1990_IDT_Logic_Data_Book 1990 IDT Logic Data Book

User Manual: 1990_IDT_Logic_Data_Book

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Integrated Device Technology, Inc.

1990·91
LOGIC DATA BOOK

2975 Stender Way, Santa Clara, California 95054
Telephone: (408) 727-6116 • TWX: 910-338-2070 • FAX: (408) 492-8674
Printed in U.S.A.
©1990 Integrated Device Technology, Inc.

GENERAL INFORMATION

•

CONTENTS OVERVIEW

Historically, Integrated Device Technology has presented our product offerings entirely under
one cover. For ease of use for our customers, we have divided the products into four separate
data books - Logic, Specialized Memory, RISC and Static RAM.
IDT's 1990 Logic Data Book is comprised of new and revised data sheets and application notes
for both the Complex Logic and Standard Logic product lines. Also included is a current, complete
packaging section for all product groups. This section will be updated in each subsequent data
book with the latest available packages.
The Logic Data Book's Table of Contents is a listing of the products contained in the 1990 Logic
Data Book, as well as those products which we believe will be in the remaining three data books,
to be published later in the year. The numbering scheme is slightly different from the past. The
number in the bottom center of the page denotes the section number and the sequence of the data
sheet within that section, (Le., 5.5 would be the fifth data sheet in the fifth section). The number
in the lower right-hand corner is the page number of that particular data sheet.
Integrated Device Technology, a recognized leader in high-speed CMOS technology, produces
a broad line of products, enabling us to provide a complete CMOS solution to designers of highperformance digital systems. Our products include industry standard devices, as well as products
with speed, lower power, package and/or architectural benefits that allow the designer to achieve
significantly improved system performance.
Use this book to find ordering Information: Start with the Ordering Information chart at the
back of each data sheet, or for the Complex LogiC product line, the Cross Reference Guide (page
1.6), then reference the Package Outline Index (page 4.2), to compose the complete IDT part
number. Reference data on our Technology Capabilities and Quality Commitments are included
in separate sections (2 and 3, respectively).
Use this book to find product data: Start with the Table of Contents, organized by product
line (page 1.3), or with the Numeric Table of Contents across all product lines (page 1.4). These
indices will direct you to the page on which the complete technical data sheet can be found. Data
sheets may be of the following type:
ADVANCE INFORMATION -contain initial descriptions, subject to change, for products that
are in development, including features and block diagrams.
PRELIMINARY - contain descriptions for products soon to be released or recently released
to production, including features, pinouts and block diagrams. Timing data are based on imulation
or initial characterization and are subject to change upon full characterization.
FINAL - contain minimum and maximum limits specified over the complete supply and temperature range for full production devices.
New products, product performance enhancements, additional package types and new product
families are being introduced frequently. Please contact your 10caiiDT sales representative to determine the latest device specifications, package types and product availability.

1.1

a

LIFE SUPPORT POLICY
.Integrated Device Technology's products are not authorized for use as critical components In life support devices
or systems unless a specific written agreement pertaining to such Intended use Is executed between the manufacturer and an officer of lOT.
1. Life support devices or systems are devices or systems which (a) are Intended for surgical Implant Into the body
or (b) support or sustain life and whose failure to perform, when properly used In accordance with Instructions for
use provided In the labeling, can be reasonably expected to result In a significant Injury to the user.
2. A critical component Is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect Its safety or effectiveness.

Note: Integrated Device Technology, Inc. reserves the right to make changes to its products or speCifications at any time, without notice,
in order to improve design or performance and to supply the best possible product. lOT does not assume any responsibility for use of any
circuitry described other than the circuitry embodied in an lOT product. The Company makes no representations that circuitry described
herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

1.1

2

1990 LOGIC DATA BOOK
SUMMARY TABLE OF CONTENTS

GENERAL INFORMATION

PAGE

Contents Overview ...................................................................................................................................................... 1.1
Summary Table of Contents ....................................................................................................................................... 1.2
Table of Contents ........................................................................................................................................................1.3
Numeric Table of Contents ......................................................................................................................................... 1.4
IDT Package Marking Description ............................................................................................................................... 1.5
Cross Reference Guide ...............................................................................................................................................1.6

TECHNOLOGY AND CAPABILITIES
IDT... Leading the CMOS Future .................................................................................................................................2.1
IDT Military and DESC·SMD Program ........................................................................................................................ 2.2
Radiation Hardened Technology .................................................................................................................................2.3
IDT Leading Edge CEMOS Technology .....................................................................................................................2.4
Surface Mount Technology .........................................................................................................................................2.5
State·of-the-Art Facilities and Capabilities .................................................................................................................. 2.6
Superior Quality and Reliability ...................................................................................................................................2.7

QUALITY AND RELIABILITY
Quality, Service and Performance ..............................................................................................................................3.1
IDT Quality Conformance Program .............................................................................................................................3.2
Radiation Tolerant/Enhanced/Hardened Products for Radiation Environments ......................................................... 3.3

PACKAGE DIAGRAM OUTLINES
Thermal Performance Calculations for IDT's Packages .............................................................................................4.1
Package Diagram Outline Index .................................................................................................................................4.2
Package Diagram Outlines .........................................................................................................................................4.3

COMPLEX LOGIC PRODUCTS
DSP and MICROSLICETM Products ............................................................................................................................~1
ReadIWrite Buffer Products ........................................................................................................................................5.8
Error Detection and Correction Products .................................................................................................................... 5.1 0
Graphics Products ...........................................................................................................................................,........... 5.14 \

STANDARD LOGIC PRODUCTS
FCT-T Products ...........................................................................................................................................................6.1
FCT Products ..............................................................................................................................................................6.26
FBT Products ..............................................................................................................................................................6.56

APPLICATION AND TECHNICAL NOTES
Complex Logic Products Technical Notes .................................................................................................................. 7.1
Complex Logic Products Application Notes ................................................................................................................ 7.3
Standard Logic Application Notes ...............................................................................................................................7.13
Standard Logic Technical Bulletins ............................................................................................................................. 7.22

lOT SALES OFFICE, REPRESENTATIVE AND DISTRIBUTOR LOCATIONS

1.2

II

SUMMARY TABLE OF CONTENTS (CONTINUED)

BOOK

SPECIALIZED MEMORY DATA BOOK
ECl Products ..............................................................................................................................................................SMP
FIFO Products .............................................................................................................................................................SMP
Specialty Memory Products ....................................................................................................................;................... SMP
Subsystems Products .................................................................................................................................................SMP

RISC DATA BOOK
RISC Components ......................................................................................................................................................RISC
RISC Subsystem Products ..... ..................................................................................................................................... RISC

STATIC RAM DATA BOOK .......................................................................................................... SRAM

1.2

2

1990 LOGIC DATA BOOK
TABLE OF CONTENTS
PAGE

GENERAL INFORMATION
Contents Overview .................................................................................................................................................... 1.1
Summary Table of Contents ..................................................................................................................................... 1.2
Table of Contents ..................................................................'...............................'..................................................... 1.3
Numeric Table of Contents ......................................................................................:............ '.................................... 1.4
lOT Package Marking Description ............................................................................................................................1.5
Cross Reference Guide ....................................................................................................;............................. ;......... 1.6

TECHNOLOGY AND CAPABILITIES
10T... Leading the CMOS Future ...............................................................................................................................2.1
lOT Military and OESC-SMO Program ........................................................................................................ ~ ............ 2.2
Radiation Hardened Technology ................................................................................'.. ;........................................... 2.3
lOT Leading Edge CEMOS Technology ................................................................................................................... 2.4
Surface Mount.Technology .......................................................................................................................................2.5
State-of-the-Art Facilities and Capabilities ................................................................................................................ 2.6
Superior Quality and Reliability ................................................................................................................................ 2.7·

QUALITY AND RELIABILITY
Quality, Service and Performance ............................................................................................................................3.1
lOT Quality Conformance Program ..........................................................................................................................3.2
Radiation ToleranUEnhanced/Hardened Products for Radiation Environments .................... ;.................................. 3.3

PACKAGE DIAGRAM OUTLINES
Thermal Performance Calculations for IDT's Packages ...........................................................................................4.1
Package Diagram Outline Index ........ ~ ...................................................................................................................... 4.2
Package Diagram Outlines ........................................... ,' ........................................................................................... 4.3

COMPLEX LOGIC PRODUCTS
DSP AND MICROSLICETM PRODUCTS
IOT39C01
4-Bit Microprocessor Slice ............................................................................................. 5.1
I OT39C 10
12-Bit Sequencer ........................................................................................................... 5.2
IOT49C402
16-Bit Microprocessor Slice ........................................................................................... 5.3
IOT49C410
16-Bit Sequencer ...........................................................................................................5.4
IOT7210L
16 x 16 Parallel Multiplier-Accumulator .......................................................................... 5.5
IOT7216L
16 x 16 Parallel Multiplier ................................................... ,.......................................... 5.6
IOT7217L
16 x 16 Parallel Multiplier (32 Bit Output) ...................................................................... 5.6
IOT7381L
16-Bit CMOS Cascadable ALU ...................................................................... :.............. 5.7
IOT7383L
16-Bit CMOS Cascadable ALU ..................................................................................... 5.7,
READ/WRITE BUFFER PRODUCTS
IOT73200L
16-Bit CMOS Multilevel Pipeline Register ........................................................ ~, ........... 5.8
IOT73201L
16-Bit CMOS Multilevel Pipeline Register ..................................................................... 5.8
IOT73210
Fast Octal Register Transceiver w/Parity ............................................................ ,......... 5.9
IOT73211
Fast Octal Register Transceiver w/Parity ................................................................. ;.... 5.9
ERROR DETECTION AND CORRECTION PRODUCTS
.
IOT39C60
16-Bit Cascadable EOC ... :........................................................................................... 5.10
32-Bit Cascadable EOC ............................................................................................... 5.11
lOT49C460
IOT49C465
32-Bit CMOS Flow-ThruEOC Unit ...........................................................................·..... 5.12
IOT49C466
64-BIT CMOS Flow-ThruEOC Unit ............................................................................... 5.13

1.3

II

1990 LOGIC DATA BOOK (CONTINUED)

PAGE

COMPLEX LOGIC PRODUCTS (CONTINUED)
GRAPHICS PRODUCTS
IDT75C457
CMOS Single 8-Bit PaletteDACTM for True Color Applications .................................... 5.14
IDT75C458
Triple 8-Bit PaletteDACTM ............................................................................................. 5.15
IDT75C48
8-Bit Flash ADC ............................................................................................................ 5.16
IDT75C58
8-Bit Flash ADC with Overflow Output ......................................................................... 5.17

STANDARD LOGIC PRODUCTS
IDT29FCT52T
IDT29FCT53T
IDT29FCT520T
IDT29FCT521T
I DT54/74FCT138T
IDT54/74FCT139T
IDT54/74FCT151T
IDT54/74FCT251T
I DT54/74FCT157T
I DT54/74FCT257T
IDT54/74FCT161 T
IDT54/74FCT163T
IDT54/74FCT191T
I DT54/74FCT193T
IDT54/74FCT240T
IDT54/74FCT241T
I DT54/74FCT244T
I DT54/74FCT540T
IDT54/74FCT541T
IDT54/74FCT245T
I DT54/74FCT640T
I DT54/74FCT645T
IDT54/74FCT273T
IDT54/74FCT299T
I DT54/74FCT373T
IDT54/74FCT533T
IDT54/74FCT573T
IDT54/74FCT374T
I DT54/74FCT534T
IDT54/74FCT574T
IDT54/74FCT377T
IDT54/74FCT399T
IDT54/74FCT521T
I DT54/74FCT543T
I DT54/74FCT646T
I DT54/74FCT648T
I DT54/74FCT651 T
IDT54/74FCT652T
IDT54/74FCT620T
IDT54/74FCT623T
IDT54/74FCT621 T
IDT54/74FCT622T
IDT54/74FCT821 T
IDT54/74FCT823T
IDT54/74FCT825T
I DT54/74FCT827T
IDT54/74FCT828T

Non-inverting Octal Registered Transceiver ................................................................. 6.1
Inverting Octal Registered Transceiver ......................................................................... 6.1
Multi-level Pipeline Register .......................................................................................... 6.2
Multi-level Pipeline Register .................................................................... ;..................... 6.2
1-of-8 Decoder ............................................................................................................... 6.3
DuaI1-of-4 Decoder ...................................................................................................... 6.4
8-lnput Multiplexer ......................................................................................................... 6.5
8-1 nput Multiplexer w/3-State ......................................................................................... 6.5
Quad 2-lnput Multiplexer ............................................................................................... 6.6
FQuad 2-lnput Multiplexer w/3-State ............................................................................. 6.6
Synchronous Binary Counter w/Asynchronous Master Reset ....................................... 6.7
Synchronous Binary Counter w/Synchronous Reset ..................................................... 6.7
Up/Down Binary Counter w/Preset and Ripple Clock .................................................... 6.8
Up/Down Binary Counter w/Separate Up/Down Clocks ................................................ 6.9
Inverting Octal Buffer/Line Driver ................................................................................. 6.1 0
Non-inverting Octal Buffer/Line Driver .......................................................................... 6.10
Non-inverting Octal Buffer/Line Driver .......................................................................... 6.10
Inverting Octal Buffer/Line Driver '" .............................................................................. 6.10
Non-inverting Octal Buffer/Line Driver .......................................................................... 6.10
Non-inverting Octal Transceiver ................................................................................... 6.11
Inverting Octal Transceiver .......................................................................................... 6.11
Non-inverting Octal Transceiver ................................................................................... 6.11
Octal D Flip-Flop w/Common Master Reset ................................................................. 6.12
8 Input Universal Shift Register w/Common Parallel I/O Pins ...................................... 6.13
Non-inverting Octal Transparent Latch w/3-State ........................................................ 6.14
Inverting Octal Transparent Latch w/3-State ................................................................ 6.14
Non-inverting Octal Transparent Latch w/3-State ........................................................ 6.14
Non-inverting Octal D Register ..................................................................................... 6.15
Inverting Octal D Register ............................................................................................ 6.15
Non-inverting Octal D Register ..................................................................................... 6.15
Octal D Flip-Flop w/Clock Enable ................................................................................. 6.16
Quad Dual-Port Register .............................................................................................. 6.17
8-Bit Identity Comparator ............................................................................................. 6.18
Non-inverting Octal Latched Transceiver ..................................................................... 6.19
Non-inverting Octal Registered Transceiver ................................................................ 6.20
Inverting Octal Registered Transceiver ........................................................................ 6.20
Inverting Octal Registered Transceiver ........................................................................ 6.20
Non-inverting Octal Registered Transceiver ................................................................ 6.20
Inverting Octal Bus Transceiver w/3-State ................................................................... 6.21
Non-inverting Octal Bus Transceiver w/3-State ............................................................ 6.21
Non-inverting Octal Bus Transceiver (Open Drain) ...................................................... 6.22
Inverting Octal Bus Transceiver (Open Drain) ............................................................ 6.22
10-Bit Non-inverting Register w/3-State ....................................................................... 6.23
9-Bit Non-inverting Register w/Clear & 3-State ............................................................ 6.23
8-Bit Non-inverting Register w/Clear & 3-State ............................................................ 6.23
1O-Bit Non-inverting Buffer ........................................................................................... 6.24
10-Bit Inverting Buffer ................................................................................................... 6.24

1.3

2

1990 LOGIC DATA BOOK (CONTINUED)

PAGE

STANDARD LOGIC PRODUCTS (CONTINUED)
IDT54/74FCT841T
IDT54/74FCT843T
I DT54/74 FCT845T

10-Bit Non-inverting Latch ............................................................................................ 6.25
9-Bit Non-inverting Latch .............................................................................................. 6.25
8-Bit Non-inverting Latch .............................................................................................. 6.25

IDT29FCT52
IDT29FCT53
IDT29FCT520
IDT49FCT661
I DT49 FCT804
IDT49FCT805
IDT49FCT806
IDT49FCT818
IDT49C25
IDT39C8XX
I DT54/74FCT138
I DT54/74FCT139
IDT54/74FCT161
IDT54/74FCT163
IDT54/74FCT182
I DT54/74FCT191
I DT54/74FCT193
I DT54/74FCT240
IDT54/74 FCT241
IDT54/74FCT244
I DT54/74FCT540
IDT54/74FCT541
IDT54/74 FCT245
IDT54/74FCT640
I DT54/74FCT645
I DT54/74FCT273
IDT54/74FCT299
I DT54/74FCT373
I DT54/74FCT533
I DT54/74FCT573
IDT54/74FCT374
IDT54/74FCT534
IDT54/74FCT574
IDT54/74FCT377
I DT54/74FCT399
I DT54/74FCT521
IDT54/74FCT543
IDT54/74FCT646
I DT54/74FCT821
IDT54/74FCT823
IDT54/74FCT824
IDT54/74FCT825
IDT54/74FCT827
IDT54/74FCT833
IDT54/74FCT841
I DT54/74FCT843
I DT54/74FCT844
IDT54/74FCT845
IDT54/74FCT861

Non-inverting Octal Registered Transceiver ................................................................ 6.26
Inverting Octal Registered Transceiver ........................................................................ 6.26
MUlti-level Pipeline Register ......................................................................................... 6.27
16-Bit Synchronous Binary Counter ............................................................................. 6.28
High-Speed Tri-Port Bus Multiplexer ............................................................................ 6.29
Buffer/Clock Driver w/Guaranteed Skew ...................................................................... 6.30
Buffer/Clock Driver w/Guaranteed Skew ...................................................................... 6.30
Octal Register with SPCTM ........................................................................................... 6.31
Microcycle Length Controller ........................................................................................ 6.32
IDT39C8XXX Family .................................................................................................... 6.33
1-of-8 Decoder ............................................................................................................. 6.34
DuaI1-of-4 Decoder ..................................................................................................... 6.35
Synchronous Binary Counter w/Asynchronous Master Reset ...................................... 6.36
Synchronous Binary Counter w/Synchronous Reset.. .................................................. 6.36
Carry Lookahead Generator ......................................................................................... 6.37
Up/Down Binary Counter w/Preset and Ripple Clocks ................................................. 6.38
Up/Down Binary Counter w/Separate Up/Down Clocks ............................................... 6.39
Inverting Octal Buffer/Line Driver ................................................................................. 6.40
Non-inverting Octal Buffer/Line Driver .......................................................................... 6.40
Non-inverting Octal Buffer/Line Driver .......................................................................... 6.40
Inverting Octal Buffer/Line Driver ................................................................................. 6.40
Non-inverting Octal Buffer/Line Driver .......................................................................... 6.40
Non-inverting Octal Transceiver ................................................................................... 6.41
Inverting Octal Transceiver .......................................................................................... 6.41
Non-inverting Octal Transceiver ................................................................................... 6.41
Octal D Flip-Flop w/Comrnon Master Reset ................................................................ 6.42
8-lnput Universal Shift Register w/Common Parallel I/O Pins ...................................... 6.43
Non-inverting Octal Transparent Latch ........................................................................ 6.44
Inverting Octal Transparent Latch ................................................................................ 6.44
Non-inverting Octal Transparent Latch ........................................................................ 6.44
Non-inverting Octal D Flip-Flop .................................................................................... 6.45
Inverting Octal D Flip-Flop w/3-State ............................................................................ 6.45
Non-inverting Octal D Register w/3-State ..................................................................... 6.45
Octal D Flip-Flop w/Clock Enable ................................................................................. 6.46
Quad Dual-Port Register .............................................................................................. 6.47
8-Bit Identity Comparator ............................................................................................. 6.48
Non-inverting Octal Latched Transceiver ..................................................................... 6.49
Non-inverting Octal Registered Transceiver ................................................................ 6.50
10-Bit Non-inverting Registerw/3-State ....................................................................... 6.51
9-Bit Non-inverting Register w/Clear & 3-State ............................................................ 6.51
9-Bit Inverting Register w/Clear & 3-State .................................................................... 6.51
8-Bit Non-inverting Register ......................................................................................... 6.51
10-Bit Non-inverting Buffer ........................................................................................... 6.52
8-Bit Transceiver w/Parity ............................................................................................ 6.53
10-Bit Non-inverting Latch ............................................................................................ 6.54
9-Bit Non-inverting Latch .............................................................................................. 6.54
9-Bit Inverting Latch ...................................................................................................... 6.54
8-Bit Non-inverting Latch .............................................................................................. 6.54
10-Bit Non-inverting Transceiver .................................................................................. 6.55

1.3

II

3

1990 LOGIC DATA BOOK (CONTINUED)

PAGE

STANDARD LOGIC PRODUCTS (CONTINUED)
IDT54/74FCT863
9-Bit Non-inverting Transceiver .................................................................................... 6.55
IDT54/74FCT864
9-Bit Inverting Transceiver ........................................................................................... 6.55
I DT54/74FBT240
IDT54/74FBT241
I DT54/74FBT244
I DT54/74FBT245
IDT54/74FBT373
I DT54/74FBT374
I DT54/74FBT540
I DT54/74FBT541
IDT54/74FBT821
I DT54/74FBT823
I DT54/74FBT827
IDT54/74FBT828
IDT54/74FBT841 .
I DT54/74FBT2240
I DT54/74FBT2244
IDT54/74FBT2373
I DT54/74FBT2827
IDT54/74FBT2828
IDT54/74FBT2841

Inverting Octal Buffer/Line Driver ................................................................................. 6.56
Non-inverting Octal Buffer/Line Driver .......................................................................... 6.57
Non-inverting Octal Buffer/Line Driver .......................................................................... 6.58
Non-inverting Octal Transceiver ................................................................................... 6.59
Octal Transparent Latch w/3-State ............................................................................... 6.60
Non-inverting Octal 0 Register ..................................... :............................................... 6.61
Inverting Octal Buffer .................................................................................................... 6.62
Non-inverting Octal Buffer ............................................................................................ 6.62
10-Bit Non-inverting Register ....................................................................................... 6.63
9-Bit Inverting Register ................................. ;............................................................... 6.64
Non-inverting 10-Bit Buffers/Driver ............................................................................... 6.65
Inverting10-Bit Buffers/Driver ....................................................................................... 6.65
10-Bit No n-inverting Latch ............................................................................................ 6.66
Inverting Octal Buffer/Line Driver w/25Q Series Resistor ............................................. 6.67
Inverting Octal Buffer/Line Driver w/25Q Series Resistor ............................................. 6.68
Octal Transparent Latch w/3-State & 25Q Series Resistor .......................................... 6.69
Non-inverting 10-Bit Buffers/Driver w/25Q Series Resistor .......................................... 6.70
Inverting1 O-Bit Buffers/Driver w/25Q Series Resistor ................................................... 6.70
10-Bit Memory Latch w/25Q Series Resistor ................................................................ 6.71

APPLICATION AND TECHNICAL NOTES
Complex Logic Products Technical Notes
TN-02
Build a 20MIP Data Processing Unit ............................................................................. 7.1
TN-03
Using the IDT49C402A ALU .......................................................................................... 7.2
Complex Logic Products Application Notes
AN-03
Trust Your Data with A High-Speed CMOS 6-, 32- or 64-Bit EDC ............................... 7.3
AN-06
16-Bit CMOS Slices - New Building Blocks Maintain Microcode Compatibility
Yet Increase Performance .................................................................................... 7.4
AN-17
FIR Filter Implementation Using FIFOs and MACs ....................................................... 7.5
AN-24
DeSigning with the IDT49C460 and IDT39C60 Error Detection and
Correction Units ..................................................................................................... 7.6
AN-32
Implementation of Digital Filters Using IDT7320, IDT7210, IDT7216 ........................... 7.7
AN-35
Address Generator in Matrix Unit Operation Engine ..................................................... 7.8
AN-37
Designing High-Performance Systems Using the lOT PaletteDACTM ........................... 7.9
AN-63
Using the IDT75C457's PaletteDACTM in True Color and Monochrome Graphics
Applications ........................................................................................................ 7.10
Protecting Your Data with lOT's 49C465 32-Bit Flow-thruEDCTM Unit ......................... 7.11
AN-64
AN-65
Using IDT73200 or IDT7321 0 as Read and Write Buffers with R3000 ........................ 7.12
Standard Log ic Application Notes •................•.....•............................................................................................... 7.13
AN-47
Simultaneous Switching Noise ..................................................................................... 7.14
AN-48
Using High-Speed Logic ............................................................................................... 7.15
AN-49
Characteristics of PCB Traces ..................................................................................... 7.16
AN-50
Series Termination ....................................................................................................... 7.17
AN-51
Power Dissipation in Clock Drivers ........................................... ;................................... 7.18
FCT Output Structures and Characteristics ................................................................. 7.19
AN-52
Power-Down Operation ................................................................................................ 7.20
AN-53
AN-54
FCT-T Logic Family ...................................................................................................... 7.21
Standard Logic Technical Bulletins .....................................................................................................................7.22

lOT SALES OFFICE, REPRESENTATIVE AND DISTRIBUTOR LOCATIONS

1.3

4

SPECIALIZED MEMORY DATA BOOK

•

The following Is a list of data sheets expected to be Included In the Specla"zed Memory Data Book due for
pub"catlon 4090. Until Its release, please refer to your 1989 Data Book Supplement.

ECl PRODUCTS
IDT10484
IDT100484
IDT101484
IDT10490
IDT100490
IDT101490
IDT10494
IDT100494
IDT101494
IDT10496ll
IDT100496ll
IDT101496ll
IDT10496Rl
IDT100496Rl
IDT101496Rl
IDT10497
IDT100497
IDT101497
IDT10498
IDT100498
IDT101498
IDT10504
IDT100504
IDT101504
IDT10506ll
IDT100506ll
IDT101506ll
IDT10506RlA
IDT100506RlA
IDT101506RlA
IDT10507
IDT100507
IDT101507
IDT10508
IDT100508
IDT101508
IDT10509
IDT100509
IDT101509

4K x 4 ECl 10K SRAM
4K x 4 ECl 100K SRAM
4K x 4 ECl 101K SRAM
64K x 1 ECl 10K SRAM
64K x 1 ECl 1OOK SRAM
64K x 1 ECl 101K SRAM
16K x 4 ECl 10K SRAM
16K x 4 ECl 100K SRAM
16K x 4 ECl 101K SRAM
16K x 4 Self-Timed latch Input, latch Output
16K x 4 Self-Timed latch Input, latch Output
16K x 4 Self-Timed latch Input, latch Output
16K x 4 Self-Timed Reg Input, latch Output
16K x 4 Self-Timed Reg Input, latch Output
16K x 4 Self-Timed Reg Input, latch Output
16K x 4 Synchronous Write, latch Output
16K x 4 Synchronous Write, latch Output
16K x 4 Synchronous Write, latch Output
16K x 4 Conditional Write, latch Output
16K x 4 Conditional Write, latch Output
16K x 4 Conditional Write, latch Output
64K x 4 ECl 10K SRAM
64K x 4 ECl 1OOK SRAM
64K x 4 ECl 100K SRAM
64K x 4 Self-Timed latch Input, latch Output
64K x 4 Self-Timed latch Input, latch Output
64K x 4 Self-Timed latch Input, latch Output
64K x 4 Self-Timed Reg Input, latch Output
64K x 4 Self-Timed Reg Input, latch Output
64K x 4 Self-Timed Reg Input, latch Output
64K x 4 Synchronous Write, latch Output
16K x 4 Synchronous Write, latch Output
16K x 4 Synchronous Write, latch Output
64K x 4 Conditional Write, latch Output
64K x 4 Conditional Write, latch Output
64K x 4 Conditional Write, latch Output
32K x 9 ECl 10K SRAM
32K x 9 ECl 1OOK SRAM
32K x 9 ECl 101K SRAM

FIFO PRODUCTS
IDT7200
IDT7201
IDT7202
IDT7203
IDT7204
IDT7205
IDT7206
IDT72021
IDT72031

256 x 9-Sit Parallel FIFO
512 x 9-Sit Parallel FIFO
1024 x 9-Sit Parallel FIFO
2K x 9-Sit Parallel FIFO
4K x 9-Sit Parallel FIFO
8K x 9-Sit Parallel FIFO
16K x 9-Sit Parallel FI FO
1K x 9-Sit Parallel FIFO wI Flags and OE
2K x 9-Sit Parallel FIFO wlFlags and OE

1.3

5

SPECIALIZED MEMORY DATA BOOK (CONTINUED)
FIFO PRODUCTS (CONTINUED)
10T72041
4K x 9-Bit Parallel FIFO w/Flags and OE
10T72103
2K x 9-Bit Configurable Parallel-Serial FIFO
4K x 9-Bit Configurable Parallel-Serial FIFO
10T72104
256 x 16-Bit Parallel-to-Serial FIFO
10T72105
512 x 16-Bit Parallel-to-Serial FIFO
10T72115
1024 x 16-Bit Parallel-to-Serial FI FO
10T72125
IOT72131
2048 x 9-Bit Parallel-to-Serial FIFO
10T72141
4096 x 9-Bit Parallel-to-Serial FIFO
2048 x 9-Bit Serial-to-Parallel FIFO
IOT72132
2048 x 9-Bit Serial-to-Parallel FIFO
10T72142
256 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO)
10T72200
10T72210
512 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO)
IOT72420
64 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO)
IOT72201
256 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO)
IOT72211
512 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO)
IOT72421
64 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO)
IOT72215A
512 x 18-Bit Parallel SyncFIFOTM (Clocked FIFO)
10T72225A
1024 x 18-Bit Parallel SyncFIFOTM (Clocked FIFO)
IOT72220
1K x 8-Bit Parallel SyncFIFOTM (Clocked FIFO)
2K x 8-Bit Parallel SyncFIFOTM (Clocked FIFO)
10T72230
IOT72240
4K x 8-Bit Parallel SyncFIFOTM (Clocked FIFO)
IOT72221
1K x 9-Bit Parallel SyncFIFOTM (Clocked FIFO)
IOT72231
2K x 9-Bit Parallel SyncFIFOTM (Clocked FIFO)
IOT72241
4K x 9-Bit Parallel SyncFIFOTM (Clocked FIFO)
IOT72235
2K x 18-Bit Parallel SyncFIFOTM (Clocked FIFO)
IOT72245
4K x 18-Bit Parallel SyncFIFOTM (Clocked FIFO)
IOT72401
64 x 4 FIFO
64 x 5 FIFO
IOT72402
64 x 4 FIFO w/OE
IOT72403
IOT72404
64 x 5 FIFO w/OE
IOT72413
64 x 5 FIFO (w/Flags)
10T7251
512 x 18-Bit -1 K x 9-Bit BiFIFO
1K x 18-Bit - 2K x 9-Bit BiFIFO
IOT7252
512 x 18-Bit -1K x 9-Bit BiFIFO
IOT72510
1K x 18-Bit - 2K x 9-Bit BiFI FO
IOT72520
IOT72511
512 x 18-Bit BiFIFO
IOT72521
1K x 18-Bit BiFIFO
256 x 18-Bit Synchronous BiFIFO (SyncBiFIFOTM)
IOT72605
IOT72615
512 x 18-Bit Synchronous BiFIFO (SyncBiFIFOTM)

SPECIALTY MEMORY PRODUCTS
IOT7130
IOT7140
10T7030
IOT7040
IOT7010
IOT70104
10T70101
IOT70105
IOT7132
IDT7142
IDT7032
IDT7042
IDT71321

8K (1 K x 8) Dual-Port RAM (MASTER)
8K (1 K x 8) Dual-Port RAM (SLAVE)
8K (1 K x 8) Dual-Port RAM (MASTER)
8K (1 K x 8) Dual-Port RAM (SLAVE)
9K (1 K x 9) Dual-Port RAM (MASTER)
9K (1 K x 9) Dual-Port RAM (SLAVE)
9K (1 K x 9) Dual-Port RAM (MASTER w/lnterrupts)
9K (1 K x 9) Oual-Port RAM (SLAVE w/lnterrupts)
16K (2K x 8) Oual-Port RAM (MASTER)
16K (2K x 8) Dual-Port RAM (SLAVE)
16K (2K x 8) Dual-Port RAM (MASTER)
16K (2K x 8) Dual-Port RAM (SLAVE)
16K (2K x 8) Dual-Port RAM (MASTER w/lnterrupts)

1.3

6

SPECIALIZED MEMORY DATA BOOK (CONTINUED)
SPECIALTV MEMORY PRODUCTS (CONTINUED)
16K (2K x 8) Dual-Port RAM (SLAVE w/lnterrupts)
IDT71421
16K (2K x 8) Dual-Port RAM (w/Semaphores)
IDT71322
18K (2K x 9) Dual-Port RAM
IDT7012
18K (2K x 9) Dual-Port RAM (MASTER w/lnterrupts)
IDT70121
IDT70125
18K (2K x 9) Dual-Port RAM (SLAVE w/lnterrupts)
32K (2K x 16) Dual-Port RAM (MASTER)
IDT7133
32K (2K x 16) Dual-Port RAM (SLAVE)
IDT7143
IDT7134
32K (4K x 8) Dual-Port RAM
IDT71342
32K (4K x 8) Dual-Port RAM (w/Semaphores)
IDT7014
32K (4K x 9) Dual-Port RAM
IDT7024
64K (4K x 16 Dual-Port RAM
64K (8K x 8) Dual-Port RAM
IDT7005
128K (8K x 16) Dual-Port RAM
IDT7025
128K (16K x 8) Dual-Port RAM
IDT7006
IDT7044
144K (4K x 36) Dual-Port RAM
IDT7050
8K (1 K x 8) FourPort™ RAM
IDT7052
16K (2K x 8) FourPort™ RAM

II

SUBSYSTEMS PRODUCTS
MULTI-PORT MODULES
IDT7M134
8K x 8 Master Dual-Port SRAM Module
IDT7M144
8K x 8 Slave Dual-Port SRAM Module
IDT7M135
16K x 8 Master Dual-Port SRAM Module
IDT7M145
16K x 8 Slave Dual-Port SRAM Module
IDT7M137
32K x 8 Master Dual-Port SRAM Module
IDT7M1003
64K x 8 Dual-Port SRAM Module
IDT7M1001
128K x 8 Dual-Port SRAM Module
IDT7M1004
8K x 8 Dual-Port SRAM Module
IDT7M1005
16K x 9 Dual-Port SRAM Module
IDT7MB6056
32K x 16 Dual-Port (Shared Memory) SRAM Module
IDT7MB1008
32K x 16 Dual-Port SRAM Module
IDT7MB1006
64K x 16 Dual-Port SRAM Module
IDT7MB6046
64K x 16 Dual-Port (Shared Memory) SRAM Module
IDT7MB6036
128K x 16 Dual-Port (Shared Memory) SRAM Module
IDT7MB6156
32K x 18 Dual-Port (Shared Memory) SRAM Module
IDT7MB6146
64K x 18 Dual-Port (Shared Memory) SRAM Module
IDT7MB6136
128K x 18 Dual-Port (Shared Memory) SRAM Module
IDT7M1002
16K x 32 Dual-Port SRAM Module
IDT7M1041
8K x 8 FourPort™ SRAM Module
IDT7M1042
4K x 8 FourPort™ SRAM Module
IDT7M1043
4K x 16 FourPort™ SRAM Module
IDT7M1044
2K x 16 FourPort™ SRAM Module
FIFO MODULES
IDT7M205
IDT7MP2005
IDT7M206
IDT7MP2011
IDT7M207
IDT7MP2010
IDT7MP2009

8K x 9-Bit CMOS FIFO Module
8K x 9-Bit FIFO Module
16K x 9-Bit CMOS FIFO Module
16K x 9 Bit FIFO Module
32K x 9-Bit CMOS FIFO Module
16K x 18-Bit FIFO Module
32K x 18-Bit FIFO Module

1.3

7

SPECIALIZED MEMORY DATA BOOK (CONTINUED)
SRAM MODULES
IDT7MC4001
IDT7M4042
IDT7M812
IDT8M824
IDT8MP824
IDT7MP4034
IDT7M4048
I DT7MP4008
IDT7M912
IDT7MC4005
IDT7MB4009
IDT8M612
IDT8MP612
IDT7M624
IDT8M624
IDT8MP624
IDT7M4016
IDT7MP4047
IDT7MC4032
IDT7MP4031
IDT7M4003
IDT7M4017
IDT7MP4036
IDT7MP4045

1M x 1 CMOS Static RAM Module
256K x 4 CMOS Static RAM Module
64K x 8 CMOS Static RAM Module
128K x 8 CMOS Static RAM Module
128K x 8 CMOS Static RAM Module
256K x 8 CMOS Static RAM Module
512K x 8 CMOS Static RAM Module
512K x 8 CMOS Static RAM Module
64K x 9 CMOS Static RAM Module
16K x 16 CMOS Static RAM Module
2(16K x 16) CMOS Static RAM Module·
32K x 16 CMOS Static RAM Module
32K x 16 CMOS Static RAM Module
64K x 16 CMOS Static RAM Module
64K x 16 CMOS Static RAM Module
64K x 16 CMOS Static RAM Module
256K x 16 CMOS Static RAM Module
512K x 16 CMOS Static RAM Module'
16K x 32 CMOS Static RAM Module w/Separate Data I/O
16K x 32 CMOS Static RAM Module
32K x 32 CMOS Static RAM Module
64K x 32 CMOS Static RAM Module .
64K x 32 CMOS Static RAM Module
256K x 32 CMOS Static RAM Module .

CACHE MODULES
IDT7MB6064
IDT7MB6044
IDT7MB6043
IDT7MB6051
IDT7MB6039
IDT7MB6049
IDT7MB6040
IDT7MB6061

Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual

(4K x 60) Data/Instruction Cache Module for IDT79R3000 CPU
(4K x 64) Data/Instruction Cache Module for IDT79R3000 CPU
(8K x 64) Data/Instruction Cache Module for IDT79R3000 CPU
(8K x 64) Data/Instruction Cache Module for IDT79R3000 CPU (Multiprocessor)
(16K x 60) Data/lnstruction'Cache Module for IDT79R3000 CPU
(16K x 60) Data/Instruction Cache Module for IDT79R3000 CPU (Multiprocessor)
(16K x 64) Data/Instruction Cache Module for General CPUs
(16K x 60) Data/Instruction w/Resettable InstructionTag

WRITABLE CONTROL STORE MODULES
IDT7M6032
16K x 32 Writable Control Store Static RAM Module
8K x 112 Writable Control Store Static RAM Module
IDT7MB6042
Flexi-Pak Module Family Various Combinations of Four SRAMs, EPROMs and EEPROMs Packaged in 32Lead JEDEC LCCs Mounted on PGA-Type Substrate

1.3

8

Rise DATA BOOK
The following Is a list of data sheets expected to be Included In the RiSe Data Book due for publication 4090.
Until Its release, please refer to your 1980 Data Book Supplement.

RISC MICROPROCESSOR PRODUCTS
RISC COMPONENTS
IDT79R3000
IDT79R3001
IDT79R3010
IDT79R3020
IDT79R4000

RIse CPU Processor
32-Bit RISController™
RISC Floating-Point Accelerator
RISC CPU Write Buffer
Third Generation RISC Processor

Rise DEVELOPMENT SYSTEMS
RS1210
RISComputer™ Development System
RC2030
RISComputer™ Development System
RC3240
RISComputer™ Development System
RC3260
RISComputer™ Development System
M/2000 RISComputer™ Development System
Rise DEVELOPMENT SOFTWARE
3106 Ada
Ada Compiler
3120C-SRC (SPP)
System Programmer's Package
3123C-SRC (SPP/e)
System Programmer's Package/e
Ada Stand-alone Programmer's Package
3178C-SRC (ASAPP)

RISC SUBSYSTEM PRODUCTS
Rise epu MODULES
IDT7RS101
IDT7RS101F
IDT7RS102
IDT7RS102F
IDT7RS103
IDT7RS103F
IDT7RS104
IDT7RS104F
IDT7RS105
IDT7RS105F
IDT7RS107F

Rise TargetSystems
IDT7RS301
IDT7RS302
IDT7RS303
IDT7RS304
IDT7RS305
IDT7RS307

R3000 Module w/64K I-Cache, 64K D-Cache,
4 Word Read Buffer and 1 Word Write Buffer
R3000, R3010 Module w/64K I-Cache, 64K D-Cache,
4 Word Read Buffer and 1 Word Write Buffer
R3000 Module w/16K I-Cache, 16K D-Cache,
1 Word Read Buffer and 1 Word Write Buffer
R3000, R3010 Module w/16K I-Cache, 16K D-Cache,
1 Word Read Buffer and 1 Word Write Buffer
R3000 Module w/16K I-Cache and 16K D-Cache
R3000, R3010 Module w/16K I-Cache and16K D-Cache
R3001 Module wI 128K I-Cache, 128K D-Cache,
1 Word Read Buffer and 1 Word Write Buffer
R3001, R3010 Modulew/128K I-Cache,128K D-Cache,
1 Word Read Buffer and 1 Word Write Buffer
R3000 Module w/32K I-Cache, 16K D-Cache,
1 Word Read Buffer, 1 Word Write Buffer and IDT Bus
R3000, R3010 Module w/32K I-Cache, 16K D-Cache,
1 Word Read Buffer, 1 Word Write Buffer and IDT Bus
R3000, R3010 Module w/64K I-Cache, 64K D-Cache,
OR3020 and 1 Word Read Buffer

TargetSystem™
TargetSystem™
TargetSystem™
TargetSystem™
TargetSystem™
TargetSystem™

for
for
for
for
for
for

IDT7RS1 01
IDT7RS102
IDT7RS103
IDT7RS1 04
IDT7RS1 05
IDT7RS1 07

1.3

9

II

RISC DATA BOOK (CONTINUED)
RISC SUBSYSTEM PRODUCTS (CONTINUED)
SUPPORT PRODUCTS
IDT7RS201
Nubus Board
IDT7RS202
Nubus Board, Supports Nubus Memory
IDT7RS203
Nubus Board, Supports Onboard Memory
IDT7RS340
System Board
IDT7RS341
Personality Board for IDT7RS101
IDT7RS342
Personality Board for IDT7RS102
IDT7RS343
Personality Board for IDT7RS1 03
Personality Board for IDT7RS1 07
IDT7RS347
I DT7RS353-B
JMI C-Executive™ Binary Code
IDT7RS353-MB
JMI C-Executive™ Maintenance for Binary Code
IDT7RS353-S
JM I C-Executive™ SourceCode
I DT7RS353-MS
JMI C-Executive™ Maintenance for Source Code
IDT7RS355-B
Floating Point Library Binary Code
IDT7RS355-MB
Floating Point Library Maintenance for Binary Code
Floating Point Library Source Code
IDT7RS355-S
IDT7RS355-MS
Floating Point Library Maintenance for Source Code
IDT7RS356-2B
R3000 C-Compiler Binary Code for 80286,80386 IDT7RS356-2MB R3000
C-CompiJer Maintenance for Binary Code for 80286, 80386 PC-DOS
I DT7RS356-3B
R3000 C-CompiJer Binary Code for PC SCO XENIX
I DT7RS356-3MB
R3000 C-CompiJer Maintenance for Binary Code SCO XENIX
I DT7RS357 -1 B
R3000 Macro Assembler Binary Code for 8086, 8088 PC-DOS
I DT7RS357 -1 MB
R3000 Macro Assembler Maintenance for Binary Code 8086, 8088
I DT7RS357 -2B
R3000 Macro Assembler Binary Code for 80286, 80386 PC-DOS
IDT7RS357-2MB
R3000 Macro Assembler Maintenance for Binary Code 80286, 80386
IDT7RS357-3B
R3000 Macro Assembler Binary Code for PC SCO XENIX
IDT7RS357-3MB
R3000 Macro Assembler Maintenance for Binary Code SCO XENIX
IDT7RS361-B
IDT PROM Monitor Binary Code
IDT PROM Monitor Maintenance for Binary Code
IDT7RS361-MB
IDT7RS361-E
IDT PROM Monitor Binary Code - in 4 EPROMs
IDT PROM Monitor Source Code
IDT7RS361-S
I DT7RS361-MS
IDT PROM Monitor Maintenance for Source Code
I DT7RS363-1
R3000 PGA Breakout Board and HP 16500A Logic Analyzer Set-up Software
I DT7RS363-2
R3000 PGA Breakout Board and HP 16500A Logic Analyzer Set-up Software
and 5 HP Adapters
IDT7RS364
HP 16500A Logic Analyzer Disassembler Software for 7RS300 Series
TargetSystems™
IDT7RS365
R3000 Flatpack Version
IDT7RS366
R3001 PGA Version
IDT7RS382
R3000 Evaluation Board
IDT7RS383
R3001 Evaluation Board
MacStation™ DEVELOPMENT SYSTEM
MacStation™ Development System w/lDT7RS201 Nubus Board, IDT/ux and C-CompiJer
IDT7RS501-1
IDT7RS501-1 D
MacStation™ Development System Documentation
IDT7RS501-1 M
MacStation™ Development System Maintenance
IDT7RS501-2
MacStation™ Development System w/150MB External Hard Disk, 40MB External
Tape Drive, IDT7RS201 Nubus Board, IDT/ux and C-Compiler
Complete IDT7RS501 MacStation™ Development System w/MAC II Computer, 8MB
IDT7RS501-3
RAM, 150MB Hard Disk, 40MB External Tape Drive, IDT7RS201 Nubus
Board, IDT/ux and C-Compiler
I DT7RS501-4
4MB SIMM Module for MAC II
IDT7RS501 MacStation™ Development System w/150MB External Hard Disk,IDT7RS201
I DT7RS501-5
Nubus Board, IDT/ux and C-CompiJer

1.3

10

RISC DATA BOOK (CONTINUED)
RISC SUBSYSTEM PRODUCTS (CONTINUED)
MacStatlon™ DEVELOPMENT SYSTEM (CONTINUED)
IDT7RS501-6
IDT7RS501 MacStation™ Development System w/40MB External Tape Drive,
IDT7RS201 Nubus Board, IDT/ux and C-Compiler
IDT7RS502-1
MacStation™ Development System w/lDT7RS202 Nubus Board, 8MB Nubus RAM
Board, IDT/ux and C-Compiler
IDT7RS502-1 D
MacStation™ Development System Documentation
IDT7RS502-1 M
MacStation™ Development System Maintenance
IDT7RS502-2
IDT7RS502 MacStation™ Development System w/150MB External Hard Disk, 40MB
External Tape Drive, IDT7RS202 Nubus Board, IDT/ux and C-Compiler
IDT7RS502-3
Complete IDT7RS502 MacStation™ Development System w/MAC II Computer, 8MB
RAM, 150MB Hard Disk, 40MB External Tape Drive, IDT7RS202 Nubus
Board, IDT/ux and C-Compiler
IDT7RS502-4
4MB SIMM Module for MAC II
I DT7RS502-5
IDT7RS502 MacStation™ Development System w/150MB External Hard Disk,
IDT7RS202 Nubus Board, IDT/ux and C-Compiler
I DT7RS502-6
IDT7RS502 MacStation™ Development System w/40MB External Tape Drive,
IDT7RS202 Nubus Board, IDT/ux and C-Compiler
IDT7RS503-1
MacStation™ Development System w/16MB RAM, IDT/ux and C-Compiler
IDT7RS503-1 D
MacStation™ Development System Documentation
IDT7RS503-1 M
MacStation™ Development System Maintenance
IDT7RS551-1 B
IDT/ux - UNIX Operating System for MacStations™
I DT7RS571-1 S
MIPS SPP for the MAC
I DT7RS572-1 S
MIPS SPP/e forthe MAC
IDT7RS573-1 B
MIPS Fortran for the MAC
IDT7RS573-1 MB
Maintenance for MIPS Fortran for the MAC

1.3

I

11

STATIC RAM DATA BOOK
The following is a list of data sheets expected to be Included In the Static RAM Data Book due for publication
1Q91. Until its release, please referto your 1980 Data Book Supplement.

STATIC RAM PRODUCTS
IDT6167
IDT6168
IDT6177
IDT6178
IDT61970
IDT71681.
IDT71682
IDT6116
IDT7187
IDT6198
IDT7188
IDT7198
IDT61B98
IDT71981
IDT71982
IDT71B88
IDT71B98
IDT7164
IDT7165
IDT7174
IDT71B64
IDT71B65
IDT71B74
IDT7186
IDT71586
IDT7169
IDT71569
IDT71B569
IDT71B69
IDT71B79
IDT71220
IDT71222
IDT71270
IDT71257
IDT61298
IDT71258
IDT61B298
IDT71281
IDT71282
IDT71B258
IDT71256
IDT71B256
IDT71B556
IDT71259
IDT71509
IDT71559
IDT71589
IDT71027
IDT71028
IDT71024

16K x 1 w/Power-Down
4K x 4 w/Power-Down
4K x 4 Cache-Tag w/Open Drain and Power-Down
4K x 4 Cache-Tag w/Power-Down
4K x 4 w/Output Enable and Power-Down
4K x 4 w/Separate 1/0 and Power-Down
4K x 4 w/Separate 1/0 and Power-Down
2K x 8 w/Power-Down
64K x 1 w/Power-Down
16K x 4 w/Output Enable and Power-Down
16K x 4 w/Power-Down
16K x 4 w/Output Enable, 2 Chip Selects and Power-Down
16K x 4 BiCEMOSTM w/Output Enable
16K x 4 w/Separate 1/0 and Power Down
16K x 4 w/Separate 1/0 and Power Down
16K x 4 BiCEMOSTM
16K x 4 BiCEMOS w/Output Enable and 2 Chip Selects
8K x 8 w/Power-Down
8K x 8 Resettable Power-Down
8K x 8 Cache-Tag w/Power-Down
8K x 8 BiCEMOSTM
8K x 8 BiCEMOSTM Resettable
8K x 8 BiCEMOSTM Cache-Tag
4K x 16 w/Power-Down
4K x 16 w/Address Latch and Power-Down
8K x 9 w/Power-Down
8K x 9 w/Address Latch and Power-Down
8K x 9 BiCEMOSTM w/Address Latch
8K x 9 BiCEMOSTM
8K x 9 BiCEMOSTM Cache-Tag
4K x 18 x 2 w/Single Address Latch and Power-Down
4K x 18 x 2 w/Dual Address Latches and Power-Down
4K x 18 x 2 Cache-Tag and Power-Down
256K x 1 w/Power-Down
64K x 4 w/Output Enable and Power-Down
64K x 4 w/Power-Down
64K x 4 BiCEMOSTM w/Output Enable
64K x 4 w/Separate 1/0 and Power-Down
64K x 4 w/Separate 1/0 and Power-Down
64K x 4 BiCEMOSTM
32K x 8 w/Power-Down
32K x 8 BiCEMOSTM
32K x 8 BiCEMOSTM w/Address Latch
32K x 9 w/Power-Down
32K x 9 w/Address Latch, Parity and Power-Down
32K x 9 w/Address Latch and Power-Down
32K x 9 Burst Mode w/Power-Down
1 Meg x 1 w/Power-Down
256K x 4 w/Power-Down
128K x 8 w/Power-Down

1.3

12

NUMERICAL TABLE OF CONTENTS
PART NO.

100484
100490
100494
100496ll
100496Rl
100497
100498
100504
100506ll
100506RlA
100507
100508
100509
101484
101490
101494
101496ll
101496Rl
101497
101498
101504
101506ll
101506RlA
101507
101508
101509
10484
10490
10494
10496ll
10496Rl
10497
10498
10504
10506ll
10506RlA
10507
10508'
10509
29FCT52
29FCT520
29FCT520T
29FCT521T
29 FCT52T
29 FCT53
29 FCT53T
3106 Ada
3120C-SRC (SPP)
3123C-SRC (SPP/e)
3178C-SRC (ASAPP)

PAGE

4K x 4 ECl 100K SRAM ................................................................................ SMP
64K x 1 ECl 100K SRAM ................. ;........................................................... SMP
16K x 4 ECl 100K SRAM .................................. ~ ......................................... . SMP
16K x 4 Self-Timed latch Input, latch Output ............................................. . SMP
16K x 4 Self-Timed Reg Input, latch Output ............................................... . SMP
16K x 4 Synchronous Write, latch Output.. ................................................. . SMP
16K x 4 Conditional Write, latch Output ...................................................... . SMP
64K x 4 ECl 100K SRAM ............................................................................. SMP
64K x 4 Self-Timed latch Input, latch Output ............................................. . SMP
SMP
64K x 4 Self-Timed Reg Input, latch Output
16K x 4 Synchronous Write, latch Output.. ................................................. . SMP
64K x 4 Conditional Write, latch Output ...................................................... . SMP'
32K. x 9 ECl 100K SRAM ............................................................................. SMP
4K x 4 ECl 101K SRAM ............................................................................... SMP
64K x 1 ECl 101K SRAM ............................................................................. SMP
16K x 4 ECl 101K,SRAM ........................................................................... .. SMP
16K x 4 Self-Timed latch Input, latch Output ............................................. . SMP
16K x 4 Self-Timed Reg Input, latch Output ................................................ SMP
16K x 4 Synchronous Write, latch Output. .................................................. . SMP
16K x 4 Conditional Write, latch Output.. .................................................... . SMP
64K x 4 ECl 100K SRAM ............................................................................. SMP
64K x 4 Self-Timed latch Input, latch Output ............................................ .. SMP
64K x 4 Self-Timed Reg Input, latch Output .............................................. .. SMP
16K x 4 Synchronous Write, latch Output.. ................................................ .. SMP
64K x 4 Conditional Write, latch Output ...................................................... . SMP
32K x 9 ECl 101K SRAM ............................................................................. SMP
4K x 4 ECl 10K SRAM ...............................................................................:. SMP
64K x 1 ECl 10K SRAM ............................................................................... , SMP
16K x 4 ECl 10K SRAM ............................................................................... SMP
16K x 4 Self-Timed latch Input, latch Output ............................................ .. 'SMP,
16K x 4 Self-Timed Reg Input, latch Output ............................................... . SMP
16K x 4 Synchronous Write, latch Output.. ................................................. . SMP
16K x 4 Conditional Write, latch Output.. .................................................... . SMP
64K x 4 ECl 10K SRAM ........ ;...................................................................... SMP
64K x 4 Self-Timed latch Input, latch Output ............................................. . SMP
64K x 4 Self-Timed Reg Input, latch Output .............................................. .. SMP
64K x 4 Synchronous Write, latch Output.. ................................................ .. SMP
64K x 4 Conditional Write, latch OutpuL .................................................... . SMP
32K x 9 ECl 10K SRAM ............................................................................... SMP
Non-inverting Octal Registered Transceiver ................................................ . 6.26
Multi-level Pipeline Register ........................................................................ .. 6.27
Multi-level Pipeline Register ........................................................................ .. 6.2
Multi-level Pipeline Register ........................................................................ .. 6.2
Non-inverting Octal Registered Transceiver ............................................... .. 6.1
Inverting Octal Registered Transceiver ....................................................... .. 6.26
Inverting Octal Registered Transceiver ......................................................... 6.1
Ada Compiler ................................................... :.......................................... .. RISC
System Programmer's Package ................................................................... . RISC
System Programmer's Packagele .............................................................. :. RISC
Ada Stand-alone Programmer's Package ................................................... .. RISC

1.4

II

NUMERICAL TABLE OF CONTENTS (CONTINUED)
PART NO.
39C01
39C10
39C60
39C8XX
49C25
49C402
49C41 0
49C460
49C465
49C466
49FCT661
49FCT804
49FCT805
49FCT806
49FCT818
54/74FBT2240
54/74FBT2244
54/74FBT2373
54/74FBT240
54/74FBT241
54/74FBT244
54/74FBT245
54/74FBT2827
54/74FBT2828
54/74FBT2841
54/74FBT373
54/74FBT374
54/74FBT540
54/74FBT541
54/74FBT821
54/74FBT823
54/74FBT827
54/74FBT828
54/74FBT841
54/74FCT138
54/74FCT138T
54/74FCT139
54/74FCT139T
54/74FCT151T
54/74FCT157T
54/74FCT161
54/74FCT161T
54/74FCT163
54/74FCT163T
54/74FCT182
54/74FCT191
54/74FCT191T
54/74FCT193
54/74FCT193T
54/74FCT240

PAGE
4-Bit Microprocessor Slice ............................................... ..............................
12-Bit Sequencer ...........................................................................................
16-Bit Cascadable EDC.................................................................................
IDT39C8XXX Family ......................................................................................
Microcycle Length Controller .......... ............ ...... .......... ................ ...... .............
16-Bit Microprocessor Slice ............................ ............ .............. .......... ...........
16-Bit Sequencer .......... ..... ....... .......... ........... ........... ....... ..............................
32-Bit Cascadable EDC .................. ...................... ....... ...................... ............
32-Bit CMOS Flow-ThruEDC Unit .................................................................
64-BIT CMOS Flow-ThruEDC Unit ................................................................
16-Bit Synchronous Binary Counter ..............................................................
High-Speed Tri-Port Bus Multiplexer ...................... .................... ............ .......
Buffer/Clock Driver w/Guaranteed Skew.......... ............ .................... .............
Buffer/Clock Driver w/Guaranteed Skew.......... ............ .................... .............
Octal Register with SPCTM .............................................................................
Inverting Octal Buffer/Line Driver w/25n Series Resistor ..............................
Inverting Octal Buffer/Line Driver w/25n Series Resistor ..............................
Octal Transparent Latch w/3-State & 25n Series Resistor ...... .....................
Inverting Octal Buffer/Line Driver ..................................................................
Non-inverting Octal Buffer/Line Driver .................... .................... ...................
Non-inverting Octal Buffer/Line Driver ........ .......... ...................... ...................
Non-inverting Octal Transceiver .................... .......... .......... ............ ................
Non-inverting 10-Bit Buffers/Driver w/25n Series Resistor .......... .................
Inverting10-Bit Buffers/Driver w/25n Series Resistor ....................................
10-Bit Memory Latch w/25n Series Resistor........ ...................... .......... .........
Octal Transparent Latch w/3-State ................................................................
Non-inverting Octal D Register ......................................................................
Inverting Octal Buffer ................................................................................. ....
Non-inverting Octal Buffer ............................................... ..............................
10-Bit Non-inverting Register ...................... ..................... ..............................
9-Bit Inverting Register .................................................... ..............................
Non-inverting 10-Bit Buffers/Driver ................................................................
Inverting10-Bit Buffers/Driver........................................... ......... .....................
10-Bit Non-inverting Latch ..................................................................... :.......
1-of-8 Decoder ........................................................................................... ....
1-of-8 Decoder ...............................................................................................
Dual 1-of-4 Decoder.......... ....... ............. ............ ............ ..................... ...........
Dual 1-of-4 Decoder ......................................................................................
8-lnput Multiplexer ............................................................................... ..........
Quad 2-lnput Multiplexer ... :...........................................................................
Synchronous Binary Counter w/Asynchronous Master Reset .......................
Synchronous Binary Counter w/Asynchronous Master Reset .......................
Synchronous Binary Counter w/Synchronous Reset.....................................
Synchronous Binary Counter w/Synchronous Reset.....................................
Carry Lookahead Generator ...................... .......... ........ ............ .......... ............
Up/Down Binary Counter w/Preset and Ripple Clocks ........ .............. ............
UpIDown Binary Counter w/Preset and Ripple Clock.......... ............ ........ ......
Up/Down Binary Counter w/Separate Up/Down Clocks ...... ................ ..........
Up/Down Binary Counter w/Separate Up/Down Clocks ........ .............. ..........
Inverting Octal Buffer/Line Driver ..................................................................

1.4

5.1
5.2
5.10
6.33
6.32
5.3
5.4
5.11
5.12
5.13
6.28
6.29
6.3
6.3
6.31
6.67
6.68
6.69
6.56
6.57
6.58
6.59
6.7
6.7
6.71
6.6
6.61
6.62
6.62
6.63
6.64
6.65
6.65
6.66
6.34
6.3
6.35
6.4
6.5
6.6
6.36
6.7
6.36
6.7
6.37
6.38
6.8
6.39
6.9
6.4

2

NUMERICAL TABLE OF CONTENTS (CONTINUED)
PART NO.
54/74 FCT240T
54/74FCT241
54/74FCT241T
54/74FCT244
54/74FCT244T
54/74 FCT245
54/74 FCT245T
54/74FCT251T
54/74FCT257T
54/74FCT273
54/74FCT273T
54/74FCT299
54/74FCT299T
54/74FCT373
54/74FCT373T
54/74FCT374
54/74FCT374T
54/74FCT377
54/74FCT377T
54/74FCT399
54/74FCT399T
54/74FCT521
54/74FCT521 T
54/74FCT533
54/74FCT533T
54/74FCT534
54/74FCT534T
54/74FCT540
54/74FCT540T
54/74FCT541
54/74FCT541 T
54/74FCT543
54/74FCT543T
54/74FCT573
54/74FCT573T
54/74FCT574
54/74 FCT574T
54/74FCT620T
54/74FCT621T
54/74FCT622T
54/74FCT623T
54/74FCT640
54/74FCT640T
54/74FCT645
54/74 FCT645T
54/74FCT646
54/74FCT646T
54/74 FCT648T
54/74FCT651T
54/74FCT652T

PAGE
Inverting Octal Buffer/Line Driver ................................................................. .
Non-inverting Octal Buffer/Line Driver .......................................................... .
Non-inverting Octal Buffer/Line Driver ...........................................................
Non-inverting Octal Buffer/Line Driver ...........................................................
Non-inverting Octal Buffer/Line Driver ...........................................................
Non-inverting Octal Transceiver ................................................................... .
Non-inverting Octal Transceiver ................................................................... .
8-lnput Multiplexer w/3-State ........................................................................ .
Quad 2-lnput Multiplexer w/3-State ............................................................ ..
Octal D Flip-Flop w/Common Master Reset ............................................... ..
Octal D Flip-Flop w/Common Master Reset ................................................ ..
8-lnput Universal Shift Register w/Common Parallel I/O Pins ..................... ..
8 Input Universal Shift Register w/Common Parallel I/O Pins ..................... ..
Non-inverting Octal Transparent Latch ......................................................... .
Non-inverting Octal Transparent Latch w/3-State ......................................... .
Non-inverting Octal D Flip-Flop .....................................................................
Non-inverting Octal D Flip-Flop ................................................................... ..
Octal D Flip-Flop w/Clock Enable ................................................................. .
Octal D Flip-Flop w/Clock Enable ................................................................. .
Quad Dual-Port Register ............................................................................. ..
Quad Dual-Port Register ...............................................................................
8-Bit Identity Comparator ...............................................................................
8-Bit Identity Comparator ...............................................................................
Inverting Octal Transparent Latch .................................................................
Inverting Octal Transparent Latch w/3-State ................................................ .
Inverting Octal D Flip-Flop w/3-State ............................................................ .
Inverting Octal D Flip-Flop .............................................................................
Inverting Octal Buffer/Line Driver ................................................................ ..
Inverting Octal Buffer/Line Driver ................................................................ ..
Non-inverting Octal Buffer/Line Driver ...........................................................
Non-inverting Octal Buffer/Line Driver ...........................................................
Non-inverting Octal Latched Transceiver .................................................... ..
Non-inverting Octal Latched Transceiver .................................................... ..
Non-inverting Octal Transparent Latch ......................................................... .
Non-inverting Octal Transparent Latch w/3-State ........................................ ..
Non-inverting Octal D Register w/3-State ..................................................... .
Non-inverting Octal D Flip-Flop .....................................................................
Inverting Octal Bus Transceiver w/3-State ................................................... .
Non-inverting Octal Bus Transceiver (Open Drain) ...................................... .
Inverting Octal Bus Transceiver (Open Drain) ............................................. .
Non-inverting Octal Bus Transceiver w/3-State ........................................... ..
Inverting Octal Transceiver ........................................................................... .
Inverting Octal Transceiver ........................................................................... .
Non-inverting Octal Transceiver ................................................................... .
Non-inverting Octal Transceiver ................................................................... .
Non-inverting Octal Registered Transceiver ................................................. .
Non-inverting Octal Registered Transceiver ................................................. .
Inverting Octal Registered Transceiver ........................................................ .
Inverting Octal Registered Transceiver ........................................................ .
Non-inverting Octal Registered Transceiver ................................................. .

1.4

6.1
6.4
6.1
6.4
6.1
6.41
6.11
6.5
6.6
6.42
6.12
6.43
6.13
6.44
6.14
6.45
6.15
6.46
6.16
6.47
6.17
6.48
6.18
6.44
6.14
6.45
6.15
6.4
6.1
6.4
6.1
6.49
6.19
6.44
6.14
6.45
6.15
6.21
6.22
6.22
6.21
6.41
6.11
6.41
6.11
6.5
6.2
6.2
6.2
6.2

3

a

NUMERICAL TABLE OF CONTENTS (CONTINUED)
PAGE

PART NO.
54/74FCT821
54/74FCT821T
54/74FCT823
54/74FCT823T
54/74 FCT824
54/74 FCT825
54/74FCT825T
54/74FCT827
54/74 FCT827T
54/74FCT828T
54/74FCT833
54/74FCT841
54/74FCT841T
54/74FCT843
54/74FCT843T
54/74FCT844
54/74FCT845
54/74FCT845T
54/74FCT861
54/74FCT863
54/74FCT864
6116
61298
6167
6168
6177
6178
61970
6198
61B298
61B98
7005
7006
7010
70101
70104
70105
7012
70121
70125
7014
7024
7025
7030
7032
7040
7042
7044
7050
7052

10-Bit Non-inverting Register w/3-State ........... ...... ........ ..... ........ .............. ....
10-Bit Non-inverting Register w/3-State ...................... ... ....... ........................
9-Bit Non-inverting Register w/Clear & 3-State ................. .......... ...... ............
9-Bit Non-inverting Register w/Clear & 3-State ................. .......... ..................
9-Bit Inverting Register w/Clear & 3-State ....................................................
8-Bit Non-inverting Register ...................................................... ....................
8-Bit Non-inverting Register w/Clear & 3-State ..... .................. ............... .......
10-Bit Non-inverting Buffer................. ........... .................................. ..............
10-Bit Non-inverting Buffer ............................................. ..... ................... .......
10-Bit Inverting Buffer... .................... ....... ..... ....... ..... ....................................
8-Bit Transceiver w/Parity ............... ................................... ..... .... ........... .......
10-Bit Non-inverting Latch ... ..... ....................................... ............... ..............
10-Bit Non-inverting Latch .................................................. ................. .........
9-Bit Non-inverting Latch..... ...... ...... ..... ........ ................... ..............................
9-Bit Non-inverting Latch...................................... ........................ ........ .........
9-Bit Inverting Latch ......................................................................................
8-Bit Non-inverting Latch...... ........... ........ ..... .................................................
8-Bit Non-inverting Latch..... ...... ....... ..... ....... ........ ........... ..............................
10-Bit Non-inverting Transceiver .......... ............................................. ............
9-Bit Non-inverting Transceiver.............................. ......................................
9-Bit Inverting Transceiver ............................................................................
16K (2K x 8) CMOS SRAM .................. ............................... ...... ....................
64K x 4 w/Output Enable .................................................... .......... ................
16K (16K x 1) CMOS SRAM (Power-Down) .................................................
16K (4K x 4) CMOS SRAM (Power-Down) ...................................................
4K x 4 Cache-Tag Open Drain......................................................................
4K x 4 Cache-Tag Totem Pole......................................................................
4K x 4 w/Output Enable .......................................... ......................................
16K x 4 w/Output Enable ........................... ... ..... ..... ......................................
64K x 4 BiCEMOS.........................................................................................
16K x 4 w/Output Enable BiCEMOS .................. ......... ................ .............. ....
64K (8K x 8) Dual-Port RAM .........................................................................
128K (16K x 8) Dual-Port RAM .....................................................................
9K (1 K x 9) Dual-Port RAM (MASTER) .........................................................
9K (1 K x 9) Dual-Port RAM (MASTER w/lnterrupts) .....................................
9K (1 K x 9) Dual-Port RAM (SLAVE) ............................................................
9K (1 K x 9) Dual-Port RAM (SLAVE w/lnterrupts) ........................................
18K (2K x 9) Dual-Port RAM .........................................................................
18K (2K x 9) Dual-Port RAM (MASTER w/lnterrupts) ...................................
18K (2K x 9) Dual-Port RAM (SLAVE w/lnterrupts) ......................................
32K (4K x 9) Dual-Port RAM .........................................................................
64K (4K x 16 Dual-Port RAM ........................................................................
128K (8K x 16) Dual-Port RAM .....................................................................
8K (1 K x 8) Dual-Port RAM (MASTER) .........................................................
16K (2K x 8) Dual-Port RAM (MASTER) ......................................................
8K (1 K x 8) Dual-Port RAM (SLAVE) ............................................................
16K (2K x 8) Dual-Port RAM (SLAVE) ..........................................................
144K (4K x 36) Dual-Port RAM .....................................................................
8K (1 K x 8) FourPort™ RAM ........................................................................
16K (2K x 8) FourPort™ RAM .......................................................................

1.4

6.51
6.25
6.51
6.25
6.51
6.51
6.25
6.52
6.23
6.23
6.53
6.54
6.24
6.54
6.24
6.54
6.54
6.24
6.55
6.55
6.55
SRM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP

4

NUMERICAL TABLE OF CONTENTS (CONTINUED)
PART NO.
71024
71027
71028
71220
71222
71256
71257
71258
71259
71270
71281
71282
7130
7132
71321
71322
7133
7134
71342
7140
7142
71421
7143
71509
71556
71559
71569
71586
71589
7164
7165
71681
71682
7169
7174
7177
7178
7179
7186
7187
7188
7198
71981
71982
71B256
71B258
71B569
71B64
71B69
71B74

PAGE
128K x 8 ........................................................................................................
1024K x 1 ......................................................................................................
256K x 4 ....................................................................................................... .
4Kx18x2Intel ............................................................................................
4K X 18 X 2 MIPS ......................................................................................... .
32K X 8 ......................................................................................................... .
256K X 1 ........................................................................................................
64K X 4 ..........................................................................................................
32K X 9 ......................................................................................................... .
4K X 18 X 2 Cache-Tag .................................................................................
64K X 4 Separate I/O .................... ................................................................ .
64K X 4 Separate I/O .......... .......................................................................... .
8K (1 K X 8) Dual-Port RAM (MASTER) ........................................................ .
16K (2K X 8) Dual-Port RAM (MASTER) ..................................................... .
16K (2K X 8) Dual-Port RAM (MASTER w/lnterrupts) .................................. .
16K (2K X 8) Dual-Port RAM (w/Semaphores) ............................................ .
32K (2K X 16) Dual-Port RAM (MASTER) .................................................... .
32K (4K x 8) Dual-Port RAM ........................................................................ .
32K (4K x 8) Dual-Port RAM (w/Semaphores) ............................................ .
8K (1 K x 8) Dual-Port RAM (SLAVE) ........................................................... .
16K (2K x 8) Dual-Port RAM (SLAVE) ......................................................... .
16K (2K x 8) Dual-Port RAM (SLAVE w/lnterrupts) ..................................... .
32K (2K x 16) Dual-Port RAM (SLAVE) ....................................................... .
32K x 9 Latched ........................................................................................... .
32K x 8 Latched ........................................................................................... .
32K x 9 w/ALE ..............................................................................................
8K x 9 Latched ..... .........................................................................................
4K x 16 Latched ........................................................................................... .
32K x 9 Burst Mode ......................................................................................
8K x 8 ............................................................................................................
8K x 8 Resettable ......................................................................................... .
4K x 4 Separate I/O .....................................................................................
4K x 4 Separate I/O .....................................................................................
8K x 9 ........................................................................................................... .
8K x 8 Cache-Tag .........................................................................................
4K x 4 Cache-Tag Open Drain ..................................................................... .
4K x 4 Cache-Tag Totem Pole ..................................................................... .
8K x 9 Cache-Tag .........................................................................................
4K x 16 ......................................................................................................... .
64K x 1 ..........................................................................................................
16K x 4 ......................................................................................................... .
16K x 4 w/Output Enable, 2 CS ................................................................... .
16K x 4 Separate I/O .................................................................................... .
16K x 4 Separate I/O ... ................................................................................. .
32K x 8 BiCEMOS .........................................................................................
64K x 4 BiCEMOS .........................................................................................
8K x 9 Latched BiCEMOS .............................................................................
8K x 8 BiCEMOS ..........................................................................................
8K x 9 BiCEMOS ..........................................................................................
8K x 8 Cache-Tag BiCEMOS ........................................................................

1.4

SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM

5

•

NUMERICAL TABLE OF CONTENTS (CONTINUED)
PART NO.
71B79
71B88
71B981
71B982
7200
7201
7202
72021
7203
72031
7204
72041
7205
7206
72103
72104
72105
7210L
72115
72125
72131
72132
72141
72142
7216L
7217L
72200
72201
72210
72211
72215A
72220
72221
72225A
72230
72231
72235
72240
72241
72245
72401
72402
72403
72404
72413
72420
72421
7251
72510
72511

PAGE
8K x 9 Cache-Tag BiCEMOS ....................................................................... .
16K x 4 BiCEMOS .........................................................................................
16K x 4 Separate 1/0 BiCEMOS ...................................................................
16K x 4 Separate I/O BiCEMOS ...................................................................
256 x 9-Bit Parallel FI FO .............................................................................. .
512 x 9-Bit Parallel FIFO ...............................................................................
1024 x 9-Bit Parallel FI FO ............................................................................ .
1K x 9-Bit Parallel FI FO wi Flags and OE .................................................... .
2K x 9-Bit Parallel FIFO ............................................................................... .
2K x 9-Bit Parallel FIFO w/Flags and OE ..................................................... .
4K x 9-Bit Parallel FI FO ............................................................................... .
4K x 9-Bit Parallel FI FO w/Flags and OE ..................................................... .
8K x 9-Bit Parallel FIFO ............................................................................... .
16K x 9-Bit Parallel FIFO ............................................................................. .
2K x 9-Bit Configurable Parallel-Serial FIFO ................................................ .
4K x 9-Bit Configurable Parallel-Serial FIFO ................................................ .
256 x 16-Bit Parallel-to-Serial FIFO ............................................................. .
16 x 16 Parallel Multiplier-Accumulator ........................................................ .
512 x 16 Parallel-to-Serial FIFO .................................................................. .
1024 x 16-Bit Parallel-to-Serial FIFO ........................................................... .
2048 x 9-Bit Parallel-to-Serial FIFO ............................................................. .
2048 x 9-Bit Serial-to-Parallel FIFO ............................................................. .
4096 x 9-Bit Parallel-to-Serial FIFO ............................................................. .
2048 x 9-Bit Serial-to-Parallel FIFO ............................................................. .
16 x 16 Parallel Multiplier ............................................................................. .
16 x 16 Parallel Multiplier (32 Bit Output) ..................................................... .
256 x 8-Bit Parallel Synchronous FIFO ....................................................... .
256 x 9-Bit Parallel Synchronous FIFO ....................................................... .
512 x 8-Bit Parallel Synchronous FI FO ....................................................... .
512 x 9-Bit Parallel Synchronous FIFO ....................................................... .
512 x 18-Bit Parallel Synchronous FIFO ...................................................... .
1K x 8-Bit Parallel Synchronous FIFO ......................................................... .
1K x 9-Bit Parallel Synchronous FIFO ......................................................... .
1024 x 18-Bit Parallel Synchronous FI FO .................................................... .
2K x 8-Bit Parallel Synchronous FI FO ........................................................ ..
2K x 9-Bit Parallel Synchronous FI FO ......................................................... .
2K x 18-Bit Parallel Synchronous FIFO ....................................................... .
4K x 8-Bit Parallel Synchronous FI FO ......................................................... .
4K x 9-Bit Parallel Synchronous FIFO ......................................................... .
4K x 18-Bit Parallel Synchronous FIFO ....................................................... .
64 x 4 FIFO w/OE .........................................................................................
64 x 5 FIFO w/OE .........................................................................................
64 x 4 FIFO w/OE .........................................................................................
64 x 5 FIFO w/OE .........................................................................................
64 x 5 FIFO (w/Flags) .................................................................................. .
64 x 8-Bit Parallel Synchronous FIFO ......................................................... .
64 x 9-Bit Parallel Synchronous FIFO ......................................................... .
512 x 18-Bit - 1K x 9-Bit BiFIFO ................................................................ .
512 x 18-Bit -1 K x 9-Bit BiFIFO ................................................................ .
512 x 18-Bit BiFIFO ..................................................................................... .

1.4

SRAM
SRAM
SRAM
SRAM
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
5.5
SMP
SMP
SMP
SMP
SMP
SMP
5.6
5.6
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP

6

NUMERICAL TABLE OF CONTENTS (CONTINUED)
PAGE

PART NO.
7252
72520
72521
72605
72615
73200L
73201L
73210
73211
7381L
7383L
75C457
75C458
75C48
75C58
79R3000
79R3001
79R3010
79R3020
79R4000
7M1001
7M1002
7M1003
7M1004
7M1005
7M1041
7M1042
7M1043
7M1044
7M134
7M135
7M137
7M144
7M145
7M205
7M206
7M207
7M4003
7M4016
7M4017
7M4042
7M4048
7M6032
7M624
7M812
7M912
7MB1006
7MB1008
7MB4009
7MB6036

1K x 18-Bit - 2K x 9-Bit BiFIFO ...................................................................
1K x 18-Bit - 2K x 9-Bit BiFIFO ...................................................................
1K x 18-Bit BiFIFO ........................................................................................
256 x 18-Bit Synchronous BiFIFO (SyncBiFIFOTM) ..................................... .
512K x 18-Bit Synchronous BiFIFO (SyncBiFIFOTM) .................................. ..
16-Bit CMOS Multilevel Pipeline Register .................................................... .
16-Bit CMOS Multilevel Pipeline Register .................................................... .
Fast Octal Register Transceiver w/Parity ..................................................... .
Fast Octal Register Transceiver w/Parity .................................................... ..
16-Bit CMOS Cascadable ALU ................................................................... ..
16-Bit CMOS Cascadable ALU ................................................................... ..
CMOS Single 8-Bit PaletteDACTM for True Color Applications ................... ..
Triple 8-Bit PaletteDACTM ........................................................................... ..
8-Bit Flash ADC ............................................................................................
8-Bit Flash ADC with Overflow Output ..........................................................
RISC CPU Processor .................................................................................. ..
32-Bit RISControlier™ ................................................................................. .
RISC Floating-Point Accelerator ................................................................. ..
RISC CPU Write Buffer ............................................................................... ..
Third Generation RISC Processor ................................................................
128K x 8 Dual-Port SRAM Module ...............................................................
16K x 32 Dual-Port SRAM Module '" ........................................................... .
64K x 8 Dual-Port SRAM Module ................................................................ ..
8K x 8 Dual-Port SRAM Module .......... '........................................................ .
16K x 9 Dual-Port SRAM Module ..................................................................
8K x 8 FourPort™ SRAM Module .................................................................
4K x 8 FourPort™ SRAM Module .................................................................
4K x 16 FourPort™ SRAM Module ...............................................................
2K x 16 FourPort™ SRAM Module ...............................................................
8K x 8 Master Dual-Port SRAM Module .......................................................
16K x 8 Master Dual-Port SRAM Module ..................................................... .
32K x 8 Master Dual-Port SRAM Module ......................................................
8K x 8 Slave Dual-Port SRAM Module ..........................................................
16K x 8 Slave Dual-Port SRAM Module ...................................................... .
8K x 9-Bit CMOS FIFO Module .....................................................................
16K x 9-Bit CMOS FIFO Module ...................................................................
32K x 9-Bit CMOS FIFO Module ...................................................................
32K x 32 CMOS Static RAM Module .......................................................... ..
256K x 16 CMOS Static RAM Module ..........................................................
64K x 32 CMOS Static RAM Module ............................................................
256K x 4 CMOS Static RAM Module .......................................................... ..
512K x 8 CMOS Static RAM Module .......................................................... ..
16K x 32 Writable Control Store Static RAM Module .................................. ..
64K x 16 CMOS Static RAM Module .......................................................... ..
64K x 8 CMOS Static RAM Module ............................................................ ..
64K x 9 CMOS Static RAM Module ..............................................................
64K x 16 Dual-Port SRAM Module .............................................................. .
32K x 16 Dual-Port SRAM Module ...............................................................
2(16K x 16) CMOS Static RAM Module ...................................................... ..
128K x 16 Dual-Port (Shared Memory) SRAM Module .............................. ..

1.4

SMP
SMP
SMP
SMP
SMP
5.8
5.8
5.9
5.9
5.7
5.7
5.14
5.15
5.16
5.17
RISC
RISC
RISC
RISC
RISC
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP

7

II

NUMERICAL TABLE OF CONTENTS (CONTINUED)
PART NO.
7MB6039
7MB6040
7MB6042
7MB6043
7MB6044
7MB6046
7MB6049
7MB6051
7MB6056
7MB6061
7MB6064
7MB6136
7MB6146
7MB6156
7MC4001
7MC4005
7MC4032
7MP2005
7MP2009
7MP2010
7MP2011
7MP4008
7MP4031
7MP4034
7MP4036
7MP4045
7MP4047
7RS101
7RS101F
7RS102
7RS102F
7RS103
7RS103F
7RS104
7RS104F
7RS105
7RS105F
7RS107F
7RS201
7RS202
7RS203
7RS301

PAGE
Dual (16K x 60) Data/Instruction Cache Module for IDT79R3000 CPU ....... .
Dual (16K x 64) Data/Instruction Cache Module for General CPUs ............ .
8K x 112 Writable Control Store Static RAM Module .................................. ..
Dual (8K x 64) Data/Instruction Cache Module for IDT79R3000 CPU ........ .
Dual (4K x 64) Data/Instruction Cache Module for IDT79R3000 CPU ........ .
64K x 16 Dual-Port (Shared Memory) SRAM Module .................................. .
Dual (16K x 60) Data/Instruction Cache Module for IDT79R3000 CPU
(Multiprocessor) ................................................. :.................................. ..
Dual (8K x 64) Data/Instruction Cache Module for IDT79R3000 CPU
(Multiprocessor) ................ ;......... ; ......................................................... ..
32K x 16 Dual-Port (Shared Memory) SRAM Module .................................. .
Dual (16K x 60) Data/Instruction w/Resetiable Instruction Tag .................. ..
Dual (4K x 60) Data/Instruction Cache Module for IDT79R3000 CPU ....... ..
128K x 18 Dual-Port (Shared Memory) SRAM Module .............................. ..
64K x 18 Dual-Port (Shared Memory) SRAM Module .................................. .
32K x 18 Dual-Port (Shared Memory) SRAM Module ................................. ..
1M x 1 CMOS Static RAM Module .............................................................. ..
16K x 16 CMOS Static RAM Module ........................................................... .
16K x 32 CMOS Static RAM Module w/Separate Data I/O ......................... ..
'8K x 9-Bit FIFO Module ............................................................................... ..
32K x 18-Bit FIFO Module ........................................................................... .
16K x 18-Bit FIFO Module ........................................................................... .
16K x 9 Bit FIFO Module ............................................................................. ..
512K x 8 CMOS Static RAM Module .......................................................... ..
16K x 32 CMOS Static RAM Module ...................... : ................................... ..
256K x 8 CMOS Static RAM Module ........................................................... .
64K x 32 CMOS Static RAM Module .......................................................... ..
256K x 32 CMOS Static RAM Module ......................................................... .
512Kx 16 CMOS Static RAM Module ......................................................... .
R3000 Module w/64K I-Cache, 64K D-Cache, 4 Word Read Buffer and 1
Word Write Buffer .................................................................................. .
R3000, R3010 Module w/64K I-Cache, 64K D-Cache, 4 Word Read Buffer
and 1 Word Write Buffer ........... ;........ :.................................................. ..
R3000 Module wl16K I-Cache, 16K D-Cache, 1 Word Read Buffer and 1
Word Write Buffer .................................................................................. .
R3000, R3010 Module w/16K I-Cache, 16K D-Cache, 1 Word Read Buffer
and 1 Word Write Buffer ............... ;....................................................... ..
R3000 Module w/16K I-Cache and 16K D-Cache ...................................... ..
R3000, R3010 Module w/16K I-Cache and16K D-Cache ........................... ..
R3001 Module w/ 128K I-Cache, 128K D-Cache, 1 Word Read Buffer and
1 Word Write Buffer ............................................................................... .
R3001, R3010 Module w/128K I-Cache, 128K D-Cache, 1 Word Read
Buffer and 1 Word Write Buffer ..............................................................
R3000 Module w/32K I-Cache, 16K D-Cache,1 Word Read Buffer, 1 Word
Write Buffer and IDT Bus ...................................................................... ..
R3000, R3010 Module w/32K I-Cache, 16K D-Cache, 1 Word Read Buffer,
1 Word Write Buffer and IDT.Bus ......................................................... ..
R3000, R3010 Module w/64K I-Cache, 64K D-Cache, R3020 and 1 Word
Read Buffer ............................................................................................ .
Nubus Board .................................................................................................
Nubus Board, Supports Nubus Memory ..................................................... ..
Nubus Board, Supports OnbOard Memory ................................................... .
TargetSystem™ for IDT7RS1 01 ................................................................. ..

1.4

SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
SMP
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC'
RISC
RISC
RISC
RISC
RISC
RISC
RISC'

8

NUMERICAL TABLE OF CONTENTS (CONTINUED)
PART NO.
7RS302
7RS303
7RS304
7RS305
7RS307
7RS340
7RS341
7RS342
7RS343
7RS347
7RS353-B
7RS353-MB
7RS353-MS
7RS353-S
7RS355-B
7RS355-MB
7RS355-MS
7RS355-S
7RS356-2B
7RS356-3B
7RS356-3MB
7RS357-1B
7RS357-1MB
7RS357-2B
7RS357-2MB
7RS357-3B
7RS357-3MB
7RS361-B
7RS361-E
7RS361-MB
7RS361-MS
7RS361-S
7RS363-1
7RS363-2
7RS364
7RS365
7RS366
7RS382
7RS383
7RS501-1
7RS501-1D
7RS501-1M
7RS501-2

PAGE
TargetSystem™ for IDT7RS102 ...................................................................
TargetSystem™ for IDT7RS1 03 ................................................................... .
TargetSystem™ for IDT7RS104 ...................................................................
TargetSystem™ for IDT7RS1 05 ................................................................. ..
TargetSystem™ for IDT7RS1 07 ...................................................................
System Board ...............................................................................................
Personality Board for IDT7RS101 .................................................................
Personality Board for IDT7RS102 ............................................................... ..
Personality Board for IDT7RS103 ............................................................... ..
Personality Board for IDT7RS107 .................................................................
JMI C-Executive™ Binary Code ...................................................................
JMI C-Executive™ Maintenance for Binary Code ........................................ .
JMI C-Executive™ Maintenance for Source Code ...................................... ..
JMI C-Executive™ SourceCode ................................................................. ..
Floating Point Library Binary Code .............................................................. .
Floating Point Library Maintenance for Binary Code .................................. ..
Floating Point Library Maintenance for Source Code .................................. .
Floating Point Library Source Code ............................................................ ..
R3000 C-Compiler Binary Code for 80286,80386 IDT7RS356-2MB R3000
C-Compiler Maintenance for Binary Code for 80286, 80386 PC-DOS .. .
R3000 C-Compiler Binary Code for PC SCO XENIX .................................. .
R3000 C-Compiler Maintenance for Binary Code SCO XENIX .................. ..
R3000 Macro Assembler Binary Code for 8086, 8088 PC-DOS ................ ..
R3000 Macro Assembler Maintenance for Binary Code 8086,8088 .......... ..
R3000 Macro Assembler Binary Code for 80286, 80386 PC-DOS ............ ..
R3000 Macro Assembler Maintenance for Binary Code 80286, 80386 ...... ..
R3000 Macro Assembler Binary Code for PC SCO XENIX ........................ ..
R3000 Macro Assembler Maintenance for Binary Code SCO XENIX ........ ..
IDT PROM Monitor Binary Code ...................................................................
IDT PROM Monitor Binary Code - in 4 EPROMs ...................................... .
IDT PROM Monitor Maintenance for Binary Code ...................................... ..
IDT PROM Monitor Maintenance for Source Code ...................................... .
IDT PROM Monitor Source Code ................................................................. .
R3000 PGA Breakout Board and HP 16500A Logic Analyzer Set-up
Software ..................................................................................................
R3000 PGA Breakout Board and HP 16500A Logic Analyzer Set-up
Software and 5 HP Adapters ..................................................................
HP 16500A Logic Analyzer Disassembler Software for 7RS300 Series
TargetSystems™ .................................................................................. ..
R3000 Flatpack Version ............................................................................... .
R3001 PGA Version ......................................................................................
R3000 Evaluation Board ............................................................................. ..
R3001 Evaluation Board ............................................................................. ..
MacStation™ Development System w/lDT7RS201 Nubus Board, IDT/ux
and C-Compiler ......................................................................................
MacStation™ Development System Documentation .................................. .
MacStation™ Development System Maintenance ..................................... ..
MacStation™ Development System w/150MB External Hard Disk, 40MB
External Tape Drive, IDT7RS201 Nubus Board, IDT/ux and CCompiler .................................................................................................

1.4

RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC.
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC

RISC

9

•

NUMERICAL TABLE OF CONTENTS (CONTINUED)

PART NO.
7RS501-3
7RS501-4
7RS501-5
7RS501-6
7RS502-1
7RS502-1 D
7RS502-1 M
7RS502-2
7RS502-3
7RS502-4
7RS502-5
7RS502-6
7RS503-1
7RS503-1 D
7RS503-1 M
7RS551-1 B
7RS571-1S
7RS572-1S
7RS573-1B
7RS573-1MB
8M612
8M624
8M824
8MP612
8MP624
8MP824
Flexi-Pak Module Family

M/2000
RC2030
RC3240
RC3260
RS1210

PAGE

Complete IDT7RS501 MacStation™ Development System w/MAC II
Computer, 8MB RAM, 150MB Hard Disk, 40MB External Tape Drive,
IDT7RS201 Nubus Board, IDT/ux and C-Compiler .............................. .
4MB SIMM Module for MAC II ......................................................................
IDT7RS501 MacStation™ Development System w/150MB External Hard
Disk, 7RS201 Nubus Board, IDT/ux and C-Compiler ............................ .
IDT7RS501 MacStation™ Development System w/40MB External Tape
Drive, 7RS201 Nubus Board, IDT/ux and C-Compiler .......................... .
MacStation™ Development System w/lDT7RS202 Nubus Board, 8MB
Nubus RAM Board, IDT/ux and C-Compiler .......................................... .
MacStation™ Development System Documentation .................................. ..
MacStation™ Development System Maintenance ...................................... ..
IDT7RS502 MacStation™ Development System w/150MB External Hard
Disk, 40MB External Tape Drive, IDT7RS202 Nubus Board, IDT/ux
and C-Compiler .................................................................................... ..
Complete IDT7RS502 MacStation™ Development System w/MAC II
Computer, 8MB RAM, 150MB Hard Disk; 40MB External Tape Drive,
IDT7RS202 Nubus Board, IDT/ux and C-Compiler .............................. ..
4MB SIMM Module for MAC II ......................................................................
IDT7RS502 MacStation™ Development System w/150MB External Hard
Disk, 7RS202 Nubus Board, IDT/ux and C-Compiler ............................ .
IDT7RS502 MacStation™ Development System w/40MB External Tape
Drive, 7RS202 Nubus Board, IDT/ux and C-Compiler .......................... .
MacStation™ Development System w/16MB RAM, IDT/ux and
C-Compiler .............................................................................................
MacStation™ Development System Documentation .................................. ..
MacStation™ Development System Maintenance ...................................... ..
IDT/ux - UNIX Operating System for MacStations™ ................................ ..
MIPS SPP for the MAC .................................................................................
MIPS SPP/e for the MAC ............................................................................ ..
MIPS Fortran for the MAC .......................................................................... ..
Maintenance for MIPS Fortran for the MAC ................................................ ..
32K x 16 CMOS Static RAM Module .......................................................... ..
64K x 16 CMOS Static RAM Module .......................................................... ..
128K x 8 CMOS Static RAM Module .......................................................... ..
32K x 16 CMOS Static RAM Module .......................................................... ..
64K x 16 CMOS Static RAM Module .......................................................... ..
128K x 8 CMOS Static RAM Module .......................................................... ..
Various Combinations of Four SRAMs, EPROMs and EEPROMs Packaged
in 32-Lead EDEC LCCs Mounted on PGA-Type Substrate .................. .
RISComputer™ Development System ......................................................... .
RISComputer™ Development System ......................................................... .
RISComputer™ Development System ......................................................... .
RISComputer™ Development System ......................................................... .
RISComputer™ Development System ........................................................ ..

1.4

RISC
RISC
RISC
RISC
RISC
RISC
RISC

RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
RISC
SMP
SMP
SMP
SMP
SMP
SMP
SMP
RISC
RISC
RISC
RISC
RISC

10

IDT PACKAGE MARKING DESCRIPTION
PART NUMBER DESCRIPTION

4.

lOT's part number identifies the basic product, speed,
power, package(s) available, operating temperature and
processing grade. Each data sheet has a detailed description,
using the part number, for ordering the proper product for the
user's application. The part number is comprised of a series
of alpha-numeric characters:

5.

1. An "lOT" corporate identifier for Integrated Device

6.

2.
3.

Technology, Inc.
A basic device part number composed of alpha-numeric
characters.
A device power identifier, composed of one or two alpha
characters, is used to identify the power options. In most
cases, the following alpha characters are used:
"S" or "SA" is used for the standard product's power.
"L" or "LA" is used for lower power than the standard
product.

7.

A device speed identifier, when applicable, is either alpha
characters, such as "A" or "8", or numbers, such as 20 or
45. The speed units, depending on the product, are in
nanoseconds or megahertz.
A package identifier, composed of one ortwo characters.
The data sheet should be consulted to determine the
packages available and the package identifiers for that
particular product.
A temperature/process identifier. The product is available
in either the commercial or military temperature range,
processed to a commercial specification, orthe product is
available in the military temperature range with full
compliance to MIL-STD-883. Many of lOT's products
have burn-in included as part of the standard commercial
process flow.
A special process identifier, composed of alpha characters,
is used for products which require radiation enhancement
(RE) or radiation tolerance (RT).

Example:
lOT

xxx. .. xxx

xx

x.. x

x... x

x

xx

1 T_:

Special Process
Processffemperature*
Package"
Speed
Power
Device Type"

" Field Identifier Applicable To All Products
2507 drw 01

ASSEMBLY LOCATION DESIGNATOR

MIL-STD-883C COMPLIANT DESIGNATOR

lOT uses various locations for assembly. These are
identified by an alpha character in the last letter of the date
code marked on the package. Presently, the assembly
location alpha character is as follows:
A = Anam, Korea
I = USA
P = Penang, Malaysia

lOT ships military products which are compliant to the latest
revision of MIL-STD-883C. Such products are identified by a
"C" designation on the package. The location of this designator
is specified by internal documentation at lOT.

1.5

1

Integr~ted

~

DIGITAL SIGNAL PROCESSING
CROSS REFERENCE GUIDE

Device Technology,lnc.

ANALOG DEVICES

lOT

CYPRESS (Con't)

lOT

ADSP·1009
ADSp·1012
ADSp·1010
ADSP·1016

7209
7212
7210
7216

CYPRESS

lOT

7C510
7C510·45DC
7C510-45GC
7C510-45LC
7C510·45PC
7C510-55DC
7C510·55DMB
7C510·55GC
7C510·55GMB
7C510·55LC
7C510-55LMB
7C510-55PC
7C510·65DC
7C510·65DMB
7C510·65GC
7C510·65GMB
7C510·65LC
7C510·65LMB
7C510-65PC
7C516
7C516-38DC
7C516·38GC
7C516·38LC
7C516·38PC
7C516·42DMB
7C516-42GMB
7C516-42LMB
7C516-45DC
7C516·45GC
7C516-45LC
7C516·45PC
7C516·55DC
7C516·55DMB
7C516·55GC
7C516-55GMB
7C516·55LC
7C516-55LMB
7C516-55PC
7C516·65DC
7C516-65DMB
7C516-65GC
7C516-65GMB
7C516·65LC
7C516-65LMB
7C516-65PC
7C517
7C517·45DC

7210
7210L45D
7210L45G
7210L45L
7210L45P
7210L55D
7210L550B
7210L55G
7210L55GB
7210L55L
7210L55LB
7210L55P
7210L65D
7210L65DB
7210L65G
7210L65GB
7210L65L
7210L65LB
7210L65P
7216
7216L35D
7216L35G
7216L35L
7216L35P
7216L40DB
7216L40GB
7216L40LB
7216L45D
7216L45G
7216L45L
7216L45P
7216L55D
7216L55DB
7216L55G
7216L55GB
7216L55L
7216L55LB
7216L55P
7216L65D
7216L65DB
7216L65G
7216L65GB
7216L65L
7216L65LB
7216L65P
7217
7217L45D

7C517-45GC
7C517-45LC
7C517-45PC
7C517-55DC
7C517-55DMB
7C517-55GC
7C517·55GMB
7C517·55LC
7C517·55LMB
7C517-55PC
7C517·65DC
7C517·65DMB
7C517·65GC
7C517·65GMB
7C517-65LC
7C517·65LMB
7C517·65PC

7217L45G
7217L45L
7217L45P
7217L55D
7217L55DB
7217L55G
7217L55GB
7217L55L
7217L55LB
7217L55P
7217L65D
7217L65DB
7217L65G
7217L65GB
7217L65L
7217L65LB
7217L65P

LOGIC DEVICES

lOT

LMA1009
LMA 1009DC-45
LMA 1009GC-45
LMA 1009DMB·55
LMA 1009GMB-55
LMA 10090C·75
LMA1009GC-75
LMA 1009DC·90
LMA 1009GC-90
LMA 1009DMB·95
LMA 1009GMB-95
LMA1009DMB·115
LMA1009GMB-115
LMA2009
LMA2009KC·45
LMA2009KMB·55
LMA2009KC-55
LMA2009KMB-65
LMA2009KC·75
LMA2009KC-90
LMA2009KMB-95
LMA2009KMB·115
LMA1010
LMA 101 OPC·45
LMA 101 ODC·45
LMA 101 OGC-45
LMA1010PC·55
LMA1010DC·55
LMA101OGC·55
LMA 101 ODBM·55
LMA 101 OGMB·55
LMA1010PC-65
LMA 101 OOC·65
LMA101OGC-65

7209
7209L45C
7209L45G
7209L55CB
7209L55GB
7209L65C
7209L65G
7209L65C
7209L65G
7209L75CB
7209L75GB
7209L75CB
7209L75GB
7209
7209L45L
7209L55LB
7209L45L
7209L55LB
7209L65L
7209L65L
7209L75LB
7209L75LB
7210
7210L45P
7210L45C
7210L45G
7210L55P
7210L55C
7210L55G
7210L55CB
7210L55GB
7210L65P
7210L65C
7210L65G

1.6

LOGIC DEVICES
(Con't)

lOT

LMA 101 OOMB-65
LMA 101 OGMB-65
LMA2010
LMA201OJC-45
LMA2010KC-45
LMA201OJC-55
LMA2010KC-55
LMA2010KMB·55
LMA201OJC-65
LMA2010KC-65
LMA2010KMB·65
LMU12
LMU12DC·45
LMU12DMB·55
LMU12DC-65
LMU12DMB·75
LMU12DC
LMU12DMB
LMU16
LMU16PC·45
LMU16DC-45
LMU16GC·45
LMU16PC-55
LMU16DC-55
LMU16GC·55
LMU16DMB·55
LMU 16GMB-55
LMU16PC·65
LMU16DC·65
LMU16GC-65
LMU16DMB·65
LMU 16GMB-65
LMU16PC
LMU160C
LMU16GC
LMU216
LMU216JC·45
LMU216KC-45
LMU216JC-55
LMU216KC-55
LMU216KMB·55
LMU216JC-65
LMU216KC-65
LMU216KMB-65
LMU17
LMU17PC·45
LMU17DC-45
LMU17GC-45
LMU17PC-55
LMU17DC-55
LMU17GC-55
LMU17DMB·55
LMU 17GMB-55
LMU17PC·65
LMU17DC-65

7210L65CB
7210L65GB
7210
7210L45J
7210L45L
7210L55J
7210L55L
7210L55LB
7210L65J
7210L65L
7210L65LB
7212
7212L45C
7212L55CB
7212L45C
7212L55CB
7212L70C
7212L90CB
7216
7216L45P
7216L45C
7216L45G
7216L55P
7216L55C
7216L55G
7216L55CB
7216L55GB
7216L65P
7216L65C
7216L65G
7216L55CB
7216L55GB
7216L65P
7216L65C
7216L65G
7216
7216L45J
7216L45L
7216L55J
7216L55L
7216L55LB
7216L65J
7216L65L
7216L65LB

7217
7217L45P
7217L45C
7217L45G
7217L55P
7217L55C
7217L55G
7217L55CB
7217L55GB
7217L65P
7217L65C

DIGITAL SIGNAL PROCESSING CROSS REFERENCE GUIDE

CYPRESS (Con't)

lOT

LMU17GC-65
LMU17DMB-65
LMU17GMB-65
LMU17PC
LMU17DC
LMU17GC
LMU217
LMU217JC-45
LMU217KC-45
LMU217JC-55
LMU217KC-55
LMU217KMB-55
LMU217JC-65
LMU217KC-65
LMU217KMB-65

7217L65G
7217L55CB
7217L55GB
7217L65P
7217L65C
7217L65G
7217
7217L45J
7217L45L
7217L55J
7217L55L
7217L55LB
7217L65J
7217L65L
7217L65LB

TRW

lOT

MPY012
MPY016
MPY016KJ1A
MPY016KJ1A1
MPY016KJ1C
MPY016KJ1C1
MPY016KJ1G
MPY016KJ1G1
TMC216H
TOC1009
TOC1010
TMC2009
TMC2010
TMC2110

7212
7216
7216L45CB
7216L45CB
7216L45C
7216L35C
7216L45C
7216L35C
7216
7209
7210
7209
7210
7210

II

1.6

2

TECHNOLOGY AND CAPABILITIES

I

IDT... LEADING THE CMOS FUTURE
A major revolution is taking place in the semiconductor
industry today. A new technology is rapidly displacing older
NMOS and bipolar technologies as the workhorse of the 80's
and beyond. That technology is high-speed CMOS. Integrated
Device Technology, a company totally predicated on and
dedicated to implementing high-performance CMOS products,
is on the leading edge of this dramatic change.
Beginning with the introduction of the industry's fastest
CMOS 2K x 8 static RAM, lOT has grown into a company with
multiple divisions producing a wide range of high-speed
CMOS circuits that are, in almost every case, the fastest
available. These advanced products are produced with lOT's
proprietary CEMOSTM technology, a twin-well, dry-etched,
stepper-aligned process utilizing progressively smaller
dimensions.
From inception, lOT's product strategy has been to apply
the advantages of it's extremely fast CEMOS technology to
produce the integrated circuit elements required to implement
high-performance digital systems. lOT's goal is to provide the
circuits necessary to create systems which are far superior to
previous generations in performance, reliability, cost weight
and size. Many of the company's innovative product designs
offer higher levels of integration, advanced architectures,
higher density packaging and system enhancement features
that are establishing tomorrow's industry standards. The
company is committed to providing its customers with an everexpanding series of these high-speed, lower-power IC solutions
to system deSign needs.
lOT's commitment, however, extends beyond state-of-theart technology and advanced products to providing the highest

2.1

level of customer service and satisfaction in the industry.
Producing products to exacting quality standards that provide
excellent, long-term reliability is given the same level of
importance and priority as device performance. lOT is also
dedicated to delivering these high-quality advanced products
on time. The company would like to be known not only for its
technological capabilities, but also for providing its customers
with quick, responsive and courteous service.
lOT's product families are available in both commercial and
mili1ary grades. As a bonus, commercial customers obtain the
benefits of mili1ary processing disciplines, established to meet
or exceed the stringent criteria of the applicable military
specifications.
lOT is the leading U.S. supplier of high-speed CMOS
circuits. The company's high-performance fast SRAM , FCT
logic family, high-density modules, FIFOs, complex logic
products, specialty memories, ECU/O BiCEMOSTM memories,
RISC subsystems, and the 32-bit RISC microprocessor family
complement each otherto provide high-speed CM OS solutions
to a wide range of applications and systems.
Dedicated to maintaining its leadership position as a stateof-the-art IC manufacturer, lOT will continue to focus on
maintaining its technology edge as well as developing a
broader range of innovative products. New products and
speed enhancements are continuously being added to each
of the existing product families and additional product lines will
be introduced. Contact your lOT field representative orfactory
marketing engineerto determine the latest product offerings.
If you're building state-of-the-art equipment,lDTwants to help
you solve some of your design problems.

I

IDT MILITARY AND DESC-SMD PROGRAM
lOT is a leading supplier of military, high-speed CMOS
circuits. The company's high-performance Static RAMs, FCT
Logic Family, Complex Logic (CLP), FIFOs, Specialty
Memories (SMP), ECL I/O BiCMOS Memories, 32-bit RISC
Microprocessor, RISC Subsystems and high-density
Subsystems Modules product lines complement each otherto
provide high-speed CMOS solutions to a wide range of
military applications and systems. Most of these product lines
offer Class B products which are fully compliant to the latest
revision of MIL-STD-883, Paragraph 1.2.1. In addition, lOT
offers Radiation Tolerant (RT), as well as Radiation Enhanced
(RE), products.
lOT has an active program with the Defense Electronic
Supply Center (DESC) to list all of lOT's military compliant
SMO

devices on Standard Military Drawings (SMD). The SMD
program allows standardization of militarized products and
reduction of the proliferation of non-standard source control
drawings. This program will go far toward reducing the need
for each defense contractor to make separate specification
control drawings for purchased parts. lOT plans to have
SMDs for many of its product offerings. Presently, lOT has 88
devices which are listed or pending listing. The devices are
from lOT's SRAM, FCT Logic family, Complex Logic (CLP),
FIFOs and Specialty Memories (SMP) product families. lOT
expects to add another 20 devices to the SMD program in the
near future. Users should contact either lOT or DESC for
current status of products in the SMD program.

SMO

SMO

SRAM

lOT

LOGIC

lOT

CLP

lOT

84036/0
5962-88740
84132/B
5962-86015/A
5962-86859
5962-86705/A
5962-85525/A
5962-88552
5962-88662
5962-88611
5962-88681/A
5962-88545
5962-88544
5962-88725/A
5962-89690
5962-89691
5962-89692
5962-89712

6116
6116LA
6167
7187
6198/7198/7188
6168
7164
71256L
71256S
71682L
71258S
71258L
71257L
71257S
6116
7164
7188
71982

39C10B & C
39C01
49C460A
39C60A
49C41 0
75C48S
75C58
75C458S
49C402/A
7216L
7217L
7210
49C402L
7320L
7321L
7383L
7209L

lOT

5962-86875/A
5962-87002/A
5962-88610/A
5962-88665/A

7130/7140
713217142
7133S/7143S
7133U7143L

FIFO

lOT

5962-87531
5962-86846/A
5962-88669
5962-89568
5962-89536
5962-89863
5962-89523
5962-89666
5962-89942
5962-89943
5962-89567

7201 LA
72404
7203S
7204L
7202L
7201S
72403L
7200L
72103L
72104L
7203L

54FCT244/A
54FCT245/A
54FCT299/A
54FCT373/A
54FCT374/A
54FCT377/A
54FCT138/A
54FCT240/A
54FCT273/A
54FCT861AlB
54FCT827 AlB
54FCT841 AlB
54FCT821 AlB
54FCT521/A
54FCT161/A
54FCT573/A
54FCT823A1B
54FCT163/A
54FCT825A1B
54FCT863A1B
54FCT520AlB
54FCT646A1B
54FCT139/A
54FCT824A1B
54FCT533/A
54FCT182/A
54FCT645A1B
54FCT640AlB
54FCT534/A
54FCT540/A
54FCT541/A
54FCT191/A
54FCT241/A
54FCT399/A
54FCT574/A
54FCT833A1B
54FCT845A1B
54FCT543/A

5962-87708/A
5962-88535
5962-88533/A
5962-88613
5962-88643
5962-88743
5962-XXXXX
5962-XXXXX
5962-89517
5962-86893
5962-87686
5962-88733
5962-XXXXX
5962-XXXXX
5962-XXXXX
5962-XXXXX
5962-XXXXX

SMP

5962-87630/B
5962-87629/C
5962-86862/A
5962-87644/A
5962-87628/C
5962-87627
5962-87654/A
5962-87655
5962-87656/A
5962-89533
5962-89506
5962-88575
5962-88608
5962-88543/A
5962-88640
5962-88639
5962-88656
5962-88657
5962-88674
5962-88661
5962-88736
5962-88775
5962-89508
5962-89665
5962-88651
5962-88652
5962-88653
5962-88654
5962-88655
5962-89767
5962-89766
5962-89733
5962-89732
5962-89652
5962-89513
5962-89731
5962-88675
5962-89730

2509 tbl 01

2.2

RADIATION HARDENED TECHNOLOGY
lOT manufactures and supplies radiation hardened products
for military/aerospace applications. Utilizing special processing
and starting materials, lOT's radiation hardened devices are
able to survive in hostile radiation environments. In total dose,
dose rate and environments where single event upset is of
concern, lOT products are designed to continue functioning
without loss of performance. lOT can supply all its products on
these processes. Total Dose radiation testing is performed in-

house on an ARACQR X-Ray system. External facilities are
utilized for device research on gamma cell, lINAC and other
radiation equipment. lOT has an on-going research and
development program for improving radiation handling
capabilities (See "lOT Radiation ToleranVEnhanced Products
for Radiation Environments" in Section 3) of lOT products/
processes.
•
•

2.3

lOT LEAOING.EOGE CEMOS TECHNOLOGY
and wide operating temperature range; it also achieves speed
and output drive equal or superior to bipolar Schottky TTL.
The last decade has seen development and production of four
"generations" of lOT's CEMOS technology with process
improvements which have reduced lOT's electrical effective
(Left) gate lengths by more than 50 percent from 1.3 microns
(millionths of a meter) in 1981 to 0.6 microns in 1989.

HIGH-PERFORMANCE CEMOS .
From lOT's beginnings in 1980, it has had a belief in and a
commitment to CMOS. The company developed a' highperformance version of CMOS, called enhanced CMOS
(CEMOS), that allows the design and manufacture of leadingedge components. It incorporates the best characteristics of
traditional CMOS, including low power, high noise immunity
CEMOSI

CEMOSII

A

C

CEMOSIII

CEMOSV

CEMOSVI

Calendar Year

1981

1983

1985

1987

1989

1990

Drawn
Feature Size

2.511

1.711

1.311

1.211

1.011

0.811

Left
Basic
Proces
Enhancements

1.311

1.111

0.911

Dual-well,
Wet Etch,
Projection
Aligned

Dry Etch,
Stepper

Shrink,
Spacer

0.811
Silicide,
BPSG,
BiCEMOS I

0.611

0.4511

BiCEMOS II

BiCEMOS III

2514 drw 01

CEMOS IV = CEMOS 111- scaled process optimized for high-speed logic.
Figure 1.

Continual advancement of CEMOS technology allows lOT
to implement progressively higher levels of integration and
achieve increasingly faster speeds maintaining the company's
established position as the leader in high-speed CMOS
integrated circuits. In addition, the fundamental process
technology has been extended to add bipolar elements to the
CEMOS platform. lOT's BiCEMOS process combines the
ultra-high speeds of bipolar devices with the lower power and
cost of CMOS, allowing us to build even faster components
than straight CMOS at a slightly higher cost.

•

"'II
I

t

.

11111

t
CEMOSI

CEMOSII

CEMOSIII

CEMOSV

1981

1983

1987

1989

SEM photos (miniaturization)

2514 drw 02

Figure 2. Flfteen-Hundred·Power Magnification Scanning Electron
Microscope (SEM) Photos of the Four Generations of rors CEMOS
Technology

2.4

-3V

II

NMOS
Potential

n-Substrate

+5V

CEMOSTM
2514drw04

2514 drw03

Figure 3. IDT CEMOS Device Cross Section

Figure 4. lOT CEMOS Built-In High Alpha Particle Immunity

ALPHA PARTICLES

Input/Output Pad

Random alpha particles can cause memory cells to
temporarily lose their contents orsuffer a "soft error." Traveling
with high energy levels, alpha particles penetrate deep into an
integrated chip. As they burrow into the silicon, they leave a
trail of free electron-hole pairs in their wake.
The cause of alpha particles is well documented and
understood in the industry. lOT has considered various
techniques to protectthe cells from this hazardous occurrence.
These techniques include dual-well structures (Figures 3 and
4) and a polymeric compound for die coating. Presently, a
polymeric compound is used in manyof lOT's SRAMs; however,
the specific techniques used may vary and change from one
device generation to the next as the industry and lOT improve
the alpha particle protection technology.

1,000

l-

.s<"
c

II900

Q)

ll~
(a)

t

Section A-A

l-

U
CD

I-

~

-

::J

n-Substrate

w _

t::

I-

Cl800
CI

-

a.

::J

.r:.

.B
j

e

1\,

700

I~
\,

~

1
01234567

(b) Collector Supply Voltage VCc (V)

Typical
2514 drw 05

Figure 5. IDT CEMOS latchup Suppression

LATCHUP IMMUNITY
A combination of careful design layout, selective use of
guard rings and proprietary techniques have resulted in virtual
elimination of latchup problems often associated with older
CMOS processes (Figure 5). The use of NPN and N-channel
I/O devices eliminates hole injection latchup. Double guard
ring structures are utilized on all input and output circuits to
absorb injected electrons. These effectively cut off the cu rrent
paths into the internal circuits to essentially isolate I/O circuits.
Compared to older CMOS processes which exhibit latchup
characteristics with trigger currents from 10-20mA, lOT
products inhibit latchup at trigger currents substantially greater
than this.

2.4

2

SURFACE MOUNT TECHNOLOGY
To take full advantage of the low-power aspect of CMOS,
and obtain two to three times the space savings, CMOS
products should be used as SMDs (surface mount devices).
However, most integrated circuits sold today are still packaged
in the traditional DIP (dual in-line package) configuration
because there is a tremendous support industry to handle
thru-board assembly.
Determined to utilize CMOS advantages, IDT re-invented
the DIP. This was accomplished by developing multilayered
substrates (either co-fired ceramics or glass filled epoxy FR4) with dual in-line (DIP) or single in-line (SIP) pins. An
advanced IR (InfraRed) reflow and vapor phase reflow surface
mount technology was also developed to produce the most
reliable solder connections available.

Products that are to be interconnected to form larger
electronic elements are electrically tested, environmentally
screened, performance selected and then thermally matched
to the appropriate ceramic or glass filled epoxy substrates.
After modular assembly, the finished product is 100% retested to ensure that it completely performs to the specifications
required.
As a result, IDT produces extraordinarily dense, highspeed combinations of monolithic ICs as complex subsystem
modular assemblies. These modules convert SMDs to userfriendly DIPs/SIPs providing customers with the density
advantages of surface mount in a format compatible with their
extensive, thru-board, assembly expertise.

2.5

STATE-OF-THE-ART FACILITIES AND CAPABILITIES
Integrated Device Technology is headquartered in Santa,
California - the heart of the "Silicon Valley." The company's
operations are housed in seven facilities totaling over 500,000
square feet. These facilities house all aspects of business
from research and development to design, wafer fabrication,
assembly, environmental screening, test and administration.
In-house capabilities include scanning electron microscope
(SEM) evaluation, particle impact noise detection (PIND),
plastic and hermetic packaging, military and commercial
testing, burn-in,life test and a full complement of environmental
screening equipment.
The over-200,000-square-foot corporate headquarters
campus is composed of four buildings. The largest facility on
this site is a 100,000 square foot, two-building complex. The
first building, a 60,000 square foot facility, is dedicated to the
Complex logic, Standard logic and RISC Microprocessor
product lines, as well as hermetic and plastic package
assembly, logiC products' test, burn-in, mark and QA, and a
reliability/failure analysis lab.
lOT's Packaging and Assembly Process Development
teams are located here. To keep pace with the development
of new products and to enhance the lOT philosophy of
"Innovation," these teams have ultra modern, integrated and
correspondingly sophisticated equipment and environments
at their disposal. All manufacturing is completed in dedicated
clean room areas (Class 10K minimum), with all preseal
operations accomplished under Class 100 laminar flow hoods.
Development of assembly materials, processes and
equipment is accomplished under a fully operational production
environment to ensure reliability and repeatable product. The
Hermetic Manufacturing and Process Development team is
currently producing custom products to the strict requirements
of Mil-STD-883. The fully automated plastic facility is cu rrently
producing high volumes of USA-manufactured product, while
developing state-of-the-art surface mount technology patterned
after MIL-STD-883.
The second building of the complex houses sales, marketing,
finance and MIS.
The RISC Subsystems and Subsystems Modules Divisions
are located behind the twO-building complex in a 54,000
square foot facility. Also located at this facility are Quality
Assurance and wafer fabrication services.
Directly across the street from the two-building complex is
a newly acquired 50,000 square foot facility that houses

2.6

administrative services, Northwest Area Sales, Human
Resources, International Planning and Shipping and Receiving
functions.
lOT's largest and newest facility, opened in 1990 in San
Jose, California, is a multi-purpose 150,000 square foot, ultra
modern technology development center. This facility houses
a 25,000 square foot, combined Class 1 (a maximum of one
particle per cubic foot of 0.2 micron or larger), sub-half-micron
R&D fabrication facility and a wafer fabrication area. This fab
supports both production volumes of lOT products, including
some next generation SRAMs, and the R&D efforts of the
technology development staff. Technology development efforts
targeted for the center include advanced silicon processing
and wafer fabrication techniques. A test area to support both
production and research is located on-site. The building is
also the new home of the FIFO and ECl product lines.
lOT's second largest facility is located in Salinas, California,
about an hour away from Santa Clara. This 95,000 square
foot facility, located on 14 acres, is the Static RAM Division
and Specialty Memory product line. Constructed in 1985, this
facility houses an ultra-modern 25,000 square foot highvolume wafer fabrication area measured at Class 2-to-3 (a
maximum of 2 to 3 particles per cubic foot of 0.2 micron or
larger) clean room conditions. Careful deSign and construction
of this fabrication area created a clean room environment far
beyond the 1985 average for U.S. fab areas. This made
possible the production of large volumes of high-density
submicron geometry, fast static RAMs. This facility also
houses shipping areas for lOT's leadership family of CMOS
static RAMs. This site will expand to accommodate a 250,000
square foot complex.
To extend these philosophies while maintaining strict control
of our processes, lOT has an operational Assembly and Test
facility located in Penang, Malaysia. This facility assembles
product to USA standards, with all assemblies done under
laminar flow conditions (Class 100) until the silicon is encased
in its final packaging. All products in this facility are
manufactured to the quality control requirements of Mil-STD883.
All of lOT's facilities are aimed at increasing our
manufacturing productivity to supply ever larger volumes of
high-performance, cost-effective leadership CMOS products.

2

SUPERIOR QUALITY AND RELIABILITY
Maintaining the highest standards of quality in the industry
on all products is the basis of Integrated Device Technology's
manufacturing systems and procedures. From inception,
quality and reliability are built into all of IDT's products. Quality
is "designed in" at every stage of manufacturing - as opposed
to being ''tested-in'' later - in order to ensure impeccable
performance.
Dedicated commitment to fine workmanship, along with
development of rigid controls throughout wafer fab, device
assembly and electrical test, create inherently reliable products.
Incoming materials are subjected to careful inspections. Quamy
monitors, or inspections, are performed throughout the
manufacturing flow.
IDT military grade monolithic hermetic products are designed
to meet or exceed the demanding Class B reliability levels of
MIL-STD-883 and MIL-M-38510, as defined by Paragraph
1.2.1 of MIL-STD-883.
Product flow and test procedures for all monolithic hermetic
military grade products are in accordance with the latest
revision and notice of MIL-STD-883. State-of-the-art production
techniques and computer-based test procedures are coupled
with tight controls and inspections to ensure that products
meet the requirements for 100% screening. Routine quality
conformance lot testing is performed as defined in MIL-STD883, Methods 5004 and 5005.

By maintaining these high standards and rigid controls
throughout every step of the manufacturing process, IDT
ensures that commercial, industrial and military grade products
consistently meet customer requirements for quality, reliability
and performance.

SPECIAL PROGRAMS
Class S. IDT also has all manufacturing, screening and
test capabilities in-house (except X-ray and some Group D
tests) to perform complete Class S processing per MIL-STD883 on all I DT products and has supplied Class S products on
several programs.
Radiation Hardened. IDT has developed and supplied
several levels of radiation hardened products for military/
aerospace applications to perform at various levels of dose
rate, total dose, single event upset (SEU), upset and latchup.
I DT products maintain nearly their same high-performance
levels built to these special process requirements. The
company has in-house radiation testing capability used both
in process development and testing of deliverable product.
I DT also has a separate group within the company dedicated
to supplying products for radiation hardened applications and
to continue research and development of process and products
to further improve radiation hardening capabilities.

2.7

QUALITY AND RELIABILITY

II

QSP-QUALITY, SERVICE AND PERFORMANCE
Ouality from the beginning, is the foundation for lOT's
commitment to supply consistently high-quality products to
our customers. lOT's quality commitment is embodied in its all
pervasive Constant Ouality Improvement (COl) program.
Everyone who influences the quality of the product-from the
designer to the shipping clerk-is committed to constantly
improving the product quality.

These systems and controls concentrate on COl byfocusing
on the following key elements:

LOGIC PRODUCTS DIVISION'S FOCUS

Standardization

'To make quantitative constant improvement in the quality
of our actions that result in the supply of leadership products
in conformance to the requirements of our customers."
lOT's Logic Products Division has dedicated its efforts to
constant quantitative improvements in quality. The result, a
supply of leadership products that conform to the requirements
of our customers.

LOGIC PRODUCTS DIVISION'S PRODUCT
ASSURANCE STRATEGY FOR CQI

Statistical Techniques
Using statistical techniques, including Statistical Process
Control (SPC) to determine whether the product!
processes are under control.

Implementing policies, procedures and measurement
techniques that are common across different operational
areas.

Documentation
Documenting and training in policies, procedures,
measurement techniques and updating through
characterization/ capability studies.

Productivity Improvement

Measurable standards are essential to the success of COL
All the processes contributing to the final quality of the product
need to be monitored, measured and improved upon through
the use of statistical tools.

USing constant improvement teams made up from
employees at all levels of the organization.

Leadership
Focusing on quality as a key business parameter and
strategic strength.

DEVELOPMENT

Total Employee Participation

I

Incorporating the COl program into the lOT Corporate
Culture.

FAB

I

PRODUCT FLOW

ASSEMBLY

Customer Service

I

Supporting the customer, as a partner, through
performance review and pro-active problem solving.

TEST

I
SHIP

People Excellence
Ourcustomers receive the benefit of our optimized systems.
Installed to enhance quality and reliability, these systems
provide accurate and timely reporting on the effectiveness of
manufacturing controls and the reliability and quality
performance of lOT logic products and services.

PRODUCT FLOW
Product quality starts here. lOT has mechanisms and
procedures in place that monitor and control the quality of our
development activities. From the calibration of design capture
libraries through process technology and product
characterization that establish whether the performance,
ratings and reliability criteria have been met. This includes
failure analysiS of parts thatwill improve the prototype product.
At the pre-production stage once again in-house qualification
tests assure the quality and reliability of the product. All
specifications and manufacturing flows are established and
personnel trained before the product is placed into productio n.

ORDER ENTRY

I
PRODUCTION CONTROL
SERVICE FLOW

Committing to growing, motivating and retaining people
through training, goal setting, performance measurement
and review.

I
SHIPPING

I

CUSTOMER SUPPORT

3.1

•

Manufacturing
To make CQI du ring the manufacturing stage, control items
are determined for major manufacturing conditions. Data is
gathered and statistical techniques are used to control specific
manufactu ring processes that affect the quality of the product.
In-process and final inspections are fed back to earlier
processes to improve product quality. All product is burnedin (where applicable) before 100% inspection of electrical
characteristics takes place.
Products which pass final inspection are then subject to
Quality Assurance and Reliability Tests. This data is used to
improve manufacturing processes and provide reliability
predictions of field applications.
Inventory and Shipping
Controls in shipping focus on ensuring parts are identified
and packaged correctly. Care is also taken to see that the
correct paperwork is present and the product being shipped
was processed correctly.

SERVICE FLOW
Quality not only applies to the product but to the quality -of
-service we give our customers. Services is also constantly
improved.
Order Procedures
Checks are made at the order entry stage to ensure the
correct processing ofthe Customer's product. Afterverification
and data entry the Acknowledgements (sent to Customers)
are again checked to ensure details are correct. As part of the
CQI program, the results of these verifications are analyzed
using statistical techniques and corrective actions are taken.
Production Control
Production Control (P.C.) is responsible for the flow and
logistics of material as it moves through the manufacturing
processes. The quality of the actions taken by P .C. greatly
impinges on the quality of service the customer receives.
Because many of our customers have implemented Just-inTime (JIT) manufacturing practices, IDT as a supplier also has

3.1

to adopt these same disciplines. As a result, employees
receive extensive training and the performance level of key
actions are kept under constant review. These key actions
include:
Quotation response and accuracy.
Scheduling response and accuracy.
Response and accuracy of Expedites.
Inventory, management, and effectiveness.
On time delivery.
Customer Support
I DT has a worldwide network of sales offices and Technical
Development Centers. These provide local customer support
on business transactions, and in addition, support customers
on applications information, technical services, benchmarking
of hardware solutions, and demonstration of various
Development Workstations.
The key to CQI is the timely resolution of defects and
implementation of the corrective actions. This is no more
important than when product failures are found by a
customer.When failures are found at the customer's incoming
inspection, in the production line, or the field application, the
Logic Products Division Quality Assurance group is the focal
point for the investigation of the cause of failure and
implementation of the corrective action. I DT constantly
improves the level of support we give our customers by
monitoring the response timeto customers that have detected
a product failure. Providing the customer with an analysis of
the failure, including corrective actions and the statistical
analysis of defects, brings CQI full circle-full support of our
customers and their designs with high-quality products.

SUMMARY
In 1990, IDT made the commitment to "Leadership through
Quality, Service, and Performance Products".
We believe by following that credo IDT and our cusotmers
will be successful in the coming decade. With the
implementation of the cal strategy within the Logic Products
Division, we will satisfy our goal...

"Leadership through Quality, Service and Performance
Products':

2

lOT QUALITY CONFORMANCE PROGRAM
A COMMITMENT TO QUALITY
Integrated Device Technology's monolithic and modular
assembly products are designed, manufactured and tested in
accordance with the strict controls and procedures required
by Military Standards. The documentation, design and
manufacturing criteria of the Quality and Reliability Assurance
Program were developed and are being maintained to the
most current revisions of MIL-3851 0 as defined by paragraph
1.2.1 of MIL-STO-883 and MIL-STD-883 requirements.
Product flow and test procedures for all Class B monolithic
hermetic Military Grade microcircuits are in full compliance
with paragraph 1.2.1 of MIL-STD-883. State-of-the-art
production techniques and computer-based test procedures
are coupled with stringent controls and inspections to ensure
that products meet the requirements for 100% screening and
quality conformance tests as defined in M IL-STD-883, Methods
5004 and 5005.
Product flow and test procedures for all plastic and
commercial hermetic products are in accordance with industry
practices for producing highly reliable microcircuits to ensure
that products meet the lOT requirements for 100% screening
and quality conformance tests.
By maintaining these high standards and rigid controls
throughout every step of the manufacturing process, lOT
ensures that our products consistently meet customer
requirements for quality, reliability and performance.

4.

Wire Bond Monitor: Product samples are routinely
subjected to a strength test per Method 2011, Condition
D, to ensure the integrity of the lead bond process.

5.

Pre-Gap Visual: Before the completed package is
sealed, 100% of the product is visually inspected to
Method 2010, Condition B criteria.

6.

Environmental Conditioning: 100% of the sealed
product is subjected to environmental stress tests.
These thermal and mechanical tests are designed to
eliminate units with marginal seal, die attach or lead
bond integrity.

7.

Hermetic Testing: 100% of the hermetic packages
are subjected to fine and gross leak seal tests to
eliminate marginally sealed units or units whose
seals may have become defective as a result of
environmental conditioning tests.

8.

Pre-Burn-In Electrical Test: Each product is 100%
electrically tested at an ambient temperature of +25°C
to lOT data sheet or the customer specification.

9.

Burn-In: 100% of the Military Grade product is
burned-in under dynamic electrical conditions to the
time and temperature requirements of Method 1015,
Condition D. Except for the time, Commercial Grade
product is burned-in as applicable to the same
conditions as Military Grade devices.

10.

Post-Burn-In Electrical: After burn-in, 100% of the
Class B Military Grade product is electrically tested to
lOT data sheet or customer specifications over the
-55°C to + 125°C temperature range. Commercial
Grade products are sample tested to the applicable
temperature extremes.

11.

Mark: All product is marked with product type and lot
code identifiers. MIL-STD-883 compliant Military
Grade products are identified with the required
compliant code letter.

12.

Quality Conformance Tests: Samples ofthe Military
Grade product which have been processed to the
100% screening tests of Method 5004 are routinely
subjected to the quality conformance requirements of
Method 5005.

SUMMARY
Monolithic Hermetic Package Processing FloW205kg)

I
lOT SPEC

Q

I

LEAD BOND PULL
TEST SAMPLE

2011

(>300grams)

I
2010

CONDo B

I
PRE·CAP VISUAL
SAMPLE

2010

CONDo B

I
lOT SPEC

I
lOT SPEC PROVIDES LOT
I
TRACEABILITY
1010 CONDo C, 10 cycles
I -65°C TO + 150°C
2001 CONDo E, Y1 Direction
>30kg (PKG < 5g)
>20kg (PKG ~ 5g)

TEMP CYCLE
CENTRIFUGE

I

FINE LEAK TEST

1014 CONDo A or B,
I <500 X 10-8 ATM/CC/SECo
1014 CONDo C

GROSS LEAK TEST

I
lOT SPEC

FiNE LEAK:
Q

HERMETICITY SAMPLE:
(SEE NOTE 3)

CONDo A or B
1014 <500 X 10-8
I ATM/CC/SECo
lOT SPEC

GROSS LEAK:
CONDo C

I

PRE BURN·IN
ELECTRICAL TEST

5004
~

DC, AC, FUNCTIONAL @ +25°C
(SEE NOTE 2)

SEE FINAL PROCESSING FLOW FOR REMAINDER OF OPERATIONS AND NOTES
2502 drw 01

302

SUMMARY
Monolithic Plastic Package Processing Flow
Refer to the Monolithic Plastic Package Processing Flow
diagram. All test methods refer to MIL-STD-883 unless
otherwise stated.
1.
Wafer Fabrication: Humidity, temperature and
particulate contamination levels are controlled and
maintained according to criteria patterned after Federal
Standard 209, Clean Room and Workstation
Requirements. All critical workstations are maintained
at Class 100 levels or better.
Topside silicon nitride paSSivation is all applied to all
wafers for better moisture barrier characteristics.

6.

Post Mold Cure: Plastic encapsulated devices are
baked to ensure an optimum plastic seal so as to
enhance moisture barrier characteristics.

7.

Pre-Burn-In Electrical: Each product is 100%
electrically tested at an ambient temperature of +25°C
to lOT data sheet or the customer specification.

8.

Burn-In: Except for MSI Logic family devices where
it may be obtained as an option, all Commercial
Grade plastic package products are burned-in 16
hours at + 125°C (or equivalent), utilizing the same
burn-in conditions as the Military Grade product.

9.

Post-Burn-In Electrical: After burn-in, 100% of the
plastic product is electrically tested to lOT data sheet
or customer specifications at the maximum
temperature extreme. The minimum temperature
extreme is tested periodically on an audit basis.

10.

Mark: All product is marked with product type and lot
code identifiers.

11.

Quality Conformance Inspection: Samples of the
plastiC product which have been processed to the
100% screening requirements are subjected to the
Periodic Quality Conformance Inspection Program.
Where indicated, the test methods are patterned after
MIL-STO-883 criteria.

Wafers from eachwaferfabrication area are subjected
to Scanning Electron Microscope analysis on a periodic
basis.
2.

Ole-Sort Visual Inspection: Wafers are 100%
visually inspected to strict lOT defined internal
criteria.

3.

Die Push Test: To ensure die attach integrity,
product samples are routinely subjected to die push
tests.

4.

Wire Bond Monitor: Product samples are routinely
subjected to wire bond pull tests to ensu re the integrity
of the lead bond process.

5.

Pre-Cap Visual: Before the package is molded,
100% of the product is visually inspected to criteria
patterned afterMIL-STO-883, Method 201 0, Condition
B.

3.2

3

II

Monolithic Plastic Package Processing Flow

Q

OPTICAL INSPECTION SAMPLE

Q

DIE ATIACH PUSH TEST SAMPLE

Q

PRE-CAP OPTICAL SAMPLE INSPECTION

CHEMICAL DEFLASH

MECHANICAL DEFLASH AND TRIM

LEAD FORMISINGULATION
OPEN/SHORT TEST SAMPLE

BURN-IN BIASED/DYNAMIC AT +125'C}
160 HRS. MAXIMUM TO 16 HRS.
MINIMUM (OR EQUIVALENT) ON ALL
PRODUCTS EXCEPT MSILOGIC
FAMILY DEVICES (FCT, FCT-T and FBT),
ON WHICH IT MAY BE OBTAINED AS
AN OPTION.

PRE-BURN-IN ELECTRICAL TEST +25'C (SEE NOTE 2)

POST BURN-IN ELECTRICAL TEST +70°C (SEE NOTE 2)
PDA
Q

S10%

ELECTRICAL TEST QUALITY SAMPLE +70°C (SEE NOTE 2)

NOTE:
1. All screens are 100% unless otherwise noted.
2. All electrical test programs are per the applicable lOT test specification.
3. lOT performs a 100% electrical test at +25°C with a 5% PDA limit at this point.
4.
= Quality sample inspection.

@

2502 drw 02

3.2

4

Monolithic Hermetic Package Final Processing Flow
Commercial

Operation

MIL·STD·B83
Test Method

Military
Compliant
Class B

Military
Temp. Range

Commercial
Temp. Range

100%
16 to 160 Hours

100%
16t0160 Hours

Burn-In

1015/0 at +125°C
Min. or Equivalent

100%
160 Hours

Post Burn-In Electrical: Static (OC). Functional and
Switching (AC)(2)

lOT Spec.

100%
+25. -55 and
+125°C

Percent Oefective Allowed (POA)(4)

5004 or lOT Spec.

5%

10%

10%

Group A Electrical: Static (OC). Functional and
Switching (AC)(2)

5005 and lOT Spec.

Sample
-55 and + 125°C

Sample
+125°C

Sample
+70°C

Mark/Lead Straighten

lOT Spec.

100%

100%

100%

+25°C Electrical(2)

lOT Spec.

100%(5)

100%

100%

100%

100%

Final VisuallPack

lOT Spec.

100%

Quality Conformance Inspection

5005 (Group B. C. 0)

Yes

Quality Shipping Inspection
(Visual/Plant Clearance)

lOT Spec.

Sample

100%
+125°C

100%
+70°C

II

-

-

Sample

Sample
25051b101

NOTES:
1. All screens are 100% unless otherwise noted.
2. All electrical test programs are per the applicable IDT test specification.
3. This hermeticity sample is performed after all lead finish operations.
4. If a lot fails the 5% PDA but is ~1 0%, the lot may be resubmitted to burn-in one time only to the same time and temperature conditions as first submission.
The subsequent post burn-in electrical test at +25°C will be performed to a PDA of 3%.
5. IDT performs a 100% electrical test at +25°C with a 2% PDA limit at this point to satisfy group A requirements, and considers this to be equivalent to the
group A requirement of an LTPD of 2, with an accept number of O. If a lot fails the 2% PDA limit, it may be rescreened one time only to a tightened PDA
limit of 1.5%.
6.
= Quality sample inspection.

@

3.2

5

RADIATION TOLERANT/ENHANCED/HARDENED PRODUCTS FOR
RADIATION ENVIRONMENTS
Neutron Irradiation will cause structural damage to the
silicon lattice which may lead to device leakage and, ultimately,
functional failure.

INTRODUCTION
The need for high-performance CMOS integrated circuits
in military and space systems is more critical today than ever
before. The low power dissipation that is achieved using
CMOS technology, along with the high complexity and density
levels, makes CMOS the nearly ideal component for all types
of applications.
Systems designed for military or space applications are
intended for environments where high levels of radiation may
be encountered. The implication of a device failure within a
military or space system clearly is critical. IDT has made a
significant contribution toward providing reliable radiationtolerant systems by offering integrated circuits with enhanced
radiation tolerance. Radiation environments, IDT process
enhancements and device tolerance levels achieved are
described below.

RadIation
Category

THE RADIATION ENVIRONMENT
There are four different types of radiation environments
that are of concern to builders of military and space systems.
These environments and their effects on the device operation,
summarized in Figure 1, are as follows:
Total Dose Accumulation refers to the total amount of
accumulated gamma rays experienced by the devices in the
system, and is measured in RADS (SI) for radiation units
experienced at the silicon level. The physical effect of gamma
rays on semiconductor devices is to cause threshold shifts (Vt
shifts) of both the active transistors as well as the parasitic field
transistors. Threshold voltages decrease as total dose is
accumulated; at some point, the device will begin to exhibit
parametric failures as the input/output and supply currents
increase. At higher radiation accumulation levels, functional
failures occur. In memory circuits, however, functional failures
due to memory cell failure often occur first.
Burst Radiation or Dose Rate refers to the amount of
radiation, usually photons or electrons, experienced by the
devices in the system due to a pulse event, and is measured
in RADS (SI) per second. The effect of a high dose rate or
burst of radiation on CMOS integrated circuits is to cause
temporary upset of logic states and/or CMOS latch-up. Latchup can cause permanent damage to the device.
Single Event Upset (SEU) is a transient logic state change
caused by high-energy ions, such as energetic cosmic rays,
striking the integrated circuits. As the ion passes through the
silicon, charge is either created through ionization or direct
nuclear collision. If collected by a circuit node, this excess
charge can cause a change in logic state of the circuit.
Dynamic nodes that are not actively held at a particular logic
state (dynamic RAM cells for example ) are the most susceptible.
These upsets are transient, but can cause system failures
known as "soft errors."

PrImary
Particle

Source

Effect

Total Dose

Gamma

Space or
Nuclear
Event

Permanent

Dose Rate

Photons

Nuclear
Event

Temporary
Upset of Logic
State or
Latch-up

SEU

Cosmic
Rays

Space

Temporary
Upset of
Logic State

Neutron

Neutrons

Nuclear
Event

Device Leakage
Due to Silicon
Lattice Damage
2510 drw 01

Figure 1.

DEVICE ENHANCEMENTS
Of the four radiation environments above, IDT has taken
considerable data on the first two, Total Dose Accumulation
and Dose Rate. I DT has developed a process that significantly
improves the radiation tolerance of its devices within these
environments. Prevention of SEU failures is usually
accomplished by system-level considerations, such as Error
Detection and Correction (EDC) circuitry, since the occurrence
of SEUs is not particularly dependent on process technology.
Through IDT's customer contracts, SEU has been gathered
on some devices. Little is yet known about the effects of
neutron-induced damage. For more information on SEU
testing, contact IDT's Radiation Hardened Product Group.
Enhancements to IDT's standard process are used to
create radiation enhanced and tolerant processes. Field and
gate oxides are "hardened"to make the device less susceptible
to radiation damage by modifying the process architecture to
allow lowertemperature processing. Device implants and Vts
adjustments allow more Vt margin. In addition to process
changes, IDTs radiation enhanced process utilizes epitaxial
substrate material. The use of epi substrate material provides
a lower substrate resistance environment to create latCh-Up
free CMOS structures.

3.3

RADIATION HARDNESS CATEGORIES
Radiation Enhanced ('RE) or Radiation Tolerant ('RT)
versions of IDT products follow IDT's military product data
sheets whenever possible (consult factory). IDT's Total Dose
Test plan exposes a sample of die on a wafer to a particular
Total Dose level via ARACOR X-Ray radiation. This Total
Dose Test plan qualifies each 'RE or 'RTwaferto a Total Dose
level. Only wafers with sampled die that pass Total Dose level
tests are assembled and used for orders (consult factory for
more details on Total Dose sample testing). With regard to
Total Dose testing, clarifications/exceptions to MIL-STD-883,
Methods 5005 and 1019 are required. Consult factory for
more details.
The 'RE and 'RT process enhancements enable IDT to
offer integrated circuits with varying grades of radiation
tolerance or radiation "hardness".
• Radiation Enhanced process uses Epi wafers and is able
to provide Logic devices that can be Total Dose qualified to
10K RADs (Si) or greater by IDT's ARACOR X-Ray Total
Dose sample die test plan (Total Dose levels require
negotiation, consult factory for more details).
• Radiation Tolerant Logic product uses standard wafer/
process material that is qualified to 10K RADs (Si) Total
Dose by I DT's ARACOR X-Ray Total Dose sample die test
plan.

3.3

Integrated Device Technology can provide Radiation
Tolerant/Enhanced versions of all Logic product types (some
speed grades may not be available as 'RE).
Please contact your IDT sales representative or factory
marketing to determine availability and price of any IDT
product processed in accordance with one of these levels of
radiation hardness.

CONCLUSION
There has been widespread interest within the military and
space community in IDT's CMOS product line for its radiation
hardness levels, as well as its high-performance and low
power dissipation. To serve this growing need for CMOS
circuits that must operate in a radiation environment, IDT has
created a separate group within the company to concentrate
on supplying products for these applications.Continuing
research and development of process and products, including
the use of in-house radiation testing capability, will allow
Integrated Device Technology to offer continuously increasing
levels of radiation-tolerant solutions.

2

II

PACKAGE DIAGRAM OUTLINES

II

THERMAL PERFORMANCE CALCULATIONS FOR lOT'S PACKAGES
Since most of the electrical energy consumed by
microelectronic devices eventually appears as heat, poor
thermal performance of the device or lack of management of
this thermal energy can cause a variety of deleterious effects.
This device temperature increase can exhibit itself as one of
the key variables in establishing device performance and long
term reliability; on the other hand, effective dissipation of
internally generated thermal energy can, if properly managed,
reduce the deleterious effects and improve component
reliability.
A few key benefits of lOT's enhanced CEMOSTM process
are: low power dissipation, high speed, increased levels of
integration, wider operating temperature ranges and lower
quiescent power dissipation. Because the reliability of an
integrated circuit is largely dependent on the maximum
temperature the device attains during operation, and as the
junction stability declines with increases in junction temperature
(TJ), it becomes increasingly important to maintain a low (TJ).
CMOS devices stabilize more quickly and at greatly lower
temperature than bipolar devices under normal operation.
The accelerated aging of an integrated circuit can be expressed
as an exponential function of the junction temperature as:
tA = to exp

[~
k

Tightly controlled the assembly procedures to meet or
exceed the stringent criteria of MIL-STD-883 to ensure
maximum heat transfer between die and packaging
materials.
The following figures graphically illustrate the thermal values
of lOT's current package families. Each envelop (shaded
area) depicts a typical spread of values due to the influence of
a number of factors which include: circuit size, package cavity
size and die attach integrity. The following range of values are
to be used as a comprehensive characterization of the major
variables rather than single point of reference.
When calculating junction temperature (TJ), it is necessary
to know the thermal resistance of the package (SJA) as
measured in "degree celsius perwatt". With the accompanying
data, the following equation can be used to establish thermal
performance, enhance device reliability and ultimately provide
you, the user, with a continuing series of high-speed, lowpower CMOS solutions to your system design needs.
SJA = [TJ - TA]/P
TJ = TA + P[SJA] = TA + P[8JC + eCA]
where

(~-~\J

,TO

4.

TJ)

SJc=TJ-Tc

SCA= Tc- TA

P

P

where
tA
lifetime at elevated junction (TJ) temperature
to
normal lifetime at normal junction (TO) temperature
Ea
activation energy (ev)
k
Boltzmann's constant (8.617 x 10-5ev/k)
i.e. the lifetime of a device could be decreased by a factor of
2 for every 10°C increase temperature.
To minimize the deleterious effects associated with this
potential increase, lOT has:
1. Optimized our proprietary low-power CEMOS
fabrication process to ensure the active junction
temperature rise is minimal.
2. Selected only packaging materials that optimize heat
dissipation, which encourages acoolerrunning device.
3. Physically designed all package components to
enhance the inherent material properties and to take
full advantage of heat transfer and radiation due to
case geometries.

Ref. MIL-STD-883C, Method 1012.1
JEDEC ENG. Bulletin No. 20, January 1975
1986 Semi. Std .. Vol. 4, Test Methods G30--86, G32--86.

4.1

S
J
P
TA
TJ
Tc
SCA

SJC

SJA

Thermal resistance
Junction
Operational power of device (dissipated)
Ambient temperature in degree celsius
Temperature of the junction
Temperature of case/package
Case to Ambient, thermal resistance-usually a
measure of the heat dissipation due to natural or
forced convection, radiation and mounting
techniques.
Junction to Case, thermal resistance-usually
measured with reference to the temperature at a
specific point on the package (case) surface.
(Dependent on the package material properties
and package geometry.)
Junction to Ambient, thermal resistance--usually
measured with respect to the temperature of a
specified volume of still air. (Dependent on SJC +
SJA which includes the influence of area and
environmental condition.)

II

100
90
80
70

t:

100
90
80
70
60
50
~ 40
30
20
10

t:
~

60

~ !~
30
20
10
OL-J-J--L-L-L~~-L-L~~~~-U

t:

60

~ 50
~ 40
30
20
10

~~MeJC~/~-Z

0

16 20 24 28 32 36 40 44 48 52 56 60 64 68
LEAD COUNT
Thermal Resistance of Ceramic DIP Packages
100
90
80
70

~///h
1620242832364044485256606468
LEAD COUNT
Thermal Resistance of PLCC/SOIC Packages

100
90
80
70
60
50
~ 40
30
20
10

~

t:
~

~0ZV///Z

~/I///////h

72ZZ/eJc0'/7a?/~

O~~~~~~~~~~~~~~~

16 20 24 28 32 36 40 44 48 52 56 60 64 68
LEAD COUNT
Thermal Resistance of Plastic DIP Packages

I-

~

16 20 24 28 32 36 40 44 48 52 56 60 64 68
LEAD COUNT
Thermal Resistance of Ceramic Sidebraze Packages

100
90
80
70
60

t:

~

50
~ 40
30
20
10

30
20
10

O L -_ _J -_ _- L_ _

80

~

_ _- L_ _

~

__

~

_ __ L

100

120 140 160 180 200
LEAD COUNT
Thermal Resistance of PPGA Packages

11x11 12x12 13x1314x14 15x1516x1617x17
PIN MATRiX
PGA Thermal Resistance

100~--------------------------~

I-

~

90
80
70
60

50
~ 40
30
20
10
OL-~-L-L-L-L-L~~-L-L-L-L~-W

16 20 24 28 32 36 40 44 48 52 56 60 64 68
LEAD COUNT
Thermal Resistance of Ceramic Leadless Chip Carrier (LCC) Packages

4.1

2512 drw 01

2

PACKAGE DIAGRAM OUTLINE INDEX
PKG.
P16-1
P18-1
P2Q-1
P22-1
P24-1
P24-2
P28-1
P28-2
P32-1
P32-2
P4Q-1
P48-1
P64-1

DESCRIPTION
16-Pin Plastic DIP
18-Pin Plastic DIP
2Q-Pin Plastic DIP
22-Pin Plastic DIP
24-Pin Plastic DIP
24-Pin Plastic DIP
28-Pin Plastic DIP
28-Pin Plastic DIP
32-Pin Plastic DIP
32-Pin Plastic DIP
4Q-Pin Plastic DIP
48-Pin Plastic DIP
64-Pin PlastiC DIP

016-1
018-1
020.-1
022-1
024-1
024-2
028-1
028-2
028-3
032-1
040.-1
040.-2

16-Pin CERDIP
18-Pin CERDIP
2Q-Pin CERDIP
22-Pin CERDIP
24-Pin CERDIP
24-Pin CERDIP
28-Pin CERDIP
28-Pin CERDIP
28-Pin CERDIP
32-Pin CERDIP
4Q-Pin CERDIP
4Q-Pin CERDIP

C2Q-1
C22-1
C24-1
C24-2
C28-1
C28-2
C28-3
C32-1
C32-2
C32-3
C4Q-1
C48-1
C48-2
C64-1
C64-2
C68-1

2Q-Pin Sidebraze DIP (30.0. mil) .................................................................................................... 3
22-Pin Sidebraze DIP (30.0. mil) .................................................................................................... 3
24-Pin Sidebraze DIP (30.0. mil) .................................................................................................... 3
24-Pin Sidebraze DIP (60.0. mil) .................................................................................................... 5
28-Pin Sidebraze DIP (30.0. mil) .................................................................................................... 3
28-Pin Sidebraze DIP (40.0. mil) ....................................................................................................4
28-Pin Sidebraze DIP (60.0. mil) ....................................................................................................5
32-Pin Sidebraze DIP (60.0. mil) .................................................................................................... 5
32-Pin Sidebraze DIP (40.0. mil) ....................................................................................................4
32-Pin Sidebraze DIP (30.0. mil) ....................................................................................................3
4Q-Pin Sidebraze DIP (60.0. mil) .................................................................................................... 5
48-Pin Sidebraze DIP (40.0. mil) ....................................................................................................4
48-Pin Sidebraze DIP (60.0. mil) .................................................................................................... 5
64-Pin Sidebraze DIP (90.0. mil) .................................................................................................... 6
64-Pin Topbraze DIP (90.0. mil) ..................................................................................................... 7
68-Pin Sidebraze DIP (60.0. mil) ....................................................................................................5

PG68-2
PG84-2
PG2Q8-2

68-Lead Plastic Pin Grid Array (cavity up) ....................................................................................43
84-Lead Plastic Pin Grid Array (cavity up) ....................................................................................43
2Q8-Lead Plastic Pin Grid Array (cavity up) ..................................................................................43

G68-1
G68-2
G84-1
G84-2
G84-3

68-Lead
68-Lead
84-Lead
84-Lead
84-Lead

Pin
Pin
Pin
Pin
Pin

(30.0.
(30.0.
(30.0.
(30.0.
(30.0.
(60.0.
(60.0.
(30.0.
(60.0.
(30.0.
(60.0.
(60.0.
(90.0.

mil)
mil)
mil)
mil)
mil)
mil)
mil)
mil)
mil)
mil)
mil)
mil)
mil)

PAGE
.......................................................................................................... 29
.......................................................................................................... 30.
..........................................................................................................30.
.......................................................................................................... 29
.......................................................................................................... 30.
.......................................................................................................... 31
..........................................................................................................31
.......................................................................................................... 29
..........................................................................................................31
.......................................................................................................... 29
..........................................................................................................31
.......................................................................................................... 31
.......................................................................................................... 31

(30.0. mil) .............................................................................................................. 1
(30.0. mil) .............................................................................................................. 1
(30.0. mil) .............................................................................................................. 1
(30.0. mil) .............................................................................................................. 1
(30.0. mil) .............................................................................................................. 1
(60.0. mil) .............................................................................................................. 2
(60.0. mil) .............................................................................................................. 2
(wide body) ......................................................................................................... 2
(30.0. mil) .............................................................................................................. 1
(wide body) ......................................................................................................... 2
(60.0. mil) .............................................................................................................. 2
(wide body) ......................................................................................................... 2

Grid
Grid
Grid
Grid
Grip

Array
Array
Array
Array
Array

(cavity up) ................................................................................................ 19
(cavity down) ........................................................................................... 25
(cavity up -12 x 12 grid) ....................................................................... 20.
(cavity down) ........................................................................................... 26
(cavity up - 11 x 11 grid) ....................................................................... 21

4.2

II

PKG.
G84-4
G108-1
G144-1
G144-2
G208-1

DESCRIPTION
PAGE
84-Lead Pin Grid Array (cavity down - MIPS) ........................................................................... 27
108-Lead Pin Grid Array (cavity up) ............................................................................................ 22
144-Lead Pin Grid Array (cavity down) ....................................................................................... 28
144-Lead Pin Grid Array (cavity up) ............................................................................................ 23
208-Lead Pin Grid Array (cavity up) ............................................................................................ 24

S016-1
S016-2
S016-5
S016-6
S018-1
S018-6
S020-1
S020-2
S020-5
S020-6
S024-2
S024-3
S024-4
S024-5
S024-6
S028-2
S028-3
S028-4
S028-5
S028-6
S032-2
S048-1
S056-1

16-Pin Small Outline IC (gull wing) ............................................................................................. 32
16-Pin Small Outline IC (J-bend) ................................................................................................ 35
16-Pin Small Outline IC (EIAJ _ .0315 pitch) ............................................................................ 34
16-Pin Small Outline IC (EIAJ - .050 pitch) .............................................................................. 34
18-Pin Small Outline IC (gull wing) ............................................................................................. 32
18-Pin Small Outline IC (EIAJ - .050 pitch) .............................................................................. 34
20-Pin Small Outline IC (J-bend) ................................................................................................ 35
20-Pin Small Outline IC (gull wing) ............................................................................................. 32
20-Pin Small Outline IC (EIAJ - .0315 pitch) ............................................................................ 34
20-Pin Small Outline IC (EIAJ - .050 pitch) .............................................................................. 34
24-Pin Small Outline IC (gull wing) ............................................................................................. 32
24-Pin Small Outline IC (gull wing) ............................................................................................. 32
24-Pin Small Outline IC (J-bend) ................................................................................................ 35
24-Pin Small Outline IC (EIAJ - .0315 pitch) ............................................................................ 34
24-Pin Small Outline IC (EIAJ - .050 pitch) .............................................................................. 34
28-Pin Small Outline IC (gull wing) ............................................................................................. 33
28-Pin Small Outline IC (gull wing) ............................................................................................. 33
28-Pin Small Outline IC (J-bend --' 350 mil) ............................................................................... 36
28-Pin Small Outline IC (J-bend - 300 mil) ............................................................................... 36
28-Pin Small Outline IC (EIAJ - .050 pitch) .............................................................................. 34
32-Pin Small Outline IC (J-bend) ................................................................................................ 36
48-Pin Small Outline IC (SSOP - gull wing) .............................................................................. 37
56-Pin Small Outline IC (SSOP - gull wing) .............................................................................. 37

J18-1
J20-1
J28-1
J32-1
J44-1
J52-1
J68-1
J84-1

18-Pin
20-Pin
28-Pin
32-Pin
44-Pin
52-Pin
68-Pin
84-Pin

Plastic Leaded
Plastic Leaded
Plastic Leaded
Plastic Leaded
Plastic Leaded
Plastic Leaded
Plastic Leaded
Plastic Leaded

L20-1
L20-2
L22-1
L24-1
L28-1
L28-2
L32-1
L44-1
L48-1
L52-1
L52-2
L68-1
L68-2

20-Pin
20-Pin
22-Pin
24-Pin
28-Pin
28-Pin
32-Pin
44-Pin
48-Pin
52-Pin
52-Pin
68-Pin
68-Pin

Leadless Chip Carrier (rectangular) ................................................................................ 18
Leadless Chip Carrier (square) ....................................................................................... 16
Leadless Chip Carrier (rectangular) ................................................ ,............................... 18
Leadless Chip Carrier (rectangular) ................................................................................ 18
Leadless Chip Carrier (square) ....................................................................................... 16
Leadless Chip Carrier (rectangular) ................................................................................ 18
Leadless Chip Carrier (rectangular) ................................................................................ 18
Leadless Chip Carrier (square) ....................................................................................... 16
Leadless Chip Carrier (square) ....................................................................................... 16
Leadless Chip Carrier (square) ....................................................................................... 17
Leadless Chip Carrier (square) ....................................................................................... 17
Leadless Chip Carrier (square) ....................................................................................... 17
Leadless Chip Carrier (square) ....................................................................................... 17

Chip
Chip
Chip
Chip
Chip
Chip
Chip
Chip

Carrier (rectangular) ...................................................................... .42
Carrier (square) .............................................................................. 41
Carrier (square) .............................................................................. 41
Carrier (rectangular) ...................................................................... .42
Carrier (square) .............................................................................. 41
Carrier (square) .............................................................................. 41
Carrier (square) .............................................................................. 41
Carrier (square) .............................................................................. 41

4.2

2

PKG.
E16-1
E20-1
E24-1
E28-1
E28-2

DESCRIPTION
16-Lead CERPACK
20-Lead CERPACK
24-Lead CERPACK
28-Lead CERPACK
28-Lead CERPACK

PAGE
.................................................................................................................... 13
.................................................................................................................... 13
.................................................................................................................... 13
.................................................................................................................... 13
.................................................................................................................... 13

CQ68-1
CQ84-1

68-Lead CERQUAD (straight leads) ........................................................................................... 14
84-Lead CERQUAD (J-bend) ..................................................................................................... 15

F20-1
F20-2
F24-1
F28-1
F28-2
F48-1
F64-1
F68-1
F84-1
F172-1

20-Lead Flatpack .........................................................................................................................8
20-Lead Flatpack (.295 body) ......................................................................................................8
24-Lead Flatpack .........................................................................................................................8
28-Lead Flatpack ......................................................................................................................... 8
28-Lead Flatpack .........................................................................................................................8
48-Lead Quad Flatpack ...............................................................................................................9
64-Lead Quad Flatpack ...............................................................................................................9
68-Lead Quad Flatpack .............................................................................................................. 10
84-Lead Quad Flatpack (cavity down) ........................................................................................ 11
172-Lead Quad Flatpack (MIPS) ................................................................................................ 12

PQ80-2
PQ100-1
PQ100-2
PQ120-2
PQ128-2
PQ132-1
PQ144-2
PQ160-2
PQ184-2
PQ208-2

80-Lead Plastic Quad Flatpack (lEAH) ....................................................................................... 39
100-Lead Plastic Quad Flatpack (JEDEC) .................................................................................. 28
100-Lead Plastic Quad Flatpack (EIAJ) ...................................................................................... 39
120-Lead Plastic Quad Flatpack (EIAJ) ...................................................................................... 39
128-Lead Plastic Quad Flatpack (EIAJ) ...................................................................................... 39
132-Lead Plastic Quad Flatpack (JEDEC) .................................................................................. 38
144-Lead Plastic Quad Flatpack (EIAJ) ......................................................................................40
160-Lead Plastic Quad Flatpack (EIAJ) ..................................................................................... .40
184-Lead Plastic Quad Flatpack (EIAJ) ...................................................................................... 40
208-Lead Plastic Quad Flatpack (EIAJ) ..................................................................................... .40

4.2

II

3

PACKAGE DIAGRAM OUTLINES
IDtell'ted Denoe TechnololY. Inc.

DUAL IN-LINE PACKAGES

L

t--

F===============~

NOTES:
1. ALL DIMENSIONS ARE IN INCHES. UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. THE MINIMUM UMIT FOR DIMENSION b1 MAY BE .023 FOR CORNER LEADS.

16-28 LEAD CERDIP (300 MIL)
OWG

#

1# OF LDS (N)
SYMBOL
A
b
b1
C
D
E
E1

e
L

L1
Q

S
S1

ex

016-1
16
MIN MAX
.105 .175
.015 .021
.038 .060
.009 .012
.750 .830
.285 .310
.290 .320
.100 Bse
.125 .175
.150
.025 .055
.045 .080
.005
o· 15'

018-1
18
MIN MAX
.105 .175
.015 .021
.038 .060
.009 .012
.880 .930
.285 .310
.290 .320
.100 BSC
.125 .175
.150
.025 .055
.045 .080
.005
o· 15'

020-1
20
MIN MAX
.105 .175
.015 .021
.038 .060
.009 .012
.935 1.060
.285 .310
.290 .320
.100 BSC
.125 .175
.150
.025 .060
.045 .080
.005
o· 15'

4.3

D22-1
22
MIN MAX
.105 .175
.015 .021
.038 .060
.009 .012
1.050 1.080
.285 .310
.290 .320
.100 BSC
.125 .175
.150
.015 .060
.020 .080
.005
15'

o·

024-1
24
MIN MAX
.105 .175
.015 .021
.045 .065
.009 .014
1.240 1.280
.285 .310
.300 .320
.100 Bse
.125 .175
.150
.015 .060
.030 .080
.005
o· 15'

028-3
28
MIN MAX
.105 .175
.015 .021
.045 .065
.009 .014
1.440 1.490
.285 .310
.300 .320
.100 BSC
.125 .175
.150
.015 .060
.030 .080
.005
o· 15'

PACKAGE DIAGRAM OUTUNES

DUAL IN-LINE PACKAGES (Continued)
24-40 LEAD CERDIP (600 MIL)
DWG

#

# OF LDS (N)
SYMBOL
A
b
b1
e
D
E
E1

e
L
L1
Q

S
S1

ex

D24-2
24
MAX
MIN
.090 .190
.014 .023
.038 .060
.008 .012
1.230 1.290
.500 .610
.590 .620
.100 Bse
.125 .200
.150
.015 .060
.030 .080
.005
o· 15·

D28-1
28
MIN
MAX
.090
.200
.014
.023
.038
.065
.008
.014
1.440 1.490
.510
.545
.590
.620
.100 Bse
.125
.200
.150
.020
.060
.030
.080
.005
o·
15·

D40-1
40
MAX
MIN
.160 .220
.014 .023
.038 .065
.008 .014
2.020 2.070
.510 .545
.590 .620
.100 Bse
.125 .200
.150
.020 .060
.030 .080
.005
o· 15·

I

28-40 LEAD CERDIP (WIDE BODY)
DWG #
# OF LDS (N)
SYMBOL
A
b
b1
e
D
E
E1

e

L
L1
Q

S
S1

ex

D28-2
28
MIN
MAX
.090 .200
.014 .023
.038 .065
.008 .014
1.440 1.490
.570 .600
.590 .620
.100 Bse
.125 .200
.150
.020 .060
.030 .080
.005
15·

o·

~32-1

32
MIN
MAX
.120
.210
.014
.023
.038
.065
.008
.014
1.625 1.675
.570
.600
.590
.620
.100 Bse
.125
.200
.150
.020
.060
.030
.080
.005
15·

o·

D40-Z
40
MIN
MAX
.160 .220
.014 .023
.038 .065
.008 .014
2.020 2.070
.570 .600
.590 .620
.100 esc
.125 .200
.150
.020 .060
.030 .080
.005
15·

o·

4.3

2

PACKAGE DIAGRAt.4 OUTUNES

DUAL IN-LINE PACKAGES (Continued)

20-32 LEAD SIDE BRAZE (300 MIL)

- - E1 - -

NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. Bse - BASIC LEAD SPACING BElWEEN CENTERS.
DWG I
II OF LOS (N)
SYMBOL
A

b
b1
C
0
E
E1

e
L
L1
Q

S
S1
S2

C20-1
C22-1
20
22
MIN
MAX
MAX
MIN
.090 .200
.100
.200
.014
.023
.014
.023
.040 .060 .040 .060
.008 1.015
.008
.015
.970 1.060 1.040 1.120
.220
.310
.260 .310
.290 .320 .290 .320
.100 BSC
.100 BSC
.125
.200
.125
.200
.150
.150
.015
.060
.015
.060
.030 .065 .030 .065
.005
.005
.005
.005
-

C24-1
C28-1
C32-3
28
32
24
MAX
MIN
MAX
MIN
MAX
MIN
.090 .200 .090 .200 .090 .200
.015
.014 .023 .014
.023
.023
.040 .060 .040 .060 .040 .060
.008
.014
.008
.015
.008 .015
1.180 1.230 1.380 1.420 1.S80 1.640
.220 .310 .280
.310
.220 .310
.290 .320 .290 .320 .290 .320
.100 BSC
.100 BSC
.100 BSC
.125
.200
.125
.200
.100
.175
.1S0
.150
.1S0
.015
.060
.015
.060 .030 .060
.030 .065 .030 .065 .030 .065
.005
.OOS
.005
.005
.005
.005
-

4.3

3

PACKAGE DIAGRA... OUTUNES

DUAL IN-LINE PACKAGES (Continued)
28-48 LEAD SIDE BRAZE (400 MIL)

- - - --------.j-I

I~·

D

48 LEAD OPTION
S2

Q

L r-------LI---'======::::L=====:~
1 -_

~

I

SEA nNG PLANE

i

~~c

f----- E1 -

NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.

DWG

#

# OF LOS eNJ
SYMBOL
A

b
b1
C
0
E
E1

e
L
L1
Q
S
S1
S2

C28-2
C48-1
C32-2
48
28
32
MIN
MIN
MAX
MAX
MIN
MAX
.090 .200 .090 .200 .085
.190
.014 .023 .014
.023 .014 .023
.040 .060 .040 .060 .040 .060
.008
.014 .008
.014
.008
.014
1.380 1.420 1.580 1.640 1.690 1.730
.380 .420 .380
.410
.380 .410
.390 .420 .390 .420 .390 .420
.070 BSC
.100 BSC
.100 BSC
.100
.175
.100
.175
.125
.175
.150
.150
.150
.030 .060 .030 .060 .020 ,070
.030 .065 .030 .065 .030 .065
.005
.005
.005
.005
.005
.005
-

4.3

4

PACKAGE DIAGRAM OUTUNES

DUAL IN-LINE PACKAGES (Continued)
24-68 LEAD SIDE BRAZE (600 MIL)

68 LEAD OPTION

..---

E1-~

NOlES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTI-fER'MSE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENlERS.

DWG II

,I OF LOS (N)
SYMSOL
A

b

~1

C

0
E
E1

e

L
L1
Q

S
S1

S2

C4O-1
C48-2
C68-1
C24-2
C28-3
C32-1
24
28
32
68
40
48
MIN
MIN
MIN
MAX
MAX
MAX
MIN
MAX
MIN
MAX
MIN
MAX
.090
.190
.085 .190
.100
.190 .085 .190
.100
.190
.085
.190
.015
.015
.023
.022 .015 .023
.015 .023 .015
.023
.015
.023
.040 .060 .038 .060 .040 .060 .038 .060 .040 .060 .040 .060
.008
.012 .008 .012 .008 .012 .008 .012 .008
.012 .008
.012
1.180 1.220 1.380 1.430 1.580 1.640 1.980 2.030 2.370 2.430 2.380 2.440
.575 .610 .580 .610 .580 .610 .580 .610 .550 .610
.580
.610
.595 .620 .595 .620 .590 .620 .595 .620 .590 .620 .590 .620
.100 SSC
.100 SSC
.100 SSC
.100 BSC
.100 SSC
.070 SSC
.125
.175
.125
.175
.125
.175
.125
.175
.125
.175
.125
.175
.150
.150
.150
.150
.150
- .150 .020 .060 .020 .065 .020 .060 .020 .060 .020 .060 .020 .070
.030 .065 .030 .065 .030 .065 .030 .065 .030 .065 .030 .065
.005
- .005 - .005 - .005 - :005 - .005 .010
010
.010
- .005 - .005 - .005 -

-

-

-

4.3

5

PACKAGE DIAGRAN OUTUNES

DUAL IN-LINE PACKAGES (ContInued)

64 LEAD SIDE BRAZE (900 MIL)
~I·------ D -----'I'y~---..I

TN
E

1~1

"""'T'"T"""T'

I-----'~

1-4--

E1-~

NOTES:
1. ALL DIMENSIONS ARE IN INCHES. UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.

DWG #
It OF LOS IN)
SYMBOL
A

b
b1
C
D
E
E1

e
L

L1
Q

S
S1
S2

C64-1
64
MIN
MAX
.110
.190
.014
.023
.040
.060
.008
.015
3.160 3.240
.884
.915
.920
.890
.100 BSC
.125
.200
.150
.015
.070
.065
.030
.005
.005

-

4.3

6

PACKAGE DIAGRAtwi OUTLINES

DUAL IN-LINE PACKAGES (Continued)
64 LEAD TOP BRAZE (900 MIL)
~------ D --~"'v~-~"I

NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. Bse - BASIC LEAD SPACING BETWEEN CENTERS.
DWG/I

~64-2

1# OF LOS (N)

64
MIN
~AX
.120
.180
.015
.021
.0..0
.060
.009
.012
3.170 3.240
.790
.810
.880
.815
.640
.660
.100 BSC
.160
.125
.150
.020
.100
.030
.065
.005
.005
-

SYMBOL
A

b

b1
C
0

E
E1
E2

e

L
L1
Q
S
S1
52

4.3

7

PACKAGE DIAGRAM OUTUNES

FLATPACKS

20-28 LEAD FLATPACK
S1

-1A
Ii

Q

L
E3
N

a
I I

S
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. SSC - SASIC LEAD SPACING SETWEEN CENTERS.
DWG

1#

#

OF LOS (N)
SYM~OL

A
b
C

0
E
E2
E3

e
K
L
Q
S
S1

F20-1
20
MIN
MAX
.045 .092
.015
.019
.003 .006
.540
.340 .360
.130
.030
.050 SSC
.008
.015
.250 .370
.010
.040
.045
.005
-

F20-2
20 t.295 BODY)
MAX
MIN
.045
.092
.015
.019
.003
.006
.540
.245
.303
.130
.030
.050 SSC
.008
.015
.250
.370
.010
.040
.045
.005
-

F24-1
24
MIN
MAX
.045 .090
.015
.019
.003
.006
.640
.360 .420
.180
.030
.050 sse
.008
.015
.250 .370
.010
.040
.045
.005
-

4.3

F28-1
28
MIN
MAX
.045 .090
.015
.019
.004 .007
.710
.740
.480 .520
.180
.040
.050 SSC
.008
.015
.250 .370
.010
.045
.045
.005
-

F28-2
28
MAX
MIN
.045
.115
.019
.015
.003
.007
.710
.740
.460 .520
.180
.040
.050 SSC
.008
.015
.250
.370
.010
.045
.045
.005

-

8

PACKAGE DIAGRAM OUTUNES

FLATPACKS (Continued)
48-64 LEAD QUAD FLATPACK
~--E--~

E2
I-- L - -

~E1

A2

-- L--

L

,

re

D

D1

D

D2

J

~

b

I

PIN 1 ID-./
L

NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
DWG /I
# OF LOS (N)
SYMBOL
A
A1
A2
b
C

DIE
D1/E1
D2/E2

e
L
ND/NE

F48-1
48
MIN
MAX
.089
.108
.079
.096
.058
.073
.018
.022
.008
.010
.750
.100 REF
.550 BSC
.050 BSC
.350
.450
12

F64-1
64
MIN
MAX
.070
.090
.060
.078
.030
.045
.016
.020
.009
.012
.885
.915
.075 REF
.750 BSC
.050 BSC
.350
.450
16

4.3

9

PACKAGE DIAGRAM OUTUNES

FLATPACKS (Continued)
68 LEAD QUAD FLATPACK
D
D1
D2

V-PIN 1

L

I"V

I

(lin

In n n In

n n In In

In 1ft

n In In

/

~

~

I

~
~

:::II
=I
:::II

~

:::II

s:
s:

:::II

•

:::II

t:

s:
s:

L_PIN 1 IND EX MARK

=I

-

:::II

-

:::II

~

::II

~

=I

E2 E1

E

t:

s:

:::II

r:

::II

I

):

t:

~IUJJJJ

1'1

.LI

=I

fII

.LI 1'1

.LI j.LI 1'1

i'"

.LI

I

---

7
L

'--e

f

NOTES:
1. ALL DIMENSIONS ARE IN INCHES. UNLESS OTHERWISE SPECIFIED
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.

DWG II
Ii_ OF LOS (N)
SYMBOL
A
A1

b
C
D/E
D1/E1
D2/E2

e
L
ND/NE

F68-1
68
MIN
MAX
.080
.145
.070
.090
.014
.021
.008
.012
1.640 1.870
.926
.970
.800 BSC
.050 BSC
.350
.450
17

4.3

10

PACKAGE DIAGRAM OUTLINES

FLATPACKS (Continued)
84 LEAD QUAD FLATPACK (CAVITY DOWN)
D1
D2

e---

~

D3 ----

LPIN 1 INDE X MARK

V,r
§§m

-

~

tL

E3

Jl

P1N 1

1
1

-

E2 E1

L

DWG II
OF lOS TN)
SYMBOL

A
A1
b

C
D/E
D1/E1

o27E2
D3/E3

e
l
ND/NE

F84-1
84
MIN
MAX
. 140
.105
.014
.020
.007
.013
1.485
1.615
1.130
1.170
1.000 BSC
.500 BSC
.050 BSC
.350
.450
21

-

E

DET. nAn

~

t

D

II

1

NOTES:
1. ALL DIMENSIONS ARE IN INCHES,
UNLESS OTHERWISE SPECIFIED .
2. BSe - BASIC LEAD SPACING
BETWEEN CENTERS.
3. CROSS HATCHED AREA INDICATES

INlEGRAL METAWC HEAT SINK.

~AX

I _

~ Ii-

I

C 012 MAX

AT BRAZE PADS
DETAIL

4.3

A

11

PACKAGE DIAGRAtti OUTLINES

FLATPACKS (Continued)
172 LEAD QUAD FLATPACK (MIPS)
D1

[.--f~

03-=i
?

l

B-

t

r P I N 1 IND EX MARK

I

--0

1I

D

'"

)

DWG #
OF LOS (N)
SYMBOL
A
A1
b
C

DIE
D1/E1
D2/E2
D3/E3

e
L
ND/NE

L

1
J

I

E

DET. "A"

L

t

D

#

PIN1

E2 E1

E3L

D

Vr

F172-1
172
MIN
MAX
•130
.105
.006
.010
.004
.008
1.580 1.620
1.135
1.165
1.050 BSC
.525 BSC
.025 BSC
.220
.230
43

-

NOlES:
1. ALL DIMENSIONS ARE IN INCHES•
UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING
BETWEEN CENlERS.

.. 008±.006
AT BRAZE PADS
DETAIL

4.3

A

12

PACKAGE DIAGRAt.i OUTUNES

CERPACKS
16-28 LEAD CERPACK
t-----

0

-------4~

S1

Q

L

~

N
E1

E

tK

.--1 r--

II

I

I I

I

--- e r--

---

L

S

NOTES:
1. ALL DIMENSION ARE IN INCHES. UNLESS OTI-lERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
DWG JI
1# OF LOS (N
SYMBOL
A
b
C
D
E
E1

e
K
L
Q

S
S1

E16-1
16
MIN
MAX
.055 .085
.015
.019
.0045 .006
.370 .430
.245 .285
.305
.050 BSC
.008
.015
.250 .370
.026 .040
.045
.005
-

E20-1
20
MIN
MAX
.045 .092
.019
.015
.0045 .006
.540
.245 .300
.305
.050 BSC
.008
.015
.250 .370
.026 .040
.045
.005
-

E24-1
24
MIN
MAX
.045 .090
.015
.019
.0045 .006
.640
.300 .420
.440
.050 BSC
.008
.015
.250 .370
.026 .040
.045
.005
-

4.3

E28-1
28
MIN
MAX
.115
.045
.015
.019
.0045 .009
.740
.460 .520
.550
.050 BSC
.008
.015
.250 .370
.026 .045
.045
.005
-

E28-2
28
MIN
MAX
.045 .090
.015
.019
.0045 .006
.740
.340
.380
.400
.050 BSC
.008
.015
.250 .370
.026
.045
.045
.005
-

-

13

PACKAGE DIAGRAM OUTUNES

CERQUADS
68 LEAD CERQUAD (STRAIGHT LEADS)

---

L[iE1

E

~

PIN 1 ID

t-

D1

D

IJ

_~=_=t==============t==

--.--A

I

~c

t

NOTES:
1. ALL DIMENSIONS ARE IN INCHES. UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.

DWG

#

II OF LOS (N)
SYMBOL
A

b
C
D/E
D1/E1
D3/E3

e
L
ND/NE

CQ68-1
68
MIN
MAX
.115
.165
.008
.013
.0045
.008
.860
1.100
.460
.500
.400 REF
.025 BSC
.200
.300
17

4.3

14

PACKAGE DIAGRAW OUTUNES

CERQUADS (Continued)
84 LEAD CERQUAD (J-BEND)

-

D

D1

.040 X 45·

e -

T-

+

D3

ll::l 1::11::11::1 1::1 1::1

I·

1::I...;r,
~

E3
E1

.1

E

c
~----- D2/E2

*

DWG II
OF LOS (N)
SYMBOL

A
A1
b1
b
C
D/E
D1/E1
D2/E2
D3/.E3

e
ND/NE

CQ84-1
84
MAX
MIN
•155
.200
. 090
.120
.022
.032
.013
.023
.006
.013
1.170
1.190
1.162
1.138
1.100 .1.150
1.000 BSC
.050 BSC
21

-------.j

NOlES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE
SPECIFIED •
2. BSC - BASIC LEAD SPACING BETWEEN CENlERS.

4.3

15

PACKAGE DIAGRAW OUTUNES

LEADLESS CHIP CARRIERS
J

X 45'

iA1[

h X 45'
3 PL

t

03

NOTES:
1. ALL DIMENSIONS ARE IN INCHES. UNLESS OlHERWISE SPECIFIED.
2. Bse - BASIC LEAD SPACING BETWEEN CENTERS.

b
~L3
B3~ ~

20-48 LEAD LCe (SQUARE)
DWG II
# OF LOS (N)
SYMBOL
A
A1
B1
B2
B3
D/E
D1/E1
D2/E2
D3/E3

e
e1
h
J
L
L1
L2
L3
ND/NE

L20-2
20
MAX
MIN
.064 .100
.054 .066
.022 .028
.072 REF
.006 .022
.342 .358
.200 BSC
.100 BSC
.358
.050 BSC
.015
.040 REF
.020 REF
.045 .055
.045 .055
.077 .093
.003 .015
5

L28-1
28
MIN
MAX
.064 .100
.050 .088
.022 .028
.072 REF
.006 .022
.442 .460
.300 BSC
.150 BSC
.460
.050 BSC
.015
.040 REF
.020 REF
.045 .055
.045 .055
.077 .093
.003 .015
7

L44-1
+4MIN
MAX
.064 .120
.054 .088
.022 .028
.072 REF
.006 .022
.640 .660
.500 BSC
.250 BSC
.560
.050 esc
.015
.040 REF
.020 REF
.045 .055
.045 .055
.077 .093
.003 .015
11

4.3

L48-1
48
MIN
MAX
.055 .120
.045 .090
.017 .023
.072 REF
.006 .022
.554 .572
.440 BSC
.220 BSC
.500 .535
.040 esc
.015
.012 RADIUS
.020 REF
.033 .047
.033 .047
.077 .093
.003 .015
12

-

16

•

PACKAGE DIAGRAM OUTUNES

LEADLESS CHIP CARRIERS (Continued)
52-68 LEAD LCe (SQUARE)

DWG #
I OF LDS .(NJ
SYMBOL
A
A1
B1
B2
B3

DIE
D1/E1
D2/E2

D3/E3
e
e1
h
J
L
L1
L2
L3
NDLNE

L52-1
52
MIN
MAX
.061 .087
.051 .077
.022 .028
.072 REF
.006 .022
.739
.761
.600 BSC
.300 BSC
.661
.050 esc
.015
.040 REF
.020 REF
.045 .055
.045 .055
.077 .093
.003 .015
13

L52-2
52
MIN
MAX
.082 .120
.072 .088
.022 .028
.072 REF
.006 .022
.739
.761
.600 esc
.300 esc
.661
.050 esc
.015
.040 REF
.020 REF
.045 .055
.045 .055
.075 .093
.003 .015
13

L68-2
68
MIN
MAX
.082 .120
.072 .088
.022 .028
.072 REF
.006 .022
.938 .962
.800 esc
.400 esc
.862
.050 BSC
.015
.040 REF
.020 REF
.045 .055
.045 .055
.077 .093
.003 .015
17

4.3

L68-1
68
MIt!
MA'-<
.065 .120
.055 .075
.008 .014
.072 REF
.006 .022
.554 .566
.400 esc
.200 esc
.535
.025 esc
.015
.040 REF
.020 REF
.045 .055
.045 .055
.077 .093
.003 .015
17

17

PACKAGE DIAGRAM OUTUNES

LEADLESS CHIP CARRIERS (Continued)
h X 45'

J X 45'

3 PL

I

A1i

~B1

I

L~

~

A

L

NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.

20-32 LEAD LCC (RECTANGULAR)
DWG#

Ii OF LOS (N
SYMBOL
A
A1
B1
B2
B3
0
01
02
03
E
E1
E2
E3

e
e1
h

J
L

L1
L2
L3
NO
NE

L20-1
20
MIN
MAX
.060 .075
.050 .065
.022 .028
.072 REF
.006 .022
.284 .296
.150 BSC
.075 BSC
- .280
.420 .435
.250 esc
.125 esc
- .410
.050 esc
.015
.040 REF
.020 REF
.045 .055
.045 .055
.080 .095
.003 .015
4
6

L22-1
22
MIN
MAX
.064 .100
.054 .063
.022 .028
.072 REF
.006 .022
.284 .296
.150 BSC
.075 BSC
- .280
.480 .496
.300 esc
.150 esc
- .480
.050 esc
.015
.012 RADIUS
.012 RADIUS
.039 .051
.039
.051
.083 .097
.003 .015
4
7

L2 4-J
.4
MIN
MAX
.064 .120
.054 .066
.022 .028
.072 REF
.006 .022
.292 .308
.200 BSC
.100 BSC
.308
.392 .408
.300 esc
.150 esc
- .408
.050 BSC
.015
.025 REF
.015 REF
.040 .050
.040 .050
.077 .093
.003 .015
5
7

-

4.3

_L~ ~-~

8
MAX
MIN
.060 .120
.050 .088
.022 .028
.072 REF
.006 .022
.342 .358
.200 BSC
.100 esc
.358
.540 .560
.400 esc
.200 esc
.558
.050 BSC
.015
.040 REF
.020 REF
.045 .055
.045 .055
.077 .093
.003 .015
5
9

-

-

L3 2-1
.2
t.iAX
M!~
.060 .120
.050 .088
.022 .028
.072 REF
.006 .022
.442 .458
.300 BSC
.150 BSC
- .458
.540 .560
.400 esc
.200 esc
- .558
.050 Bse
.015
.040 REF
.020 REF
.045 .055
.045 .055
.077 .093
.003 .015
7
9
18

PACKAGE DIAGRAW OUTUNES

PIN GRID ARRAYS
68 PIN PGA (CAVITY UP)

TOP VIEW
1 2

3

4

5

7

8

9 10 11

_-yo-

0000 0 0eJ-+---rK00000 00000
J00
00
H00
00
G00
00
L

0

+

F

E00
000
c00

B~0000

A

0000

[I.

E1

E

00
00
00

-I

0000~
000~-+-+---'-

~1~J.1

PIN 1 ID

SEATING PLANE

DWG II
I OF PINS (N)
SYMBOL
A
~B

(lB1
(lB2
DJE
D1/E1

e
L
M
Q

G68-1
68
MIN
MAX
.070
.145
•016
.020
.080
.040
.060
1.140
1.180
1.000 BSC
.100 BSC
.120
.140
11
.040
.060

NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE
SPECIFIED •
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. SYMBOL -M- REPRESENTS THE PGA MATRIX SIZE.
4. SYMBOL -N- REPRESENTS THE NUMBER OF PINS
5. CHAMFERED CORNERS ARE lOiS OPllON.

4.3

19

PACKAGE DIAGRAW OUTUNES

PIN GRID ARRAYS (Continued)
84 PIN PGA (CAVITY UP -

BOTTOM VIEW
1 2

3

4

5

6

7

8

12 X 12 GRID)

TOP VIEW

¢B1

9 10£12

+

~------D1

------~

•

PIN 1 I D /

~----D--------.j

SEATING PLANE

DWG II
I OF PINS (N)
SYMBOL

A
~B

fB1
fB2
DIE
D1/E1

e

L
M
Q

G84-1
84
MIN
MAX
.077
.145
.016
.020
.040
.080
.040
.060
1.180 1.235
1.100 BSC
.100 BSC
.120
.140
12
.040
.060

NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENlERS.
3. SYMBOL "M· REPRESENTS THE PGA MATRIX SIZE.
4. SYMBOL "N· REPRESENTS THE NUMBER OF PINS
5. CHAMFERED CORNERS ARE IDis OPTION.

4.3

20

PACKAGE DIAGRAN OUTUNES

PIN GRID ARRAYS (Continued)
84 PIN PGA (CAVITY UP -

11 X 11 GRID)
TOP VIEW

1 2

3

4

5

L00000
K00000
J00
0
H00
G000
F-f-Ht-+t-o-H-O-If---

+

E1

E

E000
000
000
00
c00
0 0
00
B00000 00000
A
0000 0000~---'-

~1~3]

1.1.

-I

PIN 1 ID

SEATING PLANE

DWG II

G84-3

# OF PINS (N)
SYMBOL
A
t5B
_B1
'B2
D/E
D1/E1

e
L
M
Q

84
MIN
.070
.016

MAX
.145
.020
.080
.040
.060
1.080 1.120
1.000 BSC
•100 BSC
.120
.140
11
.040
.060

NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OlHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. SYMBOL -M- REPRESENTS "THE PGA MATRIX SIZE.
4. SYMBOL -N- REPRESENTS "THE NUMBER OF PINS
5. CHAMFERED CORNERS ARE lOT's OPTION •

4.3

21

PACKAGE DIAGRAM OULTINES

PIN GRID ARRAYS (Continued)
108 PIN PGA (CAVITY UP)

TOP VIEW

BOTTOM VIEW

+-

E1

E

000
000
0000
000
c000000 000000
B000000 000000
A 0000000000f-+++-----L...
01

..

II

PIN 1

~---- 0 ---------t...

cl

SEATING PLANE

~I
I

#

DWG II
OF PINS (N)
SYMBOL
A
fB
fB1
'B2

DIE
D1/E1

e

L
M
Q

G108-1
108
MIN
MAX
.070
.145
.016
.020
.080
.040
.060
1.188
1.212
1.100 BSC
.100 BSC
.120
.140
12
.040
.060

+

I
10J

t

:
:
I
~ @~ ~ ~ ~ ~ ~ ~ ~ ij f

¢B2~ ~ ~~¢B

t

A

~ e~

NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. SYMBOL "M" REPRESENTS THE PGA MATRIX SIZE.
4. SYMBOL "N" REPRESENTS THE NUMBER OF PINS
5. CHAMFERED CORNERS ARE lOiS OPTION.

4.3

22

PACKAGE DIAGRAM OUTLINES

PIN GRID ARRAYS (Continued)
144 PIN PGA (CAVITY UP)
TOP VIEW
1 234 5

6 7

R0000000
p0000000
N0000000
M000
L000
K000
J000
H000
G000

~----~-----

DWG II
II OF PINS (N)
SYMBOL
A
~B

_B1
_B2
DIE
D1/E1

e
L

M
Q

+

01-----~

PIN 1

10-./

0 -----...-j

G144-2
145
MIN
MAX
.082
.125
.016
.020
.060
.080
.060
•040
1.559 1.590
1.400 BSC
.100 BSC
•120
.140
15
.040
.060

NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS •
3. SYMBOL "M" REPRESENTS THE PGA MATRIX SIZE.
4. SYMBOL "N" REPRESENTS THE NUMBER OF PINS
5. CHAMFERED CORNERS ARE lOiS OPTION •
6. EXTRA PIN (D-4) ELECTRICALLY CONNECTED TO D-3•

4.3

23

PACKAGE DIAGRAt.t OUTUNES

PIN GRID ARRAYS (Continued)
208 PIN PGA (CAVITY UP)
~B1

BOTTOM VIEW

T

TOP VIEW

~·~1'~'~1'~1'~~~~1~~~1~_J~,~,~.~,~~~I~~

S ~'~1'~'~J~~~'_'~'~"I~1'~'~1'~'~~_1~~
R ~1''-----''~'_--'~J'---_'~--''~--'.'''--'--'''''''--''~1'~~~_'~' __' _
P
N '"'-.,.....,-,"'"
M

L
K

+

.1.1

DWG II
II OF PINS (N)
SYMBOL
A
9)B
9)B1
9)B2

DIE
D1.LE1

e
L
M
Q

II
PIN 11DJ

G20B-1
20B
MIN
.070
.016

-

MAX
.145
.020

.OBO

.040
.060
1.732 1.7BO
1.600 BSC
.100 BSC
•125
.140
17
.040
.060

NOlES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. SYMBOL "M" REPRESENTS THE PGA MATRIX SIZE.
4. SYMBOL "N" REPRESENTS THE NUMBER OF PINS
5. CHAMFERED CORNERS ARE lOiS OPTION •

4.3

24

PACKAGE DIAGRAt.i OUTUNES

PIN GRID ARRAYS (Continued)
68 PIN PGA (CAVITY DOWN)

TOP VIEW
1

2

345

0000
K00000
J00
H00
G00
L

F~-tt-O--t---

+

E1

-,

E

E00
00
000
00
c00
00
BED0000 0000EB
A
0000 000EB~-L-

I.~'''~--- ~1 - - - -..-'-.l.1

PIN 1 ID

[Ql
SEATING PLANE

DWG II
II OF PINS (N)
SYMBOL
A
"B
"81
"B2
D/E
D1/E1

e
L
M
Q1

GU68-2
68
MIN
MAX
.077
.095
.016
•020
.060
.080
.040
.060
1.098 1.122
1.000 BSC
.100 BSC
.120
.140
11
.025
.060

fr

/

~

I~------------~~
I
A

,
~ e~

~~~mrr~f~

¢B2~ ~ ~~¢B

NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS •
3. SYM80L "M" REPRESENTS THE PGA MATRIX SIZE.
4. SYMBOL "Nit REPRESENTS THE NUMBER OF PINS
5. CHAMFERED CORNERS ARE loTs OP1l0N.

4.3

25

PACKAGE DIAGRAM OUTUNES

PIN GRID ARRAYS (Continued)
84 PIN PGA (CAVITY DOWN)

BOTTOM VIEW
1 2

3

4

5

6

00000
L00000
K000
J00
H00
G00
F00
E00
000
c000
B00000
A
0000
M

7

8

TOP VIEW

¢B1

9 10 11 12

000 0f-+H------r000000
000
00
00
+
00 E1
00
00
00
000
000000
0000Ef)f-+H----'-

0

0

0

+

E

0

~------01------~

PIN 1 1 0 /

SEATING

01

t

t
SYMBOL
A
fB
fB1
fB2

DIE
D1/E1

e
L
M
Q1

--.l

I
I
r
PLANE-----'-----y-~--------H-~ @~ mm ~ T

t------O----~

DWG II
# OF PINS (N)

•

0

ij

¢B2~ ~

-H-¢B

A

t

~ e~

G84-2
84
MIN
MAX
.077
.145
.016
.020
.060
.080
.040
.060
1.180 1.235
1.100 BSC
.100 Bse
.100
.120
12
.025
.060

NOlES:
1. ALL DIMENSIONS ARE IN INCHES. UNLESS OlHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENlERS.
3. SYMBOL -M- REPRESENTS THE PGA MATRIX SIZE.
4. SYMBOL -N- REPRESENTS THE NUMBER OF PINS
5. CHAMFERED CORNERS ARE IDrs OPllON.

4.3

26

PACKAGE DIAGRAM OUTUNES

PIN GRID ARRAYS (Continued)
84 PIN PGA (CAVITY DOWN -

BOTTOM VIEW
1 2

3

4

5

6

7

~----

D1

t------

D

8

r

MIPS)

TOP VIEW

¢B1

9 10/11 12

----~

rI

NOTE 6

01

----.-.j

SEATING

PLANE-'---r-~t ~ ~ ~
--tt-

¢B2~ ~
DWG II
II OF PINS (N)
SYMBOL

A
fB
'B1
.B2
O/E
D1/E1

e
L

M
01

t

nnrr ~ fiji t
--H---¢B

~e~

G84-4
84
MIN
MAX
.077
.145
•016
.020
.060
.080
.040
.060
1.180 1.235
1.100 BSC
.100 BSC
.120
.140
12
.025
.060

NOTES:
1. ALL DIMENSIONS ARE IN INCHES. UNLESS OTHERWISE
SPECIFIED •
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. SYMBOL "M" REPRESENTS THE PGA MATRIX SIZE.
4. SYMBOL "N· REPRESENTS THE NUMBER OF PINS
5. CHAMFERED CORNERS ARE IDrS OPll0N.
6. CROSS HATCHED AREA INDICATES INTEGRALL METAWC
HEAT SINK •

4.3

27

PACKAGE DIAGRAM OUTUNES

PIN GRID ARRAYS (Continued)
144 PIN PGA (CAVITY DOWN)

TOP VIEW

¢B1

1 2 3 4 5

6 7

9 10

1 12 13 14 15

R0000000 0 0000
p0000000 0000000
N0000000 0000000
u000
000
L000
000
K000
000
J 000
000
0

G

000

t-

E1

000

E
-t------

F000
000
E000
000
0000
000
c0000000 0000000
80000000 0000000
A
000000 000000
.-I~_I._____ ~1

---------.j.I.1

-+

t

t
DWG #

# OF PINS (N)
SYMBOL
A
~B

~B1
~B2

DLE
D1/E1

e
L
M
Q1

G144-1
144
MIN
MAX
.082
.100
.016
.020
.060
.080
.040
.060
1.559 1.590
1.400 BSC
.100 BSC
•120
.140
15
.025
.060

II
PIN 1 I D J

L~Q1
A -I

SEA TING PLANE

+

~ @~

I

nnrmnrr ~ ~ f ~

.B2~ ~ ~~.B

~e~

NOTES:
1. ALL DIMENSIONS ARE IN INCHES. UNLESS OlliERWlSE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. SYMBOL "M" REPRESENTS lliE PGA MATRIX SIZE.
4. SYMBOL "N" REPRESENTS lliE NUMBER OF PINS
5. CHAMFERED CORNERS ARE lOiS OPTION •

4.3

28

PACKAGE DIAGRAt.4 OUTLINES

PLASTIC DUAL IN-LINE PACKAGES
16-32 LEAD PLASTIC DIP (300 MIL)

iJS
01

~-------r~----------'

~

TI

PLANE

L

I

I

eA

---i

~

NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. D & E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

1#

DWG II
OF LDS (N)
SYMBOLS

A
A1
b
b1
C
D
E
E1

e

eA

L
ex
S
Q1

P16-1

P22-1

P28-2

16

22

28

P32-2

32

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

.140
.015
.015
.050
.008
.745
.300
.247
.090
.310
.120

.165
.035
.022
.070
.012
.760
.325
.260
.110
.370
.150
15·
.035
.070

.145
.015
.015
.050
.008
1.050
.300
.240
.090
.310
.120

.165
.035
.022
.065
.012
1.060
.320
.270
.110
.370
.150
15·
.040
.075

.145
.015
.015
.045
.008
1.345
.300
.270
.090
.310
.120

.180
.030
.022
.065
.015
1.375
.325
.295
.110
.400
.150
15·
.042
.065

.145
.015
.016
.045
.008
1.545
.300
.275
.090
.310
.120

.180
.030
.022
.060
.015
1.585
.325
.295
.110
.400
.150
15·
.060
.065

O·

.015
.050

O·

.020
.055

4.3

O·

.020
.055

o·

.020
.055

29

PACKAGE DIAGRAM OUTLINES

PLASTIC DUAL IN-LINE PACKAGES (Continued)

f

US

~----------~-+------~

Q1

t

E1

E

,

t

~

TI

•

PLANE

L

I

I

~

eA

~

NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. D & E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

18-24 LEAD PLASTIC DIP (300 MIL -

#

DWG "
OF LDS (N)
SYMBOLS
A

A1
b

b1
C

0
E
E1

e

eA
L

ex
S
Q1

P1B-1

P20-1

18

20
MIN
.145
.015
.015
.050
.008
1.022
.300
.240
.090
.310
.120

040

MAX
.10b
.035
.020
.070
.012
.910
.325
.260
.110
.370
.150
15·
.060

.050

.070

MIN
.140
.015
.015
.050
.008
.885
.300
.247
.090
.310
.120

O·

FULL LEAD)
P24-1

24
MIN
.145
.015
.015
.050
.008
1.240
.300
.250
.090
.310
.120

.025

MAX
.10b
.035
.020
.070
.012
1.040
.325
.280
.110
.370
.150
15"
.070

.055

MAX
.165
.035
.020
.065
.012
1.255
.320
.275
.110
.370
.150
15·
.075

.055

.075

.055

.070

O·

4.3

O·

30

PACKAGE DIAGRAM OUTUNES

PLASTIC DUAL IN-IlNE PACKAGES (Continued)

24- 48 LEAD PLASTIC DIP (600 MIL)

#

P24-2
24
MIN
MAX

DWG /I
OF LEADS {N,

SYMBOLS

P28-1
28
MIN
MAX

P32-1

32

P40-1
40
MIN
MAX

MIN

MAX

A

.16U

.1Hb

.16U

.1Hb

.1/U

.190

.160

A1
b
b1
C
0
E
El
e
eA
L
ex

.015
.015
.050
.008
1.240
.600
.530
.090
.610
.120

.015
.015
.050
.008
1.420
.600
.530
.090
.610
.120

.050
.020
.055
.012
1.655
.625
.550
.110
.670
.135
15·
080
.075

.015
.015
.050
.008
2.050
.600
.530
.090
.610
.120

.060
.060

.035
020
065
.012
1.460
.620
.550
.110
.670
.150
15·
.080
.080

.015
.016
.045
.008
1.645
.600
.530
.090
.610
.125

S

.035
.020
.065
.012
1.260
.620
.550
.110
.670
.150
15·
.080
.080

Q1

O·

O·

055
.060

O·

.070
.065

O·

.070
.060

P48-1,
48
MAX
MIN

.1Hb

.1/U

.~UO

.035
.020
.065
.012
2.070
.620
.550
.110
.670
.150
15·
.085
.080

.015
.015
050
.008
2.420
.600
.530
.090
.610
.120

.035
.020
.065
.012
2.450
.620
.560
.110
.670
.150
15·
.075
.080

O·

.060
.060

64 LEAD PLASTIC DIP (900 MIL)

DWG #

P64-1

# OF LEADS (N)
;)TMCUL.S

A
A1
b
bl
C
D
E
E1
e
eA
L
ex
S
Q1

64
MIN

MAX

.1HO

.230

.015
.015
.050
.008
3.200
.900
.790
.090
.910
.120

.040
.020
.065
.012
3.220
.925
.810
.110
1.000
.150
15·
.065
.090

O·

.045
.080

4.3

31

PACKAGE DIAGRAM OUTLINES

SMALL OUTLINE Ie

NOTES:
1. ALL DIMENSIONS ARE IN INCHES, ULESS OTHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. 0 & E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS
AND TO BE MEASURED FROM THE BOTTOM OF PKG.
4. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO
ONE ANOTHER WITHIN .004" AT THE SEATING PLANE.

•
PIN 1

e

~t. h~tt;~~
--jf-B

A14T

SEATING

--JL f--

ex

PLA~~ J

II

16-24 LEAD SMALL OUTliNE (GULL WING)

1#

#

S018-1

S020-2

S024-2

S024-3

16 (.300)
MIN
MAX

18 (.300)
MIN
MAX

20 (.300")

24 (.300")

24 (.300")

MIN

MAX

MIN

MAX

MIN

MAX

A

.095

.1043

.095 .1043

.095

.1043

.095 .1043

.110

.120

A1

.005

.0118

.005

.0118

.005

.0118

.005

.0118

.005

.0118

B

.014

.020

.014

.020

.014

.020

.014

.020

.014

.020

e

.0091

.0125

.0091 .0125

.0091 0125

.0091 .0125

.007

.011

D

.403

.413

.447

.497

.600

.620

.630

DWG

OF LDS (N)
SYMBOL

e

S016-1

.050 Bse

E

.292

.2992

h

.010

H
L

.462

.050 Bse

.511

.050 Bse

.614

.050 Bse

.050 Bse

.292 .2992

.292

.2992

.292

.2992

.295

.305

.020

.010

.020

.010

.020

.010

.020

.012

.020

.400

.419

.400

.419

.400

.419

.400

.419

.406

.419

.018

.045

.018

.045

.018

.045

.018

.045

.028

.045

ex

o·

8·

o·

8·

o·

8·

o·

8·

o·

8·

S

.023

.035

.023

.035

.023

.035

.023

.035

.032

.043

4.3

32

PACKAGE DIAGRAM OUTLINES

SMALL OUTLINE IC (Continued)

NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. D & E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS
AND TO BE MEASURED FROM THE BOTTOM OF THE PKG.
4. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO
ONE ANOTHER WITHIN .004" AT THE SEATING PLANE.
PIN 1

~=d-

-ll--B

A,fT

SEATING

PLA~~ J

28 LEAD SMALL OUTIJNE (GULL WING)
DWG

#

# OF LDS (N)

S028-2
28 (.300")

S028-3
28 (.330")

SYMBOL

MIN

MAX

MIN

MAX

A

.095

.1043

.110

.120

A1

.005

.0118

.005

.014

B

.014

.020

.014

.019

e

.0091

.0125

.006

.010

D

.700

.712

.718

.728

e

.050 Bse

.050 Bse

E
h

.292

.2992

.340

.350

.010

.020

.012

.020

H

.400

.419

.462

.478

L

.018

.045

.028

.045

a

0"

8"

0"

8"

S

.023

.035

.023

.035

4.3

33

PACKAGE DIAGRAt.i OUTLINES

SMALL OUTLINE IC (Continued)
16-24 LEAD SMALL OUTLINE (EIAJ DWG _I
/I OF LDS (N)
SYMBOLS
A
A1
B
e
D
E
e
H
L

ex

S016-5
16
MIN
MAX
.057
.071
.002 TYP
.012
.020
.006
.010
.248
.271
.165
.180
.0315 BSe
.232 .256
. 010
8·
o·

S020-5
20
MIN
MAX
.069 .083
.002 TYP
.020
.012
.010
.006
.331
.354
.205 .220
.0315 BSe
.295
.319
.010
8·
o·

S024-5
24
MIN
MAX
.069 .083
.002 TYP
.012
.020
.006
.010
.382 .405
.205 .220
.0315 BSe
.295
.319
.010
o·
8·

16-28 LEAD SMALL OUTLINE (EIAJ DWG 1
I' OF LDS (N)
SYMBOLS
A
A1
B
e
D
E
e
H
L

ex

S016-6
16
MIN
MAX
.057 .071
.002 TYP
.012 .020
.006 .010
.382 .406
.165 .180
.050 Bse
.232 .256
.010
8·
o·

S018-6
18
MIN
MAX
.069 .083
.002 TYP
.012
.020
.006
.010
.437 .453
.205 .220
.050 BSe
.319
.295
.010
8·
o·

.0315 PITCH)

•

.050 PITCH)

S020-6
20
MIN
MAX
.069 .083
.002 TYP
.012
.020
.006
.010
.480 .504
.205 .220
.050 BSe
.295
.319
.010
O·
8·

4.3

S024-6
24
MAX
MIN
.083
.069
.002 TYP
.012
.020
.006
.010
.580
.603
.205
.220
.050 BSe
.295
.319
.010
8·
o·

-

S028-6
28
MIN
MAX
.083
.098
.002 TYP
.012
.020
.006
.010
.720
.740
.290
.300
.050 BSe
.378
.402
.010
8·
o·

34

PACKAGE DIAGRAM OUTLINES

SMALL OUTLINE IC (Continued)

NOTES:
1. ALL DIMENSIONS ARE IN INCHES,
UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN
CENTERS.
3. D1 & E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSION AND TO BE MEASURED
FROM THE BOTTOM OF THE PKG.
4. FORMED LEADS SHALL BE PLANAR WITH
RESPECT TO ONE ANOTHER WITHIN .004"
AT THE SEATING PLANE

D1

~45'
---j~B1

1--

Jrtc
I

I

E2

-I

16-24 LEAD SMALL OUTLINE (J-BEND)
OWG

#

# OF LOS

(N)

SYMBOLS
A

A1
B
B1

C
01
E
E1
E2

e
h

S

S016-2
16 LD .300~)
MIN

MAX

.120
.140
.078
.095
.020
.024
.014
.020
.008
.013
.400
.412
.335
.347
.292
.300
.272
.262
.050 esc
.010
.020
.023
.035

S020~1

20 LD
MIN

.300~)

MAX

.140
.120
.078
.095
.020
.024
.014
.020
.008
.013
.500
.512
.335
.347
.292
.300
.262
.272
.050 BSC
.010
.020
.023
.035

S024-4
24 LD .300~)
MIN

MAX

.130
.082
.026
.015
.007
.620
.335
.295
.260
.050
.010
.032

.148
.095
.032
.020
.011
.630
.345
.305
.280

4.3

esc
.020
.043

35

PACKAGE DIAGRAM OUTLINES

SMALL OUTLINE IC (Continued)

E1

E

NOTES:
1. ALL DIMENSIONS ARE IN INCHES,
UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING
BETWEEN CENTERS.
3. D1 & E1 DO NOT INCLUDE MOLD
FLASH OR PROTRUSION AND TO
BE MEASURED FROM THE BOTTOM
OF THE PKG.
4. FORMED LEADS SHALL BE PLANAR
WITH RESPECT TO ONE ANOTHER
WITHIN .004" AT THE SEATING
PLANE .

....--E2

28-32 LEAD SMALL OUTLINE (J-BEND)

#

DWG I
OF LOS (N)
SYMBOLS
A
A1
B
B1
e
01
E
E1
E2

e
h
S

S028-5
28 LO (.300")
MIN
MAX
.120
.140
.078
.095
.020
.024
.014
.020
.008
.013
.700
.712
.335
.347
.292
.300
.262
.272
.050 Bse
.012
.020
.023
.035

S028-4
28 LD (.350")
MIN
MAX
.130
.148
.082
.095
.026
.032
.016
.020
.007
.011
.720
.730
.380
.390
.345
.355
.310
.330
.050 Bse
.012
.020
.023
.035

S032-2
32 LD (.300")
MAX
MIN
.1.30
.148
.082
.095
.032
.026
.016
.020
.008
.013
.830
.820
.340
.330
.305
.295
.260
.275
.050 Bse
.020
.012
.032
.043

4.3

36

PACKAGE DIAGRAM OUTLINES

SMALL OUTLINE IC (Continued)
48 & 56 LEAD SMALL OUTLINE (SSOP -

GULL WING)

NOTES:
1. ALL DIMENSIONS ARE IN INCHES. UNLESS
OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN
CENTERS.
3. 0 & E DO NOT INCLUDE MOLD FLASH OR
PROTRUSIONS.
4. FORMED LEADS SHALL BE PLANAR WITH
RESPECT TO ONE ANOTHER WITHIN .004"
AT THE SEATING PLANE.

N

A

SEATING

DWG

#

#

OF LOS (N)

SYMBOL

PLA~EJ

S048-1
MAX

MAX

A

.095

.110

.095

.110

.008

.016

.008

.016

b

.008

.012

.008

.012

C

.005

.009

.005·

.009

D

.620

.630

.720

.730

E

.291

.299

.291

·.299

e

.025 BSe

.025 sse

.395

.420

.395

h

.015

.025

.015

.420
.025 .

L

. 020

.040 .

~020

.040

0"

8"

o·

8"

ex

ex

56 (.300")
MIN

A1

H

L

S056-1

48 (.300")
MIN

-11--

4.3

37

PACKAGE DIAGRAM OUTLINES

PLASTIC QUAD FLATPACKS
100-132 LEAD PLASTIC QUAD FLATPACK (JEDEC)

NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS
OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN
CENTERS.
3. PIN 1 IDENTIFIER CAN BE POSITIONED AT
EITHER ONE OF THESE TWO LOCATIONS.
4. DIMENSIONS D1, D2, E1, AND E2 DO NOT
INCLUDE MOLD PROTRUSIONS. ALLOWABLE
MOLD PROTRUSIONS ARE AS FOLLOWS:
D1 & E1 = .010 MAX.
•
D2 & E2 = .007 MAX.
5. ND & NE REPRESENT NUMBERS OF LEADS
~
IN D & E DIRECTIONS . RESPECTIVELY.

E1 E E2

1#

OWG II
OF LOS (N)
SYMBOLS
A
A1
B
b1

e
o

01
02
03

e
E
E1
E2
E3

L

ex
NO/NE

PQ100-1
100

PQ132-1
132

MIN
.160
.180
.020
.040
.008
.016
.008
.012
.0055
.008
.875
.885
.747
.753
.897
.903
.600 REF
.025 Bse
.875
.885
.747
.753
.897
.903
.600 REF
.020
.030

0°
25/25

8°

MAX

.160
.180
.020
.040
.008
.016
.008
.012
.0055
.008
1.075 1.085
.947
.953
1.097 1.103
.800 REF
.025 Bse
1.075 1.085
.947
.953
1.097 1.103
.800 REF
.020
.030

0°
8°
33/33
4.3

38

PACKAGE

DIAGRA~

OUTLINES

PLASTIC QUAD FLATPACKS (Continued)
80-128 LEAD PLASTIC QUAD FLATPACK (EIAJ)

E3 E1

E

OWG #
1# OF LOS (N)

SYMBOLS
A
A1
A2

C
0
01
03

E
E1
E3
L
ND/NE

P

w
ZD
ZE

PQ80-2
80
MIN
MAX
.110
.124
.010
.100
.120
.005 .008
.909 .917
.783
.791
.724 REF
.673
.681
.547 .555
.472 REF
.026 .037
16/24
.0315 sse
.010
.018
.032
.039

PQ100-2
100
MAX
MIN
.110
.124
.010
.100
.120
.005 .008
.909 .917
.791
.783
.742 REF
.673
.681
.547 .555
.486 REF
.026 .037
20/30
.026 sse
.018
.012
.023
.032

NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS
OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN
CENTERS.
3. 01 & E1 DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE PROTRUSION IS .010 PER SIDE.
ND & NE REPRESENT NUMBERS OF LEADS IN
D & E DIRECTIONS RESPECTIVELY.

PQ120-2
120
MIN
MAX
.136
.156
.010
.125
.144
.005 .008
1.224 1.232
1.098 1.106
.913 REF
1.224 1.232
1.098 1.106
.913 REF
.026 .037
30/30
.026 sse
.012
.018
.094
.094

4.3

PQ128-2
128
MIN
MAX
.136
.156
.010
.125
.144
.005 .008
1.224 1.232
1.098 1.106
.976 REF
1.224 1.232
1.098 1.106
.976 REF
.026 .037
32/32
.0315 sse
.012 .018
.063
.063

39

PACKAGE DIAGRAt.i OUTLINES

PLASTIC QUAD FLATPACKS (Continued)
144-208 LEAD PLASTIC QUAD FLATPACK (EIAJ)

DWG :/I

1# OF LDS (N)
SYMBOLS
A
A1
A2
e
D
D1
D3
E
E1
E3
L
ND/NE
P

w

ZD
ZE

PQ144-2
144
MIN
MAX
;156
.136
.010
.125
.144
.005 .008
1.224 1.232
1.098 1.106
.896 RF
1.224 1.232
1.098 1.106
.896 REF
.026 .037
36/36
.026 BSe
.009
.014
.103
.103

PQ160-2
160
MIN
MAX
.136
.156
.010
.125
.144.005 .008
1.224 1.232
1.098 1.106
.998 REF
1.224 1.232
1.098 1.106
.998 REF
.026
.037
40/40
.026 Bse
.009
.014
.052
.052

PQ184-2
184
MIN
MAX
.136
.156
.010
.125
.144.005 .008
1.224 1.232
1.098 1.106
.886 REF
1.224 1.232
1.098 1.106
.886 REF
.026 .037
46/46
.020 Bse
.009
.014
.108
.108

4.3

PQ208-2
208
MIN
MAX
.156
.136
.010
.125
.144.005
.008
1.224 1.232
1.098 1.106
1.004 REF
1.224 1.232
1.098 1.106
1.004 REF
.026
.037
52/52
.020 BSe
.009
.014
.049
.049

I

40

PACKAGE DIAGRAM OUTLINES

PLASTIC LEADED CHIP CARRIERS
20-84 LEAD PLCC (SQUARE)
A1

45' x .045

C

B

SEAnNG PLANE
NOTES:
1.
2.
3.
4.
5.
6.

I

ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
BSC - BASIC LEAD SPACING BETWEEN CENTERS
D & E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE
ANOTHER WITHIN .004" AT THE SEATING PLANE.
ND & NE REPRESENT NUMBER OF LEADS IN D & E DIRECTIONS
RESPECTIVEL Y.
D1 & E1 SHOULD BE MEASURED FROM THE BODOM OF THE PKG.

DWG #
OF LOS
SYMBOL
A
A1
B
b1
e
e1
0
01
D2/E2
D3/E3
E
E1

e
ND/NE

J20-1
20
MIN MAX
.165 .180
.095 .115
.026 .032
.013 .021
.020 .040
.008 .012
.385 .395
.350 .356
.290 .330
.200 REF
.385 .395
.350 .356
.050 Bse
5

J28-1
28
MIN MAX
.165 .180
.095 .115
.026 .032
.013 .021
.020 .040
.008 .012
.485 .495
.450 .456
.390 .430
.300 REF
.485 .495
.450 .456
.050 Bse
7

J44-1
44
MIN MAX
.165 .180
.095 .115
.026 .032
.013 .021
.020 .040
.008 .012
.685 .695
.650 .656
.590 .630
.500 REF
.685 .695
.650 .656
.050 Bse
11

J52-1
52
MIN MAX
.165 .180
.095 .115
.026 .032
.013 .021
.020 .040
.008 .012
.785 .795
.750 .756
.690 .730
.600 REF
.785 .795
.750.756
.050 Bse
13

4.3

J68-1
68
MIN MAX
.165 .180
.095 .115
.026 .032
.013 .021
.020 .040
.008 .012
.985 .995
.950 .956
.890 .930
.800 REF
.985 .995
.950 .956
.050 Bse
17

J84-1
84
MIN MAX
.165 .180
.095 .115
.026 .032
.013 .021
.020 .040
.008 .012
1.185 1.195
1.150 1.156
1.090 1.130
1.000 REF
1.185 1.195
1.150 1.156
.050 Bse
21

41

PACKAGE DIAGRAt.i OUTLINES

PLASTIC LEADED CHIP CARRIERS (Continued)
18-32 LEAD PLCC (RECTANGULAR)

m

+

--I+-

-H---

E1

~-bJ
t

E

B

D2

_1
C
A1

SEATlNG

PLANE~
I

t--

DWG

#

II

#

OF LDS

I

E2

J18-1
18

----l

J32-1
32

SYMBOL

MIN

MAX

MIN

MAX

A

.120

.140

.120

.140

A1

.075

.095

.075

. 095

B

.026

.032

.026

.032

b1

.013

.021

.013

.021

C

.015

.040

.015

.040

C1

.008

.012

.008

.012

D

. 320

.335

.485

.495

.449

D1

.289

. 293

D2

.225

.265

D3
E

.150 REF

.453
.390 . .430
.300 REF

.520

.535

.585

.595

E1

.489

.493

.549

·.553

E2

.422

.465

.490

.530

E3

.200 REF

.400 REF

e

.050 BSC

.050 BSC

4/5

7/9

ND/NE

NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS
OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN
CENTERS .
3. D & E DO NOT INCLUDE MOLD FLASH OR
PROTRUSIONS.
4. FORMED LEADS SHALL BE PLANAR WITH
RESPECT TO ONE ANOTHER WITHIN .004"
AT THE SEATING PLANE.
5. ND & NE REPRESENT NUMBERS OF LEADS IN
. D & E DIRECTIONS RESPECTIVELY.
6. D1 & E1 SHOULD BE MEASURED MEASURED
FROM THE BOnOM OF THE PACKAGE .

4.3

42

PACKAGE DIAGRAtwi OUTLINES

PLASTIC PIN GRID ARRAYS
68-208 PIN PGA (CAVITY UP)
1-----------11

LI

+++++++++

+++++++++++

I gog
II ::
++
I

11

::jJ
E1

E

++
+++++++++

AE~1~

~t,- - - -.-f-t -'~tt ~ ~ ~ ~ ~ ~ ~ tt ~ I ,
A

SEA nNG PLANE

,

-Jel-

¢C-JI-

NOTES:
1.
2.
3.
4.
5.
6.
7.

ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
Bse - BASIC PIN SPACING BETWEEN CENTERS.
SYMBOL "M" REPRESENTS THE PGA MA mix SIZE.
SYMBOL "N" REPRESENTS THE NUMBER OF PINS.
DIM." A" INCLUDES BOTH THE PKG BODY & THE LID. IT DOES NOT INCLUDE HEATSINK OR
OTHER ATTACHED FEATURES.
PIN DIAMETER "c" EXCLUDES SOLDER DIP OR OTHER LEAD FINISH.
PIN TIPS MAY HAVE RADIUS OR CHAMFER.
DWG No.

# OF PINS eN)
SYMBOLS
A
C
D
01
E
E1

e
L
M
Q

PG 68-2
68 PIN
MAX
MIN
.115
.160
.016
.020
1.140
1.180
1.000 SSC
1.140
1.180
1.000 SSC
.100 SSC
.100
.160
11
.040
.070

PG 84-2
84 PIN
MAX
MIN
.160
.115
.016
.020
1.140
1.180
1.000 sse
1.140
1.180
1.000 sse
.100 sse
.100
.160
11
.040
.070

4.3

PG 208-2
208 PIN
MAX
MIN
.160
.115
.016
.020
1.740
1.780
1.600 sse
1.740
1.780
1.600 sse
.100 sse
.100
.160
17
.040
.070

43

COMPLEX LOGIC PRODUCTS

II

COMPLEX LOGIC PRODUCTS
The need for high performance building blocks of ever
increasing complexity is the basis for many of today's innovative design solutions. lOT's Complex Logic product line addresses this need by combining lOT's sub-micron CEMOS
process with highly sophisticated design tools to produce
VLSI building blocks that satisfy the most demanding system
requirements. lOT's Complex Logic products are divided into
four functional areas:
Error Detection and Correction
Graphics
Read-Write Buffers
DSP and Microslice

Error Detection and Correction (EDC)
Today's high performance systems are becoming increasingly DRAM intensive. lOT has developed a range of high
performance CEMOS EDC devices that eliminate the performance penalties once associated with these circuits while
assuring the designer of the continuous, error free operation
necessary in such systems. lOT's family of EDC products
offers the designer a choice of 16, 32, or 64 bit devices with
either single bus orflow through operation. These devices are
capable of detecting and correcting errors in as little as 20ns.

Graphics
The demand for performance intensive graphics in applications like 3D modelling, high performance workstations, XWindows terminals, and multimedia screens requires designs
using high performance graphics building blocks. lOT offers a
range of products in this area from PaletteDAC's running at up
to 165 MHz for true and pseudo-color displays to video speed
flash AJD converters. lOT intends to release future building
blocks that will enable a designer to easily implement all the
functions necessary to gain a competitive edge in graphics
systems.

Read-Write Buffers
The current generation of RISC and elsc microprocessors
depend on secondary cache memory for their best performance. lOT's newly released 73200 family of write buffers
provide the designerwith a flexible approach to meeting these
requirements in his system.

DSP and Microslice Processors
Digital signal processing applications have always demanded extremely high performance building blocks. lOT
continues to offer a selection of the world's fastest fixed point
DSP elements including multipliers, multiplier/accumulators,
ALU's and microslice processors. These components enable
the construction of customized, high performance architectures and instruction sets.

Quality
All lOT Complex Logic products are manufactured on a
MIL-STD-883, Class B compliant manufacturing line. lOT
military products offer: a number of DESC qualified product
options; radiation tolerant and radiation enhanced versions;
package options including hermetic 01 P, LCC and flat pack.
All lOT commercial products are manufactured using the
same military qualified production I~ne and, adhere .to strict
quality requirements developed dunng lOT s long history of
supply to military customers. lOT commercial products are
available in a variety of packages including through hole and
surface mount configurations.

The Future
lOT's Complex Logic product line will continue to upgrade
the performance of existing products while at the same time
developing the products and architectural enhancements that
will facilitate the design of the systems of the future. Our goal
is to provide the designer with components of the highest
performance, integration level, and functionality possible.

5.0

II

TABLE OF CONTENTS
COMPLEX LOGIC PRODUCTS

PAGE

DSP AND MICROSLICETM PRODUCTS

IOT39C01
IOT39C10
lOT49C402
IOT49C410
IOT721 OL
10T7216L
10T7217L
IOT7381L
IOT7383L

4-Bit Microprocessor Slice ............................................................................................. 5.1
12-Bit Sequencer ...........................................................................................................5.2
16-Bit Microprocessor Slice ........................................................................................... 5.3
16-Bit Sequencer ........................................................................................................... 5.4
16 x 16 Parallel Multiplier-Accumulator ......................................................................... 5.5
16 x 16 Parallel Multiplier .............................................................................................. 5.6
16 x 16 Parallel Multiplier (32 Bit Output) ...................................................................... 5.6
16-Bit CMOS Cascadable ALU ..................................................................................... 5.7
16-Bit CMOS Cascadable ALU ..................................................................................... 5.7

READIWRITE BUFFER PRODUCTS

IOT73200L
IOT73201 L
IOT73210
IOT73211

16-Bit CMOS Multilevel Pipeline Register ..................................................................... 5.8
16-Bit CMOS Multilevel Pipeline Register ..................................................................... 5.8
Fast Octal Register Transceiver w/Parity ...................................................................... 5.9
Fast Octal Register Transceiver w/Parity ...................................................................... 5.9

ERROR DETECTION AND CORRECTION PRODUCTS

IDT39C60
IDT49C460
IDT49C465
IDT49C466

16-Bit Cascadable EDC ...............................................................................................5.10
32-Bit Cascadable EOC ............................................................................................... 5.11
32-Bit CMOS Flow-ThruEDC Unit ................................................................................ 5.12
64-BIT CMOS Flow-ThruEOC Unit ............................................................................... 5.13

GRAPHICS PRODUCTS

IDT75C457
IDT75C458
IDT75C48
IDT75C58

CMOS Single 8-Bit PaletteOACTM for True Color Applications .................................... 5.14
Triple 8-Bit PaletteOACTM ............................................................................................. 5.15
8-Bit Flash AOC ............................................................................................................ 5.16
8-Bit Flash AOCwith Overflow Output ......................................................................... 5.17

5.0

2

(;)®
Integroated Device Technology, Inc.

IDT39C01C
IDT39C01D
IDT39C01E

4-BITCMOS
MICROPROCESSOR
SLICE

FEATURES:

DESCRIPTION:

The IDT39C01 s are high-speed, cascadable ALUs which
• Low-power CEMOSTM
-Icc (max.)
can be used to implement CPUs, peripheral controllers and
Military: 35mA
programmable microprocessors. The IDT39C01 's
Commercial: 30mA
microinstruction flexibility allows for easy emulation of most
Fast
digital computers.
- IDT39C01 C - meets 2901 C speeds
This extremely low-power yet high-speed ALU consists of
-IDT39C01 0 - 20% speed upgrade
a 16-word-by-4-bit dual-port RAM, a high-speed ALU and the
- IDT39C01 E - 40% speed upgrade
required shifting, decoding and multiplexing logic. It is
expandable in 4-bit increments, contains a flag output along
• Eight-function ALU
- Performs addition, two subtraction operations and five
with three-state data outputs, and can easily use eithera ripple
logic functions on two source operands
carry or fulliookahead carry. The nine-bit microinstruction
word is organized into three groups of three bits each and
• Expandable
- Longer word lengths achieved through cascading any
selects the ALU destination register, ALU source operands
number of IDT39C01s
and the ALU function.
The IDT39C01 is fabricated using CEMOSTM, a CMOS
• Four status flags
technology designed for high-performance and high- Carry, overflow, negative and zero
• Pin-compatible and functionally equivalent to all versions reliability. It is a pin-compatible, performance-enhanced,
of the 2901
functional replacement for all versions of the 2901.
• Available in 40-pin DIP and 44-pin LCC
Military grade product is manufactured in compliance with
• Military product available compliant to MIL-STD-883 and the latest version of MIL-STD-883, Class B.
__D_E_S_C
__
S_ta_n_d_ar_d_M_i_lit_a_ry_D_r_a_W_in_g_(S_M
__
D_}_5_9_62_-_8_85_3_5___________________________________________

FUNCTIONAL BLOCK DIAGRAM
RAM 0

cp--~=====r1=======~
03

READ ADDRESS
READIWRITE ADDRESS

D I ----r--.-=
INSTRUCTION

(1)

r---~~--------~----_,~G
J5

c n+4

~

______________

~~

____

F3 (SIGN)
OVR

~~F=O

YI

2590 drw Ot

CEMOS is a trademark of Integrated Device Technology Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
(1:>1990 Integrated Device Technology. Inc.

5.1

APRIL 1990
DSC-900012

1

II

IDT39C01C/D/E
4-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION
A3
A2
Al
Ao
16
Is
17
RAM3
RAMo
Vee
F=O
10
11
12
CP
03
80
81
82
83

40
39
38
37
36
35
34
33
32
31
30

DE
V3
V2
VI
Vo
]5
OVR
Cn+4

G

29
28
27
26
25
24
23
22
21

F3
GND
Cn
14
15
13
00
01
02
03
00

777;;LJ~;:;;~~ '"
[:t

Is

7

17

8

1

. 38

39

RAM 3

9

37

RAMo

10

36

Vee

11

F=O
10
11
12

12

35

15

31

CP
NC

16

30

17

29

L44-1

34

13

33

14

32

~~~~~~~~~~~

2590 drw 02

NC

[j ]5
[j. OVR
[j Cn+4

/

[:t
[:t
[:t
[:t
[:t

G

ct
[:t

F3
GNO
Cn
14
15
13

2590 drw03

DIP
TOP VIEW

LCC
TOP VIEW

PIN DESCRIPTIONS
Pin Name

I/O

Description

Ao - A3

I

Four address inputs to the register file which select one register and displays its contents through the A port.

Bo - B3

I

Four address inputs to the register file which select one of the registers in the file, the contents of which is
displayed through the B port. They also select the location into which new data can be written when the clock
goes LOW.

10 - 18

I

Nine instruction control lines which determine what data source will be applied to the ALU 1(0, 1,2), what function
the ALU will perform 1(3,4,5) and what data is to be deposited in the a Register or the register file 1(6,7,8).

Do - 03

I

Four-bit direct data inputs which are the data source for entering external data into the device. Do is the LSB.

Yo - Y3

a

Four three-state output lines which, when enabled, display .either the four outputs of the ALU or the data on the A
port of the register stack. This is determined by the destination code 1(6,7,8).

F3

a
a

F=O
Cn

I

Cn+4

a

03

I/O

Both bidirectional lines function identically to 03 and RAM3 lines except they are the LSB of the
RAM.

I

OVR

a
a

CP

I

G, P

Carry-out of the internal ALU.
Bidirectional lines controlled by 1(6, 7, 8). Both are three-state output drivers connected to the TIL-compatible
CMOS inputs. When the destination code on 1(6,7,8) indicates an up shift, the three-state outputs are enabled, the
MSB of the a Register is available on the 03 pin and the MSB of the ALU output is available on the RAM3 pin.
When the destination code indicates a down shift, the pins are the data inputs to the MSB of the a Register and
the MSB of the RAM.

RAMo
OE

Carry-in to the internal ALU.

I/O

RAM3

00

Most significant ALU output bit (sign-bit).
Open drain output which goes HIGH if the Fo - F3 ALU outputs are all LOW. This indicates that the result of an
ALU operation is zero (positive logic).

a Register and

Output enable on ...,ihich, when pulled HIGH, the Y outputs are OFF (high impedance). When pulled LOW, the Y
outputs are enabled.
Carry generate and carry propagate output of the ALU. These are used to perform a carry lookahead operation.
Overflow. This pin is logically the Exclusive-OR of the carry-in and carry-out of the MSB of the ALU. At the most
significant end of the word, this pin indicates that the result of an arithmetic two's complement operation has
overflowed into the sign-bit.
Clock input. LOW-to-HIGH clock transitions will change the a Register and the register file outputs. Clock LOW
time is internally the write enable time for the 16 x 4 RAM which comprises the master latches of the register file.
While the clock is LOW, the slave latches on the RAM outputs are closed, storing the data previously on the RAM
outputs. Synchronous MASTER-SLAVE operation of the register file is achieved by this.
2590tbl01
5.1

2

IDT39C01 C/D/E
4-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ALU SOURCE OPERAND CONTROL
Microcode
Mnemonic

12

It

10

AO
AB
ZO
ZB
ZA
DA
DO
DZ

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

ALU FUNCTION CONTROL

ALU Source
Operands
Octal
Code
0
1
2
3
4
5
6

7

Microcode

15

14

13

Octal
Code

ALU
Function

ADD

L

L

L

0

R Plus S

SUBR

L

L

H

1

S Minus R

H
H
L
L
H
H

L
H

2

R Minus S

R-S

3

RORS

RVS

L
H

4

RANDS

RAS

5

RANDS

RAS

L
H

6

REX-OR S

RVS

7

REX-NOR S

RV S

Mnemonic

R

S

A
A

0
B

0

0
B
A
A
0
0

0
0

D
D
D

SUBS

L

OR

L

AND

H
H
H
H

NOTRS
EXOR
EXNOR

Symbol

R+S
S-R

2590 1b1 02

2590 1b1 03

The IDT39C01 CMOS bit-slice microprocessor is
configured four bits wide and is cascadable to any number of
bits (4,8, 12, 16, etc.). Key elements which make up this fourbit microprocessor slice are: 1) the register file (16 x 4 dualport RAM) with shifter; 2) ALU and 3) 0 Register and shifter.
REGISTER FILE - RAM data is read from the A port as
controlled by the 4-bit A address field input. Data, as defined
by the B address field input, can be simultaneously read from
the B port of the RAM. This same code can be applied to the
A select and B select field with the identical data appearing at
both the RAM A port and B port outputs, simultaneously. New
data is written into the file (word) defined by the B address field
of the RAM when activated by the RAM write enable. The
RAM data input field is driven by a 3-input multiplexer that is
used to shift the ALU output data (F). It is capable of shifting
the data up one position, down one position or not shifting at
all. The other inputs to the multiplexer are from the RAM3 and
RAMo I/O pins. For a shift up operation, the RAM3 output
buffer is enabled and the RAMo multiplexer input is enabled.
During a shift down operation, the RAMo output buffer is
enabled and the RAM3 multiplexer input is enabled. Four-bit
latches hold the RAM data while the clock is LOW, with the A
port output and B port output each driving separate latches.
The data to be written into the RAM is applied from the ALU F
output.
ALU - The ALU can perform three binary arithmetic and
five logic operations on the two 4-bit input words Sand R. The
S input field is driven from a 3-input multiplexer and the R input
field is driven from a 2-input multiplexer, with both having an
inhibit capability. Both multiplexers are controlled by the 10, 11,
12 inputs. This multiplexer configuration enables the user to
select various pairs of the A, B, 0, 0 and "0" inputs as source
operands to the ALU. Microinstruction inputs (13, 14, 15) are

used to select the ALU function. This high-speed ALU also
incorporates a carry-in (Cn) input, carry propagate (p) output,
carry generate (<3) output and carry-out (Cn+4) all aimed at
accelerating arithmetic operations by the use of carry look
ahead logic. The overflow output pin (OVR) will be HIGH
when arithmetic operations exceed the two's complement
number range. The ALU data outputs (Fo, F1, F2, F3) are
routed to the RAM, 0 Register inputs and the Y outputs under
control of the 16, 17, Is control signal inputs. The MSB of the
ALU is output as F3 so the user can examine the sign-bit
without enabling the three-state outputs. An open drain
output, F = 0, is HIGH when Fo = F1 = F2 = F3 = 0 so the user
can determine when the ALU output is zero by wire-O Ring
these outputs together.
Q REGISTER - The 0 Register is a separate 4-bit file
intended for multiplication and division routines and can also
be used as an accumulator or holding register for other types
of applications. It is driven from a 3-input multiplexer. In the
no-shift mode, the multiplexer enters the ALU data into the 0
Register. In either the shift-up or shift-down mode, the
multiplexer selects the 0 Register data appropriately shifted
up or down. The 0 shifter has two ports, 00 and 03, which
operate comparably to the RAM shifter. They are controlled
by the 16, 17, Is inputs.
The clock input of the IDT39C01 controls the RAM, 0
Register and A and B data latches. When enabled, the data
is clocked into the 0 Register on the LOW-to-HIGH transition.
When the clock is HIGH, the A and B latches are open and
pass data that is present at the RAM outputs. When the clock
is LOW, the latches are closed and retain the last data
entered. When the clock is LOW and RAM EN is enabled, new
data will be written into the RAM file defined by the B address
field.

DEVICE ARCHITECTURE:

5.1

3

I

IDT39C01 C/D/E
4-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ALU DESTINATION CONTROL(1)
RAM
Function

Microcode
Mnemonic
OREG

Is
L

Octal
Code

Is

17
L

L

0

Shift

a Register
Function

Load

Shift

X

NONE

Load

NONE

RAM
Shifter

a
Shifter

Y
Output

RAMo

RAM3

ao

Q3

F

X

X

X

X

F-)O

NOP

L

L

H

1

X

NONE

X

NONE

F

X

X

X

X

RAMA

L

H

L

2

NONE

F-)8

X

NONE

A

X

X

X

X

RAMF

L

H

H

3

NONE

F-)8

X

NONE

F

X

X

X

X

RAMOD

H

L

L

4

DOWN

F/2 -) 8

DOWN

0/2 -)0

F

Fa

IN3

00

IN3

RAMD

H

L

H

5

DOWN

F/2 -) 8

X

NONE

F

Fa

IN3

00

X

RAMOU

H

H

L

6

UP

2F -) 8

UP

20-)0

F

INa

F3

INa

03

RAMU

H

H

H

7

UP

2F -) 8

X

NONE

F

INa

F3

X

03

NOTE:

2590 tbl 04

1. X = Don't care. Electrically, the shift pin is a TTL input internally connected to a three-state output which is in the high-impedance state.
B = Register Addressed by B inputs.
UP is toward MSB; DOWN is toward LSB.

SOURCE OPERAND AND ALU FUNCTION MATRIX(1)
12,1,0 Octal

Octal

ALU
Function

°

1

2

4

3

5

6

7

ALU Source

A,a

A,B

0, a

O,B

O,A

O,A

o,a

0,0

0

L
R Plus S
en = H

A+O

A+8

0

8

A

D+A

D+O

D

A+O+ 1

A+8+1

0+1

8+1

A+1

D+A+1

D+O+ 1

D+1

1

en = L

0-A-1

8-A-1

0-1

8 -1

A-1

A-D-1

0-D-1

-D-1

15,4,3

2

en =

S Minus R
en = H

O-A

8-A

0

8

A

A-D

O-D

-D

en = L

A-0-1

A-8-1

-Q-1

-8-1

-A-1

D-A-1

D-0-1

D-1

R Minus S
en = H

A-O

A-8

-Q

-8

-A

D-A

D-O

D

3

RORS

AVO

AV8

0

8

A

DVA

DVO

D

4

RANDS

AIIO

A II 8

0

0

0

DIIA

DIIO

0

5

RANDS

AIIO

AII8

0

8

A

DIIA

DIIO

0

6

REX-OR S

AVO

A V 8

0

8

A

DVA

DVO

D

7

REX-NOR S

AVO

A V 8

0

8

A

DVA

DVO

D

NOTE:
1. + = Plus; - = Minus;"

2590 tbl 05

= AND; V

= EX-OR; V = OR.

5.1

4

IDT39C01 C/D/E
4-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ALU ARITHMETIC MODE FUNCTIONS

ALU LOGIC MODE FUNCTIONS
Octal

Octal

15,4,3

12,1,0

4
4
4
4

0

3
3
3
3

1

Group
AND

5
6

0
1

OR

5
6

12,1,0

AIIO
AII8
DIIA
DIIO

0
0
0
0

0

5
6

AVO
A V 8
DVA
DVO

0
0
0
0

3
4
7

AVO
A V 8

1
1
1
2

3
4
7

2
2
2
1

3
4
7

1's Comp.

0

0-A-1
8-A-1
A-D-1
Subtract 0-D-1
(1's Camp) A-0-1
A- 8-1
D-A-1
D-0-1

0
1

6
6

5

DVA

6

DVO

7
7
7
7

0

5

AVO
A V 8
DVA

6

DVO

2

0

7
7
7
7
6
6
6

1

3
4

A

0

2

6

3
3
3
3

3
4
7

4
4
4
4

3
4
7

0
8
A
D

PASS

2

2

0
1

5
6

Function

P

0

R+S

P3P2P1PO

1

S-R

15,4,3

PASS

2
Decrement

2

1

5
6
0
1

5
6

ADD
plus one

Increment

0-1
8-1
A-1
D-1

0
8
A
D

PASS

-0-1
-8-1
-A-1
-D-1

0+ 1
8+1
A+ 1
D+1

2's Camp.
(Negate)

-0
-8
-A
-D

Subtract
(2's Camp)

O-A
8-A
A-D
O-D
A-O
A-8
D-A
D-O

P1 = R1 + S1
P2 = R2+ S2
P3 = R3+ S3
Go = RoSo
G1 = R1S1
G2 = R2S2
G3 = R3S3
C4= G3 + P3G2 + P3P2G1 + P3P2P1GO + P3P2P1POCn
C3 = G2 + P2G1 + P2P1GO + P2P1POCn
2590 tbl 06

LOGIC FUNCTIONS FOR <3,

0
8
A
D

2

Function
A+O+ 1
A+8+1
D+A+1
D+O+ 1

Po = Ro + So

AIIO
AII8
OIlA
OliO

MASK

ADD

A+Q
A+B
D+A
D+Q

Group

DEFINITIONs(1)
.
..---------, •

0
0
0
0

"ZERO"

Group

2590 tbl 07

0
8
A
D

PASS

1

1
1
1
1
2
2
2
2

B

INVERT

7

3
4
7

5
5
5
5

EX-NOR

Function

15,4,3

6
6

EX-OR

Cn= H

Cn = L

Function

NOTE:
1. + = OR

2590 tbl 08

15, Cn + 4 AND OVR (1)

I

G
G3 + P3G2 + P3P2G1 + P3P2P1GO

I

Cn+4
C4

I
I

OVR
C3V C4

Same as R + S equations, but substitute Ri for Ri in definitions

2

R-S

3

RVS

LOW

P3P2P1PO

4

RIIS

LOW

G3 + G2 + G1 + Go

5

RIIS

LOW

6

RV S

7

RVS

Same as R + S equations, but substitute Si for Si in definitions

I

P3P2P1 Po + Cn

I

P3P2P1 Po + Cn

1G3 + G2 + G1 + Go + Cn IG3 + G2 + G1 + Go + Cn

Same as R V S equations, but substitute Ri for Ri in definitions
Same as R V S equations, but substitute Ri for Ri in definitions

G3 + G2 + G1 + Go

G3 + P3G2 + P3P2G1 + P3P2P1 Po

G3 + P3G2 + P3P2G1
+ P3P2P1PO (Go + Cn)

I

(2)

2590 tbl 09

NOTES:

1. +=OR.
2. [P2 + G2P1 + G2G1PO + G2G1GoCn] V

I

[P3 + G3P2 + G3G2Pl + G3G2G1PO + G3G2G1Cn]
5.1

5

IDT39COl C/D/E
4-81T CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vee

CAPACITANCE

Rating

Com'l.

Mil.

Unit

Power Supply
Voltage

-0.5 to +7.0

-0.5 to +7.0

V

VTERM

Terminal Voltage
with Respect
to Ground

-0.5 to
Vee +0.5

-0.5 to
Vee +0.5

V

TA

Operating
Temperature

o to +70

-55 to +125

DC

TSIAS

Temperature
Under Bias

-55 to +125 -65 to +135

DC

TSTG

Storage
Temperature

-55 to +125 -65 to +150

DC

PT

Power Dissipation

1.0

1.0

W

lOUT

DC Output Current

30

30

mA

(TA

= +25°C, f = 1.0MHz)

Parameter(l)

Typ.

Unit

CIN

Input Capacitance

VIN = OV

5

pF

COUT

Output Capacitance

VOUT= OV

7

Symbol

Conditions

NOTE:
1. This parameter is sampled and not 100% tested.

pF
2590 tbl 26

NOTE:
2590 tbl 10
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS
= O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc = 5.0V ± 10%

Commercial: TA

Min.

Typ.(3)

Max.

Unit

IIH

Input HIGH Current
(AI/Inputs)

Vee = Max.
VIN = Vee

-

0.1

5

(lA

III

Input LOW Current
(AI/Inputs)

Vee = Max.
VIN =GND

-

-0.1

-5

(lA

VOH

Output High Voltage

Vee = Min.

10H = -1.0mA (MIL.)

2.4

4.3

10H = -1.6mA (COM'L.)

2.4

4.3

-

V

VIN = VIH or Vil
Vee = Min.

10l = 16mA (MIL.)

0.5

V

10l = 20mA (COM'L.)

-

0.3

VIN = VIH or Vil

0.3

0.5

Symbol

VOL

Parameter

Output Low Voltage

Test Conditions

VIH

Input HIGH Level

Guaranteed Logic HIGH Level(1)

2.0

V

Input LOW Level

Guaranteed Logic LOW Level(l)

0.8

V

loz

Output Leakage Current

Vee = Max.

VOUT= OV

-

-

-

Vil

-0.1

-10

flA

VOUT = Vee (Max.)

-

0.1

10

-30

-

-

los

Output Short Circuit Current

Vee = Max.
VOUT= OV(2)

NOTES:
1. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.
2. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
3. Vcc = 5.0V at TA +25 D C.

5.1

mA
2590tbl11

6

IDT39C01 C/D/E
4-81T CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS (Cont'd_)
= O°C to +70°C, VCC = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc = 5.0V ± 10%

Commercial: TA
VLC = 0.2V; VHC
Symbol
ICCQH

= VCC -0.2V

Test Condltlons(1)

Parameter
Quiescent Power Supply Current
, CP

= H (CMOS Inputs)

VCC

= Max.

VHC

=::;;

fcp
ICCQl

Quiescent Power Supply Current
CP

= L (CMOS Inputs)

VIH, Vil

=::;;

= 0, CP = H
= Max.
=::;;

VIH, Vil

=::;;

Typ.(3)

Max.

Unit

-

0.5

5.0

mA

-

0.5

5.0

mA

-

0.3

0.5

VlC

VCC
VHC

Min.

VlC

= 0, CP = L
= Max., VIH = 3.4V
fcp = 0
Vcc = Max.

MIL.

-

1.5

2.5

mAl

VHC

COM'L.

-

1.0

2.0

MHz

MIL.

mA

COM'L.

-

-

30

MIL.

-

-

40

COM'L.
MIL.

-

-

45

COM'L.

-

-

40

fcp
ICCT

Quiescent Input Power Supply(4)
Current (per Input @ TTL High)

ICCD

Dynamic Power Supply Current

Vcc

=::;;

VIH, Vil

=::;;

mAl
Input

VlC

Outputs Open, OE = L
Icc

Total Power Supply Current(S)

Vcc

= Max ..

IDT39C01C

Outputs Open, OE
CP

= 50 %

VHC

=::;;

=L

Duty eycle

VIH, Vil

=::;;

VlC

50% Data Duty Cycle

fcp

IDT39C010
fcp

= Max ..

VIH

= 17.5MHz

IDT39C01C

=L

fcp

= 50 % Duty Cycle
= 3.4V, Vil = O.4V

fcp

Outputs Open, OE
CP

= 15MHz

IDT39C01 E
fcp

Vcc

= 10MHz

50% Data Duty Cycle

= 10MHz

IDT39C01D

= 15MHz

IDT39C01E
fcp

= 17.5MHz

COM'L.
MIL.
COM'L.
MIL.
COM'L.
MIL.

-

30

-

25

-

35

-

30
40
35
35

II

35

2590 tbl12
NOTES:
1. These input levels should only be static tested in a noise-free environment.
2. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
3. Vcc = 5.0V at TA +25°C.
4. ICCT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out lecoH, then dividing by the total number of inputs.
5. Total Supply Current is the sum ofthe Quiescent current and the Dynamic current (at either CMOS or TTL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = ICCOH (CDH) +ICCOL (1 - CDH) + ICCT (NT X DH) + ICCD (fcp)
CDH = Clock duty cycle high period
DH = Data duty cycle TTL high period (VIN = 3.4V)
NT = Number of dynamic inputs driven at TTL levels
fcp = Clock input frequency

CMOS TESTING CONSIDERATIONS
There are certain testing considerations which must be
taken into account when testing high-speed CMOS devices
in an automatic environment. These are:
1) Proper decoupling at the test head is necessary.
Placement of the capacitor set and the value of capacitors
used is critical in reducing the potential erroneous failures
resulting from large VCC current changes. Capacitor lead
length must be short and as close to the OUT power pins
as possible.
2) All input pins should be connected to a voltage potential
during testing. If left floating, the device may begin to
oscillate causing improper device operation and possible
latchup.

5.1

3) Definition of input levels is very important. Since many
inputs may change COincidentally, significant noise at the
device pins may cause the VIL and VIH levels not to be met
until the noise has settled. To allow for this testing/board
induced noise, lOT recommends using VIL::;; OV and VIH ~
3V for AC tests.
4) Device grounding is extremely important for proper device
testing. The use of multi-layer performance boards with
radial decoupling between power and ground planes is
required. The ground plane must be sustained from the
performance board to the OUT interface board. All unused
interconnect pins must be properly connected to the ground
pin. Heavy gauge stranded wire should be used for power
wiring and twisted pairs are recommended to minimize
inductance.

7

IDT39C01C/D/E
4-81T CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
IDT39C01C
(Military and Commercial Temperature Ranges)
The tables below specify the guaranteed performance of
the IDT39C01 C over the -55°C to +125°C and O°C to +70°C
temperature ranges. VCC is specified at 5V ± 10% for military
temperature range and 5V ± 5% for commercial temperature
range. All times are in nanoseconds and are measured at the
1.5V signal level. The inputs switch between OV and 3V with
signal transition rates of 1V per nanosecond. All outputs have
maximum DC current loads.

CYCLE TIME AND CLOCK
CHARACTERISTICS
Read-Modify-Write Cycle (from
selection of A, B registers to end
of cycle)
Maximum Clock Frequency to
shift Q (50% duty cycle,
I = 432 or 632)
Minimum Clock LOW Time
Minimum Clock HIGH Time
Minimum Clock Period

Mil.

Com'l.

Unit

32

31

ns

31

32

MHz

15
15
32

15
15
31

ns
ns
ns
2590 tbl13

COMBINATIONAL PROPAGATION DELAYS(1) CL = 50pF
To Output

Y
From Input
A, B Address

D

Cn
10.1,2
13,4,5
16,7,8

A Bypass
ALU (I = 2XX)
Clock ./

F3

G, ]5

Cn+4

OVR

F=O

RAMo

00

RAM3

03

Mil. Com'J. Mil. Com'J. Mil. Com'J. Mil. Com'J. Mil. Com'l. Mil. Com'l. Mil. Com'J. MIl. Com'J. Unit

48
37
25
40
40
29
40

40
30
22
35
35
25
35

48
37
25
40
40

40
30
22
35
35

48
37
21
40
40

40
30
20
35
35

44
34

-

-

44
40

37
35

-

-

-

-

-

-

-

-

-

40

35

40

35

40

35

40

35

37
30

48
40
28
44
40

40
38
25
37
38

48
37
25
40
40

40
30
22
35
35

-

-

-

-

-

-

40

35

40

35

-

48
37
28
40
40
29

40
30
25
35
35
26

-

-

29

26

-

-

-

-

40

35

33

28

ns
ns
ns
ns
ns
ns
ns
ns
2590 tbl14

5.1

8

IDT39C01 C/D/E
4-81T CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)
CP:
Set-up Time
Before H ---+ L
Input

t

Hold Time
After H ---+ L

MIL

Com'L

Mil.

15
15

15
15

2

D

_(1)

-

en

-

-

-

-

-

A, B Source Address
B Destination Address

13,4,5

-

-

16,7,8

10

10

RAMo,3, Qo,3

-

-

10,1,2

~

tPWL

Com'l.
1 (3)

Set-up Time
Before L ---+ H
Mil.

Com'l.

30,15 + tPWL (4)

Do not change (2)

-

Mil.

Com'L

Unit

2
2

1
1

ns
ns

25

25

0

0

ns

20
30

20
30
30

0
0
0
0
0

0
0

ns

30

Do not change (2)

-

Hold Time
After L ---+ H

12

12

0
0
0

ns
ns
ns
ns

NOTES:
2590tb115
1. A dash indicates a propagation delay or set-up time constraint does not exist.
2. Certain signals must be stable during the entire clock LOW time to avoid erroneous operation.
3. Source addresses must be stable prior to the H ~ L transition to allow time to access the source data before the latches close. The A address may then
be changed. The B address could be changed if it is not a destination; i.e., if data is not being written back into the RAM. Normally A and B are not changed
during the clock LOW time.
4. The set-up time prior to the clock L ~ H transition is to allow time for data to be accessed, passed through the ALU and returned to the RAM. It includes
all the time from stable A and B addresses to the clock L ~ H transition, regardless of when the H ~ L transition occurs.

OUTPUT ENABLE/DISABLE TIMES

II

(CL = SpF, measured to O.SV
change of VOUT in nanoseconds)
Enable
Input

Output

Mil.

OE

y

25

Disable

I Com'l.
I

23

Mil.

25

I

I

Com'l.

23
2590tb116

5.1

9

IDT39C01 C/D/E
4-81T CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
IDT39C01D
CYCLE TIME AND CLOCK
CHARACTERISTICS

(Military and CommerCial Temperature Ranges)
The tables below specify the guaranteed performance of
the IDT39C01 D over the -SsoC to + 12SoC and O°C to +70°C
temperature ranges. VCC is specified at SV ± 10% for military
temperature range and SV ± S% for commercial temperature
range. Alltimes are in nanoseconds and are measured atthe
1.SV signal level. The inputs switch between OV and 3V with
signal transition rates of 1V per nanosecond. All outputs have
maximum DC current loads.

Mil.

Com'l.

Unit

Read-Modify-Write Cycle (from
selection of A, B registers to end
of cycle)

27

23

ns

Maximum Clock Frequency to
shift Q (50% duty cycle,
I = 432 or 632)

37

43

MHz

Minimum Clock LOW Time

13
13
27

11
11
23

ns

Minimum Clock HIGH Time
Minimum Clock Period

ns
ns
2590 !b117

COMBINATIONAL PROPAGATION DELAYS(1)

CL= SOpF
To Output

y
From Input
A, B Address

D
Cn
10,1,2
13,4,5

IS,7,8
A Bypass
ALU (I = 2XX)
Clock

j"

F3

G, J5

Cn+4

OVR

F=O

RAMo

00

RAM3

03

Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. MIL Com'l. Unit

33
24
18
28
27
18
26

30
21
17
26
26
16
24

33
23
17
27
27

30
20
16
25
24

33
23
14
26
26

30
20
14
24
24

33
21

-

-

28
26

24
24

-

-

-

-

-

-

-

-

27

24

26

23

26

23

25

30
20

30
24
18
25
26

-

33
25
19
29
27
-

23

27

24

-

33
24
17
27
26
-

30
21
16
24
24

26

-

ns

-

-

-

ns

-

-

ns

21

21

ns

-

-

-

ns

24

20

19

30
22
18
25
26
21

-

33
25
19
27
27
21
-

24

27

-

-

ns

ns

ns
2590 !b118

5.1

10

IDT39C01 C/D/E
4-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)

~

CP:
Set-up Time
Before H -) L
Input
A, 8 Source Address

Hold Time
After H -) L

Set-up Time
Before L -) H

Hold Time
After L -) H

Mil.

Com'l.

Mil.

Com'l.

Mil.

Com'l.

Mil.

Com'l.

Unit

11

10

0

0(3)

24,11 +

21, 10 +

2

1

ns

2

1
0
0
0
0
0
0

ns

11

10

D

_(1)

-

Cn

-

-

10.1.2

-

13.4.5

-

-

16.7.6

7

7

RAMO.3, 00.3

-

-

8 Destination Address

;r

tpWl

tPWl (4)

tPWl (4)

Do not change (2)

-

-

-

-

-

16
13
19
19

16
13
19
19

Do not change (2)

-

-

9

0
0
0
0
0

9

0

ns
ns
ns
ns
ns
ns

NOTES:
25901b119
1. A dash indicates a propagation delay or set-up time constraint does not exist.
2. Certain signals must be stable during the entire clock LOW time to avoid erroneous operation.
3. Source addresses must be stable prior to the H -+ L transition to allow time to access the source data before the latches close. The A address may then
be changed. The B address could be changed if it is not a destination: i.e .• if data is not being written back into the RAM. Normally A and B are not changed
during the clock LOW time.
4. The set-up time prior to the clock L -+ H transition is to allow time for data to be accessed. passed through the ALU and returned to the RAM. It includes
all the time from stable A and B addresses to the clock L -+ H transition. regardless of when the H -+ L transition occurs.

•

OUTPUT ENABLE/DISABLE TIMES
(CL = 5pF, measured to O.SV
change of VOUT in nanoseconds)
Enable

Disable

Input

Output

Mil.

I Com'l.

Mil.

OE

y

16

I

18

14

I

I

Com'l.

16
2590 1b120

5.1

11

IDT39C01 C/D/E
4·BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
IDT39C01E
CYCLE TIME AND CLOCK
CHARACTERISTICS

(Military and Commercial Temperature Ranges)
The tables below specify the guaranteed performance of
the I DT39C01 E over the -55°C to +125°C and O°C to +70 0
temperature ranges. vce is specified at 5V ± 10% for military
temperature range and 5V ± 5% for commercial temperature
range. All times are in nanoseconds and are measured at the
1.5V signal level. The inputs switch between OV and 3V with
signal transition rates of 1V per nanosecond. All outputs have
maximum DC current loads.

e

Mil.

Com'l.

Unit

Read-Modify-Write Cycle (from
selection of A, B registers to end
of cycle)

21

20

ns

Maximum Clock Frequency to
shift Q (50% duty cycle,
I = 432 or 632)

46

50

MHz

Minimum Clock LOW Time

10
10
21

8
8
20

ns

Minimum Clock HIGH Time
Minimum Clock Period

ns
ns
2590 tbl21

COMBINATIONAL PROPAGATION DELAYS (1) CL = 50pF
To Output

V
From Input
A, B Address

0
Cn
10,1,2

13,4,5
16,7,8

A Bypass
ALU (I = 2XX)
Clock

J

F3

G, j5

Cn +4

OVR

F=O

RAMo

00

RAM3

03

Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Unit

26
18
13
21
20
13
26

22
16
13
20
20
12
24

26
17
13
20
20

22
15
12
19
18

26
17
10
19
19

22
15
10
18
18

26
16

21
15

-

-

21
19
-

18
18
-

-

-

-

-

-

-

20

18

19

17

19

17

19

17

-

26
19
14
20
20
16
-

22
16
13
19
20
16
-

18

20

18

29
22
16
25
23

25
20
15
21
23

26
18
13
20
19

22
16
12
18
18

-

-

-

-

-

25

22

19

-

ns

16
-

16

ns

-

ns

15

15

-

ns
ns
ns
ns

ns
2590 tbl22

5.1

12

IDT39C01C/D/E
4-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)
CP:
Set-up Time
Before H ~ L
Input

t

Hold Time
After H ~ L

MIl.

Com'l.

MII_

8

7

0

A, B Source Address

B Destination Address

At

tPWL

Com'l.
0(3)

Set-up Time
Before L~ H
Mil.

Com'l.

Mil.

Com'l.

Unit

18,8+
tPWL(4)

15,7+
tPWL(4)

2

1

ns
ns

Do not change (2)

8

7

D

-(1)

-

-

Cn

-

-

-

10,1,2

-

-

13,4,5

-

-

-

16,7,8

5

5

RAMO,3, 00,3

-

-

2

1

-

12

12

0

0

ns

10

10

0

0

ns

-

14

14

0

0

ns

-

14

14

0

0

ns

0

0

ns

0

0

ns

Do not change (2)

-

Hold Time
After L ~ H

-

9

9

NOTES:
1. A dash indicates a propagation delay or set-up time constraint does not exist.
2. Certain signals must be stable during the entire clock lOW time to avoid erroneous operation.
3. Source addresses must be stable prior to the H --+ l transition to allow time to access the source data before the latches close. The A address
may then be changed. The Baddress could be changed if it is nota destination; i.e., if data is not being written back into the RAM. Normally
A and 8 are not changed during the clock lOW time.
4. The set-up time prior to the clock l--+ H transition is to allow time for data to be accessed, passed through the AlU and returned to the RAM.
It includes all the time from stable A and 8 addresses to the clock l--+ H transition, regardless of when the H --+ l transition occurs .

2590 tbl23

•

OUTPUT ENABLE/DISABLE TIMES
(Cl = SpF, measured to O.SV
change of VOUT in nanoseconds)
Enable
Input

Output

Mil.

OE

y

14

I
I

Disable

Com'l.

Mil.

10

12

I

I

Com'l.

12
2590 tbl24

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to 3.0V
1V/ns
1.5V
1.5V
See Figure 4
2590 tbl25

Test

Switch

Open Drain
Disable Low
Enable Low
All other Tests

Closed

Open
2590 tbl27

5.1

13

IDT39C01 C/D/E
4-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

INPUT/OUTPUT INTERFACE CIRCUIT

Vee

ESD
PROTECTION

INPUTS l J - - - - I '

OUTPUTS

" 'f'"

2590 drw 05

Figure 1. Input Structure (All Inputs)

--I>o-1 '00L
.

.

Figure 2. Outputs Structure (All Outputs Except F=O)

OUTPUTS'

. ,

2590 drw 06

'Figure 3. Output Structure (F=O Only)

TEST CIRCUIT LOAD

Vee

+ 7.0V

o---e

DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator'
'

Figure 4. Switching Test Circuits

5.1

14

IDT39C01 C/D/E
4·BIT CMOS MICROPROCESSOR SLICE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XXXXX

x

Device Type

Process!
Temperature

T~-1

BLANK
B

Commercial (O°C to + 70°C)
Military (- 55°C to + 125°C)
Compliant to MIL·STD·883. Class B

P
D

Plastic DIP
CERDIP
LCC

L
C

D

E
39C01

Four·Bit Microprocessor Slice
High-Speed Four-Bit Microprocessor Slice
Ultra-High-Speed Four·Bit CMOS Microprocessor Slice

2590 drw 08

II
I

5.1

15

t;)®
Integrated Device Technology, Inc.

microprogram sequencers are intended for use in controlling
the sequence of microinstructions executed in the
microprogram memory. The IDT39C10s provide several
conditional branch instructions that allow branching to any
microinstruction within the 4K microword address space. A
33-deep last-inlfirst-out stack provides for a very powerful
microprogram subroutine return linkage and looping capability.
With this depth of a microprogram return stack, the
microprogrammer has maximum flexibility in nesting
subroutines and loops. The counter contained in the
IDT39C1 Os provides for microinstruction loop counts of up to
4096, in terms of total count length.
The IDT39C10s provide a 12-bit address to the
microprogram memory. This microprogram sequencerselects
one of four sources for the address. These are (1) the
microprogram address register, (2) external direct input, (3)
internal register counter and (4) the 33-deep LIFO stack. The
microprogram counter usually contains an address that is one
greater than the microinstruction currently being executed in
the microprogram pipeline register.
The IDT39C10s are fabricated using CEMOS, a CMOS
technology designed for high-performance and high-reliability.
The devices are pin-compatible, performance-enhanced,
functional replacements for the 291 OA.

FEATURES:
• Low-power CEMOSTM
Icc (max.)
Military: 90mA
Commercial: 75mA
•

•
•
•
•
•
•
•
•

IDT39C10B
IDT39C10C

12-BIT CMOS
MICROPROGRAM
SEQUENCER

Fast
IDT39C10B matches 2910A speeds
I DT39C 1OC 30% speed upgrade
33-Deep stack
Accommodates highly nested loops and subroutines
12-bit address width
12-bit internal loop counter
16 powerful microinstructions
Three output enables control 3-way branch
Available in 40-pin DIP and 44-pin LCC/PLCC
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing# 5962-87708 is listed on this
function. Refer to Section 2/page 2-4.

DESCRIPTION:
The IDT39C1 0 microprogram sequencers are designed for
use in high-performance microprogram state machines. These

FUNCTIONAL BLOCK DIAGRAM
01

DECREMENT/
HOLD/LOAD

CI

II

12
VI

CEMOS and MICROSLICE are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
=a~a~6~

2589 drw 03

PLCC/LCC
TOP VIEW

DIP
TOP VIEW

•

PIN DESCRIPTIONS
Pin Name

1/0

Description

01

I

Direct input to
register/counter
multiplexer Do is LSB.

II

I

Selects one-of-sixteen instructions.

CC

I

Used as test criterion. Past test is a LOW
onCC.

CCEN

I

Whenever the signal is HIGH, CC is ignored
and the operates as though CC were true
(LOW).

CI

I

Low order carry input to incrementer for
microprogram counter.

RLD

I

When LOW forces
counter regardless
condition.

OE

I

Three-state control of YI outputs.

CP

I

Triggers all internal state changes at LOWto-HIGH edge.

YI

a

FULL
PL

a
a

MAP

a

Can select #2 source (usually Mapping
PROM or PLA) as direct input source.

VECT

a

Can select #3 source (for example, Interrupt
Starting Address) as direct input source.
25891bIOl

and

loading of register/
or
instruction
of

Address to microprogram memory.
LSB, Yll is MSB.

'It is

Indicates that 33 items are on the stack.
Can select #1 source (usually
Register) as direct input source.

Pipeline

5.2

2

IDT39C10B/C
12-BIT CMOS MICROPRGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PRODUCT DESCRIPTION
The IDT39C1 Os are high-performance CMOS microprogram
sequencers that are intended for use in very high-speed
microprogrammable microprocessor applications. The
sequencers allow for direct control of up to 4K words of
microprogram.
The heart of the microprogram sequencers is a 4-input
multiplexer that is used to select one of four address sources
to select the next microprogram address. These address
sources include the register/counter, the direct input, the
microprogram counter or the stack as the source for the
address of the next microinstruction.
The register/counter consists of twelve D-type flip-flops
which can contain either an address or a count. These edgetriggered flip-flops are under the control of a common clock
enable, as well as the four microinstruction control inputs.
When the load control (RLD) is LOW, the data at the 0 inputs
is loaded into this register on the LOW-to-HIGH transition of
the clock. The output of the register/counter is available at the
multiplexer as a possible next address source for the microcode. Also, the terminal count output associated with the
register/counter is available at the internal instruction PLA to
be used as condition code input for some of the microinstructions. The IDT39C10s contain a microprogram counter
that usually contains the address of the next microinstruction
compared to that currently being executed. The microprogram counter actually consists of a 12-bit incrementer followed by a 12-bit register. The microprogram counter will
increment the address coming out of the sequencer going to
the microprogram memory if the carry-in input to this counter
is HIGH; otherwise, this address will be loaded into the
microprogram counter. Normally, this carry-in input is set to
the logic HIGH state so that the incrementer will be active.
Should the carry-in input be set LOW, the same address is
loaded into the microprogram counter. This is a technique that
can be used to allow execution of the same microinstruction
several times.
There are twelve D-inputs on the I DT39C 1Os that go
directly to the address multiplexer. These inputs are used to
provide a branch address that can come directly from the
microcode or some other external source. The fourth input
available to the multiplexer for next address control is the 33deep, 12-bit wide LIFO stack. The LIFO stack provides return
address linkage for subroutines and loops. The IDT39C10s
contain a built-in stack pointer that always points to the last
stack location written. This allows for stack reference operations, usually called loops, to be performed without popping
the stack.
The stack pointer internal to the IDT39C1 Os is actually an
up/down counter. During the execution of microinstructions
one, four and five, the PUSH operation may occur depending
on the state of the condition code input. This causes the stack
pointer to be incremented by one and the stack to be written
with the required return linkage (the value contained in the
microprogram counter). On the microprogram cycle following
the PUSH, this new return linkage data that was in the
microprogram counter is now at the new location pointed to by

5.2

the stack pointer. Thus, any time the multiplexer looks at the
stack, it will see this data on the top of the stack.
During five different microinstructions, a pop operation
associated with the stack may occur. If the pop occurs, the
stack pointer is decremented at the next LOW-to-HIGH
transition of the clock. A pop decrements the stack pOinter
which is the equivalent of removing the old information from
the top of the stack.
The IDT39C10s are designed so that the stack pointer
linkage allows any sequence of pushes, pops or stack references to be used. The depth of the stack can grow to a full 33
locations. After a depth of 33 is reached, the FULL output goes
LOW. If further PUSHes are attempted when the stack is full,
the stack information at the top of the stack will be destroyed
but the stack pointer will not end around. It is necessary to
initialize the stack pointer when power is first turned on. This
is performed by executing a RESET instruction (Instruction 0).
This sets the stack pointer to the stack empty pOSition - the
equivalent depth of zero. Similarly, a pop from an empty stack
may place unknown data on the Y outputs, but the stack
pointer is designed not to end around. Thus, the stack pointer
will remain at the 0 or stack empty location if a pop is executed
while the stack is already empty.
The IDT39C10s' internal 12-bit register/counter is used
during microinstructions eight, nine and fifteen. During these
instructions, the 12-bit counter acts as a down counter and the
terminal count (count = 0) is used by the internal instruction
PLA as an input to control the microinstruction branch test
capability. The design of the internal counter is such that, if it
is pre loaded with a number N and then this counter is used in
a microprogram loop, the actual sequence in the loop will be
executed N + 1 times. Thus, it is possible to load the counter
with a count of a and this will result in the microcode being
executed one time. The 3-way branch microinstruction,
Instruction 15, uses both the loop counter and the external
condition code input to control the final source address from
the Y outputs of the microprogram sequencer. This 3-way
branch may result in the next address coming from the 0
inputs, the stack or the microprogram counter.
The IDT39C1 Os provide a 12-bit address at the Y outputs
that are under control of the OE input. Thus, the outputs can
be put in the three-state mode, allowing the writable control
store to be loaded or certain typesof external diagnostics to
be executed.
In summary, the IDT39C10s are the most powerful microprogram sequencers currently available. They provide the
deepest stack, the highest performance and the lowest power
dissipation for today's microprogrammed machine deSign.

IDT39C10 OPERATION
The IDT39C10s are CMOS pin-compatible implementations of the Am291 0 and 291 OA microprogram sequencers.
The I DT39C 1O's microprogram is functionally identical except
that it provides a 33-deep stack to give the microprogram mer
more capability in terms of microprogram subroutines and
microprogram loops. The definition of each microprogram
instruction is shown in the table of instructions. This table

3

IDT39C10B/C
12-81T CMOS MICROPRGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

shows the results of each instruction in terms of controlling the
multiplexer, which determines the Y outputs, and in controlling
the signals that can be used to enable various branch address
sources (PL, MAP, VECT). The operation of the register/
counter and the 33-deep stack after the next LOW-to-HIGH
transition of the clock. The internal multiplexer is used to
select which of the internal sources is used to drive the Y
outputs. The actual value loaded into the microprogram
counter is either identical to the Y output or the Y output value
is incremented by 1 and placed in the microprogram counter.
This function is under the control of the carry inputs. For each
of the microinstruction inputs, only one of the three outputs
(PL, MAP, orVECT) will be LOW. Note that this function is not
determined by any of the possible condition code inputs.
These outputs can be used to control the three-state selection
of one of the sources for the microprogram branches.
Two inputs, CC and CCEN, can be used to control the
conditional instructions. These are fully defined in the table of
instructions. The RLD input can be used to load the internal
register/counter at anytime. When this input is LOW, the data
at the D inputs will be loaded into this register/counter on the
LOW-to-HIGH transition of the clock. Thus, the RLD input
overrides the internal hold or decrement operations specified
by the various microinstructions. The OE input is normally
LOW and is used as the three-state enable for the Y outputs.
The internal stack in the IDT39C10s is a last-inlfirst-out
memory that is 12-bits in width and 33 words deep. It has a
stack pointerthat addresses the stack and always points to the
value currently on the top of the stack. When instruction 0
(RESET) is executed, the stack pointer is initialized to the top
of the stack which is, by definition, the stack empty condition.
Thus, the contents of the top of the stack are undefined until
the forced PUSH occurs. A pop performed while the stack is
empty will not change the stack pointer in any way; however,
it will result in unknown data at the Y outputs.
By definition, the stack is full any time 33 more pushes than
pops have occurred since the stack was last empty. When this
happens, the Full Flag will go LOW. This signal first goes LOW
on the microcycle after the 33 pushes occur. When this signal
is LOW, no additional pushes should be attempted or the
information on the top of the stack will be lost.

THE IDT39C10 INSTRUCTION SET
This data sheet contains a block diagram of the IDT39C10
microprogram sequencers. As can be seen, the devices are
controlled by a 4-bit microinstruction word (13 -10). Normally,
this word is supplied from one 4-bit field of the microinstruction
word associated with the entire state machine system. These
four bits provide forthe selection of one of the sixteen powerful
instructions associated with selecting the address of the next
microinstruction. Unused Y outputs can be left open; however, the corresponding most Significant D inputs should be
tied to ground for smaller microwords. This is necessary to
make sure the internal operation of the counter is proper
should less than 4K of microcode be implemented. As shown
in the block diagram, the internal instruction PLA uses the four
instruction inputs as well as the CC, CCEN and the internal
counter = 0 line for contrOlling the sequencer. This internal

5.2

instruction PLA provides all of the necessary internal control
signals to control each particular part of the microprogram
sequencer. The next address atthe Voutputsofthe IDT39C1 Os
can be from one of four sources. These include the internal
microprogram counter, the last-inlfirst-out stack, the register/
counter and the direct inputs.
The following paragraphs will describe each instruction
associated with the IDT39C1 Os. As a part of the discussion,
an example of each instruction is shown in Figure 1. The
purpose of the examples is to show microprogram flow. Thus,
in each example the microinstruction currently being executed has a circle around it. That is, this microinstruction is
assumed to be the contents of the pipeline register at the
output of the microprogram memory. In these drawings, each
of the dots refers to the time that the contents of the microprogram memory word would be in the pipeline register and is
currently being executed.
INSTRUCTION 0 JUMP 0 (JZ)
This instruction is used at power up time or at any restart
sequence when the need is to reset the stack pointer and jump
to the very first address in microprogram memory. The Jump
o instruction does not change the contents of the register/
counter.
INSTRUCTION 1 CONDITIONAL JUMP TO SUBROUTINE (CJS)
The Conditional Jump to Subroutine Instruction is the one
used to call microprogram subroutines. The subroutine
address will be contained in the pipeline register and presented
at the D inputs. If the condition code test is passed, a
branch is taken to the subroutine. Referring to the flow
diagram forthe IDT39C1 Os shown in Figure 1, we see that the
content of the microprogram counter is 68. This value is
pushed onto the stack and the top of stack pOinter is
incremented. If the test is failed, this Conditional Jump to
Subroutine instruction behaves as a simple continue. That is,
the content of microinstruction address 68 is executed next.
INSTRUCTION 2 JUMP MAP (JMAP)
This sequencer instruction can be used to start different
microprogram routines based on the machine instruction
opcode. This is typically accomplished by using a mapping
PROM as an input to the D inputs on the microprogram
sequencer. The JMAP instruction branches to the address
appearing on the D inputs. In the flow diagram shown in
Figure 1, we see that the branch actually will be the contents
of microinstruction 85 and this instruction will be executed
next.
INSTRUCTION 3 CONDITIONAL JUMP PIPELINE (CJP)
The Simplest branching contro I available in the I DT39C 10
microprogram sequencers is that of conditional jump to
address. In this instruction, the jump address is usually
contained in the microinstruction pipeline register and
presented to the D inputs. If the test is passed, the jump is

4

II

IDT39C10B/C
12-BIT CMOS MICROPRGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

taken. If the test fails, this instruction executes as a simple
continue. In the example shown in the flow diagram of Figure
1, we see that if the test is passed, the next microinstruction
to be executed is the content of address 25. If the test is failed,
the microcode simply continues to the contents of the next
instruction.

INSTRUCTION 4 PUSH/CONDITIONAL LOAD COUNTER (PUSH)
With this instruction, the counter can be conditionally
loaded during the same instruction that pushes the current
value of the microprogram counteron to the stack. Under any
condition independent of the conditional testing, the
microprogram counter is pushed on to the stack. If the
conditional test is passed, the counter will be loaded with the
value on the D inputs to the sequencer. If the test fails, the
contents ofthe counterwill not change. The PUSH/Conditional
Load Counter instruction is used in conjunction with the loop
instruction (Instruction 13), the repeat file based on the counter
instruction (Instruction 9) or the 3-way branch instruction
(Instruction 15).
INSTRUCTION 5 CONDITIONAL JUMP TO SUBROUTINE
R/PL (JSRP)
Subroutines may be called by a Condttional Jump Subroutine
from the internal register or from the external pipeline register.
In this instruction, the contents of the microprogram counter
are pushed on the stack and the branch address for the
subroutine call will taken from either the internal register/
counter or the external pipeline register presented to the D
inputs. If the conditional test is passed, the subroutine
address will be taken from the pipeline register. If the
conditional test fails, the branch address is taken from the
internal register/counter. An example of this is shown in the
flow diagram of Figure 1.
INSTRUCTION 6 CONDITIONAL JUMP VECTOR (CJV)
The Conditional Jump Vector instruction is similar to the
Jump Map instruction in that it allows a branch operation to a
microinstruction as defined from some external source, except that it is conditional. The Jump Map instruction is
unconditional. If the conditional test is passed, the branch is
taken to the new address on the D inputs. If the conditional test
is failed, no branch is taken but rather the microcode simply
continues to the next sequential microinstruction. When this
instruction is executed, the VECT output is LOW unconditionally. Thus, an external 12-bit field can be enabled on to the D
inputs of the microprogram sequencer.
INSTRUCTION 7 CONDITIONAL JUMP R/PL (JRP)
The Conditional Jump register/counter or external pipeline
register always causes a branch in microcode. This jump will
be to one of two different locations in the microcode address
space. If the test is passed, the jump will be to the address
presented on the D inputs to the microprogram sequencer. If
the conditional test fails, the branch will be to the address
contained in the internal register/counter.

5.2

INSTRUCTION 8 REPEAT LOOP COUNTER NOT EQUAL TO 0 (RFCT)
This instruction utilizes the loop counter and the stack to
implement microprogrammed loops. The start address forthe
loop would be initialized by using the PUSH/Conditional Load
Counter instruction. Then, when the repeat loop instruction is
executed, if the counter is not equal to 0, the next microword
address will be taken from the stack. This will cause a loop to
be executed as shown in the Figure 1 flow diagram. Each time
the microcode sequence goes around the loop, the counter is
decremented. When the counter reaches 0, the stack will be
popped and the microinstruction address will be taken from
the microprogram counter. This instruction performs a timed
wait or allows a single sequence to be executed the desired
number of times. Remember, the actual number of loops
performed is equal to the value in the counter plus 1.
INSTRUCTION 9 REPEAT PIPELINE COUNTER NOT EQUAL TO 0
(RPCT)
This instruction is another technique for implementing a
loop using the counter. Here, the branch address forthe loop
is contained in the pipeline register. This instruction does not
use the stack in any way as a part of its implementation. As
long as the counter is not equal to 0, the next microword
address will be taken from the D inputs of the microprogram
sequencer. When the counter reaches 0, the internal mUltiplexer will select the address source from the microprogram
counter, thus causing the microcode to continue on and leave
the loop.
INSTRUCTION 10 CONDITIONAL RETURN (CRTN)
The Conditional Return instruction is used for terminating
subroutines. The fact that it is conditional allows the subroutine eitherto be ended orto continue. Ifthe conditional test
is passed, the address of the next microinstruction will be
taken from the stack and it will be popped. If the conditional
test fails, the next microinstruction address will come from the
internal microprogram counter. This is depicted in the flow
diagram of Figure 1. It is important to remember that every
subroutine call must somewhere be followed by a return from
subroutine call in order to have an equal number of pushes
and pops on the stack.
INSTRUCTION 11 CONDITIONAL JUMP PIPELINE AND POP (CJPP)
The Conditional Jump Pipeline and Pop instruction is a
technique for exiting a loop from within the middle of the loop.
This is depicted fully in the flow diagram forthe IDT39C 1Os as
shown in Figure 1. The conditional test input for this instruction results in a branch being taken if the test is passed. The
address selected will be that on the D inputs to the microprogram sequencer and, since the loop is being terminated,
the stack will be popped. Should the test be failed on the
conditional test inputs, the microprogram will simply continue
to the next address as taken from the microprogram counter.
The stack will not be affected if the conditional test input is
failed.

5

IDT39C10B/C
12-BIT CMOS MICROPRGRAM SEQUENCER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

INSTRUCTION 12 LOAD COUNTER AND CONTINUE (LDCT)

The Load Counter and Continue instruction is used to place
a value on the D inputs in the register/counter and continue to
the next microinstruction.
INSTRUCTION 13TEST END OF LOOP (LOOP)

The Test End of Loop instruction is used as a last instruction
in a loop associated with the stack. During this instruction, if
the conditional test input is failed, the loop branch address will
be that on the stack. Since we may go around the loop a
number of times, the stack is not popped. If the conditional test
input is passed, then the loop is terminated and the stack is
popped. Notice that the loop instruction requires a PUSH to
be performed at the instruction immediately prior to the loop
return address. This is necessary so as to have the correct
address on the stack before the loop operation. It is for this
reason that the stack pointer always points to the last thing
written on the stack.
INSTRUCTION 14CONTINUE (CONT)

Continue is a simple instruction where the address for the
microinstruction is taken from the microprogram counter. This
instruction simply causes sequential program flow to the next
microinstruction in microcode memory.
INSTRUCTION 15THREE WAY BRANCH (TWB)

The Three-Way Branch instruction is used for looping while
waiting for a conditional event to come true. If the event does
not come true after some number of microinstructions, then a
branch is taken to another microprogram sequence. This is

5.2

depicted in Figure 1 showing the IDT39C10's flow diagram
and is also described in full detail in the IDT39C 1O's instruction
operational summary. Operation of the instruction is such that
any time the external conditional test input is passed, the next
microinstruction will be that associated with the program
counter and the loop will be left. The stack is also popped.
Thus, the external test input overrides the other possibilities.
Should the external conditional test input not be true, the rest
of the operation is controlled by the internal counter. If the
counter is not equal to 0, the loop is taken by selecting the
address on the top of the stack as the address out of the Y
outputs of the IDT39C10s. In addition, the counter is decremented. Should the external conditional test input be failed
and the counter also have countedto 0, this instruction ''times
out". The result is that the stack is popped and a branch is
taken to the address presented to the D inputs of the IDT39C 10
microprogram sequencers. This address is usually provided
by the external pipeline register.

CONDITIONAL TEST
Throughout this discussion we have talked about microcode passing the conditional test. There are actually two inputs
associated with the conditional test input. These include the
CCEN and the CC inputs. The CCEN input is a condition code
enable. Whenever the CCEN input is HIGH, the CC input is
ignored and the device operates as though the CC input were
true (LOW). Thus, a fail of the external test condition can
defined as CCEN equals LOW and CC equals HIGH. A pass •
condition is defined as a CCEN equal to HIGH or a CC equal
to LOW. It is important to recognize the full function of the
condition code enable and the condition code inputs in order
to understand when the test is passed or failed.

6

IDT39C10B/C
12·BIT CMOS MICROPRGRAM SEQUENCER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C10 INSTRUCTION OPERATIONAL SUMMARY
13

-I
0

1

0

Mnemonic
JZ
CJS

3

JMAP
CJP

4

PUSH

5

JSRP

6

CJV

7

JRP

8

RFCT

9

RPCT

10

CRTN

11

CJPP

12

LDCT
LOOP

2

13
14

CONT

15

TWB

CC
X

Counter
Test

PASS
FAIL
PASS
FAIL
PASS
FAIL
PASS
FAIL
PASS
FAIL

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X

=0
NOT=O
=0
NOT=O

PASS
FAIL
PASS
FAIL

X
X
X
X

PASS
FAIL
X

X

X

PASS
FAIL
X

X
X
X

PASS
PASS
FAIL
FAIL

=0
NOT=O
=0
NOT=O

Stack
CLEAR
PUSH
NC
NC
NC
NC
PUSH
PUSH
PUSH
PUSH
NC
NC
NC
NC
POP
NC
NC
NC
POP
NC
POP
NC
NC
POP
NC
NC
POP
POP
POP
NC

NC = No Charge; DEC = Decrement

Address
Source
0

D
PC
D
D
PC
PC
PC
D
R
D
PC
D
R
PC
STACK
PC
D
STACK
PC
D
PC
PC
PC
STACK
PC
PC
PC
D
STACK

Reglsterl
Counter
NC
NC
NC
NC
NC
NC
LOAD
NC
NC
NC
NC
NC
NC
NC
NC
DEC
NC
DEC
NC
NC
NC
NC
LOAD
NC
NC
NC
NC
DEC
NC
DEC

Enable
Select
PL
PL
PL
MAP
PL
PL
PL
PL
PL
PL
VECT
VECT
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
258911>102

5.2

7

IDT39C10B/C
12·BIT CMOS MICROPRGRAM SEQUENCER

o Jump Zero (JZ)

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

1 Cond JSB PL (CJS)

2 Jump Map (JMAP)

~ ~8'
!.

STACK
40
41
42
43

3 Cond Jump PL (CJP)

4 Push/Cond LD CNTR (PUSH)

65~

67 •

f

69

65~

68

26

35

8 Repeat Loop, CNTR *- 0 (RFCT)

~ STACK
~-~ (PUSH)

P

:: ---..t;;\
67
68
69 •
70

68

N

REGISTER!
COUNTER

7 Cond JUMP R/PL (JRP)

REGISTER!
~ COUNTER

11 Cond Jump PL & POP (CJPP)

30
31

9 Repeat PL, CNTR *- 0 (RPCT)

~

II

COUNTER
(LDCT)
65
66

68

67
68
69
70

12 LD CNTR & Continue (LDCT)

COUNTER

r

13 Test End Loop (LOOP)

66.

67
68

65~
66

15 Three·Way Branch (TWB)
65

66 5• t
6
67
68

40
41
42
43
44

10 Cond Return (CRTN)

66
67 •

65

14 Continue (CONT)

~

34

20
21

65

67

30
31
32
33

67

T 36

69

66

65
66

t

65

25

6 Cond Jump Vector (CJV)

66
67 •

5 Cond JSB R/PL (JSRP)

65t106

NOTES:
1. For conditions shown as Max. or Min. use appropriate value specified under Electrical Characteristics.
2. Typical values are at VCC = 5.0V, + 25°C ambient and maximum loading, not production tested.
3. Not more than one output should be shorted at one time. Duration of the circuit test should not exceed one second.
4. These input levels should only be static tested in a noise-free environment.
5. lecT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out IccoH, then dividing by the total number of inputs.
6. Total Supply Current is the sum of the Quiescent current and the Dynamic current (at either CMOS orTTL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = ICCOH (CDH) +lccoL (1 - CDH) + leCT (NT x DH) + IceD (fcp)
CDH = Clock duty cycle high period
DH = Data duty cycle TTL high period (V IN = 3.4V)
NT = Number of dynamic inputs driven at TTL levels
fcp = Clock input frequency

5.2

10

II

IDT39C10BIC
12·BIT CMOS MICROPRGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CMOS TESTING CONSIDERATIONS
There are certain testing considerations which must be
taken into account when testing high-speed CMOS devices in
an automatic environment. These are:
1) Proper decoupling at the test head is necessary. Placement of the capacitor set and the value of capacitors used
is critical in reducing the potential erroneous failures resulting from large Vcc current changes. Capacitor lead length
must be short and as close to the OUT power pins as
possible.
2) All input pins should be connected to a voltage potential
during testing. If left floating, the device may begin to
oscillate causing improper device operation and possible
latchup.

IDT39C1 DC AC ELECTRICAL
CHARACTERISTICS
I. MINIMUM SET-UP AND HOLD TIMES

OI~R

4) Device grounding is extremely important for proper device
testing. The use of multi-layer performance boards with
radial decoupling between power and ground planes is
required. The ground plane must be sustained from the
performance board to the OUT interface board; All unused
interconnect pins must be properly connected to the ground
pin. Heavy gauge stranded wire should be used for power
wiring and twisted pairs are recommended to minimize
inductance.

IDT39C1 DB AC ELECTRICAL
CHARACTERISTICS
I. MINIMUM SET-UP AND HOLD TIMES

t(H)

tIS)
Inputs

3) Definition of input levels is very important. Since many
inputs may change coincidentally, significant noise at the
device pins may cause the VIL and VIH levels not to be met
until the noise has settled. To allow for this testinglboard
induced noise, lOT recommends using VIL ~ OV and VIH ~
3V for AC tests.
.

t(H)

tIS)

Com'l.

Mil.

Com'l.

Mil.

Unit

6

7

0

0

ns

Com'l.

Mil.

Com'l.

Mil.

Unit

OI~R

16

16

0

0

ns

Inputs

OI~PC

13

15

0

0

ns

OI~PC

30

30

0

0

ns

10-3

23
15
15
6
11

25
18
18
7
12

0
0
0
0
0

0
0
0
0
0

ns

10-3
CC

ns

CCEN

ns

CI

ns

RLO

38
35
35
18
20

0
0
0
0
0

0
0
0
0
0

ns

ns

35
24
24
18
19

CC
CCEN
CI
RLD

ns
ns
ns
ns
2589 tbl 10

2589 tbl 07

II. MAXIMUM COMBINATIONAL DELAYS
y
Inputs
00-11

10-3
CC
CCEN
CP
OE(1)

Com'l.

PL, VECT, MAP
Mil.

12
15
20
25
16
20
16
20
28
33
10/10 13/13

II. MAXIMUM COMBINATIONAL DELAYS

. FULL

y

Com'l.

Mil.

Com'l.

Mil.

Unit

-

-

-

-

ns

00-11

13

15

10-3

-

-

ns

-

-

ns

CC

-

-

-

-

ns

CCEN

-

-

22

25

ns

CP

-

-

-

-

ns

OE(1)

Inputs

Com'l.

FULL

PL, VECT, MAP
Mil.

25
20
40
35
36
30
30
36
46
40
25/27 25/3C

Com'l.

Mil.

Com'l.

Mil.

Unit

-

-

ns

-

ns

-

-

30

35

-

-

-

-

31

35

ns

-

-

-

-

ns

ns
ns

NOTE:
2589 tbl 08
1. Enable/Disable. Disable times measure to O.SV change on output voltage
level with CL = SpF. Tested at CL = SOpF. correlated to SpF.

NOTE:
2589tbl11
1. EnablelDisable. Disable times measure to O.SV change on output voltage
level with CL = SpF. Tested at CL = SOpF. correlated to SpF.

III. CLOCK REQUIREMENTS

III. CLOCK REQUIREMENTS

Com'l.

Mil.

Unit
Minimum Clock LOW Time

ns

Minimum Clock HIGH Time

Minimum Clock Period

35

20
20
40

ns

Minimum Clock HIGH Time

18
17

ns

Minimum Clock Period

Minimum Clock LOW Time

2589 tbl 09

5.2

Com'l.

Mil.

Unit

20
20
50

25
25

ns

51

ns
ns
2589 tbl 12

11

IDT39C108/C
12·81T CMOS MICROPRGRAM SEQUENCER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C10B INPUT/OUTPUT INTERFACE CIRCUIT
Vee
ESD
PROTECTION

OUTPUTS

INPUTS

2589 drw 06

2589 drw 05

Figure 2. Input Structure

Figure 3. Output Structure

TEST LOAD CIRCUIT
Vee

+ 7.0V

o--e

Test

Switch

Open Drain

Closed

Disable Low
Enable Low
All other Tests

Open

25891b114
DEFINITIONS
CL = Load capacitance: includes jig and probe capacitance
Rr = Termination resistance: should be equal to Zour of the Pulse
Generator

Figure 4. Switching Test Circuits

2589 drw07

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times

GND to 3.0V

Wins

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figure 4
25891b113

5.2

12

•

IDT39C1 DB/C
12·BIT CMOS MICROPRGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

39C10
Device Type

X

X

x

Speed

Package

Process!
Temperature
Range

I

BLANK
B

Commercial (O°C to + 70°C)
Military (- 55°C to + 125°C)
Compliant to MIL-STD-883, Class B

P
D
J
L

40-Pin
40-Pin
40-Pin
40-Pin

B
C

Fast 12-Bit Microprogram Sequencer
Ultra-Fast 12-Bit Microprogram Sequencer

Plastic DIP
CERDIP
PLCC
LCC

2589 drw 08

5.2

13

(;)®

IDT49C402
IDT49C402A
IDT49C402B

16-81T CMOS
MICROPROCESSOR SLICE

Integrated Device Technology, Inc.

FEATURES:
• Functionally equivalent to four 2901s and one 2902
• IDT49C402B is 60% faster than four 2901Cs and one
2902A
• Expanded two-address architecture with independent,
simultaneous access to two 64 x 16 register files
• Expanded destination functions with 8 new operations
allowing Direct Data to be loaded directly into the dual-port
RAM and Q Register
• Clamp diodes on all inputs provide noise suppression
• Fully cascadable
• 68-pin ceramic PGA, Plastic Leaded Chip Carrier (PLCC),
and Ceramic Flatpack (25 mil centers)
• Military product compliant to MIL-STD-883, Class B

DESCRIPTION:
The IDT49C402s are high-speed, fully cascadable 16-bit
CMOS microprocessor slice units which combine the
standard functions of four 2901 s and a 2902 with additional
control features aimed at enhancing the performance of bitslice microprocessor deSigns.

The IDT49C402s include all of the normal functions
associated with standard 2901 bit-slice operation: a) a 3-bit
instruction field (10, 11, 12) which controls the source operand
selection for the ALU; b) a 3-bit microinstruction field (13,14, 15)
used to control the eight possible functions of the ALU; c) eight
destination control functions which are selected by the
microcode inputs (16, 17, 18); and d) a tenth microinstruction
input, 19, offering eight additional destination control functions.
This 19 input, in conjunction with 16, 17 and 18, allows for shifting
the Q Register up and down, loading the RAM or Q Register
directly from the D inputs without going through the ALU, and
having the RAM A data output port available at the Y output
pins of the device.
Also featured is an on-Chip dual-port RAM that contains
64-words-by-16 bits - four times the number of working
registers in a 2901.
The IDT49C402s are fabricated using CEMOSTM, a CMOS
technology designed for high performance and high reliability.
These performance-enhanced devices feature both bipolar
speed and bipolar output drive capabilities, while maintaining
exceptional microinstruction speeds at greatly reduced CMOS
power levels.

FUNCTIONAL BLOCK DIAGRAM

RAMo

0

3

4
5

6
7
8

ALU
SOURCE
ALU
FUNCTION

w

0

0

u
w
0

DESTINATION
CONTROL

DATAoUT

CEMOS is a trademark of Integrated Device Technology Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©t 990 Integrated Device Technology. Inc.

5.3

JUNE 1990
DSC-9011/2

1

II

IDT49C402lAlB
16-BIT CMOS MICROPROCESSOR SUCE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

Pin 1 indicator
for PLCC
D2

D6
D7
GND
Ds
D9
D 10
D 11
D 12
D 13
D 14

10
11
12
13
14
15
16
17
18
19
20
21
22
23

D 15
Y 15
Y 14

24
25
26

D3
D4

D5

A3

A2
A1

Ao
13
14
15
10

11
12
Vee
DE

80
81

82
83
84

2728293031323334353637383940414243
2524 drw 02

PLCC

TOP VIEW

5.3

2

IDT49C402lAlB
16-BIT CMOS MICROPROCESSOR SUCE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

53

A3
As
A4

17
la
19
MSS

00

RAM 15
015
C n + 16

RAMo
CP
Cn

Y7
Ya
Y5
Y6
Y3
Y4
Y1
Y2
Yo

P/OVR
G/F15

F=O
Y9
Y 10
Yll

Y12
Y13

Y14

•

2524 drw 03

PGA
TOP VIEW

5.3

3

IDT49C402lAlB
16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

o

~

0

0

~

N

M

V

~ ~ ~ ~ ~

c

0

~ ~

v

OO»»»»>OOO~~~

9 8 7 6 5 4 3 2 1 6867666564636261
D2
D3
D4
D5
D6
D7
GND
Ds
D9
D 10
D11
D 12
D 13
D 14
D 15
Y 15
Y 14

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

/-

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

PIN 1 IDENTIFICATION

CALL FOR PKG DRAWING
(AVAILABLE ONLY FOR
MILITARY PRODUCT)

A3
A2
A1
Ao
13
14
15
10
11
12
Vee
OE
80
81
82
83
84

2728293031323334353637383940414243
2524 drw 04

~~::~Olo~~~~~cnOl~~~~

» » > IILLO> +O::E cn LL,"'
..... C
~::E
'-' I~O
.~

--co

FLATPACK
TOP VIEW

5.3

4

IDT49C402lAlB
16-BIT CMpS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTIONS
Pin Name

1/0

Description

Ao -As

I

Six address inputs to the register file which selects one register and displays its contents through the A port.

80 - 85

I

Six address inputs to the register file which selects one of the registers in the file. the contents of which is
displayed through the 8 port. It also selects the location into which new data can be written when the clock
goes LOW.

10 - 19

I

Ten instruction control lines which determine what data source will be applied to the ALU 1(0, 1,2). what function
the ALU will perform 1(3,4,5) and what data is to be deposited in the 0 Register or the register file ~6, 7, 8, 9).
Original 2901 destinations are selected if (g is disconnected in this mode. proper (g bias is controlled by an
internal puilup resistor to Vee.

Do - D15

I

Sixteen-bit direct data inputs which are the data source for entering external data into the device ALU. 0
Register or RAM. Do is the LSB.

Yo - Y15

0

Sixteen three-state output lines which. when enabled. display e~her the sixteen outputs of the ALU or the data
on the A port of the register stack. This is determined by the destination code ~6, 7, 8, 9).

G/F15

0

A multipurpose pin which indicates the carry generate (Gl. function at the least significant and intermediate
slices or as F15. the most significant ALU.,Eutput (sign bit). GIF15 selection is controlled by the MSS pin. If MSS
= HIGH. F15 is enabled. If MSS = LOW. G is enabled.

F=O

0

Open drain output which goes HIGH if the Fo - F15 ALU outputs are ail LOW. This indicates that the result of an
ALU operation is zero (positive logic).

Cn

I

Carry-in to the internal ALU.

Cn+16

0

Carry-out of the ALU.

015

I/O

Bidirectional lines controlled by 1(6,7,8,9). Both are three-state output drivers connected to the TTL-compatible
inputs. When the destination code on 1(6, 7, 8, 9) indicates an up shift, the three-state outputs are enabled. the
MSB of the 0 Register is available on the 015. pin and the MSB of the ALU output is available on the RAM15
pin. When the destination code indicates a down shift. the pins are the data inputs to the MSB of the 0 Register
and the MSB of the RAM.

I/O

Both bidirectional lines function identically to 015 and RAM15 lines except they are the LSB of the 0 Register
and RAM.

OE

I

Output enable. When pulled HIGH. the Y outputs are OFF (high impedance). When pulled LOW. the Youtputs
are enabled.

PIOVR

0

A multipurpose pin which indicates the carry propagate (P) output for performing a carry lookahead operation or
overflow (OVR) the Exclusive-OR of the carry-in and carry-out of the ALU MSB. OVR. at the most significant
end of th!!. word. indicates that the result of an arithmetic two'S complement operation has overflowed intoJhe
sign bit. PIOVR selection is controlled by the MSS pin. If MSS = HIGH. OVR is enabled. If MSS = LOW. P is
enabled.

CP

I

The clock input LOW-to-HIGH clock transitions will change the 0 Register and the register file outputs. Clock
LOW time is internally the write enable time for the 64 x 16 RAM. While the clock is LOW. the slave latches on
the RAM outputs are closed. storing the data previously on the RAM outputs. Synchronous MASTER-SLAVE
operation of the register file is achieved by this.

MSS

I

When HIGH. enables OVR and F15 on the PIOVR and G/F15 pins. When LOW. enables G and P on these pins.
If left open. internal pullup resistor to Vee provides declaration that the device is the most significant slice.

RAM15

00
RAMo

25241b101

5.3

5

•

IDT49C402lAlB
16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DEVICE ARCHITECTURE
The IDT49C402 CMOS bit-slice microprocessor is configured sixteen bits wide and is cascadable to any numberof bits
(16, 32, 48, 64). Key elements which make up this 16-bit
microprocessor slice are the 1) register file (64 x 16 dual-port
RAM) with shifter; 2) ALU and 3) 0 Register and shifter.
REGISTER FILE - A 16-bit data word from one of the 64
RAM registers can read from the A port as selected by the
6-bit A address field. Simultaneously, the same data word, or
any other word from the 64 RAM registers, can be read from
the B port as selected by the 6-bit B address field. New data
is written into the RAM register location selected by the B
address field during the clock (CP) LOW time. Two sixteenbit latches hold the RAM A port and B port during the clock
(CP) LOW time, eliminating any data races. During clock
HIGH, these latches are transparent, reading the data
selected by the A and B addresses. The RAM data input field
is driven from a four-input mUltiplexer that selects the ALU
output or the D inputs. The ALU output can be shifted up one
pOSition, down one position or not shifted. Shifting data
operations involves the RAM 15 and RAMo I/O pins. For a shift
up operation, the RAM shifter MSB is connected to an enabled
RAM 151/0 output, while the RAMo I/O input is selected as the
input to the LSB. During a shift down operation, the RAM
shifter LSB is connected to an enabled RAMo I/O output, while
the RAM15 I/O input is selected as the input to the MSB.
ALU - The ALU can perform three binary arithmetic and
five logic operations on the two 16-bit input words Sand R.
The S input field is driven from a 3-input multiplexer and the R
input field is driven from a 2-input multiplexer, with both having
a zero source operand. Both multiplexers are controlled by
the 1(0, 1,2) inputs. This multiplexer configuration enables the
userto select the various pairs of the A, B, D, 0 and "0" inputs
as source operands to the ALU. Microinstruction inputs 1(3,4,
5) are used to select the ALU function. This high-speed ALU
cascades to anyword length, providing carry-in (Cn), carry-out
(Cn+16) and an open-drain (F = 0) output. When all bits of the

5.3

ALU are zero, the pull-down device of F = 0 is off, allowing a
wire-QR of this e!,n over all cascaded devices. Multipurpose
pins G/F15 and P/OVR are aimed at accelerating arithmetic
operations. For intermediate and least Significant slices, the
~SS pin is programmed LS}W, selecting the carry-generate
(G) and carry propagate (P) output functions to be used by
carry lookahead logic. For the most significant slice, MSS is
programmed HIGH, selecting the sign-bit (F15) and the two's
complement overflow (OVR) output functions. The sign bit
(F15) allows the ALU sign bit to be monitored without enabling
the three-state ALU outputs. The overflow (OVR) output is
high when the two's complement arithmetic operation has
overflowed into the sign bit, as logically determined from the
Exclusive -OR of the carry-in and carry-out of the most
significant bit of the ALU. The ALU data outputs are available
at the three-state outputs Y(0-15) or as inputs to the RAM
register file and 0 register under control of the 1(6, 7, 8, 9)
instruction inputs.
Q REGISTER - The 0 Register is a separate 16-bit file
intended for multiplication and division routines and can also
be used as an accumulator or holding register for other types
of applications. It is driven from a 4-input multiplexer. In the
no-shift mode, the multiplexer enters the ALU F output or
Direct Data into the 0 Register. In either the shift up or shift
down mode, the multiplexer selects the 0 Register data
appropriately shifted up or down. The 0 shifter has two ports,
Qo and 015, which operate comparably to the RAM shifter.
They are controlled by the 1(6, 7, 8, 9) inputs.
The clock input of the IDT49C402 controls the RAM, 0
Register and A and B data latches. When enabled, the data
is clocked into the 0 Register on the LOW- to-HIGH transition.
When the clock is HIGH, the A and B latches are open and
pass data that is present at the RAM outputs. When the clock
is LOW, the latches are closed and retain the last data
entered. When the clock is LOW and 1(6,7,8,9) define the RAM
as the destination, new data will be written into the RAM file
defined by the B address field.

6

IDT49C402lAlB
16-BIT CMOS MICROPROCESSOR SUCE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ALU SOURCE OPERAND CONTROL

ALU FUNCTION CONTROL

ALU Source
Microcode

Microcode

Operands

Mnemonic

12

It

10

Octal
Code

Aa

L

L

L

0

A

R

S
a

AB

L

L

H

1

A

B

za

L

H

L

2

0

a

ZB

L

H

H

3

0

B

ZA

H

L

L

4

0

A

ALU

12

It

10

Octal
Code

Function

ADD

L

L

L

0

R Plus S

R+S

SUBR

L

L

H

1

S Minus R

S-R

Mnemonic

Symbol

SUBS

L

H

L

2

R Minus S

R-S

OR

L

H

H

3

RORS

RVS

AND

H

L

L

4

RANDS

RAS

H

L

H

5

RANDS

RAS

DA

H

L

H

D

A

DO

H

H

L

5
6

NOTRS

D

a

EXOR

H

H

L

6

REX-OR S

R V S

DZ

H

H

H

7

D

0

EXNOR

H

H

H

7

REX-NOR S

RVS

2524 Ibl 02

ALU ARITHMETIC MODE FUNCTIONS
Octal

Cn= L

15,4,3

12, 1,0

0
0
0
0

0
1
5
6

0
0
0
0

2
3
4

1
1
1
2

Group
ADD

PASS

7
2

3
4
7

2
2
2
1

2
3
4
7

1
1
1
1
2
2
2
2

0
1
5
6
0
1
5
6

Decrement

1's Camp.

Subtract
(1's Camp)

2524 Ibl 04

ALU LOGIC MODE FUNCTIONS
Octal

Cn=H

Function
A+Q
A+B
D+A
D+Q
Q
B
A
D
Q-1
B-1
A-1
D-1
-0-1
-B-1
-A-1
-D-1
Q-A-1
B-A-1
A-D-1
Q-D-1
A-Q-1
A-B-1
D-A-1
D-Q-1

Group

Function

15,4,3

12,1,0

Group

ADD
plus one

A+Q+ 1
A+B+1
D+A+1
D+Q+ 1

4
4
4
4

0
1

AND

Increment

PASS

Q+ 1
B+1
A+ 1
D+ 1

3
3
3
3

Q
B
A
D

6
6
6
6

-0
2's Camp.
(Negate)

Subtract
(2's Camp)

-B
-A
-D
Q-A
B-A
A-D
Q-D
A-Q
A-B
D-A
D-Q
2524 Ibl 03

5
6
0
1

OR

5
6
0
1

EX-OR

5

Function
AAa
AAB
DAA
DAa
AVa
AVB
DVA
DVa

6

DVa

0
1

Ava
AVB
OVA
ova

7
7
7
7

5
6

7
7
7
7

2
3
4
7

6
6
6
6

2
3
4
7

3
3
3
3

2
3
4
7

4
4
4
4

2
3
4
7

5
5
5
5

0
1

5
6

EX-NOR

INVERT

II

Ava
AVB
DVA

a
B
A

0
PASS

PASS

"ZERO"

MASK

a
B
A
D
a
B
A
D
0
0
0
0

AAa
AAB
OAA
OAa
2524 Ibl 05

5.3

7

IDT49C4021AlB
16-BIT CMOS MICROPROCESSOR SUCE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

SOURCE OPERAND AND ALU FUNCTION MATRIX(1)
12,1,0 Octal

a

1

2

Octal

ALU

15,4,3

Function

A,a

A,B

0,0

0

en= L

A+O

A+8

0

A+O+ 1

A+8+1

0-A-1

8-A-1

5

4

3

ALU Source
O,B
O,A

6

7

D,A

0,0

0,0

8

A

D+A

D+O

D

0+1

8+1

A+1

D+A+1

D+0+1

D+1

0-1

8-1

A-1

A-D-1

0-D-1

-D-1

R Plus S
1

en = H
en = L
S Minus R

2

en= H
en= L

O-A

8-A

0

8

A

A-D

O-D

-D

A-0-1

A- 8-1

-0-1

-8-1

-A-1

D-A-1

D-0-1

D-1

R Minus S

en = H

A-O

A-8

-0

-8

-A

D-A

D-O

D

3

RORS

AVO

AV8

0

8

A

DVA

DVO

D

4

RANDS

AIIO

AII8

0

0

0

DIIA

DIIO

0

5

RANDS

AIIO

AII8

0

8

A

DIIA

DIIO

0

6

REX-OR S

AVO

AV8

0

8

A

D V A

DVO

D

7

REX-NOR S

AVO

AV8

0

8

A

D V A

DVO

D

NOTE:
1. + = Plus; - = Minus; II = AND; V = EX-OR; V = OR.

25241b106

ALU DESTINATION CONTROL(1)
RAM
Function

Microcode

o Register

0
Shifter

RAM
Shifter

Function

19

Is

17

16

Hex
Code

Shift

Load

Shift

Load

Y
Output

RAMo

RAM15

Co

015

OREG

H

L

L

L

8

X

NONE

NONE

F--)O

F

X

X

X

X

Existing 2901

NOP

H

L

L

H

9

X

NONE

X

NONE

F

X

X

X

X

Functions

RAMA

H

L

H

L

A

NONE

F--)B

X

NONE

A

X

X

X

X

RAMF

H

L

H

H

B

NONE

F--)B

X

NONE

F

X

X

X

X

RAMOD

H

H

L

L

C

DOWN

F/2 --) B

DOWN

0/2--)0

F

Fo

IN15

Co

IN15

RAMD

H

H

L

H

0

DOWN

F/2 --) B

X

NONE

F

Fo

IN15

Co

X

RAMOU

H

H

H

L

E

UP

2F--)B

UP

20--)0

F

INo

F15

INo

015

RAMU

H

H

H

H

F

UP

2F--)B

X

NONE

F

INo

F15

X

015

OFF

L

L

L

L

0

NONE

D--)B

NONE

F--)O

F

X

X

X

X

New Added

DFA

L

L

L

H

1

NONE

D--)B

NONE

F--)O

A

X

X

X

X

IDT49C402

FDF

L

L

H

L

2

NONE

F--)B

NONE

D--)O

F

X

X

X

X

Functions

FDA

L

L

H

H

3

NONE

F--)B

NONE

0--)0

A

X

X

X

X

XODF

L

H

L

L

4

X

NONE

DOWN

0/2--)0

F

X

X

Co

IN15

Mnemonic

DXF

L

H

L

H

5

NONE

D--)B

X

NONE

F

X

X

Co

X

XOUF

L

H

H

L

6

X

NONE

UP

20--)0

F

X

X

INo

015

XDF

L

H

H

H

7

X

NONE

NONE

0--)0

F

X

X

X

015

NOTE:
1. X = Don't care. Electrically, the shift pin is a TIL input internally connected to a three-state output which is in the impedance state.
B = Register Addressed by B inputs.
UP is toward MSB; DOWN is toward LSB.

5.3

25241b107

8

IDT49C402lAlB
16-BIT CMOS MICROPROCESSOR SUCE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vee

CAPACITANCE

Rating

Com'l.

Mil.

Unit

Power Supply
Voltage

-0.5 to +7.0

-0.5 to +7.0

V

VTERM

Terminal Vo~age
with Respect
to Ground

TA

Operating
Temperature

TSIAS

-0.5 to
Vee + 0.5

-0.5 to
VCC + 0.5

V

o to +70

-55 to +125

°C

Temperature
Under Bias

-55 to +125 -65 to +135

°C

TSTG

Storage
Temperature

-55 to +125 -65 to +150

°C

Pr

Power Dissipation

1.5

1.5

W

lOUT

DC Output Current

50

50

rnA

(TA

= +25°C, f = 1.0MHz)

Parameter (1)

Typ.

Unit

CIN

Input Capacitance

VIN = OV

5

pF

COUT

Output Capacitance

Your = OV

7

Symbol

Conditions

NOTE:
1. This parameter is sampled and not 100% tested.

pF
252411>109

NOTE:
252411>108
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS
= O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc = 5.0V ± 10%

Commercial: TA

Min.

Typ. (2)

Max_

Unit

VIH

Input HIGH Level

Guaranteed Logic High Level (4)

2.0

-

V

Vil

Input LOW Level

Guaranteed Logic Low Level (4)

0.8

V

hH

Input HIGH Current

Vee = Max., VIN = Vee

0.1

5

j.LA

III

Input LOW Current

Vee = Max., VIN = GND

-0.1

-5

j.LA

VOH

Output HIGH Voltage

-

-

-

V

-

-

0.3

0.5

Symbol

Val

Test Conditions

Parameter

Output LOW Voltage

(1)

Vee = Min.

IOH = -300j.LA

VIN = VIH or Vil

IOH = -6mA MIL.

2.4

4.3

IOH = -8mA COM'L.

2.4

4.3

Vee = Min.

IOl = 300j.LA

VIN = VIH or Vil

IOl = SmA MIL.

(5)

(5)

IOl = 10mA COM'L.
loz

Off State (High Impedance)

Vee = Max.

Vo=OV

Output Current
los

Output Short Circuit Current

Va = Vee (Max.)
Vee = Max., VOUT = OV

(3)

-15

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading, not production tested.
3. Not more than one output should be shorted at one time. Duration of the circuit test should not exceed one second.
4. These input levels should only be static tested in a noise-free environment.
5. Guaranteed by design, not production tested.

5.3

0.3

0.5

-0.1

-10

0.1

10

-30

-

V

j.LA

rnA
252411>110

9

•

IDT49C402lAlB
16·BIT CMOS MICROPROCESSOR SUCE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS (IDT49C402 STANDARD POWER) VERSION (Cont'd)
TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc = 5.0V ± 10%

Commercial:
VLC

= 0.2V; VHC = VCC -

Symbol
ICCQH

0.2V

Test Condltlons(1)

Parameter
Quiescent Power Supply Current

Vcc = Max.

MIl.

CP = H (CMOS Inputs)

VHC ~ VIH, Vil ~ VlC

COM'l.

Min.

Typ.(2)

Max.

Unit

-

150

265

rnA

150

215

-

80

135

80

110

fcp = 0, CP = H
ICCQl

Quiescent Power Supply Current

VCC = Max.

CP = L (CMOS Inputs)

VHC

~

VIH, Vil

MIl.
~

VlC

COM'L.

rnA

fcp = 0, CP = L
ICCT

Quiescent Input Power Supply(6)

0.3

0.5

mAl

0.3

0.5

Input

MIl.

-

2.0

3.0

mAl

COM'l.

-

2.0

2.5

MHz

VCC = Max., fcp = 10MHz

MIl.

255

rnA

COM'l.

-

135

Outputs Open, OE = L

135

190

-

145

265

145

200

Vcc = Max., VIH

= 3.4V, fcp = 0

Current (per Input @ TTL High)
ICCD

Dynamic Power Supply Current

MIl.
COM'l.

VCC = Max.
VHC ~ VIH, Vil

~

VlC

Outputs Open, OE = L
Icc

Total Power Supply Current(7)

CP = 50 % Duty cycle
VHC

~

VIH, VIL ~ VLC

Vcc = Max., fcp = 10MHz

MIl.

Outputs Open, OE = L

COM'L.

CP = 50 % Duty cycle
VIH =3.4V, Vll= 0.4V
NOTES:
252411>111
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vec = 5.0V, +25°C ambient and maximum loading, not production tested.
3. Not more than one output should be shorted at one time. Duration of the circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.
5. Guaranteed by design, not production tested.
6. leer is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out leeoH, then dividing by the total number of inputs.
7. Total Supply Current is the sum of the Quiescent current and the Dynamic current (at either CMOS or TIL input levels). For all conditions; the Total Supply
Current can be calculated by using the following equation:
Icc =IccoH (CDH) +ICCOL (1 - CDH) + Iccr (Nr x DH) + ICCD (fcp)
CDH = Clock duty cycle high period
DH = Data duty cycle TIL high period (VIN = 3.4V)
Nr,,; Number of dynamic inputs driven at TIL levels
fep := Clock input frequency

5.3

10

IDT49C402lAl8
16-81T CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS (IDT49C402 LOW POWER) VERSION (Cont'd)
= 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc = 5.0V ± 10%

Commercial: TA = O°C to +70°C, VCC
VLC = 0.2V; VHC = VCC - O.2V
Symbol
leeQH

Test Condltlons(1)

Parameter
Quiescent Power Supply Current

Vee = Max.

CP = H (CMOS Inputs)

VHC

~

VIH, Vil

MIL.
~

VlC

COM'L.

VlC

COM'L.

Min.

TypJ2)

Max.

Unit

-

-

10

rnA

-

10

-

-

10

-

10

-

-

1.2

mAl

0.85

Input

fcp = 0, CP = H
leeQl

Quiescent Power Supply Current

VCC = Max.

CP = L (CMOS Inputs)

VHC

~

VIH, Vil

MIL.
~

rnA

fcp = 0, CP = L
ICCT

Quiescent Input Power Supply(6)

Vcc = Max., VIH = 3AV, fep = 0

lecD

Dynamic Power Supply Current

MIL.
COM'L.

Current (per Input @ TTL High)

MIL.

Vcc = Max.
VHC

~

VIH, Vil

~

VlC

COM'L.

-

7.5

mAl

-

4.5

MHz

-

-

85

rnA

55

-

-

Outputs Open, OE = L
Icc

Total Power Supply Current(7)

Vce = Max .. , fcp = 10MHz

MIL.

Outputs Open, OE = L

COM'L.

CP = 50 % Duty cycle
VHC

~

VIH, Vil

~

VlC

Vcc = Max .. , fcp = 10MHz

MIL.

Outputs Open, OE = L

COM'L.

130
95

CP = 50 % Duty cycle
VIH = 3AV, Vil = OAV
NOTES:

1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics.

2.
3.
4.
5.
6.

Typical values are at VCC = 5.0V, +25°C ambient and maximum loading, not production tested.
Not more than one output should be shorted at one time. Duration of the circuit test should not exceed one second.
These input levels provide zero noise immunity and should only be static tested in a noise-free environment.
Guaranteed by design, not production tested.
ICCT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out ICCOH, then dividing by the total number of inputs.
7. Total Supply Current is the sum of the Quiescent current and the Dynamiccurrent (at either CMOS orTTL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = IccoH (CDH) +ICCOL (1 - CDH) + ICCT (NT X DH) + ICCD (fcp)
CDH = Clock duty cycle high period
DH = Data duty cycle TTL high period (VIN = 3.4V)
NT = Number of dynamic inputs driven at TTL levels
fcp = Clock input frequency

CMOS TESTING CONSIDERATIONS
Special test board considerations must be taken into account when applying high-speed CMOS products to the
automatic testing environment. Large output currents are
being switched in very short periods and proper testing
demands that test set-ups have minimized inductance and
guaranteed zero voltage grounds. The techniques listed
below will assist the user in obtaining accurate testing results:
1) All input pins should be connected to a voltage potential
during testing. If left floating, the device may oscillate,
causing improper device operation and possible latchup.
2) Placement and value of decoupling capacitors is critical.
Each physical set-up has different electrical characteristics and it is recommended that various decoupling
capacitor sizes be experimented with. Capacitors should
be positioned using the minimum lead lengths. They
should also be distributed to decouple power supply lines
and be placed as close as possible to the DUT power pins.
5.3

3)

Device grounding is extremely critical for proper device
testing. The use of multi-layer performance boards with
radial decoupling between power and ground planes is
necessary. The ground plane must be sustained from the
performance board to the DUT interface board and wiring
unused interconnect pins to the ground plane is recommended. Heavy gauge stranded wire should be used for
power wiring, with twisted pairs being recommended for
minimized inductance.
4) To guarantee data sheet compliance, the input thresholds
should be tested per input pin in a static environment. To
allowfortesting and hardware-induced noise, IDT recommends using VIL ~ OV and VIH ~ 3V for AC tests.

11

IDT49C402lAlB
16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
IDT49C402 STANDARD AND LOW POWER
VERSION
(Military and Commercial Temperature Ranges)
The tables below specify the guaranteed performance of
the IDT49C402 over the -55°C to + 125°C and O°C to + 70°C
temperature ranges. Vee is specified at 5V ± 10% for military
temperature range and 5V ± 5% for commercial temperature
range. All times are in nanoseconds and are measured at the
1.5V signal level. The inputs switch between OV and 3V with
signal transition rates of 1V per nanosecond. All outputs have
maximum DC current loads.

CYCLE TIME AND CLOCK
CHARACTERISTICS
MiL (6)

Com'l.

Unit

Read-Modify-Write Cycle (from
selection of A, B registers to end
of cycle)

50

48

ns

Maximum Clock Frequency to
shift Q (50% duty cycle,
I = C32 or E32)

20

21

MHz

Minimum Clock LOW Time

30

30

ns

Minimum Clock HIGH Time

20

20

ns

Minimum Clock Period

50

48

ns
2524 tbl13

MAXIMUM COMBINATIONAL PROPAGATION DELAYS(1) CL = 50pF
To Output
(MSS= L)

G,P

Y

From Input

RAMo

00

RAM15

015

(MSS = H)
F15

Cn +16

OVR

F=O

MIL Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Unit

A. B Address
D

52

47

47

42

35

32

34

31

35

32

34

31

27

25

Cn

29

26

-

-

29

26

27

25

20

10,1,2

41

37

30

27

41

37

38

35

52

47

47

42

47

44

40

35

32

28

26

18

29

26

23

21

29

26

41

37

30

27

38

34

52

-

-

ns

-

ns
ns
ns

13,4,5

40

36

28

26

40

36

37

34

27

25

40

36

28

26

-

-

16,7,8,9

26

24

-

-

-

-

-

20

18

20

18

27

-

-

-

-

-

-

-

-

30

-

-

A Bypass
ALU (I = AXX,
1XX,3XX)

-

-

-

-

-

-

37

42

38

41

37

42

38

41

37

25

23

Clock

;-

42

38

41

30

27

ns
ns

ns
ns
2524 tbl14

5.3

12

lOT49C4021 AlB
16-BIT CMOS MICROPROCESSOR SUCE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

MINIMUM SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)

~

CP:
Set-up Time
Before H ~ L
Input
A. B Source Address
B Destination Address

0

/
Hold Time
After H ~ L

Set-up Time
Before L ~ H

Hold Time
After L ~ H

Mil.

Com'l.

Mil.

Com'l.

Mil.

Com'l.

Mil.

Com'l.

Unit

20
20

18
18
-

2 (3)

1 (3)

50

50

2

ns

0

1
1
1
0
0
0

0

0

ns

0

0

ns

_(1)

en

-

-

10.1,2

-

13,4,5

-

16,7,8,9

12

11

RAMo,15. 00,15

-

-

2

Do not change (2)

-

-

30/40 (5)

26136 (5)

2

35
45
45

32
41
41

0

Do not change (2)

-

-

12

11

0

ns
ns
ns
ns
ns

25241b115
NOTES:
1. A dash indicates a propagation delay or set-up time constraint does not exist.
2. Certain signals must be stable during the entire clock LOW time to avoid erroneous operation.
3. Source addresses must be stable prior to the H -+ L transition to allow time to access the source data before the latches close. The A address may then
be changed. The B address could be changed if it is not a destination: i.e., if data is not being written back into the RAM. Normally A and B are not changed
during the clock LOW time.
4. The set-up time prior to the clock L -+ H transition is to allow time for data to be accessed, passed through the ALU and returned to the RAM. It includes
all the time from stable A and B addresses to the clock L -+ H transition, regardless of when the H -+ L transition occurs.
5. First value is direct path (OATAIN -+ RAM/Q Register). Second value is indirect path (OATAIN -+ ALU -+ RAM/Q Register).
6. Guaranteed by design, not production tested.

II

5.3

13

IDT49C402lAlB
16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
IDT49C402A STANDARD AND LOW POWER
VERSION

CYCLE TIME AND CLOCK
CHARACTERISTICS

(Military and Commercial Temperature Ranges)
The tables below specify the guaranteed performance of
the IDT49C402A over the -SsoC to +12SoC and O°C to +70°C
temperature ranges. Vee is specified at SV ± 10% for military
temperature range and SV ± S% for commercial temperature
range. All times are in nanoseconds and are measured at the
1.SV signal level. The inputs switch between OV and 3V with
signal transition rates of 1V per nanosecond. All outputs have
maximum DC current loads.

MII.!6)

Com'l.

Unit

Read-Modify-Write Cycle (from
selection of A, B registers to end
of cycle~6)

23

22

ns

Maximum Clock Frequency to
shift Q (50% du~ cycle,
I = C32 or E32~ )

35

41

MHz

Minimum Clock LOW Time

13

11

ns

Minimum Clock HIGH Time

13

11

ns

Minimum Clock Period 6 )

36

31

ns
25241b116

MAXIMUM COMBINATIONAL PROPAGATION DELAYS(1)

CL= SOpF

To Output
(MSS = L)

RAMo

00

RAM15

015

(MSS = H)

G,P

Y

From Input

F15

OVR

Cn + 16

F=O

MIL Com'!. Mil. Com'l. Mil. Com'l. MIL Com'l. Mil. Com'l. MIL Com'l. Mil. Com'l. Mil. Com'l. Unit

-

ns

-

ns

-

ns

-

ns

26

-

-

ns

20

18

20

18

ns

-

-

-

-

-

31

34

31

A, B Address

41

37

39

35

41

37

41

37

37

34

41

37

40

36

0

32

29

29

26

29

26

31

28

27

25

32

29

28

26

Cn

28

25

-

-

26

24

25

23

20

18

29

26

23

21

10,1,2

35

32

30

27

35

32

34

31

29

26

35

32

30

27

13,4,5

35

32

28

26

34

31

34

31

27

25

35

32

28

16,7,8,9

25

23

-

-

-

-

-

-

-

-

27

-

-

30

-

-

A Bypass
ALU (I = AXX,
1XX,3XX)

-

33

30

34

31

27

34

Clock

./

34

31

31

28

-

30

-

ns
25

23

ns
25241b117

5.3

14

IDT49C402lAlB
16-BIT CMOS MICROPROCESSOR SUCE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

MINIMUM SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)
CP:
Set-up Time
Before H -+ L
Input

"

/
Hold Time
After H -+ L

Mil.

Com'l.

Mil.

11
11

10
10

2 (3)

0

_(1)

Cn
10,1,2

-

-

-

-

13,4,5

-

-

-

i6,7,8,9

11

10

RAMo,15,Oo,15

-

-

A, B Source Address
B Destination Address

Com'l.
1 (3)

Set-up Time
Before L -+ H
Mil.

Com'l.

MIl.

Com'l.

Unit

25

21

2
2
2

1
1
1'

ns

a
a
a
a
a

0
0
0
0
0

ns

Do not change (2)

-

12122 (5)

10120 (5)

17
28
28

15
25
25

Do not change (2)

-

-

Hold Time
After L -+ H

12

11

ns
ns
ns
ns
ns
ns

NOTES:
252411>118
1. A dash indicates a propagation delay or set-up time constraint does not exist.
2. Certain signals must be stable during the entire clock LOW time to avoid erroneous operation.
3. Source addresses must be stable prior to the H -+ L transition to allow time to access the source data before the latches close. The A address may then
be changed. The B address could be changed if it is not a destination: i.e., if data is not being written back into the RAM. Normally A and B are not changed
during the clock LOW time.
4. The set-up time prior to the clock L -+ H transition is to allow time for data to be accessed, passed through the ALU and returned to the RAM. It includes
all the time from stable A and B addresses to the clock L -+ H transition, regardless of when the H -+ L transition occurs.
5. First value is direct path (DATAIN -+ RAM/Q Register). Second value is indirect path (DATAIN -+ ALU -+ RAM/Q Register).
6. Guaranteed by design, not production tested.

II

5.3

15

IDT49C402lAlB
16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
IDT49C402B LOW POWER VERSION

CYCLE TIME AND CLOCK
CHARACTERISTICS

(Military and Commercial Temperature Ranges)
The tables below specify the guaranteed performance of
the IDT49C402B overthe -SsoC to +12SoC and O°C to +70°C
temperature ranges. Vee is specified at SV ± 10% for military
temperature range and SV ± S% for commercial temperature
range. All times are in nanoseconds and are measured at the
1.SV signal level. The inputs switch between OV and 3V with
signal transition rates of 1V per nanosecond. All outputs have
maximum DC current loads.

MiI,(6)

Com'l.

Unit

Read-Modify-Write Cycle (from
selection of A, B registers to end
of cycleY6)

22

19

ns

Maximum Clock Frequency to
shift Q (50% du~ cycle,
I = C32 or E32Y )

52

60

MHz

Minimum Clock LOW Time

11

9

ns

Minimum Clock HIGH Time
Minimum Clock Period 6)

11

9

ns

24

20

ns
25241b119

MAXIMUM COMBINATIONAL PROPAGATION DELAYS(1) CL = SOpF
To Output
(MSS = L)
G, ]5

Y

From Input

RAMo

Co

RAM15

Q15

(MSS = H)
OVR

F15

Cn+16

F=O

Mil. Com'l. MIL Com'l. Mil. Com'l. MIL Com'l. MIl. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Unit
A. B Address

33

28

31

26

31

28

31

28

28

26

31

28

32

29

-

26

23

23

21

23

21

25

22

22

20

26

23

24

23

-

-

ns

D
Cn

22

20

-

-

20

18

19

17

15

14

22

20

18

17

ns

28

26

24

22

28

26

27

25

23

21

28

26

26

24

13.4.5

28

26

22

21

27

25

27

25

22

20

28

26

25

23

-

-

10,1.2

-

ns

16,7.8.9

20

18

-

-

-

-

-

14

16

14

ns

-

-

16

22

-

-

24

-

-

A Bypass
ALU (I = AXX.
1XX,3XX)

-

-

-

-

25

22

26

24

27

25

-

-

25

27

25

-

-

Clock

./

27

25

-

27

ns
ns

ns
ns
25241b120

5.3

16

IDT49C402lAlB
16-BIT CMOS MICROPROCESSOR SUCE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

MINIMUM SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)
CP:
Set-up Time
Before H ~ L
Input

"

Mil.

Com'l.

A, B Source Address

10

9

B Destination Address

9

D

10
_(1)

Cn

-

10,1,2
13,4,5

-

16,7,8,9

10

9

RAMo,15,Oo,15

-

-

/
Set-up Time
Before L ~ H

Hold Time
After H ~ L

Mil.
2(3)

Com'l.
1(3)

Hold Time
After L ~ H

Mil.

Com'l.

Mil.

Com'!.

20

18

2

1

ns

2

1

ns

Do not change(2)

-

Unit

-

12122(5)

10120(5)

2

1

ns

-

16

14

0

0

ns

-

-

26

24

0

0

ns

-

-

-

26

24

0

0

ns

0

0

ns

0

0

ns

Do not change(2)

-

-

12

10

25241b121

NOTES:
1. A dash indicates a propagation delay or set-up time constraint does not exist.
2. Certain signals must be stable during the entire clock LOW time to avoid erroneous operation.
3. Source addresses must be stable prior to the H -+ L transition to allow time to access the source data before the latches close. The A address may then
be changed. The B address could be changed if it is not a destination: i.e., if data is not being written back into the RAM. Normally A and B are not changed
during the clock LOW time.
4. The set-up time prior to the clock L -+ H transition is to allow time for data to be accessed, passed through the ALU and returned to the RAM. It includes
all the time from stable A and B addresses to the clock L -+ H transition, regardless of when the H -+ L transition occurs.
5. First value is direct path (OATAIN -+ RAM/Q Register). Second value is indirect path (OATAIN -+ ALU -+ RAM/Q Register).
6. Guaranteed by design, not production tested.

IDT49C402B
MAX. OUTPUT ENABLE/DISABLE TIMES

IDT49C402A
MAX. OUTPUT ENABLE/DISABLE TIMES

(CL = 5pF, measured to O.5V change of VOUT in nanoseconds)
Tested at CL = 50pF, correlated to 5pF

(CL =5pF, measu red to 0.5V change of VOUT in nanoseconds)
Tested at CL = 50pF, correlated to 5pF

Enable
Input

Output

Mil.

OE

y

18

I

Disable

Com'l.

Mil.

16

15

I

I

Enable

Com'l.

Input

13

OE

I

Output

'y

Mil.
22

I

I

Disable

Com'l.

Mil.

20

20

I

I

25241b122

IDT49C402
MAX. OUTPUT ENABLE/DISABLE TIMES

Input

Output

Mil.

OE

y

25

I
I

Disable

Com'l.

Mil.

23

25

I
I

18
25241b123

AC TEST CONDITIONS

(CL = 5pF, measured to O.5V change of VOUT in nanoseconds)
Tested at CL = 50pF, correlated to 5pF
Enable

Com'l.

Com'l.

Input Pulse Levels
Input RiselFali Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GNDto 3.0V

WIns
1.5V
1.5V
See Figure 1
25241b125

23
25241b124

5.3

17

I

IDT49C402lAlB
16·BIT CMOS MICROPROCESSOR SUCE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

CRITICAL SPEED PATH ANALYSIS
Critical speed paths are for the I DT49C402B versus the
equivalent bipolar circuit implementation using four 2901 Cs
and one 2902A is shown below.
The IDT49C402B operates faster than the theoretically
achievable values of the discrete bipolar implementation.
Actual speed values for the discrete bipolar circuit will
increase due to on-chip/off-chip circuit board delays.

TIMING COMPARISION: IDT49C4028 vs 2901 C w/2902A
Data Path
(Com'I.)

1S-Blt
IlP System

Data Path
(MIl.)
~F=O

AB ADDR -+ F = 0

AB AD DR -+ RAMo, 15

~71

~71

~83.5

IDT49C4028

28

23

Speed Savings

43

48

Four 2901Cs + 2902A

AB ADDR

AB AD DR -+ RAMo, 15
~

Unit

83.5

ns

31

25

ns

52

55

ns
25241b126

TIMING COMPARISION: IDT49C402A vs 2901 C w/2902A
Data Path
(Com'I.)

1S-Blt
IlP System
Four 2901 Cs + 2902A

AB AD DR -+ F = 0
~

Data Path
(Mil.)

AB ADDR -+ RAMo, 15

71

AB AD DR -+ F = 0

~71

~

AB ADDR -+ RAMo, 15
~

83.5

Unit

83.5

ns

IDT49C402A

37

36

41

25

ns

Speed Savings

34

35

42.5

43.5

ns
25241b127

TIMING COMPARISION: IDT49C402 vs 2901 C w/2902A
Data Path
(Com'I.)

1S-Blt
IlP System
Four 2901 Cs + 2902A

Data Path
(Mil.)

AB AD DR -+ F = 0

AB AD DR -+ RAMo, 15

AB AD DR -+ F = 0

AB ADDR -+ RAMo, 15

Unit

~71

~71

83.5

ns

IDT49C402A

47

40

52

44

ns

Speed Savings

24

31

31.5

39.5

ns

~

83.5

~

25241b128

5.3

18

IDT49C402lAlB
16-BIT CMOS MICROPROCESSOR SUCE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUIT LOAD

2524 drw05

DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance
RL = Termination resistance: should be equal to ZOUT of the Pulse Generator
Figure 1. Switching Test Circuit (All Outputs)

INPUT/OUTPUT INTERFACE CIRCUIT

Vee

ESD
PROTECTION

II

IiH~
INPUTSU-~.....J'

OUTPUTS

2524 drw 06
2524 drw 07

Figure 2. Input Structure (All Inputs)

Figure 3. Outputs Structure (All Outputs Except F

= 0)

OUTPUTS

2524 drw08

Figure 4. Outputs Structure (F

5.3

=0)

19

IDT49C402lAlB
16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

XXXX
Device Type

X

xx

Power

Speed

X
Package

X
Process!
Temperature
Range

y

Blank

B
J

Commercial (O°C to + 70°C)
Military (- 55°C to + 125°C)
Compliant to MIL-STD-883, Class B

G
F

Plastic Leaded Chip Carrier
Pin Grid Array
Ceramic Flatpack (25mil centers)

Blank
A
B

Standard Speed
High-Speed
Very High-Speed (Low Power Version Only)

L
Blank

Low Power Version
Standard Power Version

49C402 16-Bit Microprocessor Slice
2524 drw 09

5.3

20

(;)
Integrated Device Technology, Inc.

IDT49C410
IDT49C410A

16-81T CMOS
MICROPROGRAM
SEQUENCER

FEATURES:

DESCRIPTION:

• 16-bit wide address path
- Address up to 65,536 words of microprogram memory
• 16-bit loop counter
- Pre-settable down-counter for counting loop iterations
and repeating instructions
• Low-power CEMOSTt.A
- Icc (max.)
Military: 90mA
Commercial: 75 rnA
• Fast
- IDT49C410 meets 2910A speeds
- IDT49C410A is a 30% speed upgrade
• 33-deep stack
- Accommodates highly nested microcode
• 16 powerful microinstructions
• Available in 48-pin, 600 mil plastic and sidebraze DIP"
52-pin PLCC and 48-pin Flatpack
• Three enables control branch address sources
• Four address sources
• 2910A instruction compatibility
• Military product available compliant to MIL-STD-883,
Class B
• Standard Military Drawing #5962-88643 is listed for this
function

The IDT49C410s are architecture and function code
compatible to the 2910A with an expanded 16-bit address
path, thus allowing for programs upto 65,536words in length.
They are microprogram address sequencers intended for
controlling the sequence of execution of microinstructions
stored in the microprogram memory. Besides the capability of
sequential access, they provide conditional branching to any
microinstruction within their 65,536 microword range.
The 33-deep stack provides microsubroutine return linkage and looping capability. The deep stack can be used for
highly nested microcode applications. Microinstruction loop
count control is provided with a count capability of 65,536.
During each microinstruction, the microprogram controller
provides a 16-bit address from one of four sources: 1) the
microprogram address register (IlPC), which usually contains
an address one greater than the previous address; 2) an
external (direct) input (D); 3) a register/counter (R) retaining
data loaded during a previous microinstruction; or4) a last-in!
first-out stack (F).
The IDT49C10s are fabricated using CEMOS, a CMOS
technology designed for high-performance and highreliability.
The IDT49C410s are pin-compatible, perlormanceenhanced, easily upgradable versions of the 291 OA.
The IDT49C41Os are available in 48-pin DIP (600 milx 100
mil centers), 52-pin PLCC and 48-pin flatpack.
01

FUNCTIONAL BLOCK DIAGRAM

DECREMENTI
HOLD/LOAD

II

16

VI

CEMOS and MICROSLICE are trademarks of Integrated Device Techology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
el990 Integrated Device Technology, Inc.

5.4

2551 dlw02

APRIL 1990
DSC-901412

1

II

IDT49C410/A
16·BIT CMOS MICROPROGRAM SEQUENCER

MllITARV AND COMMERCIAL TEMPERATURE RANGES

PIN 'CONFIGURATIONS
Y13
013
Y4 .

012
V12
03
V3
02
V2
01
VI
Do
Vo

04
Ys
Os

~
f3[

MAI5
13
12

Pin 1 Identifier

~

11
10

J5[

13
12

Vcc
11
10

~

Vll
011
V10
010
Ve
De
VB
DB
'VIS

mrc

Os
Ys
07
Y7
014
V14

2
3
4
5
6
7
8
9
10
11
12

~

OJ;

cctfJ
CC
mIT

484746454443424140393837

vrer

CI
CP
GND

Vec

A

CC
~

rna:

36
35
34
33
32
31
30
29
28
27
26
25

F48-1

,

01
V1

Do
Yo

CI
CP
GNO
OE
Vl1

011

VlO
010

13 14 15 1617 18 19 2021 22 23 24

015
2551 drw 01

2551 drw04

DIP
TOP VIEW

FLATPACK
TOP VIEW

IDT49C410 PIN DESCRIPTIONS
Pin Name

VECf
PC
w;J5
13
12

Vee
11
10

CCEN
CC
RLO
FOIT
NC

8
9
10
11
12
13
14
15
16
17
18
19
20

46
45
44
43
42
41
40
39
38
37
36
35
34

J52-1

NC
01

I/O

01

I

II

I

Selects one-of-sixteen instructions.

CC

I

Used as test criterion. Past test is a LOW on
CC.

CCEN

I

Whenever the signal is HIGH, CC is ignored
and the part operates as though CC were
true (LOW).

CI

I

Low order carry input to incrementer for
microprogram counter.

RLO

I

When LOW forces loading of register/
counter regardless of instruction or
condition.

V1
Do
Vo

CI
CP
GNO
OE
V11
' 011
V10

OE

I

Three-state control of Yi outputs.

010

CP

I

Triggers all internal state changes at LOWto-HIGH edge.

YI

0

Address to microprogram memory. Yo is
LSB, Y15 is MSB.

FULL

0

Indicates that 33 items are on the stack.

PL

0

Can select #1 source (usually Pipeline
Register) as direct input source.

MAP

0

Can select #2 source (usually Mapping
PROM or PLA) as direct input source.

VECT

0

Can select #3 source (for example, Interrupt
Starting Address) as direct input source.

21 22 2324 2526 2728 2930 31 32 33

8~c>= ~;.;g;:o~

Description
Direct input to register/counter and multiplexer Do is LSB.

o~ g
2551 drw03

PLCC
TOP VIEW

25511b101

5.4

2

IDT49C410/A
16-81T CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PRODUCT DESCRIPTION
The IDT49C41Os are high-performance CMOS microprogram sequencers that are intended for use in very high-speed
microprogrammable microprocessor applications. The
sequencers allow for direct control of up to 64K words of
microprogram.
The heart of the microprogram sequencers is a 4-input
multiplexer that is used to select one of four address sources
to select the next microprogram address. These address
sources include the register/counter, the direct input, the
microprogram counter or the stack as the source for the
address of the next microinstruction.
The register/counter consists of sixteen D-type flip-flops
which can contain either an address or a count. These edgetriggered flip-flops are under the control of a common clock
enable, as well as the four microinstruction control inputs.
When the load control (RDL) is LOW, the data at the D inputs
is loaded into this register on the LOW-to-HIGH transition of
the clock. The output of the register/counter is available at the
multiplexer as a possible next address source for the
microcode. Also, the terminal count output associated with
the register/counter is available at the internal instruction PLA
to be used as condition code input for some of the
microinstructions. The I DT49C41 Os contain a microprogram
counter that usually contains the address of the next microinstruction compared to that currently being executed. The
microprogram counter actually consists of a 16-bit incrementer followed by a 16-bit register. The microprogram counter
will increment the address coming out of the sequencer going
to the microprogram memory if the carry-in input to this
counter is HIGH; otherwise, this address will be loaded into the
microprogram counter. Normally, this carry-in input is set to
the logic HIGH state so that the incrementer will be active.
Should the carry-in input be set LOW, the same address is
loaded into the microprogram counter. This is a technique that
can be used to allow execution of the same microinstruction
several times.
There are sixteen D-inputs on the IDT49C41Os that go
directly to the address multiplexer. These inputs are used to
provide a branch address that can come directly from the
microcode or some other external source. The fourth input
available to the multiplexer for next address control is the 33deep, 16-bitwide LIFO stack. The LIFO stack provides return
address linkage for subroutines and loops. The IDT49C41 Os
contain a built-in stack pointer that always points to the last
stack location written. This allows for stack reference operations, usually called loops, to be performed without popping
the stack.
The stack pointer internal to the IDT49C41 Os is actually an
up/down counter. During the execution of microinstructions
one, four and five, the PUSH operation may occur depending
on the state of the condition code input. This causes the stack
pointer to be incremented by one and the stack to be written

5.4

with the required return linkage (the value contained in the
microprogram counter). On the microprogram cycle following
the PUSH, this new return linkage data that was in the
microprogram counter is now at the new location pointed to by
the stack pOinter. Thus, any time the multiplexer looks at the
stack, it will see this data on the top of the stack.
During five different microinstructions, a pop operation
associated with the stack may occur. If the pop occurs, the
stack pointer is decremented at the next LOW-to-HIGH
transition of the clock. A pop decrements the stack pointer
which is the equivalent of removing the old information from
the top of the stack.
The IDT49C41 Os are designed so that the stack pointer
linkage allows any sequence of pushes, pops or stack
references to be used. The depth of the stack can grow to a
full 33 locations. After a depth of 33 is reached, the FULL
output goes LOW. If further PUSHes are attempted when the
stack is full, the stack information at the top of the stack will be
destroyed but the stack pOinter will not end around. It is
necessary to initialize the stack pointer when power is first
turned on. This is performed by executing a RESET instruction (Instruction 0). This sets the stack pointer to the stack
empty position - the equivalent depth of zero. Similarly, a
pop from an empty stack may place unknown data on the Y
outputs, but the stack pointer is designed not to end around.
Thus, the stack pointer will remain at the 0 or stack empty
location if a pop is executed while the stack is already empty. •
The IDT49C410's internal 16-bit register/counter is used
during microinstructions eight, nine and fifteen. During these
instructions, the 16-bit counter acts as a down cou nter and the
terminal count (count = 0) is used by the internal instruction
PLA as an input to control the microinstruction branch test
capability. The design of the internal counter is such that, if it
is preloaded with a number N and then this counter is used in
a microprogram loop, the actual sequence in the loop will be
executed N + 1 times. Thus, it is possible to load the counter
with a count of 0 and this will result in the microcode being
executed one time. The 3-way branch microinstruction,
instruction 15, uses both the loop counter and the external
condition code input to control the final source address from
the Y outputs of the microprogram sequencer. This 3-way
branch may result in the next address coming from the D
inputs, the stack or the microprogram counter.
The I DT49C41 Os provide a 16-bit address at the Y outputs
that are under control of the OE input. Thus, the outputs can
be put in the three-state mode, allowing the writable control
store to be loaded or certain types of external diagnostics to
be executed.
In summary, the IDT49C410s are the most powerful
microprogram sequencers currently available. They provide
the deepest stack, the highest performance and lowest power
dissipation for today's microprogrammed machine design.

3

IDT49C410/A
16-BIT CMOS MICROPROGRAM SEQUENCER

o Jump Zero (JZ)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

2 Jump Map (JMAP)

1 Cond JSB PL (CJS)

~!~86~

STACK
40
41
42
43
3 Cond Jump PL (CJP)

66
65t--67 •
68

4 Push/Cond LD CNTR (PUSH)

6 5 t < : 8 STACK
66

t

67 •
68

25

65
66

T 26

69

N

6 Cond Jump Vector (CJV)

68

7 Cond JUMP R/PL (JRP)

30
31

8 Repeat Loop, CNTR

* 0 (RFCT)

~ STACK
~ ~ (PUSH)
65
66

i0

---

N

34

20
21

35

T 36

69

32
33

67

t

REGISTERI
COUNTER

67
68

30
31

9 Repeat PL, CNTR

65

67

REGISTER!
COUNTER

65
66
66
65t--67 •

5 Cond JSB R/PL (JSRP)

* 0 (RPCT)

~

STACK
65
66

67 •
68

42
43
44

10 Cond Return (CRTN)

~COU~ER
(LOCT)

66

40
41

30
31
32

67
68
69
70

11 Cond Jump PL & POP (CJPP)

12 LD CNTR & Continue (LDCT)

35
36
37

65

l - + - - - - -. .
70

rCOU~ER

40
41

65
66 •

42

67
68

13 Test End Loop (LOOP)

65
66

71
14 Continue (CONT)

65t
66 •

67
68

15 Three-Way Branch (TWB)
65

67 (PUSH)
~STACK

66 _ _ _ ~ REGISTER/
67
COUNTER
68 •
72
69
73

Figure 1. IDT49C410 Flow Diagrams

5.4

~

STACK
(PUSH)

67
68
69

72

2551 drw05

4

IDT49C410/A
16-BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C410 OPERATION
The IDT49C41Os are CMOS pin-compatible implementations of the Am2910 and 291 OA microprogram sequencers.
The I DT49C410 sequencers are functionally identical except
that they are 16 bits wide and provide a 33-deep stack to give
the microprogrammer more capability in terms of microprogram subroutines and microprogram loops. The definition of
each microprogram instruction is shown in the table of
instructions. This table shows the results of each instruction
in terms of controlling the multiplexer, which determines the Y
outputs, and in controlling the signals that can be used to
enable various branch address sources (PL, MAP, VECT).
The operation of the register/counter and the 33-deep stack
after the next LOW-to-HIGH transition of the clock are also
shown. The internal multiplexer is used to select which of the
internal sources is used to drive the Y outputs. The actual
value loaded into the microprogram counter is either identical
to the Y output or the Y output value is incremented by 1 and
placed in the microprogram counter. This function is under the
control of the carry inputs. For each of the microinstruction
inputs, only one of the three outputs (PL, MAP or VECT) will
be LOW. Note that this function is not determined by any of
the possible condition code inputs. These outputs can be
used to control the three-state selection of one of the sources
for the microprogram branches.
Two inputs, CC and CCEN, can be used to control the
conditional instructions. These are fully defined in the table of
instructions. The RLD input can be used to load the internal
register/counter at any time. When this input is LOW, the data
at the D inputs will be loaded into this register/counter on the
LOW-to-HIGH transition of the clock. Thus, the RLD input
overrides the internal hold or decrement operations specified
by the various microinstructions. The OE input is normally
LOW and is used as the three-state enable for the Youtputs.
The internal stack in the IDT49C410s is a last-in/first-out
memory that is 16-bits in width and 33 words deep. It has a
stack pointerthat addresses the stack and always pOints to the
value currently on the top of the stack. When instruction 0
(RESET) is executed, the stack pOinter is initialized to the top
of the stack which is, by definition, the stack empty condition.
Thus, the contents of the top of the stack are undefined until
the forced PUSH occurs. A pop performed while the stack is
empty will not change the stack pOinter in any way; however,
it will result in unknown data at the Youtputs.
By definition, the stack is full any time 33 more PUSHes
than pops have occurred since the stack was last empty.
When this happens, the FULL Flag will go LOW. This signal
first goes LOW on the microcycle after the 33 pushes occur.
When this signal is LOW, no additional pushes should be
attempted orthe information on the top of the stack will be lost.

THE IDT49C410 INSTRUCTION SET
This data sheet contains a block diagram of the I DT49C410
microprogram sequencers. As can be seen, the devices are
controlled by a 4-bit microinstruction word (13 - 10). Normally,
this word is supplied from one 4-bit field of the microinstruction
word associated with the entire state machine system. These
four bits provide forthe selection of one of the sixteen powerful

5.4

instructions associated with selecting the address of the next
microinstructio n. Unused Y outputs can be left ope n; however,
the corresponding most significant D inputs should be tied to
ground for smaller microwords. This is necessary to make
sure the internal operation of the counter is proper should less
than 64K of microcode be implemented. As shown in the block
diagram, the internal instruction PLA uses the four instruction
inputs as well as the CC, CCEN and the internal counter = 0
line for controlling the sequencer. This internal instruction
PLA provides all of the necessary internal control signals to
control each particular part of the microprogram sequencer.
The next address at the Y outputs of the IDT49C41Os can be
from one offoursources. These include the internal microprogram counter, the last-in/first-out stack, the register/counter
and the direct inputs.
The following paragraphs will describe each instruction
associated with the IDT49C41 Os. As a part of the discussion,
an example of each instruction is shown in Figure 1. The
purpose of the examples is to show microprogram flow. Thus,
in each example the microinstruction currently being
executed has a circle around it. That is, this microinstruction
is assumed to be the contents of the pipeline register at the
output of the microprogram memory. In these drawings, each
of the dots refers to the time that the contents of the microprogram memory word would be in the pipeline register and is
currently being executed.

INSTRUCTION 0 JUMP 0 (JZ)
This Conditional Jump is used at power-up time or at any
restart sequence when the need is to reset the stack pOinter
and jump to the very first address in microprogram memory.
The Jump 0 instruction does not change the contents of the
register/counter.
INSTRUCTION 1 CONDITIONAL JUMP TO SUBROUTINE (CJS)
The Conditional Jump to Subroutine instruction is the one
used to call microprogram subroutines. The subroutine
address will be contained in the pipeline register and
presented at the D inputs. If the condition code test is passed,
a branch is taken to the subroutine. Referring to the flow
diagram for the I DT49C41 Os shown in Figure 1, we see that
the content of the microprogram counter is 68. This value is
pushed onto the stack and the top of stack pointer is
incremented. If the test is failed, this Conditional Jump to
Subroutine instruction behaves as a simple continue. That is,
the content of microinstruction address 68 is executed next.
INSTRUCTION 2 JUMP MAP (JMAP)
This sequencer instruction can be used to start different
microprogram routines based on the machine instruction
opcode. This is typically accomplished by using a mapping
PROM as an input to the D inputs on the microprogram
sequencer. The JMAP instruction branches to the address
appearing on the D inputs. Inthe flow diagram shown in Figure
1, we see that the branch actually will be the contents of
microinstruction 85 and this instruction will be executed next.
5

II

IDT49C410/A
16-81T CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C410 INSTRUCTION OPERATIONAL SUMMARY
13-10

Mnemonic

0
1

JZ
CJS

2
3

JMAP
CJP

4

PUSH

5

JSRP

6

CJV

7

JRP

8

RFCT

9

RPCT

10

CRTN

11

CJPP

12
13

LDCT
LOOP

14
15

CONT
TWB

CC

X

Counter
Test

PASS
FAIL
PASS
FAIL
PASS
FAIL
PASS
FAIL
PASS
FAIL

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X

=0
NOT= 0
=0
NOT=O

PASS
FAIL
PASS
FAIL

X

X
X
X
X
X
X
X
X

PASS
PASS
FAIL
FAIL

=0
NOT=O
=0
NOT=O

PASS
FAIL
X

X

PASS
FAIL

Stack

Address
Source

Register
Counter

Enable
Select

CLEAR
PUSH
NC
NC
NC
NC
PUSH
PUSH
PUSH
PUSH
NC
NC
NC
NC
POP
NC
NC
NC
POP
NC
POP
NC
NC
POP
NC
NC
POP
POP
POP
NC

0
D
PC
D
D
PC
PC
PC
D
R
D
PC
D
R
PC STACK
PC
D
STACK
PC
D
PC
PC
PC
STACK
PC
PC
PC
D
STACK

NC
NC
NC
NC
NC
NC
LOAD
NC
NC
NC
NC
NC
NC
NC
NC
DEC
NC
DEC
NC
NC
NC
NC
LOAD
NC
NC
NC
NC
DEC
NC
DEC

PL
PL
PL
MAP
PL
PL
PL
PL
PL
PL
VECT
VECT
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
2551 Tbl02

NC = No Charge; DEC = Decrement

INSTRUCTION 3 CONDITIONAL JUMP PIPELINE (CJP)
The simplest branching control available in the I DT49C410
microprogram sequencers is that of conditional jump to
address. In this instruction, the jump address is usually
contained in the microinstruction pipeline register and
presented to the D inputs. If the test is passed, the jump is
taken while, if the test fails, this instruction executes as a
simple continue. In the example shown in the flow diagram of
Figure 1, we see that if the test is passed, the next
microinstruction to be executed is the content of address 25.
If the test is failed, the microcode simply continues to the
contents of the next instruction.
INSTRUCTION 4 PUSH/CONDITIONAL LOAD COUNTER (PUSH)
With this instruction, the counter can be conditionally
loaded during the same instruction that pushes the current
value of the microprogram counteron to the stack. Under any
condition independent of the conditionaitesting, the microprogram counter is pushed on to the stack. If the conditional test
is passed, the counter will be loaded with the value on the D
inputs to the sequencer. If the test fails, the contents of the
counterwill not change. The PUSH/Conditional Load Counter
5.4

instruction is used in conjunction with the loop instruction
(Instruction 13), the repeat file based on. the counter
instruction (Instruction 9) or the 3-way branch instruction
(Instruction 15).
INSTRUCTION 5 CONDITIONAL JUMP TO SUBROUTINE R/PL (JSRP)
Subroutines may be called by a Condijional Jump Subroutine
from the internal register orfrom the external pipeline register.
In this instruction the contents of the microprogram counter
are pushed on the stack and the branch address for the
subroutine call will be taken from either the internal register/
counter or the external pipeline register presented to the D
inputs. If the conditional test is passed, the subroutine
address will be taken from the pipeline register. If the
conditional test fails, the branch address is taken' from the
internal register/counter. An example of this is shown in the
flow diagram of Figure 1.
INSTRUCTION 6 CONDITIONAL JUMP VECTOR (CJV)
The Conditional Jump Vector instruction is similar to the
Jump Map instruction in that it allows a branch operation to a
microinstruction as defined from some external source,

6

IDT49C410/A
16-81T CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

except that it is conditional. The Jump Map instruction is unconditional. If the conditional test is passed, the branch is
takentothe new address on the D inputs. If the conditional test
is failed, no branch is taken but rather the microcode simply
continues to the next sequential microinstruction. When this
instruction is executed, the VECT output is LOW unconditionally. Thus, an external 12-bit field can be enabled on to the D
inputs of the microprogram sequencer.

INSTRUCTION 7 CONDITIONAL JUMP R/PL (JRP)
The Conditional Jump register/counter or external pipeline
register always causes a branch in microcode. This jump will
be to one of two different locations in the microcode address
space. If the test is passed, the jump will be to the address
presented on the D inputs to the microprogram sequencer. If
the conditional test fails, the branch will be to the address
contained in the internal register/counter.
INSTRUCTION 8 REPEAT LOOP COUNTER NOT EQUAL TO 0 (RFCT)
This instruction utilizes the loop counter and the stack to
implement microprogrammed loops. The start address forthe
loop would be initialized by using the PUSH/Conditional Load
Counter instruction. Then, when the repeat loop instruction is
executed, if the counter is not equal to 0, the next microword
address will be taken from the stack. This will cause a loop to
be executed as shown in the Figure 1 flow diagram. Each time
the microcode sequence goes around the loop, the counter is
decremented. When the counter reaches 0, the stack will be
popped and the microinstruction address will be taken from
the microprogram counter. This instruction performs a timed
wait or allows a single sequence to be executed the desired
number of times. Remember, the actual number of loops
performed is equal to the value in the counter plus 1.
INSTRUCTION 9 REPEAT PIPELINE, COUNTER NOT EQUAL TO 0
(RPCT)
This instruction is another technique for implementing a
loop using the counter. Here, the branch address forthe loop
is contained in the pipeline register. This instruction does not
use the stack in any way as a part of its implementation. As
long as the counter is not equal to 0, the next microword
address will be taken from the D inputs of the microprogram
sequencer. When the counter reaches 0, the internal multiplexer will select the address source from the microprogram
counter, thus causing the microcode to continue on and leave
the loop.
INSTRUCTION 10CONDITIONAL RETURN (CRTN)
The Conditional Return instruction is used for terminating
subroutines. The fact that it is conditional allows the subroutine either to be ended or to continue. If the conditional test is
passed, the address of the next microinstruction will be taken
fromthe stack and it will be popped. Ifthe conditional test fails,
the next microinstruction address will come from the internal
microprogram counter. This is depicted in the flow diagram of
Figure 1. It is important to remember that every subroutine
call must somewhere be followed by a return from subroutine
5.4

call in order to have an equal number of pushes and pops on
the stack.

INSTRUCTION 11 CONDITIONAL JUMP PIPELINE AND POP (CJPP)
The Conditional Jump Pipeline and Pop instruction is a
technique for exiting a loop from within the middle of the loop.
This is depicted fully in the flow diagram for the IDT49C410s,
as shown in Figure 1. The conditional test input for this
instruction results in a branch being taken if the test is passed.
The address selected will be that on the D inputs to the
microprogram sequencer and, since the loop is being terminated, the stack will popped. Should the test be failed on the
conditional test inputs, the microprogram will simply continue
to the next address as taken from the microprogram counter.
The stack will not be affected if the conditional test input is
failed.
INSTRUCTION 12 LOAD COUNTER AND C9NTINUE (LDCn
The Load Counter and Continue instruction is used to place
a value on the D inputs in the register/counter and continue to
the next microinstruction.
-INSTRUCTION 13TEST END OF LOOP (LOOP)
The Test End of Loop instruction is used as a last instruction
in a loop associated with the stack. During this instruction, if
the conditional test input is failed, the loop branch address will
be that on the stack. Since we may go around the loop a
numberof times, the stack is not popped. If the conditional test
input is passed, then the loop is terminated and the stack is
popped. Notice that the loop instruction requires a PUSH to
be performed at the instruction immediately prior to the loop
return address. This is necessary so as to have the correct
address on the stack before the loop operation. It is for this
reason that the stack pointer always points to the last thing
written on the stack.
INSTRUCTION 14 CONTINUE (CONT)
The Continue instruction is a Simple instruction whereby
the address for the microinstruction is taken from the microprogram counter. This instruction simply causes sequential
program flow to the next microinstruction in microcode memory.
INSTRUCTION 15THREE WAY BRANCH (TWB)
The Three Way Branch instruction is used for looping while
waiting for a conditional event to come true. If the event does
not come true after some number of microinstructions, a
branch is taken to another microprogram sequence. This is
depicted in Figure 1 showing the IDT49C41 0 flow diagrams
and is also described in full detail in the IDT49C41 O's instruction operational summary. Operation of the instruction is such
that any time the external conditional test input is passed, the
next microinstruction will be that associated with the program
counter and the loop will be left. The stack is also popped.
Thus, the external test input overrides the other possibilities.
Should the external test input not be true, the rest of the
operation is controlled by the internal counter. If the counter
7

5

IDT49C410/A
16-81T CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

is not equal to 0, the loop is taken by selecting the address on
the top of the stack as the address out of the Y outputs of the
IDT49C410. In addition, the counter is decremented. Should
the external conditional test input be failed and the counter
also have counted to 0, this instruction ''times out". The result
is that the stack is popped and a branch is taken to the address
presented to the D inputs of the IDT49C410 microprogram
sequencer. This address is usually provided by the external
pipeline register.

Vee
VTERM

TA
TSIAS
TSTG
PT
lOUT

Rating

Com'l.

Power Supply
-0.5 to +7.0
Voltage
Terminal Voltage
-0.5 to
with Respect
Vee + 0.5
to Ground
Operating
o to +70
Temperature
Temperature
-55 to +125
Under Bias
Storage
-55 to +125
Temperature
Power Dissipation
1.0
DC Output Current
30

Throughout this discussion we have talked about microcode passing the conditional test. There are actually two inputs
associated with the conditional test input. These include the
CCEN and the CC inputs. The CCEN input is a condition code
enable. Whenever the CCEN input is HIGH, the CC input is
ignored and the device operates as though the CC input were
true (LOW). Thus, a fail of the external test condition can be
defined as CCEN equals LOW and CC equals HIGH. A pass
condition is defined as a CCEN equal to HIGH or a CC equal
to LOW. It is important to recognize the full function of the
condition code enable and the condition code inputs in order
to understand when the test is passed or failed.

CAPACITANCE (TA = +25°C, f = 1.0MHz)

ABSOLUTE MAXIMUM RATINGS(1)
Symbol

CONDITIONAL TEST

Mil.
-0.5 to +7.0

V

-0.5 to
Vee + 0.5

V

-55 to +125

DC

-65 to +135

DC

-65 to +150

DC

1.0

W
mA

30

Symbol
CIN
COUT

Unit

Parameter(1)
Input Capacitance
Output Capacitance

Conditions
VIN = OV
VOUT= OV

NOTE:
1. This parameter is sampled and not 100% tested.

Typ.

Unit
pF
pF

5

7

25511b104

NOTE:
25511b103
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

5.4

8

IDT49C410/A
16·81T CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS
Commercial: TA
VLC = 0.2V; VHC
Symbol

= O°C to + 70°C, Vcc = 5.0V ± 5%; Military:
= Vcc - 0.2V

TA

=-

55°C to + 125°C, Vcc

Test Conditions (1)

Parameter

= 5.0V ± 10%
Min.

Typ.

(2)

Max.

Unit

-

V

-

-

0.8

V

0.1

5

~A

-

-0.1

-5

~A

VHe

VHe

-

V

4.3

-

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

(4)

VIL

Input LOW Level

Guaranteed Logic LOW Level

(4)

IIH

Input HIGH Current

Vee = Max., VIN = Vee

IlL

Input LOW Current

Vee = Max., VIN = GND

VOH

Output HIGH Voltage

Vee = Min.

IOH = -300~A

VIN = VIH or VIL

IOH = -12 mA MIL

2.4

IOH = -15 mA COM'L.

2.4

4.3

-

Vee = Min.

IOL = 300~A

-

GND

VLe

VIN = VIH or VIL

IOL = 20 mA MIL

-

0.3

0.5

IOL = 24 mA COM'L

-

0.3

0.5

Vee = Max.

Vo= OV

-

-0.1

-10

Vo = Vee (Max.)

-

0.1

10

-30

-

-

VOL

loz

Output LOW Voltage

Off State (High Impedance)
Output Current

los

Output Short Circuit Current

Vee = Max .• Vour = OV (3)

2.0

NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vce = S.OV. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the circuit test should not exceed one second.
4. These input levels should only be static tested in a noise-free environment.

V

~A

mA
2551 tbl 05

II

5.4

9

IDT49C410/A
16·BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS (Cont'd.)
Commercial: TA = O°C to + 70°C, Vcc = 5.0V ± 5%; Military: TA = - 55°C to + 125°C, Vcc = 5.0V ± 10%
VLC = 0.2V; VHC = VCC - 0.2V
Symbol
I CCQH

Test Conditions (1)

Parameter
Quiescent Power Supply Current
CP

= H (CMOS Inputs)

Vcc

Quiescent Power Supply Current
CP

= L (CMOS Inputs)

= 0, CP = H
= Max.

VCC

Unit

-

50

rnA

-

35

50

rnA

-

0.3

0.5

VHC ::; VIH, VIL::; VLC
fcp

I CCT

Max.

(2)

VHC ~ VIH, VIL ~ VLC
fcp

I CCQL

Typ.
35

Min.

= Max.

Quiescent Input Power Supply

= 0, CP = L
= Max., VIH = 3.4V, fcp = a

Vcc

Current (per Input @ TIL High) (5)
I CCD

Dynamic Power Supply Current

mAl
Input

Vcc

= Max.

VHC ::; VIH, VIL::; VLC

=L
= Max., fcp = 10MHz
Outputs Open, OE = L
CP = 50 % Duty cycle

MIL

-

1.0

3.0

mAl

COM'L

-

1.0

1.5

MHz

rnA

Outputs Open, OE
Icc

Total Power Supply Current

(6)

VCC

MIL

-

45

80

COM'L

-

45

65

VHC ::; VIH, VIL::; VLC
Vcc

= Max., fcp = 10MHz

Outputs Open, OE = L
CP
VIH

MIL

-

50

90

COM'L

-

50

75

= 50 % Duty cycle
= 3.4V, VIL = O.4V

NOTES:
5. I CCOT is derived by

255111>106

measuring the total current with all the inputs tied together at 3.4V, subtracting out I CCOH, then dividing by the total number of inputs.
6. Total Supply Current is the sum of the Quiescentcurrent and the Dynamic current (at either CMOS or TIL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = I CCOH (CDH) + I CCOL (1

-

CDH) + I CCT (N Tx DH) + I CCD (I cp)

CDH = Clock duty cycle high period
DH = Data duty cycle TTL high period (V IN = 3.4V)
NT = Number of dynamic inputs driven at TTL levels
fcp = Clock Input frequency

CMOS TESTING CONSIDERATIONS
There are certain testing considerations which must be
taken into account when testing high·speed CMOS devices in
an automatic environment. These are:

3) Definition of input levels is very important. Since many
inputs may change coincidentally, significant noise at the
device pins may cause the VIL and VIH levels not to be met
until the noise has settled. To allow for this testing/board
induced noise, lOT recommends using VIL ~ OV and VIH ~
3V for AC tests.
4) Device grounding is extremely important for proper device
testing. The use of multi-layer performance boards with
radial decoupling between power and ground planes is
required. The ground plane must be sustained from the
performance board to the OUT interface board. All unused
interconnect pins must be properly connected to the ground
pin. Heavy gauge stranded wire should be used for power
wiring and twisted pairs are recommended to minimize
inductance.

1) Properdecoupling atthetest head is necessary. Placement
of the capacitor set and the value of capacitors used is
critical in reducing the potential erroneous failu res resulting
from large Vee current changes. Capacitor lead length
must be short and as close to the OUT power pins as
possible.
2) All input pins should be connected to a voltage potential
during testing. If left floating, the device may begin to
oscillate causing improper device operation and possible
latchup.

5.4

10

IDT49C410/A
16·BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C410A
AC ELECTRICAL CHARACTERISTICS
I. SET-UP AND HOLD TIMES
t
Inputs

t

(5)

IDT49C410
AC ELECTRICAL CHARACTERISTICS
I. SET-UP AND HOLD TIMES
t

(H)

Com'l.

Mil.

Com'l.

Mil.

Unit

6

7

0

0

ns

OI~R

t (H)

(5)

Com'l.

Mil.

Com'l.

Mil.

Unit

OI~R

16

16

0

0

ns

Inputs

OI~PC

13

15

0

0

ns

OI~PC

30

30

0

0

ns

10-3

23
15
15
6
11

25

0
0
0
0

ns

10-3

ns

CC

ns

CCEN

ns

CI

35
24
24
18

38
35
35
18

0
0
0
0

0
0
0
0

ns

18
18
7

0
0
0
0

12

0

0

ns

RLO

19

20

0

0

ns

CC
CCEN
CI
RLO

ns
ns
ns

2551 tbl07

2551 !bll0

II. COMBINATIONAL DELAYS
y
Inputs
00-11

10-3
CC
CCEN
CP
OE(l)

II. COMBINATIONAL DELAYS
y

FULL

PL, VECT, MAP

Mil.

Com'l.

Mil.

Com'l.

Mil.

Unit

-

-

ns

30

35

-

-

ns

CC

30

25
40
36

-

10-3

20
35

-

-

-

-

ns

-

ns

CCEN

22

25

ns

-

-

ns

CP
OE(l)

Mil.

Com'l.

Mil.

Com'l.

Mil.

Unit

12
20
16

15
25
20

-

-

-

ns

00-11

13

15

-

-

ns

-

-

-

-

-

-

-

-

-

16
20
28
33
10/10 13/13

FULL

PL, VECT, MAP

Com'l.

Inputs

Com'l.

36
30
46
40
25/27 25/30

ns

-

-

ns

-

31

-

-

35

ns

-

-

-

-

ns

NOTE:
2551 tbl08
1. Enable/Disable. Disable times measure to O.SV change on output voltage
level with CL = SpF. Tested at CL = SOpF. correlated to SpF.

NOTE:
255Hbl II
1. Enable/Disable. Disable times measure to O.SV change on output voltage
level with CL = SpF. Tested at CL = SOpF. correlated to SpF.

III. CLOCK REQUIREMENTS

III. CLOCK REQUIREMENTS

Minimum Clock LOW Time
Minimum Clock HIGH Time
Minimum Clock Period

Com'l.

Mil.

Unit

18
17
35

20
20
40

ns

Minimum Clock LOW Time

ns

Minimum Clock HIGH Time

ns

Minimum Clock Period

2551 tbl09

Com'l.

Mil.

Unit

20
20
50

25
25
51

ns

ns
ns
2551 tbl12

SWITCHING WAVEFORMS
INPUTS

OV3.0V-=====xg~:22~K=====~~~~

CLOCK

3.0V
OV
CLOCK TO
OUTPUT DELAY

OUTPUTS
2551 drw 06

S.4

11

II

IDT49C410/A
16-BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C410 INPUT/OUTPUT
INTERFACE CIRCUITRY
Vee
ESD
PROTECTION
IIH ....

OUTPUTS
INPUTS~--

Figure 3. Output Structure

Figure 2. Input Structure

2551 drw08

2551 drw 07

TEST LOAD CIRCUIT
Vee

Test

Switch

Open Drain
Disable Output from Low
Enable Output to Low

Closed

All other Outputs

Open

2551 tbl13
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator

Figure 4. Switching Test Circuits
2551 drw 09

AC TEST CONDITIONS
Input Pulse Levels
Input RiselFall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to 3.0V
1V/ns
1.5V
1.5V
See Figure 3
2551 tbl14

5.4

12

IDT49C410/A
16-BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

49C410
Device Type

x
Process!
Temperature

~y

BLANK
B

Commercial (O°C to + 70°C)
Military (- 55°C to + 125°C)
Compliant to MIL-STD-883. Class B

P
C
J
F

Plastic DIP
Sidebraze DIP
PLCC
Flatpack

Blank
A

16-Bit Microprogram Sequencer
Fast 16-Bit Microprogram Sequencer

49C410

2551 drw 10

I

5.4

13

(;5

16 x 16 PARALLEL CMOS
MULTIPLIER-ACCUMULATOR

IDT7210L

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• 16 X 16 parallel multiplier-accu mu lator with selectable
accumulation and subtraction
• High-speed: 25ns multiply-accumulate time
• IDT721 0 features selectable accumulation, subtraction,
rounding and preloading with 25-bit result
• IDT7210 is pin and functionally compatible with the TRW
TDC1010J
• Performs subtraction and double precision addition and
multiplication
• Produced using advanced CEMOSTM high-performance
technology
• TIL-compatible
• Available in plastic and topbraze DIP, PLCC, Flatpack
and Pin Grid Array
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing #5962-88733 is listed on this
function

The IDT721 0 is a high-speed, low-power 16 x 16-bit parallel
multiplier-accumulatorthat is ideally suited for real-time digital
signal processing applications. Fabricated using CEMOS
silicon gate technology, this device offers a very low-power
alternative to existing bipolar and NMOS counterparts, with
only 117 to 1/10 the power dissipation and exceptional speed
(25ns maximum) performance.
A pin and functional replacement for TRW's TDC 101 OJ the
I DT721 0 operates from a single 5 volt supply and is compatible
with standard TIL logic levels. The architecture of the IDT721 0
is fairly straightforward, featuring individual input and output
registers with clocked D-type flip-flop, a preload capability
which enables input data to be pre loaded into the output
registers, individual three-state output ports forthe Extended
Product (XTP) and Most Significant Product (MSP) and a
Least Significant Product output (LSP) which is multiplexed
with the Y input.
The XIN and YIN data input registers may be specified
through the use of the Two's Complement input (TC) as either
a two's complement or an unsigned magnitude, yielding a fullprecision 32-bit result that may be accumulated to a full 35-bit
result. The three output registers - Extended Product (XTP),
Most Most Significant Product (MSP) and Least Significant
Product (LSP) - are controlled by the respective TSX, TSM
and TSL input lines. The LSP output can be routed through YIN
ports.

FUNCTIONAL BLOCK DIAGRAM
XIN

CLKX

(XIS-Xl»

ACC, SUB,
AND, TC

CLKY

YIN

(Y1S-YO'P1S-Po)

L-__~__~

CLKP--~~____~__~____~____

TSX

2577 drwOl

CEMOS is a trademark of Integrated Device Technology, Inc.

IDT7210

MILITARY AND COMMERCIAL TEMPERATURE RANGES
«:>1990 Integrated Device Technology, Inc.

5.5

JUNE 1990
DSC·201812

1

IDT7210L
16 x 16 PARALLEL CMOS MULTIPUER·ACCUMULATOR

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

DESCRIPTION (Continued)
The Accumulate input (ACC) enables the device to perform
either a multiply or a multiply·accumulate function. In the
multiply·accumulate mode, output data can be added to or
subtracted from subsequent results. When the Subtraction
(SUB) input is active simultaneously with an active ACC, a
subtraction can be performed. The double precision
accumulated result is rounded down to either a single precision
or single precision plus 3·bit extended result. In the multiply

mode, the Extended Product output (XTP) is sign extended in
the two's complement mode or set to zero in the unsigned
mode. The Round(RND) control roundsupthe Most Significant
Product (MSP) and the 3·bit Extended Product (XTP) outputs.
When Preload input (PREL) is active, all the output buffers are
forced into a high·impedance state (see Preload truth table)
and external data can be loaded into the output register by
using the TSX, TSL and TSM signals as input controls.

PIN CONFIGURATIONS
0

Po,
P1,
P2,
P3,

P4,

Ps,

P6,
P7,

X6
X5
X4
X3
X2
X1
Xo
Yo
Y1
Y2
Y3
Y4
Y5
Y6
Y7

X7
X8
X9

C'J'M~"Uf

RND
SUB

ACC
CLKX
CLKY
Vee
TC
TSX
PREL
TSM
CLKP
P34
P33
P32
P31
P30
P29
P28
P27
P26
P25
P24

DIP
VIEW

(\.1

M

...,

L()

?-~ >-.>-.>- >- >-.>-

0

6059585756555453 525150494847464544

X11
X12
X13
X14
X15

GND

.;.>. 0

a. a. a:.a. a. a. (!) (!) a.a.

X10

Pa, Y8
pg. Y9
P10,
P11,
P12,
P13,
P14,
P1S,

~ ~ .;.>.

43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
1011121314151617181920212223242526

PH
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33

2577 drw 03

~~O~O~UUUUOX~~a.~

x~~~~~ggg~~~~~~a.
00
a. 0
PLCC
TOP VIEW
0..- N

M~

Ii)

>-~-J!.)!'';'~>-o>-~>->->- >->- >.:.;,£ ..;.,;..;-,..:z moig-::"~~:f '!!

2577 drw 02

0. 0.

0. 0. 0.0. C!) 0.0. 0. 0. 0.

c.c.

0.

JlJU1D J!JU1~JU~ UUll ~1~U

TOP

PO, Yo 1:: 1
Xo 1::2
XI 1::3
X2 1:: 4
X3 1::5
X4 C 6
X5 C7
Xs 1::8
X7 1::9
Xs 1::10
X9 1:: 11
XIO 1:: 12
XII C13
XI2 C14
XI3 1:: 15
XI4 1::16

48:::1
47:::1
46:::1
45:::1
44:::1
43::J
42::J
41:::1
40:::1
39:::1
38:::1
37:::1
36::J
35::J
34:::1
33:::1

F64·1

PIS
P17
PI8
PI9
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31

I

4

UUUUUUUUUUUUUUUU
~...JO ro()~>- g ()X...J::E 0. 0Ii
N

2577 drw04

("J

X

~~ ~() ...J~> I-~~cn ~c. &&

« () ()

0. I- ()

FLATPACK
TOP VIEW

5.5

2

II

1DT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR

11

MILITARY AND COMMERCIAL TEMPERATURE RANGES

NC

X15

RND

ACC CLKv

TSL

SUB CLKx

Vee

TC

PREL CLKp

P33

TSM

P32

P34

NC

10

X13

X14

09

XII

X12

P30

P31

08

X9

Xl0

P2a

P29

07

X7

Xa

P26

P27

06

X5

Xs

P24

P25

05

X3

X4

P22

P23

04

XI

X2

P20

P21

03

Yo,
Po

Xo

NC

Yl,
PI

Y3,
P3

Y5,
P5

•

Y2,
P2

Y4,
P4

B

C

02

01

pin1/
A
Designator

TSX

G68-2

PIa

P19

Y7,
P7

Ya,
Pa

Yl0,
PIa

Y12,
P12

Y14,
PH

PIS

P17

Ys,
Ps

GND

Y9,
P9

Yll,
Pll

Y13,
P13

Y15,
P15

NC

D

E

F

G

H

K

L
2577 drwOS

PGA
TOP VIEW

ABSOLUTE MAXIMUM RATINGS(1)
Symbol

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Commercial

Military

Unit

Power Supply
Voltage

-0.5 to +7.0

-0.5 to +7.0

V

VTERM

Terminal Voltage
with Respect to
GND

-0.5 to
Vee +0.5V

-0.5 to
Vee +0.5V

V

TA

Operating
Temperature
Temperature
Under Bias

o to +70

-55 to +125

°C

-55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

50

50

mA

Vee

TSIAS

Rating

TSTG

Storage
Temperature

lOUT

DC Output
Current

Parameter(1)

Conditions

Max.

Unit

CIN

Input Capacitance

VIN = OV

10

pF

COUT

Output Capacitance

VOUT= OV

12

pF

Symbol

NOTE:
25771b107
1. This parameter is measured at characterization and not 100%tested.

NOTE:
25771bIOl
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

5.5

3

IDT7210L
16 x 16 PARALLEL CMOS MULTIPUER-ACCUMULATOR

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS
(Commercial: Vee = 5.0V ± 10%, TA = O°C to +70°C; Military: Vec = 5V ± 10%, TA = -55°C TO + 125°C)

Symbol

Parameter

Commercial
Typ. 10 MHz

Min.

Military
Typ.(1) Max.

Unit

-

2.0

-

-

0.8

-

0.8

V

-

10

J.lA

10

-

-

10

J.lA

45

90

-

45

110

mA

-

20

50

-

20

50

mA

-

4

10

-

4

12

mA

-

-

6

-

-

8

mAl
MHz

Vee

2.4

2.4

-

-

-

-

-

Vee

0.4

-

0.4

-

-20

-

= Max., VIN = OV to vee
Hi Z, vee = Max.,
VOUT = 0 to vee
Vee

leelf(2,3) Increase in Power Supply
Current/MHz

Vee

VOH

Output HIGH Voltage

VOL(4)

Output LOW Voltage

los

Output Short Circuit Current

= Min., 10H = -2.0mA
= Min., 10L = 4mA
Vee = Max., Vo GND

-20

10

V

V
V

-

mA

NOTES:

2577tb103

1. Typical implies Vcc = 5V and TA = +25°C.
2. Icc is measured at 10MHz and VIN = 0 to 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range:
Icc = 90+ 6{f -10)mA, where f = operating frequency in MHz. For the military range, Icc = 110 + 8{f -10). f = operating frequency in MHz, f = 1/tMA.
3. For frequencies greater than 10MHz, guaranteed by design, not production tested.
4. IOL =8mA for tMA = 20ns to 55ns.

AC ELECTRICAL CHARACTERISTICS COMMERCIAL

(Vee = 5V +
- 10%, TA = 0° to +70°C)

7210L25
Symbol

Parameter

7210L35

7210L45

7210L55

7210L65

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
65
ns
25
- 35 - 45
55

tDIS

3-State Disable Time(1)

-

20

-

25

-

25

-

30

30

ns

Input Register Set-up Time

12

-

12

-

15

20

-

25

ns

tH
tpw

Input Register Hold Time

3

3

3

-

ns

10

15

-

3

10

-

3

Clock Pulse Width

20

-

-

-

-

-

ts

25

-

tMA

Multiply-Accumulate Time

to

Output Delay

tENA

3-State Enable Time

20
20

25
25

-

25

25

30

-

35

ns

30

-

30

ns

NOTES:

ns
2577tb104

1. Transition is measured ±500mV from steady state voltage.

AC ELECTRICAL CHARACTERISTICS MILITARY

(Vee =5V± 10%, TA =-55° to +125°C)

7210L30
Symbol

Parameter

7210L40

7210L55

7210L65

7210L75

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

30

-

20

-

25

25

-

-

-

3
20

3

-

3

-

ns

25

-

ns

tMA

Multiply-Accumulate Time

-

30

-

40

55

Output Delay

20

-

25

-

30

tENA

3-State Enable Time

20

-

25

3-State Disable Time(1)

20

-

25

ts

Input Register Set-up Time

12

-

15

tH
tpw

Input Register Hold Time

3

-

10

-

3
15

-

-

30

tDIS

-

-

to

Clock Pulse Width

NOTES:

25

65

-

75

ns

35

-

35

ns

30

-

35

ns

30

-

30

ns
ns

2577 tbl 05

1. Transition is measured ±500mV from steady state voltage.

5.5

4

II

IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SIGNAL DESCRIPTION
INPUTS
XIN (X15 through Xo) YIN (Y15 through Yo) -

TSX, TSL, TSM (Three-State Output Controls) - The
XTP, MSP and LSP registers are controlled by direct
non-registered control signals. These output drivers are at
high impedance (disabled) when control signals TSX, TSM
and TSL are high and are enabled when TSX, TSM and TSL
are low.

Multiplicand Data Inputs
Multiplier Data Inputs.

INPUT CLOCKS
CLKX, CLKY -Input data is loaded on the rising edge of
these clocks.
CONTROLS
ACC (Accumulate) - When ACC is high, the contents of
the XTP, MSP and LSP registers are added to or subtracted
from the multiplier output. When ACC is low, the device acts
as a simple multiplier with no accumulation being performed
and the next product generated will be stored directly into the
output registers. The ACC signal is loaded on the rising edge
of the CLKX or CLKY and must be valid forthe duration of the
data input.
SUB (Subtract) - When the ACC and SUB signals are
both high, the contents of the output register are subtracted
from the next product generated and the difference is stored
back into the output registers at the rising edge of the next
CLKP. When ACC is high and SUB is low, an addition instead
of a subtraction is performed. Like the ACC signal, the SUB
signal is loaded into the SUB register at the rising edge of
either CLKX or CLKY and must be valid over the same period
as the input data is valid. When the ACC is low, SUB acts as
a "don't care" input.
TC (Two's Complement) - When the TC control is high,
it makes both the X and Y input two's complement inputs.
When the TC control is low, it makes both inputs, X and Y,
unsigned magnitude inputs.
RND (Round}--A high level at this input adds a "1" to the
most significant bit of the LSP to round up the XTP and MSP
data. RND, like ACC and SUB, is loaded on the rising edge of
either CLKX or CLKY and must be valid for the duration of the
input data.
PREL (Preload) - When the PREL input is high, the
output is driven to a high impedance state. When the TSX,
TSL and TSM inputs are also high, the contents of the output
register can be preset to the preload data applied to the output
pins at the rising edge of CLKP. The PREL, TSM, TSL and
TSX inputs must be valid over the same period that the
preload input is valid.
YIN ILSP Output - Shares functions between 16-bit data
input (YIN) and the least significant product output (LSP).

5.5

OUTPUT CLOCK
CLKP - Output data is loaded into the output register on
the rising edge of this clock.
OUTPUTS
XTP (P34 - P32) -

Extended Product Output (3-bits)

MSP (P31 - P16) -

Most Significant Product

LSP (P15 - Po) - Least Significant Product shared with YIN
input

NOTES ON TWO'S COMPLEMENT FORMATS
1. In two's complement notation, the location of the binary
point that signifies the separation of the fractional and
integer fields is just after the sign, between the sign bit (_2°)
and the next significant bit for the multiplier inputs. This
same format is carried over to the output format, except that
the extended significance of the integer field is provided to
extend the utility of the accumulator. In the case of the
output notation, the output binary point is located between
the 2 0 and 2- 1 bit poSitions. The location of the binary point
is arbitrary, as long as there is consistency with both the
input and output formats. The number field can be considered entirely integer with the binary point just to the right of
the least significant bit for the input, product and the
accumulated sum.
2. When in the non-accumulating mode, the first four bits
(p 34 to p 31 ) will all indicate the sign of the product.
Additionally, the p30 term will also indicate the sign with one
exception, when multiplying-1 x-1. Withthe additional bits
that are available in this multiplier, the -1 x -1 is a valid
operation that yields a + 1 product.
3. In operations that require the accumulation of single products or sum of products, there is no change in format. To
allow for a valid summation beyond that available for a
single multiplication product, three additional significant
bits (guard bits) are provided. This is the same as if the
product was accumulated off-chip in a separate 35-bit wide
adder. Taking the sign at the most significant bit position will
guarantee that the largest number field will be used. When
the accumulated sum only occupies the right hand portion
of the accumulator, the sign will be extended into the lesser
significant bit positions.

5

IDT7210L
16 x 16 PARALLEL CMOS MULTIPUER-ACCUMULATOR

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS
Input Pulse Levels

PRELOAD TRUTH TABLE
GNDto3.0V

PREL

TSX

TSM

TSL

XTP

MSP

Input Rise/Fall Times

5ns

0

0

0

0

Q

Q

Q

Input Timing Reference Levels

1.5V

0

0

0

1

Q

Q

HiZ

1.5V

0

0

1

0

Q

HiZ

Q

See Figure 1

0

0

1

1

Q

HiZ

HiZ

0

1

0

0

HiZ

Q

Q

0

1

0

1

HiZ

Q

HiZ

0

1

1

0

HiZ

HiZ

Q

0

1

1

1

HiZ

HiZ

HiZ
HiZ

Output Reference Levels
Output Load

2577tbl06

LSP

1

0

0

0

HiZ

HiZ

1

0

0

1

HiZ

HiZ

PL

1

0

1

0

HiZ

PL

HiZ

1

0

1

1

HiZ

PL

PL

1

1

0

0

PL

HiZ

HiZ

1

1

0

1

PL

HiZ

PL

1

1

1

0

PL

PL

HiZ

1

1

1

1

PL

PL

PL

NOTES:
25771b108
Hi Z = Output buffers at high impedance (output disabled)
Q = Output buffers at low impedance. Contents of output register will be
transferred to output pins.
PL = Output buffers at high impedance or output disabled. Preload data
supplied externally at output pins will be loaded into the output register at the rising edge of CLKP.

5.5

6

•

IDTI210L
16 x 16 PARALLEL CMOS MULTIPUER-ACCUMULATOR

MIUTARV AND COMMERCIAL TEMPERATURE RANGES

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

25771b108
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
Rr = Termination resistance: should be equal to Zour of the Pulse
Generator.

Figure 1. AC Test Load Circuit

Vee
ESD
PROTECTION

INPUTS

~H
+-----0 OUTPUTS

O---"'../'v--+--i

t:L

ilL +- R

Figure 2. Input Interface Circuit

Figure 3. Output Interface Circuit

5.5

7

~6

)(::1

.... N

BINARY POINT

en ....

"CO

>r

4~

:::tI

X

X8

_20 2-1 12-2 2-3 2-4 2-5

DIGIT
2-7 2-6 2-9 2-10 2-11 2-12 2-13 2-14 2-15 VALUE

2~

X7

Y15 Y141 Y13 Y12 Y11 Y10 Y9

Y8

_20 2-1 12-2 2-3 2-4

2-7 2-6

2-5

2~

Y7

Xs

Ys

X5

Ys

X4

Y4

X3

Y3

X2

Y2

Xl

Xo

Yl

Yo

>

F
m

SIGNAL

XIS X14j X13 X12 XII Xl0 X9

r

o
3:
o
(J)

SIGNAL

3:

c:

DIGIT
2-9 2-10 2-11 2-12 2-13 2-14 2-15 VALUE

~

"C

1P341 P331 P321 P31 P30 P291 P28 P27 P2S P2S P24 P23 P22 P21 P20 P19 P18 P17 P1S P15 P 14 1 P 13 1P 12 1PIli P10 1 P9jP8 1 P7 1 pS

~

1_24 12 3 1

121

20

XTP

2-1 12-2 2-3 2-4

5

2-

2~

2-7 2-6
MSP

Jp5 JP4 1P31p21 P1

1Po

SIGNAL

I

DIGIT
2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-1S 2-17 12-1812-1912-201 ~212-2312~~2SI2-2M~~912-30 VALUE
LSP
2577drw 10

C
m
:::tI

:i-

o
o
c:
3:
c:
~

b

Figure 4. Franctional Two's Complement Notation.

:::tI

(11

en
BINARY POINT

:c
E
i;!
:::tI

<

>
z
c

o
o

3:
3:
m

SIGNAL
DIGIT
L-~__~~L-~__~~L--L__~~__-L__~~__- L__~~__- L__~~__~__L-~__J -__L - - L__~__L--L__~~__-L__~~__- L__~~VALUE

XTP

MSP

LSP
2577drw

Figure 5. Fractional Unsigned Magnitude Notation

11

:a
o
>
r
-I

m
3:
"C
m
:::tI

>

-I

c:
:a

m
:::tI

Q:)

>
Z

G')

m

(J)

II

~a

)(-1

~~
,,0

BINARY POINT

~r­

::a
~

XTP

MSP

rrm
r-

Xo

SIGNAL

2°

DIGIT
VALUE

yo

SIGNAL

3::

2°

DIGIT
VALUE

~

Po

SIGNAL

2°

DIGIT
VALUE

o
oen

3::

c:

"mC

:p
~
o
o
c:
c:
~

:c

LSP
2517 drw 12

d

Figure 6. Integer Two's Complement Notation

::a

en

en

,

BINARY POINT

;1

SIGNAL

el'tITe

0

2

I

I~

~

::a
<
~

Z

~ SIGNAL
2

el'tITe

~

SIGNAL

0

el'tITe

0

2

m
::a
0

j;

r

-I

m

3::

LSP

XTP

Ii

2577 drw 13

"::am
~

Figure 7. Integer Unsigned Magnitude Notation

co

-I

c:
::a
m
::a
~
z
G)
m
en

IDT7210L
16 x 16 PARALLEL CMOS MULTIPUER-ACCUMULATOR

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

XXXX
Device Type

A
Power

999
Speed

A
Package

x
Process/
Temperature
Range

~:Iank
P
C
"'"--------tJ
F
G

Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP
Topbraze DIP
Plastic Leaded Chip Carrier
Flatpack
Pin Grid Array

Com'l.
25
35
45
55
65

L...----------------Il L
~----------------------~7210

~~'.}
40
55
65

Speed in Nanoseconds

Low Power
16 x 16 Parallel
2577 drw 14

5.5

10

II

G

IDT7216L
IDT7217L

16 x 16 PARALLEL
CMOS MULTIPLIERS

Integrated Devfce Technology, Inc.

FEATURES:

DESCRIPTION:

•
•
•
•

The IOT7216/IOT7217 are high-speed, low-power
16 x 16-bit multipliers ideal for fast, real time digital signal
processing applications. Utilization of a modified Booths
algorithm and lOT's high-performance, submicron CEMOS
technology, has achieved speeds comparable to bipolar (20ns
max.), at 1/10 the power consumption.
The 10T7216/IOT7217 are ideal for applications requiring
high-speed multiplication such as fast Fourier transform
analysis, digital filtering, graphic display systems, speed
synthesis and recognition and in any system requirement
where multiplication speeds of a mini/microcomputer are
inadequate.
All input registers, as well as LSP and MSP output registers, use the same positive edge-triggered O-type flip-flop. In
the IOT7216, there are independent clocks (CLKX, CLKY,
CLKM, CLKL) associated with each of these registers. The
IOT7217 has only a single clock input (CLK) and three register
enables. ENX and ENY control the two input registers, while
ENP controls the entire product.
The IOT7216/IOT72170fferadditionalflexibilitywiththe FA
control and MSPSEL functions. The FA control formats the
output for two's complement by shifting the MSP up one bit
and then repeating the sign bit in the MSB of the LSP. The

•
•

•
•
•
•
•
•
•
•

16 X 16 parallel multiplier with double precision product
20ns clocked multiply time
Low power consumption: 120mA
Produced with advanced submicron CEMOSTM high
performance technology
IOT7216L is pin- and functionally-compatilble with TRW
MPY016H/K and AMO Am29516
IOT7217L requires only single clock with register enables making it pin- and functionally-compatible with
AMO Am29517
Configured for easy array expansion
User-controlled option for transparent output register
mode
Round control for rounding the MSP
Input and output directly TTL-compatible
Three-state output
Available in plastic and Top Braze, DIP, PLCC, Flatpack
and Pin Grid Array
Military product compliant to MIL-STO-883, Class B
Standard Military Drawing # 5962-86873 is listed on this
function for IOT7216 and Standard Military Drawing
#5962-87686 is listed for this function for IOT7217.

FUNCTIONAL BLOCK DIAGRAMS
IOTI217

IOTI216
XM X15-0

RND

YM Y15-0/P15-0
16

XM X15-0

CLKY __~~____+-+-__~
CLKX -''
l__+-+--'Ir-'""o.

RND

CLKY __4-~--~~+_--~
Em --+-..J.4.o

MULTIPLIER
ARRAY

MULTIPLIER
ARRAY
FA ________

FA--------1-~~~~

t-Tn<'1..-..-----,f"'l"'t"!'--t

CLKL--------------~~

~------~=±~=±~

MSPSEL----------I

MSPSEL----------~

OEP ------------4.

OEP----------------~

MSPOUT (P31 - P16)
CEMOS is

~__1

FT--------~__1

FT----------I
CLKM
~~~~~~

MSPOUT (P31 - P16)

2580 drw 01

2580drw02

a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
101990 Integrated Device Technology. Inc.

5.6

JUNE 1990
DSC-202311

1

IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPUERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

DESCRIPTION (Cont'd.)
MSPSEL low selects the MSP to be available at the product
output port, while a high selects the LSP to be available.
Keeping this pin low will ensure compatibility with the TAW
MPY016H.

The IDT7216/1DT7217 multipliers are manufactured in
compliance with the latest revision of MIL-STD-883, Class B,
making them ideally suited to applications demanding the
highest level of performance and reliability.

PIN CONFIGURATIONS
1017217

1017216

X4

X4

Xs

X3
X2

X7

Xl
Xo
OE!.

X9

Xl0

Xa
X9

Xl0
Xll
X12

ClK

Xl1
X12
X13
X14

Po, Yo
Pl, Yl
P2, Y2
P3, Y3
P4, Y4
Ps, Ys
PEl, Y6
P7, Y7
Pa, Ya
pg, Y9
Pl0, Yl0
Pll, y"
Pl2, Y12
Pl3, Y13
P14, Y14
P1S, Y1S
Po, P16
Pl, PH
P2, Pla
P3, P19
P4, P20
Ps, P2l
Ps, P22
P7, P23

X7

Xl
Xo
OE!.

Xa

8~KJ,

Xs

X6

X3
X2

X6

ENY'"

Po, Yo
Pl, Yl
P2, Y2
P3, Y3
P4, Y4
Ps, Ys
PEl, Y6
P7, Y7
Pa, Ya
pg, Y9
Pl0, Yl0
Pll, Yll
Pl2, Y12
Pl3, Y13
P14, Y14
P1S, Y1S
Po, P16
Pl, P17
P2, Pla
P3, P19
P4, P20
Ps, P2l
PEl, P22
P7, P23

X1S

ClKX
AND

XM
YM
Vee
Vee
GND
GND

~

FT

FA
nEP

ClKM

P1S, P3l
P14, P30
Pl3, P29
P12, P2a
Pll, P27
Pl0, P26
Pg, P2S
Pa, P24

X13
X14

X1S

Ef\JX

RNr5
XM

YM

Vce

Vee

GND
GND

~

FT

FA

•

OE"P
Ef\l'FS

P1S, P3l
P14, P30
Pl3, P29
Pl2, P2a
Pll, P27
Plo, P26
pg, P2S
Pa, P24

258Odrw04

2580 drw03

64-PIN DIP

64-PIN DIP

TOP VIEW

TOP VIEW

5.6

2

IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS (Cont'd.)
IDT7216/IDT7217

11

X13
X14

X1S
ClKX

GND

RND

YM

Vcc

FT

OEP

VCC

GND MSP- FA

ClKM

XM

or

NC

10

X11

X12

09

X9

Xl0

P30,
P14

P3l,
P1S

08

X7

Xa

P2a,
P12

P29,
P13

07

Xs

Xs

P2S,
P10

P27,
Pll

06

X3

X4.

P24,
Pa

P2S,
P9

05

Xl

X2

P22,
Ps

P23,
P7

04

OEL

Xo

P20,
P4

P2l,
Ps

ClKY

ClKl

ENY·

ClK·

Pla,
P2

P19,
P3

02

NC

Yo,
Po

Y2,
P2

Y4,
P4

Ys,
Ps

Ya,
Pa

Y1O,
Pl0

Y12,
P12

Y14,
P14

P1S,
Po

P17,
Pl

01

•

Yl,
Pl

Y3,
P3

Ys,
Ps

Y7,
P7

Y9,
P9

Y11,
P11

Y13,
P13

Y1S,
P1S

NC

Pin1/
Designator
A

B

C

D

E

F

G

J

K

03

,

NC

or

or

00·

SEL

G68-2

or

H

EfW"

L

·Pin designation forlDT7217
PGA
TOP VIEW

5.6

2580 drw 05

3

IDT7216L,IDT7217L
16 x 16 PARALLEL CMOS MULTIPUERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS (Cont'd.)
IDT7216

~a..

IDT7217

li1

li1

~oo

U)

olo~ Ii: I~~~gg~~ ~5xxx

a..
SQzz
88::0 ::ozlz
~"$::?
OLLLL I
WxxX
IWzIW-xa:

48::::J
47::::J
46::::J
45::::J
44::::J
43::J
42::J
41::::J
40::::J
39::::J
38::::J
37::::J
36::J
35::J
34::::J
33::::J

F64-1

Pl5,
Pl4,
Pl3,
Pl2,
Pll,
Plo,
P9,
Pa,
P7,
PS,
PS,
P4,
P3,
P2,
Pl,
PO,

X12

Xll
Xl0
)(g

Xs
X7

Xs
Xs
X4
X3
X2
Xl

Xo

orr

CLKL

P3l
P30
P29
P2a
P27
P26
P2S
P24
P23
P22
P2l
P20
P19
Pla
P17
P1S

. . . . -----------...w....L 48::::J X12
47::::J
46::::J
45::::J
44::::J
43::J
42:::1
41::::J
F64-1
40::::J
39::::J
38::::J
37::::J
36::J
35::J
34::::J
T'n-_ _ _ _ _ _ _ _ _ _-nT 33::::J

17181920212223242526272829303132

17181920212223242526272829303132

~~~~~~~~~~~~~~~~
':! "$- c;! r;! ~ ~ 8! rt &: if. rf &.-~ a.. &.

~~ ~~~~ ~>:~~->:>!-~~>-~­

r1

2SS0 drw 07

64-LEAD FLATPACK
TOP VIEW

64-LEAD FLATPACK
TOP VIEW

....J>-

"'~
0
~~~
O........ ..-mCO,.....CDLl)VC")NT""Q
....,J.....J
ZX>< xxX>< XXXXXXX
00
6059585756555453525150494847464544
X1361
X1462
X1563
CLKX 64
RND65
XM66
YM67
Vee 68

Vee

o C\I~O
~ ~ ~

1
2

GND
GND 3

~4
FT 5

FA 6
OEP 7

CLKM 8

NC 9

"'xC')

C\I ~ 0

xxx

•

~~~
....J
0

605958 5756555453525150494847464544
NC

X1361
X1462
X1563

Po, Yo
Pl, Yl
P2, Y2
P3, Y3
P4, Y4
Ps, Y5
Ps, Y6
P7, Y7
Pa, Y8
P9, Y9
Pl0, Yl0
Pll, Yll
Pl2, Y12
Pl3, Y13
P14, Y14
P1S, Y15

~W6~~
XM 66
YM67

Vee68
Vee 1
GND 2
GND 3
MSPSEL 4
FT5
FA 6
OEP 7
ENP 8
NC 9

1011121314151617181920212223242526

&~ ~~~~ ~~&~ I.~:r~~
';!"$ ~ ~ ;: 1rf rfa: if (fa: d!. O!. c( ~

IDT7217
Cl  10 MHz

-

-

4

-

20

leeQ2

-

6

mAl
MHz

-

0.4

lee/f(2.3) Increase in Power Supply
Current MHz

10

VOH

Output HIGH Voltage

Vec = Min., 10H = -2.0mA

2.4

-

-

2.4

VOL(4)

Output LOW Voltage

Vee = Min., 10L = 4mA

-

-

0.4

-

los

Output Short Circuit Current

Vee = Max., Vo = GND

·20

-

-

·20

V

-

V
V

-

mA

NOTES:
2580tbl03
1. Typical implies Vcc = 5V and TA = +25°C.
2. Icc is measured at 10MHz and VIN = 0 to 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range:
Icc = 80+ 4(f -10)mA; for the military range, Icc = 100 + 6(f -10). f = operating frequency in MHz, f = l/tMUC for IDT7216 and f = l/tMC for IDT7217.
3. For frequencies greater than 10MHz, guaranteed by design, not production tested.
4. 10L = 8mA for tMC = 20 to 55ns

5.6

5

IDT72161, IDT7217L
16 x 16 PARALLEL CMOS MULTIPUERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS
Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

3ns

Input Timing Reference Levels

1.SV

Output Reference Levels

1.SV

Output Load

See Figure 1
2580 IIlI 08

SWITCH POSITION

Figure 1. AC Test Load Circuit

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2580 IIlI 09
CL = Load capacitance: includes jig and probe capacitance.
Rr = Termination resistance: should be equal to Zour of the Pulse
Generator.

Vee
ESD
PROTECTION

INPUTS

J

o---'"'V'v--+-----t

III

4-

R

Figure 2. Input Interface Circuit

~H

...---0 OUTPUTS

t:L

II

Figure 3. Output Interface Circuit

5.6

6

IDT7216L, 1DT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS COMMERCIAL (Vee = 5V ± 10%, TA = 0° to +70°C)
Symbol

7216L20/25
7217L20/25
Max.
Min.

Parameter

-

30/38

tMUC

Unclocked Multiply Time

tMC

Clocked Multiply Time

ts

X, Y, RNO Set-up Time

tH

X. Y. RNO Hold Time

tPWH

Clock Pulse Width High
Clock Pulse Width Low

11/12
1/2
9/10
9/10

20/25

tPWl
tPDSEL
tpop

MSPSEL to Product Out

-

Output Clock to P

tpOY

Output Clock to Y

-"""

tENA

3·State Enable Time

----::
..•...•.•..;
:::',::..;.'

'\T

,ti:-;;""
.,.\'18/20
' ,'18/20

-1::':::/ 18/20

,T:'

18/20
18/20

7216L35/45
7217L35/45
Min.
Max.

-

Unit

55/65

-

75/85

ns

35/45

-

55/65

ns

12/15

-

20

3
10/15

-

3

-

20

-

10/15

-

tOIS

3-State Enable Time(2)

::::::::..

ts

Clock Enable Set-up Time (10T7217 only)

10

-

10

tH
tHCL

Clock Enable Hold Time (IOT7217 only)
Clock Low Hold Time CLKXY Relative to CLKML
(10T7216 only)(1·3)

0/2
0

-

3
0

-

7216L55/65
7217L55/65
Min.
Max.

15

ns
ns
ns

25

-

25/30

ns
ns

25

-

30

ns

25
25
22

-

10
3
0

30

ns

30/35

ns

25

ns

-

ns
ns

ns

NOTES:
2580tbl06
1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been
clocked.
2. Transition is measured ±500mV from steady state voltage.
3. Guaranteed by design, not production tested.

AC ELECTRICAL CHARACTERISTICS MILITARY (Vee = 5V ± 10%. TA = -55° to +125°C)
7216L25/30
7217L25/30

7216L40/55
7217L40/55

7216L65175
7217L65175

Min.

Max.

Min.

Max.

Min.

Max.

Unit

38/43

-

60175
40/55

-

85/95

ns

Clocked Multiply Time

-

65175

ns

ts

X. Y. RNO Set-up Time

12

.'.

15/20

25

X. Y, RNO Hold Time
Clock Pulse Width High

2
10

/\~

3
15

tPWL
tposEL

Clock Pulse Width Low

10 .,.::

::::-

-

3
15

15

-

15

-

ns

tH

-

-.,/}

20

25130

-

35

ns

tpop

Output Clock to P

~,,:>

20

25130

ns

Output Clock to Y

25130

-

30135

tpOY

30135

ns

tENA

3-State Enable Time
3-State Enable Time(2)

-

25

-

35/40

25

-

25

ns
ns

-

15

-

Symbol

Parameter

tMUC

Unclocked Multiply Time

tMC

tPWH

tOIS

MSPSEL to Product Out

25130

.A§l

.:'\!t'-

20

,::}?-

20

-

22

-

ts

Clock Enable Set-up Time (IOT7217 only)

10

tH

Clock Enable Hold Time (IOT7217 only)

2

tHCL

Clock Low Hold Time CLKXY Relative to CLKML
(IOT7216 only)(1,3)

0

12/15
3
0

3
0

ns
ns
ns

ns
ns
ns

NOTES:
2580tbl07
1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been
clocked.
2. Transition is measured ±500mV from steady state voltage.
3. Guaranteed by design, not production tested.

5.6

7

IDT72161, IDT7217L
16 x 16 PARALLEL CMOS MULTIPUERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

CLKX
CLKY
INPUT Xl, Yl,
RND

CLKM
CLKL
OUTPUTY

CLKM
CLKL
MSPSEL
OUTPUT P

1.---------------tMuc---------------+1
2580 drw 13

II

. Figure 4. 1DT7216 Timing Diagram

5.6

8

IDT7216L, 1DT7217L
16 x 16 PARALLEL CMOS MULTIPUERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

~tPWH~

elK

_ _----'I

,,----I_----'

X1, Y1,
RND

~~~I~_ _ _ _-+__~ ~~~~~~~~~~~~~~~~~~~~~

OUTPUTY

OUTPUTP
~-------------tMUC------~~----~
2580 drw 14

Figure 5. 1DT7217 TIming Diagram

5.6

9

IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SIGNAL DESCRIPTION:
INPUTS:
XIN (X15 through Xo)
Sixteen multiplicand data inputs
YIN (Y15 through YO)
Sixteen multiplier data inputs. (This is also an output port
for P15-0)

INPUT CLOCKS (IDT7216 ONLY)
ClKX
The rising edge of this clock loads the X15-0 data input
register along with the X mode and round registers.
ClKY
The rising edge of this clock loads the Y15-0 data input
register along with the Y mode and round registers.
ClKM
The rising edge of this clock loads the Most Significant
Product (MSP) register.
ClKl
The rising edge of this clock loads the Least Significant
Product (LSP) register.

INPUT CLOCKS (IDT7217 ONLY)
ClK
The rising edge of this clock loads all registers.

FA (RS)(1)
When the format adjust control is HIGH, afull32-bitproduct
is selected. When this control is LOW, a left-shifted 31-bit
product is selected with the sign bit replicated in the Least
Significant Product (LSP). This control is normally HIGH
except for certain fractional two's complement applications
(see Multiplier InpuUOutput Formats).
FT
When this control is HIGH, both the Most Significant
Product (MSP) and Least Significant Product (LSP) registers
are transparent.

OEl
Three-state enable for routing LSP through YIN/LSPOUT
port.

OEP
Three-state enable for the product output port.
RND
Round control for the rounding of the Most Significant
Product (MSP). When this control is HIGH, a one is added to
the Most Significant Bit (MSB) of the Least Significant Product
(LSP). Note that this bit depends on the state of the format
adjust (FA) controL If FA is LOWwhen RN D is HIGH, a one will
be added to the 2- 16 bit (P14). If FA is HIGH when RND is
HIGH, a one will be added to the 2- 15 bit (P15).ln either case,
the LSP output will reflect this addition when RND is HIGH.
Note also that rounding always occurs in the positive direction
which may introduce a systematic bias. The RND input is
registered and clocked in at the riSing edge of the logical OR
of both CLKX and CLKY.

ENX
Register enable for the X 15-0 data input register along with
the X mode and round registers.

MSPSEl
When the MSPSEL is LOW, the Most Significant Product
(MSP) is selected. When HIGH, the Least Significant Product
(LSP) is available at the product output port.

ENY
Register enable forthe Y15-0 data input register along with
the Y mode and round registers.

OUTPUTS

ENP
Register enable for the Most Significant Product (MSP)
and Least Significant Product (LSP).

MSP (P31 through P16)
Most Significant Product output.

CONTROLS

Y15-O IlSPOUT (Y15 through Yo or P15 through Po)
Least Significant Product (LSP) output available when
OEL is LOW. This is also an output port for Y15-O.

XM, YM (TCX, TCy)(1)
Mode control inputs for each data word. A LOW input designates unsigned data input and a HIGH input designates
two's complement.

5.6

lSP (P15 through Po)
Least Significant Product output.

10

I

~6

BINARY POINT

)(:j

4

01 ....

X

"=

.... N

"'COl

~r

XIS Xu X13 X12 ~11 Xl0 X9

Xe

X7

_20

Z-7

z-e

Z-1

2-,2 z-3 2""""

Y15 Y14 Y13 Y1Z

~11

2~

Z-5

IYl0 Y9

Y8

Xs X5

X4

2-9 2-10 2"11

Xz

X3

Y7

Ys Y5

z-e

2-9 2-10 2"11

Y4

Z-12

Xl

2-13

Xo

Z-14 Z-15

Y3

Y2

Yl

Z-12

2-13

Z-14 Z-15

:tI-

SIGNAL

~3
,N
m ....

, .....

DIGITAL VALUE

0'
3:

oen

SIGNAL

Yo

3:

_20

Z-1

P31

P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 PIS P17 P16 P15 P14 P13 P12 Pll Pl0 P9

_20

Z-1

2-,2 z-3 2""""

2-,2 z-3 2""""

z-s

2~

Z-7

2~

Z-5

Z-7

z-e

2-9 2- 10 2"11

Z-12

2-13

Z-14 Z-15

c

DIGITAL VALUE

-'t 2-1S Z-17

Z-18

~

2-19 Z-2O

P8

P7

Ps

P5

P4

P3

~21

2-22

Z-23

2"24

r 25

2"26

Z-27 ;>-28

Ps

P7

P5

P4

P3

MSP
lp31

P9

Ps

Z-512~ I Z-7 1 z-e I ~ 12-10 I z!1 1 Z-12 ~ - 13 1Z-1412""15 12-1S I Z-171Z-1812-191 Z-2O 12-21 12-22 1 Z-23 12"24

t-

25

cm

Po

Z-29

z-3O DIGITAL VALUE
IFA= 0

:tI

en

I

P2

PI

Po

26 27 28
I2" 1Z- ~ - IZ-29 I z-3O I

LSP

MSP

=ti

SIGNAL

PI

LSP

P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 Pl1 Pl0

1-2 112 0 Z-1 I 2-,21 z-312""""1

P2

SI GNAL

~ GITAL VALUE
!FA = 1

I

Figure 6. Fractional Two's Complement Notation

2580drw IS

en

m

BINARY POINT
3:

~15 X14 X13 X12 Xl1 ~10 X9
Z-1

2-2 2-3

z-4 Z-5

2~

Z-7

X8

X7

X6

X5

X4

2-8

2-9 12"10

~11

Z-12

X3

X2

XI

Xo

.713 12"14 2-15 7 16

E

SIGNAL

~

:tI

<

DIGITAL VALUE

~

Z

X

~15 Y14 Y13 !V12 Yll Yl0 Y9 Y8 Y7 Ys Y5 Y4 Y3 Y2 Yl Yo
Z-1 2-2 2-3 z-4 Z-5 2~ Z-7 2-8 2-9 12"10 ~11 Z-12 ,Z-13 12"14 2-15 7 16

C

SIGNAL

o

o

3:
3:
m

DIGITAL VALUE

:tI

P31

P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 PIS P14 P13 P12 Pl1 PIO

t-2"1

2-2 ~

r

75

2~

77

~

~9

Z-IO 2"11 7 12 .713

Z-14

2-15

~16 ~17

Z-18

Z-19

Ps

P5

Z-2O Z-21 2-22 7 23 2"24 7 25 2"26

~27

P9

P8

P7

LSP

MSP

P4

P3

P2

PI

Po

:>-28 2-29 2-30 z-31 z-32

o

SIGNAL

,>

DIGITAL VALUE

m
3:

I

!FA = 1
MANDATORY

-i

"'C

m

:tI

~

C

Figure 7. Fractional Unsigned Magnitude Notation

....
....

:tI

2580 drw17

m

:tI
~

Z

G')

m

en

... Ole

BINARY POINT

><::1

"'N

~

01'"
"COl

XIS Xl. X13 X12 IXll Xl0

X9

Xa

X7

X6

Xs

X4

X3

_2 0 2-1 2-2 2-3 2-4 2-s 2-0 2-7 2-8 2-9 2-10 2-11 2-12

X

Pal

~lS Y14 Y13 ty12 Yll Yl0 Y9

Ya

Y7

Y6

Ys

..

2-1 2-2 2-3 2-4 2-s 2-0 2-7 2-8 2-9 2-10 2'"11

Pac Pl9 P.za

P.z7 P.z6 P.zs

P.z4 P.z3

P.z2 P.zl

_2 0 2-1 2-2 2-3 2-4 2-s 2-0 2-7 2-8 2-9 2-10

X2

Xl

XO

~-13

2-14

~-lS

Y4

Y3

~-12

2-13 2-14

f-

Y2

P.zo Pl9 PIa Pl7
Z-11

Yl

PIs Pl4

2-12 2-13 2-14 2-1S 2-16

:%3-

>e

r::1
rN
m'"
r~

or
3:
o
en

SIGNAL
(UNSIGNED MAGNITUDE)
DIGITAL VALUE

Yo

~-lS 2-~6

Pl6

>r

SIGNAL
(TWO'S COMPLEMENT)
DIGITAL VALUE

~-17

f-

Pl3

Pl2 Pll

Plo

P9

P8

3:

c:
P7

2-18 2-19 2-20 2-21 2-22 2-23 2'"24

P6
~-2S

Ps

P4

P3

P2

PI

Po

C
m

2'"26 2-27 2-28 ~-29 2-30 ~-311 DIGITAL VALUE

:%3

en

IFA = 1 I

LSP

MSP

~

"C

SIGNAL
i

MANDATORY

Figure 8. Fractional Mixed Mode Notation

2580drw

18

BINARY POINT
U1

en

4

Xl5

X

-zo -r

,p

'!'6

,fS


z

X2

22
P2

Po

SIGNAL

t 'l

2!

21

t

DIGITAL VALUE

P6

Ps

P4

'Z'

~

P3

IFA=o

21

f1

219

18 217
2

216 215 214 213

212 211

10
2

t

MSP

I

>
r

P.

P3

P2

PI

Po

SIGNAL

't!

'Z

'Z'

~

24

'l

2!

21

t

DIGITAL VALUE

I

• In this format an overflow occurs in the attempted multiplication of the two's complement number 1,000 ... 0 with 1,000.0 yielding an erroneous
30
product of -1 in the fraction case and _2 in the integer case.

-I

m

3:
"C

m

:%3

>
-I
2580 dlW

II

m

Ps

Figure 9. Integer Two's Complement Notation
N

0

0
3:
3:
0

P6

...

-<

:ll

P7

IFA= i

:%3

e

P8

LSP

Ic

!:

p,

LSP

MSP


Z
G)

m
en

~6

><::j
_I\)

01-

'tJQ)

BINARY POINT

>.r
:::tI>0

X1S Xl. X13 X12 1X11 Xl0 X9

~~0

r:::1

rl\)
mr ......

SIGNAL

X8

X7

X6 Xs

X.

'il

28

27

Z'

5

~

t

22

21

2

DIGITAL VALUE

V1S V14 V13 V12 tvll Vl0 V9

V8

V7

Vs Vs

V4

V3

V2

Vl

Vo

SIGNAL

2 8 27

26 2 5

24

2

3 22

21

20

DIGITAL VALUE

25

21• 213 212 211

10
2

2

X,

or
~
(J)
i:

X
P31
~1

215 2 1• 2 13 212 211 2 10 2 9

P30 P29 P28 P27 P26 P2S P24 P23 P22 P21 P20 P19 P18 P17 P16 P1S P14 P13 P12 Pll Pl0
~

-f9 i

8

'i7 -z'-6

is

'i4 i

3

f2 il

~

219

~18

217

216 215

214 213

212

211

10
2

c:

~

t:

m

~

P9

P8

P7

P6

Ps

P4

P3

P2

Pl

Po

SIGNAL

t

8
2

~

6
2

2

5

~

t

22

21

rf

DIGITAL VALUE

MSB

'tJ

p-A = 1 I
MANDATORY

LSP
Figure 10. Integer Unsigned Magnitude Notation

2580 drw20

U1

i7I

BINARY POINT

•

;H
;1
2°

SIGNAL
(TWO'S COMPLEMENT)
DIGITAL VALUE

~

SIGNAL
(UNSIGNED MAGNITUDE)
DIGITAL VALUE

i:

E

i!::tI
-<
z>

c

0
0
i:
i:

m

::tI

~ SIGNAL
2°

LSP

MSB
Figure 11. Integer Mixed Mode Notation

Co)

0

>

DIGITAL VALUE

r

-t

m

IFA = 1 I

i:

MANDATORY

::tI

'tJ

m

>
-t

c:
m

::tI
2580 drw 21

1::tI

>
Z

c;')

m

(J)

IDT72161, IDT7217L
16 x 16 PARALLEL CMOS MULTIPUERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

xxxx
-;D:::""e-v":"'"ic-e-=T=-y-pe-

x
Power

x

x

x

Speed

Package

Process!
Temperature
Range

y~lank
P
C
l..------~J

F
G

L------------i~i }

Commercial (O°C to +70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-SS3, Class B
Plastic DIP
Topbraze DIP
Plastic Leaded Chip Carrier
Flatpack
Pin Grid Array

30
25 }
Commercial (tMC)

55
65

L..---------------iL

~~

Military (tMC)

65
75
Low Power

l . . -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~7216

~7217

16 x 16 Multiplier
2580 drw22

5.6

14

•

(;)®

IDT7381
IDT7383

16-81T CMOS
CASCADA8LE ALU

Integrated Device Technology, Inc.

FEATURES:
• High-performance 16-bit Arithmetic Logic Unit (ALU)
20ns to 55ns clocked ALU operations
• Ideal for radar, sonar or image processing applications
IOT7381 :
- 54/74S381 instruction set (8 functions)
- Replaces Gould S614381 or Logic Oevices L4C381
- Cascadable with or without carry look-ahead
• IOT7383:
- 32 advanced ALU functions
- Cascadable without carry look-ahead
• Pipeline or flow-through modes
• Internal feedback path for accumulation
• Three-state outputs
• TTL-compatible
• Produced with advanced submicron CEMOSTM highperformance technology
• Available in 68-lead PGA and 68-pin surface mount PLCC
• Military product compliant to MIL-STO-883, Class B

DESCRIPTION:
The IOT7381 and IOT7383 are high-speed cascadable
Arithmetic Logic Unit (ALUs). Both three-bus devices have

two input registers, ultra-fast 16-bit ALUs and 16-bit output
registers. With lOT's high-performance CEMOS technology,
the IOT7381n383 can do arithmetic or logic operations in
20ns. The IOT7381 functionally replaces four 54/74S381
four-bit ALUs in a 68-pin package.
The two input operands, A and B, can be clocked or fed
through for flexible pipelining. The F output can also be set
into clocked or flow-through mode. An output enable is
provided for three-state control of the output port on a bus.
The IOT7381 has three function pins to select 1 of 8
arithm~tic or logic operations. The two Rand S selection pins
determine whether A, B, For 0 are fed into the ALU. This ALU
has carry-out, propagate and generate outputs for cascading
using carry look-ahead.
The IOT7383 has five function pins to select 1 of 32
arithmetic or logic operations and the R, S input selections to
the ALU. The Rand S ALU inputs can be A, B, F, 0 or all1s.
This ALU has a carry-out pin for cascading.
The IOT7381 and IOT7383 are available in 68-pin PLCC or
PGA packages. Military grade product is manufactured in
compliant with the latest revision of M IL-STO-883, Class B, for
high reliability systems.

FUNCTIONAL BLOCK DIAGRAM
AO-15

AO-15

80-15

BO-15

ClK
ENS
~~~-l1r- FTAB

FTAB

RSO-l

l~-~---'-----!....----'
CIG -------l".
OVF
___-----lo.
Z ------~'_ _ _ _-,._

___J

/4--4--~~ 10-4
N
CIG
5
OVF ___- - - ' -_ _ _~-~fo~~-~- Co
Z

10-2

Co

~

FTF

FTF - - - - - -.... 1
GND

at; -------~
eEMOS is a trademark of Integrated Device Technology Inc.

~

Vee

•

Vee

16

FO-15

2525 drw 01

MILITARY AND COMMERCIAL TEMPERATURE RANGES
e1990 Integrated Device Technology. Inc.

"1-

GND

5.7

2525 drw 02

APRIL 1990
DSC·2033/1

1

1017381,1017383
16·BIT CMOS CASCAOABLE ALU

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION
1017381

Ag
Al0

87
8s

All
A12

85
84

A13
A14

83
82

A15
ClK

81
80
ENA
EN8

Vee
GND

FTAB

C16

is

RSI

IT

RSo
12

Z
OVF
ENF

11

FTF

Co

10

2525 drw 03

II

PLCC
TOPVIEW

I

11

87

8s

84

82

EN8 RSI

12

10

89

8a

85

83

81

ENA FTAE RSo

11

Co

Fe

09 811

810

F2

Fl

08

813

812

F4

F3

07

815

814

F6

F5

06

Al

Ao

Fa

F7

05

A3

A2

FlO

F9

04

As

A4

F12

Fll

03

A7

As

F14

F13

02

Aa

A9

All

A13

A15

G OVF OE

F15

Al0

A12

A14

ClK GND

8

C

D

10

•

80

G68-1

E

Vee

F

C16

is

Z

G

H

ENF FTF

J

K

l

PGA
TOPVIEW

2525 drw 04

Pin 1
Designator

5.7

2

IDT7381,IDT7383
16-BIT CMOS CASCADABlE AlU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

10T7383

A9
A10

•
Pin 1

A11
A12

Oesignator

B5
B4

58

57
56
55
54
53
52
51
50
49

A13
A14
A15
ClK

Vee
J68-1

GNO

B7
B6

59

C16
GNO*

N

48

Z
OVF
ENF

47
46

B3
B2
B1
Bo
ENA
ENB
FTAB
14
13
12
11
10
Co

45

FTF
w

Io

LO

v

(")

N

-

u:: u:: u:: u:: u::

2525 drw 05

PLCC
TOPVIEW

11

87

86

84

82

89

8a

85

83

81

09 811
08

EN8 RS1

12

10

ENA FTA8 RSo

11

Co

Fo

810

F2

F1

813

812

F4

F3

07

815

814

F6

F5

06

A1

Ao

Fa

F7

05

A3

A2

FlO

F9

04

As

A4

F12

F11

03

A7

A6

F14

F13

02

Aa

A9

A11

A13

N

DVF DE

F15

AlO

A12

A14 ClK GND GND

Z

ENF FTF

8

C

10

•
Pin 1
Designator

80

G68-1

D

A15

E

Vee

C16

F

PGA
TOPVIEW

5.7

G

H

J

K

l

2525 drw 06

3

1017381,IDTI383
16·BIT CMOS CASCADABLE ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTIONS
IDT7381 AND IDT7383 PINS
Pin Name

I/O

Description

Ao· A15

I

Sixteen-bit data input port.
Sixteen-bit data input port.

80 - 815

I

ENA

I

Register enable for the A input port; active low pin.

EN8

I

Register enable for the 8 input port; active low pin.

FTA8

I

Flow-through control pin. When this pin is high, both register A and 8 are transparent.
Sixteen-bit data output port.

Fo - F15

0

ENF

I

Register enable for the F output port; active low pin.

FTF

I

Flow-through control pin. When this pin is high, the F register is transparent.

ClK

I

Clock input.

OE

I

Output enable control pin. When this pin is high, the output port F is in a high impedance state. When low, the output
port F is active.

Co

I

Carry input. This pin receives arithmetic carries from less significant AlU components in a cascade
configuration.

C16

0

Carry output. This pin produces arithmetic carries to more significant AlU components in a cascaded
configuration.

OVF

0

This pin indicates a two's complement arithmetic overflow, when high.

Z

0

This pin indicates a zero output result, when high.

Vee

Power supply pin, 5V.

GND

Ground pin,

av.

There are two ground pins on the IDT7383.
2525 tbl 01

IDT7381 PINS
Pin Name

I/O

RSo- RS15

I

Two control pins used to select input operands for the Rand S multiplexers.

10 - 12

I

Three control pins to select the AlU function performed.

Description

P

0

Indicates the carry propagate output state to the AlU.

G

0

Indicates the carry generate output state to the AlU.
2525 tbl 02

IDT7381 RAND S MUX TABLE

IDT7381 ALU FUNCTION TABLE

RSo

RS1

RMux

SMux

12

h

10

a
a

a

A

F

a

a

1

A

a

0

a
a

1

F=R+S+Co

1

a

a

8

0

1

0

F=R+S+Co

1

1

A

8
2525 tbl 03

Function
F=O

0

1

1

F=R+S+Co

1

a

0

F = R xor S

1

0

1

F = Ror S

1

1

0

F = Rand S

1

1

1

F=aIl1's
2525 tbl 04

5.7

4

•

I

IOT7381, IDT7383
16·BIT CMOS CASCAOABLE ALU

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTIONS (Continued)
IOT7383 PINS
Pin Name

10-14

1/0
I

N

0

Description
Five control pins to select the ALU function performed.
The sign bit of an ALU operation.
2525tbl05

IOT7383 ALU FUNCTION TABLE
14

13

12

h

10

Function

a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a

a
a
a
a
a
a
a
a

a
a
a
a

a
a

a

F=A+B+Co

1

F = A or B

1

a

F=A· B

1

1

F=A+B+Co

1

a

F=A+Co

1

a
a

1

F = Aor F

1

1

a

F=A-1+Co

1

1

1

F=A+Co

1

a
a

a

F=A+F+Co

1

F = A or F

1

a

F=A+F+Co

1

a
a
a
a

1

1

F=A+F+Co

1

1

a

F=F+B+Co

1

1

a
a

1

F = Aor B

1

1

1

a

F=F+B+Co

1

1

1

1

F=F+B+Co

1

a
a
a
a

a
a

a

F = Axor B

1

F = A and B

1

a

F = A and B

1

1

F = A xnor B

1

a

F = A xor F

1

a
a

1

F = A and F

1

1

a

F = A and F

1

a
a
a
a
a
a
a
a

1

1

1

F=aIl1's+Co

1

1

a
a

F=B+Co

1

1

F = A and B

1

1

1

a

F=B+Co

1

1

a
a
a
a

a

1

1

1

F=B-1+Co

1

1

1

a

F=F+Co

1

1

1

a
a

1

F = Aor B

1

1

1

1

a

F=F-1 +Co

1

1

1

1

1

F=F+Co

1
1
1
1
1
1

1
1

2525 tbl 06

5.7

5

1DT7381 , 1DT7383

16-BIT CMOS CASCADABLE ALU

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)

CAPACITANCE

Symbol

Rating

Com'l.

Mil.

Unit

VTERM

Terminal Voltage
with Respect
to Ground

-0.5 to
Vee + 0.5

-0.5 to
Vee + 0.5

V

Vee

Power Supply
Voltage

TA

Operating
Temperature

TBIAS

-0.5 to +7.0 -0.5 to +7.0

o to +70

°C

Temperature
Under Bias

-55 to +125 -65 to +135

°C

TSTG

Storage
Temperature

-55 to +125 -65 to +150

°C

PT

Power Dissipation

1.0

1.0

W

lOUT

DC Output Current

50

50

rnA

= +2S o C, f = 1.0MHz)

Parameter(1)

Symbol

Conditions

Unit

Typ.

CIN

Input Capacitance

VIN = OV

10

pF

COUT

Output Capacitance

VOUT = OV

12

pF

NOTE:
25251b109
1. This parameter is sampled at initial characterization and is not production
tested.

V

-55 to +125

(TA

NOTE:
25251b107
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. Under no
circumstances should an input of an 1/0 Pin be greater than Vce + O.SV.

DC ELECTRICAL CHARACTERISTICS
Commercial: TA

= O°C to +70°C, Vec = S.OV ± 5%; Military:

TA = -55°C to +12S o C, vcc

= S.OV ± 10%
Min.

Typ.(2)

Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

V

VIL

Input LOW Level

Guaranteed Logic LOW Level

0.8

V

IIH

Input HIGH Current

Vee = Max., VIN

= 2.7V

-

10

~A

ilL

Input LOW Current

Vee = Max., VIN = 0.5V

-

-10

~A

108(3)

Short Circuit Current

Vee = Max., VOUT = GND

-

-100

rnA

loz

Off State (High Impedance)

Vee = Max.

-0.1

-20

~A

-0.1

20

Symbol

Test Conditions(1)

Parameter

Output HIGH Voltage

Vee = Min.
VIN

VOL

Output LOW Voltage

-

10H =-4mA

2.4

-

-

V

IOL = 4mA MIL.

-

-

0.5

V

= VIH or VIL

Vee = Min.
VIN

Vo= 2.7V

Vo= 0.5V

Output Current
VOH

-20

= VIH or VIL

10L = 8mA COM'L.

NOTES:
1. For conditions shown as Max. or Min .. use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = S.OV, +2SoC ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

S.7

25251b108

6

II

IDT7381, 1DT7383
16·BIT CMOS CASCADABLE ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Commercial: TA
VLC = 0.2V; VHC
Symbol
Iccoc
ICCQT(3)

ICCD1

= O°C to +70°C, VCC = 5.0V ± 5%; Military:
= Vcc =-0.2V

TA

= ·55°C to +125°C, Vcc = 5.0V ± 10%

Test Condltlons(l)

Parameter

COM'L.

10

35

MIL.

-

10

55

COM'L.

-

30

60

MIL.

-

30

80

COM'L.

= 3.4V
Vcc = Max.

MIL.

Vcc = Max.
Outputs Disabled
OE = HIGH
fcp = 20MHz
50% Duty Cycle
VIN ~ VHC; VIN s VLC

15
45

Vcc = Max.

TIL Inputs HIGH

Dynamic Power Supply Current

rnA

2

55

Quiescent Power Supply Current

Dynamic Power Supply Current

Unit

10

15

VIN

VIN

Max.

2

15

TIL Inputs HIGH

COM'L.

= VLC or VHC

Typ.(2)

-

Vcc = Max.

Outputs Disabled
OE = HIGH
fcp = 10MHz
50% Duty Cycle
VIN ~ VHC; VIN s VLC
ICCD2

Min.

Quiescent Power Supply Current

MIL.

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, +25°C ambient.
3. Per TIL driven input (V IN = 3.4V); all other inputs at Vce or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ie = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + IceD (fcPf2 + fiNi)
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

5.7

rnA
rnA

rnA

2525 tbl10

7

IDT7381, 1DT7383
16-BIT CMOS CASCADABLE ALU

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

COMMERCIAL (Vee = 5V ± 5%, TA = ooe to +70°C)

AC ELECTRICAL CHARACTERISTICS Maximum Combinational Propagation Delays

From Input
FTAB

F0-15 ]5, G, N Z,OVF

11

20

20
14

eo

F0-15 ]5, G, N Z,OVF

20
14

13

18

ICH, RSo, RS1

C16

F0-15 ]5,

G, N

Z,OVF

C16

Unit

26
16
22

22
16
22

20

22

26
16
22

22
16
22

33
28
28

18

25

22

22

30
20
28

28
20
28

ns
ns
ns

22

28

30
20
28

28
20
28

ns
ns
ns

24

30

28

28

20
28

20
28

ns
ns
ns
ns

30
20
28

28
20

ns
ns

28
28

=0, FTF =1

elK

Co
ICH, RSo, RS1 (1)
FTAB

C16

=0, FTF =0

elK

FTAB

IDT7381L30
IDT7383L30

IDT7381L25
IDT7383L25

IDT7381L20
I DT7383L20

20
18
20

,?§:;::y

20

:;::~:t20

18

;:::::

19.;:::::~~{ ::: 20

Ao-A15,80-815

lfm/"
::f:t3$

ICH, RSo, RS1 (1)

28

19

14
20

14
18

20
14
20

17
14
18

22

16
22

16
22

25
16
22

22
16
22

.::~~: i~~~{::~::~~

FTAB = 1, FTF = 1

ICH, RSo, RS1 (1)

22

13

::::::::::'" i=-

Co

Co

17

"':':::::

11

Ao-A15, 80-815

27
22
22

:t,:,;,;;:t,·

= 1, FTF = 0

elK

20
14
18

':~'",:i!~;

20
18
20

.:.::::

:~t:·

16
18

26
22
22

18
22

24

32
28
28

28

Maximum Combinational Propagation Delays
IDT7381L55
IDT7383L55

IDT7381L40
I DT7383L40
F0-15

]5,G, N

Z,OVF

C16

Unit

32

38

-

-

53
34
42

36
22
42

ns
ns
ns

42

53
34
42

36
22
42

ns
ns
ns

F0-15

]5,G, N

Z,OVF

C16

elK

26

30

Co

-

-

44
28
34

32
20
35

-

42

32
20
35

56
37
55

38

From Input
FTAB

=0, FTF =0

ICH, RSo, RS1
FTAB

32

=0, FTF =1
46
30
40

32

44
28
34

Ao-A15, 80-815

-

30

40

32

-

36

46

37

elK

26

-

-

-

32

-

-

Co

-

-

ICH, RSo. RS1 (1)

-

32

28
34

20
35

-

-

34
42

22
42

ns
ns
ns
ns

40
30
40

30

40
28
34

32
20
35

55
37
55

46
34
42

37
22
42

ns
ns
ns

eLK

Co
ICH, RSo. RS1 (1)
FTAB

FTAB

30

-

-

=1, FTF =0

42

=1, FTF =1

Ao-A15,80-815

Co

10-4, RSo. RS1 (1)

32

36

42

25251b112

5.7

8

1DT7381 , 1DT7383
16-BIT CMOS CASCADABLE ALU

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS -

COMMERCIAL (Vcc = 5V ± 5%, TA = aoc to +70°C) - (Cont'd.)

Minimum Set-up and Hold Times Relative to Clock (CLK)
IDT7381L20
IDT7383L20
Input

Set-up

IDT7381L25
IDT7383L25

IDT7381L30
IDT7383L30

IDT7381L40
I DT7383L40

IDT7381L55
IDT7383L55

Hold

Set-up

Hold

Set-up

Hold

Set-up

Hold

Set-up

Hold

Unit

~:::.

6
16
24
6

0
0
0
0

6
16
29
6

0
0
0

6
16
32
6

0
0

8
21
44
8

0
0

ns·

0

ns

0

ns

0

25
16
29
6

0

28
16
32
6

0

35
21
44
8

0
0
0

ns

FTAB = 0, FTF = X
Ao-A15, 80-815
Co (2)

10--4, ASo, ASl (1) (2)
ENA,ENB,ENF

5
12
15
5

........

:(~h.

..::{})
1:::::::::"'0

Ao-A15, 80-815

1~. :::::':1~

0

Co

1¢.:::,;/·

0

.::J~:::

0

.:' ..
.:::'5

ENF

0

ns

::;)::i:;:·

FTAB = 1, FTF =0

10--4, ASo, ASl (1)

0

0

0

16
16
24
6

0
0

0

0
0
0

0
0
0

ns
ns

0

ns
25251b113

Minimum Clock Cycle Times and Pulse Widths
Parameter

1DT7381L20
IDT7383L20
:::'.
5
5 Art:::·
18:. :::t:::::::

Clock LOW Time
Clock HIGH Time
Clock Period

.... ;.:.:....

IDT7381L25
IDT7383L25

IDT7381L30
I DT7383L30

IDT7381L40
IDT7383L40

IDT7381L55
IDT7383L55

6
6
20

8
8
25

10
10
34

14
14
43

Unit
ns
ns
ns
25251b114

.•.•...:....

Maximum Output Enable/Dlsa9@trlmes
Parameter
Enable Time
Disable Time

IDmi11L20
IQIT383L20

::{}:::/. 8

AI::

8

IDT7381L25
IDT7383L25

IDT7381L30
IDT7383L30

IDT7381L40
IDT7383L40

IDT7381L55
1DT7383L55

10
10

15
15

18
18

20
20

Unit
ns
ns
2525lbl15

NOTES:

1. For 1DT7381 , pins 10 -12, RSo, RS1 apply. For 1017383, pins 10 -14 apply.
2. Only for FTF =o.

5.7

9

1017381, 10T7383
16-BIT CMOS CASCAOABLE ALU

MIUTARY ANO COMMERCIAL TEMPERATURE RANGES

MILITARY (Vcc = SV ± 10%, TA = -55°C to + 125°C)

AC ELECTRICAL CHARACTERISTICS Maximum Combinational Propagation Delays
IDT7381L25
IDT7383L25
From Input

FG-15

P, G, N

14

24

Z,OVF

IDT7381L35
IDT7383L35

IDT7381L30
IDT7383L30
C16

F0-15

P,G, N

Z,OVF

C16

FG-15

P, G, N

Z,OVF

C16

Unit

26

28

34
22
28

28
22
28

27

32

45
30
34

32
23
34

ns
ns
ns

28

34
22
28

28
22
28

45
30
40

34

40
30
34

32
23
34

ns
ns
ns

28

28

28

30

35

32

34

30
34

23
34

ns
ns
ns
ns

30
30
34

32
23
34

ns
ns
ns

FTAB = 0, FTF = 0

ClK
Co
10-4, RSo, RSl (1)

24
24
18 .:~ ::. 18
24::::::::: :::::t22

22

ClK
Co
10-4, RSo, RSl (1)

28

34

/::r;~::::::::::·

FTAB = 0, FTF = 1

?4t:::;:· 24

24

25
21
25

;.:::::A~:?

22

.::::::::U~~

18
22

34
26
30

28

32

".-.:::;:;:;:::-

FTAB = 1, FTF = 0

20t11 ::::::; 25

Arr-A15, Brr-B15

ClK
Co
10-4, RSo, RSl (1)
FTAB = 1, FTF = 1
Arr-A15, Brr-B15

Co
10-4, RSo, RSl (1)

_

22

:::;:::::::::::-:...:.;;:;;

14

27

26

:\tt:::~~t
".:.;

.::::'-.

·::::::/2'::

18
24

18
22

25
18
24

22
18
22

28

22
28

22
28

28
22
28

28
22
28

Al::::~jt:::;;'

2§.:f::: : 22
....;.;:::::
21
25
22

30
26
30

28
28

40
30
40

30
34

252511:>116

Maximum Combinational Propagation Delays
IDT7381L65
IDT7383L65

IDT7381L45
I DT7383L45
FG-15

JS,G, N

Z,OVF

C16

ClK

28

34

Co
10-4, RSo, RSl (1)

-

-

50
32
38

34
23
38

-

34
23
38

From Input

FG-15

JS,G,N

Z,OVF

C16

Unit

37

44

-

48

63
42
48

45
25
48

ns
ns
ns

68
42
66

44
48

63
42
48

45
25
48

ns
ns
ns

FTAB = 0, FTF = 0

38

FTAB = 0, FTF = 1

56
32
46

34
38

50
32
38

Arr-A15, Bo-B15

-

32

46

36

-

44

56

44

ClK
Co
10-4, RSo, RSl (1)

28

-

-

-

37

-

-

-

38

32
38

23
38

-

-

42
48

25
48

ns
ns
ns
ns

46
32
38

36
23
38

65
42
66

56
42
48

44
25
48

ns
ns
ns

ClK
Co
10-4, RSo, RSl (1)

-

FTAB=1,FTF=0

48

FTAB = 1, FTF = 1
Arr-A15, Bo-B15

Co
10-4, RSo, RSl (1)

45
32
46

32

38

44

48

252511:>117

5.7

10

II

IDT7381, 1DT7383
16-BIT CMOS CASCADABLE ALU

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS -

MILITARY

(VCC

= 5V ± 10%, TA = -55°C to +125°C) - (Cont'd)

Minimum Set-up and Hold Times Relative to Clock (CLK)
IDT7381L25
I DT7383L25
Input
FTAB

Hold

Set-up

IDT7381L30
IDT7383L30
Set-up

Hold

IDT7381L35
I DT7383L35
Set-up

Hold

IDT7381L45
IDT7383L45
Set-up

Hold

IDT7381L65
IDT7383L65
Set-up

Hold

Unit

= 0, FTF = X

Ao-A15, 80-815
Co (2)

7

Jt.

8

0

8

0

8

0

10

0

ns

14

.l4:t

18

0

19

0

20

0

25

0

ns

10-4, RSo, RSl (1) (2)

19

30

0

32

0

36

0

50

0

ns

ENA,

affi, ENF
FTAB = 1, FTF = 0

7

0

8

0

8

0

8

0

10

0

ns

Ao-A15, 80-815

1.(::::::/

0

27

0

30

0

33

0

43

0

ns

Co

~4:i'

0

18

0

19

0

20

0

25

0

ns

0

30

0

34

0

36

0

50

0

ns

0

8

0

8

0

8

0

10

0

. :'{I:6
:::.::.:.:

.:;;; ~::::;::

.;~~~~t}

10-4, RSo, RSl (1)

.:};f:g:

ENF

'::::::::::7

ns
25251b118

Minimum Clock Cycle Times and Pulse Widths
IDT7381L25
I DT7383L25

IDT7381L30
I DT7383L30

IDT7381L35
IDT7383L35

IDT7381L45
IDT7383L45

IDT7381L65
I DT7383L65

Unit

Clock LOW Time

8

12

13

15

20

ns

Clock HIGH Time

8 .l~t:::::

12

13

15

20

ns

26

30

38

52

Parameter

Clock Period

...:\:...

20.::(~:r:·

.. :.;.;.:

ns
25251b1 19

Maximum Output Enable/Dlsa~l.t:'rlmes
1DT7381L30
1DT7383L30

IDT7381L35
IDT7383L35

IDT7381L45
IDT7383L45

1DT7381L65
IDT7383L65

Unit

Enable Time

18

19

20

22

ns

Disable Time

18

19

20

22

Parameter

IDU381L25
IQ;P383L25

NOTES:
1. For IDT7381. pins 10 -12. RSo. RS1 apply. For I0T7383, pins 10 -14 apply.
2. Only for FTF = O.

5.7

ns
25251b120

11

IOT7381, 1DT7383
16·BIT CMOS CASCAOABLE ALU

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

WAVEFORMS FOR FTAB

=0, FTF =X
T2

Tl

ClK

AO-15
80-15

---/

"

DATAl:

/
Set-up

Hold

(

"

"-

Co

10-4

RSO-l

DATAl

OE

II

Disable
Enable:
FO-15
(FTF = 0)
Pro

.3:

Prop. 2
Pro.1
Enable:
FO-15
(FTF= 1)
Prop. 2

Result:

P,G

: Result

Z,OVF

CIG

2525 drw07
Prop. 1: Propagation delay with respect to the ClK.
Prop. 2: Propagation delay with respect to 10-4, RS0-2.
Prop. 3: Propagation delay with respect to Co.

5.7

12

IDT7381, 1017383
16-BIT CMOS CASCADABlE AlU

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

WAVEFORMS FOR FTAB = 1, FTF = X
T2

T1

,,'------'/

ClK

(FTF = 0)

Set-up :

AO-15
Bo-15

,,'------'/

Hold

DATA 1

Set-up
DATA 1

Co

DATA 2

DATA 3

Set-up

10-4
RSO-l

ENF

DATA 1

DATA 2

DATA 3

DATA 1

FO-15
(FTF = 0)

FO-15
(FTF= 1)

fl,G

Z,OVF

Result

C16

2525 drw 08
Prop. 1:
Prop. 2:
Prop. 3:
Prop. 4:

Propagation
Propagation
Propagation
Propagation

delay with
delay with
delay with
delay with

respect to
respect to
respect to
respect to

the ClK.
10-4, RSO-2.
Co.
A, B.

5.7

13

IDT7381, 1OT7383
16-BIT CMOS CASCADABLE ALU

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PROPAGATION DELAY CALCULATIONS FOR TWO IDT7381n383s
To Output
From Input
FTAB
ClK

= 0, FTF =

°

As in 16-bit case

Co
10-4, RSO-l

....
....
· ...
... .

(1)

AO-15,80-15
ENA, ENB,ENF
FTAB
ClK

To Set PUT Time
Flags (2)

FO-15

Relative to Clock (ClK)

(Clk ~ C16) + (Co ~ flag)

.0

(Co ~ C16) + (Co ~ flag)

(Co ~ C16) + (Co set-up time)

....
....

(10-4, RSO-l ~ C16) + (Co ~ flag)

(10-4, RSO-l -) C16) + (Co set-up time)
As in 16-bit case
As in 16-bit case

••

= 0, FTF = 1
(Clk ~ C16) + (Co ~ FO-15)

(Clk ~ C16) + (Co ~ flag)

....

Co
10-4, RSO-l (1)

(Co ~ C16) + (Co ~ FO-15)

(Co ~ C16) + (Co ~ flag)

(Co ~ C16) + (Co set-up time)

(10-4, RSO-l ~ C16) + (Co ~ FO-15)

(10-4, RSO-l ~ C16) + (Co ~ flag)

AO-15,80-15
ENA, ENB,ENF

· ...
· ...

....
....

(10-4, RSO-l -) C16) + (Co set-up time)
As in 16-bit case
As in 16-bit case

As in 16-bit case

....

FTAB = 1, FTF =
ClK
Co
10-4, RSo-l (1)

°

....
....

0

AO-15, BO-15

· ...

ENA, EN8,ENF

....

FTAB = 0, FTF = 1
ClK
Co
10-4, RSo-l (1)

Don't care condition
(Co ~ C16) + (Co ~ FO-15)

Don't care condition
(Co ~ C16) + (Co ~ flag)

(10-4, RSO-l ~ C16) + (Co ~ F0-1S)

(10-4, RSO-l ~ C16) + (Co ~ flag)

AO-15,80-15

(A0-1S, 80-15 ~ C16) + (Co ~ FO-15)

ENA, ENB,ENF

....

•••

+ (Co~flag)
(Co ~ C16) + (Co set-up time)
(10-4, RSO-l ~ C16) + (Co ~ flag)
(10-4, RSO-l ~ C16) + (Co set-up time)
(A0-1S, B0-1S ~ C16) + (Co ~ flag) As in 16-bit case

(CO~C16)

o

As in 16-bit case

•••

(A0-1S, B0-1S ~ C16) + (Co ~ flag)

. ...

NOTES:
1. For 1OT7381 , pins 10-2, RSo.-:2apply. For IDT7383, pins 10-4 apply.
2. Flags are P, G, OVF, Z, C1S for IDT7381. Flags are N, OVF, Z C1S for IDT7383.

5.7

....
....
....
.
....
'"

25251b122

14

•

IDT7381, 1017383
16-BIT CMOS CASCADABLE ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CASCADING THE IDT7381/3
Some applications require 32-bit or wider input operands.
Cascading is the hardware solution. It provides a high speed
alternative in handling more than 16-bit wide operands.
This section is divided in three parts:
1. Cascading the IDT7381
2. Cascading the IDT7383
3. Time delay considerations

3. Time Delay Considerations
Once cascading has taken place, time delays may become
critical in high performance systems. Our main interest here
is focused on "propagation delays", i.e. calculating the time
required for an input signal to propagate through several
cascaded devices up to a specific output in another device
within the cascaded system.

1. Cascading the 1DT7381
Cascading to 32-bit wide operands takes only two IDT7381 s
and no external hardware. However, cascading to data widths
greater than 32-bit can be done in two ways: without external
hardware (slow method) or by using a carry look ahead
generator like the IDT39C02A or the FCT182 (fast method).

Propagation Delay
The propagation delay for two devices between the input
and output of interest (input to output delay) is done as follows:
1. Calculate delay between the input and C16 in the first
device.
2. Calculate delay between Co and the output in the
second device.
3. Add both results.
The following table is an example on how to build a
propagation delay table for all inputs in a 32-bit IDT7381/3
cascaded system.
Propagation delay calculations can be extended to
n-cascaded devices as the sum of the delays in all devices
between the input and output of interest. That is:

a) Cascading the IDT7381 without a carry-look-ahead
generator: (Figures 2 and 3)
1. Connect the C16 output of the least significant device
into the Co input of the next most significant device.
2. Common lines to all devices are: RSO-1, 10-2, Clk,
FTF, FTAB, ENA, ENB, ENF.
3. Take OVF, C16, P, Gofthe most significant device as
valid.
4. The system's zero flag (Z) is obtained by ANDing all
zero flag results.
b) Cascading three or more I DT7381 s with carry-lookahead (CLA) generator: (Figure 4)
1. Connect the P and G outputs of each device to the
CLA generator's corresponding inputs.
2. Take the CLA generator outputs into the Co inputs of
each device (except for the least significant one).
3. Common lines to all devices are: RSO-1, 10-2, Clk,
FTF, FTAB, ENA, ENB, ENF.
4. Take OVF, C16, P, G of the most significant device as
valid.
5. Carry-in to the system should be connected to the Co
input of the least significant device and also to the
CLA generator.
2. Cascading the IDT7383
(Figures 5 and 6)
1. Connect the C16 output of the least significant device
into the Co input of the next most significant device.
2. Common lines to all devices are: 10-4, Clk, FTF,
FTAB, ENA, ENB, ENF.
3. Take OVF, C16, N of the most significant device as
valid.
4. The system's zero flag (Z) is obtained by ANDing all
zero flag results.

5.7

(Input)l

~

(C16)1 = t1

(CO)i ~ (C16)i = ti
(CO)i + 1 ~ (C16)i + 1 = ti + 1
(CO)n ~(Output)n = tn
Where the subscript i denotes the device number and the
arrow (~) represents the delay in between. Notice that i + 1
is the immediate upper device from device i. Adding the
delays ti we get:
Propagation delay = t1 + t2 + ... + ti + ti + 1 + ... + tn
Total Delay
As seen from Figure 11, the propagation delay is within the
IDT7381/3 devices only. A complete analysis should also
include the delay associated with the transmission line Li
(which depends on the line length and its impedance). This
line delay should then be added to the propagation delay to
obtain the total delay for the cascaded system:
Total delay = Propagation delay + Transmission line delay

15

ID17381,IDT7383
16·BIT CMOS CASCADABLE ALU

MIUTARV AND COMMERCIAL TEMPERATURE RANGES

CMOS TESTING CONSIDERATIONS
There are certain testing considerations which must be
taken into account when testing high·speed CMOS devices in
an automatic environment. These are:
1) Proper decoupling at the test head is necessary.
Placement of the capacitor set and the value of capacitors
used is critical in reducing the potential erroneous failures
resulting from large Vee current changes. Capacitor lead
length must be short and as close to the OUT power pins as
possible.
2) All input pins should be connected to a voltage potential
during testing. If left floating, the device may begin to
oscillate causing improper device operation and possible
latchup.

3) Definition of input levels is very important. Since many
inputs may change coincidentally, significant noise at the
device pins may cause the VIL and VIH levels not to be met
until the noise has settled. To allow for this testing/board
induced noise, lOT recommends using VIL:5 OV and VIH ~
3V for AC tests.
4) Device grounding is extremely important for proper device
testing. The use of multi·layer performance boards with
radial decoupling between power and ground planes is
required. The ground plane must be sustained from the
performance board to the OUT interface board. All unused
interconnect pins must be properly connected to the grou nd
pin. Heavy gauge stranded wire should be used for power
wiring and twisted pairs are recommended to minimize
inductance.

TEST LOAD CIRCUIT

II
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance
RL = Termination resistance: should be equal to ZOUT of the Pulse Generator
Figure 1. AC Test Load Circuit

AC TEST CONDITIONS
Input Pulse Levels

GND to3.0V

Test

Switch

Input Rise/Fall Times

WIns

Open Drain

Closed

Input Timing Reference Levels

1.5V

Disable Low

Output Reference Levels

1.5V

Enable Low

See Figure 1

All other Outputs

Output Load

Open
2525 tbl23

2525 tbl21

5.7

16

10T7381, 1017383
16-BIT CMOS CASCAOABLE ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

A16-31

G-.------I
p-.------I
C16
OVF

B16-31

A0-15

B0-15

11 RS0-1
IDT7381

IDT7381

Clk, I 0-2, ENA, ENB
ENF, FTF, FTAB

-.------1

...................................~ C16

.........................-

Co~

Z

Z

co~

CIN

LSD

F0-15

F16-31

2525 drw

10

Figure 2. Cascading Two 1DT7381s to 32 Bits

A32-47

B32-47

A16-31

816-31

AO-15

80-15
RSO-1

Clk,

G--...............--I
p--...............--I
C16
OVF~----f

.........................-I

CO~

10-2,

ENA, ENS
ENF, FTF,
FTA8
CIN

1017381

CO~""'''''''''''''''''''''-I

Z
F16-31

F32-47

FO-15

2525 drw 11

Figure 3. Cascading Three 1DT7381s to 48 Bits Wide
without a Carry-Iookahead Generator

A32-47

G

832-47

A16-31

816-31

AO-15

J

J

J

1 1
ID17381

P

1017381

~

Z ~Co

Z

MSO

-

t

-

-

P
r--

r

G

P
roo-

z

Co

04-

I

F1~31

r

RSO-1

~

~

F32-47

Cn+y

J

1017381

;L-----

"\r

C16

OVF

80-15

~

/

Clk, 10-2,
ENA, ENS
ENF, FTF,
FTA8

G

z

Co

CIN

LSD

J

FO-15

P1 G1

Cn+x

IDT39C02A Lookahead Generator

Po Go

25 25 drw 12

Cn

Figure 4. Cascading Three 1DT7381s to 48 Bits Wide
with a Carry-Iookahead Generator

5.7

17

1017381, 1OT7383
16-BIT CMOS CASCAOABLE ALU

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

A16-31

B16-31

A0-15

11

IDTI383

IDTI383

N1------f
C16 .....- - - - - t
OVF1-----f

B0-15

Co~-------~

Clk. I 0-4. ENA. ENB
ENF. FTF. FTAB
Co ....- - - - -

CIN

LSD

Z

2525 drw 13

F0-15

F16-31

Figure 5. Cascading Two 1OT7383s to 32 Bits

A32-47

N ....- - - - f

B32-47

A16-31

B16-31

AO-15

BO-15
Clk. 10-4.
ENA. ENB
ENF. FTF.
FTAB

IDTI383

C1S ....- - - - f

OVF ....- - - - f

Co14-------t

Co 1 + - - - - - - - - 1

Co ....- - - - - -

CIN

Z
F32-47

FO-15

F16-31

2525 drw 14

Figure 6. Cascading Three 1OT7383s to 48 Bits

5.7

18

•

IDT7381, 1017383
16-BIT CMOS CASCADABLE ALU

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

.A-.----+-.- ClK

Fl6-31

Figure 7. 32-Bit Configuration for FTAB

=0, FTF =°

Fo-15

14-----+-;..- ClK

FO-15

Fl6-31

Figure 8. 32-Blt Configuration for FTAB

5.7

2525 drw 16

= 0, FTF = 1

19

IDT7381,IDT7383
16-BIT CMOS CASCADABLE ALU

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

A16-31

816-31

A0-15

80-15

16

16

16

16
.----.......-CLK

F16-31

2525drw 17

F0-15

Figure 9. 32-BII Configuration for FTAB

=1, FTF =0

816-31

I

80-15

16

16

16
F16-31

2525 drw 18

F0-15

Figure 10. 32-Blt Configuration for FTAB

5.7

= 1, FTF = 1

20

1DT7381 , 1017383
16·81T CMOS CASCADABLE ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Do

INPUT

01

On
OUTPUT

-t1-

~---I

-t2-

-tn-

2525 drw 19

Figure 11. Propagation Delay

= 11

+ 12 + ••• + In N·Cascaded Devices

ORDERING INFORMATION
lOT

XXXX
Device Type

__
X_

--.2QL

__X_ _

Power

Speed

Package

Ray
x

Process/
Temperature

I;

1

Blank
B

Commercial (O°C to + 70°C)
Military (- 55°C to + 125°C)
Compliant to MIL-STD-883, Class B

J
G

Plastic Leaded Chip Carrier
Pin Grid Array

25 0 }
2
30
Commercial
40
55
I

30
25}
35
Military
45
65

L

Low Power

7381
7383

16-Bit ALU
16-Bit ALU With 32 Instructions

2525 Orw 20

5.7

21

(;5
Integra.ted Device Technology, Inc.

IDTI3200
IDT73201

16-BIT CMOS
MULTILEVEL
PIPELINE REGISTERS

FEATURES:
• IDT73200: Eight 16-bit high-speed pipeline registers
• IDT73201: Seven 16-bit high-speed pipeline registers
plus a direct feed-through path
• 12ns to 20ns access time
• Programmable multilevel register configurations
• Powerful instruction set: transfer, hold, load directly
• Functionally replaces four Am29520s
• Read/Write buffer for 32-bit RISC/CISC microprocessors
• Applications as temporary address storage or
programmable pipeline registers for DSP products
• Coefficient storage for FIR filters
• Three-state outputs
• TTL-compatible
• Produced with advanced submicron CEMOSTM
high-performance technology
• Available in 48-pin plastic and ceramic DIP and 52-pin
surface mount PLCC and LCC
• Military product compliant to MIL-STD-883, Class B

DESCRIPTION:
The IDT73200 and IDT73201 are mutilevel pipeline
registers. With IDT's high-performance CEMOSTM

technology, the IDT73200 and IDT73201 have access times
of 12ns.
The IDT73200 contains eight 16-bit registers which can be
configured as one 8-level, two 4-level , four 2-level or eight
1-level pipeline registers.
The I DT73201 contains seven 16-bit registers and a direct
feed-through path. The seven registers can be configured as
one 7-level, a 4-level plus a 3-level, three 2-level or seven
1-level pipeline registers.
An eight-to-one output multiplexer allows data to be read
from anyone of the registers or from the feed-through path on
the IDT73201. Three input control pins (SELo-SEL2) select
which of the multiplexer inputs are directed to the output
(Yo-Y15).
These pipeline registers are ideal for high throughput,
vector-oriented operations such as those in digital signal
processing (DSP). The IDT73200 and IDT73201 can also be
used as quick access scratch pad registers for general
purpose computing.
The two pipeline registers are packaged in 48-pin plastic
and ceramic DIPs for through-hole designs as well as 52-pin
PLCC and LCC for surface mount designs. Military grade
product is manufactured in compliance with the latest revision
of MIL-STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAMS
00-015

00-D15

16

16

CLK~r------4--------~~--~

OE------1~

10-115

CEN

CLK~r-----~---------r~--~

OE-----------.....

GNO
Vee

10-115

CEN

YO-Y15

POWER
SUPPLY

l-- GNO
I-- Vee

YO-Y15
2562 d!w 02

2562 dIw 01

IDT73201

IDT73200
eEMOS is a trademark of Integrated Device Technology Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
ICt990 Integrated Device Technology, Inc.

5.8

JUNE 1990
DSC·9036/·

1

II

IOT73200, IDT73201
16-81T CMOS MULTILEVEL PIPEUNE REGISTERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
11

Z

12
13
Yo
Yl
Y2
Y3
GND
Y4
Ys
Y6
Y7
Vee
GND
Ys
V9
Yl0
Y11
GND
Y12
Y13
Y14
YIS
OE
ClK

10
CEN
Do
Dl
D2
D3
D4
Ds
D6
D7
GND
Vee
Ds
D9
Dl0
D11
D12
D13
D14
D1S
SEl2
SEll
SElo

INDEX

ON~OW

O~NC')

I
ZClClClO~-=.£:!.£:!>->L..JL.-.IL..JL....JL....JL....JI

7 6 5 4 3 2

03
D4
D5
Os
07
GNO
Vee

]s
J9
] 10
J 11
] 12
J13
] 14

>->-

IL....JL..J L......JL....J L......JL...J

I I
LJ

52 51 50 49 4S 47
46[
45 [
44 [
43 [
42[
41 [
40 [

1

J52 - 1
&

l52 -1

NC
GND
V4
Y5
Y6
Y7
Vee

Os
D9

] 15

39 [

GNO

] 16

3S[

Vs

Dl0

]17
]16

37[

V9

D11

3S[

Yl0

D12

] 19

35[

NC

]20

V11
GNO

34[

~~~~~~~~~~;!.!,~~
~ ~~~..:i.3I~IW~ ~ ~ ~o

Cl Cl Cl ~ ~ ~ c:3 0>- >- >- >- Z

2562 drw 03

PLCC/LCC
TOP VIEW

DIP
TOP VIEW

PIN DESCRIPTIONS
1/0

Pin Name
Do - D15

I

Yo - V15

0

Description
Sixteen-bit data input port.
Sixteen-bit data output port.

10 -13

I

Four control pins to select the register operation performed.

SElo - SEl2

I

Three control pins to select the register appearing at the output.

ClK

I

Clock input.

CEN

I

Clock enable control pin. When this pin is low. the instruction 10-13 is performed on the registers.
When high. no register operation occurs.

OE

I

Output enable control pin. When this pin is high. the output port V is in a high impedance state.
When low. the output port V is active.

Vee

Power supply pin. 5V.

GND

Ground pins.

av.
256211>101

IDT73200 OUTPUT SELECTION

IDT73201 OUTPUT SELECTION

Sf::L2

SELl

SELo

Y Output

SEL2

SELl

SELo

Y Output

a
a
a
a

a
a

a

A ~ VO-V15

a

A~ VO-V15

1

B~

a
a

1

B ~ VO-V15

1

a

c ~ Vo- V15

1

a

c ~ VO-V15

1

1

D ~ Vo- V15

a
a
a
a

1

1

D ~ VO-V15

1

a
a

a

E ~ Vo- V15

1

a

a

E ~ VO-V15

1

F ~ Vo- V15

1

0

1

F ~ VO-V15

1

1

a

G ~ Vo- V15

1

1

0

G ~ VO-V15

1

1

1

H ~ Vo- V15

1

1

1

Do - D15 ~ Vo - V15

1

Vo- V15

2562 11>1 02

2562 11>1 03

5~

2

10173200, 10173201
16·81T CMOS MULTILEVEL PIPELINE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT73200 INSTRUCTION TABLE
Mnemonic

Function

Pipeline Levels

13

12

h

10

0

0

0

0

LOA

Do - 015 -) A

0

0

0

1

LOB

Do - 015 -) B

0

0

1

0

LDC

Do - 015 -) C

1

0

0

1

1

LDD

Do - 015 -) 0

1

0

1

0

0

LDE

Do - 015 -) E

1

0

1

0

1

LDF

Do - 015 -) F

0

1

1

0

LOG

Do - 015 -) G

1
1

1
1

0

1

1

1

LDH

Do - 015 -) H

1

1

0

0

0

LSHAH

Do - 015 -) A -) B -) C -) 0 -) E -) F -) G -) H

8

1

0

0

1

LSHAD

Do - 015 -) A -) B -) C -) 0

4

1

0

1

0

LSHEH

Do - 015 -) E -) F -) G -) H

4

1
1
1

0

1

1

LSHAB

Do - 015 -) A -) B

2

1
1

0

0

LSHCD

Do - 015 -) C -) 0

2

0

1

LSHEF

Do - 015 -) E -) F

2

1

1

1

0

LSHGH

Do - 015 -) G -) H

1

1

1

1

HOLD

Hold All Registers

2
2562 tbl 04

IDT73201 INSTRUCTION TABLE
13

12

h

10

0

0

0

0

LOA

Do - 015 -) A

0

0

0

1

LOB

Do - 015 -) B

1

0

0

1

0

LDC

Do - 015 -) C

1

0

0

1

1

LDD

Do - 015 -) 0

0

1

0

0

LDE

Do - 015 -) E

1
1

0

1

0

1

LDF

Do-D15-)F

1

0

1

1

0

LOG

Do - 015 -) G

0

1

1

1

HOLD

Hold All Registers

1

0

0

0

LSHAG

Do - 015 -) A -) B -) C -) 0 -) E -) F -) G

1
7

1

0

0

1

LSHAD

Do - 015 -) A -) B -) C -) 0

4

1

0

1

0

LSHEG

Do - 015 -) E -) F -) G

3

1

0

1

1

LSHAB

Do-D15-)A-)B

2

1

1

0

0

LSHCD

Do - 015 -) C -) 0

2

1

1

0

1

LSHEF

Do - 015 -) E -) F

2

1

1
1

1

0

LOG

Do - 015 -) G

1

1

HOLD

Hold All Registers

1

Mnemonic

Function

Pipeline Levels

II

1

1

2562 tbl 05

5.8

3

IDT73200, IDT73201
16-BIT CMOS MULTILEVEL PIPELINE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT73201 PIPELINE CONFIGURATIONS

IDT73200 PIPELINE CONFIGURATIONS
Eight 1-Level

t
t
A
II E
t
t
B
II F
t
t
C
II G
t
t
D

Four 2-Level

1=0

1=4

1=1

1=5

1=2

1=6

1=3

1=7

II

I
I
I

H

Two 4-Level

I

Three 2-Level

Seven 1-Level

t 1=0

~~
: f":: f"':

I

F

t

1= 6, 14

G
D

One a-Level

I

I

One 4-Level, One 3-Level

One 7 -Level

~
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vee

Rating
Power Supply
Voltage

VTERM

Terminal Voltage
with Respect
toGND

TA

CAPACITANCE

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to
Vee + 0.5

-0.5 to
Vee + 0.5

V

Operating
Temperature

o to +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +155

°C

lOUT

DC Output
Current

50

50

Symbol

(TA = +25°C. F = 1.0MHz)

Parameter(1)

CIN

Input Capacitance

COUT

Output Capacitance

Conditions

Typ_

Unit

VIN = OV

10

pF

VOUT = OV

12

pF

NOTE:
2562 tbl 07
1. This parameter is sampled at initial characterization and is not 100%
tested.

TEST CIRCUIT

mA

NOTE:
2562 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.

5.8

Test

Switch

tPLZ

Closed

tPZL

Closed

Open Drain

Closed

All Other Tests

Open

DEFINITIONS:
2562 tbl 10
CL = Load capacitance includes jig and probe capacitance.
RT = Termination should be equal to ZOUT of the pulse generator.
(Typically SOn)
VIN = OV to 3.0V
INPUT: tr = tf = 2.Sns (10% to 90%) unless otherwise specified

4

IDT73200, IDT73201
16-81T CMOS MULTILEVEL PIPELINE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS
Commercial:
Symbol

aoc to +70°C, 5V ± 5%; Military:

-55°C to +125°C, 5V ± 10%

Parameter

Min.

Test Condition

Max

Unit

VIH

High-Level Input Voltage

-

2.0

-

V

VIL

Low-Level Input Voltage

-

O.S

V

IIH

High Level Input Current

Vee = Max.

VI = Vee

-

10

IlA

ilL

Low-Level Input Current

Vee = Max.

VI = GND

-

-10

Il A

VOH

High-Level Output Voltage

Vee = Min.,
10H = -SmA(COM'L.), -6mA(MIL.)

2.4

-

V

VOL

Low-Level Output Voltage

Vee = Min.,
10L = 16mA(COM'L.), 12mA(MIL.)

-

0.4

V

-

-1.2

V

-

mA

VIK

Input Clamp Voltage

los

Short Circuit Output
Current(2)

Vee = Max., Va = GND
VI = Vee or GND

10zH

High Impedance Output
Current

Vee = Max.

VI = Vee

-

20

Il A

10ZL

Low Impedance Output
Current

Vee = Max.

VI= GND

-

-20

IlA

II = -1SmA

-20

NOTES:
1. For conditions shown as Min. or Max., use appropriate value based on temperature range.
2. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed 100 milliseconds.

2562 tbl 08

POWER SUPPLY CHARACTERISTICS
Symbol

Parameter
Quiescent Power Supply Current

Vee = Max.
VI = VLe or VHe

leeQT(3)

Quiescent Power Supply Current
Inputs HIGH

Vee = Max.
VI = 3.4V

leeD1(4)

Dynamic Power Supply Current

Vee = Max.
Outputs Disabled, OE = HIGH
fep = 1OMHz, 50% Duty Cycle
VI ~ VHe, VI ~ VLe
VCC = Max.
Outputs Disabled, OE = HIGH
fcp = 40MHz, 50% Duty Cycle
VI ~ VHC, VI ~ VLC

lecD1(4)

Dynamic Power Supply Current

Typ.(2)

Max.

Unit

-

2

10

mA

-

15

45

mA

COM'L.

-

10

30

mA

MIL.

-

10

40

COM'L.

-

10

60

MIL.

-

10

SO

Test Conditions(1)

leeoc

Min.

NOTES:
1. For conditions shown as Min. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading, not production tested.
3. This parameter is not directly testable but is derived for use in the total power supply calculation.
4. Ic = IOUIESCENT + IINPUTS + IDYNAMIC
Ic = Iccoc + (ICCOT X DH X NT) + Iceo
Iccoc = Quiescent Current
ICCOT = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for each TTL Input High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Charge moved by an input transition pair (HLH or LHL)
All currents are in milliamps and all frequencies are in megahertz.

5.8

mA

2562 tbl 09

5

•

1DT73200, IDT73201
16-BIT CMOS MULTILEVEL PIPELINE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
Commerical: TA = O°C to +70°C, Vcc = 5V +5%;
Military: TA = -55°C to +125°C, Vcc = 5V +10%
Commercial

73200L12
73201L12
Parameter
ClK to Yo-Y15 Propagation Delay
SElo-SEl2 to Yo-Y15 Propagation Delay
00-015 to ClK Set-up Time

Min.

Max.

Min.

Max.

-

12
12

-

3

4
2
5
2

15
15
-

00-015 to ClK Hold Time

1

-

10-13 to ClK Set-up Time

4

-

10-13 to ClK Hold Time

2

CEN to ClK Set-up Time

4
2

-

CEN to ClK Hold Time
OE Enable Time(1)
OE Disable Time(1)
ClK Pulse Width HIGH
ClK Pulse Width lOW
ClK Period
Data In to Data Out Flowthrough(2)

Military

73200L15
73201115

-

8

-

-

12
12

-

Max.

Min.

4
2

-

5
3

-

-

5
2
5
2

-

10

5
5
-

-

Max.

-

-

-

5
5

Min.

73200L20
73201L20

15
15

5
2

9

73200115
73201115

Unit

20
20

ns
ns
ns

-

ns

6

-

-

3

-

ns

-

6

ns

-

3

-

-

10

-

9

13
13

ns

9

-

-

5
5
-

-

6

-

ns

6

-

ns

15
-15

-

20
20

ns

-

-

15
15

-

NOTES:
1. Output Enable and Disable times measured to SOOmV change of output voltage level.
2. 73201 only.

ns

ns
ns

ns
2562 tbltt

AC TEST CONDITIONS
Input Pulse levels

GND to 4.0V

Input Rise/Fall Times

4ns

Input Timing Reference levels

1.5V
1.5V

Output Reference levels
Output load

See Figure 1
2562 tbl t2

Figure 1. AC Output Test Circuit

CMOS TESTING CONSIDERATIONS
There are certain testing considerations which must be
taken into account when testing high-speed CMOS devices in
an automatic environment. These are:
1) Proper decoupling at the test head is necessary. Placement of the capacitor set and the value of capacitors used
is critical in reducing the potential erroneous failures
resulting from large Vee current changes. Capacitor lead
length must be short and as close to the OUT power pins
as possible.
2) All input pins should be connected to a voltage potential
during testing. If left floating, the device may begin to
oscilliate causing improper device operation and possible
latchup.

5.8

3)

4)

Definition of input levels is very important. Since many
inputs may change COincidentally, significant noise at
the device pins may cause the VIL and VIH levels not to be
met until the noise has settled. To allow for this testing/
board induced noise, lOT recommends using VIL:::;OVand
VIH ~ 3V for AC tests.
Device grounding is extremely important for proper device
testing. The use of multi-layer performance boards with
radial decoupling between power and ground planes is
required. The ground plane must be sustained from the
performance board to the OUT interface board. All
unused interconnect pins must be properly connected to
the ground pin. Heavy gauge stranded wire should be
used for powerwiring and twisted pairs are recommended
to minimize inductance.

6

IDT73200, 1DT73201
16-81T CMOS MULTILEVEL PIPELINE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xxxxx

xx

xx

x

x

Device
Type

Power

Speed

Package

Process/
Temperature
Range

Y:1ank

P
'--_ _ _ _ _ _ _~ C

J
L
'--_ _ _ _ _ _ _ _ _ _ _

~

Commercial (DOC to +70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP
Sidebraze DIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier

12
15

'--------------------1 L
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----1 73200

73201

Low Power
16-Bit 8-Level Pipeline Register
16-Bit 7-Level Pipeline Register
2562 drw 06

II

5.8

7

(;)®
Integrated Device Technology, Inc.

PRELIMINARY
IOT73210
IOT73211

FAST CMOS OCTAL
REGISTER TRANSCEIVER
WITH PARITY

FEATURES

• Even parity generation from Port B to Port A
• Parity polarity control
• High output drive capability: 64/48mA (commercial/
military)
• Available in 32-pin, 300 mil plastic DIP and sidebraze
DIP, surface mount 32-pin SOJ and LCC packages
• High-speed, low-power, CEMOSTM process technology
• Military product compliant to MIL-STD-883, Class B

• Two bidirectional interfacing ports
• Single-level pipeline register for one port and one-level
(73211) or two-level (73210) pipeline register for the
other port
• 8-bit wide interface ports plus parity bit
• Even parity checking in both directions
• Even/odd parity generation from Port A to Port B

FUNCTIONAL BLOCK DIAGRAM
PERRB

Ao-a

Vee GND2-{)

AEN----.l
CP -+--~'>
OXo-a

9
POLARITY - t - - - - - t - - . . - - - - - - - - ,

Even Parity
Check

Even/Odd
Parity
Generation

Even Parity
Check

9

9

9

Wo-a

OYo-a

1-4-----.,- BEN
1------1

LE

~---------~ SEL

'----...-----'

PERRA

BOE

2594 drw 03

Bo-a

CEMOS is a trademark of Integrated Device Technology Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
101990 Integrated Device Technology, Inc.

5.9

APRIL 1990
DSC·90351·

1

1DT73210, IDT73211
FAST CMOS OCTAL REGISTER TRANSCEIVER WITH PARITY

MILITARY AND COMMERCIAL TEMPERATURE RANGES

APPLICATIONS
• Cache memory bus interface
• Read and write buffers for RISC microprocessor system
• Registered transceiver with parity

FUNCTIONAL DESCRIPTION
The I DT7321 0/1 Octal Register Transceivers are highspeed, low-power data interface with data integrity checking
capability.
They are designed for high-performance systems requ iring
bidirectional data transfer between two buses and maintaining error checking via parity.
In any RISC or CISC microprocessor system, the
I DT7321 0/1 can be used to interface cache memory with main
memory. Data integrity is ensured through parity checking.
Control features allow dynamic reconfiguration of
check/generate and odd/even parity options.
DETAILED FUNCTIONAL DESCRIPTION
Port A to Port B Path (IDT73210 and IDT73211) is
comprised of a register (X), an even/odd parity generator and
an even parity checker. The input data is on the AO-8 lines.
When AEN is low, Ao-s is latched into Register X on the lowto-high CP transition. Even parity of the latched data is
checked. If PERRA goes high, a parity error has occurred. A
new parity bit, Bs, is generated. The output data bus is BO-8
and is enabled when BOE is low.
Port B to Port A Path (1DT73210) is comprised of a latch
(W), two registers (Y and Z), an even parity generator/checker
and a parity bit latch complementor. The input data bus is on
the Bo-s lines.
When SEL is high, the incoming data is latched into Latch
W. When LE is high, Latch W is transparent; when LE is low,
Latch W is closed. The parity bit, B8, can be complemented
by the POLARITY pin. If POLARITY is low, the parity sense
remains the same. If POLARITY is high, the parity sense is
complemented. Parity is not generated in this path. Even
parity of latched data is checked. If PERRB goes high, a parity
error has occurred. When BEN is low, WO-8 is latched into
Register Z on the low-to-high CP transition. The previous
contents are held in Register Z if BEN is high or if there is no

5.9

low-to-high CP transition. The output data bus is AO-8 and is
enabled when AOE is low. When SEL is high, there is only a
one clock cycle latency.
When SEL is low, the incoming data is latched into Register
Y on the low-to-high CP transition, when BEN is low. Even
parit~ of the registered data is checked. If PERRB goes high,
a panty error has occurred. Even parity (OYS) is generated on
the contents in RegisterY. When BEN is low, the contents of
register Yare transferred to Register Z on the low-to-high CP
transition. When BOE is low, the content of RegisterZ is made
available at output Port A. When SEL is low, there is a two
clock cycle latency.
Port B to Port A Path (IDT73211) is comprised of a latch
(W). two registers (Y and Z), an even parity generator/checker
and a parity bit latch complementor. The input data bus is on
the Bo-s lines.
When SEL is high, the incoming data is latched into Latch
W. When LE is high, Latch W is transparent; when LE is low,
Latch W is closed. The parity bit, Bs, can be complemented
by the POLARITY pin. If POLARITY is low, the parity sense
remains the same. If POLARITY is high, the parity sense is
complemented. Parity is not generated in this path. Even
parity of latched data is checked. If PERRB goes high, a parity
error has occurred. When BEN is low, Wo-s is latched into
Register Z on the low-to-high CP transition. The previous
contents are held in Register Z if BEN is high or if there is no
low-to-high CP transition. The output data bus is Ao-s and is
enabled when AOE is low. When SEL is high, there is only a
one clock cycle latency.
When SEL is low, the incoming data is latched into Latch Y
when LE is high. Latch Y is closed when LE is low. Even parity
of latched data is checked. If PERRB goes high, a parity error
has occurred. Even parity (OYs) is generated on the contents
in Latch Y. When BEN is low, the contents of Latch Yare
transferred to Register Z on the low-to-high CP transition.
When BOE is low, the content of Register Z is made available
at output Port A. When SEL is low, there is a one clock cycle
latency.
The power pins are Vcc and GNDo-2. GNDo is internal quiet
ground, GND1 is Port B ground and GND2 is Port A ground.

II

IDT73210, 1DT73211
MILITARY AND COMMERCIAL TEMPERATURE RANGES

FAST CMOS OCTAL REGISTER TRANSCEIVER WITH PARITY

PIN CONFIGURATIONS(1)

~

Index

I

B2
B3
B4
GNDo
GND1
Bs
Bs
B7
Ba

I~

0

1muj I~

BEN
BOE
Bo
B1
B2
B3
B4
GNDo
GND1
Bs
Bs
B7
Ba
PERRB
LE
CP

0

C::Cc::cC::CC::CCJ)-Im

A1
A2
A3
A4
Vce
GND2
As
As

A7
2594 drwOl

co

c::c W Cl...


I

Set-up Time
AEN, BEN to CP Low-to-High

........>

Hold Time
AEN, BEN to CP Low-to-High ...•....•.

...........

ts

Set-up Time
B0-8 to LE

tH

Hold Time
B0-8 to LE

ts

Set-up Time
B0-8 to CP to Low-to-High; LE

. . . :)_
:/t>

:

.............

>

.

..

.....

..........

••••

i

tH

Hold Time
A0-8, S0-8, POLARITY, SEL to CP

. . . . . . . ./·• •>• 1.5. . . . . . . .·.>•. .·

ts

Set-up Time
AEN, SEN to CP Low-to-High

Description

tPLH
tPHL

Propagation Delay
Clock to A0-8 (AOE
Clock to S0-8 (SOE

tPHL
tPHL

Min.

= Low)
= Low)

>

.,,/

.> ....•...•••• (

1<

t5
tH
t5
tH

Hold Time
AEN, SEN to CP Low-to-High •••.

•

••••

..... ".>

."

Set-up Time
S0-8 to LE
Hold Time
S0-8 to LE

••••••••

.")

-

-

ns

-

-

ns

2.0

-

-

ns

1.5

-

-

ns

2.0

-

-

ns

1.5

-

-

ns

3.0

-

-

ns

1.5

-

-

ns

...

i

.....

tH

;~\b .

...........
.•• >.•••

........

...

.

Set-up Time
S0-8 to CP to Low-to-High; LE

= High

Hold Time
S0-8 to CP to Low-to-High; LE

= High

tPZH
tPZL

Output Enable Time
AOE to A0-8, SOE to SO-8

-

-

7.0

ns

tPHZ
tPLZ

Output Disable Time
AOE to AO-8, SOE to SO-8

-

-

6.5

ns

tPWH

Clock Pulse Width High

8

6

-

ns

tPWL

Clock Pulse Width Low

8

6

-

NOTE:
1. Typical values are at Vee = S.OV and +25°e ambient.

ns
2594 tIllll

5.9

11

IDT73210, IDT73211
FAST CMOS OCTAL REGISTER TRANSCEIVER WITH PARITY

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Vee

ESD
PROTECTION
IIH

~

INPUTS

OUTPUTS

-+-

ilL

2594 drw 07
2594 drw 08

Figure 4. Input Interface Circuit
Figure 5. Output Interface Circuit

II
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance
RL = Termination resistance: should be equal to ZOUT of the Pulse Generator
Figure 6. AC Test Load Circuit

AC TEST CONDITIONS
Input Pulse Levels

GND to 3.0V

Test

Switch

Input Rise/Fall Times

1V/ns

Closed

Input Timing Reference Levels

1.5V

Open Drain
Disable Low
Enable Low
All other Tests

Open

Output Reference Levels
Output Load

1.5V
See Figure 6

2594 tbl13
2594 tbl 12

5.9

12

1DT73210, 1DT73211

FAST CMOS OCTAL REGISTER TRANSCEIVER WITH PARITY

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

XXXX

X

X

Device Type

Package

Process/
Temperature
Range

y~LANK

~----------------~

y
TP
TC

L
~

____________________~ 73210
73211

Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
32-pin
32-pin
32-pin
32-pin

Small Outline IC (J-Bend)
Thin Plastic Dip (300mil wide)
Thin Sidebraze Dip (300mil wide)
Leadless Chip Carrier

a-bit One Single, One Double Pipeline Registers
a-bit Two Single Pipeline Registers
2594 drw 10

5.9

13

(;)®

16-BIT CMOS
ERROR DETECTION
AND CORRECTION UNIT

Integrated Device Technology, Inc.

IDT39C60
IDT39C60-1
IDT39C60A
IDT39C60B

• Standard Military Drawing #5962-88613 available for this
function

FEATURES
• Low-power CEMOSTM
- Military: 1OOmA (max.)
- Commercial: 85mA (max.)
• Fast
- Data in to Error Detect
IDT39C60B: 16ns (max.), IDT39C60A: 20ns (max.)
IDT39C60-1: 25ns (max.), IDT39C60: 32ns (max.)
- Data in to Corrected Data out
IDT39C60B: 25ns (max.), IDT39C60A: 30ns (max.)
IDT39CBO-1: 52ns (max.), IDT39C60: 65ns (max.)
• Improves system memory reliability
- Corrects all single-bit errors, detects all double and
some triple-bit errors
• Cascadable
- Data words up to 64 bits
• Built-in diagnostics
- Capable of verifying proper EDC operation via
software control
• Simplified byte operations
- Fast byte writes possible with separate byte enables
• Available in 48-pin DIP, 52-pin PLCC and LCC
• Pin-compatible to all versions of the AMD2960
• Military product available compliant to MIL-STD-883,
Class B

DESCRIPTIONS
The IDT39C60 family are high-speed, low-power, 16-bit
Error Detection and Correction Units which generate checkbits on a 16-bit data field according to a modified Hamming
Code and correct the data word when checkbits are supplied.
When performing a read operation from memory, the
I DT39C60s will correct 100% of all single bit errors, will detect
all double bit errors and some triple bit errors.
The IDT39C60s are easily cascadable from 16 bits up to 64
bits. Sixteen-bit systems use 6 check bits, 32-bit systems use
7 check bits and 64-bit systems use 8 check bits. For all three
configurations, the error syndrome is made available.
All parts incorporate 2 built-in diagnostic modes. Both
simplify testing by allowing for diagnostic data to be entered
into the device and to execute system diagnostic functions.
. The IDT39C60s are pin-compatible, performance-enhanced
functional replacements for all versions of the 2960. They are
fabricated using CEMOS, a CMOS technology designed for
high-performance and high-reliability. The devices are packaged in either 48-pin DIPs and 52-pin PLCC and LCCs.
Military grade product is manufactured in compliance to the
latest revision of MIL-STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAM
LEOllT
Of; BYTE 0
CB~eJ~~----~--1------------------------------------'

DATA0-7

~-t-:;L--.....~

DATA8-15 ~--PTI--L~~:-'J

Of; BYTE 1 eJ-+-1-+-----'
sc~

~sc

LEIN

L>---+-+---------l

LEOIAG

LJ--------------'

CODE ID
DIAG MODE LJ--""*--+i
PASSTHRU
~ C)------+i
CORRECT

2595 drw 01

CONTROL
LOGIC

CEMOS and MICROSLICE are trademarks of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
e1990 Integrated Device Technology. Inc.

5.10

APRIL 1990
DSC·9016/2

1

II

I

IDT39C60/-1/AIB
16-BIT CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION
CORRECT
DATA15
DATA14
DATA13
DATA12
LEIN
LEDIAG
OEBYTEl
DATAl 1
DATA10
DATAg
DATAa
GND
DATA7
DATA6
DATAs
DATA4
OE BYTEo
LEoUT
DATA3
DATA2
DATAl
DATAo
SC1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

P48-1
&

C48-2

PASSTHRU
DIAG MODEl
DIAG MODEo
CODE ID2
CODE IDl
CODE IDa
GENERATE
CB6
CBo
CBs
CB4
CB3
Vee
CB2
CBl
MULT ERROR
ERROR
OEse
SCo
SCs
SC3
SC2
SC4
SC6
2595 drw 02

DIP
TOP VIEW
(600 mil x 100 mil Centers)

INDEX
I

I

L-..J

I

I

LJ

I

I

LJ

f

I

LJ

I

I

L-J

I

I

I

I

L..J

I

I

I

LJ

I

I

I

LJ

I

I

LJ

I

I

L..J

I.

I

W

LJ

I

7 6 5 4 3 t 525150494847
LEOIAG

OE BYTE,
DATA11
DATA,o
DATA9
DATAs
GND
DATA7
DATA6
DATAs
DATA4
OE BYTEo
Vee

:J 8
:J 9
:J 10
:J 11

:J

46
45
44
43
42
41
40
39
38
37
36
35
34

PIN 1
INDICATOR
FOR PLCC

12

:J 13
:J 14

:J 15
:J
:J
:J
:J
:J

J52-1

&

16
17
18
19
20

L52-1

[:

c:

c:
[:

c:

c:
[:
[:
[:
[:
[:
[:

c:

GND
GENERATE
C86
CBo
CBs
C84
CB3
Vee
CB2
CB,
MULTERROR
ERROR
OEse

21222324252627282930313233
1111'-'1111111111111111'-'11
I

I

I

I

I

I

I

1'1

I

I

I

I

I

1'1

I

I

I

I

I

1'1

2595 drw 03

PLCC/LCC
TOP VIEW
(750 mil x 750 mil Centers)
5.10

2

IDT39C60/-1/A1B
16-BIT CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTIONS
I/O

Description

I/O

16 bidirectional data lines provide input to the Data Input Latch and receive output from the Data Output Latch.
DATAo is the least significant bit; DATA15 the most significant.

CBo-s

I

Seven check bit input lines are used to input check bits for error detection. Also used to input syndrorne bits
for error correction in 32- and 64-bit configurations.

LEIN

I

Latch Enable - Data Input Latch. Controls latching of the input data. When HIGH, the Data Input Latch and
Check Bit Input Latch follow the input data and input check bits. When LOW, the Data Input Latch and Check
Bit Input Latch are latched to their previous state.

GENERATE

I

Generate Check Bits input. When this input is LOW, the EDC is in the Check Bit Generate mode. When HIGH,
the EDC is in the Detect mode or Correct mode. In the Generate mode, the circuit generates the check bits
or partial check bits specific to the data in the Data Input Latch. The generated check bits are placed on the
SC outputs. In the Detect or Correct modes the EDC detects single and multiple errors and generates
syndrome bits based upon the contents of the Data Input Latch and Check Bit Input Latch. In Correct mode,
single-bit errors are also automatically corrected - corrected data is placed at the input of the Data Output
Latch. The syndrome result is placed on the SC outputs and indicates, in a coded form, the number of errors
and the bit-in-error.

SCo-s

0

Syndrome/Check Bit outputs hold the check/partial check bits when the EDC is in Generate mode and will hold
the syndrome/partial syndrome bits when the device is in Detect or Correct modes. These are 3-state outputs.

OEsc

I

Output Enable - Syndrome/Check Bits. When LOW, the 3-state output lines SCo-s are enabled. When HIGH,
the SC outputs are in the high impedance state.

ERROR

0

Error Detected output. When the EDC is in Detect or Correct mode, this output will go LOW if one or more
syndrome bits are asserted, meaning there are one or more bit errors in the data or check bits. If no syndrome
bits are asserted, there are no errors detected and the output will be HIGH. In Generate mode, ERROR is
forced HIGH. (In a 64-bit configuration, ERROR must be implemented externally.)

MULTERROR

0

Multiple Errors Detected output. When the EDC is in Detect or Correct mode this output, if LOW, indicates
that there are two or more bit errors that have been detected. If HIGH, this indicates that either one or no errors
have been detected. In Generate mode, MUL T ERROR is forced HIGH. (In a 64-bit configuration,
MULT ERROR must be implemented externally.)

CORRECT

I

Correct input. When HIGH, this signal allows the correction network to correct any single-bit error in the Data
Input Latch (by complementing the bit-in-error) before putting it into the Data Output Latch. When LOW, the
EDC will drive data directly from the Data Input Latch to the Data Output Latch without correction.

LEoUT

I

Latch Enable - Data Output Latch. Controls the latching of the Data Output Latch. When LOW, the Data
Output Latch is latched to its previous state. When HIGH, the Data Output Latch follows the output of the Data
Input Latch as modified by the correction logic network. In Correct mode, single-bit errors are corrected by
the network before loading into the Data Output Latch. In Detect mode, the contents of the Data Input Latch
are passed through the correction network unchanged into the Data Output Latch. The inputs to the Data
Output Latch are disabled with its contents unchanged if the EDC is in Generate mode.

OE BYTEo
OE BYTE1

I

Output Enable - Bytes 0 and 1, Data Output Latch controls the 3-state outputs for each of the two bytes
of the Data Output Latch. When LOW, these lines enable the Data Output Latch and, when HIGH, these lines
force the Data Output Latch into the high impedance state. The two enable lines can be separately activated
to enable only one byte of the Data Output at a time.

PASSTHRU

I

DIAG MODE0-1
CODE 100-2

I
I

LEDIAG

I

PASSTHRU input, when HIGH, forces the contents of the Check Bit Input Latch onto the Syndrome/Check
Bit outputs (SCo-s) and the unmodified contents of the Data Input Latch onto the inputs of the Data Output
Latch.
Diagnostic Mode Select controls the initialization and diagnostic operation of the EDC.
Code Identification inputs identify the size of the total data word to be processed and which 16-bit slice of larger
data words a particular EDC is processing. The three allowable data word sizes are 16, 32, and 64 bits and
their respective modified Hamming Codes are designated 16/22, 32/39 and 64/72. Special CODE 10 input
001 (102,101,100) is also used to instruct the EDC that the signals CODE 100-2, DIAG MODE0-1, CORRECT
and PASSTHRU are to be taken from the diagnostic latch rather than the control lines.
Latch Enable - Diagnostic Latch. The Diagnostic Latch follows the 16-bit data on the input lines when HIGH.
When LOW, the outputs of the Diagnostic Latch are latched to their previous states. The Diagnostic Latch
holds diagnostic check bits and internal control signals for CODE 100-2, DIAG MODE0-1, CORRECT and
PASSTHRU.

Pin Name
DATA0-15

25951b10l

5.10

3

•

IDT39C60/-1/AIB
16-BIT CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PRODUCT DESCRIPTION
The IDT39C60 EDC Unit is a powerful 16-bit cascadable
slice used for check bit generation, error detection, error
correction and diagnostics. As shown in the Functional Block
Diagram, the device consists of the following:
-

Data Input Latch
Data Output Latch
Diagnostic Latch
Check Bit Input Latch
Check Bit Generation Logic
Syndrome Generation Logic
Error Detection Logic
Error Correction Logic
Control Logic

ERROR goes low. If two or more errors are detected, both
ERROR and MULT ERROR go low. Both outputs remain high
when there are no errors detected.
For single bit errors, the correction logic will complement
(correct) the bit in error, which canthen be loaded into the Data
Out Latches under the LEoUT control. If check bit errors need
to be corrected, then the device must be operated in the
Generate mode.

CONTROL LOGIC
The control logic determines the specific mode of operation, usually from external control signals. However, the
Internal Control mode allows these signals to be provided
from the Diagnostic Latch.

DETAILED PRODUCT DESCRIPTION

DATA INPUT/OUTPUT/DIAGNOSTIC LATCHES
The LEIN, Latch Enable input, controls the Data Input which
can load 16 bits of data from the bidirectional DATA lines. The
input data is used for either check bit generation or error
detection/correction.
The 16 bits of data from the DATA lines can be loaded into
the Diagnostic Latch under control of the Diagnostic Latch
Enable, LEDIAG, giving check bit information in one byte and
control information in the other byte. The Diagnostic Latch is
used when in Internal Control mode or in one of the Diagnostics modes.
The Data Output Latch is split into two bytes and enabled
onto the DATA lines through separate byte control lines. The
Data Output Latch stores the result of an error correction
operation or is loaded directly from the Data Input Latch under
control of the Latch Enable Out (LEoUT). The PASSTHRU
control input determines which data is loaded.

CHECK BIT GENERATION LOGIC
This block of combinational logic generates 7 check bits
using a modified Hamming Code from the 16 bits of data input
from the Data Input Latch.

SYNDROME GENERATION LOGIC
This logic compares the check bits generated through the
Check Bit Generatorwith either the check bits in the Check Bit
Input Latch or 7 bits assigned in the Diagnostic Latch.
Syndrome bits are produced by an exclusive-OR of the two
sets of bits. A match indicates no errors. If errors occur, the
syndrome bits can be decoded to indicate the bit in error,
whether 2 errors were detected or 3 or more errors.

ERROR DETECTION/CORRECTION LOGIC
The syndrome bits generated by the Syndrome Logic are
decoded and used to control the ER ROR and
MULTERROR outputs. If one or more errors are detected,

The IDT39C60 EDC unit contains the logic necessary to
generate check bits on a 16-bit data input according to a
modified Hamming Code. The EDC can compare internally
generated check bits against those read with the 16-bit data
to allow correction of any single bit data error and detection of
all double and some triple bit errors. The IDT39C60 can be
used for 16-bit data words (6 check bits), 32-bit data words
(7 check bits) or 64-bit data words (8 check bits).

CODE AND BYTE SELECTION
The 3 code identification pins, IDo-2, are used to determine
the data word size from 16,32 or 64 bits and the byte position
of each 16-bit IDT39C60 EDC device.
Code 16/22 refers to a 16-bit data field with 6 check bits.
Code 32/39 refers to a'32-bit data field with 7 check bits.
Code 64/72 refers to a 64-bit data field with 8 check bits.
The IDo-2 of 001 is used to place the device in the Internal
Control mode as described later in this section.
Table 1 defines all possible identification codes.

CHECK AND SYNDROME BITS
The I DT39C60 provides either check bits or syndrome bits
on the three-state output pins, SCo~. Check bits are generated from a combination of the Data Input bits, while syndrome
bits are an Exclusive-OR of the check bits generated from
read data with the read check bits stored with the data.
Syndrome bits can be decoded to determine the single
bit-in-error or that a double error was detected. Some triple bit
errors are also detected. The check bits are labeled:
Co,
Co,
Co,
Co,

Cl,
Cl,
Cl,
Cl,

C2,
C2,
C2,
C2,

C3,
C3,
C3,
C3,

C4
C4, Cs
C4, Cs, C6
C4, Cs, C6, C7

for the 8-bit configuration
for the 16-bit configuration
for the 32-bit configuration
for the 64-bit configuration

Syndrome bits are similarly labeled So through S7.

5.10

4

IDT39C60/-11 AlB
16-BIT CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CONTROL MODE SELECTION
Tables 2 and 3 describe the 9 operating modes of the
IDT39C60. The Diagnostic mode pins, DIAG MODEo-l,
define 4 basic areas of operation, with GENERATE, CORRECT and PASSTHRU, further dividing operation into 8
functions with the 100-2 defining the ninth mode as the Internal
mode.
Generate mode is used to display the check bits on the
outputs SCO--6. The Diagnostic Generate mode displays
check bits as stored in the Diagnostic Latch.
Detect mode provides an indication of errors or multiple
errors on the outputs ERROR and MULTERROR. Single bit
errors are not corrected in this mode. The syndrome bits are
provided on the outputs SCO--6. For the Diagnostic Detect
mode, the syndrome bits are generated by comparing the
internally generated check bits from the Data In Latch with
check bits stored in the diagnostic latch rather than with the
check bit latch contents.

CODE
102

CODE
101

CODE

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1

100

0

1

Correct mode is similar to the Detect mode except that
single bit errors will be complemented (corrected) and made
available as input to the Data Out Latch. Again, the Diagnostic
Correct mode will correct single bit errors as determined by
syndrome bits generated from the Data Input and contents of
the Diagnostic Latch.
The Initialize mode provides check bits for all zero bit data.
Data In Latch is set and latched to a logic zero and made
available as input to the Data Out Latch.
The Internal mode disables the external control pins DIAG
MODEo-l, CORRECT, PASSTHRU and CODE 10 to be
defined by the Diagnostic Latch. When in the internal control
mode, the data loaded into the diagnostic latch should have
the CODE 10 different from 001 as this would represent an
invalid operation.

Hamming Code
and Slice Selected
Code 16/22
Internal Control Mode
Code 32/39, Byte 0 and
Code 32/39, Byte 2 and
Code 64n2, Byte 0 and
Code 64n2, Byte 2 and
Code 64/72, Byte 4 and
Code 64n2, Byte 6 and

1
3
1
3
5
7

2595 tbl 02

DlAG
MODEl

DIAG
MODE2

0

0

Non-diagnostic mode. The EDC
functions normally in all modes.

0

1

Diagnostic Generate. The contents of
the Diagnostic Latch are substituted for
the normally generated check bits when
in the Generate mode. The EDC functions normally in the Detect or Correct
modes.

1

0

Diagnostic Detect/Correct. In the Detect
or Correct mode, the contents of the
Diagnostic Latch are substituted for the
check bits normally read from the Check
Bit Input Latch. The EDC functions
normally in the Generate mode.

Table 1. Hamming Code and Slice Identification

1

1

Diagnostic Mode Selected

Initialize. The outputs of the Data Input
Latch are forced to zeroes and the check
bits generated correspond to the all zero
data. The latch is not reset, a functional
difference from the Am2960.
2595 tbl 03

Table 2. Diagnostic Mode Control

5.10

5

II
I

IDT39C60/-1/A1B
16-BIT CMOS DETECTION AND CORRECTION UNIT

Operating
Mode
Generate

DMl DMo

a
1

Detect
Correct
PASSTHRU

a
a
a
a
a

a
a
a

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DAT AOUT Latch
(LEoUT High)

Check Bits Generated
from DATAIN Latch

High

PASS·
THRU

a

x

a

1

a

a

OAT AIN Latch

Syndrome Bits DATAIN/
Check Bit Latch

Error Dep(1)

1

1

a

OAT AIN Latch with
Single Bit Correction

Syndrome Bits DATAIN/
Check Bit Latch

Error Dep

x

x

1

OAT AIN Latch

=

-

1

a

ERROR
MULT ERROR

CORRECT

1

a

SC0-6
(OEsc Low)

GENERATE

=

Check Bit Latch

High

Check Bits from
Diagnostic Latch

High

0
1

a

Diagnostic
Generate

a

1

a

x

a

Diagnostic
Detect

1

a

1

a

a

OAT AIN Latch

Syndrome Bits OAT AIN/
Diagnostic Latch

Error Dep

Diagnostic
Correct

1

a

1

1

a

DA T AIN Latch with
Single Bit Correction

Syndrome Bits OATAIN/
Diagnostic Latch

Error Dep

Initialization
Mode

1

1

X

X

X

OAT AIN Latch
Set to 0000

1

-

Check Bits Generated
from DATAIN Latch

-

(0000)
Internal
Mode

100-2 = 001 (Control Signals 100-2, DIAG MODEo-1, CORRECT and PASSTHRU are taken from the Diagnostic
Latch)

NOTE:
2595 tbl 04
1. ERROR DEP (Error Dependent): ERROR will be low for single or multiple errors, with MULT ERROR low for double or multiple errors. Both signals are
high for no errors.
Table 3. IDT39C60 Operating Modes

5.10

6

IDT39C60/-1/AlB
16-BIT CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

16-BIT DATA WORD CONFIGURATION
A single IOT39C60 EOC unit, connected as shown in
Figure 2, provides all the logic needed for single bit error
correction and double bit error detection of a 16-bit data field.
The identification code 16/22 indicates 6 check bits are
required. The CB6 pin is, therefore, a "Don't Care" and 102,
101,100 = 000.

Figure 1 indicates the 22-bit data format for two bytes of
data and 6 check bits.

DATA

CHECK BITS

I BYTE, I BYTEo I
15

87

Co

C1

I C2 I

I

C3

Cs

C4

a
2595 drw 04

Uses Modified Hamming Code 16/22
16 Data Bits with 6 Check Bits
Figure 1. 16-Bit Data Format

INPUT CHECK BITS
FOR 16-BIT CONFIGURATION

A

r~----------

DATAo-1s

Co

DATAo-1s

CBo CB1

C1

C2

C3

~------T-IE-T-~

C4

So/Co

SC,

SC2

Vee

CB2 CB3 CB4 CBs CB6

IDT39C60 EDC

SCo

Cs

SC3

SC4

CODE ID

SCs

"

S2/C2

S4/C4

II

000

SC6

HIGH

~-----------~ ------------_/
'V
SYNDROME/CHECK BIT OUTPUT
Figure 2. 16·Bit Configuration

Table 3 describes the operating modes available. The
output pin SC6, is forced high for either syndrome or check bits
since only 6 check bits are used for the 16/22 code.
Table 4 indicates the data bits participating in the check bit
generation. For example, check bit Co is the Exclusive-OR
function of the 8 data input bits marked with an X. Check bits
are generated and output in the Generate and Initialization
Mode. Check bits are passed as stored in the PASSTHRU or
Diagnostic Generate Mode.
Syndrome bits are generated by an Exclusive-OR of the
generated check bits with the read check bits. For example,
SX is the XOR of check bits CX from those read with those
generated. Table 5 indicates the decoding of the six

syndrome bits to indicate the bit-in-error for a single bit error,
or whether a double or triple bit error was detected. The all
zero case indicates no errors detected.
In the Correct Mode, the syndrome bits are used to complement (correct) single bit errors in the data bits. For double or
multiple errordetection, the data available as input to the Data
Out Latch is not defined.
Table 6 defines the bit definition for the Diagnostic Latch.
As defined in Table 3, several modes will use the diagnostic
check bits to determine syndrome bits or to pass as check bits
to the SCO-5 outputs. The Internal Mode substitutes the
indicated bit position for the external control signals.

5.10

7

IDT39C60/·1/AIB
16·BIT CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Participating Data Bits(1)

Generated
Check Bits

Parity

0

Co

Even (XOR)

Cl

Even (XOR)

X

C2

Odd (XNOR)

X

C3

Odd (X NOR)

X

C4

Even (XOR)

C5

Even (XOR)

1

2

3

X

X

X

X

X

4

7

X
X

X

X

X

X

8

9

X

X

10

X

X

X

X

X

X

11

12

13

X

X

X

X

X

X
X

6

5

X

X
X

X

X

X

X

X

X
X

X

X

X

15

X

X

X

14

X

NOTE:
1. The check bit is generated as either an XOR or XNOR of the eight data bits noted by an "X" in the table.

X
X
2595 tbl 05

Table 4. 16-81t Modified Hamming Code - Check Bit Encode Chart

I Hex
Syndrome
Bits

S5
S4

0

1

2

3

Data Bit

Internal Function

0
0

0
1

1
0

1
1

0

Diagnostic Check Bito

r--

Hex

S3

S2

Sl

So

0

0

0

0

0

1

0

0

0

1

2

0

0

1

3

0

0

4

0

5

6
7

1

Diagnostic Check Bil1

2

Diagnostic Check Bit2

C4

C5

T

3

Diagnostic Check Bit3

CO

T

T

14

4

Diagnostic Check Bit4

0

C1

T

T

M

5

Diagnostic Check Bits

1

1

T

2

8

T

6, 7

Don't Care

1

0

0

C2

T

T

15

8

CODE 100

0

1

0

1

T

3

10

T

9

CODE 101

0

1

1

0

T

4

9

T

10

CODE 102

0

1

1

1

M

T

T

M

11

DIAG MODEo

8

1

0

0

0

C3

T

T

M

12

DIAG MODEl

9

1

0

0

1

T

5

11

T

13

CORRECT

A

1

0

1

0

T

6

12

T

14

PASSTHRU

B

1

0

1

1

1

T

T

M

15

Don't Care

C

1

1

0

0

T

7

13

T

0

1

1

0

1

M

T

T

M

E

1

1

1

0

0

T

T

M

F

1

1

1

1

T

M

M

NOTES:
• = No errors detected
Number = The number of the single bit-in-error
T = Two errors detected
M = Three or more errors detected

2595 tbl 07

Table 6. Diagnostic Lalch Loading -16-811 Format

T
2595 tbl 06

08-15

Table 5. Syndrome Decode 10 Bit-In-Error
(16-BII Configuration)

Vec

DATA

CHECK
BITS

00-7

CB0-4

CB5,6

OE BYTE1
IOT39C60

OE SIGNAL

OE BYTEo
ERROR

MUL TERROR

SC0-4

2595 drw06

Figure 3. 8-Bil Configuration

5.10

IDT39C601-1/A/B
16-BIT CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

32-BIT DATA WORD CONFIGURATION
Two IDT39C60 EDC units, connected as shown in Figure
5, provide all the logic needed for single bit error correction
and double bit error detection of a 32-bit data field. The
identification code 32/39 indicates 7 check bits are required.
Table 1 gives the 102, 101, 100 values needed for distinguishing the byte 0/1 from byte 2/3. Valid syndrome, check bits and
the ERROR and MUL TERROR signal come from the byte
2/3 unit. Control signals not indicated are connected to both
units in parallel. The OEsc always enables the SCO-6 outputs
of byte 0/1, but must be used to select data check bits or
syndrome bits fed back from the byte 2/3 for data correction
modes.
Data In bits 0 through 15 are connected to the same
numbered inputs of the byte 0/1 EDC unit, while Data In bits
16 through 31 are connected to byte 2/3 Data Inputs 0 to 15,
respectively.
Figure 4 indicates the 39-bit data format for 4 bytes of data
and 7 check bits. Check bits are input to the byte 0/1 unit
through a tri-state buffer unit such as the IDT74FCT244.
-Correction of single bit errors of the 32-bit configuration
requires a feedback of sydrome bits from byte 2/3 into the byte
0/1 unit. The MUX shown on the functional block diagram is
used to select the CBo-6 pins as the syndrome bits rather than
internally generated syndrome bits.
Table 3 describes the operating mode available for the
32/39 configuration.
Syndrome bits are generated by an Exclusive-OR of the
generated check bits with the read check bits. For example,
Sn is the XOR of check bits Cn from those read with those
generated. Table 7 indicates the decoding of the seven
syndrome bits to determine the bit-in-errorfor a single bit error,
or whether a double or triple bit error was detected. The all
zero case indicates no errors detected.
Inthe Correct Mode, the syndrome bits are used to complement (correct) single bit errors in the data bits. For double or
multiple errordetection, the data available as input to the Data
Out Latch is not defined.
Performance data is provided in Table 8 in relating a single
IDT39C60 EDC with the two cascaded units of Figure 5. As
indicated, a summation of propagation delays is required from
the cascading arrangement of EDC units.
Table 9 defines the bit definition for the Diagnostic Latch.
As defined in Table 3, several modes will use the Diagnostic
check bits to determine syndrome bits or to pass as check bits
to the SCO-6 outputs. The Internal Mode substitutes the
indicated bit position for the external control signals.
Table 10 indicates the data bits participating in the check bit
generation. For example, check bit Co is the Exclusive-OR
function of the 16 data input bits marked with an X. Check bits
are generated and output in the Generate and Initialization
Mode. Check bits are passed as stored in the PASSTHRU or
Diagnostic Generate Mode.

5.10

,--

Hex

I Hex

0

1

2

3

4

5

6

7

S6
S5
S4

0
0
0

0
0
1

0
1

0
1
1

1
0

1
0
1

1
1
0

1
1
1

Syndrome
Bits

0

0

S3 S2 Sl SO
T 30

0

0

0

0

0

1

0

0

0

1

C4 C5 T C6 T
CO T T 14 T M

M

2

0

0

1

0

C1

2

24

3

0

0

1

1

M

T

T 31

M

T

T

T
T

4
5

26 M
27 T

M

T

B

1

0

1

1

C

1

1

0

0

0

1

1

0

1

E

1

1

1

0

T T M
T 18 8 T
C2 T T 15
T 19 9 T
T 20 10 T
T M
M T
C3 T T M
T 21 11 T
T 22 12 T
17 T T M
T 23 13 T
M T
T M
16 T T M

F

1

1

1

1

T

4

0

1

0

0

5

0

1

0

1

6

0

1

1

0

7

0

1

1

1

8

1

0

0

0

9

1

0

0

1

A

1

0

1

0

M

M

T

T
M

T

T

T
T T M
3 25 T
M

T

T M
T M
6 28 T
T T M
7 29 T
M M T

0

T

1

T
M

T

NOTES:
• = No errors detected
Number = The number of the single bit-in-error
T = Two errors detected
M = Three or more errors detected

T

T

M

2595 tbl 08

II

Table 7. Syndrome Decode to Bit-In-Error
(32-Bit Configuration)

32-Bit
Propagation Delay
From
To
DATA Check Bits Out
DATA Corrected
DATAoUT

Component Delay
From IDT39C60
AC Specifications
(DATA to SC) + (CB to SC, CODE ID 011)
(DATA to SC) + (CB to SC, CODE ID 011)
CB to DATA, CODE ID 010)

DATA Syndromes Out
DATA ERROR for
32 Bits
DATA MULT ERROR
for 32 Bits

(DATA to SC) + (CB to SC, CODE ID 011)
(DATA to SC) + (CB to ERROR,
CODE ID011)
(DATA to SC) + (CB to MULT ERROR,
CODE ID 011)

+

2595 tbl 09

Table 8. Key AC Calculations for the 32-Bit Configuration

9

IDT39C60/-1/A1B
16-BIT CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

2595 drw 07

Uses Modified Hamming Code 32/39
32 Data Bits with 7 Check Bits
Figure 4. 32-Bit Data Format

INPUT CHECK BITS
~

(

TA1s-31 DATAo-15

Co

C1

C2

C3

C4

C5

Cs

1

I

L

I

I

1

I

'\ :

1/8 OF
; IDTFCT240
OEsc

1\l7Q77VVH«1
IDT74FCT244

DATA

CB,

CBo

CB2

CB3

CB4

CB5 CB6
OEsc

IDT39C60 EDC
BYTE 0 AND 1
CODE 10

~

-010

DATA

SCo

SC1

SC2

SC3

SC4

SC5 SCs

CBo

CB,

CB2

CB3

CB4

CB5

CB6
OEsc

IDT39C60 EDC
BYTE 2 AND 3
CODE 10 r-011
SC5 SC6

MULT ERROR
ERROR

SCo

SC1

SC2 SC3

SC4

_1

ERROR
MULT ERROR
S,/C1
So/Co

S5/C5

S3/C3
S2IC2

S4/C4

S6/C6

~-----------~ -----------~/
V

2595 drw 08

SYNDROME/CHECK BIT OUTPUTS
Figure 5. 32-BII Configuration

5.10

10

IDT39C60/·1/AIB
16·BIT CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Data Bit

Internal Function

0

Diagnostic Check Bito

1

Diagnostic Check Bitl

2

Diagnostic Check Bit2

3

Diagnostic Check Bit3

4

Diagnostic Check Bit4

5

Diagnostic Check Bits

6

Diagnostic Check Bit6

7

Don't Care

8

Slice 0/1 -

CODE 100

9

Slice 0/1 -

CODE 101

10

Slice 0/1 -

CODE 102

11

Slice 0/1 -

DIAG MODEo

12

Slice 0/1 -

DIAG MODEl

13

Slice 0/1 -

CORRECT

14

Slice 0/1 -

PASSTHRU

15

Don't Care

16-23

Don't Care

24

Slice 2/3 -

CODE 100

25

Slice 2/3 -

CODE 101

26

Slice 2/3 -

CODE 102

27

Slice 2/3 -

DIAG MODEo

28

Slice 2/3 -

DIAG MODEl

29

Slice 2/3 -

CORRECT

30

Slice 2/3 -

PASSTHRU

31

Don't Care

II

2595 tbll0

Table 9. Diagnostic Latch Loading -

Generated

32·Bit Format

Participating Data Bits

Check Bits

Parity

0

Co

Even (XOR)

X

Cl

Even (XOR)

X

C2

Odd (X NOR)

X

C3

Odd (X NOR)

X

C4

Even (XOR)

Cs

Even (XOR)

C6

Even (XOR)

1
X

2

3

X
X

4

6

7

8

9

X

X

X

X

X

X

X

X

X
X

X

5

X

X

X

X

X

X

X

X
X

X

X

X

X

X

X

X

11

X

12

13

X
X

X

X

10

15

X
X

X

X

14

X
X

X

X

X

X

X

X
X

X

X

X

X
2595 !bIll

Generated

Participating Data Bits

Check Bits

Parity

Co

Even (XOR)

Cl

Even (XOR)

16
X

17

18

19

X

X

X

X

X

20

21

22

23

24

25

X
X

X

X

C2

Odd (X NOR)

X

C3

Odd (XNOR)

X

C4

Even (XOR)

Cs

Even (XOR)

X

X

C6

Even (XOR)

X

X

X

X

X
X

X

X

X
X

X

X

X

X

X

X

26

31

28

29

X

X

X

X

X

X
X

X

27

X

30

X

X

X
X

X

X

X

X

X

X

X

X

X

X

X

X

X
2595 tbl 12

Table 10. 32·Bit Modified Hamming Code - Check Bit Encode Chart

5.10

11

IDT39C60/-1/A/B

16-BIT CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

64-BIT DATA WORD CONFIGURATION
The IDT39C60 EDC units connected with the MSI gates, as
shown in Figure 6, provide all the logic needed for single bit
error detection and double bit error detection of a 64-bit data
field. The Identification code 64/72 is used, indicating 8 check
bits are required. Check bits and Syndrome bits are generated external to the IDT39C60 EDC using Exclusive-OR
gates. For error correction, the syndrome bits must be fed
back to the CBo-6 inputs. Thus, external tri-state buffers are
used to select between the check bits read in from memory
and the syndrome bits being fed back.
The ERROR signal is low for one or more errors detected.
From any of the 4 devices, MULTERROR is low for some
double bit errors and for all three bit errors. Both are high
otherwise. The DOUBLE ERROR Signal is high only when a
double bit error is detected.
Figure 6 indicates the 72-bit data format of 8 bytes of data
and 8 check bits. Check bits are input to the various units
through a tri-state buffer such as the IDT74FCT244. Correction of Single bit errors of the 64-bit configuration requires a
feedback of syndrome bits as generated external to the
IDT39C60 EDC. The MUX shown on the functional block
diagram is used to select the CBo-6 pins as the syndrome bits
rather than internally generated syndrome bits.
Table 3 describes the operating modes available for the 641
72 configuration.
Syndrome bits are generated by an Exclusive-OR of the
generated check bits with the read check bits. For example,
Sn is the XOR of check bits Cn from those read with those
generated. Table 11 indicates the decoding of the 8 syndrome
bitsto determine the bit-in-errorfor a single bit errororwhether

4039

3231

2423

a double or triple bit error was detected. The all zero case
indicates no errors detected.
In the Correct Mode, the syndrome bits are usedto complement (correct) single bit errors in the data bits. Fordouble or
multiple error detection, the data available as input to the Data
Out Latch is not defined.
Performance data is provided in Table 12 in relating a
single IDT39C60 EDC with the four units of Figure 7. Delay
through the Exclusive-OR gates and the 3-state buffer must
be included.
Table 13 indicates the Data Bits participating in the check
bit generation. For example, check bit Co is the Exclusive-OR
function of the 32 data input bits marked with an X. Check bits
are generated and output in the Generate and Initialization
mode. In the PASSTHRU mode, the contents of the check bit
latch are passed through the external Exclusive-OR gates
and appear inverted at the outputs Co to C7.
Table 14 defines the bit definition for the Diagnostic Latch.
As defined in Table 3, several modes will use the Diagnostic
Check Bits to determine syndrome bits orto pass as check bits
to the SCO-6 outputs. The Internal Mode substitutes the
indicated bit position for the external control signals.
Some multiple errors will cause a data bit to be inverted.
For example, in the 16-bit mode where bits 8 and 13 are in
error, the syndrome 111100 (So, Sl, S2, S3, S4, S5) is
produced. The bit-in-error decoder receives the syndrome
11100 (So, Sl, S2, S3, S4) which it decodes as a single error
in data bit 0 and inverts that bit. Figure 8 indicates a method
for inhibiting correction when a multiple error occurs.

o

1615

2595 drw 09

Uses Modified Hamming Code 64/72
32 Data Bits with 8 Check Bits
Figure 6. 64-Bit Data Format

5.10

12

IDT39C60/·1/AIB
16·BIT CMOS DETECTION AND CORRECTION UNIT

I Hex
-

S7
S6
S5
S4

Syndrome
Bits

MILITARY AND COMMERCIAL TEMPERATURE RANGES

a
a
a

1

2

3

4

5

6

7

a
a

a
a

a
a

a

a

a

a

1

1

1

0

0

1

1
1

a

0

0
1

a

1
1
1

a

a

1

a

1

8

1

9

A

1

1

a

a

0

0

1

a
1

B

C

D

E

F

1

1
1

a
a

1
1

1
1

1
1

0

1

1
0

1

a
1

a

1

1

Hex

S3

S2

Sl

So

a

a
a
a
a
a
a
a
a

a
a
a
a

a
a

a

.

C4

C5

T

C6

T

T

62

C7

T

T

46

T

M

M

T

1

co

T

T

14

T

M

M

T

T

M

M

T

M

T

T

30

1
1

a

C1

T

T

M

T

34

56

T

T

50

40

T

M

T

T

M

1

T

18

8

T

M

T

T

M

M

T

T

M

T

2

24

T

1

a
a

a

C2

T

T

15

T

35

57

T

T

51

41

T

M

T

T

31

1

T

19

9

T

M

T

T

63

M

T

T

47

T

3

25

T

1
1

a

T

20

10

T

M

T

T

M

M

T

T

M

T

4

26

T

1

M

T

T

M

T

36

58

T

T

52

42

T

M

T

T

M

a
a

a

C3

T

T

M

T

37

59

T

T

53

43

T

M

T

T

M

1

T

21

11

T

M

T

T

M

M

T

T

M

T

5

27

T

1

a

T

22

12

T

33

T

T

M

49

T

T

M

T

6

28

T

1

1

17

T

T

M

T

38

60

T

T

54

44

T

1

T

T

M

1
2
3
4

5
6

7

1
1
1

8

1

9

1

A

1

B

1

a
a
a
a

C

1

1

T

23

13

T

M

T

T

M

M

T

T

M

T

7

29

T

1

1

a
a

0

D

1

M

T

T

M

T

39

61

T

T

55

45

T

M

T

T

M

E

1
1

1

1

a

16

T

T

M

T

M

M

T

T

M

M

T

0

T

T

M

1

1

1

T

M

M

T

32

T

T

M

48

T

T

M

T

M

M

F

NOTES:
• = No errors detected
Number = The number of the single bit-in-error
T = Two errors detected
M = Three or more errors detected

T
2595 tbl13

II

Table 11. Syndrome Decode to Bit-ln·Error (64·Bit Configuration)

64·Bit

Component Delay

Propagation Delay
From

From IDT39C60

To

AC Specifications

DATA Check Bits Out

(DATA to SC) + (XOR Delay)

DATA Corrected
DATAoUT

(DATA to SC) + (XOR Delay) + (Buffer
Delay) + (CB to DATA, CODE ID 1xx)

DATA Syndromes

(DATA to SC) + (XOR Delay)

DATA ERROR for
64 Bits

(DATA to SC) + (XOR Delay) + (NOR
Delay)

DATA MULT ERROR
for 64 Bits

(DATA to SC) + (XOR Delay)+ (Buffer
Delay) + (CB to MUL TERROR,
CODE ID 1xx)

DATA DOUBLE
ERROR for
64 Bits

(DATA to SC) + (XOR Delay) +
(XOR/NOR Delay)
2595 tbl14

Table 12. Key AC Calculations for the 64·Bit Configuration

5.10

13

..... -

rv:--Z
__ 0

(110

'-1

tow
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0(1)

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m

CBsCB5CB4CB3CB2CB,CBo D

CBsCB5CB4CB3CB2CB,CBo D

CBsCB5CB4CB3CB2CB,CBo D

CBeCB5CB4CB3CB2CB,CBo D

o Esc

OEsc

o Esc

o Esc

I-£:-

IDT39C60
BYTE 6 AND 7

E

I-£:-

IDT39C60
BYTE 4 AND 5

I-£:-

IDT39C60
BYTE 2 AND 3

SCSSC5SC4SC3SC2SC,SCO

SCSSC5SC4SC3SC2SC,SCO

I

o
-I

oZ
c:

IDT39C60
BYTE 0 AND 1

Z
::::j

SCeSC5SC4SC3SC2SC,SCO

I

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MULT
ERROR

CD

"'" IIIro 0X
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o
o

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o

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Z

r~

Ol

o

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~.-L..-L..L,7.L,.-L.

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0

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cO'

C5 C4 C3 C2 Cl

D31-1S

1.1 K

CD :J

o

D47-32

m to

~

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L;

DS3-48

-

~S

CD-g

XO~,
:o::l

<

o CD
c ;:::.
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I
I

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gg

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:S'
<
CD

iira.

VXOR

VXOR

_V

f) S4/C4

VXOR

S5/C5

VXOR

~ Se/Ce

V

S3/C3

:::

r=
~:0

l1il

'--------t

VXOR
S2/C2

VXOR
S7/C7

VXOR
S,/C,

XORV
So/Co

-<

>
Z
C

(')

o
:::
:::
m

:0

1

11 I
S4/C4

S5/C5

XOR

NOR

...

"'"

V
6

(')

DOUBLE ERROR

1>
r

I )....lll

.1.

s,~e,

s~e,

NOR

~

-I

S2/C2

S7/C7

S,/C,

So/Co

m

:::
"Cl

m

:0

ERROR

>
-I
c:

:0

m
:0

>
Z

G')

m

en

IDT39C60/-1/AIB
16-BIT CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Participating Data Bits(1)

Generated
Check Bits

Parity

Co
C1
C2
C3
C4
Cs
Cs
C7

Even (XOR)

0

Even (XOR)

X

Odd (XNOR)

X

Odd (XNOR)

X

1

2

3

X

X

X

X

X

4

X

7

X

8

9

X

X
X

X
X

X

X

X

X

X

Even (XOR)

X

Even (XOR)

X

X

X

X

X

X

X

X

Even (XOR)

X

X

X

X

X

X

X

X

10

11

X

12

13

X
X

X

X

X

X
X

6

X
X

X

Even (XOR)

5

X
X
X

X

X

15

14

X

X

X

X

X

X

X
X

X

X

X

2595 tbl15

Participating Data Bits(1)

Generated
Check Bits

Parity

Co
C1
C2
C3
C4
Cs
Cs
C7

Even (XOR)

16

Even (XOR)

X

Odd (X NOR)

X

Odd (XNOR)

X

17

18

19

X

X

X

X

X

20

21

X
X

22

23

X

X

25

X

X
X

X
X

X

X

X

X

X

26

27

28

29

30

31

X

X
X

X

X

X

24

X

X

X
X

X

X

X
X

X

Even (XOR)

X

X

X

X

X

X

X

X

Even (XOR)

X

X

X

X

X

X

X

X

Even (XOR)

X

X

X

X

X

X

X

X

Even (XOR)

X

X

X

''''~"

Participating Data Bits(1)

Generated
Check Bits

Parity

32

Co
C1
C2
C3
C4
Cs
Cs
C7

Even (XOR)

X

Even (XOR)

X

Odd (XNOR)

X

Odd (X NOR)

X

33
X

34

35

X
X

36

38

39

X

X

X

X

X

X

X

Even (XOR)

X

X

37

X

X

X

X

X

X

X
X

X

X

X

X

X

X

X

41

X

Even (XOR)
Even (XOR)

40

X

44

45

X

X

X

X

X

X
X

X

42

43

X
X

X

X

47

46

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Even (XOR)

X
2595 tbl17

Participating Data Bits(1)

Generated
Check Bits

Parity

48

Co
C1
C2
C3
C4
Cs
Cs
C7

Even (XOR)

X

Even (XOR)

X

Odd (XNOR)

X

Odd (XNOR)

X

49
X

50

51

X
X

52

54

55

X

X

X

X

X

X

X

Even (XOR)

X

X

53

X

X

X

X

X

X

X
X

X

X

X

X

X

Even (XOR)
X

X

X

57

X

Even (XOR)
Even (XOR)

56

13.

64-Bit Modified Hamming Code -

5.10

61

X

X

X

X

X
X

X

59

X
X

X

X

62

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

NOTE:
1. The check bit is generated as either an XOR or XNOR of the 32 data bits noted by an "X" in the table.
Table

63

60

X

58

2595 tbl 1B

Check Bit Encode Chart

15

I

IDT39C60/-1/A1B
16-BIT CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Data Bit

Internal Function

Data Bit

0

Diagnostic Check Bito

31

Internal Function
Don't Care
Don't Care

1

Diagnostic Check Bit1

32-37

2

Diagnostic Check Bit2

38

3

Diagnostic Check Bit3

39

Don't Care

4

Diagnostic Check Bit4

40

Slice 4/5 -

CODE 100

5

Diagnostic Check Bits

41

Slice 4/5 -

CODE 101

6, 7

Don't Care

42

Slice 4/5 -

CODE 102

8

Slice 0/1 -

CODE 100

43

Slice 4/5 -

DIAG MODEo

9

Slice 0/1 -

CODE 101

44

Slice 4/5 -

DIAG MODE1

10

Slice 0/1 -

CODE 102

45

Slice 4/5 -

CORRECT

11

Slice 0/1 -

DIAG MODEo

46

Slice 4/5 -

PASSTHRU

12

Slice 0/1 -

DIAG MODE1

47

Don'! Care

13

Slice 011 -

CORRECT

48-54

Don't Care

PASSTHRU

Diagnostic Check Bit6

14

Slice 0/1 -

55

Diagnostic Check Bit?

15

Don't Care

56

Slice 617 -

CODE 100

16-23

Don't Care

57

Slice 617 -

CODE 101

24

Slice 2/3 -

CODE 100

58

Slice 617 -

CODE 102

25

Slice 2/3 -

CODE 101

59

Slice 617 -

DIAG MODEo

26

Slice 2/3 -

CODE 102

60

Slice 617 -

DIAG MODE1

27

Slice 2/3 -

DIAG MODEo

61

Slice 617 -

CORRECT

28

Slice 2/3 -

DIAG MODE1

62

Slice 617 -

PASSTHRU

29

Slice 213 -

CORRECT

63

Don't Care

30

Slice 2/3 -

PASSTHRU

2595 tbl20
2595 tbl 19

Table 14. Diagnostic Latch Loading -

Some multiple errors will cause a data bit to be inverted.
For example, in the 16-bit mode where bits 8 and 13 are in
error, the syndrome 111100 (So, S1, S2, S3, S4, S5) is
produced. The bit-in-error decoder receives the syndrome
11100 (So, S1, S2, S3, S4) which it decodes as a single error
in data bit 0 and inverts that bit. Figure 8 indicates a method
for inhibiting correction when a multiple error occurs.

64-Bit Format

DATA

IDT39C60

CHECK BITS

CORRECT

CORRECT

2595 drw 11

Figure 8. Inhibition of Data Modification

5.10

16

IDT39C60/-1/AIB
16-BIT CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL EQUATIONS
function of the value of the inputs and the internal states. Be
sure to carefully read the following definitions of symbols
before examining the tables.

The following equations and tables describe in detail how
the output values of the IOT39C60 EOC are determined as a

DEFINITIONS

01 ~ DATAl if LEIN is HIGH or the output of bit I of the Data Input Latch if LEIN is LOW
CI ~ CBI if LEIN is HIGH or the output of bit I of the Check Bit Latch if LEIN is LOW
OLI ~ Output of bit I of the Diagnostic Latch
SI ~ Internally generated syndromes (same as outputs of SCI if outputs enabled)
PA ~ Do EB 01 EB 02 EB 04 EB 06 EB 08 EB 010 EB 012
PB ~ Do EB 01 EB 02 EB 03 EB 04 EB 05 EB 06 EB 07
PC ~ 08 EB 09 EB 010 EB 011 EB 012 EB 013 EB 014
PO ~ Do EB 03 EB 04 EB 07 EB 09 EB 010 EB 013 EB 015
PE ~ Do EB 01 EB 05 EB 06 EB 07 EB 011 EB 012 EB 013
PF ~ 02 EB 03 EB 04 EB 05 EB 06 EB 014 EB 015
PGl ~ 01 EB 04 EB 06 EB 07
PG2 ~ 01 EB 02 EB 03 EB 05
PG3 ~ 08 EB 09 EB 011 EB 014
PG4 ~ 010 EB 012 EB 013 EB 015
Error Signals
ERR<5R': ~ (86· (101 + 102)) • S5 • S4 • S3 • S2 ·51· so + GENERATE + INITIALIZE + PASSTHRU
MULT ERROR:
(16 and 32-Bit Modes) ~ ((S6· 101) EB S5 EEl S4 EEl S3 EEl S2 EEl S1 EEl SO) (ERROR) + TOME + GENERATE +
PASSTHRU + INITIALIZE
MULT ERROR: (64-Bit Modes) ~ TOME + GENERATE + PASSTHRU + INITIALIZE

J Hex
Hex

a

8

1
2

9

3
4
5
6
7

Syndrome(1,2)
Bits
S2
Sl
So

a
a
a
a
a

S6
S5
S4
S3

1

4

3

2

a
a
a

a
a

a
a

a

a

a

a

1

1

1

a

a
a

a

1

1
1

1
1

1

a

1
1
1

1

a

a
1

1

a

1

1

1

1
1

1

1

1

1

1
1
1

1

1
1
1

A
B

1

a

1

1

C

1

a

0
E
F

1
1

a
a

1

1

1

a

1

1

1

1

1
1
1

1

1

1

1

1

1

1

1

a

a
a

1
1

a
a

a
a
a

1
1

1

1
1

1
1
1

1

a
1

1
1

1

a
a

1

a

1
1

1

a
a
a
a

1
1

7

6

5

1

1
1
1
1
1

1
1
1

1

1
1
1

1
1

1
1
1

1

1

1

1

1

1

NOTES:

2595 tbl 21
1. 56,55, ... 50 are internal syndromes except in Modes 010, 100, 101, 110, 111 (CODE 102, 101, 100). In these modes, the syndromes are input overthe
check bit lines. S6 ~ C6, S5 ~ C5, ... S1 ~ C1, So ~ Co.
2. The 56 internal syndrome is always forced to a in CODE 10 000.
Table 15. TOME (Three or More Errors)
CODE 100-2

Generate
Mode (Check Bits)

000

010

all

100

101

110

111

SCo~

PG2 EB PG3

PGl EB PG3

PG2 EB PG3

PG2 EB PG3

PGl EB PG4

PGl EB PG4

PA
PO

PO EB CB2

PA
PO

PA

f-

PA
PO

PG2 EB PG4
EB CBo
PA EB CB,

PO

PA
PO

PA
PO
PE

SCl
SC2

f-

SC3

f-

PE

PE

PE EB CB3

PE

PE

PE

SC4

f-

PF

PF

PF EB CB4

PF

PF

PF

PF

SCs

f-

PC

PC

PC EB CBs

PC

PC

PC

PC

SCs

f-

1

PB

PC EB CBs

PB

PB

PB

PB

2595 tbl22
Table 16. Generate Mode (Check Bits)
5.10

17

II

IDT39C60/-1/A1B

MILITARY AND COMMERCIAL TEMPERATURE RANGES

16-BIT CMOS DETECTION AND CORRECTION UNIT

Detect and Correct

CODE ID0-2
all

Modes (Syndromes)

000

010

SCo~

PG2 ffi PG3
ffi Co

PGl ffi PG3
ffi Co

(1)

PG2 ffi PG4
ffi CBo

100

101

110

111

PG2 ffi PG3
ffi Co

PG2 ffi PG3

PGl ffi PG4

PGl ffi PG4

SCl

~

PAffiCl

PAffi Cl

PAffi CB,

PAffi Cl

PA

PA

PA

SC2

~

PD ffi C2

PD ffi C2

PD ffi CB2

PD  .

DATA0-15
Via Diagnostic Latch
MINIMUM SET-UP AND HOLD TIMES

.i+:~ I>: \.

.

<

DATA0-15

CB0-7 (not applic. to CODEID1,6#JU/
DATA0-15

:X

CB0-7 (CODE ID 00<1:1

t<

CB0-7 (CODE ID ~)
CORRECT
):

) :.. :::::> ..

<::: . : .

If

DIAG MODE
CODE ID1,O

If

LEIN

~
<>

>

. . . .<:: • .

40

..:/

.I
\.

24

I

ns
19

To Input
(Latching Data)
LEIN

\.

\.

LEoUT

25951b138

Set-up Time

Hold Time

Unit

6

4

ns

6

4

ns

29

2

ns

25

0

ns

0

ns

26

0

30

0

\.

34

25

-

26

LEDIAG

ns
ns
ns

-

6

ns
ns

4

25951b139

MAXIMUM OUTPUT ENABLE/DISABLE TIMES

Output tests specified with CL = 5pF and measured to 0.5V change of output voltage level. Test performed with
CL = 50pF and correlated to CL = 5pF.
Enable

Disable

To Output

Enable
Max .

Disable
Max.

Unit

OE Byteo0-3

\.

DAT0-15

15

12

ns

OEsc

\.

.I
.I

SC0-7

15

12

From Input

MINIMUM PULSE WIDTHS
LEIN, LEoUT, LED lAG

./\.

(Positive-going pulse)

5.10

II
I

\.
\.
\.
\.
\.

DATA0-15

ns

:=..

RE~.itiv~q~ LATCH ENABLES
<

From Input

«::::.

I

14

J
I

ns

Min.

I

10

I

25951b140

ns
25951b141

23

IDT39C60/-1/A1B
16-BIT CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C60B AC ELECTRICAL
CHARACTERISTICS
(Guaranteed Commercial Range Performance)
The tables below specify the guaranteed performance of
the IDT39C60B over the commercial operating range of O°C
to +70°C, with Vcc from 4.7SV to S.2SV. All data are in
nanoseconds, with inputs switching between OV and 3V at 1 V
per nanosecond and measurements made at 1.SV.

MINIMUM SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES

MAXIMUM COMBINATIONAL PROPAGATION
DELAYS CL = SOpF

To
(Latching Data)

To Output
From Input

Set-up
Time

Hold
Time

ERROR

DATA0-15

LEIN

5

3

DATA0-15

18

DATA0-15
25 (1)

MULT
ERROR

18

20

CB0-6

LEIN

5

3

CB0-6
(CODE 102-0
000,011)

12

22

17

20

DATA0-15

LEoUT

24

2

LEoUT

21

0

CB0-6
(CODE 102-0010,
100,101,110,111)

12

16

17

LEoUT

21

0

GENERATE

13

-

LEoUT

22

0

CORRECT
(Not Internal
Control Mode)

-

17

LEoUT

22

0

> PASSTHRU

LEoUT

22

0

CqDE 102-0

LEoUT

25

0

LEIN

LEoUT

28

0

DATA0-15

LEolAG

5

3

From Input

SC0-6

CB0-6
(CODE 10 000,

CB0-6
(CODE IDq10,1qO,
101,110,11jr ....

-

-

CORF:lECT.»

-

-

DIAG MODE

DIAG MODE
(Not Internal
Control Mode)

20

PASSTHRU
(Not Internal
Control Mode)

20

22

CODE IDH)

20

22

LEIN
(From latched
to transparent)

20

LEoUT
(From latched
to transparent)

-

LEolAG
(From latched to
transparent; Not
Internal Control
Mode)

20

Internal Control
Mode: LEOIAG
(From latched
to transparent)

24

33

24

27

Internal Control
Mode: DATA0-15
(Via Diagnostic
Latch)

24

33

24

27

22

91)).l<

20

<>......

16

{U;!
16

»

.

<'i;~{{

2595 tbl43

MAXIMUM OUTPUT ENABLE/DISABLE TIMES

<»

Output tests specified with CL = SpF and measured to O.SV
change of output voltage level. Test performed with CL = SOpF
and correlated to CL = SpF.

.«223< :./ 24

.:,i:ii~{{

I»

22

28•••••••••.••••••••••·
...........•........

!if':,,:I:;;:
28

Input

Output

Enable
Max.

Disable
Max.

OE BYTEo,
OE BYTE1

DATA0-15

12

10

OEsc

SC0-6

12

10

.....•.....

-

20

22

2595 tbl44

MINIMUM PULSE WIDTHS

I

LEIN, LEoUT, LEOIAG

I

8

NOTE:
2595 tbl42
1. DATA IN to corrected DATAoUT measurement requires timing as shown
below.

5.10

I

2595 tbl45

24

IDT39C60/·1/A/B
16·BIT CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

NOTES:
Device Mode = "Correct"
System Type = "Correct Always"
Min. Period = 51 ns (fMAX = 19.6MHz)

IDT39C60B COMMERCIAL - DATAIN TO CORRECTED
DATAoUT TIMING (Two C cles shown)
OEBYTE

J

"

1.=21
25

Timing Parameter
From
To

Min.!
Max.

OEBYTE = High to DATAoUT Disabled
OEBYTE = Low to DATAoUT Enabled
DATAIN to Corrected DATAoUT

Max.
Max.
Max.

DATAIN Set·up to LEIN = Low
DATAIN Hold to LEIN = Low

Min.
Min.

LEIN = High to DATAoUT
• = (Memory/System dependent)

Max .

_-..J/

/

DATA Bus

LEIN

to

to

to

2595 drw 12

II

5.10

25

IDT39C60/-1/A1B
16-BIT CMOS DETECTION AND CORRECTION UNIT

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C60A AC ELECTRICAL
CHARACTERISTICS
(Guaranteed Commercial Range Performance)
The tables below specify the guaranteed performance of
the IDT39C60A over the commercial operating range of O°C
to +70°C, with Vcc from 4.7SV to S.2SV. All data are in
nanoseconds, with inputs switching between OV and 3Vat 1V
per nanosecond and measurements made at 1.SV.

MINIMUM SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES

MAXIMUM COMBINATIONAL PROPAGATION
DELAYS CL = SOpF

To

Set-up
Time

Hold
Time

LEoUT

5
5
24
21

3
3
2
0

CB0-6
(CODE 10

LEoUT

21

0

22
22
22
25
28
5

0
0
0
0
0
3

To Output
From Input
DATA0-15
CB0-6
(CODE ID2-{)

SC~

DATA0-15

Error

MULT
ERROR

20
14

30(1)

20
20

23
23

25

DATA0-15

LEIN

CB0-6

LEIN

DATA0-15

LEoUT

CB0-6
(CODE ID

000,011)
CB0-6
(CODE ID2-{) 010,

14

18

20

(Latching Data)

From Input

23

000, 011)

010. 100.
101.110.111)

100.101.110.111)
GENERATE

15

-

-

-

CORRECT

LEoUT

CORRECT
(Not Internal
Control Mode)

-

20

-

-

DIAG MODE

LEoUT

PASSTHRU

LEoUT

DIAG MODE
(Not Internal
Control Mode)

22

25

18

21

CODE ID2-{)

LEoUT

LEIN

LEoUT

DATA0-15

LEDIAG

PASSTHRU
(Not Internal
Control Mode)

22

25

18

21

CODE 102-0

23
22

28
32

25
22

28
25

LEoUT
(From latched
to transparent)

-

13

-

-

LEOIAG
(From latched to
transparent; Not
Internal Control
Mode)

22

32

22

25

Internal Control
Mode: LEDIAG
(From latched
to transparent)

28

38

28

31

Internal Control
Mode: DATA0-15
(Via Diagnostic
Latch)

28

38

28

31

LEIN
(From latched
to transparent)

NOTE:

25951b147

MAXIMUM OUTPUT ENABLE/DISABLE TIMES
Output tests specified with CL = SpF and measured to O.SV
change of output voltage level. Test performed with CL =SOpF
and correlated to CL = SpF.
Output

Enable

Disable

OE BYTEo.
OE BYTE1

DATA0-15

24

21

OEsc

SC0-6

24

21

Input

2595 tbl48

MINIMUM PULSE WIDTHS

I

LEIN, LEoUT. LEo lAG

12

I

25951b149

2595 tbl46

1. DATAIN to corrected DATAoUT measurement requires timing as shown
below.

5.10

26

IDT39C60/·1/AIB
16-BIT CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

NOTES:
Device Mode = "Correct"
System Type = "Correct Always"
Min. Period = 61 ns (fMAX = 16.4MHz)

IDT39C60A COMMERCIAL - DATAIN TO CORRECTED
DATAOUT TIMING (Two c cles shown)
OEBYTE

J

"
~24
30

/

-----/

Timing Parameter
From
To

Min.!
Max.

OEBYTE = High to DATAoUT Disabled
OEBYTE = Low to DATAoUT Enabled
DATAIN to Corrected DATAoUT

Max.
Max.
Max.

DATAIN Set-up to LEIN = Low
DATAIN Hold to LEIN = Low

Min.
Min.

= High to DATAoUT

Max .

DATA Bus

LEIN
LEIN

• = (Memory/System dependent)

to

to

to

2595 drw 13

II

5.10

27

I DT39C60/-1/AlB
16-BIT CMOS DETECTION AND CORRECTION UNIT

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C60A AC ELECTRICAL
CHARACTERISTICS
(Guaranteed Military Range Performance)
The tables below specify the guaranteed performance of
the IOT39C60A over the military operating range of -55°C to
+125°C, with Vee from 4.SV to S.SV. All data are in
nanoseconds, with inputs switching between OV and 3V at 1V
per nanosecond and measurements made at 1.SV.

MAXIMUM COMBINATIONAL PROPAGATION
DELAYS CL = SOpF

MINIMUM SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES

To Output
ERROR

DATA0-15

22

DATA0-15
35(1)

MULT
ERROR

24

27

CB0-6
(CODE 102-0
000,011)

17

28

24

27

CB0-6
(CODE 102-0010,
100,101,110,111)

17

GENERATE
CORRECT
(Not Internal
Control Mode)

From Input

SC0-6

20

24

27

20

-

-

25

-

-

DIAG MODE
(Not Internal
Control Mode)

25

PASSTHRU
(Not Internal
Control Mode)

25

28

21

24

CODE ID2-O

26

31

28

31

LEIN
(From latched
to transparent)

24

37

26

29

LEoUT
(From latched
to transparent)

-

16

-

-

LEolAG
(From latched to
transparent; Not
Internal Control
Mode)

24

37

26

29

Internal Control
Mode: LEDIAG
(From latched
to transparent)

30

43

32

35

Internal Control
Mode: DATA0-15
(Via Diagnostic
Latch)

30

43

32

35

NOTE:

28

21

To
(Latching Data)

From Input

24

Set-up
Time

Hold
Time

DATA0-15

LEIN

5

3

CB0-6

LEIN

5

3

DATA0-15

LEoUT

27

2

CB0-6
(CODE ID 000, 011)

LEoUT

24

0

CB0-6
(CODE ID 010, 100,
101,110,111)

LEoUT

24

0

CORRECT

LEoUT

25

0

DIAG MODE

LEoUT

25

0

PASSTHRU

LEoUT

25

0

CODE ID2-O

LEoUT

28

0

LEIN

LEoUT

30

0

DATA0-15

LEolAG

5

3
25951b151

MAXIMUM OUTPUT ENABLE/DISABLE TIMES
Output tests specified with CL = SpF and measured to O.SV
change of output voltage level. Test performed with CL= SOpF
and correlated to CL = SpF.
Output

Enable

Disable

OE BYTEo,
OE BYTE1

DATA0-15

28

25

OEsc

SC0-6

28

25

Input

25951b152

MINIMUM PULSE WIDTHS

I

LEIN, LEoUT, LEOIAG

12
25951b153

25951b150

1. DATAIN to corrected DATAoUT measurement requires timing as shown
below.

5.10

28

IDT39C60/·1/AIB
16·81T CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

NOTES:
Device Mode = "Correct"
System Type = "Correct Always"
Min. Period = 70ns (fMAX = 14.3MHz)

IDT39C60A MILITARY - DATAIN TO CORRECTED
DATAoUT TIMING (Two C cles shown)
OEBYTE

J

"
1.=28

/

Timing Parameter
From
To

Min.!
Max.

OEBYTE = High to DATAoUT Disabled
OEBYTE = Low to DATAoUT Enabled
DATAIN to Corrected DATAoUT

Max.
Max.
Max.

DATAIN Set-up to LEIN = Low
DATAIN Hold to LEIN = Low

Min.
Min.

LEIN = High to DATAoUT

Max .

__..J/

35

DATA Bus

LEIN
• = (Memory/System dependent)

to

to

to

2595 drw '4

II

5.10

29

IDT39C60/-1/A1B
16-BIT CMOS DETECTION AND CORRECTION UNIT

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C60-1 AC ELECTRICAL
CHARACTERISTICS
(Guaranteed Commercial Range Performance)
The tables below specify the guaranteed performance of
the IDT39C60-1 overthe commercial operating range of O°C
to +70°C, with Vce from 4.7SV to S.2SV. All data are in
nanoseconds, with inputs switching between OV and 3V at 1V
per nanosecond and measurements made at 1.SV.

MAXIMUM COMBINATIONAL PROPAGATION
DELAYS CL = SOpF

MINIMUM SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES

To Output

To
(Latching Data)

From Input

MULT

Set-up
Time

Hold
Time
7

ERROR

DATA0-15

LEIN

6

28

DATAO-15
52(1)

ERROR

DATA0-15

25

50

CBo..o

LEIN

5

6

CBo..o
(CODE ID2-O
000, all)

23

50

23

47

DATA0-15

LEoUT

34

5

CBo..o
(CODE ID 000, all)

LEoUT

35

a

CBo..o
(CODE ID2-O 010,
100,101,110,111)

28

CBo..o
(CODE ID 010, 100,
101,110,111)

LEoUT

27

a

GENERATE
CORRECT
(Not Internal
Control Mode)

From Input

SCo.-a

34

29

34

35

-

CORRECT

LEoUT

26

1

45

-

-

-

-

DIAG MODE

LEoUT

69

a

PASSTHRU

LEoUT

26

0

75

CODE ID2-O

LEoUT

81

a

LEIN

LEoUT

51

5

DATA0-15

LEolAG

6

DIAG MODE
(Not Internal
Control Mode)

50

PASSTHRU
(Not Internal
Control Mode)

36

44

29

46

CODE ID2-O

61

90

60

80

LEIN
(From latched
to transparent)

39

72

39

59

LEoUT
(From latched
to transparent)

-

31

-

-

LEolAG
(From latched to
transparent; Not
Internal Control
Mode)

45

78

45

65

Internal Control
Mode: LEDIAG
(From latched
to transparent)

67

96

66

86

Internal Control
Mode: DATA0-15
(Via Diagnostic
Latch)

67

96

66

86

NOTE:

78

59

8
25951b155

MAXIMUM OUTPUT ENABLE/DISABLE TIMES
Output tests specified with CL = SpF and measured to O.SV
change of output voltage level. Test performed with CL= SOpF
and correlated to CL = SpF.
Output

Enable

Disable

OE BYTEo,
OE BYTE1

DATA0-15

30

30

OEsc

SC0-6

30

30

Input

25951b156

MINIMUM PULSE WIDTHS

I

LEIN, LEoUT, LEolAG

15

I

25951b157

2595 Ibl 54

1. DATAIN to corrected DATAoUT measurement requires timing as shown
below.

5.10

30

IDT39C60/·1/Al8
16·81T CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

NOTES:
Device Mode = "Correct"
System Type = "Correct Always"
Min. Period = 92ns (fMAX = 10.9MHz)

IDT39C60-1 COMMERCIAL - DATAIN TO CORRECTED
DATAoUT TIMING (Two C cles shown)

Timing Parameter
From
To

Min.!
Max.

OEBYTE = High to DATAoUT Disabled
OEBYTE = Low to DATAoUT Enabled
DATAIN to Corrected DATAoUT

Max.
Max.
Max.

DATAIN Set-up to LEIN = Low
DATAIN Hold to LEIN = Low

Min.
Min.

LEIN = High to DATAoUT
• = (Memory/System dependent)

Max .

DATA Bus

LEIN

to

to

to

2595 drw 15

II

5.10

31

I DT39C60/-1/AlB
16-BIT CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C60-1 AC ELECTRICAL
CHARACTERISTICS
(Guaranteed Military Range Performance)
The tables below specify the guaranteed performance of
the IDT39C60-1 over the military operating range of -55°C to
+125°C, with Vee from 4.5V to 5.5V. All data are in
nanoseconds, with inputs switching between OV and 3V at 1V
per nanosecond and measurements made at 1.5V.

MINIMUM SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES

MAXIMUM COMBINATIONAL PROPAGATION
DELA YS CL = 50pF

To
(Latching Data)

To Output
From Input

Set-up
Time

Hold
Time
7

ERROR

DATA0--15

LEIN

7

DATA0--15

31

DATA0-15
59(1)

MULT
ERROR

28

56

CB0-6

LEIN

5

7

CB0-6
(CODE 102--0
000,011)

25

55

25

50

DATA0--15

LEoUT

39

5

CB0-6
(CODE 10 000, all)

LEoUT

38

a

CB0-6
(CODE 102--0 010,
100,101,110,111)

30

CB0-6
(CODE 10 010, 100,
101,110,111)

LEoUT

30

a

GENERATE
CORRECT
(Not Internal
Control Mode)

From Input

SCG-6

38

31

37

38

-

-

LEoUT

28

1

49

-

CORRECT

-

DIAG MODE

LEoUT

84

a

PASSTHRU

LEoUT

30

a

DIAG MODE
(Not Internal
Control Mode)

58

89

65

90

CODE 102--0

LEoUT

89

0

LEIN

LEoUT

59

5

DATA0--15

LEolAG

7

PASSTHRU
(Not Internal
Control Mode)

39

51

34

54

MAXIMUM OUTPUT ENABLE/DISABLE TIMES

CODE 102-0

69

100

68

90

LEIN
(From latched
to transparent)

39

82

43

66

LEoUT
(From latched
to transparent)

-

33

-

-

LEolAG
(From latched to
transparent; Not
Internal Control
Mode)

50

88

49

72

Internal Control
Mode: LEolAG
(From latched
to transparent)

75

106

74

96

Internal Control
Mode: DATA0--15
(Via Diagnostic
Latch)

75

106

74

96

NOTE:

9
2595 1b159

Output tests specified with CL = 5pF and measured to O.5V
change of output voltage level. Test performed with CL = 50pF
and correlated to CL = 5pF.
Output

Enable

Disable

OE BYTEo,
OE BYTE1

Input

DATA0--15

35

35

OEsc

SC0-6

35

35
2595 IbIGO

MINIMUM PULSE WIDTHS

I

LEIN, LEoUT, LEolAG

15
2595 IblG1

2595 1b158

1. DATAIN to corrected DATAoUT measurement requires timing as shown
below.

5.10

32

IDT39C60/·1/A/B
16·BIT CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

NOTES:
Device Mode = "Correct"
System Type = "Correct Always"
Min. Period = 1 04ns (fMAX = 9.6MHz)

IDT39C60-1 MILITARY - DATAIN TO CORRECTED
DATAOUT TIMING (Two C cles shown)
OEBYTE

J

"

Timing Parameter
From
To

Min.!
Max.

OEBYTE = High to DATA OUT Disabled
OEBYTE = Low to DATAoUT Enabled
OATAIN to Corrected OATAOUT

Max.
Max.
Max.

DATAIN Set-up to LEIN = Low
DATAIN Hold to LEIN = Low

Min.
Min.

LEIN = High to DATAouT
• = (Memory/System dependent)

Max .

_--.J/

/

1..=35
59
DATA Bus

LEIN

to

to

to

2595 drw 16

II

5.10

33

IDT39C60/·1/AIB
16-BIT CMOS DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C60 AC ELECTRICAL
CHARACTERISTICS
(Guaranteed Commercial Range Performance)
The tables below specify the guaranteed performance of
the IDT39C60 overthe commercial operating range of O°C to
+70°C, with Vcc from 4.75V to 5.25V. All data are in
nanoseconds, with inputs switching between OV and 3V at 1 V
per nanosecond and measurements made at 1.5V.

MINIMUM SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES

MAXIMUM COMBINATIONAL PROPAGATION
DELAYS CL = 50pF

To
(Latching Data)

To Output
From Input

Set-up
Time

Hold
Time
7

ERROR

DATA0-15

LEIN

6

DATA0-15

32

DATA0-15
65(1)

MULT
ERROR

32

50

CB0-6

LEIN

5

6

CB0-6
(CODE ID2...-____________
~, -<
....

~XXXXXX-"""""'<""""'l~r--x-

~sc = High to SCOUT Disabled
Nsc = High to SCOUT Disabled
~sc = Low to SCOUT Enabled
OEsc = Low to SCOUT Enabled
Valid Checkblts

xxxxxxxxxxxxxxxx>

(Check Bits Exit)

(Don't Care)

NOTES:
1. BOLD indicates critical parameters.
2. Valiid "DATA" and valid CBIN" are shown to occur simultaneously, since both buses are latched and opened by the "LEIN" input.
• Assumes DATA bus becomes input 4ns before LEIN goes high.

5.11

Min.
Max.
Min.
Max.

2584 drw 09

30

I

lOT49C460/ AlB/C/O
32·BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SET-UP AND HOLD TIMES AND MENIMUM PULSE WIDTHS

Of

CBIN

zzxz~~:~xxxxxx

LEIN.

31.-3

Set·up/Hold Time
With Respect To

Min.lMax.

CBIN Set-up to LEIN = Low
CBIN Hold to LEIN = Low

Min.
Min.

LEIN width

Min.

·LEIN = High to LEouT/GEN = Low·
DATA Set-up to LEIN = Low
DATA Hold to LEIN = Low

Min.
Min.
Min.

CBIN Set-up to LEoUT/GEN = Low
CBIN Set-up to LEoUT/GEN = Low
DATA Set-up to LEoUT/GEN = Low

Min.
Min.
Min.

LEoUT/GENERATE Width

Min.

CORRECT Set-up to
LEoUT/GEN = Low

Min.

DATAIN

LEoUT/GEN

CORRECT

NOTES:
2584 drw 11
1. BOLD indicates critical parameters.
• Enable to enable timing requirement to ensure that the last DATA word applied to "DATAIN" is made available as DATAouT"; assumes that "DATAIN"
is valid at least 4ns before "LEIN" goes high.

5.11

31

IDT49C460/Al8/C/D

MILITARY AND COMMERCIAL TEMPERATURE RANGES

32-81T CMOS ERROR DETECTION AND CORRECTION UNIT

INPUT/OUTPUT INTERFACE CIRCUIT
Vee

ESD
PROTECTION
IIH

~

INPUTSLr----------~~

OUTPUTS

~

IlL

2584 drw 12

2584 drw 13

Figure 5. Input Structure (All Inputs)
Figure 6. Out put Structure

TEST LOAD CIRCUIT

II
DEFINITIONS:
= Load capacitance: includes jig and probe capacitance
RL = Termination resistance: should be equal to ZOUT of the Pulse Generator

CL

Figure 7.

AC TEST CONDITIONS
Input Pulse Levels

GND to 3.0V

Test

Switch

Input Rise/Fall Times

1V/ns

Open Drain

Closed

Input Timing Reference Levels

1.5V

Disable Low

Output Reference Levels
Output Load

1.5V

Enable Low

See Figure 7

All other Outputs
2584 tbl69

5.11

Open
2584 tbl6S

32

lOT49C4601AlB/C/O
32·BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

49C460
Device type

x

Speea

X

"'J5aCKage

x
Processl
Temperature
Range

BLANK
B

Commercial (O°C to + 70°C)
Military (- 55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Pin Grid Army
Plastic Leaded Chip Carrier
Ceramic Quad Flatpack (For Military Only)

Blank

.....-------------------4:

5.11

A
B
C
D

Standard Speed
High-Speed
Very High-Speed
Ultra-High-Speed
Fastest Speed

49C460

32-Bit E. D. C.

2584 drw15

33

(;)®

PRELIMINARY
IDT49C465

32-81T FLOW-THRU
ERROR DETECTION
AND CORRECTION UNIT

Integrated Device Technology, Inc.

FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

DESCRIPTION
n

The IDT49C46S is a 32-bit, two-data bus, Flow-thruEDC
unit. The chip provides single-error correction and multipleerror detection of both hard and soft memory errors. It can be
expanded to 64-bit widths by cascading 2 units, without the
need for additional external logic. The Flow-thruEDC has
been optimized for speed and simplicity of control.
The EDC unit has been designed to be used in either of two
configurations in an error correcting memory system. The
bi-directional configuration is most appropriate for systems
using bi-directional memory buses. A second system
configuration utilizes external octal buffers and is particularly
well suited for systems using memory with separate I/O
buses.

32-bit wide Flow-thruEDC • unit
Expandable to 64 bits
Single-chip 64-bit Generate Mode
Separate system and memory buses
On-chip pipeline latch with external control
Supports bi-directional and common I/O memories
Corrects all single-bit errors
Detects all double-bit errors, some multiple-bit errors
Error Detection Time - 1Sns
Error Correction Time - 20ns
Internal syndrome register
Four-bit error counter and error-data register on-chip
Parity generation and checking on system data bus
Low power CMOS - 1OOmA typical
144-pin PGA package
Military product compliant to MIL-STD 883, Class B

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

II

M00-31

MO
Latch

Correct
Logic
Memory
Checkblt
Generator

MLE

CBl0-7

D

c

o

Mux

·;

:z:

m

Z

II
II

::!

0

Z

-l

II

0

m
m

l>
r

()

r

0

z
>
Z

()

0

"C

II
:D

(.)

'"

~

II
C

»
MD~I

Oc.n
-l

m

SOE

,en
"T'I"'"

'TI
C

0

PLELJ~+------------------------------.

'-l

[0"",

c

()

J MUX

W-

:::0

l>

:s:

-l

(5

()

0

m
()

-l

(5
Z

c

z

=i

; ;
MOE

SLE

0

II

AFo~

jt

::

PSEL LJ>--+--+-----,

;=

~

:D

'V

P~

1

~ J

:>

;t

~

L>

I.--------II-CJ

CBOH

CBOE

PERR

-<

>
Z
o

()

o

::
:::

m

:D

L-------------------------------------------------------------~------~/~/----4.~CJ PCBI~7

IERFlOR

SYNCLK

LJ;:::d

SCLKEN

o--------J-

CLEAR

INTERNAL SYNCLK

,X;

-l

m

::
"'C

D------.

m

:D

>
-l

CODEIDO.1~

C
:D

~MODE~2~
w

()

m

1(;

:D

>
Z

~

G')

~

m

(fl

II

IDT49C465
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SYSTEM CONFIGURATIONS
The IDT49C465 EDC unit can be used in various
configurations in an EDC system. The basic configurations
are shown below.
Figure 1 illustrates a bi-directional configuration, which is
most appropriate for systems using bi-directional memory
buses. It isthe simplest configuration to understand and use.
During a correction cycle, the corrected data word can be
simultaneously output on both the system bus and memory
bus. Logically, no other parts are required for the correction
function. During partial-word-write operations, the new bytes
are internally combined with the corrected old bytes for
checkbit generation and writing to memory.

CPU
I/O

so

Figure 3 illustrates a third configuration which utilizes
external buffers and is also well suited for systems using
memory with separate I/O buses. Since data from memory
does not need to pass through the part on every cycle, the
EDC system may operate in "bus-watch" mode. As in the
separate I/O configuration, corrected data is output on the SD
outputs.

MEMORY
INPUT BUS

MEMORY
OUTPUT BUS

MO \ 4 - - _ MEMORY
I/O
EOC
2552 drw 07

CBI
CBOI----

CHECKBITS
Figure 3. Bypassed Separate 1/0 Configuration
2552 drw 05

Figure 1. Bi-Directional Configuration

Figure 2 illustrates a separate I/O configuration. This is
appropriate for systems using separate I/O memory buses.
This configuration allows separate input and output memory
buses to be used. Corrected data is output on the SO outputs
forthe system and for re-write to memory. Partial word-write
bytes are combined externally for writing and checkbit
generation.

Figure 4 illustrates the single-chip generate-only mode for
very fast 64-bit checkbit generation in systems that use
separate checkbit-generate and detect-correct units. If this is
not desired, 64-bit checkbit generation and correction can be
done with just 2 EDC units. 64-bit correction is also straightforward, fast and requires no extra hardware for the
expansion.

CHECK
BITS OUT
CPU

CHECK
BITS IN

MEMORY
INPUT BUS

m
x
:-i

MEMORY
INPUTS

CBO

EOC
MEMORY
OUTPUTS

CHECKBITS

CPU BUS

CBO

2552 drwOB

2552 drw 06

Figure 4. Separate Generate/Correction Units
with 64-Bit Checkblt Generation

Figure 2. Separate 1/0 Configuration

5.12

4

IDT49C465
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION
The error detection/correction codes consist of a modified
Hamming code; it is identical to that used on the IDT49C460.

32-BIT MODE (CODE ID 1,0=00)
Vee

LpCBI

/ CHECKBITS-OUT
CBO

7

CBI7

CHECKBITS-IN

7

CBlo-6

SYO

"7 SYNDROME-OUT
EDC

2552 drw 09

Figure 5. 32-Blt Mode

64-BIT MODE (CODE ID 1,0=10 & 11)
The expansion bus topology is shown in Figure 6. This
topology allows the syndrome bits used by the correction logic
to be generated simultaneously in both parts used in the
expansion. During a 64-bit detection or correction operation,

"Partial-Checkbit" data and "Partial-Syndrome" data is simultaneously exchanged between the two EDC units in opposite
directions on dedicated expansion buses. This results in very
short 64-bit detection and correction times.

8 PARTIAL-CHECKBITS-OUT (11)
(CORRECTION ONLY)

~

PCBI

CBO

8 PARTIAL-CHECKBITS-OUT (10)

PCBI

CBO

CBI

SYO

-

8

FINAL
CHECKBITS-O UT

(GENERATE ONLY)
CHECKBITS-IN

8

CBI

SYO

8 PARTIAL-SYNDROME

-

(DETECT/CORRECT ONLY)
LOWER EDC

ERR
UPPER EDC

(CODE 10 1,0 = 10)

(CODE 101,0 = 11)

Figure 6. 64-Bit Mode -

(DETECT AND CORRE CT)
2552 drw 10

2 Cascaded IDT49C465 Devices

64-BIT GENERATE-ONLY MODE (CODE ID 1,0=01)
If the Identity pins CODE ID 1 ,0 = 01, a single EDC is placed
in the 64-bit "Generate-only" mode. In this mode, the lower 32
bits of the 64-bit data word enter the device on the SDO-31
inputs. This provides the device with the full 64-bit word from

LOWER 32 BITS (0-31)

--,L
........_~

UPPER 32 BITS (32-63)

--,........
/_-I_~

memory. The resultant generated checkbits are output on the
CBOO-70Utputs. The generate time is less than that resulting
from using a 2-chip cascade.

MDo-31

" 32

CHECKBITS-OUT
SDo-31

" 32

EDC

2552 drw

11

Figure 7. 64-Bit "Generate-Only" Mode (Single Chip)

5.12

5

II

IDT49C465
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTIONS
Symbol

1/0

Name and Function

1/0 Buses and Controls
SOO-7
S08-15
S016-23
S024-31

110

SLE

System Data Bus: Data from MOO-31 appears at these pins corrected if MODE 2-0 = x11, or uncorrected in the other modes. The BEn inputs must be high and the SOE pin must be low to enable the SO
output buffers during a read cycle. (Also, see diagnostic section.)
Separate 1/0 memory systems: In a write or partial-write cycle, the byte not-to-be-modified is output on
SOn to n+ 7 for re-writing to memory, if BEn is high and SOE is low. The new bytes to be written to memory
are input on the SOn pins, for writing checkbits to memory, if BEn is low.
BI-directional memory systems: In a write or partial-write cycle, the byte not-to-be-modified is re-directed
to the MO 1/0 pins, if BEn is high, for checkbit generation and rewriting to memory via the MO 1/0 pins. SOE
must be high to avoid enabling the output drivers to the system bus in this mode. The new bytes to be written
are input on the SOn pins for checkbit generation and writing to memory. BEn must be low to direct input
data from the System Data bus to the MO 1/0 pins forcheckbit generation and writing to the checkbit memory.
System Latch Enable: SLE is an input used to latch data at the SO inputs. The latch is transparent when
SLE is high; the data is latched when SLE is low.
Pipeline Latch Enable: PLE is an input which controls a pipeline latch, which controls data to be output
on the SO bus and the MO bus during byte merges. Use of this latch is optional. The latch is transparent
when PLE is low; the data is latched when PLE is high.
System Output Enable: When low, enables System output drivers and Parity output drivers if corresponding Byte Enable inputs are high.

BEo-3

MOO-31

Byte Enables: In systems using separate 1/0 memory buses, BEn is used to enable the SO and Parity
outputs for byte n. The BEn pins also control the "Byte mux". When BEn is high, the corrected or uncorrected
data from the Memory Data latch is directed to the MO 1/0 pins and used for checkbit generation for byte
n_ This is used in partial-word-write operations or during correction cycles. When BEn is low, the data from
the System Data latch is directed to the MO 1/0 pins and used for checkbit generation for byte n.
BEo controls SOO-7
BE2 controls S016-23
BE1 controls S08-15
BE3 controls S024-31

1/0

MLE

Memory Data Bus: These 1/0 pins accept a 32-bit data word from main memory for error detection and/
or correction. They also output corrected old data or new data to be written to main memory when the EOC
unit is used in a bi-directional configuration.
Memory Latch Enable: MLE is used to latch data from the MO inputs and checkbits from the CBI inputs.
The latch is transparent when MLE is high; data is latched when MLE is low. When identified as the upper
slice in a 64-bit cascade, the checkbit latch is bypassed.
Memory Output Enable: MOE enables Memory Data Bus output drivers when low.

PO-3

I/O

PSEL

Parity 1/0: The parity 1/0 pins for Bytes 0 to 3. These pins output the parity of their respective bytes when
that byte is being output on the SO bus. These pins also serve as parity inputs and are used in generating
the Parity ERRor (PERR) signal under certain conditions (see Byte Enable definition). The parity is odd or
even depending on the state of the Parity SELect pin (PSEL).
Parity SELect:

If the Parity SELect pin is low, the parity is even.
If the Parity SELect pin is high, the parity is odd.

Inputs
CB10-7

I

CheckBits-ln (00)
CheckBits-ln-1 (10)
Partial-Syndrome-In (11):
In a single EOC system or in the lower slice of a cascaded EOC system, these inputs accept the checkbits
from the checkbit memory. In the upper slice in a cascaded EOC system, these inputs accept the "PartialSyndrome" from the lower slice (Oetect/Correct path).

PCBI0-7

I

Partial-CheckBits-ln (10)
Partial-CheckBits-ln (11):
In a single EOC system, these inputs are unused but should not be allowed to float. In a cascaded EOC
system, the "Partial-Checkbits" used by the lower slice are accepted by these inputs (Correction path only).
In the upper slice of a cascaded EOC system, "Partial-Checkbits" generated by the lower slice are accepted
by these inputs (Generate path).

CODE 101,0

I

CODE IDentity: Inputs which identify the slice positionl functional mode of the IOT49C465.
(10) Lower slice of a 64-bit cascade
(00) Single 32-bit EOC unit
(01) 64-bit "Checkbit-generate-only" unit
(11) Upper slice of a 64-bit cascade
2552 tbl

5.12

6

01

IDT49C465
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTIONS (Con't.)
Symbol

1/0

Name and Function

Inputs ~Con't-1
MODE 2-0

I

MODE select: Selects one of four operating modes.
(x11)
(x10)
(000)

(x01)

(100)

"Normal" Mode: Normal EDC operation (Flow-thru correction and generation).
"Generate-Detect" Mode: In this mode. error correction is disabled. Error generation and detection are
normal.
"Error-Data-Output" Mode: Allows the uncorrected data captured from an error event by the Error-Data
Register to be read by the system for diagnostic purposes. The Error-Data Register is cleared by toggling
CLEAR low. The Syndrome Register and Error-Data Register record the syndrome and uncorrected data
from the first error that occurs after they are reset oy the CLEAR pin. The Syndrome Register and ErrorData Register are updated when there is a positive edge on SYNCLK, an error condition is indicated (ERROR
= low). and the Error Counter indicates zero.
AII-Zero-Oata Source: In Error-Data-Output Mode. clearing the Error-Data Register provides a source of
all-zero-data for hardware initialization of memory. if this desired.
~iagnostic-Output Mode: In this mode, the contents of the Syndrome Register, Error Counter and ErrorType Register are output on the SO bus. This allows the syndrome bytes for an indicated error to be read
by the system for error-logging purposes. The Syndrome Register and the Error-Data Register are updated
when there is a positive edge on SYNCLK, an error condition is indicated and the Error Counter indicates
zero errors. Thus, the Syndrome Register saves the syndrome that was present when the first error occurred
after the Error Counter was cleared. The Syndrome Register and the Error Counter are cleared by toggling
CLEAR low. The Error Counter lets the system tell if more than one error has occurred since the last time
the Syndrome Register or Error-Data Register was read.
Checkbit-Injection Mode: In the "Checkbit-Injection" Mode, diagnostic checkbits may be input on System
Data Bus bits 0-7 (see Diagnostic Features - Detailed Description).
CLEAR: When the CLEAR pin is taken low, the Error-Data Register, the Syndrome Register, the Error
Counter and the Error-Type Register are cleared.

SYNCLK

SYNdrome CLocK: If ERROR is low. and the Error Counter indicates zero errors, syndrome bits are clocked
into the Syndrome Register and data from the outputs of the Memory Data input latch are clocked into the
Error-Data Register on the low-to-high edge of SYNCLK. If ERROR is low, the Error Counter will increment
on the low-to-high edge of SYNCLK, unless the Error Counter indicates fifteen errors.
SynCLK ENable: The SCLKEN enables the SYNCLK signal. SYNCLK is ignored if SCLKEN is high.

Outputs and Enables
CBOo-7

0

CheckBits-Out (DO, 01)
Partial-CheckBits-Out (10)
Checkbits-Out (11):
In a single EDC system. the checkbits are output to the checkbit memory on these outputs. In the lower slice
in a cascaded EDC system, the "Partial-checkbits" used by the upper slice are output by these outputs
(Generate path only). In the upper slice in a cascade, the "Final-Checkbits" appear at these outputs
(Generate path only).

CBOE

I

SYOO-7

o

SYndrome-Out (00)
Partial-SYndrome-Out (10)
Partial-Checkbits-Out (11):
In a 32-bit EDC system, the syndrome bits are output on these pins. In the lower slice in a 64-bit cascaded
system, the "Partial-Syndrome" bits appear at these outputs (Detect! Correct path). In the upper slice in a
cascaded EDC system, the "Partial-Checkbits" appear at these outputs (Correct path only). In a 64-bit
cascaded system, the "Final-Syndrome" may be accessed in the "Diagnostic-Output" Mode from either the
lower or the upper slice since the final syndrome is contained in both.

ERR

o

ERROR: When in "Normal" and "Detect only" modes, a Iowan this pin indicates that one or more errors have
been detected. ERR is not gated or latched internally.

o

Multiple ERRor: When in "Normal" and "Detect only" modes, a low on this pin indicates that two or more
errors have been detected. MERR is not gated or latched internally.
Parity ERRor: A low on this pin indicates a parity error which has resulted from the active bytes defined by
the 4 Byte Enable pins. Parity ERRor (PERR) is not gated or latched internally (see Byte Enable definition).

o

CheckBits Out Enable: Enables CheckBit Output drivers when low.

Power Supply Pins
Vce 1-10
GND1-12

P
P

+5 Volts
Ground
25521b102

5.12

7

II

IDT49C465
32-81T FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DIAGNOSTIC DATA FORMAT (SYSTEM BUS)
Data Out (Unlatched)

Latched Data

I

,I

Error
Counter

Error
Re·
Type served

Syndrome bits

Byte 3
3

S \ M \ - \ - \2 \2
31

2827

Partial Checkbits
Byte 1

Byte 2
2

1
\ 2 \

Checkbits
Byte 0

2° 7\ 61514j 3\2J 110 7\6\5\4\3\2\1\0 7\6\5\4\3121110
2423
o
1615
8 7
2552 drw 12

DIAGNOSTIC FEATURES -

DETAILED DESCRIPTION

Mode 2-0
x11

"NORMAL" Mode
In this mode, operation is "Normal" or non-diagnostic.

x10

"GENERATE-DETECT" Mode
When the EDC unit is in the "Generate-Detect" Mode, data is not corrected or altered by the error correction network.
(Also referred to as the "Detect-only" Mode.)

000

"ERROR-DATA-OUTPUT" Mode
In this mode, the 32-bit data from the Error-Data Register is output on the SD bus.
Error Data Register: The uncorrected data from the Memory Data bus input latch is stored in the Error-Data Register
if the error counter contents indicates "0" and there is a positive transition on the SYNCLK input when the ERROR signal
is low. Thus, the Error-Data Register contains memory data corresponding to the first error to occur since the register was
cleared. This register is cleared by pulling the CLEAR input low. The register is read via the System Data bus by entering
the "Error-Data-Output" Mode and enabling the System Data bus output drivers.
AII-Zero-Data: The Error-Data Register can be used as an "all-zero-data" data source for memory initialization in systems
where the initialization process is to be done entirely by hardware.

x01

"DIAGNOSTIC-OUTPUT" Mode
In this mode, data from the diagnostic registers, the PCBI bus and the CBI bus is output on the SD bus.
Direct Checkbit Readback: Internal data paths allow both the "Partial-CheckBit-lnput" bus and the data in the "CheckBitInput" latch to be read directly by the system bus for diagnostic purposes. Both the Checkbit Input Bus and the Partial
Checkbit Input Bus are read via the System Data bus by entering the "Diagnostic-Output" Mode and enabling the System
Data bus output drivers. The checkbits are output on System Data bus bits 0-7; the Partial Checkbits are output on bits
8-15.
Syndrome Register: After an error has been detected, the syndrome bits generated are clocked into the internal
Syndrome Register if the error counter contents indicates "0" and there is a positive transition on the SYNCLK input when
the ERROR signal is low. This register is cleared by pulling the CLEAR input low. The register is read via the System Data
bus by entering the "Diagnostic-Output" Mode and enabling the System Data bus outputs. This data is output on SD
bits 16-23.
Error Counter: The 4-bit on-board error counter is incremented if the error counter contents do not indicate FF HEX, which
corresponds to a count of 15, and there is a positive transition on the SYNCLK input when the ERROR signal is low. This
counter is cleared by pulling the CLEAR input low. The counter is read via the System Data bus by entering the
"Diagnostic-Output" Mode and enabling the System Data bus output drivers. This data is output on System Data bus
bits 24-27.
Test Register: These 2 bits are reserved for factory diagnostics only and must not be used by system software. This data
is output on System Data bus bits 28-29.
'
Error-Type Register: The Error-Type Register, clocked by the SYNCLK input, saves 2 bits which indicate whether a
recorded error was a single or a multiple-bit error. This register holds only the first error type to occur after the last Clear
operation. This data is output on System Data bus bits 30-31.

100

Direct Read-Path Checkbit Injection: In the "Checkbit-Injection" Mode, bits 0-7 of the System Data input latch are
presented to the inputs of the Checkbit Input latch. If MLE is strobed, the checkbit latch will be loaded with this value in
place of the checkbits from memory. By inserting various checkbit values, operation of the correction function of the EDC
can be verified "on-board". Except forthe "Checkbit-Injection"function, operation in this mode is identical to "Normal" Mode
operation.
25521b103

5.12

8

IDT49C465
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OPERATING MODE CHARTS
SLICE IDENTIFICATION
CODE 10 1

CODE ID 0

0
0
1
1

0
1
0
1

Slice Definition
32-bit
64-bit
64-bit
64-bit

Flow-Thru EDC
GENERATE Only EDC
EDC- Lower 32 bits (0-31)
EDC- Upper 32 bits (32-63)
2552 tbl 04

SLICE POSITION CONTROL
Checkbit Buses
Slice Position!
CODE Functional Operation
ID
r-1 0

f---

r-

SO Bus

SOE
Width

MOE

MD Bus
32

32

=

Single 32-bit EDC unit
Generate(1)
DetectlCorrect(2)

1
0

Sys.0-31
Pipe. latch

0
1

Sys. Byte Mux
MD 0-31

0 1

"64-bit Generate-only"

1

Sys.32-63

1

Sys.0-31

1 0

Lower word, 64-bit bus
Generate(1)
DetectlCorrect(2)

1
0

Sys.O-31
Pipe. latch

0
1

MD 0-31
MD 0-31

Upper word, 64-bit bus
Generate(1)
DetectlCorrect(2)

1
0

Sys.32-63
Pipe. latch

0
1

MD 32-63
MD 32-63

0 0

1 1

PCBI
Bus

CBI
Bus

CBO
Bus

SYO
Bus

P
Bus

8

8

8

8

4

-

CBs out

-

CBs in

U-SYOout
L-CBOout

-

-

-

CBs out

-

PCBs out

CBs in

L-SYOout

F.CBs out

-

Syn. out

-

PERR
1

Pin active
Pout
-

-

-

Pin active
Par.Synd Pout
Pin active
Par.Cbits Pout
-

''''~"

NOTES:
1. Checkbits generated from the data in the SD Latch.
2. Corrected data residing in the Pipeline Latch.

FUNCTIONAL MODE CONTROL
Checkbit Buses
Functional Mode
of SO Bus
f---

MODE

SOE

SO Bus

-MOE

PCBI
Bus

CBI
Bus

CBO
Bus

SYO
Bus

P
Bus

:--

32

8

8

8

8

4

1

2 1 0

Width =

x 1 1

"Normal"
Generate
Correct

1
0

CPU Data
Pipe. latch

0
1

Pipe. latch
RAM Data

-

"Generate-Detect"
Generate
Detect

1
0

CPU Data
Pipe. latch

0
1

Pipe. latch
RAM Data

-

x 1 0

32

MD Bus

-

0 0 0

"Error-Data-Output"

0

Err. D. latch

-

-

-

x 0 1

"Diagnostic-Output"

0

CBin latch
PCBlin bus
Syn. register
Err. counter
Er. type reg.

-

-

PCBI in

1 0 0

"Checkbit-Injection"
Generate
Inject Checkbits
Correct

1
1
0

SDin latch
SDO-7 in
Pipe. latch

0
0
1

Pipe. latch
Pipe. latch
RAM Data

-

CB in

CB in
CB in

-

CB in

PERR

-

Pin active
Pout
-

CB out

-

-

-

Pin active
Pout
-

CB out

-

-

CB out

-

-

-

-

Pin

active

-

-

Pout

2552 tbl 06

5.12

9

II

IDT49C465
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PRIMARY DATA PATH vs. MEMORY CONFIGURATION
SEPARATE I/O MEMORIES:

COMMON I/O MEMORIES:

1. Checkbit Generation
Write New Word to Memory
CPU

[D I----,~------.,~

c

""JJ

1. Checkbit Generation
Write New Word to Memory
DIN
CPU

MAIN
MEMORY

m

-.. SO

CBO

CHECKBIT
MEMORY

"mJJ"

CORRECTED
CPU

MAIN
MEMORY

CBI

[D

c

....,-------l~

CORRECTED

CHECKBIT
MEMORY

JJ

DIN

CORRECTED
CPU

CBI

CHECKBIT
MEMORY

CBI

SO

CORRECTED
MD

P

DOUT

IDT49C465

I/O
MAIN
MEMORY

3. Memory Generation
Re-write Corrected Word to Memory

MAIN
MEMORY

~

MD

CBO
IDT49C465

3. Memory Generation
Re-write Corrected Word to Memory

"

SO
P

DOUT

CPU

CHECKBIT
MEMORY

2. Data Correction
Read Memory Word

~ ""'-C-O-R-R-E-C-T-E-D---.j DIN

IDT49C465

:-l

CBI ~

IDT49C 465

2. Data Correction
Read Memory Word
CPU

I/O
MAIN
MEMORY

-P

DOUT
P
IDT49C465

MD

CBO
IDT49C465

CHECKBIT
MEMORY

CBI

I/O
MAIN
MEMORY
CHECKBIT
MEMORY

2552 drw 13

5.12

10

IDT49C465
32-81T FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PARTIAL-WORD-WRITE OPERATIONS
FOR COMMON I/O MEMORIES:

.

CORRECTION
BLOCK

..

~

-1
()

I

MD BUS

.. ~
.. ~
~

m

...... ~

r

Z

m

~

-

BYTE 1

0

..
..

'-

~

.

..

R3

"0

BYTE 2

r~

-

SD BUS

BYTE 3

r--

..

..
..

BYTE
MUX i

BYTE 3
-'"

BYTE 2
BYTE 1

MAIN
MEMORY

..

BYTE 0

BVTE 0

r--

A3

8
(JJ

0

~

-1

/

I

8

()

..
-

A2

8

/

A1

.. IIAO

8

B3 = 1

I

B2=1

I

---ll

~

,

CHECKBIT
GENERATOR

I

B1 = 1

B0=0

IDT49C465

In order to perform a partial-word-write operation, the
complete word in question must be read from memory. This
must be done in order to correct any error which may have
occurred in the old word. Once the complete, corrected word
is available, with all the bytes verified, the new word may be
assembled in the byte mux and the new checkbits generated.

,,
,,
,,,
,
,,
,
,,

--

CBO

W

..

,
,,
I

,,
,
,
,
,
,

CHECKBIT
MEMORY

2552 drw 14

The example shown above illustrates the case of combining 3 bytes from an old word with a new lower order byte to
form a newword. The newword, alongwiththe newcheckbits,
may now be written to memory.
In the separate I/O memory configuration, the situation is
similar except that the new word is output on the SD Bus
instead of the MD Bus (refer to previous page).

5.12

•

,
,

11

IDT49C465
32-81T FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

32-81T DATA WORD CONFIGURATION
A single IDT49C465 EDC unit, connected as shown below,
provides all the logic needed for single-bit error correction,
and double-bit error detection, of a 32-bit data field. The
identification code (00) indicates 7 checkbits are required.
The CBI7 pin should be tied high.
The 39-bit data format for four bytes of data and 7 checkbits
is indicated below.

Syndrome bits are generated by an exclusive-OR of the
generated checkbits with the checkbits read from memory.
Forexample, Sn is the XOR of checkbits from those read with
those generated. During Data Correction, the syndrome bits
are used to complement (correct) single-bit errors in the data
bits.

32-81T DATA FORMAT
CHECKBITS

DATA

32-81T HARDWARE CONFIGURATION
Vee

L

PCBl0-7

CBOo-s

7

CHECKBITS-OUT

7

--.SYNDROME-OUT

CBI7
CHECKBITS-IN

SYOo-6

CBlo-6

7

ERR
P0-3
~

SYSTEM DATA 1/0

CODE ID 1,0 = 00

;

,
32

~

MERR

SDo-31

MD0-31

IDT49C465

5.12

32

.

MEMORY DATA 1/0

2552 drw 16

12

IDT49C465
32-81T FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

64-BIT DATA WORD CONFIGURATION
Two IDT49C465 EDC units, connected as shown below,
provide all the logic needed for single-bit error correction, and
double-bit error detection, of a 64-bit data field. The "Slice
Identification"Table gives the CODE 101,0 values needed for
distinguishing the upper 32 bits from the lower 32 bits. Final
generated checkbits, ERROR and MULTIPLE ERROR signals come from the upper slice, the IC with CODE ID1,O=11.
Control signals not shown are connected to both units in
parallel.
Data-In bits 0 through 31 are connected to the same
numbered inputs of the EDC with CODE ID1,O=10, while
Data-In bits 32 through 63 are connected to data inputs 0 to 31,
respectively, for the EDC unit with CODE ID1,O=11.
The 72-bit data format of data and checkbits is indicated
below.

Correction of single-bit errors in the 64-bit configuration
requires a simultaneous exchange of partial checkbits and
partial syndrome bits between the upper and lower units.
Syndrome bits are generated by an exclusive-OR of the
generated checkbits with the checkbits read from memory.
For example, Sn is the XOR of checkbits read and checkbits
generated. During data correction, the syndrome bits are
used to complement (correct) single-bit errors in the data bits.
For double or multiple-bit errordetection, the data available as
output by the Pipeline Latch is not defined.
Critical AC performance data is provided in the Table "Key
AC Calculations", which illustrates the delays that are critical
to 64-bit cascaded performance. As indicated, a summation
of propagation delays is required when cascading these units.

64-BIT DATA FORMAT
CHECKBITS

DATA

63565548474039323124231615

8 7

o

2552 drw

17

•

64-BIT HARDWARE CONFIGURATION
L

a

~ PCBIG-7

CBOG-7

a

CHECK BITS-IN
;

(

a

~

CBIG-7

SYOG-7

a

PARTIAL-CHECKBITS (CORRECT ONLY)

PCBIG-7

CBOG-7

CBIG-7

SYOG-7 f -

PARTIAL-CHECKBITS
(GENERATE ONLY)
PARTIAL-SYNDROME
(DETECT/CORRECT)

~

a

FINALC HECKBITS
(GENER ATE ONLY)

ERR
(DETECT AND CORRECT)

PG-3

PG-3

SDG-31

SDG-31

MERR

SYSTEM gATA 0-31
~

MDG-31
MEMORY D ATA 32--B3

IDT49C465

IDT49C465

LOWER EDC
(CODE ID 1,0 = 10)

UPPER EDC
(CODE ID 1,0 = 11)

SYSTEM gATA 32--B3
MEMORY DATA 0-31
2552 drw 18

5.12

13

IDT49C465
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DEFINITIONS OF TERMS:

CMOS TESTING CONSIDERATIONS

DO - D3l
. CBlo - CBI7
PCBlo - PCBI7
FSo - FS7

Special test board considerations must be taken into
account when applying high-speed CMOS products to the
automatic test environment. Large output currents are being
switched in very short periods and proper testing demands
that test set-ups have minimized inductance and guaranteed
zero voltage grounds. The techniques listed below will assist
the user in obtaining accurate testing results:
1) All input pins shou Id be connected to a voltage potential
during testing. If left floating, the device may oscillate,
causing improper device operation and possible latchup.
2) Placement and value of decoupling capacitors is critical.
Each physical set-up has different electrical
characteristics and it is recommended that various
decoupling capacitor sizes be experimented with.
Capacitors should be positioned using the minimum lead
lengths. They should also be distributed to decouple
power supply lines and be placed as close as possible to
the OUT power pins.
3) Device grounding is extremely critical for proper device
testing. The use of multi-layer performance boards with
radial decoupling between power and ground planes is
necessary. The ground plane must be sustained from the
performance board to tile OUT interface board and wiring
unused interconnect pins to the ground plane is recommended. Heavy gauge stranded wire should be used for
power wiring, with twisted pairs being recommended for
minimized inductance.
4) To guarantee data sheet compliance, the input thresholds
should be tested per input pin in a static environment. To
allow for testing and hardware-induced noise, IDT recommends using VIL ~ OV and VIH ~ 3V for AC tests.

=
=
=
=

System Data and/or Memory Data Inputs
Checkbit Inputs
Partial Checkbit Inputs
Final Internal Syndrome bits

FUNCTIONAL EQUATIONS:
The equations below describe the terms used in the
IOT49C465 to determine the values of the partial checkbits,
checkbits, partial syndromes and final internal syndromes.
NOTE: All "ElY symbols below represent the "EXCLUSIVEOR" function.
PA = Do $ Dl $ 02 $ 04 $ 06 $ 08 $ 010 $ 012 $ 016 $ 017
$ 018 $ 020 $ 022 $ D24 $ 026 $ D28
PB = Do $ D3 $ 04 EB D7 $ D9 $ 010EB D13EB 015 EB D16 $ D19
EB 020 $ 023 $ D25 $ D26 EB D29 $ 031
PC = Do $ D1 $ D5 EB D6 EB D7 EB D 11 $ 012 EB D 13 $ D 16 EB D 17
EB 021 EB 022 $ D23 $ 027 $ 028 $ D29
PO = D2 EB D3 EB D4 $ 05 $ D6 $ D7 EB 014 EB D15 EB D18 $ D19
$ D20 EB D21 $ 022 EB D23 EB 030 $ D31
PE = 08 EEl D9 $ 010 EB Dll EB D12 EB D13 $ D14 $ D15 EB D24
$ 025 EB D26 $ D27 EB D28 $ D29 EB D30 EEl D31
PF = Do EEl Dl $ 02 EEl D3 $ 04 $ D5 EB D6 $ D7 $ D24 EB D25
EEl D26 Ef) D27 Ef) D28 $ D29 Ef) 030 EB D31
PG = D8 EEl D9 $ 010 EB Dll $ D12 $ 013 EB 014 EB D15 EB D16
$ 017 Ef) D18 Ef) 019 EB D20 EB D21 EB D22 EB D23
PHo= Do EfJD4EfJ 06 EfJ D7$ D8 $ D9 $ 011 $ D14 $ 017$ D18
EfJ 019 $ D21 $ 026 $ D28 $ D29 $ 031
PHl = 01 $02$D3$05$D8$09$Dl1 $D14$D17$018
EfJ 019 $ 021 $ D24 $ 025 $ 027 $ 030
PH2 = Do $ 04 $ D6 $ 07 $ Dl0 $ 012 $ D13 EEl D15 $ 016 $
020 EfJ 022 EEl 023 $ 026 $ 028 $ 029 $ 031

5.12

14

IDT49C465
32·BIT FLOW·THRU ERROR DETECTION AND CORRECTION UNIT

DETAILED DESCRIPTION SYNDROME GENERATION

MILITARY AND COMMERCIAL TEMPERATURE RANGES

32-BIT SYNDROME DECODE TO BIT-IN-ERROR (1)

CHECKSIT AND
CODE ID

VS.

IHEX

0

1

2

3

4

5

6

S6

0

0

0

0

1

1

1

1

S5

0

0

1

1

0

0

1

1

S4

0

1

0

1

0

1

0

1

LOGIC EQUATIONS FOR THE CBO OUTPUTS
Syndrome

CODE 10 1,0

Bits

7

Checkbit

00

10

11

Generation

Final Chkbits

Partial Checkbits

Final Checkbits

HEX
0

0

0

0

0

.

C4 C5

T

C6

T

T

30

1

0

0

0

1

CO

T

T

14

T

M

M

T

2

0

0

1

0

C1

T

T

M

T

2

24

T

3

0

0

1

1

T

18

8

T

M

T

T

M

T

r----

CBOo

PHo

PHl

PH2 EB PCBlo

CBOl

PA

PA

PA EB PCBll

CB02

PB

PB

PB EB PCBI2

CB03

PC

PC

PC EB PCBI3

CB04

PO

PO

PO EB PCBI4

S3 S2 S1

SO

CBOs

PE

PE

PE EB PCBI5

4

0

1

0

0

C2

T

T

15

T

3

25

CBOs

PF

PF

PF EB PCBls

5

0

1

0

1

T

19

9

T

M

T

T 31

CB07

-

PF

PG EB PCBI7
2552 ttl 07

LOGIC EQUATIONS FOR THE SYO OUTPUTS
CheckbiU

CODE ID 1,0

Syndrome
Generation

00

10

11

Final Syndrome Partial Syndrome Partial Checkbits

6

0

1

1

0

T

20

10

T

M

T

T

M

7

0

1

1

1

M

T

T

M

T

4

26

T

8

1

0

0

0

C3

T

T

M

T

5

27

T

9

1

0

0

1

T

21

11

T

M

T

T

M

A

1

0

1

0

T

22

12

T

1

T

T

M

B

1

0

1

1

17

T

T

M

T

6

28

T

C

1

1

0

0

T

23

13

T

M

T

T

M

T

SYOO

PHO EB CBIO

PH1 EB CBIO

PH2

SY01

PA EB CBl1

PA EB CBl1

PA

SY02

PB EB CBI2

PB EB CBI2

PB

0

1

1

0

1

M

T

T

M

T

7

29

SY03

PC EB CBI3

PC EB CBI3

PC

E

1

1

1

0

16

T

T

M

T

M

M

T

SY04

PO EB CBI4

PO EB CBI4

PO

F

1

1

1

1

T

M

M

T

0

T

T

M

SY05

PE EB CBI5

PE EB CBI5

PE

SY06

PF EB CBI6

PF EB CBI6

PF

SY07

-

PF EB CBI7

PG
2552 ttl 08

LOGIC EQUATIONS FOR THE FINAL SYNDROME (FSn)
CODE 10 1,0

Final
Syndrome

00

10,11

Generation

Final Syndrome

Final Internal Syndrome

FSo

PHo EB CBlo

PHl (l) EB PH2 (U) EB CBlo

FSl

PA EB CBI1

PA (l) EB PA (U) EB CBll

FS2

PB EB CBI2

PB (l) EB PB (U) EB CBI2

FS3

PC EB CBI3

PC (l) EB PC (U) EB CBI3

FS4

PO EB CBI4

PO (l)EB PO (U) EB CBI4

FSs

PE EB CBls

PE (l) EB PE (U) EB CBI5

FSs

PF EB CBls

PF (l) EB PF (U) EB CBls

FS7

-

PF (l) EB PG (U)EB CBI7

NOTES:
2S52 tbl12
1. The table indicates the decoding of the seven syndrome bits to identify the
bit-in-error for a single-bit error, or whether a double or triple-bit error was
detected. The all-zero case indicates no error detected.
• = No errors detected
# = The number of the single bit-in-error
T = Two errors detected
M = Three or more errors detected

2552 tbl 09

5.12

15

II

IDT49C465
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

DETAILED DESCRIPTION -

MILITARY AND COMMERCIAL TEMPERATURE RANGES

32-BIT CONFIGURATION

32-BIT MODIFIED HAMMING CODE -

CHECKBIT ENCODING CHART(l)

Generated

Participating Data Bits

Checkbits

Parity

0

CBO

Even (XOR)

X

CB1

Even (XOR)

X

CB2

Odd (X NOR)

X

CB3

Odd (XNOR)

X

CB4

Even (XOR)

CBS

Even (XOR)

CB6

Even (XOR)

1

X

2

3

X
X

X
X

6

7

8

9

X

X

X

X

X

X

X

4

5

X
X

X

X

X

X

X

-- -- -X

X

X
X

X

X

X

X

X

X

X

11

X

12

13

X
X

X

X

10

15

X
X

X

X

14

X
X

X

X

X

X

X

X
X

X

X

X

X
2552 ttll 10

Generated

Participating Data Bits

Checkbits

Parity

CBO

Even (XOR)

CB1

Even (XOR)

X

CB2

Odd (X NOR)

X

CB3

Odd (X NOR)

X

CB4

Even (XOR)

CBS

Even (XOR)

X

X

CB6

Even (XOR)

X

X

16

17

18

19

X

X

X

X

X

20

X
X
X

22

23

24

25

X
X

X

X
X

21

X

NOTE:

X
X

X
X

X

X

X

X

X

26

28

29

X

27

X

X

X

X

X
X

X

X

30

31

X

X

X
X

X

X

X

X

X

X

X

X

X

X

X

X

X
2552 ttl I 11

1. The table indicates the data bits participating in the checkbit generation. For example, checkbit CO is the Exclusive-OR function of the 16 data input bits
marked with an X.

5.12

16

IDT49C465
32·BIT FLOW·THRU ERROR DETECTION AND CORRECTION UNIT

DETAILED DESCRIPTION -

MILITARY AND COMMERCIAL TEMPERATURE RANGES

64-BIT CONFIGURATION

64·BIT MODIFIED HAMMING CODE· CHECKBIT ENCODING CHARr<1, 2)
Participating Data Bits

Generated
Checkbits

Parity

CBa

Even (XOR)

0

1

2

3

X

X

X

X

X

4

5

6

7

X
X

Even (XOR)

X

Odd (XNOR)

X

CB3

Odd (XNOR)

X

CB4

Even (XOR)

CB5

Even (XOR)

CBS

Even (XOR)

X

X

X

X

X

X

X

X

CB7

Even (XOR)

X

X

X

X

X

X

X

X

X
X

X

X

X
X

9
X

X

CB1
CB2

X

8
X

X

X

X

X

X

11

12

X

X

14

15

X
X

X

X

13

X
X

X

X
X

10

X

X

X

X

X

X

X
X

X

X

X

2552 tbl13

Generated

Participating Data Bits

Checkbits

Parity

CBa

Even (XOR)

16

17

18

19

X

X

X

X

X

20

21

22

23

X

24

25

X

X

X

Even (XOR)

X

Odd (X NOR)

X

CB3

Odd (X NOR)

X

CB4

Even (XOR)

CB5

Even (XOR)

X

X

CBS

Even (XOR)

X

CB7

Even (XOR)

X

X

X
X

X

X

X
X

X

X
X

X

X

X

X

X

Generated

27

28

29

X
X

CB1
CB2

X

26

30

31

X
X

X

X

X

X

X

X
X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

42

43

46

47

Participating Data Bits

Checkbits

Parity

32

CBa

Even (XOR)

X

CB1

Even (XOR)

X

CB2

Odd (XNOR)

X

CB3

Odd (X NOR)

X

CB4

Even (XOR)

CB5

Even (XOR)

CBS

Even (XOR)

CB7

Even (XOR)

33
X

34
X

X

36

38

39

X

X

X

X

X

X

X

X
X

37

X

X
X

X

35

X
X

40
X

X

X
X

X

X

X

X

X

X

X

41

44

45

X

X

X

X

X

X
X

X

X
X

X

X
X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X
X
2552 tbl15

Generated

Participating Data Bits

Checkbits

Parity

48

CBa

Even (XOR)

X

CB1

Even (XOR)

X

49
X

50

51

X
X

52

53

54

55

X

X

X

X

X

56
X

X

X

CB2

Odd (XNOR)

X

CB3

Odd (X NOR)

X

CB4

Even (XOR)

CB5

Even (XOR)

X

X

CBS

Even (XOR)

X

X

CB7

Even (XOR)

X
X

X

X

57

X

X

X

X

X

X

X

X

X

X

X

X

X

X

58

59

62

63

60

61

X

X

X

X

X

X
X

X

X
X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

NOTES:
2552 tbl 16
1. The table indicates the data bits participating in the checkbit generation. For example, checkbit CO is the Exclusive-OR function of the 32 data input bits
marked with an X.
2. The checkbit is generated as either an XOR or an XNOR of the 32 data bits noted by an "X" in the table.
5.12

17

IDT49C465
32·81T FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

DETAILED DESCRIPTION -

MILITARY AND COMMERCIAL TEMPERATURE RANGES

64-BIT CONFIGURATION (Con't.)

32-BIT SYNDROME DECODE TO BIT-IN-ERROR(1)

I HEX

- HEX

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

S7

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

S6

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

Syndrome

S5

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

Bits

S4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

C4

C5

T

C6

T

T

62

C7

T

T

46

T

M

M

T

T

T

14

T

M

M

T

T

M

M

T

M

T

T

30
M

S3

S2

S1

SO

0

0

0

0

0

1

CO

0

1

0

C1

T

T

M

T

34

56

T

T

50

40

T

M

T

T

0

1

1

T

18

8

T

M

T

T

M

M

T

T

M

T

2

24

T

1

0

0

C2

T

T

15

T

35

57

T

T

51

41

T

M

T

T

31

1

0

1

T

19

9

T

M

T

T

63

M

T

T

47

T

3

25

T

1

1

0

T

20

10

T

M

T

T

M

M

T

T

M

T

4

26

T

7

a
a
a
a
a
a
a
a

1

1

1

M

T

T

M

T

36

58

T

T

52

42

T

M

T

T

M

0
1
2
3
4
5
6

8

1

0

0

0

C3

T

T

M

T

37

59

T

T

53

43

T

M

T

T

M

9

1

0

0

1

T

21

11

T

M

T

T

M

M

T

T

M

T

5

27

T

A

1

0

1

0

T

22

12

T

33

T

T

M

49

T

T

M

T

6

28

T

B

1

0

1

1

17

T

T

M

T

38

60

T

T

54

44

T

1

T

T

M

C

1

1

0

0

T

23

13

T

M

T

T

M

M

T

T

M

T

7

29

T

D

1

1

0

1

M

T

T

M

T

39

61

T

T

55

45

T

M

T

T

M

E

1

1

1

0

16

T

T

M

T

M

M

T

T

M

M

T

0

T

T

M

F

1

1

1

1

T

M

M

T

32

T

T

M

48

T

T

M

T

M

M

T

NOTES:
2552 tbl 17
1. The table indicates the decoding of the seven syndrome bits to identify the bit-in-error for a single-bit error, or whether a double or triple-bit error was
detected. The all-zero case indicates no error detected .
• = No errors detected
# = The number of the single bit-in-error
T = Two errors detected
M = Three or more detected

KEY AC CALCULATIONS -

64-BIT CASCADED CONFIGURATION

64·Bit Propagation Delay
Mode

Total AC Delay for IDT49C465 in 64-bit Mode
(L)
(U)

=Lower slice
=Upper slice

From

To

Generate

SD Bus

Checkbits out

SD to CBO(L)
t SC(L)

+
+

PCB I to CBO(U)
tPCC(U)

Detect

MD Bus

ERROR for 64-bits

MD Bus

M ERROR for 64-bits

MD to
t
MDto
t

SYO(L)
MSY(L)
SYO(L)
MSY(L)

+
+
+
+

CBI to ERR (U)
tCE (U)
CBI to M ERR
tCME (U)

MD Bus

Corrected data out

MD to SYO(L)
t MSY(L)
MD to SYO(U)
tMSY(U)

+
+
+
+

CBI to SD(U)
tCS (U)
PCBI to SD(L)
t PCS(L)

Correct

(or)
NOTE:
1. (or) = Whichever is worse.

~

2552 tbl 18

5.12

18

IDT49C465
32-81T FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Com'l.

Rating

Vee

Power Supply
Voltage

VTERM

Terminal Voltage
with Respect
to Ground

TA

Operating
Temperature

TSIAS

CAPACITANCE (TA = +25°C, f = 1.0MHz)
Mil.

-0.5 to +7.0 -0.5 to +7.0

Conditions

Typ.

Unit

CIN

Input
Capacitance

VIN = OV

5

pF

COUT

Output
Capacitance

VOUT = OV

7

pF

-0.5 to
Vee + 0.5

-0.5 to
Vee + 0.5

V

a to +70

-55 to +125

°C

Temperature
Under Bias

-55 to + 125 -65 to +135

°C

TSTG

Storage
Temperature

-55 to +125 -65 to + 150

°C

lOUT

DC Output
Current

30

30

Parameter(1)

°C

Unit

Symbol

NOTE:
1. This parameter is sampled and not 100% tested.

2552 tbl20

mA

NOTE:
2552 tbl19
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Ratings for
extended periods of time may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
The following conditions apply unless otherwise specified:
Commercial: TA = O°C to +70°C, Vee = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vee
Symbol
VIH

Test Conditions(1)

Parameter
Input High Level(4)

Guaranteed Logic High

Min.

5.0V

± 10%

Typ.(2)

Max.

Normal Inputs

2.0

-

-

Hysteresis Inputs

3.0

-

-

Unit
V

VIL

Input Low Level(4)

Guaranteed Logic Low

-

-

O.S

V

IIH

Input High Current

Vce = Max., VIN = Vee

JlA

Input Low Current

Vee = Max., VIN = GND

-

5.0

IlL

-

-5.0

JlA

loz

Off State (Hi-Z)

Vee = Max.

-

-

-10

JlA

-

los

Short Circuit Current

Vee = Max.l3)

VOH

Output HIGH Voltage

Vee = Min.

10H = -6mA

VIN = VIH or VIL

Vo= OV

-

10

-20

-

-100

COM'L.

2.0

MIL.

2.4

-

V

10H = -4mA

-

Vee = Min.

IOL = SmA

COM'L.

-

-

0.5

V

VIN = VIH or VIL

10L = 6mA

MIL.

-

-

0.5

Vo=3V

VOL

VH

Output LOW Voltage

Hysteresis

CLEAR,MLE,PLE,SLE,SYNCL~SCLKEN

-

NOTES:
1. For conditions shown as min. or max., use appropriate value specified above for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°e ambient temperature and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.

5.12

200

-

mA

mV
2552 tbl21

19

II

IDT49C465
32-81T FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Con't.)
The following conditions apply unless otherwise specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc = 5.0V ± 10%
VHC = Vcc - 0.2V, VLC = Vcc + 0.2V
Symbol

Parameter

Test Conditions(1)

Min.

Typ.(;l)

Max.

Unit

Iccoc

Quiescent Power Supply Current
CMOS Input Levels

VIN = VHC, VIL = VLC
Vcc = Max. All Inputs
Outputs Disabled

-

-

5

mA

Iccor

Quiescent Power Supply Current
TIL Input Levels

VIH = 3.4V, VIL = OV
vcc = Max. All Inputs
Outputs Disabled

-

-

160

mA

ICCD1

Dynamic Power Supply Current
f = 10MHz

fcp = 10MHz, 50% Duty Cycle
VIH = VHC, VIL = VLC
All Inputs, Outputs Disabled

COM'L.

-

-

230

mA

MIL.

-

Dynamic Power Supply Current
f = 20MHz

fcp = 20M Hz, 50% Duty Cycle
VIH = VHC, VIL = VLC
All Inputs, Outputs Disabled

COM'L.

-

-

300

ICCD2

MIL.

-

-

350

NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified above for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient temperature, and maximum loading.
3. Total supply current is the sum of the Quiescent current and the dynamic current and is calculated as follows:
ICCT = Iccac (Nae) + leeae x (Noe x Dc) + leeoe x (Noe x fop) + ICCQT (NOT) + leeaT (NDT x DT) + IccDe x (Noe x fop)
where:
Noe =Total # of dynamically switching CMOS inputs
NOT = Total # of dynamically switching TIL inputs
Nae = Total # of quiescent CMOS inputs
NaT = Total # of quiescent TTL inputs
De = AC Duty cycle - % of time high (CMOS)
DT = AC Duty cycle - % of time high (TIL)
fop = Operating frequency

5.12

300

mA

25521b122

20

IOT49C465
32·BIT FLOW·THRU ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC PARAMETERS
PROPAGATION DELAY TIMES (PRELIMINARY)
32·bit
System
Standalone
Slice

Parameter Description
Parameter
Name

From
Input (edge)

I Output
To

(edge)

64·bit System

64·bit
"Generate
only"
Slice

Upper
Slice

Lower
Slice

CODE 10=00

CODE 10=01 CODE 10=10 CODE 10=11

Com.

Com.

Mil.

MIL

Com.

MIL

Com.

MIL

Max. Max. Max. Max. Max. Max. Max. Max.

Refer to
Unit

TimIng Diagram
Figure

GENERATE (WRITE) PARAMETERS

-

20

25

20

25

-

20

25

20

25

15

20

-

-

-

-

-

-

-

15

20

20

-

-

15

20

15

20

15

20

15

20

15

20

15

20

15

20

-

15

20

15

20

15

20

-

-

15

20

15

20

ERROR Low

15

20

-

20

20

24

-

-

15

MULT ERR=Low

20

24

SYO

15

20

-

10

15

15

20

tBC

BEN

CBO

20

25

tBM

BEN

MDoUT

20

25

tMe

MDIN

CBO

tpec

PCB I

CBO

-

-

tPPE

PXIN

PERR

15

CBO
SDIN

MDoUT
PERR

tse
tSM
tSPE

-

ns
ns
ns
ns
ns
ns
ns
ns

10

7

7
7

-

DETECT (READ) PARAMETERS
tCE
tCME

CBI

tCSY
tME
tMME

MDIN

tMSY

ERROR

15

20

-

-

-

-

15

20

MULT ERR

20

24

-

-

-

-

20

24

SYO

15

20

-

-

10

15

15

20

ns
ns
ns
ns
ns
ns

8,10

ns
ns
ns
ns
ns

8,11

8,10
8,10
8,10
8,10
8,10

CORRECT (READ) PARAMETERS
tcs

CBI

tMP
tMS

MDIN

tMSY
tpes

PCBI

SDOUT

20

24

-

-

-

-

20

24

Px

30

36

-

-

30

36

30

SDOUT

20

25

-

-

15

20

10

15

15

20

SDOUT

-

-

-

-

SYO

-

36
-

15

20

-

-

8,11
8,11
8,11
11

DIAGNOSTIC PARAMETERS
CLEAR = Low

SDOUT

15

MODE 10

SDOUT

15

NOTES:
1. Where "edge" is not specified, both high and low edges are implied.
2. BOLD indicates critical system parameters.

2552 tbl23

5.12

21

•

IDT49C465
32·BIT FLOW·THRU ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC PARAMETERS
PROPAGATION DELAY TIMES FROM LATCH ENABLES (PRELIMINARY)
Parameter Description
Parameter
Name
tMLC
tMLE
tMLME

From
Input

MLE =

(edge)

To
Output

High

eso
ERROR
MULTERR

tMLP

Px

tMLS
tMLSY

SDOUT
SYO

tPLS
tPLP

PLE =
PLE =

Low
Low

SDouT
Px

tSLC
tSLM

SLE =
SLE =

High
High

eso
MDoUT

Mil.

Refer to

Max.

Max.

Unit

Timing Diagram
Figure

20
15
20
30
20
18
10
20
20
15

24
20
24
36
24
22
12
22
24
20

ns
ns
ns
ns
ns
ns

Com.'1.
(edge)

ns
ns
ns
ns

13
8,10,11
8
8, 11

8,10,11
8,10
8, 11
8,11
7, 9
7,9

NOTE:

2552 tbl24

II." = Both high and low edges are implied.
ENABLE AND DISABLE TIMES (PRELIMINARY)
Parameter Description
Parameter
Name

From
Input

tBESZx
tBESxZ

SEN =

tBEPZx
tBEPxZ

SEN =

(edge)

To
Output

High
Low

SDOUT

High
Low

POUT

tCECZx
tCECxZ

eSOE = Low
High

eso

tMEMZx
tMEMxZ

MOE=

t SESZx
tSESxZ

SOE =

Com'l.
(edge)
Hi-Z
Hi-Z
Hi-Z

Low
High

MDoUT

Low
High

SDOUT

Hi-Z
Hi-Z

Refer to

Mil.

Timing Diagram
Figure

Min.

Max.

Min.

Max.

Unit

2
2
2
2
2

15
15
15
15
15
15
15
15
15
15

1

18
18
18
18
18
18
18
18
18
18

ns
ns

8,10,11

ns
ns

8,11

ns
ns

7, 9

ns
ns

7, 9
8,10
8,10
7, 9

-

NOTE:

1

1

1

1
-

ns
ns

2552 tbl25

II." = Delay to both edges.

5.12

22

IDT49C465
32·BIT FLOW·THRU ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SET-UP AND HOLD TIMES (PRELIMINARY)
Parameter Description
Parameter
Name

From
Input

Com.'1.

To
Output

Mil.

Refer to

(edge)

Min.

Min.

Unit

Timing Diagram
Figure

before MLE =

Low

4

5

ns

8,10,11

after MLE =

Low

4

5

ns

8,10,11

before MLE =

Low

4

5

ns

8,10,11

after MLE =

Low

4

5

ns

8,10,11

SOIN Set-up

before SLE =

Low

5

ns

tSSLH

SOIN Hold

after SLE =

Low

4
4

5

ns

7, 9
7, 9

tCPLS

CBI Set-up

before PLE =

High

18

22

ns

tCPLH

CBI Hold

after PLE =

High

0

0

ns

before PLE =

High

18

22

ns

-

after PLE =

High

0

0

ns

before PLE =

High

18

22

ns

-

after PLE =

High

0

0

ns

-

25

30

ns

15

25
25

30
30

ns
ns

15

4
4

5

ns

15

5

ns

15

(edge)

tCMLS

CBI Set-up

tCMLH

CBI Hold

tMMLS

MOIN Set-up

tMMLH

MOIN Hold

tSSLS

tMPLS

MOIN Set-up

tMPLH

MOIN Hold

tPCPLS

PCB I Set-up

tPCPLH

PCB I Hold

·
·
·

·
·

-

DIAGNOSTIC SET-UP AND HOLD TIMES
tCSCS

CBI Set-up

tMSCS
tMLSCS

MOIN Set-up
MLE Set-up = High

tSESCS

SCLKEN Set-up =Low

tSESCH

SCLKEN Hold =Low

·

before SYNCLK=High

after SYNCLK =High

15

NOTE:

2552 tbl26

..... = Where "edge" is not specified, both high and low edges are implied.

MINIMUM PULSE WIDTH (PRELIMINARY)
Refer to
Parameter

Minimum Pulse Width

Name
tCLR
tMLE
tPLE
tSLE
tSYNCLK

Input
Min.
Min.
Min.
Min.
Min.

CLEAR low time
MLE high time
PLE low time
SLE high time
SYNCLK high time

to
to
to
to
to

clear diag. registers
strobe new data
strobe new data
strobe new data
clock in new data

Com'!.

Mil.

Conditions

Min.

Min.

Unit

Timing Diagram

Oata = Valid
MO, CBI = Valid
SO = Valid
SO = Valid
SCKEN = Low

5
5
5
5
5

6
6
6
6
6

ns
ns
ns
ns
ns

Figure
14

-

14
2552 tbl27

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to 3.0V

Wins
1.5V
1.5V
See Figure 18
2552 tbl 28

5.12

23

II

IDT49C465
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

AC TIMING DIAGRAMS -

MILITARY AND COMMERCIAL TEMPERATURE RANGES

32-BIT CONFIGURATION
Min.!
Max.

Propagation Delay
From
To

t

BES,Z

min.

SEN

= Low to SDOUT Disabled

min.

t

BES,Z

max

SEN

= Low to SDOUT Disabled

max.

t SES,Z min.

SOE

= Low to SDOUT Disabled

min.

t SES,Z max

SOE

= Low to SDOUT Disabled

max.

t

SSLS

SDIN Set-up to SLEIN

t

SSLH

SDIN Hold to SLEIN

t

SPE

SDIN to PERRoUT

max.

t

PPE

Px to PER ROUT

max.

t
t

SM

SDIN to MDoUT

SLM(1)

SLE

t

MEMZ,

MOE

= Low

min.

= Low

min.

PN

PERR

COE
MD0-31

M DATAoUT

= High to

= Low to

max.

MDoUT

max.

MDoUT Enabled

max.

= S DATAIN

COE

eso

t sc

SDIN to

t SLC (1 )

SLE

t

'C"BlJE = Low to eso Enable

CECZ,

= High to

max.

esa

max.

max.

csa

NOTE:
1. Assumes that System Data is valid at least 4ns before SLE goes high.

2552 drw 19

Figure 7. 32·Bit Generate Timing

5.12

24

IDT49C465
32·81T.FLOW·THRU ERROR DETECTION AND CORRECTION UNIT

AC TIMING DIAGRAMS -

MILITARY AND COMMERCIAL TEMPERATURE RANGES

32-BIT CONFIGURATION
Propagation Delay
From
To

Min.!
Max.

NOTE:
1. Assumes that Memory Data and Checkbits are valid at least 4ns before MLE goes high.
Figure 8. 32·8it Detect Timing

5.12

25

IDT49C465
32·BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

AC TIMING DIAGRAMS -

MILITARY AND COMMERCIAL TEMPERATURE RANGES

32-BIT CONFIGURATION
Parameter
Name

Propagation Delay
From
To

= High to MDoUT Disabled

Min.!
Max.

t

MEM,Z

MOE

max.

t

MMLS

MDIN Set-up to MLE

t

MMLH

MDIN Hold to MLE

t

CMLS

Checkbit Set-up to MLE

t

CMLH

Checkbit Hold to MLE

t

MLS(1)

MLEIN

t

PLS(11

PLE

= Low to SDOUT (1)

max.

t

BESZ,

BEN

= High to SDOUT Enabled

max.

t SESZ,

SOE

= Low to SDOUT Enabled

max.

t cs

CBI to Corrected SDOUT

max.

t

MS

MDIN to Corrected SDOUT

max.

t

MP

MDIN to Parity Out

max.

t

MLP

MLE

= High to

Parity Out

max.

t

PLP

max.

t

BEPZ,

t

SEP

= Low to Parity Out
BEN = High to Parity Out
SOE = Low to Parity Out

MD0-31

= Low

= Low

min.
min.

CBI

= Low

= Low

min.
min.

MLE

SD0-31

= High to SDOUT (1)

max.

Corrected DAT AOUT

PLE

max.
max.

P0-3

NOTE:
1. Assumes that Memory Data and Checkbits are valid at least 4ns before MLE goes high.

2552 drw 21

Figure 9. 32·Bit Correct Timing

5.12

26

IDT49C465
32-81T FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

AC TIMING DIAGRAMS -

MILITARY AND COMMERCIAL TEMPERATURE RANGES

64-BIT CONFIGURATION
Propagation Delay
From
To

BOTH
465s

Min./
Max.

BEN

t SES.Z min.

SOE

= High to SDouT Disabled

min.

max

SOE

= High to SDOUT Disabled

max.

t'SES.Z

SD(L&U)
t

SSLS

SDIN Set-up to SLEIN

= Low

= Low

min.

t SSLH

SDIN Hold to SLEIN

t PPE

Px to PERR

max.

t

SM

SDIN to MDoUT

max.

SLE = High to MDoUT

max.

t

MEMb

MOE = Low to MDoUT Enabled

max.

t

BEM

BEN to MDoUT

max.

min.

SLE

Px

MD (L&

U)

MD DATAoUT = SD DATA IN
t SC

SD Lower In to CBO

t

SLEIN

SLC(ll

t CECZ.

= High to

CBO

max.
(ll

~ = Low to CBO Enabled

max.

max.

Partial Checkbits Out
~-------

Inter-chip delay (Design dependent)

t pcc

PCBI to CBO

NOTE:
1. Assumes that System Data is valid at least 4ns before SLE goes high.

max.

2552 drw 22

Figure 10. 64·Bit Generate Timing -

5.12

(64-Bit Cascading System)

27

II

IDT49C465
32·81T FLOW·THRU ERROR DETECTION AND CORRECTION UNIT

AC TIMING DIAGRAMS -

MILITARY AND COMMERCIAL TEMPERATURE RANGES

64-BIT CONFIGURATION

BOTH
405s

r-~--~--~--~--~---L---L---L---L---L---L--~~r-----~--

Min.!
Propagation Delay
Max.
To
From
________________________+-____

MOE

= High to

MDoUT Disabled

max.

= Low

min.

~

MD(L)

MDIN Set·up to MLE
MDIN Hold to MLE

= Low

min.

CBI Set·up to MLE

= Low

min.

CBI

CBI Hold to MLE

= Low

min.

MLE
MLE = High to SDOUT (1)

max.

BEN

t

SESZ,

BEN

= High to SDOUT Enabled

max.

SOE

= Low to SDOUT Enabled

max.

Corrected DATAoUT

SD0-31

t

MSY

MD Lower In to SYOouT

max.

t

CSY

CBI to SYO

max.

t

MLSY

MLE

= High to SYO

max.

Partial Syndrome Out

SYO

..
Partial Syndrome In

CBI

CBI to MERR
MLE

= High to

max.
MERR

max.

MERR
CBI to ERR
t

MLE

MLE (1)

= High to ERR

max.
max.

ERR
t

ME

MDIN to ERR

max.

MDINto MERR

max.

MD(u)

NOTE:
1. Assumes that System Data is valid at least 4ns before SLE goes high.

2552 drw 23

Figure 11. 64·Bit Detect Timing

5.12

28

IDT49C465
32·81T FLOW·THRU ERROR DETECTION AND CORRECTION UNIT

AC TIMING DIAGRAMS -

MILITARY AND COMMERCIAL TEMPERATURE RANGES

64-BIT CONFIGURATION
Propagation Delay
To
From

MOE

= High

to MDoUT Disabled

MDIN Set-up to MLE

= Low

Min.!
Max.

max.

min.

MDIN Hold to MLE

= Low

min.

CBI Set-up to MLE

= Low

min.

= Low

t

CMLH

CBI Hold to MLE

t

MLS (1)

MLEIN

t

PLS (1)

PLE

= Low to SDoUT (1)

max.

t

BESZ,

BEN

= High to SDouT Enabled

max.

t SESZ,

SOE

= Low to SDOUT Enabled

max.

t cs

CBI to Corrected SDouT

max.

t CSY

CBI to Syndrome

max.

t

MDIN to Corrected SDouT

max.

MS

= High to SDOUT (1)

min.

max.

Corrected OATAOUT
t CSY

CBI to Syndrome

max.

t

MSY

MDIN to Syndrome

max.

t

MP

MDIN to Parity Out

max.

t

MLP

max.

t

PLP

t

BEPZx

= High to Parity Out
PLE = Low to Parity Out
BEN = High to Parity Out
SOE = Low to Parity Out

t SEP

MLE

max.
max.
max.

Parity Out

Partial Syndrome Out

NOTE:
1. Assumes that Memory Data and Checkbits are valid at least 4ns before MLE goes high.

2552 drw 24

Figure 12. 64·8it Correct Timing (Lower Slice)

5.12

29

I

IDT49C465
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

AC TIMING DIAGRAMS -

MILITARY AND COMMERCIAL TEMPERATURE RANGES

64-BIT CONFIGURATION

64-BIT
U/L Slice

Propagation Delay
To
From

Min.!
Max.

MOE = High to MDoUT Disabled

max.

MD:~~

min.

MD0--31

Sot-up to MLE '- Lo·....

MDIN Hold to MLE = Low

min.

CSI Set-up to MLE = Low

min.

CSI Hold to MLE = Low

min.

CSI

MLE
MLEIN = High to SDOUT

PLE = Low to SDOUT

(1)

(1)

max.

max.

BEN
max.

SOE = Low to SDOUT Enabled

max.

t cs

CSI to Corrected SDOUT

max.

t

MS

MDIN to Corrected SDOUT

max.

t

MSY

MDIN to Corrected SDOUT

max.

t

MP

MDIN to Parity Out

max.

t

MLP

MLE = High to Parity Out

max.

t

SD0--31

SEN = High to SDOUT Enabled

SESZx

Corrected DATAOUT

t

PLP

PLE = Low to Parity Out

max.

t

BEPZx

SEN = High to Parity Out

max.

t

SEP

SOE = Low to Parity Out

max.

P0--3

SYO

NOTE:
1. Assumes that Memory Data and Checkbits are valid at least 4ns before MLE goes high.

2552 drw 25

Figure 13. 64-Bit Correct Timing (Upper Slice)

5.12

30

IDT49C465
32-81T FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

AC TIMING DIAGRAMS -

MILITARY AND COMMERCIAL TEMPERATURE RANGES

64-BIT CONFIGURATION
Propagation Delay
From
To

SINGLE

485

Min.!
Max.

SD Bus

t

SSLH

SDIN Set-up to SLEIN = Low

min.

SDIN Hold to SLEIN = Low

min.

SLE = High to CBO

max.

SLE

(1)

MD Bus
t

MMLS

MDIN Set-up to MLEIN = Low

min.

t

MMLH

MDIN Hold to MLEIN = Low

min.

max.

MLE
t sc

Bits 32-63 to CSO

I

MC

Bits 0-31 to CBO

max.

I

MLC(2)

MLEIN = High to CBO (2)

max.

t

CECZx

CBOE = Low to CBO Enabled

max.

~OE

~BO

Final Checkbits Out

NOTE:
1. Assumes that System Data is valid at least 4ns before SLE goes high.
2. Assumes that Memory Data is valid at least 4ns before MLE goes high.

2552 drw 26

Figure 14. 64-Bit Single Chip "Generate Only" Timing

5.12

31

I

IDT49C465
32·SIT FlOW·THRU ERROR DETECTION AND CORRECTION UNIT

AC TIMING DIAGRAMS -

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DIAGNOSTIC TIMING
Propagation Delay
From
To

Min.!
Max.

CBI Set-up to SYNClK = High

MDIN Set-up 10 SYNCLK = High

min.

MlE = High Sel-up 10 SYNClK = High

min.

SClKEN Set-up to SYNClK = High

min.

SClKEN = Hold After SYNClK = High

min.

SCLKEN Pulse Widlh
SCLKEN = High to SDOUT

min.
max.

CLEAR Pulse Width

min.

CLEAR = low 10 SDOUT

max.

2552 drw 27

Figure 15. 32·Sit Diagnostic Timing

5.12

32

IDT49C465
32·81T FLOW·THRU ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

INPUT/OUTPUT INTERFACE CIRCUITS
Vee
IIH~

ESD
PROTECTION

INPUTS lJ----t-----+--+--i
OUTPUTS

2552 drw 28

2552 drw 29

Figure 16. Input Structure (All Inputs)

Figure 17. Output Structure

AC TEST CIRCUIT
Vee

5.0V

470n

II

200n

2552 drw 30

DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance
RL = Termination resistance: should be equal to ZOUT of the Pulse Generator

Figure 18.

ORDERING INFORMATION
lOT

49C465
Device Type

• XX
Package

X
Process/
Temperature
Range

I

B

Commercial (O°C to +70°C)
Military (-55°C to + 125°C)

G

Pin Grid Array

49C465

32-Bit Flow-thru™ EDC

BLANK

2552 drw 31

5.12

33

G®
Integrated Device Technology, Inc.

Flow-thruEDCTM
ERROR DETECTION
AND CORRECTION UNIT

ADVANCE
INFORMATION
IDT49C466

FEATURES:

DESCRIPTION:

• 64-bit wide Flow-thruEDC Error Detection and Correction
Unit
• Separate System and Memory Data Input/Output Buses
• 64-bit Error Detect Time - 20ns;
Error Correct Time - 25ns
• Corrects all single bit errors; Detects all double bit errors
• Configurable 16-deep system bus readlwrite buffer with
flag indicators
• Simultaneous check bit generation and data correction of
memory data
• Supports partial word writes on byte boundaries
• 8mA output drive current to drive small memory arrays
directly
• Sophisticated error diagnostics and error logging
• Parity generation on system data bus
• 208 pin Pin Grid Array and Plastic Quad Flatpack
(PQFP)
• Military product compliant to MIL-STD-883, Class B

The IDT49C466 64-bit Flow-thruEDC is a high speed error
detection and correction unit to ensure data integrity in high
reliability memory systems. The flow-thru architecture with
separate system and memory data buses is ideally suited for
pipe lined memory systems.
Implementing a Hamming code in the 8-bit wide check bit
bus, the I DT49C466 corrects all single bit hard and soft errors,
and detects all double bit errors. The readlwrite buffer can
store up to sixteen 64-bit words until the system bus is ready
(during reads) or until the system bus is released (during
writes). Full and empty flags indicate whether additional data
can be written to the EDC.
The simultaneous check bit generation and data correction
of memory data eliminates the separate correction and
generation modes found on other EDC units. Check bit
generation for partial word writes on byte boundaries is
supported on the IDT49C466.
Diagnostics features include a syndrome latch from which
the error bit can be decoded, a four bit error counter which
counts upto 15 errors, and an error data latch which stores the
complete error data word. Parity can be generated and
checked on the system bus by the IDT49C466.
Military product is available compliant with the latest revision of MIL-STD-883, Class B, for those systems operating in
extreme environments.

Flow·thruEDC is a trademark of Integrated Device TeChnology Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
<1:It990 Integrated Device Technology. Inc.

5.13

JUNE 1990
DSC·9037/-

1

m::cO
::c~

OlD

::cO
....

om

CBI0-7

~~
m-

0°
-i::E

os.
Z"c

/MDOLE

>m

MCLKCE»~----------------------~

ZO

~~

RSO-l

:-----«

Z

o
o

PO-7

I SUPPLY
POWER ~
17

VCC
GND

~ERR ~~--------~

49C466 64-BIT DUAL BUS EDC
SYNCLKD2))

::c
<

IERROR==t>-MDNAL
1Y~a.Jt

Dash Line: Diagnostic path

~ ~~

o

3:
3:
m

::c
o

l>
,....

-i

m
3:
"'C
m

::c

~

>
-i

c:
::c
m
::c

N

>
Z

G')

m

en

II

IDT49C466 Flow-thruEDCThI
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION
A

B

c

o

17

MO_10

MO_8

MO_2

MO_1

16

MO_13

MO_9

MO_6

MO_3

15

MO_17

MO_12

MO_11

MO_5

MO_4

14

MO_18

MO_19

MO_15

GNO_N

MOJ

13

MO_23

MO_20

MO_14

VCC_N

12

MO_25

MO_22

MO_21

11

MO_27

MO_28

10

MO_31

R

T

u

N

P

5o_3

BEO

5o_9

5o_10

5o_12

5o_15

17

5o_1

5o_4

5o_6

5o_8

5o_13

5o_16

5o_17

16

PO

5o_7

P1

BE1

5o_14

5o_19

5o_21

15

5o_5

5o_11

GNO_N

GNO_N

P2

BE2

5o_20

14

5o_18

5o_22

5o_24

5o_25

13

MO_16

5o_23

5o_26

5o_28

5o_27

12

MO_24

GNO_N

P3

BE3

5o_30

5o_29

11

MO_30

MO_29

MO_26

5o_31

50EB

50lLE

5CLK

10

MOLEB

MOEB

MILE

GNO_N

MOOLEB GNO_N

MENB

R5_0

9

MO_33

MO_32

MO_34

MO_35

GNO_N

5o_33

MCLK

R5_1

MO_37

MO_36

MO_39

MO_40

5o_37

5o_34

5o_32

PERRB

MO_41

MO_38

MO_42

MO_45

5o_42

5o_38

P4

5o_35

MO_43

MO_44

MO_46

MO_52

GNO_N

P5

BE4

5o_36

MO_48

MO_49

MO_50

GNO_N

GNO_N

MO_61

CB03

VCC_2

GNO_N

5o_61

GNO_N

5o_54

5o_49

VCC_N

5o_43

5o_39

5o_40

MO_47

MO_51

MO_56

MO_60

MO-59

CBO_6

GNO_N

GNO_Q

WBENB

5o_62

5o_59

5o_57

5o_53

5o_51

5o_45

5o_44

5o_41

MO_53

MO_54

MO_57

CBOJ

CBO_5

CBO_2

CBO_O ~BRENB

5YNCLK

WBEFB

5o_60

BE7

5o_55

BE6

5o_50

5037

BE5

MO_55

MO_58

MO_62

MO_63

CBO_3

CBO_1

WB5EL

5YN5EL

WBFFB

5o_63

P7

5o_58

5o_56

P6

5o_52

5o_48

5o_46

A

B

0

E

F

G

H

J

K

L

N

P

R

T

U

G

H

MERRORB CBIN_6

CBIN_1

RBENB

ERRORB CBIN_3

E

K

L

RB5EL

RBHFB

5o_2

CBIN_2

RBRENB RBEFB

RBFFB

CBIN_7

CBIN_4

CBIN_O

5o_0

MO_O

CBIN_5

GNO_N

F

GNO_Q

VCC_Q

GNO_N

M

G208-1

~

C

M

Pin 1 reference

5.13

3

7

3

IDT49C466 Flow-thruEDCTM
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION
Pin Name

I/O

Description

Data Buses
SOO-63

I/O

System Data Bus is a bidirectional 64-bit bus interfacing to the system or CPU. When System Output
Enable, SOE, is high or Byte Enable, BEo-7, is low, data is input. The data is latched into the system
data (SO) latch when the System Data Input Latch Enable (SOILE) is low. The System Data Bus is
an output of the corrected memory data during a read operation. Corrected data can come from the
memory data (MO) output latch or the content of the read buffer. When the Read Buffer Select
(ROSEL) pin is low, the MD latch is selected. When RDSEL is high, the read buffer contents are
selected. When System Output Enable, SOE, is low and Byte Enable, BEa-7, is high, the SD bus output
drivers are enabled .

MDo-63

I/O

. Memory Data Bus is a bidirectional 64-bit bus interfacing to the memory _ During a read cycle, memory
data is input for error detection and correction. The data is latched in the memory data (MD) input latch
when the Memory Data Input Latch Enable (MDILE) is low. Data from the SD output latch or the read
buffer is is output on the Memory Data Bus on a memory write cycle.

CB10-7

I

Check Bit Inputs interface to the check bit memory.

CBSYNo-7

I

Check Bit or Syndrome Output, when MOE is low, is enabled. When CBSEL is high, the check bits
are selected. When CBSEL is low, the syndrome bits are selected.

I/O

Parity input/output for bytes 0 to 7. Byte parity is generated from the system data bus data word and
output on the PO-7 pins. These pins are parity inputs when the corresponding Byte Enable (BE) is low,
and are used to generate the parity error Signal (PERR). The parity select bit (PSEL) of the mode
register selects odd or even parity.

SOE

I

System Output Enable enables system data output drivers if the corresponding Byte Enable (BEo-7)
is high.

BEo-7

I

Byte Enable is used to enable the System Data outputs for a particular byte in systems using separate
III memories. For example, if BE1 is high, the System data outputs for byte 1 (S08-15) are enabled.
In systems using common I/O memories, the BEo-7 pins also control the data byte mux. If a particular
BE is high, data is feed back to the memory data bus and used for check bit generation of that byte.
This is used during partial word write operations and rewriting corrected data to the memory. If a
particular BE is low, data from the system data latch is directed to the memory data bus and used for
check bit generation of that byte, used in writing new data during a partial word write operation. BE
is buffered with the data in the write buffer.

MOE

I

Memory Output Enable, when low, enables the output buffers of the memory data bus (MD) and the
check bit output bus (CBO).

MILE

I

Memory Input Latch Enable on the high to low transition latches data at the MD inputs and the
checkbits at the CBI inputs. The latch is transparent when MILE is high.

MOLE

I

Memory Output Latch Enable latches both the data at the output of the byte mux and the output of the
checkbit generator on the low to high transition of MOLE. The latch is transparent when MOLE is low.

WBSEL

I

Write Buffer Select, when high, the output of the write buffer is selected. The WBSEL is low, the SD
input latch is selected.

SDILE

I

System Data Input Latch Enable latches data on the system data bus (SO) into the SD input latch on
the low to high transition. When SDILE is high, the SD input latch is transparent.

WBEN

I

Write Buffer Enable allows system data (SD) input to be written to the write buffer.

WBREN

I

Write Buffer Read Enable, when low, the output of the write buffer is enabled.

RSo-1

I

Reset and FIFO Select pins set both read and write buffer FIFOs.
RSo-1
Function
00
Reset 16-deep FIFO or first a-deep FIFO
Reset second a-deep FIFO
10
01
Select 16-deep FIFO or first a-deep FIFO
11
Select second a-deep FIFO

RBSEL

I

Read Buffer Select when high the output of the read buffer is selected. When low, the MD latch output
is selected.

PO-7

Control Inputs

2617tbl01

5.13

4

II

IDT49C466 Flow-thruEDCTM
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION (Cont.'d)
Pin Name

110

Description

RBEN

I

Read Buffer Enable when low allows data to be written into the read buffer on the low to high transition
of the memory clock.

RBREN

I

Read Buffer Enable, when low, the output of the read buffer is selected.

CBSEl

I

Checkbit Select, when high, selects the checkbits at the CBSYNo·7 output. When CBSEl is low, the
syndrome bits are selected.

MelK

I

Mamory Clock. On the low to high transition of MClK, data is written to the read buffer when HHEN
is low.

SClK

I

System Clock. On the low to high transition of the system clock, data is read from the read buffer when
RBREN is low. Data on the system data bus is written into the write buffer when WBEN is low on the
low to high transition of SClK.

WBEF

0

Write Buffer Empty Flag, when low, indicates that there is only one more data word at the output of
the write buffer. Further read operations are then inhibited. At reset, the WBEF is set low.

WBFF

0

Write Buffer Full Flag, when low, inhibits further write operations to the buffer and indicates that the
write buffer is full. After a reset, WBFF is high, and remains high until for 16 consecutive write
operations without any read operations in the 16-deepconfiguration; or a consecutive write operations
in the dual a-deep configuration.

RBEF

0

Read Buffer Empty Flag, when low, indicates that there is only one more data word at the output of
the read buffer. Further read operations are then inhibited. At reset, the RBEF is set low.

RBHF

0

Read Buffer Half-full Flag, when low, indicates that there are eight or more data words (in the 16-deep
configuration) or four or more data words (in the dual a-deep configuration) in the read buffer. The
flag will return high when less than eight (or four) data words are in the buffer.

RBFF

0

Read Buffer Full Flag, when low, inhibits further write operations to the buffer and indicates that the
read buffer is full. After a reset, RBFF is high, and remains high until for 16 consecutive write
operations without any read operations in the 16-deep configuration; or a consecutive write operations
in the dual a-deep configuration.

ERR

0

Error Flag. In normal mode (Mode 3), when ERR is low, a data error is indicated. The ERR is not
latched internally.

MERR

0

Multiple Error. In normal mode (Mode 3), when MERR is low, a multiple data error is indicated. The
MERR is not latched internally.

PERR

0

Parity Error. Parity error signal, when low, indicates a parity error on the system data bus input.

Clock Inputs

Status Outputs

Power Supply
Vee

P

Power Supply Voltage, +5 volts.

GND

P

Ground.
26171bIOl

5.13

5

G®

CMOS SINGLE 8-BIT PaletteDACTM
FOR TRUE COLOR APPLICATIONS

PRELIMINARY
IDT75C457

Integrated Device Technology, Inc.

FEATURES

DESCRIPTION

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

The IDT75C457 is a single channel 8-bit video DAC with
on-chip, dual-ported color palette memory. This chip is
specifically designed forthe display of true-color, high resolution
graphics. The architecture eliminates the ECl pixel interface
by providing multiple TTL-compatible pixel ports and by
multiplexing the pixel data on-chip.
Features included on-Chip are programmable blink rates,
bit plane masking and blinking, as well as color overlay
capability. The IDT75C457 generates an RS-343Acompatible
video output that is capable of driving a doubly terminated 75
ohm coaxial cable directly. A Pll current output enables
synchronization of three I DT75C457s, thus allowing display of
true-color images.
The IDT75C457 military PaletteDACs are manufactured in
compliance with the latest revision of Mll-STD-883, Class B,
making them ideally suited to military temperature applications
demanding the highest levels of performance and reliability.

165/135/125/110/80 M Hz operating speeds
Pin- and function-compatible with Brooktree Bt 457
Fixed pipeline delay: No external circuitry required
50ns read access time
Integral and differential linearity < 1/2 lSB
Single 8-bit DAC
256 x 8 Dual-Ported Color Palette RAM
4 x 8 Dual-Ported Overlay Palette RAM
Multiplexed TTL pixel and overlay inputs
RS-343A compatible output
Single 5 volt power supply
84-pin PGA and PlCC packages
Typical power dissipation: 1000mW
CEMOSTM Monolithic construction
Military product is compliant with Mll-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
ClK

ClK

VREF

II

FSADJ

>-----+--.

[0--+-----,

COMP

40
P()-P7{A-E}

B
l
I

R
E

N
K

10

loUT

A

o

D~Dl1{A-E}

2

SYNC
BLANK

_+-_-....
_+-_-....

BLINK REG
READ REG
TEST/CONT

Pll

1+----------+-------'
DATAIADDR

ADDR REG

COMMREG ~----~----~

8

CO

C1

RiW CE

VIlA

AGND

2523 drw 01

CEMOS and PaleneDAC are trademarks of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE ~ANGES
e 1990 Integrated Device Technology. Inc.

5.14

JANUARY 1990
DSC-50091-

1

.IDT75C457 CMOS Single 8-BIT PaietteDAC 111

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
A

12

s

COMP AGND

C

D

E

F

G

H

VAA

F7{D}

F7{S}

P6{E}

P6{C}

P6{S}

VAA

F7{E}

F7{C}

F7{A}

P6{D}

P6{A}

11

PlL

10

lOUT FSAO. VREF

9

VAA

NC

8

Cl

RJW

7

VAA

CO

AGND

K

l

M

PS{E}

PS{C}

PS{S}

P4{E}

PS{O}

PS{A}

P4{C}

P4{A}

P4{D}

P4{S}

SYNC

1BCANi< D5
ClK

ClK

VAA

VAA

P3{E}

AGND

G84-2

6

AGNO AGNO

s

CE

0,

P3{C}

P3{0}

4

l:\)

D5

P3{A}

P3{S}

3

04

[Q

P2!A}

P2!C}

P2!E}

2

Os

OJ

~

ALIGNMENT MARK

~
Ol{){S} Ol{){E} Oll{S} Oll{E} PolS}

PolO}

Pl{A}

Pl{O}

Pl{E}

P2!O}

Ol{){A} Ol{){C} Ol{){O} Oll{A} OLl{C} OLl{O} PolA}

PolC}

PolE}

Pl{S}

Pl{C}

P2!S}

PGA

2523 drw 02

TOP VIEW

5.14

2

IDTI5C457 CMOS Single a·BIT PaietteDAC 111

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

uuuuuuuuuuwwuwuuuuwuu
P2{A}

Pl{E}
Pl{O}
Pl{C}
Pl{B}
Pl{A}
PolE}
PolO}
Po{C}
Po{B}
Po{A}
OL1{E}
OL1{O}

74737271 70696867666564636261 60595857565554
75
53 [:

:J
:J 76

:J

52 C
51 [:

77

50
49
48
47
46
45

:J
:J
:J
:J
:J

78
79
80
81
82
:1 83
:1 84

::::J

1

J64·1

:J 2

[:
[:
[:
[:
[:
[:

44 C
43 r:
42 [:

P4{E}
P5{A}
P5{B}
P5{C}
P5{O}
P5{E}
P6{A}
P6{B}
P6{C}
P6{O}
P6{E}
P7{A}
P7{B}

41 r:
40 r:
39 [:

OL1{A}

:1 3
:J 4
:J 5
:J 6

38 [:

P7{E}

OLo{E}

:J

37 [:

VAA

36 r:
35 [:

VAA

OL1{C}
OL1{B}

OLo{O}
OLo{C}
OLo{B}
OLo{A}

7
:J 8

:1 9
:J 10
:J 11

34 r:
33· [:

P7{C}
P7{O}

AGND

II

AGND
VREF

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
I I II II II"
I. I I I I II II II I I I I II I I I I II I I I I II
-~-~----------------­

II

2523 drw 03

PLCC
TOP VIEW

5.14

3

IDT75C457 CMOS Single 8-BIT PaietteDAC 111

MILITARY AND COMMERCIAL TEMPERATURE RANGES

GENERAL INFORMATION
The I DT75C457 triple 8-bit PaietteDAC is a highly integrated
building block which interfaces a relatively low bandwidth
frame buffer memory to analog RS-343A high bandwidth
output.
The IDT75C457 includes a look-up table for updating color
information and other graphics applications. The basic
functional blocks are the microprocessor bus interface, the
frame buffer memory interface and multiplexer, a dual-port
RAM wilh one RN" port, one high-speed RIO port and one 8bit video speed DAC.

after a read orwrite cycle to location $FF. When accessing the
overlay palette, the address register increments to $04 following
a read or write cycle to overlay color three.
In RGB mode, writing color data entails the MPU loading
the address register with the address of the color palette
location or overlay palette location to be modified. The MPU
performs th ree successive write cycles (eight bits each of red,
green or blue), using CO or C1 to select eitherthe color palette
or the overlay palette. After the blue write cycle, the address
register then increments to the next location which the MPU
may modify by simply writing another sequence of red, green
or blue data. Reading color data is similar to writing except the
MPU executes the read cycles.
RGB mode is useful if only an eight-bit data bus is available.
Each IDT75C457 is programmed to be red, green or blue
PaletteDAC, and will respond only to the assigned read or
write cycle. In this application, the IDT75C457s share a
common eight-bit data bus. The CE inputs of all three
IDT75C457s must be asserted simultaneously only during
color read/write cycles and address register write cycles.

MICROPROCESSOR BUS INTERFACE
The IDT75C457 supports a standard microprocessor bus
interface, allowing the MPU direct access to the internal
control registers and color/overlay palettes. The dual-port
color palette RAM and overlay registers allow color updating
without contention with the display refresh process.
The bus interface consists of eight bidirectional data pins,
Do-D7, with two control inputs, CO and C1, a read/write
direction input, R/W, and a clock input, CE. All data and control
information are latched on the falling edge of CE, as shown in
Figure 3. All accesses to the chip are controlled by the data
in the address register combined with the control inputs CO,
C1 and R/W, depicted in the Truth Table (Table 1).
An access to a control register requires writing a 4 through
7 into the address register (CO = C1 = 0) and then writing or
reading data to the selected register (CO = 0, C 1 = 1). When
accessing the control registers, the address register is not
changed, facilitating read-modify-write operations. If an invalid
address is loaded into the address register, data written is
ignored or invalid data is read out.
It is also possible to access the color palette information.
The palette is organized as 256 address with 8 bits of red, blue
or green information. Additionally, there are two extra
addresses aSSigned to overlay information, yielding a total
memory size of 260 x 8.
There are two modes of acceSSing palette entries on the
IDT75C457, "Normal", and "RGB".
In Normal mode, writing color data entails the MPU loading
the address register with the address of the color palette
location or the overlay palette location to be modified. The
MPU performs a color write cycle, using CO and C1 to select
either the color palette or the overlay palette. The address
register then increments to the next address location which
the MPU may modify simply by writing another color. Reading
color data is similar to writing, except the MPU executes read
cycles.
Normal mode is useful if a 24-bit data bus is available, as
24 bits of color information (eight bits each of red, green, and
blue) may be read or written to three IDT75C457s in a single
MPU cycle. In this application the CE inputs of all three
IDT75C457s are connected together. If only an eight-bit data
bus is available, the CE inputs must be individually selected
during the appropriate color read orwrite cycle (red CE during
red write cycle, blue during blue write cycle, etc.). When
accessing the color palette the address register resets to $00

Address Register
Data

X
$OO-$FF
$00
$01
$02
$03
$04
$05
$06
$07

C1

CO

0
0

0

1
1
1
1

1
1
1

1

1
1
1
1
1
0
0
0
0

Access
Address Register
Color Palette
Overlay Color 0
Overlay Color 1
Overlay Color 2
Overlay Color 3
Read Mask Register
Blink Mask Register
Command Register
Test Register
25231b10l

Table 1. Truth Table for MPU Operations

When accessing the color palette, the address register
resets to $00 after a blue read or write cycle to location $FF.
When accessing the overlay palette, the address register
increments to location $04 following a blue read or write cycle
to overlay color three. To keep track of the red, green and blue
read/write cycles, the address register has two additional bits
(ADDRa, ADDRb) that count module three. They are reset to
owhen the MPU reads or writes to the address register. The
MPU does not have access to these bits. The other eight bits
ofthe address register (ADDR 0-7) are accessible to the MPU.

FRAME BUFFER INTERFACE
The frame buffer interface consists of five 8-bit input ports
which correspond to five consecutive pixels. In addition, there
are two extra bits per port which may be used for overlay
information. To reduce the bandwidth requirements for the
pixel data, the IDT75C457 latches 4 or 5 pixels (the multiplex
factor is programmable to 4 or 5 by bit 7 of the command
register) on each rising edge of LD. The color and overlay
information is internally multiplexed atthe pixel clock frequency,

5.14

4

IDT75C457 CMOS Single 8-BIT PaietteDAC 111

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ClK, and sequentially output. This arrangement allows pixel
data to be transferred at a rate 4 or 5 times slower than the
pixel clock. Typically, lD is the pixel clock divided by 4 or 5 and
is used to clock data out of the frame buffer memory.
As shown in Figure 2, sync, blank, color and overlay
information are latched on the rising edge of lD. Up to 40 bits
of color information are input through POoP? {A-E} and up to 10
bits of overlay information are input through Olo-Ol1 {A-E}.
Both sync and blank have separate inputs, SYNC and BLANK,
respectively. The IDT75C457 outputs color information on
each clock cycle. Four or five pixels are output sequentially,
beginning with the {A} information, then the {B} information,
until the cycle is completed with the {D} or {E} information. In
this configuration, sync and blank are limited to multiples of
four or five clock cycles.
The multiplexing factor, 4:1 or 5:1, is programmable from
the command register, bit 7. In the 4:1 mode, the {E} color and
overlay inputs are not used and the lD clock should be
CLOCK divided by 4. The {E} color and overlay inputs must
be connected to a valid logic level.
The overlay inputs (Olo-Ol1) have the same timing as the
pixel inputs (Po-P?). It is possible to use additional bit planes
or external logic to control the overlay selection for cursor
generation.

•

5.14

5

IDT75C457 CMOS Single 8-81T PaietteDAC 111

MILITARY AND COMMERCIAL TEMPERATURE RANGES

INTERNAL MULTIPLEXING

Video Generation, DACs

lD is typically ClK divided by fourorfive and it latches color
and overlay information on every rising edge, independent of
ClK. A digital Pll allows lD to be phase independent of ClK.
The only restriction is that only one rising edge of lD is allowed
to occur per four (4:1 multiplexing) or five (5:1 multiplexing)
ClK cycles.

On every ClK cycle, the selected a bits of color information
from the Color Palette RAM are presented to the a-bit D/A
converters. The IDT75C457 uses a 5 x 3 segmented approach
where the five MSBs of the input data are decoded into a
parallel ''Thermometer'' code which produces thirty two "coarse"
output levels. The remaining three lSBs of input data drive
three binary weighted current switches with a total contribution
of one-thirty second of full scale. The MSB and lSB currents
are summed ::It the output to produce 256 levels.
The SYNC and BLANK inputs are pipelined to maintain
synchronization with the pixel data. Both inputs drive
appropriately weighted current switches which are summed at
the output of the. DACs to produce the specific output levels
required by RS-343, as shown in Figure 3. Table 3 details the
output levels associated with SYNC, BLANK and data.

Color Palette
On the rising edge of each ClK cycle, eight bits of color
information (Po·P?) and t',,'.. o bits of overlay information
(Olo-OU) for each pixel are processed by the read mask,
blink mask and command registers. This information provides
the address to the dual-port color palette RAM. Note that Po
is the lSB when addressing the color palette RAM. The value
stored at a selected address determines the displayed color.
Through the use of the control register, individual bit planes
may be enabled or disabled for display and/or blinked at one
of four blink rates and duty cycles.
The blink timing is based on vertical retrace intervals which
are defined by at least 256 lD cycles since the last falling edge
of BLANK. The color changes during this normally blanked
time.
The processed pixel data is then used to select which color
palette entry or overlay register is used to provide color
information. Table 2 illustrates the truth table used for color
selection.
CR6(1)

OL1

OLo

P7·PO

1
1

0
0

0
0

$00
$01

1
0

x
x
x

0
0
0
1
1

0
0
1
0
1

$FF
$xx
$xx
$xx
$xx

Monitor Interface
The analog outputs of the IDT75C457 are high-impedance
current sources which are capable of directly driving a doubly
terminated 75Q coaxial cable to standard video levels. A
typical output circuit is shown in Figure 4.
Description
WHITE
DATA
DATA and SYNC
BLACK
BLACK and SYNC
BLANK
SYNC

Palette Entry
Color Palette Entry $00
Color Palette Entry $01

B

DAC Data

lOUT (mA)

1
1

1
1
1
1
1
0

$FF
Data
Data
$0
$0

Data + 9.05
Data + 1.44
g.. 05
1.44

X
X

7.62
0

0
1

0
1
0

0

26.67

NOTE:
1. Typical values with full scale lOUT = 26.6?mA, RSET = 523Q,
VREF = 1.235V, S is SYNC, B is BLANK.

Color Palette Entry $FF
Overlay Color 0
Overlay Color 1
Overlay Color 2
Overlay Color 3

NOTE:

5

2523 tbl 03

Table 3. Video Output Truth Table

25231b102

1. CR6 is bit 6 of the Command Register.
Table 2. Palette and Overlay Select

5.14

6

IDT75C457 CMOS Single 8-BIT PaietteDAC 1>1

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

lOUT

rnA

V

26.67

1.000

NORMAL HIGH (WHITE)

7.62

256 "GRAY lEVELS"

92.5 IRE

.
9.05

····r·······························

0.340
0.285

..... 1...........
7.5 IRE

1

NORMAL lOW (BLACK)

-----~----------------40 IRE
____ _ , _______________________ .10-_ _ _,_______________ _

0.00

0.000
2523 drw04

Figure 1. Composite Video Output Waveform

II

1 + - - - - - - - - - - PIPELINE DELAY -----------~.I
ClK

PO-P7.

ala-all.
SYNC
OUTPUT DELAY
lOUT

{8}

PLL

------------------------------------------~

2523 drw 05

Figure 2. Pixel Timing

5,14

7

IDT75C457 CMOS Single 8-BIT PaietteDAC TIl

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ts
tH

Rm
CO,C1
14--~

HI-ZTO DATA BUS DRIVEN

~---t-----~

CHIP ENABLE TO DATA VALID

00-07,

DATA VALID

READ

ts

00-07,
WRITE
2523 drw 06

Figure 3. Data Bus Timing

COMP

VAA

VREF

IDT75C457
AGND

FSADJ
RSET
VIDEO OUT

lOUT

2523 drw07

Figure 4. Typical Application

5.14

8

IDT75C457 CMOS Single 8-BIT PaietleDAC 1M

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTIONS
Pin Name

Description

Data Bus
00-07

a-bit, bidirectional data bus. Oata is input and output over this bus and the flow is controlled by RIW and
CE. 07 is the most significant bit.

CE

Chip Enable Input. The chip is enabled when this control pin is lOW. Ouring a write cycle (RIW lOW),
the data present on 00-07 is internally latched on the lOW-to-HIGH transition of this pin.

R/W

ReadlWrite Control input. The ReadlWrite input is latched on the HIGH-ta-lOW transition of CE and
determines the direction o.!Jhe bidirectional data bus, 00-07. If RiW is HIGH during the falling edge of CE,
a read cycle occurs. If R/W is lOW dud!!g the falling edge of CE, a write cycle occurs and, additionally,
00-07 are latched on the rising edge of CE.

CO,C1

Register Control inputs. CO and C1 determine which register or palette entry is accessed during a read or
write cycle. These inputs are latched on the HIGH-to-lOW transition of CEo

Pixel
ClK,ClK

Pixel Clock Inputs. These inputs are differential and may be driven by ECl operating from a +5V supply.
The clock frequency is normally the system pixel clock rate.

lO

load Clock input. The load Clock is normally ClK divide~or 5 (determined by the Control Register
bit 7). The pixel data, PO-P7 {A-E} and ala-all {A-E}, BLANK and SYNC are internally latched on the
lOW-to-HIGH transition of lO.

PO-P7 {A-E}

Pixel Input Oata. These inputs provide the address input to the color palette RAM. The data stored at a
particular address is the color output by the OAC. Four or five consecutive pixels, as determined by bit 7
in the Command Register, are internally latched on the lOW-to-HIGH transition of lO. The pixels are
output sequentially, first {A} then {B}. After all four or five pixels have been output, the cycle repeats.
Unused inputs must be connected to a valid logic level.

ala-all {A- E}

Pixel Overlay Inputs. The Overlay inputs have the same timing as PO-P7 and select between either the
color palette or the overlay palette. When the overlay palette is selected, the pixel information PO-P7 {A-E}
is ignored. Bit 6 of the command register determines if Overlay = 0 displays overlay color 0 or the color
palette entry. See Table 2 for details.

BLANK

Composite Blank Input. A lOW on this input forces the analog ou~ts (lour) to the blanking level. The
BLANK input is internally latched on the lOW-to-HIGH transition of lO. This input overrides all other pixel
information.

SYNC

Composite Sync Input. A lOW on this input subtracts ~imately 7mA from the lOG analog output and
overrides no other pixel information. For the correct SYNC level, this input should be lO~only when
BLANK is also lOW. The SYNC input is internally latched on the lOW-to-HIGH transition of lO.

Analog
AGND

Analog Ground Power Supply, OV.

VM

Analog Power Supply, 5V.

VREF

Voltage Reference Input, 1.235V. This input supplies a reference voltage for the OAC circuitry. Care must
be taken to correctly decouple this voltage because noise on this pin will couple directly to the OAC
outputs.

FSAOJ

Full-Scale Adjust Input. The current flowing from this pin to AGND is directly proportional to the full-scale
analog output current. Normally, a resistor is connected between this pin and AGND. The voltage on this
pin is approximately equal to VREF. The relationship lOUT (rnA) = 11.294 x VREF (V)/RSET (Kn).

lOUT

DAC current output.

CaMP

Compensation Input.
amplifier.

Pll

Phase lock loop Current Output. This high impedance current source is used to enable multiple
IDT75C457s to be synchronized with sub-pixel resolution when used with an external PlL. A logic one on
the BLANK input results in no current being output onto this pin, while a logic zero results in the following
current being output:

This pin provides the ability to compensate the internal reference operational

Pll (rnA)

= 3227 • VREF

(V)/RSET (ohm).

If sub-pixel synchronization of multiple devices is not required, this output should be connected to GNO
(either directly or through a register up to 150 ohms).
2523 tbl 04

5.14

9

II

IDT75C457 CMOS Single 8-BIT PaietleDAC TU

-

R
E
A
D
M
A
S
K

MILITARY AND COMMERCIAL TEMPERATURE RANGES

B
L
I
N
K
M
A
S
K

.... -

,

256

OVERLAY
LOOK-UP
TABLE

,

,2 ..

~

'"
,

r"

Read Mask Register
The Read Mask Register is accessed by reading or writing
with the Address Register= $04, CO = 0 and C1 = 1 (see Table
1). It internally ANDs the pixel information with a bit from the
register before the color palette selection, effectively enabling
(HIGH) or disabling (LOW).the entire pixel plane. The Read
Mask Register may be read or written at any time. RMR7
(Read Mask Registerbit7) correspondsto D7 (Data Bus bit 7).

,

I

DATA

I

__i

I
DAC

8

8
2523 drw08

Figure 5. IDT75C457 Register Block Diagram

Command Register
The Command Register is accessed by reading or writing
with the Address Register =$06, CO =0 and C1 = 1 (see Table
1). It internally ANDs the pixel information with a bit from the
register before the color palette selection, effectively enabling
(HIGH) or disabling (LOW) the entire pixel plane. The Read
Mask Register may be read or written at any time. RMR7
(Read Mask Register bit 7) corresponds to D7 (Data Bus bit 7).

CR1

Multiplex Select. This bit selects between 4:1
(CR7 = 0) or 5:1 (CR7 = 1) multiplexing. When
using 4:1 multiplexing the {E} inputs are never
used and must be connected to a valid logic
level.

8

00-D7

CRO

CR7

j

COMMREG

~--

Color Palette RAM Enable. This bit specifies
whether to use the Color Palette or the Overlay
Palette when OLo = OL 1 = LOW.

4x8

,

~

CR6

X8

BLINK REG

AD DR REG

Blink Rate Select. These bits select blink rates
based on Vertical Sync cycles, defined as more
than 256 LD cycles during BLANK.

COLOR
LOOK-UP
TABLE

,8 ...

READ REG

TEST/CaNT

CR4, CR5

po-

OLo Display Enable. This bit isANDed internally
with the data from OLo prior to the palette
selection. If CRO is LOW, the internal OLo bits
are set LOW, allowing only overlay colors 0 and
2 to be selected.

Blink Mask Register
The Blink Mask Register is accessed by reading or writing
with the Address Register= $05, CO =0 and C1 = 1 (see Table
1). Each register bit causes the corresponding pixel bit (PoP7) to internally switch between the input value and 0 at the
blink rate specified in the Command Register. For this
function to work, the corresponding enable bit in the Read
Mask Register must be set HIGH. The Blink Mask Register
may be read or written at any time. BMR7 (Blink Mask
Register bit 7) corresponds to D7 (Data Bus bit 7).
Test/Control Register
The Test/Control Register is accessed by reading or writing
with the Address Register =$07, CO = 0 and C1 = 1 (see Table
1). This register allows the MPU to read the a input bits of the
DAC. It may be written to or read by the MPU at any time, and
is not initialized. The register bits are defined as follows:

OL 1 Display"Enable. This bit is ANDed internally
with the data from OL 1 prior to the palette
bits
selection. If CR1 is LOW, the internal
are set LOW, allowing only overlay colors 0 and
1 to be selected.

au

CR2

OLo Blink Enable. If this bit is set HIGH, the OLo
bit is internally switched between the value input
and 0 at the rate specified by the CR4 and CR5
bits. CRO must be set HIGH for this function.

CR3

OL 1 Blink Enable. If this bitis set HIGH, the
bit is internally switched between the value input
and 0 at the rate specified by the CR4 and CR5
bits. CR1 must be set HIGH for this function.

au

5.14

D7-D4

DAC input data (one nibble)

OJ

Upper (LOW) or Lower (HIGH) nibble select

D2

Blue enable

D1

Green enable

Do

Red enable
2523 tbl 05

When writing to the register, upper four bits (D4-D7) are
ignored.
To use the tesVcontrol register, the MPU writes to it,
specifying the upperor lower nibble of the a-bit input information
to the DAC. When the M PU reads the register, the four bits of
color information from the DAC inputs are contained in the
upperfour bits of the register, and the lower four bits contain
whatever was previously written to the register. Note that
either the CLOCK must be slowed down to the MPU cycle
time, orthe same pixel and overlay data must be presented to
the device during the entire MPU read cycle.
10

IDT75C457 CMOS Single 8·BIT PalelteDAC TIl

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

The red, green and blue enable bits are also used to specify
the mode of writing color data to, and reading color data from,
the IDT75C457. If all three enable bits are a logic zero, each
write cycle to the color palette orthe overlay palette loads eight
bits of color data. During each read cycle of the color palette
or the overlay palette, eight bits of color data are output onto
the data bus. If a 24·bit data bus is available, this enables
three IDT75C457 to be accessed simultaneously.
If any of the red, green, blue bits are a logic one, the
IDT75C457 assumes the MPU is reading or writing color
information using red, green, blue cycles, such as are used on
the IDT75C458. Setting the appropriate enable bit configures

CR7

CR6

CR5

CR4

CR3

CR2

the IDT75C457 to output or input color data only for the color
read/write cycle corresponding to the enabled color. Thus, if
the green enable bit is a logic one, and a red, green, blue write
cycle occurred, the IDT75C457 would input data only during
the green write cycle. If a red, green, blue read cycle occurred,
the IDT75C457 would output data only during the green read
cycle. Note that CEmustbe a logiczeroduring eachofthe red,
green, blue cycles. One, and only one, of the enable bits must
be a logic one. This mode of operation is useful where only an
8·bit data bus is available and the software drivers are written
for RGB operation.

CR1

CRO

Tl----11

0 disable OLo
enable Ow

o disable OL1
~------t 1 enable OL1
1--________--1

0 blinking of Ow disabled
1 blinking of Ow enabled

1---------------1

0 blinking of 011 disabled
1 blinking of 011 enabled

1--________________--1

00 16 Vsync on 148 Vsync off
01 16 Vsync on 116 Vsync off
10 32 Vsync on 132 Vsync off
64 Vsync on 164 Vsync off

11

1-------------------------1

.....--------------------------i

o

Use overlay color 0
1 Use color palette 0

0 4:1 Multiplex
1 5:1 Multiplex
2523 drw 09

Figure 6. Command Register Designations

5.14

11

I

IDT75C457 CMOS Single 8-BIT PaietteDAC TIl

RMR?

RMR6

RMR5

MILITARY AND COMMERCIAL TEMPERATURE RANGES

RMR4

RMR3

RMR2

RMR1

a disable A>
1 enable Rl

a

disableP,

I - - - - - - - - - f 1 enableP1

"--------------1

a

disable P2
1 crl:::b!c Pz

a

disable P3
1 enable PJ

a

disable P4
1 enable P4

a

disable Ps
1 enable Ps

a

disable PI;
1 enable PI;

a

disable P7
1 enable PI
2523 drw 010

Figure 7. Read Mask Register Designations

BMR?

BMR6

BMR5

BMR4

BMR3

BMR2

BMR1

BMRa

~

a

disable A> blinking
1 enable Rl blinking

a

disableP, blinking
1 enableP, blinking

a

disable P2 blinking
1 enable P2 blinking

a disable P3 blinking
1 enable PJ blinking

a

disable P4 blinking
1 enable ~ blinking

a

disable Ps blinking
1 enable Ps blinking

a

disable PI; blinking
1 enable R; blinking

a

disable P7 blinking
1 enable PI blinking
2523 drw 11

Figure 8. Blink Mask Register Designations

5.14

12

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

IDT75C457 CMOS Single 8·BIT PaietteDAC 1loI

ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

Value

Unit

Power Supplies
Measured to AGND

-0.5 to +7.0

V

Measured to AGND

-0.5 to VAA +0.5

V

Applied Voltage (2)

Measured to AGND

-0.5 to VAA +0.5

Applied Current (2,3,4)

Externally forced

-1.0 to +6.0

Analog Output Short
Circuit Duration

Analog output High
to AGND

VAA

Input Voltage
Applied Voltage (2)

Output

Indef

V
mA
s

Temperature
Operating

Military

-55 to +125

Ambient

Commercial

oto +70

°C

Storage

Military

-65 to +150

°C

Commercial

-55 to +125

°C

°C

NOTES:
252311>1 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to Absolute
Maximum Rating conditions for extended periods may affect reliability. Absolute
Maximum Ratings are limiting values applied individually while all other parameters
are within specified operating conditions. Functional operation under any of these
conditions is NOT implied.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current when flowing into the device.

5.14

I

13

IDT75C457 CMOS Single 8·BIT PaietteDAC TIl

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS
Symbol

Min.

Typ.

Max.

VM

Power Supply

Parameter

Measured to AGND

Test Conditions

4.75

5.0

5.25

V

1M

Power Supply Current

VM = Typ., Static

-

120

-

rnA

-

VM + 0.5

V

O.B

V

VIH(1)

Input Voltage HIGH

2.0

Vil (1)

Input Voltage LOW

AGND ·0.5

Unit

VCIH

Clock Input Voltage HIGH

VM·1.0

-

VM + 0.5

V

VCll

Clock Input VoltagA LOW

AGND - 0.5

-

VAA - 0.6

V

IIH

Input Current HIGH

VIN = 2.4V

-

-

1

JlA

I Il

Input Current LOW

VIN = O.4V

-

-

·1

JlA

VOH

Output Voltage HIGH

VM = Min., IOH = -BOOJlA

2.4

-

-

V

VOL

Output Voltage LOW

VM = Min., IOl = 6.4rnA

-

-

0.4

V

loz

Output 3-State Current

-

-

10

JlA

NOTE:
1. All digital inputs except elK and CCK.

2523 tbl07

AC ELECTRICAL CHARACTERISTICS
Following conditions apply unless otherwise specified:
TA = O°C to +70°C (Commercial Temperature Range)
TA = -55°C to +125°C (Military Temperature Range)
VAA = 5.0V ±5%
TIL Inputs, Vil = OV, VIH = 3V, riselfall time <5ns
ClK Inputs, VIH = VAA - 1.0V, Vil = VAA - 1.6V, rise/fall time <2ns
Timing reference points at 50% of signal swing
Symbol

FCLK

Parameter

Clock Frequency

75C457·165(1;

75C457·135(1)

Min.

Max.

Min.

Max.

-

165

-

135

0

-

0
15

-

75C457·125
Min.
Max.

75C457·110
Min.
Max.

75C457·80
Min.
Max.

Unit

-

110

-

80

MHz

28

-

20

MHz

0
15

-

0

-

15

-

ns
ns

25

-

ns
ns

75
15

ns
ns
ns

5
5
50

-

-

20
20

-

ns
ns
ns

-

125

0
15

-

50
10

-

FClD

LD Clock Frequency

tcs
tCH

Control Set·up Time, CO, C1, RNY
Control Hold Time, CO, C1, RNY

tCEH

CE HIGH Time

20

20

-

25

tCEL
tCEZO

CE LOW Time
CE to Data Bus Driven

30
10

-

30

-

50

-

10

-

10

tCED

CE to Data Valid

30

-

30

-

50

-

CE to Data Bus Hi-Z

15

15

15

-

twos
tWDH

Write Data Set·Up Time
Write Data Hold Time

30
0

30

-

-

15

-

-

-

50

tCEOZ

-

35

-

0

tCLKCY

Clock Cycle Time

6

7.4

-

8

tCLKPl
tClKPH

2.8
2.8
24

-

3.2
3.2

-

-

3.0
3.0

4
4

tLDCY

Clock Pulse Width LOW
Clock Pulse Width HIGH
LD Cycle Time

-

-

50

0

-

35

-

-

29

31

tLDPH

LD Pulse Width HIGH

10

-

tLDPL
tps

LD Pulse Width LOW

10

-

12
12

-

Pixel Data Set·up Time

2

-

3

-

-

-

2

-

2

2

-

4

1

-

3

Pixel Data Hold Time

2

-

ns

Dynamic Supply Current
Commercial Temp.

-

270

-

250

-

230

-

210

-

190

mA

Dynamic Supply Current
Military Temp.

-

-

-

-

-

260

-

240

-

220

mA

tPH
IMD
IMD

15

41

34

-

13
13
3

32

-

25

0

9

35
15
15

-

50
10

0
12

ns

ns
ns
ns
ns
ns

-

2523 till 08

NOTE:
1. 165 and 135 specification over commercial temperature only.

5.14

14

IDT15C457 CMOS Single 8-81T PaietteDAC T10I

MIUTARV AND COMMERCIAL TEMPERATURE RANGES

ANALOG OUTPUT DC ELECTRICAL CHARACTERISTICS
Symbol

Parameter

Min.

Typ.

Max.

Unit

Res

Resolution

Test Conditions

-

8

-

bits

ILSB

LSB Current Size

-

69.1

-

~A

1/2

±1

LSB

1/4

±112

LSB

I LSB Version

-

112

±1

LSB

1/2 LSB Version

-

1/4

±1/2

LSB

-1.0

-

1.2

Lr

I LSB Version

1/2 LSB Version
LD

Voc

Output Compliance Voltage

RAOUT (2)

Output Impedance

CAOUT (2)

Output Capacitance

IREF

VREF Input Current

V

50
f

= 1MHz,

lOUT

= OmA

kn

8

12

pF
~A

10

EM

Matching Error (DAC to DAC)

PSRR

Power Supply Rejection
Ratio

-

2

5

50

-

%

dB

Iw(1)

Wh~e

Current

Measured to Blank

17.69

19.05

20.40

mA

IB(1)

Black Current

Measured to Blank

0.95

1.44

1.90

mA

IBLANK

Blank Current lOR, lOB

0

5

50

~A

IBLANK (1)

Blank Current lOG

6.29

7.62

8.96

mA

ISYNC

Sync Current lOG

0

5

50

~A

NOTES:

2523 tbl 09

1. RSET = 523n, VREF = 1.235V
2. This parameter is guaranteed but not tested in production.

•

ANALOG OUTPUT AC ELECTRICAL CHARACTERISTICS
Following conditions apply unless otherwise specified:
TA = O°C to +70°C (Commercial Temperature Range)
TA = -55°C to +125°C (Military Temperature Range)
VAA = 5.0V ±5%
TTL Inputs, VIL = O.BV, VIH = 2.0V, rise/fall time <5ns
ClK Inputs, VIH = VAA - 1.0V, VIL = VAA - 1.6V, rise/fall time <2ns
Timing reference points at 50% of signal swing
75C457-165(31
Symbol

Parameter

FCLK

Clock Frequency

tvo

Video Output Delay Time

tVT

Video Output Transition Time

ts

Video Output Skew

ts

Video Ouput Sening Time

75C457-135 (31

75C457-125

75C457-80

75C457-110

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

-

-

165

-

135

125

110

-

-

80

MHz

15

15

15

-

2

-

2

-

ns

1.8

-

-

1.7

-

15

1.5

-

-

-

-

0

<2

0

<2

-

-

15

0

<2

-

0

<2

<2

ns

7

8

-

50

50

100

-

100

-

100

-

-

100

-

ns

50

-

12

-

-

8

50

-

-

50

-

-

0

6

-

pV-s
clock

FT

Clock and Data Feedthrough

GE

Glitch Energy

CT

Crosstalk, DAC to DAC

tvp

Pipeline Delay

9

-

9

9

-

9

9

-

9

9

-

9

9

-

9

tPLL

PLL Delay Time

-

15

-

-

15

-

-

15

-

-

15

-

-

15

-

50

50

NOTES:

50

-

-

50
50
100

ns

pV-s
pV-s

ns
2523 tbll0

1. CL = 10pF, 10%-90% points.
2. This parameter is guaranteed but not tested in production.
3. 165 and 135 MHz over commercial temperature range only.

5.14

15

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

IDT75C457 CMOS Single a·BIT PaietteDAC 111

ClK

PO·P7,
OLo-OL1,
SYNC

m:ANR
lOUT

PLL

--------------------~

2523 drw 12

Figure 9. Video 1/0 Timing Diagram

tMPUCY

tcs
tCH --------t~

CO,C1

twos
00-07,
WRITE
2523 drw 13

Figure 10. MPU WRITE Timing Diagram

5.14

16

IDT75C457 CMOS Single a-BIT PaietteDAC TIl

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

tMPUCY

tcs
tCH --------I~

CO, C1

t4---I~ tCEOZ

tCEZO

Do-07,
READ
2523 drw 14

Figure 11. MPU READ Timing Diagram

ORDERING INFORMATION
IDT

xxxx

x

Device Iype

Power

X

speecr

X
Package

II

x
Processl
Temperature'
Range

I
I BLANK
~B
I

G
L------------i J

Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
Pin Grid Array
PLCC

l

COM

MIL

80 "" 80 ""
110 1110 1
125 125
peed in Megahertz
135
165

JJ
s

~---------------------------~: S
75C457

Standard Power
8-bit PaletteDACTM
2523 drw 15

5.14

17

tQ

lOT 75C458

CMOS TRIPLE 8-BIT
PALETTEDAC™

Integrated DeviceTechnoIogy.Inc.
FEATURES:

DESCRIPTION:

• 165/135/125/110/80MHz operating speed

The IDT75C458 is a triple 8-bit video DAC with on-chip, dualported color palette memory. This chip is specifically designed for
the display of high resolution color graphics. The architecture
eliminates the ECl pixel interface by providing multiple TTL-compatible pixel ports and by multiplexing the pixel data on-chip.
The IDT75C458 supports up to 259 simultaneous colors from a
palette of 16.8 million. Other features included on-chip are programmable blink rates, bit plane masking and blinking as well as a
color overlay capability. The IDT75C458 generates RS-343A compatible red, green, and blue video outputs which are capable of directly driving a doubly terminated 750 coaxial cable.
The IDT75C458 military DACs are manufactured in compliance
with the latest revision of MIL-STD-883, Class B, making them ideally suited to military temperature applications demanding the
highest level of performance and reliability.

• Fixed pipeline delay: 9 clock cycles
• 50ns read access time
• Integral and differential linearity < 1/2lSB
• Triple 8-bit DACs
• 256 x 24 Dual-Ported Color Palette RAM
• 4 x 24 Dual-Ported Overlay Palette RAM
• Multiplexed TTL pixel and overlay inputs
• RS-343A compatible RGB outputs
• CEMOS ™ monolithic construction
•
•
•
•
•

Single 5V power supply
84-pin PGA and PlCC packages
Typical power dissipation: 1000mW
Pin- and function-compatible with Brooktree BT458
Military product is compliant to Mll-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
CD<

ClK

VREF

FSADJ
. . . . - - - - - - - - - l l - - - COMP

m --+-----,
B

l
I
N

K

OLa-Oll {A-E}

R
E
A
D

>--+---i... lOs
>--1-- lOG

~--t---...

~--t---...

BLINK REG
READ REG
TEST REG
ADDR REG
COMM REG

CO C1 R/W CE

CEMOS and PaietteDAC are trademarks of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1989 Integrated Device Tehnology, Inc.

JANUARY 1989
DSC-5002/1

5.15

1

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1DT75C458 CMOS TRIPLE 8.BIT PALETTEDAC ™

PIN CONFIGURATIONS
A

12

B

COMF AGND

C

D

E

F

G

H

l

K

VAA

P 7{D} P 7{B} P6 {E} P6 {C} P6 {B} P5 {E} P5 {C

M

P5 {B} P4 {E}

11

lOB

AGND

VAA

P7{E} P7{C} P7{A} P6{D} P6{A} P5{D} P5{A} P4 {C} P4{A}

10

lOG

FSADJ VREF

P4 {D' P4 {B} ~

9

VAA

lOR

8

C1

R/W

7

VAA

CO

/t3EAffi m
CO<

ClK

VAA

VAA

G84-2
6

P3 {E} AGND

AGND AGND

5

a:

D7

4

D6

D5

P3 {C} P3 {D}
P3 {A} P3 {B}

A ALIGNMENT MARK
3

D4

D2

2

D3

D,

P2{A} P2 {C} P2 {E}

Do

Plo{B 9 l o{E 9l, {B Ol, {E Po{B} Po{D} P, {A} P, {D} P, {E} P2 {D}

II

Olo{A Olo{C Plo{D Pl, {A Pl, {C Ol, {D Po {A} Po{C} Po{E P, {B} P, {C} P2 {B
PGA
TOP VIEW

u~uwuwwwwwwwuwwwwwwww

P2{A}
PI {E}
PI {D}
PI {C}
PI {B}
PI {A}
Po {E}
Po{D}
Po{C}
Po{B}
Po {A}
Ol, {E}
all {D}
all {C}
all {B}
all {A}
Olo{E}
OLo{D}
Olo{C}
Olo {B}
Olo{A}

7473727' 70696867666564636261 605958 5756 55 54
75
53
76
52
77
51
78
50
79
49
80
48
81
47
82
46
83
45
84
44
:::J 1
43
J84-1
:I 2
42
:I 3
41
:14
40
:15
39
:16
38
:1 7
37
:1 8
36
:I 9
35
:I 10
34
33
:I 11
121314 151617 18192021 2223242526272829303132
nnnnnnnnnnnnnnnnnnnnn

P4 {E}
P5 {A}

L
I:
I:
I:
I:
I:
I:

I:
I:
I:
I:

P5~B~
P
5 C
P5{D}
P5{E}
P6{A}
P6~B}
P6 C}
P6 {D}
P6{E}
PdA}
Pd B}
P 7{C}
P 7{D}
P 7{E}
VAA
AGND
VAA
AGND
VREF

PlCC
TOP VIEW

5.15

2

MILITARYANDCOMMERCIAL TEMPERATURE RANGES

1DT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™

GENERAL INFORMATION:

ADDRESS REGISTER
DATA

The IDT75C458 triple 8-bit PaietteDAC is a highly integrated
building block which interfaces a relatively low bandwidth frame
buffer memory to an analog RS-343A, high bandwidth output. To
decrease the frame buffer memory requirements, the IDT75C458
has a color lookup table (dual-port RAM) included on-chip.The basic functional blocks are the microprocessor bus interface, the
frame buffer memory interface and multiplexer, a dual-port RAM
with one RM port and one high-speed R/O port and three 8-bit
video speed DACs.

X

$OO-$FF
$00
$01
$02
$03
$04
$05
:05
$07

MICROPROCESSOR BUS INTERFACE
The IDT75C458 supports a standard microprocessor bus interface, allowing the MPU direct access to the internal control registers and color/overlay palettes. The dual-port color palette RAM
and overlay registers allow color updating without contention with
the display refresh process.
The bus interface consists of eight bidirectional data pins,
Do - 07, ~th two control input~CO and C1, a read/write direction
input, R/ W, and a clock input, CE . All data and control information
are latched on the falling edge of CE, as shown in Figure 3. All accesses to the chip are controlled by the data in the address register
combined with the control inputs CO, C1 and R/ Vi, depicted in the
Truth Table (Table 1).
An access to a control register requires writing a 4 through 7 into
the address register (CO = C1 = 0) and then writing or reading data
to the selected register (CO = 0, C1 = 1). When accessing the control registers, the address register is not changed, facilitating readmodify-write operations. If an invalid address is loaded into the address register, data written is ignored or invalid data is read out.
It is also possible to access the color palette information. The
palette is organized as 256 addresses with 8 bits of red, blue and
green information. Additionally, there are four extra addresses assigned to overlay information, yielding a total memory size of
260 x 24.
Access to the palette entries is, again, through the address register. The desired palette address is loaded into the address register, CO and C1 are modified to point to the color palette or overlay
and the information is read or written. In this case, however, an internal counter is used to access the red, green or blue color information. The first color palette or overlay access reads or writes red.
The next access is for green, while the third access is for blue. After
the third access, the address register is incremented, allowing the
reading or writing of the red information of the next palette address.
When writing, red and green information is temporarily stored in
registers and, during the blue cycle, all 24 bits are written.
The internal counter is reset by an access to the address or any
of the control registers. After setting the address register, it is possible to read or write the entire palette without accessing the address
register again. Some care is needed; only continuous reads or
writes are allowed and it is not possible to switch between the color
palette and overlay.
The color palette RAM and overlay registers are dual-ported
which allows simultaneous access from the MPU port (Do - D7 )
and the pixel port (Po - P7 {A-E}). If the pixel port is reading the
same palette entry as the MPU is writing, it is possible that the DAC
output may be invalid. I! is recommended that the palette and overlay entries be updated during the blanking time.

C1

CO

0
0
1
1
1
1
1
1

0

1

1

1

1
1
1
1
0
0
0
0

ACCESS
Address Register
Color Palette
Overlay Color 0
Overlay Color 1
Overlay Color 2
Overlay Color 3
Read Mask Register
Blink Mask Register
Command Regislt::r
Test Register

NOTE:
Control input CO = 1 enables the internal counter which accesses the red,
green and blue colors individually and increments the address counter after the blue access. CO = 0 disables auto-increment of the address register
allowing read-modify-write operations.
Table 1. Truth Table for MPU Operations

FRAME BUFFER INTERFACE
The frame buffer interface consists of five 8-bit input ports which
correspond to five consecutive pixels. In addition, there are two extra bits per port which may be used for overlay information. To reduce the bandwidth requirements for the pixel data, the
IDT75C458 latches 4 or 5 pixels (the multiplex factor is programmable to...!or 5 by bit 7 of the command register) on each rising
edge of LD. The color and overlay information is internally multiplexed at the pixel clock frequency, ClK, and sequentially output.
This arrangement allows pixel data to be transferred at a rate 4 or 5
times slower than the pixel clock. Typically, lD is the pixel clock
divided by 4 or 5 and is used to clock data out of the frame buffer
memory.
As shown in Figure 2, sync, blank, color and overlay information
are latched on the riSing edge of lD. Upt040 bits of colorinformation are input through Po - P7 {A-E} and up to 10 bits of overlay information are input throu~ - all {A-E}. Both sync and blank
have separate inputs, SYNC and BLANK, respectively. The
IDT75C458 outputs color information on each clock cycle. Four or
five pixels are output sequentially, beginning with the {A} information, then the {B} information, until the cycle is completed with the
{D} or {E} information. In this configuration, sync and blank times
are limited to multiples of four or five clock cycles.
The multiplexing factor, 4:1 or 5:1, is programmable from the
~ommand register, bit 7. In the 4:1 mode, the {E} color and overlay
Inputs are not used and the lD clock should be CLOCK divided by
4. The {E} color and overlay inputs must be connected to a valid
logic level.
The overlay inputs (aLa - all) have the same timing as the pixel
inputs (Po - P7 ). I! is possible to use additional bit planes or external
logic to control the overlay selection for cursor generation.

INTERNAL MULTIPLEXING
LD is typically ClK divided by four or five and it latches color
and overlay information on every riSing edge, independent of ClK.
A digital Pll allows lD to be phase inde~ndent of ClK. The only
restriction is that only one riSing edge of LD is allowed to occur per
four (4:1 multiplexing) or five (5:1 multiplexing) ClK cycles.

5.15

3

IDT75C458 CMOS TRIPLE 8-BIT PAlETTEDAC ™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Color Palette

VIdeo Generation, DACs

On the rising edge of each ClK cycle, eight bits of color information (Po - P7 ) and two bits of overlay information (Olo - Oll ) for
each pixel are processed by the read mask, blink mask and command registers. This information provides the address to the dualport color palette RAM. Note that Po is the lSB when addressing
the color palette RAM. The value stored at a selected address determines the displayed color. In this way, 8 bits of information can
select from a palette of over 16 million with 256 simultaneous displayed colors (plus 3 overlay colors). Through the use of the control register, individual bit planes may be enabled or disabled for
display and/or blinked at one of four blink rates and duty cycles.
The blink timing is based on vertical retrace intervals which are
defined by at least 256 lD cycles since the last falling edge of
BLANK. The color changes during this normally blanked time.
The processed pixel data is then used to select which color palette entry or overlay register is used to provide color information.
Table 2 illustrates the truth table used for color selection.

On every ClK cycle, the selected 24 bits of color information
(8 bits each of red, green and blue) from the Color Palette RAM are
presented to the three 8-bit D/A converters. The IDT75C458 uses a
5 x 3 segmented approach where the five MSBs of the input data
are decoded into a parallel "Thermometer" code which produces
thirty two "course" output levels. The remaining three lSBs of input
data drive three binary weighted current switches with a total contribution of one-thirty second of full scale. The MSB and lSB currents are summed at the output to produce 256 levels.
The SYNC and BLANK inputs are pipelined to maintained synchronization with the pixel data. Both inputs drive appropriately
weighted, current switches which are summed at the output of the
DACs to produce the specific output levels required by RS-343, as
shown in Figure 3. Note that the sync information is only available
at the lOG (green) output and that the input data to the DAC sums
with the sync current. Table 3 details the output levels associated
with SYNC, BLANK and data.

Monitor Interface
CRS

Oll

Olo

P7 - Po

1
1

0
0

0
0

$00
$01

The analog outputs of the IDT75C458 are high-impedance current sources which are capable of directly driving a doubly terminated 750 coaxial cable to standard video levels. A typical output
circuit is shown in Figure 4.

PALETTE ENTRY
Color palette entry $00
Color palette entry $01

Description
1
0
x
x
x

0
0
0
1
1

0
0
1
0
1

$FF
$xx
$xx
$xx
$xx

Color palette entry $FF
Overlay color 0
Overlay color 1
Overlay color 2
Overlay color 3

S

WHITE
DATA
DATA & SYNC
BLACK
BLACK & SYNC
BLANK
SYNC

NOTE:
CR6 is bit 6 of the Command Register.

1
1
0
1
0
1
0

B

DAe
data

100 (rnA)

lOR. lOB
(rnA)

1
1
1
1
1
0
0

$FF
data
data
$0
$0
X
X

26.67
data + 9.05
data + 1.44
9.05
1.44
7.62
0

19.05
data + 1.44
data + 1.44
1.44
1.44
0
0

II

NOTE:
Typical values with full scale lOG =26.67mA. RSET = 5230.
VREF = 1.235V. S is SY'N'C'. B is m:Af\JR.

Table 2. Palette and Overlay Select

Table 3. Video Output Truth Table

lOR. lOB

lOa

rnA

V

rnA

V

19.05

0.714

26.67

1.000

··

.
.

..

0.054

9.05

0.340

NORMAL HIGH (WHITE)

.

.
1.44
0.00

·

0.000

7.62

0.286

--r----------------92.5 IRE

256 "GRAY LEVELS"

J________ j

NORMAL LOW (BLACK)

7.5 IRE

-1----------40 IRE

0.00

0.000

_1 ____________________
Figure 1. Composite Video Output Waveform

5.15

4

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1DT75C458 CMOS TRIPLE 8.BIT PAlETTEDAC ™

ClK

It

:- OUTPUT DELAY

___X,-_-"X

LJ'----_"X. ._X-JI....-_+_
Figure 2. Pixel Timing

I

\

ts

I
R/W
CO.C1

XXXXXXXXl

I

tH

1
I

...

1+

:x

:y :x

HI-Z TO DATA BUS DRIVEN
CHIP ENABLE TO DATA VALID

V////////////

DATA VALID

""""""""""""
,
I

'\

:xxx XX xxx xxx XXxxx x uxxxxxxxxx xxxxx xxxxx
~

CHIP DISABLE TO HI·Z

'\
/

t:~

ts

IHY HHn XXXXXXXXXXXX XXXXI I XX XX

XXUH XXX XX XX XX XX XXI

-,
Figure 3. Data Bus Timing

COMP

\.....;1.--

+5.0V

IDT75C458
PGND

~--...--~--...--...--...--...----------~---

OV

FSADJ
RSET

lOs

VIDEO OUT

lOG

Figure 4. Typical Application

5.15

5

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC rM

PIN DESCRIPTIONS
DESCRIPTION

PIN NAME
DATA BUS

cr. D7 is the most significant

Do - D7

a-bit, bidirectional data bus. Data is input and output over this bus and the flow is controlled by R/W and
bit.

cr

Chip Enable input. The chip is enabled when this control pin is lOW. During a write cycle (R/W lOW), the data present on Do - D7 is
internally latched on the lOW-to-HIGH transition of this pin.

R/W

Read/Write Control input. The Read/Write input is latched on the HIGH-to-lOW transition of CE and determines the direction of the
bidirectional data bus Do - D .1f R/W is HIGH during the falling edge ofCE, a read cycle occurs. If R/W is lOW during the falling edge of
- D7 are latched on the rising edge of CE.

7
cr, a write cycle occurs and,
additionally, Do
CO,C1

Register Control inputs. CO and C1 determine which register or palette entry is accessed during a read or write cycle. These inputs are
latched on the HIGH-to-lOW transition of

cr.

PIXEL

+ 5V supply. The clock frequency is

ClK. CD<

Pixel Clock inpu~s. These inputs are differential and may be driven by ECl operating from a
normally the system pixel clock rate.

[0

load Clock input. The load Clock is normallyClKdivided by40r5 (determined by the Control Register, bit7). The pixel data, Po - P 7
{A-E} and Olo - Oll {A-E}, ~ and S NC are internally latched on the lOW-to-HIGH transition of [0.

Po - P7 {A-E}

Pixel Input Data. These inputs provide the address input to the color palette RAM. The data stored at a particular address is the color
output by the DAC. Four or five consecutive pixels, as determined by bit 7 in the Command Register, are internally latched on the lOWto-HIGH transition of
The pixels are output sequentially, first {A} then {B}. After all four or five pixels have been output, the cycle
repeats. Unused inputs must be connected to a valid logic level.

m.

Olo - Oll {A-E}

Pixel Overlay Inputs. The Overlay inputs have the same timing as Po - F) and select between either the color palette or the overlay
palette. When the overlay palette is selected, the pixel information Po - Pr {A-E} is ignored. Bit 6 ofthe command register determines if
Overlay = 0 displays overlay color 0 or the color palette entry. See Table 2 for details.

~

Composite Blank Input. A lOW on this input forces the analog outputs (IDA' lOG' lOB) to the blanking level. The g[ANR input is
internally latched on the lOW-to-HIGH transition of
This input overrides all other pixel information.

SYNC

Composite Sync Input. A lOW on this input subtracts approximately 7mA from the lOG analog output and overrides no other pixel
information. For the correct SYNC level, this input should be lOW only when gu;J;JR is also lOW. The ~ input is internally latched
on the lOW-to-HIGH transition of

m.

m.

ANALOG
AGND

Analog Ground Power Supply, OV.

VAA
VREF

Analog Power Supply, 5V.

FSADJ

Voltage Reference Input, 1.235V. This input supplies a reference voltage for the DAC circuitry. Care must be taken to correctly decouple
this voltage because noise on this pin will couple directly to the DAC outputs.

lOG' lOR' lOB

Full-Scale Adjust Input. The current flowing from this pin to AGND is directly proportional to the full-scale analog output current. Normally, a resistor is connected between this pin and AGND . The voltage on this pin is approximately equal to V REF . The relationship
between the full-scale output current and RSET is:
lOG (mA) = 11.294 x VREF M/RSET (KO)
IDA' lOB (mA) = 8.067 x VREF M/RSET (KO)
Green, Red and Blue DAC current outputs.

COMP

Compensation Input. This pin provides the ability to compensate the internal reference operational amplifier.

5.15

6

II

MILITARYANDCOMMERCIAL TEMPERATURE RANGES

IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™

INTERNAL REGISTERS
Command Register

Read Mask Register

The Command Register is accessed by reading or writing with
the Address Register = $06, CO=Oand C1 = 1 (see Table 1). It provides control over multiplexing and blink rate selection. The Command Register may be read or written at any time. CR7 (Command
Register bit 7) corresponds to 07 (Data Bus bit 7).

The Read Mask Register is accessed by reading or writing with
the Address Register = $04, CO = 0 and C1 = 1 (see Table 1). It internally ANOs the pixel information with a bit from the register before the color palette selection, effectively enabling (HIGH) or disabling (lOW) the entire pixel plane. The Read Mask Register may
be read or written at any time. RMR7 (Read Mask Register bit 7)
corresponds to 07 (Data Bus bit 7).

CRO

Olo display enable. This bit is ANOed internally with
the data from Olo prior to the palette selection. If
CRO is lOW, the internal Olo bits are set lOWallowing only overlay colors 0 and 2 to be selected.

CR1

Ol, display enable. This bit is ANOed internally with
the data from Ol, prior to the palette selection. If
CR1 is lOW, the internal Ol, bits are set lOW allowing only overlay colors 0 and 1 to be selected.

CR2

Olo blink enable. If this bit is set HIGH, the Olo bit is
internally switched between the value input and 0 at
the rate specified by the CR4 and CR5 bits. CRO
must be set HIGH for this function.

CR3

Blink Mask Register
The Blink Mask Register is accessed by reading or writing with
the Address Register = $05, CO = 0 and C1 = 1 (see Table 1). Each
register bit causes the corresponding pixel bit (Po - P7 ) to internally
switch between the input value and 0 at the blink rate specified in
the Command Register. For this function to work, the corresponding enable bit in the Read Mask Register must be set HIGH. The
Blink Mask Register may be read or written at any time. BMR7
(Blink Mask Register bit 7) corresponds to 0 7 (Data Bus bit 7).

Test Register
The Test Register is accessed by reading or writing with the Address Register = $07, CO =0 and C1 = 1 (see Table 1). This register
allows the MPU to read the 24 input bits of the OACs. The register
bits are defined below.

Ol, blink enable. If this bit is set HIGH, the Ol, bit is
internally switched between the value input and 0 at
the rate specified by the CR4 and CR5 bits. CR1
must be set HIGH for this function.

CR4, CR5

Blink Rate Select. These bits select blink rates based
on Vertical Sync cycles, defined as more than 256
LO cycles during BLANK.

CR6

Color Palette RAM enable. This bit specifies whether
to use the Color Palette or the Overlay Palette when
Olo = Ol, = lOW.

CR7

Multiplex Select. This bit selects between 4:1
(CR7 = 0) or 5:1 (CR7 = 1) multiplexing. When using
4:1 multiplexing, the {E} inputs are never used and
must be connected to a valid logic level.

CR7

CR6

CR5

CR4

CR3

TR7-TR4
TR3
TR2
TR1
TRO

Read data (one nibble of red, blue or green)
Upper (lOW) or lower (HIGH) nibble select
Blue enable
Green enable
Red enable

The desired OAC is selected by setting only one color enable bit
(Do - O2 ) HIGH and the upper or lower nibble is selected with 0 3 •
After this write operation, a subsequent read yields the OAC data
on 0 7 - 0 4 and the previously written enable data on Do - 0 3 , For a
correct read, pixel and overlay data must remain constant for the
entire MPU read cycle. When BLANK is asserted, the Test Register
information 0 7 - 0 4 will be forced to zero. TR7 (Test Register bit 7)
corresponds to 0 7 (Data Bus bit 7).

CR2

C~Rl
TY

Od,,.bl.OL,
1 enable Olo
o disable Ol,
1 enable Ol,

L . . . - - - - - - - - - - - I 0 blinking of Olo disabled

1 blinking of Olo enabled

o blinking of Ol, disabled

L . . . - - - - - - - - - - - - - - i 1 blinking of Ol, enabled

00 16 Vsync on /48 Vsync off

L . . . - - - - - - - - - - - - - - - - - - - i 01 16 Vsync on /16 Vsync off
10 32 Vsync on /32 Vsync off
11 64 Vsync on /64 Vsync off

L...------------------------i
L...-_________________________--\

0 Use overlay color 0
1 Use color palette 0
04:1 Multiplex
1 5:1 Multiplex

COMMAND REGISTER DESIGNATIONS

5.15

7

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1DT75C458 CMOS TRIPLE 8.BIT PALETTEDAC TO.

MR7

MR6

RMRS

RMR4

T

RMR2

RMR3

AT"

:01 d;,ilil.
P,
enable Po
o disable P,
1 enable P,

L...._ _ _ _ _ _ _ _~

0 disable P2
1 enable P2

L...._ _ _ _ _ _ _ _ _ _ _ _~

0 disable P3
1 enable P3

L...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _--I

0 disable P.t
1 enable P4

L---------------------l 01 disable
Ps
enable Ps
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

0 disable P
a
1 enable Pa

L---------------------------l 01 enable
disable P7
P
7

READ MASK REGISTER DESIGNATIONS

BMR7

MR6

MRS

BMR4

BMR3

BMR2

BMR1

BMRO

I

I

I

:~=~$~~~~~
o disable P,

blinking
1 enable P, blinking

L...._ _ _ _ _ _ _ _~

0 disable P2 blinking
1 enable P2 blinking

L...._ _ _ _ _ _ _ _ _ _ _ _~

0 disable P3 blinking
1 enable P3 blinking

L...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

0 disable P blinking
4
1 enable P4 blinking

L...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

0 disable Ps blinking
1 enable Ps blinking

L-______________________

~

0 disable P blinking
a
1 enable P6 blinking

L---------------------------l 01 enable
disable P 7 blinking
P blinking
7

BLINK MASK REGISTER DESIGNATIONS

5.15

8

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1DT75C458 CMOS TRIPLE 8.BIT PALETTEDAC ™

ABSOLUTE MAXIMUM RATINGS
SYMBOL

(1)
VALUE

RATING

UNIT

POWER SUPPLIES
Measured to AGND

-0.5 to +7.0

V

Measured to AGND

-0.5V to VAA + 0.5

V

Applied Voltage (2)

Measured to AGND

-0.5V to VAA + 0.5

V

App!!~d Currcnt(2.3.4)

Ext=:-n~!!y

-1.0 to

rnA

VAA
INPUT VOLTAGE
Applied Voltage (2)
OUTPUT

Short
Circuit Duration

forced

Single output
High to AGND

of

6.0

Indefinite

-

TEMPERATURE
Operating.
Ambient
Storage

Military

-55 to +125

Commercial

o to

Military

-65 to + 150

Commercial

-55 to + 125

+70

°c
°c
°c
°c

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress ratIng only and functional operation of the device at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect reliability. Absolute Maximum Ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current when flowing into the device.

5.15

9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™

DC ELECTRICAL CHARACTERISTICS
SYMBOL
VAA

TEST CONDITIONS

PARAMETER
Power Supply

Measured to AGND

Power Supply Current

VAA = Typ .. Static

TYP.

MAX.

4.75

5.0

5.25

V

-

200

-

mA

-

VAA +0.5

V

IAA
. '-"H(1)

Input Voltage HIGH

2.0

'-"L(1)

Input Voltage lOW

AGND -0.5

VCIH

Clock Input Voltage HIGH

VAA -1.0

VCIL

Clock Input Voltage lOW

AGND -0.5

Input Current lOW

VIN = O.4V

-

VOH

Output Voltage HIGH

VAA = Min .• 10H = -800jJA

2.4

VOL

Output Voltage lOW

VAA = Min., 10L = 6.4mA

-

10l

Output 3-State Current

IIH
IlL

Input Current HIGH

VIN = 2.4V

NOTE:
1. All digital inputs except ClK and

UNIT

MIN.

-

0.8

V

VAA +0.5

V

-

VAA -1.6
1

jJA

-1

jJA

-

V

-

0.4

V

10

jJA

V

CIT.

AC ELECTRICAL CHARACTERISTICS
. Following conditions apply unless otherwise specified:
TA = O°C to + 70°C (Commercial Temperature Range)
TA = -SSoC to + 12SoC (Military Temperature Range)
VAA = S.OV ±S%
TTL Inputs, VIL =OV, VIH =3.0V, rise/fall time :;;:

-

ns

ns

2

-

2

-

2

-

2

-

-

425

-

400

-

380

-

360

mA

-

-

-

450

-

430

-

410

mA

13
13

ns
ns ,
ns
ns
ns

NOTE:
1. 165 and 135 MHz specified over commercial temperature only.

5.15

10

I

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™

ANALOG OUTPUT DC ELECTRICAL CHARACTERISTICS
SYMBOL

TEST CONDITIONS

PARAMETER

Res

Resolution

I LSB

LSB Current Size
1 LSB VERSION

LI

1/2 LSB VERSION
Lo

1 LSB VERSION
1/2 LSB VERSION

MIN.

TYP.

MAX.

UNIT

-

S

bits

69.1

-

-

1/2

±1

LSB

1/4

±1/2

LSB

1/2

±1

LSB

1/4

±1/2

LSB

-1.0

-

1.2

pA

Voc

Output Compliance Voltage

RAOUT (2)
CAOUT (2)

Output Impedance

IREF
EM

VREF Input Current
Matching Error (DAC to DAC)

-

2

S

%

PSRR

Power Supply Rejection Ratio

-

SO

-

dB

IW(I)

White Current

Measured to Blank

17.69

19.0S

20.40

mA

IW(I)

White Current

Measured to Black

16.74

17.62

1S.S0

mA

I B(1)

Black Current

Measured to Blank

0.95

1.44

1.90

mA

I BLANK
I SLANK (1)

Blank Current lOR. lOB

0

S

SO

pA

6.29

7.62

S.96

mA

0

5

50

pA

V

SO

Output Capacitance

kO

S

f = 1MHz. lOUT = OmA

12

pF

10

Blank Current lOa

I SYNC
Sync Current lOa
NOTE:
1. RSET =S230, VREF =1.235V
2. This parameter is guaranteed but not tested in production.

pA

ANALOG OUTPUT AC ELECTRICAL CHARACTERISTICS
Following conditions apply unless otherwise specified:
TA = aoc to + 70°C (Commercial Temperature Range)
TA = -55°C to + 125°C (Military Temperature Range)
VAA = 5.0V ±5%

TTL Inputs, V1L = O.BV, V1H = 2.aV, rise/fall time < 5ns
ClK Inputs, V1H = VAA -1.0V, ~L =VAA -1.6V, rise/fall time <2ns
Timing reference points at 50% of signal swing
I DT75C458-165 (3) I DT75C458-135 (3) 1DT75C45S-125
SYMBOL

PARAMETER

FCLK

Clock Frequency

-

-

165

-

-

.1.~5

-

125

tvo

Video Output Delay Time

-

-

15

-

1§

..~~:.

tVT

Video Output Transition Time

-

1.S

-

1]

-

-

15

-

-

1.8

-

ts

Video Output Skew(l)

-

0

<2

t SI (2)

Video Output Settling Time

6

f;8,} 1\2

FT(2)

Clock and Data Feedthrough

GE(2)
CT(2)

-

Crosstalk. DAC to DAC

tvp

Pipeline Delay

Glitch Energy

I DT75C4SS-11 0

MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP.

.nt to MIL-STD-883, CI(l.sS B
Pin Grid Array
PLCC

~~L}
110

Speed in Megahertz

125

135
165

~------------------------------~I S

L - - - - - - - - - - - - - - - - - - - - l 75C458

5.15

Standard Power
Triple 8-bit PaietteDAC ™

13

G

IDT75C48

CMOS FLASH
AID CONVERTER

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

The IDT75C48 is a 30 MegaSample per Second (MSPS),
fully parallel, 8-bit Flash Analog to Digital Converter. The wide
input analog bandwidth of 1OMHz permits the conversion of
analog input signals with full-power frequency components up
to this limit with no input sample and hold. Low power
consumption due to CEMOSTM processing, virtually eliminates
thermal considerations. The IDT75C48 is available in 28-pin
plastic and hermetic DIPs and a 28-pin LCC.
The IDT75C48 consists of a reference voltage generator,
255 comparators, encoding and EDC (Error Detection and
Correction) logic and an output data register. A single clock
starts the conversion process and controls all internal
operations. Two control inputs allow the output coding format
to be programmed for straight binary or offset two's
complement in either the true or inverted form.
The IDT75C48 military Flash AID Converters are
manufactured in compliance with the latest revision of
MIL-STD-883, Class 8, making them ideally suited to military
temperature applications demanding the highest level of
performance and reliability.

8-bit resolution
30 MSPS conversion rate
Guaranteed no missing codes
Pin- and function-compatible with TRW 1048
Low power consumption: 500mW
Extended analog input range
On-chip EDC (Error Detection and Correction)
Improved output logic HIGH drive, no pull-up needed
No sample and hold required
Differential Phase < 1 Degree
Differential Gain < 2%
Selectable output formats
TIL-compatible
Available in 28-pin CERDIP and LCC
Military product compliant to MIL-STD-883, Class 8
Standard Military Drawing #5962-88743 is listed for this
function

II

FUNCTIONAL BLOCK DIAGRAM
NMINV
NLiNV
VIN

CONV
Rr

R1 ~

/"

'--

~

~t>- r----.
•

··

I
I
I

R ~

..-

~27

R/2 ~

RM
R/2

Ir-R
I

.

:

R
R ~

--...
~
v'"

-

255 TO 8
ENCODE
+EDC

~

LATCH

~ Dl- D8

··•

254

~
v

R2:

As

I

-V;

R >
R

I

..- ~N

-

256 DIFFERENTIAL
COMPARATORS

2579 drw 01

CEMOS is a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
"'1990 Integrated Device Technology. Inc.

5.16

JUNE 1990
DSC·5003/2

1

1DT75C48
CMOS FLASH AJD CONVERTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

en

en>
INOEX

NMINV

01 (MSS)

v ~ N
C:H::lO

RM

02
03

Rs

04

AGND
VIN
VIN
VIN

OGND
VCC
VEE
VEE
VEE
VCC
OGND
NLiNV

OGND
VCC
VEE
VEE
VEE
VCC
OGND

YiN

VIN
AGND

RT

:]5
:]6

08 (LSB)

06

07
DIP
TOP VIEW

::-~:::

CD

~1i~U~~~ ~

25 [:
24[:
:]7
23[:
:]8
L28-1
22 [:
:J9
21
:]10
20[:
:]11
19[:
12131415161718

1

c:

AGND
VIN
VIN
VIN
VIN
VIN
AGND

nnnnnnn

CONY

05

~~

OZa:a:

~ 80 oen~CI:
:J
~o

2579 drw 03

~()

Z
2579 drw 02

LCC
TOP VIEW

GENERAL INFORMATION
The I DT75C48 has four functional sections: a comparator
array, a reference voltage generator, encoding logic with EDC
and output logic. The comparator array compares the input
signal with 255 reference voltages to produce an N - of - 255
code. This is sometimes called a ''Thermometer'' code because
all of the comparators with their reference voltage less than
the input signal will be "on" while those with their reference
above the input will be "off".
The reference voltage generator consists of a string of
precisely matched resistors which generate the 255 voltages
needed by the comparators. The voltages at the ends of the
resistor string set the maximum and minimum conversion
range and are typically OV and -2V, respectively.
The encoding logic converts the "Thermometer" code into
binary or offset two's complement numbers and can invert
either code. Included in the encoding function is Error Detection
and Correction logic which ensures that a corrupted
Thermometer code is correctly encoded.
The output logic latches and holds the data constant
between samples. The output timing is designed for an easy
interface to external latches or memories using the same
clock as the ADC.

POWER
The IDT75C48 requires two power supply voltages, Vee
and VEE. Typically, VEE = -5.2V and Vee = +5.0V. Two
separate grounds are provided, AGND and DGND, the analog
and digital grounds. The difference between AGND and DGND
mllet
nnt t:>y,.t:>t:>ri
+n
~II
n"\A'O~
-:>nri
n~""nri ,..,"1\.1
nine II._V"
m"et
••
,_"'. I'"".
........ _ _
...... 1I \I
.. _~nri
•• _ _
'I ,..,_
•• __ ........
_ ::;1'--"be connected.
_,~...,

REFERENCE
The I DT75C48 converts analog input signals that are within
the range of the reference (VAS ~ VIN ~ VAT) into digital form.
VAS (Reference Bottom) and VAT (Reference Top) are applied
across the reference resistor chain and both must be within

the range of +2.1 V to -2.1 V. In addition, the voltage applied
across the reference resistorchain (VAT-VAS) must be between
1.8V and 2.2V, with VAT more positive than VAS. Nominally,
VAT = O.OV and VAS = -2.0V.
The IDT75C48 provides a midpoint tap, RM, which allows
the converter to be adjusted for optimum linearity or a nonlinear transfer function. Adjustment of RM is not necessary to
meet the linearity specification. Figure 5 shows a circuit which
will provide approximate Iy 112 LSB adjustment of the midpoint.
The characteristic impedance of RM is about 170Q and this
node should be driven from a low impedance source. Any
noise introduced at this point will couple directly into the
resistor chain, seriously affecting performance.
Due to the unavoidable coupling with the clock and the
input signal, RT and Rs should provide low AC impedance to
ground. For applications with a fixed reference, a bypass
capacitor is recommend.

CONTROL
The IDT75C48 provides two function control pins, NMINV
and NLINV. These controls are for steady state use and are
usually tied to the appropriate voltages. They control the
output coding format in either straight binary or offset two's
complement. In addition, both formats may be either true or
inverted. These pins are active low and perform the functions
shown in Figure 1.

CONVERT
The IDT75C48 begins a conversion with every riSing edge
"f
tho ""n\lart "inn",1
_. ",. _ _ V".V'"

V'~''',A',

('("\,\1\1
Tho ",n",lnn inn"t
"inn",1 ......
i"
"' ............ " "... 1Io.A" .....
11.1'-''"'"''
''''~

VI~'I\.AI

sampled on the riSing edge of CONY, while the outputs of the
comparators are encoded on the falling edge. The next rising
edge latches the encoder output which is presented on the
output pins.
The input sample is taken within 15ns of the rising edge of
CONY. This is called tSTO or the Sampling Time Offset. This
delay varies by a few nanoseconds from part to part and as a

5.16

2

IDT75C48
CMOS FLASH AID CONVERTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

function of temperature, but the short term uncertainty or jitter
is less than 60ps.
If the maximum CONV pulse width HIGH time (tPWH) is
exceeded, the accuracy of the input sample may be impaired.
The maximum CONV pulse width LOW time (tPWL) may be
exceeded, but the digital output data for the sample taken by
the previous rising edge of CONV will be meaningless. It is
recommended that CONV be held LOW during longer periods
of inactivity.
The digital output data is presented at to, the Digital Output
Delay Time, after the next rising edge of CONV. Previous
output data is held for the tHO (Output Hold Time) after the
rising edge of CONV to allow for non-critical timing in the
Step

external circuitry. This means that the data for samples N is
acquired while the converter is taking sample N + 2.

ANALOG INPUT
The IDT75C48 uses strobed, auto-zeroing, latching
comparators. All five analog input pins must be connected
together as close to the package as possible.
If the analog input signal is within the reference voltage
range, the output will be a binary number between a and 255.
An input signal above VRTWill yield a full-scale positive output
while an input below VRS will cause a full-scale negative
output.
Offset Two's

Binary

Range
-2.0000V FS
7.8431mV/Step

-2.0480V FS
8.000mV/Step

*NMINV=1
NLlNV=1

NMINV=O
NLlNV=O

NMINV=O
NLlNV=1

NMINV=1
NLlNV=O

000
001

O.OOOOV
-a.0078V

O.OOOOV
-a.0080V

00000000
00000001

11111111
11111110

10000000
10000001

01111111
01111110

127
128
129

-a.9961V
-1.0039V
-1.0118V

-a.0160V
-1.0240V
-1.0320V

01111111
10000000
10000001

10000000
01111111
01111110

11111111
00000000
00000001

00000000
11111111
11111110

254
255

-1.9921V
-2.0000V

-2.0320V
-2.0400V

1111-1110
11111111

00000001
00000000

01111110
01111111

10000001
10000000

··
··

··

··

·

-

·

-

.-

.-

··

·-

·

·

·When NMINV and NLiNV are both high a 1Kn series resistor must be inserted between NMINV and Vee.

'''Od~''

CONV

ANALOG INPUT

~~DtSTO

~~

Vee

.1

Figure 2. Timing Diagram

2579 drw 05

810n

TO
OUTPUTo-____~--~--~
PIN

1N3062

2579 drw 06

Figure 3. Output Load 1

5.16

3

II

1DT75C48
CMOS FLASH AlD CONVERTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

Commercial

Unit

Power Supply
Vee

Measured to DGND

-0.5 to +7.0

V

VEE

Measured to AGND

+0.5 to -7.0

V

AGND

Measured to DGND

-0.5 to +0.5

V

-0.5 to Vee +0.5

V

Input Voltage
CONV.
Measured to DGND
NMINV, NUN\i
VIN, VRT, VRS

Measured to AGND

VRT

Measured to VRS

Veeto VEE

V

-4.0 to +4.0

V

-0.5 to Vee +0.5

V

-20.0 to +20.0

rnA

1.0

S

-55 to +125

°C

o to +70

°C

Output
Applied
Voltaqe (2)

Measured to DGND

Applied
Current (2.3,4)

Externally forced

Short Circuit
Duration

Single output High to
DGND

Temperature
Operating

Military

Ambient

Commercial

Storage

Military

-65 to +150

°C

Commercial

-55 to +125

°C

NOTES:
257911>101
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. Absolute Maximum
Ratings are limiting values applied individually while all other parameters
are within specified operating conditions. Functional operation under any
of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current when flowing into the device.

5.16

4

IDT75C48
CMOS FLASH AID CONVERTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS
Temperature Range
Commercial
Symbol

Parameter

Test Condltlons(l)

Min.

Nom.

Military

Max.

Min.

Nom.

Max.

Unit

V

Power Supply
Vee

Positive Power Supply

4.75

5.0

5.25

4.5

5.0

5.5

VEE

Negative Power Supply

-4.9

-5.2

-5.5

-4.9

-5.2

-5.5

V

VAGND

Analog Ground Voltage (ref DGND)

-0.1

0

+0.1

-0.1

0

+0.1

V

lee

Positive Supply Current

Vee = Max.,. Statict 1)

-

50

70

-

60

SO

mA

lEE

Negative Supply Current

VEE = Max., Static(1)

-

-25

-35

-

-25

-35

mA

Digital Inputs (CONV, NMINV, NLlNV)
VIL

Input Voltage, Logic LOW(4)

-0.5

-

O.S

-0.5

-

O.S

V

VIH

Input Voltage, Logic HIGH(4)

2.0

Vee +.1

2.0

-

Vee +.1

V

IlL

Input Current, Logic LOW

Vee = Max., VIL = 0.5V

-

±10

Vee = Max., VIH = 2.4V

-

±10

±10

JlA

II

Input Current, Max. Input Voltage

Vee = Max., VI = Vee

-

50

-

CI

Digital Input Capacitance(4)

TA;= +25°C, F = 1MHz

-

15

-

-

JlA

Input Current, Logic HIGH

-

±10

IIH

-

50

JlA

15

pF

Dig Ital Outputs
VOL

Output Voltage, Logic LOW

Vee = Min., 10L = 4.0mA

-

-

V

Vee = Min., 10H = 4.0mA

2.4

-

2.4

-

0.5

Output Voltage, Logic HIGH

-

0.5

VOH

-

V

los

Output Short Circuit Current

Vee = Max.t 2)

-

-

-50

-

-

-50

mA

Reference
VRT

Most Positive Reference Voltage(3)

-0.1

0

+0.1

-0.1

0

+0.1

V

VRS

Most Negative Reference Voltage(3)

-1.9

-2.0

-2.1

-1.9

-2.0

-2.1

V

VRTVRS

Reference Voltage Range

1.S

2.0

2.2

1.S

2.0

2.2

V

IREF

Reference Current (AT to Rs)

VRT, VRS = Nom.

-

5

RREF

Reference Current (AT to Rs)

VRT, VRS = Nom.

250

400

9

-

200

6
330

10

mA
Ohm

-

Analog Input

-

VRT

-

-

50

pF

-

-

10

JlA

-

-

-

°C

VIN

Input Voltage Range

VRS

-

RIN

Equiv. Input Resistance(4)

VRT, VRS= Nom., VIN = VRS

100

-

-

100

CIN

Equiv. Input Capacitance(4)

VRT, VRS= Nom., VIN = VRS

-

-

50

les

Input Const. Bias Current

VEE = Max.

-

-

10

TA

Ambient Temperature, Still Air

0

-

70

Te

Case Temperature

-

-

-

VRT

VRS

-55

-

-

V
KOhm

+125

°C

NOTES:
2579tbl02
1. Worst case, all digital inputs and outputs LOW.
2. Output HIGH, one pin to ground. one second duration.
3. VRT must be more positive than VRB and the voltage reference must be within the specified range. Although the device is specified and tested with the
reference equal to OV and -2V, the part will operate with VRT up to +2.1V. Likewise, the reference range may vary from 1.2V to 2.6V.
4. This parameter is guaranteed but not tested in production.

5.16

5

II

IDT75C48
CMOS FLASH AID CONVERTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS FOR ID175C48SX20 (20MHz Version)
Specifications over the DC Electrical range unless otherwise stated.
Temperature Range
Military

Commercial
Symbol

Parameter

Test Conditions
Vee = Min., VEE

= Min.

Fs

Conversion Rate

tPWl

CONY, Pulse Width LOW(3)

tPWH

CONY, Pulse Width HIGH(3)

tSTO

Sampling Time Offset

EAP

Aperture Error(4)

to

Digital Output Delay

Vee = Min., VEE
Load 1

= Min.,

tHO

Digital Output Hold Time

Vee = Min., VEE
Load 1

= Min.,

Ell

Linearity Error, Integral

VRT,

Vee = Min., VEE

= Min.

11/2 LSB(2)

= Nom. 13/4 LSB(2)
VRT, VRB = Nom.
VRB

ElD

Linearity Error, Differential

CS

Code Size(1)

EOT

Offset Error, Top

VIN

EOB

Offset Error, Bottom

VIN

Teo

Offset Error,
Temperature Coefficient(4)

= midpoint code 0
= midpoint code 255
VIN = VRB

Min.

Typ.

20

30

18
22
0
-

-

Max.

100,000

Min.

Typ.

20

30

18
22
0

-

-

-

-

Max.

-

Unit
MSPS

100,000

ns
ns

-

20,000
15
60
35

-

-

20,000
10
60
30

5

-

-

5

-

-

ns

-

-

0.2
0.3
0.2

-

-

0.2
0.3
0.2

%FS

100
10

175
45

100
10

175
45

%Nom

-10
-

-30
±20

25
-

-10

-

-

-30
±20

25
-

-

-

-

-

ns
ps
ns

%FS
%FS

mV
mV
f!V/oC

BW

Bandwidth, Full Power Input

7

12

-

5

10

-

TTR

Transient Response, Full Scale(5)

-

-

20

-

-

20

nS

SNR

Signal to Noise Ratio

55
55
46
46
39

-

-

dB
dB

.5
1

1
2

Peak SignallRMS Noise
RMS SignallRMS Noise
NPR

Noise Power Ratio

DP

Differential Phase Error

DG

Differential Gain Error

20 MSPS Conversion Rate,
10 MHz Bandwidth
54
1.248 MHz Input
2.438 MHz Input
53
45
1.248 MHz Input
2.438 MHz Input
44
36.5
DC to 8 MHz White Noise
Bandwidth 4 Sigma Loading
1.248 MHz Slot
20 MSPS Conversion Rate
Fs = 4 x NTSC
Fs = 4 x NTSC
-

56
56
47
47
39

.5
1

-

-

1
2

53
52
44
43
36.5

-

MHz

dB
dB
dB

Degree
%

NOTES:
2579tbl03
1. Guarantees no missing codes.
2. See the ordering information section regarding the part number designation.
3. No damage to the part will occur if the Max. times are exceeded. See the Convert section for more information about the Conv Max. time limitations.
4. This parameter is guaranteed but not tested in production.

5.16

6

IDT75C48
CMOS FLASH AID CONVERTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS FOR IDT75C48SX30 (30MHz Version)
Specifications over the DC Electrical range unless otherwise stated.
Temperature Range
Commercial
Symbol

Parameter

Fs

Conversion Rate

tPWL

CONV, Pulse Width LOW

tPWH

CONV, Pulse Width HIGH

Test Conditions
Vee = Min., VEE .. Min.

tSTO

Sampling Time Offset

EAP

Aperture Erro,-(4)

to

Digital Output Delay

Vee = Min., VEE = Min.,
Load 1

tHO

Digital Output Hold Time

ELI

Linearity Error, Integral

Vee = Min., VEE = Min.,
Load 1
l3/4 LSB(2)
VRT,

Vee = Min., VEE = Min.

VRB = Nom.
ELD

Linearity Error, Differential

CS

Code Size(l)

11 LSB(2)

VRT, VRB = Nom.

EOT

Offset Error, Top

VIN = midpoint code

EOB

Offset Error, Bottom

VIN = midpoint code

Teo

Offset Error,
Temperature Coefficient(4)

VIN = VRB

0
255

Min.

Typ.

30
14
14
0

40

-

-

-

5

-

-

-

25

100
10
-10

-

-

Military

Max.

100,000

20,000
10
60
25

Min.

Typ.

30
14
14
0

40

-

Max.

-

Unit
MSPS

-

100,000

ns

-

20,000
15
60
28

ns

-

ns

-

-

-

5

-

-

0.3
0.4
0.2
175
45
-30
±20

-

-

%Nom

MHz

-

100
10
-10

-

-

0.3
0.4
0.2
175
45
-30
±20

25

-

ps
ns
ns
%FS
%FS
%FS

mV
mV

't!V/oC

BW

Bandwidth, Full Power Input

10

13

-

8

10

-

TTR

Transient Response, Full Scale(4)

-

-

20

-

-

20

nS

SNR

Signal to Noise Ratio

44
44
35
35

48
48
39
39

-

48
48
39
39

-

-

dB
dB

-

dB
dB

-

-

-

44
44
35
35

-

-

-

dB

-

.5
1

1
2

-

.5
1

1
2

Peak SignallRMS Noise
RMS SignallRMS Noise
NPR

Noise Power Ratio

DP

Differential Phase Error

DG

Differential Gain Error

30 MSPS Conversion Rate,
15 MHz Bandwidth
5 MHz Input
10 MHz Input
5 MHz Input
10 MHz Input
DC to 15 MHz White Noise
Bandwidth 4 Sigma Loading
5 MHz Slot
30 MSPS Conversion Rate
Fs = 4x NTSC
Fs = 4x NTSC

-

-

Degree
%

NOTES:
25791b104
1. Guarantees no missing codes.
2. See the ordering information section regarding the part number designation.
4. No damage to the part will occur if the Max. times are exceeded. See the Convert section for more information about the Con v Max. time limitations.
5. This parameter is guaranteed but not tested in production.

5.16

7

II

IDT75C48
CMOS FLASH AJD CONVERTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CALIBRATION

TYPICAL INTERFACE

The calibration of the IDT75C58 involves the setting of the
1st and 255th comparator thresholds to the desired voltages.
This is done be varying the top and bottom voltages on the
reference resistor chain, VRT and VRS, to compensate for any
internal offsets. Assuming a nominal OV to -2V reference
range, apply -O.0039V (1/2 LSB from OV) to the analog input,
continuously strobe the device and adjust VRT until the OVFL
outputtoggles between 0 and 1. To adjustthe first comparator,
apply -1.996V (1/2 LSB from -2V) to the analog input and
adjust VRB until the converter output toggles between the
codes 0 and 1.
The offset errors are caused by the parasitic resistance
between the package pins and the actual resistor chain onchip and are shown as R1 and R2 in the Functional Block
Diagram. The offset errors, EaT and Eas, are specified in the
AC Electrical Characteristics and indicate· the degree of
adjustment needed.
The previously described calibration scheme requires that
both ends of the reference resistor chain be adjustable, i.e. be
driven by operational amplifiers. A simpler method is to
connect the top of the resistor chain, RT, to analog ground or
OV and to adjust this end of the range with the input buffer
offset control. The offset error at the bottom of the resistor
chain results in a slight gain error which can be 'compensated
for by varying the voltage applied to Rs. This is a preferred
method for gain adjustment since it is not the input signal path.
See Figure 5 for a detailed circuit diagram of this method.

Figure 5 shows a typical application example for the
IDT75C58. The analog input amplifier is a bipolar wideband
operational amplifier whose low impedance output directly
drives the AID Converter. The input buffer amplifier is configured
with a gain of minus two which will convert a standard video
input signal (1 V p-p) to the recommended 2V converter input
range. Both VIN pins are connected together as close to the
package as possible and the input buffer feedback loop is
closed at this point. Bipolar inputs, as well as the calibration of
the reference top, are accomplished using the offset control.
A band-gap reference is used to provide a stable voltage for
both the offset and gain control. A variable capacitor in the
input buffer feedback loop allows optimization of either the
step or the frequency response and may be replaced by a
fixed value in the final version of the printed circuit board.
To ensure operation to the rated specifications, proper
decoupling is needed. The bypass capacitors should be
located close to the chip with the shortest lead lengths
possible. Massive ground planes are recommended. If separate
digital and ground planes are used, they should be connected
together at one point close to the IDT75C58.
The bottom reference voltage, VRS, is supplied by an
inverting amplifier buffered by a PNP transistor. The transistor
provides a low impedance source and is necessary to provide
the current flowing through, the resistor chain. The bottom
reference voltage may be adjusted to cancel the gain error
introduced by the offset voltage, Eas, as discussed in the
calibration section.

5.16

8

IDT75C48
CMOS FLASH AID CONVERTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PARTS
+SV----------~------------------_4------------~~----~--~

R1 LIST o.on
80.7n
R2
R3
1Kn
R4
2Kn
RS
220n
2Kn
R6
1Kn
R7
2Kn
R8
R9
2Kn
R10
10Kn
20Kn
R11
R12
27n

L1

~
V

R1

R3

R5

ANALOG
INPUT

6
R7

20

R6
R12

VIN
VIN
VIN
VIN
VIN

10

Vee Vee

U1
10T7SC48

26

01 (MSB)
02
AGND
03
Rr
04
05
RM
06
CONY

L2
01
C12

V

RB

5,11

DGND

1
2
3
4
13
14
15
16

CLOCK----------~--~----_r------_+--------~

-S.2V

10~F

C1-C4
CS-C14
C1S

O.1~F

U1
U2
U3
U4

10T7SC48
HA-2539·S
uA741C
LM313

01

2N2907

L1, L2

Ferrite Bead

1-6pF Variable

-------------------------------------------------C-7~-:-·~-+---fcfv

I

2579 drw 07

Figure 4. Application Example

RT

(1)

IOT7SC48

2579 drwoa

Figure 5. Mid-Point Adjust

NOTE:

1. When NMINV and NLiNV are both HIGH a 1Kn series register must be inserted between NMINV and Vee.

5.16

9

IDT75C48
CMOS FLASH AJD CONVERTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vcc

SWITCH POSITION
0-.7.0V

soon

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2578 tbl 6
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

Z&t

l

PULSE WIDTH

'IoIt...~..M~

~ OV
~~V
-

tsU~'I4--~

TIMING
INPUT _ _ _ _ _ _- '

- 3V
_ 6~V

LOW-HIG~~~~

-

HIGH-LOW-HIGH

ASYNCHRONOUS CONTROL
PRESET - - - -......
CLEAR
ETC. - - - - - '
SYNCHRONOUS CONTROL
CLOCK

--+------

:~~~~~ vvJr
l
~sU
ETC.

t

""'-~~~

3V
l.SV
OV

=t-

~ 15V
I.

--1.SV

PULSE

- 3V
-1.SV
-OV

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

3V
SAME PHASE
INPUT TRANSITION

OUTPUT

OV
3.SV

VOH
-1.SV

VOL

VOL
OUTPUT
NORMALLY
HIGH

OPPOSITE PHASE
INPUT TRANSITION

OV

SWITCH
OPEN

VOH
OV

NOTES
2578 drw 12
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ son; tF ~ 2.Sns;
tR ~ 2.Sns.

5.16

10

IDT75C48
CMOS FLASH AID CONVERTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

X
-Device
-XXX
- Type
-

x
Power

x

x

x

Speed

Package

Processl
Temperature
Range

~~Iank

I - -_ _ _ _ _--I

D
L

Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
CERDIP (600 mil)
Leadless Chip Carrier

20

MHz
MHz

S

Standard Power, 1/2 LSB Integral Linearity·
Standard Power, 3/4 LSB Integral Linearity
Standard Power, 1 LSB Integral Linearity··

~----------~30

~--------------------------,SB

SC
~----------------------------------~75C48

Flash AID Converter

2579 drw09

• 20 MHz Version only
•• 30 MHz Version only

II

5.16

11

G

IDT75C58

CMOS FLASH
AID CONVERTER

Integrated Devfce Technology, Inc.

FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

8-bit resolution
30 MSPS conversion rate
Overflow output
Low power consumption: 500mW
Guaranteed no missing codes .
Power-Down mode
Extended analog input range ':
On-chip EDC (Error Detection and Correction)
Tri-state outputs
Improved output logic HIGH drive, no pull-up needed
No sample and hold required
Differential Phase = 1 Degree
Differential Gain = 2%
TIL-compatible
Available in 28-pin CERDIP or LCC
Military product compliant to MIL-STD-883, Class B

DESCRIPTION:
The IDT75C58 is a 30 MegaSample per Second (MSPS),
fully parallel, 8-bit Flash Analog to Digital Converter. The wide

input analog bandwidth of 10MHz permits the conversion of
analog input signals with full-power frequency components
up to this limit with no input sample and hold. Low power
consumption, due to CEMOSTM processing, virtually eliminates thermal considerations. The IDT75C58 is available in
28-pin plastic and hermetic DIPs and a 28-pin LCC.
The IDT75C58 consists of a reference voltage generator,
256 comparators, encoding and EDC (Error Detection and
Correction) logic and an output data register. A single clock
starts the conversion process and controls all internal
operations. An additional comparator detects an Overflow
condition (VIN more positive than Full-Scale +1 LSB) and
activates the OVFL output. This output, together with two
output enable inputs (OE1 and OE2), allow the stacking of two
I DT75C58s for 9-bit resolution with no external components.
The IDT75C58 military Flash AID Converters are
manufactured in compliance with the latest revision of
MIL-STD-883, Class B, making them ideally suited to
military temperature applications demanding the highest
level of performance and reliability.

FUNCTIONAL BLOCK DIAGRAM
CONV
VIN

r

Rr
R1 ~

R

)

f-f--

R

'-

R

R

",256

"

~

R

As

R2 i"

-

OE1
OE2

256 TO 9
ENCODE
+EDC

W

f--+

LATCH

~ Do- D7, OVFL

.... 127
0-

R

r--to

I
tOVF~

I-a.

'128

~

Rl2~

R

~
,

~

···

~

i"

Rl2i"

%

I-a.

W.,

··

.....

2

f--~1
~CV
256 DIFFERENTIAL
COMPARATORS

I

2578 drw 01

CEMOS is a trademark 01 Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
4:>1990 Integrated Device Technology, Inc.

5.17

JUNE 1990
DSC·500413

1

IDT75C58
CMOS FLASH AiD CONVERTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
D7 (MSB)
D6
Ds
D4

INDEX

OE2
OE1

RB

, , ,

RM
VIN
VIN
AGND
RT

OVFL
D3
D2

CONV
Do
D1

II "

,

25 [: AGND
24[: IB Adj
:]7
23[: RM
:]8
L28-1
22 [: VIN
:]9
21
VIN
:]10
20 [: AGND
:]11
19[: RT
12131415161718

:]6

c:

Vee

DIP

' •• '

'i '""'1 282726

:]5

IBAdj

DGND
Vee
VEE
VEE
VEE
Vee
DGND

, ,

~~

AGND

nnnnnnn
ii8aoffi~8
~

2578 drw 02

~

8

8>

2578drw 03

LCC

TOP VIEW

TOP VIEW

GENERAL INFORMATION
The IDT75C58 has four functional sections: a comparator
array, a reference voltage generator, encoding logic with EDC
and output logic. The comparator array compares the input
signal with 256 reference voltages to produce an N - of - 256
code. This is sometimes called a "Thermometer" code because
all of the comparators with their reference voltage less than
the input signal will be "on" while those with their reference
above the input will be "off".
The reference voltage generator consists of a string of
precisely matched resistors which generate the 256 voltages
needed by the comparators. The voltages at the ends of the
resistor string set the maximum and minimum conversion
range and are typically OV and -2V, respectively.
Included in the encoding function is Error Detection and
Correction logic which ensures that a corrupted Thermometer
code is correctly encoded.
The output logic latches and holds the data constant
between samples. The output timing is designed for an easy
interface to external latches or memories using the same
clock as the ADC.

across the reference resistor chain (VRT-VRS) must be between 1.8V and 2.2V, with VRT more positive than VRS.
Nominally, VRT = O.OV and VRS = -2.0V.
The IDT75C58 provides a midpoint tap, RM, which allows
the converter to be adjusted for optimum linearity or a nonlinear transfer function. Adjustment of RM is not necessary to
meet the linearity specification. Figure 6 shows a circuit which
will provide approximately 112 LSB adjustment to the midpoint. The characteristic impedance of RM is about 170Q and
this node should be driven from a low impedance source. Any
noise introduced at this point will couple directly into the
resistor chain, seriously affecting performance.
Due to the unavoidable coupling with the clock and the
input signal, RT and Rs should provide low AC impedance to
ground~ For applications with a fixed reference, a bypass
capacitor is recommended.

CONTROL
Two function control pins, OE1 and OE2, control the
outputs with the function shown in Table 1.

18 Adj
POWER
The IDT75C58 requires two power supply voltages, vcc
and VEE. Typically, VEE = -5.0V and vcc = +5.0V. Two
separate grounds are provided, AGND and DGND, the analog
and digital grounds. The difference between AGND and DGND
must not exceed ± 0.1 V and all power and ground pins must
be connected.

An analog control pin, IB Adj, controls the bias current in the
comparators. Normally, this pin is connected to analog ground.
To reduce the quiescent current, a "power-down" mode,
IB Adj, may be connected to VEE. For somewhat better analog
performance at higher input frequencies, IB Adj may be
connected to a voltage between AGND and Vcc.

CONVERT
REFERENCE
The IDT75C58 converts analog input signals that are within
the range of the reference (VRS ::; VIN ::; VRT) into digital form.
VRS (Reference Bottom) and VRT (Reference Top) are applied
across the reference resistor chain and both must be within
the range of +2.1 V to -2.1 V. In addi~ion, the voltage applied

The IDT75C58 begins a conversion with every rising edge
of the convert signal, CONV. The analog input signal is
sampled on the rising edge of CONV, while the outputs of the
comparators are encoded on the falling edge. The next rising
edge latches the encoder output which is presented on the
output pins.

5.17

2

5

IDT75C58
CMOS FLASH AJD CONVERTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

The input sample is taken within 15ns of the rising edge of
CONV. This is caHed tSTO or the Sampling Time Offset. This
delay varies by a few nanoseconds from part to part and as a
function of temperature, but the short term uncertainty or jitter
is less than 60ps. The maximum CONV pulse width LOW time
(tPWL) may be exceeded, but the digital output data for the
sample taken by the previous rising edge of CON V will be
meaningless. It is recommended that CONV be held LOW
during longer periods of inactivity.
The digital output data is presented at to, the Digital Output
Delay Time, after the next rising edge of CONV. Previous
output data is held for the tHO (Output Hold Time) after the
rising edge of CONV to allow for non-critical timing in the

external circuitry. This means that the data for sample N is
acquired while the converter is taking sample N + 2.

ANALOG INPUT
The IDT75C58 uses strobed, auto-zeroing, latching comparators. Both analog input pins must be connected together
as close the package as possible. The input Signal must
remain within the range of VCe to VEE to prevent damage to
the device.
lithe analog input signal is within the reference voltage
range, the output will be a binary number between 0 and 255.
An input signal below VRS will yield a full-scale (all outputs low)
output while an input above VRT will cause OVFL output.

Range

Step

Output

OVFL

-2.0000V FS
7.8125mV/Step

-2.0480V FS
8.000mV/Step

256
255
254

O.OOOOV
-0.007BV
-0.0156V

O.OOOOV
-O.OOBOV
-0.0160V

11111111
11111111
11111110

1
0
0

129
12B
127

-0.9961V
-1.0039V
-1.0118V

-0.o160V
-1.0240V
-1.0320V

10000000
01111111
01111110

0
0
0

001
000

-1.9921V
-2.0000V

-2.040V
-2.04BV

0000·0001
00000000

0

··
·

.
.

.

.

··

··
·

a·
2578 drw 04

Figure 1. Output Coding

CONy

ANALOG INPUT

SAMPLE N+2

~~tsTO
tD

~

tHO

__

I

j.DATA
N

DIGITAL OUTPUT

Figure 2. Timing Diagram

5.17

2578 drw 05

3

IDT75C58
CMOS FLASH AID CONVERTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)

._X

OE1,OE2

I

tHZ,tZL

....

.

Rating

Symbol

Value

Unit

Power Supply
Vee

Measured to DGND

-0.5 to +7.0

V

Do, D7

VEE

Measured to AGND

-0.5 to -7.0

V

OVFL

AGND

Measured to DGND

-0.5 to +0.5

V

Measured to DGND

-0.5 to Vee +0.5

V

Input Voltage
2578 drw06

CONV,OE1,
FIgure 3. Output, Enable/DIsable Timing

OE2

Vcc

VIN, VRT, VRB

Measured to AGND

VRT

Measured to VRB

Vceto VEE

V

-4.0 to +4.0

V

-0.5 to Vce +0.5

V

-3.0 to +6.0

mA

1.0

S

-55 to +125

°C

-0 to +70

°C

Output

8100.

TO
OUTPUTu-____~--~--~
PIN

1N3062

Applied
Voltage (2)

Measured to DGND

Applied
Current (2. 3, 4)

Externally forced

Short Circuit
Duration

Single output High to
DGND

Temperature

2578 drw 07

Figure 4. Output Load 1

OE1

OE2

Do - 07

OVFL

0

1

Valid

Valid

1

1

HighZ

Valid

X

0

High Z

High Z
2578tbl01

Table 1. Function Control

Operating,

Military

Ambient

Commercial

Storage

Military

-65 to +150

°C

Commercial

-55 to +125

°C

NOTES:
2578 till 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. Absolute Maximum
Ratings are limiting values applied individually while all other parameters
are within specified operating conditions. Functional operation under any
of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current when flowing into the device.

5.17

4

II

IDT75C58
CMOS FLASH AID CONVERTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS
Temperature Range
Military

Commercial
Parameter

SYmbol

Test Conditions(1)

Min.

Nom.

Max.

Min.

Nom.

Max.

Unit

V

Power Supply
Vee

Positive Power Supply

4.75

5.0

5.25

4.5

5.0

5.5

VEE

Negative Power Supply

-4.75

-5.2

-5.5

-4.5

-5.2

-5.5

V

VAGND

Analog Ground Voltage (ref DGND)

-0.1

0

+0.1

-0.1

0

-10.1

V

Icc

Positive Supply Current

Vee = Max., Static(l)

70

-

60

80

mA

Negative Supply Current

VEE = Max., Static(l)

-

50

lEE

-15

-25

-

-15

-25

mA

-

0.8

V

Vee +.1

V

±10

J-l-A

Digital Inputs (CONV, NMINV, NLlNV)
VIL

Input Voltage, Logic LOW(4)

-0.5

-0.5

Input Voltage, Logic HIGH(4)

2.0

-

0.8

VIH

Vee +.1

2.0

IlL

Input Current, Logic LOW

Vee = Max., VIL = 0.5V

-

-

±10

IIH

Input Current, Logic HIGH

Vee = Max., VIH = 2.4V

-

-

±10

II

Input Current, Max. Input Voltage

Vee = Max., VI = Vee

-

-

50

CI

Digital Input Capacitance(4)

TA = +25°C, F = 1MHz

-

-

15

-

-

±10

J-l-A

-

50

J-l-A

15

pF

-

4.0

mA

-2

mA
J-l-A

Digital Outputs
10L

Output Current, Logic LOW

Vee = Min., Vo = 0.4V

-

-

4.0

-

10H

Output Current, Logic HIGH

Vee = Min., Vo = 2.4V

-

-

-2

-

loz

Output HIGH Z Current(4)

Vee = Max.

-

5

-

-

5

-

VOH

Output Voltage, Logic HIGH

Vee = Min., 10H = Max.

2.4

-

-

2.4

-

V

VOL

Output Voltage, Logic Low

Vee = Min., 10L = Max.

-

-

0.5

0.5

V

los

Output Short Circuit Current

Vee = MaxP)

-

-

-50

-

-

-50

mA

Reference
VRT

Most Positive Reference Voitage(3)

-0.1

0

+0.1

-0.1

0

+0.1

V

VRS

Most Negative Reference Voltage(3)

-1.9

-2.0

-2.1

-1.9

-2.0

-2.1

V

VRTVRS

Reference Voltage Range

1.8

2.0

2.2

1.8

2.0

2.2

V

IREF

Reference Current (RT to Rs)

VRT, VRS = Nom.

9

-

RREF

Reference Current (RT to Rs)

VRT, VRS = Nom.

250

400

-

220

-

5

6
330

10

-

mA
Ohm

Analog Input
VIN

Input Voltage Range

VRS

-

VRT

VRS

-

VRT

RIN

Equiv. Input Resistance(4)

VRT, VRS= Nom., VIN = VRS

100

-

-

100

-

CIN

Equiv. Input Capacitance(4)

VRT, VRS= Nom., VIN = VRS

Input Const. Bias Current

VEE = Max.

-

-

50

les

-

-

10

TA

Ambient Temperature, Still Air

0

-

70

Te

Case Temperature

-

-

-

-55

V
KOhm

50

pF

10

J-l-A

-

°C

+125

°C

NOTES:
25781bI03
1. Worst case, all digital inputs and outputs LOW.
2. Output HIGH, one pin to ground, one second duration.
3. VAT must be more positive than VAB and the voltage reference must be within the specified range. Although the device is specified and tested with the
reference equal to OV and -2V, the part will operate with VAT up to +2.1V. Likewise, the reference range may vary from 1.2V to 2.6V.
4. This parameter is guaranteed but not tested in production.

5.17

5

IDT75C58
CMOS FLASH AID CONVERTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS FOR IDT75C58X20 (20MHz Version)
Specifications over the DC Electrical range unless otherwise stated.
Temperature Range
Military

Commercial
Symbol

Parameter

Test Conditions
Vee = Min., VEE

= Min.

Min.

Typ.

20

30

Max.

-

Min.

Typ.

20

30

-

Fs

Conversion Rate

tPWl

CONV, Pulse Width LOW(4)

18

-

100,000

18

tPWH

CONV, Pulse Width HIGH(4)

22

-

20,000

22

tSTO

Sampling Time Offset

0

10

0

EAP

Aperture Error'S)

-

-

60

tD

Digital Output Delay

Vee = Min., VEE = Min.,
Load 1

-

-

30

-

tHO

Digital Output Hold Time

Vee = Min., VEE
Load 1

= Min.,

5

-

-

5

tHZ

Output Disable Time from HIGH(S)

Vee = Min., VEE
Load 1

= Min.,

-

5

10

tlZ

Output Disable Time from LOWS)

Vee = Min., VEE
Load 1

= Min.,

-

5

tZH

Output Enable Time to HIGH(S)

Vee = Min., VEE
Load 1

= Min.,

-

tZl

Output Enable Time to LOW(S)

ELI

Linearity Error, Integral

Vee = Min., VEE = Min.,
Load 1
1112 LSB(2)
VRT,

Linearity Error, Differential

= Nom. 13/4 LSB(2)
VRT, VRB = Nom.

Vee = Min., VEE

= Min.

VRB

ELD
CS

Code Size(1)

EaT

Offset Error, Top

EOB

Offset Error, Bottom

Eoo

Offset Error, OVFL(3)

Teo

Offset Error,
Temperature Coefficient(S)

= Midpoint Code 255
VIN = Midpoint Code 0
VIN = VRT
VIN = VRB
VIN

-

Unit
MSPS

100,000

ns

20,000

ns

15

ns

60

ps

35

ns

-

-

ns

-

5

10

ns

10

-

5

10

ns

12

18

-

12

-

ns

-

12

18

-

12

18

ns

-

-

0.2

-

0.2

%FS

0.3

%FS

0.2

-

0.2

%FS

25

100

175

%Nom

10

20

mV

0.3

100

175

25

-

10

20

-

-

-10

-20

-6

0

6

-

-

±20

BW

Bandwidth, Full Power Input

7

12

-

TTR

Transient Response, Full Scale(S)

-

-

20

SNR

Signal to Noise Ratio

20 MSPS Conversion Rate,
1OMHz Bandwidth

Peak Signal/RMS Noise

1.248MHz Input
2.438MHz Input

54
53

56
56

RMS Signal/RMS Noise

1.248MHz Input
2.438MHz Input

45
44

47
47

NPR

Noise Power Ratio

DC to 1OMHz White Noise'
Bandwidth 4 Sigma Loading
1.248MHz Slot
20 MSPS Conversion Rate

36.5

39

-

DP

Differential Phase Error

Fs

DG

Differential Gain Error

Fs

= 4 x NTSC
= 4x NTSC

Max.

-

.5

1

-

1

2

-10

-20

mV

-6

0

6

mV

-

-

±20

IlV/ 0 C

10

-

-

-

20

ns

53
52

55
55

dB
dB

44
43

46
46

36.5

39

-

5

-

MHz

dB
dB
dB

.5

1

Degree

1

2

%

2579 tbl 04
NOTES:
1. Guarantees no missing codes.
2. See the ordering information section regarding the part number designation.
3. A OmV offset means 1 LSB above the 255th code threshold.
4. No damage to the part will occur if the Max. times are exceeded. See the Convert section for more information about the Conv Max. time limitations.
5. This parameter is guaranteed but not tested in production.
'

5.17

6

I

1DT75C58
CMOS FLASH AID CONVERTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS FOR IDT75C58X30 (30MHz Version)
Specifications over the DC Electrical range unless otherwise stated.
Temperature Range
Symbol
Fs

Parameter
Conversion Rate

Test Conditions
Vcc = Min., VEE

= Min.

Commercial
Typ. Max.
Min.
30

40

-

Min.

Military
Max.
Typ.

-

Unit

30

40

MSPS

100,000

14

-

100,000

ns

20,000

11\

-

20,000

n::;

10

0

15

ns

60

ps

EAP

Aperture Error(S)

tD

Digital Output Delay

Vee = Min., VEE
Load 1

= Min.,

-

-

tHO

Digital Output Hold Time

Vce = Min., VEE
Load 1

= Min.,

5

-

tHZ

Output Disable Time from HIGH(S)

Vee = Min., VEE
Load 1

= Min.,

-

5

-

-

5

-

ns

tlZ

Output Disable Time from LOWS)

Vee = Min., VEE
Load 1

= Min.,

-

5

-

-

5

-

ns

tZH

Output Enable Time to HIGH(S)

Vee = Min., VEE
Load 1

= Min.,

-

12

-

-

12

-

ns

tZl

Output Enable Time to LOW(S)

-

12

-

-

12

-

ns

ELI

Linearity Error, Integral

Vee = Min., VEE = Min.,
Load 1
13/4 LSB(2)
VRT,

-

-

-

0.3

%FS

-

-

0.3

= Nom. 11 LSB(2)
VRT, VRS = Nom.

0.4

-

-

0.4

%FS

-

-

0.2

-

-

0.2

%FS

25

100

175

25

100

175

%Nom

-

45

20

mV

-30

-20

mV

0

6

mV

±20

IlV/o C

tPWl

CONV, Pulse Width LOW(4)

14

tPWH

CON V, Pulse Width HIGH(4)

14

tsTO

Sampling Time Offset

Vee = Min., VEE

= Min.

VRS
ELD

Linearity Error, Differential

CS

Code Size(1)

= Midpoint Code 255

0

60

-

-

25

-

-

28

ns

-

5

-

-

ns

EOT

Offset Error, Top

VIN

-

10

45

Eos

Offset Error, Bottom

VIN = Midpoint Code 0

-

-10

-30

Eoo

Offset Error, OVFL(3)

VIN = VRT

-6

0

6

Teo

Offset Error,
Temperature Coefficient(S)

VIN = VRS

-

-

±20

-6

-

-

BW

Bandwidth, Full Power Input

10

13

-

10

-

TTR

Transient Response, Full Scale(S)

-

-

20

-

-

20

ns

SNR

Signal to Noise Ratio

30 MSPS Conversion Rate,
15MHz Bandwidth

Peak Signal/RMS Noise

5MHz Input
10MHz Input

44
44

48
48

44
44

48
48

-

dB
dB

RMS Signal/RMS Noise

5MHz Input
10MHz Input

35
35

39
39

35
35

39
39

-

dB
dB

DC to 15MHz White Noise
Bandwidth 4 Sigma Loading
5MHz Slot
30 MSPS Conversion Rate

-

-

-

-

-

-

.5

1

1

2

-

.5

1

1

2

NPR

Noise Power Ratio

DP

Differential Phase Error

Fs = 4x NTSC

DG

Differential Gain Error

Fs = 4x NTSC

NOTES:

1.
2.
3.
4.
5.

8

MHz

-

dB

Degree
%
2578tbl05

Guarantees no missing codes.
See the ordering information section regarding the part number designation.
A OmV offset means 1 LSB above the 255th code threshold.
No damage to the part will occur if the Max. times are exceeded. See the Convert section for more information about the Conv Max. time limitations.
This parameter is guaranteed but not tested in production

5.17

7

1DT75C58

CMOS FLASH AiD CONVERTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

+5V----------~------------------~------------~--------_,

~
V

R1

L1

R3

I

+

C1V

C16

C13
R5

ANALOG

C15

INPUT
R7

18V

V
R6
R12

>

cc
21
VIN
22
VIN

6

10

CC

cc

IBAdj

24

PARTS LIST
R1
o.on
R2
80.7n
R3
1Kn
R4
2Kn
R5
22n
R6
2Kn
R7
1Kn
R8
2Kn
R9
2Kn
R10
10Kn
R11
20Kn
R12
27n

AM
OVFL
26
C4
L2

RB

20,25 AGND
19

I

Rr

01

D7(MSB)
Os
Os
04
03

17

5,11
CLOCK--------~----~----~------~------~

02
CONV
01
DGND
Do (LSB)
7,8,9

13
14
15
16

cfv

-------4------------------------'.---1

-5.2V ----------......----------......

C14v

C1-C4
C5-C15
C16

10llF
O.1IlF
1-6pF Variable

U1
U2
U3
U4

IOT75C58
HA-2539-5
uA741C
LM313

01

2N2907

L1.L2

Ferrite Bead

2578 drw08

Figure 5. Application Example

RT

10T75C58

2578 drw 09

Figure 6. Mid-Point Adjust

5.17

8

II

IDT75C58
CMOS FLASH AID CONVERTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CALIBRATION

TYPICAL INTERFACE

The calibration of the IDT75C58 involves the setting of the
1st and 255th comparator thresholds to the desired voltages.
This is done by varying the top and bottom voltages on the
reference resistor chain, VAT and VAB, to compensate for any
internal offsets. Assuming a nominal OV to -2V reference
range, apply-O.0039V (1/2 LSB from OV) to the analog input,
continuously strobe the device and adjust VRT until the OVFL
output toggles between 0 and 1 . To adjust the first comparator,
apply -1.996V (1/2 LSB rrom -2V) to the analog input and
adjust VRB until the converter output toggles between the
codes 0 and 1.
The offset errors are caused by the parasitic resistance
between the package pins and the actual resistor chain onchip and are shown as R1 and R2 in the Functional Block
Diagram. The offset errors, EOT and EOB, are specified in the
AC Electrical Characteristics and indicate the degree of
adjustment needed.
The previously described calibration scheme requires that
both ends of the reference resistor chain be adjustable, i.e. be
driven by operational amplifiers. A simpler method is to
connect the top of the resistor chain, RT, to analog ground or
OV and to adjust this end of the range with the input buffer
offset control. The offset error at the bottom of the resistor
chain results in a Slight gain error which can be compensated
for by varying the voltage applied to RB. This is a preferred
method for gain adjustment since it is not the input signal path.
See Figure 5 for a detailed circuit diagram of this method.

Figure 5 shows a typical application example for the
IDT75C58. The analog input amplifier is a bipolar wide band
operational amplifier whose low impedance output directly
drives the AID Converter. The input buffer amplifier is configured with a gain of minus two which will convert a standard
video input signal (1 V p-p) to the recommended 2V converter
input range. Both VIN pins are connected together as close to
the package as possible and the input buffer feedback loop is
closed at this point. Bipolar inputs, as well as the calibration of
the reference top, are accomplished using the offset control.
A band-gap reference is used to provide a stable voltage for
both the offset and gain control. A variable capacitor in the
input buffer feedback loop allows optimization of either the
step or the frequency response and may be replaced by a
fixed value in the final version of the printed circuit board.
To ensure operation to the rated specifications, proper
decoupling is needed. The bypass capacitors should be
located close to the chip with the shortest lead lengths
possible. Massive ground planes are recommended. If separate digital and ground planes are used, they should be
connected together at one point close to the IDT75C58.
The bottom reference voltage, VRB, is supplied by an
inverting amplifier buffered by a PNP transistor. The transistor
provides a low impedance source and is necessary to provide
the current flowing through the resistor chain. The bottom
reference voltage may be adjusted to cancel the gain error
introduced by the offset voltage, EOB, as discussed in the
calibration section.

CLOCK
ANALOG

INPUT

CON V

OE1 I--OV

VIN

OE2

RT

OV

IOT?5C58

··

00- 07

RB

I
-

CON V

OE2 1--5V

VIN

OE1

ClK

IOT?5C58

RT
-2V

lATCH

OVFl

RB
00- 07

··

IN8

Os

IN?

07

INO

00

··

·· ··

Os (MSB)

Do (lSB)
2578 drw 10

Figure 7. Simplified 9-Bit Application

5.17

9

IDT75C58
CMOS FLASH AiD CONVERTER

MIUTARV AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION

Vee

o--e 7.0V

soon

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
257811>16
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

PULSE WIDTH

-= ~~V

J

.-.,...-._;...".a -

OV

tsu~>/4--~

TIMING - - - - - - . . . . .
INPUT _ _ _ _ _ _-'

LOW-HIG~U~~

- 3V
V
_

6J

ASYNCHRONOUS CONTROL
PRESET - - - - . . . . . ~-+----I----­ - 3V
CLEAR
- - + - - - - - - 1.SV
- OV
ETC. - - - - "
SYNCHRONOUS CONTROL
CLOCK

:~~~~~
vvJr J
ETC.~SU

" " -_ _ _ _;...,,.a

=t-

HIGH-LOW-HIGH
PULSE

~ 15V
tw

_ _ 1.5V

II

3V

-1.SV
OV

t

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

- - -.... - - - - 3 V
SAME PHASE
INPUT TRANSITION

~~'+----OV

OV

3.SV

_-...;..._.+--- VOH
OUTPUT

DISABLE
----3V
---1.5V

-1.SV

VOL

VOL

VOH

OPPOSITE PHASE
INPUT TRANSITION

SWITCH
OPEN
_ _ _..I - - - -

OV

OV

NOTES
2578 drw 12
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate $ 1.0 MHz; Zo:s son; tF:S 2.5ns;
tR:S 2.5ns.

5.17

10

IDT75C58
CMOS FLASH AID CONVERTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

lOT

XXX X
----Device Type

x

x

x

x

Power

Speed

Package

Processl
Temperature
Range

~~Iank
L . -_ _ _ _ _- - /

Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883,

Cla~~

B

D
L

CERDIP (600 mil)
LCC (450 mil square)

20

MHz
MHz

S

Standard Power, 1/2 LSB Integral Linearity
Standard Power, 3/4 LSB Integral Linearity
Standard Power, 1 LSB Integral Linearity

~----------~30

1...----------------4 SB
SC

1...---------------------1 75C58

Flash AID Converter
257Bdrw 11

5.17

11

STANDARD LOGIC PRODUCTS

II

STANDARD LOGIC PRODUCTS
The demand for high-performance systems continues to
push the need for faster and faster clock frequencies that
exceed the capabilities of ASICs and older generation logic
families such as FASTTM and FACTTM. The use of high-speed
MSI logic building blocks in the "speed-critical" processor/
memory interface has allowed designers to produce the
highest performance 25/33MHz microprocessor-based systems. The use of MSllogic with the fastest speed and lowest
switching noise characteristics, as realized by the FCT-CT
devices, has become all pervasive in today's high-performance systems.
The Standard Logic Product Line represents families of
Memory and Bus Interface Devices that take advantage of two
different IDT technology platforms.
The FCT and FCT-T (Fast CEMOSTM TTL-compatible)
logic families have taken advantage of the pioneering IDT has
done in CMOS technologies. Today's technology utilizes
state-of-the-art sub-micron and double-layer metal processing.
The FBT (Fast BiCEMOSTM TTL-compatible) logic family is
manufactured using an advanced dual metal BiCMOS technology that combines the most advanced sub-micron CMOS
technology with high-performance bipolar processing.

THE FCT & FCT-T LOGIC FAMILY
This logic family was designed to allow easy upgrade of
0lderbipolar54/74F and Am29000 series deSigns totheirperformance equivalents in CMOS. The FCTfamilycomes intwo
versions. There is the standard switching noise version (FCT)
and a low switching noise version called FCT-T. Each version
has various speed grades. Key features of these families are:
• FCT/FCT-T isadirectreplacementofthe FAST family of
products.
• FCT/FCT-T is a direct replacement of the Am29000
family of products.
• FCT-A series is up to 25% faster than FCT speeds with
standard switching noise.
• FCT-AT series is equivalent to FCT-A speeds with low
switching noise.
• FCT-C series is up to 50% faster than FCT, with standard switching noise.
• FCT-CT series is equivalent to FCT-C speeds with low
switching noise.

• High output drive to 64mA (commercial) and 48mA
(military).
• Substantially lower input current levels (5JlA maximum).
• Consistent with JEDEC Standard No. 18.
• Excellent ESD and latch-up immunity.

THE FBT LOGIC FAMILY
This logic family is manufactured using an advanced BiCEMOS, dual metal technology. This technology provides the
highest device speeds while minimizing simultaneous switching noise and maintaining CMOS power levels. The FBT
family comes in various speed grades. Key features of this
family are:
• FBT series is equivalent to BCT speeds with ultra-low
switching noise.
• FBT -A series is up to 30% faster than BCT speeds, with
low switching noise.
• FBT-C series is up to 45% faster than BCT speeds with
low switching noise.
• Output drive to 64mA (commercial) and 48mA (military)
(non-resistor parts).
• CMOS power levels (5~W typical static).
• TTL-compatible input and output levels.
• High-impedance in power-off state.
• Some devices have 25Q series resistor outputs.
• JEDEC standard pinout for DIP, SOIC and LCC packages.
A series of memory driver functions ave been designed
using the BiCEMOS process. These functions include a 25Q
series resistor on the output driver, acting as a series termination. This results in a greater ability to drive transmission lines· •
with high-capacitance loads such as large banks of memory.
AIiIDT logic devices are manufactured and assembled on
a MIL-STD-883, Class B compliant line. Key features of the
military products include:
• Fully compliant to MIL-STD-883, Class B.
• Offer numerous devices to DESC drawings.
• Available in Radiation Tolerant and Radiation Enhanced
versions.
• Packages include hermetic DIP, LCC and CERPACK.
Commercial products are manufactured using the same
production line and stringent quality requirements acquired
from building military products. All commercial products are
available in dual in-line as well as surface mount packages.

PRODUCT MATRIX
NOISE
Standard
Improved
Low
Ultra-Low
SPEED

FCT-A
FCT-CT
FBT-C
Very Hioh-Speed

FCT-AT
FBT
Hioh-Speed

6.0

FCT
FCT-T
FAST

TABLE OF CONTENTS
STANDARD LOGIC PRODUCTS
I DT29FCT52T
IDT29FCT53T
IDT29FCT520T
IDT29FCT521T
IDT54/74FCT138T
IDT54/74FCT139T
IDT54/74FCT151T
IDT54/74FCT251T
IDT54/74FCT157T
I DT54/74FCT257T
IDT54/74FCT161T
IDT54/74FCT163T
IDT54/74FCT191T
IDT54/74FCT193T
I DT54/74 FCT240T
I DT54/74FCT241T
IDT54/74FCT244T
IDT54/74FCT540T
IDT54/74FCT541T
I DT54/74 FCT245T
IDT54/74FCT640T
IDT54/74FCT645T
IDT54/74 FCT273T
I DT54/74FCT299T
I DT54/74FCT373T
IDT54/74FCT533T
IDT54/74FCT573T
I DT54/74FCT374T
I DT54/74FCT534T
I DT54/74 FCT574T
IDT54/74FCT377T
I DT54/74FCT399T
IDT54/74FCT521T
I DT54/74FCT543T
I DT54/74FCT646T
I DT54/74FCT648T
IDT54/74FCT651T
I DT54/74FCT652T
I DT54/74FCT620T
I DT54/74FCT623T
IDT54/74FCT621T
I DT54/74FCT622T
IDT54/74FCT821T
I DT54/74FCT823T
I DT54/74FCT825T
IDT54/74FCT827T
I DT54/74FCT828T
I DT54/74FCT841 T
I DT54/74FCT843T
I DT54i74FCT845T
IDT29FCT52
IDT29FCT53

PAGE
Non-inverting Octal Registered Transceiver ................................................................. 6.1
Inverting Octal Registered Transceiver ......................................................................... 6.1
Multi-level Pipeline Register .......................................................................................... 6.2
MUlti-level Pipeline Register .......................................................................................... 6.2
1-of-8 Decoder ............................................................................................................... 6.3
Dual 1-of-4 Decoder ...................................................................................................... 6.4
8-lnput Multiplexer ......................................................................................................... 6.5
8-lnput Multiplexer w/3-State ......................................................................................... 6.5
Quad 2-lnput Multiplexer ............................................................................................... 6.6
Quad 2-lnput Multiplexer w/3-State ............................................................................... 6.6
Synchronous Binary Counterw/Asynchronous Master Reset ....................................... 6.7
Synchronous Binary Counter w/Synchronous Reset ..................................................... 6.7
Up/Down Binary Counter w/Preset and Ripple Clock .................................................... 6.8
Up/Down Binary Counter w/Separate Up/Down Clocks ................................................ 6.9
Inverting Octal Buffer/Line Driver ................................................................................. 6.1 0
Non-inverting Octal Buffer/Line Driver .......................................................................... 6.10
Non-inverting Octal Buffer/Line Driver .......................................................................... 6.10
Inverting Octal Buffer/Line Driver ................................................................................. 6.10
Non-inverting Octal Buffer/Line Driver .......................................................................... 6.10
Non-inverting Octal Transceiver ................................................................................... 6.11
Inverting Octal Transceiver .......................................................................................... 6.11
Non-inverting Octal Transceiver ................................................................................... 6.11
Octal D Flip-Flop w/Common Master Reset ................................................................. 6.12
8 Input Universal Shift Register w/Common Parallel flO Pins ...................................... 6.13
Non-inverting Octal Transparent Latch w/3-State ........................................................ 6.14
Inverting Octal Transparent Latch w/3-State ................................................................ 6.14
Non-inverting Octal Transparent Latch w/3-State ........................................................ 6.14
Non-inverting Octal D Register ..................................................................................... 6.15
Inverting Octal D Register ............................................................................................ 6.15
Non-inverting Octal D Register ..................................................................................... 6.15
Octal D Flip-Flop w/Clock Enable ................................................................................. 6.16
Qu ad Dual-Port Register .............................................................................................. 6.17
8-Bit Identity Comparator ............................................................................................. 6.18
Non-inverting Octal Latched Transceiver ..................................................................... 6.19
Non-inverting Octal Registered Transceiver ................................................................ 6.20
Inverting Octal Registered Transceiver ........................................................................ 6.20
Inverting Octal Registered Transceiver ........................................................................ 6.20
Non-inverting Octal Registered Transceiver ................................................................ 6.20
Inverting Octal Bus Transceiver w/3-State ................................................................... 6.21
Non-inverting Octal Bus Transceiver w/3-State ............................................................ 6.21
Non-inverting Octal Bus Transceiver (Open Drain) ...................................................... 6.22
Inverting Octal Bus Transceiver (Open Drain) ............................................................ 6.22
10-Bit Non-inverting Register w/3-State ....................................................................... 6.23
9-Bit Non-inverting Register w/Clear & 3-State ............................................................ 6.23
8-Bit Non-inverting Register w/Clear & 3-State ............................................................ 6.23
10-Bit Non-inverting Buffer ........................................................................................... 6.24
10-Bit Inverting Buffer ................................................................................................... 6.24
1O-Bit Non-inverting Latch ............................................................................................ 6.25
9-Bit Non-inverting Latch .............................................................................................. 6.25
8-Bit Non-inverting Latch .............................................................................................. 6.25
Non-inverting Octal Registered Transceiver ................................................................ 6.26
Inverting Octal Registered Transceiver ........................................................................ 6.26

6.0

2

STANDARD LOGIC PRODUCTS (CONTINUED)
PAGE
IDT29FCT520
Multi-level Pipeline Register ......................................................................................... 6.27
16-Bit Synchronous Binary Counter ............................................................................. 6.28
IDT49FCT661
IDT49FCT804
High-Speed Tri-Port Bus Multiplexer ............................................................................ 6.29
IDT49FCT805
Buffer/Clock Driver w/Guaranteed Skew ...................................................................... 6.30
IDT49FCT806
Buffer/Clock Driver w/Guaranteed Skew ...................................................................... 6.30
IDT49FCT818
Octal Register with SPCTM ........................................................................................... 6.31
IDT49C25
Microcycle Length Controller ........................................................................................ 6.32
IDT39C8XX
IDT39C8XXX Family .................................................................................................... 6.33
IDT54/74FCT138
1-of-8 Decoder ............................................................................................................. 6.34
IDT54/74FCT139
Dual 1-of-4 Decoder ..................................................................................................... 6.35
IDT54/74FCT161
Synchronous Binary Counter w/ Asynchronous Master Reset.. .................................... 6.36
IDT54/74FCT163
Synchronous Binary Counter w/Synchronous Reset .................. :................................. 6.36
I DT54/74FCT182
Carry Lookahead Generator ......................................................................................... 6.37
IDT54/74FCT191
UplDown Binary Counter w/Preset and Ripple Clocks ................................................. 6.38
IDT54/74FCT193
Up/Down Binary Counter w/Separate Up/Down Clocks ............................................... 6.39
IDT54/74FCT240
Inverting Octal Buffer/Line Driver ................................................................................. 6.40
IDT54/74FCT241
Non-inverting Octal Buffer/Line Driver .......................................................................... 6.40
IDT54/74FCT244
Non-inverting Octal Buffer/Line Driver .......................................................................... 6.40
IDT54/74FCT540
Inverting Octal Buffer/Line Driver ................................................................................. 6.40
IDT54/74FCT541
Non-inverting Octal Buffer/Line Driver .......................................................................... 6.40
IDT54/74FCT245
Non-inverting Octal Transceiver ................................................................................... 6.41
IDT54/74FCT640
Inverting Octal Transceiver .......................................................................................... 6.41
IDT54/74FCT645
Non-inverting Octal Transceiver ................................................................................... 6.41
IDT54/74FCT273
Octal D Flip-Flop w/Common Master Reset ................................................................ 6.42
IDT54/74FCT299
8-lnput Universal Shift Register w/Common Parallel I/O Pins ...................................... 6.43
IDT54/74FCT373
Non-inverting Octal Transparent Latch ........................................................................ 6.44
IDT54/74FCT533
Inverting Octal Transparent Latch ................................................................................ 6.44
IDT54/74FCT573
Non-inverting Octal Transparent Latch ........................................................................ 6.44
IDT54/74FCT374
Non-inverting Octal D Flip-Flop .................................................................................... 6.45
IDT54/74FCT534
Inverting Octal D Flip-Flop w/3-State ............................................................................ 6.45
IDT54/74FCT574
Non-inverting Octal D Register w/3-State ..................................................................... 6.45
IDT54/74FCT377
Octal D Flip-Flop w/Clock Enable ................................................................................. 6.46
IDT54/74FCT399
Quad Dual-Port Register .............................................................................................. 6.47
IDT54/74FCT521
8-Bit Identity Comparator ............................................................................................. 6.48
IDT54/74FCT543
Non-inverting Octal Latched Transceiver ..................................................................... 6.49
IDT54/74FCT646
Non-inverting Octal Registered Transceiver ................................................................ 6.50
IDT54/74FCT821
10-Bit Non-inverting Registerw/3-State ....................................................................... 6.51
IDT54/74FCT823
9-Bit Non-inverting Register w/Clear & 3-State ............................................................ 6.51
IDT54/74FCT824
9-Bit Inverting Register w/Clear & 3-State .................................................................... 6.51
IDT54/74FCT825
8-Bit Non-inverting Register ......................................................................................... 6.51
IDT54/74FCT827
10-Bit Non-inverting Buffer ........................................................................................... 6.52
IDT54/74FCT833
8-Bit Transceiver w/Parity ............................................................................................ 6.53
IDT54/74FCT841
10-Bit Non-inverting Latch ............................................................................................ 6.54
IDT54/74FCT843
9-Bit Non-inverting Latch .............................................................................................. 6.54
IDT54/74FCT844
9-Bit Inverting Latch ...................................................................................................... 6.54
IDT54/74FCT845
8-Bit Non-inverting Latch .............................................................................................. 6.54
IDT54/74FCT861
10-Bit Non-inverting Transceiver .................................................................................. 6.55
IDT54/74FCT863
9-Bit Non-inverting Transceiver .................................................................................... 6.55
IDT54/74FCT864
9-Bit Inverting Transceiver ........................................................................................... 6.55
IDT54/74FBT240
IDT54/74FBT241
IDT54/74FBT244
IDT54/74FBT245
IDT54/74FBT373
IDT54/74FBT374
IDT54/74FBT540

Inverting Octal Buffer/Line Driver .............................. ,.................................................. 6.56
Non-inverting Octal Buffer/Line Driver .......................................................................... 6.57
Non-inverting Octal Buffer/Line Driver .......................................................................... 6.58
Non-inverting Octal Transceiver ................................................................................... 6.59
Octal Transparent Latch w/3-State ............................................................................... 6.60
Non-inverting Octal D Register ..................................................................................... 6.61
Inverting Octal Buffer .................................................................................................... 6.62

6.0

3

I

STANDARD LOGIC PRODUCTS (CONTINUED)
PAGE
IDT54/74FBT541
Non-inverting Octal Buffer ............................................................................................ 6.62
IDT54/74FBT821
10-Bit Non-inverting Register ....................................................................................... 6.63
IDT54/74FBT823
9-Bit Inverting Register ................................................................................................. 6.64
IDT54/74FBT827
Non-inverting 10-Bit Buffers/Driver ............................................................................... 6.65
IDT54/74FBT828
Inverting10-Bit Buffers/Driver ....................................................................................... 6.65
IDT54/74FBT841
10-Bit Non-inverting Latch ............................................................................................ 6.66
Inverting Octal Buffer/Line Driverw/250 Series Resistor ............................................. 6.67
IDT54/74FBT2240
Inverting Octal Buffer/Line Driver w/250 Series Resistor ............................................. 6.68
IDT54/74FBT2244
Octal Transparent Latch w/3-State & 250 Series Resistor .......................................... 6.69
IDT54/74FBT2373
IDT54/74FBT2827
Non-inverting 10-Bit Burrers/Driverw/2S0 Series Resistor .......................................... 6.70
IDT54/74FBT2828
Inverting10-Bit Buffers/Driver w/250 Series Resistor ................................................... 6.70
IDT54/74FBT2841
10-Bit Memory Latch w/250 Series Resistor ................................................................ 6.71

6.0

4

~®
Integrated Device Technology, Inc.

FAST CMOS
OCTAL REGISTERED
TRANSCEIVERS

IDT29FCT52AT/BT/CT
IDT29FCT53AT/BT/CT

FEATURES:

DESCRIPTION:

• Equivalent to AMD's Am2952/53 and Fairchild's 29F521
53 in pinout/function
• IDT29FCT52AT/53AT equivalent to FASTfM speed
• IDT29FCT52BT/53BT 25% faster than FASTTM
• IDT29FCT52CT/53CT 37% faster than FASTTM
• IOL = 64mA (commercial) and 48mA (military)
• CMOS power levels (2.5mW typo static)
• TIL input and output level compatible
• IOFF feature ideal for hot switching of backplane drivers
• Available in 24-pin DIP, SOIC, 28-pin LCC and PLCC
with JEDEC standard pinout
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• . Military product compliant to MIL-STD-883, Class B

The IDT29FCT52AT/BT/CT and IDT29FCT53AT/BT/CT
are 8-bit registered transceivers manufactured using
advanced CEMOSTM, a dual metal CMOS technology. Two
8-bit back-to-back registers store data flowing in both
directions between two bidirectional buses. Separate clock,
clock enable and 3-state output enable signals are provided
for each register. Both A outputs and B outputs are
guaranteed to sink 64mA.
The IDT29FCT52AT/BT/CT is a non-inverting option of the
IDT29FCT53AT/BT/CT.

FUNCTIONAL BLOCK DIAGRAM
CPA----__________________-,

I

CEA - - - - - - - - - - - - ,

K>--------R

,------<]0>----- OEB

Ao - - - - - - - + - - - l Do 2E CP 00

80

A1
A2
A3
A4
As

01
01B
02
02
03
A 03 ~
04 Reg. 04
05
as

B1
B2
B3
84
85

~~

~~

:~

OEA

---<:I

>------'

~R

II

00
Do I 01
01
02
D2
03
B 03
04 Reg. 04
as
05
06
06~----------~
07 CECP07~-----~

IL--_________ CPB
I~-----------CEB

Y

NOTE:
1. IDT29FCT52 function is shown.

2629drw 01

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a registered trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
e1990 Integrated Device Technology. Inc.

6.1

JUNE 1990
DSC-4224/-

1

IDT29FCT52AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

Inco,....o8,....co

INDEX

COCOCOZ>«

Vee

B7
B6
Bs
B4
B3
B2
B1
Bo
OEB
CPA
CEA
GND

L-JL-JL.....JIIL.....JL..JL.....J

A7
A6
As
A4
A3
A2
A1
Ao
OEA
CPB
CEB

4 3 2 I I 28 27 26
B4
B3
B2
NC
B1
Bo
OEB

LJ

JS
J6
J7
J8
J9
J10
J 11

2S[
24[
23[
22[
21 [

1
J28-1
L28-1

20(

19 [
12 13 14 lS 16 17 18

As
A4
A3
NC
A2
A1
Ao

,......,,.., rl""''''''''' ,..,,......,


Temperature
Under Bias
TSTG
Storage
Temperature
PT
Power Dissipation
lOUT

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

o to +70

-55 to +125

°C

-55 to + 125

-65 to + 135

°C

-55 to +125

-65 to +150

°C

DC Output Current

0.5

0.5

W

120

120

mA

Symbol

Parameter(l)

CIN

Input Capacitance

GoUT

Output Capacitance

= OV
VOUT = OV
VIN

Unit

Max.

Conditions Typ.
6

10

pF

8

12

pF

NOTE:
2619tbl04
1. This parameter is measured at characterization data but not tested.

NOTES:
2619 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +O.5V unless otherwise noted.
2. Inputs and Vec terminals.
3. Outputs and I/O terminals.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA

= -55°C to + 125°C, Vcc = 5.0V ± 10%
Min.

Typ.(2)

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

V

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

0.8

V

IIH

Input HIGH Current
Input LOW Current

-

5

IlL

= Max.
Vee = Max.
Vee = Max.

-

·5

IlA
IlA

-

10

Il A

-

-10

-0.7

-1.2

V

-60

-120

-225

mA

2.4

3.3

-

V

2.0

3.0

-

-

0.3

0.5

-

200

-

mV

0.2

1.5

rnA

Symbol

Test Condltions(1)

Parameter

10ZH

High Impedance

lozl

Output Current

= Max., VI = Vee (Max.)
= Min., IN = -18mA
Vee = MaxP), Vo = GND
Vee = Min.
VIN = VIH or Vil

II

Input HIGH Current

Vee

VIK

Clamp Diode Voltage

Vee

los

Short Circuit Current

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

VH

Input Hysteresis
Quiescent Power
Supply Current

= Min.
= VIH or Vil

Vee
VIN

Icc

= 2.7V
VI = 0.5V
Vo = 2.7V
Vo = 0.5V
VI

Vee

Vee = Max.
ViN = GND or Vee

10H = -6mA MIL.

= -8mA COM'L.
10H = -12mA MIL.
10H = -15mA COM'L.
10l = 32m A MIL.
10l = 48mA COM'L.

Max.

20

IlA

10H

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

6.2

Unit

V

2619 tbl 05

3

IDT29FCT520AT/BT/CT,521AT/BT/CT
MULTILEVEL PIPELINE REGISTERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol

Parameter

Typ.(2)

Max.

Unit

-

0.5

2.0

rnA

VIN = Vee
VIN = GND

-

0.15

0.25

mAl
MHz

Vee = Max., Outputs Open
fep = 10MHz
50% Duty Cycle
OE = GND
One Bit Toggling
atfi = 5MHz
50% Duty Cycle

VIN = Vee
VIN = GND

-

1.7

4.0

rnA

VIN = 3.4V
VIN = GND

-

2.2

6.0

Vee = Max., Outputs Open
fep = 10MHz
50% Duty Cycle
OE = GND
Eight Bits Toggling
at fi = 5MHz
50% Duty Cycle

VIN = Vee
VIN =GND

-

7.0

12.S(5)

VIN = 3.4V
VIN=GND

-

9.2

21.S(5)

Test Condltlons(1)

~Iee

Quiescent Power Supply
Current, TIL Inputs HIGH

Vee = Max.
VIN = 3.4V(3)

IceD

Dynamic Power Supply Current(4)

Vee = Max., Outputs Open
OE=GND
One Input Toggling
50% Duty Cycle

Ie

Total Power Supply Current(6)

Min.

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vee or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT +IINPUTS + IDYNAMIC
Ic = Icc + dice DHNT + IceD (fcp/2 + fiN!)
Icc = Quiescent Current
dlcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.2

26191b106

I

4

IDT29FCT520ATlBT/CT,521AT/BT/CT
MULTILEVEL PIPELINE REGISTERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT520BT/521 BT

FCT520A T/521 AT
Com'l.
Symbol

Parameter

Com'/.

Mil.

Mil.

Condition(1) Mln.(2) Max. MlnP) Max. Mln.(2) Max. Mln.(2) Max.

FCT520CT/521 CT
Com'/.

Mil.

Mln.(2) Max. Mln.(2) Max. Unit

2.0

14.0

2.0

16.0

2.0

7.5

2.0

8.0

2.0

6.0

2.0

7.0

ns

Propagation Delay
Soor Sl to Yn

2.0

13.0

2.0

15.0

2.0

7.5

2.0

8.0

2.0

6.0

2.0

7.0

ns

tsu

Set-up Time HIGH
or lOW Dn to elK

5.0

-

6.0

-

2.5

-

2.8

-

2.5

-

2,8

-

ns

tH

Hold Time HIGH
or lOW Dn to ClK

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

ns

tsu

Set-up Time HIGH
or lOW loor 11
to ClK

5.0

-

6.0

-

4.0

-

4.5

-

4.0

-

4.5

-

ns

tH

Hold Time HIGH
or lOW loor 11
to ClK

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

ns

tPHZ
tPLZ

Output Disable Time

1.5

12.0

1.5

13.0

1.5

7.0

1.5

7.5

1.5

6.0

1.5

6.0

ns

tPZH
tpzL

Output Enable Time

1.5

15.0

1.5

16.0

1.5

7.5

1.5

8.0

1.5

6.0

1.5

7.0

ns

tw

Clock Pulse Width
HIGH or lOW

7.0

5.5

-

6.0

-

5.5

-

6.0

-

ns

tPHL
tPLH

Propagation Delay
ClKto Yn

tPHL
tPLH

CL = 50pF
RL = 500n

-

-

8.0

NOTES:

2619 tbl 07

1. See test circuit and waveforms.
2. Minimum units are guaranteed but not tested on Propagation Delays.

6.2

5

IDT29FCTS20AT/BT/CT, S21AT/BT/CT
MULTILEVEL PIPELINE REGISTERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vee

SWITCH POSITION
o--e 7.0V

soon

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

2619 Ibl 08
DEFINITIONS:
CL = load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt.

PULSE WIDTH

j >----or+""'IIr""'7Or...,.!"""7'-=
-

tsu -"0j4--~
TIMING
INPUT _ _ _ _ _ _ _

~~V

OV

6:J

LOW-HIG~~~~

3V
l.SV

HIGH-LOW-HIGH
PULSE

- 3V
_
V

ASYNCHRONOUS CONTROL
PRESET - - - - , ~--+---+---CLEAR

ETC.

-

OV

=t_

~ 1.5V
tw

_ _ l.SV

SYNCHRONOUS CONTROL
CLOCK

:~~~~~ "III:vvJr~~M-r-~1 ~+-~"""'::""'~~'7'-= ~~V
ETC.

~tsu

~..-.--~

-

OV

PROPAGATION DELAY

II

ENABLE AND DISABLE TIMES
ENABLE

DISABLE
----3V

SAME PHASE
INPUT TRANSITION

~"""'+----OV

3.SV
OUTPUT

VOL
VOH

SWITCH
OPEN

OPPOSITE PHASE
INPUT TRANSITION
' - - _ _..I - - - -

OV

OV

NOTES
2619 drw 05
1. Diagram shown for input Control Enable-lOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ son; tF ~ 2.Sns;
tR ~ 2.Sns.

6.2

6

IDT29FCT520AT/BT/CT,521AT/BT/CT
MULTILEVel PIPELINE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT29FCT

X

X

X

Device
Type

Package

Processl
Temperature
Range

1-1----11 ~Iank
P
D
L
E
SO
520AT
521AT
' - - - - - - - - - - - - - - - - - 1 520BT
521 BT
520CT
521 CT

Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP
CERDIP
Leadless Chip Carrier
CERPACK
Small Outline IC
Multilevel Pipeline Register
Multilevel Pipeline Register
Fast Multilevel Pipeline Register
Fast Multilevel Pipeline Register
Super Fast Multilevel Pipeline Register
Super Fast Multilevel Pipeline Register
2619dIW 04

6.2

7

~

FAST CMOS
1-0F-8 DECODER

IDT54114FCT138T
IDT54/74FCT138AT
IDT54114FCT138CT

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• IDT54/74FCT138T equivalent to FASl'M speed
• IDT54174FCT138AT 35% faster than FASl'M
• Equivalent to FASTTM speeds and output drive over full
temperature and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1mW typo static)
• True TTL input and output levels
• Substantially lower input current levels than FASl'M
(5J.lA max.)
• 1-of-8 decoder with enables
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54174FCT138T/AT/CT are 1-of-8 decoders built
using advanced CEMOSTM, a dual metal CMOS technology.
The IDT54/74FCT138TI AT/CT accepts three binary weighted
inputs (Ao, A1, A2) and, when enabled, provides eight mutually
exclusive active LOW outputs (50-07). The IDT54174FCT138TI
AT/CT featu res three enable inputs, two active LOW {E" 1, E2)
and one active HIGH (E3). All outputs will be HIGH unless E1
and E2 are LOW and E3 is HIGH. This multiple enable function
allows easy parallel expansion of the device to a 1-of-32 (5
lines to 32 lines) decoderwith justfour IDT54/74FCT138T/ATI
CT devices and one inverter.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

Ao
A1

Vee

50
01
02

15

2
3

"8
E2

4

E3

6

P16-1
D16-1 14
S016-2 13
&
12
E16-1
11

07

7

10

aS

GND

8

9

Os

A2.

5

(53

04
"roo."

DIP/SOIC/CERPACK
TOP VIEW
INDEX

aQUa

~«zgIO
I I I II
........,........, I

07

2

3
06

05

04

03

02

01

00
2570 cnv· 03

A2 :] 4

El

:] 5

NC

:] 6

I

II
II
I
I 1--1 1--1
I

,.,

20 19
18[:

17[:
16[:

L20-2

E2 :] 7

15[:
E3 :] 8
14[9 10111213
. . , . . , . . , .., r-t
I

II

II

I

I

2570 drw02

I

LCC
TOP VIEW

CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
11:>1990 Integrated Device Technology. Inc.

II

6.3

JUNE 1990
DSC-42131-

1

I

IDT54174FCT138T/AT/CT
FAST CMOS 1·0F·8 DECODER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION
Pin Names
Ao-A2.
E1.E2
E3

00-07

Description
Address Inputs
Enable Inputs (Active LOW)
Enable Input (Active HIGH)
Outputs lActive LOWl
257011>106

FUNCTION TABLE
E1

E2

H

X

X
X

H

L
L
L
L
L
L
L
L

Outputs

InJ:uts
E3
Ao

X
L
L
L
L
L
L
L
L

X
X
L
H
H
H
H
H
H
H
H

A1

A2

00

01

02

03

04

05

06

07

X
X
X

X
X
X

X
X
X

L
H
L
H
L
H
L
H

L
L
H
H

L
L
L
L

H
H
H
H
L
H
H

H
H
H
H
H
L
H

H
H
H
H

H
H
H
H

H
H
H
H
H
H
H
H
L
H
H

H
H
H
H
H
H
H

H
H
H
H

H
H
H
H
H
H
L
H
H
H
H

H
H
H
H
H
H
H

L
L
H
H

H
H
H
L
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H
H
H
L

L
H
H
H

H
H
L
H

257011>107

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
TSIAS
Temperature
Under Bias
TSTG
Storage
Temperature
PT
Power Dissipatior
lOUT

DC Output
Current

Commercial
-0.5 to +7.0

CAPACITANCE

Military
-0.5 to +7.0

(TA

Parameter(1)
Symbol
CIN
Input

Unit
V

= +25°C, f = 1.0MHz)
Conditions
VIN = OV

Typ.

6

Max.
10

Unit
pF

VOUT= OV

8

12

pF

C~acitance

-0.5 to Vee

-0.5 to Vee

V

o to +70

-55 to +125

°C

-55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

0.5

0.5

W

120

120

mA

COUT

Output
Capacitance

NOTE:
257011>102
1. This parameter is measured at characterization but not tested.

NOTE:
257011>101
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vec by +O.5V unless otherwise noted.
2. Input and Vce terminals only.
3. Outputs and 110 terminals only.

6.3

2

IDT54n4FCT138T/AT/CT
FAST CMOS 1-0F-8 DECODER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, VCC = 5.0V ± 5%; Military: TA
Symbol

= -55°C to +125°C, VCC = 5.0V ± 10%

Test Condltlons(l)

Parameter

Min.

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

VIL

Input LOW Level

Guaranteed Logic LOW Level

IIH

Input HIGH Current

Vee = Max.

VI = 2.7V

-

IlL

Input LOW Current

Vee = Max.

VI = 0.5V

II

Input HIGH Current

Vee = Max., VI = Vcc (Max.)

VIK

Clamp Diode Voltage

los
VOH

-

Typ.(2)

-

Max.

Unit

-

V

O.S

V

5

~A

-5

~A

20

~A

Vee = Min., IN = -1SmA

-

-0.7

-1.2

V

Short Circuit Current

Vee = Max.(3), Vo= GND

-60

-120

-225

mA

Output HIGH Voltage

Vee = Min.

10H = -6mA MIL.

2.4

3.3

-

V

VIN = VIH or VIL

10H = -SmA COM'L.
2.0

3.0

-

V

-

0.3

0.5

V

-

200

-

mV

0.2

1.5

mA

10H = -12mA MIL.
10H = -15mA COM'L.
VOL

Output LOW Voltage

VH

Input Hysteresis

lee

Quiescent Power Supply Current

Vee = Min.

10L = 32mA MIL.

VIN = VIH or VIL

10L = 4SmA COM'L.

Vee = Max.
VIN = GND or Vee

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

2570 Ibl 03

POWER SUPPLY CHARACTERISTICS
Symbol
~Iee

leeD

Test Conditlons(l)

Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Curren~4)

Vee = Max.
VIN = 3.4V(3)
Vee = Max.

VIN = Vee

Outputs Open

VIN = GND

Typ.(2)

Max.

Unit

-

0.5

2.0

mA

-

0.15

0.3

Min.

mAl
MHz

One Bit Toggling
50% Duty Cycle
Ie

Total Power Supply Curren~5)

Vee = Max.

VIN = Vee

Outputs Open
Toggle El, E2 or

VIN =GND

-

1.7

4.5

-

2.0

5.5

mA

E3

50% Duty Cycle

VIN = 3.4V

fo= 10MHz

VIN = GND

One Output Toggling
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (V IN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + dlcc DHNT + ICCD (fcP/2 + foNo)
Icc = Quiescent Current
dlcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fo = Output Frequency
No = Number of Outputs at fa
All currents are in milliamps and all frequencies are in megahertz.

6.3

25701b104

3

I

IDT54174FCT138T/AT/CT
FAST CMOS 1·0F·8 DECODER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT138T
Com'l.
Symbol

Parameter

tPLH
tPHL

Propagation Delay
An to On

tPLH
tPHL
tPLH
tPHL

Condltlon(1)

= 50pF
AI. = 500n
CL

Mil.

IDT54174FCT138AT
Com'l.

MlnP) Max. Mln.(2) Max. MlnP) Max.

Com'l.

Mil.

Mln.(2) Max.

Mln.(2) Max.

Mln.(2) Max.

Unit

12.0

1.5

5.8

1.5

7.8

-

-

-

-

ns

1.5

12.5

1.5

5.9

1.5

8.0

-

-

-

-

ns

1.5

12.5

1.5

5.9

1.5

8.0

-

-

-

-

1.5

9.0

1.5

El

Propagation Delay
or E2 to On

1.5

9.0

Propagation Delay
E3 to On

1.5

9.0

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

IDT54174FCT138CT

Mil.

ns
2570 tbl DB

6.3

4

IDT54174FCT138T/AT/CT
FAST CMOS 1-0F-8 DECODER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2570 tbl 09
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

~

}

tsu --40j4--~

PULSE WIDTH

~~....M~

-= ~~V
-

OV

LOW-HIG~U~~

6J

TIMING - - - - - - - 3V
V
INPUT _ _ _ _ _ _,.,~~--+------_ASYNCHRONOUS CONTROL
PRESET - - - - - - , ~--+_--~-------­ - 3V
- - t - - - - - - 1.5V
CLEAR
ETC. - - - - - - - ,
- OV

=t

HIGH-LOW-HIGH
PULSE

_

~ 1.5V
1w

_ _ 1.5V

SYNCHRONOUS CONTROL
CLOCK

:~~~~~ ~tsu
vvJr
J

ETC.

~~....M~

- 3V
-1.5V
-OV

PROPAGATION DELAY

ENABLE

DISABLE
_---3V

---1.5V

SAME PHASE
INPUT TRANSITION

) o - . . . . J ' + - - - - OV

_----_.+-OUTPUT

II

ENABLE AND DISABLE TIMES

OV
3.5V

VOH
-1.5V

VOL

VOL
VOH
3V
OPPOSITE PHASE
INPUT TRANSITION

OV

NOTES
2570 drw 10
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; ZO:5 50Q; tF:5 2.5ns;
tR ~ 2.5ns.

6.3

5

IDT54174FCT138T/AT/CT
FAST CMOS 1-0F-8 DECODER

MIUTARV AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT _ _X_X....-_ FCT
XXXX
Temp. Range
""b:""e-v,"-c-e....
T-yp~e~

x

x

Package

Process
Commercial
MIL-STD-883, Class B

P

D
~------------~SO

E
L

~

____________________

J138T

~138AT

i138CT

154

~------------------------------~174

Plastic DIP
CERDIP
Small Outline IC
CERPACK
Leadless Chip Carrier
1-of-8 Decoder
Fast 1-of-8 Decoder
Super Fast 1-of-8 Decoder
-55°C to + 125°C
O°Cto +70°C
2570 cnv· 09

6.3

6

G

IDT54/74FCT139T
IDT54/74FCT139AT
IDT54/74FCT139CT

FAST CMOS DUAL
1-0F-4 DECODER

Integrated Device Technology, Inc.

FEATURES

DESCRIPTION

• IDT54/74FCT139T equivalent to FASTfM speed
• IDT54174FCT139AT 35% faster than FASTfM
• Equivalent to FASTTM output drive over full temperature
and voltage supply extremes
• IOL = 4BmA (commercial) and 32mA (military)
• CMOS power levels (1 mW typo static)
• TTL input and output level compatible
• Substantially lower input current levels than FASTfM

The IDT54/74FCT139T/AT/CT are dual 1-of-4 decoders
built using advanced CEMOSTM , a dual metal CMOS technology. These devices have two independent decoders, each of
which accept two binary weighted inputs (Ao-A 1) and provide
four mutually exclusive active LOW outputs (00-03). Each
decoder has an active LOW enable (E). When E is HIGH, all
outputs are forced HIGH.

(5~max.)

• Dual 1-of-4 decoder with enable
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-BB3, Class B

FUNCTIONAL BLOCK DIAGRAM

Ea

PIN CONFIGURATIONS
Vee

Ea
Aoa

Ala

AOb

Alb

Aoa
Ala

15

2
3

Eb

P16-1
016-1 14
S016-2 13

AOb

OOa

4

Ola
02a

5

03a
GND

7

10

Olb
02b

8

9

03b

&

E16-1

6

Alb
COb

12
11

2566 cnv' 01

DIP/SOIC/CERPACK
TOP VIEW

INDEX

g

 uil

'I

II

I

I L--I L--I

2 U 20 19
1
18[: AOb

:]5

17[: Alb

:] 6

L20-2

16[: NC

:J 7
:J 8

15[:
14[:

Gab
Glb

9 10 11 12 13
r-t r-t r-t r-t ,...,

,

""""

Cl ()

18

az,8

I

.c

.c

1

0
2566 cnv' 02

LCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
et 990 Integrated Device Technology, Inc.

6.4

JUNE 1990
DS~206/-

I

IDT54174FCT139T/AT/CT FAST
CMOS DUAl1-0F-4 DECODER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE(1)

PIN DESCRIPTION
Pin Names

Description

Inputs

Out Juts

AO,A1

Address Inputs

E

Ao

A1

00

01

02

E

Enable Input (Active LOW)

H

H

H

H

Outputs (Active LOW)

L

X
L
L
H
H

H

00-03

X
L
H
L
H

L

H

H

H

H

L

H

H

H

H

L

H

H

H

H

2566tbl 07

L
L
L

03

L

NOTES:

2566 till 06

1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Commercial

Military

-0.5 to +7.0

-0.5 to +7.0

Unit
V

-0.5 to Vee

-0.5 to Vee

V

Parameter(l)

Conditions

Typ.

Max.

Unit

CIN

Input
Capacitance

VIN = OV

6

10

pF

COUT

Output
Capacitance

VOUT= OV

8

12

pF

Symbol

NOTE:
1. This parameter is measured at characterization but not tested.

TA

Operating
Temperature

oto +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipatior

0.5

0.5

W

lOUT

DC Output
Current

120

120

mA

2566 till 02

NOTES:
2566 till 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vec by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 110 terminals only.

6.4

2

IDT54174FCT139T1AT/CT FAST
CMOS DUAL 1·0F·4 DECODER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V -+ 5%; Military: TA
Symbol

= -55°C to +125°C, Vcc = 5.0V +- 10%

Test Condltlons(1)

Parameter

Min.

Typ,(2)

Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

VIL

Input LOW Level

Guaranteed Logic LOW Level

V

Input HIGH Current

Vee = Max.

VI = 2.7V

5

jlA

VI = 0.5V

-

-

O.S

liH

-

-5

jlA

-

20

jlA

IlL

Input LOW Current

Vee = Max.

Ii

Input HIGH Current

Vee = Max., VI = Vee (Max.)

VIK

Clamp Diode Voltage

Vee = Min., IN = -1SmA

los

Short Circuit Current

Vee = Max.(3), Vo= GND

VOH

Output HIGH Voltage

Vee = Min.
VIN = VIH or VIL

VOL

Output LOW Voltage

VH

Input Hysteresis

lee

Quiescent Power Supply Current

Vee = Min.
VIN = VIH or VIL

Vee = Max.
VIN = GND or Vee

-

-0.7

-1.2

V

-60

-120

-225

mA

10H = -6mA MIL.
10H = -SmA COM'L.

2.4

3.3

-

V

10H = -12mA MIL.
10H = -15mA COM'L.

2.0

3.0

-

V

10L = 32mA MIL.
10L = 4SmA COM'L.

-

0.3

0.5

V

-

200

-

mV

-

0.2

1.5

mA

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

6.4

V

25661bl03

3

IDT54174FCT139T/AT/CT FAST
CMOS DUAL 1·0F·4 DECODER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Tvp.(2)

Max.

-

0.5

2.0

rnA

-

0.15

0.3

mAl
MHz

-

1.7

4.5

rnA

VIN = 3.4V
VIN = GND

-

2.0

5.5

VIN = Vee
VIN =GND

-

3.2

7.5(5)

VIN = 3.4V
VIN = GND

-

3.7

9.5(5)

Test Condltlons(1)

Min.

Sy_mbol

Parameter

~Iee

Quiescent Power Supply Current
TIL Inputs HIGH

Vee = Max.
VIN = 3.4V(3)

IceD

Dynamic Power Supply
Current(4)

Vee = Max.
Outputs Open
One Bit Toggling
50% Duty Cycle

VIN = Vee
VIN = GND

Ie

Total Power Supply Curren~6)

Vee = Max.
Outputs Open
fo= 10MHz

VIN = Vee
VIN =GND

50% Duty Cycle
One Output Toggling
Vee = Max.
Outputs Open
fo= 10MHz
50% Duty Cycle
One Output Toggling
on Each Decoder

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (V IN = 3.4 V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + !iNPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + foNo)
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fa = Output Frequency
No = Number of Outputs at fa
All currents are in milliamps and all frequencies are in megahertz.

Unit

25661b104

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT139AT

IDT54174FCT139CT

Com'l.

Mil.

Com'l.

Mil.

Com'l.

Mil.

Mln.(2) Max.

Min.(2) Max.

Min.(2) Max.

Min.(2) Max.

Min.(2) Max.

Min.(2) Max.

IDT54174FCT139T

Parameter

Description

tPLH
tPHL

Propagation Delay
AoorA1 to On

tPLH
tPHL

Propagation Delay
EtoOn

Condltlon(l)

CL = 50pF
RL = 50

on

1.5

9.0

1.5

12.0

1.5

5.9

1.5

7.8

-

-

-

-

1.5

8.0

1.5

9.0

1.5

5.5

1.5

7.2

-

-

-

-

NOTES:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

Unit

ns
ns
2566tbll 08

6.4

4

IDT54f74FCT139T/AT/CT FAST
CMOS DUAL 1-0F-4 DECODER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
25661b109
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA

INPUT

zzt

j

"""..K....M~

PULSE WIDTH

-= ~~V
-

OV

-

3V

tSU----l'l4--~

TIMING
INPUT _ _ _ _ _ _"

----1
f---,_-+
___
_- - -

1.5V
- OV

LOW-HIG~U~~

ASYNCHRONOUS CONTROL
PRESET - - - - - , ~-~--+---­ - 3V
CLEAR
- - + - - - - - 1.5V
ETC. _______J

-

OV

-

3V

HIGH-LOW-HIGH
PULSE

=t-=

~ 15V

tw

_ _ 1.5V

SYNCHRONOUS CONTROL

CLOCK:~~~~~ ~
vvY
ETC.

J
t su

""-..K....M~

-1.5V
OV

PROPAGATION DELAY

I

ENABLE AND DISABLE TIMES

SAME PHASE
INPUT TRANSITION

OUTPUT

OPPOSITE PHASE
INPUT TRANSITION

NOTES
2566 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate:5 1.0 MHz; ZO:5 son; tF:5 2.5ns;
tR:5 2.5ns.

6.4

5

IDT54n4FCT139T/AT/CT FAST
CMOS DUAL 1·0F-4 DECODER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XX
FCT
XXX X
Temp. Range
Device Type

x

x

PaCkage

Process

y~lank
P
D
~------------~so

L
E
139T
~--------------------~139AT

139CT

54
~----------------------------------~74

6.4

Commercial
MIL·STD-883, Class

B

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Dual 1-of-4 Decoder
Fast Dual 1-of-4 Decoder
Super Fast Dual 1-of-4 Decoder

-55 D C to +125 D C
ODC to +70 DC

2566 cnv' 09

6

(;j

FAST CMOS
a-INPUT MULTIPLEXER

IDT54/74FCT151T/AT/CT
IDT54/74FCT251T/AT/CT

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• IDT54/74FCT151T/251T equivalent to FASTTM speed
and drive
• IDT54174FCT151AT/251AT 25% faster than FASTllI
• IDT54/74FCT151 CT/251 CT 50% faster than FASTru
• Equivalent to FASTTM output drive over full temperature
and voltage supply extremes
• TTL input and output level compatible
- VOH = 3.3V (typ.)
VOL = O.3V (typ.)
• IOL = 48mA (commercial), 32mA (military)
• CMOS power levels (1 mW typo static)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class 8

The IDT54174FCT151T/AT/CTand IDT54/74FCT251TI ATI
CT are high-speed 8-input multiplexers built using advanced
CEMOSTM, a dual metal CMOS technology. They select one
bit of data from up to eight sources under the control of three
select inputs. 80th assertion and negation outputs are
provided.
The IDT54174FCT151T/AT/CThas acommon active-LOW
enable (E) input. When E is LOW, data from one of eight inputs is routed to the complementary outputs according to the
3-bit code applied to the Select (SO-S2) inputs. A common
application of the 'FCT151 is data routing from one of eight
sources.
The IDT54/74FCT251T/AT/CThas a common active-LOW
Output Enable (0 E) input. When OE is LOW, data from one
of eight inputs is routed to the complementary outputs. When
OE is HIGH, both outputs are in the high impedance state.
This feature allows multiplexer expansion by tying several
outputs together.

FUNCTIONAL BLOCK DIAGRAM

"'

.J

17
------' r----i

'\
./

16

)-

15

I

'--

-

F=I

~

14

'------\
,...---I

Z

)

R

13

Z

l.-

I

L

' - 1---4

12

)-

I

L

.J

11

I

L

'--

10

1==1
I

r-

I
I
I
I

I- -

-j

I
I
I
I
I

r-J

L_FCT25~nIY J
S2

S1

So

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1990 Integrated Device Technology, Inc.

E for 151
OE for 251

CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of National SemiconduC1or, Inc.

6.5

2635 drw 03

JUNE 1990
DSC-42121·

1

II

IDT54174FCT151T/AT/CT,IDT54174FCT251T/AT/CT
FAST CMOS 8-INPUT MULTIPLEXER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

INDEX

()

I

Vee

13
15

14

14

Is

13

ki

12

17

11

So

12

2

11
10

3

Z

5

Z

6

*E or OE

7

10

S1

GND

8

9

S2

4

P16-1
D16-1
S016-1
&
E16-1

II

I

2

NC :] 6
Z :] 7

z

U

1

11 :] 4
10 :] 5

S

II II
I
I L-I L-I

I

~~I

3

0

z!s

~.!2

20 19
18[:

L20-2

]8

15

17[:

16

16[:

NC

15[:

17

14[:

SJ

9 10 11 12 13
,...., r"'""1

I

II

r-t ,...., ,......,

I I

I I

II

I

I~ ~ g OJ cJ5
Ci(!)

DlP/SOIC/CERPACK
TOP VIEW

I\;U

2635 drw 01

2635 drw 02

LCC
TOP VIEW

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

*E for 151 only. OE for 251 only.

PIN DESCRIPTION
Pin Names

TA

Operating
Temperature

o to +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

E

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

OE
Z

PT

Power Dissipatior

0.5

0.5

W

lOUT

DC Output
Current

120

120

rnA

10 -17
So - S2

Z

2635tbiOl

FUNCTION TAB LE(2)

NOTES:
263511>103
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +O.5V unless otherwise noted.
2. Input and Vec terminals only.
3. Outputs and 110 terminals only.

CAPACITANCE
Symbol
CIN
COUT

Description
Data Inputs
Selects Inputs
Enable Input (Active LOW)-FCT151
Output Enable Input (Active LOW)-FCT251
Data Output
Inverted Data Output

(TA

Parameter(l)

Inputs
52

= +25°C, f = 1.0MHz)
Conditions

Typ.

Max.

Unit

Input
Capacitance

VIN = OV

6

10

pF

Output
Capacitance

VOUT= OV

8

12

NOTE:
1. This parameter is measured at characterization but not tested.

51

X
X
X
X
L
L
L
L
H
L
H
L
L
H
L
H
H
H
H
H
NOTES:
1. E for 151, OE for 251 .
2. H = HIGH Voltage Level,
High Impedance.

pF

Outputs
So

£10£(1)

Z

L

X
X
L
H
L
H
L
H
L
H

H
H
L
L
L
L
L
L
L
L

L(151)
Z(251)
10
11
12
13
14
15
16
17

H(151)
Z(251)
10
11

12
h
14

Is
16

h
2635tbl02

L = LOW Voltage Level, X = Don't care, Z =

2635tbl04

6.5

2

IDT54174FCT151T/AT/CT,IDT54174FCT251T/AT/CT
FAST CMOS a-INPUT MULTIPLEXER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vce= 5.0V
Symbol

Test Condltlons(1)

Parameter

± 10%

Min.

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

VIL

Input LOW Level

Guaranteed Logic LOW Level

IIH

Input HIGH Current

Vee = Max.

IlL

Input LOW Current

Vee = Max.

VI = 0.5V

-

IOZH

High Impedance Output Current

.vee

Vo= 2.7V

-

Vo= 0.5V

II

Input HIGH Current

Vee = Max., VI = Vee (Max.)

-

VIK

Clamp Diode Voltage

Vee'= Min., IN = -1SmA

-

los

Short Circuit Current

Vee = Max.(3), Vo= GND

VOH

Output HIGH Voltage

=0

VI = 2.7V

Max.

IOZl

Vee = Min.

10H = -6mA MIL.

VIN = VIH or Vil

10H = -SmA COM'L.
10H = -12mA MIL.

TypJ2)

-

Max.

Unit

-

V

O.S

V

5

~A

-5

~A

10

~A

-10
20

~A

-0.7

-1.2

V

-60

-120

-225

mA

2.4

3.3

-

V

2.0

3.0

-

V

-

0.3

0.5

V

-

200

-

mV

-

0.2

1.5

mA

10H = -15mA COM'L.
VOL

Output LOW Voltage

VH

Input Hysteresis

lee

Quiescent Power Supply Current

Vee = Min.

10l = 32mA MIL.

VIN = VIH or Vil

10L = 4SmA COM'L.

Vee = Max.
VIN = GND or Vee

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

2635tbl05

POWER SUPPLY CHARACTERISTICS
Symbol

Test Conditions(1)

Parameter

~Iee

QuiescentPower Supply Current
TTL Inputs HIGH

Vee = Max.
VIN = 3.4V(3)

IceD

Dynamic Power Supply Current<4)

Vee = Max.
Outputs Open
EorOE=GND
One Bit Toggling
50% Duty Cycle

Ie

Total Power Supply Current(5)

VIN = Vee

Typ.(2)

Max.

Unit

-

0.5

2.0

mA

-

0.15

0.25

Min.

Vee = Max.
Outputs Open
fi= 10MHz

VIN = Vee
VIN = GND

-

3.2

6.5

50% Duty Cycle
EorOE=GND
One Input Toggling

VIN = 3.4V
VIN =GND

-

3.5

7.5

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc =5.0V, +25°C ambient.
3. Per TIL driven input (V IN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + .:llcc DHNT + ICCD (fCP/2 + fiNo)
Icc = Quiescent Current
.:llcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
Iceo = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
No = Number of Outputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.5

mAl
MHz

VIN = GND

mA

2635tbl06

3

I

IDT54f74FCT151T/AT/CT,IDT54f74FCT251T/AT/CT
FAST CMOS a-INPUT MULTIPLEXER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE-IDT54/74FCT151T/AT/CT
IDT54f74FCT151 T
Com'l.
Symbol

Parameter

MIl.

IDT54f74FCT151AT
Com'l.

Mil.

IDT54f74FCT151CT
Com'l.

Mil.

Condltlon{1 )

Min.(2)

Max.

Min.(2)

Max.

Min.(2)

Max.

Min.(2)

Max.

Min.(2)

Max.

Min.(2)

Max.

Unit

= 50pF
RL = 500n

1.5

9.0

1.5

10.0

1.5

6.6

1.5

7.4

1.5

5.6

1.5

6.2

ns

tPLH
tPHL

Propagation Delay
SNtol

tPLH
tPHL

Propagation Delay
SNtoZ

1.5

10.5

1.5

11.5

1.5

6.8

1.5

7.6

1.5

5.8

1.5

6.5

ns

tPLH
tPHL

Propagation Delay
Etol

1.5

7.0

1.5

7.5

1.5

5.6

1.5

6.3

1.5

4.8

1.5

5.4

ns

tPLH
tPHL

Propagation Delay
'EtoZ

1.5

9.5

1.5

11.0

1.5

5.8

1.5

6.6

1.5

5.0

1.5

5.7

ns

tPLH
tPHL

Propagation Delay
INtol

1.5

6.5

1.5

7.5

1.5

5.2

1.5

5.8

1.5

4.4

1.5

4.9

ns

tPLH
tPHL

Propagation Delay
INtoZ

1.5

7.5

1.5

9.0

1.5

5.5

1.5

6.1

1.5

4.7

1.5

5.2

ns

CL

2635tbl07

SWITCHING CHARACTERISTICS OVER OPERATING RANGE-IDT54/74FCT251T/AT/CT
IDT54/74FCT251T
Com'l.
Symbol

Parameter

MIl.

IDT54f74FCT251AT
Com'l.

Mil.

IDT54f74FCT251 CT
Com'l.

Mil.

Cond itlon(1)

Min.(2)

Max.

Min.(2)

Max.

Min.(2)

Max.

Min.(2)

Max.

Min.<2)

Max.

Min.(2)

Max.

Unit

= 50pF
RL = 500n

1.5

9.0

1.5

9.5

1.5

6.6

1.5

7.4

1.5

5.6

1.5

6.2

ns

1.5

11.0

1.5

14.0

1.5

6.8

1.5

7.6

1.5

5.8

1.5

6.5

ns

tPLH
tPHL

Propagation Delay
SNtol

tPLH
tPHL

Propagation Delay
SNtoZ

tPLH
tPHL

Propagation Delay

1.5

7.0

1.5

8.0

1.5

5.2

1.5

5.8

1.5

4.4

1.5

4.9

ns

tPLH
tPHL

Propagation Delay
INtoZ

1.5

7.0

1.5

8.0

1.5

5.5

1.5

6.1

1.5

4.7

1.5

5.2

ns

tPZH
tPZL

Output Enable Time
OEtoZ

1.5

9.0

1.5

10.0

1.5

6.7

1.5

7.4

1.5

5.7

1.5

6.3

ns

tPHZ
tPLZ

Output Disable Time
OEtoZ

1.5

7.5

1.5

8.5

1.5

6.0

1.5

6.4

1.5

5.0

1.5

5.4

ns

tPZH
tPZL

Output Enable Time
OEtoZ

1.5

9.0

1.5

10.0

1.5

6.7

1.5

7.6

1.5

5.7

1.5

6.5

ns

tPHZ
tPLZ

Output Disable Time
OEtoZ

1.5

7.0

1.5

7.0

1.5

6.0

1.5

6.3

1.5

5.0

1.5

5.2

ns

INtol

CL

NOTES:

2635tbiOB

1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

6.5

4

IDT54174FCT151T/AT/CT,IDT54174FCT251T/AT/CT
FAST CMOS a·INPUT MULTIPLEXER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2635 till 09
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to lOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

XX{

PULSE WIDTH

-= ~~V

j
tsu ---4'f4--~

"'-..-....K~ -

TIMING
INPUT

OV

LOW-HIG~~~~

- 3V
_ 6JV

ASYNCHRONOUS CONTROL
PRESET - - - -......
CLEAR
ETC.
SYNCHRONOUS CONTROL
CLOCK

:~~~~~ vvY
j
~tsu
ETC.

-

--+------

"'-..-....K~

3V
1.5V
OV

=t

HIGH-LOW-HIGH
PULSE

~'5V
t

w

_ _ 1.5V

- 3V
-1.5V
- OV

PROPAGATION DELAY

•

ENABLE AND DISABLE TIMES
ENABLE

DISABLE
3V

3V
SAME PHASE
INPUT TRANSITION

OUTPUT

3.5V

VOH
-1.5V

VOL

VOL
OUTPUT
NORMALLY
HIGH

OPPOSITE PHASE
INPUT TRANSITION
OV

VOH
SWITCH
OPEN
OV

NOTES
2635 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; lo ~ son; tF ~ 2.Sns;
tA ~ 2.Sns.

6.5

5

I

IDT54174FCT151T/AT/CT,IDT54174FCT251T/AT/CT
FAST CMOS 8-INPUT MULTIPLEXER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT =-_X;".;;X..,;,.-_ FCT
XXXX
Temp. Range
Device Type

x

x

Package

Process

y~lank
P
D
'----------1

SO
L

E
151T
251T
,151AT

~----------------------~251AT

151CT
251CT
~

__________________________~154
174

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
a-Input Multiplexer
a-Input Multiplexer (3-state)
Fast a-Input Multiplexer
Fast a-Input Multiplexer (3-state)
Super Fast 8-lnput Multiplexer
Super Fast a-Input Multiplexer (3-state)
-55°C to + 125°C
O°Cto +70°C
2635 drw 09

6.5

6

G®

IDT54174FCT157T/AT/CT
IDT54174FCT257TIAT/CT

FAST CMOS
QUAD 2-INPUT
MULTIPLEXER

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• IDT54/74FCT157T/257T equivalent to FASTTM speed
and drive
• IDT54174FCT157AT/257AT 25% faster than FASTTM
• IDT54174FCT157CT/257CT 50% faster than FASTTM
• TIL input and output level compatible
- VOH = 3.3V (typ.)
- VOL = O.3V (typ.)
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1 mW typo static)
• Product available in Radiation Tolerant and Radiation
Enhanced Versions
• Military product compliant to MIL-STD-883, Class Band
DESC listed

The IDT54/74FCT157T/AT/CT and IDT54174FCT257TI
AT/CT are high-speed quad 2-input multiplexers built using
advanced CEMOSTM, a dual metal CMOS technology. Four
bits of data from two sources can be selected using the
common select input. The four buffered outputs present the
selected data in the true (non-inverting) form.
The IDT54/74FCT157T/AT/CT has a common, activeLOW, enable input. When the enable input is not active, all
four outputs are held LOW. Acommon application of 'FCT157T
is to move data from two different groups of registers to a
common bus. Another application is as a function generator.
The 'FCT157T can generate any four of the 16 different
functions of two variables with one variable common.
The IDT54/74FCT257T/AT/CT has a common Output
Enable (OE) input. When OE is HIGH, all outputs are switched
to a high-impedance state allowing the outputs to interface
directly with bus-oriented systems.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

S
Vee

S

E orOE"

lOA

I1A

loe
11e
Ze

ZA
lOB
11 B -1m ---+-t-+-t-+--I----L.~

ZB-ZO

11B

100

ZB

110
ZD

GND

lOB -100 ---+~+-!-+--I---I...,.,

DIP/SOIC/CERPACK
TOP VIEW

11A ----t--t-i-+----L.~

ZA

I I

lOA

I I

r--------------~ I
257 Only :L OE
______________

INDEX

:

~

2537 drw02

11A

"

] 4

NC

] 5
] 6

lOB

] 7

ZA

I1B

L...J L..JI

IL..JL...J

loe

H[

he

l'

L20-2

16 [

NC

15 [
14 [
] 8
9 10 11 1213

Ze

"'-

".,,,.,,.....,

LCC
TOP VIEW
CEMOS is a trademark 01 Integrated Device Technology, Inc.
FAST is a registered trademark 01 National Semiconductor Co.

"

MILITARY AND COMMERCIAL TEMPERATURE RANGES
<1:>1990 Integraled Device Technology, Inc.

6.6

"

3 2 I I 20 19
18 [

100

/

2537 drwOl

E for FCT157, OE for FCT257.
JUNE 1990
DSC-4221/·

1

IDT54174FCT157T/AT/CT, IDT54174FCT257T/AT/CT
FAST CMOS QUAD 2·INPUT MULTIPLEXER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE(1)

PIN DESCRIPTION
Description

Pin Names

Output ZN

Inputs

lOA-laD

Source 0 Data Inputs

ElOE

S

10

h

157

257

I1A-110

Source 1 Data In-,",,-uts

H

X

X

X

L

Z

E

Enable Input (Active LOW)-FCT157T

L

H

X

L

L

L

OE

Output Enable (Active LOW)-FCT257T

L

H

X

H

H

H

S

Select Input

L

L

L

X

L

L

ZA-Zo

Outputs

L

L

H

X

H

H

NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance

2537 till 05

CAPACITANCE (TA = +25°C, f = 1.0MHz)

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
to GND
VTERM(3) Terminal Voltage
with Respect
to GND
TA
Operating
Temperature
TBIAS
Temperature
Under Bias
TSTG
Storage
Temperature
Power Dissipation
PT
lOUT
DC Output Current

2537 till 06

Commercial

Military

-0.5 to +7.0

-0.5 to +7.0

Unit

Symbol

V

-0.5 to Vee

-0.5 to Vee

V

o to +70

-55 to +125

°C

-55 to +125

-65 to + 135

°C

-55 to +125

-65 to +150

°C

0.5
120

0.5
120

mA

Parameter(1)

CIN

Input Capacitance

COUT

Output Capacitance

Conditions

= OV
Your = OV
VIN

NOTE:
1. This parameter is guaranteed but not tested.

Typ. Max.

Unit

6

10

pF

8

12

pF

2537 tbl 02

W

NOTES:
2537 till 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability. No terminal voltage may
exceed Vcc by +O.5V unless otherwise noted.
2. Inputs and Vee terminals only.
3. Outputs and 1/0 terminals only.

6.6

2

IDT54174FCT157T/AT/CT, IDT54174FCT257T/AT/CT
FAST CMOS QUAD 2·INPUT MULTIPLEXER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vce = 5.0V ± 5%; Military: TA = ·55°C to +125°C, Vcc = 5.0V ± 10%
Min.

Typ.(2)

Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

V

Vil

Input LOW Level

Guaranteed Logic LOW Level

IiH

Input HIGH Current

Vee = Max.

-

-

Symbol

Test Condltlons(l)

Parameter

VI = 2.7V

lil

Input LOW Current

Vee = Max.

VI = 0.5V

10ZH

High Impedance Output

Vee = Max.

Vo = 2.7V

10Zl

Current

Vo = 0.5V

II

Input HIGH Current

Vee = Max., VI = Vee (Max.)

VIK

Clamp Diode Voltage

Vee = Min., IN = -1SmA

los

Short Circuit Current

Vee = Max.(3), Vo

VOH

Output HIGH Voltage

Vee = Min.
VIN

= GND
IOH = -SmA MIL.

= VIH or Vil

IOH
IOH
IOH

VOL

Output LOW Voltage

Vee = Min.
VIN

VH

Input Hysteresis

lee

Quiescent Power Supply
Current

= -SmA COM'L.
= -12mA MIL.
= -15mA COM'L.

IOl = 32mA MIL.

= VIH or Vil

O.S

V

5

JlA

-5

JlA

-

10

JlA

-

-10
20

JlA

-0.7

-1.2

V

-so

-120

-225

mA

2.4

3.3

-

V

2.0

3.0

-

V

-

0.3

0.5

V

-

200

-

mV

-

0.2

1.5

mA

IOl = 4SmA COM'L.

Vee = Max.
VIN = GND or Vee

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

25371b103

I

6.6

3

I

IDT54n4FCT157T/ATlCT, IDT54n4FCT257T/AT/CT
FAST CMOS QUAD 2·INPUT MULTIPLEXER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol

Parameter

Min.

Typ.(2)

Max.

Unit

-

0.5

2.0

rnA

VIN = Vee
VIN = GND

-

0.15

0.25

rnA/MHz

Vee = Max.
Outputs Open
fi= 10MHz
50% Duty Cycle
E orOE = GND
One Bit Toggling

VIN = Vee
VIN= GND

-

1.7

4.0

rnA

VIN = 3.4V
VIN= GND

-

2.0

5.0

VIN = Vee
Outputs Open
fi= 2.5MHz
50% Duty Cycle
EorOE=GND
Four Bits Toggling

VIN = Vee
VIN = GND

-

1.7

4.0(5)

VIN = 3.4V
VIN = GND

-

2.7

8.0(5)

Test CondltIons(1)

~Icc

Quiescent Power Supply Current
TTL Inputs HIGH

Vee = Max.
VIN = 3.4V(3)

ICCD

Dynamic Power Supply Current(4)

Vee = Max.
Outputs Open
E orOE = GND
One Bit Toggling
50% Duty Cycle

Ie

Total Power Supply Current(6)

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vee or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + Alec DHNT + ICCD (fcp/2 + fiNi)
lec = Quiescent Current
Alcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.6

25371b104

4

IDT54f74FCT157T/AT/CT,IDT54f74FCT257T/AT/CT
FAST CMOS QUAD 2·INPUT MULTIPLEXER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE - FCT157T/AT/CT
54rT4FCT157T
Com'l.
Symbol

Parameter

tPLH
tPHL

Propagation Delay
INtoZN

tPLH
tPHL
tPLH
tPHL

54rT4FCT157AT

Mil.

Com'l.

Mil.

Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Mln.(2) Max.

= 50 pF
= soon

54rT 4FCT157CT
Com'l.
Min.(2)

Mil.

Max. Min.(2) Max. Unit

1.5

6.0

1.5

7.0

1.5

5.0

1.5

5.8

1.5

4.3

1.5

5.0

ns

Propagation Delay
Eto ZN

1.5

10.5

1.5

12.0

1.5

6.0

1.5

7.4

1.5

4.8

1.5

5.9

ns

Propagation Delay
StoZN

1.5

10.5

1.5

12.0

1.5

7.0

1.5

8.1

1.5

5.2

1.5

6.0

ns

CL
RL

SWITCHING CHARACTERISTICS OVER OPERATING RANGE - FCT257T/AT/CT
54rT4FCT257T
Com'l.
Symbol

Parameter

tPLH
tPHL

Propagation Delay
INtoZN

tPLH
tPHL

54rT4FCT257AT
Com'l.

MIl.

Mil.

54rT4FCT257CT
Com'l.

Cond ition(1) Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Min.(2) Max. Min.(2)
CL = 50 pF
RL = soon

Mil.

Max. Min.(2) Max. Unit

1.5

6.0

1.5

7.0

1.5

5.0

1.5

5.8

1.5

4.3

1.5

5.0

ns

Propagation Delay
StoZN

1.5

10.5

1.5

12.0

1.5

7.0

1.5

8.1

1.5

5.2

1.5

6.0

ns

tPZH
tPZL

Output Enable
Time

1.5

8.5

1.5

10.0

1.5

7.0

1.5

8.0

1.5

6.0

1.5

6.8

ns

tPHZ
tPLZ

Output Disable
Time

1.5

6.0

1.5

8.0

1.5

5.5

1.5

5.8

1.5

5.0

1.5

5.3

ns

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

2537 till 07

I

6.6

5

IDT54n4FCT157T/AT/CT, IDT54n4FCT257T/AT/CT
FAST CMOS QUAD 2-INPUT MULTIPLEXER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION

TEST CIRCUITS FOR ALL OUTPUTS

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
;:5::7:-: co
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

PULSE WIDTH

-= ~~V

l

""-..x.~~ -

OV

tsu-;---..r

TIMING
INPUT _ _ _ _ _ _-'

LOWHIG~~~S~

- 3V
_

6gV

ASYNCHRONOUS CONTROL
PRESET - - - -.....
CLEAR
ETC.

-

--+------

=t-

HIGH-LOW-HIGH
PULSE

3V
1.5V
OV

~ 15V
IW

_ _ 1.5V

SYNCHRONOUS CONTROL

CLOCK:~~~~~ vvY
l
~tsu
ETC.

- 3V
-1.5V
"'------.-.. - OV

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE
3V

3V

SAME PHASE
IN PUT TRANSITION

OV
3.5V

OUTPUT

VOH
-1.5V

VOL

VOL

OUTPUT SWITCH
NORMALLY OPEN
HIGH

OPPOSITE PHASE
INPUT TRANSITION

VOH

OV

NOTES
2537 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-H I GH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ 50Q; tF ~ 2.5n5;
tR ~ 2.5ns.

6.6

6

IDT54f74FCT157T/AT/CT,IDT54f74FCT257T/AT/CT
FAST CMOS QUAD 2-INPUT MULTIPLEXER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XX

FCT

Temperature
Range

X

X

X

Device
Type

Package

Process

~~Iank
~------------~

P
D

Commercial
MIL-STD-883, Class B

E

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

157T
257T
157AT
257AT
157CT
257CT

Quad 2-lnput Multiplexer
Quad 2-lnput Multiplexer (3-state)
Fast Quad 2-lnput Multiplexer
Fast Quad 2-lnput Multiplexer (3-state)
Super Fast Quad 2-lnput Multiplexer
Super Fast Quad 2-lnput Multiplexer (3-state)

SO

L

~--------------------------------11 54

174

-55°C to + 125°C
O°C to +70°C

2537 drw 03

I

6.6

7

t;)®

IDT54/74FCT161T
IDT54174FCT161AT
IDT54174FCT163T
IDT54174FCT163AT

FAST CMOS
SYNCHRONOUS
PRESETTABLE
BINARY COUNTERS

Integrated Device Technology. Inc.

FEATURES:

DESCRIPTION:

• IDT54/74FCT161TI163T equivalent to FASTTM speed
• IDT54174FCT161AT/163AT 35% faster than FASTTM
• Equivalent to FASTTM output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial), 32mA (military)
• CMOS power levels (1 mW typo static)
• True TTL input and output levels
• Substantially lower input current levels than FASTTM

The IDT54174FCT161T/163T and IDT54174FCT161ATI
163AT are high-speed synchronous modul0-16 binary
counters built using advanced CEMOSTM, a dual metal CMOS
technology. They are synchronously presettable for
programmable dividers and have two types
application in
of count enable inputs plus a terminal count output for
versatility in forming synchronous multi-stage counters. The
IDT54/74FCT161T and IDT54/74FCT161AT have
asynchronous Master Reset inputs that override all other
inputs and force the outputs LOW. The IDT54/74FCT163T
and IDT54/74FCT163AT have Synchronous Reset inputs
that override counting and parallel loading and allow the
outputs to be simultaneously reset on the rising edge of the
clock.

(5~max.)

• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
Po

PE~----~~--------------~__r---------~~------~r-------------.
CEP~=====F==~lt~------+---+-~------~--H-------+-H-------'
CET----~-r~------------r_--r_+_------_+~+_------~+_------r_----~_,

-

: 163
:ONLY

---,

TC

CP

DETAIL
A

DETAIL
A

DETAIL
A

00
2611 drw01

CEMOS is a trademark of Integrated Device Techology. Inc.
FAST is a registered trademark of National Semiconductor Co.

MILITARY AND. COMMERCIAL TEMPERATURE RANGES
--+--or+-""'If"""'7Ir'''''~-= ~~V
ETC.

~tsu

-

OV

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

_---3V
---1.5V
l---'-I-----OV

SAME PHASE
INPUT TRANSITION

3.5V
OUTPUT

VOL
VOH

SWITCH
OPEN

OPPOSITE PHASE
INPUT TRANSITION

OV
NOTES
2611 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate:s; 1.0 MHz; Zo :s; son; tF S 2.5ns;
tR S 2.5ns.

6.7

6

I

IDT54174FCT161T/AT,IDT54174FCT163T/AT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

X

---Temperature
Range

FCT

xxxx

X

X

Device
Type

Package

Process

~~Iank
P
D

~--------------~

L

SO
E

1611
163T
161AT
163AT

'- - - - - - - - - - - - - - - - - - - - - - -___~174
54

Commercial
MIL-STD-883, Class B
PI3.$tic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC
CERPACK
Synchronous Binary Counter
with Asynchronous Master Reset
Synchronous Binary Counter
with Synchronous Reset
Fast Synchronous Binary Counter
with Asynchronous Master Reset
Fast Synchronous Binary Counter
with Synchronous Reset
-55°C to + 125°C
0° to +70°C
2611 drw 03

6.7

7

G®

IDT54174FCT191T
IDT54174FCT191 AT

FAST CMOS
UP/DOWN BINARY
COUNTER

Integrated Device Technology. Inc.

FEATURES:

DESCRIPTION:

• IDT54/74FCT191T equivalent to FASTfM speed
• IDT54174FCT191AT 35% faster than FAST
• Equivalent to FASTfM output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial), 32mA (military)
• CMOS power levels (1 mW typo static)
• True TTL input and output levels
• Substantially lower input current levels than FAST
(5JlA max.)
• JEDEC standard pinout for DIP, LCC and SOIC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT191T and IDT54/74FCT191AT are
reversible modu10-16 binary counters, featuring synchronous
counting and asynchronous presetting and are built using
advanced CEMOSTM, a dual metal CMOS technology. The
preset feature allows the IDT54/74FCT191T and IDT54/
74FCT191AT to be used in programmable dividers. The
count enable input, terminal count output and ripple clock
output make possible a variety of methods of implementing
multiusage counters. In the counting modes, state changes
are initiated by the rising edge of the clock.

FUNCTIONAL BLOCK DIAGRAM
P3

Po

CP UID

1 1

\/\~

90

(
~

I

I

I

I

Jl J

1(1

I

I

I

T

9

I

J CLOCK K

Y: PRESET

1

TC

%9

1 I~
1
A

I
I

6
L--

1
00

1

1

I
I

It
I

1-.

Y: PRESET

CLEAR

P-

6
L--

1

a

1

1

U

.~

J CLOCK K

J CLOCK K

a

~

~I

-c PRESET

CLEAR ::>-

O

RC

I

1-.

'1

I

T

I~

1

I

A

I

J CLOCK K
-c PRESET

CL~R ::>-

a

L--

a

1

p-

CL~R

a

~

1

2615 drw 01

CEMOS is a trademark of Integrated Device Techology. Inc.
FAST is a registered trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
1I:l1990 Integrated Device Technology, Inc.

6.8

JUNE 1990
DSC-4207/·

1

IDT54174FCT191T/AT
FAST CMOS UPIDOWN BINARY COUNTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
INDEX
Vcc
Po
CP
RC
TC
PL
P2
P3

P1
01
00
CE
DID
02
03
GND

L...J L...J

3 2

00

]

CE
NC
DID
02

4

] 5
] 6
] 7
] 8

I I

Y

L-J L...J

20 19

L20-2

18 [

CP

17 [

RC
NC
TC
PL

16 [
15 [
14 [

9 10 11 1213
2615 drw02

8 00MN
zza.a.
(!)

DIP/CERPACKISOIC
TOP VIEW

LCC
TOP VIEW

RC FUNCTION TABLE(2)

PIN DESCRIPTION
Pin Names

I I

Description

Outputs

Inputs
CP

TC(1)

RC

L

LJ

H

-U-

Parallel Data Inputs

H

X

X

H

PL

Asynchronous Parallel Load Input (Active LOW)

X

X

L

H

UID

UplDown Count Control Input

00-3

Flip-Flop Outputs

CE

Count Enable Input (Active LOW)

CP

Clock Pulse Input (Active Rising Edge)

PO-3

RC

Ripple Clock Output (Active LOW)

TC

Terminal Count Output (Active HIGH)

CE

2615 tbl 06

MODE SELECT FUNCTION TABLE(2)
Inputs
2615 tbl 05

PL

CE

UlD

CP

H

L

L

./

Count Up

H

L

H

./

Count Down

L

X

X

X

Preset (Asynchronous)

H

H

X

X

No Change (Hold)

Mode

NOTES:
2615tbl07
1. TC is generated internally.
2. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don't Care, h
LOW-to-HIGH clock transition.

6_8

2

IDT54174FCT191T/AT
FAST CMOS UP/DOWN BINARY COUNTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)

CAPACITANCE

Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage
with Respect
toGND
Operating
TA
Temperature
TSIAS
Temperature
Under Bias

Commercial

Military

-0.5 to +7.0

-0.5 to +7.0

TSTG
PT
lOUT

Unit
V

-0.5 to Vee

-0.5 to Vee

V

o to +70

-55 to +125

°C

-55 to +125

-65 to +135

°C

Storage
Temperature
Power Dissipation

-55 to +125

-65 to +150

°C

0.5

0.5

W

DC Output Current

120

120

mA

(TA = +25°C, f = 1.0MHz)

Parameter(1)

Conditions Typ.

CIN

Input Capacitance

VIN= OV

COUT

Output Capacitance VOUT

Symbol

= OV

Max.

Unit

6

10

pF

8

12

pF

NOTE:
26151b102
1. This parameter is guaranteed at characterization but not tested.

NOTES:
26151b101
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vce by +O.5V unless otherwise noted.
2. Inputs and Vee terminals.
3. Outputs and 110 terminals.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, vcc = 5.0V
Symbol

Test Conditions(1)

Parameter

Typ.(2)

-

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

IIH

Input HIGH Current

Vee

ilL

Input LOW Current

II

Input HIGH Current

VIK

Clamp Diode Voltage

los

Short Circuit Current

VOH

Output HIGH Voltage

= Max.

VI

= 2.7V

VI = 0.5V

= Max., VI = Vee (Max.)
Vee = Min., IN = -1SmA
Vee = MaxP), Va = GND
Vee = Min.
VIN = VIH or VIL
Vee

IOH
IOH

= -6mA
= -SmA

MIL.
COM'L.

IOH = -12mA MIL.
IOH = -15mA COM'L.
VOL

Output LOW Voltage

VH

Input Hysteresis

lee

Quiescent Power
Supply Current

Vee = Max.
VIN = VIH or VIL

IOL
IOL

Vee = Max.
VIN = GND or Vee

= 32m A
= 4SmA

MIL.
COM'L.

± 10%

Min.

-

Max.

V

O.S

V

5

JlA

-5

-

20

JlA

-0.7

-1.2

V

-225

mA

-60

-120

2.4

3.3

-

V

2.0

3.0

-

V

-

0.3

0.5

V

-

200

-

mV

-

0.2

1.5

mA

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

6.8

Unit

-

26151b103

3

II

IDT54174FCT191T/AT
FAST CMOS UPIDOWN BINARY COUNTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol

Parameter

Typ.(2)

Max.

Unit

-

0.5

2.0

mA

= Vee
= GND

-

0.15

0.25

mAl
MHz

VIN
VIN

= Vee
= GND

-

1.0

2.8

mA

VIN
VIN

= 3.4V
= GND

-

1.2

3.8

VIN = Vee
VIN = GND

-

3.2

6.5(5)

VIN = 3.4V
VIN = GND

-

4.2

10.5(5)

Test Condltions(l)

Min.

.1 lee

Quiescent Power Supply Current
TTL Inputs HIGH

Vee = Max.
VIN = 3.4 V(3)

leeD

Dynamic Power Supply Current(4)

Vee = Max., Outputs Open
Preset Mode
PL = CE = U/D = CP = GND
One Bit Toggling
50% Duty Cycle

VIN
VIN

Ie

Total Power Supply Currenl(6)

Vee = Max., Outputs Open
Preset Mode
PL = CE = U/D = CP = GND
One Bit Toggling
at fi = 5MHz
50% Dut~ Cycle
Vee = Max., Outputs Open
Preset Mode
PL = CE = U/D = CP = GND
Four Bits Toggling
at fi = 5MHz
50% Duty Cycle

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vee or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic =laulEscENT +IINPUTS + IDYNAMIC
Ic = Icc + .1lccDHNT + ICCD(fcp/2 + f;Ni)
Icc = Quiescent Current
.1lcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fep = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6B

2615 tbl 04

4

IDT54174FCT191T/AT
FAST CMOS UPIDOWN BINARY COUNTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT191 AT

IDT54/74FCT191T
Com'1.
Symbol

Parameter

Com'1.

Mil.

Mil.

Condition(1)

MlnP>

Max.

MinP>

Max.

Min.(2)

= 50pF
= 500n

2.5

12.0

1.5

16.0

2.5

7.8

1.5

10.5

ns

Max. MinP> Max.

Unit

tPLH
tPHL

Propagation Delay
CP to an

tPLH
tPHL

Propagation Delay
CP toTC

3.0

14.0

2.0

16.0

3.0

11.8

2.0

12.2

ns

tPLH
tPHL

Propagation Delay
CP to RC

2.5

8.5

1.5

12.5

2.5

8.5

1.5

10.0

ns

tPLH
tPHL

Propagation Delay
CE to RC

2.0

8.0

2.0

8.5

2.0

7.2

2.0

8.0

ns

tPLH
tPHL

Propagation Delay
DID to RC

4.0

20.0

4.0

22.5

4.0

13.0

4.0

14.7

ns

tPLH
tPHL

Propagation Delay
DID to TC

3.0

11.0

3.0

13.0

3.0

7.2

3.0

8.5

ns

tPLH
tPHL

Propagation Delay
Pn to an

2.0

14.0

1.5

16.0

2.0

9.1

1.5

10.4

ns

tPLH
tPHL

Propagation Delay
PL to an

3.0

13.0

3.0

14.0

3.0

8.5

3.0

9.1

ns

tsu

Set-up Time, HIGH or LOW
Pn to PL

5.0

-

6.0

-

4.0

-

5.0

-

ns

tH

Hold Time, HIGH or LOW
Pn to PL

1.5

-

1.5

-

1.5

-

1.5

-

ns

tsu

Set-up Time LOW
CE to CP

10.0

-

10.5

-

9.0

-

9.5

-

ns

tH

Hold Time LOW
CE to CP

0

-

0

-

0

-

0

-

ns

tsu

Set-up Time, HIGH or LOW
DID to CP

12.0

-

12.0

-

10.0

-

10.0

-

ns

0

-

0

-

0

-

0

-

ns

tH

CL
RL

Hold Time, HIGH or LOW

Ufo to CP
tw

PL Pulse Width LOW

6.0

-

8.5

-

8.0

-

ns

Clock Pulse Width HIGH or LOW

5.0

-

7.0

-

5.5

tw

4.0(3)

-

6.0

tREM

Recovery Time PL to CP

6.0

-

7.5

-

5.0

-

6.5

-

ns

NOTES:

ns
2615 tbl 08

1. See test circuit and waveform.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.

6.8

5

I

IDT54174FCT191T/AT
FAST CMOS UP/DOWN BINARY COUNTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vee

SWITCH POSITION
0---4 7.0V

soon

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

26151b109
DEFINITIONS:
CL = Lc:::d c:::p:::dtnlicc: includes jig and PIQue capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

PULSE WIDTH

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

Z&t

-= ?~V

j

~...x....x~ -

OV

-

3V

-

OV

-

3V

-

OV

-

3V

-

OV

tsu~0j4--~

TIMING
INPUT

LOWHIG~UL~~

- - t - - - - - - 1.5V

=}

ASYNCHRONOUS CONTROL
PRESET - - - - ,
CLEAR
ETC. - - - - - '

HIGH-LaW-HIGH
PULSE

- - f - - - - - - - 1.5V

~ 1.5V

'~

- - .-1.5V

SYNCHRONOUS CONTROL
CLOCK

:~~~~~
vvYETC.~tsU
J

~...-..-x-......

1.5V

ENABLE AND DISABLE TIMES

PROPAGATION DELAY

ENABLE

DISABLE

__- - - 3 V
SAME PHASE
INPUT TRANSITION
3.5V

OUTPUT

VOL
VOH

SWITCH
OPEN

OPPOSITE PHASE
INPUT TRANSITION

OV
'----J----OV

NOTES
2615 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate $; 1.0 MHz; Zo $; SOQ; tF $; 2.Sns;
tR $ 2.Sns.

6.8

6

IDT54174FCT191T/AT
FAST CMOS UP/DOWN BINARY COUNTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES·

ORDERING INFORMATION
lOT

x

FCT XXXX

Temperature
Range

Device
Type

x

x

Package

Process

~~Iank
P

o

~------------~ E
SO
L

191T
191 AT
~

________________________________

6.8

~

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Small Outline IC
Leadless Chip Carrier
Up/Down Binary Counter
Fast Up/Down Binary Counter

54

-55°C to + 125°C

74

0° to +70°C

2615 drw 03

7

~®

IDT54/74FCT193T
IDT54174FCT193AT

FAST CMOS
UP/DOWN
BINARY COUNTERS

Integrated Device Technology. Inc.

FEATURES:

DESCRIPTION:

• IDT54/74FCT193T equivalent to FASTI"M speed
• IDT54174FCT193AT 35% faster than FASTTM
• Equivalent to FASTTM output drive overfull temperature
and voltage supply extremes
• IOL = 48mA (commercial), 32mA (military)
• CMOS power levels (1 mW typo static)
• TTL input and output level compatible
• Substantially lower input current levels than FASTTM
(5jJA max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT193T and IDT54174FCT193AT are upl
down modul0-16 binary counters built using advanced
CEMOSTM, a dual metal CMOS technology. Separate countup and count-down clocks are used and, in either counting
mode, the circuits operate synchronously. The outputs change
state synchronously with the LOW-to-H IGH transitions on the
clock inputs. Separate terminal count-up and terminal countdown outputs are provided that are used as the clocks for
subsequent stages without extra logic, thus simplifying
multistage counter designs. Individual preset inputs allow the
circuit to be used as a programmable counter. Both the
Parallel Load (PL) and the Master Reset (MR) inputs
asynchronously override the clocks.

FUNCTIONAL BLOCK DIAGRAM
PI

Po

-<{)
cPu

CPo

(CAR Ry)

.~

~

TCu
-1

rl>

.1

TCo

?

Co

a
y
MR

I
1

J

CP

K

--f(BOR ROW)

r:0

~~

~

P3

P2

So

a

b-

~

L--

?
00

©

f

I
I
J

1

K

CP

a
Y

So

a

y
I

~
-

Co

P-

L--

CP

K

a

?
02

01

I

I
I

I

K

CP

So

a

y

J

CD

)'

?

©
b-

L--

~

I

J

CD

a
~

So b-

a

L--

1
03

2628 drw 01

CEMOS is a 1rademark of Integrated Device Technology. Inc.
FAST is a trademark of National Semicondudor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
e1990 Integrated Device Technology. Inc.

6.9

APRIL 1990
DSC-4218f-

1

IDT54174FCT193T/AT
FAST CMOS UP/DOWN BINARY COUNTERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

<5

INDEX
."

3

P1

Vee

01

Po

00

MR
TCo
TCu
PL
P2
P3

CPO
CPU

02
03
GND

00 ]

~~~

] 5
] 6

CPU

] 7

]

2

I

I

'1"

4

CPo
NC

02

a:

L..JL...JIIL..JL..J

"

20 19
18 [
17 [

L20-2

16 [
15 [

8

14 [

MR
TCo
NC
TCu
PL

,!!.,~~~;.;

"

8~~~~

2628 drw 02

C!)

DIP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW

FUNCTION TABLE(1)

DEFINITION OF FUNCTIONAL TERMS
Pin Names

MR

PL

CPu

CPo

Mode

Count Up Clock Input (Active Rising Edge)

H

X

X

X

Reset (Asyn.)

CPo

Count Down Clock Input (Active Rising Edge)

L

L

X

X

Preset (Asyn.)

MR

Asynchronous Master Reset (Active HIGH)

L

H

H

H

No Change

PL

Asynchronous Parallel Load Input (Active LOW)

L

H

i

H

Count Up

Pn

Parallel Data Inputs

L

H

H

i

Count Down

an

Flip-flop Outputs

TCD

Terminal Count Down (Borrow) Output (Active
LOW)

TCu

Terminal Count Up (Carry) Output (Active LOW)

CPu

Description

NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
t = LOW-to-HIGH Clock Transition

2628 till 06

2628 tbl 05

ABSOLUTE MAXIMUM RATINGS(1)

CAPACITANCE (TA = +25°C, f = 100M Hz)

Commercial

Military

Unit

Symbol

Parameter(1)

Conditions

Max.

Unit

VTERM(2) Terminal Voltage
with Respect
toGND

-0.5 to +7.0

-0.5 to +7.0

V

CIN

Input
Capacitance

VIN = OV

6

10

pF

GoUT

8

12

pF

-0.5 to Vee

-0.5 to Vee

V

Output
Capacitance

VOUT = OV

VTERM(3) Terminal Voltage
with Respect
toGND

Symbol

Rating

TA

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

Typ.

NOTE:
2628 tbl 02
1. This parameter is measured at characterization but not tested.

NOTE:
2628tbl01
1. Stresses greater than those listed under ABSOLUTE MAXI MUM RATI NGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals.
3. Output and 110 terminals.

6.9

2

II

IDT54174FCT193T/AT
FAST CMOS UP/DOWN BINARY COUNTERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125° C , Vcc = 5.0V

Symbol

Test Condltlons(l)

Parameter

± 10%

Min.

Typ.(2)

Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

V

VIL

Input LOW Level

Guaranteed Logic LOW Level

V

Input HIGH Current

Vec

VI

IiL

Input LOW Current

Vee

VI

II

Input HIGH Current

-

O.S

IiH

VIK

Clamp Diode Voltage

-0.7

-1.2

V

los

Short Circuh Current

-so

-120

-225

mA

VOH

Output HIGH Voltage

2.4

3.3

-

V

10H = -12mA MIL.

2.0

3.0

-

V

= -15mA COM'L.
10L = 32m A MIL.
10L = 4SmA COM'L.

-

0.3

0.5

V

-

200

-

mV

-

0.2

1.5

mA

= Max.
= Max.
Vee = Max., VI = Vee (Max.)
Vee = Min., IN = -1SmA
Vee = Max.P), Vo = GND
Vee = Min.
VIN = VIH or VIL

= 2.7V
= 0.5V

10H

= -SmA MIL.

5

~A

·5

~A

20

~A

10H = -SmA COM'L.
10H

VOL

Output LOW Voltage

Vee
VIN

VH

Input Hysteresis

lee

Quiescent Power
Supply Current

= Min.
= VIH or VIL

Vee = Max.
VIN = GND or Vee

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

6.9

2628 tbl 03

3

IDT54f74FCT193T/AT
FAST CMOS UP/DOWN BINARY COUNTERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol

Typ.(2)

Max.

Unit

-

0.5

2.0

mA

VIN = Vee
VIN =GND

-

0.15

0.25

mAl
MHz

VIN
VIN

= Vee
= GND

-

1.7

4.0

mA

VIN
VIN

= 3.4V
= GND

-

2.0

5.0

VIN
VIN

= Vee
= GND

-

3.2

6.5(5)

VIN
VIN

= 3.4V
= GND

-

4.2

10.5(5)

Test Condltlons(1)

Parameter

~Icc

Quiescent Power Supply
Current TTL Inputs HIGH

Vee = Max.
VIN = 3.4V(3)

leeo

Dynamic Power
Supply Current(4)

Vee = Max.
Outputs Open
Preset Mode
PL = MR = CPu = CPo = GND
One Bit Toggling
50% Duty Cycle

Ic

Total Power Supply
Current(6)

Vee = Max.
Outputs Open
Preset Mode
PL = MR = CPu = CPo = GND
One Bit Toggling
at fi = 10MHz
50% Duty Cycle
Vee = Max.
Outputs Open
Preset Mode
PL = MR = CPu = CPo
Four Bits Toggling
at fi = 5MHz
50% Duty Cycle

Min.

= GND

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V): all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + Alcc DHNT + ICCD (fcp/2 + fi Ni)
Icc = Quiescent Current
Alcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

2629 tbl 04

I

I
I

6.9

4

IDT54174FCT193T/ AT
FAST CMOS UP/DOWN BINARY COUNTERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT193T

Symbol

Parameter

tPLH
tPHL

Propagation Delay
CPu or CPo to TCu or TCo

tPLH
tPHL

Condltlon(1)
CL = SOpF
RL = soon

Com'l.
Mln.(2) Max.

IDT54174FCT193AT

Mil.
Mln.(2) Max.

Com'l.
Mln.(2) Max.

Mil.
Mln.(2) Max.

Unit

2.0

10.0

2.0

10.S

2.0

6.S

2.0

6.9

ns

Propagation Delay
CPu or CPo to an

2.0

13.S

2.0

14.0

2.0

8.8

2.0

9.1

ns

tPLH
tPHL

Propagation Delay
Pnto an

2.0

1S.S

2.0

16.S

2.0

10.1

2.0

10.8

ns

tPLH
tPHL

Propagation Delay
PL to an

2.0

14.0

2.0

13.5

2.0

8.8

2.0

9.1

ns

tPHL

Propagation Delay
MR toOn

3.0

15.5

3.0

16.0

3.0

10.1

3.0

10.4

ns

tPLH

Propagation Delay
MR toTCu

3.0

14.5

3.0

15.0

3.0

9.4

3.0

9.8

ns

tPHL

Propagation Delay
MR toTCo

3.0

15.5

3.0

16.0

3.0

10.1

3.0

10.4

ns

tPLH
tPHL

Propagation Delay
PL to TCu or TCo

3.0

16.5

3.0

18.5

3.0

10.8

3.0

12.0

ns

tPLH
tPHL

Propagation Delay
Pn to TCu or TCo

3.0

15.5

3.0

16.5

3.0

10.1

3.0

10.8

ns

tsu

Set-up Time, HIGH or LOW
Pnto PL

5.0

-

6.0

-

4.0

-

5.0

-

ns

tH

Hold Time, HIGH or LOW
Pnto PL

2.0

-

2.0

-

1.S

-

1.5

-

ns

6.5

tw

PL Pulse Width LOW

6.0

CPu or CPo Pulse Width
HIGH or LOW
CPu or CPo Pulse Width LOW
(Change of Direction)

5.0

-

7.5

tw

7.0

-

5.0
4.0(3)

-

6.0

-

ns

10.0

-

12.0

-

8.0

-

10.0

-

ns

6.0

tw

ns

tw

MR Pulse Width HIGH

6.0

5.0

-

ns

6.0

8.0

-

-

Recovery Time
PL to CPu or CPo

-

5.0

tREM

5.0

-

7.0

-

ns

tREM

Recovery Time
MR to CPu or CPo

4.0

-

4.5

-

3.0

-

3.5

-

ns

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.

2628 tbl 07

6.9

5

IDT54174FCT193T/AT
FAST CMOS UP/DOWN BINARY COUNTERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION

TEST CIRCUITS FOR ALL OUTPUTS

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

262811:>108
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

PULSE WIDTH

-= ~~V

1

"'-~~~ -

OV

tsu----I'I4--~

TIMING
INPUT _ _ _ _ _ _,

- 3V
_ 6~V

LOW-HIG~Ji1~
HIGH-LOW-HIGH

ASYNCHRONOUS CONTROL
PRESET - - - - CLEAR
ETC.

-

3V

-

OV

-

3V

- - + - - - - - - 1.5V

=t-

~ 1.5V
tw

_ _ 1.5V

PULSE

SYNCHRONOUS CONTROL

CLOCK:~~~~~ vvJr
J
~SU
ETC.

-1.5V
--..------ - OV

t

PROPAGATION DELAY

•

ENABLE AND DISABLE TIMES
ENABLE

SAME PHASE
INPUT TRANSITION

DISABLE

) -___r + - - - - OV
3.5V

OUTPUT

VOL
VOH

SWITCH
OPEN

OPPOSITE PHASE
IN PUT TRANSITION

OV

' - - - - - ' - - - - OV

NOTES
2628 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate S 1.0 MHz; Zo S 50n; tF:::; 2.5ns;
tR S 2.5ns.

6.9

6

IDT54174FCT193T!AT
FAST CMOS UP/DOWN BINARY COUNTERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

X

----

Temperature
Range

FCT

xxxx

X

X

Device
Type

Package

Process

~~Iank
P
D
'---------~ SO
L
E
193T
193AT

'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-1 54

74

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
UplDown Binary Counter
Fast Up/Down Binary Counter
-55°C to +125°C
0° to +70°C
2628 drw 03

6.9

7

IDT54174FCT240T/AT/CT
IDT54174FCT241 TI AT/CT
IDT54/74FCT244T/AT/CT
IDT54174FCT540T/AT/CT
IDT54174FCT541T/AT/CT

FAST CMOS OCTAL
BUFFER/LINE DRIVER

G

Integrated Device Technology,lnc.

FEATURES:

DESCRIPTION:

• IDT54/74FCT240T/241T/244T/540T/541T equivalent to
FAS"fTM speed and drive

The IDT octal buffer/line drivers are built using advanced
CEMOSTM, a dual metal CMOS technology. The IDT541
74FCT240T/AT/CT, IDT54/74FCT241T/AT/CT and IDT541
74FCT244T/AT/CT are designed to be employed as memory
and address drivers, clock drivers and bus-oriented transmitter/receivers which provide improved board density.
The IDT54/74FCT540T/AT/CT and IDT54174FCT541TI
AT/CTare similar in function to the IDT54/74FCT240T/AT/CT
and IDT54174FCT244T/AT/CT, respectively, except that the
inputs and outputs are on opposite sides of the package. This
pinout arrangement makes these devices especially useful as
output ports for microprocessors and as backplane drivers,
allowing ease of layout and greater board density.

• IDT54174FCT240AT/241AT/244AT/540AT/541AT 25%
faster than FASlTM
• IDT54174FCT240CT/241CT/244CT/540CT/541CT up to
55% faster than FASlTM
• True TTL input and output compatible
- VOH = 3.3V (typ.)
- VOL = O.3V (typ.)
• IOL = 64mA (commercial) and 48mA (military)
• CMOS power levels (1 mW typo static)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Meets or exceeds JEDEC Standard 18 specifications

FUNCTIONAL BLOCK DIAGRAMS
OEA

.-241--,Only

OEA

I

OEe

I

OEe

OEA

OEs"

OAo

OAo

OAo

00

00"

OBo

OBo

OBo

OBo

01

01"

OAl

OAl

OAl

OAl

02

02"

OBl

OBl

OBl

OBl -

03

03"

OA2

OA2

OA2

OM

04

04·

OB2

OB2

OB2

OB2

05

05·

OA3

OA3

OA3

OA3

06

06·

OB3

OB3

OB3

OB3

07

07·

OAo

IDT54/74FCT240T

IDT54/74FCT241T/244T

·OEsfor241T,OEefor244T
2565

cnv' 01

2565

II

IDT54/74FCT540T/541T

"Logic diagram shown for 'FCT540T.
'FCT541 T is the non-inverting option.

cnv' 02

2565

cnv' 03

CEMOS is a trademark of Integrated Device TechnOlogy, Inc.
FAST is a trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
(1:)1990 Integrated Device Technology, Inc.

6.10

JUNE 1990
DSC-4211/·

1

IDT54174FCT240/241/244/540/541 TI AT/CT
FAST CMOS OCTAL BUFFER/UNE DRIVER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
IDT54/74FCT240T
o~<()

INDEX

Vee

OEA
DAo

2

19

OEs

OBo

3

18

OAo

DAl

4

17

DBo

DAl

:J 4

OBl

5

16

OAl

OBl

:] 5

I I I I I
II
II
I
L-..IL-IIIL-...4L--1

DBl

DA2 :] 6

14

OA2

0132

8

13

DB2

DA3

9

12

OA3

10

11

DB3

6

7

DA3
OB3

2 ~ 20 19
1
18[:

3

15

DM
OB2

GND

P20-1
D20-1
S020-2
&
E20-1

CD

,~ Cl'~ g ,~

OAo

17[: DBo
16[:

L20-2

:J 7
:J 8

OAl

15[:

DB1

14[:

OA2

9 10 11 12 13
~~~"""r--1
I I I I I II II
I

,03

~ a3 ,:{ ~
O(!}ClOCl

DIP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW
2565cnv' 07

2565cnv' 04

IDT54/74FCT241T/244T

DAo

2

19

OBo
DA1

3

18

4

DBo

DA1

OB1

5

OAl

OBl

DA3

17
P20-1
16
D20-1
6 S020-2 15
&
14
7
E20-1
13
8

OB3

9

12

10

11

DM
OB2

GND

·CD

INDEX

Vee

OEA

al Cl
~ ~ >8 ~
o

OEs'

I

OAo

32U2019

DB1

DA2

OA2

OB2

DB2

DA3

:J
:J
:J
:J
:J

I

I

I:

II

II

1

4

I

18 [:

OAo

17 [: DBo

5

16 [:

L20-2

6

OAl

7

DB1

8

OA2

OA3

9 10 11
I
I I
ro
"I I"I "I

DB3

M

CJ

0

DIP/SOIC/CERPACK
TOP VIEW

I

"I

I

Cla3:{d:!

~ClOCl
LCC
TOP VIEW

'OEs for 241T, DEs for 244T
2565cnv' 08

2565cnv' 05

IDT54/74FCT540T/541T
INDEX

Vee

OEA

OJ

2

19

D1

3

18

0:1'

D2

4

01"

D2

OJ

5

P20-1 17
020-1 16
S020-2 15

oz

OJ

:J 4
:J 5

~~LJ~~
1

18 [:

at

17 [: 01"

OJ'

D4

:J 6

14

01"

Ds

:] 7

15 [:

OJ"

8

13

0::

Os

:J 8

01"

9

12

0;"

14 [:
9 10 11 12 13

10

11

Of

D4

6

Ds

7

Os
D7
GND

OEB

US () al
c581o~1o

&
E20-1

16 [:

at

nnnnn
o~aaa
(!)

DIP/SOIC/CERPACK
TOP VIEW
'OEs for 241T, OEs for 244T

L20-2

LCC
TOP VIEW
2565cnv' 09

2565cnv' 06

6.10

2

IDT54174FCT240/241/244/540/541 TI AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE

PIN DESCRIPTION
Pin Names
OEA, OEs

Description
3-State Output Enable Inputs (Active LOW)

OEA

OEs

Inputs(1)
OES(2)

D

240

241

244

540

OEs(1)

3-State Output Enable Input (Active HIGH)

L

L

H

L

H

L

L

H

L

Dxx

Inputs

L

L

H

H

L

H

H

L

H

Oxx

Outputs

H

H

L

X

Z

Z

Z

Z

NOTES:
1. OEB for 241 only

2565 tbl 04

TA
TSIAS
TSTG

Operating
Temperature
Temperature
Under Bias
Storage
Temperature

NOTE:
1. H = High Voltage Level
X = Don't Care
L = Low Voltage Level
Z = High Impedance
2. OEB for 241 only.

541

Z
2565tb105

CAPACITANCE (TA = +25°C, f = 1.0MHz)

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
VTERM(2) Terminal Voltage -0.5 to +7.0
with Respect to
GND
VTERM(3) Terminal Voltage
-0.5 to Vee
with Respect to
GND

OutputS<1)

Military

Unit

-0.5 to +7.0

V

-0.5 to Vee

V

o to +70

-55 to +125

°C

-55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

Parameter<1)
Symbol
CIN
Input
Capacitance
GoUT

Output
Capacitance

Conditions

Typ.

Max.

Unit

VIN = OV

6

10

pF

VOUT = OV

8

12

pF

NOTE:
2565tbl02
1. This parameter is measured at characterization but not tested.

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output
Current

120

120

mA

NOTES:
2565tb101
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 1/0 terminals only.

6.10

II

3

IDT54f74FCT240/241/244/540/541 TI A TlCT

FAST CMOS OCTAL BUFFER/UNE DRIVER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C,Vcc = 5.0V ± 5%; Military: TA
Symbol

Parameter

= -55°C to +125°C, vcc = 5.0V ± 10%

Test Conditions

(1)

Min.

Typ. (2) Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

V

Vil

Input LOW Level

Guaranteed Logic LOW Level

V

InputHIGH Current

Vee = Max.

VI = 2.7V

-

0.8

IIH

5

~

III

Input LOW Current

Vee = Max.

VI = 0.5V

-

-5

~

IOZH

H:gh Impodance Output Cum;nt

Vee = Max.

Vo= 2.7V

-

-

10

~

-

-10

~

-

20

~

10Zl

Vo = O.SV

II

Input HIGH Current

Vee = Max., VI = Vee (Max.)

VIK

Clamp Diode Voltage

Vee = Min., N = -18mA

los

Short Circuit Current

Vee.= Max.(3), Vo '" GND

VOH

Output HIGH Voltage

Vee"; Min.
VIN = VIH or V,l

VOL

Output LOW Voltage

VH

Input Hysteresis

Icc

Quiescent Power Supply Current

Vee= Min.
VIN = VIH or Vil

~.7

-1.2

V

-60

-120

-225

mA

10H = -6mA MIL.
10H = -8mA COM'L.

2.4

3.3

-

V

10H = -12mA MIL.
10H = -15mA COM'L.

2.0

3.0

-

V

10l = 48mA MIL.
10l = 64mA COM'L.

-

0.3

0.55

V

-

200

-

mV

-

0.2

1.5

Vee = Max., V,N = GND orVee

NOTES:

mA
2565 tbl 03

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

6.10

4

IDT54174FCT240/241/244/540/541 TIAT/CT
FAST CMOS OCTAL BUFFER/UNE DRIVER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol
~Iee

IceD

Test Condltlons(1)

Parameter
Quiescent Power Supply Current

TIL Inputs HIGH
Dynamic Power Supply Curren~4)

Vee = Max.
VIN = 3.4V(3)
Vee = Max.

VIN = Vee

Outputs Open
OEA = OEs = GND or

VIN =GND

Tvp.(2)

Max.

Unit

-

0.5

2.0

rnA

-

0.15

0.25

Min.

mAl
MHz

OEA = GND, OEs = Vee
One Input Toggling
50% Duty Cycle
Ic

Total Power Supply Curren~6)

Vee = Max.

VIN = Vee

Outputs Open

VIN= GND

-

1.7

4.0

-

2.0

5.0

-

3.2

6.5(5)

-

5.2

14.5(5)

rnA

fi = 10MHz
50% Duty Cycle

OEA = OEs = GND or
OEA = GND, OEs = Vee

VIN = 3.4V
VIN =GND

One Bit Toggling
Vee = Max.

VIN = Vee

Outputs Open

VIN =GND

fi = 2.5MHz
50% Duty Cycle

OEA = OEs = GND or
OEA = GND, OEs = Vee

VIN = 3.4V
VIN = GND

Eight Bits Toggling
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25 c C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fiNi)
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (V IN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.10

2565tb106

I

5

IDT54174FCT240/241/244/540/541 TI AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT240T
54/74 FCT240T
Com'l.
Symbol

tPLH
tPHL

Parameter
Propa~ation

Delay

ON toON

Condition(l)

= 50pF
RL = 500n
CL

54/74FCT240CT

54/74FCT240AT

Mil.

Com'l.

Mil.

Com'l.

Mil.

Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Min.(2) Max. Min.(2) Max.

Unit

1.5

8.0

1.5

9.0

1.5

4.8

1.5

5.1

1.5

4.3

1.5

4.7

ns

tPZH
tPZL

Output Enable Time

1.5

10.0

1.5

10.5

1.5

6.2

1.5

6.5

1.5

5.0

1.5

5.7

ns

tPHZ
tPLZ

Output Disable Time

1.5

9.5

1.5

10.0

1.5

5.6

1.5

5.9

1.5

4.5

1.5

4.6

ns
2565 tbl 07

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT241T AND FCT244T
54/74 FCT241 T1244 T
Com'l.
Symbol

Parameter

tPLH
tPHL

Propagation Delay
ON to ON

tPZH
tpZL
tPHZ
tPLZ

Conditlon(1)

CL = 50pF

Mil.

54/74FCT241 AT/244AT
Com'l.

Mil.

54/74FCT241 CT/244CT
Com'l.

Mil.

Mln.(2) Max. Mln.(2) Max. iMln.(2) Max. iMln.(2) Max. Min.(2) Max. Mln.(2) Max.

Unit

1.5

6.5

1.5

7.0

1.5

4.8

1.5

5.1

1.5

4.1

1.5

4.6

ns

Output Enable Time

1.5

8.0

1.5

8.5

1.5

6.2

1.5

6.5

1.5

5.8

1.5

6.5

ns

Output Disable Time

1.5

7.0

1.5

7.5

1.5

5.6

1.5

5.9

1.5

5.2

1.5

5.7

RL = 500n

ns
2565 tbl 08

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT540T AND FCT541T
54174FCT540T/5411
Com'l.
Symbol

tPLH
tPHL

Parameter

Conditlon(l)

Propagation Delay
ON to ON

CL = 50pF

IDT54/74FCT540T

RL = 500n

Mil.

54174FCT540AT/541 AT
Com'l.

Mil.

5417 4FCT540CT/541 CT
Com'l.

Mil.

Min.<2) Max. MlnP) Max. Min.<2) Max. Min.(2) Max. Min.<2) Max. Min.(2) Max.

Unit

1.5

8.5

1.5

9.5

1.5

4.8

1.5

5.1

1.5

4.3

1.5

4.7

ns

tPLH
tPHL

Propagation Delay
DN to ON
IDT54/74FCT541 T

1.5

8.0

1.5

9.0

1.5

4.8

1.5

5.1

1.5

4.1

1.5

4.6

ns

tPZH
tPZL

Output Enable Time

1.5

10.0

1.5

10.5

1.5

6.2

1.5

6.5

1.5

5.8

1.5

6.5

ns

tPHZ
tPLZ

Output Disable Time

1.5

9.5

1.5

10.0

1.5

5.6

1.5

5.9

1.5

5.2

1.5

5.7

ns

NOTES:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

2565tbl09

6.10

6

IOT54174FCT240/241/244/540/541 T/ AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2565tbl10
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

Z&t

PULSE WIDTH

-= ~~V

1

""-~...K~ -

OV

tsU~'i'4---~

6J

TIMING
INPUT _ _ _ _ _ _"

- 3V
V
_

LOWHIG~~~~=t ~'5V

ASYNCHRONOUS CONTROL
PRESET - - - -....
CLEAH
ETC.
SYNCHRONOUS CONTROL

P~~~f~

CLOCK ENABLE
ETC.

zzt=

-

3V

-

OV

--+--------

1
"""-..-.....K~

tsu

HIGH-LOW-HIGH

1.5V

Iw

_ _ 1.SV

PULSE

- 3V
-1.5V
- OV

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

r---~-----3V

SAME PHASE
INPUT TRANSITION

l - - - ' -+-----

OV
3.SV

OUTPUT

VOL
VOH

SWITCH
OPEN

OPPOSITE PHASE
INPUT TRANSITION

OV

' - - - - - ' - - - - - OV

NOTES
2565 drw 10
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate:5 1.0 MHz; Zo :5 son; tF :5 2.Sns;
tR:5 2.Sns.

6.10

7

I DT54f74FCT240/241/244/540/541 TI A TICT
FAST CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT~---=-:.XX=-_ FCT -;:::--..,..X_XX-::;X:--_
Temp. Range
Device Type

x

x

Package

Process

y~lank
P
D
~------------~SO

L
E
240T
241T
244T
540T
541T
240AT
241 AT
~---------------------;244AT

540AT
541AT
240CT
241CT
244CT
540CT
541CT
54

~----------------------------------~74

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Inverting Octal Buffer/Line Driver
Non-Inverting Octal Buffer/Line Driver
Non-Inverting Octal Buffer/Line Driver
Inverting Octal Buffer/Line Driver
Non-Inverting Octal Buffer/Line Driver
Fast Inverting Octal Buffer/Line Driver
Fast Non-Inverting Octal Buffer/Line Driver
Fast Non-Inverting Octal BufferlLine Driver
Fast Inverting Octal Buffer/Line Driver
Fast Non-Inverting Octal Buffer/Line Driver
Super Fast Inverting Octal BufferlLine Driver
Super Fast Non-Inverting Octal Buffer/Line Driver
Super Fast Non-Inverting Octal Buffer/Line Driver
Super Fast Inverting Octal Buffer/Line Driver
Super Fast Non-Inverting Octal Buffer/Line Driver
-55°C to + 125°C
O°C to +70°C

2565 cnv' 15

6.10

8

G®
Integrated Device Technology, Inc.

IDT54114FCT245T/AT/CT
IDT54114FCT640T/AT/CT
IDT54114FCT645T/AT/CT

FAST CMOS OCTAL
BIDIRECTIONAL
TRANSCEIVERS

FEATURES:

DESCRIPTION:

• IDT54/74FCT245T/640T/645T equivalent to FASTI'M
speed and drive
• IDT54174FCT245AT/640AT/645AT 25% faster than
FASTfM
• IDT54174FCT245CT/640CT/645CT 40% faster than
FASTfM
• True TTL input and output compatibility
- VOH = 3.3V (typ.)
- VOL = O.3V (typ.)
• IOL = 64mA (commercial) and 48mA (military)
• CMOS power levels (2.5mW typical static)
• Direction control and over-riding 3-state control
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class Band
DESC listed
• Meets or exceeds JEDEC Standard 18 specifications

The IDT octal bidirectional transceivers are built using
advanced CEMOSTM, a dual metal CMOS technology. The
IDT54/74FCT245T/AT/CT, IDT54/74FCT640T/AT/CT and
IDT54/74FCT645T/AT/CT are designed for asynchronous
two-way communication between data buses. The transmitl
receive (TiR) input determines the direction of data flow
through the bidirectional transceiver. Transmit (active HIGH)
enables data from A ports to B ports, and receive (active LOW)
from B ports to A ports. The output enable (OE) input, when
HIGH, disables both A and B ports by placing them in HIGH Z
condition.
The IDT54/74FCT245T/AT/CT and IDT54!74FCT645TI
AT/CT transceivers have non-inverting outputs. The IOT541
74FCT640T/AT/CT has inverting outputs.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

~--~--~----+-OE

Ao
80
Al

T/R

Vee

Ao
Al
A2
A3
A4
As
A6

OE
80
81
82
83
84
85
86
87

A7

81

GND

A2

II

DIP/SOIC/CERPACK
TOP VIEW

A3
83

~ ~I~
81w
1->0

INDEX

~

L...JL-JIIL...JL.....J

A2
A3
A4
As
A6

As
85
A6
86

]
]
]
]
]

4
5
6
7
8

3 2 : : 20 19
18
"1
17
L20-2
16
15
14
9 1011 1213
,....,,....,..,,....,rI

~~dl~C8

A7

[
[
[
[
[

80
81
82
83
84
2539 drw 02

(!)
2539 drw 01

LCC
TOP VIEW

FCT245T, 645T are non-inverting options.
FCT640T is the inverting option.
CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
1C1990 Integrated Device Technology. Inc.

6.11

JUNE 1990
DSC-420lI-

1

IDT54174FCT245T/AT/CT, 640T/AT/CT, 645T/AT/CT
FAST CMOS OCTAL BIDIRECTIONAL TRANSCEIVERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABlE(2)

PIN DESCRIPTION
Pin Names

Inputs

Description
OE

TiR"

L

L

Outputs

OE

Output Enable Input (Active LOW)

T/R

TransmitlReceive Input

Ao-A7

Side A Inputs or 3-State Outputs

L

H

Bus A Data to Bus B(l)

Bo-B7

Side B Inputs or 3-State Outputs

H

X

High ZState

2539 tbl05

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
TBIAS
Temperature
Under Bias
TSTG
Storage
Temperature
PT
Power Dissipation
lOUT
DC Output Current

Bus B Data to Bus A(l)

NOTE:
1. 640 is inverting from input to output.
2. H;;;: HIGH Vc!t:!go Leve!
L = LOW Voltage Level
X =Don't Care

(TA = +25°C, f = 1.0MHz)
Parameter(l)
Symbol
Conditions Typ. Max.
Input Capacitance VIN = OV
6
10
CIN
1/0 Capacitance
8
CliO
VOUT= OV
12

2539 tbl06

CAPACITANCE

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

o to +70

-55 to +125

°C

-55 to +125

-65 to +135

°C

-55 to +125

-65 to + 150

°C

0.5
120

0.5
120

W
mA

Unit
pF
pF

NOTE:
2539
1. This parameter is measured at characterization but not tested.

NOTES:
2539 tbl at
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability. No terminal voltage may
exceed Vce by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Outputs and 1/0 terminals only.

6.11

2

tbl 02

IDT54n4FCT245T/AT/CT, 640T/AT/CT, 645T/AT/CT
FAST CMOS OCTAL BIDIRECTIONAL TRANSCEIVERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, vcc = 5.0V ± 5%; Military: TA
Symbol
VIH
Vll
IIH

Input HIGH Level
Input LOW Level
Input HIGH Current

Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
Except 110 Pins
Vee = Max
VI

ill

iI
VIK

= -55°C to +125°C, Vcc = 5.0V ± 10%

Test Condltlons(1)

Parameter

= 2.7V

110 Pins
Except 1/0 Pins

Input LOW Current

Vee = Max

Input HIGH Current
Clamp Diode Voltage

110 Pins
VI = 0.5V
Vee = Max., VI = Vee (Max.)
Vee = Min., IN= -18mA

= MaxPl,

los

Short Circuit Current

Vee

VOH

Output HIGH Voltage

Vee = Min.
VIN = VIH or Vll

VOL

Output LOW Voltage

VH
Icc

Input Hysteresis
Quiescent Power Supply
Current

Vo

= GND
= -6mA Mil.
= -SmA Com'l.
= -12mA Mil.
= -15mA Com'l.
10l = 48mA Mil.
10l = 64mA Com'l.

10H
10H
10H
10H

Vee = Min.
VIN = VIH or Vll
Vcc

= Max., VIN = Vee or GND

Min.
2.0

Typ.(2)

Max.

-

Unit

-

V
V

-

-0.7

20
-1.2

JlA
V

-60

-120

-225

mA

2.4

3.3

-

2.0

3.0

-

-

0.3

0.55

-

200
0.5

1.5

-

0.8
5

JlA

15
-5

JlA

-15

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vec = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

V

V

-

mV
mA
2539 till 03

I

6.11

3

IDT54174FCT245T/AT/CT, 640T/AT/CT, 645T/AT/CT
FAST CMOS OCTAL BIDIRECTIONAL TRANSCEIVERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol

Parameter

Test Condltlons(1)

Typ.(2)

Max.

Unit

-

0.5

2.0

mA

0.15

0.25

Min.

~Iee

Quiescent Power Supply Current
TIL Inputs HIGH

Vee = Max.
VIN = 3.4v(3)

IceD

Dynamic Power Supply Current(4)

Vee = Max.
Outputs Open
OE = Tiff = GND
One Input Toggling
50% Duty Cycle

VIN = Vee
VIN= GND

-

Vee = Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
OE = T/R =GND
One Bit Toggling

VIN = Vee
VIN =GND

-

2.0

4.0

VIN = 3.4V
VIN =GND

-

2.3

5.0

Vee = Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
OE = T/R =GND
Eight Bits Toggling

VIN = Vee
VIN =GND

-

3.5

6.5(5)

VIN = 3.4V
VIN = GND

-

5.5

14.5(5)

Total Power Supply Current(6)

Ie

mN
MHz

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25 c C ambient.
3. Per TTL driven input (VIN = 3.4V): all other inputs at Vee or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IOUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Ice DHNT + IceD (fcp/2 + fiNi)
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH Duty Cycle for TTL Inputs High
NT Number of TTL Inputs at DH
ICCD Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

mA

2539 Ibl 04

=
=
=

6.11

4

IDT54174FCT245T/AT/CT, 640T/AT/CT, 645T1AT/CT
FAST CMOS OCTAL BIDIRECTIONAL TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT245T/AT/CT

Symbol

Parameter

tPLH
tPHL

Propagation Delay
A to B, Bto A

tPZH
tPZL

54174 FCT245T
54174 FCT245AT
54174FCT245CT
Com'l.
Com'l.
Mil.
Mil.
Com'l.
Mil.
Conditions(l) Mln.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
CL = 50 pF
RL = 500n

1.5

7.0

1.5

7.5

1.5

4.6

1.5

4.9

1.5

4.1

1.5

4.5

ns

Output Enable Time
OE to A or B

1.5

9.5

1.5

10.0

1.5

6.2

1.5

6.5

1.5

5.8

1.5

6.2

ns

tPHZ
tPLZ

Output Disable Time
OE to A or B

1.5

7.5

1.5

10.0

1.5

5.0

1.5

6.0

1.5

4.8

1.5

5.2

ns

tPZH
tPZL

Output Enable Time
T/R to A or B(3)

1.5

9.5

1.5

10.0

1.5

6.2

1.5

6.5

1.5

5.8

1.5

6.2

ns

tPHZ
tPLZ

Output Disable Time
T/R to A or B(3)

1.5

7.5

1.5

10.0

1.5

5.0

1.5

6.0

1.5

4.8

1.5

5.2

ns
2534 tbl07

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT640T/AT/CT
54174FCT640T
Symbol

Parameter

tPLH
tPHL

Propagation Delay
Ato B, BtoA

tPZH
tPZL

5417 4FCT640CT

54174FCT640AT

Com'l.
Com'l.
Com'l.
Mil.
Mil.
Mil.
Conditions(l) Min.(2) Max. Mln.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Mln.(2) Max. Unit
CL = 50 pF
RL = 500n

2.0

7.0

2.0

8.0

1.5

5.0

1.5

5.3

1.5

4.4

1.5

4.7

ns

Output Enable Time
OE to A or B

2.0

13.0

2.0

16.0

1.5

6.2

1.5

6.5

1.5

5.8

1.5

6.2

ns

tPHZ
tPLZ

Output Disable Time
OE to A or B

2.0

10.0

2.0

12.0

1.5

5.0

1.5

6.0

1.5

4.8

1.5

5.2

ns

tPZH
tPZL

Output Enable Time
T/R to A or B(3)

2.0

13.0

2.0

16.0

1.5

6.2

1.5

6.5

1.5

5.8

1.5

6.2

ns

tPHZ
tPLZ

Output Disable Time
T/R to A or B(3)

2.0

10.0

2.0

12.0

1.5

5.0

1.5

6.0

1.5

4.8

1.5

5.2

ns
2534 tbl08

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT645T/AT/CT
54174 FCT645T
Symbol

Parameter

tPLH
tPHL

Propagation Delay
Ato B, BtoA

tPZH
tPZL

5417 4FCT645AT

54174 FCT645 CT

Com'l.
Com'l.
Com'l.
Mil.
Mil.
Mil.
Conditions(l) Min.(2) Max. Min.'2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit

= 50 pF
= 500n

1.5

9.5

1.5

11.0

1.5

4.6

1.5

4.9

1.5

4.1

1.5

4.5

ns

Output Enable Time
OE to A or B

1.5

11.0

1.5

12.0

1.5

6.2

1.5

6.5

1.5

5.8

1.5

6.2

ns

tPHZ
tPLZ

Output Disable Time
OE to A or B

1.5

12.0

1.5

13.0

1.5

5.0

1.5

6.0

1.5

4.8

1.5

5.2

ns

tPZH
tPZL

Output Enable Time
T/R to A or B(3)

1.5

11.0

1.5

12.0

1.5

6.2

1.5

6.5

1.5

5.8

1.5

6.2

ns

tPHZ
tPLZ

Output Disable Time
T/R to A or B(3)

1.5

12.0

1.5

13.0

1.5

5.0

1.5

6.0

1.5

4.8

1.5

5.2

ns

CL
RL

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.

2534 tbl09

6.11

5

I

I

IDT54n4FCT245T/AT/CT, 640T/AT/CT, 645T/AT/CT
FAST CMOS OCTAL BIDIRECTIONAL TRANSCEIVERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
o--e 7.0V

Vec

soon

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2539 !bllO
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt·

PULSE WIDTH

-= ~~V

1

.-.,.___....-~ -

OV

tsu ---I0j4--~

TIMING
INPUT

- 3V
V
_

LOWHIG~UL&~=t- ~'5V

-

3V

HIGH-LOW-HIGH

-

OV

6J

ASYNCHRONOUS CONTROL
PRESET - - - -.....
CLEAR
ETC. - - - - ,

- - t - - - - - - 1.SV

lw

_ _ 1.SV

PULSE

SYNCHRONOUS CONTROL
CLOCK

:~~~~~ vvir
~tsu
J

ETC.

.-.,.---....-~

- 3V
-1.SV
- OV

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

3V
3V
SAME PHASE
INPUT TRANSITION

OUTPUT

OV
3.SV

VOH
-1.SV

VOL

VOL
VOH
SWITCH
OPEN

OPPOSITE PHASE
INPUT TRANSITION

OV
OV

NOTES
2539 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ 50n; tF ~ 2.5ns;
tR ~ 2.5ns.

6.11

6

IDT54174FCT245T/AT/CT, 640T/AT/CT, 645T/AT/CT
FAST CMOS OCTAL BIDIRECTIONAL TRANSCEIVERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xx

FCT

Temperature
Range

x

x

x

Device
Type

Package

Process

~~Iank
P

E

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

245T
640T
645T
245AT
640AT
645AT
245CT
640CT
645CT

Non-Inverting Buffer Transceiver
Octal Inverting Buffer Transceiver
Non-Inverting Buffer Transceiver
Fast Non-Inverting Buffer Transceiver
Fast Octal Inverting Buffer Transceiver
Fast Non-Inverting Buffer Transceiver
Super Fast Non-Inverting Buffer Transceiver
Super Fast Octal Inverting Buffer Transceiver
Super Fast Non-Inverting Buffer Transceiver

D
L-.-------~SO

L

L-._ _ _ _ _ _ _ _ _ _-j

~

Commercial
MIL-STD-883, Class B

__________________________~154
174

-55°C to + 125°C
O°Cto +70°C

2S3S1 ctw 03

•

6.11

7

G

Integrated Device Technology, Inc.

IDT54174/FCT273T
IDT54174FCT273AT
IDT54174FCT273CT

FAST CMOS
OCTAL 0 FLIP-FLOP
WITH MASTER RESET

FEATURES:

DESCRIPTION:

•
•
•
•

The IDT54/74FCT273T/AT/CT are octal D flip-flops built
using advanced CEMOSTM, a dual metal CMOS technology.
The IDT54/74FCT273T/AT/CT have eight edge-triggered
D-type flip-flops with individual D inputs and outputs. The
common buffered Clock (CP) and Master Reset (MR) inputs
load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop's
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.

•
•
•
•
•
•
•
•

IDT54/74FCT273T equivalent to FASl'Mspeed
IDT54174FCT273AT 45% faster than FASl'M
IDT54174FCT273CT 55% faster than FAS"fTM
Equivalent to FAST'" output drive over full temperature
and voltage supply extremes
IOL = 48mA (commercial) and 32mA (military)
CMOS power levels (1 mW typo static)
True TTL input and output levels
Substantially lower input current levels than FASl'M
(5JlA max.)
.
Octal D flip-flop with Master Reset
JEDEC standard pinout for DIP and LCC
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B

a

a

FUNCTIONAL BLOCK DIAGRAM
00

05

02

06

07

CP

00

01

03

02

05

04

07

06

2568 cnv' 03

PIN CONFIGURATIONS

00

00
01
01
02
02
03
03
GNO

INDEX

Vee

MR

19
2
3
18
4
P20-1 17
020-1 16
5
6 5020-2 15
&
7
E20-1 14
8
13
9
12
10
11

07
07
06
06
05

01
01
02

05
04

02
03

"'"

04
CP

I

I

I

I

I

~~I

II
II
I
I L-I L-I

3 2 U 20 19
1
:] 4
18[:
17[:
:] 5
:] 6
16[:
L20-2
15[:
:J 7
14[:
:J 8
9 10 11 12 ,......,
13
,.....,,......,,......,,.....,
I

I

I

I

I

I

I

I

I

07
06
06

05
05

I

..:. 0

'" '"
Oz a..
0 00

2568 cnv' 01

2568 cnv' 02

C)

DIP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconduc1or Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
---rl"T"'7'Ir''''''~-= ~~V
- OV
tsu~'!+--~

TIMING - - - - - - ,
INPUT

,,--+----- _

3V

6J

V

lOW-HIG~~~S~

ASYNCHRONOUS CONTROL
PRESET - - - - ,
CLEAR
ETC.

,,-+---+----- -

3V
1.SV
OV

=t-

HIGH-lOW-HIGH
PULSE

~ 1.5V

_'~

--1.SV

SYNCHRONOUS CONTROL

CLOCK:~~i~~ ~sU
vvJr
ETC.

t

J

~..M.~~

- 3V
-1.5V
OV

PROPAGATION DELAY

I

ENABLE AND DISABLE TIMES
ENABLE

DISABLE
3V

SAME PHASE
INPUT TRANSITION

OUTPUT

1.SV
OV
OV
3.5V

VOH
-1.5V

VOL

VOL
OUTPUT
NORMALLY
HIGH

OPPOSITE PHASE
INPUT TRANSITION
OV

VOH
SWITCH
OPEN
OV

NOTES
2632 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate:s; 1.0 MHz; Zo:s; son; tF:S; 2.Sns;
tR:S; 2.Sns.

6.13

6

IDT54f74FCT299T!AT
FAST CMOS 8·INPUT UNIVERSAL SHIFT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XX

--------

Temperature
Range

FCT

X

X

X

Device Type

Package

Process

--------

~~Iank
P
D
SO
L
IE

'------------1

Commercial
MIL·STD·883, Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

299T
8·lnput Universal Shift Register
' - - - - - - - - - - - - - - - - - 1 2 9 9 A T Fast 8·lnput Universal Shift Register
'----------------------l

54
-55°C to + 125°C
740°C to +70°C
2632drw 03

6.13

7

G

FAST CMOS OCTAL
TRANSPARENT LATCHES

IDT54174 FCT373TI AT/CT
IDT54174FCT533T/AT/CT
IDT54/74FCT573T/AT/CT

IntegrOlted Device Technology, Inc.

FEATURES

DESCRIPTION

• IDT54/74FCT373T/533T/573T equivalent to FAS"JIM
speed and drive
• IDT54/74FCT373AT/533AT/573AT up to 30% faster
than FAS"JIM
• IDT54/74FCT373CT/533CT/573CT up to 40% faster
than FAS"fThI
• Equivalent to FASTTM output drive over full temperature
and voltage supply extremes
• CMOS devices with TRUE TTL input and output compatibility
- VOH =3.3V (typ.)
- VOL = O.3V (typ.)
• 10L = 48mA (commercial) and 32mA (military)
• CMOS power levels (1 mW typo static)
• Octal transparent latch with 3-state output control
• JEDEC Standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class 8

The I DT54/74FCT373T/AT/CT, IDT54/74FCT533T/AT/CT
and IDT54/74FCT573T/AT/CT are octal transparent latches
built using advanced CEMOSTM, a dual metal CMOS
technology. These octal latches have 3-state outputs and are
intended for bus oriented applications. The flip-flops appear
transparent to the data when Latch Enable (LE) is HIGH.
When LE is LOW, the data that meets the set-up time is
latched. Data appears on the bus when the Output Enable
(OE) is LOW. When OE is HIGH, the bus output is in the high
impedance state.

FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT373T/AT/CT AND IDT54174FCT573T/AT/CT

I
02

FUNCTIONAL BLOCK DIAGRAM IDT54174FCT533T/AT/CT

2564 cnv' 02

CEMOS is a 1rademark of In1egra1ed Device Technology. Inc.
FAST is 1rademark of National Semiconductor

MILITARY AND COMMERCIAL TEMPERATURE RANGES
te>1990 Integrated Device Technology. Inc.

2564cnv' 01

6.14

JUNE 1990
DSC-42161·

1

IDT54n4FCT373/533/573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
IDT54/74FCT373T

0

I I I I I
L-..I L....J I

17

01
02

6

8 oo

07

:J 4
:J 5
:J 6
:J 7

07

17[: 06
16[: 06

L20-2

15[: 05
14[:

]8

05

9 10 11 12 13
r-1 ,....., ,..., ,..., ,......,
I

2564 cnv· 03

II

II

0

C')

II

I

I

2564 cnv· 04

-r
0

o

OZ-l

DIP/SOIC/CERPACK
TOP VIEW

I

-r

W

(9

LCC
TOP VIEW

IDT54/74FCT573T

00
01
02

INDEX

Vee

OE
2
3
4

03

5

04

6

05

7

P20-1
020-1
8020-2
&
E20-1

19

00

18

01
02

17
16
15

02

05
OS

8

13

07
GNO

9

12

07

I

o

04

:J 4
:J 5
:J 6
:J 7
:J 8

8

0 >

I

I

L...J L...J

03

06

11

I

03
04
05
06

10

14

()

IW ()

o

Ci

I
I

II
II
I
I 1--1 1--1

3 2 ~ 20 19
1
18[: 01
17[: 02
16[: 03
15[: 04
14[: 05

L20-2

9 10 11 12 13
nronrol1
I I I I I I I I
I

I

LE
2564 cnv· 05

t--

t--Ow

2564 cnv· 06

to

00

°Z-l
(9

DIP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW

IDT54174FCT533T
OE

Vee

00

07

INOEX

W

(5
I

00

07

01

06

01

I
L...J L...J I

01

:] 4

Os

51

0'2

'Os

02

05

52
02
03

:J 5
:J 6
:J 7
:J 8

03

04

0'3
GNO

04
2564 cnv· 07

DIP/SOIC/CERPACK
TOP VIEW

I

I

10

II
II
I
I 1--1 1--1

3 2 :..J 20 19
1
18[:
17[:

07
06

16[: 56
15[: 55

L20-2

14[:

05

9 10 11 12 13
...,...,...,...,
,....,
I

LE

I

()

~

1810

II

10

II

I

I

I

I

I

~ ~1c3 2)

2564 cnv· 08

(9

LCC
TOP VIEW

6.14

2

IDT54f74FCT373/533/573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE (FCT533)(1)
Inputs

FUNCTION TABLE (FCT373 and FCT573)(1)
Outputs

DN

LE

OE

Outputs
ON

DN

LE

OE

ON

H

H

L

L

H

H

L

H

L

H

L

H

L

H

L

L

X

X

H

Z

X

X

H

Z

NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = HIGH Impedance

Inputs

25641b105

NOTE:
1. H = HIGH Voltage Level
L =LOW Voltage Level
X = Don't Care
Z = HIGH Impedance

2564tbl06

DEFINITION OF FUNCTIONAL TERMS
Pin Names
DN

Description
Data Inputs

LE

Latch Enable Input (Active HIGH)

OE

Ou1put Enable Input (Active LOW)

ON

3-State Ou1puts

ON

Complementary 3-State Ou1puts
25641b1l07

6.14

3

IDT54174FCT373/533/573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
Sj'mbol
Rating
VTERM(2) Terminal Voltage
'. with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND

CAPACITANCE

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

TA

Operating
Temperature

o to +70

-55 to +125

°C

TSIAS

Temperature

-55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

(TA

= +25°C, f = 1.0MHz)
Conditions

Typ.

Max.

Unit

CIN

Input
Capacitance

VIN = OV

6

10

pF

COUT

Output

VOUT= OV

S

12

pF

Symbol

Parameter

Capacitance
NOTE:
1. This parameter is measured at characterization but not tested.

2564 tbl 02

Under Bias
TSTG

Storage
Temperature

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output
Current

120

120

mA

NOTES:
2564tblOt
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vec by +O.5V unless otherwise noted.
2. Input and Vec terminals only.
3. Outputs and I/O terminals only.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, VCC= 5.0V +
- 10%
Min.

TypP)

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

Vil

Input LOW Level

Guaranteed Logic LOW Level

-

-

O.S

V

IIH

Input HIGH Current

Vce = Max.

VI = 2.7V

-

5

~A

III

Input LOW Current

Vee = Max.

VI = 0.5V

-5

~A

10ZH

High Impedance Output Current

Vec = Max.

Vo= 2.7V

-

10

~A

Sj'mbol

Test Condltlons(1)

Parameter

II

Input HIGH Current

Vce = Max., VI = Vcc (Max.)

-

VIK

Clamp Diode Voltage

Vcc = Min., IN = -1SmA

-

los

Short Circuit Current

Vee = Max.(3), Vo= GND

VOH

Output HIGH Voltage

Vce = Min.
VIN = VIH or Vil

lOll

Vo= 0.5V

Max.

Unit
V

-10

~A

20

-0.7

-1.2

V

-60

-120

-225

mA

10H = -6mA MIL.
IOH = -SmA COM'L.

2.4

3.3

-

V

10H = -12mA MIL.

2.0

3.0

-

V

-

0.3

0.5

V

-

200

-

mV

0.2

1.5

mA

10H = -15mA COM'L.
Val

Output LOW Voltage

VH

Input Hysteresis

Icc

Quiescent Power Supply Current

Vcc = Min.

IOl = 32m A MIL.

VIN = VIH or Vil

IOl = 4SmA COM'L.

Vee = Max.
VIN = GND or Vee

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

6.14

2564 tbl 03

4

IDT54n4FCT373/533/573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol
~Iee

IceD

Ie

Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current(4)

Total Power Supply Curren~6)

Typ.<2)

Max.

Unit

-

0.5

2.0

mA

VIN = Vee
VIN= GND

-

0.15

0.25

mAl
MHz

VIN = Vee
VIN =GND

-

1.7

4.0

mA

VIN =3.4V
VIN =GND

-

2.0

5.0

VIN = Vee
VIN =GND

-

3.2

6.5(5)

VIN = 3.4V
VIN=GND

-

5.2

14.5(5)

Test Condltlons(1)
Vee = Max.
VIN = 3.4V(3)
Vee = Max.
Outputs Open
OE=GND
One Input Toggling
50% Duty Cycle
Vee = Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
OE=GND

Min.

LE = Vee
One Bit Toqqlinq
Vee = Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
OE= GND
LE= Vee
Eight Bits Toggling

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC

256411>104

Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fiN i)
Icc = Quiescent CUrrent
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)

DH = Duty Cycle for TTL Inputs High
NT =Number of TTL Inputs at DH
ICCD =Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
Ii = Input Frequency
Ni. Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.14

5

IDT54174FCT373/533/573T/AT/CT

FAST CMOS OCTAL TRANSPARENT LATCHES

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING
RANGE FOR FCT373T/AT/CT/FCT573T/AT/CT
FCT373T/573T
Com'l.
Symbol

Parameter

tPLH
tPHL

Propagation Delay
DNto ON

tPLH
tPHL

Propagation Delay
LE to ON

tPZH
tPZL

Output Enable Time

tPHZ
tPLZ

Output Disable Time

tsu

Condltlons(1)
CL

= 50pF
= 500n

FCT373AT/573AT
Com'l.

Mil.

FCT373CT/573CT
Com'l.

Mil.

Mil.

Mln.(2 Max. Mln.(2 Max. Mln.(2 Max. Mln.l2 Max. Mln.12 Max. MlnP Max. Unit
1.5

8.0

1.5

8.5

1.5

5.2

1.5

5.6

1.5

4.2

1.5

5.1

ns

2.0

13.0

2.0

15.0

2.0

8.5

2.0

9.8

2.0

5.5

2.0

8.0

n~

1.5

12.0

1.5

13.5

1.5

6.5

1.5

7.5

1.5

5.5

1.5

6.3

ns

1.5

7.5

1.5

10.0

1.5

5.5

1.5

6.5

1.5

5.0

1.5

5.9

ns

Set-up Time HIGH
or LOW, DN to LE

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

ns

tH

Hold Time HIGH
or LOW, DN to LE

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

ns

tw

LE Pulse Width HIGH

6.0

-

6.0

-

5.0

-

6.0

-

5.0

-

6.0

-

RL

ns
2564 tbl 08

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT533T/AT/CT
FCT533T

Svmbol

Parameter

tPLH
tPHL

Propagation Delay
DNtoON

tPLH
tPHL

Propagation Delay
LE to ON

tPZH
tPZL

Output Enable Time

tPHZ
tPLZ

Output Disable Time

tsu

Set-up Time HIGH
or LOW, DN to LE

tH

Hold Time HIGH
or LOW, DN to LE

tw

LE Pulse Width HIGH

Condltlons(1)
CL
RL

= 50pF
= 500n

FCT533AT
Mil.

Com'l.

Com'l.

FCT533CT
Com'l.

Mil.

Mil.

Mln.12 Max. Mln.12 Max. Mln.12 Max. Mln.(2 Max. Mln.12 Max. Mln.l2 Max. Unit
1.5

10.0

1.5

12.0

1.5

5.2

1.5

5.6

1.5

4.2

1.5

5.1

ns

2.0

13.0

2.0

14.0

2.0

8.5

2.0

9.8

2.0

5.5

2.0

8.0

ns

1.5

11.0

1.5

12.5

1.5

6.5

1.5

7.5

1.5

5.5

1.5

6.3

ns

1.5

7.0

1.5

8.5

1.5

5.5

1.5

6.5

1.5

5.0

1.5

5.9

ns

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

ns

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

ns

6.0

-

6.0

-

5.0

-

6.0

-

5.0

-

6.0

-

ns

NOTES:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

2564tbl09

6.14

6

IDT54174FCT373/533/573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vcc

SWITCH POSITION
0---.7.0V

500n

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
25641b1
CL = load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zxt

1

PULSE WIDTH

"'-..K...JiIII:~

-=

~~V

-

OV

-

3V

tsu~0j4--~

TIMING
INPUT _ _ _ _ _ _,

LOW-HIG~UL&~

---1
- - -_
- - - 1.5V
,_-+
___
- OV

ASYNCHRONOUS CONTROL
PRESET - - - -.....
CLEAR
ETC.

10

,,-+---+---- -

=f-

HIGH-LOW-HIGH

3V
1.5V
OV

_

~ '.5V
lw

_ _ 1.5V

PULSE

SYNCHRONOUS CONTROL
CLOCK

:~~f!~ "'II:vvJr~~""-+"""""1J}--+--....n~""",,~~r-= ~~V
ETC.

~tsu

"'-..K...JiIII:~

-

OV

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

SAME PHASE
INPUT TRANSITION

DISABLE
3V
1.5V
OV

OV

3.5V
OUTPUT

VOL
VOL
SWITCH
OPEN

OPPOSITE PHASE
INPUT TRANSITION

VOH
OV

OV

NOTES
2564 drw 14
1. Diagram shown for input Control Enable-lOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ 50Q; tF ~ 2.5ns;
tR ~ 2.5ns.

6.14

7

I

IDT54f74FCT373/533/573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT=--.....;.;X~X_ _ FCT=-....:,.X:.:...;X::..,;X~X_
Temp. Range
Device Type

x

x

Package

Process

y~lank
P
D
~------------~SO

L

E
373T
573T
533T
373AT
~--------------------~573AT

533AT
373CT
573CT
533CT
~

____________________________________

~54

74

6.14

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Srnali Oulline Ie
Leadless Chip Carrier
CERPACK
Non-Inverting Octal Transparent Latch
Non-Inverting Octal Transparent Latch
Inverting Octal Transparent Latch
Fast Non-Inverting Octal Transparent Latch
Fast Non-Inverting Octal Transparent Latch
Fast Inverting Octal Transparent Latch
Super Fast Non-Inverting Octal Transparent Latch
Super Fast Non-Inverting Octal Transparent Latch
Super Fast Inverting Octal Transparent Latch
-55°C to + 125°C
O°C to +70°C

2564 cnv' 13

8

t;)

FAST CMOS OCTAL D
REGISTERS (3-STATE)

IDT54174FCT374T/AT/CT
IDT54174FCT534T/AT/CT
IDT54174FCT574T/AT/CT

Integrated Device Technology, Inc.

FEATURES

DESCRIPTION

• IDT54/74FCT374T/534T/574T equivalent to FAST'"M
speed and drive
• IDT54174FCT374AT/534AT/574AT up to 30% faster
than FAST'"M
• IDT54174FCT374CT/534CT/574CT up to 50% faster
than FAST'"M
• True TTL input and output compatibility
- VOH =3.3V (typ.)
- VOL = O.3V (typ.)
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1 mW typo static)
• Edge triggered master/slave, D-type flip-flops
• Buffered common clock and buffered common threestate control
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Meets or exceeds JEDEC Standard 18 specifications

The IDT54174FCT374T/AT/CT, IDT54/74FCT534T/AT/CT
and IDT54174FCT574T/AT/CT are 8-bit registers built using
advanced CEMOSTM, a dual metal CMOS technology. These
registers consist of eight D-type flip-flops with a buffered
common clock and buffered 3-state output control. When the
output enable (OE) input is LOW, the eight outputs are enabled. When the OE input is HIGH, the outputs are in the highimpedance state.
Input data meeting the set-up and hold time requirements
of the 0 inputs is transferred to the 0 outputs on the LOW-toHIGH transition of the clock input.

FUNCTIONAL BLOCK DIAGRAM IDT54174FCT374T AND IDT54174FCT574T

I
2569 drw 01

FUNCTIONAL BLOCK DIAGRAM IDT54174FCT534T

2569 drw 02

CEMOS is a lrademark of Inlegrated Device Technology. Inc.
FAST is a trademark of National Semiconductor

JUNE 1990

MILITARY AND COMMERCIAL TEMPERATURE RANGES
<01990 Integrated Device Technology. Inc.

6.15

DSC-4214/·

1

IDT54174FCT374/534/574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE)

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
IDT54174FCT374T
OE

Vee

00

07

Do

07
06
06
Os

01
01
02
D2

INDEX

I

04

03
GNO

04
CP

II

I I

I,

L....-'~I

3 2
01

Os

03

0

881~g<5

:J

D2
03

:] 7
:] 8

I

20 19
1
18[:

:1 4
:1 5

01
02

II

IL-IL-I

:...J

17[:
16[:

L20-2

6

15[:
14[:
9 10111213

07
06
00
05

Os

,...,,...,,...,,..., ,.....,
I

II

II

II

I

I

I

2569 drw 03

o~~oc3
(!)

DIP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW

IDT54174FCT574T

Do
01
D2

03
04

Os
06
07
GNO

2
3
4

P20-1
020-1
6 5020-2
&
7 E20-1
8

5

9
10

19

00

18
17

01
02

16
15

03
04

14

05
06

13
12

07

11

CP

I 0
680g8

INDEX

Vee

OE

W

I

II

I

I I'

II

I

~~:...J~~
1

D2 :] 4
03 :] 5
04 :] 6
Os :] 7
06 :] 8

18[:

01

17[:
15[:

02
03
04

14[:

05

L20-2

16[:

9 10 11 12 13

11 11 11 11 . ,
•

II

I

I

I

I

I

(3 ~ ~
(!)

DIP/SOIC/CERPACK
TOP VIEW

I

I

2569 drw 04

<50

LCC
TOP VIEW

IDT54174FCT534T

50

19
18

8 18 I0

INDEX

\te

OE

W

(5"7

0

10......

~

Do

2
3

01

4

01

5

02
D2

7

03

8

13

04

03
GNO

9

12

04

910111213
,....,,....,,....,,....,
,.....,

10

11

CP

I

6

P20-1
020-1
5020-2
&
E20-1

17

07
06

16
15

Os
Os

14

Os

I I I I I I I ". I
L....-'L....-'IIL-IL-I

3 2
01
01

:...J

:] 4
:] 5

1

20 19
18 [:

17 [:

02 :] 6
D2 :] 7
03 :] 8

L20-2

I I

II

II

"

10 (!)~ ~IO

DIP/SOIC/CERPACK
TOP VIEW

07
06

16 [:

Os

15 [:

05

14 [:

Os

I

2569 drw 05

v
Cl

LCC
TOP VIEW

6.15

2

IDT54174FCT374/534/574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE)

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION
Pin Names

Description

DN

D flip-flop data inputs

CP

Clock Pulse for the register. Enters data on
LOW-to-HIGH transition.

ON

3-state outputs, (true)

ON

3-state outputs, (inverted)

OE

Active LOW 3-state Output Enable input
256911>1 06

FUNCTION TABLE(1)
FCT534
Inputs

FCT3741574

Outputs

Internal

Outputs

Internal

OE

CP

ON

ON

aN

ON

aN

HI-Z

H
H

L
H

X
X

Z
Z

NC
NC

Z
Z

NC
NC

LOAD REGISTER

L
L

i
i
i
i

L
H
L

H
L

L
H
L

L

H
L

Function

H
H

Z
Z

H

H

H
Z
Z

H
L

NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = HIGH Impedance
NC = No Change
i = LOW-to-HIGH transition

256911>105

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Ratina
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND

CAPACITANCE

Commercial

MllltaJY

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

TA

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

Storage

-55 to +125

-65 to +150

°C

TSTG

(TA

Parameter(1)

= +25°C, f = 1.0MHz)
Conditions

Typ.

Max.

Unit

CIN

Input
Capacitance

VIN = OV

6

10

pF

COUT

Output
CaQacitance

VOUT= OV

8

12

pF

Symbol

NOTE:
1. This parameter is measured at characterization but not tested.

Tem~erature

PT

Power Dissipatior

0.5

0.5

W

lOUT

DC Output
Current

120

120

mA

NOTES:
256911>101
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 1/0 terminals only.

6.15

3

256911>1 02

II

IDT54f74FCT374/534/574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3·STATE)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:

Commercla:
. I TA= O°C to +70 °C Vee = 5 OV ± 5°1c0; MT
Iitary: TA= Symbol

0+

ee= 50V

Test Conditlons(l)

Parameter

± 10%0
Min.

Typ.(2)

Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

O.S

V

IIH

Input HIGH Current

Vee = Max.

VI = 2.7V

-

-

5

JlA

IlL

Input LOW Current

Vee = Max.

VI = 0.5V

-

-

-5

JlA

IOZH

High Impedance Output Current

Vee = Max.

Vo= 2.7V

-

10

JlA

Vo= 0.5V

II

Input HIGH Current

Vee = Max., VI = Vee (Max.)

VIK

Clamp Diode Voltage

Vee = Min., IN = -1SmA

-

-

los

Short Circuit Current

Vee = Max.(3l, Vo= GND

VOH

Output HIGH Voltage

Vee = Min.
VIN = VIH or VIL

10ZL

VOL

Output LOW Voltage

VH

Input Hysteresis

Icc

Quiescent Power Supply Current

Vee = Min.
VIN = VIH or VIL

V

-10
20
-1.2

V

-so

-120

-225

mA

10H = -SmA MIL.
10H = -SmA COM'L.

2.4

3.3

-

V

10H = -12mA MIL.
10H = -15mA COM'L.

2.0

3.0

-

V

10L = 32mA MIL.
10L = 4SmA COM'L.

-

0.3

0.5

V

-

200

-

0.2

1.5

Vee = Max., VIN = GND or Vee

mV

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.

mA
2569 tbl 03

3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

6.15

JlA

-0.7

4

IDT54f74FCT374/534/574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE)

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol
~Icc

IceD

. Ie

Tvp.(2)

Max.

Unit

-

0.5

2.0

mA

VIN = Vee
VIN = GND

-

0.15

0.25

mAl
MHz

VIN = Vee
VIN =GND

-

1.7

4.0

mA

OE=GND
fi = 5MHz
50% Duty Cycle
One Bit Toggling

VIN = 3.4V
VIN =GND

-

2.2

6.0

Vee = Max.
Outputs Open
fep = 10MHz
50% Duty Cycle
OE=GND
Eight Bits Toggling
fi = 2.5MHz
50% Duty Cycle

VIN = Vee
VIN =GND

-

4.0

7.8(5)

VIN = 3.4V
VIN = GND

-

6.2

16.8(5)

Test Condltlons(1)

Parameter
Quiescent Power Supply Current
TIL Inputs HIGH
Dynamic Power Supply
Current(4)

Total Power Supply Curren~6)

Vee = Max.
VIN = 3.4V(3)
Vee = Max.
Outputs Open
OE= GND
One Input Toggling
50% Duty Cycle
Vee = Max.
Outputs Open
fep = 10MHz
50% Duty Cycle

Min.

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (V IN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + 61cc DHNT + ICCD (fcp/2 + fNi)
Icc = Quiescent Current
61cc = Power Supply Current for a TTL High Input (V IN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.15

2569tb104

I

5

IDT54174FCT374/534/574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE)

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT374T/S34T/S74T
Com'l.
Symbol
tPLH
tPHL

Parameter
Propagation Delay
CPto ON(3)

tPZH
tPZL

Output Enable Time

tPHZ
tPLZ

Output Disab!e Time

tsu

Set-up Time HIGH
or LOW ON to CP

tH

Hold Time HIGH
or LOW ON to CP
CP Pulse Width
HIGH or LOW

tw

Mil.

FCT374A T/S34AT/S74AT FCT374CT/S34CT/S74CT
Com'l.

Mil.

Com'l.

Mil.

Conditlons(1) Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.'2) Max. Mln.(2) Max. MlnP) Max.
CL = SOpF
RL = 500n

Unit

2.0

10.0

2.0

11.0

2.0

6.5

2.0

7.2

2.0

5.2

2.0

6.2

ns

1.5

12.5

1.5

14.0

1.5

6.5

1.5

7.5

1.5

5.5

1.5

6.2

ns

1.5

8.0

1.5

8.0

1.5

5.5

1.5

6.5

1.5

5.0

1.5

5.7

ns

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

ns

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

ns

7.0

-

7.0

-

5.0

-

6.0

-

5.0

-

6.0

-

ns

NOTES:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. ON for FCT374 and FCT574, ON for FCT534.

25691b107

6.15

6

IDT54174FCT374/534/574T1AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE)

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
25691b108
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

PULSE WIDTH

j)---ri-~"7'r"""~-= ~~V
_ OV

tsu ---J0j4---~
TIMING
INPUT

LOW-HIG~UL&~

- 3V
V
_

6J

ASYNCHRONOUS CONTROL
PRESET - - - -....
CLEAR
ETC. _ _ _ _J

-

3V

-

OV

-

3V

=t-

HIGH-LOW-HIGH

- - + - - - - - - 1.5V

_

~ 15V
lw

_ _ 1.5V

PULSE

SYNCHRONOUS CONTROL

CLOCK:~~~~ vvJr
1
~tsu

__...___.._...A -1.5V
- OV

ETC.

PROPAGATION DELAY

II

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

_--""'----3V
SAME PHASE
INPUT TRANSITION

,..........., - t - - - - - OV

3.5V
OUTPUT

VOL
VOH

OPPOSITE PHASE
INPUT TRANSITION

SWITCH
OPEN
OV

"---J----OV

NOTES
2569 drw 06
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate S 1.0 MHz; Zo S
tF S 2.5ns;
tR S 2.5ns.

son;

6.15

7

IDT54174FCT37415341574TIATICT
FAST CMOS OCTAL D REGISTERS (3·STATE)

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

XX
FCT
T:;:'e-m-p-."""R....a-n-ge-

XXXX

X

-:=D~e-v,...ic-e-:;:T,....ype-

X

Package

Process

Y:1ank
P

o

~

_ _ _ _ _ _~SO

L

E
374T
574T
534T
374AT
~----------~574AT

534AT
374CT
574CT
534CT
~

_ _ _ _ _ _~_____________~54
74

6.15

Commercial
MIL·STO·883, Class 8
Plastic DIP
CEROIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Non-Inverting Octal 0 Register
Non-Inverting Octal 0 Register
Inverting Octal 0 Register
Fast Non-Inverting Octal 0 Register
Fast Non-Inverting Octal 0 Register
Fast Inverting Octal 0 Register
Super Fast Non-Inverting Octal 0 Register
Super Fast Non-Inverting Octal 0 Register
Super Fast Inverting Octal 0 Register
-55°C to + 125°C
O°C to +70°C

2569 cnv' 11

8

(;)®

I DT54/74FCT377T
I DT54/74FCT377 AT
IDT54/74FCT377CT

FAST CMOS
OCTAL 0 FLIP-FLOP
WITH CLOCK ENABLE

Integrated Device Technology. Inc.

FEATURES:

DESCRIPTION:

•
•
•
•

The IDT54/74FCT377T/AT/CT are octal 0 flip-flops built
using advanced CEMOSTM, a dual metal CMOS technology.
The IDT54174FCT377T/AT/CT have eight edge-triggered, 0type flip-flops with individual 0 inputs and
outputs. The
common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is
fully edge-triggered. The state of each 0 input, one set-up
time before the LOW-to-HIGH clock transition, is transferred
to the corresponding flip-flop's output. The CE input must
be stable only one set-up time prior to the LOW-to-HIGH
transition for predictable operation.

•
•
•
•
•
•

IDT54/74FCT377T equivalent to FASl'M speed
IDT54174FCT3nAT 25% faster than FAS"fI"M
IDT54174FCT3nCT 40% faster than FAS"fI"M
True TTL input and output compatibility:
- VOH = 3.3V (typ.)
- VOL = 0.3V (typ.)
IOL = 48mA (commerCial) and 32mA (military)
CMOS power levels (1 mW typo static)
Octal 0 flip-flop with clock enable
Meets or exceeds JEDEC Standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B

a

a

FUNCTIONAL BLOCK DIAGRAM

11
2630 drw02

PIN CONFIGURATIONS

° O\W 8,...

INOEX
CE
00

Vee

00
01
01

2
3
4
5

02
02

6
7

03

8
9

03

GNO

10

P20-1
020-1
5020-2

&
E20-1

19

07

18
17
16
15

07
06
06
05
05

14
13
12
11

000>0

.".
01
01
02
02
03

04
04

]
]
]
]
]

4
5
6
7
8

32: :2019
18
"1

17
16
15
14
9 10 11 12 13
rlnronro /
l20-2

8°a..~~

CP

"
[
[
[
[
[

07
06
06
05
05
2630 drw 01

ZOOO

(!)

LCC
TOP VIEW

DlP/SOIC/CERPACK
TOP VIEW
CEMOS is a trademark 01 Integrated DeVice Technology. Inc.
FAST is a trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
f>t990 Integrated Device Technology. Inc.

6.16

JUNE 1990
DSC-4200I·

1

IDT54f74FCT377T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE(1)

PIN DESCRIPTION
Pin Names

Description

Inputs

00- 07

Data Inputs

CE

Clock Enable (Active LOW)

Load "1"

00-07

Data Outputs

Load "0"

CP

Clock Pulse Input

Hold (Do Nothing)

Operating Mode

CE

D

0

i
i
i

I

h

H

I

I

L

h
H

X
X

No Change
No Change

H

2630 lbl 05

Outputs

CP

NOTE:
2630 lbl 06
1. H = HIGH Vc!t:l;~ Level
h = HIGH Voltage Level one setup time prior to the LOW-ta-HIGH
Clock Transition
L = LOW Voltage Level
I = LOW Voltage Level one setup time prior to the LOW-ta-HIGH Clock
Transition
X = Immaterial
i = LOW-to-HIGH Clock Transition

ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

CAPACITANCE

Conditions

Max.

Unit

Input
Capacitance

VIN = OV

6

10

pF

COUT

Output
Capacitance

VOUT = OV

8

12

pF

Unit

Symbol

VTERM(2) Terminal Voltage
with Respect
toGND

-0.5 to +7.0

-0.5 to +7.0

V

VTERM(3) Terminal Voltage
with Respect
toGND

-0.5 to Vee

-0.5 to Vee

V

Operating
Temperature

Oto +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

= +25°C, f = 1.0MHz)

CIN

Military

TA

(TA

Parameter(l)

Commercial

NOTE:
1. This parameter is guaranteed but not tested.

Typ.

2630 lbl 02

NOTE:
263Olbl01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and I/O terminals only.

6.16

2

IDT54174FCT377T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE

MIUTARV AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V +
- 5%; Military: TA
Symbol

= -55°C to +125°C, Vcc = 5.0V +- 10%

Test CondltJons(1)

Parameter

Min.

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

VIL

Input LOW Level

Guaranteed Logic LOW Level

IIH

Input HIGH Current

Vee = Max.

VI = 2.7V

-

IlL

Input LOW Current

Vee = Max.

VI = 0.5V

II

Input HIGH Current

Vee = Max., VI = Vee (Max.)

VIK

Clamp Diode Voltage

los
VOH

Typ.(2)

Max.

-

-

Unit
V

0.8

V

5

Jl.A

-5

Jl.A

-

20

Jl.A

Vee = Min., IN = -18mA

-

-0.7

-1.2

V

Short Circuit Current

Vee ... MaxP), Vo = GND

-60

-120

-225

mA

Output HIGH Voltage

Vee = Min.

10H = -6mA MIL.

2.4

3.3

-

V

VIN = VIH or VIL

10H = -8mA COM'L.
2.0

3.0

-

V

-

0.3

0.5

V

-

200

-

mV

-

0.2

1.5

mA

10H = -12mA MIL.
10H = -15mA COM'L.
VOL

Output LOW Voltage

VH

Input Hysteresis

Icc

Quiescent Power
Supply Current

Vee = Min.

10L = 32mA MIL.

VIN = VIH or VIL

10L = 48mA COM'L.

Vee = Max.
VIN = GND or Vee

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

2630 tbl 03

I

6.16

3

IDT54f74FCT3m/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol

Min.

Typ.(2)

Max.

Unit

-

0.5

2.0

mA

VIN = Vee
VIN =GND

-

0.15

0.2S

Vee = Max., Outputs Open
fep = 1OMHz, SO% Duty Cycle

VIN = Vee
VIN = GND

-

1.7

4.0

CE=GND
One Bit Toggling at fi = SMHz
50% Duty Cycle

VIN = 3.4V
VIN =GND

-

2.2

6.0

Vee = Max., Outputs Open
fep =1 OMHz, SO% Duty Cycle

VIN = Vee
VIN = GND

-

4.0

7.8(5)

CE= GND
Eight Bits Toggling at fi = 2.SMHz
50% Duty Cycle

VIN = 3.4V
VIN= GND

-

6.2

16.8(5)

Test Condltlons(l)

Parameter

61ee

Quiescent Power Supply
Current TIL Inputs HIGH

Vee = Max.
VIN = 3.4 V(3)

IceD

Dynamic Power Supply
Current(4)

Vee = Max., Outputs Open
CE= GND
One Input Toggling
50% Duty Cycle

Total Power Supply
Current(S)

Ie

mAl
MHz

mA

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IrNPuTs + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fi Ni)
Icc =Quiescent Current
~Icc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cyde for TIL Inputs High
NT = Number of TIL inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

2630 Ibl 04

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT377T

Symbol
tPLH
tPHL
tsu

tH

tsu

tH

tw

Parameter
Propagation Delay
CPto On
Set-up Time
HIGH or LOW
Dnto CP
Hold nme
HIGH or LOW
Dnto CP

I DT54/74 FCT377AT

IDT54/74FCT377CT

Com'l.
Mil.
MIl.
Cond ltion(l) Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Min.(2) Max. Mln.(2) Max. Unit
Com'l.

CL = 50pF
Rl = soon

2.0

13.0

Com'l.

Mil.

2.0

1S.0

2.0

7.2

2.0

8.3

2.0

5.2

2.0

5.S

ns

2.5

-

3.0

-

2.0

-

2.0

-

2.0

-

2.0

-

ns

2.0

-

2.5

-

1.5

-

1.5

-

1.5

-

1.5

-

ns

Set-up Time
HIGH or LOW
CEto CP
Hold nme
HIGH or LOW
CEtoCP

4.0

-

4.0

-

3.5

-

3.5

-

3.5

-

3.5

-

ns

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

ns

Clock Pulse Width,
HIGH or LOW

7.0

-

7.0

-

6.0

-

7.0

-

6.0

-

7.0

-

ns

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

2630 Ibl 07

6.16

4

IDT54174FCT377T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2630 1b1 08
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

PULSE WIDTH

-= ~~V

l

.......-.___ -

OV

tsu --I0j4--~
-

TIMING
INPUT

---if------

-

LOW-HIG~UL~~

3V
1.5V
OV

ASYNCHRONOUS CONTROL

HIGH-LOW-H"H

PRESET - - - - - - - - , I--+---~-------- - 3V
CLEAR
- - + - - - - - - 1.SV

_

~ 1.5V
IW

__

1.SV

PULSE

ETC. - - - - - - - - , ,--+---~-------- - OV
SYNCHRONOUS CONTROL
- 3V
-1.5V
___
OV
CLOCK
!
ETC.

:~~t1~ vvJr
~tsu

=t-

..K...K~

PROPAGATION DELAY

II

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

,_-----3V
SAME PHASE
INPUT TRANSITION

P--~+----OV

OV

3.SV

_----"""'.t-- VOH
OUTPUT

-1.SV

VOL

VOL

OPPOSITE PHASE
INPUT TRANSITION

SWITCH
OPEN

OV

' - - - - - - ' - - - OV

NOTES
2630 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ son; tF S 2.Sns;
tR S 2.Sns.

6.16

5

IDT54174FCT377T/AT/CT
FAST CMOS OCTAL 0 FLIP-FLOP WITH CLOCK ENABLE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XX

FCT

Temperature
Range

XXXX

X

x

Device Type

Package

Process

~~Iank

Commercial
MIL-STD-883, Class B

P

Plastic DIP
CERDIP
Small Outline IC
L
Leadless Chip Carrier
E
CERPACK
377T
Octal
D Flip-Flop w/Clock Enable
' - - - - - - - - - - - - - 11 377AT Fast Octal D Flip-Flop w/Clock Enable
1
377CT Super Fast Octal D Flip-Flop w/Clock Enable

D

' - - - - - - - - - - 1 SO

154
74

'--------------------------------~I

-55°C to + 125°C
O°C to +70°C
2630 drw 03

6.16

6

(;)®

IDT54/74FCT399T
IDT54/74FCT399AT

FAST CMOS QUAD
DUAL-PORT REGISTER

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• IDT54/74FCT399T equivalent to FASl'M speed
• IDT54174FCT399AT 30% faster than FASl'M
• Equivalent to FASl'M pinout/function and output drive
over full temperature and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1 mW typo static)
• TTL input and output level compatible
• Available in 16-pin DIP and SOIC, and 20-pin LCC
• Product avilable in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

80th these devices are high-speed quad dual-port
registers. They select four bits of data from either of two
sources (Ports) under control of a common Select input (S).
The selected data is transferred to a 4-bit output register
synchronous with the LOW-to-HIGH transition of the Clock
input (CP). The 4-bit D-type output register is fully edgetriggered. The Data inputs (lox, 11X) and Select input (S) must
be stable only one set-up time priorto, and hold time after, the
LOW-to-HIGH transition of the Clock input for predictable
operation.

FUNCTIONAL BLOCK DIAGRAM
10A-------,

S
OA
I1A---+----t--t-I

lOB -------,---+-+--I-~

OB
11B-------t-+-I

•

IOC-------t--t-I

Oc
11c-------t--t-I

10D-------+-+-I

OD
110---------1

cp------------,
2633 drw 01

CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of National Semicondudor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
O

INDEX

Vee

00

OA
lOA
11A
11B
lOB
OB
GND

'-''--'I

3

100
110

lOA
11A
NC
I1B
lOB

l1e
loe
Oe
CP

l

]
)
]
)
)

IL..-J

L-J

2 1 1 20 19

'1'

4

H[

L20-2

6

7
8

100
110
16[ NC
1S[ 11C
14[ loe
18[

5

~~~~~

)

o~~~8

DIP/SOIC/CERPACK
TOP VIEW

(!)

2633 drw02

LCC
TOP VIEW

FUNCTION TABLE(1)

PIN DESCRIPTION
Pin Names

Description

Outputs

Inputs

S

Common Select Input

S

10

It

CP

Clock Pulse Input (Active Rising Edge)

I

I

X

L

lOA -100

Data Inputs from Source 0

I

h

X

H

11A-110

Data Inputs from Source 1

h

X

I

L

OA-Oo

Register True Outputs

h

X

h

H

26331b105

NOTE:
1. H

L
h

LOGIC SYMBOL

x

Q

26331b106

HIGH Voltage Level
LOW Voltage Level
HIGH Voltage Level one set-up time prior to the LOW-Io-HIGH
clock transition
LOW Voltage Level one set-up time prior to the LOW-to-HIGH
clock transition
Immaterial

S

2633 drw 03

6.17

2

IDT54f74FCT399T/AT
FAST CMOS QUAD DUAL-PORT REGISTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE(TA = +25°C, f = 1.0MHz)

ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

Commercial

Military

Unit

Symbol

Parameter(1)

Conditions Typ.

CIN

Input
Capacitance
Output
Capacitance

VIN

VTERM(2) Terminal Voltage
with Respect
toGND

-0.5 to +7.0

-0.5 to +7.0

V

VTERM(3) Terminal Voltage
with Respect
toGND

-0.5 to Vee

-0.5 to Vee

V

CoUT

= OV

VOUT = OV

Max.

Unit

6

10

pF

8

12

pF

NOTE:
26331b102
1. This parameter is measured at characterization data and not tested.

TA

Operating
Temperature

o to +70

-55 to + 125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

NOTE:
26331bIOl
1. Stresses greater than those listed under ABSOLUTE MAXI MUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals.
3. Outputs and 1/0 terminals.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial' TA = O°C to +70°C Vcc = 5 OV -+ 5%' Military' TA = -55°C to +125°C , Vcc = 5.0V +
- 10%
Typ.(2)
Test Condltlons(1)
Symbol
Parameter
Min.
VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

VIL

Input LOW Level

Guaranteed Logic LOW Level

IIH

Input HIGH Current

Vee = Max.

VI = 2.7V

-

IlL

Input LOW Current

Vee = Max.

VI = 0.5V

-

II

Input HIGH Current

Vee = Max., VI = Vec (Max.)

-

VIK

Clamp Diode Voltage

Vce = Min., IN = -1SmA

-

los

Short Circuit Current

Vee = Max(3)., Vo = GND

VOH

Output HIGH Voltage

Vee = Min.

10H = -6mA MIL.

VIN = VIH or VIL

10H = -SmA COM'L.
10H = -12mA MIL.

-

Max.

Unit

-

V

0.8

V

5

~A

-5

~A

20

~A

-0.7

-1.2

V

-60

-120

-225

mA

2.4

3.3

-

V

2.0

3.0

-

V

-

0.3

0.5

V

-

200

-

mV

0.2

1.5

rnA

10H = -15mA COM'L.
VOL

Output LOW Voltage

VH

Input Hysteresis

lee

Quiescent Power
Supply Current

Vee = Min.

10L = 32mA MIL.

VIN = VIH or VIL

10L = 4SmA COM'L.

Vee = Max.
VIN = GND or Vee

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = S.OV, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

6.17

26331b103

3

•

IDT54174FCT399T/AT
FAST CMOS QUAD DUAL-PORT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol

Min.

Typ.(2)

Max.

Unit

-

0.5

2.0

rnA

VIN = Vee
VIN = GND

-

0.15

0.25

mAl
MHz

Vee = Max., Outputs Open
fep = 10MHz, 50% Duty Cycle

VIN = Vee
VIN = GND

-

1.7

4.0

rnA

One Bit Toggling at fi
50% Duty Cycle
S = Steady State

VIN = 3.4V
VIN = GND

-

2.2

6.0

Vee = Max., Outputs Open
fep = 1OM Hz, 50% Duty Cycle

VIN = Vee
VIN= GND

-

4.0

7.8(5)

Four Bits Toggling at fi = 5MHz
50% Duty Cycle
S = Steady State

VIN = 3.4V
VIN= GND

-

5.2

12.8(5)

Test Condltlons(l)

Parameter

~Iee

Quiescent Power Supply
Current TIL Inputs HIGH

Vee = Max.
VIN = 3.4v(3)

IceD

Dynamic Power Supply
Current(4)

Vee = Max., Outputs Open
One Input Toggling
50% Duty Cycle

Ie

Total Power Supply
Current(6)

=

5MHz

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + l1lcc DHNT + ICCD (fcp/2 + fi Ni)
Icc = Quiescent Current
l1lcc = Power Supply Current for a TTL High Input (V IN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

2633 till 04

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT399AT

IDT54/74FCT399T

Com'l.
Symbol

Parameter

Conditlon(l)

Min.(2) Max.

Min.(2) Max.

MinP)

Mil.

Max. Min.(2) Max.

Unit

2.5

7.0

2.5

7.5

ns

-

3.5

-

4.0

-

ns

1.5

-

1.0

-

1.0

-

ns

-

9.5

-

8.5

-

9.0

-

ns

0

-

0

-

0

-

0

-

ns

5.0

-

7.0

-

5.0

-

6.0

-

tPLH
tPHL

Propagation Delay
CP to Qn

tsu

Set-up Time HIGH or LOW
In to CP

4.0

-

4.5

tH

Hold Time HIGH or LOW
Into CP

1.0

-

tsu

Set-up Time HIGH or LOW
StoCP

9.0

tH

Hold Time HIGH or LOW
StoCP

tw

CP Pulse Width HIGH or LOW

CL = 50pF
RL = 500n

Com'l.

Mil.

3.0

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

10.0

3.0

11.5

ns
2633 till 07

6.17

4

IDT54174FCT399T/AT
FAST CMOS QUAD DUAL-PORT REGISTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:

2633 Ibl 08

Cl = load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

PULSE WIDTH

-= ~~V

J

___...-.____ -

OV

tsu~0j4--~

TIMING
INPUT _ _ _ _ _ _-'

3V
- - - 1 - - - - - - 1.5V
- OV

ASYNCHRONOUS CONTROL
PRESET - - - -.....
CLEAR

-

3V

-

OV

HIGH-LOW-HIGH
PULSE

- - + - - - - - - 1.5V

ETC. - - - - ,

=t

LOW-HIG~~~~

-

~ 1.5V
IW

__

1.5V

SYNCHRONOUS CONTROL
CLOCK

:~~~~
vvJr l
ETC. ~tsu

- 3V
-1.5V
---------- - OV

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

----3V
---1.SV
)---,~ + - - - - OV

SAME PHASE
INPUT TRANSITION

3.5V
OUTPUT

VOL
VOH

OPPOSITE PHASE
INPUT TRANSITION

SWITCH
OPEN

OV

' - - - - . . I - - - - OV

NOTES
2633 drw 05
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ son; tF ~ 2.Sns;
tR ~ 2.Sns.

6.17

5

II

IDT54174FCT399T/AT
FAST CMOS QUAD DUAL-PORT REGISTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

XX

FCT

Temperature
Range

XXXX

X

x

Device Type

Package

Process

~~Iank·
P

o

'----------; L
SO
E

I 399T

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC
CERPACK
Quad Dual-Port Register

' - - - - - - - - - - - - - - - - 11 399AT Fast Quad Dual-Port Register
L - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~I

54

-55°C to +125°C

I 740°C to +70°C
2633 drw04

6.17

6

G

FAST CMOS a-BIT
IDENTITY COMPARATOR

IDT54174FCT521 T
IDT54174FCT521 AT
IDT54174FCT521 BT
IDT54174FCT521 CT

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

•
•
•
•
•

The IDT54/74FCT521T/AT/BT/CT are 8-bit identity comparators built using advanced CEMOSTM, a dual metal CMOS
technology. These devices compare two words of up to eight
bits each and provide a LOW output when the two words
match bit for bit. The expansion input fA = 8 also serves as an
active LOW enable input.

•
•
•
•
•
•
•
•

IDT54/74FCT521T equivalent to FASTTM speed
IDT54174FCT521AT 35% faster than FAS"fnI
IDT54174FCT521 BT 50% faster than FAS"fnI
IDT54174FCT521CT 60% faster than FAS"fnI
Equivalent to FASTTM output drive over full temperature
and voltage supply extremes
IOL = 48mA (commercial), and 32mA (military)
CMOS power levels (1 mW typo static)
True TIL input and output levels
Substantially lower input current levels than FASTTM
(5~ max.)
8-bit Identitiy Comparator
Product available in Radiation Tolerant and Radiation
Enhanced versions
JEDEC standard pinout for DIP and LCC
Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

II

2572 drw 01

CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
1C1990 Integrated Device Technology, Inc.

6.18

JUNE 1990
DSC-421 01·

1

IDT54f74FCT521T/AT/BT/CT
FAST CMOS 8-BIT IDENTITY COMPARATOR

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
INDEX
iA=B

Vee

Ao

2

19

OA=B

80

3

18

87

Al

4

17

A7

81

5

A2

6

82

7

A3

8

P20-1
D20-1
S020-2
&
E20-1

16

86

15

A6

14

8s

13

As

I

II

3
Al

:] 4

81

:] 5

f1.2.

:] 6

~

:] 7

k3

:] 8

2

83

9

12

84

10

11

A4

20 19
18[:

87

17[:

Pv

L20-2

16[:

a;

15[

P6

14[:

Bs

9 10 11 12 13
I

r--1 , - , , - , r-'1
I I I I I I I
I

I

t£3~103

POWER SUPPLV CHARACTERISTICS
Symbol

TypJ2)

Max.

Unit

-

0.5

2.0

rnA

VIN = Vee
VIN = GND

-

0.15

0.25

Vee = Max.
Outputs Open

VIN = Vee
VIN = GND

-

1.7

4.0

f i = 10MHz

VIN =3.4V
VIN = GND

-

2.0

5.0

Test Conditlons(l)

Parameter

!lIce

Quiescent Power Supply
Current TIL Inputs HIGH

Vee = Max.
VIN = 3.4V(3)

IceD

Dynamic Power Supply Current(4)

Vee = Max.
Outputs Open
One Input Toggling
50% Duty Cycle

Ie

Total Power Supply Current(5)

One Bit Toggling
50% Duty Cycle

Min.

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (V IN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fiNi)
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
Ii = Input Frequency
Ni = Number of Inputs at Ii
All currents are in milliamps and all frequencies are in megahertz.

6.18

mAl
MHz

rnA

257211:>104

3

II

IDT54174FCT521T/AT/BT/CT
FAST CMOS 8·BIT IDENTITY COMPARATOR

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT521T

Com'!.
Symbol

Parameter

Conditlon<1)

tPLH
tPHL

Propagation Delay
An or Bn to

CL = SOpF
RL=

soon

Mil.

IDT54174FCT521AT

Com'l.

Mil.

IDT54174FCT521 BT

Com'l.

Mil.

IDT54/74FCT521 CT

Com'l.

Mil.
Unit

Mln.(2 Max. MlnP Max. Mln.(2 Max. Mln.(2 Max. Mln.(2 Max. Mln.'2 Max. Mln.'2 Max. Mln.(2 Max.

1.S 11.0 l.S 1S.0 1.S 7.2

1.S 9.S

1.S S.S

1.S

7.3 1.S 4.S 1.5 S.1

ns

1.S 10.0 1.5 9.0

1.S 7.8

1.5 4.6

1.S

6.0

1.5 4.S

ns

OA=B
tPLH
tPHL

Propagation Delay

iA = B to
OA=B

l.S

NOTES:
1. See test drcuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

6.0

1.S 4.1

2572lbl07

6.18

4

IDTS4174FCTS21 T/AT/BT/CT
FAST CMOS a-BIT IDENTITY COMPARATOR

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vcc

SWITCH POSITION
0--.7.0V

soon

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

2572lbl08
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

j

PULSE WIDTH

__..K._ _~

-= ~~V
-

OV

tsu --I0j4--~

TIMING
INPUT _ _ _ _ _ _"

LOW_HIG~uLi1~=t- ~'5V

- 3V
_ 6~V

ASYNCHRONOUS CONTROL
PRESET - - - - , ~-~-~---­ --+-----CLEAR
ETC. - - - - "
SYNCHRONOUS CONTROL
-

CLOCK:~~t~~ vvY
l
~Su
ETC.

_ _..K._ _

~

HIGH-LOW-HIGH

3V

1.5V

_ _ 1.5V

3V
-1.5V
OV

•

ENABLE AND DISABLE TIMES
ENABLE

DISABLE
,..----3V

)0---.

OV

+ - - - - OV
3.5V

,..---~.+-- VOH

OUTPUT

tw

t

PROPAGATION DELAY

SAME PHASE
INPUT TRANSITION

_

PULSE

OV

-1.5V

VOL

VOL
VOH
OPPOSITE PHASE
INPUT TRANSITION

SWITCH
OPEN
OV
---J----OV

NOTES
2572 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate::;; 1.0 MHz; Zo s son; tF $ 2.Sns;
tR S 2.Sns.

6.18

S

IDT54174FCT521T/AT/BT/CT
FAST CMOS 8-BIT IDENTITY COMPARATOR

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT _~XX...:....-_ FCT
Temp. Range

XXXX

x

x

Device Type

Package

Process

Y:lank

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC

521T
521 AT
~-----------~521BT

521CT
~

___________________________~54

74

8-Bit Comparator
Fast 8-Bit Comparator
Very Fast 8-Bit Comparator
Super Fast 8-Bit Comparator
-55°C to + 125°C
O°C to +70°C
2572 cnv' 08

6.18

6

t;)®
Integr.ated Device Technology,lnc.

IDT54n4FCT543T
IDT54n4FCT543AT

FAST CMOS
OCTAL LATCHED
TRANSCEIVER

FEATURES:

DESCRIPTION:

• IDT54/74FCT543T equivalent to FAST'"M speed
• IDT54174FCT543AT 25% faster than FAST'"M
• Equivalent to FASTTM output drive over full temperature
and voltage supply extremes
• IOL = 64mA (commercial), 48mA (military)
• 8-bit octal latched transceiver
• Separate controls for data flow in each direction
• Back-to-back latches for storage
• CMOS power levels (1 mW typo static)
• Substantially lower input current levels than FAST'"M

The IDT54/74FCT543T/AT are non-inverting octal
transceivers built using advanced CEMOSTM, a dual metal
CMOS technology. These devices contain two sets of eight Dtype latches with separate input and output controls for each
set. For data flow from A to B, for example, the A-to-B Enable
(CEAB) input must be LOW in order to enter data from Ao-A7
orto take data from Bo-B7, as indicated in the Function Table.
With CEAB LOW, a LOW signal on the A-to-B Latch Enable
(LEAB) input makes the A-to-B latches transparent; a
subsequent LOW-to-HIGH transition of the LEAB signal puts
the A latches in the storage mode and their outputs no longer
change with the A inputs. With CEAB and OEAB both LOW,
the 3-state B output buffers are active and reflect the data
present at the output of the A latches. Control of data from B
to A is similar, but uses the CEBA, LEBA and OEBA inputs.

(5~max.)

• True TIL input and output levels
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
r--------------------------------------------------.,

D

DETAIL A

a

~-------....--+-

Bo

LE
AO~-+-~------4-<

a

D

II

L_________________ _____ _
A1
A2

B1
B2

A3

A4

DETAIL A x 7

As
As
A7

B3
B4
Bs

B6

B7

OEBA-----a
D-----OEAB
CEBA---~~~~--~---------~

LEBA

D - - - - - CEAB

2614 drw 01

CEMOS is a trademark of Integrated Device Techology. Inc.
FAST is a registered trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
1I:l1990 Integrated Device Technology, Inc.

6.19

JUNE 1990
DSC-4203/·

1

IDT54174FCT543T/AT
FAST CMOS OCTAL LATCHED TRANSCEIVER

MIUTARV AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
Vee

LEBA
OEBA
Ao
A1
A2
A3
A4
As
A6
A7
CEAB
GND

INDEX

CEBA
Bo
B1
B2
B3
B4
Bs
B6
B7
LEAB
OEAB

m lex:
mum
ex:
lex:
Wo
ex:°OWwOu
-.JZ> om

l

L-J L...J L...J

4 3 2

I I

L...J L......J L-...J

I 128 2726
w
25 [
A1 Js
1
24 [
J6
A2
23 [
A3 J7
J28-1
22 [
NC J8
L28-1
21 [
A4 _] 9
20 [
As J 10
19 [
A6 J 11
12 13 14 15 16 17 18

B1
B2
B3
NC
B4
Bs
B6

rlrt'--'''-'r1r-.,--,

2613 drw 02
. DIP/SOIC/CERPACK
TOP VIEW

LCC/PLCC
TOP VIEW

FUNCTION TABLE(1, 2)

PIN DESCRIPTION
Pin Names

For A-to-B (Symmetric with B-to-A)

Description

OEAB

A-to-B Output Enable Input (Active LOW)

OEBA

B-to-A Output Enable Input (Active LOW)

CEAB

A-to-B Enable Input (Active LOW)

CEBA

B-to-A Enable Input (Active LOW)

LEAB

A-to-B Latch Enable Input (Active LOW)

CEAB

LEBA

B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
26131b102

LOGIC SYMBOL

LEAB

OEAB

A-to-B

-

H

-

-

-

H

-

H

Ao-A7
Bo-B7

Latch
Status

Inputs

-

Storing

Output
Buffers
Bo-B7
High Z

-

Storing
High Z

L

L

L

Transparent

Current A Inputs

L

H

L

Storing

Previous· A Inputs

NOTES:
25131b101
1. • Before LEAB LOW-to-HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
- = Don't Care or Irrelevant
2. A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA.

LEAB CEAB CEBA LEBA
Ao

Bo

A1

B1

A2

B2

A3

B3

A4

B4

As

Bs

A6

B6

A7

B7

OEBA

OEAB

2613 drw 03

6.19

2

IDT54f74FCT543T/AT
FAST CMOS OCTAL LATCHED TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage
with Respect
toGND

CAPACITANCE

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

o to +70

-55 to +125

°C

TA

Operating
Temperature

TSIAS

-55 to +125

-65 to + 135

°C

-55 to +125

-65 to + 150

°C

PT

Temperature
Under Bias
Storage
Temperature
Power Dissipation

0.5

0.5

lOUT

DC Output Current

120

120

W
mA

TSTG

Symbol

(TA= +25°C, f = 1.0MHz)

Parameter(l)

Max.

Unit

CIN

Input Capacitance

Conditions Typ.
VIN = OV

6

10

pF

CliO

1/0 Capacitance

VOUT = OV

S

12

pF

NOTE:
26141b104
1. This parameter is guaranteed by characterization and not tested.

NOTES:
26141b103
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vce by +O.5V unless otherwise noted.
2. Inputs and Vee terminals only.
3. Outputs and 1/0 terminals only.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, VCC = 5.0V ± 5%; Military: TA = -55°C to + 125°C, VCC = 5.0V ± 10%
Symbol

Test Condltions(1)

Parameter

Min.

Typ.(2)

-

Max.

Unit

-

V

O.S

V

5

IlA

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

VIL

Input LOW Level

Guaranteed Logie LOW Level

IIH

Input HIGH Current

Vee

-

-0.7

·1.2

Il A
V

-60

-120

-225

mA

2.4

3.3

-

V

2.0

3.0

-

V

-

0.3

-

200

-

mV

-

0.2

1.5

mA

= Max.

Except 1/0 Pins

= 2.7V
110 Pins
Except 1/0 Pins
Vee = Max.
1/0 Pins
VI = 0.5V
Vee = Max., VI = Vee (Max.)
Vee = Min., IN = -1SmA
Vee = MaxP), Vo = GND
Vee = Min.
10H = ·6mA MIL.
10H = -SmA COM'L.
VIN = VIH or VIL
10H = -12mA MIL.
10H = -15mA COM'L.
10L = 48mA MIL.(4)
Vee = Min.
VIN = VIH or VIL
10L = 64mA COM'L.
VI

ilL

Input LOW Current

II

Input HIGH Current

VIK

Clamp Diode Voltage

los

Short Circuit Current

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

VH

Input Hysteresis

Icc

Quiescent Power
Supply Current

Vee = Max.
VIN = GND or Vcc

15
-5

Il A

-15
20

0.55

V

NOTES:
26131b105
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These are maximum IOL values per output. for 8 outputs turned on simultaneously. Total maximum IOL (all outputs) is 512mA for commercial and
384mA for military. Derate IOL for number of outputs exceeding 8 turned on simultaneously.

6.19

3

II

IDT54174FCT543T/AT
FAST CMOS OCTAL LATCHED TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol

Parameter

Typ.(2)

Max.

Unit

-

0.5

2.0

mA

VIN = Vee
VIN = GND

-

0.15

0.25

Vee = Max., Outputs Open
fep = 10MHz (LEAB)
50% Duty Cycle
CEAB and OEAB = GND
CEBA = Vee
One Bit Toggling
at fi = 5MHz
50% Duty Cycle

VIN = Vee
VIN = GND

-

1.7

4.0

VIN = 3.4V
VIN = GND

-

2.2

6.0

Vee = Max., Outputs Open
fep = 10MHz (LEAB)
50% Duty Cycle
CEAB and OEAB = GND
CEBA = Vee
Eight Bits Toggling
at fi = 5MHz
50% Duty Cycle

VIN = Vee
VIN = GND

-

7.0

12.8(5)

VIN = 3.4V
VIN = GND

-

9.2

21.8(5)

Test Conditions(1)

61ee

Quiescent Power Supply
Current TIL Inputs HIGH

Vee = Max.
VIN = 3.4 V(3)

IceD

Dynamic Power Supply Current(4)

Vee = Max., Outputs Open
CEAB and OEAB = GND
CEBA = Vee
One input Toggling
50% Duty Cycle

Ie

Total Power Supply Current(G)

Min.

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at vee or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT +IINPUTS + IDYNAMIC
Ic = Icc + .1lcc DHNT + ICCD(fCP/2 + fiNi)
Icc = Quiescent Current
Alcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non·Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.19

mAl
MHz

mA

2613 Ibl 06

4

IDT54174FCT543T/AT
FAST CMOS OCTAL LATCHED TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT543T
Com'l.
Symbol
tPLH
tPHL
tPLH
tPHL

Parameter
Propagation Delay Transparent
Mode An to Bn or Bn to An
Propagation Delay
LEBA to An, LEAB to Bn

Condltlon(1)
CL = 50pF
RL = soon

Mln.(2) Max.

IDT54174FCT543AT
Com'l.

Mil.
Mln.(2) Max.

Mln.(2)

Mil.
Max. Mln.(2) Max.

Unit

2.5

8.5

2.5

10.0

2.5

6.5

2.5

7.5

ns

2.5

12.5

2.5

14.0

2.5

8.0

2.5

9.0

ns

tPZH
tPZL

Output Enable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn

2.0

12.0

2.0

14.0

2.0

9.0

2.0

10.0

ns

tPHZ
tPLZ

Output Disable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn

2.0

9.0

2.0

13.0

2.0

7.5

2.0

8.5

ns

tsu

Set-up Time, HIGH or LOW
An or Bn to LEBA or LEAB

3.0

-

3.0

-

2.0

-

2.0

-

ns

tH

Hold lime, HIGH or LOW
An or Bn to LEBA or LEAB

2.0

-

2.0

-

2.0

-

2.0

-

ns

tw

LEBA or LEAB Pulse Width LOW

5.0

-

5.0

-

5.0

-

5.0

-

ns

NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

25131b107

II

6.19

5

IDTS4f74FCTS43T/AT
FAST CMOS OCTAL LATCHED TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

o--e 7.0V

Vcc

soon

DEFINITIONS:

26131bIOS

CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
IN
PUT

zzt

j

~

PULSE WIDTH

_____--110

-= ~~V
-

OV

-

3V

tsu----t'l4--~

TIMING
INPUT

-~------

-

lOWHIG~Ul~S~

1.5V
OV

ASYNCHRONOUS CONTROL
PRESET - - - - - - - - , I--+---~-------­ - 3V
- - t - - - - - - - 1.5V
CLEAR
- OV
ETC.

=t-

HIGH-laW-HIGH

_

~ 15V
"

--1.5V

PULSE

SYNCHRONOUS CONTROL
CLOCK

:~~~~~ vvJr
~tsu

-

J

,,",-...JIoI:.....lOllt....lo.

ETC.

3V

-1.5V
OV

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

SAME PHASE
INPUT TRANSITION

OV
3.5V

_----....." +- VOH
OUTPUT

DISABLE
__-----3V

-1.5V

VOL

VOL

OPPOSITE PHASE
INPUT TRANSITION

OV

'------- - - - - OV

NOTES

2613drw05

1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate S 1.0 MHz; Zo s son; tF s 2.Sns;
tR S 2.Sns.

6.19

6

IDT54f74FCT543T/AT
FAST CMOS OCTAL LATCHED TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

X

----

FCT

Temperature
Range

xxxx

X

X

Device
Type

Package

Process

G~lank
P
D
'--_ _ _ _ _ _ _~ L
SO
E

J

Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC
CERPACK
Plastic Leaded Chip Carrier

543T

Octal Registered Transceiver
Fast Octal Registered Transceiver

54
74

-55°C to +125°C
0° to +70°C

'-------------~ 543AT

L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- j

Commercial
MIL-STD-883, Class B

2613 drw 04

II

6.19

7

~

FAST CMOS OCTAL D
REGISTERS (3-STATE)

Integrated Device Technology, Inc.

I DT54/74 FCT646T/AT/CT
I DT54/74 FCT648T/AT/CT
IDT54/74FCT651 TI AT/CT
IDT54/74FCT652TI AT/CT

FEATURES:

DESCRIPTION:

• IDT54/74FCT646T/648T/651T/652T equivalent to
FASTTM speed
• IDT54/74FCT646AT/648AT/651AT/652AT 30% faster
than FAST"• IDT54/74FCT646CT/648CT/651CT/652CT 40% faster
than FAST"• Independent registers for A and B buses
• Multiplexed real-time and stored data
• Choice of true and inverting data paths
• IOL = 64mA (commercial), 48mA (military)
• CMOS power levels
• TTL input and output level compatible
• Available in 24-pin (300 mil) CERDIP, plastic DIP, SOIC,
CERPACK, 28-pin LCC and PLCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The I DT54/74 FCT646/648T/AT/CT and IDT54/74FCT6511
652T/AT/CT consist of a bus transceiver with 3-state D-type
flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal
storage registers.
The '651/652 utilize GAB and GBA signals to control the
transceiver functions. The '646/648 utilize the enable control
(<:3) and direction (DIR) pins to control the transceiver functions.
SAB and SBA control pins are provided to select either real
time or stored data transfer. The circuitry used for select
control will eliminate the typical decoding glitch that occurs in
a multiplexer during the transition between stored and realtime data. A low input level selects real-time data and a high
selects stored data.
Data on the A or B data bus, or both, can be stored in the
internal 0 flip-flops by low-to-high transitions at the appropriate clock pins (CPAB or CPBA), regardless of the select or
enable control pins.

FUNCTIONAL BLOCK DIAGRAM

SBA--------~------~

CPAB
SAB -------+-~__i

646/652
ONLY

1 OF 8 CHANNELS

2634 cnv' 01

646/652
ONLY

TO 7 OTHER CHANNELS

CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of Fairchild Semiconductor, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©t990 Integrated Device Technology, Inc.

6.20

JUNE 1990
DSC-42231·

1

IDT54f74FCT646/648/651/652TIATICT
FAST CMOS OCTAL TRANSCEIVER/REGISTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

Vee

CPA8
SA8
DIR
A1
A2
A3
A4
As
A6
A7
A8
GND

IDT54/74FCT646T/648T

co

«

~~o:o 8~;ii

INDEX

cU)oz >oU)

CP8A
S8A

I

"

II

I I

I I I I

I I

I

'4~'t1282726

G

:]5
:]6

25[:
24[:
23[:
:]7
J28-1
:]8
22[:
&
:]9
21[:
L28-1
:]10
20[:
:]11
19[:
12131415161718

81
82
83
84
85
86
87
88

G
81
82
NC
83
84
85

nnnnnnn
. . . coco co . . .

2634 cnv' 02

K9

~

I I I I I
L-A L-A I

3

()

~

-

~

:J 4
:J 5
:J 6

P20-1
020-1
S020-2
&
E20-1

DIP/SOIC/CERPACK
TOP VIEW

Pin Names
GBA. GAB

co

INDEX

Vee

GAB

PT

Power Dissipatior

0.5

0.5

W

lOUT

DC Output
Current

120

120

mA

NOTES:

2563 tbl 03

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +O.5V unless otherwise noted.
2. Input and Vcc terminals only.
3. Outputs and 1/0 terminals only.

CAPACITANCE

(TA = +25°C, f =

Parameter(1)

1.0MHz)

Conditions

Ty~.

Max.

Unit

CIN

Input
Capacitance

VIN = OV

6

10

pF

ClIO

I/O
Capacitance

VOUT= OV

8

12

pF

Symbol

NOTE:

2563tbl04

1. This parameter is measured at characterization but not tested.

6.21

2

I

IDT54n4FCT620/623T/AT/CT
FAST CMOS OCTAL BUS TRANSCEIVERS (3-STATE)

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vee = 5.0V ± 5%; Military:

TA

Min.

Typ.(2)

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

Vil

Input LOW Level

Guaranteed Logic LOW Level

-

-

0.8

V

IIH

Input HIGH Current

Vee = Max.

-

-

5

~A

lil

Input LO'vV Current

Test Condltlons(l)

Parameter

Except 110 Pins
I/O Pins

-

-

15

Vee = Max.

Except I/O Pins

-

-

-5

VI = O.5V

I/O Pins

-

-

-15

II

Input HIGH Current

Vee = Max., VI = Vee (Max.)

VIK

Clamp Diode Voltage

Vee = Min., IN = -18mA

los

Short Circuit Current

Vee = Max.(3), Vo= GND

10FF

Power Down Disable

Vee = GND, VA = 4.5V

VOH

Output HIGH Voltage
(A and B Bus)

Vee = Min.
VIN = VIH or Vil

Val

Output LOW Voltage (A Bus)

Vee = Min.
VIN = VIH or Vil

Val

Output LOW Voltage (B Bus)

Vee = Min.
VIN = VIH or Vil

VH

Input Hysteresis

Icc

Quiescent Power Supply Current

Max.

VI = 2.7V

-60

Unit
V

~A

~A

20

-0.7

-1.2

V

-120

-225

mA
~A

-

-

100

10H = -6mA MIL.
10H = -8mA COM'L.

2.4

3.3

-

V

10H = -12mA MIL.
10H = -15mA COM'L.
10l = 32mA MIU4)
10l = 48mA COM'L.
10l = 48mA MIU 4)

2.0

3.0

-

V

-

0.3

0.5

V

-

0.3

0.55

V

-

200

-

mV

-

0.2

1.5

mA

10l = 64mA COM'L.

Vee = Max., VIN = GND or Vee

NOTES:

1.
2.
3.
4.

= -55°C to +125°C, Vee = 5.0V ± 10%

VIH

Symbol

2563tb105

For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
These are maximum IOL values per output, for 8 outputs turned on simultaneously. Total maximum IOL (all outputs) is 512mA for commercial and 384mA
for military. Derate IOL for number of outputs exceeding 8 furned on simultaneously.

6.21

3

IDT54174FCT620/623TIATICT
FAST CMOS OCTAL BUS TRANSCEIVERS (3.STATE)

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol
~Iee

IceD

Test Condltlons(1)

Parameter
Quiescent Power Supply Current
TTL Inputs HIGH

Vee = Max.
VIN = 3.4V(3)

Dynamic Power Supply
Current(4)

Vee = Max.
Outputs Open
GBA = GAB = GND

Typ.(2)

Max.

Unit

-

0.5

2.0

rnA

0.15

0.25

Min.

= Vee
= GND

-

VIN

VIN
VIN

= Vee
= GND

-

1.7

4.0

VIN

= 3.4V
= GND

-

2.0

5.0

VIN
VIN
VIN

= Vee
= GND

-

3.2

6.5(5)

= 3.4V
= GND

-

5.2

14.5(5)

VIN

mAl
MHz

One Input Toggling
50% Duty Cycle
Ie

Total Power Supply Curren~6)

Vee = Max.
Outputs Open

fi

rnA

= 10MHz

50% Duty Cycle
GBA = GAB = GND
One Bit To~gling
Vee = Max.
Outputs Open

fi

= 2.5MHz

50% Duty Cycle
GBA = GAB = GND

VIN
VIN

Eight Bits Toggling
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcP/2 + fiNi)
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (V IN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.21

2563 tbl 06

I

4

IDT54174FCT620/623T/AT/CT
FAST CMOS OCTAL BUS TRANSCEIVERS (3-STATE)

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT620T/AT/CT
54174FCT620T
Com'l.
Symbol

Parameter

tPLH
tPHL

Propagation Delay
An to Bn

tPLH
tPHL

Propagation Delay
8n to An

tPZH
tPZL

GBAtoAn

tPHZ
tPLZ

Conditlon(1)
CL

= 50pF
= 500n

5417 4FCT62OA T

Mil.

Com'l.

54174FCT620CT

Mil.

Com'l.

Mil.

Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
1.5

7.0

1.5

8.0

1.5

5.2

1.5

6.0

1.5

4.5

1.5

5.1

ns

1.5

7.0

1.5

8.0

1.5

5.2

1.5

6.0

1.5

4.5

1.5

5.1

ns

1.5

9.0

1.5

10.0

1.5

7.0

1.5

8.0

1.5

6.1

1.5

6.9

ns

Output Disable Time
GBAtoAn

1.5

8.0

1.5

9.0

1.5

6.5

1.5

7.4

1.5

5.6

1.5

6.4

ns

tPZH
tPZL

Output Enable Time
GAB to Bn

1.5

9.0

1.5

10.5

1.5

7.0

1.5

8.0

1.5

6.1

1.5

6.9

ns

tPHZ
tPLZ

Output Disable Time
GAB to Bn

1.5

8.0

1.5

9.0

1.5

6.5

1.5

7.4

1.5

5.6

1.5

6.4

RL

Output Enablo Time

ns

2563tb107

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT623T/AT/CT
54174FCT623T
Com'l.
Symbol

Parameter

tPLH
tPHL

Propagation Delay
An to Bn

tPLH
tPHL

Conditlon(1)
CL = 50pF

5417 4FCT623AT

Mil.

Com'l.

54174FCT623CT

Mil.

Com'l.

Mil.

Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
1.5

7.5

1.5

9.0

1.5

5.5

1.5

6.3

1.5

4.8

1.5

5.4

ns

Propagation Delay
Bn to An

1.5

7.5

1.5

9.5

1.5

5.5

1.5

6.3

1.5

4.8

1.5

5.4

ns

tPZH
tPZL

Output Enable Time
GBAtoAn

1.5

9.0

1.5

10.0

1.5

7.0

1.5

8.0

1.5

6.1

1.5

6.9

ns

tPHZ
tPLZ

Output Disable Time
GBAtoAn

1.5

8.0

1.5

9.0

1.5

6.5

1.5

7.4

1.5

5.6

1.5

6.4

ns

tPZH
tPZL

Output Enable Time
GAB to Bn

1.5

9.0

1.5

10.5

1.5

7.0

1.5

8.0

1.5

6.1

1.5

6.9

ns

1.5

9.0

1.5

6.5

1.5

7.4

1.5

5.6

1.5

6.4

ns

RL = soon

tPHZ
Output Disable Time
1.5 8.0
tPLZ
GAB to Bn
NOTES:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays

6.21

2563tbl08

5

IOT54174FCT620/623TIATICT
FAST CMOS OCTAL BUS TRANSCEIVERS (3-STATE)

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
o-e 7.0V

Vee

soon

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
25631b109
CL = Load capacitance: indudes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

PULSE WIDTH

-= ~~V

l

__..K...x~ -

OV

tsu~>I4--~

- 3V
- - - i r - - - - - - - 1.SV

TIMING
INPUT

-

LOW-HIG~J~s~

OV

ASYNCHRONOUS CONTROL
PRESET - - - - - - - - , I--+---~-------­ - 3V
CLEAR
- - r - - - - - 1.SV
- OV
ETC. - - - - - - - "
SYNCHRONOUS CONTROL
CLOCK

:~~~~~ vvJr
J
~tsu

__

..K...x~

=t-

HIGH-LOW-HIGH
PULSE

~ 15V
--l.SV

Iw

- 3V
-l.SV
- OV

ETC.

PROPAGATION DELAY

ENABLE

SAME PHASE
INPUT TRANSITION

DISABLE

)--'+----OV

_----_.+-OUTPUT

I

ENABLE AND DISABLE TIMES

OV

3.SV
VOH

-l.SV

VOL

VOL
OUTPUT SWITCH

VOH

NORM~~~ OPEN

OPPOSITE PHASE
INPUT TRANSITION
' - -_ _..I - - - -

OV

OV

NOTES
2563 drw 05
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate $ 1.0 MHz; Zo $ son; tF $ 2.5ns;
tR $ 2.5ns.

6.21

6

IDT54174FCT620/623T/AT/CT
FAST CMOS OCTAL BUS TRANSCEIVERS (3-STATE)

ORDERING INFORMATION
IDT=--_X=X_ _ FCT -=--:-X_X-=XX=--_
Temp. Range
Device Type

x

x

Package

Process

y~lank
P

D
~----

________~SO

L
E
620T
623T
620AT

~----------------------~623AT

620CT
623CT

154

~----------------~174

Commercial
MIL-STD-883. Class B
Plastic DIP
CERDIP
Small Outline Ie
Leadless Chip Carrier
CERPACK
Octal Bus Transceiver (Inverting)
Octal Bus Transceiver (Non-Inverting)
Fast Octal Bus Transceiver (Inverting)
Fast Octal Bus Transceiver (Non-Inverting)
Super Fast Octal Bus Transceiver (Inverting)
Super Fast Octal Bus Transceiver (Non-Inverting)
-55°C to +125°C
O°C to +70°C
2563 cnv' 10

6.21

7

G®

IDT54/74FCT621T/AT
IDT54/74FCT622T/AT

FAST CMOS
OCTAL BUS TRANSCEIVER
(OPEN DRAIN)

Integr.ated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• IDT54/74FCT621T/622T equivalent to FASTTM speed
• IDT54174FCT621AT/622AT 25% faster than FASTTM
speed
• Equivalent to FASTTM output drive over full temperature
and voltage supply extremes
• IOL = 64mA (commercial) and 48mA (military)
• CMOS power levels (1 mW typo static)
• TIL input and output level compatible
• Substantially lower input current levels than FASl"TM
(5J.LA max.)
• Power Down Disable feature
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT621 T/AT is an octal transceiver with
non-inverting Open-Drain bus compatible outputs in both
send and receive directions. The B bus outputs are capable
of sinking 64mA providing very good capacitive drive
characteristics. These octal bus transceivers are designed for
asynchronous two-way communication between data buses.
The control function implementation allows for maximum
flexibility in timing. The IDT54174FCT622T/AT is the inverting
option of the '621.

FUNCTIONAL BLOCK DIAGRAM (1)

PIN CONFIGURATIONS

GBA

A1

Vee

GAB
A1
A2
A3
A4
As
A6
A7
Aa
GND

GAB

B1

19
1S
5
7
a
9
10

P20-1,
D20-1,
S020-2,

GBA
B1
B2
B3
B4
B5
B6
B7
Ba

17

16
15
14
13
12
11

&

E20-1

II

DIP/SOIC/CERPACK
TOP VIEW

A2-As

co u

<

C\I~«uCO

INDEX

B2-Bs

«I(!)

L-J'-'UL-JL-J
3 2
20 19
7 Other Transceivers

A3
A4
As
A6
A7

2538 drw 01

FCT621T
NOTE:
1. The FCT622T is the inverting option of FCT621 T.

]
]
]
]
]

4
5
6
7
a

1a
17
L20-2
16
15
14
9 10 11 12 13
r - , , - , r-1 ,.., ro
1

~~rom~

[
[
[
[
[

B1
B2
B3
B4
B5

2538 drw 02

105
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. This test is performed with outputs preconditioned to the low state. lee with outputs preconditioned to the high state is guaranteed when the outputs
are forced to Vec or GND.
4. These are maximum IOl values per output, for 8 outputs turned on simultaneously. Total maximum IOl (all outputs) is 512mA for commercial and
384mA for military. Derate IOl for number of outputs exceeding 8 turned on simultaneously.

I

6.22

3

IDT54174FCT621T/AT, IDT54174FCT622T/AT
FAST CMOS OCTAL BUS TRANSCEIVER (OPEN DRAIN)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol

Test Condltlons(l)

Parameter

Min.

Typ.(2)

Max.

Unit

-

0.5

2.0

rnA

t\lee

Quiescent Power Supply Current
TIL Inputs HIGH

Vee = Max.
VIN = 3.4v(3)

IceD

Dynamic Power Supply Current(4)

Vee = Max.
Outputs Open
GBA = GAB = GND or Vee
One Input Toggling
50% Duty Cycle

VIN = Vee
VIN = GND

-

0.15

0.25

rnA/MHz

Ie

Total Power Supply Current(6.7)

Vee = Max.
Open
GBA = GAB = GND or Vee
One Bit Toggling
at fi =10MHz
50% Duty Cycle

VIN = Vee
Vir~ =GND

-

1.7

4.0

rnA

VIN =3.4V
VIN =GND

-

2.0

5.0

Vee = Max.
Outputs Open
GBA = GAB = GND or Vee
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle

VIN = Vee
VIN = GND

-

3.2

6.5(5)

VIN = 3.4V
VIN = GND

-

5.2

14.5(5)

Output~

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + t.lcc DHNT + ICCD (fcp/2 + fiNi)
Icc = Quiescent Current
t.lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
7. This test is performed with outputs tied to GND through a pull-down resistor.

6.22

25381b1 04

4

IDT54174FCT621T/AT, IDT54174FCT622T/AT
FAST CMOS OCTAL BUS TRANSCEIVER (OPEN DRAIN)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE-IDT54n4FCT621T/AT
IDT54/74FCT621 AT

IDT54/74FCT621 T
Com'l.
Symbol

Parameter

Cond it lon(1 I

MinPI Max.

Mil.
MinPI Max.

Com'l.
Mil.
Mln.(2) Max. Min.(21 Max.

Unit

5.5
1.5

13.0
8.5

5.5
1.5

13.5
9.5

5.5
1.5

12.0
6.8

5.5
1.5

12.5
7.6

ns

Propagation Delay B to A

5.5
1.5

12.5
8.0

5.5
1.5

13.0
9.0

5.5
1.5

12.0
6.4

5.5
1.5

12.5
7.2

ns

tPLH
tPHL

Propagation Delay GBA to A

5.5
1.5

14.0
8.5

5.5
1.5

14.5
9.5

5.5
1.5

13.0
6.8

5.5
1.5

13.5
7.6

ns

tPLH
tPHL

Propagation Delay GAB to B

5.5
1.5

14.0
8.0

5.5
1.5

14.5
9.0

5.5
1.5

13.0
6.4

5.5
1.5

13.5
7.2

ns

tPLH
tPHL

Propagation Delay A to B

tPLH
tPHL

CL = 50pF
RL = 5000.

SWITCHING CHARACTERISTICS OVER OPERATING RANGE-IDT54n4FCT622T/AT
IDT54/74FCT622AT

IDT54/74FCT622T
Com'l.
Symbol

Parameter

tPLH
tPHL

Propagation Delay A to B

tPLH
tPHL

Condition(1)

= 50pF
= 5000.

MinPI Max.

Mil.
Min.(2) Max.

Com'l.
Min.(2)

Mil.

Max. MinPI Max.

Unit

5.5
1.5

13.5
8.0

5.5
1.5

14.0
9.5

5.5
1.5

12.0
6.0

5.5
1.5

12.5
7.0

ns

Propagation Delay B toA

5.5
1.5

12.5
8.0

5.5
1.5

13.0
9.5

5.5
1.5

12.0
5.5

5.5
1.5

12.5
6.5

ns

tPLH
tPHL

Propagation Delay GBA to A

5.5
1.5

12.5
10.0

5.5
1.5

13.0
11.5

5.5
1.5

11.5
7.0

5.5
1.5

12.0
8.5

ns

tPLH
tPHL

Propagation Delay GAB to B

6.0
1.5

12.5
9.5

6.0
1.5

13.0
11.0

6.0
1.5

11.5
6.5

6.0
1.5

12.0
7.5

ns

CL
RL

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

25381b107

I

6.22

5

IDT54f74FCT621T/AT, IDT54f74FCT622T/AT
FAST CMOS OCTAL BUS TRANSCEIVER (OPEN DRAIN)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

D[rlNITlm~5:

2~3!l1tl1 O!l

CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt·

PULSE WIDTH

-=

l
tsu --t>l+---+l

~..x.....JIioI~ -

nV

OV

6V

TIMING
INPUT _ _ _ _ _ _- '

- 3V
V
_

lOW-HIG~Ul&~

ASYNCHRONOUS CONTROL
PRESET - - - -.....
CLEAR
ETC. - - - - - '
SYNCHRONOUS CONTROL
CLOCK

-

3V

-

1.5V
OV

-

3V

--+------

:~~t~~ vvY
~tsu
J

~..x._~

ETC.

=t-

HIGH-lOW-HIGH
PULSE

__

1.SV

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

-J'+_ _ _ _ OV

OV
3.SV

_------I.+-VOH
OUTPUT

IW

-1.5V
- OV

PROPAGATION DELAY

SAME PHASE
INPUT TRANSITION

~ 15V

-1.SV

VOL

VOL
VOH
OPPOSITE PHASE
INPUT TRANSITION

OV
- - - - - ' - - - - OV
NOTES
2538 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate $ 1.0 MHz; Zo $ son; tF $ 2.Sns;
tR $ 2.Sns.

6.22

6

IDT54174FCT621T/AT, IDT54174FCT622T/AT
FAST CMOS OCTAL BUS TRANSCEIVER (OPEN DRAIN)

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xx
Temperature
Range

FCT

x

x

x

Device
Type

Package

Process

~glank
P
D
' - - - - - - - - - - 1 SO
L
E
621 T
621AT
622T
622AT

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Octal Bus Transceiver
Fast Octal Bus Transceiver
Octal Bus Transceiver (Inverting)
Fast Octal Bus Transceiver (Inverting)

2538 drw 03

I

6.22

7

~

IDT54/74FCT821 ATIBT/CT
IDT54/74FCT823ATIBT/CT
IDT54/74FCT825AT/BT/CT

HIGH-PERFORMANCE
CMOS BUS INTERFACE
REGISTERS

Integrated Devlc.e Technology, Inc..

FEATURES:
•
•
•

•
•
•
•
•
•

•
•
•
•

DESCRIPTION:

IDT54/74FCT821AT/823AT/825AT equivalent to FASliM
speed and drive
IDT54174FCT821 BT/823BT/825BT upto 30% fasterthan
FASTTM
IDT54174FCT821 CT/823CT/825CTupto50%fasterthan
FASTTM
Equivalent to AMD's Am29821-25 bipolar registers in
pinout/function, speeds and output drive over full temperature and voltage supply extremes
High-speed parallel registers with positive edge-triggered
D-type flip-flops
Buffered common Clock Enable (EN) and asynchronous
Clear input (CLR)
IOL = 48mA (commercial) and 32mA (military)
Clamp diodes on all inputs for ringing suppression
CMOS power levels (1 mW typo static)
True TTL input and output compatibility
- VOH = 3.3V (typ.)
- VOL = O.3V (typ.)
Substantially lower input current levels than AMD's bipolar
Am29800 series (5~ max.)
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
Meet or exceed JEDEC Standard 18 specifications

The IDT54/74FCT800AT/BT/CT series is built using
advanced CEMOSTM , a dual metal CMOS technology.
The IDT54/74FCT820 series bus interface registers are
designed to eliminate the extra packages required to buffer
existing registers and provide extra data width for wider
address/data paths or buses carrying parity. The IDT541
74FCT821 AT/BT/CT are buffered, 1O-bit wide versions of the
popular '374 function. The IDT541 74FCT823AT/BT/CT are
9-bit wide buffered registers with Clock Enable (EN) and Clear
(CLR) - ideal for parity bus interfacing in high-performance
microprogrammed systems. The I DT54/74 FCT825AT/BT/CT
are 8-bit buffered registers with all the '823 controls plus
multiple enables (OE1, OE2, OE3) to allow multiuser control
of the interface, e.g., CS, DMAand RD/WR. They are ideal for
use as an output port requiring high IOLlIOH.
All of the IDT54/74FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in high impedance
state.

FUNCTIONAL BLOCK DIAGRAM

Yo

Y,

Y3

Y2

Y4

Ys

Yn

Yn·'

2567 drw 01

CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark 01 Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
((:>1990 Integrated Device Technology, Inc.

6.23

JUNE 1990
DSC-4202/·

1

IDT54174FCT821/823/825AT/BT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

LOGIC SYMBOLS

IDT54/74FCT821T 10-BIT REGISTER

Vee

OE
Do
Dl
D2
D3
D4
Ds
Ds
D7
Ds
D9
GND

INDEX

~ol.UO 8o~

>>->-

oOlQz

Yo
Yl
Y2
Y3
Y4
Ys
Ys
Y7
Ys
Y9
CP

I 1111

D2
D3
D4
NC
Ds
Ds
D7

II

I111111

'4 '3' '2' 1-11 28 27 26

:]5
25 [:
:]6
24[:
:]7
23[:
:]8
L28-1
22[:
:]9
21 r:
:]10
20[:
:]11
19[:
12131415161718

Y2
Y3
Y4
NC
Ys
Ys
Y7

D~D

CP

CP-----1

Q~10
I

I

Y

DE ------------~

nnnnnnn

2567 en ... • 02

iSo~§E~~~
(!)

LCC
TOP VIEW

DIP/SOIC/CERPACK
TOP VIEW
IDT54174FCT823T 9-BIT REGISTER
OE
Do
Dl
D2
D3
D4
Ds
Os
07
Os
CLR
GND

Vee
Yo
Y1
Y2
Y3
Y4
Ys
Ys
Y7
Ys
EN
CP

INDEX
11111

D2
D3
04
NC
05
Os
07

~5

II

I111111

'4'3''2'1 282726

25C
24[:
23[:
:]7
:]8
22[:
L28-1
:]9
21[:
:]10
20[:
:]11
19[:
12131415161718
:]6

Y2
Y3
Y4
NC
Ys
Ys
Y7

D

Y

CP
EN
CLR

DE

nnnnnnn

is I~ f@

g ~ laJ ~

O(!)

LCC
TOP VIEW

DIP/SOIC/CERPACK
TOP VIEW

IDT54/74FCT825T 8-BIT REGISTER
OEl
OE2
Do
Dl
D2
D3
D4
Ds
Qs
07
CLR
GNO

Vee
OE3
Yo
Y1
Y2
Y3
Y4
Ys
Ys
Y7
EN
CP

INDEX

M

0

I II II

01
D2
03
NC
04
05
Os

II

:]5
25[:
:]6
24[:
:]7
23[:
:]8
22[:
L28-1
:]9
21[:
:]10
20[:
:]11
19[:
12131415161718

nnnnnnn

I

O(!)

0Z

0

I11111 I

'4'3''2'1 282726

Ci ....JZ
a: 0
DlP/SOIC/CERPACK
TOP VIEW

u

~

N

wO
81 wo lOz
>u~ >-

~

Yl
Y2
Y3
NC
Y4
Ys
Ys

Y

CP
EN
CLR
OEl

DE2
OE3

2567 en... • 04

IZw :>:

LCC
TOP VIEW
6.23

2

IOT54174FCT821/823/825ATIBT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TAB LE(1)

PIN DESCRIPTION .
Names

1/0

Description

DI

I

The D flip-flop data inputs.

CLR

I

When the clear input is LOW and OE is
LOW, the 01 outputs are LOW. When
the clear input is HIGH, data can be
entered into the reQister.

CP

I

Clock Pulse for the Register; enters
data into the register on the LOW-toHIGH transition,

YI

a

The register three-state outputs.

EN

I

Clock Enable. When the clock enable is
LOW, data on the DI input is transferred
to the 01 output on the LOW-to-HIGH
clock transition. When the clock enable
is HIGH, the 01 outputs do not change
state, regardless of the data or clock
input transitions.

OE

I

Internal!
Out Juts

Inputs
OE

CLR

EN

01

CP

QI

VI

Function

H
H

H
H

L
L

L
H

i
i

L
H

Z
Z

High Z

H
L

L
L

X
X

Z
L

Clear

H
H

H
H

X
X
X
X

L
L

H
L

X
X
X
X

NC
NC

Z
NC

Hold

H
H
L
L

H
H
H
H

L
L
L
L

L
H
L
H

i
i
i
i

L
H
L
H

Z
Z
L
H

Load

I

NOTE:
1. H = HIGH
L=LOW
X = Don't Care
NCe' No Change
i = LOW-to-HIGH Transition
Z = HIGH-impedance

Output Control. When the OE input is
HIGH, the YI outputs are in the high
impedance state. When the OE input is
LOW, the TRUE register data is present
at the YI outputs.

2567 tbl 03

2567 tbl 02

ABSOLUTE MAXIMUM 'RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND

CAPACITANCE

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

(TA = +25°C, f = 1.0MHz)

Parameter(1)

Conditions

Typ.

Max.

Unit

CIN

Input
Capacitance

VIN = OV

6

10

pF

COUT

Output
Capacitance

VOUT= OV

8

12

pF

Symbol

NOTE:
1. This parameter is measured at characterization but not tested.

TA

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65to +150

°C

25671bl05

PRODUCT SELECTOR GUIDE
Device
10-Bit

PT

Power Dissipatior

0.5

0.5

W

lOUT

DC Output
Current

120

120

mA

9-Bit
8-Bit
I
I
54/74FCT821 AT/BT/CTI 54/74FCT823AT/BT/CTI 54/74FCT825ATI BT/CT
25671bIOl

NOTES:
25671bl04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device, This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vec by +O.5V unless otherwise noted.
2. Input and Vcc terminals only.
3. Outputs and 110 terminals only.

6.23

3

IDT54f74FCT821/823/825AT/BT/CT
HIGH·PERFORMANCE CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to + 125°C, Vcc = 5.0V ± 10%
Test Condltlons(1)

Svmbol
VIH

Parameter
Input HIGH Level

Guaranteed Logic HIGH Level

Vil

Input LOW Level

Guaranteed Logic LOW Level

IIH

Input HIGH Current

Vee = Max.

VI = 2.7V

ilL

Input LOW Current

Vee = Max.

10ZH

High Impedance Output Current

Vee = Max.

II

Input HIGH Current

Vee = Max., VI = Vee (Max.)

VIK

Clamp Diode Voltage

Vee = Min., IN = -1SmA

-

los

Short Circuit Current

Vee = Max.(3), Vo= GND

VOH

Output HIGH Voltage

Vee = Min.
VIN = VIH or Vil

10Zl

VOL

Output LOW Voltage

VH

Input Hysteresis

Icc

Quiescent Power Supply Current

Vee = Min.
VIN = VIH or Vil

Vee = Max.
VIN = GND or Vee

Min.
2.0

Tvp.(2)

Max.

Unit
V

-

-

O.S

V

-

-

5

Il A

VI = 0.5V

-

-5

Vo= 2.7V

-

-

Il A
Il A

VO= 0.5V

-

-

-10

-

-

10

20

Il A

-0.7

-1.2

V

-60

-120

-225

mA

10H = -6mA MIL.
10H = -SmA COM'L.
10H = -12mA MIL.
10H = -15mA COM'L.

2.4

3.3

-

V

2.0

3.0

-

V

10l = 32mA MIL.
10l = 4SmA COM'L.

-

0.3

0.5

V

-

200

-

mV

0.2

1.5

mA

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

2567tbl06

II

6.23

4

IOT54174FCT821/823/825ATIBT/CT
HIGH·PERFORMANCE CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLV CHARACTERISTICS
Symbol

leeo

Ie

Total Power Supply Curren~6)

L'1lee

Test Conditions(1)

Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Curren~4)

Vee = Max.
VIN = 3.4V(3)

Min.

Typ.(2)

Unit

Max.

-

0.5

2.0

mA

Vee = Max.
Outputs Open
OE= EN = GND
One Input Toggling
50% Duty Cycle

VIN = Vee
VIN = GND

-

0.15

0.25

mAl
MHz

Vee = Max.
Outputs Open
fep= 10MHz
50% Duty Cycle

VIN = Vee
VIN =GND

-

1.7

4.0

mA

OE= EN = GND
One Bit Toggling
at fi = 5MHz
50% Dutv Cvcle

VIN =3.4V
VIN =GND

-

2.2

6.0

Vee = Max.
Outputs Open
fep= 10MHz
50% Duty Cycle

VIN = Vee
VIN =GND

-

4.0

7.8(5)

OE= EN = GND
Eight Bits Toggling
at fi = 2.5MHz
50% Dutv Cycle

VIN = 3.4V
VIN = GND

-

6.2

16.8(5)

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + t.lcc DHNT + ICCD (fCP/2 + fiNi)
Icc = Quiescent Current
t.lcc = Power Supply Current for a TTL High Input (V IN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic CUrrent Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Numberof Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.23

2567tbl07

5

IOT54174FCTB21/B23/B25ATIBT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT821AT-825AT
Com'l.

Test
Symbol

tPLH
tPHL

tsu

Parameter

Propagation Delay
CP to Y i (OE = LOW)

Set-up Time HIGH or LOW
D ItoCP

IDT54/74FCT8218T-8258T
Com'l.

Mil.

Condltlons(1) Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. MlnP

= SOpF
RL = soon
CL = 300pF(3)
RL = soon
CL = SOpF
RL = soon
CL

IDT54/74FCT821 CT -825CT
Com'l.

Mil.

Max. Min.(2

Mil.

Max. Mln.(2 Max.

Unit

ns

-

10.0

-

11.S

-

7.S

-

B.5

-

6.0

-

7.0

-

20.0

-

20.0

-

1S.0

-

16.0

-

12.S

-

13.S

4.0

-

4.0

-

3.0

-

3.0

-

3.0

-

3.0

-

ns

tH

Hold Time HIGH or LOW

2.0

-

2.0

-

1.S

-

1.S

-

1.S

-

1.S

-

ns

tsu

Set-up Time HIGH or LOW
EN to CP

4.0

-

4.0

-

3.0

-

3.0

-

3.0

-

3.0

-

ns

tH

Hold Time HIGH or LOW
EN to CP

2.0

-

2.0

-

0

-

0

-

0

-

0

-

ns

D ItoCP

tPHL

Propagation Delay, CLR to

-

YI

tREM
tw

Recovery Time CLR to CP
Clock Pulse Width
HIGH or LOW

tw

CLR Pulse Width
LOW

tPZH
tPZL

tPHZ
tPLZ

Output Enable Time OE
tOYI

CL = SOpF
RL = soon
CL = 300pF(3)

Output Disable Time OE

RL = soon
CL = SpF(3)

tOYI

RL

= soon
CL = 50pF

RL =

soon

14.0

-

1S.0

-

9.0

-

9.5

-

8.0

-

8.S

ns

6.0

-

7.0

-

6.0

-

6.0

-

6.0

-

6.0

-

ns

7.0

-

7.0

-

6.0

-

6.0

-

6.0

-

6.0

-

ns

6.0

-

7.0

-

6.0

-

6.0

-

6.0

-

6.0

-

ns
ns

-

12.0

-

13.0

-

B.O

-

9.0

-

7.0

-

8.0

-

23.0

-

2S.0

-

1S.0

-

16.0

-

12.S

-

13.S

-

7.0

-

B.O

-

6.S

-

7.0

-

6.2

-

6.2

-

B.O

-

9.0

-

7.S

-

B.O

-

6.S

-

6.S

NOTES:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This paramter is guaranteed but not tested.

ns

2567tbl09

6.23

6

I

IDT54174FCT821/823/825AT/BT/CT
HIGH·PERFORMANCE CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
256711>108
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

j
tsu -4'14--~

""-..K.....K~

PULSE WIDTH

-= ~~V

TIMING
INPUT

-

OV

LOW-HIG~UL&~

- 3V
V
_

6J

ASYNCHRONOUS CONTROL

-

PRESET - - - - , ~-+---+---CLEAR
ETC.
-

3V
1.SV
OV

=t-

HIGH-LaW-HIGH
PULSE

~ 15V

'~

-"--1.SV

SYNCHRONOUS CONTROL
CLOCK

:~~t~~ vvJr
j
~tsu
ETC.

- 3V
-1.SV
........-..... - OV

~..-..

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

3V
SAME PHASE
INPUT TRANSITION

OV
3.SV

OUTPUT

VOL
VOL
OUTPUT SWITCH
NORMALLY OPEN
HIGH

3V
OPPOSITE PHASE
INPUT TRANSITION
OV

VOH
OV

NOTES
2567 drw 05
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo s son; tF ~ 2.Sns;
tR ~ 2.Sns.

6.23

7

IOT54174FCT821/823/825AT/BT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT =--___
X=X_ _ FCT -=-..,.X_X-::XX,,-_
Temp. Range
Device Type

x

x

Package

Process

y~lank
P

D

L...-_ _ _ _ _ _-; E

L
SO
821AT
821BT
821CT
823AT
L...-------------;823BT
823CT
825AT
825BT
825CT

54

~-----------------------------------;74

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
1O-Bit Non-Inverting Register
Fast 10-Bit Non-Inverting Register
Super Fast 10-Bit Non-Inverting Register
9-Bit Non-Inverting Register
Fast 9-Bit Non-Inverting Register
Super Fast 9-Bit Non-Inverting Register
8-Bit Non-Inverting Register
Fast 8-Bit Non-Inverting Register
Super Fast 8-Bit Non-Inverting Register
-55°C to + 125°C
O°C to +70°C
2567 cnv· 10

II

6.23

8

t;)

HIGH-PERFORMANCE
CMOS BUFFERS

IDT54/74FCT827 AT/BT/CT
IDT54/74FCT828AT/BT/CT

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• Faster than AMD's Am29827-28 series
• Equivalent to AMD's Am29827-28 bipolar buffers in
pinout/function, speeds and output drive over full temperature and voltage supply extremes
• IDT54/74FCT827/828AT equivalent to FASl'M speed
• IDT54/74FCT827/828BT 35% faster than FASl'M
• IDT54/74FCT827/828CT 45% faster than FASl'M
• IOL = 48mA (commercial), and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1 mW typo static)
• True TTL input and output level compatible
• Substantially lower input current levels than AM D's
bipolar Am29800 series (5JlA max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT800AT/BT/CT series is built using
advanced CEMOSTM, a dual metal CMOS technology.
The IDT54/74FCT827AT/BT/CT and IDT54/74FCT828AT/BT/CT 10-bit bus drivers provide high-performance bus
interface buffering for wide data/address paths or buses
carrying parity. The 10-bit buffers have NAND-ed output
enables for maximum control flexibility.
All of the IDT54/74FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in high impedance
state.

FUNCTIONAL BLOCK DIAGRAM
IDT54/74FCT827AT/BT/CT/828AT/BT/CT 10-BIT BUFFERS

2573 cnv' 01

PRODUCT SELECTOR GUIDE
10-Bit Buffer

I Non-invertinq

IDT54/74FCT827 AT/BT/CT

Iinvertinq

IDT54/74FCT828AT/BT/CT

CEMOS is a trademark 01 Integrated Device Technology. Inc.
FAST is a trademark 01 Fairchild Semiconductor Co.

2573 tbl 01

MILITARY AND COMMERCIAL TEMPERATURE RANGES
Il:lt990 Integrated Device Technology. Inc.

6.24

JUNE 1990
DSC-42171·

1

IDT54f74FCTS27ATIBTICT, IDT54f74FCTS2SAT/BT/CT
HIGH-PERFORMANCE CMOS BUFFERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

LOGIC SYMBOL

PIN CONFIGURATIONS
INOEX

Vee
Yo
Yl
Y2
Y3
Y4
Ys
Ys
Y7
Ya

OEl

00
01
02
03
04

05
Os
07
Os

09

I

1.,1 II

I

10
>--r-YO-9

00-9----~

'! ~ ....1 282726

:]5
25[:
:]6
24E:
:]7
23E:
:]8
L28-1
22 E:
:]9
21 C:
Os :]10
20[:
07 :]11
19[:
12131415161718

Y9
OE2

GNO

II II'I

~

Y2
Y3
Y4
NC
Ys
Ys
Y7

GEl
GE2 _ _ _.q

nnnnnnn

rPClIOONClI->­

DlP/CERPACKlSOIC
TOP VIEW

C)
2573

LCC
TOP VIEW

cnv· 02-{)4

PIN DESCRIPTION
Names
OEI

Description

1/0

I

When both are LOW the outputs are
enabled. When either one or both are
HIGH the outputs are High Z.

01

I

1O-bit data input.

YI

0

1O-bit data output.
2573 tbl 02

FUNCTION TABLES
IDT54114FCT827 AT/BT/CT
(NON-INVERTING)(1 )
Inputs

IDT54/74FCT828AT/BT/CT (INVERTING)(1)

Output

Inputs

Output

OEl

OE2

01

VI

Function

OEl

OE2

01

YI

Function

L
L

L
L

L
H

L
H

Transparent

H

Transparent

X
H

X
X

Z
Z

Three-State

L
L
X
H

L
H

H
X

L
L
H
X

X
X

Z
Z

NOTE:
1. H = HIGH, L = LOW, X = Don't Care, Z

2573 tbl 03

= High-Impedance

L

NOTE:
1. H = HIGH, L = LOW, X = Don't Care, Z

6.24

Three-State
2573 tbl 04

= High-Impedance

2

II

IDT54f74FCT827AT/BT/CT,IDT54f74FCT828AT/BT/CT
HIGH-PERFORMANCE CMOS BUFFERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
RatlnQ
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND

CAPACITANCE

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

TA

Operating
Temperature

o to +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output
Current

120

120

rnA

(TA = +25°C, f = 1.0MHz)

Parameter(l)

Conditions

Typ.

Max.

Unit

CIN

Input
Capacitance

VIN = OV

6

10

pF

COUT

Output
Capacitance

VOUT = OV

S

12

pF

Symbol

NOTE:
1. This parameter is measured at characterization but not tested.

2573 tbl 06

NOTE:
25731b105
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vec by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 1/0 terminals only.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to + 125°C, Vcc = 5.0V ± 10%
Symbol

Test Condltlons(1)

Parameter

Min.

Typ.(2)

Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

V

Vil

Input LOW Level

Guaranteed Logic LOW Level

V

Input HIGH Current

Vee = Max.

VI = 2.7V

-

O.S

IIH

-

5

Il A

I Il

Input LOW Current

Vee = Max.

VI = 0.5V

-

-5

Il A

IOZH

High Impedance Output Current

Vee = Max.

Vo= 2.7V

-

-

10

Il A

lOll

Vo= 0.5V

II

Input HIGH Current

Vee = Max., VI = Vee (Max.)

-

VIK

Clamp Diode Voltage

Vee = Min., IN = -1SmA

-

los

Short Circuit Current

Vee = Max.<3), Vo= GND

VOH

Output HIGH Voltage

Vee = Min.
VIN = VIH or Vil

Val

Output LOW Voltage

VH

Input Hysteresis

Icc

Quiescent Power Supply Current

Vee = Min.
VIN = VIH or Vil

Vee = Max.
VIN = GND or Vee

-

20

Il A

-0.7

-1.2

V

":'60

-120

-225

mA

10H = -6mA MIL.
10H = -SmA COM'L.

2.4

3.3

-

V

10H = -12mA MIL.
10H = -15mA COM'L.

2.0

3.0

-

V

10l = 32m A MIL.
10l = 4SmA COM'L.

-

0.3

0.5

V

-

200

-

mV

-

0.2

1.5

mA

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vec = 5.0V, +25 c C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

6.24

-10

2573 tbl 07

3

IDT54f74FCT827AT/BT/CT, IDT54f74FCT828AT/BT/CT
HIGH·PERFORMANCE CMOS BUFFERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol
!llee
ieeD

Test Conditions(1)

Parameter
Quiescent Power Supply Current
TIL Inputs HIGH
Dynamic Power Supply Curren~4)

Vee = Max.
VIN = 3.4V(3)
Vee = Max.

VIN = Vee

Outputs Open
OEl = OE2 = GND

VIN = GND

Typ.!2)

Max.

Unit

-

0.5

2.0

rnA

-

0.15

0.25

Min.

mN
MHz

One Input Toggling
50% Dutv Cycle
Ie

Total Power Supply Curren~6)

Vee = Max.

VIN = Vee

Outputs Open

VIN =GND

-

1.7

4.0

-

2.0

5.0

-

3.2

6.5(5)

-

5.2

14.5(5)

rnA

fi = 10MHz
50% Duty Cycle
OEl = OE2 = GND

VIN = 3.4V
VIN =GND

One Bit Toqqlinq
Vee = Max.

VIN = Vee

Outputs Open

VIN = GND

fi = 2.5MHz
50% Duty Cycle
OEl = OE2 = GND

VIN = 3.4V
VIN = GND

Eiqht Bits Toqqlinq
NOTES:
1.
2.
3.
4.
5.
6.

2573 tbl DB

For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 5.0V, +25°C ambient.
Per TIL driven input (V IN = 3.4V); all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fiN i)
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
IcCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
f i = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.24

4

IDT54174FCT827AT/BT/CT, IDT54174FCT828AT/BT/CT
HIGH·PERFORMANCE CMOS BUFFERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT827AT·
828AT
Symbol
tPLH
tPHL

Parameter
Propagation Delay
DltoYI
IDT54/74FCT827T
(Non·inverting)

tPLH
tPHL

Propagation Delay
DltoYI
IDTS4/74FCT828T
(Inverting)

tPZH
tPZL

tPHZ
tPLZ

Output Enable Time
OEltoYI

Output Disable Time
OEltoYI

Condltlons(1)

= 50pF
RL = soon
CL = 300pF(3)
RL = 500n
CL = SOpF
RL = soon
CL = 300pF(3)
RL = soon
CL = SOpF
RL = soon
CL = 300pF(3)
RL = soon
CL = SpF(3)
RL = soon
CL = SOpF
RL = soon
CL

IDT54/74FCT8278T·
8288T

IDT54/74FCT827CT·
828CT

Com'l.

MIL

Com'l.

Mil.

Com'l.

Mil.

Mln.(2) Max.

Mln.(2) Max.

Min.(2) Max.

Min.(2) Max.

Min.(2) Max.

Min.(2) Max.

-

8.0

-

9.0

-

5.0

-

6.5

-

4.4

-

5.0

-

1S.0

-

17.0

-

13.0

-

14.0

-

10.0

-

11.0

-

9.0

-

10.0

-

S.S

-

6.S

-

4.4

-

s.o

-

14.0

-

16.0

-

13.0

-

14.0

-

10.0

-

11.0

-

12.0

-

13.0

-

8.0

-

9.0

-

7.0

-

8.0

-

23.0

-

2S.0

-

1S.0

-

16.0

-

14.0

-

1S.0

-

9.0

-

9.0

-

6.0

-

7.0

-

S.7

-

6.7

-

10.0

-

10.0

-

7.0

-

8.0

-

6.0

-

7.0

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.

Unit
ns

ns

ns

ns

2573 tbl 10

6.24

5

IDT54f74FCT827AT/BT/CT, IDT54f74FCT828AT/BT/CT
HIGH·PERFORMANCE CMOS BUFFERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2573 tbl 09
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

J

~...x.....K~

PULSE WIDTH

-= ~~V
-

OV

tsu~'I4--~

TIMING
INPUT _ _ _ _ _ _-'

LOW-HIG~UL~~

- 3V
- - - - 1 - - - - - - 1.5V
- OV

ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.

-

--+------

zxt

-

=t-

HIGH-LOW-HIGH
PULSE

3V
1.5V
OV

~ 15V
tw

-·--1.5V

SYNCHRONOUS CONTROL

P~E~f~

CLOCK ENABLE
ETC.

- 3V
-1.5V
--------- - OV

J
tsu

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

J----3V

J-----,. - - - - 3V
SAME PHASE
INPUT TRANSITION

)--~+----OV

3.SV
OUTPUT

VOL
OUTPUT

SWITCH

VOH

NORM~~~ OPEN

OPPOSITE PHASE
INPUT TRANSITION

OV

' - - - - - - ' - - - - OV

NOTES
2573 drw 11
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate $ 1.0 MHz; Zo $ son; tF $ 2.Sns;
tR $ 2.Sns.

6.24

6

IDT54f74FCT827ATIBTICT, IDT54f74FCT828AT/BT/CT
HIGH·PERFORMANCE CMOS BUFFERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xx
Temp. Range

FCT

xx

x

x

Device Type

Package

Process

y~lank
P

D
L---------i E
L
SO
827AT
828AT
827BT
L--------------~828BT

827CT
828CT

1

54

~------------------------------~174

Commercial
MIL·STD·883, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Non·lnverting 10·Bit Buffer
Inverting 10-Bit Buffer
Fast Non-Inverting 10-Bit Buffer
Fast Inverting 10-Bit Buffer
Super Fast Non-Inverting 1O-Bit Buffer
Super Fast Inverting 1O-Bit Buffer
-55°C to + 125°C
O°C to +70°C
2573 cnv' 10

6.24

7

~

HIGH-PERFORMANCE
CMOS BUS INTERFACE
LATCHES

I DT54/74 FCT841 AT/BT/CT
I DT54/74 FCT843ATIBT/CT
IDT54/74FCT845AT/BT/CT

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

I DT54/74FCT841 AT/843AT/845 AT equivalent to
FASpM speed
• IDT54/74FCT841 BT/843BT/845BT up to 30% faster
than FASpM
• IDT54/74FCT841CT/843CT/845CT up to 50% faster
than FASpM
.

The IDT54/74FCT800AT/BT/CT series is built using
advanced CEMOSTM , a dual metal CMOS technology.
The IDT54/74FCT840 Series bus interface latches are
designed to eliminate the extra packages required to buffer
existing latches and provide extra data width for wider
address/data paths or buses carrying parity. The IDT541
74FCT841 AT/BT/CT are buffered, 1O-bit wide versions of the
popular '373 function. The IDT54/74FCT843AT/BT/CT are 9bit wide buffered latches with Preset (PRE) and Clear (CLR)
- ideal for parity bus interfacing in high-performance systems.
The IDT54/74FCT845AT/BT/CT are 8-bit buffered latches
with all the '843 controls, plus multiple enables (OE 1, OE2,
OE3) to allow multiusercontrol of the interface, e.g., CS, DMA
and RD/WR. They are ideal for use as an output port requiring
high loUloH.
All of the IDT54/74FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in high impedance
state.

• TRUE TIL input and output compatible
- VOH = 3.3V (typ)
- Val = O.3V (typ).
• Equivalent to AMD's Am29841-45 bipolar registers in
pinout/function, speeds and output drive over full temperature and voltage supply extremes
• IOl = 48mA (commercial) and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1 mW typo static)
• Substantially lower input current levels than AM D's
bipolar Am29800 series (51J.A max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Meet or exceed JEDEC Standard 18 specifications

FUNCTIONAL BLOCK DIAGRAM

2571 cnv' 01

PRODUCT SELECTOR GUIDE
Device

CEMOS is a trademark of Integrated Device Technology. Inc.
FAST IS a trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
~1990

Integrated Device Technology. Inc.

6.25

10-Bit

9-Bit

8-Bit

IDT54/74FCT841

IDT54/74FCT843

IDT54/74FCT845

AT/BT/CT

AT/BT/CT

AT/BT/CT

JUNE 1990
DSC-4204I-

1

IDT54174FCT841/843/845AT/BT/CT
CMOS BUS INTERFACE LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
IDT54/74FCT841T 10-BIT LATCH
Vee
Yo
Y1
Y2
Y3
Y4
Ys
Y6
Y7
Ya
Y9
LE

OE
Do
D1
D2
D3
D4
Ds
D6
D7
Ds
D9
GND

INDEX
I

D2
D3
D4
NC
Ds
Ds
D7

:]5
:]6

II II

IIII

II

II

I

';f '3' 'i ~1 282726

25[:
24 [:
:]7
23[:
:]8
L28-1
22[:
:]9
21 [:
:]10
20[:
:]11
19 [:
12131415161718

Y2
Y3
Y4
NC
Ys
Ys
Y7

D~D

LE

LE - - - - '

Q~10
I

Y

I

OE _ _ _ _ _ _---J

nnnnnnn

~o~g~~>
C)

LCC

D1P/CERPACKISOIC
TOP VIEW

2571 cnv· 02,03,08

TOP VIEW

IDT54/74FCT843T 9-BIT LATCH
Vee
Yo
Y1
Y2
Y3
Y4
Ys
Ys
Y7
Ys
PRE
LE

DE
Do
D1
D2
D3
D4
Ds
Ds
D7
Ds
CLR
GND

INDEX
I

D2
D3
D4
NC
Ds
Ds
D7

II

II

II II

II

II

I

~'3''i1282726

25[:
24[:
23[:
:]7
:]8
22C
L28-1
:]9
21[:
20[:
:]10
19[:
:]11
12131415161718
:]5
:]6

Y2
Y3
Y4
NC
Ys
Ys
Y7

D

Y

LE
PRE
CLR
DE

~~~,-,,...,,...,,...,

1.1

II

II

I.

11.1

I

~1~~g~I~~
() (j
a..
LCC
TOP VIEW

DIP/CERPACKISOIC
TOP VIEW

2571 cnv· 04,05,09

IDT54/74FCT845T 8-BIT LATCH
DE1

Vee

OE2
Do
D1
D2
D3
D4
Ds
Ds
D7

OE3
Yo
Y1
Y2
Y3
Y4
Ys
Y6
Y7

CLR
GND

PRE
LE

INDEX
I

D1
D2
D3
NC
D4
Ds
D6

II

II

II II

II

II

25[:
:]5
24[:
:]6
:]7
23C
:]8
22[:
L28-1
:]9
21[:
:]10
20[:
:]11
19[:
12131415161718
,-, ,...., r-t,...., ,.., ,..., ,..,
I

II

II

II

II

D

I

~'3''i1282726

Y1
Y2
Y3
NC
Y4
Ys
Y6

Y

LE
PRE
CLR
OE1
OE2
OE3

11'1'

Cil ()(j
a: 0Z ()
UJ IUJ
...J
Z...J
a: >Q..

DIP/CERPACKISOIC
TOP VIEW

LCC
TOP VIEW

6.25

2571 cnv· 06,07,10

2

IDT54174FCT841/843/845AT/BT/CT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CMOS BUS INTERFACE LATCHES

FUNCTION TABLE(1)

PIN DESCRIPTION
Name
CLR

110
I

Description
When CLR is low, the outputs are LOW
if OE is LOW. When CLR is HIGH, data
can be entered into the latch.

Inter-

01

I

The latch data inputs.

LE

I

The latch enable input. The latches are
transparent when LE is HIGH. Input data
is latched on the HIGH-to-LOW
transition.

YI
OE

PRE

a
I

I

Inputs
CLR PRE OE LE

nal
QI

Output

01

X

X

Z

High Z
High Z

Function

YI

H

H

H

X

H

H

H

H

L

L

Z

H

H

H

H

H

H

Z

High Z

H

H

H

L

X

NC

Z

Latched (High Z)

H

H

L

H

L

L

L

Transparent

The 3-state latch outputs.

H

H

L

H

H

H

H

Transparent

The output enable control. When OE is
LOW, the outputs are enabled. When OE
is HIGH, the outputs Y I are in highimpedance (off) state.
Preset line. When PRE is LOW, the
outputs are HIGH if OE is LOW. Preset
overrides CLR.

H

H

L

L

X

NC

NC

H

L

L

H

Preset

H

L

L

L

L

L

H

H

L

X
X
X
X

H

L

X
X
X

H

L

H

L

X

2571 tbl 02

Latched

L

L

Clear

H

H

Preset

L

Z

Latched (High Z)

H

Z

Latched (High Z)

NOTE:
2571 tbl03
1. H =HIGH, L= LOW, X = Don'tCare. NC= No Charge, Z= High-Impedance

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GNO
VTERM(3) Terminal Voltage
with Respect to
GNO
TA
TSIAS

Operating
Temperature
Temperature
Under Bias

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

o to +70

-55 to +125

°C

-55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

Symbol
CIN
COUT

TSTG

Storage
Temperature

PT

Power Oissipatior

0.5

0.5

W

lOUT

OC Output
Current

120

120

mA

Parameter(1)
Input
Capacitance
Output
Capacitance

Conditions

Typ.

Max.

Unit

VIN = OV

6

10

pF

VOUT= OV

8

12

pF

NOTE:
1.This parameter is measured at characterization but not tested.

2571 tbl 05

I

II

NOTE:
2571 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +O.5V unless otherwise noted.
2. Input and Vce terminals only.
3. Outputs and 110 terminals only.

6.25

3

IDT54174FCT841/843/845ATIBTICT
CMOS BUS INTERFACE LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc= 5.0V
Svmbol

Test Condltlons(1)

VIH

Parameter
Input HIGH Level

Guaranteed Logic HIGH Level

Vil

Input LOW Level

Guaranteed Logic LOW Level

IiH

Input HIGH Current

Vee = Max.

III

Input LOW Current

10ZH

High Impedance Output Current

O.S

V

VI = 2.7V

-

-

5

~A

Vee = Max.

VI = 0.5V

-

~A

Vo= 2.7V

-

-5

Vee = Max.

10

~A

Vo= 0.5V

-

-

-10

Input HIGH Current

Vee = Max., VI = Vee (Max.)
Vee = Min., IN = -1SmA

los

Short Circuit Current

Vee = MaxP), VO= GND

VOH

Output HIGH Voltage

Vee = Min.
VIN = VIH or Vil

Input Hysteresis
Quiescent Power Supply Current

Unit

-

Clamp Diode Voltage

Icc

Max.

-

II

VH

TvpP)

-

VIK

Output LOW Voltage

Min.
2.0

-

10Zl

Val

± 10%

Vee = Min.
VIN = VIH or Vil

Vee = Max.
VIN = GND or Vee

-

-

~A

20

-0.7

-1.2

V

-60

-120

-225

mA

10H = -6mA MIL.
10H = -SmA COM'L.

2.4

3.3

-

V

10H = -12mA MIL.
10H = -15mA COM'L.

2.0

3.0

-

V

10l = 32mA MIL.
10l = 48mA COM'L.

-

0.3

0.5

V

-

200

-

mV

-

0.2

1.5

mA

NOTES:
1. For conditions shown as Max. or Min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

6.25

V

25711b106

4

IDT54174FCT841/843/845AT/BT/CT
CMOS BUS INTERFACE LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Svmbol

T~p.(2)

Max.

Unit

-

0.5

2.0

mA

VIN = Vee
VIN = GND

-

0.15

0.25

mAl
MHz

Vee = Max.
Outputs Open
fi = 10MHz

VIN = Vee

-

1.7

4.0

mA

50% Duty Cycle
OE = GND

VIN =3.4V
VIN =GND

-

2.0

5.0

VIN = Vee
VIN =GND

-

3.2

6.5(5)

VIN = 3.4V
VIN = GND

-

5.2

14.5(5)

Test Condltions(1)

Parameter

~Iee

Quiescent Power Supply Current
TIL Inputs HIGH

Vee = Max.
VIN = 3.4V(3)

leeD

Dynamic Power Supply Curren~4)

Vee = Max.
Outputs Open
OE = GND

Min.

LE = Vee
One Input Toggling
50% Duty Cycle
Ie

Total Power Supply Curren~6)

VIN = GND

LE = Vee
One Bit Toqqlinq
Vee = Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
OE = GND
LE = Vee
Eight Bits Toggling
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vee or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + I INPUTS + IDYNAMIC
Ic = Icc + ~Ice DHNT + ICCD (fcP/2 + fiN i)
Icc = Quiescent Current
~Ice = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.25

25711bl07

I

5

IDT54f74FCT841/843/845AT/BT/CT
CMOS BUS INTERFACE LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT841 AT-

IDT54/74FCT841 BT-

845AT

845BT

Symbol

Mil.

Com'l.

Test

Com'l.

IDT54/74FCT841CT845CT

Mil.

Com'l.

Mil.

Conditlons(1) Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Min.(2) Max. Mln.(2) Max. Unit

Parameter

tPLH

Propagation Delay

CL

tPHL

D ItOYI

RL

= SOpF
= soon

-

9.0

-

10.0

-

6.S

-

7.S

-

S.S

-

6.3

-

13.0

-

lS.0

-

13.0

-

1S.0

-

13.0

-

1S.0

ns

(LE = HIGH)

= 300pF(3)
= soon
CL = SOpF
RL = soon
CL = SOpF
RL = soon
CL = 300pF(3)
RL = soon
CL = SOpF
RL = soon

CL

RL

tsu

Data to LE Set-up Time

tH

Data to LE Hold Time

tPLH

Propagation Delay

tPHL

LE toYI

2.S
2.S

-

-

2.S

2.S

2.S

-

ns
ns
ns

2.S

8.0

-

10.S

-

6.4

-

6.8

-

16.0

-

20.0

-

lS.S

-

18.0

-

1S.0

-

16.0

-

12.0

-

8.0

-

10.0

-

7.0

14.0

10.0

-

9.0

13.0

14.0

-

10.0

-

13.0

-

-

14.0

-

11.0

-

10.0

-

10.0

-

9.0

17.0

-

ns
ns
10.0 ns
9.0 ns
4.0 ns
4.0 ns
4.0 ns

Propagation Delay, CLR to YI

tREM

Recovery Time CLR to Y I

tw

LE Pulse Width(3)

HIGH

4.0

tw

PRE Pulse Width(3)

LOW

S.o

tw

CLR Pulse Width(3)

LOW

tPZH

Output Enable Time OE to YI

Output Disable Time OE to YI

2.S

-

tPHL

tPLZ

-

2.S

2.S

13.0

Recovery Time PRE to YI

tPHZ

2.S

-

-

tREM

tPZL

-

12.0

Propagation Delay, PRE to YI

4.0

= SOpF
RL = soon
CL = 300pF(3)
RL = soon
CL = SpF(3)
RL = soon
CL = SOpF
RL = soon

2.S
3.0

-

tPLH

CL

-

14.0

-

S.O
7.0
S.O

17.0

-

9.0

4.0

-

4.0

-

4.0

4.0

4.0

-

4.0

4.0

-

4.0

-

4.0

-

9.0

12.0

-

11.S

-

13.0

-

8.0

-

8.S

-

6.S

-

7.3

-

23.0

-

2S.0

-

14.0

-

1S.0

-

12.0

-

13.0

-

7.0

-

9.0

-

6.0

-

6.S

-

S.7

-

6.0

-

8.0

-

10.0

-

7.0

-

7.S

-

6.0

-

6.3

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.

ns

ns

2571 tbl 09

6.25

6

IDT54174FCT841/843/845AT/BT/CT

CMOS BUS INTERFACE LATCHES

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vee

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

0--.7.0V

soon

DEFINITIONS:

25711bll0

CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

j

PULSE WIDTH

-= ~~V

""-..x.-x~ -

OV

tsu --'\4--~

lOW-HIG~~~~

bJ

TIMING
- 3V
V
INPUT _ _ _ _ _ _,.,~~--+------_
ASYNCHRONOUS CONTROL
PRESET - - - - ,
CLEAR
ETC. - - - - "
SYNCHRONOUS CONTROL
CLOCK

- 3V
,-+---+---- - - + - - - - - - l.SV

:~~~~~ vvJr
j
~tsu
ETC.

""-..x.-x~

-

-

OV

-

3V
1.5V

=t-

HIGH-lOW-HIGH
PULSE

_

~ 15V
tw

--1.SV

- OV

PROPAGATION DELAY

I

ENABLE AND DISABLE TIMES
ENABLE

DISABLE
3V

SAME PHASE
INPUT TRANSITION

OUTPUT

OV
OV
3.SV

VOH
-1.SV

VOL

VOL
OUTPUT
NORMALLY
HIGH

3V
OPPOSITE PHASE
INPUT TRANSITION

NOTES

VOH
SWITCH
OPEN
OV
2571 drw 11

1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
.
2. Pulse Generator for All Pulses: Rate:s; 1.0 MHz; Zo:s; son; tF:S; 2.5ns;
tR:S; 2.5ns.

6.25

7

I DT5417 4FCT841/843/845AT/BT/CT
CMOS BUS INTERFACE LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT
XX
FCT
XXX X
T:;="e-m-p-.-:::R==-a-n-ge-=O,....e-vl:-·c-e"=T""'yp-e-

X

X

Package

Process

~~Iank
P
1 - -_ _ _ _ _ _. ,

o

E

L
SO
841AT
843AT
845AT
841BT
L----------------------~843BT

845BT
841CT
843CT
845CT
54

L-------------------------------------~74

Commercial
MIL-STO-883, Class B
Plastic DIP
CEROIP
CERPACK
Leadless Chip Carrier
Small Outline IC
1O-Bit Non-Inverting Latch
9-Bit Non-Inverting Latch
8-Bit Non-Inverting Latch
Fast 10-Bit Non-Inverting Latch
Fast 9-Bit Non-Inverting Latch
Fast 8-Bit Non-Inverting Latch
Super Fast 10-Bit Non-Inverting Latch
Super Fast 9-Bit Non-Inverting Latch
Super Fast 8-Bit Non-Inverting Latch
-55°C to + 125°C
O°C to +70°C
2571 cnv· 16

6.25

8

(;)®

I DT29FCT52A/B/C
IDT29FCT53A/B/C

FAST CMOS
OCTAL REGISTERED
TRANSCEIVERS

Integrated Devtce Technology, Inc.

FEATURES:

DESCRIPTION:

• Equivalent to AMD's Am2952/53 and National's
29F52/53 in pinouVfunction
• IDT29FCT52A153A equivalent to FASl'M speed
• IDT29FCT528/538 25% faster than FA SliM
• IDT29FCT52C/53C 37% faster than FASTTM
• IOL = 64mA (commercial) and 48mA (military)
• IIH and IlL only 5JlA max.
• CMOS power levels (2.5mW typo static)
• TIL input and output level compatible
• CMOS output level compatible
• Available in 24-pin DIP, SOIC, 28-pin LCC and PLCC
with JEDEC standard pinout
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT29FCT52A1B/C and IDT29FCT53A1B/C are 8-bit
registered transceivers manufactured using advanced
CEMOSTM, a dual-metal CMOS technology. Two 8-bit backto-back registers store data flowing in both directions between
two bidirectional buses. Separate clock, clock enable and
3-state output enable signals are provided for each register.
Both A outputs and B outputs are guaranteed to sink 64mA.
The IDT29FCT52A1B/C is a non-inverting option of the
IDT29FCT53A1B/C.

FUNCTIONAL BLOCK DIAGRAM(1)
CPA
CEA

Ao
A1
A2
A3
A4

As
A6

A7

!

I

Do CE CP 00

01
01
02
02
03
03
A
04 Reg. 04
Os
as
06
06
07
07
00
00
01
01
02
02
03
03
8
04 Reg. 04
as
Os
06
06
07 CE CP 07

OEA

I

NOTE:
1. IDT29FCT52 function is shown.

I

J
[5

~

<1: <1:

Vee

B7
B6
Bs
B4
B3
B2
B1
Bo
OEB
CPA
CEA
GND

L...JL-J L-JI

A7
A6
As
A4
A3
A2
A1
Ao
OEA
CPB
CEB

IL...J

L...JL!....J

4 3 2 I 126 27 26
B4
B3
B2
NC
B1
Bo
OEB

LJ

JS
J6
J7
J6
J9
JlO
J 11

25 [
24 [
23 [
22 [
21 [
20 [
19 [

1
J28-1
L28-1

As
A4
A3
NC
A2
A1
Ao

1213 14 15 16 17 16
,.--, r-1

,.--, " , . - - ,

, . , ,.--,

2533 drw 02

<1:1<1:0 Olen enl<1:

~~~Z~~~

DIP/CERPACKISOIC
TOP VIEW

LCC/PLCC
TOP VIEW

PIN DESCRIPTION
Name

1/0

AO-7

I/O

Description
Eight bidirectional lines carrying the A Register inputs or B Register outputs_

80-7

I/O

CPA

I

Clock for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition
of the CPA signal.

CEA

I

Clock Enable for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH
transition of the CPA signal. When CEA is HIGH, the A Register holds its contents, regardless of CPA signal
transitions.

OEB

I

Output Enable forthe A Register. When OEB is LOW, the A Registeroutputs are enabled onto the 80-7Iines. When
OEB is HIGH, the BO-7 outputs are in the high impedance state.

CP8

I

Clock for the B Register. When CE8 is LOW, data is entered into the 8 Register on the LOW-to-HIGH transition
of the CPB signal.

CE8

I

Clock Enable for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH
transition of the CPB signal. When CEB is HIGH, the B Register holds its contents, regardless of CPB signal
transitions.

OEA

I

Output Enable forthe B Register. When OEA is LOW, the B Registeroutputs are enabled onto the AO-7Iines. When
OEA is HIGH, the AO-7 outputs are in the high impedance state.

Eight bidirectional lines carrying the 8 Register inputs or A Register outputs_

2533 tbl 05

REGISTER FUNCTION TABLE(1)

OUTPUT CONTROL(1)

(Applies to A or B Register)
Inputs
D

CP

X
L
H

Internal
Internal
Q

X

CE
H

NC

i
i

L
L

L
H

V-Outputs

OE

Q

52

53

Function
Hold Data

H

X

Z

Z

Disable Outputs

Load Data

L

L

L

H

Enable Outputs

L

H

H

L

2533 tbl 06

NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
NC = No Change
i = LOW-to-HIGH Transition

6.26

Function

2533 tbl 07

2

IDT29FCT52A1B/C, IDT29FCT53A1B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

CAPACITANCE

Commercial

Military

Unit

VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage
with Respect
toGND
TA
Operating
Temperature

-0.5 to +7.0

-0.5 to +7.0

-0.5 to Vcc

TBIAS

(TA

= +25°C, f = 1.0MHz)

Symbol

Parameter(1)

Conditions

Typ.

Max.

Unit

V

CIN

Input
Capacitance

VIN = OV

6

10

pF

-0.5 to Vcc

V

ClIO

I/O
Capacitance

VOUT = OV

8

12

pF

o to +70

-55 to +125

°C

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT
lOUT

Power Dissipation

0.5

0.5

W

DC Output Current

120

120

mA

NOTES:

NOTE:
2533 tbl 02
1. This parameter is guaranteed by characterization data and not tested.

2533 tbl 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability. No terminal voltage may
exceed +O.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Outputs and 1/0 terminals only.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = O.2V; VHC = Vcc - O.2V
Commercial: TA = O°C to +70°C, Vee = 5.0V ± 5%; Military: TA = -55°C to + 125°C, Vee
Symbol

Test Conditlons(1)

Parameter

= 5.0V +-

Typ.(2)

-

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

IIH

Input HIGH Current

Vcc = Max.

ilL

IIH

VI =Vcc

-

(Except I/O Pins)

VI

Input LOW Current

VI = 0.5V

(Except I/O Pins)

VI

-

Input HIGH Current

Vcc = Max.

VI

= 2.7V

-

-

-

-

Vce = Min., IN = -18mA

los

Short Circuit Current

Vcc = MaxP), Vo = GND

VOH

Output HIGH Voltage

V

5
5(4)

).LA

-0.7

-5
15
15(4)

-15

Vcc = 3V, VIN = VLC or VHC, 10H = -32).LA

VHC

Vcc

Vcc

VHC

Vcc

10H = -15mA MIL.

2.4

4.0

-

10H = -24mA COM'L.

2.4

4.0

=

Min.

-60
10H

=

-300).LA

Vcc = Min.

10L = 300).LA

VIN = VIH or VIL

10L = 48mA MIL.(5)

-

10L = 64mA COM'L.(5)

-

Vcc = 3V, VIN = VLC or VHC, 10L = 300).LA

-120

GND

).LA

-1.2

-

VIN = VIH or VIL
Output LOW Voltage

V

0.8

-15(4)

VI = 0.5V
VI = GND

Unit

-

_5(4)

Input LOW Current
Clamp Diode Voltage

Max.

-

(I/O Pins Only)
VIK

VOL

=GND

VI = Vcc

(I/O Pins Only)
IlL

= 2.7V

10%

Min.

V
mA
V

-

GND

VLC
VLd 4)

0.3

0.55

0.3

0.55

V

NOTES:
2533 tbl 05
1. For conditions shown as Max. or Min .. use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vec = 5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. These are maximum 10L values per output, for 8 outputs turned on simultaneously. Total maximum 10L (all outputs) is 512mA for commercial and
384mA for military. Derate IOL for number of outputs exceeding 8 turned on simultaneously.

6.26

3

II

IDT29FCT52A1B/C, IDT29FCT53A1B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC

=O.2V; VHC = VCC - a 2V

Symbol
Icc

Test Condltlons(1)

Typ.(2)

Max.

Unit

-

O.S

1.5

mA

-

0.5

2.0

mA

VIN ~ VHC
VIN ~ VLC

-

0.15

0.25

mAl
MHz

Vcc = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
OEA or OEB= GND
One Bit Toggling
at fi = 5MHz
50% Duty Cycle

VIN ~ VHC
VIN ~ VLC
(FCT)

-

2.0

4.0

mA

VIN = 3.4V
VIN = GND

-

2.5

6.0

VCC = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
OEA or DEB = GND
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle

VIN ~ VHC
VIN ~ VLC
(FCT)

-

4.3

7.8(5)

VIN = 3.4V
VIN = GND

-

6.5

16.8(5)

Parameter
Quiescent Power Supply
Current

Vee = Max.
VIN ~ VHC; VIN

~Icc

Quiescent Power Supply
Current TTL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

ICCD

Dynamic Power Supply
Current(4)

Vcc = Max.
Outputs Open
OEA or OEB= GND
One Input Toggling
50% Duty Cycle

Ic

Total Power Supply
Current(6)

~

Min.

VLC

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vee or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ie = laulEscENT + IINPUTS + IDYNAMIC
Ie = Icc + t.lee DHNT + IceD (fep/2 + fiNi)
Icc = Quiescent Current
t.lee = Power Supply Current for a TTL High Input (V IN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
IceD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fep = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.26

2533 tbl07

4

IDT29FCT52A1B/C, IDT29FCT53A1B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

Symbol

Parameter

tPLH
tPHL

Propagation Delay
CPA, CPB to An, Bn

tPZH
tPZL

I DT29 FCT52A153A

IDT29FCT52B/53B

Com'l.

Com'l.

IDT29FCT52C/53C

Com'l.
Mil.
Conditlon(1) Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Unit
CL = SOpF
RL = soon

Mil.

Mil.

2.0

10.0

2.0

11.0

2.0

7.S

2.0

8.0

2.0

6.3

2.0

7.3

ns

Output Enable Time
OEAorOEB to
An or Sn

1.S

10.S

1.S

13.0

1.5

8.0

1.S

8.5

1.5

7.0

1.S

8.0

ns

tPHZ
tPLZ

Output Disable Time
OEAorOESto

1.S

10.0

1.S

10.0

1.S

7.S

1.S

8.0

1.5

6.S

1.5

7.5

ns

tsu

Set-up Time HIGH
or LOW An, Bn to
CPA,CPS

2.5

-

2.S

-

2.5

-

2.S

-

2.S

-

2.S

-

ns

tH

Hold Time HIGH
or LOW An, Bn to
CPA, CPB

2.0

-

2.0

-

1.5

-

1.5

-

1.5

-

1.5

-

ns

tsu

Set-up Time HIGH
or LOW CEA, CEB to
CPA,CPB

3.0

-

3.0

-

3.0

-

3.0

-

3.0

-

3.0

-

ns

tH

Hold Time HIGH
or LOW CEA, CEB to
CPA, CPB

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

ns

tw

Pulse Width, HIGH(3)
or LOW CPA or CPB

3.0

-

3.0

-

3.0

-

3.0

-

3.0

-

3.0

-

ns

An or Bn

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.

2533 Ibl 08

II

6.26

5

IDT29FCT52A1B/C, IDT29FCT53A1B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vcc

SWITCH POSITION

soon

SOpF

11

RT

soon

Closed

All Other Outputs

Open
25331b109

PULSE WIDTH

-= ~~V

j

........______ -

OV

tsu -t'i4--~

TIMING
INPUT _ _ _ _ _ _,

Open Drain
Disable Low
Enable Low

CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES

zzt

Switch

DEFINITIONS:

l..CL

DATA
INPUT

Test

O-7.0V

LOWHIG~UL~S~

- 3V
- - - - j - - - - - - 1.SV
- OV

ASYNCHRONOUS CONTROL

=t-

HIGH.LOW.HIGH

PRESET - - - - , I ..~-+--t----­ - 3V
- - + - - - - - - 1.SV
CLEAR
- OV
ETC. - - - - " "
SYNCHRONOUS CONTROL
- 3V
-1.SV
CLOCK
I
........- - - - - - - OV

~ 15V
tw

_ _ 1.SV

PULSE

:~~~~~
vvY
ETC.~tsu

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

3V
SAME PHASE
INPUT TRANSITION

OUTPUT

OV
OV
3.SV

VOH
-1.SV

VOL

VOL
OUTPUT
NORMALLY
HIGH

3V
OPPOSITE PHASE
INPUT TRANSITION

VOH
SWITCH
OPEN

OV

OV

NOTES

2533 drw 04

1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ son; tF ~ 2.Sns;
tR ~ 2.5ns.

6.26

6

IDT29FCT52A1B/C, IDT29FCT53A1B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT29FCT

XXX

X

X

Device
Type

Package

Processl
Temperature
Range

'-------tl ~Iank
P

'------------l

D
E
J
L
SO

52A
53A
' - - - - - - - - - - - - - - - - - t 528
538
52C
53C

Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class 8
Plastic DIP
CERDIP
CERPACK
Plastic Leaded Chip Carrier
Leadless Chip Carrier
Small Outline IC
Non-Inverting Octal Registered Transceiver
Inverting Octal Registered Transceiver
Fast Non-Inverting Octal Registered Transceiver
Fast Inverting Octal Registered Transceiver
Super Fast Non-Inverting Octal Registered Transceiver
Super Fast Inverting Octal Registered Transceiver
2533 drw03

I

I

6.26

7

(;)®

IDT29FCT520A
IDT29FCT520B
IDT29FCT520C

MULTILEVEL
PIPELINE REGISTER

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• Equivalent to AMD's Am29520 bipolar Multilevel Pipeline
Register in pinoUt/function, speed and output drive over
full temperature and voltage supply extremes
• Four 8-bit high-speed registers
• Dual two-level or single four-level push-only stack
operation
• All registers available at multiplexed output
• Hold, transfer and load instructions
• Provides temporary address or data storage
• IOL = 48mA (commercial), 32mA (military)
• CMOS power levels (1 mW typo static)
• Substantially lower input current levels than AMD's
bipolar (5~ typ.)
• TIL input and output level compatible
• CMOS output level compatible
• Manufactured using advanced CEMOSTM processing
• Available in 300 mil plastic and hermetic DIP, as well as
LCC, SOIC and CERPACK
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT29FCT520AlB/C contains four8-bit positive edgetriggered registers. These may be operated as a dual2-level
or as a single 4-level pipeline. A single 8-bit input is provided
and any of the four registers is available at the 8-bit, 3-state
output.
In the IDT29FCT520AlB/C when data is entered into the
first level (I = 2 or I = 1), the existing data in the first level is
moved to the second level. Transfer of data to the second
level is achieved using the 4-level shift instruction (I =0). This
transfer also causes the first level to change.

FUNCTIONAL BLOCK DIAGRAM
00-07

YO-Y7

2620 drw 01

CEMOS is a trademark of Integrated Device Techology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1990 Integrated Device Technology. Inc.

6.27

APRIL 1990
DSC46081·

1

IDT29FCT520AlB/C
MULTILEVEL PIPELINE REGISTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
10
11

INOEX

Vee

00
01
02
03
04
05
06

So
S1
Yo
Y1
Y2

01

J5

02
03

J 6
J7

22[
L28-1
J8
21 [
J9
20[
J 10
19[
J 11
12 13 14 1516 1718

L-J LJ

4

Y3

NC

Y4
Y5

04
05

07

Y6

06

CLK
GNO

Y7

L-J

3 2

I I L...J
I 128

L...J L...J

2726

L.J

1

24 [
23[

OE

Yo
Y1
Y2
NC

Y3

Y4
Y5
2620 drw02

DIP/CERPACK/SOIC
TOP VIEW

Lce
TOP VIEW

DEFINITION OF FUNCTIONAL TERMS
Pin Names

25[

REGISTER SELECTION

Description

Sl

So

Register

On

Register input port.

0

0

82

CLK

Clock input. Enter data into registers on LOWto-HIGH transitions.

0

1

81

1

0

A2

1

1

A1

10,11

Instruction inputs. See Figure 1 and
Instruction Control Tables.

SO,S1

Multiplexer select. Inputs either register A1, A2,
81 or 82 data to be available at the output port.

OE

Output enable for 3-state output port

Yn

Register output port.

2620 till 02

2620 till 01

OUAL 2-LEVEL

II

SINGLE 4-LEVEL

cb
dJ

cb
dJ

NOTE:
1. I = 3 for hold.

Figure 1. Data Loading in 2-Level Operation

6.27

2

IDT29 FCT520AlB/C
MULTILEVEL PIPELINE REGISTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage

CAPACITANCE

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

Operating
Temperature

o to +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to + 135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

rnA

Conditions Typ.

CIN

Input Capacitance

VIN = OV

6

10

pF

CoUT

Output Capacitance

VOUT = oV

8

12

pF

Unit

Max.

2620 tbl 04
NOTE:
1. This parameter is measured at characterization data but not tested.

with Respect
toGND
TA

(TA= +25°C, f = 1.0MHz)

Parameter(1)

Symbol

NOTES:
2620 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Inputs and Vee terminals.
3. Outputs and 110 terminals.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = O.2V, VHC = Vcc - O.2V
Commercial: TA = O°C to +70°C, VCC = 5.0V +
- 5%; Military: TA = -55°C to + 125°C, Vce = 5.0V +- 10%
Typ.(2)
Test Condltlons(1)
Symbol
Parameter
Min.
VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

VIL

Input LOW Level

Guaranteed Logic LOW Level

IIH

Input HIGH Current

Vee

IlL

Input LOW Current

10ZH

Off State (High Impedance) Vee

-

= Max.

= Vee
VI = 2.7V

VI

VI = 0.5V

= GND
= Vee
Vo = 2.7V
VI

= Max.

Vo

Output Current
10ZL

Vo = O.5V
Vo

los

Short Circuit Current

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

= MaxP), Vo = GND
Vee = 3V, VIN = VLe or VHe,
Vee = Min.
VIN = VIH or VIL

= GND

Vee

10H = -3211A

= -3OOI1A
10H = -12mA MIL.
10H = -15mA COM'L.
Vee = 3V, VIN = VLe or VHe, 10L = 3OOl1A
Vee = Min.
10L = 3OOl1A
VIN = VIH or VIL
10L = 32mA MIL.
10L = 48mA COM'L.
10H

Max.

Unit

-

V

-

-

-

I1A

-5
10
10(4)

-10

-60

-120

VHe

Vee

-

VHe

Vee

-

2.4

4.3

2.4

4.3

-

-

I1A

-10(4)

GND

VLe

GND

VLd 4)

0.3

0.5

0.3

0.5

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

6.27

V

5
5(4)
_5(4)

-

-

0.8

rnA
V

V

2620 tbl 05

3

IDT29FCT520AlB/C
MULTILEVEL PIPELINE REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

VLC

=O.2V, VHC =VCC - O.2V
Min.

Typ.(2)

Max.

Unit

Icc

Quiescent Power
Supply CUrrent

Vcc = Max.
VIN ~ VHC; VIN :5 VlC

-

0.2

1.5

mA

~Icc

Quiescent Power Supply
Current, TIL Input HIGH

Vcc = Max.
VIN = 3.4 V(3)

-

0.5

2.0

mA

ICCD

Dynamic Power Supply Current(4)

Vcc = Max., Outputs Open
OE=GND
One Input Toggling
50% Duty Cycle

VIN~ VHC
VIN:5 VlC

-

0.15

0.25

mAl
MHz

Ic

Total Power Supply Current(6)

Vcc = Max., Outputs Open
fcp = 10MHz
50% Duty Cycle

VIN ~ VHC
VIN:5 VlC
(FeT)

-

1.7

4.0

mA

-

2.2

6.0

-

7.0

12.8(5)

-

9.2

21.8(5)

Symbol

Parameter

Test Condltlons(1)

VIN = 3.4V
OE = GND
One Bit Toggling
VIN= GND
at fi = 5MHz, 50% Duty Cycle
Vcc = Max., Outputs Open
fcp = 10MHz
50% Duty Cycle

VIN ~ VHC
VIN:5 VlC
(FCT)

VIN = 3.4V
OE = GND
Eight Bits Toggling
VIN = GND
at fi = 5MHz, 50% Duty Cycle

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT +IINPUTS + IDYNAMIC
Ic = Icc + .::llcc DHNT + ICCD (fcP/2 + fiNi)
Icc = Quiescent Current
.::llcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fep = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.27

2620 tbl 06

4

IDT29FCT520AlB/C
MULTILEVEL PIPELINE REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT520A
Com'l.
Symbol

Parameter

tPHL
tPLH

Propagation Delay
ClKto Yn

tPHL
tPLH

MIL

IDT54/74FCT520B
Com'l.

MIL

IDT54/74FCT520C .
Com'l.

MIL

Condltlon(1) Mln.(2) Max. Mln.(2) Max. Mln.<2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Unit

= 50pF
= 500n

2.0

14.0

2.0

16.0

2.0

7.5

2.0

8.0

2.0

6.0

2.0

7.0

ns

Propagation Delay
So or Sl to Yn

2.0

13.0

2.0

15.0

2.0

7.5

2.0

8.0

2.0

6.0

2.0

7.0

ns

tsu

Set-up Time HIGH
or lOW Dn to ClK

5.0

-

6.0

-

2.5

~

2.8

-

2.5

-

2.8

-

ns

tH

Hold Time HIGH
or lOW Dn to ClK

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

ns

tsu

Set-up Time HIGH
or lOW loor 11
to ClK

5.0

-

6.0

-

4.0

-

4.5

-

4.0

-

4.5

-

ns

tH

Hold Time HIGH
or lOW loor 11
to ClK

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

ns

tPHZ
tPLZ

Output Disable Time

1.5

12.0

1.5

13.0 . 1.5

7.0

1.5

7.5

1.5

6.0

1.5

6.0

ns

tPZH
tPZL

Output Enable Time

1.5

15.0

1.5

16.0

1.5

7.5

1.5

8.0

1.5

6.0

1.5

7.0

ns

tw

Clock Pulse Width
HIGH or lOW

7.0

5.5

-

6.0

-

5.5

-

6.0

-

ns

CL
RL

-

8.0

NOTES:
1. See test circuit and waveforms.
2. Minimum units are guaranteed but not tested on Propagation Delays.

-

2620 tbl 07

6.27

5

IDT29FCT520AlB/C
MULTILEVEL PIPELINE REGISTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vcc

SWITCH POSITION
e-.7.0V

soon

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2620 Ibl 08
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

l

PULSE WIDTH

-= nV

""-.-.__~ _ OV

tsu--4~-~

TIMING
INPUT _ _ _ _ _ _J

_

6J
3V

LOW-HIG~U~~

V

ASYNCHRONOUS CONTROL
PRESET - - - - - - , ~--~--~-------­ - 3V
- - + - - - - - l.SV
CLEAR
ETC. - - - - - '
- OV
SYNCHRONOUS CONTROL

CLOCK:~~~~~ vvJr
~tsu
J

___

...M._~

HIGH-LOW-HIGH
PULSE

=t-

~ ,5V
tw

--1.SV

- 3V
-1.5V
OV

ETC.

PROPAGATION DELAY

ENABLE AND DISABLE TIMES

SAME PHASE
INPUT TRANSITION

OUTPUT

OPPOSITE PHASE
INPUT TRANSITION

NOTES
2620 drw 05
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate S 1.0 MHz; Zo s son; tF S 2.Sns;
tR:5 2.Sns.

6.27

6

IDT29FCT520AlB/C
MULTILEVEL PIPELINE REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT29FCT

X

X

x

Device
Type

Package

Processl
Temperature
Range

~~rank
P

o

'--------------1

L
E
SO
520A

' - - - - - - - - - - - - - - - - - - - - i 5208

520C

Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class 8
Plastic DIP
CERDIP
Leadless Chip Carrier
CERPACK
Small Outline IC
Multilevel Pipeline Register
Fast Multilevel Pipeline Register
Super Fast Multilevel Pipeline Register

2620drw 04

6.27

7

(;)

ADVANCE
INFORMATION
IDT49FCT661

HIGH-SPEED 16-BIT
SYNCHRONOUS
BINARY COUNTER

Integrated Device Technology, Inc.

FEATURES:
• 16-bit synchronous up/down counter, synchronously
programmable
• Maximum frequency of 50MHz commercial
• Clock to V-bus of 15ns commercial
• Both synchronous and asynchronous clear inputs
• Three-state counter outputs interface directly with busorganized systems
• Ripple carry output for cascading
• Clocked carry output for convenient modulo configuration
Latched inputs provide for modulo load function or
interface to a processor
• Latched readback path for interface to a processor
• IOL = 48mA commercial and 32mA military
• CMOS power levels (1 mW typo static)
• TIL input and output level compatible
• Available in 48-pin Shrink-DIP, 52-pin PLCC and LCC
• Product Available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

DESCRIPTION:
The IDT49FCT661 is a programmable 16-bit synchronous
up/down binary counter which is conveniently organized for

FUNCTIONAL BLOCK DIAGRAM

operation in a standalone configuration, as well as interfaced
with a processor. All operations except latch, output enable
and asynchronous clear happen on the rising edge of the
Clock Input (CP).
With a LOAD input LOW, the counter will load the value at
the output of the input latch. The input latch is transparent
when LE is LOW, allowing for easy connection to processor
address decode and strobe logic. The D-Bus Output Enable
(OED) is used for reading back the state of the counter in
processor-based applications. When OED is LOW, the latch is
closed and the D bus is driven with the contents of the latch;
otherwise the output buffer is in a high-impedance state when
OED is HIGH. Counting is enabled only when CEp and CET are
LOW and LOAD is HIGH. The Up/Down Input (Ui5) controls
direction of the count. Internal carry look-ahead logic and an
active LOW on Ripple Carry Output (RCO) allow for counting
and cascading. During up-count, the RCO is LOW at binary
65K and upon down-count is LOW at binary O. Normal
cascade operations require only the RCO to be connected to
the succeeding block at CET. When counting, the Clock Carry
Output (CCO) provides a HIGH-LOW-HIGH pulse for a
duration equal to the clock LOW time of the input clock only
when the RCO is LOW. Two active LOW resets are available:
synchronous clear (SCLR) and Master Asynchronous Clear
(ACLR). The output control (OEY) input forces the output to
high impedance when HIGH, otherwise the V-bus reflects the
output of the counter.

I

0

LE -------I~

OED

U!D----~~
LOAD----~~
CEp-----~

CET·----~~

SCLR
ACLR
RCO
CCO

16-81T
SYNCHRONOUS
COUNTER

CP'-----~

oE v , - - - - - - - - a .

Vcc
~

73

GND

Y
2625 drw Ot

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
iI:l1990 Integrated Device Technology, Inc.

6.28

JUNE 1990
DSC-4619/·

1

t;)

PRELIMINARY
lOT49FCT804A
IDT49FCT804C

HIGH-SPEED TRI-PORT
BUS MULTIPLEXER

Integrated Device Technology, Inc.

FEATURES:
•
•
•
•
•
•
•
•
•
•
•

High-speed, 10 bit x 3 port Bus Multiplexer
Allows bidirectional communication between any 2 ports
10 bits provide extra addressing capability
Latched inputs for asynchronous storage of incoming
data
Controls designed for shared memory applications
IOL = 48mA (CommerCial), 32mA (Military)
CMOS Power Levels (1 mW typo static)
TIL input and output level compatible
Available in DIP, PLCC, LCC and Flatpack
Military product compliant to MIL-STD-883, Class B
Product available in Radiation Tolerant and Radiation
Enhanced versions

DESCRIPTION:
The Busmux is a multiport device intended for inter-bus
communication in a multiprocessing, DSP, Array processing

or networking environment. It offers significant space savings
and performance benefit over discrete implementations of the
function.
The architecture consists of 3 I/O ports. The input of each
port has a transparent latch controlled by a Latch Enable input
(LE). The output of each latch is connected to an internal bus.
The output of each port consists of a multiplexer and a tri-state
buffer. The multiplexer will select one of the other two busses
under control of Path Select Logic inputs (S1, So).
The direction of signal flow is determined by Direction
Control inputs (Dxx). The output enable pins of each port
(OEx) provide independent tri-state control. In addition, when
both Path Select Logic inpt:Jts (S1, So) are high, all three ports
are in a high impedance state.
Forshared memory applications the device is configured to
use ports A and C for 2 system busses and port B for the
shared memory bus. The RAM output enable (RAM OE)
output is asserted when the signal path is from B to A or B to
C. It is disasserted under all other conditions.

FUNCTIONAL BLOCK DIAGRAM
abc

APORT
LEA

SPORT
LEB

CPORT
LEc

DABC>
DCBL>
DCAL>
S1
So

PATH
SEL
LOGIC

00
01
10

OEAC>
OEBC>

OE
CONTROL
LOGIC
RAMOE

OEcC>
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor, Inc.

2622 drwOl

MILITARY AND COMMERCIAL TEMPERATURE RANGES
1i:l1990 Integrated Device Technology, Inc.

6.29

JUNE 1990
DSC-4627/-

1

IDT49FCTS04A1C
HIGH-SPEED TRI-PORT BUS MULTIPLEXER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
INDEX
GND

Ca
C9
RAMUE
S1
So
Ao
A1
A2
A3
A4
Vee
GND
80
81
82
83
84
DAB
DeB
DeA

Co
C1
C2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

P48-1
&
D48-1

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

C7

C6

Ao
A1
A2
A3
A4
Vee
NC
GND
80
81
82
83
84

Cs
rEe
rEB
rEA
89
88
87
86
Vee
85
GND
A9
A8
A7
A6
A5
OEe
OEB
OEA

3 2 u 525150494847
1
461::
45[:
441::
43[:
42[:
411::
J52-1
40[:
391::
38[:
37[:
361::
35[:
] 20
34[:
21222324 2526 2728293031 3233

89
88
87
86
Vee
85
NC
GND
A9
A8
A7
A6
A5

,...,n,...,~nr-tnr-t,...,n,...,,...,,...,

I 1111 II 1111 1111 11111111111

co co <

80~

C§ 8 8

(\J

0 0'<'2

Oz

.Y.

< co c.>

t§U ul~pl~

PlCC
TOP VIEW

C4
C3

2622 drw 03

GND

DIP
TOP VIEW
2622 drw 02

~

LOGIC SYMBOL

:!:

INDEX

b)

I

c.>co<

0

cI)~ 8ot§ 0(3 c'S~~I~

LlLlLJLlLJIIUUULlLJLl
Ao
A1
A2
A3
A4
Vee
GND
80
81
82
83
84

]7

6 5 4 3 2 u 484746 4544 43
1

]8

J9
] 10
] 11
] 12
] 13
] 14
] 15
] 16
] 17
] 18

L48-1
&
F48-1

421::
41 [:
401::
39 [:
38 [:
371::
36 [:

351::
34 [:
33 [:
321::
31 [:

89
88
87
86
Vee
85
GND
A9
A8
A7
A6
A5

192021222324252627282930
~r"""IP"""I""'P"'""'IP"""I""''''''''-''''''P'''''''I'''''

11111111111 IIII

C0

II

IIII

III

86[)O

C§88
co

&

PlCC
TOP VIEW
2622 drw 05

6.29

2

IDT49FCT804A1C
HIGH·SPEED TRI·PORT BUS MULTIPLEXER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE- BUS CONTROL

PIN DESCRIPTION
Name

Type

Ao· A9

1/0

Description
A port 1/0

Sl

OE=O LE=O
So DAB DCB DCA APORT BPORT CPORT RAMOE

Bo· B9

110

B port I/O

0

0

0

X

X

0

I

Co· C9

110

C port I/O

0

0

1

X

X

I

0

RAMOE

0

Asserted (LOW) when B to A or B to C
paths are enabled

0

1

X

1

X

0

1

X

0

X

Z
Z

1

0

X

X

0

I

1

0

X

X

1

0

1

1

X

X

X

Z

I

LEA

I

Active low enable for A port input latch

LEs

I

Active low enable for B port input latch

LEe

I

Active low enable for C port input latch

SO,S1

I

Path selection inputs

Z
Z

H

0

I

H

I

0

L

Z
Z
Z

0

H

I

H

Z

H

L

NOTE:
2622 tbl 02
1. H = HIGH, L = LOW, I = IN, 0 = Out, Z = High Impedance, X = Don't Care

DAB

I

Direction control for AB path

DCB

I

Direction control for CB path

DCA

I

Direction control for CA path

OEA

I

Output enable control for A port

LE

Operation

OEs

I

Output enable control for B port

0

Transparent

Output enable control for C port

1

Port Data Latched

LATCH OPERATION

OEe

I

GND 1·3

PWR

One ground for each port (Noisy ground)

GND4

PWR

Signal ground (Quiet ground)

VCC 1·2

PWR

+5V power supply

2622tb103

2622tbiOt

ABSOLUTE MAXIMUM RATINGS(1)

CAPACITANCE

Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
TA
Operating
Temperature

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

o to +70

-55 to +125

°C

TSIAS

-55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

TSTG

Temperature
Under Bias
Storage
Temperature

PT

Power Dissipatior

0.5

0.5

W

lOUT

DC Output
Current

120

120

mA

(TA

= +25°C, f = 1.0MHz)

Parameter > 0

I

L.-I

GNDB

<

~ :x:
0 0

16[:

GNDs

15[:

084
085

14[:
9 10 11 12 13
r-t r-t r-t r-t r--t
I

I

I

I~

DIP/SOIC/CERPACK
TOP VIEW

II

I

I

I

I

I

< co co z
zzra
-0 0

~

LCC
TOP VIEW

2574 drw 01

2574 drw 02

IDT49FCT806
VCCA
OAl
0A2

2
3

OA3
GNDA

4
5

P20-1
D20-1
8020-2
&
E20-1

082

17

083

16

GNDs

15

I

GNDA

:] 5

084

OA4

:] 6

14

085

Oi'i:s
GNDo

:J 7
:J 8

8

13

OE"A

9

12

MON
DEs

10

11

INs

I.'

3

:] 4

GNDa

I

I";: ()< ()co I@
o ~ ~

L-I L-I I

0i'i:3

7

6

~

"

081
18

OA4
OAs

INA

INDEX

VCCB

2

U

I
"
II
I ........ L--I

1

20 19
18[:

082

17[:

083

L20-2

16[:

GNDs

15[:

084

14[:

085

II

9 10 11 12 13
r-t r-t r - t r-t r--t
I

II

II

I

I

II

I

IZ
K)~~~~
~ <

DIP/SOIC/CERPACK
TOP VIEW

co co

LCC
TOP VIEW

2574 drw04

2574 drw05

FUNCTION TABLE(1)

PIN DESCRIPTION
Pin Names
OEA,OEs
INA,lNs
OAn,08n
MON

Outputs

Description
3-State Output Enable Inputs (Active LOW)
Clock Inputs
Clock Outputs
Monitor Output

Inputs

49 FCT80S

OEA,OEB INA,INB OAn,OBn

25741b105

OAn,OBn

MON

H

L

L

L

L

H

L

H

H

H

L

L

H

L

L

H

Z
Z

H

H

Z
Z

NOTE:
1. H = HIGH, L = LOW, Z

6.30

49FCT806

MON

H

L
25741b106

= High Impedance

2

lOT49FCT805/806/A
FAST CMOS BUFFER/CLOCK DRIVER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERW 3) Terminal Voltage
with Respect to
GND

CAPACITANCE

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

(TA - +25°C, f ... 1.0MHz)

Parameter(1)

Symbol

Conditions

Typ.

Max.

Unit

CIN

Input
Capacitance

VIN - OV

6

10

pF

GoUT

Output
Capacitance

VOUT- OV

8

12

pF

NOTE:

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipatior

0.5

0.5

W

lOUT

DC Output
Current

120

120

mA

NOTE:

25741b102

1. This parameter is measured at characterization but not tested.

TA

2574tbiOl

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may
exceed Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals.
3. Output and 1/0 terminals.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C; VCC = 5.0V ± 5%, Military: TA = -55°C to +125°C; vec= 5.0V

± 10%

Min.

Typ.(2)

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

Vil

Input LOW Level

Guaranteed Logic LOW Level

-

-

0.8

V

IIH

Input HIGH Current

Vee ... Max.

VI- Vee

-

-

5

J.l.A

-

-

-5

J.l.A

10

J.l.A

-10

J.l.A

-

-0.7

-1.2

V

-60

-120

-225

mA

IOH =-12mA MIL.
IOH '" -15mA eOM'L.

3.6

4.3

-

V

IOH '" -24mA MIL.
IOH .. -24mA eOM'L.

2.4

3.8

-

V

IOl ... 48mA MIL.
IOl ... 64mA COM'L.

-

0.3

-

200

Symbol

Test Condltlons(1)

Parameter

III

Input LOW Current

Vee ... Max.

VI- GND

10ZH

Off State (HIGH Z)

Vee .. Max.

Vo .. vee

10Zl

Output Current

VIK

Clamp Diode Voltage

Vee - Min., IN - -18mA

los

Short Circuit Current

Vee .. Max,<3), Vo .. GND

VOH

Output HIGH Voltage

Vee- Min.
VIN = VIH or Vil

VOL

Output LOW Voltage

VH

Input Hysteresis for all inputs

Vo- GND

Vee", Min.
VIN .. VIH or Vil

Vee - 5V

NOTES:

Max.

Unit
V

V

0.55

-

mV
25741bI03

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

6.30

3

IDT49FCT805I806/A
FAST CMOS BUFFER/CLOCK DRIVER

UIUTARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol
lee

Parameter
Quiescent Power Supply Current

leeD

Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current(4)

Ie

Total Power Supply Current(S)

.1 lee

Typ.(2)

Max.

Vee - Max.
VIN - GND or Vee

-

0.2

1.5

Unit
mA

Vee - Max.
VIN _ 3.4V<3)

-

0.5

2.0

mA

Test Condltlons(1)

Min.

Vee - Max.
Outputs Open
OEA - OEs - GND
Per Output Toggling
50% Duty Cycle

VIN- Vee
VIN- GND

-

0.15

0.25

mAl
MHz

Vee - Max.
Outputs Open
f i-10MHz
50% Duty Cycle
OEA - OEs - GND
Five Outputs Toggling

VIN- Vee
VIN-GND

-

7.7

14.0

mA

VIN -3.4V
VIN -GND

-

8.0

15.0

Vee - Max.
Outputs Open
f i-2.5MHz
50% Duty Cycle
OEA - OEs - GND
Eleven Outputs
Toggling

VIN - Vee
VIN- GND

-

4.3

8.4(5)

VIN -3.4V
VIN -GND

-

4.8

10.4(5)

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vee or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the lee formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IiNPUTS + IDYNAMIC
Ic = lee + alee DHNT + leeD (fcp/2 + fiNo)
lee = Quiescent Current
alee = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
leeD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fI = Input Frequency
No = Number of Outputs at fI
All currents are in milliamps and all frequencies are in megahertz.

6.30

25741b104

4

IDT49FCT80S/806/A
FAST CMOS BUFFER/CLOCK DRIVER

IolIUTARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
lOT49FCT805/S06

Symbol

Parameter

tPLH
tPHL

Propagation Delay
INA to OAn, INB to OSn

tPZL
tPZH

Output Enable Time
OEAtoOAn.
OEBtoOSn
Output Disable Time
OEAtoOAn,
OEBto OBn

tPLZ
tPHZ
Tskew(0)(3)
Tskew(t)(3)
Tskew(p)(3)

Condltlon(1)
CL - SOpF
RL-

soon

Skew between two outputs of
same package (same transition)
Skew between opposite transitions
(tPHL-tPLH) of same output
Skew between two outputs of
different package at same
temerature (same transition)

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew measured at worse case temperature (max. temp.).

Mln.(2)

1.5

IOT49FCTS05A1S06A

Mil.

Com'l.

Mil.

Com'l.
Max.

Mln,<2)

Max.

Unit

S.S

1.S

6.0

ns

1.5

8.0

1.5

8.5

ns

7.5

1.S

7.0

1.5

7.5

ns

-

0.6

-

O.S

-

0.6

ns

0.6

-

0.7

-

0.6

-

0.7

ns

1.0

-

1.2

-

1.0

-

1.2

ns

Max.

Mln.(2)

Max.

Mln,<2)

7.0

1.S

8.0

1.S

1.5

S.O

1.5

8.5

1.5

7.0

1.S

-

0.5

-

2574tbl07

6.30

5

IDT49FCTSOS/S06/A
FAST CMOS BUFFER/CLOCK DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION

TEST CIRCUITS FOR ALL OUTPUTS

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

2574 ttll 09
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

PULSE WIDTH

-= ~~V

J

.-.,...-..____ -

OV

-

3V

tsu----t0j4---+i

TIMING
INPUT _ _ _ _ _ _,

LOW-HIG~UL~~

,_-+____ _ 6;JV

ASYNCHRONOUS CONTROL
PRESET - - - - , ~-+---+---­ - 3V
- - + - - - - - - 1.SV
CLEAR
- OV
ETC. - - - - " "
SYNCHRONOUS CONTROL
CLOCK

:~~~t~ vvJr
l
~sU
ETC.

t

=f

HIGH-LOW-HIGH
PULSE

~ 15V
tw

_ _ 1.SV

- 3V
-1.SV
.-.,...-..---- - OV

PROPAGATION DELAY

I

ENABLE AND DISABLE TIMES
ENABLE

DISABLE
3V

SAME PHASE
INPUT TRANSITION

OV
OV
3.SV

OUTPUT

VOH
-1.SV

VOL

VOL

OUTPUT
NORMALLY
HIGH

3V

OPPOSITE PHASE
INPUT TRANSITION

VOH

SWITCH
OPEN
OV

NOTES
2574 drw 05
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate:!> 1.0 MHz; ZO:!>
tF:!> 2.Sns;
tR:!> 2.Sns.

son;

6.30

6

IDT49FCTSOS/S06/A
FAST CMOS BUFFER/CLOCK DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT49FCT

xxx

xx

x

Device Type

Package

Process/
Temperature
Range

Y:1ank

P
D
'----------1 E
L
SO

L..-_ _ _ _ _ _ _ _ _ _ _~

Commercial
Military (-5S0C to +12S0C) Compliant to
MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC

80S
806
80SA

Non-Inverting Buffer/Clock Driver
Inverting Buffer/Clock Driver
Fast Non-Inverting Buffer/Clock Driver

806A

Fast Inverting Buffer/Clock Driver
2574 drw 07

6.30

7

G

PRELIMINARY
IDT49FCT818
IDT49FCT818A

HIGH-SPEED
OCTAL REGISTER
WITH SPCTM

Integrated Device Technology, Inc.

FEATURES:

• Product available in Radiation Tolerant and Radiation
Enhanced versions

• High-speed, non-inverting 8 bit parallel register for any
data path, control path or pipelining application
• New, unique command capability which allows for
multiplicity of diagnostic functions
• High-speed Serial Protocol Channel (SPCN) provides
- Controllability:
- Serially scan in new machine state
- Load new machine state "on the fly"
- Temporarily force Y output bus
- Temporarily force data out the D input bus (as in
loading WCS)
- Observability:
- Directly observe D and Y buses
- Serially scan out current machine state
- Capture machine state "on the fly"
• IOL = 32mA (commercial) and 24mA (military)
• CMOS power levels (1 mW typo static)
• TIL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than 29818 and
54/74AS818 (5JlA max.)
• Available in plastic and sidebraze DIP, SOIC, LCC and
CERPACK

• Military product compliant to MIL-STD-883, Class B

DESCRIPTION:
The IDT49FCT818 is a high-speed, general purpose octal
register with Serial Protocol Channel (SPC). The D-to-Ypath
of the octal register provides a data path that is designed for
normal system operation wherever a high-speed clocked
register is required.
The SPC command and data registers are used to observe
and control the octal data register for diagnostic purposes.
The SPC command and data registers can be accessed while
the system is performing normal system function. Diagnostic
operations can then be performed "on the fly", synchronous
with the system clock, or can be performed in the "single step"
environment. The SPC port utilizes serial data in and out pins
(a concept originated at IBM) which can participate in a serial
scan loop throughout the system. Here normal data, address,
status and control registers are replaced with the
IDT49FCT818. The loop can be used to scan in a complete
test routine starting point (data, address, etc). Then, after a
specified number of clock cycles, the data can be clocked out
and compared with expected results.
As well as diagnostic operations, SPC can be used for
initializing.at power-on time functions such as Writable Control
Store (WCS).

FUNCTIONAL BLOCK DIAGRAM
SOl
07-0

SCLK

I

r-----.

C/U

SERIAL
PROTOCOL
DATA
AND
COMMAND
REGISTERS

PARALLEL
DATA REGISTER

PCLK

AJ~----------~~OEy

2627 drw Ot

Y7-0

SDO
CEMOS and SPC are trademarks of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
1l:l1990 Integrated Device Technology. Inc.

6.31

JUNE 1990
DSC-4600/-

1

I

IDT49FCT818/A
HIGH·SPEED OCTAL REGISTER WITH SPC'M

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
QEy

Vee

SCLK

c/O

07

~liliUfsH~

Y7
Ys
Ys
Y4
Y3
Y2
Y1
Yo

D6
05
04

03
02
01

Do
SOl
GNO

Os :]5
1
25[:
05 :]6
24 [:
04 :]7
23 [:
NC :]8
L28-1
22 [:
OJ :]9
21 [:
02 :]10
20[:
01 :]11
19 [:
12131415161718

Ys
Y4
NC

Y3
Y2
Y1

,..., ,...., ,--, r-1 ,..., ,..., ,...,

'11'1

I.

"

1'1"

SOO
PCLK
DlP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW

2627 drw 02

LOGIC SYMBOL

2627 drw 03

FUNCTION TABLE(1)
X
X
X

X
X
X

X
I
/

H

D
Function
Y
X High Z Tri·state Y

L

H

H

Clock D to Y

L

L

L

Clock D to Y

H

/

X

X

X

X

Shift Bit into SPC
Command Register

L

/

X

X

X

X

Shift Bit into SPC
Oata Register

\.

/

H or L
(Static)

X

X

X

Excute SPC
Command during time
Between C/O & SCLK

CID

07
SOO
PCLK

C/O

Y6

DEy
Yo Y1 Y2 Y3 Y4 Ys Ys Y7

2627 drw 04

SCLK PCLK

DEy

NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level

26271b101

X = Don't care
Z = High Impcdnnce
Y = Trnnsition, High-to-Low or Low-to-High

PIN DESCRIPTION
Pin Names
PCLK

lID
I

Description
Parallel Oata Register Clock

= LSB, 07 = MSB)
= LSB, Y7 = MSB)

07-0

I/O

Parallel Oata Register Input Pins (Do

Y7-0

110

Parallel Oata Register Output Pins (Yo

OEy

I

SOl

I

SOO

0

Output Enable for Y Bus (Overidden by SPC Ins!. 8 and 14)
Serial Oata In for SPC Operation, Oata and Command Shifts in the Least Significant Bit First
Serial Data Out for SPC Operation, Oata and Command Shifts Out the Least Significant Bit First

C/O

I

Mode Control for SPC

SCLK

I

Serial Shift Clock for SPC Operations
2627tbl02

6,31

2

IDT49FCT818/A
HIGH-SPEED OCTAL REGISTER WITH SPCTM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1}
Symbol
Rating
VTERM(2) Terminal Voltage
with Respec1 to
GND
VTERM(3) Terminal Voltage
with Respect to
GND

CAPACITANCE

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

TA

Operating
Temperature

o to +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output
Current

120

120

mA

(TA= +25°C,

Parameter(1)

f = 1.0MHz)

Conditions

Typ.

Max.

Unit

CIN

Input
Capacitance

VIN = OV

6

10

pF

CliO

1/0 Capacitance

VOUT = OV

8

12

pF

Symbol

NOTE:
2627tbl04
1. This parameter is guaranteed by characterization and not tested.

NOTES:
2627 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +O.5V unless otherwise noted.
2. Input and Vcc terminals only.
3. Outputs and 1/0 terminals only.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C, VCC = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc= 5.0V
Symbol

Parameter

Test Conditions(1)

± 10%

Min.

Typ.!2)

Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

0.8

V

hH

Input HIGH Current

Vee = Max.

-

jlA

IlL

hH

(Except 1/0 pins)

VI = 2.7V

-

-

5
5(4)

Input LOW Current

VI = 0.5V

-

-

-5(4)

(Except 1/0 pins)

VI = GND

-

-

-5

VI = Vee

-

-

15

VI = 2.7V

-

-

15(4)

Input LOW Current

VI = 0.5V

-

-

-15(4)

(1/0 pins only)

VI = GND

-

-

Input HIGH Current

VI = Vee

Vee = Max.

(1/0 pins only)
hL

-

VIK

Clamp Diode Voltage

Vee = Min., IN = -18mA

los

Short Circuit Current

Vee = Max.(3), Vo= GND

VOH

Output HIGH Voltage

Vee = 3V, VIN = VLC or VHC, IoH = -32JlA

VOL

Output LOW Voltage

-0.7

-15

VHC

Vcc

Vee = Min.

IoH = -300~lA

VHe

Vee

-

VIN = VIH or VIL

IoH = -12mA MIL.

2.4

4.3

-

IoH = -15mA COM'L.

2.4

4.3

-

Vee = 3V, VIN = VLe or VHe, IoL = 300~lA
Vee = Min.

IoL = 300~lA

VIN = VIH or VIL

IoL = 24mA MIL.
IoL = 32mA COM·L.

-120

-

GND

VLe

GND

VLd 4)

0.3

0.5

0.3

0.5

NOTES:
1. For conditions shown as Max. or Min, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25"C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
6.31

jlA

-1.2

-

-60

V

V
mA
V

V

2627 tbl 05

3

I

IDT49FCT818fA
HIGH·SPEED OCTAL REGISTER WITH SPCTM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = O.2V; VHC = VCC - O.2V
Symbol
icc

to icc
Iceo

Test Conditions(l)

Parameter
Quiescent Power Supply Current

Vcc = Max.
VIN ~ VHC' VIN ~ VLC

Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Curreni 4 )

Vcc = Max.
VIN = 3.4 V(3)
Vcc = Max.

VIN ~ VHC

Outputs Open

VIN ~ VLC

Typ)2)

Max.

Unit

-

0.2

1.5

mA

-

0.5

2.0

mA

-

0.15

0.25

Min.

mAl
MHz

OEv= GND
One Input Toggling
50% Duty Cycle
Ic

Total Power Supply Curren~5)

Vcc = Max.

VIN ~ VHC

Outputs Open

VIN ~ VLC

fcp = 10MHz

(FCT)

-

1.7

4.0

-

2.2

6.0

-

4.0

7.8(5)

-

6.2

16.8(5)

mA

50% Duty Cycle
OEv = GND
One Bit Toggling

VIN = 3.4V

at fl = 5MHz

VIN = GND

50% Duty Cycle
SCLK = C/O = Vcc
SOl = Vcc
Vcc = Max.

VIN ~ VHC

Outputs Open

VIN ~ VLC

fcp = 10MHz

(FCT)

50% Duty Cycle
OEv = GND
Eight Bits Toggling

VIN =3.4V

at fl = 2.5MHz

VIN = GND

50% Duty Cycle
SCLK = C/O = Vcc
SOl = Vcc
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vec or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Ie = IQUIESCENT + IINPUTS + IDYNAMIC
Ie = Icc + ~Icc DHNT + ICCD (fcPf2 + fiNi)
lec = Quiescent Current
t.lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
lecD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.31

2627tbl06

4

IDT49FCT818/A
HIGH-SPEED OCTAL REGISTER WITH SPCTM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT818A

IDT54174FCT818

Symbol

Parameter

Condition(1)

Com'l.

Mil.

Com'l.

MIL

MinJ2) Max. MinJ2) Max. MinJ2) Max. MinJ2) Max.

tPHL

T1

PCLK etta V

CL = 50pF

3.0

12.5

3.0

14.0

3.0

9.0

3.0

10.0

tPLH

T2

SCLK et to SOO

RL = 500n

3.0

20.0

3.0

22.0

3.0

14.0

3.0

15.0

3.0

20.0

3.0

22.0

3.0

14.0

3.0

15.0

3.0

16.0

3.0

18.0

3.0

13.0

3.0

14.0

3.0

20.0

3.0

22.0

3.0

13.0

3.0

14.0

3.0

12.5

3.0

14.0

3.0

10.0

3.0

11.0

T3

SOlto SOO

Unit
ns

I(in stub mode)
T4

C/O 0to V

I(OEY= Low Inst. 8 & 14)
T5 SCLK etta V

tsu

I(OEY = Low, Inst. 8 & 14)
T6 C/O to SOO
1(lnst. 0, 1,2 & 4)
S1
to PCLK et

o

2.5

-

3.0

-

2.5

-

3.0

-

S2

C/O to SCLK et

12.0

-

14.0

-

12.0

14.0

S3

SOl to SCLK et

4.0

-

5.0

-

4.0

-

S4

Vor 0 to C/O 0
(Inst. 0, 2 & 4)

2.0

-

2.5

-

2.0

-

2.5

-

C/O (Low) to PCLK et

8.0

-

9.0

-

8.0

-

9.0

-

S5

5.0

ns

I(Inst. 3 & 13)

tH

S6

Vto PCLK et

1.0

-

1.5

-

1.0

-

1.5

-

H1

(lnst.3)
to PCLK et

o

2.0

2.5

2.0

2.5

H2

C/O to SCLK 0

12.0

14.0

12.0

14.0

H3

SOl to SCLK et

1.0

-

1.0

-

1.0

-

1.0

-

H4

Vor 0 to C/O 0
[(Inst. 0, 2 & 4)

2.0

-

2.5

-

2.0

-

2.5

-

H5

SCLK (Low) to PCLK et
I (Inst. 3 & 13)

2.0

-

2.5

-

2.0

-

2.5

-

C/O (Low) to PCLK et

2.0

-

2.5

-

2.0

-

2.5

-

-

4.5

-

5.0

-

H6

ns

I

I(Inst. 3 & 131
H7

V to PCLK et (Inst. 3)

4.5

-

5.0

tPHZ

1Z

OEYto V

3,0

10.0

3.0

11.0

3.0

8.0

3.0

9.0

tPLZ

2Z

SCLK et to 0 (Inst. 5 & 9)

3.0

13.0

3.0

14.0

3.0

10.0

3.0

11.0

3Z

C/O et to 0 (Inst. 5 & 9)

3.0

13.0

3.0

14.0

3.0

10.0

3.0

11.0

4Z

SCLK et to V (OEY = High
Inst. 8 & 14)
C/O et to V (OEy = High

3.0

13.0

3.0

14.0

3.0

10.0

3.0

11.0

3.0

13.0

3.0

14.0

3.0

10.0

3.0

11.0

5Z

ns

Inst.14)
tPZH

Z1

OEYto V

3.0

11.0

3.0

12.0

3.0

9.0

3.0

10.0

tPZL

Z2

C/O 0to 0 (Inst. 5 & 9)

3.0

14.0

3.0

15.0

3.0

10.0

3.0

11.0

Z3

C/O 0to V (OEY = High
Inst. 14)

3.0

14.0

3.0

15.0

3.0

10.0

3.0

11.0

W1

PCLK (High & Low)

tw

7.0

-

8.0

-

7.0

-

8.0

-

W2 SCLK (High & Low)

25.0

-

25.0

-

25.0

-

25.0

-

W3 C/O (High)

25.0

-

25.0

-

25.0

-

25.0

-

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

ns

ns

2627 tbl 07

6.31

5

IDT49FCT818/A
HIGH-SPEED OCTAL REGISTER WITH SPCrM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

GENERAL AC WAVEFORMS FOR PARALLEL INPUTS AND OUTPUTS
PCLK

D

y

OEv
2627 drw 05

GENERAL AC WAVEFORMS FOR SERIAL PROTOCOL INPUTS AND OUTPUTS

SCLK

SDI

-..£\1
I
I@ ~hw-I®
=tJ-F
®

®1tSu\~®

soo

i.•t~

®

tH

(DECODE)

tsu

@

(EXECUTE)

c/o

2627 drw 06

6.31

6

IDT49FCT818/A
HIGH-SPEED OCTAL REGISTER WITH SPcrM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DETAILED WAVEFORMS FOR SERIAL PROTOCOL OPERATIONS
PARALLEL DATA REGISTER -SPCData(lns!.1)
SET SERIAL MODE (Ins!. 11)
SET STUB MODE (Ins!. 12)

Y - S P C Data (Ins!. 0)
o - S P C Data (Ins!. 2)
Status - S P C Data (Ins!. 4)
SCLK

C/O"

0, Y,OE,
PCLK

SDO

SCLK

®~'H~
--{

I

c/O"
Isu

)--

SDO

®~®

Ff®-T6--

2627 drw 07

2627 drwoa

SPC Data PARALLEL DATA REGISTER (Ins!. 10)
SPC Data - Y (Ins!. 8)
CONNECT D TO Y (Ins!. 14)

CONNECT Y TO 0 (Ins!. 5)
SPC Data 0 (Inst. 9)
SCLK
CIIT

o

SCLK

r
i

rc I

CIIT

Y

-ba-'~~

I

14-'

I

2627 drw 09

Y - . . SPC Data SYNCHRONOUS W/PCLK (Ins!. 3)

2627 drw 10

SPC Data -

SCLK

PARALLEL DATA REGISTER SYNCHRONOUS
WI PCLK (Ins!. 13)

SCLK

I
C/O

C/O

PCLK

PCLK

-{r®1
®

-@
Y

I

~ZZZZZZZZZ

n

I
®

tH
tH

2627 drw 11

®

2627 drw 12

6.31

7

IDT49FCT818/A
HIGH·SPEED OCTAL REGISTER WITH SPC'"

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DETAILED FUNCTIONAL BLOCK DIAGRAM

o

SOl

1---

-SERIALPROTOCO~OMMAND~AT~EGISTERS---l

1

1

1

1

I
I
1

CID

--L..-_.....-.j.--l

PCLK

SCLK _ .......- 4 - - - - l

1:)----

QEv

1

I
1
1_ _ _ _ -

y

SDO
The detailed block diagram consists of two main elements:
the parallel data register and the SPC data /command registers.
The main data path is from the 0 inputs down to the data
register and through the Y outputs. This path is typically used
during standard operations. For diagnostic or systems
initialization, the internal SPC data path is used. This path
allows access between the SPC data and command registers
and the standard data path, pins and data register. The SPC
da.!.9 and command registers are accessed via the SOl, SDO,
C/O and SCLK pins.
C/O

CID

XFER
(EXECUTE
SPC
COMMAND)

SCLK

CID

SCLK

SPC
COMMAND
REGISTER

XFER

SDO
SCLK

2627 drw 13

SPC
DATA
REGISTER

2627 drw 15
2627 drw 14

SPC FUNCTIONAL DESCRIPTION
The Serial Protocol Channel (SPC) has been optimized for
the minimum number of pins and the maximum flexibility. The
data is passed in on a Serial Data Input pin (SOl) and out on
a Serial Data Output pin (SDO). The transfer of the data is
controlled by a Serial Clock (SCLK) and a Command/Data
mode input (C/O). These four pins are the basic SPC pins. To
the outside, the SPC appears as two serial shift registers in
parallel - one for command and the other data. The serial
clock shifts data and the Command/Data (C/O) line selects

which register is being shifted. The command register is used
to control loading of data to and from the data register with
other storage elements in the device.
With respect to executing an SPC command, there are four
distinct phases: (1) data is shifted in, (2) followed by the
command, (3) the command is executed, and (4) data is
shifted out. During the data mode, data is simultaneously
shifted into the serial data registerwhile the data inthe register
is shifted out. During the command mode, opcode-type
information is shifted through the serial ports. The command

6.31

8

IDT49FCT818/A
HIGH-SPEED OCTAL REGISTER WITH SPC'"

MILITARY AND COMMERCIAL TEMPERATURE RANGES

is executed when the last bit is shifted in and the C/O line is
brought LOW. The execution phase is ended with the next
serial clock edge.
SPC data and commands are shifted in through the SOl pin,
which is a serial input pin, and out through the SDO pin, which
is a serial output pin. Data and commands are shifted in Least
Significant Bit first; Most Significant Bit last (Yo = LSB,
Y7 = MSB). Execution of SPC commands is performed by
stopping the shift clock, SCLK, and lowering the C/O line from
HIGH-to-LOW. Later SCLK may then be transitioned from
LOW-to-HIGH. SPC commands and data can be shifted
anytime without rE~gard for operation. During the execution
phase, care must be taken that there is no conflict between
the SPC operation and parallel operation. This means that if
the SPC operation attempts to load the parallel data register
(opcode 10) while PCLK is in transition, the results are
undefined. In gen,eral, it is required that PCLK be static during
SPC operations. The synchronous commands (opcode 3
and 13), however, allow PCLK to run. In these operations, the
HIGH-to-LOW transition of the C/O line takes on the function
of an arm signal in preparation for the next LOW-to-HIGH
transition of PCLK.

Opcode 0 is used for transferring data from the Y output
pins into the SPC data register. Opcode 1 transfers data from
the output of the parallel data register, before the tri-state gate,
into the SPC data register. Opcode 2 transfers data from the
input pins into the SPC data register.

o

Y _SPC Data (Ins!. 0)
SOl

0

SERIAL
PROTOCOL
SCLK
PCLK

ClD
.t:>-----OEy

SOO

Y

2627 drw 16

SPC COMMANDS
Data Register _

There are 16 possible SPC opcodes. Fourteen of these are
utilized, the other two are reserved and perform NO-OP
functions. The top eight opcodes, 0 through 7, are reserved for
transferring data into the SPC data register for shifting out.
The lower eight opcodes, 8 through 15, are used fortransferring
data from the SPC data register to other parts of the device.
Two of the commands are also used for connecting the data
in and out pins.
Opcode

Y to SPC Data Register

1

Parallel Data Register to SPC Data Register

o to SPC Data Register

3

Y to SPC Data Register Synchronous w/PCLK

4

Status (OEY, PCLK) to SPC Data Register

5

Connect Y to 0

8

SCLK

ClD

2

6-7

SERIAL
PROTOCOL

SPC Command

0

SPC Data (Inst. 1)

0

SOl

DATA

&
COMMAND

SOO

Y

2627 drw 17

ReseNed (NO-OP)
SPC Data to Y (OEY is Overidden)

9

SPC Data to 0

10

SPC Data to Parallel Data Register

D_SPC Data (Ins!. 2)
SOl

11

Select Serial Mode

12

Select Stub Mode

13
14

SPC Data to Parallel Data Register Synchronous
w/PCLK
Connect 0 to Y (OEy is Overidden)

15

NO-OP

0

SERIAL
PROTOCOL
SCLK

CfD

DATA
&
COMMAND

PCLK

of-----OEy
REGISTERS

2G27 till 08

SOO
6.31

Y

2G27 drw 18

9

IDT49FCT818/A
HIGH-SPEED OCTAL REGISTER WITH SPcrM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Opcode 3 transfers data on the Y pins to the SPC data
register on the next PCLK, thus achieving a synchronous
observation of the Y data pins in real time. This operation can
be forced to repeat without shifting in a new command by
pulsing C/O LOW-HIGH-LOW after each PCLK. As soon as
data is shifted out using SCLK, the command is terminated
and must be loaded in again.
Y-

Opcode 5 connects Y to D. Opcodes 6 and 7 are reserved,
hence designated NO-OP.
Connect Y to D (Inst. 5)
SOl

SPC Data Synchronous w/PCLK (Inst. 3)
SOl

0
SCLK

SERIAL
PROTOCOL
SCLK
C/O

C/O
~

____ OE"v

DATA
&
COMMAND
REGISTERS

SOO

y

SOO

SPC Data _

2627 drw 19

Opcode 4 is used for loading status into the SPC data
register. The format of bits is shown below.

SOl

2627 drw 20

Y

Y (Inst. 8)

o

SERIAL
PROTOCOL
SCLK
C/O
2G27 drw 22

DATA
&
COMMAND
~

____ OE"v

REGISTERS
Status _
SOl

SPC Data (Inst. 4)
SOO

Opcode 8 is used for transferring SPC data directly to the
Y pins. When executing opcode 8, the state of OEv is a "do not
care"; that is, data will be output even if OEv = HIGH. Opcode
9 is used for transferring SPC data to the D pins. Operands 8
and 9 can be temporarily suspended by raising the C/O input
and resumed by lowering C/O. As soon as SCLK completes
its LOW-to-HIGH transition, the command is terminated.

SERIAL
PROTOCOL
SCLK
C/O

2627 drw 21

0

DATA
&
COMMAND
REGISTERS

SOO

y

2627 drw 23

6.31

10

IDT49FCT818/A
HIGH·SPEED OCTAL REGISTER WITH SPC'"

SPC Data _

MILITARY AND COMMERCIAL TEMPERATURE RANGES

InStubmode, SDI isconnecteddirectlytoSDO.lnthisway,
the same diagnostic command can be loaded into multiple
devices of like type. For example, in four clock cycles the same
command could be loaded into 8 IDT49FCT818s (64·bit
pipeline register). Dissimilar devices must be segregated into
serial scan loops of similar type, as shown below. During the
command phase, the serial shift clock must be slowed down
to accommodate the delay from SDI to SDO through all of the
devices. The slower clock is typically a small tradeoff compared
to the reduced number of clock cycles.

D (Inst. 9)

SOl

SERIAL
PROTOCOL
SCLK
C/O

DATA
&
COMMAND

PCLK
,o-_ _ _ _ 0E"v

STUB MODE

REGISTERS
DEVICE #2

DEVICE #3

DEVICE #4

SOl -+--.-~r--,--+~-~~~SOO
SOO

y

2627 drw 24

Opcode 10 is used for transferring data from the SPC data
register into the parallel data register, irrespective of the state
of PCLK. However, PCLK must be static between C/O going
HIGH-to-LOW and SCLK going LOW-to-HIGH.
SPC Data _

SOl

Parallel Data Register (Inst. 10)

SOl

0
Opcode 13 transfers data from the SPC data registerto the
parallel data register on the next PCLK. Opcode 14 connects
the D bus to the Y. Operation 14 can be temporarily suspended
by raising the C/O input and resumed by lowering the C/O
input again. The operation is terminated by SCLK.

SERIAL
PROTOCOL
SCLK
C/O

DATA

PCLK

&

COMMAND

SPC Data -

,(;r----0E"v

REGISTERS

Parallel Data Register Synchronous w/PCLK
(Inst. 13)

SOl

y

SOO

SERIAL
PROTOCOL

2627 drw 25

Opcodes 11 and 12 are used to set Se rial and Stub Mode,
respectively. After executing one of these opcodes, the device
remains in this mode until programmed otherwise. The Serial
mode is the default mode that the IDT49FCT818 powers up in.
In Serial mode, commands are shifted through the SPC
command register and then to the SDO pin. This is the typical
mode used when several varieties of devices that utilize the'
SPC access method are employed on one serial ring.

SCLK
C/O

DEVICE #2

DEVICE #3

DATA
&

COMMAND
REGISTERS

SOO

SERIAL MODE

DEVICE #1

DEVICE #4

0

y

2627 drw 28

DEVICE #5

SOl

SOO

2627 drw 27

6.31

11

II

IDT49FCT818/A
HIGH·SPEED OCTAL REGISTER WITH SPCTM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Opcodes 3· and 13 transfer data synchronous to PCLK
which means that the HIGH·to-LOWon the C/O input is an arm
signal. The data and command can be shifted in while PCLK
is running. The C/O line is dropped prior to the desired PCLK
edge and raised before the next edge. Instruction 13 can be
repeated over many times by leaving the C/O line LOW during
multiple transitions of PCLK while not clocking SCLK. PCLK
cycles can even be skipped by raising the C/O input during the
desired clock periods. Instruction 3 can be repeated by
pulsing C/O high after each PCLK. The ability to continuously

execute a synchronous command can provide major benefits.
For example, the synchronous read (Instruction 3, Y to SPC
data) instruction could be clocked into the SPC command
register. Then, it could be continuously executed by pulsing
the C/O line HIGH. When the whole system is stopped (PCLK
quiescent), the serial data register will contain the next to the
last state of the parallel data register. That value can be shifted
out and the current state of the parallel register can then be
observed, allowing for the observation of two states of the
parallel register (the current and the previous).

Connect 0 to Y (Inst. 14)

Cin
SOl
SCLK

SCLK
ClO

OATA

EXECUTE
(SPC CMO)

PCLK

&
COMMANO

PCLK

k-----O"E"v

2627 drw:xl

SDO

2627 drw 29

TYPICAL MICRO·PROGRAM APPLICATION WITH SPCTM

SOO

SOl

IOT49C410
SEQUENCER

SOO
IOT49C403
(w/SPC)
ALU WITH REGISTER FILE

WCS
I0T71981

SOl

SOO
SOl

SOl

SDO

2627 drw 31

6.31

12

IDT49FCT818/A
HIGH-SPEED OCTAL REGISTER WITH SPC'"

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TYPICAL APPLICATION
In the block diagram of the typical application, the SPC data
register is shown being used with a writable control store in a
microprogrammed design. The control store can be initialized
through the diagnostic path. The SPC data register is used for
the instruction register going into the lOT49C41 0, as well as
for data registers around the IOT49C403. In this way, the
designer may use the SPC data register to observe and
modify the microcode coming out of the writable control store,
as well as observing and being able to modify data and
instructions in the overall machine. The lOT49C403 is a 16-bit
version of the 2903A1203 which inciudes an SPC port for
diagnostic and break point purposes.
The block diagram of the diagnostics ring shows how
devices with diagnostics are hooked together in a serial ring
via the SOl and SOO signals. The diagnostics signals may be
generated through registers which are hooked up to a
microprocessor. This microprocessor could conceivably be
an IBM PC.

As companies like lOT continue to integrate more onto
each device and put each device into smaller packages such
as surface mount devices, the board level testing becomes
more complex forthe designer and the manufacturing divisions
of companies. To help this situation, serial diagnostics was
invented. This allows for observation of critical signals deep
within the system. During system test when an error is
observed, these signals may be modified in order to zero in on
the fault in the system.
Serial diagnostics is primarily a scheme utilizing only a few
pins (4) to examine and alter the internal state of a system for
the purpose of monitoring and diagnosing system faults. It can
be used at many points in the life of a product: design debug
and verification, manufacturing test and field service. This
document describes a serial diagnostic scheme which was
developed at lOT and will be used in future VLSllogic devices
designed by lOT.

•

6.31

13

I

IDT49FCT818/A
HIGH·SPEED OCTAL REGISTER WITH SPCI"

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vee

SWITCH POSITION
o-7.0V

soon

Switch
Closed

All Other Outputs

Open

DEFINITIONS:
2627 tbl 08
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

RT

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

Test
Open Drain
Disable Low
Enable Low

XX{

PULSE WIDTH

-= ~~V

J

"'-..x.._~ -

OV

-

3V

tsU~'i4--~

TIMING
INPUT

- - - I f - - - - - - - 1.SV

-

OV

ASYNCHRONOUS CONTROL
PRESET - - - -.....
CLEAR
ETC. _ _ _ _J

-

3V

-

OV

-

3V
l.5V
OV

--+------

1.SV

SYNCHRONOUS CONTROL
CLOCK

:~~~~~ ~
1
~tsu
ETC.

""'------"''--''

-

-

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

--------3V
SAME PHASE
INPUT TRANSITION

DISABLE
r-----3V
'1-----" - - l - - - - - OV

3.SV

OUTPUT

VOL

~
PLH

OPPOSITE PHASE
INPUT TRANSITION

VOL

tPHL

OUTPUT
NORMALLY
HIGH

3V

- - - - 1.SV
OV

VOH
OV

NOTES
2627 drw 32
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ 50n; IF ~ 2.5ns;
IR ~ 2.5ns.

6.31

14

IDT49FCT818/A
HIGH-SPEED OCTAL REGISTER WITH SPC'\I

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

XXXX

xx

x

Device fype

Package

Process
Commercial
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B

P
C

'-----------;E
L
SO
49FCT818

'------------------------------1 49 FCT818A

Plastic DIP
Sidebraze DIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Octal Register with SPC
High-Speed Octal Register with SPC
2627 drw 37

II

6.31

15

t;)®

IDT49C25
IDT49C25A

CMOS MICROCYCLE
LENGTH CONTROLLER

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• Similar function to AMD's Am2925 bipolar controller with
improved speeds and output drive over full temperature
and voltage supply extremes
• Four microcode-controlled clock outputs allow clock cycle
length control for 15 to 30% increase in system throughput. Microcode selects one of eight clock patterns from 3
to 10 oscillator cycles in length
• System controls for RUN/HALT and Single Step
- Switch-debounced inputs provide flexible halt controls
• Low input/output capacitance
- 6pF inputs (typ.)
- 8pF outputs (typ.)
• CMOS power levels (1 mW typo static)
• Available in 300 mil 24-pin plastic and ceramic THINDIP,
28-pin LCC and PLCC packages and CERPACK
• 80th CMOS and TIL output compatible
• Military product compliant to MIL-STD-883, Class 8

The IDT49C25/A are single-chip general purpose clock
generator/drivers built using IDT's advanced CEMOSTM, a
dual metal CMOS technology. It has microprogrammable
clock cycle length to provide significant speed-up over fixed
clock cycle approaches and meets a variety of system speed
requirements.
The IDT49C25/A generate four different simultaneous
clock out-put waveforms tailored to meet the needs of the
IOT3900 CMOS family and other MOS and bipolar
microprocessor-based systems. One of eight cycle lengths
may be generated under microprogram control using the cycle
length inputs, L 1, L2 and L3.
A buffered oscillator output, Fo, is provided for external
system timing in addition to the four microcode controlled
clock outputs, C1, C2, C3 and C4.
System control functions include RUN, HALT, Single-Step,
Initialize and Ready/Wait controls. In addition, the FIRSTi
LAST input determines where a halt occurs and the Cx input
determines the end point timing of wait cycles. WAITACK
indicates that the IDT49C25/A are in a wait state.

FUNCTIONAL BLOCK DIAGRAM

osc

----------~>-----------------------------------------_+----------~

Fa
C4

MICROCYCLE
CONTROL
LATCH

CLOCK
GENERATOR
REGISTER

CONTROL
STATE
DECODER

EN
FIRST/LAST
HALT
RUN
SSNC
SSNO

RUN/HALT
AND
SINGLE STEP
CONTROL

WAIT
CONTROL

1 - - - - - - - - -. .

WAIT ACK

~ ------------+-------------------------~

WAITREQ
READY
Cx

----------------------------------------~
----------------------------------------------~

--------------------------------------------------~

2550 drw 01

CEMOS and MICROSLICE are 1rademarks of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
0:>1990 Integrated Device Technology. Inc.

6.32

APRIL 1990
DSC-4628/·

1

IDT49C25/A
CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

>Vee

GND
READY
L1
L2
L3
C1
C2
C3
C4
SSNC
SSNO
GND

~o

l-

w Z 8xz..:::ia:CJ>t)I~
t)

INDEX

1

Cx
INIT
WAITREO
WAITACK
RUN
HALT
FIRST/LAST
OSC
NC
Fa

'r

L......J

L...J ~

4 3 2
L2
L3
C1
C2
C3
C4
NC

J5
J6
J7
J8

J9
JlO
J 11

"-

Vee

I I

L-J L......J L......J

I I

28 27 26

LJ

1

J28-1
L28-1

12 13 14 15 16 17 16

.....

25 [
24 [
23 [
22[
21 [
2a [
19 [

r--1"'--''''--''''-'

g~~~~gg

NC
WAITREO
WAITACK
RUN
HALT
FIRST/LAST
OSC

/
2550 drw 02

~~CJ

DIP/CERPACK
TOP VIEW

LCC/PLCC
TOP VIEW

PIN DESCRIPTIONS
Pin Names

Description

1/0

a

System clock outputs. These outputs are all active during every system clock cycle. Their timing is
determined by clock cycle length controls: L1, L2 and L3.

I

Clock cycle length control inputs. These inputs receive the microcode bits that select the microcycle
lengths. They form a control word which selects one of the eight microcycle waveform patterns F3
through FlO.

a

The buffered oscillator output. Fa internally generates all of the timing edges for outputs C1, C2, C3,
C4 and WAITACK. Fo rises just prior to all of the C1, C2, C3, C4 transitions.

HALT and RUN

I

Debounced inputs to provide HALT control. These inputs determine whether the output clocks run or
not. A LOW input on HALT (RUN = HIGH) will stop all clock outputs.

FIRST/LAST

I

HALTtime control input. A HIGH input in conjunction with a HALT command will cause a halt to occur
when C4 = LOW and C1 = C2 = C3 = HIGH (see clock waveforms). A LOW input causes a HALT to
occur when C1 = C2 = C3 = LOW and C4 = HIGH.

SSNO and SSNC

I

Single Step control inputs. These debounced inputs allow system clock cycle single stepping while
HALT is activated LOW.

WAITREQ

I

The Wait Request active LOW input. When LOW, this input will cause the outputs to halt during the
next oscillator cycle after the Cx input goes LOW.

Cx

I

Wait cycle control input. The clock outputs respond to a wait request one oscillator clock cycle after
Cx goes LOW. Cx is normally tied to anyone of C1, C2, C3 or C4.

a

The Wait Acknowledge active LOWoutput. When LOW, this output indicates that all clock outputs are
in the "WAIT" state.

C1, C2, C3, C4
L1, L2, L3

Fa

WAITACK
READY

I

The READY active LOW input is used to continue normal clock output patterns after a wait state.

INIT

I

The Initialize active LOW input. This input is intended for use during power-up initialization of the
system. When LOW, all clock outputs run free regardless of the state of the Halt, Single Step, Wait
Request and Ready inputs.

OSC

I

External oscillator input (TIL level input).
2550 Ibl 01

6.32

2

IDT49C25/A
CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

LOGIC DIAGRAM

W

STATE MACHINE DECODER
(6-AND-OR-INVERTER)

iN
C4

C4

K1 = C3C2C1H W + C1H + C1W

c4BUF~ERrFO I~

K2= C4C3E3E2E1HW + A2A1C4C3E3E2HW

+ A2A 1C3C2H W + C3C2C1 + C2H + C2W

C1

K3= C4C3E3E2E1H W + A2A1C4C3H W +

C1

C3C2 + C3C1 + C3H + C3W

A2

A2
A1

/\1

B, = A2C3E,H W + C4C3E1H W + A2A,C4C3

H

H

B2 = C4C3E2H W + A1C4C3E3H W + A2A1C4

,-:---------1

I
I

MICROCYCLE
CONTROL

r--+__~.L~ATCH

+

A1H· A1W

H W + A2C3H W + A2H + A2W

I'
I

I

EXAMPLE:
E3

E2

E1

A2

;~z

/\2

Z = AB + CD + EF

1--------------------------------,
STATE MACHINE CONTROL
FIRST/LAST

S

C1
RS
LATCH

C 1--+----1'",

R

S
SSNC

Q

I
I
I
I

I
I
I
HI
I
HI
I
I

RS
LATCH

I
I
I
I
I
I

R
SSNO
INIT
WAITREQ

I

Cx

I
I
W I

>---------~g-o-fi:n~-K_-_~~ _____________ 9__________~~A1TACK

D __
READY

2550 drw 03

6.32

3

IDT49C25/A
CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM(2)

CAPACITANCE

Rating

Commercial

Military

Unit

Terminal Voltage
with Respect
toGND

-0.5 to +7.0

-0.5 to +7.0

V

VTERM(3)

Terminal Voltage
with Respect
toGND

-0.5 to Vee

-0.5 to Vee

V

TA

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

NOTES:

Symbol

(TA = +25°C,

Parameter(l)

CIN

Input Capacitance

COUT

Output Capacitance

f = 1.0MHz)

Conditions

Typ.

Max.

= OV
VOUT = OV

6

10

pF

8

12

pF

VIN

NOTE:

Unit

2550 tbl 03

1. This parameter is guaranteed by characterization data and not tested.

2550 tbl 02

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vce by +O.5V unless otherwise noted.
2. Inputs and Vee terminals only.
3. Outputs and 110 terminals only.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - O.2V
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, VCC
Symbol

= 5.0V ± 10%

Test Conditions(1)

Parameter

Min.

Typ.(2)

Max.

Input HIGH Level

Guaranteed Logie HIGH Level

2.0

-

-

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

-

0.8

V

ilH

Input HIGH Current

Vee = Max., VIN = Vee

-

-

25

JlA

ilL

Input LOW Current

mA

VIK

Vee = Max.

SSNO,SSNC,RUN,HALT

-

-

-1.0

VIN = GND

FIRST/LAST

-

-

-1.5

Other Inputs

-

JlA
mA

-60

-120

Vee = 3V, VIN = VLC or VHe, IOH = -32JlA

VHe

Vee

-

Vee = Min.

IOH= -300JlA

VHe

Vee

-

IOH = -3.0mA MIL.

2.4

4.0

-

IOH= -5.0mA COM'L

2.4

4.0

Short Circuit Current
Output HIGH Voltage

Output LOW Voltage

-5

Vee = MaxP), Vo = GND

Ise
VOH

Vee = Min.
VIN = VIH or VIL

mA
V

-

IOL = 300JlA

-

IOL = 16mA MIL.

-

-

0.5

IOL = 24mA COM'L

-

-

0.5

Vee = 3V. VIN = VLC or VHe, IOL = 300JlA

V

-1.2

-0.7

Vee = Min., IN = -18mA

VOL

-

-

Clamp Diode Voltage

VIN = VIH or VIL

GND

VLe

GND

VLc'4)

NOTES:

1.
2.
3.
4.

Unit

VIH

V

2550 tbl 04

For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at vee = 5.0V, +25°C ambient and maximum loading.
Not more than one output should be shorted at one time. Duration of the short circiut test should not exceed one second.
This parameter is guaranteed but not tested.

6.32

4

IDT49C25/A
CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC

= O.2V; VHC = VCC - O.2V

Symbol

Test Conditions(1)

Max.

Unit

Quiescent Power Supply
Current

VCC '" Max., VIN ~ VHC, VIN ~VLC

-

0.2

1.S

mA

t1lcc

Quiescent Power Supply
Current TIL Inputs HIGH

Vcc", Max., VIN '" 3.4V(3)

-

0.5

2.0

mA

ICCD

Dynamic Power Supply
Current(4)

Vcc", Max.
Outputs Open

-

0.24

0.4

Total Power Supply
Current(S)

Vcc", Max., Outputs Open,
fcp '" OSC '" SMHz (SO% duty cycle)
READY, SSNO, WAITREQ, HALT, INIT '" Vcc
Ll, L2, L3, SSNC, FIRST/LAST, RUN, Cx '" GND

-

6.S

9.7

Vcc", Max.

-

8.S

16.6

I

VIN~ VHC
VIN ~ VLC

Min.

Typ.(2)

Icc

Ic

Parameter

mAl
MHz
mA

Outputs Open
fcp", OSC '" SMHz (SO% duty cycle)
SSNO, HALT '" Vcc
READY, WAITREQ, INIT '" 3.4V (98% duty cycle)
Ll, L2, L3, SSNC, FIRST/LAST, RUN, Cx '" GND
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + tolcc DHNT + ICCD (fcP/2 + fONO)
Icc = Quiescent Current
tolcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fa = Output Frequency
No = Number of Outputs at fa
.
All currents are in milliamps and all frequencies are in megahertz.

6.32

2550 ttl 05

5

IDT49C25/A
CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT49C25
Com'l.
Symbol

Parameter

Condition

Min.

Max.

IDT49C25A
Com'l.

MIl.
Min.

Max.

Min.

Max.

Mil.
Min.

Max.

Unit

31

-

31

-

40

-

40

-

MHz

Fo Frequency
(Cx = HIGH) 6)

-

-

-

-

-

-

-

-

MHz

tOFFSET

Fo (./j to C1, C2, C3, C4
or WAITACK (./j

-

8.5

-

8.5

-

6.0

-

6.0

ns

4

tOFFSET

Fo (./j to C1, C2, C3, C4
or WAITACK ('}

-

17

-

18

-

11.5

-

12

ns

5

tSKEW

C1 (./j to C2 (./j

-

2

-

2

-

1.5

-

1.5

ns

6

tSKEW

C1 (./j to C3 (./j

-

2

2

-

1.5

-

1.5

ns

7

tSKEW

C1 (./j to C4 ('}
Opposite Transition

-

11

-

11

-

8.0

-

8.0

ns

8

tsu

L1, L2, L3, to C1 (./j

6

-

6

-

5

-

5

-

ns

9

tH

L1, L2, L3, to C1 (.i)

8

-

8

-

6

-

6

-

ns

10

tsu

Cx to Fo ( ./j(2)

18

18

0

0

0

0

-

ns

Cx to Fo ( ./j(2)

-

12

tH

-

12

11

-

12

tsu

WAITREQ to Fo (.i}(3)

18

-

18

-

12

-

12

-

ns

13

tH

WAITREQ to Fo (.i}(3)

0

-

0

-

0

14

tsu

READY to Fo (./j(3)

18

-

18

-

12

15

tH

READY to Fo (.i}(3)

0

-

0

0

16

tsu

RUN, HALT (.i) to
Fo (./j(3,4)

18

-

18

-

12

-

17

tsu

SSNC, SSNO to
Fo (.i}(3,4)

18

-

18

-

12

18

tsu

FIRST/LAST to
Fo (./j(5)

18

-

18

-

12

1

fMAX1

Fo Frequency
(Cx Connected)(1, 6)

2

fMAX2

3

CL
RL

= 50pF
= soon

ns

0

-

ns

12

-

ns

0

ns

12

-

-

12

-

ns

-

12

-

ns

ns

19

tsu

INIT (./j to Fo (./j(3)

18

-

18

-

12

-

12

-

ns

20

tw

INIT LOW Pulse Width

20

-

25

-

18

-

23

-

ns

21

tPLH

INITto WAITACK

25

-

27

18

ns

tPLH

OSC to Fo

13

-

16

8.5

-

10.5

ns

23

tPHL

-

13

-

16

-

16

22

-

8.5

-

10.5

ns

NOTES:
2550 tbl 06
1. The frequency guarantees apply with Cx connected to C" C2, C3, C4 or HIGH. The Cx input load must be considered part of the SOpf/SOOn clock output
loading.
2. These set-up and hold times apply to the Fo LOW-to-HIGH transition of the period in which Cx goes LOW.
3. These inputs are synchronized internally. Failure to meet ts may cause a liFo delay but will not cause incorrect operation.
4. These inputs are "debounced" by an internal R-S flip-flop and are intended to be connected to manual break-before-make switches.
5. FIRST/LAST normally wired HIGH or LOW.
6. This parameter is guaranteed but not tested.

6.32

6

I

I

IDT49C2S/A
CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING WAVEFORMS

fo

(INTERNAL)

Figure 2. Normal Cycle Without Wait States (Pattern Fs Shown)
2550 drw 04

PERIOD

WAIT TIMING (Cx Connected to C )

Figure 3. Wait Timing (CX Connected to Cl)

6.32

7

IDT49C2S/A
CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DETAILED DESCRIPTION
The IDT49C25/A are dynamically programmable generalpurpose clock controllers. They can be logically separated
into two parts - a state machine decoder and a state machine
control section.

The state machine takes microcode information from the
Microcycle Length (L) inputs L1, L2 and L3 and counts the
fundamental frequency of the oscillator (OSC) to create the
clock outputs Fa, C1, C2,C3 and C4.
The clock outputs have a characteristic wave shape
PATIERN

PATIERN

I---

WAVEFORMS
AND
TIMING

INPUT
CODE

L3, L2,L1

WAVEFORMS
AND
TIMING

INPUT
CODE

L3, L2,L1

C1~
F3
LLL

C2Jl.lJ
C3I1J.S
C4Dh
:

Fa

I

I

;

F7

LHH

riJlliJ

Lf

C1~
F4

Fa
LHL

LLH

1

Fa

C1J

::

Lf

' 2 ; 3 ; 4 : 5 ! 6

i

7

C3s-liJs
C41J ;
L
rUUutru

F9
HHL

! !

i

8

rL

hHhhhhhhl

IU U U U U U U U

Lf

C1~

: tC2.. Jr------t-1
. I Ll.......J

F5
HLH

~

C2J
C3 J
C4LJ

C2 Ji--.----WC3J
I I r
~ i !
~

C4

2

3

4

5! 6 ! 7

8 i 9

Fo

C1J
Lf
C2s-nJJ

Fs
HHH

r
::lrluuutn}
C3J

F10

.!'

HLL

2550 drw 06

Figure 4. IDT49C2S/A Clock Waveforms

6.32

8

IDT49C25/A
CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

relationship for each microcycle length. For example, C1 is
always LOW only on the last Fo clock period of a microcycle
and C4 is always LOW on the first. C3 has an approximate duty
cycle of 50% and C2 is HIGH for all but the last two periods (see
Figure 4).
The current state of the machine is contained in a register,
part of which is the Clock Generator Register. C 1, C2, C3 and
C4 are the outputs of this register. These outputs and the
outputs of the Microcycle Control Latch are fed into
combinatorial logic to generate the next state. On each falling
edge of the internal clock, the next state is entered into the
current state register. The Microcycle Control Latch is latched
when C1 is HIGH. This means that it will be loaded during the
last state of eachmicrocycle (C1 =C2=C3 = LOW, C4 = HIGH).
This internal latch selects one of eight possible microcycle
lengths, F3 to F10.
The state machine control logic, which determines the
mode of operation of the state machine, is intended to be
connected to a front panel. There are four basic modes of
operationofthe IDT49C25/Acomprisedof RUN, HALT, WAIT
and SINGLE STEP.

SYSTEM TIMING
In the typical computer, the time required to execute
different instructions varies. However, the time allotted to
each instruction is the time that it takes to execute the longest
instruction. The IDT49C25/A allows the user to dynamically
vary the time allotted for each instruction, thereby allowing the
user to realize a higher throughput.

IDT49C2S/A CONTROL INPUTS
The control inputs fall into two categories, microcycle
length control and clock control. Microcycle length control is
provided via the "L" inputs which are intended to be connected
to the microprogram memory. The "L" inputs are used to
select one of eight cycle lengths ranging from three oscillator
cycles for pattern F3 to ten oscillator cycles for pattern F10.
This information is always loaded at the end of the microcycle
into the Microcycle Control Latch which performs the function
of a pipeline register for the microcycle length microcode bits.

RUN

Vee

HALT

SSNC
SPOT

SSNO

IDT49C25/A

GND

PUSHBUnON

-=- SWITCH

2550 drw 07

Figure 5. Switch Connection for RUN/HALT and Single Step

Therefore, the cycle length goes in the same microword as the
instruction that it is associated with.
The clock control inputs are used to synchronize the
microprogram machine with the external world and I/O
devices. Inputs like RUN, HALT, SSNO and SSNC, which
start and stop execution, are meant to be connected to
switches on the front panel of the microprogrammed machine
(see Figure 5). These inputs have internal pull-up resistors
and are connected to an R-S flip-flop in orderto provide switch
debouncing. The FIRST/LAST input is used to determine at
what point of the microcycle the IDT49C25/A will halt when
HALT or a SINGLE STEP is initiated. In most applications, the
user wires this input HIGH or LOW, depending on the design.
When HALT is held low (RUN = HIGH), the state machine
will start the halt mode on the last (C1 = LOW) or the first (C4
= LOW) state of the microcycle as determined by the FIRST/
LAST input. When RUN goes low (HALT = HIGH), the state
machine will resume the run mode.
The WAITREO, Cx, READY and WAITACK signals are
used to synchronize other parts of a computer system (memory,
I/O devices) to the CPU by dynamically stretching the
microcycle. For example, the CPU may access a slow
peripheral that requires the data remain on the date bus for
several microseconds. In this case, the peripheral pulls the
WAITREO line LOW. The Cx input lets the design specify
when the WAITREO line is sampled in the microcycle. This
has a direct impact on how much time the peripheral has to

Fa

WAITREQ

Cx

WAITACK

READY
2550 drw 08

Figure 6. WAIT/READY Timing

6.32

9

1DT49C2S/A

CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

respond in order to request a wait cycle (see Figure 6). The
READY line is used by the peripheral to signal when it is ready
to resume execution of the rest of the microcycle. The
WAITACK line goes ~OW on the next oscillator cycle after the
Cx input goes LOW and remains LOW until the second
oscillator cycle after READY goes LOW.
The SSNO and SSNC inputs are used to initiate the
SINGLE STEP mode. These debounced inputs allow a single
microcycle to occur while in the halt mode. SSNO (normally
open) and SSNC (normally closed) are intended to be
connected to a momentary SPDT switch. After SSNO has
been high for one clock edge, the state machine will change
to the next run mode. The microcycle will end on the first or
last state of the microcycle, depending on the state of the
FIRST/LAST.

AC TIMING SIGNAL REFERENCES
Set-up and hold times in registers and latches are
measured relative to the clock signals that drive them. In the
IDT49C25/A, the external oscillator provides a free running
clock Signal that drives all the registers on the devices. This
clock is provided forthe user through the buffered output of Fo.
Therefore, Fa is used as the reference of set-up, hold and
clock-to-output times. However, for the Microcycle Control
Latch, the set-up and hold times are referenced to the C1
output which is the buffered version of the latch enable. This
reference is appropriate for the Microcycle Control Latch
because, in a typical application, this latch is considered part
of the pipeline register which is also driven by one of the uC"
outputs.

Fa

SSNC

SSNO

r----------------------...,

Cl

C2 and C3

I

C4
r-----------------------j

HALT

I

MODEl

RUN
MODE
(F3)

I

I

HALT
MODE

I

2550 drw 09

Figure 7. Single Step Timing Sequence

6.32

10

IDT49C25/A
CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT49C

xxx

x

x

Device Type

Package

Processl
Temperature

y~lank
P
D
'----------1

'--_ _ _ _ _ _ _ _ _ _ _--1

Commercial (O°C to +70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class 8

L
E

Plastic DIP
CERDIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier
CERPACK

25
25A

Microcycle Length Controller
Fast Microcycle Length Controller

J

2550 drw 10

6.32

11

(;)®

IDT39C8XX

HIGH-PERFORMANCE
CMOS BUS INTERFACE

Integrated Devfce Technology, Inc.

The part numbering scheme for the I DT39C8XX family had been changed in 1988 to conform with the new proposed J EDEC
part numbering system. The new system is as follows:

Previous Part Number

New Part Number

IDT39C821
IDT39C822
IDT39C823
IDT39C824
IDT39C825
IDT39C826

IDT54/74FCT821A
IDT54/74FCT822A
IDT54/74FCT823A
IDT54/74FCT824A
IDT54/74FCT825A
IDT54/74FCT826A

IDT39C827
IDT39C828

IDT54/74FCT827A
IDT54/74FCT828A

IDT39C841
IDT39C842
IDT39C843
IDT39C844
IDT39C845
IDT39C846

IDT54/74FCT841A
IDT54/74FCT842A
IDT54/74FCT843A
IDT54/74FCT844A
I DT54/74FCT845A
IDT54/74FCT846A

IDT39C861
IDT39C862
IDT39C863
IDT39C864

IDT54/74FCT861A
IDT54/74FCT862A
IDT54/74FCT863A
IDT54/74FCT864A

Refer to data sheets under the new part number system for all specifications.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
Iceo = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fO = Output Frequency
NO = Number of Outputs at fa
All currents are in milliamps and all frequencies are in megahertz.
.6.34

2581 tbl 04

3

IDT54174FCT138/A1C
FAST CMOS 1·0F·8 DECODER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT138
Com'l.
Symbol

Parameter

Mil.

IDT54/74FCT138A

IDT54/74FCT138C

Mil.

Com'l.

Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.

Com'l.
Min.(2)

Mil.

Max. Min.(2) Max.

Unit

1.5

9.0

1.5

12.0

1.5

5.8

1.5

7.8

-

-

-

-

ns

Propagation Delay
E1 or E2 to On

1.5

9.0

1.5

12.5

1.5

5.9

1.5

8.0

-

-

-

-

ns

Propagation Delay
E3 to On

1.5

9.0

1.5

12.5

1.5

5.9

1.5

8.0

-

-

-

-

ns

tPLH
tPHL

Propagation Delay
An to On

tPLH
tPHL
tPLH
tPHL

CL = 50pF
RL = 500n

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

2581 tbl07

II

6.34

4

IDT54174FCT138! AlC
FAST CMOS 1·0F·8 DECODER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vee

SWITCH POSITION
0--.7.OV

500n

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

2581
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

XX{

PULSE WIDTH

-= ~~V

l

~~;....;::a"-;Jo, -

OV

tsu--t'l4---~

LOWHIG~~~~

- 3V
_ ~JV

TIMING
INPUT _ _ _ _ _ _-'
ASYNCHRONOUS CONTROL
PRESET - - - -......
CLEAR
ETC. - - - - - '
SYNCHRONOUS CONTROL
CLOCK

:%~~1~ vvY
l
~tsu

-

3V

-

OV

-

3V

HIGH-LaW-HIGH
PULSE

- - t - - - - - - - 1.SV

~~;....;::a"-;Jo,

=t-

till 08

~ 15V
tw

--l.SV

-1.5V

ETC.

-

PROPAGATION DELAY

OV

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

3V
3V
SAME PHASE
INPUT TRANSITION

OV
OV
3.5V

OUTPUT

VOL
VOL
VOH
SWITCH
OPEN

3V
OPPOSITE PHASE
INPUT TRANSITION

OV
OV
NOTES
2581 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ son; tF ~ 2.Sns;
tR ~ 2.Sns.

6.34

5

IDT54174FCT138/A1C
FAST CMOS 1-0F-8 DECODER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XX

----Temperature
Range

FCT

X

X

X

Device
Type

Package

Process

~~Iank
~-------~--l

L . -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - j

P
D
SO
E
L

Plastic DIP
CERDIP
Small Outline IC
CERPACK
Leadless Chip Carrier

138
138A
138C

1-of-8 Decoder
Fast 1-of-8 Decoder
Super Fast 1-of-8 Decoder

54

-55°C to + 125°C
O°C to +70°C

~---------------------~74

6.34

Commercial
MIL-STD-883, Class B

2581 drw 03

6

t;)

DUAL 1-0F-4 DECODER

IDT54/74FCT139
IDT54/74FCT139A
I DT54/74FCT139C

Integrated Device Temnology, Inc.

FEATURES:

DESCRIPTION:

• IDT54/74FCT139 equivalent to FASFM speed
• IDT54/74FCT139A 35% faster than FASFM
• Equivalent to FASFM output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1 mW typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FASFM
(5JlA max.)
• Dual 1-of-4 decoder with enable
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT1391NC are duaI1-of-4 decoders built
using advanced CEMOSTM, a dual metal CMOS technology.
These devices have two independent decoders, each of
which accept two binary weighted inputs (Ao-Al) and provide
four mutually exclusive active LOW outputs (50-53). Each
decoder has an active LOW enable (E). When E is HIGH, all
outputs are forced HIGH.

PIN CONFIGURATIONS

FUNCTIONAL BLOCK DIAGRAM
Ea
AOa
Ala

Ea
AOa

2

Ala
DOa

3
4

Dla

5

D2a

6

P16-1
016-1
S016-2
&
E16-1

15

12
11

D3a

7

10

8

9

DIP/SOIC/CERPACK
TOP VIEW

~

"'OZ8.c
>IUJ

I

I I
L-' L-' I

I I

NC
01a

]7

02a

:J 8

OOa

03b
2605 cnv· 03

II
II
I
I L--I L-..I

2 U 20 19
1
18[: AOb

3

:J 4
:J 5
:J 6

A1a

2605 cnv· 01

LU

1990 Integrated Device Technology. Inc.

6.35

JUNE 1990
DSC4613/·

I DT54f7 4FCT139/ AlC
DUAL 1-0F-4 DECODER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE(1)

DEFINITION OF FUNCTIONAL TERMS

Inputs

Outputs

00

01

02

03

H

A1
X

H

L

L

L

H
H

H
H
H

H
H
H

H

L
L

H

L

L

L

L

H

H
H

L

H
H

Ao, Al

H
H
H

L

H

NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care

Address Inputs

E

Enable Input (Active LOW)

50-03

Outputs (Active LOW)
2605 tbl 04

L
2605 tbl 05

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND

Description

Pin Names

Ao
X

E

CAPACITANCE (TA= +25°C, f = 1.0MHz)

Commercial

Milltary_

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

TA

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power
Dissipation

0.5

0.5

W

lOUT

DC Output
Current

120

120

mA

Parameter(l)

Conditions

Typ.

Max.

Unit

CIN

Input
Capacitance

VIN = OV

6

10

pF

COUT

Output
Capacitance

VOUT= OV

8

12

pF

Sy_mbol

NOTE:
2605tbl02
1. This parameter is measured at characterization but not tested.

NOTES:
2605 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and I/O terminals only.

6.35

I

2

I DT54f7 4FCT139! AlC
DUAL 1-0F-4 DECODER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc= 5.0V
Symbol

Test Condltlons(1)

Parameter

± 10%

Min.

TypP)

Unit

Max.

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

-

0.8

V

IIH

Input HIGH Current

Vee

-

-

flA

-

-

S
5(4)

IlL

Input LOW Current

-

-

_S(4)

VIK

Clamp Diode Voltage

los

Short Circuit Current

VOH

Output HIGH Voltage

= Min., IN = -18mA
Vcc = Max.(3), Vo = GND
Vcc = 3V, VIN = VLC or VHC,

-

=

Min.

10H

. 10H

= VIH or VIL

=

= -32flA

-300flA

-0.7

VHC

Vcc

VHC

Vee

-

-120

10H

2.4

4.3

-

10H

2.4

4.3

-

-

GND

VLC

GND

VLC<4)

0.3

O.S

-

0.3

O.S

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

6.35

-S
-1.2

-

-60

= -12mA MIL.
= -15mA COM'L.
Vce = 3V, VIN = VLC or VHC, 10L = 300flA
Vcc = Min.
10L = 300flA
VIN = VIH or VIL
10L = 32mA MIL.
10L = 48mA COM'L.
VIN

Output LOW Voltage

= Vcc
VI = 2.7V
VI = O.SV
VI = GND
VI

Vcc

Vcc

VOL

= Max.

V

V
mA
V

V

26051b103

3

IDT54174FCT139fA/C
DUAL 1-0F-4 DECODER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol
lee
61cc
Iceo

VLC

= O.2V; VHC = VCC -

O.2V
TypY)

Max.

Unit

Quiescent Power Supply Current

Vee = Max.
VIN> VHC' VIN < VLC

Test Conditions(1)

-

0.2

1.S

mA

Quiescent Power Supply Current
TTL Inputs HIGH

VCC = Max.
VIN = 3.4V(3)

-

O.S

2.0

mA

Dynamic Power Supply
Current(4)

VCC = Max.

VIN ~ VHC

-

0.1S

0.3

Outputs Open

VIN ~ VLC

Parameter

Min.

mAl
MHz

One Bit Toggling
SO% Duty Cycle
Ic

Total Power Supply Current(6)

VIN ~ VHC

Vcc = Max.
Outputs Open

f

1.7

4.S

-

2.0

S.S

-

3.2

7.S(5)

-

3.7

9.S(5)

mA

(FCT)

i = 10MHz

SO% Duty Cycle

VIN = 3.4V

One Bit Toggling

VIN = GND

Vcc = Max.

VIN ~ VHC

Outputs Open

VIN ~ VLC
(FCT)

f

-

VIN ~ VLC

i = 10MHz

SO% Duty Cycle

VIN = 3.4V

One Bit Toggling
on Each Decoder

VIN = GND

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (V IN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + t.lcc DHNT + ICCD (fcpf2 + fiNo)
Icc = Quiescent Current
t.lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
No = Number of Outputs at fi
All currents are in milliamps and all frequencies are in megahertz.

2605 tbl 04

II
I

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT139
Com'l.
Parameter
tPLH
tPHL

Description
Propagation Delay
Aoor A1 to On

Condition(1)

= SOpF
RL = 500n
CL

Mil.

IDT54174FCT139A

IDT54174FCT139C

Com'l.

Com'l.

Mil.

Mil.

Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.
1.S

9.0

tPLH
Propagation Delay
1.5 8.0
'EtoOn
tPHL
NOTES:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

6.35

Unit

1.S

12.0

1.S

S.9

1.S

7.8

-

-

-

-

ns

1.5

9.0

1.5

5.5

1.5

7.2

-

-

-

-

ns
2605 tbl 07

4

IDT54f74FCT139/A/C
DUAL 1·0F·4 DECODER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

2605 tbl DB
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zxt

PULSE WIDTH

--= ~~V

j
""'-~...x~ tsu ---4'14--~

TIMING
INPUT

OV

_

6;JV

-

3V
1.5V
OV

lOW-HIG~J~s~

3V

ASYNCHRONOUS CONTROL
PRESET ................,
CLEAR
ETC . ...._ ........J

........--------

,----+-----~

---+------

=t-

HIGH-lOW-HIGH

~ 1.5V
tw

--1.5V

PULSE

SYNCHRONOUS CONTROL
CLOCK

:~~~~~ vvJr
~tsu
J

ETC.

""'-~...x~

- 3V
-1.5V
- OV

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE
3V

SAME PHASE
INPUT TRANSITION

OUTPUT

OV
OV
3.5V

VOH
-1.5V

VOL

VOL
OUTPUT
NORMALLY
HIGH

3V
OPPOSITE PHASE
INPUT TRANSITION

VOH
SWITCH
OPEN
OV

NOTES
2605 drw 10
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ son; tF ~ 2.Sns;
tR ~ 2.Sns.

6.35

5

IDT54174FCT139/A1C
DUAL 1·0F·4 DECODER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xx

T==-e-m-p-.-=R::-a-n-ge-

FCT

XXX X
-=D-e-:vi"""ce--=Ty-p-e-

x

x

Package

Process

y~lank
P

D
~------------~SO

L
E
139
~----------------------~139A

139C

54

~----------------------------------~74

6.35

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Dual 1-of-4 Decoder
Fast Dual 1-of-4 Decoder
Super Fast Dual 1-of-4 Decoder
-55°C to + 125°C
O°C to +70°C

2605 cnv' 09

6

t;)®

IDT54/74FCT161
IDT54/74FCT161A
IDT54/74FCT163
I DT54/74FCT163A

FAST CMOS
SYNCHRONOUS
PRESETIABLE
BINARY COUNTERS

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• IDT54/74FCT161/163 equivalent to FASpM speed
• IDT54/74FCT161A/163A 35% faster than FAS"pM
• Equivalent to FASpM output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial), 32mA (military)
• CMOS power levels (1 mW typo static)
• TIL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAS"pM
(5J..LA max.)
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class 8

The IDT54/74FCT161/163 and IDT54/74FCT161A!163A
are high-speed synchronous modul0-16 binary counters built
using advanced CEMOSTM , a dual metal CMOS technology.
They are synchronously presettable for application in
programmable dividers and have two types of count enable
inputs plus a terminal count output for versatility in forming
synchronous multistage counters. The I DT54/74FCT161 and
IDT54/74FCT161A have asynchronous Master Reset inputs
that override all other inputs and force the outputs LOW. The
I DT54/74FCT163 and IDT54/74 FCT163A have Synchronous
Reset inputs that override counting and parallel loading and
allow the outputs to be simultaneously reset on the rising edge
of the clock.

FUNCTIONAL BLOCK DIAGRAM
Po

PE-.----~~~--------------~~----------~~------~+_------------~
CEP~====~==~~--____-+__-+~________~~______~-H______- .

CET--~---+~------------~--~-+--------+--H-------4-+~------~----~-,

: 163

:ONLY

,,~
,
,,
,

I

DETAIL
A

DETAIL
A

DETAIL
A

01

02

03

I

L _____

____ Q§I6Ih~J

00

2612 drw 01

CEMOS is a tr.ademark of Integrated Device Techology. Inc.
FAST is a registered trademark of National SemiconduC1or Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1990 Integrated Device Technology. Inc.

6.36

JUNE 1990
DSC4607/·

1

IDT54174FCT161/A, IDT54174FCT163/A
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

OR

8u
u. uZ>I-

INDEX

Vee
TC

CP
Po

1l.1a:

."

L-JL-JIIL-JL-J
3 2 I I 20 19

Qo

P1

01
02

P2

P3

]

P1

] 5

NC

03
CET
PE

CEP
GND

Po

]

P2
P3

~

4

L20-2

6

] 7
] 8

'"
DIP/SOIC/CERPACK
TOP VIEW

18 [

00

17 [

01

16 [

NC

15 [

02
03

14 [

~;Q~~Q
Il. 0 ()

IW

I-

~azll.~

2612 drw 02

"MRfor'161

LCC
TOP VIEW

"SR for '163

FUNCTION TAB LE(2)

PIN DESCRIPTION
Pin Names

Description

Action on the Rising
Clock Edge(s)

SRt1)

PE

Count Enable Trickle Input

L

X

X

X

Reset (Clear)

Clock Pulse Input (Active Rising Edge)

H

L

X

X

Load

MR('161)

Asynchronous Master Reset Input (Active LOW)

H

H

H

H

Count (Increment)

SR ('163)

Synchronous Reset Input (Active LOW)

H

H

L

X

No Change (Hold)

H

H

X

L

No Change (Hold)

CEP

Count Enable Parallel Input

CET
CP

PO-3

Parallel Data Inputs

PE

Parallel Enable Input (Active LOW)

00-3

Flip-Flop Outputs

TC

Terminal Count Output

CET

NOTES:
1. For FCT163/163A only.
2. H = HIGH Voltage Level, L

CEP

(Pn~On)

26121b106

= LOW Voltage Level, X = Don't Care.

26121b105

6.36

II

2

IDT54174FCT161! A, I DT5417 4FCT163!A
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
to GND
VTERM(3) Terminal Voltage
with Respect
toGND,

CAPACITANCE (TA =

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

o to +70

-55 to +125

°C

TA

Operating
Temperature

TSIAS

"":55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

PT

Temperature
Under Bias
Storage
Temperature
Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

rnA

TSTG

+25°C, f

Parameter(1)

Symbol

= 1.0MHz)

Conditions Typ.

CIN

Input Capacitance

VIN = OV

COUT

Output Capacitance VOUT =

OV

Max.

Unit

6

10

pF

8

12

pF

NOTE:
2612 tbl 02
1. This parameter is measured at characterization but not tested.

NOTES:
2612tbl01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
, conditions above those indicated in the operational sections of this
specification is. not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vec by +O.5V unless otherwise noted.
2. Inputs and Vee terminals only.
3. Outputs and 110 terminals only.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V, VHC = Vee - 0.2V
Commercial: TA = O°C to +70°C, Vee = 5.0V ± 5%; Military: TA = -55°C to + 125°C, Vee = 5.0V

± 10%
Typ.(2)

Max.

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

Vil

Input LOW Level

Guaranteed Logie LOW Level

V

Input HIGH Current

Vee = Max.

VI = Vee

-

0.8

IIH

-

IlA

VI = 2.7V

-

III

Input LOW Current

VI = 0.5V

-

_5(4)

VI= GND

-

-

5
5(4)

-

-0.7

-1.2

-60

-120

Symbol

Test Conditlons(1)

Parameter

VIK

Clamp Diode Voltage

Vee = Min., IN = -18mA

los

Short Circuit Current

Vee = Max.(3), Vo

VOH

Output HIGH Voltage

Vee = 3V, VIN = Vle or VHe, 10H = -321lA

=GND

Vee = Min.
VIN = VIH or Vil
Val

Output LOW Voltage

= Vle or VHe,
= Min.
VIN = VIH or Vil
Vee = 3V, VIN

Vee

Min.

VHe

Vee

10H = -3OOIlA

VHe

Vee

-

10H = -12mA MIL.

2.4

4.3

-

10H = -15mA COM'L.

2.4

4.3

-

-

GND

10l = 300llA

GND

Vle
Vle(4)

10l = 32mA MIL.

-

0.3

0.5

10l = 48mA COM'L.

-

0.3

0.5

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

6.36

V

-5

-

IOl = 300llA

Unit

V
rnA
V

V

2612tbl03

3

IDT54174FCT161/A, IDT54174FCT163/A
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS

POWER SUPPLY CHARACTERISTICS
Symbol

MILITARY AND COMMERCIAL TEMPERATURE RANGES

VLC = O.2V, VHC = VCC - O.2V

Typ.(2)

Max.

Unit

-

0.2

1.5

mA

-

0.5

2.0

mA

VIN;::: VHC
VIN::; VLC
(FCT)

-

0.15

0.25

mAl
MHz

Vec = Max., Outputs Open
Load Mode
fcp = 10MHz
50% Duty Cycle
CEP = CET = PE = GND
MR or SR = Vcc
One Bit Toggling
at fi = 5MHz
50% Duty Cycle

VIN;::: VHC
VIN::; VLC
(FCT)

-

1.7

4.0

mA

-

2.2

6.0

Vcc = Max., Outputs Open
Load Mode
fcp = 10MHz
50% Duty Cycle
CEP = CET = PE = GND
MR or SR = Vcc
Four Bits Toggling
at fi = 5MHz
50% Duty Cycle

VIN;::: VHe
VIN::; VLC
(FCT)

-

4.0

7.8(5)

-

5.2

12.8(5)

Test Conditions(l)

Parameter

lee

Quiescent Power
Supply Current

Vee = Max.
VIN ;::: VHC; VIN ::; VLC

~Icc

Quiescent Power Supply Current
TIL Inputs HIGH

Vec

leeD

Dynamic Power Supply Current(4)

Vec = Max., Outputs Open
Load Mode
CEP = CET = PE = GND
MR or SR = Vec
One Input Toggling
50% Duty Cycle

Ic

Total Power Supply Current(6)

= Max.,

VIN

Min.

= 3.4V(3)

VIN
VIN

VIN
VIN

= 3.4V
= GND

= 3.4V
= GND

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vec or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IOUIESCENT +IINPUTS + IDYNAMIC
Ic = Icc + ~lccDHNT + ICCD(fcp/2 + fiNi)
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (V IN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.36

2612 tbl 04

I
I

4

IDT54174FCT161/A,IDT54174FCT163/A
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT161A1163A

IDT54/74FCT161/163
Com'l.
Symbol

Parameter

Conditlon(1)

Min.'2) Max.

Com'l.

Mil.
Min.'2) Max.

Min.'2)

Mil.

Max. Min.(2) Max.

Unit

2.0

11.0

2.0

11.5

2.0

7.2

2.0

7.5

ns

Propagation Delay
CP to On (PE Input LOW)

2.0

9.5

2.0

10.0

2.0

6.2

2.0

6.5

ns

tPLH
tPHL

Propagation Delay
CPto TC

2.0

15.0

2.0

16.5

2.0

9.8

2.0

10.8

ns

tPLH
tPHL

Propagation Delay
CETtoTC

1.5

8.5

1.5

9.0

1.5

5.5

1.5

5.9

ns

tPHL

Propagation Delay
MRtoOn (,161)

2.0

13.0

2.0

14.0

2.0

8.5

2.0

9.1

ns

IPHL

Propagation Delay
MRtoTC (,161)

2.0

11.5

2.0

12.5

2.0

7.5

2.0

8.2

ns

tsu

Set-up Time, HiGH or LOW
Pn to CP

5.0

-

5.5

-

4.0

-

4.5

-

ns

tH

Hold Time, HIGH or LOW
Pn to CP

1.5

-

2.0

-

1.5

-

2.0

-

ns

tsu

Set-up Time, HIGH or LOW
PEar SR to CP

11.5

-

13.5

-

9.5

-

11.5

-

ns

tH

Hold Time, HIGH or LOW
PEar SR to CP

1.5

-

1.5

-

1.5

-

1.5

-

ns

tsu

Set-up Time, HiGH or LOW
CEP or CET 10 CP

11.5

-

13.0

-

9.5

-

11.0

-

ns

tH

Hold Time, HIGH or LOW
CEP or CET to CP

0

-

0

-

0

-

0

-

ns

IW

Clock Pulse Width (Load)
HIGH or LOW

5.0

-

5.0

-

4.0(3)

-

4.0(3)

-

ns

tw

Clock Pulse Width (Count)
HIGH or LOW

7.0

-

8.0

-

6.0

-

7.0

-

ns

tw

MR Pulse Width, LOW (,161)

5.0

-

5.0

-

4.0(3)

-

4.0(3)

-

ns

tREM

Recovery Time MR to CP (,161)

6.0

-

6.0

-

5.0

-

5.0

-

ns

tPLH
tPHL

Propagation Delay
CP to On (PE Input HiGH)

tPLH
tPHL

CL = 50pF
RL = soon

NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.

2612tbl07

6.36

5

IDT54174FCT161/A,IDT54174FCT163/A
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION

Vee

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

2612tbl08
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal 10 ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zxt

PULSE WIDTH

-= ~~V

j

.-.,...-.....M~ -

OV

Isu~0j4--~

LOW-HIG~ULfs~

- 3V
- - - - - - 1 r - - - - - - - 1.5V

TIMING
INPUT

-

OV

ASYNCHRONOUS CONTROL

=t-

HIGH-LOW-HIGH

PRESET - - - - - - - - , ~--~--~--------­ - 3V
- - t - - - - - - - 1.5V
CLEAR
ETC.
- OV

~ 1.5V
IW

__

1.5V

PULSE

SYNCHRONOUS CONTROL
CLOCK

:~~~~~ vvJr
1
~ISU

.-.,...-..--~

ETC.

3V

-1.5V
- OV

I

PROPAGATION DELAY

ENABLE

SAME PHASE
INPUT TRANSITION

DISABLE

)--'+----OV
3.5V

_----~,+-

OUTPUT

I

ENABLE AND DISABLE TIMES

VOH
-1.5V

VOL

VOL
VOH
SWITCH
OPEN

3V
OPPOSITE PHASE
INPUT TRANSITION

OV

' - - - - - - ' - - - - OV

NOTES
2612drw04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate S 1.0 MHz; Zo s son; tF S 2.Sns;
tR S 2.Sns.

6.36

6

IDT54174FCT161/A, IDT54174FCT163/A
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

X
FCT XXXX
---Temperature
Device
Range
, Type

X

X

Package

Process

Commercial
MIL-STD-883, Class B

P

~------------~

o

L

SO

E
161
163
~-------------1

161A
163A

' - - - - - - - - - - - - - - - - - - 1 ] 54

174

Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC
CERPACK
Synchronous Binary Counter with
Asynchronous Master Reset
Synchronous Binary Counter with
Synchronous Reset
Fast Synchronous Binary Counter with
Asynchronous Master Reset
Fast Synchronous Binary Counter with
Synchronous Reset
-55°C to + 125°C
0° to +70°C
2612 drw 03

6.36

7

G®

IDT54/74FCT182
IDT54/74FCT182A

FAST CMOS
CARRY LOOKAHEAD
GENERATOR

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• IDT54/74FCT182 equivalent to FASpM speed;
• IDT54/74FCT182A 30% faster than FAST ™
• Equivalent to FASpM speeds and output drive over full
temperature and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1 mW typo static)
• TIL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FASpM
(51lA max.)
• Carry lookahead generator
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT182 and IDT54/74FCT182A are highspeed carry lookahead generators built using advanced
CEMOSTM, a dual metal CMOS technology. The IDT541
74FCT182 and I DT54/74FCT182A are carry lookahead
generators that accept up to four pairs of active LOW Carry
Propagate (Po, P1, P2, P3) and Carry Generate (Go, G1, G2, (3)
signals and an active HIGH carry input (Cn) and provides
anticipated HIGH carries (Cn+x, Cn+y, Cn+z) across four groups
of binary adders. These products also have active LOW Carry
Propagate (P) and Carry Generate (G) outputs which may be
used for further levels of lookahead.

FUNCTIONAL BLOCK DIAGRAM
Cn

Go Po

G1 P1

Cn+y

Cn+x

G3 P3

G2 P2

P

Cn+z

2560 drw02

PIN CONFIGURATIONS
INDEX

G1
P1
Go
Po
G3
P3

1
2
3
4

P16-1,
016-1,
S016-1
&

E16-1

P
GND

16
15
14
13
12
11
10
9

Vee

32: :2019

P2
<32

Go J 4
Po ] 5
NC J 6
G3 ] 7
P3 JB

Cn
Cn+x
Cn+ y

G

9

~

1B [

<32

L20

17 [

Cn

16 [ NC
15 [ Cn +X
14[ Cn + y
1011 12 13

r"'"1"-'''-'''''''''' ...,

Cn+z

,0....

0 0

~

,,,

ZZ c:

"

DlP/SOIC/CERPACK
TOP VIEW

2560 drw at

()

LCe
TOP VIEW

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©t99a Integrated Device Technology, Inc.

6.37

JUNE 1990
DSC-4623/·

IOT54174FCT1821 A
FAST CMOS CARRY lOOKAHEAD GENERATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION
Pin Names

Description

Cn

Carry Input

GO-G3

Carry Generate Inputs (Active LOW)

PO-P3

Carry Propagate Inputs (Active LOW)

Cn+x - Cn+z

Carry Outputs

G

Carry Generate Output (Active LOW)

P

Carry Propagate Output (Active LOW)
2560tbl05

FUNCTION TABLE(1)
Inputs
Cn

Go

Po

X
X
H

H
H
L
X

H
X
X
L

X
X
L
X
X
H

X
H
H
X
L
X

X
H
X
X
X
L

H
H
H
L
X
X

H
X
X
X
L
L

X
X
X
L
X
X
X
H

X
X
H
H
X
X
L
X

X
X
H
X
X
X
X

X

X
H
X
X
X
X
L

L

L

X
X
X

G1

H

H
H
H

X
L
X
X

L

X

L

H
X
X
X
L

Outputs
G2

G3

P2

P3

Cn+x

Cn+y

Cn+z

G

P

L
L
H
H

X
X
H
H
X
X

X
X
X

P1

L
L
L
H
H
H

L

H
H
H
H
L
X
X
X

H
X
X
X
X
L
L
L

X
X
H
X
X
X
X
L

X
H
H
H
X
L
X
X

X
H
X
X
X
X
L
L

X
H
X
X
L

L
L
L
L
H
H
H
H
H
H
H
H
L
X
X
X

H
X
X
X
X
L
L
L

X
X
H
X

X
X
X
H

L

L

NOTE:
1. H = HIGH Voltage level
l = lOW Voltage level
X = Don't Care

H
H
H
H
L
L
L
L

H
H
H
H
L
2560 tbl 06

6.37

2

IDT54n4FCT1821A
FAST CMOS CARRY LOOKAHEAD GENERATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

CAPACITANCE

Commercial

Military

VTERM(2) Terminal Voltage
with Respect
toGND

-0.5 to +7.0

-0.5 to +7.0

V

VTERM(3) Terminal Voltage
with Respect
toGND

-0.5 to Vee

-0.5 to Vee

V

Unit

(TA = +25°C, f = 1.0MHz)

Parameter(1)

Symbol

Max.

Unit

CIN

Input
Capacitance

Conditions
VIN = OV

6

10

pF

COUT

Output
Capacitance

VOUT = OV

8

12

pF

Typ.

NOTE:
2560 tbl 02
1. This parameter is guaranteed by characterization data and not tested.

TA

Operating
Temperature

o to +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT
DC Output Current
120
120
mA
NOTES:
2560 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
Vcc by +O.5V unless otherwise noted.
2. Input and Vcc terminals only.
3. Outputs and I/O terminals only.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = O.2V; VHC = Vcc - O.2V
Commercial: TA = O°C to +70°C Vcc = 5 OV +
- 5%' Military' TA = -55°C to +125°C Vcc = 5 OV +
- 10%
Min.

Typ.(2)

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

-

0.8

V

IiH

Input HIGH Current

Vee

-

-

5
5(4)

~A

-0.7

-60

-120

Symbol

IlL

Input LOW Current

VIK

Clamp Diode Voltage

los

Short Circuit Current

VOH

Output HIGH Voltage

VOL

Test Conditions(l)

Parameter

Output LOW Voltage

= Max.

= Vee
VI = 2.7V
VI = 0.5V
VI = GND
VI

= Min., IN = -18mA
Vee = Max,l3), Vo = GND
Vee = 3V, VIN = VLe or VHe, 10H = -32~A
Vee = Min.
10H = -300~A
VIN = VIH or VIL
10H = -12mA MIL.
10H = -15mA COM'L.
Vee = 3V, VIN = VLe or VHe, 10L = 300~A
Vee = Min.
IOL = 300~A
VIN = VIH or VIL
10L = 32mA MIL.
10L = 48mA COM'L.
Vee

Max.

-

V

_5(4)

-

-5
-1.2

VHC

Vee

-

VHC

Vee

-

2.4

4.3

-

2.4

4.3

-

-

GND

VLe

-

GND

VLcl 4)

-

0.3

0.5

-

0.3

0.5

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

6.37

Unit

V
mA
V

V

2560 tbl 03

3

II

IDT54f74FCT1821A
FAST CMOS CARRY LOOKAHEAD GENERATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC

= O.2V; VHC = VCC - O.2V
Typ.(2)

Max.

Unit

Icc

Quiescent Power Supply
Current

VCC = Max.
VIN ~ VHC; VIN:5 VLC

-

0.2-

1.5

mA

.1 Icc

Quiescent Power Supply
Current TTL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

-

0.5

2.0

mA

ICCD

Dynamic Power Supply
Current(4)

VIN ~ VHC
VIN:5 VLC

-

0.15

0.3

mAl
MHz

Ic

Total Power Supply
Current(S)

Vcc = Max., Outputs Open
One Input Toggling
50% Duty Cycle
Vcc = Max., Outputs Open
fi = 1OMHz, 50% Duty Cycle
One Bit Toggling

VIN ~ VHC
VIN:5 VLC
(FCT)

-

1.7

4.5

mA

VIN = 3.4V
VIN = GND

-

2.0

5.5

Symbol

Test Conditions(1)

Parameter

Min.

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vee or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + IceD (fePf2 + fi Ni)
Icc = Quiescent Current
~Iee = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.37

256011>104

4

IDT54174FCT1821A
FAST CMOS CARRY lOOKAHEAD GENERATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT182A

IDT54/74FCT182
Mil.

Com'l.
Symbol

Parameter

Conditions(1)

Com'l.

Mil.

MinP>

Max.

Min.(2)

Max.

MinP>

Max.

MinP>

Max.

Unit

2.0

10.0

2.0

16.S

2.0

7.0

2.0

10.7

ns

tPLH
tPHL

Propagation Delay
Cn to Cn + x,
Cn + y, Cn + z

tPLH
tPHL

Propagation Delay
Po, P1, P2to
Cn + x, Cn + y, Cn + z

1.S

9.0

1.S

11.S

1.S

8.5

1.5

9.0

ns

tPLH
tPHL

Propagation Delay
Go, G1, G2to
Cn + x, Cn + y, Cn + z

1.S

9.5

1.S

11.S

1.5

8.5

1.5

9.0

ns

tPLH
tPHL

Propagation Delay
P1, P2, P3 to G

2.0

11.0

2.0

16.5

2.0

7.2

2.0

10.7

ns

tPLH
tPHL

Propagation Delay
GntoG

2.0

11.S

2.0

16.S

2.0

7.6

2.0

10.7

ns

tPLH
tPHL

Propagation Delay
Pnto P

1.S

8.5

1.S

12.S

1.5

6.0

1.5

7.4

ns

CL = SOpF
RL = soon

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

2560 tbl 07

II
I

6.37

5

IDT54174FCT1821A
FAST CMOS CARRY LOOKAHEAD GENERATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vee

SWITCH POSITION
a-.7.0V

50011

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

2560 tbl OB
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to lOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

J

PULSE WIDTH

""'-___...K~

-= ~~V
-

OV

-

3V

tsu----t'l4--..;

TIMING
INPUT

---1f------

LOWHIG~~~~

1.SV

-

OV

-

3V

-

OV

-

3V

ASYNCHRONOUS CONTROL
PRESET - - - -.....
CLEAR

HIGH-LaW-HIGH
PULSE

- - t - - - - - - - 1.5V

ETC. - - - - - '

=t-

~ 15V
--1.SV

1w

SYNCHRONOUS CONTROL
CLOCK

:~~~1~ vv:V
1
~tsu

""'-___

...K~

-1.5V
OV

ETC.

ENABLE AND DISABLE TIMES

PROPAGATION DELAY

ENABLE

DISABLE

, . . . - - _ - - - - 3V
SAME PHASE
INPUT TRANSITION

OV
3.SV

_--~,+-VOH

OUTPUT

-1.5V

VOL

VOL
VOH
SWITCH
OPEN

3V
OPPOSITE PHASE
INPUT TRANSITION

OV

'---------OV

NOTES
2560 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate:5 1.0 MHz; lO:5 50n; tF:5 2.5ns;
tR:5 2.5ns.

6.37

6

IDT54174FCT1821A
FAST CMOS CARRY LOOKAHEAD GENERATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xx
Temperature
.Range

FCT

X

x

x

Device
Type

Package

Process/
Temperature
Range

I'--------il ~Iank
'-----------1

'--------------------1

Commercial
MIL-STD-883, Class B

P
D
SO
L
E

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

182
182A

Carry Lookahead Generator
Fast Carry Lookahead Generator

' - - - - - - - - - - - - - - - - - - - - - - - i 54
75

-55°C to +125°C
O°C to +70°C

2560 dew 03

I

6.37

7

(;)®

IDT54/74FCT191
IDT54/74FCT191 A

FAST CMOS
UP/DOWN BINARY
COUNTER

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• IDT54/74FCT191 equivalent to FASFM speed
• IDT54/74FCT191A 35% faster than FASFM
• Equivalent to FASFM output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial), 32mA (military)
• CMOS power levels (1 mW typo static)
• TIL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST
(5~A max.)
• JEDEC standard pinout for DIP, LCC and SOIC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT191 and IDT54/74FCT191 A are
reversible modul0-16 binary counters, featuring synchronous
counting and asynchronous presetting and are built using
advanced CEMOSTM , a dual metal CMOS technology. The
preset feature allows the IDT54/74FCT191 and IDT541
74FCT191A to be used in programmable dividers. The count
enable input, terminal count output and ripple clock output
make possible a variety of methods of implementing
multiusage counters. In the counting modes, state changes
are initiated by the rising edge of the clock.

FUNCTIONAL BLOCK DIAGRAM
CP

DID

Po

0 9
~

I

P2

CE

I

I
I

II

I

~

II

I

T
I
I
11
I
J CLOCK K

(~

L....c PRESET

o

1

RC

TC

I

~

(Y

(]

P3

1

I

I
11
I
J CLOCK K

L....c PRESET

CL~R 0-

a

~

Y'
00

a

~

~
Ie

I

1

I

I
I

I
11
J CLOCK K

a

~

a

1

Y'

Y'

1 I

I

J
(t'

A

I

J CLOCK K
L....c PRESET

L....c PRESET

CL~R J-

1

I~

CL~R J-

a

~

CLEAR

a

1

p-

Q
~

Y'
2616 drw 01

CEMOS is a trademark of Integrated Device Techology. Inc.
FAST is a registered trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES ,
~~1990

Integrated Device Technology, Inc.

6.38

JUNE 1990
DSC46141.

IDT54174FCT191/A
FAST CMOS UP/DOWN BINARY COUNTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
~~og~

INDEX
P1
01

Qo

2
3

CE

UID

02
03
GND

016-1,
P16-1,
E16-1,

&
6
7

8016-1

8

16
15
14
13
12
11
10
9

Oo..z>

Vee

L......J

]
]
]
]
]

00
CE
NC

CP
RC
TC
PL
P2
P3

UID
02

I I

L......J

L......J

20 19
18
4
1
5
17
L20-2
16
6
15
7
8
14
9 1011 12 13
I I
LJ

[
[
[
[
[

CP
RC
NC
TC
PL

rlrlrL~"

aOOC'lN

ZZo..o..

DIP/SOIC/CERPACK
TOP VIEW

2616 drw 02

(!J

LCC
TOP VIEW

RC FUNCTION TABLE(2)

PIN DESCRIPTION
Pin Names

L......J

3 2

Po

Description

Outputs

Inputs
CE

CP

TC(l)

RC

Clock Pulse Input (Active Rising Edge)

L

--u-

H

--u-

PO-3

Parallel Data Inputs

H

X

X

H

PL

Asynchronous Parallel Load Input (Active LOW)

X

X

L

H

U/D

Up/Down Count Control Input

00-3

Flip-Flop Outputs

CE

Count Enable Input (Active LOW)

CP

RC

Ripple Clock Output (Active LOW)

TC

Terminal Count Output (Active HIGH)

26161b106

MODE SELECT FUNCTION TABLE(2)
Inputs
26161b105

Mode

PL

CE

UfD

CP

H

L

L

Count Up

H

L

H

./
./

L

X

X

X

Preset (Asynchronous)

H

H

X

X

No Change (Hold)

Count Down

NOTES:
26161b107
1. TC is generated internally.
2. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don't Care,
/: LOW- to-HIGH clock transition.

6.38

2

IDT54174FCT191/A
FAST CMOS UP/DOWN BINARY COUNTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage

CAPACITANCE

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vcc

-0.5 to Vcc

V

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to + 135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

Conditions Typ.

CIN

Input Capacitance

VIN = OV

COUT

Output Capacitance VOUT = oV

Max.

Unit

6

10

pF

8

12

pF

NOTE:
2616tbl02
1. This parameter is guaranteed at characterization but not tested.

with Respect
toGND
TA

(TA = +2S o C, f = 1.0MHz)

Parameter(1)

Symbol

NOTES:
2616tbl01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device a't these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Inputs and Vce terminals.
3. Outputs and I/O terminals.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLe = 0.2V; VHe = Vee - 0.2V
Commercial: TA = O°C to +70°C, Vee = S.OV ± 5%; Military: TA = -55°C to +12S o C, Vee
Symbol

Typ.(2)

Guaranteed Logic HIGH Level

2.0

-

-

V

Input LOW Level

Guaranteed Logic LOW Level

-

0.8

V

Input HIGH Current

Vcc

-

-

~A

-

-

5
5(4)

VI = O.SV

-

-

= GND

-

-

VIH

Input HIGH Level

VIL
hH

IlL

= Max.

= Vcc
VI = 2.7V
VI

Input LOW Current

VI
VIK

Clamp Diode Voltage

los

Short Circuit Current

VOH

Output HIGH Voltage

VOL

= S.OV ± 10%
Min.

Test Conditlons(1)

Parameter

Output LOW Voltage

= Min., IN = -18mA
Vcc = Max.P), Vo = GND
Vcc = 3V, VIN = VLC or VHC,
Vcc = Min.
VIN = VIH or VIL
Vcc

Vcc
Vcc
VIN

= 3V, VIN = VLC or VHC,
= Min.
= VIH or VIL

= -32JlA
= -300JlA
10H = -12mA MIL.
10H = -15mA COM'L.
10L = 300~A
10L = 300JlA
10L = 32mA MIL.
10L = 48mA COM'L.

10H

10H

Max.

_5(4)
-5

-

-0.7

-60

-120

VHC

Vcc

-

VHC

Vcc

-

2.4

4.3

-

2.4

4.3

-

-1.2

-

GND

VLC

-

GND

VLC(4)

0.3

0.5

-

0.3

0.5

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°e ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

6.38

Unit

V
mA
V

V

2616 till 03

3

IDT54f74FCT191/A
FAST CMOS UP/DOWN BINARY COUNTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

VLC = O.2V, VHC = VCC - O.2V
Typ.(2)

Max.

Unit

Icc

Quiescent Power
Supply CUrrent

Vcc = Max.
VIN ~ VHC; VIN ~ VLC

-

0.2

1.5

mA



TCD
r-f(BOR ROW)

r--

:9

:9

0

I

(

?
1

~

K

J

CP

Co

a

y

MR

TCu

So ::>-

a

L-

1
00

:=n

~

f

I
I

T

K

CP

I
I
J

I
I

~

CD

a
Y

~

So ::>-

a

Y

K

CP

CD
So

a
Y

L-

1

?

I
I
J

T

02

a

p.

L--

I

I
I

~

I

Y
I

I

K

J

CP

CD

a
Y

~

So ::>-

a

L--

2621 drw 01

CEMOS is a trademark of tntegrated Device Technology. Inc.
FAST is a trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
1:1090 Integrated Device Technology, Inc.

6.39

JUNE 1990
DSC-461S·

1

IDT54f74FCT193/A
FAST CMOS UP/DOWN BINARY COUNTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
INDEX

P1

Vee

01

Po

00
CPO
CPU

,...

3

MR
TCo
TCu
PL
P2
P3

02
03
GND

L....JL-IIIL-IL...J

"

2 I I 20 19
~
18 [

00
CPO
NC

] 4
] 5
] 6

CPU

] 7

15 [

]

14 [

02

17 [
16 [

L20-2

8

MR
TCo
NC
TCu
PL

~~~~~

2621 drw 02

DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW

FUNCTION TABLE(1)

PIN DESCRIPTION

MR

PL

CPu

CPo

Mode

CPu

Count Up Clock Input (Active Rising Edge)

H

X

X

X

Reset (Asyn.)

CPo

Count Down Clock Input (Active Rising Edge)

L

L

X

X

Preset (Asyn.)

MR

Asynchronous Master Reset (Active HIGH)

L

H

H

H

No Change

PL

Asynchronous Parallel Load Input (Active LOW)

L

H

i

H

Count Up

L

H

H

i

Count Down

Pin Names

Description

Pn

Parallel Data Inputs

On

Flip-Flop Outputs

TCo

Terminal Count Down (Borrow) Output (Active
LOW)

TCu

Terminal Count Up (Carry) Output (Active LOW)

NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
i = LOW-to-HIGH Clock Transition.

2621 tbl 06

2621 tbl05

ABSOLUTE MAXIMUM RATINGS(1)

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Commercial

Military

Unit

Symbol

Parameter(1)

Conditions

VTERM(2) Terminal Voltage
with Respect
to GND

-0.5 to +7.0

-0.5 to +7.0

V

CIN

Input
Capacitance

VIN

COUT

-0.5 to Vee

-0.5 to Vee

V

Output
Capacitance

VOUT

VTERM(3) Terminal Voltage
with Respect
toGND

Symbol

Rating

TA

Operating
Temperature

o to +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

rnA

= OV
= OV

Typ.

Max.

Unit

6

10

pF

8

12

pF

NOTE:
2621 tbl02
1. This parameter is guaranteed by characterization data and not tested.

NOTE:
2621 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal
voltage may exceed Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals.
3. Output and I/O terminals.

6.39

2

IDT54174FCT193/A
FAST CMOS UP/DOWN BINARY COUNTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C, VCC = 5.0V ± 5%; Military; TA = -55°C to +125°C, Vcc
Test Condltions(1)
Symbol
Parameter

= 5.0V ± 10%
Min_

Typ.(2)

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

VIL

Input LOW Level

Guaranteed Logic LOW Level

IiH

Input HIGH Current

Vee = Max.

-

-

IiL

Input LOW Current

-

-

VI = Vee
VI = 2.7V
VI = 0.5V
VI = GND

Max.

Unit

-

V

0.8

V

5
5(4)

Il A

_5(4)
-5

VIK

Clamp Diode Voltage

Vee = Min., IN = -18mA

-

-0.7

-1.2

V

los

Short Circuit Current

Vee = Max.l3), Vo = GND

-60

-120

-

mA

VOH

Output HIGH Voltage

Vee = 3V, VIN = VLe or VHe, IOH = -321lA

VHC

Vce

-

V

Vee = Min.

IOH = -3OOIlA

VHC

Vee

IOH = -12mA MIL.

2.4

4.3

-

10H = -15mA COM'L.

2.4

VIN = VIH or VIL

VOL

Output LOW Voltage

-

4.3

Vee = 3V, VIN = VLC or VHe, IOL = 300llA

-

GND

Vee = Min.

IOL = 300llA

GND

VIN = VIH or VIL

IOL = 32mA MIL.

-

VLe
VLd 4)

0.3

0.5

0.3

0.5

IOL = 48mA COM'L.

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

V

26211b103

I

6.39

3

IDT54174FCT193/A
FAST CMOS UP/DOWN BINARY COUNTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLV CHARACTERISTICS
VLC

= O.2V, VHC = VCC - 0 2V

Symbol

Test Condltlons(1)

Parameter

Icc

Quiescent Power
Supply Current

Vee", Max.
VIN ~ VHC; VIN $ VLC

61cc

Quiescent Power Supply
Current TIL Inputs HIGH

Vcc

Icco

Ic

= Max., VIN = 3.4V(3)
I

VIN ~ VHC

Dynamic Power

Vcc", Max.

Supply Current(4)

Outputs Open
Preset Mode
PL '" MR = CPu", CPo", GND
One Input Toggling
50% Duty Cycle

Total Power Supply
Current(6)

Vcc

= Max.

VIN ~ VHC
VIN $ VLC
(FCT)

One Bit Toggling

VIN '" 3.4V

at fi = 10MHz
50% Duty Cycle

VIN '" GND

= Max.

Max.

Unit

0.2

1.5

mA

-

0.5

2.0

mA

-

0.15

0.25

VIN $ VLC

Outputs Open
Preset Mode
PL '" MR '" CPu", CPo", GND

Vcc

Typ.(2)

-

Min.

VIN ~ VHC

Outputs Open
Preset Mode
PL '" MR '" CPu", CPo", GND

VIN $ VLC
(FCT)

Four Bits Toggling

VIN '" 3.4V

at fi '" 5MHz

VIN

mAl
MHz

-

1.7

4.0

-

2.0

5.0

-

3.2

6.5(5)

-

4.2

10.5(5)

mA

= GND

50% Duty Cycle
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +2SoC ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ie = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + t.lcc DHNT + ICCD (fcp/2 + Ii Ni)
Icc = Quiescent Current
t.lcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic CUrrent Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.39

26211b104

4

IDT54174FCT193/A
FAST CMOS UP/DOWN BINARY COUNTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT193A

IDT54/74FCT193
Com'l.
Symbol

Parameter

Cond It lon(1)

Mln.(2) Max.

Mil.
Mln.(2) Max.

Com'l.
Min.(2) Max.

Mil.
Min.(2) Max.

Unit

2.0

10.0

2.0

10.5

2.0

6.5

2.0

6.9

ns

Propagation Delay
CPu or CPo to an

2.0

13.5

2.0

14.0

2.0

8.8

2.0

9.1

ns

tPLH
tPHL

Propagation Delay
Pn to an

2.0

15.5

2.0

16.5

2.0

10.1

2.0

10.8

ns

tPLH
tPHL

Propagation Delay
PL to an

2.0

14.0

2.0

13.5

2.0

8.8

2.0

9.1

ns

tPHL

Propagation Delay
MR to an

3.0

15.5

3.0

16.0

3.0

10.1

3.0

10.4

ns

tPLH

Propagation Delay
MRto TCu

3.0

14.5

3.0

15.0

3.0

9.4

3.0

9.8

ns

tPHL

Propagation Delay
MR to TCo

3.0

15.5

3.0

16.0

3.0

10.1

3.0

10.4

ns

tPLH
tPHL

Propagation Delay
PL to TCu or TCo

3.0

16.5

3.0

18.5

3.0

10.8

3.0

12.0

ns

tPLH
tPHL

Propagation Delay
Pn to TCu or TCo

3.0

15.5

3.0

16.5

3.0

10.1

3.0

10.8

ns

tsu

Set-up Time, HIGH or LOW
Pn to PL

5.0

-

6.0

-

4.0

-

5.0

-

ns

tH

Hold Time, HIGH or LOW
Pn to PL

2.0

-

2.0

-

1.5

-

1.5

-

ns

tPLH
tPHL

Propagation Delay
CPu or CPo to TCu or TCo

tPLH
tPHL

CL = 50pF
RL = 500n

tw

PL Pulse Width, LOW

6.0

-

7.5

-

5.0

-

ns

CPu or CPo Pulse Width
HIGH or LOW

5.0

-

7.0

-

4.0(3)

-

6.5

tw

6.0

-

ns

tw

CPu or CPo Pulse Width LOW
(Change of Direction)

10.0

-

12.0

-

8.0

-

10.0

-

ns

tw

MR Pulse Width HIGH

6.0

-

6.0

-

5.0

-

5.0

Recovery Time
PL to CPu or CPo

6.0

-

8.0

-

5.0

-

7.0

-

ns

tREM
tREM

Recovery Time
MR to CPu or CPo

4.0

-

4.5

-

3.0

-

3.5

-

ns

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.

ns

2621 tbl07

6.39

5

I

IDT54174FCT193/A
FAST CMOS UP/DOWN BINARY COUNTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vee

SWITCH POSITION
()-e

7.0V

soon

Test

Switch

Open Drain
Disable.Low
Enable Low.

Closed

All Other Outputs

Open

DEFINITIONS:
26211b109
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

Z&t

PULSE WIDTH

--= ~~V

J

__..x.....x~ -

OV

tsu --''1+---+1

lOWHIG~J~S~=t- ~'5V

6J

TIMING
INPUT _ _ _ _ _ _ _

- 3V
V
_

ASYNCHRONOUS CONTROL

HIGH.LOW.HIGH

- 3V
PRESET - - - - _ . .
- - + - - - - - - 1.SV
CLEAR
ETC. - - - - - - - , ,--+---~------- - OV
SYNCHRONOUS CONTROL
- 3V
J
-1.SV
__
- OV
CLOCK EN~~~~ ~I- tsu

P~E~~~

-

tw

---1.SV

PULSE

vvJr

..x.....x~

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

_--"""""----3V
SAME PHASE
INPUT TRANSITION

)----'" -+----- OV
3.SV

OUTPUT

VOL
OUTPUT

OPPOSITE PHASE
INPUT TRANSITION

SWITCH

VOH

NORM~~~ OPEN
'__ _ _. . J _ _ _ _

OV

OV

NOTES
2621 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-H I GH.
2. Pulse Generator for All Pulses: Rate:5 1.0 MHz; ZO:5 50n; tF:5 2.5ns;
tR:5 2.5ns.

6.39

6

IDT54174FCT193/A
FAST CMOS UP/DOWN BINARY COUNTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATIONIDT

x

Temperature
Range

FCT XXXX
Device
Type

x

x

Package

Process

~~Iank
E

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

193
193A

Up/Down Binary Counter
Fast Up/Down Binary Counter

54

-55°C to +125°C
0° to +70°C

P

D

~------------~ISO

L

I

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~I

Commercial
MIL-STD-883, Class B

174

2621 drw03

I

6.39

7

t;)

IDT54/74FCT2401 A/C
IDT54/74FCT241 lAIC
IDT54/74FCT2441 A/C
IDT54/74FCT5401 A/C
IDT54/74FCT541 lAIC

FAST CMOS OCTAL
BUFFER/LINE DRIVER

Integrated Devfce Technology, Inc.

FEATURES:

DESCRIPTION:

• IOT54/74FCT240/241/244/540/541 equivalent to FASTn.4
speed and drive
• IDT54/74FCT240A/241A/244A/540A/541A 25% faster
than FASpM
• IDT54/74FCT240C/241 C/244C/540C/541 C up to 55%
faster than FAST"'
• IOL = 64mA (commercial) and 48mA (military)
• CMOS power levels (1 mW typo static)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STO-883, Class B
• Meets or exceeds JEOEC Standard 18 specifications

The IDT octal buffer/line drivers are built using advanced
CEMOSTM a dual metal CMOS technology. The IOT54/
74FCT2401AlC, IOT54/74FCT241 lAIC and I OT54/74FCT244/
AlC are designed to be employed as memory and address
drivers, clock drivers and bus-oriented transmitter/receivers
which provide improved board density.
The IOT54/74FCT540lAlC and IOT54/74FCT541/AlC are
similar in function to the IOT54/74FCT240lAlC and IOT54/
74FCT244/AlC, respectively, except that the inputs and'outputs are on opposite sides of the package. This pinout
arrangement makes these devices especially useful as output
ports for microprocessors and as backplane drivers, allowing
ease of layout and greater board density.

FUNCTIONAL BLOCK DIAGRAMS
DEA

----0---+--- O1i:o

000 --+----C< 1-+--- OBo

DEA-----., .----DEs

DEB"

>--+--- OAo

Do

::>0---+---- 00"

OBo - - + - - < 1--+--- DBo

01

~_-+-

___ 01"

OAl

--+--I

;>0---+--- OJ\ 1

OAl

OAl

02

::>0---+---- 02"

001

--+----C< 1-+--- OBl

OB1

OBl

03

::>0---+---- 03"

OM

--t--i

> - - + - - - OA2

04

: > 0 - - 4 - - - - 04"

OB2

05

: > 0 - - 4 - - - - OS"

> - - - - - OA3

06

::>0---+---- 06"

OB3

07

: > 0 - - 4 - - - - 07"

:;:.0..-+--- 01i:2

OA2

OB2

OB2

002
OA3

--t--i ::>0-----

003
IOT5417 4FCT240

OA3

OA3

DB3

OB3

--+--I

--f-l

IOT54174FCT241/244

"OEB for 241, NB for 244

IDT54174FCT540/541

"Logic diagram shown for 'FCT540.
'FCT541 is the non-inverting option.
2606 dwg 0 t-{)3

CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
?lt990 Integrated Device Technology. Inc.

6.40

JUNE 1990
DSC-4610!-

1

IDT54!7 4FCT240/241/244/54 0/541/AlC
FAST CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
I DT54/74FCT240
INDEX

Vee

OEA

19

OEB

000

3

18

01\0

DA1

4
5
6

P20-1 17
020-1 16
S020-2 15

DBa

DA1

01\1

001

DB1

DA2

0A2

002

DB2

DA3

DAo

001
OM
002
DA3

003
GND

&

7
8
9
10

E20-1

14
13
12
11

I
I I I I
i---J L.......I I

II

II

I

I L--I L---I

2 U 20 19
1
18 [: 01\0

3

17[: DBa
16 [: 01\1

L20-2

[=

DB1
15
14[= 01\2

910111213

0A3
I"

DB3

I"

I

I"

I

Cl

C')

I"

I
C')

I Ir-tI

N

C')

Oa~tj~

DIP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW

I DT54/74FCT241 1244
o

INDEX

Vee

OEA

lill

U

p

DAo

2

19

OEB"

OBo
DA1

3

18

OAo

4
5
6

P20-1 17
020-1 16
8020-2 15

DBa

DA1

=]4

1

18[= OAo

OA1

OB1

DB1

DM

=]5
=] 6

L20-2

14
13

OM

OB2

:]7

17[= DBa
16 [= OA1
15[: DB1

DB2

DA3 :] 8

12
11

OA3

OB1

DM

&

OB2

7
8

DA3
OB3
GND

E20-1

9

10

I

I I

I:

: I

II

I

32L-!2019

14[: OA2
9 10 11 12 13

II

11 11 11 11 r-l

I

DB3

I

I

I

I

I

I

II

I

a

cBCl~~C)
o
Cl 0 0

DIP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW

·OEs for 241, 'DEs for 244

I DT54/74FCT540/541
OEA
Do

01
02
03

04

05

2
3
4
5
6

P20-1
020-1
S020-2
&
E20-1

19

OEB

18

00"

17
16
15

01"

02

:] 4

02"

03

:] 5

03"

04

:] 6

04"

05

]7

Os"

06

07"

06

7
8

D7

9

14
13
12

10

11

GND

INDEX

Vee

I

I

I

I

I

II
II
I
I L--I L---I

L-.I 1--1 I

3

1

17[:
16[:
15C

=] 8

14[=
910111213
I"

o

I

I"

I

~

CD

I"

I

I"

I Ir-tI

6~ B

LCC
TOP VIEW

·Ox for 540, Ox for 541

6.40

19
18[:

L20-2

Os"

DIP/SOIC/CERPACK
TOP VIEW

L-! 20

2

2606 env' 04-09

2

IDT54174FCT240/241/244/540/541/AIC
FAST CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE

PIN DESCRIPTION

Inouts(1)
OEs OEs(2)

Pin Names
OEA,OEs

Description
3-State Output Enable Inputs (Active LOW)

OEA

OEs(1)

3-State Output Enable Input (Active HIGH)

L

L

Dxx

Inputs

L

Oxx

Outputs

H

NOTE:
1. OEs for 241 only.

260611>104

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
TSIAS
Temperature
Under Bias
TSTG
Storage
Temperature
Power Dissipation
PT
lOUT

DC Output
Current

Outputs(1)
D

240

241

244

540

H

L

H

L

L

H

L

L

H

H

L

H

H

L

H

H

L

X

Z

Z

Z

Z

NOTE:
1. H = High Voltage Level
X = Don't Care
L = Low Voltage Level
Z = High Impedance
2. OEs for 241 only.

541

Z
26061b105

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Military

Commercial
-0.5 to +7.0

-0.5 to +7.0

Unit
V

-0.5 to Vee

-0.5 to Vee

V

o to +70

-55 to +125

°C

-55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

0.5

0.5

W

120

120

mA

Symbol
CIN
GoUT

Parameter (1)

Conditions

Typ.

Input
Capacitance

VIN

= OV

6

Max.
10

Unit
pF

Output
Capacitance

VOUT

= OV

8

12

pF

NOTE:
1. This parameter is measured at characterization but not tested.

26061b102

NOTES:
26061b101
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and I/O terminals only.

6.40

3

IDT54f74FCT240/241/244/540/541/AlC
FAST CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VlC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C, VCC = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vec= 5.0V ± 10%
Symbol
VIH

Parameter
Input HIGH Level

Test Conditions
Guaranteed Logic HIGH Level

Vil

Input LOW Level

Guaranteed Logic LOW Level

IIH

Input HIGH Current

Vce = Max.

(l)

VI = \tc
VI = 2.7V

III

Input LOW Current

VI = 0.5V
VI = GND

10ZH

Off State (High Impedance)

Vee = Max.

Vo= Vcc

Output Current

Vo= 2.7V

lozl

Vo= 0.5V
Vo=GND

VIK

Clamp Diode Voltage

Vce = Min., N = -18mA

los

Short Circuit Current

Vcc = Max.(3), Vo= GND

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

Min.
2.0

Typ.

(2)

Max.

Unit

-

V

0.8

V

5
5(4)

Il A

-

-5(4)

-

-5

-

10
10(4)

-

-0.7

-60

-120

-

mA
V

-

-

-10(4)
-10
-1.2

Vee = 3V, \tiN = VlC or VHC, 10H = -321lA

VHC

Vee

-

Vee = Min.

10H = -3001lA

VHC

Vee

-

VIN = VIHor Vil

10H= -12mA MIL.

2.4

4.3

-

10H = -15mA COM'L.

2.4

4.3

Vee = 3V, \tiN = Vle or VHC, 10l = 300llA
Vce = Min.

10l = 300llA

VIN = VIHor Vil

10l = 48mA MIL.
10l = 64mA COM'L.

-

V

-

GND

VlC

GND

VlC(4)

0.3

0.55

0.3

0.55

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

6.40

Il A

V

2606 tbl 03

•

4

IDT54174FCT240/241/244/540/541/A1C

FAST CMOS OCTAL BUFFER/UNE DRIVER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC

=O.2V; VHC =VCC - O.2V

Symbol
Icc
~Icc

ICCD

Parameter
Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current(4)

TypJ2)

Max.

Unit

-

0.2

1.5

mA

-

0.5

2.0

mA

-

0.15

0.25

mAl
MHz

-

1.7

4.0

mA

VIN .. 3.4V
VIN =GND

-

2.0

5.0

VIN~ VHC
VIN S VLC
(FCT)

-

3.2

6.5(5)

-

5.2

14.s(5)

Test Condltlons(1)
VCC - Max.
VIN> VHC' VIN < VLC
Vcc- Max.
VIN .. 3.4V(3)
Vcc- Max.
Outputs Open
OEA - OEB .. GND or
OEA-GND,

VIN~VHC

Min.

VINSVLC

OEB - Vcc
One Input Toggling
50% Duty CVcle
Ic

Total Power Supply Current (6)

Vcc .. Max.
Outputs Open
fi -10MHz
50% Duty Cycle
OEA - OEB .. GND or
OEA- GND,

VIN~VHC

VINSVLC
(FCT)

OEB - VCC
One Bit Toggling
Vcc .. Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle'
OEA - OEB - GND or
OEA .. GND,

VIN - 3.4V
VIN= GND

OEB - Vcc
Eight Bits Toggling
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vce or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
S. Ic = laUIESCENT + IINPUTS + IDYNAMIC
Ic = Ice + t.lce DHNT + IceD (fcp/2 + fiNi)
Icc = Quiescent Current
t.lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
IceD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.40

26061bI06

5

I OT5417 4FCT240/241/244/540/5411AlC
FAST CMOS OCTAL BUFFER/UNE DRIVER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT240(1,2)
54174FCT240
Com'l.
Symbol

Parameter

tPLH
tPHL

Propagation Delay
DNtoON

tPZH
tPZL
tPHZ
tPLZ

Condition

Q= 50pF

54/74FCT240C

54/74FCT240A

Mil.

Com'l.

Mil.

Com'l.

Mil.

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

Unit

1.5

8.0

1.5

9.0

1.5

4.8

1.5

5.1

1.5

4.3

1.5

4.7

ns

Output Enable Time

1.5

10.0

1.5

10.5

1.5

6.2

1.5

6.5

1.5

5.0

1.5

5.7

ns

Output Disable Time

1.5

9.5

1.5

10.0

1.5

5.6

1.5

5.9

1.5

4.5

1.5

4.6

RL = 500n

ns
26061b107

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT241 AND FCT244(1,2)
54174FCT241 1244
Com'l.
Symbol

Parameter

tPLH
tPHL

Propagation Delay
DNto ON

tPZH
tPZL
tPHZ
tPLZ

Condition

Q= 50pF

54/74FCT241A1244A .

Mil.

Com'l.

Mil.

54/74FCT241 C/244C
Com'l.

Mil.

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

Unit

1.5

6.5

1.5

7.0

1.5

4.8

1.5

5.1

1.5

4.1

1.5

4.6

ns

Output Enable Time

1.5

8.0

1.5

8.5

1.5

6.2

1.5

6.5

1.5

5.8

1.5

6.5

ns

Output Disable Time

1.5

7.0

·1.5

7.5

1.5

5.6

1.5

5.9

1.5

5.2

1.5

5.7

ns

RL = 500n

26061b108

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT540 AND FCT541 (1,2)
5417 4FCT540/541

Com'l.
Symbol

tPLH
tPHL

Parameter

Condition

Propagation Delay
DNtoON

Q= 50pF

IDT54174FCT540

RL = 500n

54174FCT540A/541 A

Mil.

Com'l.

Mil.

54174FCT540C/541C

Com'l.

Mil.
Unit

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

1.5

8.5

1.5

9.5

1.5

4.8

1.5

5.1

1.5

4.3

1.5

4.7

ns

tPLH
tPHL

Propagation Delay
DNto ON
IDT54174FCT541

1.5

8.0

1.5

9.0

1.5

4.8

1.5

5.1

1.5

4.1

1.5

4.6

ns

tPZH
tPZL

Output Enable Time

1.5

10.0

1.5

10.5

1.5

6.2

1.5

6.5

1.5

5.8

1.5

6.5

ns

Output Disable Time

1.5

9.5

1.5

10.0

1.5

5.6

1.5

5.9

1.5

5.2

1.5

5.7

ns

tPHZ
tPLZ
NOTES:

26061b109

1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

6.40

6

I

I DT5417 4FCT240/241 /244/540/541 /AlC
FAST CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vcc

SWITCH POSITION
0--.7.0V

soon

Ti

RT

50pF

~CL

soon

zzt.

j

tsu --4'14--~

Switch
Closed

All Other Outputs

Open

2606 tbl10
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

Test
Open Drain
Disable Low
Enable Low

PULSE WIDTH

~ OV
f~v

~'-'...M~ -

TIMING
INPUT

lOW-HIG~i~~

- 3V
V
_

6J

ASYNCHRONOUS CONTROL
PRESET - - - - ,
CLEAR
ETC. - - - - ,

-

3V
1.5V

-

OV

---4------

=t-

HIGH-laW-HIGH
PULSE

~ 15V
IW

~

__

1.5V

SYNCHRONOUS CONTROL
CLOCK

:~~~~~ vvJr
I
~tsu

'"'-.-....M~

ETC.

- 3V
-1.5V
- OV

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

SAME PHASE
INPUT TRANSITION

)0-......,

+ - - - - OV

OV
3.5V

~--..,.-t--

OUTPUT

DISABLE

VOH
-1.5V

VOL

VOL
OUTPUT

OPPOSITE PHASE
INPUT TRANSITION

SWITCH

VOH

NORM~~~ OPEN

OV

' - - - _ . I - - - - OV

NOTES
2606 drw 10
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ son; tF ~ 2.5ns;
tR ~ 2.5ns.

6.40

7

IDT54f7 4FCT240/241/244/540/541/AlC
FAST CMOS OCTAL BUFFER/UNE DRIVER

MIUTARV AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT=--_X=X_ _ FCT =-....,.X_X-:;XX,,;.-_
Temp. Range
Device Type

x

x

Package

Process

y~lank
P

D
~------------~SO

L

E
240
241
244
540
541
240A
241A
~--------------------~244A

540A
541A
240C
241C
244C
540C
541C
54

~-------------------------------------474

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Inverting Octal Buffer/Line Driver
Non-Inverting Octal BufferlLine Driver
Non-Inverting Octal Buffer/Line Driver
Inverting Octal Buffer/Line Driver
Non-Inverting Octal Buffer/Line Driver
Fast Inverting Octal Buffer/Line Driver
Fast Non-Inverting Octal BufferlLine Driver
Fast Non-Inverting Octal Buffer/Line Driver
Fast Inverting Octal BufferlLine Driver
Fast Non-Inverting Octal BufferlLine Driver
Super Fast Inverting Octal Buffer/Line Driver
Super Fast Non-Inverting Octal Buffer/Line Driver
Super Fast Non-Inverting Octal Buffer/Line Driver
Super Fast Inverting Octal Buffer/Line Driver
Super Fast Non-Inverting Octal Buffer/Line Driver
-55°C to + 125°C
O°Cto +70°C
2606 cnv· 15

II

6.40

8

G®

IDT54/74FCT245/A1C
IDT54/74FCT6401AlC
I DT54/74 FCT645/A1C

FAST CMOS OCTAL
BIDIRECTIONAL
TRANSCEIVERS

Integrated DevJce Technology, Inc.

FEATURES:

DESCRIPTION:

• IDT54/74FCT245/640/645 equivalent to FASTTM speed
and drive
• IDT54/74FCT245A/640A/645A 25% faster than FASl'M
• IDT54/74FCT245C/640C/645C 40% faster than FASl'M
• TIL input and output level compatible
.
• CMOS output level compatible
• IOL = 64mA (commercial) and 48mA (military)
• Input current levels only 5JlA max.
• CMOS power levels (2.5mW typical static)
• Direction control and over-riding 3-state control
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class Band
DESC listed
• Meets or exceeds JEDEC Standard 18 specifications

The IDT octal bidirectional transceivers are built using
advanced CEMOSTM, a dual-metal CMOS technology. The
I DT54/74 FCT245/A/C , IDT54/74FCT640/A/C and IDT541
74FCT645/A/C are designed for asynchronous two-way
communication between data buses. The transmit/receive
(TiR) input determines the direction of data flow through the
bidirectional transceiver. Transmit (active HIGH) enables
data from A ports to B ports, and receive (active LOW) from B
ports to A ports. The output enable (OE) input, when HIGH,
disables both A and B ports by placing them in HIGH Z
condition.
The IDT54/74FCT245/A/C and IDT54/74FCT645/A/C
transceivers have non-inverting outputs.
The
IDT54/74FCT640/A/C has inverting outputs.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS
T/R

Vce

Ao
A1
A2

80
81

A3

82

DE

A4

83

As

84
8s
86
87

A6

A7

GND
DIP/SOIC/CERPACK
TOP VIEW

INDEX
L-J l...J I

3

A2

] 4

A3

] 5

A4

] 6

f L-..J L...J

2' '20 19

~

18 [

L20-2

80

17 [

B1

16 [

B2

As

] 7

15 [

83

A6

] 8

14 [

B4

9

10 11 1213

"

ro "

ro "

LCC
TOP VIEW

2534 dow 02

FCT245, 645 are non-inverting options.
FCT640 is the inverting option.
CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a registered trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
11:>1990 Integrated Device Technology. Inc.

6.41

JUNE 1990
DSC-4611/·

IDT54f74FCT245/A1C,IDT54/74FCT640/A/C,IDT54f74FCT645/A1C
FAST CMOS OCTAL BIDIRECTIONAL TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TAB LE(2)

PIN DESCRIPTION
Pin Names

Description

Inputs
OE

T/R

L

L

Bus B Data to Bus A(1)

Side A Inputs or 3-State Outputs

L

H

Bus A Data to BusS(1)

Side B Inputs or 3-State Outputs

H

X

High Z State

OE

Output Enable Input (Active LOW)

T/R

Transmit/Receive Input

Ao-A7
Bo-B7

Outputs

NOTE:

2534 tbl05

2534 tbl06

1. 640 is inverting from input to output.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage

TA
TBIAS
TSTG
PT
lOUT

with Respect
toGND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
Power Dissipation
DC Output Current

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

o to +70

-55 to +125

°C

-55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

0.5
120

0.5
120

W
mA

Parameter(1)

Conditions

Typ.

Max.

CIN

Input Capacitance

6

10

pF

CliO

110 Capacitance

= OV
Your = OV

8

12

pF

Symbol

VIN

Unit

NOTE:
2534 tbl 02
1. This parameter is measured at characterization but not tested.

NOTES:
2534 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +0.5V unless otherwise noted.
.
2. Inputs and Vcc terminals.
3. Outputs and 110 terminals.

6.41

II

2

IDT54174FCT2451A1C, IDT54/74FCT640/A/C, IDT54174FCT6451A1C
FAST CMOS OCTAL BIDIRECTIONAL TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C, vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc

= 5.0V ± 10%
Min.

Typ.(2)

Max.

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

V

VIL

Input LOW Level

Guaranteed Logic LOW Level

0.8

V

Input HIGH Current

Vee = Max

-

5
5(4)

~A

Symbol

IIH
ilL

Test Condltions(1)

Parameter

(Except I/O pins)

VI = 2.7V

-

Input LOW Current

VI = 0.5V

-

VI = GND

-

VI= Vee
VI= 2.7V

-

VI= 0.5V

-

VI= GND

-

VI = Vee

(Except 1/0 pins)
IIH

Input HIGH Current

Vec = Max

(I/O pins only)
ilL

Input LOW Current
I

, (I/O pins only)
VIK

Clamp Diode Voltage

Vee = Min., IN = -18mA

los

Short Circuit Current

Vce = MaxP), Vo = GND

VOH

Output HIGH Voltage

Vee = 3V, VIN = VLC or VHe, 10H = -32~A
Vee = Min.
VIN = VIH or VIL

VOL

-60

-

-

_5(4)
-5

_15(4)
-15

"';'0.7

-1.2

-120

mA
V

VHe

Vce

-

Vcc

10H = -12mA MIL.

2.4

4.3

-

10H = -15mA COM'L.

2.4

-

4.3
GND

Output LOW Voltage

Vec = 3V, VIN = VLe or VHC, IOL =

(Port A and Port B)

Vcc = Min.

10L = 300~A

VIN = VIH or VIL

10L = 48mA MIL.

-

0.3

0.55

10L = 64mA COM'L.

-

0.3

0.55

GND

V

VLC
VLC(4)

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = S.OV, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration 01 the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

6.41

V

-

VHC

-

~A

15
15(4)

10H = -300~A

300~A

Unit

2534 tbl 03

3

IDT54174FCT2451AlC, I DT54/74 FCT6401A/C, IOT54174FCT645/A1C
FAST CMOS OCTAL BIDIRECTIONAL TRANSCEIVERS .

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC

= O.2V; VHC = VCC -

Symbol

O.2V

Parameter

Test Condltlons(1)

Typ.(2)

Max.

Unit

Icc

Quiescent Power Supply Current

Vee = Max.
VIN ~ VHC; VIN ~ VLC

-

0.5

1.5

mA

~Icc

Quiescent Power Supply Current
TIL Inputs HIGH

Vee = Max.
VIN = 3.4V(3)

-

0.5

2.0

mA

Iceo

Dynamic Power Supply Current(4)

VIN ~ VHC
VIN ~ VLC

-

0.15

0.25

mA/MHz

Vee = Max.
Outputs Open
fi = 10MHz

VIN ~ VHC

-

2.0

4.0

mA

50.!o Duty Cycle

VIN = 3.4V
VIN =GND

-

2.3

5.0

Vee = Max.
Outputs Open
fi = 2.5MHz

VIN ~ VHC
VIN ~ VLC
(FCT)

-

3.5

6.5(5)

50% Duty Cycle

VIN = 3.4V
VIN =GND

-

5.5

14.5(5)

Vee = Max.
Outputs Open
OE = GND
Tiff = GND or VCC
One Input Toggling
50% Duty Cycle

Ic

Total Power Supply Current lb )

T/R = OE = GND

Min.

VIN ~ VLC
(FCT)

One Bit Toggling

T/R = OE =GND
Eight Bits Toggling

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vee or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fiNi)
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cyde for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.41

25341b104

4

I DT5417 4FCT2451 AlC, IDT54/74FCT6401A/C, I OT5417 4FCT6451AlC
FAST CMOS OCTAL BIDIRECTIONAL TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT24S/A/C
54!74FCT245
Com'l.
Symbol

Parameter

54!74FCT245A

MIl.

Com'l.

54!74FCT245C

Mil.

Condition(l) Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max.

Com'l.
Mln.(2)

Mil.

Max. Mln,l2) Max. Unit

1.5

7.0

1.5

7.5

1.5

4.6

1.5

4.9

1.5

4.1

1.5

4.5

ns

Output Enable Time
OEtoAor 8

1.5

9.5

1.5

10.0

1.5

6.2

1.5

6.5

1.5

5.8

1.5

6.2

ns

tPHZ
tPLZ

Output Disable Time
OE to A or 8

1.5

7.5

1.5

10.0

1.5

5.0

1.5

6.0

1.5

4.8

1.5

5.2

ns

tPZH
tPZL

Output EnableTime

1.5

9.5

1.5

10.0

1.5

6.2

1.5

6.5

1.5

5.8

1.5

6.2

ns

T/R to A or 8(3)

tPHZ
tPLZ

1.5

7.5

1.5

10.0

1.5

5.0

1.5

6.0

1.5

4.8

1.5

5.2

ns

T/R to A or 8(3)

tPLH
tPHL

Propagation Delay
A to 8, 8to A

tPZH
tPZL

CL = 50 pF
RL = 500n

Output Disable Time

2534 fbi 07

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT640/A/C
54!74FCT640
Com'l.
Symbol

Parameter

54!74FCT640A

Mil.

Com'l.

54174FCT640C

Mil.

Condition(l) Min.(2) Max. Mln.(2) Max. Min.(2) Max. Mln.(2) Max.

Mln.(2)

Mil.

Max. Mln.(2) Max. Unit

2.0

7.0

2.0

8.0

1.5

5.0

1.5

5.3

1.5

4.4

1.5

4.7

ns

Output Enable Time
OEto Aor 8

2.0

13.0

2.0

16.0

1.5

6.2

1.5

6.5

1.5

5.8

1.5

6.2

ns

tPHZ
tPLZ

Output Disable Time
OEto Aor 8

2.0

10.0

2.0

12.0

1.5

5.0

1.5

6.0

1.5

4.8

1.5

5.2

ns

tPZH
tPZL

Output Enable Time

2.0

13.0

2.0

16.0

1.5

6.2

1.5

6.5

1.5

5.8

1.5

6.2

ns

T/R to A or 8(3)

tPHZ
tPLZ

2.0

10.0

2.0

12.0

1.5

5.0

1.5

6.0

1.5

4.8

1.5

5.2

ns

T/R to A or 8(3)

tPLH
tPHL

Propagation Delay
A to 8, 8 to A

tPZH
tPZL

CL = 50 pF
RL = 500n

Com'l.

Output Disable Time

2534 fbi 08

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT64S/A/C
54!74FCT645
Com'l.
Symbol

Parameter

54!74FCT645A

Mil.

Com'l.

54174FCT645C

Mil.

Condition(l) Min.(2) Max. Min.(2) Max. Min.(2) Max. ~in.(2) Max.

Com'l.
Min,l2)

Mil.

Max. Min,l2) Max. Unit

1.5

9.5

1.5

11.0

1.5

4.6

1.5

4.9

1.5

4.1

1.5

4.5

ns

Output Enable Time
OEto Aor 8

1.5

11.0

1.5

12.0

1.5

6.2

1.5

6.5

1.5

5.8

1.5

6.2

ns

tPHZ
tPLZ

Output Disable Time
OEto A or 8

1.5

12.0

1.5

13.0

1.5

5.0

1.5

6.0

1.5

4.8

1.5

5.2

ns

tPZH
tPZL

Output Enable Time

1.5

11.0

1.5

12.0

1.5

6.2

1.5

6.5

1.5

5.8

1.5

6.2

ns

TIR to A or 8(3)

tPHZ
tPLZ

Output Disable Time
TIRto A or 8(3)

1.5

12.0

1.5

13.0

1.5

5.0

1.5

6.0

1.5

4.8

1.5

5.2

ns

tPLH
tPHL

Propagation Delay
A to 8, 8to A

tPZH
tPZL

CL = 50 pF
RL = 500n

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.

2534 fbi 09

6.41

5

IDT5417 4FCT2451 AlC, IDT54/74FCT6401 A/C, IDT5417 4FCT6451AlC
FAST CMOS OCTAL BIDIRECTIONAL TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vee

SWITCH POSITION
a-.7.0V

soon.

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2534 tbl 08
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal 10 ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zxt

j

PULSE WIDTH

""-...K.-K_

--= ~~V
-

OV

-

3V

-

OV

-

3V

-

OV

tsU~'I4--"'"

TIMING
INPUT ____________- '

- - - - - 1 f - - - - - - - l.SV

lOWHIG~~~S~

ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC. - - - - - , /

- - + - - - - - - 1.SV

=t-

HIGH-lOW-HIGH
PULSE

~ 15V
IW

_ _ 1.SV

SYNCHRONOUS CONTROL
CLOCK

:~~i~~ ~Su
vv:V
t J

ETC.

",,-..-.-~

- 3V
-1.SV
- OV

PROPAGATION DELAY

I

ENABLE AND DISABLE TIMES
ENABLE

DISABLE
3V

SAME PHASE
INPUT TRANSITION

OUTPUT

OV
3.SV

VOH
-1.SV

VOL

VOL
OUTPUT
NORMALLY
HIGH

OPPOSITE PHASE
INPUT TRANSITION
OV

VOH
SWITCH
OPEN
OV

NOTES
2534 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate::; 1.0 MHz; Zo::; SOn.; IF::; 2.Sns;
tR::; 2.Sns.

6.41

6

IDT54174FCT245/A1C, IDT54/74FCT640/A/C, IDT54174FCT645/A1C
FAST CMOS OCTAL BIDIRECTIONAL TRANSCEIVERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xx

Temperature
Range

FCT

x

x

x

Device
Type

Package

Process

~~Iank
E

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

245
640
645
245A
640A
645A
245C
640C
645C

Non-Inverting Buffer Transceiver
Octal Inverting Buffer Transceiver
Non-Inverting Buffer Transceiver
Fast Non-Inverting Buffer Transceiver
Fast Octal Inverting Buffer Transceiver
Fast Non-Inverting Buffer Transceiver
Super Fast Non-Inverting Buffer Transceiver
Super Fast Octal Inverting Buffer Transceiver
Super Fast Non-Inverting Buffer Transceiver

54
74

-55°C to + 125°C
O°C to +70°C

P

D
~--------------~

SO

L

'---------------1

Commercial
MIL-STD-883, Class B

2534 drw03

6.41

7

G®

IDT54174FCT273
IDT54/74FCT273A
IDT54174FCT273C

FAST CMOS
OCTAL FLIP-FLOP
. WITH MASTER RESET

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

•
•
•
•

The IDT54/74FCT273/A/C are octal D flip-flops built using
advanced CEMOSTM, a dual metal CMOS technology. The
IDT54/74FCT273/A/C have eight edge-triggered D-type flipflops with individual D inputs and 0 outputs. The common
buffered Clock (CP) and Master Reset (MR) inputs load and
reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop's 0
output.
All outputs will be forced LOW independently of Clock or
Data inputs by LOW voltage level on the MR input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.

•
•
•
•
•

IDT54/74FCT273 equivalent to FASTTM speed;
IDT54/74FCT273A 45%faster than FASTTM
IDT54/74FCT273C 55% faster than FASTTM
Equivalent to FASTTM output drive over full temperature
and voltage supply extremes
IOL = 48mA (commercial) and 32mA (military)
CMOS power levels (1 mW typo static)
TTL input and output level compatible
CMOS output level compatible
Substantially lower input current levels than FASTTM
(5~max.)

a

• Octal D flip-flop with Master Reset
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
Do

01

02

03

04

Os

06

07

CP

MR

as

00

07

06

2558 drw Ot

PIN CONFIGURATIONS

MR
Do
01
01
02
02
03
03
GNO

o 0la: 8 ,...
OO~>O

INDEX

VCC
07
07
06
06

00

,.

L-J L...J I

01
01
02
02
03

as
05
04
04

]
]
]
]
]

4
5
6
7
8

I

L...J L-.J

3 2 : : 20 19
18 [
17[
L20-2
16 [
15 [
14 [
9 1011 1213

07
06
06

as
05

"""11.-,11,....,

CP

"'Oo...vv

OzoOO

"Lee

DlP/SOIC/CERPACK
TOP VIEW

2558 drw 02

TOP VIEW

CEMOS is a trademark of Integrated Device Techology. Inc.
FAST is a registered trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1990 Integrated Device Technology. Inc.

6.42

JUNE 1990
DSC-4609/-

1

"
iii

IDT54174FCT2731A1C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION

FUNCTION TABLE

Pin Names

MR

CP

DN

Reset (Clear)

L

X

X

L

Clock Pulse Input (Active Rising Edge)

Load "1"

H

h

H

Data Outputs

Load "0"

H

i
i

I

L

ON

Data Input

Operating Mode

MR

Master Reset (Active LOW)

CP
ON

CAPACITANCE (TA = +25°C f = 1

ABSOLUTE MAXIMUM RATINGS(1)
Rating

VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

Symbol

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

rnA

Parameter(l)

CIN

Input Capacitance

COUT

Output Capacitance

OMHz)

Conditions Typ.

= OV
VOUT = OV
VIN

Max.

Unit

6

10

pF

8

12

pF

NOTE:
2558 lbl 02
1. This parameter is guaranteed by characterization data and not tested.

with Respect
toGND
TA

ON

NOTES:
2558 lbl06
H = HIGH voltage level steady-state
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock
transition
L = LOW voltage level steady state
I = LOW voltage level one sel-up time prior to the LOW-to-HIGH clock
transition
X = Don't care
i = LOW-to-HIGH clock transition

2558 tbl05

Symbol

Outputs

Inputs

Description

NOTES:
25581bIOl
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions forextended periods may affect reliability. No terminal voltage
may exceed Vcc by +O.5V unless otherwise noted.
2. Input and Vce terminals only.
3. Outputs and 110 terminals only.

6.42

2

IDT54174FCT273/A1C FAST CMOS
OCTAL D FLlP·FLOP WITH MASTER RESET

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C, VCC = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc
Symbol

Test Condltlons(l)

Parameter

= 5.0V ± 10%
Min.

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

Vil

Input LOW Level

Guaranteed Logic LOW Level

-

IIH

Input HIGH Current

Vcc

III

Input LOW Current

VIK

Clamp Diode Voltage

los

Short Circuit Current

= Min., IN = -18mA
Vee = MaxP), Vo = GND

VOH

Output HIGH Voltage

Vee = 3V, VIN .. VlC or VHC, 10H = -32JlA

= Max.

= Vcc
VI = 2.7V
VI = 0.5V
VI = GND
VI

Vee

Vee

= Min.

VIN .. VIH or VIL
Output LOW Voltage

= 3V, VIN = VlC or VHC,
Vee = Min.
VIN = VIH or Vil
Vee

-

Max.

V

5
5(4)

JlA

-1.2

V

-60

-120

-

mA

-

V

Vcc

VHC

Vcc

10H = -12mA MIL.

2.4

4.3

_5(4)
-5

4.3

-

GND

10l

= 300JlA
10l = 32mA MIL.

-

GND

VlC
VlC(4)

0.3

0.5

10l .. 48mA COM'L.

-

0.3

0.5

10l = 300JlA

V

0.8

-0.7

VHC

= -15mA COM'L.

Unit

-

-

10H .. -300JlA
10H

VOL

Typ.(2)

2.4

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

V

2558 tbl03

I

6.42

3

IDT54174FCT273!AlC FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC

= O.2V; VHC = VCC -

O.2V
Typ.(2)

Max.

Unit

Icc

Quiescent Power Supply Current

Vee = Max.
VIN ~ VHC; VIN ~ VLC

-

0.2

1.5

mA

~Icc

Quiescent Power Supply Current
TIL Inputs HIGH

Vee = Max.
VIN = 3.4V(3)

-

0.5

2.0

mA

ICCD

Dynamic Power Supply Current(4)

Vee = Max.
Outputs Open
MR = VCC
One Input Toggling
50% Duty Cycle

VIN ~ VHC
VIN ~ VLC

-

0.15

0.25

mA/MHz

Ic

Total Power Supply Current(6)

Vee = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
MR = VCC
One Bit Toggling
at fi = 5MHz
50% Duty Cycle

VIN ~ VHC
VIN ~ VLC
(FCT)

-

1.7

4.0

mA

-

2.2

6.0

-

4.0

7.8(5)

-

6.2

16.8(5)

Symbol

Parameter

Test Conditions(l)

Vee = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
MR = VCC
Eight Bits Toggling
fi = 2.5MHz
50% Duty Cycle

Min.

VIN
VIN

= 3.4V
= GND

VIN ~ VHC
VIN::; VLC
(FCT)
VIN
VIN

= 3.4V
= GND

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + !iNPUTS + IDYNAMIC
Ic = Icc + 61cc DHNT + ICCD (fCP!2 + fiNi)
Icc = Quiescent Current
61cc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.42

2558 tbl 04

4

IDT54f74FCT273/A1C FAST CMOS

OCTAL D FLlp·FLOP WITH MASTER RESET

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT273
Com'l.

Symbol
tPLH
tPHL

Parameter
Propagation Delay
Clock to Output

IDT54/74 FCT273A

Mil.

MIl.

Com'l.

IDT54/74FCT273C
Com'l.

MIl.
Conditlon(1) Mln.(2) Max. Mln.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
8.3
2.0
5.8
2.0 6.5
CL = 50 pF
2.0 13.0
2.0 15.0
2.0
7.2
2.0
ns
RL = soon

2.0

7.2

2.0

8.3

2.0

6.1

2.0

6.8

ns

-

2.0

-

2.0

-

2.0

-

2.0

-

ns

2.0

-

1.5

-

1.5

-

1.5

-

1.5

-

ns

-

7.0

-

6.0

-

6.0

-

6.0

-

6.0

-

ns

7.0

-

7.0

-

6.0

-

6.0

-

6.0

-

6.0

-

ns

4.0

-

5.0

-

2.0

-

2.5

-

2.0

-

2.5

-

ns

tPHL

Propagation Delay
MRto Output

2.0

tsu

Set·up Time HIGH
or LOW Data to CP

3.0

-

3.5

tH

Hold Time HIGH
or LOW Data to CP

2.0

-

tw

Clock Pulse Width
HIGH or LOW

7.0

tw

MR Pulse Width
LOW

tREM

Recovery Time
MRto CP

13.0

2.0

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

15.0

2558 tbl 07

I

6.42

5

IDT54n4FCT273/A1C FAST CMOS
OCTAL D FLlP·FLOP WITH MASTER RESET

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:

25581b108

CL = Load capacitance: indudes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

1

PULSE WIDTH

"V....x._-..JIo

-= nV
-

OV

tsu ~"14--~

TIMING
INPUT _ _ _ _ _ _J

lOW-HIG~~~~=t ~'5V

- 3V

--1-------

1.SV
OV

ASYNCHRONOUS CONTROL
PRESET - - - -..... ~-+---+---­ - 3V
CLEAR
- - + - - - - - - 1.SV
- OV
ETC. - - - - "
SYNCHRONOUS CONTROL
CLOCK

:~~i~~ vvJr
J
~tsu

HIGH-lOW-HIGH
PULSE

tw

--1.5V

- 3V
"V....x._-..JIo

ETC.

-1.SV
OV

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

,---~----3V

SAME PHASE
INPUT TRANSITION

~--"

-+----- OV
3.SV

OUTPUT

VOL

SWITCH
OPEN

OPPOSITE PHASE
INPUT TRANSITION
" " - _ _..I - - - -

VOH

OV

OV
NOTES

2558 drw 04

1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate S 1.0 MHz; Zo S son; tF S 2.5ns;
tR S 2.5ns.

6.42

6

IDT54174FCT273/A1C FAST CMOS
OCTAL D FLlp·FLOP WITH MASTER RESET

. MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XX

FCT

Temperature
Range

X

X

X

Device
Type

Package

Process

~~Iank
P
~------------~

~--------------------~

~

________________________________

~

Commercial
MIL·STD-883, Class B

E

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

273
273A
273C

Octal D Flip·Flop w/Clear
Fast Octal D Flip·Flop w/Clear
Super Fast Octal D Flip·Flop w/Clear

54
74

-55 C to +125 C
ODC to +70 DC

D
SO
L

D

D

2558 drw 03

I

6.42

7

t;)®

'I DT54/74/FCT299
IDT54/74/FCT299A

FAST CMOS
a-INPUT UNIVERSAL
SHIFT REGISTER

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• IDT54/74FCT299 equivalent to FASTTM speed
• IDT54/74FCT299A 25% faster than FASTTM
• Equivalent to FASTTM output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1 mW typo static)
• TIL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAS'fTM

The IDT54174FCT299 and IDT54174FCT299A are built
using advanced CEMOSTM, a dual-metal CMOS technology.
The IDT54/74FCT299 and IDT54174FCT299A are 8-input
universal shift/storage registers with 3-state outputs. Four
modes of operation are possible: hold (store), shift left, shift
right and load data. The parallel load inputs and flip-flop
outputs are multiplexed to reduce the total numberof package
pins. Additional outputs are provided for flip-flops 00 and 07
to allow easy serial cascading. A separate active LOW Master
Reset is used to reset the register.

(5J1A max.)
• 8-input universal shift register
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class 8
• Standard Military Drawing# 5962-86862 is listed on this
function. Refer to section 2

FUNCTIONAL BLOCK DIAGRAM
51

50

1/00

1/01

1102

1/03

1/04

1105

II0s

1/07
2561 drw 01

CEMOS is a 1rademark of Integraled Device Technology. Inc.
FAST is a registered trademark of Nalional Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1990 Integrated Device Technology. Inc.

6.43

JUNE 1990
DSC-4604I-

IDT54174FCT299/A
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

IW ~ ~
Iw
0000>00

INDEX
Vee
SI
DS7
07

So
OEI
OE2

1/06
1/04

3

1/06
1/04
1/02

] 4
] 5
] 6

1/00

]

1/03
1/01

00
MR
GND

00

'1

L20-2

7

] 8

17 [
16 [
15 [
14 [

~~~~~
ex: 0 0 a. ~
~t§~o~

CP
DSo

DS7
07

1/07

1/05
1/03

/

l

DIP/SOIC/CERPACK
TOP VIEW

Lce

2561 drw02

TOP VIEW

FUNCTION TAB LE(1)

PIN DESCRIPTION
Pin Names

I I '-' '-'
2 I 120 19
18 [

' - ' L....J

1/07
1/05

1/02
1/00

0

Description

Inputs

CP

Clock Pulse Input (Active Edge Rising)

DSo

Serial Data Input for Right Shift

MR

51

50

CP

Response

L

X

X

X

Asynchronous Reset 0~7 = LOW

DS7

Serial Data Input for Left Shift

H

H

H

;-

Parallel Load; liOn ~ On

So, SI

Mode Select Inputs

H

L

H

Shift Right; DSo ~ 00, 00 ~ 01, etc.
Shift Left; DS7 ~ 07, 07~ Os, etc.
Hold

MR

Asynchronous Master Reset Input (Active LOW)

H

H

L

./
./

OE1,OE2

3-State Output Enable Inputs (Active LOW)

H

L

L

X

1/0~1/07

Parallel Data Inputs or 3-State Parallel Outputs

00,07

Serial Outputs
2561 tbl05

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VrERM(2) Terminal Voltage
with Respect
toGND
VrERM(3) Terminal Voltage
with Respect
toGND

NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
. / = LOW-to-HIGH clock transition

CAPACITANCE

Commercial

Military

Unit·

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

TA

Operating
Temperature

o to +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TsrG

Storage
Temperature

-55 to +125

-65 to + 150

°C

Pr

Power Dissipation

lOUT

DC Output Current

0.5
120

0.5
120

rnA

Symbol

(TA

2561 tbl OG

= +25°C, f = 1.0MHz)

Parameter(l)

CIN

Input Capacitance

Cvo

1/0 Capacitance

Conditions

= OV
Your = OV

VIN

Typ_ Max.

Unit

6

10

pF

8

12

pF

NOTE:
2561 tbl 02
1. This parameter is guaranteed by characterization data and not tested.

W

NOTES:
2561 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability. No terminal voltage may
exceed Vcc by +0.5 unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Outputs and 1/0 terminals only.

6.43

2

II

IDT54174FCT299/A
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V
Commercial: TA = O°C to +70°C, VCC = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc

= 5.0V ± 10%
Min.

Typ.(2)

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

VIL

Input LOW Level

Guaranteed Logic LOW Level

IIH

Input HIGH Current

Vcc = Max.

-

_5(4)

-

-15(4)

Symbol

IlL

Test Conditions(1)

Parameter

(Except I/O Pins)

VI

= 2.7V

-

Input LOW Current

VI = 0.5V

-

VI

-

VI =Vcc

(Except I/O Pins)
IIH

Input HIGH Current

Vcc = Max.

(I/O Pins Only)
IlL

=GND

VI = Vcc
VI

= 2.7V

Input LOW Current

VI = 0.5V

(I/O Pins Only)

VI = GND

VIK

Clamp Diode Voltage

Vee = Min., IN = -18mA

los

Short Circuit Current

Vee = MaxP), Vo = GND

VOH

Output HIGH Voltage

Vee = 3V, VIN = VLC or VHC, IOH = -32~A

VOL

Output LOW Voltage

-60

Max.

V

5
5(4)

~A

-5

-

-15

-0.7

-1.2

V

-120

-

mA

VCC
Vcc

IOH = -12mA MIL.

2.4

4.3

IOH = -15mA COM'L.

2.4

4.3

-

GND
GND

VLC
VLC(4)

0.3

0.5

0.3

0.5

VIN = VIH or VIL

Vee = 3V, VIN = VLC or VHC, IOL = 300~A
Vee = Min.

IOL = 300~A

VIN = VIH or VIL

IOL = 32mA MIL.

-

IOL = 48mA COM'L.

-

~A

15
15(4)

VHC

IOH = -300~A

V

-

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

6.43

V

0.8

VHC

Vee = Min.

Unit

-

V

2561 tbl 05

3

IDT54174FCT299/A
FAST CMOS a-INPUT UNIVERSAL SHIFT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0 2V· VHC = VCC - 0 2V
Typ.(2)

Max.

Unit

Icc

Quiescent Power Supply
Current

Vee = Max.
VIN ~ VHC; VIN ~ VLC

-

0.2

1.5

mA

L'1lcc

Quiescent Power Supply
Current TTL Inputs HIGH

Vee = Max.
VIN = 3.4V(3)

-

0.5

2.0

mA

ICCD

Dynamic Power Supply
Current(4)

Vee = Max.
Outputs Open
OE1 = OE2 = GND
MR = VCC
So = S1 = VCC
DSo = DS1 = GND
One Input Toggling

Symbol

Test Condltions(1)

Parameter

Min.

VIN ~ VHC
VIN ~ VLC

mA/MHz

-

0.15

0.25

-

1.7

4.0

-

2.2

6.0

-

4.0

7.8(5)

-

6.2

16.8(5)

50% Duty Cycle
Ic

Total Power Supply
Current(6)

Vee = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
OE1 = OE2 = GND
MR = Vcc
So = S1 = Vcc
DSo = DS7 = GND
One Bit Toggling
at fi = 5MHz
50% Duty Cycle

VIN~ VHC
VIN ~ VLC
(FCT)

Vcc = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
OE1 = OE2 = GND
MR = Vcc
So = S1 = Vcc
DSo = DS7 = GND
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle

VIN ~ VHC
VIN ~ VLC
(FCT)

VIN =3.4V
VIN =GND

VIN =3.4V
VIN =GND

mA

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = S.OV. +2SoC ambient.
3. Per TIL driven input (VIN = 3.4V): all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fiNi)
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.43

I
25611b106

4

IDT54174FCT299! A
FAST CMOS a·INPUT UNIVERSAL SHIFT REGISTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT299A

IDT54174FCT299
Com'l.
Symbol

Parameter

tPLH
tPHL

Propagation Delay
CPto 00 or07

tPLH
tPHL

Condltlon(1)
CL
RL

= 50pF
= 500n

Mln.l2) Max.

MIl.
Mln.(2) Max.

Com'l.
Mln.(2)

Mil.

Max. Min.(2) Max.
7.2
2.0
9.5

Unit

2.0

10.0

2.0

14.0

2.0

Propagation Delay
CP to lIOn

2.0

12.0

2.0

12.0

2.0

7.2

2.0

9.5

ns

tPHL

Propagation Delay
MRto Qo or 07

2.0

10.0

2.0

10.5

2.0

7.2

2.0

9.5

ns

tPHL

Propagation Delay
MR to lIOn

2.0

15.0

2.0

15.0

2.0

8.7

2.0

11.5

ns

tPZH
tPZL

Output Enable Time
OEn to lIOn

1.5

11.0

1.5

15.0

1.5

6.5

1.5

7.5

ns

tPHZ
tPLZ

Output Disable Time
OEn to lIOn

1.5

7.0

1.5

9.0

1.5

5.5

1.5

6.5

ns

tsu

Set-up Time HIGH or LOW
Soor S1 to CP

7.5

-

7.5

-

3.5

-

4.0

-

ns

tH

Hold Time HIGH or LOW
SoorS1 to CP

1.0

-

1.0

-

1.0

-

1.0

-

ns

tsu

Set-up Time HIGH or LOW
lIOn, DSo or DS7 to CP

5.5

-

5.5

-

4.0

-

4.5

-

ns

tH

Hold Time HIGH or LOW
liOn, DSo or DS7 to CP

1.5

-

1.5

-

1.5

-

1.5

-

ns

tw

CP Pulse Width HIGH or LOW

7.0

-

6.0

7.0

7.0

-

5.0

MR Pulse Width LOW

5.0

-

6.0

Recovery Time MR to CP

7.0

7.0

-

5.0

-

6.0

-

ns

tREM

-

7.0

tw

NOTES:

ns

ns

ns
2561 1bl07

1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

6.43

5

IDT54n4FCT299/A
FAST CMOS a·INPUT UNIVERSAL SHIFT REGISTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

2561
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

PULSE WIDTH

-= nv

j

---..-.___ -

OV

tsu-'+--~

TIMING
INPUT _ _ _ _ _ _,

- 3V
----l-_- - - 1.5V
,_-1-_
_-_

lOW-HIG~Ji1~

- 3V
- - t - - - - - - 1.5V

HIGH-lOW-HIGH

-

OV

ASYNCHRONOUS CONTROL
PRESET - - - -.....
CLEAR
ETC.

-

=t-

tbl08

~ 15V
tw

_ _ 1.5V

PULSE

OV

SYNCHRONOUS CONTROL
CLOCK

:~~~~~ ~tsu
vvY I

- 3V

-1.5V
---..-.--- - OV

ETC.

PROPAGATION DELAY

I

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

,---~-----3V

SAME PHASE
INPUT TRANSITION

)0-'-'

_--_.+--OUTPUT

-+----- OV
3.5V

VOH

--1.5V

VOL

VOL
VOH

OPPOSITE PHASE
INPUT TRANSITION

SWITCH
OPEN

OV

' - - - - . 1 - - - - OV

NOTES
2561 drw04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate::;; 1.0 MHz; Zo::;; 50Q; tF::;; 2.5ns;
tR::;; 2.5n5.

6.43

6

IDT54f74FCT299/A
FAST CMOS a-INPUT UNIVERSAL SHIFT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XX

-------Temperature
Range

FCT

x

X

x

Device Type

Package

Process

-------

~~Iank
L---______________- - j

P
D
SO
L
E

I 299
L-----------------------------l1
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~I

299A

54

I 74

6.43

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
8-lnput Universal Shift Register
Fast 8-lnput Universal Shift Register
-55°C to +125°C
O°C to +70°C

2561 drw 03

7

t;)

FAST CMOS OCTAL
TRANSPARENT LATCHES

I DT5417 4 FCT373/AlC
I DT5417 4FCT533/ AlC
I DT5417 4FCT573/ AlC

Integrated Device Technology, Inc.

FEATURES

DESCRIPTION

• IDT54/74FCT373/533/573 equivalent to FASTTM speed
and drive
• IDT54/74FCT373A/533A/573A up to 30% faster than
FASTTM
• Equivalent to FASTTM output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1 mW typo static)
• Octal transparent latch with 3-state output control
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT373/NC, IDT54/74FCT5331NC and
IDT54/74FCT5731NC are octal transparent latches built
using advanced CEMOSTM, a dual metal CMOS technology.
These octal latches have 3-state outputs and are intended for
bus oriented applications. The flip-flops appear transparent to
the data when Latch Enable (LE) is HIGH. When LE is LOW,
the data that meets the set-up time is latched. Data appears
on the bus when the Output Enable (0 E) is LOW. When OE
is HIGH, the bus output is in the high impedance state.

FUNCTIONAL BLOCK DIAGRAMS
IDT54/74FCT373 AND IDT54174FCT573

I
I

2602

cnv· 01

IDT54/74FCT533

CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of Fairchild Semiconductor Co.

2602 cnv· 02

MILITARY AND COMMERCIAL TEMPERATURE RANGES
<01990 Integrated Device Technology. Inc.

JUNE 1990

6.44

DSC-46241-

1

IDT54174FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
IOT54/74FCT373
INOEX

Vee

OE

07

00
00
01

3

18

07

4

01

:] 4

5

P20-1 17
020-1 16
S020-2 15

06

01
02

06

01

:] 5
:] 6

7

13

05
05
04

02

02
03

02
03

12

04

:J 7
:J 8

11

LE

6

&

E20-1

8
9
10

03
GNO

14

o0 ,...
>0

8 8 I~
••
L-I

I
I
......

3

2

I
,

,

"
'" ..............

U 20 19
1

18[:

07

17[: 06
16[: 06

L20-2

15[: 05
14[: 05
9 10 11 12 13
r-rr-lr-lr-rr-:"!
I

II

II

0

M

Oz

DIP/SOIC/CERPACK
TOP VIEW

I

I '"

v
0

v

W

o

-I

(!)

LCC
TOP VIEW

IOT54/74FCT573

00
3

03

5

4

I

04
05
06

6

05

7

06

8

05
06

9
10

07
LE

&

E20-1

02

03
04

04

II

,;

8

>0
;,

II

I

32U2019

01
02

P20-1
020-1
S020-2

0

~

2) oo

00

01
02

07
GNO

INOEX

Vee

OE

03

1

]4
5

18[: 01

:1

17[: 02

:J

16[: 03
15[: 04

L20-2

6
:] 7

14[: 05

:] 8
9 10 11 12 13

nnnnn
,...

w

,... 0

<0

00

°Z-l
(!)

DIP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW

IOT54/74FCT533

00
00

INOEX

Vee

OE

01

4

01

5

I

07

P20-1 17
020-1 16
S020-2 15

06

01

:] 4

06

01

:] 5

05

02
02
03

:J 7
:J 8

6

02

7

03

8

13

04

0'3
GNO

9

12

04

10

11

LE

&

E20-1

14

II

3

05

I'

2

:] 6

0

go

10

...... L-I ,

18

0'2

w

o0

(57

2
3

U

,

"
'" ..............

20 19
1
18[:
17[:

07
06

16[:

56

L20-2

15[: 05
14[: 05
9 10 11 12 13
r-r
I

r-I r-I r-r r-1
II II II I I
I

10

DIP/SOIC/CERPACK
TOP VIEW

~ ~
(!)

0 0

LCe
TOP VIEW
6.44

2602 cnv· 03-{)8

2

IDT54n4FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE (FCT533)(1)

FUNCTION TABLE (FCT373 and FCT573)(1)

Inputs

Outputs

Inputs

ON

LE

OE

OutQuts
ON

ON

LE

OE

ON

H

H

L

L

H

H

L

H

L

H

L

H

L

H

L

L

X

X

H

Z

X

X

H

Z

NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = HIGH Impedance

NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = HIGH Impedance

260211>105

260211>106

PIN DESCRIPTION
Pin Names
ON

Description
Data Inputs

LE

Latch Enable Input (Active HIGH)

OE

Output Enable Input (Active LOW)

ON

3-State Outputs

ON

Complementary 3-State Outputs
260211>107

ABSOLUTE MAXIMUM RATINGS(1)

CAPACITANCE (TA= +25°C, f = 1.0MHz)

Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
TA
Operating
Temperature

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

Oto +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

Pr

Power Dissipation

0.5

0,5

W

lOUT

DC Output
Current

120

120

rnA

Conditions

T~

Max.

Unit

CIN

Input
Capacitance

VIN = OV

6

10

pF

COUT

Output
Capacitance

Vour= OV

8

12

pF

Symbol

Parameter

NOTE:
260211>102
1. This parameter is measured at characterization but not tested.

NOTES:
260211>101
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 1/0 terminals only.

6.44

3

I

I DT54174FCT373/533/5731A/C
FAST CMOS OCTAL TRANSPARENT LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C, vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc = 5.0V ± 10%
Symbol

Test Conditlons(1)

Parameter

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

VIL

Input LOW Level

Guaranteed Logic LOW Level

IIH

Input HIGH Current

Vec = Max.

ilL

Input LOW Current

10ZH

Off State (High Impedance)
Output Current

10ZL

V

5
5(4)

Il A

VI = 2.7V

-

VI = 0.5V

-

VI = GND

-

Vo= Vcc

-

Vo= 2.7V

-

Vo= 0.5V

-

Vo=GND

-

-120

Vcc = 3V, VIN = VLC or VHC, 10H = -321lA

VHC

Vcc

Vcc = Min.

VHC

Vcc

10H = -12mA MIL.

2.4

4.3

10H = -15mA COM'L.

2.4

los

Short Circuit Current

Vec = Max.(3), Vo = GND

VOH

Output HIGH Voltage

10H = -3OOIlA

VIN = VIH or VIL

Output LOW Voltage

0.8

-

Vcc = Min., IN = -18mA

V

-5(4)
-5
10

IlA

10(4)
-10(4)

4.3

-10
-1.2

-

-

GND

VLC

Vcc = Min.

10L = 300llA

-

GND

VLC(4)

VIN = VIH or VIL

10L = 32mA MIL.

-

0.3

0.5

10L = 48mA COM'L.

-

0.3

0.5

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. D.uration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

V
mA
V

-

Vcc = 3V, VIN = VLC or VHC, 10L = 300llA

6.44

Unit

-

-60

Clamp Diode Voltage

Max.

-

-0.7

VIK

VOL

-

Typ.(2)

-

VI = Vec

Vcc = Max.

Min.
2.0

V

2602 tbl 03

4

IDT54174FCT373f533f573fAfC
FAST CMOS OCTAL TRANSPARENT LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC

= O.2V; VHC = VCC -

Symbol
Icc
~Iee

IceD

Ie

O.2V

Parameter
Quiescent PowerSupply Current

Typ.(2)

Max.

Unit

-

0.2

1.5

mA

-

0.5

2.0

mA

VIN ~ VHe
VIN ~ VLC

-

0.15

0.25

Vce = Max.
Outputs Open
f i = 10MHz

VIN ~ VHC
VIN ~ VLe
(FCT)

-

1.7

4.0

50% Duty Cycle
OE=GND
LE = Vee
One Bit Toggling

VIN =3.4V
VIN = GND

-

2.0

5.0

Vee = Max.
Outputs Open
f i = 2.5MHz

VIN ~ VHe
VIN ~ VLC
(FCT)

-

3.2

6.5(5)

50% Duty Cycle
OE = GND
LE = Vee
Eight Bits Toggling

VIN = 3.4V
VIN = GND

-

5.2

14.5(5)

Test Conditions(1)
Vee = Max.
VIN ~ VHe; VIN ~ VLC

Quiescent Power Supply Current
TTL Inputs HIGH

Vee = Max.
VIN =.3.4V(3)

Dynamic Power Supply
Current(4)

Vee = Max.
Outputs Open
OE = GND
One Input Toggling
50% Duty Cycle

Total Power Supply Current(6)

Min.

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = S.OV, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + I INPUTS + (DYNAMIC
Ic = Icc + t.lcc DHNT + ICCD (fcPf2 + fiNi)
Icc = Quiescent Current
t.lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
Iceo = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at Ii
All currents are in milliamps and all frequencies are in megahertz.

6.44

mAl
MHz

mA

26021b104

I

IDT54174FCT373/533/573fAfC
FAST CMOS OCTAL TRANSPARENT LATCHES

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT373/A/C/FCT573/A1C
FCT373f573
Com'l.
Symbol

Parameter

tPLH
tPHL

Propagation Delay
DN toON

tPLH
tPHL

Propagation Delay
LE to ON

tPZH
tPZL

Output Enable Time

tPHZ
tPLZ

Output Disable Time

tsu

Set-up Time HIGH
or LOW, DN to LE
Hold Time HIGH
or LOW, DN to LE
LE Pulse Width HIGH

tH
tw

Conditions(')

CL = 50pF
RL = 50 on

FCT373Af573A

Mil.

Com'l.

FCT373Cf573C

Mil.

Com'l.

Mil.

Min.12 Max. Min.12 Max. Min.(2 Max. MinJ2 Max. Min.12 Max. Min.12 Max.

Unit

1.5

8.0

1.5

8.5

1.5

5.2

1.5

5.6

1.5

4.2

1.5

5.1

ns

2.0

13.0

2.0

15.0

2.0

8.5

2.0

9.8

2.0

5.5

2.0

8.0

ns

1.5

12.0

1.5

13.5

1.5

6.5

1.5

7.5

1.5

5.5

1.5

6.3

ns

1.5

7.5

1.5

10.0

1.5

5.5

1.5

6.5

1.5

5.0

1.5

5.9

ns

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

ns

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

ns

6.0

-

6.0

-

5.0

-

6.0

-

5.0

-

6.0

-

ns
2602 tbl 08

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT533/A/C
FCT533
Com'l.
Symbol

Parameter

tPLH
tPHL

Propagation Delay
DNto ON

tPLH
tPHL

Propagation Delay
LE to ON

tPZH
tPZL

Output Enable Time

tPHZ
tPLZ

Output Disable Time

tsu

Conditions(')

= 50pF
RL = 50 on
CL

FCT533C

FCT533A
Com'l.

Mil.

Mil.

Mil.

Com'l.

Min.12 Max. Min.(2 Max: MinJ2 Max. Min.l2 Max" Min.12 Max. Min.(2 Max.

Unit

1.5

10.0

1.5

12.0

1.5

5.2

1.5

.5.6

1.5

4.7

1.5

5.1

ns

2.0

13.0

2.0

14.0

2.0

8.5

2.0

9.8

2.0

6.9

2.0

8.0

ns

1.5

11.0

1.5

12.5

1.5

6.5

1.5

7.5

1.5

5.5

1.5

6.3

ns

1.5

7.0

1.5

8.5

1.5

5.5

1.5

6.5

1.5

5.0

1.5

5.9

ns

Set-up Time HIGH
or LOW, DN to LE

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

ns

tH

Hold Time HIGH
or LOW, DN to LE

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

ns

tw

LE Pulse Width HIGH

6.0

-

6.0

-

5.0

-

6.0

-

5.0

-

6.0

-

NOTES:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

ns
2602 tbl 09

6.44

6

IDT54174FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
o--e 7.0V

Vee

500n

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2537 Ibl 08
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

J

~..-..

PULSE WIDTH

-= ~~V

_ _ _ _ OV

tsu~-+--~

TIMING
INPUT _ _ _ _ _ _J

3V

LOW-HIG~i~~

-

3V

HIGH-LaW-HIGH

-

OV

-

3V

_

6~V

ASYNCHRONOUS CONTROL
PRESET - - - - ,
CLEAR
ETC. - - - - "
SYNCHRONOUS CONTROL
CLOCK

- - f - - - - - - 1.SV

:~~~~
vvJr J
ETC. ~tsu

~~~~

=t_

~ I£V
1W

__

1.SV

PULSE

-1.5V
-OV

PROPAGATION DELAY

I

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

SAME PHASE
INPUT TRANSITION
3.SV
OUTPUT

VOL

OUTPUT

OPPOSITE PHASE
INPUT TRANSITION

VOH

SWITCH

NORM~~~ OPEN
' - -_ _oJ - - - -

OV

OV

NOTES
2537 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-H I GH.
2. Pulse Generator for All Pulses: Rate s; 1.0 MHz; Zo s;
tF s; 2.Sns;
tR s; 2.5ns.

son;

6.44

7

IDT54174FCT373/533/5731 A/C
FAST CMOS OCTAL TRANSPARENT LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XX

"re-m-p-......R....a-n-g-e

FCT

XXXX
..,.D~e":":"vl'-c-:-e....
T':":'"yp:"':e=-

x

x

Package

Process

y~lank
~

____________

P
D
~SO

L

E
373
573
533
373A
~--------------------~573A

533A
373C
573C
533C
54

~------------------------------------~74

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Non-Inverting Octal Transparent Latch
Non-Inverting Octal Transparent Latch
Inverting Octal Transparent Latch
Fast Non-Inverting Octal Transparent Latch
Fast Non-Inverting Octal Transparent Latch
Fast Inverting Octal Transparent Latch
Super Fast Non-Inverting Octal Transparent Latch
Super Fast Non-Inverting Octal Transparent Latch
Super Fast Inverting Octal Transparent Latch
-55°C to + 125°C
O°C to +70°C
2602 cnv· 14

6.44

8

t;)

I DT54/7 4FCT3741 A/C
IDT54/74FCT534/A/C
IDT54/74FCT574/A/C

FAST CMOS OCTAL D
REGISTERS (3-STATE)

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• IDT54/74FCT374/534/574 equivalent to FASFM speed
and drive
• IDT54/74FCT374A/534A/574A up to 30% faster than
FASpM
• IDT54/74FCT374C/534C/574C up to 50% faster than
FASTTM
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1 mW typo static)
• Edge triggered masterlslave, D-type flip-flops
• Buffered common clock and buffered common threestate control
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Meets or exceeds JEDEC Standard 18 specifications

The IDT54/74FCT3741NC, IDT54/74FCT534/A/C and
I DT54/74FCT574/A/C are 8-bit registers built using advanced
CEMOSTM, a dual metal CMOS technology. These registers
consist of eight D-type flip-flops with a buffered common clock
and buffered 3-state output control. When the output enable
(OE) is LOW, the eight outputs are enabled. When the OE
input is HIGH, the outputs are in the high-impedance state.
Input data meeting the set-up and hold time requirements
of the D inputs is transferred to the 0 outputs on the LOW-toHIGH transition of the clock input.
The I DT54/74 FCT374/A/C and IDT54/74FCT574/A/C have
non-inverting outputs with respect to the data at the D inputs.
The IDT54/74FCT534/A/C have inverting outputs.

FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT374 AND IDT54/74FCT574

00

01

02

03

04

05

06

07
2603 cnv' 01

FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT534
00

01

02

03

04

05

06

07

2603 cnv' 02

CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of Fairchild Semiconductor. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
~1

990 Integrated Device Technology, Inc.

6.45

JUNE 1990
DSC-4622/-

II

IDT54f74FCT374/534/574/A/C
FAST CMOS OCTAL 0 REGISTERS (3-STATE)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
IDT54/74FCT374
INOEX

Vee

OE

19

07

3

18

07

4
5
6

P20-1 17
020-1 16
5020-2 15

06
Os
05

00
00
01

01
02
02
03

I

&

7

E20-1

8

9
10

03
GNO

I~ g 0

3
01

:] 4

01
02

:] 5

02
03

:J 7

:...J 20

2

1

:] 6

19
18[:

07

17[:

06

L20-2

16[: 06
15[: 05
14[: 05

:J 8

04

I,
II
I
I L..-...I L--I

I ",
I

L-I L-I

05
04

14
13
12
11

()

o8

910111213
1"""'11"""'11"""'11"""'1,.......,

CP

I

2603 cnv· 03

I

'"

"

I

I

a. ..,.

0

M

I

2603 cnv· 04

..,.

O ZOOO

DIP/50lC/CERPACK
TOP VIEW

CJ

Lee
TOP VIEW

IDT54/74FCT574
INOEX

Vee

OE
00
01
02

2
3

19
18

4

P20-1 17
020-1 16
5020-2 15

03

5

04

6

&

05

7
8

06

E20-1

9
10

07
GNO

00

I

14
13

05
06

12
11

07
CP

I

I

I I' "

I

I

32:...J21

01
02
03
04

02

:] 4

03

:] 5

04
05
06

:] 7

:J 6

01
[: 02

1

1 [:

L20-

[:

03

[: 04
1 [: 05

:] 8

9 1 1 1 1
nroronr1
I I I I I I
I I
I

I

2603 cnv· 05

a.

... 0

o

...

2603 cnv· 06

cD

ZOO 0

CJ

DIP/50lC/CERPACK
TOP VIEW

LCC
TOP VIEW

IDT54/74FCT534
INOEX

DE

00

19

2

00

3

18

01

4
5
6

P20-1 17
020-1 16
5020-2 15

01
02
02

&

7

03

8

03

9
10

GNO

E20-1

Vee
'07

I

'06

12

'04

11

CP

I

01

:] 4

0"1

:] 5

2

I

I,

02
03

04

II

I

'L.-oIL--I
I

I

20 19
18[: 07

'T

17[: 06
L20-2

02 :] 6

05
05

I

3

07
06

14
13

I

a....-JI--I'

:J 7
:J 8

16[: 06
15[: 05
14[: 05

910111213
1"""'11"""'11"""'11"""'1 ,.......,
I

2603 cnv· 07

I

I

(3 ~
CJ

I

I

I

~

I

I

0

I

I

2)

2603 cnv· 08

Lce

DIP/50lC/CERPACK
TOP VIEW

TOP VIEW

6.45

2

IDT54n4FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION
Pin Names
ON
CP

Description

o flip-flop data inputs.

ON

Clock Pulse for the register. Enters data on
LOW-to-HIGH transition.
3-state outputs, (true).

ON

3-state outputs, (inverted).

OE

Active LOW 3-state Output Enable input.
2603tbl06

FUNCTION TABLE(1)
FCT534
Inputs
Function
Hi-Z
Load Register

CP

ON

ON

ON

ON

ON

L
H

X
X

.I
.I
.I
.I

L
H
L
H

Z
Z
H
L
Z
Z

NC
NC
L
H
L
H

Z
Z
L
H
Z
Z

NC
NC
H
L
H

L
2603tbl05

Z = HIGH Impedance
NC = No Change
.I = LOW-to-HIGH transition

CAPACITANCE

Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
TA
Operating
Temperature

Commercial
-0.5 to +7.0

Military
-0.5 to +7.0

Unit
V

-0.5 to Vee

-0.5 to Vee

V

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
-55 to +125
Temperature
Power Dissipation
0.5

-65 to +150

°C

DC Output
Current

FCT3741574
Outputs
Internal

H
H
L
L
H
H

ABSOLUTE MAXIMUM RATINGS(1)

lOUT

Internal

OE

NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care

PT

Outputs

120

0.5

W

120

mA

(TA

Parameter(1)
Symbol
CIN
lriput
'Capacitance
COUT

Output
Capacitance

= +25°C, f = 1.0MHz)
Conditions
VIN = OV

Typ.
6

Max.
10

Unit
pF

VOUT= OV

8

12

pF

NOTE:
2603 tbl 02
1. This parameter is measured at characterization but not tested.

NOTES:
2603 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and I/O terminals only.

6.45

3

II

IDT54174FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE)

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C, VCC = 5.0V ± 5%; Military: TA = -55°C to + 125°C, Vcc = 5.0V
Symbol

Test Condltlons(1)

± 10%

Min.
2.0

VIH

Parameter
Input HIGH Level

Guaranteed Logic HIGH Level

Vil

Input LOW Level

Guaranteed Logic LOW Level

-

IIH

Input HIGH Current

Vee = Max.

-

IlL

Input LOW Current

VI = Vee
VI = 2.7V

10ZH

Off State (High Impedance)
Output Current

lozl
VIK

Clamp Diode Voltage

Vee = Min., IN = -18mA

los

Short Circuit Current

Vee = Max.(3), Vo= GND

VOH

Output HIGH Voltage

Output LOW Voltage

-5

V

5
5(4)

Il A

-

Vo= Vee

-

-

Vo= 2.7V

-

-

10
10(4)

Vo= 0.5V

-

-

-10(4)

Vo=GND

-

-

-

V

0.8

Il A

-10
-1.2

-0.7

V

-

mA

Vee

-

V

Vee

-

-120

Vee = 3V, VIN = Vle or VHe, 10H = -321lA

VHe

Vee = Min.

10H = -3OOIlA

VHe

10H = -12mA MIL.

2.4

4.3

-

10H = -15mA COM'L.

2.4

4.3

-

Vee = 3V, VIN = VLe or VHe, 10l = 300llA

-

GND

VLe

Vee = Min.

10l = 300llA

-

GND

Vlc!4)

10l = 32mA MIL.

-

0.3

0.5

10l = 48mA COM'L.

-

0.3

0.5

VIN = VIH or Vil
NOTES:
1. For conditions
2. Typical values
3. Not more than
4. This parameter

-5(4)

-

Unit

-

-60

VIN = VIH or Vil
VOL

Max.

-

VI= GND

VI = 0.5V

Vee = Max.

Tvp.(2)

V

2603 tbl 03

shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
are at Vee = 5.0V, +25°C ambient and maximum loading.
one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
is guaranteed but not tested.

6.45

4

IDT54174FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC

= a 2V· VHC = VCC - a 2V

Symbol
Icc
~Icc

ICCD

Ic

Typ.(2)

Max.

Unit

-

0.2

1.5

rnA

-

0.5

2.0

rnA

VIN ~ VHC
VIN S VLC

-

0.15

0.25

VCC = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle

VIN ~ VHC
VIN S VLC
(FCT)

-

1.7

4.0

OE = GND
f i = 5MHz
50% Duty Cycle
One Bit Toggling

VIN = 3.4V
VIN = GND

-

2.2

6.0

Vcc = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle

VIN~ VHC
VIN S VLC
(FCT)

-

4.0

7.8(5)

OE = GND
Eight Bits Toggling
f i = 2.5MHz
50% Duty Cycle

VIN = 3.4V
VIN= GND

-

6.2

16.8(5)

Test Condltlons(1)

Parameter
Quiescent Power Supply Current

Vcc = Max.
VIN ~ VHC; VIN s VLC

Quiescent Power Supply Current
TTL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

Dynamic Power Supply
Current(4)

Vcc = Max.
Outputs Open
OE = GND
One Input Toggling
50% Duty Cycle

Total Power Supply Current(6)

Min.

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = S.OV, +25°C ambient.
3. Per TIL driven input (V IN = 3.4V); all other inputs at Vccor GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. lc = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + 61cc DHNT + ICCD (fcp/2 + fiNi)
Icc = Quiescent Current
6lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni '"' Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.45

rnA!
MHz

rnA

2603tbl04

•

5

IDT54174FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE)

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT374/534/574
Com'l.
Symbol

Parameter

tPLH
tPHL

Propagation Delay
CPto ON(3)

tPZH
tPZL

Output Enable Time

tPHZ
tPLZ

Output Disable Time

tsu

Set-up Time HIGH
or LOW, ON to CP
Hold Time HIGH
or LOW, ON to CP

tH
tw

CP Pulse Width
HIGH or LOW

Mil.

FCT374A1534A1574A

FCT374C/534C/574C

Com'l.

Com'l.

Mil.

Mil.

Conditions(1) Min.(2) Max. Mln.l2) Max. Mln.(2) Max. Mln.(2) Max. Mln.l2) Max. Min.(2) Max.

= 50pF
RL = 500n
Cl

Unit

2.0

10.0

2.0

11.0

2.0

6.5

2.0

7.2

2.0

5.2

2.0

6.2

ns

1.5

12.5

1.5

14.0,

1.5

6.5

1.5

7.5

1.5

5.5

1.5

6.2

ns

1.5

8.0

1.5

8.0

1.5

5.5

1.5

6.5

1.5

5.0

1.5

5.7

ns

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

2.0

-

ns

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

ns

7.0

-

7.0

-

5.0

-

6.0

-

5.0

-

6.0

-

NOTES:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. ON for FCT374 and FCT574, ON for FCT534.

ns
2603tbl07

6.45

6

IDTS4174FCT374/S34/S74/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE)

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vee

SWITCH POSITION
0---.

7.0V

soon

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2603 tbl 08
CL = Load capacitance: indudes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

xzt

-= ~~V

1
Isu --I'!4--~

TIMING
INPUT

PULSE WIDTH

""'---.....K~ -

OV

LOWHIG~UL~~

-

3V
- - 1 - - - - - - 1.5V

-

OV

ASYNCHRONOUS CONTROL
PRESET - - - -......
CLEAR
ETC. - - - - - '

-

3V
1.SV

-

OV

--+------

=t-

HIGH-LOW-HIGH

~ 15V
Iw

--1.5V

PULSE

SYNCHRONOUS CONTROL

CLOCK:~~~~~ vvY
j
~ISU
ETC.

""'-..x.....K~

- 3V
-1.5V

-

PROPAGATION DELAY

OV

ENABLE AND DISABLE TIMES
ENABLE

DISABLE
3V

3V
SAME PHASE
INPUT TRANSITION

OV
OV
3.5V

OUTPUT

VOL
VOL
VOH
SWITCH
OPEN

OPPOSITE PHASE
INPUT TRANSITION

OV
OV

NOTES
2603 drw 15
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate $ 1.0 MHz; Zo $ SOD.; tF $ 2.Sns;
tR $ 2.Sns.

6.45

7

IDT54174FCT374/534/574/A/C

FAST CMOS OCTAL D REGISTERS (3-STATE)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xx
Temp. Range

FCT

xxxx

x

x

Device Type

Package

Process

y~lank
P
~

____________

D
~SO

L

E
374
574
534
374A
.......................................................~574A
534A
374C
574C
534C

~

54

~""'------------""'------------------~74

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Non-Inverting Octal D Register
Non-Inverting Octal D Register
Inverting Octal D Register
Fast Non-Inverting Octal D Register
Fast Non-Inverting Octal D Register
Fast Inverting Octal D Register
Super Fast Non-Inverting Octal D Register
Super Fast Non-Inverting Octal 0 Register
Super Fast Inverting Octal 0 Register
-55°C to + 125°C
QOCto +70°C
2603 cnv· 14

6.45

8

(;)®

IDT54/74FCT377
I DT54/74FCT377 A
IDT54/74FCT377C

FAST CMOS
OCTAL 0 FLIP-FLOP
WITH CLOCK ENABLE

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

•
•
•
•

The IOT54n4FCT3771NC is an octal D flip-flop built using
advanced CEMOSTM, a dual metal CMOS technology. The
IOT54/74FCT3771NC have eight edge-triggered, Ootype
flip-flops with individual 0 inputs and 0 outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously
when the Clock Enable (CE) is LOW. The register is fully
edge-triggered. The state of each 0 input, one set-up time
before the LOW-to-HIGH clock transition, is transferred to the
corresponding flip-flop's 0 output. The CE input must be
stable only one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.

•
•
•
•
•
•
•

IOT54/74FCT377 equivalent to FASTTM speed
IDT54n4FCT377A 25% faster than FASTTM
IDT54n4FCT377C 40% faster than FASTTM
Equivalent to FASTTM output drive over full temperature
and voltage supply extremes
10L = 48mA (commercial) and 32mA (military)
IIH and IlL only 5~ max.
CMOS power levels (1 mW typo static)
CMOS output level compatible
Meets or exceeds JEOEC Standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STO-883, Class B

FUNCTIONAL BLOCK DIAGRAM
Do

01

02

03

06

05

04

07

II
I

00

01

02

04

03

06

05

07
2535 drw 02

PIN CONFIGURATIONS
INOEX
CE
00
00
01
01
02
02
03
03
GND

6
7

10

19
18
P20-1
17
020-1 16
8020-2
15
&
E20-1
14
13
12
11

Vee
07
07
06
06
05
05
04
04
CP

01
01
02
02
03

o

0IUJ 8 f"-

000>0
]
]
]
]
]

4
5
6
7
8

32: :2019
18
l'

17
L20-2 16
15
14
9 10 11 12 13

rlnrlrlrl

[
[
[
[
[

07
06
06
05
05
2535 drw 01

8°0..<1'<1'
ZoOO
~

DIP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
105

Outputs

CP

NOTE:
2535 11>1 06
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH
Clock Transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH Clock
transition
X = Immaterial
i = LOW-to-HIGH clock transition

ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

CAPACITANCE

(TA = +25°C, f = 1.0MHz)

Parameter(1)

Conditions

Max.

Unit

CIN

Input
Capacitance

VIN = OV

6

10

pF

COUT

Output
Capacitance

VOUT = OV

8

12

pF

Commercial

Military

Unit

Symbol

VTERM(2) Terminal Voltage
with Respect
toGNO

-0.5 to +7.0

-0.5 to +7.0

V

VTERM(3) Terminal Voltage
with Respect
toGND

-0.5 to Vee

-0.5 to Vee

V

Typ.

NOTE:
1. This parameter is guaranteed but not tested.

TA

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

rnA

25351b102

NOTE:
253511>101
1. Stresses greater than those listed under ABSOLUTE MAXI MU M RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
Vce by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 1/0 terminals only.

6.46

2

IDT54174FCT377/A1C
FAST CMOS OCTAL D FLlp·FLOP WITH CLOCK ENABLE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C, vcc = 5.0V ± 5%; Military: TA = ·55°C to +125°C, Vcc

= 5.0V ± 10%
Min.

Typ.(2)

VIH

input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

VIL

Input LOW Level

Guaranteed Logic LOW Level

V

Input HIGH Current

Vee = Max.

-

0.8

IIH

S
S(4)

~A

= 2.7V

-

IlL

Input LOW Current

O.SV

-

VIK

Clamp Diode Voltage

Vce = Min., IN = -18mA

los

Short Circuit Current

Vee = MaxP), Vo = GND

VOH

Output HIGH Voltage

Vee = 3V, VIN = VLe or VHe, 10H = -32~A

Symbol

Test Conditions(1)

Parameter

VI =Vec
VI
VI
VI

VOL

Output LOW Voltage

=

=GND

-60

-0.7

VHC

Vee

10H =-300~A

VHC

Vee

VIN = VIH or VIL

10H = -12mA MIL.

2.4

4.3

10H = -1SmA COM'L.

2.4

Unit
V

_S(4)
-S
-1.2

V

-

-120

Vee = Min.

Vee = 3V, VIN = VLe or VHe, 10L = 300~A

Max.

4.3

-

GND

VLe

GND

VLd 4)

Vee = Min.

10L = 300~A

VIN = VIH or VIL

10L = 32mA MIL.

-

0.3

O.S

10L = 48mA COM'L.

-

0.3

O.S

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = S.OV, +25°C ambient and maximum loading
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

mA
V

V

25351b105

I

II

.~

6.46

3

I

IDT54174FCT377/A1C
FAST CMOS OCTAL D FLlp·FLOP WITH CLOCK ENABLE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPL V CHARACTERISTICS
VLC

= O.2V; VHC = VCC -

Symbol

O.2V
Test Condltlons(l)

Parameter

Max.

Unit

Quiescent Power Supply
Current

Vee = Max.
VIN ~ VHC; VIN $ VLC

-

0.2

1.5

rnA

~Icc

Quiescent Power Supply
Current TIL Inputs HIGH

Vee = Max.
VIN = 3.4V(3)

-

0.5

2.0

rnA

ICCD

Dynamic Power Supply
Current(4)

Vee = Max.
Outputs Open
CE = GND
One Input Toggling
50% Duty Cycle

VIN ~ VHC
VIN $ VLC

-

0.15

0.25

Total Power Supply
Current(6)

Vee = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
CE = GND
One Bit Toggling
at fi = 5MHz
50% Duty Cycle

VIN ~VHe
VIN $ VLC
(FCT)

-

1.7

4.0

VIN = 3.4V
VIN =GND

-

2.2

6.0

VCC = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
CE = GND
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle

VIN ~VHC
VIN $ VLC
(FCT)

-

4.0

7.8(5)

VIN = 3.4V
VIN = GND

-

6.2

16.8(5)

Ic

Min.

Typ.(2)

lee

mAl
MHz

rnA

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vee or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fiNi)
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

SAS

2535 till 07

4

IDT54f74FCT3nIAlC
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
1OT54/74FCT377
Symbol
tPLH
tPHL
tsu

tH

tsu

tH

tw

Parameter
Propagation Delay
CP to On
Set-up Time
HIGH or LOW
Onto CP
Hold Time
HiGH or LOW
Dn to CP
Set-up Time
HIGH or LOW
CE to CP
Hold Time
HIGH or LOW
CE to CP
Clock Pulse Width,
HIGH or LOW

IOT54/74FCT377A

CL
RL

= SOpF
= soon

2.0

13.0

Com'l.

IOT54/74FCT377C

Mil.
Condition(1) MlnP) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Unit
Com'l.

Mil.

2.0

1S.0

Com'l.

Mil.

2.0

7.2

2.0

8.3

2.0

S.2

2.0

S.S

ns

2.5

-

3.0

-

2.0

-

2.0

-

2.0

-

2.0

-

ns

2.0

-

2.S

-

1.S

-

1.S

-

1.5

-

1.S

-

ns

4.0

-

4.0

-

3.S

-

3.S

-

3.5

-

3.S

-

ns

1.S

-

1.S

-

1.5

-

1.S

-

1.5

-

1.5

-

ns

7.0

-

7.0

-

6.0

-

7.0

-

6.0

-

7.0

-

ns

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

2535 Ibl 07

I

6.46

5

IOT54174FCT377! AlC
FAST CMOS OCTAL D FLlp·FLOP WITH CLOCK ENABLE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vee

SWITCH POSITION
a---.7.0V

soon
Your
I-H:>+---.-~

D.U .T. H-o-t--.---.

SOpF

11

Rr

~CL

soon

Z&t

l
tsu ----of4--...;

TIMING
INPUT _ _ _ _ _ _J

~~:...JI~~

Switch
Closed

All Other Outputs

Open

DEFINITIONS:
2535 till 08
CL = Load capacitance: includes jig and probe capacitance.
Rr = Termination resistance: should be equal to Zour of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

Test
Open Drain
Disable Low
Enable Low

PULSE WIDTH

-= ~~V
-

OV

-

3V
V
6S

_

LOW-HIG~J~~

ASYNCHRONOUS CONTROL
PRESET - - - - - - - , ~-~-~----­ - 3V
- - + - - - - - - l.SV
CLEAR
- OV
ETC. - - - - - - - ,

HIGH-LOW-HIGH

=t-

~ 15V
Iw

--1.SV

PULSE

SYNCHRONOUS CONTROL
CLOCK

:~~~~ ~tsu
vvJr )
ETC.

PROPAGATION DELAY

-

3V

-1.SV
.......-----~ - OV

ENABLE AND DISABLE TIMES

SAME PHASE
INPUT TRANSITION

OUTPUT

OPPOSITE PHASE
INPUT TRANSITION

NOTES
25·35 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ son; tF S 2.Sns;
tR ~ 2.5ns.

6.46

6

IDT54f74FCT377IA1C
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XX

---Temperature
Range

FCT

X

X

X

Device
Type

Package

Process

~~Iank
P
'--------~

'--________________________________

~

B

E

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

377
377A
377C

Octal D Flii:>-Flop w/Clock Enable
Fast Octal D Flip-Flop w/Clock Enable
Super Fast Octal D Flip-Flop w/Clock Enable

54
74

-55°C to + 125°C
O°C to +70°C

D

SO

L

~--------------------~

Commercial
MIL-STD-883, Class

2535 drw 03

II

6.46

7

~®

IDT54/74FCT399
IDT54/74FCT399A

FAST CMOS QUAD
DUAL-PORT REGISTER

Integrated Devfce Technology, Inc.

FEATURES:

DESCRIPTION:

• IDT54/74FCT399 equivalent to FASFM speed
• IDT54/74FCT399A 30% faster than FASpM
• Equivalent to FASFM pinout/function and output drive
over full temperature and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1 mW typo static)
• TTL input and output level compatible
• Available in 16-pin DIP and SOIC, and 20-pin LCC
• Product avilable in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT399/A is a high-speed quad dual-port
register. The register selects four bits of data from either of two
sources (Ports) under control of a common Select input (S).
The selected data is transferred to a 4-bit output register
synchronous with the LOW-to-HIGH transition of the Clock
input (CP). The 4-bit D-type output register is fully edgetriggered. The Data inputs (lox, 11X) and Select input (S) must
be stable only one set-uptime prior to, and hold time after, the
LOW-to-HIGH transition of the Clock input for predictable
operation.

FUNCTIONAL BLOCK DIAGRAM
lOA - - - - - - - ,

s

a

OA

a

OB

a

ae

a

aD

11A -----1f----t-----1--I..---'

CP
lOB - - - - - - - t - - - l - r - " " " " ' \

11B -------+----1--1..---'

CP

loc

-------t-----1~

b--t---d

D

be - - - - - - - t - - - l - L - . J
CP
laD

--------+----1~

D
110 - - - - - - - - - - 1 . . - - - '
CP

cp--------~~-----~
2559 drw 01

CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of National Semioonductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1990 Integrated Device Technology. Inc.

6.47

JUNE 1990
DSC4616/-

1

IDT54174FCT399/A
FAST CMOS QUAD DUAL·PORT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
1

7

16
15
14
13
12
11
10

OA
IDA
11A
11B
lOB
OB

2

00
100
110
11C
loc
Oc

3
4
5
6

GND

8

9

CP

P16·1,
D16-1
S016-1
&
E16-1

uSo

«

INDEX

S

OCJ)z>O

VCC

L-J

L........I

3
IDA

] 4

11A

] 5

NC

] 6

11B

] 7

lOB

] 8

I

I

L......J

L..-..J

2 I I 20 19
L..J

1

L20-2

18 [

100

17[

110

16 [

NC

15 [

11C

14 [

loe

9 1011 12 13
2559 drw 02

IDOUQ.O

DIP/SOIC/CERPACK
TOP VIEW

O zzUO
<.9

Lce
TOP VIEW

FUNCTION TABLE(1)

PIN DESCRIPTION
Pin Names

Description

Inputs

Outputs

S

Common Select Input

S

10

h

a

CP

Clock Pulse Input (Active Rising Edge)

I

I

lOA -100

Data Inputs from Source 0

I

h

X
X

H

11A-11O

Data Inputs from Source 1

h

L

Register True Outputs

h

X
X

I

OA-OO

h

H

2559 tbl 03

NOTE:

1.

H
L

LOGIC SYMBOL

h

x

IDA 11A lOB 11S loe 11C 100 110

L

2559 tbl 04

HIGH Voltage Level
LOW Voltage Level
HIGH Voltage Level one set-up time prior to the LOW-to-HIGH
clock transition
LOW Voltage Level one set-up time prior to the LOW-to-HIGH
clock transition
Immaterial

I

S

CP
OA

Os

Oc

OD
2559 drw 03

6.47

2

IDT54f74FCT399! A
FAST CMOS QUAD DUAL-PORT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1}
Symbol

Rating

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Commercial

Military

Unit

VTERM(2) Terminal Voltage
with Respect
to GND

-0.5 to +7.0

-0.5 to +7.0

V

VTERM(3) Terminal Voltage
with Respect
to GND

-0.5 to Vcc

-0.5 to Vcc

V

Symbol

Parameter(1)

Conditions

Typ.

Max.

Unit

CIN

Input
Capacitance

VIN = OV

6

10

pF

COUT

Output
Capacitance

VOUT = OV

8

12

pF

NOTE:
25591b1 02
1. This parameter is measured at characterization but not tested.

TA

Operating
Temperature

o to +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

NOTE:
25591b101
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +O.5V unless otherwise noted.
2. Input and Vce terminals only.
3. Outputs and I/O terminals only.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc
Symbol

Test Conditions(l)

Parameter

= 5.0V ± 10%
Min.

Typ.(2)

Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

0.8

V

IIH

Input HIGH Current

Vcc

5
5(4)

Il A

IlL

Input LOW Current

-

= Max.

VI
VI
VI
VI

VIK

Clamp Diode Voltage

los

Short Circuit Current

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

= Min., IN = -18mA
Vcc = Max.(3), Vo = GND
Vec = 3V, VIN = VLC or VHC,
Vee = Min.
VIN = VIH or VIL

= Vcc
= 2.7V
= 0.5V
= GND

Vee

= 3V, VIN = VLC or
Vee = Min.
VIN = VIH or VIL
Vcc

VHC,

= -321lA
= - 3OOIlA
10H = -12mA MIL.
10H = -15mA COM'L.
10L = 300llA
10L = 300llA
10L = 32mA MIL.
10L = 48mA COM'L.

10H

10H

-

-

-0.7

-60

-120

VHC

Vcc

VHC

VCC

2.4

4.3

2.4

-

V

_5(4)
-5
-1.2

-

4.3
GND

VLC

GND

VLC(4)

0.3

0.5

0.3

0.5

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee =5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

V
mA
V

V

25591b1 05

IDT54174FCT399/A
FAST CMOS QUAD DUAL-PORT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = O.2V; VHC = VCC - O.2V
Test Conditions(1)

Typ.(2)

Max.

Unit

icc

Quiescent Power Supply
Current

Vcc = Max.
VIN ~ VHC; VIN ~ VLC

-

0.2

1.5

mA

l.icc

Quiescent Power Supply
Current TIL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

-

0.5

2.0

mA

ICCD

Dynamic Power Supply
Current(4)

Vcc = Max.
Outputs Open
One Input Toggling
50% Duty Cycle

VIN~ VHC
VIN ~ VLC

-

0.15

0.25

mAl
MHz

Ic

Total Power Supply
Current(6)

Vcc = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
S = Steady State

VIN~ VHC
VIN ~ VLC
(FCT)

-

1.7

4.0

mA

VIN = 3.4V
VIN = GND

-

2.2

6.0

VIN ~ VHC
VIN ~ VLC
(FCT)

-

4.0

7.8(5)

VIN = 3.4V
VIN = GND

-

5.2

12.8(5)

Symbol

Parameter

Vcc = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
Four Bits Toggling
at fi = 5MHz
50% Duty Cycle
S = Steady State

Min.

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TIL driven input (V IN = 3.4V); all other inputs at Vce or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + 61cc DHNT + ICCD (fCP/2 + fiNi)
Icc = Quiescent Current
61cc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.47

2559 tbl 06

I

4

I

IDT54f74FCT399! A
FAST CMOS QUAD DUAL-PORT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT399
Com'l.
Symbol

Parameter

Conditlon(1)

MlnP) Max.

tPLH
tPHL

Propagation Delay
CP to an

tsu

Set-up Time HIGH or LOW
In to CP

4.0

-

4.S

tH

Hold Time HIGH or LOW
In to CP

1.0

-

tsu

Set-up Time HIGH or LOW
Sto CP

9.0

tH

Hold Time HIGH or LOW
Sto CP

tw

CP Pulse Width HIGH or LOW

CL = SOpF
RL = soon

3.0

11.S

Com'l.
MinP)

Mil.
Max. Mln.(2) Max.

Unit

2.S

7.0

2.S

7.S

ns

-

3.S

-

4.0

-

ns

1.S

-

1.0

-

1.0

-

ns

-

9.S

-

8.S

-

9.0

-

ns

0

-

0

-

0

-

0

-

ns

s.o

-

7.0

-

s.o

-

6.0

-

3.0

10.0

IDT54/74FCT399A

Mil.
Mln.(2) Max.

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

ns
2559 tbl 07

6.47

5

IOT54174FCT3991 A
FAST CMOS QUAD DUAL·PORT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION

TEST CIRCUITS FOR ALL OUTPUTS

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

2559 ttll 08
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
Rr = Termination resistance: should be equal to Zour of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT

zzt

l

~...K.....K~

PULSE WIDTH

-= ~~V
-

OV

-

3V
1.5V
OV

Isu-0j4--~

x---+------------'

-

lOWHIG~~~~

ASYNCHRONOUS CONTROL

-

PRESET - - - -.....
CLEAR
ETC. ----~.

--+-------

=t-

HIGH-lOW-HIGH
PULSE

3V
1.5V
OV

_

~ 1.5V
_ _ 1.5V

lw

SYNCHRONOUS CONTROL
CLOCK

:~~~~~ vvY
l
~ISU

~...K.....K~

ETC.

- 3V
-1.5V
OV

II

ENABLE AND DISABLE TIMES

PROPAGATION DELAY

ENABLE

DISABLE

I

_--_.----3V
SAME PHASE
INPUT TRANSITION

\--'+----OV

3.5V
OUTPUT

VOL
VOH

OUTPUT

OPPOSITE PHASE
INPUT TRANSITION

SWITCH

NORM~~~ OPEN

OV

'---------OV
NOTES
2559 drw 05
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ SOQ; IF ~ 2.Sns;
tA ~ 2.5ns.

6.47

6

IDT54f74FCT399!A
FAST CMOS QUAD DUAL-PORT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xx
Temperature
Range

FCT

XXX X

x

x

Device
Type

Package

Process

~~Iank
L..-_ _ _ _ _ _ _-j

L..-------------t
L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--j

Commercial
MIL-STD-883, Class B

P
D
L
SO
E

Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC
CERPACK

399
399A

Quad Dual-Port Register
FAST Quad Dual-Port Register

54
75

-55°Cto+125°C
O°C to + 70°C
2559 drw 04

6.47

7

t;)

IDT54/74FCT521
IDT54174FCT521 A
IDT54174FCT521 B
I DT54/74 FCT521 C

FAST CMOS 8-BIT
IDENTITY COMPARATOR

Integrated Device Technology, Inc.

FEATURES:
•
•
•
•
•
•
•
•
•
•

IDTS4/74FCTS21 equivalent to FASpM speed
IDTS4174FCTS21A 35% faster than FASTTM
IDT54174FCT521 B 50% faster than FASTTM
IDT54/74FCT521C 60% faster than FASTTM
Equivalent to FASTTM output drive over full temperature
and voltage supply extremes
IOl = 48mA (commercial), and 32mA (military)
CMOS power levels (1 mW typo static)
TIL input and output level compatible
CMOS output level compatible
.Substantially lower input current levels than FAS"fTM
(SJlA max.)

• Product available in Radiation Tolerant and Radiation
Enhanced versions
• JEDEC standard pinout for DIP and LCC
• Military product compliant to Mll-STD-883, Class B

DESCRIPTION:
The I DT54174FCT521 I AlBIC are 8-bit identity comparators
built using advanced CEMOSTM , a dual metal CMOS technology. These devices compare two words of upto eight bits each
and provide a lOW output when the two words match bit for
bit. The expansion input fA = 8 also serves as an active lOW
enable input.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS
-1A=8

Ao
Bo
A1
B1

Vee

4
6

B2
A3
B3

7

OA=8

OA=8

B7
A7
Bs
As
Bs
As
B4
A4

17

P20-1
020-1
S020-2
&
E20-1

5

A2.

GND

19
18

2
3

16
15
14

8

13

9

12

10

11

I

II

I

2604 drw 01

DI P/SOIC/CER PACK
TOP VIEW
CD

INDEX

CD

0

I

I

I

I

..............

3

2604 drw 03

A1
B1
A2
B2
A3

()

o
II
()
co <,s;
>

2

:] 4

II

«

1°

I

II
I
, L-I L-I
I
""
U 20 19

1

:] 6

:J 7
:J 8

18[:

B7

17[: A7

:] 5
l20-2

16[:
15[:
14[:

Bs
As
Bs

9 10 11 12 13
......, ......,
I I I I

......, ......, r - t
I II I I
I

0:l~~£D<
(9

2604 drw 02

Lce
CEMOS is a 1rademark of Integrated Device Technology. Inc.
FAST is a trademark of Fairchild Semiconductor. Inc.

TOP VIEW

MILITARY AND COMMERCIAL TEMPERATURE RANGES
1' 05

L
H
H
H

A;tS
A = S*
A;tS

NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level

*Ao

ABSOLUTE MAXIMUM RATINGS(1)

=

So. Al

=

S1. A2

260411>1' 06

=

S2. etc.

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol

Rating

Commercial

Military

Unit

VTERM(2)

Terminal Voltage
with Respect to
GND

-Q.5 to +7.0

-Q.5 to +7.0

V

VTERM(3)

Terminal Voltage
with Respect to
GND

-Q.5 to Vee

-Q.5 to Vee

V

Parameter<1)
Symbol
Input
ON
Capacitance
CoUT
Output
Capacitance

Conditions
VIN = OV

Typ,

Max,

6

10

Unit
pF

VOUT= OV

8

12

pF

NOTE:
260411>1' 02
1. This parameter is measured at characterization but not tested.

TA

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature

-55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

0.5

0.5

W

120

120

mA

Under Bias
TSTG

Storage
Temperature

PT

Power
Dissipation

lOUT

DC Output
Current

NOTES:
260411>1' 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed vec by +0.5V unless otherwise noted.
2. Input and vee terminals only.
3. Outputs and 110 terminals only.

6.48

2

IDT54f74FCT521/A1B/C FAST CMOS

8-BIT IDENTITY COMPARATOR

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C, VCC = 5.0V ± 5%; Military: TA = -55°C to + 125°C, VCC = 5.0V ± 10%
Min.

Typ.(2)

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

V

VIL

Input LOW Level

Guaranteed Logic LOW Level

0.8

V

IIH

Input HIGH Current

Vcc = Max.

-

-

-

S

IlA

-

S(4)

Symbol

Test Conditions

Parameter

(1)

VI- Vcc
VI= 2.7V

ilL

Input LOW Current

VI- O.SV
VI=GND

VIK

Clamp Diode Voltage

Vcc = Min., ~= -18mA

los

Short Circuit Current

Vcc = Max.l3), Vo= GND

VOH

Output HIGH Voltage

Output LOW Voltage

-S

-0.7

-1.2

-120

Vcc = 3V, VIN = VLC or VHC, bH", -321lA

VHC

Vcc

-

Vcc= Min.

VHC

Vcc

-

IoH = -3001lA
IoH = -12mA MIL.

2.4

4.3

IoH = -1SmA COM'L.

2.4

4.3

Vcc = 3V, VIN = VLC or VHC, bL = 300llA
Vcc = Min.

IoL = 300llA

VIN= VIHor VIL

IoL = 32m A MIL.
IoL = 48mA COM'L.

-

Unit

-S(4)

-60

VIN = VIHor VlL

VOL

Max.

GND

VLC

GND

VLd 4)

0.3

O.S

0.3

O.S

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable devico typo.
2. Typical values are at Vcc= 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

V
mA
V

V

;>(,()4IlJI· 0)

•

6.48

3

I

I

IDT54f74FCT521/A1B/C FAST CMOS
8-BIT IDENTITY COMPARATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol

VLC

= O.2V; VHC = VCC -

Tvp.(2)

Max.

Unit

-

0.2

1.5

mA

-

0.5

2.0

mA

VIN ~ VHC
VIN ~ VLC

-

0.15

0.25

Vcc = Max.
Outputs Open

VIN ~ VHC
VIN ~ VLC (FCT)

-

1.7

4.0

fi = 10MHz
One Bit Toggling
50% Duty Cycle

VIN = 3.4V
VIN =GND

-

2.0

5.0

Quiescent Power Supply Current

Vcc = Max.
VIN> VHC' VIN < VLC

tilcc

Quiescent Power Supply Current
TTL Inputs HiGH

Vce = Max.
VIN = 3.4 V(3)

Iceo

Dynamic Power Supply Curreni 4 )

Vcc = Max.
Outputs Open
One Input Toggling
50% Duty Cycle

lec

Total Power Supply Curreni S)

Ie

O.2V

Test Conditions(1)

Parameter

Min.

mAl
MHz

mA

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + t1lcc DHNT + ICCD (fCPf2 + fiNi)
Icc = Quiescent Current
t1lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Numberof Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

2604 tbl' 04

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54f74FCT521
Com'l.
Symbol

IDT54f74FCT521A

Mil.

Mil,

Com'l.

IDT54f74FCT521 B
Com'l.

IDT54f74FCT521C
Com'l.

Mil.

Mil.

Parameter Condition(1) Min.(2) Max. Min.(21 Max. Min.(21 Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.

tPLH

Propagation

CL = 50pF

tPHL

Delay

RL =

soon

Unit

1.5

11.0

1.5

15.0

1.5

7.2

1.5

9.5

1.5

5.5

1.5

7.3

1.5

4.5

1.5

5.1

ns

1.5

10.0

1.5

9.0

1.5

6.0

1.5

7.8

1.5

4.6

1.5

6.0

1.5

4.1

1.5

4.5

ns

An or 8n to
OA=B
tPLH

Propagation

tPHL

Delay
iA = 8 to
OA=B

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

2604 tbl' 07

6.48

4

IDT54f74FCT521/A1B/C FAST CMOS
8-BIT IDENTITY COMPARATOR

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vee

SWITCH POSITION
0--.7.0V

soon

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
26041b108
CL = Load capacitance: indudes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

XX{

j

tsu .......'i4--~

PULSE WIDTH

~..K.~~

-= ~~V
-

OV

"OW-HIG~U"&~

- 3V
V
_

TIMING
INPUT

6J

ASYNCHRONOUS CONTROL
PRESET - - - - - - - - , ~--+_---r-------­ - 3V
- - + - - - - - - 1.SV
CLEAR
- OV
ETC. - - - - - - - - "
SYNCHRONOUS CONTROL
CLOCK

:~~it~ ~tsu
vvJr j

~..K.~~

ETC.

=t

HIGH-lOW-HIGH
PULSE

tw

_ _ 1.SV

- 3V
-1.SV
OV

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

J---"\. - - - -

__

~ 1.5V

DISABLE

_-----3V
---1.SV
)----'. + - - - - OV

3V

SAME PHASE
INPUT TRANSITION

3.SV
OUTPUT

VOL
OUTPUT

SWITCH

NORM~~~ OPEN

OPPOSITE PHASE
INPUT TRANSITION

VOH

OV

NOTES
2604 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate 5 1.0 MHz; Zo 5 son; tF 5 2.5ns;
tR 5 2.5ns.

6.48

5

IDT54174FCT521/AlBfC FAST CMOS
8-BlT IDENTITY COMPARATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XX
FCT
XXXX
----Temp. Range
Device Type

X

X

Package

Process

Y:1ank
P

D
'--------1 E

L
SO

521
521A

1--------------~521B

521C

154

~--------------------------------I174

Commercial
MIL-STD-aa3, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
a-Bit Comparator
Fast a-Bit Comparator
Very Fast a-Bit Comparator
Super Fast a-Bit Comparator

-55°C to + 125°C
O°C to +70°C
2604 cnv· 09

6.48

6

(;)®

IDT54/74FCT543
IDT54/74FCT543A

FAST CMOS
OCTAL LATCHED
TRANSCEIVER

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• IOT54/74FCT543 equivalent to FASTTM speed
• IDT54174FCT543A 25% faster than FASTTM
• Equivalent to FASTTM output drive over full temperature
and voltage supply extremes
• IOL = 64mA (commercial), 48mA (military)
• 8-bit octal latched transceiver
• Separate controls for data flow in each direction
• Back-to-back latches for storage
• CMOS power levels (1 mW typo static)
• Substantially lower input current levels than FASTTM

The IOT54/74FCT543/A is a non-inverting octal transceiver built using advanced CEMOSTM, a dual metal CMOS
technology. These devices contain two sets of eight Ootype
latches with separate input and output controls for each set.
For data flow from A to B, for example, the A-to-B Enable
(CEAB) input must be LOW in order to enter data from Ao-A7
orto take data from Bo-B7, as indicated in the Function Table.
With CEAB LOW, a LOW signal on the A-to-B Latch Enable
(LEAB) input makes the A-to-S latches transparent; a
subsequent LOW-to-HIGH transition of the LEAB signal puts
the A latches in the storage mode and their outputs no longer
change with the A inputs. With CEAB and OEAB both LOW,
the 3-state B output buffers are active and reflect the data
present at the output of the A latches. Control of data from B
to A is similar, but uses the CESA, LEBA and OEBA inputs.

(5~max.)

• TIL input and output level compatible
• CMOS output level compatible
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
r---------------------------------------------------,
DETAIL A
D

Q

>-------------~-+--Bo

LE
Ao-+--+-~----------_4_<

Q

D

I

LE
_________________ _______ ___ _________________ __.J

A1
A2
A3
A4

B1

82
83

DETAIL Ax 7

B4
85

As
As
A7

8s

87

D----OEAB
CEBA - - -......>---1:1
LEBA

~

____________________~~r-+----CEAB

2614 drw 01

CEMOS is a trademark of Integrated Device Techology, tnc.
FAST is a registered trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
<01990 Integrated Device Technology. Inc.

6.49

JUNE 1990
DSC-4602I-

1

IOT54174FCT543! A
FAST CMOS OCTAL LATCHED TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
Vee

LEBA
OEBA
Ao
A1
A2
A3
A4
As
A6

A7
CEAB
GND

ol~'ffi....JZ>OCIl
° slffi

INDEX

CEBA
Bo
B1
B2
B3
B4
Bs
B6
B7
LEAB
OEAB

<:

4 3 2

A1
A2
A3
NC
A4
A5
A6

28 27 26

1

J28-1
L28-1

]B

]9
] 10
] 11
12 13 14 15 16 17 18

. . . ,CIl 0 0ICIlICIlCIl. . .
<:<:zz<:<:
~C)

~~

25[
24 [
23 [
22 [
21[
20[
19 [

B1
B2
B3
NC
B4
B5
B6

2614 drw 02

LCC/PLCC
TOP VIEW

FUNCTION TABLE (1,2)

PIN DESCRIPTION

For A-to-S (Symmetric with S-to-A)

Description

OEAB

A-to-B Output Enable Input (Active LOW)

OEBA

B-to-A Output Enable Input (Active LOW)
CEAB

tEAS

A-to-S Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)

LEAS

A-to-B Latch Enable Input (Active LOW)

LEBA

B-to-A Latch Enable Input (Active LOW)

Arr-A7

A-to-B Data Inputs or B-to-A 3-State Outputs

26141b102

LEAB

OEAB

A-to-B

-

-

Storing

-

H

-

Storing

-

-

H

H

B-to-A Data Inputs or A-to-B 3-State Outputs

LOGIC SYMBOL

Latch
Status

Inputs

CESA

Brr-B7

I I
LJ

]5
]6
]7

DIP/SOIC/CERPACK
TOP VIEW

Pin Names

0

L...JL...JL...JIIL...JL...JL......J

-

Output
Buffers
Brr-B7
High Z

High Z

L

L

L

Transparent

Current A Inputs

L

H

L

Storing

Previous· A Inputs

NOTES:
26141b101
1.· Before LEAB LOW-to-HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
- = Don't Care or Irrelevant
2. A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA.

LEAB CEAB CEBA LEBA
Ao

Bo

A1

B1

A2

B2

A3

B3

A4

B4

As

Bs

A6

B6

A7
OEBA

B7
OEAB
2614 drw 03

6.49

2

IDT54n4FCT543/A
FAST CMOS OCTAL LATCHED TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage

CAPACITANCE

Commercial

Military

Unit

-C.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vcc

-0.5 to Vcc

V

Operating
Temperature

o to +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

"C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

= +25°C, f = 1.0MHz)
Conditions Typ.

CIN

Input Capacitance

VIN = OV

6

10

pF

CliO

liO Capacitance

VOUT = OV

8

12

pF

Max.

Unit

NOTE:
2614 tbl 04
1. This parameter is guaranteed by characterization data and not tested.

with Respect
toGND
TA

(TA

Parameter(1)

Symbol

NOTES:
2614 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +O.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Outputs and 110 terminals only.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

=

=

Following Conditions Apply Unless Otherwise Specified: VLC 0.2V, VHC VCC - 0.2V
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA -55°C to +125°C, Vcc

=

= 5.0V ± 10%
Min.

Typ.(2)

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

V

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

-

0.8

V

Input HIGH Current

Vee = Max.

5
5(4)

)lA

_5(4)

)lA

Symbol

IIH

IlL

Test Condltlons(1)

Parameter

= Vee

-

-

VI = 2.7V

Input LOW Current

VI

-

(Except 1/0 pins)

VI = GND

-

= Vee

-

15
15(4)

)lA

-

-15(4)

)lA

-

-15

-0.7
-120

VI

= 0.5V

VIK

Clamp Diode Voltage

Vee = Min., IN = -18mA

los

Short Circuit Current

Vee = Max.(3), Vo = GND

-60

VOH

Output HIGH Voltage

Input HIGH Current

Vee = Max.

VI

(1/0 pins Only)
IlL

VI = 2.7V

= 0.5V

Input LOW Current

VI

(1/0 pins Only)

VI = GND

Output LOW Voltage

-5

-1.2

Vee = 3V, VIN = VLe or VHC, 10H = -32)lA

VHe

Vee

-

Vee = Min.

10H = -300)lA

VHC

Vee

-

10H = -12mA MIL.

2.4

4.3

10H = -15mA COM'L.

2.4

4.3

-

VIN = VIH or VIL
VOL

Unit

(Except 1/0 pins)

-

IIH

Max.

Vee = 3V, VIN = VLe or VHe, 10L = 300)lA

-

GND

VLe

Vee = Min.

10L = 300)lA

-

GND

VLd 4)

VIN = VIH or VIL

10L = 48mA MIL.(S)

-

0.3

0.55

0.3

0.55

10L = 64mA COM'L. (5)

V
mA
V

V

NOTES:
2614 tbl 05
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not excedd one second.
4. This parameter is guaranteed but not tested.
.
5. These are maximum 10L values per output, for 8 outputs turned on simultaneously. Total maximum IOL (all outputs) is 512mA for commercial and 384mA
for military. Derate 10L for number of outputs exceeding 8 turned on simultaneously.
6.49

3

I

IDT54174FCT543/A
FAST CMOS OCTAL LATCHED TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

VLC

= O.2V; VHC = VCC - O.2V
Typ.(2)

Max.

Unit

Icc

Quiescent Power
Supply Current

Vcc = Max.
VIN ~ VHC; VIN ~ VLC

-

0.2

1.5

rnA

tilcc

Quiescent Power Supply
Current TIL Inputs HIGH

Vcc = Max., VIN = 3.4V(3)

-

0.5

2.0

rnA

ICCD

Dynamic Power Supply Current(4)

Vcc = Max., Outputs Open
CEAB and OEAB = GND
CEBA = Vcc
One Input Toggling
50% Duty Cycle

VIN ~ VHC
VIN $ VLC

-

0.15

0.25

rnA!
MHz

Ic

Total Power Supply Current(6)

Vcc = Max., Outputs Open
fcp = 10MHz (LEAB)
50% Duty Cycle
CEAB and OEAB = GND
CEBA= Vcc
One Bit Toggling
at fi = 5MHz
50% Duty Cycle

VIN ~ VHC
VIN $ VLC
(FCT)

-

1.7

4.0

rnA

VIN = 3.4V
VIN = GND

-

2.2

6.0

Vcc = Max., Outputs Open
fcp = 10MHz (LEAB)
50% Duty Cycle
CEAB and OEAB = GND
CEBA = Vcc
Eight Bits Toggling
at fi = 5MHz
50% Duty Cycle

VIN ~ VHC
VIN $ VLC
(FCT)

-

7.0

12.8(5)

VIN = 3.4V
VIN = GND

-

9.2

21.8(5)

Symbol

Parameter

Test Condltions(1)

Min.

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IOUIESCENT +IINPUTS + IDYNAMIC
Ic = Icc + 61cc DHNT + ICCD(fcP/2 + fiNi)
Icc = Quiescent Current
61cc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.49

26141b106

4

IDT5417 4FCT543! A
FAST CMOS OCTAL LATCHED TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT543
Com'l.

Symbol

Parameter

tPLH
tPHL

Propagation Delay Transparent
Mode An to Bn or Bn to An

tPLH
tPHL

Cond ition(1)

Mln.!2) Max.

IDT54/74FCT543A

Mil.

Com'l.

Mln.(2) Max.

Min.!2)

Mil.

Max. Min.!21 Max.

Unit

2.S

8.S

2.S

10.0

2.S

6.S

2.S

7.S

ns

Propagation Delay
LEBA to An, LEAB to Bn

2.S

12.5

2.5

14.0

2.S

8.0

2.5

9.0

ns

tPZH
tPZL

Output Enable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn

2.0

12.0

2.0

14.0

2.0

9.0

2.0

10.0

ns

tPHZ
tPLZ

Output Disable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn

2.0

9.0

2.0

13.0

2.0

7.S

2.0

8.S

ns

tsu

Set-up Time, HIGH or LOW
An or Bn to LEBA or LEAB

3.0

-

3.0

-

2.0

-

2.0

-

ns

tH

Hold Time, HIGH or LOW
An or Bn to LEBA or LEAB

2.0

-

2.0

-

2.0

-

2.0

-

ns

tw

LEBA or LEAB Pulse Width LOW

s.o

-

s.o

-

s.o

-

s.o

-

ns

CL = SOpF
RL = soon

NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

2514 tbl 07

I

6.49

5

I DT5417 4FCT543! A
FAST CMOS OCTAL LATCHED TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vee

SWITCH POSITION
0-.7.0V

soon

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2614 tbl 08
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

j

""'-~~~

PULSE WIDTH

--= ~~V
_ OV

tsu -40\4--..-.t

TIMING
INPUT _ _ _ _ _ _-'

lOW-HIG~~&~

- 3V
- - - - . . , f - - - - - - 1.5V
- OV

ASYNCHRONOUS CONTROL
PRESET - - - -....
CLEAR
ETC. _ _ _ _J

- 3V
- - t - - - - - - 1.5V
- OV

=f-

HIGH-lOW-HIGH

~ 15V
tw

--1.5V

PULSE

SYNCHRONOUS CONTROL

CLOCK:~~~~~ ~SU
vvY j
ETC.

""'-~~~

t

- 3V
-1.5V
-OV

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

----3V
SAME PHASE
INPUT TRANSITION

3.5V
OUTPUT

VOL
VOH

SWITCH
OPEN

OPPOSITE PHASE
INPUT TRANSITION

OV

"--------OV

NOTES
2614 drw 05
1. Diagram shown for input Control Enable-LOW and input Control
Disable-H I GH.
2. Pulse Generator for All Pulses: Rate S 1.0 MHz; Zo s 50n; tF S 2.5ns;
tR:5 2.Sns.

6.49

6

I DT54f7 4FCT543/ A
FAST CMOS OCTAL LATCHED TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XX

----

FCT XXXX

Temperature
Range

Device
Type

X

X

Package

Process

~~Iank
'-----------1

P
D
L
SO
E

J

Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC
CERPACK
Plastic Leaded Chip Carrier

543

Octal Registered Transceiver
Fast Octal Registered Transceiver

54
74

-55°C to + 125°C
0° to +70°C

' - - - - - - - - - - - - - - - 1 543A
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

Commercial
MIL-STD-883, Class B

2614 drw 04

I

6.49

7

t;)®

IDT54/74FCT646
I DT54/74FCT646A
IDT54/74FCT646C

FAST CMOS OCTAL
TRANSCEIVER/REGISTER

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

•
•
•
•
•
•
•
•
•
•

The IDT54/74FCT6461NC consists of a bus transceiver
with 3-state D-type flip-flops and control circuitry arranged for
multiplexed transmission of data directly from the data bus or
from the internal storage registers.
The IDT54/74FCT6461NC utilizes the enable control (<3)
and direction (DIR) pins to control the transceiver functions.
SAB and SBA control pins are provided to select either real
time or stored data transfer. The circuitry used for select
control will eliminate the typical decoding glitch that occurs in
a multiplexer during the transition between stored and realtime data. A LOW input level selects real-time data and a
HIGH selects stored data.
Data on the A or B data bus or both can be stored in the
internal D flip flops by LOW-to-HIGH transitions at the
appropriate clock pins (CPAB or CPBA) regardless of the
select or enable control pins.

IDT54/74FCT646 equivalent to FASTTM speed;
IDT54/74FCT646A 30% faster than FASpM
IDT54/74FCT646C 40% faster than FASpM
Independent registers for A and B buses
Multiplexed real-time and stored data
IOL = 64mA (commercial) and 48mA (military)
CMOS power levels (1 mW typical static)
TIL input and output level compatible
CMOS output level compatible
Available in 24-pin (300 mil) CERDIP, plastic DIP, SOIC,
CERPACK, 28-pin LCC and PLCC
• Product available in Radiation Tolerant and Radiation
Enhanced Versions
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

DIR - - - - - - - I
CPBA-------~-----------~ ~---------+_,

SBA
CPAB

-------~-----t

----I

SAB----------~--+---1

1 OF 8 CHANNELS

BREG

- -,

",--+--+-,-. B 1

A 1 +-1+--+---'

-

--------------

~

~------------~y~------------~

TO 7 OTHER CHANNELS

2536 drw 01

CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a registered trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1990 Integrated Device Technology. Inc.

6.50

JUNE 1990
DSC-4626/·

1

IDT54174FCT646/AIC
FAST CMOS OCTAL TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
INDEX

Vex;

CPA8
SA8
DIR
A1
A2
A3
A4
As
A6

L.....J L...J L-J

A1
A2
A3
NC
A4
As
A6

G
81
82
83
84
85
86
87
B8

A7
A8
GND

I 1 L-J

L-J L-J

4 3 2 1 1 28 27 26

CP8A
S8A

JS
J6
J7
J8
J9
J10
] 11

25 [
24 [
23 [

1
J28-1
&
L28-1

G
81
82
NC
B3
84
85

22 [

21 [
20 [
19 [

12 13 14 lS 16 17 1a

2536 drw 02

Lce

D1P/SOIC/CERPACK
TOP VIEW

TOP VIEW

PIN DESCRIPTION

LOGIC SYMBOL

Pin Names

Description

A1-Aa

Data Register A Inputs
Data Register 8 Outputs

81-88

Data Register 8 Inputs
Data Register A Outputs

CPA8, CPBA

Clock Pulse Inputs

SA8,S8A

Output Data Source Select Inputs

DIR,G

Output Enable Inputs

CPAB
SA8
DIR
CPBA
S8A

A1

A2

A3

A4

As

A6

A7 As

G

81

B2

83

84

8s

B6

87 8a

2536 tbl 01
2536 drw 06
I

II

FUNCTION TABLE(2)
Data

Inputs

110(1)

Operation or Function

G

DIR

CPAB

CPBA

SAB

SBA

A1-Aa

B1-Ba

H
H

X
X

H or L

H or L

Input

i

X
X

Input

i

X
X

Isolation
Store A and B Data

L
L

L
L

X

X
H or L

X
X

L
H

Output

Input

Real Time B Data to A Bus
Stored B Data to A Bus

L
L

H
H

X

L
H

X
X

Input

Output

Real Time A Data to B Bus
Stored A Data to B Bus

X
X
H or L

X

IOT54/74FCT646

NOTES:
2536 tbl 02
1. The data output functions may be enabled or disabled by various signals at the G or DIR inputs. Data input functions are always enabled, i.e., data at
the bus pins will be stored on every low-to-high transition on the clock inputs.
2. H = HIGH, l = lOW, X = Don't Care, i = lOW-to-HIGH Transition.

6.50

2

I DT5417 4FCT646/ AlC
FAST CMOS OCTAL TRANSCEIVER/REGISTER

'I

MILITARY AND COMMERCIAL TEMPERATURE RANGES

'I

'I

I

III

I

I

III

I

BUS
A

'I

I

III

I

I

III

I
BUS

BUS
A

BUS

B

B

'----y---J

'----y---J
DIR

G

CPAB

CPBA

SAB

SBA

L

L

X

X

X

L

DIR

G

CPAB

CPBA

SAB

SBA

H

L

X

X

L

X

REAL-TIME TRANSFER
BUS A TO BUS B

REAL-TIME TRANSFER
BUS B TO BUSA

2536 drw 03

BUS

B

'----y---J
DIR
H
L

G
L

CPAB

L

X

X

H

~
~

CPBA

SAB

SBA

X

X
X
X

X
X
X

+
~

DIR(1)

G

CPAB

L

L

X

H

L

H or L

CPBA
H or L

SAB

X

TRANSFER STORED
DATA TO A AND/OR B

STORAGE FROM
A AND/OR B

X

H

SBA
H

X
2536 drw 04

NOTE:
1. Cannot transfer data to A bus and B bus simultaneously.

6.50

3

IOT5417 4FCT646/ AlC
FAST CMOS OCTAL TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE (TA = +25°C, f = 1.0MHz)

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3l Terminal Voltage
with Respect
toGND
TA
TSIAS
TSTG

Operating
Temperature
Temperature
Under Bias
Storage
Temperature

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

o to +70

-55 to +125

°C

-55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

·DC Output Current

120

120

mA

Parameter(1)

Symbol

Conditions

Typ. Max.

Unit

CIN

Input Capacitance

VIN = OV

6

10

pF

CliO

1/0 Capacitance

VOUT = OV

8

12

pF

NOTE:
2536
1. This parameter is measured at characterization but not tested.

tbl 04

NOTES:
2536 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Inputs and Vee terminals only.
3. Outputs and I/O terminals only.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc

= S.OV± 10%
Min.

Typ.(2)

Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

V

VIL

Input LOW Level
Input HIGH Current

Guaranteed Logic LOW Level

-

-

0.8

V
Il A

-

5
5(4)

Symbol

IIH
IlL
IIH
IlL
VIK
los
VOH

Test Conditions(1)

Parameter

Vee = Max.

VI = Vee

(Except 1/0 pins)

VI = 2.7V

-

Input LOW Current

VI = 0.5V

(Except 1/0 pins)

VI = GND

-

Input HIGH Current

(1/0 pins only)
Input LOW Current
(1/0 pins only)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage

Vee

= Max.

VI = Vee
VI = 2.7V
VI = 0.5V
VI = GND

Vee = Min., IN = -18mA
Vee = Max.\.j!, Vo = GND
Vee

= 3V,

VOL

Output LOW Voltage

= 3V, VIN = VLC
Vcc = Min.
VIN = VIH or VIL
Vee

_5(4)
-5
15
15(4)
-15

-

-0.7

-60

-120

-

mA
V

-1.2

VHe

Vcc

-

VHe
2.4

Vec
4.0

-

10H = -15mA COM'L.

2.4

-

4.0
GND

-

GND

VLC
VLd 4)

-

0.3

0.55

0.3

0.55

or VHC, 10L = 300ilA
10L = 300llA
10L = 48mA MIL.
10L = 64mA COM'L.

V

-

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

6.50

Il A

-15(4)

10H = - 3OO IlA
10H = -12mA MIL.

VIN = VLe or VHC, 10H = -321lA

Vcc = Min.
VIN = VIH or VIL

-

-

-

V

2536 tbl 05

4

I

I

IDT54f74FCT646/A1C
FAST CMOS OCTAL TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC

= O.2V; VHC = VCC -

O.2V
Min.

Typ.(2)

Max.

Unit

Icc

Quiescent Power Supply Current

Vcc = Max.
VIN ~ VHC; VIN s VlC

-

0.2

1.5

mA

L'1lcc

Quiescent Power Supply Current
TTL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

-

0.5

2.0

mA

ICCD

Dynamic Power Supply Current(4)

Vcc = Max.
Outputs Open
G = DIR =GND
One Input Toggling
50% Duty Cycle

VIN ~ VHC
VIN S VLC

-

0.15

0.25

mAlMHz

Ic

Total Power Supply Current(6)

Vcc = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
G = DIR =GND
One Bit Toggling
at fi = 5MHz
50% Duty Cycle

VIN ~ VHC
VIN S VLC
(FCT)

-

1.7

4.0

mA

VIN = 3.4V
VIN = GND

-

2.2

6.0

Vcc = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
G = DIR =GND
Eight Bits Toggling
at fi = 5MHz
50% Duty Cycle

VIN ~ VHC
VIN S VLC
(FCT)

-

7.0

12.8(5)

VIN = 3.4V
VIN = GND

-

9.2

21.8(5)

Symbol

Parameter

Test Conditions(1)

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived lor use in Total Power Supply calculations.
5. Values lor these conditions are examples 01 the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (lcP/2 + liNi)
Icc = Quiescent Current
Lllcc = Power Supply Current lor a TTL High Input (VIN = 3.4V)
DH = Duty Cyde lor TIL Inputs High
NT = Number 01 TIL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
Icp = Clock Frequency lor Register Devices (Zero lor Non-Register Devices)
Ii = Input Frequency
Ni = Number 01 Inputs at Ii
All currents are in milliamps and all frequencies are in megahertz.

6.50

2536 tbl 06

5

IDT54f74FCT646/ AlC
FAST CMOS OCTAL TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
54174 FCT646A

54174FCT646
Com'l.
Symbol

Parameter

tPLH
tPHL

Propagation
Delay
Bus to Bus

tPZH
tPZL

Com'l.

Mil.

54174FCT646C

Mil.

Condition(l) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.

Com'l.
Mln.(2)

Mil.

Max. Min.(2) Max.

Unit

2.0

9.0

2.0

11.0

2.0

6.3

2.0

7.7

1.5

5.4

1.5

6.0

ns

Output Enable
Time G, DIR to
Bus

2.0

14.0

2.0

15.0

2.0

9.8

2.0

10.5

1.5

7.8

1.5

8.9

ns

tPHZ
tPLZ

Output Disable
Time G, DIR to
Bus

2.0

9.0

2.0

11.0

2.0

6.3

2.0

7.7

1.5

6.3

1.5

7.7

ns

tPLH
tPHL

Propagation
Delay Clock
to Bus

2.0

9.0

2.0

10.0

2.0

6.3

2.0

7.0

1.5

5.7

1.5

6.3

ns

tPLH
tPHL

Propagation
Delay SBA or
SAB to Bus

2.0

11.0

2.0

12.0

2.0

7.7

2.0

8.4

1.5

6.2

1.5

7.0

ns

tsu

Set-up Time
HIGH or LOW
Bus to Clock

4.0

-

4.5

-

2.0

-

2.0

-

2.0

-

2.0

-

ns

tH

Hold Time
HIGHor LOW
Bus to Clock

2.0

-

2.0

-

1.5

-

1.5

-

1.5

-

1.5

-

ns

tw

Clock Pulse
Width HIGH or
LOW

6.0

-

6.0

-

5.0

-

5.0

-

5.0

-

5.0

-

ns

CL = 50 pF
RL = 500n

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

2536 tbl07

II

6.50

6

IDT54174FCT646/A/C
FAST CMOS OCTAL TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION

TEST CIRCUITS FOR ALL OUTPUTS

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2536 tbl 08
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zxt

J

~

PULSE WIDTH

-= ov~~V

______ -

tSU---+---+i

TIMING
INPUT

-

3V

-

OV

-

3V

-

OV

LOWHIG~UL~~

- - r - - - - - - - 1.5V

ASYNCHRONOUS CONTROL
PRESET - - - - ,
CLEAR
ETC. - - - - ,

zzt

=t-

HIGH-LOW-HIGH
PULSE

- - j - - - - - - - l.SV

~ 15V
Iw

_ _ 1.SV

SYNCHRONOUS CONTROL

P~r~f~

CLOCK ENABLE
ETC.

J
"",,-~~;....Jo.

tsu

- 3V
-1.SV
OV

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

----3V

_--_----3V
SAME PHASE
INPUT TRANSITION

~--"r

+ - - - - OV
3.SV

OUTPUT

VOL
VOH

SWITCH
OPEN

OPPOSITE PHASE
INPUT TRANSITION

OV

'---------OV

NOTES
2536 drw 07
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ SOil; tF ~ 2.Sns;
tR ~ 2.5ns.

6.S0

7

IDT54n 4FCT646/ AlC
FAST CMOS OCTAL TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

xx

-------Temperature
Range

FeT

XXXX

xx

x

Device
Type

Package

Process/
Temperature
Range

'---------11 ~Ia

nk

P

o

'--________________~ SO
L
E
J
~------------------------~

646
646A
646C

~--------------------------------------1 54
75

Commercial
MIL-STO-883, Class B
Plastic DIP
CEROIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Plastic Leaded Chip Carrier
Non-inverting Octal Transceiver/Register
Fast Non-inverting Octal Transceiver/Register
Super Fast Non-inverting Octal Transceiver/Register
-55°C to + 125°C
O°C to +70°C

2536 drw 05

II

6.50

8

~

I DT54/74FCT821 AlBIC
I DT54/74FCT823A/B/C
I DT54/74FCT824A/B/C
I DT54/74FCT825A/B/C

HIGH-PERFORMANCE
CMOS BUS INTERFACE
REGISTERS

Integrated Device Technology, Inc.

FEATURES:

•
•
•
•
•
•
•
•
•
•
•
•

DESCRIPTION:

Equivalent to AMD's Am29821-25 bipolar registers in
pinouVfunction, speed and output drive over full temperature and voltage supply extremes
IDT54/74FCT821N823N824A1825A equivalent to
FAS"fTM speed
IDT54/74FCT821 8/8238/8248/825825% faster than
FASTTM
IDT54/74FCT821 C/823C/824C/825C 40% faster than
FASTTM
Buffered common Clock Enable (EN) and asynchronous
Clear input (CLR)
IOL = 48mA (commercial) and 32mA (military)
Clamp diodes on all inputs for ringing suppression
CMOS power levels (1 mW typo static)
TIL input and output compatibility
CMOS output level compatible
Substantially lower input current levels than AM D's
bipolar Am29800 series (5j.LA max.)
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT800 series is built using advanced
CEMOSTM, a dual metal CMOS technology.
The IDT54/74FCT820 series bus interface registers are
designed to eliminate the extra packages required to buffer
existing registers and provide extra data width for wider address/data paths or buses carrying parity. The IDT54/
74FCT821 are buffered, 10-bit wide versions of the popular
'374 function. The IDT54/74FCT823 and IDT54/74FCT824
are 9-bit wide buffered registers with Clock Enable (EN) and
Clear (CLR) - ideal for parity bus interfacing in high-performance microprogrammed systems. The IDT54/74FCT825 are
8-bit buffered registers with all the '823 controls plus multiple
enables (OE1, OE2, OE3) to allow multiuser control of the
interface, e.g., CS, DMA and RD/WR. They are ideal for use
as an output port requiring high loUloH.
All of the IDT54/74FCT800 high-performance interface
family are deSigned for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in high impedance
state.

FUNCTIONAL BLOCK DIAGRAMS
IDT54/74FCT824

IDT54/74FCT821/823/825
Do

Do

ON

ON

EN

CLR

CP

OE

Yo
CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of Fairchild Semiconductor Co.

YN

Yo

2608 cnv' 01

2608 cnv' 02

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1990 Integrated Device Technology. Inc.

YN

6.51

JUNE 1990
DSC-4618/-

1

IDT54f74FCT821/823/824/825A1B/C

HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

LOGIC SYMBOLS

IDT54/74FCT821 1 O-BIT REGISTER

Vee

OE
Do
01
02
03
04
05
06
07
Oa
09
GNO

INDEX

~oUJo8o~

ooOz>>->-

Yo
Y1
Y2
Y3
Y4
Ys
Y6
Y7
Ya
Y9
CP

I

02
03
04
NC
05
06
07

II

II

II II

II II

I

'4'3''2'1 282726

25[:
24[:
23[:
:]7
:]8
22[:
L28-1
:J9
21[:
:]10
20[:
:]11
19[:
12131415161718
:]5
:]6

Y2
Y3
Y4
NC
Ys
Y6
Y7

D~D
CP

CP

Q~Y

DE

nnnnnnn
0 0 c...
Cl

<0

Cl

a:l

OOZZO>->G
LeC
TOP VIEW

DIP/SOIC/CERPACK
TOP VIEW

2608 cnv' 03

IDT54/74FCT823/824 9-BIT REGISTERS
OE
Do
01
02
03
04
05
06
07
Oa
CLR
GNO

Vee
Yo
Y1
Y2
Y3
Y4
Ys
Y6
Y7
Ya
EN
CP

INDEX

~8~o8o~
Z>>->-

o
I

02
03
04
NC
05
06
07

:]5
:]6

II 11'1

I'll

II

I

'4'5'2'1 282726

25[:
24[:
:]7
23[:
:]8
22[:
L28-1
:J9
21[:
:]10
20[:
:]11
19[:
12131415161718

Y2
Y3
Y4
NC
Ys
Y6
Y7

0

Y

CP
EN
CLR

DE

II

,..., ,-, ,....,,-, ...... 1"""1 ,...,
•

I'"

II

II

II

tit

Z co
Clla:
0 0 c...I W >..JZZO
OG
LCC
TOP VIEW

DIP/SOIC/CERPACK
TOP VIEW

2608 cnv' 04

IDT54/74FCT825 8-BIT REGISTER
OE1
OE2
Do
01
02
03
04
05
06
07
CLR
GNO

Vee
OE3
Yo
Y1
Y2
Y3
Y4
Ys
Y6
Y7
EN
CP

INDEX
I II I I

01
02
03
NC
04
05
06

:]5
:]6

I

I I

I

I I

I I

25[:
24[:
23[:
:]7
:]8
22[:
L28-1
21[:
:J9
:]10
20[:
:]11
19[:
12131415161718
,...,,.., ,....,,......,,...,,...,,...,
I.

I

"ll

II

II

I

0

I

'4'3''2'1 282726

Y1
Y2
Y3
NC
Y4
Ys
Y6

Y

CP
EN
CLR
OE1
OE2
OE3

••

0la:o
O~IZ>=
..JZ Z
W
OG
DIP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW

6.51

2608 cnv' 05

2

IDT 5417 4FCT821/823/824/825A1B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE(1)
IDT54/74FCT821 18231825

PRODUCT SELECTOR GUIDE
Device

I Non-inverting
I Inverting

9-Bit

8-Bit

54f74FCT821 AlBIC

54f74FCT823A1B/C

54f74FCT825A1B/C

54f74FCT824A1B1C
26081b101

PIN DESCRIPTION
Name

1/0

Description

01

I

The 0 flip-flop data inputs.

CLR

I

CP

I

For both inverting and non-inverting
registers, when the clear input is LOW
and OE is LOW, the 01 outputs are
LOW. When the clear input is HIGH,
data can be entered into the reqister.
Clock Pulse for the Register; enters
data into the register on the LOW-toHIGH transition.

YI,YI

a

EN

I

OE

I

CLR

EN

DI

CP

01

VI

Function

H
H

H
H

L
L

L
H

i
i

L
H

Z
Z

High Z

H
L
H
L

L
L
H
H
H
H
H
H

X
X

X
X
X
X

X
X
X
X

L
L
NC
NC

Clear

L
H
L
H

i
i
i
i

L
H
L
H

Z
L
Z
NC
Z
Z
L
H

H
H
L
L
L
L

Hold
Load

NOTE:
2608 tbl 02
1. H = HIGH, L = LOW, X = Don't Care, NC = No Change, i = LOW-to-HIGH
Transition, Z = HIGH-impedance

FUNCTION TABLE(1)
IDT54/74FCT824

Clock Enable. When the clock enable
is LOW, data on the 01 input is
transferred to the 01 output on the
LOW-to-HIGH clock transition. When
the clock enable is HIGH, the 01
outputs
do
not
change
state,
regardless of the data or clock input
transitions.
Output Control. When the OE input is
HIGH, the YI outputs are in the high
impedance state. When the OE input is
data

OE

H
H
L
L

The register three-state outputs.

LOW, the TRUE register
present at the YI outputs.

Internal!
Outluts

Inputs

10-Bit

Internal!
Outluts

Inputs

is

26081b101

OE

CLR

EN

DI

CP

01

VI

Function

H
H

H
H

L
L

L
H

i
i

H
L

Z
Z

High Z

H
L
H
L

L
L
H
H

X
X

X
X
X
X

L
L
NC
NC

H
H
L
L

H
H
H
H

L
L
L
L

L
H
L
H

i
i
i
i

H
L
H
L

Z
L
Z
NC
Z

Clear

H
H

X
X
X
X

Hold
Load

Z
H
L

NOTE:
2608 tbl 03
1. H = HIGH, L = LOW, X = Don't Care, NC = No Change, i = LOW-toHIGH Transition, Z = HIGH-impedance

6.51

3

I DT5417 4FCT821/823/824/825A1B/C
HIGH·PERFORMANCE CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
VTERM(2) Terminal Voltage -0.5 to +7.0
with Respect to
GND
VTERM(3) Terminal Voltage
-0.5 to Vee
with Respect to
GND

CAPACITANCE

Military

Unit

-0.5 to +7.0

V

-0.5 to Vee

V

(TA = +25°C,

Parameter(1)

Symbol

f = 1.0MHz)

Conditions

Typ.

Max.

Unit

CIN

Input
Capacitance

VIN = OV

6

10

pF

COUT

Output
Capacitance

VOUT= OV

8

12

pF

NOTE:
2608 till 05
1. This parameter is measured at characterization but not tested.

TA

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipatior

0.5

0.5

W

lOUT

DC Output
Current

120

120

mA

NOTES:
2608 till 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Input and Vec terminals only.
3. Outputs and 110 terminals only.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc= 5.0V ± 10%
Symbol

Parameter

Test Conditions

(1)

Min.

Typ. (2) Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

V

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

-

0.8

V

IIH

Input HIGH Current

Vee = Max.

VI = \Ce

-

)lA

-

-

5

VI = 2.7V

5(4)

VI = 0.5V

-

-

-5(4)

VI = GND

-

-

-5

Vo= Vee

-

-

10

Va = 2.7V

-

10(4)

Vo= 0.5V

-

Va = GND

-

-

IlL

10ZH

Input LOW Current

Off State (High Impedance)

Vee = Max.

Output Current
lOlL

VIK

Clamp Diode Voltage

Vee = Min., IN = -18mA

los

Short Circuit Current

Vee = MaxP), Va = GND

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

-

-0.7

-10(4)
-10
-1.2

mA

Vee

-

V

Vee

-

2.4

4.3

-

2.4

4.3

-120

Vee = 3V, VIN = VLe or \Me, 10H = -321lA

VHe

Vee = Min.

10H = -300)lA

VHe

VIN = VIH or VIL

10H = -15mA MIL.
10H = -24mA COM'L.

-

Vee = 3V, VIN = VLe or \Me, 10L = 300llA

-

GND

VLe

Vee = Min.

10L = 300llA

-

GND

VLc'4)

10L = 32m A MIL.

-

0.3

0.5

10L = 48mA COM'L.

-

0.3

0.5

NOTES.
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vec = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
6.51

V

-

-75

VIN = VIH or VIL

)lA

V

2608 till 06

IOT54174FCT821/823/824/825A1B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLV CHARACTERISTICS
VLC

= 0 2V' VHC = VCC - 0 2V

Svmbol
Icc
L\lcc
ICCD

Tvp.(2)

Max.

Unit

-

0.2

1.5

mA

-

0.5

2.0

mA

VIN ~ VHC
VIN $ VlC

-

0.15

0.25

mAl
MHz

Vec = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle

VIN ~ VHC
VIN $ VlC

-

1.7

4.0

mA

OE = EN= GND

VIN =3.4V
VIN =GND

-

2.2

6.0

VIN~ VHC

-

4.0

7.8(5)

-

6.2

16.8(5)

Test Conditlons(l)

Parameter
Quiescent Power Supply Current

Vec = Max.
VIN> VHC' VIN < VlC

Quiescent Power Supply Current
TIL Inputs HIGH

Vec = Max.
VIN = 3.4V(3)

Dynamic Power Supply
Current(4)

Vcc = Max.
Outputs Open
OE= EN = GND

Min.

One Input Toggling
50% Duty Cycle
Ic

Total Power Supply Current(6)

One Bit Toggling

(FCT)

atf i = 5MHz
50% Duty Cycle
Vcc = Max.
Outputs Open
fcp = 10MHz

VIN $ VlC
(FCT)

50% Duty Cycle
OE= EN = GND
Eight Bits Toggling
at f i = 2.5MHz
50% Duty Cycle

VIN = 3.4V
VIN = GND

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IOUIESCENT + I INPUTS + IDYNAMIC
Ic = Icc + Lllcc DHNT + ICCD (fcp/2 + fNi)
Icc = Quiescent Current
Lllcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.51

2608 lbl 07

5

I DT 5417 4FCT821/823/824/825A1B/C
HIGH·PERFORMANCE CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

tPLH
tPHL

Description
Propagation Delay
CP to Y I(OE = LOW)

Conditlons(l)

CL = SOpF

soon

RL =
CL = 300pF(3)
RL =

tsu

Set-up Time HIGH or LOW
DitoCP

tH

soon

CL = SOpF
RL =

soon

Hold Time HIGH or LOW
D ItoCP

IDT54174FCT821 BI

823A1824A/825A

823B/824B/825B

Com'l.

Test
Parameter

IDT54174FCT821 AI

Com'l.

Mil.

IDT54174FCT821CI

823C/824C/825C
Com'l.

Mil.

Mil.

Min.l2) Max. Min.(2) Max. Min.(2) Max. Min.l2) Max. Min.l2) Max. Min.(2) Max.

-

10.0

-

11.S

-

7.S

-

8.S

-

6.0

-

7.0

-

20.0

-

20.0

-

1S.0

-

16.0

-

12.S

-

13.S

Unit
ns

4.0

-

4.0

-

3.0

-

3.0

-

3.0

-

3.0

-

ns

2.0

-

2.0

-

1.S

-

1.S

-

1.S

-

1.S

-

ns

tsu

Set-up Time HIGH or LOW
EN to CP

4.0

-

4.0

-

3.0

-

3.0

-

3.0

-

3.0

-

ns

tH

Hold Time HIGH or LOW
EN to CP

2.0

-

2.0

-

0

-

0

-

0

-

0

-

ns

tPHL

Propagation Delay, CLR to

-

9.0

-

9.S

-

8.0

-

8.S

ns

-

VI

tREM

Recovery Time CLR to CP

tw

CP Pulse Width
HIGH or LOW

tw

CLR Pulse Width

tPZH
tPZL

Output Enable Time OE

LOW
to VI

CL = SOpF
RL =
CL = 300pF(3)

soon
soon

tPHZ
tPLZ

Output Disable Time OE

RL =
CL = SpF(3)

to VI

RL =

soon

CL = SOpF
RL =

soon

14.0

-

1S.0

6.0

-

7.0

-

6.0

-

6.0

-

6.0

-

6.0

-

ns

7.0

-

7.0

-

6.0

-

6.0

-

6.0

-

6.0

-

ns

6.0

-

7.0

-

6.0

-

6.0

-

6.0

-

6.0

-

ns
ns

-

12.0

-

13.0

-

8.0

-

9.0

-

7.0

-

8.0

-

23.0

-

2S.0

-

1S.0

-

16.0

-

12.S

-

13.S

-

7.0

-

8.0

-

6.S

-

7.0

-

6.2

-

6.2

-

8.0

-

9.0

-

7.S

-

8.0

-

6.S

-

6.S

NOTES:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.

ns

2608 tbl· 08

rI
I

6.51

6

IDT54f74FCT821/823/824/825A1B/C

HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION

TEST CIRCUITS FOR ALL OUTPUTS

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2608 tbl 09
CL = Load capacitance: includes jig and probe capacitance.
Rr = Termination resistance: should be equal to Zour of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zxt

PULSE WIDTH

--= ~~V

l

~..K.....K~ -

OV

-

3V

-

3V
1.5V
OV

-

3V

tsu -4'14--~

TIMING
INPUT

- - - j f - - - - - - 1.5V
- OV

LOWHIG~U~~

ASYNCHRONOUS CONTROL
PRESET - - - -.....
CLEAR
ETC. - - - - "
SYNCHRONOUS CONTROL

P~~~~~

CLOCK ENABLE
ETC.

zzt

--+------

l
""-..K.....K~

tsu

=t-

HIGH-LOW-HIGH
PULSE

~ 15V
tw

--1.5V

-1.5V
- OV

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

----3V

_--_----3V
SAME PHASE
INPUT TRANSITION

l - - - ' -+----- OV

3.SV
OUTPUT

VOL
VOH

SWITCH
OPEN

OPPOSITE PHASE
INPUT TRANSITION

OV

NOTES
2608 drw 01
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate::; 1.0 MHz; Zo::; SOQ; tF ::; 2.Sns;
tR::; 2.Sns.

6.51

7

IDT54n4FCT821/823/824/825A1B/C

HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xx

T='e-m-p-.-=R::""a-n-g-e

xxxx

x

x

Package

Process

y~lank
P
D
~--------;E

L
SO
821A
821B
821C
823A
~------------~823B

823C
824A
824B
824C
825A
825B
825C
54

~----------------------------------~74

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
1O-Bit Non-Inverting Register
Fast 1O-Bit Non-Inverting Register
Super Fast 1O-Bit Non-Inverting Register
9-Bit Non-Inverting Register
Fast 9-Bit Non-Inverting Register
Super Fast 9-Bit Non-Inverting Register
9-Bit Inverting Register
Fast 9-Bit Inverting Register
Super Fast 9-Bit Inverting Register
8-Bit Non-Inverting Register
Fast 8-Bit Non-Inverting Register
Super Fast 8-Bit Non-Inverting Register
-55°C to + 125°C
O°C to +70°C
2GOO cov· 11

6.51

8

(;)

I DT54/74 FCT827 A
IDT54/74FCT827B
IDT54/74FCT827C

HIGH-PERFOMANCE
CMOS BUFFERS

Integrated Device Technology, Inc.

FEATURES:
•

•
•
•
•
•
•
•
•
•
•
•

DESCRIPTION:

Faster than AMO's Am29827 series
Equivalent to AMO's Am29827 bipolar buffers in pinoutl
function, speed and output drive over full temperature
and voltage supply extremes
IOT54/74FCT827A equivalent to FASl'M
IDT54/74FCT827B 35% faster than FASpM
IDT54/74FCT827C 45% faster than FASpM
IOL = 48mA (commercial), and 32mA (military)
Clamp diodes on all inputs for ringing suppression
CMOS power levels (1 mW typo static)
TIL input and output level compatible
CMOS output level compatible
Substantially lower input current levels than AMO's
bipolar Am29800 series (5JlA max.)
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STO-883, Class B

The IOT54/74FCT800 series is built using advanced
CEMOSTM, a dual metal CMOS technology.
The IOT54/74FCT827 AlBIC 10-bit bus drivers provide
high-performance bus interface buffering for wide datal
address paths or buses carrying parity. The 10-bit buffers
have NANO-ed output enables for maximum control flexibility.
All of the IOT54/74FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in high impedance
state.

FUNCTIONAL BLOCK DIAGRAM
Yo

Yl

Y2

Y3

Y4

Ys

Ys

Y7

YB

yg

2609 drw 01

PRODUCT SELECTOR GUIDE
10-Bit Buffer
IDT54174FCT827A/B/C
2609 tblOl
CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1990 Integrated Device Technology. Inc.

6.52

JUNE 1990
DSC-46121-

1

IDT54174FCT827 AlBIC
HIGH-PERFOMANCE CMOS BUFFERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

LOGIC SYMBOL
INDEX

Vee

C5E1

00

Yo

D1

Y1

D2

Y2
Y3

OJ
D4

Y4
Ys

Os
06
Os

Y6
Y7
Ya

[)g

Y9

D7

GND

D2

:]5

03
D4
NC

:]6

~ Ii Ii Y~M~25 [:
24[:
23 [:

:]7
:]8
Os :]9
06 :]10
D7 :]11

L28-1

22 [:
21 [:
20[:
19 [:
12131415161718

C5E2

I

YI

0

2609 drw 04

FUNCTION TABLE(1)
Output

Inputs

Description
When both are LOW, the outputs are

OEl

OE2

DI

VI

Function

enabled. When either one or both are

L

L

L

L

Transparent

Z.

L

L

H

H

1a-bit data input.

H

X

X

1O-bit data output.

X

H

X

Z
Z

2609lbl02

ABSOLUTE MAXIMUM RATINGS(1)
Rating
Sxmbol
VTERMI'::) Terminal Voltage
with Respect to
GND
VTERM(J) Terminal Voltage

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

Operating

Three-State

NOTE:
1. H = HIGH, L = LOW, X = Don't Care, Z = High-Impedance

CAPACITANCE
Symbol
CIN

(TA

Parameter(1)
Input

2609 tbl 03

= +25°C, f = 1.0MHz)
Conditions

Typ.

Max.

Unit

VIN = OV

6

10

pF

VOUT = OV

8

12

pF

Capacitance
GoUT
-0.5 to +7.0

-0.5 to Vee

V

o to +70

-55 to +125

°C

-55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

with Respect to
GND
TA

C5E2 _ _--OI

2609 drw 03

HIGH, the outputs are High
DI

0E'1

LCC
TOP VIEW

1/0

I

10
.>--;.-YO-9

88~~~~>

PIN DESCRIPTION
OEI

Y2
Y3
Y4
NC
Ys
Y6
Y7

10
------"7"-i

nnnnnnn

DIP/CERPACKISOIC
TOP VIEW 2609drw02

Name

00-9

Output
Capacitance

NOTE:
1. This parameter is measured at characterization but not tested.

2609 Ibl 05

Temperature
TSIAS

Temperature
Under Bias

TSTG

Storage
Temperature

Pr

Power Dissipation

0.5

0.5

W

lOUT

DC Output

120

120

mA

Current
NOTE:
2609lbl04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and 1/0 terminals only.

2

IDT54174FCT827AlBIC
HIGH-PERFOMANCE CMOS BUFFERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHe = Vec-0.2V
Commercial: TA = O°C to +70°C, Vec = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vee = 5.0V ± 10%
Symbol

Test Condltlons(1)

Parameter

Min.

Typ.(2)

Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

0.8

V

IIH

Input HIGH Current

Vce = Max.

-

-

5
5(4)

JlA

I IL

Input LOW Current

10ZH

Off State (High Impedance)

VI = Vcc

Vee = Max.

Output Current
10ZL

VI = 2.7V

-

VI = 0.5V

-

VI = GND

-

Vo= Vce

-

Vo= 2.7V

-

Vo= 0.5V
Vo= GND

VIK

Clamp Diode Voltage

Vee = Min., IN = -18mA

los

Short Circuit Current

Vee = Max.(3), Vo= GND

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

-

-

-5(4)

-

_5(4)

-

10(4)

-

-10(4)

10

-0.7

-10
-1.2

Vcc

-

V

Vce

-

Vcc = 3V, VIN = VLe or VHC, IOH = -32JlA

VHe

Vee = Min.

IOH = -300JlA

VHe

VIN = VIH or V1L

IOH = -15mA MIL.

2.4

4.3

IOH = -24mA COM'L.

2.4

4.3

-

Vce = 3V, VIN = VLC or VHC, IOL = 300JlA

-

GND

Vce = Min.

IOL = 300JlA

-

GND

IOL = 32mA MIL.

-

0.3

0.5

0.3

0.5

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

6.52

V
mA

-120

IOL = 48mA COM'L.

JlA

-

-75

VIN = VIH or VIL

V

V

VLC
VLd 4)

2609 tbl 06

3

I DT5417 4FCT827AlBIC
HIGH·PERFOMANCE CMOS BUFFERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Svmbol

VLC

= O.2V; VHC = VCC -

O.2V

Test Conditions(l)

Parameter

Min.

Typ.(2)

Max.

Unit

0.2

1.5

mA

Quiescent Power Supply Current

Vcc = Max.
VIN> VHC' VIN < VLC

Lllcc

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

-

0.5

2.0

mA

ICCD

Dynamic Power Supply Current(4)

Vcc = Max.
Outputs Open
OE1 = OE2 = GND
One Input Toggling
50% Duty Cycle

VIN 2: VHC
VIN ~ VLC

-

0.15

0.25

mAl
MHz

Ic

Total Power Supply Current(6)

Vcc = Max.
Outputs Open
f i= 10MHz

VIN 2: VHC
VIN ~ VLC
(FCT)

-

1.7

4.0

mA

50% Duty Cycle
OE1 = OE2 = GND

VIN =3.4V
VIN = GND

-

2.0

5.0

VCC = Max.
Outputs Open
f i = 2.5MHz

VIN 2: VHC
VIN ~ VLC
(FCT)

-

3.2

6.5(5)

50% Duty Cycle
OE1 = OE2 = GND
Eight Bits Toggling

VIN = 3.4V
VIN = GND

-

5.2

14.5(5)

Icc

-

One Bit Toqqlinq

NOTES:
1.
2.
3.
4.
5.
6.

:'GO,) ttll 07

For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicablo duvic() typo.
Typical values are at Vcc = 5.0V, +25°C ambient.
Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + .1.lcc DHNT + ICCD (fcp/2 + fiN i)
Icc = Quiescent Current
.1.lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.52

I

4

IDT54f74FCT827AlBIC
HIGH·PERFOMANCE CMOS BUFFERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

Parameter

tPLH
tPHL

tPZH
tPZL

tPHZ
tPLZ

Description

Propagation Delay
Dlto YI

Output Enable Time
OEltoYI

Output Disable Time
OEI tOYI

Conditions(1)

= 50pF
RL = soon
C!. = 300pF(3)
RL = soon
C!. = 50pF
RL = soon
C!. = 300pF(3)
RL = soon
C!. = 5pF(3)
RL = soon
C!. = 50pF
RL = soon
C!.

IDT54f74FCT827A

IDT54f74FCT827B

IDT54f74FCT827C

Com'l.

Com'l.

Com'l.

Mil.

Mil.

Mil.

Min.(2) Max. Mln.(2) Max. Mln.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.

-

8.0

-

9.0

-

5.0

-

6.5

-

4.4

-

5.0

-

15.0

-

17.0

-

13.0

-

14.0

-

10.0

-

11.0

-

12.0

-

13.0

-

8.0

-

9.0

-

7.0

-

8.0

-

23.0

-

25.0

-

15.0

-

16.0

-

14.0

-

15.0

-

9.0

-

9.0

-

6.0

-

7.0

-

5.7

-

6.7

-

10.0

-

10.0

-

7.0

-

8.0

-

6.0

-

7.0

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.

Unit

ns

ns

ns

2609 tbl 08

6.52

5

IDT54174FCT827AlBIC
HIGH·PERFOMANCE CMOS BUFFERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vee

SWITCH POSITION
O-7.0V

soon

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2609 tbl 09
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zxt

j

PULSE WIDTH

~...M~IIL-;a.

-= ~~V
-

OV

-

3V
1.SV
OV

tsu--t~-~

TIMING
INPUT

--1-------

lOW-HIG~Ul~~

ASYNCHRONOUS CONTROL
PRESET - - - - - - - - , ~--~--~--------­ - 3V
- - + - - - - - - 1.SV
CLEAR
- OV
ETC. - - - - - - - " "
SYNCHRONOUS CONTROL
- 3V
-1.SV
J
CLOCK
~..K.~~ OV
ETC.

=t

HIGH-lOW.HIGH
PULSE

~ 1.5V
_ _ 1.SV

lw

:~~~~~ vvJr
~tsu

I

PROPAGATION DELAY

II

ENABLE AND DISABLE TIMES
ENABLE

DISABLE
3V

3V

1.SV

SAME PHASE
INPUT TRANSITION

OUTPUT

OV
3.SV

VOH
-1.SV

VOL

VOL
VOH
SWITCH
OPEN

OPPOSITE PHASE
IN PUT TRANSITION

OV

OV

NOTES
2609 drw 11
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ son; tF ~ 2.Sns;
tR ~ 2.Sns.

6.52

6

I DT5417 4FCT827AlBIC
HIGH-PERFOMANCE CMOS BUFFERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDTXXFCT

xx

x

x

Device Type

Package

Process

y~[ank
P
D

L...---------IE
L
SO
827A
L...-.--------------------~827B

827C
L...-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~54

74

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Non-Inverting 1a-Bit Buffer
Fast Non-Inverting 1a-Bit Buffer
Super Fast Non-Inverting 1 a-Bit Buffer

-55°C to + 125°C
aoc to +7aoC
2609 eny· 10

6.52

7

G®

I DT54/74FCT833A
IDT54/74FCT833B

FAST CMOS
PARITY BUS
TRANSCEIVER

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• Equivalent to AMO's Am29833 bipolar parity bus
transceiver in pinout/function, speed and output drive
over full temperature and voltage supply extremes
High-speed bidirectional bus transceiver for processororganized devices
I OTS4/74 FCT833A equivalent to Am29833A speed and
output drive
IDT54174FCT833B 30% faster than Am29833A
Buffered direction and three-state controls
Error flag with open-drain output
IOL = 48mA (commercial) and 32mA (military)
TIL input and output level compatible
CMOS output level compatible
Substantially lower input current levels than AMO's
bipolar Am29800 series (SJlA max.)
Available in plastic OIP, CEROIP, LCC, PLCC and SOIC
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STO-883, Class B

The IDTS4/74FCT833s are high-performance bus
transceivers designed for two-way communications. They
each contain an 8-bit data path from the R (port) to the T (port),
an 8-bit data path from the T (port) to the R (port), and a 9-bit
parity checker/generator. The error flag can be clocked and
stored in a register and read at the ERR output. The clear
(CLR) input is used to clear the error flag register.
The output enables OET and OER are used to force the
port outputs to the high-impedance state so that the device
can drive bus lines directly. In addition, OER and OETcan be
used to force a parity error by enabling both lines
simultaneously. This transmission of inverted parity gives the
designer more system diagnostic capability. The devices are
specified at 48mA and 32mA output sink current over the
commercial and military temperature ranges, respectively.

FUNCTIONAL BLOCK DIAGRAM
RI

TI

PARITY

II

OET
OER

I

D

Q

ERR

Q

ClK

CP
ClR
2557 drw 01

ClR

CEMOS is a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1990 Integrated Device Technology. Inc.

6.53

JUNE 1990
DSC-4621 1-

1

IDT54f74FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
INDEX

Vee

OER

Ro

L....JL....JL......JUL....JL....JL....J

To

R1
R2
R3
R4
Rs
R6
R7
ERR
ClR
GND

4 3 2

T1
T2
T3
T4
Ts
T6
T7
PARITY
OET
ClK

R2
R3
R4
NC
Rs
R6
R7

Js
J6
J7
J8
J9
J 10
J 11

282726

1
J28-1
l28-1

12 13 14 lS 16 17 18

I

ERROR FLAG OUTPUT FUNCTION TABLE(1,2)
Description
Inputs

RECEIVE enable input.

CLR

RI

1/0

8-bit RECEIVE data inpuVoutput.

ERR

0

Output from fault registers. Register
detection of odd parity fault on rising clock
edge (ClK). A registered ERR output
remains low until cleared. Open drain
output, requires pull up resistor.

ClR

I

TI

1/0

PARITY

1/0

a:-.JZZ-.JIWI-

Iwo(,!)

OER

2S [
24 [
23 [
22[
21 [
20 [
19 [

H
H
H
l

ClK
i
i
i

-

Internal
To Device

Output
Pre-State

Output

Point "P"

ERRn-l

ERR

Function

H

H
l

Sample
(1's
Capture)
Clear

l

-

H
l
l

-

-

H

-

NOTE:
1. OET is HIGH and OER is LOW.

Clears the fault register output.

2. H = HIGH
L= LOW
i = LOW to HIGH transition of clock
- = Dont Care or Irrelevant

8-bit TRANSMIT data inpuVoutput.
1-bit PARITY output.

OET

I

TRANSMIT enable input.

ClK

I

External clock pulse input for fault register
flag.
2557 tbl 01

6.53

2557 tbl 02

IDT54174FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE(2)
Inputs

Outputs
TI Incl Parity

OET

OER

ClR

ClK

RI (:2: or H's)

(L. of H's)

RI

TI

Parity

ERR(l)

L
L
L
L

H
H
H
H

H
H
H
H

H (Odd)
H (Even)
L(Odd)
L (Even)

NA
NA
NA
NA

NA
NA
NA
NA

H
H
L
L

L
H
L
H

H
L
H
L

Transmit data from R Port
to T Port with parity;
receiving path is disabled.

H
H
H
H

L
L
L
L

H
H
H
H

i
i
i
i
i
i
i
i

NA
NA
NA
NA

H (Odd)
H (Even)
L(Odd)
L (Even)

H
H
L
L

H
L
H
L

Receive data from T Port
to R Port with parity test
resulting in flag:
transmitting path is disabled.

-

NA
NA
NA
NA
NA

H

Clear the state of error flag
register.

-

-

L

H
H
H
H

H
H
H
H

H
L
H
H

L
L
L
L

L
L
L
L

H
H
H
H

H or L

-

i
i
i
i
i
i

Function

-

-

NA

NA
NA
NA
NA
NA

-

-

Z
Z
Z
Z

Z
Z
Z
Z

Z
Z
Z
Z

"
H
H
L

Both transmitting and
receiving paths are disabled.
Parity logic defaults to
transmit mode.

NA
NA
NA
NA

NA
NA
NA
NA

H
H
L
L

H
L
H
L

L
H
L
H

Forced-error checking.

-

H or L (Odd)
H or L (Even)
H (Odd)
H (Even)
L(Odd)
L (Even)

NOTES:
1. Output state assumes HIGH output pre-state.
2. H
= HIGH
L
= LOW
i
= LOW to HIGH transition of clock
"No change to stored Error State

2557 tbl 03

Z
NA

=
=

HIGH Impedance
Not Applicable
Don't Care or Irrelevant

Odd
Even

I

=
=

Odd number of logic one's
Even number of logic one's
0, 1, 2, 3, 4, 5, 6, 7

I

6.53

3

I

IDT54174FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(l)
Symbol

Rating

VTERM(2) Terminal Voltage
with Respect
to GND
VTERM(;j) Terminal Voltage

CAPACITANCE

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

(TA = +25°C, f = 1.0MHz)

Symbol Parameter(l)

Conditions

CIN

Input

Typ.

Max.

Unit

VIN = OV

6

10

pF

VOUT = OV

8

12

pF

Capacitance
-0.5 to VCC

-0.5 to Vcc

V

CIlO

with Respect
to GND
TA

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

I/O
Capacitance

NOTE:
2557
1. This parameter is guaranteed by characterization but not tested.

tbl 05

lOUT
DC Output Current
120
120
rnA
NOTE:
2557 tbl 03
1. Stresses greaterthan those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
Vcc by +O.5V unless otherwise noted.
2. Inputs and Vcc terminals.
3. Outputs and 1/0 terminals.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C VCC = 5 OV -+ 5%' Military' TA = -55°C to +125°C Vcc

Symbol

Test Conditions(1)

Parameter

=5

OV -+ 10%

Min.

Typ.(2)

-

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

VIL

Input LOW Level

Guaranteed Logic LOW Level

'-

IIH

Input HIGH Current

Vcc = Max.

Max.

V

5
5(4)

Il A

(I/O Pins Only)

VI = 2.7V

IlL

Input LOW Current
(I/O Pins Only)

VI = 0.5V
VI = GND

VIK

Clamp Diode Voltage

Vcc = Min., IN = -18mA

los

Short Circuit Current

Vcc = Max.(3), Vo = GND

-60

-120

VOH

Output HIGH Voltage

Vcc = 3V, VIN = VLC or VHC, 10H = -321lA

VHC

Vcc

(Except ERR)

Vcc = Min.

10H = -3OOIlA

VHC

Vcc

-

VIN = VIH or VIL

10H = -15mA MIL.

2.4

4.3

-

10H = -24mA COM'L.

2.4

4.3

IlL

(Except I/O Pins)

VI = 2.7V

Input LOW Current

VI = 0.5V

(Except I/O Pins)
IIH

VOL

Input HIGH Current

Output LOW Voltage

VI = GND
Vcc = Max.

VI = Vcc

10L = 48mA COM'L.

-

10L = 48mA

-

Vcc = 3V, VIN = VLC or VHC, 10L = 300llA
Vcc = Min.

Except

10L = 300llA

VIN = VIH

ERR

10L = 32 rnA MIL.

or VIL
ERR

-0.7

GND

_5(4)
-5
Il A

15
15(4)
-15(4)
-15
-1.2

V
rnA
V

-

GND

VLC
VLc!4)

0.3

0.5

0.3

0.5

0.3

0.5

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested,

6.53

V

0.8

-

VI =Vcc

Unit

-

v

2557 tbl06

4

I OT5417 4FCT833AfB
FAST CMOS PARITY BUS TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol
Icc
L'1lcc
ICGD

Ic

Parameter
Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current(4)

Total Power Supply Current(6)

VLC

= O.2V; VHC = VCC -

O.2V

Test Conditions(l)

Min.

Vcc = Max.; VIN > VHC, VIN ~ VLC
Vcc = Max.
VIN = 3.4V(3)
Vcc = Max.
Outputs Open
OET = OER = GND
One Input Toggling
50% Duty Cycle

VIN ~VHC
VIN ~ VLC

Vcc = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
OET = GND
OER = Vcc
fi = 2.5MHz
One Bit Toggling
Vcc = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
OET = GND
fi = 2.5MHz
OER = Vcc
Eight Bits Toggling

VIN ~ VHC
VIN ~ VLC
(FCT)

-

Typ.(2)

Max.

Unit

0.2

1.5
2.0

mA

0.5

mAl
MHz

-

0.15

0.25

VIN ~ VHC
VIN ~ VLC
(FCT)

-

1.4

3.4

VIN =3.4V
VIN =GND

-

1.9

5.4

-

4.0

7.8(5)

-

6.2

16.8(5)

VIN =3.4V
VIN =GND

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ie = laulEscENT + IINPUTS + IDYNAMIC
Ic = Ice + ~Icc DHNT + ICCD (fcpf2 + fiNi)
Icc = Quiescent Current
~Ice = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or lHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.53

mA

mA

2557 tbl07

II

5

IDT54f74FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT833A
Com'l.
Symbol

Parameter

tPLH

Propagation Delay

tPHL

Conditions(l)

Min.(2)

IDT54/74FCT833B

Mil.

Max.

Min.(2)

Com'l.
Max.

Min.(2)

Mil.
Max.

Unit

10.0

ns

14.S

-

10.S

-

14.0

27.S

-

18.0

-

8.S

-

21.S

16.0

-

23.S

-

16.0

-

18.S

10.7

-

14.7

-

7.2

-

9.8

12.0

-

16.0

-

8.S

-

11.0

-

10.0

-

14.0

-

7.0

RI to TI, TI to RI

= SOpF
CL = 300pF(3)

-

17.S

-

21.S

-

tPLH

Propagation Delay

CL

1S.0

-

20.0

Rlto PARITY

CL

= SOpF
= 300pF(3)

-

tPHL

-

Output Enable Time

CL

12.0

-

tPZL

OER, OET to RI, TI

19.5

tPHZ

Output Disable Time

= SOpF
CL = 300pF(3)
CL = SpF(3)

-

22.S

tPZH

-

tPLZ

OER, OET to RI, TI

CL

-

tsu

TI, PARITY to ClK
Set-up Time

tH

TI, PARITY to ClK
Hold Time

tREM

CL

= SOpF
CL = SOpF

Min.(2)

-

Max.

17.S
ns

11.0

ns

ns

12.0

-

16.0

-

8.S

-

11.0

-

ns

0

-

0

-

0

-

0

-

ns

Clear Recovery Time
ClRto ClK

1S.0

-

20.0

-

10.S

-

14.0

-

ns

tw

Clock Pulse Width
HIGH or lOW

7.0

-

9.S

-

S.S

-

7.0

-

ns

tw

Clear Pulse Width
LOW

7.0

-

9.S

-

S.S

-

7.0

-

ns

tPHL

Propagation Delay
CLKto ERR

-

12.0

-

16.0

-

8.S

-

11.0

ns

tPLH

Propagation Delay
CLR to ERR

-

16.0

-

20.0

-

1S.0

-

18.0

ns

-

1S.0

-

20.0

-

10.S

-

14.0

ns

-

22.S

-

27.S

-

18.0

-

21.S

tPLH

Propagation Delay

CL

= SOpF

tPHL

OER to PARITY

CL

=

300pF(3)

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.

2557 tbl08

6.53

6

I DT54n 4FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION

TEST CIRCUITS FOR ALL OUTPUTS

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

2557 tbl 09
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

PULSE WIDTH

~ OV
~~V

j

__~~~ -

tsu ---t0j4--~

TIMING - - - - - - " "
INPUT

LOW-HIG~J~s~

-3V

- - - 1 - - - - - - 1.5V

-

OV

ASYNCHRONOUS CONTROL
PRESET - - - - - - - - , ~--~--~--------­ - 3V
- - + - - - - - - 1.5V
CLEAR
ETC.
- OV

=t-

HIGH-LaW-HIGH
PULSE

~ 1.5V
lw

--1.5V

SYNCHRONOUS CONTROL
CLOCK

:~~~~~ ~tsu
vvJr I
ETC.

--~~~

- 3V
-1.5V
- OV

PROPAGATION DELAY

I

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

-----3V
SAME PHASE
INPUT TRANSITION

3.5V
OUTPUT

VOL
VOH

SWITCH
OPEN

OPPOSITE PHASE
INPUT TRANSITION

OV
'------- - - - - OV
NOTES
2557 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-H IGH.
2. Pulse Generator for All Pulses: Rate:;; 1.0 MHz; Zo ~ son; tF ~ 2.Sns;
tR ~ 2.Sns.

6.53

7

I DT5417 4FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xxx
Temperature
Range

FCT

x

x

x

Device
Type

Package

Process/
Temperature
Range

1<-----11 ~Iank
P
D
'----------1 L
SO
E

'----------------j

Commercial (O°C to +70°C)
Military (-55°C to +125°)
Compliant to MIL-STD-883, Class B

J

Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC
CERPACK
Plastic Leaded Chip Carrier

833A
833B

Non-inverting Parity Bus Transceiver
Fast Non-inverting Parity Bus Transceiver

2557 drw 03

6.53

8

G

I DT54/74FCT841 AlBIC
IDT54/74FCT843A1B/C
IDT54/74FCT844A/B/C
IDT54/74FCT845A1B/C

HIGH-PERFORMANCE
CMOS BUS INTERFACE
LATCHES

Integrated Device Technology, Inc.

FEATURES:

•
•
•

•
•
•
•
•
•
•
•
•

DESCRIPTION:

Equivalent to AMD's Am29841-46 bipolar registers in
pinouUfunction, speed and output drive over full temperature and voltage supply extremes
IDT54/74FCT841A1843A1844A1845A equivalent to
FASTTM speed
IDT54/74FCT841 8/8438/8448/8458 25% faster than
FASTTM
IDT54/74FCT841C/843C/844C/845C 40% faster than
FASpM
Buffered common latch enable, clear and preset inputs
IOL = 48mA (commercial) and 32mA (military)
Clamp diodes on all inputs for ringing suppression
CMOS power levels (1 mW typo static)
TTL input and output level compatible
CMOS output level compatible
Substantially lower input current levels than AMD's
bipolar Am29800 series (5j1A max.)
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT800 series is built using advanced
CEMOSTM, a dual metal CMOS technology.
The IDT54/74FCT840 series bus interface latches are
designed to eliminate the extra packages required to buffer
existing latches and provide extra data width forwider addressl
data paths or buses carrying parity. The IDT54/74FCT841 is
a buffered, 1O-bit wide version of the popular '373 function.
The IDT54/74FCT843 and IDT54!74FCT844 are 9-bit wide
buffered latches with Preset (PRE) and Clear (CLR)-ideal for
parity bus interfacing in high-performance systems. The IDT541
74FCT845 is an 8-bit buffered latch with all the '843/4 controls,
plus multiple enables (OE1, OE2, OE3) to allow multiuser
control of the interface, e.g., CS, DMA and RD/WR. It is ideal
for use as an output port requiring high IOUIOH.
All of the IDT54/74FCT800 high-performance interface
family are deSigned for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in the high impedance state.

IDT54/74FCT844

FUNCTIONAL BLOCK DIAGRAM

Do

I DT54/74FCT841 1843/845

00

ON

ON

II

Yo

2607 cnv· 02

YN

PRODUCT SELECTOR GUIDE
Yo

YN

2607 cnv· 01

Device
10-Bit
Noninverting

9-Bit

a-Bit

IOT54174FCT841 IOT54174FCT843 IOT54174FCT845

AlBIC

AlBIC·

AlBIC

IOT54174FCT844

Inverting

CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of National Semiconductor Co.

2607 tbl 01

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1990 Integrated Device Technology. Inc.

AlBIC

6.54

JUNE 1990
DSC-4603/-

1

lOT 5417 4FCT841/843/844/845A1B/C
HIGH·PERFORMANCE CMOS BUS INTERFACE LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
IDT54/74FCT84110-BIT LATCH
OE

Vee

Do

08

Yo
Y1
Y2
Y3
Y4
Ys
Y6
Y7
Ya

[)g

yg

GND

LE

01
02

D3
04
05
06

D7

INDEX

LtYYLJW~~
1

L28.1

14 15 16

17

18

25[:
24[:
23[:
22[:
21 C:
20[:
19[:

Y2
Y3
Y4
NC
Ys
Y6
Y7

D~D

LE

LE _ _ _---J

Q~10
I

Y

I

OE - - - - - - - - '

nnnnnnn
o8~~~5!!~
G

LCC
TOP VIEW

DIP/CERPACK/SOIC
TOP VIEW

2607 cnv' 03,04,05

IDT54/74FCT843/844 9-BIT LATCHES
OE

Vee

Do

Yo
Y1
Y2
Y3
Y4
Ys
Y6
Y7
Ys
PRE
LE

D1
D2

D3
D4
Ds
06
D7
Ds
CLR
GND

INDEX

~
Cl

8po
80
Z ::>~:>=

UUUIIUUU
4 3 2"-: 2B 27 26
D4
NC
Ds
06
D7

L28·1

14 15 16 17 lB

25[:
24[:
23[:
22[:
21 C:
20[:
19[:

Y2
Y3
Y4
NC
Ys
Y6

Y7

D

Y

LE
PRE
CLR
OE

nnnnnnn

o. ,a:-,ZZ-'
Cl 0 W ,W
a: ;>?
0 G
Cl.

LCC
TOP VIEW

DIP/CERPACK/SOIC
TOP VIEW

2607 cnv' 06,07,OB

IDT54/74FCT845 8-BIT LATCH
OEl
082
Do
D1
D2

D:3
D4
Ds
06
07
CLR
GNO

Vee
0E3
Yo
Yl
Y2
Y3
Y4
Ys
Y6
Y7
PRE
LE

DIP/CERPACK/SOIC
TOP VIEW

INDEX

D1 :]5
D2 :]6

25[:
24[:
23[:
22[:
21 C:
20[:
19[:

D3 :]7
NC
D4
Ds
06

D

UUUI .L.1UU
432'-;'2B2726

:] B

L28-1

:J9
:] 10
:] 11
12 13 14 15 16 17 18

nnnnnnn
o - , 0Z z0 -W, IW >::

,a:o G

Y

LE
PRE
CLR
OE1
082

0E3

a:

Cl.

LCC
TOP VIEW

6.54

Yl
Y2
Y3
NC
Y4
Ys
Y6

2607 cnv' 09,10,11

2

IDT54f74FCT841/843/844/845A1B/C

HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION
Name

FUNCTION TABLE(1)
I DT54/74FCT841 /843/845

1/0

Description
IDT54/74FCT841 18431845 (Non-inverting)
CLR

I

When CLR is low, the outputs are LOW
if OE is LOW. When CLR is HIGH, data
can be entered into the latch.

Inputs
CLR PRE OE LE
H

H

X

Inter -

Out puts

01

nal
01

X

X

YI

Function

DI

I

The latch data inputs.

LE

I

H

H

H

H

L

L

Z

High Z

H

H

H

H

H

H

Z

High Z

H

H

H

L

X

NC

Z

Latched (High Z)

H

H

L

H

L

L

L

Transparent

H

H

L

H

H

H

H

Transparent

H

H

L

L

X

NC

NC

H

L

L

X

X

H

H

YI

0

The latch enable input. The latches are
transparent when LE is HIGH. Input
data is latched on the HIGH-to-LOW
transition.
The 3-state latch outputs.

OE

I

The output enable control. When OE is

PRE

I

LOW, the outputs are enabled. When
OE is HIGH, the outputs (YI) are in the
hiqh-impedance (off) state.
Preset line. When PRE is LOW, the
outputs are HIGH if OE is LOW. Preset
overrides CLR

IDT54/74FCT844 (Inverting)
CLR

I

DI

I

LE

I

YI

0

The latch enable input. The latches are
transparent when LE is HIGH. Input
data is latched on the HIGH-to-LOW
transition.
The 3-state latch outputs.

OE

I

The output enable control. When OE is

can be entered into the latch.
The latch inverting data inputs.

I

L

H

L

X

X

L

L

Clear

L

L

X

X

H

H

Preset

L

H

H

L

X

L

Z

Latched (High Z)

H

L

H

L

X

H

Z

Latched (High Z)
2607 tbl 03

= No Charge,

FUNCTION TABLE(1)
IDT54/74FCT844

LOW, the outputs are enabled. When
OE is HIGH, the outputs (VI) are in the
PRE

Latched
Preset

L

NOTE:
1. H = HIGH, L = LOW, X = Don't Care, NC
Z = High-Impedance

When CLRis low, the outputs are LOW
if OE is LOW. When CLR is HIGH, data

Z

High Z

H

high-imRedance (off) state.
Preset line. When PRE is LOW, the
outputs are HIGH if OE is LOW. Preset
overrides CLR
2607tbl02

Inputs
CLR PRE OE LE

Inter -

Out puts

01

nal
01

H

H

H

X

X

X

Z

H

H

H

H

H

L

Z

High Z

H

H

H

H

L

H

Z

HighZ

H

H

H

L

X

NC

Z

Latched (High Z)

H

H

L

H

H

L

L

Transparent
Transparent

Function

I

I

High Z

H

H

L

H

L

H

H

H

H

L

L

X

NC

NC

H

L

L

X

X

H

H

Preset

L

H

L

X

X

L

L

Clear

L

L

L

X

X

H

H

Preset

L

H

H

L

X

L

Z

Latched (High Z)

H

L

H

L

X

H

Z

Latched (High Z)

NOTE:
1. H = HIGH, L = LOW, X = Don't Care, NC
Z = High-Impedance

6.54

VI

Latched

2607 tbl 04

= No Charge,

3

I

IDT54f7 4FCT841/843/844/845A1B/C
MILITARY AND COMMERCIAL TEMPERATURE RANGES

HIGH·PERFORMANCE CMOS BUS INTERFACE LATCHES

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
VTERM(2) Terminal Voltage -0.5 to +7.0
with Respect to
GND
VTERM(3) Terminal Voltage
-0.5 to Vee
with Respect to
GND

C APA CI TAN CE (TA =

Military

Unit

-0.5 to +7.0

V

-0.5 to Vee

V

Parameter

+25°C, f = 1.0MHz)
Max.

Unit

CIN

Input
Capacitance

VIN = OV

6

10

pF

CoUT

Output
Capacitance

VOUT = OV

8

12

pF

Symbol

(1)

Typ.

Conditions

26071b106
NOTE:
1. This parameter is measured at characterization but not tested.

TA

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output
Current

120

120

mA

NOTE:
26071b105
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +O.5V unless otherwise noted.
2. Input and Vcc terminals only.
3. Outputs and 110 terminals only.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = O.2V; VHC = Vcc - O.2V
Commercial: TA = O°C to +70°C, vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc= 5.0V
Symbol

(1)

± 10%
Typ.

Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

V

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

0.8

V

IIH

Input HIGH Current

Vee = Max.

VI = \k::e

-

5
5(4)

~A

VI = 2.7V

-

IlL

Input LOW Current

10ZH

Parameter

Off State (High Impedance)

Test Conditions

Vee = Max.

Output Current
10ZL

-

-

_5(4)

VI = GND

-

-

-5

Vo= Vee

-

-

Vo= 2.7V

-

10
10(4)

VO= 0.5V

-

-

-10(4)

Vo=GND

-

-

Clamp Diode Voltage

Vee = Min., 1N=-18mA

los

Short Circuit Current

Vee = MaxP), Va = GND

VOH

Output HIGH Voltage

Vee = 3V. VIN = VLe or VHe. 10H = -321lA

= Min.

VOL

Output LOW Voltage

-10

-0.7

-75

-120

-

mA
V

-1.2

VHe

Vee

-

VHe

Vee

-

2.4

4.3

-

10H = -24mA COM'L.

2.4

4.3

Vee = 3V. VIN = VLe or VHe, 10L =

300~A

GND
GND

VLe
VLd 4)

10L = 300~A

-

VIN = VIH or VIL

10L = 32mA MIL.

-

0.3

0.5

10L = 48mA COM'L.

-

0.3

0.5

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vec = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

V

-

-

Vee = Min.

6.54

~A

-

= -3OOIlA
10H = -15mA MIL.
10H

VIN = VIH or VIL

(2)

VI = 0.5V

VIK

Vee

Min.

V

2607 tbl06

4

IDT5417 4FCT841f843f844f845A1BfC
HIGH·PERFORMANCE CMOS BUS INTERFACE LATCHES

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = O.2V; VHC = VCC - O.2V
Symbol
Icc
!llcc
Iceo

TypP)

Max.

Unit

Quiescent Power Supply Current

Vcc = Max.
VIN> VHC' VIN < VLC

-

0.2

1.5

mA

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

-

0.5

2.0

mA

VIN ~ VHC
VIN ~ VLC

-

0.15

0.25

VIN ~ VHC

-

1.7

4.0

VIN =3.4V
VIN =GND

-

2.0

5.0

Vcc = Max.
Outputs Open

VIN ~ VHC
VIN ~ VLC

-

3.2

6.5(5)

Ii = 2.5MHz

(FCT)

-

5.2

14.5(5)

Test Condltions(1)

Parameter

Dynamic Power Supply
Current(4)

Vcc = Max.
Outputs Open
OE = GND

Min.

mA!
MHz

LE = Vcc
One Input Toggling
50% Du~ Cycle
Ic

Total Power Supply Curren~6)

Vcc = Max.
Outputs Open
Ii = 10MHz
50% Duty Cycle
OE = GND
LE = Vcc
One Bit Toqqlinq

mA

VIN ~ VLC
(FCT)

50% Duty Cycle
OE = GND

VIN = 3.4V

LE = Vcc

VIN = GND

EiQht Bits TOQQlinQ
NOTES:
1. For conditions shown as Max. or Mn., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCc = 5.0V, +25°C ambient.
3. Per TTL driven input (V IN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + lilcc DHNT + ICCD (fcpf2 + fiN i)
Icc = Quiescent Current
lilcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.54

2607 tbl08

I

5

IDT54174FCT841/843/844/845A18/C
HIGH-PERFORMANCE CMOS 8US INTERFACE LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT841AI

IDT54174FCT84181

IDT54174FCT841CI

843A1844A1845A

8438/8448/8458

843C/844C/845C

Com'l.

Com'l.

Test
Parameter

Description

Conditions

(1) Mln.(2)

(FCT841,
843,84S)

Propagation Delay

CL = SOpF

DltoVI

RL =

tPLH

(LE = HIGH)

CL = 300pp3)

tPHL

(FCT844)
tPLH

soon

RL =

soon

Propagation Delay

CL = SOpF

DltoVI

RL =

soon

CL = 300pp3)

(LE = HIGH)

tPHL

RL =

soon

Max.

Mil.
Mln.(2)

Max.

Mil.
Mln.(2)

Max.

Unit
ns

6.S

-

7.S

-

S.S

-

6.3

-

13.0

-

1S.0

-

13.0

-

1S.0

-

13.0

-

1S.0

-

10.0

-

12.0

-

8.0

-

9.0

-

7.0

-

8.0

-

13.0

-

1S.0

-

13.0

-

1S.0

-

13.0

-

1S.0

CL = SOpF

2.S

-

2.S

soon

2.S

-

3.0

tPLH

Propagation Delay

CL = SOpF

tPHL

LEto VI

soon

Mln.l.2)

-

RL

RL =

Com'l.

Max.

10.0

Data to LE Hold Time

soon

Min .(2)

-

Data to LE Set-up Time

RL =

Max.

9.0

tH

CL = 300pp3)

Min .(2)

-

tsu

=

Max.

Mil.

-

ns

-

2.S

-

2.S

-

2.S

2.S

-

ns

2.S

-

2.S

2.S

ns

2.S

ns

-

12.0

-

13.0

-

8.0

-

10.S

-

6.4

-

6.8

-

16.0

-

20.0

-

1S.S

-

18.0

-

1S.0

-

16.0

tPLH

Propagation Delay, PRE to VI

CL = SOpF

-

12.0

-

14.0

-

8.0

-

10.0

-

7.0

-

9.0

ns

tREM

Recovery Time PRE to VI

RL =

soon

-

14.0

-

17.0

10.0

-

13.0

-

9.0

-

12.0

ns

tPHL

Propagation Delay, CLR to VI

-

13.0

-

14.0

-

10.0

-

11.0

-

9.0

-

10.0

ns

tREM

Recovery Time CLR to VI

-

14.0

-

17.0

-

10.0

-

10.0

-

9.0

-

9.0

ns

tw

LE Pulse Width(3)

HIGH

CL = SOpF

4.0

-

S.O

4.0

ns

tw

PRE Pulse WidttP>

LOW

RL =

soon

s.o

-

7.0

4.0

-

tw

CLR Pulse Widtt!3>

LOW

4.0

-

s.o

4.0

-

ns

tPZH

Output Enable TimeOE to VI

ns

tPZL

CL = SOpF
RL =

soon

CL = 300pp3)
RL =
tPHZ
tPLZ

Output Disable TimeOE to VI

soon

CL = Spp3)
RL =

soon

CL = SOpF
RL =

soon

-

4.0

-

4.0

4.0

-

4.0

-

4.0

4.0

-

4.0

-

4.0

-

4.0

ns

-

11.S

-

13.0

-

8.0

-

8.S

-

6.S

-

7.3

-

23.0

-

2S.0

-

14.0

-

1S.0

-

12.0

-

13.0

-

7.0

-

9.0

-

6.0

-

6.S

-

S.7

-

6.0

-

8.0

-

10.0

-

7.0

-

7.S

-

6.0

-

6.3

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.

ns

2607 tbl09

6.54

6

I DT5417 4FCT841/843/844/845A1B/C
HIGH·PERFORMANCE CMOS BUS INTERFACE LATCHES

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION

TEST CIRCUITS FOR ALL OUTPUTS

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

2607 tbl 07
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

j

PULSE WIDTH

~..K._ _~

-= ~~V
-

OV

tsu --I'!4--~

- 3V
TIMING
X - - - t - - - - - - 1.5V
INPUT - - - - - - - '
- OV
ASYNCHRONOUS CONTROL

PRESET - - - -.....
CLEAR

-

--+------

ETC.

-

3V
1.5V
OV

lOW-HIG~~~~

=}

HIGH-lOW-HIGH
PULSE

_

~'5V
tw

--1.5V

SYNCHRONOUS CONTROL
CLOCK

:~~~~~ vvJr
j
~tsu

~..K.

_ _~

- 3V
-1.5V
OV

ETC.

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE
3V

3V

1.SV

SAME PHASE
INPUT TRANSITION

OV
3.5V

OUTPUT

VOL
VOL
VOH

SWITCH
OPEN

3V

OPPOSITE PHASE
IN PUT TRANSITION

OV
OV

NOTES
2607 drw 12
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo::; son; tF::; 2.5ns;
tR::; 2.5ns.

6.54

7

IOT54174FCT841/843/844/845A1B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES

MILITARY ANO COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT
XX
FCT
XXXX
TTe-m-p-.rR:;-"a-n-geDevice Type

X

X

Package

Process

y~lank
P
D
'---------1 E

L
SO
841A
843A
844A
845A
~------------l841B

843B
844B
845B
841C
843C
844C
845C
54
'--------------------------------------1 74

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
1O-Bit Non-Inverting Latch
9-Bit Non-Inverting Latch
9-Bit Inverting Latch
8-Bit Non-Inverting Latch
Fast 10-Bit Non-Inverting Latch
Fast 9-Bit Non-Inverting Latch
Fast 9-Bit Inverting Latch
Fast 8-Bit Non-Inverting Latch
Super Fast 1O-Bit Non-Inverting Latch
Super Fast 9-Bit Non-Inverting Latch
Super Fast 9-Bit Inverting Latch
Super Fast 8-Bit Non-Inverting Latch
-55°C to + 125°C
O°C to +70°C
2607 cny' 17

6.54

8

(~J
Integrated Device Technology, Inc.

HIGH-PERFORMANCE
CMOS BUS
TRANSCEIVERS

IDT54/74FCT861 AlBIC
IDT54/74FCT863A1B/C
IDT54174FCT864A/B/C

FEATURES:

DESCRIPTION:

• Equivalent to AMD's Am29861-64 bipolar registers in
pinouVfunction, speed and output drive over full temperature and voltage supply extremes
• IDT54/74FCT861N863N864A equivalent to FAST'"M
speed
• IDT54/74FCT861 8/8638/8648 25% faster than FASPM
• High-speed symmetrical bidirectional transceivers
• IOL = 48mA (commercial) and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1 mW typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than AM D's
bipolar Am29800 Series (5~ max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT800 series is built using advanced
CEMOSTM, a dual metal CMOS technology.
The I DT54/74FCT860 series bus transceivers provide
high-performance bus interface buffering for wide
data/address paths or buses carrying parity. The
IDT54/74FCT863/864 9-bit transceivers have NAND-ed
output enables for maximum control flexibility.
All of the IDT54!74FCT800 high-performance interface
family are designed for high-capacitance load drive capability
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in the highimpedance state.

FUNCTIONAL BLOCK DIAGRAMS
IDT54/74FCT861

I DT54/7 4FCT863/864

I
R1-Rg

Ro

DET
2610drw01

PRODUCT SELECTOR GUIDE
Device

I

l

Non-inverting

10-Bit

9-Bit

IOT54/74FCT861

IOT54/74FCT863

Inverting

IOT54/74FCT864
2610tbl01

CEMOS is a trademark of Integrated Device Techology. Inc.
FAST is a registered trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1990 Integrated Device Technology. Inc.

6.55

JUNE 1990
DSC-4620/·

1

I

IDT54174FCT861A/B/C, IDT54174FCT863A1B/C, IDT54174FCT864A1B/C
HIGH·PERFORMANCE CMOS BUS TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
IDT54/74FCT861 1 O·BIT TRANSCEIVER

OER
Ro
R1
R2
R3
R4
Rs
Rs
R7
Rs
R9
GND

Vee

INDEX

To
T1
T2
T3
T4
Ts
Ts
T7
Ts
T9
OET

R2
R3
R4
NC
Rs
Rs
R7

~olffi08

~

a:a:oz>~1L...JL..J L...JI

]S
JS
]7
JS
]9
] 10
] 11

IL...JL..J L....J

4321128272S
w
2S[
1
24[
23 [
J28·1
22[
L28·1
21 [
20 [
19[
12 13 14 1S 1S 17 18
,-, , . , ,-, r t ,-, ,.-, ,......,

T2
T3
T4
NC
Ts
Ts
T7

Ol Cl 0Il- Ol
a:a:ZZWI-Iex)

ex)

o

DlP/CERPACKlSOIC
TOP VIEW

0

LCC/PLCC
TOP VIEW

IDT54/74FCT863/864 9·BIT TRANSCEIVERS

OER1
Ro
R1
R2
R3
R4
Rs
Rs
R7
R8
OER2
GND

INDEX

Vee

To
T1
T2
T3
T4
Ts
Ts
T7
T8
OET2
OET1

~

IOC

u
owo u

L...J L...JL......JI

R2
R3
R4
NC
Rs
Rs
R7

~

a:a:Oz>~1IL...JL...JL...J

4 3 2 1 1282726
LJ
2S[
Js
1
24 [
J6
23 [
J7
J28-1
22 [
]s
L28-1
21 [
]9
20[
J10
] 11
19[
12 1314 1S 16 1718

T2
T3
T4
NC
Ts
T6
T7

,......,rt,......,~,......,,..,,-,

cI:1a:~C9~ ~I'=I~~
~~

DlP/CERPACKlSOIC
TOP VIEW

2610 drw 02

LCC/PLCC
TOP VIEW

6.55

2

IDT54174FCT861A/B/C, IDT54174FCT863A1B/C, IDT54/74FCT864A1B/C
HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS

PIN DESCRIPTION
Name

I/O

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE(1)
IDT54/74FCT861/863 (Non-Inverting)

Description

IDT54/74FCT861
OER
OET
RI
TI

I
I

110
110

Outputs

Inputs
When LOW in conjunction with OET HIGH
activates the RECEIVE mode.
When LOW in conjunction with OER HIGH
activates the TRANSMIT mode.
1a-bit RECEIVE input/output.
1a-bit TRANSMIT input/output.

IDT54/74FCT863/864
OERI

I

When LOW in conjunction with OETI HIGH
activates the RECEIVE mode.

OETI

I

When LOW in conjunction with OERI HIGH
activates the TRANSMIT mode.

RI

liD

9-bit RECEIVE input/output.

TI

liD

9-bit TRANSMIT input/output.

OET

OER

RI

TI

RI

TI

L

H

L

N/A
N/A

L

Transmitting

Function

H

Transmitting

L

H

H

N/A
N/A

H

L

N/A

L

L

N/A

Receiving

H

L

N/A
X

H

H

N/A

Receiving

High Z
X
Z
Z
H
H
NOTE:
2610 till 03
1. H = HIGH, L = LOW, Z = High Impedance, X = Don't Care, N/A = Not
Applicable.

FUNCTION TABLE(1)
IDT54/74FCT864 (Inverting)
Outputs

Inputs
2610 tbl 02

Function

OET

OER

RI

TI

RI

TI

L

H

L

N/A

N/A

H

Transmitting
Transmitting

L

H

H

N/A

N/A

L

H

L

N/A

L

H

N/A

Receiving

H

L

N/A

H

L

N/A

Receiving

High Z
X
X
Z
Z
H
H
NOTE:
2610tbl04
1. H = HIGH, L = LOW, Z = High Impedance, X = Don't Care, N/A = Not
Applicable.

LOGIC SYMBOLS
IDT54/74FCT861

IDT54/74FCT863/864

OET1

I

OET 2 - - - - - < ( t

10

T

9

T

OER1
OER2---U

6.55

3

IDT54174FCT861 AlBIC, IDT54174FCT863A1B/C, IDT54/74FCT864A1B/C
HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage

CAPACITANCE

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

Operating
Temperature

o to +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

= +25°C, f = 1.0MHz)
Conditions Typ.

Max.

Unit

CIN

Input Capacitance

VIN = oV

6

10

pF

ClIO

I/O Capacitance

VOUT = OV

8

12

pF

NOTE:
2610 ttl I 06
1. This parameter is guaranteed by characterization but not tested.

with Respect
toGND
TA

(TA

Parameter(1)

Symbol

NOTES:
2610 ttll 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +0.5V unless otherwise noted.
2. Inputs and Vee terminals only.
3. Outputs and 110 terminals only.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V, VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, vcc
Symbol

Test Conditions(1)

Parameter

= 5.0V ± 10%
Min.

Typ.(2)

-

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

IIH

Input HIGH Current

Vec = Max.

ilL

IIH

VI

= Vec

(Except 1/0 pins)

VI = 2.7V

Input LOW Current

VI

(Except 1/0 pins)

VI= GND

Input HIGH Current

Vee = Max.

VI

= 0.5V
= Vec

-

-

-

(1/0 pins Only)

VI = 2.7V

IlL

Input LOW Current

VI

VIK

Clamp Diode Voltage

Vee = Min., IN = -18mA

-

-0.7

los

Short Circuit Current

Vec = Max.(3), Va = GND

-75

-120

VOH

Output HIGH Voltage

Vee = 3V, VIN = VLe or VHe, 10H = -321lA

VHC

Vee

Vce = Min.

10H = -3001lA

VHC

Vee

VIN = VIH or VIL

10H = -15mA MIL.

2.4

4.3

10H = -24mA COM'L.

2.4

(110 pins Only)

VOL

Output LOW Voltage

= 0.5V

VI = GND

Vee = 3V, VIN = VLe or VHe, 10L = 300llA
Vee = Min.

10L = 300llA
10L = 32mA MIL.(5)

VIN = VIH or VIL

10L = 48mA COM'L.(5)

-

-

4.3
GND

Max.

Unit

-

V

0.8

V

5
5(4)

IlA

_5(4)

Il A

-5
15
15(4)
_15(4)
-15
-1.2

V

-

mA
V

-

GND

VLe
VLC(4)

0.3

0.5

0.3

0.5

V

NOTES:
2610 ttll 07
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. These are maximum 10L values per output, for 10 outputs turned on simultaneously. Total maximum IOL (all outputs) is 480mA for commercial and 320mA
for military. Derate IOL for number of outputs exceeding 10 turned on simultaneously.
6.55

4

IDT54n4FCT861A/B/C, IDT54n4FCT863A1B/C, IDT54/74FCT864A1B/C
HIGH·PERFORMANCE CMOS BUS TRANSCEIVERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC

= O.2V; VHC = VCC - O.2V
Typ.(2)

Max.

Unit

Icc

Quiescent Power
Supply Current

Vee = Max ..
VIN ~ VHC ; VIN ~ VLC

-

0.2

1.5

mA

~Icc

Quiescent Power Supply
Current TIL Inputs HIGH

Vcc= Max.
VIN = 3.4V(3)

-

0.5

2.0

mA

ICCD

Dynamic Power Supply Current(4)

Vcc = Max., Outputs Open
OER or OET = GND
One Input Toggling
50% Duty Cycle

VIN ~VHC
VIN ~ VLC

-

0.15

0.25

mAl
MHz

Ic

Total Power Supply Current(6)

Vcc = Max., Outputs Open
fi=10MHz
SO% Duty Cycle

VIN ~VHC
VIN ~ VLC
(FCT)

-

1.7

4.0

mA

OER or OET = GND
One Bit Toggling

VIN = 3.4V
VIN = GND

-

2.0

5.0

Vcc = Max., Outputs Open
fi = 2.SMHz
SO% Duty Cycle

VIN~VHC

-

3.2

6.S(5)

VIN ~ VLC
(FCT)

OER or OET = GND
Eight Bits Toggling

VIN = 3.4V
VIN = GND

-

5.2

14.5(5)

Symbol

Parameter

Test Conditlons(l)

Min.

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (V IN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT +IINPUTS + IDYNAMIC
Ic = Icc + ~lccDHNT + ICCD(fcp/2 + fNi)
Icc =Quiescent Current
Alcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
Iceo = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at Ii
All currents are in milliamps and all frequencies are in megahertz.

6.55

2610tbiOS

5

IDT54174FCT861 AlBIC, I DT54174FCT863A1B/C, IDT54/74FCT864A1B/C
HIGH·PERFORMANCE CMOS BUS TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT861 A/863A/864A
Symbol
tPLH
tPHL

Parameter
Propagation Delay
AI to TI or TI to RI
FCT861/863

tPLH
tPHL

Propagation Delay
AI to TI or TI to RI
FCT864

tPZH
tPZL

Output Enable Time
OETto Tlor
OERto RI

tPHZ

Output Disable

tPLZ

Time OET to TI or
OERto RI

FCT8618/8638/8648

Mil.

FCT861 C/863C/864C

Mil.

Com'/.
Mi/'
Conditlon(1) Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Min.(2) Max. Unit
Com'/.

= 50pF
= soon
CL = 300pF(3)
RL = soon
CL = 50pF
RL = soon
CL = 300pF(3)
RL = soon
CL = 50pF
RL = soon
CL = 300pF(3)
RL = soon
CL = 5pF(3)
RL = soon
CL = 50pF
RL = soon

CL
RL

Com'/.

-

8.0

-

9.0

-

6.0

-

6.5

-

-

-

-

ns

-

15.0

-

17.0

-

13.0

-

14.0

-

-

-

-

ns

-

7.5

-

9.0

-

5.5

-

6.5

-

-

-

-

ns

-

14.0

-

16.0

-

13.0

-

14.0

-

-

-

-

ns

-

12.0

-

13.0

-

8.0

-

9.0

-

-

-

-

ns

-

20.0

-

22.0

-

15.0

-

16.0

-

-

-

-

ns

-

9.0

-

9.0

-

6.0

-

7.0

-

-

-

-

ns

-

10.0

-

10.0

-

7.0

-

8.0

-

-

-

-

ns

NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter guaranteed but not tested.

2610 tbl 09

6.55

6

IDT54f74FCT861A/B/C, IDT54f74FCT863A1B/C, IDT54/74FCT864A1B/C
HIGH·PERFORMANCE CMOS BUS TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vee

SWITCH POSITION
0-.7.0V

soon

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2610tbll0
CL = Load capacitance: includes jig and probe capacitance.
Rr = Termination resistance: should be equal to Zour of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zxt

1

PULSE WIDTH

___..K._ _~

--= OV~~V
-

tsu----t~-~

TIMING
INPUT

LOW-HIG~UL~~

- 3V
V
_

6J

ASYNCHRONOUS CONTROL
PRESET - - - - ,
CLEAR
ETC. - - - - ,
SYNCHRONOUS CONTROL

P~E~f~

CLOCK ENABLE
ETC.

zzt

-

3V

-

OV

-

3V

HIGH-LOW-HIGH
PULSE

- - + - - - - - - 1.5V

1

___..K.__

~

=t-

~ 15V
t.

_ _ 1.5V

-1.5V
OV

tsu

PROPAGATION DELAY

I

ENABLE AND DISABLE TIMES
ENABLE

DISABLE
3V

3V
SAME PHASE
INPUT TRANSITION
3.5V
OUTPUT

VOL
VOL
OUTPUT
NORMALLY
HIGH

3V
OPPOSITE PHASE
INPUT TRANSITION

VOH
SWITCH
OPEN
OV

OV

NOTES
2610drw05
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ son; tF ~ 2.5ns;
tA ~ 2.5ns.

6.55

7

I OT5417 4FCT861 AlBIC, IDT54174FCT863A1B/C, IDT54/74FCT864A1B/C
HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xx

Temperature
Range

FCT XXXX
Device
Type

X

x

Package

Process

~~Iank
P
D

~

______________~ E
J
L

SO
861A
861B
861C
863A
' - - - - - - - - - - - - - - - l 863B
863C
864A
864B
864C
~__________________________~J54

174

6.55

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Plastic Leaded Chip Carrier
Leadless Chip Carrier
Small Outline IC
1a-Bit Non-inverting Transceiver
Fast 1a-Bit Non-inverting Transceiver
Super Fast 10-Bit Non-inverting Transceiver
9-Bit Non-inverting Transceiver
Fast 9-Bit Non-inverting Transceiver
Super Fast 9-Bit Non-inverting Transceiver
9-Bit Inverting Transceiver
Fast 9-Bit Inverting Transceiver
Super Fast 9-Bit Inverting Transceiver
-55°C to + 125°C
0° to +70°C

2610 drw 04

8

(~5
Integrated Device Technology, Inc.

ADV ANCE INFORMATION
IDT54/74FBT240
I DT54/74FBT240A
IDT54/74FBT240C

HIGH-SPEED BiCMOS
OCTAL BUFFER/LINE
DRIVER

FEATURES:

DESCRIPTION:

•
•
•
•

The FBT series of BiCMOS Octal Buffers and Line Drivers
are built using advanced BiCEMOSTM, a dual metal BiCMOS
technology. This technology is designed to supply the highest
device speeds while maintaining CMOS power levels.
The FBT series of bus interface devices are ideal for use in
designs needing to drive large capacitive loads with low static
(DC) current loading. All data inputs have a 200mV typical
input hysteresis for improved noise rejection.

•
•
•
•

IDT54/74FBT240 equivalent to 54/74BCT240
IDT54/74FBT240A 25% faster than the 240
IDT54174FBT240C 10% faster than the 240A
Significant reduction in ground bounce from standard
CMOS devices
TIL compatible input and output levels
±10% power supply for both military and commercial
grades
JEDEC standard pinout for DIP, SOIC and LCC
packages
Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

OEB
DAo

OAo

OBo

DBo

DAl

OAl

OBl

DBl

DA2

OA2

OB2

DB2

OEA

Vce

DAo
OBo
DAl
OBl
DA2
OB2
DA3
OB3
GND

OEB
OAo
DBo
OAl
DBl
OA2
DB2
OA3
DB3
__

D1P/SOIC/CERPACK
TOP VIEW

iii
I

DA3

OA3

OB3

DB3


0

INDEX

]
]
]
]
]

4

5
6

I

L...J L......J

2 ' , 20 19

~

18 [

L20-2

17 [
16 [

7

15 [

8

14 [

OAo
DBo
OAl
OBl
OA2

9 1011 1213
r-I 1"1 r I 11 r I

Lce

2644 drw 02

TOP VIEW

BiCEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1990 Integrated Device Technology, Inc.

6.56

JUNE 1990
DSC-0006/·

1

IDT54174FBT240/AIC
HIGH·SPEED BiCMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE(1)

PIN DESCRIPTION
Pin Names

Description

OEA,OEB

3-State Output Enable Inputs (Active LOW)

Inputs

Dxx
Oxx

OEA,OEB

D

Output

Inputs

L

L

H

Outputs

L

H

L

H

X

Z

2644 tbl 01

NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM

Rating
Terminal Voltage
with Respect
to GND

CAPACITANCE

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

TA

Operating
Temperature

a to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

(TA

2644 tbl 02

= +25°C, f = 1.0MHz)

Parameter(1)

Typ.

Unit

CIN

Input Capacitance

VIN = OV

6

pF

COUT

Output
Capacitance

VOUT = OV

8

pF

Symbol

Conditions

NOTE:
2644 tbl 05
1. This parameter is measured at characterization but not tested.

NOTE:
2644 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may aHect reliability. No terminal voltage may exceed
Vee by +O.5V unless otherwise noted.

6.56

IDT54174FBT240/AiC
HIGH-SPEED BiCMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 10%; Military: TA
Symbol

= -55°C to + 125°C, Vcc = 5.0V ± 10%

Test Condltlons(1)

Parameter

Min.

Typ.(2)

Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

V

Vil

Input LOW Level

Guaranteed Logic LOW Level

-

-

0.8

V

-

10

IlA

-10

Il A

50

Il A

-

-50

hH

Input HIGH Current

Vee = Max., VI = 2.7V

-

III

Input LOW Current

Vee = Max., VI = 0.5V

-

lozH

High Impedance

Vee = Max.

IOZl

Output Current

Va = 2.7V

-

Va = 0.5V

II

Input HIGH Current

Vee = Max., VI = 5.5V

-

VIK

Clamp Diode Voltage

Vee = Min., IN = -18mA

-

los

Short Circuit Current

Vee = Max., Va = GND(3)

-75

-

VOH

Output HIGH Voltage

2.4

3.3

-

V

2.0

3.0

-

V

-

0.3

-

200

Vee = Min.

IOH = -12mA MIL.

VIN = VIH or Vil

10H = -15mA COM'L.
10H = -18mA MIL.

Val

Output LOW Voltage

-

100

-0.7

Il A

-1.2

V

-225

mA

10H= -24mA COM'L.
IOl = 48mA MIL.

0.55

V

IOL = 64mA COM'L.
VH

Input Hysteresis

Vee = 5V

IOFF

Bus Leakage Current

Vee = OV, Vo = 4.5V

Icc

Quiescent Power
Supply Current

Vee = Max.
VIN = GND or Vee

-

mV

-

100

IlA

0.2

1.5

mA

NOTES:

26441b103

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

I

6.56

3

IDT54174FBT240/A/C
HIGH-SPEED BiCMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol
~Ice

Parameter
Quiescent Power Supply
Current (Inputs TTL HIGH)

IceD

Dynamic Power Supply
Current(4)

Ie

Total Power Supply
Current(6)

Typ.(2)

Max.

Unit

-

-

2.0

mA

= Vee
= GND

-

-

0.2S

mAl
MHz

= Vee
= GND
VIN = 3.4V
VIN = GND
VIN = Vce
VIN = GND
VIN = 3.4V
VIN = GND

-

-

4.0

mA

-

-

S.O

-

-

6.S(5)

-

-

14.S(5)

Test Conditlons(1)

Min.

Vcc = Max.
VIN = 3.4v(3)
Vee = Max., Outputs Open
OEA = OEe = GND
One Input Toggling
SO% Duty Cycle

VIN
VIN

Vee = Max., Outputs Open
= 1OMHz, SO% Duty Cycle

VIN
VIN

fi

OEA = OEe = GND
One Bit Toggling
Vee = Max., Outputs Open
= 2.SMHz, SO% Duty Cycle

fi

OEA = OEe = GND
Eight Bits Toggling

NOTES.
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient, and maximum loading.
3. Per TTL driven input (V IN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + t.lcc DHNT + ICCD (lcp/2 + Ii Ni)
Icc = Quiescent Current
t.lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz

2644 tbl 06

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FBT240
Com'l.
Symbol

Parameter

IDT54/74FBT240A

Mil.

Com'l.

IDT54/74FBT240C
Com'l.

Mil.

Cond iUon(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.

Min.(2)

Mil.

Max. Min.!2) Max. Unit

1.S

S.6

-

-

1.S

4.8

-

-

1.S

4.3

-

-

ns

Output Enable Time

1.S

8.8

-

-

1.S

6.2

-

-

1.S

5.0

-

-

ns

Output Disable Time

1.5

8.1

-

-

1.5

5.6

-

-

1.S

4.5

-

-

ns

tPLH
tPHL

Propagation Delay
DntoOn

tPZH
tPZL
tPHZ
tPLZ

CL = SOpF
RL = soon

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

2644 tbl 07

6.56

4

I DT5417 4FBT240/ AlC
HIGH·SPEED BiCMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vcc

SWITCH POSITION
o...-7.0V

soon

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2644 tbl 08
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

J

PULSE WIDTH

~..K.~~

-=
-

nV
OV

tsu --Io!+---~

LOW-HIG~UL~~

- 3V
X----+------1.5V
-------'
- OV
ASYNCHRONOUS CONTROL
TIMING
INPUT

PRESET - - - - ,
CLEAR
ETC. - - - - ,

zzt

-

3V

-

OV

=t-

HIGH-LaW-HIGH
PULSE

- - + - - - - - - - 1.5V

~ 15V

'~

--1.5V

SYNCHRONOUS CONTROL

P~c~f~

CLOCK ENABLE
ETC.

J
tsu

"",,-..K.~~

- 3V
-1.5V
OV

PROPAGATION DELAY

I

ENABLE AND DISABLE TIMES
ENABLE

DISABLE
3V

3V
SAME PHASE
INPUT TRANSITION

OV
3.SV

OUTPUT

VOL
VOL
OUTPUT
NORMALLY
HIGH

3V
OPPOSITE PHASE
INPUT TRANSITION

VOH
SWITCH
OPEN
OV

OV
NOTES
2644 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ son; tF ~ 2.5ns;
tR ~ 2.5ns.

6.56

5

I

IDT54174FBT240/AIC
HIGH-SPEED BiCMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

xx

FBT

Temperature
Range

XXXX

X

x

Device Type

Package

Process

~~Iank
P

o

L . - - - - - - - - - - - - l SO

L
E

240
240A
1 240C

L - - - - - - - - - - - - - - - - - l1

~

______________________________~I 54
I 74

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Octal Buffer/Line Driver
High-Speed Octal Buffer/Line Driver
Very High-Speed Octal Buffer/Line Driver

-55°C to +125°C
O°C to +70°C
2644 drw 03

6.56

6

(;)®
Integr~ted

ADVANCE INFORMATION
IDT54/74FBT241
IDT54/74FBT241 A
IDT54/74FBT241 C

HIGH-SPEED BiCMOS
OCTAL BUFFER/LINE
DRIVER

Device Technology, Inc.

FEATURES:

DESCRIPTION:

•
•
•
•

The FBT series of BiCMOS Octal Buffers and Line Drivers
are built using advanced BiCEMOSTM, a dual metal BiCMOS
technology. This technology is designed to supply the highest
device speeds while maintaining CMOS power levels.
The FBT series of bus interface devices are ideal for use in
designs needing to drive large capacitive loads, with low static
(DC) current loading. All data inputs have a 200mV typical
input hysteresis for improved noise rejection.

•
•
•
•

IDT54/74FBT241 is equivalent to the 54/74BCT241
I DT54/74F BT241A Is 25% faster than the 241
IDT54/74FBT241C Is 10% faster than the 241A
Significant reduction in ground bounce from standard
CMOS devices
TIL compatible input and output levels
±10% power supply for both military and commercial
grades
JEDEC standard pinout for DIP, SOIC and LCC
packages
Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

PIN CON FIG URATIONS

OEB
DAo

OAo

OBo

DBo

DAI

OAI

OBI

DBI

DA2

OA2

OB2

DB2

DA3

OA3

OEA

Vee

DAo
OBo
DAI
OBI
DA2
OB2
DA3
OB3

OEB

OAo
DBo
OAI
DBI
0A2

DB2
OA3
DB3

GND

OB3

DIP/SOIC/CERPACK
TOP VIEW

II

INDEX

"T

DAI
OBI
DA2
OB2
DA3

DB3
2639 drw Ot

] 4
] 5
] 6

32: :20~
18
'1

17
L20·2
16
] 7
15
14
] 8
1011
1213
9 .,
,.....,
,.....,,.....,
,.....,

~~~0

DB2

I.........J

DA3

OA3

OB3

DB3

II

DIP/SOIC/CERPACK
TOP VIEW

DA1
OB1
OM
OB2
DA3

2645 drw 01

]
]
]
]

4
5
6
7

] 8

t........Il

1'---'

I

L......J

3 2 : : 20 19
18
l'
17
L20·2
16
15
14
9 10 11 1213

[
[
[
[
[

OAo
DBo
OA1
DB1
OM

nnnnn

~~~~&)
0,,00 0

2645 drw 02

Lce
TOP VIEW

BiCEMOS is

a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
0

32: :2019
A2
A3
A4

] 4
] 5
] 6

A5
A6

] 7
] 8

T

18 [
17 [
16 [

Bo
B1
B2

15 [
14 [
9 10 11 12 13
,-, n ,-, n ,-,

B3
B4

L20-2

~~lDcg(fl

B6

2646 drw 02

(!)

LCC
TOP VIEW

B7

BiCEMOS is a trademark of Integrated Device Technology Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1990 Integrated Device Technology, Inc.

6.59

JUNE 1990
DSC-601S/-

1

I

IDT54174FBT2451A1C
HIGH-SPEED BiCMOS NON-INVERTING BUFFER TRANSCEIVER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE(1}

PIN DESCRIPTION
Pin Names

Description

Inputs

OE

Output Enable Input (Active LOW)

TIR

TransmitlReceive Input

Ao-A7
Bo- B7

OE

TIR

Outputs

L

L

Bus B Data to Bus A

Side A Inputs or 3-State Outputs

L

H

Bus A Data to Bus B

Side B Inputs or 3-State Outputs

H

X

High Z State

2646 tbl 01

LOGIC SYMBOL

NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care

2646 tbl 02

TiR

OE
--..---LO ;)----f----1I~-

B

2640 drw 03

ABSOLUTE MAXIMUM RATINGS(1}
Symbol
VTERM

Rating
Terminal Voltage
with Respect
toGND

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

TA

Operating
Temperature

o to +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to + 135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

Parameter(1)

Typ.

Unit

CIN

Input Capacitance

VIN = OV

6

pF

COUT

Output
Capacitance

VOUT = OV

8

pF

Symbol

Conditions

NOTE:
2646 tbl 04
1. This parameter is measured at characterization but not tested.

NOTE:
2646 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +O.5V unless otherwise noted.

6.59

2

IDT54f74FBT245! AlC
HIGH-SPEED BiCMOS NON-INVERTING BUFFER TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 10%; Military: TA

= -55°C to +125°C, Vcc = 5.0V ± 10%
Min.

Typ.(2)

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

V

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

-

0.8

V

IiH

Input HIGH Current

Vee = Max.

Except I/O Pins

-

-

10

IlA

VI = 2.7V

I/O Pins

-

-

60

Vee = Max.

Except I/O Pins

-

I/O Pins

-

-

-10

VI = 0.5V

Symbol

ilL

Test Conditions(1)

Parameter

Input LOW Current

Max.

Unit

Il A

-60

-

II

Input HIGH Current

Vee = Max., VI = 5.5V

-

VIK

Clamp Diode Voltage

Vee = Min., IN = -18mA

-

los

Short Circuit Current

Vee = Max., Vo = GND(3)

-75

-

VOH

Output HIGH Voltage

Vee = Min.

10H = -12mA MIL.

2.4

3.3

-

V

VIN = VIH or VIL

10H = -15mA COM'L.
2.0

3.0

-

V

-

0.3

-

200

-

mV

-

100

0.2

1.5

IlA
mA

10H = -18mA MIL.

Il A

100
-1.2

V

-225

mA

-0.7

10H = -24mA COM'L.
VOL

Output LOW Voltage

10L = 48mA MIL.

0.55

V

10L = 64mA COM'L.
VH

Input Hysteresis

Vee = 5V

10FF

Bus Leakage Current
Quiescent Power
Supply Current

Vee = OV, Vo = 4.5V

Icc

Vee = Max.
VIN = GND or Vee

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

2646 tbl 05

II

6.59

3

IDT54174FBT245/A1C
HIGH-SPEED BiCMOS NON-INVERTING BUFFER TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol
~Iee

IceD

Ie

Parameter
Quiescent Power Supply
Current (Inputs TTL HIGH)

Test Conditlons(l)

Typ.(2)

Min.

Vee = Max.
VIN = 3.4v(3)

-

-

Max.
2.0

-

0.25

Dynamic Power Supply
Current(4)

Vee = Max., Outputs Open
OE = GND, T/R = GND or Vee
One Input Toggling
50% Duty Cycle

VIN
VIN

= Vee
= GND

-

Total Power Supply
Current(6)

Vee = Max., Outputs Open
fi = 1OMHz, 50% Duty Cycle

VIN = Vee
VIN = GND

-

-

4.0

T/R = OE = GND

VIN = 3.4V
VIN = GND

-

-

5.0

One Bit Toggling
Vee = Max., Outputs Open
fi = 2.5MHz, 50% Duty Cycle

VIN
VIN

= Vee
= GND
VIN = 3.4V
VIN = GND

-

-

6.5(5)

-

-

14.5(5)

T/R = OE = GND
Eight Bits Toggling

Unit
mA

mAl
MHz

mA

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient, and maximum loading.
3. Per TIL driven input (V IN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2+ fi Ni)
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

2646 tbl 06

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FBT245
Com'l.
Symbol

Parameter

IDT54/74FBT245A
Com'l.

Mil.

IDT54/74FBT245C
Com'l.

Mil.

Condition(l) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.

Min.(2)

Mil.

Max. Min.(2) Max. Unit

1.5

7.0

-

-

1.5

4.9

-

-

1.5

4.1

-

-

ns

Output Enable Time
OE to A or B

1.5

10.9

-

-

1.5

6.2

-

-

1.5

5.8

-

-

ns

tPHZ
tPLZ

Output Disable Time
OE to A or B

1.5

9.1

-

-

1.5

5.0

-

-

1.5

4.8

-

-

ns

tPZH
tPZL

Output Enable Time
T/Rto A or B

1.5

10.9

-

-

1.5

6.2

-

-

1.5

5.8

-

-

ns

tPHZ
tPLZ

Output Disable Time

1.5

9.1

-

-

1.5

5.0

-

-

1.5

4.8

-

-

ns

T/Rto Aor B

tPLH
tPHL

Propagation Delay
A to B, B to A

tPZH
tPZL

CL
RL

= 50pF
= 500n

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

2646 tbl 07

6.59

4

IDT54f74FBT2451A1C
HIGH·SPEED BiCMOS NON·INVERTING BUFFER TRANSCEIVER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION

Vee

500n

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2646 tbl 08
CL = Load capacitance: indudes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

J

PULSE WIDTH

~..M......M~

-= ~~V
-

OV

tsu --i>l+---+!

LOW-HIG~i~~

6S

TIMING
- 3V
INPUT _ _ _ _ _ _-'~~--+------_
V
ASYNCHRONOUS CONTROL
PRESET - - - - ,
CLEAR
ETC. _ _ _ _"

Z&t

-

--+------

3V
1.5V
OV

HIGH-LOW-HIGH
PULSE

=t-=

~ 1.5V

lw

--1.5V

SYNCHRONOUS CONTROL

P~E~f~

CLOCK ENABLE
ETC.

1
~..M.....M-"-"

tsu

- 3V
-1.5V
OV

PROPAGATION DELAY

I

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

,.----3V
- - -.... - - - - 3 V
SAME PHASE
INPUT TRANSITION

OUTPUT

'>----~+----OV

_--_.1--

3.5V

VOH

-1.5V

VOL

VOL
VOH

OPPOSITE PHASE
INPUT TRANSITION

SWITCH
OPEN

3V
' - - _ _oJ - - - -

OV

OV

NOTES
2646 drw 05
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate::; 1.0 MHz; Zo ::; son; tF ::; 2.5ns;
tR::; 2.5ns.

6.59

5

I DT5417 4FBT245! AlC
HIGH·SPEED BiCMOS NON·INVERTING BUFFER TRANSCEIVER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

XX

FBT

Temperature
Range

XXXX

X

x

Device Type

Package

Process

~~Iank
P

o

'--------------1

SO

L
E

I 245
245A

'--------------1

1

245C

' -_______________~I 54
I 74

Commercial
MIL·STD-883, Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Non·inverting Buffer Transceiver
High·Speed Non-inverting Buffer Transceiver
Very High-Speed Non-inverting Buffer Transceiver

-55°C to +125°C
O°C to +70°C
2646 drw 04

6.59

6

t;)®

ADVANCE INFORMATION
I DT54/74FBT373
IDT54/74FBT373A
IDT54/74FBT373C

HIGH-SPEED BiCMOS
OCTAL TRANSPARENT
LATCH

Integrated Devfce Technology, Inc.

FEATURES:

DESCRIPTION:

•
•
•
•

The FBT series of SiCMOS Octal Transparent Latches are
built using advanced SiCEMOSTM, a dual metal SiCMOS
technology. This technology is designed to supply the highest
device speeds while maintaining CMOS power levels.
The IDT54/74FST373 series are 3-state, 8-bit latches for
Sus Driving applications. The flip-flops appear transparent to
the data when Latch Enable (LE) is HIGH. When LE is LOW,
the data that meets the set-up times is latched. Data appears
on the bus when the Output Enable (OE) is LOW. When OE
is HIGH, the bus output is in the high impedance state.
The FBT series of bus interface devices are ideal for use in
designs needed to drive large capacitive loads with low static
(DC) current loading. All inputs have a 200mV typical input
hysteresis for improved noise rejection.

•
•
•
•
•

Functionally equivalent to 54/74SCT373
IDT54/74FBT373A 30% faster than the 373
IDT54/74FBT373C 15% faster than the 373A
Significant reduction in ground bounce from standard
CMOS devices
TIL compatible input and output levels
Low power in all three states
±10% power supply for both military and commercial
grades
JEDEC standard pinout for DIP, SOIC and LCC
packages
Military product compliant to MIL-STD-883, Class S

FUNCTIONAL BLOCK DIAGRAM

I
2597 drw 01

PIN CONFIGURATIONS
OE

Vee

00
00
01
01
02
02
03
03
GNO

o0 I~~ a

INOEX

07
07
06
06
05
05
04
04

~~II~~

3 2

01
01
02

O2
03

LE

]
]
]
]
]

4
5
6
7
8

19
18
17
L20-2
16
15
14
9 10 11 12 13
11 . , . , . , . . ,
I I 20
L.J

1

[ 07
[ 06
[ 06
[ 05
[ 05

8@~oo
(!)

DIP/SOIC/CERPACK
TOP VIEW

2597 drw 02

LeC
TOP VIEW

BiCEMOS is a tradermrk of Integrated Device Techology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES


INOEX

01
01
02
02
03

] 4
] 5
] 6

32: :2019
18
"1

17
L20·2
16
] 7
15
] 8
14
9 1011 1213

[
[
[
[
[

07
06
06
05
05

1"1r1"""''''''''

8

~ ~

0

2:)

2637 drw 02

C9

DIP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW

BiCEMOS is a trademark 01 Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
1i:l1990 Integrated Device Technology, Inc.

6.61

JUNE 1990
DSC-0002I·

1

IDT54f74FBT374/A1C
HIGH-SPEED BiCMOS OCTAL D REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE(1)

PIN DESCRIPTION
Pin Names

Description
The 0 flip-flop data inputs.

CP

Clock Pulse for the register. Enters data
on the LOW-to-HIGH transition.

00-07

The register three-state outputs.

OE

Output Control. An active-LOW three-state
control used to enable the outputs. A HIGH
level input forces the outputs to the high
impedance (off) state.

Function
Load
Register

VTERM

Terminal Voltage
with Respect
toGND

Clock

./"

.I
.I
./"

01
L
H
L
H

01
L
H

01
H
L
H
L

Z
Z

2637 tbl 02

CAPACITANCE (TA = +25°C, f = 1.0MHz)

ABSOLUTE MAXIMUM RATINGS(1)
Rating

OE
L
L
H
H

NOTE:
1. H = HIGH
L=LOW
X = Don't Care
Z = High Impedance
.I = LOW-to-HIGH Clock Transition

2637 tbl 01

Symbol

OUTPUTS INTERNAL

INPUTS

00-07

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

TA

Operating
Temperature

o to +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to + 150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

Parameter(1)

Typ.

Unit

CIN

Input Capacitance

VIN = OV

6

pF

COUT

Output
Capacitance

VOUT = OV

8

pF

Symbol

Conditions

NOTE:
2637 tbl 05
1. This parameter is measured at characterization but not tested.

NOTE:
2637 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may
exceed Vee by +O.5V unless otherwise noted.

6.61

2

IDT54174FBT374/A1C
HIGH·SPEED BiCMOS OCTAL D REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V +
- 10%; Military: TA

= ·55°C to +125°C, vcc = 5.0V ± 10%
Min.

Typ.(2)

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

Vil

Input LOW Level

Guaranteed Logic LOW Level

-

-

0.8

V

IIH

Input HIGH Current

Vee = Max., VI = 2.7V

-

-

10

JlA

·10

JlA

-

50

JlA

-

·50

Symbol

Test Conditions(l)

Parameter

Max.

Unit
V

II

Input HIGH Current

Vee = Max., VI = 5.5V

VIK

Clamp Diode Voltage

Vee = Min., IN = ·18mA

-

los

Short Circuit Current

Vee = Max., Vo = GNO(3)

·75

·150

2.4

3.3

-

V

VOH

Output HIGH Voltage

2.0

3.0

-

.V

-

0.3
200

III

Input LOW Current

Vee = Max., VI = 0.5V

10ZH

High Impedance

Vee = Max.

10Zl

Output Current

Va = 2.7V
Vo= 0.5V

Vee = Min.

IOH = ·12mA MIL.

VIN = VIH or Vil

IOH = ·15mA COM'L.
IOH = ·18mA MIL.

100

JlA

·0.7

·1.2

V

·225

mA

IOH = ·24mA COM'L.
VOL

Output LOW Voltage

IOl = 48mA MIL.

V

0.55

IOl = 64mA COM'L.

-

VH

Input Hysteresis

Vee = 5V

-

10FF

Bus Leakage Current

Vee = OV, Vo = 4.5V

-

-

100

JlA

lee

Quiescent Power
Supply Current

Vee = Max.
VIN = GNO or Vee

-

0.2

1.5

mA

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

mV

26371b103

II

6.61

3

IDT54174FBT374/A1C
HIGH-SPEED BiCMOS OCTAL 0 REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol

Test Condltlons(l)

Parameter

Typ.!2)

Max.

Unit

-

-

2.0

rnA

= Vee
= GND

-

-

0.2S

mAl
MHz

Vee = Max., Outputs Open
fep = 1OM Hz, SO% Duty Cycle

VIN = Vee
VIN = GND

-

-

4.0

rnA

OE = GND
One Bit Toggling at fi

VIN = 3.4V
VIN = GND

-

-

S.O

= Vee
= GND
VIN = 3.4V
VIN = GND

-

-

7.8(5)

-

-

16.8(5)

Min.

L'1lee

Quiescent Power Supply
Current (Inputs TIL HIGH)

Vee = Max.
VIN = 3.4v(3)

IceD

Dynamic Power Supply
Current(4)

Vee = Max., Outputs Open
OE = GND
One Input Toggling
SO% Duty Cycle

VIN
VIN

Ie

Total Power Supply
Current(6)

= SMHz

SO% Duty Cycle
Vee = Max., Outputs Open
SO% Duty Cycle
OE = GND
Eight Bits Toggling at fi

VIN
VIN

= 2.SMHz,

SO% Duty Cycle
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vec = 5.0V, +25°C ambient, and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcP/2 + fi Ni)
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (V IN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

2637 tbl 06

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FBT374
Com'l.
Symbol

Parameter

IDT54/74FBT374A

Mil.

Com'l.

IDT54/74FBT374C

Mil.

Com'l.

Conditlon(1) Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max.

Mln.(2)

Mil.

Max. Mln.(2) Max. Unit

2.0

10.0

-

-

2.0

6.5

-

-

-

S.2

-

-

ns

Output Enable
Time

1.5

12.3

-

-

1.5

6.5

-

-

-

5.5

-

-

ns

tPHZ
tPLZ

Output Disable
Time

1.5

6.8

-

-

1.5

5.5

-

-

-

5.0

-

-

ns

tsu

Set-up Time HIGH
or LOW Dn to CP

6.5

-

-

-

2.0

-

-

-

2.0

-

-

-

ns

tH

Hold Time HIGH
or LOW Dn to CP

0

-

-

-

1.5

-

-

-

1.5

-

-

-

ns

tw

CP Pulse Width
HIGH or LOW

7.0

-

-

-

S.O

-

-

-

5.0

-

-

-

ns

tPLH
tPHL

Propagation Delay
CP to On

tPZH
tPZL

CL = SOpF
RL = 500n

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

2637 tbl 07

6.61

4

IDT54f74FBT374/A1C
HIGH-SPEED BiCMOS OCTAL D REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

2637 Ibl 08
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA z z t .
INPUT

1

PULSE WIDTH

~..K...K~

TIMING
INPUT

=t

--= ~~V
-

OV

-

3V
1.SV
OV

tsu -4'14--~

---i------

lOW-HIG~i~~

ASYNCHRONOUS CONTROL
PRESET - - - - - - - - ,
CLEAR
ETC.

- 3V
I--+----r-------- - + - - - - - - 1.SV
-

OV

HIGH-lOW-HIGH

~ 15V
_ _ 1.SV

lw

PULSE

SYNCHRONOUS CONTROL
CLOCK

:~~~~~ vvJr
~tsu
J

~..K...K~

ETC.

- 3V
-1.SV
OV

PROPAGATION DELAY

II

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

,-----~-----3V

SAME PHASE
INPUT TRANSITION

OUTPUT

'1--.......' -+----- OV

OV
3.SV

, - - - - - _ . .-f-- VOH
-1.SV

VOL

VOL
SWITCH
OPEN

3V
OPPOSITE PHASE
INPUT TRANSITION

VOH
OV

'------'-----OV

NOTES
2637 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate:s; 1.0 MHz; Zo:s; SOQ; tF:S; 2.Sns;
tR:S; 2.Sns.

6.61

5

IOT54174FBT374! AlC
HIGH·SPEED BiCMOS OCTAL D REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

xx

FBT

Temperature
Range

XXXX

X

x

Device Type

Package

Process

~~Iank
P

o

'-----------j

SO

L
E

I

Plastic DIP
CEROIP
Small Outline IC
Leadless Chip Carrier
CERPACK

374C

Octal 0 Register (3-state)
High-Speed Octal 0 Register (3-state)
Very High~Speed Octal 0 Register (3-state)

54
74

-55°C to + 125°C
O°C to +70°C

374

' - - - - - - - - - - - - j l1 374A

' -______________________________~I

Commercial
MIL·STO·883, Class B

2637 drw 03

6.61

6

t;)®
Integrated Device Technology, Inc.

ADVANCE INFORMATION
I OT54/74FBT540/541
IDT54174FBT540A/541 A
IDT54174FBT540C/541 C

HIGH-SPEED BiCMOS
OCTAL BUFFER/LINE
DRIVERS

FEATURES:

DESCRIPTION:

•
•
•
•

The FBT series of BiCMOS Octal Buffers and Line Drivers
are built using advanced BiCEMOSTM , a dual metal BiCMOS
technology. This technology is designed to supply the highest
device speeds while maintaining CMOS power levels.
The IDT54174FBT540 and IDT54/74FBT541 are similar in
function to the 54/74FBT240 and 54174 FBT241, respectively,
except that the inputs and outputs are on opposite sides of the
packages. This pinout arrangement allows for easier layout
and greater board density when designing output ports for
microprocessors.
The FBT series of bus interface devices are ideal for use in
designs needing to drive large capacitive loads with low static
(DC) current loading. All data inputs have a 200mV typical
.
input hysteresis for improved noise rejection.

•
•
•
•

IDT54/74FBT540/541 equivalent to 54/74BCT540/541
I DT54174FBT540/541A 25% faster than the 540/541
IDT54/74FBT540/541C10% faster than the 540/541 A
Significant reduction in ground bounce from standard
CMOS devices
TIL compatible input and output levels
±10% power supply for both military and commercial
grades
JEDEC standard pinout for DIP, SOIC and LCC
packages
Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAMS
OEA - - - - - - - - ,

OEs

OEA

OEs

00

->---+--- 00

01

-~--+---01

02

->---+--- 02

03

·~--+---03

04

>---+---04

05

~--+---Os

06

06

>---+---06

07

07

-">----+--- 07

00

00

01

01

02

02

03

03

04

04

Os

05

06
07

2636 drw Ot

IDT54/74 FCT540

IDT54/74FCT541

PIN CONFIGURATIONS
OEA
00
01
02
03
04
05
06
07
GNO

INDEX

Vee
OEs

32::2019

00
01
02
03
04

T

02 ] 4
D3 ] 5
D4 ] 6
D5 ] 7
D6 ] 8

as

9

18 [

17
L20-2 16
15
14
1011 1213

[
[
[
[

00
01
02
03
04

111'111r-'1ra

06
07

o~ooo

2636 drw02

C)

DIP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW

BiCEMOS is a trademark of Integrated Device Technology. Inc_

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1990 Integrated Device Technology, Inc_

6.62

APRIL 1990
DSC-6000/-

1

IDT54f74FBT540/A/C, IDT54/74FBT541/A/C
HIGH-SPEED BiCMOS OCTAL BUFFER/LINE DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE(1)

PIN DESCRIPTION
Pin Names

Description

Output

Inputs

OEA,OEB

3-State Output Enable Input (Active LOW)

00-07
00-07

541

OEA,OEB

D

540

Inputs

L

L

H

L

Outputs

L

H

L

H

H

X

Z

Z

26361b101

NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM
Terminal Voltage
with Respect
to GND

CAPACITANCE

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

TA

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

Symbol

(TA

2636 tbl 02

= +25°C, f = 1.0MHz)

Parameter(1)

Conditions

= OV

CIN

Input Capacitance

VIN

COUT

Output
Capacitance

VOUT = OV

Typ.

Unit

6

pF

8

pF

NOTE:
2636 tbl 04
1. This parameter is measured at characterization but not tested.

NOTE:
2636 tbl 03
1. Stresses greaterthan those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
Vee by +O.5V unless otherwise noted.

6.62

2

IDTS4f74FBT540/AlC,IDTS4/74FBT541/A/C
HIGH-SPEED BiCMOS OCTAL BUFFER/LINE DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 10%; Military: TA = -55°C to + 125°C, Vcc = 5.0V ± 10%
Min.

Typ.(2)

Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

V

Vil

Input LOW Level

Guaranteed Logic LOW Level

-

IIH

Input HIGH Current

Vee = Max., VI = 2.7V

-

III

Input LOW Current

Vee = Max., VI = O.5V

-

10ZH

High Impedance

Vee = Max.

-

10Zl

Output Current

-

-50

Symbol

Test Condltlons(l)

Parameter

0.8

V

10

~A

-10

~A

50

~A

II

Input HIGH Current

Vee = Max., VI = 5.5V

-

VIK

Clamp Diode Voltage

Vee = Min., IN = -18mA

-

los

Short Circuit Current

Vee = Max., Vo = GND(3)

-75

-

VOH

Output HIGH Voltage

Vee = Min.

IOH = -12mA MIL.

2.4

3.3

-

V

VIN = VIH or Vil

10H = -15mA COM'L.
2.0

3.0

-

V

-

0.3

-

200

-

100

~A

-

0.2

1.5

mA

Vo = 2.7V
Vo = 0.5V

10H = -18mA MIL.

~A

100

-0.7

-1.2

V

-225

mA

10H= -24mA COM'L.
VOL

Output LOW Voltage

10l = 48mA MIL.

0.55

V

10l = 64mA COM'L.
VH

Input Hysteresis

Vee = 5V

10FF

Bus Leakage Current

Vee = OV, Vo = 4.5V

Ice

Quiescent Power
Supply Current

Vee = Max.
VIN = GND or Vee

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

-

mV

26361b105

I

6.62

3

IDT54174FBT540/A/C, IDT54/74FBT541fAfC
HIGH·SPEED BiCMOS OCTAL BUFFER/LINE DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol

Test Conditions(l)

Parameter

Min.

Max.

Unit

-

2.0

mA

= Vee
= GND

-

-

0.25

mAl
MHz

= Vee
= GND
VIN = 3.4V
VIN = GND
VIN = Vee
VIN = GND
VIN = 3.4V
VIN = GND

-

-

4.0

mA

-

-

5.0

-

-

6.5(5)

-

-

14.5(5)

Quiescent Power Supply
Current (Inputs TIL HIGH)

Vee = Max.
VIN = 3.4V(3)

leeo

Dynamic Power Supply
Current(4)

Vee = Max., Outputs Open
OEA = OEB = GND
One Input Toggling
50% Duty Cycle

VIN
VIN

Ie

Total Power Supply
Current(6)

Vee = Max., Outputs Open
= 1OMHz, 50% Duty Cycle

VIN
VIN

fi

OEA = OEB = GND
One Bit Toggling
Vee = Max., Outputs Open
= 2.5MHz, 50% Duty Cycle

fi

OEA = OEB = GND
Eight Bits Toggling

Typ.(2)

-

~Iee

.

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient, and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcpf2 + fi Ni)
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.62

2636 tbl 06

4

IDT54n4FBT540/AlC, IDT54n4FBT541/A1C
HIGH·SPEED BICMOS OCTAL BUFFER/UNE DRIVERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR 'FBT 540
IDT54174FBT540

Symbol
tPLH
tPHL

Parameter
Propagation Delay
Dn to On

IDT54174FBT540A

Mil.

Com'l.

Mil.

Com'l.

IDT54174FBT540C

Mil.

Com'l.

Condltlon(1) Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. MIn.(2) Max. Unit
CL - 50pF
RL- soon

1.5

6.9

-

-

1.5

4.8

-

-

1.5

4.3

. tPZH
tPZL

Output Enable
Time

1.5

10.1

-

-

1.5

6.2

-

-

1.5

5.8

tPHZ
tPLZ

Output Disable
Time

1.5

8.5

-

-

1.5

5.6

-

-

1.5

5.2

-

-

ns

-

-

ns

-

ns

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR 'FBT 541
IDT54174FBT541

Symbol

Parameter

IDT54174FBT541 A

Mil.

Com'l.

Mil.

Com'l.

IDT54174FBT541 C

Mil.

Com'l.

Condltlon(1) Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Unit
1.5

8.2

-

-

1.5

4.8

-

-

1.5

4.1

-

-

ns

Output Enable
Time

1.5

10.7

-

-

1.5

6.2

-

-

1.5

5.8

-

-

ns

Output Disable
Time

1.5

8.6

-

-

1.5

5.6

-

-

1.5

5.2

-

-

ns

tPLH
tPHL

Propagation
Delay Dn to On

tPZH
tPZL
tPHZ
tPLZ

CL = 50pF
RL .. 500n

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

26361b107

I

6.62

5

IDT54f74FBT540/AlC, IDT54f74FBT541/A/C
HIGH-SPEED BICMOS OCTAL BUFFER/LINE DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vcc

SWITCH POSITION
0---.

7.0V

soon

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
26361b108
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

j

PULSE WIDTH

",,-~....JIoI~

-= ~~V
-

OV

tsu~'i4----r

,--+---- -_ 6JV
3V

lOW-HIG~~~S~

PRESET - - - - . . . . . ~--+---+---- - 3V
- - f - - - - - - 1.SV
CLEAR
- OV
ETC. - - - - "
SYNCHRONOUS CONTROL

HIGH-lOW-HIGH
PULSE

TIMING - - - - - -.....
INPUT _ _ _ _ _ _-'
ASYNCHRONOUS CONTROL

CLOCK

:~~~~~ ~Su
vvJr j
ETC.

=t-=-

~ 15V
lw

_ _ 1.SV

- 3V
-l.SV
~~_--.a

t

-

PROPAGATION DELAY

OV

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

_ - -.... - - - - 3 V
SAME PHASE
IN PUT TRANSITION

OUTPUT

~--"~

_--_-r--

+ - - - - OV
3.SV

VOH

-l.SV

VOL

VOL

OUTPUT SWITCH

3V

VOH

NORM~~~ OPEN

OPPOSITE PHASE
INPUT TRANSITION

OV
NOTES
2636 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ son; tF ~ 2.Sns;
tR ~ 2.Sns.

6.62

6

IDT54174FBT540/AlC, IDT54/74FBT541/A/C
HIGH-SPEED BiCMOS OCTAL BUFFER/LINE DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XX

----

FBT

Temperature
Range

XXXX

x

x

Device Type

Package

Process

~~Iank
P
D
' - - - - - - - - - - - ; SO
L
E
540
541
540A
L - - - - - - - - - - - - - - - - - l 541 A
540C
541 C

Commercial
MIL-STD-883. Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Octal Buffer/Line Driver
Octal Buffer/Line Driver
High-Speed Octal Buffer/Line Driver
High-Speed Octal BufferlLine Driver
Very High-Speed Octal BufferlLine Driver
Very High-Speed Octal BufferlLine Driver

L - - - - - - - - - - - - - - - - - - - - - - t 54

-55°C to +125°C
740°C to +70°C
2636 drw 03

I
I

6.62

7

t;)®

ADV ANCE INFORMATION
IDT54/74FBT821 A
IDT54/74FBT821 B
IDT54/74FBT821 C

HIGH-SPEED BiCMOS
10-BIT REGISTER

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• IDT54/74FBT821A equivalent to the 54174BCT821
• IDT54/74FBT821 B 25% faster than the 821 A
• IDT54174FBT821C 10% faster than the 821 B
• Significant reduction in ground bounce from standard
CMOS devices
• TTL compatible input and output levels
• Low power in all three states
• ±10% power supply for both military and commercial
grades
• JEDEC standard pinout for DIP, SOIC and LCC
packages
• Military product compliant to MIL-STD-883, Class B

The FBT series of BiCMOS registers are built using
advanced BiCEMOSTM, a dual metal BiCMOS technology.
This technology is designed to supply the highest device
speeds while maintaining CMOS power levels.
The I DT54/74FBT821A is a buffered, 10-bit wide version of
the '374/'574 function.
The FBT series of buffers are ideal for use in designs
needing to drive large capacitive loads with low static (DC)
current loading. All data inputs have a 200mV typical input
hysteresis for improved noise rejection.

FUNCTIONAL BLOCK DIAGRAM
08

09

Ya

Y9

CP
CLOCK

OE

OUTPUT
ENABLE

263B drw Ot

PIN CONFIGURATIONS
24
23

OE
00
01
02
03

2
3
4
5

04

&

05
06
07
08
09

GNO

P24-1.
024-1.
E24-1
5024-2

22
21
20
19
18
17

10
11
12

16
15
14
13

Vcc
Yo
Y1

L...J L-J L...J

4
02
03

Y2
Y3

04

Y4
Y5
Y6
Y7

NC
05
06
07

Y8
Y9

I

I

L...J L-J L...J

3 2 I 128 2726
LJ

J5
J6
J7
J8
J9
J10
J 11

1

25 [
24 [
23 [

Y2
Y3

J28-1
L28-1

22[

NC

21 [

Y5

20[
19[

Y6
Y7

Y4

12 13 14 1516 17 18

I I r I r-I . . , . . ,

CP
->-

263B drw 02

LCC/PLCC
TOP VIEW

DIP/SOIC/CERPACK
TOP VIEW

BiCEMOS is a trademark of Integrated Device Techology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©t990 Integrated Device Technology. Inc.

6.63

JUNE 1990
DSC-OOOS/-

1

IDT5417 4FBT821 AlBIC
HIGH-SPEED BICMOS 10-BIT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE(1}

PIN DESCRIPTION
Pin Names
Do-D9
OE
CP
YO-Y9

1/0
I
I

I

a

Output

Inputs

Description
The D flip-flop data inputs.

OE

01

CP

YI

Function

Three-state Output Enable input (Active
LOW).

H

L
H

z
z

Load

H

Clock Pulse for the register; enters data into
the register on the LOW-to-HIGH transition.

L

L

L

H

i
i
i
i

The register three-state outputs.

Data

L
H

NOTE:
1. H = HIGH
L=LOW
X = Don't Care
i = LOW-to-HIGH Transition
Z = High Impedance

26381b101

LOGIC SYMBOL

26381b102

Y

ABSOLUTE MAXIMUM RATINGS(1}
Symbol
VTERM

Rating
Terminal Voltage
with Respect
toGND

CAPACITANCE (TA = +25°C. f = 1.0MHz)

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

TA

Operating
Temperature

a to +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to + 150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

Parameter(l)

Typ.

Unit

CIN

Input Capacitance

VIN = OV

6

pF

COUT

Output
Capacitance

VOUT = OV

8

pF

Symbol

Conditions

NOTE:
26381b104
1. This parameter is measured at characterization but not tested.

I

NOTE:
26381b103
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may
exceed Vce by +O.5V unless otherwise noted.

6.63

2

IDT54174FBT821 AlBIC
HIGH-SPEED BICMOS 10-BIT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 10%; Military: TA

= -55°C to +125°C, Vcc = 5.0V ± 10%
Min.

Typ.(2)

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

Vil

Input LOW Level

Guaranteed Logic LOW Level

-

-

IIH

Input HIGH Current

Vee = Max., VI = 2.7V

-

III

Input LOW Current

Vee = Max., VI = 0.5V

10ZH

High Impedance

Vee = Max.

IOZl

Output Current

Symbol

Test Conditions(l)

Parameter

Vo = 2.7V
Vo = 0.5V

-

II

Input HIGH Current

Vee = Max., VI = 5.5V

-

Clamp Diode Voltage

Vee = Min., IN = -18mA

-

los

Short Circuit Current

Vee = Max., Vo = GND(3)

-75

-

VOH

Output HIGH Voltage

2.4

Vee = Min.

IOH = -12mA MIL.
IOH = -15mA COM'L.
IOH = -18mA MIL.

Unit

-

-

VIK

VIN = VIH or Vil

Max.

V

0.8

V

10

~A

-10

~A

50

~A

-50

-

~A

100
-1.2

V

-225

mA

3.3

-

V

2.0

3.0

-

V

-

0.3

0.5

V

-0.7

IOH= -24mA COM'L.
VOL

Output LOW Voltage

IOL = 32m A MIL.
IOl = 48mA COM'L.

VH

Input Hysteresis

Vee = 5V

-

200

-

IOFF

Bus Leakage Current

Vee = OV, Vo = 4.5V

-

100

~A

Icc

Quiescent Power
Supply Current

Vee = Max.
VIN = GND or Vee

-

0.2

1.5

mA

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

6.63

mV

2638 tbl 05

3

IDT54f74FBT821 AlBIC
HIGH·SPEED BiCMOS 10·BIT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPL V CHARACTERISTICS
Symbol

Test Conditions(1)

Parameter

Typ.(2)

Max.

Unit

-

-

2.0'

mAl

VIN = Vee
VIN = GND

-

-

0.25

mAl
MHz

Vee = Max., Outputs Open
fi = 1 OMHz, 50% Duty Cycle

VIN = Vee
VIN = GND

-

-

4.0

rnA

OE = GND
One Bit Toggling

VIN = 3.4V
VIN =GND

-

-

5.0

Vee = Max., Outputs Open
fi = 2.5MHz, 50% Duty Cycle

VIN = Vee
VIN= GND

-

-

7.8(5)

OE = GND
Eight Bits Toggling

VIN = 3.4V
VIN = GND

-

-

17.8(5)

t.lee

Quiescent Power Supply
Current (Inputs TTL HIGH)

Vee = Max.
VIN = 3.4 V(3)

leeD

Dynamic Power Supply
Current(4)

Vee = Max., Outputs Open
OE = GND
One Input Toggling
50% Duty Cycle

Ie

Total Power Supply
Current(6)

Min.

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specilied under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient, and maximum loading.
3. Per TTL driven input (VIN =3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fi Ni)
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.63

2638 till 06

4

IDT54174FBT821 AlBIC
HIGH-SPEED BiCMOS 10-BIT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FBT821A
Com'l.
Symbol

Parameter

IDT54/74FBT821 B

Mil.

IDT54/74FBT821 C

. Mil.

Com'l.

Com'l.

Condition(l) Min.(2) Max. Min.(2) Max. Min.(2) Max. Mln.(2) Max.

Min.(2)

Mil.

Max. Min.(2) Max.

Unit

-

10.0

-

-

-

7.5

-

-

-

6.0

-

-

ns

Output EnableTime
OEtoYI

-

12.0

-

-

-

8.0

-

-

-

7.0

-

-

ns

tPHZ
tPLZ

Output Disable
Time OE to YI

-

8.0

-

-

-

7.5

-

-

-

6.5

-

-

ns

tsu

Data to CP

-

7.0

-

-

ns

1.0

-

-

ns

Clock Pulse Width

-

1.0

tw

-

-

3.0

1.0

-

-

-

-

-

Data to CP

-

3.0

tH

tPLH
tPHL

Propagation Delay
Clock to YI
(OE = LOW)

tpz
tPZL

CL = SOpF
RL = soon

7.0

-

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

5.0

-

5.0

ns
26381b107

6.63

5

IOT5417 4FBT821 AlBIC
HIGH-SPEED BiCMOS 10-81T REGISTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vee

SWITCH POSITION
<>-7.0V

soon

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

2638 tbl 08
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zxt

PULSE WIDTH

-= ~~V

J

......_______ -

OV

tsu~0i4--~

TIMING
INPUT

LOW-HIG~UL~1

- 3V
V
_

6J

ASYNCHRONOUS CONTROL
PRESET - - - - ,
CLEAR
ETC. - - - - ,

-

3V

-

OV

--+------

=t-

HIGH-LOW-HIGH

1.5V

~ '.5V
Iw

_ _ 1.SV

PULSE

SYNCHRONOUS CONTROL
CLOCK

:~~~t~ ~tsu
vvJr
J

.-.,.___

....M:~

-

3V

-

1.5V
OV

ETC.

PROPAGATION DELAY

II

ENABLE AND DISABLE TIMES
ENABLE

DISABLE
3V

I

3V

SAME PHASE
INPUT TRANSITION

OUTPUT

3.SV

VOH
-1.SV

VOL

VOL
VOH

SWITCH
OPEN

3V

OPPOSITE PHASE
INPUT TRANSITION

OV
OV

NOTES
2638 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate $ 1.0 MHz; Zo $ son; tF $ 2.5ns;
tR $ 2.5ns.

6.63

6

IDT54174FBT821 AlBIC
HIGH-SPEED BiCMOS 10-BIT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xx

FBT

Temperature
Range

XXXX

X

x

Device Type

Package

Process

~~Iank
P
~______________~

D
SO

J
L

E
~

~

________________________

821B
I 821A
I 821C

~

______________________________~I 54
I 74

Commercial
MIL-STD-883. Class B
Plastic DIP
CERDIP
Small Outline IC
Plastic Leaded Chip Carrier
Leadless Chip Carrier
CERPACK
Non-inverting 1a-Bit Register
High-Speed Non-inverting 1a-Bit Register
Very High-Speed Non-inverting 1a-Bit Register

-55°C to +125°C
aoc to +7aoC
2638 drw 04

6.63

7

(;)®

HIGH-SPEED BiCMOS
9-BIT REGISTER

Integrated Device Technology, Inc.

ADV ANCE INFORMATION
IDT54/74FBT823A
IDT54/74FBT823B
IDT54/74FBT823C

FEATURES:

DESCRIPTION:

•
•
•
•

The FBT series of BiCMOS buffers and bus drivers are built
using advanced BiCEMOSTM, a dual metal BiCMOS
technology. This technology is designed to supply the highest
device speeds while maintaining CMOS power levels.
The IDT54n4FBT823 is a 9-bit wide buffered register with
Clock Enable (EN) and Clear (CLR). The '823 is ideal for parity
bus interfacing in high-peformance microprogrammed
systems.
The FBT series of buffers are ideal for use in designs
needing to drive large capacitive loads with low static (DC)
current loading. All data inputs have a 200mV typical input
hysteresis for improved noise rejection.

•
•
•
•
•

IDT54/74FBT823A equivalent to 54/74BCT823A
IDT54/74FBT823B 25% faster than the 823A
IDT54/74FBT823C 10% faster than the 823B
Significant reduction in ground bounce from standard
CMOS devices
TIL compatible input and output levels
Low power in all three states
±10% power supply for both military and commercial
grades
JEDEC standard pinout for DIP, SOIC and LCC
packages
Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

EN

I

CLR

CP

OE

2643 drw 01

BiCEMOS is a trademark of Integrated Device Techology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1990 Inlegrated Device Technology. Inc.

6.64

JUNE 1990
DSC~11/·

1

IDT54174FBT823A/B/C
HIGH·SPEED BiCMOS 9·BIT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

0IUJ ° u 0

~
U
~
oooz>>->-

INDEX
Vcc
Yo
Y1
Y2
Y3
Y4
Ys
Y6
Y7
Y8
EN
CP

OE
Do
01
D2
D3
D4
Ds
D6
07
D8
CLR
GND

L-JL-JL-.JIIL...JL...JL...J

4 3 2

D2
D3
D4
NC
Ds
D6
07

L28·1

12 1314 1S 16 1718

Y2
Y3
Y4
NC
Ys
Y6
Y7

2643 drw 02

LCC
TOP VIEW

FUNCTION TABLE(1)

Name

1/0

DO-8

I

The D flip-flop data inputs.

CLR

I

For both inverting and non-inverting
registers, when the clear input is LOW, the
01 outputs are LOW. When the clear input
is HIGH, data can be entered into the register_

Description

Internal
Outputs

Inputs

Clock Pulse for the Register; enters data
into the register on the LOW-to-HIGH
transition.

Yo- Y8

0

The register three·state outputs.

EN

I

Clock Enable. When the Clock Enable is
LOW, data on the DI input is transferred to
the 01 output on the LOW-to-HIGH clock
transition. When the clock enable is HIGH,
the 01 outputs do not change state,
regardless of the data or clock input
transitions.

I

°

co leI: 0
c..IZ co
O...lzzoUJ>-

PIN DESCRIPTION

OE

2S [
24 [
23 [
22 [
21 [
20 [
19 [

r--.r-'lr-,'-"r-"I"r-,

DIP/SOIC/CERPACK
TOP VIEW

I

28 27 26

1

0<.9

CP

I I
L..J

Js
J6
J7
J8
J9
JlO
J 11

Output Control. When the OE input is HiGH,
the YI outputs are in the high impedance
state. When the OE input is LOW, the TRUE
register data is present at the YI outputs.

OE

CLR

EN

01

CP

QI

VI

Function

H
H

H
H

L
L

L
H

i
i

L
H

Z
Z

High Z

H
L

L
L

X
X

X
X

X
X

L
L

Z
L

Clear

H
L

H
H

H
H

X
X

X
X

NC
NC

Z
NC

Hold

H
H
L
L

H
H
H
H

L
L
L
L

L
H
L
H

i
i
i
i

L
H
L
H

Z
Z
L
H

Load

NOTE:
1. H = HIGH
L=LOW
X = Don·t Care
NC = No Change
i = LOW-to-HIGH Transition
Z = High Impedance

2643 Ibl 06

2643 Ibl 05

6.64

2

IOT54f74FBT823A/B/C
HIGH-SPEED BiCMOS 9-BIT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM

Rating
Terminal Voltage
with Respect
toGND

CAPACITANCE

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

TA

Operating
Temperature

a to +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

(TA

= +25°C, f = 1.0MHz)

Parameter(1)

Symbol

Conditions

CIN

Input Capacitance

VIN = OV

COUT

Output
Capacitance

VOUT

Typ.

= OV

Unit

6

pF

8

pF

NOTE:
26431b102
1. This parameter is measured at characterization but not tested.

NOTE:
2643 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other oonditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating oonditions for
extended periods may affect reliability. No terminal voltage may exceed
Vcc by +O.5V unless otherwise noted.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = ooe to +70 oe, vcc = 5.0V ± 10%; Military: TA
Symbol

= -55°C to +125°e, Vcc = S.OV± 10%

Test Conditions(1)

Parameter

Min.

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

Vil

Input LOW Level

Guaranteed Logic LOW Level

-

= 2.7V
= Max., VI = .5V

IIH

Input HIGH Current

Vee = Max., VI

III

Input LOW Current

Vee

10ZH

High Impedance

Vee = Max.

Va = 2.7V

10Zl

Output Current

Ii

Input HIGH Current

Vee = Max., VI = S.SV

VIK

Clamp Diode Voltage

Vee = Min., IN = -18mA

los

Short Circuit Current

Vee

VOH

Output HIGH Voltage

Vee = Min.

10H = -12mA MIL.

VIN = VIH or Vil

10H = -15mA COM'L.

Vo= .SV

= Max.,

Vo = GND(3)

10H = -18mA MIL.
10H
Val

Output LOW Voltage

Typ_(2)

Max.

Unit

-

-10

jlA

-

50

jlA

-

V

0.8

V

10

jlA

-

-SO

-

100

jlA

-1.2

V

-225

mA

-0.7

-75

-

2.4

3.3

-

V

2.0

3.0

-

V

-

0.3

0.5

V

-

200

= -24mA COM'L.

10l = 32mA MIL.
10l = 48mA COM'L.

= SV

VH

Input Hysteresis

Vee

10FF

Bus Leakage Current

Vee = OV, Va

lee

Quiescent Power
Supply Current

Vee = Max.
VIN = GND or Vee

-

= 4.SV

mV

-

jlA

0.2

1.5

mA

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one seoond.

6.64

100

26431b105

3

I

IDT54174FBT823A/B/C
HIGH·SPEED BICMOS 9·BIT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol
f1lee
IceD

Ie

Parameter
Quiescent Power Supply
Current (Inputs TTL HIGH)
Dynamic Power Supply
Current(4)

Total Power Supply
Current(6)

Test Condltions(l)

Typ.(2)

Max.

Unit

-

-

2.0

mA

-

0.25

Min.

Vee = Max., Outputs Open
VIN = 3.4V(3)
Vee = Max., Outputs Open
OE= GND
One Input Toggling
50% Duty Cycle

VIN = Vee
VIN = GND

-

Vee = Max., Outputs Open

VIN = Vee
VIN=GND

-

-

4.0

fi = 1OMHz, 50% Duty Cycle
OE = GND
One Bit Toggling

VIN = 3.4V
VIN= GND

-

-

5.0

Vee = Max., Outputs Open

VIN = Vee
VIN = GND

-

-

7.2(5)

fi = 2.5MHz, 50% Duty Cycle
OE = GND
Eight Bits Toggling

VIN = 3.4V
VIN= GND

-

-

16.2(5)

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient, and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + L\lcc DHNT + ICCD (fCP/2 + fi Ni)
Icc = Quiescent Current
L\lcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
. fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.64

mAl
MHz

mA

26431b104

4

IDT54n4FBT823A1B/C
HIGH-SPEED BICMOS 9-BIT REGISTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FBT823A
Symbol

Parameter

tPLH
tPHL

Propagation Delay
ClocktoYI
(OE ... LOW).

tsu

Data to CP
Set-up Time

IDT54174FBT823C

IDT54174FBT823B

Mil.

Com'l.

Mil.

Com'l.

Mil.

Com'l.

Condltlon(1) Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.<2) Max. Mln.(2) Max. Mln,<2) Max. Unit
CL- 50pF
RL ... 500n

-

10

-

-

-

7.5

-

-

-

7

-

-

-

3

-

-

-

1.5

6.0

-

-

ns

3

-

-

-

ns

tH

Data CP Hold Time

-

3

-

-

-

ns

3

-

1.5

-

-

-

6

-

1.5

Enable (EN) to
CP Set-up Time

-

-

tsu
tH

Enable (EN) to CP
Hold Time

0

-

-

-

0

-

-

-

0

-

-

-

ns

tPHL

Propagation Delay,
Clear to YI

-

12

-

-

-

9

-

-

-

8.0

-

-

ns

tREM

Clear Recovery
(CLR)Time

6

-

-

-

6

-

-

-

6

-

-

-

ns

tw

Clock Pulse Width

7

-

6

-

-

6

-

-

ns

-

-

-

6

-

6

Clear (CLR-LOW)
Pulse Width

-

-

tw
tPZH
tPZL

Output Enable Time
OEto YI

-

12

7.0

-

-

ns

tPHZ
tPLZ

Output Disable
Time OE to YI

-

8

-

6.5

-

-

ns

-

-

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

6

-

-

8

-

-

-

-

7.5

-

-

-

ns

ns

26431b107

I

~.64

5

IOT54174FBT823A/B/C
HIGH·SPEED BICMOS 9-BIT REGISTER

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION

TEST CIRCUITS FOR ALL OUTPUTS

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

2643 tbl 08
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

Z&t

1

PULSE WIDTH

~..-..~~

-= ~~V
_ OV

tsU-'i4---toi

,TIMING
INPUT _ _ _ _ _ _-'

- 3V
_

6JV

LOW-HIG~~~~=t ~ '5V

-

3V

HIGH-LOW-HIGH

ASYNCHRONOUS CONTROL
PRESET - - - -....
CLEAR
ETC. - - - - SYNCHRONOUS CONTROL
CLOCK

- - + - - - - - - 1.SV

:~~~~~
vvY 1
ETC.~tsu

~..-..~~

tw

_ _ 1.SV

PULSE

- OV
- 3V
-1.SV

- ov

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE
----3V

r---~-----3V

SAME PHASE
INPUT TRANSITION

OUTPUT

,....--_.+-- VOH

3.SV

-1.SV

VOL

VOL
VOH

SWITCH
OPEN

3V
OPPOSITE PHASE
INPUT TRANSITION

OV
NOTES
2643 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ son; tF ~ 2.Sns;
tR ~ 2.Sns.

6.64

6

IDT54174FBT823A/B/C
HIGH-SPEED BICMOS 9-BIT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

xx

FBT

Temperature
Range

XXXX

X

x

Device Type

Package

Process

~~lank
P
D
~--------------~ SO

L

E

I 823A

' - - - - - - - - - - - - - - - - - - 1 823B
1
~

______________________________~I

823C
54

I 74

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Non-inverting 9-Bit Register
High-Speed Non-inverting 9-Bit Register
Very High-Speed Non-inverting 9-Bit Register
-55°C to +125°C
O°C to +70°C
2643 drw 03

I

6.64

7

(;5
Integr~ted

ADV ANCE INFORMATION
IDT54/74FBT827 AlBIC
IDT54/74FBT828A1B/C

HIGH-SPEED BiCMOS
10-BIT BUFFERS AND
BUS DRIVERS

Device Technology, Inc.

FEATURES:

DESCRIPTION:

• Functionally equivalent to 54/74BCT827A1828A
• IDT54/74FBT827B/828B 25% faster than the
827A/828A
• IDT54/74FBT827C/828C 10% faster than the
827B/828B
• Significant reduction in ground bounce from standard
CMOS devices
• TIL compatible input and output levels
• Low power in all three states
• ± 10% power supply for both military and commercial
grades
• JEDEC standard pinout for DIP, SOIC and LCC
packages
• Military product compliant to MIL-STD-883, Class B

The FBTseries of BiCMOS buffers and bus drivers are built
using advanced BiCEMOSTM, a dual metal BiCMOS
technology. This technology is desgined to supply the highest
device speeds while maintaining CMOS power levels.
The IDT54/74FBT827 and IDT54/74FBT828 are 3-state,
10-bit bus drivers. They provide bus interface to wide
data/address paths or buses carrying parity. The output
buffers are enabled when the two active-low output enable
pins are both logic low.
The FBT series of buffers are ideal for use in designs
needing to drive large capacitive loads with low static (DC)
current loading. All data inputs have a 200mV typical input
hysteresis for improved noise rejection.

FUNCTIONAL BLOCK DIAGRAM(1)
Yo

Y1

Y2

Y3

Y4

Ys

NOTE:
1. Non-inverting part shown.

Y6

Y7

Ya

yg

2598 drw 01

PRODUCT SELECTOR GUIDE
1O-Blt Buffers

I Non-inverting
I Inverting

IOT54/74FBT827 AlBIC
IOT54/74FBT828A/B/C
2598 tbl 01

BiCEMOS is a trademark of Integrated Device Techology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
C1990 Integrated Device Technology, Inc.

6.65

JUNE 1990
DCS-6013!-

IDT54n4FBT827A/B/C, IDT54n4FBT828A1B/C
HIGH-SPEED BiCMOS 10-BIT BUFFERS AND BUS DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
~

INDEX
Yo
Y1
Y2
Y3
Y4
Ys
Y6
Y7
Y8

Dg

yg

GND

L.....J

I

128 2726
2S [
24 [
23 [
22 [
21 [
20 [
19 [

1
L28-1

cocnOOC\Jcnco
00 Z Z
>- >-

~

Y2
Y3
Y4
NC
Ys
Y6
Y7

ILlJ
0

2598 drw02

LCC
TOP VIEW

FUNCTION TABLES
IDT54/74FBT827 AlBIC (NON-INVERTING)(1)
Inputs

Name

1/0

Description

I

When both are LOW the outputs are
enabled. When either one or both are
HIGH the outputs are High Z.

I

~

12 13 14 15 16 17 18

OE2

OE1,2

0

a

IL......JL...JL......J

,....., ,..-, ,....., ro ,....., ro ,.....,

PIN DESCRIPTION

Do - 09

L......JI

LJ

]S
J6
]7
J8
]9
] 10
] 11

DIP/CERPACKlSOIC
TOP VIEW

Yo- Y9

L...J

4 3 2
02
03
04
NC
Os
06
07

8

0lwO

oooz> >->-

Vee

OE1
Do
D1
D2
D3
D4
Ds
D6
D7
D8

1O-bit data input.
10-bit data output.
25981b102

Output

OE1

OE2

DI

VI

L
L

L
L

L
H

L
H

Transparent

X
X

Z
Z

Three-state

X
H
H
X
NOTE:
1.H = HIGH. L = LOW. X

25981b103

= Don't Care, Z = High Impedance.

I DT54/74FBT828A/B/C (INVERTING)(1)

LOGIC SYMBOL

Inputs
DO·9 - - - - - - - , , " - 4

Function

Yo·g

OE1
O E 2 - - -a
2598 drw03

OE2

DI

VI

L
L

L
L

L
H

H
L

Transparent

X
X

Z
Z

Three-state

X
H
H
X
NOTE:
1. H = HIGH. L = LOW, X

6.65

Output

OE1

Function

25981b104

= Don't Care. Z = High Impedance.

2

I

IDT54174FBT827A/B/C, IDT54174FBT828A1B/C
HIGH-SPEED SiCMOS 10-BIT BUFFERS AND BUS DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)

CAPACITANCE (TA = +2S0C f = 1 OMHz)

Symbol

Rating

Commercial

Military

Unit

VTERM

Terminal Voltage
with Respect
to GND

-0.5 to +7.0

-0.5 to +7.0

V

TA

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to + 150

°C

PT

Power Dissipation

0.5 .

0.5

W

lOUT

DC Output Current

120

120

mA

Symbol

Parameter(l)

Conditions

Unit

Typ.

CIN

Input Capacitance

VIN = OV

6

pF

COUT

Output Capacitance

VOUT = OV

8

pF

NOTE:
2598 tbl
1. This parameter is measured at characterization but not tested.

06

NOTES:
25981b105
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = S.OV -+ 10%; Military: TA
Symbol

= -55°C to +125°C, Vcc = 5.0V ± 10%

Test Conditions(l)

Parameter

Min.

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

IIH

Input HIGH Current

Vcc

= Max.,
Vcc = Max.,
Vee = Max.

-

IlL

Input LOW Current

10ZH

High Impedance

10ZL

Output Current
Input HIGH Current

Vee

Clamp Diode Voltage

Vcc

los

Short Circuit Current

VOH

Output HIGH Voltage

Output LOW Voltage

VH

Input Hysteresis

10FF

Bus Leakage Current

Icc

Quiescent Power
Supply Current

= 2.7V
Vo = 0.5V
Vo

= Max., VI = 5.5V
= Min., IN = -18mA
Vee = Max., Vo = GND(3)
Vee = Min.
VIN = VIH or Vil

II
VIK

VOL

= 2.7V
VI = 0.5V
VI

= 5V
= OV, Vo = 4.5V
Vee = Max.
VIN = GND or Vee
Vee

Vee

= -12mA MIL.
= -15mA COM'L.
10H = -18mA MIL.
10H = -24mA COM'L.
10l = 32m A MIL.
10l = 48mA COM'L.

10H
10H

Typ.(2)

Max.

-

V

0;8

V

10

JlA

-10

JlA

50

JlA

-

-0.7

-1.2

V

-75

-150

-225

mA

2.4

3.3

-

V

2.0

3.0

-

V

-

0.3

0.5

V

-

200

-50

-

100

JlA

-

mV

-

100

JlA

0.2

1.5

mA

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

6.65

Unit

-

-

2598 tbl 05

3

IDT54174FBT827A/B/C, IDT54174FBT828A1B/C
HIGH·SPEED BiCMOS 10·BIT BUFFERS AND BUS DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol

Parameter

Test Conditions(1)

Max.

Unit

-

-

2.0

mA

VIN = Vcc
VIN = GND

-

-

0.25

VIN = Vcc
VIN = GND

-

-

4.0

fi = 1 OMHz, 50% Duty Cycle
OEl = OE2 = GND
One Bit Toggling

VIN = 3.4V
VIN = GND

-

-

5.0

Vcc = Max .• Outputs Open

VIN = Vcc
VIN = GND

-

-

7.8(5)

fi = 2.5MHz. 50% Duty Cycle
OEl = OE2 = GND
Ten Bits Toggling

VIN = 3.4V
VIN = GND

-

-

17.8(5)

~Icc

Quiescent Power Supply Current
(Inputs TIL HIGH)

Vcc = Max.
VIN = 3.4V(3)

ICCD

Dynamic Power Supply Current(4)

Vcc = Max .• Outputs Open
OEl = OE2 = GND
One Input Toggling
50% Duty Cycle
Vcc = Max., Outputs Open

Ic

Total Power Supply Current(6)

Min.

Typ.

mAl
MHz

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are atVcc = 5.0V. +25°C ambient, and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + .1lcc DHNT + ICCD (fcp/2 + fiNi)
Icc = Quiescent Current
.1lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
Iceo = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz ..

mA

2598 tbl 08

I

6.65

4

IDT54f74FBT827A/B/C, IDT54f74FBT828A1B/C
HIGH-SPEED BiCMOS 10-BIT BUFFERS AND BUS DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE -IDT54/74FBT827A/B/C
54174FBT827B

54174FBT827A
Com'l.
Symbol

Parameter

Condition(1)

Com'l.

Mil.

54174FBT827C

Mil.

Com'l.

Mil.

Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit

-

7.0

-

-

-

5.0

-

-

-

4.4

-

-

ns

Output Enable Time
OEtoYI

-

12.0

-

-

-

8.0

-

-

-

7.0

-

-

ns

Output Disable Time
OE to YI

-

12.0

-

-

-

7.0

-

-

-

6.0

-

-

ns

tPHL
tPLH

Propagation Delay
Dlto YI

tPZH
tPZL
tPHZ
tPLZ

CL
RL

= SOpF
= soon

SWITCHING CHARACTERISTICS OVER OPERATING RANGE -IDT54/74FBT828A/B/C

Parameter

Condition(1)

tPHL
tPLH

Propagation Delay
Dlto YI

CL = SOpF
RL = soon

tPZH
tPZL
tPHZ
tPLZ

Symbol

54174FBT828C

54174FBT828B

54174FBT828A
Com'l.

Com'l.

Mil.

Com'l.

Mil.

Mil.

Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. MinP) Max. Unit

-

7.0

-

-

-

S.s

-

-

-

4.4

-

-

ns

Output Enable Time
OEtoYI

-

11.0

-

-

-

8.0

-

-

-

7.0

-

-

ns

Output Disable Time
OEtoYI

-

10.0

-

-

-

7.0

-

-

-

6.0

-

-

ns

NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed, but not tested.

2598 ttl 07

6.65

5

IDT5417 4FBT827AlBIC, IDT54174FBT828A1B/C
HIGH-SPEED BiCMOS 10-BIT BUFFERS AND BUS DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS

SWITCH POSITION

TEST CIRCUITS FOR ALL OUTPUTS

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
259S1bIOS
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

PULSE WIDTH

-= ~~V

J

'OL."-'_ _ _ -

OV

tsu~-+--~

TIMING - - - - - - INPUT

LOW-HIG~i~~

- 3V
_ ~JV

ASYNCHRONOUS CONTROL
PRESET - - - -.....
CLEAR
ETC. - - - - - '
SYNCHRONOUS CONTROL

CLOCK:~~~~~ vvJr
j
~tsu
ETC.

-

--+------

3V
1.5V
OV

=t-

~ '.5V
W

--1.5V

HIGH_LOW_HIGH'
PULSE

- 3V
-1.5V
OV

'OL."-'___ -

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE
3V

3V
SAME PHASE
IN PUT TRANSITION

1.5V
OV

OV
3.5V

OUTPUT

VOL
VOL
VOH
SWITCH
OPEN

3V
OPPOSITE PHASE
INPUT TRANSITION

OV

OV

NOTES
259S drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate::;; 1.0 MHz; Zo::;; son; tF ::;; 2.Sns;
tR::;; 2.Sns.

6.65

6

•

IDT54174FBT827AlBIC, IDT54174FBT828A1B/C
HIGH-SPEED BiCMOS 10-BIT BUFFERS AND BUS DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

xx

FBT

Temperature
Range

XXXX

x

x

Device
Type

Package

Process

~~Iank
P
~--------------~

E

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

827A
828A
827B
828B
827C
828C

Non-inverting 1D-Bit Buffer and Line Driver
Inverting 1D-Bit Buffer and Line Driver
High-Speed Non-inverting 1D-Bit Buffer and Line Driver
High-Speed Inverting 1D-Bit Buffer and Line Driver
Very High-Speed Non-inverting 1D-Bit Buffer and Line Driver
Very High-Speed Inverting 1D-Bit Buffer and Line Driver

o

SO

L

~

~

____________________~

Commercial
MIL-STD-883, Class B

__________________________~154
174

-55°C to + 125°C
0° to +70°C
2598 drw 04

6.65

7

G®

ADVANCE INFORMATION
IDT54/74FBT841 A
IDT54/74FBT841 B
IDT54/74FBT841 C

HIGH-SPEED 8iCMOS
10-81T INTERFACE
LATCHES

Integr..ted Device Technology, Inc.

FEATURES:

DESCRIPTION:

•
•
•
•

The FBT series of BiCMOS Bus Interface Latches are built
using advanced BiCEMOSTM, a dual metal BiCMOS
technology. This technology is desgined to supply the highest
device speeds while maintaining CMOS power levels.
The IDT54/74FBT841 series are 3-state, 10-bit bus
interface latches.
The FBT series of bus interface devices are ideal for use in
designs needing to drive large capacitive loads with low
static(DC) current loading. All data inputs have a 200mV
typical input hysteresis for improved noise rejection.

•
•
•
•
•

Functionally equivalent to the 54/74BCT841 series
I DT54/74FBT841 B 20% faster than the 841 A
IDT54/74FBT841C 15% faster than the 841 B
Significant reduction in ground bounce from standard
CMOS devices
TIL compatible input and output levels
Low power in all three states
±10% power supply for both military and commercial
grades
JEDEC standard pinout for DIP, SOIC and LCC
packages
Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

II
2600drw Ot

PIN CONFIGURATIONS
OE
Do
01
02
03
04
05
06
07
Oa
09
GNO

~ 0lwO

INDEX

Vee
Yo
Y1
Y2
Y3
Y4
Ys
Y6
Y7
Ya
Y9

02
03
04
NC
05
06
07

8 ° ~

ClClOZ> >->-

'Y

JS
J6
J7
Ja
J9
JlO
J 11

L...J L......JL...J

I IL..J
I
LJ

L......J

L...J

128 27 26
25 [
1
24 [
23 [
L28-1
22 [
21 [
20 [
19 [
12 1314 1516 17 1a
4 3 2

ror--l,-,...,..,,.,'-'

LE

co"'ClOUJ"''''
ClClZZ...J>->-

Y2
Y3
Y4
NC
Ys
Y6
Y7

/
2600 drw 02

(!)

DIP/SOIC/CERPACK
TOP VIEW

LCe
TOP VIEW

BiCEMOS is a trademark of Integrated Device Techology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
et990 Integrated Device Technology. Inc

6.66

APRIL 1990
DSC-6004/-

1

IDT54f74FBT841 AlBIC
HIGH-SPEED BiCMOS 10-BIT INTERFACE LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE(1)

PIN DESCRIPTION
Name

I/O

Description

I

The latch data inputs.

LE

I

The latch enable input. The latches are
transparent when LE is HIGH. Input data is
latched on the HIGH-to-LOW transition.

VO-9
OE

0
I

The 3-state latch outputs.
The output enable control. When OE is LOW,
the outputs are enabled. When OE is high,
the outputs VI are in the highimpedance (off) state.
2600 till 05

D

Outputs

OE

LE

01

QI

VI

H

X

X

X

Z

High Z

H

H

L

L.

Z

High Z

H

H

H

H

Z

High Z

H

L

X

NC

Z

Latched (High Z)

L

H

L

L

L

Transparent

L

H

H

H

H

Transparent

L

L

X

NC

NC

Function

Latched

NOTE:
2600 tbl 06
1. H = HIGH, L = LOW, X = Don't Care, NC = No Change, Z = High
Impedance

LOGIC SYMBOL
D

Internal

Inputs

DO-9

10

.>O---,.t-

V

LE
LE-----1
OE _ _ _ _ _ _ _ _ _----l
2600 drw03

ABSOLUTE MAXIMUM RATINGS(1)

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol

Rating

Commercial

Military

Unit

VTERM

Terminal Voltage
with Respect
toGND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
Power Dissipation

-0.5 to +7.0

-0.5 to +7.0

V

TA
TBIAS
TSTG
PT
lOUT

DC Output Current

o to +70

-55 to +125

°C

-55 to + 125

-65 to +135

°C

-55 to +125

-65 to +150

°C

0.5
120

0.5
120

mA

Symbol

Parameter(1)

CIN

Input Capacitance

COUT

Output Capacitance

Conditions

= OV
VOUT = OV
VIN

Typ.

Unit

6

pF

8

pF

NOTE:
2600 till 02
1. This parameter is measured at characterization but not tested.

W

NOTES:
2600 till 01
t. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.

6.66

2

IDT54174FBT841 AlBIC
HIGH-SPEED BiCMOS 10-BIT INTERFACE LATCHES

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vce = 5.0V ± 10%; Military: TA

= -55°C to +125°C, Vee = 5.0V ± 10%
Min.

Typ.(2)

VIH

input HiGH Level

Guaranteed Logic HIGH Level

2.0

Vil

Input LOW Level

Guaranteed Logic LOW Level

-

IiH

Input HIGH Current

Vee = Max., VI = 2.7V

-

-

Symbol

Test Conditlons(l)

Parameter

Max.

Unit

-

V

0.8

V

10

~A

-10

~A

50

~A

II

Input HIGH Current

Vee = Max., VI = 5.5V

-

VIK

Clamp Diode Voltage

Vee = Min., iN = -18mA

-

-0.7

-1.2

IlA
V

los

Short Circuit Current

Vee = Max., Vo = GNO(;J)

-75

-150

-225

mA

VOH

Output HIGH Voltage

Vee = Min.

10H = -12mA MiL.

2.4

3.3

-

V

VIN = VIH or Vil

10H = -15mA COM'L.
IOH = -18mA MIL.
10H = -24mA COM'L.

2.0

3.0

-

V

10l = 32mA MIL.
10l = 48mA COM'L.

-

0.3

0.5

V

-

200

-

mV

-

100

0.2

1.5

Il A
mA

III

Input LOW Current

Vee = Max., VI = 0.5V

10ZH

High Impedance

Vee = Max.

10Zl

Output Current

VOL

Vo = 2.7V
Vo = 0.5V

Output LOW Voltage

VH

Input Hysteresis

Vee = 5V

10FF

Bus Leakage Current

Vee = OV, Vo = 4.5V

lee

Quiescent Power
Supply Current

Vee = Max.
VIN = GNO or Vee

-

100

-50

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not excedd one second.

6.66

2600 tbl 03

3

IDT54174FBT841 AlBIC
HIGH·SPEED BiCMOS 10·BIT INTERFACE LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol

Parameter

Test Conditions(1)

Max.

Unit

-

2.0

mA

= Vee
= GND

-

-

0.25

-

-

4.0

-

-

5.0

Vee = Max., Outputs Open
fi = 2.5MHz, 50% Duty Cycle

= Vee
= GND
VIN = 3.4V
VIN = GND
VIN = Vee
VIN = GND

-

-

7.8(5)

OE = GND, LE = Vee
Ten Bit Toggling

VIN
VIN

-

-

17.8(5)

Quiescent Power Supply
Current (Inputs TIL HIGH)

Vee = Max.
VIN = 3.4V(3)

ieeD

Dynamic Power Supply Current(4)

Vee = Max., Outputs Open
OE = GND
One input Toggling
LE = Vee
50% Duty Cycle

VIN
VIN

Vee = Max., Outputs Open
fi = 1OMHz, 50% Duty Cycle

Ie

Total Power Supply Current(6)

Typ.(2)

-

Min.

61ee

OE = GND, LE = Vee
One Bit Toggling

VIN
VIN

=

3.4V

= GND

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient, and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vee or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT +IINPUTS + IDYNAMIC
Ic = Icc + lllccDHNT + ICCD(fcp/2 + fNi)
Icc = Quiescent Current
lllcc =Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.66

mAl
MHz

mA

2600 tbl 04

4

IDT54174FBT841 AlBIC
HIGH-SPEED BiCMOS 10-BIT INTERFACE LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
54174FBT841A
Com'l.
Symbol

tPLH
tPHL

f--

Parameter

Condition(1)

Data (01) to Output (YI) CL = SOpF
(LE = HIGH)
RL =

54174FBT841C

54174FBT841 B
Com'l.

Mil.

Com'l.

Mil.

Mil.

Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit

-

8.0

-

-

-

6.5

-

-

-

5.5

-

-

ns

-

-

-

-

-

-

-

-

-

-

-

-

ns

soon

CL = 300pF(3)
RL =

tPLH
tPHL

soon

tsu

Data to LE Set-up Time CL = SOpF

-

1.5

-

-

-

1.5

-

3.5

-

-

-

2.5

-

2.5

-

-

ns

soon

-

1.5

Data to LE Hold Time

-

-

tH
tPLH
tPHL

Latch Enable (LE) to YI CL = SOpF
RL =

-

10.0

-

-

-

8.0

-

-

-

6.4

-

-

ns

soon

f--

tPLH
tPHL
tw

RL =

CL = 300pF(3)
RL =

-

-

-

-

-

-

-

-

-

-

-

-

ns

CL = SOpF
RL =

-

4.0

-

-

-

4.0

-

-

-

4.0

-

-

ns

CL = SOpF
RL =

-

8.0

-

-

-

8.0

-

-

-

6.5

-

-

ns

CL = 300pF(3)

-

-

-

-

-

-

-

-

-

-

-

-

ns

-

-

-

7.0

-

-

-

6.0

-

-

ns

-

-

-

-

-

-

-

-

-

-

ns

soon

LE Pulse Width HIGH

soon

tPZH
tPZL

Output Enable Time
OE tOYI

tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ

ns

soon

RL =
Output Disable Time
OE tOYI

soon

CL = SOpF(3)
RL =

-

15.0

soon

CL = SOpF
RL =

soon

-

-

NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter guaranteed but not tested.

2600 tbl 07

I

II

6.6.6

5

IDTS4n4FBT841 AlBIC

HIGH·SPEED BiCMOS 10·BIT INTERFACE LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS

SWITCH POSITION

TEST CIRCUITS FOR ALL OUTPUTS
Vcc

0--.7.0V

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

2600 tbl 08
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

~

PULSE WIDTH

-= ~~V

l
tsu ---toj+--~

~~~~ -

TIMING
INPUT _ _ _ _ _ _,

OV

LOW-HIG~~~S~

- 3V
_ 6~V

ASYNCHRONOUS CONTROL
PRESET - - - - , ,-+--~----- - 3V
- - t - - - - - - 1.SV
CLEAR
ETC.
- OV
SYNCHRONOUS CONTROL
CLOCK

:~~~~~ vvJr
l
~tsu

~~...K~

ETC.

=t-

HIGH-LaW-HIGH
PULSE

_

~ 15V
tw

--1.5V

3V

-1.5V
-

PROPAGATION DELAY

OV

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

~--_---3V

SAME PHASE
INPUT TRANSITION
~--_.+-- VOH

OUTPUT

-1.5V
VOL

OPPOSITE PHASE
INPUT TRANSITION

' - - - - . 1 - - - - OV

NOTES
2600 drw 04
1. Diagram shown for input Control Enable·LOW and input Control
Disable·HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ SOQ; tF ~ 2.Sns;
tR ~ 2.Sns.

6.66

6

IDT54174FBT841 AlBIC
HIGH-SPEED BiCMOS 10-BIT INTERFACE LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XX

---Temperature
Range

FBT XXXX
Device
Type

X

X

Package

Process

~~rank
P
D
' - - - - - - - - - - - - 1 SO
L
E
841 A

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

841 C

Non-inverting 1O-Bit Bus Interface Latch
High-S~ed Non-inverting 1O-Bit Bus Interface Latch
Very High-Speed Non-inverting 1O-Bit Bus Interface Latch

54
74

-55°C to +125°C
0° to +70°C

-I 841 B

L..-_ _ _ _ _ _ _ _ _ _ _

'---_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- j

Commercial
MIL-STD-883, Class B

2600 drw 04

II

6.66

7

t;)®

"

ADVANCE INFORMATION
'IDT54/74FBT2240
IDT54/74FBT2240A
IDT54/74FBT2240C

HIGH-SPEED BiCMOS
MEMORY DRIVERS

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

•
•
•
•

The FBT series of BiCMOS Memory Drivers is built using
advanced BiCEMOSTM, a dual metal BiCMOS technology.
This technology is designed to supply the highest device
speeds while maintaining CMOS power levels.
The IDT54/74FBT2240 series are octal buffers/line drivers
where each output is terminated with a 250 series resistor.
The FBT series of bus interface devices are ideal for use in
designs needing to drive large capacitive loads with low static
(DC) current loading. All data inputs have a 200mV typical
input hysteresis for improved noise rejection. This higher
output level in the high state will result in a significant reduction
in overall system power dissipation.

•
•
•
•
•

IDT54/74FBT2240 equivalent to the 54/74BCT2240
IDT54/74FBT2240A 25% faster than the 2240
IDT54/74FBT2240C 10% faster than the 2240A
250 output resistors reduce overshoot and undershoot
when driving MOS RAMs
Significant reduction in ground bounce from standard
CMOS devices
TTL compatible input and output levels
±10% power supply for both military and commercial
grades
JEDEC standard pinout for DIP, SOIC and LCC packages
Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS
Vee

OEA
OEs
DAo

OAo

OBo

080

DAl

OAl

081

081

DA2

OM

082

082

DA3

OA3

2
3
4

DAo
OBo
DA1
OB1
DA2
OB2
DA3
OB3
GND

P20-1
D20-1
8020-2
&
E20-1

6

7
8

9
10

OEs
OAo
DBo
OA1
OB1
OM
DB2
OA3
OB3

DlP/SOIC/CERPACK
TOP VIEW
o

<: u

0

,.

32:
OAl
081
OM
082
OA3

083

2642drw 01

CD

I~ C31~~I~

INDEX

083

19
1B
17
16
15
14
13
12
11

]
]
]
]
]

4
5
6
7
8

:~';9

18
17
16
15
14
9 10 11 1213

L20-2

[
[
[
[
[

OAo
DBo
OAl
DBl
OM

r--1r1 1111 r-1

LCC
TOP VIEW

2642 drw 02

BiCEMOS is a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
<1:>1990 Integrated Device Technology. Inc.

6.67

APRIL 1990
DSC-W01/·

IOT5417 4FBT22401AlC
MILITARY AND COMMERCIAL TEMPERATURE RANGES

HIGH·SPEED BiCMOS MEMORY DRIVERS

FUNCTION TABLE(1)

PIN DESCRIPTION
Pin Names

Description

OEA,OEB

3·State Output Enable Inputs (Active LOW)

00-07
00-07

Inputs
OEA,OEe

D

Output

Inputs

L

L

H

Outputs

L

H

L

H

X

Z

2642 tbl 01

NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance

LOGIC SYMBOL

2642 tbl 02

O:~_O
2642 drw 03

ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Commercial

Military

Unit

VTERM(2) Terminal Voltage
with Respect
toGND

-0.5 to +7.0

-0.5 to +7.0

V

VTERM(3) Terminal Voltage
with Respect
toGND

-0.5 to Vee

-0.5 to Vee

V

TA

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

rnA

Parameter(1)

Typ.

Unit

CIN

Input Capacitance

VIN = OV

6

pF

COUT

Output
Capacitance

VOUT = OV

8

pF

Symbol

Conditions

NOTE:
2642 tbl 04
1. This parameter is measured at characterization but not tested.

NOTE:
2642 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 1/0 terminals only.

6.67

2

IDT54f74FBT2240/AlC
HIGH-SPEED BiCMOS MEMORY DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vee = 5.0V ± 10%; Military: TA

= -55°C to +125°C, Vee = 5.0V ± 10%
Min.

Typ.(2)

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

Vil

Input LOW Level

Guaranteed Logic LOW Level

-

-

0.8

V

IIH

Input HIGH Current

Vee

= Max.,
Vee = Max.,
Vee = Max.

-

-

10

)lA

-

-

-10

)lA

-

-

50

)lA

-

-50

Symbol

Test Condltlons(')

Parameter

III

Input LOW Current

10ZH

High Impedance

10Zl

Output Current

= 2.7V
Va = 0.5V
VA

= Max., VI = 5.5V
= Min., liN = -18mA
Vee = Min., Va = 2V
Vee = Min., VA = 2V
Vee = Max., Va = GND(3)
Vee = Min.
VIN = VIH or Vil

II

Input HIGH Current

Vee

VIK

Clamp Diode Voltage

Vee

10DH

Output Drive Current

10Dl

Output Drive Current

los

Short Circuit Current

VOH

Output HIGH Voltage

Val

= 2.7V
VI = 0.5V
VI

Output LOW Voltage

= 5V

VH

Input Hysteresis

Vee

lee

Quiescent Power
Supply Current

Vee = Max.
VIN = GND or Vee

= -1mA
10H = -12mA
10l = 1mA
10l = 12mA

-

-

100

-0.7

-1.2

-

V

)lA
V

50
-60

-

2.4

3.3

-

2.0

3.0

-

-

0.15

0.5

-

0.35

0.8

-

200

-

mV

-

0.2

1.5

mA

-225

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°e ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

6.67

Unit

-

-35

10H

Max.

mA
mA
mA
V

V

2642 tbl 05

3

IDT54174FBT2240/AlC
HIGH-SPEED BiCMOS MEMORY DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol

Test Conditlon3(1)

Parameter

Typ.(2 j

Max.

Unit

-

-

2.0

rnA

-

0.25

Min.

61ee

Quiescent Power Supply
Current (Inputs TIL HIGH)

Vee = Max.
VIN = 3.4V(3)

leeD

Dynamic Power Supply
Current(4)

Vee = Max., Outputs Open
OEA = OEs = GND
One Input Toggling
50% Duty Cycle

VIN = Vee
VIN = GND

-

Total Power Supply
Current(6)

Vee = Max., Outputs Open
fi = 1OMHz, 50% Duty Cycle

VIN = Vee
VIN = GND

-

-

4.0

OEA = OEs = GND
One Bit Toggling

VIN = 3.4V
VIN = GND

-

-

5.0

Vee = Max., Outputs Open
fi = 2.5MHz, 50% Duty Cycle

VIN = Vee
VIN = GND

-

-

6.5(5)

OEA = OEs = GND
Eight Bits Toggling

VIN = 3.4V
VIN = GND

-

-

14.5(5)

Ie

mN
MHz

rnA

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient, and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IOUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fCP/2 + fi Ni)
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (V IN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz

2642 tbl 06

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

Symbol

Parameter

Condition(1)

IDT54/74FBT2240

IDT54/74FBT2240A

Com'l.

Com'l.

Mil.

Com'l.

Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.

Min.(2)

Mil.

Max. Min.(2) Max. Unit

1.5

5.7

-

-

-

-

-

-

-

-

-

-

ns

Output Enable Time

1.5

9.3

-

-

-

-

-

-

-

-

-

-

ns

Output Disable Time

1.5

8.7

-

-

-

-

-

-

-

-

-

-

ns

tPLH
tPHL

Propagation Delay
On to On

tPZH
tPZL
tPHZ
tPLZ

CL = 50pF
RL = 500n

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

I

IDT54/74FBT2240C

Mil.

2642 tbl 07

6.67

4

IDTS4n4FBT2240/AlC
HIGH-SPEED BiCMOS MEMORY DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vcc

SWITCH POSITION
0--.7.0V

soon

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2642 tbl 08
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zxt

j

"",-..K...JIII:~

PULSE WIDTH

-= ~~V
-

OV

tsu~>!4--~

TIMING
INPUT _ _ _ _ _ _- '

LOWHIG~J~s~

- 3V
- - 1 1 - - - - - - - 1.SV
- OV

ASYNCHRONOUS CONTROL
PRESET - - - - - - - , ~--~--~--------­ - 3V
- - f - - - - - - - 1.SV
CLEAR
- OV
ETC. - - - - - '
SYNCHRONOUS CONTROL

CLOCK:~~~~~
vvJr l
ETC.~SU

~~-~

t

=t-

HIGH-LOW-HIGH
PULSE

~ 1.5V
tw

~

_ _ 1.SV

- 3V
-l.SV
-OV

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

-----3V
SAME PHASE
INPUT TRANSITION

3.SV
OUTPUT

VOL
VOH

SWITCH
OPEN

OPPOSITE PHASE
INPUT TRANSITION

OV

"-------' - - - - OV

NOTES
2642 drw 05
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate S 1.0 MHz; Zo S SOQ; tF S 2.Sns;
tR S 2.Sns.

6.67

IDT54f74FBT2240/A/C
HIGH-SPEED BiCMOS MEMORY DRIVERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT
XX
FBT XXXXX
---Temperature
Device Type
Range

X

X

Package

Process

~~Iank
P

o

L-------------i

SO
L
E

. I 2240
L-----------------i

l

L---------------------il

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

2240A
2240C

Memory Driver
High-Sf>€:!ed Memory Driver
Very High-Speed Memory Driver

54

-55°C to +125°C .

I 740°C to +70°C

2642 drw 04

I

II

I

6.67

6

t;)®

ADVANCE INFORMATION
IDT54/74FBT2244
IDT54/74FBT2244A
IDT54/74FBT2244C

HIGH-SPEED BiCMOS
MEMORY DRIVERS

Integr.ated Device Technology, Inc.

FEATURES:

DESCRIPTION:

•
•
•
•

The FBT series of BiCMOS Memory Drivers are built using
advanced BiCEMOSTM, a dual metal BiCMOS technology.
This technology is designed to supply the highest device
speeds while maintaining CMOS power levels.
The IDT54/74FBT2244 series are octal buffers/line drivers
where each output is terminated with a 25Q series resistor.
The FBT series of bus interface devices are ideal for use in
designs needing to drive large capacitive loads with low static
(DC) current loading. All data inputs have a 200mV typical
input hysteresis for improved noise rejection. This higher
output level in the high state will result in a significant reduction
in overall system power dissipation.

•
•
•
•
•

I DT54/74FBT2244 equivalent to the 54/74BCT2244
IDT54174FBT2244A 25% faster than the 2244
IDT54/74FBT2244C 10% faster than the 2244A
25Q output resistors reduce overshoot and undershoot
when driving MOS RAMs
Significant reduction in ground bounce from standard
CMOS devices
TIL compatible input and output levels
±10% power supply for both military and commercial
grades
JEDEC standard pinout for DIP, SOIC and LCC packages
Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

OEA------~aLT.>-----~

OEs
DAo

OAo

OBo

DBo

DAl

OAl

OBl

DBl

DA2

OA2

OB2

DB2

DA3

OA3

Vee

OEA
DAo
080
DAl
OBl
DA2
082
DA3
083
GND

P20-1
D20-1
5020-2

4
5

&

E20-1

10

19
18
17
16
15
14
13
12
11

OEB
OAo
DBo
OAl
DBl
0A2
DB2
OA3
DB3

DIP/SOIC/CERPACK
TOP VIEW

00 ~ 1L5 81{fl

INDEX

000> 0

32: :20';9
OB3

DAl
081
DA2
082
DA3·

DB3
2641 drw 01

]
]
]
]
]

4
5
6
7
8

18
17
16
15
14
9 1011 1213

l'

L20-2

[
[
[
[
[

OAo
DBo
OAl
DBl
0A2

rlr1rlr1rl

iD~iD~cD

O(!}OOO

2641 drw 02

LCC
TOP VIEW

BiCEMOS is a Uademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
~1990

Integrated Device Technology. Inc.

6.68

JUNE 1990
DSC.oo12/·

1

IDT54f74FBT2244/A1C
HIGH-SPEED BiCMOS MEMORY DRIVERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE(1)

PIN DESCRIPTION
Pin Names

Inputs

Description

OEA,OEB

3-State Output Enable Inputs

Dxx

Inputs

Oxx

Outputs

OEA,OEB

D

Output

L
L
H

L
H

L
H

X

Z

26411bIOl

NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance

ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

26411b102

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Commercial

Military

Unit

VTERM(2) Terminal Voltage
with Respect
toGND

-0.5 to +7.0

-0.5 to +7.0

V

VTERM(3) Terminal Voltage
with Respect
toGND

-0.5 to Vee

-0.5 to Vee

V

TA

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

Parameter(l)

Typ_

Unit

CIN

Input Capacitance

VIN = OV

6

pF

GoUT

Output
Capacitance

VOUT = OV

8

pF

Symbol

Conditions

NOTE:
26411b104
1. This parameter is measured at characterization but not tested.

NOTE:
26411b103
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal
voltage may exceed Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 1/0 terminals only.

6.68

II

2

IDT54f74FBT2244/A1C
HIGH-SPEED BiCMOS MEMORY DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = S.OV ± 10%; Military: TA
Symbol

= -55°C to +12S o C, Vcc = S.OV ± 10%

Test Condltions(l)

Parameter

Min.

Typ.(2)

Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

Vil

Input LOW Level

Guaranteed Logic LOW Level

-

-

0.8

V

IIH

Input HIGH Current

Vee

-

Il A

Input LOW Current

-

10

III

-10

Il A

10ZH

High Impedance

= Max.,
Vee = Max.,
Vee = Max.

-

50

Il A

10Zl

Output Current

-50

IlA

II

Input HIGH Current

-

100

Il A

VIK

Clamp Diode Voltage

-0.7

-1.2

10DH

Output Drive Current

10DL

Output Drive Current

los

Short Circuit Current

VOH

Output HIGH Voltage

VOL

= 2.7V
Va = 0.5V
Va

= Max., VI = 5.5V(4)
Vee = Min., IN = -18mA
Vee = Min., Va = 2.25V
Vee = Min., VA = 2.25V
Vee = Max;, Va = GND(3)
Vee = Min.
VIN = VIH or Vil

Vee

Output LOW Voltage

VH

Input Hysteresis

leeH

Quiescent Power
Supply Current

leel

= 2.7V
VI = 0.5V
VI

= 5V
Vee = Max.
VIN = GND or Vee
Vee

-35
50

10H = -1mA

2.4

= -12mA
10l = 1mA
10l = 12mA

2.0

-

10H

V

-

-

-

-60

V

mA
mA

-225

mA

-

V

-

V

-

0.15

0.5

V

-

0.35

0.8

V

-

200

-

mV

-

0.2

1.5

mA

leel
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

6.68

2641 tbl 05

3

IDT54174FBT2244fAlC
HIGH-SPEED BiCMOS MEMORY DRIVERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol

Test Condltlons(l)

Parameter

Max.

Unit

-

2.0

mA

VIN = Vee
VIN = GND

-

-

0.2S

VIN = Vee
VIN = GND

-

-

4.0

fi = 1OMHz, SO% Duty Cycle
OEA = OEB = GND
One Bit Toggling

VIN = 3.4V
VIN= GND

-

-

S.O

Vee = Max., Outputs Open

VIN = Vee
VIN = GND

-

-

6.S(5)

fi = 2.SMHz, SO% Duty Cycle
OEA = OEB = GND
Eight Bits Toggling

VIN = 3.4V
VIN = GND

-

-

14.S(5)

Quiescent Power Supply
Current (Inputs TIL HIGH)

Vee = Max.
VIN = 3.4v(3)

IceD

Dynamic Power Supply
Current(4)

Vee = Max., Outputs Open
OEA = OEB = GND
One Input Toggling
SO% Duty Cycle
Vee = Max., Outputs Open

Ie

Total Power Supply
Current(6)

Typ.(2)

-

~Iee

Min.

mN
MHz

mA

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (V IN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcpf2 + fi Ni)
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

26411b106

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

Symbol

Parameter

IDT54/74FBT2244

IDT54/74FBT2244A

Com'l.

Com'l.

Mil.

IDT54/74FBT2244C
Com'l.

Mil.

Condition(l) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.

Min.(2)

Mil.

Max. Min.(2) Max. Unit

-

6.7

-

-

-

-

-

-

-

-

-

-

ns

Output Enable Time

-

8.7

-

-

-

-

-

-

-

-

-

-

ns

Output Disable Time

-

7.8

-

-

-

-

-

-

-

-

-

-

ns

tPLH
tPHL

Propagation Delay
Dn to On

tPZH
tPZL
tPHZ
tPLZ

CL = SOpF
RL = soon

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

26411b107

6.68

4

I

IDT54174FBT2244/A1C
HIGH·SPEED BiCMOS MEMORY DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vee

SWITCH POSITION
o-7.0V

500n

50pF

1i

RT

soon

SET-UP, HOLD AND RELEASE TIMES

zxt

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

2641
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

.lCL

INPUT
DATA

Test

PULSE WIDTH

-= ~~V

I

________ -

OV

tsu ---t'l4--~

TIMING
INPUT _ _ _ _ _ _,

lOW-HIG~Ul~~

- 3V
V
_

6J

ASYNCHRONOUS CONTROL

=t-

HIGH-lOW-HIGH

PRESET - - - - , I--+--~---­ - 3V
- - + - - - - - - 1.5V
CLEAR
- OV
ETC. - - - - - ,

tbl OS

~ 1.5V
_ _ 1.SV

IW

PULSE

SYNCHRONOUS CONTROL
CLOCK

:~~t~~ vvJr
J
~tsu

- 3V
-1.5V

-------- -

ETC.

PROPAGATION DELAY

OV

ENABLE AND DISABLE TIMES
ENABLE

SAME PHASE
INPUT TRANSITION

DISABLE

)--........' + - - - - OV
3.5V

OUTPUT

VOL

VOH
SWITCH
OPEN

OPPOSITE PHASE
INPUT TRANSITION

OV

' - - - - " " - - - - OV
NOTES
2641 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; Zo ~ 500; tF ~ 2.Sn5;
tR ~ 2.Sn5.

6.68

5

IDT54174FBT2244/A1C
HIGH-SPEED BiCMOS MEMORY DRIVERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

XX

FBT

Temperature
Range

XXXXX
Device Type

X

x

Package

Process

~~lank
P

o

~--------------~ SO

L
E

Commercial
MIL-STD-883. Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

I 2244C

12244
2244A

Memory Driver
High-Speed Memory Driver
Very High-Speed Memory Driver

154
74

-55°C to + 125°C
O°C to +70°C

~----------------------~

~--------------------------------~I

2641 drw 03

II

6.68

6

t;)®
Integrated Device Technology. Inc.

ADV ANCE INFORMATION
IDT54/74FBT2373
I DT54/74FBT2373A
I DT54/74FBT2373C

HIGH-SPEED BiCMOS
OCTAL TRANSPARENT
LATCH DRIVERS

FEATURES:

DESCRIPTION:

• 25Q output resistors reduce overshoot and undershoot
when driving MOS RAMs
• Significant reduction in ground bounce from standard
CMOS devices
• TTL compatible input and output levels
• Low power in all three states
• ±10% power supply for both military and commercial
grades
• JEDEC standard pinout for DIP, SOIC and LCC
packages
• Military product compliant to MIL-STD-883, Class B

The FBT series of BiCMOS Latch Drivers are built using
advanced BiCEMOSTM, a dual metal BiCMOS technology.
This technology is designed to supply the highest device
speeds while maintaining CMOS power levels.
The IDT54/74FBT2373 series are 3-state, 8-bit latches
where each output is terminated with a 25.0 series resistor.
The flip-flops appear transparent to the data when Latch
Enable (LE) is HIGH. When LE is LOW, the data that meets
the set-up times is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
The FBT series of bus interface devices are ideal for use in
designs needing to drive large capacitive loads with low static
(DC) current loading. All data inputs have a 200mV typical
input hysteresis for improved noise rejection. This higher
output level in the high state will result in a significant reduction
in overall system power dissipation.

FUNCTIONAL BLOCK DIAGRAM

LE

OE

2640 drw 01

PIN CONFIGURATIONS
OE
00
Do
D1
01
02
D2
D3
03
GND

° °lw

INDEX

Vee

07
D7
D6
06
05
Ds
D4
04
LE

D1
01
02
D2
D3

8 r-.
000>0
]
]
]
]
]

32: :20'19

4
5
s
7
8

18 [ D7
17 [ Ds
L20-2
lS [ Os
15 [ 05
14 [ D5
10 11 1213

"1

9

r I r1 11 r I 11

MOW"" .".
O

OZ-IO
DlP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW

BiCEMOS is a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
4:>1990 Integrated Device Technology. Inc.

2640 drw 02

(!J

6.69

JUNE 1990
DSC-6003/·

1

IDT54f74FBT2373/A1C
HIGH-SPEED BiCMOS OCTAL TRANSPARENT LATCH DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE(1)

PIN DESCRIPTION
Pin Names

00- 07

Description
Data Inputs

LE

Latch Enables Input (Active HIGH)

OE

Output Enables Input (Active LOW)

00-07

3-State Latch Outputs

Outputs

Inputs

2640 till 05

On

LE

OE

On

H

H

L

H

L

H

L

L

X

L

L

an

X

X

H

Z

NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance

CAPACITANCE (TA = +25°C, f = 1.0MHz)

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage
with Respect
toGND
Operating
TA
Temperature
TSIAS
Temperature
Under Bias
TSTG

Storage
Temperature

PT
lOUT

Power Dissipation
DC Output Current

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

2640 till 06

-0.5 to Vee

Symbol

V

Parameter(l)

CIN

Input Capacitance

COUT

Output
Capacitance

Conditions

= OV
VOUT = OV
VIN

Typ.

Unit

6

pF

8

pF

NOTE:
2640 till 02
1. This parameter is measured at characterization but not tested.

a to +70

-55 to +125

°C

-55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

0.5
120

0.5
120

W
mA

NOTES:
2640 till 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability. No terminal voltage may
exceed Vcc by +O.5V unless otherwise noted.
2. Inputs and Vee terminals only.
3. Outputs and I/O terminals only.

6.69

I

2

IDT54174FB T2373!AlC
HIGH-SPEED BiCMOS OCTAL TRANSPARENT LATCH DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 10%; Military: TA

= -55°C to +125°C, Vcc = 5.0V ± 10%
Min.

Typ.(2)

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

IIH

Input HIGH Current

Vee = Max., VI = 2.7V

IlL

Input LOW Current

Vee = Max., VI = 0.5V

10ZH

High Impedance

Vee = Max.

10ZL

Output Current

Symbol

Test Conditions(1)

Parameter

I Vo = 2.7V

I Vo = 0.5V

Max.

Unit

-

-

V

-

0.8

V

-

-

10

IlA

-

-10

Il A

50

Il A

-

-

-

-50

Ii

Input HIGH Current

Vee = Max., VI = 5.5V

100

Clamp Diode Voltage

Vee = Min., IN = -18mA

-

-

VIK

-0.7

-1.2

V

los

Short Circuit Current

Vee = Max., Vo = GND(3)

-60

-

-225

mA

VOH

Output HIGH Voltage

Il A

Vee = Min.

10H = -1mA MIL.

2.4

3.3

10H = -12mA COM'L.

2.0

3.2

-

V

VIN = VIH or VIL

10L = 1mA COM'L.

-

0.15

0.5

V

10L = 12mA MIL.

V

VOL

Output LOW Voltage

-

0.35

0.8

VH

Input Hysteresis

Vee = 5V

-

200

-

mV

lee

Quiescent Power
Supply Current

Vee = Max.
VIN = GND or Vee

-

0.2

1.5

mA

10DH

Output Drive Current

Vee = Min., Vo = 2.25V

-35

Output Drive Current

Vee = Min., Vo = 2.25V

50

-

-

mA

IODL

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee ~ S.OV, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

6.69

V

mA
2640 tbl 03

3

IDT54f74FBT2373/A1C
HIGH·SPEED BICMOS OCTAL TRANSPARENT LATCH DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol
~Iee

Parameter
Quiescent Power Supply
Current (Inputs TIL HIGH)

leeD

Dynamic Power Supply
Current(4)

Ie

Total Power Supply
Current(6)

Test Conditions(l)

Min.

Vee = Max.
VIN = 3.4V(3)

Typ.(2)

Max.

-

-

2.0

Unit
rnA

Vee = Max., Outputs Open
OEl = OE2 = GND
One Input Toggling
50% Duty Cycle

VIN = Vee
VIN = GND

-

-

0.25

mAl
MHz

Vee = Max., Outputs Open

VIN = Vee
VIN= GND

-

-

4.0

mA

fi = 1OMHz, 50% Duty Cycle
OE1 = OE2 = GND
One Bit Toggling

VIN = 3.4V
VIN=GND

-

-

5.0

Vee = Max., Outputs Open

VIN = Vee
VIN = GND

-

-

6.5(5)

fi = 2.5MHz, 50% Duty Cycle
OEl = OE2 = GND
Ten Bits Toggling

VIN = 3.4V
VIN = GND

-

-

14.5(5)

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient, and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fi Ni)
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (V IN = 3.4V)
DH = Duty Cycie for TIL Inputs High
NT = Number of TIll inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

6.69

2640 tbl 04

4

IDT54f74FBT2373fAlC
HIGH-SPEED BiCMOS OCTAL TRANSPARENT LATCH DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

Symbol

Parameter

IDT54/74FBT2373

IDT54/74FBT2373A

Com'l.

Com'l.

Mil.

IDT54/74FBT2373C
Com'l.

Mil.

Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Mln.(2) Max.

Min.(2)

Mil.

Max. Min.(2) Max.

Unit

-

-

-

-

-

-

-

-

-

-

-

-

ns

Output Enable Time

-

-

-

-

-

-

-

-

-

-

-

-

ns

tPHZ
tPLZ

Output Disable Time

-

-

-

-

-

-

-

-

-

-

-

-

ns

tPLH
tPHL

Propagation Delay
LE to On

-

-

-

-

-

-

-

-

-

-

-

-

ns

tsu

Set-up Time
HIGH or LOW
Dn to LE

-

-

-

-

-

-

-

-

-

-

-

-

ns

tH

Hold Time
HIGH or LOW
Dn to LE

-

-

-

-

-

-

-

-

-

-

-

-

ns

tw

LE Pulse Width
HIGH or LOW

-

-

-

-

-

-

-

-

-

-

-

-

ns

tPLH
tPHL

Propagation Delay
Dn to On

tPZH
tPZL

CL = SOpF
RL = soon

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

2640 tbl 07

6.69

5

IDT54174FBT2373!AlC
HIGH·SPEED BiCMOS OCTAL TRANSPARENT LATCH DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION

TEST CIRCUITS FOR ALL OUTPUTS

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

2640 tbl 08
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zzt

PULSE WIDTH

-= ~~V

1

___..-..__~ -

OV

-

3V

tSU-=

Yo
Y,
Y2
Y3
Y4
Ys
Y6
Y7
Ya
Y9
OE2

02
03
04
NC
05
06
07

~
o

00-9

Vee

OE,
00
0,
02
03
04
05
06
07
Oa
09
GNO

OE,

Y2
Y3
Y4
NC
Ys
Y6
Y7

OE2

.IT

10

Y0-9

2516 drw 03

coa>OONa>CO

00

2516 drw 02A

IW >- >-

~Zo

2516 drw 028

LCC
TOP VIEW

DlP/CERPACKlSOIC
TOP VIEW

PIN DESCRIPTION
Name

1/0
I

OEI
OE2
01

I

YI

0

Description
When both are LOW, the outputs are
enabled. When either one or both are
HIGH the outputs are High Z.
1O-bit data input.
1O-bit data output.
2516 tbl 02

FUNCTION TABLES
IDT54/74FBT2827 AlB (Non-lnverting)(1)
OE,

Inputs
OE2

Di

Output
Vi

L
L

L
L

L
H

L
H

H
X

X
H

X
X

Z
Z

NOTE:
1. H = HIGH, L

IDT54/74FBT2828A/B (Inverting)(1)
OE1

Inputs
OE2

Di

Output
Vi

Transparent

L
L

L
L

L
H

H
L

Transparent

Three-State

H
X

X
H

X
X

Z
Z

Three-State

Function

2516tbl03

= LOW, X = Don't Care, Z = High

Impedance

NOTE:
1. H = HIGH, L

6.70

Function

2516 tbl 04

= LOW,

X

= Don't Care, Z = High

Impedance

2

IDT54174FBT2827A1BIIDT54/74FBT2828A1B
HIGH SPEED BiCMOS 10-BIT MEMORY DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE (TA = +25°C, f = 1.0MHz)

ABSOLUTE MAXIMUM RATINGS(1)
Com'l.

Symbol
Rating
VTERM(2) Terminal
Voltage with
Respect to GND
VTERM(3) Terminal
Voltage with
Respect to GND

-0.5 to +7.0

Unit

Mil.

-0.5 to Vee

-0.5 to Vee

V

TA

Operating
Temperature

a to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature.

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

Parameter(1)

Typ.

Unit

CIN

Input Capacitance

VIN = OV

6

pF

COUT

Output
Capacitance

VOUT = OV

8

pF

Symbol

V

-0.5 to +7.0

Condition

NOTE:
1. This parameter is measured at characterization but not tested.

2516 tbl 07

NOTE:
2516 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty. No terminal voltage may exceed Vec by +O.5V
unless otherwise noted.
2. Input and Vce terminals only.
3. Outputs and 110 terminals only.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 10%; Military: TA = -55°C to +125°C, Vcc = 5.0V ± 10%
Symbol

Test Condltion(1)

Parameter

Min.

Typ.(2)

Unit

Max.

VIH

Input HIGH Level

Guaranteed Logic High Level

2.0

-

-

V

Vil

Input LOW Level

Guaranteed Logic Low Level

-

0.8

V

IIH

Input HIGH Current

Vee = Max.

VI

-

~A

Input LOW Current

Vee = Max.

VI = 0.5V

-10

~A

Vee

= Max.

Va = 2.7V

-

10

III

50

~A

= 2.7V

-

10ZH

High Impedance

10Zl

Output Current

II
VIK

Input HIGH Current
Clamp Diode Voltage

Vee = Max., VI = 5.5V
Vee = Min., IN = -18mA

10DH

Output Drive Current

Vee = Min., Va = 2.25V

IODl

Output Drive Current

Vee = Min., Va = 2.25V

50

los

Short Circuit Current

Vee = Max., Va = GND(3)

-60

-

VOH

Output HIGH Voltage

10H = -1mA

2.4

3.3

Vce = Min.

10H = -12mA

2.0

VIN = VIH or Vil

10l = 1mA

-

Val

Output LOW Voltage

VH

Input Hysteresis

lecH
leez
leel

Quiescent Power
Supply Current

Va = 0.5V

-35

10l= 12mA

Vee = Max.
VIN = GND or Vee

-0.7

-50
~A

100
-1.2

V

-

mA

-

mA

-225

mA
V

3.2

-

0.1

0.5

0.35

0.8

200

-

mV

0.2

1.5

mA

V
V
V

NOTES:
1. For condition shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

6.70

2516 tbl 05

3

I

IDT54174FBT2827 AlB/IDT54/74FBT2828A1B
HIGH SPEED BiCMOS 10·BIT MEMORY DRIVERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol

Test Condltlon(1)

Parameter

Min.

Typ.

Max.

Unit

-

0.5

2.0

mA

VIN = Vee
VIN =GND

-

0.15

0.25

mAl
MHz

VIN = Vee
VIN= GND
VIN .. 3.4V
VIN= GND

-

1.7

4.0

-

2.0

5.0

VIN = Vee
VIN = GND

-

4.0

7.8(5)

fi = 2.5MHz, 50% Duty Cycle
OEl = OE2 = GND
Ten Bits Toggling

VIN = 3.4V
VIN= GND

-

6.5

17.8(5)

~Iee

Quiescent Power Supply Current
(Inputs TTL HIGH)

Vee = Max.
VIN = 3.4V(3)

leeD

Dynamic Power Supply Current(4)

Vee = Max., Outputs Open
OEl = OE2 = GND
One Input Toggling
50% Duty Cycle

Ie

Total Power Supply Current(6)

Vee = Max., Outputs Open

fi = 1OMHz, 50% Duty Cycle
OEl = OE2 .. GND
One Bit Toggling
Vee = Max., Outputs Open

mA

NOTES:
1. For condition shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs atVcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT = INPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fi Ni)
Icc = Quiescent Current
~Icc = Quiescent Current
DH = Duty Cycle for a TIL High Input (VIN = 3.4V)
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in MHz.

25161b108

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FBT2827B

FBT2827A
Symbol

Parameter

Commercial
Min.(2)
Max.

Military
Min.(2)
Max.

Commercial
Min.(2)
Max.

Military
Min.(2)
Max.

tPHL
tPLH

Prop Delay, Di to YI

-

7.0

-

7.5

-

5.0

-

6.5

tPZH
tPZL

Output Enable Time OE to YI

-

13.0

-

14

-

8.0

-

9.0

tPHZ
tPLZ

Output Disable Time OE to YI

-

13.0

-

14

-

7.0

-

8.0

FBT2828A
Symbol

Parameter

Commercial
Min.<2)
Max.

FBT2828B

Military
Min.(2)
Max.

Commercial
Min.(2)
Max.

Military
Mln.(2)
Max.

tPHL
tPLH

Prop Delay, Di to YI

-

8.0

-

8.5

-

5.5

-

6.5

!PZH
tPZL

Output Enable Time OE to YI

-

12.0

-

13.0

-

8.0

-

9.0

tPHZ
tPLZ

Output Disable Time OE to YI

-

14.0

-

15.0

-

7.0

-

8.0

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested

25l61b109

6.70

4

IDT54174FBT2827A1B/IDT54/74FBT2828A1B
HIGH SPEED BiCMOS 10·BIT MEMORY DRIVERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vcc

SWITCH POSITION
0-.7.0V

soon

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All O1her Outputs

Open

2516tbll0
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

Z&t

PULSE WIDTH

-= ~~V

I

""~~""-~ _ OV

tsu --40j4---ti

TIMING
INPUT

lOW-HIG~~~~

- 3V
- - - 1 - - - - - - 1.SV
- OV

ASYNCHRONOUS CONTROL
PRESET - - - -.....
CLEAR
ETC. - - - - ,
SYNCHRONOUS CONTROL
CLOCK

:~~i~~ ~tsu
vvJr I
ETC.

-

--+------

3V
1.SV
OV

=f-

HIGH-laW-HIGH

_

~ '5V

'w

__ 1.SV

PULSE

- 3V
-1.SV
---_.-....... - OV

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE
3V

SAME PHASE
INPUT TRANSITION

OV
3.SV

OUTPUT

VOL
VOL
OUTPUT
NORMALLY
HIGH

3V
OPPOSITE PHASE
IN PUT TRANSITION

VOH
SWITCH
OPEN
OV

OV

NOTES
2516drw05
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate S 1.0 MHz; Zo S son; tF :S 2.Sns;
tR:S 2.Sns.

6.70

5

II

IDT54174FBT2827AJB/IDT54/74FBT2828AJB
HIGH SPEED BiCMOS 10·BIT MEMORY DRIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

xx
Temp. Range

FBT

XXXXX

x

x

Device Type

Package

Process

Commercial
MIL-STD-883, Class B

P

'------------j

o

SO

L
E
2827 A
'--_ _ _ _ _ _ _ _ _ _ _ _ _~ 2828A
2827B
1 2828B
1

' - - - - - - - - - - - - - - - - - - - - - - 11 54

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Non-inverting 1a-Bit Memory Driver
Inverting 1a-Bit Memory Driver
High Speed Non-inverting 1a-Bit Memory Driver
High Speed Inverting 1a-Bit Memory Driver
-55°C to + 125°C

I 740°C to +70°C
2516 drw 04

6.70

6

(;)®

ADV ANCE INFORMATION
IDT54/74FBT2841 A
IDT54/74FBT2841 B
IDT54/74FBT2841 C

HIGH-SPEED BiCMOS
1O-BIT MEMORY
LATCHES

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• 25Q output resistors reduce overshoot and undershoot
when driving MaS RAMs
• Significant reduction in ground bounce from standard
CMOS devices
• TIL compatible input and output levels
• Low power in all three states
• ± 10% power supply for both military and commercial
grades
• JEDEC standard pinout for DIP, SOIC and LCC
packages
• Military product compliant to MIL-STD-883, Class B

The FBT series of BiCMOS Memory Drivers are built using
advanced BiCEMOSTM, a dual metal BiCMOS technology.
This technology is designed to supply the highest device
speeds while maintaining CMOS power levels.
The IDT54/74FBT2841 series are 3-state, 10-bit latches
where each output is terminated with a 25Q series resistor.
The FBT series of memory line drivers are ideal for use in
designs needed to drive large capacitive loads with low static
(DC) current loading. They are also designed for rail-to-rail
output switching. This higher output level in the high state will
result in a significant reduction in overall system power
dissipation.

FUNCTIONAL BLOCK DIAGRAM
Do

Ds

DN

DN-1

D6

D

LE

6

I
Yo

Ys

Y1

YN-1

Y6

PIN CONFIGURATIONS
OE
Do
D1

2599 drw at

~ 0lwO

INDEX

Vee

D4

Y1
Y2
Y3
Y4

Ds

Ys

D6
D7
DB

4 3

J6

NC

JB

D6
D7

2

~

I I

28 27 26

~

J5

D2
D3
D4

Ds

YB
Y9

GND

a

L......JL...JL-JIIL-JL...JL...J

Y6
Y7

D9

8

Oooz>>->-

Yo

D2
D3

YN

J7

L28-1

J9
J 10
J11

2S[
24 [
23 [
22[
21 [

Y2
Y3
Y4

NC
Ys

20[

Y6

19[

Y7

12 13 14 15 16 17 1B

LE

->-

2599 drw 02

(!)

DIP/SOIC/CERPACK
TOP VIEW

Lee
TOP VIEW

BiCEMOS is a trademark of Integrated Device Techology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1990 Integrated Device Technology. Inc.

6.71

JUNE 1990
DSC-6014/-

1

IDT54f74FBT2841 AlBIC
HIGH-SPEED BiCMOS 10-BIT MEMORY LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE(1)

PIN DESCRIPTION
Name

1/0

Do - 07

I

The latch data inputs.

LE

I

The latch enable input. The latches are transparent when LE is HIGH. Input data is latched
on the HIGH-to-LOW transition.

YO-Y7
OE

a
I

Description

Inputs

The 3-state latch outputs.
The output enable control. When OE is LOW,
the outputs are enabled. When OE is high, the
outputs YI are in the high-impedance (off)
state.

Internal

Outputs

OE

LE

DI

QI

VI

H

X

X

X

Z

High Z

H

H

L

L

Z

High Z

H

H

H

H

Z

High Z

H

L

X

NC

Z

Latched (High Z)

L

H

L

L

L

Transparent

L

H

H

H

H

Transparent

L

L

X

NC

NC

25991b105

NOTE:
1. H = HIGH, L = LOW, X = Don't Care, NC
Impedance

Function

Latched
25991b1 06

= No Change, Z = High

LOGIC SYMBOL

o

o

10
>-' .... / , . ----'-

Y

LE
LE------'
OE---------------~

2599 drw 03

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage

CAPACITANCE

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

Symbol

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

= +25°C f = 1 OMHz)

CIN

Input Capacitance

COUT

Output Capacitance

Conditions

= OV
VOUT = OV
VIN

Typ.

Unit

6

pF

8

pF

NOTE:
25991b102
1. This parameter is measured at characterization but not tested.

with Respect
toGND
TA

(TA

Parameter(1)

NOTES:
25991b101
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +O.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Outputs and I/O terminals only.

6.71

2

IOT54174FB T2841 AlBIC
HIGH·SPEED BiC~mS 10·BIT MEMORY LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, vcc = 5.0V ± 10%; Military: TA

= -55°C to + 125°C, Vcc = 5.0V ± 10%
Min.

Typ.(2)

Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

V

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

-

0.8

V

IIH

Input HIGH Current

Vee = Max., VI = 2.7V

-

-

10
·10

Il A
IlA

50

Il A

Symbol

Test Conditions(1)

Parameter

IlL

Input LOW Current

Vee = Max., VI = 0.5V

10lH

High Impedance

Vee = Max.

lOlL

Output Current

Va = 2.7V

-

Va = 0.5V

II

Input HIGH Current

Vee = Max., VI =5.5V(4)

VIK

Clamp Diode Voltage

Vee = Min., IN = ·18mA

-

·0.7

10DH

Output Drive Current

Vee = Min., Vo = 2.0V

-35

10DL

Output Drive Current

Vee = Min., Vo = 2.0V

50

los

Short Circuit Current

Vee = Max., Vo = GND(3)

-60

-

VOH

Output HIGH Voltage

Vee = Min.

10H = -1mA

2.4

3.3

VIN = VIH or VIL

10H = -12mA

2.0

10L = 1mA

-

VOL

Output LOW Voltage

10L = 12mA
VH

Input Hysteresis

Vee = 5V

lecH
Icel
lecL

Quiescent Power
Supply Current

Vee = Max.
VIN = GND or Vee

·50
Il A
V

100
·1.2

-

mA

-

mA

-225

mA
V

3.2

-

0.1

0.5

V

0.35

0.8

200

-

mV

0.2

1.5

mA

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

V
V

2599 tbl 03

I

6.71

3

IDT54f74FBT2841 AlBIC
HIGH·SPEED BICMOS 10·BIT MEMORY LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol
t.lee

Parameter
Quiescent Power Supply
Current (Inputs TTL HIGH)

Test Conditlons(1)
Vee = Max.
VIN = 3.4V(3)

leeD

Dynamic Power Supply Current(4)

Vee = Max., Outputs Open
OE = GND
One Input Toggling
LE = Vee
50% Duty Cycle

Ie

Total Power Supply Current(b)

Typ.(2)

-

-

Max.
2.0

Unit
mA

VIN = Vee
VIN = GND

-

-

0.25

mAl
MHz

Vee = Max., Outputs Open
fi = 1OMHz, 50% Duty Cycle

VIN = Vee
VIN = GND

-

-

4.0

mA

OE = GND, LE = Vee
One Bit Toggling

VIN = 3.4V
VIN = GND

-

-

5.0

Vee = Max., Outputs Open
fi = 2.5MHz, 50% Duty Cycle

VIN = Vee
VIN = GND

-

-

7.8(5)

OE = GND, LE = Vee
Eight Bits Toggling

VIN = 3.4V
VIN = GND

-

-

17.8(5)

Min.

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient, and maximum loading.
3. Per TIL driven input (V IN = 3.4V); all other inputs at vee or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laUIEscENT +IINPUTS + IDYNAMIC
Ic = Icc + tolccDHNT + ICCD(fcP/2 + liNi)
Icc = Quiescent Current
tolcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number 01 TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
Icp = Clock Frequency lor Register Devices (Zero for Non-Register Devices)
Ii = Input Frequency
Ni = Number 01 Inputs at Ii
All currents are in milliamps and all Irequencies are in megahertz.

6.71

2599 tbl 04

4

IDT54f74FBT2841 AlB/C
HIGH-SPEED BiCMOS 10-BIT MEMORY LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
54f74FBT2841A
Com'1.
Symbol
tPLH
tPHL

Parameter
Data (01) to Output
(YI) (LE = HIGH)

tPLH
tPHL

-

-

-

-

-

-

-

-

-

-

-

ns

-

-

-

-

-

-

-

-

-

-

-

-

ns

= 50pF
= 500n
CL = 50pF
RL = 500n
CL = 3OOpF(3)
RL = 500n
CL = 50pF
RL = 500n
CL = 50pF
RL = 500n
CL = 300pF(3)
RL = 500n
CL = 5pF(3)
RL = 500n

-

-

-

-

-

-

-

-

-

-

-

-

ns

-

-

-

-

-

-

-

-

-

-

-

-

ns

-

-

-

-

-

-

-

-

-

-

-

-

ns

-

-

-

-

-

-

-

-

-

-

-

-

ns

-

-

-

-

-

-

-

-

-

-

-

-

ns

-

-

-

-

-

-

-

-

-

-

-

-

ns

-

-

-

-

-

-

-

-

-

-

-

-

ns

-

-

-

-

-

-

-

-

-

-

-

-

ns

Data to LE Hold Time

tPLH

Latch Enable (LE) to YI

tw

LE Pulse Width
HIGH/LOW

tPZH

Output Enable Time
OE tOYI

tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ

Output Disable Time
OE tOYI

Unit

-

Data to LE Set-up Time CL

tPHL

Mil.

Min.(2) Max. Min.(2) Max.

= 50pF
= 500n
CL = 3OOpF(3)
RL = 500n
CL
RL

tH

tPLH

54f74FBT2841C
Com'1.

Mil.

Com'1.

Condition(1) Mln.(2) Max. Mln.(2) Max. Min.(2) Max. Min.!2) Max.

tsu

tPHL

54f74FBT2841 B

MIL

RL

CL
RL

= 50pF
= 500n

NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed, but not tested.

2599 tbl 07

I

6.71

5

IDT54f74FBT2841 AlBIC
HIGH·SPEED BiCMOS 10·BIT MEMORY LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS

SWITCH POSITION

TEST CIRCUITS FOR ALL OUTPUTS

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

2599 tbl DB
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zxt

PULSE WIDTH

--= OV~~V

J

"'-..K.~~ -

tsu - t o j + - - - + i

TIMING
INPUT _ _ _ _ _ _-'

- 3V
V
_

6S

lOWHIG~J~~
HIGH-lOW-HIGH

ASYNCHRONOUS CONTROL
PRESET - - - - ,
CLEAR
ETC. - - - - ,
SYNCHRONOUS CONTROL
CLOCK

-

3V

-

1.5V
OV

-

3V

--+------

:~~~~~ vvJr
~tsu
J

ETC.

"'-...JIIIt.~~

=t

~ 15V
tw

--1.5V

PULSE

-1.5V
- OV

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

_--__..----3V
SAME PHASE
INPUT TRANSITION

OV
_--~.+-VOH

OUTPUT

-1.5V
VOL
3V

OPPOSITE PHASE
INPUT TRANSITION

NOTES
2599 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate:s 1.0 MHz; Zo :s son; tF :S 2.Sns;
tR:S 2.Sns.

6.71

6

IDT54174FBT2841 AlBIC
HIGH-SPEED BiCMOS 10-BIT MEMORY LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

xx
Temperature
Range

FBT XXXX
Device
Type

x

x

Package

Process

~~Iank
P

SO
L
E

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

2841 A
2841B
2841 C

Non-inverting 10-Bit Memory Driver
High-Speed Non-inverting 1O-Bit Memory Driver
Very High-Speed Non-inverting 10-Bit Memory Driver

54
74

-55°C to + 125°C
OOto+70°C

o

L--_ _ _ _ _ _ _- j

L..-_ _ _ _ _ _ _ _ _ _ _-I

L..-------------------I

Commercial
MIL-STD-883, Class B

2599 drw 04

II

6.71

7

I

APPLICATION AND TECHNICAL NOTES

•

I

TABLE OF CONTENTS

PAGE
APPLICATION AND TECHNICAL NOTES
Complex Logic Products Technical Notes
TN-02
Build a 20M IP Data Processing Unit ............................................................................. 7.1
TN-03
Using the IDT49C402A ALU .......................................................................................... 7.2
Complex Logic Products Application Notes
AN-03
Trust Your Data with A High-Speed CMOS 6-, 32- or 64-Bit EDC ............................... 7.3
AN-06
16-Bit CMOS Slices - New Building Blocks Maintain Microcode Compatibility
Yet Increase Performance .................................................................................... 7.4
FIR Filter Implementation Using FIFOs and MACs ....................................................... 7.5
AN-17
AN-24
Designing with the IDT49C460 and IDT39C60 Error Detection and
Correction Units .................................................................................................... 7.6
Implementation of Digital Filters Using IDT7320, IDT721 0, IDT7216 ........................... 7.7
AN-32
Address Generator in Matrix Unit Operation Engine ..................................................... 7.8
AN-35
Designing High-Performance Systems Using the lOT PaletteDACTM ........................... 7.9
AN-37
Using the IDT75C457's PaletteDACTM in True Color and Monochrome Graphics
AN-63
Applications ........................................................................................................ 7.10
AN-64
Protecting Your Data with lOT's 49C465 32-Bit Flow-thruEDCTM Unit ......................... 7.11
AN-65
Using IDT73200 or IDT73210 as Read and Write Buffers with R3000 ........................ 7.12
Standard Logic Application Notes ....................................................................................................................... 7.13
AN-47
Simultaneous Switching Noise ..................................................................................... 7.14
AN-48
Using High-Speed Logic ............................................................................................... 7.15
AN-49
Characteristics of PCB Traces ..................................................................................... 7.16
AN-50
Series Termination ....................................................................................................... 7.17
AN-51
Power Dissipation in Clock Drivers ............................................................................... 7.18
AN-52
FCT Output Structures and Characteristics ................................................................. 7.19
AN-53
Power-Down Operation ................................................................................................ 7.20
AN-54
FCT-T Logic Family ...................................................................................................... 7.21
Standard Logic Technical Bulletins ..................................................................................................................... 7.22

I

II

7.0

,;5

TECHNICAL
NOTE
TN-02

BUILD A 20 MIP DATA
PROCESSING UNIT

Integrated Device Technology, Inc.
by Michael J. Miller

INTRODUCTION

BALANCED PATHS

With the latest generation of CMOS devices from lOT, it is
now possible for a user to design a data processing unit that
will operate at 20 million instructions per second. The devices
that make this possible are in the MICROSLICETM family
which provides such VLSI building blocks as sequencers and
ALUs, a new generation of CMOS RAM devices which
support 15ns access times, and a memory interface family
called FCTwhich is 20-50% fasterthanthe equivalentfunctions
in Fairchild FASTTM. Putting these devices together, the
designer can construct a microprogrammed machine which
has a system clock speed of 20 MHz. These microprogram
designs can be used in a variety of application areas where
high-speed processing and control sequences are required.
Such application areas include dedicated graphics engines,
digital signal processing, I/O controls for disk and tape,
medical imaging, process control and special purpose
computers.

Formaximum performance and highest return on hardware
investment, all critical paths should be as well-balanced as
possible. Figure 1 shows a simplified block diagram of the
basic structure of a microprogrammed machine.
Microprogrammed machines are composed of static RAM,
registers, latches and combinational logic. There are no
dynamic elements involved. In the block diagram, there are
three main elements: next state generator, current state
register, and data processing element. The next state
generator takes the current state information and generates
the next state to be executed. The next state is stored into a
current state register by the system clock on each clock
cycle. Out of the current state register flow all control lines to
the rest of the system. These control lines must control the
next state generation as well as the data processing elements.
The data processing elements might include such devices
as fixed and floating point ALUs, registerfiles and I/O devices.
These data processing elements can generate status
information which also may be fed back into the next state
generator such that the next state is determined by a
combination of current state and the current status.

Status
Co ntrol

,-----.

Next State
Generator

Ck +-

-

Data Processing
Elements

Control

Current State
Reg

I

Ck

Ck

I

II

Syste m
Clock

I
2582 drw 01

Figure 1. Simplified Block Diagram of a Microprogrammed Machine

MICROSLICE is a trademark 01 Integrated Device Technology. Inc.
FAST is a trademark 01 National Semiconductor Co.
©1990 Integrated Device Technology. Inc.

7.1

1/90

1

BUILD A 20 MIP DATA PROCESSING UNIT

TECHNICAL NOTE TN-{l2

Most designs generally have two critical paths. One path
incorporates the time delay from the current state register
clocked by the system clock, through the next state generator,
and a set up into the current state register. This is called the
control path (Path B in Figure 2). The other path generally
involved is from the system clock, through the current state
output which controls the data processing elements which
generate status which, in turn affects the next state selected.
This is called the data path (Path A in Figure 2). In order to
break up the data path delay, the status can be put in a register
rather than directly into the next state generator. For the
highest performance designs, a status register is used.
Therefore, when optimizing a microprogrammed design, these
two paths must be taken into consideration and balanced for
maximum performance.

CONTROL PATH
The control path can be designed using the IOT49C410A
as the heart of the next state generation mechanism. Figure
2 shows the block diagram of a data processing unit using lOT
devices. The lOT49C41 OA is used to generate the next
address which is put into a RAM referred to as a writable
control store (WCS). Out of the WCS comes the next
instruction to be executed. This is stored in a register built of
IOT74FCT374A octal registers. This is the current state
register and is often referred to as the pipeline register. The
pipeline register can be viewed as containing several control
fields - one control field for the lOT49C41 OA, another for the
data processing elements, as well as additional fields for
control of other elements in the system.
The field which controls the lOT 49C41 OA contains
instructions for the IOT49C410A, as well as bits to control a
multiplexer which selects status bits from a current status
register. The particular status bit which is selected out of the
status register is used in combination with the instruction of the
IOT49C41 OA to generate the next address. This latter path is
the critical path. In the block diagram, the critical path in the
control half is labeled as path B. All cycles start out with a
system clock which generates a new instruction in 6.5ns(1)
using the IOT74FCT374A. This current instruction then
controls the status mux which can be constructed of a 74F151
using the Z bar output, which is the fastest output of the mux.
The propagation delay is 9ns. The condition code input on the
lOT49C41 OA will then be combined together with the
instruction input and generate a new microprogram address in
16ns. This new address can then be used to access the next

microprogram instruction in 15ns using the I OT6167 A-15
static RAMs. At this point in the cycle, the microprogram
instruction must be placed in the pipeline register with a 2.5ns
set-up time. The total control loop then is 49ns, thus
accommodating 20MHz operation in the control path.

THE DATA PATH
The other critical path in the data processing unit is the data
path which includes elements for processing data. The data
may, for example, be data coming off a disk controller,
graphics information or DSP data, just to name a few
possibilities. Shown in the block diagram is an IOT49C402A
which is a 16-bit cascadable binary ALU with 64 x 16 register
file. The critical path starts with the system clock which
generates a new instruction at the output of the pipeline
register in 6.5ns. The field in the pipeline register is then fed
into an IOT49C402A. This instruction controls the operation
of the ALU unit, as well as providing addresses to select
operands out of the internal 64 word register file. As a
consequence of the.data coming out of the register file into the
ALU and the ALU instruction inputs, a result is generated. The
ALU result can be brought out on the Y -bus or stored back into
the register file. Status flags which correspond to Zero, Sign
and Overflow are also output. The instruction and AlB
addresses delay to status flags and Y output is 37ns. The
status flags require a 2.5ns set-up time into the status register.
Therefore, this path totals 45ns (labeled Path A) and matches
the control path fairly well.

CONCLUSION
It can be seen that, by using the latest in CMOS devices
from lOT, the designer is capable of creating a machine that
can execute 20 million instructions per second. This type of
performance is almost twice that achievable a year ago using
the 2900 family and corresponding devices. With the previous
devices, the typical control path required 100ns to execute
and the data path typically took BOns to execute. This was
using the fastest available devices implemented in bipolar
TIL interface-type technology. Not only are the CMOS
devices from lOT extremely fast, they also consume a
minimum of power-75mAforthe IDT49C410A and 125mA
for the IOT49C402A. Each of the IDT74FCT374s typically
consume 10mA. Therefore, it is not unreasonable to expect
the designerto achieve a design which consumes about 1 watt
for the ALU and sequencer shown in the simplified block
diagram in Figure 2.

NOTE:
1. Times given are worst case maximum over commercial range.

7.1

2

BUILD A 20 MIP DATA PROCESSING UNIT

TECHNICAL NOTE TN-02

Data Input Bus

o
IOT49C402A

IOT49C410A

~""-~-~A.B

y

y

Data Output Bus

A
01

16K x 1
SRAM

IOT6167A
DO

<1"-------11------<>--------1---+--- System clock
20 MHz

Control for other
system elements

Path

Path@

@

CP~Q
CC~Y

Flags & Y
Set-up

6.5 ns
37.0 ns
2.5 ns

RAM
Set-up

6.5 ns
9.0 ns
16.0 ns
15.0 ns
2.5 ns

Total

45.0 ns

Total

45.0 ns

MUX (,F151)
CP~Q
ABI~

II
2582 drw 02

Figure 2. More Detailed Diagram of a DPU Capable
of 20 MIPS Using lOT MICROSLICE Parts

7.1

3

t;)®

TECHNICAL
NOTE
TN-03

USING THE
IDT49C402A ALU

Integrated Device Technology. Inc.

by Michael J. Miller
ALUs from IDT. This high-speed ALU (shown in Figure 1) is
capable of supporting 20MHz operations. This phenomenal
speed is a result of CEMOS"", a single-poly double-metal
structure using 1.2 micron gate lengths designed for highperformance and high-reliability.

The MICROSLlCE'" family consists of high-performance
VLSI building blocks that provide such functions as ALUs,
sequencers for building complex finite state machines, registerfiles and support devices. The IDT49C402A is a member
of this MICROSLICE family and is the first in a series of 16-bit

DATA IN

II

;.

r---

RAM SHIFT
,

READ
ADDR

f--

6

READI
WRITE
ADDR

f--

6"

-l7---

I

I aSHIFT I

{7

'7

DATA
A
ADDRESS

IN

64 x 16
RAM

I

B

ADDRESS

U
tr

7

a REGISTER

f----CJ

CP

DATA OUT

I

LOGIC 0

I

I

I 2-{)
I ~3
I s-s
19

8=:

8=:

~J ~ 7

C
~O
Instruction
Decode

MSS

D

A

N

7

'<;

7

a

0

B

SOURCE SELECTOR

T
R

S

R

~O

L

L

I

~ 7

\

G/F15
P/OVR
C n + 16

\

R

SL

_\
\

F=O

ALU

Cn

\

t

-I DATA OUT SELECTOR I

0

DATAoUT
2583 drw 01

Figure 1. Block Diagram of the IDT49C402A

CEMOS and MICROSLICE are Irademarks of Integrated Device Technology. Inc.
©1990 Integrated Device Technology, Inc.

7.2

1/90

1

TECHNICAL NOTE TN-03

USING THE IDT49C402A ALU

APPLICATIONS
The IOT49C402A can be thought of as a VLSI building
block. This building block has a register file, an ALU and an
accumulator. Since the lOT49C402A is designed out of static
random logic, this device may be used in many different
places. It can be used as a data path element in a general
purpose computer or as an address generator to generate
complex addresses for accessing data structures and linked
lists. It might also be used as a complex accumulator with an
ALU on its input to achieve sophisticated counter-type operations where constants may be in the register file in order
COROIC-type algorithms. Put simply, the IOT49C402A can
be thought of and used as a very high-performance 16-bit
version of the widely used 4-bit 7400 family (74181,251,381)
ALUs.

FUNCTIONAL DESCRIPTION
The IOT49C402A is a high-speed, fully cascadable 16-bit
CMOS ALU slice with 64-by-16-bit register file. It combines
the standard functions of four 2901 s (4-bit ALU) and a 2902
(carry lookahead) with additional control features aimed at
enhancing the performance of bit-slice microprocessor designs.
Based on the normal control functions associated with a
standard 2901 bit-slice operation, the IOT49C402A includes
twice the destination codes. Its standard functions (Figures 2
and 3) include a 3-bit instruction field which controls the
source operand select of the ALU (10, 11, 12), a 3-bit instruction
field used to control the 8 possible functions of the ALU (13, 14,
Is), and a 3-bit instruction field (16, 17, la) for selecting the
standard 8 destination control functions supported by the
2901. A tenth microinstruction input, 19, offers 8 additional

FUNCTION CONTROL

destination control functions. This 19 input, in conjunction with
16 through la, allows many new functions to take place - like
shifting of the Q register up and down independently, as well
as loading the RAM or Q registers directly from the 0 inputs
without going through the ALU. By tying the 19 instruction input
high, the la through 16 instruction lines exhibit the destination
codes found in the 2901. With the 19 line low, the new
additional functions of the IOT49C402A can be accessed.

EXTRA DATA PATHS
The IOT49C402A, while using the same basic 290Hype
architecture, incorporates a new data path aimed at increasing system parallelism. This data path goes directly from the
o inputs into the register file and Q register. Normally, the
loading of the register file and the Q register in the 2901
requires that the ALU work as a pass function in order to route
the direct data input path through the ALU and then store the
results inthe registerfileorQ register. With the new data path,
the data can be put directly into the register file in parallel with
other ALU operations. For example, in one cycle the DFF
destination instruction allows the A output port of the register
file and the Q registerto be combined together in the ALU with
the results being stored into the Q register, while new data is
brought into the registerfile and stored at the address selected
by the B address port. One of the more sophisticated
destination functions available in the IOT49C402A is DFA.
This allows the RAM to be loaded directly from the 0 inputs,
the Q registerto receive the resu Its of the ALU and the Youtput
bus to output data directly from the RAM. This extra data path
allows full, complete utilization of all three major buses inside
the IOT49C402A.

SOURCE CONTROL

Microcode

15

14

13

Octal
Code

ADD

L

L

L

0

R Plus S

SUBR

L

L

H

1

SUBS

L

H
H

L

2

H

L

L

L

H

Mnemonic

OR

L

AND

H
H
H
H

NOTRS
EXOR
EX NOR

H
H

ALU
Function

ALU Source
Operands

Microcode
Mnemonic

12

h

10

Octal
Code

R

S

S Minus R

AO

L

L

L

0

A

0

R Minus S

AB

L

L

H

1

A

B

3

RORS

ZO

L

L

2

0

0

4

RANDS

ZB

L

H
H

H

3

0

B

5

RANDS

ZA

L

L

A

L

H

4
5

0

DA

H
H
H
H

0

A

H
H

L

6

D

0

H

7

0

L

6

REX-OR S

H

7

REX-NOR S

DO
DZ

2583 tbl 01

0
2583 tbl 02

Figure 2. Function and Source Codes

7.2

•

I

TECHNICAL NOTE TN-03

USING THE IDT49C402A ALU

ALU DESTINATION CONTROL
Microcode
Data to be Stored
In Q Register

Y Output

-

F

F

Original 2901

9

-

F

Functions

A

F

-

A

Mnemonic

19

18

17

16

Hex
Code

OREG

H

L

L

L

8

NOP

H

L

L

H

RAMA

H

L

H

L

Data to be Stored
in RAM at B Address

RAMF

H

L

H

H

B

F

-

F

RAMOD

H

H

L

L

C

F/2

0/2

F

RAMD

H

H

L

H

D

F/2

-

F

RAMOU

H

H

H

L

E

2F

20

F

.H

H

H

H

F

2F

-

F

DFF

L

L

L

L

0

D

F

F

New Added

DFA

L

L

L

H

1

D

F

A

IDT49C402

FDF

L

L

H

L

2

F

D

F

Functions

FDA

L

L

H

H

3

F

D

A

RAMU

XODF

L

H

L

L

4

-

0/2

F

DXF

L

H

L

H

5

D

-

F

XOUF

L

H

H

L

6

20

F

XDF

L

H

H

H

7

-

D

F
25831b103

Figure 3. Destination Codes

REGISTER FILE
The register file in the IOT49C402A is 64 addressable
locations, each 16 bits wide. Being fourtimes larger than most
other 16-bit slices, this increased data space provides a larger
cache of data which minimizes the traffic to bring in data from
the outside world into the register file. From another perspective, the register file also can be viewed as 4 banks of 16
location register files. By using 2 of the address lines a
register file may be bank-selected, thus allowing the progra'mmerto have 4 virtual 2901soperating inside the IOT49C402A.
This enables the userto perform multi-tasking microcode. On
e~c~ clock cycle a new task may be selected, thus having the
minimal overhead for context switches.

INCREASED PERFORMANCE
The critical path through the IOT49C402A is the address
and instruction lines to the Y output and status flags (ABI to
Y/Flags). For the A version of the IOT49C402 this is 37ns,
the time requiredforthe address input lines to select operands
out of the RAM register file and be output as data. This allows
the user to construct a data path well under 50ns. This would
include the pipeline register instruction time with a clock-to-Q

7.2

of 6.5ns (utilizing the IOT74FCT374A) and a set-up time of
data and status (37ns) from the IOT49C402A into a status
register with a set-up time of 2.5ns.

32-BIT APPLICATIONS
High-speed operation for most 32-bit applications is easily
obtainable when using the IOT49C402A. In order to build a
32-bit ALU, two IOT49C402As can be cascaded by connecting the carryout of the ALU of one device into the carry-in of the
~ext device (see Figure 4). In this 32-bit design the critical path
IS through the ABI to carryout (Cn+ 16), which is 34ns, and then
through the carryin (Cn) of the most significant device as a setup to the clock, which is 32ns. Using lOT's new FCT/A logic
family, a cycle time of 75ns can be constructed.

CONCLUSION
The lOT49C402A can be used in a multitude of applications
which previously incorporated discrete 2901 s. Upgrading to
this high-performance device allows the user to operate at a
20MHz level while reducing board space and overall power. It
exemplifies its overall flexibility as a VLSI building block
wherever an ALU function with register files is used.

3

USING THE IDT49C402A ALU

TECHNICAL NOTE TN-()3

32-Bits DatalN

System
Clock

32-Bits DataouT
2583 Drw 02

Figure 4. 32-81t configuration showing
critical delay path

•
7.2

4

I

G®
Integrated Device Technology, Inc.

APPLICATION
NOTE
AN-03

TRUST YOUR DATA WITH
A HIGH-SPEED CMOS
16-, 32-, OR 64-BIT EDC
By Suneel Rajpal and John R. Mick

INTRODUCTION
As a computer-science corollary to Parkinson's First Law,
"Work expands to fill the time available," it is observably
always true that "Computer software expands to fill the
memory available." There is an insatiable demand for higher
speed and denser memory, be it dynamic RAM or static
RAM. However, there are reliability considerations that have
to be made in large memory systems that must always
provide correct data. This article deals with methods of
enhancing data integrity and system performance by using
Error
Detection and Correction (EDC) logic circuits.

In memory systems, two types of errors can occur - hard
errors or soft errors. A hard error is a permanent error and it
occurs when a memory location is stuck-at-one or stuck-atzero. A soft error is temporary, random and correctable. As
these errors are non-recurring and non-destructive they can
be corrected using EDC logic.
Hard errors are caused by factors such as interconnect
failures, internal shorts and open leads. Soft errors can be
caused by system noise, power surges, pattern sensitivity
and alpha particle radiation. The charge of an alpha particle
can become comparable to the charge on memory cells as
geometries shrink. This implies that susceptibility to alpha
particle radiation is likely to increase as memory densities
increase; however, memory manufacturers try to reduce or
eliminate the problem by design or packaging techniques.
In spite of that there is a probability of failure or error,
especially where large systems are concerned. A graph that
shows the trend of error rate versus chip density for dynamic
RAMs is presented in Figure 1. One can calculate the Mean
Time Between Failures (MTBF) for a DRAM system quite
easily based on such data from a DRAM manufacturer.
A common method to examine data integrity is to
incorporate parity. In a simple case of a three bit number and
one parity bit, the following relationship exists as shown in
Table 1.

TABLE 1.
DATA

ODD PARITY

000
001
010
011
100

1
0
0
1
0
1
1
0
2587 drw Ot

MICROSLICE and CEMOS are trademarks of Integrated Device Technology, Inc.
(i!lt990 Integrated Device Technology, Inc.

o

HARD ERRORS

w

~

0:.
0:0:Cf)

0.1

ffi§

0.01

o
o:I

-I""':
<:0:

2w
0...0...

0.001

~~ 0.0001

TYPES AND SOURCE OF ERROR

101
110
111

• SOFT ERRORS DUE TO
ALPHA PARTICLES ONLY

7.3

1K

4K 16K 64K 256K 1M
DENSITY BITS/CHIP

2587 drw Ot

Figure 1. Typical Error Rates

The odd parity is generated by an exclusive-NOR operation of the data bits. An error can be identified by taking the
entire word and the parity bit, called a code, and performing
an exclusive-OR operation. If the exclusive-OR result was a
one, it indicates that the data was probably correct and the
combination of the data and parity bits represent a valid
code; "probably" is mentioned, and will be explained in the
following lines. However, if the exclusive-OR result was a
zero, then it can only be identified that an error occurred and
the combination of the data and parity bits represent an
invalid code.
Another interesting aspect of Table 1 is the fact that to go
from one valid code, say 0001 to another valid code 0100, at
least two bits have to change. This is called a distance of
two. If only one bit changed on the code, it could be used to
identify an error, but it could not point to the correct valid
code. For example, if an invalid code of 0011 is seen, it lies
between 0001 and 0010 and it is not possible to tell if the last
data bit is in error or the parity bit is in error. Now, back to the
mention of the word "probably." If two bits in the data
changed erroneously, the parity tree performing the
exclusive-OR would not be able to catch that kind of an error.
Detection codes using parity are therefore limited and useful
only in detecting one bit in error (or any number of odd
errors), and they cannot provide any correction. Unfortunately, they cannot detect two errors (or any even number
of errors).
The detection capability of the codes with different
distances are shown in Figure 2. An invalid code that occurs
in the distance of two cannot tell which bit was erring as
outlined in the previous paragraph. Codes that keep a
distance of three (or at least 3 bits have to change to go from

TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-, 32-, OR 64-BIT EDC

VALID CODE

.

INVALID CODE

DISTANCE OF nNO -

VALID

VALID CODE

DETECTS SINGLE BIT ERRORS

~

INVALID

cr •

INVALID

VALID

DISTANCE OF THREE - DETECTS AND CORRECTS
SINGLE BIT ERRORS

.~

VALID
-

INVALID

o

INVALID

INVALID

VALID

DISTANCE OF FOUR
DETECTS AND CORRECTS SINGLE BIT ERRORS
- DETECTS DOUBLE BIT ERROS
2587 drw 02

Figure 2. Codes of Various Distances and Their Effectiveness

one valid code to another) can detect single bit errors and
also correct them. However, codes with a distance of three
cannot detect two failing bits. As shown in the distance of
three example, if a two-bit error occurs, it would be identified
as if one bit failed. An invalid code associates detection/
correction with the valid code adjacent to it rather than the
other valid code that is a distance of two from it. Codes of a
distance of four can detect all single-bit errors, detect all
double-bit errors and also correct all single-bit errors. Doublebit errors are equidistant from two valid codes as shown by
the central invalid code in Figure 2. The Single Error Correction and Double Error Detection (SECDED) capability is
highly desirable for data integrity in high-reliability computer
systems.

EDC ICs TO THE RESCUE
Codes with a distance of four are used in the IDT39C60/
IDT49C460 Error Detection and Correction ICs. The overhead in the EDC implementation is additional check bits to
the words in memory. For example, 6 bits are needed for

APPLICATION NOTE AN-03

16-bit data, 7 bits for 32-bit data, and 8 bits for 64-bit data to
generate a distance of four. The code formed is a catenation
of the word bits and the check bits and, as in the parity case,
the code can be valid or invalid. The valid codes are a
distance of four apart from the next valid code. Valid codes
are implemented by generating check bits based on the data
word and writing the check bits with the data bits to the
memory. On reading the data and check bits from memory,
a possibly valid or invalid code could have been read. The
determination of whether the code was valid or not is done
byregenerating check bits using the data bits; these are
compared (ex-ORed) to the check bits that were read and
the result is syndrome bits. These syndrome bits are indicative of an error-free Situation, or a single or double-bit error,
and are used to determine validity of a code, and also to
point to single-bit errors and identify the occurrence of two or
more bits in error.
As an example, let us write (FFFF)H as the data word.
The corresponding check bits that· will be written in the
memory are 001100 and can be computed using Table 2
which is based on a modified Hamming code. On reading
back, if the data was FFFE and the data in position 15 had
erroneously flipped from a "1" to a "0," the regenerated check
bits would be 000111 (based on FFFE). The syndrome bits
are the ex-OR of the two sets of check bits and are 001011.
Referring to Table 3, a syndrome of 001011 indicates bit 15
is in error and has to be flipped.
The internal hardware of the IDT39C60 16-bit EDC, shown
in Figure 3A, consists of ex-OR trees that can generate
check bits and syndromes and also contains hardware to
correct data. In addition, two or four IDT39C60s and some
SSI, MSI can be connected to form 32-bit or 64-bit EDC
systems. The IDT39C60 is a functional and pin-compatible
replacement of the 16-bit 2960, and runs at a quarter of the
power. Faster versions, such as IDT39C60-1 and the
IDT39C60A (the IDT39C60-1 replaces the Am2960-1 and
the IDT39C60A is the fastest 16-bit EDC available), demonstrates that CMOS circuits can not only run cooler than their
equivalent bipolar circuits, but also run faster with higher
output drive.
The architecture of a 32-bit EDC, the IDT49C460, is shown
in Figure 38. The IDT49C460 provides efficient means of
generating check bits, calculating syndrome bits and

TABLE 2: 16-BIT MODIFIED HAMMING CODE CHECK BIT GENERATION(1)
GENERATED
CHECK BITS

CX

PARTICIPATING DATA BITS
PARITY

0

Even (XOR)

CO

Even (XOR)

X

C1

Odd (X NOR)

X

C2

Odd (X NOR)

X

C4

Even (XOR)

C8

Even (XOR)

1

2

3

X

X

X

X

X

4

7

X

X

X
X

6

X
X

X
X

5

X

8

9

X

X

X
X

X

X

X

X

X

X

NOTE:

11

X

12

13

X
X

X

X

10

X
X

X

X

15

14

X
X

X

X

X

X

X

X
X

X

X

X
2587 tbl 02

Tho chock bit is generated as either an XOR or XNOR of the eight data bits noted by an ·X" in the table.

7.3

2

I

TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-, 32-, OR 64-BIT EDC

correcting data bits on a 32-bit data path. In addition,
diagnostic capability is provided to verify data operations in
the memory system and verify that the EDC IC is functional
too.
Figures 4A and 4B show the dataflow for the generate and
error detect/correct operations in the IDT49C460. In Figure
4A, check bits based on input data are generated by the
EDC and are written to the check-bit memory along with the
data. In Figure 4B, the data and check bits are read from the
memory. Based on their values the syndrome bits are
generated inside the IDT49C460. If the EDC is in the correct
mode, any single-bit error is corrected and the corrected
data is placed in the output data latch. The syndrome bits
are also available if error logging is done.
Another necessary operation that is required is byte handling. When the memory is organized as a 32-bit word and
an a-bit update is being performed, it requires a 2-step
operation. The first step is to read the 32-bit data and check
bits, and correct any erroneous single bit failure. The second
step is to write the new byte with the unmodified bytes back
to the system memory. The check bits corresponding to the
newly formed 32-bit word are generated and also written to
the memory. This operation is supported by having four
separate output byte enables in the IDT49C460. The twostep process is shown in Figures 5A and 5B.

TABLE 3:
SYNDROME DECODE TO ERROR LOCATION/
TYPE
SYNDROME

S8

0

1

0

1

0

1

0

BITS

S4

0

0

1

1

0

0

1

1

S2

0

0

0

0

1

1

1

1

C8 C4 T C2

SX

1

SO S1

0

0

0

*

M

0

1

C1

T

T 15

T
T 13

T

0

7

T

0

1

0

CO

T

T

M

T

12

6

T

0

1

1

T 10

4

T

0

T

T

M

1

0

0

CX T

T

14

T

11

5

T

1

0

1

3

T

M

M

1

1

T
T

1

1

M

T

0

T
T

8

2

T

1

T
T

1

M

T

T

M

T

M

9

NOTES:
• = No errors detected
Number = Number of the single bit-in-error
T = Two errors detected
M = Three or more errors detected

APPLICATION NOTE AN-03

M

2587 drw 03

LEoUT
~ BYTE 0 L_~>------....,

CB

0-6

DATA 0-7
DATA 8-15
OE BYTE

ERROR DECODE
& CORRECT

~r-r--~~~

1

LEIN

LEOIAG
CODE 10
DIAG MODE
PASS THRU

3
2
CONTROL
LOGIC

GENERATE
CORRECT
Figure 3A. The IDT39C60/-1/A 16-Bit EDC Architecture

7.3

3

TRUST YOUR DATA WITH A HIGH·SPEED CMOS 16·, 32·, OR 64·BIT EDC

LEouT/GENERA TE
OE BYTE

L~>----------,

4

0-3

CB 0-7

APPLICATION NOTE AN·03

8
32

DATA

0-31

ERROR DECODE
& CORRECT

OEsc

LEIN
MULTERROR

LEOIAG
2

CODE ID
DIAG MODE

2587 drw 04

2

CONTROL
LOGIC

LEoUT/G~NERA TE

CORRECT

l_~>----~~

Figure 3B. The IDT49C60/A 32·Bit EDC Architecture

LEouT/GENERA TE
OEBYTE 0-3
CB 0-7

~>----------,

4

8
32

DATA 0-31

ERROR DECODE
& CORRECT

OEsc

LEIN
MULT ERROR

LEOIAG
CODE ID
DIAG MODE

CONTROL
LOGIC

Figure 4A. Check Bit Generation in the IDT49C460

7.3

II

TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-, 32-, OR 64-BIT EDC

APPLICATION NOTE AN-03

LEoUT/GENERATE
OE BYTE

0-3

CB

0-7

DATA

4
8
32

0-31

OEBYTE

1

SC

0-7

OEsc

LEIN

L -_ _ _ _ _--".

ERROR

.----._~

MULTERROR

LEOIAG

CODE ID
DIAG MODE

2587 drw 06

2
2

CONTROL
LOGIC

LEouT/GENERA TE
CORRECT

Figure 4B. Error Detection and Correction in the IDT49C460

MEMORY LOCATION

HOST COMMAND TO
WRITE BYTE "E"
AT MEMORY LOCATION

A

B
IDT49C460

B

E

IDT49C460

C

D

D
'-----------1

A

L -_ _ _ _ _ _~

CHECK

CHECK
25B7 drw OB

Figure 5B. Byte-Write Operation; Step 2. Newly Generated
Check Bits Corresponding to Bytes A, B, E, and D
Are Written to Memory Along With Bytes A, B, E, and D

2587 drw07

Figure SA. Byte-Write Operation; Step 1. Read 32-Bit Word
and Correct Any Single-Bit Error

The IDT49C460 is expandable to 64-bit wordlengths as
shown in Figure 6A. The external buffer may notbe required
if the path from the memory already has a three-state buffer
in its output stage or externally in the data path to the EDC.
Figure 68 shows a 2-step operation when an error detection
and correction occurs in bit 32-63 of the 64-bit word. The IC
on the first level, with code ID=10, receives the data bits 0-31
and the entire check bits. In the example shown, bit 63 has
erroneously flipped from a "1" to a "0". The partial syndrome
bits are passed from the first device to the second. (The
actual syndrome bits are generated from a table not shown
in this article but are in the IDT49C460 data sheet.) The
check input latch of the second device is open, due to its
7.3

code 10=11, and the partial syndrome bits are combined with
the data bits to generate the final syndrome bits. The final
syndrome bits indicate that bit 63 is in error and it is inverted
to produce a correct result. The final syndrome bits are also
sent back to the first device, but the resulting syndrome does
not alter any data bits in the first device. Therefore, the error
correction is a 2-step process. In Figure 6C, an error occurs
in bits 0-31. In this case, the partial syndrome is sent to the
second device. The second device generates the final syndrome and sends it back to the first device. Finally the
erroneous bit is flipped over. In this case, a 3-step operation
takes place.

5

TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-, 32-, OR 64-BIT EDC

APPLICATION NOTE AN-03

INPUT CHECK BITS
OEsc

CB

0-7

OEsc

IDT49C460A

DATA

SC

0-7

CB

0-7

CODE
10 = 10

OEsc
OEscr---------------r---L----

IDT49C460A
CODE 10 = 11

OUTPUT SYNDROME/CHECK BITS

2587 drw 09

Figure 6A. The IDT49C460 in a 64-Bil Configuration

DATA

CHECK

FFFFFFFFFFFFFFFF

30

WRITE

FFFFFFFFFFFFFFFE

30

READ

CODE = 10 FFFFFFFF (BITS 0-31)

30 (INPUT CHECK BITS)

"-

DO (PARTIAL SYNDROME) ,/'"
CODE = 11 FFFFFFFE (BITS 32-63)

STEP 1

00 (PARTIAL SYNDROME) " -

FFFFFFFFF (CORRECTED 32-63) AE (FINAL SYNDROME)

/'

STEP 2

CODE = 10 FFFFFFFF (UNCHANGED 0-31)

I

2587 drw 10

Figure 6B. Error Correction on a 64-Bit Word, When Error is in Bits 32-63

DATA

CHECK/SYNDROME

FFFFFFFFFFFFFFFF

30 (CHECK)

WRITE

FFFFFFFEFFFFFFFF

30 (CHECK)

READ

CODE = 10 FFFFFFFE (BITS 0-31)

30 (INPUT CHECK BITS)

"-

2F (PARTIAL SYNDROME),/'" STEP 1
CODE

=

11 FFFFFFFF (BITS 32-63)

2F (PARTIAL SYNDROME) " 2F (FINAL SYNDROME)

FFFFFFFF (BITS 32-63)

CODE = 10 FFFFFFFF (CORRECTED 0-31) 2F (FINAL SYNDROME)

,/'" STEP 2
STEP 2
2587 drw 11

Figure 6C. Error Correction on a 64-Bit Word, with Error in Bits 0-31

7.3

6

APPLICATION NOTE AN-03

TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-, 32-, OR 64-BIT EDC

HOW THE IDT49C460 FITS IN A SYSTEM
By virtue of their function, EDC ICs tie in closely with
system memory architectures. Figure 7 shows a host that
generates addresses and accesses a memory system. The
memory contains memory elements, error detection logic
and interface circuits. These are needed to start a memory
cycle, to send/receive data on the system bus, and to inform
the host that it has completed the memory operation.
One may use EDC for dynamic RAM memories or static
RAM memories. Figures 8A and 8B show general
configurations for DRAM arrays. Normally, in DRAM systems,
separate pins exist for the DATAOUT and DATAIN. Therefore,
IDTFCT244s can be used to provide an isolation between
the DATA port of the EDC and the DATAoUT from the RAM.
This isolation may be required after a read operation, and the
EDC provides corrected data to the system and the DRAM.
Another buffer is needed between the DATA port of the EDC
and the system data bus to allow the corrected data to be
placed on the system bus. The DRAM controller can be
implemented using standard off-the-shelf products. An

important operation that has to be supported is byte or word
handling. The IDT49C460 EDC configuration shown in Figure
8A has four individual byte enable controls going to the
I DTFCT244s and their complements to the IDT49C460. The
IDT39C60 shown in Figure 8B has two individual byte controls
to the IDTFCT244s and their complements going to the
IDT39C60.

ADRS
v

MEMORY
HOST
DATA

A

"

CONTROLS

"v

INTERFACEl

EDC
2587 drw 12

Figure 7. Typical High-Reliability Memory System

DATA ARRAY
/

DATA BITS

/

IDT
FCT244s

r-

IDT49C460

DATAoUT

32

!
DATA
OE

DATAIN

32

0-3

4

CB

OUT

MERR

ERR

~

I

CHECK BITS

IN

SC

8
BYTE
HANDLING
CONTROLS
/
/

r---

RAS
CAS, WE

lOT
FCT245s ~

tV

ADRS CONTROLS
DRAM
CONTROLLER

TIMING
CONTROLLER
(PAL-BASED)
DATA BUS

HIGH ADRS

LOWADR S

t t
ADDRESS BUS

CONTROL BUS

2587 drw 13

Figure SA EDC Logic in 32-Bit DRAM-Based Memory Systems

7.3

7

TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-,32-, OR 64-BIT EDC

APPLICATION NOTE AN-03

DATA ARRAY
DATA BITS
./

,-

IDT39C60

lOT
FCT244s

DATAoUT

16

!
DATA

DATAIN

16

/

OEo-1

/2

CB

OUT

SC

IN

MERR

ERR

~

I

/ 4
BYTE
HANDLING
CONTROLS
./

.----

CHECK BITS

RAS
CAS, WE

lOT
FCT245s ~

tV

ADRS CONTROLS
DRAM
CONTROLLER

TIMING
CONTROLLER
(PAL-BASED)
DATA BUS

HIGH ADRS

LOWADR S

t t
CONTROL BUS

ADDRESS BUS
2587 drw 14

Figure 8B. EDC Logic in 16-Bit DRAM-Based Memory Systems

In static RAM systems, as shown in Figure 9, there is no
need for dynamic memory array controller; however,
bidirectional buffers are required on the ports of the static
RAMs as RAMs have common 1/0 lines for data. If the
SRAMs had separate 110 pins for the data, the buffer configuration of the DRAM array could be used.
The timing controller, common to both DRAM and SRAM
systems, controls the buffer and the EDC ICs. This is an
interesting task to the memory system designer, as a choice
of EDC architectures are available.

BUS-WATCH AND FLOW-THROUGH EDC
ARCHITECTURES
The architecture of the EDC ICs can be categorized as
Bus-Watch and Flow-Through as shown in Figure 10. In a
bus-watch architecture, there is only one bus to handle the
data and one set of pins that handle incoming data from the
memory, corrected data from the EDC, and incoming data

7.3

from the system to be written to the memory. The IDT39C60
and IDT49C460 are based on a bus-watch architecture. In a
flow-through architecture, such as Intel's 8206, there are two
ports that handle data movement. The WDIN/DoUT handle
incoming data from the system, so that the EDC can generate check bits. The second function of the WDIN/DoUT is to
supply the corrected data to the system and the memory.
The second set of pins, DIN, only handles incoming data from
the RAM. These architectures lend themselves to "Check
Only" and "Correct Always" configurations.
The "Check Only" method is used in high-performance
systems. The memory system always sends data directly to
the host when a read is requested. In the event a single bit
error occurs, one approach is that the read cycle is delayed
and a correction is performed. The corrected data is sent to
the host and written into the memory. In this case, the timing
control circuit would disable the Memory Data Out Buffer (the
IDTFCT244 for the DRAM case and the IDTFCT245 for the

8

I

APPLICATION NOTE AN-03

TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-, 32-, OR 64-BIT EDC

STATIC RAM ARRAY
DATA BITS

FC!g~5S ~

-

IDT39C60
OR
IDT49C460

DATAournN

DATA
CB
SC
MERR

ERR

~

I

lOT
CHECK BITS
FCT245s . . - . . OUTIIN

J
lOT
1 __
FCT245s ~

ttt

...--_-'--_....L.....I.............,
TIMING
CONTROLLER
(PAL-BASED)

DATA BUS

HIGH ADRS
LOWADRS

tt

ADDRESS BUS

CONTROL BUS

2587 drw 15

Figure 9. EDC Logic in 16-, 32-, 64bBit Static RAM-Based Systems

MEMORY

CBOUT CBIN
BUS-WATCH EDC

MEMORY

SYSTEM DATA BUS
"---l~

2587 drw 16

Figure 10. Architecture of Bus Watch and Flow-Through EDC Logic

7.3

9

TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-, 32-, OR 64-BIT EDC
static RAM case) and put corrected data from the EDC IC
onto the system data bus, also writing the corrected data
back into the memory array. For the "Check Only" method,
the DATA TO ERR parameter is of key concern to designers
as this can be used to generate the DTACK, READY or
BERR signals to the host.
The other option is that a "Correct Always" method is
used. In this case, the EDC always corrects data (regardless
of the fact that it may be error-free), sends it on the system
data bus and writes it back to the memory. In this case, the
cycle time for the data read includes the "DATAIN TO
CORRECTED DATAoUT" parameter for the EDC. The
IDT49C460 and the IDT39C60 provide the fastest timings for
the "DATAIN TO ERR" and "DATAIN TO CORRECTED
DATAoUT" parameters when compared to other currently
available 32-bit and 16-bit EDCs. This was made possible
by using lOT's CEMOSTM II 1.211 process.
The IDT49C460A dissipates only 95mA and the
IDT39C60A dissipates only 85mA over the commercial temperature range. The quiescent power consumption is only
5mA for the IDT49C460A and the IDT39C60A.
The delay for the DATAIN TO ERR is only 30ns for the
stand-alone 32-bit lOT49C460A (worst case commercial)
and is 46ns for the 64-bit for the cascaded case. The delay
for the DATAIN TO CORRECTED DATAoUT is only 36ns for
the stand-alone case and 63ns for the 64-bit cascaded case.
These parameters are very important when considering EDC
ICs discussed further in a later section. They are, however,
shown in Tables 4 and 5 for the 16-bit IDT39C60 and 32-bit
IDT49C460, respectively.

TABLE 4:

KEY PARAMETERS FOR THE
IDT39C60/-1/A FOR COMMERCIAL RANGE
CONDITIONS
OATAIN to ERR
OATAIN to

IDT39C60 IDT39C60-1

32ns
65ns

IDT39C60A

25ns

20ns

52ns

30ns

Corrected OATAOUT
2587 tbl 04

TABLE 5:

KEY PARAMETERS FOR THE
IDT49C460/A FOR COMMERCIAL RANGE

CONDITIONS
OATAIN to ERR
OATAIN to

IDT49C460

40ns
49ns

21DT49C460As
FOR
64-BIT EDC
IDT49C460A

30ns
36ns

46ns
63ns

Corrected OATAoUT

APPLICATION NOTE AN-03

The acid test is how a flow-through architecture compares
in performance to a bus-wa~ch architecture in the "Check
Only" mode and the "Correct Always" mode. In Figure 11, a
flow-through EDC device is connected to a DRAM array
system for the IDTFCT244 buffer to the system bus directly
and simultaneously to the EDC device. Within the DATAIN
TO ERR of the device, it is determined if a single-bit error
occurred and, if so, a timing controller would disable the
IDTFCT244 and allow corrected data to be sent on the
system bus via the IDTFCT245.
A bus-watch EDC in a "Check Only" configuration is shown
in Figure 12. The data path from the DRAM to the EDC goes
through one IDTFCT244 delay and is identical to the flowthrough case. After that the DATAIN TO ERR delay determines whether or not the cycle would be stretched. The data
from the DRAM goes through an IDTFCT244 buffer and an
IDTFCT245 .buffer in the bus-watch case. One emerging
fact is that the time it takes to make a decision to stretch a
memory cycle is the same for the bus-watch and flow-through
EDC parts and is determined by the DATAIN TO ERR of the
respective devices.
In the flow-through "Correct Always" configuration, as
shown in Figure 13, data has to always pass through the
EDC and any IDTFCT245 and on to the system bus. In the
case of bus-watch ICs, data from the DRAM goes through an
IDTFCT244, in and out the EDC device and through an
IDTFCT245 as shown in Figure 12. A bus switch has to take
place every cycle as memory data comes into the EDC, is
corrected and then transferred to the system bus. In a
practical design this bus switch may be the longest delay
path for "Correct Always". However, if just the specification
is being reviewed, the flow-through path is shorter by an
IDTFCT244 delay. A specification comparison is that the
"DATAIN TO CORRECTED DATAoUT" delay of a flow-through
EDC part should be compared to the "DATAIN TO
CORRECTED DATAouT"delayofthe IDT49C460/A, plus an
external 7ns buffer delay (for the IDTFCT244). However, in
an actual system, such as the one in Figure 8A, a
"bus-switch" has to take place, as explained below.
In a DRAM system that has a bus-watch EDC, a
sequence of events has to be created by the timing controller
that was shown in Figure 8A. The timings that the controller
generates are shown in Figure 14. The example being
considered is "Correct Always." The RAS, CAS, WE signals
have to be generated to read data from the DRAM. The read
takes place before state 7, and the read data is latched in the
DATAIN latch of the EDC. It is then corrected and the
corrected data can be latched in the DATAoUT latch. The
data correction can take place between states 7 and 10. Any
time after state 10, the EDC can place the corrected data on
the bus. The bus that was loading the data in the EDC has to
be turned around as the EDC is going to send corrected data

2587 tbl 05

7.3

10

II

APPUCATION NOTE AN-03

TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-,32-, OR 64-BIT EDC

MEMORY
SYSTEM DATA BUS

lOT
FCT244

r+---

DATAIN

~

.

DIN
DIN

CBour
CBIN ...

lOT
FCT245

Dour

Dour

ERR
DATAour/WDIN

2587 drw 17

-ERR
Figure 11. The "Check Only" Configuration for Flow-Through EDC ICs

........

lOT
FCT244

lOT
FCT245

4---

Dour
DATA
DIN

IDT49C460
OR IDT39C60

Dour
CHECK
DIN

CBIN
-+--- ERR

CBour

2587 drw 18

Figure 12. The Bus-Watch EDC in
"Check Only" or "Correct Always" Configurations

~

SYSTEM
OATA
BUS

lOT FCT245

WDIN/
Dour

L
DIN
CBo
CB1

DIN
DATA
DOUT
DIN
CHECK
Dour
2587 drw 19

Figure 13. A Flow-Through EDC in "Correct Always" Mode

7.3

11

TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-,32-, OR 64-BIT EDC

STATE
RAS

APPLICATION NOTE AN-03

o 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0

~~------------~~

ROW/COL
CAS

~~------------~

OEMEM BUF

DATA
LEIN

_____X

(1)

XDATAIN FROM EDC

OATAIN TO EDC

~'-------'/

LEoUT/GEN
aEON EDC
READIWRITE

~
2587 drw 20

NOTE:

1. A BUS-SWITCH TAKES PLACE BETWEEN STATES 6 AND 10.
Figure 14. Timing Diagram for Correct Always in Figure 7A

to the host. The EDC also writes back the corrected data
and the newly generated check bits to the memory. The
memory buffers shown in Figure 8A are three-stated, as the
OE MEM BUFF are high from state 7 onwards and the EDC
would be enabling data on the bus. The timing diagram in
Figure 14 explains a typical case and users will have to
customize it based on their memory speeds and the time the
system has for receiving valid data.
Other factors that may be a consideration are package
count and board space. The number of packages used in
flow-through and bus-watch implementations are the same
for "Check Only" configurations. In "Correct Always"
configurations the bus-watch implementation requires four
more IDTFCT244s than the flow-through implementation.
Flow-through ICs have more pins and therefore leave a

7.3

larger footprint on the PC. However, in terms of board
space, since the footprint of the flow-through EDC is larger
than the bus-watch, the bus-watch approach takes less space
for "Check Only" configurations and there is a tie for the
"Correct Always" configuration.

SUMMARY
This article has covered reliability issues in memory
systems and solutions using EDC devices. In considering
EDC devices, two parameters are critical: the "DATAIN TO
ERR" and the "DATAIN TO CORRECTED DATAoUT". At
Integrated Device Technology, we have optimized these two
parameters and produce ultra fast, TTL-compatible CMOS
Error Detection and Correction devices for high performance
16-, 32- and 64-bit systems.

12

I

G®
Integrated Device Technology, Inc.

16-BIT CMOS SLICES-NEW
BUILDING BLOCKS MAINTAIN
MICROCODE COMPATIBILTY YET
INCREASE PERFORMANCE

APPLICATION
NOTE
AN-06

by Michael J. Miller

INTRODUCTION

RE-EMERGENCE OF MICROPROGRAMMING

The electronics industry has been an evolutionary
succession of dominating technologies. This has been true
for semiconductor devices in general, as well as the product
family called bit-slice microprocessors. With the extinction of
each technology and the emergence of the new, there is an
associated transition for both the manufacturer and the
consumer. Each company seeks to minimize the effort of
this transition.
In the 1950s it was a generation of germanium diodes and
transistors. During the 1960s, silicon transistors and bipolar
ICs dominated. The last decade saw the emergence of the
NMOS microprocessor and dynamic memories. This decade
will be dominated by very high-speed CMOS as the primary
volume process. This evolution is not only taking place with
the industry but, in specific, with the microprogrammed bitslice microprocessors. Today very high-speed, low-power
CMOS is taking the place of very high-speed bipolar. CMOS
is capable of operating faster and at 1/5 to 1110 the power of
bipolar technologies. Because of this, CMOS is becoming
the technology of choice for bit-slice microprocessors.
In the past, technological changeovers have been
expensive to the manufacturer as well as the consumer. The
MICROSLlCE'" family from lOT seeks to facilitate this
transition by offering two families of CMOS bit-slice devices:
IDT39COOO, IOT49COOO. ThelDT39COOO family provides
high-speed CMOS devices that fit into the sockets of current
designs which utilize the 2900 family of bit-slice devices.
The IDT39COOO family is pin-for-pin compatible to the 2900
family as well as compatible with its highest speed grade. An
easy upgrade path is provided by the IDT49COOO family of
bit-slice devices. This family starts off by providing higher
densities, improved architecture, and progresses on into
innovative architectures of the future.

As a result of CMOS, bit-slice microprogram designs are
experiencing a new renaissance. In the mid-70s, the
emergence of the 2900 family, as heralded by the 2901, was
designed entirely using TTL bipolar technology. The 2901
has progressed from a propagation time - AlB to Gip equal
to 80ns - to the 2901 C which sports 37ns. To achieve
these final speeds though, the total TTL design had to be
abandoned and ECl was substituted for the inner workings
of the 2901, with TTL buffers interfacing to the outside world.
Today at IDT, very high-speed CMOS is being used to
produce an IDT39C01 E with AlB to Gip of 21 ns, at 1/8 the
power of the bipolar 2901 C.
In parallel with the evolution of the 2901 has been the
blossoming of the 2900 family to a multi-device product
family. All of the latest designs use ECl internally. The trend
in this family has been to add more and more gates on chip.
To achieve this, though, more current has been consumed
by each of the ICs starting with the 2901 at 1.2SW to the
29300 family at approximately 8W. To handle the 8W, new
packaging technology was developed which incorporates
heat spreaders and cooling towers mounted on top.
Within the limits of maximum speed and density, tradeoffs
can be made. For a given package, more speed can be
achieved with less gates; or conversely, more gates can be
incorporated at the expense of overall speed in critical paths.
This relationship is referred to as the speed/power product of
a given technology. The bipolar 2900 family has been
extended to the limit of feasible packaging and cooling
technology because of the density and speed requirements
of today's applications. Very high-speed CMOS, in contrast,
has a speed/power product an order-of-magnitude smaller
than bipolar for the same speed. Therefore, CMOS requires
less expensive packages and cooling systems.

COMPARISON OF FAMILY PERFORMANCE(1)
MICROS LICE

BIPOLAR

SPEED (ns)

DYNAMIC POWER (rnA)

SPEED (ns)

DYNAMIC POWER (rnA)

SPEED PATH

IDT39C01C

37, 25

30

37,25

265

AlB - G/P, Cn - F = 0

IDT39C01D

28,17

35

-

-

AlB - G/P, Cn - F = 0

IDT39C01 E

21,14

40

-

-

AlB - G/P, Cn - F = 0

IDT39C10B

30

80

30

340

CC-Y

IDT39C10C

16

80

-

340

CC-Y

NOTE:

2588 tbl 01

1. Reflects performance over commercial temperature and voltage range.

MICROSLICE and CEMOS are trademarks of Integrated Device Technology. Inc.
:1::1990 Integrated Device Technology, Inc.

7.4

16-BIT CMOS SLICES - NEW BUILDING BLOCKS MAINTAIN
MICROCODE COMPATIBILITY YET INCREASE PERFORMANCE

APPLICATION NOTE AN-06

A decade ago, CMOS was noted for lower power and
low-performance. Today, CMOS is capable of running at
speeds faster than bipolar at 1/5 to 1/10 the power.
Dramatically smaller power consumption and smaller gate
sizes allow for even higher levels of integrations to be
achieved. In previous bipolar designs, an ALU, a barrel
shifter, and a multiplier each required a package of their own
for heat dissipation, whereas CMOS can incorporate them all
on one piece of silicon while still having room to include a
reasonable amount of RAM. This means that CMOS has
room to grow, thus providing for new innovative architectures
in the future.
While the lower power consumption allows for more gates
in the same package, there is also freedom to shrink the size
of the packages because the package is being used less as
a means of dissipating the heat. This is timely because
consumers are requesting more and more in smaller volume
of space.

THE IDT49COOO FAMILY,
THE NEXT GENERATION
The IDT49COOO family takes advantage of all the benefits
that CEMOS has to offer: high-speed, low-power, very large
scale integration and smaller packages. Because of the new
freedoms imparted by CEMOS, the IDT49COOO family is the
next family of innovation for bit-slice microprogrammed
designs.
While the IDT39COOO family minimizes upgrade costs by
being pin-compatible, the IDT49COOO family addresses the
aspect by providing parts in the family which are codecompatible, thus achieving conservation of previously written
code. This is significant because, in the last decade, the cost
of the software portion of the system has surpassed the
hardware. The IDT49COOO family, however, is not limited to
code-compatible devices and will, in the future, include devices
with new and wider architectures.

THE IDT49C402A 16-81T ALU PLUS

THE LATEST IN CMOS TECHNOLOGY
CEMOS'" is used to produce the MICROSLICE family
with its two sub-families - named, respectively, the
IDT39COOO family and the IDT49COOO family. These families
address microprogrammable deSigns of the present and
future. CEMOS is a trademark for the proprietary CMOS
process. technology of IDT. CEMOS is an enhanced CMOS
technology which includes such features as high ESD
protection, latch-up protection and high alpha particle
immunity.

MICROSLICE IN EXISTING DESIGNS
The IDT39COOO family allows the designer to take
advantage of very high-speed CMOS in existing designs.
This family is a pin-for-pin compatible family with the 2900
counterparts. By replacing the current 2900 parts with
IDT39COOO parts in existing sockets, the power consumption of that portion of the circuitry may be reduced down to
115 to 1/10 of the bipolar power consumption at full operating
speeds. The IDT39COOO family is specified around the
highest speed grade versions of the current bipolar devices.
Currently in the IDT39COOO family is one of the cOmmon
ALU architectures, the IDT39C01. Included in the family is
the sequencer IDT39C1 O. The family also includes the 16 x
16 multipliers, IDT7216/17, and the 16 x 16 multiplieraccumulator, IDT7210. Not to be ignored, the IDT39C60
family is available for high-performance error correcting
memory designs. This family also includes the first speed
upgrade beyond the bipolar technology. The IDT39C01 D is
25% faster than the 2901 C, while the IDT39C01 E exhibits
speeds 40% faster than the 2901 C.

7.4

The first ALU in the IDT49COOO family is the IDT49C402A
which is a 16-bit ALU and register file. This device is a
superset of the 2901 architecture. It is a very high-speed,
fully-cascadable 16-bit CMOS microprocessor slice, which
combines the standard functions of four 2901 s and one 2902
with additional control features aimed at enhancing the
performance of bit-slice microprocessor designs. The
I DT49C402A includes all of the normal functions associated
with the standard 2901 bit-slice operation: (A) a 3-bit
instruction field (10, 11, 12) which controls the source operands
selection of the ALU; (B) a 3-bit microinstruction field
(13, 14, 15) used to control the eight possible functions of the
ALU; (C) eight destination control functions which are selected
by the microcode inputs (16, 17, 18); and (D) a tenth instruction
input (19) offering eight additional designation and control
functions. This 19 input, in conjunction with 16, 17 and 18,
allows for shifting the
Register up and down, loading the
Register directly from the D inputs without going
RAM or
through the ALU, and new combinations of destination
functions with the RAM A-port output available at the Y
output pins of the de.vice .. This eliminates bottlenecks of
inputting data into the on-Chip RAM.
The block diagram, Figure 1, shows the familiar.
architectures of the 2901 with register files which have both
A and B data feeding into an ALU data source selector. This
combines together the data from the register file along with
direct data input (D) and the Q Register. The output of the
ALU data source selector produces two operands, Rand S.
Rand S are fed into an eight-function ALU, the output of
which can go to the data output pins or be fed back into the
register file and/or Register.

a

a

a

2

II

16-BIT CMOS SLICES - NEW BUILDING BLOCKS MAINTAIN
MICROCODE COMPATIBILITY YET INCREASE PERFORMANCE

APPLICATION NOTE AN-06

RAMo
CLOCK

0

ALU
SOURCE

READ ADDRESS

ALU
FUNCTION

6
7
8
9

DESTINATION
CONTROL

DIRECT DATA

IN

DATAoUT

Figure 1. IDT49C402A 16-bit Microprocessor Slice

WHERE THE IDT49C402A EXCELS
The IDT49C402A, however, differs from the regular 2901
architecture by the addition of a new data bus that goes from
the direct data input pins (D) into the register file and Q
Register, thus providing a data path directly into the register
file and Q Register rather than passing through the ALU
block. With conventional 2901 architecture, in order to get
data into the register file the ALU must be placed in the pass
mode taking data directly from the 0 inputs through the ALU
and around to the register file. With this new architecture,
data can be operated on out of the register file and the Q
Register and the result placed back in the Q Register while
new direct data is being brought into the register file.
Conversely, the Q Register can be loaded while operations
are being performed on the register file and placed back into
the register file.
.
Whereas the 2901 has a 16-deep register file, the
IDT49C402A has 64 addressable registers. The 2901
architecture does not allow for direct cascading of the register
file. Dead cycles can be eliminated because four times
more data can be cached on-chip with the ALU. Other
applications may use the 64 registers as four banks of 16
registers. The bank selection could be thought of as task
switching for interrupt-driven multi-tasked applications.
The third difference from the 2901 is the ALU expansion
mechanism. The IDT49C402A incorporates an MSS input

7.4

which programs the device, being the most significant device
or not. When not the most significant slice, the P and G
signals are brought out. When the most significant slice, the
sign and overflow are brought out on the P and G.

IDT49C402A 16-BIT ALU DESTINATION
FUNCTIONS
2901
Functions
(3-Bits 16 - Ie)
19 HIGH

RAM

Q

V-OUT

F-Up
F-Up
F - Down
F - Down

a-up

F
F
F
F
F
F
F

-

Load
Load
Load
Load

0
0
F
F

Load 0

-

a - Down

Load F

Load F
Load F
Added
lOT
Functions
(1 Additional
Bit 19)
19 LOW

-

Load F
Load F
Load 0
Load 0
a-up
a - Down

Load 0

A
F
A
F
A
F
F
F
F
2588 tbl 02

3

1S-BIT CMOS SLICES - NEW BUILDING BLOCKS MAINTAIN
MICROCODE COMPATIBILITY YET INCREASE PERFORMANCE

APPLICATION NOTE AN-OS

CODE CONSERVATION

THE IDT49C402A IS COOL

The microinstruction word of the IDT49C402A looks the
same as the 2901 with the exception of the additional
destination control line called 19. Conservation of microcode
can be achieved via two methods. The first and the most
simple method is to tie the instruction line, 19. high on the
socket and not connect it to the microcode. In this way, the
remaining destination control lines, Is, 17 and 16. are compatible
to the 2901.
Forthose systems that intend to add more code, or rewrite
code for performance optimization, the second method is
performed by making minor alterations on the microcode.
For many designers this can be a fairly easily-achieved task
by making minor alterations in the meta assembler used to
compile the microcode source. The alteration in the meta
assembler would add 19 such that all previously written code
would have this signal default to a Don't Care state of high,
thus enabling the standard destination instructions (the
traditional 2901 codes). Additional code could then be written
which utilizes this instruction line and the extra features
provided in the IDT49C402.
An alternative to the second method for achieving
microcode compatibility would take the already-compiled
microcode and run it through a simple program, written in
another language, which would spread the microcode apart
and introduce in this additional instruction bit. This method is
used for microcode which no longer has existing source.

Even though the IDT49C402A has five times the circuitry
on-chip as does the 2901, it is 112 the power of just one 2901.
The 16-bit solution of the IDT49C402A is 1/8 the power of
four 2901 Cs and one 2902A. While total power consumption
is the concern of many designers because it has impact on
power supplies and cooling systems, the lower power
consumption also provides other benefits. Because less
power is being consumed, less of the package is needed as
a heat sink. This allows for packages with much smaller
outlines. Besides being offered in a standard 58-pin PGA,
the IDT49C402A comes in a standard 58-pin LCC with pad
spacing of 50 mil centers. When the board space taken up
by just the packages are added up, the LCC version of the
IDT49C402A is 0.32 square inches, as opposed to 1.8 square
inches for four 2901Cs and a 2902A. Respectively, the
IDT49C402A in the PGA package is 1.0 square inches as
opposed to 5 square inches for four 2901 Cs and a 2902A.
Not included in the calculations for the multi-chip solutions is
the spacing between the ICs.

ONE IDT49C402A WINS
RACE AGAINST FOUR 2901 S
While the IDT49C402A seeks to improve performance
through architectural enhancements, it also achieves
improved performance through raw technology. The
IDT49C402A achieves an A and B address to Y output of
41 ns for military and 37ns for commercial temperature ranges,
as compared to four 2901 Cs and a 2902A which have A and
B to Y and flag of 80ns for military and 68ns for commercial.
Thus, the IDT49C402A is 45% faster than five discrete parts
of the older 2900 family, the IDT49C402A could achieve
processing of approximately 15 MIPS.

COMPARISON OF 16-BIT
MICROPROGRAMMED SOLUTIONS

Dyna~ir
Power'
ABI- V/FLAG(1)

IDT49C402A
CMOS

4-2901C
& 2902A
BIPOLAR

29116
BIPOLAR

125mA

1049mA

735mA

37ns

68ns

84ns

Package
Space
Sq. Inches

0.32 LCC
1.5 DIP

1.8 LCC
5.04 DIP

0.56 LCC
2.08 DIP

Features

ALU
64 RAM
o REG
SHIFTER

ALU
16RAM
OREG
SHIFTER

ALU
32 RAM
ACCUM
BAR. SHIFT

2588 tbl 03
NOTE:
1. Reflects performance over commercial temperature and voltage range.

7.4

A 16-BIT SEQUENCER TO MATCH A
16-BIT ALU
While ALUs provide the data path for performing
computations, the sequencer is another important building
block which orchestrates the entire machine. The first
sequencer in the IDT49COOO family is the IDT49C410. The
IDT49C410 is architecture- and function code-compatible to
the 2910A, with an expanded 16-bit address path which
allows for programs up to 64K words in length.
The IDT49C41 0 is a microprogram address sequencer
intended for controlling the sequence of execution of
microinstructions stored in microprogram memory. Besides
the sequential accesses, it provides conditional branching to
any microinstruction within its 64K word range.
While the 2910A incorporates a 9-deep stack, the
I DT49C41 0 has a 33-deep stack which provides micro
subroutine return linkage and looping capability. This deep
stack can be used for highly nested microcode apPlications..
Referring to Figure 2, it can be observed that, during each
microinstruction, the microprogram controller provides a 16bit address from one of four sources: 1) the microprogram
address register (J..lPC) which usually contains an address of
one greater than the previous address; 2) an internal direct
input (D); 3) a register/counter (R) retaining data loaded
during a previous microinstruction; 4) a last-in first-out
stack (F).
The IDT49C410 is completely code-compatible with the
2910A. This allows the IDT49C410 to execute previously
written microcode, while allowing for more microcode to be
added to the application and taking the program beyond the
4K word boundary. Because the IDT49C410 is microcodecompatible, older microcode routines can be incorporated in
new designs utilizing the IDT49C410.
The 16-bit IDT49C410 uses approximately 1/4 the power
consumption of the 2910A (which is a 12-bit sequencer),
thus maintaining the 1/5 power consumption on a bit-by-bit
basis. The IDT49C410 consumes, over frequency and
4

16-BIT CMOS SLICES - NEW BUILDING BLOCKS MAINTAIN
MICROCODE COMPATIBILITY YET INCREASE PERFORMANCE

APPLICATION NOTE AN-06

DI

DECREMENT!
HOLD!LOAD

II

CLEARICOUN

CI

2588 drw 02

16
YI
Figure 2. IDT49C410 16-bit Microprogram Sequencer

temperature ranges, 7SmA for commercial and 90mA for
military. The 2910A compares with 340mA for military and
344mA for commercial. Because of the lower power
consumption, smaller packaging may be utilized. The
IOT49C410 is offered in a·standard 600 mil wide package
with pins on tenth inch spaces. '

WORKING TOGETHER

This allows the input side to be connected conveniently to an
8-bit bus for initialization at power up.
The second major section is on the right hand side. This
section is called the data path. The heart of this section is
the lOT49C402A. In it is contained all of the working registers
and the arithmetic logic unit for performing data computations.
One of the internal registers always contains the value of the
program counter (PC) which is the address at which the
opcode for the machine instruction is fetched. When an
opcode is fetched, the memory address register (MAR) is
loaded with the value of the PC while, at the same time, the
value of the PC plus one is loaded back into the internal
register. file. The OATAIN and OATAoUT registers are used
to buffer data coming from and going to the memory during
execution of the machine instruction.

The simplified block diagram of an example Central
Processing Unit (CPU) is shown in Figure 3 using devices
manufactured by lOT. This CPU architecture can be viewed
as two major sections which have a MICROSLICE family
part at the heart of each. The major section of the left hand
side of the diagram is the control path. The microprogram
sequencer at the heart is the lOT49C41 0 which generates
the address for the microprogram stored in the write able
control store (WCS). The output of the WCS is registered by COMPARISON OF MICROPROGRAM
the pipeline register. . Together, the sequencer, WCS and: SEQUENCERS
pipeline register make up a state machine which controls the
IDT49C410A IDT49C410
2910A
operation of the entire CPU. In this CPU, the state machine
CC-y(1)
24ns
15ns
24ns
first fetches a machine instruction and captures it in the
instruction register. The instruction register determines the
9
33
33
Stack Depth
starting address for each sequence of microinstructions
4K
64K
64K
Address Range
associated with each machine opcode.
Dynamic Power(1)
340mA
75mA
75mA
In this example, both the microprogram store and the
2588 tbl 04
instruction mapping memory are formed using RAM. The NOTE:
RAM has separate DATAINand DATAouTbuses (IOT71682). 1. Reflects performance over commercial temperature and vlotage range.
7.4

5

16-BIT CMOS SLICES - NEW BUILDING BLOCKS MAINTAIN
MICROCODE COMPATIBILITY YET INCREASE PERFORMANCE

APPLICATION NOTE AN-06

CONCLUSION
The MICROSLICE family from IDT provides highperformance CMOS solutions for microprogrammed
applications. Not only does the family provide for yesterday's
designs with plug-compatible devices of the IDT39COOO
family, it also provides solutions for future applications. With
the IDT49COOO family, the designer can take advantage not

only of the lower power consumption of CMOS, but utilize
higher speeds and smaller board spacing, yielding smaller
packaging concepts required by today's customers. In the
future, the IDT49COOO MICROSLICE family will provide
alternative architectures which will provide for yet higher
performance solutions.

16

16

o
ALU
AND
REGISTER
FILE
IDT49C402

IDT49C410

16

Y

ADDR
WRITABLE CONTROL STORE
IDT71682

8

DO

ADDRESS BUS

CONTROL BUS
2588 drw03

Figure 3. Central Processing Unit Block Diagram

•
7.4

6

t;)®
Integrated Device Technology, Inc.

APPLICATION
NOTE
AN-17

FIR FILTER
IMPLEMENTATION USING
FIFO AND MACs
By Suneel Rajpal and Dave Wyland

INTRODUCTION
This application note shows a relatively simple method of
implementing an N-tap finite duration impulse response (FIR)
filter using FI FOs for the data and coefficient storage instead
of space-consuming counters, RAMs and control logic. The
multiply-accumulate operations can be performed 16 x 16
multiply-accumulators (MACs) such as the IOT7210.
Finite duration impulse response filters are popular in many
OSP applications. FIRs have no feedback elements and no
poles and they are unconditionally stable. Also, with FI Rs one
can have linear phase response that may be important for
certain applications.
FIR filters are one of the basic building blocks of digital
signal processing (OSP). The FIR filter uses digital multipliers
and accumulators to perform a series approximation of an
analog filter. High-pass, low-pass and band-pass filters may
be implemented. The digital FIR filter has several advantages
over its analog counterpart. Its performance can be precisely
specified and does not drift with time. Also, the filter type and
performance can be changed with no change in hardware

components and not introduce any amplifier noise. These
features make the FIR filter popular in high-performance
designs.
The FIR filter continuously processes (i.e. filters) the digital
equivalent of the input analog signal. It does this by processing
each input digital data word in a repetitive manner as a sumof-products algorithm. In this algorithm, the current data word
and some number of previous data words used and by the
coefficients. The number of data words used is called the
number of filter taps. An N-tap filter uses N data words and
coefficients in the FIR calculation.
An FIR can be thought of as an average of incoming data
values. Each of the successive data values is multiplied by its
own coefficient and these values are totaled by an adder. A
block diagram of this operation is shown in Figure 1. This
sequence continues for each clock cycle as each data value
advances one position and is multiplied by a new coefficient
and a new sum is output. If one used a multiplier for every tap,
a1 to a4, and an adder that added the four products (the
multiplier outputs), a result can be obtained every cycle.

INPUT

a1

a2

a3

a4

1---

OUTPUT

2593 drw 01

Figure 1. FIR Block Diagram

In many applications, only one MAC is used and the
calculation is performed in 4 clock cycles for a four tap filter.
If a single chip MAC is used, the appropriate data and
coefficients are loaded to the MAC input registers. A new
output results every four cycles, while a new input data value
is loaded every four cycles. The hardware for loading the data
and the coefficients is RAM with up/down counters and some
logic. However, with the advent of FIFOs with asynchronous
read and write capabilities and retransmit capability, one can
have a better solution.
The IOT7201l7202 are high-speed 512 x 9 and 1K x 9

11:>1990 In1egra1ed Device Technology, Inc.

7.5

FIFOs that can be used to hold the data and coefficients
for FIR filters. Higherdensity FIFOs such as the IOT7203/
7204 (2K x 9/4K x 9) are also available. The IOT7201/
7202, shown in Figure 2, are high-speed buffers that
have an access time of 35ns and a cycle time of 45ns.
These FIFOs support asynchronous and simultaneous
read and write operations. On every falling edge of the
write line, a new write cycle begins and the read pointer
is incremented on every rising read edge. The data is
available after a delay of tA (or 35ns for the highest
speed part) after the falling read edge.

4190

1

FIR FILTER IMPLEMENTATION USING FIFO AND MACs

APPLICATION NOTE AN-17

DATA INPUTS
(Do-Os)

Vi

THREESTATE
BUFFERS
DATA OUTPUTS
(Oo-Os)

I-----+--~ EF
L-____-I----~---- FF

Xi------~

I------~

XO/HF
2593 drw 02

Figure 2. FIFO Block Diagram

The IDT7201/7202 FIFOs have a retransmit feature which
is particularly useful in applications where the same data is
repeatedly required. In a FIFO, N bytes can be written and
then read. The retransmit feature allows the same N bytes to
be read again without rewriting them. The retransmit feature
resets the read pointer in the FIFO to zero, allowing a reread

of the written information. If a FIFO is used to hold the filter
coefficients, the retransmit feature can be used to reread the
coefficients for each FIR calculation pass without having to
reload them. Retransmit is performed by pulsing the retransmit
input with the read and write clock lines high. This is shown
in Figure 3 and, in greater detail, in Figure 7.

T5
T3
T2
4
MAC DATA
IN X REG

T1

T4
T2
T3
T4
'2'3
T2

T3

TS
T4
T5
T3
T3
T4
T5
'5'3'4
T2

T3

T4

T7

T5
TS
T4
T4
T5
TS
,S,4,5
T3

T4

T5

TS
T5
'7
T4

MAC COEFFICIENT
IN Y REG
'
CLOCK IN
ENABLE DATA
RETRANSMIT
ONE FIR CYCLE:--j4-- ONE FIR CYCLE·--t4---- ONE FIR CYCLE
2593 drw 03

Figure 3. Sequence of Operations to Perform an FIR

7.5

2

I

FIR FILTER IMPLEMENTATION USING FIFO AND MACs

APPLICATION NOTE AN-17

The clock cycle time can be at 120ns with a 50% duty cycle.
For the data storage, the data is read from the FIFO, passes
through the multiplexer and is then stored back in the FIFO.
The delay path for the clock low time is as follows:
Read Going Low to Data on FIFO Output
FIFO Output to Multiplexer Output
Multiplexer Output to Write Going
Low-to-High (Set-up)

35ns
5ns
18ns

Minimum Clock Low Time

58ns

CLOCK

RT
t7
t6 = Time for External Circuit to Create RT Going From
High-to-Low = 10ns
t7 = Minimum Pulse Width for Retransmit Pulse = 3Sns
t8 = Read/Write High Time Requirement After the RT
Goes From Low-to-High = 10ns
2593 drw06

The delay path for the clock high time is as follows:

Figure 5. Clock High Timings

Control Circuit to Have RT Go From High-to-Low 10ns
Retransmit Minimum Low Time
35ns
Read and Write High Time After the RT
1Ons .
Low-to-High
Minimum Clock High Time

The MACs have input registers and an output accumulator.
The MAC specification is based on the multiply-accumulate
time or the time it takes for the input operates to be multiplied,
the accumulator added or subtracted from this product and the
result stored in the accumulator. The specification, called the
multiply-accumulate time, is a register-to-register delay.
Another timing consideration for the data path is the set-up
time for the MACs input registers. In the case of the FIFO
loading data to the MAC, the tA of the FIFO plus the set-up of
the MAC is 60ns (forthe IDT721 0 1OOns MACs) and this delay
is equal to the suggested clock low time.
With the configuration shown in Figure 6, the clocked cycle
time is 120ns at a 50% duty cycle using 35ns FI FOs (I DT720 1/
2) and 1OOns multiplier-accumulators (I DT721 0). This system
gives an output every 120ns where N is the number of taps.

55ns

Timing diagrams for these cases are shown in Figures 4 and

5.
CLOCK

",

//

)K

FIFO DATA
OUTPUT
t1
MULTIPLEXER
OUTPUT

)K

NEW DATA

t2

t3

t 1= FIFO Access Time, tA = 3Sns
t2= Multiplexer Delay = Sns
t3= FIFO Input Set-up Time = 18ns

ENABLE
NEW
DATA
DATA
FIFO
IDT7201

t

2593 drw04

CLOCK~
FIFO DATA

>K

COEFFICIENTS
LOAD
COEFFICIENT

COEFF.
FIFO
IDT7201

----+-~----t-1--~+ t2

t1 = FIFO Access Time = 3Sns
t2 = MAC Data Set-up Time = 2Sns on 1OOns (Com'!.) MAC
2593 drw05

FILTER OUTPUT

Figure 4. Clock Low Timings

2593 drw 07

Figure 6. Logic Implementation of N·Tap FIR

7.5

3

FIR FILTER IMPLEMENTATION USING FIFO AND MACs

APPLICATION NOTE AN-17

If the 120ns cycle time is considered slow for the user's the FIFO initially from another source and, after loading, the
application, a faster speed of 70ns cycle (60ns clock low and FIFO output data,becomes its input data (Le., the input MUX
1Ons clock high) can be achieved. This is done by recirculating selects the FIFO output to bethe input after the initial loading
the coefficient through the FI FO using a multiplexer instead of of the coefficients). This configuration reduces the clock high
using the retransmit feature, as shown in Figure 7. This is minimum time requirements as the retransmit feature is not
similar to the way the data is recirculated on the left side of. used. The clock low time does not change from the 60ns
Figure 6. The difference is that the coefficients are loaded into value.

NEW DATA
ENABLE
NEW
DATA

COEFFICIENTS
LOAD
COEFFICIENT

DATA
FIFO
IDT7201

COEFF.
FIFO
IDT7201
I - + - -...

W

1-+--'" R

FILTER OUTPUT
2593 drw 08

Figure 7. Logic Implementation of a Higher Speed N-Tap FIR

The FIFOs used in this application have 35ns access times,
but MACs faster than the 1OOns used in the previous example
have to be used. lOT has MACs that are as fast as 35ns
clocked multiply-accumulate times and these would have to

be used if the clock high time was only 1Ons.' The FI FO read
and write minimum high times are also 10ns. This system
yields a filter that gives an output every 70ns where N is the
number of taps.

II

7.5

4

Integrated Device1echnoIogy.1nc.

DESIGNING WITH THE
IDT49C460 AND IDT39C60
ERROR DETECTION
AND CORRECTION UNITS

APPLICATION
NOTE
AN-24

By Robert Stodleck

INTRODUCTION

buffers to be a latched type such as an IDT74FCT646 instead of the
IDT74FCT245 shown. A family of waveforms appropriate for the
bus format shown in Figure 1 is shown in Figure 2. The waveform
diagrams do not include precise timing considerations which are
left to the designer.
In any given system, any of the buffers separating the EDC from
the memory IC's may be eliminated if bus capacitance and speed
considerations allow.

The Error Detection and Correction (EDC) chip itself is one
element of an EDC system. How it is connected to the surrounding
system and controlled is left to the system designer. Because there
are so many design variations possible, it is important for the
designer to develop a clear idea of the target design before
beginning the design process. Basic design approaches and
perturbations are enumerated in this application note.
The details of the EDC control logic depend on the configuration
of the EDC system, EDC bus topology, the nature of the CPU or
system bus involved and the nature of diagnostic hardware used.
The data bus topology is highly dependent on the individual target
system.
This applications note approaches the bus topology issue first.
The advantages and disadvantages of using EDC word widths that
are different from the system bus are discussed. The next topic to
be covered is the use of EDC in a system with a cache. Then the
operational configuration of the EDC system is discussed. This
implies answering questions about how the EDC unit handles
errors in a particular system is discussed. How an operating
system deals with the EDC function is discussed, followed by a
practical discussion of some non obvious hardware topics. The
final topic is memory system diagnostics and verification. An
appendix includes tables and software that are useful in
debugging and in writing diagnostic software for an EDC board.

EDC Bus Width vs. System Bus Width
The width of the EDC bus and the System Bus are normally
matched. However, there are valid reasons for making the EDC
bus both wider or narrower than the system bus.
Wide EDC words are significantly more efficient than narrower
EDC word widths in terms of the amount of check-bit memory used
for a given amount of data memory. The amount of check-bit
memory required for 64 data bits is 8 bits if the 64 data bits are
organized as one word and 14 bits if it is handled as two 32-bit
words. Twenty-four bits of check-bit memory would required for
64 data bits organized as four 16-bit EDC data words.
For the purposes of speed, it would be ideal to have 8-bit EDC
words for systems that do byte write operations. This would make it
unnecessary to ever have to read a memory location prior to writing
a partial word on these systems. Unfortunately, eight-bit EDC
words are grossly inefficient in terms of check-bit memory usage.
Therefore, the EDC word widths are normally 16-bits or more.
Since the EDC word widths must generally be 16-bits or more
for check-bit memory efficiency, and since general-purpose
computers generally use byte or partial-word-write operations,
general-purpose computers force the EDC unit to be able to
process partial EDC word-width write operations. Partial
word-width write operations require the EDC subsystem to execute
a read-modify-write type memory cycle. Thus, the EDC controller
must take over control of the memory system and execute a read
before completing a partial word write. For some applications,
where EDC is in use, it may be desirable to speed up processing by
prohibiting partial word operations either at the hardware level or
software level. Speed critical sections of code should be executed
without partial-word write operations.
The read-modify-write EDC cycle executed during a
partial-word write is identical to the EDC correction cycle executed
during a read cycle when an error has occurred. The
read-modify-write EDC cycle should not be confused with the
read-modify write cycle executed by some CPU's.
Verification of a memory system using an EDC word wider than
the system word is complicated by the fact that all memory write
cycles become read-modify-write cycles i.e. partial-word-write
EDC cycles. Careful consideration of diagnostic procedures
needs to be made during the design to avoid unnecessarily
complex debugging procedures.

Data Bus Topology
Most contemporary CPUs execute write operations of a byte or
other sub-word width types. These cause special problems for all
EDC units since EDC transactions with the memory are carried out
on whole width EDC words. To facilitate partial word write
operations with the IDT39C60 or IDT49C460 type EDC units, a set
of tri-state transceivers are normally required between the system
bus and the EDC unit. These buffers are required to prevent bus
contention between the CPU or system bus drivers and the EDC
units data outputs during partial word write operations. Figure 3
shows a bus arrangement appropriate for large DRAM arrays. The
need for isolation of the EDC data bus and the system bus is shown
by examining the data paths, shown with white arrows. These are
used by the final write operation of a partial-word write cycle. In this
case, only data bits 0-7 are being written from the processor to
memory. If the processor or system bus drivers can be tri-stated on
byte boundaries then this set of buffers could be removed, but this
is not a common situation.
Depending on the memory size, additional buffering may be
required between the EDC and the memory bus proper. The buffer
configuration must be determined before beginning the EDC and
memory controller design.
An appropriate general purpose bus topology is shown in
Figure 1. It is common for one or the other sets of bi-directional

©

1989 Integrated Device Technology, Inc.

Printed In the U.S.A.

7.6

01/88

DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECTION AND CORRECTION UNITS

APPLICATION NOTE AN-24

OPTIONAL

CPU

MEMORY
CARD

SEPARATE I/O
CHECK-BIT RAM

Figure 1. A general purpose 16-blt EDC data bus topology. Corresponding timing waveforms are shown In Figure 2. IDT74FCT245 buffers
separate the EDC data bus from the CPU and the main memory. Separate-I/O RAMs are used In the check-bit memory.

II

7.6

2

DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECTION AND CORRECTION UNITS

APPLICATION NOTE AN-24

READ - NO ERROR

READ - CORRECT ALWAYS OR
CORRECT ON ERROR

ERROR DETECT
TIME LIMIT

ERROR DETECT
TIME LIMIT

NON-CASCADED
CONFIGURATION

o

OEN
TiR

...

I--

r:.

OE BYTEm
LEIN

~

~

l-

e

ERROR

~
l-

n. ~

=-...

OEN

-

•

OE BYTE n
OE BYTEm
LEIN
LEOUT
/GEN
ERROR

r

M

m

UU-

e•

,

-

-

T/R

I-

I--

245 GROUP - UPPER AN o LOWER
BYTES - MEMORY TO EDC BUS
NOTE: T/R = 1
OEN
DRIVES EDC BUS
T/R
DATA TOWARD
MEMORY BUS

J. U-

1m

LEOUT
/GEN

OEN

TiFi

245 GROUP - UPPER BY TE
PROCESSOR TO EDC B US - OEN
NOTE: T/R = 1
lDRIVES PROCESSOR
T/R
BUS DATA TOWARD
r-EDC BUS.
39C60 GROUP
CORRECT=1
OE BYTE n
I--

-

o

1 23 4 WW 5 6 7

245 GROUP - LOWER BY TE
PROCESSOR TO EDC B US

OEN

WE

I~ ~

r

...

OE BYTE n
OE BYTEm
LEIN

I-

LEOUT
/GEN

I--

~

U-

I-

~

U-

I--

Ll

lI-

=.
r-

ERROR

I-

n

OEN

-

I--

OEN

l-

T/R

t-

II!

OEN

1 234 5 6 7 8 9

T/Fi

I--

T/R

WE

r:;:;:;:;:;:;:;· I;:;:;::.

I--

n

o

1 23 4 5 6 7

1:::;:;:::;:;:;:; :;:;:;:;.
I-

71256 GROUP - UPPER AND LOWER BYT I:=s
71981 CHECK BIT MEMO RY
OEN

WRITE PARTIAL WORD
- CORRECT ALWAYS

r

...

OEN

TiFi

m

OEN

L.

WE

r

'M

•

--

1::

I~ ~

Figure 2. A sample family of timing waveforms for an EDC system. The target system Is based on IDT71256 static RAMs for main memory
with IDT71981 separate I/O RAMs for checkbit memory. (See Figure 1.) The partial word write case illustrates a low order byte write.

7.6

3

DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECTION AND CORRECTION UNITS

APPLICATION NOTE AN-24

1-------------- ..

32-Bit
CPU or
SYSTEM
BUS

DRAM
Figure 3. A general purpose 32-bit EDC bus topology for 1 bit wide DRAMS. The white arrows Indicate the data flow paths used on the final
write phase of a partial word write cycle. Data bits 0-7 are being written Into memory from the processor.

EDC in Systems Using Cache

instruction word back to memory after detection, since the
instruction is usually backed up on a different media. In most
systems there is no way for the EDC to know whether it is operating
on instructions or data, so a correction philosophy must be
selected that can be applied to both instruction and data words.

In systems using cache memory, it may be desirable to place
the EDC function between the cache and main memory, as
opposed to locating the EDC function between the processing
elements and cache. Parity can be used as a single-bit error
detection scheme between the CPU and cache. RISC
architectures tend to require more memory accesses per unit time
that complex-instruction-set processors. This makes the use of
cache memory more important in the RISCsystem. An appropriate
bus topology for a RISC type processor with cache memory is
shown in Figure 4.
Use of a cache memory also affords the possibility of using a
different error correcting philosophy. If the EDC function is located
between the cache and main memory, then it may be allowable for
data reads to be corrected and sent on to the cache, but not to be
immediately written back to main memory, after an error has been
discovered. In this approach, corrected memory words are
updated in the normal write-back processes of the cache memory.
Instruction reads must be thought of differently than data reads
since instructions are normally not written back to memory from the
cache. However, it may be possible to not write a corrected

Diagnostic Hardware
A syndrome latch for capturing syndrome values after errors
and transferring them to the system data bus is always
recommended. Providing a check-bit memory read-back ability
allows direct verification of the gross functionality of the check-bit
memory 'on board'. This greatly facilitates check-bit memory
verification. More subtle problems can be explored indirectly by
interpreting correction patterns on known data or by using
syndrome data to interpret failure patterns. Depending on the EDC
configuration, it may be possible to use the same latch to capture
check-bits from the check-bit memory, or a second latch may be
provided to allow this.
Ideally, diagnostic hardware includes address latches to
capture the address of an error. However, this may not be practical
in any particular application. It may be sufficient to identify the
individual RAM in which an error has occurred.

7.6

4

I

DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECTION AND CORRECTION UNITS

APPLICATION NOTE AN-24

R2000A

RISC
CPU

RISC

CACHE

CPU

RAM

WRITEBACK
BUFFERS
DRAM

EDC
Figure 4. An EOC bus arrangement appropriate for a CPU with caches such as the IDT R3000 or lOT R2000 RISC processor.

7.6

5

DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECTION AND CORRECTION UNITS

APPLICATION NOTE AN-24

It is desirable to log single bit errors and as much information
about the error as is practical. Relevant data ideally includes the
syndrome bits to identify the' bit location in the word, and the
physical address of the error. For complete EDC transparency,
such as that desired for real time systems, error logging must be
eliminated or accommodated entirely in hardware. For non
real-time systems, interrupting the CPU after an error occurrence is
the conventional way to log error data. Syndrome data is collected,
and any other error information the system hardware retains is
retrieved.

OVERVIEW OF EDC OPERATIONAL MODES
Bus Watch vs. Correct Always for the Memory
Read Cycle
In a bus-watch system, errors are only corrected after they have
been detected by the EDC chip. Data is corrected and written back
to memory to scrub errors, only after an error has been detected. In
theory, the EDC chip only "watches" the bus normally, and does
not slow memory read cycles with correction delays unless an
error has been detected. Since errors during read operations are
normally very rare, read cycle bus-watch systems are normally
faster than correct-always systems.
In correct-always systems, data read by the system is always
corrected. The EDC control logic is simpler to design and
implement because there is only one type of read cycle. Memory
cycle timing in correct-always systems can be completely
deterministic and thus such systems may lend themselves more
effectively to real-time applications.

Non-obvious Hardware Topics
In a 32-bit system with a bi-directional check-bit bus or in 64-bit
cascaded mode, the check-bit input-output and syndrome
functions are ti me-multiplexed onto the same bus. If the EDC unit is
in the correction mode, the input latches are open, and the OESC
pins are low, the bus will tend to oscillate. This combination of
control inputs would not be appropriate for normal operation but
might occur in an idle period between memory cycles unless the
designer specifically designs this condition out. The oscillation
occurs in this condition because the EDC units are attempting to
output syndrome bits based on the data and 'check-bit' inputs.
However, the syndrome outputs in this state are being fed back to
the check-bit inputs. The result is an oscillation on the check-bit!
syndrome bus.
It is an important and sometimes overlooked fact that it is not
acceptable to allow inputs on most CMOS parts to 'float'. The result
of doing this is increased power consumption, on chip noise and
sometimes outright oscillation which can lead to latch-up. The
check-bit inputs and the data bus of an EDC unit should not be
allowed to float when not being used. In low power systems in
particular, all inputs not in use must be brought to logic highs or
lows when not in use. This may imply not tri-stating some buffers
that would otherwise be tri-stated when not actively driving, or
actually including pull-up or pull-down resistors on a bus to bias it
when it is not actively being driven.

Bus Watch vs. Correct Always for the Partial Word
Write Cycle
A write operation that is of a width less than the EDC word width
forces the EDC subsystem to execute a read cycle prior to actually
writing to memory. This is required to provide the EDC unit with the
whole data word to be written into memory for the purpose of
check-bit generation. No time is saved by not correcting the data
read from memory prior to the subsequent write operation. The
partial-word-write operation is virtually identical to a read cycle in
correct-always mode or a read cycle with an error detected.
Consequently, a partial word write is usually done in a "correct
always" mode.

Operating System Involvement
In systems capable of doing partial-word-write operations, it is
necessary to initialize the memory on power up. This can be done
in hardware but it is usually done by the operating system.
Initialization implies writing every memory location with an
arbitrarily chosen constant and thereby writing the check-bit
memory with the correct corresponding check.bits. The need to
initialize memory results from the nature of the read-modify-write
EDC cycle required by the event of a partial-word-write operation. If
the memory has not been initialized, the read cycle will normally
result in an error indication and an attempt to 'correct' a bit in the
data field before writing back to memory. This tends to introduce
errors into previously written data bytes or sub-words.
It is possible to design a state machine EDC controller that
corrects all single bit errors in a fashion transparent to the CPU.
This is not always desirable since it masks hard single-bit errors
that indicate hardware problems. In any case, the operating
system must become involved in the event of multiple errors if only
to issue an appropriate error message to the system operator.

Basic EDC Unit Operation
Basic 32-bit 49C460 EDC operation with timing diagrams is
illustrated in Figures 5,6 and 7. These timing diagrams are also
appropriate for a 16-bit IDT39C60 system. In the IDT39C60, the
LEout and the Generate functions have separate pins. In the
IDT49C460, they are both controlled by one pin. It is usually
convenient when using the IDT39C60 to wire the two pins together.
In the non-expanded case, with either EDC unit, use of the input
latch may be convenient but is not logically dictated (Le. the LEin
pin may be tied high). Also, the correct pin may be simply left
asserted in normal operation. The "detect" mode is usually only
used as a diagnostic aid, which allows the data correction function
to be shut off while still generating an error signal based on the
input data.

7.6

6

II

DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECTION AND CORRECTION UNITS

APPLICATION NOTE AN-24

Diagnostic Modes

Memory.System Verification Strategies

Since the EDC function introduces a complicating layer
between the system bus and the memory, diagnostic modes are
provided for the EDC to provide testability for the entire memory
subsystem. In memory systems where the EDC word is wider that
the system bus memory, verification is complicated by the fact that
all writes are partial word writes. Good diagnostic design requires
forethought.
The EDC unit's internal diagnostic latches have two distinct and
unrelated data·fields. The check-bit data field is used to provide
check data to be substituted for normal check-bits in the diagnostic
modes. These will be written to memory in diagnostic generate
mode, or substituted for check-bits read from memory in
diagnostic-detect or correct mode. The second field in the
diagnostic latch is the control field. The control field is ignored
except when the part is placed in the internal control mode.
The control byte is used to control the operating features of the
part when the part has been placed in Internal control mode. Each
bit in the control field corresponds to a pin on the part and overrides
the logic sense of that pin when the part is in the internal control
mode. For example, we could place the part Into the correct mode
by setting the correct pin on the EDC unit to a logic high, or we
could put the part into the internal control mode and set the correct
bit in the diagnostic latch to "'. Thus there are always two ways to
achieve any mode of operation. For example, the diagnostic
modes may be entered by setting the external diagnostic inputs
appropriately, or entering the internal control mode and setting the
diagnostic latch bits appropriately. The internal control mode is
provided as a convenience and is useful for controlling operating
modes during diagnostic testing and software initialization.
Conceptually, it is important to realize that anything that can be
done in this mode can be done with external logic as well.

When a new design is being verified, it is critical to isolate
different problem factors; this is one function of the EDC
diagnostics.
To prove the function of the primary memory array, the EDC unit
is placed in the pass-through mode so that it does not interact with
the data stream. Once the primary memory array has been verified
as functional, the check-bit memory must be verified. The
diagnostic generate mode is used to write known data into the
check-bit memory. Reading the check-bit memory directly
through the EDC is not possible, so gross functional testing must
be done via an external latch or with a logic analyzer. Using an
external latch greatly facilitates check-bit memory verification.
Collecting syndrome data from error events requires that an
external latch be included in the design to capture the syndrome
data after an error has occurred. It should be possible to clear this
latch after reading its contents from the system bus. Depending on
the EDC configuration, it may be possible to use the same latch to
capture check-bits from the check-bit memory. More subtle
problems can be explored indirectlY by interpreting correction
patterns on known data or by using syndrome data to interpret
failure patterns.

7.6

SUMMARY
The error detection and correction unit is located in the critical
path between a CPU and the memory. The operational
configuration of the EDC intimately affects the speed of the final
system. Due to the wide variation between computer architectures
that EDC is desirable for, the EDC unit is necessarily a generalized
IC. Thus, designing an EDC system is' not a straightforward
process. The object of this applications note has been to illuminate
some of the topics that any designer will encounter in the process
of designing an EDC system.

7

DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECTION AND CORRECTION UNITS

APPLICATION NOTE AN-24

WRITE WORD TO MEMORYGENERATE CHECK-BITS - WRITE CHECKBITS TO MEMORY

SCO-7

~~-----.~

.L:~~-r1l------.MULTERROR

LEDIAG

-==t==nr=~.L4

CODE 100.1DIAG MODEo 1 -----1--'----+.-1

LEouT/GE"N-----I--''-':'-I~
CORRECT--~2T~~~~~ii

I

DIAG MOD Eo.

1

= 00

LEDIAG =

X

CODE 100. 1 = 00

PDAE T@RS00002 8/18/87

Figure 5. 32-bit full-word-width write operation (generate mode).

7.6

8

DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECTION AND CORRECTION UNITS

APPLICATION NOTE AN-24

~
DATA
DO

DI

I

CHECK BITS
DO

DI

READ WORD FROM MEMORY - DETECT ERRORS CORRECT WORD AND LATCH CORRECTION IN OUTPUT LATCH

ERROR DETECT
MIN TIME LIMIT
LEoUT/~

~n

DATA, CB

CORRECT

SCa-7

DIAG MODEa. 1 = 00

LEDIAG = X

CODE IDa.

1

= 00

PDAE T@RS00003 8/18/87

Figure 6. Memory read and error detect. Identical for read operations and the first phase of a partial-word-write operation (correct mode).

7.6

9

DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECTION AND CORRECTION UNITS

APPLICATION NOTE AN-24

~
DATA
DO

01

I

CHECK BITS
DO
01

WRITE CORRECTED WORD AND
CHECKBITS TO MEMORY

.....
1 ...._ _ _ _ _ _ _......._

CBo-71

.::::...

I.....
i:.:..

::

...._ ...._ ................_ ...

:: . .:.::.:.<:<:.:<::.:.:> . . . :.::::::

.:

> : . .:.> . <>.•. :.:. :.:}>

.. ::.: .••.::>

.. I

OE" 0-3

•.. ::.

.

< .: .:.: .•:.: .•.·:·:.1
. L....:. :> / i

::.
~<
• :.:•. >
:.:•. •. X< ••.•. ••
::.•..•. < .M
. :....·: .:U.... .:X.... ):tI

:}2<:

ER
.R
DATA
OUT L.11IIII.t:
....O:.R. D
...E.....C... O.... :.D. . .:. :E. . . :. . .
LATCH
L~ ...&CORRECT::

I)

•. .

..:

. . .· . .

......'~.> :. :. :. : . :. . :. . :.:. : . : . :. . . . . . :·:. . . :. ::;~t)
DATA INPUT r
:. .
> .. : CHECK BIT
.•....:: ",,;:::::i

•: . ~<

<

SYSTEM
('
MEMORY BUS'

LATCH

I

GENERATEI:_

: ~P,~~~t~~;. ~.-;-i<
()
)

.:..+
I·:::

.: ••. ::.:: .• :.

plAGNOSTlp

i .: :.JNLATCH

,<~U)

......1'01::.......~. SCO-7

1,«'1·: . :

~ "'.;, ;.[....~---

~: ••••••:~ ~~~~~~~EI
~5~~~~T
I.• :
.....>
. .

IT •.'::>::>

.:::.>

~

OE"sc

nrnm:J"RrT"iT""'' ' --'-' ' ' ' ' ' '

..

••: : : : i

:..:):<

.....

LEDIAG
CODE 100.1
DIAG MODEo 1
LEoUT/GEN
CORRECT
•••••

PDAE RWS00004 8/18/87

LEoUT/GEN

.lr\
.....__________..6IX
..
\XXXXXXXXX
I[

DATA

XXXXX

IX

I

CORRECT

SCO-7

XXXXX

DIAG MODE o. 1 = 00

LEDIAG = X

CODE 100.

1

= 00

Figure 7. Memory correct and check-bit regenerate. Identical for the second phase of a read operation in which an error has occurred, and
for a partial-word-write operation except for the state of the individual byte output enables.

7.6

10

DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECTION AND CORRECTION UNITS

APPLICATION NOTE AN-24

Appendix
0

1

2

3

4

5

6

7

DECIMAL

S6

0

0

0

0

1

1

1

1

SYNDROME

S5

0

0

1

1

0

0

1

1

HE~

S4

0

1

0

1

0

1

0

1
30

HEX

ERROR

0

S3

S2

Sl

SO

0

0

0

0

DECIMAL EQUIVALENT> >

NE

C4

C5

T

C6

T

T

0

16

32

48

64

80

96

112

T

T

14

T

M

M

T

1

0

0

0

1

CO
1

17

33

49

65

81

97

113

2

0

0

1

0

C1

T

T

M

T

2

24

T

2

18

34

50

66

82

98

114

3

0

0

1

1

T

18

8

T

M

T

T

M

3

19

35

51

67

83

99

115

4
5
6
7

0
0
0
0

1
1
1
1

0
0
1
1

0
1
0
1

8

1

0

0

0

9

1

0

0

1

C2

T

T

15

T

3

25

T

4

20

36

52

68

84

100

116

T

19

9

T

M

T

T

31

5

21

37

53

69

85

101

117

T

20

10

T

M

T

T

M

6

22

38

54

70

86

102

118
T

M

T

T

M

T

4

26

7

23

39

55

71

87

103

119

C3

T

T

M

T

5

27

T

8

24

40

56

72

88

104

120

T

21

11

T

M

T

T

M

9

25

41

57

73

89

105

121

12

T

1

T

T

M

A

1

0

1

0

T

22

10

26

42

58

74

90

106

122

B

1

0

1

1

17

T

T

M

T

6

28

T

11

27

43

59

75

91

107

123

C

1

1

0

0

T

23

13

T

M

T

T

M

12

28

44

60

76

92

108

124
T

D

1

1

0

1

M

T

T

M

T

7

29

13

29

45

61

77

93

10

125

M

T

M

M

T
126

E

1

1

1

0

16

T

T

14

30

46

62

78

94

110

F

1

1

1

1

T

M

M

T

0

T

T

M

15

31

47

63

79

95

111

127

NE= NO ERROR
Cn = check-bit error bit n
n = data-bit error bit n
n = decimal equivalent of the syndrome

T = Two errors
M = Multiple errors

Table 1. 32-bit Syndrome Tables with Hex, Binary and Decimal Equivalents.

7.6

11

DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECTION AND CORRECTION UNITS

HEX

ERROR

S7
S6
S5
S4

IHEX

S3

S2

Sl

SO

I

0

0

o

0

0

I

0

0

I 2

0

0

I

I

I

3

0

4

I 6
7

0

9

0

A

B

I

I Ell
F

I
I
I

7

o

o
o

o

o

o

8

9

A

B

o
o
o

o
o

o

o

o

C

D

o
o

o

E

F

o

T

C6

T

T

62

C7

T

T

46

T

M

M

48

64

80

96

112

128

144

160

176

192

208

224

240

I

CO

T

T

14

T

M

M

T

T

M

M

T

M

T

T

30

1

17

33

49

65

81

97

113

129

145

161

177

193

209

225

241

o I

Cl

T

T

M

T

34

56

T

T

50

40

T

M

T

T

M

2

18

34

50

66

82

98

114

130

146

162

178

194

210

226

242

T

18

8

T

M

T

T

M

M

T

T

M

T

2

24

T

3

19

35

51

67

83

99

115

131

147

163

179

195

211

227

243

C2

T

T

15

T

35

57

T

T

51

41

T

M

T

T

31

4

20

36

52

68

84

100

116

132

148

164

180

196

212

228

244

T

19

9

T

M

T

T

63

M

T

T

47

T

3

25

T

5

21

37

53

69

85

101

117

133

149

165

181

197

213

229

245

0

I
I

0

I
I

o I

0

o

6

o

32

o

0

I C I
I I
I DI
I I
I
I
I

o

5

o

C5

0

8

4

o

16

o I

0

3

o
o

C4

o

0

2

o
o

NE

o

o

o
o
o

o

0

0

5

I
I

o
o
o
o
o

APPLICATION NOTE AN-24

0

o

I
I

o

T

T

20

10

T

M

T

T

M

M

T

T

M

T

4

26

T

6

22

38

54

70

86

102

118

134

150

166

182

198

214

230

246

M

T

T

M

T

36

58

T

T

52

42

T

M

T

T

M

7

23

39

55

71

87

103

119

135

151

167

183

199

215

231

247

C3

T

T

M

T

37

59

T

T

53

43

T

M

T

T

M

8

24

40

56

72

88

104

120

136

152

168

184

200

216

232

248

T

21

11

T

M

T

T

M

M

T

T

M

T

5

27

T

9

25

41

57

73

89

105

121

137

153

169

185

201

217

233

249

T

22

12

T

33

T

T

M

49

T

T

M

T

6

28

T

10

26

42

58

74

90

106

122

138

154

170

186

202

218

234

250

17

T

T

M

T

38

60

T

T

54

44

T

1

T

T

M

11

27

43

59

75

91

107

123

139

155

171

187

203

219

235

251

T

23

13

T

M

T

T

M

M

T

T

M

T

7

29

T

12

28

44

60

76

92

108

124

140

156

172

188

204

220

236

252

M

T

T

M

T

39

61

T

T

55

45

T

M

T

T

M

13

29

45

61

77

93

109

125

141

157

173

189

205

221

237

253

16

T

T

M

T

M

M

T

T

M

M

TOT

T

M

14

30

46

62

78

94

110

126

142

158

174

190

206

222

238

254

T

M

M

T

32

T

T

M

48

T

T

M

T

M

M

T

15

31

47

63

79

95

111

127

143

159

175

191

207

223

239

255

NE=NO ERROR

II

T = Two errors
M = Multiple errors

en = check-bit error bit n
n = data-bit error bit n
n = decimal equivalent of the syndrome

Table 2. 64-bit Syndrome Tables with Hex, Binary and Decimal Equivalents.

7.6

12

DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECTION AND CORRECTION UNITS

APPLICATION NOTE AN-24

CB

DATA

CB

DATA

CB

DATA

CB

DATA

0

28

20

127

40

E

60

101

1

1000F

21

10100

41

10029

61

10126

2

10000

22

1010F

42

10026

62

10129

3

27

23

128

43

63

10E

4

1000C

24

10103

44

1002A

64

10125

5

28

25

124

45

D

65

102

6

24

26

128

46

2

66

100

7

10003

27

1010C

47

10025

67

1012A

8

10024

28

10128

48

10002

68

10100

9

3

29

10C

49

25

69

12A

A

C

2A

103

4A

2A

6A

125

8

10028

28

10124

48

10000

68

10102

C

0

2C

10F

4C

26

6C

129

D

10027

2D

10128

4D

10001

6D

1010E

E

10028

2E

10127

4E

1000E

6E

10101

F

F

2F

100

4F

29

6F

126

10

10022

30

10120

50

10004

70

10108

11

5

31

10A

51

23

71

12C
123

12

A

32

105

52

2C

72

13

10020

33

10122

53

10008

73

10104

14

6

34

109

54

20

74

12F

15

10021

35

1012E

55

10007

75

10108

16

1oo2E

36

10121

56

10008

76

10107

17

9

37

106

57

2F

77

120

18

2E

38

121

58

8

78

107

19

10009

39

10106

59

1002F

79

10120

1A

10006

3A

10109

5A

10020

7A

1012F

18

21

38

12E

58

7

78

108

1C

1000A

3C

10105

5C

1002C

7C

10123

10

20

30

122

50

B

70

104

1E

22

3E

120

5E

4

7E

108

1F

10005

3F

1010A

5F

10023

7F

1012C

Table 3. Minimal 32-bit check-bit to data tables for diagnostic use. One data value is listed to generate every possible check-bit pattern.

7.6

13

DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECTION AND CORRECTION UNITS

APPLICATION NOTE AN·24

DATA

CB

DATA

CB

DATA

CB

DATA

0

C

100

2F

10000

2

10100

21

1

43

101

60

10001

4D

10101

6E

2

46

102

65

10002

48

10102

6B

3

9

103

2A

10003

7

10103

24

4

5E

104

7D

10004

50

10104

73

CB

5

11

105

32

10005

1F

10105

3C

6

14

106

37

10006

1A

10106

39

7

5B

107

78

10007

55

10107

76

8

58

108

7B

10008

56

10108

75

9

17

109

34

10009

19

10109

3A

A

12

10A

31

1000A

1C

1010A

3F

B

5D

10B

7E

1000B

53

1010B

70

C

A

10C

29

1000C

4

1010C

27

D

45

10D

66

1000D

4B

1010D

68
6D

E

40

10E

63

1000E

4E

1010E

F

F

10F

2C

1000F

1

1010F

1F

20

54

120

77

10020

5A

10120

79

21

1B

121

38

10021

15

10121

36

22

1E.

122

3D

10022

10

10122

33
7C

23

51

123

72

10023

5F

10123

24

6

124

25

10024

8

10124

2B

25

49

125

6A

10025

47

10125

64
61

26

4C

126

6F

10026

42

10126

27

3

127

20

10027

D

10127

2E

28

0

128

23

10028

E

10128

2D

29

4F

129

6C

10029

41

10129

62

2A

4A

12A

69

1002A

44

1012A

67

2B

5

12B

26

1002B

B

1012B

28

2C

52

12C

71

1002C

5C

1012C

7F
30

2D

10

12D

3E

1002D

13

1012D

2E

18

12E

3B

1002E

16

1012E

35

2F

57

12F

74

1002F

59

1012F

7A

Table 4. Minimal 32·bit data to check·bit tables for diagnostic use. At least one data value is listed for every possible check·bit pattern. This
table is identical to Table 3 except in sequence of presentation.

7.6

14

I

(;)®
Integrated Device Technology, Inc.

APPLICATION
NOTE
AN-32

IMPLEMENTATION OF DIGITAL
FILTERS USING IDT7320,
IDT7210,IDT7216, AND IDT7383
By Tao Lin and Dahn Le Ngoc

INTRODUCTION
Traditionally, signal processing tasks were performed with
specialized analog processors. However, it is well known that
digital techniques have some inherent advantages such as
flexibility, accuracy, reliability over analog techniques.
Moreover, because of the rapid progress in digital computer
and VLSI technology, both digital processing units and storage
devices are becoming less expensive yearby year. Therefore,
the digital approach is usually preferred over modern signal
processing.
Digital filtering is one of the most important digital signal
processing techniques. This technique has found many
applications in a variety of areas. Perhaps the most widely
known applications of digital filtering have been in the area of
speech processing and communication. In many situations,
speech signals are degraded in ways that limit their
effectiveness for communication. In such casesdigitalfiltering
techniques are applied to improve speech quality (to remove
noise or echoes from speech, etc.). Lowpass and bandpass
digital filters have also been utilized in speech analysis and
synthesis, speech coding, and data compression. Digital
filtering techniques have also been widely used in the area of
image processing: enhancement of the image to make it more
acceptable to the human eye; removal of the effects of some
degradation mechanism; separation of features for easier
identification or measurement by human or machine. For
example, we can use two-dimensional digital filters to reduce
spatial low-frequency components in an X-ray image, and this
process will make features with large high-frequency
components such as fracture lines easier to identify.

A digital filter is said to be causal or realizable if the output
at n = no is dependent only on values of the input for n~ no. This
implies that the impulse response h(n) is zero for n < O. The
most important subset of the class of causal digital filters is
that where the transfer function H(z) can be described by an
Nth-order rational function
H(z)

=I

h(k)z-k

k=O

=

ao + a1 Z-1 + ... + aN z-N
1 -b1Z-1 - ... -bN Z -N

(2-1)

FIR FILTERS
A digital filter is said to be a finite impulse response (FIR)
filterifthe numberof nonzero h(k) is finite. Otherwise, it is said
to be an infinite impulse response (IIR) filter. It can be readily
seen that for FIR filters, the denominator of H(z) is 1, i.e. the
transfer function becomes
H(z) = h(O) + h(1 )Z-1 + h(2)r2 + .... + h(N)z-N
= ao + a1z- 1 + a2r2 + .... + aNrN

(2-2)

The output of an Nth-order FIR filter can be calculated from
N+1 input data as follows:
y(k) = aOJl.(k)"+ a1Jl.(k-1) + a2Jl.(k-2) + .... + aNJl.(k-N),
for k = 0, 1, 2, ....
(2-3)
with initial conditions: Jl.(-1) = Jl.(-2) = .... = Jl.(-N) = O.
Therefore, FIR filters nonrecursive and can be implemented
by using adders, multipliers and delay elements without a
feedback path. The canonical form of an FIR filter is illustrated
in Figure 2.
ao

BASIC THEORY OF DIGITAL FILTERS
General Form
A digital filter is a system or device which transforms an
input sequence {Jl.(k)} into an output sequence {y(k)}. As
shown in Figure 1, a digital filter is characterized by its impulse
response {h(k)} or by its transfer function H(z).

~(k)--~1 H(k)=k~~z-k II----·y(k)

y(k)

2585 drw 01

Figure 1. Block Diagram of Digital Filter

The output sequence can be calculated from the input
sequence as follows:
y(n)

=I

h(k) Jl(n-k)

k =-00
2585 drw 02

Figure 2. Block Diagram of Canonical FIR Filter
©1990 Integrated Device Technology. Inc.

7.7

4/90

1

IMPLEMENTATION OF DIGITAL FILTERS USING 1DT7320,
IDT7210,1DT7216, AND IDT7383

APPLICATION NOTE AN-32

IIR Filters
On the other hand, IIR filters are recursive, i.e., the output
of an II R filters is calculated from both input data and previous
output data as follows:
y(k) = b1y(k-1) + b2y(k-2) + .... + bNy(k-N)
+ aOIl(k) + a11l(k-1) + a21l(k-2) + .... + aNIl(k-N),
for k = 0, 1,2, ....

y(k) of the transversal structure is simply the weighted sum of
the current input Il(k) and the delayed inputs ll(k-1), ll(k-2).
The coefficient ao, a 1, .... determine the frequency response
of a particular filter such as lowpass, bandpass or highpass.

ao
(2-4)

with initial conditions: 11(-1) = 11(-2) = .... = Il(-N) = O. The
canonical form of IIR filters is shown in Figure 3.
While FIR filters have the advantages of being
unconditionally stable,less sensitive to quantization error and
linear phase, IIR filters have lower order than FIR filters with
equivalent performance. Therefore, IIR filters require less
memory and fewer arithmetic operations than FIR filters.
ao
y(k)
f - - - - - - - - r - - y(k)

y(k-1)

y(k-2)
I
I

x

~Y(k_N+1)

2585 drw 04

Figure 4. 8-Tap Transversal Structure

Z -1

bN
y(k-N)

x
2585 drw 03

Figure 3. Block Diagram of CanonicalliR Filter

In this application note, we will discuss various
implementations of both FIR and IIR filters using the lOT
16-bit OSP building block family: IOT7320, 16-bit 8-level
pipeline register; IOT721 0, 16x16-bit multiplier-accumulator;
IOT7216 16x16-bit multiplier and IOT7383, 16-bit ALU.

IMPLEMENTATIONS OF FIR FILTERS
There are many FIR filter structures. Two particular
structures are universally utilized: the transversal structure
and the lattice structure.
Transversal Structure
The transversal structure is a rather direct realization of the
equation (2-3) in terms of delays, multiplications, and additions.
As shown in Figure 4 for a 7th--order (8-tap) filter, the output

7.7

Figure 5 illustrates the implementation of the 8-tap
transversal structure using two IOT7320s and an IOT7210.
One IOT7320 is forthe storage of input data, and the other for
the storage of filter coefficients. The I OT721 0 is used to
perform multiplication and accumulation. Registers REG G1
and REG H2 of the IOT7320s are connected to X and Y input
registers of the IOT7210, respectively. 80th IOT7320s are
shifted every clock cycle. Thus, the input data and the
coefficients are loaded into the input registers of the IOT721 0
in the sequence shown in Figure 6. In the first clock cycle, a
new input word is loaded into REG A1 and the pipeline
registers A1-G1 shift down. In the next seven clock cycles, the
output of REG G1 is connected to the input of REG Al, so that
the pipeline registers Al-Gl shift as a ring every clock cycle.
Similarly, the output of REG H2 is connected to the input of
REG A2. A new output is unloaded every eight clock cycles.
A sequence controller generates the clock and the control
signals SEL and ACC. The filter coefficients are preloaded
into the pipeline registers A2-H2. Generally, for an N-tap
transversal structure, a filter cycle has N clock cycles.
Therefore, a filter cycle time is NStMA, where tMA = 25ns is the
multiply-accumulate time of IOT7210.

2

I

IMPLEMENTATION OF DIGITAL FILTERS USING 1DT7320,
IDT7210,1DT7216, AND IDT7383

APPLICATION NOTE AN-32

INPUT

Jl(k)

IDT7320

CLOCK

16
CLOCK
IDT721 0
ACC

SEQUENCE
CONTROLLER

SEL

ACC

OUTPUT
y(k)

2585 drw 05

Figure 5. Implementation of the Transversal Structure Using IDT7320s and IDT7210

7.7

3

IMPLEMENTATION OF DIGITAL FILTERS USING IDT7320,
IDT7210, 1DT7216, AND IDT7383

APPLICATION NOTE AN-32

tMA= 25ns

CLOCK

IDT7320
A1-G1

IDT7320
A2-H2

IDT7210

X. Y

IDT721 0

P

1+-----------

ONE FIR FILTER CYCLE (200ns)

----------~
2585 drw 06

Figure 6. Operation Sequence of IDT7320s and IDT7210 for the Transversal Structure

II

7.7

4

IMPLEMENTATION OF DIGITAL FILTERS USING 1DT7320,
1DT7210, 1DT7216, AND 1DT7383

APPLICATION NOTE AN-32

Lattice Structure

also be represented within a multiplicative constant by the
lattice structure. The origin and utility of the structure is that
it has several advantages overthe transversal structure in the
field of adaptive filtering.

The lattice structure of an Nth-order FIR filter shown in
Figure 7 for n = 8. The lattice structure is equivalent to the
transversal structure, in the sense that any transfer function
which can be represented by the transversal structure can
1st STAGE

8th STAGE

2nd STAGE
ef1

(k)

ef2

(k)
-

eb1(k)

ef8
- - - -

- -

- -

(k)

=y(k)

--i------,---~

eb2(k)

e b8 (k)
2585 drw 07

Figure 7. Block Diagram of the Lattice Structure

From Figure 7, we can see that an Nth-order lattice structure consists of N stages, each having two inputs and two
outputs. The outputs (efm(k), k = 0,1,2, .... } and (ebm(k), k =
0, 1, 2, .... } of the mth (1 mN) stage are called mth-order
forward and backward prediction errors, respectively, which
are related to the inputs of the stage (the outputs of the
previous stage) as follows:
efm(k) = ef(m-1)(k) - km-1 eb(m-1)(k-1)
ebm(k) = eb(m-1)(k-1) - km-1 ef(m-1)(k)

(3-1a)
(3-1b)

where the input of the first stage is
eiO(k) = ebo(k) = Jl(k)

(3-1c)

Equation (3-1) shows that we need to store (ebo(k-1),
eb1(k-1), .... ,eb(N-1)(k-1)}, the backward prediction errors at
time k-1, for calculating the outputs of all stages at time k:
(eb1(k), ef1(k), eb2(k), ef2(k), .... ,ebN(k), efN(k)}. An implementation of the 8-stage lattice structure is given in Figure 8
using IOT7320s, 7216s, and 7383s. Two IOT7320s store the
previous outputs ebo(k-1), eb1(k-1), .... , eb7(k-1) and the
coefficients ko, k1, .... , k7. The multiplications of
km-1 eb(m-1)(k-1) and km-1 ef(m-1)(k)
are performed by two IOT7216s. Two IOT7383s execute the
subtractions
ef(m-1 )(k) - km-1 eb(m-1 )(k-1 ) and eb(m-1 )(k-1) - km-1 ef(m-1 )(k).
The sequence of the operations is shown in Figure 9. A
filter cycle consists of 8 clock cycles. In the first clock cycle,

7.7

ebo(k-1) = Jl(k-1) stored in REG H1 is loaded into registers X1
and R1; ko stored in REG H2 is loaded into registers Y1 and
Y2; and the new input Jl(k) = eiO(k) is loaded into registers X2
and R2. The new input Jl(k) = ebo(k) is also loaded into REG
H1. After a time delay of tMUC = 30ns, the results of multiplication appear at the output pins of the IOT7216s which are
directly connected to the input of the ALU of the IOT7383s.
Then, after another time delay of tALU = 25ns, we obtain the
outputs of the first stage, eb1(k) and ef1(k), at the output pins
of the IOT7383s. In the second clock cycle, eb1(k-1) stored
in REG G1, k1 stored in REG G2, and ef1(k) appeared at the
output port of the IOT7383 are loaded into corresponding input
registersof the IOT7216s and 7383s. Atthe same time, eb1 (k)
is loaded into REG G1. After a time delay of tMUC + tALU =
55ns, we obtain eb2(k) and ef2(k), at the output pins of the
IOT7383s, and so on. Finally, in the eighth cycle, we obtain
eb8(k) and y(k) = ef8(k). It should be noted that in each clock
cycle, the IOT7216s first perform the multiplication, then the
IOT7383s complete the subtraction. Therefore, the time of a
clock cycle is tc = tMUC + tALU = 55ns. For an Nth-order lattice
FIR filter, the filter cycle time is 55 x N nanoseconds (440ns for
N = 8).
The signals 10-3 control to which register of the IOT7320 a
new backward prediction error will be written. The signals
SELo-2 select one of the eight registers of the IOT7320s to be
read from the output port. A sequence controller is needed to
generate the clock and the control signals 10-3 and SELo-3.
The filter coefficients ko-k7 are preloaded into the registers
A2-H2.

IMPLEMENTATION OF DIGITAL FILTERS USING 1DT7320,
1DT721 0, 1DT7216, AND 1DT7383

APPLICATION NOTE AN-32

~(k)

t

-4

16

MUX

SEL3

~
IDT7320

4

10-3~

~

REGAl

~

REGBl

I
eb6(k-1) I
eb7(k-1)

~ REGCl ebs(k-1)

I

4

~ REGDl eb4 (k-1)

CLOCK

~

REGE1

eb3(k-1)

~

REGF1

eb2(k-1)

EL

REGH1

0-

2

3

~ REGG1 eb1 (k-1)

~

4

IDT7320

CLOCK

ebo(k-1)

~

REGA2

k7

~

REG B2

k6

~ REGC2

ks

t>

REGD2

k4

~

REG E2

k3

t>

REG F2

k2

~ REGG2

k1

t>

ko

REG H2

}16

CLOCK
SEQUENCE
CONTROLLER

10-3
SEL0-3

~EL0-2

3

~SEL3

16

I
IDT7216

4

¥J~
I

MULTIPLIER
I
}16

~D3B3

IDT7383

I

-- ~
I

IDT7216

R2

ALU

I

I

f---ALU

~~

I

',16

'1'16

I

MULTIPLIER

I

I

i

16

II

e 11 (k), el2 (k), .... , el7 (k)

eb1(k), eb2(k), .... , eb7(k)

e 18 (k)

= y(k)
2585drw 08

Figure 8. Implementation of the Lattice Structure Using IOT7320s, IOT7216s and IOT7383s

7.7

6

IMPLEMENTATION OF DIGITAL FILTERS USING IDT7320,
1DT7210,1DT7216, AND IDT7383

APPLICATION NOTE AN-32

CLOCK

Y1, Y2

X1, R1

X2,R2

A1-H2
~-------------

ONE FILTER

CYCLE-------------~
2585 drw 09

Figure 9. Operation Sequence of 1DT7320s, IDT7216s and IDT7383s for the Lattice Structure

w(k)

IMPLEMENTATIONS OF ItR FILTERS
Since IIR filters have feedback elements, architecture for
implementing IIR filters are more complex than those for
filters. Moreover, roundoff errors of multiplication may accumulate and be amplified through the feedback loop so that the
roundoff noise at the filter output becomes a serious problem.
However, lOT's flexible and high-precision oSP product lines
provide unique solution for implementing IIR filters.
There are a variety of structures to implement IIR filters,
such as direct form structure, cascade structure, parallel
structure, lattice structure, ladderstructure, state-space structure. Among these, direct form, parallel and cascade structures are popular in many applications. In the following, we will
consider how to implement these filter structures using the
IDT7320, 7210, and 7383.

=

J.1(k) + b1W(k-1) + b2W(k-2) + ... + bNW(k-N) (4-3a)

and
y(k) = aow(k) + a1w(k-1) + a2w(k-2) + ... + aNw(k-N)(4-3b)
From (4-3), we get the direct form structure of the IIR filter
as shown in Figure 10. The direct form structure can be
implemented using a single MAC or two MACs.
ao

Direct Form Structure
The direct form structure is the simplest implementation of
IIR filters and requires the fewest multiplication, addition and
delay elements. This means that it can achieve higher speed
and needs less hardware than other structures. The disadvantage of the direct form structure is that it may have
multiplication roundoff noise. This can be overcome by using
the IDT high-precision 16-bit multiplier-accumulator (MAC),
where the whole 32-bit product is preserved and used in the
accumulator.
Let U(z) and Y(z) be the z-transforms of the input (J.1(k)} and
the output (y(k)}, respectively, then an IIR filter is described by

aN-1

bN-1

w(k-N+1)

Y(z) = H(z) U(z) = ao + a1 Z-1 + ... + aNz-N U(z) = A(z) U(z).
1 - b1 Z-1 - ... - bNZ-N
8(z)

(4-1)
Define W(z)

W(z)8(z)

=

_1_ U(z), we obtain
8(z)

= U(z) and Y(z) = A(z)W(z).

(4-2)

2585 drw 10

Figure 10. Block Diagram of the Direct Form Structure

Equation (4-2) can be written in the time domain as
7.7

7

1M PlEM ENTATION OF DIGITAL FilTERS USING IDT7320,
IDT7210, 1OT7216, AND IDT7383

APPLICATION NOTE AN-32

coefficients {b1, b2, ... , b7, 1} and the coefficients {ao, a1, ... , a6,
a7}. The new input ~(k) and the data {w(k)} stored in the
IDT7320 are sent to X input port of the IDT7210 through a
multiplexer, while the coefficients {ao, a1, ... , a6, a7} are sent
to Y input port of the IDT7210 through another multiplexer.

Implementation Using A Single MAC
Using a single MAC, for each new input ~(k), we first
calculate w(k) given by (4-3a), and then calculate y(k) by
(4-3b). The implementation of a 7th-order filter is shown in
Figure 11. Three IDT7320s are used to store {w(k)}, the
INPUT Jl(k)
',,16
"1'16
10T7320

10-3~

4

CLOCK

----
t>

REG C1 w(k-3)

I

!:?

REG 01 W(k-4)

r>

REG E1 w(k-5)

t>

REG F1 w(k-6)

t>

REG A1 w(k-1)

r>

REG 81

t>

r> REG G1
t>

REG H1

10T7320

10T7320
REG A2

b1

REG 82

b2

t>
t>

t>

REG C2

b3

I

t>

REG 02

I

t>
t>
t>

REG G2

b7

[:::>-

REG H2

1

I
w(k-7) I
rw(k-8) I

---

REG A3

ao

REG 83

a1

t>

REG C3

a2

b4

t>

REG 03

a3

REG E2

bs

t>

REG E3

a4

REG F2

b6

t>
t>

REG F3

as

REG G3

a6

t>

REG H3

a7

,--.
~

J

'0. 16

"1'16

~SEL'
',16

IOT721 0
ClK X, Y, P

~qJ
I

ACC_

MULTIPLIER
I
ACCUMULATOR

I
I

~

I

'['16

MUX
',16

SEl 0-2

"3"

SEl3

-

CLOCK

+4-

SEl0-4

~

10-3

-

SEQUENCE
CONTROllE R

II

ACC

, \,16

wlk~

FilTER OUTPUT
y(k)

2585 drw 11

Figure 11. Direct Implementation of IIR Filter Using a Single MAC

7.7

8

IMPLEMENTATION OF DIGITAL FILTERS USING 1OT7320,
1OT721 0, 1DT7216, AND 1OT7383

APPLICATION NOTE AN-32

As shown in Figure 12, each filter cycle consists of 16 clock
cycles. The firsteight clock cycles calculate w(k) while the last
eight clock cycles calculate y(k). In the first clock cycle, the
new input J.1(k) and the content of REG H2 are loaded into the
input registers of the IDT7210. Since 1 is stored in REG H2,
the result obtained in the output register of the IDT721 0 is J.1(k).
In the second clock cycle, the contents of REG G1 and REG
G2 are sent to the input registers of the IDT721 0, and so on.
Then, in the ninth clock cycle, w(k) is obtained in the output
register of the IDT721 O. In the tenth cycle, we load w(k) into
tMA =

REG A1 which will be used in the sixteenth cycle. Before w(k)
is loaded, in the eighth cycle, we shift down the pipeline
registers A1-H1, so that in the ninth cycle, the data stored in
H1 is not w(k-8) but w(k-7) which is multiplied by a7 stored in
REG H3. A new output y(k) is obtained in the first clock cycle
of the next filter cycle. It should be noted that in this
implementation, we obtain different data at the output ports of
the I DT7320s by using the output selection signal SELo-2, not
by shifting the pipeline registers every clock cycle.

25ns

CLOCK

IDT7320
A1-H1

HOLD

HOLD

IDT721 0
X,Y

IDT721 0
P
1 4 - - - - - - - - - - - - 0 N E IIR FILTER CYCLE

(400ns)------~----__.;
2585 drw 12

Figure 12. Sequence of Operations of 1OT7320s and 1OT721 0 for the Direct Form Implementation Using a Single MAC

7.7

9

IMPLEMENTATION OF DIGITAL FILTERS USING IDT7320,
IDT7210, 1OT7216, AND IDT7383

APPLICATION NOTE AN-32

Implementation Using Two MACs

A filter cycle has 8 clock cycles as shown in Figure 14. In the
first cycle, Jl(k+ 1) is loaded into register X, and multiplied by
the content of REG H2 which· is one, so that the result in the
output register Pl is still Jl(k+ 1). In the next seven cycles,
w(k-6), w(k-5), ... , w(k) are loaded into register Xl through the
multiplexer and multiplied by b7, bs, ... , bl, respectively. In the
eighth cycle, we shift down the pipeline registers Al-Hl to
prepare for the next filter cycle. Then, in the first clock cycle
of the next filter cycle, we obtain w(k+ 1) in the output register
Pl which is loaded into REG Al in the second clock cycle.
When one IDT7210 calculates w(k+1), another IDT7210
calculates y(k) and an output is unloaded from register P2
every 8 clock cycles.

In the implementation mentioned above, we use a single
MAC to calculate w(k) and y(k) alternately. If we use two
MACs, one MAC for calculating y(k) given by
y(k) = aow(k)+alw(k-1)+a2W(k-2)+ ... +aNw(k-N)

(4-4a)

and another MAC for simultaneously calculating w(k+ 1) given
by
w(k+ 1) = Jl(k+ 1)+blW(k}+b2W(k-1 }+ ... +bNW(k-N+ 1) (4-4b)
then the processing speed can be doubled. The implementation
of a 7th-order filter using two IDT721 Os is shown in Figure 13.
INPUT Il(k}
'r'--16
'1'-16
10T7320
~ REGAl

10T7320

w(k}

I

~ REG 81 w(k-1)
I

~ REG Cl w(k-2)

IDT7320

~

REGA2

bl

~

REG A3

ao

~

REG 82

b2

~

REG 83

al

~ REG C2

b3

~ REG C3

a2

~ REG 02

b4

~ REG 03

a3

~

REG E2

bs

~

REG E3

a4

t>

REG F2

b6

t>

REGF3

as

~ REGG2

b7

~ REG G3

a6

~ REG H2

1

~ REG H3

a7

I
10-3~

4

~ REG 01 w(k-3)
I

~ REG El w(k-4)

CLOCK
-~

t>

I

REG Fl w(k-5)
I

,.-t

~ REGGl w(k-6}

t>

I--

I

REG Hl w(k-7}

~

I--

I

SEL3~
',,16

'r'--16

'1'-16

IOT7210

I
ACC-

I

CLK X, Y, P

ACCUMULATOR

I

ACC

$
w(k+1)

MULTIPLIER

1
ACCUMULATOR

-

~

~~

I

MULTIPLIER
I

'1'-16

10T7210

~~I

~

CLK X, Y, P

J

3~

'~16

',,16

'r'--16

,SEL 0-2

J

~

CLOCK
10-3
SE~UENCE

CONTROLLE R
ACC
SELo-3

$

~16

~16

FILTER OUTPUT y(k)
2585 drw 13

Figure 13. Direct Form Implementation of IIR Filter Using Two MACs

7.7

10

•

IMPLEMENTATION OF DIGITAL FILTERS USING IDT7320,
IDT7210, IDT7216, AND IDT7363
tMA=

APPLICATION NOTE AN-32

25ns

CLOCK

IDT721 0
Xl,Yl

ll(k+1)+Xl
H2--t>-Yl ' - - - - - - '
......................

IDT721 0
Pl

X1Yl +
Pl--t>-Pl

' - - - - - - - I ..................... .

X1Yl +
Pl--t>-Pl

...-----,. ......................
IDT721 0
X2, Y2

Hl--t>-X2
H3--t>-Y2
......................L--_ _--J.

IDT721 0
P2

X2Y2 +
P2--t>-P2

.1.-_ _----1 ..................... .

IDT721 0
Xl-Yl

HOLD

X2Y2 +
P2--t>-P2

SHIFT
HOLD
Al-Hl !--_ _--J ......................."

' - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----I. ......................

I + - - - - - - - - - O N E IIR FILTER CYCLE (200ns)---------+t
2585 drw 14

Figure 14. Sequence of Operations of 1DT7320s and 1DT721 0 for the Direct Form Implementation Using Two MACs

Whether using a single MAG or two MAGs, the signals 10-3
control whether or not the pipeline registers shift or hold and
to which register of the IDT7320 a new result w(k) will be
written. On the other hand, the signals SELo-2 select one of
the eight registers of the IDT7320s to be read from the output
port. A sequence controller generates the clock and the
control signals. The filter coefficients are preloaded into
IDT7320s as in the FIR filter case.

Parallel Structure
The parallel structure has the advantage of less multiplication
roundoff noise and coefficient quantization sensitivity than the
direct form structure. However, the parallel structure uses
more hardware. The basic principle of the parallel structure is
that an Nth-order rational transfer function
H (z) =

ao + al Z-l + ... + aNz- N
1 + bl z-l + ... + bNZ- N

first-order filter or a second-order filter
H i (z) = _a_o_+_a_l_z-_1_+_a_2_z_-2_
1 + bl z-l+ b2 z-2

(4-8)

which can be implemented by the direct form structure
mentioned before. For example, a fourth-order filter can be
implemented with two parallel sections, each being a secondorder filter, as shown in Figure 16. In this particular
implementation, each section uses two MAGs. The outputs of
two sections are added by the IDT7383 to obtain the filter
output {y(k)}.
INPUT DATA
{J.l.(k)}

(4-5)

can be expanded to partial fraction as follow
H(z)

= H1(Z) + ... + HM(Z)

(4-6)

The expansion suggests that the filtercould be implemented
in a parallel structure shown in Figure 15. To minimize the
roundoff noise and coefficient sensitivity, Hi(Z) is usually a
Hi (z) =

ao + alZ1 + bl Z-l

l

FILTER OUTPUT
{y(k)}
2585 drw 15

(4-7)

Figure 15. Parallel Structure of IIR Fillers

7.7

11

IMPLEMENTATION OF DIGITAL FILTERS USING 1017320,
IOT7210, 1017216, AND 1017383

APPLICATION NOTE AN-32

INPUT
~(k)

1
~

~

IOT7320

IOT7320

IOT7320

IOT7320

I

10T7320

I

~

¥
lOT 7210

IOT7320

lOT 7210

lOT 7210

I

IOT7210

I
SECOND·ORDER SECTION

SECOND·ORDER SECTION

~

I

~

IOT7383

~

I

y(k)
2585 drw 16

Figure 16. Parallel Implementation of a Fourth-Order Filter Using Two Second-Order Sections

Cascade Structure
Like the parallel structure, the cascade structure has the
advantage of less multiplication roundoff noise and coefficient
quantization sensitivity and the disadvantage of more hardware
than the direct form structure. The basic principle of the
cascade structure is to decompose an Nth-order rational
transfer function given by (4-5) into first-order or secondorder sections as follows:

structure. Forexample, a fourth-orderfiltercan be implemented
with two cascade sections, each being a second-order filter,
as shown in Figure 18. The output of the first section is the
input of the second section.
INPUT

FILTER

OATA·~--·~ ~OUTPUT
{~(k)}~

~{y(k)}

2585 drw 17

H(z) = H1(Z)S .... SHM(Z)

Figure 17. Cascade Structure of IIR Fillers

(4-9)

where Hi(Z) is given by (4-7) or (4-:-8). From the decomposition,
the filter of (4-5) can be implemented by the direct form

7.7

12

II

IMPLEMENTATION OF DIGITAL FILTERS USING 1OT7320
1OT121 0, 1OT7216, AND IDT7383
'

APPLICATION NOTE AN-32

INPUT
~(k)

I
THE FIRST SECTION

IOT7320

IOT7320

THE SECOND SECTION

IOT7320

I0T7320

I

lOT 7210

I0T7320

IOT7320

I

lOT 7210

lOT 7210

I

lOT 7210

I

SECOND·ORDER SECTION

SECOND·ORDER SECTION

t

y(k)
2585 drw 18

Figure 18. Cascade Implementation of a Fourth-Order Filter Using Two Second-Order Sections

CONCLUSIONS
In this application note, we have discussed the basic
methods to implement a variety of structures of both FIR and
IIR filters using lOT DSP building block family: pipeline registers,
MAGs, multipliers, and ALUs. Which structure and
implementation should be selected in a particular application
is decided by many factors such as the available filter design
tools, cost, speed, etc.. In many applications, the FIR
transversal structures is used because of the simplicity of filter
design and implementation. The FIR lattice structure is
employed in the application where the filter coefficients have
to be adaptively changed and fast convergency of the
coefficients is required. In applications requiring high speed
and compact hardware, IIR filters are usually preferred.
Different IIR filter structures may have completely different
finite wordlength effects (roundoff error, coefficient error and
limit cycles). The direct form structure is the simplest one and
uses the least hardware. However, if the filter order is large
and the bandwidth of the filter is very narrow, then the direct

7.7

form structure may have severe roundoff noise and Iimitcycles so that the actual input-output characteristic of the filter
dramatically deviates from the ideal one. In this situation,
parallel structure or cascade structure should be utilized.
The building block approach discussed in this application
note can achieve 10 times the performance of some simple
FIR and IIR filter structures. Table 1 gives a comparison
between the building block approach using lOT's DSP building
blocks and the single chip DSP approach using the latest
Texas Instruments TMS320G25-50, a single chip digital
signal processor with an instruction cycle time of 80ns.
lOT's extensive and flexible product lines provide various
possibilities to implement different filter structures. In the FIR
filter implementations and II R filter direct form implementations
shown in this application note, we have using at most two
MAGs, multipliers and ALUs. The number of the clock cycles
in a filter cycle is proportional to the filterorder. If more MAGs,
multipliers and ALUs are used, a filter cycle can contain only
a single clock cycle to achieve the highest speed.

13

G®
Integrated Device Technology, Inc.

APPLICATION
NOTE
AN-35

ADDRESS GENERATOR FOR
A MATRIX MANIPULATION
ENGINE
By Yuping Chung

INTRODUCTION

addressing, and indexed addressing. Theseflexible accessing
modes are especially useful in systems with structured data,
such as matrices. The following sections discuss a high speed
matrix manipulation engine incorporates its own ALU-based
addressing generators.
Digital signal processing, array processing and scientific
computing systems require matrix operations. An example
shown in Figure 1 is the matrix multiplication. Most often, the
data of each matrix are stored sequentially in a buffer. However,
the matrix operation requires accessing the memory both
sequentially and non-sequentially. We will examine the
memory organization of the matrix first and subsequently
examine the matrix manipulation engine.

An addressgeneratoris essential in every system requiring
access to both the programming code and data. In a
microprocessor-based system, the address generator is
already built-in on the microprocessor chip. Other high
performance systems use dedicated address generators to
achieve a high degree of parallelism. The address generator
must be fast and flexible to cope with the system's different
addressing requirements, such as random addressing and
structured data addressing. A loadable up/down counter can
be used as an address generator, but it is limited to access the
adjacent locations. A better solution is an ALU based address
generator which can access the address in several modes:
sequential accessing, interval accessing, segmented

a11 a12
a21 "-

[

·
··

• • •

b11

j
a1 ]

"-

··

x

"- """-

ai1

b12

b21 "-

b1k]
""- "-

·

[
aij

•••

""-

bj1

j
Cik = Iaij bjk
j

[all
a21

a12
a22

a"J
a23

X

··

• • •

C1k]

"-

"- "-

·

""-

CI1

Clk

i = 1.2 ....• i
j = 1. 2 ..... j
k = 1.2 ..... k

=1

[bll

bJk

[C11
C21 "- C12

b12

b13

b21

b22

b23

b24

b31

b32

b33

b34

b'J

(Cll

C21

C12

C13

C22

C23

C')
C24

C11= a11b11 + a12b12+ a13b13

II

2586drw 01

Figure 1. Matrix Multiplication and its Unit Operation

I

©1990 Inlegrated Device Technology. Inc.

7.8

4/90

1

APPLICATION NOTE AN-3S

ADDRESS GENERATOR FOR A MATRIX MANIPULATION ENGINE

illustrated in Figure 2. In applications such as spectrum
analysis, image processing, and graphics engine, the segment
size may be as large as several thousand words.

MATRIX MEMORY ORGANIZATION AND
ADDRESSING
Sequential Memory Organization
In most applications the entries each matrix are stored
linearly row by row in a dedicated memory segment, as

.----1 pointer A
- = 1 pointer A
~
1pointer A+1

~

i
a21 '

~

1

+ 0
+ 0

1pointer A+j-2 I + 0

i = 1,2, ... , i
j = 1,2, ... , j

+0
2586 drw 02

Figure 2. Sequential Memory Organization and Sequential Accessing for a Matrix

Interleaved Memory Organization

[Xl and [Yl. The entries of [Xl and [Yl are interleaved

Another type of memory organization is implemented by
interleaving matrices in the same memory segment (Figure 3).
This can be found in the time multiplexed data acquisition and
processing. The memory segment contains two sets of data

in the same segment of the memory and therefore
the entries of each matrix is accessed at an interval
of two.

Pointer X - - - - - - -........
Pointer Y

X11

~~~~s.{X1j

Y1j

:::

j [ ···

Xi1

,X:2

•••

K]====::::::::-___
Y11

Xi1

y12

j

•••

y21 "

"

,

,

[

··

·

yi1

"

Y1 ]

,

j

,
yij

2586 drw 03

Figure 3. Interleaved Memory Organization and Interval Accessing for Two Matrices

7.8

2

i

ADDRESS GENERATOR FOR A MATRIX MANIPULATION ENGINE

APPLICATION NOTE AN-35

Matrix Column Addressing
In the example of multiplication in Figure 1. the multiplier
matrix [B] is accessed by the column instead of the row.

Therefore. the address pointer increments at an interval of k.
the column size of the matrix. Figure 4 shows the memory
organization and accessing of the matrix [B].

pointer B
Current
Address
pointer B

Displacement

+ 0

1st ROW
j=1
(k Locations)

--

b12

bl1

"-

2nd ROW
j=2
pointer B+k

.

b21· ,

+ 0

""-

bj1

:J li

j = 1.2 ....• j
k= 1. 2 •.... k

+0
LAST ROW

2586 drw 04

Figure 4. Sequential Memory Organization and Interval Accessing for Matrix [8]

Address Generator
Different addressing schemes are required to access
different memory organizations. or different structured data

organizations. An ALU-based address generator is best
suited for this type of application since it can increment the
address based on a pointer and a displacement (Figure 5).

+

T

ADDRESS

CURRENT ADDR + k

(a)

(b)

II

2586 drw 05

Figure 5. ALU-based Address Generator for Matrix Column Addressing

MATRIX UNIT OPERATIONS
In a matrix multiplication (Figure 1) involving two matrices
[A] and [B]. each entry in the product matrix [C] is obtained by
summing the products which are obtained by multiplying the
entries in the first matrix [A] with the corresponding entries in
the second matrix [B].
The matrix multiplication process can be described as
C-Ianguage program where the loop in the line 6 and 7 fetches
two entries from the memory and stores the product entry back
into the memory. The unit operation line 7 consists of a
multiplication and an addition which can be performed in
hardware with a single chip multiplier-accumulator. such as
the IDT7210 16-bit MAC.

7.8

2
3
4
5
6
7
8
9
10

for (i = O. i < MaxRow_A •. i++)
{
for (k = O. k < MaxColumn_B. k++)
{
for (j = O. j < MaxColumn_A. j++)
Cik = Cik + aij x bjk

Max Row_A = number of row in matrix A.
MaxColumn_A = number of column in matrix A.
MaxColumn_B = number of column in matrix B.

3

ADDRESS GENERATOR FOR A MATRIX MANIPULATION ENGINE

APPLICATION NOTE AN-35

the pipeline registers (Figure 7).
The multiplication-and-addition is performed using a
multiplier-accumulator. The two input data pipeline registers
and output data pipeline register reduces the part count during
pipelined operation. It allows the system to do the multiplication
and addition while the result of the previous operation is stored
into memory.
The multi-bank memory allows the system to simultaneously
access two entries of matrices [A] and [B]. It also allows the
system to write the product entry into matrix [C] in the same
cycle. It requires one address generator for each bank of
memory to simultaneously access all three banks of memory.
The 1&-bit ALU-based address generator is capable of
accessing up to 64K locations.

PIPELINED MATRIX MANIPULATION ENGINE
To implement the matrix operation in hardware, three
functional blocks are required: the address generator, the
multiplier/accumulator (MAC), and the memory (Figure 6).
The IDT7383 or IDT7381 is used as the address generator.
An IDT7210 is used to implement the multiply-accumulate
operation. This implementation uses both pipeline registers
and a multi-bank memory to achieve the highest performance
using a high degree of parallelism. In the pipelined architecture,
four operations execute in parallel during a single cycle:
generating a read address, reading out data from memory,
loading two operands and multiplying and adding, and
generating write address and writing data to memory. These
four stages are easily identified by locating the clock input of

~ PIPELINE REG

I> PIPELINE REG I

ADDRESS
GENERATOR

ADDRESS
GENERATOR

2

3

I> PIPELINE REG I

t> PIPELINE REG

MEMORY
BANK

MEMORY
BANK

MEMORY
BANK

1

2

3

I~---------F---P-IP-E-L-IN-E-R-E-G-S----~-----l
~

~

I>

l>

X-REG

~..

~~
~

MULTIPLIERI
ACCUMULATOR
(MAC)

~

Y-REG

I

~~

~--------------.-------------~
I

~

t>

~

~

..

PIPELINE REG

i~
~~
~

~~

§

I
~

~-lI~;"""'_IDT7210~

2586 drw 06

Figure 6. Block Diagram of Pipelined Matrix Manipulation Engine

7.8

4

ADDRESS GENERATOR FOR A MATRIX MANIPULATION ENGINE

APPLICATION NOTE AN-35

PIPELINED STAGE, DATA PATH, AND CYCLE
TIME
The first pipeline stage, i.e. address calculation, consists of
the input pipeline registers and the ALU in the 10T7383/
IOT7381. The ALU calculates the address and sends the
results to the output pipeline register. The propagation delay
from the input clock to the valid result from the ALU is 25ns

(Figure 7).
The second pipeline stage, i.e. memory read, consists of
the output pipeline register of the IOT7383/7381 and two
banks of IOT6116 2K x 8 SRAMs. The address generator
provides the address to the memory. The data is subsequently
read from the memory. The propagation delay from the output
clock to the memory output data valid is 33ns (Figure 7).

ClK

STAGE 1
25ns
A 0
-q-

"'C')
c.o

W

f-

Q

STAGE 2
35ns

f-

()

u..
-q-

A

A

IOT6116
SRAMs

IOT6116
SRAMs

0

0

"'-

f-

Q

x
V
IOT7210 MAC

/

STAGE 3
25ns

STAGE 4
32ns

IOT6116
SRAMs
2586 drw 07

Figure 7. Propagation Delay of the 4-Stage Pipelined Matrix Manipulation

The third pipeline stage, i.e. multiply-accumulate, consists
of the input registers and multiplier-and-accumulator in the
IOT7210. Two operands are multiplied and added to the
content retained in the accumulator. The result, stored in the
accumulator, is ready to be clocked into the output register.
The propagation delay from the clock of the input register to
the valid output of the MAC is 25ns.
The fourth pipeline stage, i.e. memory write, consists of the
output pipeline register of the IOT721 0 and the third bank of
IOT6116 2K x 8 SRAM. An address generator simultaneously
provides the address for the memory write. The propagation
delay from the clock of the t.-utput registerofthe IOT721 0 to the

7.8

end of the memory write is 32ns.
The control section consists of the IOT6116 2K x 8 SRAM
and IOT74FCT374 Octal register. It is found that the
propagation delay is the combination of the output valid delay,
6.5ns, and the instruction setup time, 19ns. The total
propagation delay is 25.5ns.
Effectively, the cycle time of this engine is determined by
the memory read cycle which requires a 35ns cycle time. The
four-stage pipelined cycle time and timing diagram are shown
in Figure 8 and Figure 9. . For the corresponding control
signals, please refer to the lOT data book.

5

I

APPLICATION NOTE AN-35

ADDRESS GENERATOR FOR A MATRIX MANIPULATION ENGINE

Stage 1
ADDRESSING

Min. ClK to ClK IDT7383/81

25ns

ClK to F IDT7383/81
(FTAB = 0, FTF = 0)

11 ns

Stage 2
SRAM READ

Addrto Data IDT6116-12

12ns

Input Setup IDT721 0

12ns

Min. ClK to ClK IDT721 0

25ns

Stage 4

ClK to P IDT721 0

20ns

SRAMWRITE

Addr to Data IDT6116-12

12ns

ClK to Q IDT74FCT374

6.5ns

I Setup IDT7383/81
(FTAB = 0, FTF = 0)

19ns

25ns

C§)

Stage 3
25ns

MAC CYCLE

32ns

CONTROL
CYCLE

25.5ns

2586 drw 08

Figure 8. Minimal Cycle Time of Each Stage of Matrix Manipulation Engine

STAGE 1
STAGE 2
STAGE 3
STAGE 4
MULTIPLY
ADDRESS
READ RAM
ACCUMULATE
WRITE RAM
1 - 4 - - - 35ns --~~--- 35ns --~~--- 35ns ----1~--- 35ns --~
SYS ClK
AlU OUTPUT
OUTPUT F
SRAM 1,2
DATA
MAC'S OUT
PRODUCT
SRAM 3
DATA

DATAWR

4-STAGE PIPELINE MULTIPLY-ACCUMULATE

"--J
2586 drw 09

Figure 9. Pipelined Timing Diagram of Matrix Manipulation Engine

7.8

6

ADDRESS GENERATOR FOR A MATRIX MANIPULATION ENGINE

APPLICATION NOTE AN-35

SUMMARY
A high performance matrix manipulation engine can be
implemented by using the IOT7383/IOT7381 1&-bit ALU,
IOT7210 MAC. and IOT6116 2K x 8 SRAM. A cycle time of
35ns is achieved in the matrix unit operation engine by using
a 4-stage pipelined architecture. These four stages,
addressing, SRAM read, Multiply-Accumulate, and SRAM
write, are pipe lined together so that effectively one matrix unit
operation is processed every cycle. Both the IOT7383/
IOT7381 16-bit ALU and the IOT7210 16-bit MAC have on

chip inpuUoutput pipeline registers, which reduce board space
and chip count.
Highly structured data is 'easily accessed by using the
10T738317381 ALU-based address generator. The structured
data may be organized in several ways: segmented
organization, sequential organization, and interleaved
organization. The ALU-based address generator supplies
the sequential or non-sequential addresses based on the
base-pointer and displacement provided by the system.

II

7.8

7

(;)®
Integrated Device Technology, Inc.

HIGH-PERFORMANCE GRAPHICS
SYSTEM DESIGN USING THE
IDT75C458 PaletteDACTM

APPLICATION
NOTE
AN-37

By Tao Lin, Wing Leung and Frank Schapfel

INTRODUCTION
The IDT75C458 PaletteDACTM is a triple 8-bit video DAC
with on-chip dual-ported color palette memory. The
PaietteDAC is optimally designed for use in high performance
bit-mapped graphics display applications. The architecture
eliminates the ECl pixel interface by providing multiple
TTl-compatible pixel ports and by multiplexing the pixei data
on chip.
Video data rates of 165MHz enable color monitors of 1600
x 1280 pixel resolution to display up to 256 simultaneous
colors from a palette of 16.8 million colors using one
PaletteDAC. Using three IDT75C458s, the full spectrum of
16.8 million colors can be displayed, a required feature in true
color, photo realistic graphics display.
Synchronizing Three PaletteDACs
When synchronizing three PaletteDACs for true color
applications, an on-chip Phase-locked loop (Pll) fixes the
pipeline delay from the pixel input ports to the triple DAC. The
Pll sets the pipeline delay to nine clock cycles, and insures
synchronization of the three PaletteDACs with only one clock
signal. The performance of true color systems is enhanced
because the time skew from the digital components of the
pixel data path.
Other implementations of the PaletteDAC, such as the
Brooktree® 81458, have a variable pipeline delay of six to ten
clock cycles, which must be set du ring the power up sequence.
To set the pipeline delay of the Bt458, a complicated power up
and timing sequence is necessary by starting, stopping and
re-starting the CLOCK and CLOCK signals. When using
multiple Bt458s, a hardware reset of the blink counter circuitry
is not possible when setting the pipeline delay to 8 clock
cycles. Therefore, the blink counters must be synchronized
using software control.
The PaletteDAC's on-chip Pll automatically sets the
pipeline delay to 9 clock cycles, thereby eliminating the
complicated power up sequence required by the Bt458. We
will discuss the mechanism to fix the pipeline delay and the
role of the Pll.
On-Chip Phase-locked loop
The next generation, true color graphics display will use a
1600 x 1280 pixel resolution screen and requires three
PaletteDACs with the pixel clock operating at 165MHz to
display the full spectrum of 16.8 million colors. Typically, slow
speed video RAMs (VRAM) built using dynamic RAM
technology store the pixel information in the frame buffer. Five

pixel ports and internal multiplexing on the PaietteDAC enable
a TTL-compatible interface to the frame buffer while
maintaining a 165MHz pixel clock rate.
On the rising edge of load Clock input (lD) color data for
four or five consecutive pixels is latched into the PaletteDAC.
Therefore, the lD signal is four to five times slower than the
pixel clock (ClK), and is typically derived by externally dividing
the pixel clock by 4 or 5. Inevitably, the lD signal is phase
shifted with respect to ClK because of the propagation delay
of generating lD.

External CLOCK

External LD

IDT75C458
Phase
Locked
Loop

Internal CLOCK

Internal LD
2592 drw 01

Figure 1. Phase Locked Loop on the PaietteDAC

The Pll on the IDT75C458 synchronizes the lD and ClK
signals. As shown in Figure 1, the Pll receives the external
lD and ClK signals and generates internal lD and ClK
signals. The phases of the external lD and external ClK may
differ, (Figure 2). The Pll corrects the phase shift by forcing
the internal lD and internal ClK to have the same phase. The
Pll approach guarantees that the internal lD follows the
external lD by less than one pixel clock cycle. Alternatively,
the internal counter approach implemented in the Bt458
allows the internal lD to follow the external lD by between one
and four clock cycles.
External CLOCK

External LD

Internal CLOCK

Internal LD
2592 drw 02

Figure 2. Phase Relationship of the Internal and External Load
Clock and Clock

PaletteDAC is • trademark 01 Integrated Device Technology, Inc.
Brooktree is • registered trademark of Brooktree Corporation
(01990 Integrated Device Technology. Inc.

7.9

4/90

1

HIGH-PERFORMANCE GRAPHICS SYSTEM DESIGN USING THE IDT75C458 PaletteDACTM

Fixing the Pipeline Delay
Figure 3 illustrates the data path inside the PaietteDAC for
the pixel select input data, overlay select input data, SYNC
and BLANK signals. All data operations are pipe lined to
maximize throughput performance. The rising edge of external
LD latches pixel data to the Master Latch while the rising edge

APPLICATION NOTE AN-37

of the internal LD latches pixel data to the Slave Latch. All
subsequent internal data operations are controlled by the
internal pixel clock. Since the on~hip PLL forces the internal
LD signal to follow the external LD by less than one clock
cycle, the pipeline delay from the pixel input port to the triple
DAC is fixed at 9 clock cycles.

Internal CLOCK

External CLOCK
External LD

M

40
P{A-E}

OL{A-E}
SYNC

A
S
T
E
R

S
L
A

L
A
T
C
H

L
A
T
C
H

lOR

V

B
L

E

I
N
K

R
E
A

COLOR
PALETIE

D

lOB
lOG

BLANK
DELAY REGISTERS
2592 drw 03

Figure 3. Pixel Data Path of the IDT75C458

25MHz Graphics Engine Interface
Today's high-speed graphics workstations employ graphics
engines operating at clock frequencies in excess of 10MHz.
The I DT75C458's microprocessor interface can handle a data
rate of up to 25MBytes per second. The enhanced interface
to the color palette allows today's 25MHz graphics engines or
RISC microprocessors, such as the IDT7953000, the ability to
change the colors in the PaletteDAC's RAM thereby increasing
the throughput of the controlling microprocessor. Since the
IDT75C458 is intended for high-speed operation, there is less
control timing error tolerance compared to that of a slower
part. To maintain proper operation, the control timing
parameters (Le., zero write data hold time) must not be
exceeded at full operational speed and throughout the
operational temperature range.
High-Speed Analog Output
To achieve a 165MHz pixel conversion rate, the analog
outputs are designed to operate with a 1.5ns rise/fall time at
a full-scale swing of 0 to 0.7V. The full-scale output settles
within 6ns (including the rise and fall time) with proper
termination and an output load to 17pF. The fast settling time
is the result of the low output capacitance (7-8pF) of the
digital-to-analog converters and the minimal package
inductance of the 84-pin grid array and plastic leaded chip
carrier (PLCC).

7.9

High Performance Design Considerations
When designing high performance digital and analog
systems using the IDT75C458, special attention should be
paid to the PC board layout, impedance matching and
decoupling considerations, as these are crucial to minimizing
noise and obtaining stable performance.
Analog Output Connection and Impedance Matching
To fully utilize the superior performance capabilities of the
IDT75C458, special attention must be paid to the handling of
the analog output signals. To minimize the transmission line
effects, accurate termination resistance, cable assembly and
well-matched characteristic impedance in the operating
frequency range are necessary. The loading impedance to
the analog outputs resulting from the PC board metal trace,
cable assembly, and termination must not be inductive.
Inductive loading impedance introduces overshoots and ringing
on the analog output waveforms, which in turn in increase the
settling time and smear images on the CRT screen. To avoid
inductive loading impedance, the PC board metal traces
connecting the analog outputs of the IDT75C458 to the BNC
must be as short as possible, as illustrated in Figure 4.
For most applications, the inductive effect can be cancelled
out (at the expense of frequency bandwidth) by adding 10 to
20pF capacitor at the analog outputs as close to the package
pins as possible. Each analog output should have a 75 ohm

2

7

HIGH-PERFORMANCE GRAPHICS SYSTEM DESIGN USING THE 1DT75C458 PaletteDACTId

load resistor connected to ground to achieve maximum
performance. To minimize transmission line effect reflections,
the resistors should have the shortest leads and be placed as
close to the IDT75C458 as possible.
Red

Green

Blue

For/=
Impedance
Matching r - - - ' - - - - - ' - - - - - , - - - - ' - - - - ,
lOR
lOG
lOB

decoupled to the analog VAA. To minimize noise on the board,
the analog groundplane area should surround all peripheral
circuitry and connections forthe IDT75C458: the decoupling
capacitors, the external voltage reference circuitry, the analog
output traces and output amplifiers and all digital input signals
leading to the IDT75C458.
Analog Power Plane and Supply Decoupling
Most of the circuits on the chip are synchronized to the pixel
clock and switch at the clock edges. Consequently, large
voltage spikes are generated on the power supply lines.
Without good power supply decoupling these voltage spikes
can be decoupled to the analog outputs and result in a snowy
screen. Therefore, a separate analog power plane should be
furnished forthe I DT75C458 and its associated analog circu itry.
Figure 5 illustrates how the analog power plane should be
connected to the digital PC board power plane (Vee) at a
single point through a ferrite bead located as close as possible
to the IDT75C458. The IDT75C458 has six analog ground
pins separated into three groups, with each group decoupled
with a 0.1 JlF ceramic capacitor in parallel with a 0.1 JlF chip
capacitor. These capacitors should be installed close to the
PaietteDAC using the shortest leads possible.

Capacitors
To Cancel
Inductive
Effects

750hm

APPLICATION NOTE AN-37

Very Short
Trace

IDT75C458
2592 drw 04

Figure 4. Output Connection and Impedance Matching

Ground Plane
Although the ground pins on the IDT75C458 are called
analog ground (AGND), they should be connected to the
digital groundplane of the PC board through ferrite beads and

VAA

t

(PGA: Pin A7 & A9)
(PLCC: Pin 23, 27)

VAA

0.1~F T

y

y

VAA

IDT75C458

O.01IlF

Chock
y

(PGA: Pin L7 & M7)
(PLCC: Pin 63, 64)

fO. 1IlF

VAA
(PGA: Pin C11 & C12)
(PLCC: Pin 35, 37)

fO. 1IlF

PC Board

y

Vee

fO

r

11l F

J-O.O

2592 drw 05

Figure 5. Analog Power Plane and Decoupling of Each Group of Analog Pins

Forthe lowest levels of cross talk and noise pickup between
the PaletteDAC's analog circuitry and the digital traces on the
printed circuit board, power for the digital logic should come
from the digital power supply plane.

CONCLUSION
The PaietteDAC provides an easy upgrade of existing high
performance graphics display boards: With the 165MHz
version, a 1600 x 1280 pixel screen resolution can be achieved

7.9

with minimal design effort. Taking advantage of the on-chip
phase locked loop, three PaletteDACs display true color
images using a palette 6f 16.8 million colors, without
complicated external synchronization circuitry. The 25MHz
microprocessor interface allows today's high performance
graphics engines and R ISC microprocessors to change palette
colors without wait states. The PaietteDAC clearly supplies
the best upgrade path for t,?day's graphics display boards.

3

(;)®
Integrated Device Technology, Inc.

USING THE IDT75C457s
PaletteDACTM IN TRUE-COLOR
AND MONOCHROME
GRAPHICS APPLICATIONS

APPLICATION
NOTE
AN-63

by Tao Lin

The IDT75C457 is the newest member in the IDT
PaletteDACTM family which targets high-performance graphics
systems. The IDT75C457 is primarily used in high-resolution
true-color applications, although it can also be applied to
high-resolution monochrome graphics systems.
Besides having all the features of the industry standard
Bt457, the IDT75C457 is unique in that the device includes
an on-Chip Phase-Locked Loop (PLL) and consumes less
power. The block diagram of the IDT75C457 is shown in
Figure 1. The PLL automatically synchronizes the load-data
clock, LD, and the high-frequency pixel clock, CLOCK. This
feature results in the following major advantages of the
IDT75C457 over the Bt457: (1) a reset operation is not
required. Therefore, an external clock chip with a reset feature
such as the Bt439, is not necessary, (2) the internal pipeline
delay is automatically fixed to 9 clock cycles and (3) in truecolor graphics systems where three IDT75C457s are used
for red, .green and blue channels, respectively, the internal
pixel clocks of all the three chips are synchronized to the
same external reference clock, LD. The synchronization
minimizes the internal pixel clock skew from chip to chip.
Consequently, the video output skew among the three
channels is usually within sub-pixel resolution even without
an external PLL.
The low power consumption of the device results from the
lower static and dynamic switching current of the chip. Thus,
the IDT75C457 generates less digital noise than the industry
standard part. As a result, less noise is coupled to the analog
output and the display quality is improved. To further decouple

the internal analog circuitry from outside noise and improve
the stability of the analog video output, it is recommended
that a separate ground be provided for the external voltage
reference circuitry.
A typical configuration using the IDT75C457 in a
monochrome graphics system is shown in Figure 2. In truecolor' applications, three IDT75C457s are needed and a
typical configuration is shown in Figure 3. Note that a separate
ground is provided for the external voltage reference circuitry.
This ground is connected to the PC board ground plane at a
single point through a ferrite bead. Moreover, for maximum
and stable performance, designers using the IDT75C457
should pay close attention to high-speed design issues such
as PC board layout, impedance matching and decoupling.
They should follow the same guidance as given in
Application Note AN-37(1) for the IDT75C458.
Since the IDT75C457 does not need an external clock
reset operation to synchronize the internal clock signals, the
clock generator can be simply built using a crystal oscillator
and a few ECL chips. Figure 4 shows a typical clock circuit
using three t=CL chips for either 4:1 multiplexing or 5:1
multiplexing. Figure 5 shows another typical clock circuit
using two ECL chips for 5:1 multiplexing.
In conclusion, the IDT75C457 simplifies the design of
high-resolution graphics systems and, with the advantages
of the internal PLL and low power dissipation, offers the best
upgrade path towards tomorrow's photo-realistic graphics
display systems.

I
NOTE:

1. Tao Lin, Wing Leung and Frank Schapfel, "High-performance Graphics System Design Using the IDT75C458 PaletteOACTM", lOT
Application Note AN-37.

PalietteDAC is a trademarks of Integrated Device Technology. Inc.
©1990 Integrated Device Technology, Inc.

7.10

6190

1

USING THE IDT5C457s PalietteDACT" IN TRUE-COLOR
AND MONOCHROME GRAPHICS APPLICATIONS

CLK

APPLICATION NOTE AN-53

CLK

VREF

FSAOJ

COMP

MUX
CONTROL

LD

PO-P7
{A-E}

R
E
A
D

B
L

I

8

Color
Look-up
Table

N
K
lOUT

M
A
S
K

OLO-OL1
{A-E}

M
A
S
K

4x8
PLL

DELAYED
SYNC & BLANK

2

8
READ REG
BLINK REG
AD DR REG
TEST/CONT
COMM REG

8

8
6
CO

C1

RNi

IT

DO-07

VAA

7.10

AGND

2

l>C
ZC/l

Oz

::Cl
O-t

Z:J:

om
0-

:J:o

Ferrite Bead

VAA Plane

PC Board
Power Plane

:D-t

oU'l

::~

mU'l
....,

Cl'"

0.1flF

~
Ferrite Bead
VREF

VAA
AGND
(PGA:C11,C12) (PGA:B11, B12)
(PLCC: 35, 37) (PLCC: 34, 36)

(1rD

C/l0

l>l>

~~
~z

l>-t
-t:D

,..

-c
Om
z,
C/l0

o
o

r-

FS ADJUST

----f----,

1-1

VAA
(PGA: A7, A9)
(PLCC: 23, 27)

AGND (PGA: M6)
(PLCC: 65)

o

:0

The separate
ground for the
voltage reference

CaMP

0.01flF

~

:J:!!

0.1flF

VAA (PGA: L7, M7)
(PLCC: 63, 64)

0.1 flF

lee

:D'l:J
l>Dl
'l:J=

c:

C')

C\J
LO

CLOCK
CLOCK
GENERATOR

AG ND 1-1-tet-------l
(PGA: A6, B6)
(PLCC: 21, 22)
BNC

IOTI5C457

CLOCK
LD

FRAME
BUFFER

PO-P7
{A-E}

'\:

lOUT,

••

I OLO-OL1

To
MonoChrome
Monitor

{A-E}
SYNC
GENERATOR

SYNC
BLANK

CO

C1

RIW

CE

DO-D7

PLL

8
MPU INTERFACE
Figure 2. A Typical Configuration for Monochrome Applications

l>

'l:J
'l:J

r(1

l>
-t

o
Z
Z

o
-t

m

Co>

l>
Z

a,
Co>

II

USING THE IDT5C457s PalietteDACT" IN TRUE-COLOR
AND MONOCHROME GRAPHICS APPLICATIONS

APPLICATION NOTE AN-53

Ferrile Bead PC Board
~
Power Plane

..

VAA Plane

:; 1
VAA
(PGA:C11,C12)
(PLCC: 35, 37)

AGND
(PGA:B11, B12)
(PLCC: 34, 36)

VREF

0.111~~ VAA (PGA: L7, M7) (PLCC: 63,64)
0.01111"

FS

~F'

r--:--:----J---4.....---..:5:~~~

VAA
(PGA: A7, A9)
(PLCC: 23, 27)
AGND
(PGA: A6, B6)
(PLCC: 21, 22)

AGND (PGA: M6) (PLCC: 65)

CLOCK
I
C_L_OC_K
GENERATORIJ--. .+ - - - - - - f CLOCK

IDT75C457

L-______r-~tr----~:1ill

FRAME 1J---4++---~
.......
,,-I PO-P7{A-E}
r-----1
,40
BUFFER I
,
L---I1----+++--~10:?o't"'"""'-I OLO-OU {A-E}
SYNC

A~~~:T

lOUT

)"'II1II

1-_.1'_1_1-....,

~

0.111F
;:~
p.0111F

il='

~~
"

BNC

\Ferrite BeadV
The separate
ground for the
voltage reference

> '"
.......
"

~

Red Channel

750

--IH~H-+------f -SY-NC-

L;G~E~N~E~RA~T~O~R~II~r_Hlr_----~B~~~N~K-~C~0-C~1~~Rm~-~C;~E~D~0~-~D7~--~PL~L~~
8
,

'MPU I'NTEtACt

:~
VAA
(PGA:C11,C12)
(PLCC: 35, 37)
0.111F ~t:;"

o 01 11fT'
It'

AGND
(pGA:B11, B12)
(PLCC: 34, 36)

CLOCK
CLOCK

IDT75C457

LD
::0

~I
uBUu,F, ,FLE_,R, J---I-IHI-Hf---.,.,lO~".---I

VREF
0.111F
CaMP 1--1'\\ 1.--.
FS ADJUST 1-. I'_I_f--.

VAA (PGA: L7, M7) (PLCC: 63,64)

ff\

~ ~ AGND (PGA: M6) (PLCC: 65)

I.----~

~

1

VAA
(PGA: A7, A9)
(PLCC: 23, 27)
AGND

-:~O.1I1F ~

(PGA: A6, B6)
(PLCC: 21, 22)

~7

PO-P7{A-E}

lOUT

,.~

~
0.0111 F

r- •

~

~~

BNC

~

OLO-OU {A-E}

7511

Green Channel

I·~~----~SYNC

~-111-----t!B~LA~N~K~~C~0~C~1-~R~m~c;~E~D~0~-D~7~-~P~L~L~~

, I I I

~8

MPU INTERFACE

VAA
AGND
(PGA:C11,C12) (PGA:B11, B12)
(PLCC: 35, 37) (PLCC: 34, 36)

..I:":t"

0.1I1 F
O.01I1F'1' '

VREF
0.111F
CaMP
FS ADJUST

VAA (PGA: L7, M7) (PLCC: 63,64)

r-

~ ~ AGND (PGA: M6) (PLCC: 65)

L - - - - - - f CLOCK
L-_ _ _ _
CLOCK
~

IDT75C457

L - - - - - - - f LD

"

I-_J'_
I_t-....,

VAA
(PGA: A7, A9)
(PLCC: 23, 27)
AGND
(PGA: M, B6)
(PLCC: 21, 22)

" 40

FRAME IJ--++-----~"'.---f PO-P7 {A-E}
BUFFER

"

10 "

lOUT

OLO-OU {A-E}

L--------fSYNC
BLANK

Blue Channel
750

CO C1

RIW CE DO-D7

PLL

I I I I i.

8

MPU INTERFACE

Figure 3_ Typical Configuration for True-Color Applications

7.10

4

>c

ZUl
Cz

Vcc

::"

I

I~~
:x:

R1 = 220Q

f

14

Eel,

Om

0C
:D-I

R2= 330Q

R1

OU1

::~

R1

mU1

R,

~

"en

:D"O

51

Crystal
Oscillator

~

41~

I3

CLOCK

>0>
"0=
I~~
om

I 2

CLOCK

I> f)

UlC

::g

i!

r-

OZ

R2

R2

I~~
5ffi

R2

ECl Chip list:

z·
UlO

10H116

16-pin

Triple Line
Receiver

10H136

16-pin

Universal
Counter

10H350

16-pin

ECl To TTL
Translator

7

0
r
0
:D

:-l

o
Pin 11 = VBB
R1
03-00 are programmed for
5:1 or 4:1 multiplexing

5-to-1
4-to-1

03

02

l

H

l

l

01
l
H

~

00

11

l
H

Q1

15

3

1 Ain
lO

01
DO

6

02

5

03

-14

4. Ain

~rry

Out

_.9

19
10H136

S1

OE
10H350

>
"0
"0

r

o>
-I

5
Z

Z

U1

Figure 4. A Typical Clock Circuit for 5:1 or 4:1 Multiplexing

o-I

m

>
z
.;,
w

111

USING THE IDT5C457s PalietteDACTM IN TRUE-COLOR
AND MONOCHROME GRAPHICS APPLICATIONS

APPLICATION NOTE AN-63

Vcc

14
R1

ECl
Crystal
Oscillator

8

CLOCK
CLOCK

R2

R2
11

R1 = 220n
R2= 330n

7

lD

12009
8,10,11,12,13
ECl Chip List:
10H116

16-pin

Triple Line
Receiver

12009

16-pin

Prescaler wI
ECl To TIL
Translator

Figure 5. A Typical Clock Circuit for 5:1 Multiplexing

7.10

6

t;)®

PROTECTING YOUR DATA
WITH THE IDT49C465
32-81T Flow-thruEDCTM UNIT

APPLICATION
NOTE
AN-64

Integrated Device Technology, Inc.

by Tao Lin, Gerard Lyons and Frank Schapfel

INTRODUCTION
A TIME FOR ERROR· FREE MEMORIES
With the advent of high-performance 32-bit RISC and
CISC microprocessors, general purpose computing across a
wide spectru m of applications software is now easily
accessible on a desktop. We can now draw on computer
resources which are very sophisticated, multi-task systems
with distributed processing power, and we no longer must rely
on the centralized mini-computers and mainframes for
processing horsepower. Both the technical and the commercial
computing environments demand the insatiable hunger for
processing power.
This increasing demand for sophisticated applications
software requires more system memory on a local level.
Tightly coupled microprocessors and cache memory are
designed for optimized processing throughput, but the cache
memory is no substitute for system memory. Cache memory
is typically composed of very high-speed static RAMs, with
access times of 35 nanoseconds or less. System or main
memory is almost always comprised of slower but very

high-density dynamic RAMs, typically with access times of
100 nanoseconds or more, but with four times the density of
static RAMs. So, when the state-of-the-art static RAMs are 1
Megabit large, the newest density dynamic RAM is 4 Megabits.
Therefore, dynamic RAMs will always provide the most
cost-effective implementation for system memory.
Dynamic RAMs, though, are very prone to externally
induced errors. These externally induced errors are called soft
errors, since they do not cause permanent damage to the
memory cell. Soft errors can be induced by system noise,
alpha particle and power supply surges, and will cause random
data bits to be flipped from "1" to "0", or vice versa. Although
these soft error occurrences may be rare and inconsequential
when using small amounts of DRAMs, large DRAM arrays are
much more error prone. Also, as seen in Figure 1, larger
DRAM components are much more susceptible to soft errors
by virtue of their smaller memory cell size. Hardware errors
may also occuron system memory boards. These hard errors
occur if one RAM component or RAM cell fails and is stuck at
"0" or stuck at "1". Although less frequent, hard errors may
cause a complete system shut down.

Typical
Error
Rate
% Per
1,000 Hours

•

SOFT ERRORS DUE TO ALPHA PARTICLES ONLY

o

HARD ERRORS

0.1

I

0.01

0.001

0.0001

Density Bits/Chip
Flow-thruEDC is a trademark of Integrated Devioe Technology. Inc.

C-t
Zl>

.,

=l:E
=l

:I:

CPU

-t

:I:

m

6
Address

Tag

I..

.IData

Main
Memory

~

~

Address

""
0'>
til

I-Cache

Data

&

~
.....

Check Bit
Memory

Address

D-Cache

I'NR
Write
Buffer

DRAM
Controller

l>

Timing
Control
Logic

'tJ
'tJ

C

C')

Crystal
Oscillator

l>
-t

oZ
Z

o-t

N

Figure 2. A Typical Architecture of High-performance RiSe or else Systems

m
l>
Z

.;,

""

PROTECTING YOUR DATA WITH THE IDT49C465
32-BIT Flow-thruEDCTM UNIT

APPLICATION NOTE AN-64

ERROR CORRECTION TO THE RESCUE
A scheme exists that not only is able to detect soft and hard
errors, but is capable of correcting the erroneous bits. This
scheme is implemented by a family of error detection and
correction chips from Integrated Device Technology. Using a
modified Hamming code, developed at AT&T Bell Labs, all
single-bit errors may be detected and corrected, while all
two-bit and most three-bit errors can be detected. I DT pioneered
EDC chips, using CMOS technology in 1986, after recognizing
the importance of large DRAM memory arrays in distributed
computing.

The operation of an EDC device can be generally split
into:(1) generation of a coded word based on the data-word
being written to memory. This coded word is called The
Check-Bit Word. This operation is called Generate; (2)
detection of errors in a data-word read from memory by
comparing the corresponding check-bit word read from
memory and a newly generated check-bit word (based on the
data-word read from memory) and if possible correcting this
error. The comparison of these two check-bit words
(an exclusive-or (XOR) function) produces the so-called
Syndrome Word. This operation is called Detect/Correct.
The coding scheme employed in IDT's EDC devices is a
modified Hamming Code. For each data-word written to
memory, a coded pattern, or check-bit word, is appended to
the date-word. The new word (the data-word plus the checkbit word) can be termed a valid code. The modified Hamming
Code establishes a Distance-of-4 between one valid code
and another. This means that to go from one valid code to
another, 4-bits have to change. It can be shown that a
Distance-of-4 code enables you to detect all Single and
Double-Bit errors and correct all Single-Bit errors.
To implement a Distance-of-4 code on a 32-bit data-word,
a 7-bit check-bit word must be appended. For a 64-bit word,
a 8-bit check-bit word must be appended. The Hamming
Code algorithm to generate a check-bit word from a 32-bit
data-word or a 64-bit data-word can be found in either
I DT49C460 data sheet or I DT49C465 data sheet.

TYPICAL ARCHITECTURE OF
HIGH-PERFORMANCE RISC/CISC SYSTEMS
Figure 2 shows a typical architecture of high-performance
RISC orCISC systems which have the following features: (1)
high-speed cache memory (separate or common, Instructioncache and Data-cache) for fast access to frequently used
instructions and data, (2) write and read buffers to handle the
mismatch between the high-speed CPU and the slow-speed
main memory and (3) high-speed flow-thru EDC unit to insure
data integrity.
While most high-performance computer systems in current market have the first and second features, the third
feature is becoming more attractive and important when the
main memory space grows and the memory word-length
increases.
Certainly, using an EDC unit is an effective way
to improve the system reliability.

EDC ARCHITECTURES AND WORD-LENGTH
There are two basic architectures for EDC operation: flowthru and bus-watch. IDT provides a full line of EDC devices to
support 16-bit and 32-bit bus-watch architectures and 32-bit
and 64-bit flow-thru architectures, as shown in Table 1.

GENERAL EDC OPERATION
The basic function of an EDC device is to check the
integrity of data being read from a memory system, flag an
error if one has been detected and if possible correct that
error. The I DTfamily of EDC devices implements this function
using the same general principles, with some variations from
device to device.

I

Part Number

Architecture

Word-length

I

Comment

IDT39C60

Bus-watch

16-bit

Cascadable up to 64-bit
using 4 devices

IDT49C460

Bus-watch

32-bit

Cascadable up to 64-bit
using 2 devices

IDT49C465

Flow-thru

32-bit

Cascadable up to 64-bit
using 2 devices

IDT49C466

Flow-thru

64-bit
Table 1. IDT EDC Product Line

7.11

3

PROTECTING YOUR DATA WITH THE IDT49C465
32-BIT Flow-thruEDCTM UNIT

APPLICATION NOTE AN-64

-------------------------------,
,

WRITE (GENERATE)

,

READ (DETECT and CORRECT)

Main
Memory

Main
Memory

CPU

DRAM

DRAM

Error

IDT49C460

Check
Bit

Check
Bit

DRAM

DRAM

EDC

'- - - - - - - - - - - - - - - - - - - - - - (a) Common 1/0 Memory System

,- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .,,

,-------------------------------"
WRITE (GENERATE)

READ (DETECT and CORRECT)

Main
Memory

Main
Memory

CPU

CPU
DRAM

DRAM

Error

, Error

Data

IDT49C460
'--

"

\.
~S~C~=~"'~

EDC

IDT49C460

Check
Bit

EDC

Check
Bit

1------,1"'/

CB
L...-_ _ _ _ _

.A

DRAM

DRAM

--'~

,

,

,

'

._------------------------------,

I... _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ,

(b) Separate 1/0 Memory System
Figure 3. Basic Configurations Using a Bus-watch EDC Architecture

7.11

4

PROTECTING YOUR DATA WITH THE IDT49C465
32-81T Flow-thruEDCTM UNIT

APPLICATION NOTE AN-64

~-------------------------------

~------------------------------,

•

WRITE (GENERATE)

READ (DETECT and CORRECT)

•
•

Main
Memory
CPU

CPU

DRAM

, Error

, Error

Check

Check

Bit

Bit

DRAM

'- - - - - - - - - (a) Common 1/0 Memory System

,-------------------------------"

,- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -,,

WRITE (GENERATE)

READ (DETECT and CORRECT)

Main
Memory

Main
Memory

DRAM

DRAM

, Error

1.1

Error

Check

Check

Bit

Bit

DRAM

DRAM

,
...

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

_I

(b) Separate 1/0 Memory System
Figure 4. Basic Configurations Using a Flow-thru EDC Architecture

7.11

5

PROTECTING YOUR DATA WITH THE IDT49C465
32-BIT Flow-thruEDC'M UNIT

APPLICATION NOTE AN-64

System Data Bus
32- It

64-bit

Memory Data Bus
32- It

SO

SO

MD

IDT49C465

Lower
32-bit

Upper
32-bit
PCB I

CODE 10
SYO
=10
CBI

IERR
IMERR

CBO
Check
Bit In

MD

IDT49C465

CBI

CBO

SYO

PCBI

Check
Bit Out

CODE 10
= 11
8-

(a) Cascading Flow-thru EDC IDT49C465

Data
Bus

32- It

64-bit

Data

IDT49C460

IDT49C460

Check
Bit In
8-bit

CB

IERR

Data

Lower
32-bit

Upper
32-bit

CODE 10
=10

CODE 10
= 11
8-bit

SC

CB

Check
Bit Out
SC

3-State
Buffer
- I

(b) Cascading Bus-watch EDC IDT49C460

Figure 5. 64-bit Configurations by Cascading Two 32-bit EDC Units

7.11

6

PROTECTING YOUR DATA WITH THE IDT49C465
32·BIT Flow-thruEDCTM UNIT

APPLICATION NOTE AN-64

bus. The basic configurations usingthe I DT49C465 for common
I/O memory and separate I/O memory are illustrated in
Figure 4.
In the common I/O configuration, during a write (store)
operation, the data from CPU flows through the EDC unit and
is written to the main memory. When the data flows through
the EDC, the check bits are generated and stored into the
check-bit memory. During a read (load) operation, the data
from the main memory enters the EDC unit through the MD
bus while the check bits enter the EDC unit through the CBI
bus. The EDC unit then detects any errors and loads the
corrected data to the CPU through the SD bus.
In the separate I/O configuration, during a write (store)
operation, the data from CPU are directly sent to the main
memory. At the same time, the data is sent to the EDC unit
through the SD bus. The EDC unit then generates the check
bits and stores them into the check-bit memory. During a read
(load) operation, the data from the main memory enters the
EDC unit through the MD bus while the check bits enter the
EDC unit through the CBI bus. The EDC unit then detects any
errors and loads the corrected data to the CPU through the
SD bus.

BUS·WATCH ARCHITECTURE
A bus-watch EDC such as the IDT49C460 has a single
data bus. The basic configurations, using the IDT49C460 for
common 110 memory and separate 110 memory, are illustrated
in Figure 3.
During a write (store) operation, the CPU sends data to the
main memory. Atthe sametimethe datagoestothe EDC unit,
which then generates the check bits and stores them in the
check-bit memory.
On the other hand, during a read (load) operation, the data
from the main memory and the check bits from the check-bit
memory first go to the EDC unit. Based on the information
carried by the check bits, the EDC unit can detect all single-bit
and some multiple-bit errors, and correct all single-bit errors.
The corrected data is then sent to the CPU.
FLOW-THRU ARCHITECTURE
In contrast to a bus-watch EDC, a flow-thru EDC such as
the IDT49C465 provides two data buses: a system data (SD)
bus and a memory data (MD) bus. The dual-bus architecture
improves the throughput of the EDC operation and simplifies
the interface between the CPU system bus and the memory
~

SD _
O 31

I

!

__ --~-:.. , .-.~7;:--... -.•.• -~-.• -.•.• __ - - - -__ ~,
.....

. . . . . . . . ...

..

"'~"

______--1".

=

32-bit wide Busses

~------~------------------~

PO-3

MDO-31

P'E'R'R"
PSEL

f:ilUE

SDE

MLE

BEO-3

SLE
PEE

SYNCLK
SCLKEN 0 - - - - - - - - - - - - - - - 1
CLEAR

CODEID1'O~
MODE 2-0

3

Control
Logic

:

PCBI O_?

CBIO_?

Figure 6_ Block Diagram of IDT49C465

7.11

7

II

PROTECTING YOUR DATA WITH THE IDT49C465
32-81T Flow-lhruEDCTM UNIT

APPLICATION NOTE AN-64

CASCADING 32-BIT EDC DEVICES FOR 64-BIT
MEMORY SYSTEMS
As mentioned in the previous section, for a 32-bit data
word, 7 check bits are necessary, while for a 64-bit data word,
8 check bits are needed. Although the IDT49C460 and the
IDT49C465 are both 32-bit EDC units, they have an S-blt
output-bus for output of generated check-bits to memory and
an S-bit input bus to read back check-bit from me mory. In this
way, they can be cascaded to support 64-bit applications. In
the 32-bit mode, only 7 bits of the check-bit input and output
buses are used, while in the 64-bit mode, all 8 bits are used.
Figure5shows how two IDT49C465s (ortwo IDT49C460s)
can be cascaded to build a complete 64-bit EDC unit. In the
cascaded 64-bit mode, the EDC operation can be broken into
two stages; a lower 32-bit stage and an upper 32-bit stage.
For the IDT49C465 (see Figure 5a), a general description
of the EDC operation is discussed below.
1. Generation starts by generating a Partially Generated
Check-bit Word in the lower slice, based on the lower
32-bit of the 64-bit data-word, and sending this to the
upper slice. The upper slice combines the Partially
Generated Check-bit word from the lower slice, with its
generated check-bit word (based on the upper 32-bit of
the 64-bit data-word), to form a final check-bit word. Thus,
the source of check-bit in a cascaded system is the
upper-slice device.
2. Detection/Correction starts in the lower-slice where the
check-bits from memory are input, as well as the lower
32-bit of the 64-bit data-word. Here the inputted checkbits are compared with the newly generated check-bits
(based on the lower 32-bit of DATA-word) using an XOR
function to produce a Partial Syndrome Word, which is
passed onto the upper-slice device. At the same time, in
the upper slice the upper 32-bits of 64-bit data-word is
used to generated a so-called Partial Check-Bit Word
which is sent to the lower slice. So now we have in both
the upper and lower slice devices almost simultaneously
two pieces of data; the Partial Syndrome Word (generated in the lower-slice) and the Partial Check-Bit Word
(generated in the upper-slice). In each slice these two
pieces of data are XOR'd to produce a Final Syndrome
Word which is used to detect and correct errors on the
64-bit data word.

The IDT49C460 carries out Detect/Correct slightly differently (see Figure 5b), namely, the Partial Syndrome generated in the lower-slice is sent to the upper slice, then the Final
Syndrome is generated in the upper-slice and this FinalSyndrome is now fed back to the lower-slice. Thus Detect/
Correct in the lOT49C460 employs a serial approach, whereas
the IDT49C465 uses a faster paralleled approach. Moreover,
in the IDT49C460 case, an additional tri-state buffer such as
the I DT74FCT244 is needed while in the I DT49C465 case, no
additional external logic is needed.

OVERVIEW OF THE IDT49C465
ARCHITECTURE
The IDT49C465 architecture is an evolutionary development on the IDT49C460 EDC device. The IDT49C460 is a
single-bus32-bit EDCcascadableto 64-bits. The IDT49C465
draws on this basic architecture to provide a dual-bus or
flow-Thru 32-bit EDC cascadable to 64-bits. Figure 6 shows
a block diagram of the IDT49C465; the key difference
between the lOT49C460 and the I DT49C465 is the presence
of a second 32-bit DATA bus to provide the flow-thru path for
data through the device.

7.11

DATA BUSES
The System Data Bus, or SO Bus, is a 32-bit bi-directional
bus. Data is written to the EDC using this bus for Check-Bit
Generation, so that when a data-word is written to memory
the corresponding check-bits are written simultaneously. Also
when a data-word read from memory is corrected, the corrected data-word is read from the SO Bus by the system
processor. The SD Bus has associated with parity-checking
and generation and also separate byte enables on the SD Bus'
output buffers so that Partial Byte operations can be supported.
The Memory Data Bus, or MD Bus, is a 32-bit bi-directional
bus. Data written from the system processor through the SD
Bus can be written to memory using this bus. When the
processor is reading a word from memory, the data word is
read in through the MD Bus and the corrected data word
(depending on the status of the data) is sent to the processor
through the SO Bus.

8

PROTECTING YOUR DATA WITH THE 1DT49C465
32-81T Flow-thruEDCTM UNIT

APPLICATION NOTE AN-64

EXPANSION BUSES
The IDT49C465 has four 8-bit buses that are an integral
part in the Detect/Correct path for both a 32-bit EDC system
and a 64-bit EDC system.
CBI(7:0)
1. When the IDT49C465 is operating as a 32-bit EDC
system or is the lower 32-bit slice in a 64-bit EDC system,
this 8-bit bus is the input port for Check-Bits read from
Memory.
2. When the IDT49C465 is operating as the upper 32-bit
slice in a 64-bit EDC system, this bus is the input port for
partial Syndromes from the lower slice.
PCBI(7:0)
1. When the IDT49C465 is operating as a 32-bit EDC
system, this bus is unused.
2. When the lOT49C465 is operating as the lower 32-bit slice
in a 64-bit EDC system, this 8-bit bus is the input port for
Partial Check-Bits read from the upper slice.
3. When the IDT49C465 is operating as the upper 32-bit
slice in a 64-bit EDC system, this bus is the input port for
Partially Generated Check-Bits from the lower slice.

CBO(7:0)
1. When the IDT49C465 is operating as a 32-bit EDC
system or is the upper 32~bit slice in a 64-bit EDC system,
this 8-bit bus is the output port for Check-Bits being written
to Memory
2. When the lOT49C465 is operating as the lower 32-bit slice
in a 64-bit EDC system, this bus is the output port for
Partially Generated Check-bits being sent to the upper
slice.
SYO(7:0)
1. When the IDT49C465 is operating as a 32-bit EDC
system, this 8-bit bus outputs the Final Syndrome word
associated with the DetecVCorrect logic.
2. When the lOT49C465 is operating as the lower 32-bit slice
in a 64-bit EDC system, this bus is the output port for
Partial Syndrome word being sent to the upper slice.
3. When the IDT49C465 is operating as the upper 32-bit
slice in a 64-bit EDC system, this bus is the output port for
Partial Check-bit word being sent to the lower slice.

Operating Modes
The IDT49C465 has 3 mode control pins, MODEID(2:0),
which enable the user to select which mode the part is
operating in. These modes are summarized in Table 2.

MODE DESCRIPTION

000

ERROR DATE MODE

X01

DIAGNOSTIC OUTPUT MODE

X10

GENERATE-DETECT MODE

100

CHECK-BIT INJECTION MODE

X11

NORMAL OPERATING MODE

II

Table 2. IDT49C465 Operating Modes

7.11

9

PROTECTING YOUR DATA WITH THE IDT49C465
32-BIT Flow-thruEDC'"M UNIT

APPLICATION NOTE AN-64

ERROR DATA MODE (000) :
In this mode the contents of the Error-Data Register are
output uncorrected on the SO Bus. The Error-Data Register
is a 32-bit register which gets latched under the following
conditions: 1. an error condition has been detected by the
EDC-ERROR) and is asserted low, 2. the on-chip 4-bit
Error-Counter reads zero 0000 (Le. no error has occurred
since the last clear operation), 3. the input Signal, SCLKEN),
is held low so that the diagnostic clock, SYNCLK, is enabled,
4. the diagnostic clock, SYNCLK, undergoes a LOW-to-HIGH
transition.
Data islatched into the Error-Data Registerfrom the output
of the Memory Data Latch when and only when these conditions are met. Thus, the Error Data Register contains the
Memory Data word corresponding to the first error since a
clear operation (assuming SYNCLK has been run continuously). If the Error Data Register has just been cleared, then
output of the contents of this register will provide a source of
zero-data if that is required.

BIT16:23

The contents of the Syndrome Register, which is
an 8-bit register within the Diagnostic Unit, is
output on the SO Bus at these positions (LSB at
bit 16, MSB at bit 23). The Syndrome Register
gets latched at the same time as the Error Data
Register and contains the Final Syndrome corresponding to the first error to occur since a clear
operation. .

BIT 24:27

The contents of the on-chip 4-bit Error-Counter
are output on the SO Bus at these positions (LSB
at bit 23 and MSB at bit 27). The Error-Counter
which gets clocked under the following conditions: 1. An error condition has been detected by
the EDC, i.e. xto(ERROR) is asserted low, 2. the
on-chip 4-bit Error Counter does not read 1111
(or F HEX), therefore, not more than 16 errors
have occurred since the last clear operation, 3.
the input Signal, xto(SCLKEN), is held low so that
the diagnostic clock, SYNCLK is enabled and 4.
the diagnostic clock, SYNCLK, undergoes a LOWto-HIGH transition.

DIAGNOSTIC OUTPUT MODE (X01) :
In this mode a 32-bit Diagnostic Word is output on the SO
Bus. The structure of this word is outlined in Figure 7.
BITS 0:7

BIT 8:15

Error
Type

The output of the check-bit multiplexer is output
directly on the SO Bus at these positions (LSB at
bit 0 and MSB at bit 7).

The Error Counter will tell the number of errors
that have occurred since the last clear operation.
BIT28:29

Reserved

BIT30:31

The contents of the Error Signal Register, which
is a 2-bit register is output on the SO Bus at these
positions (SB at bit 30 and.MSB at bit 31 ). Bit 0
and bit 1 of the register are set if a Multiple Error
has been flagged and bit 1 only is set if a Single
Error has been flagged at the same time and
underthe same conditions as the Error Data and
Syndrome Registers are latched.

Whatever is being forced on the PCBI(7:0) input
pins is output on the SO Bus at these positions
(LSB at bit 8 MSB at bit 15).

Test

Error
Counter

Partial Checkbits
from Input Pins

Syndrome Bits
Register Contents

Byte 3

Byte

2

Byte

Checkbits

1

Byte

0

Mis -1- 23 1221 2' I 2° 716151413121110 716151413121110 716151413121110

31

28 27

24 23

16 15

8

7

Figure 7. Output Syndrome/Diagnostic Word

7.11

10

PROTECTING YOUR DATA WITH THE IDT49C465
32-BIT Flow-thruEDCTM UNIT

APPLICATION NOTE AN-64

GENERATE-DETECT MODE (X10) :
In this mode, detection and generation take place but no
correction. Data whether correct or not, passes thru the
device from the MD Bus to the SD Bus.
NORMAL OPERATING MODE (X11) :
This is the mode where normal detection/correction and
generation takes place for a single-slice device (32-bit EDC
system) or for the upper and lower slices in a cascaded 64-bit
EDC system.
CHECK-BIT INJECTION MODE (100) :
In this mode the check-bit multiplexer enables bits 0:7from
the output of the System Data Latch to be fed into the EDC as
a check-bit input, normal correction is activated. This is a very
useful capability for carrying out a diagnostic check on the
detecUcorrect path of the EDC.
PARITY FOR THE SYSTEM BUS
The IDT49C465 supports byte parity on the SD Bus, with
the polarity of the parity ( even or odd) selectable using the
input pin PSEL. If PSEL is low, then parity (both checking and
generation) will be even. If SPSEL is high, then parity will be
odd. The part has 4 parity I/O lines one for each byte of the SD
Bus and a parity error signal, PERR), which flags a parity error
on in-coming data by being asserted low.
PARTIAL BYTE WRITE AND READ-MODIFY-WRITE
CAPABILITY
The IDT49C465 supports, through a number of features,
Partial Byte Writes and Read-Modify-Writes cycles. Firstly
the SD Bus has 4 Byte Enable signals associated with it,
BE(3:0), these input lines provide, in conjunction with SOE),
separate output enable control on each byte of SD bus data.
The BE bus is also the control input to the Sys-Byte-Mux, this
mux enables mixing on a byte-by-byte basis of data from the
SD latch (A input to mux) and from the Pipe-Line latch (B input
to mux). So, for example, if the processor wanted to do a
Partial Write or Partial Store of a byte (byte position 3) to a
memory location byte position 3 the following sequence would
occur: (1) read the memory location in question through the
MD Bus and correct if possible or necessary. The corrected
data-word will be latched into the Pipe-Line latch, (2) the byte
to be written is latched into the SD Latch at byte position 3, all
other byte are undetermined, (3) Now we have both pieces of
data necessary to construct the 32-bit word to be written to
memory and (4) BE(3) is held low and all other BEs are held
high. Thus the output of the Sys-byte-Mux is the correctly
constructed 32-bit word which is then written to memory
through the MD Bus with it's corresponding check-bits.
64-BIT GENERATE
A very useful and ultimately cost-saving measure associated with the IDT49C465, is its 64-bit generate mode. If the
CODE ID of the IDT49C465 is set at 01, the part is configured
as a single-slice 64-bit generate EDC. While operating in this
mode, the lower 32-bit of the 64-bit data word is input on the

7.11

MD bus pins and the upper 32-bit of the 64-bit data word is
input on the SD bus. The 8-bitgenerated check bits are output
on the CBO bus. In 64-bit generate mode, the EDC is dedicated to check-bit generation, all other features are disabled.
Because the 64-bit generate is executed in a single slice,
very fast generate speed can be achieved (15ns as opposed
to 30ns in a two-slice 64-bit cascaded system). This feature
can also help reduce part count. In 64-bit memory systems, it
is common to use 4 32-bit EDC devices; 2 for detecUcorrect
and 2 for generate. With the 64-bit generate capability, this
part count is reduced from four to three.

WHY FLOW-THRU EDC
To fully understand the advantages of the IDT49C465
flow-thru EDC over the IDT49C460 bus-watch EDC, it is
necessary to first know the architectural differences between
the IDT49C465 and the IDT49C460. Figure 8 compares the
simplified internal architectures of the two chips. As compared with the IDT49C460, the IDT49C465 has the following
unique features:
•
•
•
•
•
•
•
•

Dual data buses
Dual check-bit generators: one for SD Bus and the other for
MD bus
Independent check-bit generation path
Independent error detection/correction path
Dedicated syndrome output
Dedicated check-bit output
Output pipeline latch
Parity check/generation

These features greatly simplify the interface of the EDC
unit with the system data bus and the memory data bus, and
thus can considerably improve the system performance.
Generally speaking, in a single bus EDC architecture like the
IDT49C460, the data bus connects to both the processor and
the memory system. Thus, in a normal correction cycle, data
is read into the EDC from memory through the data bus, and
the data is corrected. Then, the data bus is enabled as an
output and the corrected data is sent to the processor.
Therefore, during a correction cycle, the data bus must be
turned around from being an input to being an output.
Consequently, a single bus architecture has inherent delays
associated with the enable/disable times of the data bus
output buffer. On the other hand, separate data buses, as in
the IDT49C465, allow us to dedicate buses to a specific
direction of data flow and, as such, is a superior architecture.
In a 32-bit system using common I/O memory, the dual bus
architecture of the IDT49C465 allows direct interface of the
flow-thru EDC unit with the system data bus and the memory
data bus, as shown in Figure 4a. On the other hand, if the
IDT49C460 is used, then two sets of transceivers are needed
to buffer both system data bus and memory data bus to the
single data bus of the IDT49C460, as shown in Figure 3a.
Similarly, in a 32-bit system using separate 110 memory,
the dual bus architecture of the IDT49C465 allows direct
interface of the flow-thru EDC unit with the memory data bus.
Only a single set of transceivers is used to connect the CPU

11

II

PROTECTING YOUR DATA WITH THE IDT49C465
32-81T Flow-thruEDCTM UNIT

APPLICATION NOTE AN-64

system data bus to the EDC unit, as shown in Figure 4b. On
the other hand, if the IDT49C460 is used, then a set of
transceivers and a set of buffers are needed to hook up both
system data bus and memory data bus with the single data
bus of the IDT49C460.
In particular, the multi-bus architecture and the independent
error generation and detection/correction paths of the
IDT49C465 provide significant performance improvement in a
64-bit system using two cascaded EDC units. Figure 9 shows
the internal data paths of cascaded IDT49C465s and cascaded
I DT49C460s during a read (error detect/correct) operation. In
the IDT49C465 case, the entire error detect/correct path can
be divided into two steps. In the first step, the lower 32-bit unit
generates the partial check bits from the lower 32-bit data, and
then compares the partial check bits with the original check
bits to generate the partial syndrome bits. At the same time,
the upper 32-bit unit generates the partial check bits from the
upper 32-bit data. Then, the partial syndrome bits from the
lower unit and the partial check bits from the upper unit are
exchanged between the two units. In the second step, both
lower and upper units generate the final syndrome bits
independently and then correct errors in the lower 32-bit data
and the upper 32-bit data, respectively, in parallel. Therefore,
the total delay time is the sum of MD-to-SYO plus CBl-to-SD.
On the other hand, in the IDT49C460 case, the entire error
detect/correct path can be divided into three steps. In the first

7.11

step, like in the IDT49C465 case, the lower 32-bit unit generates
the partial check bits from the lower 32-bit data, and then
compares the partial check bits with the original check bits to
generate the partial syndrome bits. At the same time, the
upper 32-bit unit generates the partial check bits from the
upper 32-bit data. However, in contrast to the IDT49C465
case, only the partial syndrome bits from the lower unit are
sent to the upper unit. In the second step, the upper unit
compares the partial check bits from the upper 32-bit data with
the partial syndrome bits from the lower unit to generate the
final syndrome bits. Then, the final syndrome bits are sent
back to the lower unit. Finally, in the third step, the lower unit
and the upper unit correct the errors in the lower 32-bit data
and the upper 32-bit data, respectively. Consequently, the
total delay time is the sumof DATA-to-SC plus BC-to-SC plus
CB-to-DATA, which is much longer than the delay in the
IDT49C465 case. Moreover, since the IDT49C460 has only
one check bit input bus, an external octal tri-state buffer is
needed to multiplex the original check bits and the partial
check bits.
Based on the above discussion, Table 3 summarizes the
performance comparison between the IDT49C465 and the
IDT49C460D, the fastest version of the IDT49C460. It can be
seen that in most situations, the IDT49C465 has significant
speed advantage over the IDT49C460.

12

PROTECTING YOUR DATA WITH THE IDT49C465
32-BIT Flow-thruEDCTM UNIT

APPLICATION NOTE AN-64

(

Features Of IDT49C465 )
-Dual Data Bus Architecture
-Dual CheckBit(CB) Generators
-Independent CB Generate Path
-Independent Error
Detect/Correct Path

-Dedicated Syndrome Output
-Dedicated CB Output
-Output Pipeline Latch
-Parity Check/Generate
-1 Off-chip Feedback for
64-bit Error Correct
-144-pin PGA

IIHIIlmII

Path For Detect
and Correct Only

c::J Path For Generate,
Detect and Correct
(a) Simplified Block Diagram of IDT49C465 EDC Unit

(

Features Of IDT49C460 )
-Single Data Bus Architecture

-Single Checkbit Generator
-Shared Syndrome and CB Output
-2 off-chip Feedback for
64-bit Error Correct
-68-pin PGA
I

I
c::J Path For Generate,

II!mImU Path For Detect

Detect and Correct

and Correct Only

(b) Simplified Block Diagram of IDT49C460 EDC Unit
Figure 8. Internal Architecture Differences Between IDT49C465 and 1DT49C460

7.11

13

I

PROTECTING YOUR DATA WITH THE IDT49C465
32-BIT Flow-thruEDCn.< UNIT

APPLICATION NOTE AN-64

MD32-63

SD32-63

Generate
Final

Upper 32·Bit
CODE ID 11

=

CBIO-7

---+----..;.........,
Lower 32·Bit
CODE ID 10

=

Syndrome
SDO-31

MDO-31

(a) 64-blt Error Detect/Correct Path of Cascading IDT49C465

DATA32-63

DATA32-63 -

. . . . .- - - - - -_ _ _ _ _ _ _ _ _ _ _. .

Upper 32·Bit
CODE ID 11

=

Check
Bits

Generate
Partial Syndrome
DATAO-31

Lower 32·Bit
CODE ID 10

=

DATAO-31
(b) 64-bit Error DetectlCorrect Path of Cascading IDT49C460
Figure 9. Comparison of 64·bit Error DeteclfCorrect Path Between IDT49C465 and IDT49C460

7.11

14

W"C

"':0

too

=irTl

E'g
=:z

.!.c)

Common 1/0

:r-<
Co
me:

Separate 1/0

0:0

64-bit
Cascade

32-bit

32-bit

(1)

Read (1)

Write

Read

Read(1)

Write

<:lo
l:>

64-bit
Cascade

z>
=i:E

~

Read(1)

Write

e:-I

-I
::I:

Write

m

C
MD->SD

20ns

SD->CBO

15ns

MD->SYO

15ns

SD->CBO

CBI->SD

20ns

PCBI->CBO 15ns

15ns

MD->SD

20ns

FCT24S(2)

5ns

SD->CBO

5ns MD->SYO

15ns

FCT24S(2)

5ns

20ns

SD->CBO

15ns

~

CD

~

20ns

15ns

35ns

Faster

26%
Faster

34%
Faster

28ns

19ns

47ns

40%

IOT49C
4600

FCT24S(2)
D->D

5ns
18ns

(2)
FCT24S
D->SC

5ns
14n5

FCT24S(2}

30ns

25ns

30ns

CBI->SD

5ns

(2)
FCT24S

5ns

(2)
FCT24S

14n5

D->SC

14n5

D->D

CB->SC

11ns

CB->SC

11ns

FCT24S

CB->D

12ns

til

5ns PCBI->CBO 15ns

40ns

35ns

18%
Faster

28ns

D->SC

19ns

5ns
18n5

FCT24S(2}
D->SC

47ns

30ns

(2)
5ns
14n5

(2)
FCT24S

FCT24S

5ns

D->SC

14n5

D->SC

14n5

CB->SC

11ns

CB->SC

11ns

CB->D

12ns

5ns

(2)

5ns

FCT24s(2)
NOTES:
1. The EDC units perform correction always.
til

20ns

12%
Faster

(2)

FCT24S

.....

en

15ns

FCT24S(2}

IOT49C
465

~

FCT24S(2)

(2)

5ns

FCT24S

Table 3. Performance Comparison

2. FCT245 is high-speed bidirectional transceiver.

5ns

5ns

>
"C
"C

r

o
>
-I
o
Z
Z

o-I

m

>
z
a,

II

"'"

PROTECTING YOUR DATA WITH THE IDT49C465
32-81T Flow-thruEDCTM UNIT

APPLICATION NOTE AN-64

CONCLUSIONS
Whether designing a correct always (flow-thru) EDC or
bus-watch EDC memory systems, IDT offers a high
performance solution for keeping memories error free. The
key system benefit for using EDC is the continuous system
operation, even with hard or soft errors occur. The key benefit
for using a flow-thru EDC is the reduced memory design time
when performing the correct always function, and improved
performance for 64-bit memory systems.

7.11

16

G

IntegrOlted Devic.e Technology, Inc..

USING IOT73200 OR IOT73210
AS READ AND WRITE
BUFFERS WITH R3000

APPLICATION
NOTE
AN-65

CONTENTS
AN-6SA

USING THE IDT73200 MULTILEVEL PIPELINE REGISTER AS READ AND WRITE
BUFFERS WITH R3000/1
by Danh Le Ngoe, Ignaslo Osorio, Avlgdor Wlllenz

AN-6SB

USING IDT73210 AS READ AND WRITE BUFFERS WITH R3000
by V.S. Ramaprasad

II

"'1990 In1egra1ed Device Technology, Inc.

6:90

7.12

t;)®
Integrated Device Technology, Inc.

USING THE IDT73200 MULTILEVEL
PIPELINE REGISTERS AS READ AND
WRITE BUFFERS WITH R30QO/1

APPLICATION
NOTE
AN-GSA

By Danh le Ngoc, Ignacio Osorio and Avigdor Willenz

INTRODUCTION
The objective of this application note is to describe the use
of the lOT 73200 multilevel pipeline register as thewrite buffer
and read bufferforthe R3000/1 RiSe processor.Thefoliowing
topics are discussed:
• The IDT73200 Multilevel Pipeline Register, presents a
brief description of general characteristics and configura
.
tions of the multilevel pipeline register.

• Read-Write buffers, explains what read and write buffers
are, and how they function in a R3000/1 system.
• Implementing R~W Buffers, describes how to implement
the IDT73200 as read and write buffers. Buffer depths are
also discussed in this section.
• A Typical System, provides an example of read-write
buffers using the IOT73200, within a RiSe system. It also
presents the control logic and PAL equations to operate the
IOT73200 as read and write buffers.

00-15
16

ep-I-+~a

SELO-2 ~3~_ _~I---'---'L---..L..-w~---'---L.--~

)Jo

10-3 4

eEN

mo

vee

~~
rrjo

cn)J

VSS3-0

)Jr

2647drw 16

YO-15

OE

Figure 1. Block Diagram of the 1OT73200

6190

©1990 Integrated Device Technology. Inc.

7.12

2

USING THE 10173200 OR 10173210 AS
READ AND WRITE BUFFERS WITH R3000

APPLICATION NOTE AN-65

13 12

11

10

MNEMONIC

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

LOA
LOB
LOC
LOO
LOE
LOF
LOG
LOH
LSHAH
LSHAO
LSHEH
LSHAB
LSHCO
LSHEF
LSHGH
HOLD

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

PIPELINE
LEVEL

FUNCTION

00-15->A
00-15->B
00-15->C
00-15->0
00-15->E
00-15->F
00-15->G
00-15->H
00-15->A->B->C->0->E->F->G->H
00-15->A->B->C->0
00-15->E->F->G->H
00-15->A->B
00-15->C->0
00-15->E->F
00-15->G->H
HOLD ALL REGISTERS

1
1
1
1
1
1
1
1
a
4
4
2
2
2
2

2647 drw 17 02

Figure 2. Load Control

THE lOT 73200 MULTILEVEL PIPELINE
REGISTER

processor supports a write-through cache policy, all data
written into the data cache must also be written into the main
memory to maintain the cache coherency. Due to the
The lOT 73200 is a high-speed, low-power Programmable
data-rate mismatch between the high-speed processor bus
Multilevel Pipeline Register. It has a dedicated 16-bit input
(33MHz -> 240M bytes/sec) and slow speed main memory
port and a dedicated 16-bit output port.
(10-15MHz ->10-40 Mbytes/sec), a write buffer and a readAs shown in figure 1, the IOT73200 contains eight 16-bit.
buffer are required. The write buffer is an elastic buffer which
registers which can be configured as one a-level, two 4-level,
is used to capture addresses and data at the cache speed. At
four 2-level, or eight 1-level pipeline registers. Data at the input
the other side of the write buffer, data is transfered into the
port 00-15 can be written into any of the eight registers under
main memory at the system memory speed.
control of the load control: 10-3. Figure 2 illustrates the load
When a load operation causes a cache miss, a main
control for the input port .
memory read is initiated. Two types of main memory read are
An eight-to-one output multiplexer allows data to be read
supported on the R3000/1: single word transfer and multiple
on the V-bus from any of the eight registers using the outputword transfer. In either case, a read-buffer is used to capture
selection control: SO-2. Figure 3 illustrates the output control.
data from the system memory at memory speed. Then data is
written into the cache at the cache speed. The depth of the
READ-WRITE BUFFERS
write buffer and the read-buffer are dependent on different
As shown in the Figure 4 , a high-speed computer system factors such as processor speed, system memory speed, bus
consists of a R3000/1 chip set, high-speed cache, write buffer,
protocol and the application.
read buffer, I/O devices, and main memory. Since the main
SEL2

SEL1

SELO

Y OUTPUT

0
0
0
0
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1

AREG
B REG
CREG
DREG
E REG
FREG
GREG
H REG

1
1
1

0
1

2647 drw 18

Figure 3. Output Selection

7.12

3

7 '

USING THE IDT73200 OR 1DT73210 AS
READ AND WRITE BUFFERS WITH R3000

APPLICATION NOTE AN-65
HIGHEST BANDWIDTH
(NATIVE RATE OF CPU)

PROCESSOR
IDT79R3000

IDT79R3010

DATA

ADDRESS

CACHE

INSTRUCTION
CACHE

I

'f

---

WRITE

IWRITE BUFFER

("

+

MBYTES/Sec

33MHZ

~240

MBYTES/Sec

25MHZ

~100

MBYTES/Sec each

33MHZ

~120

MBYTES/Sec each

... It-

-

.

~200

--------~

,t

~ I-- DATA CACHE

25MHZ

---------~

.

----

READ BUFFER

&

READ
BUFFER

"> 10-15 MHz......

HIGH-SPEED SYSTEM BUS

1

1

BiFIFO

l

MAIN MEMORY

SCSI
CONTROL

t

SCSI BUS

~ I
I

10-40 Mbytes/Sec

1I

DISK
CONTROL

cb

LOWESTBA NDWIDTH
( SYSTEM MEMORY & 1/0 DEVICES)
2647 drw 19

Figure 4. Simplified Block Diagram of a High-Speed RISC System

IMPLEMENTING R-W BUFFERS
As previously described in section 1, the IDT 73200 is like
a high-speed synchronous memory with a depth that is
programmable from 1 to 8 deep. Therefore, a write buffer and
read buffer for the high performance R3000/1 system can be
easily implemented with the help of the IDT 73200.
Figure 5 illustrates adetailed R3000/1 system which consists
of the R3000/1 chip set, write buffer, read buffer, IDT49C465
Flow-thruEDCTM, system main memory, and several state
machines to control the main memory interface. In this scheme,
the data bits together with the parity bits flow from the main
memory through the EDC device for error detection and
correction. When an error is detected, the EDC informs the
read buffer control through an error feedback path.

In figure 5 the write buffer consists of two paths: address
and data. The address path (34-bit) is created with three IDT
73200s to capture the address, tag, and the access type bits.
The data path of the write buffer (32-bit), is formed by two
IDT73200. Data coming from the CPU is buffered into the
"data path" write buffer prior to being written into the main
memory.
The read buffer in figure 5 consists only of a "data path"
(36-bits) which includes the required data parity on the
R3000/1 system. The IDT 49C465 high speed Flow-thruEDC
can be used to maintain the data integrity of the system main
memory. Also, parity bits are generated with the help of the
IDT49C465 Flow-thruEDC.

7.12

4

:IlC
m(/)

FPU
R3010

OSC

~~

-

~ESET-"
INITO

INIT
PAL

;;~

:"'i f---+

CPU
R3000

no,,,- :J~: ~
~
ITA 5-0-..

DATAl

I

-

... .

"'''~J
"'" l

E;~

~~
(4::;

X60

zI

4)

~ ACCTYP1-0

21

~

~

BUSY
RD&WF

MEM
RD&WR

,

AWBCT

~

7<-i

mo
CO

,,0
":Il
m_
:Ilo

(/)::1
:E",
-N
IO

J

~2

CP

10-3

74FCT373A
2X

16

D15-0

lOT 73200
AS

ACUTYP
WRITE
BUFFER

rrr--

IOT 73200
AS
TAG
WRITE
BUFFER

~
Yl-0

-..
-..
-..

D15-0

AS

ADRLOW
WRITE
BUFFER

-

Y15-0

CP

-

•

D15-0

~

lOT 73200

-..
-..

rr-

rSEb}?

16

D15-0

f-+

~

;::

-<

mN

-1-

PAL AS
MEMORY DWBCT
CONTROL

>
OW
~m~~~
o
rO

~::1

-I",
36

D CACHE
X60 BITS

FCT240A

§~~I

:Eo

~

~

ADDRLO

~ "m"C:~''"'''11

>-1
om

~

10-3

lOT 73200
AS

DATA
WRITE
BUFFER

~
Y15-0

~

Y15-0

:Il>

!

•

-..

-..
-..

w(/)

36

t

-

or

f--

Yl1-0

~

lOT 73200
AS
DATA PARITY
READ
BUFFER

~~

-..
-..

t
f--

Yll-Q

SEL2-0
,--..
lOT 73200
AS
DATA
WRITE
BUFFER

o
o
o

rf-+

IOT 73200
AS
DATA
READ
BUFFER

r-

~

~

~

f--

lOT 73200
AS
DATA
READ
BUFFER

~
D15-0

D15-0

r--

Yll-0

D15-0

N

I
[:4

J~
I 'FJrnW

I READY

ADDRESS
DRAM CONTROL

VIR "CAS

~

ROW
COLUM
ADDRESS

+

SDO-31

IEm

FLOW-THROUGH EDC

I

CBOO-6

CB10-6

t

+ II

f

74FCT245

+

t

A"

~, ~

"'MO", W',"

I

>

"'tl
"'tl

C",,,·,,,,I

USING COMMON ItO DRAMS

~

12

MOO-31

74FCT245

:"m"
j
~

ss

lOT 49C465

I

CJ1

12

DATA BUS

ADDRESS BUS

r-

o>
-I

(5
Z
Z

o-I

m

Figure 5. Detailed R3000 System with Read and Write Buffer

'"a

>
z
..;,
CJ1

111

USING THE IDTI3200 OR IOTI321 0 AS
READ AND WRITE BUFFERS WITH R3000

APPLICATION NOTE AN-65

BUFFER DEPTH
As discussed earlier, the lOT 73200 can be configured for
different depths: eight 1-level, four 2-level, two 4-level or one
8-level deep registers. This feature makes the 73200 particularly flexible in Read/Write buffer applications.
The depth of the write buffer is programmable using the
load-control and the output selection. A single lOT 73200 can
be programmed to a buffer depth of 1 to 8. A deeper write
buffer can be implemented by cascading several devices in
depth as shown in the figure 6. The right depth depends on the
application program and/or hardware requirements.

,
CP
CEN
10-5

.
..

015-0

00-31
32
1

....

,
015-0

~

...
lOT 73200
AS
WRITE
BUFFER

SELO-2
Vss~

~

....

lOT 73200
AS
WRITE
BUFFER

~

OE

Y15-0

Y15-0

t
015-0

~

,

015-0

~
lOT 73200
AS
WRITE
BUFFER

...

,

Y15-0

~

~
~

Typical write buffer depths are two and four levels. However, high end applications with intensive memory access
may require deeper write buffers, i.e., eight or sixteen levels
as shown in figure 6.
Read buffer depth design issues are somewhat different
from those of the write buffers. For example, when an I-cache
miss occurs we are faced with the question of "how many
blocks to refill in the I-cache? " To answer this question, we
should recall that the miss rate is determined by the cache size
and the block size. Therefore, the block size determines the
size of the read buffer. Thus to bring 16 words from memory
into the I-cache would require a 16 level deep read buffer.
Fetching small blocks of instructions using a shallow read
buffer implies constantly fetching instructions and therefore
stalling the CPU for several cycles. Depending on the application, this could impose significant penalty on system performance. Due to program locality (sequentiality of instructions),
we would benefit most by fetching a large block. Deep read
buffers for I-cache are therefore an appealing solution. Typical read buffer depths are 4levels; high end applications could
consider from 8 to 16 levels read buffers.
O-cache fetching, on the other hand, is random in nature
and typical schemes prefer a 1-level deep read buffer.
The flexibility of the 73200 allows instantaneous
re-configuration when fetching for the I-cache and then for the
D-cache. For example, We could have an R3000/1 initialized
for 16 words I-cache fetching and 1 word D-cache fetching and
still use the same read buffer. This can be accomplished
through a read buffer controller capable of configuring the
73200 to different depths.
Lets now discuss two popular read buffer configurations.

lOT 73200
AS
WRITE
BUFFER

,t

a) 1-level deep Read Buffer &
b) 8-level deep Read Buffer

Y15-0
1

Y31-0
2647 drw 21

Figure 6. 16-Deep and 32-Wide Write Buffer Using 1OT73200s

With the help of the write buffer, the CPU can write to the
memory without regard to the memory speed. However, if
consecutive (or back to back) write operations take place, the
write buffer would eventually become full and cause the CPU
to stall. Naturally, this could present a problem in high performance systems. A logical solution to CPU stalls is to increase
the depth of the write buffer.

1-LEVEL DEEP READ BUFFER
One-level deep read buffers can be used in high
performance systems where the data transfer between the
main memory and the CPU is efficiently handled. This can be
accomplished through a sophisticated memory scheme, like
interleaving, and supported by a fast DRAM architecture.
Such a scheme minimizes the transfer rate mismatch
between the CPU and the main memory. One-level deep read
buffers can also be applied in low performance systems where
the penalty in fetching one word at a time is not significant.
a-LEVEL DEEP READ BUFFER
This configuration can be used in a general purpose
system. An 8-level deep write buffer offers the benefit of
effective data rate capture from the R3000/1 to the main
memory. The 8-level Read Buffer is convenient for slow main
memory systems.

7.12

6

USING THE IDT73200 OR IDT73210 AS
READ AND WRITE BUFFERS WITH R3000

APPLICATION NOTE AN-65

--

-..

DATA

ADDRES~

I

R3000/1

M

11-

INSTR.
CACHE

-

--

IL_

DATA
CACHE

--..

....

j

CONT ROL

~

,

CONTROL
STATE
MACHINE

~r

,Ir

WRITE BUFFER

WRITE BUFFER

ADDRESS

DATA

73200

73200

73200

73200

READ BUFFER

73200

: 73200

,r
~

-

MEMORY & I/O

~

2647 drw 22

Figure 7. R3000/1 System with the Read-Write Buffers

A TYPICAL SYSTEM
Figure 7 shows the interconnections among the R3000/1 ,
Instruction and Data Cache, Read/Write Buffers, control state
machine, and the system memory. The read and write buffe rs
are built from multilevel pipeline registers denoted by the lOT
73200. The control state machine represents the logic needed
to drive the read and write buffers.

WRITE BUFFER INTERFACE
A write buffer, as discussed earlier, transfers data from
cache to main memory and provides address bits to select
memory locations. This is illustrated in Figure 8: one write
buffer is dedicated to pass address bits and the other transfers
data to the main memory. Therefore, the write buffer labeled
"address" is activated in both memory reading and memory
writing operations.
As seen in Figure 8, the address path carries address,
tag and Acc type bits. Notice that the write buffer labeled
"Address", is formed by two lOT 73200. The first 73200
captures Address low 0-13 and AccTyp 0,1. The second
73200 captures Adr High 14-29 and Tag 0,1.
The Data path, as shown in figure 8, carries data and parity
bits. The data write buffer uses two lOT 73200. They latch 32
data bits from the cache and transfer them to a memory
location selected by a memory controller. Notice that parity
bits can be generated using the IOT49C465 when data is
flowing from the write buffer to the system memory.

A situation of interest in deep write buffers is the following:
The CPU requests reading data from a memory location that
is about to be updated by the write buffer. The potential
problem is clear: reading data that hasn't been updated yet.
To avoid this problem, write buffer systems use conflict
checking schemes.
A common "conflict checking scheme" is implemented by
comparing addresses of memory locations to be read and
written by the readlwrite buffers. When an address match is
found, a match signal is send to the CPU. This solution may
involve using more hardware to implement such scheme.
Another approach is ''flushing''. To simplify the design, the
write buffer is ''flushed'', i.e., all pending writings are placed in
the main memory before any read buffer operation takes
place. Such is the case in figure 8 where no additional
hardware was needed.
Figure 8 shows the associated control circuitry to drive the
write buffer. Notice that write buffer "data" and AdrHi (14-31)
are clocked at the SYSOUTsignal, whereas AccTyp (0:1) and
adr-Lo(0:13) are clocked at SYSOUT.

WRITE BUFFER CONTROLLER
The write buffer controller is internally driven by two counters: The I-counter selects the load operation for the input to
the 73200. The SEL-counter selects the register to be read in
the 73200 output. The write buffer controller also takes care of
the ''flushing'' scheme.

7.12

7

I

USING THE 1DT73200 OR 1DT73210 AS
READ AND WRITE BUFFERS WITH R3000

APPLICATION NOTE AN-65
ADDRESS PATH

DATA PATH

t
G>o

()o

-lr

~

CPU
CONTROL
PATH

....

~

~

...

:...~

..o~

~

.......u;>

ACCTYPO ....
ACCTYP1

0:0

-<0
"'0 0

113imST ...

SYSOiJT

SYSOUT
WRITE
BUFFER
CONTROL
LOGIC

MEMm ..

L..

IC(O-2)

-

WBCm ...
SELC(O-2)

"

WRITE
BUFFER

L.
~

-..

SYSOUT ...
_WRBOS'i'

~

0

~

-~

SYSOiJT

WRITE
BUFFER

73200

L..
~

" WRITE

BUFFER

~

DATA

~

73200 : 73200

,r

WBFULL

:0

,r

ADDRESS ~ ADDRESS
73200

0
»-l
»

-I»
»0

»»
()o

"

r
:0

, ,~
0

~

,

MEMORY CONTROL PATH

"

ADDRESS PATH

DATA PATH
2647 drw 23

Figure 8. Write Buffer Interface

The PAL equations for the write buffer controller are:
MODULE WB_CONT;
TITLE WB_CONT:
TYPE MMI 16R4:
Inputs:
IC3
SELC3
WBEMPTY
WRACQ
MEMRD
WBFULL
MEMWR
RESET

Table:
XNOT=
LWRNOT:=
Node[pin2]:
Node[pin3]:
Node[pin4]:
Node[pin4]:
Node[pin5]:
Node[pin6]:
Node[pin7]:
Node[pin9]:

LRD
LWR

Node[pin1S]:
Node[pin14]:

LRD
LWR

Node[pin1S]:
Node[pin14]:
Node[pin19]:
Node[pin 12]:
Node[pin13]:
Node[pin18]:

ICE3 XOR SELC3:
LRD AND WBEMPTY AND WRACQ
AND RESETOR LRD AND! MEMWR
AND WRACQ AND! WB EM PTY AND

RESET:
LRD NOT:=

(!WBEMPTY AND !MEMRD AND
LWRAND RESEl) OR (!LRD AND
!MEMRD AND RESEl):

WBCEN NOT =

WBFULL;

ICE NOT =

(!MEMWRANDWBFOiI)
OR(!MEMRD AND !WBEMPTY):

SELCE NOT=

(!LWR AND !WRACQ) OR
(!LRD AND MEMRD):

Outputs:

X
WBCEN
ICE
SELCE

END:
END WB_CONT.

7.12

8

USING THE 10T73200 OR 10T73210 AS
READ AND WRITE BUFFERS WITH R3000

APPLICATION NOTE AN·65

The PAL equations for the I-counter are:
MODULE I-COUNTER;
TITLE ,-COUNTER;
TYPE MMI 16R4;
Inputs;

X
IC
ICE
R3KRST
IC3
IC2
IC1
ICO

Node[pin2];
Node[pin3];
Node[pin4];
Node[pin5];
Node[pin17];
Node[pin16];
Node[pin15];
Node[pin14];

WBFiJIT
WB EM PTY

Node[pin 17];
Node[pin16];
Node[pin 15];
Node[pin14];
Node[pin19];
Node[pin12];

SO
S1
S2

Node[pin18];
Node[pin13];
Node[pin19];

SO
S1
SELC3
SELC2
SELC1
CO
S2
C

Node[pin18];
Node[pin13];
Node[pin 17];
Node[pin16];
Node[pin15];
Node[pin14];
Node[pin19];
Node[pin 12];

SELCO NOT:=

(SELCO AND !SELCE) OR
(!SELCO AND SELCE) OR
!R3KRST;

SELC1 NOT:=

(!SELCO AND !SELC1 AND
!SELCE) OR (SELCO AND
SELC1 AND !SELCE) OR
!R3KRST;

SELC2 NOT:=

(!SELCO AND !SELC1 AND
!SELC2 AND !SELCE) OR
(SELCO AND SELC1 AND
SELC2 AND !SELCE) OR
(!SELCO AND SELC1 AND
!SELC2 AND !SELCE) OR
(SELCO AND !SELC1 AND
!SELC2 AND !SELCE) OR
(!SELC2 AND SELCE) OR
!R3KRST;

SELC3 NOT:=

(!SELC2 AND !SELC3 AND
!SELCE) OR (!SELC1 AND
SELC2 AND !SELC3 AND
!SELCE) OR (!SELCO AND
SELC1 AND SELC2 AND
!SELC3 AND !SELCE) OR
(SELCO AND SELC1 AND
SELC2 AND SELC3 AND
!SELCE) OR (!SELC3 AND
SELCE) OR !R3KRST;

Table;

Table;
ICO NOT:=

( ICO AND !ICE ) OR (!ICO
AND ICE) OR !R3KRST;

IC1 NOT:=

(!ICO AND !IC1 AND !IC1AND
!ICE) OR (ICO AND IC1 AND
!ICE) OR (!IC1 AND ICE) OR
!R3KRST;

IC2 NOT:=

Node[pin 17];
Node[pin16];
Node[pin 15];
Node[pin14];

Outputs;

Outputs;
IC3
IC2
IC1
ICO

SELC3
SELC2
SELC1
SELCO

(!ICO AND !IC1 ABD !IC2
ABD !ICE) OR (ICO AND IC1
AND IC2 AND !ICE) OR
(!ICO AND IC1 AND !IC2 AND
!ICE) OR (ICO AND !IC1
AND !IC2 AND !ICE) OR
(!IC2 AND ICE) OR
!R3KRST;

IC3 NOT:=

(!IC2 AND !IC3 AND !ICE)
OR (!IC1 AND IC2 AND !IC3
AND liCE) OR (lICO AND
IC1 AND IC2 AND lIC3 AND
liCE) OR (ICO AND IC1 AND
IC2 AND IC3 AND !ICE) OR
(lIC3 AND ICE) OR
!R3KRST;
WBFULL NOT = lIC AND IX;
WEMPTY NOT= !IC AND X;

SO NOT =
S1NOT=
S2 NOT =

End;
End I_Counter;

The PAL equations for the SEL-counter are:
MODULE SEL_COUNTER;
TITLE SEL_COUNTER;
TYPEMMI16R4;

(ICO XOR SELCO);
(IC1 XOR SELC1);
(IC2 XOR SELC2);

C NOT = SO AND S1 AND S2;
End;
End SEL_Counter;

Inputs;
SELCE
ICO
IC1
IC2
R3KRST

Node[pin2];
Node[pin3];
Node[pin4];
Node[pin5];
Node[pin6];
7.12

9

II
I

USING THE 1DT73200 OR 1DT7321 0 AS
READ AND WRITE BUFFERS WITH R3000

APPLICATION NOTE AN-65

DATA PATH

t

FJEMRD...

YO-y"

~

CPU

RACJ<'.....

CONTROL~

PATH

~

SELC(0-2) ..

READ
BUFFER
CONTROL
LOGIC

READ
BUFFER

IC(0-3) ..
~

SYSOUr ..

...

DATA

...

73200 : 73200
l~

00-0 31

~ SYSRO
MEMORY CONTROL PATH

DATA PATH
2647 drw 24

Figure 9. Read Buffer Interface

READ BUFFER INTERFACE

Outputs;

When reading from the main memory to the cache, the
R3000/1 sends a memory read signal to the control state
machine, represented in Figure 9 as the Read Buffer Control
Logic. Once the signal has been acknowledged, the R3000/1
places the address, tag, and data size in the write buffers.
Internally, the 73200 registers capture this information at
R3000/1 clock rate with load and output configurations determined by the read buffer controller. Once the address is
available in the address bus, the controller will then drive
memory signals to initiate the memory transfer at memory
clock rate into the read buffer.

LRD
LWR
WB_CLK_DiS
WB_DATA_OE
CMEMRD
CCMEMRD
WRBUSY

Node[pin 15];
Node[pin14];
Node[pin19];
Node[pin 12];
Node[pin13];
Node[pin1B];
Node[pin16];

LWR NOT:=

LRD AND lMEMWR AND
RESET OR lLWR AND
WRACO;
LWRAND lMEMRD;

Table;

LRD NOT:=

READ BUFFER CONTROLLER

WRBUSY NOT:=

The read buffer controller monitors the flow of data within
the Read Buffer by programming the 73200 internal registers
to the appropriate load mode and memory clock frequency_
Finally, the controller selects the output registers at such
speed to match the R3000/1 frequency.
The PAL equations for the read buffer controller are:

lMEMWR OR lWB_CLK_DIS
AND WRACQ OR lMEMRD
AND CCMEMRD;
LRD AND lMEMWR OR
{need to be inverted}
lLWRANDWRACO;

MODULE WIRB_CONT;
TITLE W/RB_CONT;
TYPE MMI 16R8;

Inputs;

CMEMRD NOT :=
WRACO
MEMRD
MEMWR
RESET
LRD
LWR
WB CLK_DIS
CMEMRD
CCMEMRD
WRBUSY

lMEMWROR
lWRBUSY AND WRACO
OR lMEMRD;

Node[pin5];
Node[pin6];
Node[pinB];
Node[pin9];
Node[pin15];
Node[pin14];
Node[pin19];
Node[pin 13];
Node[pin 1B];
Node[pin16];

CCMEMRD NOT:=
End;
End W/RB_CONT;

lMEMRD;
CMEMRD;

CONCLUSION
As the speed of the processor increases, write and read
buffers must also become faster and deeper. The high-speed
multi-level pipeline register lOT 73200 meets that challenge
by providing a fast and flexible data path to suit various highspeed RISC and CISC processors_

7.12

10

G®
Integrated Device Technology, Inc.

USING IDT73210 AS
READ AND WRITE
BUFFERS WITH R3000

APPLICATION
NOTE
AN-GS8

By V. S. Ramaprasad

INTRODUCTION
In this application note, the design of one deep read and
one deep write buffer to be used in an R3000 system is
described with boolean equations and timing diagrams. The
boolean equations are for the control signals of the read and
write buffers and the main memory interface. This control
logic can be implemented with any PLD. The syntax chosen
to describe these equations is simple and it is not associated
with any PLD programming software. The timing diagrams
explain the various states during the operation of one deep
read and write buffers. Also described in this application note
are the other possible configurations of implementing read
and write buffers with IDT7321 as. These components can be
used as two deep read and one deep write, and one deep read
and two deep write buffers. Beforetheapplication is presented,
the features of 73210 are described and a summary of the
memory interface Signals of R3000 is given.
R3000 based systems require readlwrite buffers between
the CPU and the main memory due to memory bandwidth
mismatch. The main memory system supplies the instructions/
data through a read buffer. The CPU makes the data updates
to the main memory through a write buffer. The speed
differences between the CPU, the caches and the main
memory that typically exist in many systems demand the use
of at least one level deep read and write buffers. The use of
these buffers isolates the caches from the rest of the memory
system. They also limit the physical length of the address and
data lines and serve as drivers to the rest of the system.
The gain in performance by increasing the depth of the read
and the write buffers is completely dependent on the application
program being executed. By modeling memory subsystems
with different depths of read/write buffers (using the System
Programmer's Package tools for the R3000) and running the
application program on the model, the designer can make the
trade-off between the cost and the depth of the buffers. For
high performance systems with sophisticated main memory
schemes like interleaving, and for systems with fast DRAM
architectures like Page Mode, or Static Column Mode, a one
deep read buffer might satisfy the transfer rate of the processor.

©t990 Integrated Device Technology. Inc.

For low performance systems, where the penalty of fetching
one word at a time is not Significant, and for applications with
infrequent successive writes, a one deep write buffer might
also deliver optimal performance.
In systems where one-level deep read and write buffers
proved to be sufficient, a bidirectional register can be utilized
to serve as both read and write buffers. The 8-bit bidirectional
register, IDT7321 a, with parity checking and parity generation
is an ideal candidate for this purpose. This bidirectional
register also allows the designerto build a two-level deep read
buffer and one level deep write buffer, or one-level read buffer
and two-level write buffer configurations. Using IDT73210
reduces the parts that are needed for parity generation. Also,
by clocking in the lower address bits and the higher address
bits with separate clocks, the designer can eliminate latching
the address low bits.

IDT73210 FEATURES
Figure 1 shows the features of IDT7321 Owith all the control
signals and data paths. It is a bidirectional buffer with separate
output enables and clock enables. Data is registered with the
same clock in both directions. There is a single data path from
port A to port B. The 8-bit data and the parity bit are clocked
through register X. The POLARITY signal is used to select
even or odd parity generation. Even parity checking is done
on the data, and a parity error is indicated by PERRA. The 8bit data and the parity bit are enabled through a tri-stateable
buffer to port B.
There are two data paths from port S to port A. A multiplexer
controlled by SEL selects a path. Even parity checking is done
in both the paths and parity error is indicated by PERRS. The
first path is through latch Wand register Z. In this path bit W8
is complemented by POLARITY to yield either even or odd
parity.The second path is through registers Y & Z and even
parity is generated on the data. The two registers in the
second data path provide the user with two- level deep
buffering. The 9-bit output is enabled through a tri-stateable
buffer to port A.

690

7.12
11

7

USING THE IDT73200 OR 1OT73210 AS
READ AND WRITE BUFFERS WITH R3000

APPLICATION NOTE AN-65

A 0-8

AOE

t
r

1>

AEN
CP

hr

REGX

I

REGZ

1 {3

POWER
SUPPLY

I

I

I

i9

I

',9

MUX

I

9

9

I

,
Even/Odd
Even Parity
Parity
Check
Generation

'" 9

Complement
Even Parity
Even/Odd
Check
Parity

I

i
MUX

~

I-

L~

'['9

Generate
Even
Parity

~ REGyi

t

I

SOE

Even Parity
Check

QY0-8

ILATCH wi

rY

J

'['9

W0--8

PERRA

Vee GN00--2

4:

QX0-8

POLARITY

PERRS

I

t

LE

1

J

ox

t

I

SEL

2647 drw 01

Figure 1. 1OT73210

7.12

12

USING THE 1DT73200 OR 1OT73210 AS
READ AND WRITE BUFFERS WITH R3000

APPLICATION NOTE AN-65

AdrLo (0:17) <

-y

AcTyp2

....

Data (0:31)
MemRd

AcTyp1
AcTypO

v>

Tag (16:31)

RdBusy

IDT79R3000

BusErr

MemWr

CpCondO

~

WrBusy

XEn

SysOut

2647 drw 02

Figure 2. Memory Interface Signals

IDT79R3000 MEMORY INTERFACE
The R3000 has interfaces to the main memory through the
asynchronous memory bus. The output signals indicate the
n~ture of operation that the R3000 is performing. The input
slg.nals are used to indicate the termination of a stall, block
refills, and to cause exception processing.
The figure above shows the signals used to interface to
main memory. The address bus is split into AdrHi and AdrLo.
The AdrHi bus is also used as the Tag bus for cache reads and
therefore is shown as bidirectional.
MemRd: This signal indicates the entry into the stall on
a read operation. It is an active-low output signal. This
output signal of the R3000 is used by the state machines
to enter a read state and signal the memory system that
the R3000 accepts data from the supplied 32-bit address.
For one word refill, MemRd is deasserted by the R3000
one cycle after the RdBusy signal is deasserted indicating
that the required data is ready. The deassertion of
MemRd signals the end of a read stall. MemRd stays
asserted during the entire stall cycles.
RdBusy: This input signal to the R3000 is used to enter
and terminate read stall cycles. The deassertion of
RdBusy terminates stall cycles and the R3000 enters a
fixup one cycle later during single word loads or it enters
refill c~cles in case of multiple word loads. RdBusy
assertion and deassertion is sampled by the R3000 in
phase 1 of the clock cycle.
XEn: This active-low, output signal is used to enable the
output of the read buffer in refill and fixup cycles.
MemWr: This output signal is asserted low for store
operations. Unlike MemRd, this signal is active for only
one cycle as are the associated data and addresses.
MemWr is used to enter a write state.

7.12

WrBusy: In order to create a write stall, this input signal
to the R3000 has to be asserted low during the cycle in
which MemWr is asserted. The deassertion of WrBusy
terminates a write stall and the R3000 enters the fixup
cycle. In the fixup cycle, the last write operation during
which WrBusy was asserted is repeated. WrBusy is
usually tied to the signal that indicates the write buffer is
full. WrBusy assertion is sampled by the processor in
phase 2 and the deassertion is sampled in phase 1 of the
clock cycle.
.
SysOut: This is the clock output of the 79R3000 and is
the clock frequency at which the R3000 is rated.
CpCondO: The condition of this input signal to the
R3000 in stall cycles determines if the processor will do
a single word read or a multiple word read.
BusErr: This input signal is provided as a mechanism
to create an exception in the R3000 and as an aid to
escape from interminable stall cycles.
AccTypO: This output signal has three functions. During
cached reads it indicates whether there was a data
cache miss or an instruction cache miss. This information
is useful if the block refill size is different for data and
instructions. During uncached reads it is used with
AccTyp1 to indicate the size of the data being read.
During writes it is used along with the AccTyp1 to
indicate the size of the data being written.
AccTyp1: This output signal is undefined for cached
reads. For uncached read operations and for store
operations, AccTyp1 along with AccTypO, indicates the
size of data transfer.
AccTyp2: AccTyp2 is undefined for store operations
with stall cycles. For load operations, it is high for cached
operations and low for uncached operations. During run
cycles, this line indicates whether there is any data
transfer during the second phase.

13

I

.

USING THE 10173200 OR 10173210 AS
READ AND WRITE BUFFERS WITH R3000

APPLICATION NOTE AN-55

USING IDT73210s
Figure 3 shows the application of the 7321 Os as one-deep
read and one-deep write buffer. Four 73210s are used to
transfer the 32-bit data and the associated four parity bits. On
the address bus, four 73210s are used to pass the 32-bit
physical address and the access type bits(0:1) to the main
memory. Port B of the 7321 Os are connected to the processor
side, and Port A of the 7321 Os are connected to the memory
side.
The read and the write data paths are explained in Figures
4 and 5. In this design, one single set of four IDT7321 Os serve
the function of read and write buffers. Also, a set of four
IDT7321 Os are used to capture the addresses during read and

write operations. The timing diagrams point out the control
signals that resolve any conflicts in the use of these buffers.
The control logic, described in the following sections, can
be implemented with any PLD that matches the processor
speed. To interface with the main memory, signals are
defined to make a request to the main memory (MREQ), to
specify a read or a write operation to the main memory (MRD,
MWR), and a signal from the main memory to indicate the
completion of read or write operation (CYCEND).
The memory interface signals from the R3000 are used by
the PAL state machine inorder. to generate controls to the
buffers and the main memory. The RdBusy, WrBusy, MREQ,
MRD, MWR, and the clock and data output enables for the
73210s are generated by the state machine.

IOT79R3000
/ 32 + 4

Data

/

.--

WrBusy
MemWr

c:x:

(4)

"350 MHz bandwidth.
3. High impedance scope probes.

WHEN IS THE PCB TRACE TRANSMISSIVE?
As a general statement, a PCB trace looks like a transmission
line for fast edge rates of the transmitted signal. To quantify this, a
commonly used rule of thumb is:

TREA T A PC BOARD TRACE AS A TRANSMISSION LINE IF

T.s.... 2L x Tt.

Method
a. If the source impedance of the pulse generator is unknown, it
can be easily obtained by observing the unloaded output
waveform of the pulse generator, and then loading the pulse generator output with a resistance that will halve the amplitude of the
original signal. The value of this load resistance is the source impedance (Rs) of the pulse generator.
b. Connect the pulse generator and the oscilloscope to one end
of the PCB trace. Use a minimum of 9 inches of PCB trace. Insert
the devices that will form the distributed load on the PCB trace. See
Figure 5.

In this equation, T = output transition time (rise or fall time)
TL= loaded transmission delay per unit length.
TL = To for the point-to-point case
l = length of the PCB trace

Example
Consider the loaded transmission line in the example cited
above. If the clock driver has an output transition time of 5 ns, the
length at which the PCB trace should be treated as transmissive is
given by:
l = T 12TL = 51 (2 x 0.37) = 6.8 inches.
It is clear that. with slower edge rates a driver can drive longer
traces without transmission line effects. The table in Figure 4
shows the limiting signal line length for different logic families
based on tvpical edge rates for each of the families and~­
loaded signal traces.

TO lOADS (IC INPUTS)
LOGIC FAMILY

SIGNAL LINE LENGTH"
(INCHES)

lS

25

S,AS

11

F,ACT

8

AS,ECl

6

FCT, FCT A

5

Figure 5. Test Set-Up for Measuring PCB Trace Parameters

c. Set up the pulse generator to obtain a 5V amplitude square
wave of 1 MHz frequency. Adjust the rise and fall times to get30 ns
(10% to 90%). These slow edges ensure that the PCB trace behaves like a lumped load and not like a transmission line. Overshoots and undershoots on the waveform are avoided. Record the
amplitude (Vs) observed on the oscilloscope under these conditions as shown in Figure 6A.
d. Now change the setting on the pulse generator to get the
fastest rise and fall time. Observe the high to low transition on the
oscilloscope. Note that there is a step in the output transition as
shown in Figure 6B. Record the amplitude of the first segment of
the output transition (VI) and time interval between the start of the
first transition and the start of the second transition (2l x TL).
e. Determine the characteristic impedance of the loaded PCB
trace (ZL) by the formula:

·Length above which the signal trace looks like a transmission line.

Figure 4. Signal line Length vs Logic Family

This table shows that, as we go to faster logic devices, it becomes more critical to understand the transmission-line effects.
Note that the signal lengths given in the table are not guarantees
for any logic family. The actual limiting signal length is a function of
trace and board characteristics, trace loading and the edge rates of
individual devices in any logic family.

MEASUREMENT OF PCB TRACE
PARAMETERS

ZL = Rs x [VI I (Vs - VI)

Since both ZL and TL depend on board layout and loading, a simple practical method of determining these two parameters is use-

7.16

1

3

CHARACTERISTICS OF PCB TRACES

APPLICATION NOTE AN-49

v

,~

V

a

V[__________________

Time (ns)
Measuring Vs with Slow Edge Rate

2L·Tl

Time (ns)
Measuring Vt and TL with Fast Edge Rate

Figure SA.

Figure 58.

device may not respond to the signal at the driving end (see Figure
6B) until the reflected wave reinforces the signal after a turnaround delay along the PCB trace. This implies that if a driver is
driving a PCB trace from one end, the receiver nearer to the driver
will respond afterthe receiver at the far end of the PCB trace. Such
skew may be unacceptable in certain conditions.
The relative values of trace impedance and the load impedance
at the far end also determine the amount of reflection and hence
the overshoots and undershoots on the waveform. By understanding the implications of transmissive traces, a designer can choose
the right termination and drive capability of the driving circuit to derive the maximum benefit.

The line propagation delay to the end of the trace is given by T L.

Example
In a test performed on a 9 inch trace, we get Rs = 45 n, VI = 2.8 V
and 2L x TL = 6 ns. Then,
ZL

= 45 x [ 2.8 I (5 -

2.8)

~

1

=57n.
TL = 61 (2 x 9)
= 0.33 ns per inch

THE IMPORTANCE OF PCB TRACE
CHARACTERISTICS

SUMMARY

The relative values of source impedance (Rs) of the driving circuit
and the loaded characteristic impedance of the transmission line
(ZL) determine the effectiveness of driving transmission lines. As
Rs increases for a given ZL, the amplitude of the transmitted component of the waveform (VI) decreases. If the transmitted wave
does not cross the threshold of a receiving device, the receiving

This application note describes the effect of fast edge-rates on
the behavior of PCB traces. A simplified method for measuring the
trace parameters in a given application environment is shown. The
procedure discussed here can be extended to fully loaded backplanes.

I
I

7.15

4

APPLICATION
NOTE
AN-50

SERIES TERMINATION

(~5
.;:;; dt

Integrated Device Technology, Inc.
By Suren Kodical
Series termination is one of several forms of terminating transmissive lines. In this bulletin we discuss the pros and cons of series
termination and the effect of termination impedance on simultaneous switching noise (a.k.a. Ground Bounce).

SERIES TERMINATION
Figure 1 shows a typical case of a series terminated driver connected to a load via a PCB trace.

i'/.

WHY TERMINATE?
With the constant push for higher speeds, particularly in the area
of standard logic and bus interface products, system designers
have to deal with devices with fast edge rates. At the same time,
high packing density of multi-layer boards results in PC board
traces with low loaded impedance and long transmission delays.
This combination of fast edge rates and low transmission line impedance requires the system designer to pay careful attention to
PCB design in order to maximize the benefits of today's highspeed logic. As more and more devices on the boards go to CMOS
technology, typical nets consist of outputs with fast edges looking
into transmission lines with some distributed capacitance along
the line or lumped capacitance of CMOS IC inputs at the end of the
line or a combination of both. In the absence of some form of termination, overshoots and undershoots on the signal can impose
bandwidth limitation on the system, or subsystem due to settling
time requirements or, even worse, can cause false triggering and
data loss.
Termination of transmission lines is the time-honored method of
improving signal quality. There are several forms of termination:
a. Parallel or shunt termination: a single resistor terminated
to either Vee or GND at the end of the PCB trace. For backplanes, termination is provided at each end.
b. Series termination: a single resistor is connected between
the output node of the driver and the PCB trace or any other transmission line being driven.
c. Thevenln termination: two resistors form a potential divider
at the far end of the transmission line. The junction of thetwo resistors goes to the transmission line and the two ends typically go to
GND and Vee. This type of termination is commonly used on backplanes at both ends.
d. RC termination: an R-C series combination is connected
between the transmission line and GND at the far end.
Each of the termination schemes listed above has certain advantages and disadvantages. A detailed discussion of the relative
merits of these schemes will be part of a separate application note.
In this issue, we will focus on SERIES TERMINATION.

R: •

PCB TRACE Zo

~\. ~To--'

@

LOADS

L- SERIES TERMINATION

DRIVER

Rs
Figure 1.

The effective output impedance of the driver is now the sum of
device source impedance (Ro) and the series terminating resistance (Rs). This modified output impedance of the driver comes in
series with the characteristic impedance (Zo) of the PCB trace and
forms a potential divider for the incident signal. Therefore, the signal that propagates down the trace is a fraction of the "open-circuit" signal at the driving end. The magnitude of the transmitted
wave is given by the following equation:
VI

=

Vs [ Zo I (Ro + Rs + Zo)

1................ (1)

This equation shows that, as the total source impedance approaches the characteristic impedance of the line, approximately
half of the incident wave will be transmitted to the other end of the
trace. Since the load impedance is much larger than Zo due to the
high input impedance of the CMOS devices, most of the transmitted wave is reflected. As a result, overshoots and undershoots on
the signal are minimized at the receiving end. If Ro + Rs is much
smaller than Zoo a larger portion of the incident wave is transmitted
down the trace. Since most of it is reflected, such a condition will
cause overshoots and undershoots at the receiving end. Figure 2
shows the effect of series termination under prefect matching (total
source impedance equals trace impedance).

OPEN-CIRC:'UiT"\
SIGNALAT
1\

o

Jr---

SENDING-E NO"""""'
SIGNALAT
B
CW
RECEIVING END
SIGNAL AT

........
To

,

To

To

To

/

\

@
Figure 2.

© 1989 Integrated Device Technology, Inc.

7.17

Printed in the U.S.A.

11/89

APPLICATION NOTE AN-50

SERIES TERMINATION

Reworking equation #1, we get:

The example shown highlights some important points:
1. For the best signal quality, the series terminating resistor
should be chosen such that the total source impedance (Ro + Rs) is
close to the characteristic impedance of the PCB trace. It is not essential that the two quantities match exactly. It is, however, important to ensure that the total source impedance is not greater than
the trace impedance. Otherwise, multiple reflections may be
needed to obtain the entire signal transition at the receiving end.
2. The waveforms in Figure 2 clearly show the effect of series
termination on the waveform at both the sending end A and receiving end B. For a perfectly matched condition, the signal will attain
the final value at the sending end after a round-trip delay ( 2To ),
although it will attain the final value after one transmission delay
(TD) at the receiving en'd. If loads (several IC inputs) are distributed along the PCB trace and are driven by the driver at one end,
this condition results in signal skew which may be unacceptable.
Therefore, series termination may not be the most suitable form of
termination for distributed loads. Of course, the ratio of source to
trace impedance can be adjusted to ensure that the threshold of
the receiver is crossed on the first incidence of the transmitted
wave, but this is normally at the expense of some undershoot and
overshoot during signal transitions.
3. There is no limit to the number of lumped loads (as shown in
Figure 1) that can be used, provided that the total DC loading does
not reduce the static noise margin because of a voltage drop
across the series terminating resistor. This implies that series termination is well-suited to drive inputs of CMOS devices because
of their very low input current requirements. The primary limitation
to the number of CMOS loads is the additional delay due to the total input capacitance being driven.
4. When series termination is used with lumped loads, the distance between the indvidualloads should be kept to a minimum. If
the loads being driven are spread apart, a preferred method of driving them from one source is to make several groups of loads and
drive each group from the driving source via individual transmission lines with their own series termination resistors. The driver
should of course be capable of handling this additional transmission line loading.
5. It is clear that the series termination does not add any power
dissipation to the system. It is, therefore, the preferred form of termination if power dissipation is a key consideration.
6. Series termination adds flexibility to the design in that the termination values can be tailored to suit a variety of trace characteristics and timing requirements.

Therefore,
Rs = Zo [ VIL / (VOH - VIL) j- Ro ............... ( 2 )
Using the values for Vs and VI and for a device source impedance of 6 ohms, the maximum value of series termination resistance which will assure incident wave switching is given by
Rs = Zo [0.8/ (4.8 -

o. ) ]- 6

= (0.2Zo - 6) ohms

For example, if the PCB trace impedance is 70 ohms, the maximum value of series termination resistance is 8 ohms to assure incident wave switching. A similar consideration for the low to high
transition yields the expression:
Rs

=

Zo [ ( VOH - VIH) / VIH j- Ro .............. ( 3 )

For a VOH = 4.8 V, VIH = 2.0 V and a source impedance of 25
ohms in the logic high state, the maximum value of series termination resistance to assure incident wave switching is,
Rs = (l.4Zo - 25) ohms
Again, if the PCB trace impedance is 70 ohms, the maximum
value of Rs is 73 ohms. This indicates that the high to low transition
is the worst case.
The above example shows that a requirement for incident wave
switching will impose severe restrictions on the series termination
resistance due to the high to low switching case. Since the termination value is much less than the trace impedance, a certain
amount of overshoots and undershoots are to be expected on the
output waveform at the far end of the PCB trace. In effect, the incident wave switching requirement is in conflict with signal integrity
for FCT logic devices with rail to rail output switching when using
series termination. If signal integrity is the primary consideration,
then the series termination has to be chosen to match the trace impedance. However, signal skew has to be tolerated when driving a
transmission line with distributed loading. Alternatively, series termination should be limited to driving lumped loads at the far end of
the transmission line (PCB trace).
In high-speed switching circuits, series termination offers a n - I
other advantage. When driving predominantly capacitive loads,
the series resistor serves to limit the peak current in the output
pUll-down transistor and therefore the resultant dildt in the parasitic lead and bond wire inductance. This has the beneficial effect
of limiting the amount of ground bounce (induced by the L.dildt effect) as a result of simultaneous switching of high drive outputs.

SERIES TERMINATION WITH FeT DRIVERS
Like most TIL-compatible drivers designed to meet the standard DC specifications, the FCT output buffers offer different output impedance in the logic LOW and HIGH states. Typically, the
output impedance is 6 ohms in the LOW state and 25 ohms in the
HIGH state. Since the internal thresholds of all TIL-compatible
devices (independent of technology) are with reference to GND
and the noise immunity is normally worse in the logic LOW state, it
is important to consider the logic LOW state and the high-to-Iow
transitions when evaluating the effect of terminations.
First, let us consider the requirements for first incident wave
switching. The aim is to cause enough voltage swing on the first
part of the transmitted wave to cross the threshold of a receiving
device close to the driver. For a typical VOH of 4.8V with CMOS
P-channel pull-up transistors and specified VIL = 0.8 V for the receiver, the required amplitude of the incident signal is VI = VOHVIL = 4.8 - 0.8 = 4 V. The open circuit swing is Vs = 4.8 V.

SUMMARY
Series termination is an effective method for minimizing overshoots and undershoots on signals with fast edges and for reducing the amount of ground bounce caused by simultaneous switching. An understanding of the device output characteristics, particularly the output impedance values, is required to properly determine the value of series termination in order to assure incident
wave switching.

7.17

2

G
;: t t

~:; cIt

APPLICATION
NOTE
AN-51

POWER DISSIPATION IN
CLOCK DRIVERS

Integrated Device Technology, Inc.
By Suren Kodical
Power dissipation in switching circuits is discussed in this bulletin, particularly with reference to CMOS clock driver circuits. The
IDT54/74FCT244 octal buffer is used as an example to compare
the power supply current in CMOS, bipolar and bipolar-based BiCMaS technologies over a wide range of operating frequencies.

~
First, we need to determine the Cpo for the device. Since Cpo =
IccoN in pF if Iceo is expressed in /lA/MHz, we can determine Cpo
using the max. limit specified for Icco in the data sheet. Therefore,
Cpo = 250 /5.5 = 45 pF

POWER DISSIPATION COMPONENTS

When the device is loaded with 30 pF capacitance per output, the
dynamic dissipation component increases due to load. The loaded
value is given by,

There are two components of power dissipation in integrated circuits. One is the steady-state component. This is the dissipation
when all inputs are held at some fixed voltage level. The other
component is frequency dependent and is generally referred to as
the dynamic component.
In CMOS and CMOS-based BiCMOS circuits, the steady-state
component is further divided into two sUb-components; the quiescent power supply current (Icc) primarily due to device leakage
and the quescent power supply current when inputs are at TIL
high level (~Icc). This latter component applies to circuits with TIL
compatible inputs. In bipolar and bipolar-based BiCMOS circuits,
no such distinction is made and it is customary to specify power
supply current for a given logic state on the output(s).
The dynamic component of power dissipation (Icco) is dominant
in CMOS circuits because most of the power is dissipated in moving charge in the parasitic capacitors of CMOS gates. Therefore,
the simplified model of a CMOS circuit consisting of several gates
looks like one large capacitor which is charged and discharged between power supply rails. For this reason, a parameter called Cpo
(power dissipation capacitance) is often specified as a measure of
this equivalent capacitance and is used by the designers to estimate the dynamic power supply component. In the bipolar technology, the dynamic component is generally very sma" in comparison with the steady-state component because internal voltage
swings are small.
Since power supply parameters are traditionally specified under
"unloaded" condition, a comparison of power dissipation for a
given device type (FCT244 with F244, for example) based on data
sheet numbers alone can be misleading. For a true "apples-toapples" comparison, the effect of capacitive load on the device
should be taken into consideration. This is particularly true in the
case of clock drivers which drive heavy capacitive loads and operate at high frequency. Under these conditions, the dynamic power
dissipation component due to output loading could be significant in
both bipolar and CMOS circuits. This is illustrated in the following
section by using the '244 Octal Buffer as an example.

Iceo ( loaded) = { (Cpo + Cl) / Cpo} Icco

={ (45 + 30) /45 } 250 /lA / MHz / bit
= 0.42 mA / MHz / bit.

When a" eight outputs are switching simultaneously, the total
Icco (loaded) is 3.3 mA/MHz.
If quiescent power dissipation is ignored, the above equation can
be used to determine the total power dissipation at any frequency
when the input levels are CMOS compatible. For the case where
the inputs are driven from a bipolar TIL device, the ~Icc component needs to be added in order to obtain the total power dissipation. Assuming a 50 duty cycle, for ~Icc (max.) of 2 mA, this static
Icc component is 8 mA. Figure 1 shows the power dissipation versus frequency for both conditions.

F244
The specified power dissipation is ICCl = 90 mA and ICCH = 60
mAo For a 50 duty cycle, the steady-state dissipation is 75 mA. In
addition, the dynamic dissipation component appears due to the
external load capacitance and the output pin capacitance of the
device. For Cl = 30 pF and COUT = 10 pF (assumed), the dynamic
component can be derived:
Icco (loaded) = 40 pF x (4.3 V - 0.3 V) in /lA/MHz.
= 160 /lA / MHz / bit

where the 4.3 V - 0.3 V represents the voltage swing (for Vcc =
5.5V) on the total load capacitance. For 8 outputs switching simultaneously, Icco is 1.28 mAl MHz. The total dissipation as a function of frequency is also shown in Figure 1.

BCT244
The BCT family from TI is developed with a bipolar-based
BiCMOS process. Therefore, the power dissipation characteristics are similar to F244. The steady-state dissipation is 57.5 mA
for a 50 duty cycle. The dynamic component of the dissipation is
1.28 mA/MHz. The total power dissipation versus frequency is
again shown in Figure 1.

'244 Example
Considerthe '244 as a clock driver with 30 pF load on each of the
8 outputs, operating at room temperature and Vcc = max. Power
dissipation of lOT's FCT244 is compared with F244 (FASP.4) and
Tl's BCT244. Data sheet numbers are used where applicable.

© 1989 Integrated Device TechnOlogy, Inc.

7.18

Printed in the U.S.A.

1"/89

APPLICATION NOTE AN-51

POWER DISSIPATION IN CLOCK DRIVERS

than that of BCT and F families, even under heavy capacitive
loading.

The graph in Figure 1 shows that over a wide range of frequencies the power dissipation of FCT family of circuits is much less

120

100

80
TOTAL

Icc
(rnA)

60

I ECT244 I
(TTL LEVEL INPUTS)
40

20

o

5

10

15

20

25

FREQUENCY (MHz)
Figure 1. Total Icc vs Frequency
method can be extended to any other product and can be used to
determine realistic power consumption if the loading and effective
operating frequency can be estimated for each device.

SUMMARY
A simple method for calculating "real" power dissipation in an operating environment is shown by using '244 as an example. This

I
I

7.18

2

APPLICATION
NOTE
AN-52

FCT OUTPUT STRUCTURES
AND CHARACTERISTICS

~
;: ~; dt

Integrated DevICe Technology, Inc.
By Suren Kodlcal

ration is designed to give a resistive characteristic during the LOW
to HIGH transition at the output.

INTRODUCTION
The FCT family of products has gone through an evolution in
terms of die size, process technology (critical dimensions) and circuit implementation. Originally, the family of products was derived
from the Z-step gate arrays ("4004" gate array for small gate count
and "8000" array for large gate count). Later, a "shrunk" version of
the smaller array was developed to obtain performance improvement. This array is called the V-step. Recently, some of the high
volume runners have been "customized", i.e. redesigned to minimize the die size and get some performance improvement with a
more efficienttopology. These customized versions are called the
W-step devices. The current FCT portfolio consists of a mix of Z, Y
and W step devices. This bulletin describes the output structures
used in different steppings and the corresponding output characteristics for the logic HIGH and LOW states.

"4004" Z- STEP OUTPUT BUFFER
The schematic fot the buffer used in the "4004" Z step devices is
shown in Figure 1. This output consists of an N-<:hannel "sink"
transistor which turns on in the logic low state at the output and
maintains a logic low voltage close to GROUND for normal loading.
The pull-up or "source" circuit consists of a combination of a Pchannel transistor, an N-<:hannel transistor and an NPN bipolar
transistor with a series current lim iting resistor. This circuit configu-

Figure 1. Step Output Structure

The output V-I characteristics for the Z step output structure in
the logic HIGH and LOW states are shown in Figures 2A and 28,
respectively.

(VOUT)

o

250

5

200
-50
150
-100

(mA)
(mA)

100

-150
50
-200

o

2

-250

3

4

5

(VOUT)
Figure 2B. "4004" Z Step Logic "Low" Characteristics

Figure 2A. "4004" Z Step Logic "High" Characteristics

state, the output characteristic is that of a large N-<:hannel pulldown transistor. Note that the characteristics shown in Figure 2
represent typical process parameters at 25°C.

The output characteristic in the logic HIGH state is dominated by
the current limiting resistor in series with the NPN pull-up transistor. As the output reaches the Vee rail, the output characteristic is
primarily influenced by the P-<:hannel transistor. In the logic LOW

©

1989 Integrated Device Technology, Inc.

7.19

Printed in the U.S.A.

11/89

1

FCT OUTPUT STRUCTURES AND CHARACTERISTICS

APPLICATION NOTE AN-52

V-STEP OUTPUT BUFFER
The circuit schematic for the Y step output buffer is shown in Figure 3.

Figure 3. V-Step Output Structure

This output structure is designed to get shorter propagation delays. The output characteristic in both HIGH and LOW states is
non-linear as shown in Figures 4A and 4B. below.

(VOUT)
3

4

5

250
200

150
-100

(mA)

(mA)

100

-150
50
-200

a

-250

2

3

4

I

5

(VOUT)
Figure 4A. V Step Logic "High" Characteristics

Figure 48. V Step Logic "Low" Characteristics

W STEP & "8000" Z STEP OUTPUT BUFFER

structure consists of a parallel combination of P---+---1

INPUT
CIRCUIT

OUTPUT
BUFFER

INPUT

GNO

I

Figure 1. Fer logic with Parasitic Diodes

FCT and AHCT inputs thus permit power down operation on the
input side.
An FCT or AHCT device in the power-down mode can easily
drive TTL-compatible inputs or 1/0 ports. because the TTL-compatible inputs normally demand negligible input current in the logic
high state.

POWER-DOWN OPERATION
Consider the case where an FCT or AHCT device operating in
the power-down mode (say at a Vee of 3 volts) is driven from another device operating from a higher Vee. Because of the absence
of a diode clamp to Vee. there is no current flow from the driving
device into the low voltage power supply through the input pin. The

© 1989 Integrlled Device Technology. Inc.

7.20

Printed in the U.S.A.

11/89

I

POWER-DOWN OPERATION

APPLICATION NOTE AN-53

operation when the output of a device which is powered down is in
the high-impedance state and the bus to which this device is tied is
driven by another device operating from a higher Vee (see Figure
2).

LIMIT ATIONS
The presence of a diode from the output pin to Vee as shown in
Figure 1, however, imposes certain limitations in the power-down

BUS

Vee (POWER DOWN)

Vee (NORMAL)

GND
OUTPUT IN HI-Z STATE

OUTPUT IN HIGH STATE

Figure 2.

port consists of an input node physically connected to an output
which can be put in high-Z state when the port is to be used as an
input. The presence of P-channel pull-up transistor in the output
circuit adds a parasitic diode to Vee at the 1/0 port. Therefore, this
diode will offer a low impedance path to the lower Vee if the driving
device pulls up to the higher (nominal 5V) Vee.

In this case, the output diode to Vee provides a low impedance
path to the lower Vee if the interfacing device output is in the HIGH
state and the logic HIGH voltage is in excess of the power-down
supply rail by more than a forward diode drop. In such an event,
the logic high voltage will be clamped. This is normally not a serious issue if the driving devices have bipolar outputs or N-channel
CMOS outputs with reduced voltage swings. However, if the driving device pulls up to Vee and offers a low source impedance, the
current into the output of the FCT or AHCT device in the powerdown mode can exceed the absolute maximum rating. This situation can be avoided if a current limiting resistor (25 ohms or more)
is used in series with the outputs of the device in power-down
mode.
A similar restriction applies to 1/0 ports of devices such as the
FCT245 and FCT646 when operating from a lower Vee. The 1/0

SUMMARY
The design of the FCT and AHCT input structures facilitates use
of these devices in a dual-rail system or in a power-down mode to
conserve system power or to provide a battery back-up. Although
the design of the output structures imposes a limitation in certain
power-down situations, it can be overcome easily.

7.20

2

G®

APPLICATION
NOTE
AN-54

FCT-T LOGIC FAMILY

:t : :

:1::

dt.

Integrated Device Technology, Inc.
By SUren Kodical

for a given speed. This feature also slows the output edge rates
and minimizes transmission-line effects on PC boards.
Input Hysteresis - Input buffers (TIL-to-CMOS translators)
have been designed to offer 200mV (typical) hysteresis in order to
improve both high and low level noise immunity. This feature decreases propensity for data loss or oscillations in high noise environment and offers immunity to noise superimposed on slow input
signal transitions.
Variety Of Speed Grades - The FCT- T family offers the following speed grades:

INTRODUCTION
Present day systems and board level products have two important characteristics; higher clock rates to obtain improved throughput and higher packing density to reduce space and cost. System
designers are demanding higher speed and user friendliness from
IC vendors 10 cope with the tight timing requirements and with the
switching noise induced by high-speed TIL circuits. As discussed
in the Application Note entitled "SIMULTANEOUS SWITCHING
NOISE', high speed and simultaneous switching noise (particularly Ground Bounce) go hand in hand. For a given speed, less
board-level noise translates into reduced design time, lower rework cost and better quality of outgoing product. Since most standard "glue" logic elements such as buffers, transceivers, latches
and registers are used for their high drive capability and speed,
they can also become the primary source of noise. Therefore, vendors of such high-speed circuits are faced with the challenge of
providing "friendly but fasf' glue logic to the performance-driven
user.
lOT has met this challenge with the FCT- T family of standard
logic which is designed to give the best speed/noise trade-off to
the syste'm designer. This new logic family features reduced output voltage swing and a high current output stage designed to minimize simultaneous switching noise. In this application note, we
discuss this TIL-compatible family in terms of its features and
benefits, product characteristics, performance curves and certain
special features.

FCTxxxT - corresponds to FCTxxx
FCTxxxAT -corresponds to FCTxxxA
FCTxxxBT - corresPondS to FCTxxxB
FCTxxxCT - corresponds to FCTxxxC
The system designer can choose the speed grade necessary for
optimum performance. It is important to note, however, that there
is a strong correlation between the amount of simultateous switching noise and speed. Therefore, designers using higher speed devices should pay careful attention to board layout, termination,
decoupling and package selection in order to get the maximum
benefit.
Compatibility - The FCT- T logic family is compatible with all
other TIL compatible logic families (AS, ALS, FAST, BCT, etc.).
The reduced output swing makes the FCT-T outputs look very
much like standard bipolar outputs. The static noise margin when
driving from an FCT- T device is the same as that with any bipolar
output device in the logic HIGH state. In the logic LOW state, the
typical static noise margin is greater with the FCT- T family than
with any bipolar logic family because of the absence of a voltage
offset usually seen in bipolar Schottky outputs in the logic LOW
state. Input thresholds are set to be within the 0.8V and 2.0V range.
Power-Off Disable - Certain members of the FCT-T family
are designed to offer the power off/up/down disable feature.
These devices with 3-state control maintain high:-impedance
state at their outputs during power supply ramping and power
down ( i.e., Vee = OV ) if the Output Enable pin is conditioned to
disable the outputs. This feature is attractive, and often essential,
for backplane drivers in applications which require hot insertion.
These applications include on-line transaction systems, factory
floor automation, critical medical life support systems, etc. This
feature is currently offered in double density devices with high
drive capability, since these devices offer board space savings in
backplane environment.
JEDEC Standard 18 Compliance - FCT-T specifications
meet or exceed the requirements of JEOEC Standard No. 18 entitled "Standard for Description of 54n4FCTXXXX, Fast CMOS
TTL Compatible Logic".

WHAT IS FCT-T LOGIC?
The FCT- T family is form, fit and function compatible with the
industry standard FCT family of high-speed, high-drive logic from
lOT. The FCT- T family offers the same speed grades (standard,
A, B and C) as the FCT family while generating much lower level of
noise (particularly ground bounce). It is, therefore, backwardcompatible with the FCT family of products in all applications
where rail-ta-rail switching at the output is not essential. Typical
FCT- T output logic levels are 0.1 V in the logic LOW state and 3.3V
in the logic HIGH state.
The FCT- T family also includes several products with power off/
up/down disable feature. These are intended for backplane driving, especially in applications which require "hot insertion" capability for the boards without interrupting system operation.

FCT-T FEATURES AND BENEFITS
The key features of FCT- T family are described below:
TTL Level Outputs - The output pull-up circuit has been modified to offer a quiescent output HIGH level of about 3.3V, similar to
most bipolar and BiCMOS output stages. This feature makes
FCT-:-T truly compatible with existing bipolar and BiCMOS functions and thus offers an attractive low-power alternative without
any performance penalty.
Ground Bounce Control - The output pull-down circuit has
been modified to control the rate of build-up of current in the "sink"
transistors so that the Lgdi/dt effect is minimized (Lg is the total inductance in the ground return path) and ground bounce is reduced

© 1989 Integrated

Device Technology, Inc.

FCT-T CHARACTERISTICS
In this section, we discuss various characteristics of the FCT- T
family. This information is offered to the system designer to understand the operation of a device, boundary conditions and interface
requirements in terms of transmission line driving.

7.21

Printed in the U.S.A.

1

11/89

II
I

APPLICATION NOTE AN-54

FCT-T LOGIC FAMILY

DC CHARACTERISTICS TABLE
Commercial: TA = O°C to +70°C; Vee = 5.0V ± 5%
Military: T A = -55°C to + 125°C; Vee = 5.0V ± 10%
SYMBOL

TEST CONDITIONS(1)

PARAMETER

MIN.

TYP.<2)

MAX.

UNIT

VIL

Input HIGH Level

Guaranteed Logic High Level

2.0

-

-

V

VIH

Input LOW Level

Guaranteed Logic Low Level

V

IIH

Input HIGH Current

IlL

Input LOW Current

Vee = Max.
VI = 2.7V
Vee
VI

10ZH
10ZL

High Impedance
Output Current

= Max.

= 0.5V

-

-

O.S

Except I/O Pins

-

-

5

I/O Pins

-

-

15

Except I/O Pins

-

-

-5

I/O Pins

-

-

-15

= 2.7V

-

-

10

Vo = 0.5V

-

-

-10

Vo
Vee = Max.

Ii

Input HIGH Current

Vee

= Max.; VI = Vee (Max.)

VIK

Clamp Diode Voltage

Vee

= Min.;

los

Short Circuit Current

Vee = Max.; Vo = GND(3)

-

liN =-1SmA

Output HIGH Voltage

Vee = Min.

10H = -SmA COM'L.

VIN = VIH or VIL

10H = -12mA MIL.
10H = -15mA COM'L.

VOL

Output LOW Voltage

VOL

Output LOW Voltage

Vee = Min.
VIN = VIH or VIL
Line Drivers

10L

Il A

IlA

100

Il A

-1.2

V

-225

mA

-60

-

2.4

3.3

-

V

2.0

3.0

-

V

-

0.3

0.55

V

-

0.3

0.5

V

-

200

-

mV

-

0.2

1.5

mA

= -6mA MIL.

10H
VOH

-0.7

IlA

= 4SmA MIL.

10L = 64mA COM'L.

Vee = Min.
VIN = VIH or VIL
Standard,3-State
and SOO Series

10L

= 32mA MIL.

10L = 4SmA COM'L.

VH

Input Hysteresis

Vee

Icc

Quiescent Power
Supply Current

Vee = Max.; VIN = GND or Vee

= 5V

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
Figure 1.

The table in Figure 1 is similar to that for the FCT family of products. Significant differences are summarized below. Then individual parameters are discussed in detail with the aid of circuit schematics and V-I characteristics.

2. Maximum limit of -225mA has been added to the los (Short
Circuit Current) specification to maintain compatibility with other
ITL-output families.
3. Since the output voltage swing is reduced, low drive (300JlA)
specifications for logic HIGH and LOW levels have been omitted.
Similarly, all specifications at Vee = 3.3V have been omitted, as
these CMOS level output specifications are not applicable.

Differences between FCT- T and FCT
1. VOH limit of 2.4 volts is guaranteed at -6mA military and
-SmA commercial for the FCT- T family. The corresponding currents are -12mA and -15mA, respectively, for FCT.

7.21

2

FCT-T LOGIC FAMILY

APPLICATION NOTE AN-54

4. Hysteresis specification has been added to indicate the
amount of nominal hysteresis built into the design.
5. Static Icc specification has been added to maintain compatibility with other TTL data sheets.

INPUT CIRCUIT AND CHARACTERISTICS
The input circuit for the FCT-:Tfamily is shown in Figure 2.

Vee

TO
NEXT
STAGE

INPUT

I
ESD
PROTECTION .CIRCUIT &
INPUT CLAMP

Figure 2. FCT-T Input Stage

The input stage is, in effect, a TTL to CMOS translator. It consists
of (a) Input clamp diode to limit input voltage undershoots to approximately one diode below ground, (b) ESD protection circuit, (c)
Input buffer designed for TTL threshold with a typical 200mV hysteresis and (d) Inverter which interfaces with the following stage.

Hysteresis is achieved by means of a change in the ratio of Pchannel to N-channel transistor areas in the input translator. Typical V-I characteristics of the input stage is shown in Figure 3A and
the typical transfer characteristic is shown in Figure 3B.

INPUT
BREAKDOWN
lin (ilA)

-2

2

3

4

5

6

7

II

8

I

VIN(V)

/
CLAMP
DIODE

=-40
-60

Figure 3A. FCT-T Input V-I Characteristics

because of the forward-biased input clamp diode. Input breakdown voltage is well outside the normal operating limit of Vee
(max).

The input current in the operating input voltage range is extremely low, in the order of nanoamps because of the very high input impedance of the CMOS gate. At voltages greater than one
diode drop below device ground, the input offers low impedance

7.21

3

APPLICATION NOTE AN-54

FCT-T LOGIC FAMILY

VOH

HYSTERESIS
MARGIN

VOUT

(Volts)

VOL

1.4V

1.6V

VIN (Volts)

Figure 38. Input Stage Transfer Characteristics

An important feature of the FCT- T logic family is that all inputs
have hysteresis in the input stage transfer characteristic. Hysteresis increases static noise immunity in both logic states and also
offers immunity to noise superimposed on slow edge-rate input
signals, if the amplitude of the superimposed noise is less than the
hysteresis margin.

distortion of signal propagating through a chain of devices is minimized.
3. For the same High-to-Low edge rate, reduced output swing
would result in improved tpHL because of smaller output voltage
excursion relative to a device with full rail-to-rail output swing. Alternatively, a given tpHL spec can be met with a slower High-toLow edge rate. In the FCT- T family, we have taken advantage of
this latter feature and improved the output circuit to reduce ground
bounce as well as the level of radiated noise (EMI and RFI) caused
by sharp output transitions and fast edges.
4. Less energy is stored in the output load capacitance when
compared with a rail-to-rail swing device. This results in less
ground bounce for the same speed when compared with a rail-torail switching device.

OUTPUT CIRCUIT AND CHARACTERISTICS
The FCT- T output circuit is designed for a nominal voltage swing
of about 3.3V. (In comparison, the FCTfamily output swing is from
rail to raiL) The reduced output swing has certain benefits:

Benefits of reduced output swing
1. The output characteristics of FCT- T logic more closely
match those of the industry-accepted Bipolar and BiCMOS logic
families (AS, ALS, FAST, BCT, etc.).
2. Nominal threshold of any TIL inputs tied to an FCT- T output
is almost in the middle of the output swing. Therefore duty-cycle

Output Circuit Schematic
The equivalent circuit of a typical FCT- T output stage is shown in
Figure 4.

Vee
FROM
PREVIOUS
STAGE

'---+-OUTPUT

OE SIGNAL-----------I

Figure 4. FCT-T Output Stage Schematic

7.21

4

APPLICATION NOTE AN-54

FCT-T LOGIC FAMILY

The schematic shown here differs from a traditional CMOS output stage (P-<:hannel pull up and N-channel pull-down) in the following ways:
• An N-channel pull-up transistor is used to obtain a voltage offset in the logic High state, so that the quiescent VOH level is approximately 3.3 volts.
• The pull-down circuit consists of two stages. During the Highto-Low transition, a small N-channel transistor turns on first, followed by a large N-channel transistor after some delay. This arrangement results in a smaller dildt in the ground return path dur-

ing the output transition and adequate DC drive in the logic Low
state. There are minor variations in the actual implementation of
the output stage from mask-set to mask-set. The schematic
shown is intended to give the general concept.
DC Output Characteristics (Logic LOW and HIGH
States)
Typical DC output characteristics for the logic LOW and HIGH
states are shown in Figures 5A and 58, respectively. These
curves are obtained at 25°C and Vee = 5 volts.

VOUT (V)

o

2

5

15
-25
-50

10
lOUT

-75

LOGIC LOW STATE

(rnA)

lOUT

30n (typical)

75

(rnA

-100
LOGIC HIGH STATE

25

-125
-150

2

3

4

5

VOUT (V)
Figure 58. Output High Characteristics

Figure SA. Output Low Characteristics

The output characteristic in the logic LOW state shows high static
drive capability and low output impedance in the linear region.
Typical output impedance in the LOW state is 5Q.
The output characteristic in the logic HIGH state has a slope of
30Q typical. This relatively high output impedance and the reduced voltage swing make the LOW-to-HIGH transition the worst
case for incident wave switching. The characteristics are presented here to assist the system designer in determining proper
termination based on the application at hand.

output voltage above Vee depends on the actual circuit implementation.
In the High Impedance state, both pull-up and pull-down sections of the output stage are disabled. Therefore, the output ports
exhibit very high impedance in the normal operating range. For
output voltages below GND, parasitic junction diodes associated
with the N-channel output transistors come into effect and offer
very low output impedance to GND as shown by the diode characteristic in Figure 6. For output voltages above Vee, one of two different characteristics can be observed:

DC Output Characteristics (High Z State)
The output characteristics in the High Impedance state are
shown in Figure 6 on the following page. The breakdown region for

7.21

5

I

I

FCT-T LOGIC FAMILY

APPLICATION NOTE AN-54

60
(8)

(A)

lOUT (mA) 40

20

2

3

4
5
VOUT (V)

6

8

(A): Outputs Without Power-Off Disable Feature
(8): Outputs With Power-Off Disable Feature

Figure 6. Output High-Z Characteristics

Curve (A): The devices with P-channel transistors in the output
stage exhibit low impedance at output voltage greater than a diode
above Vee. These devices do not have the "power-off disable"
feature.
Curve (8): The devices with the "power-off disable"feature show
high output impedance at output voltages higher than Vee. The
output stage in these devices has been designed to avoid any
parasitic junction diode to Vee.
The "power-off disable" feature is discussed in detail later in this
bulletin.

rent normally represents internal leakages as well as pacakagerelated leakages.
(2) ~Iee - The quiescent power supply current when inputs are
held at "TTL levels", and
(3) leeD- Dynamic current caused by an Input Transition Pair
(HLH or LHL). This current is a function of frequency associated
with the signal transitions.
The total current Ie = Icc + ~Iee + IceD.
The last two components of power supply current are discussed
in detail below.
~Icc

POWER SUPPLY CHARACTERISTICS

Characteristics

The input stage of a CMOS device draws current from the power
supply pin for an input voltage range bounded by Vtn and (Vee-V tp )
where Vtn and Vtp are the thresholds of N-channel and P-channel
devices, respectively. Within this voltage range, both P and N
channel transistors in the input translator stage are on (see Figure
2 for reference). Figure 7 shows the relationship between ~Iee
and input voltage (VIN) for a typical FCT- T input stage.

Components of Power Supply Current
There are three power supply current components in TTL compatible CMOS circuits:
(1) Icc - The quiescent power supply current through the supply
pin when all inputs are either at GND or at applied Vee. This cur-

6
5

L'1lee
Per Input
(mA)

4
3

2

0
0

2

3

4

5

VIN (Volts)
Figure 7. ~Icc Characteristics

7.21

6

FCT-T LOGIC FAMILY

APPLICATION NOTE AN-54

i = average switching current through the power
supply path.

As the input voltage is raised above Vtn , the ~Icc component increases, reaching a peak at the input threshold for the low-ta-high
transition. The sharp drop in current at threshold indicates the
presence of hysteresis which effectively modifies the P-channel to
N-channel ratio. As the input voltage is raised further, the ~Icc
component falls because the P-channel transistor is being progressively turned off. Note that the characteristic is plotted "per input". The total current drawn from an IC depends on the number of
inputs and the voltage applied to each input. The ~Icc parameter
is specified for an input voltage of 3.4 volts at Vcc = max. in the
data sheet.

Dynamic Power Supply Current -

The average power supply current is given by i = fC pV. Since this
current is a function of frequency, it can be represented in the form
of current per MHz and its value is given by CpV with appropriate
units. This is the dynamic power supply current for the gate. In a
CMOS integrated circuit the total dynamic current is the sum of all
such currents and is represented by ICCD.
ICCD is measured with the switching output(s) open, so that there
is no influence of capacitance external to the package. Capacitive
loading on the switching outputs will increase the measured value
of ICCD by an amount equal to the load-dependent fCl V. Also, input transitions should be from GND to Vcc to eliminate any ~Icc
component in the measurement. For devices with multiple identical paths (FCT244T Octal Buffer, for example), ICCD is specified for
one bit switching. Figure 8 shows a graph for dynamic power supply current for FCT244T buffer. This graph shows the linear relationship between ICCD and frequency. ICCD characteristic for an
FCT244 with rail-to-rail output swing is also shown for comparison. The difference in the current at any frequency is due to the
reduced output voltage swing.

ICCD

CMOS gates use power from the power supply source to charge
and discharge parasitic capacitances when changing logic levels.
This power is related to the frequency at which the logic level transitions occur. It is given by the formula:

where

Power = V xi = fC pV2
f = frequency of logic level transitions,
Cp = parasitic capacitance associated with the gate,
V = voltage change on the capacitor, and

6

TA = 25°C
Vcc = 5.5 V
Input Swing: 5V peak-to-peak

5

ICCD (mA)
PER BIT

4

3

FCT-T

2

o

o

5

10

20

15

25

30

35

FREQUENCY (MHz)
Figure 8. Dynamic Power Supply Current

NOTE: The units for ICCD have the dimensions of current x time.
Therefore, this parameter should be treated as "charge". In fact,
the JEDEC Standard 18 for FCT logic uses the symbol QCCD for
this parameter. In this application note, the author has chosen the
SYMBOL

symbollCCD since the measurement isin terms of current and is
also consistent with the data sheets.
Figure 9, below, shows the Power Supply Characteristics table
for FCT244T as an example.

PARAMETER

TEST CONDITIONS

Icc

Quiescent Power Supply Current

Vcc = Max.
VIN = Vcc or GND
f= 0

~Icc

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max.
VIN = 3.4V

ICCD

Dynamic Power Supply Current

Vcc = Max.
Outputs Open
One Bit Toggling

I

VIN = Vcc
VIN = GND

TYP_

MAX.

UNIT

0.2

1.5

mA

0.5

2.0

mA

0.15

0.25

mAl
MHz

Figure 9. FCT244T Power Supply Characteristics

7.21

7

I

APPLICATION NOTE AN 54

FCT-T LOGIC FAMILY

Note that the above example shows the dissipation due to the
device alone. In reality, the capacitive loading on the outputs will
contribute additional power dissipation and must be taken into
consideration for determining power supply requirements. This
topic is discussed in depth in the Application Note entitled
"POWER DISSIPATION IN CLOCK DRIVERS'.
Similar calculations can be performed for any device once the
operating conditions are known. In more complex devices, as well
as in interface devices used in data and address paths, it is necessary to estimate the "average" frequency of operation to determine
the total device dissipation under realistic operating conditions.

Total Power Supply Current - Example
From the information provided in the table above, the total power
supply current can be calculated for a given operating condition.
For example, let us assume that the FCT244T is used as a clock
buffer, distributing the clock with a fan-out of 8 (one input, 8 outputs) at 25 MHz with 50 duty cycle. This clock distribution is accomplished by tying all inputs together. Output Enable pins are at
GNO. Inputs are driven from a TIL compatible device.
Typical power supply current Ie (outputs unloaded) is calculated
as follows:
lee = 0.2mA
= 0.5(duty ratio) x 8(switching inputs) x 0.5mA = 2mA
leeD = 2S(frequency) x 8(switching outputs) x 0.1SmA = 30mA

AC PERFORMANCE

~Iee

Except for the reduced output voltage swing, the AC characteristics of the FCT-Tfamily are the same as those of the FCTfamily in
terms of operating conditions and limits. Given below in Figure 10
are the performance figures for four FCT- T logic parts for different
speed grades. The performance is compared with the popular
FAST family of bipolar parts.

Therefore,
Ie = 0.2 + 2 + 30 = 32.2mA (typical).

FCT- T Speed Grades
74 FCT-CT
CMOS

74FCT-AT
CMOS

74FCT-T
CMOS

74F
BIPOLAR

244 Buffer

4.1ns

4.8ns

6.5ns

6.Sns

OtoY

245 XCVR

4.1ns

4.6ns

7.0ns

7.0ns

A to B, Bto A

373 Latch

4.7ns

S.2ns

8.0ns

8.0ns

On to an

374 Register

S.2ns

6.Sns

10.0ns

10.0ns

CLKto an

DEVICE

PARAMETER

Figure 10. FCT-T AC Performance Comparison

The variety of speed grades offer the system designer a choice in
optimizing overall system performance. In many cases, the use of
higher speed logic allows the designer a choice of using lower
speed memory devices to reduce the overall cost of the system.

AC Performance Over Temperature Range
The AC performance of FCT- T family of products over the operating temperature range is similar to that of the FCT family. A normalized graph of tpLH and tpHL for the FCT244T device is presented in Figure 11 as an example.

244 BUFFER
1_2

Vee=S.OV
RL = soon, CL = SOpF

1.1
1.0

0.9
tpHL
0.8

0.7

-55

-35

-15

5

25

45

65

85

105

125

AMBIENT TEMPERATURE (OC)
Figure 11. Normalized Switching Characteristics

7.21

8

APPLICATION NOTE AN-54

FCT-T LOGIC FAMILY

cant reduction in the magnitude of both the positive and the negative components of ground bounce. The relationship between
ground bounce and tpHL for the FCT244T is shown in Figure 12.
The graph shows the improvement achieved when compared with
the FCTfamily overthe same speed range. All measurements are
at Vee = 5 volts and 25°C ambient temperature.

Simultaneous Switching Noise
One of the primary benefits of FCT- T family of products is the improvement in performance with respect to simultaneous switching
noise, or ground bounce, when compared with any CMOS family
with rail-to-rail output swing. The combination of a modified TTL
output stage and reduced output voltage swing results in a signifi244 BUFFER

3

(DIP PACKAGE)
•

•

+VE GROUND BOUNCE

C

C

-VE GROUND BOUNCE

2

Vg
(volts)

3

4

5
tpHL

6

(ns)

Figure 12. Ground Bounce vs. Speed

The reader is referred to the Application Note entitled "SIMUL TANEOUS SWITCHING NOISE" for an in-depth discussion on the
cause and effects of ground bounce and applications guidelines.

Vee by a junction diode drop. This feature precludes use of such
devices in applications which require power-off or power up/down
disable capability.
Certain members of the FCT-T family (such as the 646/648T,
651/652T Bidirectional RegisterITransceivers, FCT52/53T
bidirectional registers, 620/621 1622/623T backplane transceivers)
offer the power off/up/down disable capability. When the outputs
of these devices are conditioned to be in the High Impedance
state, all3-state outputs will offer high imped2.nce independent of
power supply voltage (excluding negative Vee with respect to
GND). The Power Off Disable capability is shown in the DC Characteristics table in the form of a leakage current of 1001lA max. at
Vee = 0 volts and VOUT = 4.5 volts.

POWER-OFF DISABLE FEATURE
Power-off Disable is a condition where the output of a device
maintains high impedance state during power supply ramping if
the output enable control pins are conditioned to place the appropriate outputs in the high-Z state. This is a desirable feature in
backplane applications where it is often necessary to perform "hot"
insertion and disinsertion of printed circuit cards for on-line maintenance. It is essential that this activity does not violate data integrity on the backplane. Another application where this feature is
useful is in systems with multiple redundancy where one or more
redundant cards may be powered off while still plugged into the
system. Under these conditions the backplane drivers on these
cards should offer very low loading on the backplane.
Most drivers designed for backplane application do not offer this
feature. For example, CMOS drivers which use a P-channel output transistor in the pull-up circuit have a parasitic diode to the Vee
rail at each such output. Therefore the output node offers a low impedance to the Vee pin when the output voltage exceeds applied

SUMMARY
The FCT- T family of logic products is introduced in an effort to
alleviate some of the simultaneous switching noise problems while
maintaining compatibility with the industry-standard FCTfamily as
well as with other TTL-compatible logic families. A variety of
speed grades and packaging alternatives are offered to help design an optimum system in terms of speed, cost, performance and
board space.

7.21

9

I

(;)®
Integrated Device Technology, Inc.

SHARED RAM APPLICATION
128K X 8 Shared RAM
This application illustrates the use of IDT49FCT804 Bus
Multiplexer in a shared memory application. In this example,
two processors share a 128Kbyte memory bank. A pair of
IDT49FCT804 multiplexers are used for address selection.
The address buses from the two processors are connected to
A and C ports,respectively. The B port serves as the memory
address bus. With all Latch Enable and Output Enable signals
asserted, address from A or C ports is routed to B port under

the control of SO which receives its input from an external
arbiter/decoder (S1 = 0 and DAB = DCB = 1).
Two more IDT49FCT804 multiplexers route data between
the processor data buses connected to A and C ports and the
memory data bus connected to the B port. Again, address bus
selection is under the control of input SO. Inputs DAB and DeB
provide direction control for READ and WRITE operations.
The RAM OE signal is asserted during the READ operation.
An external arbiter/decoder performs arbitration between
two processor requests and provides chip select and write
enable signals for the memory array.

I
54174FCT804/A

MEM

-r--l-

LADDR_
ADDRESS
3-PORT
MUX

A (0:14LI

l

f-

RADDR

--

71256: 32K x 8 SRAM

/ 7
/

RADDR_

LADDR

LOGIC TECHNICAL
BULLETIN
IDT49FCT804

SHARED RAM AND DRAM
ADDRESS MULTIPLEXER
APPLICATION

i LlR SEL

71256

71256

71256

712561

71256

71256

71256

712561

"I
1/0 (0:7)

WRITE ENABLE
ARBITERI
DECODER I - -

CHIP SELECT

CS, DS & R/W
CONTROLS -+

A (0:14)1

I
54174FCT804/A

l

LDATA _

.-

DATA
RDATA_
3-PORT
MUX

DIRCONT~

"I

1/0 (8:15)

-

r

LlR SEL
2631 drw 01

Figure 1. 128K x 8 Shared RAM

1!!>1990 In1egrated Device Technology. Inc.

7.22

4190

IDT49FCT804
SHARED RAM AND DRAM ADDRESS MULTIPLEXER APPLICATION

LOGIC TECHNICAL BULLETIN

DRAM ADDRESS MULTIPLEXER
APPLICATION
This application illustrates the use of IDT49FCT804 Bus
Multiplexer for row and column addressing in a large DRAM
array. In this example, the full 10-bit capability of the Bus
Multiplexer is used to address a 1 MBit DRAM array. The row

address lines are connected to the A port and the column
address lines are connected to the C port. All address signals
are latched simultaneously in the A and C port input latches.
Under the control of path selection input SO (S1 = LOW), the
row and column addresses are sent sequentially to the DRAM
array.

RAM ARRAY
ROW
/

/10
ADDRESS
BUS

..
~

/

54174FCT804/A

LEA
B PORT

COLUMN
/10
LATCH
ENABLE

/
/

I

/20
/

//'1

APORT

CPORT

/

7

10

/

--

1 MBIT
DRAM

---;;-"
r---

/

LEC

T

SELECT

2631 drw 02

Figure 2. DRAM Address Multiplexer Application

I
I

7.22

2

,;5

TB-LOGIC
001-A
IDT74FCT138/139

PREVENTING DECODE
GLITCHES

Integrated Device Technology, Inc.

By Suren Kodical
This bulletin describes the timing considerations for avoiding
spurious output glitches in FCT138 and 139 decoders.
When these decoders are used in microprocessor-based
systems to generate clock or latch enable signals, spurious
decoding glitches are likely to cause system errors. Even

though the input signals to the decoders may be clean,
differences in the propagation delays in the combinatorial
paths can cause unwanted output transitions under certain
conditions. This is illustrated below by using an FCT138
decoder as an example:

E3
E2

E1
0----

E n --~

00

AD
A1
A2 - - - - - - 1

An--~

2631 drw 04

2631 drw 03

Figure 3. Section of Decc;>der

Figure 4. Signal Delays

When the enable lines are asserted, the decoded output
corresponding to the appropriate weighted binary inputs will
be LOW. When the enable lines are deasserted, the outputs
may respond to logic level changes at An inputs if the

propagation delay TA is shorter than delay TE through the
enable path. This is illustrated in the timing diagram.

2631 drw 05

Figure 5. Timing Diagram

To prevent spurious transitions at the decoder outputs, it is
necessary to keep the address lines stable for at least TE - TA.
This is designated in the timing diagram by Th.
Characterization data on the IOT54/74FCT138 shows that

:e1990 Inlegraled Device Technology. Inc.

Th = 1ns can be used as a guideline for design. The same
number also applies to FCT139. Note, however, that this is
not a testable parameter on automated test equipment.

7.22

4/90

3

(;)®

TB-LOGIC
002-A
I DT74FCT374/574

PIPELINE TIMING

Integrated Device Technology, Inc.

By Suren Kodical
When devices such as the FCT374 (Octal Register) are
used as Pipeline Registers (as shown in Figure 1), two sets of
AC parameters govern performance boundaries:
1. tPD (max.) from clock to output + tsu determines the

2.

maximum frequency of operation.
The timing difference between tPD (min.) from clock to
output and tH from data to clock determines the amount
of margin for successful pipelining.

Ox

DATA

Ov

FCT374

Y
CP

2631 drw 06

Figure 1.

In the case of high-speed registers, the maximum frequency
limit far exceeds most design requirements. Therefore,
condition #1 described above is generally not an issue.
However, the high-speed switching and data transfer can
DATA

xxxxxXx~

cause problems if the minimum delay from clock to output
approaches the positive tH in magnitude. This situation is
described by means of Figures 2 and 3, below.

On XXXXXxX,--_On_+l-----"-X~X~X----"'­

~~~tsu

CP ________________~__

, ,_____~~

>_t~H,~
r.:_________________________
~X
n

Ox _ _________________________________
n-1

Ov _________________n_-_2________________-J)xC~

~
n+1

_____________n_-_1____________J)x(~____n______
2631 drw 07

Figure 2.

In Figure 2, the propagation delay from CP to Ox exceeds
the hold time tH for register X. Therefore, for each positive
transition of the clock, data at the input of register X is
transferred to output Ox and previous data at Ox is transferred
to output OYof register Y. The difference between tPD from CP
to Ox and the hold time tH is the safety margin for successful
pipelining.

©1990 Integrated Device Technology. Inc.

7.22

Figure 3 shows the result of loss of timing margin. In this
illustration, the clock to output delay of the high-speed register
X is less than the required hold time for register Y under given
conditions. As a result, on the positive transition of the clock,
register Y will transfer new data at the input of the pipeline
instead of the previous data at Ox.

4190

4

II
I

PIPELINE TIMING

DATA

CPx

TB·LOGIC 002·A

XXXXXXX)cr Dn XXXXXXx"---_Dn_+1--,,-X~X---,,-,-X~
~~~tsu

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