1990_Intel_Microcommunications_Volume_II_Applications 1990 Intel Microcommunications Volume II Applications

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Intel the Microcomputer Company:
When Intel invented the microprocessor in 1971, it created the era of
microcomputers. Whether used in embedded applications such as automobiles
or microwave ovens, or as the CPU in personal computers or supercomputers,
Intel's microcomputers have always offered leading-edge technology. Intel continues
to strive for the highest standards in memory, microcomputer components, modules
and systems to give its customers the best possible competitive advantages.

MICROCOMMUNICATIONS
APPLICATIONS

1990

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors
which may appear in this document nor does it make a commitment to update the information contained
herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before· placing your order.
The following are trademarks rof Intel Corporation and may only be used to identify Intel Products:
376,386,387,486, 4-SITE, Above, ACE51 , ACE96, ACE186, ACE196,
ACE960, BITBUS, COMMputer, CREDIT, Data Pipeline, DVI, ETOX,
FaxBACK, Genius, i, t, i486, i750, i860, ICE, iCEL, ICEVIEW, iCS, iDBP,
iDIS, 12 1CE, iLBX, iMDDX, iMMX, Inboard, Insite, Intel, intel, Inte1386,
intaiBOS, Intel Certified, Intelevision, inteligent Identifier, inteligent
Programming, Intellec, Intellink, iOSP, iPAT, iPDS, iPSC, iRMK, iRMX,
iSBC, iSBX, iSDM, iSXM, Library Manager, MAPNET, MCS,
Megachassis, MICROMAINFRAME, MULTIBUS, MULTICHANNEL,
MULTIMODULE, MultiSERVER, ONCE, OpenNET, OTP, PR0750,
PROMPT, Promware, QUEST, QueX, Quick-Erase, Quick-Pulse
Programming, Ripplemode, RMX/80, RUPI, Seamless, SLD, SugarCube,
TooITALK, UPI, Visual Edge, VLSiCEL, and ZapCode, and the
combination of ICE, iCS, iRMX, iSBC, iSBX, iSXM, MCS, or UPI and a
numerical suffix.
MDS is an ordering code only and is not used as a product name or trademark. MDS@ is a registered
trademark of Mohawk Data Sciences Corporation.
·MULTIBUS is a patented Intel bus.

>

CHMOS and HMOS are patented processes of Intel Corp.
Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its
FASTPATH trademark or products.
.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
@INTELCORPORATION 1989

CUSTOMER SUPPORT
INTEL'S COMPLETE SUPPORT SOLUTION WORLDWIDE
Customer Support is Intel's complete support service that provides Intel customers with hardware support,
software support, customer training, consulting services and network management services. For detailed information contact your local sales offices.
After a customer purchases any system hardware or software product, service and support become major
factors in determining whether that product will continue to meet a customer's expectations. Such support
requires an international support organization and a breadth of programs to meet a variety of customer needs.
As you might expect, Intel's customer support is quite extensive. It can start with assistance during your
development effort to network management. 100 Intel sales and service offices are located worldwide-in the
U.S., Canada, Europe and the Far East. So wherever you're using Intel technology, our professional staff is
within close reach.

HARDWARE SUPPORT SERVICES
Intel's hardware maintenance service, starting with complete on-site installation will boost your productivity
from the start and keep you running at maximum efficiency. Support for system or board level products can be
tailored to match your needs, from complete on-site repair and maintenance support to economical carry-in or
mail-in factory service.
Intel can provide support service for not only Intel systems and emulators, but also support for equipment in
your development lab or provide service on your product to your end-user/customer.

SOFfWARE SUPPORT SERVICES
Software products are supported by our Technical Information Service (TIPS) that has a special toll free
number to provide you with direct, ready information on known, documented problems and deficiencies, as.
well as work-arounds, patches and other solutions.
Intel's software support consists of two levels of contracts. Standard support includes TIPS (Technical Information Phone Service), updates and subscription service (product-specific troubleshootmg guides and;
COMMENTS Magazine). Basic support consists of updates and the SUbscription service. Contracts are sold in
environments which represent product groupings (e.g., iRMX® environment).

CONSULTING SERVICES
Intel provides field system engineering consulting services for any phase of your development or application
effort. You can use our system engineers in a variety of ways ranging from assistance in using a new product,
developing an application, personalizing training and customizing an Intel product to providing technical and
management consulting. Systems Engineers are well versed in technical areas such as microcommunications,
real-time applications, embedded microcontrollers, and network services. You know your application needs;
we know our products. Working together we can help you get a successful product to market in the least
,
possible time.

CUSTOMER TRAINING
Intel offers a wide range of instructional programs covering various aspects of system design and Implementation. In just three to ten days a limited number of individuals learn more in a single workshop than in weeks of
self-study. For optimum convenience, workshops are scheduled regularly at Training Centers worldwide or we
can take our workshops to you for on-site instruction. Covering a wide variety of topics, Intel's major course
categories include: architecture and assembly language, programming and operating systems, BITBUS™ and
LAN applications.
.

NETWORK MANAGEMENT SERVICES
Today's networking products are powerful and extremely flexible. The return they can provide on your investment via increased productivity and reduced costs can be very substantial.
Intel offers complete network support, from definition of your network's physical and functional design, to
implementation, installation and maintenance. Whether installing your first network or adding to an existing
one, Intel's Networking Specialists can optimize network performance for you.

Table of Contents
Alphanumeric Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AP-302 Microcommunications Overview .....................................

viii
ix

SECTION ONE-DATA COMMUNICATIONS COMPONENTS
CHAPTER 1
Local Area Networks
CSMA/CD Access Method
AP-235 An 82586 Data Link Driver ..........................................
AP-236 Implementing StarLAN with the Intel 82588 ......................... ~..
AP-320 Using the Intel 82592 to Integrate a Low-Cost Ethernet Solution into a PC
Motherboard ....................................................... ;...
AP-274 Implementing EthernetiCheapernet with the Intel 82586 .............. ..
AP-324 Implementing Twisted Pair Ethernet with the Intel 82504TA, 82505TA, and
82521 TA . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-327 Two Software Packages for the 82592 Embedded LAN Module .. . . . . . . ..
AP-331 Using the Intel 82592 to Implement a Non-Buffered Master Adapter for ISA
Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

1-1
1-81
1-155
1-200
1-289
1-308
1-386

CSMA/CD Access Method Evaluation Tools
AP-326 PS592E-16 Buffered Adapter LAN Solution for the Micro Channel
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-328 PC592E Buffered LAN Adapter Solution for the IBM PC-XT and AT . .. . . ..

1-468
1-519

CHAPTER 2
Wide Area Networks
AP-401 Designing With the 82510 Asynchronous Serial Controller. . . . . . . . . .. .. . .
AP-31 0 High Performance Driver for 82510 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .
AP-36 Using the 8273 SDLC/HDLC Protocol Controller . . . . . . . . . . . . . . . . . . . . . . ..
AP-134 Asynchronous Communication with the 8274 Multiple-Protocol Serial
Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-145 Synchronous Communication with the 8274 Multiple Protocol Serial
Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-222 Asynchronous and SDLC Communications with 82530 . . . . . . . . . . . . . . . . ..

2-1
2-81
2-112
2-164
2-202
2-240

CHAPTER 3
Other Components
AP-166 Using the 8291A GPIB Talker/Listener.............................. ..
AP-66 Using the 8292 GPIB Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1
3-31

SECTION TWO-TELECOMMUNICATION COMPONENTS
CHAPTER 4
Modem Products
AB-24 89024 Modem Customization for V.23 Data Transmission ................

4-1

CHAPTERS
ISDN Products
AP-282 29C53 Transceiver Line Interfacing. . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . ..
AP-400 ISDN Applications with 29C53 and 80188 .............................

5-1
5-15

CHAPTER 6
PCM Codec/Filter and Combo
Applications Information 291 OAl2911 Al2912A ...............................

6-1

AP-142 DeSigning Second-Generation Digital Telephony Systems Using the Intel
2913/14 Codec/Filter Combochip.........................................

6-4

vii

Alphanumeric Index
AB-24 89024 Modem Customization for V.23 Data Transmission ...................... .
AP-134 Asynchronous Communication with the 8274 Multiple-Protocol Serial Controller .. .
AP-142 Designing Second-Generation Digital Telephony Systems Using the Intel 2913/14
Codec/Filter Combochip ....................................................... .
AP-145 Synchronous Communication with the 8274 Multiple Protocol Serial Controller ... .
AP-166 Using the 8291A GPIB Talker/Listener ..................................... .
AP-222 Asynchronous and SDLC Communications with 82530 ........................ .
AP-235 An 82586 Data Link Driver ................................................ .
AP-236 Implementing StarLAN with the Intel 82588 .................... ; ............ .
AP-274 Implementing EthernetlCheapernet with the Intel 82586 ...................... .
AP-282 29C53 Transceiver Line Interfacing ......................... " .............. .
AP-302 Microcommunications Overview ........................................... .
AP-31 0 High Performance Driver for 82510 " .......................................•
AP-320 Using the Intel 82592 to Integrate a Low-Cost Ethernet Solution into a PC
Motherboard .............................................•....................
AP-324 Implementing Twisted Pair Ethernet with the Intel 82504TA, 82505TA, and
.
82521TA .................................................................... .
AP-326 PS592E-16 Buffered Adapter LAN Solution for the Micro Channel Architecture ... .
AP-327 Two Software Packages for the 82592 Embedded LAN Module ................ .
AP-328 PC592E Buffered LAN Adapter Solution for the IBM PC-XT and AT ............. .
AP-331 Using the Intel 82592 to Implement a Non-Buffered Master Adapter for ISA
Systems ...................... , ........... ; ........•..........................
AP-36 Using the 8273 SDLC/HDLC Protocol Controller ...............-............... .
AP-400 ISDN Applications with 29C53 and 80188 ..................... : ..........•...
AP-401 Designing With the 82510 Asynchronous Serial Controller ..................... .
AP-66 Using the 8292,GPIB Controller ............................................. .
Applications Information 2910Al2911A12912A ....... : ............................. .

viii

4-1
2-164
6-4
2-202
3-1
2-240
1-1
1-81
1-200
5-1
ix
2-81
1-155
·1-289
1-468
1-308
1-519
1-386
2-112
5-15
2-1
3-31
6-1

Ap·302

Kobayashi's macro vision hints at the obstacles confronting the future of C&C. When taken to the micro
level, to silicon itself, one begins to understand the'
complexities that are involved. When Intel invented the
microprocessor fifteen years ago, the first seeds of the
personal computer revolution were sown , marking an
era that over the last decade has dramatically influenced the way people work and live. PCs now proliferate in the office, in factories, and throughout laboratory
environments. And their "intimidation" factor has lessened to where they are also becoming more and more
prevalent in the home, beginning to penetrate a market
that to date has remained relatively untapped.

OVERVIEW
Imagine for a moment a world where all electronic
communications were instantaneous. A world where
voice, data, and graphics could all be transported via
telephone lines to a variety of computers and receiving
systems. A world where the touch of a finger could
summon information ranging from stock reports to
classical literature and bring it into environments as
diverse as offices and labs, factories and living rooms.
Unfortunately, these promises of the Information Age
still remain largely unfulfilled. While computer technology has accelerated rapidly over the last twenty
years, the communications methods used to tie the wide
variety of electronic systems in the world together have,
by comparison, failed to keep pace. Faced with a tangle
of proprietary offerings, high costs, evolving standards,
and incomplete technologies, the world is still waiting
for networks that are truly all-encompassing, the missing links to today's communications puzzle.

Thanks to semiconductor technology, the personal
computer has raised the level of productivity in our
society. But most of that productivity has been gained
by individuals at isolated workstations. Group productivity, meanwhile, still leaves much to be desired. The
collective productivity of organizations can only be enhanced through more sophisticated networking
technology. We are now faced with isolated "islands
of automation" that must somehow be developed
into networks of productivity.

Enter microcommunications-microchip-based digital
communications products and services. A migration of
the key electronics communications functions into silicon is now taking place, providing the vital interfaces
that have been lacking among the various networks
now employed throughout the world. Through the evolution ofVLSI (Very Large Scale Integration) technology, microcommunications now can offer. the performance required to effect these communications interfaces
at affordable costs, spanning the globe with silicon to
eradicate the troublesome bottleneck that has plagued
information transfer during recent years.

But no amount of computing can meet these challenges
if the corresponding communications technology is not
sufficiently in step. The Information Age can only grow
as fast as the lowest common denominator-which in
this case is the aggregate communications bandwidth
that continues to lag behind our increased computing
power. Such is the nature of the communications bottleneck, where the growing amounts of information we
are capable of generating can only flow as fast as the
limited and incompatible communications capabilities
now in place. Clearly, a crisis is at hand.

"There are three parts to the communications puzzle,"
says Gordon Moore, Intel Chairman and CEO. "The
first incorporates the actual systems that communicate
with each other, and the second is the physical means
to connect them-such as cables, microwave'technology, or fiber optics. It is the third area, the interfaces
between the systems and the physical links, where silicon will act as the linchpin.. That, in essence, is what
microcommunications is all about."

BREAKING UP THE BOTTLENECK
Three factors have contributed to this logjam: lack of
industry standards, an insufficient cost/performance
ratio, and the incomplete status of available communications technology to date.
• Standards-One look at the tangle of proprietary
systems now populating office, factory, and laboratory environments gives a good indication of the
inherent difficulty in hooking these diverse systems
together. And these systems do not merely feature
different architectures-they also represent completely different levels of computing, ranging from
giant mainframes at one end of the scale down to
individual microcontrollers on the other.
The market has simply grown too fast to effectively
accommodate the changes that have occurred. Suppliers face the dilemma of meshing product differentiation issues with industry-wide compatibility as

THE COMMUNICATIONS
BOTTLENECK
Visions of global networks are not new. Perhaps one of
the most noteworthy of these has been espoused by Dr.
Koji Kobayashi, chairman of NEC Corporation. His
view of the future, developed over the nearly fifty years
of his association with NEC, is known as C&C (Computers and Communications). It defines the marriage of
passive communications systems and computers as
processors and manipulators of information, providing
the foundation for a discipline that is changing the basic character of modern society.

ix

intJ

•

•

AP-302

they develop their strategies; opting for one in the
past often meant forsaking the other. And while
some standards have coalesced, the industry still
faces a technological Tower of Babel, with many
proprietary solutions vying to be recognized in leadership positions.
Cost/Performance Ratio-While various communications technologies struggle toward maturity,
the industry has had to cope with tremendous costs
associated ,with interconnectivity and interoperation. Before the shift to microelectronic interfaces
began to occur, these connections often were prohibitively expensive.
Says Ron Whittier, Intel Vice President and Director of Marketing: "Mainframes offer significant
computing and communications power, but at a
price that limits the number of users. What is needed is cost-effective communications solutions to
hook together the roughly 16 million installed PCs
in the market, as well as the soon-to-exist voice/
data terminals. That's the role of microcommunications-bringing cost-effective communications solutions to the microcomputer world."
Incomplete Technology-Different suppliers have
developed many networking schemes, but virtually
all have been fragmented and unable to meet the
wide range of needs in the marketplace. Some of
these approaches have only served to create additional problems, making OEMs and systems houses
loathe to commit to suppliers who they fear cannot
provide answers at all of the levels of communications that are now funneled into the bottleneck.

The distances over which information may be transmitted via a WAN are essentially unlimited. The goal of
ISDN is to take what is largely an analog global system
and transform it into a digital network by defming the
standard interfaces that will provide connections at
each node.
These interfaces will allow basic digital communica-'
tions to occur via the existing twisted pair of wires that
comprise the telephone lines in place today. This would
bypass the unfeasible alternative of installing completely new lines, which would be at cross purposes with the
charter of ISDN: to reduce costs and boost performance through realization of an all-digital network.
The second category, Local Area Networks, represents
the most talked~about link provided by microcommunications. In their most common form, LANs, are comprised of-but not limited to-PC-to-PC connections.
They incorporate information exchange over limited
distances, usually not exceeding five kilometers, which
often takes place within the same building or between
adjacent work areas. The whole phenomenon surrounding LAN development, personal computing, and distributed processing essentially owes its existence to microcomputer technology, so it is not surprising that this
segment of networking has garnered the attention it has
in microelectronic circles.
Because of that, progress is being made in this area.
The most prominent standard-which also applies to
WANs and SANs-is the seven-layer Open Systems Interconnection (OSI) Model, established by the International Standards OrgaI)ization (ISO). The model provides the foundation to which all LAN configurations
must adhere if 'they hope to have any success in the
marketplace. Interconnection protocols determining
how systems are tied together are defined in the first
five layers. Interoperation concepts are covered in the
upper two layers, defining how systems 'can c:ommunicate with each other once they are tied together.

THE NETWORK TRINITY
Three principal types of networks now comprise the
electronic communications marketplace: Wide, Area
Networks (WANs), Local Area Networks (LANs), and
Small Area Networks (SANs). Each in its own fashion
is turning to microcommunications for answers to its
networking problems.

In the LAN marketplace, a large number of networking
products and philosophies are available today, offering
solutions at various price/performance points. Diverse
approaches such as StarLAN, Token Bus and Token
Ring, Ethernet, and PC-NET, to name a few of the
more popular office LAN architectures, point to many
choices for OEMs and end users.

WANs-known by some as, Global Area Networks
(GANs)-are most commonly associated with the
worldwide analog telephone system. The ,category also
includes a number of other segments, such as satellite
and microwave communications, traditional networks
(like mainframe-to-mainframe connections), modems,
statistical multiplexers, and front-end communications
processors. The lion's share of nodes-electronic network connections-in the WAN arena, however, resides in the telecommunications segment. This is where
the emerging ISDN (Integrated Services Digital Network) standard comes into focus as the most visible
portion of the WAN marketplace.

A similar situation exists in the factory., While the
Manufacturing Automation Protocol (MAP) standard
is coalescing around the leadership of General Motors,

x

inter

AP-302

Boeing, and others, a variety of proprietary solutions
also abound. The challenge is for a complete set of interfaces to emerge that can potentially tie all of these
networks together in-and among-the office, factory,
and lab environments.

the LAN segment, which should grow from 34.5% of
the total silicon microcommunications market in 1985
to 44.5% of the expanded pie in 1989.
Opportunities abound for microcommunications suppliers as the migration to silicon continues. And
perhaps no VLSI supplier is as well-positioned in this
marketplace as Intel, which predicts that 50% of its
products will be microcommunications-related bY1990.
The key here is the corporation's ability to bridge the
three issues that contribute to the communications bottleneck: standards, cost-performance considerations,
and the completeness of microcomputer and microcommunications product offerings.

The final third of the network trinity is the Small Area
Network (SAN). This category is concerned with communications over very short distances, usually not exceeding 100 meters. SANs most often deal with chip-tochip or chip-to-system transfer of information; they are
optimized to deal with real-time applications generally
managed by microcontrollers, such as those that take
place on the factory floor among robots at various
workstations.

INTEL AND VLSI: THE
MICROCOMMUNICATIONS MATCH

SANs incorporate communications functions that are
undertaken via serial backplanes in microelectronic
equipment. While they represent a relatively small market in 1986 when compared to WANs and LANs, a
tenfold increase is expected through 1990. SANs will
have the greatest number of nodes among network applications by the next decade, thanks to their preponderance in many consumer products.

Intel innovations helped make the microcomputer revolution possible. Such industry "firsts" include the
microprocessor, the EPROM, the E2PROM, the
microcontroller, development systems, and single board
computers. Given this legacy, it is not surprising that
the corporation should come to the microcommunications marketplace already equipped with a potent arsenal of tools and capabilities.

While factory applications will make up a large part of
the SAN marketplace probably the greatest contributor
to growth will be in automotive applications. Microcontrollers are now used in many dashboards to control
a variety of engine tasks electronically, but they do not
yet work together in organized and efficient networks.
As Intel's Gordon Moore commented earlier this year
to the New York Society of Security Analysts, when
this technology shifts into full gear during the next decade, the total automobile electronics market will be
larger than the entirel semiconductor market was in
1985.

The first area centers on industry standards. As a VLSI
microelectronic leader, Intel has been responsible for
driving many of the standards that are accepted by the
industry today. And when not actually initiating these
standards, Intel has supported other existing and
emerging standards through its longtime "open systems" philosophy. This approach protects substantial
customer investments and ensures easy upgradability
by observing compatibility with previous architectures
and industry-leading standards.

MARKET OPPORTUNITIES

Such a position is accentuated by Intel's technology relationships and alliances with many significant names
in the microcommunications field. Giants like AT&T
in the ISDN arena, General Motors in factory networking, and IBM in office automation all are working
closely with Intel to further the standardization of the
communications interfaces that are so vital to the
world's networking future.

Such growth is also mirrored in the projections for the
WAN and LAN segments, which, when combined with
SANs, make up the microcommunications market pie.
According to Intel analysts, the total silicon microcommunications market in 1985 amounted to $522 million.
By 1989, Intel predicts this figure will have expanded to
$1290 million, representing a compounded annual
growth rate of 25%.

Cost/performance considerations also point to Intel's
strengths. As a pioneer in VLSI technology, Intel has
been at the forefront of achieving greater circuit densities and performance on single pieces of silicon: witness
the 275,000 transistors housed on the 32-bit 80386, the
highest performance commercial microprocessor ever
built. As integration has increased, cost-per-bit has decreased steadily, marking a trend that remains consistent in the semiconductor industry. And one thing is

And although the WAN market will continue to grow
at a comfortable rate, the SAN and LAN pieces of the
pie will increase the most dramatically. Whereas SANs
represented only about 12.5% ($65 million) in 1985,
they could explode to 22.5% ($290 million) of the larger pie by 1989. This growth is paralleled by increases in

xi

AP-302

certain: microcommunications has a healthy appetite
for transistors, placing it squarely in the center of the
VLSI explosion.

That leadership extends beyond products. Along with
its own application software, Intel is promoting expansion through partnerships with many different independent software vendors (ISVs), ensuring that the necessary application programs will be in place to fuel the ,
gains provided by the silicon "engines" residing at the
interface level. And finally, the corporation's commit-'
ment to technical support training, service, and its
strong force of field applications engineers guarantees
that it will back up its position and serve the needs that
will continue to spring up as the microcommunications
evolution becomes a reality.

But it is in the final area-completeness of technology
and products-where Intel is perhaps the strongest. No
other microelectronic vendor can point to as wide an
array of, products positioned across the various, segment: that comprise the microelectronic marketplace.
Whether it be leadership in the WAN marketplace as
the number one supplier of merchant telecommunications components, strength in SANs with world leadership in microcontrollers, or overall presence in the
LAN arena with complete solutions in components,
boards, software, and systems, Intel is a vital presence
in the growing microcommunications arena.

Together, all the market segment alluded to in this article comprise the world of microcommunications, a
world coming closer together every day as the web of
networking solutions expands-all thanks to the technological ties that bind, reaching out to span the globe
with silicon.

xii

Local Area Networks

1

APPLICATION
NOTE

AP-235

November 1986

An 82586 Data Link Driver

CHARLES YAGER

Order Number: 231421-002
1-1

inter

AP-235

INTRODUCTION
This application note describes a design example of an
IEEE 802.2/802.3 compatible Data Link Driver using
the 82586 LAN Coprocessor. The design example is
based on the "Design Model" illustrated in "Programming the 82586". It is recommended that before read'ing this application note, the reader clearly understands
the 82586 data structures and the Design Model given
in "Programming the 82586".
'
"Programming the 82586" discusses two basic issues in
the design of the 82586 data link driver. The first is
how the 82586 handler fits into the operating system.
One approach is that the 82586 handler is treated as a
"special kind of interface" rather than a standard I/O
interface. The special interface means a special driver
that has the advantage of utilizing the 82586 features to
enhance performance. However the performance enhancement is at the expense of device dependent upper
layer software which precludes the use of a standard
I/O interface.
The second issue "Programming the 82586" discusses
is which algorithms to choose for the CPU to control
the 82586. The algorithms used in this data link design
are taken directly from "Programming the 82586".
Command processing uses a linear static list, while receive processing uses a linear dynamic list.
The application example is written in C and uses the
Intel C compiler. The target hardware for the Data
Link Driver is the iSBC 186/51 COMMputer, however
a version of the software is also available to run on the
LANHIB Demo board.

1.0 FITTING THE SOFTWARE INTO
THE OSI MODEL
The application example consists of four software modules:

OSI REFERENCE
MODEL LAYERS
APPLICATION
PRESENTATION

• Data Link Driver (DLD): drives the 82586, also
known as the 82586 ~andler.
• Logical Link Control (LLC): implements the IEEE
802.2 standard.
• User Application (UAP): exercises the other software modules and runs a specific application.
• C hardware support: written in assembly language,
supports the Intel C compiler for I/O, interrupts,
,_ and run time initialization for target hardware.
Figure 1 illustrates how these software modules combined with the 82586, 82501 and 82502 complete the
first two layers of the OSI model. The 82502 implements an IEEE 802.3 compatible transceiver, while the
82501 completes the Physical layer by performing the
serial interface encode/decode function.
The Data Link Layer, as defined in the IEEE 802 standard documents, is divided into two sublayers: the Logical Link Control (LLC) and the Medium Access Control (MAC) sublayers. The Medium Access Control
sublayer is further divided into the 82586 Coprocessor
plus the 82586 Handler. On top of the MAC is the LLC
software module which provides IEEE 802.2 compatibility. The LLC software module implements the Station Component responses, dynamic addition and deletion of Service Access Points (SAPs), and a class 1 level
of service. (For more information on the LLC sublayer,
refer to IEEE 802.2 Logical Link Control Draft Stan, dard.) The class 1 level of service provides a connectionless datagram interface as opposed to the class 2
level of service which provides a connection oriented
level of service similar to HDLC Asynchronous Balanced Mode.
On top of the Data Link Layer is the Upper Layer
Communications Software (ULCS). This contains the
Network, Transport, Session, and Presentation Layers.
These layers are not included in the design example,
therefore the application layer of this ap note interfaces
directly to the Data Link layer.

_-----------------EuA~P~U~~~~~~UL~E~~=~

~~~RAP~:'::IotUNlCAlION

---------"-,-,~:'~~~AC-~t-, ~~~ ~~~~~~ ~LOGICAL
M

SESSION

, / ' ,',',',','

UNK CONTROL
82586 HANDLER
DATA LINK COPROCESSOR
ENCODE/DECODE (ESI)

TRANSPORT
NETWORK
DATA LINK
PHYSICAL

,

':,',',"

"

TRANSCEIVER CABLE

HARDWARE CONNECTOR

Figure 1. Data Link Driver's Relationship to 051 Reference Mode 1
1-2

SOFTWARE

AP-235

} APPLICAnON

DATA LINK

TERMINAL EMULATOR
AND
STATION MONITOR

OLD MODULE
82586

PHYSICAL

231421-2

Figure 2. Block Diagram of the Hardware and Software
The application layer is implemented in the User Application (UAP) software module. The UAP module operates in one of three modes: Terminal Mode, Monitor
Mode, and High Speed Transmit Mode. The software
initially enters a menu driven interface which allows
the program to modify several network parameters or
enter one of the three modes.

The C_Assy_Support module has a run time start off
function which loads the DLD data segment into a
global variable SEGMT_. This data segment is used
by the 82586 Handler for address translation purposes.
The ·82586 uses a flat address while the 80186 uses a
segmented address. Any time a conversion between
82586 and 80186 addresses are needed the SEGMT_
variable is used.

The Terminal Mode implements a virtual terminal with
datagram capability (connectionless "class I" service).
This mode can also be thought of as an async to IEEE
802.3/802.2 protocol converter.

Pointers for the 80186 in the large model are 32 bits,
segment and offset. All the 82586 link pointers are 16
bit offsets. Therefore when trading pointers between the
82586 and the 80186, two functions are called:
Offset (ptr), and Build_Ptr (offset). Offset (ptr) takes a
32 bit 80186 pointer and returns just the offset portion
for the 82586 link pointer. While Build_Ptr (offset)
takes an 82586 link pointer and returns a 32 bit 80186
pointer, with the segment part being the SEGMT_
variable. Offset () and Build_Ptr() are simple functions written in assembly language included in the C_
Assy_Support module.

The Monitor Mode provides a dynamic update on the
terminal of 6 station related parameters. While in the
monitor mode, any size frame can be repeatedly transmitted to the cable in a software loop.
High Speed Transmit Mode transmits frames to the cable as fast as the software possibly can. This mode demonstrates the throughput performance of the Data Link
Driver.

In the small model, Offset ( ) and BuilLPtr( ) are not
needed, but the variable SEGMT..:... is still needed for
determining the SCB pointer in the ISCP, and in the
Transmit and Receive Buffer Descriptors.

The UAP gathers network statistics in all three modes
as well as when it is in the menu. In addition, the UAP
module provides the capability to alter MAC and LLC
addresses and re-initialize the data link.. (Figure 2
shows a combined software and hardware block diagram.)

3.0 THE 82586 HANDLER

2.0 LARGE MODEL COMPILATION

3.1 The Buffer Modei

All the modules in this design example are compiled
under the Large Model option. This has the advantages
of using the entire 1 Mbyte address space, and allowing
the string constants to be stored in ROM. In the Large
Model it is important to consider that the 82586's data
structures, SCB, CB, TBD, FD, and RBD, must reside
within the same data segment. This data segment is
determined at locate time.

The buffer model chosen for the 82586 Handler is the
"Design Model" as described in "Programming the
82586". This is based on the 82586 driver as a special
driver rather than as a standard driver. Using this approach the ULCS directly accesses the 82586's Transmit and Receive Buffers, Buffer Descriptors and Frame
Descriptors. This eliminates h.lffer copying. Transmit
and receiver buffer passing is done entirely through
pointers.
1-3

AP·235

The only hardware dependencies between the Data
Link and ULCS interface are the buffer structures. The
ULCS does not handle the 82586's CBs, SCB or initiali-'
zation structures. To isolate the data link interface from
any hardware dependencies while still using the design
model, another level of buffer copying must be introduced. For example, when the ULCS,transmits a frame
it would have to pass its own buffers to the data link.
The data link then copies the data from ULCS buffers
into 82586 buffers. When a frame is received, the data
link copies the data from the 82586's buffers into the
ULCS buffers. The more copying that is done the slower the throughput. However, this may be the only way
to fit the data link int,o the operating system. The 82586
Handler can be made hardware independent by adding
a receive and transmit function to perform the buffer
copying.

rupts the handler. The handler passes a FD pointer to
the ULCS. Linked to the FO is one or more RBDs and
RBs. The ULCS extracts what it needs from the FD,
RBDs and RBs, and returns the FD pointer back to the
handler. The handler places the'FD and RBDs back
into Jhe free RFA pool.

3.2 The Handler Interface
The handler interface provides the following basic functions:
•
•
•
•
•

The 82586 Handler allocates buffers from two pools of
memory: the Transmit pool, and the Receive pool as
illustrated in Figure 3. The Transmit pool contains
Transmit Buffer Descriptors (fBDs) and Transmit
Buffers (TBs). The Receive pool contains Frame Descriptors' (FOs), Receive, Buffer Descriptors, (RBDs),
and Receive Buffers (RBs).

Figure 4 lists the Handler Interface functions.
On power up, the initialization function is called. This
function initializes,the 82586, and performs diagnostics.
After initialization, the handler is ready to transmit and
receive frames, and add ~d delete multicast addresseS.
To send a frame, the ULCS gets one or more transmit
buffers from the handler, fills them with data, and calls
the send function. When a frame is received, the handler calls a receive function in the ULCS. The ULCS
receive function removes the information it needs and,
returns the receive buffers to the handler. The addition
and deletion of multicast addresses can be done "on the
fly" any .time after initialization. The receiver doesn't
have to be disabled when this is done.

UPPER LAYER
COMMUNICATIONS SOFTWARE
SEND

G~'·1
POOL

~
TB

I

initialization
sending and receiving frames'
adding and deleting multicast addresses
getting transmit buffers
returning receive buffers

RECEIVE

0

~~

DATA

I

TAIL
< ......

Any frames addressed to active SAPs are passed directly to them. The Station Component will not respond to
SAP addressed frames. Therefore it is the responsibility
of the SAPs to recognize and respond to frames addressed to them. When a SAP transmits a frame, it
builds the IEEE 802.2 frame itself and calls the Handler's Send_Frame() function directly. The LLC
module is not used for SAP frame transmission. The
only functions which the LLC module implement are
the dynamic addition and deletion of DSAPs, multiplexing the frames to user SAPs, and the Station Component command recognition and responses. This is
one implementation of the IEEE 802.2 standard. Other
implementations may have the LLC module do more
functions, such as SAP command recognitions and responses. A list of the functions included in the LLC
module is as follows:

~

IOSAP I SSAP I CONTROL I D;";-I

LLC Functions

231421-14

IniLLlc()

. Description

Initializes the DSAP
address table and calls
IniL586()
Add_Dsap_
Add a DSAP address to
Address (dsap, pfunc) the active list
dsap - DSAP address
pfunc - pOinter to the
SAP function
Delete a DSAP address
Delete-DsapAddress (dsap)
dsap - DSAP address
Recv-Frame (pfd)
Receives a frame from
the 82586 Handler
pfd - Frame Descriptor
Pointer
Station-Component- Generates a response to
Response (pfd)
a frame addressed to the
Station Component
pfd - Frame Descriptor
Pointer

Figure 16. IEEE 802.2 Class 1 Frame Format

From Figure 15 it can be seen that there are no LLC
class 1 VI responses because information frames are not
acknowledged at the data link level. The only command frames that may require responses are XID and
TEST. If a command frame is addressed to the Station
Component, it checks the control field to see what type
of frame it is. If it's an XID frame, the Station Cotnponent responds with a class 1 XID response frame. If it's
a TEST frame, the Station Component responds with a
TEST frame, echoing back the data it received. In both
cases, the response frame is addressed to the source of
the command frame.

1-14

inter

Ap·235

4.1 Adding and Deleting LSAPs

Terminal Mode - implements a virtual terminal with
datagram capability (connectionless "class 1" service).
This mode can also be thought of as an async to IEEE
802.2/802.3 protocol converter.

When a user process wants to add a LSAP to the active
list, the process calls Add_Dsap-Address(dsap,
pfunc). The dsap parameter is the actual DSAP address, and the pfunc parameter is the address of the
function to be called when a frame with the associated
DSAP address is received.

Monitor Mode - allows the station to repeatedly transmit any size frame to the cable. While in the Monitor
Mode, the terminal provides a dynamic update of 6
station related parameters.

The LLC module maintains a table of active dsaps
which consists of an array of structures. Each structure
contains two members: stat - indicates whether the address is free or inuse, and (*p_sap_func)() contains
the address of the function to call. The index into the
array of structures is the DSAP address. This speeds up
processing by eliminating a linear search. Delete_
Dsap-Address (dsap) simply uses the DSAP index to
mark the stat field FREE.

High Speed Transmit Mode - sends frames to the cable
as fast as the software possibly can. This mode demonstrates the throughput performance of the Data Link
Driver.
Change Transmit Statistics - When Transmit Statistics
is on several transmit statistics are gathered during
transmission. If Transmit Statistics is off, statistics are
not gathered and the program jumps over the section of
code in the interrupt routine which gathers these statistics. The transmission rate is slightly increase when
Transmit Statistics is off.

5.0 APPLICATION LAYER
For most networks the application layer resides on top
of several other layers referred to here as ULCS. These
other layers in the OSI model run from the network
layer through the presentation layer. The implementation of the ULCS layers is beyond the scope of this
application note, however Intel provides these layers as
well as the data link layer with the OpenNET product
line. For the purpose of this application note the application layer resides on top of the data link layer and its
use is to demonstrate, exercise and test the data link
layer design example.

Print All Counters - Provides current information on
the following counters.
Good frames transmitted:
Good frames received:
CRC errors r~ceived:
Alignment errors received:
Out of Resource frames:
Receiver overrun frames:

Each time a frame has been successfully transmitted the
Good frames transmitted count is incremented. The
same holds true for reception. CRC, Alignment, Out of
Resources, and Overrun Errors are all obtained from
the SCB. Underrun, lost CRS, SQE error, Max retry,
and Frames that deferred are all transmit statistics that
are obtained from the Transmit command status word.
82586 Reset is a count which is incremented each time
the 82586 locks up. This count has never normally been
incremented.

There can be several processes sitting on top of the data
link layer. Each process appears as a SAP to the data
link. The UAP module, which implements the application layer, is the only SAP residing on top of the data
link layer in this application example. Other SAPs
could certainly be added such as additional "connectionless" terminals, a networking gateway, or a transport layer, however in the interest of time this was not
done:

5.1 Application Layer Human Interface
The UAP provides a menu driven human interface via
an async terminal connected to port B on the iSBC
186/51 board. The menu of the commands is listed in
Figure 17 along with a description that follows:
T - Terminal Mode
X - 'High Speed Transmit Mode
P - Print All Counters
A - Add a Multicast Address
S - Change the SSAP Address
N - Change Destination Node Address
R - Re-Initialize the Data Link

M - Monitor Mode
V - Change Transmit Statistics
C - Clear All Counters
Z - Delete a Multicast Address
D - Change the DSAP Address
L - Print All Addresses
B - Change the Number Base

Figure 17. Menu of Data Link Driver Commands

1-15

inter

AP-235

Clear All Counters - Resets all of the counters.

reinitialized, and the selftest diagnostic and loopback
tests are executed. The results of the diagnostics are
printed on the terminal. The possible output messages
from the 82586 selftest diagnostics are:

AddlDelete Multicast Address - Adds and Deletes
Multicast Addresses.
Change SSAP Address - Deletes the previous SSAP
and adds a new one to the active list. The SSAP in this
case is this stations LSAP. When a frame is received,
the DSAP address in the frame received is compared
with any active LSAPs on the list. The SSAP is also
used in the SSAP field of all transmitted frames.

Passed Diagnostic Self Tests
Failed: Self Test Diagnose Command
Failed: Internal Loopback Self Test
Failed: External Loopback Self Test
Failed: External Loopback Through Transceiver Self
Test

Change DSAP Address - Delete the old DSAP and add
a new one. The DSAP is the address of the LSAP
which all transmit frames are sent to.

Change Base - Allows all numbers to be displayed in
Hex or Decimal.

Change Destination Node Address - Address a new
node.

5.2 A Sample Session

Print All Addresses - Display on the terminal thestation address, destination address, SSAP, DSAP, and all
multicast addresses.

The following text was taken directly from running the
Data Link software on a 186/51 board. It begins with
the iSDM monitor signing on and continues into executing the Data Link Driver software.

Re-initialize Data Link - This causes the Data Link to
completely reinitialize itself. The 82586 is reset and

iSDM 86 Monitor, Vl.O
Copyright 1983 Intel Corporation
.G DOOO:6
**********************************************************.*****

• 82586 IEEE 802.2/802.3 Compatible Data Link Driver •

•

•

***.*******************.***.*********.***.***** ••••••••••• ** ••••

Passed Diagnostic Self Tests
Enter the Address of the Destination Node in Hex -> 00AA0000179E
Enter this Station's LSAP in Hex - > 20
Enter the Destination Node's LSAP in Hex - > 20
Do you want to Load any Multicast Addresses? (Y orN) -> Y
Enter the Multicast Address in Hex - > OOAAOOllllll
Would you like to add another Multicast Address? (Y or N) -> N
This Station's Host Address is: 00AA00001868
The Address of the Destination Node is: 00AA0000179E
This Station's LSAP Address is: 20
The Address of the Destination LSAP is: 20
The following Multicast Addresses are enabled: OOAAOOllllll
1-16

inter

AP-235

CO!11lllands are:
T - Terminal Mode

M - Monitor Mode

x-

v-

High Speed Transmit Mode

Change Transmit Statistics

P - Print All Counters

C - Clear All Counters

A - Add a Multicast Address

Z - Delete a Multicast Address

S - Change the SSAP Address

D - Change the DSAP Address

N - Change Destination Node Address

L - Print All Addresses

R - Re-Initialize the Data Link

B - Change the number Base

Enter a command, type H for Help - > P
Good frames transmitted:

24

Good frames received:

1

CRC errors received:

o

Alignment errors received: 0

Out of Resource frames:

o

Receiver overrun frames·:

0

82586 Reset:

o

Transmi t underrun frames:

0

Lost. CRS:

o

SQE errors:

9

Maximum retry:

o

Frames that deferred:

4

Enter a command, type H for Help --> T
Would you like the local echo on? (Y or N) --> Y
This program will now enter the terminal mode.
Press 'C then CR to return back to the menu
Hello this is a test.

*'

,"C CR
Enter a command, type H for Help --> M
Do you want this station to transmit? (Y or N) --> Y
Enter the number of data bytes in the frame --> 1500
Hit any key to exit Monitor Mode.
of Good
Frames
Transmitted
#

32

#

of Good
Frames
Received

o

CRC
Errors

Alignment
Errors

00000

I' CR "'
Enter a command, type H for Help --> X
Hit any key to exit High Speed Transmit Mode.

*'

I' CR
Enter a command, type H for Help --> R
Passed Diagnostic Self Tests
1-17

00000

Receive
No
Resource Overrun
Errors Errors
00000

00000

inter

AP-235

5.3 Terminal Mode
The Terminal mode buffers characters received from
the terminal and sends them in a frame to the cable.
When a frame is received from the cable, data is extracted and sent to the terminal. One of three events
initiate the UAP to send a frame providing there is data
to send: buffering more than 1500 bytes, receiving a
Carriage Return from the terminal, or receiving an interrupt from the virtual terminal timer.
The virtual terminal timer employs timer 1 in the 80130
to cause an interrupt every .125 seconds. Each time the
interrupt occurs the software checks to see if it received
one or more characters from the terminal. If it did, then
it sends the characters in a frame.
The interface to the async terminal is a 256. byte software FIFO. Since the terminal communication is full
duplex, there are two half duplex FIFOs: a Transmit
FIFO and a Receive FIFO. Each FIFO uses two func-'
tions for I/O: Fifo_ln() and Fifo_Out(). A block
diagram is displayed in Figure 18.
The serial I/O for the async terminal interface is always
polled except in the Terminal mode where it is interrupt driven. The Terminal mode begins by enabling the
8274 receive interrupt but leaves the 8274 transmit interrupt disabled. This way any characters received from
the terminal will cause an interrupt. These 'characters
are then placed in the Transmit FIFO. The only time
the 8274 transmit interrupt is enabled is when the ReFunction
FIFO_T_IN()
FIFO_T_OUT( )
FIFO_R_IN( )
FIFO_R_OUT( )

ceive FIFO has data in it. The receive FIFO is filled
from frames being received from the cable. Each time a
transmit interrupt occurs a byte is removed from the
Receive FIFO and written to the 8274. When the Receive FIFO empties, the 8274 transmit interrupt is disabled.
The flow control implemented for the terminal interface is via RTS and CTS. When the Transmit FIFO is
full, RTS goes inactive preventing further reception of
characters (see Table 1). If the Receive FIFO is full,
receive frames are lost because there is no way for the
data link using class 1 service to communicate to the
remote station that the buffers are full. Lost receive
frames are accounted for by the Out of Resources
Frame counter.
The Async Terminal bit rate sets the throughput capability of the station in the terminal mode because the
bottle neck for this network is the RS232 interface. Using this fact a simple test was conducted to verify the
data link driver's capability of switching between the
receiver's No Resource state and the Ready State. For
example if station B is ~ending frames in ·the High
Speed Transmit mode to station A which is in the Terminal mode, frames will be lost in station A. Under
these circumstances station A's receiver will be switching from Ready state to' Out of Resources ~tate. The
sum of Good frames received plus Out of Resource
frames from station A should equal Good frames transmitted from station B; unless there were any underruns
or overruns.

Table 1 FIFO State Table
Next State
Present State
EMPTY
IN USE
IN USE
FULL
FULL
IN USE
IN USE
EMPTY
EMPTY
IN USE
FULL
IN USE
IN USE
FULL
IN USE
EMPTY

Action
Start Filling Transmit Buffer
Shut Off RTS
Enable RTS
Stop Filling Transmit Buffer
Turn on Txlnt
Stop Filling FIFO from Receive Buffer
Start Filling FIFO from Receive Buffer
Turn Off Txlnt

SEND FRAMES

RECEIVE FRAMES

ASYNC
TERMINAL

231421-15

Figure 18
1-18

inter

AP-235

Recv_Data_l() will discard any UI frames received
unless it is in the Terminal Mode. When in the Terminal Mode, Recv_Data_l() skips over the IEEE 802.2
header information and uses the length field to determine the number of bytes to place in the Receive FIFO.
Before a byte is placed in the FIFO, the FIFO status is
checked to make sure it is not full. Recv_Data_l()
will move all of the data from the frame into the Receive FIFO before returning.

5.3.1 SENDING FRAMES

The Terminal Mode is entered when the Terminal_
Mode() function is called from the Menu interface.
The Terminal_Mode( ) function is one big loop, where
~ach pass sends a frame. Receiving frames in the Ter·
minal Mode is handled on an interrupt driven basis
which will be discussed next.
The loop begins by getting a TBD from the 82586 handler. The first three bytes of the first buffer are loaded
with the IEEE 802.2 header information. The loop then
waits for the Transmit FIFO to become not EMPTY,
at which point a byte is removed from the Transmit
FIFO and placed in the TBD. After each byte is removed from the Transmit FIFO several conditions are
tested to determine whether the frame needs to be
transmitted, or whether a new buffer must be obtained.
A frame needs to be transmitted if: a Carriage Return is
received, the maximum frame length is reached, or the
send_frame flag is set by the virtual terminal timer. A
new buffer must be obtained if none of the above is true
and the max buffer size is reached.

When a frame is received by the 82586 handler an interrupt is generated. While in the 82586 interrupt routine the receive frame is passed to the LLC layer and
then to the UAP layer where the data is placed in the
Receive FIFO by Recv_Octal_Data_l(). Since
Recv_Data_l() will not return until all of the data
from the frame has been moved into the Receive FIFO,
the 8274 transmit interrupt must be nested at a higher
priority than the 82586 interrupt to prevent a software
lock. For example if a frame is received which has more
than 256 bytes of data, the Receive FIFO will fill up.
The only way it can empty is if the 8274 interrupt can
nest the 82586 interrupt service routine. If the 8274
could not interrupt the 82586 ISR then the software
would be stuck in Recv_Data_l() waiting for the
FIFO to empty.

If a frame needs to be sent the last TBD's EOP bit is set
and its buffer count is updated. The 82586 Handler's
Send_Frame() function is called to transmit the
frame, and continues to be called until the function returns TRUE.

5.4 Monitor Mode
The Monitor Mode dynamically updates 6 station related parameters on the terminal as shown below.

The loop is repeated until a 'C followed by a Carriage
Return is recieved.

The Monitor_Mode() function consists of one loop.
During each pass through the loop the counters are
updated, and a frame is sent. Any size frame can be
transmitted up to a size of the maximum number of
transmit buffers available. Frame sizes less than the
minimum frame length are automatically padded by the
82586 Handler.

5.3.2 RECEIVING FRAMES

Upon initialization the UAP module calls the Add_
Dsap--Address(dsap, pfunc) function in the LLC module. This function adds the UAP's LSAP to the active
list. The pfunc parameter is the address of the function
to call when a frame has been received with the UAP's
LSAP address. This function is Recv_Data_lO.
Recv_Data_l() looks at the control field of the
frame received and determines the action required.

The data in the frames transmitted in the Monitor
Mode are loaded with all the printable ASCII characters. This way when one station is in the Monitor Mode
transmitting to another station in the Terminal Mode,
the Terminal Mode station will display a marching pat~
tern of ASCII characters.

The commands and responses handled by Recv_
Dat~l() are the same as the Station Component's
commands and responses given in Figure 15. One difference is that Recv-.Dat~l() will process a UI
command while the Station Component will ignore a
UI command addressed to it.
# of Good
Frames
Transmitted

# of Good
Frames
Received

CRC
Errors

Alignment
Errors

No
Resource
Errors

Receive
Overrun
Errors

32

a

00000

00000

00000

00000

1-19

intJ

AP-235

5.5 High Speed Transmit Mode
The High Speed Transmit Mode demonstrates the
throughput performance of, the 82586 Handler. The
Hs-'Cmit_Mode() function operates in a tight loop
which gets a TBD, sets the EOF bit, and calls Send_
Frame( ). The flow chart for this loop is shown in Figure 19.
The loop is exited when a character is received from the
terminal. Rather than· polling the 8274 for a receive

buffer full status, the 8274's receive interrupt is used.
When the Hs-'Cmit~ode( ) function is entered, the
hs~tat flag is set true. If the 8274 receive interrupt
occurs, the hs_stat flag is set false. This way the loop
only has to test the hs_stat flag rather than calling
inb( ) function each pass through the loop to determine
whether a character has been received.
, The performance measured on an 8 MHz 186/51 board
is 593 frames per second. The bottle neck in the
throughput is the software and not the 82586. The size
of the buffer is not relevant to the transmit frame rate.
Whether the buffer size is 128 bytes or 1500 bytes,
linked or not, the frame rate is still the same. Therefore
assuming a 1500 byte buffer at 593 frames per second,
the effective data rate is 889,500 bytes per second.
This can easily be demonstrated'by using two 186/51,
boards running the Data Link software. The receiving
stations counters should be cleared then placed in the
Monitor mode. When placing it in the monitor mode,
transmission should not be enabled. When the other
station is placed in the High Speed Transmit Mode a
timer should be started. One can use a stop watch to
determine the time interval for transmission. The frame
rate is determined by dividing the number of frames
received in the Monitor station by the time interval of
transmission.

231421-16

Figure 19. High 'Speed Transmit Mode
FlowChart

1-20

inter

AP-235

APPENDIX A
COMPILING, LINKING, LOCATING, AND RUNNING THE
,
SOFTWARE ON THE 186/51 BOARD
*********

*""******

Instructions for using the 186/51 board

Use 27128A for no wait state operation, 27128s can be used but wait states will have to be added.
Copy HLBYT and LO.BYT files into EPROMs
PROMs go into U34 - HI.BYT and U39 - LO.BYT on the 186/51 board

JUMPERS REQUIRED

WIRE WRAP

Jumper the 186/51 board for 16K byte PROMs in U34
and U39 Table 2-5 in 186/51 HARDWARE REFERENCE MANUAL (Rev-DOl)

E36-E47IN
E39-E44IN
E79-E45IN

186/51(E5)

E151-E152 OUT
E152-E150 IN
E94-E95IN
E100-E1061N
E107-E113IN
E133-E134IN

186/51 (5)/186/51

E199-E203 OUT
E203-E191 IN
E120-E119IN
E116-E1121N
E111-E1071N
E94-E93IN

USE SDM MONITOR
The SDM Monitor should have the 82586's SCP
burned into ROM. The ISCP is located at OFFFOH.
Therefore for the SCP the value in the SDM ROM
should be:
ADDRESS
FFFF6H
FFFF8H
FFFFAH
FFFFCH
FFFFEH

also change interrupt priority jumpers - switch 8274
and 82586 interrupt priorities
E36-E44 OUT
E39-E47 OUT
E37-E45 OUT

E43-E50 IN
E46-E47IN
E90-E4BIN

E43-E47 OUT
E46-ESOOUT
E44-E4BOUT

DATA
XXOOH
XXXXH
XXXXH
FFFOH
XXOOH

To run the program begin execution at ODOOO:6H

1-21

inter

AP-235

I.E. G DOOO:6
GOOD LUCK!

-

..........

submit file for compiling one module:

••••••••••

run
cc86.86 :F6:%O LARGE ROM DEBUG DEFINE(DEBUG) include(:F6:)

exit
••••••••••

submit file for linking and locating:

.,.. ........

run
l1nk86

:F6:assy.obj, :F6:dld.obj, :F6:llc.obj, &

:F6:uap.obj, lclib.lib to :F6:dld.lnk segsize(stack(4000h)) notype
10c86 :F6:dld.lnk to :F6:dld.loc&
initcode (ODOOOOH) start (begin) order(classes(data, stack, code)) &
addresses(classes(data(3000H), stack(OCBOOH), code(OD0020H)))
oh86 :F6:dld.loc to :F6:dld.rom
exit

••••••••••

submit file for burning EPROMs using IPPS:

ipps
i

86

f :F6:dld.rom (OdOOOOh)
3
2
1

o to

:F6:1o.byt

Y

1 to :F6 :h1. byt,
y

t 27128
9

c :F6:lo.byt t p
n

C :F6:hi.byt t p
n

exit

1-22

••••••••••

inter

AP-235

IPCO/USR/CHUCK/CSRC/DLD. H

.

1 •••••••• *** ••••••••••••••••••••••••••* ••••••••••••••• •••••••••••••••••••

·••

*

••••••••_••••••••••••••••••••••••••••••••••••••••••••••••••**** •••••••••••1

.dofino INUSE

o

.CI.'ine EWTV

I
2

.dofino
.dofino
.d •• in.
.dofino
.define

FULL
FREE

I

TRUE

I

FALSE
NULL

o
OIFFFF

.define RBUF _SIZE
.deflne TBUF _SIZE
.define ADD....L£N
ed.'in. f'IIUL TI_ADDR_CNT

I:2B /. ,..cI1vI bu.f .... sizl . /
128 /* 't"Anl.it bu'fl" t1z1 *1
6
16

'"ped., unsigned short int u_Iho1't'

'*

"'Ilults '1"011 T'lt_LinkO:

laadld into Self_T'lt chI'"

.d.fin. PASSED

.deflne
.doflno
.doflno
.doflne
/* F .... m.
ed,'in.
ed.'in.

ed"ine

edl'ine
ed"ine

FAILEDJlIAQNOSE
FAILED..L/'BK_INTERNAL
FAILED_LPBK...EXTERNAL
FAILED..L/'BK_TRANSCEIYER

*'

CallYUndl
UI
XlD
TEST
P.J' _BIT
C_RJlIT

ed"in.

*'

0
3
4

'*

0103
OlAF
0lE3
OlIO
0101

OSAP_CNT

I

a

*' *'*'

/* UnnUllbll"ld Information F,.. ... I
ElchAn •• Identification

1* R.llat. Loopblc Ie T.lt
1* Poll/Fin.1 8it POlltion

'*
S

COlMland/R •• pon •• bit in SSAP

*'

*'

I . Numbe" of .llowabl. DSAPsl mu.t b• • Multipl.
of 2**N, • nd DSAP .dd" •••••••• ign.d must b •

divi.ibl. bU 2*.(S-N).
(I .•. the N L.SB. must b. 0) *'

*'

_d.fin.

DSAP _SHIFT

:I

I · DSAP _SHIFTS mu.t .qu.l S-N

.d.fin.

XlD_LENQTH

6

I. Numb.,. a. Info b,t •• '01' KID R.spon ••

'* S".t.m

Con.igu1"etion Pointe,. SCP

.t"uet BCP

•,.••• *'

*'

'*

u_short .,.bull
82:586 bus ,ddth, 0 - 16 bit.
1 - S bit • • ,

231421-17

1-23

intJ

AP·235

IPCD/USR/CHUCK/CBRC/DLD. H

'*

u_oh01't JunH2J,
u_shol"' :l.epl,
low.,.. 16 bit. D' i.ep .dd" ••• *1
u_.hort t.cph,
/. uPP." B bit. of i.ep .dd.,. ••• *1
),

'* Int ....... di.". S,.t.m Configul'ation Point.,. ISCP *'
ot1'uct ISCP (

)

b.'a",. tt. fit,. ....
.'t."
,....••cant1"ol
d inl *'
.,.t
blocll . /
.v.te.. cont'rol blocll . ,

U_.hD ... t off •• t

/ ••• t to 1 bl\l cpu
c 1•• .,..d ltV 82:t86
J
/ . of, •• t of

u_,hort ba •• 1
u_,ho ... ' .....a

J
J

u_'ho"t lIu ... ,

,

'* b••• of

CA,

1* Sv.hm Cont1'ol Blod SCB *1

ot1'uct SCB

u_.hort .tat,
u_.ho"t
u_'hort: cll1_off •• t,
u_.ho,., 1"._o •••• t,

,.d,

U_.hD'I"t '1"C_.,,1'"

u_.ho"t .In_err.,
u_,ho ... t
u_,ho,., DY1' _e,.r'J

'*'*
'*'* o••••tt
'* CRt

"',C_."''I"''

),

stT'uct

CB

u_sho1't
u_sho ... t
u_sho ... t
u_shoT't
u_sho ... t:

s,.t.
cad,
linkl,
p."'1I11

pa"tn:z,

*' 0' *'
*'

accu.ulated
/. Al itn ..ent ."1'ora
F1'atn•• last becaus.
no R.sau ... c ••
Ov .... 1'un .1'T'a1'.

'*'*

*/

*'

o' fh'".t 'ra... d.,c1'ipta1' in RFA ./

.1''1''01''

'* Statu.
0'
Ca .... nd
/*

*'

Statu. ",o1"d
COlllmand word . /
O•••• o. fi".t co. . .nd block in elL

Co. . .nd

*'

*'

1* link flold *1

'* Para•• t.,.. *'

U_ShDT't p.T'il3J
u_shoT't ,aT'1I4,
u_sho,.t p.T'1I8,
u_sho1't p ......6'

st,.uct ",,_CB(

u_sho,.t stat,
u_ahoT't c.d,
u_oh01't link'

0' COII••nd
'* Status
Co.and ./
/*

*1

1* Link fleld *1 ,
u_shaT't ac_cnta I . NUllbeT' 0' Ie .ddT' ••••• • ,
ch.r .cJdd,.[ADDJ,EN*HULTl-l\DDR_CNTJ,
HC .ddre . . n •• *1

'*

),

1* Tnn . . U Buffe1' D"c1'lph1' TBD *1

.t1'uct TID

(

231421-18

1-24

intJ

AP-235

IPCD/USR/CHUCK/CSRC/DL.D. H

1* Nu_b.,. of bvte. hi buffer *1
1* of'set to next TBD
1* 10wel' 16 bits of buffer add1"ess *1
u_thort buff_hi
1* upp .... B bit. of bu'f.r addl'ess *1
.truet TB _bu" J t r '
1* not used b .. the 586: u •• d b\l the

u_shart act_cntJ
u_shart 1inkl

*'

u_short buff_II

.oft .... ". to savi .dd,.las translation
routine.
*1
1* Tl'ansmi t Bu,f.1's *1
.t'l"uct T8

<

Cho1lT data [TBUF _SIZEl;

),

1* F,..III DeSCTiptor FD *1
st1"uc:t

FD
u_sho,.t

.t.t,

*'

1* Status Word of FD *1
1* EL and S bit.

u_short al_s,
u_short linlll
u_shoT't 1'bd_o'f •• t,

1* link to next FD *1

1* Rlceivl buflfer descriptor offset *1

char d •• t_.ddrCADD_L.ENll/*Destination address *1
chaT' src_addrCADD_LEN]; 1* Source .dd1"ess *1
u_thort length,
1* Length field *1
),

.truet

RDD (

u_short
u_shol't
u_shol't
u_short
u shol't

1* Actual number of bUtes received *1
1* Of'.et to nell t RBD *1
1* Lower 16 bits of buffe" add,.ess *1
1* upper 8 bits of buffe" add,. ••• *1
1* SiZR of buffe ... *1
1* not used b~ the 586: used bU the

IiIct_cnti

I inlo
buff _I;

buff_hi
.izes
si',.uct RD *buff -Itr;

soft..,.re to save add,.es5 translation
routine.

*1

/* Receive Buffers *1

.t,.uct RD

ch.,. data[RBUF _SIZE];
),

struct

FRAI'IE_STRUCT
(

unsigned char
unsigned chaT'
unsigned chaT'

d •• pi
.sap;
cmdl

),

1* De.tination' Service Access Point *1
1* SOUT'c. SeT'V1Ce Access PDlnt *1
ISO Data Link Command *1

'*

1* L.6AP Addres. Tlilble *1
.true t LAT (

stat;

1* INUSE Dr FREE *1

231421-19

1-25

intJ

AP-235

IPCO/USR/CHUCK/CSRC/DLO. H

int

<.p_I.p_func) (),/* Point.,. to LSAP function, ••• oci.t.d
11111 th d •• p .dd,. ••• *1

_t'ruet "AT
cha,.
chI'''

•• '
'* "vltic
actual
1*

stat,

lNUSE

add,.tADDJ.ENl,

1*

Add,. ••• Tabl.

FREE *1
AIle add ...... *1

01"

*'

.},

.truet FLAilS {
.

unsigned dial_don.
unsilned st.t_on:

J

unstgned "' •••
unsigned ...... t..."end

1
1
1

t_....

unligned Ipbk_t •• t:
unsilned Ipbk_IIod.:
}

Ideflne
Ideflne
Idefine
Ideflne
Ideflne
Ideflne
Ideflne

,

ELBIT
EOFBIT
SBIT
IBIT
CBIT
BBIT
DKBIT

I
1

I
I
I
I
I

dlagno •• co_and cOlllpl.t.
'* n.twoT'k
diagnostic statistician/a"
t
t
*1

/*

/. don't ", ••• IIIhen this bit is ••
/* " ••• , IIhen this bit ts •• t *1
/. loopback , •• t flag . /
1* laopback lIod. an/of' *1

*1

*1

O,BDDD
O,BDDD
0,4000
0,2000

o,aooo
0,4000
0,2000

1* SCI p.tt .... n • • /
CX

o,aooo

FR

0,4000
0,2000
0,1000
0,0080
0,0100
0,0010
0,0040
0,0700
0,0070
0,0040

Ideflne
Ideflne
Ideflne
Ideflne
Ideflne
Ideflne
Ideflne
Ideflne
Ideflne
Ideflne
Idoflne

RESET
CU_START
RU_START
RU-",BORT
CUJlASK
RUJlASK
RUJlEAOV

Ideflne
Ideflne
Ideflno
Ideflne
Idoflno
Idoflne
Idoflno
Idoflne

NDP
IA
CDNFlllURE
MC_SETUP
TRANSI1IT
TDR
DUMP
DIAIINDSE

CNA
RNR

0,0000
0,0001
0.0002

0.0003
0,0004
0.0005
0,0006
0,0007

231421-20

1-26

inter

AP-235

IPCO/USR/CHUCK/CSAC/OLO. H

Idofino
Idofino
Idofino
Idofino
Idofino
IUfino
Idofino
Idofino
'dofino

CIIDJ1ASK
010007
NOERRBlT
012000
CDLLIIASK
OIOOOF
DEFERIIASK
010080
NDCRSIIASK
010400
UNDERRUNIIASII
010100
SGEIIASII
010040
IIAXCDLIIASK
010020
OUT_OF_RESOURCES 0,0200

Idofino
Idofino
Idoflno
Idofln.
Idofi no
Idofino
Idofino
Idofino
Idofino
Idofino
Idofino
Idofino
Idofino
IUfino
Idoflno
.de'tn.
Idofino
.dofino
.doflno
Idofino
Idoflno
'dofino
.doflno
'dofln.
.doflno
'dofino
Idoflno
Idoflno
Ido'ino

FIFO_LIII
BYTE_CNT
SRDY
SAV.JIF
ADDRJ.EN
ACJ.DC
PREAII_LEN
INT_LPBCK
EXTJ.PBCK
LIN"'pRIO
ACR
BOF JET
IFS
SLOT_TIllE
RETRY_NUll

010800
010008
010040
010080
0101000
010800
012000
014000
018000
010000
010000
010080

I.

OlbODO
oloaoo
OIFooo

, . IFS

PR"

0.0001
010002
010004

u.o FIFO 11 .. of B . ,

, . no p"io,.ttv

*'

ti ••
us.e *'
'*
.10t tl •• :51. i2 u•• ,
/ . r.tl'V nUllb.,. 1!t *'
9.6

*/

BCJ)JS
IlANCHESTER
TONOSRS
OloooB
NCRC_INS
010010
CRC_Ib
010020
IT_STUFF
010040
PAD
010080
CRSF
010000
CRS_SAC
010800
CDTF
010000
, . no collision d.tect 'Ut.,.
CDT_SAC
018000
IIINJRKJ.EN 010040
I . 64 b .. t ••• /
KINJ)ATAJ.EN IIINJRKJ.EN - IB
1* a.lu ••• Ethernet/IEEE 802.3
41,. •••• with 6 bVt •• of .dd,. •••

*,

*'
231421-21

....

1-27

intJ

AP-235

IPCO/USR/CHUCK/CSRC/DLD. C

1**•••••••••••••••••••••••••••••••••••••** ••** ••••••** ••••••••••**** •••••
*
*
82586 tMndleT'
..
*•••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••****••••**1
*
..

.define
Idefine
'define
Idefine

CB_CNT
FD_CNT
RBD_CNT
TBD_CNT

B
16

64
16

'*/. Nu_be,.
0'of availabl. Co....nd Blocks d•• c1'ipto".
NUllbe" of availabl. Receive
'* Nu_beT' of available Tran•• Buff.,. d•• c,,.iptors *'

Idefine INTERNAL.J.OOPB/ICK
'define EXTERNAL.J.OOPB/ICK
.define NO.J.OOPB/ICK

.do.lne TI~Rl_CTL
.define TUIER1_CNT
Idefine TI~2_CTL
Idefine TlI'IER2_CNT

1* I/O *1
Int
in..,'),

*1
availabl. Fr ••• D•• cT'ipto.,.. *1
Bu".",
it

Nu ....,.

/*

014000
018000
010000

OIFFSE
OIFFSB
0lFF66
OIFF60

*'
*'*'

'*

/ . input wO'l'd : in.(add1" ••• )
output IIDT'd: Dutw(addr •••• Value) *1

void

Dutil",

void

intt_intvC), /* initlaliz. the inter1"upt v.eta,. t.b1.
enable')'
enab1. 80186 int.,.,.upts
di •• ble').
, . di •• bl. 80186 inteor ... upts

void

void

*1

'*

*'

'* o.t• •paint.or
e, ..ent value *'
I. NULL

*1

1* tleCorD "tvpe" D' d.finitions *1

Ide.ine Cat.

out.CO.CB,O)

,- the cOlMland to i.su • • Channel Attention *1

'*

.de'lne ESI.J.OOPB/ICK out"tOICB.OI
put the ESI In Loopbuk *1
Idefine NO..ESI.J.OOPB/lCK· out.tOI,ca. BI
take the ESI out of Loopback *1

'*

*'

.de.tne EOJ_SOl30
outb COIEO, 0163)
1* End D' Jnt.l' ... upt
.deflne TI~1_EOIJlO1B6 out,.tOIFF22.01041 1* EOI for Tillor 1 on the lB6 *1
ad.'in. TJ"ER1~aJ_aol30 outbCOIEO,OI64) '-EOI 'Gor 186·s Tim .... l on the 13~ *1

231421-22

1-28

AP-235

IPCO/USR/CHUCIVCSRC/DLD. C

, ...........,.0..-..,
tnt Self_Telt'

u_Ihol"t temp'

alloc.tion . . . . . . . . . . . . . . . . ,

'*/. t ••po".1"\1

used fa,," diagnoltil::: pUl'pOI ••

.to...... • ,

Id."n. LPBKjRAI1E_SIZE
4
.her
Ipbk_'rell.tLPBKjRAIEJlIZEJ •
0."1 OxAA, aI'S, OIM),
*d.'ine whaami_io_add
O.OOFO
ch."
... hoamiCADDJ.ENl,

unligned long

u_,hort;:
u_short
unligned long
u_Iho1't
U_IhoT't

un' i lined 1Dnl

u_sho"t

'*,*

*'

<

*'

1/0 .ddT-." of HOlt Add,. ••• Prom
Ram aT"'.'" \alh.,.. hOlt .dd,. ••• is .ta,..d . /

DOod_l.it_cntl
unde"ru"_cnt,
no_e,.,_cnt •
. def.r_ent,
.,e_e,.. ... _ent'
•• ,_col_ent,
.... Cy_,,. ••• _cnt'
,. ••• t_entl

'*'* SVita
.. Configur.tion Point.,.: Rail Initialization
struet
lep •
010000, 0.0000, O.IFF6,
'* stl'uct
ilcp;
Intel' ••
SI,I.t .... Configu,..tion Paint.,. *'
.t,.uet sca sebJ
'* Swat .... Cant,.ol Block -,
st,.uet
'*
Blacll.
SCP

*1
010000),

buIV • 1.
pll'p-:>o' ••• 1 ; . Off •• tC •• cb),
pilcp->b ••• l • SEQMT « 4.
phep->b . . .2 • (SEllIn» 121 • OxOOOF ,

*'

'* '*

pNULL a BuildJ't,.(NULLII
" build. NULL paint.,. - 8086 tvp.: 32 bih "
BuildJU.C)J
inlt Receive Fr.,.. A" ••
Build_CbC)1
lnit Ca ••and Blacl!: lilt *1
ma_cb. clld - O.
/ . multic •• t addre ••••
inlt */

".pho".

leb .• tat • OJ

foT' ( i • O.

i

<-

OxFFOO,

i++)

231421-25

1-31

inter

AP-235

IPCD/USR/CHUCK/CBRC/DLD. C
if (Icb .• tat •• (ex I CNA)>>
br •• 1I1

If (I :>OIFFOOI
Fata1C It DLD: inlt - Dld not get an int:.,.,.upt •• ter Re.et/CA\n"),
1* Aell: the r ••• t Int.,. ... upt . ,
ocb.cmd - (CX I CNAII
CAl
Walt_Sc b () I
En.b 1o_586_Int () I

Icb. cbl_off •• t - Df, •• tC'cIt(01),
Icb.

,.'8_0"5.' - Off •• tC"dCOl),

,*

link ICIt to eb and ,d lilt. *1

1* move the ~T'O. bVt •• into ... hoa ... ! aT'''.''

f.,.

*'

01 I (ADDJ.ENI 1++1
.. h .... 1[ (ADD_LEN - 1 I - Il - Inb ".h •• ml_I._add + 1*211
(I •

'*

Inltiallzati.n tho Multica.t Add,.. . . T.bl.

foT' (pmat . . . .8tCO]1

pmet

<-

IcmetCt1ULTJ-"DDR_CNT -

*'
III p•• t++)

pmat->.tat - FREE.
C.nflgu,..( INTERNALJ.DDPBACKII

1* Put 586 in int.,.nel loopback *1

S.tAdd,. ••• C),

'*

run diagnostics *1

If (Solf_T•• t

!- PABBEDI

".turneS.I._Te,t).
C.nfigu,..(NO_LDDPBACKII

'*

C.n.igu,.. the 82586

*,

Bui Id..Rf.( I

<

.truet
struet
struet

FD
RBD
RB

unsigned long

f.,. (pfd

*pfdl
.prltd.

.,bu',
baddJ

= &fdlOll ,p.d

(~

&fdIFD_CNT -

III pfd++1

pfd->stat = pfd->el_5 • Oi
pfd-:>Unk - Df'ut(pfd+lll
pfd->1"bd_o .. , •• t • NULL,

231421-26

1-32

AP-235

IPCD/USR/CHUCK/CSRC/DLD. C

*'

1* point to &'dCFD_CNT - 1] *1
1* last I'd link is NULL
1* l •• t fd h •• EL bit •• t *1
1* point to first 'd
pfd->rbd_of, •• t - O" •• tC&rbdCO])s
1* link fir.t fd to first Tbd

end_I'd Ii:I --pfds
pfd->11nk • NULL,
pfd-:>el_s • ELBJTs
b.gin_fd =- pld • II:fd[Oll

= a.:,.bd[O],

for (pI"bd
bad d

SEQ"T

IS

«

*'

pbu". &!,.bu'[Ol,

prbd

buff _1 • b.dd,

pT'bd->bu" _h • badd »
prbd->bu" ,...pt,. - pbufl

prbd->act_cnt..

16,

OJ

prbd->linll .. Of, •• tCprbd + 1)1

prbd->.il . . . RBUF_SIZEJ
.nd_1'bd III: --pTbd.
p,.bd->l inll .. NULLJ
p1'bd-)sil' J. ELBITJ

1* la.t rbd paint. to NUL.L
1* la.t rbd hal .1 bit •• t

*'*'

b.gin_rbd = lt1'bd[Ols

Build_Cbe)
{

.truct
.truct
struct

'*

Build • • tacle of

'r"

callm.nd blacks *1

CD .pcbJ
TBD *ptbdJ
TD
*pbu'J

unsigned

long

b.ddJ

for (pcb - Ircb[OJ; pcb <- 'cb[CB_CNT pcb->st.t - 0;
pcb->cllld • ELBIT;
pcb->l ink • Off •• t(pcb + 1).

1l;

pcb++) (

--pcb,
begin_cbl ... end_cbl - pNULLJ
pcb->link - NUL.L.
cb_tos • &cbtOl,

1* Build a stack of transmit buffer descriptors *1
'or (ptbd

a

IItbd[OJ,

pb,...

IS

Cctbu'[Ol;

ptbd

<=-

Cctbd[TBD_CNT - ll;
ptbd++,

pbu'++) -(

ptbd->ut_cnt • TBUF _SIZE,
ptbd->link - Dfh.tlptbd + II,
badd

a

SEIII1T

«

4,

231421-27

1-33

inter

AP-235

IPCD/UBR/CHUCII/CBRC/DLD. C

badd +- Off •• t(pbufJ,
ptbd->bu" _1 - badd.
ptbd->buff _h - b.dd
ptbd->bu" .,JItr • pbu',

»

--ptbd.
ptbd->link •

NULL.

tbd_tol • • tbd[OlJ

stl'uct

CB

16.

'*

1* l . . t tbd link is NULL *1
Set the Top 0' the Stack *1

.get_CbC) 1* ,..tul'n • painte,.. to • fre. command block *1

(

.t1"uct

CB .pcb,

if' (OffsetCpcb • cit tal) - . NULL)
,...tu1'nCpNULLJ,
cb_tos III Cst,.uct CB .> Build_Pt,.C.pcb->link)i
pcb->1 ink -= NULL,

return(pcb),
1* Put. Command Block beck onto the fre. lilt

*'

Put_CbCpcb)

.tT'uct

CB .pcb,

(

pcb-:>st.t .. 0,
pcb->1 ink • Offset (cb_tol) J

cb_tol - pcb,

stl'lJct TBD

*g.t_TbdC)

(

,tT"uct

TID

'* ,..tU1'n
• pOinte"
d."1'ipto1' *'

to • fre. t,.ansmit bu"e,.

*ptbd.

flags. r ••• t_s.m• • tJ
Di.abl._5B6_IntC ),

if (Cptbd • tbd_tosJ !- pNULL) <
tbd_tas. Cstl"uct TBD . , Bu:lld_Pt1'(ptbd->link),
ptbd->link z NULL.

Enab le_SSiI_lnt (),
flags. ", ••• t_s.m• • OJ
if, (fl.g •. ", ••• tJend

1)

Reset_586C ) J
",etu",nCptbdJJ
)

231421-28

1-34

inter

AP-235

IPCD/U5R/CHUCK/CSRC/DLD, C

.truct

THll

<

stT"UC

t

*ptbd.
*p ,

THO

, . find the end of the tbd li.t retUl'nltd.

=

for (p

ptbd;

p->11nk

!- NULL.,

P->Act_cnt • TBUF_SIZE,
p->11nk • O'f •• tCtbd_tal)'
tbd_tos

=

stTuct

CB

P

:III

ptbd is the beginning */

CstT'uct TBD .) Butld_PtT'Cp->l:lnk»

, . c1 ..... EOFBIT and update

.i,.

J

on l •• t tbd *1

ptbd,

.pcb;

Mifdef DEBUO
;f «pcb. Oet_CbC»
•• pNULL)
Fatal("dld. C - SetAdd" ••• - couldn't get .. C8\""),

•• 1 ••
pcb

Iond i f

III

Get_Cb();

1* DEBUO *1

bCDP,,« (cher .)ltpcb->p."ml • •whoemiI:Ol, ADD_L.EN),

pcb->cmd

:II

1* move the P1'OIl

addre •• to IA cmd

IA I EL.BtTi

*'

I.lue_CU_'md Cpc"),

faT' Cstat

:=II

FAL.SE,

.t.t •• FALSE, ) (

fo1' (i=O; i<=OxFFOO. 1++)
if Cscb.clld
0)

break,
i f <1 > OxFFOO) <
Buge"DL.D: 9cb commend nat c1 •• r\""),
CA;

else

stat = TRUE;
23142,1-29

1-35

inter

Ap·235

IPCO/USR/CHUCK/CSRC/DLD.C
)

Issue_CU_CmdCpcbl 1* Gueue up a com.and and i.sue a
other co...nds a~e queued *1
.t~uct
CD *pcb;

.ta~t

CU co. .and if no

(

Dhable_5B6_IntC II'
if Cbegin_cbl aa pNULLI (
1* if the list is inactive sta~t CU *1
begin_cbl = end_cbl a pcb,
scb.cbl_off.et a Off.etCpcbl,
Wait_Scb(J,
scb. c.d - CU_START'
Set_Ti.eoutCI,
1* .et deadman time~ fo~ CU *1
CAl
)

el.e (
end_cbl->link a Off.etCpcbl,
.nd_cbl - pcb,
)

Enable_i586_lntC I,
)

In7C I
(

outbCOIEO. 01671;

1* EOI 80130 *1

)

Isr6C '(
W~it.C·\nlnte~ru-pt

outbCOIEO. 01661,

6\n"I,
1* EOI 80130 *1

)

Isr5C I
(
W~iteC"\nlnt.~rupt

outbCO.EO. 016511

5\n"l;
1* EOI 80130 *1

)

1* Deadman
ls~
(

Ti.e~

_Tim.outC I

1*

lnte~~upt S.~vice

Int.~~upt

-Routine *1

4 *1

R.s.t_TimeoutCI,
i. Cflags.~eset_sema _. 11
flag •. ~ ••• t-p.nd • 1,
.1.e
R•• et_586C II
TIMERljEOJ_801S61
TIMER1_EOI_801301
)

1*
1*

Int.r~upt
Inte~~upt

0 i. Ua~t in UAP Module *1
2 i. Ti.er in UAP Module *1
231421-3Q

1-36

intJ

Ap·235

IPCO/USR/CHUCK/CSRC/DLD. C

ioriO
(

W"itIC"\nlntll""upt l\n""
autb (OlEO. 016111

I. EOI 80130 . ,

'* 586 Int.rrupt ••rvici rautine:
U_Iho,.t
• ,,.uti;

Intl1"1'upt 3 . ,

Itat_Icb •
CB

.pcb.

Watt_ScbC).

leb. cmd -

Clt.t_lcb • leb.ltat) II (eX I CNA I FR : RNRh

CAl
If (stat_scb •

(FR I RNRII

Rlcv_Int_P"ac ••• tng C) I
if Cltat_lcb .. CNA) (

1* Ind of cb p"ac ••• ing *1

RII.t_Tilllout().
1* cl •• l" d •• dman ti.I"
pcb. BuildJt,.Clcb. cbl_o-p ••• t)1

*1

_lfdof DEBUQ
if (billin_cbl •• pNULL)(
BUll C"DLD: bl.in_cbl •• NULL in int'''l''upt TDutinl\n lll

) •

.,..tu1'n.
if «pcb-:>.t.t .. OICOOO) !- 018000)

Fatal ("DLD: C bit not •• t a,. B bit •• t in intll""upt 'routine\n").
_ond If I . DEBUQ . ,
..... ttch (pcb->cmd .. CMD_"ASK) (

c ••• TRANSMIT:

'* thilIqlcondition
b i t . 0 and th.,., ....... no
111111 occu" an the fi"st

if
callisianl -> Iq. IrY"o"
t"ans"is.ian if
th." .....". no colli.ions, a,. if the p".vious t"an •• it
command ".ach.d the rna. colli.ion count, and th. cU'r".nt
transmi •• ion had no colli.ion.

*'

if «pcb->stat •

(SOEMASK : MAXCOLMASK I COLLI1ASKII == 01

++5,._."" _tnt;
if (pcb->stat • DEFERI1ASKI

++d.'." _cntl

231421-31

1·37

inter

AP-235

IPCO/USR/CHUCK/CSRC/DLD. C

i f (pob-:>.tat • NOERRBIT)

++good_Imtt_cntl
.1 •• "
I ' (pob-:>.tat •

NDCRSI'IASK)

++no_c,.,_cn"a
i f (pob-:>.t.t • UNDERRU_SK)

++und.,.,.u"_cnt,
I f (pob-:>.tat • I1AXCOLI1ASK)

++•• x_col_cnt.

>

if (pcll-:>p.'I"lIl f. NULL)
Put_Tbd (Bui ld-"t~ (pob-:>puftll)).
b ..... lu

on. DIAQNOSE:
flilill. dial_dane· 1,
If «pob-:>.tat • NOERRBITl •• 0)
S.1f _T . . t • FAILEDJ)JAONOSE.
b,. •• 11I

d.fault:

if (pcb-:>linll •• NULL)

begin_cbl • pNULL,

begin_obi •

Build-"t~(pob->l1n~).

seb. cbl_of, •• t • pcb->linlu
Welt_SebC),
leb. elld - CU_START'

>

CA.
Walt_Sob (II
Set_Ti .. eoute).

,*

START d •• dman timer

*'

i f « pob-:>olOd • CI'IDJ1ASK) •• I'IC_SETUP)
pcb->cmd • OJ 1* cl •• .,. Me_SETUP elftd WO'l"',

tltis will implement.
lock •••• phD,.. 10 that it .. an't be reus.d until
i t is completed

el,.
Put_CbCpcb),
di •• bleO,
EOJ_80130.

'* Don't
".tU1'"
• ene".1 pu,"po ••

*'

It'. not' •
black 'rom, ,,. •• CD list *1

tIC_SETUP Cllld bloc-II.
comm.~d

/ . di •• ble cpu tnt 10 that the '86

i.,.

will not n •• t ttl

231421-32

1-38

intJ

AP-235

IPCD/USR/CHUCK/CBRC/DLD. C

Recv_lntJT"Dc ••• tnll« )
(

Itruet
.truet

.q,.

FD
RBD

.,fdl

'* point.
to
point. to

'*
/*

*prbd;

the Frame D"cl"iptD1'" *1
thl 1 •• t .... bd for thl ''' •• 1
pointa to the fi,.,t rbd 'or thl ,,. •••

*'*'

'01' Cpfd .. blgift_.dl p.d !- pNULLJ p.d • blgin_fd)
If Cp'd->.tat • CBIT! (
blgin_'d. C.truct FD *J Bu:lld-Pt'l"Cpfd->l:LnIlJ,
p,.bd • "t"uet RID .) Bu:lldJ't,.Cpfd->,.bd_of ••• tJJ
if Cprbd !- pNULL) (
chick to ••• i • • buff • .,. is attached

'*

*'

.Ifdof DEBUg
if Cpl"bd ,- '111"_1'bd)
Fatal ("DLD: prbd !- '1IIln_1"bd in Rlcv_lntJ,.oc ••• ing\n")1

. . ndif 1* DEBUg *1

'a,. (Il • p,.bdl (q,-).ct_,nt &.: EOFBIT) !- EDFBITI
II -

Cstruct RBD *1 BulldJ'trCII->linkll.

blll"_1"bd - C,truet RID .) Bu:lld-Pt1"CIl-:>link)1
11,-:>1 inll • NULLJ

>

I' Cpfd->stat • DUT_DFJlESDURCEBI

Put_F..... _RFA Cp fd ) I
,I •• -(
if thl DL.D il in a loopbaclr te.t,

'* (.la••. lpblr-JRade ••
i'

checlr the .,. ...e ,.ecv *1

1)

L.aopb.clr_Chec Ir (pfd) I
.1 ••
1* if it' • • flultic •• t .dd,. ••• check to ••• if it'.

in the lDultic •• t .dd,..,. t.ble, i. not di.c.,.d the ,,. .... e *1

If C IIpfd->dost_addr[Ol .011 PutJnoJlFACpfd I.
el.e
(
Recvj,. ... eCp.d)1
++,.ecv_'l"' ••• _cntl

011 •• C!ChockJlultlc ... tCpfdlll

>

.15.

0(

Ru_St.,.tC), 1* If RU h•• lone into no ,. •• ou,.ce., ..... t."t· it *1
b" •• lu

L.oopbac Ir_Chee II (pfd)

1* Called b\l Recv_lntJl... oce •• lngJ checlr • • dd,. •••

.nd d.ta 0' potential loapbaclr 'T' ••• *1
.tT'uct

FD

st1"uct RHD
.t"uct RB

*p.dJ
*prbdl
*pbu"

231421-33

1-39

inter

AP-235

IPCO/USR/CHUCK/CBRC/DLD. C
if ( b,.p«ch.", .) .pfd-),,,,cJlddrCOl • •who.mitO). ADDJ.EN) !- 0 ) (
PutjreoJlFAC p.d I.

>

r.turn,

,T'bd • Cst,.uct RID .) BUild1tT'Cpfd->l'bd_oP, •• t),

'*

point to .... ceive
bU".1" d.,c1'ipto1' *1 '
pbu' • (st'l'uet RS .) pT'bd->bu"Jtr, 1* point to ..... c.iv. bu".",
If C bCIRpCCch.,. *1 pbu', "lpbk_....... tOl.

*'

L.PBKjRAIIE_BtzEI !- 01 (

Putj"'.JlFACpfd I •

.,.etv.,.",

'lagl. Ipblc_t •• t -

I, ..

Putj"'.JlFACp.dl.

'*

p •••• d laopback t •• t

'* ,..tu,.nl t'l'ue

CheckJ1ultic •• tCp'd)
,t"uet
FD .p'd,
,true",

'0,.

*'

i . . .ultic.,' add".,1 tl in MT

*'

HAT .p ..at,

Cp ... t ...... ttOl. p•• t <. " ... ttMUL.TI..,ADDR_CNT - 11, pmat++1
i' C p ... t->st.t •• lNUBE ....
(bcmp«cha1' .) .p.d-)d •• t_addTCOl, .pmat->.dd'l'tOl. ADDJ-EN) ··0»
b'l" •• k,

i' Cpmat > ..... ttMULTI_ADDR_CNT - I])
,..tu,.n CFAL.SE I.
,,*tu,.nCTRUE),

T. . t.J-ink ()
(

Self_T •• t - PASSED,

Diagnos.e ),
i' CB.I. _Tnt •• FAILED,..DIADNOBEI
,..turn,
Ru_St.,.te),
, . sta ... t up the RU foT' loapbacll t •• ta
'I."s. Ipbll_ItDd • • 11 /* "D into loopb8cll Itod. */

'*'* ••

*'

*' *'

'Iags. Ipbk_t •• t • 01
t loob.ck t •• t to 'al ••
S.nd.-Lpbk_Fl"8111.C)1
int."'n81 loopb8Ck t •• t
i ' (.Iag •. Ipbk_t •• t •• 0) (
B.lf _Tnt· FAlLED.J-PBK_INTERNAL.
flag •. IpbkJlod • • 01
",.tUf'n'

'18.S. Ipbk_t •• t • O.
/* •• t .... nal loopback t.st
Configu",.CEXTERNAL.-LDOPBACK).
S.nd-.L,pbll_F,.8111.C ),
i. cn.g •. Ipbk_hst - 0) (
B.I._T.st • FAILED.J-PBKjEXTERNAL.

w'

ESI in Ipbk

*'
231421-34

1-40

inter

AP-235

IPCO/USR/CHUCK/CSRC/DLD. C
flilg •. Ipbll_rIIode .. 0;

return,
'lags. Ipbk_t ... t .. 0;
1* •• ternal loopbilck test through transceiver *1
NO_ESI_LODPBACKI
SendJ.p b "_Fr.... ( ) J
if (flags. Ipbk_t •• t _. 0)
So If _To.t = FAlLED_LPBK_TRANSCElYER.

Send_Lpbkjr ••• C)
{

struct

*ptbdJ

TBD

II

Int
flor (1 • OJ

i

<

BJ

i++)

<

*'

1* .end Ipbk fr .... S tim •••
b •• t .,fort del iv.,."

lince it's

_Udof DEBUg
if ((ptbd ~ got_Tbd 0) == pNULLl
FatalC"dld - SendJ.pblc_F".lIe - couldn't get. TBD\"");
ptbd .. get_Tbd(),

_end!' 1* DEBUg *1
ptbd->act- ptbd->buff,-Pt,., Iclpbk_',..ameI:Ol, LPBKjRAME_SIZE);

Diagnose( )
{

.truct

CB

.pcb;

_I,dof DEBUg
if «pcb - got_CbO)
pNULLl
Fatal("dld - Diagnol. - couldn't get III CB'n");

".lse
.end:i f

pcb

= Oet_CbOI

1* DEBUQ *1
flags. diag_dane - OJ
S.lf _Test .. FALSE,
pcb->cmd = DIAGNOSE

ELBITJ

Issue_CU_Cmd (pcb),

"'hile (flags. diag_dane a·O)

231421-35

1-41

inter

AP-235

IPCD/USR/CHUCK/CSRC/DLD. C

Can.tIU""« laop.l •• )

u_.ho"t 100p.lell'

,'-rue'

CB

.pclt,

.ifd.' DEBUg
if Ilpcb • got_Cbll) •• pNULL)
FatalC"dld - Con.ilu"" - cQuldn't I.t • CI\n"),
•• 1••

pcb. g.t_Clte),

•• nd if

1* DEBUg *1

pl:b-),.".1 • O.08OC.
pcb-)par-=Z: • 0.2600 I 100p'18.,

pcb-),.",.3 • 016000.
pcb-)parm4 • O.F200,

pcb-),.1'".' • 0.0000,
if 1I •• pU_, •• NDJ.DDPIACK)
pcb-)p.,..• • 0.0040,

.1 ••
pc 11'-),.",.6 • 0.0006,

pcb-)clld

• CONFICIURE

*'

1* loopbaclt ' .... m. i l l ••• but •• than
the lIintMuli ,,. ••• l.ngth

ELI IT •

)

1* S.nd a

''''.111.

*'

to thl cab1" p•••• ,oint.,. to the d•• tination .dd ......
and a ,oint.r to the ,i,..,t ,,..n •• U. buf"'" d'lc1'I,tol'.

Slndjr ••• e,tbd, p.dd) /. ,..tU,.nl '.1 •• if it tan't I.t • CO.llland black . /
.truct
. TID
*ptbd.
chat'
.p.dd,
(

.truet

CI

.pcb.
l.n,th.

if ((pcb. g.t_Cbll) •• pNULL)
'1 •••. ,.. ••• t_. . . . - 0,
if ( '1 •••. " ••• tJ.nd •• 1»
R••• t_~()J
, 1'.tu1'nCFALSEh
pcb->par .. l • D. . . . tlptbdl.

231421-36

1-42

inter

Ap·235

IPCO/USR/CHUCK/CSRC/Dl.D. C

'*

*'

mav. d •• tination .dd,. ••• to cD",•• nd block
bcaplJ«cha,. .).p,b->p.,.1II2. (char .)p.dd, ADDJ.EN),

'* calculate

the l.ngth ".1d IIv.au_ing up all the

fo1' Clongth - O. ptbd->Unk !- NULL.

bu".",

*'

ptbd - DulldJ't1'Cptbd->Unkll

l.ngth +- ptbd->.ct_cntl

l.ngth +- cptbd->act_cnt Ie OI3FFF)J

i.

/* check to •••

'* .dd

,._,u1,..d.

p.dding 1,

the l •• t bu'f.,.

*'

do not do p.dding an loopback *1

1* thia .. 111 nat wa1'k I f "INJlATA.J.EN > TDUF_SIZE *1
If CCl.ngth < "INJlATA.J.ENI.. 1* . . . u •• ' • 4 b~t. CRC *1
CbctlpClcwha.m:HO:J, (,h.,. .)p.dd. ADD.-LEN) !- 0»

J 'lu._CU_Cmd (pcb),

'la.l. ,. ••• t_••••• 0,
If Cfl.g •. ,.. . . t..JI.nd
R••• t_586C

11

)J

,..tu1'nCTRUE),
)

AddJlultlc •• t_Add,. ••• CplNl)
ch.,.
.p •• '

pm. - point.,. to multic.lt .dd" ••• *'
'*/. ,..tu'I'n:l."1
.a1 •• ,. •• n. the Multic •• .dd ......
*1
t:

tablo ia full

(

'* thenthe".turn
multica.t .dd,. •••
i,

i, •

duplicate of ane .11· •• dU in the ftAT,

*1

for (pm.t • m.t, pmat <- ... tU'ULTI~DR_CNT - 111 pmat++)
if ( p •• t->.t.t -- INUBE ••
(bemp( .p •• t->.dd,.[Ol, (char .) p.a, ADD..LEN) -.0»

r.tu'rnCTRUE)1

<

'01" (pmat - .... t, p.At c- . . . ttt1ULTJ,J\DDR_CNT - 111 p... t++)
i 9 (pmet->stet .- FREE) (

plII.t->stat - INUSEI

bcap~C

.p •• t->add1'[OJ.

Cch.,. *1 p••• ADD.J.ENI.

b,. •• k,

231421-37

1-43

intJ

AP-235

IPCO/USR ICHUCK/CBRC/DLD. C

If

(pm.' :> ..... ttI1ULTIJlDDR_CNT - III (
fl1ag •. r.s.t_..... = O.
if ('lags ....... t..JI.nd -- 1)

Reset_'S6() J
returnCFALSEJ,

SetJ1ultic •• tjlddr ••• C),
'lags. r ••• t_•••• - OJ
if ('1 •••. ,. ••• tJend •• 1)
R••• t_5B6( ),

retu1"nCTRUEJ,

Deletlt_"ultic •• t_Add'l" ••• Cp •• '
cha'"
(

1* returning ,.1 . . . . . . na the lIultica.t: .-dd,. •• s

*,..,

... a nat found

*'

<- ... tntULTI_ADDR_CNT - 111 p . .t++)
pm.'-:>s'.' - INUSE ••
(bell, ( .pfNt->add,,[O], (char.) pilla, ADD.-LEN) . - 0»
p •• t->.tet • FREE,

'01' (p ...at - .at' , •• t
if (

bre.k.
if (p ... ' :> .... ttI1ULTIJlDDR_CNT - III (

.1ag •. r ••• t_. . . . . 0,
if ('lag8. 'I" • • • t...,P.nd .- 1)
Re.e'_5B6( I,
return CFALSE) J

S.tJ'lultica.t-.Add,. ••• C),
'1 ..... ,. ••• t'_••••• OJ
if ('lags. ,. ••• tJ.nd •• 1)
R••• t_586( ),

retu1"nCTRUEJ,

SetJ1ulticast_Addr ••• ( )
(

.t,.uct
.truet

"AT
"A_CB

*p.atJ
*p.a_cbJ

i • 0;
pma_cb • 8cma_cbf
whil. (pma_cb->cmd !- 0)
p ..a_cb-:>llnk • NULL.

J

1* if the f1A_Ca i. inus., .... it until i t ' . f" ••

*,
231421-38

1-44

AP-235

IPCD/USR/CHUCK/~SRC/DLD.

C

'01' «pmat • met' pilat <- Icmat[t1ULTI.-ADDR_CNT - 11, p... t++)
if C pmat-).t.t •• INUSE) (
bCDPU C 'p ... _cb-:> .. c __ ddr[ iJ. 'p ... '-:>.ddr[Ol. ADD_LEN).

i +- ADD..J-EN.

pm._cb->ltc_cnt - il
p ..._cb-:>clOd - "C_SETUP I ELBIT.

'* R.turn
Fra .. e D•• cl'iptor and Receive Buf'."
D•• c1'ipto",. to the Fr •• Receive Fr ••• A,. • • • /

PutJr •• ..RFACpfd)

FD
RDD

It1'UCt

.prbd.

,..tu1'ned
'*'* points
to
of
*' *'
/. indicat •• ..,hethe,. to r •• t.,.t RU *'
points to beg inning of

ell.l
ru_'t.'I"t_'Pl.I_fd,

end

RBD 1 tst

,..tu1'ned RBD lilt

ru_,t.rt_'l·lI_rbd,
'18gl. r ••• t_...... 1,

ru_start_'lal_'d • ru_st.,.t_'l.l_rbd • FALSE,
pfd-).l_s ... ELBIT,
pfd->st.t =- 0;
p,.bd • (struct RDD .) Build-pt,.Cp'd->rbd_o'f •• t), /. pick up the link to the rbd
pfd-)Unll • p'd-)rbd_of, •• t - NULL,

*'

'*p,.og,.am.

Di •• bl._586_IntCh this command is onl\l n.c.I •• ,." in a multitasking
Ho .... v.,. in thil lingl. t.sk envi,.an •• nt thil "autin. il a,.ig1nal1\1
called f,.om ilr _586 ( ). therefa". int.,.,.upts are al"e.dv disabl.d *1

i f Cbogin_.d -- pNULL'
begin_.d • end_fd .. p'd.
else (
end_.d->linll .Df's.t(pfdh
end_.d->.l_• • OJ
end_'d • ptldJ
rU_lt.,.t_'lag_fd • TRUEJ

if Cprbd !- pNULL)
'Dr Cq

m

1* if there il a rbd .ttached to the fd then
find the beginning and .nd of the rbd lilt *1

prbd. q-:>Unk !- NULL. q . Bu!ldJ"rCq-:>Unk))

q,->act_cnt • OJ
1* no .. pt"bd points to the beginning of the rbd Ust and
II. paint' to the end of the l'st *1
q-:>Iizo • RBUF JlIZE I ELBIT.
q,->act_cnt • OJ

231421-39

1-45

AP-235

IPCO/USR/CHIICK/CSRC/DLD. C

'*c"•• t •"".r.
• n...

i l nothinl on the lilt
I i i ' */

if

~

'egin_"bd - p"b ••
end_I'lId - "
if Cprbd !- q)

,.u_I,."'_.I •• _,,bd • TRUE,

'*

if

,t. ..... il 110". than an. ,.bd

.... tu,.n.d

.t.,.,

'*

the RU . /

*'

if the ".bd Iii' al1· •• d" •• ,.ts add on
tb. n .... .,..tu"n ..... bd.
.nd_'I"bd->link • D" •• tC,,.II&I);

.nd_"bd-:>.I •• - R8UF _SIZE,
.nd_1". . . .

ctl

1"U_It.,.t_'l •• _"bd • TRUE,
}

If

'*

C~u_ota~t_flag_fd

....

~u_ota~t_flag_~bd)

Ru_8t.,.t ( ).
Enable_:I86_lntC h

t.

Dl •• bl*_586_lnt() t. u •• d above . ,

fla,l. r ••• t_...... O.
if (fl •••. ,. ••• 'J.nd •• 1»
R••• t_586C ),

RuJltutc)

<

if «Icb. stat. RU-"ASK) . - RUJ'EADY)

If CCbe.ln_fd-)otat • CIIT) -

,...tu,.n •

'*then return

if the RU i . al,. •• d" '" •• dV'
*/

CIIT>

.... in_'d-:>"bd_o., •• t - Dff •• tCb •• :l.n_"bdh /* link the ".ginning of the I'bd
Uot to the Unt fd *1
Icb. ,,'a_of, •• t • O" •• tCb.gin_.d)J
w..it_Scb( ),
.cb. cfltd • RU_START,
CAl

Sa.t ..a",eJte •• t ()

<

scb. cllld • RESET,
CAl

Wdt_ScbClI
J •• U.Jt ••• t_CMd.( )

<

WaitJlcbC )1
acb. ctld • CU_START'
CAl

231421-40

1·46

AP-235

IPCO/UBR/CHUCK/CSRC/DLD. C

out .. ( OxFF'E, 0)

J

Dut .. ITlIlER1_CNT. 01,
'Qutw(OxFF5E. OICOO.),
whil. «in ... (OJlFF~) • 0.00:20) -

0)

*'

1* if PIa. Cnt bit il •• t before eNA
:h •• t, 596 emd de.dlocked

if C(Ieb .• tat Ie CNA) . - eNA)
b,. •• lu

if

(Ieb . • t.t

• eNA !- eNA)

Fat:alC"DLD: 1 •• ue.ft ••• t_Clldl - Co ..Mnd d •• dlocll dU1'ing "'It.ltt procedure\""),

R.I.t_Ti •• out C) I
leb. emd - CNlu
CA,

'*

Acll"o,lI1.d.1I CNA inter1"upt

*'

Wait_Scbl I,

1*

e •• cute

• 1' • • • t, Configul"l, S.tAdd"' •••• and rlC_S.tup.
R.e.iv. Unit And the COII•• nd Unit *1

th.n r •• te,,'I: the

Ro . . t_'SIoII
(

MT
i,

++,. ••• 'I:_C"'I:;
Di.abl._SB6_lntC ),
ESJ_LOOPBACK,

Soft".-r.,jt ••• t () J

fo1' C :f. • OJ i <- OIFFOO, i++)
if DIFFOOI

'*

Fatale "DLD: inl'1: - Did not I.t an int,,,,",upt . f t .... Soft ...". R•• ltt'n"),
Aell the 1' • • • t

Jnt.1'1'upt _,

Wait_ScbO,
Icb. cmd • (eX t CNA),

CA,
WaitJlcbC I,

IUdo. DEBUg
if ( b •• in_cbl •• pNULL)
F.t.l("DLD: b •• tn_cbl • NULL tn R.let_5B6 H
londi f

),

I. DEBUg . ,

231421-41

1-47

Ap·235

IPCO/USR/CHUCK/CSRC/DLD. C

1* Canflgun t h 586 *1

*' t.,..,

1* Eth.,.net default ,.,. •••

del.ul t pa ......

lt.,.,

Conftllu'r,1 il not n.c •••• ,." IIIh.n ulin.

,..,_cb. link - NULL,

,.,.,.1 •

"'I_cb.
OxOBOC,
1'.,_cb. p.,..2 • 012.00,
"1'_CIt. parm3 • 016000.
"I'_CIt. p.,.114 • OxF200,

,.I,_cb. p.,. ..5 •
, ".,_clt. p.,....
".,_clt. cmd

0.0000,

010040.

• CONFIOURE , ELIJTJ

leb. cb1_off •• t • O, ••• 1;("'.,_cb. Itat),

J •• UIJf ••• t_CMdIC h
1* Set the Individual Add,. •••

*'

bcopU«ch.,. .) Ie,..,_cb. p.,.1ft1, &lIIh'01 .. 1[01, ADD-.L,EN), 1* lIIove thl

'''011

add,..sl to IA cmd

*'

1"UI_R.•• et_CfldIC ),

'* ,.,load
i

the multic'lt .dd,. •••••

- ".,-",a_clt. st.t •

,. •• .JII._clt. 1 ink •
'a~

*'

o.

N~LI

Cp..at ...... teOl'

p ..at

<- ..... tCI'lULTI_IIODR_CNT

if ( pmat->Itat •• INUSE ) (
badd~[Ol.

IIODJ.EN),

r".JII"_clt. mc_tnt • I,
,. •• .In._cb. c.d • I'1CJlETUP I ELBJTJ

Icb. cb l_olPleto: • Off •• to:(Ic,. •• .JI._cb. stat),
Issu._Reset_elld.( )J
1* R•• t:.,.t the ColIftftI.nd Unit and the Receiv. Unit

*' "

flag •. 1" ••• t_. . . . . O.
flag •. ,.e.etJend • O.

ND..ESI.J-OOPBIICK,
R.cv_lntJ»1"Dc.ssing ( »J

Icb. cbl_o'fI.et • begin_cbl'
Walt_B

•• 1 • • • 2.
nll\lt •••
IIIhtl. (nll,., •• -- . . . . 1++ -

••:2++),

.... tu1'nC.--.l - *--12),

231421-43

1-49

AP-235

IPCD/USR/CHUCK/CSRC/LLC. C

*******·.*****·············***···**····**··**.****.*****••*•••••••,.

**1 ....***** ••

IEEE e02.2 Logical Link Cont1'ol Lave..
(Station Component)

..

..

**•••**************.***.*.*.*.**************••• *.***** *.**** ••*****.**********1
.include "dld. h"
•• t .... "

ch.,.

.pNULL,

.xt.,..n

struet

ext.,.n

chaT'

TID ..o.t:_TltdC),
*8uildJt"()J

" •• donl" cha,.
xid_f .... m.tXIDJ.,ENQTHl. -C O. O. XID. O.Bl. Ox01. 0),
1* DSAP, SSAP, KID. xid cl ••• 1 ,. •• pon •• *1

.t,.uct LAT lattDSAP _CNTl,
Init..Llc()
{

.t1'uct

LAT

fOT (plat. 1e1attOl, plat

<-

8clattDSAP_CNT -

ll,

plat++'

plat->.tat • FREE,
,..turn( Init_586(»'
1* Function fa,. .dding .. ne ... DSAP *1

AddJ) •• p.-Addr.I.(d •• p, ,func)

int dsap,

(*pfunc)

'*

DBAP .Ult be divisible b .. :Z*.CB-N), IIIh.,..
2**N • DSAP _CNT. Ci .•. N LSBs must b. 01The function ..,ill ,..tuT'n FALSE if do •• not
m•• t the .bov. "eq,uiT'enl.nt.~ aT' the lo •• p
Add" ••• T.ble i . full, at' the add "e •• h ••
• l"e.d .. been us.d. NULL DSAP add",e •• i.
'I"e •• "v.d '01" the St.tion Companent *1

()I

{

.t"uct

LAT

if (Cd •• p « CS-DSAP_SHIFT) .. OxOOFF) ! - 0 II d •• p -- 0)
,..tu1'n (FALSE),

1* Check 'OT" duplic.te d •• ps. *1
if ( (plat - .. lateds .. p » DBAP_SHIFTl)->stat
P lat->stat • INUSE,
plat->p_s.p_'unc • pfunc;
1'.tu1'n (TRUE),

-= FREE)

{

.Ise
retuT'nCFALSE);

1* Function faT' deleting DBAP • • ,
neleteJ) •• p..AddT' ••• Cd •• p) I. I. th. speci.ied connection e.i.t., i t i • • ev."ed.
I. the connection do •• not •• is.t, th. co_and Is ignoT'ed. *1

231421-44

1-50

inter

AP-235

IPCO/USR/CHUCK/CSRC/LLC. C

Recv_FrameCpfd)
struct FD

struct
.truct

struct

*pfdl
*prbdi
.pf.;
.platl

RBD

FRAME_STRUCT
LAT

p1"bd • (stl'uct RBD *) Build1trCpfd-)T'bd_offset)i
pfl • • (struct FRAI'1E_ST~UCT *) prbd-)buff_ptl'l

if (pfd->1'bd_off •• t

,- NULL) ( 1* The,.. has to be
to the fd,
too shoT't.

if (pf.->d •• p -- 0) (

iI

rbd attached

or .15e the fl'ilme
*1

i~

1* if the frame is addressed to the Station

Component,

then,. respon •• me" b. required

*,

if ( ! (pf.-:> ••• p &.: C.-R_BIT) ) (/* if the '"am. received is a response.
inst •• d of ill command, then reJlI'ctl it.

aecau •• this Bafh,a .... doe. not implement
DUPLICATE_ADDRESS_CHECK. -> no response
fram •• should be ... ecy'd *1
Stati an_Component_Response (pfd) I

'* nat add,. •••• d to St.tion Component.

*1
1* check to ••• if the d •• p addressed 1s lIc:tivI *1
oliO I f ((pfl->d •• p <:<: (S-DSAP _SHIFT> .. O.OOFF)
0 ....
. (plat - .. laU(pfl->dup) » DBAP_SHIFTl)->stat .- INUSE ) {
(*plat'-)p_,.p_func) (pfld).
1* call thl function ••• ociated
with the ds.p rlclived . ,

retU1"nl

>

Put_F1" •• _RFAtpfd)i

1* .,..tu,.n the pfd 1f nat given to the use,. saps *1

Station_ComponentJt.lpon •• (pfd)
st,.uct

FD
*p,., • • •ptfsi
*blgin,..ptbd. *q.

Itruct FRAME_BTRUCT
st,.uct TSD
struct RBD

.ptbd.

*pT'bdl

=

prbd
(Itruct RBD .) BulldJ'trCpfd->rbd_ofhot),
p,., • • (ItT'Uct FRAME_STRUCT .) p,.bd->bu"_pt,. •.
• ",1 tch Cprh->cmd ..

~P

J'_BIT>

{

case

XID:

231421-45

1-51

AP-235

IPCO/USR/CHUCK/CSRC/LLC. C

while «ptbd •

O.t_Tbd()

. - pNULL) I

ptbd->oct_cnt - EOF81T I XID_LENgTH,
bcop .. «chaT' *) ptbd->buffJtT, aclid_f,..m.r;Ol, XJD-.LENQTH);
pUs. (.t~uct FRAI'IE_STRUCT *1 ptbd->buff ..... t~,

ptfs-')cmd - p,,"s->c.d.

c...

ptfs->d •• p • pT'f.-> ••• p I C_R_BITi J* .,..tUT'n the , .......
to the sende,.. *1
ptfs-> ••• p • O.
while' !SendJ"AlieCptbd, Build_Ptf'Cpfd->.,.,_ add,.»)1
br •• k,
TEST:

fo,. Cpl'bd •

CstT'uct RBD .) Bul1dJltl'Cpfd->rbd_off •• t),
II. •

beginJtbd •
p~bd

whil. Uptbd • Oet_Tbd()

•

pNULL,

prbd !-. pNULL,

8ui1d--"t~(p~bd->link))

•• pNULL).J

1f (II. !- pNULL)
q->Unlc • Off •• tCptbd),
el ••
b.ginJtbd :. ptltd,

ptbd->act_cnt • p,.bd->.ct_cnti
bcoPIJ«ch." .) ptbd->buffJtT'.
II.

ptfs •

D

(char.) prbd-:>buffJt1",
ptbd->act_cnt Ie O.3FFF).

ptltdJ
,.tf'uc:t FRAME_STRUCT

*>

beginJtbd-'>buff .. ptr;

ptf.->cmd - p,.f.->Clldi
ptf,->d •• p • P1"II'->55., I C_R_BITI

1* l'etu.,.n the frame to
the send • .,. *1
ptfs->ssap • 0;
whi le( !Sl!'ndJra•• (beginJtbd, Build_Pt,.Cpfd-:>."c_addT')).
b.,. ••• 1

231421-46

1-52

inter

Ap·235

IPCD/USR/CHUCK/CSRC/UAP. C

, ..****.............**** •••••••••••••••• ***•••••••••••••••• *.*****.********.***
*..
Use" Application Pl'ogl'am

*
..
..

Asunc to IEEE B02. 2/802. :3 Protocol Converte"

LF
CR
BS
BEL
SP

**1

*'

1* ASCII Ch.,.ect.,..
ESC
O,IB

IIdoUno
.deftne
IIdofino
lido Uno
IIdoHno
IIdofino

..

**···.·.***........ *

*
••••••••••••
***.......................***••••••** ••••••••

OIOA
0,00
0,09
0,07
0,:/0

.de"n. DEL
IIdoHne CTL_C

Ox7F
0,03

1* Hard ....,.. *1
IIdofino CH.JI_CTL
O,OODE
lido Uno CH_A_CTL
O,OODC
lido Uno CH.JI_DAT
O,OODA
IId,'ino CH-A_DAT
O,OODS
IIdoUn. UART_STATJlSK
0,70

'*

°

Intl"'1'upt ca.es fat' 8274 *1
IIdofine UART_TX_B
.dofino UART_RECV_B
O,OB
IIdoUne UART_RECV_ERR_B O,OC
.doUno EXT_STAT_INTJI 0,04
IId.fln. EXT_STAT_INT-A 0,14
char

fifD_t[25bJJ

ch.,.
'l'o_,,[256JI
ch.,.
...,..C5J, ..,rbC5JJ
unsigned
char
In_'::I.'o_1o. out_hfo t.

u_lhort

In_'lfo_1', aut_fifo_t'. actual;

t_buf _stat. ,. _bu' _stat;
cbufCB01J
1 in.,[Sl],

1* Command line buff.,. *1
1* Hanitor ,",od. displilU lin.

*'

unsignld
cha,.
dsap, ss.p, Sind_flag, local_.choi
ch.,.
DI.t_Add,.[ADD,J.ENll
cha,.
Multi_Add,.CADD_L.ENll

'*

int tmstati
teT'min.l made status: for l.aving terminal mode *1
int dh,x, monitor _fl1ag, hs_,tat;
1* fllags *1
Ilt.,.n
Ixtlrn

struct TOO
char

*get_TbdO,

extl ... n

st,.uc't: FLAGS

flagsl

Ixte ... n
ext.,.n

char
cha,.

.BuildJ't~( )i

lid_,,.ameClJ
whoamitl;

231421-47

1-53 .

inter

AP-235

IPCD/UBR/CHUCK/CBRC/UAP. C

•• t.,,"
•• t.,,"
•• t.,.n

stl'uct
st'l'uct
ch.r

•• t."n
•• tern
e.t.rn

unsigned long
u_short
u_sho"t

•• t.,,"
•• t.,."

elt.,,"
•• t.,.n

IlAT
LAT
*pNULL,

unsigned long

u_sho"t
u_short

e.t.,,"

unsigned long
u_sho,.t

•• t.,.n

struct

'*

BCB

rute],
latl:l.
gOOd_lilt t_cnt,
unde",.u"_cntJ
no_c,.,,_cnt;
defe,,_cnt.
.",._."1' _tnt,
",.x_col_cnt.
".cy_f"••• _cnt.
,.. ••• t_cnt'

seb,

Macro' t\lp.' of definitions

'define
'define
'define
'deflne
'define
'define
'define
'define
'define
'define
'define
'define

*'

RTB_DNB Dutb ICHJI_CTL. 01011), Dutb ICH_B_CTL. ""bCIIJ ...rbCIIJ 10102)
RTB_DFFB Dutb ICHJI_CTL. 01011), DutbCCHJl3TL ...rbCIIJ ...rbCIIJ ..OIFD)
RTB_DNA DUtb CCH.J\_CTL. 01011), Dutb CCH_A_CTL ..... CIIJ_. . CIIJ 10102)
RTB_DFFA DutbCCH.J\_CTL. 01011), DutbCCH.J\_CTL ...r.CSJ·.... CIIJ ..OIFD)
UART_TX..pIJI Dutb ICH_B_CTL. 0101), Dutb CCHJI_CTL ...rbCI J...rbC IJI

1211),

'*

Dutb (OxEA, OaOO),
Timer 1 lnt.rl'Uptl' eve,.., . 12~ .ee: *1
send_'Uag • FALSE,
e: • inb(0IlE2); 1* ,. •• d the 80130 lnt.".".upt M •• "..,I.t.,. *1
OUtbCOIE2, OIOOFB • c); 1* ",,.ite to the 80130 int.,.,.upt .. alk ,..giste,. *1

231421-48

1-54

intJ

AP-235

IPCD/U5R/CHUCK/CSRC/UAP. C

Di •• ble_Timer_lnt( )
(

tnt

Ci

c = inbCOxE2);
autb COxE2, 0.0004 Ie),

COCc)
cha,.

el

while ( CinbCCH_B_CTL) •
autb (CH_B_DAT, c) I

4) . - 0 ),

CHI
(

11th! 1. C Cinb (CH_I_CTLJ Ie 1) • • 0 lJ
rotuTnCinbCCH_BJ)ATI 110 0.7FI,
R•• dCpmsg,

ent.

pact)

che,.
.pmag'
unsigned cha"

ent, .pact,

unsigned ch.,..
I,
ch.,.
c. buft2001,
fiaT" ( i •

0,

c •

(c

!- CR) , . (c != LF) It&.

(:i

C 198),

) {

c • Ci () 81 Ox7FI
If Ce •• DS II e == DEL)
if Ci > 01 (

--1,

CaCDSI,

lIse

CaCSPI,

>= BPI
CoC, ),
bufC 1++1 -

CaCBSI,

if Ce

(I

=-

81 ••
if (Cc

CAl II (c
buft 1++1 • CRI

1;11.

L.F»

{

bu.t i++l • L.FI
}

.1s. CaCBELl

J

}

CaCCRl, CaCLFJI
If C i > entl

.pac t = cnt,

1151

.p.et • 1,
i

<: .pact

.pmag++ •

buftil,

fo1' (1 .0,

J

i++)

231421-49

1-55

Ap·235

IPCO/USR/CHUCK/CSRC/UAP. C

unligned char

1.

R•• d (lIcbufCOl. eo. ..ctual) I
I • SHpllocbuf[O]J,
returnC cbu'[ i l),
Wl"iteCp"'lg)

,hal'

.p.",

",hile '.pmlg !- '\0') -(
if
111
'\n')
ColCRJ,
Co(.pmll++"

'*p.'••

'*

FataICpm'g)
",rit. _ ......... to the Ic,..en then atop *1
che,.
*pmlg'

Wl"ite("Fatal: 1111
W,.iteCpm.g),
foT'(, J "

DugCpmsg)
ch.,.

'/* "rtte • m•••••• to the .e,.. •• n then continue *1

*pmsg,

WrtteCIlBug;

N);

WriteCpm •• ',

'*

A,.cii_To_Ch.,.Cc)

cha"

« '0' <-

c)

i f « 'A' C-

c)

if

convlT't ASCII-H •• to Cha,. *1

CI

returnC Ii -

...

(c

'0",
••

(c

<- '9'»
(-

'F'))

returnee - 0.37),

If «la' (c c) •• (c (1'lturn(c - OaS?),

Ifl/»

,..turnCOaFF',
Low.", _Ca.1 (c)
ch.r

<

«'.' (-

c)

if «'A' C-

c)

if

..

(c

<- '1'»

••

(c

<-

,..turn (c) I
,.,turn(c + 0.20';

'l'»

1"etu1'nCO',

231421-50

1-56

inter

AP-235

IPCO/USR/CHUCIVCSRC/UAP. C

Ch.,,_To.-Asci!(c. c:h) 1* convert c:h." to ASCII-He. *1
unsigned char
Co th[]1

unsigned char

ii

i = (c II: a.FO) » 4.
if (i < 10)
cheOl ... i + Ox30;

al ••

cheal = i + 0.37.
j = (c " OxOF) ;
i f (1 < 10)
chell CI i + 0130;

else
ch[ll = i
cht2J ;;:: '\0',;
Slcip(pmsg)
ch.T'

+ 0,37,

'*

skip blank. *1
.pmagi

11

tnt

fo,. (i ..

01

.p ... g

raturnCi);
R•• d_lnt ()

<

=-

t

,

J

i++.

pmsg++) I

1* Read a 16 bit Integer *1
wd. wh. wdl. whl, Ji
i. dan •• hex. doveT",

foT' (dane -= FALSEi done •• FALSE!
R•• dC&':cbu.pC01. 80. &cactuaUI
i ,. SlcipC&':cbuftOl)1

haverl
) (

for Che .... dover'" hover" FALSE. laid ... wh .. wdl .. whl ... 0;
(J • AscU,_To_CharCcbu'Ci]»
(. 15; i++) ..
I

jf

(J :> '1)
hex = TRUE;

wd
... h
if

= wd*tO + J;
= wh*16 + Ji
(llald

<

wdl)

dav .... -

TRUEI

if (wh <: ... hl)
hover ,. TRUEI
IaIdl •

Wdi

... hl •

"'hi

)

1F [cbufU] •• 'H'

II cbuf[i] ...... 'h' : I c:buf[ll •• CR ::
c:buf[ll == LF I: cbu"[il ......
'h' )
'H' II cbu"[ 1 J

i f (cbu"[ iJ
ho. l1li TRUE,
• f (hex == TRUE .... haver ~= FALSE)
done = TRUE,
i f (hex
FALSE
dover •• FALSE)
don .... TRUEI
.~

..

t

')

{

~~

....

231421-51

1-57

AP-235

IPCD/USR/CHUCK/CSRC/UAP, C

if C ~don.) (
WT'ti;e("\" Th1s nUMb." i . too Ittl. \" It ha. to b. le.1 than 65S3b. \n"),

W"tte(-'n Ent .....numb." --)

P),

)

el ••

WT'ttl(" 111 ••• 1 Ch.,..act.,.," Ent." a numbe", __ >"),

)

If (h.l)

,...tu1'n<-..")'

,..tu1'n(lIId )i

(valul, b••• , Id, chi wtdth) /. con".", an int •• _", to an ASCII It'l"ing *1
unligned 10nl
valUl1
u_short
b •••• width.
eha'"
che 1, Id,

Jnt_To~.c1i

fOT" (i - O. i < ,ddt'" 1++) (
J • "alul X b ••• ,
If (J < 10)
ch[i] - J + 0130,
81s1 ch[il • J + 0.37,
valUI • valul I b ••• ,

'aT' 'Ci • width - I. ch[tl _. '0' Me i ,. O. 1--)
chCiJ •
ch[lIIIidth] •

Id.
'\0'.

W1'it.j.ong_lntCdw,
unlignld long

u_Iho,.t

u_,ho,.t
ch.,.

t)

db..

ii

JI
ch[111,

If'(dhn)
In1:_To-"lc i i (dill.

lb.

81 ••

Int_ToJlsc i i (dOl. 10.
fo~

(J • OJ ch[ J] !- '\0',
lin.[i] • chtJ]'

Wrtt._Sho1't_lnthh
u_short .., li
u_ahol"t J'
c:h....
ch[61.
un_ilned 10nl
dill •

'.

'ch[O]. B),

" 'ch [0].
i--, J++)

1011

i)

dl.u

III.

i f (dbOl)

Jnt_To_AacU(dw,

16,

'0', .c:h[O],

4)1

.1.8

231421-52

1-58

inter

AP-235

IPCD/UBR/C/iUCK/CBRC/UAP. C
Int_To.-Alcitcdl.b 10, '0', "chCO],
for  ""

cnt) /* P.'&I -

*'

point.,. to the output m• • • • • • • ,

1* add - paint.,. to the ad dr •••

/. cnt - numb." of b\lt •• in thl addr ••• *1

ch.",

*P.SII' addt], c:ntl

'01' C I

;

)

(

WritlCplIlg)J
R•• dCltcbufCO], 80 • • • ctu.l) i
for (J - •• ipU.cbufC01), i
i <: a*cnt I i++.
if (C'O' <- cbufCJ1) lele (cbuf[J] <- '9'»
cbuftil a cbuf[Jl - '0',

.0,

els.
,I ••

if (C'A' <- cbu.tJl) , . Ccbuf[Jl
cbuftiJ • cbuftJl - 0137;

i' «'.' <-

<-

J++)

0(

'F'»

cbufCJ]) Ie.. (cbuftJl <:- 'f'))

cbufCl1 -

cbufCJl - 0.'7,

else (
Writ.(" Il1.g.1 Ch.".ct."\n")l
by-.alll
)

if (i :>= :Z*cnt br •• lli

1)

.par (1 .. 0, :I. <- tnt - 1, i++)
add[(cnt - 1) - il
tbuft:Z*l] « 4
";II

J

cbu '[2*i + 1J;

IWrit._Addr(padd, tntl
char
padd[ J. cnt;

i. c[3JI
fOr (

J

cnt )0

i

cnt--) (

231421-53

1·59

inter

Ap·235

IPCD/USR/CHUCK/CSRC/UAP. C

t • p.ddtcnt-llJ
C;h." _To_Asc it (i. lcetOl),
Wrt hClocCO] II
e[Ol •

"n',

ttll • '\0',
W,.tte(lcc[Ol);
)

<

at'ruct

FD

.,,,,.. .pt •••

.truet FRME_STRUCT
• truet TID
.t,.uet RID
char
tnt

*ptbd. *lIe,I"-Itbd. *ql
.prbd,

.,,,bu"
cnia

p1'bd =- CstTuct ABD .) Build.-pt1'Cpfd-:>,.bd_off •• th
pr'. - CatT'uct FRAtfE_STRUCT .) BUildJltrCprtuf->bu"Jtr),

... iteh Cprh->e1ld 10 ~P J JIlT>
<
ca..
01:
if Cllonitor_.lag)
b1' •• k.
1* Don't put d.t. in fifo unless in t.,.minal ,mod. *1
pTbu' •

(cha", .) ,,.,.,

'* •.,i,

p,..bu' +- 3,
ent • 3,
pfd->1.ngth -

ove'" the h •• d.,. info and point to the d.t. *1

3.
far ,(' prlld !- pNULL' tnt - o. p"bu' - (ch." .) p,.bd->buffJtrO)-(
fa,. ( f cnt < (prbd->."t_cn't II OI03FFF) ... ,'d->length':> 0,

ent++, p,..bu'++, pf'->length--) -(

whileC,,_bu'_stat •• FULL),
Fifo_R_ln (*'T'bu')J
pT'bd • Bui ld_ptr (pT'bd->l ink) I
II1II- 0 • ., pT'bd
!~ pNULL)
F.t.l("U.p: R.cv_D.t __ l(p'd) ")1

if (p'd-:>l.ngth

•• "dil 1* DEBUG *1
}

b,.e.lu

cas.

XID·

==

\IIhil. (ptbd - Oet_TbdO)
,NULL),
ptbd->act_cnt • EOFBIT I XIDJ-ENgTH,
bCOPItI (ch.r -) ptbd-:>bu"-pt"~ 8clid_fT'ant.[Ol~ XID_LENGTH);
,tfs =- c,t,.uct FRAPE_STRUCT .) ptbd->buffJtri
,tf.->cmd •

'1".->C."
,r'&->, •• , I C_R_BlTI 1* r.turn
the frame
to the sender *1
ptf.-:> ••• p - ".'1
while( !S.nd,Jr ..... ('tbd, - Sui ldJtr(pfd->,rc_addr»);

,tf.->dsap a

231421-54

1-60

AP-235

IPCO/USR/CHUCK/CSRC/UAP. C

case

TEST:
for (prbd •

(st'l"uc't RBO .) Bui 1 d1t,. Cpfd-:>rbd_offslrt),
q, -= begin-ptbd • pNULL, prbd ~. pNULL,

pl'bd • Bui Id_Ptr CpT"bd->l ink») (
...hil. CCptbd • aat_TbdO) ... pNULL),

If (q !- pNULLI
q-:>lInk - Offset (ptbd I.
el ••
begln..JItbd • ptbd.

ptbd-:>act_cnt • prbd-:>.ct_cnti
bCDPlltech.,. .) ptbd->buff_pt1',

(eh.,.

*)

p"bd->bu'f_ptr,

ptbd-:>act_cnt 8r O1lll3FFF);

!I - ptbd.
ptfo •

(.truet FRA"E_BTRUCT *1 begln..JItbd-:>buH..JItr.

ptfs->c.d • pr'.->cltd,

*,

C~JUTJ
, . ,..tut'n the f,..me to
the •• nd.,.
ptf'-)llap • , •• pl
!.Ifh Ue( !Sendj,..me Cbeg in...ptbd, Bui Id_Pt,. (pfd-:>src_addr) )) I

pt,.->d •• p • ,"'.-)II.p I

b,. •• lu

>
Put_Fr •• _RFA(pfd) I

'*

Fifo_T_OutC)
{

'*

ratu,.n the fra"'e

*'

c.alled b\l main p1'og"a", *1

c • fi'D_tCout_'l'o_t++lJ

'*

Di.able_Uart_lntC "
if (aut_fltflo_t •• in_,t'o_t)
if the fifo is ."'pt\l
t_bu._stet .. EMPTV,
,top fI:i.lling r,..nl",it Bu'f.,. D.,c,.iptar.
el..
if the fifla III.' full .nd il nalal d,..ining *1
,i' (t_bu'_lot~t .D FUL.L •• aut_flifla_t - SO ... in_fli'D_t) <
tu,.n Dn
tha spigot *1

'*

'*

*'

'*

*'

ATB_DND.
t_buf _,t.t • INUSEI

Eneble_U.,.t_lnt( ),
,.eturn(c ),
1* c.lled b\l UiII1't receive intaT'1'upt *1

F1fo_T_ln(c)

cha,.

c.

fiflD_tl:in_'i'D_t++l == Ci
If (t_buf _"tot == EI!PTYI

231421-55

1-61

inter

AP-235

IPCO/UBR/CHlJCII/CSRC/UAP. C

.1..

'_bu._.ta' • JNUSE, 1* .t .... , filling T,...nlilit Buffer D.scriptor *1
1* if th.,.. are onlv 20 locationa l.,t, turn of' the .pilot
If Ct_bu'_stat •• INUBE •• in_'lfo_t + l!O out_'lfo_" (
RTS3IFF8.
'-'ul _Itat • FUL.L,

'*

Fifo_R_Oute)

<

called ltV ,,..nl.i'l: int ....rupt

if (out_fifo_r ••

1"_'1'0_")

r _bu, _stat • E"TYJ

'*

*'

*'

if the fi'a i , ••ptv

*'

'* the "fa ".1 full and ,. nOIll d,..inlng *1
C,,_bu'_stet - FULL . . out_'I'o_" - SI - in_fifo_")

.1..

if

If
l' _bu' _,tat • INUSEf
,..turnCC )i

Fifo_R_InCcl
cha...

CJ

'*

cell •• bU Recv.J)4lte_lC) *1

'l'o_"l:ln_"'o_",++) - CI
Dheblo_U. . t,;,lntC II
If C,,_bu'_stat -- EI'I'TV)
UART _TX_EI_B.
CoCO).
I. pri . . th internpt *1
r _bu, _,tat. JNU8E.

el..

if

'*

*'

if the bu",,,, i. full. indicat. it
C1'Ju,_,tat - lNUSE •• 1"_"'D_" _. out_'i'o_1')
r_bu,_,tat • FULLJ

Eneblo_U. . t_lntC ).

outbCCH_B_CTL. 21.

'* point to RR2 In 8274 *1

u .. UART_TXJI:
'if (,,_buf_Itat •• EI1PTY)

UART_TXJlIJI.
RESET_TX_INT •
• 1 ••

ouU CCHJlJlAT. Flfo--,,_OuU».
b ..... ~J

231421-56

1·62

AP-235

IPCO/UBR/CHUCK/C8RC/UAP. C
c . . . UARTJlECV_ERRJI:
Dutb (CHJt_CTL.

1),

'*

paint to RRI in 8274

.t.t • inb CCH_B_CTL) J

*'

DutbICHJI_CTL. 01301,
i f I.tat .. 0.0010)

W,..:lt.C"\nP.,..it" E"raT' Detected\"");
if

C .t.t

.. 0.00201

Wl'ite''''nDve.,.run ET'l'or Detected\n");
i f I .t.t .. 0.0040)

Wl'i t. C• \nF"ellling Error Detected\"")J
b,. •• lu

c •

inbCCH_BJ)AT),

if (hi_stat •• TRUE) (
hs_stat • FALSE.
br •• lu

i' (local_echo)
CoCc"
:1,"

(c.

••

'*

'*

Flag to t.,.minet. High Spe.d Transmit mode . ,

*'

echo the cha" back to the t.,.lft1n.l, could cause
a ,,..namit overrun if TI inte"1'upt i . enabled

eTL. C)

t.atat • -FALSE;

.1 ••
Fiflo_T_In(c),

bre.k,
c . . . EXT_STAT_INTJI:
Du1:bICHJI_CTL. 0.101,
bl' •• II.
c ••• EXT_STAT_INTJI:
DutbICHJI_CTL. 0.101,
break;

)

EOl_80130_8274,
EOIJ1274,
I.,.;!C)
{

.end_fleg • TRUE.
aut .. (OxEA,

125);

DutbeGIEA, 0.00),
Dutb 101EO. 0162),

'*

Tim.,. 1 inte1'rupta eve ... " .12' •• c . ,
1* EOI 80130 *1

231421-57

1-63

AP-235

/PCO/UBR /CHUCIVCSRC /UAP. C

LoadJ."p!)
(

'aT'C, J)

0(

R•• d-"ddT'CtI\n\nEnt.,. this Btatlon'. LaAP in He. --:> ", ..... p,
i f C!AddJl.apJlddnIOC."p. R.cvJlata_lIl (

1),

WT'tteC"'n\nE","oT': LSAP Add ...... mu.t: be on. o' thl 'ollotdnl: 'n"',
Writ.C"'"
20H, 4OH. 6OH. BOH, AQH. COM, EOH \n")'

>
Load-"ultic . . tC I
(

'a,.

«

I

I

)

(

R•• d~ddl"( "'nEnte ... the Multic •• t Add,. ••• in HI. __)11,
,,"ul UJlddr[OJ. ADDJ.ENI.
If CCMultlJlddr[Ol • 01011 •• 01

.10. (

W,.tt.C"\nSo"'''~1

thl LSI of the "ultic •• t Add" • • • •u.t 'e l\n"),
If C!Add-"ultlca.t_Addr.IOI ..Mult1J1ddr[OJII (
W1"iteC"\n\nSo,.",. Multica.t Add,. ••• Table i • • ull "nil),
b..... lu
)

,I •• -C,
W,.ttitC"'n\nWauld .. ou Itll. to edd anath.,. Multic •• t Add,. ••• ?"),
Write' If CV aT' N) -::> "h
if I !V•• CII
b,. •• k,

RIIIIDVI-"ultica.tC)
(

.ar (

i

I

)

0(

R•• d-"dd"C "\nEnt.,. thl

"ultic,.'

Add,. ••• the' \IOU .. ant to delete in H•• --)." ,
,,"ult1_Addr[OJ. ADDJ.ENI'
If CCMuUIJlddr[Ol .. 0.011 •• 01
,
W"iteC -'nBa,.,.", the LBB af the "ultic •• t Add,. •• 1 mUlt b. 1 \n")J
.1 . . ( If ('!Deleh-"ult1c . . tJlddnIlC,,"ultIJlddr[Olll (
. WTiteC"\n\nBa,.,. .. , tihet "ultic •• t Add" ••• da •• n't e.ilt!\n").1
b,. •• ki
)

et .. (

Wrtt.C"\n\nWauld Vou l:U:. ta del.te .nother "ultic.lt Add" ••• ?"),
WTtteC" (Y D" Nt --> ")J
if C!V. . III
b,..ekf

231421-58

1-64

inter,

AP-235

IPCD/USR/CHUCK/CSRC/UAP. C

Pl'int--'dd" ••••• C)
{

.truc:1:
lnt

MAT .p ... ii1

.t.ti

Write''''" This Stations Hast Addr ••• 1s:

")1

Write_AddrCIc..,hoa",i[Ol. ADD_LEN);
W,.tte("\n The "Add" ••• a' the D•• tination Node is;
Write.,AddrC.D. . t_Addr[Ol. ADD_~EN)I

Writee"\" Thil Station. LSAP Address is: ");
W"ite_Add,.' •••• p. I),
WriteC 'I ," The Add"I". D' the D•• tination LSAP is:
W"ite..Addr'lcd •• p, 1);

.t.t • FALSEJ
'or Cpmat

/ill

,

...

at[O]s

pilat

<-

&!matCI'IULTI_ADDR_CNT -

"),

");
1 JJ

Pnlilt++)

if (p •• t:-:>.1:.t •• JNUSE) (

.t.t • TRUE.
b,. •• lu
)

If Cshtl

{

Wl'ite''''n The .alloliling Multica.t Addresses .re enabled:
'01'" (p ... t a bateOl; plII.t <- &cmatCI'IULTJ_ADDR_CNT if (p ••1:->.t.1: •• INUSEJ (
Write.,Addr C.pmet->edd,.[Ol.. ADDJ.ENI.

lJ;

OIl;

pmat++)

Writee"

"),

el ••

WriteC"'" There .,.. no Multic •• t Add"esses enabl.d. \n H

);

In1 t_DataLinlf ( )
{

int
if

stat;

= Init_Llc(») •• PASSED)
W,.lteC"\n\nP •• sed Di_gnostic Self T •• t_\n\n\n H

«~tilt

);

.1 ••
jfCst.t =m

FAI~EDJlIAQNDSEI

W,.tt.(H\n'nF.il.d: Self Test Diilgnos. Commilnd'n'"),

else

i f Cstat a. FAI~EDJ.PBK_INTERNALl
W,.it.("\n\nFail.d: Int.,."ill Loapbilck S.lf T •• t\n"),

.ls.
ilC.tat

~a

FAI~ED_~PBKJ:XTERNA~)

W,.,t.("'n\nF.il.d: Ext'1'n.l Loopb.ck S.lf Test\n");
.1se
ifCstat

=-

FAI~ED_~PBK_TR"'NSCEIVERI

W,.tte("\n\nFili,lld: Ext.,.n.1 Loopback Th,.ough T,.anacltvl,. Self TIst\n'").

outb (OxEO. 01.31) I
outbCOxE2, 01.20).

l*initaUII 80130 pic 1* lCW2 *1

ICWl *1

231421-59

1-65

inter

AP-235

IPCO/USR/CHUCK/CSRC/UAP. C
Dutil (0IE2. 0110) I
Dutil (01£2. 0.00) I

1*
1*
1*
1*

outb IO.E2. 0.101,
outb COIE2. O.FFII

ICW3
ICW.
ICW"
m•• 1I:

*1
*1
*1
all inte"l"upts *1

out1llCOxFF20. 010020),

outbCO.EE. 0.341,
outb CO.ES. OIBSII
QutbCOxEB. 0.08), 1* BYBTJCK. •• t 'or 1 ... ee *1
outb CO.EE. 01701'
outb(O.E/.. 1251,
outb(OIEA, O.OOh /. Tillie,. 1 int.",.upt. eve"" . 12' sec *1

1* Inl ttali I.
outb (CHJI_CTL.
outbCCH-,,_CTL.
outb(CHJI_CTL.
outb(CHJI_CTL.
outbCCHJI_CTL.

the B274 *1
0.1011 outbCCHJI_CTL. 0.2Sh outbCCHJI_CTL. 0.301,
0.381,
211 outbCCHJI_CTL . . .~bC21 .0.141,
II, outbCCHJI_CTL •.• ~bCll ·0.151,
51! outbeCHJI_CTL. . .~bC51 • O.EAI,

W,. it.e Ii\n'n\"\"'n\n\"\n\n\n'n\"");
W,. i t. c..
• ..
W1"it.C"
.. 825B6 IEEE 802. 2/B02. 3 Compatibl. Date L.ink DT"iv." *'n");
W,. i t. ( II
• • • • • • • • • • _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .________ \ nil) ;
WT"i t. (It\n\n\n\n\"\n\n") I

******.................*.......................**•• \"'" );

In! tJlat"LinkC I,
dhe • • FALSE.J

manito,. _'la. - TRUE;
R•• d..AddrC"\n\nEnte1" the Add,. ••• 0' the D•• tination Nade in He.

--> ",

IoDnt_Add,.C01. ADD....LENI,
Load_L •• p ( ) I

,R •• d_Add1"'("\"\nEnt.,. the D•• tination Nad. 's LSAP in He.

--> ".

Wl'it.C"\n\nDa "au ....nt to Load an.., Multica.t Add,. ••••• ?

(Y 01" N» __ >"),

IId •• pI

1);

i f (V . . el)

Laad_"ulth: •• t (
PT'lnt~ddres.es(

int

, Itruet
ch.,.

),

);

f"allle_ent, buf _entl
TBD

*ptbd. *q. *b.ginJtbd,
.pbu •• Ci
'

W1"it.C"\" Would 'OU 1ill. the local echo an? CY

Q1'

N)-->")J

ifCVes() »

231421-60

1-66

AP·235

IPCO/USR/CHUCII/CSRC/UAP. C

local_echo" TRUEJ
.1 ••
local_echo:;. FALSE.

Writ.("\" This program w1ll

nOlAf ant.,. the terminal mode. \n\n");
WT'ite("\n Pres. "'C th.n CR to r.turn back to the menu\n\n");

1* Initialize Fifo vilT'iabl •• */

aut_fifD_t

=:I

in_fifo_t .. aut_fifo_\", • in_fifo_"

t_buf _stoillt =- EMPTY,

.a

01

,. _bu' _stat .. EMPTY,

EOI_BOI30_B2741

Enable_Ua,.t_JntC ),
Enab la_Tim.,. _tnt () J
manito," _flag III FALSE.

tm5tat = TRUE;
lIIhile (tmstat)
far ('Tame_cnt -

01

framll_cnt

<

MAXjRAME_SIZEI

.,h:ll. «ptbd .. Oat_TbdC)) •• pNULL);
pbuf -

(ch .... *) ptbd-:>buffJltT'1

bu' _cnt =- 0;
if! ('''tlme_cnt . - 0) (

'*

q,

-= ptbd) {

1* get iii limit buff.,. from the
data link *1

1* point to the buffer *1

if this is the fir.t bu'fer, add on IEEE 802.2
headel" info1'mation *1

begtn,JItbd D ptbd;
*pbuf++ III d •• pl
*pbuf+'" - •• apl
*pbu'++ • UJI
bu' _cnt • 3,

Il->link =- OfFsetCptbd)1 1* if this isn't the first bufFer
link the previous buFfer \ltith the new one *1
1* fill up • datil IJ.nk .mit buffer f,.om IIs~nc transmit fife *1
for C ; buf _tnt < TBUF _SIZE leI.. frame_tnt < MAX_FRAME_SI2'EJ
bu' _cnt ...., pbuf++, ,rame_cnt++> {
if (fT'.me_cnt !. 0 &-Ie send_flag)

else

br •• kJ

4IIhile Ct_bu._stilt == EMPTV);
1* wait until fifo has data *1
if C(c • *pbuf • Fifo_T_DutO) .... CR) {
+"'bu' _cnt i ++pbufi ++f,..me_cnt.
br ••• '

==

if Cc
CR : I bu._cnt < TBUF_5~ZE II send_flag)
ptbd-)act_cnt • bu' _cnt t EOFBIT;
send_flag ::II FALSE;
br.ak.
while(!SendJ'T"ameCbeginJltbd, &-D.st_Addr[O]».

< 1*

1* keep

last buffer in list *1

tT'~ing until
successful *1

231421-61

1·67

AP-235

IPCD/UBR/CHUCK/CBRC/UAP. C

Di •• ble_UaT"'_lntC h
Di.able_Tilll." _In\:()1
monito,. _flag =: TRUEs

.truet

*8uildJ"' ..... (cnt)
cnt.

TDD

u ..shart
u __ hart

"'ruet
char

.pOl'

(

bu' _ent. '"ame_ent. if
TBD

.ptbd,

*Il'

*bellinJtbdl

.pbu';

J

J

Cl. ptlld)

whil. «ptlld - Oet_TlldC»

... pN'-A..L); 1* get .. amit buff.,. ""om the
data link

,bu' = (cha,. .) ptbd->buffJt~J

bu'_ent

a

01

·ifl (fir ••• ent _. 0) (

'*

*'

1* paint to the buffe,. *1

if this i . the 'j,.8t buff.,.,
h •• de ... infDrmation */

add

on

IEEE 802.2

beginJtb" • ,tbdl
.,bu'++ •

dsap •

• pbu'++ • • s.p'
.,bu'++ • UJI

bu' _ent • 3.
}

q->11n. - Of'.eteptbd),; 1* if! this i,n't the fiT,.t buff."

else

link the p".viGu, buf,.,. with the new one
'*for fill
d.t. link
buff.r lIith ASCII ,ha,,_ct.,.. *1
(; bu'_tnt < TBUF_SJZE Srlc cnt > 0;

*1

XIIlit

up •

i++, buf _cnt++, pbuf++, cnt--,

fT'.me_cnt++)

.pbuf • il
H

(1

> Ox7EI

i

Ox1F.

=

)

if (cnt =... 0) { 1* lest buffer in list *1
ptbd->.ct_cnt - buf _cnt I EOFBIT;

breaks

Monitor _"ode'»
{

u_short
IImi t. cnt, i;
struct TBD
*BuildJrameC), *ptbd',
Writ.(" Do

"OU .... nt

thi. station to transmit? (V or N) -_>

I»;

1f eVes()>>

231421-62

1-68

Ap·235

IPCD/USR/CHUCK/CSRC/UAP. C

'or (amit • FALSEJ .... i t •• FALSE; ) (
Writee"\" Ent.,. thl nu.bl,. of deta bVt •• in the ,,.aml -> "),
t n t . Read_lntC)i
I f Cent> 204111
Writ. ("\" Sa,"'rv, the numb,,. has to b. I ••• than 2046!\"")'
11.1
.mit • TRUE,

Wt'tteC"\" Hit .nV .... to IX i t "onttar ,",odl. \n\n")1

• FrI
0' •••

Writ,C"
W,.itIC"

• of! Qood
F,. ••••
Writ,C'1 T,..n ... itt,d

CRC
Er1"O,..

Goad

Alillnment

E,.",or.

Rlclived

No

Rlceive'n"),

R•• ou,.'1
E",,,,o,,.

Ova,.,.un\n") J

E,.,.ors\"");

1* "01234'67B901234'67B901234'67B901234'67B901234'67B901234567B901234'67B9012345679
.1111'11.1

XI •••• I •••
•••• 11 ••

2'

i (791
linot I J • 0.20,
linot79J • CR.
lineCSO] • '\0',

for U

1111

.11111 ••

11
• OJ

33

••••

44

.XXI

57

.1 I •

71 *1

t++)

=-

",hllo CllnbCCH,JI_CTLI " II
foT' Ci • O. i (72J t++)
line[l] =all O.:zO,

01 (

WritlJ,.onl_lntC good_Illlli '_tnt,
W"i tl_Lanl_lnt '-r:.cv_• .,. ...._cn't.
W1"it._Sho1"t_IntClcb. C1'C_'1"1"I.
W,.it._Sho1't_IntClcb .• In_.,,,,,,
W1" i t._Sho"t_Int (Icb. "IC_,,."I,
W"it._Short_IntClcb.ovT'_'1"1"',
W~lto C.lInotOJ I,
If C... ltI (

11) I

2S),
33h
44),
~7) I

11)1

ptbd - BulldJnmo(entl,
"'h 11. ( !S.nd,.Fr.m.C ptbd, IrD •• t_Add,,[Ol»J
• CI

Itruct

n.

TBD

*ptbdi

hl_Itat == TRUEi
EDl_BOI30_B274'
Enabl._U ... t_lntC

)J

231421-63

1-69

intJ

AP-235

IPCO/USR/CHUCK/CBRC/UAP. C

whll. Ih,_"t .. "

<

while _(ptbd - Oet_TlldC»

•• , pNULL),

'*

'*

get . . . . tt buffa" frail

tho dd. link *1
ptbd->act_cnt 1- EOF81TJ
.et the End D' Frame bit *1
whileC!Send_F,..meCptbd, IcD•• tJdd,..I:OJ»; 1* Send F.......,

}

eh.,.
ehtl1::1, b8'., d.idth, ... idth,
unlt"ned
long
temp'

11

-

i

OJ

1--)

'"am.'"

W,.itll(" R.e.iv .... overrun
for Cl • I, i <= 12 - I,,;,..~t ••

II~.

'&"'+'

CaCSP),
temt. = ~;::... ".,,. ....
.&nt_TD~5C i i Cti,.p. b •• e. ' " Itch [0]. ",tdth);
for ( i • width - Ii i >- 01 i--)
Ca(chCil),
Writee","," 82586 R••• t: 1'\.
for «i • 1; i <... ~.,
Wl.d.:h. i++)

1".,

CcfSP':
t Itm~

1' • • • '_cnt,

z.

Int_To_Asc:Li Ct.mp. b.... ' , I leeh [0]. width) I
fol' (:I. =- width - 11 i )= 0; i--l
Co(chtiJ)1

WriteC"

Transmit. IInd"l'f'un ..... m•• :

fn ... t j Ilol 1;
ColSP),

.i. ...=- 11 -

<idth.

t.mp - underru"_cnt,
Int_To_Asciiet •• p. b•• e •. '

'a,.

( i ,. width Colc:h[i])'

1;

i

Writ.' "\"\" loo," C.Rt:I:
f.n

~i ... 11
CO(SP)I

i

<=-

>=-

&leh[O],

i.

")1

i :> ..

I

"

no

Ca(cht1J)1

t++)
Sec.h[Ol.

"--1

W.. ite'" SOE .1'1'01'.: "),
t"or (i = 11 i <- 2' - width;
Ca(SP),

temp = _,a_arr _cnti
Int_TD_Asc i i (temp, bllse,
for ( i = "idth - 1; i

,=

CDCc:hl:l]li
~rJ,teC

for

i

<=

21 -

lIIidth);

i++)
~ch[O],

• '.

width) i

i--)

\11

"\n\n Haximum retru:

(i. • 11
CoCSP),

... ldt"~;

;--'

26 - width,

tl"'P .. no_c,.,_cnt.
Int_To_Alcii.U.,.p. b •• a;
'01' (1 .... idth -

"

OJ

">;

i++)

II),

lIIidthi

i++)

tamp D max_col_cnt'
Jnt'_To-AsclHtempI base. ' " 'chtO], lIIidth);
for Ci 1:1 lIIidth - I, i >- 0, i--)
CDC ch [i l) I

WriteC" Fram •• th.t deferred:
far Ci • 1, i (- l ' - d1llidthi

I'),
1++)

Co(SP),

[nt_To_AsciHd.fe'T'_cnt.
for (i := dwidth - I. i
CaCch[ll),

bilse.

>-

OJ

I

I,

lr:c:hCOl,

dwidth)i

i--)

Write ("\n\n Commands. are: \r,\n"),
Write ( .. T - Termin.l Hode

231421-65

1-71

Ap·235

IPCO/USR/CHUCK/CSRC/UAP. C
W,.it.
W'r1t.
Writ,
WT.:L t.
W,.ite
W1'lt.

X P' P (" A «" S -

'High SpI.d T,.an.llit Hade
Print All Counter,
Add. Multi, •• t Add ......
Changl thl aSAP Addt'I'.
(" N - Cheng. D,.tination Nod. Add" •••
(" R - RIl-InitlaUzI the Dat, Link

(I.

int

Y - Change T.... n •• i,t Statistics'n" h
C - CI ••,. All Caunt.,.,'n"',
.
Z
D
L
8

- Dllltl • Multica.t Add,. •• ,,\""),
- Chang_ th .. DSAP Add,. ••• \" .. "
- p,.int All Add,. ••••• \" .. "
- Chang' the numb.,. Base'n" h

1:1

Init_Uop(l,
P~int..H.lp (I,

faT' CH) (

W,.it.

e"\"\"

Ent,,. a co•• and. tuP' H foT' Help

--> ");

c • R.ad_Cha,.«) I
.witch CLDWll'_C •• ICc»
CI"

'h';
P~int..H.lp

e),

bl' •• lu

ca •• 'm':
Hanita",-"odaC)1
br •• k,
ca.e 't':
Terminal_Mode C) J
br ••• ,

ca •• ' K':
Hs_Xmit_"adl( .,
b..... II,

ca •• 'v':
Wl'it""," T,..n.mit Statistics .T'. no ...

(:~~::'c::~~\~nW::l~) \IOu

if
Ill ••

if

")i

lik. to changl i t ? CY 0,. N)

W1'ite(lIof'. \n Would 1I0U l:Lke to chan.e it ? CV 0,. N)

ev .. e» (
i' (flagl .• tat_on

••

--»

")i

--> ");,

1)

fl •••.• tat_an • O.

elle 'la ••.• tat_an • 1.
bT'.alu

ca •• 'p':
P1'int_entC ).
b1' •• kJ

ca •• 'c':
Clear _entC),
bT' •• lu
ca., 'a':

Load_l'Iultica.tC'1
bT'eaks
case '1':

Remove-"ultica.tC ),
break.
cas. 's':

231421-66

1-72

AP-235

/PCO/USR/CHUCK/CSRC/UAP. C

De lete_Osap_Adllres!t( ssap);
L08d_Lsap ( );

case

break;
'd I:
Read Addr(lI\n\nEnter the De.tination Node's LSAP

in Hex

--> ",

&dsap.

1).

break.
cas. 'n';
Read_Addl'( n\n\nEntl'r the Addr ••• of the Oe.tination Node in Hex
&COeost_Addr[Ol,

--> ",

ADD_LEN);

case '1':
Pri nt_Addr ••••• ();
bT'l!'ak,

c .... '1":
50ftware_R •• et( )i
Init_OataLink () I
Add_Osap_Address (ssap,

Recv_Oata_l);

break;
case 'b I:
Writ.("\" Th. c:uT'rl!'nt base is ");
if (dhe. =a TRUE)
W"ite'''Hex. \n Would "ou like to Change i t ? (Y or N) --> ");
else
Write("Decimal. \n Would IJDU like to change i t 7 (Y Dr N) __ >

It).

if (Yes(»
{
1f (dhe. ::a.... TRUE)
dhex = FALSE;
e1s11 dhex == TRUE.

bre ... ;
default:
Wrlt .. ("'" Unknown command'n")J
break;

231421-67

1-73

inter

AP·235

IPCO/USR/CHUCK/CSRC/ASSY. AS"

name

c: ••• V lupport

.tack
Itletap

•• gmlnt "tee k
label
word

.tack

ends

DLD_DATA

•• III"'lnt public:

e.t,."
SEQI'tT_: word
DLDJlATA

end •

• eg",.nt public

UAP_DATA
UAP_DATA
OLD_CODE

UAPSODE

elt.,."

••• ",en1; pubUc

'CODE'

ends

•• gment public
'CODE'
J.,._Ua'rt_: f.", 1 • .,.:2_: f.", M.l"_:

.lgmln1; public

public
public

11,,7_: fa"

f.,.

'CODE'

inllll_' outw_, init_intv_, In.llll_,· di •• bll_, Buil(_Ptr
Dff •• t_, begin. lnb_, Dutb_

oqu
oqu

tOP + bJ
tOP + SJ

•• s.ume

CS: Dei_CODE

••• u".

f.".
f."

1sT' _T1meout_: far, 1sT' _586_:
1 .... 6_: fa", 111'~_: '1111', 1.,,1_:

ends

UAP _CODE

1
."'1
8'1'512

'DATA'

ends

I.t.,."
e.t,."

OLD_CODE

'DATA'
data !leament addr •••

J

OS: DLDJlATA

,+
initialilation progTam fo,. the 82586 data link driv ....

•u
mav

mav
mov

DLD_DATA ; get b ••• of dg1'DUp and
SeQMT_, a.
i p••• the segmlnt value to thv c prDgram
ds, ex

81,

call Main_

~

go to th. c p'l'D91'am

hlt

inb

proc
push
.. DV

pUBh
.. DV

in
pDp
IIDV

fn
8P
DP. SP
DX
DX • • I"g 1
A~. DX
DX
SP. OP

231421-68

1-74

inter

AP-235

1-75

inter
IPCD/USR/CHUCK/CSRC/ASBY. AS"
pU5h

mov
m.v
m.v
pop
rot
Offset_ endp
•• rve_int_isT'
push
push

push
push
push
push

push
puah

mov
m.v

....

call

BP
BP. SP
AX • • ,.gl
BP. BP
BP

proc

AX. DLDJ)ATA
DS.· AX
EB. AX

Is,. _5B6_

p.p
p.p
p.p
p.p
p.p
pop
pop
pop
iret
serve_tnt_is"

EB
DB

•• rve_int_B274

proc

push

f ..

AX
BX
CX
DX
BI
DI
DS
ES

01
SI
DX
CX

ax

AX
endp

far

AX

push

ex

push
pU15h
push
push
push
push

CX
DX
SI
DI
DS
ES

IOOV
IDOV

AX. UAI' J)ATA
DB. AX
EB. AX

m.v
call

Isr_U.,.t_

pop
pop
pop
pop
pop

ES
DB
DI

81
DX

231421-70

1-76

inter

Ap·235

IPCO/USR/CHUCIVCSRC/ASSY. ASM
pap
pap
pap

CX
ax
AX

t,..t
•• rve_tnt_B274

endp

serve_tnt_timeout
push

AX

push
push

ax
CX

push

DX

prac

push
push

SI
01

puoh
push

DB
ES

may
may
mav

AX. OLOJIATA
DB. AX
ES, AX

pap
pap
pap
pap
pap
pap
pap
pap

E5
OS

01
51

OX
CX
ax
AX

irat
•• rve_tnt_timeDut

serve_int1_ta1"
push
push

push
push
push
push
push

'a,.

endp

pToe

AX
ax
CX
OX
51

01

push

05
E5

may
may
Olav

AX. OLOJIATA
OB. AX
ES. AX

call

IST'7_

pap
pap
pap
pap
pap
pap
pap
pap

E5
05

01
51

OX
CX
ax
AX

231421-71

1-77

AP-235

IPCO/U6R/CHUCK/C5RC/A6BY. ABM

iT-.t
•• rv._int7_i!l"

5.1've_1 nt6_i 51"
push
push
push
push
push
push
push
push

mov
mov

.ndp

for

prot
AX
BX
CX
DX
SI
DI
DB
EB
AX.
D5.
EB.

DLD_DATA
AX
AX

call

15r6_

pop
pop
pop
pop
pop
pop
pop
pop

ES
DS
DI
BI
DX
CX
BX
AX

lret
sel"vI_int6_i5"
•• rvI_int5_is"

Indp

proc

for

push
push
push
push
push
push
push
push

AX
BX

mov

AX. DLD_DATA
DS. AX
EG. AX

mov
mov

ex

DX
51
DI
DS
ES

call

IST'5

pop
pop
pop
pop
pop
pop
pop
pop

ES
DS
DI
81
DX

iret
servI_int5_isr

ex

BX
AX
endp

231421-72

1-78

Ap·235

IPCO/USR/CHUCK/CSRC/ASSV. ASH

s.rv __ int:il_isr

push
IODY
OlDY
mDY

AX.
DS.
ES.

pufth
pU5h

push
push
push
push

,..

Pl'DC

AX
BX
CX
DX
91
D1
DS
ES

push

UAP _DATA
AX
AX

c.11

]51'2_

pDp
pDP
PDP
pDp
pDp
pDp
PDP
pDp

ES

OS
D1
91
DX

ex

BX
AX

h,.t
... rv._int2_isl'

endp

•• r"e_intl_ 10 •

pl'DC

push

push
puah
push
push
push
push

far

AX
BX

ex

pUlh

DX
51
D1
DB
EB

mDY
mDY
mDV

AX. DLDJlATA
DS. AX
ES. AX

call

ISI'1

PDP
PDP
pDp
pDP
pDP
pDP
pDp
PDP

EB
DS
D1
91
DX

ex

BX
AX

u,.t

5erve_intl_isr

"ndp

en.bl,,_ p,.OI:

far

st1

231421-73

1-79

Ap·235

IPCO/UBR/CHUCK/CBRC/ABBV. AB'"
,..t

en.bl._ endp

proc

di •• ble_

fa,.

eli
nt
disablo_

init_intv_

endp

proc

push
push

DB
AX

,or
moy

AX.
DB.

J

fn

AX
AX

Jnte""upt t\lpe. fo1' the 186/81 CDMMpute,..

moy
moy
moy
moy
moY
moy
moy
moY
moy
moy
moY
moY
moy
,"oy
may
may

DB:IIID'rd ptr
DS: word ptr
DB: word ptr
DS:WDrd ptr
DS:wo1"'d ptr
DS: IIIDT'd ptr
DS:IIIDT'd ptr
DS:word ptr
DS:WDT'd ptr
DS:WD'I"d ptr
DS:\IIord ptr
DS:wol'd ptr
DS:ward ptr
DS: wo,.d ptr
DB: W01'd ptr
DS:word ptr

pap
pap
ret

AX
DS

init_in'tv_

BOh,
B2h.
B4h.
B6h.
BBh.
BAh.
BCh.
BEh.
90h.
92h.
94h.
96h.
9Bh.
9Ah.
9Ch.
9Eh.

off •• t •• rve_int_S:274
DO_CODE

•

offset •• "va_intl_is"

Int 0
Int 1

DO_CODE

offset s.'I"ve_int2_is,..

tnt 2

DO_CODE

offset •• rve_tnt_1s"
DO_CODE

•

off.et s.'I've_int_timeout
DO_CODE

off.et •• ,.ve_int5_is.,.
DO_CODE

Int 4

•

offset serve_into_isl'
DO_CODE
off •• t •• ,.ve_int7_i.,.
DO_CODE

lnt 3

lnt S
Int 6

•

int 7

endp

DO_CODE ends
nd

It.-gin, 6 .. : dld_d.t •. ... : st.e'k: stir top

231421-74

1-80

APPLICATION
NOTE

AP-236

November 1986

Implementing StarLAN with
the Intel 82588

ADIGOLBERT
DATA COMMUNICATIONS OPERATION

SHARAD GANDHI
FIELD APPLICATIONS-EUROPE

Order Number: 231422-003
1-81

inter

AP-236

1.0 INTRODUCTION
Personal computers have become the most prolific
workstation in the office, serving a wide range of needs
such as word processing, spreadsheets, and data bases.
The need to interconnect PCs in a local environment
has clearly emerged, for purposes such as the sharing of
file, print, and communication servers; downline loading of files and application programs; electronic mail;
etc. Proliferation of the PC makes it the workstation of,
choice for acCessing the corporate mainframe/s; this
function can be performed much more efficiently and
economically when clusters of PCs are already interconnected through Local Area Networks (LANs). According to market surveys, the installed base of PCs in
business environments reached about 10 million units
year-end '85, with only a small fraction connected via
LANs. The installed base is expected to double by
1990. There is clearly a great need for locally intercon'necting these machines; furthermore, end users expect
interconnectability across vendors. Thus, there is an urgent need for industry standards to promote cost effec, tive PC LANs.
A large number of proprietary PC LANs have become
available for the office environment over the past several years. Many of these suffer from high installed cost,
technical deficiencies, non-conformance to industry
standards, and general lack of industry backing. StarLAN, in Intel's opinion, is one of the few networks
which will emerge as a standard. It utilizes a proven
network access method, it is implemented with proven
VLSI components; it is cost effective, easily'installable
and reconfigurable; it is technically competent; and it
enjoys the backing of a large cross section of the industry which is collaborating to develop a standard (IEEE
802.3, type IBASE5).

1.1 StarLAN
StarLAN is a I Mb/s network based on the CSMA/
CD access method (Carrier Sense, Multiple Access
with Collision Detection). It works over standard,
unshielded, twisted pair telephone wiring. Typically,
the wiring connects each desk to a wiring closet in a
star topology (from which the IEEE Task Force working on the standard derived the name StarLAN in
1984). In fact, telephone and StarLAN wiring can coexist in the same twisted pair bundle connecting a desk to
the wiring closet. Abundant quantities of unused phone
wiring exist in most office environments, particularly in
the U.S. The StarLAN concept of wiring and networking concepts was originated by AT&T Information Systems.

tions needed for such networks. Besides inplementing
the standard CSMA/CD functions like framing, deferring, backing off and retrying on collisions, transmit-,
ting and receiving frames, it performs data encoding
and decoding in Manshester or NRZI format, carrier
sensing and collision detection, all up to a speed of 2
Mb/s (independent of the chosen encoding scheme).
These functions make it an optimum controller for a
StarLAN node. The 82588 has a very conventional microcomputer bus interface, easing the job of interfacing
it to any processor.

1.3 Organization of the Application
Note
This application note has two objectives. One is to describe StarLAN in practical terms to prospective implementers. The other is to illustrate designing with 82588,
particularly as related to StarLAN which is expected to
emerge as its largest application area.
Section' 2 of this Application Note describes the Star, LAN network, its basic components, collision detection, signal propagation and network parameters. Sections 3 and 4 describe the 82588 LAN controller and its
role in the StarLAN network. Section 5 goes into the
details of designing a StarLAN node for the IBM PC.
Section 6 describes the design of the HUB. Both these
designs have been implemented and operated in an actual StarLAN environment. Section 7 documents the
software used to drive the '82588. It gives the actual
procedures used to do operations like, configure, transmit and receive frames. It also shows how to use the
DMA controller and interrupt controller in the IBM
PC and goes into the details of doing I/O on the PC
using DOS calls. Appendix A shows oscilloscope traces
of the signals at various points in the network. Appendix B describes the multiple point extension (MPE) being considered by IEEE. Appendixes C and D talk
about advanced usages of the 82588; working with only
one DMA channel, and measuring network delays with
the 82588.

1.4 References
For additional information on the 82588, see the Intel
Microcommunications Handbook. StarLAN specification are currently available in draft standard form
through the IEEE 802.3 Working Group.

2.0StarLAN
StarLAN is a low cost 1 Mb/s networking solution
aimed at office automation applications. It uses a star

1.2 The 82588
The 82588 is a single-chip LAN controller designed for
CSMA/CD networks. It integrates in one chip all func1-82

AP-236

topology with the nodes connected in a point-to-point
fashion to a central HUB. HUBs can be connected in a
hierarchical fashion. Up to 5 levels are supported. The
maximum distance between a node and the adjacent
HUB or between two adjacent HUBs is 800 ft. (about
250 meters) for 24 gauge wire and 600 ft. (about 200
meters) for 26 gauge wire. Maximum node-to-node distance with one HUB is 0.5 km, hence IEEE 802.3 designation of type lBASE5. 1 stands for 1 Mb/s and
BASE for baseband. (StarLAN doesn't preclude the use
of more than 800 ft wiring provided 6.5 dB maximum
attenuation is met, and cable propagation delay is no
more than 4 bit times).

5) Off-the-shelf, Low cost RS-422, RS-485 drivers/receivers compatible with the StarLAN analog interface requirements.

2,1 5tarLAN Topology
StarLAN, as the name suggests, uses a star topology.
The nodes are at the extremities of a star and the central point is called a HUB. There can be more than one
HUB in a network. The HUBs are connected in a hierarchical fashion resembling an inverted tree, as shown
in Figure 1, where nodes are shown as PCs. The HUB
at the base (at level 3) of the tree is called the Header
Hub (HHUB) and others are called Intermediate HUBs
(IHUB). It will become apparent, later in this section,
that topologically, this entire network of nodes and
HUBs is equivalent to one where all the nodes are connected to a single HUB. Also StarLAN doesn't limit
the number of nodes or HUBS at any given level.

One of the most attractive features of StarLAN is that
it uses telephone grade twisted pair wire for the transmission medium. In fact, existing installed telephone
wiring can also be used for StarLAN. Telephone wiring
is very economical to buy and install. Although use of
telephone wiring is an obvious advantage, for small
clusters of nodes, it is possible to work around the use
of building wiring.

2.1.1 TELEPHONE NETWORK

Factors contributing to low cost are:
1) Use of telephone grade, unshielded, 24 or 26 gauge
twisted pair wire transmission media.
2) Installed base of redundant telephone wiring in most
buildings.
3) Buildings are 'designed for star topology wiring.
They have conduits leading to a central location.
4) Availability of low cost VLSI LAN controllers like
the 82588 for low cost applications and the 82586 for
high performance applications.

StarLAN is structured to run parallel to the telephone
network in a building. The telephone network has, in
fact, exactly the same star topology as StarLAN. Let us
now examine how the telephone system is typically laid
out in a building in the USA. Figure 2 shows how a
typical building is wired for telephones. 24 gauge
unshielded twisted pair wires emanate from a Wiring
Closet. The wires are in bundles of 25 or 50 pairs. The
bundle is called D inside wiring (DIW). The wires in
these cables end up at modular telephone jacks in the
wall. The telephone set is either connected directly to

HUB LEVEL 1

231422-2
'Maximum of 5 HUB levels.
'pes or DTEs can connect directly at any level.

Figure 1. StarLAN Topology

1-83

AP-236

the jack or through an extension cable. Each telephone
generally needs one twisted pair for voice and another
for auxilliary power. Thus, each modular jack has 2
twisted pairs (4 wires) connected to it. A 25 pair DIW
cable can thus be used for up to 12 telephone connections. In most buildings, not all pairs in the bundle are
used. Typically, a cable is used for only 4 to 8 telephone
connections. This practice is followed by telephone
companies because it is cheaper to install extra wires
initially, rather than retrofitting to expand the existing
number of connections. As a result, a lot of extra, unused wiring exists in a building. The stretch of cable
between the wiring closet and the telephone jack is typically less than 800 ft. (250 meters). In the wiring closet
the incoming wires from the telephones are routed to
another wiring closet, a P ABX or to the central office
through an interconnect matrix. Thus, the wiring closet
is. a concentration point in the telephone network.
There is also a redundancy of wires between the wiring
closets.

2.1.2 StarLAN AND THE TELEPHONE
NETWORK

StarLAN does not have to run on building wiring, but
the fact that it can significantly adds to its attractiveness. Figure 3 shows how StarLAN piggybacks on telephone wiring. Each node needs two twisted pair wires
to connect to the HUB. The unused wires in the 25 pair
DIW cables provide an electrical path to the wiring
closet, where the HUB is located. Note that the telephone and StarLAN are electrically isolated. They only
use the wires in the same bundle cable to connect to the
wiring closet. Within the wiring closet, StarLAN wires
connect to a HUB and telephone wires are routed to a
different path. Similar cable sharing can occur in connecting HUBs to one another. See Figure 4 for a typical
office wired for StarLAN throu~h telephone wiring.

231422-3

Figure 2. Telephone Wiring in a Building

WIRING CLOSET

800 f1

.........

" - - - BUNDLES or - - . /
.
25 - 50 PAIRS

~2 lWlSTED PAIRS

24 GAUGE. UNSHIELDED

231422-4
• StarLAN and telephones share the same bundle, but are electrically isolated.
'SlarLAN uses the unused wires in existing bundles.

Figure 3. Coexistence of Telephone and StarLAN
1-84

AP-236

WIRING CLOSET

WIRING CLOSET

ROOM

#1

ROOM

#2

ROOM

#3

WIRING CLOSET

TELEPHONE
WIRES TO PBX

WIRING CLOSET

231422-5

Figure 4. A Typical Office Using Telephone Wiring for StarLAN

1-85

inter

AP-236

2.1.3 StarLAN AND Ethernet
StarLAN and Ethernet are similar CSMAlCD networks. Since Ethernet has existed longer and is better
understood, a comparison of Ethernet with StarLAN is
worthwhile.
1. The data, rate of Ethernet is IOMb/s and that of StarLAN.is 1 Mb/s.
2. Ethernet uses a bus topology with each node connected to a coaxial cable bus \ via a 50 meter transceiver cable containing four shielded twisted pair
wires. StarLAN uses a star topology, with each node
connected to a central HUB by a point to point link
through two pairs of unshielded twisted pair wires.
3. Collision detection in Ethernet is done by the transceiver connected to the coaxial cable. Electrically, it
is done by sensing the energy level on the coax cable.
Collision detection in StarLAN is done in the HUB
by sensing activity on more than one input line connected to the HUB.

4. In Ethernet, the presence of collision is signalled by
the transceiver to the node by a special collision detect signal. In StarLAN, it is signalled by the HUB
using a special collision presence signal on the receive data line 'to the node.
5. Ethernet cable segments are interconnected using repeaters in a non-hierarchical fashion so that the distance between any, two nodes does not exceed 2.8
kilometers. In StarLAN, the maximum distance between any two nodes is 2.5 kilometers., This is
achieved by wiring a maximum of five levels of
HUBs in a hierarchical fashion ..

2.2 Basic StarLAN Components
A
1.
2.
3.

StarLAN network has three basic components:
StarLAN node interface
StarLAN HUB
Cable

ETHERNET

STAR LAN
231422-6

Figure 5. Ethernet and StarLAN Similarities

1-86

inter

AP-236

2.2.1 A StarLAN NODE INTERFACE

Figure 6 shows a typical StarLAN node interface. It
interfaces to a processor on the system side. The processor runs the networking software. The heart of the
node interface is the LAN controller which does the job
of receiving and transmitting the frames in adherence
to the IEEE 802.3 standard protocol. It maintains all
the timings-like the slot time, interframe spacing
etc.-required by the network. It performs the functions of framing, deferring, backing-off, collision detection which are necessary in a CSMA/CD network. It
also does Manchester encoding of data to be transmitted and clock separation-or decoding-of the Manchester encoded data that is received. These signals before going to the unshielded twist pair wire, may under- .
go pulse shaping (optional) pulse shaping basically
slows down the fall/rise times of the signal. The purpose of that is to diminish the effects of cross-talk and
radiation on adjacent pairs sharing the same bundle
(digital voice, Tl trunks, etc). The shaped signal is sent
on to the twisted pair wire through a pulse transformer
for DC isolation. The signals on the wire are thus differential, DC isolated from the node and almost sinusoidal (due to shaping and the capacitance of the wire).
NOTE:
Work done by the IEEE 802.3 committee has shown
that no slew rate control on the drivers is required.
Shaping by the transformer and the cable is sufficient
to avoid excessive EMI radiation and crosstalk.
The squelch circuit prevents idle line noise from affecting the' receiver circuits in the LAN controller. The
squelch circuit has a 600 mv threshold for that purpose.
Also as part of the squelch circuitry an envelope detector is implemented. Its purpose is to generate an envelope of the transitions of the RXD line. Its output serve

as a carrier sense signal. The differential signal from the
HUB is received using a zero-crossing RS-422 receiver.
Output of the receiver, qualified by the squelch 'circuit,
is fed to the RxD pin.of the LAN controller. The RxD
signal provides three kinds of information:
I) Normal received data, when receiving the frame.
2) Collision information in the form of the collision
presence signal from the HUB.
3) Carrier sense information, indicating the beginning
and the end of frame. This is useful during transmit
and receive operations.
2.2.2 StarLAN HUB

HUB is the point of concentration in StarLAN. All the
nodes transmit to the HUB and receive from the HUB.
Figure 7 shows an abstract representation of the HUB.
It has an upstream and a downstream signal processing
unit. The upstream unit has N signal inputs and 1 signal output. And the downstream unit has 1 input and
N output signals. The inputs to the upstream unit come
from the nodes or from the intermediate HUBs
(IHUBs) and its output goes to a higher level HUB.
The downstream unit is connected the other way
around; input from an upper level HUB and the outputs to nodes or lower level IHUBs. Physically each
input and output consist of one twisted pair wire carrying a differential signal. The downstream unit essentially just re-times the signal received at the input, and
sends it to all its outputs. The functions performed by
the upstream unit are:
1. Collision detection
2. Collision Presence signal generation
3. Signal Retiming
4. Jabber Function
5. Start of Idle protection timer

PULSE
TRANSFORMER
8 BIT BUS

< >
< >

TELEPHONE
JACK

PULSE
SHAPING
~----t (OPTIONAL)

82S88

CONTROL

RxD

SYS ClK

SQUELCH

+ '
ENABLE
CIRCUITS
231422-7

Figure 6. 82588 Based StarLAN Node
1-87

inter

AP·236

the HUB associated with this function and their operation .is described in section 6.

231422-8

Figure 7. A StarLAN HUB
co~li.sion detect~on in the HUB is done by sensing
activity on the Inputs. If there is activity (or transItions) on more than one input, it is assumed that more
than one node is transmitting. This is a collision. If a
collision is detected, a special signal called the Collision
Presence Signal is generated. This signal is generated
and sent out as long as activity is sensed on any of the
input lines. This signal is interpreted by every node as
an occurrence of collision. If there is activity only on
one input, that signal is re-timed--or cleaned up of any
accumulated jitter-and sent out. Figure 8 shows the
input to output relations of the HUB as a black box.

The
t?~

If a node transmits for too long the HUB exercises a
function to disable the node from interfering
with traffic from other nodes. There are two timers in

J~bber

IDLE
IDLE
IDLE

VALID
MANCHESTER

The last function implemented by the HUB is the start
of Idle prot~ction timer. During the end of reception,
the HUB Will see a long undershoot at its input port.
This undershoot is a consequence of the transformer
discharging accumulated charge during the 2 microseconds of high of the idle pattern. The HUB should implement a protection mechanism to avoid the undesirable effects of that undershoot.
Figure 9 shows a block diagram of the HUB. A switch
position determines whether the HUB is an IHUB or a
. HI:IUB (Header HUB). If the HUB is an IHUB, the
sWitch decouples the upstream and the downstream
units. HHUB is the highest level HUB; it has no place
to send its output signal, so it returns its output signal
(through the switch) to the outputs of the downstream
unit. There is one and only one HHUB in a StarLAN
network and it is always at the base of the tree. The
returned signal eventually reaches every node in the
network through the intermediate nodes (if any). StarLAN specifications do not put any restrictions on the
number of IHUBS at any level or on number of inputs
to any HUB. The number of inputs per HUB are typically 6 to 12 and is dictated by the typical size of clusters in a given networking environment.

COLLISION PRESENCE
IDLE
IDLE

VALID MANCHESTER

IDLE

VALID MANCHESTER
IDLE
VALID MANCHESTER

COLLISION PRESENCE
IDLE
IDLE

COLLISION
PRESENCE

COLLISION
PRESENCE

HUB
COLLISION
PRESENCE

VALID MANCHESTER

IDLE

231422-9

Figure 8. HUB as a Black Box

1-88

intJ

AP-236

TRANSMIT PAIR

#1

~II

~II
TRANSMIT PAIR

RECEIVE PAIR

'-3
'-3

+

TO HIGHER
LEVEL HUB

JABBER

+

#N

#

PROTECTION
TIMER

1

HHUB

IH~""B----I,--R_i_~_~A_INL_G KhJII
...

11

E

11

RECEIVE PAIR

#

N

231422-10

Figure 9. StarLAN HUB Block Diagram

Although it is outside the scope of the IEEE 802.3
IBASE5 standard, there is considerable interest in using fiber optics and coaxial cable for node to HUB or
HUB to HUB links especially in noisy and factory environments. Both these types of cables are particularly
suited for point-to-point connections. Even mixing of
different types of cables is possible (this kind of environments are not precluded).

2.2.3 StarLAN CABLE

Unshielded telephone grade twisted pair wires are used
to connect a node to a HUB or to connect two HUBs.
This is one of the cheapest types of wire and an important factor in bringing down the cost of StarLAN.
Although the 24 gauge wire is used for long stretches,
the actual connection between the node and the telephone jack in the wall is done using extension cable,
just like connecting a telephone to a jack. For very
short Star LAN configurations, where all the nodes and
the HUB are in the same room, the extension cable
with plugs at both ends may itself be sufficient for all
the wiring. (Extension cables must be of the twisted
pair kind, no flat cables are allowed).

NOTE:
StarLAN IEEE 802.3 !BASES draft calls for a maximum attenuation of 6.5 dB between the transmitter
and the corresponding receiver at all frequencies between 500 KHz to 1 MHz. Also the maximum allowed cable propagation delay is 4 microseconds.

2.3 Framing

The telephone twisted pair wire of 24 gauge has the
following characteristics:
Attenuation

: 42.55 db/mile

@

Figure 10 shows the format of a 802.3 frame. The beginning of the frame is marked by the carrier going
active and the end marked by carrier going inactive.
The preamble has a 56 bit sequence of 101010 . . . .
ending in a O. This is followed by 8 bits of start of frame
delimiter (sfd) - 10101011. These bits are transmitted
with the MSB (leftmost bit) transmitted first. Source
and destination fields are 6 bytes long. The first byte is
the least significant byte. These fields are transmitted
with LSB first. The length field is 2 bytes long and gives
the length of data in the Information field. The entire
information field is a minimum of 46 bytes and a maximum of 1500 bytes. If the data content of the Informa-

1 MHz

DC Resistance : 823.69 fl./mile
Inductance
Capacitance
Impedance

0.84 mH/mile
0.1 fLF/mile
92.6D, -4 degrees

@

1 MHz

Experiments have shown that the sharing of the telephone cable with other voice and data services does not
cause any mutual harm due to cross-talk and radiation,
provided every service meets the FCC limits.
1-89

AP-236

tion field is less than 46. padding bytes are used to
make the field 46 bytes long. The Length field indicates

The frames can be directed to a specific node (LSB of
address must be 0). to a group of nodes (multicast or
grnnp-LSB of address must be I) or all nodes (broadcast-alI address bits must be 1).

hnw mlll'h rp"l cl"t" i. in thp TnfnrmMinn fj,,1cl. Th" l"st

32 bits of the frame is the Frame Check Sequence
(FCS) and contains the CRC for the frame. The CRC is
calculated from the beginning of the destination address to the end of the Information field. The generating polynomial (Autodin II) used for CRC is: .

2.4 Signal Propagation and Collision
Figure 11 will be used to illustrate three typical situations in a StarLAN with two IHUBs and one HHUB.
Nodes A and B are connected to HUBI. nodes C and D
to HUB2 and node E to HUB3.

+ X26 + X23 + X22 + XI6 + XI2 + Xii +
xlO + XB + X7 + X5 + X4 + X2 + X + 1

X32

No need for Figure N.

CARRIER ON

+

7

1

6

6

2

t.4AX=1500
t.4IN = 46

CARRIER OFF
I
4 ..

I PREAt.4BLE I SFD I DA I SA I LEN IINFORt.4ATION I FCS
,.

SFD ~ Start of Frame Delimiter
DA ~ Destination Address .
SA ~ Source Address

LEN

~

I

FRAt.4E LENGTH ~
t.4AX=1518
t.4IN=64

Length

FCS ~ Frame Check Sequence
All numbers indicate field length in octets.

Figure 10. Framing

1-90

231422-11

inter

Ap·236

231422-12

Situation # 1. A Transmitting

231422-13

Situation # 2. A & B Transmitting

231422-14

Situation # 3. A, B & C Transmitting
HUB1, HUB2 are IHUBs
HUB3 is the HHUB
Fa, Fb, Fe-Frames from nodes A, B & C
Fx-Collision Presence Signal

Figure 11. Signal Propagation and Collisions

1-91

inter

AP-236

Backoff method ........ Truncated binary exponential
Encoding ..... .' ...................... Manchester

2.4.1 Situation # 1
WhpnpVPT nnop A tnm.mit. ~ fr~me Fa, it will reach
,HUB 1. If node B is silent, there is no collision. HUB I
will send Fa to HUB3 after re-timing the signal. If
nodes C, D and E are also silent, there is no collision at
HUB2 or HUB3. Since HUB3 is the HHUB, it sends
the frame Fa to HUBI, HUB2 and to node E after retiming. HUBI and HUB2 send the frame Fa to nodes
A, Band C, D. Thus, Fa reaches all the nodes on the
network including the originator node A. If the signal
received by node A is a valid Manchester signal and not
the Collision Presence Signal (CPS) for the entire duration of the slot time, then the node A assumes that it
was a successful transmission.

2.4.2 Situation # 2
If both nodes A and B were to transmit, HUBI will
detect it as a collision and will send signal Fx (the Collision Presence Signal) to the HUB3-Note that HUBI
does not send Fx to nodes A and B yet. HUB 3 receives
a signal from HUB I but nothing from node E or
HUB2, thus it does not detect the situation as. a collision and simply re-times the signal Fx and sends it to
node E, HUB2 and HUBI. Fx ultimately reach all the
nodes. Nodes A and B detect this signal as CPS and
call it a collision.

Clock tolerance ................ ±0.01 % (100 ppm)
Maximum jitter per segment .............. ± 62.5 ns

3.0 LAN CONTROLJ-ER FOR StarLAN
One of the attractive features of StarLAN is the availability of the 82588, a VLSI LAN controller, designed
to meet the needs of a StarLAN node. The main ·requirements of a StarLAN node controller are:
1. IEEE 802.3 compatible CSMA/CD controller.
2. Configurable to StarLAN network and system parameters.
3. Generation of all necessary clocks and timings.
4. Manchester data encoding and decoding.
5. Detection of the Collision Presence Signal.
6. Carrier Sensing.
7. Squelch or bad signal filtering.
8., Fast and easy interface to the processor.
82588 performs all these functions in silicon, providing
a minimal hardware interface between the system processor and the StarLAN physical link. It also reduces
the software needed to run the node, since a lot of functions, like deferring, back off, counting the number of
collisions etc., are done in silicon.

2.4.3 Situation # 3
In addition to nodes A and B, if node C were also to
transmit, the situation at HUBI will be the same as in
situation # 2. HUB2 will propagate Fc from C towards
HUB3. HUB3 now sees two of its inputs active and
hence generates its own Fx signal and sends it towards
each node.
These situations should also illustrate the point made
earlier in the chapter that, the StarLAN network, with
nodes connected to multiple HUBs is, logically, equivalent to all the nodes connected to a single HUB (Yet
there are some differences between stations connected
at different HUB levels, those are due to different delays to the header hub HHUB).

3.1 IEEE 802.3 Compatibility
The CSMA/CD control unit on the 82588 performs the
functions of deferring, maintaining the Interframe
Space (IFS) timing, reacting to collision by generating a
jam pattern, calculating the back-off time based on the
number of collisions and a random number, decoding
the address of the incoming frame, discarding a frame
that is too short, etc. All these are performed by the
82588 in accordance to the IEEE 802.3 standards. For
inter-operability of different nodes on the Star LAN network it is very important to have the controllers strictly
adhere to the sam\! standards.

3.2 Configurability of the 82588
2.5 StarLAN System and Network
Parameters
Preamble length (incl. sfd) .................. 64 bits
Address length .................. : ......... 6 bytes
FCS length CRC (Autodin II) ............... 32 bits
Maximum frame length ................. 1518 bytes
Minimum frame length .................... 64 bytes
Slot time ................ " .......... 512 bit times
Interframe spacing ............. ',' ...... 96 bit times
Minimum jam timing .................. 32 bit times
Maximum number of collisions .................. 16
Backoff limit ................................. 10

Almost all the networking parameters are programmable over a wide range. This means that the StarLAN
parameters form a subset of the total potential of the
82588. This is a major advantage for networks whose
'standards are being defined and are in a flux. It is also
an advantage when carrying over the experience gained
with the component in one network to other applications, with differing parameters (leveraging the design).
The 82588 is initialized or' configured to its working
environment by the CONFIGURE command. After
the execution of this command, the 82588 knows its
system and net~ork parameters. A configure block in
1-92

Ap·236

memory is loaded into the 82588 by DMA. This block
contains all the parameters to be programmed as shown
in Figure 12. Following is a partial list of the parameters with the programmable range and the Star LAN
value:
StarLAN
Parameter
Range
Value
Preamble length 2,4, 8, 16 bytes
8
Address length o to 6 bytes
6
CRCtype
16,32 bit
32
Minimum frame
length
6 to 255 bytes
64
Interframe
12 to 255 bit times
spacing
96
Slot time
1 to 2047 bit times
512
Number of
retries
oto 15
15

StarLAN
Value

Parameter

Range

Data encoding

NRZI, Man.,
Diff. Man.
Code viol.,
Bitcomp.

Collision
detection

Manch.
Code Viol.

Beside these, there an: many other options available,
which mayor may not apply to StarLAN:
Data sampling rate of 8 or 16
Operating in Promiscuous mode
Reception of Broadcast frames
Internal loopback operation
External loopback operation
Transmit without CRC
HDLC Framing

BIT
BYTE

7

o

2

6
I

I

I
I

_1
I

I BYTE

SERIAL
MODE

CHNG

4

5

_ I BYTE
SMPLG
RATE

3

COU~T (L.S.B)
i

J

I
I

OSC
RANGE

4
5

BOF
METD

EXP

PREAM LEN
I
I
PRIO

I

I

I~TER

6
I
I

I
I

I
I

I

7

9

PAD

10

COT
SRC

BIT
STUFF

11

I

MINIMUM

I

I

I

I

I

I

I

I

I
ADD lEN

I

I

I

I
LIN PRIO

I

SPACING
I
I

I

I
I

I
I

I
I

MAN
/NRZ·

CRS
SRC
FRAME

I

(~)

BC
DIS

PRM

CRSF

lENGTH

I

I

SllOT TIME

TON
NCRS

CDTF

I

I
I

I

NCRC
INS

I

I

I

CDBBC

I

I

I

OIF.MAN
/MAN

I FRAME
I
I
I I
SLOT TIME (l)

CRC16

I

lENGT~
NO SRC
ADD INS

RETRY NUMBER

8

i

FIFO ILiMIT

I
I

I

I

i

COU~T (M.S.B) I

I

INT
LP.BCK

I

I

i

BUFFER
I
EXT
LP.BCK

o

2

3

I

I
I

I
I

I

I

CONFIG PARAMETER FORMAT
231422-15

Figure 12. Configuration Block

1-93

AP-236

time, Back off time, Number of collisions, Minimum
frame length, etc. These timers are started and stopped

3.3 Clocks and Timers

e~!0:ne.ti~?-!!y 1)y th~ R'~RR.

H::4UiH;:~ LWU ",l\.n...~~, uji~ fur thi: upcrutiGu. of
the system interface and another for the serial side.
, Both clocks are totally asynchronous to each other.
This permits transmitting and receiving frames at data
rates that are virtually independent of the speed at
which the system interface operates.

The 02.300

3.4 Manchester Data Encoding and
Decoding
In StarLAN the data transmitted by the node must be
encoded in Manchester format. The node should also
be able to decode Manchester encoded data when receiving a frame--a process also known as clock recovery. The 82588 does the encoding and decoding of data
bits on chip for data rates up to 2 Mb/s.

The serial clock can be generated on chip using just an
external crystal of a value 8 or 16 times the desired bit
rate. An external clock may also be used.
The 82588 has a set of timers to maintain various timings necessary to run the CSMA/CD control unit.
These are timings for the Slot time, Interframe spacing

DATA

I

1

I0 I

1

Besides Manchester, the 82588 can also do encoding
and decoding in NRZI and Differential Manchester
formats. Figure 13 shows samples of encoding in

I

1

I0 I

1

I

0

I0 I0 I

1

I

NRZ
NRZI
MANCHESTER
DIFFERENTIAL
MANCHESTER

Encoding
Method

231422-16

Mid Bit Cell
Transitions

Bit Cell Boundary
Transitions

NRZ

Do not exist.

Identical to original data.

NRZI

Do not exist.

Exist only if original data
bit equals o.
Dependent on present
encoded signal level:
to 0 if 1
to 1 if 0

Manchester

Exist for every bit of
the original data:
from 0 to 1 for 1
from 1 to 0 for 0

Exist for consequent equal
bits of original data:
from 1 to 0 for 1 1
from 0 to 1 for 0 0

Differential
Manchester

Exist for every bit of
the original data.
Dependent on present
Encoded signal level:
to 0 if 1
t01 if 0

Exist only if original data
bit equals o.
Dependent on present
Encoded signal level:
to 0 if 1
to 1 if 0

Figure 13. 82588 Data Encoding Rules

inter

AP-236

these three formats. The main advantage of NRZI over
the other two is that NRZI requires half the channel
bimdwidth. for any given data rate. On the other hand.
since the NRZI signal does not have as many transitions as the other two. clock recovery from it is more
difficult. The main advantage of Differential Manchester over straight Manchester is that for a signal that is
differentially driven (as in RS 422). crossing of the two
wires carrying the data does not change the data received at the receiver. In other words. NRZI and Differential Manchester encoding methods are polarity insensitive (Even though NRZI. Differential Manchester
are polarity insensitive. the 82588 expects a high level
in the RXD line to detect carrier inactive at the end of
frames).

periodic intervals. When the 82588 decodes this signal.
it fails to see mid-cell transitions repeatedly at intervals
of 2.5 bit times and hence calls it a code violation. The
edges of CPS are marked for illustration as a. b. c.
d •... 1. Let us see how the 82588 interprets the signal if
it starts calling the edge 'a' as the mid-cell transition for
'I'. Then edge at 'b' is '0'. Now the 82588 expects to see
an edge at ••• but since there is none. it is a Manchester
code violation. The edge that eventually does occur at
'd' is then used to re-synchronize and. since it is a falling edge. it is taken as a mid-cell transition for '0'. The
edge at 'e' is for a 'I' and then again there is no edge at
•••. This goes on. with the 82588 flagging code violation
and re-synchronizing again every 2.5 bit times. When a
transmitting node sees this CPS signal being returned
by the HUB (instead of a valid Manchester signal it
transmitted). it assumes that a collision occurred. The
82588 has two built-in mechanisms to detect collisions.
These mechanisms are very general and can be used for
a very broad class of applications to detect collisions in
a CSMA/CD network. Using these mechanisms. the
82588 can detect collisions (two or more nodes transmitting simultaneously) by just receiving the collided
signal during transmission. even if there was no HUB
generating the CPS signal.

3.5 Detection of the Collision
Presence Signal
In a StarLAN network. HUB informs the nodes that a
collision has occurred by sending the Collision Presence Signal (CPS) to the nodes. The CPS signal is a
special signal which contains violations in Manchester
encoding. Figure 14 shows the CPS signal. It has a 5 ms
period. looking very much like a valid Manchester signal except for missing transitions (or violations) at

10 1

ENCODING

1 01

K

1

J

10 1

CPS

abc

EDGES:

d

e f

9

k I

h

! - 5 . us PERIOD-I

I 2t I t i t = 0.5 .us
• MISSING MID-CELL TRANSITION

82588
DECODING

1

0

.rt.r1.
abc

d

o

1

1..JL..1'
d

e f

9

1

0

.rt.r1.
J

kim
O·

1

1..JL..1'
J

kim

Figure 14.82588 Decoding the Collision Presence Signal

1-95

231422-17

Ap·236

Collision also if:
RxD stays low for 25 samples or more
A mid cell transition is missing

3.5.1 COLLISION DETECTION BY CODE
VIOLATION

If during transmission, the 82588 sees a violation in the
"encoding (Manchester, NRZI or Differential Manchester) used, then it calls it a collision by aborting the
transmission and transmitting a 32 bit jam pattern. The
algorithm used to detect collisions, and to do the data
decoding, is based on finding the number of sampling
clocks between an edge to the next one. Suppose an
edge occurred at time 0, the sampling instant of the
next edge determines whether it was a collision (C), a
long pulse (L)-with a nominal width of 1 bit time-, or
a short pulse (S)-nominal width of half a bit time. The
following two charts show the decoding and collision
detection algorithm for sampling rates of 8 and 16
when using Manchester encoding. The numbers at the
bottom of the line indicate sampling instances after the
occurrence of the last edge (at 0). The alphabets on the
top show what would be inferred by the 82588 if the
next edge were to be there.

Sampling rate = 8 (clock is 8x bit rate)

C C S S S L L L L L C C

I I I I I I I I I I I I

o

23456"78910111213

Collision also if:
RxD stays low for 13 samples or more
A mid cell transition is missing
Sampling rate = 16 (clock is 16x bit rate)

CCCCCSSSSSCLLLLLLLLLCCCC
111111111111111111111111111

o

2

4

6

8

A single instance of code violation can qualify as collision. The 82588 has a parameter called collision detect
filter (CDT Filter) that can be configured from 0 to 7.
This parameter determines for how many bit times the
violation must remain active to be flagged as a collision:
For StarLAN CDT Filter must be configured to 0that is disabled.
3.5.2 COLLISION DETECTION BY SIGNATURE
(OR BIT) COMPARISON
"

This method of collision detection compares a signature
ofthe transmitted data with that of the data received on
the RxD pin while transmitting. Figure 15 shows a
block diagram of the logic. As the frame is transmitted
it flows through the CRC generation logic. A timer,
called the Tx slot timer, is started at the same time that
the CRC generation starts. When the count in the timer
reaches the slot time value, the current value of the
CRC generator is latched in as the" transmit signature.
As the frame is returned back (through the HUB) it
flows through the CRC checker. Another timer-Rx
slot timer-is started at the same time as the CRC
checker starts checking. When this timer reaches the
slot time value, the current value of the CRC checker is
latched in as the receive signature. If the recdved signature matches the transmitted one, then it is assumed
that there was no collision. Whereas, if the signatures
do not match, a collision is assumed to have occurred.

10 12 14 16 18 20 22 24 26

TRANSMITTED
FRAME

TX CRC

TRANSMIT CHANNEL

!.
Tx SLOT
TIMER

TX SIGNATURE
LATCH

+
Rx SLOT
TIMER

COMPARE·

RX SIGNATURE
LATCH

f
RECEIVED
FRAME

RX CRC

RE CEIVE CHANNEL

=

• MATCH NO COLLISION
NO MATCH COLLISION

=

Figure 15. Collision Detection by Signature Comparison
1-96

231422-18

AP-236

b) Half a slot time + 16 bit times elapse and the opening flag (sfd) is not detected.
c) Carrier sense goes inactive after an opening flag is
received with transmitter still active.

Note that, even if the collision were to occur in the first
few bits of the frame, a slot time must elapse before it is
detected. In. the code violation method, collision is detected within a few bit times. However, since the signature method compares the signatures, which are characteristic of the frame being transmitted, it is more robust. The code violation method can be fooled by returning a signal to the 82588 which is not the same as
the transmitted signal but is a valid Manchester signal-like a I MHz signal. Both methods can be used
simultaneously giving a combination of speed and robustness.

These mechanisms add a further robustness to the collision detection mechanism of the 82588. It is also possible to OR an externally generated collision detect signal
to the internally generated condition by bit comparison
(see Figure 17).

3.6 Carrier Sensing

NOTE:
In order to reliably detect a collision using the collision by bit comparison mode, the transmitter must
still be transmitting up to the point where the receiver
has seen enough bits to complete its signature. Otherwise, the transmitter may be done before the RX signature is completed resulting in an undetected collision. A sufficient condition to avoid this situation is to
transmit frames with a minimum length of 1.5 • slottime (see Figure 16).

A StarLAN network is considered to be busy if there
are transitions on the cable. Carrier is supposed to be
active if there are transitions. Every node controller
needs to know when the carrier is active and when not.
This is done by the carrier sensing circuitry. On the
82588 this circuit is on chip. It looks at the RxD (receive data) pin and if there are transitions, it turns on
an internal carrier sense signal. It turns off the carrier
sense signal ifRxD remains in idle (high) state for 13/8
bit times. This carrier sense information is used to mark
the start of the interframe space time and the back off
time. The 82588 also defers transmission when the carrier sense is active.

3.5.3 ADDITIONAL COLLISION DETECTION
MECHANISM

In addition to the collision detection mechanisms described in the preceding sections, the 82588 also flags
collision when after starting a transmission any of the
following conditions become valid:
a) Half a slot time elapses and the carrier sense of
82588 is not active.

When operating in the NRZI encoded mode, carrier
sense is turned off if RxD pin is in the idle state for 8 bit
times or more (see Figure 18).

82588

PD

TX

HEADEND
PD

RX

CONDITION FOR RELIABLE CDBBC
TLMIN_FRAMCLENGTH

> SLOLTIME+ 2*PD

t SLOLTIME ~ 2*PD

231422-75

Figure 16. Limitation of CDeeC Mechanism

1-97

inter

Ap·236

COLLISION DETECTION BY BIT COMPARISON (CDBBC)
(CONrIGURE BYTE B, BIT 3)
COLLISION DETECTION SOURCE (INTERNAL, EXTERNAL)
(CONrIGURE BYTE 10, BIT 7)

231422-76

Figure 17. Mode 0, Collision Detection

3.7 Squelching the Input
Squelch circuit is used to filter idle noise on the receiver
input. Basically two types of squelch may be used: Voltage and time. Voltage squelch is done to filter out signals whose strength is below a defined voltage threshold (0.6 volts for StarLAN). It prevents idle line noise
from disturbing the receive circuits on the controller.
The voltage squelch circuit is placed right after the receiving pulse transformer. It enables the input to the
RxD pin of the 82588 only when the signal strength is
above the threshold.

If the signal received has the proper level but not the
proper timing, it should not bother the receiver. This is'
accomplished by the time squelch circuit on the 82588.
Time squelching is essential to weed out spikes, glitches
and bad signal especially at the beginning of a frame.
The 82588 does not tum on its carrier sense (or receive
enable) signal until it receives three consecutive edges,
each separated by time periods greater than the fast
time clock high time but less than 13/8 bit-times as
shown in Figure 18.

MANCHESTER
DATALFu-

CARRIER

b

--------~

I

I

I.

--+-E-D~-E-S-j.J

.'---1

13/BBTxB
25/16BTx 16

-----u--

DATALFu-

CARRIER

b

HI~H. :r .1

I

I

--+-E-D~-E-S-j...l

1

OR 1.1- - -

231422-77

Figure 18. Carrier Sensing

1-98

intJ

AP-236

shows that it has an 8 bit data bus, read, write, chip
select, interrupt and reset pins going to the processor
bus. It also needs an external DMA controller for data
transfer. A system clock of up to 8 MHz is needed. The
read and write access times of the 82588 are very
short-95 ns-as shown by Figure 20. This further facilitates interfacing the controller to almost any processor.

The carrier sense activation can be programmed for a
further delay by up to 7 bit times by a configuration
parameter called carrier sense filter.

3.8 System Bus Interface
The 82588 has a conventional bus interface making it
very easy to interface to any processor bus. Figure 19

SE~IAl

CLOCK
X2/RxC

Xl/TxC

RTS

RESET - - +

00-7
STANDARD
BUS
INTERFACE

R5

JI--I\

+ - - CTS
Tx 0

\r-v"

WR

SERIAL
INTERFACE

82588

cs

28 PIN
PLASTIC/CERAMIC

INT

+--RxD
TClK

DRQO
DMA [ DACKO--+
INTERFACE DRQl
DACKI

(MODE 0)

CRS} CSMA/CD
INTERFACE
COT

t

ClK

SYSTEM CLOCK

231422-20

Figure 19. Chip Interface

-

80n.
(MIN)

.

95n •

I

(MIN)

55n.(MAX)

DATA

-75ns(MIN)

\

.

95n •
(MIN)

-on'

ll

(MIN)
DATA

231422-21

Figure 20. Access Times

1-99

inter

AP-236

The 82588 has over 50 bytes of registers, and most are
accessed only indirectly. Figure 21 shows the register
access mechanism of the 82588. It has one I/O port and
.2 uIviA cilannei pons. Tilese are tile windows into the
82588 for the CPU and the DMA controller. An external CPU can write into the Command register and read
from the Status registers using I/O instructions and
asserting chip select and write or read lines. Although
there is just one I/O port and 4 status registers, they
can be read out in a round robin fashion through the
same port as shown in Figure 22. Other registers like
the Configuration, Individual Address registers can be

accessed only through DMA. All the internal registers
can be dumped into memory by DMA using the Dump
command. The execution of some of the commands is
oescrioeo in section 4. :See the !s~:)1S!s Keterence Manual
for details on these commands.

3.9 .Debug and Diagnostic Aids
Besides the standard functions that can be used directly
for StarLAN, the 82588 offers many debug and diag-

82588 REGISTER SET

~

_-II---f~--I---"L-.~--

I

t

COMMAND

STATUS

I

~

WRITE ONLY

READ ONLY

CONFIGURATION
IA
MULTICAST

READ
&

WRITE

Tx CRC
Rx CRC

IMPLICIT REGISTERS
(OVER 50 BYTES)
231422-22

Figure 21. Register Access

1-100

AP·236

4 Status registers are accessed through one read port
POINTER

L

o:J

STATUS 0

1-----1
STATUS 1

--+ I READ PORT

STATUS 2
STATUS 3

231422-23

The pointer can be changed using a command or can be automatically incremented.

READ_STATUS_588: PROCEDURE;

COMMAND 15 *f
RELEASE POINTER, INITIAL = 00
f*

OUTPUT (CS_588) = 15;
STATUS_588(0)=INPUT (CS_588)
STATUS_588(1)=INPUT (CS_588)
STATUS_588(2)=INPUT (CS_588);
STATUS_588(3)=INPUT (CS_588);
RETURN
END READ_STATUS_588;

f*

of

f* REFRESH STATUS REGISTER IMAGE *f
/* . IN MEMORY.

READING 4 STATUS REGISTERS
Figure 22. Reading the Status Register

± 62.5 ns at 1 Mbs for both 8X, 16X Manchester encoded data.

nostics functions. The DIAGNOSE command of the
82588 does a self-test of most of the counters and timers
in the 82588 serial unit. Using the DUMP command,
all the internal registers of the 82588· can be dumped
into the memory. The TDR command does Time Domain Reflectometery on the n.etwork. The 82588 has
two loopback modes of operation. In the internal loopback mode, the TXD line is internally connected to the
RXD one. No data appears outside the chip, and the
82588 is isolated from the link. This mode enables
checking of the receive and transmit machines without
link interference. In the external loopback mode, the
82588 becomes a full duplex device, being able to receive its own transmitted frames. In this mode data
goes through the link and all CSMA/CD mechanisms
are involved.

Jitter ~ ± variation of an edge from its nominal position.
Jitter can occur on every edge.

I dW I dW I

r:+= :

______ ____
:._._L
=F-:

___ ________ __ •
~

~.

~

1-1.- - - W - - - - - - I ,1

231422-78
x8

x16

± V'6

±1/16

NRZI
(Code Violations Enabled)

±1/16BT

±3/32 BT

NRZI
(Code Violations Disabled)

±3/16 BT

±3/16 BT

Manchester

3.10 Jitter Performance
When the 82588 receives a frame from the HUB, the
signal has jitter. Jitter is the shifting of the edges of the
signal from their nominal position due to the transmission over a length of cable. Many factors like, intersymbol interference (pulses of different widths have different delays through the transmission media), rise and
fall times of drivers and receivers, cross talk etc., contribute to the jitter. StarLAN specifies a maximum jitter of ± 62.5 ns whenever the signal goes from a
NODE/HUB or HUB/HiJB. Figure 23 shows that the
jitter tolerance of the 82588 is exactly the required

I dW I dW I

Figure 23. 82588 Jitter Performance

4.0 THE 82588
This chapter describes the basic 82588 operations.
Please refer to the 82588 reference manual in Intel Microcommunications Handbook for a detailed description. Basic operations like transmitting a frame, receiving a frame, configuring the 82588 and dumping the
register contents are discussed here to give a feel for
how the 82588 works.

1-101

inter
4~1

AP-236

status registers to fmd out if the transmission was successful. If a collision occurs during transmissiQn, the
82588 aborts transmission and generates the jam sequence, as required by ,IEEE 802.3, and informs the
CPU through interrupt and the status registers. It also
starts the back-off algorithm.

Transmit and Retransmit
Operations

To transmit a frame, the CPU prepares a block in the
memory called the transmit data block. As shown in
Figure 24, this block starts with a byte count field, indicating how long the rest of the block is. The destination
address field contains the node address of the destination. The rest of the block contains the information or
the data field of the frame. The CPU also programs the
DMA controller with the start address of the transmit
data block. The DMA byte count must be equal to or
greater than the block length. The 82588 is then issued
a TRANSMIT command-an OUT instruction to the
command port of the 82588. The 82588 starts generating DMA requests to read in the transmit data block by
DMA. It also determines whether and how long it must
defer on the link and after that, it starts transmitting
the preamble. The 82588 constructs the frame on the
fly. It takes the destination address from the memory,
source address from its own individual address memory
(previously programmed), data field from the memory
, and the CRC, is generated on chip, at the end of the
frame.

To re-attempt transmission, the CPU must reinitialize
the DMA controller 7to the start of the transmit data
block and issue a RETRANSMIT command to the
82588. When the 82588 receives the retransmit command and the back-off timer has expired, it transmits
.again. Interrupt and the status register contents again
indicate the success or failure of the (re)transmit attempt.
.
The main difference between transmit and retransmit
commands is that retransmit does not clear the internal
count for the number of collisions occurred, whereas
transmit does. Moreoever, retransmit takes effect only
when the back-off timer has expired.

. 4.2 Configuring the 82588
To initialize the 82588 and program its network and
system parameters, a configure operation is performed.
It is very similar to the transmit operation. Instead of a
transmit data block as in transmit command, a configure data block-shown in Figure 12-is prepared by
the CPU in the memory. The first two bytes of the
block specify the length of the rest of the block, which
specify the network and system parameters for the
82588. The DMAcontroller is then programmed by
the CPU to the beginning of this block and a CONFIGURE command is issued to the 82588. The 82588 reads
in the parameters by DMA and loads the parameters in
the on-chip registers.

I. Prepare Transmit Data-Block in Memory
2. Program DMA Controller
3. Issue Transmit Command on the Desired
Channel
BYTE
COUNT
DESTIN.
ADDRESS

INFORMATION

U

Similarly, for programming the INDIVIDUAL ADDRESS and MULTICAST ADDRESSes, the DMA
controller is used to load the 82588 registers. '

231422-25

Transmit Data Block

4.3 Frame Reception

4. Interrupt is received on completion of command or if the command was aborted or
there was a collision. The status bytes 1 and
2 indicate the Jesult of the operation.
6
TX
'OEr

COll

5

HRT MAX
BEAT COll
TX
OK

4

2

o
STAnJS 1

NUM. or COlliSIONS

I lOST I lOST IUNDER
CRS
CTS RUN STAnJS 2

231422-26

TransmIt & Retransmit Results Format
Figure 24. Transmit Operation

At the conclusion of transmission the '82588 ,generates
an interrupt to the CPU. The CPU can then read the

Before enabling the 82588 for reception the CPU must
make a buffer available for the frame to be received.
The CPU must program the DMA controller with the
starting address of the buffer and then issue the lULENABLE command to the 82588. When a frame arrives at the RxD pin of the 82588, it starts being received. Only if the address in the destination address
matches either the Individual address, Multicast address or if it is a broadcast address, is the frame deposited into memory by the 82588 using DMA. The format
of storage in the memory is shown in Figure 25. At the
end, a two byte field is attached which shows the status
of the received frame. If CRC, alignment or overrun
errors are encountered, they are reported. An inter-

1-102

inter

AP-236

RECEIVED FRAME

1. Prepare a Buffer for Reception

2. Program DMA Controller
3. Issue Receiver Enable Command
When a frame is received, it is deposited in the
memory. Receive status bytes (2) are appended to
the frame in the memory, byte count written in the
status registers 1, 2, and an interrupt is generated.
RECEIVE
STATUS

SRT
FRM

DESTIN.
ADDRESS

SOURCE
ADDRESS

NO
EOF
RCV
O.K.

CRC
ERR

ALG
ERR

STATUS REG. 1
STATUS REG. 2

INFORMATION

OVER
RUN

~

BYTE
COUNT

A

RECEIVE
STATUS
./

231422-27

Figure 25. Receive Operation (Single Buffer)

rupt from 82588 occurs when all the bytes have been
transferred to the memory. This informs the CPU that
a new frame has been received.
If the received frame has errors, the CPU must recover
(or re-use) the buffer. Note that the entire frame is deposited into one buffer. The 82588 when NOT configured for the external loopback mode, will detect collisions (code violations) during receptions. If a collision
is detected, the reception is aborted and status updated.
CPU is then informed by an interrupt (if the collided
frame fragment is shorter than the address length, no
reception will be started), and no interrupt will happen.

4.3.1 Multiple Buffer Frame Reception
It is also possible to receive a frame into a number of
fixed size buffers. This is particularly economical if the
received frames vary widely in size. If the single buffer
scheme were used as described above, the buffer required would have to be bigger than the longest expected frame and would be very wasteful for very short
(typically acknowledge or control) frames. The multiple buffer reception is illustrated in Figure 26. It uses
two DMA channels for reception.

@BUFFER 1
@BUFFER 2
@BUFFER 3

·
·
··

@BUFFER N

Buffer
Pointer
Table
(Managed by CPU)

231422-28

Figure 26. Multiple Buffer Reception

1-103

intJ

AP-236

As in single buffer reception, the one channel, say channel 0, of the DMA controller is programmed to the
start of buffer I, and the R25RR i~ p.n~hlprl fnr rprP!'tlr'!!
with the chaining bit set. As soon as the first byte is
read out of the 82588 by the DMA controller and written into the first location of buffer 1, the 82588 generates an interrupt, saying that it is filling up its last available buffer and one more buffer must be allocated. The
filling up of the buffer 1 continues. The CPU responds
to the interrupt by programming the other DMA channel--channel I-with the start address of the second
buffer and issuing an ASSIGN ALTERNATE buffer
command with an INTACK (interrupt acknowledge).
This informs the 82588 that one more buffer is available on the other channel. When buffer 1 is filled up
(the 82588 knows the size of buffers from the configuration command), the 82588 starts generating the DMA
requests on the other channel. This automatically starts
filling up buffer 2. As soon as the first byte is written
into buffer 2, the 82588 interrupts the CPU again asking for one more buffer. The CPU programs the channel of the DMA controller with the start address of
buffer 3, issues an ASSIGN ..LTERNATE buffer command with INTACK. This keeps the buffer 3 ready for
the 82588. This switching of channels continues until
the entire frame is received generating an end of frame
interrupt. The CPU maintains the list of pointers to the
buffers used.

°

Since a new buffer is allocated at the time of filling up
of the last buffer, the 82588 automatically switches to
the new buffer to receive the next frame as soon as the
last frame is completely received. It can start receiving
the new frame almost immediately, even before the end
of frame interrupt is serviced and acknowledged by' the
CPU. If a new frame comes in, and the previous frame

interrupt is not yet acknowledged, another interrupt
needed for new buffer allocation is buffered (and not
lnlilt)

A Col Clnnn

'!lie!

thoIlIo rt ...cot nneo

----J' - - - - - - - - _ .....---

---~ ...

......... -

........ : ....
-O""'-, +"................
-

t~ ......l ....... n .. nl .... ...I ....... ...I
..... - -...~ ... u··& ...

terrupt line goes active again for the buffered one.
If by the time a buffer fills up no new buffer is available,
the 82588 keeps on receiving. An overrun will occur
and will be reported in the received frame status. How. ever, ample time is available for the allocation of a new
buffer. It is roughly equal to the time to fill up a buffer.
For 128 byte buffers it is 128 x 8 = 1024 ms or approximately 1 millisec. You get 1 ms to assign a new
buffer after getting the interrupt for it. llence the process of multiple buffer reception is not time critical for
the system performance.

This method of reception is particularly useful to guarantee the reception of back-to-back frames separated by
IFS time. This is because a new buffer is always available for the new frame after the current frame is received.
Although both the DMA channels get used up in re-.
ceiving, only one channel is kept ready for reception
and the other one can be used for other commands until
the reception starts. If an execution command like
transmit or dump command is being executed on a
channel which must be allocated for recepfion, the
command gets automatically aborted when the AS~
SIGN ALTERNATE BUFFER command is issued to
the channel used for'the execution command. The interrupt for command abortion occurs after the end of
frame interrupt.

1-104

AP-236

the 82588 command register and knowing the results (if
any) through the status registers.

4.4 Memory Dump of Registers
All the 82588 internal registers can be dumped in the
memory by the DUMP command. A DMA channel is
used to transfer the register contents to the memory. It
is very similar to reception of a frame; instead of data
from the serial link, the data from the registers gets
written into the memory. This provides a software debugging and diagnostic tool.

4.5 Other Operations
Other 82588 operations like DIAGNOSE, TDR,
ABORT, etc. do not require any parameter or data
transfer. They are executed by writing a command to

5.0 StarLAN NODE FOR IBM PC
This chapter deals with the hardware-the StarLAN
board-to interface the IBM PC to a StarLAN Network. This is a slave board which takes up one slot on
the I/O channel of the IBM PC. Figure 27 shows an
abstract block diagram of the board. It requires the
IBM PC resources of the CPU, memory, DMA and
interrupt controller on the system board to run it. Such
a board has two interfaces. The IBM PC I/O Channel
on the system or the parallel side and the telephone
grade twisted pair wire on the serial side. Figures 28, 29
show the circuit diagram of the board.

PULSE
TRANSFORMER

TELEPHONE
JACK

8 BIT BUS
82588

TxD

PULSE

JIII.:;""'--1 SHAPING
SYSTEM
BUS

CONTROL

< >

RxD

SYS CLK

SQUELCH

+
ENABLE
CIRCUITS
231422-29

Figure 27. 82588 Based StarLAN Node

1-105

5

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.

OSC

D

I

+D?
+D.
+DO
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'DO
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+D'
+De

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AS

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£.
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81

-DACK.l
t::I

-DACKa

'AS
+A.

A24
A2&
A2.
A2?

+A?
'A.
+AS
+A4

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All

~ll

fli

0

U4

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a

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~
0

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'8

&
4

REG

REG

~ .....
.8

ua

""
Irr~~Q·

,.
II
8

II

'2

EN
UO

o
•
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U2

704L5125

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8

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9

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6

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15

~

TK. 2a
RK.

2

, .........

~&

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A22
A2.

..., ...

CLK

~ 1*

5
4

i!R

1974L832

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ca
c

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2'iiF2
231422-80

intJ

AP-236

to 82588 for commands and status, address 30lH accesses an on board control port that enables the various

5.1 Interfacing to the IBM PC 1/0
Channel

1ntprrnnt tIInti OM A linpl;l

IBM PC has '8 slots oil the system board to allow expansion of the basic system. All of them are electrically
identical and the I/O channel is the bus that links them
all to the 8088 system bus. The I/O channel contains
an 8 bit bidireCtional data bus, 20 address lines, 6 levels
of interrupt, 3 channels of DMA control lines and other
control lines to do I/O and memory read/write operations. Figure 30 shows the signals and the pin assignment for the I/O Channel.

spaces from 300H to 30FH. This was done to keep simplicity and minimum component count. Registers address decoding is done using a PAL (16L8) and an external NAND gate (U8).

Hex Range
OOO-OOF
020-021
040-043
060-063
080-083
OAX'
OCX
OEX
200-20F
210-217
220-24F
278-27F
2FO-2F7
2F8-2FF

Rear Panel
SIGNAL NAME
GNO

...,...

SIGNAL NAME
81

Al

~

1/0 CH CK

+RESET DRV

+07

+5V

+06

+IRQ2

+05

-5VOC

+04

+ORQ2

+03

-12V

+02

-CARD SLCTD

+01

+12V

+00

GNO

+1/0 CH ROY

810 Al0

-MEMW

+AEN

-MEMR

+A19

-lOW

+A18

-lOR

+A17

-OACK3

+A16

+ORQ3

+A15

-OACKl

+A14

+DROl

+A13

-OACKO

3AO-3A9
3BO-3BF
3CO-3CF
3DO-3DF
3EO-3E7
3FO-3F7
3F8-3FF

+Al1

820 A20

+IRQ6

+Al0

+IRQ7

+A9

+IRQ5

+A8

+IRQ4

+A7

+IRQ3

+A6

-OACK2

+A5

+T/C

+A4

+ALE

+Al

+5V

+A2

+OSC
GNO

300-31F
320-32F
378-37F
380-38C··
380-389"

+A12

CLOCK

\.

831 A31

+AO

....;;..

\

Usage
DMA Chip 8237 A-5
Interrupt 8259A
Timer 8253-5
PP18255A-5
DMA Page Registers
NMI Mask Register
Reserved
Reserved
Game Control
Expansion Unit
Reserved
Reserved
Reserved
Asynchronous Communications
(Secondary)
Prototype Card
Fixed Disk
Printer
SDLC Communications
Binary Synchronous Communications
(Secondary)
Binary Synchronous Communications
(Primary)
IBM Monochrome Display/Printer
Reserved
Color/Graphics
Reserved
Diskette
Asynchronous Communications
(Primary)

• At power-on time, the Non Mask Interrupt into the
8088 is masked off.
This mask bit can be set and reset through
system software as follows:
Set mask: Write hex 80 to I/O Address hex AO
(enable NMI)
Clear mask: Write hex '00 to I/O Address hex AO
(disable NMI)
•• SDLC Communications and Secondary Binary
Synchronous Communications cannot be used
together because their hex addresses overlap.

+Al

...;..

PUP." thnnn-h nnhr turn g,.L

d~~;e;r~r~-;e~~d: -th~-~rd ;;~--~llth~ -1-6'add;es~;s

COMPONENT SIDE

231422-31

Figure 39.1/0,Channel Diagram
5.1.1 REGISTER ACCESS AND DATA BUS
INTERFACE

Figure 31. I/O Address Map
The CPU accesses the StarLAN adapter card through 2
I/O address windows. Address 300H is used to access

1-108

inter

AP-236

M-A9---+
AO---.

~ CS_ (to 588)

LOGIC
U2, U8

AEN---+

~ LDPRL (to DMA, INTERRUPT enable lines)

IOW_---+

'-----'

231422-56

Register Access

Format of Following Equations Will Be According To
The Following Specifications:
INVERT
SIGNAL ACTIVE LOW
II:

LOGIC AND

#

LOGIC OR

A9NANDA8
CS_

=I

LDPORT_
BUSEN_

=I

(A9

( IAEN

=I

II:

IA9NANDA8

II:

( lAEN

=DACKl_

A8)

II:

II:

II:

IA7

IA9NANDA8

DACK2_

II:

II:

IA6

IA5

II:

II:

IA4

II:

lAO )

IA7

II:

IA6

IA5

II:

IA4

II:

(I ( IAEN

II:

IA9NANDA8

II:

IA7

II:

II:

The signal CS_ decodes address 300H, it is only active
when AEN is inactive meaning CPU and not DMA
cycles. LDPORT_ has exactly the same logic for address 301H, but it is only active during I/O write cycles. The I/O port sitting on address 30lH is write
only. The data BUS lines DO to D7 are buffered from
the 82588 ·to the PC bus using an 74LS245 transceiver
chip.

II:

AO
IA6

IIOWR_ )

II:
II:

IA5

II:

IA4»;

The Bus transceiver is enabled if: A DMA access is
taking place, or I/O ports 300H to 30FH are being
accessed.
5.1.2 Control Port
As mentioned the StarLAN adapter port has. a 4-bit
write only control port. The purpose of this port is to
selectively enable the DMA and INTERRUPT request
lines. Also it can completely disable the transmitter.
Control Port Definition

I ENDRQ1 I

ENDRQ3

I

EN INTER

I TXEN

TO 588

231422-57

Data Bus Interface

ENDRQl, ENDRQ2 : "I" Enable DMA requests.
: "I" Enable INTERRUPT
ENINTER
request.
: "I" Enable the transmitter.
TXEN
On power up all bits default to "0".

1-109

intJ

AP-236

5.1.3 CLOCK GENERATION
The 82588 requires two clocks for operation. The system clock and the serial clock. The serial clock can be
generated on chip by putting a crystal across Xl and
X2 pins. Alternatively, an externally generated clock
:can be fed in at pin XI (with X2 left open). In both
cases, the frequeQcy must be either 8 or 16 times (sampling factor) the desired bit rate. For StarLAN, 8 or 16
MHz are the correct values to generate I Mbls data
rate. A configuration parameter is used to tell the
82588 what the sampling factor is. An externally supplied clock must have MOS leve~s (~.6V -3.9V). ~pec~­
cations for the crystal and the CIrcuIt are shown In FIgure 32.
The system clock has to be supplied externally. It can
be up to 8 MHz. This clock runs the parallel side of the
82588. Its frequency does not have any impact on the
read and write access times but on the rate at which
data can be transferred to and from the 82588 (Maximum DMA data rate is one byte every two system
clocks). This cI~ck doesn't require MOS levels.
The 1/0 channel of the IBM PC supplies a 4.77 MHz
signal of 33% duty cycle. This signal could be used as a
system clock. It was decided, however, to generate a
separate clock on the StarLAN board to be independent of the 1/0 channel clock so that this board can
also be used in other IBM PCs and also in some other
compatibles. The 8 MHz system clock is generated us-

ing a DIP OSCILLATOR which have the required 50
ppm tolerance to meet StarLAN. This clock is converted to MOS levels by 74HCTOO and fed into both the
system and' serial clock inputs.
5.1.4 DMA INTERFACE
The 82588 requires either one or two DMA channels
for full operation. In this application, one channel is
dedicated for reception and the other is used for transmissions and the other commands. Use of only one
DMA channel is possible' but may require more complex' software, also some RX frames may be lost during
switches of the DMA channel from the receiver to the
transmitter (Those frames will be recovered by higher
layers of the protocol). Also using only .0J?e pMA
channel will limit the 82588 loopback functionalIty. So
the recommendation is to operate with two DMA channels if available. APPendix C describes a method of operating with only one DMA channel without loosing
RX frames.
'
The IBM PC system board has on~ 8237A DMA controller. Channel 0 is used for doing the refresh of
DRAMs. Channels I, 2 and 3 are available for add-on
boards on the I/O Channel. The floppy disk controller
board uses the DMA channel 2 leaving exactly two
channels (I and 3) for the 82588. The situation is worse
if the IBM PC/XT is used, since it uses channel 3 for
the Winchester hard disk leaving just the channel I for

Series Resonance
-Frequency Will Drift by About 400 PPM from Nominal
-No Capacitors Needed
-Doesn't Meet StarLAN Requirements

CRYSTAL

Meeting StarLAN 100 PPM Requirements
-Use Parallel Resonance Crystal
-Recommended For Precise Frequencies
-82588 X-TAL ,Oscillator Stability ± 35 PPM (0-70°C)

.=h
0
--

I

i
i-

Crystal: Load Capacitance
= 20 pF
Shunt Capacitance = 7 pF Maximum
Series Resistance = 30n Maximum
Frequency Tolerance = 50 PPM (0-7fY'C)
CI, C2 -+ 27 pF or 39 pF, 5%
Figur, 32. Crystal Specifications

1-110

C1

82588

C2
231422-81

intJ

AP-236

the 82588. On the other hand, the IBM. PCIAThas 5
free DMA channels. We will assume that 8237ADMA
channels I and 3 are available for the 82588 as in the
case of the IBM PC.
Since the channel 0 of 8237A is used to do refresh of
DRAMs all the channels should be operated in single
byte transfer mode. In this mode, after every transfer
for any channel the bus is granted to the current highest priority channel. In this way, no channel can hog
the bus bandwidth and, more important, the refresh of
DRAMs is assured every 15 microseconds since the refresh channel (number 0) has the highest priority. This
mode of operation is very slow since the HOLD is
dropped by the 8237A and then asserted again after
every transfer. Demand mode of operation is a lot more
suitable to 82588 but it cannot be used because of the
refresh requirements.

5.1.5 INTERRUPT CONTROLLER

The 82588 interrupts the CPU after the execution of a
command or on reception of a frame. It uses the 8259A
interrupt controller on the system board to interrupt
the CPU. There are 6 interrupt request lines, IRQ2 to
IRQ7, on the I/O channel. Figure 34 shows the assignment of the lines. In fact, none of the lines are completely free for use. To add any new peripheral which
uses a system board interrupt, this interrupt needs to
have the capability to share the specific line, by driving
the line with a tri-state driver. The 82588 StarLAN
adapter board can optionally drive interrupt lines
IRQ3, IRQ4 or IRQ5 (An 74LSI25 driver is used).
Number

Usage

NMI

Parity
Timer
Keyboard
Reserved
Asynchronous Communications
(Secondary)
SDLC Communications
SSC (Secondary)
Asynchronous Communications
(Primary)
SDLC Communications
SSC (Primary)
Fixed Disk
Diskette
Printer

0
1
2
3

Whenever the 82588 interfaces to the 8237A in the single transfer mode, there is a potential 8237A lock-up
problem. The 82588 may deactivate its DMA request
line (DREQ) before receiving an acknowledge from the
DMA controller. This situation may happen during
command abortions, or aborted receptions. The 8237A
under those circumstances may lock-up. In order to
solve this potential problem, an external logic must be
used to insure that DREQ to the DMA controller is
never deactivated before the acknowledge is received.
. Figure 33 shows the logic to implement this function.
This logic is implemented in the 16L8 PAL.
The 82588 DREQ lines are connected to the IBM/PC
bus through tri-state buffers which are enabled by writing to 1/0 port 301H. This function enables the use of
either .one or two DMA channels and also the sharing
of DMA channels with other adapter boards.

4

5
6
7

,Figure 34. IBM PC Hardware Interrupt Listing

588REO~
.
DREO
DACK

RESET----------'

588 REO---.l

DREO---.l
231422-82

Figure 33. DMA Request Logic

1-111

inter

AP-236

5.2 Serial Link Interface

5.2.1 TRANSMIT PATH

A ..... _: .... ",1 Ct ......1 "ltrt.T "'..:I ................. l... ........ ...:1 : ....................... ,..+ ... ...:1 +........... ...
... ... Jl".OW-....... u .........
...............................
.., .................... u
.... v ..............................................

Thp

~.L.L

twisted pair wiring using an extension cable (typically
up to 8 meters-25 ft.). See Figure 35. One end of the
cable plugs into the telephone modular jack on the StarLAN board and the other end into a modular jack in
t,he wall. The twisted pair wiring starts at the modular
jack in the wall and goes to the wiring closet. In the
wiring closet, another telephone extension cable is used
to connect to a StarLAN HUB. The transmitted signal
from the 82588 reach the on-board telephone jack
through a RS-422 driver with pulse shaping and a pulse
transformer. The received signals from the telephone
jack to the 82588 come through a pulse transformer,
squelch circuit and a receive enable circuit.

~, L.L.L.L.U..u.&.&.U

~inO'lp

pnrlpti

tr~nQ.m1t Qion~l

nn thp Iyn nin 1q

~~;;v~rt;d-t~-~' diff~;~tial sig~al a~d the rise a~d fall

times are increased to 150 to 200 ns before feeding it to
the pulse transformer (this pulse shaping is not a requirement, but proves to give good results). Am26LS30
is a RS-422 driver which converts the TxD signal to a
differential signal. It also has slew rate control pins to
increase to rise and fall times. A large rise and fall time
reduces the possibility of crosstalk, interference and radiation. By the other hand a slower edge rate increases
the jitter. In the StarLAN adapter card, the first approach was used. The 2~LS30 converts /l square pulse
to a trapezoidal one-see Figure 36. The filtering effect
of the cable further adds to reduce the higher frequency
components from the waveform so that on the cable the
signal is almost sinusoidal. The pulse transformer is for
DC isolation. The pulse transformers from Pulse Engineering-type PE 64382-was used in this design. This
is a dual transformer package which introduces an additional rise and fall time of about 70-100 ns on the
signal, helping the former discussed waveshaping.
5.2.2 IDLE PATTERN GENERATION

INTO IBM PC

WIRING
PANEL

IN THE WIRING CLOSET
231422-33

StarLAN requires transmitters to generate an IDLE
pattern after the last transmitted data bit. The IDLE
pattern is defined to be a constant high level for 2-3
microseconds. The purpose of this pattern is to insure
that receivers will decode properly the last transmitted
data bits before signal decay. Currently the 82588 needs
one external component to generate the IDLE. The operation principle .is to have an external shift register
(74LSI64) that will kind of act as an envelope ,detector
of the TXD line. Whenever the TXD line goes low

Figure 35. Path from StarLAN Board to HUB

82588

TxD

26LS30

\

150n.
RISE/FALL
TIMES

•

II~

~)
231422-34

Figure 36. Wave Shaping
1-112

inter

AP-236

(first preamble bit), the output of the shift register
(third cell) will immediately go low, enabling the RS422 driver, the shift register being clocked by TCLKwill time the duration of the TXD high times. If the
high time is more than 2 microseconds, meaning that
the 82588 has gone idle, the transmitter will be disabled
(See Figure 37). Another piece of this logic is the ORing of the output of the shift register with TXEN-signal which comes from the board control' port. This signal completely disables the transmitter. The other purpose of this enable signal, is to make sure that after
power-up, before the 82588 is configured, the RS-422
drivers won't be enabled (TCLK_ is not active before
the configure command). See Figures 28, 29 for the
complete circuit.
5.3 RECEIVE PATH

The signal coming from the HUB over the twisted pair
wire is received on the StarLAN board through a lOOn
line termination resistor and a pulse transformer. The
pulse transformer is of the same type as for the transmit
side and its function is dc isolation. The received signal
which is differential and almost sinusoidal is fed to the
Am26LS32 RS-422 receiver. As seen from Figure 38
the pulse transformer feeds two RS-422 receivers. The
one on the bottom is for squelch filtering and the one
above is the real receiver which does real zero crossing
detection on the signal and regenerates a square digital
waveform
from
the
sinusoidal
signal
that

is received. Proper zero crossing detection is very essential; if the edges of the regenerated signal are not at zero
crossings, the resulting signal may not be a proper
Manchester encoded signal (self introduced jitter) even
if the original signal is valid Manchester. The resistors
in the lower receiver keep its ·differential inputs at a
voltage difference of 600 mY. These bias resistors ensure that the output remains high as long as the input
signal is more than -600 mY. It is very important that
the RxD pin remains HIGH (not LOW or floating)
whenever the receive line is idle. A violation of this may
cause the 82588 to lock-up on transmitting. Remember,
that based on the signal on the RxD pin, the 82588
extracts information on the data being received, Carrier
Sense and Collision Detect. This squelch of 600 mY
keeps the idle line noise from getting to the 82588. Figure 39 shows that when the differential input of the
receiver crosses zero, a transition occurs at the output.
It also shows that if the signal strength is higher than
-600 mY, the output does not change. (This kind of
squelching is called negative squelching, and it is done
due to the fact that the preamble pattern starts with a
going low transition). Note that the differential voltage
at the upper receiver input is zero when the line is idle.
The output of the squelch goes to a pulse stretcher
which generates an envelope of the received frame, The
envelope is a receive enable signal and is used to AND
the signal from the real zero crossing receiver before
feeding it to the RxD pin of the 82588.

-u::BL
18- 22
TX - FAST CLOCKS

'''--wm.J - - - - - - - - - RS-422

ENABLE-----,~)_______________________________________C_E_LL__~!

231422-83

Figure 37. Idle Generation

1-113

inter

AP-236

FILTERING OF
IoIlm-l F"RF"nllF"Nr.v Nnl<:;F"

:101! ·~I '-. . .I·~.~--,----or

ftl'!"I"t:"nII'!"O '''1:''01'\
0. . . . . . . . . . . . . " , . . . . . 0. ....

CROSSING

>--------------+ DATA

t

TERMINATION

>-----1

TIME
SQUELCH

ENVELOPE
IDLE
DETECT

CARRIER

(OPTIONAL)

INPUT
, DATA

------~

-'I!!!!!!!!!!!!!'"

CARRIER -

~----------------

_ _ _ _ _--'
3 EDGES

b-

1.6}Ls

Figure 38. Input Ports

600
400

...J

...'"

;:

200

%

...""
"-

mV

0

a

-200

.......
""

-600

"-

-400

~::l

"'11.

... -

0%
D::

FILTERED-OUT
BY SQUELCH

,,,t

I

LJ1S

VOL~~__________________________

VOHtmu
•
u'
VOL

-r------------

Figure 39. Squelch Circuit Output

1-114

231422-35

231422-84

inter

AP-236

5.4 80188 Interface to 82588

5.5 iSBX Interface to StarLAN

Although the 82588 interfaces easily to almost any
processor, no processor offers as much of the needed
functionality as the 80186 or its 8 bit cousin, the 80188.
The 80188 is 8088 object code compatible processor
with DMA, timers, interrupt controller, chip select logic, wait state generator, ready logic and clock generator
functions on chip. Figure 40 shows how the 82588, in a
StarLAN environment interfaces to the 80188. It uses
the clock, chip select logic, DMA channels, interrupt
controller directly from the 80188. The interface components between the CPU and the 82588 are totally
eliminated.

Figure 41 shows how to interface the 82588 in a StarLAN environment to the iSBX bus. It uses 2 DMA
channels-tapping the second DMA channel from a
neighboring iSBX connector. Such a board can be used
to make a StarLAN to an Ethernet or a SNA or DECNET gateway when it is placed on an appropriate SBC
board. It may also be used to give a StarLAN access to
any SBC board (with an iSBX connector) independent
of the type of processor on the board.

1-115

cl

4

D

SYSTEn RESET
BIUBB

..

8Ea "'4

jj

"2

RESET "1
DRQ818
BRQ. 19

."

a'
I:
;

..

AD?
AD6
AD6
AD"

17
16
13
11

....•••

ESET

IDLE
lfR'f' "')(21

.•"•• h

....
?
!....

Rn 5
eLI< OUT

......, :S'
Ol

INTI

H.le

T)lt"~~~~

'"

.

~

."

U'

iil'

p.)
Co)
CJ)

U3

iS'

B

co
J\)

~

+5U

.4

,.0

704LS191

~10

..

I

Q.~

B
•
C
D

4

I?

~.co
§

QB
QC
QD

2
'"
1

LIJ

1
D....U 5

nA'
Ul

5

••
•••.5
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231422-86

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AP-236

6.0 THE StarLAN HUB

6.1 A. StarLAN Hub for the. IBM/PC

The function of a StarLANHUB is described in section
2.0. Figure 42 shows a block diagram of a HUB. It
receives signals from the nodes (or lower level HUBs)
detects if there is a collision, generates the collision
presence signal, re-times the signal and sends it out to
the higher level HUB. It also receives signals from the
higher level HUB, re-times it and sends it to all the
nodes and lower level HUBs connected to it. If there is
no higher level HUB, a switch on the HUB routes the
upstream received signal down to all the lower nodes.
The functions performed by a HUB are:

Figure 43 shows the implemention of a 5/6 port HUB
for the IBM/PC.
The idea of the following design is to show a HUB that
plugs into the IBM/PC backplane. This HUB not only
gets its power from the backplane, but also enables the
host PC to be one NODE into the StarLAN network.
This embedded node scheme enables further savings
due to the fact that aU the analog interface for this port
is saved (receiver, transmitter, transformer, etc).
This kind of board would suit very much a smaU cluster topology (very typical in departments and small offices) where the HUB board would be plugged into the
FILE SERVER PC (pC/XT, PC/AT).

"Receiving signals, squelch
• Carrier Sensing
'Collision Detection
'Collision Presence Signal Generation
'Signal Retiming
"Driving signals on to the cable
'Jabber Function
'Receive protection Timer

The HUB design doesn't implement the Jabber and the
protection timers as called by the IBASE5 draft standard. Those functions are optional and were not closed
during the writing of this AP-NOTE. This HUB does
implement the RETIMING circuit which is an essential requirement of StarLAN..
Figures 44 to 49 show a complete set of schematics for
the HUB design.

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RECEIVE PAIR # N
231422-40

Figure 42. Star LAN HUB

1-118

inter

AP-236

PHONE JACKS

231422-87
• Low Cost HUB, Uses IBM/PC Power Supply
• 82588, Embedded Port Savings
Transformers
422 Drivers
• Functional StarLAN Cluster, For Low Cost/Small Topologies

Figure 43, IBM/PC Resident HUB

1-119

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231422-93

inter

AP-236

The time squelch for the NODE board is implemented
by the 82588 (see section 3.7) this circuit makes sure
that pulses that are shorter than a specified duration
will be filtered out.

6.1.1 HUB. INPUT PORTS
Figure 38 shQWS a block diagram of an input port. Dif-.
ferently than the implementation in Figure 29 the HUB
input port is potentially more complex than the NODE
input port. The reason being that the HUB is a central
resource arid much more sensitive to noise. For example, if the NODE input port would falsely interpret
noise on an IDLE. line as valid signal, the worst case
situation would be that this noise would be filtered out
by the 82588 time squelch circuitry, on the HUB by the
other hand, this false carrier sense could trigger a COLLISION and a good frame (on another input) potentially discarded.

The other components of the block diagram were explained in section 3.0.
The HUB design doesn't implement the HIGH FREQUENCY FILTER and TIME SQUELCH. In the
HUB design as an output of each input port, two signals are available: Rn, En, (RA, RB ... , EA, EB ... ).
The Rn signals are the receive data after the zero crossing receivers. The En lines are CARRIER SENSE signals. The HUB design supports either 5 or 6 input
ports, dependent upon if it is configured as IHUB or
HHUB. Port RE, EE (Figure 49) is bidirectional, configurable for either input or output. Port RF, EF_ is
the embedded 82588 port, and doesn't require the ana. log circuitry (EF is inverted, being generated from the
. RTS_ signal).

As shown in Figure 38 immediately after the termination resistor, there is a HIGH FREQUENCY FILTER
circuit. The purpose of this circuit is to eliminate high
frequency noise components keeping noi~e jitter into
the allocated budget (about ± 30 ns). A 4 MHz two
pole butterworth filter is being recommended by the
IEEE 802.3 IBASE5 task force (see Figure 50).

·"I!f !110~ XX ::~TED

RXVE...RI-_...._ _ _ _ _ _ _ _

231422-94

Figure 50. Receiver High Frequency Filter

1-126

inter

AP-236

6.1.2 COLLISION DETECTION
Rn and En signals from each channel are fed to a 16L8
PAL, where the collision detection function is per·
formed.

Collision Detection in the Star LAN HUB is performed
by detecting the presence of activity on more than one
input channels. This means if the signal En is active for
more than one channel, a collision is said to occur. This
translates to the PAL equations:

COLLISION DETECTION:
COT = ! (EA & !EB & !EC & !ED & !EE & EF_ #
! EA & EB & IEC & !ED & !EE & EF_ #
!EA&!EB&EC&!ED&!EE&EF_ #
!EA&!EB&!EC& ED&!EE&EF_ #
! EA & IEB & !EC & lED & EE & EF_ #
!EA&!EB&!EC&!ED&!EE&!EF_ #
! EA & !EB & !EC & !ED & !EE & EF_);

(only EA active)
(only EB active)
(only EC active)
(only ED active)
(only EE active)
(only EF active)
(none of the inputs active)

COLLISION DETECTION SR·FF:
COLLEN_ = ! (COT # COLLEN );

(set with collision)

COLLEN_ = ! ( RESET_ # COLLEN_ #
( !CDT & !EA & !EB & !EC & !ED & !EE & EF_);
( reset when all inputs inactive)
RECEIVE DATA OUTPUT:
RCVDAT = ( (RA # !EA ) & ( RB # !EB ) & ( RC # !EC) &
(RD # !ED) & (RE # lEE) & (RF # EF_»;
(output is high ifno active input)

1·127

AP·236

The COLLEN signal once triggered will stay active until all inputs go quiet. This signal is used externally to .
either enable passing RCVDAT or the collision presence signal (CPS) to the retiming logic. An external
multiplexer using 3 nand gates is used for this function.
Note that in this specific implementation the. CPS/
RCVDAT mUltiplexer is before the retiming logic,
which is different from Figure 42 diagram. StarLAN
provides enough BIT-BUDGET delay to allow the CPS
signal to be generated through the retiming FIFO. In
this HUB implementation it was decided to use this
option to make sure that the CPs startup is synchronized with the previously transmitted bit as required by
the lBASE5 draft.
'
6.1.3 THE LOCAL 82588

As described before, the purpose of the local 82588 is to
enable the Host IBM/PC to also be a node into the
Star LAN network. The interface of this 82588 is exactly similar to the one explained in section 5. The RTS_
signal serves as the carrier EF_ signal, and TXD as
RF signal. This local node interfaces to the HUB without any analog interface which is a significant saving.
6.1.4 THE COLLISION PRESENCE SIGNAL

The Collision Presence Signal (CPS) is generated by the
HUB whenever the HUB detects a collision. It then
propagates the CPS to the higher level HUB. The CPS
signal pattern is shown in Figure 51. Whenever a StarLAN node receives this signal, it should be able
to detect within a very few bit times that a collision
occurred. Since the, nodes detect the occurrence of a '
collision by detecting violations in Manchester encoding, the CPS must obviously be a signal which violates

Manchester encoding. Section 3.5 shows that the CPS
has missing mid-cell transitions occurring every two
and a half bit cells. These are detected as Manchester
code violations. Thus, the StarLAN node is presented'
with collision detection indications every two and a half
ms. This results in fast and reliable detection of collisions. CPS has a period of 5 ms.
One may wonder why such a strange looking signal was
selected for CPS. The rationale is that this CPS looks
very much like a valid Manchester signal-edges are
0.5 or 1.0 microsec. apart-resulting in identical radiation, cross-talk and jitter characteristics as a true Manchester. This also makes the re-timing logic for the signals simpler-it need not distinguish between valid
Manchester and CPS. Moreover, this signal is easy to
generate.
A few important requirements for CPS signal are: a) it
should be generated starting synchronized with the last
transmitted bit cell. CPS is allowed to 'start either low
or high, but no bit cell of more than 1 microsecond is
allowed (Avoid false idles, very long "low" bits). b)
once it starts, it should continue until all the input lines
to the HUB die out. Typically, wheh the collision occurs, the multiplexor in the HUB switches from RCV
signal to the CPS. This switch is completely asynchronous to the currently being transmitted data, and by
such may violate the requirement of not having bit cells
longer than 1 /Ls. In order to avoid those long' pulses,
the output of the CPS/RCVDAT multiplexer is passed
through the retiming circuitry which will correct those
long pulses to their nominal value. The reason for restriction b) is to ensure that the CPS is seen by all nodes
on the network since it is generated until every node
has finished generating the Jam pattern.

I 2t I t I 2t I 2t It i t = 0.5 }-'S
~5}-'s PERIOD---I
• MISSING MID-CELL TRANSITION

231422-42

• Collision Presence Signal (CPS) is generated by the HUB when it detects more than one input line active.
• CPS violates Manchester encoding rules-due to missing mid-cell transitions-hence is detected as a collision by the DTE (82588).
Choice of Collision Presence Signal
• It is a Manchester look-alike signal-edges are 0.5 or 1.0 /Ls apart.
- Identical radiation, crosstalk and jitter characteristics
- Eases ietiming of the signal in the HUB
• It is easy to generate--1.5 TTL pack, or in a PAL
Figure 51. Collision Presence Signal

1-128

AP-236

CPS is generated using a 4-bit shift register and a flipflop as shown in Figure 52. It works off a 2 MHz clock.
A closer look at the CPS waveform shows that it is
inverse symmetric within the 5 /ks period. The circuit is
a 5-bit shift register with a complementary feedback
from the last to the first bit. The bits remain in defined
states (01100) till collision occurs. On collision the bits
start rotating around generating the pattern of
0011011001, 0011011001, 00110 ... with each state
lasting for 0.5 /ks.

a result of jitter, may no longer be decodable. The process of either re-aligning the edges or reconstructing the
signal or even re-generating' the signal so that it once
again "looks new" is called re-timing. StarLAN requires for the signal to be re-timed after it has travelled
on a segment of cable.· In a typical HUB two re-timing
circuits are necessary; one for the signals going upstream towards the higher level HUB and the other for
signals going downstream towards the nodes.
6.1.6 RETIMING CIRCUIT, THEORY OF

o

OPERATION

o
COLLISION
, - - -..... PRESENCE
SIGNAL
Q

COLLISION

231422-43

Figure 52. Collision Presence
Signal Generation

6.1.5 SIGNAL RETIMING
Whenever the signal goes over a cable it suffers jitter.
This means that the edges are no longer separated by
the same 0.5 or 1.0 /ks as at the point of origin. There
are various causes of jitter. Drivers, receivers introduce
some shifting of edges because of differing rise and fall
times and thresholds. A random sequence of bits also
produces a jitter which is called intersymbol interference, which is a consequence of different propagation
delays for different frequency harmonics in the cable.
Meaning short pulses have a longer delay than long
ones. A maximum of 62.5 ns of jitter can accumulate in
a StarLAN network from a node to a HUB or from a
'HUB to another HUB. The following values show what
are the jitter components:
Transmitter skew
Cable Intersymbol interference
Cable Reflections
Reflections due to receiver
termination mismatch
HUB fan-in, fan-out
Noise
Total

± 10 ns
± 9 ns

± 8 ns
±5 ns
±5 ns
±25.5

±62.5 ns

It is important for the signal to be cleaned up of this
jitter before it is sent on the next stretch of cable because if too much jitter accumulates, the signal is no
longer meaningful. A valid Manchester signal would, as

This section will discuss the principles of designing a
re-timing circuit. Figure 53 shows the block diagram of
a re-timing circuit. The data coming in is synchronized
using an 8 MHz sampling clock. Edges in the waveform
are detected doing an XOR of two consecutive samples.
A counter counts the number of 8 MHz clocks between
two edges. This gives an indication of long (6 to. 10
clocks) or short (3 to 5 clocks) pulses in the received
waveform. Pulses shorter than 3 clocks are filtered out.
Every time an edge occurs, the length-(S)hort or
(L)ong-of the pulse is fed into the FIFO. Retiming of
the waveform is done by actually generating a new
waveform based on the information being pumped into
the FIFO. The signal regeneration unit reads the FIFO
and generates the output waveform out of 8 MHz clock
pulses based on what it reads, either short or longs. In
summary every time a bit is read from the fifo, it indicates that a transition needs to occur, and when to fetch
the next bit. When idle the output of the retiming logic
starts with a "high" level.
FIFO
empty

S
S
L
L

Output

...... 1111
0000
1111
00000000
11111111

It can be seen that the output always has edges separated by 4 or 8 clock pulses---D.5 or 1.0 /ks.
The FIFO is primarily needed to account for a difference of clock frequencies at the source and regeneration
end. Due to this difference, data can come in faster or
slower than the regeneration circuit expects. A 16 deep
FIFO can handle frequency deviations of up to 200
ppm for frame lengths up to 1600 bytes. The FIFO also
overcomes short term variations in edge separation. It
is essential that the FIFO fills in up to about half before
the process of regeneration is started. Thus, if the regeneration is done at a clock slightly faster than the
source clock, there is always data in the FIFO to work
from. That is why the FIFO threshold detect logic is
necessary, which counts 8 edges and then enables the
signal regeneration logic.
.

1-129

intJ ,
Example:
Input Waveform

AP-236

... 11110001111000000011111111110001111100 ...

I

Input into
the FIFO

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Regenerated Output:
... 1 11110000111100000000111111110000111 ...
Output:
FIFO:
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INPUT
DATA ---:-+

INCREt.lENT EDGE !
COUNTER

efl FO ACCOt.lt.lODATES fOR fREQ.
DR 1m (SPEC 100 PPt.l)

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(1 500 BYTES x 8) x 200 PPt.l

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EDGE
DETECTOR

SYNCHRONIZER

8t.lHztLOCK



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DISCRlt.lINATOR

LOAD!
fifO

fifO
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DETECT

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SHORT/LONG
INfO

fiFO

FIFO OUTPUT
ENABLE SIGNAL
REGENERATION

-

SIGNAL
REGENERATION

--+ OUTPUT
231422-95

Figure 53. Retiming Block Diagram

6.1.7 RETIMING CIRCUIT IMPLEMENTATION
The retiming circuit implementation can be seen in Figures 47, 48. Both figures implement exactly the same
function, one for the upstream, and the other for the
downstream. The retiming circuit was implemented using about 8 SSI, MSI TTL components, one fifo chip
and one PAL. The purpose of implementing this function with discrete components was to show the implementation details. The discussion of the implementation will refer to Figure 47 for unit numbers.
The signal UPIMP which is an output of the HUB
JilUltiplexing logic, is asynchronous to the local clock.
This signal is synchronized by two flip-flops and fed
into an edge generation logic (basically an XOR gate
that compares the present sample with the previous
one). On every input transition a 125 ns pulse will be

generated at the output of the edge detector (U28). This
pulse will reset the 74LSI61 counter that is responsible
for measuring pulse widths (in X8 clock increments).
The output of the pulse discriminator will reflect the
previous pulse width every time a new edge is detected.
The following events will take place on every detected
edge:
1. U26 which is the threshold detector will shift one
"I" in. The outputs of U26 will be used by the control PAL to start the reconstruction process.
2. The output of U23 which specifies the last pulse
width will be input into the control PAL for determining if it was a long or short pulse. The result of
this evaluation will be the LSIN signal which will be
loaded into the fifo (U22).
U22 is the retiming FIFO, it is 16x4 fifo, but only one
bit is necessary to store the SHORT/LONG information.

1-130

inter

AP-236

CONTROL LOGIC PAL functions (U25):

Terminal count of the reconstruction
counter, indicating that reconstruction
of a new bit will get started.
Output of the FIFO indicating, that the
FIFO is empty and that IDLE generation can get started.

CNTTC:

Signals definition:
INPUTS:
PDO.. PD3:

THRESH:
CNTEN:

CNTEND:
OUTDAT:

OR:
Outputs of the pulse descriminator, indicate the width of the last measured
pulse.
Output of the edge detector, pulse of 125
ns width, indicates the occurrence of an
edge in the input data.
Output of the threshold logic, indicates
at least one bit was already received.
Output of the Threshold logic, indicates
7 bits have been loaded into the FIFO,
and that signal reconstruction can begin.
The same signal as before delayed by one
clock.
Output of the retiming logic, is feedback
into the PAL to implement a clocked
T-FF.
Resets the retiming logic.

LDFIFO_ = ! ( PDl

PD2

#

#

OUTPUTS:
LDFIFO_:

Loads SHORT/LONG indications into
the FIFO.
Indicates SHORT/LONG
Loads FIFO SHORT/LONG output
into the reconstruction counter.
Together with the external U21 flip-flop
and OUTDAT implement a clocked
T-FF.

ODAT:

Loading the FIFO will be done every time there is an
edge, we have passed the one bit filter threshold level,
and the pulse width is longer than two 8X clocks. This
one bit threshold level serves as a time domain filter
discarding the first received preamble bit.

PD3 )

&:

!EDD_

&:

THRESH ) ;

Whenever there is an edge, we are above the first received bit threshold
and the pulse width is longer than '1" the fifo is loaded.

LSIN

=!

(PD3

(PD2

#

&:

PD~)

#

(PD2

&:

PD1»;

Every pulse longer than 6is considered to be a long pulse.

CNTPE_

=!

( (CNTEN

&:

!CNTEND)

#

CNTTC ) ;

The reconstruction counter is loaded in two conditions:
Whenever CNTEN comes aati ve, meaning the FIFO threshold of seven was exceeded.
Whenever the terminal count of U24 is acti ve meaning a new pulse is going to be reconstructed.

ODAT

= !RESET_

#
#
#

(!CNTPE_
CNTPE_
(!CNTPE_
(

&:
&:
&:

!OUTDAT)
OUTDAT)
lOR)

(A)
(B)

(C)

Minterm (A) and (B) implement a T-FF, whenever CNTPE. is 'low"
ODAT will toggle. The external U21is part of this flip-flop.
Minterm (C) insures the output of the flip-flop will go inactive
'high' when the FIFO is empty. RESET. causes the output to go
"high" on ini tial1zation.

1-131

inter

AP-236

U24 as mentioned is the reconstruction counter. This
counter is loaded by the control logic with either 8 or
12, it counts up and is reloaded on terminal count. Essentially generating at the output nominal length longs
and shorts.

will be started, and Tl will time out after 25 to 50 ms.
T2 will time-out after 51 to lOOms. During T2 time,
after Tl expired, the HUB will send the CP-PATTERN informing any jamming stations to quit their
transmissions. If on T2 time-out there are still jamming
ports, their input is going to be disabled. A disabled
port, will be reenabled whenever its. input becomes
again active and the downward side is idle.

U22 is the retiming FIFO, and its function as mentioned is to accommodate frequency skews between the
incoming and outgoing signal.
U27 is the IDLE generation logic. The purpose of this
logic is to detect when the FIFO is empty, meaning that
no more data needs to be transmitted: On detection of
this event this component will generate 2 ms of IDLE
time. On the end of IDLE the whole retiming logic will
be reset.
6.1.8 DRIVER CIRCUITS

The signal coming out of the RETIMING LOGIC is
fed into 26LS30s and pulse transformers to drive the
twisted pair lines (See section 5,0 for details).
6.1.9 HEADER/INTERMEDIATE HUB SWITCH

As seen on Figure 43 this hub can be configured as
either an intermediate hub, or a Header one. One of the
phone jacks, more specifically JACK #5 is either an
input port or an output one. In order to implement this
function, an 8 position DIP SWITCH (SWI) is used.
The phone jacks are marked with UD, DD notation,
meaning upstream data, and downstream data respectively. As specified in the StarLAN IBASE5 draft
NODES transmit data on UD pair, and HUBS on the
DD pair. Switch SWI has the function to invert UD,
DD in PHONE JACK # 5 to enable it to be either
input or output port.

The following is an explanation of the requirement that
the downward side be idle to reenable an input port.
Consider the case of Figure 54. The figure shows a two
port HUB. Port A has two wires Au, Aci for the up and
down paths. Port B has Bu, Bd respectively. Port C is
the output port, that broadcasts to the other HUBs
higher in the hierarchy. Consider the case as shown,
where Bu and Bd are shorted together. Suppose the case
that port Au is active. Its signal will propagate up in the
hierarchy through Cu and come down from Cd to Ad,
and Bd. Due to the short between Bd and Bu the signal
will start a loop, that will first cause a collision and jam
the network forever. This kind of fault is taken care of
by the jabber circuitry. Tl and T2 will expire, causing
the jabber logic to disable Bu input. Upon this disabling
Bu is going to go Idle and be a candidate for future
enabling. Suppose now that Au is once again active. If
the reenable condition would not require Cd to be
IDLE, Bu would be reenabled causing the same loop to
happen once again. Note that in this case Cd will be
active before Bu causing this port to continue to be
disabled and avoiding the jamming situation (Figure
55) gives a formal specification of the jabber function).

6.1.10 JABBER FUNCTION

This design does not implement the jabber unit but it is
described here for completeness. IEEE 802.3 does not
mandate this feature, but it is "Strongly Recommended". The jabber function in the HUB protects the network from abnormally long transmissions by any node.
Two timers TI, T2 are used by the JABBER function ..
They may be implemented either as local timers (one
for each HUB port) or as global timers shared by all
ports. After detecting an input active, tim~rs 11, T2

1-132

231422-96

Figure 54. Jabber Function

inter

AP-236

Power On

.... Walt for Input active.

____

.:!~~EE ~~TEI!.

___ _

• stort_Jobber TIme 1

.... Input Is active, activate timers Tl, T2 •
If Input goes Idle, then It was a

• start_Jobber TIme 2

normal transmission. Otherwise If

jabber Timer 1 expires, the transmissIon
Is Illegal. Start generating collision
pott.rn In stat. JABBER JAM •
.... Variable probation_alternative indicates
two possible ways of implementing the function.
Implementation of either one Is allowed.
«Jobb.rTlm. Ldon.+ INPUT(UPPER) = Idl.)
.INPUT(X) = ocllv.
'-----;==::;~=~;+~(;pr;o~bo~I:;o::n-~oJternotive * INPUT(X) = idle}

Condilions for going to stat. JABBER SHUTOFF
- 12 expires.
-INPUT(UPPER) = Idl•• INPUT (X) = ocllv.
It maans thot the current HUB was

SHUTOFF by a higher hierarchy one.
This one will olso SHUTOFF with the

purpose that a jamming Input be
DISABLED

-INPUT (X)

at the lowest possible level.

=Idl.

Two alternatives are allowed:

Go bock to JABBER IDLE. or
go to the SHUTOFF stat ••
On slot. JABBER SHUTOFF. th.
Input Is disabled.
Input will be reenabled If input is active,
and the upper port Is quiet.

231422-99

Figure 55. Jabber State Diagram
6.1.11 HUB RECEIVER PROTECTION TIMER

On the end of a transmission, during the transition
from IDLE to high impedance state, the transmitter
will exhibit an undershoot and/or ringing, as a consequence of transformer discharge. This undershoot/
ringing will be transmitted to the receiver which needs
to protect itself from false carriers due to this effect.
One way of implementing this protection mechanism is
to implement a blind timer, which upon IDLE detection will "blind" the receiver for a few microseconds.
Causes of the transmitter undershoot/ringing:
1. Difference in the magnitudes of the differential output voltage between the high and the low output
stages.
2. Waveform assymmetry due to transmitter jitter.
3. Transmitter and receiver inductance (transformer
L).

All the described elements will contribute to energy
storage into the transfonner inductor, which will discharge during the transition of the driver to high impedance.
The blinding timer is currently defined to be from 20 to
30 microseconds for the HUBs, being from 0 to 30 microseconds for the nodes (optional). The 82588 has
built-in this function. It won't receive any frames for an
inter-frame-spacing (IFS) from the idle detection.
6.1.12 HUB RELIABILITY

Since the StarLAN HUBs form focal points in the network, it is important for them to be very reliable, since
they are single points of failure which can affect a number of nodes or can even bring down the whole network. StarLAN !BASES draft requires HUBs to have
a mean time between failures (MTBF) of at least 5
years of continuous operation.

4. Two to three microseconds of IDLE pattern.

1-133

AP-236

7.0 SOFTWARE DRIVER

7.1.1 DOING 1/0 ON IBM PC

The software needed to drive the 82588 in a StarLAN
environment is not different from that needed in a generic CSMA/CD environment. This section goes into
specific procedures used for operations like TRANSMIT, RECEIVE, CONFIGURE, DUMP, ADDRESS
SET-UP, etc. A special treatment will be given to interfacing with the IBM PC-:--DMA, interrupt and I/O.

The safest way to use the PC monitor as an output
device and the keyboard as the input device is to use
them through DOS system calls. The following is a set
of routines which are'handy to do most of the I/O:
key$stat
-to find out if a new key has been
pressed
keyin$noecho -to read a key from the keyboard
-to display a character on the screen
char$out
msg$out
-to display a character string on the
screen
-to read in a character string from the
line$in
keyboard

Since all the routines were written and tried out in
'PLM-86 and ASM-86, all illustrations are in these languages.
The following software examples are pieces of an 82588
exerciser program. This program's main purpose was to
exercise the 82588 functionality and provide the functions of traffic generation and monitoring. By such the
emphasis was on speed and accuracy of statistics gath,
ering. '

The exact semantics and the protocol for doing these
functions through DOS system calls is shown in the
listing in Figure 56. Refer to the DOS Manual for a
more detailed description. To make a DOS system call,
register AH of 8088 is loaded with the call Function
Number and then, a software interrupt (or trap) 21 hex
is executed. Other 8088 registers are used to transfer
any parameters between DOS and the calling program.
The code is written in Assembly language for register
access. Let us see an example of the 'msg$out' routine:

7.1 Interfacing to IBM PC
The StarLAN board interfaces to the CPU, DMA controller and the interrupt controller on the IBM PC system board. The software to operate the 82588 runs on
the system board CPU. The illustrated routines in this
section show exactly how the software interface works
between the system resources on the IBM PC and the
StarLAN board.

lds dX,STRING_POINTER
mov ah,09h
int 21h

load pointer to string in reg. ds:dx
9
function number for string o'p
DOS System Call

=

These procedures are called from another module, written in a higher level language like PLM-86. The parameters
are transferred to the ASM-86 routines on the stack.
Examples of using the I/O routines:

=

KEY_STATUS
key$stat;
NEW_KEY = keyin$noecho;
call line$in(@LINE_BUFFER) ;
call char$out (CHAR_OUT) ;
call msg$out(@('THIS IS A MESSAGE.$'));

"
/*
"
/*
/*
/*

1-134

*'0'
*'*'

INQUIRE KEYBOARD STATUS
INPUT NEW KEY
STRING INPUT
"
TO OUTPUT CHAR_OUT ON SCREEN*,
OUTPUT STRING
NOTE $ TERMINATOR

intJ

AP-236

/ ... -------------- ------ -------------------------- - --- -- -------------------- -_ ... I

Deolara.tions for external IBM PC 110 routines

1*

.. I

/. ------:-- ---------------------------------------------------;--- ------------- ... I

keySstat: prooedure byte external:
end keyS stat :

I

* key status routine • /

::si~;$~~~~~O~~~oedure byte external:
oharSout: prooedure(ohar) external:
deolare ohar byte:
end charS out :

/* oonsole input routine . . I

I' oonsole output routine 'I

msgsout: prooedure(msgSptr) external:
declare msgSptr painter:
end msgSout:

I ' oonsole string output routine

l1neUn: prooedure(lineSptr) external:
deolare l1neSptr pOinter:
end l1neSin:

I ' console string input routine

Assembly Language implementation of the routines
STITLB(IBM/PC

DOS CALLS PROCEDURES)

HAIlE

DOSPROCS

OOROUP
CGROUP

GROUP
GROUP

DATA
DATA

SEGMENT WORD PUBLIC 'DATA'
ENDS

Dos
CoDE

EQU

DATA
CODE

21R

SEGMENT WORD PUBLIC 'CODE'
ASSUME CS: CGROUP, DS : OOROUP

231422-58

CHAR$OUT: PROCEDURE(CHAR) EXTERNAL:
DECLARE CHAR BYTE:
END CHAR$OUT:
Outputs character to the screen.
DOS system call 2
CHAR
CHAROUT

CHAROOT

EQU
PUBLIC
PUSH
MOV
MOV
MOV
INT
POP
RET

[BP+41

PROC
NEAR
CHAROUT
BP
BP,SP
DL,CHAR
AH.2
DOS
BP
2
ENDP

STACK.
+------+

!

CHAR

!

x

+------+
lIP 10 I
+------+

x-1

lIP hi

x-2

!
+------+
IBP 10 !

x-3

+------+

IBP hi I x-4

<--SP

+------+

KEYINSNOECHO: PROCEDURE BYTE EXTERNAL:
END KEYIN$NOECHO:
Reads character withcut echOing to display
KEYINNOECHO PROC
PUBLIC
MOV
INT
RET
KEYINNOECHO ENDP

NEAR

KEYINNOECHO
AH,8
DOS

(DOS call 8)

Figure 7-56. I/O Routines for IBM/PC

Figure 56. 1/0 Routines for IBMIPC

1-135

(continued)

231422-59

intJ

AP-236

IISGSOUT: PROCEDtJRE(IISGSPTR) EXTERNAL;
DECLARE IISGSPTR POllITER;
END IISGSOUT;
/. NOTE: IIESSAG]! IS TERliINATED WITH A DOLLAR SIGN • /
IISGSPTR is double word pOinter SEG:OFFSET
IISG_L
IISG-H.
HSGOUT
PUBLIC
PUSI!
1I0V

IIOV
PUSI!
IIOV
1I0V

IIOV
INT
POP
POP
IISGOUT

RET

-.v

~

[BP+41
[BP+61

PROC
IISGOUT

NEAR

BP
BP,SP
DX,IISGJ.
OS
AX,IISU
DS,AX
AII,9
DOS
'OS
BP

(DOS oall 9)

4

ENDP

LINE SIN : PROCEDURE(LINESPTR) EXTERNAL;
DECLARE LINESPTR POINTER;
END LlNESIN
[BP+41
[BP+61

LlNEIN

PROC
NBAR
PUBLIC· LINEIN
PUSI!
BP
IICV
BP,SP
PUSI!
OS
IICV
AX,LlNE_H
IICV
DS,AX
IICV
DX,LlNEJ.
IIOV
AII,10
INT
DOS
POP
OS
POP
BP
4
RET
ENDP

(DOS oall 10)

231422-60

KEYSSTAT: PROCEDURE BYTB EXTERNAL;
END !tEYS STAT;
Indioates whether any keyboard key was pressed.
!tEYSTAT
PUBLIC

IICV

INT
RET
KEYSTAT

Com

PROC
NEAR
KEYSTAT
AII,l1
DOS

(DOS oall 11)

ENDP

ENDS
END

231422-61

Figure 56. I/O Routines for IBM/PC (Continued)

7.2 Initialization and Declarations
Figure 57 shows some declarations describing what addresses the devices have and also some literals to help
understand the other routines in this section.

Figure 58 shows the initialization routines for the IBM
PC and for the 82588. It also shows some of the typical
values taken by the memory buffers for Configure,
lA_Set, Multicast and transmit buffers.
.

1-136

intJ

AP-236

Following are some literal declarations that are used in the procedure examples
Following are some literal

prooedure examples

deolarations

that

are

used

in

the

deolare

cS_5BB
brd_port
pic_mask
p1c_oow2
dma.Jnask
dm!Lmode
dma31ff
dma_addr_l
dma_bo_l
dm!LaddrJLl
dma_addr_3
dm!Lbo_3
dma_addrh_3
dma_on...l
dmB._oD_3

dm!LofLl
dma_off_3
enable_B8B
seoLp1oo
t~d1r
r~d1r

dma_rx_mode_l
dma_=_mode_3
dm!Ltx_mode_l
dma_tXJ\ode_3

literally '0300h'
/' B25BB COMIIAND/ STATUS
'/
literally '0301h'
/' DIIA/INTERUPT BNABLE PORT
literally '021h'
/' B259A IIASS: REGISTER
literally '02Ch'
/' 8259A COMIIAND WORD 2
literally 'Oab'
/' 8237A IIASS: REGISTER
literally 'Obh'
/' B237A HODE REGISTER
literally 'Och'
/' 8237A 1ST/2ND BYTE FLOP
literally '02h'
/, 8237A ClIANIIEL 1 ADDR. REG.
11 terally '03h'
/' 8237A ClIANIIEL 1 BYTE COUNT
literally '083h'
/' ClIANIIEL 1 PAGE REGISTER
literally '06h'
/' 8237A ClIANIIEL 3 ADDR. REG.
literally '07h'
/' 8237A ClIANIIEL 3 BYTE COUNT
literally '082h'
/' CI!AlINEL 3 PAGE REGISTER
literally 'Olh'
/' START ClIANIIEL 1
literally , 03h '
/' START CIIAlIIIEL 3
literally '05h'
/' STOP ClIANIIEL 1
literally '07h'
/, STOP ClIANIIEL 3
literally 'Odfh'
/' UNIIASS: INTERRUPT LEVEL 5
literally '065h'
/' SPECIFIC EOI LEVEL 5
literally
'1 '
/' MEHORY TO 82588
literally
'0'
/, 825BB TO HEHORY
literally '045h'
/' RlI: ON ClIANIIEL • 1
literally , 047h '
/' RlI: ON CIIAlIIIEL • 3
literally '049h'
/' TX ON ClIANIIEL • 1
literally '04bh'
/' TX ON ClIANIIEL i 3

'/
,/
'/
'/
'/
'/
,/
'/
'/
'/
'/
'/
'/
'/
'/
,/
'/
'/
'/
'/
'/
'/
'/
'/

231422-62

Figure 57. Literal Declarations

Initialization Routines

Initialization routines
/' SYSTEH INITIALIZE '/
sys_1n1t: procedure;
oall set$1nterrupt Cl3,1ntr_58B);
/' BASE B, LEVEL 5
'/
output(p1o_maak) - 1nput(p1o_mask) and enable_B88; /' ENABLE 588 INTERR. '/
output(p1o_oow2) seo1_p1co;
/' ACXS PENDING INTBRR'/
wr_ptr, rd.-ptr, fifoont-O;

/' RESET STATUS FIFO

'/

, •••• *** •••••••••••••••••••••••••••••••••••••••••••• ,
/' CONVERT SEG:OFFSET FORIIAT TO 20 BIT ADDRBSSES
/' FOR ALL THE BUFFERS
/

'/
'/
/

...................................................

1aset_dm!Laddr
cnf_dma_addr
dmp_dm!Laddr
mC_dma_addr
tX_dm!Laddr
do 1-0 to 7 ;

- convert_20b1t_addr (@:l.a_set_bufL5B8(0) ) ;
- conv.ert_20b1t_addr(@Conf:l.g_BB8(0»;
oonvert_20b1t_addr (lIldumpJrufL588 (0» ;
- convert_20b:l.t_addr (@mult:l.oastJrufL5B8(0)) ;
- oonvert_20b1t_addr(@t~ffer_5B8(0» ;

rx_dm!Laddr(1)-oonvert_20b1t_addr(@r~buffer(1)

end;
output (brd_port)-Offh;

.buff(O»;

/' ENABLE DIIA AND INTERRUPT DRIVERS ,/

end ays_1n1 t ;
B25BB initialization
1n1t_588: prooedure:
conf1g_58B(00)
conf1g_588(01)
conf1g_588(02
conf1g_5B8(03)
conf1g_588(04)
oonf1g_58B(05)
oonf1g_58B(06)
conf:l.g_588 (07)
conf:l.g_58B(08)
conf:l.g_588(09)
conf:l.g_58B(l0)
oonf:l.g_588(1l)

- 10;
= 00:
- OOOOlOOOb;
- buff_len/4;
- OOlOOllOb;
- OOOOOOOOb:
- 96;
- 0;
- 1l1lOOlOb;
- OOOOOlOOb;
- 10001000b;
- 64:

/' TO CONFIGURE ALL 10 PARAHBTERS

'/

/'
/'
/'
/'
/,
/'
/,
/'
/'
/'

'/
'/
'/
,/
'/
'/
'/
'/
,/
'/

HODE 0, 8 HBZ CLOClt, 1 HE/S
RECEIVE BUFFER LENGTH
NO LOOPBACX, ADDR LEN - 6, PREAMBLE - 8
DIFFERENTIAL MANCHESTER - OFF
IFS - 96 TCLK
SLOT TIME - 512 TCLK
HAll:. NO. RETRIES - 15
MANCHESTER ENCODING
INTERNAL CRS AND CDT, CRSF - 0
HIN FRAME LENGTH - 64 BYTES - 512 BITS

Figure 58. Initialization Routines

1-137

231422-63

inter

AP-236

1a...set_buff_555(O)
1a...setJlufC588(l)
1a_setj>ufC555(2)
1a_setJluff_585(3)
1a...setJluff_588(4)
1a...setJluff_588(5)
1a...set_uf:C588(6)
1a...setJlufC5BB(7)

-

6;
0;
OOOh
041h
OOOh
OOCh
OOOh
OOOh

mult1oast_bufC5BB(OO)
mult1oastJlufC5BB(Ol)
mult1oastJlufC58B(02)
mult1oastJlufC5BB(03)
mult1oasLbuff.5BB(04)
mult1oastJluff.5BB(OS)
mult1oe.stJlufC55B(06)
mult1oastJlufC5BB(07)
mult1oastJluff.5BB(OB)
mult1oastJluff.5BB(09)
mult1oastJlufC5BB(10)
mult1oastJluff.58B(1l)
mul tioe.stJlufC5BB (lB)
mult1oastJlufCS88(13)

- 12;
- OOh
- llh
- 12h
- 13h
- 14h
- 15h
- 1Bh
- 21h
- 2ah
- 2Sh
-24h;
- 25h;
- Bah;

tzJ>uffer.5BB(OO) - t,,-frame.len mad 256;
tzJ>uffer_5BB(Ol) - t"-frame.len / 256;
;~~~:~=ggm:~
INITIAL DESTINATION ADDRESS - 110(1) ' /
tzJ>uffer_58B(04) - 01Sh;
tzJ>uffer.5BB(05) - 014h;
tzJ>uffer.5B8(06) - 015h;
tzJluffer.588(07) - 016h;

: gm;

/'

. end 1n1 t.5B8;

231422-64

Figure 58. Initialization Routines (Continued)

fourth parameter = pointer to a 20 bit
addre'ss of the
memory buffer
(=@CONFIG.588.ADDR)

7.3 General Commands
Operations like Transmit, Receive, Configure, etc. are
done by a simple sequence of loading the DMA controller with the necessary parameters and then writing
the command to the 82588.

The second statement writes l2h to the command register of the 82588 to execute a Configure command on
channell.

Example: Configure Command

When the command execution is complete (successfully
or not), 82588 interrupts the 8088 CPU through the
8259A, on the system board. This executes the interrupt service routine, described in section 7.5, which
takes the epilogue action for the command.

To configure the operating environment of the 82588.
This command must be the first one to be executed
after a RESET.

oall
DMA.LOAD(1,1,12,@CONFIG.588.ADDR) ;
output (CS.588) = 12h;
The first statement is the prologue to' the configure
command to the 82588 which calls a routine to load
and initialize the DMA controller (or the desired operation. This routine is described in section 7.4. The parameters for DMA_LOAD are:

first parameter = 82588 ohannel
number ( = 1)
seoond parameter = direotion ( = 1,
memory > > 82588)
third parameter = length of DMA
transfer ( = 12)

Most operations are very similar in structure to Configure. The 82588 Reference Manual describes them in
detail. Figure 59 shows a listing of the most commonly
used operations like:

CONFIGURE

INDIVIDUAL·ADDRESS (IA)
SET·UP
TRANSMIT
MULTICAST·ADDRESS (MC)
SET·UP
DIAGNOSE
RECEIVE (RCV)-ENABLE
DUMP
RECEIVE (RCV)-DISABLE
TDR
. RECEIVE (RCV) -STOP
RETRANSMIT
READ-STATUS

1-138

AP·236

1a_set: prooedure publ1o:

/' COl!MAND - 01 ,/

00.11 clmlLload(om(Lohannel, tx_d1r, 8,@1aset_clma_addr) :
/'

SE~

DIIA Cl!AllllEL 0 01\ 1 W TRANSFER FROII IIEIIORY

W THE 82588. 1aset_dma_addr VARIABLE SWRES THE
20

BI~

POINTER W THE INDIVIDUAL ADDRESS BUFFER

'/

if omuffer_5BB(00) • low(buffer_len);
tlLbuffer_5BB(01) • h1gh(buffer_len);
oall dmlLload( Omd.-ohe.nnel, tlLd1r , 1536 ,@tlLdmlLaddr) ;
1£ omd..ohe.nnel then output (OS_8B8) • 14h;
elsa output(os_5B8) • 04h;
end transm1 t ;

231422-65

Figure 59. General Commands

1-139

AP-236

tdr: prooedure publiO;

/" COIIMAND - 05 */

if OlIld_ohannel then output (os_6B8) - lSh;
else output(os_588) - 05h;
end tdr;
/* ---------------------------------------------------------------:--;---------*'

dump_S8B: prooedure publ1o;

'" COIIMAND - 08 "'

oall. dm",--load( amd_ahannel, rZ-dir ,84, Cld.mp_~addr) ;
i f amcLOOannel then output (os_688) - lSh;
else autput(os_588) - OSh;
end dump_S88;

'* --------------------------------..-----------------------------------------*

diagnose: prooedure publ1o;

I

/" COIIMAND - 07 "/

i f OlIld_ohallllel then output (os_588) - 17h;
else output(os_58B) - 07h;

end diagnose;

/ * --------------------------.... ----------------------------------------------rov_enable: procedure (ohannel ,buffer_no ,len) publio;

*'

/" COIIMAND - 08 "/

deolare ohannel ~e;
deolare len word;
deolare buffer~o ~e;
oall dma_load(OOannel, rz_dir,len,iI1'Z-dm",--addr(buffer_no));
;is~~~~~~S~~~) o~t~:; (os_S88) - 18h;

/ * --------------------------------------------------------------------------* /
rev_disable: prooedure publio;

/* COIIMAND - 10 ./

enable_rov-O;
output (os_S88) -OalL;
end rev_disable;

231422-66

/. -------------------------------------------------------------------------- */

rev_stop: prooedure publio;

'" COIIMAND - 11 "/

ene.b18_rcv-O;
output(os_58B)- Ohh;

end rev_stop;

/. ----------------------------------------------------------T--------------- *'
retransmit: prooedure publio;

'" COIlllA1lIl - 12 "'
oall dmaJoad(amd_ohannel, tz_dir, 1538, ct1:z-dm",--addr) ;
i f amcLohannel then output (os_688) - 100; .
. else output(os_58B) - Ooh;

end retransmit;

'*--------------------------------------------------------------------------*'
abort: procedure publio;

'" COIIMAND - 13 "'

:ir:~~~s~:~~;( ~~;
end abort;

'* --------------------------------------------------------------------------*'

reset_SB8: procedure publio;

'" COIIMAND - 14 "'

enable_rev-O;
output(os_SB8) - 1eh;
oall oonfig;
end resat_s88;

231422-67

F.igure 59. General Commands (Continued)

1·140

inter

AP-236

7.4 DMA Routines
DMA_LOAD procedure is used to program the
8237A DMA controller for all the operations requiring
DMA service. It also starts or enables the programmed
DMA channel after programming it. Figure 60 shows

the listing of this procedure. It accepts 4 parameters
from the calling routine to decide the programming
configuration for the 8237A. The parameters for
DMA_LOAD are: Channel; direction, buff_len, and
buff_addr.

Convert1ng a pOinter SEG:OFFSET to a 20 llit address
oonvert_2Dllit_addr: procedure(ptr) dword publio:

deola.re

ptr

po1nter,

ptr_addr

pOinter.

f;~d20~~~e~w~~~_addr) (2)

word:

ptr_addr-@ptr :
ptr_20llit-shl((ptr_20llit :-wrd(l» ,4)+wrd(0):
return(ptr_20ll1t) :
end oonvert_20ll1t_addr:
IBII/PC DIIA loading prooedure
dmB.-lcad: prooedure (ohannel. direction • buff_len .lluff_addr) reentrant publio:
deolare
deolare
deolare
deolare
deolare

channel byte:
direction byte:
bufClen word: .
llufCaddr pcinter:
(wrd llased llufCaddr)(2)

/' CIIANIIEL •• 0 or 1
'/
/' O-RX, 588 -. MEII: lon, IIEII -. BBB ,/
/, BYTE COUNT
'/
/' BUFFER ADDR IN 20 BITS FORM
'/

word;

channel-channel and 1:

/' GET LEAST SIGNIFICANT BIT

'/

if ohannel-O then
do:

/' EXECUTE COIIIIAND ON CIIANIIEL 1

'/

/' CLEAR FIRST/LAST FLIP-FLOP

'/

~~t~;~:~!:6f)

- 0:

then output(dma_mode)-dma_rJUllcde_l: /' DIRECTION BIT, TELLS
else output (dma.Jllcde)-dma_tx--",ode_l :
/' TRANSIlIT OR RECEIVE
cutput(dma_addr_ll - lcw (wrd(O»:
/' LOAD LSB ADDRESS BYTE
cutput(d.ma.-addr_l) - high(wrd(D»:
/, LOAD IISB ADDRESS BYTE
cutput(dmB.-addrlLl) - low (wrd(l»:
/' LOAD PAGE REGISTER
output (dma_llo_l)
- low (buff_len):
/' LOAD LSB BYTE COUNT
cut put (dlna.-llc_l)
- high(bufClen):
/' LOAD IISB BYTE COUNT
cutput(dmB.-mask) - dmB.-on..l:
/' START CllANllBL.l
end:
else do:
/' SAllE AS BEFORE FOR CllANllBL 3

'/

'/
'/
,/
'/
,/
'/
'/
,/

~~t~~;~~o!:6f)

- 0:
then cutput(dma.Jllode)-dmB.-rJUllcde_3:
else cutput(dma_mode)-dma_tx--",ode_3:
cutput(dma_addr_3) - lcw (wrd(O»:
cutput(dma_addr_3) - high(wrd(O)):
cutput(dmB.-addrh_3) - low (wrd(l»:
cutput(dmaJ>c_3)
- low (llufClen):
cut put (dmaJ>c_3)
- high(llufClen):
cutput(dma_mask) - dmB.-cn..3:
end:

end dma...load:

231422-68

Figure 60. DMA Routine

1-141

inter

Ap·236

. One peculiarity about this procedure is that in order to
speed up the DMA step-up, this procedure doesn't get a
pointer to the buffer, but a pointer to a 20 bit address in
the 8237 format. The 8088/8086 architecture define
pointers as 32 bits seg:offset entities, where seg and offset are 16 bit operands. By the other hand the IBM/PC
uses an 8237A and a page register, requiring a memory
address to be a 20 bit entity. The process of converting
a seg:offset pointer to a 20 bit address is time

consuming and could negatively affect the performance
of the 82588 driver software. The decision was to make
the pointer/address conversions during initialization,
considering that the buffers are static in memory (essentially removing this calculation from the real time '
response loops).
Figure 61 is a listing of the DMA-LOAD procedure
for the 80188 or 80188 on-chip DMA controller. It has
the same caller interface as the 8237A based one.

dma_Ioad: procedure(channel ,direction, trans_Ien,'buff_addr) reentrant:
/* To load and start the

80186 DMA controller for the desired operation */

dma_rx~ode
literally '1010001001000000b': /* rx channel */
/* src=IO, dest=M(inc), sync=src, TC" noint, priority, byte */

declare

dma_t~ode
literally '000011010000000b': t* tx, channel */
/* src-M(inc), dest-IO, sync-dest, TC, noint, noprior, byte */

declare

declare
declare
declare
declare

channel byte:
direction byte:
trans_len word:
buff_addr pointer:

'*

/* channel
/*

o -

*/

rx, S88 -> mem: I - tx, mem -> S88 */
/* byte count
*/
/* buffer pointer in 20 bit addr. form
*/

declare (wrd based buff_addr)(2) word:
do case channel and OOOOOOOlbl
do case direction and OOOOOOOlb:
do:
t* channel 0, S88 to memory */
output (dma_O_dpl) =wrd(O):
out put (dma_O_dph) - wrd(l):
output(dma_O_spl) - Ch...A388:
output (dma_O_sph) - 0:
output (dma_O_tc)
- trans_len:
output (dma_O_cw)
- dma.J'~ode or 0006h; /* Start DMA chI
end;
do;
1*
output(dma_O_dpl)
output (dma_O_dph)
ou tpu t (dma_O_spl)
outpu~(dma_O_sph)

'ou tpu t (dma_O_t c)
output (dma_O_cw)
end;
end;

° *1

channel 0, memory to' 588 */
- cl!....,,-S88;

=

0:

- wrd(O);
-wrd(!);
~

trans_len;

-

dma_t~ode

or 0006h: /* Start DMA chI 0 *t
231422-69

Figure 61. 80186 DMA Routines

1-142

inter

AP-236

do case direction and 00000001b;
do;
f* channell 588 to memory *f
output(dma_l_dpl)
wrd(O);'
output (dma_l_dph)
wrd(l);
output(dma_l_spl) = clLb_588;
outputCdma_l_sph) _ 0;
outputCdma_l_tc)
= trans_len;
output (dma_l_cw)
= dma_r~ode or 0006h; f* Start DMA chi 1 *f
end;
do;
f*
output (dma_l_dpl)
output (dma_l_dph)
output(dma_l_spl)
output (dma_l_sph)
ou t pu t (dma_l_t c)
output (dma_l_cw)
end'

end;

channel 1, memory to 588 *f
- clLb_588;

=

o·

- ~d(O);
- wrd(l);
trans_len;
dma_t~ode

or 0006h; f*

Star~

DMA chi 1 *f

.

end;

231422-70

Figure 61. 80186 DMA Routines (Continued)

7.5 Interrupt Routine
The interrupt service routine, 'intr_588', shown in
Figure 62, is invoked whenever the 82588 interrupts.
The main difficulty in designing this interrupt routine
was to speed its performance. Fast status processing
was a basic requirement to be able to handle back to
back frames.

The interrupt handler will read 82588 status, and put
them into a 64 byte long EVENT_FIFO. Those
statuses are going to be used in the main loop for updating screen counters. All the statistics are updated as fast
as possible in the interrupt handler to fulfill the backto-back frame processing requirement.
The interrupt handler is not reentrant, interrupts are
disabled at the beginning and reenabled on exit.

1-143

AP-236

Interrupt service routine
intx_S8e : procedure interrupt 13;

deolare stat
event

byte.
byte,

i
(stO,.tl,st2,st3)
rx_stO
rx_st 1

byte,
byte,
byte.

byte;

/ ' FOLLOWING LITERALS HAVE THE PURPOSE OF ENAllLE ACTING
ON EITHER CHANNEL 1 OR 3 SELECTIVELY

"

declare
literally 'if omd_ohannel
then output(dma_mask)-dma_off_3;
else output(dma._mask)-dma_off_l'.
literally 'if rx_ohannel
then output(dma_mask)""dma_off_3;
else output(dme._mask)-dma._off_l'.

'if cmd_channel
then output(oB_688) .. lCh;
else output(os_5SB)"Ooh·.
'1f cmd_Channel
then output(os_68B)-14h;
else output(os_68B)",,04h';
;, DISABLE INTERRUPTS
*/
/. NO IN'l'ERR. NESTING
*/
I' RLS 68B PTa. START 0 *1

disable;
output(cs_688)

-Ofh:

event_fifo(wr_ptr). atO. stO ... 1nput(os_588):
event_f1fo(wr_ptr). stl. stl-input(os_668);
event_flfo(wr_ptr) . st2, st2-1nput (os_688) ;
event_flfo(wr_ptr). st3, st3 ... 1nput(OS_688);

/'
/'
/'
/'

wr_ptr-(wr_ptr+l) and Ofh;
flfocnt-(flfoont+1) and Ofh:

/' INCREMENT FIFO
/' COUNTERS

'/

event-stO and Ofh;

/' GET EVENT- FIELD

'/

output (os_S88)-80h:

/' ACKNOWLEDGE 82688
/' INTERRUPT

'/

READ 82588 STATUS
REGISTERS, PASSING
THEM TO THE MAIN
PROGRAM ON THE FIFO

'/

'/
,/
,/
'/

'/

231422-71

do oase event;
ev_oo
eV_01
ev_02
eV_03
ev_04

~t op_cmd_dma.;
st op_cmd_dma;
stop_omd_dma:
do:
stop_cmd_dma:

1* NOP COMMAND
I * lA_SETUP, STOP DMA

*I

/' CONFIGURE, STOP DNA
I * MULTICAST. STOP DMA
I' TRANSMIT DONE

'/
*I
*1.

*I

/' CHECK IF THERE WAS A COLLISION AND IS NOT THE
MAX COLLISION

'/

stat-(st2 and lOOOOOOOb) or (stl and OOlOOOOOb):
U (stat-60h)
then do;
I * RETRANSMIT
*I
call dma._load(cmd_channel, tx_d1r, 1536,@tx_dma._addr) ;
1ssue_rtx_cmd ;
,/
I· UPDATE STATISTICS
tota.l_tx_count .. total_tx_count+1 ;
coll_ont(l7) - ooll_ont(17) + 1; I'TOTAL COLLII'I
bzuLtx_oount .. bad._tx_oount + 1;
end;
else do;
i f in_loop
/' EXECUTING TRANSMISSIONS IN LOOP ' /
then do:
/ '" RE ISSUE TRANSMIT COMMAND
*/
oall dma_loadCcmd_ohannel. tX_dlr .1536,@t]cdma_addr
1ssue_tx_cmd:
total_ t::lcoount-total_tx_count+ 1:
end;
U (st2 and OOlOOOOOb) - 0
1* BAD TRANSMIT$o/
then do;
bad_t:lCOOunt .. bad_tx_oount + 1;
/' INCREMENT UNDERRUN COUNTER
'/
tmp-sor( tmp: -st2, 1) :

;~~~iMi~~~i ~iss~bmBR

end;

tmp-scr(tmp,l) :
lost_ots-lost_cts plus 0;
/' INCREMENT LOST CRS COUNTER
tmp-sor(tmp, 1):
lost_ors-lost_crs plus 0;
if (stat-OAOh) /, INC COLLISIONS COUNTER
then ooll_ont(l7) - ooll_ont(17) + 1:
end:

/' INCREMENT DEFER COUNTER
tmp-sol( (tmp: -stl) ,1):
tx_defer-tx_defer plus 0;

end;

'/
'/

'/

'/

231422-72

Figure 62. Interrupt Routine

1-144

inter

AP-236

ev_OS: stop_cmd_dma;
Bv_06: stop_cmd_dma;
ev_07: stop_cmd_dme.;
ev_08:

/.. TDR COMMAND

I

STOP DMA

/, DUMP COI!HANll, STOP DHA
/' DIAGNOSE CHD, STOP DHA
I" RECEIVED FRAME

.. /

'/
' /
.. /

do;
stop_rx_dma;
i-(current_buff+l) and OOOOOlllb; /' INC BUFFER NO. MOD 8'/
if ena.ble_rov<)O
/- IF RECEIVER IS ON
If.j
then do;

/.. PREPARE NEXT BUFFER • /

can dma_load(rx_channel,rx_dir,l632,@1'x_dma_addr(i));
if rJcchannel then output(os_6SS)- 16h:
else output(os_688)-08h;
rX_Duffer(i) .chaln_cnt-O;
end;

else 06011 rov_disable j

/, DISABLE RECEIVER

/, FIND ADDRESS OF END OF CURRENTLY RECEIVED BUFFER
/, BY CALC1lLATING IT WITH THE 82688 BYTE COtlNT REGS.
r,,-bufCoff-(shl(double(st2) ,8) or double(stl));
/' READ STATUS BYTES FROM MEMORY
rx_stO-rx_bufferCcurrent_buff). buf:f'Crx_huff_off-2);
rx_st l-rx_buffer(ourrent_huff) . buffCrx_buff_off-l) ;
/, UPDATE ACTUAL BUFFER SIZE
rx_buffer( current_buff) . actual_size-rx_Duff_Off;
r::Z:_Duffer( current_buff) . etC-rx_sta;
rx_buffer(ourrent_buff). Btl-rx_Btl;
ourrent_huff-1;
/' UPDATB TOTAL RECEIVED BUFFERS

total_rcv _count-total_xcv_oount+ 1 :
/' UPDATE STATISTICS
if (n_stl and OOlOOOOOb)-O

'/
'/
'/
'/

'/

'/
'/

then do;
bad_rov_count-bad_rov_count+l;
/' INCREMENT NO END OF FRAME COUNTER
tmp-scr(tmp: -r,,_stO, 7);

,/

nO_Bof-no_eof plus 0;
/, INCREMBNT

SHORT FRAME COUNTER

tmp-sor( tmp, 1) ;
srt_frm-srt_frm plus 0;

/' INCREMENT RX OVERRUN COUNTER
tmp-scr(tmp:-rx_stl,l) ;

'/

'/

rx_over-rx_over plus 0;-·
/, INCREMENT ALIGNMENT ERROR COUNTER
tmp-sor(tmp, 2);

'/

alg_err-alg_Brr plUS 0;
/, INCREMENT eRC ERROR COUNTER
tmp-scr(tmp,1) ;
orc_err-oro_err plus 0;

'/

end;
end'

ev_09
ev_-10
ev_ll
ev_12

231422-73
/'

BV_09 REQUESTS ASSIGNMBNT OF A NEW BUFFER

'/

call allocate_new_buffer(not(rol(st3,l)) and OOOOOOOlb);
stop_rx_dma;
1* RECEIVE DISABLE
*1
stop_rx_dma;
I" STOP RECEIVE
.. /
do;
/.. RE-TRANSMIT DONE
.. 1
stat-(st2 and lOOOOOOOb) or (stl and OOlOOOOOb);

i f (stat-BOh)

then do:

/.. RETRANSMIT

*1

call dma_load(l, tx_dir,l636,@t,,_dma_addr);

1ssue_rtx_cmd;
colLcnt(l7) - ooll_cnt(l7) + 1;

total_tx_oount-total_tx_oount+1 ;
bad._tx_count-bad_tx_oount +1;
end;
else do:
if in_loop

then do;
1 * LOOP RETRANSMISSIONS
*/
call dma_load( cmd_channel, tx_d.1r, 1536.@tx_dIna_a
1ssue_t~cmd;

total_tx_oount-total_tx_oount+1 ;
end;
i f (stat-OAOh) /' MAX COLLISION

'/

then do;
coll_ont(l6) - ooll_cnt(l6)+l;
oolLcnt(l7) - coll_cnt(l7)+1;·

bad._tx_oount-bad_tx_count +1;
end;
I" UPDATE SPECIFIC COLLISION COUNTER

else

.. 1

coll_ont(stl and Ofh)
- ooll_cnt(stl and Ofh) + 1;

end;

ev_13:

:~::::i~~

end;
stop_cmd_dma;
stop_Omd_dma;

end:
/..

ACKNOWLEIXig 82S9A

/' EXECUTION ABORTED

'/

/' DIAGNOSE FAILED

,/

INTERRUPT

output(pio_ocw2)- seoi_pico;

/, SPECIFIC EOI FOR 8269

end intr_688;

'/
'/

231422-74

Figure 62, Interrupt Routine (Continued)

1-145

Ap·236

. APPENDIX A
STARLAN SIGNALS

1-146

Ap·236

82588

nco

RTS

(1)------

5pF

5 pF

(2)---

24 GAUGE
800 FT TWISTED PAIR WIRE
IN 25 PAIR BUNDLE

(.)~

231422-47
231422-55

Figure 63. StarLAN Signals

1-147

inter

AP-236

Eye Diagram (58ils), DIW Cable
Manchesler Encoded Signal
Transmission Distance ~ 0.8 Kit.
0
0
0
N

0
0

'"
0
0
0

>8
5'"

.",

'"z

0
0..
",0

'"
'"
Q:

(!)

~o
00

>?
0
0
0

.
0
0

'"I
0
0
0
N

I

0.0

0.2

0.4

0.6

O.S

1.0

TIME (~SEC)
231422-48

Figure 64. Received Signal Eye Diagram

1-148.

intJ

A~-236

APPENDIX B
802.3 1BASES MULTI-POINT EXTENSION (MPE)
As previously stated, one of the most important advantages of StarLAN is being able to work on already installed phone wires. This advantage is considerably diminished in Europe where numerous constraints exist
to the using of those wires:

Recently the StarLAN 802.3 !BASES task force has
been considering the extension of the StarLAN base
topology. This extension called MULTI POINT EXTENSION (MPE) is going to be developed to address
the previously described marketing requirements.

I. Wire belongs to local PTTs.
2. Not enough spare wires.

Currently no agreement has been reached by the
StarLAN task force on the MPE exact topology and
implementation. Multiple approaches have been presented, but no consensus met. It was decided though
that the MPE is going to be an addendum to the STAR
topology, and that its final specification will happen
after the approval of the current !BASES STAR topology (July 1986).

This same issue is raised when talking about small businesses where in a lot of cases no wiring closets and/or
spare wires are available.
In summary, in a lot of cases rewiring will be necessary,
in which case the STAR topology may not be the most
economical one.

1-149

__..._ - - THROUGH A HUB UPGRADABLE
TO THE FULL STAR LAN TOPOLOGY
(2500 m. MAX END-TO-END)
HUB COST ELIMINATED
IN SMALL TOPOLOGIES.
LOWER COST PER PORT
(UP TO 8 STATIONS PER PORT)

HUB

l

...
CONNECTION OPTIONAL,
NOT NEEDED FOR SMALL
TOPOLOGIES

"II

cO·
e

...
(II

en

PI

iii:

~
(J1

o

):0
"U
,

e

a:
"0

-~

I\,)
CI)

s·0
::J

en

en
LOWER COST.
TERMINALS ATTRACTIVE

o·

::J

FEWER CONNECTIONS TO
WIRING CLOSETS
231422-97

inter

AP-236

APPENDIX C
SINGLE DMA CHANNEL INTERFACE
In a typical system, the 82588 needs 2 DMA channels
to operate in a manner that no received frames are lost
as discussed in section 5.1.3. If an existing system has
only one DMA channel available, it is still possible to
operate the 82588 in a way that no frames are lost. This
method is recommended only in situations where a second DMA channel is impossible to get.
Figure 66 shows how the 82588 DMA logic is interfaced to one channel of a DMA controller. Two DRQ
lines are ORed and go to the DMA controller DRQ
line and the DACK line from the DMA controller is
connected to DACKO and DACKI of the 82588. The
82588 is configured for multiple buffer reception
(chaining), although the entire frame is received in a
single buffer. Let us assume that channel CH-O is used
as the first channel for reception. After the ENAble
RECeive command, CH-O is dedicated to reception. As
long as no frame is received, the other channel, CH-1,
can be used for executing any commands like transmit,
multicast address, dump, etc., by programming the
DMA channel for the execution command. The status
register should be checked for any ongoing reception,
to avoid issuing an execution command when reception
is active.

OROO
OROl
OACKO .
OACKl
82588

..,

OROn

lished, as shown in Figure 67. After this, the received
bytes start filling up the on-chip FIFO. The 82588 activates the DRQ.line after 15-FIFO LIMIT + 3 bytes
are ready for transfer in the FIFO (about 80 microseconds after the interrupt). The CPU should react to the
interrupt within 80 p.s and disable the DMA controller.
It should also issue an ASSIGN ALTERNATE BUFFER command with INTACK to abort any execution
command that may be active. The FIFO fills up in
about 160 p.s after interrupt. To prevent an underrun,
the CPU must reprogram the DMA controller for
frame reception and re-enable the DMA controller
within 160 p.s after the interrupt (time to receive about
21 bytes). No buffer switching actually takes place, although the 82588 generates request for alternate buffer
every time it has no additional buffer. The CPU must
respond to these interrupts with an ASSIGN ALTERNATE BUFFER command with INTACK. To keep
the CPU overhead to a minimum, the buffer size must
be configured to the maximum value of 1 kbyte.
If a frame transmission starts deferring due to the reception occurring just prior to an issued transmit command, the transmission can start once the link is free
after reception. A maximum of 19 bytes are transmitted
(stored in the FIFO and internal registers) followed by
a jam pattern and then an execution aborted interrupt
occurs. The aborted frame can be transmitted again.
If the transmit command is issued and the 82588 starts
transmitting just prior to receiving a frame then transmit wins over receive-but this will obviously lead to a
collision.

OACKn
OMA
CONTROLLER
231422-49

Figure 66. 82588 Using One DMA Channel

If a frame is received, an interrupt for additional buffer
occurs immediately after an address match is estab-

Note that the interrupt for additional buffer is used to
abort an ongoing execution command and to program
the DMA channel for reception just when a frame is
received. This scheme imposes real time interrupt handling requirements on the CPU and is recommended
only when a second DMA channel is not available.

1-151

intJ

Ap·236

REQUEST
ALT BUFF
INTERRUPT

ASSIGN
ALT BUFF
WITH INTACK

1

82588

~;

1

-.-J

I

I

:':==~~_-_!::B_O_~S_ _ _--;.·II____

,-

1

ADDRESS MATCH
ON FRAME
RECEPTION

1

. DMA CONTROLLER
MUST BE DISABLED
PRIOR TO THIS

rFIFO FULL

•
!::160~S-----+l'1

1

DMA CONTROLLER
MUST BE PROGRAMMED
FOR RECEPTION AND
ENABLED PRIOR TO THIS

231422-50
Figure 67. Timing at the Beginning of Frame Reception for Single DMA Channel Operation

1-152

AP-236

APPENDIX D
MEASURING NETWORK DELAYS WITH THE 82588
Knowing networks round-trip delays in local area networks is an important capability. The round-trip delay
very much defines the slot time parameter which by
itself has a direct relationship to network efficiency and
throughput. Very often the slot-time parameter is not
flexible, due to standards requirements. Whenever it is
flexible, optimization of this number may lead to significant improvement in network performance.
Another possible usage of the network delay knowledge
is in balancing the inter-frame -spacing (IFS) on broadband networks. On those networks, stations nearer to
the HEAD-END hear themselves faster than farther
ones. Effectively having a shorter IFS than stations far
from the HEAD-END. This difference causes an inbalance in network access time for different stations at
different distances from the HEAD-END. Knowing
the STATION/HEAD-END delay allows the user to
reprogram the 82588 IFS accordingly, and by that balance the effective IFS for all the stations.

The 82588 has an internal mechanism that allows the
user to measure this delay in BIT-TIME units. The
method is based on the fact that the 82588 when configured for internal collision detection, requires that the
carrier sense be active within half a slot-time after
transmission has started. If this requirement is not fulfilled the 82588 notifies that a collision has occurred.
Thus it is possible to configure the 82588 to different
slot time values, then transmit a long frame (of at least
half a slot-time). If the transmission succeeds, the network round-trip delay is less than half the programmed
slot-time. If a collision is reported, the delay is longer.
The value of the round-trip delay can be found by repeating this experiment process while scanning the slottime configuration parameter value and searching the
threshold. A binary search algorithm is used for that
purpose. First the slot-time is configured for the maximum (2048 bits) and according if there was a collision
or not, the number changed for the next try. (See Figure 68)

1-153

Ap·236

8
2

5
8
8

TX

PROPAGATION DELAY
HEADEND

RX

• SCHEt.lE IS BASED ON THE F"ACT THAT THE 82588 EXPECTS RX CARRIER
TO BE ACTIVE ArTER 1/2 SLOT TIt.lE

=

K APPROXIt.lATION F"ACTOR

231422-98

Figure 68. Network Delay Measurement using the 82588

1-154

APPLICATION
NOTE

AP-320

November 1988

Using the Intel 82592 to Integrate
a Low-Cost Ethernet Solution
into a PC Motherboard

MICHAEL ANZILOTTI
TECHNICAL MARKETING ENGINEER

Order Number: 290189-001
1-155

AP-320

the LAN solution; e.g., system memory and DMA.
This leaves the 82592, the serial interface, and some
control logic as the only components required to complete a motherboard LAN solution.

1.0 INTRODUCTION
During the past several years office networking has become an increasingly efficient method of resource sharing for companies looking to increase productivity
while reducing cost. Networking allows multiuser access to a data base of files or programs v,ia a network
file server; it allows sharing of expensive peripherals;
e.g., laser printers; and it offers a greater degree of data
security by centralizing the hard disk and backup facilities. This type of network allows a user to concentrate
his resources; e.g., a high-capacity, high-performance
hard disk, at the network file server, allowing the other
nodes, or PC workstations, on the network to function
with limited or no mass data storage capability.

1.1 Objective
This Application Note presents the general concept of
integrating a Local Area Networking into a PC moth- '
erboard, and how the 82592 ,suits this purpose. The
design of the 82592 Embedded LAN Module, which
plugs into an Intel SYP301 motherboard (or any standard PC AT style motherboard), is explained in detail-providing a demonstration of an integrated Ethernet LAN solution.

As I,.ocal Area Networks (LANs) have become more
common in the office and in industry, some clear market development trends have emerged. Possibly the
most significant development in the LAN marketplace
is the concern for cost reduction. This need is driven by
intense competition between network vendors for market share. Today's .LAN marketplace requires low-cost,
simple network solutions that do not sacrifice performance. Another significant development in the LAN
marketplace is the acceptance of Ethernet, or a derivative (e.g.; Cheapernet or Twisted Pair Ethernet), as the
industry standard for high-performance LANs. Because of Ethernet's popularity, there is a great need for
cost 'reduction in this market.

1.2 Acknowledgements
For their contributions to this Application Note, and
for their work in developing the architecture of the
82592 Embedded LAN Module, I would like to acknowledge, and thank, Uri Elzur, Dan Gavish, and
Haim Sadger, of the Intel Israel System Validation
group; and Joe Dragony, of Intel's (Folsom) Data
Communications Focus Group.

2.0 THE EVOLUTION OF LAN
SOLUTION ARCHITECTURES

Personal computers (PCs) have also seen significant
changes over the past several years. PCs have become
firmly entrenched in the office. Their popularity, coupled with a highly competitive market, has compelled
PC vendors to both reduce costs for their LAN solutions and to attempt to distinguish their product from
the competition's. The means of this cost reduction
range from eliminating expensive hardware, such as
disk drives and their associated hardware,. to using
highly integrated VLSI devices that implement the
functions of a PC in a combination chip set containing
several devices. Differentiation has been achieved by
integrating peripheral functions, normally contained on
an external adapter card, into the main processor
board, or motherboard, of the PC. Video Graphics Array (VGA) and LAN connections are examples of this
strategy.
.
The Intel 82592 LAN controller is uniquely suited for
integration into a PC AT style motherboard. It meets
the demands of today's market by providing the PC
vendor (1) a means of reducing cost while maintaining
high performance, and (2) a path for differentiation. An
82592 integrated into a PC motherboard provides a
very low cost and very simple implementation because
,it uses the host system's existing resources to' complete

LAN solutions have undergone an evolution in architecture--from expensive and complex to more cost-efficient and streamlined. A definite trend in office networking can be seen, as these solutions permit the host
system to perform functions that were previously included in the LAN solution.
The first LAN solutions were usually intelligent buffered adapter cards, with a CPU, large memory requirements (up to 512 kB), firmware, a LAN controller, and
a serial interface. As networking became more prevalent in the office environment-linking PCs and workstations via Ethernet-this complex architecture
evolved into simpler and more streamlined nonintelligent, buffered adapters. In this architecture the CPU is
no longer part of t~e LAN solution; its processing power is supplied by the host system. This architecture does
not need memory to support a local CPU. Memory is
only needed to supply a buffer space to store data before moving it to system memory or onto the serial link.
The memory requirement for nonintelligent, buffered
architectures is typically 8 kBytes to 32 kBytes. The
firmware to boot the CPU is also no longer needed. The
evolution to a nonintelligent, buffered architecture has
resulted in significant cost savings and reduced complexity.

1-156

inter

AP-320

Significant increases in speed and processing power
have been made to PCs during the past several years.
This trend to higher performance host systems has allowed further streamlining of the LAN solution's architecture, resulting in even greater cost reduction and
simplification. This is accomplished by using host system resources whenever possible. A nonintelligent, nonbuffered architecture is the result. In this architecture,
the host system's memory and DMA are used by the
LAN controller. The complexity associated with buffered LAN solutions (e.g., supplying a dual-port arbitra-

tion scheme for local memory access by both the CPU
and the LAN controller) is reduced; this complexity is
removed from the LAN solution and returned to the
host system, which is designed for these complex tasks.
The result of this architectural optimization is a very
simple, low component count, cost-efficient solution for
a LAN connection. The 82592 Embedded LAN Module is the realization of this optimization. The trend to
optimization of LAN architectures is shown in Figure
1.

Intelligent Buffered Adapter

EJ

290189-1

Nonintelligent Buffered Adapter
Nonintelligent Non-Buffered Architecture
Embedded Module

290189-3

290189-2

Figure 1. Architectural Optimization of LAN Solutions

1-157

i~

AP-320

3.0 THE 82592 LAN CONTROLLER
3~1

• Internal and externalloopback
• Internal register dump
• A TDR mechanism
• Internal diagnostics

General Features

The 82592 is a second generation, CMOS, advanced
CSMA/CD LAN controller with a l6-bit data path.
Along with 'its 8-bit version, the 82590, it is the followon design to the 82588 LAN controller. The 82592 is
upwards software compatible from the 82588. The
82592 has two modes of serial operation, High Speed
Mode and High Integration Mode. In High Speed
Mode (up to 20 Mb/s) the 82592 couples with the Intel
82C50l to provide an all CMOS kit for IEEE 802.3
Ethernet applications. In this mode the 82592 can also
serve as the controller for Twisted Pair Ethernet (TPE)
applications. In High Integration Mode (up to 4 Mb/s)
the 82592 performs Manchester and NRZI encoding/
decoding, collision detection, transmit clocking, and receive clock recovery on chip; in this mode it can serve
as a controller for StarLAN and other midrange LANs.

For further information on the 82592, please refer to
the Intel Microcommunications Handbook.

3.2 Unique Features for Embedded
LAN Applications
The 82592 has several unique features that enable implementing a high-performance embedded LAN solu,tion with minimal cost and complexity.

The 82592 provides several features that' allow an efficient system interface to a wide variety of Intel microprocessors (e.g., iAPX 188, 186, 286,and 386) and industry standard buses (e.g., the IBM PC I/O channel
or the PS/2™ Micro ChanneI™). To issue a command to the 82592 (e.g., TRANSMIT or CONFIGURE) the CPU only needs to set up a block in memory
that contains the parameters to be transferred to the
82592, program the DMA controller to point to that
location and issue the proper opcode to the 82592. The
82592 and DMA controller perform the functions
needed to complete the command, with the 82592 interrupting the CPU when the command is complete. The
82592 has a high-performance, 16-bit bus interface, operating at up to 16 MHz. It also implements a specialized hardware handshake with industry standard DMA
controllers (e.g., the Intel 8237, 82380, and 82370) or
the Intel 82560. This allows for back-to-back frame reception, and automatic retransmission on collision'without CPU intervention. The 82592 FIFOs (Rx and
Tx) can have their 64 bytes divided into combinations
of 32/32, 16/48, 48/16, or 16/16.
The 82592 features a Deterministic Collision Resolution (DCR) mode. When a collisiori is detected while in
this mode, all nodes in a deterministic network enter
into a time-division-multiplexed algorithm where each
node has its own unique slot in which to transmit. This
ensures that the collision is resolved within a calculated
worst-case time. The 82592 also features a number of
network management and diagnostic capabilities; for
example,
• Monitor mode
• A 24-bit timer

Peripherals on a motherboard must compete for access
to the system bus. Because there is no local buffer for '
intermediate buffering of data, data transfers take place
in real-time over the system bus to the system memory.
A LAN controller must have a large internal data storage area to be able to wait for access to the system bus
while serial data is being received or transmitted. Without sufficient internal data storage, a LAN controller
cannot take advantage of the cost efficiency and simplicity of a non-buffered architecture. The 82592 has a
total of 64 bytes of FIFOs. This expanded FIFO section
allows the 82592 to tolerate long system bus latencies.
For example,' during a Receive (with the Rx FIFO
length configured to 48 bytes) the 82592 can tolerate up
to 38.4 ,""S of bus latency-the time from a DMA request to reception of a DMA Acknowledge from the
DMA controller-before the possibility of a data overrun occurring in a 10 Mb/s Ethernet application. Once
access to the system bus has been obtained, the 82592's
high-performance, l6-bit bus interface provides efficient data transfer over the system bus, thus reducing
the bus utilization load for a LAN connection on the
host system.
The 82592 features a specialiied hardware handshake
with industry standard DMA controllers. This hardware handshake between the 82592 and the DMA controller (on signal lines DRQ and EOP) relays the status
of a Receive or Transmit and allows for back-to-back
frame reception and automatic retransmission on collision without CPU intervention. This allows the 82592
and the DMA controller to perform these time-critical
operations in real-time without depending on the CPU
via an interrupt service routine, and without the time
delays inherent in such routines. For the 82592 Embedded LAN Module, this hardware handshake is enabled
by configuring the 82592 to the Tightly Coupled Interface (TCI) mode. Figure 2 shows details of the 82592's
TCI signals.

• Three l6-bit event counters

1-158

inter

AP-320

Transmit/Receive Status Encoding on ORQ and EOP
ORQ

EOP

0

Hi·Z

Idle

Status Information

1

Hi·Z

DMA Transfer

0

0

Transmission or Reception Terminated OK

1

0

Transmission or Reception Aborted

Tightly Coupled Interface Timings

DRQO,
DRQl
DACKO,
DACKl

~

'\.

'\.

--T23

-

T1D4

--I

§~

wR,Rfi

EOP
..... T1DS

Symbol

Parameter

I-

I2901e~-4

Max

Units

45

ns

CL = 50 pF

65

ns

CL = 50 pF

WR or RD Low to EOP Active

45

ns

Open Drain 1/0 Pin

EOP Float after DACKO
or DACK1 Inactive

40

ns

Open Drain 1/0 Pin

t23

WR or RD Low to DRQO
or DRQ1 Inactive

tl04

WR or RD High to DRQO
or DRQ1 Inactive

t105
t106

Min

..... T1DS

2.5

Figure 2. TCI Encoding and Timings

1·159

Notes

intJ

AP-320

These three features (FIFO depth, high-performance
bus interface, and TCI) allow the 82592 to operate successfully in a high-performance motherboard LAN
application. The application of these features will be
discussed further in Section 4.

schematics. The module consists of an 82592, two
20LIO PALs, and two 8-bit LS573 address latches that
combine to provide a 16-bit address latch. The module
contains no DMA unit or local memory.
The 82592 Embedded LAN Module is a simple; lowcost, low component count solution because it uses the
available system resources (DMA and memory) to provide for those functions normally added to a LAN solution. Removing DMA and local memory from a LAN
solution reduces cost and, complexity. Two host DMA
channels, one for receive and one for transmit, are
needed to support the module. The DMA interface
from the 82592 (through PAL B) is the standard combination ofDRQ, DACK and EOP. These three signals
also provide the TCI between the 82592 and the DMA
controller. The size of the memory buffer needed to
support the module depends'on the specific application
and the amount of free memory available; the buffer
size can be specified by the programmer.

4.0 SYP301 INTERFACE
This section will discuss the details of the Interface of
the 82592 Embedded LAN Module to the Intel
SYP301. The basic architecture will be presented, demonstrating that the 82592 Embedded LAN Module is a
low-cost, low component count Ethernet solution for
networking office PCs or .workstations.
The Intel SYP301 is compatible with the IBM PC
ATTM. It features an Intel 80386TM microprocessor,
running at 16 MHz, as its CPU. Its system bus is compatible with the standard PC AT I/O-channel bus.

4.1 Basic Architecture
Figure 3 shows the basic architecture of the 82592 Embedded LAN Module, and Figure 4 shows the module's

JI

ADDRESS BUS AO-15

,

LATCH

"
DATA BUS 00-15

LTCwt
DRQO
DRQl
DACK
EOP
INT

+

JI

(RECEIVE)
(TRANSMIT)
(BOTH CHANNELS)

DMA INTERfACE

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I~
cs

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INTRQ

....

lORD

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ADDRESS BUS AO-2 A5-9
PAL A
lORD

82592

"

OE

"

..

..

IOWR

lORD
IOWR

lolA BUS 00-15"
I'

290189-5

Figure 3. 82592 Embedded LAN Module Basic Architecture

1-160

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82592

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290189-48

N
0

inter

Ap·320

The two PALs (PAL A and B) provide two major junctions for the module: (1) address decode (PAL A), and
(2) interpreting the TCI from the 82592 (PAL B). PAL
A decodes addresses for CS to the 82592, OE for the
address latches, and an Enable/Disable of the LAN
module. PAL B interprets the TCI of the 82592. When
PAL B detects EOP from the 82592 during reception of
a frame (BOP indicates the last byte of the receive
frame) it loads the memory address of the last byte of

the receive frame (the byte count) into the Address
Latch at the time it is written into memory. This allows
back-to-back frame reception without CPU intervention, and will be covered in detail in Section 4.2. For
Auto-Retransmit on collision, PAL B passes the EOP
signal from the 82592 to the DMA controller, reinitializing the DMA controller for retransmission. This process will be discussed in more detail in Section 4.3. Both
sets of PAL equations are listed in Table 1.

Table 1. PAL Equations
PAL20L 10 MMI-PAL A (Version 1.1)

AEN A2 RESET NC AO IOWBAR A5 A6 A7 AS A9 GND IORBAR 501LB Al 59CTS OE2BAR
OE1BAR LANRSTBAR NC NC ENLANBAR 592CSOBAR VCC

=592CTS
592CSOBAR =AEN •
OE2BAR =AEN • A9
OE1BAR =AEN • A9

IF (VCC) 501LB
IF (VCC)
IF (VCC)
IF (VCC)

IF (VCC) 1ANRSTBAR
IF (VCC) ENLANBAR

A9 • AS • A7 • A6 • A5·. A2 • Al • AO • ENLANBAR
• AS • A7 • AS • 'A5 • A2 • Al • AO • IORBAR • ENLANBAR
• AS • A7 • AS • A5 • A2 •. Al • AO • IORBAR • ENLANBAR

=!EN
• A9 • AS • A7 • A6 • A5 • A2 • Al • AO •
ENLANBAR

IOWBAR •

=LANRSTBAR •

ENLANBAR + AEN • A9 • AS • A7 • A6 • A5 • A2 • Al
• AO • IOWBAR

PAL20L 10 MMI-PAL B (Version 1.1)

592DRQO RESET DACK7BAR DACKSBAR lORBAR 592DRQl 592EOPBAR ENLANBAR AEN NC
IOWBAR GND 592INT NC DRQSBAR DRQ7 DRQS DISDACK IRQ10 NC MSEOPBAR LTCW
.
592DACKBAR VCC
IF (VCC) LTCW = IORBAR + 592EOPBAR + DACK7BAR
IF (ENLANBAR • 592EOPBAR • DACKSBAR) MSEOPBAR
IF (VCC) 592DACKBAR
IF (VCC) DISDACK
IF (VCC) DRQ7 =
IF (VCC) DRQSBAR
IF (VCC) i5RQ6
IF (ENLANBAR)

=DACKSBAR •

= IOWRBAR •

=592EOPBAR •

DACKSBAR

DISDACK • ENLANBAR + DACK7BAR • ENLANBAR

DISDACK • RESET + 592DRQO • DISDACK • RESET

+ 592DRQO • IOWRBAR ~

RESET

592DRQl + 592EOPBAR • DACK7BAR

=592DRQO

• RESET + DACK6BAR • DRQSBAR • RESET

=DRQSBAR
IRQ10 =592INT

NOTE:
The suffix BAR added to the above signal names indicates an active low signal. A signal in these equations' with a line
drawn above it indicates this Signal is to be in a low state for the equation.

1-162

intJ

Ap·320

4.2 Back-to-Back Frame Reception

TCI signals of the 82592 (PAL B loads the address
latch with the address of the last byte of the received
frame) and the structure of the received frame transferred from the 82592 to memory. Figure 5 shows the
format of an 82592 receive frame in TCI mode. After
the information fields are written to memory, the Status
and byte count of the received frame are appended to
the frame in memory. These four bytes (two bytes of
Status and two bytes of byte count) are the last four
bytes of the receive frame written to memory. The high
byte of the byte count is the last byte transferred from
the 82592 to memory. As this last byte is transferred to
memory, the 82592 asserts the EOP signal. When PAL
B detects the assertion of EOP by the 82592, it loads
the address of the last byte of the receive frame into the
Address Latch as this byte is written into memory. This
action ensures that there will always be a pointer (the
contents of the Address Latch) to the byte count of the
last frame stored in the RFA buffer in system memory.
Based on the value of the byte count, the beginning
address of the receive frame in memory can be calculated; i.e., Byte Count Address Pointer - Byte Count =
Beginning of Frame. The byte count of a previous receive frame would reside one address location before
the first byte of the current receive frame. That frame,
and any additional receive frames that may have preceded it, can have their start addresses recovered by the
same calculation used to recover the last frame received. This process allows frames to be continually
stored in the RFA buffer without CPU intervention,
and to be recovered by the CPU for processing. Figure
6 illustrates the process of back-to-back frame reception.

The architecture of the 82592 Embedded LAN Module
allows it to receive back-to-back frames without CPU
intervention. It uses a contiguous Receive Frame Area
(RFA) buffer in host system memory where receive
frames can be continuously stored. This sequential storage of receive frames can continue until the buffer space
is exhausted. The size of the RFA buffer can be specified by the programmer. Its size will be programmed as
the byte count of the Rx DMA channel. The Base Address Register contents of that channel serve as the
start address of the RFA buffer. The receive frames will
be stored sequentially in the RFA buffer based on the
contents of the Current Address Register of the Rx
DMA channel. The module's architecture, and the
82592 receive frame memory structure, allows the CPU
to recover the addresses of each Receive frame in memory for processing. The CPU can also reinitialize the
RFA buffer (by reinitializing the Rx DMA channel) as
the RFA buffer fills up and its contents are processed.
Alternatively, configuring the Rx DMA channel to
Auto-Initialize mode will allow the Rx buffer to automatically wrap around, back to the beginning of the
buffer, when its end is reached. This creates a virtual
"en'dless" circular buffer. When using this approach,
care must be taken to avoid writing over unprocessed
Rx frames-either by the addition of a hardware Stop
Register, or by guaranteeing that the Rx frames can be
processed faster than the buffer can wrap around.
Back-to-back frame reception without CPU intervention-and eventual recovery of the frames for processing by the CPU-is based on PAL B's decoding of the
14

15

12

13

11

10

9

8

7

5

6

DESTINATION ADDRESS SECOND BYTE

4

o

2

3

DESTINATION ADDRESS FIRST BYTE

DESTINATION ADDRESS LAST BYTE
SOURCE ADDRESS FIRST BYTE

SOURCE ADDRESS SECOND BYTE

I
SOURCE ADDRESS, LAST BYTE
INFORMATION (LENGTH FIELD, HIGH)

I

I

I

INFORMATION (LENGTH FIELD, LOW)

I

.I

I

I

I

I

~

INFORMATION LAST BYTE
CRC BYTE o·

CRCBYTE l '
CRC BYTE 3'

CRC BYTE 2'

X

X

X

X

X

X

X

X

SHORT
FRAME

X

X

X

X

X

X

X

X

0

X

X

X

X

X

X

X

X

NO
EOF

TOO
LONG

1

NO
SFD

NOADD
MATCH

I·A
MATCH

Rx
CLD

0

Rx
OK

LEN
ERR

CRC
ERROR

ALG
ERROR

0

OVER
RUN

BYTE COUNT LOW

X
BYTE COUNT HIGH
X
X
X
X
X
X
X
'The CRC bytes are transferred to memory only when the deVice IS so configured

Figure 5. Receive Format for the 82592 in 16·Bit Mode (Tightly Coupled Interface Enabled)

1-163

i~

AP-320

Example No.1

Example No.2

First Frame
Received

Second Frame
Received

I Rev

Rev

Frame AreaIn Host Memory

In

I

1--+

Frame Area

~ost

RCV Frame Area

Memory

In Host Memory

Frome 1

Frame 1

Latch

Example No.3
nth Frame
Received

Frame 1

Status

Status

Slalus

Byte Count

Byte 'Count

Byte Count

Remainder of

Frame 2

Additional
RCV Frames

RFA Buffer

290189-6

Frame n

Slatus

I

Latch

1-----+

I

Byte Count
Status

Remainder of
RFA Buffor

r

Latch

J-----.

290189-7

Byte Count
Remainder of

RFA Buffor

290189-8

NOTES:

'

The 82592 a'ppends the byte count to the'end of each RCV frame.
PAL 'B' loads the latch with the memory address of the last byte of each RCV frame.
Based on latch contents and the byte count of each frame, the CPU recovers the RCV frames.

Figure 6. Back-to-Back Frame Reception

4.3 Automatic Retransmission on
Collision
Automatic 'retransmission on collision detection is ac·
complished by the T<;!I between the 82592 and the host
8237 OMA controller and requires no CPU interven·
tion. The transmit channel of the 8237 should be configured for Auto·Initialize mode. The transmit block
(data to be transmitted) starts at the location pointed to
by the Base Address Register of the Tx OMA channel.
Ouring a Transmit command, the 82592 riMA requests begin at the start of the transmit block and work
sequentially through the block (by incrementing the
contents of the 8237's Current Address Register) until
the transmission is complete. Should a collision occur,
the 82592 asserts the EOP signal and ORQ' to the
8237 (these signals pass through PAL B) causing the
8237 to auto-initialize back, to the beginning of the
transmit block (the Current Address Register is loaded
with the value in the Base Address Register). Internal-

ly, the 82592 generates a Retransmit command and begins making DMA requests to the 8237, which is now
pointing to the beginning of the transmit block. The
82592 also enters into a back-off algorithm (counting to
a random number to resolve the collision). When the
back-off algorithm is complete, and the 82592 regains
access to the serial link, retransmission is attempted.
The 82592 will repeat this process until the retransinission is completed successfully or until the maximum
allowable number of collisions per Transmit command
is reached-at that point all retransmit attempts stop.
No CPU involvement is required to carry out a retransmission. The process of automatic retransmission is
shown in Figure 7.
NOTE:
"For Auto-Initialization of the S237, the signal ORQ
must be asserted to'the 8237 along with assertion of
EOP. With the 82380 and 82370 OMA controllers,
Auto-Initialization can be triggered by asserting the
EOP signal alone.

1-164

AP-320

Prior to Transmission
BAR = CAR
Transmit DMA Channel In
Auto-Initialize Mode

During Transmission
CAR Increments

BAR/CAR~

BAR ~ , - - - - - - - - ,
Transmit
Buffer in
System
Memory

CAR~

Collision:
82592 EOP Asserted to 8237
CAR Reset to BAR
(by 8237's Auto-Initialize)
BAR/CAR ---+
Transmit
Buffer in
System
Memory

Transmit
Buffer in
System
Memory

After Back Off the 82592
Retransmits from Beginning of
Transmit Buffer.
No CPU Intervention is
Required for Retransmission

BAR = Base Address Register
CAR = Current Address Register

Figure 7. Automatic Retransmission on Collision

4.4 Target Systems for Integration
The 82592 Embedded LAN Module is designed to be
implemented on an Intel SYP301 motherboard; thereby
demonstrating a low-cost LAN connection for a workstation. The SYP301 has an IBM PC AT style bus architecture with a 32-bit Intel 80386 as the main processor. The interface between the 82592 LAN Module and
the SYP301 is based on standard interface signals
(DRQ, DACK, EOP, IRQ, lOR, lOW, etc.) so the
basic architecture of the module can be implemented on
PC AT based systems. This design has been successfully tested in PC AT style systems produced by several
manufacturers. For some PC;:: AT based systems, and
PS/2 Micro Channel systems, the module's design may
require some modification. IBM PC and PC XT based
systems do not have sufficient DMA bandwidth to support the non-buffered architecture of this module.
4.4.1 PC AT BASED DESIGNS

High-integration chip sets replace a large number of
discrete. VLSI, LSI, and TTL components with several
integrated VLSI devices that duplicate a large portion
of the PC's functionality. PC AT compatible systems
using such chip sets may lack support for the automat~c
retransmission feature of the 82592 LAN Module. ThIs
is because many manufacturers of such chip sets have
integrated the EOP function but e~iminated th.e .~O~
input. This lack of an EOP input dIsables auto-Initialization of the DMA controller for retransmission. In

this case retransmission can be performed in one of two
ways.
• Should a collision occur while transmitting the preamble, the 82592 (when configured to automatic r~­
transmission mode) will automatically retransmIt
without CPU intervention or auto-initialization of
the DMA. This is effective for shorter network topologies where collisions are normally detected early in the frame.
• Should a collision occur after the preamble, the
82592 will interrupt the CPU and the CPU will initiate the retransmission.
For a PC AT style architecture, logic must be implemented to accommodate DRAM refresh. DRAM refresh cycles typically occur at 15 ,...S intervals. In a standard PC AT, any DMA user should limit the time of a
DMA burst to 15 J-LS; this is to ensure that the system
bus is free for the refresh to take place. Any designer
using burst mode DMA must consider this requirement
when implementing a design.
4.4.2 PS/2 MICRO CHANNEL ARCHITECTURE
DESIGNS

The IBM PS/2 and other compatibles using the Micro
Channel architecture have a different host interface to
the 82592 Embedded LAN Module; however, the basic
architecture of the module is still applicable. As in the
SYP301 solution, the TCI between the 82592 and a

1-165

inter

AP-320

control PAL loads the address latch with a pointer to
the last receive frame. Based on the contents of the'
latch and the 82592 receive memory structure, the
frames are recovered for prpcessing by the CPU. The
differences between a PC AT architecture and a Micro
Channel architecture require different control signal
decoding. The Micro Channel requires a 24-bit address
latch, as opposed to a 16-bit latch in the 301, and to
acquire the system DMA it requires different arbitration logic to drive a 4-bit arbitration level on the Micro
Channel. The Micro' Channel also does not have an
EOP input; therefore, auto-initialization of the Tx
DMA channel and support of automatic retransmission
without CPU intervention must be provided by using
one of the alternative methods recommended in the
previous section.
4.4.3 EMBEDDED CONTROL DESIGNS

The 82592 Embedded LAN Module architecture can
also be applied to an embedded control application that
contains some DMA functions. For an embedded application using an 8237, 82380 or 82370 DMA controller,
the. basic architecture of the 82592 Embedded LAN
Module can be used. For an interface to DMA devices
that do not feature the EOP signal 'as an input (for
example, DMA units on board a CPU), the alternative
methods for retransmission given earlier can be used.

5.0

SERIAL INTERFACE MODULE

The serial interface for the Intel SYP301 82592 Embedded LAN Module is implemented as a separate module.
Since the 82592 Embedded LAN Module is intended to
be integrated into a system motherboard, implementing
the serial interface as a separate module-perhaps as a
very small PC board that plugs into a 'socket-allows
for easy interchangeability b\'tween different serial interface media. This modularity allows the system board
manufacturer to avoid committing his motherboard to
only one type of medium, and thus requiring a major
.redesign for each different serial interface..
Modularity in the data communications field is encouraged by the Open Systems Interconnect (OSI) ref~rence
model. The 82592 is designed to operate through the
lower half of the Data Link Layer (see Figure 8), implementing CSMA/CD Medium Access Control and interfacing directly with the Physical layer below it. By
interfacing the 82592's standard CSMA/CD interface
signals~a serial module (TxD, RxD, TxC, RxC,
CDT, CRS, and others) different Physical Link modules can be implemented without any change to software. Examples of serial interface modules that could
. be interchanged by simply plugging a new module into
the motherboard are Ethernet/Cheapernet, Twisted
Pair Ethernet (TPE), StarLAN, Broadband Ethernet,
and many proprietary CSMA serial media. Figure 9
shows the schematics of an Ethernet module; and Figure 10 those of an .EthernetiCheapernet module.

OSI
Reference Model Layer.

7

Application

6

Presentation

5

Session

4

Transport

3

Network

2

Data Link
Physical

"

,"
,,

......

,

"

"

LLC
Logical Link Control

2.-------~------~
MAC

....
.... ....

Medium Access Control

PLS
Physical Signaling

290189-10

Figure 8. The 82592 Embedded LAN Module Relationship to the OSI Reference Model

1-166

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290189-47

inter

AP-320

6.0 PERFORMANCE COMPARISON

7.0 SOFTWARE EXAMPLES

Figure II compares the performance of the 82592 Embedded LAN Module with the PC586E nonintelligent,
buffered adapter. The PC586E is an 'Intel evaluation
board based on the Intel 82586 LAN Coprocessor. It
contains 16 kB of local memory, has a 16-bit bus interface, and has a high-performance arbitration scheme
providing both the CPU and the 82586 LAN controller
zero wait state access to local memory. The PC586 has
been characterized in the industry as one of the highest
performance nonintelligent, buffered adapters available.

The following examples are from a driver written for an
82592 Embedded LAN Module operating in an Intel
SYP301. The driver was written by Joe Dragony, Intel
Data Communications Technical Marketing Engineer.
The excerpts will cover (I) declarations of program
constants and variables, (2) initializing the Embedded
LAN Module hardware and buffer space, (3) assembly
and transmission of a frame, and (4) processing received frames. A brief description of each of these processes is followed by excerpts from the code. The driver
uses the Xerox Internetwork Packet Exchange (IPX)
protocol and serves as a software interface between the
82592 Embedded LAN Module hardware and the IPX.

A perfornlance comparison, using Novell's Perform 2
utility, shows that the 82592 Embedded LAN Module,
operating as a workstation accessing a file server, outperforms the PC586E. For all tests the host system was
an Intel SYP301. The SYP301 was run in both standard mode, a nominal 16 MHz", and in its reduced
speed mode, 6 MHz. In all cases the SYP301 system
DMA operates at 4 clocks per cycle at 4 MHz. The file
server was a Novell 286A, an 8 MHz, zero wait state
system, using a PC586E as the LAN adapter. The tests
recorded are for one node on the network (the worksta, tion under test). For write tests to the file server's hard
disk, the performance numbers are generally the same.
This is due to limitations in accessing the, file server's
hard disk. This slow access causes a bottleneck. For the
read tests the workstations are accessing files stored in
cache memory, thus removing 'the bottleneck for this
test. Without this limitation, the 82592 Embedded
LAN Module accesses the file server at a higher rate
than the PC586E: at full speed, 318 kB/s vs
282.3 kB/s; and at reduced speed, 202.8 kB/s vs
195.2 kB/s.

Exerciser Software for the 82592 Embedded LAN
Module is also available from Intel. Detailed documentation for both the exerciser program and the network
driver are available upon request from Intel.

7.1 Declarations
Table 2 shows declarations of program variables and
equates of program constants. This section is included
to help the reader understand the following program
excerpts.
"NOTE:
The benchmark program Landmark CPU Speed Test,
@ 1986 by Landmark Software, shows an effective
throughput of 14.3 MHz for a SYP301 in standard
mode; and 5.4 MHz in reduced speed mode.

•

Standard
Write

~

Standard

III

Reduced

Write

~

Reduced
Read

Read

Kilobytes per Second
290189-11

NOTES:
Novell Perform 2 Version 2.3
File Server: '2B6A. B MHz, Zero-Wait-State with PC5B6E LAN Adapter
Node System: SYP301 (One Node on Network)
Reduced Speed Mode: Equivalent to 5.4 MHz AT
Standard Mode: Equivalent to 14.3 MHz AT
301 System DMA: 4 MHz, Four Clocks per Transfer

Figure 11_ 82592 SYP301 Embedded LAN Module vs PC586E Buffered Adapter

1-169

inter

Ap·320

Table 2. Declarations
$'*define(slow) local label
jmp
short 'label
Habel:
)

%*define(fastcopy) local label (
shr cx, 1
rep movsw
jnc Habel
movsb
,iabel:
)

'*define(inc32 m) (
add word ptr %m[D], 1
adc word ptr 'm[2], 0
name

LANOnMotherboardModule

CGroup

group

asswne
Code

cs: CGroup, ds: CGroup

segment word public 'CODE'

public
public
public

DriverSendPacket
DriverBroadcastPacket
DriverPoll

public

LANOptionName

extrn
extrn
extrn
extrn

rpXGetECB: NEAR
rpXReturnECB: NEAR
rpXReceivePacket: NEAR
rpXReceivePacketEnabled: NEAR
l;PXHoldEvent: NEAR
rpXServiceEvents: NEAR
rpXrntervalMarker: word
MaxPhysPacketSize: word
ReadWriteCycles: byte
rpXStartCriticalSection: NEAR
rPXEndCriticalSection: NEAR

extrn

extrn
extrn
extrn

extrn
extrn
extrn

290189-16

1-170

intJ

AP-320

Table 2. Declarations (Continued)
:;;;;;; i;;;;;;:;;;;;

E'!'1ates
....................
.. " " " " " " "

,."

CR
LF
BAD

BPORT
lRQLOC
DMAOLOC
DMA6LOC
TransmitHardwareFailure
PackstUnDalivarable
PacketOvertlow
ECBProcessing
'l"xTimaOutTicks

e'!'1
e'!'1
a'!'1
e'!'1
e'!'1
8'!'1
8'!'1
a'!'1
a'!'1
a'!'1
s'!'1
s'!'1

ODh
OAh
OFFh
0
19
23
2S
OFFh
OFEh
OFDh
OFAh
20

Latch definitions
'l"anC&ntLo
a'!'1 301h
'l"enCentHi
e'!'1 302h
Enablas for 10cent
EnLAN
B'!'1 303h
Dis LAN
e'!'1 304h
8259

definitions

lnterruptControlPort
lnterruptHaskPort

e'!'1
e'!'1

ExtraInterruptContro1Port

equ

EOl

e'!'1

020h
OAlh
OACh
020h

;for sacondary S2S9A

8237 definitions
DMAc:lDdstat
DMAraq
DMASnglmsk
DMAmode
DHAff
DMAtmpclr
DMAclrmak
DMASllmsk
DMA6paga
DMA6addr
DMA6wdcount
DMA7pags
DMA7addr
DMA7 ..dcount
DMAtx6
DMAt,,7
DMArx6

DHArx7
DMA6m.sk
DMA6unmsk
DHA7mak
DMA7unmak
DMAena

S'!'1
a'!'1
a'!'1
s'!'1
a'!'1
s'!'1
s'!'1
s'!'1
e'!'1
s'!'1
s'!'1
s'!'1
s'!'1
e'!'1
e'!'1
a'!'1
e'!'1
e'!'1
e'!'1
a'!'1
B'!'1
a'!'1
e'!'1

ODOh
OD2h
OD4h
OD6h
ODSh
ODAh
ODCh
ODEh
089h
OCSh
OCAh
OSAh
OCCh
OCEh
01Ah
01Bh
006h
007h
006h
002h
007h
003h
Oh

demand mode, autoinit, read transfer
demand moda, autoinit, read transfer
demand mode, no autoinit, writQ transfer

demand mode, no autoinit, write transfer

290189-17

1-171

AP-320

Table 2. Declarations (Continued)
NetWareType

equ

llllh

: 82592 COlIU1Iands
C NOP
C-SWPl
C-SELRS"l"
C-SWPO
C-IASET
C-CONl!":IG
C-KCSE"l"
C-TX
C-TOR
C-OtlMl?
C-OIAG
C-RXENB
C-ALTBUF
C-RXDISB
C-STPRX
C-RETX
C-ABORT
C-RST
C-RLSPTR
C-F:IXPTR
·C:INTACK

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

OOh
10h
OFh
Olh
Olh
02h
03h
04h
05h
l6h
07h
l8h
09h
lAb

lBh
OCh
OOh
OEh
OFh
lFh
BOh

..............................

"""""""""""""""
Data Structures
...............................
"",
""""""""""."

even

..

hardware structure
io addrl
io:range1
.i.o addr2
decode_range2
IDem addrl
mem:rangel
mem addr2
_:range2
int usedl
int-linel
int-used2

int-line2
dma-usedl
dma-chanl
dma-used2
dma-chan2
hardware_structure

struc
dOl
?
dOl
dOl
?
dw
?
dOl
?
dw
dw
dw
?
db
db
db
db
db
db
db
db

?
?
?
?
?
?

ends

ecb structure
struc
-link
esr address
in use
coiiipletion_code

dd
dd

0

db
db

0
0

0
290189-18

1-172

intJ

Ap·320

Table 2. Declarations (Continued)
socket nWllber
ip,,_workspace
driver_workspace
immediate address
fragment count
fragment:descriptor_list
eob_structure
ends
fragment_descriptor
fragment_address
fragment_length
fragment_descriptor
:r:x buf stz:uctUl:ti

dw
db
db
db
dw
db

0

4
12
6

(0)
(0)
(0)

1
6

dup (7)

struc
dd
7
dw
?
ends

struc

- rx-dest addr
rz-source adelr

db
db

dup (7)
dup (7)

r,,:physical_length
rx checksum
r":length

dw
dw
dw

rx tran control
r",:hdr_type
rx. deat net
r,,-dest-node
rx-dest-socket
rZ-SQurce net

db
db
db
db

7
7
7
7
7
4 dup (7)
6 dup (7)

dw
db
db

rx-source-node

rx-source-socket
dw
rX_buf:structure
ends

tci status
-status 0
deadl
status 1
dead2
bc 10
de&"d3
bc hi
tCi_st&"tus

dup
dup
dup

4 dup (7)
6 dup (7)
7

struc
db
db
db
db
db
db
db

7
7
7

ends

ip,,_header_structure
struc
checksum
dw
?
packet_length
dw
7
transport_control
7
db
packet_type
db
7
destination network db
4 dup (7)
destination-node
db
6 dup (7)
destination-socket
dw
7
aQuJ:'ce network
4 dup (7)
db
source-node
db
6 dup (?)
source-socket
dw
ipx_header:structure
ends
iii;;;;;;;:;:;;;;;:;;;;;;;

Variables
iii;:;;;;::;;;:::::;:;;;;;

even

290189-19

1-173

intJ

AP-320

Table 2. Declarations (Continued)
tz atart t1Dla
adapte,,_To
confiq
aend list
buffer_segment
tx:ecb

dv
dw
dv
dd
dv
dd
dd

confiq block

db

rx acb

0
?
?

;points to liat of ECBs to be sent

0
?
?

?

Orh,00h,4~h,80h,26h,00h,60h,00h,OF2h,00h,00h,40h,OF5h,0Oh,3Fh, 87h,OFOh,ODFh

temp_flaq
int_mask_"eqiste"
old_ir'Lvector
int vecto" add"
int-bit
int-mask
ccmiDand_req
"ead_in_length
confiq_dmaO_1oc
confiq_dmal_loc
confiq_i"'Ll0c
config_bport
tx_sctive_flaq
f"ame status
atatuslO
statuall
status20
status2l

o

db
dw
dd
dw
db

?
?
?
?
?

db

dw
dw
db
db
db
dw
db
db

300h

;82592 port 0 addresa

?
?
?
?
?

o
o
o
o

db

db

o
o

db

db

even
'lP buf
'lP_length
'lP_buf_offaet
'lP_offaet_sdjust
'lP_buf_stsrt
'lP_buf"'psqe
t,,_byte_cnt
"" buf atart
rz:bufJ,aqe
rx buf head
here rx buf tail
r,,:bufJ,tr
",,_buf_stop
r"_buf_length
r,,_buf_segtMnt
curr_rx_lenqth
"z liat

num of

frames

reset rx buf
padding -

dw
dw
dw
dw
dw
dw
dw
dw
dw
d.
dw
dw
dw
dw
dw
dw
dw
dw
' dv
dw

5000 dup (0)
1388h
cgroup: 'lP_buf

o
o

o
o
o
o
o

o
o

o
o
o
o

;twice the required size

;Al-AU of General Purpose Buffer EA
;Al7-A23 of General Purpoae Buffar EA
;IPX packet length plus header length
;Al-Al6 of General Purpose Buffer EA
;A17-A23 of General Purpoae Buffar EA
;current rx bead, buffer has been flushed to
ivalue read fram 10 cent latches
;u.ad during rz list generation
;point to reset tha DNA controller

;calculated at init for use by IPXReceivePackat

180 dup (0)

o
o

'0

Define Hardware Configuration
290189-20

infef

Ap·320

Table 2. Declarations (Continued)
ConfigurationID

db

SDriverConfiguration

'NetWareDriverLAN WS

LABEL

reserved1
db
node addr
db
reserved2
db
node addr type
db
max data size
dw
(512, 1024, 2048, 4096)
Ian deBe offset
dw

byte
4 dup (0)
6 dup (-0)

o
o

inon-zero means is a real driver.

;address is determined at initialization
1024 ;largest read data request will handle
LANOptionName
OAllh
; Bogus Type Code

lan-hardware id

db

traiisport tiDie
reserved "3
major version

dw
db
db

minor- vez:sion

db

fla!Lbits
selected_configuration

db
db

o
o

db
dw

01
eonfigurationO

;transport time

1

11 dup (0)
Olh ;Bogus version number

OOh
:board configuration (interrupts, IO

addressBs, etc.)

number_of_configs
config-pointers
LANOptionName
configurationO
db

dw
db
dw
db

o
o,
o
o"

db

db
db

db

'Intel LAN-On-Motherboard Module',O,'$'

d"

300h, 16, 0, 0

;10 ports and ranges

0

0

:m&mOry decode
;interrupt lavel 10
:DMA channels 6 and 7

OFFh, 10, 0, 0
OFFh, 6, OFih, 7
0,0
'IRQ 10, 10 Addr

= 300h,

DMA 6 and 7, For Evaluation Only', 0

;**.****~********************************************* .*

..

Error Counters

i.--........................-.._...........-.._.*._...

A ••

Public DriverDiagnosticTable,DriverDiagnosticText

DriverDiagnosticTable

LABEL

DriverDebugCount

dw

D~ive~Ve:r:sion

db
db

StatistiesVersion
- Tota1TxPacketCount
TotalRxPacketCount
NoECBAvailableCount
PacketTxTooBigCount
PacketTxTooSmallCount
PacketRzOve:r:£1owCount

PacketRxTooBigCount
PaeketRxTooSmallCount
PacketTxHiscErrorCount
PacketRzMiscErrorCount
RetryTxCount
ChecksumErrorCount

dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
d"
dw

byte
DriverDebugEnd-DriverDiagnost'ic-:able

01,00
01,00
0,0
0,0
0
-1
-1
0
0
0
-1
-1
0
-1

inot used
; not used

inot used
;not used

;not used
290189-21

1-175

Ap·320

Table 2. Declarations (Continued)
HardwareRXMismatchCount
NumberOfCUstomvariables
DriverDebUgEndl

dw
dw

LABEL

0
(DriverDiagno8tic~ext-DriverDebugEndl)/2

byte

.......................................

"""1"",., •• " " " " . " . " " " . " , ,
Driver Specific Error counts

.......................................

""""""""""""""""""""
rx errors
underruns

no_cta
no era
rx-aborts

no-S90 int
false 590 int
lost

rx -

stop:tx

ten cent latch crash

rx disb failure
t,,-abort failure
rxbuff ovflw
tx:U.meout

dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
d"
dw

0
0
0
0
0
0
0
0
0
0
0
0
0
0
LABEL

DriverDiagnostic~ext

db
db
db

db
db

db
db
db
db
db
db
db
db
db
db

byte

'RxErrorCount',O
'OnderrunCount',O
'LostC~SCount' ,0
'LostCRSCount',O
' RxAbortCount I

I

0

'NoS90InterruptCount' ,0
'FalseS90InterruptCount',O

'LostOUrReceiverCount',O
'QuitTransm1ttingCount',O
'TencentLatchCrashCount',O

'RxDisableFailureCount',O
'TxWontAbort',O

'ReceiveBufferOverflow',O
'TxTimeoutErrorCount',O

0,0

DriverDebugEnd

LABEL

word
290189-22

1-176

inter

AP-320

7.2 Initialization Routine
This routine, Driver Initialize, initializes the Embedded
LAN Module hardware and the system hardware needed to support the module. It also sets up the system
memory structure to support the module.
7.2.1 HARDWARE INITIALIZATION AND 82592
CONFIGURATION

Initialization of the Embedded LAN Module hardware
begins with generating an individual address for the station, initializing the interrupt line and interrupt vector,
and enabling the module by writing to port address
303h. After initializing the memory structure, the
82592 is directly programmed. This programming includes configuring the 82592 and initializing it with the
station's individual address. The 82592 is configured in
two steps. The first specifies a l6-bit-wide system bus
interface by issuing a Configure command to the 82592,

with OOh as the byte count; i.e., no parameters passed to
the device. Then a second Configure command is issued; it does the following.
• The 82592 is put in High Speed Mode to support
Ethernet serial bit rates.
• It is placed in TCI mode for interface to the Embedded LAN Module architecture.
• All network parameters (e.g., Frame Length, Slot
Time, and Preamble Length) are set up for default
Ethernet values.
FollowiIig this initialization llnd configuration of the
module's hardware, the 8259A Programmable Interrupt Controller's-interrupt line for the module is enabled, allowing the interrupt-driven events frame reception and completed transmission. Then a Receive Enable command is issued to the 82592. Table 3 contains
the code for hardware initialization.

Table 3. Hardware Initialization
segment ' CODE'

public
OriverInitialize, DriverUnHook
no card massage
db CR,LF, 'No adapter installed in PC$'
configJailure_Dlessage
db CR, LF, 'Cqnfiquration Failure$'
iaset failure message
db CR,LI', 'IA Setup Fail.ure$'
ConfigDatauncie'rrUnHeSS
db CR , LF, , Configuration underrun$'
Driver Initial.iza
assumes:
OS, ES are set to CGroup (= CS)

DI points to where to stuff node: address
Interrupts are ENABLED
'lha Real. 'rilDe Ticks variabl.a is being set, and the
entire US system is initial.ized.

returns:
If initialization is clone OK:
AXhasaO

Xf board malfunction:
AX gets offset (in CGroup) of ' $' -terminated error string
DriverInitial.ize PROC
NEAR.
mov
MaxPhysPacketSize, 1024
cl.i
c:l.d

ax, cs
cis, ax
moves, ax
get DOS tizn& and use :for address.
mov
ah,02Ch

mov
mov

int
mav
mav

mov
mov
mev
mov
mev
mov
movsw

2lh
bx, OFFSET CGroup: nod.a_ ac1dr
byte ptr c:group: [bx], OOh
byte ptr cgroup: [bx+l], OAAh
byte ptr cgroup: [bx+2], ch
byte ptr cgroup: [bx+3], dl.
byte ptr cgroup: [bx+4], db
byte ptr cgroup: [bx+S], 7Eh
si, bx ,
; stuff address at point IPX indicated

DlOVSW

mavs",

ati
initia,U.ze the configuration tabl.e
!nOv
a1, selected_configuration
cbw
shl
ax, 1
; multiply ·by two
add
az,OFESET CGROW:config.J'Ointers

iax contains the offset value

290189,-23

1-177

inter

AP-320

Table 3. Hardware Initialization (Continued)
IIIDV
IIIDV

mov
mov
mov
mov
mov
mov
mov
mov
mov

bx,ax
bx, [bal
Config,hz
al, [ba+DMAOLOC]
config_dmaO_loc,al
al, [ba+DMA6LOCl
config_dmal_loc,al
al, [bxURQLOCl

;of the default configuration
; list

config_i~loc,al

aa,[ba+BPOM]
command_reg, 300h

Set~heInterruptVector:

SBT UP THlii

push
mov
mov
call
pop
mov
out
hlow

d1
al,

DI'l'BRRUP~ VBC~ORS

config_ir~loc

OFFSE~ CGroup: DriverISR
SetInterruptVector
di
dx, BnLAN
dx, a1
;enable LAN on MB module

hz,

IDOV

dx, command_reg

mov
out

al, C RS~
dx, aT

; reset the 82592 controller

;generate 20 bit addreas for DMA controller from configure block location
;this i8 necessary to accomodate the page register used in the PC DNA
call

set_up_buffers

:set up DMA channel for configure,command
ax, aa
xor
DMAff, al
out
;data i8 don't care
hlow
al, DMAena
mov
DMAcmdstat, al
out
ax, gp_buf_stsrt
mov
'slow
out
DMA6addr, al
al, ah
mov
'slow
DMA6aclclr, al
out
ax, gp_buf.J>age
mov
blow
DNA6page, al
;DNA page value
out
ax, 1
mov
'slow
DNA6wdcount, al
;make two transfers
out
al, ah
mov
blow
DMA6wdcount, al
out
al, DMAtx6
mov
: setup channel 6 for tx mode
hlow
DHAmode, al
out
al, DMA6Wl111Sk
mov
290189-24

1·178

intJ

AP-320

Table 3. Hardware Initialization (Continued)
%slow
out
XOI:'

DMAsnglmsk, a1
ax, ax

mov

di, 9P buf offset

the
atoaw
stOB'"
%slow
mov
mov

out
%slow

-

;mov zeroes into the byte count field of the

-;buffer to put the 82592 into 16 bit mode

dx, command rag
al, C CONFXG
dx, 81

;configure the 82592 for 16 bit mode
:issua configure command

wide_modB_wait_100p:
xor
al, a1
%slow

out

dx, al

;point to register

°

%slow

in
and
cmp
jz
loop
mov
jmp

°

a1, dx
;read register
a1,ODFh
;dioregard exec bit
al, 82h
i is configure finished?
do config
wide-mode wait loop
ax, OFFSET CGroup: no card message
init_exit
--

do_confiq:

mov
out
xor

al, C IN'rACK
dx, aI

;clear interrupt

ax, ax

%slow

out
mov

DMAff, a1

idata is don't care

ax, gp_buf_start

%slow

out
mov
%slow
out
mov

DMA6addr f

a1

al, ah
DMA6addr, a1
ax, 9P_bufJ'age

%slow

out

DMA6page, al

;DMA page value

%slow

mov
out

al, DMAtx6

;setup channell for tx·mode

DMAmode, a1

%slov

mov
out

ax, 8
DMA6wdcount, &1

%slow

mov
out
%810"
mov

out
mav
mov
mov
mov

al, ah
DMA6wd.count, a1
al, DMA6unmsk

DMAsnglmsk, a1
ax, d.s
es, ax
8i, offset cgroup:config block
di, 9P_buf_offset
290189-25

1·179

,inter

AP-320

Table 3. Hardware Initialization (Continued)
mav

ex, 18

rep movab
mav
mav

dx, command_reg

out

dx,

a1, C CONFIG

configure the 82592

a1

%slow

zor

ex, ex

config wait 100p:
%a10" a1, a1
"or
%slow

out
..10..
in
and
cmp
jz

100p
mav
jmp

c:bI:, a1

;point to register 0

a1, c:bI:
a1, ODFh

;read register 0
:discard·extranaous bits

a1, 82h
; is configure finished?
config done
config_wait_1oop
ax, OFFSET CGroup: config_fai1ure_message
init_exit

config done:
c1ear interrupt caused by configuration
mav
a1, C IN'rACK
out
cix, a1
do an lA_setup

mov
mov

di, gp_buf_offset
al, 06h
:address byte count

stoab
mov
stosb

a1, DOh

mov
mov

8i, OFFSET CGROUP : node addr
cx, SIZE node_addr
-

rep movsb

out

DMAff, a1

;data is don't care

%slow

mov
out
mov
'a1,?"

out

mav

h10w
out

ax, gp buf start
DMA6addr, 81
al, ah
DMA6addr, a1
ax, gp_bufJ>age
DMA6page, a1

:DMA page value

%slow

mov
out
%&10w
mav
out

a1, DMAtx6
DMAmode, 81

:setup channell for tx mode

ax, 3
DMA6wdcount, a1

%slow

mov

a1, ah

out

DMA6wdcount, a1

%slow

mov·
out

a1, DMA6unmsk
DMAsng1mak, a1
290189-26

1-180

inter

Ap·320

Table 3. Hardware Initialization (Continued)
IIIOV

dx, cOlnIl\and reg

IIIOV

al, C IASETc!x, aT

out
xor

;set up the 82592 individual ac1c1ress

ex, ex
:cz is used by the loop instruction below. this
:causea the loop to be executed 64k times max

ia wait loop:
- xo:out

blow
in
and
cmp

jz
loop

a~, a1
dx, a1

al, c!x
al, ODFh
al, alh
ia done

:discard extraneous bits

; is command finished?

IIIOV

ia_wAit_loop
ax, OFFSET CGroup: iaset failure message

jmp

init_exit

--

ia_done:
mov

a~,

C_DnACK

out
dz, a1
:clear interrupt from iaset
;initialize the receive DNA channel
xo:
al, a1
out
DMAff, al
mov

blow
out
mav

blow
out
IIIOV

%slow
out
IIIOV

hlow
out
IIIOV

%slow
out
mov

ax, rz_buf_start

:set dma up to point to the beginning of rx buf

DMA7ac1c1r, al
al, ah

DMA7ac1c1r, al
ax, rz_buf"'paqe

:set rz page register

DllA7paqe, al
al, DKArx7

DMAmoc1e, al
ax, rx_buf_length

;set wordcount to proper value

DMA7wc1count, al
a1, ah,

'slow

out
mov

OMA7wdcount, a1

al, dma7unmsk

:unmask receive DNA channel

%slow
out

DMAsnglmsk, 81

;unmask our interrupt channel
in
al, InterruptHaskPort
mov
bl, OFBh
and
al, bl
blow
out

InterruptMaskPort, a1

;enable the receiver
mav
dz, command_reg
mov
al, C RXENB
out
c!x, aT
xor
ax, as.

ienable receives

290189-27

1-181

inter
Table 3. Hardware Initialization (Continued)
mov

ex, 1

init exit:
ret
ConfigDataUnderrun:
mov
ax, orrsJ:~ CGro"p: ConfigDataUnclerrunMaas
:imp
init_axit
ZASet"poataunderrun:
mov
ax, orrSE~
:imp
init_exit
Driverlnitiali.a

CG~o"p:

ZASet"pDataUnderrun

andp

SetlnterruptVector
Sat the interrupt vector to the interrupt procedure' a address
aave the old vector for tha unhook procedure
assumes: bz has the ISR off.et
al has the IRQ lavel
intarrUpts are disabled
.SetlnterruptVector
PROC
!lEAR
mask on the appropriate interrupt mask
push
ax
xchg
ax, ex
raov
dl, 1
iget the appropriata bit location
shl
d1, c1
iset the interrupt bit variable
mov
eIl.int_bit, ell.
not
raov
int mask, ell.
; set th8 interrupt mask variable
raov
az,-IntarruptMaakPort
II10V
int_mask_register, ax
pop
ax
cld
cbw
ex, ex
xor
IIIOV

as, ex

shl
shl

al, 68h
lint 4
ax, 1
'ax, 1

xchg

az, eli

add

IIIOV
IIIOV

IIIOV

mov
mov
xchg
stos"

mov

;adding 8 converts int number to int type, i.e.,
12, int 5 = ,type 13 etc.

= type

;two shifts • mul by 4 to create offset of vector

int vector addr, di
;save this address,for unhook
ax,-as: IdYl
;save old interrupt vector
word ptr old_i~vector, ax
ax, es: ldil + 2
word ptr old_i~vector + 2, ax
ax, bx
;bx has tha ISR offsat
ax, os
290189-28

stos"

ret
SetlnterruptVector

endp
290189-29

1-182

inter

AP-320

• No page break occurs. The buffer size is not adjusted, the Tx/GP buffer area will be in the first 1200
bytes of the 10 kB buffer, and the Rx area will use
the remainder.
• A page break occurs, and the buffer is divided so
that one fragment is smaller than 1200 bytes. This
fragment is too small to be used and both the
TxlGP and Rx areas will be placed in the larger
segment.
• A page break occurs that divides the 10 kB buffer
into two segments both larger than 1200 bytes. The
software then places the Tx/GP area in the smaller
segment, and the Rx area in the larger.

7.2.2 INITIALIZING SYSTEM MEMORY

A buffer is constructed in system memory to support
the Embedded LAN Module architecture. This buffer
is divided into a receive buffer area and a transmit/general-purpose buffer area. This buffer (Tx/GP) is used as
the transmit buffer and as the parameter block for
82592 commands that require parameters.
The combined size of the buffer areas requested by the
program is 10 kB. The TxlGP buffer should be at least
1200 bytes long. The Rx buffer should be at least 5 kB
long. The amount of memory requested is twice the size
of the minimum Rx buffer length because of the possibility of a DMA page break occurring at some point in
the 10 kB buffer area. A page break can occur because
the SYP301 (or any PC AT based architecture) uses a
static page register to supply the upper address bits
(A17-A23 for a 16-bit DMA channel) during a DMA
cycle. These upper bits of the address cannot be incremented. The software checks for a page break and adjusts the buffer size if one is found. There are three
possible page break scenarios.

These three scenarios are shown in Figure 12. In no
case is the Rx area less than 5 kB-half the total buffer
size. Once these calculations are m~de, the transmit
and receive DMA channels, along with their page registers, are programmed to point to their respective areas
in the buffer (Tx/GP and Rx). With the memory now
initialized, configuration and initialization of the 82592
can begin.

Buffer

Buffer

Buffer

Start

Start

Start

A

Transmit and

General Purpose
Buffer Space.

A

A

Unusable Portion
(Less than

Transmit and
General Purpose

1200 Byte.)

Buffer Space.

DMA

1200 Bytes

boundary

1200 Byte.

B

",-buLstart

B

Transmit and
General Purpose
Buffer Space.

DMA

Wasted Space

boundary

age, dz
9P_buf..l'age, 1

290189-30

1-184

inter

AP-320

Table 4. Buffer Memory Initialization (Continued)
mov

gp buf sta:t, ax
rz-buf'-start, OOOOh
rx-buf-head, DOOGh
d:&-; 1 ; next page
r%_buf-page, dx
rX_buf...,page, 1.
ax, 1
dx, 0
bz, ex
; save number of bytes to page break

mov
mov
aCd

!nOv
shl
shl
ada

mov

mov

ex, 12

shl

dx, a1

mov

rx_ buf_segment, dx

sub
mov

gp_length, bx
ex, 9P_length
rz_buf_length, ex
ex, 258h
ex, 1
cz., ax
rx_buf_stop, ex
buffers_set

mov
sub
shl

add.
mov
jmp

rx first:

- mov
shl

rz_buf"'page, dx
rz_ buf-page, 1

mov

rx buf start, ax

mov

rx-]:)uf-head, ax

shl

rx-buf-head, 1

mav

rx:buf:langth, ex

mev

:ex buf stop, OFB9Eh
; 1200 bytes from end of buffer
gp-buf-st.art., DOOOh
1 ;next paqe
gp_buf""page, dx
gp_ buf""page, 1

mov
add
. mov
shl
acld
shl.

mev
add
sub
shl

dx-;

ex, 1
ex, 1

gp_offset._adjust, ex
gp buf offset, ex

dx;

1 dx, 1

shl

ax, 1.

ado

dz, 0
oz, 12
dx, a1

mov
shl
mov
jmp

rX_buf_segment,dx
buffers_eet

copacetic:
mav gp_buf_start, ax
add ax, 258h
mov l:X bUf start, ax
mov rx-buf-head, ax
ehl. rx-bUf-head, 1
sub 9P:1Qn~h, 258h
mov ex, w_l.engtb
mav

shl.
mav
mav

rx_buf_length, ex
dz, 1
rx_buf-PBqe, dz
gp_bu.£-page, dx

;Al-Al6 of gp buffer, gp buffer is first
; 1200 bytes for gp buffer at front of buffer space
; rx buffer starts 1200 bytes in

; convert segment to byte address

290189-31
sh1

ade
mav
shl

mav
mav
sub
sh1

add
mav

ax, 1
;convert offset to byte address
; adjust segment for shift
dx, 0
ex, 12
dx, e1
; load variable for transfers to IPX
l:X_buf_segment, dx
ex, rx_ buf_l.ength
; setup marker for low rx buffer space, >600 words
ex, 258h
cz, 1
ax, ex
l:X_buf_stop, ax

buffers set:

ret-

290189-32

1-185

AP·320

area. The construction of the frame is based on .the
ECB's address information and fragment list. The
transmit DMA channel is now initialized to point to
the beginning of the transmit frame in the Tx/GP area,
and the byte count for that channel is also initialized. A
Transmit command is now issued to the 82592. A separate routine monitors the transmission for a time-out
error. When an interrupt from the 82592 indicates that
the transmission attempt is complete (whether successful or unsuccessful), or if a time-out error has occurred,
the proper completion code is inserted into the fraine's
ECB, and the ECB is passed back to IPX. If additional
ECBs remain in the transmit queue the processing of
the next ECB will begin. Table 5 contains the code used
for assembly and transmission of frames.

7.3 Assembly and Transmission of
Frames
Frame assembly and transmission ,is accomplished by
the interaction of the software driver and IPX through
the use of IPX Event Control Blocks (ECBs). To transmit a frame, a transmit ECB is prepared that contains
address information and a list of fragments in memory
containing the frame to be transmitted. This ECB is
placed in a queue for assembly and transmission of the
frame. If the queue is empty, or when the ECB reaches
the ~ront of the queue, a routine is called that processes
the ECB for transmission. This routine determines the
length of the frame (padding the frame if necessary)
and then constructs the frame in the Tx/GP buffer

Table s. Assembly and Transmission of Frames
Ddver Sand Packat
Assumes

ES:SI points to a fully prepared Event Control Block
DS
CS
Iftterrupts an DISABLED b\l.t JDay be reenabled tempoZ'arily if necessary

=

don't naad to save any registar.
DrJ.varBroaclc••tPackat:
DdvarSendl'ackat
PROC
NEAR
cU.
; disabla the interrupts
mov cz, word ptr send_list + 2
jczz AddToFrontOfList
saarch to the end of the list, and add there.
mov di, word ptr send_list
AddToListLoop:
mov da, ex
mov cx, ds: word ptr [di).link
jczz AddLiatBndFound
IIIOV
di, de: word ptr [di).link
jmp AddToListLoop
AddListEndFound :
mav .s: vom
moves: word
mov de: word
mov de: word

mov
mov

az, cs
ds, ax

ptr
ptr
ptr
ptz:

+

2

[ai] .link, ex
[s1) .link + 2, cz
'[di) . link, s1
[di].l1nk + 2, a.

;move null pOinter to newest SCB's
;link field

; sat ds back to entry condition

ret
AddTol'rontOfList:
mov a.:word ptr[s1].l1nk, ox
mov as:word ptr[d].link + 2, ox
mov word ptr .and list, ai
mav worc:l ptr .end.:list + 2, .s
dz:op through to Start Sand
DriverSendl'acket

endp

Start Send
assumes:

BS: SI
points to the BCB to ba sant.
intarllUpts are disabled
start sand

public
oli

PROC
NEAR
start sand
- ; dis.ble the interrupts

290189-33

1-186

inter

AP-320

Table 5. Assembly and Transmission of Frames (Continued)
cld
save SCB address in vsriable tx_ecb to liberate regist~rs
mov word ptr tx_ecb, si
mov word ptr tx_ecb + 2, es
push de
;save da for future uae
get XPX packet length out of the first fragment (XPX header)
lds bx, es: dword ptr [sil.fragment_dascriptor_list
mov ax, ds: [bxl.packet_length
pop ds
; restore de to CGROUP
push ax
;save length for later use in 590 length field
zchg al, ah
;byte swap for 592 length field calculation
add ax, 18
;add in the overhead bytes DA,SA,CRC,length
mov

padding, 0
ax, 64
ja
long enough
mov paddIng, 64
;minimum length frame
sub padding, ax
;pad length
!DO?
ax, 64
long_enough:
sub ax, 10
;SA and CRC are done automatically
cmp

inc
and
mev

ax
a1, OFEh
iframe must be even
tx byte ant, ax

mov

di;gp buf offset

mev bx, C8
maves, bx

-

move the byte count into the transmit buffer
stosw

move the destination address from the tx BCB to the tx buffer
mov

bx, ai

lea
mov

8i, [bxl.immediate address
de,word ptr tx_ecb-+ 2

movsw
movs..,

movsw
mov ax,es
mav cis,ax

; qet back to the coda (Dqroup) section

now the 590 length field
pop ax
xchq ah, al
inc ax
imake Bure E-Net length field is even
and al, OFBh
xchq ah, al
s~osw

1ds
mav
lea

ai, tx ecb
ax, ds: [sil.fragment count
bx, [sil.fragment_dascriptor_list

move_frag_loop:

push ds

; save the segment

ez, ds: [bxl.fragment_length
lds si, ds: [bxl.fragment_address
%fasteopy
; qet the segment back
pop de
add bx, 6
dec ax
jnz move_frag_loop

mev

290189-34

1-187

inter

AP-320

Table 5. Assembly and Transmission of Frames (Continued)
;start transmitting
mov
mov

;add any
mov
add
ahr
rep
mov
ZOE'

out
mov
blow
out

mov
%2110.
out

ex, cs
da, ex
~ired padding
ex, 4
;maka s~ra frame ends with a NOP
cx, padding
ex, 1
stosw
t,,_active_flag, 1
ax, az
DMAff, al
idat. is don't care, AX has been zeroed
ax, 9P_buf_start

DMA6addr, 81 \

a1, ah
DMA6addr, al
ax, w_bufJ'age

mov
%slow
out DNA6page, al
iDHA page value
talow
mov al, DMAtx6
; setup channel 1 for tx mode
out . DMAmode, a1
mov ax, tX_byte_cnt
add ax, 4
;add two for byte count, two for tx chain fetch
shr ax, 1
iconvert to word value and account for odd
ade ax, 0
;byte DNA transfer
out DNA61fdcount, al
%slow
mav

out
blow
mov
out

al, ah
DMA6wdcount, a1

Il10''

a1, DMA6unmsk
DMAsnglmsk, a1
dx, command reg

mev

a1, C TX

-

out dx, al
mov ax, IPXlntervalMarker
:mov tx start time, ax
',inc32 -~otal:rxPacketCount
ret

; ; ••• *****.** •••••• ******** ••• **********.,******.***.*************
Driverpoli
Poll the driver to see

i~

there is anything to do

Is there a transmit timeout? 7£ 80, abort transmdssion and return
ECB with bad completion code. Check to aee if frames

a~ ~eued.

If they are set up ES:SI and call DriverSendPacket.

;**********************************************************************
DriverPoll
c1i

PROC

290189-35

1-188

inter

AP-320

Table 5. Assembly and Transmission of Frames (Continued)
amp
jz

mav
sub

amp
jb

tx active flag, 0

Ho~WaitingonTx
dx, IPXlntervalMarker

cIz, tz start time
cIz, TxTimeOutTicks
NotTimedOutYet

Thia tranamit is taking too long so let'. terminate it now
Issue an abort to the 82592
mov
out

dx, command :ego
al, C ABORTdz, a1

inc

tx timeout

II10V

iabort transmit

les

si-;- tz eob
es: [aTl.completion_code, TransmitHardwareFailure
coda of a failed tz
II10V
ax, ea: word ptr [ail.link
II10V

mav

word ptr sand list, ax

II10V

ax, es: word ptr [ail.link + 2
word ptr send_list + 2, ax

II10V

:stuff completion

Finish the transmit
moves: [ai].in use,

call IPXHoldEvent
:make sure that execution unit didn't lock up because of abort errata
II10V
II10V

out
II10V

islow
out
II10V

islow
out
II10V

blow
out
II10V

cIz,
al,
cIz,
al,

command_reg
C_SlIPl
al
C_SELRST

cIz, al
al, C_SIIPO
cIz. al
al, C_RXENB
cIz, al
tx_active_flag, 0

See if any frames are queued
mov cx, word ptr send_list + 2
jcxz queue_empty
moves, ex
mov ai, word ptr send_list
call sta"_send
queue_empty:
NotWaitingOnTx:
NotT.imedOutYet:
ret
290169-36

1-189

inter

Ap·320

Table 5. Assembly and Transmission of Frames (Continued)
DriverPoll

endp

:*********************************** ••• **************** ••••••••••
Interrupt Procedure
j

***** •• *****.********************************,*******************

even
RxErrorType~eck:

BufferOverflow,
ino
rx buff ovflw
jmp
int_ezit
not 590 int:
-inc- no 590 int
jq> int_exIt
Dr1verISR
publio
push
push
push
push
push
push
push

PROC
DriverISR

far

ax
bx
cx
de

s1
di

bp

push dB
push es
old
int"'poll_loOp:
cli
oall IPXStartCriticalSection
mov al, EOI

;tell AES we're busy

out

%nta~~ptControlPort,

out

ExtralnterruptControlPort, al

mav

mov
mov
mov

ax,

a1

CIS

de, ax

;DS pOints to C/DGroup

de, command_reg
a1, 0
de, al
;aet status reg

out
"slow
in
al, de
teat al, SOh
jz
not_590_int
and
mov

ah, al

al, NOT 20h

amp

ah, OoSh

t~

point to reg 0

;ignore the EXEC bit
isava the status in AH

;did I receive a frame?
290189-37

1·190

intJ

Ap·320

Table 5. Assembly and Transmission of Frames (Continued)
cmp
:I z
cmp

jz

rcvoll_lOop:
and al,~:r 20h
;ignore the EXEC bit
JIIOV
ah, al
;save the status in AH
cmp ah, ODBh
:did I receive a frame?
jx
zcvdJ>acket
cmp ah, 84h
;did I finish a transmit?
jx
sentJ>acket~mp
cmp ah, Beb
;did I finish a retransmit?
jx
sentJ>acket~mp
inc false_SgO_int ;unwanted interrupt
jmp int_exit
sentJ>8cket~mp:

jmp sentJ>aCket
bad rc,;:
-inc
jmp

rx errors

RXZrzcr:rypeCheck

int_exit_jmp:
jmp int_exit
;When the address bytes are being read it is pcssible that another frame
;could come in and cause a coherency problem with the ten-cent latches.
;1 am dealing with this possibility by reading :renC8ntHi twice and making
;aure the values match. If they don't the read is re~ne.
rcvd.J>acket:
cli
JIIOV

in
Il\OV

JIIOV

dx, :renCentHi
;read high address byte of last frame received
al, dx
ah, a1
;save it in ah
dx, :renCentLo
;read low address byte of last frame received
al, dx

in
JIIOV
>:X buf tail,'ax
;this is the last location containing rx data
:Read :renCeDtHi-again to make sure it hasn't changed ..... ,.
mov dx, :renCentHi
;read high address byte again
in
al, dx
cmp al, ah
jz
addr ok
;Z8ad the latches again
jmp rcvd:packet
addr_ok:
this ia a valid address
mov ax, Z'x buf tail
this is the last location containing rz data
mav rZ_bufJ»t:r:7 ax
is most of the buffer already used?
czap rx_buf_8top, ax
ja
BufferOlC
mov

BufferOK:
cmp

ja
inc
jmp

reset rs buf, 1

-ax, >:x_buf_head
process_new_frames
ten cent latch crash
int:...it-

do next frame:
procass:naw_frames:
JIIOV
bz, rx_bufJ>tr
aub bz, 6
moves, Z'z_huf_sagment

end of current frame to process
set bx up to point to beginning of the status
this is necessary because latches hold SA not
offset relative to CGROUP
290189-41

1-194

inter

AP-320

Table 6. Receive Frame Processing (Continued)
mov
test
jnz
mov
mov
clec
ancl
sub

al, es:[bx] .status1
81,20h
goocl_rx
cl, es: [bx] .bc 10
ch, es: [bx] .bc:hi
ex

cl, Ofeh
hz, ex
amp rx buf heBcI, bx
je
hancl_off-packet_jmp
mev rx_bufJ>tr, bx
sub rx_bufJ>tr, 2
to clo next frame:
dO_next_frame
hancl_offJ>&Cket_jmp:
jmp hancl_offJ>Bcket

;teat for good receive

:cx has actual number of bytes reacl
: toss byte count & status
: rouncl up
:bx points to first location of frame
:this was the first frame in the sequence

- jmp

goocl_rx:
c~, es:[bx] .be 10
mov ch, es: [bx].bc-hi
mov curr_rx_length; ex
dec cx
ancl cl, Ofeh
sub bx, ex
mov rx_bufJtr, bx
sub rx_buf-ptr, 2
sub ex, 14
amp ex, 1024 + 64
jbe not_too_big
inc PacketRxTooBigCount
jmp clo_next_frame
not too big:
-amp- ex, 30
jae not_too_small

mav

iCX

has actual number of bytes read

; toss byte count , status
; round up

:bx points to first location of frame

=

:rx_buf-ptr
last location of n-l frame
: sub length of 802.3 header

inc PacketRxTooSmallCount
jmp clo next frame
not_t.oo_small: -

mav ax, es:[bx] .rx length
xchg al, ah
inc

get

rpx length

ax

ancl al; Ofeh
xchg al, ah
amp ax, es:[bx].rx-physical_length
to do next frame
xchg a1; ah
amp ax, 60 - 14

; same as 802.3 length?

jne

ja
mov
len_ok:
amp
jz

; at least mdn length minus header
; yes, continue
; no, round up

len ok
a",-60 - 14
ax, cx

: match physical length

not_inconsistent

; yes, continue

inc HarclwareRxMismatchCount
jmp cIo_next_frama
not inconsistent:
-'inc32 TotalRxPacketCount
mov

ax, 12

mul

num_of_frames

Double Word Increment

290189-42

1-195

inter

Ap·320

Table 6. Receive Frame Processing (Continued)
mov

di, ax

mav
add

rx list [di], bx
rx-list [di] , 14

:first location of ethernet frame
:first location of ipx packet

mov

ax~ rx_buf_segment

mav
mav

rx list [di + 2], ax
ax; word ptr es:[bx].rx length

xchg a1,ah

-

mav
mav
mav

rx list [di + 4], ax
ax; word ptr es: [bx]."",_source_addr
word ptr rx list [di + 6], ax

mov

ax, word ptr as: [bx] . rx source addr -I- 2

mav

+

0

word ptr rx_list [di.+ i], ax-

mav

ax, word ptr es:[bx].rx source addr -I- 4

mav

word ptr rx_list [di

add

num of fratrLas, 1

+ 10], ax-

CII9i' . rx buf-head, bx

je
CII9i'

je
jmp

hand_off-paeket
num of f:cames, 50
hand_off-packet
do_next_frame

hand_off-packet :
mav ai, rx list[di]
mav as, rx-list[di -I- 2]
mav cx, rx:list[di + 4]
les bx, rx_list[di -I- 6]
cli
push da
call IPXReceivePacket
pop ds
sub

num of frames, 1

jz

adjust-rx head
di,.12- jmp hand_off-packet
adjust rx head:
sub

mo;
add
mov

ax,
ax,

rx but tail
2 rx buf head, ax

-

-

;ast rx_buf_head to new value for next receive

:inter:cupt

int exit:
-push cs

pop
CII9i'

jnz

ds
tx_active_flag, 0
finish_exit

ve:cify that our receiva:c is still going.
mov

mav
out
%slow

in
test
jnz
jmp

dx, ccmmand_reg
al, 60h
dx, a1

;point to status byta 3

al, dx
al, 20h
finish exit
LostOUrReceive:c

finish exit:

eli

290189-43

1-196

Ap·320

Table 6. Receive Frame Processing (Continued)
call
mov
mov
out.

'81o"

xor

out
%alo",

IPXEndCriticalSect.ion
dz, coltlltand_reg
al, C_INTAClt
dx, 81
; issue interrv.pt acknowledge to the 590

al, a1.
dx, a1

; set status reg to point to reg 0

in
al, dx
test al, SOh
jnz intJ"'nding
c:mp reset rx buf, 1

jnl:
moy
Qut
,"slow
out
mov
mov
shl

no_Z'z.:buf_reset
al, dma7msk
CMA8nglmsJc, a1
CHAff, a1

ax, rx bu! start
rx but-heaCi, ax
:cx-buf-head, 1

out

OMA7addr, a1

mov

al, ah

;mask receive DMA

ch~nnel

:data i" don't care
; set dma up to point to the beginning of rx buf

tslow
Qut

mov
'slow

out
mov

'slov
out
mov

'slow
out
mov

mov

DMA'7adc1r, a1

al, OMArx7
DMAmacie, a1
ax, l:X_buf_l.enqth

; set up

rx buf

DMA7wdcount, a1
al, ah
DMA7wdeount, a1
dx, DMAsnglmsk

a1., DHA7unm.sk

IbloW'
out.

dx, a1

mov

dx, command_reg

mov

al, C RXENB
dx, aT

out
mov

reset_Z'z_buf,

no rx buf reset:

- eli -

call 'IPXServiceEvents
pop as
pop ds-

pop
pop
pop
pop
pop
pop

bp
di
si
cIx
ex
b"

pop

ax

290189-44

aU
iret
LostOurReceiver:
inc l.ost rx
1l\OY
al., C RXENB
mov dx, command reg
out d:c., al.
jmp finish_ ent

too_big:
.inc PacketRxOverfl.oWCount
jmp int_ent
int..,pending:
jmp intJ'oll_loop

290189-45

1-197

inter

AP-320

APPENDIX A
Expanding the 82592 Embedded LAN
Module Architecture to a Low-Cost ,
Non-Buffered Adapter

ADAPTER BLOCK DESCRIPTIONS
DMA Machine

The basic architecture ef the 82592 Embedded LAN
Medule can be expanded and applied to. a lew-cest,
nen-buffered adapter. This requires adding a DMA
unit and seme legic fer a bus master handshake. Such
an adapter would centain no. lecal bUffer memery. Its
cest advantage weuld ceme frem using existing system
memery, as the embedded medule dees. This adapter is
less cemplex than mest existing designs because it does
net require arbitratien legic fer access to. lecal memery.
This adapter becemes a bus master when data transfers
take place, either to. the 82592 (Tx) from system memery er frem the 82592 (Rx) into. system memery.
The same features ef the 82592 that make it successful
in embedded applicatiens make it well-suited fer nenbuffered adapters. As with the embedded medule, there
is no. intermediate buffering ef data in a lecal memery,
therefere data transfers to. and frem system memery
take place in real time. The 82592's large FIFO area
allews it to. telerate leng system bus latencies during
memery access. The 82592's high-perfermance, 16-bit
bus interface allews the adapter to. efficiently transfer
data to. and frem system memery when it gains access
to. the system bus. The TCI ef the 82592 will interface
with the adapter's centrellegic and DMA unit to. previde back-te-back frame receptien and autematic retransmissien en cellisien (both witheut CPU interventien). Figure 13 is a bleck diagram ef the basic architecture ef the embedded medule medified fer a nen-buffered adapter applicatien. The bleck titled "Centrel
PALs and Latch" tegether with the 82592 is the cere ef
the embedded medule architecture. One additienal
PAL (PAL C) has been added to. the basic architecture
to. effer mere legic fer deceding additienal cemponents
added to. the adapter. The address latch has alSo. been
,expanded to. 24 bits. The three shaded blecks (DMA
Machine, Master Legic, and Centrel PALs and Latch)
show the mest likely path fer integration on this adapter, providing a three-chip solutien ef ASIC, 82592, and
82C501. 'The 82C37 is commen in many ASIC cell Iibraries, effering a migratien path for this integration.

• 8237 DMA Controller. Serves as the core' fer the
DMA machine. Performs addressing and centrol fer
data transfers between the 82592 and hest system
memery.
• 8-Bit Page Counter. Provides the addressing bits fer
the upper bits ef address (A17-A23)'
• 8·Bit Register. Serves as the base register fer the
upper bits of the Tx DMA channel fer reinitializatien for automatic retransmission.
• 8-Bit Multiplexer. Selects between the upper bits of
Rx- er Tx-channel DMA.
• 8-Bit Latch. Latches the upper bits of address frem
the 8237 (AS-A IS).

Master Logic
• Master PAL. Implements a "master" handshake
with the hest system bus to gain access to. the bus as
a bus master.
• Timers (2). Contrels the maximum time the adapter
can held the bus, and the minimum time it must
wait befere attempting to. regain bus access.

Control PALs and Latch (Together
with 82592 and 82C501)
The basic architecture of the 82592 Embedded LAN
Medule.

Transceivers
Used to. buffer the adapter legic frem the hest system
bus, fer drive purpeses. Address consists.ef24 bits; and
Data, 16 bits.

1-198 .

1::
WR

DNA Woellin.

I

'I
c0

..

iii
CII

>

l-

e(

5 IolHz

I~

~
N

::t:

:2

I!
Q

0

IolRD
IolRW
lORD
10WN

0
C'oI

'I ;.)

·1_8

2

I

,.

2

}Z

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I

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I

I

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iii

l

u

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0

lORD
IOWR

fom:OA

a.

LANHIB
2. C: > IUPHIB
If the TSMS program is to be run on the iSBC 186/51,
steps required are:
1. C:>SBC
2. C: > IUPSBC

4.2 Capabilities and Limits of the
TSMS Program
The TSMS program initializes the LANHIB Ethernet!
Cheapernet station by executing 82586's Diagnose,
Configure, lA-Setup, and MC-Setup commands. The
program asks a series of questions in order to set up a
linked list of these 82586 commands. After initialization is completed, the program automatically starts the
82586's Receive Unit (monitoring capability). Transmissions are optional (traffic simulation capability).
The TSMS program has two modes of operation: Continuous mode and Interactive Command Execution
mode. The program automatically gets into the Continuous mode after initialization. The Interactive Command Execution mode can be entered from the Continuous mode. Once entered in the  Y
Enter byte number (1 - 11) _a> 4
Enter byte 4 (4H)
A6H
Any more bytes? (Y or N) _a> Y
Enter byte number (1 - 11) _a> 11
Enter byte 11 (BH) _a> 6
Any more bytes? (Y or N)
N
Configure the 586 with the prewired board addres~ _a> N
Enter this station's address in Hex ••> 000000002200
You can enter up to 8 Multicast Addresses.
Would you like to enter a Multicast Address? (Y or N) ==> N
You entered 0 Multicast Address(es).

._>

-->

Would you like to transmit?
Enter a Y or N
Y
Enter a destination address in Hex

-->

==>

000000002200

Enter TYPE _a> 0
How many bytes of transmit data?
Enter a number =-> 2
Transmit Data is continuous numbers (0, 1, 2, 3, ••• )
Change any data bytes? (Y or N) ==> N
Enter a delay count -=> 10000000000
The number is too big.
It has to be less than or equal to 65535 (FFFFH).
Enter a number _a> 60000
setup a transmit terminal count? (Y or N)
Enter a transmit terminal count ==> 500

==>

Y

Destination Address: 00 00 00 00 22 00
Frame Length: 20 bytes
Time Interval between Transmit Frames: 30.18 miliseconds
Network Percent Load generated by this station:
.0'
Transmit Frame Terminal Count: 500
Good enough? (Y or N)

==>

Y

Receive Unit is active.

292010-16

Figure 14. External Loopback Execution

1·216

inter

AP-274

---Transmit Command Block--0000 .at 033E
8004
FFFF
034E
2200
0000
0000
0000
Hit  to countinue
transmission started!

**************************** station Configuration *************************
Host Address: 00 00 00 00 22 00
Multicast Address(es): No Multicast Addresses Defined
Destination Address: 00 00 00 00 22 00
Frame Length: 20 bytes
Time Interval between Transmit Frames: 30.18 miliseconds
Network Percent Load generated by this station:
.0 %
Transmit Frame Terminal Count: 500
82586 Configuration Block: 08 00 A6 00 60 00 F2 00

00

06

***************************** station Activities ***************************
1# of Good
Frames
Transmitted
500

1# of Good
Frames
Received
500

CRC
Errors

Alignment
Errors

a

a

No
Resource
Errors

a

Receive
Overrun
Errors

a

292010-17

Figure 14. External Loopback Execution (Continued)

1-217

inter

AP-274

Traffic Simulator and Monitor Station Program

Initialization bequn
Configure command is set up for default values.
Do you want to change any bytes? (Y or N) .~> Y
Enter byte number (1 - 11) _a> 9
Enter byte 9 (9H) _a> 1
Any more bytes? (Y or N) ._> N
Confiqure the 586 with the prewired board address =z> Y
You can enter up to 8 Multicast Addresses.
Would you like to enter a Multicast Address? (Y or N) ==> N
You entered 0 Multicast Address(es).
Would you like to transmit?
Enter a Y or N =-> N
Receive unit is active.

**************************** Station Configuration ************************
Host Address: 00 AA 00 00 18 6D
Multicast Address(es): No 'Multicast Addresses Defined
82586 configuration Block: 08 00 26 00 60 00 F2

01

00

40

*.* •••••••••••••••• ********** Station Activities ********** •••••• **.*******

*

*

of Good
of Good
CRC
Frames
Frames
Errors
Transmitted Received
o
100
0
Enter command (H for help) ==>,D

Alignment
Errors

o

No
Resource
Errors

o

Command Block or Receive Area? (R or C) ..-> R
Frame Descriptors:
4000 at 036C AOOO at 0382 AOOO at 0398 AOOO at 03AE
0000
0000
0000
0000
0382
0398
03AE
03C4
03DA
03E4
03EE
03F8
2200
2200
2200
2200
2200
2200
2200
2200
0000
0000
0000
0000

Receive
OVerrun
Errors

o

AOOO at 03C4
0000
036C
0402
2200
2200
0000
292010-18

Figure 15. Frame Reception In Promiscuous Mode

1-218

Ap·274

0000
0000
0000
0000

0000
0000
0000
0000

0000
0000
0000
0000

Receive Buffer Oescriptors:
C064 at 030A C064 at 03E4 C064 at 03EE
03F8
03EE
03E4
OFEO
09F6
040C
0000
0000
0000
050C
050C
050C

0000
0000
0000
0000

0000
0000
0000
0000

C064 at 03F8
0402
15CA
0000
050C

C064 at 0402
030A
1BB4
0000
050C

Oisplay the receive buffers? (Y or N) ==> Y
Receive Buffers:
Receive Buffer 0
002C:014C 00 01
002C:015C 10 11
002C:016C 20 21
002C:017C 30 31
002C:018C 40 41
002C:019C 50 51
002C:01AC 60 61

:
02
12
22
32
42
52
62

03
13
23
33
43
53
63

04
14
24
34
44
54

05
15
25
35
45
55

06
16
26
36
46
56

07
17
27
37
47
57

08
18
28
38
48
58

09
19
29
39
49
59

OA
1A
2A
3A
4A
5A

OB
1B
2B
3B
4B
5B

OC
1C
2C
3C
4C
5C

00
10
20
30
40
50

OE
lE
2E
3E
4E
5E

OF
1F
2F
3F
4F
5F

03
13
23
33
43
53
63

04
14
24
34
44
54

05
15
25
35
45
55

06
16
26
36
46
56

07
17
27
37
47
57

08
18
28
38
48
58

09
19
29
39
49
59

OA
1A
2A
3A
4A
5A

OB
1B
2B
3B
4B
5B

OC
1C
2C
3C
4C
5C

00
10
20
30
40
50

OE
1E
2E
3E
4E
5E

OF
1F
2F
3F
4F
5F

03
13
23
33
43
53
63

04
14
24
34
44
54

05
15
25
35
45
55

06
16
26
36
46
56

07
17
27
37
47
57

08
18
28
38
48
58

09
19
29
39
49
59

OA
1A
2A
3A
4A
5A

OB
1B
2B
3B
4B
5B

OC
lC
2C
3C
4C
5C

00
10
20
3D
40
50

OE
1E
2E
3E
4E
5E

OF
1F
2F
3F
4F
5F

03
13
23
33
43
53
63

04
14
24
34
44
54

05
15
25
35
45
55

06
16
26
36
46
56

07
17
27
37
47
57

08
18
28
38
48
58

09
19
29
39
49
59

OA
1A
2A
3A
4A
5A

OB
lB
2B
3B
4B
5B

OC
1C
2C
3C
4C
5C

00
10
20
30
40
50

OE
1E
2E
3E
4E
5E

OF
1F
2F
3F
4F
5F

Hit  to countinue
Receive Buffer 1
002C:0736 00 01
002C:0746 10 11
002C:0756 20 21
002C:0766 30 31
002C: 0776 40 41
002C:0786 50 51
002C:0796 60 61

:
02
12
22
32
42
52
62

Hit  to countinue

I

Receive Buffer 2
002C:0020 00 01
002C:0030 10 11
002C:0040 20 21
002C:0050 30 31
002C:0060 40 41
002C:0070 50 51
002C:0080 60 61

:
02
12
22
32
42
52
62

Hit  to countinue
. Receive Buffer 3
002C:130A 00 01
002C: 131A 10 11
002C:132A 20 21
002C:133A 30 31
002C:134A 40 41
002C:135A 50 51
002C:136A 60 61

:
02
12
22
32
42
52
62

Hit  to countinue
292010-19

Figure 15. Frame Reception in Promiscuous Mode (Continued)

1-219

inter

AP-274

Receive Buffer 4
002C:18F4 00 01 02
002C:1904 10 11 12
002C: 1914 20 21 \22
'002C: 1924 30 31 32
002C:1934 40 41 42
002C:1944 50 51 52
002C:1954 60 61 62

03
13
23
33
43
53
63

04
14
24
34
44
54

05
15
25
35
45
55

06
16
26
36
46
56

07
17
27
37
47
57

08
18
28
38
48
58

09
19
29
39
49
59

OA
1A
2A
3A
4A
SA

OB
1B
2B
3B
4B
5B

OC
1C
2C
3C
4C
5C

OD
1D
2D
3D
4D
5D

OE
lE
2E
3E
4E
5E

OF
IF
2F
3F
4F
SF

Hit  to countinue
Enter command (H for help) ==> E

****************************

station Co figuration

*************************

Host Address: 00 AA 00 00 18 6D
Multicast Address(es): No Multicast Addresses Defined
82586 cop figuration Block: 08 00 26 00 60 00 F2

*****************************
II of Good
Frames
Transmitted

a

station Activities

*Frames
'of Good

CRC
Errors

Alignment
Errors

Received
100

0

0

01' 00

40

**************************
No
Resource
Errors
0

Receive
OVerrun
Errors
0
292010-20'

Figure 15. Frame Reception in Promiscuous Mode (Continued)

1-220

inter

AP-274

Traffic Simulator and Monitor Station Program

Initialization begun
Configure command is set up for default values.
Do you want to change any bytes? (Y or N) ==> N
configure the 586 with the prewired board address ==> Y
You can enter up to 8 Multicast Addresses.
Would you like to enter a Multicast Address? (Y or N) ==> N
You entered 0 Multicast Address(es).
Would you like to transmit?
Enter a Y or N ==> Y
Enter a destination address in Hex ==> FFFFFFFFFFFF
Enter TYPE ==> 0
How many bytes of transmit data?
Enter a number ==> 100
Transmit Data is continuous numbers (0, 1, 2, 3, ••• )
Change any data bytes? (Y or N) ==> N
Enter a delay count ==> 0
setup a transmit terminal count? (Y or N) ==> N
Destination Address: FF FF FF FF FF FF
Frame Length: 118 bytes
Time Interval between Transmit Frames: 159.4 microseconds
Network Percent Load generated by this station: 35.7 %
Transmit Frame Terminal Count: Not Defined
Good enough? (Y or N) ==> Y
Receive Unit is active.
---Transmit Command Block--0000 at 033E
8004
FFFF
034E
FFFF
FFFF
FFFF
0000
Hit  to countinue

292010-21

Figure 16. 35.7% Network Load Generation

1-221

inter

AP-274

transmission started I

****************************

station configuration

************************

Host Address: 00 AA 00 00 l86D
Multicast Address(es): No Multicast Addresses Defined
Destination Address: FF FF FF FF FF FF
Frame Length: 118 bytes
Time Interval.between Transmit Frames: 159.4 microseconds
Network Percent Load generated by this station: 35.7 %
Transmit Frame Terminal Count: Not Defined
82586 Configuration Block: 08 00 26 00 60 00 F2 00 00

*****************************

station Activities

**************************

Alignment
Errors

# of Good
# of Good
CRC
Frames
Frames
Errors
Transmitted Received
10459
0
0
Enter command (H for help) ==> H

40

No
Resource
Errors

o

o

Receive
Overrun
Errors

o

- Commands are:
D - Display RFD/CB
S - setup CB
C - SCB Control CMD
P
Print SCB
N
- ESI Loopback Off
ESI Loopback On
L
A
Toggle Number Base
Z
Clear Tx Frame Counter
Y
Clear Rx Frame Counter
E
Exit to continuous Mode
Enter command (H for help)
Enter command block type
Command block type:
N - Nop
I C - Configure
M T - Transmit
R D - Diagnose
S H - Print this message

==>

S

(H for help)

H

==>

S

IA setup
MA setup
TDR
Dump status

Enter command block type (H for help)
Enter command (H for help)

==>

==>

C

Do you want to enter any SCB commands? (Y or N)
Enter. CUC ==> 1
Enter RES bit ==> 0
Enter RUC ==> 0
Issued Channel Attention

==>

Y

Enter command (H for help) ==> D
292010-22

Figure 16.35.7% Network Load Generation (Continued)

1-222

inter

AP-274

Command Block or Receive Area? (R or C)
---Dump status Command Block--AOOO at 0364
8006
FFFF
27D6
Dump status Results
at 27D6
00 E8 3F 26 08 60
AA 00 40 20 00 00
62 63 3F BO 00 00
00 00 00 00 00 00
DC 05 00 00 OC 04
82 03 6C 03 F8 03
06 80 FF FF 64 03
00 00 D6 27 00 01
20 00 40 06 30 01
00 00 6A 03 OE 00
00 00 00 00 00 CO

00
00
00
00
DC
64
00
00
00
6C
00

Enter command (H for help)

FA
00
00
00
05
80
00
28
00
28
00

00
FF
00
00
E4
D6
D2
00
90
00
00

==>

S

00
FF
00
00
03
27
02
00
00
00
00

==>

40
FF
00
00
DA
E8
00
00
10
74

C

FF
FF
00
00
03
21
00
00
01
03

6D
B5
FF
70
DA
FF
00
30
00
00

18
9E
85
03
03
FF
00
26
00
00

00
EE
08
06
78
4E
00
00
6C
00

00
CF
FC
00
05
03
00
00
03
00

Enter command block type (H for help) ==> T
Enter a destination address in Hex ==> FFFFFFFFFFFF
Enter TYPE ==> 0
How many bytes of transmit data?
Enter a number ==> 100
Transmit Data is continuous numbers (0, I, 2, 3, ..• )
Change any data bytes? (Y or N) ==> N
Enter a delay count

==>

0

Setup a transmit terminal count? (Y or N)

==>

N

Destination Address: FF FF FF FF FF FF
Frame Length: 118 bytes
Time Interval between Transmit Frames: 159.4 microseconds
Network Percent Load generated by this station: 35.7 %
Transmit Frame Terminal Count: Not Defined
Good enough? (Y or N)

==>

Enter command (H for help)

Y

==>

C

Do you want to enter any SCB commands? (Y or N)
Enter CUC ==> 1
Enter RES bit ==> 0
Enter RUC ==> 0
Issued Channel Attention

==>

Y

292010-23

Figure 16.35.7% Network Load Generation (Continued)

1-223

inter

Ap·274

**************************** station Configuration *,***********************
Host Address: 00 AA 00 00 18 60
Multicast Addressees): No Multicast Addresses Defined
Destination Address: FF FF FF FF FF FF
Frame Length: 118 bytes
Time Interval between Transmit Frames: 159.4 microseconds
Network Percent Load generated by this station: 35.7 %
Transmit Frame Terminal Count: Not Defined
82586 configuration Block: 08 00 26 00 60 00 F2 00 00

40

***************************** Station Activities **************************
# of Good
Frames
Transmitted
106020

# of Good
Frames
Received
0

CRe
Errors

Alignment
Errors

0

0

No
Resource
Errors
0

Receive
Overrun
Errors
0
292010-24

Figure 16. 35.7% Network Load Generation (Continued)

5.0 IN CASE OF DIFFICULTV
This section presents methods of troubleshooting ("debugging") a LANHIB board. When a LANHIB board
is powered up with the TSMS program stored in
EPROMs, it should display "TRAFFIC SIMULATOR AND MONITOR STATION PROGRAM"
message on a terminal screen. If the message is not
displayed, the board has to be debugged. Section 5.1
describes basic- 80186/82586 system troubleshooting
procedures. Section 5.2 is for troubleshooting 82501
and 82502 circuits. After the 80186/82586 system is
debugged, the 82501/82502 circuits have to be tested.

and the other debugs the 80186/82586 system. The
waveform of the TRXCB output of the 82530 determines which path to be taken. If the 82530 is getting
programmed properly, there should be 153.6 KHz
(1/f = 6.51 p.s) clock on this output pin. If there is a
clock, the problem is probably in the RS-232 interface.
If there is no clock, then the system has to be debugged
using a logic analyzer.

'5.2 Troubleshooting 82501/82502
Circuits
If the TSMS program runs on the LANHIB but the
82586 is not able to transmit or receive, there must be a
problem in 82501/82502 circuits. The flow chart in
Figure 19 will guide troubleshooting in these circuits.
An oscilloscope is required.

5.1 Troubleshooting 80186/82586
System
Shown in Figure 17 is a flow chart for troubleshooting
80186/82586 system. The procedure requires an oscilloscope. A logic analyzer is needed if problems appear '
to be serious. The procedures will de~ug the board to
the point where the 82530 is initialized properly. If the
82530 can be initialized properly, ROM and RAM interfaces must be functioning. Board initialization routines (INIl86.PLM) linked to the TSMS program requires ROM and RAM accesses. Since the '82586
shares most of the system with the 80186, no special
debugging is required for the 82586. Wiring of all
82586 parallel signal pins should, however, be checked.
The flow chart branches to two major paths after the
first decision box. One path debugs the RS-232 channel

The board should be configured to Cheapernet and disconnected from the network. Two terminators will be
required to terminate a "T" BNC connector providing
an effective load resistance of 250 to the 82502.
The 82586 must have the system and transmit clocks
running upon reset. Since the transmit clock is generated by the 82501, the 82501 transmit clock output pin
(pin 16) should be checked. The TSMS program executes 82586's Diagnose, Configure, lA-Setup, and MCSetup commands during initialization. If the 82586 has
active CRS (Carrier Sense) signal, it cannot complete
execution of these commands. The 82501 should, therefore, be checked if it is generating inactive CRS signal
to the 82586 after power up. The LANHIB powers up
the 82501 i~ non-Ioopback mode.

1-224

AP-274

After making sure that the 82501 is generating proper
signals to the 82586, the TSMS program is restarted
with an initialization shown in Figure 20. The 82586 is
configured to EXT-LPBK= 1, TONO-CRS= I, and
MIN-FRM-LEN=6. The chip is also loaded with a
destination address identical to the source address. If
there are no problems in the 82501/82502 circuits, the
station will be receiving its own transmitted frames. If
problems exist, the station will only be transmitting.
Since the 82586 is configured to TONO-CRS (Transmission On NO Carrier Sense), the chip will keep trans-

(
-

YES

mitting regardless of the state of carrier sense. The
82501/82502 circuits can then be probed with an oscilloscope at the locations indicated in Figure 21. Probing
will catch problems like wiring mistakes, missing load
resistors, etc.
Once the station is debugged, it can be connected to the
network. If there is a problem in the network, the
82586's TDR command can be used to find the location
and nature of the problem.

)

START

I

IS "TRAffiC SIMULATOR AND
MONITOR STATION PROGRAM"
MESSAGE ON CRT?

NO

(HAVE AN OSCILLOSCOPE READY)

(

START DEMO

)
~

CHECK CLOCK WAVEFORM ON THE
TRXCB PIN(PIN 26) OF THE 82530
NO
USING AN OSCILLOSCOPE.
IS IT 153.6KHz(l/f=6.51 J.Lsec.}
SQUARE WAVE?

CHECK RS-232 DRIVER &
RECEIVER CHIPS. ARE THEY
CONNECTED PROPERLY? NOTE
THAT THE 1488(75188)
REQUIRES +12V & -12V AND
THAT THE 1489(75189}
REQUIRES ONLY +5V.

"-

CHECK RS-232 DCE & DTE
CONNECTIONS. THE LANHIB IS
A DCE AND AN ASCII TERMINAL
IS A DTE. ONLY PIN2(TXD}.
3(RXD}. AND 7(GROUND} ARE
USED.

"-

CHECK CONFIGURATION OF THE
ASCII TERMINAL. BAUD RATE
SHOULD BE SET TO 9600.
ALSO 8 BITS/CHAR. NO PARITY.
AND 2 STOP BITS/CHAR.

(

"START DEMO

(A LOGIC ANALYZER
MAY BE REQUIRED.)

CHECK CLOCK WAVEFORM ON THE
FOLLOWING PINS:
1. CLKOUT PIN(PIN 56} OF B0186
THIS SHOULD BE 8 MHz 50% DUTY
CYCLE MOS CLOCK.
2. CLK PIN(PIN 32} OF 82586.
THIS CLOCK IS PROVIDED BY 80186.
3. CLK PIN(PIN 20} OF 82530.
THIS SHOULD BE 4 MHz CLOCK.

"-

CHECK SIGNAL LEVELS OF THE FOLLOWING
80186 INPUT PINS.
1. RES PIN(PIN 24} SHOULD BE HIGH
AFTER POWER UP RESET.
2. NMI PIN(PIN 46) SHOULD BE LOW.
3. SRDY PIN(PIN 49} SHOULD BE HIGH.
4. ARDY PIN(PIN 55) SHOULD BE HIGH.
5. HOLD PIN(PIN 50} SHOULD BE LOW.
82586 IS NOT INITIALIZED YET.

ctJ

)
292010-25

Figure 17. Flowchart for 80186/82586 System Troubleshooting

1-225

AP-274

CONNECT A LOGIC ANALYZER ON THE
MULTIPLEXED BUS.
1. CONNECT ADI5-ADO, ALE, RD, WR, ROMHI
ROMLO, RAMHI, RAMLO, AND CS PIN(PIN 33)
OF 82530.
2. USE CLKOUT OF 80186 TO CLOCK THE
LOGIC ANALYZER. SAMPLE DATA ON RISING
EDGES.
3. TRIGGER THE LOGIC ANALYZER ON ALE
BECOMING HIGH.

~

CHECK RS-232 DRIVER lie
RECEIVER CHIPS. ARE THEY
CONNECTED PROPERLY? NOTE
THAT THE 1488(75188)
REQUIRES + 12V lie -12V 'AND
THAT THE 1489(75189)
REQUIRES ONLY +5V.

SHOWN IN FIGURE 18 IS AN EXAMPLE OF A
LOGIC ANALYZER TRACE. COMPARE WHAT'S
OBTAINED TO THE ONE IN FIGURE 18.
II' DIFFERENT. POSSIBLE PROBLEMS ARE:
1. HIGH BYTE EPROM AND LOW BYTE EPROM
ARE SWAPPED.
2. ADDRESS/DATA LINES ARE NOT CONNECTED'
PROPERLY.
3. ADDRESS DECODE PAL IS NOT PROGRAMMED
PROPERLY.

.1CHECK RS-232 DCE lie DTE
CONNECTIONS. THE LANHIB IS
A DCE AND AN ASCII TERMINAL
IS A DTE. ONLY PIN2(TXD),
3(RXD), AND 7(GROUND) ARE
USED.

etc.

.1-

CHECK II' 82530 IS GmlNG INITIALIZED PROPERLY
ON THE LOGIC ANALYZER. TRY OTHER LOGIC
ANALYZER TRIGGERING EVENT, 8.g. CS PIN(PIN 33)
OF 82530 BECOMING LOW.
,
MAKE SURE THERE IS 153.6 KHz(l/f= 6.51 },S8C.)
SQUARE WAVE ON TRXCB(PIN 26) OF 82530.

CHECK CONFIGURATION OF THE
ASCII TERMINAL. BAUD RATE
SHOULD BE SET TO 9600.
ALSO 8 BITS/CHAR, NO PARITY,
AND 2 STOP BITS/CHAR •

.1-

(

START DEMO

)

292010-26

292010-27

Figure 17. Flowchart for 80186/82586 System Troubleshooting (Continued)

1-226

AP-274

. - - - - - - - - AD15-ADO
. - - - - - - - ALE
,-----RD#

.,.....-,

jjj

1r~

~~~: 1rn~EA" .~m ~.
~~~L~~

Sa=

(PIN 33) OF 82530

009700 41 01001111
00980041 01001111
009900 41 01101111
TRIG 0041 11101111 · .... LOGIC ANALVZER IS TRIGGERED ON ALE HI.
0101 FF FO 01001111 · .... 80186 JUMPS TO FFFOH AFTER RESET.
010206 EA 00101111 • .... JMP INSTRUCTION (DIRECT INTERSEGMENT)
010306 EA 00101111
SEGMENT OFFSET = 0006H
010406 EA 00101111
SEGMENT SELECTOR = FFCOH
010506 EA 00101111
(80186 INSERTS 3 WAIT STATES BEFORE
010606 EA 00101111
UMCS REGISTER IS PROGRAMMED.)
010706 EA 11101111
0108 FF F201101111
0109 CO 40 00101111
0110 CO 00 00101111
0111 CO 00 00101111
0112 CO 00 00101111
0113 CO 00 00101111
0114 CO 00 11101111
0115 FF F401101111
0116 FF FF 00101111
0117 FF FF 00101111
0118 FF FF 00101111
0119 FF FF 00101111
0120 FF FF 00101111
0121 FF FF 11101111
0122 FF F6 01101111
012300 40 00101111
0124000000101111
0125 00 00 00101111
0126 00 00 00101111
0127000000101111
0128 00 00 11101111
0129 FC 06 01101111 ..... JUMPED TO FC06H
0130 2E FA 00101111
0131 2E FA 00101111
0132 2E FA 00101111
0133 2E FA 00101111
0134 2E FA 00101111
0135 2E FA 11101111
0136 FC 08 01101111
0137 16 8E 00101111
0138 16 8E 00101111

=

Figure 18. Example of Logic Analyzer Trace.

1·227

292010-28

AP-274

(

START

)

1
DISCONNECT COAX. PUT TERMINATORS ON
BOTH ENDS OF "T" CONNECTOR. MAKE SURE
THE BOARD IS CONFIGURED TO CHEAPERNET.

UPON POWER UP, DOES
82501 GENERATE:
1. 10 101Hz Tx C AND R x C ..N;..O_ _.,
r-_ _ _ _-"'YE;;.;S~
TO 82586?
2. INACTIVE CRS
RUN TSMS PROGRAM.
TO 82586?

I

I

I

.....

'--~-~...----WHEN A TRANSMISSION IS

~ ATIEMPTED, DOES THE TSMS' ~
PROGRAM DISPLAY "NO
CARRIER SENSE" MESSAGE?

POWER DOWN AND RESTART TSMS PROGRAM
WITH 82586 CONFIGURED
TO:
1. EXT-LPBK = 1
2. TONO-CRS 1
3. MIN-FRM-LEN 6
EXECUTE LOOPBACKS BY
USING DESTINATION ADDR
SAME AS SOURCE ADDR.
TRANSMIT ONLY A FEW
DATA BYTES.

=

82501/82502 CIRCUITS
MUST BE WORKING O.K.
IF THE STATION IS STILL
NOT RECEIVING, CHECK
STATION'S DESTINATION
AND SOURCE ADDRESSES,
CONFIGURATION OF 82586.

=

I

MAKE SURE THE 82501 IS
POWERED UP IN NONLOOPBACK MODE.

I

AN EXAMPLE EXECUTION
IS SHOWN IN FIGURE 20.
IF THE STATION IS NOT
RECEIVING WHILE IT'S
TRANSMITIlNG, THERE IS
A PROBLEM. PROBE
SIGNALS AT LOCATIONS
SHOWN IN FIGURE 21.
IT'S PROBABLY A WIRING
PROBLEM.

I
(

BOARD SHOUtD BE FUNCTIONAL.

)
292010-29

Figure 19. Flowchart for 82501/82502 Circuits Troubleshooting

1-228

AP-274

Traffic Simulator and Monitor Station Program
Initialization begun
configure command is set up for default values.
Do you want to change any bytes? (Y or N) =~> Y
Enter byte number (1 - 11) ==> 4
Enter byte 4 (4H) ==> A6H
Any more bytes? (Y or N) ==> Y
Enter byte number (1 - 11) =-> 9
Enter byte 9 (9H) ==> 08H
Any more bytes? (Y or N) ==> Y
Enter byte number (1 - 11) ==> 11
Enter byte 11 (BH) ==> 6
Any more bytes? (Y or N) ==> N
Configure the 586 with the prewired board address ==> N
Enter this station's address in Hex ==> 000000002200
You can enter up to 8 Multicast Addresses.
Would you like to enter a Multicast Address? (Y or N) ==> N
You entered 0 Multicast Address(es).
would you like to transmit?
Enter a Y or N ==> Y
Enter a destination address in Hex

==>

000000002200

Enter TYPE ==> 0
How many bytes of transmit data?
Enter a number ~=> 2
Transmit Data ie continuous numbers (0, 1, 2, 3, •.• )
Change any data bytes? (Y or N) ~~> N
Enter a delay count ==> 0
setup a transmit terminal count? (Y or N) ==> N
Destination Address: 00 00, 00 00 22 00
Frame Length: 20 bytes
Time Interval between Transmit Frames: 159.4 seconds
Network Percent Load generated by this station: 11.0 %
Transmit Frame Terminal Count: Not Defined
Good enough? (Y or N)

==>

Y
292010-77

Figure 20. TSMS Initialization for 82501/82502 Circuits Troubleshooting

1-229

l
12V

TI

+12V
OV

10V
ISOLATED

:~;:'i~

I
I

t

5V

t

,

II

1 M.I1,1/4W, 750V(MIN)

I
"1'1

~

~

....

aI

TXD

0'

, ~.

~ ~
o ~

....

co

m~"\

7

iFi
c

I

TXC
RXD

I

RXC

27

\,,=

26

16 TXC

~I
~

~
c

COT

;: I

RTS

10

240.11 .

·~lIf·

\

*

240.11

8

91

Vss AVss

16

t"7ol
5

Vee AVec

2 TRMT

VDD

3 TRMT

CXTD

50.11

14

78.11

15 I~

5V
25

9 RXD

23

8 RXC

RCV 4

82586
CRS

TRMT

~t;-

.O.017~

o,l~F

31
30

82501
ESI

V
\
78.11

6 CRS

\

28

RCV 5

15 TEN

CLSN

CLSN

12

11

BNC

''T'' CONNECTOR

43.11 4

RCV

82502
ETC

CXRD

~

12
100.11
FUSIBLE
1/8W

43.11

~

5 RCV

NC~

\

\

·~II~·

CL5N
HBD
43.11
6 CLSN

~
"a
I
N

..........

50.11
TERMINATOR

1143.11 7

78.11

1

Numbers are probing sequence.

lit

*

l/~~
~.22J'F

5V

0°
NOTE:

•

7 cor

r- LPBK

LPBK COMMAND
FROM I/O PORT

t~
0.22J'F

I~

,....

h

1
243.!l
0.5"

'7
292010-30

inter

Ap·274

APPENDIX A
LANHIB SCHEMATICS
PARTS LIST
PAL EQUATIONS
DIP SWITCH SETTINGS
WIRE WRAP SERVICES

1-231

PARTS
REFERENCES
Ul
U2
US.

U4

US
U6.U7
U9
U9
UI9
Ull
U12. U27

U29
ula
UI ...
UI6
Ul6
UI7
U19~

U22.

r\)

~

U2-:-

U2 ...
U25
U29
US9
ual
U.. 2
RI-RS. R6
R19.

Re. R12

R9. Ria
RII
Rla-R16
RI?

RI9
R21. R22
RPI
R2a-R26
CL C2
C3
C4. C5
C6
C?
CILCI2
cia
C9. C9
CRI
CR2. eRa
'II
'12

IC. 6"'K-Blt EPROM
IC
IC. SRAM
IC. 2S6-Blt PROM
IC
IC
IC
IC
IC. 1M-Bit EPROM (0 tional>
Resistor. 10K ohm. 11'41.L 5;(

82sall
1-489
1-488
27210
COItL

M R.
CODE
OBD
OBD
OBD
OBD
OBD
INT
INT
OBD
OBD
OBD
OBD
OBD
INT
PE
INT
PE
INT
OBD
HIT
TI
OBD
INT
OBD
OBD
INT
OBD

COItL
COML
COItL
COML
COML

OBD
OBD
OBD
OBD
OBD

COML
COML

OBD
RCD
OBD
ODD
OBD
OBD
ODD
OBD
ODD
OBD
ODD
OBD
OBD
OBD
OBD
OBD
OBD
OBD

~~:T

NO

74532

?4LS94,
74LS24S

74Fa7a
7 ...LSa?S
811186
82586

16L8
7 ...LS1I2
74LS7-4
74AS?4
?4LS165

925111
PE6 ... 192
92502
PE6 ...S69
276"'-29
7
NOTES:

I

I.

2.

1

I

I'"

§
§

12M

POWER SUPPLY COtlHECTIOItS.

6

...

I ~2~F

-12U

2
I
2
I
I
I
I
I
I

3
2
I

2~F

2. 2uF
I20U

R20

R...
RS
Ri'.

DESCRIPTION
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
Pulse Transror •• r Pack
IC
DC/DC Convert.er

U20

u26

l

LIST

I

THE BOARD REQUI~ES +SU. +12U. AND·-12U.
MULTIBUS PO~ER PINS FOR THESE VOLTAGES AND
GROUND ARE SHOUN ABOVE.

EACH Ie SHOULD HAVE A 0.1u'f' CAPACITOR BETUEEN
POIIER PIN AND GROUND PIN.
PARTS LIST DOES
NOT INCLUDE DECOUPLIHG CAPACITORS.

3.

nTR.
CODE

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292010-79

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DATA

292010-80

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DATA

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ADDRESS

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Ul
(J1

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292010-81

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AS
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21
24
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104
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102
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IDS
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102
101

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HM6264P-lS

~~t9
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Al2
All
AtB
AS
A8
A7
AG
AS
A4
Aa
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DATA

D7
D.
DS
D4
Da
D2
Dl
D.

18
17
16
15
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12
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D.
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292010-82

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ADDRESS

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292010-83

inter

AP-274·

OPTlotIAL 1ttEG (64)(..16) WOIID-NIDE EPRDI1

-

ADDRESS (A16 AU

21218
LA1691
01& 8
1&
A1686 14 014 4
A1486
19
019
Ala 94 12
012 6
A1293
011 1
11
A1192
Ie
018
Ale 91
08
9
A9 28 8
0818
A8 28 A1
0112
A? 21 A6
0613
A6 26 6
A6 26 4
.. 4 24 9
OS 16
AS 23 2
0211
A2 22
0118
I
AI 21
011 ~9
e
S9

DATA (DiS-DB)
ml&
D14
DIS
m12
mu
Die
D9
D8
D1
D6

~&:: ~:

"'fi.I

aH/C
U92

n
ROI1BUS

D8
D2
ml
De

m!~

'PI

292010-84

Module Addr_dec
Title "LANHIB Address Decode Logic
Kiyoshi Nishide
Intel Corp.

March, 1986'

"Declarations
PALl
AO. A14, A15
A16. A17. Al8
A19. BHE
HLDA. 52
RAMLO, RAMHI
ROMLO. ROMHI
ROM
RI04

device

'P16L8' ;

pin
pin

I, 2, 3;
4 •. 5. 6;
7. 8;
9, 11;

pin
pin

pin
pin
pin
pin

18. 17;
19, 12;

13 ;
16 ;

Equations
!ROMHI = A15 &: A16 &: A17 &: A18 II: A19 &: (HLDA # 52) II: RI04;
!ROMLO = !A15 &: A16 II: A17 II: A18 II:A19 II: (HLDA # 52) II: RI04;
!ROM = A17 &: A18 II: A19 II: (HLDA # 52) II: !RI04;
!RAMHI
!A14 &: !A15 II: !A16 &: !A17 II: !A18 &: !A19 II: !BHE II: (HLDA # 52);
!RAMLO = !AO &: !A14 II: !415 II: !A16 II: !A17 II: !A18 &: !A19 II: (HLDA # 52) ;
End Addr_dec
PAL Equations

1-238

inter

AP-274

3. To select the 2764-20 EPROMs or 27210 EPROM:

DIP SWITCH SETTINGS FOR
VARIOUS OPERATIONS

SW3
87654321 .

"I" indicates ON (Switch is closed).
"0" indicates OFF (Switch is open).
"X" indicates Don't Care.

2764-20 EPROMs
27210 EPROM

1. To configure the board to Ethernet or Cheapernet:

SW3
87654321

4. Dip Switch Setting Examples:

SW3
SW4
87654321 87654321

Comment

Ethernet
XXOOOOOO
Cheapernet XX111111 Transceiver Cable should
not be connected.

1) To run the TSMS Program OX111111 XXXX0010
from the 2764-20 EPROMs
in Cheapernet Configuration

2. To run the TSMS program or the Data Link Driver
program'

SW4
87654321

Comment

TSMS Program XXXXOO01 TSMS program uses
the 82530 in
or
Asynchronous Polling
Data ~ink Driver
mode. Data Link Driver
Program
program uses the
825830 in
Asynchronous Polling
and Vectored Interrupt
modes.

OXXXXXXX
1XXXXXXX

2) To run the TSMS Program OXOOOOOO XXXX0010
from the 2764-20 EPROMs
in Ethernet Configuration

S) To run the TSMS Program
or the Data Link Driver
program from the 27210
EPROM in Cheapernet
Configuration

1X111111 XXXXOO01

~)To run the TSMS Program

1XOOOOOO XXXXOO01

or the Data Link Driver
program from the 27210
EPROM in Ethernet
Configuration

5. Dip Switch SW2 programs the number of wait states
for the 82586 (see Table 3).

1-239

inter

AP-274

COMPANIES OFFERING WIRE WRAP. SERVICES
AUGAT
Interconnection Systems Division
40 Perry Avenue
P.O. Box 1037
Attleboro, MA 02703
(617) 222·2202
100935 South Wilcrest Drive
Houston, TX 77099
(713) 495·3100

Automation Delectronlcs Corporation
1650 Locust Avenue
Bohemia, NY 11716
(516) 567·7007

dataCon, Inc.
Eastern Division
60 Blanchard Road
Burlington, MA 01803
(617) ~73.5800
Mid·Western Division'
502 Morse Avenue
Schaumburg, IL 60193
(312) 529·7690
Western Division
20150 Sunburst Street
Chatsworth, CA 91311·6280
(818) 700·0600

South·Western Division
1829 Monetary Lane
Carrollton, TX 75006
(214) 245·6161
European Division
In der Klinge 5
D·7100 Heilbronn, West Germany
(01731) 217 12

DATAWRAP
37 Water Street
Wakefield, MA 01880
(617) 938·8911

Elma/EMS
A Division of Sandberg Industries
Berkshire Industrial Park
Bethel, CT 06801
(203) 797-9711
1851 Reynolds Avenue
Irvine, CA 92714
(714) 261·9473
3042 Scott Boulevard
Santa Clara, CA 95054
(408) 970·8874

WRAPEX Corporation
96 Mill Street
Woonsocket, RI 02895
(401) 769·3805

1-240

inter

AP-274

APPENDIX B
SOFTWARE LISTINGS-TSMS PROGRAM AND
LANHIB INITIALIZATION ROUTINE

1-241

AP·274

1*****************************************************************************1
1*
1*
1*

R/

r,.affic SimulatoT'/MonitoT' Station P1"ogram
for 186/586 High IntRgration Baa,.d and

iSBC 186/51

1*
1*
1*
1*
1*
1*

Vu.

December 17, 1984

1.0

IH~oshi Nishide

Intel COT'poT'ation

f/

*1

*1
*1
*1
*1
*1
*1

1*****************************************************************************1
1* This software

c~n be conditlonallv compiled to work on the iSBC 186/~1 Dr
on the LANHIB.
If ' •• tCSDCI8651), is added to the compiler call statement,
this source program will be compiled for the iSBC18651. *1

tsms:
do;

2

daclare main label publiCi
1* literals *1

$IF SBCI8651
declare lit
true

Ii terall V
lit
false
lit
forever
lit
ISCP$LOC$LO
lit
ISCP.LOC.HI
lit
SCB.BASE.LO
lit
SCBUASESHI
lit
CA.PORT
lit
BOARD.ADDRESS.BASE lit
INTSTVPE.586
lit
INTSTVPE.TIMERO
lit
INTSCTL.TIMERO
lit
INT$7
lit
PIC$MASK.130
lit
PIC.MASK.18b
lit
ENABLE.S86
lit
ENABLE.SBb.18b
lit
PIC$EOI$130
lit
EOI$CMDO.130
lit
EOI$CMD4S130
lit
PIC.EOI$IBb
lit
EOI$CMDO.IBb
lit
PIC$VTR$18b
lit

'literally
'1',

I,

'0',
',-,h i 1 It 1',

'OFFFOH',
'0',
'0',
'0',
'OeBH',

'OFOH',
'20H',
'30H',

'OFF32H',
'27H',
'OE2H',

'OFF28H',
'OFEH',
'OEEH',
'OEOH',

'60H',
'64H',

'OFF22H',
'0',

'OFF20H',
292010-31

Traffic Simulator/Monitor Station Program

1-242

AP-274

TIMERO.CTL
TIMERO.COUNT
MAX.COUNTtA
CA
ESItPORT
NO.LOOPBACK
LOOPBACK

lit
lit
lit
lit
lit
lit
lit

'OFF56H',
'OFF50H',

'OFF52H',
'0',

'oeBH',
'B',
'O'i

.ELSE
:3

d .. cla .... lit

literall~

true
false

foreve"

ISCP.LOC.LO
ISCP.LOC.HI
SCBtBASE.LO
SCB.BASE$HI
CA.PORT
BOARD.ADDRESS.BASE
INTtTVPE$5B6
INTtTVPE$TIMERO
INTtCTL.TIMERO
PIC.MASK.IB6
ENABLE$5B6
ENABLE.5B6.IB6
PIC.EOI.IB6
EOItCMDO$IB6
EOItCMD4.IB6
TIMERO.CTL
TIMERO.COUNT
MAXtCOUNT.A
CA
ESItPORT
NO.LOOPBACK
LOOPBACK

'literally',

lit ' 1',
lit '0',
lit 'whi Ie 1',

IH

lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit

'03FFBH',

'0'.
'0',
'0',
'BaCOH',
'SISOH',
'12',

'B',
'OFF:32H',
'OFF28H',

'OEFH' ,
'OEEH',
'OFF22H',
'12',

'B',
'OFF56H',

'OFF50H',
'OFF52H',
'0',
'BIOOH',

'I' ,
'O'i

.ENDIF
.IF NOT SBCIB651
1*
4

S~.t.m

Configuration Pointer *1

declare scp structure
(
s~.bus

b~te,

unused (5) but.,

iscp'addr$lo word,
iscp'addr$hi word
)

at (OFFFF6H) data (0, 0, 0, 0, 0, 0,

ISCP$LOC.LO, ISep$LOe'HI) i

$ENDIF
1* Intermediate System Configuration Painter *1

292010-32

Traffic Simulator/Monitor Station Program (Continued)

1-243

inter
5

Ap·274

declare iscpSptr pointer.
isep based iscp.ptr structure
(

busV bvte.
unused bVte,
scb$o \aiD I' d ,

,*

set to 1 bU CPU before its first CA to 5Bb.

cleared bV 586 after reading lnfo from It *1
1* unused *1
1* offset of sgstam'control block *1

scb$b (2) ,"ord 1* base of svstem control block *1
),

1* System Control Block *1
declare 5tb structure
(

status word.

1* cause(s) of intel"',rupt,

1*
'cblSoffset word. 1*
rp ..$offset ,"ord. 1*
ereSerrs word,
1*
1*
alnSerrs lIIord,
1"scSerrs word,
1*
cmd lIIord.

Dvrn'erT& lUord

int acks.
of' set of
of' set of
ere error

CU state,

RU state *1

CU cmd. RESET bit. RU cmd *1
'irst command block in CBL *1
first packet descriptor in RPA *1

e"counterd so far *1
alignment 'errors *1
no resources *1
1* overrun errors *1

),

1* B25Bb Action Commands *1
1* NOP *1
7

declare nap structure
(

cmd word,

link.offset ,"ord
),

1* Individual Address Setup *1
B

declare iaSsetup structure
(

statuI lIIord,
cmd word,

link.offset ,"ord.
iaSaddress (6) byte
),

,*
<;I

Con'igure *1

declare configure structure
(

,

statuI \IID'rd,
cmd lIIord,

link.offset ,"ord.
bvt.Scnt byte.
info (11) bVt.
),

292010-33

Traffic Simulator/Monitor Station Program (Continued)

1-244

inter

AP-274

1* Multicast
10

d.cla~.

Add~es.

Setup *1

me.setup structure
(

status

lUDT"d,

cmd ward,

link.offset word,
me.byt •• count word,
mcSadd~ess

(48) byte

1* only 8 Me

add~e.s ••

a~e

allowed *1

),

1* Transmit *1
1* This transmit command is made of one transmit buffeT descriptor and one
buffe~.

1518 bytes long
11

*1

declare transmit structure
(

status word,
cmd lIIord,

link'offset word,
bdSoffset
destSad~

type

wo~d.

(6) byte.

wo~d

),

1* Transmit BuFfer Descriptor *1

12

declare tbd structure
(

act.count \IIord,
link.offset word,
adO lIIord,

adl

wo~d

),

1* TT"ansmit Buffer *1

13

d.cla~e

14

decla~e

tlSbuffe~

tdr

(1518) byte,

.t~ucture

(

status

laJOT'd,

cmd word,
linkSoffset word.

result la.IDT"d
),

1* Diagnose *1
15

declare diagnose structure
(

292010-34

Traffic Simulator/Monitor St~tion Program (Continued)

1-245

inter

AP-274

status lIIord,
cmd ward,

linkSoffset word
),

1* Dump Status *1
16

declare dump structure
(

status lIIord,

cmd word,
link.offset word,

b u ffSp tr

1001'

d

),

1* Dump Are. *1
17

dec!.,.. dumpSarea (170) buts,
1* Frame Descriptor *1

1* Receive frame area is made of 5 RFDs. 5 RBDs. and 5 1514 butes long
buffers. *1
18

declare rfd (5) structure
(

status w01"d,

elSs word.
linkSoffset word.
bdSoUnt word.
destS.dr (3) word.
src$adr (3) word,

tupe word
),

1* Receive Buffor Descriptor *1
19

declare rbd (5) structure
(

act.caunt lIIo1'd,

n •• tSbdSlink word.
adO word,
ad1 lIIord,

size wo,.d
),

1* Receive Buff.r *1

20

declare rbuf (5) structure
(buff.r (1514) bUte),

21

declare status ward,

I*'global variable. *1
1* UART status *1

292010-35

Traffic Simulator/Monitor Station Program (Continued)

1-246

AP-274

ae tua 1 word,
c$buf (80) b~te.
dh,,. b~te.
ch bvte at (@c$buf).
char.count b'lte,
receive'caunt dCliord,

1* actual number of chars UART transferred *1
1* buffer fOT a line of chaT'S *1

1* number base switch *1

count dCliord,
pt"eamble word,
add~es.$length

b~te.

ad.loc bvte.
CT'C

but.,

goback b~te.
reset bvt.,
delav word,
curScb'of'set word,

current.frame bvte,

1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*

counte,. for received frames *1
counter for transmitted frames *1
preamble length in word *1
add~ess length in byte *1
add~ess location cont~ol of B2~8b *1
c~c length *1
if set, go back to Continuous Mode *1
reset flag *1
dela" conunt for tranmission dela~ *1
offset of current command block *1
offset of frame descriptor Just used *1

1*

t~ansmit

no.transmission bVte,

stop.count dWDT'd,

te~minal

f~ame

count *1

stop b~te.
mc'count bvte,
z b~te.
9 b~tei

1* external procedures *1

O!O!
23

1
2

~ead:

Ca,
(b,

24

2

end

25
2b

1
2

w~ite:

Ca, b, c, d,
c) wD~d,
d, e) PQinte~.i

p~ocedu~e

decla~e

e)

exte~n.l.i

~ead;

decla~e

p~ocedure (a,

b,

(iii,

c)

(b,

d) pointer;

c, d) exte~nai;

wo~d,

27

2

end

28
29

1

2

csts: p~ocedu~e blJte
end c StS1

w~ite;

1* utilitv

exte~nal;

p~ocedures

*1

offset: procedure (ptr) word.i

30

1* This

p~ocedu~e

absolute
and then
31

2

32

2

point.~ va~iable (selector:offset), caluculates an
subt~acts the 82586 SCB o'fset from the absolute address,
the result as an offset value for the 82586. *1

takes a

.dd~e5s,

~etu~ns

declare (ptr, ptr$loc) pointer,
base586 dword,
w based ptrSloc (2) word;
pt~$loc

=

@pt~,

1* 8258b SeB Base

Add~ess

(20-bit wlde in this l8b based

syst~m)

*1
292010-36

Traffic Simulator/Monitor Station Program (Continued)

1-247

inter
33
34

2
2

35

2

AP-274

base59b s (shl!doubh (iscp. scbSb(Il>. Ib) and OOOFOOOOH) + iscp. scbSb(O),
return 101d«shl!double (..,(1)). 4) + lOW)) - base58b),
end offseti

writeln:

3b

procedure (a.

b,

c', d)i

1* This procedure writes a line and put a CR/LF at the end. *1
37

2

dec lare (a,
(b,

39
39

2
2

40

2

1IIOT,d,'

d) painter;

·call ",rite(., b,

c,

d');

call .. rite(O. @(ODH. OAH). 2. @statusl,
end write!n;

cr$lf:

41

c)

procedure;

1* This procedure .. rites a CR/LF. *1
42

2

43

2

call Idrite (0. @(ODH. OAHI. 2. @statusl,
end crSlf,
pause: procedure;

44

1* This procedure breaks a program fl.old. and ... its for a char to be tuped. *1
45
47

2
2
2

49

2

4b

call write(O. @(ODH. OAH. 'Hit (CR> to countinue·l. 23. @statusl,
cali read(l. @cSbuf. 90. @actual. istatusl,
call crSIf,

skip: procedure but.,

49

1* This procedure skips all leading blank characters and returns the first
non-blank character. *1
'0

'1

2
2
2

dec loire i bUte,
i

- 0;

do Idhile (c'buf '),

20. @status);

end read$b i ti

yes:

74

*1

word;

procedure byte;

1* This procedure reads a character and determines if it is a y(~) or NCn),

75

2

76

2
3
3
3
3

77

7B
BO
'B1
B2

3

B3

3

B4

2

dec laTe b b'Jte;

do forever;
b = read.chaT;
if (b
'V') or (b
'1:1'> the~ return true;
else
if (b = 'N') or (b
'n') then return false;
else
call writeCO, @(ODH, OAH, ' Enter a Y 01' N ==)
end;

=

=

=

~),

22. @status);

end yes;
cha1'$to$int: procedu1'e

B5

(c)

blJtei

1* This procedure converts a blJte of ASCII integer to an intege1'

B6

2

B7
B9
90
91

2
2
2
2

.,

*1

declare c b1jtei
if ('0'

<= c) and (c <= '9') then 1'etu1'n (c -

30H)i

else

if('A' <= c) and (c

(=

'F') then 1'etu1'n (c - 37H)i
292010-38

Traffic Simulator/Monitor Station Program' (Continued)

1-249

intJ
92
93

2
2

94

2

AP·274

if ('a' <= c) and (c
else return OFFHi

57H);

end char$to.inti
i.ntstoSasci:

95

'f') then return (c -

(=

procedure (value,

base.

Id.

1* This p,.oce.du,.. conv.,.t. an int.,.g..,.

<

bufadl"'. width),

OFFFFFFFFH to an .,';,..,u of ASCII

codes.

Input variables are:

96

97
98
99
101
102
103
104
lOS
lOb
107
108
109
110

2

2

declare value dword.
bufadr pOinter,
(i, J' base, Id, width) bljte,
ch.,,.s based buf.,d,. (1) bute.
do i

3

3
3
3

3
2
2
3

3
3
2
2

valure = integer to be converted,
base = number base to be used for conversion,
Id = leading ch.r.cter to be filled in,
buledr = buffer address of the arra~,
.. idth = .i Ie of a,.,.au. *1

=

1 to .. idth.
J - value mod base;
if J < 10 then cha,.. ( .. idth - i) = J + 30H.
else cha,.s ( .. idth - i) = J + 37H.
value
v.alue j base;
Ig

endJ

i = 0.

do while ch.rs (1) chars (i) - IdJ
i = i + 1;
end;

char.count

m

'O"and

< .. idth

- 1.

width - ii

end jnt.to.asci,
out.word: p'rocedura (w.ptl'.' distance),

111

1* An intege,. at (selecto,. of ... pt,.): (offset of ... pt,. + distance) is p,.;nted
•• ., 4 digit hex.,decimal numb.,..
*1

112

2

decla,.e chars(4) byte.
IIISptr point .... ,

dhtance byte •
.. besed ... pt,. (1) wo,.d.

113
114

2
2

115

2

11b

call intSto.asciC .. (distance). lb. '0'.' I!cha,.s(O).
call ..,.ib(O. I!cha,.s(OI. 4. i!statusll

4);

end outtlalOrdi

..,.ita.int:

p,.ocedu,..(d ...

t).

1* An ;ntege,.· (d .. ) i. p,.inted in hexadecimal (t

= 1)

0,. in decimal (t

a

01. *1

292010-39

Traffic Simulator/Monitor Station Program (Continued)

1-250

intJ
117

2

AP-274

dw

d.cla~e

dwo~d,

chars e 10) byte.
t byte,
118
119
120
121
122
123

2
2
3
3
3
2

124
12:1
126

3
3
3

127

2

if

t then

do;

call intStoSasciCdw. 16, 0, @cherseO), 8»)
call writeCO, C!chat's(S-cha",ScDunt), ch~r'cQunt, @status);
end;

else
do;

12e

call intStoSasciCdw, 10. 0, @charsCO), 10);
call writ.CO, echars(10-charScDunt), char'count,

@.tatus);

end ",,.it •• int;

out'dec'hex:

pracedureCdw);

1* This procedure prints an integer in decimal and hexadecimal.

129

2

130
131
132
133

2
2
2
2

134

2

call writ.tinted"" O)i
call ..riteeo. @e' e'). 2. I!status),
call ..rite.inted ... I),
calfwrite(O. @(/H)'), 2, 8status);
end out_dec.heli

..rite.offset:

135

proceduree"'ptr),

1* This procedure takes a pointer variable.

and prints it in hexadecimal.
136

2

137
138
139
140

2
:2
2
2

141

2

*1

declare dUl dwordJ

converts it to a 82586 type offset.

*1

declare UI'ptr pointer.
til lIIo'rdj

call ",.rit.,CO, @(' at '), 4, @status);
.. = offsete"'ptr),

call DutS",ord(@w, 0);
call ~rite(O, @(/
' ) , 2, @status);
end IIIrite$offset;
IIIrite$addr~ss:

142

procedure Cptr);

1* This procedure takes a pointer variable and prints i t in thr
'selector:offset' format.
*1

143

2

144

2

declare (ptr, ptr$loc) pointer,
III based ptr.loc (2) word;
ptr'loc = I!ptr,

292010-40

Traffic Simulator/Monitor Statlon.Program (Continued)

1-251

inter
145
146
147
148

2
2
2
2

149

2

Ap·274

call
call
call
call

out$word

(@w(I). 0),
Ie': '), 1. @status);
out$word(@w(O). 0),
writeCO, @(' ' ) , 1. @status)i

",riteCO.

end write'address;
print$wds:

150

proc~dure(w'ptr,

no'words);

1* This procedure pr.ints no'words number of words starting at wSptr.

151

2

152
153
154
155
156
157
158
159
160
161

.2
2
3
3
4
4

162

2

declare "'$ptr pointer.
(i, nO'IIIDT'ds) bVtei
if no$words

<>

0 then

do;

call cr$]f,
do i = 0 to no.words - 1;
call outSwordCwSptr, i ) ;
if i = 0 then
call write'Dffse~(w'ptr);
call cr$lf;

4

4
4
3

*1

end;
end;

end pT"intSlllds;

163
1* This procedure prints len number of

164

2

165
166
167
168
169
170
171

2
2
3
3
3
3
2

172

2

173

decla,..e (len, i) bljte,
chars (2) b~te.
st,.Sptr pOinter,
str based str$ptr (1)

b~t.s

starting at strSptr.

*1

b~te,

if len <> 0 then
do i
0 to (len - 1),
call intSto$asciCstrCi), 16, '0', @chars(O),
call writ,,(O. @chars(O). 2. @status),
call ",,.iteCO, @e'
'), 2. @status);

=

2);

end;
call cr$lf,

print$buff:

procedure (ptr.

cnt),

1* This procedure prints cnt number of buffer contents starting at ptr.

174

2

*1

declare ptr painter,
bt based ptr (1) buteo
(i. J) b~te.

cnt aa.ardi
292010-41

Traffic Simulator/Monitor Station Program (Continued)

1-252

inter
175
176
177
178
179
180
181
182
183
184
185
187
188
189

2
2
3
3
4
4
4'
4
4
3
:3
3
:3
2

190
191
192

:3
3
:3

193

2

AP-274

i

-

16 then

sh1"(cnt,

do J -

4) -

Ii

0 to is

call ~rit ••• ddr ••• (ebt(16*J»'
call print.str(lbt(16*J)' 16),
if (J = 20) or (J
40) or (J = 60) or (J
call pause;

=

= 80)

then

end;
i
i + 1;
If cnt-16*i <> 0 then call ~rlte.addre •• (lbt(16*i»,
call print •• tr(ebtlI6*il, cnt-16*i),

=

call ~rlte.addr ••• (lbt(O)I'
call print •• tr(lbt(O), cnt),
end;

end prlnt.buff.

,..ad.jnt:

194

>

if cnt
do;

p'rocedul"e (limit) dl&Jordi

1* This procedure reads integer characters and forms an integer.

integer is bigger than 'limit' Dr an
an .1"1"01" message is p,.inted.
*1
195

2

196
197
198
199
200
201
202
203
205
206
208
210
211
214
215
216
217
218

2
3
3
:3
3
3
3
4
4
4
4
4
4
4
4
4
4
3

219
220

3
3

221
223

4
4

declare (l&Jd. ""h, limit) d\llord.
(i. J • • , dane. he., dover,

Dv.rflo~

If thp
erroT' is encounterred. then

have,.) b"te;

do forever;
call read(l, leSbuf, eo. tactual. @st.tus),
i. II = skip;
hex. done, dove,., hover = falseJ
~d, ~h = 0,
J
char.to.int(c.buf(i)l,
do ~hile J <= 15,
if J > 9 then he. = t,.uei
if not dover then
If ~d > 429496729 then dover
true,
else if (~d
429496729) and (J > 5) then dover
true,
~d = ~d*10 + J'
if not hover then if ~h > OFFFFFFFH then hover = true,
wh = ",h*16 + Ji
i - i + 1;
J = char.to.lnt(c.buf(i»,
end;
If «c.buf(i) <> 'H') and (cSbuf(i) <> 'h') and (c.buf(l) <> ODli) and
(c.buf(i) <> OAH) and (cSbuf(i) <> ' .» or (i = k) then
call ~ri teln(O, I(ODH, OAH, ' II ltPgal character'), 20, .status),
else
do;
i f (c.buf(l) = 'W) or (c.buj>(1l = 'h') then hllx = true;
if he. then

=

=

=

=

292010-42

Traffic Simulator/Monitor Station Program (Continued)

1-253

intJ

AP-274

224
225
227
228
229
230

4
5
5
4
4
4

do.

231

4

call writeCO,

232
233
234
235
236

4
4
4
3
3

call DutSdecShex(limit);

237

2

hove~

if not

<=

and (wh

limit) then return

wh~

end;

else

if not dover and (wd <= limit) ~hen return wd;
call writeinCO, @(ODH, OAH, , The number is too big. '), 25,
(!StktU5) i

It has to be less than ar eq,ual to '),

(!('

3i"
(!StLctU5) ;

call lIJritelnCO.

2

@:status);
==)

'),

20, (!statu-a.);

end read' inti
proc ed ure (wh ere);

1* This procedure puts an address
location 'where'. *1

239

1,

@C' Enter a number

end;

put'address:

238

@('. ' ) ,

end;

call blriteCO,

declare where painter,
(i. J. m, 'err)

t~ped

in hexadecimal to the specified

b~te,

addr based where (I) byte.
240
241
242
243
244
245
246
247
249

2
3
3
3
3
3
4
4
4

250
251
252
254
255
256
257
258
259
260
261
262
263
264
265
266
267

5
5
5
5
5
4
4
4
3
3
4
4
4
4
3
3
3

268

2

do

f01"eVeTi

=

err
false;
call read(!, @cSbuf,
i

eo,' @actual, @status);

= skipi

m = addressSlengthl

do while (m (> 0) and not err.
J = char.to.int(c.buf(i)),
if J
OFFH then err = true.
else
do;
.ddr(m-I)
shlCJ. 4).
J = char.to'int(c'buf(i+l)),
if J D OFFH then err
true,
else addr(m-I) = addr(m-l) or J'

=

=

=

end;

i =
+ 21
m = m - 1;

end;
i f not err then
do;

m = c'buf(i),
if (m
ODH) or (m
,then return;

=

= OAH)

or (m = 'h') or (m

'H") or (m

,

.)

end;

'call ..riteln(O. (I (ODH. OAH. ' Illegal character' h 20. @status),
call "'1'ite(O, @(' Enter an address in Hex
29, .status);

==> ').

end;

end put.address;

292010-43

Traffic Simulator/Monitor Station Program (Continued)

1-254

intJ
269

AP-274

percent:

procedure;

1* This procedure calculates and prints a network percent load generated
blJ this sta'tion.
The eq,uatian used in this procedure was obtained
from actual measurements. *1

270

2

271

2
2

272
274
275

2

2

declare i word,
(J. k) d.. ord.
pcent (3) b~te,

J = (tbd.act.count and 3FFFH)*B,
if not ad.loc then k
(2*addres •• length + 2 + cre + preamble)*B,
else k = (ere + preamble>*Si
if dela~ <> 0 then

=

.IF NOT SBCIB651
276

lo .. «1000*(J + k»/(lB05 + k + 5*double(delay) + J»'
.ELSE
i

= lo .. «1000*(J + k»/(2021 + k + 5*double(delay) + J)l,

.ENDIF
277

2

else

.IF NOT SBCIB651
lo .. «1000*(J + k»/(lBI0 + k + J»'
.ELSE

= Io .. «1000*(J + k»/(2026 + k + J»l
.ENDIF
27B
279
2BO
2Bl
2B2

2
2
2
2
2

2B3

2

2B4

call jnt.toSasci(i,

10, 0, @pcentCO), 3);
call "'Tite(O, @pcentCO), 2, estatus);
call w... iteCO, @:('. '), 1. @status)j
call write(O. @pcent(2). 1. @status)'
call wT'itelnCO, (!( I X'), 2, (lstatus);

end percent;

print.net .. ork.addr:

procedure (ptr),

1* This station's address is printed with its least signlficant bit
in the most right position.
*1

2B5

2

declare ptr pOinter,
addr based ptr (1)
char (6) b~te.
i

b~te.

b~te,

292010-44

Traffic Simulator/Monitor Station Program (Continued)

1-255

inter
28b
287
288
289

2
3
3
2

290

2

291

AP-274

= 1 to address.length;
chaT(i-l) = addrCaddress$Ienqth-i);

do i
end;

call prinUstr CC!char CO). addressSlength),
end

print'net~ork'addr;

print'parameters:

procedure;

1* This procedure prints transmission parameters. *1
292

2

dec lare

1&1

dword,

stgs Cb)
293
294
295
29b
297
298
299
300
301
302
303
304
305

2
2

b~te,

call writeCO.

C!e' Destination Address:

'), 22, (!status),

2

if not adSloc then
call printSnetworkSaddrC@transmit.destSadrCO»,

2

else

2

2
2

2
2
2

2
2
2

call printSnetworkSaddrC@txSbufferCO»,
if nat ad'loc then

w = Ctbd.actScount and 3FFFH) + addressSlength
else w Q Ctbd.actScount and 3FFFH) + cre,

*

2 + 2 + erc,

call writ.CO. @(' Frame Length: '), 15, .status);
call write.lnth." 0);
call writelnCO. @C' b~te5·>. b. C!status),
call 1I.IriteCO, @(' Time InteT'val between Transmit Frames:
if delay <> 0 then
do;

'),

40, @status);

SIF NOT SBCIBb51
30b

- 1)

*

5,

+ CdoubleCdelay> - 1)

*

5,

w = IBIO +

3

CdoubleCdela~)

SEI.SE
w

= 202b

SENDIF
307
308
309
310
311
312
313
314
315

3
3
3
4
4
4
4
4
3

316
317
31B
319
320
321
322

4
4
4
4
4
3
2

call 1nt.to'asciCw.

if w
do,

>=

10, 0,

@stgs. 6);

10000 then

call lII",iteCO, (lstg.COh 2, @status);
call w1'iteCO, IC'. '), 1, .status);

call writeCO. @stgs(2), 2, @status),
call writelnCO, C!C' miliseconds'),

12, @status)J

endJ
else

do,
call writeCO. @stgsIO), 5. @status),
call writeCO. @C'. 'I. 1. @status),
call writeCO. @stgs(5), 1. C!status),
call IaJriteln(O,

(!('

micl'oseconds'),

13, @status);

end;
end;
.lse

292010-45

Traffic Simulator/Monitor Station Program (Continued)

1-256

inter

AP-274

$IF NOT SBC1B651
call writeln(O.

(!('

159.4 miCl'DSeConds'),

19.

C!status);

@('

172. B micTDseconds'),

19.

@status)i

$ELSE
call writeln(O.

$ENDIF
323

2

call writeCO.

324
325
326
32B
3:Z9

2
2
2
2
2

call percent.;

330

2

end print.parameters;

@('

Netlllork Percent Load generated blJ this station:

'),

49.

@:statu5);

call ul'rite(O, @(' Transmit Frame Terminal Count: '), 32. @status)i
if stop then cal} w1'iteSint(stapScount, dhex);
else call IdriteCO. @('Not Defined'), 11, C!status)j
call crSl.,;

printf,scb:

331

procaduTei

1* print. the SeB *1

332
333

2
2

334

2

335

call "'TitelnCO. (!(ODH. OAH, '*** System Control Block ***'), 30, @status);
call printS.... ds«!scb. status, 8);
end pTintSscbJ

waitSscb:

proceduT"e;

1* This pTocedure provids a wait loop for the
become cleared.
*1

336

2

337
33B
. 339
340
341
342
343
344
345
346

2
2
3
3
2
2
3
3
3
3

347

2

34B

sen command word to

dec lare i word;
i = 0;
do while (scb. cmd
i

=i

<:>

0) and (i

<

BOOOH);

+ 1;

end;
if scb. cmd <:> 0 then
do;
call ,."ite(O, @(ODH, OAH,
e.l1 blJ'ite$intCi, 0);
call cr$lf;
end;

' Wait Time

').

15,

@status);

end waitSseb;
startStimerO:

procedure.

1* B01B6 timerO is sta"ted.

*1

292010-46

Traffic Simulator/Monitor Station Program (Continued)

1-257

inter
349

2

350

2

AP.-274

output (TIMEROSCTL)

OEOOOH,

isr: procedure interrupt INTSTYPES586 reentrant.

351

1* interrupt .ervice routine for 82586 interrupt *1

352

2

declare

i

byte.

1* Enable 82586 Interrupt *1

SIF SBC18651
output (PICSEDISI30)

D

EDISCMDOSI30 •

• nab lei

SEL.SE
353
354

2

2

output· (PICSEOlSI86) .. EOISCMDOSIB6.
enolble.
SENDIF
1* Frame Received Interrupt has the highest priority *1

355
356'
357
358
359
360
361
362
363
364
365
367
368
369

2
2
3
3
3
3
3
3
4
4
4
4
3
3

370
371
372
373
374
375
376
377
378
379
380
382

2
2
3
3
3
3
3
3
3
4
4
4

i ' (scb. status and 4000H)

4000H then

do;

disabh.
sob. cmd .. 4000H.
output (CASPORT) = CA.
c.l1 .. aitSscb.
i' rfd(currentS'r.me), status D OAOOOH then
do.
receiv •• count = receive.count + 1;
current.frame = current.frame + 1;
if CUTTent.fr.me • 5 then current.frame

0;

endJ

return;
endJ

i' (scb. status and 2000H)

2000H then

do.
disable.
scb. cmd .. 2000H.
output(CASPORT) - CA.
call ..aitSscb.
enable.
if (transmit. status and OAOOOH) = OAOOOH then
do;

caunt = count + 1;
if (stop and (count = stopScount»

then return.

e1.e'

do.

292010-47

Tra.ffic Simul~tor/Monltor Station Program (Continued)

1-258

inter
3B3
3B4
3B5
3B6
3B7
3BB
3B9
390
391
392

Ap·274

transmit. status = 0;
if dela~ = 0 then

:I

5
5
6
6
6
6
6
6
5

do;

disable;
scb. cmd = 0100H.
output(CASPORT)
call waitSscbi
retuTni

CA.

end;

else
do;

393
394
395
396
397
39B
399
400
401
402
403
404
405
406
407
40B
409
410
411
412
'413
414
415
416
417
41B
419
420
421
422
423
424
425
426
427
42B
429
430
431
432
433
434
435
436
437
43B

6
6
6
5
4
3
3
4
4
4
4
4
4
4
3
3
4
4
4
4
4
4
4
4
3
3
4
4
4
4
4
4
4
4
3
3
4
4
4
4
4
4
4
4
3
2

call startStim.rO.
end;

end;
end;
if (transmit. status and 0020H)
0020H then
do;
transmit. status = 0;
disable,
scb.cmd
0100H.
output (CASPORT) = CA,
call waitSscbi
return;
end.
if (transmit. status and 0400H)
0400H then
do;
call ,.rrite(O, @(ODH, ' No Carrier Sense! I,

=

=

=

transmit. status

=

disable;
scb. cmd
0100H.
output (CASPORT)
call ",aitSscb.
return;

=

ODH)' 20, @statu!;.);

OJ

= CA.

end;
if (transmit. status and 0200H) = 0200H then
do;

call "'rite(O. @(ODH.
transmit. status = OJ
disable;

'Lost Cle .. r to Send! '. ODH). 22. @status).

=

scb. cmd
0100H.
output (CASPORT) = CA.
call waitSscbi
return;
end;

if (transmit. status and 0100H) = 0100H then

do.
call writeCO,

@(ODH,

transmit. status

= 0;

disable;
scb. cmd = 0100H.
output (CASPORT)
call wai'tSscbi

'DMA Underl"un! I,

ODH),

16, @status)j

= CA.

t"etu'rn;

end;
end;

if (scb. status and BOOOH)

BOOOH then
292010-48

Traffic Simulator/Monitor Station Program (Continued)

1-259

AP·274

439
440
441
442
443
444
445
446
447
44e
449
450
,451

2

do,

3
3
2

end;
i f Cscb.status

2

do;

disable,
scb. cmd = BOOOH,
Dutput CCA.PORT)
call .... U.scb'

3
3
3

= CA,

and 1000H) .. 1000H than

disable,
scb. cmd a 1000H,
output CCA.PORT) - CA,
call ..ait.ub,
call ..rUaCO. ICODH• • Receive Unit became not read,. '. ODH). 33.

3

3
3

3
3

·.&tatu~)'

and,

452

3

453
454
455
456
457
45e
459
460
461
462
463
464
465
466

2
3
3
4
'4
4
4
4
4
4
4

3

end,

467

2

end isr,

2

3

46e

i f rasat than

do,

.if
do,

isc~bus,

and,

then

call .. rit.lnCO. ICODH. OAH. 'Re •• t faUed. '). 16. 'status),
disable, .
scb. cmd - 008OH,
output CCA.PORT) • CA,
call .... i t •• cb'
output CCA.PORT) - CA,
c .. 11 writ.1nCO. IC' Soft... r. Re.et E •• cuted!'). 25. Istatus),

el •• r ••• t .".1 •• ,

tx.i.r: procedure interrupt INT.TYPE.TIMERO,
1* interrupt survic. routine for 80186 timer interrupt_I

469
470
471

:I

2
:I

scb. cmd - OIOOH,
outputCCA.PORT) - CA,
caU ..Bi t'scb,
.IF SBCle651
outputCPIC.EOI.130) - EOIfCMD4.130.
en .. ble,
outputCPIC.EOI.l86) = EOI.CMDO.le6,
, .ELSE

472

:I

473

2

outputCPIC.EOI.le6)

a

EOI.CMD4.1e6,

fEND IF
end tx.isY"
292010-49

Traffic Simulator/Monitor Station Program (Continued)

1·260

inter

AP-274

SIF SBCI8b51
i5r$7:

procedure interrupt INT$7i

1* The 80130 generates an interrupt 7 if the original lnterrupt 15 not

active

an~

more when the first interrupt acknowledge is received. *1

call writeCQ,

@(ODH,""lnterrupt 7',

OOH),

13, @status);

end i sr$7i

SENDIF
474
475

1

2

47B
479

2
2
2
2

4BO

:1

47b

477

read.byte: procedure (k) blJtei
dec lare k word;
call writeCO,

OAH,

call writeCO, @(' ==)
return readSint(OFFH);

' Enter blJte '),

14, @status);

'),

5, @status);

end read$byte;

1nit.lab$timerO:

4BI

(!(ODH,

call QutSdecShe,(k),

procedure;

1* This procedure initializes the 80186 timer O.

482

2

dec lare i

*1

byte;

SIF SBCIBb51
Qutput(INT$CTLSTIMERO) = B,
call writeCO,

@(ODH,

OAH,

delay = readSfnt(OFFFFH),
if (delay < 100) and (delay

Enter a delay count ==> '), 27, @status)i

<> 0) then

do;
call cr$If;
call crSl fj

call loopSchar(35,

call Ulrite(O,

@('

'*');

WARNING '), 9, @.tatu.),

call 100p$char(35, '*')i
call writeln(O, @(ODH, OAH, 'A delalj count between 0 and 100 malj be verlj "
~dangerous when this station starts'), 80, @status);
call writeln(O, @('to receive many frames separated onl\1 by the
'IFS period (9. b microseconds). '), 75, @status);
call writeln(O. (!( 'If this station never receives a frame. then "
'ignoTe this warning. '), 65, @status);
call loop$char(79, '*');
\
end;

Qutput(MAXSCDUNTSA)
call c1'$lf;

Qutput(PICSMASKS1Bb)

= delay,
= 3EH,
292010-50

Traffic Simulator/Monitor Station Program (Continued)

1-261

inter

AP-274

$EISE
483
484
485
48b
487
488

2
2
2
2
2
2

output(INT$CTL$TIMERO) = OCH;
call WT'lte(O, @(ODH, OAH, ' Enter a delalj count
delay = read$.nt(OFFFFH);
output (MAX$COUNT$A) = delay;

==> '),

27, @statub);

call cr.lf;

out put(PIC$MASK$18b), = ENABLE$58b$18b;
$ENDIF

489

2

end initS1B6$timerOi

490
491

1
,2·

setup.ia'parameters:
declare i byte;

492

2

call w,..iteCO, @(ODH, OAH,

493
494
495
49b
497

2
2
3
3
2

if yes then
do i = 0 to address$length - 1;
ia$setup. ia$address(!)
!nput(BOARO$ADDRESS$BASE + 10 - 2

498

3

499
500

3
3

501

2

end setup.is'parameters;

502
503

1
2

setup.me.parameters: procedure;
declaT"~ (J,
k, done) btjtei

504
505

2
2

J = 0;
call writelnCO, (!(ODH, OAH,

50b
507

2
2

508
509
510
511
512
513
514
515
51b

2
3
3
4
4
4
4
4
5

done = false;
call writeCO, @(' Would lJou like to enter a Multicast Address?',
, fY or N) ==> '), 59, @status);
do ~hile not done;
if yes then

517
518
519

5
5
4

520

5

procedure;
Configure the 58b ~ith the pre~ired'
, board address ==> '), 57, @5tatu~)j

*

i);

end;

else
do.
call writeCO,

@(OOH, OAH, ' Enter this station"s address',
I
in Hex =~> '),43, @statu~)J
call put$address(@ia$setup. ia$address(O»;
end;

do;

I

You can enter up to 8 Multicast Addresses. '),
45, @status).

k = J * address$length;
J = J + 1;
call cr$lf.
i f J = 9 then
do;
call write(O. @(' You

done

=

call

~rite(O,

alread~

entered B Multicast addresses.
43, @!.tatus);

I),

true;

end;
else
do.
@(' Enter a Multicast Address

==> '),

31, @status);
292010-51

Traffic Simulator/Monitor Station Program (Continued)

1-262

inter

AP-274

call putSaddressC@mcSsetup.mcSaddressCk»;

521
522

5
5

523
524
525
526
527
529
530
531
532
533

5
4
3
3
2
2
2
2
2
2

534

2

end setup.me.parameters;

535
536

1
2

setup'configure'parameters: procedure;

537
538
539
540
541
542
543
544
545
546
547
548
549

2
2
2
2
2
2
2
2
2
2
2
2
2

cQnfigur •. b~t.'cnt = l1i
configure. in'o(O)
8;
con.igure. infoCl)
0;
configure. info(2)
26H;
configure. info(3)
Oi
configure. in'o(4) = 96;
configure. info(5)
0;
configure. in'o(6) = OF2Hi
configure. in'o(7)
OJ
configure. info(8)
0;
configure. in'o(9) = 64;
J = 0;
call \IITiteCO, @(ODH, OAH.
, values.', ODH, OAH,

550
551
552

2
3
4

do urhile 'Ies;
do .. hile J = 0;
. call writ.CO. @CODH. OAH • • Enter byte number C1 - 11)

553
554
555
556
557
559
560
561

4
4
4
4
3
3
3
3

562
563
564
565
567
568
571

3
2
2
2
2
2
2

573

2

call writ.CO,

(!(ODH,

OAH,

'More Multicast Addresses?',
,

(V Dr N) ==)

'),

42,

@status);

endi

end;

t,.uei

else don.
end;

if J = 9 then
= J - Ii
me'caunt = address'length * Ji
mc$setup.mcSbvt.Scaunt = me'count;
call '-I",iteCO,

@(ODH.

DAH,

You entered

I

'),

15.

@status);

call ..riteSintC J. 0);
call lIIT"ltelnCO.

declare Ck.

J)

C!(

I

Multicast Addressees>' '),

23.

@status);

byte;

=

Configure command is set up for default',
' Do you urant to change an" bytes?',
, (Y or N) ==:> '), 99, @status);

I

==>

'I. 34.

@status)i

J = r.adSint(11);
if J = 0 then
call ..riteCO. @CODH. OAH • • lllegal byte number').

end;
if J

=1

J = Oi
call ..,rite(O, @(ODH, OAH,
end;

preamble

22. @status);

=

then configure. byteScnt
readSbyteCJ);
else configure. infoCJ - 2) = readSbyteCJ);

=-

shiel,

=

Any more bytes? (Y ar N) =="<>

shr«canfigure. infD (2) and 30H),

addressSlength
configure. info(2) and 07H;
if addressSlength
7 then addressSlength = 0.
adSloc = shrC Cconfigure. info(2) and 08H). 3);
if shrCCconfigure. info(7) and 20H). 5) then crc
if shr( (configure. info(7) and 10H), 4) then cre

i),

3;'!,
(!status)

j

4)+1);

=

2;

else crc

4.

0;

end setup'cDnfigure'parameters;
292010-52

Traffic Simulator/Monitor Station Program (Continued)

1-263

intJ
574
575

1
2

576
577
578
579
580
581

2
3
3
3
3
4

AP-274

setupSt x'parameter 5:
declaT"1!'

(511e.

i)

prot edure,

UJordi

do forever;
no.transmission = false;
transmit. bdSoffset = offset (@tbd. act'count);
if not ad'loc then
do;
call IIJriteCO,
I

call

@eODH,

OAH,

Enter a destination address in Hex

==> '),

42, @statu!.);

put$add~e5s(@t~ansmit, dest$ad~(O»,

582
583
584

4
4
3

585
586
587
588
589
590
591

3
3'
3
4
4
4
3

call crSlfl
if not ad$loc then
do;

592
593
594
595
596
597
598
599
600
601
602
603

3
3
3
3
3
4
4
4
4
5
5
4

call writeCO, @(/ Enter a number
size = readSint('1518);

604

4

call ..~iteln(O,
@(ODH, OAH, ' Transmit Data is continuous numbers (0, 1, 2, 3, I,
) '), 57, @sta1.us),
call ..~ite(O, @(' Change an~ data bVt ... ? (V or N) ==> '). 'j't,

605
606

4
5

do while yes;
call .. ~ite(O, @(ODH. OAH.

607
608
609
610
611
612
613
614

5,
5
5
5
5
5
5
5

615
616
617

5
4
3

end;
else

618

3

call

end;
else call writelnCO,

@(/

82586 i5 configured to pick up OA.

and TVPE

call IIJrite(O,
t~ansmit,

tvpe

end;
call \.fritelnCO,

(!(ODH.

'~om

OAH,

TX

buf'.~.

' Ente'r TYPE

IA. '.

'), 64, @status),

==> '),.

18,

@status);

='~ead$int(OFFFFH),

(!(ODH.

OAH,' How manlj b\ltes of transmit data?'),

3S,

~sti:ltus)

==> '),

20,

;

@status);

tbd.act$count = size o~ eOOOH,
if size <> 0 then
do,
tbd. link$offset = OFFFFH,
tbd,adO = offset (@t'$buffe~(d»,
tbd. adl = 0,
do i = 0 to 1,517,
tx$bufferCi) = il
endl

et.1.b1.ub);

' Enter a b~te numbe~ ==> ').
2,./,

i

-

call
call
call
call
call

@status);

readSint(size);
..~ite(O, @(ODH, OAH. 'Bvte '). e, @status),
out$dec$he.(i),
writeCO, @(' cury.ently contains '), 20, @status);
out$dec$he.(t.$buffe~(i»,

writeCO,

@('. '),

1, @status);

t.$buffe~(i) = ~ead$b~te(i)'
call .. ~ite(O. @(ODH. OAH. ' AnV

mD~e

bytes?

(y o~

N) ==> ').
32, es1.atus),

end;
t~ansmit.

bd$offset - OFFFFH,

c~$lf,

292010-53

Traffic Simulator/Monitor Station Program (Continued)

1-264

inter

AP-274

619
620

3
3

call init$186.time~Oi
call l.l'riteCO. @(ODH, OAH,

621
622
623
624

3
3
4
4

if yes then
do;

625
626
627
628
629
630
631

4
4
3
3
3
3
3

632
634

3
3

635

2

end setupStxSparameters;

636
637

1
2

loop.char: procedure (i.
declare (i, J. k) blJtei

638
639
640

2
3
3

641

2

end loopSchari

643

2

declare

644
645
646
647

2
2
2
2

648
649
650
651
652
653
654
655

2
2
2
2
2
2
2
2

' Setup a transmit terminal count?',

(Y or N)

==> '),

49. @status)l

stop = true;
call un"ite (0. @(ODH. OAH.

' Enter a transmit',
, terminal count ==~ '),
stop'count = Tead'int(OFFFFFFFFH),

39, @status);

end;

else stop = false;
call cT'I',
call crSlfi

call printSparameters;
call wTite(O. @(ODH. OAH.

' Good enough? (V DT N) ==) '). 29,
@stat.U5)';

642

if

~e5

end;

do k

= 1 to ii
call u..rite(O.

init:

2
2

J)i

@J'

I.

@status);

end;

procedure;
i

byte;

call
call
call
call

crSlf;
loop'chaT(13. OAH),
loop'chaT( 15. ' '),
wTiteln(O, @('TRAFFIC SIMULATOR AND MONITOR'.
, STATION PROGRAM '). ,46. @status),
call loop'chaT(7, OAH),
Initialization begun'), 23, @status);
call wTiteln(O. @(ODH. OAH,
call cr.lf.
reset = true;
cUT'cb'offset
OFFFFH,
Dutput(ESI'PORT) - NO.LOOPBACK,
output(ESISPORT)
LOOPBACK,
dhex = false;

=

=

1* set up

656
657

then return;

inte~~upt

logic *1

call set'inteTTupt '), 20, 
enff initi

procedure;

727
728

2
2

call writeln(O, @(ODH,
call ",riteln(O, (!(ODH,

OAH,
OAH,

Commands are: '),
5 - Setup CD

16, @status);
D - Di'splay "FD/CO'I,

729

2

call ",riteln(O, (!(' P - Print SCD

C - SCD Control CMD'I,

730

2

call ",riteln(O,

N - ESI Loopback Uff'I,

45,

@!!:.Latus)i
~~,

@st.atuS)i

(!(' L - ESI Loopback On

731

2

call wrlteln(O, @(' A - Toggle Number Base'), 23,

732
733
734

2
2
2.

call wl'ite'lnCO,
call writelnCO,
call writelnCO,

735

2

end pT'int$helpi

736
737

1
2

enterSscb$cmd: procedure;
declare i btjtei

@(/
@(/

(!("

45,

Z - Clear Tx Frame Counter'), 27, @status),
Y - Clear Rx Frame Counter'), ~7, C!$Jtatus);
E - Exit t!J Continuous Mode'), 28, @status),

".

1* enter a command into the SCD *1
738
739
740
741
742

2
2
2
3
3

743
744
745
746
747
748
749
750
751

3
3
4
4
4
4
4
3
2

752
754
755
756
757
759
760
761
762
763
764

2
2
2
2
2
2
2
2
2
2
2

call cr$if;
if 5cb.cmd <> 0 then
do;
call wl'itelnCO, @(' sea command lIIord is nat cleared'), 32, (tstatus);
call ",rite(O. (!(' Tru a Channel Attention? (V or NI
'I.
39, @!.tatus)i

==>

output(CASPORTI a CA;
call writ.lnCO, @e' Issued channel attention'),
call crSlf;
1"etU1"n;

25. @status);

end;
end;
call

w~ite(O,

@(' Do

~ou

want to ente1"

an~

SeD commands? (Y 01" N)
53.

if not

~e

•. then

==)

@statu~

'),

I;

~&tu,.n;

call ..,~ite(O, @(ODH, OAH, ' Ente~ cue ==:> "), '17. @.tatus);
1
raadSint(4l,
scb. cmd
scb. cmd or shlCdoubleCil, 81,
if i = 1 then scb.cblSoffset
curScbSoffset;
call ..,~it.(O, @(ODH. OAH, ' Ente~ RES bit ==> '), 21, @status);
i = ~ead.b i t;
5cb. cmd = scb. cmd or shl(i, 7)i
tall ",rite(O. @(ODH. OAH. 'Enter RUC
'I. 17. @st"tusl,
i = ~ead.int(4);
scb. cmd = scb. cmd o~ shl(i, 4);

=

=

=

==>

292010-57

Traffic Simulator/Monitor Station Program (Continued)

1-268

intJ
765

2

766
767
76B
769

2
2
2
2

770

2

AP-274

if «(scb. cbl.offset = offset (@transmit. statusII
and «scb. cmd and 0100HI
0100HI I Dr «scb. cmd and 0010HI
OOIOHI I
and not «scb. cmd and OOBOHI
OOBOHI
th.n goback = 1;
call lIIritelnCO, (teODH. OAH, I Issued Channel Attention '), 27. @statlls)'
call cr.H,
output(CA$PORTI = CA,

=

end enterSscbScmdi
print.t~peShelp:

771

=

=

call
call
call
call
call
call

procedure;

writelnCO. @(ODH.
writelnCO, @( • N
IIIritelnCQ. @(' C
writeinCO, @(' T
UJriteinCO, @( , D
writeln(O. @(' H

772
773
774
775
776
777

2
2
2
2
2
2

77B

2

end

779
7BO

1
2

setupScb: procedure;
declare Ct, valid) byte;

7Bl
7B2
7B3

2
2
3

7B4
7B5

3
3

7B6

3

7B7
7BB
7B9
790
791
792
793
794
795
796
797
79B
799
BOO
BOI
B02
B03
B04
B05

3
3
3
3
2
2
3
3
3
3
3
2
2
3
3
3
3
3
3

--

OAH. OAH. 'Command block t~pe: • I. 22. @statuf.);
IA Setup' I. 35. @statu5)i
Nap
I
Configure
M - MA Setup' I. 35, @statu~) ,
30, @statu5);
TDR'I.
Transmit
R
Dump Status ') I 3B. @statu5)j
Diagnose
S
Print this message I), 23. @statusl,

-

printSt~pe$help,

valid = false;
do lIIhile not valid;
call wT'iteCO. @(OOH,
t

=

read$char;
<> 'H'I
(t <> 'N')
(t <> 'D')
(t <> ' I')
(t <> 'S')
call write(O,
i f (t

OAH,

J

Enter command block type (H for',
, help) ==) '), 45, @status)i

and ( t <> 'h'l and (t .:> 'T'I
and (t <> In' ) and (t <> 'R'I
and (t <> 'd ' I and (t <> 'e' )
and (t <> ' i ') and (t <> 'M')
and (t <> 's ') then
, Illegal command
@(ODH. OAH.

and (t ..::> ' t ' l
and (t <> 'T' ')
and (t <> 'e ')
and (t <> 'm')
block

t~pe')

and
and
and
and

• 29,
~&1.iJ1.UE»i

else
if ( t

=

'H'I Dr

else valid

=

(t

'h') then call

printSt~peShelp,

t~ue;

end;
if (t = 'N') o~ (t = 'n') then
do;
curScbSoffset = offset (@nop. status),
nap. status = 0;
nap. cmd
BOOOH,
nap. linkSoffset = OFFFFH,
end;
if (t = ' 1') D~ (t = ' i ') then

=

dOi

= offset (@ia$setup. status);
iaSsetup. status = 0;
iaSsetup. cmd
BOOIH,
iaSsetup. link.offset
OFFFFH,

cu~Scb$affset

=

call

=

setup$ia$pa~amete~s;

end;

292010-58

Traffic Simulator/Monitor Station Program (Continued)

1-269

AP-274

if (t = 'e')

813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852

2
2
3
3
3
3
3
3
2
2
3
3
3
3
3
3
2
2
3
3
3
3
3
3
2
2
3
3
3
3
3
3
2
2
3
3
3
3
3
3
2
2
3
3
3
3
3

853

2

end setupSCbi

854
855

1
2

display.command.block:
declare (i. J) byte.
"'h pOinter,
5.1 aelector,

806
807
808
809
810
811
812

01'

= 'e') then

(t

do;

cur$cbSoffset = offset  '). 46, @status);
if yes then
do.
ca 11 cr$lf;
call writeln(O, @(' Transmit Buffer: '), 17, @status)j
UI = tbd.act$count and 3FFFH.
call print$buff(@tx$buffer(O). "'),
end;
end;
end;
if cur$cb$of'set = offset (@iaSsetup. status) then
do;
call write(O. @('---IA Setup Command Block---'), 28. @status);
call p,.intSwds (@iaSsetup. status, b);
end;
if curScbSoffset = offset (@configure. status) then
d OJ

call write(O. @('---Configure Command Block---'), 29. @status);
call print$wds(@configure. status. 9);
end;

if cur$cb$of'set

= of'set

(@mc$setup. status) then

do;

call write(O. @('---MC Setup Command Block---'). 28. @status)i
i = 4 + mc$count/2;
292010-60

Traffic Simulator/Monitor Station Program (Continued)

1-271

Ap·274

913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
92"
930
931
932
933
934

3
3
4
4
4
4
4
3
3
2
2
3
3
3
3
4
4
4
4
5

if mc.count > 24 then
do;

call printSwdsC@mc$setup. status,

16»)

call pause;
i = i - 16.

call print$wds(@mc$setup.mcSaddress(S),

i)j

end;

else call print$wds(@mcSsetup. statusJ"

i)i

endi

if cur.cb.offset = offset (@dump, status) then
do;
call wTite(O, @( '---Dump Status Command Block---'), 31, @status);
call print$wds(@dump. status, 4);
if dump, status = OAOOOH then

do.
call laIriteln(O,

@(ODH,

OAH,

' Dump Status Results'),

22,

@st.atus)

call writeSoffset(@dump$area(O»i
call CT"Slfi

= 0 to 9;
call pl'intSstT«(!dumpSarea(16*i),
end;
call print'str(@dumpSarea<160). 10);
call crSlfi
do i

5

4

q35

4

'>'36
937

4
3

938

2

end display'command$block;

939
940

1
2

displav$receiveSarea: procedure;
declare (i, k, J, 1) bvte,
chars(4) byte;

941
942
943
944

2
2
2
3

945
946
947
948
949
950

3
3,
2
2
3
4

95:

4

953
954
955
956
957

4
4
3
3
2

16),

end;
end;

call write]n(O, C!(ODH, OAH, ' Frame Descriptors: '), 21, @status);
if ad!U oc then
do;
call wrlhln(O. @(OCH. OAH • • CA. SA. and TYPE are In buffer, '. OIJB.
OAtH, 36, @!.tBttlS);
J = 3;
end;
el5e J • address'length ~ 4;
do k = 0 to J;
do I
0 to 4;
call outSword(@rfd(l)' status. k);
i f k = 0 then call wrlte'offset«!rfd(i), statu.);
else call 100pSchar(IO• • '),

=

end;

call cr.lf;
end;

call writelnCO,

.(ODH,

OAH,

OAH,

' Receive Buffer Descripto1"'s: '),

~J,

tSt.£ttU5) ,;

958
959
960
961
963
964

2

3
4
4
4
4

do k = 0 to 4;
do i = 0 to 4,
call out'word(@rbd(i),act'count. k),
if k = 0 then call writeSoff.et(@r'bd(!),act'cou"t,.
else call loopSchar(10, ' ');
end;

292010-61

Traffic Simulator/Monitor Station Program (Continued)

1-272

intJ

AP-274

965
966
967

3
3
2

~l.t-

2
2
2
3
3
3

~o1Il

J. crSl fi

end;

call I.&Irite(Q, @(ODH,

OAH,

OAH,

I

Displa\l th,. reCtHve',
(Y ar N) ==> ' l ,

bU4l'E-:";i.f
I

970
971
972
973
974
q7~

'J
3

977
979

3
3

990
991

\IRS

=

k = rbd(i).attStount and 3FFF~,
call print'buffCC!l"hll.e(ii. DufferCO),
call P8US":

d i sp Ialj'cbS,.pa:
det lare ~ blJte;

2

2
2

k)i

endi

1

993

(~d.at.us);

call ..,,.itelnCO, @(ODH, OAH.
Receive Bu-ffers. ')' 19, @status),
do i
n t ... .;,
call writeCO, @(ODH. DAH.
Receive Buffer '), 18. @c;,t::~.,,"·'
call IIIrit.$intCi. O)i
call writ.InCO, @(' : ' ) , 2. @status':

end displavSreceive$area,

2

46.

then return;

2

992
.'':;':

if not

proCedU,.ei

callI t:.IT'iteCO,

@(OOH,

OAH,

Command Block or Receive Area':'

,~

98:>
996
997
989
989
.L=-t

3
3
3
2

992

2

993
994

1
2

995

2
:;:

gobac k

.2

tall cl'Slf;
i f (b <> 'W) and (b <> 'h ') and ( b <> '9' ) and ( b (> 's' ) and
(b <> 'D') and (b '-- 'd' ) and ( b <> 'P') and (b .;." 'p
.'"d
10
'r:') and (b <> 'c ') and (b <:> 'E') and (b <> 'e ') and
(b <> 'L') and (b <> ' I ' ) and (b <> 'N') .. nd (b <> 'n' ) and
(b <> 'Z' ) and (b c.::.- '2'1) and ( b <> 'V') and ( b <> '\.I') and
(b <> 'A') and (b <> 'a' ) then
tall I&I"ite(O. (!(' Illegal command' ), 16, @status);
i f (b = 'W) or (b = 'h' ) then tall print"help,
It ,b '= 'A') or (b = 'a') then

-.-:Jt.,

997
999

3

2

2

01

"'

;=> '),

47. @statu!."
= read'chari
do while (i <:> 'R') and (i ...::... '1"') and (i (> 'C') ancJ (i <) 'c')J
call I&IritelnCO, @CODH, OAH, ' :i:ll~gal command'), 18, @status',
call write(Q, @C' Enter R or C ==> '), 18, @:status);
i = read$chari
i

enu,

if (i = 'R'I or (i :II 'r') then call Glspla1J$receive$iireai
else call di5pla~'command$block;

FoT'!'''":essScmd:

declare \",
b

procedure;

i \ blJte;

= 0,
= readSchar;

--

999
1000
1002
1003
11)04

,,:C,

2
2
2
2
2

.,

1006

3

1007
1009

3
2

if dhlu

do;

t.hen

=

dh.x
false;
call writeCO.

@(,'

Counters are displayed in decimal, '), 3!:J.

end;
@.1se
292010-62

Traffic Simulator/Monitor Station Program (Continued)

1-273

Ap·274

do;

1009
1010
1011
'012

3
3

dhex

=

truei

call wTite(O,

@('

CaunteT!. aT'e displaved in heAcide,=i",al. '), :39,
~ •.

3
2

end;
if (b = 'L') or (b = '1') then
do;

~01':

"!

1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1035
1037
1039
1041
1043

:;

3
3
"2
2
3
3
3
2
2
3
3
3
2
2
3
3
3
3
2
2
2
2
2
2

1044

2

end process$c:md.

1045
1046

I

2

getout: procedure;
declare b byte,

1047
1048
1049

2
2
2

b = read'char,

1050
1051
1052
1053
1054
1055
1056
1058

2
3
3
4
4
4
4
4

do forav.,..;
i f cst. then
do,
disable;
call process$cmd,

: , ' 'Ir ' ;

=

Qutput(ESI$PORT)
LOOPDACK.
call writeCO, @(' ESI is in Loopback Mode. '), 25, @status);
end;
if (b =

'N'~

DT"

(b

=

'n')

then

output(ESI$PORT) = NO$LOOPDACK.
call lIIT'iteCO.

end;

if (b
do;

=

'Z') or (b

count = 0;
call writeCO,
end;

if (b

=

@('

ESI

=

'I')

@('

is NOT in Loopback Mode. '), ·29.

@status);

then

Transmit Frame Counter is cleared. '), 35, estatus);

'V') Dr (b = '':1') then

do;

receive.count = 0;
scb.aln'errs, SCb.Tsc'eTl"S, scb. avrn.errs = 0;
call writeCO, @(' Receive Frame Counter is cleared. '), 34, @status);

SCb.CTc'errs,
end;

if (b

'e') or
'S') or
if (b s 'Pi) or
(b
'0· ) or
if
i f (b = 'E') or
call cr$U.

i f (b

goback = 0,
call .. rite(O.

=

Ie I )
(b
(b
's' )
(b = 'p' )
(b
'd ' )
(b
'e' )"

@(ODH, OAH.

then
then
then
then
then

call enteT"'scbScmd;
call setup$cb,
call print$scb.
"call display$cb$rpa,
1,
gob.ck

=

' Entu"command (H for help) ==:> 'I,

34,
@statu5)J

_nab lei
if gabac. then returni
call .. rite(O, (i!(ODH, OAH,

' Enter command (H foT' help)

==> ').

34.

@!JtiJtU5)J

1059
1060

3

1061

2

4

end;
end,

end ,.tout.

292010-63

Traffic Simulator/Monitor Station Program (Continued)

1-274

inter

AP-274

1062
1063

2

1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077

2
2
2
2
2
2
2
2
2
2
2
2
2
2

1078
1079
1080
1081
1082
1083
1085
1086
1087
1088
1089
1090
1091
1092
1093

3
3
3
3
2
2
2
2
2
2
2
2
2
2
2

1094

2

1095

2

1096

2

I

1097
1098
1099
1100
1101
1102
1103
1104
1105

update: proceduTe;
dec lal'l i byte;
call cr$lf;
call loop.char (10. OAH) ,
call loopSchar(28, '*')j
call "'TiteeO, @( I Station Configuration '), 23. @:status);
call Ioop$char(27. '*');
call cr.lf,
call crSlfi
call IIIriteCO, (!(I Host Address: '), 15, @:status);
call printSnetwDT'kSaddT(@ia$setup. ia$address(O»i
i = OJ
call lIIT'ite(O, @e' Multicast Address(es): '), 24, @:statuS)i
if mc$s.tup.mc$b~te'count = 0
then call writelnCO, @('Na Multicast Addresses Deofined '), 30.
else
do while i ( me.setup mc$b~te$count;
call printSnetwDTk$addT(@mcSsetup.mc$sddT'essCt»;
call 100p.char(24 • • '),
i
i + 6;
end;

@status)i

=

call IIIriteCO, @CODH). I. @statusl;
if not no.transmission then call print.parameters;
call "'riteCO, (!( I 82586 Configu1'ation Block: '), 28, @status)j
call print.strC@tonfigure. infoCO), 10),
call cr.If,
call IoopScha1'(29, '*/)j
call \lJrite(O. e(' Station Activities'), 20, @status);
call1oopScha1'(29, '*')i
call c1'Slfi
call c ... If,
call w1'iteln(O.
@C'
of GDod
of Good
CRC
Alignment
No
Rp.teive'),
73. @Stcstu5);
call w'riteln(O,
Resource
UV~1'run').
E1'ro1'S
@(' Frames
Frames
Er1'ors
73, @StC'ttU5)j
call writelnfO,
E1'rurs
E1"t"ort. '),
ee/TT'ansmitted Received
72. (!status),

*

*

end update;

main:

I

call initi
enable;
do IaIhile reset;

2

end;

I

disable;
scb. cmd = 0100H,
outputCCA.PORT)
call wait$scbi
enable;

1

1
1
1
1

CA,

292010-64

Traffic Simulator/Monitor Station Program, (Continued)

1-275

intJ
li06
1107
1108
110'1
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
113'1
1140
1141
1142
1143
1144
1145
1146
1147
1148
114'1
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166

2
1
1
1
1
1
1'
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
3
3
2
2
2
2
2
2
2
2
1
1
2
2
3
4
4
4
4
4
4
4
3
3
3
2
2
3
3
3
3
2

AP-274

do while (diagnose.statu5 and BOaOH) () BeaOHi
end;
call cr$lf;

if diagnose status

OAOOOH
Diagnose failed! '),
OAOOOH
@(' Configul"e failed!'),
1 f la.setup. status (> OAOOOH
then call writelnCO. @(' IA Setup failed! '),
if me.setup. status (> OAOOOH
then call writelnCO. @(/ Me Setup failed! '),
<~

then cail writelnCO.
If configure. status
then call wrltelnCO.

scb. cbI.offset

@e'

<>

= nffset

17 • • status);
'18,

@status);

17

C!status);

17

@status),

(@transmit. status);

call urriteln(O, @(ODH, OAH,
disable.
5tb. cmd == OOIOHi
Dutput(CA$PORT) = CA;
call wait.5cb;
enab Ie;

I

Receive Unit is active. '), 26, @statut.);

Dutput(ESI$PORT) - NO$LOOPBACK;
call cr$l fi
if not no$transmission then
do;
call write(O. @('---Transmit Command Block---'), 2e. @status);
call printSwds(@transmit. status. e);
call crSlfi
curScbSoffset = offset C@transmit. status);
call pauslf;
do z = 1 to &0;
call time(250);
endi
call writeln(O, (!(ODH, OAH. 'transmission st .. rt.d! '), 23, @status);
call c,.$If;
disable;

scb, cmd = 0100H;
output (CAtPORT)

CA;

call UJait$scbi
enable;
end;
call update;
do fo,.ever;
call write(O,' @(ODH. I ' ) , 2. @status);
d.o IJ = 0 to Si
do case 1ji
call I&Irite$int(CDunt. dhex)i
call I.IJriteSint(receive.count, dhex);
call I&Irit •• int(scb. crc.errs. dhex);
call writeSint(scb. aInSerrs. dhex);
call I&Irite$intCscb. rlc.errs. 'dhex),
call I&Irite$int(scb. DvrnSerrs, dhex)i
end;
~har.count
13 - char.count;
call loop$char(char.cDunt, , ' ) i
end;
if csts then

=

do;

disable;
call getout;
call update;

292010-65

end;
end;
end tsms;

MODULE INFORMATION:
CODE AREA SIZE
= 23C3H
CONSTANT AREA SIZE
OF85H
VARIABLE AREA SIZE = 265EH
MAXIMUM STACK SIZE
OO'l2H
19'14 LINES READ
o PROGRAM WARNINGS
o PROGRAM ERRORS

'11550
39730
'1822D
1460

DICTIONARY SUMMARY:
15'1KB MEMORY AVAILABLE
23KB MEMORY USED
(14X)
OKB DISK SPACE USED
END OF PL/M-86 COMPILATION

292010-66

Traffic Simulator/Monitor Station Program (Continued)

1-276

Ap·274

/*******************9~k~**.*************************** .********************.w.,

1*
1*
'.
Iii

186/5B6 High Integration Board init!31j.ation Routine
(This driver is configured for Ethernet/Cheapernet Desi~n
5(j t Demo Board)

.'"
1*

Vel'.

1*
1*

Ki~oshi

,

,

2.0

Nishide

1981,

Mal'ch

14,

Intel

~utpD~atiDn

<·1
*1
*1
*1

*1

'·1
*1
*1

/ **************'*.*1: iI tc. . . . . ********************************************* ..... w .. "
1* rhe conditional compilatIon ya"a",eter 'EPROM27128, determines board r(OM
size.
If it is true, the 80186'5 ~alt ~tat~ aenerator 15 programmed to
o wait state for upper 64K-byte memory locations.
if ~~ i& false,
the
wait gtate generator is programmed to 0 wait state for uppe~ t~8K-byt~
memory locaclan~
*1

ini186:
do;
~eclare hib_ir label public
declare main label external
decla~e menu laD~l eyternal

1* literals *1

5

declare lit
UMCS_reg

literally
lit
:..~r.S_l"eCJ
lit
PACS_reg
lit
MPCS_reg
lit
INT_MASK_reg
lit
ISCP$LOC$LO
lit
ISCP$LOC$HI
lit
!:cr. . CH_B_CMO
lit
SCC Ct1 ii ~.'TII
lit
Iii.
SCC:CH:A:CMO
SCC_CH_A _OIlT'.
ilt
Nt u_
lit
CR
lit
LF
lit
BS
lit
SP
lit
lit
OM
DEL
11t
BEL
lit

'li teral1~ "
'OFFAOH',
'OFFA2H',
'OFFA4H',
·OFrN:-J.l',

'OFF28H',
'03FF8H'.
'0'.
'8300H',
'B302H',
'c;:.":J04H',
, 8306H "

'0',

'OOH' ,
'OAH' ,
'OBH' ,
'20H'.
'3Fn" ,

'07FH',
'07H',

292010-67

186/586 High Integration Board Initialization Routine

1-277

inter

Ap·274

declare acp structure

6

(

_V.bUB bvta.
unu •• d (:U b"tel

iscp'addrSlo word.
iscp'addr.hi word
I

at (OFFFF6HI data (0. O. O. O. O. O. ISCP.LDC.LO. ISCPSLOC$H.,.
7

output(INT_mask_regl • OFFH. 1* mask all interrupts *1

8

2

'I

2

and initSintSclt.

10

1
2

rra: procedure (reg_nol bVte.

11
12

2

14

2

IS

2

end ,.raJ

16
17

1
2

rrb: procedure (reg_no I bvte.

18

20

2
2

21

2

22

declare rag_no bvte.
i9 (rag_no and OFHI <> 0 then output(SCC_CH_A_CMDI
return input(SCC_CH~_CMDI.

declare ,.eg_"o b"te,

if Crag_no and OFHI <>0 than output CSCC_CH_D_CMDI
return inputCSCC_CH_B_CMDI.

and OFH.

end 1',.bJ

procedure (reg_"o, value);
declare (reg_no, value) byte;

~ra:

2~

;:

24
26

2
2

27

if Creg_no and OFHI <> 0 then output C6CC_CH_A_CMDI a reg_no and OFH.
output CSCC~CH_A_CMDI • value.

2

end laIra;

2B
2"

;;

W1'b: procedure (reg_"o, value);
declare (reg_no, value) byte;

30
32

2
2

33

2

34
3~

= reg_no

if (reg_no and OFHI ~> 0 then output
output C6CC_CH_B_CMDI = value.

C6CC_CH~_CMDI

= reg_no and

O~H.

end tu,.bJ

initSSCC'D: procedure.
<:

call wrbCO'l. 01000000bl.

1* channel B reset *1
292010-68

186/586 High Integration Board Initialization Routine (Continued)

1-278

inter
36
37
38
39
40
41
42
43
44

2
2
2
~

2
2
2
2
2

46

2
2

47

2

4~

48

AP-274

1* 2 stop. no parit~. brf = 16x *1
1* rx 8 bits/chal'. no auto-enable *1
1* tx 8 bits/char *1

wrb 104.
wrb (03,
wrbl05.
wrbe 10.
wrbe II.

010011 lOb ).
11000000b) ,
01100000b) ,
OOOOOOOOb ) ,
01010110b) ,
IIIrb( 12, OOOOIOllb),
wrb( 13, OOOOOOOOb ) ;
lIIrb (14, 00000011 b),
wrb( 15, OOOOOOOOb ),

call
call
c.::.l1
call
call
call
call
call
call

call wrbe03.

call IIIrb(05.

1* rxc = txc
1* baud rate

DRG.

= 9600
source = SYS

trlc

DRG out *1

*1

CLK. enable DRG *1
1* BRG
1* all ext status interrupts off *1

11000001b) ,
11101010b),

1* scc-b receive enable *1
1* scc-b transmit enab 1 e, dtr on. rts on *1

end init$SCC$B;
,Sin:

procedure blJte public;

49
51

3
2

do whlle einputeSCC_CH_O_CMD) and I)
return e inputeSCC_CH_B_DATA))'

52

2

end cSin;

53
54

I
2

declare char blJtei

55
57

3
2

58

2

end C$Duti

59
60

I
2

r .. ad: pl"oceduT'e (fileSid,
declare fileSid ward,
msgSptr pointer.
count lIIord.

cSout:

0;

end;

0;

end;

procedul'e (char) publiCi

do while e,nputeSCC_CH_B_CMD) and 4)
outputeSCC_CH_B_DATA) = char,

msgSptr,

count, actual'ptr,

statusSptY') publiCi

actual'ptr pointer,
status$ptr pointer.
msg based msg$ptr el) b~te.
buf (200) b~te.
actual based actualsptr word,
status based status$ptr word,
i word,
ch b~te,
1* This procedure implements the ISIS read p~ocedure. All control characters *1
1* except LF, BS, and DEL a1'e ignored. If BS Dr DEL is encountered. a
*1
1* backspace is done.
*1

61
62
63
64
65
66

2
2
2
3
3

3

status = 0;
i, ch = 0;
do while (ch <> CR) and (ch <> LF) and ei
ch = c$in and 07FHi
if ech
OS) or ech
DEL) then
do;

=

<

198),

=

292010-69

186/586 High Integration Board Initialization Routine (Continued)

1-279

inter
67
loB
69
70
71

72
73
74
75
76

Ap·274

> '0

l~ I

4
4
5
5

then

-do.
i .. i - I .

cd!
call
call
call
call

'5
5

5
5

cSoutCDELI.
cSoutCBBI.
cSDutCSPI.
cSoutCDELI.
cSoutCBSI.

and.

5

ehe

4

call cSoutCBELI.
77
7B

4
3

79
BO
Bl
B2
B3
B4

3
4
4
4
4
3

B5
B6
B7
BB
B9
90

3
4
4
4
4
3

91
92
93
95
96
97
9B

3
2

99

2

and.

else
H

ch

>-

SP than'

do.
call cSoutCchl.
bu~Ci) • chI
i .. i + I.
end.
81 . .

if Cch - CRI or Cch • LFI then
do.
bufOI .. CR.
bu~Ci + II - LF.
i .. i + 2.
end.

else
call cSoutCBELI.

2
2
2

3
3

endl

call cSDutCCRI.
if i > count than i
count.
actual -= i;
do i
0 'to actual - I.
msgCiI .. buf(U.
- end.

=

=

end read;

CltS: procedura bvte publiCI

100

return «lnput(SCC_CH_B_CMDI and II

<>

01.

101

2

102

2

end csts;

103
104

1
2

..rit.: procedure (hlo!Sid. msgSptr. count. statu.Sptrl publiCI
declare (fileSid. countl .. ord.
(msgSptr. status'ptrl pointer;
msg ba.ed msgSptr (II bvte.
Itatul based .tatusSptr .. ord.
ch bvte.
i word;

105

2

1* This procedure implements the ISIS ..rit. *1

status = 0;
292010-70

186/586 High Integration Board Inltlallzatlo,n Routine (Continued)

1-280

intJ
106
107
lOB
1'09

AP-274

2
2
3
3

i

=

0;

do whlle i < count;
ch = msg(i)i
if

((ch

:>= SP) and (ch ( DEll) or (ch

CR)

or

(c

h

LF)

or

(ch

NUll

then
110
III

3
3

112
113

3
3

114

2

115

call c$out(ch);
else
i

call c$out(GM);
+ 1;

= i

end;

end write;

hi b

i r:

$IF EPROM2712B
output IUMCS_reg)

OF03BH,

1* Starting Address
no wait state *1

OFOOOOH,

output (UMCS_reg)

OE03BH,

1* Starting Address

OEOOOOH,

$ELSE

no wait state *1
$ENDIF
116
117

output(LMCS_reg)
output(PACS_reg)

03FCH,
OB3CH,

1* 16K,
1* PBA

no wait state *1

= BOCOH.

no wait state for

PSCO-3 *1

liB

OBFH,

call init$int$clti

119
120
121
122

1* Peripherals in 110 space. no At 8( A2
provided, 3 wait states +01' PSt4-6 *1

call

ini t$SCC$B,

go to main;
end

ini186;

292010-71

186/586 High Integration Board Initialization Routine (Continued)

1-281

inter

AP-274

THE 82530 SCC

APPENDIX C
80186 INTERFACE AP BRIEF

INTRODUCTION

INTERFACi: OVERVIEW

The object ofthis document is to give the 82530 system
designer an in-depth worst case design analysis of the
typical interface to a 80186 based system. This document has been revised to include the new specifications
for the 6 MHz 82530. The new specifications yield better margins and a 1 wait state interface to the CPU (2
wait states are required for DMA cycles). These new
specifications will appear in the 1987 data sheet and
advanced specification information can be obtained
from your local Intel sales office. The following analysis 'includes a discussion of how the interface TTL is
utilized to meet the timing requirements of the 80186
and the 82530. In addition, several optional interface
configurations are also considered.

The 8253'0 - 80186 interface requires the TTL circuitry
illustrated in Figure 1. Using five 14 pin TTL packages,
74LS74, 74AS74, 74AS08, 74AS04, and 74LS32, the
following operational modes are supported:
•
•
•
•
•

Polled
Interrupt in vectored mode
Interrupt in non-vectored mode
Half-duplex DMA on both channels
Full-duplex DMA on channel A

A brief description of the interface functional requirements during the five possible BUS operations follows
below.
.

DATA (D7-D8)

B25a8
.7

••
••••••
.,
••
.2

<4 DB?
37 DB6

S

THIIA

RHIIA

'fI!lmi

DI&

Jm!eli

38 DB'"

.. ..
2
89
I

~

••
82
Bl

1!T!li
~

m!

••
ao

JI'1!71mIli
fKlIB
litX1l8

3'" A... l'

aa

nu

I.

7
6

"lIEGB
"REBB
lEI
lEO

28

CHAHIIEL
A

II

17
I.
I•

.0
"
.7

CHANNEL

'rIIll9 2.
Ift'i!9 2.
'fVli9 2'

82 DI''f'

••
••

I.
I.
I.
12

1:'I'D
'fR
liYII7IImW

uee

Lt<

ON.

HOtES'

B

.,

2'
2'

•••
S!

.ou

H - PULLED HIGH THROUGH 6K OH"
UI - " ..LS?"
U2 - 14Ase8

U3 - ? ..AS''''
U4 - 1"'AS14

us - ?4LS82

74Ase4
IIRGe

"

U3

~'~'----------------------~
292010-72

Figure 1. 82530-80186 Interface

1-282

AP-274

UN ITS,

125NS/19

CLKOUT
AD

0-15
I

DT/R

ALE

90196

TCLJ)X

----~~--------~------------------------~------~
..~
~r_+-

___~~r-_o_oo_o_oo_oo_oo_o_oo_oo

~~_ _ _ _~~_ _ _ __ _

__
o_oo_oo_oo_oo_o_o0_00_00_0_00_00_00_0_00_00_0_0

TCLRH

92590

DATA

292010-73

Figure 2. 80186-82530 Interface Read Cycle

UNITS,

125 NS/19

CLKOUT

DT/R

90196

---------+-------- ""..-+-______________________~-,-----~/o

°

0.00.0 . . 0.000

-i--+______________-!---i;-_ _°i'o

- - - - - - _ _ f _ . ' - -_ _

o

0 - 0- 0
'-0
0-0
0 -.
0-0.0 - '0

ADDRESS
92590

DATA

TPDHR/S86-WR/S30 (HIGH)

292010-74

Figure 3. 80186-82530 Interface Write Cycle

READ CYCLE: The 80186 read cycle requirements are
met without any additional logic, Figure 2. At least one
wait state is required to meet the 82530 tAD access
time.
WRITE CYCLE: The 82530 requires that data must be
valid while the WR pulse is low,§ure 3. A D FlipFlop delays the leading edge of- WR until the falling
edge of CLOCKOUT when data is guaranteed valid
and WR is guaranteed active. The CLOCKOUT signal

°

is inverted to assure that WR is active low before the D
Flip-Flop is clocked. No wait states are necessary to
meet the 82530's WR cycle requirements, but one is
assumed from the RD cycle.
INTA CYCLE: During an interrupt acknowledge cycle, the 80186 provides two INTA pulses, one per bus
cycle, separated by two idle states. The 82530 expects
only one long INT A ~e with a RD pulse occurring
only after the 82530 lEI/lEO daisy chain settles., As

1-283

inter

AP-274

UNITS: 125 NS/12

T.

T.

T..

2T
IDLE S'l'A'l'ES

TI

T'
2

ToO

CLKOUT

AD "-15
80186

Dulf
TII'l'1i
RN

: ~: :::::.: :::: ::::::: ::: :::: :::::::: :::::::: :::::::: ::::::: ::: ::::::::: ::: :t:~~';:: ::rECfO~

~:::t:~~~~:

=It,;~lF·;;<'~l,==

··············1···································1············
.. ·················· .. ··········
................. .
·············1···· .. ········ .. ···················1·· .. ··· ...........................
·········,' ....
......···········1·
·········1···················

CLK

........ I..

.. ...... I ..

TII'l'1i
82530
Q

VECTOR

292010-75

Figure 4. 82530-801861NTA Cycle

illustrated in Figure 4, the INTA signal is sampled on
the rising edge of CLK (82530). Two D Flip-Flops and
two TTL gates, U2 and U5, are implemented to generate the proper INTA and RD pulses. Also, the INT
signal is passively pulled high, through a I k resistor,
and inverted through U3 to meet the 80186's active
high requiremep.t.
DMA CYCLE: Conveniently, the 80186 DMA cycle
timings are the same as generic read and write operations. Therefore, with two wait states, only two modifications to the DMA request signals are necessary.
First, the RDYREQA signal is inverted through ·U3
similar to the INT signal, and second the DTR/REQA
signal is conditioned through a D Flip-Flop to prevent
inadvertent back to back DMA cycles. Because the
82530 DTR/REQA signal remains active low for over
five CLK (82530)'s, an additional DMA cycle could
occur. This uncertain condition is corrected when U4
resets the DTRlREQ signal inactive high. Full Duplex
on both DMA channels can easily be supported with
one extra D Flip-Flop and an inverter.
RESET: The 82530 does not have a dedicated RESET
input. Instead, the simultaneous assertion of both RD
and WR causes a hardware reset. This hardware reset
is implemented through U2, U3, and U4.

need not be as extensive as the typical interface used in
this analysis. Two alternative configurations are discussed below.
8288 BUS CONTROLLER: An 80186 based system
implementing an 8288 bus controller wilL not require
the preconditioning of the WR signal through the Ii
Flip-Flop U4. When utilizing an 8288, the control signal IOWC does not go active until data is valid, therefore, meeting the timing requirements of the 82530. In
such a configuration, it will be necessary to logically
OR the lowe with reset to accommodate a hardware
reset operation.
NON-VECTORED INTERRUPTS: If the 82530 is to
be operated in the non-vectored interrupt mode (B step
only), the interface will not require UI·or U5. Instead,
INTA on the 82530 should be pulled high, and pin 3 of
U2 (RD AND RESET) should be fed directly into the
RD input of the SCC.
Obviously, the amount of required interface logic is application dependent and in many cases can be considerably less than required by the typical configuration,
supporting all modes of sec operation.

DESIGN ANALYSIS
ALTERNATIVE INTERFACE
CONFIGURATIONS
Due to its wide range of applications, the 82530 interface can have many varying configurations. In most of
thes~ applications the supported modes of operation

This design analysis is for a typical microprocessor system, pictured in Figure 5. ,The Timing analysis assumes
an 8 MHz 80186 and a 4 MHz 82530. Also, included in
the analysis are bus loading,. and TTL-MOS cOmpatibility considerations.

1-284

Ap·274

ADDRESS
LATCH

r--

MICROPROCESSOR

l;t

ADDRESS BUS

[\r

r---

~
ALE

c--i--

.---

--...£Q!:!!.RObJ!!,!L

"'-..7'

""

:>

. "()7

7'

c--'---

~

~

ROM

RAM

~

1/0

r-'----

---

l;t
f\

.~

DATA BUS

DATA
TRANSCEIVER

292010-76

Figure 5. Typical Microprocessor System

Bus Loading and Voltage Level
Compatabilities

TIMING ANALYSIS

The data and address lines do not exceed the drive capability of either 80186 or the 82530. There are several
control lines that drive more than one TTL equivalent
input. The drive capability of these lines are detailed
below.
WR: The WR signal drives U3 and U4.
101 (2.0 rnA) > Iii (-0.4 rnA + -0.5 rnA)
loh (-400 ,.A) > lih (20,.A + 20,.A)

Certain symbolic conventions are adhered to throughout the analysis below and are introduced for clarity.
1. All timing variables with a lower case first'letter are
82530 timing requirements or responses (i.e., tRR).
2. All timing variables with Upper case first letters are
80186 timing responses or requirements unless preceded by another device's alpha-numeric code (i.e.,
Tclcl or '373 Tpd).
3. In ~ writ~cIe analysis, the timing variable
TpdWR186-WR530 represents the propagation delay between the leading or traili~dge of the WR
signalleav~he 80186 and the WR edge arrival at
the 82530 WR input.

•

PCS5: The PCS5 signal drives U2 and U4.
• 101 (2.0 rnA) > Iii (-0.5 rnA + -0.5 rnA)
loh (-400 ,.A) > lih (20 p.A + 20 ,.A)

Read Cycle

INTA: The INTA signal drives 2(Ul) and U5.
101 (2.0 rnA) > Iii (-0.4 rnA + -0.8 rnA + -0.4 rnA)
loh (-400 ,.A) > lih (20 ,.A + 40,.A + 20,.A)
•

All the 82530 1/0 pins are TTL voltage level compatible.

1. tAR: Address valid to RD active set up time for the
82530. Since the propagation delay is the worst case
path in the assumed typical system, the margin is calculated only for a propagation delay constrained and not
an ALE limited path. The spec value is 0 ns minimum.
• 1 Tclcl - Tclav(max) - '245 Tpd(max)
2(U2) Tpd(min) - tAR(min)
= 125 - 55 - 20.8

1-285

+

10

+

+ Tclrl(min) +

2(2) - 0 = 63.2 ns margin

inter

AP·274
*3 Tclcl + 1(Tclclwait state) - Tclav(max) - '373
Tpd(max) - '245 Tpd - Tdvcl(min) - tAD

2. tRA: Address to RD inactive hold time. The ALE
delay is the worst case path and the 82530 requires 0 ns
minimum.
• 1 Tclcl -' Tclrh (max) + Tchlh(min)
Tpd(min) - 2(U2) Tpd(max)
=

55 - 55

+ 5 + B - 2(5.5)

=

= 375
margin

+ '373 LE

+ 125 - 55 - 20.8 -14.2 - 20 -325

=

65 ns

,

Write Cycle

2 ns margin

3. tCLR: CS active low to RD active low set ,up time.
The 82530 spec value is 0 ns minimum.

1. tAw: Address required valid to WR active low set
up time. The 82530 spec is 0 ns minimum.

• 1 Tclcl - Tclcsv(max) - Tclrl(min) - U2
skew(RD - CS) + U2 Tpd(min)

•

=

125 - 66 - 10 - 1

+2

=

50 ns margin

= 125 - 55 - 5 - 20.B
=

4. tRCS: RD inactive to CS inactive hold time. The
82530 spec calls for 0 ns minimum.
•

Tcscsx(min) - U2 skew(RD - CS) - U2 Tpd(max)

=

35 - 1 ~ 5.5 = 28.5 ns margin

• Tclch(min) - Tcvctx(max) + Tchlh(min) + '373 LE
Tpd(min) - TpdWR186=WR530(HIGH) [U2 Tpd(max) +
U3 Tpd(max) + U4 Tpd(max)]
= 55 - 55
margin

• 1 Tclcl + 1 Tchcl - Tchcsx(max) + Tclrl(min) - U2
skew (RD - CS) + U2 Tpd(min) - tCHR
125

+ 55 - 35 - 10 - 1 + 2 - 5

=

1 Tclcl - Tclcsv(max) + Tcvctv(min) - U2 Tpd(max)
+ TpdWR1B6=WR530(LOW) [Tclcl - Tcvctv(min) + U3
Tpd(min) + U4 Tpd(min)1
'
•

= 125 - 66 + 5 - 5.5
183.9 ns margin

+ 1(Tclclwait state) - 2(U2 s~ew) - tRR

= (250-50) +

= 173 ns margin

1(125) - 2(1) - 150

+ [125 - 5 + 1 + 4.41 =

4. tWCS: WR invalid to Chip Select invalid hold time.
82530 spec is 0 ns.
'
-

7. tRDV: RD active low to data valid maximum delay
for 80186 read data set up time (Tdvcl = 20 ns). The
margin is calculated on the Propagation delay path
(worst case).

• Tcxcsx(min) - U2 Tpd(max) TpdWR1B6=WR530(HIGH) [U2 Tpd(max)
Tpd(max) + U4 Tpd(max)]

• 2 Tclcl + 1(Tclclwait state) - Tclrl(max) - Tdvcl(min)
- '245 Tpd(max) -; 82530 tRDV(max) - 2(U2) Tpd(max)
=
=

+ 5 + 8 - [5.5 + 3 + 7.11 = -2.6 ns

3. tCLW: Chip select active low to WR active low hold
time. The 82530 spec is 0 ns.

131 ns margin

6. tRR: RD pulse active low time. One 80186 wait state
is included to meet the 150 ns minimum timing requirements of the 82530.
* Trlrh(min)

+ [125 - 5 + 1 + 4.41 - 0

170.6 ns margin

2. tWA: WR inactive to address invalid hold time. The
82530 spec is 0 ns.

5. tCHR: CS inactive to RD active set up time. The
82530 requires 5 ns minimum.

=

Tclcl - Tclav(max) - Tcvctv(min) - '373 Tpd(max)

+ TpdWR186 - WR530(LOW) [Tclcl - Tcvctv(min) +
U3 Tpd(min) + U4 Tpd(min)1 - tAW

= 35

+ U3

+ 1.5 - [5.5 + 3 + 7.11 = 20.9 ns margin

5. tCHW: Chip Select inactive high to WR active low
'
set up time. The 82530 spec is 5 ns.

2(125) + 1(125) - 70 - 20 - 14.2 - 105 - 2(5.5)
154 ns margin

8. tDF: RD inactive to data output float delay. The
margin is calculated to DEN active low of next cycle.

• 1 Tclel + Tchel(min) + Tcvctv(min) - Tehesx(max) U2 Tpd(max) + TpdWR1B6=WR530(LOW) [Telel Tevetv(min) + U3 Tpd(min) + U4 Tpd(min)] - tCHW

• 2 Tclcl + Tclch(min) - Tclrh(max)
2(U2) Tpd(max) - 82530 tDF(max)

=-125 + 55 + 5 - 35 - 5.5
5 = 264 ns margin

=

'250

+ 55 -55 + 10 - 11- 70

=

+ Tchctv(min) 179 ns margin

9. tAD: Address required valid to read data valid maximum delay. The 82530 spec value is 325 ns maximum.

+ [125 -5 + 1 + 4.41 -

6. tWW: WR active low pulse. 82530 requires a minimum of 60 ns from the falling to the rising edge of WR.
This includes one wait state.

1-286

inter

AP-274

• Twlwh [2Tclcl - 40] + 1 (Tclclwait state) - TpdWRI
186-WR530(lOW) [Tclcl - Tcvclv(min) + U3 Tpd(max)
+ U4 Tpd(max)] + TpdWR/186=WR/530(HIGH) [U2
Tpd(min) U3 Tpd(min) + U4 Tpd(min)] - tWW

should never exist. 82530 drivers should insure that at
least one CPV cycle separates INTA and WR or RD
cycles.

= 210 + 1(125) - [125 - 5 + 4.5 +
+ 3.2] - 60 = 135.6 ns margin

4. tWI: WR inactive high to INT A active low minimum hold time. The spec is 0 ns and the margin assunies CLK coincident with INTA.

~.2]

- [1.5 + 1

7. tDW: Data valid to WR active low setup time. The
82530 spec requires 0 ns.
• Tcvctv(min) - Tcldv(max) - '245 Tpd(max) +
TpdWR186-WR530(lOW) [Tcici - Tcvclv(min) + U3
Tpd(min) + U4 Tpd(min)]

• Tclcl - Tcvctx(max) - TpdWR186 - WR530(HIGH)
[U3 Tpd(max) + U4 Tpd(max)] + Tcvctv(min) + Ul
Tpd(min)
= 125 - 55 - [5.5 + 3 + 7.1] + 5 + 10
margin

= 5 - 44 - 14.2 + 125 - 5 + 1.0 + 4.4 = 72.2 ns
margin

=

69.4 ns

8. tWD: Data valid to WR inactive high hold time. The
82530 requires a hold time of 0 ns.

5. tlR: INTA inactive high to RD active low minimum
setup time. This spec pertains only to 82530 RD cycles
and has a value of 55 ns. The margin is calculated in
the same manner as tIW.

• Tclch - skew (Tcvctx(max) + Tcvctx(min)l + '245
OE Tpd(min) - TpdWR186-WR530(HIGH) [U2 Tpd(max)
+ U3 Tpd(max) + U4 Tpd(max)]

6. tRI: RD inactive high to INTA active low minimum
hold time. The spec is 0 ns and the margin assumes
CLK coincident with INTA.

= 55 - 5 + 11.25 - [5.5 + 3.0 + 7.1] = -50.6 ns
margin

•

Tclcl - Tclrh(max) - 2 U2 Tpd(max)

=

125 - 55 - 2(5.5)

+ Ul Tpd(min)

INTACycle:
1. tiC: This 82530 spec implies that the INTA signal is
latched internally on the rising edge of CLK (82530).
Therefore the maximum delay between the 80186 asserting INTA active low or inactive high and the 82530
internally recognizing the new state of INTA is the
propagation delay through VI plus the 82530 CLK period.
•
=

Ul Tpd(max) + 82530 ClK period
45

+ 250

=

295ns

2. tel: rising edge of CLK to INTA hold time. This
spec requires that the state of INTA remains constant
for 100 ns after the rising edge of CLK. If this spec is
violated any change in the state of INTA may not be
internally latched in the 82530. tel becomes critical at
the end of an INTA cycle when INTA goes inactive.
When calculating margins with tCI, an extra 82530
CLK period must be added to the INTA inactive delay.
3. tIW: INTA inactive high to WR active low minimum setup time. The spec pertains only to 82530 WR.
cycle and has a value of 55 ns. The margin is calculated
assuming an 82530 WR cycle occurs immediately after
an INTA cycle. Since the CPV cycles following an
82530 INTA cycle are devoted to locating and executing the proper interrupt service routine, this condition

+ 5 + 10

=

+ Tcvclv(min)

74 ns margin

7. tIID: INTA active low to RD active low minimum
setup time, This parameter is system dependent. For
any sce in the daisy chain, t1ID must be greater than
the sum of tCEQ for the highest priority device in the
daisy chain, tEl for this particular SCC, and tEIEO for
each device separating them in the daisy chain. The
typical system with only 1 sec requires t1ID to be
greater than tCEQ. Since tEl occurs coincidently with
tCEQ and it is smaller it can' be neglected. Additionally, tEIEO does not have any relevance to a system with
only one sec. Therefore t1ID > tCEQ = 250 ns.
• 4 Tclcl + 2 Tidle states - Tcvclv(max) - tiC [Ul
Tpd(max) + 82530 ClK period] + Tcvclv(min) + U5
Tpd(min) + U2 Tpd(min) - tliD
=
=

500 + 250 - 70 - [45 + 250] + 5 + 6 + 2 - 250
148 ns margin

8. tlDV: RD active low to interrupt vector valid delay.
The 80186 expects the interrupt vector to be valid on
the data bus a minimum of 20 ns before T4 of the second acknowledge cycle (Tdvcl). tIDV spec is 100 ns
maximum.
• 3 Tclcl - Tcvclv(max) - U5 Tpd(max) - U2
Tpd(max) - tlDV(max) - '245 Tpd(max) - Tdvcl(min)
= 375 - 70 - 25 - 5.5 - 100 - 14.2 - 20 = 140.3
ns margin

1-287

inter

AP·274

9. tIl: RD pulse low time. The 82530 requires a minimum of 125 ns.

= 375 - 70 - 25 - 5.5 + 5 + 6 + 1.5 - 125 =
162 ns margin

3. tWRI: 82530 WR active low to REQ inactive high
delay. Assuming destination synchronized DMA transfers, the 80186 needs two wait states to meet the tWRI
spec. This is because the 80186 DMA controller samples requests two clocks before the end of the deposit
cycle. This leaves only 1 Tclcl + n(wait states) minus
WR active delay for the 82530 to inactivate its REQ
signal.

DMACycle

• Tclcl + 2(Tclclwait state) - Tcvctv(min) TpdWAI86-WA530(LOW) [Tclcl - Tcvctv(min) + U3
Tpd(max) + U4 Tpd(max)1 - Tdrqcl - tWAI

• 3 Tclcl - Tcvctv(max) - U5 Tpd(max) - U2
Tpd(max) + Tcvctx(min) + U5 Tpd(min) + U2 Tpd(min)
- tII(min)

Fortunately, the 80186 DMA controlier emulates CPU
read and write cycle operation during DMA transfers.
The DMA transfer timings are satisfied using the above
analysis. Because of the 80186 DMA request input requirements, two wait states are necess~o prevent
inadvertent DMA cycles. There are also CPUDMA intracycle timing considerations that need to be addressed.
1. tDRD: RD inactive high to DTRREQ (REQUEST)
inactive high delay. Unlike the READYREQ signal,
DTRREQ does not immediately go inactive after the
requested DMA transfer begins. Instead, the DTRREQ
remains active for a maximum of 5 tCY + 300 ns. This
delayed request pulse could trigger a second DMA
transfer. To avoid this undesirable condition, a D Flip
Flop is implemented to reset the DTRREQ signal inactive low following the initiation of the requested DMA
transfer. To determine if back to back DMA transfers
are required in a source synchronized configuration,
the 80186 DMA controller samples the service request
line 25 ns before T1 of the deposit cycle, the second
cycle of the transfer.
• 4 Tclcl - Tclcsv(max) - U4Tpd(max) - Tdrqcl(min)
= 500 - 66 - 10.5 - 25 = 398.5 ns margin
2. tRRI: 82530 RD active low to REQ inactive high
delay. Assuming source synchronized DMA transfer,
the 80186 requires only one wait state to meet the"tRRI
spec of 200 ns. Two are included for consistency with
tWRI.

=375 - 5 - [125 - 5 + 4.5 + 9.21 - 25 - 200 =
11.3 ns margin
NOTE:
If one wait state DMA interface is required, external
logic, like that used on the DTRREQ signal, can be
used to force the 82530 REQ signal inactive.
4. tREC: eLK recovery time. Due to the internal data
path, a recovery period is required between SCC bus
transactions to resolve metastable conditions internal to
the SCC. The DMA request lines are marked from requesting service until after the tREC has elapsed. In
addition, the CPU should not be allowed to violate this
recovery period when interleaving DMA transfers and
CPU bus cycles. Software drivers or external logic
should orchestrate the CPU and DMA controller operation to prevent tREC violation.

Reset Operation
During hardware reset, the system RESET signal is asserted high for a minimum of four 80186 clock cycles
(1000 ns). The 82530 requires WR and RD to be simultaneously asserted low for a minimum of 250 ns.
• 4 Tclcl - U3 Tpd(max) - 2(U2) Tpd(max) + U4
Tpd(min) - tREe
= 1000 - 17.5 - 2(5.5) + 3.5 - 250 ns = 725 ns
margin

• 2 Tclcl + 2(Tclclwait state) - Tclrl(max) - 2(U2)
Tpd(max) - Tdrqcl - tRRI
=2(125) + 2(125) - 70 - 2(5.5) - 200 = 219 ns
margin

1-288

APPLICATION
NOTE

AP-324

June 1989 .

Implementing Twisted Pair
Ethernet with the Intel 82504TA,
82505TA, and 82521TA .

WILLIAM WAGER
TECHNICAL MARKETING ENGINEER

Order Number: 292057-001
1-289

infef

AP-324

ABSTRACT

1.0 INTRODUCTION

The market for Local Area Networks (LANs) has been
growing rapidly for several years, and LANs based on
the ANSI/IEEE 802.3-1985 standard have proven to
be the most popular. These networks are called
.CSMA/CD LANs because of their Medium Access
Control method (MAC)-Carrier Sense Multiple Access with Collision Detection. Intel has been a contributor to both the standardization and the widespread
acceptance of CSMA/CD LANs since their conception.

This Ap Note is intended to aid system designers who
have some knowledge of IEEE 802.3 standards, but
limited experience with analog design. System designers
designing Twisted Pair Ethernet LANs with Intel's
TPE products and Ethernet LAN controllers will find
this and other Intel Ap Notes useful (see also: AP-274,
Implementing Ethernet/Cheapernet with the Intel
82586, Kiyoshi Nishide; and AP-320, Using the Intel
82592 to Integrate a Low-Cost Ethernet Solution into a
PC Motherboard, Michael Anzilloti).

The two most prevalent types of CSMA/CD LANs are
called, in IEEE terminology, IOBASE5 (aka Ethernet,
Yellow Cable, or Thick Wire) and IOBASE2 (Cheapernet or Thin Wire Ethernet). Ethernet operates over a
customized coaxial cable configured as a bus and restricted to a maximum length of 500 meters-point-topoint. Ethernet transmits data at 10 Mb/s on a baseband network. Cheapernet uses the more common RO58 cable and has a maximum point-to-point distance of
185 meters; its data transmission rate is also 10 Mb/s.
Other types of CSMA/CD networks are IOBROAD36
(IO-Mb/s Broadband, 3600m on Coax) and IBASE5 (1
Mb/s Baseband, 500m on standard telephone wire).

Intel has introduced the 82504TA Transceiver Serial
Interface (TSI), the 82505TA Multiport Repeater controller (MPR), and the 82521 Serial Supercomponent
(SSC). These products simplify designing Twisted Pair
Ethernet LANs based on the emerging 10BASE-T standard. These LANs are compatible with existing ANSI/
IEEE 802.3 networks at the Physical Signaling layer
and the MAC portion of the Data Link layer. This
means that a Twisted Pair Ethernet LAN built with
these products will be software compatible with current
802.3 networks and can connect to other 802.3 networks through the standard Attachment Unit Interface
(AUI) port of a Multiport Repeater.

The cost of the cable and its installation and reconfiguration has been a factor in the acceptance of CSMA/
CD LANs. The members of the IEEE 802.3 Working
Group, including Intel, have recognized this, and we
are addressing this issue. We are· preparing a new
CSMA/CD standard (IOBASE-T) that operates at
10 Mb/s with a 100m point-to-point range and uses
unshielded, twisted-pair wiring-the common telephone wire already installed in most buildings: Besides
using a less expensive wire type, 10BASE-I0 (TPE)
uses a star topology that can operate concurrently with
normal telephone traffic, and other services, in a parallel cable plant.

A Twisted Pair Ethernet LAN comprises several ele-'
ments: data terminal equipment (DTR), medium attachment units (MAU), multiport repeaters (MPR),
and the cable plant. More complex networks, which
interconnect with existing 802.3 networks, are made
possible by using the 802.3-standard AUI port of the
MPR. Figure 1 illustrates a network that uses all these
elements..

Besides its active participation in the IOBASE-T Task
Force, Intel is now marketing products based on the
work of the task for(;;e. With these products-the
82504TA Transceiver Serial Interface, the 82505TA
Multiport Repeater controller, and the 82521 Serial Supercomponent-our customers can design high-speed
LANs that operate over unshielded twisted pair wiring,
which is usually already installed. These networks can
coexist with existing CSMA/CD networks; that is, they
can be integrated into a single network interfacing with
already installed Ethernet or Cheapernet networks.
Furthermore, Intel is committed to maintaining compatibility and conformity with the emerging standard.

Figure 1 shows three types of DTE and MAU combinations. Two have embedded MAUs, the other has an
external MAU connected to the DTE node by a standard AUI cable. Embedded MAU designs either use
the 82504TA, and its associated circuitry, or the
82521 TA SSC. The multiport repeaters are designed
around the 82505TA, they also contain one 82504TA.
Each of the eleven twisted pair ports contains an embedded MAU. The cable plant is standard telephone
wire, 4- or 25-pair unshielded twisted pair (26 to 22
gauge). Each segment uses two twisted pairs for data, .
one for transmission and one for reception, and the unused pairs can carry other services as well. In a TPE
design the maximum node-to-repeater distance is 100
meters.

1-290

Ap·324

10 Mb/s Star Wired 100m Cable Length

MPR

292057-1

Figure 1. Typical TPE Network

1-291

Ap·324
The transmit circuitry incorporates the predistortion
algorithm adopted by the lOBASE-T Task Force. This
algorithm improves overall system jitter performance
by reducing the amount of jitter induced by the twisted
pair. The line drivers will drive at full amplitude during
"thin" (50 ns) pulses and the first half of "fat" (100 ns)
Manchester pulses. They will reduce their drive level to
33% during the second half of "fat" Manchester'pulses.
This prevents the twisted pair from overcharging during the fat pulses. Without this predistortion, the overcharge would cause a delay in the zero crossing following the "fat" bit, resulting in more induced jitter. Figure 2 shows the idealized output waveform for the predistorted signal at the transmitter.

2.0 SYSTEM DESCRIPTION

2.1 Network Description
The network shown in Figure 1 is a typical representation of TPE networks designed with Intel TPE products. The network follows the lOBASE-T draft standard specifications wherever possible. We recommend
that network designers follow the same practice. Table
1 compares the TPE network features to the earlier
10 Mb/s standards, and Table 2 compares TPE networks based on the Intel products to those based on the
most likely outcome of the lOBASE-T Task Force deliberations.

MAD Line Receiver: The MAD line receiver is also dc
isolated by a transformer. It must have a matched differential impedance such that the return loss is at least
15 dB from 5 MHz to 10 MHz. The line receiver must
operate properly in the presence of a signal having a
350 mV to 2.8V differential. It must detect the start of
Idle within 1.8 bit times, and must include a squelch
circuit that rejects, as noise, any signals less than
250 mY, and accepts signals greater than 350 mV having a pulse width greater than 20 ns.

2.1.1 MEDIUM ATTACHMENT UNIT (MAU)

The MAD (i.e., the transceiver) provides the required
circuitry for interfacing with the twisted pair wire. It
performs several functions; e.g., line driving with predistortion, line reception, and collision detection. Multiport repeaters and DTEs can contain embedded
MADs or attach to external MADs.
MAD Line Drivers: The transmitter is designed to
drive a 960 properly terminated cable and must meet
all its specifications under this load (unless otherwise
specified). A transformer provides dc isolation from the
twisted pair, and the transmitter has a matched source
impedance of 960 ± 20%. It will achieve a drive level
of 2.2V to 2.8V peak differential. The power spectrum
amplitude will be less than - 30 dB at, or above,
30 MHz from its 10 MHz value. The signal is Manchester encoded like 10BASE5 and lOBASE2.

Collision Detection: The MAD detects collision by noting simultaneous activity on the transmit and receive
pair. No provision is made for receive-based collision
detection. When a transmitting station detects a collision it begins the normal 802.3 collision sequence of
jam, random backoff, and retransmit. When a repeater
detects a collision it also begins a jam and it enforces
the minimum frame length of 96 bits.

Table 1. Comparison of Network Features
Feature
Wire
Topology

TPE

10BASE5

10BASE2

Unshielded TP

Yellow Coax

Thin Coax

Star

Bus

Bus

100m

500m

185m

Software

Existing

Existing

Existing

Controller

82586/8259x

82586/8259x

82586/8259x

Data Rate

10 Mb/s

10 Mb/s

10 Mb/s

CSMAlCD

CSMAlCD

CSMAlCD

Segment Length

Access Method

Table 2. Differences between Current TPE and Expected 10BASE·T
Feature
Squelch
Collision Detect

CurrentTPE

10BASE-T

Single Pulse

Multiple Pulse

Tx and Rx Active

Tx and Rx Active for 5 Bits

Link Integrity

None

Single Linkbeat

Jabber Function

None

Watchdog Timer

DO -- 01 Loopback

None

Supported

1-292

Ap·324

Coax Cable
Tx Waveform

o

o

o

TPE
Tx Waveform

292057-2

Figure 2. Predistortion Waveform
2.1.2 MULTIPORT REPEATER

The Multiport Repeater is the central point in the starconfigured network. It is usually located in a telephone
closet or some other central wiring point. The link segments (repeater to node wiring) can then' be run using
available twisted pairs in the existing telephone cable
plant or a dedicated parallel cable plant. The repeater
conforms to the ANSI/IEEE 802.3c-1988 standard
for repeaters. It has eleven twisted-pair ports (embedded MAUs) and one AUI port.
A block diagram of an 82505TA-based repeater is
shown in Figure 3. It uses one 82505TA, one 82504TA,
eleven TP port processors, two 74LS529 latches, a
74LA154 decoder, and an AUI interface processor. The
82505T A handles the repeater state functions such as
automatic preamble regeneration, minimum frame
length enforcement, signal retiming, collision detection
and jam, and control for the LED status indicators.
The 82504TA handles Manchester decoding and clock
recovery for the incoming data packet. The AUI interface processor contains the DO line drivers and the DI
and CI line receivers as required by the ANSI/IEEE
802.3-1985 standard for AUI connectors. The
72LS 154 decoder disables the transmitter on the receiving port, and the 72LS259 latches control the status
LEDs.
.
During normal transmission without contention (i.e.,
no collisions) the repeater detects the transmitting port
and immediately begins automatic preamble regeneration (APR) to all other ports. It routes the incoming
data to the Manchester decoder and begins loading its
internal FIFO. When the FIFO reaches its threshold

the repeater ceases APR and begins to send data from
the FIFO. This data is Manchester encoded and retimed before it is rebroadcast. When a collision occurs,
the repeater stops broadcasting from the FIFO and begins transmitting a jam pattern. It continues to jam
until the collision ceases and at least 96 bits have been
transmitted to each port (minimum frame length enforcement).
The repeater also supports autopartitioning and jabber
protection. These two features prevent faulty nodes
from bringing the network down. When such a fault is
detected, the port in question is removed from the network, and the remainder of the network resumes normal operation. The repeater continually monitors the
faulty port, and when the fault is fixed the port is reconnected to the network.
2.1.3 DATA TERMINAL EQUIPMENT

Data Terminal Equipment (DTE) includes usernodes,
file servers, and other devices that can originate and
accept data packets. A TPE network uses the same controllers as other 802.3 networks. These are Intel's
82586, 82590, and 82592, as well as any future Intel
Ethernet controllers. This ensures a design continuity
that allows for migration from Ethernet or Cheapnet
designs to Twisted Pair Ethernet. The only part of the
design that requires redesign is that between the controller and the connector.
I~tel's product line supports two DTE designs. Over
the twisted· pair they are functionally equivalent; however, they differ in the way they interface to the host

1-293

inter

AP·324

'82505 MPR
82504 TSI

AUI INTERFACE

AUIRxO
AUICRS

TRxO

AUICOT

TRxO

TPS

TPS

TRMT

MCV

MCV'

TRMT

CRS

CRS

TPEN

RxC

RxC

RxO

RxO

POC
TRO'"
TCS'"

LEOF

LE08
TP PORT 1'"
LED7

POC
. TR01'"

LEO'"

TCS1'"

292057-3

Figure 3. Repeater Block Diagram

LAN controller. Figure 4 shows the first DTE design.

Table 3. Pin Assignments for MOl Connector

It is based on the 82504TA, and comprises the

82504TA, the interface logic, the twisted pair.transmitters, and the twisted pair receivers. This circuit contains an embedded MAU; i.e., it connects directly to
the twisted pair wire. The second DTE design, shown
in Figure 5, also contains an embedded MAU. It is
built around the 82521TA Serial Supercomponent and
interfaces directly with the LAN controller and the
twisted pair. The complete twisted pair design consists
of an 82521TA and the qonnector. External MAUs,
which interface a standard Ethernet AUI node to the
twisted pair, are also allowed. External MAUs are part
of Intel's future product plans.
2.1.4 LINK SEGMENT

A link segment connects two twisted pair Medium Attachment Units (MAUs); it comprises two Medium Dependent Interface connectors (RJ-45, 8-pin standard
telephone connectors), two pairs of twisted pair wire
(note to exceed 100m) and a crossover. The connector's
pin assignments are shown in Table 3.

Pin

Signal

1
2

Transmit Data + (TO + )
Transmit Data- (TO-)
Receive Data + (AD + )
Not Used
Not Used
Receive Data - (RD - )
Not Used
Not Used

3
4

5,
6

7
8

The crossover function connects the TD outputs of one
MAU to the RD inputs of the other. This function can
be implemented externally or embedded within a
MAU. If the function is embedded, then the signal
names on the connector refer to the remote.MAU. That
is Pin 1 (TD +) on a MAU with an embedded crossover is connected to the Transmit Data (+) of the remote MAU, and to its own Receive Data (+). The
crossover function is defined by the following connections between MAU A and MAU B.

1-294

inter

AP-324

OTE

= High

CLK(20 MHz)

TRxO

RO+

TPS

z

82504TA

:3;

Transceiver

'- C

Serial
Interface

iJe
c_
G> 0

RO-

TRMT

Analog
Front End

TRMT

TO+

... "
.., C

TO-

~o

'0
1lII G>

'" 0~

TPEN
POC

292057-4

Figure 4. 82504TA Based DTE Block Diagram

'-

.

CTS

G> "

TxC

TxC

Co>

TxO

TxO

e~
_N
o

III

ON

_co

RxC

RxC

c

•

'-CO
G>1lI

.eN
~CO

TO+

TD+

TD-

TO-

CTS
'-

Ill;:!

82521TA
RO+

RO+

RO-

RO-

-

....., "c
I

G>

~8

292057-5

Figure 5. 82521TA Based DTE Block Diagram

1·295

inter

Ap·324

MAUA

MAUB

TD+ 1

3RD+
6RD'1 TD+
2TD-

TD- 2

RD+ 3
RD- 6

Cheapernet networks they have an implicit software
compatibility. That is, Twisted Pair Ethernet designs
based on the 82586 (8259x) will be software compatible
with Ethernet/Cheapernet design based on the 82586
(8259x).

When an embedded crossover function is used in a
DTE to repeater connection, the crossover must be embedded in the repeater MAU. in general, repeater
MAUs have an embedded crossover, and DTE MAUs
do not. With proper use of the crossover function repeaters can be cascaded through twisted pair ports, and
two DTEs can be connected in a point-to-point network. Repeaters can be cascaded in two' ways. First,
one twisted pair port on a repeater can be designed to
have a switched (optional) crossover function. This enables a DTE connection on that port when the crossover is active, or a repeater connection when the crossover is disabled. Secondly, twisted pair ports with embedded crossovers can be connected by using a third
external crossover.

2.2 Interoperation with Existing
802.3 Networks
Twisted Pair Ethernet networks that use Intel's Ethernet controllers and TPE products are fully compatible
with existing 802.3 networks at the Medium Access
Control and Physical Signaling levels. Therefore, TPE
networks can be integrated with existing 802.3 networks to form one large network. The IEEE 802.3c1988 standard allows connecting different types of
lO-Mb/s networks. Because the repeater definition extends to a DTE type AUI connection on each port, the
type of wiring is determined by the choice of MAU.
Optionally, a repeater can have embedded MAUs on
any of its ports. The only requirement is that functionality at the Medium Dependent Interface point (e.g.,
'
coax tap or twisted pair connector) be maintained.
The 82505TA Multiport Repeater provides embedded
MAUs on 11 of the 12 ports, and an AUI connection
on the remaining port. This allows creating local twisted pair subnetworks that are connected to an Ethernet
backbone. Care must be taken not to violate the system
topology rules of 802.3 networks. The most important
of these are: (1) only one active signal path is allowed to
exist between any two stations on the network and (2)
no more than four repeaters are allowed in the signal
path between any two stations on the network. There is
an overall limit of 1024 stations on a network (repeaters
do not count as stations).

Two minor software configuration changes are required
when the 82504TA and 8252ITA are used. These
changes will not 'be necessary in future Twisted Pair
Ethernet products. Both these changes can be handled
by the application-specific soft~are driver for the TPE
application.
• Manchester Encoding. The Ethernet controller
needs to be configured for Manchester encoding.
For the 82586, bit 2, byte 14 of the CONFIGURE
command must be set to 1. For the 8259x, bit 2, byte
9 of the CONFIGURE command must be set to 1.
• External Loopback. The 82504TA and the 8252ITA
do not support the external loopback mode of the
Ethernet controllers. Software packages that used
this mode will fail without a workaround. Normally,
this is only an issue for diagnostics that use this
mode during self-test. This problem can be avoided
by modifying the software driver to look for external
loopback mode, and to do its own software loopback
when appropriate (based on a destination address
check).

3.0 NETWORK SYSTEM COMPONENT
DESIGN
The design of various TPE network system components
is presented, here. DTEs with embedded MAUs are
shown first, and then the repeater design is shown.

3.1 Designing a DTE Node Based on
the 82504TA
Figure 4 has shown a DTE node with an embedded
MAU based 011 the 82504TA. It showed the Ethernet
LAN controller, the 82504TA, the analog front-end,
and the connector. As in previous Ethernet designs, the
LAN controller provides the MAC services such as
transmission deferral, collision backoff and retransmission, CRC generation and checking, and address checking. It also provides the host interface. The 82504TA,
in conjunction with the analog front-end, provides both '
the Physical Signaling and Physical Medium Attachment services. These include carrier sense, collision detect, Manchester decoding, clock recovery, line driving,
and line receiving. The analog front-end handles the
line driving and receiving functions from the 82504TA.
3.1.1 HOST TO ETHERNET LAN CONTROLLER

2.3 Software Compatibility
Because the twisted pair networks use the same controller chips (82586 and 8259x) as current Ethernet and

The interface of the Ethernet LAN Controller is discussed in previous Intel Ap Notes, AP-274 and
AP-320.

1-296

intJ

AP-324

3.1.2 82504TA TO ETHERNET LAN
CONTROLLER

The 82504TA to controller interface consists of the di·
rect connection of TxC, TxD, RxC, RxD, and RTS.
The CRS signal to the controller is generated by a logical AND (a 74F08 is used) of CRS from the 82504TA
and RTS. CDT is the NAND of TPS and an inverted'
RTS; both the NAND function and invert function are
done by a 74FOO.
For clocking the 82504TA a clock oscillator is recommended. Many that meet the requirements of the device
are available commercially. It must meet the following
specifications.
Frequency Tolerance ..................... ~0.01 %
Rise and Fall Times ........................ ~ 5 ns
Duty Cycle ...................... 40/60% or better
Output .......................... TTL compatible
The 82586 and the 82504TA have two specification incompatibilities. These are data sheet incompatibilities
only, and will not affect performance. Work is in progress to ensure that the 82586 and 82504TA specifications are fully compatible.
• TxD setup time. The 82504TA requires a 10 ns setup time from TxD to the TxC edge. The 82586 specifies that TxD will change within 40 ns of the previous TxC edge. Therefore, if the TxC duty cycle is
not exactly 50% the TxD setup time is violated.
However, the 82586 actually places the TxD edge
approximately 25 ns from the previous TxC edge,
and it never exceeds 30 ns. The next revision of the
82586 data sheet will correct this specification problem.
• TxC duty cycle. The 82504T A does not specify the
TxC duty cycle; however, the worst case would be
better than 40/60% based on the high- and low-time
specifications and signal rise and fall times. The
82586 data sheet requires a 45/55% duty cycle for
Manchester encoding. In fact, the tight duty cycle is
only important when control of the TxD duty cycle
is important. The 82504TA can tolerate the worst
case TxD duty cycle generated by the 82586 with a
worst case TxC, therefore there is no problem. The
82586 specification will become a recommendation
in the next revision of the data sheet.

3.1.3 ANALOG FRONT-END
The analog front-end is shown in Figure 6. It consists
of two main sections, Transmit and Receive. The trans-

mit section contains the interface, the line drivers, the
EMI filter, and the line coupling devices. The receive
section consists of the line coupling devices, the EMI
filter, the line receivers, and the squelch circuitry. The
line coupling devices and EMI filter are similar for both
the transmit and receive sections, and will be described
in a common section.
The 82504TA to Line Driver Interface. The 82504TA
to line driver interface consists of the four signals from
the 82504TA (TRMT, TRMT, PDC, and TPEN), a
quad XOR (e.g., 74F86), and quad line drivers. The
design shown here uses an octal line driver
(74ACT244) with the drivers paired. The four pairs are
configured using a voltage summing circuit to give two
differential drivers, one at 67% power, and the other at
33%. During "thin" pulses and the first half of "fat"
pulses, the two differential drivers act in unison to give
100% power. During the second half of "fat" pulses,
the 33% driver is inverted to provide only 33% power
as required by the predistortion algorithm.
The circuit operates as follows. The TPEN signal is the
enable signal for the drivers. It is asserted by the
82504TA whenever the node is transmitting. During
idle, it is deasserted, and the driver enters the tri-state
mode. The Manchester data~rovided by the
82504TA on the TRMT and TRMT lines, and each
signal is fed into two XOR gates. One of the XORs for
each signal has one input grounded, therefore it acts as
a non-inverting buffer. The output of these XOR gates
feeds the two line drivers composing the 67% differential driver. Therefore, the 67% driver is always driving
the exact Manchester pattern. The other XOR gates are
also fed by the PDC signal. This signal is low for "thin"
pulses and the first half of "fat" pulses, and it is high
for the second half of "fat" pulses. These XOR gates
feed the 33% differential driver. The combination of
the PDC signal and the XOR gates ensures that the
33% driver follows the 67% drivers when 100% power
is required, and inverts when 33% power is required.
The design of this circuit is intended to present a constant driver impedance during packet transmission.
This is vital since variations in the matching of driver
impedance to the twisted pair cable impedance will
cause reflections resulting in added jitter.
High.Voltage Protection. To prevent damage to the active devices caused by high-voltage transients from the
twisted pair line, protection should be provided. We
recommend placing a pair of diodes on each of the four
differential signals (two transmit and two receive) as
shown in Figures 7 and 8. The diodes connect to the

1-297

inter

AP-324

74F86

74ACT244
22A

TRt.tT

q

A

FILTER

0

and
LINE
COUPLING
DEVICES

PDC

TRt.tT

2

B

....
0

If) .....

22A·

«t-

"""
I

0

...., CI)
c::
a::: c::
0

1.19
TPEN

U

0
"""
If)
C'I

00

NE521

74F08

FILTER

3

and

TRxD

LINE
COUPLING
DEVICES

6

TPS
4
2

V

= 300 mV @ Vee = 5V

74F175

14
20t.tHz __~t-____~~____~~____~____~
CLOCK
292057-6

Figure 6. Analog Front End

± 5V power supplies. Tliese should be placed at the
interface between the active devices and the low pass
filters so the active circuits are protected and the filter
attenuates the transients.
Filter Design. The main function of the low-pass filter
is to remove the high-frequency components of the
transmitted signal without affecting the in-band frequencies (5 MHz to 10 MHz). The high frequency components can create electromagnetic interference (EMI)
above the levels permitted by FCC regulations. The design should provide minimum inband loss and minimum-in-band ripple while providing maximum atten-

uation of frequencies above 30 MHz with appropriate
roll-off in the transition band.
The Group Delay variation is another critical factor in
the design of the filter. The group delay is defined as
the variation in signal phase with the frequency. The
group delay variation is the derivative of the group delay. The group delay variation defines the difference in
propagation delay through the filter for the frequencies
of interest. These differences in propagation delay cause
amplitude and phase distortions in the signal, which
translate into jitter.

1-298

inter

AP-324

+5V
33pF

39pF

91 pF

A'

A

-5V
+5V

r~
~1

~1

~1
8'

8
39 pF

33pF

91 pF

-5V

High Voltage
Protection

Filter
292057-7

Figure 7. Tx Filter Section

+5V
91 pF

39 pF

33pF

C

C'

o

0'
91 pF

39pF

33pF

-5V

High Voltage
Protection

Filter
292057-8

Figure 8. Rx Filter Section

1-299

inter

AP-324

The impedance of the filter must be matched to both
the transmitter i~pedance and the line impedance.
Also, balance and grounding should be tightly controlled for proper operation. Due to these considerations we recommend a differential filter built syrnmetrically on each line of the differential pairs with the impedance matched at each end.

proper balance between the two ends of the transformers, the windings should be identical. To provide appropriate impedance matching in the frequency range of
interest, the transformers should have appropriate primary and secondary induc~nce (200 I-'-H typical) and
minimal interwindjng capacitance « 20 pF).

Filters that provide all these characteristics are presented in Figures 7 (transmit) and 8 (receive). Their characteristics meet the requirements of the twisted pair environment. The requirements are as follows.
Type .................... 7 Pole, Balanced Elliptical
I/O Impedance ...... 960 ± 15% (5 MHz to 10 MHz)
3 dB Frequency ................ 17 MHz to 19 MHz
50 dB Frequency ....................... 2 30 MHz
In-Band Ripple ........................... :s; 1 dB
Line Coupling Devices. The line coupling devices,
shown in Figure 9, include the transformers, common
mode chokes, and common mode noise filters. The
transformers provide ac coupling between the line and
the circuitry while providing dc isolation. The recommended minimum isolation is 2250 Vde. To provide

The common mode choke is provided to reject common
mode radio frequency and electromagnetic interference
picked up from the unshielded telephone lines. It
should provide 1000 Vde isolation between the windings. The common mode choke has four windings, each
one connected with proper polarity, in series with the
receive and transmit twisted pairs. The balance of the
choke is very important in order to provide proper
noise cancellation while passing through the differential
signal unaffected. We recommend a common mode to
differential balance of 30 dB at all frequencies up to
20 MHz.
The common mode noise filter removes undesirable
high-frequency common mode signals picked up on the
line, or generated by the transmitter. These signals are
mainly generated by fast rise and fall times and signal
crosstalk in the transmitter.

.-.--

Common Mode Common Mode
Choke
Noise filter

2

292057-9

Figure 9. Line Coupling Devices

1-300

inter

AP-324

Line Receivers. The incoming receive signal passes
through the line coupli~g devices and the low pass filter. From there it is fed into a gated line receiver controlled by the squelch circuitry. The line receiver converts the received differential signal to TTL levels and
feeds it to the 82504TA. The receiver can be designed
using a zero crossing detector (e.g., NE521) and gated
with the TPS signal with a 74F08. A lOOn load resistor
is placed on the 74F08 output to reduce jitter induced
by the difference in the threshold mismatch between
the 82504TA input and the 74F08 output circuits.
Squelch Circuit. The, squelch circuit differentiates noise
from valid incoming data on the receive pair. It does
this by detecting signals that are above a preset voltage
level for a sufficient period. When there is no signal on
the receive pair, the squelch circuit disables the line
receiver, and deasserts the TPS signal to the 82504TA.
When a signal above the threshold arrives, TPS is asserted, and the line receiver is enabled. The squelch
circuit ensures that the receive circuits in the 82504TA
are operating only during packet reception. The
squelch circuit should meet the following specifications.
Reject ................................ < 250 m V
Accept ..................... > 350 mV and> 30 ns
The circuit shown in Figure 6 uses a high-speed comparator with an offset threshold. The output of this
comparator is fed to a retriggerable timing circuit that
controls the TPS signal to the 82504TA. To ensure recognition of the IDL (end of packet) signal, and to prevent midpacket deassertion of TPS, the timing circuit
should be set to detect positive pulses between 1.5 and
2.0 bit times (200 ns). The timing circuit can be implemented by using either a quad flip-flop (74FI75)
clocked from the 20 MHz clock generator or a retriggerable monostable multi vibrator with an appropriate
time constant. The first method provides better stability
and requires fewer discrete components. If the multi vibrator is used, then the selection of the timing components is critical. The timing capacitor must have very
low leakage with good temperature and aging stability.
The timing capacitor and resistor need to be as close as
possible to the IC to minimize stray capacitance and
noise injection.
Layout Considerations. The power and ground wiring
should conform to good high-frequency practice and
standards to minimize switching transients and parasitic interaction between various circuits. To achieve this,
the following guidelines are presented.
• Place bypass capacitors (usually 0.01 /-LF) on each
IC between Vee and ground. They should be located close to the Vee pins.

1-301

• Make power supply and ground traces as thick as
possible. This will reduce high-frequency cross coupling caused by the inductance of thin traces.
• Separate and decouple all of the analog and digital
power supply lines.
o Close signal paths to ground as close as possible to
their sources to avoid ground loops and noise cross
coupling.
• Connect all unused IC inputs (except as directed by
the manufacturer) to ground or Vee to avoid noise
injection or parasitic oscillations of unused circuits.
o Use high-loss magnetic beads on power supply distribution lines.
• Group each of the receive and transmit circuits, but
keep them separate from each other. Separate their
grounds.
" Layout all differential circuits symmetrically so
parasitic effects are also symmetrical.
" Layout the circuitry from the line connector to the
active circuitry (especially the EMI filter) on a
ground plane to prevent undesirable EMI effects.

3.2 Designing a Simplified DTE Node
Based on the 82521TA Serial
Supercomponent
A design for an 82521TA based DTE node within embedded MAU is shown in Figure 5. It includes all of the
functions described in Section 3.1, thereby relieving the
designer of those responsibilities. It is simple to use,
and it does not require mastering of pole-zero diagrams.
It is a direct interface from the Ethernet controller to
the RJ-45 connector.
Currently, the 82521 TA has the same specification incompatibilities with the 82586 as the 82504TA does,
and these will be resolved concurrently. There is one
added signal, Clear to Send (CTS), its implementation
is optional.
The layout of the 82521TA and the RJ-45 connector
should keep the TD +, TD, RD + , and RD signal lines
as short as possible. The power supply traces (Vee,
VEE, Voo, and ground) should be as thick as possible,
and bypass capacitors should be placed between each
power supply and ground. We also recommend laying
out the 82521TA on a ground plane.

intJ

Ap·324

The 82S0STA to Line Driver Interface. The 82505TA
to line driver interface consists of the fout signals from
the 82505TA (TRMT, TRMT, PDC, and TPEN), the
port enable (PEx) signal from the port disable control,
two NAND gates, a quad XOR (e.g., 74F86), and quad
line drivers. The design shown here uses an octal line
driver (74ACT244) with the drivers paired. The four
pairs are configured using a voltage summing circuit to
give two differential drivers, one at 67% power, and the
other at 33%. During "thin" pulses and the first half of
"fat" pulses, the two differential drivers act in unison to
give 100% power. During the second half of "fat" pulses, the 33% driver is inverted to provide only 33%
power as required by the predistortion algorithm.

3.3 Designing a Multiport Repeater
Using the 82505TA
Figure 3 shows the multiport repeater based on the
82505TA (with one 82504TA). The repeater contliins
11 twisted pair ports with embedded MAUs and 1 AUI
port. The 82505TA controls the operation of the repeater in accordance with ANSI/lEEE 802.3c-1988
repeater unit specifications; this includes signal retiming, automatic preamble generation, autopartitioning,
and jam signal generation. The 82504TA performs
Manchester decoding and clock recovery during an active incoming signal. Two addressable latches
(74LS259) are used to control the 16 LED indicators.
A 4-to-16 decoder (74LSI54) is used to disable the
transmitter of the receiving port during transmission
without contention. The Twisted Pair port functions
contain the line drivers, the line receivers, the filter, and
the isolation required for a twisted pair embedded
MAU. In addition, one AUI interface is present to provide access to existing (IEEE 802.3) 10 Mbls baseband
segments.
3.3.1 82505TA TO 82504TA INTERFACE AND
CLOCK GENERATION

The 82505TA to 82504TA interface is straightforward.
It consists of six signals directly connected between the
devices. The signals are TRxD, TPS, MCV, CRS, RxC,
and RxD. The interface is shown in Figure 3.
A single clock oscillator is recommended for clocking
the 82505TA and 82504TA. The requirements are identical to those shown for the DTE design using the
82504TA. They are:
Frequency Tolerance ..................... ~0.01 %
Rise and Fall Times ........................ ~ 5 ns
Duty cycle ...................... 60/40% or better
Output .......................... TIL compatible
3.3.2 TWISTED PAIR PORT DESIGN

The design of the twisted pair port circuits is nearly
identical to the analog front-end circuits of the DTE
design based on the 82504TA. It is shown in Figure 10.
The design consists of two mian sections, transmit and
receive. The transmit section contains the interface circuits, the line drivers, the EMI filter, and the line coupling-devices. Conversely, the receive section consists of
line coupling devices, an EMI filter, line receiver,
squelch circuit, and interface circuits. The line coupling
devices and noise filter are similar for both the transmit
and receive sections, and will be described in a common
section.

The circuit operates as follows .. The TPEN signal is
inverted and NAND'd with the individual port's Port
Enable signal. This generates the enable signal for that
port's drivers. It is asserted whenever the port is transmitting; i.e., when another port is receiving, or during a
collision jam. During idle it is deasserted, and the drivers enter the tri-state mode. The Manchester data is
provided by the 82505TA on the TRMT and TRMT
lines, and each signal is fed into two XOR gates. One of
the XORs for each signal has one input grounded,
therefore it acts like a non-inverting buffer. The output
of these XOR gates feeds the two line drivers composing the 67% differential driver. Therefore.. the 67%
driver is always driving the exact Manchester pattern.
The other XOR gates are also fed by the PDC signal.
This signal is low for "thin" pulses and the first half of
"fat" pulses, and it is high for the second half of "fat"
pulses. These XOR gates feed the 33% differential driver. The combination of the PDC signal and the XOR
gates ensures that the 33% driver follows the 67% drivers when 100% power is required, and inverts when
33% power is required.
The design of this circuit is intended to present a constant source impedance during packet. transmission.
This is vital since variations in the matching of driver
impedance to the twisted pair cable impedance will
cause reflec~ions resulting in added jitter.
High.Voltage Protection. To prevent damage to the active devices due to high voltage transients from the
twisted pair line, high-voltage protection should be provioed. We recommend placing a pair of diodes on each
of the four differential signals (two transmit and two
receive) as shown in Figures 7 and 8. The diodes connect to the ± 5V power supplies. These should be
placed at the interface between the active devices and
low pass filters so that the active circuits are protected,
and the filter attenuates the transients.
Filter Design. The main function of the low-pass filter
is to remove the high-frequency components of the
transmitted signal without affecting the in-band

1-302

infef

AP-324

74ACT2-4'"

m"T~~:q~[~~~~~~~~~~~~~r---~
I

FILTER

,,'

LINE
COUPLING
DEVICES

""o
U

",2

.
g-

... u

iii

,I •c

'" ug

g-

'"1::o

PEx

1----=::---'

g-

FILTER

co,
LINE

:;
~

+-------:+---"""+-..,....-r~ cg~~~~G

v = 300mV 0 Vee '" 5'1

20t.lHZ_-.l==========..J
CLOCK

292057-10

Figure 10. TP Port x

(5 MHz to 10 MHz) frequencies. The high frequency
components can create electromagnetic interference
(EMI) above the levels permitted by FCC regulations.
The design should provide minimum in-band loss and
minimum in-band ripple while providing maximum attenuation of frequencies above 30 MHz with appropriate roll-off in the transition band.
The Group Delay variation is another critical factor in
the design of the filter. The group delay is defined as
the variation in signal phase with the frequency. The
group delay variation is the derivative of the group d~­
lay. The group delay variation defines the difference.m
propagation delay through the filter for the frequencIes
of interest. These differences in propagation delay cause
amplitude and phase distortions in the signal, which
translate into jitter.
The impedance of the filter must be matched to both
the transmitter impedance and the line impedance.
Also balance and grounding should be tightly controll;d for proper operation. Due to these considerations we recommend a differential filter built symmetrically on each line of the differential pairs with the
impedance matched at each end.
Filters that provide all these characteristics are presented in Figures 7 (transmit) and 8 (receive): Their ~hara~­
teristics meet the requirements of the tWIsted paIr envIronment. The requirements are as follows.
Type .................... 7 Pole, Balanced Elliptical
I/O Impedance .......... 96.n ± 15% (5 to 10 MHz)

3 dB Frequency ................ 17 MHz to 19 MHz
50 dB Frequency ....................... :;;: 30 MHz
In-Band Ripple ............ .' .............. :,; 1 dB
Line Coupling Devices.' The line coupling' devices,
shown in Figure 9, include the transformers, common
mode chokes, and common mode noise filters. The
transformers provide ac coupling between the line and
the circuitry while prmdding dc isolation. The recommended minimum isolation is 2250 Vdc' To provide
proper balance between the two ends of the transformers, the windings should be identical. To provide appropriate impedance matching in the frequency ~ange ~f
interest the transformers should have appropriate Primary a~d secondary inductance (200 ,...H typical) and
minimal interwinding capacitance «20 pF).
The common mode choke is provided to reject common
mode radio frequency and electromagnetic interference
picked up from the unshielded telephone lines: It
should provide 1000 Vdc isolation between the wmdings. The common mode choke has four windings, each
one connected with proper polarity, in series with the
receive and transmit twisted pairs. The balance of the
choke is very important in order to provide proper
noise cancellation while passing through the differential
signal unaffected. We recommend a common mode to
differential balance of 30 dB at all frequencies up to
20 MHz.
The common mode noise filter removes undesirable
high-frequency common mode signals picked up on the
line, or generated by the transmitter. These signals are

1-303

inter

AP-324

'mainly generated by fast rise and fall times and signal
crosstalk in the transmitter.

• Close signal paths to ground as close as possible to
their sources to avoid ground loops and noise cross
coupling.
• Connect all unused IC inputs (except as directed by
the manufacturer) to ground or Vee to avoid noise
injection or parasitic oscillations of unused circuits.,
• Use high-loss magnetic beads on power supply distribution lines.
• Group each of the receive and transmit circuits, but
keep them separate from each other. Separate their
grounds.
• Layout all differential circuits symmetricalIy so
parasitic effects are also symmetrical.
• Layout the circuitry from the line connector to the
active circuitry (especially the EMI filter) on a
ground plane to prevent undesirable EMI effects.

Line Receiver. The incoming receive signal passes
through the line coupling devices and the low pass filter. From there it is fed into a gated line receiver controlled by the squelch circuitry. The line receiver converts the received differential signal to TTL levels and
feeds it to the MPR. The receiver can be designed using
a zero crossing detector (e.g., NE521) and gated with
the TCSx signal with a 74F08.
Squelch Circuit. The squelch circuit differentiates noise
from valid incoming data on the receive pair. It does
this by detecting signals above a preset voltage level.
When there is no signal on the receive pair, the squelch
circuit disables the line receiver, and deasserts the
TCSx signal to the 82505TA. When a signal above the
threshold arrives, TCSx is asserted, and the line receiver is enabled. The squelch circuit ensures that the receive circuits in the 82505TA are operating oniy during
packet reception. The squelch circuit should meet the
following specifications:
Reject ................................ <250 mV
Accept ..................... > 300 mV and > 30 ns
The circuit shown in Figure 10 uses a high-speed comparator with an offset threshold. The output of this
comparator is fed to a retriggerable timing circuit that
activates the TCSx pin of the 82505TA. To ensure recognition of the IDL (end of packet) signal, and to prevent mid packet deassertion of TCSx, the timing circuit
should be set to detect positive pulses between 1.5 and
2.0 bit times (200 ns). The timing circuit can be implemented by using either a quad flip-flop (74FI75)
clocked .from the 20 MHz clock generator or a retriggera!>le monostable multivibrator with an appropriate
time constant. The first method provides better stability
and requires fewer discrete components. If the multivibrator is used, then the selection of the timing components is critical. The timing capacitor must have very
low leakage with good temperature and aging stability.
The timing capacitor and resistor need to be as close as
possible to the IC to minimize stray capacitance and
noise rejection.
Layout Considerations. The power and ground wiring
should conform to good high-frequency practice and
standards to minimize switching transients and parasitic interaction between various circuits. To achieve this,
the following guidelines are presented.
• Place bypass capacitors (usually 0.01 /loF) on each
IC between Vee and ground. They should be located close to the Vee pins.
• Make power supply and ground traces as thick as
possible. This will reduce high-frequency cross coupling caused by the inductance of thin traces.
• Separate and decouple all of the analog and digital
power supply lines.

3.3.3 AUI PORT
The AUI port circuitry is shown in Figure 11. It comprises interface circuits, the DO line drivers, two quad
o flip-flops (74FI75), and terminated line receivers for
the, DI (squelch and data) and CI (squelch only) cir~
cuits.
The CI squelch line receiver feeds the 0-0 and clear
inputs for one of the quad 0 flip-flop circuits. When a
signal larger than the squelch offset is seen, the flipflops are cleared and AUICDT is asserted. This continues for as long as CI is active. During the start of idle,
the squelch teceiver output is held high, and the flipflops set in sequence. After four clocks, 150 ns to
200 ns, the last flip-flop is set, and AUICDT deasserts.
It remains deasserted during the entire idle period.
The 01 line receivers work in much the same way, except that activity on CI, or an active transmission will
inhiJ?it AUICRS. The data channel on 01 is processed
without a voltage offset, and is gated by AUICRS. In
this way, the least amount of jitter is added on the
AUIRxD line, and the data channel is not sensitive to
idle noise.
The DO line drivers are controlled by the TPEN and
PEl 1. The drivers should activate when both are asserted. A voltage divider is provided after the drivers to
achieve the proper driver levels.
3.3.4 PORT DISABLE CONTROL
The Port Disable Control, shown in Figure 12, is performed by a 74LS154 4-to-16 decoder. During transmission without contention, the address of the originating port is given to the decoder, and the control line
asserted. This in turn disables the transmitter to that
port. When a transmit based collision occurs, the controlline to the decoder is deasserted, and jam is broadcast on all ports.

1-304

inter

AP-324

NE521
CI+
CI-

~

c:I

:1l
AiTICDT
20 MHz
CLOCK

V=300mVOVCC =5V

~

L.

01+
L.

2u

.,c:

01-

G)

E
.E.,
c:

~

c:

I-

0
U

NE521

".

u

..'" ..'"
c:I

0

iii

c:I

L.

AUICRS

~

G)

..

::>

E

-<

.,
15
.,
.,"0::

.c:

W

1::
0
":;:;

20MHz
CLOCK

:;

AUIRXO

::;

74ACT244
10011
DO+

TRMT

10011
00-

TRMT

. .
c:I
....

c:I
....

PEll

'fiiEN

292057-11

Figure 11. AUI Port

1-305

intJ

AP-324

3.3.5 LED CONTROL

4.0 UPGRADE PATH TO THE FINAL
10BASE-T STANDARD

LED' control (Figure 13) is handled by two 8-bit addressable latches (74LS259). The controller cycles
through the addresses for the LEOs every 105 ms, and
will tum each one on or off. The three least significant
address bits (LO-L2) for the LED control are fed to
each 8-bit latch. The most significant address bit (L3)
controls the enable line to the two packages. When it is
strobed by LEDSTRB, the LEDCTRL signal determines the state of the LED.

As the IOBASE-T Task Force completes writing the
standard, Intel is finalizing its plans for a standardcompliant product. Our commitment is to provide an
upgrade to the final standard as soon as possible, while
minimizing the effort required by our customers to implement it. In addition, Intel will ensure that networks
designed with our current (prestandard) products will
coexist with lOBASE-T networks. That is to say, there
is no built-in -obsolescence with these current products.

74LS154
PDO
,:,.
CJ

PDl

0

iii
....
II)

....0
II)

a.

II)

0::

PD2
PD3
PDCTL

23

22
21
20
19
18

A

PEO
PEl

B

PE2

C

PE3
D

PE4

G1

PE5

G2

PE6
PE7

1::
0
a.
:;:;

PE8
PE9

:;
~

Qll

13

PE10
PEll
292057-12

,:,.
CJ

0

LO
Ll

iii
....
(I)

L2

II)

LEDCTRL

....0
a.

II)

0::

1::
0
a.

:E
::J

~

L3
LEDSTRB

inter

AP-324

Prestandard and standard-compliant networks will coexist at the AUI interface. Network sections based entirely on prestandard components will be able to connect to network sections based entirely on compliant
components through coax backbones, or through external MAUs connected to the AUI ports of the repeaters.
The simplest upgrade path will be a DTE designed with
the 82S21TA Serial Supercomponent. Here, the user
will merely have to substitute the standard-compliant
Supercomponent, and his design will work. At this time
we are planning to include a prestandard compatible
mode for the device, which will be a strapping option.
Since the 82S21TA has defined the pins required for
this mode, users can include either mode of operation
in their designs, or the ability to select between them.
Upgrading 82S04TA designs will be slightly more difficult, since the standard-compliant device will have
more functions integrated; e.g., line drivers, line receivers, and interface logic. These functions were not defined by IOBASE-T when the 82S04TA was designed,
therefore they were intentionally not included. This will
require that the system designer change the design for
DTE nodes based on the 82S04TA, but will allow reductions in the bill of material cost and board space
requirements for the design.
Intel intends the 82S0STA standard-compliant product
to incorporate the Manchester decoder and clock recovery functions; therefore, an 82S04TA will not be
needed in the repeater. Intel further intends the device
to be backward compatible with the previous version,
that is, the new controller can be plugged into an old
controller socket. The standard-compliant MPR will
also include the capability for parallel expansion, allowing repeater design with more than II twisted pair
ports.
Overall, the upgrade from the current products to standard-compliant products is easy, and incorporates low-

er cost, higher functionality, or both. The 82S21TA
SSC was designed to eliminate the effort (and the risk)
required for compliance. In both the case of the
82S04TA and 82S0STA, the upgrade will require minimal redesign, and will maintain or reduce the requirements of material, board space, and power consumption.

5.0 SUMMARY
In this Application Note, a 10 Mb/s Local Area Network has been introduced that uses standard telephone
twisted pair wiring and a star configuration for cost
savings and flexibility. It is based on the IEEE 802.3
standard for CSMA/CD medium access. It complies
with the standard at the MAC and PLS levels, and
follows the emerging 10BASE-T standard at the PMA
level. This network type is fully software compatible
with and can coexist with current Ethernet or Cheapernet networks. The hardware connection is made by including an 802.3 defined AUI port and complying with
the repeater standard ANSI/IEEE 802.3c-1988.
Intel has introduced three products for designing network components (DTEs and repeaters). DTE design
can be done with either the 82S21TA Serial Supercomponent or the 82S04TA Transceiver Serial Interface.
The Supercomponent contains all the circuitry required
between the Ethernet controller and the RJ-45 connector. It also provides a transparent upgrade path to a
standard compliant design. Multiport repeaters can be
designed using the 8250STA with an 82S04TA. It allows for II twisted pair ports and I AUI port.
Finally, upgrade paths to the upcoming IOBASE-T
standard for Twisted Pair Ethernet were presented.
This simplest path is for designs which use the supercomponent; however, all designs can be easily upgraded
to the standard when it is available.

1-307

APPLICATION
NOTE

AP-327

July 1989

Two Software Packages
for the 82592 Embedded·.
LAN Module

JOSEPH DRAGONY
APPLICATIONS ENGINEER
URI ELZUR
SYSTEM VALIDATION
INTEL CORPORATION

Order Number: 292062-001
1-308

intJ

AP-327

1.0 INTRODUCTION
This Application Note is a companion piece to AP-320,
Using the Intel 82592 to Integrate a Low-Cost Ethernet
Solution into a PC Motherboard. While AP-320 deals
mostly with hardware issues this Application Note
deals almost entirely with software. Two programs are
presented. One is written in "C" and the other is written in assembly language. The NetWare driver presented in this Application Note is a revised version. of the
code in section 7 of A~-320.

1.1. Objective
This Application Note was written to serve as a design
example to aid the user in developing software for the
Intel 82592 LAN Controller. Two programs are provided. The ELM Exerciser Program demonstrates the
embedded LAN architecture and provides the user a
tool for exercising the 82592 in a system environment.
This program is written mainly in the "C" programming language with assembly language used when necessary. The NetWare driver provides an example of an
interface to a widely used networking package. The
NetWare driver provides an avenue for evaluation of
the ELM concept in a real LAN environment. The
Net Ware driver code provides routines that accomplish
all of the common functions required by LAN interfaces. This code should be adaptable to drivers for network software packages other than NetWare without
too much effort. The NetWare driver is written completely in assembly language.

'1.2 Acknowledgements
We would like to thank Dror Avni, Gideon Prat, Zeev
Sperber and Koby Gottlieb of Intel Israel Design Center for their excellent support during the development
of the Exerciser software. We also thank Ben L. Gee of
San Jose, California and Drex Dixon of Novell for their
advice during the development of the NetWare driver
software.

2.0 ELM HARDWARE
The ELM is intended to demonstrate the concept of
embedded LAN connections. This concept could be implemented either directly on the motherboard of a microcomputer system or as a socket option similar to
todays math coprocessor sockets. The ELM illustrates
how little board space this concept requires, and also
makes it possible to evaluate the performance potential
of the nonbuffered architecture. The ELM is not intended as a final solution. Additional hardware features
such as a DMA stop register and DMA capable of
chaining noncontiguous buffers could simplify the driver software.

The ELM is implemented as a small printed circuit
board containing an 82592 Advanced CSMA/CD
LAN Controller, two PALs, and two latches. It is connected by a ribbon cable to an analog module, which
provides the interface to the media. There are two analog modules available. They are an Ethernet module
and an Ethernet/Cheapernet module. Using this approach, other analog modules, for example, StarLAN
or twisted Pair Ethernet, could be implemented without
modifying the digital module.
The ELM is designed to function in PC AT compatible
systems. It has been used in the Intel SYP301 system,
Compaq Deskpro 386-16, Compaq Portable 386-20,
Compaq Portable 286, and both 6- and 8-MHz IBM
PC AT machines. The ELM takes liberties with the
refresh cycles of the PC. It does not sense the system's
refresh request and can cause refresh cycles to be
missed occasionally. In a commercial implementation a
timer should be used to limit the amount of time the
ELM can control the bus. The ELM hardware and
driver software are used daily by one of the authors as
his connection to our department LAN and no problems have been caused by the lack of a refresh kickoff
timer. The module uses two of the system's 16-bit
DMA channels to provide transmit and receive DMA.
Channels 6 and 7 are used. The module also uses the
IntlO interrupt line. None of these hardware requirements are jumper selectable. The module also requires a
small modification to the system motherboard. A connection must be made to the EOP pin of the DMA
controller to allow autoinitialization to be controlled by
the module for retransmission in case of collision. This
can be accomplished by soldering a binding post to the
EOP pin of the secondary 8237A DMA controller. In
cases where a connection to EOP cannot be made, the
software would have to be altered to allow retransmission to be controlled by the CPU.
As well as providing all required address decoding, the
two PALs interpret the Tightly Coupled Interface
handshake signals from the 82592 and generate control
signals to the latches and the DMA controller. These
signals accomplish two things. First, at the end of a
received frame, the Tightly Coupled Interface generates
a handshake. The PALs convert this to a signal that
latches the last location of the frame just received. The
82592 transfers length and status information into the
memory as the last four words of a received frame.
Using this information it is possible to reconstruct a
string of frames in memory. This feature of the module
allows reception of back-to-back frames. Second, when
a collision occurs, the Tightly Coupled Interface generates a handshake, which the PALs use to send an EOP
to the system's DMA controller. This allows the ELM
to execute a retransmission without intervention by the
CPU. This feature serves two purposes. The CPU is
free to continue the processing it is'involved with, and
the node is also guaranteed fair and equal access to the
media. When the CPU must actually handle retrans-

1-309

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AP-327

mission it is unlikely that the station will be ready to
retry access to the link in a timely fashion.

memory containing the packet to be transmitted, The
driver routine DriverSendPacket is then called. DriverSendPacket processes the ECB and constructs the me. dia specific frame, which allows the information to be
transmitted to the target node on the Iletwork. When
the attempt to transmit the frame has been completed,
the driver stuffs a completion code into the proper position in the ECB and passes it back to IPX through a
call to the IPX routine IPXHoldEvent. IPX puts the
ECB in a queue and later does the processing required
to complete the operation.
.

Section 2 Design Documentation for
82592 Embedded LAN Module Novell
NetWare* Driver
3.0 OVERVIEW
The Novell NetWare* Driver for the 82592 Embedded
LAN Module (ELM) is the first NetWare driver internally generated by MCFG LAN Marketing. The purpose of the Embedded LAN Module project is to demonstrate the feasibility of an embedded Ethernet LAN
connection.By providing a driver for a very widely used
Network Operating System (the popular NetWare from
Novell, Inc.) we are attempting to provide an tool for
evaluating this concept under real network conditions.
This driver is a workstation shell driver. This section of
the Application Note is intended to be used in conjunc-.
tion with the program listing in Appendix C. It is presented as an adjunct to the comments in the source
code listing itself. Hopefully the text will shed the needed light where the source code comments fail to illuminate.
The first part of this section contains an overview of the
requirements of a NetWare driver to allow those unfamiliar with NetWare drivers to follow the discussion. A
bibliography is provided as an appendix for those who
desire more detailed information. The balance of the
section is a discussion of each routine the driver software. provides. Each routine is first explained from a
functional point of view. Then any hardware considerations are discussed. Where it is warranted, alternative
approaches to the routine are given.
This document is not meant to be a tutorial on writing
Novell NetWare driver software. It is a discussion of
the generation of a single driver for a particular piece of
hardware. This driver is a demonstration tool and is not
represented to be a commercial NetWare driver. Neither. the author nor .Intel Corporation accept any responsibility for the use or misuse of this driver or of this
documentation. For.complete information on NetWare
driver generation please contact Novell.
'
Novell's NetWare Network Operating System uses an
implementation of the Xerox Internetwork Datagram
Packet (IDP) protocol called the Internetwork Packet
Exchange (IPX) protocol. It provides the developer a
set of media independent services, and dictates a set of
services that the driver must provide. Information concerning transmit and receive operations are communicated between IPX and the driver by using Event Control Blocks (ECBs). For example, if Net Ware wants to
transmit a packet, a transmit ECB is prepared that contains address information and a list of fragments in
*NetWare is a registered trademark of Novell Incorporated

NetWare requires the driver to provide several routines
for its use. Some of these routines may not be required
by a driver and can be implemented as a simple return.
This driver implements the routines DriverDisconnect
and DriverOpenSocket as a return. The remaining routines are implemented and are listed below.

• DriverInitialize configures the LAN adapter hard.ware and any variables that need to be initialized at
start up time such as the node' address.
• DriverSendPacket and DriverBroadcastPacket are
implementect. as a single routine with two labels at
the entry point. This routine processes the transmit
ECB that is passed to it and make a best effort attempt to send it to the target node. It is not a guaranteed delivery routine.
• DriverISR is the interrupt service routine for the
driver and processes all interrupt events.
• DriverPolI checks to see if a transmit is in progress.
If there is no active transmit it returns. If a transmit
is underway DriverPolI checks to see if it has timed
out. If so, the transmission i~ aborted and its ECB is
returned with an error code.
• DriverCancelRequest searches the transmit queue
for the specified ECB and removes it from the
queue. It then stuffs the completion code and returns.
• DriverCloseSocket unlinks all pending ECBs for the
specified socket and returns them to IPX.
• DriverUnhook is used to disinstall the driver if no
active file server can be found during initialization.
This involves restoring the interrupt vector to its
original value and disabling the LAN adapter so it
will not affect system operation.
• SetInterruptVector is called by DriverInitialize to
insert the interrupt vector for the LAN adapter into
the correct location in the system's interrupt vector
table after saving any vector that is already there:

4.0 DRIVER SOFTWARE ROUTINES
4.1 Driverlnitialize
This is the first routine IPX calls when the driver software is being loaded. This routine is responsible for

1-310

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AP-327

initializing the LAN adapter hardware and any variables or memory structures required by the driver. It
also sets the interrupt vector in system RAM after saving any vector already there. When IPX calls this routine it specifies a point in memory for the initialization
routine to place the node address.
The first thing this driver does is set the IPX variable
"MaxPhysPacketSize" to 1024. This value is used when
attaching to a fileserver to negotiate the largest packet
size that will be passed between the two stations. This
allows transferring packets larger than the 576-byte default packet size between the fileserver and the workstation.
4.1.1 GENERATING A STATION ADDRESS
The next action generates a station address. Since the
ELM has no address PROM the driver generates the
address by using a combination of hard-coded numbers
and the value read from the system's real-time clock.
The real-time clock is read using function 2Ch of the
DOS interrupt 21h. The first two bytes of the address
are OOh and AAh, which are Intel's Ethernet code. The
next three bytes are the minutes, seconds, and hundredths of seconds read from the real-time clock. The
sixth byte is 7Eh, which' was a dysteieological choice on
the authors part. This technique gives a high likelihood
that several ELMs can be operated in a small network
without duplicate addresses occurring. A commercial
implementation of the ELM concept should be provided with a hard-coded address in PROM or EPROM on
the card. After the address bytes have been moved into
the drivers local variable array they are copied to the
location indicated by IPX in the DI register.
When the address initialization has been completed, the
driver initializes some parameters from the hardware
configuration table. This is mainly done as an example,
since there is only one possible hardware configuration
for this module. However, the code required to step
through the tables is provided.
4.1.2 INITIALIZING THE INTERRUPT VECTOR
Initializing the interrupt vector is the next action. The
interrupt number is read from the configuration variable confi~irq_loc and placed in the AL register.
The offset of the interrupt service routine is moved into
the BX register then SetlnterruptVector is called. SetInterruptVector first generates the mask variables for
the 8259A by writing a one into DL and then shifting it
left a number of times corresponding to the value
passed in AL. The unmask variable is then generated
by the negation of the value in DL. SetlnterruptVector
then saves the vector for the interrupt that the board
will use and inserts the vector for DriverISR in its
place. The routine then returns control to DriverInitialize.

Upon returning from SetInterruptVector the ELM is
enabled by a write to location 303h. The PALs decode
this write, and enable DMA and interrupts from the
ELM to the system (as well as reads and writes to and
from the 82592 registers). A Reset command is then
issued to the 82592.
4.1.3 INITIALIZING THE BUFFER VARIABLES
The driver must calculate the effective address of the
transmit and receive buffers to use the system DMA.
Since the PC architecture uses a static page register for
the upper address bits, checks must be made to ensure
that the buffers do not cross these hardware imposed
boundaries. This is accomplished through a call to
set_up_buffers. This routine sets up two buffers in
the lO-kB space allocated at load time. One buffer is
used fo~ a transmit buffer and as the parameter block
for commands th!!t require parameters. This buffer is
set up to be at least 1200 bytes long. All remaining
space is used for the receive buffer. The receive buffer is
implemented as a restartable linear buffer. This approach was taken to allow the use of the IPX routine
IPXReceivePacket, which requires the receive packet
to be contained in a single, contiguous buffer. IPXReceivePacket does most of the required receive processing itself which makes the driver simpler.
There are four basic conditions that can exist for the
buffer space with which the driver must work.
• The buffer space has no hardware boundary. See
figure 1.
• The buffer space contains a boundary, and the lower
section is too small to use (i.e., less than the 1200
bytes used for the transmit buffer). See figure 2.
• The buffer space contains a boundary, and the upper
section is too small to use. See figure 3.
• The buffer space contains a boundary, and both sections are usable. See figure 4.
In the first case the transmit and general purpose buffer
will be located in the first 1200 bytes of the buffer
space, and the receive buffer will occupy the remainder
of the space. In the second case the unusable fragment
is discarded by adding the length of the fragment to the
original starting address of the buffer. The total buffer
area is adjusted by subtracting the length of the fragment from the original length (lO-kB) of the original
total buffer area. The transmit buffer uses the first 1200
bytes of the buffer space. In the third case the starting
address remains the same and the total buffer area is
adjusted by subtracting the length of the unusable fragment from the original total buffer area. In these three
cases the required addressing variables can now be calculated. The fourth case adds one additional step. Since
both fragments are usable the larger fragment must be
determined. The receive buffer will be located in the
larger fragment. The receive buffer will be at least 5000
bytes and can be as large as 8800 bytes depending on
where DOS loads the driver.

1-311

infef

AP-327

_'andG~~Buftar

gpJ'",--

apace. 1200 byteS.

B

_Buller

TOIaI buffer space. 1200 bytes

IIuIIorEnd

292062-52

Figure 1. Buffer with No Hardware Boundary

Unusable PortiOn

~ 111M 1200 bytes)

OMA boundary

B

Traromil and General Purpose Buller
space. 1200 bytes.

c
_Buller

Total buner space - (A + B)

._._._. _ _ _ _ _ .... ____

nt.but_Slllp(12OObyteslrom.nd)

IlutIerEnd

292062-54

Figure 2. Buffer with Boundary and Unusable Portion at Top
BuI1er_
T"-'omG~PurposeBuffer
space. 12OObytes.

11'-""'--

B

_Buller

TotaI_r space • (A + C)

DMA boundary

C

Unusable Portion (.... than 1200 bytes)

Buller End

292062-53

Figure 3. Buffer with Boundary and Unusable Section at Bottom

1-312

inter

AP-327

BufferSIart

A
Transmi1 and General Purpose Buffer
space. 1200 bytes.

B
Potential Unusable Portion

DMA boundary

"'_bul_sIart

c
Receive Buffer
Total buffer space - (A -I- B)

-----------------------------------------

",_buLstop (1200 bytes from end)

Buffer End

292062-55

a
BufferSIart

A
Receive Buffer
Total buffer space - (B

-I-

C)

--------------------------------------

",_buLS1OP (1200 bytes from end)

Transmit and General Purpose Buffer
space. 1200 bytes.

C

Potential Unusable Portion
Buffer End

292062-56

b

Figure 4. Buffer with Boundary and Both Portions Usable

1-313

inter

AP-327

Once these initial calculations have been made set_
up_butTers uses this information· to generate the addressing information to be used to program the DMA
control channels and their respective page registers.
Since the 16-bit DMA channels are set up to provide
word moves only, the etTective address ofthe beginning
of the transmit and receive butTers must be shifted right
one place so only AI-AI6 are contained in the variable.
The least significant bit of the page register is not used
by the l6-bit DMA channels because A16 is generated
by the DMA controller. The receive channel requires
an artificial segment to be generated because the latches
contain an etTective address rather than an otTset to the
actual segment the butTer resides in. This artificial segment is used when the received packet is passed up to
IPX. Once the required variables have been initialized,
control is returned to DriverInitialize.
4.1.4 CONFIGURING THE 82592
With the DMA variables initialized, the driver can now
prepare to configure and initialize the 82592 Advanced
CSMA/CD LAN Controller. The transmit DMA
channel is used during configuration to allow the 82592
to read parameters from memory. To put the 82592
into 16-bit mode, the first operation to the 82592 after
reset must be a Configure command with zero in the
byte count of the parameter block. To do this the transmit DMA channel is set up to point to the beginning of
the transmit/general purpose butTer area. This is done
by first resetting the indexing flip-flop in the 8237 A,

and then enabling it by writing 10h to the command
register. This puts the 8237A into rotating priority, late
write, and normal (rather than compressed) timing.
Next the address of the first location of the transmit/
general purpose butTer is written to the 2-byte base address register of the 8237A (low byte first) and the
DMA page register. A "I" is written to the word count
register of the DMA controller. This allows two transfers to be made because the 8237A interprets this register as "transfer count - 1." The channel is then set up to
do the desired type of transfer by writing to the DMA
controller's mode register. Finally, the channel is unmasked by a ~rite to the 8237A mask register. After
moving "O's" into the first two words of the butTer
space, a Configure command is issued to the 82592.
DriverInitialize then enters a polling loop, reading register zero of the 82592 and waiting for the command to
complete. After the command has completed, an Interrupt Acknowledge is'issued to the 82592 to clear the
interrupt generated by the completion of the command.
All transfers that the 82592 makes through DMA will
be l6-bits wide from this point on.
The DMA channel is set up again as previously described; however, the word count is set to eight. This
allows the 82592 to read in its configuration parameters
from the transmit/general-purpose butTer area. The
configuration parameters are copied into the butTer
from the array confi~block by the CPU using a
MOVSB instruction with a REP prefix. CX contains an
18 decimal when the MOVSB is executed. When the

1-314

inter

AP-327

copy is completed a Configure command is issued and a
polling loop is entered to wait for command completion.
The parameters in the configure block set the 82592 to
function in the following manner. The serial mode is set
to high speed to allow Ethernet operation; both the
transmit and receive TCI modes are enabled;and slot
time, minimum frame length, preamble length are set to
the values required by Ethernet. After the command is
completed the generated interrupt is cleared.
4_1.5 SETTING THE STATION'S INDIVIDUAL
ADDRESS

The transmit DMA channel is again set up for use, this
time with a word count of three for use by the Individual Address Setup command. The node address is copied
from its place in memory to the Tx/GP buffer area, and
the IASetup command is issued to the 82592. After the
command is completed the interrupt is cleared by an
Interrupt Acknowledge command.
4.1.6 FINAL INITIALIZATION

The receive DMA channel is now initialized to point to
the beginning of the receive buffer. The word count is
set so the receive DMA cannot go beyond the end of
the assigned receive buffer area.
Next, the interrupt channel is unmasked to allow interrupt driven operation and a Receive Enable command
is issued to the 82592. The AX register is set to zero to
indicate successful completion of the initialization routine and control is returned to IPX. Should some part
of the initialization routine fail, AX would contain a
pointer to a $ terminated error message string in memory. On return of control IPX would display the specified message and terminate.

4_2 DriverSendPacket,
DriverBroadcastPacket
These two routines are treated as a single routine with
two labels at the entry point. The first action taken
when these routines are called is to disable interrupts
through a CLI command. The routine then determines
if any packets are queued for transmission. This is done
by checking the segment portion of the double-word
variable send_list to see if it is null. If it is, no frames
are queued and the packet is put in the first location in
the list. Flow then drops through to the start_send
routine, which does the actual transmission. (The
start_send routine will be detailed later.) If the transmit queue is not empty then DriverSendPacket searches
to the end of the queue and adds the packet there. The
routine then returns control to IPX. The queued packet

will be sent when it is reached in the list. The queue is
maintained as a linked list using a dedicated link field
in the transmit ECBs. The head is the ECB contained·
in the send_list variable and the tail is the ECB with a
null link field.
The start_send routine is a subfunction of DriverSendPacket. It is not called directly by IPX but it can be
called by DriverPoll in response to a transmission timing out when frames are queued for transmission. This
routine starts by clearing the interrupt and direction
flags through a CLI and CLD instruction respectively.
It then retrieves the length of the packet to be transmitted from the transmit ECB packet length field. The
packet length is compared to the minimum length required by Ethernet after a byte swap to allow arithmetic operations to be performed on it. If it requires padding the value is stored in the padding variable.
The byte count for the 82592 is then calculated and the
construction of the frame in the transmit buffer is begun. Since NetWare requires the Ethernet length field
be an even number start_send next increments the
byte count then performs a bitwise AND operation
with FEh. This ensures that the byte count is consistent
with the Ethernet length.
'
The first step in constructing the frame in memory is
to move the transmit byte count into the first word of
the transmit buffer. The byte count is stored low byte
first. The destination address is then copied from the
transmit ECB to the buffer by the CPU using MOVSW
instructions. It is not necessary to copy the source address to the transmit buffer since the 82592 is configured to do automatic source address insertion. After
ensuring that it is an even number, the length is moved
into the Ethernet header. Now the fragment list from
the transmit ECB must be processed. First the fragment count is moved into the AX register. This value
indicates the number of fragments the list contains. By
decrementing AX after each fragment is copied to the
buffer the completion of the fragment processing can be
determined. The address of the first fragment is loaded
into DS;SI, and the length of the fragment is loaded
into ex. The fragment is then copied into the buffer
through a REP MOVSW. If the fragment was an odd
length a MOVSB is done to finish the copy. The pointer
to the fragment descriptor list is indexed to the next
entry. AX is decremented and ifit is not zero the operations above are repeated until all the fragments have
been copied to the buffer. Once the fragment list is
completely processed any required padding is moved
into the buffer. The word following the last location in
the frame must be a zero since the 82592 in TCI mode
checks this location to see if it has a chain of frames to
transmit. A zero is interpreted as end of chain, a 04h is
interpreted as a new transmit command. This driver
does not implement transmit chaining.

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AP-327

The transmit DMA channel is now initialized and
transmit~ctiveJag is set to "I". The DMA address
registers and the page register are set to point to the
beginning of the transmit buffer. The channel mode is
set to move data from memory to the 82592. Four is
added to the transmit byte count that was calculated
earlier to allow the DMA controller to transfer the two
bytes of the byte count field and the transmit chain
word that completes a transmit in Tightly Coupled Interface mode. After this addition the transmit byte
count is shifted right one bit to convert it to a word
count. This value is then moved into the DMA controller's word count registers. Finally, the channel is unmasked.

4.4 DriverlSR
This routine services all interrupts generated by the "
ELM. It first calls IPXStartCriticalSection to tell the
Asynchronous Event Scheduler (AES) function of IPX
'that it should not execute until an IPXEndCriticalSection call is issued. This allows interrupts to be reenabled for sources other than IPX's AES which is executed in response to the system clock tick interrupt. DriverISR then saves the machine state by pushing the
general purpose registers, the index registers, the base
pointer and the ES and DS registers. Next the direction
and interrupt flags are cleared with a CLD and CLI
instruction, respectively. An EOI is then issued to each
of the two system interrupt controllers to clear them.
The DS and ES registers are then set to the same value
as the CS register because the driver is contained in a
single segment. The cause of the interrupt is now determined by reading register "0" in the 82592 .. A zero is
first written to the 82592 to set the internal pointer.
The value read from the 82592 is then compared with
the values representing a receive, transmit, and retransmit interrupt, then a jump is taken to the proper section
of the interrupt service routine. If the value does not
match one of the expected values, the variable false_
590_int is incremented 'and a jump to the label int_
exit is performed.

A Transmit command is now issued to the 82592. IPX
provides a time mark called IPXIntervalMarker that
represents the PC clock tick. The current value of this
variable is read and moved into tlL-start_time to be
used by the DriverPoll routine to check for transmit
timeouts. The TotalTxPacketCount variable is incremented and control is returned to IPX. The 82592 contains a programmable timer that could be used to generate transmit timeouts in an application that does not
have such a built-in mechanism. This routine,must return with interrupts disabled.

4.3 DriverPoll

4.4.1 RECEIVE CASE

DriverPoll is called at intervals by IPX to allow the
driver to check for transmit timeouts or other non-interrupt driven events, that need to be serviced. The first
thing done after disabling interrupts with a CLI is to
check if the transmit_active_flag variable is set. If it
is not set, a return is performed. If it is set, the tx_
start_time variable is subtracted from the current value of IPXIntervalMarker. If the result is less than the
value of TxTimeOutTicks, in this case 20, a return is
performed. If the transmit has timed out the transmission is aborted and a completion code of TransmitHardwareFailure is moved into the completion code
field of the ECB. The ECB is then unlinked from the
transmit queue and returned to IPX through a call to
IPXHoldEvent.
To accommodate errata No. three of the 82592 A-I
stepping, as stated in revision 1.2 (December, 1988) of
the 82592 Errata Sheet,. a Switch to PorU command is
issued to the device. This is followed by a Selective
Reset in Portl, followed by a switch back to PortO. The'
receiver is' then reenabled by a Receive enable command. The flag that indicated an active transmission is
then cleared. The transmit queue is then checked. If the
queue is not empty, the ES:SI register pair is set up
with the values from the queue, and start_send is
called. If the queue is empty control is returned to IPX.

If the value read from the 82592 indicates that a frame
has been received, a jump is made to the beginning of
the code that services receives. The first action is to
read the two latches that contain the address of the last
word that was transferred during the receive. This value is moved into the variables rlL-buf_tail and rx_
buf_ptr. This value is then compared with the value
stored in rlL-buf_stop by the set_up":""buffers routines to determine if most of the receive buffer has been
used and a reset is required. If most of the buffer has
been used the flag reset_rx_buf is set to indicate that
the buffer variables must be initialized before the interrupt service routine is exited. The value read from the
latches is then compared with the value in rlL-buf_
head. This value represents the last location that contains a received frame. If no frames have been received
it contains the address of the first location in the receive
buffer. If this comparison indicates that no new frame
has been received the ten_cent_IatcLcrash variable
is incremented and a jump is made to the label intexit.
If a frame, or frames, has been received the receive
buffer must be processed to allow the received frames
to be sent up to IPX in the order in which they were
received. This is accomplished by using the count and
status information that the 82592 deposits at the end of

1-316

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Ap·327

each frame when it is in TCI mode. Using the value
read from the latches as a base, the routine ProcessFrames indexes back through the chain of received
frames. The rx_buf_ptr variable keeps track of the
current position in the buffer. The status of the frame is
read from the end of the receive buffer and if it is good
a jump is done to the label good_rx. If the status is
bad, rlL.buf_ptr is adjusted to point to the end of the
previous frame in the buffer. This value is compared to
the value of rx_bufJead, which contains the location last processed by the receive routine or the beginning of the receive buffer if this is the first receive. If
the values are equal, all currently received frames have
been processed and a jump is made to the label hand_
off_packet. At the label good_rx three length checks
are made as required by the NetWare implementation
of Ethernet. First the frame is checked to see that is
does not exceed the maximum length of 1102 bytes
(1024 data size, 64 NetWare bytes, and 14 Ethernet
header bytes). Next it is checked to see that it is at least
the minimum size of 30 bytes. This 30 byte value is only
the IPX packet size, it does not count the Ethernet
header or the pad bytes required by Ethernet. The last
check ensures that the actual number of bytes received
agrees with both the Ethernet and IPX header length
fields. If the IPX length is less than the minimum
Ethernet frame length the total number of bytes received is expected to be 60. This represents Ethernet's
64 byte minimum frame length less the four CRC bytes,
which are not counted as receive bytes. If all these
checks pass, the frame is added to the list of received
frames by' storing its location, length, and source address in an array of structures called rx_list. Each entry consists of 12 bytes. These bytes are the location of
the frame in memory, the length of the frame, and the
address of the node that sent the packet.
When all received frames have been processed, all good
frames are passed up to IPXin the order they were received using calls to IPXReceivePacket. When all entries in rx_list have been. processed, the variable rlL.
bufJead is set to the value read from the latches at
the beginning of the interrupt service routine and stored
in rx_buf_tail. ProcessFrames then returns to the
point from which it was called and execution falls
through to int_exit.
4.4.2 TRANSMIT CASE

If the status read from the 82592 indicates that a transmit completion is the cause of the interrupt, a jump is '
performed to the label sent_packet.The first action is
to check that tx_active_flag is set. If it is not set no
transmit should have been taking place, so a jump is
made to the label int_exit., If tx_active_flag was set,
the status is read from the 82592. If the status is bad a
jump is made to tlL.error, which increments the appropriate counter and moves an error code to the AX
register before jumping to the FinishUpTransmit code.

If the status is good any retries contained in the status
register are added to the RetryTxCount variable, the
AX register is XOR'd to indicate a good transmission
and execution falls through to FinishUpTransmit. This
code inserts the proper completion code in the transmit
ECB, unlinks it from the transmit queue, and hands it
off to IPX by calling IPXHoldEvent. The transmit
queue is then checked to see is any frames are waiting.
If send~ist is not empty the next frame's ECB address
is put into the ES:SI register pair and a call is made to
start-send. On return execution jumps to int_exit.
4.4.3 EXITING THE INTERRUPT SERVICE
ROUTINE

At int_exit the driver makes a safety check to ensure
that the receiver is still enabled. This is done by checking the two bits in status register 3. If the receiver is
disabled, a Receive Enable is issued to the 82592. Next,
an Interrupt Acknowledge is issued to the 82592 and
the interrupt bit is polled to see if any new interrupts
have occurred. If a new interrupt has occurred, execution jumps back into the interrupt service routine at the
label int_poILloop. If no new interrupts have occurred, the reset_rlL.buf flag is checked to determine
if the receive buffer needs to be reinitialized. If reinitialization is required, a final check is made to see if any
new frames have been received. If a new frame has been
received ProcessFrames is called. On return the Receive DMA channel is masked and the receiver is disabled by issuing a Receive Disable command to the
82592. It is necessary to disable the receiver during the
reprogramming of the 8237 A because if there is an active request on a channel when it is unmasked the
8237A enters an undefined state which can result in a
system crash. The necessary variables are reinitialized
as well as the receive DMA controller. The receive
DMA channel is then unmasked and the receiver is
reenabled by issuing a Receive Enable command to the
82592. The interrupt enable flag in the processor is then
cleared through a CLI instruction and IPXEndCriticalSection is called to tell IPX that it is now free to run. A
call is made to IPXServiceEvents, and on return the
registers are popped to restore the machine state and
the interrupt service routine is exited.
This covers the main sections of code that make up this
driver. The routines that were not covered in detail are
generic in nature and can be understood by a reading of
the driver source code included as Appendix C.

Section 3. ELM Exerciser Program

5.0 OVERVIEW
The ELM Exerciser software is specifically written for
the Embedded LAN Module Demonstration board but
can accommodate other 82592 TCI (Tightly-Coupled-

1-317

AP-327

Interface) implementatiol)s, with minimal changes. The
~LM Exerciser software supports system and 82592
configuration, command execution and statistics display for the 82592 in the Embedded LAN hardware.

parameter. For the receive FIFO this determines the
number of bytes that may gather in the FIFO, before it requests the bus. The lower the FIFO limit,
the earlier the bus is requested and the 82592 will be
able to overcome a higher bus latency (the time it
takes from request asserted to actual bus transfers).
However, if the bus latency is short, fewer bytes will
be gathered in the FIFO and, before a request is
made. This increases the arbitration overhead per
transfer.
• The OSC RANGE and SMPLG RATE bits are set
to '0' as required in High Speed Mode. (Refer to the
82592 User Manual for more explanations on High
Speed Mode).

This section of the Application Note includes a description of the Exerciser, a discussion 0\1 design considerations for 82592 software drivers and some programming hints.

6.0 INITIALIZATION
System initialization begins with setting up all memory
structures. The 8259A PIC IRQlO is masked, to prevent unsolicited 82592 interrupts before initialization is
completed. Control is then transferred to the user. The
ELM hardware is enabled by a write to I/O Port 303h.
This is d'one using the "LAN En" coml)1and.To activate the 82592, the following sequence should' be executed. This sequence can be executed through the "Initialize" command or by executing each command separately. First the 82592 should be reset. This places the
device in the default configuration. The default bus
width is eight bits. Next a Configur~command is issued
to the 82592 with "0" in the byte count field. This
places the 82592 into 16 bit mode. The 82592 will now
use a 16-bit data bus for DMA transfers. For commands and status" only the low byte is used.

• The CHAINING bit is set to '0'. Together with
RxEOP set to '1' and TxEOP set to 'I', this causes
the 82592 to signal with the EOP# pin for all the
receive frames last byte (BC field)' and collided
transmit frames. The ELM logic uses EOP# with
DRQ lines to determine transmission status and to
latch the pointer to the byte count field into the
ELM latch.
• BUFFER LENGTH/TCI is set to "80h'. Together
with the chaining set to '0', RxEOP set to '1' and
TxEOP set to '1', this puts the 82592 in TCI mode.
In this mode the EOP # and DRQ pins signal the
completion and status of transmit and receive
events. This allows retransmission on collision by
auto initializing the DMA controller as well as reception of back to back frames without CPU intervention. When the device is not configured to TCI
mode, it requires CPU acknowledgement' after each
received frame. In TCI mode the status is stored in
memory, so the 82592 does not need immediate
CPU attention. If this parameter is programmed to
COh, the 82592 will not generate an interrupt upon
frame reception. The ELM Software packages use
this interrupt to invoke the RCV ISR. Note that
'Params3' fields are described in the manual using
decimal numbers. They should be translated into a
Hexadecimal base for programming, e.g. inter frame
spacing of 96 bits is programmed as '60h'.

The ELM Software Package uses the 82592 in a configuration different from the 82592 default configuration.
Whenever a parameter is used that varies from the default, an explanation is given. The 82592 configuration
is presented in code example one. The Configure command is issued through channel 0, which is used for
memory read I/O write cycles. ,
'ByteCnt' is a word-wide field containing the number of
parameter bytes in the CONFIGURE command (excluding the 'ByteCnt' field). The maximum length is 15
bytes. The 82592 will execute 9 DMA word wide transfers (1 for ByteCnt and 8 for parameters) but will ignore the last (the 16th) byte.
The following 'Paramsl' fields are different from the
default:
• The FIFO limit field is set to OFh.This configures
the FIFO's as two equal 32 byte banks for receive
and transmit. For, this configuration, this parameter
is internally multiplied by 2 to generate the actual
FIFO limit. This parameter configures the transmit
side, so transmit FIFO limit equals 2 • OFh = 30.
The receive FIFO limit is then 32 - 30 = 2. This
means that the 82592 will issue a bus request after
the first word has been written into it. Note that this
configuration is provides the maximum bus latency
(Refer to the 82592 User Manual for more detailed
explanation). The system bus request mechanism of
the transmit and receive FIFO's is tuned using this

The 'Params4' Max Retry' field is set by default to
'OFh'. In the case of a frame transmission attempt that
has experienced 15 retries, the NUIIL-Coll status is set
to '0', instead of 16. Namely, the first attempt and 15
retransmissions have collided so the Num_Coll should
be 16. Instead the 82592 will set this field to '0'. This is
further discussed in the transmit section.
The 'Params7' Monitor Interrupt field is set to '1'. This
prevents Monitor interrupts. This bit can remain in its
default state, since the Monitor Mode is, disabled.
The following 'Params8' fields are different from the
default:
'
,

1-318

• 'Params8' CLK divider is not used.

inter

AP-327

CODE EXAMPLE 1

CONF.CONF_Ptr->ByteCnt
CONF.CONF_Ptr->Params1
CONF.CONF_Ptr->Params2
CONF.CONF_Ptr->Params3
CONF. CONF _Pt r- > Params4
CONF. CONF_Ptr->Params5
CONF.CONF_Ptr->Params6
CONF. CONF _Pt r- > Params 7
CONF.CONF_Ptr->Params8

=
=
=
=
=
=
=
=
=

OxOOOF;
Ox804F;
OxOO26;
OxOO60;
OxOOF2 ;
Ox4000;
OxOOFF;
Ox873F;
OxFFFO;

/* 15 BYTES */
/* TCI, Tx FIFO LIMIT = 32 */
/* PREAMBLE LEN =7 */

9.6 uS INTERFRAME, 512 SLOT */

/~'

/* RETRY =15 NO PROMISCUOUS */

/* minimum frame 64 "~I
/* NO AUTO RE-XMT ON COLLISION */
/* NO MONITOR INT */
/~' RX & TX EOP, 32B RX & TX FIFO */

• RxEOP and TxEOP are set to '1' to enable the TCI
signaling as explained above.
• Status length is set to 6 bytes. Together with the
TCI mode configuration, this causes the Frame
Counter to be presented in the STATUS 2_0 register. The 7 LSBs of STATUS 2_0 count the number
of frames received after the Receive Enable command was issued. Both good and bad frames are
counted. The frame counter value is valid when the
MSB of Status 2_0 is set. Comparison of the ISR
frame counter with the number reported by the
frame count contained in Status 2_0 can aid in the
ISR software debug.

7.0 TRANSMIT
Transmission is very simple with the 82592. The data is
stored in memory. The DMA is initialized to point at
the first byte of the data. After the 82592 is given a
Transmit command (code 04h, when using channel
O),it will request DMA data transfers, acquire the link
as soon as the first byte is stored in the internal transmit FIFO and transmit the data. When transmission is
completed, the status field is updated and the INT pin
is asserted. However, if a collision occurs, retransmission is performed external to the 82592 by the ELM
logic. The ELM hardware uses the EOP# signal to
force the 8237 A DMA controller to point to the first
byte of the frame (DMA is in autoinitialize mode). The
82592 issues a data request to the DMA controller and
starts transmission again. This is done without CPU
intervention. The IEEE 802.3 time gap of9.6 uSec for a
retransmit attempt (for the first slot) is easily met. Retransmission is attempted until the internal 82592 maximum retry counter expires. In the ELM example, 15
retries will be attempted. Our laboratory experiments
indicate that most collisions are resolved within less
than 15 retries. In the case of errors the software driver
should intervene.
The 82592 is configured for TCI. This causes the 82592
to use its EOP# pin and thus, enables the external
ELM hardware to detect transmit collision events. The
ELM hardware uses both the EOP# and DRQ lines to
force the DMA to autoinitialize for the retransmissions.

The configuration used in the Exerciser software (TCI
mode) causes the 82592 to search for a command byte
after the last data byte. This byte should always be so
it will be interpreted by the 82592 as a NOP command.
If the least significant 3 bits in this byte are 100 binary,
the 82592 will interpret this byte as a Transmit command and treat the following bytes as the byte count
field of a new frame. The 82592 will then attempt to
transmit it. XMT chaining is not used in the Exerciser
software. The ELM retransmission mechanism uses the
8237A DMA autoinitialize capability. If a chain of
frames is stored in the transmit buffer, there will be no
way to handle automatic retransmission for all the
frames but the first one. There is no way to cause the
8237A DMA controller to jump to the first byte of the
n-th frame, required for a retransmission when chaining is used. However, transmit chaining is possible
when using the 82560/82561 DMA controller.

°

In case of a fatal transmission error, the 82592 will
signal the event to the CPU through the interrupt and
status mechanism. The CPU will issue another Transmit command with the same data (or issue a higher
layer activity when not in the ELM Exerciser software
environment). The CPU will control the number of
times it retransmits the same frame. In case this number exceeds the ELM MAX_RETRY (default = 15.
This is a SW variable, not the 82592 internal max retry
counter) transmission is stopped and the following message is printed on the screen: "ERROR no. 1 ". The
ELM Exerciser software 'MAX_RETRY' default value is 16.
Transmission of an exact number of frames in the range
of 1-32000 or an endless number of frames is
supported. The background transmit command, found
in the EXECUTE menu, communicates with the transmit interrupt service routine (ISR) The XMT_LOOP
flag variable is reset by the background routine immediately before transmission and set by the transmit ISR.
This handshake allows transmission of 1 frame at a
time. The background transmit command polls the
XMT_LOOP flag until it is found to be set. The display is updated periodically. To stop the transmission
loop hit any key on the keyboard.

1-319

AP-327

an endless number of frames, while transmission is performed in parallel and its status stored in this special
internal queue. This optional pending event will be presented in the STATUS register after each CPU interrupt acknowledge sequence. The 82592 will use one receive event to report all the frames received from the
first INT assertion until its acknowledgement. The
82592 will not wait for the CPU to acknowledge the
interrupt; nor will the 82592 generate new interrupts by
toggling its INT pin. New 82592 interrupts for all
events will be generated after the CPU agknowledges
the previous INT request.The CPU can do so by issuing a command to the 82592 with the ACK bit (bit 7),
in the 82592 command byte, ~et.

8.0 INTERRUPT SERVICE ROUTINE
When an execution command has been completed, or a
frame has been received, the 82592 will assert its INT
pin. This is true if the BUFFER LENGTH/TCI parameter of the Configure command was 80h. If programmed to COh, the 82592 will not generate an interrupt upon frame reception. The ELM Exerciser software uses this interrupt to invoke the receive ISR). The
82592 INT pin drives IRQlO of the system bus. IRQlO
is connected to the slave PIC on the motherboard. The
slave PIC output drives one of the master PIC inputs.
If the 82592 INT pin is asserted, the slave .PIC generates (if not masked) an Int signal to the Master PIC
. which transfers (if not masked) the signal to the CPU.
Both PICs have experienced an INT event. This requires that an EOI be issued to both PICs before exiting the ISR.
The 82592 will present the event that caused interrupt
generation in its status register number 0, along with bit
7 set to indicate an unacknowledged interrupt event.
The content of the status registers will not be altered
until the CPU acknowledges the interrupt. When configured to TCI mode, the 82592 will store one more
event in an internal queue. This allows the reception of

At program initiillization, the assembly language procedure "ini_int" is executed. It saves the local environment pointers (private stack and segment registers) and
replaces the current 72h INT Vector in the interrupt
table, with a pointer to the int_hnd routine. The int_
hnd routine is the routine invoked upon any 82592 interrupt. The original 72h interrupt vector, is saved in a
place known to be empty in the DOS interrupt vector
table (62h). The ELM Exerciser software will restore
the original vector before exiting to DOS at the end of
the execution.

CODE EXAMPLE 2

;************************************************************
INI~INT : SET CONDITIONS TO WORK WITH 8259A COMMUNICATION INT
IRQIO IS CONNECTED TO 82592 INT PIN
INT VEC 72h IS JUMP TARGET FOR IRQIOMASKING IRQIO IS DONE
,
AT THE CALLING LEVEL
;************************************************************

push bp
mov bp,sp
jlush es
push bx
.
mov bx, _mstck2
mov cs:lss, bx
mov bx, _mstckl
mov cs:lsp, bx
mov cs:lds, ds
mov cs:les, es
mov al,vec
call sys35
mov al,62h
call sys25
mov al,vec
. mov bx, offset int_hnd
push cs
pop es
call sys25
pop bx
pop es
mov sp,bp
pop bp
ret
_inLint endp

;save local stack segment
;save local stack pointer
;save local data segment
;save local extra 'segment
;hex communication interrupt no.
;es:bx ,hold returned address
;save for later retrieve in vec 62
;hex int no. of irqlO (LAN)
;address of interrupt handler routine
;es-segment of interrupt handler
;install via DOS system call

1-320

intJ

AP-327

The assembly language procedure "int.hnd" is invoked
when the 82592 interrupts the CPU using IRQI0. First
it checks whether this is the first entry of "int.hnd" or
if the interrupt service routine has been reentered while
the previous interrupt was still being processed. The
section on the interrupt service routine discusses interrupt nesting. In the ELM Exerciser Software, 82592
interrupt nesting is prevented. Therefore, the above test
should always return a "no nesting" answer. Then the
host process environment is stored in memory and the
local environment is restored (see the section "Interfacing with DOS"). Next, the machine state is saved by
pushing the general purpose . registers (AX, BX, cx

and OX) and the index registers (SI and 01). The execution until now is considered critical, in the sense that
it should not be interrupted. The processor hardware
prevents any new interrupts of the same level or lower
in priority from interrupting the execution.
The routine "irqlO_mask" masks interrupt request 10
of the 8259A PIC. This is the interrupt generated by
the 82592. This prevents the 82592 from causing nested
interrupts. Now an STI instruction can be issued. This
will enable processing of other interrupts by the processor in a timely fashion. An optional approach is discussed later in the section on interrupt nesting.

CODE EXAMPLE 3

.************************************************************
,

INT_HND: INTERRUPT HANDLER FOR IRQIO (VEC 72)
DEALS WITH THE LOWER LEVEL OF THE TREATMENT, AND CALLS
THE CHANDLER
;************************************************************

inc cs:counter
cmp cs:counter, I
jne inter
first_entl:
mov cs:hsp,sp
mov cs:hss,ss
mov cs:hes,es
mov cs:hds,ds
mov sp,cs:lsp
mov sS,cs:lss
mov dS,cs:lds
mov eS,cs:les
inter:
push bp
mov bp,sp
push ax
push bx
push cx
push dx
push si
push di
call _irqiO_mask
sti
push ax
mov aX,20h
out OAOh,al
mov aX,20h
out 20h,al
pop ax

;saves sS,sp,ds,es only for the first entry

;save registers of host process in memory

;pop local registers from memory

;end of interrupt to 8259A Slave
;end of interrupt to 8259A Master

11:

1-321

inter

AP-327

CODE EXAMPLE 3 (Continued)

exit:
call _parazit_rcv
cli
:enter a critical section must disable int only
:if eoi is before this section
call _irqlO_unmask
,pop di
pop si
pop dx
pop cx
pop bx
pop ax
mov sp,bp
pop bp
dec cs:counter
;nesting check
cmp cs:counter,O
jnz inexit
last:
mov sp,cs:hsp
:pop host registers from memory
mov sS,cs:hss
mov ds,cs:hds
mov es,cs:hes
inexit:
sti
ext_int:
iret
inLhnd endp
Before program control is transferred to the "c" routine "c~ntO" the two 8259A PICs are acknowledged.
The "c_intO" routine reads the 82592 status from the
6 byte status register. To make sure Status byte is the
first byte read and that the following bytes are read in
order, a RLS_PTR (OFh) command, with as a pointer value (points to Status_O), is issued. If no command
is issued to the 592 during the Status read sequence,
each successive read to the 82592 will increment the
internal status pointer and guarantee properly ordered

°

°

status bytes. Now the 82592 Interrupt can be acknowledged. This allows the next event to be presented in the
status register, and the INT pin to be asserted. Since
the PIC is masked all further interrupts from the 82592
will be ignored until the ISR has been exited. The
'INTJROC_Stat' variable holds the interrupt event
presented in STATUS_O. For receive and transmit
events, a lengthy processing is required. It is described
below.

1-322

inter

Ap·327

CODE EXAMPLE 4

far c_int()
(

register a; /* for a faster detection of the INT event */
write_592(OxOF) ;
get_592_status () ;
outp(ADDR_592,Ox80) ;
a = STAT_REG_Stat[O] ;
if (a &: Ox80)

/*
/*
/*
/*
/*

RLS_PTR to 0 command */
IN operation from the 82592 */
acknowledge to 82592 */
Status byte 0 holds the event */
INT bit active */

(

a &:= OxOF;
switch (a)

/* clear irelevant bits */

(

case 8:
INT_PROC_Stat = "RCV-; /* last INT event for screen display */
inLrcv() ;
/* call the RCV ISR */
break;
case 4:
INT_PROC_Stat = "XMTn;
int_xmt() ; /* TRANSMIT event */
break;
case 12:
INT_PROC_Stat = "ReX"; /* Re-TRANSMIT event */
inLxmt() ;
break;
case l:
INT_STAT_RDY = TRUE; /* Individual Address */
INT_PROC_Stat = lilA "; /* executed */
break:
case 2:
INT_STAT_RDY = TRUE: /* Configure executed */
INT_PROC_Stat = "CNF":
break:
case 5:
INT_STAT_RDY'= TRUE: /* TDR executed */
INT_PROC_Stat = "TDR";
break:
case 6:
INT_STAT_RDY = TRUE; /* Dump Executed */
INT_PROC_Stat = nDMpn:
break;

1-323

inter

AP-327

CODE EXAMPLE 4 (Continued)

case 7:
INT_RDY
TRUE; /* Diagnose Passed */
INT_PROC_Stat
nDgP";
break:

=

case 10:
INT_STAT_RDY
INT_PROC_Stat
break;

=

=TRUE; /*
= nRxD";

RCV Aborted */

case 13:
INT_STAT_RDY
INT_PROC_Stat
break;

= TRUE;

/* Execution aborted */

= nExA";

case 15:
INT_STAT_RDY
INT_PROC_Stat
break;

=TRUE;n /*
=DgF ;

default:
INT_STAT_RDY
INT_PROC_Stat
break;

= TRUE;

=• ?

Diagnose Failed */

n:

/* end switch */
I /* end i f */
/* exit interrupt handler */
Before leaving the "intJnd" interrupt service routine,
the 82592 interrupt is unmasked in the 8259A PIC. The
machine state is then restored by popping the registers
pushed on the stack at the entry of the interrupt handier. The nesting control 'counter' variable is decremented and finally the host process environment is restored.
8.1 RCV Interrupt Service Routine: "lnLrcv( )"

The RCV interrupt service routine handles the reception of one or more frames. All the frames received are·
stored in memory in successive addresses by the 8237A
DMA controller. After the 82592 has completed reCeiving a frame it interrupts the CPU. The 82592 will continue to receive frames as long as the DMA continues
to service its requests to store data in memory.

The "int~cv( )" routine implements a cyclic RCV
buffer handling. The buffer size is configurable. The
ELM Exerciser software uses 16 KB, a smaller size can
be used if interrupt latency is small enough. The maximum receive buffer size for this architecture is limited
to 120 kB due to the physical page register implementation of the PC-AT DMA subsystem. In the ELM it is
further limited to 64 kB due to the fact that AO through
A 15 are latched in the TCI latches. If A 1 through A 16
are latched then the full 128 kB that the DMA can
access could be ·used as a receive buffer. To allow maximum buffer size, the ELM Exerciser software locates
its r~eive buffer at the beginning of a physical address
segment, i.e. address of type xxOOOOh, (which of
course is not a must). This allows a simplification in
address calculation because the lowest 16 bits can be
directly used for address calculations: There is no need
to add a displacement from the beginning of the physical address segment.

1-324

inter

Ap·327

The receive ISR starts with the frame received last
(pointed by the latch) and processes received frames,
backwards. The last received frame byte count field is
used to find the byte count field of the next to last
frame. After the pointer to the beginning of the frame
has been reproduced, the received frames can be processed. This goes on until the first frame has been
found. The frames can then be processed in the order in
which they were received.

As seen in figure 5, the 82592 appends the frame's
status and byte count fields, after the last data byte. In
the case of odd frame length (data field in bytes), the
592 will leave one byte empty so the status and byte
count are stored on a word boundary when the 82592 is
set to 16 bit mode.

Throughout the RCV ISR session, the length of the
current frame is being subtracted from the "Cur-Latchabs" variable (pointer to the current frame Byte Count
field), to obtain the previous frame's byte count field.
When the 'Cur-Latch-abs' variable points to the byte
preceding the first byte received in this session of the
ISR, the receive ISR has completed processing all the
frames received in this session.

READING THE LATCH

8.2 Execution Algorithm

The first action taken in the receive ISR is to read the
16-bit latch. It holds the low 16 bit physical address of
the byte count field of frame number N, the last completely received frame (latcLcontent = 470h in the
example of figure I). Note that more than I frame can

D15

DO

~

previous RD_POINTER_abs

DA2

DAI

Rev Start

r"
r"

Frame #1

XXXX
DA2

BC High
DAI

192h

Frame #2

~

XXXX

BC High

-----------

-----------

DA2

DAI

IEBh

r

Frame #N-l

XXXX
DA2

BC High
DAI

)"'"

Latch
D15

F~ame #N

DO

~

30Eh

IJ

Latch_content
Cur_Iatch_c~ntent J
F_Iatch_abs J
Old_latch_content J

xxx x

BC High

470h

Rev End

Figure 5. Memory Organization of RCV Frames

1-325

292062-1

inter

AP-327

be handled by "int_rcvO" in one session. It is not necessarily the very same frame, designated 1, that its reception completion has generated the INT signaUn
this program, the latch is read twice. The latch is read
in two 8 bit accesses since 16-bit I/O is not supported
, so the latch content can be altered in between. As the
DMA can work in parallel with INT processing, it can
capture the bus during the receive ISR latch read operation. If a frame was completed exactly at this time, a
new byte count field pointer. is loaded into the latch.
The second receive ISR read operation will then get
half of the new BC field pointer). If the read operations
yield the same result, the data is valid. In case of mismatch, the read operations are repeated. Latch read
action is very short compared with frame reception, so
there will be no need for more than two iterations. This
can alsobe accomplished by doing a word read at the
low byte of the two latches. Since the ELM does not
return MEMCSI6 the processor will execute two back
. to back byte reads at consecutive I/O locations. These
two reads are locked thus pointer integrity is guaranteed.
FALSE ALARM

A "false alarm" is detected by the fact that the latch
content is equal to its value in the previous service sequence. If the latch was not updated no frame was received since the last receive ISR invocation. If exactly
the butTer size bytes were stored in memory from the
last time a receive was serviced, this test may indicate
wrong results. However, the butTer size should be big
enough to accommodate the longest CPU latency in
servicing interrupts.

BYTE COUNT AND STATUS

The frame length is read from the byte count field (two
words). The general status maintained by the ELM Exerciser software is updated from the status field attached to the end of the frame before the byte count
field. Then the frame q:tay be copied to the user's application receive area. By now one frame has. been received and processed (FRTT_CNT = I).Note that
the byte count field includes the number of the destination address field bytes, source address field bytes, information field (type field included) and two status
bytes. The'Byte Count field itself (four bytes) plus two
bytes of the status field are not included in the calculation. In 16-bit mode, the 82592 extends the status and
byte count fields to words instead of bytes This is treated in more detail in the 82592 User Manual. The previous frame's byte count field has now been located (byte
count + 6) bytes.previous to the current one. See figure
5.
DATA CHECK.

This utility allows checking the received data. The basic assumption is, of course, that the data is known in
advance so we have a reference to compare with. In the
ELM case, the data transmitted is sequential (word
wide), in case the user did not change the default transmission data blocks. This is illustrated in the following
code example.

CODE EXAMPLE 5

/***********************************************

*
*
*
*
*
*

checkS the data words to be sequential data
0,1,2, if data length is longer than 4. *
length
4·data
0000 0000 *
length
5 data
0000 0001 00 *
length
6 data
0000 0001 0000 *
length
7 data
0000 0001 0002 00 *

=
=
=

=

*

=
=
=
=

***********************************************/
/* RD_POINTER_seg.Ptr is pointing to the first byte of the frame
Cur_Latch_abs is pointing to the byte count of the previous frame
Prev_latch_abs is pointing to the byte count of the current frame
*/

1-326

inter

AP-327

CODE EXAMPLE 5 (Continued)

find_boundary (f_byte)
unsigned int f_byte; /* offset of first byte in frame */
(

/* Don't compare last 5 words, 2* BC, 2* STATUS + last word is zero */
if_byte < Prev_Iatch_abs)
return«Prev_1atch_abs - f_byte - 10)/2);
else if(f_byte > Prev_Iatch_abs)
{

H(

(Prev_Iatch_abs - Sixteen_I) > 10)
(

wrap_required = TRUE;
return«RD_END_abs - f_byte)/2);
else

I

return«(RD_END_abs - f_byte)/2) - (10 - (Prev_Iatch_abs Sixteen_I) ) ) ;

I
else

I

RX_CHECK = TRUE; RX_CHECK_DT = Oxa5a5; RX_CHECK_BNUM = Oxa5a5;

I
wrap()
(

wrap_around = TRUE;
bound_dist == find_boundary(Sixteen_1) ;
local.temp.xoffset = Sixteen_I;

I
check_data (f_byte)
unsigned int f_byte; 1* offset of first byte in frame */
(

int i ,j ;
int far * tmp;
unsigned int tmpl, delta, dt1en;
/* reset flags */
wrap_around = wrap_required = FALSE;
/* first find buffer boundary cross point from first DA word if any */
bound_dist = find_boundary(f_byte) ;
/* second find DA and compare to IA */
loca1.tmp = mk_pointer(Prev_latch_abs, -(Cur_Byte_Count + 4»;
if (*(local.tmp++)

!=IASU.IASU_Ptr -- laAdd1)

{

RX_CHECK = TRUE; RX_CHECK_DT =
return;

* (local.tmp)

I
if (bound_dist- __ 0)
wrap() ;

1-327

; RX_CHECK_BNUM = Oxaa1;

intJ

AP-327

CODE EXAMPLE 5 (Continued)

if (*(local.tmp++) 1= IASU.IASU_Ptr -> laAdd2)
{

RX_CHECK = TRUE; RX_CHECK_DT = * (local.tmp) ;,RX_CHECK_BNUM = Oxaa2;
return;

l
if (bound_dist- __ 0)
wrap() ;
i f (*(local.tmp++) I=IASU.IASU_Ptr -> IaAdd3)
{

RX_CHECK
return;

= TRUE; RX_CHECK_DT

= * (local.tmp) ; RX_CHECK_BNUM = Oxaa3;

l
/* second, disregard SA */
if (bound_distwrap() ;
local.tmp ==;
i f (bound_di stwrap() ;
local.tmp ++;
if (bound-distwrap() ;
local.t)llp ==;

--

0)

-- 0)
-- 0)

/* third'check if frame includes data 1= 0 using LEN field */

==

if (bound_dist0)
wrap() ;
if ((dtlen = *(local.tmp++»

== 0)

{

RX_CHECK = TRUE; RX_CHECK_DT = * (local.tmp) ; RX_CHECK_BNUM = Oxaa6;
return;

l
/* if frame includes data 1= 0 compare all bytes till boundary cross */
i

= 0;

if (bound_dist > 0)
[

for (i=O; i SRT_FRM +=' 1;
if (*(tmp_ptr) Be Ox0040)
SCB. SCB_Ptr -> NO_EOF += 1;
if (*(tmp_ptr) Be Ox0020)
SCB.SCB_Ptr -> TOO_LNG += 1;
if (*(tmp_ptr) Be Ox0008)
SCB.SCB_Ptr -> NO_SFD += 1;
if (*(tmp_ptr) Be/Ox0004)
SCB.SCB_Ptr -> NAD_MCH += 1;
if (*(tmp_ptr) Be Ox0002)
SCB. SCB_Ptr -> lA_MCH += 1;
if (*(tmp_ptr) Be Ox0001)
SCB.SCB_Ptr -> RCV_CLD += 1;
tmp_ptr = mk_pointer(Cur_Latch_abs, -4);
if(*(tmp_ptr) Be Ox0020)
{

SCB.SCB_Ptr -> RCV_OK += 1;
UPDATE_RXCNT
TRUE;
}

=

1-330

inter

Ap·327

CODE EXAMPLE 6 (Continued)

if(*(tmp_ptr) & Ox001D)
(

rut-ERR = TRUE;
if (*(tmp_ptr) & Ox0010)
SCB.SCB_Ptr -> LEN_ERR += 1;
if (*(tmp_ptr) &'Ox0008)
SCB.SCB_Ptr -> CRCErrs += 1;
if (*(tmp_ptr) & Ox0004)
SCB.SCB_Ptr -> A1inErrs += 1;
if (*(tmp_ptr) & Ox0001)
SCB.SCB_Ptr -> OvernErrs+= 1;
FRTT_CNT = 1;
/* Frames Received This Time count.Compi1e with DEB_PRT
switch, to monitor number of frames received each int_rcv invocation */
Prev_1atch_abs = Cur_Latch_abs; /* for Data Check */
RD_POINTER_seg.Ptr = mk_pointer(Cur_Latch_abs, -(Cur_Byte_Count + 6));
Cur_Latch_abs = RD_POINTER_seg.Addr.xoffset; /* previous frame BC pointer
308h */
RD_POINTER_seg.Ptr = mk_pointer(Cur_Latch_abs, 2) ; /* frame N 1st byte 310h
*/
tmp = RD_POINTER_seg.Addr.xoffset;
/******* Data Check ********
RD_POINTER_seg.Ptr points to the' first byte of the frame
Cur_Latch_abs points to the byte count of the previous frame */
if (CheckEnab1e == ON)
check_data(tmp) ;
while ((k = more_to_read(tmp)) != 0)

/* MAIN LOOP */

(

cbc_h = * (mk_pointer(Cur_Latch_abs,O));
Cur_Byte_Count = * (mk_pointer(Cur_Latch_abs, -2));
Cur_Byte_Count = (cbc_h ~ 8) + (Cur_Byte_Count & OxOOFF) ;
if ((Cur_Byte_Count % 2) == 1)
Cur_Byte_Count++;
tmp_ptr = mk_pointer(Cur_Latch_abs, -6);
if (*(tmp_ptr) & OxOOEF)
(

rut-ERR = TRUE;
if(*(tmp_ptr) & Ox0080)
SCB.SCB_Ptr -> SRT_FRM += 1;
if(*(tmp_ptr) & Ox0040)
SCB.SCB_Ptr -> NO_EOF += 1;
if(*(tmp_ptr) & Ox0020)
SCB.SCB_Ptr -> TOO_LNG += 1;
1f(*(tmp_ptr.) & Ox0008)
SCB. SCB_Ptr -> NO_SFD += 1;
if(*(tmp_ptr) & Ox0004)
SCB.SCB_Ptr -> NAD_MCH += 1;
if(*(tmp_ptr) & Ox0002)
SCB.SCB_Ptr -> IA_MCH += 1;
if(*(tmp_ptr) & Ox0001)
SCB.SCB_Ptr -> RCV_CLD += 1;

I '

tmp_ptr = mk_pointer(Cur_Latch_abs, -4);

1-331

intJ

AP-327

CODE EXAMPLE 6 (Continued)

if(*(tmp_ptr) & ox0020)
(

SCB.SCB_Ptr -> RCV_OK += 1;
UPDATE_RXCNT = TRUE;

I

if(*(tmp_ptr) & Ox001D)
(

RX_ERR = TRUE;
if (*(tmp_ptr) & Ox0010)
SCB.SCB_Ptr -> LEN_ERR += 1;
if(*(tmp_ptr) & OxOOOB)
SCB.SCB_Ptr -> CRCErrs += 1;
if (*(tmp_ptr) & Ox0004)
SCB.SCB_Ptr -> AlinErrs += 1;
if (*(tmp_ptr) & Ox0001)
SCB.SCB_Ptr -> OvernErrs+= 1;

I
Prev_latch_abs = Cur_Latch_abs;:
/* for Data Check */
RD_POINTER_seg.Ptr = mk_pointer(Cur_Latch_abs, -(Cur_Byte_Count + 6));
Cur_Latch_abs = RD_POINTER_seg.Addr.xoffset;
RD_POINTER_seg.Ptr =.mk_pointer(Cur_Latch_abs, 2);
tmp= RD_POINTER_seg.Addr.xoffset;
/******* Data Check ********
RD_POINTER_seg.Ptr points to the first byte of the frame
Cur_Latch_abs points to the byte count of the previous frame*/
if(CheckEnable == ON)
check_data(tmp) ;
FRTT_CNT++ ;
if (FRTT_CNT >1250)
break;
. /* GUARD BAND * /
I ; /* MAIN LOOP END */
RD_POINTER_seg.Ptr = mk_pointer(F_Latch_abs, 2) ;
RD_POINTER_abs = RD_POINTER_seg.Addr.xoffset; /* next int_rcv session 1st
byte 472h */
RxCount += FRTT_CNT;
copy_data() ;
/* from RCV buffer to user's application *1
INT_STAT_RDY = TRUE;
/* for screen status update */
return;
/* end of int_rcv() */

I
address calculation

In code example 3, the routine "mLpointer(address,
delta)" is used. This routine handles a 16-bit physical
address to pointer conversion (see Code Example 7)
and the buffer internal address calculation (which are
not straightforward).
As noted before, the RCV buffer is a cyclic buffer.
When calculating an address starting from one address
and adding/subtracting some 'delta' value, the buffer
boundaries can be crossed. Overlapping the buffer .

boundaries is further illustrated in Figure number 6.
When subtracting the byte Count of frame N, which
starts in (1) and ends in (2), a direct decrement will not
give the right results. If we calculate backwards and fall
out of the receive area, (address region within which
the buffer for all frames resides) ~'mk-pointerO" adds
the length of the receive area to get the right address. If
we go in the other direction, "mk_pointer" subtracts
the receive area length. Due to receive area alignment
into a physical address segment, the case in which the
address we get is lower than RCV~REA--START
is impossible.

1-332

intJ

AP-327

CODE EXAMPLE 7

/***************************************

*
*

mk_pointer transforms a 16 bit *
abs to a pointer within the RCV_AREA

*

***************************************/
int far *
mk_pointer(abs,delta)
unsigned int abs;
int delta;
(

unsigned int The_length;

=

The_length
(unsigned) DECRCVBLEN; /* buffer length */
RD_POINTER_seg.Addr.xoffset
abs + delta;
if(RD_POINTER_seg.Addr.xoffset > RD_END_abs)

=

{

/* check if going backwards */

(delta <0)
RD_POINTER_seg.Addr.xoffset += The_length;
/* check if going forward */
i f (delta> 0)
RD_POINTER_seg.Addr.xoffset
The_length;

if

-=

1

/* if result is before RCV buffer starts in the segment. */

/* impossible result for aligned RCV_AREA */
return(RD_POINTER_seg.Ptr) ;

Rev Start

c

A

A

c

B

A
Rev End

n
The frames begin at RD_POINTER and end at F_LATCH.

Figure 6. Overlapped Buffer Boundary

1-333

292062-2

intJ

Ap·327

Another address calculation is performed to determine
whether there is "more_to_readO" (see code example
8) i.e., whether.all the frames received this time were
processed and whether the next frame to be read is
valid. Cases of invalidity ate detected by this routine.
This error is denoted "SW_OVERRUN", for software
overrun errors. In case the interrupt handling was too
slow, the DMA could have over written received
frames which were not processed yet. In this case, a
valid byte count field can be replaced by arbitrary data.
This will mislead the backwards address calculation. It
may also cause a detectable address error, where the
previous frame byte count field is located in an area
known to be outside the last valid receive area. The
following variables are used in this calculation:

detect a frame that is wrapped-around the end of the
receive buffer.
RD-POINTER-abs, labeled OLD LATCH in figure 7,
always points to the first byte of the next frame to be
processed in the next "int~cvO" invocation. It is updated at the end of each service cycle; to hold F-latchabs + 2. (Note: 'RD-POINTER-abs' is not equivalent
to 'RD-POINTER-seg.Ptr' ,which serves as a template
for various pointer calculations.)
The following scenarios are possible for such intermediate results.
Legal intermediate results should fall in the "A" area if
the results are in "A", namely between RD-POINTER
(start of this session RCV-AREA) and F-LATCH
(First Latch, end of this session RCV-AREA). Note
that F-LATCH may be greater or smaller than RDPOINTER. See Figure 7A.

Cur-Latch-abs, labeled CUR LATCH in figure 7, is
used to hold the address of the current frame's byte
count in memory, while the ISR processes them. At the
beginning, it holds the last frame's byte coupt (frame
n), then it will hold frame n-I's byte count address and
soon.

If however, the result falls in "B" or "C" areas it is not
legal. This may happen if the buffer was too small and
the 82592 had overrun it in reception. This would occur
if the whole buffer was filled and then more frames
were received, before being processed by the ISR. See
figure 7B.
.

F-latch-abs, labeled NEW LATCH in figure 7, holds
the address of the byte count of the last received frame
(frame N) in this "int~cvO" invocation. It is used to

Rev Start
A

c

c

A
Rev End,

n

][

~ Data received In this session
292062-3

Figure 7a_ Legal "CUR_LATCH" Values

1-334

AP-327

Rev start

C

B

A

Rev End

m

1I

292062-4

Figure 7b. More Frames TO READ

Before Corruption

After Corruption

Frame 1
Frame 2

Frame 2

Frame 3

Frame 3

Frame 4

Frame 4

Frame 5
Start

Frame 5
Start
292062-5

Figure 8. Receive Buffer Corrupted by Overrun

Frame # 5 erases the byte count infonnation stored by
frame # 1. When we calculate our way backwards we
will not find the byte count field of frame # I and read
instead a data word of frame # 5. This data may be
interpreted wrong and cause an avalanche in the frame
reconstruction process. This event can be detected by
the above test.

POINTER (the beginning of the current ReV-AREA)
and prevent write access to areas previously written by
592/DMA and not serviced yet. In case the maximum
delay of the system is detennined and known, one can
allocate a big enough buffer to accommodate that delay
in the ISR. eRe should be stored in memory and
checked by the S/W to assure data integrity.

This can be completely avoided if a stop register is implemented in hardware. This register would hold RD-

1-335

inter

AP-327

CODE EXAMPLE 8

/************************************

* checks whether more frames to *

*

be read as indicated by the latch

*

************************************/
more_to_read{tmp)
unsigned int tmp;
(

unsigned int cur_content, f_content, rd_content;

=
=

cur_content
tmp; /* Cur_Latch_abs [flow chart: cur latch] */
f_content
F_Latch_abs; /* [flow chart: new latch] */
rd_content
RD_POINTER_abs; /* [flow chart: old latch] */
if (f _content > rd_content)

=

(

if{ (cur_content> rd_content) &:&: (cur_content <= f_content))
return{l) ;
if ({cur_content < rd_content)
(cur_content> f_content))
,
(

. SW_OVR++;
RX_ERR
TRUE;

I

=

return{O) ;

I
i f (f_content
(

< rd_content)

if ({cur_content> rd_content)
(cur_content <= f_content))
return{l) ;
if ({cur_content < rd_content) &:&: (cur_content> f_content))
(

SW_OVR++ ;
RX_ERR
TRUE;

I

=

return{O) ;

1-336

inter

AP-327

CODE EXAMPLE 9

far parasite_rcv()
{

int i;
unsigned int

j;

i f ((i=latch_read ())
(

!= 0)

LATCH_ERROR++ ;

return;

I

if((RxCount != 0) && (latch_content != Old_latch_content))
(
PARASITE++ ;

int-rcv() ;

I

Frames may be received during execution of the receive
ISR. These frames are handled before the receive ISR is
exited. This saves the interrupt latency involved and the
context switching overhead. Therefore, it will increase
the overall performance of the code. For all interrupt
events, the "parasite_rcv" routine is invoked, before
exiting the "intJnd" routine (see code examples 9
and 3). The routine "parasite_rcv" checks whether a
frame has been received using the address latch for indication. It compares the current 'latcLcontent' with
the latest value known to this ISR invocation (stored in
'Old-Iatch-content'). Obviously, a different value will
indicate that a new frame has been received from the
time this ISR has been invoked until it is about to be
exited.
In the case of an odd frame length (data field in bytes),
the 592 will leave one byte empty so the status and byte
count are stored on a word boundary (when the 82592
is set to 16 bit mode).
8.3 Transmit Interrupt Service Routine: "inL
xmt{ )"

The transmit ISR is simpler than the receive ISR. It
mainly deals with status update and software generated
retransmissions. First, collision status is checked.
Num_ColI is the number of times this frame has experienced a collision during a transmission attempt.
Num_ColI is equal to, or greater than 0, and smaller
or equal to the configuration parameter Max Retry.
FRM_COLL is an indication generated by the ELM
Exerciser software based on the status reported by the
82592. All the other status reports reflect the 82592
status report, with no further processing. FR~
COLL ,contains the number offrames that have experi-

enced at least one collision. COLL indicates that the
last transmission attempt has experienced a collision;
but, transmission was stopped due to other fatal
events). MAX_COLL indicates that the 82592 has attempted to transmit this frame "Max Retry" times plus
1. All these attempts have experienced collisions.
The events of transmit deference, heartbeat and frame
too long are merely registered and transmission is considered successful. A frame too long error may indicate
a hardware error that caused the 82592 to load an incorrect value into its byte count counter; e.g., 700h was
loaded into the 82592 byte count counter. However,
700h is greater than the maximum allowed length of an
Ethernet frame. This could have happened because of a
hardware or software malfunction.
The events of underrun, lost CRS, lost CTS, late collision or Max-Coll indicate a fatal error with which the
82592 cannot cope. The decision taken here is to retransmit in these cases. However, this decision can be
left for a higher software layer, where such a layer exists.A status report mismatch is fixed for the MA~
COLL status. There is a special case when the 82592 is
configured for 15 retries. After 15 retries it increments
the internal counter to hold (15 + I)MODI6 and hence
NUIIL-Coll holds zero. In this case 16 is added to
Num_CoII. A frame transmission that has been completed successfully still may have suffered from collisions. Hence, this field should be checked even in TX_
OK cases.
Next, the statistics update flag is set ('INTJTAT_
RDY').
The last section of this code handles the counter load
for XMT LOOP cases.

1-337

inter

AP-327

CODE EXAMPLE 10

'****************************
* XMT interrupt service *
'****************************

TxCount++;

,. update XMT frame counter "
,. for all events, do
SCB.SCB_Ptr->Num_COLL += (STATUS.STATUS_Ptr-> Status_l_O & OxOOOF) ;
if( (STATUS.STATUS_Ptr -> Status_LO & OxOOOF)
(STATUS.STATUS_Ptr -> Status_l_O & Ox0020) )
SCB. SCB_Ptr->FRM_COLL++;
if(STATUS.STATUS_Ptr -> Status_Ll & OxOOBO)
SCB.SCB_Ptr->COLL += 1;
status report, only',
if(STATUS.STATUS_Ptr-> Status_l_O & OxOODO)

0,

'0
[

if(STATUS.STATUS_Ptr->Status_l_O
SCB.SCB_Ptr->TX_DEF += 1;
if(STATUS.STATUS_Ptr->Status_l_O
. SCB. SCB_Ptr->HRT_BEAT += 1;
if(STATUS.STATUS_Ptr->Status_LO
SCB.SCB_Ptr->FRTL += 1;
TX_ERR = TRUE;
,. for status

&

OxOOBO)

& Ox0040)
& Ox0010)

display purposes .,

I

r

Fatal errors, ELM Software Package initiates another transmission of

0'

the frame
if! (STATUS.STATUS_Ptr->Status_Ll & OxOOOF)
(STATUS.STATUS_Ptr->Status_LO & Ox0020»
[

if (STATUS. STATUS_Ptr-> Status_Ll & Ox0001)
SCB.SCB.Ptr->UndernErrs+= 1;
if(STATUS.STATUS_Ptr->Status_l_l & Ox0004)
SCB.SCB_Ptr->LOST_CRS+= 1;
if(STATUS.STATUS_Ptr->Status_l_l & Ox0002)
SCB.SCB_Ptr->LOST_CTS+= 1;
if(STATUS.STATUS_Ptr->Status_l_l & OxOOOB)
SCB.SCB_Ptr->LTCOL += 1;
if(STATUS.STATUS_Ptr-> Status_l_O & Ox0020)
[

SCB. SCB_Ptr- > MAX_COLL += 1;
if( !(STATUS.STATUS_Ptr->Status_1_0 & OxOOOF))
SCB.SCB_Ptr->Num_COLL += Ox10;

I

r

FLAG_RE_XMT = TRlJE;
signals Re_XMT. is required .,
INT_STAT_RDY = TRUE;
TX_ERR = TRUE;
" for status display purposes
return;

0'

rI xmt

ok .,
if (STATUS.STATUS_Ptr->Status_l_1 & Ox0020)
(

SCB.SCB_Ptr->TX_OK += 1;
UPDATE_TXCNT = TRUE;
RETRY_CNT = 0;

I

inter

Ap·327

CODE EXAMPLE 10 (Continued)

/ •••••••••• statistics ••••••••••••••• /

=

INT_STAT_RDY
TRUE;
/......... if xmt loop •••••••••••••••• / TermCount - ;
/. reload running counter '/
if«XMT_FOREVER
TRUE) && (TermCount
0))
TermCount
Ox7FFF;
i f (TermCount > 0)
XMT_LOOP
TRUE; /. set condition for next frame transmission, if
transmission in loop is requested ./

=
=

==

==

return;

I

9.0 SOFTWARE DESIGN HINTS
9.1 Segment Boundaries

The PC AT DMA subsystem uses an 8-bit page register
which allows 24 bit addressing. The page register divides the 16 MB memory space into 128KB physical
segments in the 16-bit channels. This is because the
address 0 through 15 generated by the 8237A drive
address I through 16 of the system. in the 16-bit channels the page register is used to generated address 17
through 23. If a buffer is allocated so that it lies in two
physical segments, a special logic should take care of
segment boundary crossing and update the page register. To prevent this complicated logic, memory buffer
allocation should prevent physical segment boundary
crossing.
9.2 Set Pointer

The internal status registers of the 82592 are read in
sequence. One of the ISR operations is reading the
status. One should make sure that the first byte of
status is read first. The background utilities can be interrupted while reading the status. In that case, the internal 82592 status register pointer is not set to O. However, the background software will now get the status
pointer set to 0, while it expected it to be different.
Hence, during status read in the background, the interrupts should be disabled.
9.3 Interfacing with DOS'

The 82592 can interrupt the program at any instant.
Since the ELM Exerciser software is run under the
DOS, the 82592 may interrupt a DOS system call. DOS
saves a small stack for its own use. It does not support
other uses for this stack. Calling routines or passing

parameters by using the DOS stack may cause a stack
overflow error and consequently a system collapse. In
order to prevent this from happening, a private stack
was constructed. Its size is dependent upon the routine
calls within the ISR and upon the stack required for
passing parameters to or from called routines.
9.4 Screen Operations

It is not advisable to use DOS screen operations from
within the ISR.This may cause the system to collapse,
due to DOS not being reentrant. Within the ISR, one
can use a software flag to indicate that data for screen
update is available. In the main program outside the
ISR, DOS services or direct BIOS calls can be made.
9.5 Nested Interrupts

The first check made when interrupt processing starts
is whether this is a nested interrupt. A memory variable
"counter" is incremented every time execution of int_
hnd starts and decremented just before exiting. If
"counter" is greater than I, then this is not the first
entry, it is a nested interrupt. In the code example, the
processing continues at the label "inter." This demonstrates that, since we are using the local environment,
execution has to continue using the current stack pointer and it should not be set to initial value. In this case,
local.environment restoration is skipped.
Another method to prevent interrupt nesting is by not
issuing the "STI" command in the "int_hnd" routine.
This blocks the CPU interrupt input and prevents external interrupt sources from preempting the "int_
hnd" execution. The drawback of this approach is that
it can significantly enlarge the interrupt latency of other devices. These devices may not be designed to cope
with long interrupt latencies.

.1-339

Ap·327

APPENDIX A
LIST OF USEFUL DOCUMENTS
Documents used in the development of the NetWare
driver.
1) Advanced NetWare V2.1 Internetwork Packet Exchange Protocol (IPX) with Asynchronous Event
Scheduler (AES) Revision 1.00. Copyright Novell,
Inc.
'
2) Net Ware V2.1 Driver Specification for Network Inter-

face Cards Copyright Novell, Inc.
3) Advanced Net Ware Theory of Operations Version 2.1
Copyright Novell, Inc.

Other Useful Documents
4) Internet Transport Protocols (Xerox Corporation;
Xerox System Integration Standard; Stamford, Connecticut; December,1981; XSIS-028112)
5) Local Area Network (LAN) Component User's Manual1988 Edition Copyright Intel Corporation
6) AP-320 Using the Intel 82592 to Integrate a Low Cost
Ethernet Solution into a PC Motherboard Copyright
Intel Corporation, 1988
7) 82590-82592 Advanced LAN Controller A-I Step Er, rata version 1.2, December, 1988

1-340

intJ

AP-327

APPENDIX B
ELM EXERCISER FLOWCHARTS
ELM Exerciser Program RCV ISC Flow Chart
START

y

292062-6

1-341

AP-327

ELM Exerciser Program RCV ISC Flow Chart (Continued)

292062-7

ELM Exerciser Program Transmit ISR Flow Chart

UPDATE· TOTAL

# of COLLISIONS

(NUM-COLL)

UPDATE COUNTER:
DEFERRED DURING XMT
HEART BEAT
FRAME TOO LONG

FATAL ERRORS
UNDER RUN
LOST CRS
LOST CTS
LATE COLLISION
MAX COLLISION
UPOATE COUNTERS
SC_T SW RETRANSMIT FLRS
EXIT

SET XMT LOOP

to ALLOW NEXT
FRAME XMT
EXIT
292062-8

1-342

intJ

Ap·327

NetWare Driver Flowcharts
Driver Broadcast Packet
Driver Send Packet

Drop Through

to StarLSend
292062-9

1-343

AP-327

Start Send

Calculate Padding

Calculate Byte Count to
Move Into Tx Buffer Space
Get Destination Address From
ECB to Move Into Buffer
Move ENet Length Field
Into Buffer
Get Fragment Count
Into AX Register
Get Length and Location of
f'lrst Fragment (or Next)
Copy to Tx Buffer
Decrement Fragment Count

292062-10

1-344 -

inter

AP-327

Driver Poll

IPX Hold Event

292062-11

1-345

inter

Ap·327

DriverlSR

292062-12

1·346

inter

Ap·327

rcvd_packet

292062-13

1-347

inter

AP-327

Process Frames

292062-14

1-348

inter

AP-327

Process Frames (Continued)

292062-15

1-349

inter

AP·327

SenLPacket

Put proper completion
code in transmit ECB then
unlink it from send_list
and return It to IPX

No

292062-16

1-350

inter

Ap·327

APPENDIX C
NETWARE DRIVER SOURCE CODE LISTING
NetWare Driver Source Code Listing
$mod186
;********************************************************************

lIt!!! FOR EVALUATION PURPOSES ONLY!!!!!!
NetWare(Rl Driver for the LAN-On-MotherQoard Module
This shell driver is written for use in SYP301 systems.
Joe Oragony

DFG Technical Marketing

REVISION 3.11
Last revision: Date 04-12-89

Time 16:30

;**********************************************************************

'*define(slowl local label
jmp
short 'label
Uabel:

'*define(waitl local label (
mov ex. 03Fh
'label:
nop
loop 'label

'*define(fastcopyl local label (
shr ex, 1
rep movsw

jnc Uabel
movsb

Uabel:

'*define(inc32 ml (
add word ptr tm[Ol. 1
ado word ptr 'm[21. 0
292062-17

1-351

intJ

AP-327

NetWare Driver Source Code Listing (Continued)
name

LANOnMotherboardModule

CGroup

group

assume

Code

Code, mombo_init

cs: CGroup, ds: CGroup

segment word public 'CODE'
public
public
public
public
public
public
public
public

Dri verSendPacket
DriverBroadcastPacket
DriverOpenSocket
DriverCloseSocket
DriverPoll
DriverCancelRequest
DriverDisconnect
SDriverConfiguration

public

LANOptionName

extrn
extrn
extrn
extrn
extrn
extrn
extrn
extrn
extrn
extrn
extrn

IPXGetECB: NEAR
IPXReturnECB: NEAR
-IPXReceivePacket: NEAR
IPXReceivePacketEnabled: NEAR
IPXHoldEvent: NEAR
IPXServiceEvents: NEAR
IPXlntervalMarker: word
MaxPhysPacketSize: -word
ReadWriteCycles: byte
IPXStartCriticalSection: NEAR
IPXEndCriticalSection: NEAR

iii;;;;;;;;;;;;;;;;;

Equates
iii;;;;;;;;;;;;;;;;;

equ 1
TRUE
FALSE
equ
CR
equ ODh
LF
equ OAh
equ OFFh
BAD
BPORT
equ
IRQLOC
equ
DMAOLOC
equ
DMA6LOC
equ
TransmitHardwareFailure
Packet UnDeliverable
equ
PacketOverflow
equ
ECBProcessing
equ
TxTimeOUtTicks
equ

0

19
23
25

equ
OFEh
OFDh
OFAh
20

OFFh

292062-18

1-352

AP-327

NetWare Driver Source Code Listing (Continued)
Latch definitions
TenCentLo
equ 301h
TenCentHi
equ 302h
Enables for lOcent
EnLAN
equ 303h
DisLAN
equ 304h
B259

definitions

InterruptControlPort
InterruptMaskPort
ExtralnterruptControlPort
EOl

equ
equ
equ
equ

020h
OAlh
OACh
020h

:for secondary B259A

8237 definitions
DMAcmdstat
DMAreq
DMAsnglmsk
DMAmode
DMAff
DMAtmpclr
DMAclrmsk
DMAallmsk
DMA6page
DMA6addr
DMA6wdcount
DMA7page
DMA7addr
DMA7wdcount
DMAtx6
DMAtx7
DMArx6
DMArx7
DMA6msk
DMA6unmsk
DMA7msk
DMA7unmsk
DMAena

equ ODOh
equ OD2h
equ OD4h
equ OD6h
equ ODBh
equ ODAh
equ ODCh
equ ODEh
equ OB9h
equ OCBh
equ OCAh
equ OBAh
equ OCCh
equ OCEh
equ OlAh
equ OlBh
equ 006h
equ 007h
equ 006h
equ 002h
equ 007h
equ 003h
equ OlOh

idemand mode, autoinit, read transfer

; demand mode, autoinit, read transfer
;demand mode, no autoinit, write transfer
idemand mode, no autoinit, write transfer

292062-19

1·353

Ap·327

NetWare Driver Source Code Listing (Continued)
82592 Commands
C_NOP
C_SWPl
C_SELRST
C_SWPO
C_IASET
C_CONFIG
C_MCSET
C_TX
C_TDR
C_DUMP
C_DIAG
C_RXENB
C_ALTBUF
C_RXDISB
C_STPRX
C_RETX
C_ABORT
C_RST

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
~_RLSPTR
C_FIXPTR equ
C_INTACK equ

OOh
lOh
OFh
Olh
Olh
02h
03h
04h
05h
16h
01h
18h
09h
lAh
lBh
OCh
ODh
OEh
OFh
lFh
80h

;;\;;;;;;;;;;;;;;;;;;;;;;;;;;; ;

Data Structures

ii;;;;;;;;;;;;;;;;;;;;;;;:;;;;
even
hardware structure

-

io_addrl
io_rangel
io_addr2
decode_range2
mem_addrl
mem_rangel

mem_addr2
mem_range2
int_usedl
int linel
int_used2
int 11ne2
dma_usedl
dma_chanl
dma_used2
dma_chan2

-

hardware_structure

struc

dw
dw
dw
dw
dw
dw
dw
dw
db

?

db
db

db
db
db
db
db

?

ends
292062-20

1-354

intJ

AP-327

NetWare Driver Source Code Listing (Continued)
ecb_structure

struc

dd
0
dd
0
db
completion_code
db
0
socket_number
dw
ipx_workspace
db
transmitting
db
0
driver_workspace
db
11
immediate_address
db
6
dw
fragment_count
fragment_de script or_ list
db
6
ecb_structure
ends
link

esr_address
in_use

fragment_descriptor
fragment_ address
fragment_length
fragment_descriptor

(0)

dup (0)
dup (0)
dup

(1)

struc

dd
dw
ends

rx_buf_structure
struc
rx_dest addr
db
rx_source_addr
db
rX-9hysical_length dw
rx_checksum
dw
rx_length
dw
rx_tran_control
db
rx_hdr_type
db
rx_dest_net
db
rx_dest_node
db
rx_dest socket
dw
rx_source_net
db
rx_source_node
db
rx_source_socket
dw
rx_buf_structure
ends

-

-

tci_status
statusO
deadl
statusl
dead2
bc_lo
dead3
bc_hi
tci_status

dup

dup

(1)

6 dup ( 1)

dup

( 1)

6 dup (1)

dup

( 1)

6 dup (1)

strue

db
db
db
db
db
db
db
ends

1
292062-21

1-355

inter

AP-327

NetWare Driver Source Code Listing (Continued)
ipx_header_structure
struc
checksum
dw
packet_length
dw
transport_control
db
packet_type
db
destination_network db
db
6
destination_node
dw
destination_socket
db
4
source_network
db
6
source_node
dw
source_socket
?
ends
ipx_header_structure

dup
dup

(1)

dup
dup

(1)

(1 )

(1)

;;;;;;;:;:;;:;;;;;;;;;;;;;;

Variables
ii;;;;;:;;;;;;;;;;;;;;;;;:;
even

tx_start_time
adapter_io
con fig
send_list
buffer_segment
rx_ecb

tx_ecb
config_block

dw
dw
dw
dd
dw
dd
dd
db

°
:points to list of ECBs to be sent

°
1

?
?

OFh,OOh,48h,80h,26h,OOh,60h,OOh,OF2h,OOh,OOh,40h,OF7h,OOh,3Fh, 87h,OFOh,OFFh

db
temp_flag
int_mask_register dw
dd
old_irq_vector
dw
int_vector_addr
db
int_mask
db
int_unmask
dw
command_req
dw
read_in_length
db
config_dmaO_loc
db
config_dmill_loc
db
config_irq_loc
dw
config_bport
db
tx_active_flag
frame_status

db

statuslO
statusll
status20
status21

db
db
db
db

o

1

300h

:82592 port

° address

?

°°
°o
o
o
292082-22

1-356

inter

AP-327

NetWare Driver Source Code Listing (Continued)
even

gp_buf_offset
gp_offset_adjust
gp_buf_start
gp_bufyage
tx_byte_cnt
rx_buf_start
rx_bufyage
rx_buf_head
rx_buf_tail
rxJ>uf_ptr
rx_buf_stop
rx_buf_length
rx_buf_segment

curr_rx_length
rx_list
nurn_of_frames
reset_rx_buf
padding

dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw

5000 dup (0)
1388h
cgroup:gp_buf

;twice the required size

o
o

o
o
o
o
o

o
o
o
o
o

;A1-A16 of General Purpose Buffer EA
;A17-A23 of General Purpose Buffer EA
;1PX packet length plus header length
;A1-A16 of General Purpose Buffer EA
;A17-A23 of General Purpose Buffer EA
;current rx head, buffer has been flushed to here
;value read from 10 cent latches
;used during rx list generation
:point to reset the DMA controller'

;calculated at in it for use by IPXReceivePacket

o
180 dup (0)

o

o
o

Define Hardware Configuration
ConfigurationID

db

SDr1verConfiguration

LABEL

reservedl

db
db
db

node_addr
reserved2

node_addr_type
max_data_s1ze
lan_desc_offset
lan_hardware_id
transport_time
reserved_3

major_version
minor_version
flag_bits
selected_configuration
number_of_configs
config_pointers

db

dw
dw
db
dw
db
db
db
db
db
db
dw

'NetWareDriverLAN WS
byte
4 dup (0)
6 dup (0)
a
inon-zero means is a real driver.
o
;address is determined at initialization
1024 ;largest read data request will handle
LANOptionName
OAAh
;Bogus Type Code
1
;transport time
11 dup (0)

Olh ;Bogus version number
OOh

o
;board configuration (interrupts, 10 addresses, etc.)
01
conf1gurationO
292062-23

1-357

inter

AP-327

NetWare Driver Source Code Listing (Continued)
LANOpt ionName'
confiqurationO
db
dw
db
dw
db
db
db
db

db

'Intel LAN-On-Motherboard Module',O,'$'

dw

300h, 16, 0,

a
a, a
a
a , a

;~mory

a

;IO ports and ranges

decode

;~nterrupt level 10
OFFh, 10, 0, 0
;DHA channels 6-and 7
OFFh, 6, OFFh, 7
0,0
'IRQ la, IO Addr - 300h, DHA 6 and 7, For Evaluation Only',

a

;********************************************************

Error Counters

-'.********************************************************
Public DriverDiagnosticTable,DriverDiagnosticText
DriverDiagnosticTable

LABEL

dw
DriverDebugCount
db
DriverVersion
db
StatisticsVersion
dw
TotalTxPacketCount
dw
TotalRxPacketCount
dw
NoECBAvailableCount
dw
PacketTxTooBigCount
PacketTxTooSmallCount
dw
PacketRxOverfloWCount
dw
dw
PacketRxTooBiqCount
dw
PacketRxTooSmallCount
dw
PacketTxMiscErrorCount
PacketRxMiscErrorCount - dw
dw
RetryTxCount
ChecksumErrorCount
dw
HardwareRxMismatchCount dw
NumberOfCustomVariables dw
DriverDebugEndl

LABEL

byte
DriverDebugEnd-DriverDiagnosticTable
01,00

oi,oo
0,0
0,0

a
-1
-1

;not used

;not used

a
a
a
-1

;not used

-1

;not used

a
-1

;not used

a
(DriverDiagnosticText-DriverDebugEndl)/2

byte 292062-24

1-358

AP-327

NetWare Driver Source Code Listing (Continued)
i;i:;;;;;;;;;;;;:;;;;;;;:;;;;;;;;;;;;;;
Driver Specific Error counts

.......................................

""""""""""""""""",,,,,
rx_errors
underruns
no_ets
no_ors
rx_aborts
no_590 int
false_590 int
lost rx
stop_tx
ten cent latch_crash
rX_disb_failure
tx_abort failure
rx_buff_ovflw
tx_timeout

-

-

dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw

0
0
0
0
0
0
0
0
0
0
0
0
0
0

DriverDiagnosticText

db
db

db
db
db
db
db
db
db
db
db
db

LABEL

, RxErrorCount' ,

byte

°

'Underruncount',O
'LostCTSCount',O

'LostCRSCount',O
'RxAbortCount',O

'N0590InterruptCount',0
'False590InterruptCount' ,0
'LostOurRece1vercou~t',O

'QuitTransmittingCount',O
'TencentLatchCrashCount',O

db
db

'RxDisableFailureCount',O
'TxWontAbort',O
'ReceiveBufferOverflow',O
'TxTimeoutErrorCount',O

db

0,0

DriverDebugEnd

LABEL

word
292062-25

1-359

Ap·327

NetWare Driver Source Code Listing (Continued)
;****.*._-*-_.*.* ••• * ••

_*_ .... _... __ .. *.**--**.* ••• ****************

Interrupt Procedure

;_ •. _*.*.*_ •• * •••• *_ .. __ .. *-_ .. *._---*_.*_ ..... _.. *._-**.* .. _* •••• _.
even
~xErrorTypeCheck:

BufferOyerflow:
inc
rx_buff_oYflw
jmp
int_exit

not_590_int:
inc no_590_int
jmp int_exit
OriYerISR
public

PROC
OriYerISR

far

call IPXStartCriticalSection
;tell AES we're busy
pusha
push ds
;save machine state
push es
cld
;read current interrupt mask
in al, InterruptMaskPort
;mask our channel
or al, int_mask
'slow
;write it to the 8259A
out InterruptMaskPort, al
moy a1, EOI
out InterruptContro1Port, a1
;issue E01's to the 8259A's
out ExtralnterruptControlPort, al
;e,nable interrupts to be friendly
sti
mov ax, cs
;OS points to C/OGroup
mov ds, ax
;ES also
mov es, ax
mov dx, command_reg
mov a1, 0
;set status reg to point to reg 0
out dx, al
'slow
in a1, dx
;read status from 82592
test al, 80h
;cheek if the INT bit is set
jz
not_590_int
292062-26

1-360

inter

AP-327

NetWare Driver Source Code Listing
int_poll_loop:
and aI, NOT 20h
mav

ah, a1

cmp

ah, OD8h
rcvdyacket
ah, 84h

jz
cmp
jz
cmp
jz
inc
jrnp

(Continued)

;ignore the EXEC bit
isave the status in AH
;did I receive a frame?
;did

finish a transmit?

ah, aCh
;did I finish a retransmit?
sent-packet_jmp
false_590_int ;unwanted interrupt
int_exit

sent-packet_jmp:
jmp sentyacket
bad_rev:
inc

rx_errors

jmp

RxErrorTypeCheck

int_exit_jmp:
jmp int_exit
;When the address bytes are being read it is possible that another frame
;could come, in and cause a coherency problem with the ten-cent latches.
; I am dealing with this possibility by reading TenCentHi twice and making
;sure the values match. If they don't the read is redone.
rcvd-packet:
eli
mav

dx, TenCentHi ;read high address byte of last frame received

in

aI, dx

mav

ah, a1

;save it in ah

mov
in

dx, TenCentLo ; read low address byte of last frame received
aI, dx
;this is the last location containing rx data
;Read TenCentHi again to make sure it hasn't changed .•.•.••
mov dx, TenCentHi
;read high address byte again
aI, dx
in
;da values match?
cmp aI, ah
;if so, proceed
jz addr_ok
;else, read the latches again
jmp rcvdyacket
addr_ok:
;this is a valid address
mov ax, rx_buf_tail
;this is the last location containing rx data
moV rx_buf_ptr. ax
lis most of the buffer already used?
cmp rx_buf_stop, ax
;if not, proceed
ja BufferOK
;else, set flag for exit routin'e
mov reset- rx_buf. 1
BufferOK:
cmp

ax, rx_huf_head
;have we really received a frame?
ja process_new_frames
; if so, process it
inc ten_cent_latch_crash ;else, increment error count and exit

jmp

int_exit
292062-27

1-361

Ap·327

NetWare Driver Source Code Listing (Continued)
process_new_frames:

call ProcessFrames
int_exit:
push cs
pop ds
cmp 'tx_active_flaq. 0
jnz finish_exit
verify that our receiver is still qoinq.
mov
mov
out
'slow
in
test
jnz
jmp

dx, co~and_req
aI, 60h
:point to status byte 3
dx, a1
:read status byte 3
;check to see if, receiver is enabled
; i f SO, proceed
;else, take eorre~tive action
LostOurReceiver

aI, dx
a1. 60h

intyendinq:
jmp 1nt_po1l_1oop

finish_exit:
cli
mav

mov
out
'slow
xor

out
'slow
in
test
jnz
cmp
jnz
mov
out
mov
in

dx, command_reg

a1. C_INTACK
dx. al

:issue interrupt acknowledqe to the 590

a1, A1

;clear a1

dx. al

;set status req to point to req 0

; read status 0
a1, dx
lis INT bit set1
al. 80h
int-pendinq ;if so. service pendinq interrupt
;do we need to reinitialize receive DMA channe11
reset_rx_buf. 1
no_rx_buf_reset
al, dma7msk
:mask receive DMA channel
DMAsnqlmsk. al
;read hiqh address byte of last frame received
dx. TenCentHi
al, dx
moV ah,. a1
:save it in ah
:read low address byte of last frame received
mov dx. TenCentLo
in a1. dx
;de we have a new frame1
cmp ax. rx_buf_head
jna no_new_frames
;this is the last location containinq rx data
'mov rx_buf_tail. ax
:set pointer for use durinq buffer processinq
mov rx_buf-ptr. ax
call ProcessFrames
292062-28

1-362

AP-327

NetWare Driver Source Code Listing (Continued)
no_new_frames:
mov dx. command_reg
;issue rx disable to kill any active requests
mov al. C_RXDISB
out dx. al
mov al. C_SWP1
out dx. al
mov al. C_SELRST
out dx. al
'slow
mov al. C_SWPO
out dx. al
out DMAff. al
;data is don·t care
mov ax. rx_buf_start
;set dma up to point to the beginning of rx bUf
mov rx_buf_head. ax
shl rx_buf_head. 1
out DMA7addr. a1
mov al. ah
'slow
out DMA7addr. al
mov al. DHArx7
'slow
;set proper mode for receive
out DMAmode. a1
mov ax. rX_buf_1ength ;set up rx buf

'slow
out

mav
'slow
out
mov
mov
'blow
out
mav
mov
out
mov

DMA7wdcount, al

a1, ah

DMA7wdcQunt. al
dx. DMAsnglmsk
al. DMA7unmsk
dx. al
dx, command_req
al. C_RXENB
dx. al
reset_rx_buf. 0

;make sure receiver is enabled
;clear the flag

no_rx_buf_reset:
eli
call IPXEndCriticalSection
in al. InterruptMaskPort
and al. int_unmask
'slow
out InterruptMaskPort. al
pop eB
pop dB
papa
sti

iret
292062-29

1-363

AP-327

NetWare Driver Source Code Listing (Continued)
LostOUrReceiver:
inc lost rx
mov al, C_RXENB
mov dx, command_reg
out dx, al
jmp finish_exit
too_big:
inc PacketRxOverflowCount
jmp int_exit
sentJlacket:
eli
cmp tx_&ctive_flag, 0
jz
false_tx_int
;shouldn't have been transmitting
in
al, dx
mov statuslO, al
'slow
in
al, dx
mov statusll, al
test statusll, 20h
jz
tx_error
mov al, statuslO
;extract the total number of retries from
and ax, OFh
;the status register and add to retry count
add RetryTxCount, ax
xor ax, ax
;status - 0, good transmit
FinishUpTransmit:
les si, send_list
cmp es: [sil.transmitting, TRUE
jnz ecb_cancelled

;if the transmitting flag is not set
;then an ECB has been cancelled and

moves: [sil.completion_code, al
mo~

mov
mov
mov

ax, es: word ptr [sil.link
~ord ptr send_list, ax
ax, es: word ptr [sil.link + 2
word ptr send~list + 2, ax

mav

es: [si] . in_use .. 0

;this is a fresh one

;,finish the transmit

call IPXHoldEvent
ecb_caneelled:
push cs
pop ds
mov ex, word ptr send_list + 2
mov tx_aetive_flag, c1
jcxz int_exit_jmpl
;segment of next SCB in list
mov es, ex
;offset of next SCB in list
mav si, word ptr send_ list
call start_send
jmp f~nish_exit
int_exit_jmpl:
jmp int_exit
292062-30

1-364

inter.

AP-327

NetWare Driver Source Code Listing (Continued)
false_tx_int:
jmp int_exit
tx_error:
;Max collisions??
test statuslO. 20h
jnz QuitTransmittinq
;Tx underrun1?
test statusll. Olh
lost_cts
jz
inc underruns
lost_cts:
;did we lose clear to send??
test statusll. 02h
jz
lost_crs
inc no_cts
lost_crs:
;did we lose carrier sense??
test statusll. 04h
jz
hmmm
inc no_era
hmmm:
mov al. TransmitHardwareFailure
jmp FinishUpTransmit
QUitTransmittinq:
mov al. statuslO
and ax. OFh
add RetryTxCount,. ax
inc stop_tx
mov al. TransmitHardwareFailure
jmp FinishUpTransmit
DriverISR

endp

ProcessFrames:

a routine to process received frames and hand them
off to IPX

Assumes: rx_buf_tail and rx_bufytr have been set up with the value
read from the ten cent latches.
Returns: nothinq
292062-31

1-365

inter

Ap·327

NetWare Driver Source Code Listing (Continued)
ProcessFrames

proc

near

do_next_frame:

sti
mov
sub

bx, rx_buf-ptr
bx, 6

maves, rx_buf_se9ment

lend of current frame to process

;set bx up to point to beginning of the status
;this is necessary because latches hold EA not

;offset relative to CGROUP
mov al, es:[bxl.status1
test al,20h
;test for good receive
jnz good rx
inc

rx_errors

mov c1, es: [bxJ.bc_10
;cx has actual number of bytes read
mov ch, es: fbxJ.bc_hi
; toss byte count , status
dec cx
; round up
and cl, Ofeh
;bx points to first location of frame
sub bx, cx
cmp rx_buf_head, bx
hand_off-yacket_jmp ; this was the first frame in the sequence
je
cmp rx_buf_head, bx
;this frame is a fragment in the beginning of
ja check_rx_queue
;the receive buffer
mov rx_bufytr, bx
sub rx_buf-ytr, 2
to_do_next_frame:

jmp do_next_frame
hand_off-packet_jmp:
jmp hand_off-packet ~~
check_rx_queue:

cmp

num_of_frames, 0

;have any frames been processed?

jne
jmp

hand_off-yacket_jmp
process exit

;if yes, give them to IPX
;if not, go back to ISR

good rx:
mov cl, es:[bxJ.bc_lo
mov ch, es:[bxJ.bc_hi
mav
dec

curr_rx_lenqth, ',ex
ex

and

cl, Ofeh

sub

bx, ex

cmp rx_buf_head, bx
ja check_rx_queue
mov rx_buf-ptr, bx
sub rx_buf-ytr, 2
sub

ex, 14

cmp
jbe
inc
jmp

cx, 1024 + 64
not_too_big
PacketRxTooBigCount
do_next_fram,e

;cx has actual number of bytes read
;toss byte count , status
;round up

;bx'points to first location of frame

;rx_buf_ptr = last location of n-l frame
;sub length of 903.2 header

not_too_big:

cmp

ex, 30

jae
inc

not too_small
PacketRxTooSmallCount
292062-32

1-366

inter.

AP-327

NetWare Driver Source Code Listing (Continued)
not._t.oo_srnall:
mov ax, es:[bxl.rx_length
xchg aI, ah
inc

and
xchg
cmp
jne
xchg
cmp
ja
rnov
len_ok:
cmp
jz

inc
jrnp

get· IPX length

ax

al. Cfeh
al. ah
same as 802.3 length
ax. es:[bxl.rx-Fhysical_length
to_do_next_frarne
al. ah
;at least min length minus header
14
ax. 60
;yes, continue
len_ok
;no, round up
ax. 60 - 14
;match physical length

ax, ex
not_inconsistent

;yes, continue

HardwareRxMisrnatchCount

do_next_frame
not_inconsistent:

\inc32

TotalRxPacketCount

Double Word Increment

mav

ax, 12

mul
mov
add

nurn_of_frames
di, ax
rx_Iist [dil. bx
rx_list [dil. 14

mav

ax, rx_buf_segment

rnov
mov
xchg
mov
mov

rx_list [di + 21. ax
ax. word ptr es:[bxl.rx_length
al. ah
rX_Iist. [di + 41. ax
ax. word ptr es:[bx).rx_source_addr + 0

mav

rx_~i5t

;first location of ethernet frame
;first location of ipx packet

[di + 6], ax

mav

word ptr

mov

ax, word ptr es:[bx).rx_source_addr + 2

mov

word pt.r rx_list [di + 81. ax

moV

ax, word ptr es:[bx).rx_source_addr +

rnov
add

word ptr rx_list [di + 101. ax
nurn_of_frames. 1

cmp

nurn_of_frames, 50

je
cmp
je
jrnp

hand_off-Facket.
rx_buf_head. bx
hand_off_packet.
do_next_frame

;prevent list overflow

292062-33

1-367

AP-327

NetWare Driver Source Code Listing (Continued)
hand_off-packet:
;offset in receive buffer space
mov si, rx_list[dl]
moves, rx_list[di + 2] :receive buffer bogus segment
mov cx, rx_list[di + 4] ;IPX packet length
lea bx, rx_list[di + 6] ;pointer to immediate address
cli
push ds
call IPXReceivePacketEnabled ;since packet is contiguous let IPX do
;the work
pop ds
;decrement count
sub nurn_of_frames, 1
;if all frames are processed adjust head
jz adjust_rx_head
sub di, 12
jmp hand_off_packet
adjust_rx...:head:
mav

add
mav

ax, rx_buf_tail
ax, 2
rx_buf_head, ax

process_exit :
ret
ProcessFrames

;otherwise index to next list entry
;and loop to process next frame
:location of last location used in receive
:index to next word location
;set rx_buf_head to new value for next receive

; interrupt
endp

Driver Send Packet
Driver Broadcast Packet
Assumes

ES:SI points to a fully prepared Event Control Block
OS = CS
Interrupts are DISABLED but may be reenabled temporarily if necessary
don't need to save any registers
DriverBroadcastPacket:

NEAR
PROC
DriverSendPacket
; disable the interrupts
cli
moves: [siJ,transmitting, FALSE ;make sure the flag is initially clear
mov cx, word ptr send_list + 2
lit will be used later to prevent a
jcxz AddToFrontOfList
;cancelled ECB from being given to IPX twice
;search to. the end of the list, and add there.
mov di, word ptr send_list
AddToListLoop:
mav ds, ex
mov cx, ds: word ptr [diJ.link + 2
jcxz AddListEndFound
mov di, ds: word ptr [di].link
jmp AddToListLoop
292062-34

1-368

inter

AP-327

NetWare Driver Source Code Listing
AddListEndFound:
mov es: word
mov es: word
mov ds: word
mov ds: word
mov ax, es
mov ds, ax
ret

ptr
ptr
ptr
ptr

lsi] • link. ex
lsi] • link + 2, ex
[di] .link, si
[di].link + 2, es

(Continued)

imove null pointer to newest SCB's
:link field

iset ds back to entry condition

AddToFrontOfList:
mov es:word ptr[si].link, cx
mov es:word ptr[si].link + 2, cx
mov word ptr send_list, 51
mav word ptr send_list + 2, es
;drop through to Start Send
DriverSendPacket

endp

Start Send
assumes:

points to the ECB to be sent.
ES: SI
interrupts are disabled

PRoe

start_send

public
cli
cld
mav

NEAR

start_send

; disable the interrupts
es:

[s1] .transmitting, TRUE

;save SCB address in variable tx_ecb to liberate registers
mav

mav
push
;get IPX
Ids
mov
pop
push
xchg
add

mov
cmp
ja
mov
sub
mov

word ptr tx_ecb, 81

word ptr tx_ecb + 2, es
ds
;save ds for future use
packet length out of the first fragment (IPX header)
bx, es: dword ptr [si].fragment_descriptor_list
ax, ds: [bx].packet_length
ds
:restore ds to CGROUP
ax
;save length for later use in 590 length field
al, ah
;byte swap for 592 length field calculation
lB
;add in the overhead bytes DA,SA,CRC,length
ax"

padding, 0
ax, 64
long_enough
padding, 64
padding, ax
ax, 64

:minimum length frame

;pad length
292062-35

1-369

inter

AP-327

NetWare Driver Source Code Listing (Continued)
long_enough:
sub ax, 10
inc ax
and aI, OFEh

iSA and eRe are done automatically

mev

;frame must be even
tx_byte_cnt, ax

mov

di,gp_buf_offset

mav bx, os
maves, bx

;move the byte count into the transmit buffer
stosw
imove the destination address from the tx ECB to the tx buffer

mav bx, si
lea si, [bxJ. immediate_address
mav ds,word ptr tx_ecb + 2
movsw
movsw

movsw
mav
mav

get back to the code (Dgroup) section

ax,es
ds,ax

;now the 590
pop ax
xchg ah,
inc ax
and al,
xchg ah,
stosw
Ids si,
mov ax,
lea bx,

length fieid
al
;make sure E-Net length field is even

OFEh
al
tx_ecb

ds: [5i] . fragment_count
[siJ.fragment_deseript'or_list

move_frag_loop:
push ds

; save the segment

mov ex, ds:· [bxJ • fragment_length
Ids si, ds: [bxJ.fragment_address
%fasteopy
; get the segment back
pop ds
add bx, 6
dec

ax

jnz

move_frag_loop

;start transmitting
mav ex, cs
mav ds, ex

;add any required padding
mav

ex, 4

add

ex, padding

;make sure frame ends with a NOP

shr

ex, 1

rep

stDSW

mav
xor
out

tx_active_flag,
ax, ax

DMAff, al

mav

ax, 9P_buf_start

;data is don't care, AX has been zeroed

'slow

out

DMA6addr, al
292062-36

1-370

inter

AP-327

NetWare Driver Source Code Listing (Continued)
mav

tslow
out
mov
tslow
out
'slow
mov
out
maV

add
shr
adc
out
'slow
mov
out
'slow
mov
out

aI, ah

DMA6addr, al
ax, gp_buf-page
DMA6page. al
al. DMAtx6
DMAmode, a1

;DMA page value

;setup channell for tx mode

ax, tx_byte_cnt

ax, 4

;add two for byte count, two for tx chain fetch
;convert to word value and account for odd
;byte DMA transfer
DMA6wdcount, al
ax, 1
ax, 0

al. ah
DMA6wdcount. al
al. DMA6unmsk
DMAsnglmsk. al

maV

dx, command_reg

mov
out

al. C_TX
dx. a1

mev

ax, IPXlntervalMarker

mav

tx_start_time, ax

'inc32
ret
start_send

TotalTxPacketCount

Iget a fix on the time that transmission
istarted and save it for later' use ,

;increment counter

endp

DriverOpenSacket:
DriverDisconnect:
ret
292062-37

1-371

inter

AP-327

NetWare Driver Source Code Listing (Continued)
i*****************************************************

--------_._----**

Driverpoll
Poll the driver to see if there is anything to do
Is there a transmit timeout? If so, abort transmission and return
ECB with bad completion code. Check to see if frames are queued.
I f they are set up ES:SI. and call DriverSendPacket.
i*****************************************************

--_._----_.*----*

DriverPoll
PROC
NEAR
cmp tx_active _flag, 0
jz
NotWaitingOnTx
mov dx, IPXlntervalMarker
sub dx, tx_ start_time
cmp dx, TxTimeOUtTicks
jb
NotTimedOutYet
This'transmit is taking too long so let's terminate it now
Issue an abort to the 82592
mav

dx, command_reg

mov aI, C_ABORT
; abort transmit
out dx, al
inc tx_timeout
les si, tx_ecb
moves: [sil.completion_code, PacketUnDeliverable
mov ax, es: word ptr [sil.link
mav

word ptr send_list, ax

mov
mov

ax, es: word ptr [sil.link + 2
word ptr send_list + 2, ax

;stuff completion code of a failed tx

Finish the transmit
mov e~: [sil.in_use, 0
call IPXHoldEvent
292062-38

1-372

Ap·327

NetWare Driver Source Code Listing (Continued)
;make sure that execution unit didn't lock up because of abort errata

mov
mov
out
hait
mov
out
'wait
mov
out
'wait
mov
out
mov

dx, command_reg
al, C_SIIPl
dx, al
al, C_SELRST
dx, al
aI, C_SIIPO
dx, al
aI, C_RXENB
dx, al
tx_aetive_flaq, 0

;See if any frames are queued

mov ex, word ptr
jexz queue_empty
mov es, ex
mav' ai, word ptr
call start_send
queue_empty:

NotWaitinqOnTx:
NotTimedOutYet:
ret
DriverPoll

endp
292062-39

1-373

intJ

Ap·327

NetWare Driver Source Code Listing (Continued)

Driver Cancel Request

Assumes on entry:
ES:SI is.pointer to ECB· we want to cancel
OS is setup
Interrupts are DISABLED

Assumes any registers may be destroyed.
Returns completion code in AL:
00
Buffer was located and canceled.
FF
Buffer was not found to be in use by the driver

DriverCancelRequest

PROC

NEAR

;first, see 1f it is the one we are currently sending_

mav
dx, es
word ptr send_list. si
cmp
NotFirstOne
jnz
word ptr send_list + 2, dx
cmp
NotFirstOne
jnz
;we need to cance'l the first entry. first, unlink i t
;from the send list.
ax, es: word ptr [sil.link
moV
word ptr send_list, ax
mov
cx, es: word ptr [sil.link + 2
mov
word ptr send_list + 2, cx
mov
es: [sil.completion_code, OFch
mov
es: [si]. in_use, 0
mov
ax, ax
xor
ret
;we need to search down the send list

NotFirstOne:
mov
cx, word ptr send_list + 2
mov
di, word ptr send_list
ScanTheSendListLoop:
jcxz
NotFound
;move to the next link
es, cx
mov
bx, di
mov
cx, es: word ptr (bx].link + 2
mov
di, es: word ptr (bxl.link
mov
;next node is pointed to by CX:DI
iprevious node is pointed to by ES:BX
isee if we found it
cmp

dl, 5i

jnz

ScanTheSendListLoop

cmp

ex, dx

jnz

ScanTheSendListLoop
292062-40

1-374

inter

Ap·327

NetWare Driver Source Code Listing (Continued)
;we found it. now unlink it.
. push
ds
ds, cx
mov
mov
mov
mov
mov
mov
mov
pop
xor
ret
NotFound:
mov

ax, ds: word ptr [sil.link
es: word ptr [bxl.link, ax

ax, ds: word ptr [sil.link + 2
es: word ptr [bxl . link + 2, ax
ds: [sil .completion_code, O.FCh
ds: [sil.in_use, 0
ds
ax, ax

aI, OFFh

ret
DriverCancelRequest

endp

Driver Close Socket
Assumes on entry:
OX has socket number

OS is setup
Interrupts are DISABLED
Assumes any registers may be destroyed.

DriverCloseSocket PROC NE~
mov
cx, word ptr send_list + 2
jcxz
les

DriverCloseExit
si, send_list

DriverCloseLoop:
cmp
es: [sil.socket_number, dx
jnz
push
call
pop
jmp

DriverToNext
dx·
DriverCancelRequest
. dx
OriverCloseSocket

DriverToNext:
moV
cx, es: word ptr [sil.link + 2

jcxz
les
jmp

DriverCloseExit
si, es: [sil.link
OriverCloseLoop
292062-41

1-375

Ap·327

NetWare Driver Source Code Listing (Continued)
DriverCloseExit:
ret
DriverClosesocket
Code

endp

ends

segment 'CODE'
DriverInitialize, DriverUnHook
db CR,LF,'No adapter installed in PC$'
db CR,LF, 'Configuration Failure$'
config_failure_message
CR,LF,'IA Setup Failure$'
db CR,L~,'configuration underrun$'
ConfigDataUnderrunMess
public

no_card_message

Driver Initialize
assumes:

OS, ES are set to CGroup (== CS)
DI points to where to stuff node address
Interrupts are ENABLED
The Real Time Ticks variable is being set, and the
entire AES system is 'initialized.
returns:

If initialization is done OK:
AX has a 0
If board malfunction:
AX gets offset (in CGroup) of '$'-terminated error string

NEAR
DriverInitialize PROC
mov
MaxPhysPacketSize, 1024
eli

cld
mav
mov
mev

ax, cs
ds, ax'

es, ax

;get DOS time and use for address.
mov
ah,02Ch
int
21h
mov
bx,. OFFSET CGroup: node_addr
moV
byte ptr cgroup:[bxl, OOh
moV
byte ptr cgroup:[bx+1], OAAh
byte ptr cgroup: [bx+2]. ch
mev
byte ptr cgroup: [bx+3], dl
mov
byte ptr cgroup: [bx+4] , dh
moV
byte ptr cgroup: [bx+S], 7Eh
moV
si, bx
mov
292062-42

1·376

AP-327

NetWare Driver Source Code Listing (Continued)
;stuff address at point IPX indicated

movsw
movsw

movsw
sti
;initialize the configuration table
mav

al,selected_configuration

cbw
shl
add
mov
mov

; multiply by two
ax,l
:ax contains the offset value
ax,OFFSET CGROUP:config_pointers
;of the default configuration
bx,ax
;list
bx, [bxj

mav

Confiq,bx

mov
mov
mov

aI, [bx+DMAOLOCj
config_dmaO_loc,al
aI, '[bx+DMA6LOC)

mov
mov

config_dmal_loc,al
aI, [bx+IRQLOC)

mav

confi9_irq_loc,al

mov
mov

ax, [bx+BPORT)
command_reg, 300h

Set The Interrupt Vector:
SET UP THE INTERRUPT VECTORS
push
mov
mov
call

di
aI, config_ir'Lloc
bx, OFFSET CGroup: DriverISR
Set Interrupt Vector

pop
mov
out

di
dx, EnLAN
dx, al

'slow
mov
mov
out

;enable LAN on MB module

dx, command_req
aI, C_RST
dx, al

;

reset the 82592 controller

;generate 20 bit address for DMA controller from configure block location
;this is necessary to accomodate the page register used in the PC DMA

;set up OMA channel for configure command

xor
out

ax, ax
DMAff, al

:data 1s don't care

%slow
mav

aI, DMAena

out
mav

DMAcmdstat, al
ax, 9P_buf_start

%slow
out
mov

DMA6addr, al
aI, ah

292062-43

1-377

intJ

AP-327

NetWare Driver Source Code Listing

(Continued)

'slow
out

mov
\slow
out
mav
hlow
out
mov
blow
out
mov

DMA6addr, al

ax, gp_buf-page
DMA6page, al
ax, 1
DMA6wdcount, al

;DMA page value

;make two transfers

aI, ah
DMA6wdcount, al
aI, DMAtx6

isetup channel 6 for tx mode

'slow
out

mav
'slow
out
xor
mov
stosw
stoaw
blow
mov
mov
out

DMAmode, al

aI, OMA6unmsk
DMAsnglmsk, al
ax, ax
di, gp_buf_offset ;mov zeroes into the byte count field of the
;buffer to put the 82592 into 16 bit mode

dx, command_reg
al, C_CONFIG
dx, a1

;configure the 82592 for 16 bit mode
; i'ssue configure command

'slow
wide_mode_wait_loop:
xor
a1, a1
'slow
dx, al
out
'slow
in
and
cmp
jz
loop
mov
jmp
do_config:
mov
out
xor
hlow
out
mav

%slow
out
mav

hlow
out
mov

IPoint to register 0

al, dx
; read register 0
;disregard exec bit
al,ODFh
aI, 82h
; is configure finished?
do_config
wide_mode_wait_loop
ax, OFFSET CGroup: no_card_message
init_exit

al, C_INTACK
dx, al
ax, ax
DMAff, al

;clear interrupt

;data is don't care

ax, 9P_buf_start

DMA6addr, al
al, ah

DMA6addr, al
ax, gp_buf-page
292062-44

1·378

AP-327

NetWare Driver Source Code Listing (Continued)
'slow

out
%slow
mov
out
%slow
mav
out
hlow
mav
out
%slow
mav
out
mav

DMA6page, al

iDMA

page value

isetup channell for tx mode

aI, DMAtx6
DMAmode, al
ax, B
DMA6wdcount, al
aI, ah
DMA6wdcount, al

al, DMA6unmsk
DMAsnglmsk, al
ax, ds

maves, ax

mov
mov
mav
rep movsb
mov
mov
out
hlow
xor

si, offset cgroup:config_block
di, gp_buf_offset
ex, 18
dx, command_reg
aI, C_CONFIG
dx, al

configure the 82592

cx, cx

config_wait_loop:
%slow
xor
aI, al
, 'slow
out
, %slow
in
and
cmp
jz
loop
mov
jmp

dx, al

;point to register 0

al, dx
;read register 0
al, ODFh
;discard extraneous bits
aI, 82h
; is configure finished?
can fig_done
config_wait_loop
ax, OFFSET CGroup: config_failure_message
init_exit

config_done:
;clear interrupt caused by configuration
mov
aI, C_INTACK
out
dx, al
;da an lA_setup
mov
di, gp_buf_offset
mov
aI, 06h
;address byte count
stasb
mov
aI, OOh
stosb
mov
si, OFFSET CGROUP:node_addr
ex, SIZE node_addr
mov
rep movsb

292062-45

1-379

intJ

Ap·327

NetWare Driver Source Code Listing (Continued)
out
hlow
mav

out
mav
hlow
out
mciv
'slow
but
'slow
mov
out
'slow

;data is don't care

DHAff, al
ax, gp_buf_start

DHA6addr, al
aI, ah
DHA6addr, al
ax, qp_buf.Jlaqe
;DMA paqe value

DMA6paqe, al

;setup channell for tx mode

aI, DMAtx6
DMAmode, al

mav

ax, 3

out

DMA6wdcount, al

'slow
mov
out
hlow
mov
out

mav
mov
out
xor

aI, ah
DMA6wdcount, al
aI, DHA6unmsk
DHAsnqlmsk, al
dx, conunand_reg
;set up the 82592 individual address
aI, C_IASET
dx, al
cx, cx
;cx is used by the loop instruction below. this
;causes the loop to be executed 64k times max

ia_wait_loop,
xor
aI, a1
out
dx, a1
'blow
aI, dx
in
aI, ODFh
and

cmp
jz
loop
mov
jmp
ia_done,
mov
out

;discard extraneous bits
is command finished?

ia_wait_loop
ax, OFFSET CGroup, iaset_failure_messaqe
init_exit

aI, C_INTACK
dx, a1

:clear

int~rrupt

from iaset

;initialize the receive DMA channel
xor
aI, a1
out
DMAff, al
mov
ax, rx_buf_start ;set dma up to point to the beginning of rx buf
blow
out
DMA7addr, al
mev
aI, ah
blow
out
DMA7addr, al
:set rx page register
mov
292062-46

1-380

inter

AP-327

NetWare Driver Source Code Listing (Continued)
"slow
out
mov
"slow
out
mov
"slow
out
mov
"slow
out
mov
'slow
out

DMA1page, al
al, DMArx1
DMAmode, al

;set wordcount to proper value
DMA7wdcount, al
al, ah
DMA1wdcount, al
al, dma7unmsk

;unmask receive DMA channel

DMAsnglmsk, al

;unmask our interrupt channel
in
al, InterruptMaskPort
and
aI, int_unmask
blow
out
InterruptMaskPort, al
;enable the receiver
mev
dx, command_reg
mev
al, C_RXENB
eut
dx, al
xer
ax, ax
cx, 1
mev

DriverInitialize

;enable receives

endp
292062-47

1-381

inter

AP~327

NetWare Driver Source Code Listing (Continued)
Set up Buffers:
This routine generates the page and offset addresses for the 16 bit
DMA. It checks for a page crossing and uses the smaller half of the
buffer area for Tx and general purpose if a crossing'is detected. If
no crossing is detected the general purpose/transmit buffer is placed
at the beginning of the buffer area. This routine also generates a
seqment 'address for the receive buffer which allows the value read
from the "10 cent" latches to be used as read for the offset passed
to IPXReceivePacket. This saves some arithmetic steps when tracing
back through the rx buffer chain.

proc

near

mov ax, offset cgroup: gp_buf
mov qp_buf_offset, ax
mov bx, cs
mov dx, cs
shr ax, 1
mov cx, 3
shl bx, cl
;get upper 3 bits for page register
rol dx, cl
;c1ear all but the lowest 3 bits
and dx, 0007h
laX contains EA of first location in buffer
add ax, bx
;if addition caused a carry add it to page
adc dx, 0
;of buffer to page break
mov cx, OFFFFh
;cx contains the number of bytes to page break
sub ·ex, ax
cmp cx, 01388h
intel_hop
jb
;it's cool, whole buffer space is in one page
jmp copacetic
intel_hop:
cmp cx, 0258h
;low fraqment ·is a usable size, check upper fragment
ja low_ok
;move pointer past the page break to discard fragment
add ax, ex
sub qp~length, cx;adjust length variable to reflect shorter length
mov qp_offset_adjust, cx
shl qp_offset_adjust, 1 ;convert to byte format
mov cx, qp_offset_adjust
add qp buf offset, cx
;adjust qp_buf starting point to reflect change
jmp copacetic
;both buffers will be in the'same page, rx buf shortenec
low_ok:
cJ!lP
jb
mov
jmp

cx, 1130h
high_ok
gp_length, cx;adjust length variable, discard upper buffer fragment
copacetic
;both buffers will be in the, same page" rx buf shortened

high_ok:
cmp
ja
mov
shl
mov

;now since both fragments are, usable we have to fi'nd the
ex, 09C4h
;actual page break. the large' half will be the receive
rx_first
;buffer and the small half will be the gp-tx buffer.
gp_buf-page, dx
qp_buf-page, 1
gp_buf_start, ax
292062-48

1-382

inter

AP-327

NetWare Driver Source Code Listing (Continued)
mov
mov
add

rK_buf_start, OOOOh
rK_buf_head, OOOOh
inext page
dK, 1

mav

rx_buf_page, dx

shl
shl
adc

rx_buf_page,
ax, 1
dx, 0

mav

bx, ex

mav

ex, 12

shl

dx, cl

;save number of bytes to page break

mev

rx_buf_seqment,dx

sub
mov

qp_lenqth, bK
CK, qp_lenqth

mav

rx_buf_length, ex

sub

CK, 258h

shl

ex, 1

add

ex, ax

mav

rx_buf_stop, ex

jmp

buffers_set

rx_first:

mov

rx_buf-paqe, dx

shl
mav

rK_buf-paqe, 1
rx_buf_start, ax

mav

rx_buf_head, ax

shl

rx-puf_head, 1

mov
mov
mov
add
mov
shl
add
shl
mov
add
sub
shl
shl
adc

rK_buf_lenqth, CK
rx_buf_stop, OFB9Eh ;1200 bytes from end of buffer
qp buf start, OOOOh
dx, 1
;next page
qp_buf-paqe, dK
gp_buf-paqe,
CX, 1
ex, 1
qp_offset_adjust, CK
gp_buf_offset, cx
dx, 1
dx, 1
ax,
dx, a
ex, 12
dx, cl

mav
shl
mav

rx_huf_segment,dx,

jmp

buffers_set

copacetic:

mov
add

qp_buf_start, ax
ax, 258h

;A1-A16 of gp buffer, gp buffer is first
;1200 ~ytes for qp buffer at front of buffer space
;rx buffer starts 1200 bytes in

mav

rx_buf_start, ax

mav

rx_buf_head, ax

shl
sub
mov
mov

rK_buf_head, 1
qp_lenqth, 258h
cx, qp_ienqth
rK_buf_lenqth, CK
292062-49

1-383

intJ

AP-327

NetWare Driver Source Code Listing (Continued)
;convert segment to byte address

shl

dx, 1

mov

rx_buf_page, dx

mov

gp_buf-page, dx

shl
adc

ax, 1
dx, 0

mev

ex, 12

shl
mav
maV
Bub

dx, el
;load variable for transfers to IPX
rx_buf_segment, dx
ex, rx_huf_length
ex, 258h
:setup marker for low rx buffer space, >6UO words

shl
add
mev

ex, 1
ax, ex
rx_buf_stop, ax

:convert offset to byte address
;adjust segment for shift

buffers_set:
ret

Set Interrupt Vector
Set the interrupt vector to the interrupt procedure's address
save the old vector for the unhook procedure
assumes: bx has the ISR offset
al has the IRQ level
interrupts are disabled

Set InterruptVeetor
PROC
NEAR
;mask on the appropriate interrupt mask
push

ax

xchg
and
.hl

ax, ex
ex, 07h
dl, 1
dl, cl

mqv

int_mask, dl

not
mov

dl

mov

mev
mov
in
or
hlow
out
pop

;get the appropriate bit location
;set the interrupt bit variable

;set the interrupt mask variable
ax, InterruptMaskPort
int_mask_reqister, ax
aI, InterruJ?tMaskPort
aI, int_mask
InterruptMaskPort, a1
ax

eld
cbw

xor
ex, ex
moves, ex
add

aI, 68h
oint 4

;addinq 8 converts int number to int type, i.e.,
B

type 12, int 5 - type 13 etc.
292062-50

1-384

inter

Ap·327

NetWare Driver Source Code Listing (Continued)
shl
shl
xchg
mav
mav
mav
mov
mov
xchg

ax,
;tWD shifts ~ mul by 4 to create offset of vector
ax,
ax, di
int_vector_addr, di
;save this address for unhook
ax, es: [diJ
;save old interrupt veetor
word ptr old_ir~vector, ax
ax, es: [dil + 2
word ptr ~ld_ir~vector + 2, ax
ax, bx
;bx has the I5R offset

stosw
mav

ax, cs

stosw

ret
5etInterruptVector

endp

Driver Unhook
Assumes
DS = C5 = IPX segment
Interrupts are DI5ABLED
Assumes any registers but D5, 55, 5P may be destroyed
This procedure restores the original interrupt vector
This procedure will never be called if DriverInitialize
did not complete successfully.

DriverUnhook
PROC
NEAR
in
aI, InterruptMaskPort
or
aI, int_mask
"slow
out

InterruptMaskPort, al

xor

ax, ax

mov
mov
mov
mov
mov
mov
ret

es,
bx,
ax,
es:
ax,

;es is set to vector table segment
ax
word ptr int_vector_addr
word ptr old_ir'Lvector
[bxl, ax
;restore old interrupt offset
word ptr old_irq_vector + i
es: [bx + 2l, ax
; restore old interrupt segment

DriverUnhook

mombo_init
end

endp

ends

292062-51

1·385

APPLICATION
NOTE

AP-331

August 1989

U,sing the Intel 82592
to Implement a
Nonbuffered Master Adapter
for ISA Systems

JOSEPH DRAGONY
APPLICATIONS ENGINEER

Order Number: 292066-001
1-386

intJ

AP-331

1.0 INTRODUCTION

1.1 Objective

The modern office has become increasingly computerized due to the availability of reasonably priced, yet
very powerful, microcomputers. One of the rapidly
growing uses of these powerful computers is desktop
publishing. This technology allows text and graphics
output to be generated that rivals the quality of work
that could only be produced by very expensive phototypesetting equipment a few years ago. Another major
application is Computer Aided Design (CAD). One
thing that both of these applications have in common is
that the output devices they require are still relatively
expensive. Networking has enabled sharing these expensive peripherals, such as sophisticated laser printers,
plotters, and FAX equipment, that would not be practical if attached to a single user machine. Since these
peripherals are seldom in constant use by a single user,
sharing them throughout an office over a LAN allows
much better utilization of each unit. Through print
spooling, the sharing of the equipment is transparent to
the user except for the short walk to the print station to
retrieve any spooled jobs. The cost reduction aspects of
networking are beginning to be reflected in the network
hardware itself. Media 'cost has been reduced, first from
Ethernet to Cheapernet. Now the move to Twisted Pair
Ethernet (TPE) lowers medium costs even further. The
increased market for LAN adapters is also driving cost
reduction in the adapter market. The 82592 Nonbuffered Master (NBM) is a simple, cost effective integrated LAN adapter for Industry Standard Architecture
(ISA) workstations which addresses this need for cost
reduction, coupled with high performance.

The objective of this Application Note is to present the
NBM592 architecture using the 82592. The implementation that will be described here uses readily available
off-the-shelf devices. This low level of integration is
presented as a starting point. Gate array or other ASIC
technology could be used to reduce the parts count of
this architecture while lowering cost and possibly increasing performance. The software aspects of this solution will also be discussed. A NetWare* shell driver is
the vehicle for illustrating the programming of the
NBM.

The NBM592 takes advantage of the increased bandwidth capabilities of the bus and memory subsystems in
current ISA computers, commonly known as "AT"
type computers. It is based on the Intel 82592 Advanced CSMA/CD LAN Controller. The NBM592 has
its own DMA, which consists of an 82C37 A DMA controller and support logic implemented in PALs and
TTL. Part of this logic implements the master handshake which allows the NBM592 to take control of the
host bus. This DMA is used to transfer data from the
network directly into' the host memory subsystem. The
NBM contains no local buffer memory. This allows the
cost of local buffer memory to be trimmed from the
cost of the adapter. The low cost and very high performance of this adapter architecture make it uniquely
suited to todays market.
Because the NBM592 is derived from the Embedded
LAN Module (ELM) the reader might find the following Application Notes helpful. AP-320 Using the Intel
82592 to Integrate a Low-Cost Ethernet Solution into a
PC Motherboard, and AP-327 Two Software Packages
for the 82592 Embedded LAN Module. These publications are available from the Intel Literature Department.

1.2 Acknowledgements
I acknowledge and thank Dan Gavish of the Intel Israel System Validation group, David Bar-On of Moran
Systems, Haifa, Israel, and Yosi Mazor of Intel MCFG
LAN Marketing for their efforts in the definition, development, and debugging of the hardware. I also
thank Ben L. Gee of San Jose, California for his work
in modifying the Embedded LAN Module driver to run
on the NBM592 hardware.

2.0 HARDWARE OVERVIEW
The NBM592 is an extension of the ELM architecture.
The NBM592 differs from the ELM in the fact that it
contains its own DMA resources. The NBM592 also
contains logic to implement the ISA bus master handshake, which allows the NBM592 to operate as a master adapter on the ISA bus. This allows the adapter to
transfer data from the network directly into host memory at higher speeds than the system DMA channels
are capable of.
The NBM592 was specifically designed' to work in 6and 8-MHz IBM PC AT machines. Although the
NBM592 has been tested successfully in a variety of
other machines, a thorough worst-case timing analysis
would be required to ensure proper functioning in clone
machines using integrated chipsets. To implement the
master handshake logic in a gate array or other ASIC,
this analysis would need to be done for all of the current motherboard chip sets to ensure clone compatibi1~
ity.
Figure 1 contains a block diagram of the NBM592 circuitry. The circuitry in the shaded area marked DMA
logic and the TCI address latches from the area marked
CSMA/CD logic would be good candidates for integration into gate array or other dense ASIC logic. The cost
reduction benefits would depend.on the level of integration ..

'NetWare is a registered trademark of Novell Incorporated.

1-387

l
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292066-1

inter

AP-331

2.1 DMA Functional Block

2.4 System Bus Interface

The DMA functional block is comprised of an 8-MHz
82C37A DMA controller, page registers for the upper
addresses in DMA cycles, a receive ring buffer overflow
prevention circuit (stop register), a watchdog timer that
limits NBM592 DMA bursts to less than 15 us, and a
wait state generator for DMA cycles. Also contained in
this block are two latches that store the address of the
last memory location containing receive data.

The system interface for the NBM592 is I/O mapped.
It uses 16 bytes of read/write I/O space. The 82592
command and status registers, 82C37A registers, page
registers, and stop register are all accessible in this
l6-byte address space. The IA ROM contents can also
be read in this window.

3.0 DMA OPERATION
2.2 CSMA/CD Functional Block

3.1 Better System Bus Utilization

The CSMAlCD functional block is implemented by
the 82592 Advanced CSMA/CD LAN Controller. This
device supports all industry standard CSMA/CD
LANs, such as IEEE lOBASE5, lOBASE2,
lOBROAD36, 10BASE-T, and IBASE5. The 82592
also supports proprietary CSMA LANs from 1 to 20
Mb/S such as the IBM PC Network. The 82592 also
implements the CSMA/DCR protocol that provides
deterministic collision resolution on CSMA LANs.
This feature can be used when the worst case time for
accessing the medium must be known.
The 82592 also implements a Tightly Coupled Interface
(TCI) to industry standard DMA controllers that allows back-to-back frame reception and retransmission
on collision to be done without CPU intervention.
When the 82592 is configured to TCI mode it generates
four additional DMA requests after the last byte of the
frame has been transferred to memory. The first two of
these transfers are used to 'move the status for the current reception into memory. The second two transfers
write the number of bytes transferred into memory. By
using this byte count value it is possible to reconstruct
the chain of packets in memory so they can be handed
off to the 'higher layers of the software. This will be
discussed more fully in the software section of the Application Note.

The NBM592 operates as a DMA master on the I/O
channel of the host computer. This means that all address and control signals are generated by the NBM592
while it is actively transferring data. The NBM592
DMA block is based on the 8-MHz 82C37A DMA
controller. By providing its own DMA the NBM592 is
able to transfer data between the network and memory
at a higher rate than the system DMA channels would
allow. Two of the four available channels of the on
board 82C37A are used by the NBM592. In the default
configuration Channel 0 is used as the transmit channel
and Channel 1 the receive channel. Channels 2 and 3
are not used. The transmit and receive channels may be
exchanged by using jumpers. The 82C3 7A provides address lines A 16 through A 1. Address lines SA 16-SA9
on the ISA bus are latched from the multiplexed address/data bus of the 82C37A by ADSTB. Address
lines SA8-SAl are driven by the A7-AO outputs of the
82C37A through a transceiver. AO is pulled low during
DMA transfers because all transfers are word aligned.
The upper address bits are provided by the page registers, which are programmed during initialization. IClO
is the page register used for the Transmit channel, and
ICII is the page register used for the Receive channel.
This architecture allows DMA transfers across a
128-kB memory space for both transmit and receive.

2.3 Analog Interface

3.2 System Bus Arbitration

The analog interface for the NBM592 consists of a separate daughterboard that attaches to the NBM592
through an SBX connector. By using this approach it is
possible to support IEEE lOBASE5, lOBASE2,
lOBase-T, lBASE5, and other proprietary network
standards by simply removing one daughterboard from
the digital assembly and installing a different analog
interface. There are currently three analog interface
modules, an Ethernet module, a Cheapernet module,
and a Twisted Pair Ethernet (TPE) module, which is
based on the Intel 82521 Serial Supercomponent.

When the 82592 needs to perform DMA cycles it asserts its request to the on-board 82C37A. The 82C37A
then asserts its HRQ pin. This pin is connected to the
DRQ6 line in the I/O channel. When DACK6 is returned the NBM592 drives the MASTER line in the
I/O channel low, waits one clock and then drives the
address bus. One clock later the NBM592 drives the
control lines. The NBM592 may then perform DMA
cycles for' up to 15 /J-s. This time limitation exists to
ensure that the system can access the bus to perform
refresh cycles.

1-389

inter

AP-331

If a collision occurs during transmit, the NBM592 must
be able to reinitialize the DMA controller to point back
to the beginning of the transmit buffer. This reinitialization must be done without CPU intervention to be
ready to retransmit the frame within the 9.6 ,""S Interframe Spacing (IFS) time. The NBM592 does this by
performing the TCI handshake with the 82592 to determine when a collision has occurred. The EOP pin on
the 82C37A is then activated by the TCI logic. Since
the 82C37A has been programmed to autoinitialize
mode it resets its address to the beginning of the transmit buffer. After the IFS time and the random backoff
time, if any, the 82592 will begin to make DMA requests and the frame will be retransmitted.

by the CPU. This prevents corruption of the receive
buffer structure during extremely heavy network traffic
conditions. The stop register can be tested on power up ,
by reading the overflow bit. The lower five bits of the
stop register are used to select the IA PROM address.
The OVERFLOW line is pulled up to Vcc' to allow
removing the overflow ,comparator and register IC8
and IC9 for ,a lower cost version of the board. If the
stop register circuitry is removed it would be advisable
to use the linear restartable buffering approach that was
used in the ELM driver. In this approach, as frames are
received, the driver software checks to see how much of
the ,receive buffer remains available. When most of the
buffer has been consumed the software reinitializes the
DMA controller to point back to the beginning of the
buffer space, and reception can resume. '

3.4 Receive DMA Channel

3.5 Wait State Generator

The receive DMA channel in the NBM592 uses a ring
buffer. This is done by programming channel 1 of the
82C37A to autoinitialize mode. When the DMA channel reaches the end of the receive buffer space, it autoinitializes to the beginning of the receive buffer space
and continues reception there. This approach ensureS
that the maximum possible buffering capacity is always
available to the adapter., The integrity: of the receive
buffer is protected by a stop register, which is discussed
in detail in section 3.4.1. A pair of latches is used to
store the last address in memory that contains receive
data. These latches are triggered by the TCI handshake
at the completion of a receive operation. At that instant
the latches are clocked and the address on the A16-Al
lines are latched. When the NBM592 receives a packet
it appends four words of information. The upper bytes
of these four words are not used. The lower bYtes contain the status of the reception and the byte count of the
frame. The byte count, along with the value from the
TCI latches, is used to recover the received frame chain
from the receive buffer. This process is discussed in
section 7.3.1.

The DMA circuitry also contains an optional wait state
generator. Zero to three DMA wait states can be selected by a jumper that controls the wait state generator
(IC23). Timing calculations show that one wait state is
needed for a 6 MHz AT, and that no wait states are
needed for an 8-MHz AT. The basic DMA transfer
~e is 3 clocks, two clocks for the command (RD or
WR) and one clock for address setup time. Wait states
extend the command. The address setup time can be
extended to two clocks by programming the 82C37A to
normal write cycle. In this case a wait state should be
added.

3.4.1 Stop Register

4.1 Transmit EOP

The Stop register (IC9) holds the stop address for the
receive ring buffer. This implementation uses a
256-byte resolution. A finer resolution would require
additional components. The CPU loads it with a new
value as each receive buffer is processed. The value
in the stop register is compared by IC8 to the corresponding address lines during DMA receive cycles
(DMA_MW). When the contents of the latch and the
address bus contain the same value, the OVERFLOW
signal is activated. The OVERFLOW signal is latched
by PAL 4, and the interrupt line is asserted. The
OVERFLOW bit can be read by the CPU by an I/O
read at offset OEh from the base address of the adapter.
The bit appears on the DO' data line. When
OVERFLOW is active, the Receive channel of the
DMA is 1W. BADTX is EOP • DRQ delayed by one
pal. DMA_MW is not delayed by the PALs; thus timing requirements are met and DISDACK is generated
properly.

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4.2 Separate Receive and Transmit
Page Registers

4.6 DRAM Precharge Time

An address setup time of 120 ns is required before asserting the command (Read or Write). This is done by
adding a I-clock delay to the first command in each
burst, and asserting an additional wait state to this first
command. The signal EN_CMD is generated by
PAL3. EN_CMD is activated two clocks after
DACKO or DACKI, and remains active until the end
of the cycle. A wait state is added to this first command
by the qualification of the RD_O~WR signal by
EN_CMD. The EN_CMD controls the enable line of
the command bus buffer. This buffer drives SAO and
BHE, which are part of the address and must be active
before command. These lines are driven by the PALs.

4.3 Extra Wait State
The 82C37A lOW signal can be active after the end of
the 82C37A S4. This will cause an extra wait state to be
inserted. This can be eliminated by using the 82C37A
MEMW signal for the wait state generator instead of
the 82C37A lOW. This line will always go inactive before the end of S4. This prevents the insertion of extra
wait states.

4.4 TCI·Direction
When the TCI latch is read by the CPU the data buffer
direction line that is driven from the RD line is in the
wrong direction. This is because the DMA controller
clear mask register can be accessed by writing to the
same address. To prevent this the RD line has been
disabled.
When addressing the DMA clear mask register the
37 CS is deactivated. This prevents access to this register: The local RD signal is driven by lORD during
slave cycles.

4.5 Bus Contention
Since the 82C37A specification does not guarantee that
the mid address (strobed by ADSTB) will float before
the command is active, contention can occur on these
lines. The solution is to delay the command (Read or
Write) until after each ADSTB cycle. This is done by
generating EN_CMD, which disables the command
for one clock and adds one wait state in addition to
those added by the wait state generator. This is implemented in PAL3.
The high data buffer is enabled by EN~DDR, which
is active only during master cycles. This prevents the
NBM592 from enabling the high data buffer (SDI5SD8) during slave accesses to odd I/O addresses. If this
was not done, contention with low data multiplexed
into the high data by the motherboard would occur.

There is a problem with the worst case timing of the
82C37A when more than one transfer cycle is executed.
The problem is that the worst case time between two
commands can be lower than the precharge time required by the DRAMs. If extreme values are taken for
two delay parameters, (maximum value for inactive
time and minimum value for active time) the DRAM
precharge time will be violated. We assume that for the
same signal the difference between those two parameters does not exceed 30 ns. This satisfies the precharge
time for the DRAM chips. The required precharge time
is 100 ns. For the address setup time, the assumption is
that command is activated after the address is stable
(i.e., the address setup time is greater than zero). The
address path to the memory chips consists of the delay
through the 74LS245 transceiver on the NBM plus the
delay of the 74FI58 in the host system. The total delay
is 19 ns. The command path to RAS consists of one
74LS244 on the NBM plus a 74FIO and a 74FOO in the
host'system. This path totals 9 ns. The required setup
time specified for the DRAM chips is 0 ns. Therefore, a
10 ns setup time from the 82C37A will satisfy the required setup time. The same analysis holds for read and
write cycles.
The 82C37A worst case timing does not guarantee that
the Read command signal will stay active after the
Write command is deactivated. For proper board operation the Read must stay active after the deactivation of
the Write signal.

5.0 DATA PATH
The data path includes the 82592, the interface to the
analog circuit, the 16-bit address latch for the TCI address (IC2 and 4), the 16-bit data transceiver for buffering data (IC3 and 5), and the IA PROM which contains the station address (IC6). 82592 connections and
signal names are the same as in the ELM. The low
address latch latches its data directly from the 82C37A
lines in order to minimize the loading on the bus. The
high address latch latches its data from the system's SA
lines.
'
The Station IA is read from the PROM, which is enabled by PROM_CS. To read the IA PROM, the
CPU first preJoads the stop register with the address of
the byte to be read. The CPU then reads from I/O
address 30Ah. In the current design the 82592, the
DMA, and all the other circuitry is clocked by the same
8-MHz clock. In future versions the 82592 can be
clocked by a 16-MHz clock. In this case, the 8-MHz
clock to the rest,ofthe board will be generated by dividing the 16-MHz clock by 2, in the unused flip-flop of
ICI5A. This requires jumper changes. There is an option of driving the 82592 clock from a 16 MHz clock.
The clock can be divided by 2 to produce the local
8-MHz Clk to the 82C37. The local oscillator could be
eliminated by using a IO-MHz 82C37A and using a

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Table 1. NBM592 I/O Map
Address

DMA
Register

300h

Write

Read

0

Base and Current
Address No. 0

Current Address No. 0

301h

8

Command Register

Status Register

302H

1

Base and Current
Word Count No. 0

Current Word Count No. 0

303h

9

Request Register

304h

2

Base and Current
Address No. 1

305h

A

Single Mask

306h

3

Base and Current
Word Count No. 1

307h

B

Mode Register

308h

4

592 PortO

Current Word Count No. 1

592 Port 0

309h

C

Byte Pointer FF

30Ah

5

Page Register 0 (Tx)

IAPROM

30Bh

D

Master Clear

Temporary Register

30Ch

6

Page Register 1 (Rx)

30Dh

E

LowTCI Byte
High TCI Byte

30Eh

7

Stop Register

30Fh

F

Write Mask Register

Overflow Flag

buffered version of the TxC signal generated by the
82C50lAD on the analog module to clock all NBM592
circuitry.

and SMEMWR are buffered by the system. The lORD
and IOWR signals are inputs and are buffered by the
PALs. AEN is an input to the decode PAL.

Provisions have been made for a boot EPROM (IC25).
This optional device is accessed during the system boot
process. The BIOS searches for a remote boot ROM,
and if one is found the ROM initialization code is executed. IC24 serves as its address decoder. EPROM size
and memory allocation are jumper selectable (see APPENDIX B for details). If a remote boot is not needed,
both IC24 and IC2S can be omitted.

The NBM592 can used IRQ 10, II, 12, 14, or IS.
IRQlO is the default interrupt request, driven by the
82592 interrupt signal OR'd with the overrun latch.
The interrupt line is jumper selectable. Jumper locations to select the various lines are given in the jumper
tables.

6.0 PC AT 1/0 CHANNEL INTERFACE
The board was designed to occupy no more than 16
I/O addresses; to meet this restriction, during slave
mode access to the 82C37A SAO is routed to A3 and
during DMA cycles A3 is routed to SA4.
The NBM592 uses a 16-bit DATA path. All signals in
the data path are buffered. SA lines are decoded directly by the PAL, and driven by the DMA through buffers. LA lines are driven by the latches. MEMRD and
MEMWR lines are driven by the DMA. SMEMRD

The master handshake requires the use of one host
DMA channel. In the NBM592 host DMA channels 5,
6, or 7 can be used. The channel is used in cascade
mode to allow the NBMS92 to master the host bus. The
default connectio~ is channel 6 with channels 5 or 7
available through jumper selection (see APPENDIX B
for details) .. The MASTER signal is activated by the
PALs when the board DMA is active.

6.1 Refresh Watchdog Timer .
There are two watchdogs on the NBM592. The watchdogs are driven from the local 8-MHz clock. Watchdog
No.1 is used to ensure that the refresh mechanism will
be able to gain control of the bus when it needs to.

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Refresh cycles occur approximately every 15 /Ls. When
a refresh request occurs the DMA must release the bus
within 15 /Ls. This 'is done by using a time constant of
12 /Ls in the watchdog. When a refresh request is sensed
the watchdog starts to run. The watchdog timer will
expire after approx. 12 /Ls. This corresponds to W5 •
W6 at 8-MHZ, the 3 extra /Ls will be spent transferring
bus control between the two DMAs. After the bus is
relinquished, the request is regenerated one clock after
DACK6 is inactivated. Analysis and lab inspection
show that while working with no wait-states, 82592
bursts do not exceed 12 /Ls. Therefore, this circuitry
may be removed from future versions of the board.

6.2 Floppy Disk Watchdog Timer
Watchdog No.2 i~ an optional floppy disk watchdog
(SPARE-I). The purpose of this watchdog is to avoid
the possibility of bus starvation to the floppy disk during DMA bursts by the NBM592. DRQ2 is used to
sense activity of the floppy drives. The watchdog drops
the 82592 request with a delay after a floppy DMA
request is encountered. This watchdog is disabled by a
jumper, as it is redundant. This is an optional feature
and is not used in the present implementation.
The + 12-V line in the ISA bus provides power to the
analog module.
The Reset line from the bus is used to reset the
NBM592 circuitry during system initialization.

7.0 SOFTWARE
The software discussion in this Application' Note is
based on a driver intended to be used with Novell
NetWare V2.1. The driver is based on the driver that
appears in AP-327, Two Software Packages for the
82592 Em.bedded LAN Module. There are two major
differences between the driver in AP-327 and the driver .
in this Application Note. First, this driver uses a ring
buffer approach, as opposed to the linear restartable
buffer used in the ELM. Secondly, this driver uses macros for conditional blocks to allow the code to be written in a manner resembling a high-level language. This
makes the code more readable for those with limited
assembly language experience.
While this driver 'is written to run with a specific networking package, it contains all the functions that
would normally be required by any networking package. Once a good understanding of the code is gained it
should be possible to modify most of the procedures to
operate under another networking package. The main
differences will be the format of the communicating
structures between the driver and the lowest layer of
the networking software. The procedures that will be
discussed in detail in this Application Note are DriverInitialize, DriverSendPacket, DriverlSR, and Driver-

Poll. These four procedures are the backbone of the
driver and represent the most important code for understanding the functionality of the NBM592. Procedures called from within the primary procedures will
also be covered.
The source code for the procedures discussed below is
included as APPENDIX E.

7.1 Initialization
In our software example, initialization is carried out by
the procedure Driverlnitialize. This procedure is called
by the networking software when it is loaded. This procedure initializes the hardware and any software variables that must be initialized at run time. The transmit
and receive buffer variables are initialized through a
call to SetUpBuffers. Driverinitialize also calls the procedure SetInterruptVector to initialize the proper entry
in the system interrupt vector table, after first saving
the vector that is already there.
7.1.1 Driverlnitialize

The first function that Driverinitialize performs is to
set the variable MaxPhysPacketSize to 1024. This value
is used to negotiate the maximum size of the frames
that will be transferred between the fileserver and the
workstation.
Next, the base I/O address is read from the configuration table and this value is added to the offset value for
each register in the NBM592 I/O space. This includes
the 82C37 A registers, the stop register, the TCI latches,
and the IA PROM address.
The CPU now reads the Master DMA channel number
from the configuration table and calculates the required
variables. This is the host DMA channel that will be
used to implement the master handshake between the
NBM592 and the host.
The next operation is to read the station address from
the address PROM. This is done by first writing the
address of the byte to be read to the Stop register and
then reading from the IA PROM port. The value written into the stop register is used to drive the address
inputs of the IA PROM. The code to read the PROM
is implemented as a loop, with the value written to the
latch staring at zero and incrementing through five to
read the six bytes of station address. These six bytes of
address are stored in the array node_addr and also are
written into a location in IPX's space. The location
IPX wants the address written to is passed in the DI
register when Driverlnitialize is called.
After the station address has been read and stored, Driverinitialize loads the AL register with the number of
the interrupt line that the NBM592 will use, loads the
BX register with the offset of the procedure DriverISR,

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and calls the procedure SetlnterruptVector. Details of
this routine are provided in section 7.1.2. After SetInterruptVector retu,rns, a call is made to the procedure
SetUpBuffers. SetUpBuffers initializes all the buffer
management variables. Details of this procedure appear
in section 7.1.3.
After SetUpBuffers returns, DriverInitialize is ready to
configure the DMA channels that the NBM592 will
use. One host DMA channel and two of the on-board
DMA channels will be configured. The host DMA
channel is configured to cascade mode. This allows the
onboard DMA to use this channel for arbitration in the
ISA bus. The onboard DMA controller is configured
for extended write, active low DREQ, and rotating priority. The transmit DMA channel in the onboard controller is programmed next. The channel is configured
to autoinitialize mode to allow retransmission on collision without CPU intervention. This channel wilf be
used to transfer the configuration and address parameters to the 82592.

Now that the 82592 is' initialized, the receive DMA
channel can be set up. This channel is also programmed
to autoinitialize mode and the word count is set to the
size of the receive buffer-I. This will cause the DMA
to wrap around to the beginning of the receive buffer
when it reaches the end. This results in a ring buffer.
The receive stop register is programmed with a value
near the end of the buffer. The receiver is enabled by
issuing a Receive Enable command to the 82592. The
AX register is zeroed to indicate that the initialization
completed successfully and control is returned to IPX-.
The, hardware is now ready for operation.
7_1.2 SetlnterruptVector

The' 82592 operates in the 8-bit-bus mode after reset. It
is put into the 16-bit-bus mode by giving it a Configure
command with zero in the byte count field. This is the
first command that the driver issues to the 82592. The
transmit channel is set up to point to the beginning of
the'transmit buffer area. The word count is set to I
because the'82C37A interprets this register as transfersto-be-made - 1. A Configure command is now given to
the 82592. DriverInitialize n9w enters a polling loop to
determine when the command has been completed. The
software can tell when the command is complete by
reading the 82592 StatusO register and testing to see if
the interrupt bit is set. This loop will be repeated a
maximum of 65,536 times. If, the command has not
completed by that time, a pointer to an error message is
moved into the AX register and control is returned to
IPX. At that point the error message will be displayed
and the loading of the driver will be aborted.
After the first Configure command has completed, another Configure must be done to actually load the desired parameters into the 82592. The transmit channel
is set up to point to the beginning ofthe transmit buffer
space and the word count is set to eight. This will allow
the nine required transfers to be made. The byte count
and configuration parameters are copied into the transmit buffer area and a Configure command is issued to
the 82592. Once again a polling loop is entered to wait
for command completion.
To set the station address the transmit channel is set up
to point to the beginning of the transmit buffer and the
word count is programmed to 3. The byte count and
station address are copied into the transmit buffer and
an IA Setup command is issued to the 82592. The
82592 is again polled for command completion.

The CPU reads the value of the interrupt line to be
used from the configuration table. It puts this value in
the AL register. The offset of the Interrupt Service
Routine (ISR) is placed in the BX register and SetlnterruptVector is called. This procedure calculates the
mask and unmask variables for the interrupt channel
that will be used for the driver. This channel is then
masked to prevent any unwanted interrupts. The CPU
now calculates the address in the interrupt vector table
where the vector will be stored. After saving the vector
that is already at the location to be used SetInterruptVector installs the interrupt vector for the NBM592.
The procedure ends in a return that passes control back
to Driver initialize.
The next initialization task is to set up the transmit and
receive buffer space to accommodate the architecture of
the NBM592 DMA subsystem. This is done by a call to
SetUpBuffers.
7.1.3 SetUpBuffers
The NBM592 DMA architecture is essentially the same
as the ISA DMA subsystem. It is made up of an
82C37A supplying AI6-Al and a page register supplying AI7-A23. AO is pulled low when DMA transfers
are being made because all transfers are done on word
boundaries. Because of the fact that no carry can be
generated from A 16 to A 17, the buffers must be located
such that no 128-kB boundary exists in them. If the
address of the 82C37A is allowed to roll over from
FFFFh to OOOOh the page register will remain unchanged. This will cause memory locations at the very
bottom of the 128-kB page to be overwritten. SetUpBuffers prevents the occurrence of this problem by
checking to see if a boundary exists in the buffer area
and then allocating the buffer space to the transmit and '
receive buffers accordingly. It is strongly recommended
that commercial implementations of the NBM concept
use counters instead of latches for the upper address
bits. This would eliminate the problems associated with
the page register implementation and would simplify
buffet setup and processing.

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The SetUpBuffers procedure in this Application Note is
an improved version of the procedure presented in AP327. Although the general approach is the same, several
changes have been made to accommodate the ring buffer implementation.

7.2 DriverSendPacket
Transmission on the network is accomplished by the
procedure DriverSendPacket. When the IPX wants to
send a packet to the fileserver or another station, it
prepares a Transmit ECB and calls DriverSendPacket.
The address of the ECB is passed in the ES:SI register
pair. The procedure checks to see if frames are already
queued for transmission. If frames are queued, DriverSendPacket adds the new ECB to the end of the queue
and returns control to IPX. If no frames are queued for
transmission, execution falls through to the procedure
StartSend.
7.2.1 StartSend

The procedure StartSend is responsible for actually
building the frame in the transmit buffer, setting up the
DMA controller, and issuing the Transmit command to
the 82592. This routine also calculates any padding
needed to bring the frame up to minimum Ethernet
length. '
The first action that StartSend takes is to set the transmitting flag in the driver workspace area of the ECB.
This flag is used to ensure that only valid transmit
ECBs are returned to IPX by the transmit ISR. If a
transmit request is cancelled and then the interrupt for
the cancelled transmit occurs, the code could erroneously return a packet that had never been transmitted.
Having this flag available prevents this.
If the IPX packet plus the Ethernet overhead bytes do
, not add up to a frame size of 64 bytes StartSend calculates the number of padding bytes required and stores
this value in memory for later use. After the padding
calculations have been done StartSend begins to build
the transmit frame in memory. The frame begins with
the 82592 byte count. This includes the IPX packet, the
Ethernet header and CRC bytes, and the chaining byte
at the end of the frame. In this application the chaining
byte will always be zero, since chaining is not supported.
The transmit ECB contains a fragment list which describes the length and location of each fragment in
memory that makes up the frame to be sent. This list ·is
processed by StartSend with the fragments being copied
in order into the transmit buffer. After the copy is complete any required pad bytes are moved into the end of
the buffer.

After the transmit frame has been built in memory the
DMA controller and page register are programmed
with the address of the beginning of the transmit buffer.
The word count for the frame is written to the DMA
controller and then it is unmasked. Writing a Transmit
command to the 82592 causes it to begin making DMA
. requests and transmission begins. The starting time of
the transmission is saved in memory and StartS end returns control to the calling code.

7.3 DriverlSR
DriverISR is the interrupt service procedure. It calls
the procedures RcvdPacket or SentPacket after it has
determined the source of the interrupt.
The first task in the Interrupt Service Routine (ISR) is
to save the machine state. This is done by pushing all
the registers on the stack as soon as the ISR is entered.
Once the machine state is saved the program is free to
use all of the processor's registers for its own purposes.
The segment registers are then set so they all point to
the same segment since the driver is implemented as a
.COM program. In this memory model code and data
share the same segment.
The ISR code next issues an End Of Interrupt (EOI) to
the two 8259A Programmable Interrupt Controllers
(PIC). This allows the PICs to accept interrupts from
other sources. Since the PICs are configured in the edge
triggered mode they can be cleared before the 82592
interrupt has been cleared. In a system that uses level
triggered interrupts, the interrupt from the 82592
would have to be cleared first. If this architecture were
migrated to the PS/2TM it would require the 82592 to
be acknowledged first because the PS/2 systems use
level triggered interrupts.
DriverlSR now checks to see what event caused the
interrupt. This is accomplished by comparing the status
read from the StatusO register of the 82592 to the event
codes for receive, transmit and retransmit. The value
read from StatusO is AND'd with ODFh prior to the
comparison to mask the state of the Exec bit. This simplifies the comparison step. If the event code is not
receive, transmit, or retransmit, the driver increments
an error counter called false_590_int and proceeds to
the exit code. If the event code is receive;, the procedure
RcvdPacket is called. If the event code'is transmit or
retransmit, the procedure SentPacket is called. Upon
return the driver proceeds through the exit code.

7.3.1 RcvdPacket
The driver's first action upon entering the RcvdPacket
procedure is to read the TCI address latches. These two
8-bit latches contain A 1-A 16 of the ending address of

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the last frame received. This address is used as the
starting point for the buffer reconstruction process. It is
saved in a variable called rx_buff_tail. The last four
words of the receive buffer contain status and length
information for the packet. By subtracting the length of
the current buffer from the current address read from
the TCI latches, the end of the previous frame can be
found. By repeating this process the complete chain of
unprocessed frames can be reconstructed. The status
bytes are used to determine whether the frame should
be processed or discarded. The procedure Normalize
Pointer is used to account for the possibility that the
packet is wrapped around in the receive ring buffer
while the status and length bytes are being read.
Each packet contains two length fields. One is contained in the IPX header and the other is contained in
the Ethernet header. The length of the packet is validated by doing several length checks. The length of the
Ethernet header' is subtracted from the total bytes received prior to doing the length checks. The first length
check determines if the packet exceeds the 1088 byte
maximum length for this driver (1024 data bytes and 64
NetWare bytes). The next length check determines if
the frame is shorter than the miniinum dictated by IPX
(30 bytes plus padding). The final check makes sure
that,the IPX length and the actual number of bytes
received agree. If any of these length checks fail, the
appropriate error counter is incremented and the frame
is discarded. If all the length checks pass, the packet is
added to a list of good received frames by putting a
pointer to the first byte of the frame into the array rlLlist and incrementing the variable num_of_frames.
Since the length of rx~ist is limited to 30 entries a
check is made to see if this is the last entry in rx_list.
This cycle is repeated, until all frames have been processed, or all entries in rlL-list have been used. When
one of these two events occur the driver enters a small
loop of code that takes care of handing the received
packets off to IPX.
The handoff loop is controlled by the variable nuIIL.
of_frames. Mter each frame is hamled off to IPX
num_oLJrames is decremented. When, num_of_
frames reaches zero there are no more frames to hand
off and the loop terminates. The list is processed by
reading the offset of the first byte of the frame from
rx_list. This offset is used to read the socket number
from the IPX header of the frame. The socket number
is used as a parameter for a call to the IPX routine
IPXGetECB. If there is an ECB available for that socket IPX passes a pointer back to the driver. If an ECB is
available the loop calls the procedure DeliverPacket,
which does the processing necessary to transfer a packet from the. driver to IPX. If no ECB is available, the
next frame is processed.

After all frames have been processed the stop register is
checked to see if a receive overflow occurred. If an
overflow occurred the variable rx_buff_overflow is
incremented. The stop register is then updated by writing the value of rx_buf_tail- 256 into it. The value of
receive buffer head is then updated by writing the value
of rlL-buf_tail + 2 into it. The variable rlL-buf_
head now points to the first byte of the next receive
buffer. Execution now returns to DriverISR.
7.3.2 SentPacket

The first action taken in the SentPacket procedure is to
test the software flag tx_active_flag. If this flag is not
set then a transmit had not been initiated and the trallsmit interrupt is erroneous. In this case, control simply
returns to DriverISR. If tx_active_flag is set the driver reads the status of the transmission from the 82592.
The driver tests the status to see if the transmission
completed successfully. If an error occurred the status
is tested to determine the type of failure, and the corresponding error counter is incremented. If the transmit
completed successfully, this code is skipped. Next the
driver extracts the total number of collisions the frame
experienced and adds this value to the variable RetryTxCount. The driver writes a completion code for
the transmission into the ECB, unlinks it from the
transmit queue, and returns it to IPX through a call to
IPXHoldEvent. The driver now checks the transmit
queue to see if any packets are awaiting transmission. If
there is a packet in the queue, the driver loads the ES:SI
register pair with the address of the ECB and calls
StartSend. If no packets are queued, control is returned
to DriverISR.
7_3.3 Exiting DriverlSR

After control is returned to DriverISR the driver
checks to make sure that the receiver is enabled. If it is
not, then a Receive Enable command is issued to the
82592. DriverISR then Issues an Interrupt Acknowledge to the 82592. This clears the interrupt that caused
entry into the DriverISR code and allows any new interrupt that may have occurred during processing to
move into the 82592 StatusO register. DriverISR reads
this register to determine if a new interrupt occurred. If
a new interrupt is detected then execution loops back to
the beginning of the ISR and the new interrupt is processed. If no new interrupt is detected a call is made to
IPXServiceEvents to tell IPX it has events to process,
the machine state is restored to its condition when DriverISR was entered, and an IRET instruction returns
control to the code that was executing when the interrupt occurred.

1-396

AP-331

7.4 DriverPoll
The procedure DriverPoll is called by IPX to allow the
driver to check for timed-out transmits and any other
non-interrupt-driven events that need to be handled.
DriverPoll first checks to see if tx_active_flag is set.
If it is not, then control is returned to IPX. If tx_active_flag is set, then the driver checks to see if the
current transmission has timed out. This is done by
reading IPXIntervalMarker, subtracting tlL-start_
time from the value read, and comparing the result
with TxTimeOutTicks. If the result of the subtraction is
greater than TxTimeOutTicks, the transmission is
aborted by issuing an Abort command to the 82592.

DriverPoll then writes a bad completion code into the
ECB for the packet, unlinks the ECB from the transmit
queue, and returns the ECB to IPX through a call to
IPXHold Event. The 82592 is then given a Selective
. Reset command to put it in a known state. All configuration parameters are maintained when a Selective Reset is done but the Receive, Execution, and FIFO machines are all put in a known state. A Receive Enable
command is given to the 82592 to reenablethe receiver.
DriverPoll then checks the transmit queue to see if any
packets are queued. If a packet is awaiting transmission, the ES:SI register is loaded with the address of the
ECB and StartSend is called. If no packets are waiting
control"is simply returned to IPX.

1-397

intJ

AP·331

APPENDIX A
SPECIAL CONSIDERATIONS
FOR A-1 STEPPING ANOMALIES
write arrives, or when the current'DMA burst ends
(this is identified by the DACK signal going inactive).
This function is implemented in ICI5B and PAL2.

There are a few anomalies in the operation of the A-I
stepping of the 82592 that require workarounds in the
NBM592. They are discussed below.

ReceiveEOP
When bad frames are received, the 82592 signals this to
the hardware by not dropping the DREQ signal during
EOP. This can cause the 82C37A to issue another·
DMA cycle. This extra cycle can corrupt the receive
buffer chain. The NBM592 contains an Extra DMA
Read Elimination circuit to prevent this extra read cycle. The DREQ signal is disabled during the time that
the EOP is active. The DREQI # signal to the 82C37A
is qualified by the EOP signal to eliminate another cycle. The EOP goes active after the activation of the
RD# pin, this deactivates DREQI#, thus the DMA
will not issue another transfer. The EOP signal to the
DMA controller is blocked during receive cycles. This
is done because the receive channel is reinitialized when
the upper limit of the receive buffer is reached, not at
the end of each receive.
NOTE:
The NBM592 does not discard bad received frames.

Transmit EOP
The NBM592 also contains an Extra DMA Write
Elimination circuit for the Transmit channel. In some
case, when EOP and DREQ are driven active, the,
82C37A can execute an extra write cycle. This redundant cycle can be wrongly interpreted by the 82592.
The NBM592 contains a circuit that eliminates this extra cycle, if it occurs. To disable the extra write, a signal
DISDACK # is generated. This signal, when active,
disables the DACK to the 82592, causing the 82592 to
ignore the write cycle. This signal is activated whim at
the rising edge of the 82592 WR # signal (at DMA
cycles), a bad Transmit event is identified. A BAD_
TX # signal is generated when the DRQ signal is active
during the occurrence of the 82592 EOP #. The DISDACK # signal is deactivated when either the next

In many cases the extra write cycle does not occur. The
DISDACK signal, in this case, would cause the elimination of the next write cycle. This write cycle would be
the first cycle of the next frame, which would cause
undefined data to be sent instead of the next frame.
This problem was remedied by canceling the DISDACK signal at the end of the current burst. This is
done by connecting the preset signal of the DISDACK
flip-flop to the DMA controller's DACKO signal. Thus
if the extra write occurs, it is eliminated.

Transmit Error EOP
When a collision occurs after all the transmit data has
been transferred to the FIFO, the 82592 does not issue
the bad transmit EOP. This will cause the DMA controller to continue with the retransmit cycle from the
current address, instead of autoinitializing to the beginning of the transmit buffer. One solution to this problem is to program the 82C37A count register to the
actual transmit count. This will cause the 82C37A to
autoinitialize. This solution can cause a problem with
good transfers. The 82592, when tJ.'ansmitting in TCI
mode, can transmit a chain of frames. After the end of
a good transmit the 82592 issues another DMA cycle to
read the next memory location in the transmit buffer. If
the first three bits of that location are binary 100, then
the 82592 attempts to transmit another frame. With the
proposed solution to errata No.1, the 82592 will read
the chained command from the byte-count field of the
Transmit buffer. To prevent" an extra frame transmission, the NBM592 uses the 82592 EOP signal, which is
active during the' chain command read, to force the DO
line high. This is done by generating a KIL_DATA#
signal which disables the bidirectional data buffers. A
pull-up resistor on the local DO forces this line to 'I',
thus ensuring that the value read by the 82592 will not
be binary 100.

1-398

inter

AP-331

APPENDIX B
JUMPERS
Jumpers are provided to allow selection of interrupt line used, DMA wait states, and the host DMA channel used for
the master handshake. The tables below show how to set the jumpers in each jumper block as required for your
configuration.

INTERRUPT JPl
IRQI0 (default)
IRQ12
IRQ13
IRQ14

pins
pins
pins
pins

1-6
3-8
4-9
5-10

HOST DMA CHANNEL JP2
pins 1-7 and 2-8
DRQ5
DRQ6 (default)
pins 3-9 and 4-10
pins 5-11 and 6-12
DRQ7
EPROM SIZE JP3
8 kB
16 kB
32 kB

pin
pin
pin
pin
pin
pin

1-7
2-8
1-7
2-8
1-7
2-8

not connected
not connected
connected
not connected
connected
connected

EPROM ADDRESS JP4
Address
C8000
CAOOO
CCOOO
CEOOO
DOOOO
D2000
D4000
D6000
D8000
DAOOO
DCOOO
DEOOO
EOOOO

A19
1-8
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

A18
2-9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

Jumpers
A17
A16
3-10
4-11
C
C
C
C
C
C
C
C
C
NC
C
NC
C
NC
C
NC
NC
C
NC
C
NC
C
C
NC
NC
C

A15
5-12
NC
NC
NC
NC
C
C
C
C
NC
NC
NC
NC
C

A14
6-13
C*
C*
NC*
NC*
C*
C*
NC*
NC*
C*
C*
NC*
NC*
C*

A13
7-14
C**
NC**
C**
NC**
C**
NC**
C**
NC**
C**
NC**
C**
NC**
C**

• When using a 32 kB EPROM this jumper is not used for address selection. Pin 13 should be connected to JP6.

*. When using a 16 kB or 32 kB EPROM this jumper is not used for address selection. Pin 14 should be connected
to JP5.

I/O ADDRESS SELECT JPI0
300h-30Fh
pins 1-2 connected
310h-31Fh
pins 1-2 not connected
WAIT STATES JP11
o WS
1 WS (use for 6 MHz AT)
2 WS
3 WS

pins
pins
pins
pins

1-5
2-6
3-7
4-8
1-399

inter

AP-331

APPENDIX C
PAL EQUATIONS
PAL 1
PALl
module PALl flag '-R3'
title 'NBMS92 - PAll X023'
IC18 device 'P20LIO' ;
SAO

pin 1; tlin

SAl

pin 2;

SA2

pin 3; "in

SA3

pin 4; lIin

lORD_BAR

pinS; ttin

IOWR_BAR

pin 6; "in

LIMIT_LATCH_BAR

pin 7; !lin

BOARD_CS_BAR

pin 8; , "in

EN_ADDR_BAR

pin 9; ''in

EPROM_CS_BAR

pin 10; ''in

NCl

pin 11; "not used

NC2

pin 13; "not used

LD_RX_BAR

pin 14; "out

LD_TX_BAR

pin 15; "out

LD_LIMIT_BAR

pin 16; "out

OE1_BAR

pin 17; "out

OE2_BAR

pin 18; "out

i592CSO_BAR

pin 19; "out

i37CS_BAR

pin 20; "out

PROM_CS_BAR

pin21; "out

DO

pin22; "out

RD_BAR

pin23; "out

"in

H,L,x=l,O,.X.;
292066-2

1-400

AP-331

Equations

!LD_TX_BAR= !BOARD_CS_BAR & SA3 & !SA2 & SAl & !SAO & !lOWR_BARi "0AH
!LD_RX_BAR = !BOARD_CS_BAR & SA3 & SA2 & !SAl & !SAO & !I0WR_BAR; "QCH
!LD_LIMIT_BAR = IBOARD_CS_BAR & SA3 & SA2 & SAl & !SAO & !lOWR_BAR; "OEH
!.OECBAR =!BOARD_CS_BAR & SA3 & SA2 & ISAl & ISAO & !lORD_BARi "OCH
!OE2_BAR = !BOARD_CS_BAR & SA3 & SA2 & !SAl & SAO & !IORD_BAR; "ODH
li592CSO_BAR = !BOARD_CS_BAR & SA3 & !SA2 & !SAl & !SAO & EPROM_CS_BAR; "OSH
!i37CS_BAR = !BOARD_CS_BAR & EPROM_CS_BAR &( (!SA3) # (SAO & SAl) # (lSA2 & SAO»;
enable DO =IBOARD_CS_BAR & SA3 & SA2 & SAl' & !SAO & !lORD_BAR; "0EH
!DO = LIMIT_LATCH_BAR;
!PROM_CS_BAR = !BOARD_CS_BAR & SA3 & !SA2 & SAl & !SAO & nORD_BAR; "0AH
enable'RD_BAR = EN_ADDR_BAR;
!RD_BAR =!lORD_BAR # !EPROM_CS_BAR;
end PAll
292066-3

1-401

AP-331

PAL2
module PAL2 flag '-R3'
title 'NBi592 -pal2 REV X024'
IC19 device 'P20LlO' ;
RD_BAR

pin 1; "in

NCI

pin 2; "in (spare)

i592EOP_BAR

pin3; "in

i592DREQO

pin 4; "in

i592DREQl

pin 5; "in

DAKO_BAR

pin6; "in·

DAKl_BAR

pin 7; "in

RESET

pin 8; "in

WATCHDOG_BAR

pin9; "in

DISDACK_BAR

pin 10; "in

i592DRQODD

pin 11; "in

LIMIT_LATCH_BAR

pin 13; "in

LTCW

pin 14; "out

DREQO_BAR

pin 15; "out

DREQl_BAR

pin 16; "out

i592DACK_BAR

pin 17; "out

MSEOP_BAR

pin 18; "out

KILL_DATA_BAR

pin 19; "out

DAKO

pin 20; "out

WD_TICBAR

pin 21; "out (for internal use)

WD_RX_BAR

pin 22; "out (for internal use)

BADTX_BAR

pin 23; "out
292066-4

1-402

AP-331

Equations
DAKO = !DAKO_BAR;
LTCW = !RD_BAR & !i592EOP_BAR & lDAK1_BAR;
!WD_TX_BAR = i592DREQO & !DAKO_BAR & IWATCHDOG_BAR & !RESET # !WD_TX_BAR
& !WATCHDOG_BAR & !RESET;"Arm when DACK active"
IWD_RX_BAR = i592DREQl & IDAK1_BAR & !WATCHDOG_BAR & !RESET # !WD_RX_BAR
& !WATCHDOG_BAR & lRESETi"Arm when DACK active"
!DREQ1_BAR = i592DREQl & DAK1_BAR & WD_RX_BAR & LIMIT_LATCH_BAR #
i592DREQl & i592EOP_BAR & WD_RX_BAR & LIMIT_LATCH_BAR;
!DREQO_BAR = i592DREQO & i592DRQODD & !RESET & WD_TX_BAR # lDREQO_BAR &
DAKO_BAR & !RESET & WD_TX_BAR; " KEEP TIL DACK
li592DACK_BAR = !DAK1_BAR# lDAKO_BAR & DISDACK_BARi
enable MSEOP_BAR =!i592EOP_BAR & !DAKO_BAR;
MSEOP_BAR = 0; "EOP TX UNIT
IBADTX_BAR = !i592EOP_BAR & i592DREQO; "DREQ active at EOP
!KILL_DATA_BAR = !DAKO_BAR & 1i592EOP_BAR;
endPAL2
292066-5

1-403

intJ

Ap·331

PAL 3
module PAL3 flag '-R3'
title 'NBiS92 - PAL3 REV X024'
IC20 device 'P20LIO' ;
DMA_MW_BAR

pin 1; "in

CIS_BAR

pin 2; "in·

IOWR_BAR

pin 3; "in

DACK6_BAR

pin 4; "in

DASTB

pinS; "in

DDASTB

pin 6; "in

FLOPPY

pin 7; "in

RESET

pin 8; "in

WS

pin9;"in

W6

pin 10; "in

DHALDA_BAR

pin 11; "in

NO

pin 13; "in (spare)

MASTER_BAR

pin 14; "out

WR_BAR

pin 15; "out

EN_CMD_BAR

pin 16; "out

NC3

pin 17; "I/O (spare)

LPBK_BAR

pin 18; "out

WATCHDOG_BAR

pin 19; "out

QRD_OR_WR

pin 20; "out

SAO

pin 21; "I/O

EN_ADDR_BAR

pin 22; "out

A3

pin 23; "out

H,L,x=l,O,.x.;
292066-6

1-404

AP-331

Equations

enable SAO = !EN_ADDR_BAR;
SAO =0;
enable WR_BAR = EN_ADDR_BAR;
WR_BAR = IOWR_BAR;
enable MASTER_BAR = IDACK6_BAR;
MASTER_BAR = 0;
!WATCHDOG_BAR =FLOPPY & !RESET
"ARM by FLOPPY WATCHIX>G

# W5 & W6 & !RESET
"ARM by 15 ~ WATCHDOG

#!WATCHDOG_BAR & IDACK6_BAR & !RESET; "DROP after release
QRD_OR_WR = (IDMA_MW_BAR # !WR_BAR) & IEN_CMD_BARi
IEN_ADDR_BAR = !DACK6_BAR & !DHALDA_BARi
!EN_CMD_BAR = !DASTB & IDDASTB & !DACK6_BAR;
enable A3 = EN_ADDR_BAR;
A3=SAOi
LPBK_BAR = !CTS_BAR;
endPAL3
292066-7

1-405

intJ

AP-331

PAL 4
modulePAU
title 'MBN592 - PAU REV X023'
IC21 device 'P20LIO' ;
AEN

pin 1; "in

SA9

pin 2;

SA8

pin 3; "in

SA7

pin 4; "in

SA6

pin 5; "in

SAS

pin 6; "in

SA4

pin 7; "in

RESET

pin 8; "in

RANGE

pin 9; ·"in

EPROM_CS_BAR

pin 10; "in

OVERFLOW_BAR

pin l1i "in

i592INT

pin 13; "in

EN_DATA_BAR

pin 14; "out

IRQ10

pin 15; "out

BOARD_CS_BAR

pin 16; "out

EN_CMD_BAR

pin 17; "in

KILL_DATA_BAR

pin 18; "in

HLDA37

pin 19; "out

LD_LIMIT_BAR

pin 20; "in

EN_ADDR_BAR

pin 21; "in

LIMIT_LATCH~BAR

pin 22;. "out

BHE_BAR

pin 23;

"in

H,L,X=1,0,.X.;
QADD=[X,x,SA9,SA8,SA7,SA6,SA5,SA4];
292066-8

1-406

intJ

Ap·331

Equations

enable EN_CMD_BAR = Oi
enable LD_LIMIT_BAR = Oi
enable EN_ADDR_BAR = Oi
enable KILL_DATA_BAR= Oi
lBOARD_CS_BAR = (!AEN & SA9 & SAS & !SA7 & !SA6 & !SAS & EN_ADDR_BAR &: ISA4 &
!RANGE) # ( !AEN & SA9 & SAS & !SA7 & !SA6 & !SAS & EN_ADDR_BAR & SA4 & RANGE }i
!LIMIT_LATCH_BAR = ( IOVERFLOW_BAR # !LIMIT_LATCH_BAR & LD_LIMIT_BAR ) &
IRESETi
!EN_DATA_BAR

=

!EN_ADDR_BAR

&

!EN_CMD_BAR

&

KILL_DATA_BAR

!BOARD_CS_BAR# !EPROM_CS_BARi
HLDA37 = !EN_ADDR_BARi
enable BHE_BAR =!EN_ADDR_BARi
BHE_BAR=Oi
IRQ10 = iS92INT # !LIMIT_LATCH_BARi
endPAU
292066-9

1-407

#

l

+5V

SIP2 10K

1

z

0
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D'

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it

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JP4

~II

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a.

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13
14

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DI
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a.

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SA17
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SA14
SA13

SMEMRO.

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0
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m
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0
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II
9
10
11
12
13
14

2
4
8
II
11
13
111
17
3
II
7
II
12
14
,.
111
1

1
1
1
1
1
1
1

REFRESH WATCHDOG
1

10C
100
2A 20A
~ 2CLR20B

,g..

74LSII1I8
PO p-o~
PI
P2
P3
P4
PS
PII
P7
00
01
02
03
04
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111

iil

T

wo

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~
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ENT

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SA4
SAIl
SAil
SA7
SAil
SAil
SAID
SAil
SA12
SA13 1
SA14 2

10 I'D
9 AI
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7A3
8 A4

liAS
4
3
25
24
21
23
2

All
A7

01
02
03
04
05

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011
Q7

011

11
12
13
111
III
17
111
III

DO

01
02

D3
D4
OS
Oil
07

o

(0-7)

-

M
All
AID
Atl
A12

~A13

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II
3

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II

UIISP

SA2

a.

1101HZ

~
rti""

74LS1S3

EPROM ADD DEC

SAO
SAl

:::r

20C
200

4

+SV

272511

:E
!!l.
n

I

r-+

Ii"

U4

U18
IIMHZ
5920ACK.
OR02

74LS3113
lA
lOA

~ lCLR10B

4---l Vpp

.,....!
JP3

U211

EPROM
-

292066-11

l

~

~H:iii

1~

20L'QA

WATCHDOG_
DISDACK.

II
10

5112DIlClOOD "
LIMIT I.ATC~
'3
..

z

0
:I
0-

582DREQ1
I»J(Q.

5
II

DAlCl.
RESET
5112DREQO

7
II
4

5e2EOPlItO_

3
1

2

-..

~
1,0
11 1
112
l!!i
18
17

18
14
13

02
03

011
OS

oe

'4
22

LTCW
WD RXWD TX_
DREClO_
KILL DATA.
MSEOP.

2'
15
111
18

07'7
011 111
04 20
01

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SSl2DACK.
DRECI,.

DAl(O

23

BADTX-

11

12

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CD
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9

DPRQ

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CUi

CLK
13

II

011

'"

08

II

lSI

02

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1

U3B

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A3

15
18

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22

EN ADOR-

110 010 '4
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O4bo

_

WR_
LPBK_

10

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12

u"
l1liHZ

12

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we

OIIIIRD

t
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13
14

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74LS174
2D
4D

4
11

MASTER_
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RD...JILWR

7415184
A
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I

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4
5

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3
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W. S. GENERATOR

u;-s-

292066-12

cl
~1I~:Z3
20L1OA

7
II

-¥
S

lORD_
IOWR_
EPROM CS_

z

o:::l

C"
C

8
10
SAO
SA1
SA2

:::::
CD
ii!

SA3

+!
1
2
3
4

17
02
03
19
112 04
1:1
OS
lIS
08
110 07
111 08
11
09
12
010
13
1<4-

RD.

22
21
20
111
18
17
16
1S

DO
PROW CS.

37 CS.
SII2CSO.
OE:Z.
0E1.
lJ) LIMIT_

LD TX.
L.D RX.

14

Co

i!:
I»
en

.,iD

,
./>.

~

»
Co
I»

"C

.,iD
oo
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~

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PALl

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T
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a

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:
r

~

SA (0-1n

SA (0-191

RESET

AEN
EPROW CS.

OVERFLOW.
S921NT

~

~l

SA9
SAIl

SA7
SA8
SAS
SA4

20L1OA
06
12
02
2
3
13
03
1<44
04
S
1:1
OS
16
8
08
7
17
07
16
8
01
1
11
09
10 110 010
11 111
13 112
II
151

-

l>

l'
Co)
Co)

-"
16
22
21
20
19
18

17
23
1S
14

BOARD CS.
LIMIT LATCH_

EN AODR.
LD LIMIT_
HLDA37
KILL OAT".
EN CWD.
SHE_
IRQ10

-

EN DATA_

~

UII
PAL.

292066-13

l

+5V
~r-

.--

..Ii: !!'

82592
CSNA/CO
CONTROLLER

U13

z

28 RXC.
31 TXO
30 RXO

RXC.
TXO
RXO

0

-.
:::I

cr

C

CTS.
CRS.
COTTXC.

CD
CD

a.

33 CTS.
35 CRS_
34 COT_
25 TXC.
NC
~
.!! NC

3l:

III

..>
....
!!!.
CD

RO-

a.

5112DACK.
5112CSORESET

WR_

III

"'C
~

.J:,..
~

I\)

CD

CO
N
U1
ID

e RD-

..

+~

!'J

~
21

<:7

14
1

0
~

N

0..

iii

0

~

PROM CS.

C)
CD
:::I
CD

PUllUP

.
..

2L

0

32
38
37
38
311
9

10

011 11

0..

iii

RTS.
015
014
013
012
01.1
010
OS

o 13

III

07
08
05
04
03
02
01

20

DO

~

o
o
~

14
15
18
17
111

o

U2
11/18

~ ClKSRC
~5 FREQ

8
7

ClK

82S123
07
08
05
04
03
02
01
DO

9

7
8
5
4
3
2
1

PA4
PA3
PA2
PAl
PAD

PA (0-4)

»"tI
I

Co)
Co)

U14

5920REOO
5920REQI
51121 NT
592EOP.

(0-7)

o.t.LE XO-438

~
2 D,PR
Q

211
27
41
42

"4 14
"3 13
.0.2 12
11
"I
"0 10

07
08
05
04
03
02
01
00

o

101HZ DSC

'"~

ORal
ORQO
INT
CSI/EOP.

(8-15)

I.A. ROM

011

OS 12

o
o

'"

~

15 CS

a: oi'"
0:

4 WR2 o.t.CK3 CS.
40 RESET

RTS.
015
014
013
012
011
010

N

......

-

5

3 C~
8
CLR
I
U3A

JPII~

8IotHZ

~
1

~
¢

292066-14

i
z0

::l
C"
C

-...
CD
CD
Co

-

TCI

SA (0-19)

3:

III
III

...iii

LTCW
OE2.

~

..

III
"C
CD

1111

C

!.
III

-

-

A (0-7)

A4
All
A8
A7

tD

...CD
J!l

-I

il -»
Co

0

:::r

AD
AI
A2
A3

c

g

DO

DO

01
02
03
04
05
08
07

01
02
03
D4

05
08
07

2
3
4
5
II
7
II

II

74LS245
- 111 III
A1
A2
112 17
A3
113 111
A4
114 15
AS
as 14
AS
1111 13
A7
B7 12
AS
&II II
OIR

+v Ii

I

ATOO
ATOI
AT02
AT03
AT04
AT05
ATOll
AT07

U211

Ril.
EN ADOR.

0

tD

III
III
17
18
15
14
13
12

EN OATA.

::::
c

2
3
4
5
II
7
II
II
II
1 DC

LSB DATA BUFFER

U27

...

~
(.)

SAil
SAl0
SAIl
SA12
SA13
SA14
SA15
SAIII

MSB lATCH
74ALS573
lQ
10
20
2Q
3D
3D
4D
4Q
50
50
80
IIQ
70
7Q
110
IIQ
ENe

DE,.

2
3
4

5
II
7
II
II
II
I

74ALS573
lQ
10
20
2Q
3D
3D
4D
4Q
50
50
80
8Q
70
7Q
80
IIQ
ENe
De

III
111
17
18
15
14
13
12

U24

o (0-7)
o (8-15)
ATD (0-15)

TCI

LSB lATCH

DO

01
02
03
04
D5
011

07

011

2

011

3
4
5

DID
OIl
012
013
014
015

II

7
II

II

74LS2045
AI
III
A2
112
A3

A4
AS
AS

A7
AS

+a Ii

111
17
18
B3
114 15
as 14
BII 13
B7 12
&II II

>'tI
I

...

(,,)
(,,)

AT08
ATOll
AT010
ATOll
AT012
AT013
AT014
ATOIS

OIR
U19

IASB DATA BUFFER

D (0-7)
D l8-15}
ATD (0-15)

--

292066-15

74LS1I74

DO
01
D2
03
D4
Oll
011
07

z

0

:::I

-.
C'

5.

LD TX*

C1)

CAKO_

C1)

2
3
4
1I
II
7
II
II
11
1

Co

III
C1)

Co

..

~
C1)

"'0

III
CD

-

.

~

LD RX-

C1)

OAK'.

J!I

::u
C1)

....in

.g...
13
15

....1.l..

.g..
111

CLK

oc '

1Yl
1Y2
1Y3
1Y4
2Yl
2Y2
2Y3
2Y4

~
7

2G

SA (0-19)

SAl II
SAl II
SA17
SA4

-

cl
-

IoIWR.

WRO.

5

t--2

U25

74LS1I74
2 10
10
320
20
4 30
3Q
5 4Q
4Q
II lID
SO
7 lID
IIQ
II 70
70
8 110
IIQ
11 CLK
1 OC

111
111
17
111
111
14
13

LA17
LAla
LAla
LA20
LA21
LA22
LA23

~
a

!!"

rll-

-

SAIl
SAil
SAl0
SA" .
SA12
SA13
SA14
SIIlli

PA (0-4)

STOP REGISTER

II"
0
0

DO
01
02
D3

3

"C

D4

III
III

05
011
07

0

LD LIMIT_

74LS1I74
2 10
10
320
20
4 3D
3Q
5 .0
4Q
II lID
SO
7 lID
IIQ
II 70
70
II lID
110
'1 eLK

~

OC..

"~

»
"0

0

I

;;:

W

W
-"

iii

OVERFLOW COMPARATOR

U12

C1)

.....

IIQ

1... 1
1... 2
1...3
1...4
10
2Al
2A2
2A3
2A4

la
111
14
12

RCV PAGE REGISTER
DO
01
02
03
D4
DlI
011
07

~ '9.
.j>.

CD

IIQ

.70

2
4
II
II
1

MOST SIG. ADD. BUFFER

o (0-7)

C1)

en
0'

SO

LA17
LAlli
LAlli
LA20

--

EN CWD_

::u
C1)

"C

3Q
4Q

.0
50
110
70
aD

EN AOOR.
OMA w_
, DMIotRO

III

III

10
2Q

LA17
LAla
LAlli
LA2D
LA21
LA22
LA23

U20

3:

.»...

10
20
3D

74LS244
111
la
17
111
15
14
13

..

-'

XNT PAGE REGISTER

111

111
17
111
15
14
13
12

PAD
P... l
PA2
PA3
PA4

PAD
PAl
PA2
PA3
PA4

2
4
II
II
11
13
15
17
3
5
7
II
12
14
111
111
1

74LS81111
PO p..0
Pl
P2
P3
P4
P5
PII
P7
00
A'
02
03
04
05
all

19

OVERFLOW

Q7

G

U22

292066-16

-

0<1

_ _ -.

A (0-7)
D (0-7)

z

0

:I
0C

=
...
CD
CD

a.

s:::

DI
IIJ

...
CD

~ DI~

UI

-...

'tI
CD

C

s:::

•

D (0-7)

SAS
SAID
SAil
SAI2
SA13
SA14
SAUl

18
18
17
18
15
1.
13

74573
lQ
lD
2Q
2D
3D
3D
4Q
4D
50
5D
lID
liD
7Q
7D

SAU.

12

8Q

DREQO.
DREQI.

2
3
4
5
II
7
II

eo e

ENC

MID. ADD. LATCH

ri-!-

11237
DBO
M
OBI
"I
DB2
A2
DB3
A3
DB4
M
DB5
A5

32
33
34
35
37

M
"I
A2
A3
M

M
"I
A2
A3
M

311
38
40

AS
"II

AS

AS
",7

DO
Dl
02
03
D4
05
D8

DD
Dl
02
D3
D4
D8

30
28
211
27
28
23
22 DBS

07

D7

21

OS

DB7

II ADSTB HRQ 10
18 DRQD AEN ~

oc ~

III

1 JP7 3
2
4 '

II

HLDA37

RESET
37 CS.

l

.... _

A (0-7)

U21

/1.7

I

AS
1..7

111
17
18
15
1.
13
12

74245
Bl
"I 2
B2
A2 3
B3
A3"
B4
". 5
B5
AS II
B8
"II 7
B7
"7 II

11

B8

All

CIR

ADD. XCVR.

SAl
SA2
SA3
SA4
&AS

SAil
SA7

sa

SAil

H 1",..._-.

G~

I~ ~~ ~~i~~:!i=~~!I~~~~~~!;t:;;l::;U;30;;~~;:~::J:::~~~;;::::

13 RST
11 CS

CLK 12
DAKO 25
OAKI 24
DRQ2 iOR
1
DRQ3 lOw
2
EOP 38

DRQ •
OACK 1
OACK2

~ RDY

---*
........,!!.

READY'

1~7

JP8

1iiR

4

1

3

DIIIA 18 ..

):0

IotRD

3

2

4

OIotIlRD

l'

...
Co)
Co)

Ul

EN ADDR.
DACKO..

-.

1l1otH2

.

RD_

RD.

r

MSEOP.

0
0

:I

..... IL.

0

CII

=;-

'

...iii'

lNXXXX
CRNNN

+5 V

~

%"
~
a
~ii:~ii:.~~!!:~ii:

~ii~iii~a:2"'~ii

SIP1C

L-____------~----+_~~~~~
10Kt

RNNN

XXXXI

...•

ASTB

z

SI 5
292066-17.

inter
Parts List
Reference
IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
IC9
IC10
IC11
IC12
IC13
IC14
IC15
IC16
IC17
IC18
IC19
IC20
IC21
IC22
IC23
·IC24
IC23
SPARE1
SPARE2
SIP1
SIP2
SIP3
JP1
JP2
JP3
JP4
JP5
JP6
RR1
RR2
RR3
C1
C2
C3-C20
P18

AP·331

Vee

Gnd

Pins

1,44,43
20
20
20
20
16
31
20
20
20
20
20
20
20
14
14
16
24
24
24
24
14
14
20
28
16

21,22,23
10
10
10
10
8
20
10
10
10
10
10
10
10
7
7
8
12
12 .
12
12
7
7
10
14
8

44 (PLCC)
20
20
20
20
16
40
20
20
20
20
20
20
20
14
14
16
24
24
24
24
14
14
20
28
16
10
10
10
10

Type
82592
74ALS573
74LS245
74ALS573
74 LS245
82S123
82C37A
74LS688
74ALS574
74ALS574
74ALS574
74ALS573
74LS245
74LS244
74LS74
74LS393
74AS174
PAL20L10
PAL20L 10
PAL20L10
PAL20L10
OSC8MHz
. 74LS164
74LS688
27256
74LS163
DIP SWITCH
10K
10K
10K
10 pin jumper
12 pin jumper
10 pin jumper
3 pin jumper
16 pin jumper
12 pin jumper
13K%W.
1K%W
1K%W
100,...F/16V
100,...F/16V
0.1,...F
IBM CONN. 803,829
801,810,83162

1
1
1

1-416

inter

AP-331

APPENDIX E
FLOWCHARTS AND PROGRAM LISTINGS

292066-18

Driver Broadcast Packet-Driver Send Packet

Decrement Fragment Count

292066-19

Start Send

1-417

intJ

AP-331

IPX Hold [vent

292066-20

Driver Poll

1-418

Ap·331

292066-21

DriverlSR

1-419

inter

AP-331

292066-22

RcvdPacket

1-420

inter

Ap·331

292066-23

1-421

inter

AP-331

292066-24

Deliver Packet

1-422

inter

AP-331

292066-25

Sent Packet

1-423

AP-331

$mod186
$nogen
;********************************************************tittttttt __ _

IIIII! FOR EVALUATION PURPOSES ONLY IIIIII
NetWare Driver for the Intel Non Buffered Master adapter.
Written by Ben L Gee.
Based on Joe Dragony's driver for the LAN-On-Motherboard Module.
;*******~.**********************.*****************

•• ** ttttttt,ttttt*_

name Shell_Module
false equ 0
true equ 1
$ include (relid.ine)
$inelude(smaero.ine)
het (V2_l, 1)
het (V2_0, 0)
'*define(slow) local label
jmp short 'label
Uabel:

'*define(fasteopy) local label (
shr ex, 1
rep movsw
jne Uabel
movsb
Uabel:

'*define (ine32 m) ,(
add word ptr 'mID], 1
ade word ptr tm[2], D
292066-26

1-424

inter

AP-331

;;;;;I;;;i;;;II;;;;;;;;;;;;;;;

Data Structures
iii;;;;;;;;;;;;;;;;;;;;;;;;;;;
ECBStructure struc
Link
dd 0
ESRAddress
dd 0
InUseFlag
db 0
CompletionCode
db 0
SocketNumber
dw 0
IPXWorkspace
db 4 dup (0)
Transmitting
db 0
DriverWorkspace db 11 dup (0)
ImmediateAddress db 6 dup (0)
dw 1
FragmentCount
FragmentDescriptorList db 6 dup (1)
ECBStructure ends
FragmentDescriptor struc
FragmentAddress dd
FragmentLength
FragmentDescriptor ends

?

rx_buf_structure strue
rx_dest_addr
rx_source_addr
rx-physical_Iength
rx_checksum
rx_length
rx_tran_eontrol db 1
rx_hdr_type
rX_dest_net
rx_dest_node
rX_dest_socket
rx_source_net
rx_source_node
rx_source_socket dw 1

dw ?

db6 dup (1)
db 6 dup (1)
dw 1
dw
dw 1
db 1
db4
db 6
dw
db 4
db 6

dup
dup

(1)
(1)

dup (1)
dup (7)

rx_buf_strueture ends
tei_status strue
statusO db
db
statusl db?
db1
bc_Io
db1
bc_hi
db 1
tci_status ends

db
db 1

292066-27

1-425

inter

AP-331

ipx_header_structure struc
checksum
dw
packet_length
dw
transport_control
db
packet_type
db 7
destination_network
db 4 dup (7)
destination_node db 6 dup (7)
destination_socket
dw 7
source_network
db 4 dup (7)
source_node
db6 dup (7)
source_socket
dw ?
ipx_header_structure ends

CGroup group Code, mombo_init
assume cs: CGroup, ds: CGroup
Code

segment word public 'CODE'
public
public
public
public
public
pubUc
public
public
public

DriverSendPacket
OriverBroadcastpacket
Dri~erOpenSocket

DriverCloseSocket
DriverPoll
DriverCancelRequest
DriverOisconnect
SDriverConfigurstion
DriverISR

public LANOptionNams
extrn
extrn
extrn
extrn
extrn
extrn
extrn
extrn

extrn
extrn
extrn

IPXGetECB: NEAR
IPXReturnECB: NEAR
IPxReceivePacket: NEAR
IPXRece1vePacketEnabled: NEAR
IPXHoldEvent: NEAR
IPXServiceEvents: NEAR
IPXlntervalMarker: word
MaxPhysPacketS1ze: word
ReadWritecycles: byte
IPXStartCriticalSection: NEAR
IPXEndCriticalSection: NEAR

292066-28

1-426

inter

AP-331

Define Hardware Configuration
ConfigurationID db 'NetWareDriverLAN WS
SDriverConfiguration LABEL byte
db 4 dup (0)
db 6 dup (0)
db 0
db 0
address is determined at initialization
node_addr_type
dw 1024 I largest read data request wi~l handle (512, 1024, 2048, 4096)
max_data_size
dw LANOptionName
lan_desc_offset
db 'LanType
lan_hardware_id
dw 1

transport_time

; transport time

db 11 dup (0)
reserved_3
db tMajorVersion
major_version
db tMino'rVersion
minor_version
dbO
flag_bits
selected_configuration db
; board configuration '(interrupts, 10 addresses, etc.)
number_of_configs
db 10
config-pointers
dw CFGO, CFG1. CFG2, CFG3, CFG4
dw CFG5, CFG6, CFG7. CFG8, CFG9
LANOptionName

'db' Intel '
db 'Non Buffered Master'
db' (For Evaluation Only)'
db' VtMajorVersion.tMinorVersion'
db ' (tVersionDate)'
db O. ' $'

Hardware Setting table ,structure

HardwareStructure struc
dw
H_IOBase
dw
H_IOLength
dd
H_Auxl
tif (tV2_1) then (
db
)fi
H_RAMsegment
dw
dw
H_RAMSize
Uf (tv2_1) then (

unsigned

db

)fi

H_Aux2
H_IRQUsedFlag
H_IRQ
"_Aux3
H_DMAOUsedFlag
H_DMAO

dd
db
db
dw
db
db
292066-29

1·427

inter

Ap·331

H_DMA1UsedFlaq db ?
H_DMAl
db ?
'if ('V2_11 then
H_Flaql
db ?
H]laq2
db
If!
H_Descrlptlon db
HardwareStructure ends

'*deflne(CFG(pl,p2,p3,p4,ml,m2,m3,m4,11,12,13,14,dl,d2,d3,d4,fl,f2,msql) ( label byte
dw 'pl, 'p2, -'p3, tp4
tif (tV2_1I then ( db 0 ) £1
dw 'ml
dw 'm2 * 16 I f !
tif (tV2_01 then
dw tm2 If!
tif ('V2_11 then
tif ('V2_1) then ( db 0 I fi
dw 'm3
tif (tV2_01 then ( dw tm4 * 16
f!
f!
tif ('V2_11 then I dw tm4
db '11, '12, '13, '14, 'dl, td2, 'd3, 'd4
tif I"V2_11' then ( db tfl, U2 ) f!
''If ('pl ne 01 then (
db 'I/O Base - "pl'
'if l"p3 ne 0) then
db ' and tp4'
If!
'If (Itm2 ne 0) or (tl1 ne 0) or ,"dl ne 0» then (
db "
)£1

f!
'If '''m2 ne 0) then ,
db 'RAM Base - tml'
'If l'm4 ne 01 then (
- db ' and 'm3'
)f!
'if «'11 ne 01 or ,'dl ne 01) then (
db '
) fi
)f!
'If I'il ne 0) then (
db ' INT - t12'
'If ,'i3 ne 0) then
db ' and \14'
)£1

'if Itdl ne 0) then
db "
If!
)f!
292066-30

1-428

AP·331

tif (tell ne 0) then (
cIb ' DMA = tel2'
tif (tel3 ne 0) then
elb ' anel 'el4'
) fi
f1

elb 'msq,

CFGO
CFG1
.CFG2
CFG3
CFG4
CFG5
CFG6
CFG1
CFGS
CFG9

°

flaqs
Memory Int
DMA
I/O
tCFG(300h,16,O,O,O,0,O,O,-1,lO,O,O,-l,6,O,O,O,0,")
tCFG(310h,16,O,0,0,O,O,0,-l,ll,O,0,-1,1,O,O,0,0,")
tCFG(300h,16,0,O,0,0,O,O,-1,12,0,O,-1,5,O,O,0,O,")
tCFG(310h,16,O,0,0,0,0,O,-1,14,0,O,-1,6,0,O,0,O,")
tCFG(300h,16,O,0,0,0,0,0,-1,15,0,0,-1,1,O,0,O,0,")
tCFG(310h,16,O,0,0,0,0,0,-1,10,0,0,-1,5,0,0,0,0,")
tCFG(300h,16,O,O,O,0,0,0,-1,11,0,0,-1,6,0,0,0,0,")
tCFG(310h,16,0,0,0,0,0,0,-1,12,0,0,-1,1,0,0,O,O,")
tCFG(300h,16,O,0,O,O,O,O,-l,14,O,0,-1,5,O,0,O,O,")
tCFG(310h,16,O,O,O,O,O,O,-1,15,O,O,-l,6,0,O,O,O,")

even

;*********************************************************

Error Counters

i-*----*·**-----*-*---**-**·_-*------_· __ ·_*· __ ·_*------Public DriverDiaqnosticTable, DriverDiaqnosticText

DriverDiaqnosticTable LABEL byte
elw DriverDebuqEnel-DriverDiaqnosticTable
DriverDebuqCount
cIb tMajorVersion, 'MinorVersion
DriverVersion
cIb 01, 00
StatisticaVeraion
elw 0, 0'
TotalTxPacketCount
elw 0, a
TotalRxPacketCount
elw a
NOECBAvailab1eCount
not useel
elw -1
PacketTxTooBiqCount
not useel
PacketTxTooSmallCount elw -1
PacketRxOverflowCount elw a
elw a
PacketRxTooBiqCount
PacketRxTooSmallCount elw a
not useel
PacketTxMiscErrorCount elw -1
PacketRxMisoErrorCount elw
elw 0
RetryTxCount
I not useel
elw -1
ChecksUmErrorCount
HarelwareRxMismatchCount elw 0
NumberOfCustomVariables elw (DriverDiaqnosticText-DriverDebuqEnel1)/2

°

DriverDebuqEnel1 LABEL byte
292066-31

1-429

intJ

AP-331

I;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Driver Specific Error counts
i;;:;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;ll:

false_59a int
no_ers
no_ets

-

lost_rx

MaxCollisions
no_59a_int
rx_buff_ovflw
ten_cent latch_crash
tx_timeout
underruns

-

.dw
dw
dw
dw
dw
dw
dw
dw
dw
dw

a
a
a
a
a
a
a
a
a
a

DriverDiaqnosticText LABEL byte

db
db

'False59alnterruptCount',
' LostCRSCount' , 0
'LostCTSCount' , a
'LostOurRecelverCount', 0
, MaxCollisionsCount', 0
'No590InterruptCount', a
'ReceiveBufferOverflow',a
, TencentLatchCrashCount',
, TxTimeoutErrorCount', a
'UnderrunCount', a

db

a, a

db
db
db
db

db
db
db
db

a

a

DriverDebuqEnd LABEL word
even

I;;;;;;;;;;;;;;;;;;;

Equates
I;;;;;;;;;;;;;;;;;;;

CR
LF

equ ODh
equ aAb

TransmitHardwareFailure equ aFFh
Packet UnDeliverable
equ OFEh
equ OFDh
PacketOverflow
equ OFAb
ECBProcessinq
equ 10
TxTimeOutTicks
Adapter I/O ports
Addr592
IA_PROMyort
AddrLatchLow
AddrLatchHiqh
LimitReqister

dw
dw
dw
dw
dw

aSh
aah
ach
Odh
Oeh

+
+
+
+
+

IOBase
IOBase
IOBase
IOBase
IOBase

(I/O)
(I)

(I)
(I)
(I/O)
292066-32

1-430

inter
8259

AP-331

definitions

InterruptControlPort
equ
InterruptMaskPort
equ
ExtralnterruptControlPort
equ
ExtralnterruptMaskPort
equ
EOI
egu 020h

020h
021h
OAOh
OAlh

8237 definitions
; Command Register
RotatingPriority
ExtendedWrite
ActiveLowDREQ

equ OlOh
equ 020h
equ 040h

; Mode Register
WriteTransfer
ReadTransfer

AutoInitialization
DemandMode
CascadeMode

equ
equ
equ
equ
equ

OOOOOlOOb
OOOOlOOOb
OOOlOOOOb
OOOOOOOOb
llOOOOOOb

even

OOlh
005h
007h
009h

+
+
+
+

IOBase (I/O)
IOBase (0)
IOBase (0)
IOBase (0)

DMAcmdstat
DMAsnglmsk
DMAmode
DMAff

dw
dw
dw
dw

XmtDMApage
XmtDMAaddr
XmtDMAwdcount

dw OOah
dw OOOh
dw 002h

+ IOBase (0)
+ IOBase (I/O)
+ IOBase (I/O)

RcvDMApage
RcvDMAaddr
RcvDMAwdcount

dw OOch
dw 004h
dw 006h

+ IOBase (0)
IOBase (1/0)
+ IOBase (I/O)

MasterDMAcmdstat
MasterDMAsnglmsk
MasterDMAmode
MasterDMAff

equ
equ
equ
equ

MasterDMApage
MasterDMAaddr
MasterDMAwdcount

dw
dw OcOh
dw Oc2h

XmtDMAtx
XmtDMAmsk
XmtDMAunmsk

db DemandMode + AutoInitialization + ReadTransfer
db 4
db 0

RcvDMArx
RcvDMAmsk
RcvDMAunmsk

db DemandMode + AutoInitialization + WriteTransfer + 1
db 4" + 1
db 0 + 1

ODOh
OD4h
OD6h
ODSh

292066-33

1-431

inter-

Ap·331

MasterDMAmodevalue
MasterOMAmsk
MasterOMAunmsk

db CascadeMode
db 4
db 0

82592 commands
C_NOP
equ OOh
C_SWP1
equ 10h
equ OFh
C_SELRST
C_SWPO
equ 01h
C_IASET
equ 01h
C_CONFIG
equ 02h
C_MCSET
equ 03h
equ 04h
C_TX
C_TDR
equ 05h
C_DUMP
equ 16h
equ 07h
C_DIAG
equ 18h
C_RXENB
C_ALTBUF
equ 09h
equ lAb
C_RXOISB
C_STPRX
equ 1Bh
equ OCh
C_RETX
C_ABORT
equ OOh
equ OEh
C_RST
equ OFh
C_RLSPTR
equ 1Fh
C]IXPTR
C_INTACK
equ 80h
I;;;;;;;;;;;;;;;;;;;;;;;;;;

Variables
;;;;:;;;;;;;;;;;;;;;;;:;;;;
even

gp buf size
equ 600
in words
max_rx_buf_size equ 2200
in words
gp_buf
dw gp_buf_size + max_rx_buf_size dup (1)
gp_buf-pointer dd 1
gp buf start
dw
A1-A16 of General Purpose Buffer EA
gp_buf-page
dw ?
A17-A23 of General Purpose Buffer EA
tx_byte_cnt
dw 1
IPX packet length plus header length
rx_buf_start
dw 1
A1-A16 of Receive Buffer EA
rx_buf-page
dw
A17-A23 of Receive Buffer EA
rx_buf_head
dw ?
current rx head, buffer has been flushed to here
rx_buf_taU
dw 1
value read from 10 cent latches
rx_buf_length dw
word size of rx_buf
rx_buf_segment dw 1
calculated at init-for use by IPXReceivePacket
rx_buf_first
dw ?
offset from rx_buf_segment of start of rx_buf
rx_buf_limit
dw
offset from rx_buf_segment of limit of rx_buf
rx_buf_size
dw ?
byte size of rx_buf
Logica12Physical dw ?
add this to convert from rx_buf_segment to rx_buf-psge
rx_list
dw 30 dup (1)
292066-34

1·432

inter

AP-331

paddinq
SencIList
tx Btart_time
tx_active_flaq

dw ?
dd 0
dw 0
db 0

paints to list of ECBs to be sent

.;***************************************************.**************

Interrupt Procedure
;*t _____ ** _______ * ___

*_______ ***_* ______________

*. ___

***************

even

DriverISR PROC far
pusha
push ds
push es
may ax, cs

DS points to C/DGroup
ES also

mov ds, ax
moves, ax

mav al, EOI
aut InterruptControlPart, al
out ExtraInterruptContralPart, al
mav dx. Addr592
may al, 0
set status req to paint to req 0
out dx, al
'slow
in al, dx
test al, BOh
Ufz
590 int
inc no
,
'else
'do
iqnare the EXEC bit
and al, NOT 20h
save the status in AU
maY ah, al
did I receive a frame?
cmp ah, ODBh
Ufe
call RcvdPacket
'else
did I finish a transmit?
cmp ah, B4h
'He
call SentPacket
'else
cmp ah, Bch ' 1 did I finish a retransmit?
Ufe
call SentPacket
'elae
inc falae_590_int ; unwanted interrupt
tendH
'endif
'endH

-

292066-35

1:433

AP-331

push cs
pop ds
cmp tx_active_flag, false
tife
: verify that our receiver is still going.
mov dx, Addr592
mov al, 60h
: point to status byte 3
out dx, al
blow
in .. 1, dx
test'al, 60h
Ufz

inc
mov
mov
out
hndif
'endif

lost_rx
al, C_RXENB
dx, Acidr592
dx, al

mov dx, Addr592
mov al, C_INTACK
out dx, al
blow
xor al, al
out dx, al
hlow
in al, dx
test al, BOh
hhUenz
tendif

issue interrupt acknowledge to the 590

set status reg to point to reg 0

call IPXServiceEvents
pop es
pop ds
popa
iret
DriverISR endp
even

RcvdPacket proc near
When the address bytes are being read it is possible that·
another frame could come in and cause a coherency problem
with the ten-cent latches. I .. m dealing with this
possibility by reading AcidrLatchHigh twice and making
sure the'values match. If they don't the read is redone.
cli
mov dx, AddrLatchHigh
read high address byte of last frame received
in al, dx
292066~36

1·434

Ap·331

'do
save it in bh
mov bh, al
read low address byte of last frame received
mov dx, AddrLatchLow
in al, dx
mov bl, a1
; Read AddrtatchHigh again to make sure it hasn't changed •••••••
mov dx, AddrtatchHigh
; read high address byte again
in al, dlt
cmp a1, bh
'lwhilene
shl bx, 1
; convert to byte address
sub bx, Logical2fhysical I bx - magic - physical - (physical-logical)
logical
this is the last location contai,ning rlt data
mov ai, bx
normalize si
call Norma1izefointer
was it already a valid pointer 1
bx, a1
if not, big trouble •••
Ufne
inc ten cent latch_crash
'elsel
'do
moves, rx_buf_segment
mov ch, ea: [ail
get bc_hi
sub si, 2
call Normalizefointer
mov cl, es: [si]
aub si, 2
call NormalizePointer
get statual
mov ah, es: [ail
sub si, 2
call Norma11zePointer
; get atatuaO
mov a1, es: [si]

cmp

I cx haa actual number of bytes read
dec cx'
; toss byte count , atatus
round up
and c1, Ofeh
si points to first location of frame
Bub si, ex
call Normal1zePo1nter
aave in bx
mov bx, a1

test for good receive
bad receive
inc facxetRxH1acErrorCount
jmp ahort Sk1pThiaFrame
good rece1ve
telidif

test ah, 20h

'lfz

sub cx, 14
cmp cx, 1024 + 64

sub length of 802.3 header

Ufa
inc PacketRxTooBigCount
jmp short SkipThisFrame
'endif
292066-37

1-435

intJ

AP-331

cx, 30
Ufb
inc PacketRxTooSmallCount
jmp short SkipThisFrame
'endif

Chip

lea si, [bx].rx_length
call NormalizePointer
mov ax, es: [si]
get IPX length
xchg al, ah
inc ax
and al, Ofeh
xchq al, ah
lea 8i, [bx].rx-physical_length
call NormalizePointer
cmp ax, es: [si]
; same as 802.3 lenqth
Ufne
inc HardwareRxHismatchCount
jmp short SkipThisFrame
'endif
xchg al, ah
at least min lenqth minus header
cmp ax, 60 - 14
tifbe

mov ax, 60 - 14
'endif

DO,

round up

match physical lenqth
cmp ax, ex
'ifne
inc HardwareRxHismatchCount
'else
mov di, num_of_frames
add di, di
mov rx li.t[dil, bx ; first location of ethernet frame
cinc num_of_frames
cmp num_of_frames, length rx_list
je hand_off-packet
.endif
Sk!pThisFrame:
movai, bx
cmp rx_buf_head, ai
first frame of sequence 1
yes, go process list
je hand_off-packet
sub si, 2
call NormalizePointer
• forever
no, continue processing frames
hand_off-packet:
~end1f

cli
mov di, num_of_frames
add di, di
Ufnz
'do
sub di, 2
mov ai, rx_list'(dil
lea si, [si].,rx_dest_socket
292066-38

1-436

intJ

AP-331

call NormalizePointer
maves, rx_buf_segment

mov ax, es: (si)
call IPXGetECB
Ufnz
call DeliverPacket
hndif
dec num_of_frames
'whilenz
'endif
; update the limit reqister
mov dx, LimitReqister
1n al, dx
test aI, 1

\ifnz
inc rx_buff_ovflw
hndif
mov si, rx_buf_tail
sub 31, 256
call NormalizePo1nter
mav ax, 51
add ax, Loqical2Physical
mov al, ah
out dx, al

just for the record

move new limit value to ax
convert to physical address
only need bits Al5 •• A8
store it in the limit reqister

mav 51, rx_buf_tall

add si, 2
call Normal1zePointer
mov rx_buf_head, 8i
ret

set rx_buf_head to new value for next receive

RcvdPacket endp
even

DellverPacket proc near
push di
mav di, rx_list[di)
mov bp, si
xchq si, di

copy ecb offset to bp
es:di
ecb
ds:s! - packet

may ds, rx_buf_segment

assume ds: noth1nq
add d, 6
lea d1, (d1).Immed1ateAddress
call NormalizePointer
movsw
call NormalizePointer

skip destination address

movsw

call NormalizePointer
movsw

add si, 4
call NormalizePointer
mov dx, ds: (si)

; skip etype and checksum
; qet lenqth from IPX header
292066-39

1-437

AP-331

xchq dh, dl
sub si, 2
call NormalizePointer
moy di, bp·

point to checksum

disburse the packet
ds:si = packet data source
es:bp - ECB
ax
fraqment count
dx
- amount of data in source
bx
- pointer to the FraqmentDescriptorList
cx
= size of this fraqment
moy cx, es: [bp).FraqmentCount
lea bx, [bp).FraqmentDescriptorList
'do
push es
push cx
moy cx, es: [bx].FraqmentLenqth
les di, es: [bx).FraqmentAddress
moy ax, rx_buf_l1mit
sub ax, si
cmp ax, ex
lifb
xchq cx, ax
cx = amount to copy
sub ax, ex
ax - amount not copied
cmp dx, cx
Ufb
moy ex, dx
'endif
sub dx, ex
'fastcopy
moY si, rx_buf_first
mov ex, ax
tendif
cmp dx, cx
Uib

mov ex, dx
tendif
sub dx, cx
'fastcopy
pop cx
pop es
add bx, 6
Uoop
292066-40

1~438

inter

AP-331

; deliver the ECB
mov si, bp
moves: [sij.CompletionCode, 0
push cs
pop ds
assume ds: CGroup
'inc32 TotalRxPacketCount
call IPXHoldEvent
pop di
ret
DeliverPacket endp

even

input:
si = pointer into rx_buf
output:
si a valid pointer into rx_buf
no other registers modified
NormalizePointer proc near
cmp si, cs:
Ufae
cmp si,
tifb
ret
%endif
sub si,
ret
tendif
add si, cs:
ret

rx_buf_first
cs: rx_buf_limit

cs: rx_buf_size

rx_buf_size

NormalizePointer endp
even
SentPacket proc near

eli
cmp tx_active_flag, true
tHe
in al, dx
mov ah, al
hlow
in aI, dx
xch9 ah, al
test ah, 20h
Ufz
292066-41

1·439

AP-331

Max collisions?1
test al, 20h
Ufnz
inc MaxCollisions
'endif
test ah. Olh
Tx underrun?1
Ufnz
inc underruns
'endif
did we lose clear to aend??
test ah. 02h
Ufnz
inc no_cts
\endif
did we lose carrier sense??
test ah. 04h
Ufnz
inc no_crs
'endif
may al, TransmitHardwareFailure
'else
; extract the total number of retries from the status
and ax. OFh
register and add to retry count
add RetryTxCount. ax
xor ax, ax
status - O. good transmit
'endif
may cx. word ptr SendList[2]
'ifcxnz
segment of next sca in list
offset of next sca in list
mov si, word ptr SendList[O]
cmp es: [si].Transmitting. true I if not canceled
Ufe
mayes: [si].CompletionCode. al
movax. ea: word ptr [si].Link[O]
mav ward ptr SendList[O]. ax
moyax. e8: word ptr [si].Link[2]
moY word ptr SendList[21. ax
; finish the transmit
moves: [si].InUaeFlag. 0
call IPXHoldEyent
'endif
'endif

mav 8a, ex

mav tx_actiye_flag. false
may cx. ward ptr SendListl2]
'ifcxnz
segment of next sca in list
mav ea, ex
offset of next sca in list
maY si. word ptr SendList[O]
call StartSend
'endif
tendif
ret
Sent Packet endp .

292066-42

1·440

intJ

Ap·331

Driver Send Packet
Driver Broadcast Packet
Assumes

es: 51 points too a fully prepared Event Control Block
DS - CS
Interrupts are DISABLED but may be reenabled temporarily if necessary
don't need to save any reqisters
even

DriverBroadcastPaeket:
DriverSendPacket PROC NEAR
moves: [sil.Transmitting. false

mov cx. word ptr SendList[2)
Ufcxnz
; search to the end of the list. and add. there.
mov di. word ptr SendList[Ol
'do
mov ds, ex
mov cx. ds: word ptr [dil.Link[21
jcxz AddListEndFound
mov di. ds: word ptr [d11.Link[Ol
'forever

AddListEndFound:
mov es: word
mov es: word
mav ds: word
mov ds: word
mav ax. es
mov ds. ax
ret
'endif

ptr
ptr
ptr
ptr

[sil.Link [01.
[sil .Link [2).
[di).Link[O).
[dl).Llnk[2).
;

move null pointer to newest SCB's
l1n~ field

cx
ex
si
es

set ds back to entry condition

moves: word ptr[si).Link[O). cx
moves: word ptr[si).Link[2). cx
mov word ptr SendList[O). s1
mov word ptr SendL1st[21. es
; drop through to Start Send
DriverSendPacket endp

Start Send
assumes:

es: SI
points to the ECB to be sent.
interrupts are disabled
292066-43

1-441

inter

AP-331

even

StartSend PROC NEAR
old
moves: (si].Transmittinq, true
push ds
I save ds for future use
I qet IPX packet le~qth out of the first fraqment (IPX header)
lds bx, es: dword ptr (si].FraqmentDescriptorList
mov ax, ds: (bx].packet_lenqth
; restore ds to CGROUP
pop ds
save lenqth for later use in 590 lenqth field
push ax
byte swap for 592 lenqth field calculation
xchq al, ah
add in the overhead bytes DA, SA, CRC, lenqth
add ax, 18

I

mov paddinq, 0
cmp ax, 64
Ufb
minimum lenqth frame
mov paddinq, 64
pad lenqth
sub paddinq, ax
moV ax, 64
tendif
sub ax, 10
SA and CRC are done automatically
inc ax
and al, OFEh
frame must'be even
mov tx_byte_cnt, ax
lea ~:. qp_buf-pointer
I move the byte count ~nto the transmit buffer
stosw
I move the destination address from the tx ECB to the tx buffer
mov bx, si
lea si, [bx].ImmediateAddress
mov dB, word ptr SendList[2]
movsw

movsW
mOVSN

mav ax, cs

qat'back to the code (Dqroup) section

mov dB, ax

; now the 590 lenqth field
pop ax
xchq ah, al
inc IIX
make sure E-Net lenqth field is even
and al, OFEh
xchq ah, al
stosw
lds si, SendList
movax, ds: (ai].FraqmentCount
lea bx, [ail .,FraqmentDescriptorList
'do
push ds,
; save the seqment
mov cx, ds: [bx].FraqmentLenqth
lds si, ds: [bx].FraqmentAddress
Hastcopy
pop ds
; qet the seq~nt back
292066-44

1-442

AP-331

add bx,
dec ax
'whllenz
; start transmitting
mov ex, cs
mov ds, ex

; add any required padding
; make sure frame ends with a NOP
add cx, padding
shr cx, 1
rep stosw
mov tx_active_flag, true

mav ex, 4

mov dx, DMAff
out dx, al
mov
mov
out
mov
out

dx,
al,
dx,
al,
dx,

data is don't care

XmtDMAaddr
byte ptr gp_buf_start[Oj
al
byte ptr gp_buf_start[lj
al

mov ax, gp_bufJ>age
mav dx, XmtDMApage
out dx, al

DMA page value

mov al, XmtDMAtx; setup ohannel 1 for tx mode
mov dx, DMAmoda
out dx, al
ax, tx_byte_cnt
ax
ax, 1
dx, XmtDMAwdcount
out dx, al
hlow
mav d, ah
out dx, al

mov
inc
shr
mov

convert to word value and account for odd
byte DMA transfer

mov al, XmtDMAunmsk
mov dx, DMAsnglmsk
out dx, al
mov dx, Addr592
mov al, C_TX
out dx, al
mov ax, IPXIntervalMarker
mov tx_start_time, ax
tinc32
TotalTxPacketCount
ret
StartSend endp
292066-45

1-443

AP-331

DriverOpen5Dcket:
DriverDiscDnnect:
ret
;**********************************************************************

DriverpDll
PDll the driver to, see if there is anything to, do,
Is there a transmit timeDut? If so" abDrt transmissiDn and return
ECB with bad cDmpletiDn cDde. Check to, see if frames are queued.
If they are set up es: 51 and call DriverSendPacket.
;**********************************************************************

even

DriverPDll PROC NEAR
cmp tx_active_flag, true
Ufe

mDv dx, IPXIntervalMarker
sub dx, tx_start_time
cmp dx, TxTimeOutTicks

tHa
This transmit is taking tDD IDng
mDV tx_active_flag, false
1

; Issue
mDV dx,
mDV al,
Dut dx,

so,

let's terminate it nD,w

an abDrt to, the 82592
Addr592
abDrt transmit'
C_ABORT
al

inc tx_timeout
mDV cx', wDrd ptr SendList [2]
tifcxnz
mav es. ex
segment of next 5ca in list
mov si, word ptr 5endList[O)
offset of next sca in list
cmp es: (ai).Transmitting, true
if not canceled
Ufe

moves: [si].CDmpletionCode, TransmitHardwareFailure
mDvax, es: wDrd ptr [si).Link[O)
mov wDrd ptr 5endLiat(0), ax
mDvax, es: wDrd ptr [si).Link[2)
mDV wDrd ptr SendL1st[2], ax

stuffcDmpletion cDde Df
a f~iled tx

; Finish the transmit
mOVes: [si).InUseFlag, 0
call IPXHDldEvent
tend i f
'endif
292066-46

1-444

inter

Ap·331

; make sure that execution unit didn't lock up because of abort errata
mov dx, Addr592
mov al, C_SlIPl
out dx, al
mov al, C_SELRS'l'
hlow
out dx, al
mov al, C_SIIPO
hlow
out dx, al
mov al, C_RXENB
'slow
out dx, a1
: See if any frames are queued
mov ex, word ptr SendList[2]
Ufcxnz
moves, cx
: segment of next SCB in list
mov si, word ptr SendList[O] ; offset of next SCB in list
call StartSend
hndif
hndif
tendif
ret
Dri verPoll endp

Driver Cancel Request
Assumes on entry:
es: SI is pointer to ECB we want to cancel
DS is setup
Interrupts are DISABLED
Assumes any registers may be destroyed.
Returns completion code in ALI

00
FF

Buffer was located and canceled.
Buffer was not found to be in use by the driver

even

DriverCancelRequest proc near
: first, see if it is the one we are currently sending.
mav dx, es

cmp word ptr SendL1st[0], s1
Ufe
cmp word ptr SendList[2], dx
Ufe
we need to cancel tbe first entry.
from the send list.
movax, es: word ptr [si].Link[O)

first, unlink it

292066-47

1-445

inter

AP~331

mov word ptr SendList[O). ax
mov ex. es: word ptr [si).Link [2)
mov word ptr SendList[21. ex
mov e8: [si).CompletionCode. OFCh
mov es: [si).InUseFlag. 0
xor ax. ax
ret
\endif
'endif
; we need to search down the send list
movex. word ptr SendList[2)
mov di. word ptr SendList(O)
'do
'do
jexz Not Found
; move to the next link
mov ea, ex
mov bx. di
movex. es: word ptr [bx).Link(2)
mov di. es: word ptr (bx).Link(O)
next node is pointed to by CX:DI
; previous node is pointed to byes: BX
; see if we found it
emp di. si
hhUenz
cmp ex. dx
hhUen,z
; we found it. now unlink it.
push ds
mav ds, ex
movax. ds: word ptr (si).Link(O)
moves: word ptr (bx).Link(O). ax
movax. ds: word ptr [si).Link(2)
moves: word ptr [bx).Link(2). ax
mov ds: (si).CompletionCode. OFCh
mov ds: [si).InUseFlag. 0
pop ds
xor ax, a~
ret
NotFound:
mov al. OFFh
ret
DriverCaneelRequest endp
292066-48

1-446

intJ

AP-331

Driver Close Socket
Assumes on entry:

DX has socket number
DS is setup
Interrupts are DISABLED
Assumes any registers may be destroyed.

even

DriverCloseSocket proc near
mov cx. word ptr SendList[2]
jcxz DriverCloseExit
les si. SendList
~do

cmp es: [si].SocketNumber. dx
Ufe
push dx
call DriverCancelRequest
pop dx
jmp DriverCloseSocket
~endif

mov cx. es: word ptr lsi] .Link[2]
jcxz DriverCloseExit
les si. es: [si].Link[O]
Horever
DriverCloseExit:
ret
DriverClosesocket endp

Code

ends

mombo_init

~egment

'CODE'

public Driverlnitialize,
no_card_message
db CR,
config_failure_messagedb CR.
iaset_failure_message db CR,

DMAPageRegisters
con fig_block
dw 15
db 48h
db BOh
db OOlOOllOb

DriverUnHook
LF, 'No adapter installed in PC$'
LF. 'Configuration Failure$'
LF. 'IA Setup Failure$',

6
7
5
1
2
3
db 87h, 83h. 81h. 82h. Bfh. Bbh. 89h. 8ah

2:
3:

; 0 •• 1: byte count
High-Speed Mode. Fifo Limit - 8
TCI mode

4:
292066-49

1-447

AP-331

db
db
db
db
db
db
db
db
db
db
db
db
db

OOh
96
OOh
OF2h
OOOOOOOOb
OOh
64
1111011lb
OOh
3Fh
87h
ODOh
OFFh

5:
6:

Interframe Spacing

7:
8:
9:

10:'
11:

12:
13:
14 :
15:
16:
17:

Minimum Frame Size
Auto Restransmit

db
db

InterruptB1t
InterruptMask
even

dd 1
OldIRQVector
InterruptMaskRegister dw 1
InterruptVectorAddress dd

Driver Initialize
assumes:
DS, ES are set to CGroup (-- CS)
DI points to where to stuff node address
Interrupts are ENABLED
The Real Time Ticks variable is being set, and the
entire AES system is initialized.
returns:

If initialization is d~ne OK:
AX has a 0
If board malfunction:
AX gets offset (in CGroup) of '$'-terminated error string

DriYerInitialize PROC NEAR
moy MaxPhysPacketSize, 1024
cld
c11
; initialize the configuration table
mov al, selected_configuration
cbw
shl ax, 1
; multiply by two
mov bx, ax
moY bx, config-pointers/bx]
mov ax, [bx] .R_IOBase
add Addr592, ax
add AddrLatchLow, ax
add AddrLatchRigh, ax
292066-50

1-448

. AP-331

add
add
add
add
add
add
add
add
add
add
add
add

L!m!tRegister, ax
DMAcmdstat, ax
DMAsnglmsk, ax
DMAmode, ax
DMAff, ax
XmtDMAaddr, ax
XmtDMAwdcount, ax
XmtDMAPage, ax
RcvDMAaddr, ax
RcvDMAwdcount, ax
RcvDMAPaqe, ax
IA_PROM-port, ax

; setup the dma registers
moval, [bxJ.H_DMAO
cbw
mav si, ax

mov cl, DMAPaqeReqisters[siJ ; qet the page register address
xor ch, ch
: save it
mov MasterDMAPage, ex
and
add
add
add
add
add

aI, 03h
MasterDMAmsk, al
MasterDMAunmsk, al

MasterDMAmodevalue, al
ax, ax
ax, ax
~dd MasterDMAaddr, ax
add MasterDMAwdcount, ax
; load the node address
lea si, node_addr
xor ax, ax

tarqets are es:s! and es:di
ah = prom address

mav ex, size node_addr

'do
mov al, ah

mov dx, L1m1tReg1ster
out dx, al
mov dx, IA_PROM-port
in aI, dx
stosb
xchg si, di
stosb
inc ah
Hoop

set prom address

read prom value
store it at es:di .
and at es:s!
increment prom address

SET UP THE INTERRUPT VECTORS
moval, [bxJ.H_IRQ
mov bx, OFFSET CGroup: Dr!verISR
call Set Interrupt Vector
292066-51

1-449

intJ

AP-331

mov dx, Addr592
mov aI, C_RST
; reset the 82592 controller

out dx, a1

qenerate 20 bit address for DMA controller from
configure block location this is necessary to
accomodate the paqe reqiater used in the PC DMA
call SetUpBuffers
; configure the master channel for cascade mode
mov al, MaaterDMAmak
mov dx, MasterDMAsnq1msk
out dx, al

disable the channel

mov aI, MasterDMAmodevalue
mov dx, MasterDMAmode
out dx, al

qet the mode reqister address
set the mode

mov ai, MasterDMAunmsk
mov dx, MasterDMAsnqlmsk
out dx, a1
; set up DMA channel for
mov al,

; enable the channel
confiqu~e

command

XmtD~sk

mav dx, DMAsnqlmsk

out dx, al

disable the channel

mav a1, RcvDMAmsk
mov dx, DMAsnqlmsk
out dx, al

disable the channel

mov dx, DHAFF
out dx, a1

; data is 'don't care

mov al, ActlveLowDREQ + ExtendedWrlte + RotatinqPriority
mov dx, DMAcmdstat
out dx, a1

mov
mov
out
mov

dx,
aI,
dx,
a1,

XmtDMAaddr
byte ptr qp_buf_start[OJ
a1
byte ptr qp_buf_start[l]

out dx, a1

mov ax, qp_bufJ'aqe
mov dx, XmtDMApaqe
out dx, al

DMA paqe value

mov ax,
mov dx, XmtDMAwdcount
out dx, al

make two transfers
292066-52

1-450

inter

AP·331

mov a1, ah

hlow
out dx, 0.1
maY 0.1, XmtDMAtx
maY dx, DMAmode
out dll, al

setup tll mode

may al, XmtDMAunmsk
may dll, DMAsnglmak
out dll, al
maY zeroes into the byte count field
of the buffer to put the 82592 into
16 bit made

les di, gp_buf.J'ointer
stosw
stosw

may dx, Addr592
may al, C_CONFIG
out dx, 0.1

configure the 82592 for 16 bit made
; issue configure command

hlow
xor ex, ex
'do
xor 0.1, al
point to register 0

out dx, 0.1

hlow
al, dx
in
and al, ODFh
emP al, 82b
%!oopne

read register 0
disregard exec bit
is configure finished1

Ufne
maY ax, OFFSET CGroup: no_card_message
ret
hndif
maY al, C_INTACK
out dx, al
maV

clear interrupt

dx, DMAff
data 1. don't care

out dx, al

maY
maY
aut
mov
out

dx, XmtDMAaddr
al, byte ptr gp_buf_start[O)
dx, al
al, byte ptr '1P_buf_start [1)
dx, 0.1

mov ax, '1P_buf.J>age
may dx, XmtDMApage
out dx, al
maY al, XmtDMAtx
maY dx, DMAmode
aut dx, 0.1

DMA page value

setup channel 1 for tx mode

292066-53

1-451

AP-331

mov ax,
mov dx,
out dx,
'slow
mav aI,
out dx,

8

XmtDHAwdcount
a1
ah
a1

mov aI, XmtDHAunmsk
mov dx, DHAsnqlmsk
out dX', a1
mov
1es
mov
rep
mov
mov
out

8i, offset cqroup' config_b1ock
di, qp_bufJlointer
ex, 18
movsb

dx, Addr592
aI, C_CONFIG
dx, a1

xor ex, cx
'do
xor aI, a1
blow
out dx, al
blow
in aI, dx
and aI, ODFh
cmp aI, 82h
'loopne

configute the 82592

point to register 0
read register .0
discard extraneous bits
is configure finished?

Ufnz

mav ax, OFFSET CGroup, confiq_failura_messaqe
ret
'endif
; clear interrupt caused by· configuration
mov aI, C_INTACK
out dx, al
; do an lA_setup
les di, 9P_bufJlointer
add.resa byte count
mov al, 06h
stosb
mov al, COh
stosb
mov si, OFFSET CGROUP, node_addr
mov ex, SIZE node_addr
rep movsb
mav dx, DHAff
out dx, al

data is don't care
292066-54

1-452

inter
mov
mov
out
mov
out

dx,
aI,
dx,
aI,
dx,

AP-331

XmtDMAaddr
byte ptr gp_buf_startIOl
al
byte ptr 9P_buf_startlll
al

mov ax, gp_bufJlage
mov dx, XmtDMApage
out dx, al
mov aI, XmtDMAtx
mov dx, DMAmode
out dx, al
mov ax,
mov dx,
out dx,
hlow
mov al,
out dx,

DMA page value

setup channel 1 for tx mode

3

XmtDMAwdcount
al
ah
al

mov al, XmtDMAunmsk
mov dx, DHAsnglmsk
out dx, al
mov dx, Addr592
mov aI, C_IASET
out dx, al
xor cx, cx
'do
xor al, al
out dx, al
'slow
in aI, dx
and al, ODFh
cmp al, 8lh
Uoopne

set up the 82592 individual address

discard extraneous bits
is command finished?

Ufne
mov ax, OFFSET CGroup: iaset_failure_message
ret
'endif
moy al, C_INTACK
out dx, al

; clear interrupt from iaset

;initialize the receive DMA channel
mov dx, DHAff
out dx, al
mov dx, RcvDMAaddr
maY al, byte ptr rx_buf_startIOl

set dma up to point to the
292066-55

1-453

inIJ

AP-331

out dx, al
mov al, byte ptr rx buf_startI1]
out dx, al

beginning of rx_buf

set rx page register

mov ax, rx_buf-page
mov dx, RcvDMApage
out dx, ax
mov al, RcvDMArx
mov dx, DMAmode
out dx, a1
mov dx,
mov ax,
dec ax
out dx,
mov al,
blow
out dx,

RcvDMAwdcount
rx_buf_length
al
ah
al

I initialize the limit register
mov aX, rx_buf_limit
sub ax, 2
mov bx, rx_buf_seqment
shl bx, 4
add ax, bx
mov aI, ab
mov dx, LimitRegister'
out dx, a1

mov aI, RcvDMAunmsk
mov dx, DMAsnglmsk
out dx, al
I 'enable the receiver
mov dx, Addr592
mov al, C_RXENB
out dx, al

compute physical address

unmask receive DMA channel

enable receives

at!

xor ax, ax
mov cx, 1
ret
Driverlnitialize endp
292066-56

1-454

AP-331

,. __ .a ..•. __ •___ ._____ •••• _* __ • __ • __ •• _._-_._-_._ •• -.-*-*---_ .. _.----_.-.-._Set Interrupt Vector
Set the interrupt vector to the interrupt procedure's address.

Save the old vector for the unhook procedure.
assumes:

cs:bx is the ISR routine

al has the IRQ level 10 •• 15
interrupts are disabled
;** •• _-----_ •••••••••

_*----**--_._.*----*------_._----*-*-----*._-----_._.---

Set Interrupt Vector proe near

I mask on the appropriate interrupt mask
push ax
xchq ax, ex

mov dl, 1
sub
shl
mov
not
mov

cl,
dl, el
InterruptBit, dl
dl
InterruptMask, dl

in al, BxtralnterruptMaskPort
and al, dl
hlow
out BxtralnterruptMaskPort, al
mov InterruptMaskReqiater, BxtralnterruptMaskPort
; also mask on level 2 of first controller

in al, InterruptMaskPort
and al, not 4

blow
out InterruptMaskPort, al
pop ax

cld
ebw
xor ex, ex
mov ea, cx
add
shl
shl
mov

al,
ax,
ax,
di,

70h - 8
1
1
ax

mov word ptr Inter 7uptVeetorAddress[01, di
mov word ptr InterruptVectorAddress[21, as
292066-57

1-455

AP-331

mov
mov
mov
mov

ax, es: [di] [0]
word ptr OldIRQVector[O], ax
ax, es: [di] [2]
ward ptr OldIRQVector[2], ax

mav ax, bx
stosw
mav ax, c.
stos"

ret
Set Interrupt Vector endp

Set up Buffers:
This routine generates the page and offset addresses for the 16 bit
DMA. It checks for a page crossing and uses the smaller half of the
buffer area for Tx and general purpose if a crossing is detected. If
no crossing is detected the general purpose/transmit buffer is placed
at the beginning of the buffer area. This routine also generates a
segment address for the receive buffer which allows the value read
from the "10 cent" latches to be used as read for the offset passed
to IPXReceivePacket. This saves same arithmetic steps when tracing
back through the rx buffer chain.

gp_length
gp_offset_adjust

dw gp_buf_size + max_rx_buf_size
dw 0

SetUpBuffers proc near
mov
mov
mov
shr
mov
shl
rol
and
add
adc
xor
sub

ax,
bx,
dx,
ax,
cx,
bx,
dx,
dx,
ax,
dx,
cx,
cx,

offset cgroup: gp_buf
cs
cs
1

3

cl
cl
0007h
bx

get upper 3 bits for page register
clear all but the lowest 3 bits
ax contains A16 •• Al of first location in buffer
if addition caused a carry add it to page
of buffer to page break
cx contains the number of wards to page break

o
cx
ax

cmp ex,

Ufae
jmp copacetic
tendif

I

it's cool, whale buffer space is in one page
292066-58

1-456

inter

AP-331

cmp cx, 9P_buf_size
tUbe
move pointer past the paqe break to discard fraqment
adjust lenqth variable to reflect shorter lenqth
both buffers will be in the same paqe, rx buf shortened

add ax, ex

sub 9P_length, cx
jmp copacetic
'endU
cmp ex, max_rx_buf_size
Ufae
mav 9P_lenqth, cx
jmp.copacetic
'endU

adjust lenqth variable, discard upper buffer fraqment
both buffers will be 1n the same paqe, rx buf shortened

now since both fraqments are usable we have to find the
actual page break. the large half will be the receive
buffer and the small half will be the gp-tx buffer.
cmp cx, (gp_buf_size + max_rx_buf_size) I 2
, Ufbe
; transmit buffer first
mov 9P_buf-paqe, dx
mav gp_buf_start, ax
mov rx_buf_start, OOOOh
next paqe
inc dx
mov rx_buf-paqe, dx
mov ax, gp_length
sub ax, ex

mov rx_buf_lenqth, ax
'else
; receive buffer first
mav rx_buf-paqe, dx
mav rx_buf_start, ax

mov rx_buf_lenqth, cx
mav qp_buf_start, OOOOh
inc dx
mov 9P_buf-paqe, dx
'end!f
jmp SetUpBuffers_exit

next paqe

copacetic:
mav 9P_buf_start, ax
add ax, gp_buf_slze
mav rx_buf_start, ax

mov
sub
mov
mov
mav

A1-A16 of qp buffer, qp buffer 1s first
allocate qp_buf at front of buffer space
rx b~ffer starts 1200 bytes in

cx, gp_length
cx, gp_buf_size
rx_buf_length, cx
rx_buf'-page, dx

9P_buf-paqe, dx

SetUpBuffers_exit:
mov ax, gp_buf_start
mav dx, 9P_buf-paqe
shr dx, 1
rcr ax, 1

shr dx,
292066-59

1-457

inter

Ap·331

rcr ax, 1
shr dx, 1
rcr ax, 1
I ax - a19 •• a4 of gp_buf
mav dx, cs
sub ax, dx
sh1 ax, 4
mov bx, gp_buf_start
shl bx, 1
and bx, Ofh
or ax, bx
; compute offset within cgroup
mov word ptr CJP_buf-pointer[O], ax
mav word ptr gp_bufJlointer.[2], cs
mov ax, rx_buf_1ength
shl ax, 1
mov rx_buf_size, ax
mov ax, rX_buf_start
mov dx, rx_bufJlage
shl ax, 1
rc1 dx, 1
push ax
xar al, a1
mov cx, 12
'do
sh1 ax, 1
rcl dx, 1
Uoop
pop ax
mov ah, eOh
sub dx, eOOh
mav rx_buf_segment, dx
mov rx_buf_first, ax
mov rx_buf_head, ax
add ax, rX_buf_size
mav rx_buf_limit, ax
mav
shl
sub
mov
ret

ax, rX_buf_start
ax, 1
ax, rx_buf_first
Logica12Physica1, ax

get the physical word
address of rx_buf
convert to byte address
save bits A19 •• A8

compute the closest segment
baundry to rx_buf
increment offset by BOOOh bytes
decrement segment by BOOh paragraphs

logical to physical mapper

SetUpBuffers endp
292066-60

1-458

Ap·331

Driver Unhook
Assumes

OS - cs - IPX segment
Interrupts are DISABLED
Assumes any registers but OS, SS, SP may be destroyed
This procedure restores the original interrupt vector
This procedure will never be called if DriverInitialize
did not complete successfully.

DriverUnhook PROC NEAR
mov dx, InterruptMaskRegister
in al, dx
or al, InterruptBit
blow
out dx, al
las bx, InterruptVectorAddress
mov ax, word ptr OldIRQVactor[O)
mov es: [bx), ax; restore old interrupt offset
mov ax, word ptr OldIRQVactor[2)
; restore old interrupt segment
mav es: [bx) [2), ax
ret
DriverUnhook endp
mombo_init ends
end
292066-61

1-459

AP-331

i********************************************··******* ***************

SMacro.inc:

A set of macros that allows assembly code to be

written in a structured fashion resemblin9 a hi9h
level lan9uage.
Written by Ben L Gee. San Jose, Ca.
~his

(408)578-1123

code may be used freely as 'long as the authors name appears

in the l1stln9.

;**********************************************************************

het (lev, 0)
het(number,O)
t'define (ifa) (
het (lev, Uev+1)
\set(number, tnumber+l)
het (level%lev, ,number)
iif (%lev eq 1) then (het(num,
%if (Hev eq 2) then (tset (num,
tif (%lev eq 3) then (het(num,
%if (%lev eq 4) then (het(num,
\if (%lev eq 5) then (het(num,

%level0lH) )
.level02H) )
Uevel'03H»
Uevel04H) )
%level05H»

f1
fi
fi
fi
fi

jna anum

"define (ifae)
'set (lev, Uev+,1)
'set (number, tnumber+l)
het (levelUev, tnumber)
\if (Hev eq 1) then (het(num,
iif (Ueveq 2) then (tset (num,
tif (Hev eq 3) then (het (num,
'if (Heveq 4) then (het(num,
Hf (Ueveq 5) then (het (num,
jnae anum

"define (lfb)
het(lev, Hev+1)
het (number, 'number+l)
%set(leveltlev, 'number)
Uf (%lev eq 1) then (het(num,
\if (Uev eq 2) then (het (num,
Uf (Uev eq 3) then (het (num,
Hf (Hev eq 4) then (het (num,
Hf (Hev eq 5) then (het(num,
jnb Hnum

Uevel0lH) )
Uevel02H»
Hevel03H»
Uevel04H»
%level05H) )

UevelOlH) )
Uevel02H) )
Uevel03H) )
%level04H) )
Hevel05H) )

fi'
fi
f1

fl
fi

f1
f1
fi
f1
fi

292066-62

1-460

Ap·331

'·define (ifbe) (
'II set (lev, Uev+l)
\set(number, 'number+1)
'set (leveHrlev, 'number)
tif (Uev eq 1) then (het(nurn,
tif (Uev eq 2) then ('set (nurn,
tif (%lev eq 3) then ('set (nurn,
tif (Uev eq 4) then (het (nurn,
tif ('lev eq 5) then ('set (num,
jnbe Unurn

'·define (ife)
het (lev, Uev+1)
\set(number, 'number+1)
het (level%lev, 'number)
tif ('lev eq 1) then ('set (nurn,
tif (Uev eq 2) then "set (nurn,
Hf (%lev eq 3) then ('set (nurn,
Hf (Uev eq 4) then (het (nurn,
Hf (%lev eq 5) then ('het (nurn,

Ueve101H)
Uevel02H)
Uevel03H)
Uevel04H)
Uevel05H)

)
)
)
)
)

Uevel01H)
Ueve102H)
Uevel03H)
Uevel04H)
Uevel05H)

)
)
)
)
)

Uevel01H)
Uevel02H)
Uevel03H)
Uevel04H)
%level05H)

)
)
)
)
)

fi
fi
fi
fi
f1

Uevel01H)
Uevel02H)
Uevel03H)
Uevel04H)
Uevel05H)

)
)
)
)
)

fi
fi

fi
fi

fi
fi
fi

fi
fi

fi
fi
fi

jnc l'nurn

'.define (ifcxnz)
'het(lev, Uev+l)
'IIset(number, 'number+1)
het (leveHrlev, 'number)
tif (Uev eq 1) then ('set
Hf (Uev eq 2) then ('set
tif (Uev eq 3) then ('set
lsif (Uev eq 4) then ('set
'if (Uev eq 5) then ('set

(nurn,
(nurn,
(nurn,
(nurn,
(nurn,

jcxz Unurn

,"define (ifnc)
'set (lev, !Uev+l)
het (number, 'number+1)
'set (level'lev, 'number)
tif (Uev eq 1) then ('set (nurn,
tif (Ueveq 2) then ('set (nurn,
tif (Ueveq 3) then ('set (nurn,
tif ('lev eq 4) then ('set (nurn,
tif (Ueveq 5) then ('set (nurn,
je Unurn

fi

fi
fi

292066-63

1-461

AP-331

%*define(ife) (
'set (lev, Uev+l)
'set (number, 'number+l)
'set (levelUev, 'number)
%if (Uev eq 1) then "set (nurn,
%if (%lev eq 2) then ('set (nurn,
%if (Ueveq 3) then- ('set (nurn,
'if (%leveq 4) then (%set (nurn,
' i f ('Hev eq 5) then ('set (nurn,

Uevel01H) )
Uevel02H) )
Uevel03H) )
'IIlevel04H»
Uevel05H»

fi

Uevel01H)
Uevel02H)
Uevel03H)
Uevel04H)
'IIlevel05H)

)
)
)
)
)

fi
fi
fi

%level01H) )
Uevel02H) )
Uevel03H»
%level04H»
UevelO5H»

fi

Uevel01H)
Uevel02H)
Uevel03H)
Uevel04H)
Uevel05H)

fi
fi
fi
fi
fi

fi
fi

fi
fi

jne Unurn

%*define (ifne)
het(lev, Uev+1)
tset(number, 'number+l)
%set (level,lev, 'number)
%if (Ueveq 1) then ('set (nurn,
%if (Uev eq 2) then- ('set (nurn,
%if (Uev eq 3) then ('set (nurn,
\if (Uev eq 4) then ('set (nurn,
%if (Uev eq 5) then ('set (nurn,

fi
fi

je Unurn

t*define (Hz)
'set (lev, 'Hev+l)
'set (number, 'lsnumber+l)
'set (leveU1ev, 'number)
Uf ('Hev eq 1) then ('set (nurn,
%if (%leveq 2) then ('set (nurn,
%if ('Heveq 3) then ('set (nurn,
%if (Ueveq 4) then ('set (nurn,
'if ('lev eq 5) then ('set (nurn,

fi
fi
fi
fi

jnz l%nurn

'*define (ifnz)
tset (lev, Uev+l)
'bet (number, 'number+l)
'"et (leve l% lev, 'number)
%if ('Hev eq 1) then ('set (nurn,
%if (Ueveq 2) then ('set (nurn,
' i f ('Heveq 3) then ('set (nurn,
%if (%leveq 4) then "set (nurn,
Uf (Uev eq 5) then ('set (nurn,
jz Unum

)
)
)
)
)

292066-64

1-462

inter

AP-331

"*define (else) (
'Hf (Hev eq 1) then (het(t, Hevel01H) ) fi
'liif (Hev eq 2) then ('set(t, %level02H) ) fi
fi
'Hf (%lev eq 3) then ("set (t, %levelO3H»
Hf (Hev eq 4) then ('set (t, Hevel04H) ) fi
'Hf (%lev eq 5) then (het(t, %levelO5H»
"set (number, "'number+1)
'set (leveUlev, 'number)
Uf (%lev eq 1) then ('set (nurn,
Uf (Hev eq 2) then (het(nurn,
Hf (%lev eq 3) then ("set (nurn,
'Hf (Hev eq 4) then ("set (nurn,
Uf (%lev eq 5) then ("set (nurn,

fi

UevelOlH»

fi

HevelO2H»

fi

UevelO3H»
UevelO4H»
%levelO5H»

fi
fi

fi

jrnp short anum
Ut:
)

"*define (elsel)
Hf (%lev eq 1) then
Uf (Uev eq 2) then
Uf (%lev eq 3) then
\if (%lev eq 4) then

("'set (t, UevelOlH» fi
!'set (t, UevelO2H»
fi
("set(t, Uevel03H) ) fi

("'set (t, Uevel04H) )
\if (Hev eq 5) then ("set(t, Uevel05H) )
"set (number, 'number+1)
"set \leveUlev, 'number)
tif (%lev eq 1) then ('set (nurn, %levelOlH)
Hf (%lev eq 2) then ("set (nurn, %level02H)
\if (%lev eq 3) then ("set (nurn, %level03H)
' i f (Uev eq 4) then ("set (nurn, %level04H)
tif (%lev eq 5) then ("set (nurn, %level05H)

fi

fi

)
)
)
)
)

fi

fi
fi
fi
f1

jrnp Unum
at:

"*define (endif)

"if (Ueveq 1) then
tif (%leveq 2) then
Uf ('lev eq 3) then
Uf (Uev eq 4) then
Uf (%lev eq 5) then
Unum:
"set (lev, %lev-I)

("set
("set
('set
('set

(nurn,
(nurn,
(nurn,
(nurn,

%levelOlH) ) fi
%levelO2H»
fi
%levelO3H»
fi
%level04H) ) fi

('set (nurn, 'llevel05H) ) fi

292066-65

1-463

intJ

AP·331

t*define (do) (
'set (lev, Uev+l)
'bet (number, "number+l)
"set (leveUlev, 'number)
tif (Heveq 1) then (tset (num,
(Heveq 2) then (het(num,
tif (Heveq 3) then ("set (num,
tif ('lev eq 4) then ('set (num,
Hf ('lev eq S) then ("set (nurn,
Unum:

UevelOlH)
Uevel02H)
Uevel03H)
Uevel04H)
Hevel05H)

)
)
)
)
)

(tset (num,
(tset (nurn,
(tset(num,
(tset (num,
(tset (num,

UevelOlH)
UevelO2H»
Uevel03H)
Uevel04H)
'level05H)

) f1

(tset (nurn,
(tset (num,
(tset(num,
(tset (nurn,
(tset (num,

UevelOlH» fi
Uevel02H) ) fi
UeveI03H» f1
UeveI04H» fi
Uevel05H) ) fi

(tset (nurn,
(tset (num,
(het (num,
(het (nurn,
(tset (num,

UevelOlH) ) fi
Uevel02H) ) fi
Uevel03H) ) fi
UeveI04H» fi
UeveI05H» fi

('set (nurn,
("set (nurn,
('set (nurn,
"tset (nurn,
(het(nurn,

'leveIOlH»
Uevel02H)
Uevel03H)
Uevel04H)
UeveIOSH)

"if

t*def1ne(forever)
Hf ('lev eq 1) then
Hf (Uev eq 2) then
"if (Uev eq 3) then
Uf (Uev eq 4) then
tif (Hev eq 5) then
jmp Unurn
tset(lev, Hev-l)

t*define (whilea)
tif (Hev eq 1) then
tif ('lev eq 2) then
tif (Hev eq 3) then
tif ('lev eq 4) then
Uf (neveq 5) then
ja Unurn
tset (lev, %lev-l)

t*define(whileae)
tif (Uev eq 1) then
tif (Uev eq 2) then
tif (Uev eq 3), then
tif (nev eq 4) then
tif ('lev eq 5) then
jae Unum
tset (lev, Hev-l)

fi
fi
fi
fi
fi

fi

) fi
) f1
) fi

t*define (whileb)

'Hf (Uev eq

1) then
(Uev eq 2) then
('Hev eq 3) then
(Uev eq 4) then
(nev eq 5) then
jb Unurn
tset (lev, Hev-l)

tif
Uf
Uf
tif

fi

)
)
)
)

fi
f1
fi

fi

292066-66

1-464

AP-331

'*def1ne(whilebe) (
Hf ('Heveq 1) then
Hf "lev eq 2) then
tif (Ueveq 3) then
'Hf (Heveq 4) then
tif (Uev eq 5) then
jbe Unurn
'set (lev, 'Hev-1)

'*define (whilee)
'Hf (Uev eq 1) t.hen
'Hf (Hev eq 2) then
tif (Uev eq 3) then
tif (Hev eq 4) then
Hf (Uev eq 5) then
je Unum
'set (lev, Hev-1)

'*def1ne(whilecxzl
Hf (%leveq 1) then
tif (%leveq 2) then
tif (%leveq 3) then
Hf ('IIleveq 41 then
Hf ('Heveq 5) then
jcxz Unum
'set (lev, Hev-1)

'*define(whilenc)
tif (Heveq 11 then
' i f ('leveq 2) then
tif (Ueveq 3) then
Hf (Ueveq 4) then
Hf (Ueveq 5) then
jne l'nurn
'set (lev, Uev-l)

'*define(whilee)
tif ('IIleveq 1) then
tif (\leveq 2) then
tit ("lev eq 3) then
tif (Ueveq 4) then
Hf ("lev eq 5) then
je Unum
"set (lev, 'lev-1)

('set (nurn,
('set (nurn,
('set (nurn,
(het (nurn,

UevelO1H» fi
'Uevel02H) ) f i
UevelO3H» f i
UevelO4H» fi
('set (nurn, 'UevelO5H» f1

('set (nurn,
('set (nurn,
('set (nurn,
('set (nurn,
('het(nurn,

UevelO1H»
UevelO2H»
Hevel03H) )
'levelO4H»
UevelO5H»

fi
fi

fi
fi

fi

('set (nurn, UevelO1HI) fi
(het(nurn, Hevel02H) I fi
('set (nurn, UevelO3H» fi
"set Inurn, 'IIlevel04H) ) fi
('set (nurn, HevelO5H» fi

("set (nurn,
("set (nurn,
('bet (nurn,
("set (nurn,
('bet (nurn,

%levelO1H»
'UevelO2H»
UevelO3H»
%levelO4H»
Uevel05H) )

f1

"set (nurn,
("set (nurn,
("set (nurn,
("set (nurn,
('het(nurn,

UevelO1H»
UevelO2H»
'levelO3H»
UevelO4H»
UevelO5H»

fi
fi
fi

fi
fi
fi

fi

fi
f1

292066-67

1-465

inter
'*define(whilene) (
tif "leY eq 1) then
tif (Uey eq 2) then
tif (Ueyeq 3) then
tif (neY eq 4) then
tif (neY eq 5) then
jne Unurn
'set (leY. UeY-l~

'*define (whilez)
tif ('ley eq 1) then
tif (Uey eq 2) then
tif (Uey eq 3) then
tif ('ley eq 4) then
tif (Uey eq 5) then
, jz l"num
""et (ley. Uey-1)

'*define(whilenz)
tif (Uey eq 1) then
tif ('Heyeq 2) then
tif (Ueyeq 3) then
..i f ('Heyeq 4) then
tif (Ueyeq 5) then
/jnz Unum

AP-331

(tset(nurn.
""et (nurn.
( ....et(nurn.
"set (nurn.
(' .. et (nurn.

UeyelO1H»
UeyelO2H»
neyelO3H»
neyelO4H»
UeyelOSH»

fi
fi
fi
f1
f1

" .. et (nurn. Ueyel01H) ) £1
(het(purn, Ueyel02H) ) £1
(' .. et (nurn, UeyelO3H» fi
" ..et (nurn. UayalO4H» f1
("set (nurn, UevelOSH) ) fi

(het(num.
(het(num,
(het(num.
("set (num,
"set (num,

UeyelO1H» fi
Uevel02H) ) fi
Ueyel03H) ) £1.
UeyelO4H» £1
UeyelOSH» fi

(het(num,
(het (num,
"set (num,
('set (num,
(het(nurn,

Ueyel01H» fi
Uevel02H» f1
'HeyelO3H» f1
'Heyel04H) ) fi
UeyelOSH» f1

(het(num,
(het(num,
('set (num,
(het(num,
('_et (num,

UeyelO1H»
Ueyel02H»
Ueyel03H»
UevelO4H»
'Hevel05H) )

' ..et(leY ... ley-l)
)

'*define(loop)
tif ('Heyeq 1) then
tif ('ley eq 2) then
tif (Uey eq 3) then
tif ('ley eq 4) then
tif ('Hey eq 5) then
loop Unum
' .. et(leY, Uey-l)

'*define Iloope)
tif (Uey eq 1) then
tif (Uey eq 2) then
tif (Uey eq 3) then
tif (UeYeq.4) then
tif ('Hey eq 5) then
loope Unum
..etlley, 'Hey-1)

f1
fi
f1
f1
fi

)

292066-68

1-466

AP-331

'*define (loopz)
' i f ('leveq 1) then
'llif ('lev eq 2) then
' i f ('lev eq 3) then
tif (Hev eq 4) then
IIdf (Uev eq 5) then
loopz Hnurn
tset(lev, 'lev-1)

t*deflne(loopne)
Hf (nev eq 1) then
Hf (neveq 2) then
tif ('lev eq 3) then
Hf ('lev eq 4) then
tif ('lev eq 5) then
loopne Hnurn
tset (lev, Uev-!)

"'*define (loopnz)
tif (%lev eq 1) then
"'if (Uev eq 2) then
'Hf (Hev eq 3) then
tif ('Islev eq 4) then
Hf (nev eq 5) then
loopnz Unum
'set (lev, Uev-1)

'level01H) )
tlevel02H) )
Uevel03H) )
Uevel04H) )
('set (nurn, Uevel05H) )

fi
fi

(tset (nurn,
(het (nurn,
(het(nurn,
(het (nurn,
(tset (nurn,

%level01H)
nevel02H)
Uevel03H)
'Islevel04H)
%level05H)

)
)
)
)
)

fi
f1
f1

('IIset(nurn,
(tset(nurn,
(tset (nurn,
(tset (nurn,
("'set (nurn,

Uevel01H)
'level02H)
'Islevel03H)
'level04H)
Uevel05H)

)
)
)
)
)

fl'

(tset(nurn,
(tset(nurn,
(tset (nurn,
(tset(nurn,

fi
fi

fi

fi

f1

fi

f1
fi
fi

)

i·····················································......

292066-69

; Relid.inc Include file eoDtaining revision information

fill' the NBMS92 driver software.

; Written by Ben L. Gee San Jose, Califomia
j •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••

"*derme(MajIll'Vellion)(I)
"*derme(MioorVellion)(OO)
..*define(VeniODOate)(890129)
"*detine(LanType)(171)

; DOl yet assigned

; 890124 use eateDded write cIma mode
; 890129 correcI BCB cancel bug
292066-70

1-467

APPLICATION
NOTE

AP-326

July 1989

PS592E-16
Buffered Adapter LAN Solution
for the Micro Channel Architecture

DARYOOSH KHALILOLAHI
TECHNICAL MARKETING ENGINEER

Order Number: 292060-001
1-468

AP-326

1.0 INTRODUCTION

2.2 Terminology

As the performance of personal computers increases,
their role in the office environment expands. This expansion, coupled with the rapid increase in the number
of personal computers, makes interconnection an indespensible option. Sharing expensive peripherals (such as
high quality printers) reduces the cost. Sharing a single
data base improves data control and security. Having
electronic mail capabilities improves communication.
Proliferation of personal computers as the workstations
of choice provides yet another new application for networking. Clusters of workstations connected in Local
Area Networks (LANs) can improve productivity by
leveraging other station's (in the same or other clusters)
computing and storage capabilities. In such an environment the network throughput of workstation nodes is
increasingly important.

In the PAL equations and schematics a "_" at the end
of a signal name indicates that the signal is active low,
"#" stands for logical OR, "&" stands for logical
AND, and "!" stands for logical inversion. In the schematics any signal name starting with the letter "L" indicates that the signal is latched on the board or that all
the signals used in generating this signal are latched.

The best choices for Local Area Networks are those
that provide reliability, low cost, ease of expansion, and
the backing of major VLSI manufacturers. In recent
years IEEE 802.3 lOBASE5 (Ethernet), IOBASE2
(Cheapernet), and Twisted Pair Ethernet (TPE)
lOBASE-T have emerged as popular choices.
The PS592E is a 16-bit nonintelligent, 32-KByte, buffered slave adapter. It interfaces IBM Micro Channel
(Personal System 2 models 50, 60, 70 and 80) computers to an Ethernet or Cheapernet based network.The
82592 LAN Controller and 82561 DMA Controller are
used to receive and transmit frames between the network and local memory. The board can perform default
cycle (zero wait-state, 200 ns) memory data transfers
on the Micro Channel. The board comes with two interchangeable network serial interface modules for
Ethernet and Cheapernet applications. A TPE network
module will be available in the near future.
A menu driven exerciser software and a NetWare driver are provided with the demo board.

2.0 OBJECTIVE
This application note describes how the Intel 82561 and
82592 are used to build a high-performance, cost-effective LAN adapter that implements the traditional buffered architecture. The last chapter describes an easy
migration to a 32-bit adapter design.

2.1 Acknowledgements
I ackowledge and thank Yosi Mazor and Joe Dragony,
of Intel's (Folsom, Calif.) Data Communications Focus
Group, and Adi Golbert of Intel's (Israel) architecture
definition group for their work in developing the hardware and the software and their contribution to this
application note.

3.0 ORGANIZATION
Chapter 4 provides an overview of the 82561 and 82592
functionality. The reader needs a basic knowledge of
these components to better understand the following
chapters. Chapter 5 provides a functional description of
the PS592E. In this chapter, the design is divided into
three architectural subsections (host interface, memory
subsystem, and network interface). PAL·equations and
schematics are broken down according to the architectural division. Chapter 6 is the software chapter; samples from the Novell NetWare driver are given. Chapter 7 provides the performance benchmarks for the
board. Chapter 8 shows how the design can be modified
(including new PAL equations) to upgrade it to a 32-bit
adapter. The appendix gives a brief description for most
of PS592E internal signals.

4.0 COMPONENT OVERVIEW
4.1 82592 LAN Controller
The CHMOS 82592 is CSMA/CD controller with a 16bit data path. It can be configured to support a wide
variety of industry standard networks, including Ethernet, Cheapernet, TPE, PCNet, and StarLan. The 82592
consists of three subsystems: parallel, serial, and FIFO.
The parallel subsystem provides an 8- or 16-bit interface to the external bus. The 82592 supports memory
transfers (at up to 16 MB/s), accepts commands from
the processor that controls the bus, and provides status
to it. The 82592 can support simultaneous transmission
and reception including autoretransmit, transmit frame
chaining, and back-to-back frame reception. The serial
subsystem consists of a highly flexible CSMA/CD unit,
a data encoder/decoder, collision detect and carrier
sense logic, and a clock generator. In high- integration
mode it supports NRZI, Manchester, or Differential
Manchester encoding and decoding at bit rates up to 4
Mb/s. In high-speed mode the 82592 is capable of 20Mb/s Manchester or NRZI encoding. The FIFO subsystem consists of a transmit FIFO, a receive FIFO,
and control logic (with prqgrammable threshold). A total of 64 bytes of FIFO can be divided between receive
and transmit. This can be done in any of four possible
combinations (16/48, 32132, 48/16, 16/16 byte resolution).

1-469

inter
4.2 82561 Host
controller

AP-326

Int~rface

and Memory

The CHMOS 82561 is a high-performance DMA controller designed to work in a tightly coupled fashion
with the 82592 in a PC AT or PS/2 adapter application.
Two independent DMA channels support transfers of
up to to MB/s to/from the local SRAM/LAN Controller. Up to 32 KB of ring buffer memory can be I/O
or memory mapped into the address space. Host accesses to the local memory can be made with zero wait
states. These accesses can be 16- or 32-bit wide. The
82561, without CPU intervention, supports all of the
82592 tightly coupled functions. It can also reclaim bad
receive buffers.
The 82592/82561 is an ideal choice for 16 or 32-bit
buffered adapters. The combination provides ease of design, high performance, low component count, low
power requirements, and competitive cost.
NOTE:
The 82560 and 82561 have similiar functionality. The
only exception is that the double-host bus mode of the
82561 supports 32-bit-wide local memory. The 82592/
82560 combination is equally suitable for a 16-bit-wide
buffered adapter design. The 82561 is used in the
PS592E design to demonstrate a 32-kB (8k X 32) buff~
ered memory implementation.

5.0 IMPLEMENTATION
The board is divided into three sections (Figure I), the
host interface, the memory subsystem, and the network
subsystem. Both the 82592 and 82561 operate on the

to-Mhz clock generated by the serial side. In the following sections of this chapter a component (designated
by its U No. on the board and the schematic) is defined
as part of a subsystem if one or more of its, output pins
are in that subsystem. The host CPU generates a request to the 82561 to access any port (including
SRAM) on the board. SRAM accesses are 16-bit wide.
All other transfers are 8-bit wide. The local memory is
accessed either directly (nonpipeline mode) or through
the data latches (pipeline mode). The data transfers between the local memory and the 82592 are 16 bits wide
and are controlled by the 82561. During DMA transfers low and high banks of memory are accessed alternately.

5.1 Host interface
This subsystem consists of the POS ID register (U2),
POS configuration register (U3), the command register
(Ul), the status register (U4), the address decoder
(U14, U25, U24, U29, U23, and US), the address latches (U9 and U12), the data latches/transceivers (U32,
U22, U26, and U16), and their control (U31 and U21),
the request generator (USP, U24, U30, U23, U21, US,
and U19), and the controller (U7) and its support logic
(U20, U23, U30, and U13).
5.1.1 ADDRESS DECODING

After power-up the host reads the POS Read Identification register of the board, and if it is what the host
expects, the host will configure the board. The ID resides in location 16 and 17 of the on-board 32-byte
PROM. The first six Bytes of the PROM hold the
board's network address. The PAL equation for the
PROM chip select is given in section 5.2. For a complete list of the ports accessed by the 82561 GCS_
output see the table in section 5.1.4.

Address
Decode
and
Control

Logic

------~

+-_,-!1~6-+1

16

I

:
I
I
I

[-------CSM;/CDL~k--------·

I
I

I
I
I

I
I
I
I
I

: L----:r---I

._--I

,
"

~--~--~ ~--~~~

:,

L-~~__~~L_-_-_-_-_-_-_-_~
__

!

,

292060-3

Figure 1. PS592E/16 Block Diagram

1-470

(
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2
4

4-

GND
TXD

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8
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15
17

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21

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22

23

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RTS.
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LPSK.

RXC.
GND
GND
RXD
+SV
CHRESET

CoN2
3
7
11
2
4
8
II

FCC

--

+13
15
10
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1
12

292060-4

inter

Ap·326

MICRO-CHANNEL
MICRO-CHANNEL
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II

IRQ3.

~

CHD
eWD. 34
CHRDYRRT
CDSFDBK_ ~
31
ON 37
DO' 38
D0338
D0440
ON 4'
CHRESET.42
RESERV",

+5V

~

CDDS,,,,,,"

OND
IRQI.

?4Fa.

CHCK. ~

DO
01
D7

43

*"
*"

OND
AI4
A'3
AI2

-

MICRO-CHANNEL
RESERVEI
RESERV.EI

+'2V
COCHRDV

CD CHRD 38

~~

CHD
AI7
AI8
A"

~

at

'IND 3,

DS18RTN'"
REFRESH_

GND

.RG07 21
OND2S1

'2V

~

PSBUS A

ADDRESS 0-23

A20
All
AI8

IRooe ~

""-1.20

ON

I

IRQD5

MICRO-CHANNEL

DO? 42

A23
A22
A2'

OND1?

...,418

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ARlO' ~
ARlO

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DO 4'

""518

PSBUS B

""318

~

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D0238

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OND

OND 13

A171.

BURST_
-12YD 23

Te.

~
~

A231
A227
A2, I
ONDa
A20 10

ADDRESS 0-23

7

AlII

AUD'!,~~~ t!.-

CDSETUP.
MAD£24

;'

~
~~ ~
48

SBHE.

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+5V

IRQ"

ClIO
CWD.
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D,
D.
04

DATA 0-15
eND
CHRESET

eND
DB
DI
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0'2
0'4
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OND

~

~

tlRQ12 S7
GN SB

:=~:;' ~
~

4
U24

*~

001 48
ONDSO
01251
D1452
D'S S3
ON S4
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+,2V

3
CND

IRata_
OND

83I1-SB

292060-5

Figure 2b. PS592E·16 Digital Assembly Schematics (Continued)

1-472

...but

,

~4ALS311

ENINT3
•

2

UMC,-

A14
A13
A12
All
AID

AS
All

T

orlolD"-

.-niP.

3
4

5

8
7
II
9
10
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74ALS1I41
10
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2D
2Q
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4Q
5D
50
liD
8Q
70
7Q
8D
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23

22
21
20
19

III
17

III
15
14

LA14
LA13
LA12
LAll
LAID
LA9

ENINTa

2[U13

ENINT12

3

IRQ3.

8

IRQ7.

8

IRQDo

74AL5311
4

~
74AL538
9

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l

12
131 U13

IRQ12.

II

----.!.! C
-----,-

~

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•
liTE.

0-23

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OC

U12

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All
A5

2 lD
3 2D
4 3D

M

540

A3
A2
AI
AD

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8D
8 7D
II 8D
10 9D
II 10D
13 C
8
7

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23

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LA7

~~

~

50

20
19

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LA3

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7Q

t-~~

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14

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:

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LCDSETUP.

Co)

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9

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r-_-,1"'0-l1

CRI

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8

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74FOO

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292060-6

~

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+ov

.......
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LA'O
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LA'2
LA'3
LA' 4

LADDRESS 0-14

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co

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ADDRESS 0-23

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292060-7

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LOCAL DATA 0-15

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292060-8

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17
18
15
14
13
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LD17
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LD23

01
02
03
04
05
08
07

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17
18

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14
13

t-+,
23
1

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18
17
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8
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2
3

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8
7
8
9
I
19

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A3
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A7

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81
82
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B5

88
B7

B8

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18
17
16
15
I ..
13
12
II

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LD25
LD2B
LD27
LD28
LD29
LD30
LD31

OIl
012
013
014
015

20~48
19
18
17
18
15
I ..
13

S2
S3
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5
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6
S6
7
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8
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A
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SWEN.

WOE.

(!)

DATA 0-15

S
LOCAL DATA 0-15

LOCAL DATA 16-31
292060-10

intJ

AP-326

. The board has one POS configuration register (address
102 h). The contents of this register are shown below.

achieved by configuring the 82561 to its pipeline mode.
The following is the PAL equation for writing into the
command register.

Bit 0: Enable/Disable the adapter ,
Bit 1-3 : Mapping window (four below and four above
1 Megabyte)
Bit 2
0
0'

Bit3

0
0
0
0

1
1
0
0

Bit 1

0
1
0
1
0
1
0

The status register is five bits wide. The three least significant bits of this read only register are the contents of
the command register. The two most significant bits are
generated by the network module and determine the
type of the network module installed.

Memory window
OCOOOO h to OC7FFF h
OC8000 h to OCFFFF h
000000 h to OOFFFF h
008000 h to OOFFFF h
FCOOOO h to FC7FFF h
FC8000 h to FCFFFF h
FOOOOO h to F07FFF h
F08000 h to FOFFFF h

Bit 4
0
0

Bit 4-7: Selective Interrupt level. Bit 4 when set selects
IRQ3_; Bit 5 selects IRQ7_; Bit 6 selects
IR,Q9_; Bit 7 selects IRQI2_.

Bit 3
0
1
0
1

Ethernet
Cheapernet
Reserved
TPE

The reserved combination is for future use.
The following is the PAL equation for reading the
status register.

The following PAL equations are for reading from and
writing to the POS configuration register.
POSRDCNF_ = I (IGCS_&ILAO&LA1&ILA2&!lORD_
&ILCDSETUP_);

RDST_ = 1(IGCS_&IL561WIN_&ILSBHL&IIORD-l;

POSLDCNF_ = I (IGCS_&ILAO&LA1&ILA2&IIOWR_
&ILCDSETUP_);

5.1.2 DATA TRANSCEIVERS/LATCHES

The upper 256 bytes of the address space (Base + 7FOO
to Base + 7FFF) are used to acccess the command
register and the 82561 register ports. All accesses in
this range must be byte accesses. An active SBHE_
(odd byte) is interpereted as a request for accessing the
command register and an inactive SBHE_ (even byte)
for 8256'1.2592 accesses.
.
The remainder of the 32-kB memory window is shared
by the local SRAM, PROM, and an optional 8-or 16kB EPROM. The sharing is accomplished by a paging
scheme implemented in a 3-bit command register. Bit 0
and I of the command register are decoded as shown in
the following table.
Bit 1

0
0
1
1

BitO

0
1
0
' 1

EPROM access
RAM access
PROM access
reserved

Bit 2 of the command register determines the mode for
accessing the buffer memory. When this bit is 0 the
host accesses to the local SRAM are made with 3 or 4
waits.tates. These are referred to as nondefault cycles in
the Micro Channel documents. When this bit is I, the
host accesses to the local SRAM are made without any
wait states. This'is referred to as default cycles. This is

Bit 3 of the command register determines the mode in
which the host accesses the local SRAM. When 0 the
access is in nonpipeline mode (wait states asserted).
When I, the access is in the pipeline mode (Microchannel default cycles). This bit, and bit 0 of the 82561 host
mode register should be set to the same value before a
memory access is attempted.
In the nonpipeline mode the data transceivers/latches
act as simple transceivers. The cycles are extended by
pulling CHRDY low until the transfer (to/from) local
memory is completed. AI, which is the second least
significant bit of host address, determines which 16-bit
bank of memory is being accessed. All non-SRAM accesses are in the nonpipeline mode.
In the pipeline mode the data transcieverllatches act as
data latches. In this mode a read ahead / write behind
operation is performed by the 82561 after every oddword access requested by the host CPU. These accesses
are to sequential locations in the local SRAM. In this
mode no wait states are asserted (default cycle on the
Micro Channel). Tlie direction of the pipeline transfer
is determined by the value of bit I of the 82561 host
mode register, therefore the direction cannot be
changed on the fly. In read cycles, after the current
transfer the 82561 updates the buffer with the contents
of the next local memory address. This is referred to as

1-478

inter

AP-326

"read ahead" (in anticipation of the next host read request). In write cycles, the data is copied from the data
latch to' the local memory after the host has finished
writing to the data latch. This is referred to as "write
behind". Pipeline transfers are made after the host requests accessing an odd word, they are double-word
wide (both memory chip selects are activated).

The following PAL equations realize the above table.
HFOU and HFI U are the unqualified HF line. They are
qualified using the host's status and command lines before they become 82561 input requests.
HFl U = «LRDWR & LCDSFDBK) & (!L561 WIN_ #
!RAM)) #
(!LCDSETUP_ & LRDWR);
HFOU = «LRDWR & LCDSFDBK) & ((!L561 WIN_ &
!LSBHE_) # (L561WIN_
& RAM & !PIPELlNE) # (L561WIN_& RAM &
LA1)
# (L561 WIN_ & !RAM))) # (ILCDSETUP_ &
LRDWR);

The control signals to the transcievers/latches are generated by the following PAL equations.
Gl_

GL

= I «IMEMREQ_ & PIPELINE & ILREAD_ &
ILAl & ICMD_)
(IXVR1_ & ICMD_)
(IIORD_ & PIPELINE & IXVR2_));

#
#

= I «IHFO_ & HF1_ & PIPELINE & ILREAD_ &
LA 1 & !CMD_)
#
(IHFO_ & HF1_ & !PIPELINE & IXVR2_ &
!CMD_)
#
(1I0RD_ & PIPELINE & !XVR2-l);

CAB_ =! (1I0WR_ & !XVRL);
CBA1_ = ! (!CMD_& PIPELINE & ILWRITE_& ILAl &
RAM & L561 WIN_ & LCDSFDBK);
CBAL = I (IHFO_ & HF1_ & !CMD_ & PIPELINE &
ILWRITL&LA1);
DIR_

SX

= I «PIPELINE & !XVR2_ & 1I0RD_)
#
(I(!HFO_ & HF1_) # !PIPELlNE) & !LWRITE_
);
= (IMEMREQ_ & PIPELINE # IIORD_ &
PIPELINE & !XVR2_);

NOTE
1. The request is qualified earlier (with status line decode) in the case of pipeline cycles. In the pipeline
mode the 82561 provides half-clock glitch protection
(on its HF inputs). In nonpipeline cycles the request is
qualified later (with CMD_), when the address decode is free of any glitch.
2. CRI, R4, and C36 are added to delay the low-tohigh transition of the signal. The 82561 spec requires
100-ns inactive time on its HF inputs. The CMD inactive time can be as short as 80 ns. During back-toback nonpipeline write cycles this can cause the 82561
to miss the deassertion of the first request. The added
circuitry guarantees that the HF inputs of the 82561
will be inactive for at least 100 ns.

5.1.5 MEMORY CONTROLLER AND ITS
SUPPORT LOGIC

5.1.3 ADDRESS LATCHES
The host address and status are latched using the falling edge of CMD_. The latches become transparent
when CMD_ goes inactive.

5.1.4 REQUEST GENERATOR
Active SO--"SI_ and CDSFDBK_ or CDSETUP_
initiate a Host request. "CYCACT" indicates an active
request. The following table shows the complete list of
Host requests to the 82561.

To access any port on the board the host generates a
request to the 82561. SO_ and SI_ are decoded to
determine if the request is a read or a write. The interrupt from the 82561 activates one of the four interrupt
lines on the Micro Channel, depending on the POS configuration. In the non pipeline mode CDCHRDY is
pulled low immediately after the cycle starts. In the
pipeline mode the CDCHRDY is high when the cycle
starts.

CYCACT LCDSETUP_ L561WIN_ RAM SBHE_ HF1_ HFO_
1
0
1
X
X
X
1
Idle
O·
0
GCS_ cycle: Command/Status
1
1
X
0
0
GCS_ cycle: ROM·
0
X
0
0
1
SRAM cycle
1
X
1
0
1
0
X
1
1
82561 cycle
0
GCS_ cycle: POS registers
0
X
X
X
0
0
• ROM refers to either PROM or EPROM. Bit 1 of the command register determines which.

1-479

inter

Ap·326

Nonpipeline Cycles

292060-1

5.1.5.1 Nonpipeline Cycles

5.1.5.2 Pipeline Cycles

In all nonpipeline cycles (SRAM or otherwise)
CDCHRDY is pulled low within 30 ns after the status
(SO_ or SI_) becomes active. It remains low until the
82561 HRDY output goes to 1, then it goes to I.

During SRAM pipeline cycles CDCHRDY stays high.
It goes low after the cycle is over (HF_ removed). This
is when the 82561 performs read ahead or write behind
operations. Read ahead means that the next double
word of data is copied from the local memory into the
data latches in anticipation of the next two requests.
Write behind means that two words of data are first
latc:hed in the data latches and then the 82561 copies
them (two words at a time) into the local memory. The
memory address in this mode is provided by the host
address register, which is incremented by one after every 82561 transfer. To change the direction of the
transfer the 82561 Host mode register should be accessed first and its bit 1 changed.

The memory address provided by the 82561 in the nonpipline mode is the same as the host CPU address except that its three most significant bits (12, 13, and 14)
are logically ORed with the three least significant bits
of the 82561 host address register. The low bank of
memory is accessed for even-word addresses and the
high bank for odd-word addresses.
BEO"':"

BE1_

=! «LRDWR & LCDSFDBK & !CMD_ &
!L561WIN_l
# ( LCDSFDBK & LRDWR & !CMD_ &
!(RAM& LA1))
# (!LCDSETUP# ));

LPIPECYC = (LCDSFDBK & L561 WIN_ & RAM &
PIPELINEl;

=! ((LRDWR & LCDSFDBK & !CMD_l &
(L561WIN_& RAM & LA1));

CYCLE_ = ! «!(LREAD_ & LWRITE_ & CMD_l &
!LCDSETUP- l #
(!CMD_ & LCDSFDBK));

1-480

AP-326

Pipeline Cycles

''--_--If

'-----h

-~

82561 HRDY

CDHRDY
292060-2

'CDHRDY is Pulled low only if the next CPU request is to the board (while the local bus cycle is being completed).
EPROMCS_ = ! (IGCS_&IIORD_&IPROM&L561WIN_);

5.2 Memory Subsystem
The memory subsystem consists of the network address
PROM (V2), the low bank of SRAM (V 17 and
V27),the high bank of SRAM (V18 and V28),the data
bus transcievers (VII and V6), an optional EPROM
(VIO), part of a PAL (VIS), and the controller (V7).
All controls are generated by the 82561 except for chip
select for the PROM and the EPROM. Note that the
second term of the "PROMCS" is for recognizing the
host's request to access the POS identification registers
that reside in locations 16 and 17 of the PROM.

1-481

PROMCS_

= I ((IGCS_&IIORD_) & (PROM&L561 WIN_ #

LCDSETUP

= I (LCDSETUP_);

ILA 1&ILA2&ILCDSETUP-l);

The data bus transceivers isolate the low- and highword data paths of the local SRAM. This is needed
because during pipeline read ahead or write behind operations the accesses to the SRAM are double word
wide.

LAuurct.::a~

(

U-I'"

LOCAL DATA 16-31
MADDRESS 0-12

.... '2
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2
23
2'
24
25
3
4
5

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NJ
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107 '11
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1015 , .
10
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103'3
102'2
10'

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LD28
LOU
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L02.
L025
LD24

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23 At'

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25
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4
5

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7

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R"D
R>oInters
LANOptionName

byte

4 dup (0)
6 dup (0)
1
;non-zero means is a real driver.
0
;address is determined at initialization
1024
;largest read data request'will handle
LANOptionName
OAAh
; Bogus Type Code
1
;transport time
11 dup (0)
Olh
;Bogus version number
OOh

0
0

;board configuration (int., 10 add., etc.)
01
configurationO

' Intel PS592E Evaluation Driver$'

db

;10 ports and ranges
configurationO dw 4 dup (0)
db 0
;memory decode
dw 0, 0
db 0
;memory decode (secondary, not used)
dw 2 dup (0)
;interrupt level
.
db 4 dup (0)
:DMA
db 4 dup (0)
db 2 dup (0)

Count

dw
db

.,

OFFFFh

o

'Self Configuring Adapter

.,

Error Counters

jVVVVVVVVVVVVVVVVVVVVVVVi

Public DriverDiagnosticTable,DriverDiagnosticText
DriverDiagnosticTable

LABEL

DriverDebugCount
DriverVersion
,StatisticsVersion
TotalTxPacketCount
TotalRxPacketCount
NoECBAvailableCount
PacketTxTooBigCount
PacketTxTooSmallCount
PacketRxOverflowCount
PacketRxTooBigCount
PacketRxTooSmallCount
PacketTxMiscErrorCount
PacketRxMiscErrorCount
RetryTxCount
ChecksurnErrorCount
HardwareRxMismatchCount
NurnberOfCustomVariables
DriverDebugEndl

LABEL

dw
db
db
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw

byte
DriverDebugEnd-DriverDiagnosticTable
01,00
01,00
0,0
0,0

o

-1
-1

jnot used

-1
-1

;not used
:not used

-1

:not used

jnot used

o
o
o

o

byte

o

(DriverDiagnosticText-DriverDebugEnd1)/2
•
292060-18

1·494

inter

Ap·326

Table 1 (Continued)

,

,

.A~AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA.

Driver Specific Error Counters
;

iVvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv;
rx errors
underruns

no_cts
no ers

rx-aborts
no-590 int
false 590 int
false-rx Tnt
false-tx- int
lost rx stop=tx
rx disb failure
tx-int count
rx -buff ovflw
tic:::tirneout

dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

DriverDiagnosticText

LABEL

byte

db
db
db
db
db
db
db
db
db
db
db
db
db
db
db

'RxErrorCount' ,0
'UnderrunCount',O
'LostCTSCount',O
'LostCRSCount',O
'RxAbortCount',O
'N0590InterruptCount',O
'False590InterruptCount',0
'FalseRxlnterruptCount',O
'FalseTxlnterruptCount',O
'LostOurReceiverCount',O
'QuitTransrnittingCount',O
'RxDisableFailureCount',O
'TxlntCount',O
'ReceiveBufferOverflow',O
'TxTirneoutErrorCount',O

db

0,0

DriverDebugEnd

LABEL

word
292060-19

1-495

AP·326

6.2 Identification
The first step in the initialization is the identification of
the system and the board. If no mismatch is found, then
the POS configuration register is read. The PS592E
identification number (assigned by IBM) is 60F9. If

mismatch is found or no card enable bit is found, then
an error message is given and the initialization routine
is exitecI. If no problem is found, then the "Set Interrupt Vector" routine is called to set the vector to the
address of the interrupt routine and save the old vect()r.
Table 2 contains the code for the identification process.

Table 2

,

.AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAftAAAAAAAAAAAAAAAAA.

'

Driver Initialize
assumes:
OS, ES are set to CGroup (== CS)
01 paints to where to stuff node address
Interrupts are ENABLEO
The Real Time Ticks variable is being set, and the
entire AES system is initialized.
No registers or flags need to be preserved
returns:
If initialization is done OK:
AX has a 0
If board malfunction:
AX gets offset (in CGroup) of '$'-terminated error string
;

.'

;

;vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvVVVVVVVVVVVVVVVVVi

Oriverlnitialize PROC
NEAR
mov MaxPhysPacketSize, 1024
cld
iFirst, find out the system we are in ....
OFC04h (3 slots)
,Model 50
OFC05h (8 slots)
,Model 60
,Model 70
?????h (3 slots)
OF800h (8 slots)
,Model 80

mov
int

ah, OCOh
ISh

cli

jc
cant get id
mov ah, eS:[bx+l)
mov aI, es:[bx+2)
cmp ax, OFC04h
jnz eight_slots
mov num of slots, 03h
jmp slots_set
eight_slots:
mov num of slots, 08h
cant get id:- slots set:
add nurn of slots, OSh
mav dl,-num_qf_slots

,model byte
,5ubmodel byte
iis it a model 50?

,model 50 just has three slots
,models 60 and 80
,for now, default to eight slots
;add OSh so we can use this in compare operation

;Next, find out which slot of the system we are in ....
mov' curr slot, D8h
next slot:
mov aI, curr slot
out POSPort,-al
mov dx, CardIDLo
in

aI, dx

cmp
je
inc

aI, IDValLo
next_byte
curr slot

cmp

curr-slot, dl

~e
card-not found
Jrnp next:::slot
next byte:
mov dx, CardIDHi
in
aI, dx
cmp aI, IDValHi
je
its_us
inc curr slot
cmp curr:::slot, dl
je
card_not_found
jmp next_slot

islot number

,Output slot 10 to Channel Position Select Reg.

~

Read the low byte of card 10.
If it matches our low byte ...
check the next byte
Otherwise, index to the next slot and check there.
Make sure we don't check beyond num_of_slots.
Check next slot.
Read high byte.
Compare with expected high byte.
If it's a match we can cont.inue.

Otherwise, index to the next slot and check there.
Make sure we don't check beyond nim_of_slots.
Check next slot.
292060-20

1-496

inter

AP-326

Table 2 (Continued)
card not found:
xor -aI, al
out POSPort, a1
;take system out of setup
mov ax, offset cgroup:no_card_message
jmp init_exit
;Next, read the POS register on the PS592E to determine setup and
;fi11 in the variables for later use ...
bogus pas data:
mav ax, offset cgroup:pos_data_error_message
jmp init_exit
its_us:
mov
in
mov
xor

dx, POSCnf
aI, dx
pas_byte, al

;save the value in a register

aI, a1

out POSPort, al
mov aI, pas byte
mov bx, 0 try_next_Ioc:
shl aI, 1
jc
set int
inc bxcmp bx, 03h
ja
bogus-pos_data
jmp try_next_Ioc
set_int:
mov aI, irq_array[bx)
mov irCLchannel, al
mov aI, pas_byte
cbw
and ax, 06h
mov bx, ax
mov ax, mem_array[bx1
mov adapter_base, ax

;if bx reaches 3 without finding a set POS bit
;then POS register was 1) not initialized or
;2) not read correctly so abort

iremove all extraneous bits

;bx will index into array of memory offsets
;get the value into ax
;set the variable
.

;set up registers then call set_vector
push di
mov aI, irq_channel
mov bx, OFFSET CGroup:DriverISR
call SetlnterruptVector
pop di
292060-21

1-497

AP-326

two configure commands. The first one puts the 82~92
into 16 bit mode and the second one does the following:
Puts the 82592 in High Speed Mode to support
Ethernet serial bit rates.
All netwo~k parameters are set up for default
Ethernet values.

6.3 Hardware Initialization
The 82561 configuration registers are set appropriately
(enable memory mapped accesses, DMA 82588 Tel,
double host bus mode, etc.). The command register is
set to read the address PROM and store its value. Then
the commimd register· is set to enable RAM access.
Then the transmit channel is set and 82592 is issued

Table 3 shows the intialization code.

Table 3

,

82561 Initialization section

;VVVVVVVVVVVVVVVVVVVVVVVVVVVVV~VVVVVVV

mov

ax, adapter_base

moves, ax

mov
%slow
mov
mov
mov
mov
mov

;reset the 82561

es:byte ptr id_reg, OOh

es:byte ptr master mode, 031h ;DMA has priority, double bus width
;late write, 0 i/o/mem wait state
es:byte ptr control_reg, Olh
es:byte ptr himm_int_mask_reg, 082h ;high assert,edge trig,drive,int on tx
es:byte ptr dma_mode_reg, 040h ; 588 TCI, discard bad frames
es:byte ptr select_reg+4, OCOh ;enable access, memory mapped,

mov es:byte ptr command_reg, 02h ;enable address PROM
mov aI, es:byte ptr mem_space
mov byte ptr ds:[di), al
;read address from PROM and store in
mov byte ptr node addr, al
mov a1, es :byte ptr mem_space+1 ; local variable "node_addr"
mov byte ptr ds:[di+l], a1
mov byte ptr node_addr[l], al
mov aI, es:byte ptr mem_space+2
mov byte ptr ds:[di+2], al
mov byte ptr node_addr[2], al
mov aI, es:byte ptr mem_space+3
mov byte ptr ds:[di+3], al
mov byte ptr node_addr[3], al
mov aI, es:byte ptr mem_space+4
mov byte ptr ds:[di+4], al
mov byte ptr node_addr[4], al
mov aI, es:byte ptr mem_space+5
mov byte ptr ds:[di+5], al
mov byte ptr node_addr[5], al
mov es:byte ptr command_reg ,Olh ;enable RAM

Receive Channel

,

Initial~zation

Receive is set up to use channel O. Receive buffer is 28K
at location zero of adapter memory

s~arting

;vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv~vvvvvvvvvvvvvvvvvvvvvvv

mov
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov

es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte

ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr

b.:..c_addrO_reg, OOh
b_c_addrO_reg+4, OOh
b_c_addrO_reg+8, OOh
la_lim itO_reg , OOh
10_limitO_reg+4, OOh
10_limitO_reg+8, OOh
up_limitO_reg, OFFh
up_limitO_reg+4, 01Sh
up_limitO_reg+8, OOh
stopO_reg, OFDh
stopO_reg+4, OlSh
stopO_reg+8, OOh

;receive buffer starts at location.
;zero in the adapter memory
;lo_limitO_reg points to beginning
;of adapter memory
;up_limitO_reg points to the last
;word of the 28K receive buffer
;stopO_reg points to the location
;two words before the end of the
;receive buffer
292060-22

1-498

intJ

AP-326

Table 3 (Continued)

,

.~~~~AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

AAAAAAAAAAAAA

Transmit Channel Initialization
Transmit is set up to use channel 1. Transmit buffer is "4k
starting directly above the receive buffer. Transmit buffer
stops 256 bytes before the end of adapter memory because the
B2561 registers and control registers are mapped there.
~vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvyvvvvvv

mov
mov·
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov

es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte

ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr

b_c_addr1_reg, OOh
b_c_addr1_reg+4, 01Ch
b_c_addr1_reg+B, OOh
lo_limit1_reg, OOh
lo_limitl_reg+4, 01Ch
lo_limit1_reg+B, OOh
up_limit1_reg, 07Fh
up_Iimitl_reg+4, OlFh
up_Iimitl_reg+B, OOh
stop1 reg, 07Dh
stop1-reg+4, OlFh
stopl=reg+8, OOh
dma_ctrll_reg, 14h

mov
mov

tx buf head, 7000h
rx=buf=head, OOOOh

;transmit buffer starts at location
;7000h (word 3BOOh) in the adapter
imemory
;lo_limitl_reg points to location
;7000h in the adapter memory
;up limitl reg points to the last
;adapter memory location before the
;561 mapping begins
;stop register points to the spot
;2 words before the 561 space
;enable channel

mov ax, OOh
mov di, rx buf head
mov cx, 3F7Fh rep stosw
;set up-for configure command
mov es:byte ptr portO, C RST
mov di, tx buf head
;the 82592 must be given a configure comma~d
xor ax, ax;with zero in the byte count field to put
stosw
;the 82592 into 16 bit mode
stosw

mov es:byte ptr portO, C_CONFIG ;configure the 82592 for 16 bit mode
xor ex, ex
wide mode wait loop:
mov es:byte ptr portO, OOh
%slow
mov aI, as:byte ptr portO
;read register 0
and al,ODFh
;disregard exec bit
cmp aI, 92h
lis configure finished?
jz
do_config
loop wide_mode_wait_loop
mov ax, offset cgroup:no_response_message
jmp init_exit
do_config:
mov es:byte
mov es:byte
mov es:byte
mov es:byte
mov es:byte
mov es:byte

ptr
ptr
ptr
ptr
ptr
ptr

portO, C INTACK
dma_ctrII_reg, 04h
b_c_addrl_reg, OOh
b_c_addrl_reg+4, OlCh
b_c_addrl_reg+8, OOh
dma_ctrll_reg, 14h

mov si, offset cgroup:config_block
mov di, tx buf head
mov cx, 9 rep movsw
mov es:byte ptr portO, C_CONFIG

xor

ex, ex

;clear interrupt in 592
;disable channel
transmit buffer starts at location
7000h (word 3BOOh) in the adapter
memory
;enable channel

;configure the 82592
292060-23

1-499

intJ

AP-326

Table 3 (Continued)
config_w~it_loOP:
mov es:byte ptr portO, OOh
%slow
iread register 0
mov aI, es:byte ptr portO
;discard extraneous bits
and aI, ODFh
,;is, configure finished?
cmp aI, 92h
conf ig_done
jz
loop config_wait_loop
mov ah, al
mov ax, offset cgroup:config_failure_m~ssage
jmp init_exit
config_done:
clear interrupt caused by configuration
mov es:byte ptr portO, C INTACK
mov es:byte ptr int_ctrl=stat_reg, Olh
do an lA_setup
mov es:byte ptr dma_ctrll_reg, 04h
mov es:byte ptr b c addrl reg, OOh
mov es:byte ptr b=c=addrl=reg+4, OlCh
mov es:byte ptr b_c_addrl_reg+8, OOh
mov es:byte ptr dma_ctrll _reg, l6h
mov
mov

;clear 561 external interrupt
;disable channel
; tra'nsmi t buf fer starts at location
;7000h (word 3800h) in the adapter
: memory
;enable channel

di, tx buf head

ax, 06h

-;address byte count

stosw

mav
mov

si, OFFSET CGROUP:node_addr
cx, 03h

rep movsw

mov

es:byte ptr portO, C_IASET

xor

ex, ex

;set up the 82592 individual address
;cx is used by the loop instruction below. this
;causes the loop to be executed 64k times max

ia wait loop:
- mov- es:byte ptr portO, OOh
%slow
mov aI, es:byte ptr portO
;discard ext'raneous bits
and aI, ODFh
is command finished?
cmp aI, 9lh
ia done
jz
loop ia=wait_Ioop
mov ah, al
mov ax, offset cgroup:iaset_failure_message
jmp init_exit
,ia done:

mov
mov

es:byte ptr portO, C_INTACK
es:byte ptr int_ctrl_stat_reg, Olh

;clear 561 external interrupt

;urunask our interrupt channel

mov
in
mov
and
%slow
out
mov

dx,
aI,
bl,
aI,

int_mask_reg
dx
int unmask
bl -

dx, al
es:byte ptr himm_int_mask_reg, 04h

;enable the receiver
mov es:byte ptr dma c'trlO reg, 3Eh
mov es:byte ptr portO, C_RXENB
xor

ax, ax

mov

ex, 1

in it exit:

;enable channel

;make sure interrupts are enabled
;return control to IPX

sti

ret
Driverlnitialize

;enable slave interrupt

endp
292060-24

1-500

inter

Ap·326

6.4 Interrupt Routines
First the current status of the machine is saved and the
interrupt mask bits are set appropriately. Then the type
of Interrupt is identified and the control is transferred

to the appropriate routine. Transmit and receive interrupts are handled by the 82561, other interrupts are
passed to the CPU. Table 4 shows the Interrupt routines.

Table 4

Interrupt Service Procedure
DMA channel 0 is the transmit channel
DMA channel

,

is the receive channel

BX is set to point to the current receive or transmic buffer head
after the cause of the interrupt has been determined.

;vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv

DriverISR
public

PROC
far
DriverlSR

pusha
push ds
push es
call lPXStartCriticalSection ;tell AES we're busy
mov ax, cs
;DS points to C/DGroup
mov ds, ax
;segment of adapter memory base
mov es, adapter_base
mov dx, int_mask_reg
;get mask state of 8259
in
aI, dx
;set mask bit for our channel
or
aI, int_mask
;write new mask to 8259
out dx, al
mov aI, EOl
out PriIntControlPort, al
;is our assigned interrupt in the secondary 8259?
cmp at_flag, Oh
jz
below 8
out SeclntControlPort, al ;if so, clear secondary too
below 8:
cld
mov aI, es:byte ptr
int_poll_loop:
;enable interrupts to be friendly
sti·
idid I receive a frame?
test aI, RxChannel
jnz rcvd_packet_jmp
;did
finish a transmit?
test aI, TxChannel
jnz sent_packet_jmp
;is there an error condition?
test aI, Ext Interrupt
jnz other 588 int
inc false-590-int
;unwanted interrupt
jmp int_exitsent_packet_jmp:
jmp sent_packet
rcvd_packet_jmp:
jmp rcvd_packet
other 588 into
inc false 590 int
mov es:byte ptr portO, C_INTACK
mov es:byte ptr int_ctrl_stat_reg, Olh
mov es:byte ptr portl, C_lNTACK
jmp int_exit
292060-25

1-501

inter

AP-326

6.4.1 RECEIVE

An interrupt on the receive channel is either due to
receiving a frame or due to hitting the stop register. The
location pointed to by the receive buffer head is exam·
ined to check if a complete frame was received. This
location is initalized to FF h (by the 82561). After receiving a frame the byte count is copied to this location.
Assuming the value read is not FF h (a full frame was
received), the routine checks the size of the frame. If
the frame is too short, too long or does not match the
phsical length, "buffer crash" routine is called. In this

routine the receive error count is increased, the DMA
channel is disabled, the DMA address registers are reprogrammed and then the channel is reenabled. If the
frame length is O.K., then routine that processes the
received frame is called. At the end the buffer head is
incremented to point to the beginning of the next frame
in the buffer. The stop register is then updated. A check
is performed to findout if a wrap around was done duro
ing the reception of the last frame. If so, then the buffer
head is appropriately modified. Table 5 shows the driver code for this section.

TableS
;

............................... ,."" .............. '''' ............. ;

;

RECEIVE EVENT

,vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv;

buffer crash:

inc

rx errors

mav
mev

eS:byte ptr portO, C_RXDISB
eubyte ptr portl, C_SELRST

mev

es :byte ptr elma_ctrIO_reg, 2Eh

mev
mav

es:byte
es: byte
eSlbyte
eSlbyte

mev

8S

ptr
ptr
ptr
ptr

b_c_addrO_reg, QOh
b c addrO reg+4, DOh
b:c::a.ddrO:reg+8, DOh
la_IimitO_reg, OOh

ibyte ptr lO_limitO_reg+4, DOh

mav
mev
mav

es:byte ptr lo_limitO_req+S, DOh
eSlbyte ptr up_limitO_r~g, OFFh
es:byte ptr up_limitO_reg+4, DISh
-maY es;byte ptr up_limitO_reg+9, ,DOh
mov es:byte ptr stopO_reg, aFOh
mev eSlbyte ptr BtopO_reg+4, OlBh
moves, byte ptr stopO _..:::eg+8, OOh
mov rx buf head, OOOOh
mov estbyte ptr dma_ctrlO_reg, 3Eh
mov es:byte ptr porta, C_RXENB
mov eSfbyte ptr portO, C_SWPI
moves: byte ptr portO, C_SWPO
jmp int_exit

false rXf
inc false_rx_int
jmp int_exit

1disable channel
;receive buffer starts at location
; zero in the adapter memory
;10 limitO reg points to beginning

; of-adapter memory
;up_limitO_reg points to the last
;word of the 2BK receive buffer
;stopO_reg points to the location
; two words before the end of the
;receive buf,fer
;enable channel

; i f not, increment counter and

rcvd-packet:
mov ax, rx buf head
;get index into rx buffer
mov rx buf~tr-; ax '
;get index into rx buffer
mav eS:byte ptr int_ctrl_stat_reg, Oeh Jack 561 interrupt
mov bx, rx buf head
;get index into rx buffer
mov ax, estword ptr mem_space(bx] ;word moves are required when accessing
mav cx, es:word ptr mem_space(bx] + 2
mav ah, cl
;make sure we really received a frame
cmp ax, OFFFFh
jz
false rx
do next frame I - mov- curr_rx_length, ax
lax contains total length of the frame buffer
; index bx to point to beginning of data
add bx, 4
;toss byte count & status
dec ax
and aI, Ofeh
;round up
;sub length of 802.3 header
sub ax, 14
cmp ax, 1024 + 64
jbe not_too_big
inc packetRxTooBigCount
jmp buffer_crash
not_too_bigl
cmp ax, 30
jae not_too_small
inc PacketRxTooSmallCount
jmp buffer_crash
not too small:
-mov- dx, eS:[bx].rx_Iength ;qet IPX length
xchg dl, dh
inc dx
and dl, Ofeh
xchg dl, dh
cmp dx, 8S: [bx] .rxyhysieal_length :same as 802.3 lengt.h
,je
fields match
jmp buffer:crash
fields match:
xchg dl, dh
at least min length minus header
cmp dx, 60 - 14
yes, continue
ja
len_ok
no, round up
mov dx, 60 - 14

292060-26

1-502

intJ

AP-326

Table 5 (Continued)
len_ok:
cmp

ax, dx

; match physical length

jz

not_inconsistent

; yes, continue

inc
jmp

HardwareRxMismatchCount
buffer crash

not_inconsistent:

%inc32 TotalRxPacketCount
call ProcessRxFrame
mav

add
add
and
add
%slow
mov
cmp
jb
sub
mov
no wrap:
- shr

ax, curr rx length

ax, 10 - ax, 3
aI, OFCh
rx_buf_head, ax

; Double Word Increment
;get original byte count back
;add overhead bytes to receive length
;round up to nearest. double word
; boundary
;rx_buf_head points to next frame buffer

ax, rx buf head
ax, 7000h no_wrap
ax, 7000h
rx_buf_head, ax

ax, 2
;convert byte address to doubleword address
;calculate the stop value
ax, 4
;check for negative value (stop was at 1st 16 bytes)
jns set_stop
;mask to generate required stop value
and ax, IBFFh
set_stop:
mov new_s top_va I , ax
;load bx for use as pointer
mov bx, rx buf head
;get byte count LSB
mov ax, word ptr es:mem_space[bx]
mov cx, word ptr es:mem_space[bx] + 2 ;get byte count MSB
;combine them in cxi
mov ch, al
mov ax, new stop val
mov es:byte-ptr stopO_reg, al
;update the stop register
mov es:byte ptr stopO_reg + 4, ah . ;by writing new values
mov es:byte ptr stopO reg + 8, OOh ;to all three bytes
cmp cx, OFFFFh
;Is there another received frame to be
je
int_exit
; processed?
mov ax, cx
;receive loop expects count to be in ax
jmp do_next_frame
sub

int exit:
-push cs
pop ds
finish_exit:
moves, adapter_base
mov aI, es:byte ptr int_ctrl_stat_reg
test aI, himm_int_mask
;check for new interrupt
;if we do, service it
jnz int_pending
;mask interrupts so we can unmask our
cli
;channel without reentrancy problems
mov dx, int_mask_reg
;get mask state of 8259
in
aI, dx
;clear mask bit for our channel to
and aI, int_unmask
;enable new interrupts from adapter
%slow
;write new mask to 8259
out dx, al
IPXEndCriticalSection
;tell
IPX it can run
call
;restore machine state
pop es
pop ds
popa
ireturn
iret
too_big:
inc PacketRxOverflowCount
jmp int_exit
int_pending:
jmp int_poll_loop
292060-27

1-503

inter
S.4.2 TRANSMIT

After acknowledging the 82561 transmit interrupt, the
routine checks if the transmit flag is set. If it is set,
th,e routine reads the status registers of the 82561. If the
transmit OK bit is not set, there was a problem with

the transmit. In this case, other bits are read to deter·
mine the exact cause of the problem so that the appropriate action can take place. If transmit was successfull
the routine updates the retry count and returns the TX
EeB to IPX with a good completion code. Table 6
.
shows the code for transmit.

TableS

TRANSMIT EVENT
:vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv:
sentJ>acket:
eli
mov eS:byte ptr int_ctrl_stat_reg, 30h lack 561 interrupt
cmp tx active flag, 0
bogus tx Tnt
;shouldn't have been transmitting
jz
inc tx lnt count
mov al~ es,byte ptr statl_588_reg
mov result!, a1
mov aI, eS:byte ptr stat2_588_reg
mov result2, a1
test aI, 20h
jz
tx error
iextract the total number of retries from
mov a1-; resultl
;the status register and add to retry count
and ax, OFh
add RetryTxCount, ax
jstatus ; 0, good transmit
xor ax, ax

FinishUpTransmit:
les si, send list
cmp es:byte ptr [sil.transmitting, TRUE
jnz not active
mav es:-[si].completion_code, a1
mav ax, eSI word ptr [si].link
mav word ptr send_list, ax
mev ax, es: word ptr [sil.link + 2
mav word ptr send_list + 2, ax
;finish the transmit
moves: [si].in_use, 0
call IPXHoldEvent
not active:
,
-push cs
pop ds
mav cx, word ptr send_list + 2
mav tx active flag, cl
jcxz int_exit_Jmpl
maves, ex
;segment af next SeB in list
mav si, word ptr send list
;offset af next seB in list
call start send
jmp finish_exit

int exit jmp1:
-jmp -int_exit
bagus_tx.:.,.int:
inc false tx int
jmp int_exi ttx_errar:
test resultl, 20h
;Max collisions??
jnz QuitTransmitting
test result2, Olh
~Tx underrun??
jz
lost ets
inc underruns
mav aI, TransmitHardwareFailure
jmp FinishUpTransmit
lost ct.:
test result2, 02h
;did we lose clear to send??
jz
lost crs
inc no cts
mov al~ TransmitHardwareFailure
jrnp FinishUpTransmit
lost ers:
test result2, 04h
;did we lose carrier sense??
jz
late coll
inc no crs
mav al~ TransmitHardwareFailure
jmp FinishUpTransmit
292060-28

1-504

inter

AP-326

Table 6 (Continued)
late coll:
test result2, OSh
;did we have a late collision?
jz
hmmm
inc no ers
mov al; TransmitHardwareFaiIure
jmp FinishUpTransmit
hmmm:
mov aI, TransmitHardwareFaiIure
jmp FinishUpTransmit
QuitTransmitting:
add RetryTxCount, OFh
inc stop_tx
mov aI, TransmitHardwareFailure
jmp FinishUpTransmit
DriverISR

endp
292060-29

1-505

inter

AP-326

LAN

/

Under / r r Test

IBM PS/2T1ot
Model 50 I!c 70
with
PS592E-16
Adopter

Novell 286A
8-MHz,OWS
with
PC5B6E
Adopter

I

I

.. Novell Perform2 Ver 2.3
~ File Server: Novell 286A with PC586E Adopter
.. Workstotlon Node: IBM PS/2 Model 50 ond io (One Node on Network)
Doto Throughput of Workstotlon Node to Flleserver

.....
o
z

~
a::

e.....a::

PS/2
Model 50
PS/2
Model 70

Q.

300

350

Kilobytes per Second

292060-30

, Figure 3. PS5292E/16 Performance Benchmarks

7.0 PERFORMANCE

8.0 PS592E-32

The PS592E provides very high performance compared
to many commercial adapters. The result of the performance experiment is shown in Figure 2. The PS592E
can perform default cycles (200 ns) on the Micro Channel. This is done when the board is configured for pipeline mode. Without this feature each host access would
take about 500 ns, resulting in less efficient use of the
host bus bandwidth. In addition to reducing the host
bandwidth consumption, performing the default cycles
(200 ns) on the Micro Channel improves the network
performance by about 10% over non-default cycles.
The experiment was performed using the standard
Perform2 with one station and the file server (no collision).

This chapter shows how the'PS592E-16 design can be
modified to provide an adapter for the 32-bit Micro
Channel I/O slots (Models 70 and 80). The design is so
similar to the 16"bit design that only the differences
. (PAL equations and schematics) are specified.

8.1 Architecture
The data path between tlie Micro Channel and the data
latches/transceivers is 32-bit wide. The low word (DOD15) goes to U32 and U22 and the high word (D16D31) goes to U26 and U16. The component count is
the same as in the 16-bit design. The complete set of the
PS592E-32 schematic is given.

1-506

AP·326

8.2 Schematics

8.3 PAL Equations

Besides the 32-bit data path, two other minor modifications are made to the schematics.
1. U5 is changed from a 3-input NAND gate to a 4-input NAND gate. Half of it is used to generate the
CDDS32_ signal (indicating 32-bit data transfers)
to the Micro Channel. An extra input is added to the
CDDS16_logic (PIPELINE_, pin II ofUt). Only
the memory transfers in the pipeline mode can be 32bit wide. Nonpipeline memory transfers remain 16bit wide on the low word (DO-DI5), and non-memory transfers remain 8-bit wide on the low Byte (DOD7).
NOTE:
1. Our Netware driver uses the pipeline mode to transfer the frame data and nonpipeline mode to transfer
other frame information (byte count, status, etc.).
Since most of the time is spent in transfering frame
data, the restriction (pipeline mode for data transfer
only), does not reduce performance. However, if a designer would like to extend the 32-bit transfers to nonpipeline cycles he can do so. To do this, (BEO_ #
BEI_) and (BE2_ + BE3_) should be generated
on the board and latched (BEn_ are the Byte enable
signals on the Micro Channel).
.
2. CBA2_ signal (which was generated in U31) is removed and CBAI_ is renamed CBA_. CBA2_ was
the latch signal for the high word data latch/transciever (U26, U16) in the 16-bit version. It is not needed
because the data is latched 32 bits at a time. The extra
pins of U31 are used to generate SWEN_ in the PAL.
SWEN_ is the enable signal to the local bus transceivers (U6 and Uti).

8.3.1 HOST REQUEST

The equation for unqualified HFO is modified. A request to the 82561 is generated each time the host CPU
requests access to local memory (double word). Thus,
LAI is removed as the qualifier.
HFOU

=

((LRDWR & LCDSFDBKl & ((!L561WIN_ &
!LSBHE_l # (L561WIN-ll #
(ILCDSETUP_ & LRDWRl;

8.3.2 DATA LATCH/TRANSCEIVER CONTROLS

CBAI_ is renamed CBA_, and LAI is removed from
the equation, because the data is latched 32 bits at a
time (independent of LAI). CBA2_ is removed.
CBA- = ! (!CMD_ & PIPELINE & !LWRITL & RAM &
L561WIN_ & LCDSFDBKl;

For the same reason, data latch/transciever enable signals are modified to be independent of LA I during
pipeline memory accesses.
G1_ = ! ((!MEMRE~ & PIPELINE & ILREAD_ &
!CMD-l
(!XVR1_&!CMD_l
(IIORD_ & PIPELINE & !XVR2_»;
GL = ! ((!HFO_ & HF1_ & PIPELINE & !LREAD_ &
!CMD_l
(!HFO_ & HF1_ & !PIPELINE & !XVR2_ &
ICMD_l
(IIORD_ & PIPELINE & !XVRL»;

3. Only the low 24 bits of address are decoded (no
change from the PS592E-16). If the software code is
that of the 80386, then the higher 8 bits should also be
decoded and the result should be latched.

1-507

#
#

#

#

+sv

-

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.01"F -: .01"F
:-0.01"F-: .01"F
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0.01UF-:
... ce ' I' cIa ~ ... Cll' ... C12'

0.01uF-:
C13 '

0.01uF
0.01uF
0.01uF
C14 ... ,
C15 ;; ...
C18.'

0:01uF
C17

(

DND

"

0.01uF-: :-0. 01 uF-: 0.01uF
0.01uF-: :-0.01uF :-0.01uF
Cl .... ...
020' "
022' I'
023'
Cl.' I'
021'" I'

!!

+IIV

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Gl

cg

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024

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i

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4
8

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-1 4a
D"50
01 51
12VO 52
RESERVED
saHE

GND

51.
t.I 10.
+12V

~
~~

..'to. I;ji'*"

~
:~:~~~
CHCK ~

+5V

so. 32

11001 ..
110015

GND
A23
A2.
A21

eND ~
IRQO. .
IAQOII ~
.RQ07 • a
GND21

-12V

MICRO CHANNEL

A

A1815
""5111
ON017
A14111

PSBUS B

ARBO
ARBOI ~

PSBUS

GND

aND 13

A17, ...

A3

..oLo

REFRESH.

~
~

A231
A2'7
A211
GIlD.
A2010

PREEMPT...

-

i:1-

eND
IRQ12.

OND

830-158

292060-32

Figure 4. PS592E·32 Digital Assembly Schematics (Continued)

1-509

(
MICRO-CHANNEL
RES.
RES •
~
RES.
~
RES.
GNO
~
016
64
017
65
016
66
GNO
022
68
023
69
RES.
~
GNO
~027
72
028
73
74

g..

."

iFi
c

;

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en
CD
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2!
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o

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,

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PSBUS B ~~~

()

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3

01129
A30
A31
GNO
RES.
RES.

In

o

3

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(1)

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-

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3
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en

.

ADDRESS 0-23
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()

III
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0

a

5

4D

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50
7 eo
B 70
9 eo
10 90

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2Q

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22
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20

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17

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LA' 2
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50

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74ALS38
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13

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IR:012.

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LSBHE.

A2
A1
NJ

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LA7
LAO

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1..A3
1..A2
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2

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4

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20
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1
2

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4

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2

3

,

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-

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----

SSHE·

R

74ALS3e
ENINT3

18

LCDSFOBK

LCDSETUP.

W

[ADDRESS 0 , 4
LRE'AO •
LWRITE_

'4
1N4148

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292060-35

1

HFO.
HFh

IOWR_
CSH·

•

11

ClIO.

18

IN

3

PIPELINE

LREAD.

4

LWRITE·

~

e

>

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10
13
12
II

N

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en

en

LAI4
LAI3
LAI2
LAII
LAIO
LAII

UI
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m

~

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!2

LAII

!!!!.

LA7
LA8
LAS
LA4

~

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en
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LA2

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intJ

AP-326

APPENDIX A
Signal Name
ABOVE

Description
POS register bit that determines
mapping below or above 1 Meg.
data latch clock (direction: local
memory to latch)
data latch DO-DI5 clock (direction: host to latch)
data latch D16-31 clock (direction: host to latch)
local SRAM chip selects (low
and high banks)
CDEN
POS register bit for card enable
active host cycle enveloping sigCYCACT
nal
partial active host cycle envel'
oping signal
direction signal for data latchDIItes/trasceivers
ENINT3,7,9,12
POS register bits determining
the selected interrupt signal
EPROMCS_
EPROM chip select signal
general chip select (output of
82561)
data latch DO-DI5 ,transceiver
tristate enable
data latch D16-D31 transceiver
tristate enable
HFOU,HFIU
unqualified, active high host request signal
active low host request signals
to the 82561
IORD_I MWIt- read from non-SRAM port or
'write to SRAM (output of
82561)
IOWItwrite to non-SRAM port (output of 82561)
INTOUT
Interrupt output of the 82561

Signal Name
LAO-LAI4
LCDSETUP_
LCDSFDBK

, Description
latched host address lines
latched card set up signal
latched card select feedback signal
load command register
LDO-LD31
local data bus
loopback signal
LPBKLPIPECYC
latched pipeline cycle signal
LREAD,LWRITE
latched read and write signals
latched byte high enable
L56IWIN_
latched 82561 subwindow
MAO-MAI2
memory address lines (output of
82561)
MEMREQ_
memory request' from the host
memory output enable (output
of 82561)
POSLDCNF_
load POS configuration register
POSRDCNF_
read POS configuration register
command register bit determinPROM
ing PROM vs EPROM paging
PROMCS_
PROM chip select
command register bit determinRAM
ing RAM vs. ROM paging
read f!om the status, register
unlatched read or write (decode
RDWR
of SO_ and SI_)
SX
select between latched and real
time data
transceiver!latch enable signals
(output of 82561)
561BEO_, 56IBE1_ low word and high word enable
signals (input to 82561)
IORDY output of 82561
561IORDY

1-518

APPLICATION
NOTE

AP-328

August 1989

PC592E
Buffered LAN Adapter Solution
for the IBM PC-XT and PC-AT*

DARYOOSH KHALILOLAHI
TECHNICAL MARKETING ENGINEER
TSVIKA KURTS
SYSTEM VALIDATION GROUP

'IBM, PC-XT and PC-AT are trademarks of International Business Machines.

Order Number: 292063-001
1-519

inter

AP-328

1.0 INTRODUCTION

2.2 Terminology'

In recent years IBM PC·AT*s and compatibles have
become the most popular personal computers. Judged
by the amount of adapter hardware and application
software developed for them, the trend seems likely to
continue in the near future. Introduction of the Extend·
ed Industry Standard Architecture (EISA) is another
reason supporting this prediction.

The following table shows the terminology used in this
document.

The role of local area networks (LANs) expands as the
role of the personal computers in the office environ·
ment increases. Some examples of the benefits provided
by networking are sharing expensive peripherals (to re·
duce the cost); sharing a single data base (to improves
data control and security), and having electronic mail
capabilities (to improve communication).
The best choices for Local Area Networks are those
that provide low cost, reliable operation, ease of expan·
sion, and the backing of major VLSI manufacturers.
The 82592/82560 is an ideal choice for 16·bit, buffered
adapter applications. The high level of integration re·
duces the component count and the design cycle. The
combination provides high performance and competi·
tive cost.
The PC592E is a 16·bit, nonintelligent, buffered slave
adapter design. It interfaces the IBM PC·AT or PC·
XT* or compatibles to an Ethernet network. The 82592
LAN Controller and 82560 host interface and DMA
Controller are used to receive and transmit frames be·
tween the network and local memory (16 kB). The
PC592E can perform zero wait state memory data
transfers on the PC bus. The design permits the use of
interchangeable network serial interface modules for
Ethernet*', Cheapernet and TPE applications.

2.0 OBJECTIVE
This application note demonstrates how to use the Intel
82560 and 82592 to build a high·performance, cost·ef·
fective PC·AT LAN adapter that implements the tradi·
tional buffered architecture.

2.1 Acknowledgements
We acknowledge and thank Yosi Mazor and Joe Dra·
gony, of Intel's (Folsom, Calif.) Data Communications
Focus Group, for their work in developing the hard·
ware and the software and their contribution to this
application note.

Symbol

#

&

Description
at the end of a signal name indicates
active low
logical OR
logical AND
logical INVERSION

3.0 ORGANIZATION
Section 4 provides an overview of the 82560 and 82592
functionality. The reader needs a basic knowledge of
these components to better understand the following
chapters. Section 5 provides a functional description of
the PC592E. In this section, the design is divided into
three architectural subsections (host interface, memory
subsystem, and network interface). PAL equations and
schematics are broken down according to the architec·
tural division. The last section provides the perform·
ance benchmarks for the board. Appendix A provides a
brief description of most PC592E internal signals. Ap·
pendix B provides the complete sets of PAL equations.

4.0 COMPONENT OVERVIEW
4.1 82592 LAN Controller
The CHMOS 82592 is a CSMA/CD controller with a
16·bit data path. It can be configured to support a wide
variety of industry standard networks, including Ether·
net, Cheapernet, TPE, PCNet, and STARLAN***.
The 82592 also supports Deterministic Collision Reso·
lution (DCR) applications. The 82592 consists of three
subsystems: parallel, serial, and FIFO. The parallel
subsystem provides an 8· or 16·bit interface to the ex·
ternal bus. The 82592 supports memory transfers (at up
to 16 MB/s); it accepts commands from the processor
that controls the bus and provides it with status infor·
mation. The 82592 can support simultaneous transmis·
sion and reception including autoretransmit, transmit
frame chaining, and back·to·back frame reception. The
serial subsystem consists of a highly flexible CSMA/
CD unit, a data encoder/decoder, collision detect and
carrier sense logic, and a clock generator. In high inte·
gration mode it supports NRZI, Manchester, or Differ·
ential Manchester encoding and decoding at' bit rates
up to 4 Mb/s. In high speed mode the 82592 is capable
of 20·Mb/s Manchester or NRZI encoding. The FIFO
subsystem consists of a transmit FIFO, a receive FIFO,
and control logic (with programmable threshold). A to·
tal of 64 bytes of FIFO can be divided between receive
and transmit.

'IBM, PC·AT and PC·XT are trademarks of International Business Machines Corp. '
"Ethernet is a trademark of Xerox Corp.
"'STARLAN is a trademark of AT&T.

1·520

!

infef

AP-328

4.2 82560 Host Interface and Memory
Controller

5.1 Hardware Configurable Options

The CHMOS 82560 is a high-performance DMA controller designed to work in a tightly coupled fashion
with the 82592 in a PC-XT, PC-AT or MCA adapter
application.
Two independent DMA channels support a transfer
rate of up to 10 MB/s to/from the local SRAM. Up to
16 kB of ring buffer memory can be I/O or memory
mapped into the address space. Host accesses to the
local memory can be made with zero wait states. These
accesses can be byte or word wide. The 82560 implements all of the 82592 tightly coupled functions: back
to back frame reception, bad receive buffer reclaimation, auto retransmit upon collision, and transmit
chaining.

5.0 IMPLEMENTATION
The board is divided into three sections (see figure 1),
the host interface, the memory subsystem, and the network subsystem. Both the 82592 and 82560 operate on
the IO-MHz Ethernet clock generated by the serial side.
In the rest of this section a component (designated by
its unit No. on the board and the schematic) is defined
as part of a subsystem if one or more of its output pins
are in that subsystem. To access any port on the board
(including SRAM), the host CPU generates a request
to the 82560. When in a 16-bit slot the board supports
16-bit hosts (PC-AT), otherwise it supports 8-bit hosts
(PC-XT). To enable the board the most significant bit
(bit 3) of the command register should be set to 1. In
the 16-bit configuration SRAM accesses can be word
(zero wait state or nonzero wait state) or byte wide
(nonzero wait state). All other transfers (non-SRAM)
are byte wide. In the 8-bit configuration SRAM accesses can be either with zero added wait state (pipeline
mode) or with 3 to 4 added wait states (nonpipeline
mode). The reader is referred to the table and listing in
Section 5.2.3 for a complete set of host memory cycles.

The board has seven jumpers and one switch. These can
be set to change the board configuration.
5.1.1 MEMORY MAPPING WINDOW

E 1 through E6 are used to select the lower portion of
the address window. The letter E followed by a number
refers to a unique jumper node. These two jumpers are
used to select the lower portion of the memory address
window. El, E2, E3 select the least significant bit
(MAPO) of the three bit address selector. E4, E5, E6
select the next bit (MAP1).
E7 through E9 select the most significant bit (MAP2)
of the address selector. MAP2 determines the upper
portion of the address window; namely below I Megabyte or above 1 Meg. Together with MAPO and MAP1,
these three jumper selections determine which one of
the eight 16-kB windows of host memory address is
chosen.
a) Below 1 Megabyte
memory window
OCOOOO to OC3FFF
OC8000 to OCBFFF
000000 to 003FFF
008000 to OOBFFF

MAP2
0
E9/E8
0
E9/E8
0
E9/E8
0
E9/E8

MAP1
0
E6/E5
0
E6/E5
1
E4/E5
1
E4/E5

MAPO
0
E3/E2
1
E1/E2
0
E3/E2
1
E1/E2

MAP1
0
E6/E5
0
E6/E5
1
E4/E5
1
E4/E5

MAPO
0
E3/E2
1
E1/E2
0
E3/E2
1
E1/E2

b) Above 1 Megabyte

The data transfers between the local memory and the
82592 are 16 bits wide and are controlled by the 82560
DMA channels.

1-521

memory window
FCOOOO to FC3FFF
FC8000 to FCBFFF
FOOOOO to F03FFF
F08000 to FOBFFF

MAP2
1
E7/E8
1
E7/E8
1
E7/E8
1
E7/E8

(factory
default)

intJ

AP-328

address decoder (U1 and V2) and its latch (V4); the
data latches/transceivers (V8 and V9), the high memory bank to D7 -0 data transceiver (VlO), and their control (V5); the host request generator (U2); and the
memory and peripheral controller (U6).

5.1.2 INTERRUPT
A switch is used to determine the interrupt line selected
as shown below.
PC bus Interrupt
Switch position
IROp
IR07
IR09
IR012

1 (factory default)

2
3
4

5.2.1 .cOMMAND AND STATUS REGISTERS
The command register is four bits wide.

3

I

5.1.316- OR a-BIT HOST SUPPORT

Jumper E16 through E18 is used to select the source of
the BHE_. In a 16-bit sI0t'E16/E17 should be selected. This connects the SBHE_ from the PC bus to the
BHE_ of the board. In an 8-bit slot E18/E17 should
be selected. This connects the inverted SAO to the
BHE_ of the board. The factory default is E16/E17
(PC-AT).

2

BOARDEN

I

PIPELINE

I

1

0

PROM

RAM

After power up; or reset, the board is disabled. When
disabled, the board recongnizes only host requests to
access its command and status registers.
Bit 0, Bit 1: Determine the memory port being accessed.
Bit 1
Bit 0

o

PCXT is a signal on the board that can be read by the
host (through the status register) to determine if the
board is plugged into a 16- or 8-bit slot. This signal is
connected to the GND pin of the D connector (pin 18)
of the 16-bit I/O channel. A l-kohm pull-up resistor
connects the node to the + 5-V supply. Therefore in a
16-bit slot PCXT will be read as 0, otherwise it will be
read as 1.

o

o

1

o

1

EPROM access
RAM access
PROM access
Reserved

Bit 2: Determines the mode for accessing the buffer
memory. When 0 the host accesses to the local
SRAM are made with added wait states. When I,
and the 82560 is configured for the pipeline
mode, the host accesses to the local SRAM are
made with no added wait states '(pipelined data
transfers). This bit and the bit 0 of the 82560 host
mode register should always be set to the same
value before an SRAM memory access is attempted.
Bit 3: Is the board enable bit. After power up, or reset,
this bit should be set to 1 in order to access the
on-board ports (SRAM, ,PROM, EPROM, 82560
regisiers, and 82592 registers).

5.1.4 CLOCK SOURCE
Jumper E19 , E20, E21 selects the source of the clock
for the 82592 and the 82560.
Jumper position
Clock source
E19/E21
lO-MHz serial clock from the serial
unit connected to TXC of 82592 (fac,tory default)
E20/E21
external crystal connected to Xl of
82592

The following is the PAL (VII) equation for writing to
the, command register.

= !( !GCS_ & !L560WIN_ & !IOWR_l

5.2 Host Interface

LDCMD_

This subsystem consists of the command register (U4),
the status register (U12), and their control (U11); the

The status is seven bits wide read only register.

6

5

4

3

2

PCXT

MODT1

MODTO

BOARDEN

PIPELINE

1-522

o
PROM

RAM

intJ

AP-328

The four least significant bits are the contents of the
command register.

!L560WIN_

= (SAI3

Bit 4, Bit 5: Are generated by the network module and
determine the type of network module installed.
Bit 5
Bit 4
o
0
Ethernet
o
Cheapernet
Reserved
o

!MEMCSI6_

= ( !LSBDEC_

&

SAl2

&

SAll

« SAIO « SA9 & SA8 «
SA7)

TPE

The reserved combination is for future use.
Bit 6: Is read to determine if the board is plugged into
an 8- or 16-bit slot. In a 16-bit slot a 0 is read,
otherwise a I is read.
The following is the PAL (Vll) equation for reading
the status register.

RDST_

= !( !GCS_

& !L560WIN_ & !IORD_)

& LMSBDEC
RAMEN & L560WIN_ &
!SAO & !BHE_)
enable (ZEROWS_) = (RAM & !LSBDEC_ &
LMSBDEC & BOARDEN &
PIPELINE « L560WIN_)
ZEROWS_
= !L560IORDL
&

5.2.3 DATA TRANSCEIVERS/LATCHES
Bit 2 of the command register determines the mode in
which the host accesses the local SRAM.
In the non pipeline mode the data transceivers/latches
act as simple transceivers. The cycles are extended by
pulling IOCHROY low until the transfer to/from local
memory is completed. All non-SRAM accesses are in
non pipeline mode.

5.2.2 ADDRESS DECODER
The highest bits of the address (LA23 - 20) are decoded
in V2. The output is the MSBOEC signal, which is
latched on the falling edge of the BALE in V4. The
latched signal (LMSBOEC) is input to the other PAL
(VI). SA19-14 are decoded in this PAL for the lower
portion (within I Megabyte) of the address mapping.
The output is LSBOEC.
Three signals from the board provide the handshake
required by the host:

IOCHRDY. MEMCSI6_. and ZEROWS_.
The relevant PAL equations (of VI and V2) are given
below. The reader is referred to the appendix A for the
decription of internal signals.

RAMEN
MSBDEC

= (RAM & BOARDEN)
= ( !LA20 & !LA21 &

!LA22

&

!LA23 & !MAP2) #

(LA 20 & LA21 & LA22 & LA23
& MAP2)

!LSBDEC_ = ( (SAI9 & SAl8 & !SAl7
!SAI6 & !SAI5 & !SAI4
!MAPI & !MAPO) #
(SAI9 &
& SAI5
MAPO) #
(SAI9 &
& !SAI5·
!MAPO) #
(SAI9 &
& SAI5
MAPO))

&
&

SAl8 & !SAI7 & !SAI6
& !SAI4 & !MAPI &
SAI8 & !SAl7 & SAl6
& !SAI4 & MAPI &
SAl8 & !SAI7 & SAl6
& !SAI4 & MAP I &

In pipeline mode the data transciever/latches act as
data latches. In this mode a read ahead or write behind
operation is performed after every host request to the
82560. These accesses are to sequential locations in the
local SRAM. In this mode no wait states are asserted.
The direction of the pipeline transfer is determined by
the value of bit I of the 82560 host mode register. In
read cycles, after the current transfer, the 82560 updates the buffer with the contents of the next local
memory address. This is called "read ahead" (in anticipation of the next host read request). In write cycles the
data is copied from the data latch to the local memory
after the host has finished writing to the data latch.
This is called "write behind."
In the 8-bit configuration, during odd byte memory accesses the transceiver VIO becomes transparent. Thus
the data path would be from/to the high bank of
SRAM (V13), through UIO, to the low byte of data bus
(07-00).
In the non pipeline mode V8 and V9 serve as simple
data transceivers. All non-SRAM accesses use the even
byte (07 - 00). In the 16-bit configuration the value of
SAO and SBHE. determines which bank of memory (or
both) should be accessed.
The following table shows different types of memory
cycles and the expected value of the transceiver and
data latch (74ALS646) control signals. B is the host
side and A is the local bus side. When SX is I, stored
data is selected. When 0, real time data is selected. X
stands for don't care.

1-523

inter

AP-328

cycle Pipeline PCXT BHE_ SAO MEMW_ MEMR_ G1L G1H_ G2_ CBA1_ CBA2_ SX
1
1
1
0
0
0
0
1
0
0
0
0
1
2
1
0
0
1
1
0
0
1
0
0
0
1
X
X
1
0
3
0
0
0
4
0
0
1
X
1
0
0
0
X
5
0
0
0
0
X
X
0
0
1
0
0
1
0
1
6
0
1
0
1
7
1
0
1
0
0
1
1
0
1
0
0
0
0
0
1
8
1
0
9
1
0
1
1
0
0
1
1
10
0
1
0
X
X
0
1
1
0
t
0
X
1
1
0
11
0
0
1
X
0
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle

1 : PCAT pipelined (word-wide) memory write
2 : PCAT pipelined (word-wide) memory read
3 : PCAT nonpipelined even-byte memory access
4 : PCAT nonpipelined odd-byte memory access
5 : PCAT nonpipelined word-wide memory access
6 : PCXT pipelined even-byte memory write
7 : PCXT pipelined even-byte memory read
8 : PCXT pipelined odd-byte memory write
9 : PCXT pipelined odd-byte memory read
10 : PCXT nonpipelined even-byte memory access
11 : PCXT nonpipelined odd-byte memory access

The control signals to the transcievers/latches are generated by the PAL U5, which realizes the above table.

lGIL_

=(MEMREQ

& PCXT & SAO_ & lMEMR_l # (lPCXT & PIPECYC & MEMR_l #
( lXCVL & SAO_l # (lHFO_ & lHFLl # (lXCV2_ & HFLl

lG2_

= (PIPECYC & lMEMR_l # (lXCVL
= (PCXT & MEMREQ & lSAO_l

lCAB_

= ( !IOWR_

lCBAl_

=(PIPECYC

lGIH_

&

lBHE_l # (lXCV2_

& HFLl

& lXCV2_ & HFLl

&

lMEMW_

&

lPCXTl # (MEMREQ

& PIPELINE &

lMEMW_

SAO_l
lCBA2_
SX
lDIR_

= (PIPECYC

=(MEMREQ
=( lXCV2_

& lMEMW_l

& PIPELINE #

lIORD_

& HFL & lIORD_l

& PIPELINE &

# (lMEMW_l

1-524

lXCV2_

& HFl_l

& PCXT &

inter

Ap·328

5.2.4 HOST REQUEST GENERATOR

The following table shows how different ports on the board are accessed. BOARDSEL refers to the board address
decoded, that is the logical AND of LSBDEC and LMSBDEC. X stands for don't care.
BOARDSEL L560WIN_ BOARDEN RAM SBHL* HF1_ HFO_
X
X
X
X
0
1
1
Idle
X
X
0
0
0
GCS_ access: Command/Status
0
GCS_ access: ROM *.
0
X
0
0
1
1
X
1
0
SRAM access
0
X
1
0
1
82560 register access
• In the a·bit configuration, inverted SAO serves as SBHE_.
•• ROM refers'to either PROM or EPROM. Bit 1 of the command register determines which.

The following PAL equations realize the above table. HFO_ and HF1_ are the request lines to the 82560.

mFO_

mFL

=

=

( !MEMW_
( !MEMW_
( !MEMW_
( !MEMR_
( !MEMR_
( !MEMR_

&: L560WIN_
&: L560WIN_
&:!L560WIN_
&: L560WIN_
&: L560WIN_
&:!L560WIN_

( !MEMW_
( !MEMW_
( !MEMR_
( !MEMR_

&:
&:
&:
&:

&:
&:
&:
&:
&:
&:

BOARDSEL
BOARDSEL
BOARDSEL
BOARDSEL
BOARDSEL
BOARDSEL

&:
&:
&:
&:
&:
&:

BOARDEN &:
BOARDEN &:
!BHE_) #
BOARDEN &:
BOARDEN &:
!BHE_)

REQEN)
#
!PIPELINE) #
REQEN) #
!PIPELINE) #

!RAM &: BOARDSEL &: BOARDEN) #
BOARDSEL &: !L560WIN_) #
!RAM &: BOARDSEL &: BOARDEN) #
BOARDSEL &: !L560WIN_)

5.2.5 MEMORY AND PERIPHERAL
CONTROLLER

To access any port on the board the host generates a
request to the 82560. The 82560 will then synchronize
the request and perform arbitration (with any active
local DMA request). It then asserts the proper memory
or peripheral control signals.
The 82560 also supports the interrupt function. The
interrqpt initiated by either the 82592 or the 82560 is
passed to the host system through one of the four interrupt lines (depending on the position of the switch).
In nonpipeline mode 10CHRDY is pulled low immediately after the board address is decoded. It goes high a
programmable number of clock transitions after the
host cycle starts. The 82560 register bit that can affect
it are: HRDY delay, HRDY delay reference source, 10
and access delays. The reader is referred to the 82560
data sheet for more details. In pipeline mode the 10CHRDY remains high until after the request is removed. Then the 82560 HRDY output goes low while
the local bus cycle is being completed. 10 CHRDY will
, be pulled low while the board address decode is 'active
and 82560 HRDY output is low. In either case the
10CHRDY is tristated until the board address is de·
coded.

enable (IOCHRDy) = (LSBDEC & LMSBDEC)
IOCHRDY = !560I0RDY_
# (!LSBDEC_ & LMSBDEC &. lBOARDEN . &
L560WIN_)
# (!LSBDEC & LMSBDEC & !BOARDEN & !BSAO)
5.2.5.1 Nonpipeline cycles

In ALL nonpipeline cycles (SRAM or otherwise) 10CHRDY is pulled low within 30 ns after the address on
the PC bus becomes valid. It remains low until the
82560 HRDY output goes high, then it goes high.
The memory address input to the 82560 in th~ nonpipline mode is the same as the host CPU address shifted
by one bit (SAl goes to AO input of 82560). During
byte-wide memory accesses byte enable inputs of the
82560 (BEO_ and BE1_) determine which bank of
SRAM is being accessed.
The output address of the 82560 is the same as its input
address, except that its three most significant bits (12,
13, and 14) are logically OR'd with the three least sig·
nificant bits of the 82560 host address register. The low
bank of memory is accessed for even-byte addresses and
the high bank or odd-byte addresses.

1-525

inter

AP-328

',,--. ___--II
82560 HRDY

''----II

IDCHRDY

292063-3

programmable). Autoretransmit, back-to-back frame
reception, and bad receive buffer reclamation are all
performed without CPU intervention. '

5.2.5.2 Pipeline Cycles
. During SRAM pipeline cycles IOCHRDY stays high.
It goes low after the cycle is over (HF_ removed). This
is when the 82560 performs read· ahead or write behind
operations. Read ahead means that the next word (or
byte in the case of 8-bit configuration) of data is copied
from the local memory into the data latches in anticipation of the next request. Write behind means that data
is first latched in the data latch(s) and then the 82560
copies the data into the local memory. The memory
address in this mode is provided by the host address
register, which is incremented by one after each 82560
transfer. To change the direction of the transfer the
82560 Host mode register should be accessed first and
its bit 1 changed.

The 82560 in the 82592 TCI mode supports transmit
chaining. DMA channels are also used to configure the
82592 and to read its 69 bytes of internal information
through the dump command.
The arbitration between the two DMA requests, and
between the host request and the DMA request, are
performed by the 82560 local bus arbiter function. .
Transmit buffer size (including the configuration block)
can be about two kilobytes. It should stop 128 bytes
before the end of the adapter memory. The last 128
bytes of address (highest addresses) are for accessing
the 82560 and the command and the status registers.

5.3 Memory Subsystem
The receive memory buffer can occupy the rest of the
local memory. It can be arranged as a ring buffer and
managed by the 82560. The lower limit register of the
82560 holds the starting address of the ring, and its
upper limit register holds the ending address of the
ring. The 82560 performs the wraparound without
CPU intervention. The stop register of the 82560 points
to the last receive buffer location processed by the host
CPU. The 82560 generates an interrupt to the host if
the current address register of the channel reaches the
stop register of that channel.

The memory subsystem consists of the network address
PROM (U15), the low bank of SRAM (U14), the high
bank of SRAM (U13), an optional EPROM (U16),
control PAL (UU, U5), and the 82560 memory controller (U6).
All controls are generated by the 82560, except for chip
select for the EPROM and the PROM.

EPROMCS_ = !( !GCS_ & !IORD_ & !PROM &
L560WIN_l
PROMCS_ =!( !GCS_ & !IORD_ & PROM &
L560WIN_l

For more information about DMA transfers and the
format of the transmit and receive frame, the user is
referred to the 82560/82561 Technical Reference ManualOrder #290198.

5.4 Network Interface
The network interface consists of the 82592 LAN controller (U7), the 82560 DMA controller (U6), and a
plug-in analog module (Ethernet, CNet, or TPE).
5.4.1 DMA TRANSFERS
Two independent DMA channels of the 82560 are used
to transmit and receive frames. Each word-wide DMA
transfer can have a duration of 200 to 500 ns (82560

5.4.2 SERIAL INTERFACE
The 82592 CSMA/CD controller is used in the highspeed mode. The 82C501AD performs Manchester encoding and decoding; it also provides a watchdog timer,
collision detection, and transmit/receive clack generation. Using the loopback modes, the transmitted data is
routed to the receive path (at the 82592, the
82C501AD, or on the wire). This feature is useful for
controller and physical layer diagnostics.

1-526

inter

AP-328

5.5 Schematics
015-08

07-00

PC BUS

LATCH/
XVR

SRAM
High Bank

PALS

1
-'--

XVR

-SRAM
Low Bank

LATCH/
XVR

I
592

560

I
COM/
STATUS
REG.

P
R
0
M

E
P
R
0
M
292063-4

Figure 1. PC592 Block Diagram

1-527

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30
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~

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292063-5

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292063-6

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292063-9

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19
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17
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---_.-

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(5 HEET 3)
5 HEET 3)

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(5 HEET 8)

REQEN
IOCHRDY

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(5 HEET 2)

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292063-11

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292063-21

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intJ

Ap·328

6.0 PERFORMANCE

state cycles should improve the network performance
by about 12% over wait state cycles.

The PC592E design is expected to provide very high
performance compared to many commercial adapters.
When the board is configured for. pipeline mode, it can
perform zero wait state cycles on the PC-AT bus. Without this feature each host access would be with three or
four additional wait states, resulting in a less efficient
use of the host bus bandwidth. In addition to reducing
the host bandwidth consumption, performing zero wait

Network performance can be influenced by how fast
the station can retransmit after a collision. Measurements show that an 82592/82560 design in the 82588
TCI mode can retransmit 4.8 /LSec after collision. In
the 82592 TCI mode this time is reduced to 2.1 ,...Sec.
The 82592 built in FIFOs reduce the possibility of underruns and overruns.

1-539

inter

AP-328

APPENDIX A

APPENDIX A
Signal name
BALE

BHE
BOARDEN
CAB
CBAI
CBA2CSL -; CSH_
DIREPROMCS
GCS
GlLGIHG2 HFO ,HFl
IOCHRDY IORD / MWR
IOWRINT LA23-LA20
LDCMD
LDO-LD15
LMSBDEC
LPBK
LSBDEC
L560IORDY
L560WIN MAPO,MAPI
MAP 2
MAO-MA12
MEMR
MEMREO
MEMW
MODTO,MODTl
MOE
MSBDEC
MEMCS16
PCXT
PIPECYC
PIPELINE
PROM
PROMCS
RAM
RAMEN

RDST
REOEN
RESET
5BHE
SX 5AI9-SAO
XVRI ,XVR2 .
ZEROW5
56 0 IORDY_

Description

-------------------------------------------------------------

address latch enable (from the PC bus)
byte high enable (input of 82560)
board enable (command register bit 3)
data latch clock (direction: local memory to latch)
data latch 07-00 clock (direction: host to latch)
data latch D15-D7 clock (direction: host to latch)
SRAM chip select outputs of 82560 (loW and high bank)
direction signal for data latches/transceivers
EPROM chip select signal
general chip select (output of 82560)
data D7-DO latch/transceiver tristate enable
data 015-D8 latch/transceiver tristate enable
byte swap transceiver tristate enable
active low host request signals to the 82560
IOCHROY to the PC bus
read from non-SRAM port or write to SRAM (output of 82560)
write to non-SRAM port (output of 82560)
interrupt output of the 82560
unlatched host address lines
load command register
local data bus
latched most significant bit decode
loopback signal
least significant bit address deccode
latched (falling edge of BALE), inverted 560 HRDY output
latched 82560 subwindow
Jumper selections for lower portion of the address mapping
JUmper selection that determines mapping below or above 1 Meg.
memory address lines (output of 82560)
memory read (from the PC bus)
memory access requested by the host CPU
memory write (from the PC bus)
network module identifier (bits 4 and 5 of the status register
memory output enable (output of 82560)
most significant bit decode (output of U2)
memory chip select 16 (to the PC bus)
8-bit vs. 16-bit configuration
pipeline cycle
pipeline mode (comamnd register bit 2)
command register bit determining PROM vs EPROM paging
PROM chip select
command register bit determining RAM VS. ROM paging
RAM and board enabled
read from the status register
memory request enabled (output of Ull)
reset (from the PC bus)
byte high enable (from the PC bus)
select between latched and real time data
latched PC address lines
transceiver/latch enable signals (output of 82560)
zero wait state cycle (to the PC bus)
buffered (inverted) HROY output of 82560
292063-13

1-540

inter

AP-328

APPENDIX B

.... ........•.......... -........ -... __ ...... _.-.- ........•...............
_

Module UI
5/3/89
Ti tie 'MEMCSI6
REV 4.0
Daryoosh Khalilolahi,
Intel Corporation
PAL20LBB (15ns)'
PC592PI

-

LMSBDEC
BHL
RAMEN
MAPO
MAP I
SA7
SA8
SA9
SAIO
SAl1
SAl 2
GND

'P20L8' :

Device
Pin
Pin
pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

VCC
MEMeS I 6_
LSBDEC_
L56OWIN_
SAO
SAI9
SAI8
SAt7
SAI6
SAI5
SAI4
SAI3

"I"

I:
2:
3:
4:
5:
6:
7:

"I"

" I"
"I"

Itl"

"I"
"I"
"I"
"I"
"I"

8:

9:
10 :
It:
12 :

"1"

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

24:
22:
15:
21:
20:
23:
19 :
18 :
17:
16 :
14 :
13:

"0"
"0"
"0"

"I"
"I"
"I"
"I"

"I"

III"
"I"
"I"

" SIGNAL DEFINITIONS:
"INPUTS: LMSBDEC
"
SAO
RAMEN
MAPO,MAPI
SA7-SAt9
BHL

%
%
%
%
%
%

latched'most significant bits (LA23-LA20) decode
host address input
RAM selection anded with board enable
Jumper selection for the mapping window.
Latched address lines from the PC bus
Byte high enable

"OUTPUTS: MEMeS 16_
LSBDE<=L560W1N_

% MEMCS16_ for the below 1 Meg. windows
%'Least signifiacnt bit address decode
% 82560/command subwindow addre.s decode

EQUATIONS
" the corresponding addre •• lines are compared with MAPO and MAPI to generate
" the least significan,t bits address, decode.
- «SAt9
(SA19
(SAt9
(SAt9
(SA19

I LSBDE<=-

&
&
&
&
&

SA18
SAI8
SA18
SA18
SAt8

&
&
&
&
&

ISA17
I SAt 7
ISA17
ISA17
ISAt7

&
&
&
&
&

ISAt6
I SA16
SA16
SA16
SA16

&
&
&
&
&

I SAlS
SA15
ISAlS
SA15
SAIS

&
&
&
&
&

I SAl4
ISA14
ISA14
ISA14
ISA14

*'
*'
*'

& IMAPl & IMAPO)
& IMAPI & MAPO)
& MAPI & IMAPO)
& MAPl & MAPO»:
& MAPI & MAPO»:

"If SA7 through SA13 are all one, assuming that higher bits of address match,
" the address is for accessing the 82560 or cOlIlDand/status register.
IL560W1N-

s

(SA13 & SA12 & SAil & SAIO & SA9 & SA8 & SA7):

" a 16 bit memory transfer is recognized if the address for SRAM access is
" matched and both SAO and BHL are low.
IMEMCSI6_ -

(LMSBDEC & RAMEN & I SAO & I BHL & L560W1N-) &
«SA19 & SAlS & ISAl7 & ISA16 & ISA15 & ISAl4 &
(SA19 & SAlS & ISA17 & ISAt6 & SAlS & ISA14 &
(SA19 & SAIS & ISA17 & SAl6 & ISAIS & ISA14 &
(SA19 & SA18 & ISA17 & SA16 & SAl5 & ISA14 &

IMAPI
IMAPI
MAPI
MAPI

&
&
&
&

IMAPO) *'
MAPO) *'
IMAPO) *'
MAPO»:

end Ul:
292063-22

1-541

inter
**.** ••

Ap·328

_._.*.**.*._- ••.... *--.-.... _-_ ... -------_ ... _.. _-_ ........ ,..... .

Module , U2
Ti tIe
unlatched address decode and host interface
Daryoosh Khalilolahi, Intel Corporation
PAL20LBB (15ns)'
PC592P2

Device

RAM
LSBDEC"":'
L560WHL
LA20
LA21
LA22
LA23
BHIL
MAP 2
MEMN_
MEMIL.
GND

Pin
Pin
pin
Pin'
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

REV 5.0

5/10/89

'P20LB' ;

1;
2;
3;
4;
5;
6;

Pin
vee
REQEN
Pin
Pin
MEMREQ
pin
BOARDEN
PIPELINE Pin
Rin
LMSBDEC
Pin
MSBDEC
RAMEN
Pin
BFO_
Pin
HF1_
Pin
ZEROWS_
Pin
L560IORDYJ'in

"I"
"I"

"I"

"I"
"I"
"I"
Itl"
"I"

7;

8;
9;
10;

,. I
I"

II

II

"1"

11;

12;

24;
H;

"I"
"0"
"I"
"I"
"I"

22;

"0"
"0"

17;
16;
13 ;
23;
15;
2();
21 ;
19;
14;

"0"
"0"
"0"
"I"

"Definitions
BOARDSEL'· ILSBDEC-& LMSBDEC;
" SIGNAL DEFINITIONS:
"INPUTS: RAM
LSBDEC
"
LMSBDEC
L560WIN_
LA20-LA23
BHlL
MAP2
MEMt\!...

MEMIL
PIPELINE
BOARDEN
L560IORDY_
"OUTPUTS: MSBDEC
HFO_,HFl_
"
ZEROWS_
IOCHiIDY
MEMREQ

RAM selected
% least significant bits address decode
% latched most significant bit address decode

%

% 560/command register sUUwind~
% unlatched address lines

byte high enable
jumper selection for
memory write command
memory read command
% command register bit
% command register bit
% latched and inverted
%
%
%
%

%
%
%
%
%

below/above 1 Meg.
2-, indicating pipeline mode
3, board enabled
82560 HRDy output

Most significant bits address decode
host request to the 82560
0 wait state output to the PC bus
output to the PC bus
host request to access SRAM

E~ATIONS

" HFO_ is asserted during SRAM and GCS (general purpose chip select) cycles.
(IMEMN_ & L560WHL &
(1MEMt\!... & L560WIN- &
(IMEMN_&IL560WIN_&
( IMEMIL & L5.6OWIN- &
(IMEMIL& L560WIN-&
(IMEMIL &IL56OWIN- &

BOARDSEL
BOARDSEL
BOARDSEL
BOARDSEL
BOARDSEL
BOARDSEL

&
&
&
&
&
&

BOARDEN &
BOARDEN &
IBHlL) •
BOARDEN &
BOARDEN &
IBHIL);

REQEN)
•
IPIPELINE).
REQEN) , •
IPIPELINE).

" HF1_ is asserted during 560/592 register accesses'and also GCS accesses.
" That Is all non-SRAM cycles.
IHF1_ - (IMEMW_ & IRAM & BOARDSEL &' BOARDEN) •
( IMEMW_ & BOARDSEL & IL56OWIN_) #
292063-23

1-542

intJ

Ap·328

&

( !~ & !RAM
BOARDSEL & BOARDEN) ~
(!~ & BOARDSEL & IL56OWIN_);
.. 0 Wait states cycles are performed only when accessing the SRAM and in the
" pipeline mode.
enable ZEROWS_ ZEROWS_

=

(RAM & BOARDSEL & BOARDEN & PIPELINE & L56mWIN_);

L560IORDY_;

MEMREQ - L56OWIN_& BOARDSEL & BOARDEN & RAM;
" most significant bits of address are compared with jumper node MAP2.
MSBDEC

((ILA20 & ILA21 & ILA22 & ILA23 & IMAP2) ~
(LA20 & LA21 & LA22 & LA23 & MAP2));

=

RAMEN = RAM & BOARDEN;
end U2;

*** •••• *.** •• ** •••••• ******************.************************.*****
Module US
Title 'Local bus control
REV 5.0 7/7/89
Daryoosh Khali10lahi,
Intel Corporation
PAL20LS (25 ns)'
Device

PC592P3
PCXT
SAO_
BUlL
HFO_
MEMR....
MEMN_

MEMREQ
HFL
IORD_
I OWL
XCVL
GND

Pin
Pin
pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

'P20L8' ;

nln

1;
2;
3;
4;
5;
6;
7;
8;
9;
10;
11;

VCC
GIL_
G2_

"In
"I"
I'I"
ItI"
"1 11

CAB_

SX
DlL
GIlL
CBA1_
CBAL
PIPELINE
unused
XCV2_

., I"
"I"
"I"
"I"
"I"

12;

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

24;
22;
21;
20;

"0"
"0"

19;

"0"
,"0"

18;

"0"

15;
17;

"0"

16;
14;

tlO"
II I"

23;
13;

"I"
"I"

"0"

"Definition
PIPECYC

-

(HFL & IHFO_ & PIPELINE);

"The following table shows different types of memory cycles and the expected
"value of the transceiver and data latch (74ALS646) control signals. B is the
"host side and A is the local bus side. When SX is 1, stored data is selected.
''When O. real time data is selected. X stands for don't care.
::cyc 1 e
1
2
3

4
5
6
7
8
9
10
11

Pipeline

--------

PCXT

BHlL

1

0
0
0
0
0
1
1
1

0

1

1

0

0
0

1
1

0

1
1
0
0
0

1
1

0
0
1
0
0
1
1

1

SAO
0
0
0
1
0
0
0
1
1
0
1

MEMN_ MEMR....
0
1
X
X
X

1
0

X
X
X

0
1

1
0
1
0

X

X
X

0
1

.x

GIL- GIlL G2_ CBAl_ CBA2_ SX
0
0
0
1

0
0
0
0

1
0
1

0
0
1
0
0
1
1
0
0
1
0

1
1
1
1

1
1
1
0
0
1
0

0
1
1
1
1
0
1
1
1
1
1

0
1
1
1
1
1
1
0
1
1

1

1
1
0
0
0
1
1
1
1
0
0

292063-24

1-543

infef

AP-328

.. cycle 1
, cycle 2
cycle 3
cycle 4
cy,cle 5
cycle 6
cycle 7
cycle 8
cycle 9
cycle 10
cycle 11,

PCAT pipel ined (word-wide) memory wri te
PCAT pipel ined (word-wide) memory read
PCAT nonpipelined even-byte memory access
PCAT nonpipelined odd-byte memory access
PCAT nonpipelined word-wide memory access
PCXT pip~lined even-byte memory write
PCXT pipelined even-byte memory read
PCXT pipelined odd-byte memory write
?CXT pipelined odd-byte memory read
PCXT nonpipelined even-byte memory access
: PCXT nonpipelined odd-byte memory access

" SIGNAL DEFINITION
"INPUTS:
"

.."OUTPUTS:

PCXT
SAO_
MEML
MEMN_
IORD_
lo.vIL
XCVl_
XCV2_
HFO_,HFl_
PIPELINE

% Jwnper slecting 8 bit or 16 bit machine
% inverted address line 0

GIL
GIlL

% Data transceiver/latch tristate enable (07-00)
% Data transceiver/latch tristate enable (DI5-D8)

GL

CAB_

CBAl_
CBA2_
SX
DIlL

% MEML from the PC bus

% MEMN_ from the PC bus

% IORD-fMEMWR- output of the 82560

% lo.vIL output of the 82560

%
%
%
%

XCVl_ output of the 82560
XCV2_ output of the 82560
host requests to the 82560
command register bit for 0 added W.S. cycles

% local bus transceiver enable signal
% Local data latch clock

%
%
%
%

latch host data (07-00)
latch host da~a (015-08)
Real time vs. latched data select
Data transceiver/latch direction

EQUATIONS
IGIL

- (MEMREQ & PCXT & SAO_ & lMEML) # (I PCXT & PI PECYC & MEML)
( IXCVl_ & SAO_) # ( IHFO_ & IHFl_) # (IXCV2_ & HFl_) ;

IGIIL

e

IG2_

- (PCXT & MEMREQ & I SAO_) ;

(PIPECYC & IMEML)

#

(IXCVl_& IBHE-)

*

#

(IXCV2_& HFl_);

- ICAIL - (I lo.vIL & IXCV2_ & HFL);
ICBAL - (PIPECYC & lMEMN_ & IPCXT)

*

(MEMREQ & PIPELINE &IMEMN_ & PCXT & SAO_)

ICBAl_ - (P I PECYC & IMmml.J;
SX

(MEMREQ & PIPELINE

*

IIORD_& PIPELINE & IXCV2_& HFl_);

IDIIL - (IXCV2_ & HFL & 1-IORD_)

*

(!MEMN_J;

end U5;
*************************************.***************************.******

Module U11
Title 'Local ports control
REV 3.0
5/3/89
Daryoosh Khalilolahi, Intel Corporation
PAL16L8B-2 (25ns)'
PC592P4

Device

'P16L8';
292063-25

1-544

inter

AP-328

LSBDEC_
IORDY_
BSAO
PCXT
GCS_
L56OWlN_
lCJNIL
IORD_
BOARDEN
GND

P
P
P
P
P
P
P
P
P
P

n
n
n
n
n
n
n
n
n
n

VCC
EPR

IOCS7

t"T---nU C -

RESET

: J'

CD

CO

en
....
0

III It

A3-A,

L::::t==:1~ so

•

~~~Y E~
ALE

6

ADDRESS AZ3-0

INTA -

DT/R
DEN

J,.

C)

CD

I\)

"D

....

()

0

l>

Is

II

1----+--.....

82288
231928-3

cl
READY
NA

ClK2~~::t:::~~=fl==;9E;,;~~~;;~~~~~~~
REsETt-::======~:t:;l

T---'---_---"r

ADS!-

"11

~.

...c:

"!-"co
0

w

I.l/iO

ole
W/P.

80386

8516

CO

~

S-

~ ...iD
III
0

:::T

CO

N

....0
CI1

lE

o
~~~~~~~~~go
o
o

(I)

...
.."0
"

WE

A31- 2
8E3-0

~'-'I

gII~~~~~~~~~
g
LATCHES

7445373

Q

WE

HIoI651629-2

H).(651629-2

2Kx8 SRAM

2Kx8SRAM

~

~

AI0-?07_0
023-16

AI0-?07_0
015-8

l>

07-0

-g

0
0

o

I

...."""o

I

I '111119

DT/P. DEN

A14-:"'1IA13-007_0

~

I"="il=

A13-0
07-0

ID7-D
TXD
RXD

RESET ...= - INTR

231928-4

intJ

AP·401

The required recovery time between successive commands is 123 ns for the 82510, this is well within the
331.75 ns provided by the Basic I/O interface.

with the PC software). Also since in the PC family the
interrupt request pin of the UART is gated by the
OUT2 pin, The OUT2 pin must be available in the
16450 compatibility mode, consequently the user is restricted to an external clock source when using the
82510 in the IBM PC compatible mode. The default pin
out is given in Figure 6 and the configuration is given in
Table 1. The default register values are given in the
82510 register map shown in Figure 2 in section 3.1.1.

Write Cycle:
Addven to Write Low = 132.75 ns
82510TAVWL

= 7ns

Write Active Time

= 300.5 ns

82510 TWLWH

= 231 ns

Data to Write High

= 289.5 ns

Table 1.82510 Default Configuration
INTERRUPTS
Auto Acknowledge
All Interrupts Disabled

82510 TnvwH

= 90ns

RECEIVE
NOTE:
The interface sho~iJ. in Figure 5 uses a different address decoding scheme than that used for the IBM
PC/PC AT families, for the serial ports. Therefore,
the interface in Figure 5 can not be used in PC/PC
AT compatible designs.

Stand Ctl. Char. Recogn. disabled
Digital Phase Locked Loop (DPLL) disabled
3/16 SamplinsMajority Vote Start bit
Non J-Llan (Normal) mode

BkD, FE, OE, PE Int. enabled

3.2 Reset

FIFO
The 82510 can be reset either through hardware (Reset
pin) or Software (reset command via Internal Command Register-ICM). Either reset would cause the
82510 to return to its default wake up mode. In this
mode the register contents are reset to their default values and the device is in the 16450 compatible configuration. The Reset pulse must .be held active for' at least
eight system clocks, the system clock should be running
during reset active time.

Rx FIFO Depth = I
Tx FIFO Threshold

=0

AUTO ECHO Disabled
LOOP BACK Configured
for Local Loopback
CLOCK OPTIONS

3.2.1 DEFAULT MODES FOR 16450
COMPATIBILITY
Upon reset the 82510 will return to its Default Wake
Up mode. The default register bank is bank zero. The'
registers in bank zero are identical to the 16450 register
set, and provide complete software compatibility with
the 16450' in the IBM PC environment. The registers
in the other banks have default values, which configure
the 82510 for 16450 emulation. The recommended system clock (for PC compatibility) is 18.432 MHz, this
allows the baud rates generation to be done in a manner
compatible with the PC software. The PC software calculates baud rates based on a source frequency of
1.8432 MHz. The 82510 system clock (18.432 MHz) is
divided by two before being fed to BRG A and then is
again divided by five (BRG B default). This causes the
frequency to be divided by ten before being fed into
BRG A. 18.432 divided by ten yields 1.8432 MHz, so in
effect the BRG A is generating baud rates from a
source frequency of 1.8432 MHz (which is compatible
. '16450 is the PC AT version of the INS 8250A.

2-12

Baud Rate = 57.6K
Rx Clock = 16 x
Rx Clock Source = BRG B
Tx Clock = 16 x
Til Clock Source = BRG B
BRG A Mode

= BRG

BRG A Source = Sys. Clock
BRG B Mode = BRG
BRG B Source = BRG A Output
TRANSMIT
Manual Control of RTS
1 Stop Bit
No Parity
5 Bit Character

inter

AP-401

EXTERNAL CLOCK
04

03

05

02

06

01

07

DO
A2

TXD

VSS
OUT2

A1
AO

Vee

iii

Rii
Viii

DSR

cs

OCD

RESET

eLK

231928-7

NOTE:

Crystal Oscillator is always divided by two.
Figure 8. Disable Divide by Two

RTS
CTS

If the Crystal Oscillator is being used to supply the

OTR

231928-5

Figure 6. Default Pin Out Configuration
of the 82510

3.3 System Clock Options
The term "System Clock" refers to the clock which
provides timings for most of the 82510 circuitry. The
82510 has two modes of system clock usage. It can
generate its system clock from its On-Chip Crystal Oscillator and an external crystal, or it can use an externally generated clock, input to the device through the
CLK pin. The selection of the system clock option is
done during reset. The default system clock source is an
externally generated clock, which can be reconfigured
by a strapping option on the RTS pin. During Reset,
the RTS pin is an input; it is internally pulled high, if it
is externally driven low, then the 82510 expects to use
the Crystal Oscillator for system clock generation, otherwise it is set up for using an external clock source.
This can be done by using an open collector inverter to
RTS, the input of the inverter is the Reset signal. The
82510 has a pull up resistor in the RTS circuitry so no
external pull up is needed. In the crystal oscillator
mode the CLK/Xl pin is automatically configured to
Xl, and the OUT2/X2 pin is configured to X2. In the
External Clock mode, the CLK/Xl is configured to
CLK and the OUT2/X2 is configured to OUT2.

system clock, then the clock frequency is always divid. ed by two before being fed into the rest of the 82510
circuitry. If, however an external clock source is being
used to supply the system clock, then the user has two
options:
1. Use the System Clock after division by two, e.g. if a
8 MHz clock is being fed into the CLK pin, then the
actual frequency of the 82510 system clock will be 4
MHz (default).
2. Disable Division by two and use the direct undivided clock, e.g. if an 8 MHz clock is being fed into the
CLK pin, then the actual frequency of the 82510
system clock is also 8 MHz.
The divide by two option is the default mode of operation in the External Clock mode of the 82510. A strapping option can be used to disable the Divide By :Two
operation (For Crystal Oscillator Mode Divide By Two
must always be active). During Reset, the DTR pin is
an input; it is internally pulled high, if it is externally
driven low then the Divide By Two operation is disabled. The strapping option is identical to the one used
on RfS for selection of the System Clock source.
The 82510 system clock must be chosen with care since
it influences the wait state performance, Baud Rate
Generation (if being used as source frequency for the
BRGs), the power consumption, and the Timer counting period. The power consumption of the 82510 is dependent upon the system clock frequency. If using the
system clock as a source for the Baud Rate Generator(s), then the system clock frequency must be a baud
rate multiple in order to minimize frequency deviation.
For standard baud rates a multiple of 1.8432 MHz can
be used, in fact the 18.432 MHz maximum frequency
was chosen with this particular criteria in mind.

231928-6

1 ms is needed for Oscillator startup
Figure 7. Crystal Oscillator Strapping Option
2-13

intJ

AP-401

BACF(6)

SCLK---"

BRGA
FSt.! + COUNTER
+ LOGIC

DEF'

CLK/X1-~~

BBCF'(7-6)

SCLK .....-

RXt.!
16X
CLOCK

CLCF'(6)

BRGB
F'St.! + COUNTER
+ LOGIC

___..

CLK/X1-+.......~

TXt.!
16X
CLOCK

'---CLCF'(4)

TXt.!

Tx Ct.! BIT~_ _- ;
OF' CLCF'

\------------------~~1X

Rx Ct.! BIT _ _ _- ;
IN CLCF"

l--------------------~1X

r

CLOCK
RXt.!

CLOCK
231928-8

Figure 9. Timing Flow of the 82510

2-14

intJ

AP-401

3.3.1 POWER DOWN MODE

3.3.1.2 Idle Mode

The 82510 has a "power down" mode to reduce power
consumption when the device is·not in use. The 82510
powers down when the power down command is issued
via the Internal Command Register (ICM). There are
two modes of power down, Power Down Sleep and
Power Down Idle.

The 82510 is said to be in the Idle mode when the
Power Down command is issued and the system clock
is still running (i.e. the system clock is generated externally and not disabled by the user). In this mode the
contents of all registers and memory cells are preserved,
however, the power consumption in this mode is greater than in the Sleep mode. Reading FLR will take the
82510 out of this mode.

3.3.1.1 Sleep Mode

NOTE:
The data read from FLR when exiting Power Down is
incorrect and must be ignored.

This is the mode when even the system clock of the
82510 is shut down. The system clock source of the
82510 can either be the Crystal Oscillator or an external clock source. If the Crystal Oscillator is being used
and the power down command is issued, then the
82510 will automatically enter the Sleep mode. If an
external clock is being used, then the user must disable
the external clock in addition to issuing the Power
Down command, to enter the Sleep mode. The benefit
of this mode is the increased savings in power consumption (typical power consumption in the Sleep
mode is in the range of hundreds of microAmps. However, upon wake up, if using a crystal oscillator, the
user must reprogram the device. The data is preserved
if the external clock is disabled after the power down
command, and enabled prior to exiting the power down
mode. To exit this mode the user can either issue a
Hardware reset, or read the FIFO Level Register (FLR)
and then issue a software reset (if using a Crystal Oscillator). In either case the contents of the 82510 registers
are not preserved and the device must be reprogrammed prior to operation.

4.0 INTERRUPT BEHAVIOR

4.1 FIFO Usage
The 82510 has two independent four bytes transmit and
receive FIFOs. Each FIFO can generate an interrupt
request, when the FIFO level meets the Threshold requirements. The FIFOs can have a considerable impact
on the performance of an asynchronous communications system. For systems using high baud rates they
can provide increased interrupt-to-service latency reducing the chances of an overrun occurring. In systems
constrained for CPU time, the FIFOs can increase the
CPU Bandwidth by reducing the number of interrupt
requests generated during asynchronous communications. It can reduce the interrupt load on the CPU by
up to 75%. By choosing the FIFO thresholds which
reflect the system bandwidth or service latency requirements, the user can achieve data rates and system
throughput, unattainable with traditional UARTs.

NOTE:
If the Crystal Oscillator is being used then the user

must allow about 1 ms for the oscillator to wake up
before issuing the software reset.

Table 2. The Power Down Modes
Mode
Sleep

Idle

Clock Source

Exit Procedure

Power Consumption

Data Preservation

CrystalOscill.
Automatically
Disabled

H/W Reset or
Read FLR and
Issue S/W Reset

100-900/LA

Not Preserved
Must be Reprogrammed

External Clock
Must be Disabled
by User

Enable External
Clock, Read FLR
and Issue S/W Reset
H/W Reset

100-900 !LA

Not Preserved
Must be Reprogrammed

External Clock
Running

H/W Reset
Read FLR

1-3mA

All Data Preserved
Does Not Need to be
Reprogrammed

2-15

AP-401

4.1.1 INTERRUPT·TO-SERVICE LATENCY

Going back to equation (2):

The interrupt·to·service latency is the time delay from
the generation of an interrupt request, to when the interrupt source in the 82510 is actually serviced. Its
primary application is in the reception of data. In traditional UARTs the CPU must read the current character in the Receive Buffer before it is overrun by the next
incoming character. The Rx FIFO in the 82510 can
buffer up to four characters, allowing an interrupt-toservice latency of up to four character transmission
times. The character transmission time is the time period required to transmit one full character at the given
Baud Rate. It is dependent upon the baud rate and is
given by equation (1):

Int._to_service latency < Buffer size x lO/baud rate
Int_to_service latency = # of Channels X (# of
into sources per channel)
X Time required to service interrupt

(I) Character Transmission Time

=

Int_to_service latency

=

4 X 2 X Time required to
service interrupt

The Time required to service interrupt has been calculated to be 100 f.Ls for a slightly optimized service routine. RMX86 interrupt service time is given as 250 f.Ls
and for other operating systems it should be slightly
higher.
Int_to_service
latency
= 4x2xlO0 s

Num. of Bits per Character Frame
Baud Rate

= 800 f.Ls
82510 max Baud Rate
(four byte FIFO)
82510 max Baud Rate
(one byte FIFO)

The Transmit and Receive FIFO thresholds should be
selected with consideration to two factors the Baud
rate, and the (CPU Bandwidth allocated for Asynchronous Channels is dependent upon the number of channels supported since it does not include the overhead of
supporting other peripherals) number of Asynchronous
Serial ports being supported by the CPU. In order ,to
avoid overrun, the interrupt-to-service delay must be
less than the time it takes to fill the 82510 Rx FIFO.
The relationship is given by equation (2):
(2) Int_to_service-Iatency < FIFO Size X

=

=

4 X 10/800 f.Ls
50K bits/sec
I X 10/800 f.Ls
12.5K bits/sec

4.2 Interrupt Handling
The 82510 has 16 different sources of interrupt, each of
these sources, when set and enabled, will cause their
respective block interrupt requests to go active. The
block interrupt request, if enabled, will set the 8251O's
INT pin high, and will be reflected as a pending interrupt in the General Interrupt Register (GIR) if no other
higher priority block is requesting service. If a higher
priority block interrupt is also active at the same time,
then the General Interrupt Register will reflect the higher priority request as the source of the 82510 interrupt.
The lower priority interrupt will issue a new edge on
the interrupt pin only after the higher priority interrupt
is acknowledged and if no other priority block requests
are present. Both the block interrupts and the individual sources within the blocks are maskable. The block
interrupts are enabled through the General Enable Register (GER) which prevents masked bits in the General
Status Register (GSR) from being decoded into the
General Interrupt Register. This does not prevent the
block request from being set in the General Status Register, it only prevents the masked GSR bits from being
decoded into the General Interrupt Register, and thus
generating any interrupts. The individual sources within the block are masked out via the corresponding interrupt enable register associated with the specific block
(Rx Machine, Timing Unit and the Modem I/O module each have an Interrupt Enable register).

Character Transmission Time
Example

Calculate the maximum baud rate that can be supported by a 6 MHz PC AT to support four Full Duplex
Asynchronous channels using
a) The 82510 with four byte FIFO.
b) The 82510 with one byte FIFO.
Assumptions:

• CPU dedicated to Asynchronous communications.
• UART Interrupts limited to Transmission and Reception only.
• Interrupt Routines are optimized for fast throughput.
• 10 bits per charaCter frame.

2-16

inter

AP-401

FIFO BELOW
OR EQUAL
THRESHOLD

GER

AUTOMATIC MODE

11.40(3)

231928-9

Figure 9. 82510'5 Interrupt Scheme

2·17

intJ
4.2.1 THE INTERRUPT SCHEME

The 82510 interrupt logic consists of the following elements:
4.2.1.1 Interrupt Sources Within Blocks

Three of the 82510 functional" blocks (Rx Machine,
Timer, Modem I/O) have more than one possible
SO)lrce of interrupts, for instance the Rx Machine has
seven different sources of interrupts-standard control
character recognition (Std. CCR), control character
Match (special CCR), Break Detect, Break Terminated, Overrun Error, Parity Error, and Framing Error.
The mUltiple sources are represented as Status bits in
the Status registers of. each of these blocks. When enabled the Status bits cause the block request to set in
the General Status Register. There is no difference in
the behavior of the INT pin or the block status bits in
GSR, for multiple sources within a block becoming active·simultaneously. The corresponding block status bit
in GSR is set when one or more interrupt sources within the block become active. When the status register for
the block is read all the active interrupt sources within
the block are reset. Each source within the three blocks
can be masked through its respective enable register.
4.2.1.2 General Status Register (GSR)

This register holds the status of·the six 82510 blocks
(all except Bus Interface Unit). Each bit when set indicates that the particular block is requesting interrupt
service, and if enabled via the General Enable Register.
will cause an interrupt.

4.2.1.4 Priority Resolver and General Interrupt
Register

If more than one enabled Interrupt request from GSR
is active, then the priority resolver is used to resolve
contention. The priority resolver finds the highest priority pending and enabled interrupt in GSR and decodes it into the General Interrupt Register (bits 3 to 1).
The General Interrupt Register can be read at any time.
NOTE:
GIR is updated continuously, so while the user may
be serving .one interrupt source, a new interrupt with
higher priority may update GIR and replace the older
one.
4.2.2 INTERRUPT ACKNOWLEDGE MODES

The 82510 has two modes of interrupt acknowledgement-Manual acknowledge and Automatic acknowledge. In Manual Acknowledge mode, the user has to
issue an explicit Acknowledge Command via the
Internal Command Register (ICM) in order to cause
the INT pin to go low. In Automatic Acknowledge
mode the INT pin will go low as soon as an active or
pending interrupt request is serviced by the CPU. An
operation is considered to be a service operation if it
causes the source of the interrupt (within the 82510) to
become inactive (the specific status bit is reset). The
service procedures for each source vary, see section
4.2.3.2 for details.
.
4.2.2.1 Automatic Acknowledgement

In the automatic acknowledge mode, a service operation by the CPU will be considered as an automatic
acknowledgement of the interrupt. This will force the
INT pin low for two clock cycles, after that the INT
pin is updated i.e. if there is an active enabled source
pending then the INT pin is set high again (reflected in
GIR). This mode is useful in an edge triggered Interrupt system. Servicing any enabled and active GSR bit
will cause Auto Acknowledge to occur (independently
of the source currently decoded in the GIR register).
This can be used to rearrange priorities of the 82510
block requests.

4.2.1.3 General Enable Register (GER)

This register is used to enable/disable the corresponding bits in the General Status Register. It can be programmed by the CPU at any time.
Table 3. Block Interrupt Priority
Block

Priority

Timers
TxMachine
RxMachine
RxFIFO
TxFIFO
Modem I/O

5 (highest)
4
3
2
1
o(lowest)

..

GIRCODE
3 2 1 (Bits)
1 0 1
100
011
010
001
000

2-18

intJ

AP-401

GSR 5
TIMER
GSR 3

GIR
GIR

= 1--

INT

8259A

USER
OPERATIONS

READ GIR SERVE
(= 10) TIMER

ISSUE
EOI
TO

8259A

READ GIR SERVE ISSUE
(= 2) TX FIFO
EOI
(WRITE
CHARACTERS)

READ GlR SERVE
(= 0) MODEM

ISSUE
EOI
231926-10

6259A

~

Edge Triggered
Non Auto EOI
62510 Automatic Acknowledge

Figure 10. Automatic Acknowledge Mode Operation

GSR
bit 3

---.J
(MODEM)

b?tS:

(TXM)

b~tS~

(TIMER)

GIR

GIR

=1

(82590)
INT

8259A

USER

READ GIR SERVE MODEM READ GIR
(=0)
INTERRUPT
(=10)

SERVE
TIMER

READ GIR

(=8)

SERVE

TXN

READ GIR ISSUE
(= 1) MANUAL
ACK TO

82510

231926-11

NOTE:
Vector refers to GIR bit (3-0)
62510: Manual Ack. Mode
6259A: Edge Triggered Non AEOI

Figure 11. Manual Acknowledge Mode Operation

2-19

intJ

AP-401

mode. Of course the user has the option of issuing the
acknowledge command immediately after the service,
which would be similiar in behavior to the automatic
mode. If the manual acknowledge command is given
before the active source has been serviced· and no higher·
priority request is pending, then the same source will
immediately generate a new interrupt. Therefore, the
software must make sure that the Manual Acknowledge command is issued after the interrupt source has
been serviced by the CPU (see section 4.2.3.2. for more
details on interrupt service procedures for each source).

.4.2.2.2 Manual Mode of Acknowledgement
The Manual Acknowledgement Mode requires that,
unlike the automatic mode where a service operation is
considered as an automatic acknowledg~, an explicit
acknowledge command be issued to the 82510 to cause
INT to go inactive. In this mode the CPU has complete
control over the timing of the Interrupts. Before exiting
the service routine, the CPU can check the GIR register
to see if other interrupts are pending and can service
those interrupts in the same invocation, avoiding the
overhead of another interrupt as in the Automatic

READ CORRESPONDING
STATUS REGISTER &:
SERVICE ALL APPROPRIATE
ACTIVE BITS

RESTORE ORIGINAL
VALUE OF GIR/BANK
TO RETURN TO
ORIGINAL BANK

231928-12

Figure 12. Typical Interrupt Handler

2-20

AP-401

Since the 82510 registers are divided into banks, and
the interrupt handler may change register banks during
service, it is best to save the bank being used by the
main program and then do the interrupt processing.
Upon completion of service, the original bank value is
restored to the GIRIBank register.

4.2.3 GENERAL INTERRUPT HANDLER

In general an interrupt handler for the 82510 must first
identify the interrupt source within the 82510, transfer
control to the appropriate service routine and then
service the active source. The active source can be identified from two registers-General Interrupt Register.
or General Status Register. The GIR register identifies
the highest priority active block interrupt request. The
GSR register identifies all active (pending or in service)
Block Interrupt Requests. The .typical operation of the
82510 interrupt handler is given in Figure 12. The two
major issues of concern are the source identification
and Control Transfer to the appropriate service routine.

4.2.3.1 Source Identification

The 82510 has 16 interrupt sources, and the CPU must
identify the source before performing any service. Although the procedure varies, the typical method would
be to identify the block requesting service by reading

USER PRIORITY
RX FIFO (HI)
RX MACHINE
TIMER
TX
FIFO
(
TX MACHINE
MODEM (LOW)

=!

231928-13

Figure 13. Bypassing the 82510 Fixed Interrupt Priority

2-21

inter

AP-401

GIR bits 3-1. If the source is either Tx Machine, Tx
FIFO, or Rx FIFO, no further indentification is needed, the user can transfer control to the service routine
(in most cases, only one Timer will be used, therefore
the Timer Routine can also be directly invoked). All
modem I/O interrupts can be handled via one routine
as all the modem interrupt sources are supplementary
to the modem handshaking function. The Rx Machine,
however, has two different types of interrupt sources,
event indications (CCR/Address recognition CCR! Address Match, Break Detect, Break Terminate, and
Overrun Error), and error indicati~ns (Parity Error,
Framing Error, these error indications do not refer to
any particular character, they just indicate that the specific error was detected during reception). For most applications, the error indicators can be masked off, and
only the event driven interrupts enabled. The error indicators can be read from the Receive Flags prior to
reading a character from the FIFO. This interrupt
scheme can be used, because the Receive character error indicators are available in the Receive Flags, and
can be checked by the Receive routine before reading
the character from the Rx FIFO.

user can bypass the 8251O's priority resolution by using
the General Status Register (rather than GIR) to determine the block interrupt sources requesting service.
Each source is checked in order of user priority and
serviced when identified (There will be no problem with
using this algorithm in auto acknowledge mode because
the INT pin will go low as soon as a pending and enabled interrupt request goes low). The user will be trading some service latency time for additional source
identification time, this algorithm's efficiency will improve as the number of block sources to verify is reduced. See Figure 13 for the algorithm.
4.2.3.2 Interrupt Service

A service operation is an operation performed by the
CPU, which causes the source of the 82510 interrupt to
go inactive (it will reset the particular status bit causing
the interrupt). An interrupt request within the 82510
will not reset until the interrupt source has been serviced. Each source can be serviced in two or three different ways; one general way is to disable the particular
status bit causing the interrupt, via the corresponding
block enable register. Setting the appropriate bit of the
enable register to zero will mask off the corresponding
bit in the status register, thus causing the INT pin to go
inactive. The same effect can be achieved by masking
off the particular block interrupt request in GSR via
the General Enable Register. Another method, which is
applicable to all sources, is to issue the Status Clear
command from the Internal Command Register. The
detailed service requirelIlents for each source are given
below:

Since all active status bits (except Rx FIFO interrupt in
LSR and RST) are reset when the corresponding block
status register is read, the interrupt routine must check
for all possible active sources within the block, and
service each active source before exiting the interrupt
handler.
The 82510 interrupt contention is resolved on a fixed
priority basis. In some applications the fixed priority
may not be suitable for the user. For these cases the

Table 4 Service Procedures For Each Interrupt Source
Interrupt
Source

Status Bits
& Registers

Interrupt
Masking

Specific
Service

General
Service

Timers

TMST(1·0)
GSR(5)

TMIE(1-0)
GER(5)

ReadTMST

Issue
Status Clear
(StC)

Tx
Machine

GSR(4)
LSR (6)

GER(4)

Write Character
toTxFIFO

Issue StC

Rx
Machine

LSR (4·1)
RST(7-1)
GSR(2)

RIE(7-1)
GER(2)

Read RST or LSR
Write 0 to bit
in RST/LSR

Issue StC

RxFIFO

RST/LSR (0)
GSR(O)

GER(O)

Write 0 to LSR/RST
Bit zero.
Read Character(s)

IssueStC

TxFIFO

LSR (5)
GSR(l)

GER(l)

Write to FIFO
ReadGIR

IssueStC

Modem

MSR(3-0)
GSR(3)

MIE(3-0)
GER (3)

Read MSR
write 0 into the
appropriate bits of
ofMSR(3-0)

IssueStC

NOTE:
The procedures listed in Table 4 will cause the INT pin to go low only if the 82510 is in the automatic acknowledge mode.
Otherwise. only the internal source(s) are decoded. the INT pin will go low only when the Manual Acknowlege command is
issued.

2-22

inter

Ap·401

6. Configure the Transmit Mode Register for the
Stop Bit length, modem control, and if using echo
or 9 bit length or software parity, configure the
appropriate bits of the register. The default mode
of the modem control is Manual, if using the FIFO
then the automatic mode would be most useful).
7. Configure the Rx FIFO depth, interrupt acknowl·
edge mode, /lolan or normal mode and echo modes
in IMD register.
8. Load ACRI if necessary
9. Enable Rx Machine Interrupts as necessary via
RIE.
10. Configure RMD for CCR, DPLL operation, Sampling Window, and start bit.
11. Switch to Bank 3.
12. Configure CLCF register for Tx and Rx clocks and
or Sources
13. Configure BACF register for BRG A mode and
source.
14. Load BBL and BBH if BRGB is being used (as
either a BRG or a Timer).
15. Configure BBCF register if necessary.
16. If reconfiguration of the modem pin is necessary
then program the PMD register.
17. Enable any modem interrupt sources, if required,
via MIE register.
18. Enable Timer interrupts, if necessary, via TMIE.
19. If using interrupts
then
i) Switch to Bank zero.
Disable Interrupts at CPU (either by masking
the request at the interrupt controller or executing the CLI instruction).
ii) Enable the appropriate 82510 Block interrupts
by setting bits in the GER register. (CPU interrupts can now be reenabled, but it is recommended to switch banks before enabling the
CPU interrupts).

4.3 POlling
The 82510 can be used in a polling mode by using the
General Status Register to determine the status of the
various 82510 blocks, this is useful when the software
must manage all the blocks at once. If the software is
dedicated to performing one function at a time, then
the specific status registers for the block can be used,
e.g. if the software is only going to be Transmitting, it
can monitor the Tx FIFO level by polling the FIFO
Level Register, and write data whenever the Tx FIFO
level decreases. Reception of data can be done in the
same manner.

5.0 SOFTWARE CONSIDERATIONS
5.1 Configuration
The 82510 must be configured for the appropriate
modes before it can be used to transmit or receive data.
Configuration is done via read and write registers, each
functional block (except for BIU) has a configuration
register. Typically the configuration is done once after
start up, however, the FIFO thresholds and the interrupt masks can be reconfigured dynamically. If the
82510 configuration is not known at start up it is best to
bring the device to a known state by issuing a software
reset command (ICM register, bank one). At this point
all block interrupts are masked out in GER and all
configuration and status registers have default values.
The bank register is pointing to bank zero. The 82510
can now be configured as follows:
1. If BRG A is being issued a baud rate generator
then load the baud rate count into BAL and BAH
registers.
2. Configure the character attributes in LCR register
(Parity, Stop Bit Length, and Character Length).

as

(Note if interrupts are being used, steps 1 and 2 can
also be done at the end, since the user will have to
return to bank zero to set the interrupt masks in GER)
3. Load ACRO register with the appropriate Control
or Address character (if using the Control Character Match or Address Match capability of the
82510).
4. Switch to Bank two.
(In this Bank the configuration can be done in any
order)
5. Configure the Receive and Transmit FIFO thresholds if using different thresholds than the default).

NOTE:
At this stage it is best to leave the TxM and Tx FIFO
interrupt disabled. See section 6.3 Transmit Operation
for details)
20. Switch to Bank One. Load Transmit Flags if using
9-bit characters, or 8051 9-bit mode or software
parity. If using interrupts CPU interrupts can now
be enabled.
Bank One is used for general operation, the 82510 can
now be used to transmit or receive characters.

2-23

inter

AP-401

GENERAL
CONFIGURATION

CONFIGURE:
1. STOP BIT LENGTH
2. MODE OF RTS CONTROL
3. 9-BIT CHAR. LENGTH}
4. S/W PARITY
OPTIONAL

5. AUTO ECHE MODE IN
TRANSMIT MODE REGISTER

SET RX FIFO DEPTH.
INTERRUPT
ACKNOWLEDGE MODE,
).LLAN OR NORMAL AND
AUTO ECHO IN INTERNAL
MODE REGISTER

ENABLE INTERRUPTS FOR
RX STATUS BITS VIA
RX INTERRUPT
ENABLE REGISTER

231928-14

SET MODES OF CONTROL
CHARACTER RECOGNITION,
DATA SAMPLING, AND
DPLL USE,
IN RX MODE REGISTER

TO C
231928-15

Figure 14. Configuration Flow Chart

2-24

intJ

AP·401

MODEM AND
TIMING UNIT
CONFIGURATION

C

IN CLOCKS CONFIGURE
REGISTER: SELECT SOURCES
OF TX & RX CLOCKS
SELECT MODES OF
TX & RX CLOCKS

CONFIGURE BRG A CLOCK
SOURCE AND MODE OF
OPERATION VIA BRG A
CONFIGURATION REGISTER

o

ENABLE THE 82510
BLOCK INTERRUPT
SOURCES VIA GENERAL
ENABLE REGISTER

CONFIGURE BRG B FOR
SOURCE AND MODE VIA BRG B
CONFIGURATION REGISTER
(IF BEING USED AS A BRG)

ENABLE INTERRUPTS
(IF NECESSARy) ON
MODEM INPUT PINS VIA
MODEM INTERRUPT
ENABLE REGISTER

231928-17

'. ENABLE TIMER INTERRUPTS
""S NECESSARY. VIA
TIMER INTERRUPT
ENABLE REGISTER

TO D

231928-16

Figure 14. Configuration Flow Chart (Continued)
2-25

inter

AP-401

T
X
F
I
F

4

o
~

,l
•

L

3

E
L

-2
THRESHOLD

",
'1

•,

·

-- --- ..-- ......
'~~------~~---------~-~
-- -- -- ................

1 ):-_".._-----. . . .-=o;a",

~

,

O-L----~-----------------~-~~--INACTIVE

INTERRUPTS

ACTIVE

231926-16

--- Tx Machine and 82510
---- User write operation
Figure 15. Tx FIFO Interrupt Hysteresis

The transmitter has two status flags. Tx Machine Idle
and Tx FIFO interrupt request, each of these conditions may cause an interrupt, if enabled. The Transmit
Idle condition indicates that the Tx Machine is either
empty or disabled. The Tx FIFO interrupt bit is set
only when the level of the Tx FIFO is less than or equal
to the threshold. These interrupts should remain disabled until data is available for transmission. Because
outside of disabling the corresponding GSR status bits,
the only way to service Tx Idle is by writing data to the
Transmitter. Otherwise, the Tx Machine interrupt may
occur when no data is available for transmission, and as
a result will keep the INT pin active, preventing the
82510 from generating any further interrupts (unless
the Transmit Interrupt routine automatically disables
the Tx Machine Idle and Tx FIFO interrupt requests in
GSR). The threshold of the Tx FIFO is programmable
from three to zero, at a threshold of three the Tx FIFO
will generate an interrupt after a character has been
transmitted. While at a threshold of zero the interrupt
will be generated only when the Tx FIFO is empty. For
most applications a threshold of zero can be used. If the
threshold is dynamically configured, i.e. it is being
modified during operation, then the Tx FIFO level
must be checked before writing data to the transmitter.

5.2 Transmit Operation
5.2.1.1 Transmit Interrupt Handler

5.2.1 GENERAL OPERATION

To transmit a character the CPU must write it to the
TXD register, this character along with the flags from
the Tx Flags register is loaded to the top of the TX
FIFO. If the Tx Machine is empty, then the character
is loaded into the shift register, where it is serially
transmitted out via the TXD pin (the flags are not
transmitted unless the 8251O's configuration requires
their transmission e.g. if software parity is selected then
the S/W parity bit is transmitted as the parity bit of the
character). The CPU may write 'more than one character into the FIFO, it can write four characters in a burst
(five if the Tx Machine is empty) or it can check the
FIFO level before each write, to avoid an overrun condition to the transmitter. In the case of the latter, the
software overhead of checking the FIFO level must be
less than the time required to transmit a character, otherwise the transmit routine may not exit until another
exit cO,ndition has been met.
e.g. at 288,000 bps for an 8-bit char no parity
It takes 34.7 JLs to transmit one character.

The Transmit Interrupt Handler will be invoked when
either the Tx FIFO threshold has been met or if the
Transmitter is empty. Since the Tx Machine interrupt
is high priority (second highest priority, with Timer
being the highest), the interrupt line will not be released
to other lower priority, pending 82510 sources until the
Tx Machine interrupt has been serviced. If no data is
available for transmission, then the only way to acknowledge the interrupt is by diSabling it in the General
Enable Register. Thus the Tx Machine interrupt should
not be enabled until there is data available for transmission. The T1!: Machine interrupt should be disabled after transmission is completed.
5.2.1.2 Transmission By Polling

Transmission on a polling basis can be done by using
the General Status Register and/or the FIFO Level Register. The software can wait until the Tx FIFO and/or
the Tx Machine Idle bits are set in the General Status
Register, and then do a set number of writes to the TXD
register. This method is useful when the software is trying to manage other functions such as modem control,
timer management and data reception, simultaneously
with transmission.

If the time, from the write to TXD to the reading of the
Transmit FIFO level, is greater than 34.7 JLs then the
Tx FIFO level will never reach higher than zero, and
the FIFO will always appear to be empty. Therefore, if
the transmit routine is checking for a higher level in the
FIFO it may not be able to return until some other exit
condition-such as no more data available-is met.
This can be a problem in the interrupt handler, where
the service routine is required to be efficient and fast.

If management of other functions is not needed while
transmitting, then continuous transmission can be done
by monitoring the Tx FIFO level. A new character is
written to TXD as soon as the FIFO level drops by one
level.
2-26

Ap·401

DISABLE TX MACHINE
IDLE, AND TX FIFO
INT. REO. IN GER

Tx FIFO Threshold = 0

231928-19

NOTE:
TxM Idle and Tx FIFO Empty interrupts are enabled by the Main Program, when data transmission is required.

Figure 16.16 Tx Interrupt Handler Flow Chart

2-27

intJ

AP-401

231928-20

Figure 17. Using GSR for Polling,

2-28

inter

AP-401

231928-21

Figure 18. Data Transmission by Monitoring FIFO Level

2·29

AP-401

231928-22

Figure 19. Break Transmission Using Tx FIFO to Measure Break Length

2-30

AP-401

read characters from the 82510. Each character on the
Rx FIFO has flags associated with it, all of these flags
are generated by the Rx Machine during reception of
the character. These flags provide information on the
integrity of the character, e.g. whether the character
was received OK, or if there were any errors. The receiver status is provided via the Receive Status Register
(RST), which provides information on events occurring
within the Rx Machine, since the last time RST was
read. The information mayor may not apply to the
current character being read from the RXD register.
The CPU may read one or more characters from the
Rx FIFO. After each read, if the FIFO contains more
than a single character, a new character is loaded into
the RXD register and the flags for that character are
placed into the RXF register. The software can check
for the Rx character OK bit in the flags to make sure
that the character was received without any problems.

5.2.1.3 Break Transmission

The 82510 will transmit a break when bit six of the
Line Control Register is set high. This will cause the
TXD pin to be held at Mark for one or more character
time. The Tx FIFO can be used to program a variable
length break, see Figure 19 for details. If the break
command is issued in the midst of character transmission the TXD pin will go low, but the transmitter will
not be disabled. The characters from the Tx FIFO will
be shifted out on to the Tx Machine and lost. To prevent the erroneous transmission of data, The CPU must
make sure the Transmitter is empty or disabled before
issuing the Send Break command.

R
X
F
I
F

OVERRUN

........ .-----

4

o
L
E
V
E
L

3

,,
~

--2
THRESHOLD

5.3.1 RECEIVE INTERRUPT HANDLER

The Receiver will generate two types of interrupts, Rx
FIFO interrupt and Rx Machine Interrupt. The Rx
FIFO interrupt requires that the CPU read data characters from the Rx FIFO. If the Rx Machine interrupts
are disabled then the CPU should also check for errors
in the character before moving it to a valid buffer. The
interrupts generated by the Rx Machine can be divided
into two categories-occurrence of errors during reception of data (parity error, framing error, overrun error),
or the occurrence of certain events (ControllAddress
character received, Break detected, Break Terminated).
For typical applications, the error status of each received character can be checked via the Receive Flags,
and the events can be handled via interrupts.

.. " "

,

I

I
~

•,

,,
~

O~--~--------------------~r---

INACTIVE

INTERRUPTS

ACTIVE
231928-23

•• _. User Read Operations
82510 Character Reception

5.3.2 RECEIVING DATA BY POLLING

Figure 20. Rx FIFO Hysteresis

To receive data through polling. the 82510 can use the
General Status or the Receive Status Registers to check
for the Rx FIFO request. If the Receive routine does
not generate time outs or modem pin transitions, then
the data can also be received by monitoring the Rx
FIFO level in the FIFO Level Register. The implementation using GSR would be useful in applications where
the software routine must monitor the timer for time
outs or the modem pins for change in status. The example polling routine illustrates the use of the FIFO Level
Register in receiving data. It waits for the Rx FIFO
request before beginning data reception. The procedure
Rx_DataJoll will receive the number of characters
requested in Char_count and place them in the Receive buffer.

5.3 Data Reception
The receiver provides the 82510 with three types of
information:
a) Data characters received
b) Rx Flags for each data character
c) Status information on events within the Rx Machine.
The Rx FIFO interrupt request goes active when the
Rx FIFO level is greater than the threshold, if the interrupt for this bit is enabled then it will generate an
interrupt to the CPU. This is a request for the CPU to

2-31

inter

AP-401

231928-24

Figure 20. Rx FIFO Interrupt Handler

2-32

inter

AP-401

#define base Ox3F8;
/* base address of 82510 */
#define buff __ size 128;
RX __ Data __ Po11 (Char __ count, Rxbuffer)
int Char __ count;
/* Total # of bytes to be received */
char *Rxbuffer [buffsize];
{

int count = 0;
int status, lvI, Rok;
While (((status = (Inp(base+7) & Ox05))
{

OxOl) /* If Rx FIFO Req in GSR set *1
/* Assume in bank one */

/* If Rx FIFO is not empty */
While ((IvI = ((Inp (base+4) & Ox70)/Ox10)0&&(count < (Char __ count))
{

/* If Character Received OK */
if (((Rok.= (Inp (base+l) & Ox60))

Ox40)

(

Rxbuffer [count] = Inp (base);
++count;

Figure 21. Example Polling Routine

ters (e.g. abort) can be received at any stage of communication, these can be received by using the Control
Character Matching capabilities of the 82510.

5.4.3 CONTROL CHARACTER HANDLING

The 82510 has two modes of control character recognition. It can recognize either standard ASCII or standard EBCDIC control characters, or it can recognize a
match with two user programmed control (or Address
Characters in MCS-51 9-bit mode, for Automatic Wake
up) characters. Each mode generates an interrupt
through the Receive Status Register. The Receive Flags
also indicate whether the character being read is a control character. The usage of CCR depends on the maximum number of possible control characters that can be
received at anyone time. Applications such as Terminal Drivers, which have no more than two control
characters outstanding, such as XON and Ctl-C, or
XOFF and Ctl-C, can use just the Control Character
Match mode by programming the registers ACRO and
ACRI. If the CPU needs to process text on a line by
line basis, the standard Control Character recognition
capability can be used to determine when an end of line
has occurred e.g. a whole line has been received when a
Carriage Return (CR) or Line Feed (LF) is received by
the UART.

5.3.3 BREAK RECEPTION

The 82510 has two status indications of break reception, Break Detect indicates that a break has been detected on the RXD pin. Break Terminated indicates
that the Break previously detected on the RXD line has .
terminated and normal Data reception can resume.
Each of these status bits can generate an interrupt request through the Rx Machine Interrupt request. Normal consequence of break is to abort the data reception
or to introduce a line idle delay in the middle of data
reception. In the case of the former, the Break Detect
interrupt can be used to reset the 82510 Receive Machine and the Rx routine flags; in the case of the latter,
the break terminated interrupt can be used to filter out
the break characters and resume normal reception.
Each break character is identified by a break flag in the
Rx Flags Register (the CCR flag, Framing error, and
CCR Match flag also may become active when a break
character is received) and is loaded onto the Rx FIFO
as a NULL character. If break continues even after the
Rx FIFO is full, then an overrun error will occur but
no further break characters will be loaded on to the Rx
FIFO. The user can also measure the length of the
break character stream by using the Timer.

Implementation of a character oriented asynchronous
file transfer protocol can be done using both standard
and specific Control Character Recognition. In such
protocols most control characters such as Start of
Header (SOH), can only be received during certain
states, these characters can be received via Standard
Control Character Recognition. A few Control Charac-

2-33

inter

Ap·401

RXMINTERRUPT-.

READ DATA CHAR

READ CONTROL CHAR

YES

READ DATA CHAR
READ CONTROL
CHARACTER

231928-25

Figure 22. Handling Control Character Interrupts

2-34

inter

AP-401

SPECIAL CTL-CHARACTER

=XOFF
XON

CTL-C

NO

231928-26

Figure 23. Uslrig Control Character Match in Terminal Ports

2·35

intJ

AP-401

5.3.4 DATA INTEGRITY

To improve the reliability of the incomIng data the
82510 provides a digital filter, a Digital Phase Locked
Loop, and multiple sampling windows (which provide a
noise indication bit).
5.3.4.1 Digital Filter

The Digital Filter is used to filter spikes in the input
data. The Rx Machine uses a 2 of 3 filter. The output is
determined by the majority of samples. If at least two of
the three samples are "I" then the output will be a "1".
Spikes of one sample duration will be filtered but spikes
of two or more samples duration will not be filtered.

The sampling windows also provide a Noisy character
bit in the RXF register. This bit indicates that the current character being read had some noise in one or
more of its bits (all the samples were not in agreement).
This bit can be used along with the Parity and Framing
error bits to provide an indication of noise on the channel. For example, if the Noisy Character bit and the
Parity or the Framing errors occur simultaneously,
then the noise is probably sufficient to merit a complete
check of the communications channel. The noisy bit
can also be used to determine when the cable is too long
or the baud rate is too high. The user would keep a tally
of the noisy characters, and if more than a certain number of characters were received with noise indications,
then either the baud rate should be lowered or the distance between the two nodes should be reduced.

5.3.4.2 Digital Phase Locked Loop

5.4 Timer Usage

The Digital Phase Locked Loop (DPLL) is used by the
Rx, Machine to synchronize to the incoming data, and
adjust for any jitter in the incoming data.

The 82510 has two baud rate generators, each of these
can be configured to operate as Timers. Typical applications use BRG A as a BRG and BRG B as a Timer.
Since both the Transmitter and the Receiver may need
to generate time outs, it is best, to use the Timer as a
Time Base to decrement ticks (upon a Timer Expired
Interrupt) from (software implemented) Tx and/or Rx
counters. The Timer can also be used to time out the
Rx FIFO and read characters that otherwise may not
have been able to exceed the Rx FIFO threshold.

The 82510 DPLL operates on the assumption that a
transition in the incoming data indicates the beginning
of a new bit cell. A valid asynchronous character frame
will contain one or more transitions depending upon
the data. If upon occurrence of the transition, the
DPLL phase expectation is different from the sampled
phase, then there is jitter in the incoming data. The
DPLL will compensate for the phase shift by adjusting
its phase expectations, until the expected phase and the
sampled phase are locked in. The user can enable or
disable the DPLL through the Receive Mode Register
(RMD).
.

5.4.1 USE AS A TIME BASE

The transmitter and the receiver routines use a software
variable which acts as a counter. The variable is loaded
with the required number of ticks that are needed for
the Time Out period. Once started the Timer generates
an interrupt each time it expires, the interrupt handler
then decrements the counters. Once loaded the software mouitors the counters until their value reaches
zero, this would indicate to the software that the required time period has elapsed. The Time Base value
should be selected with regards to the CPU interrupt
load. The CPU load will increase substantially when
the Timer is used as a Time Base, therefore using the
Timer in this mode at very high baud rates may cause
character overruns. A time base of 5 or 1 ms is probably the most useful. An additional benefit of the Time
Base is that it can support more than two counters if
required.

5.3.4.3 Sampling Windows

The' sampling windows are used to generate the data
bit, by repeated sampling of the RXD line. The bit polarity decision is based upon a majority vote of the samples. Ifa majority ofthe samples are "I" then the bit is
a "I". If all samples are not in agreement then the
Noisy Character bit in the RXF register is set. The sampling windows are programmable for either 3 of 16 or 7
of 16. The 3/16 mode improves the jitter tolerance of
the medium. While the 7/16 window improves the impulse noise tolerance of the channel.

2-36

Ap·401

5.4.2 USE FOR RX FIFO TIME OUT

BRG·B is used as Timer.
BRG·A is used as BRG.
TB Ex bit in TMST Enabled.
TlL-Timer_Count contains count for Transmitter.
RlL-Timer_Count contains count for Receiver.

In the 82510, Rx FIFO interrupts will occur only after
the FIFO level has exceeded the threshold. Due to this
mechanism and the nonuniform arrival rate of characters in asynchronous communications. there is a chance
that characters will be "trapped" in the Rx FIFO for
an extended period of time.
For example, assume the 82510 is a serial port on a
system and is connected to a terminal. The user is entering a command line. The Rx FIFO Threshold = 3,
and at the end only two bytes are received. Since the
FIFO threshold has not been exceeded, the Rx FIFO
.interrupt is not generated. No other characters are received for 30 minutes, if the characters (in the Rx
FIFO) are a line feed and carriage return, respectively,
the CPU may be waiting for the CR to process the
characters it has received. Consequently the characters
will not be processed for 30 minutes.
In order to avoid such situations, a Rx FIFO Time Out
mechanism can be implemented by using the 82510
Timer. The time out indicates that a certain amount of
time has elapsed since the last read operation was performed. It causes the CPU to check the Rx FIFO and
read any characters that are present.
In applications where the character reception occurs in
a spurious manner (the exact number of characters cannot be guaranteed), the Rx FIFO Time Out is the only
way to prevent characters from being trapped. The time
out period is measured from the last read operation,
every read operation resets the Rx FIFO Timer. To
synchronize with the beginning of the data reception,
initially the Rx FIFO threshold is set to zero. After the
first character has been received. the threshold is adjusted to the desired value. When a Rx FIFO time out
occurs and no data is available, the threshold is reset to
zero. In error free data transmission, the beginning of
data transmission is signaled by the reception of a control character, such as SOH or STX, the Rx FIFO time
out mechanism should be triggered to the reception of
these control characters.

231928-27

Figure 24. Timer use as Time Base for Transmit
and Receive

2-37

AP-401

(

MAIN RX ROUTINE)

RX FIFO INTERRUPT ROUTINE

231928-28
231928-29

Figure 25. Rx FIFO Time Out Flow Chart

2-38

inter

AP-401

8 BIT

ONE'S
COMPLEMENT
Of" PACKET
NUMBER

128 BYTES
Of" DATA

8 BIT

128 BYTES

CONTROL
CHARACTER

231928-30

Figure 26. Packet Structure of XMODEM

6.0 82510 IMPLEMENTATION OF
XMODEM

6.2 Software
Interrupts are used to transmit and receive data. The
software is implemented as two independent finite state
machines-Transmit State Machine and Receive State
Machine. Each state machine is triggered by external
events such as user commands and data or Control
Character reception. The state machines communicate
with the 82510 interrupt service routines through software flags. The overall structure of the main routine is
given in Figure 31. The major modules of the software
are given in the hierarchy Chart, Figure 34, which lists
the different modules in order.

The 82510 XMODEM implementation is a file transfer
program for the 82510 based on the XMODEM protocol. The software runs on the PC AT on a especially
designed adapter board (the adapter board design is
shown in Figure 33). The software uses most of the
82510 features including the baud rate generator, Timer, Control Character Recognition and FIFOs. The
software uses an interrupt driven implementation, written in both assembly and C languages.

The interface between the main program and the interrupt service routine is done through global flags. The
interrupt handler services four sources-Transmit,
Timer, Receive, and Control Characters. Each of the
interrupt sources communicates with each of the state
machines through the global flags. The state machines
keep track of their individual states through state variables. The interface between the individual states within
a state machine is done through state flags. The state
machine diagrams are given in Figure 29 and Figure

6.1 XMODEM Protocol
XMODEM is a popular error free data transfer protocol for asynchronous communications. Data is transferred in fixed length 128 byte packets, each packet has
a checksum for error checking. The packets are delineated by control characters, which act as flags between
the Receiver and the Transmitter. There are four control characters, SOH, EOT, ACK, and NAK. SOH indicates the Start of a Packet, EOT indicates the End Of
Transmission; ACK and NAK are positive or negative
acknowledgements of the packet respectively. The
packet structure and protocol flow of XMODEM is
provided in the figures given below.

30.

2-39

AP-401

(

TRANSMIT)

NO

ASSEMBLE
NEXT PACKET

231928-31

Figure 27. Protocol Flow for Transmit Side of XMODEM

2-40

intJ

AP·401

SEND NAK

SEND ACK

RX PACKET #
AND PACKET COMP

231928-32

Figure 28. Protocol Flow for Receive Side of XMODEM

2·41

AP-401

231928-33

Figure 29. Transmit State Machine

2-42

inter

Ap·401

4 SEC TIME OUT
AND <10 TIME OUTS

231928-34

Figure 30. Rx State Machine

2-43

inter

AP·401

mit interrupt service routine reads characters from the
packet buffer and writes it to the Tx FIFO. Since it
does not require the use of the Transmit Flags, no information is written to the TXF register.

START
Initialization

WHILE (NOT QUIT)
{

I

UPDATE STATUS ON SCREEN
IF (KEYBOARD HIT)
THEN PROCESS COMMAND
PROCESS TRANSMIT STATE MACHINE
PROCESS RECEIVE STATE MACHINE

6.2.2 RECEPTION OF DATA

Data reception begins only after a Start of Header
(SOH) control character is received. This control character puts· the receiver in a data reception mode. After
receiving the SOH, the CCR interrupt is disabled (since
all data being received now is transparent and can not
be interpreted as a control character). After 132 characters are received, the CCR interrupt is reenabled and
the corresponding ACK or NAK sent to the Transmitting system. The receiver has a time out feature, which
causes it to check the Rx FIFO for any remaining characters. End of Transmission is indicated by an EOT
control character, which causes the file to be closed and
the Receiver to go into the Idle state.

END
Figure 31. Software Structure
6.2.1 TRANSMISSION OF DATA

The Transmit interrupts are disabled until data transmission is required, this prevents unnecessary Transmit
interrupts. The Transmit interrupt is enabled when a
packet has been assembled or if a Control Character is
required to be transmitted. Upon invocation the Trans-

r--------- SEND_CCR_RQ(F'ROM RECEIVE STATE MACHINE)
TX
STATE
MACHINE
CCR_TO_GET
GELCCR_RQ

t~~
RX
STATE
MACHINE

BYTES RXD

RECEIVE
231928-35

Figure 32. Using Flags for Communications with Interrupt Routine

2·44

l

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RESET
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INT
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231928-36

l
'TI

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CD
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()

CONVIG_510

INILINLHANOlER

@]~
WAIT

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:::.

231928-37

AP-401

6.3 Software Listings
PACE

ttp.c

MAIN FROCnAM

82510 XMODEM

'include "C:\ftp\ftp.dtlf"
Z. linclude "C.\Ic:.\fcntl.h"
3. 'include "C' \Ic\s'tdlib.h"
4. 'include "C.\le\ltdio.h"
5 , •••••••••••••••••••••••••••••••••••••••••••••••• ,

.......... ,,

,u.

6.,
7. , .. .

a. , ... .

.tUt,

SEPTEMBER 198&

9. ,...
82510 I"ODE" IMPLEMENTATION
..... ,
10. / ................................................. ,
11. tnt
eof,=falui
end of f i l l flag
12.

int

13. tnt
14. tnt
15.
U.

tnt

tnt
11. tnt

18.
19.
10.
11.

12.
23.

24.
25 .
U.

Int
Int
Inl
Int
Int
Int
int
int
Int

'*

npt =0;
tirO;;
ruflg;
up_plct_null.
pht;

::I

1j

fltocnti

'*

*,

ne.t picht nUllbu IIpleled by reclinf *1

for rlt.her

J' Time Out countll'

.

to,

0;
lohent .0 ;

ulent .0 ;
cerc.nt .0 ;
tI_5t&te .h_idll j
rI_state = rI_idhi
inacti.,.;
la_cad
inact h i i
fl_cad

..

/'
/'
/'
/'
/'
/'
/'

• of 5011 chifactul rlceivld ./
of HI FnO Intl1'rupts ./
of Ct IMChu. Interrupts ./

Tunsa1thr Stah Variable .,
Rec.lur State Variable .,
Indicates I Valid T. C01lalnd wu ginn ./
Indicatas I valid ftl COIDmand was illued .,

27.
28. /* rile to ba Tl'ln.1lltted ./
29. chl1'
h_flla_nl1lel401.
30.
31. ,. Fila to be Received .,
U. char
1'._fl.la_namet401.
33.
lend_CCf_l'.q :r: inaetive;
34. lnt

It F!aQ

3S.

int

Inh.c .OJ

,. contains the

36

Int
chAr
char
chit'
char

I;

37.

38.
39.
40.
4\.

42.

43.
44.

Request to T. Ctl-Chu .,

GIft VIctor .,

,. TI Bufhl' '1
,. RI Bufhr ./

rlbuf tUt];
rldatao [131l;

,. R.

"_'_bu' [32000];

ri I,

Stoud In thh bufhr

*'

*•• *••••••••••••••••••• ,
, ... tl state variables ..... ,
, •••••••••••••••• *••••••••••• ,

4S. int

n.

t.data [lU1j

~

/ •••••

H.
47.
48. struel
49.
50.

'1.

*'

quit IIIlI!!!;

I' Polntlt to the nut charlctlt' in the
buf fer

tl_indl;

picket
char
char
char
chit
char

t,

held i
pa.ct_nulli
pack_cmpl;
buff I t [128] ;
chkl1li

53.
54.
55.
56. struct pact.t 1'lpaclc, hpaeti
57.

231928-38

82510 XMODEM Implementation

2-47

intJ
PACE. 2

Ap·401

"AIN PROCRAH

lip.

t._._

82510 rHODEM

t._

58.
59. I II t t II • • • • • II t • • • •
lit .... t • • • t • • _
t • • • • • • • • • • • • • • t. I
60. ,....
h State •• chine Ind inhrrupt
...... ,
61. ,....
handler flags
.... ul
62 .. /* II • • • • • • • • • • • • • t •••• t . t t*t.t. t t • • • • t . t •••• t . t

t*_.t.

I

tt

63.
64.
tam and tI fifo
6S. int
tl_uq .OJ

'**

u.

tt, /* FI.g - indicates a requut for tran.mission
IlSl0 Inhrrupt Hlndler
cct_to_h
OJ ,t Actual Ctl-char to Trans.it *1
h_byh_c.nt .. OJ
of aytes Trans.ithd ./
ptts_slnt .0;
,t.Total'
of Pickets sent

to

*/

&:
int
It
int
*/
" . int
70.
71. , .. Timer
.. ,
71. tnt
tI_tiae_c.nt =0; f. Trans.ttter Timer Counter */

67.
68.

73.
74.

75.
76.
17.
71.
79.
80.
11.
8Z
13.
84.
15.
16.

, .. Ceft .. ,.

int

aet_e:u_rq =0;'

int

cu_h_get

't

Flag - Request to Ree.he Ctl-charaehr */
.0. f. Rec.it,d ell-char n,lue *1

t._ ....

'*""' •••••••• ,

..........,,

, •••••• *t •• llttt • • • • • • t . t . t lI.t t • •
tlll.* • •
/....
.. ... ,
, .. ..
HI STATE VARIABLES
, ... .
• •••• I
, .. ..
, •••••••••••••••••••••••••••••••••••••••••••••••••••••••••• /
char

17. 'int
88. tnt

pk_chts.i
eot_cnt cO;
bl.d_pkt_cnti

,. Calculated Chhua .,
, • • of EDTs Reeeiud .,
'*. of aad Packets RecelYed

*/

19.
fO. / ••••••••••••••••••••••••••••••••••••••••••_••••••••• ,
91. ,....
n state mlchine and Interrupt'
..... ,
92. , . . . .
handler flagl
..... ,
f3
, ••••••••••••••••••••••••••••••••••••••••••••••••••• /
94.

'**

95.
n
" . Int
97.
U.

**,

hID
rK_b,te_cnt .. 0 i

/ • • of a,tll R.c,lud .,

, .. eCR ttl

n.
100 lnt
101.
102. int
103.
104. Itt Timer
105. int

'*

Flaq-IndieatinljJ that a Ctl-Char. has b.en
uelifd"

I ' Actaal Ctl-ebar rec:.elVed .,

**'

,. Reeene Til.. r Count .,

82510 XMODEM Implementation (Continued)

2-48

231928-39

Ap·401

f I p .t

HA III PROCRAH

PACE

82 5 I a XHODEH

10& .

107.
108.
109.
110.
III.
112.
113.
114.
115.
116.
117.
III.
119.
120.
121.
122.
123.
124.
125.
126.
127.
118.
U9.
130.
131.
132.
133.
134.
135.
136.
'37.
138.
139,
140.
141
142 .
143.
144.
145.
IU.
147.

/ •••••••••••••••••••••••••••••••••••••••• /
,..
HUN ROUTINE
, •••••••••• tt • • • • • • UI • • • • • • • ,U • • • • • • fI • • • • • /

.U,

1Iain

()

(

q.tlfl,uf1;
.0,
r,al"
0,
cad
wn_statul .0,
0,
ee,odl
t fp;
trlfp;
rWlt;
west;
utl_cnt .0,
tocnt .0,
t I_sees t rl_,.c5
i 1St lpent
A'

lnt
,nt
lnl
inl
int
r! LE
rILE
int
lnl
lnl
int
Inl
int

.

.

.

/' Rlt unsmi t count ' /
/' TilDe Out Count ,/
j

eLR 0,
ttV_CURS (so_r,so_c)j
prlntf (sl);
ini I (),
HENU 0,
tnbint4 OJ
Qutp (tpOO,laU;
Gutp «bp&+3),OI2U;
Jpcnt =0;

/' Cllar Settln '/
/' SiQn On KIlSioO' ' /
/. Initialize 82510 and Vu hbles '/
/' PI int Klnu ' /
/' En&b Ie Interrupti in 8Z59A '/
,/
/' illUI ED!
/' shrt t i.er B ,/
Keepl
Track
of
I 01 Loop. ,/
/'

/ .................................................... /
.Iin while loop
'U',

,t..

/ ••••••••••••••••••••••••••••••••••••••••••• 111 •••

.,1:.,

while (quih=falsl)
(
, ••••••••••••••••••••••••••••••••••••• ,
display protocol par.aeleu
ttl

'tt

,.*** •••••••••••••• *•••••••••••••••••• ,
++ lpcnt;

148.

IIlV_CUfl (4,30);

149.
150.
151.
152.
153.
154
155.
156.
151.
158.
159.
160
161.
162.
163.
164.
US.

print! ("loop' • IfIu",.pcntJ;
mv_cuu (4,50);
printf (lin i~t. cnt :I 'Au",nfcnt),
In_curs (5,501,
printf ("eu tnt cnt II 'u",eerent),
mv_curs (4,1);
printf ("interrupt ,.etor .. ,"U \n", intvte);
q II tnp (bp&+4),
hO I; q & 0101,
mY_curs (S,Ui
prsntf CUTX FIFO II "U ",hO);
q II inp (bpa+4);
rdl II q , 0110;
.,_ears (6,1),
printf (l'RX FIFO. 'Au \n",r1fl/l6)i
.v_curs ",50) i
printf ("SOH coant & . . 3a .... ohcnt);

231928-40

82510 XMODEM Implementation (Continued)

2-49

AP-401

PACE

IIA1N PROCRAII

4

1"

82SI0 XIIODEH

ftp.<

my_curs (1,1);
prlntf ("bytes received 'IUu".u_bJh_cnt),
mv_curs (7,30),

167
168.

169.

printt ("Iyt .. sint .. "3u".II_byte_cnt);

170.
171.
172.

.,_curs (7,50);
printf ("EaT count
.,,_ears (5,30);

173.
174.
175.
176.

printf ("pttl tad . . .3u",CI.p_ptt_nulD-l»;
8"_curs <6.30);
printf ("ptts 'Int
11311", pttl_"nt);
tI_'tU = lI_tl.,_cntl200i
tI_net 1:1 rI_tia._cnl/ZOOi
op.n_wind (3,l,"TI Tiatt");
printe COl. "2u slc.",ll_SICI);
open_wind (3,'50,"RI Tlau");
prinU COO ."2u Ile.",II_I.e..);
.,,_curt (I,U;
pr int f ("Bad Packets ad • "3u" I bad_ptt_cnt)
.,,_curlU,30);
prlntt ("I of ReTa pachtl . . . 3u lO ,reh_cnl'j

118.

179.
110.
II..
112.

:::.
191.
192.
193.
194.
195.
196.
19?
198 .
199 .
200.
101.
202.
203.
204
20S.
206.
207.
201.
209.
210.
211.
ZI2 .
213.
214.
ZlS.
216.
217.
218.
119 .

no.

221.
222.
ZZ3.

124.

lot_ent);

=

177.

183.
114.
115.
116.
111.
188.

"h n ,

'*

j

If Co •• and lI.uld then procllIi the Comllind ./
If ((ke, .kbhlt()) ) 0)

quit

.11.
I

I'"

prae.e.,_cad OJ

,........................................................,
Procu.
It ... ,
revision
,
, ••• *•••••• *•••••••••
*•••••••••••••••••• , •••• ,

,.....

,.....

.....

Ta STATE MACHINE
0

aa ••• ,

, ••• a.

a •••••••• a ••

Iwitch (la_ltate) (
CIII h_idle:
"

••••••• t ••••• , •• , t ••••••••••••••••••••

*•••••••••••••• ,.,

,....

,It..
I....
lit..
lit..

,.* ••

tUtti

TRANSMITTER IDLE STATE

Checks for I. Send Ct I-Char.
Chick. for the Transmit Co •• and

I····

.It".,
.... ,
.. ... ,
... ttl

.....,
*** •• ,

, ••••••••••••••••••••••••••••••••••••••••• a •••••••••••••• I

I. II Control Character to b. Transmitted Thin Transait the

Control Ch4racter b, ,ettino thl TI_teq Uag and enabling
the TIM and Ta FIFO interrupts .,

h_uq -c t1_chr;
h_i_enb () j
whill'( h_uq)O);
h_l_d is ();
.Ind_ccr_uq_ inact I,,;

22S.

231928-41

82510 XMODEM Implementation (Continued)

2-50

inter
PAC£

126.
127.
HI.
129.
230.
131.
23% .
233.
234.
235.
236.
237.
238 .
239.
240.
241.
242.
243.
244.
245.

AP-401

HAIN PROCRAH

5

lip .•

12510 IHOD£"

/t If the Ttlftlllit C01l1und is 'Sluld then Wait for a HAlt
if Ctl_cmd
&CliVI)

gtt_c.cr_rq .act in;
tl_timl_cnt .. 200"0; /* '0 IIC. Tia. Out
h_ltatl • wut_HAlti

'*
..... .............................•...................
..........,
....
..........,
\rI&itinQ for

,....
/
J

/* •••• I

UI.

269.
270.
271.
272.
273.
274.

275.
276.
277.
171.
279.
ZlO.
211.

Chick. For 71 •• Out
or HAlt Recelnd

• • • • • *t •••••

..... ,

*t. til 'II: 11;. *lII.t . . . . . . *•• t
()j

•• t.

/

*•••••••••••• */

1* Ti •• Out or NAK Re::,d? */

(

'*

If Ti •• Out thin Abort
Tun •• iI.ion *1
tl_stat. .tI_idhi
bliP ();
pra'l) C"Tl •• OUT! I!' Etceher not Etld,") j
ell Ctl_r. tI_c)j
open_wind Ctl_r,tl_c."NONE")j
brllk;

easlI watt in;
break

'*

if no Tilll Out Ind no NAft
rc,d thin do nothinG */

j

/* If NAK. reclh.d th.n Opln
~ i Ie Ind Idunc. to
Tranlllloit 'Ick.t atlt. *1

fp .Iopen Ctl_Iill_nl.I."rb" );
if Cfp •• NULL)
I
hip ();
pr." ("ERROR III fill do .. not I.ist");
ell Ch_r.tI_c);
0Pln_wind Ctl_r.tl_c, "nonl");
tl_ltate sh_idll;
I
lIse
'h_state • tI_rdy;
tlrfl; • akptt;
WD_ltatUI • OJ
I

21Z.
213.
214.
215.

*'

,/

/

It..

,....

switc.h Cwn_,tatus)

257.
251.
1S9.
260.
261.
262..
263.
264.
265.
266 .
267.

NAl c.h&uc.ter to blain 11

TRANSKISSION.

wn_ltatus = chick_wait

254.
255.
256.

&

_
,.... TRANSMITTER \lAITINe FOR A HAlt TO BEC IN
/

246 .

251.
252.
253.

*'

br.at;
c.ase wait_NAl :

247 .

241.
249 .
250.

*'

I

,. First tut for TI

il to Prepare Pactet *1
1* R••• t Vlit_NAK FlaG *1

brelk;
I

brlat; 1* end

Witt nit *1

231928-42

82510 XMODEM Implementation (Continued)

2-51

inter
PAGE

Ap·401

"AIN PROGRAM

8251D 'MODE"

tI_rdy:

216 .
287.

CIII

218.

/ ....

J• •

IIp.e

t ••••••••

tt III • • • • • • • • • • • • • • t • • • • • • • • • • • • • • • • • • • • • • • • • • • ,

TANSHITTER READY TO TRANSMIT

flit . . . ,

219 .

,....

thr .. st&91. of tranl.Jllion

tt . . . ,

29D.

,....

pr.pau plet,t

.Utt/

HI.
292 .
1f3.
294.
29$ .

,....

Int. Handler Tunsaitting ... ttl

296.

,*

/....

In.

..... ,

t. t t • • • • • • • • • • • • • • • • • • • • • • • • • • • • t • • • • • t • • • • • • • • ,

*'

1* Any Control Character To TransaU?
Ullnd_cc:r_,eq •• lethe) " (u_req,u:'»

if

tI_r.q aetl_eh"

H7.
H8.
3DD.
3DI.
3DZ
3D3.
3D4.

or rettan.att rlqul.t

It t • • • • •

/* Vhich ShOt of transmilsion ,./
switch (tuflg)
(

CIII

.ltpt t :
if
(tI_uq •• O)

/' Preplre 'Ictet

'/

(

30$ .

... bptt (ptts_sent.fp);

3D6.
3D7.
3Da.
309 .
3\D.
311.
312 .
313.
3\4.
315.
316.
317.

epylbul () i
tI_r.q .ptt;

/' R.qulst Int. Hlndler
to TI data in buffer '/

t i f f I'll =hatgi
tI_iftd • • Q j ,
h_i_lnb () i

brllt i
Casl hat'll
if Ch_req

c.

/' A. . . . bh 'Icket */

/' St I f t Tt In •• tnt on

*'

/' Enable TIK and TI FIFO
Inhrrupts '/

/* Interrupt HaRdIn R... t,
thil f lag to 0, wbln 132
b,llS UI tran •• Utld ' I

D)

318 .
319 .
32D.

321.
3U.
323.
324.
32$ .
326 .
327.
328 .
329 .
33D.
331.
332.
333.
334.

h_lndl .OJ

pra.g ("pactet tunlmUted")
get_eel_'ll aacU,,;
tl_Ua,_cnt • 100'1Oi

tI_ltate • wlil_CCi
tarfl; •• tpktj
tI_l_dil ();

Interrupts *1

else
brut

1* Tz_req not t . . lt then
pr •• a ("tranIIiUting");
ltill tran.aitting *1

,*

j

call uti :
outp«bPI+U,tlln)j

336 .
337.
338.

h_uq

= ptti

Th, Retrln •• tt request is
ilsued b, the Walt _CC

state

*'

Jt enable till. flulh tI fUo
& tam .. ,

1* tranlmit 'Ictet.pkt. In
bothr *1
1* nelt tnt - ReTrln •• it ./
It Enalt Ie T.M Ind TI F no

339.

hrflg ct..tv;

340 .
3U.
342.

344.
34$ .

*'

J. DiuUe T.r1 Ind TI FIFO

33$ .

343.

j

J' Wilt for ACK or HAl "
/* 10 SIC: Tia. Out
,. Wilt for ctl Charac.ter ./

h_i_Inb C);

Interrupts· ,
heat i
I
break;

'*

End tI rd, cal.

t

I

231928-43

82510 XMODEM Implementation (Continued)

2-52

infef
PACE

7

AP-401

f t p. c

IIA IN PROCRAII

82510 XIIODEH

3U.
347.

ClI. WII t_CC
/ ••••••••••••••••••• 111.,1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . /

348.
349.
350.
351.
352.
353.
354.
355.
356.
357.
358.
359 .
360.
361.
361.
363.
364.

,....
, .. u
, ... .
, ... .
, .. ..

**,
.....
..:1 •. /
.....
..*....••• ,
.....
t ..

Transmitter

St~t.

/

- Wutlng For ttl Char.

/
/

NAK
requests retransllusion
leX - Tuns.it·Nut Pacht

/
/ •••••••••••••••••••••••••••••••••••••••••••••••••••••••• I

/' Check for on. of the

wcst • check_wait ();

Following e'llnts :
Time Out

NAIt Ret.hed
leJC R.ceived
or St ill Waltlng ' /

,

Iwi t ch (wes t)

365.
366 .

/* If Time Out, then restart
T. Tiller. Abort if Tille
Out count is C)ruter than
ten */

367.
368.
369 .
370
371

372 .

,

373.

wcst =0;

374.
375
376.
377.
378.
379.
380.
381.

abort_h ();
prmsg ("receiver not responding");

(toent ) 10)

1f

)

++tocnt i
\1_t i1le_ent :1:200*10;

,. Inc.. Time Out Count .,

)

3n.
383.
384.
385.
386 .
317.

break,

1*.

c.ase WII tina

388 .
389
390.

391.
392.
393
394.
395.
39' .
397.
398.
399

if waiting,

do nothing .,

break.
1* If NAI or Corrupted

ctl .. char. tecli,..d .,
case rX_gen
prllls; ("NAI Iecel'ud n
If (retl_cnt )10)

);

'*

more than 10 attempts ,
then Abort.,

tocnt =0;
abott_tI (I;
ptmsg (tlBad link transmISsion aborled"),
)

231928-44

82510 XMODEM Implementation (Continued)

2-53

AP-401

~kGt

400.
401
401.
403'.
404 ..
405.
406.
407.
408.
40' .
410.
411.
411.
413.
414.
415.
416 .
417 .
418.
419.

8

MklN PROCRkK

HSID lKODtM

!\p.t

1* If R,tUft.mlt Count Not
I.cllded thin ,.0 back to

Ill..

Tranlmit ltagl - talt h

tetran,.it *1
tuflg autli

++ rell_cnt

i

ll_ltate all_tdYi
I

brllt i
CUI

fI_ACK:

/* ACE Rlceitld*'

pra.o ("ACK tlceivld");
rltl_cnhOj
toent • OJ

++pttl_lent

j

printf ("pUI_ltnt •
if (Iof •• ral.,)

"3u", pU'_I'nt)

no.

411.
411.
413.
414.
415.
416.

tuf IIJ .atpU j
h_.t&h .h_rdy;
I
lis'
\
pratCJ ("lInding EOT") i

427.
41B .

1* wait for Int. Handlu
to r ... t flag
tl_'_dll ();
Olt_ccf_rq =Icthl;
1* wait for Ad .,
whi I, (oet_cCf_rq •• IC~"') j
pra.v C"EDT &ctnowlldv ••• nt rlctived");
.if (ect_lo_'lt .u Ael)
,. ACK rid I Clan Fll, .,
.\
• • fcloll «(p);
abor t_t I () j
prlllg ("fil' tran •• illton co.pllh");

while (h_req !. 0) i

431.
433.
434
435.
436 ..

437.

438.

447 .

thin

tl_l_enb ();

430.
431.

441.

,. if tnd of fill,
lind EDT */

ccr_to_h • EOTi
h_uq .et l_chr;

42' .

43' .
440.
441.
442 .
443 .
441.
445.
446 .

j

1* If mOrl data to tran.m,U
thin r.hun to all:pU
stagl,lDd tJ new pl:t. *1

tl_.tat • • h_Jdhi

*'

It Return to ldlt ./

I

brut;
) I. lend wait_cc cue "
breat;
) " end twitch h ltate *1

231928-45

82510 XMODEM Implementation (Continued)

2-54

AP-401

PAGt

9

lip c

MAIN PROGRAM

82SI0 XMODtM

449.
450.

'****1111:.** ••••••••••• _.111 •• '/1 • • • • • •1'111 •••••••• " ••••••• 111**filii'.'

451.
452.

, ... ..
, . . . ..

453
45 11

' •• _111.*** •• '/111: • • • • • • • 11 •••••••••••••••••••••••••••••••••••• /
switch In_state)

,

455
456.
457.
4SB.

459.
460.

461
462.
463.
464.
465.
466 .
467.

*** __1/

Process R. STAT£ HACHINE

,.....

[IV

is ion 0

(

case II_idle:

/ •••••••••••••••••••••••••••••••••••••••••••••• '1, •••••••• ,
,....
.. ••• /

f····
....
,f····
........
.....
l'III:·····················*····,···t....................
, .... RECEIVER IDLE:

..... ,
• • • • 111{

/

WJ.tll for user cOllmand
befote sending NAK.

• • • 111'

/

/*

469.
470.

II_ltatl

472 .
473.
474

u_t imt_cnt .100*' 0;
[a_cmd = in~ctive;
break i

........................................................
,....
.......... ,,
.....
.
,,...
..... ,,,
.....
,,...
.........
.......... ,,
,....

,

cise tl_rdy:

, .... RECEIVER READY:

/

sends NAK upon Time Out
or checks for SOH
or EDT ctl-chu.

, • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • t t •• t • • • • • • • t • • • • • • • • • • • /

/. Checks HI Tilller ind returns
Tillie Out if tlpirtd
Witting if not .. pind
SOH if SOH ecr receiud
EOT if EDT ecr received ./

4?1
492 .
193.
194
195.
4H.
197.
198.

Iwitch (urf1g)
(

ciSe wiiting:

easl

SOH

499
502.
503.
504.
50S.
506.

/. If wa.iting then do nothlng .,

bre~k i

500
501.

It Teeelu Com.m.and is illutd
thin Itut RI tilltr and thangl
Rec:.livtr stat. to rudy 1/

= rl_rdy j

471

415.

/

*.*/

468

476 .
477.
478 .
479 .
480.
411.
482
483
484
485.
486
487
488
489
190

• •• t*,

.. .. ii/

++

/. If SOH received,

then go into
da.ta reclpt ion modi lnd cha.nge RI
Timer eo~nt to 4 UCI . /

sohent;

,,_stitt cu_pkt;
u_U.e_cnt .100.4, ,. four ucond thu out .,
rxtocnt =0;
bruk j

231928-46

82510 XMODEM Implementation (Continued)

2-55

inter
PAGE

"

AP-401

"AIN PROCR""

ftp.Co

82510 ZHODE"

,- U tim. out I not In tI•••• d.t of
packet rec'ptlon thin und HAl ./
If CC "p_pU_Dua . . I) " tu_'ytt_cnt .. 0»

507.

Ha.

so,

510.
511

{

COl" tI •• out IIIII tlndlnG'
if (s.nd_cn_uq .. )nae.th.l

pt •• ,

,

'11

'I'

514.

e.cr_tO_h .NAX. j

'15

stnd_cer_r'lI .act i •• ;

'51'
16

"A''''.

ra_lim'_CDl _ZOO*lO,

511.

break,

519 .
520,

"I
51.

,t

CUt EDT-

523.
'524.
$%5.

51'

II End Of Tut rewd,
and data rewd th.n
und lCX: and .... a 11
p.chls reethld in
Hit "

.... lot_cnt;
open_wind ,val)i
reset_did (00',
I

lUte 'act,norall

.,

I. RHD - ASCII CCR,dl5lble dpl1,7/U sllIpl
J. window, absolute start bit sampling
,tTHD _ manual aode, 2. stop bits

.,
.,
.,
.,

I. lliD - RI FIFO depth =4,
It local

loopbact

tl

It no 9-bit char, no s/w parity
FHD _ R. fifo Threshold. 3

,II'

It T. fifo

threshold =0
I. RIE - Enable fa interrupts

""
"

"It
"
"
"
"lie
"/.
""
/ t

HOD EM CONFIGURATION
CLCF - 161. aRGA
BDL

- for :ims base

BBH - fo r 5 ms ba u

Bocr -

5J5 c:.1t 50uree, timer mode

11'/

./

"
"
"
"
"
"
'/
"
"
"
"
"

"
THIE - Timer B interrupt enable
"
"
BANK 0 FOR GENERAL CONFIG
"
/. GER - .nab 1 e timer, tI, CCR
"
I. block interrupts
"
It LeR - disable parit"
8 bit char
"
"
"
"
"It BRGA divisor =OlEOH for 1200
"/
/. t t t t t t t . t •••••• t ••••• tt ••••••• t ••••••••••••

=

231928-52

82510 XMODEM Implementation (Continued)

2-61

inter

AP-401

PAGE 16

839 .
840.
84 I.
84Z.
843 .
844 .
81S.
846 .

"AIN PROGRA"

ftp .•

82510 I"OOE"

....
..
....
,................................................... ,
, • • • • • • • • • • • • • • • • • • • • • • • Ul • • • • • • • • • • • • • • • • • • • • • • • • /

/
/

/

Set DLAB llit to &I1'ow acciss to
Dhilor Regilters

../
/
../

/

/

lnt bant;

847 .

(

841 .
8U.
8H,
85\.

lnt
inn.;
• tt_bant (00);
in .... I • inpCbp. +3);

'*

In,,.l sh,.1 : OIao i
852 , outp «bpI+3).'n"11~i

I.t dlab in LeRt,

853, 'It_bank (bant) j
854, I
855 .
.,6. r ••• t_ellab (bant)
857. I.t tt ••••• t • • • • • • t . t tt •••• _.'11 ..................... I

an.

,tt
,tt

859. 1**

ttl

R••• t DLAI bit

or

tI,
tt,

LeR

160.
861. , •••••••••••••••••• ** ••••••••••••••••••••••••••••• ,

161.
1163. int bant.
864, (
865. tnt
inYII;
166 . • • t_bant (00):

8&7. in,i! • Inp(bp' +3);
168. in,.l • (in.al , Dl7f)j
'69. outp C(bpI+3) I in'ul) j
'70 . • et_blnle (blnt);
811, I

,*

dlab • 0 in Ltlt,

231928-53

82,510 XMODEM Implementation (Continued)

2-62

Ap·401

PAGE 17

MA IN PROGRAM

It p. ,

B2 51 0 XMODEM

t,
.....
.....,,

.72.. , ••• t t t • • • • • • • • • • • • • • • • • • • • • • I. . . . . . . . . . . . . . . . . . . . . . . . . . . t ••
813. , .. ..
t.t.*/
174. , .. ..
82510 interrupt slrv\ce routine
875./uU

876. , .. ..
817. , ... .
87 •.

, . . ..

879.
BIG.
881,
812.
813.
884.
a15.

, .. ..
,....
,....
/....
,....
,....
I.t lII.t t

12510 Interrupt sources:
ToM
CCR

......
.... ,
/

TX FIFO

• •••• I

Rl FIFO
TIMER B

t . t •• ,

.. ... ,
..... ,
... ... ,

Identifi . . and . . rvie . . thl 12510 inhrrupt

lourel requllting service.

..t .. ,
.. ... ,

• • • • fl • • • • t . t

.t •••••••••• t.t_ •• t • • • I ' ••••••••••••••• */

B86 •
817. isr_510 (I

BII.

(

BI!. Int

10urCI

Int
Int
Int
Int
Int
Int
B9& . Int
B97 . int

c1lld_b.

190.
BII.
BIZ.
B93.
Bl4.
B95.

st_b;
i;

ct lei
f 191;

gir,,1

j

nf 1'11;
lJ_chu;

'*

Stor .. T.ap. Vl.lul of CIA */

It

SUI

B98 .

'99, gJrnl
900.

~inp

(bpl+2);

BAnt reGlstlr ln temp.
location .,

901. Gulp «bp&+2),OJ20)

'OZ.

/. Get Victor Fro. CIR 123 .,
lourCI II: getsrc ()i
903. in hIe .Iourel;
904. switch (Iource)
I. Slulc. thl Sourc • • ,
905.
ea •• thur :
906.
907. I • ••••••• -_ ••••••••••••••••••••••••• t tt •• t •••••• ••••••••• ,
/
/
9DB.

....
,....

909. /....
910. ,....
911. ,....

......
....
.....
.....

TIMER SERVICE ROUTINE
decrtm,ntl tI counhr
dlcrealnts r I counter

*.

/
/
/

• •••• I
91Z .
I
913 . , ••••••••••••••••• t •• _ •••••••••••••••••••••••••••••••••

914.
915.
916.
917.
911.
919.
910,
9Zl.
922.
913.

It_b z: inp (bpl+3)j
(la_tim'_tnt )0)
lI_timl_cnt :l:1I_t i.,_cnt - 1 j
if (n_Hal_cnt )0)
rI_Ume_cnt =rI_tim,_cnt - 1 j
cmd_b
0122;
outp ( (bpa+3),emd_b );
outp (Cbpu1),Oz08)i
break;

,* DeeUlllnt Trln •• it Counter */

if

'*

Dleremlnt RICI1"'1 Counter

*'

=

/. [l5tart ti.er ./
mlDual lock

'*

*'

231928-54

82510 XMODEM Implementation (Continued)

2-63

inter

AP-401

HAIN PROCRAM

PACE 18

t14.
725.
'%6.

ease tllD
cu. tlf

917.
918.

,....

In.
130.
931.

932.
133.
934,

I

.t ... _.......

,....
/....

ft • • •

lip .•

82510 XHODEH

***.tw.t***t •••• t* ••••••••••••••••••••• /

..... ,
• .... /

TRANSHITTER SERVICE ROUTINE

• •••• J

,****

**.ul
•• t.*/

tran •• l ts Four c.haracters
and r.sets h_teq flag: when
whole paekl)lt tu,Ds.!tted

,....
Itt..

.. ... ,
.....

/
' ••• 11 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 1: • • • • • • • • • • • • • • /

/****

935.

91'.

If

(t

I_uq

/. II data 10 und

)0)

..

/

137.

938.

il (h_uq

139.
940.
141.

[

lor

(I

/. request to lind Picht . /

ptU
.0 i

1<4

j

iu)

<

In

ta char. hdala [1

143.
944.
945.

outp (bpa,h_chu)j

h_ind. +_4;
h_byh_c.nt +_4

946.
147.
148.
949
ISO.

+ h_indll

j

j

It if 132 chit. sent thin ./
/. reset TI request *1

951.

151.

953.

else

954.
955.
956.

(

/. if ell c:har.

trans.inion

requelhd . then trans.it the
char. in cc:r_to_h ./

957.
958.

959 .
960.
961.
961.
963.

964.
965.
966.
967.
961.

969 .
970.

else
(

*'

/. if no data to trans.it
1* then diu.ble ta inhuupts */
set_bank (00) j
oulp «bpa+1L (inpCbpa) &hUb);
set_b~nt (01) i

Gutp (Upu7).0I0,1);
break j

,. issue .. ~nual acknowledge *1

971.

231928-55

82510 XMODEM Implementation (Continued)

2-64

AP-401

PAGE 19

973 .
973.
974 .
975.
97, .
917.
978.

979.
910.
911.

913.
913.
91 •.
915.
91, .
917.
91B.

9., .
"0.

"I.

91Z .
993.
994.

IIAIN PROGRllI

CI •• eer
/t t t . t •• t . t ••••••• t

,....
,.t.t

....

,,....
,,....
....

1016.
lOZ? .

t._

*'
.".t,,

....

...............,,

t t . t •••••• t • • • • • • • • • • • • • • • • • •

if control char • NAI or ACK
inform
trlnl.Atter

..........

or
,,......................................
,,
intora recdyer
"' ................. ,
II SOH

EOT

...cerenl i
f191 .. Jnp (bpI +5);

Hal .1np (bPI+l) j
ctle _inp (bpl)j
if (U191 , OJFF) •• 0148)
I

'*

t •••• ,

rla'd RST fighter to Iuyici
K.K interrupt

*'

*'

Jt it no Irror. Ind cU. chlr
/* thin proc ••• control char. */

''lInd. "Ind to h

or u .• t,tt

switch (etle)
I
CUI NAI:
CI •• ACIt:
if (;It_ecf_rq
I

" ..

Ion.

•••••

12510 IMODEM

Control Charl,chr S""ie, Rout in.

"5.
99, .
"7.
"9.

lOOO.
lOOI.
1003.
lO03.
lO04.
lO05.
1006.
1007.
1001.
lO09.
1010.
lOll.
lOll .
lOl3 .
1014.
1015 .
1016 .
1017.
1011.
1019 .
1010.
lUI.
IOU.
1023 .
1024.

lip .•

*'

Icth,)

'* etl.
inleta tran •• lttu
char.

that
nelh,d */

vlt_cct_rq ainlcthl;
tU_tO_'lt attlt;

brelk;
CI.I SOH:

u •• EDT:
if Cttlc .. SOH.
/' II SOH dillbil CCR Int. '/
I
.It_blnk (00.;
Gutp C(bp&+l. I ClnpCbpl+l U ttidb.) i
IIt_blnt COl) i

if etl_ltIt! aa u_rd,)

,I if rlcliver wlltlnl for
SOH Ind uld, to f t .

thin infora rlc.i,,, of
I .llld ctl. chlr . • ,
ct l_ud_f 1, alct hi;
u_ctl_chf -etlei

brelk;

I

I
outp «bpl+7) ,01.08);

/. ilsul _'null lek . • /

231928-56

82510 XMODEM Implementation (Continued)

2-65

inter

AP-401

PACE %0

HAIN PROCRAH

Ion.

else nt

10%9 .
1030 .
1031.

,....

/....
/....
,....

IIp.e

8%51011l0DEH

.......... ,
..........,,

I •••••••••••••••••••••••••• •••••••••• t . t ••••••••••••••••• ,

Ion.

R. FIFO SERVICE ROUTINE

/

,....
/ • .,..

lOSS.

breat;
default

,* ••• *

..... ,

Rtads four by tel
Byte Count lndle,t •• padlt re.,d.

1033.
1034.
1035.
IOU.
1037 .
1038 .
1039 .
1040.
1041.
IOU.
1043 .
1044.
1045.
1046 .
1047 .
IOU.
1049 .
1050.
1051.
1052 .
1053.
1054.

tt

'*

..... ,

.. ... ,

*.... **t ••• t t. *.t •• *.t.t. *t. tt **t. t . t *. *t. *•• t ••• */

Rxr nat chected for IUOU, linel ell.chua is 11rl.d, U•• dllll,

'* ehar.t
r ...

r.' 1... 1 • (C lnp ( bpI
while ( n t h l I- G)

+4)

RI Tiaer

to indlcah
rte,hed before tl ••. out

*'

0.70) 10110) i
1* Chick RI FIFO 1e.,ll Ind r •• d
data it FIFO not •• pt, */
,

ndlh [rl_byte_cntl • inp (bpI);
++ rI_bytt_cnt i
++ ufcnt;

..- fI.U".

aut p (Upl.'), hOI};

1056,
1057.
1051.
1059,

'*

ill'U' a.RuII aetnowlld,1 */

1* if in,alid source thin illal a

alnual Ictnowlld,1 .,
Gutp CUp&+7),0I0Uj

1060.
brlaki
1061.
I
1062. oatp «bpa+1)r'oir1'al)i
1063 .
1064.
1065.
10". outp (1pOO,lo1)j
1067. I
1061.
1069 .
1070. Set_bant (bank_nua)
1071. int
hnt_nua;

"

RI.tort Orl,inll 1'1 lUI of lant
rioiller to rlturn thl 12510 to
orioinai lant '1

,. ll1ue Ind of int. to US'"

101:& .•••••••••••••••••••••••••••••••••••••••••••••••••••••••••• ,
1073. ,....
PROCEDURE SET_lANK
..... /
1074. ,....
Iwitchl' 1:&510 rioisler bank to
..... ,
1075. ,....
ohen ,aha..
• .... ,
1016. I •••••••••••••••••••••••• ~ •••••••••••••••

*•••••••••• *. *•••• ,

1077 .
1078.
1079.
1080.
1081.
lUI.
1083.
1014.
1085 .

Inl
Inl

port;
bant_r ..~_·"1 ;

bant_uo_val
_bant_llu • • 0120.
port = 9it_lddr +bpl;
outp (port, ballt_u9_1'II);
I

/. output 1'11a1 to bank rilishr

*'
231928-57

82510 XMODEM.lmplementatlon (Continued)

2-66

inter

AP-401

PAGE 21

It p..

HA IN PROGRAM

82510 XIIODEH

1086. getstc ()

1087. / .................................................. ,
1088. /wt
reid GIR Iond returns the
1089.
lourCI Vector
UI

**'

,*.

..

10'0. /
1091 . / "
Ion. / "
10'3. / "
10'4. / "
1095. / "

Timer
05
Ta tlac.hine - 04
CCR
03
HI FIFO
OZ
T. FIFO
01

-

,,/
,,/

HII
HII
HII
HII
HII

,,/
,,/
,,/
"/

,,/
IOU. / "
1091, , ••••••••••••••••••••••••••••••••••••• *••••••••••• ,
1098 .
10" .
1100. tnt
". Irc j

,'I
'* Hut

1101.

read CIR .,

1102 vdnp (bPI +2):
1103. src 11' v , 0I0E;
1104.
lID'. Ire. src/2i

out all bits ncept for

bits 1.2 Ind 3 I,

1106, uturnCsrc);

1107. )
1108.
1109. process_cad ()
1110.
1111.
1112.
1113.
1114.
1115
1116.
1111.
1118.
1119.
lUO.

.....
,
*.*.*,
*.*.*,
.....
.....
......
.....

, ..........1 • • • • • • • • • • • _ • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • ,
, ....
IU" PROCESS COMMAND
,....
Proceun User coamandl
/
/....
I - Tu.nslI.it
/
,....
Z - Rteei."
/
,....
- RUlt USiO
/
, .. ..
o - quit
, . . ..
r - Reinitillhe SlSIO
*/

*•••

11Z1.

,.**.
,

I12Z.

, • • • • • • • • • • • • • • • • • • • • • • • • • • • III

....

.".t/

- 5,stem monitor

.111'.*'

, ....

t •••

tf

*•• *III III *•• **III .. *....... III ....... III • • I

lin.
IIZI.
1125.
1126. tnt
rj
1117. int
IIflG .hl.1
lU8. int
ncp;
lIZ' .
1130.
r = g.tch ( ) j
1131.
switch (r) (
1132.

1133.
1134.
1135.

casl '0' :
.. fl9 = trulj
brlak

/.

el i

t.• ,

231928-58

82510 XMODEM Implementation (Continued)

2-67

inter
PAGE

AP-401

n

HA IN PROGRAH

113& .
1137.
1138.
113' .
1140.
1141.
1141.
1143 .
1144.

It p. c

82 5 I 0 XHODEH

'1'

CIS I

if

<\I_,tate

,. Tun •• it Coallind only
Iccepted if Idle ./

eLKS C) j
eLL (tI_r I h_c) i

MV_CURS ltl_' I h_c) i
printl ,"U1t :");
Icanf (III"", ltl_fill_ft ••• );
ell (tl_r. tl_C);

1145.
IIH.

open_wind (t

1147.
1148.
114' .
1150.
1151.

tl,.

IIH.

I

,t

Cit n •••

or

fill to T. '/

1_'. h_1! ," trans •• t tina") i

open_wind (h_1', tI_c+14,lI_f i "_n •• ,) i
tl_cad • lett'l;
,- Acthahl flag to Ilgnal

TransmU idle state .,

1153.
1154.
1155.
115& .
1157.
1158.
115' .
1160.
1161.

1I •• p OJ

pr.'9 ("tranl.I.llon in proar .. ,");
1
bUlk;
elll

'1' :
CLHS (I i
eLL (ra_r,u_c)j
"V_CURS (rI_,.

u_c) ;

printl ("fill :");

Icant (II",", 'lI_fill_na •• );
ell en_r lu_cd i

lin.
1163.
1164.
1165.
1166 .
1167 .
1168.
116' .
1170.
1171.
1171.
1173.
1174 .
1175.

"

Get u

fill n •••• ,

open_wind (fl_t I rl_c, "Inab ltd") i
open_wind (u_r, r~_c:+141 rI_f t 1I_n •• ,> i

u_cad 8,ett.,,:

I' Actit.h flag to Ilgnal
rI

ltate machine .,

bred:,
Clle

I ••

:

/. r .. et 82510 .,
ut 51 D () i
op.n_wind C24.30,"devie.e re.et");
breat j

c.le • r

I

:

rstSIO ();
lnit ();

/. reinithille IUto *1

enbint4 ();
hep ();
pra., (II USlO reinitialil.d");

II" .

1177 .
1178.
II" .

C.I,

1180.
1181.
1181 .
1183.
1184.
1185.
1186.
1187.
1188 .
118' .
1110.

elle

II! I.

I. end

helt;
'!'

:

ncp • • ,stea (I'd: \aico.")
default: .
BEEP ()

j

j

pratO ("incorrect

cO•• lnd,

reenter"',

buat;
I
if (tlflg .. true)

return ctrue)

/. if e.1t e.ommlnd j lIaed,
then qllit progr.m .,

i

retarn (Calse)

i

of co_and proc:tlling .,

231928-59

82510 XMODEM Implementation (Continued)

2-68

inter

AP-401

PAGE 13

HAIN PROGRAM

ftp.e

81510 lHOOE"

1192. as.bpU (,Jets_stnt,fp>
1193. / ............................................................ ,
ReAds f i l t to b. lran.1littld Ind puts
the data Into lhe proper •• od •• pactet foraat

1194,u
1195. It.
1196.

I

1197.
lUI. int
1199 .
1100. FILE
1201.

HI
U/

*•••••••••••••••••• ** ••• "••••••••••••••••••••••••••••• *•••• ,

'* ,et
this u1"1 11 used to
tile
t ,Jr:t •• ,
ft • •

Ifp;

{

1102. Int
int
1204. inl

sua aO i
i. blkent;
It, It;

1203.

1205. char

110'.
1107.
IZUI.
1209
UIO.

bIkent -(read Uhplct.bufhr[Ol,128.1, fp);
if (bIkent (1)
(
if «shfeofel,»
)0 && !;
set_bank (DOli;

13%0.

'1321.
1322.
1323.
1324.
13%5.

1326

1321.
outpC(bpa+6),OIDD);
1328.
tI_state :h_idl.;
1329.
prmsg ("transmitter resf!t"l;
1330.
1331.
1332.
1333. wai t_tl ()
1334. , ••••• trtr.tr.trtr.tr •••• trtr • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • ,
1335.
1336.
1331
1338.
1339.
1340

,....
,....
, ....
, . . fit
, ....

..... ,

c.hlcks

fJ

timer, and returns the

following "JUt
SOH - SOH rH.• iud
EOT - EOT rec:eiud

IfItflt

......
.... ,
/

......**.,,

·*··*1
..... * I
, .............. *••••••••••••••••• 111: • • • • • • • • • • *•••••••••

1341.

/ ... .

1342.
1343.

, .. ..
, •• fIt

1344.

..*.......*',,
. . ..

1JUT_RX:

time out - [ I timet Il.pired.
waiting - wliting for event

1345
1346 .
1348.
1341 .
1310
1351.
1352.
1313.
1314.
1315.
1356.
1311.

cll_fld_flg l::inactiu,
return ( tI_c.tl_c.hr)j
e lie

if ( rll_time_c.nt ...

0)

return (t hu_out)

j

.1 ••
uturn (wliting);
I

231928-62

82510 XMODEM Implementation (Continued)

2-71

AP-401

PAGE 26

MAIN PROGRAM

ftp.t

82510 XMODEM

1358. e.htpkt i
Inab 11 TIll AND TX F!FO
1437. set_bant (Ol)j
uturn to bant one ./
1438. InUnt4 C)i
Inab It interrupti
1439.
1440.
144!.
un. Ih_ptt_pUIID ()
1443. , ••••••••••• *••• ,. t,.t t.,.t t,. •• t t •• t,.. ,.,. •••••• t . t I • • '
1444.
Display. the para.ltu of thl Hlcdvld
1445. Itt pact.t nUBbn. and the tlpecttd plti.mltera It/
1446. / •••••••••••••••••••••••••••••••••• ,. ••••••••••••• ,
1447. C
1448. ++ bad_ptt_cnt i
1449. pr.'9 (I'undin; NAIIt: II);
1450. prlntf (" error :=I "5u",pht);
1451. aY_curs C13.1);
1452. print( (1Illptd 'ptt . . . . .3u".np_ptt_nvm)j
1453. 1n_e~rs (14,1);
1454, printf ("rId ptt ... "3u", ndata[O])j
1455, m"_curs (13.40)j
1456. printf (".Ipd ptt cllpl
"X", C-nd&tdO])j
. 1457. a"_cars (14.40);
1458. print( (lind plct coapltalnl ;0
rldatdlJ)j
1459. a"_curs «15,1) i
1440. prinU (Nrld cblcsulI;o Ii'X", ndah[t30])j
1461 . • v_curs CI5,40);
146Z. printf ("elpd chhua = "'X",pk_cbtsm)j
1463 . • • nd_ccr_rlq _act hlj
1464. ccr_to_h .. N1Kj
1465. 1

*•••••

"
"
"
"
"

,It

"

"

"

tI'

=

"X",

82510 XMODEM Implementation (Continued)

2-73

231928-64

AP·401

PAGE 11

IIA IN PROGR!I'I

1\ P . •

n

5\ 0 IIIODEII

1466. , •• t ••• t • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • /
1461, / ... PROCEDURe BUF_CPY
HI
t468. ,..

coph. picht to UII bufhr H/

146'. , •••••••••••• ** .......... *••••••••••••• ,

1470. buf_cPT Cpl.ckt_id)

1411. int pactt_ldi
147%.

(

1473. int
1474. Int
1.475.

I;
inda .0

j

1476 ind. = (packt_id-1) *128;
1477. if (inda < (320aO - 129»
No overwrite of' bufhr */
1478 (
1479.
for (ho; 1<121; h+'
1480.
rI_'_baf [ind.+i] • nbuf ttl;
148 I.
1412. else
1483.
pra.; ("ttle too big. cannot su" in ••• ary");

'*

1484.

231928-65

82510 XMODEM Implementation (Continued)

2-74

inter

AP-401

DEFINITiON F!LE

PAGE

ftp def

1. Idel Jne
2. Idellne
3. 'define
4. Idef 1ft.

51 "82510 FTP 1000 6130' 86"
bpa 0a3f8
9U_l.ddr
01
esc 1 17
5. Idef ine btl 07
6. Idd ine 1119_1: 17
7.
8. Ide( Ine 1Il11J_f I
9. Idef in. tI_c 35
10. Ide I lne tJl_f
10
II. 'define fl_C 35
U. 'define fl_f
12
13 . • deflne 5o_I: 50
14. Idel ine 10_f 14
IS. 'd.f in. h i l t
16 Idefin. true
17. Id.fine active I
18. Idefine inact i " 0
U. Idet lne ct l_ch'r 2
20. Idet ine ptt I
11. Idef ine eot 5555
U. Id.t ine echksm 5500
13. Idefine eptcmp 5501
24. Idef I ne eold
5501
15. Idefin. eptnum 5503
16
21. / ............... 11 • .,1 • • • • • • • • ,
28. , ... h stlte defintionstUI
29. / •••••••••••••••••••••••••• ,
30.
31. 'define h_idl.
000
32. Ullin. w&it_NAX
001
33. Ide( ine TO_eu_&D
DOt
34 . • define h_rd,
003.
35. 'de'ine tI_pad:et
004
36 .define w&it_CC
005
31. 'del ine tl_pt_comp au
38 . • def ine to_err
007

39 . • define tun
40. 'def 1ft. lItptt

haZ
111

82510 XHOOEH

/ ' S Igft on mISSIV, ' /
/' BUe I.ddress ' /

/' esea.p. char.

in h .. ' /

/' c.oordin&tlS of the
• • 51&91: lin. '/
/'

coordinates

,/

/' control char translli t '/
/' It:1\d PloCttt '/
/' pacht received ot '/
/' checksull error '/
/' packet compl incorrect ,/
/' old pact num [lceived ' /
/' inval id piloCtit I rcvd. ,/

1* Transmit packet stag . . . /

41 . • def ine hato
112
42. Idefin. retl
113
43. Idefine waiting
114
44.
45. , •••••••••••••••••••••••••• ,

U.
47.
48
49.
50.
51.
51.
53.
54.
55.

'*'

rw state definition II/
, •••••••••••••••••••••••••• ,

Idefine u_id1e
Idet ine rl_rd,
Idet in. u_ptt

000
001
002

/ •••••••••••••••••••••••••• /

56, .de( ine
57. Idel in.
58 . • def ine
59. Idet int:,

t 1ml_out
rw_NAK
rl_AeK
E'I_gln

90
91
92
93

I' u

state signal 'alues .,

60.

231928-66

82510 XMODEM Implementation (Continued)

2-75

AP-401

PAGE

%

DEFINITION FILE

Itp del

82510 I"ODE"

6\,

12, /t' •• , •• *.t't .t •• t • • • • t • • • • • • • • • ,
63,
Pro toco! Control
64,
chluchu'
/
•••••••••••••••••••••••••••••
**,
II,

....
.... ,,

,""
,,,

",

67,

68, Idellne NAK
Id.f he Atk

0114
0101

It Negat h' Act */
,. POliti" Act */

70,
71.
7%.
73,
74,
75,
76,
77,
78,
7?,
80,
11.

0.01

Start of Helder II
/* End of Tet.t .,

",

Id,t h.
Idlf in.
.deOnl
'dolinl

SOH
EDT
CAN
NUL

'*

0104
0118
DIDO

.... ,

J . . . . . . . . . . . . . . . . . . .:***u: ••••••• /

,..

inhrrupt lource

/ • • • • • • • • • • • • • • • • • • • • • • • • • • 1 •••• '

Idef In.
'd,f ill.
Id,t In.
n, .d,f ine
13, .dd Ine
84, 'dlf in.
15, 'def inl

thaer
t ...

ccr
nl
til
hiln
tiiO

16, 'd,f In. eel'n
17, Ide'ine ccidb
II, thtifte b nlnll

'*

D5
04
03

az

01
DIU
01%0
0104
0133

,. unallt TIM Ind TI FUO 111

'*,*
/*

0125'

89,
to,
91. , ••••••••••••••• 'u •••••• tt ••• 1/
/
9%,
82'59,\ ulan

.........

,,,

n,

,.............................

94,
!I, .d.finl

",

101

12510 Int. veetors */

0110

'dtfine IpOO

OIlD

97, Ide'ln. IpOI

hZ1

'*

*'

mask TIM and Ts FIFO
enable CCR inllrruptl */
mask CCR int *'
enable, block interrupts
throuGh tEA for 82510

*'

/

1* end of interrupt */
," 8U9A port D ",
1259" port 1

'*

*'

82510 XMODEM Implementation (Continued)

2-76

231928-67

inter

AP-401

PACE

CRT 110 ROUTINES

eio c

82510 X!100EM

1. linclude "ftp def"
2.

3

CLR()

5,

,....
/uu

/11:**11.** •••••••••••••••••••••• " ........................... /
6.

.....
..... ,,
.....
.....
..... ,,
• •••• /

PROCEDURE CLR

fit . . . ,

/ • • • 11

8.

9.
10
11.
12
1314.
1~

/ ••

**

/

clears

".u
11"**

/.11: fit:
, •• " •••••••••• ** ••••••••••• " ••••••••••• ** •••••••••••••••• ,

tnt escchr :: esci,

16
17
18

putch (escchr);

pr lntf

(" [2J");

!V.
20
21
22.
23 VOH ()
2<'1
, ............................. 111
2S
26.

27
28
Z9
30
31
32.
33
34.

/....
, •• fIt

.......

1 •• fIt:

Turns Reverse Video

.....
.....
..... ,,
.....
*•••• ,

orr
,
, ,*'.11...•••••••••••••
*
** ••••••••••••••••••••••••
/*11"

**

I
• •••• ,

••••••••••••••••••••• " ••••

PROCEDURE VOH

111: • •

/
*/

/

111: • • • • • • • • • • •

fl • • '

3S. lnt escchr :: esci;
37
38

putch (esc.c.htl,
pr intf ("[Om" 1;

3'
40
41

42.
43. RVON ()
44
45.
46
47.

* •• ".* •• " •• ""* •• *".*.* •••• " •• "",,,* •••• ,, ••••• ,, ••• 11 • • • • • • ,
*
."".",
.tt.t,
1*·*" PROCEDURE RVON
.11: ••• /

, ••
1" ••

..

,."
f···t
, "."

.....

tt.t.,
Reverse Vi deo ON
..t •• ,
4 •.
• • 1l;Il;1II' ,
50 /
•• *•• /
/."t*
51
52
,." •••••• t • • • • " " • • • • • • • • • • *." •••• *••• *•••• ** •••• *•• *••••• J
53
54.
55. int escchr = esc:i;
56.
51.
putc:.h (esc:.chr);
58
print! ("[7111.");
59
48

60

231928-68

82510 XMODEM Implementation (Continued)

2-77

inter
PACE

AP-401

CRT 1/0 ROUTINES

1

 0 ) ;
IF (INPUT(MSR) . AND DSR MSR) <> 0
THEN MODEM_HANDSHAKE
TRUE
-

END

END WAIT_FOR_MODEM_STATUS

/ ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• *••• *.*.*.**
• Procedure

INTERRUPT HANDLER

*

• input:
• output:
• function:

Tx Buffer
Rx Buffer, Finish_TX, Finish_Rx
service all 82510 interrupt sources:
Rx Fifo, Tx Fifo, status, Timer, Modem
82510 hardware interrupt
Rx Fifo Intr, Tx Fifo Intr, Status Intr,
Timer_Intr, Modem_Intr
-

•
•
•
•
•
•
.•

•••••••••••••••••••••••••••••••••••••••••••••••••••• *•••••••••• *.** ••••• *

•

• cal'led by:
• calling:
•

••

•

flowchart: figure 10 . description: paragraph 6.4, 6.4.1
•
*********************************************.***************************1

INTR_HANDLER: PROCEDURE INTERRUPT INTR_510 REENTRANT PUBLIC ;"

ENABLE

/. Enable Interrupts of
/. HIGHIER priority devices

*/

INTR_VEC=INPUT(GIR);

/. Get the 82510-highest priority
/. pending interrupt

*/
*/

*/

292038-21

2-102

in1:ef

AP-310

/*************************************************************************
Rx FIFO INTR
*

*

*************************************************************************

*
*

*
*

*
*

input:
output:
function:

called by:
calling:

none
Rx Buffer, Burst Algo
service Rx Fifo Interrupt
receive characters; store 'in receive buffer
INTERRUPT HANDLER
BURST_ALGO

**

*
*
*

*
*

*
**

flowchart:
figure 11
description: paragraph 6.4.2
*************************************************************************/
IF INTR_VEC=RXI_GIR THEN DO ;
RX_OCC=INPUT(FLR)

;

RX_OCC=SHR(RX_OCC,4)

/* Rx fifo level occupancy
/* Shift the Rx occupancy bit

/*
/*
/*
/*

to get it's real value

- OPTIMIZE code -

Empty the Rx FIFO and store the
received character in RX_BUF
RX BUF(IX RX:=IX RX+l)=INPUT(RXD)
/* Read the first character immediatly
/* to save Real Time
DO WHILE (RX OCC:=RX OCC-l) > 0 ;
RX BUF(IX-RX:=IX RX+l)=INPUT(RXD)
END ;,

*/
*/

'*/
*/
*/

*/
*/
*/

/*************************************************************************
*
BURST ALGORITHM
*

************,*************************************************************

*
*

*
*

*
*
**

input:
output:
function:

called by:
calling:

Burst Algo
Burst-Algo
execute a step in the burst algorithm
after characters are received
Rx_FIFO_INTR
rione

*

*
*
*
*
*

**

flowchart: figure 5
description: par. 6.2.2.1 to 6.2.2.3
*************************************************************************/

/*-----------------------------------------------------------------*
* BUR S T
MOD E - step 3
(full fifo threshold)
*
*

*

*
*

Reset the Timer status
Restart the Timer

*-----------------------------------------------------------------*/

IF BURST ALGO = BURST MODE THEN DO ;
TEMP ~ INPUT(TMST);
OUTPUT (TMCR) =STARTIMB_TMCR;
END;

/*-----------------------------------------------------------------*
* HUN TIN G MOD E - step 1
*
*

*

Oper0) THEN
BURST_ALGO= HUNTING_MODE :
ELSE 00:
OUTPUT (BANK) = GEN2:/* switch to BANK TWO - General Config
OUTPUT(FMO)=TXTHRESHO_FMD OR RXTHRESH3_FMO:
OUTPUT (BANK) =NASO: /* switch to BANK ZERO - NAS
OUTPUT (GER) -= ENTIMRX GER:
/* Enab~e TIMER,RX and MODEM interrupts
OUTPUT(BANK)-WORK1: /* switch to BANK ONE - WORK
BURST ALGO = BURST MODE:
TEMP; INPUT(TMsT); /* Reset timer status
OUTPUT (TMCR) = STARTIMB TMCR:
END:
'
END:
/* End of SINGLE mode

*/
*/
*/
*/
*/
*/

/* •••• End of BURST algorithm •••••• ~ ••••••••••••••••••.•••••••••••.... */
/*
/*

Another try to empty the Rx fifo
before leaving the' interrupt handler
•
/* Empty the Rx FIFO and store the
/* received character in RX_BUF
RX BUF(IX RX:=IX RX+1)=INPUT(RXD) :
END :DO

END :

*/
*/

WHILE (INPUT (FLR) <>0)

/* End of Rx fifo interrupt

*/
*/

*/

/*************************************************************************
*
TxFIFO INTR
*
*************************************************************************
* input:
Tx Buffer
*
Finish_tx
*
* output:
* function:
service Tx Fifo interrupt
*
transmit characters from transmit buffer (OPTIMIZE code) *
*
* called by: INTERRUPT HANDLER
*
none
*
* calling:

*

•

* flowchart: figure 12
description: paragraph 6.4.3
*
*************************************************************************/
ELSE IF INTR VEC.,TXI GIR THEN DO :
TX OCC=INPUT(FLR)-AND MASK TXOCC :
- /* Tx fifo level occupancy
*/
/* Fill Tx FIFO, the transmitted characters are taken from TX_buf
*/'
DO WHILE (TX OCC:=TX OCC+1)O AND (NOT FIN RX»:
RX OCC=RX-OCC-1 :
1* First, empty Rx FIFO
RX::::CHR=iNPuT(RXD)

*1

IF RECEIVER THEN
ELSE DO:
IF RX CHR = X OFF THEN DO ;
OUTPUT(BANK)=NASO:I* Switch to BANK ZERO - NAS
OUTPUT (GER) = INPUT (GER) AND DISTX_GER :
1* Disable Transmit interrupt
OUTPUT(BANK)=WORK1:1* switch to BANK ONE - WORK
END :
ELSE IF RX CHR = X ON THEN DO :
OUTPUT(BANK)= NAsO ;
OUTPUT (GER) = INPUT (GER) OR ENTX GER ;
1* Enable Transmit interrupt again
OUTPUT(BANK)= WORKl ;
END
END
END ;
IF RECEIVER THEN DO ;
IF «STAT AND ACRSTAT_RST) <> 0) THEN DO ;
OUTPUT(BANK)= NASO;
1* If End_Of_Line was recognized,
OUTPUT (GER) = DISRTX GER ;
OUTPUT(BANK)= WORK1; 1* Disable 82510-interrupts and the
FIN RX
= TRUE;
1* Reception
END ; ELSE IF «STAT AND ERRCHR RST) <> 0) THEN DO ;
CALL WRITE(@('** ERROR-in character Status ',0»
~LL ERROR_CHAR_HANDLER ;
IF BURST ALGO=BURST MODE THEN DO ;
1* In BURST mode do:
TEMP = INPUT(TMST); 1* Reset timer status,
OUTPUT (TMCR) = STARTIMB TMCR;
END;
1* Restart TIMER
END

*1
*1
*1

*1

*1
*1
*1

*1
*1
*1

END
END ;

1* End of STATUS interrupt

*1
292038-24

2-105

intJ

AP-310

1***************************************************** ********************
*
TIMER INTR
*
*************************************************************************
* input:
none
*
* output:
Burst Algo
*
* function: service Timer interrupt; receive characters
*
and switch Burst_Algo to HUNTING mode
*
*
*
* called by: INTERRUPT HANDLER
* calling:
BURST &TIMER
*

**

flowchart:

figure 14

description:

paragraph 6.4.5

**

*****************************************~************ *******************1

ELSE IF INTR_VEC=TIMI_GIR THEN DO ;
IF ((RX_OCC:=INPUT(FLR»<>O) THEN DO
RX_OCC=SHR(RX_OCC,4) ; 1* Rx fifo level occupancy, shift right */
1* - OPTIMIZE code */
1* Empty the Rx FIFO and store the
*/
/* received character in RX_BUF
*/
RX BUF(IX RX:=IX RX+l)=INPUT(RXD) ;
DO-WHILE (RX OCC:=RX OCC-l) > 0 ;
RX BUF(IX-RX:=IX RX+l)=INPUT(RXD)
END 1* Store the received character in RX_buf*/
END ;

1*************************************************************************
*

*

BURST & TIMER

*************************************************************************

*
*
*

* called by:
* calling:

Burst_AI go
Burst Algo
execute a step in the burst algorithm
after timer interrupt; switoh to HUNTING
TIMER_INTR
none

*
*
*
*
*
*

*

figure

*

*

input:
output:
function:

* flowchart:

6

description:

paragraph 6.2.2.4

*

*************************************************************************/
OUTPUT (BANK) ~ GEN2;
/* switoh to BANK TWO - General Config
*/
OUTPUT (FMD) = TXTHRESHO_FMD OR RXTHRESHO FMD;
1* Rxfifo threshold=O, Txfifo threshold=O*/
OUTPUT (BANK) = NASO;
OUTPUT (GER) ~ ENRX'GER;
OUTPUT (BANK) = WORKl;
TEMP = INPUT(TMST);
BURST_ALGO
HUNTING_MODE
END ;

/* Switch to BANK ZERO - NAS
/* Disable Timer interrupt and
/* Enable RX,STAT,MODEM interrupts
/* Acknowledge TIMER interrupt
1* Back to HUNTING mode
1* End of TIMER interrupt

*/
*/
*/
*/
*/
*/
292038-25

2-106

AP-310

1*************************************************************************

*
MODEM INTR
*
*************************************************************************
* input:
none
*
* output:
none
*
*
* function: service Modem interrupt and handle modem errors.
Modem interrupt is occurred if No Modem was setup, or
*
*
if DSR was dropped in the middle of the communication
*
*
*
* called by: INTERRUPT HANDLER
none
*
* calling:

** flo~chart: figure 15
description: paragraph 6.4.6
**
*************************************************************************/

STAT=INPUT(MSR)

1* Get MODEM status

*1

CALL ERROR_MODEM_HANDLER

1* Handel Modem Errors handshake

*1

END

1* End of MODEM interrupt

*1

OUTPUT (PORT_EOI) =COMM_EOI

1* Write End Of Interrupt command to the *1
1* PIC (8259A) *1

END INTR_HANDLER

1***************************************************** ********************
* Procedure ERROR MODEM HANDLER
*
*************************************************************************/
ERROR_MODEM_HANDLER: PROCEDURE PUBLIC ;
MODEM_HANDSHAKE = FALSE ;

1* Flag indicates that an Error occurred *1
1* in Modem
*1

1*************************************************************************

* Procedure ERROR CHAR HANDLER
*
*************************************************************************/

= TRUE
OUTPUT (BANK)
OUTPUT (GER)
OUTPUT (BANK)

NASO ;
DISRTX GER
WORKl ;-

1* Flag indicates that an Error occurred *1
1* during Reception
*1
1* switch to BANK ZERO - NAS
1* Disable all the 82510 Interrupts
1* Switch to BANK ONE - WORK

*1
*1
*1

END ERROR CHAR_HANDLER
292036-26

2-107

inter

AP·310

1***************************************************** ********************
*

Procedure

LOOP

*

**

LOOP procedure is executed until TransmissionlReception Finishes
* or until the loop ends.

**
*

*************************************~**************** *******************1

LOOP: PROCEDURE PUBLIC
DECLARE N WORD :
DECLARE NUM WORD :.
DECLARE MAXLOOP BYTE
MAXLOOP= 20 :
NUM=O :
DO WHILE ( (NOT FIN TX) AND (NOT FIN RX) AND (NUM' ,
CR-;-LF,
, ABCDEFGHIJKLMNOPQRSTUVWXYZO123456789abcdefghijklmnopqrstuvwxyzo123456789',
CR,LF,
'ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789abcdefghijklmnopqrstuvwxyz0123456789',
CR,LF,
'ABCDEFGHIJKLMNOP~RSTUVWXYZ0123456789abcdefghijklmnopqrstuvwxyz0123456789',

CR,LF,
, ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789abcdefghij klmnopqrstuvwxyzO 123456789',
CR,LF,
'ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789abcdefghijklmnopqrstuvwxyz0123456789',
CR,LF,End_Of_File,0)
1* End_Of_Fiie-terminate the Transmission*1
END TEXT ;
292038-27

2-108

,i~

AP-310

1***************************************************** ********************
* External
procedures
*

*************************************************************************
* WRITELN:
* MENU:

I/O console utility - dispaly a string, end with CR
I/O console utility - display a menu, enter the user
*
selection
* DISPTEXT: I/O console utility
display the contents of the
*
Receive buffer (Rx bUf)
* INIT HARDWARE SETUP: Setup and Hardware configuratIons of the
*
specific station

*
*
*

*

*
*
*

*******************************~********************** *******************/

1***************************************************** ********************
* Procedure MAIN
*
*************************************************************************
* input:
Finish Rx, Finish Tx
*
* output:
Receiver flag
*
* function:
get station type (Rx or Tx) from the operator;
*
*
wait till communication is completed; display;
*
*
RECEIVER STATION SHOULD BE ACTIVATED FIRST
*
~ called by:
Application
*
* calling:
INITIALIZATIONS, LOOP
*

** flowchart: figure 3
description: paragraph 6.1
**
*************************************************************************/
MAIN:

'/* External, Setup and H/W configurations*/
FIN=FALSE ;
DO WHILE NOT (FIN)
SELECTION=O ;
CALL WRITELN(@('------------------------------------------------ ',0»;
SELECTION=MENU(SELECTION,@('station: (Quit/Transmitter/Receiver) ',0» ;
/* Get operator selection.
*/
/* Receiver station should be activated */
/* prior to the transmitter' station
*/
DO CASE SELECTION ;
FIN=TRUE
/*
Quit of HIGH PERFORMANCE Driver
*/
DO ;
/* 1 - Transmit station
*/
RECElVER=FALSE ;
CALL INITIALIZATIONS
CALL LOOP ;
END ;
DO ;
/* 2 - Receive station
*/
RECEIVER=TRUE
CALL INITIALIZATIONS
CALL LOOP ;
END
END
END

°-

CALL EXIT
END HIGHPERFORMANCE ;

/*************************************************************************/
292038-28

2·109

AP-310

APPENDIX B
82510 BASED SBX SERIAL CHANNEL
This document describes the implementation of an
82510 based SBX board that provides a RS-232 interface to any iSBC board which has an SBX connector.
The SBX can be useful for customers that need a fast
software development vehicle while the 82510 system
hardware is still in the design stage. The customer can
also use the SBX for evaluation of the 82510 in 11 system environment.

BOARD DESCRIPTION (See F'igure B-1)

In order to minimize the customer's software development costs, the RMX86/286 Terminal Device Drivel'
for the 82510 has also been developed and can be run
by the RMX user on his iSBC with the SBX-8251O
board described herewith. The RMX86/286 drivers are
available from INSITE, along with the source code and
the documentation.

The following 82510 signals are connected directly to
the SBX connector (installed on the pin side): DATA,
ADDRESS, INTERRUPT, RESET, READ#,
WRITE# and CS #. Wait states are generated by a
shift register logic (U5, U7), clocked by the MCLK
signal of the SBX interface. The number of wait states
is selected by installing one of the eight jumpers to select one parallel output of the shift register. The 82510
is clocked by an 18.432 MHz Crystal (using its on-chip
oscillator). A discrete transistor is used to pull down
the RTS# signal during RESET to set the crystal mode
(note that in a larger board, an unused open collector
inverter or three-state gate can be used for this purpose). The 82510 is connected to the communication
channel through RS-232 line drivers and receivers. Either a 25 pin D-Type connector (P) or a 26 pin Flat-Cable connector (F) is used to connect the board to the
RS-232 channel.

2-110

i

2N2222

, ...

5 INT

...E.

/1

P/4 r/20. RTS

AO

~Al
~A2

.2:!

~~

________________________________________~Dl

:27jD2
__________________________________________2_8jD3

.=~~

.,L~
~~

~~

!p

CTS#P4

11

,""""3

0<

4 07
RD#

4

P/20 F/13, DTR

P/5 F/18 , eTS
P/6 F/16'DSR

r-~2:10

13

19 WR#

~~~-------------t--------------------t1~1'18Le_S~#X~I~~~~

:-"

~

____________________________________

.:i~

ID

8

~2

~3

. i:io

...

IUr

P/2 F/24 , nOATA

11

:!!

CD
C

~

I

Ul
nD
82510

1 04
________________________________________ D5
____________________________________
D6

~~

~

DTR# 1'5

DO

P/22 r/9"RI
P/8 F/12 , DeD

~ 10

III
0

...a.
DI

U4

en

()

~

P/3 r/22 ~ RXDATA
P/7, 1 F/14

F

"P

...

GND

c,,)

C)

GilD

:::r
ID

3

292038-29

DI

g-

J/3,17,35
GND4
10)"r:::t:::1!:::1!:::1!::::l!.
J
Vcc 4 / 4 ,18,36
J/2
·=O.l~F
-12

TTTTT

III

+;';:"'I

+ 12

4..i
~~

#

WAIT State Generator
States

Jumper
to CLOSE

# of WAIT

States

Jumper
to CLOSE

1
2
3
4

S1
S2
S3
S4

5
6,
7
8

S5
S6
S7
S8

# of WAIT

Only One Jumper Should Be Closed at a Time

Type

Vee

GND -12 +12

U1 82510

21

7

U2 1488

5,9

7

U3 1489

14

7

U4 1489

14

U5 74LS164 1,2,14

#

Type

Vee

GND

14

7

-12

U6 Jumper
1

14

U7 74LSOO
J

SBX Male Connector for 8 Bit Bus

7

P

25 Pin D-Type Connector (Male)

7

F

26 Pin Flat-cable Connector (Male)

-

Either P or F should be installed,

+12

APPLICATION
NOTE

November 1986

Using the 8273 SOLC/HOLC
Protocol Controller

JOHN BEASTON
MICROCOMPUTER APPLICATIONS

Order Number: 611001-001
2-112

intJ

Ap·36

INTRODUCTION

SDLC/HDLC OVERVIEW

The Intel 8273 is a Data Communications Protocol
Controller designed for use in systems utilizing either
SDLC or HDLC (Synchronous or High-Level Data
Link Control) protocols. In addition to the usual features such as full duplex operation, automatic Frame
Check Sequence generation and checking, automatic
zero bit insertion and deletion, and TTL compatibility
found on other single component SDLC controllers, the
8273 features a frame level command structure, a digital phase locked loop, SDLC loop operation, and diagnostics.
.

SDLC is a protocol for managing the flow of information on a data communications link. In other words,
SDLC can be thought of as an envelope-addressed,
stamped, and containing an s.a.s.e.-in which information is transferred from location to location on a data
communications link. (Please note that while SDLC is
discussed specifically, all comments also apply to
HDLC except where noted.) The link may be either
point-to-point or multi-point, with the point-to-point
configuration being either switched or nonswitched.
The information flow may use either full or half duplex
exchanges. With this many configurations supported, it
is difficult to find a synchronous data communications
application where SDLC would not be appropriate.

The frame level command structure is made possible by
the 8273's unique internal dual processor architecture.
A high-speed bit processor handles the serial data manipulations and character recognition. A byte processor
implements the frame level commands. These dual
processors allow the 8273 to control the necessary byteby-byte operation of the data channel with a minimum
of CPU (Central Processing Unit) intervention. For the
user this means the CPU has time to take on additional
tasks. The digital phase locked loop (DPLL) provides a
means of clock recovery from the received data stream
on-chip. This feature, along with the frame level commands, makes SDLC loop operation extremely simple
and flexible. Diagnostics in the form of both data and
clock loopback are available to simplify board debug
and link testing. The 8273 is a dedicated function peripheral in the MCS-80/85 Microcomputer family and
as such, it interfaces to the 8080/8085 system with a
minimum of external hardware.
This application note explains the 8273 as a component
and shows its use in a generalized loop configuration
and a typical 8085 system. The 8085 system was used to
verify the SDLC operation of the 8273 on an actual
IBM SDLC data communications link.
The first section of this application note presents an
overview of the SDLC/HDLC protocols. It is fairly
tutorial in nature and may be skipped by the more
knowledgeable reader. The second section describes the
8273 from a functional standpoint with explanation of
the block diagram. The software aspects of the 8273,
including command examples, are discussed in the
third section. The fourth and fifth sections discuss a
loop SDLC configuration and the 8085 system respectively.

Aside from supporting a large number of configurations, SDLC offers the potential of a 2 X increase in
throughput over the presently most prevalent protocol:
Bi-Sync. This performance increase is primarily due to
two characteristics of SDLC: full duplex operation and
the implied acknowledgement of transferred information. The performance increase due to full duplex operation is fairly obvious since, in SDLC, both stations can
communicate simultaneously. Bi-Sync supports only
half-duplex (two-way alternate) communication. The
increase from implied acknowledgement arises from the
fact that a station using SDLC may acknowledge previously received information while transmitting different
information. Up to 7 messages may be outstanding before an acknowledgement is required. These messages
may be acknowledged as a block rather than singly. In
Bi-Sync, acknowledgements are unique messages that
may not be included with messages containing information and each information message requires a separate
acknowledgement. Thus the line efficiency of SDLC is
superior to Bi-Sync. On a higher level, the potential of a
2 X increase in performance means lower cost per unit
of information transferred. Notice that the increase is
not due to higher data link speeds (SDLC is actually
speed independent), but simply through better line utilization.
Getting down to the more salient characteristics of
SDLC; the basic unit of information on an SDLC link
is that of the frame. The frame format is shown in Figure 1. Five fields comprise each frame: flag, address,
control, information, and frame check sequence. The
flag fields (F) form the boundary of the frame and all

Opening
Flag

Address
Field (A)

Control
Field (C)

Information
Field (I)

01111110

8 Bits

8 Bits

Any Length
o to N Bits

Figure 1. SOLC Frame Format

2-113

Frame
Check
Sequence
(FCS)

Closing
Flag

16 Bits

01111110

inter

AP-36

other fields are positionally related to one of the two
flags. All frames start with an opening flag and end
with a closing flag. Flags are used for frame synchronization. They also may serve as time-fill characters between frames. (There are no intraframe time-fill characters in SDLC as there are in Bi-Sync.) The opening flag
serves as a reference point for the .address (A) and control (C) fields. The frame check sequence (FCS) is referenced from the closing flag. All flags have the binary
configuration 01111110 (7EH).

The 8 bits following the address field form the control
field. The control field embodies the link-level control
of SDLC. A detailed explanation of the commands and
responses contained in this field is beyond the scope of
. this application note. Suffice it to say that it is in the
control field that the implied acknowledgement is carried out through the use of frame sequence numbers.
None of the currently available SDLC single chip controllers utilize the control field. They simply pass it to
the processor for analysis. Readers wishing a more detailed explanation of the control field, or of SDLC in
general, should consult the IBM documents referenced
on the front page overleaf.

SDLC is a bit-oriented protocol, that is, the receiving
station must be able to recognize a flag (or any other
special character) at any time, not just on an 8-bit
boundary. This, of course, implies that, a frame may be
N-bits in length. (The vast majority of applications tend
to use frames which are multiples 'of 8 bits long, however.).
,The fact that the flag has a unique binary pattern would
seem to limit the contents of the frame since a flag
pattern might inadvertently occur within the frame.
This would cause the receiver to think the closing flag
was received, invalidating the frame. SDLC handles
this situation through a technique called zero bit insertion. This techniques specifies that within a frame a
binary 0 be inserted by the transmitter after any succession of five contiguous binary Is. Thus, no pattern of
01111110 is ever transmitted by chance. On the receiving end, after the opening flag is' detected, the receiver
removes any 0 following 5 consecutive Is. The inserted
and deleted Os are not counted for error determination.
Before discussing the address field, an explanation of
the roles of an SDLC station is in order. SDLC specifies two types of stations: primary and secondary. The
primary is the control station for the data link and thus
has responsibility of the overall network. There is only
one predetermined primary station, all other stations
on the link assume the secondary station role. In general, a secondary station speaks only when spoken to. In
other words, the primary polls the secondaries for responses. In order to specify a specific secondary, each
secondary is assigned a unique 8-bit address. It is. this
address that is used in the frame's address field.
When the primary transmits a frame to a specific secondary, the address field contains the secondary's address. When responding, the secondary uses its own
address in the address field. The primary is never identified. This ensures that the primary knows Which of
many secondaries is responding since the primary may
have many messages outstanding at various secondary
stations. In addition to the specific secondary address,
an address common to all secondaries may be used for
various purposes. (An all Is address field is usually
used for this "All Parties" address.) Even though the
primary may use this common address, the secondaries
are expected to respond with their unique address. The
address field is always the first 8 bits following the
opening flag.

In some types of frames, an information field follows
the control field. Frames used strictly for link management mayor may not contain one. When an information field is used, it is unrestricted in both content and
length. This code transparency is made possible because
of the zero bit insertion mentioned earlier and the bitoriented nature of SDLC. Even main memory core
dumps may be transmitted because of this capability.
This feature is unique to bit-oriented protocols. Like
the control field, the information field is not interpreted
by the SDLC device; it is merely transferred to and .
from memory to be operated on and interpreted by the
processor.
The final field is the frame check sequence (FCS). The
FCS is the 16 .bits immediately preceding the closing
flag. This 16-bit field is used for error detection through
a Cyclic Redundancy Checkword (CRC). The 16-bit
transmitted CRC is the complement of the remainder
obtained when the A, C, and I fields are "divided" by a
generating polynomial. The receiver accumulates the
A, C, and I fields and also the FCS into its internal
CRC register. At the closing flag, this register contains
one particular number for an error-free reception. If
this number is not obtained, the frame was received in
error and should be discarded. Discarding the frame
causes the station to not update its frame sequence
numbering. This results in a retransmission after the
station sends 'an acknowledgement from previous
frames. [Unlike all other fields, the FCS is transmitted
MSB (Most Significant Bit) first. The A, C, and I fields
are transmitted LSB (Least Significant Bit) first.] The
details of how the FCS is generated and checked is
beyond the scope of this application note and since all
single component SDLC controllers handle this function automatically, it is usually sufficient to know only
that an error has or has not occurred. The IBM documents contain more' detailed information for those
readers desiring it.
The closing flag terminates the frame. When the closing
flag is received, the receiver knows that the preceding
16 bits constitute the FCS and that any bits between the
control field and the FCS constitute the information
field.

2-114

intJ

Ap·36

SOLC does not support an interframe time-fill character such as the SYN character in Bi-Sync. If an unusual
condition occurs while transmitting, such as data is not
available in time from memory or CTS (Clear-to-Send)
is lost from the modem, the transmitter aborts the
frame by sending an Abort character to notify the receiver to invalidate the frame. The Abort character
consists of eight contiguous Is sent without zero bit
insertion. Intraframe time-fill consists of either flags,
Abort characters, or any combination of the two.
While the Abort character protects the receiver from
transmitted errors, errors introduced by the transmission medium are discovered at the receiver through the
FCS check and a check for invalid frames. Invalid
frames are those which are not bounded by flags or are
too short, that is, less than 32 bits between flags. All
invalid frames are ignored by the receiver.
Although SOLC is a synchronous protocol, it provides
an optional feature that allows its use on basically asynchronous data links-NRZI (Non-Return-to-Zero-Inverted) coding. NRZI coding specifies that the signal
condition does not change for transmitting a binary I,
while a binary 0 causes a change of state. Figure 2 illustrates NRZI coding compared to the normal NRZ.
NRZI coding guarantees that an active line will have a
transition at least every 5-bit times; long strings of zeroes cause a transition every bit time, while long strings
of Is are broken up by zero bit insertion. Since asynchronous operation requires that the receiver sampling
clock be derived from the received data, NRZI encoding plus zero bit insertion make the design of clock
recovery circuitry easier.

DATA
BtT SAMPLE

1

o

IIIIIIIIII

NRZ

NRZI

611001-1

Figure 2. NRZI vs NRZ Encoding

All of the previous discussion has applied to SOLC on
either point-to-point or multi-point data networks.
SOLC (but not HOLC) also includes specification for a
loop configuration. Figure 3 compares these three configurations. IBM uses this loop configuration in its
3650 Retail Store System. It consists of a single loop
controller station with one or more down-loop secondary stations. Communications on a loop rely on the
secondary stations repeating a received message down
loop with a delay of one bit time. The reason for the
one bit delay will be evident shortly.
Loop operation defines a new special character: the
EOP (End-of-Poll) character which consists of a 0 followed by 7 contiguous, non-zero bit inserted, ones. After the loop controller transmits a message, it idles the
line (sends all Is). The final zero of the closing flag plus
_the first 7 Is of the idle form an EOP character. While

POINT·TO·POINT

LOOP

611001-3
MULTI·POINT

611001-2

Figure 3. Network Configurations

2-115

AP-36

repeating, the secondaries monitor their incoming line'
for an EOP character. When an EOP is detected, the
secondary checks to see if it has a message to transmit.
If it does, it changes the seventh I to a 0 (the one bit
delay allows time for this) and repeats the modified
EOP (now alias flag). After this flag is transmitted, the
secondary terminates its repeater function and inserts
its message (with multiple preceding flags if necessary).
After the closing flag, the secondary resumes its one bit
delay repeater function. Notice that the final zero of the
secondary's closing flag plus the repeated Is from the
controller form an EOP for the next down-loop secondary, allowing it to insert a message if it desires.

lowed by 7 Is) and the HOLC Abort (7 Is). This possible incompatibility is neatly handled by the HOLC protocol not specifying a loop configuration.
This completes our brief discussion of the SOLCI .
HOLC protocols. Now let us tum to the 8273 in particular and discuss its hardware aspects through an explanation of the block diagram and generalized system
schematics.

One might wonder if the secondary missed any messages from the controller while it was inserting its own
message. It does not. Loop operation is basically halfduplex. The controller waits until it receives an EOP
before it transmits its next message. The controller's
reception of the EOP signifies that the original message
has propagated around the loop followed by any messages inserted by the secondaries. Notice that secondaries cannot communicate with one another directly, all
secondary-to-secondary communication takes place by
way of the controller.
Loop protocol does not utilize the normal Abort character. Instead, an abort is accomplished by simply
transmitting a flag character. Oown loop, the receiver
sees the abort as a frame which is either too short (if the
abort occurred early in the frame) or one with an FCS
error. Either results in a discarded frame. For more
details on loop operation, please refer to the IBM documents referenced earlier.
Another protocol very similar to SOLC which the 8273
supports is HOLC (High-Level Oata Link Control).
There are only three basic differences between the two:
HOLC offers extended address and control fields, and
the HOLC Abort character is 7 contiguous Is as opposed to SOLC's 8 contiguous Is.
Extended addressing, beyond the 256 unique addresses
possible with SOLC, is provided by using the address
field's least significant bit as the extended address modifier. The receiver examines this bit to determine if the
octet should be interpreted as the final address octet.
As long as the bit is 0, the octet that contains it is
considered an extended address. The first time the bit is
a I, the receiver interprets that octet as the final address
octet. Thus the address field may be extended to any
number of octets. Extended addressing is illustrated in
Figure 4a.
A similar technique is used to extend the control field
although the extension is limited to only one extra control octet. Figure 4b illustrates control field extension.
Those readers not yet asleep may have noticed the similarity between the SOLC loop EOP character (a 0 fol-

FIRST BIT TRANSMITTED elsa FIRST)

611001-4
A. HDLC ADDRESS FIELD EXTENSION

C
FLAG

A

EXTENSION BIT (1 MAXI

It c,l c.i., I .• I FCO, IFCo.1

FLAG

, 611001-5
B. HDLC CONTROL FIELD EXTENSION

Figure 4

BASIC 8273 OPERATION
It will be helpful for the following discussions to have

some idea of the basic operation of the 8273. Each operation, whether it is a frame transmission, reception or
port read, etc., is comprised of three phases: the Command, Execution, and Result phases. Figure 5 shows
the sequence of these phases. As an illustration of this
sequence, let us look at the transmit operation.

611001-6

Figure 5. 8273 Operational Phases

When the CPU decides it is time to transmit a frame,
the Command phase is entered by the CPU issuing a
Transmit Frame command to the 8273. It is not sufficient to just instruct the 8273 to transmit. The frame
level command structure sometimes requires more information such as frame length and address and control
field content. Once this additional information is sup-

2-116

inter

AP-36

plied, the Command phase is complete and the Execution phase is entered. It is during the Execution phase
that the actual operation, in this case a frame transmission, takes place. The 8273 transmits the opening flag,
A and C fields, the specified number of I field bytes,
inserts the FCS, and closes with the closing flag. Once
the closing flag is transmitted, the 8273 leaves the Execution phase and begins the Result phase. During the
Result phase the 8273 notifies the CPU of the outcome
of the command by supplying interrupt results. In this
case, the results would be either that the frame is complete or that some error condition causes the transmission to be aborted. Once the CPU reads all of the results (there is only one for the Transmit Frame
command), the Result phase and consequently the
operation, is complete. Now that we have a general
feeling for the operation of the 8273, let us discuss the
8273 in detail.

CPU Interface
The CPU interface consists of four major blocks: Control/Read/Write logic (C/R/W), internal registers,
data transfer logic, and data bus buffers.
The CPU module utilizes the C/R/W logic to issue
commands to the 8273. Once the 8273 receives a command and executes it, it returns the results (good/bad
completion) of the command by way of the C/R/W
logic. The C/R/W logic is supported kseven registers
which are addressed via the Ao, AI, RD, and WR signals, in addition to CS. The Ao and A I signals are generally derived from the two low order bits of the CPU
module address bus while RD and WR are the normal
I/O Read and Write signals found on the system control bus. Figure 7 shows the address of each register
using the C/R/W logic. The function of each register is
defined as follows:

HARDWARE ASPECTS OF THE 8273

Address Inputs

The 8273 block diagram is shown in Figure 6. It consists of two major interfaces: the CPU module interface
and the modem interface. Let's discuss each interface
separately.

.A1

Ao

CS-RD

CS-WR

0
0
1
1

0
1
0
1

Status
Result
TxlfR
RxlfR

Command
Parameter
Test Mode

Control Inputs

-

Figure 7. 8273 Register Selection

. - - - - - - - - - FLAG DETECT

, - - - - - - - CD
REGISTERS

.-------CTS

'TxI/R

COMMANO

RxllR

PARAMETER

TEST MODE

,-----RTS

STATUS
RESULT

080_7

p..---T'C

TxDRO-----t
DATA
TIMING
LOGIC

I----T'D

p..---iiXc
J-----RxD

L-_ _ _ _ _ DPLL
L---------32XCLK

Ao----I

A'---_I
INTERNAL
DATA BUS
RESET-----'
OCLK - - - - - - - '
TxlNT _ _ _ _ _---'
R,INT _ _ _ _ _ _...J
CPU MODULE INTERFACE

MODEM INTERFACE

611001-7

Figure 6. 8273 Block Diagram
2-117

inter

AP-36

Command-8273 operations are initiated by writing
the appropriate command byte into this register.
Parameter-Many commands require more information than found in the command itself. This additionalinformation is provided by way of the parameter register.

munications channel. Figure 8 illustrates the transfer
rate of data bytes that are acquired by the 8273 based
on link data rate. Full-duplex data rates above 9600
baud usually require DMA. Slower speeds mayor may
not require DMA depending on the task load and interrupt response time of the processor.
Figure 9 shows the 8273 in a typical DMA environment. Notice that a separate DMA controller, in this
case the Intel 8257, is required. The DMA controller
supplies the timing and addresses for the data transfers
while the 8273 manages the requesting of transfers and
the actual counting of the data block lengths. In this
case, elements of the data transfer interface are:

Immediate Result (Result}-The completion information (results) for commands which execute immediately
are provided in this register.
Transmit Interrupt Result (TxI/R)-Results of transmit operations are passed to the CPU in this register.
Receiver Interrupt Result (RxI/R)-Receive operation
results are passed to the CPU via this register.

TxDRQ: Transmit DMA Request-Asserted by the
8273, this line requests a DMA transfer from memory
to the 8273 for transmit.

Status-The general status of the 8273 is provided in
this register. The Status register supplies the handshaking necessary during various phases of the 8273 operation.

TxDACK.: Transmit DMA Acknowledge-Returned by
the 8257 in response to TxDRQ, this line notifies the
8273 that a request has been granted, and provides access to the transmitter data register.

Test Mode-This register provides a software reset
function for the 8273.
,
_The commands, parameters, and bit definition of these
registers are discussed in the following software section.
Notice that there are not specific transmit or receive
data registers. This feature is explained in the data
transfer logic discussion.
The final elements of the CIR/W logic are the interrupt lines (RxINT and TxINT). These lines notify the
CPU module that either the transmitter or the receiver
requires service; i.e., results should be read from the
appropriate interrupt result register or a data transfer is
required. The interrupt request remains active until all
the associated interrupt results have been read or the
data transfer is performed. Though using the interrupt
lines relieves the CPU module of the task of polling the
8273 to check if service is needed, the state of each
interrupt line is reflected by a bit in the Status register
and non-interrupt driven operation is possible by examining the contents of these bits periodically.
The 8273 supports two independent data interfaces
through the data transfer logic; receive data and transmit data. These interfaces are programmable for either
DMA or non-DMA data transfers. While the choice of
the configuration is up to the system designer, it is
based on the intended maximum data rate of the com-

RxDRQ: Receive DMA Request-Asserted by the 8273,
it requests a DMA transfer from the 8273 to memory
for a receive operation.
RxDACK: Receive DMA Acknowledge-Returned by
the 8257, it notifies the 8273 that a receive DMA cycle
has been granted, and provides a'icess to the receiver
data register.
RD: Read-Supplied by the 8257 to indicate data is to
be read from the 8273 and placed in memory.
WR: Write-Supplied by the 8257 to indicate data is to
be written to the 8273 from memory.
To request a DMA transfer the 8273 raises the appropriate DMA request line; let us assume it is a transmitter request (TxDRQ). Once the 8257 obtains control of
the system bus by way of its HOLD and HLDA (hold
acknowledge) lines, it notifies the 8273 that TxDRQ
has been granted by returning TxDACK and WR. The
TxDACK and WR signals transfer data to the 8273 for
a transmit, independent of the 8273 chip select pin
(CS). A similar sequence of events occurs for receiver
requests. This "hard select" of data into the transmitter
or out of the receiver alleviates the need for the normal
transmit and receive data registers addressed by a combination of address lines, CS, and WR or RD. Competi-

2-118

AP-36

tive devices that do not have this "hard select" feature
require the use of an external multiplexer to supply the
correct inputs for register selection during DMA. (Do
not forget that the SDLC controller sees both the addresses and control signals supplied by the DMA controller during DMA cycles.) Let us look at typical
frame transmit and frame receive sequences to better
see how the 8273 truly manages the DMA data transfer.

At this point the requests stop, the FCS and closing flag
are transmitted; and the TxINT line is raised, signaling
the CPU that the frame transmission is complete. Notice that after the initial command and parameter loading, absolutely no CPU intervention was required (since
DMA is used for data transfers) until the entire frame
was transmitted. Now let's look at a frame reception.

80 ms

Before a frame can be transmitted, the DMA controller
is supplied, by the CPU, the starting address for the
desired information field. The 8273 is then commanded
to transmit a frame. (Just how this is done is covered
later during our software discussion.) After the command, but before transmission begins, the 8273 needs a
little more information (parameters). Four parameters
are required for the transmit frame command: the address field byte, the control field byte, and two bytes
which are the least significant and most significant
bytes of the information field byte length. Once all four
parameters are loaded, the 8273 makes RTS (Requestto-Send) active and waits for CTS (Clear-to-Send) to go
active. Once CTS is active, the 8273 starts the frame
transmission. While the 8273 is transmitting the opening flag, address field, and control field; it starts making
transmitter'DMA requests. These requests continue at
character (byte) boundaries until the pre-loaded number of bytes of information field have been transmitted.

8 ms
sec/byte
800

"s

80 "s

100

DACK1
DROO
DACKO

TxDACK
RxDRO

10K

100K

BAUD RATE (bps)
611001-8

Figure 8. Byte Transfer Rate vs Baud Rate

DR01
8257
DMA
CONTROLLER

1K

RD
8273

RxDACK
CS AO

lOR
lOW

WR
A1

r'm'o,
BUS

07-DO

~ ~OA"""'

ADDRESS
BUS

611001-9

Figure 9. DMA, Interrupt-Driven System

2-119

inter

AP-36

The receiver operation is very similar. Like the initial
transmit sequence, the DMA controller is loaded with a
starting address for a receiver data buffer and the 8273
is commanded to receive. Unlike the transmitter, there
are two different receive commands: General Receive,
where all received frames are transferred to memory,
and Selective Receive, where only frames having an address field matching one of two preprogrammed 8273
address fields are transferred to memory. Let's assume
for now that we want to general receive. After the receive command, two parameters are required before the
receiver becomes active: the least significant and most
significant bytes of the receiver buffer length. Once
these bytes are loaded, the receiver is active and the
CPU may return to other tasks. The next frame appearing at the receiver input is transferred to memory using
receiver DMA requests. When the closing flag is received, the 8273 checks the FCS and raises its RxINT
line. The CPU can then read the results which indicate
if the frame was error-free or not. (If the received frame
had been longer than the pre-loaded buffer length, the
CPU would have been notified of that occurrence earlier with a receiver error interrupt. The command description section contains a complete list of error conditions.) Like the transmit example, after the initial command, the CPU is free for other tasks until a frame is
completely received. These examples have illustrated
the 8273's management of both the receiver and transmitter DMA channels.
It is possible to use the DMA data transfer interface in

a non-DMA interrupt-driven environment. In this case,
4 interrupt levels are used: one each for TxINT and
RxINT, and one each for TxDRQ and RxDRQ. This
configuration is shown in Figure 10. This configuration
offers the advantages that no DMA controller is re-

quired and data requests are still separated from result
(completion) requests. The disadvantages of the configuration are that 4 interrupt levels are required and that
the CPU must actually supply the data transfers. This,
of course, reduces the maximum data rate compared to
the configuration based strictly on DMA. This system
could use an Intel 8259 8-level Priority Interrupt Controller to supply a vectored CALL (subroutine) address
based on requests on its inputs. The 8273 transmitter
and receiver make data requests by raising the respective DRQ line. The CPU is interrupted by the 8259 and
vectored to a data transfer routine. This routine either
writes (for transmit) or reads (for receive) the 8273 using the respective TxDACK or RxDACK line. The
DACK lines serve as "hard" chip selects into and out
of the 8273. TxDACK + WR writes data into the 8273
for transmit. RxDACK + RD reads data from the
8273 for receive.) The CPU is notified of operation
completion and results by way of TxINT and RxINT
lines. Using the 8273, and the 8259, in this way, provides a very effective, yet simple, interrupt-driven interface.
Figure 11 illustrates a system very similar to that described above. This system utilizes the 8273 in a nonDMA data transfer mode as opposed to the two DMA
approaches shown in Figures 9 and 10. In the nonDMA case, data transfer requests are made on the
TxINT and RxINT lines. The DRQ lines are not used.
Data transfer requests are separated from result requests by a bit in the Status register. Thus, in response
to an iJ;lterrupt, the CPU reads the'Status register and
branches to either a result or a data transfer routine
based on the status of one bit. As before, data transfers
are made via using the DACK lines as chip selects to
the transmitter and receiver data registers.

07-00

611001-10

Figure 10. Interrupt-Based DMA System

2-120

infef

AP-36

CONTROL
BUS

611001-11

Figure 11. Non-DMA Interrupt-Driven System

NC

NC

NC

NC

lOR

-CONTROL
BUS

TxOACK

8213

01-00

_DATA BUS

611001-12

Figure 12. Polled System

Figure 12 illustrates the simplest system of all. This
system utilizes polling for all data transfers and results.
Since the interrupt pins are reflected in bits in the
Status register, the software can read the Status register
periodically looking for one of these to be set. If it finds
an INT bit set, the appropriate Result Available bit is
examined to determine if the "interrupt" is a data
transfer or completion result. If a data transfer is called
for, the DACK line is used to enter or read the data
from the 8273. If the interrupt is a completion result,
the appropriate result register is read to determine the
good/bad completion of the operation.

The final block of the CPU module interface is the
Data Bus Buffer. This block supplies the tri-state, bidirectional data bus interface to allow communication to
and from the 8273.

The actual selection of either DMA or non-DMA
modes is controlled by a command issued during initialization. This command is covered in detail during
the software discussion.

The modem control block provides both dedicated and
user·defined modem control functions. All signals s'upported by this interface are active low so that EIA .in-

2-121

Modem Interface
As the name implies, the modem interface is the modem side of the 8273. It consists of two major blocks:
the modem control block and the serial data timing
block.

inter

AP-36

This function is handled automatically by the 8273. If
RTS is inactive (pin is high) when the 8273 is commanded to transmit, the 8273 makes it active and then
waits for CTS before transmitting the frame. One byte
time after the end of the frame, the 8273 returns RTS to
its inactive state. However, if RTS was active when a
transmit command is issued, the 8273 leaves it active
when the frame is complete.

verting drivers (MCI488) and inverting receivers
(MCI489) may be used to interface to standard modems.
Port A is a modem control input port. Its representation on the data bus is shown in Figure 13. Bits DO and
D1 have dedicated functions. Do reflects the logical
state of the CTS (Clear-to-Send) pin. [If CTS is active
(low), Do is a I.J This signal is used to condition the
start of a transmission. The 8273 waits until CTS is
active before it starts transmitting a frame. While transmitting, if CTS goes inactive, the frame is aborted and
the CPU is interrupted. When the' CPU reads the interrupt result, a CTS failure is indicated.

Bit D5 reflects the state of the Flag Detect pin. This pin
is activated whenever an active receiver sees a flag character. This function is useful to activate a timer for line
activity timeout purposes.

D) reflects the logical state of the CD (Carrier Detect)
pin. CD is used to condition the start of a frame reception. CD must be active in time for a frame's address
field. If CD is lost (goes inactive) while receiving a
frame, an interrupt is generated with a CD failure result. CD may go inactive between frames.

Bits DI thru D4 provide four user-defined outputs. Pins
PBI thru PB4 reflect the logical state of these bits. The
8273 does not interrogate or manipulate these bits. D6
and D7 are not used. In addition to being able to output
to Port B, Port B may be read using a Read Port B
command. All Modem control output pins are forced
high on reset. (All commands mentioned in this section
are covered in detail later.)

Bits D2 thru D4 reflect the logical state of the PA2 thru
P A4 pins respectively. These inputs are user defined.
The 8273 does not interrogate or manipulate these bits.
Bits D5, D6, and D7 are not used and each is read as a I
for a Read Port A command.

The final block to be covered is the serial data timing
block. This block contains two sections: the serial data
logic and the digital phase locked loop (DPLL).
Elements of the serial data logic section are the data
pins, TxD (transmit data output) and RxD (receive
data input), and the respective data clocks, TxC and
RxC. The transmit and receive data is synchronized by
the TxC and RxC clocks. Figure 15 shows the timing
for these signals. The leading edge (negative transition)

Port B is a modem control output port. Its data bus
representation is shown in Figure 14. As in Port A, the
bit values represent the logical condition of the pins. Do
and ~are dedicated function o~ts. Do represents
the RTS (Request-to-Send) pin. RTS is normally used
to notify the modem that the 8273 wishes to transmit.

D7

1,

D6

DS

1

I I

D4

Dj

D2

D,

DO'

~ C~EAR

I

1

I

I I

CTS TO SEND
CD - CARRIER DETECT
PA2 }
PAa
USER·DEFINED INPUTS
PA4

611001-13

Figure 13. Port A (Input) Bit Definition

D7

D6

l' I

1

DS

I

D4

I

Da

I

D,

D2

I

I

lI

Do

I

I

L

l

RTS _ REQUEST TO SEND
PB,
PB2
USER,DEFINED OUTPUTS
PBa
PB4
FLAG DETECT

611001-14

Figure 14_ Port B (Output) Bit Definition

2-122

AP-36

nal circuitry. Clock loopback overcomes th~oblem
by allowing the internal routing of TxC and RxC. Thus
the same clock used to transmit the data is used to
receive it. Examination of Figure 15 shows that this
method ensures bit synchronism. The final element of
the serial data logic is the Digital Phase Locked Loop.

of TxC generates new transmit data and the trailing
edge (positive transition) of RxC is used to capture the
receive data.

hO

The DPLL provides a means of clock recovery from
the received data stream. This feature allows the 8273
to interface without external synchronizing logic to low
cost asynchronous modems (modems which do not
supply clocks). It also makes the problem of clock timing in loop configurations trivial.

=x'--------'

:::~

To use the DPLL, a clock at 32 times the required baud
rate must be supplied to the 32 X CLK pin. This clock
provides the interval that the DPLL samples the received data. The DPLL uses the 32 X clock and the
received data to generate a pulse at the DPLL output
pin. This DPLL pulse is positioned at the nominal center of the received data bit cell. Thus the DPLL output
may be wired to RxC and/or TxC to supply the data
timing. The exact position of the pulse is varied depending on the line noise and bit distortion of the received
data. The adjustment of the DPLL position is determined according to the rules outlined in Figure 16.

611001-15

Figure 15. Transmit/Receive Timing
It is possible to reconfigure this section under program
control to perform diagnostic functions; both data and
clock loop back are available. In data loop back mode,
the TxD pin is internally routed to the RxD pin. This
allows simple board checkout since the CPU can send
an SDLC message to itself. (Note that transmitted data
will still appear on the TxD pin.)

Adjustments to the sample phase of DPLL with respect
to the received data is made in discrete increments. Referring to Figure 16, following the occurrence of DPLL

When data loopback is utilized, the receiver may be
presented incorrect sample timing (RxC) by the exter-

1 BIT TIME

x

R,D
NO TRANSITION

2 4 6 8 10 12 14 16 18 2D 22 24 26 28 30 32

1 - - - - - 3 2 CLOCKS - - - - - 1

DPlL

1 - - - 1 - - - 30 CLOCKS --':~-=--I

I

I

I

I

I

I

1~--If---33CLOCKS

I

I

I

I

I

I

:1

I1

I
I

I
I

I
QUADRANT I
ADJUSTMENT I

A,
-2

I
I

I

C-2

I

I

A

I
32 CLOCKS

---+----

F

---t----

I
I

.,
-1

I
' .2

I

C NOMINAL

I

+1

I
A2
+2

I
I

611001-16

Figure 16. DPLL Phase Adjustments

2-123

AP-36

pulse A, the DPLL counts 32 X CLK pulses and examines the received data for a data edge. Should no edge
be detected in 32 pulses, the DPLL positions the next
DPLL pulse (B) at 32 clock pulses from pulse A. Since
no new phase information is contained in the data
stream, the sample phase is assumed to be at nominal
1 X baud rate. Now assume a data edge occurs after
DPLL pulse B. The distance from B to the next pulse C
is influenced according to which quadrant (A[, B[, B2,
or A2) the data edge falls in. (Each quadrant represents
8 32 X CLK times.) For example, if the edge is detected
in quadrant AI, it is apparent that pulse B was too close
to the data edge and the time to the next pulse must be
shortened. The adjustment for quadrant A I is specified
as - 2. Thus, the next DPlI pulse, pulse C, is positioned 32 - 2 or 30 32 X CLK pulses following DPLL
pulse B. This adjustment moves pulse C closer to the
nominal bit center of the next received data cell. A data
edge occurring in quadrant B2 would have caused the
adjustment to be small, namely 32 + 1 or 33 32 X
CLK pulses. Using this technique, the DPLL pulse
converges to the nominal bit center within 12 data transitions, worse case-4-bit times adjusting through
quadrant Al or A2 and 8-bit times adjusting through
BI or B2.

This completes our discussion of the hardware aspects
of the 8273. Its software aspects are now discussed.

T,e
T,O
8273

RiC

SYNC
MODEM

R,O
32XCLK

DPLL
Ne

611001-17
Synchronous Modem Interface

611001-18
Asynchronous Modem Interface

When the receive data stream goes idle after 15' ones,
DPLL pulses are generated at 32 pulse intervals of the
32 X CLK. This feature allows the DPLL pulses to be
used as both transmitter and receiver clocks.

Figure 17. Serial Data Timing Configuration

SOFTWARE ASPECTS OF THE 8273
In order to guarantee sufficient transitions of the received data to enable the DPLL to lock, NRZI encoding of the data is recommended. This ensures that,
within a frame, data transitions occur at least every five
bit times-the longest sequence of Is which may be
transmitted with zero bit insertion. It is also recommended that frames following a line idle be transmitted
with preframe sync characters which provide a minimum of 12 transitions. This ensures that the DPLL is
generating DPLL pulses at the nominal bit centers in
time for the opening flag. (Two OOH characters meet
this requirement by supplying 16 transitions with
NRZI encoding. The 8273 contains a mode which supplies such a preframe sync.)

The software aspects of the 8273 involve the communication of both commands from the CPU to the 8273
and the return of results of those commands from the
8273 to the CPU. Due to the internal processor architecture of the 8273, this CPU-8273 communication is
basically a form of interprocessor communication. Such
communication usually requires a form of protocol of
its own. This protocol is implemented through use of
handshaking supplied in the 8273 Status register. The
bit definition of this register is shown in Figure 18.

Figure 17 illustrates 8273 clock configurations using
either synchronous or asynchronous modems. Notice
how the DPLL output is used for both TxC and RxC in
.the asynchronous case. This feature eliminates the need
for external clock generation logic where low cost asynchronous modems are used and also allows direct connection of 8273s for the ultimate in low cost data links.
The configuration for loop applications is discussed in a
following section.

2-124

T.'RA R~IRA

hiNT RESULT AVAILABLE

- R.INT RESULT AVAILABLE

L~=~====

TxlNT
INTERRUPT
Rill NT -- hR.l.INTERRUPT
CRBF - COMMAND RESULT
- BUFFER FULL
' - - - - - - - - CPBF - COMMAND PARAMETER
BUFFER FULL

' - - - - - - - - - - C B F - COMMAND BUFFER FUll
' - - - - - - - - - - - C B S y - COMMAND BUSY

611001-19

Figure 18. Status Register Format

inter

AP-36

CBSY: Command Busy-CBSY indicates when the
8273 is in the command phase. CBSY is set when the
CPU writes a command into the Command register,
starting the Command phase. It is reset when the last
parameter is deposited in the Parameter register and
accepted by the 8273, completing the Command phase.
CBF: Command Buffer Full-When set, this bit indicates that a byte is present in the Command register.
This bit is normally not used.
CPBF: Command Parameter Buffer Full-This bit indicates that the Parameter register contains a paramete~. It is set when the CPU deposits a parameter in the
Parameter register. It is reset when the 8273 accepts the
parameter.
CRBF: Command Result Buffer Full-This bit is set
when the 8273 places a result from an immediate type
command in the Result register. It is reset when the
CPU reads the result from the Result register.
RxINT: Receiver Interrupt-The state of the RxINT
pin is reflected by this bit. RxINT is set by the 8273
whenever the receiver needs servicing. RxINT is reset
when the CPU reads the results or performs the data
transfer.
TxINT: Transmitter Interrupt-This bit is identical to
RxINT except action is initiated based on transmitter
interrupt sources.
RxIRA: Receiver Interrupt Result Available-RxIRA is
set when the 8273 places an interrupt result byte into
the RxI/R regis~er. RxIRA is reset when the CPU
. reads the RxI/R register.
TxIRA: Transmitter Interrupt Result AvailableTxIRA is the corresponding Result Available bit for
the transmitter. It is set when the '8273 places an interrupt result byte in the TxI/R register and reset when
the CPU reads the register.
The significance of each of these bits will be evident
shortly. Since the software requirements of each 8273
phase are essentially independent, each phase is covered
separately.

Command Phase Software
Recalling the Command phase description in an earlier
section, the CPU starts the Command phase by writing
a command byte into the 8273 Command register. If
further information about the command is required by
the 8273, the CPU writes this information into the Parameter register. Figure 19 is a flowchart of the Command phase. Notice that the CBSY and CPBF bits of
the Status register are used to handshake the command
and parameter bytes. Also note that the chart shows

611001-20

Figure 19. Command Phase Flowchart

that a command may not be issued if the Status register
indicates the 8273 is busy (CBSY = 1). If a command
is issued while CBSY = 1, the original command is
overwritten and lost. (Remember that CBSY signifies
the command phase is in progress and not the actual
execution of the command.) The flowchart also ,includes a Parameter buffer full check. The CPU must
wait until CPBF = 0 before writing a parameter to the
Parameter register. Ifa parameter is issued while CPBF
= 1, the previous parameter is overwritten and lost.
An example of command output assembly language
software is provided in Figure 20a. This software assumes that a command buffer exists in memory. The'
buffer is pointed at by the HL register. Figure 20b
shows the command buffer structure.
The 8273 is a full duplex device, i.e., both the transmitter and receiver may be executing commands or' passing
interrupt results at any given time. (Separate Rx and Tx
interrupt pins and result registers are provided for this
reason.) However, there is only one Command register.
Thus, the Command register must be used for only one
command sequence at a time and the transmitter and
. receiver may never be simultaneously in a command
phase. A detailed description of the commands and
their parameters is presented in a following section.

2-125

inter

Ap·36

;FUNCTION: COMMAND DISPATCHER
;INPUTS: HL - COMMAND BUFFER ADDRESS
;OUTPUTS: NONE
;CALLS: NONE
;DESTROYS: A,B,H,L,F/F'S
;DESCRIPTION: CMDOUT ISSUES THE COMMAND + PARAMETERS
;IN THE COMMAND BUFFER POINTED AT BY HL
CMDOUT: LXI
MOV
INX
CMD1:
IN
RLC
JC
MOV
OUT
CMD2:
MOV
ANA
RZ
INX
DCR
CMD3:
IN
ANI
JNZ
MOV
OUT
JMP

H,CMDBUF ;POINT HL AT BUFFER
B,M
;lST ENTRY IS PAR. COUNT
H
;POINT AT COMMAND BYTE
STAT73
;READ 8273 STATUS'
;ROTATE CBSY INTO CARRY
CMDl
;WAIT UNTIL CBSY=O
A,M
;MOVE COMMAND BYTE TO A
;PUT COMMAND IN COMMAND REG
COMM73
A,B
;GET PARAMETER COUNT
A
;TEST IF ZERO
;IF 0 THEN DONE
H
;NOT DONE, SO POINT AT NEXT PAR
;DEC PARAMETER COUNT
B
STAT73
;READ 8273 STATUS
CPBF
;TEST CPBF BIT
CMD3
;WAIT UNTIL CPBF IS 0
A,M
;GET PARAMETER FROM BUFFER
PARM73
;OUTPUT·PAR TO PARAMETER REG
;CHECK IF MORE PARAMETERS
CMD2
Figure 20A. Command Phase Software

+4

PARAMETER 3

+3

PARAMETER 2

+2

PARAMETER 1

+1
CMDBUF:

Execution Phase Software

COMMAND
PARAMETER COUNT

~HL

Figure 20B. Command Buffer Format

During the Execution phase, the operation specified by
the Command phase is performed. If the system utilizes
DMA for data transfers, there is no CPU involvement
during this phase, so no software is required. If nonDMA data transfers are used, either interrupts or polling is used to signal a data transfer request.
For interrupt-driven transfers the 8273 raises the appropriate INT pin. When responding to the interrupt,

2-126

infef

Ap·36

the CPU must determine whether it is a data transfer
request or an interrupt signaling that an operation is
complete and results are available. The CPU determines the cause'by reading the Status register and interrogating the associated IRA (Interrupt Result
Available) bit (TxIRA for TxINT and RxIRA for
RxINT). If the IRA = 0, the interrupt is a data
transfer request. If the IRA = I, an operation is
complete and the associated Interrupt Result register
must be read to determine the completion status (good/
bad/etc.). A software interrupt handler implementing
the above sequence is presented as part of the Result
phase software.
When polling is used to determine when data transfers
are required, the polling routine reads the Status register looking for one of the INT bits to be set. When a set
INT bit is found, the corresponding IRA bit is examined. Like in the interrupt-driven case, if the IRA = 0,
a data transfer is required. If IRA = I, an operation is
complete and the Interrupt Result register needs to be
read. Again, example polling software is presented in
the next section.

Result Phase Software
During the Result phase the 8273 notifies the CPU of
the outcome of a command. The Result phase is initiated by either a successful completion of an operation or
an error detected during execution. Some commands
such as reading or writing the I/O ports provide immediate results, that is, there is essentially no delay from
the issuing of the command and when the result is
available. Other commands such as frame transmit,
take time to complete so their result is not available
immediately. Separate result registers are provided to
distinguish these two types of commands and to avoid
interrupt handling for simple results.

Immediate results are provided in the Result register.
Validity of information in this register is indicated to
the CPU by way of the CRBF bit in the Status register.
When the CPU completes the Command phase of an
immediate command, it polls the Status register waiting
until CRBF = 1. When this occurs, the CPU may read
the Result register to obtain the immediate result. The
Result register provides only the results from immediate commands.
Example software for handling immediate results is
shown in Figure 21. The routine returns with the result
in the accumulator. The CPU then uses the result as is
appropriate.
All non-immediate commands deal with either the
transmitter or'receiver. Results from these commands
are provided in the TxI/R (Transmit Interrupt Result)
and RxI/R (Receive Interrupt Result) registers respectively. Results in these registers are conveyed to the
CPU by the TxIRA and RxIRA bits of the status register. Results of non-immediate commands consist of one
byte result interrupt code indicating the condition for
the interrupt and, if required, one or more bytes supplying additional information. The interrupt codes and the
meaning of the additional results are covered following
the detailed command description.
Non-immediate results are passed to the CPU in response to either interrupts or polling of the Status register. Figure 22 illustrates an interrupt-driven result handier. (Please note that all of the software presented in
this application note is not optimized for either speed or
code efficiency. They are provided as a guide and to
illustrate concepts.) This handler provides for interrupt-driven data transfers as was promised in the last
section. Users employing DMA~based transfers do not

;FUNCTION: IMDRLT
;INPUTS: NONE
;OUTPUTS: RESULT REGISTER IN A
;CALLS: NONE
;DESTROYS: A, F/F'S
;DESCRIPTION: IMDRLT IS CALLED AFTER A CMDOUT FOR AN
;IMMEDIATE COMMAND TO READ THE RESULT REGISTER
IMDRLT: IN
ANI
JZ
IN
RET

STAT 73
CRBF
IMDRLT
RESL73
;RETURN

;READ
;TEST
;WAIT
;READ

8273 STATUS
IF RESULT REG READY
IF CRBF=O
RESULT REGISTER

Figure 21. Immediate Result Handler

2·127

intJ

AP-36

;FUNCTION: RXI :INPUTS: RCRBUF,
;CALLS: NONE

place the results in a result. buffer pointed at by
RCRBUF and TxRBUF,

INTERRUPT DRIVEN RESULT/DATA HANDLEH
RCVPNT

:OU'rpUTS: RCRBUF, RCVPNT

A typical result handler for systems utilizing polling is
shown in Figure 23, Data transfers are also handled by
this routine, This routine utilizes the routines of Figure
22 to handle the results,

; DESTROYS: NOTHING

IS ENTERED AT It. RECEIVER IN'l'ERRUPT.
:THE INTERRUPT IS TESTED FOR DATA TRANSFER (IRA"'0)
;OR RESULT (IRA a l).
FOR DATA TRANSFER. THE DATA IS
;PLAC£D IN A BUFFER AT RCVPNT. RESULTS ARE PLACED IN
; A BUFFER AT RCRDUF.
iA FLAG IRXFLAGJ IS SET IF TttE INTERRUPT WAS Po RESULT.
; (DATA TRANSFER INSTRUCTIONS ARE DENOTED BY (*) AND
;DESCRIPTION: RXI

:HAYBE ELIMINATED BY USt.RS USING OMA.

"

RXI:

PUSb
PUSH
PUSH

IN
ANI
JZ

AXIl:

LULD
IN

A.,
JZ
IN
ANI
JZ
IN

MOV
INX
BULD

JHF
AXI2,:

kX!4:

SHLD
IN
MOV
INX

J"P
MVI
STA

AXIl:

POP
POP
POP

EI
REl'

H
PSW
B

At this point, the readef'Should have a good conceptual
feel about how the 8273 operates, It is now time for the
particulars of each command to be discussed,

;SAVE
;SAVE
;SAVE
: (*)
: (*)

HL
PSW I
B
STAT71
R!::AD 8271 STA1'US
RXIRA
1'1;;:'T IRA B11'
RXI2
: C*) IF It, DA1'A TRAhSFE1-c NI:.I::CED
RCRBUF
;GE'r RE.SuL1' BuFfl::J., PuIN'lt::R
STAT71
;Nt-AC 8271 S'I'A1'US AGAlh '
RXINT
;TE.5T INT BI'I:
RXl4
:IF e, 'l'H~h [jONE.
STAT71
;READ 8271 S1'A1'US AGAIN
RXIAA
;TEST IkA AGAI~
RUI
: LllOP UN'I I L R~SUL,[ IS hEAD's
aXIR71
;R.E.ACY, If'¥1 ~
l

Parameter

Serial 1/0 Mode

CLOCK LOOPBACK

Figure 25. Serial I/O Mode Register

De

Hex
Code

ZOMODE

611001-22

07

Command

Operating Mode

I ,1.1 ••
~

"

Register

The 8273 supports three receive commands plus a receiver disable function.

INTERRUPT DATA TRANSFERS
NOT USED - DO NOT CHANGE

611001-23

General Receive

Figure 26. Data Transfer Mode Register

One Bit Delay Register (Figure 27)
One Bit Delay-When set, the 8273 retransmits the received data stream one bit delayed.
This mode is entered and exited at a received
character boundary. When reset, the transmitted and received data are independent. This
mode is utilized for loop operation and is discussed in a later section.
D6-DO: Not Used-These bit must be 0 for the Set
command and 1 for the Reset command.

D7:

When commanded to General Receive, the 8273 passes
all frames either to memory (DMA mode) or to the
CPU (non-DMA mode) regardless of the contents of
the frame's address field. This command is used for
primary and loop controller stations. Two parameters
are required: Bo and BI. These parameters are. the LSB
and MSB of the receiver buffer size. Giving the 8273
this extra information alleviates the CPU of the burden
of checking for buffer overflow. The 8273 will interrupt
the CPU if the received frame attempts to overfill the
allotted buffer space.

Selective Receive

NOT USED -

DO NOT CHANGE

ONE BIT DELAY ENABLE

611001-24

Figure 27. One Bit Delay Mode Register

Figure 28 shows the Set and Reset commands associated with the above registers. The mask which sets or
resets the desired bits is treated as a single parameter.
These commands do not interrupt nor provide results
during the Result phase. After reset, the 8273 defaults
to all of these bits reset;

In Selective Receive, two additional parameters besides
Bo and BI are required: Al and A2. These parameters
are two address match bytes. When commanded to Selective Receive, the 8273 passes to memory or the CPU
only those frames having an address field matching either A I or A2. This command is usually used for secondary stations with A I being the secondary address
and A2 is the "All Parties" address. If only one match
byte is needed, Al and A2 should be equal. As in General Receive, the 8273 counts the incoming data bytes
and interrupts the CPU if Bo, BI is exceeded.

Selective Loop Receive
This command is very similar in operation to Selective
Receive except that One Bit Delay mode must be set

2-130

inter

Ap·36

and that the loop is captured by placing transmitter in
Flag Stream mode automatically after an EOP character is detected following a selectively received frame.
The details of using the 8273 in loop configurations is
discussed in a later section so please hold questions until then.
The handling of interrupt results is common among the
three commands. When a frame is received without error, i.e., the FCS is correct and CD (Carrier Detect)
was active throughout the frame or no attempt was
made to overfill the buffer; the 8273 interrupts the CPU
following the closing flag to pass the completion results. These results, in order, are the receiver. interrupt
result code (RIC), and the byte length of the information field of the received frame (RO, R\). If Buffered
mode .is selected, the address and control fields are
passed as two additional results. If Buffered mode is not
selected, the address and control fields are passed as the

first two data transfers and RO, R\ reflect the information field length plus two.

Receive Disable
The receiver may also be disabled using the Receive
Disable command. This command terminates any receive operation immediately. No parameters are required and no results are returned.
The details for the Receive command are shown in Figure 29. The interrupt result code key is shown in Figure
30. Some explanation of these result codes is appropriate.
The interrupt result code is the first
CPU in the RxI/R register during
Bits D4 - Do define the cause of the
Since each result code has specific
are discussed separately below.

byte passed to the
the Result phase.
receiver interrupt.
implications, they

Command

Hex
Code

Parameters

Results'
Rxl/R

General Receive
Selective Receive
Selective Loop Receive
Disable Receiver

CO
C1
C2
C5

. Bo, B1
Bo, B1, A1, A2
Bo, B1, A1, A2
None

RIC, Ro, R1, A, C
RIC, Ro, R1, A, C
RIC, Ro, R1, A, C
None

"NOTE:
A and C are passed as'results only in buffered mode.

Figure 29. Receiver Command Summary
RIC

07- 0 0

•
"
000
000
000
000
000
000
000
000
000

00000
00001
00011
00100
00101
00110
00111
01000
01001
01010
01011

'07- 0 5
111
000
100
010
110
001
101
011

Receiver Interrupt Result Code

Rx Status
After INT

A1 Match or General Receive
A2 Match
CRC Error
Abort Detected
Idle Detected
EOP Detected
Frame < 32 Bits
DMAOverrun
Memory Buffer Overflow
Carrier Detect Failure
Receiver Interrupt Overrun

Active
. Active
. Active
Active
Disabled
Disabled
Active
Disabled
Disabled
Disabled
Disabled

Partial Byte Received
All 8 Bits of Last Byte
Do
01- 0 0
02- 0 0
03- 0 0
04- 0 0
05- 0 0
06- 0 0
Figure 30. Receiver Interrupt Result Codes (RIC)
2-131

intJ

AP-36

The first two result codes result from the error-free reception of a frame. If the frame is received correctly
after a General Receive command, the first result is
returned. If either Selective Receive command was used
(normal or loop), a match with Al generates the first
result code and a match with A2 generates the second.
In either case, the receiver remains active after the interrupt; however, the internal buffer size counters are
not reset. That is, if the receive command indicated 100
bytes were allocated to the receive buffer (Bo, BI) and
an 80-byte frame was received correctly, the maximum
next frame size that could be received without recommanding the receiver (resetting Bo and BI) is 20 bytes.
Thus, it is common practice to recommand the receiver
after each frame reception. DMA and/or memory
pointers are usually updated at this time. (Note that
users who do not wish to take advantage of the 8273's
buffer management features may simply use Bo, BI =
OFFH for each receive command. Then frames of 65K
bytes may be received without buffer overflow errors.)
The third result code is a CRC error. This indicates
that a frame was received in the correct format (flags,
etc.); however, the received FCS did not check with the
internally generated FCS. The frame should be discarded. The receiver remains active. (Do not forget that
even though an error condition has been detected, all
frame information up until that error has either been
transferred to memory or passed to the CPU. This information should be invalidated. This .applies to all receiver error conditions~) Note that the FCS, either
transmitted or received, is never available to the CPU.
The Abort Detect result occurs whenever the receiver
sees either an SDLC (8 Is) or an HDLC (7 Is), depending on the Operating Mode register. However, the intervening Abort character between a closing flag and an
Idle does not generate an interrupt. If an Abort character (seen by an active receiver within a frame) is not
preceded by a flag and is followed by an idle, an interrupt will be generated for the Abort, followed by an
Idle interrupt one character time later. The Idle Detect
result occurs whenever 15 consecutive Is are received.
After the Abort Detect interrupt, the receiver remains
active. After the Idle Detect interrupt, the receiver is
disabled and must be recommanded before further
frames may be received.
If the EOP Interrupt bit is set in the Operating Mode
register, the EOP Detect result is returned whenever an
EOP character is received. The receiver is disabled, so
the Idle following the EOP does not generate an Idle
Detect interrupt.
The minimum number of bits in a valid frame between
the flags is 32. Fewer than 32 bits indicates an error. If
Buffered mode is selected, such frames are ignored, i.e.,
no data transfers or interrupts are generated. In nonBuffered mode, a < 32-bit frame generates an interrupt

with the < 32-bit frame result since data transfers may
already have disturbed the 8257 or interrupt handler.
The receiver remains active.
The DMA Overrun results from the DMA controller
being too slow in extracting data from the 8273, i.e., the
RxDACK signal is not returned before the next received byte is ready for transfer. The receiver is disabled if this error condition occurs.
The Memory Buffer Overflow result occurs when the
number of received bytes exceeds the receiver buffer
length supplied by the Bo and BI parameters in the
receive command. The receiver is disabled.
The Carrier Detect Failure result occurs when the CD
pin ~ high (inactive) during reception of a frame.
The CD pin is used to qualify reception and must be
active by the time the address field starts to be received.
If CD is lost during the frame, a CD Failure interrupt
is generated and the receiver is disabled. No interrupt is
generated if CD goes inactive between frames.
If a condition occurs requiring an interrupt be generated before the CPU has finished reading the previous
interrupt results, the second interrupt is generated after
the current Result phase is complete (the RxINT pin
and status bit go low then high). However, the interrupt result for this second interrupt will be a Receive
Interrupt Overrun. The actual cause of the second interrupt is lost. One case where this may occur is at the
end of a received frame where the line goes idle. The
8273 generates a received frame interrupt after the closing flag and then IS-bit times later, generates an Idle
Detect interrupt. If the interrupt service routine is slow
in reading the first interrupt's results, the internal
Rxl/R register still contains result information when
the Idle Detect interrupt occurs. Rather than wiping
out the previous results, the 8273 adds a Receive Interrupt Overrun result as an extra result. If the system's
interrupt structure is such that the second interrupt is
not acknowledged (interrupts are still disabled from the
first interrupt), the Receive Interrupt Overrun result· is
read as an !;xtra result, after those from the first interrupt. If the second interrupt is serviced, the Receive
Interrupt Overrun is returned as a single result. (Note
that the INT pins supply the necessary transitions to
support a Programmable Interrupt Controller such as
the Intel 8259. Each interrupt generates a positive-going edge on the appropriate INT pin and the high level
is held until the interrupt is completely serviced.) In
general, it is possible to have interrupts occurring at
one character time intervals. Thus the interrupt handling software must have at least that much response
and service time.
The occurrence of Receive Interrupt Overruns is an indication of marginal software design; the system's interrupt response and servicing time is not sufficient for the

2-132

intJ

Ap·36

data rates being attempted. It is advisable to configure
the interrupt handling software to simply read the interrupt results, place them into a buffer, and clear the
interrupt as quickly as possible. The software can then
examine the buffer for new results at its leisure, and
take appropriate action. This can easily be accomplished by using a result buffer flag that indicates when
new results are available. The interrupt handler sets the
flag and the main program resets it once the results are
retrieved.
Both SDLC and HDLC allow frames which are of arbitrary length (> 32 bits). The 8273 handles this N-bit
reception through the high order bits (D7-DS) of the
result code. These bits code the number of valid received bits in the last received information field byte.
This coding is shown in Figure 30. The high order bits
of the received partial byte are indeterminate. [The address, control, and information fields are transmitted
least significant bit (Aa) first. The FCS is complemented and transmitted most significant bit first.]

Transmit Commands
The 8273 transmitter is supported by three Transmit
commands and three corresponding Abort commands.

returns to either Idle or Flag Stream, depending on the
Flag Stream bit of the Operating Mode register. IfRTS
was active before the transmit command, the 8273 does
not change it. If it was inactive, the 8273 will deactivate
it within one character time.

Loop Transmit
Loop Transmit is similar to Frame Transmit (the parameter definition is the same). But since it deals with
loop configurations, One Bit Delay mode must be selected.
If the transmitter is not in Flag Stream mode when this
command is issued, the transmitter waits until after a
received EOP character has been converted to a flag
(this is done automatically) before transmitting. (The
one bit delay is, of course, suspended during transmit.)
If the transmitter is already in Flag Stream mode as a
result of a selectively received frame during a Selective
Loop Receive command, transmission will begin at the
next flag boundary for Buffered mode or at the third
flag boundary for non-Buffered mode. This discrepancy
is to allow time for enough data transfers to occur to fill
up the internal transmit buffer. At the end of a Loop
Transmit, the One Bit Delay mode is re-entered and the
flag stream mode is reset. More detailed loop operation
is covered later.

Transmit Frame
The Transmit Frame command simply transmits a
frame. Four parameters are required when Buffered
mode is selected and two when it is not. In either case,
the first two parameters are the least and the most significant bytes of the desired frame length (La, L,). In
Buffered mode, La and L, equal the length in bytes of
the desired information field, while in the non-Buffered
mode, La and L, must be specified at the information
field length plus two. (La and L, specify the number of
data transfers to be performed.) In Buffered mode, the
address and control fields are presented to the transmitter as the third and fourth parameters respectively. In
non-Buffered mode, the A and C fields must be passed
as the first two data transfers.

Transmit Transparent
The Transmit Transparent command enables the 8273
to transmit a block of raw data. This data is without
SDLC protocol, i.e., no zero bit insertion, flags, or
FCS. Thus it is possible to construct and transmit a BiSync message for front-end processor switching or to
construct and transmit an SDLC message with incorrect FCS for diagnostic purposes. Only the La and L,
parameters are used since there are not fields in this
mode. (The 8273 does not support a Receive Transparent command.)

Abort Commands
When the Transmit Frame command is issued, the'
8273 makes RTS (Request-to-Send) act~pin low) if
it was not already. It then waits until CTS (Clear-toSend) goes active (pin low) before starting the frame. If
the Preframe Sync bit in the Operating Mode register is
set, the transmitter prefaces two characters (16 transitions) before the opening flag. If the Flag Stream bit is
set in the Operating Mode register, the frame (including
Preframe Sync if selected) is started on a flag boundary.
Otherwise the frame starts on a character boundary.
At the end of the frame, the transmitter interrupts the
CPU (the interrupt results are discussed shortly) and

Each of the above transmit commands has an associated Abort command. The Abort Frame Transmit command causes the transmitter to send eight contiguous
ones (no zero bit insertion) immediately and then revert
to either idle or flag streaming based on the Flag
Stream bit. (The 8 Is as an Abort character is compatible with both SDLC and HDLC.)
For Loop Transmit, the Abort Loop Transmit command causes the transmitter to send one flag and then
revert to one bit delay. Loop protocol depends upon
FCS errors to detect aborted frames.

2-133

AP-36

The Abort Transmit Transparent simply causes the
transmitter to revert to either idles or flags as a function of the Flag Stream mode specified.

support intraframe'time fill, if the DMA controller or
CPU does not supply the data in time, the frame must
be aborted. The action taken by the transmitter on this
error is automatic. It aborts the frame just as if an
Abort command had been issued.

The Abort commands require no parameters, however,
they do generate an interrupt and return a result when
complete.

Clear-to-Send Error result is generated if CTS goes inactive during a frame transmission. The frame is aborted as above.

A summary of the Transmit commands is shown in
Figure 31. Figure 32 shows the various transmit interrupt result codes. As in the receiver operation, the
transmitter· generates interrupts based on either good
completion of an operation or an error condition. to
start the Result phase.

The Abort Complete result is self-explanatory. Please
note however that no Abort Complete interrupt is generated when an automatic abort occurs. The next command type consists of only one command.

The Early Transmit Interrupt result occurs after the
last data transfer to the 8273 if the Early Transmit Interrupt bit is set in the Operating Mode register. If the
8273 is commanded to transmit again within two character times, a single flag will separate the frames. (Buff- .
ered mode must be used for a single flag to separate the
frames. If non-Buffered mode is selected, three flags
will separate the frames.) If this time constraint is not
met, another interrupt is generated and multiple flags
or idles will separate the frames. The second interrupt
is the normal Frame Transmit Complete interrupt. The
Frame Transmit Complete result occurs at the closing
flag to signify a good completion.
The DMA Underrun result is analogous to the DMA
Overrun result in the receiver. Since SDLC does not

Reset Command
The Reset command provides a software reset function
for the 8273. It is a special case and does not utilize the
normal command interface. The reset facility is provided in the Test Mode register. The 8273 is reset by simply outputting a OlH followed by a DOH to the Test
Mode register. Writing the 01 followed by the 00 mimicks .the action required by the hardware reset. Since
the 8273 requires time to process the reset internally, at
least 10 cycles of the 4>CLK clock must occur between
the writing of the Oland the 00. The action taken is the
same as if a hardware reset is performed, namely:
1) The modem control outputs are forced high inactive.

Hex
Code

Parameters'

Results
TxllR

Transmit Frame
Abort

C8
CC

La, Lj, A, C
None

TIC
TIC

Loop Transmit
Abort

CA
CE

La, Lj, A, C
None

TIC
TIC

Transmit Transparent
Abort

CO
CD

La, Lj
None

TIC
TIC

Command

'NOTE:
A and C are passed as parameters in buffered mode only.

Figure 31. Transmitter Command Summary
RIC

Transmitter Interrupt
Result Code

07- 0 0
00001100
00001101
00001110
00001111
00010000

Early Tx Interrupt
Frame Tx Complete
DMA Underrun
Clear to Send Error
Abort Complete

TxStatus
after INT
Active
Idle or Flags
Abort
Abort
Idle or Flags

Figure 32. Transmitter Interrupt Result Codes

2-134

AP-36

2) The 8273 Status register is cleared.
3) Any commands in progress cease.
4) The 8273 enters an idle state until the next command
is issued.

If non-Buffered mode is used, the A, C, and I fields are
in memory. The software must examine the initial characters to find the extent of the address field. If Buffered
mode is used, the characters corresponding to the
SOLC A and C fields are transferred to the CPU as
interrupt results. Buffered mode assumes the two characters following the opening flag are to be transferred
as interrupt results regardless of content or meaning.
(The 8273 does not know whether it is being used in an
SOLC or an HOLC environment.) In SOLC, these
characters are necessarily the A and C field bytes, however in HOLC, their meaning may change 'depending
on the amount of extension used. The software must
recognize this and examine the transferred results as
possible address field extensions.

Modem Control Commands
The modem control ports were discussed earlier in the
Hardware section. The commands used to manipulate
these ports are shown in Figure 33. The Read Port A
and Read Port B commands are immediate. The bit
definition for the returned byte is shown in Figures 13
and 14. 00 not forget that the returned value represents
the logical condition of the pin, i.e., pin active (low) =
bit set.

Frames may still be selectively received as is needed for
secondary stations. The Selective Receive command is
still used. This command qualifies a frame reception on
the first byte following the opening flag matching either
of the AI or A2 match byte parameters. While this does
not allow qualification over the complete range of
HOLC addresses, it does perform a qualification on the
first address byte. The remaining address field bytes, if
any, are then examined via software to completely qualify the frame.

The Set and Reset Port B commands are similar to the
Initialization commands in that they use a mask parameter which defines the bits to be changed. Set Port
B utilizes a logical OR mask and Reset Port B uses a
logical ANO mask. Setting a bit makes the pin active
(low). Resetting the bit deactivates the pin (high).
To help clarify the numerous timing relationships that
occur and their consequences, Figures 34 and 35 are
provided as an illustration of several typical sequences.
It is suggested that the reader go over these diagrams
and re-read the appropriate part of the previous sections if necessary.

Once the extent of the address field is found, the following bytes form the control field. The same LSB test
used for the address field is applied to these bytes to
determine the control field extension, up to two bytes
maximum. The remaining frame bytes in memory represent the information field.

HDLC CONSIDERATIONS
The 8273 supports HOLC as well as SOLC. Let's discuss how the 8273 handles the three basic HOLC!
SOLC differences: extended addressing, extended control, and the 7 Is Abort character.
Recalling Figure 4a, HOLC supports an address fi~ld
of indefinite length. The actual amount of extension
used is determined by the least significant bit of the
characters immediately following the opening flag. If
the LSB is 0, more address field bytes follow. If the
LSB is I,this byte is the final address field byte. Software must be used to determine this extension.

Port
A Input

B Output

The Abort character difference is handled in the Operating Mode register. If the HOLC Abort Enable bi,~ is
set, the reception of seven contiguous ones by an active
receiver will generate an Abort Oetect interrupt rather
than eight ones. (Note that both the HOLC Abort Enable bit and the EOP Interrupt bit must not be set
simultaneously.)
Now let's move on to the SOLe loop configuration
discussion.

Command

Hex
Code

Parameter

Reg
Result

Read

22

None

Port Value

Read

23

None

Port Value

Set

A3

Set Mask

None

Reset

63

Reset Mask

None

Figure 33. Modem Control Command Summary

2-135

intJ

AP-36

CARRIER DETECT

-...-J

\~-

RxD

Rx COMMAND

t

OR~~~:~~~~~~~i~ ___________________________________________________~~_A
____~I_c____~t~ll_______________________

t

t

NON·BUFFERED
FRAME
POSSIBLE
IN~~~~~~~~ __________________________________________M
___
O_DE______________~~C~O~M~P~LE~T~E~___~ID~L~E~I~NT

611001-25
A. Error·Free Frame Reception

CARRIER DETECT

-...-J

\\\\\\\\\\\\

RxO

Rx COMMAND t

IN~~~~~~~~ _______________________t;,. . F. ;,A.;.~; .L~;.,R.; E;,. . I;,. . . .:.-. . ; ,. . . .:.-. . ;__..:.......;__..:...____. :. . .;,F. :.A; .:~:.:~. :.R: E_____
611001-26
B. Carrier Detect Failure During Frame Reception

Figure 34. Sample Receiver Timing Diagrams

LOOP CONFIGURATION
Aside from use in the normal data link applications, the
8273 is extremely attractive in loop configuration due
to the special frame-level loop commands and the Digital Phase Locked Loop. Toward this end, this section
details the hardware and software considerations when
using the 8273 in a loop application.
The loop configuration offers a simple, low-cost solution for systems with multiple stations within a small
physical location, i.e., retail stores and banks. There are
two primary reasons to consider a loop configuration.
The interconnect cost is lower for a loop over a multipoint configuration since only one twisted pair or fiber
optic cable is ,used. (The loop configuration does not
support the passing of distinct clock signals from station to station.) In addition, loop stations do not need
the intelligence of a multi-point station since the loop

protocol is simpler. The most difficult aspects of loop
station design are clock recovery and implementation
of one bit delay (both are handled neatly by the 8273).
Figure 36 illustrates a typical loop configuration with
one controller and two down-loop secondaries. Each
station must derive its own data timing from the received data stream. Recalling our earlier discussion of
the DPLL, notice that TxC and RxC clocks are provided by the DPLL output. The only clock required in the
secondaries is a simple, non-synchronized clock at 32
times the desired baud rate. The controller requires
both 32 X and 1 X clocks. (The 1 X is usually implemented by dividing the 32 X clock with a 5-bit divider.
However, there is no synchronism requirement between
these clocks so any convenient implementation may be
used.)

2-136

inter

AP-36

Tx COMMAND!

TxD

RTS~

L
L

C T S - - - - -.....

1A

1C

111

112

OR~~~:~~~~~~~~~------------I---I---I----------------------------------------------------

1

NON·BUFFERED
MODE

IN~~;=~~~~----------------------------------------------------------~FR-A-M-E-C~O~M~P~L~E~TE
611001-27
A. Error-Free Frame Transmission

2ND FRAME
I I I I I

1ST FRAME
Tx COMMAND

1

I I I I I

TxD

RTS~
CTS~
hARLYT.

IN~~;~~~;~----------------------------~--------------------------------------611001-28
B. Diagram Showing Tx Command Queing and Early Tx Interrupt
(Single flag between frames) Buffered Mode is Assumed

T. COMMAND

I

L
CTS------......

1 CTS

IN~~;=~~;~----------------------------------------~O~R~A~~~:~R~O~R--------------ERROR
INTERRUPT
611001-29
C. CTS Failure (or other error) During Transmission

Figure 35_ Sample Transmitter Timing Diagrams

2-137

inter

AP-36

1.LOOP
OSCILLATOR
OR
DIVIDER

If the controller wants to poll the secondaries, it transmits a polling frame followed by all Is (no zero bit
insertion). The final zero of the closing frame plus the
first seven is form an BOP. While repeating, the secondaries monitor their incoming line for an BOP. When
an EOP is received, the secondary checks if it has any
response for the controller. If not, it simply continues
repeating. If the secondary has a response, it changes
. the seventh BOP one into a zero (the one bit time of
delay allows time for this) and repeats it, forming a flag
for the down-loop stations. After this flag is transmitted, the secondary terminates its repeater function and
inserts its response frame (with multiple preceding flags
if necessary). After the closing flag of the response, the
secondary re-enters its repeater function, repeating the
up-loop controller Is. Notice that the final zero of the
response's closing flag plus the repeated I s from the
controller form a new BOP for the next down-loop secondary. This new BOP allows the next secondary to
insert a response if it desires. This gives each secondary
a chance to respond.

8273
LOOP
CONTROLLER
TxD

RxD

RKC

8273

TKC

LOOP
TxD
TERMINAL

1--+--+--+1 RKD

TKC

RxC

TxD

8273
LOOP
TERMINAL

611001-30

Figure 36. SOLe Loop Appli,catlon

A quick review of loop protocol is appropriate. All
communication on the loop is controlled by the loop
controller. When the controller wishes to allow the secondaries to transmit, it sends a polling frame (the control field contains a poll code) followed by an EOP
(End-of-Poll) character. The secondaries use the EOP
'character to capture the loop and insert a response
frame as will be discussed shortly.
The secondaries normally operate in the repeater mode,
retransmitting received data with one bit time of delay.
All received frames are repeated. The secondary uses
the one bit time of delay to capture the loop.
When the loop is idle (no frames), the controller transmits continuous flag characters. This keeps transitions
on the loop for the sake of down-loop phase locked
loops. When the controller has a non-polling frame to
transmit, it simply transmits the frame and continues to
send flags. The non-polling frame is then repeated
around the loop and the controller receives it to signify
a complete traversal of the loop: At the particular secondary addressed by the frame, the data is transferred
to memory while being repeated. Other secondaries
simply repeat it.

Back at the controller, after the polling frame has been
transmitted and the continuous Is started, the controller waits until it receives an BOP. Receiving an BOP
signifies to the controller that the original frame has
propagated around the loop followed by any responses
inserted by the secondaries. At this point, the controller
may either send flags to idle the loop or transmit the
next frame. Let's assume that the loop is implemented
completely with the 8273s and describe the command
flows for a typical controller and secondary.
The loop controller is initialized with commands which
specify that the NRZI, Preframe Sync, Flag Stream,
and BOP Interrupt modes are set. Thus, the controller '
encodes and decodes all data using NRZI format. Preframe Sync mode specifies that all transmitted frames
be prefaced with 16 line transitions. This ensures that
the minimum of 12 transitions needed by the DPLL to
lock after an all I s line has occurred by the time the
secondary sees ,a frame's opening flag. Setting the Flag
~tream mode starts the transmitter sending flags which
Idles the loop. And the BOP Interrupt mode specifies
that the controller processor will be interrupted whenever the active receiver sees an BOP, indicating the
completion of a poll cycle.
When ~he. controller wishes to transmit a non-polling
frame, It simply executes a Frame Transmit command.
Since the Flag Stream mode is set, no BOP is formed
after the closing flag. WheIi a polling frame is to be
transmitted, a General Receive command is executed
firs~. Thi~ enables the receiver and allows reception of
all mcommg frames; namely, the original polling frame
plus any response frames inserted by the secondaries.
After the General Receive command, the frame is
transmitted with a Frame Transmit command. When
the frame is complete, a transmitter interrupt is gener-

2-138

AP-36

ated. The loop controller processor uses this interrupt
to reset Flag Stream mode. This causes the transmitter
to start sending all Is. An EOP is formed by the last
flag and the first 7 Is. This completes the loop controller transmit sequence.
At any time following the start of the polling frame
transmission the loop controller receiver will start receiving frames. (The exact time difference depends, of
course, on the number of down-loop secondaries due to
each inserting one bit time of delay.) The first received
frame is simply the original polling frame. However,
any additional frames are those inserted by the secondaries. The loop controller processor knows all frames
have been received when it sees an EOP Interrupt. This
interrupt is generated by the 8273 since the EOP Interrupt mode was set during initialization. At this point,
the transmitter may be commanded either to enter Flag
Stream mode, idling the loop, or to transmit the next
frame. A flowchart of this sequence is shown in Figure
37.

o

The secondaries are initialized with the NRZI and One
Bit Delay modes set. This puts the 8273 into the repeater mode with the transmitter repeating the received
data with one bit time of delay. Since a loop station
cannot transmit until it sees an EOP character, any
transmit command is queued until an EOP is received.
Thus whenever the secondary wishes to transmit a response, a Loop Transmit command is issued. The 8273
then waits until it receives an EOP. At this point, the
receiver changes the EOP into a flag, repeats it, resets
One Bit Delay mode stopping the repeater function,
and sets the transmitter into Flag Stream mode. This
captures the loop. The transmitter now inserts its message. At the closing flag, Flag Stream mode is reset, and
One Bit Delay mode is set, returning the 8273 to repeater function and forming an EOP for the next downloop station. These actions happen automatically after a
Loop Transmit command is issued.
When the secondary wants its receiver enabled, a Selective Loop Receive command is issued. The receiver
then looks for a frame having a match in the Address
field. Once such a frame is received, repeated, and
transferred to memory, the secondary's processor is interrupted with the appropriate Match interrupt result
and the 8273 continues with the repeater function until
an EOP is received, at which point the loop is captured
as above. The processor should use the interrupt to determine if it has a message for the controller. If it does,
it simply issues a Loop Transmit command and things
progress as above. If the processor has no message, the
software must reset the Flag Stream mode bit in the
Operating Mode register. This will inhibit the 8273
from capturing the loop at the EOP. (The match frame
and the EOP may be separated in time by several
frames depending on how many up-loop stations inserted messages of their own.) If the timing is such that the
receiver has already captured the loop when the Flag
Stream mode bit is reset, the mode is exited on a flag
boundary and the frame just appears to have extra closing flags before the EOP. Notice that the 8273 handles
the queuing of the transmit commands and the setting
and resetting of the mode bits automatically. Figure 38
illustrates the major points of the secondary command
sequence.

DEN~TES COMMAND

<=:) DENOTES INTERRUPT CODE
611001~31

Figure 37. Loop Controller Flowchart

2-139

AP-36

It is hopefully evident from the abC?ve discussion that
the 8273 offers a very simple and easy to implement
solution for designing loop stations whether they are
controllers or down-loop secondaries.

INITIALIZE SET NAZI. ONE
BIT DELAV MODES

R•• t------~------UP.LOOPDATA
8273

h·I----+---r'\

DOWN·LOOP DATA

PORT I---+--~>o-J

611001-33

Figure 39. Loop Interface

APPLICATION EXAMPLE

o

DENOTES COMMANDS

c : ) DENOTES INTERRUPT CODES
611001-32

Figure 38. Loop Secondary Flowchart
When an off-line secondary wishes to come on-line, ,it
must do so in a manner which does not disturb data on
the loop. Figure 39 shows a typical hardware interface.
The line labeled Port could be one of the 8273 Port B
outputs and is assumed to be high (1) initially. Thus uploop data is simply passed down-loop with no delay;
however, the receiver may still monitor data on the
loop. To come on-line, the secondary is initialized with
only the EOP Interrupt mode set. The up-loop data is
then monitored until an EOP occurs. At this point, the
secondary's CPU is interrupted with an EOP interrupt.
This signals the CPU to set One Bit Delay mode in the
8273 and then to set Port low (active). These actions
switch the secondary's one bit delay into the loop. Since
after the EOP only. Is are traversing the loop, no loop
disturbance occurs. The secondary now waits for the
next EOP, captures the loop, and inserts a "new online" message. This signals the controller that a new
secondary exists and must be acknowledged. After the
secondary receives its acknowledgement, the normal
commarid flow is used.

This section describes the hardware and software of the
8273/8085 system used to verify the 8273 implementation ofSDLC on an actual IBM SDLC Link. This IBM
link was gratefully volunteered by Raytheon Data Systems in Norwood, Mass. and I wish to thank them for
their generous cooperation. The IBM system consisted
of a 370 Mainframe, a 3705 COmmunications Processor, and a 3271 Terminal Controller. A Comlink II
Modem supplied the modem interface and all communications took place at 4800 baud. In addition to observing correct responses, a Spectron D60 I B Datascope
was used to verify the data exchanges. A block diagram
of the system is shown in Figure 40. The actual verification was accomplished by the 8273 system receiving
and responding to polls from the 3705. This method
. was used on both point-to-point and multi-point configurations. No attempt was made to implement any higher protocol software over that of the poll and poll
responses since such software would not affect the verification of the 8273 implementation. As testimony to
the ease of use of the 8273, the system worked on the
first try.

370

MAINFRAME

3705
COMM.
PROCESSOR

611001-34

Figure 40. Raytheon Block Diagram
An SDK-85 (System Design Kit) was used as the core
8085 system. This system provides up to 4K bytes of
ROM/EPROM, 512 bytes of RAM, 76 I/O pins, plus

2-140

AP-36

two timers as provided in two 8755 Combination
EPROM/IIO devices and two 8155 Combination
RAM/IIO/Timer devices. In addition, 5 interrupt inputs are supplied on the 8085. The address, data, and
control buses are buffered by the 8212 and 8216 latches
and bidirectional bus drivers. Although it was not used
in this application, an 8279 Display Driver/Keyboard
Encoder is included to interface the on-board display
and keyboard. A block diagram of the SDK-85 is
shown in Figure 41. The 8273 and associated circuitry
was constructed on the ample wire-wrap area provided
for the user.
The example 8237/8085 system is interrupt-driven and
uses DMA for all data transfers supervised by an 8257
DMA Controller. A 2400 baud asynchronous line, implemented with an 8251A USART, provides communication between the software and the user. 8253 Programmable Interval Timer is used to supply the' baud
rate clocks for the 8251A and 8273. (The 8273 baud
rate clocks were used only during initial system debug.
In actual operation, the modem supplied these clocks
via the RS-232 interface.) Two 2142 1K x 4 RAMs
provided 512 bytes of transmitter and 512 bytes of receiver buffer memory. (Command and result buffers,

2-141

plus miscellaneous variables are stored in the 8155s.)The RS-232 interface utilized MC1488 and MC1489
RS-232 drivers and receivers. The schematic of the system is shown in Figure 42.
One detail to note is the DMA and interrupt structure
of the transmit and receive channels. In both cases, the
receiver is always given the higher priority (8257 DMA
channel 0 has priority over the remaining channels and
the 8085 RST 7.5 interrupt input has priority over the
RST 6.5 input.) Although the choice is arbitrary, this
technique minimizes the chance that received data
could be lost due to other processor or DMA commitments.
Also note that only one 8205 Decoder is used for both
peripheral and. memory Chip Select. This was done to
eliminate separate memory and 110 decoders since it
was known beforehand that neither address space
would be completely filled.
The 4 MHz crystal and 8224 Clock Generator were
used only to verify that the 8273 operates correctly at
that maximum spec speed. In a normal system, the
3.072 MHz clock from the 8085 would be sufficient.
(This fact was verified during initial checkout.)

ADDRESS
DECODER

CPU

ROMIIO (1355)
EPROMtlO (1755)

ADDRESS
FIELD

I

I

I

I
I
I
I
I

I
I
I
I
I
I

I
I
I

I

I

"11

IFi
c

I

I

I
I
I

;

.......
~

en

....

I\)

~

:::I

ao

INTERRUPT
INPUTS

~
1085 .

:::I

III

n

~

o

:1

8205

1\

DATAl.
ADDRESS

BUS

[

U

iii

3

SINGLE
STEP

GO

I

I

I

C

E

F

• •

A

B

•

•

H

0

L

SUBST
MEM

EXAM
5
1
REG SPH SPL PCH PCL

NEXT

EXEC

0

1

2

3
!

ir=>

74lS15&
DATA

BUS

"It

I
8219

.J
L

J

I
I
I

l>

I

(0)
0)

I
I
I

:'

I

I

I

I

I

I

I
I

I

I

I

I

I
I

I

I
I

I
I

I

I

I

I

I

I

I

:

I

'U
I

I

I

I

ji;

VEeT
INTR

,
I

co

~

I
I

1155

.J

;>

RESET

10 LINES

I
I

8355

L

!!!.

0'

1755

,~,.

L

~mt, ~n~-,

D1

en

~.

~
[V

I

,0

,,, ,

,::,.

SDK-as KEYBOARD LAYOUT

I
I

I

DATA
FIELD

~""-"
C'.CI.,=,.,:::,.,

I

I

I

I

I

I
I

I
I

ADDRESSI

"v

r::')
..J] .
L __

r--,I

"v IL __
0212

BUS

I
I
I

:

CONTROL

I

I

I

8US

rL -___
- -.J

l

FOR BUS-EXPANSION

KEYBOARD DISPLAY

RAMtlOJCOUNTER

I

.J

ADDRESS
8US

'

r---,

"/ ~L

K:4

.J

3 .. 121&

__.

15

CONTROL
BUS

I
OPTIONAL A PLACE HAS BEEN PROVIDED ON THE PC BOARD FOR THE DEVICE BUT THE

DEV'CE IS NOT 'NCLUDED,

611001-35

l

m
A'

3

ReI--

B'

5

A2

6

82

01~

021'

745257

03

WRI-_j'---'-'-I

I'

0,1"

MEMR

, "OR

I I

-

MEMW

, I

f

III

;ow

I

I

I

T

I

I I

, I
-t-

L2.~_~
15

"T1

.

40"
c

01-00

CD
01>0

I

::::

DATA BUS

I

X

,.

!"
CO

I\)
-.j

ROT

SDK·8S

BUS

Co)
~ .....
C/)

.::.

'"

c

"=
U1

..

HLOA

10

f-I---------t--j

DACio
DRat

HRO

25
18

DACKI

llHLDA 8257

H-----"-l

A0C-

C/)

'<
(II

Dl-DO

RESET~

CD

- ,-1'1
~

3

Rm 5

\--. IF
611001-45

2-148

inter

AP-36

A S~-P OR RR(9)-P IS RECEI'IED. A RESPONSE FRl1ItE OF NSA-F
56
OR RR(9J-F IS TRflHSAITTED. OTHER C!XttANI)S OPERATE HIIUR.I. Y.
57
62
63 ; .................**••***..........*••••*** .....................................

64.
9999
9999
9991
9991
9992
0093
9992
9929
9994
eee8
0091
9002

9999

999C
9990
999£

eeec
9936
9006
2917
2918

65
66
67
68
';9
78
.1
72
73
74
75
76
77
78
79
se
81
82
B3
84
85
86
87
99
89
99
91
92
93

; 9273 EQUATES
;
geIi
STAm EIlU
C1J11173 EQU
99H
PARP173 EOU
91H
EQU
~ESL73
91H
TXIP7J EQU
92H
RXIR73 EQU
93H
TEsm EIlU
92H
EQU
CPBF
2l'tH
IXINT EIlU
94/1
RXINT EIlU
99H
81H .
TXIRA EQU
RXIRA EIlU
92H
;
; 825, EQUATES
;
troOE53 EIlU
98N
CNT953 EIlU
9CH
CNTl53 EIlU
90H
CNT253 EIlU
9EH
COOR
EIlU
aeacH
!!OCNre EIlU
36H
/IDCNT2 EIlU
006H
LKBRl EIlU
2917H
LKBI12 EIlU
291811
;
; BAUD RATE TAIlLE.
;

94;

96;
97 ;

98 ;
99;

99A8
00A9
8SAl

99A2
00A3
98A8
8289

seee
9862
41FF
0063
8961
81FF

; 82SJ PIOO£ ~ REGISTER
; crulTER 9 REGISTER
; CIlUNTER 1 REGISTER
; COUNTER 2 REGISTER
; CONSOlE BAUD RATE (2499)
; PIOOE FOR CWNTER 9
; tIOOE FOR COUNTER 2
; B273 BAUD RATE LSB AOR
; 8273 BAUD RATE ItS8 AOR
BAUD RATE

•••***...
9600
4999
2499
1299
699
399

95 ;

199 ;
181 ;
192 ; 8257 EIlUATES
193 ;
194 "ODES7 EIlU
195 CHBADR [aU
196 CHeTe EIlU
187 CH1ADR EQU
198 CHiTC EQU
199 STAT57 EIlU
119 RXElUF EIlU
111 TXBUF EIlU
112 CROllA EIlU
113 RXTC
EIlU
114 ENDM EIlU
115 OTDIIA EIlU
116 TXIe
EIlU
117 ;

; STATUS REGISTER
; COI'MND REGISTER
; PARAI£TER REGISTER
;RESlJI..T REGISTER
; IX INTERRUPT RESllT REGISTER
; RX INTERRUPT RESllT REGISTER
; TEST ItODE REGISTER
; PARlmETER BUFFER R.lL BIT
; TX INTERRUPT BIT IN STATUS REGISTER
; RX INT~T BIT [N STATUS REGISTER
• IX INT RESULT AYAIUIlLE BIT
; RX INT RESULT AYAILABLE BIT

9A8H
9A8H
8A1H
9A2H
BA,H
9A8H
8298H

00B9H
62H
41FFH
63H
61H
81FFH

_. .....

LKBRl

LKBI12

2E

99
00
99
91
92
95

sc

89
72
ES
C9

; 8257 ItOOE PORT
; CHe (RX) AOR REGISTER
; CH8 TERI1INAL COUNT REGISTER
; CHi (TX) ADR REGISTER
; CHi TER"INAL COUNT ~EG1STER
; STATUS REGISTER
; RX BUFFER START ADDRESS
; r. BlfFER START ADDRESS
•D[SABLE RX DIll CIRf£L TX STILL ON
; TERI1INAL COUNT AND t100E FOR RX CHAII£L
£HABLE 80TH IX I'll) RX CIflNNELS-EXT. IIR. IX SlW
DISABLE TX DIll CIiH£L RX STILL ON
~J1INAL COUNT AND "DOE FOR IX CHIH£I.
611001-46

2-149

AP-36

90S9
9889
8888

8888
eec£
8827
9892

961F
85F8
975E
959B
95EB
96C7

29C9
9893

eees
2909
2829
090D
009A
2804
28CE
2818
2813

2809
9093
9011
9073

9011
2815
2816
2827

118 ; 8251A EQUATES
119 ;
129-CNTL51 EIlU
89H
; CONTROL lolOO) REGISTER
121 STAT51 EIlU
89M
; STATUS REGISTER
122 0051 EIlU
8SH
; lli DATA REGISTER
12] RXD51
EIlU
; RX DATA REGISTER
8SH
124 ~DE51 EQU
BCEH
; ItOOE 16X. 2 STOP. III PARITY
; COIMlD. ElflBl.E TX&RX
125 0051 EQU
27H
126 ROY
EIlU
82H
; RXRDY BIT
127 •
128 ; ~ITOR SUBROUTINE EQUATES
129 ;
; GET CHR FRM KEYBOARD. ASCII IN CH
139 GETCH EQU
061FH
131 ECHG' EQU
85FSH
; ECHG CHR TO DISPLAY
; CHECK IF VALID DIGIT. C/lRRY SET IF VALID
132 YIUlG EIlU
975EH
; COOYERTS ASCII TO I£X
133 CNYBN EQU
95BBH
134 CRLF
EQU
05ESH
; DISPLAY CR. t£Ia LF TOO
; CltWERT BYTE TO 2 ASCII CHR All) DISPLAY
135 NI«lUT EQU
96C7H
136;
137 ; "ISC EIlUATES
138 ;
; 5TACI: START
139 STKSRT EQU
2OC9H
; CNTL-C EIlUIYALENT
149 CNTLC EQU
03H
14110ITIR EQU
9119SH
;'OUTOR
142 CKDBUF EIlU
; START Of COIfIlNI) BUFFER
2909H
; POLL KOOE SPECIAL lli COIIIM) BUFFER
143 CKDBFl EIlU
2820H
144 CR
EQU
;ASCII CR
9DH
EQU
;ASCII LF
145 LF
0AH
2004H
; RST7. 5 JUKP ADDRESS
146 RST75 EQU
147 RST65 EQU
; RST6, 5 JUKP ADDRESS
28CEH
; RESULT BUFFER LIRl POINTER STIRAGE
148 L~ EIlU
291911
; RESULT BUFFER COOSOl.E POINTER STIRAGE
149 CIRlR EQU
2913H
; RESULT BUFFER START - 255 BYTES
1511 RESSUF EIlU
280IIH
; SNRK-I' CONTROL CODE
151 ~P EIlU
93H
; RR(91-1' ClJfIROl. CODE
152 AROP
EQU
11H
153 NSAF
EQU
73H
; NSA-f CONTROl. CODE
; RR(9)-f ctlNTROL CODE
154 RR0F
EQU
11H
EQU
; PRI1PT STORAGE
155 PRItPT
2815H
; POLL KODE SELECTI~ INDICATOR
156 PIl.IN EQU
2016H
157 DEl10DE EQU
2827H
; DOO "ODE INDICATOR
161 ;
,162 ; ........***** ...........******............................................
163 ;
164 ; RAK STORAGE DEl'INITI~S:
165 ;
LOC
DEI'
166 ;
ClJII1AII) BUFFER
167 ;
2BB0-200F
168 ;
2819-2911
RESULT BUFFER LOAD POINTER
169 ;
2813-2814
RESULT 8UFFER C~E POINTER
179 ;
2815
PROKPT CIRlIICTER STORfliE
171 ;
2816
POLL I'KIIlE INDICATIR
8AIJ) RATE LS8 FIR 5ELF-TEST
172 ;
2017
8fIU) RATE KS8 FIR SELF-TEST
173 ;
2818
177 ;
SPARE
2819
179 ;
RESPONSE COKKAND BUFFER FOR POLL ItOOE
2829-2826
188 ;
2809-28FF
RESULT BUFFER
181 ;

182

i ...........................................................................

611001-47

2-150

intJ

AP·36

9800
e898
9Se3
0005
eB07
009A
esee
BOOF
9S11
9814
0017
9819
8818
0010
OO1F
0021
9824
0826
9829
9B2C
982F

31C828
3E36
039B
3Al;'28
D39C
3A1820
039C
CDIA98
C03588
3E91
0392
3E89
0392
3E2D
321529
lE99
321629
322729
21A30C
C0929C

9832
0835
98:18
883A
9838
983C
B830
B83E
0041
0044
9846
9847
9848
0849
984A
984C
9940

210429
918eec
36C3
23
71
2:1
79
21CE28
91CEOC
36(3
23
71
23
79
3E1S
39
FB

994E 218928
8951 221329
9854 221929

183
184
185
166
18;'
18S
169
198
191
192
193
194
195
196
197
198
199

PROGRAII STAilT
INITIALIZE 8253, 825;', 8251A, AND RESET 8273.
,ALSO SET NOFMAL liODE. AND PRINT SIGNOIl "ESSAGE
;
ORG
8\l0H

START. LXI
SPoSTKSRT
; INITIALIZE SP
A, MOCNTe
; 8253 MODE SET
t1II1
; 8253 HODE PORT
OUT
I'IODES3
,GET 8273 BAlI) RATE L5B
LDA
LKBR1
,USING COUNTER 8 AS BAlI) RATE GEN
OUT
CNT953
; GET 8273 8UAO RATE ~
LOA
LKB~2
;COUNTER e
OUT
CNT953
; INITIALIZE 8257 RX D~ CIM£L
CALL
RXDMA
; INITIALIZE 8257 IX DIll CHfNlEI.
CALL
Txr.m
A,01J1
; OUTPUT 1 FOLLOIED BY A 9
299
t1II1
; TO TEST I!OOE REGISTER
281
OUT
TEsm
A,9aH
282
; TO RESET Tl£ 8273
"VI
283
OUT
TEsm
294
,NORMAL HaDE PRIJ'PT CHR
MYI
A, '-'
STA
PRMPT
; PUT IN STOI(OOE
285
A,99H
286
HVI
, TX POLL RESPONSE INDICATOR
; e MEANS NO SPECIAL TX
297
STA
POLIN
,CLEAR DEl10 t10DE
STA
DEMODE
m
H, SIGNON
; SIGNON ~SSAGE AOR
212
LXI
TYMSG
; DISPLAY SIGNOH
213
CAlL
214;
215 ; MONITOR USES JUIIPS IN RAIl TO DIRECT INTERRUPTS
216;
217
LXI
H, RST75
; RST7. 5 JUIf> LOCATION USED BY HONIT1~
; ADDRESS OF RX INT ROUTII£
218
LXI
8, RXI
H,9elH
; LOAD 'JMP' OPCDDE
HVI
219
; INC POINTER
INX
229
H
H,C
; LOAD RXI LS8
221
HOY
; INC POINTER
222
INX
H
H,8
223
HOY
; LOAD RXI "58
; RST6. 5 JUMP LOCATION USED BY MONITOR
224
LXI
Ii. RST6S
LXI
8, TXI
; ADDRESS OF TX INT ROUTINE
22S
; LOAD 'JIIP' OPCODE
226
",OC3H
"VI
,; INC POINTER
227
INX
H
M,C
; LOAD IXI L58
228
HOV
; INC POINTER
229
INX
H
H, B
; LOAD TXI ~
239
HOV
A,1SH
231
MVI
; GET SET TO RESET INTERRUPTS
; RESET' INTERRUPTS
232
51"
; ENABLE INTERRUPTS
233
EI
234 ;
235 ; INITIALIZE BUFFER POINTER
236,
237;
; SET RESIA.T BlJ'FER POINTERS
238
LXI
li.RESBUF
; RESULT CONSOLE POINTER
SHLO
CNAOR
239
; RESULT LOll) POINTER
240
SHLO
l.DIIOR
241;
242 ; HAIN PROGRAII LOOP - CHECKS FOR CHANGE IN RESULT POINTERS, USIlRT STATUS,
243 ;
OR POLL STATUS

611001-48

2-151

intJ

AP-36

8857 COEB95
88SR 3A1529
9aso 4F
9S5E CDF885

9861 2A1329
0864 ro
99652A1929
8868 SO
8869 C2398A
986C 0089
986£ E682
9879 C2roS8
8873 3A1629
8876 A7
88i7 C24C99
987ft C36198

Il87D CD1F96
9889 CDF885

9983
9884
9886
9899
9988
Il88E
9899
9893
9895

79
FE52
CAAF98
FE53
CAD798
FE47
CAFF98
FE54
CAIlE99
Il89.8 FE41
989A CA2299
989D FE5A

989F CR3199
98A2 FE93

98A4 CR9989
98A7 0E3F
98A9 CDF895
98RC C35798

98AF CD1F96
9892 CDF985
9985 79
11886 FE4F
9888 CA5D99
Il88B FE53
988D CA6799
1l8C9 FE44
98C2 CR7199
1l8C5 FE59
98C7 CAD899
88CA FE52
98CC CA98e8
98CF FE42
1l8D1 CR7989

244 ;
245 CI1>REC: CAlL
246
LDA
247
ftOII
249
CAlL
249 LOOPIT: LHLD
~y
259
251
LHlD
252·
CPIP
253
JNZ
IN
259
ANI .
268
261
JN2
262
LDA
263
ANA

CRLF
PRPlPT
C,R
ECIfl
CNADR
1l.L
LDADR
L
DISPY
STAT51
ROY
GETCItIl
POLIN
A
TXPtl.
LOOPIT

264
JNZ
265
JIF
266 ;
267 ;
268 ; COIIIRlD RECOGNIZER ROOTiNE
269 ;
279 ;
GETCH
271 GETell>: CAlL
272
CAlL
Eoo
273
HOY
II.C
274
CPI
'R'
275
JZ
RDIfI
276
CPI
'5"
277
JZ
50IIl
278
CPI
'6'
279
JZ
GOWN
CPI
'T'
289
281
TOWN
JZ
282
CPI
'A'
293
JZ
ADIf4
CPI
284
'Z'
295
JZ
CIIOOE
CNTU;
299
CPI
291
JZ
~OR
I ?'
C,
292 ILLEG: !WI
293
CRI.L
ECHO
294
JPIP
CItOREC
295
296 ROlIN: CALL
GETCH
297
CALL
Eoo
A,C
HOY
299
CPI
'0'
299
398
ROCItD
JZ
'5'
381
CPI
392
JZ
RSCItl
383
CPI
'D'
JZ
RDCItl
384
'P'
395
CPI
JZ
RPCItl
396
387
CPI
'R'
START
JZ
398
CPI
389
'B'
319
JZ
RBCItIl

DISPLAY CR
GET etmNT PRtWT CIt!
"DYE TO C
DISPLAY IT
GET CONSOLE POINTER
SIM: POINTER LS8
GET LOll) POINTER
SIIIE LS8?
NI1 RatTS t£EI) DISPLAYING
YES, CI£CK KEVBOARI)
CIt! RECEI'IED?
IIU5T BE ctI! 50 GO GET IT
GET POLL II)I)E STATUS
15 IT 9?
NO, THEN Pru. 0CClIU!Ep
YES, TRY AGAIN

GET CIt!
ECHO IT
5ET\.IP FOR CIJIPfI89
JIf'
CIlIIII2
390 ,
391 ,
392 ,
393 ; COt1llAll) IHPlEI1ENTlI«i ROUTINES

,ClEAR PCtL' IN>ICAT!I!
, INDICAT!I! RlR
; SETUP STACK F!I! COIRI) OUTPUT
; PUT RrnJRN TO CI1DREC ON sTAcK
; GET • OF PARfl£TERS REfI)Y
,POINT TO SPECIAl 8U'FER
,JlIf' TO C!JIIIfIIl OUTPUTER

394 ,

8950
995F
8961
8964

8691
0E51
CDE50A
C35708

8967
8969
9968
896E

8681
eE68
CDE59A
C35708

8971
9973
8975
9978

8688
SEC5
CDE59f1
C35708

9978
897D
997F
9982

8681
8E64
CDES8A
Cl5788

8905
9987
9989
998C

8691 ,
CDE58A
C35708

99BF
9991
9993
9996

8684
eEC2
CDE59f1
C35788

eEA4

39'5 ,
396 ,RO - RESET OPERATING HOllE
397,
,I OF PARAI£TERS
398 ROCI1D: KYI
B,81H
; COIttfN)
KYI
C,51H
399
,GET PARAl£TERS AN> ISSUE COIfN)
488
CAlL
COM
,GET rEliT COIfN)
481
JI'f
CnoREe
4B2 ,
483 ,RS - RESET SERIAl 1/0 HOllE COIMH)
4jI4'
,. OF PARAI£TERS
B,81H
485 RSCKO: KYI
, mIlAN>
C,68H
486
ItIII
; GET PARAI1ETERS AN> ISSlE ClHIAN>
487
CAll
COIIt
; GET I£liT COIRI)
JItP
488
CI1DREC
489 ,
418 ; RO - RECElYER DISABlE COIIKAN>

411 ,
412 ROCItD: /lV1

;. OF PARll'lETERS
B,eeH
,COIIRI)
C,8C5H'
413
/lV1
• ,ISSIE CIJIft'VI)
414
CAll
COllI
,GET I£XT COIIIfN)
415
mP
CIIlREC
416 ;
417 ,RB - RESET ONE BIT DELAY cmRII)
418 ,
,. OF PARAl£TERS
419 RBCKD: ItIII
B,91H
,COllIN)
C,64H
429
HYI
; GET PARfI£TER AN> ISSlE COIRI)
421
CAlL
COM
,GET NEXT COIIIfN)
422
JIf'
CIIlREC
423;
424 ,58 - SET 0/£ BIT DElAY COIIIAN>
425 ,
,. OF PARfl£TERS
B,8tH
426 SBCItl: ItIII
,COllIN)
C,9fI4H
427
!WI
;GET PARllllETER AN> ISSlE ClIIIN)
4211
CAlL
COIIt
,GET rEliT COIIRI)
429
JIfP
CHDREC
438 ,
431 ,SL - SELECTlYE LOOP RECElYE COItIIRII)
432 ,
B,84H
• OF PARAI£IEREs
433 SLOO: ttYI
C!JMI)
C,9C2H
434
KYI
GET MR£TERS AN> ISSlE COIRI)
435
CAll
COIIt
GET NEXT COIIIfN)
436
JI1P
CKDREC
437 ;
438 ,Tl - TRANSltlT LOOP COIIIlND

2-154

611001-51

AP-36

11999
999C
B99E
99AB
89A3

B9A6
99A8
B9M
B9AO

21082B
8682
30CA
21B228
ClF689

BOB1
8E91
Cl\E5IlA
C35708

89119 BOB1
9982 B£AQ
9984 CDE5I!A

B9B7 C15798

B9BA
B9BC
\l9BE
B9C1

B684
BEC1
CDE59A
Cl57BS

B9C4
99C6
B!'C8
99C1!

B682
BECB
CDE59A
C357BB

B9CE B088

9908 SEC(
B902 CDE59A
\l905 C35798

\l908 B081

99M SE63
\l9OC CDE5Bfl
89DF C35788

\l9E2
89E4
89E6
89E9

9691
B£A3
CDE59A
Cl57B8

439
44B
441
442
443
444
445
446
447
44B
449
451!
451
452
453
454
455
456
457
458
459
46B
461
462

i

TLCI1!l'

LX[
MV[
MV[
LXI
JMP

H, CNI)BUF
B, B2H
M,BCAH
H, CMCBlIF+2
TFCMD1

,SET CIJI1IIfH) BLfFER PO[NTER
i LM> P~MTER ClUHER
,LI:m CIlIft1Nl) INTO BUFFER
i POINT AT AOR AN) CNTL POSITI(Jl5
i FINISI! OFF COMIIfH) IN TF ROJT[NE

i

'SO - SET OPERATING MODE COII'I1N)
i
B,81H
5OCI1!l' 11Y[
'IOFP~S
11Y[
iCIJI1ItAN)
C,91H
i (ET PRRfI1E1£R IN) [SSIE CCMH)
CflLL
COI'I1
.III'
i GET NEXT COIfIN)
CI1DR£C
i
,55 - SET SERIAL 1i0 COI9IINO
i
B,B1H
i I OF PARAIlETERS
S5CMC: MV[
, COI9tfM)
C,BA8H
MVI
i (ET PflRIIIETER IN) ISSIE COItfPH)
CALL
COIIIt
,GET NEXT COPIfAII)
JMP
CIt>REC
i
i 511 - SELECTIVE RECE[YE ClHfIII)
i
SRCI1D: MVI
B,Q4H
,I OF PPilAlETERS
; CMIANI)
~lVI
C,9C1H
463
; GET PARA1!ETER5 AND [SSIE COII'I1N)
CALL
CO/1I1
464
; (ET 1£01 COItiAND
465
JMP
CI1!lREC
466 i
467 i GR - (ENERAl. RECEIVE ClIV1RND
468 i
469 GRCHD: MV['
B,B2H
i NO PARAI£TER5
C,9CBH
479
MVI
' COI'I1fW)
, ISSIE COIti1fd)
471
CALL COI'I1
,GET NEXT com:INl)
472
JHP
CMOREC
473 i
474 i f'F - ABORT FRAME CMlANO
475 i
B,BIlH
476 f'FCHO: MYI
NO PARMTERS
CIIIffN)
C,BCCH
477
HVI
478
CALL
COllI
ISSlE COMI1AND
(ET NEXT COPIfAII)
479
JIll>
CMOREC
488 i
481 i RP - RESET PORT COIIHAND
482 i
B,B1H
I OF PARAIIETERS
483 RPCMD' MVI
ClmAN!)
C,63H
484
MVI
GET PARfIIETER IN) 1S5I.E COIfIN)
485
CALL
COHM
GET NEXT COIfIN)
JIf'
CMOREe
486
487 i
488 i SP - SET PORT COIWIlD
489 i
8,B1H
498 SPCMD' MVI
I OF PARfIItETERS
COMIN)
C, BA3H
491
MVI
GET P~I£TER IN) ISSIE COIfIN)
492
CAlL
COMII
GET HEX C!JtlRl)
493
JIf'
CHOREe
494 i
495 i TF - lRfINSIIlT FRfft CQI1ItH)
496 i
611001-52

2-155

inter

Ap·36

89EC 218828
89EF 8682
. 89F1 36C8
Il9F3 219228
89F67l!
89F7 R7
89F8 CA87l!A
89FB CDfIl8A
89FE 0AA788
9A81 23
8A82 95

TFC/tI):

499

see

see

8A84 C3f6119

5419
519
511 TBlfL:
512
513 TBlfL1:
514
515
516
517
518
519
528
521 EI«If(:
522
5Z3
524
525 llllfFL:
526
527
528
5Z9
538
531
532
533

8A8A 81081!8
BAIlI.l C5

8A8E
8A11
8A14
8A15
8A16
eA17
8A18
8A1B
9A1D
8A28
8A21
8fI24

8A25
8A28
8A29
8A2A
0A28
0AZO
0A38
0A31
8A32
0A33
0A36

0A39
0fI38
0A3E
0A3f

COA08fl
DA1B8A
77
23
C1
83
C3808A
FE80 ,
CA248A
C1
C3A788
C1
210128
71
23
7l!
86e4
21360A
C5
E3
C5
C3fII8A
C357118

1685
2A1320
E5
7E

8A49 E61F
8A42 FEBC
0A44 0A628A
0A4721C39C
0A4A C092tM:

0A4D E1
0A4E 7E
0A4F COC786

LXI
IWI
IWI
LXI

581 TFCIID1: "OY

5412
583
5e4
585
5e6
5e7

8fMl3 77

1!A87 21888IJ

-

497
498

534

535
536 TFRET:

fHI

JZ
CALL
JC
INX
OCR

II, CII)IIlf

B,82H
PL8C6If
II, CII)SUf+2
A,B
A
TllIJ'I.
PARIN
ILLEG
H

~

B
",A

JII>

TFOO1

LXI
LXI
PUSH
CALL
JC

II, TXBIF

~

INX
POP
INX

B,888I!H
B
PARIN
ENlCII<
PLA
H
B
B

JII>

TBUFL1

CPI
JZ
POP

CR
TBUFFL
B
ILLEG
B
II, CtIlelf+1
PLC
H
PLB
B,84/I
H, TFRET
8

J~

POP
LXI
~

INX
~

11'11
LXI

PUSH
XTHL
PUSH
JII>
JII>

8
C/OOJT
CIIIlREC

; SET COIftIII) BUFFER POINTER
; LIR> PAAAlETER COUNTER
; LM> CMfAN) INTO BUFFER
; POINT AT ADR fill) CNTL POSITIONS
; TEST PII!AI£TER truIT
; IS IT 8?
; YES, LIR> TX DATA BUFFER
;GETPARfI£TER
; ILLER CIIi RETIRED
; Ill: COIftIII) BUFFER POINTER
; DEC PARII'IETER CfUITER
; L(R) PfIiAIETER INTO COIftIII) BlFFER
; GET NEXT PARfI£TER
; Lim TX DATA BUFFER POINTER
; CLEfI! Be - BVTE CWITER
; SRYE Bm COLtITER
;GET DATA, ALIAS PARfI£TER
; IfIYBE END IF ILLER
; LOfIl DATA BVTE INTO B\fFER
; Ill: BUFFER POINTER
; RESTORE BVTE ClUtTER
; INC BVTE CWITER
; GET NEXT DATA
; REMNED ILLEGAL CIIR CR?
; YES, THEN TX IMFFER FIll
; RESTORE B TO SRYE STACK
; ILLEGAL CII!
; RESTORE BYTE CIUlTER
; POINT INTO CMfVI) BlFFER
; STORE BVTE truIT LS8
; Ill: POINTER
; STORE BVTE truIT IISB
; LOAD PfIRfI£TER COUNT INTO B
; GET RETlJ!N AIlR FOR THIS ROOTIHE
; PUSH IKE
; PUT RETLRN oN STACK
; PUSH IT SO C!tlOUT CAN USE IT
; ISSUE C09RI)
; GET NEXT ClIftN)

537 ;
538 ;
539 ; ROOTIHE TO DISPLAY RESULT IN RESILT BUFFER Nt£N LIR> fill) COOSOLE
548 ; POINTERS ARE DIFFERENT.
541 ;
542 ;
O,B5H
543DISPY' IWI
D IS RESUl.T ClUtTER
544
LHLO
CNAIlR
GET CONSOLE POINTER
545
PUSH
H
SRYE IT
546
IfOY
GET RESILT IC
A,"
547
ANI
1FH
L1"1T TO RESILT cooe
TEST IF AX OR TX 5ru!CE
548
CPI
9tH
CIIRRY, THEN AX 5ru!CE
549
JC
RXSIlRC
H, TXIIISG
55e TXSIlRC: LXI
TX INT IESSAGE
551
CALL
TYIISG
DISPLAY IT
552 DISPY2: POP
H
RESTORE CONSOLE POINTER
553 OISPY1: ~
GET RESULT
A,"
CONYERT
fill) DISPLAY
554
CALL
tIIOUT

I

611001-53

2-156

infef

AP-36

1lA52 BE28
0A54 CDF885
1lA57 2C
8fIS8 15
BAS9 C24E8R
IlA5C 221328
8A5F 05788

8R62
8R65
8R68
8R69
8R6Il
8A6D
8R6F
8R72
8R73
8R74
eA75
eA7,
eA7A

21888C
CD928C
E1
7E
CDC786
8E28
CDF885
2C
15
7A
FE84
CAA28A
FE83

8A7C CAA78R

eA7F
eA88
8A83
9AS6
8A89
8A8C
8A8I)

8R8E
9A8F
8A92
8A93
9A94
8A97
BA99
8A9C

A7
C2698A
221329
CDE885
219882
C1
78
B1
CA5798
7E
C5
COC786
9E29
CDF885
C1

8A9D 9B

8R9E 23
8A9F C3B08A

8AA2 4E
8AA3 C5

• 8AA4 C37F9A
eAR7 C1
eARS 46
8AA9 C5
8AfIII C37F8A

c~ I •
S55
iSP C~
"VI
S56
CALL
ECHO
i DISPLAY IT
557
INR
L
; INC BUFFER POINTER
,DEC RESU..T ClXJlTER
558
OCR
D
559
JN2
DI5P'I1
; NOT 001£
; UPOATE CONSOLE POINTER
569
SHLD
CNfIlR
561
JI!P
CIIOREC
; RETlRN TO LIU'
562;
563 i
564 ;RECElVER SOURCE - DISPLAY RESUl.TS RII) RECEYIE BlFFER COOENTS
565 i
566 ;
567 RXSORC: l.l(l
II, RXIHSG
i RX INT I£5SRGE fI)R
569
CRLL
TYIISG
i DISPLAY 1ES5&
; RESTORE ClJl5O..£ POINTER
569
H
POP
; RETRIEVE RESU..T FRO! BlFFER
578 RXS1: lillY
A,"
; CIIMRT AN) DISPLAY IT
571
NllXJT
CAlL
C, I I
; ASCII SP
572
~I
; DISPLAY IT
573
CALL
ECIIIl
,INC COOSOLE POINTER
574
I~
L
575
OCR
D
; DEC RESULT crulTER
A,D
576
MY
i GET SET TO TEST CIXJITER
;IS THE RESU..T R8?
577
CPI
84H
i YES, 00 SAYE IT
578
J2
R8PT
579
CPI
i 15 THE RESIU Ri?
8SH
; YES, 00 SAYE IT
588
JZ
RiPT
; TEST RESILT ClXJlTER
581 RXS2: ANA
R
; NOT 001£ YET, GET NEXT RESlLT
582
JNZ
RXS1
i D(l£, SO UPOATE CONSOLE POINTER
593
SHLD
CNADR
; DISPLAY CR
594
CALL
CRLF
II, RXBlF
585
LXI
i POINT AT RX SUFFER
P(P
586
B
i RETRIEYE RECEIVED COlfiT
; 15 CWIT 9?
597 RXS3: MY
ItB
588
ORA
C
; YES, 00 BACJ( TO lO(P
CIIlREC
599
JZ
iN(), GET ~
599
"OY
It"
591
PUSH
B
iSA\'E BC
; C!IlYERT AN) DISPLAY ~
592
CALL
NllXJT
C,' ,
;ASCII SP
593
"VI
;DISPLAY IT TO 5EPRRATE DATA
594
CALL
ECIIIl
P(P
; RESTORE BC
595
B
DCX
B
; DEC COCtIT
596
; INC POINTER
597
INX
H
J~
598
RX53
iGET NEXT ~
599
69B RaPT: lillY
i GET R9 FOR RESILT BlFFER
C,"
; SAYE IT
691
PUSH
B
; RETURN
692
JIf'
RXS2
693
684 RiPT: POP
iGET R9
695
i GET R1 FOR RESIl.T BlFFER
~
B,"
iSAYE IT
6e6
PUSH B
RXS2
697
mP
698
699
618
611 PARAPIETER INPUT - PARAl£TER RETURNED IN E REGISTER
612

611001-54

2-157

AP-36

IlAAO
BRAE
BABe
9AB3
eAll6
eAll7

CS
1681
C01F96
C[,FeeS
79
me
9A!I9 C2EeeR
9ABC C01Fe6
0A!IF CDFees
9AC2 CDSEe7
eACS 02E99A
eACS CDBBeS
9AC8 4F
Mec 7A
9ACD A7
eACE CADcaR
9ADl 15
0AD2 AF
9AD3 79
9A04 17
eAr,s 17
9AD6 17
9AD7 17
9AD8 5F
eAD9 GBCeR
9ADC 79
811){) 83
9A!lE Cl
9ADf C9
9AEa 79
eRE1 37
9AE2 Cl
eRE3 C9

9AE4 CF

8AES 219820
HB
8AE9
eREA
HB
HC
9AEF
9AF2
9AFS
1!AF6
1!AF7
9AF8
9AFB
9AFE

C5
71
7B
A7
CAF99A
CDAD9A
DAA798
23
as
77
C3EAeA
21ee20
C1

613 ;
614 PARIN:
61S
616
617
618
619
620
621 PARIN3,
622
623
624
625
626
627
628
629
63e
631
632

m

634
635
636
637
638
639
648
641
642
643
644
645
646
647
648
649
6S9
651
6S2
653
654
65S
656
657
6S9
659
669
661
662

PUSH
MVI
CALL
CALL
!WI'
CPI
JNZ
CALL
CALL
CALL
JNC
CALL
"OY
I10V
ANA

JZ
OCR
XRA
!WV
RAL
RAt.
RAL
RAt.
!WY
Jl1P

8
D,9tH
GETCH
ECHO
A,C
PARIN1
GETCH
ECHO

YALOO
PARIHi
CNVBN
C,A
A,D
A
PARIN2
D
A
ftC

E,A
PARIN3
A, C
PARIN2: "OV
ORA
E
POP
B
RET
A,C
PARIN1: IWV
STC
POP
RET
;
;
; JUItP HERE IF BUFFER FUlL
;
BUFFUL: DB
OCFH
,;
;
; CO/1I1fINI) DISPATCHER
;
;
H, CI'IDBUF
COItII: LXI
PUSH
B
MOIl
",C
A,B
C0I'I11: MOIl
Atf!
A
JZ
OOOUT
CALL
PARIN
663
664
JC
ILLEG
INX
H
66S
OCR
B
666
667
IIIJV
",A
668
JIf'
COIIPI1
669 OOOUT. LXI
ILCIIl!ltF
PDP
67B
B

; SRVE Be
; SET CHI! COltHER
;GET CIf1
,; ECHO IT
;PUT CIf1 IN A
; SP?
; NO, ILLEGAL TRY AGIHN '
; GET CHR ,OF PARfII£TER
; ECHO IT
; IS IT A VALID CHR?
,; NO, TRY AGAIN
,; CONYERT IT TO HEX
; SA'/E IT IN C
; GET CIf1 COUNTER
;IS Ii a7
; YES, DONE WITH THIS PAAMTER
;llEC CIf1 COUNTER
; CLEAR CARRY
; RECOVER 1ST CIf1
; ~OTATE LEFT 4 PLAC£S

; SAVE IT IN E
; GET NEXT CIf1
,; 2HC CIf1 IN A
; COMBINE BOTH CHRS
; RESTORE Be
; RETURN TO ClUING PROGRAII
; PUT ILLEGAL CIf1 IN A
; SET CARRY AS ILLEGfl.STATUS
; RESTORE Be
,; RETURN TO CALLII«l f'ROGRPI!

; EXIT TO MONITOR

; SET POINTER

;5RVE Be
; LOOD CClMI) INTO BlfFER
; CHECI< PARAI£TER COOHER
; IS IT al
; YES, GO IS5t£ C(JIfH)
; GET, PARAMETER
; ILLEGAL CHR RE1U1I£I)
; INC BUFFER POINTER
,DEC PARAItETER COUNTER
; PARAItETER TO BlfFER
; GET NEXT PARfIIETER
; REl'OINT POINTER
;RESTORE PARfl£TER CMT

611001-55

2-158

Ap·36

9AFF 0098
eBe187
8882 DAFF8A
BBI!5 7E
eee6 m8
eaea 78
Be89 A7
888A CB
BB88 23
BBeC 85
BeeD 0898
BBeF m8
BBi1 C2B0e8
BBi4 7E
8815 0391
BBi7 CJeSBB

BBiA
BBiC
881E
8821
BB22
8824
8825
8827
882A
8IJ2B
BB2D
BB2E
8838
8832
8834

3E62
D3AS
81Be82
79
D3Ae
78
D3A8
B1FF41
79
D3A!
78
D3Ai
3£63
DlAS
C9

671 COI1112:
672

673
674
675
676 P1Il1:

677
678
679
6ee
681 PAR2:

682
683
6B4
6B5
686
687
6BB
6B9
698
691
692
693

IN
RLC
JC

HOY
OUT

I10V
ANA
RZ
INX
OCR
IN
ANI

1HZ
HOY
OOT

STAm
COIIII2
It"
CDIIIm
A,B
A
H
B
STAm

CPBF
PAR2
It"

PAR~3

8273 STATUS
; ROTATE CBSV INTO CARRY
;WIlIT FOR OK
; OK, PIIM: COIItAII) INTO A
; OUTPUT CCftRi)
; GET PARfI£TER COLtH
;15 IT 8?
; YES, DO£, RETIRIN
; INC COItRil BUFFER POIHTEI!
; DEC PARIItETER CIUIT
; READ STATUS
; 15 CPBF BIT SET?
; IIlIT TIL ITS B
; IJI(, GET PARAI£TER FR1JI BLFFEI!

; REJlI)

; OOTPUT PRRAI£TER

; GET IEXT PARMTER
J~
PAR1
;
;
; INITIALIZE AND EllAIIlE RX DIll CHAIf£L
;
;
A,DROIIA
; DISABLE RX DIll CffHfl.
RXDI1A: ~I
OUT
; 8257 ID>E PORT
1'OOE57
B, RXBUF
; RX BUFFER START AOOR£SS
694
LXI
; Rl( BUFFER LSB
695
HOY
ItC
; CH8 ADR PORT
696
OUT
CHeADR
697
ItS
; RX BUFFER ItSS
"DV
698
OUT
; CH8 AOR PORT
CHeADR
S,Rl(TC
LXI
; RX CH TEERltINAL COUNT
699
A,C
; RX ~I1R. COONT L58
788
HOY
781
OUT
;CH8 TC PORT
CHeTC
782
HOY
ItS
; RX TERlfIIR. CIUIT ItSS
783
OUT
; CH8 TC PORT
CHeTC
; ElRIlE DIll WORO
7114
11'11
It~
; 8257 ID>E PORT
785
OUT
IIODE57
;~
786
RET
797 ;

788 ;

8835 3E61
BBJ7 DJAS
BBJ9 Maese
8BJC 79
BBJD DJA2
BBJF 78
I!B4B DJA2
8842 B1FF81
8845 79
BB46 D3AJ
e84B 78
8849 D3AJ
884B 3£6J
BB4D DJAB
BB4F C9

; INITIALIZE AND ENABlE TX DIll CIRI£I.
;
;
;DlSABLE TX DIll CffHfl.
TXDIIA: 11'11
It DTDIIA
; 8257 ID>E PORT
71J
OUT
IIlDE57
; TX BUFFER START fI>ORESS
714
B, TXBLF
LXI
; TX BUFFER LSB
715
I10V
ItC
; CHi AOR PORT
716
OUT
CH1ADR
717
A,B
; TX BUFFER ItSS
I10V
; CHi AOR PORT
718
OUT
CH1AOR
S, mc
; TX CH TERIHIR. CtuH
719 TXDIftI.: LXI
; TX TERlfIIR. COONT LSB
fl.e .
728
~
; CIU. TC PORT
721
OUT
CHiTC
; TX TERlfIIR. C!UIT ItSS
722
~
itS
; CHi TC PORT
OUT
CHiTC
72J
724
11'11
R.EIMl
; ElRIlE DIll IUD
; 8257 I10DE PORT
725
OUT
IIOOES7
;RET\JRN
726
RET
727;

789
718
711
712

728 ;
611001-56

2-159

intJ

AP-36

IlC89

1lC88 E5
I!CI!1 F5
9C82 C5
1lC83 05
9C84 3£62
9C86 D3A8
BC88 3E18
IlC8R 3Il
8C88 1684
IlC8D 2R1829
BC18 E5
8C11 E5
BC1245
8C13 2R1328
BC16 84
BC17 78
BC18 SO
BC19 CRE48R
BC1C 15
BC1D C2168C
BC28 16115
BC22 E1
8C23 DB9Il
8C25 E698
8C27 CA39BC
BC2R DB9Il
BC2C E6lI2
IIC2E CA23BC
9C31 0893
BC33 77
BC34 2C
BClS 15
BC36 C323BC
BC39 7R
8ClR A7
BC38 CR458C
8C3£ 3688
BC48 2C
8C4115
8C42 C339BC
8C45221828
BC48 3111528
8C4B FE2[)
BC4D CR858C

729
738
731
732
733
734
735
736

; lNERRUPT PROCESSING SECTI(JI
;
ORG
1lC89H.
;
;
; RECEIVER INTERRUPT - RST 7. 5 (LOC lCH)
;
; SAVE HL
RXI:
PUSH
H
PUSH
; 5A'/E PSII
737
PSII
;5A'/E BC
738
PUSH
8
PUSH
0
; SAVE DE
748
ItVI
fbDRDIII
; DISlB.E RX DIll
741
; 8257 IIOOE P(RT
OUT
IDl£57
742
ItVI
R.iSH
; RESET RST7. 5 FIF
743
51"
744
O.84H
;0 IS RESIU CWlTER
ItVI
745
; GET LOll) POINTER
LHLD
LDADR
;SAVE IT
746
PUSH
H
747
PUSH
; SAVE IT flGAlN
H
748
; SAVE LS8
!roY
8.L
; GET CONSDLE POINTER
749
LHLO
CIRlR
758 RXI1: INR
; BUt' LOfI> POINTER LS8
B
; GET SET TO TEST
fbB
751
/lOY
; LOfIl=CIIIS(l.E?
752
CI'I'
L
; 'r£S. BlFfER Fll.L
753
JZ
1lU'fll.
; DEC CIUITER
754
OCR
0
; NOT DONE. TRY AGAIN
755
JNZ
RXI1
; RESET CWiTER
ItVI
0.95H
756
; RESTORE LOfI> POINTER
757
POP
H
758 RX12: IN
; READ STATUS
STAID
; TEST RX [NT BIT
RXINT
759
ANI
; 1)(1£. GO FIN[SH If
RX13
768
JZ
[N
; READ STRTUS fIGA[N
761
STAID
AN[
RX[RA
; [5 RESll.T READY?
762
RX[Z
; NO, TEST fIGA[N
763
JZ
[N
RX[R73
764
; 'r£S. READ REru.T
;STORE [N BlFFER
765
It.R
HOY
[NR
; [t«: IlU'fER PO[NTER
766
L
; DEC CIUITER
767
OCR
0
768
RXI2
; GET /lORE RESllTS
JIf'
769 RXI3: /lOY
fbO
; GET SET TO TEST
; ALL RESllT51
RNA
A
RX[4
; 'r£S. SO F[N[SH If
771
JZ
1tV[
; 110. LOfI> 8 TIL [)(J£
1t.90H
[NR
; BUIf' PO[NTER
m
L
;DEC CWITER
774
OCR
0
RX[3
; GO fIGA[N
775
JIf'
776 RX[4: SHLD
; lfOATE LOfI> PO[NTER
l.DfilR
; GET IIOOE [ND[CATOR
LOA
PRII'T
CP[
;NORIR. IIODE'?
778
'-'
RX[6
; YEs, CLEAN If BEFORE RETUIN
779
JZ
788
POLL HODE SO CHECK ClINTRQ. BYTE
7B1
[F CONTRU. [5 A POLL. SET If SPEC[AL TX COlIN) BlFFER
7B2
AND RETURN W[TH POLL [ND[CATOR NOT 8
783

-

m

'.

m

m

m

7B4
BC59 E1

BC51 7E

7B5
"786

POP
/lOY

H
R."

; GET PREVIOUS LOfI> AOR POINTER
; GET [e BYTE FROH BlFFER

2-160

611001-57

inter

AP·36

9C52
8&54
8C57
9C58
8C59

E61E
C2890C
ZC
ZC
ZC

8CSA 56

0C5B ZC
8C5C 7E
8C5D FE!'3
8CSF CA6C8C
8C62 FEU
9C64 C2898C
OC67 1£11
0C69 C36E8C
0C6C 1E73
0C6E 212828

OC71 36C8
OC73 23
Be74 3688
8C7623
OC77 3688
OC79 23
OC7A 72
0C7B 23
OC7C 73
8C70 3£81
OC7F 321628
8C82 C3890C

8C85 E1
8C86 C3890C
8C89
0C8C
8C8O
8C8E
8C8F
8C98
OC91

C01R88
01
C1
F1
E1
FB
C9

OC92
BC93
BC94
0C95
OC97

C5
7E
23
FEFF
CAR1BC

BC9A
BC98
BC9E
8CA1

4F
COF895
C393BC
C1

0CA2 C9

,UJO( AT GOO) FRAI£ BITS
ANl
1EH
JNZ
RXI5
,IF NOT e. INTERRUPT IIlSN'T FRMR CIfH£L
824
POP
,RESTORE REGISTERS
0
825
PCf
B
826
POP
P5W
827
POP
H
828
EI
,Elfl8lE INTERRUPTS
829
RET
,REruRN
838 ,
831;
832 ,I£SSRGE TYPER - ASSlItES I£SSRGE STARTS RT II.
833 ,
834 ,
835 T'iItSG: PUSH
a
SfII/E Be
836 TYII5G2: !lOY
GET ASCII CHR
fL"
837
INX
H
It«: POINTER
838
CPI
SFFN
STOP?
839
J2
TYI15G1
YES, GET SET FOR EXIT
848
NOY
C.A
SET II' FOR OISPUIY
841
CALL
ECHO
OISPUIY CHR
842
JIf'
TYHSG2
GET NEXT CHR
843 T'IIISG1: PCf
a
RESTORE ae
844
RET
RETURN
845
846
847 SIGNON I£SSAGE
848
787
788
7a9
798
791
792
793
794
795
796
797
798

D."

m

2-161

611001-58

inter

Ap·36

9CR3
SCM
8CR8
8CfIC
ecse
8C84
8CB6
8C87

8CB8
ecB9
8C8D
8CC1
8CC2

8CC3
8CC4
8CC8
ecce
8CCD

80
38323733
284D4F4E
49544F52
28285631
2E31
80
FF

eo
52582949
4£542820
2S
FF

eo
54582849
4E54282O
28
FF

ecCE E5
8CCF F5
8CDB C5

BCD1
8CD2
8CD4
8CIl6
8CDB
8CDB
eeoc

ecoo

BCES
BCE1
BCE2
8CE3
·BCE6

D5
3E61
D3A8
1684
2A1928
E5
45
2A1328
84
78
so
CAE48A
15

8CE7 C2E1l8C
BCEft E1
8CEB DB92
8CED 77
8CEE 2C
8CEF 3688
8CF12C

8CF2
8CF4
8CF5
8CF7

36Il8
2C
36Il8
2C

849 SIGNOO: DB

CR, '8273 IOHm! Y11',CR,8FFH

sse ;
851
852
853
854
855
856

;
;
; RECEIVER INTERRuPT I£55AGES
;
;
RXIItSG: DB
CR, 'RX INT - ',8FFH

857
858
859
868

;
; TRANSltITTER INTERRIJ'T ItESSIIGES
;
CR, 'TX INT - ',8FFH
TXIItSG: DB

861;
862 ;
863 ; TRAHSI1ITTER INTERRIJ'T ROOTitE
864 ;
PUSH
865 TXI:
H
866
PUSH PSW
867
PUSH 8
868
PUSH
A,DTDIfl
869
ItVI
878
OUT
I9JDE57
D,84H
871
ItVI
872
LlLD
LOADR
873
PUSH H
!tOy
8,L
874
875
LILIl
CIRlR
876 TXI1: llil
8
A,S
877
lIlY
878
Clf'
L
B79
JZ
BIJ'F\L
BB8
OCR
D
8B1
TXI1
JN2
H
882
POP
IN
883
TXIR73
It, A
B84
lIlY
llil
B85
L
It,IlIlH
B86
ItVI
L
887
llil
1t,3lH
BB8
ItVI
BB9
llil
L
H,1lIlH
898
"YI
B91
IHI!
L

;SAYE HI.
;SA:t'E PSW
; SIM: 8C
;.5A'/E DE
; DISABlE TX DIll
; 8257 IQlE PlRT
; SET w..tflER
; lET LIJI) POINTER
; SIM: IT
; SIIYE LS8 IN 8
; GET caISOC.E POINTER
; INC POINTER
; lET SET TO TEST
; LOAI>=COOSOI.E?
; YES, BlfFER FI.lL
; NO, TEST NEXT LOCATION
;TR'/ fOIlN
; RESTIH: LIJI) POINTER
; REfI) RESll.T
; STORE IN BlfFER
; llil POINTER
; EXTRA lIESIl.T SPOTS e

2-162

611001-59

inter

AP-36

e(1'8
I)CI'R
OCFS
OCFE
0001
0{002
(t09:!
0084
OOOS
0006

S,;~O

B92

2C
221020
C[I,5e8
D1
(1
Fl
E1
1'8
(9

,39~

894
899
9il0
901
902
90,
904
905
%6
90,
952
95:;
954

MVl
ItIF
;HLD
CALL
POF
POP
POP
POP
EI
,:ET

N· eOH
L
L[!fIDP
TX[,IR
0
B
PSH
H

,UP['I1TE LOil~ POINTER
· FESET 01'111 CHANNEL
· PESTOPE ~E
· ~ESTORE BC
· P.ESTORE PSI!
,~ESTORE HI.
· EHI1SLE INTERRUPTS
, RETURN

'
.
'
.
EN~

PUSL!( SW1BOLS

EAmNAL SYMBOLS

USER SYMBOLS
A['HN A 0922
CMV51 A 082,
CNT053 A 0i!9C
COlIN A OAES
A 8000
DEH
ECHO A 85F8
lLLEG A 0BA,
I1CoCNT2 A 9iJ86
PARl A 0808
POLIN A 201.
R['I'
A 0092
RSCIiIl A 0967
RXI1 ~ 0el.
~,lNT A 0008
RSTC ~ 41FF
SPCHD A 09E2
STKSRT A 20ce
TESF'l A 0992
Ti:BUF A 8000
T;;INT A 0004
T'IHSG r1 OC9~

AFClI['
em,8Fl
GNUS,
ClJIIHl
['EHO[o£
ENDCHi<
LDA['~

MDE51
PAR2
PRtlPT
PESBUF
RSi65
R:m
RXim
S8CMD
SPCND

sw

A 09(E
A 2928
A e09D
A 9AEA
A 2827
A 8A1S
A 2018
A eeCE
A 0880
A 291S
A 2808
A 20CE
A 0[2l

p:m

A 0093
A 0985
A 89BA

R"IRA
SDWN
SS[MD
T1
TFCHDl
Ti:(lltA
TXIRA
TVNSG2

A 094,

TFCIiIl A 09E[
TXD51 ~ 0088
T~IRn A 0092
T'fMSGl A OCAl

ASSEMBLY COMFLETE.

BUFFUL
CI'H)BllF
CNT2S:;
COll'12
['ISPI'
EtIDllA
LF
MODE)?
PAI1IN
ROPT
RESL;:
RST,S

A 0AE4
A 2!l00
A 009E
A 9ilFF
A 0ffi9
A 0061
A OOOA
A 0898
A 8AAu
A 0AA2
A 0891
A 2tl!i4
A 0C,9

A 000.
A eSD?
A 09B0
A 0C6C
A 99F';
A 08::5
A 9001
A em

CHOADP A 80A0
';~100UT A OAFS
(NTLSl A 9989
CIJIIH7:; A 9990
DISPVl A 0A4E
Gl'WH r1 88FF
LK8Pl r1 201,
NODE57 R B0A8
PAPINi A OREa
RIPT A BAA7
ROCHD A 095['
RX8UF A 8200
RXI4 A 8C45
Ri:Sl A 01109
SIGNOH A OCA]
START A 0800
TBUFFL A 0A24
mET A 0A3';
n:DMAl A 9B42
n:POL A 094C
VALDG A 075E

CHef(
CttllREC
CNTLC
CPBF
DISPV2
GETCH

LlllR2
MONTOR
PRP.IN2
RSCH"
RPCM~

R:\DSl

iI:m
RXS2
SLOO
STATS!
TBUFL
TW1Co
TXI
Ti:P.£T

A 89Al
A 08';7
A 0003
A 0020
A 0A4D
A 061F
A 2018
A ee08
A OADe
A 09,B
A 09~a
A oeas
A 0C69
A 0A7F
A 9981'
A 00B9
A 0A07
A 0999
A eccE
A OC6E

CHlAOR A !l9fl2
CllfM A 8921

CIMlH
CA
DRDHA
GETOO
LOOPlT
NI10lJT
PARIN3
R~CI'H)

RR0F
RXNUl
RXI6
RXS:i
5IIRI1P
STAT57
TBUFLl
TRUE
TXI1
r..:sQRC

A 95B8
A 0000
A 006.2
A 1iiI7rI
A tJ861
A eoc7
A fIAB(
A 9971
A OOU
A 081R
A BC85
A 9A8D
A 0093
A e9RS
A BAOO
A iJ800
A BCEe
A 0A47

CHlTC A 98A3
~ A 2813
CoeR A B8IIC
(IllF R 95EB
DTDHR A 0001
iJRCII) A e9C4
IIlCNT9 R 9936
HSPf A 0073
PARII73 R 1!891
RDIf; A 0SAF
RR9P A 0011
RXI
R BC0B
R~IHSG A 9CB8
RX~ A 9A62
SOCII) A09A6
STAT73 A 0099
TDIfj A 9ge£
TRUE1 A eooe
TXIMSG A OCC?
TXTC A 81FF

NO ERROPS
611001-60

2-163

APPLICATION
NOTE

AP-134

October 1986

Asynchronous Communication
with the 8274 Multiple-Protocol
Serial Controller

Order Number: 210311-002
2-164

inter

AP-134

INTRODUCTION
The 8274 Multiprotocol serial controller (MPSC) is a
sophisticated dual-channel communications controller
that interfaces microprocessor systems to high-speed
serial data links (at speeds to 880K bits per second)
using synchronous or asynchronous protocols. The
8274 interfaces easily to most common microprocessors
(e.g., 8048, 8051, 8085, 8086, and 8088), to DMA controllers such as the 8237 and 8257, and to the 8089 I/O
processor. Both MPSC communication channels are
completely independent and can operate in a full-duplex communication mode (simultaneous data transmission and reception).

3. DMA Mode. The MPSC automatically requests data
transfers from system memory for both transmit and
receive functions by means of two DMA request signals per serial channel. These DMA request signals
may be directly interfaced to an 8237 or 8257 DMA
controller or to an 8089 I/O processor.
•4. WAIT Mode. The MPSC ready signal is used to synchronize processor data transfers by forcing the
processor to enter wait states until the 8214 is ready
for another data byte. This feature enables the 8274
to interface directly to an 8086 or 8088 processor by
means of string I/O instructions for very high-speed
data links.

Scope

Communication Functions
The 8274 performs many communications-oriented
functions, including:
Converting data bytes from a microprocessor system into a serial bit stream for transmission over
the data link to a receiving system.
Receiving serial bit streams and reconverting the
data into parallel data bytes that can easily be processed by the microprocessor system.
Performing error checking during data transfers.
Error checking functions include computing/transmitting error codes (such as parity bits or CRC
bytes) and using these codes to check the validity of
received data.
.
Operating independently of the system processor in
a manner designed to reduce the system overhead
involved in data transfers.

This application note describes the use of the 8274 in
asynchronous communication modes. Asynchronous
communication is typically used to transfer data to/
from video display terminals, modems, printers, and
other low-to-medium-speed peripheral devices. Use of
the 8274 in both iI;lterrupt-driven and polled system environments is described. Use of the DMA and WAIT
modes are not described since these modes are employed mainly in synchronous communication systems
where extremely high data rates are common. Programming examples are written in PL/M-86 (Appendix
B and Appendix C). PL/M-86 is executed by the
iAPX-86 and iAPX-88 processor families. In addition,
PL/M-86 is very similar to PL/M-80 (executed by the
MCS-80 and MCS-85 processor families). In addition,
Appendix D describes a simple application example using an SDK-86 in an iAPX-86/88 environment.

SERIAL-ASYNCHRONOUS DATA
LINKS

System Interface
The MPSC system interface is extremely flexible, supporting the following data transfer modes:
1. Polled Mode. The system processor periodically
reads (polls) an 8274 status register to determine
when a character has been received, when a character is neeried for transmission, and when transmission errors are detected.
2. Interrupt Mode. The MPSC interrupts the system
processor when a character has been received, when
a character is needed for transmission, and when
transmission errors are detected.

A serial asynch~onous interface is a method of data
transmission in which the receiving and transmitting
systems need not be synchronized. Instead of transmitting clocking information with the data, locally generated clocks (16, 32 or 64 times as fast as the data transmission rate) are used by the transmitting and receiving
systems. When a character of information is sent by the
transmitting system, the character data is framed (preceded and followed) by special START and STOP bits.
This framing information permits the receiving system
to temporarily synchronize with the data transmission.
(Refer to Figure 1 during the following dis~ussion of
asynchronous data transmission.)

2-165

inter

AP-134

-1-0.1

1-1-

DA~~~~I~~LE S~~~T ~
PARITY

CHARACTER (UPPER CASE S·53HI

o

I

0

o

I

0

I

1

210311-2

Figure 1. Transmission of a 7-Bit ASCII Character with Even Parity

Normally the data link is in an idle or marking 'state,
continuously transmitting a "mark" (binary 1). When a
character is to be sent, the character data bits are im·
mediately preceded by a "space" (binary 0 START bit).
The mark·to·space transition informs the receiving system that a character of information will immediately
follow the start bit. Figure 1 illustrates the transmission
of a 7-bit ASCII character (upper case S) with even
parity. Note that the character is transmitted immediately following the start bit. Data bits within the character are transmitted from least-significant to most-significant. The parity bit is transmitted immediately fol~
lowing the character data bits and the STOP framing
bit (bi~ary 1) signifies the end of the character.

Characters
In asynchronous mode, characters may vary in length
from five to eight bits. The character length depends on
the coding method used. For example, five-bit characters are used when transmitting Baudot Code, seven-bit
characters are required for ASCII data, and eight-bit
characters are needed for EBCDIC and binary data. To
transmit messages composed of multiple characters,
each character is framed and transmitted separately
(Figure 2).
This framing method ensures that the receiving system
can easily synchronize with the start and stop bits of
each character, preventing receiver synchronization errors. In addition, this synchronization method makes
both transmitting and receiving systems insensitive to
possible time delays between character transmissions.

Asynchronous interfaces are often used with human interface devices such as CRTlkeyboard units where the
time between data transmissions is extremely variable.

.

VARIABLE DELAY BETWEEN
CHARACTERS

~

NODELAY

BETWEEN
CHARACTERS

-,ft'I'IrI'I'I''IT""'''''I

I·
...iii ...iii
...
0
~
I;; '"
I I'"

...
...iii
'"~

tI
...1:
iii'"

Q.

m

ICHARACTER

*'

I:
Q.

0'"

t;;~

I
I
CHARACTER CHARACTER

.2

...iii

I:

'" ...'"
...0 '"
m ~

Q. ...

H3

Q.

...
0

m

I

I

...iii
...
...'"...

'"

Q.

...0

m

m

I

I

CHARACTER

CHARACTER

.4

H5

Figure 2. Multiple Character Transmission

2-166

I:

210311-1

AP-134

Framing
Character framing is accomplished by the ST ART and
STOP bits described previously. When the START bit
transition (mark-to-space) is detected, the receiving system assumes that a character of data will follow. In
order to test this assumption (and isolate noise pulses
on the data link), the receiving system waits one-half bit
time and samples the data link again. If the link has
returned to the marking state, noise is assumed, and the
receiver waits for another START bit transition.

bits per seco'nd to 38,400 bits per second. Table I illustrates typical asynchronous data rates and the associated clock frequencies required for the transmitter and
receiver circuits,
Table 1. Communication Data Rates and
Associated Transmitter/Receiver Clock Rates
Data Rate
(Bits/Second)

75
150
300
600
1200
2400
4800
9600
19200
38400

When a valid START bit is detected, the receiver samples the data link for each bit of the following character. Character data bits and the parity bit (if required)
are sampled at their nominal centers until all required
characters are received. Immediately following the data
bits, the receiver samples the data link for the STOP
bit, indicating the end of the character. Most systems
permit specification of 1, 11/ 2 , or 2 stop bits.

Clock Rate (kHz)

X16

X32

X64

1.2
2.4
4.8
9.6
19.2
38.4
76.8
153.6
307.2
614.4

2.4
4.8
9.6
19.2
38.4
76.8
153.6
307.2
614.4

4.8
9.6
19.2
38.4
76.8
153.6
307.2
614.2

-

-

Timing
The transmitter and receiver in an asynchronous data
link arrangement are clocked independently. Normally,
each clock is generated locally and the clocks are not
synchronized. In fact, each clock may be a slightly different frequency. (In practice, the frequency difference
should not exceed a few percent. If the transmitter and
receiver clock rates vary substantially, errors will occur
because data bits may be incorrectly identified as
START or STOP framing bits.) These clocks are designed to operate at 16, 32, or 64 times the communications data 'rate. These clock speeds allow the receiving
device to correctly sample the incoming bit stream.
Serial-interface data rates are measured in bits/second.
The term "baud" is used to specify the number of times
per second that the transmitted signal level can change
states. In general, the baud is not equal to the bit rate.
Only when the transmitted signal has two states (electricallevels) is the baud rate equal to the bit rate. Most
point-to-point serial data links use RS-232-C, RS-422,
or RS-423 electrical interfaces. These specifications call
for two electrical signal levels (the baud is equal to the
bit rate). Modem interfaces, however, may often have
differing bit and baud rates.
While there are generally no limitations on the data
transmission rates used in an aysnchronous data link, a
limited set of rates has been standardized to promote
equipment interconnection. These rates vary from 75

Parity
In order to detect transmission errors, a parity bit may
be added to the character data as it is transferred over
the data link. The parity bit is set or cleared to make
the total number of "one" bits in the character even
(even parity) or odd (odd parity), For example, the letter "A" is represented by the seven-bit ASCII code
1000001 (4IH). The transmitted data code (with parity)
for this character contains eight bits; 01000001 (4IH)
for even parity and 11000001 (OCIH) for odd parity,
Note that a single bit error changes the parity of the
received character and is therefore easily detected. The
8274 supports both odd and even parity checking as
well as a parity disable mode to support binary data
transfers.

Communication Modes
Serial data transmission between two devices can occur
in one of three modes. In the simplex transmission
mode, a data link can transmit data in one direction
only. In the half-duplex mode, the data link can transmit data in both directions, but not simultaneously. In
the full-duplex mode (the most common), the data link
can transmit data in both directions simultaneously.
The 8274 directly supports the full-duplex mode and
will interface to simplex and half-duplex communication data links with appropriate software controls,

2-167

intef

AP-134

BREAK Condition
Asynchronous data links often include a special se. quence known as a break condition. A break condition
is initiated when the transmitting device forces the data
link to a spacing state (binary 0) for an extended length
of time (typically 150 milliseconds). Many terminals
contain keys to initiate a break sequence. Under software control, the 8274 can initiate a break sequence
when transmitting data and detect a break sequence
'
when receiving data.

The 8274-processor hardware interface can be configured in a flexible manner, depending on the oPerating
mode selected-polled, interrupt-driven, DMA, or
WAIT. Figure 3 illustrates typical MPSC configurations for use with an 8088 microprocessor in the polled
and interrupt-driven modes.
All serial-to-parallel conversion, parallel-to-serial con-'
version, and parity checking required during asynchronous serial I/O operation is automatically performed
by the MPSC.

Operational Interface

MPSC SYSTEM INTERFACE
Hardware Environment
The 8274 MPSC interfaces to the system processor over
an 8-bit data bus. Each serial I/O channel responds to
two I/O or memory addresses as shown in Table 2. In
addition, the MPSC supports non-vectored and vectored interrupts.
The 8274 may be configured for memory-mapped or
I/O-mapped operation.

Command, parameter, and status information is stored
in 21 registers within the Mpsc (8 writable registers
and 2 readable registers for each channel, plus the interrupt vector register). These registers are all accessed
, by means of the command/status ports for each channel. An internal pointer register selects which of the
command or status registers will be written or read during a command/status access of an MPSC channel.
Figure 4 diagrams the command/status register archi, tecture for each serial channel. In the following discussion, the writable registers will be referred to as WRO
through WR7 and the readable registers will be referred to as RRO through RR2.

Table 2. 8274 Addressing

CS

A1

Ao

Read Operation

Write Operation

0
0
0
0

0

0
0

1

1
1

1

X

X

Ch. A Data Read
Ch. A Status Read
Ch. 8 Data Read
Ch. 8 Status Read
High Impedance

Ch. A Data Write
Ch. A Command/Parameter
Ch. 8 Data Write
Ch. 8 Command/Parameter
High Impedance

1

0

2-168

intJ

AP-134

~

.,. ...

ADDRESS BUS

6 DATA

6
II

BUS

iiD
WR

-

8205

'--

~
0

'--

U
VCC

DBO-7

INTA

' - - - Ao
A,
CS
RD
WR

MPSC

210311-3

a) Polled Configuration

'~HJ

INTA
CPU

INT

~

IPI

b

INTA

b

INTA

INT

IPO

IPO

IPI
MPSC

MPSC
HIGHEST PRIORITY

INT
IPI

b

INTA

IPO

MPSC
LOWEST PRIORITY

210311-4

b) Daisy-Chained Interrupt Configuration
Figure 3. 8274 Hardware Interface for Polled and Interrupt-Driven Environments
The least-significant three bits ofWRO are automatically loaded into the pointer register every time WRO is
written. After reset, WRO is set to zero so that the first
write to a command register causes the data to be loaded into WRO (thereby setting the pointer register). After WRO is written, the following read or write accesses
the register selected by the pointer. The pointer is reset
after the read or write operation is completed. In this
manner, reading or writing an arbitrary MPSC channel
register requires two I/O accesses. The first access is
always a write command. This write command is used
to set the pointer register. The second access is either a
read or a write command; the pointer register (previously set) will ensure that the correct internal register is
read or written. After this second access, the pointer
register is automatically reset. Note that writing WRO

and reading RRO does not require presetting of the
pointer register.
During initialization and normal MPSC operation, various registers are read and/or written by the system
processor. These actions are discussed in detail in the
following paragraphs. Note that WR6 and WR7 are
not used in the asynchronous communication modes.

RESET
When the 8274 RESET line is activated, both MPSC
channels enter the idle state. The serial output lines are
forced to the marking state (high) and the modem interface signals (RTS, DTR) are forced high. In addition, the pointer register is set to zero.

2-169

inter

Ap·134

COMMAND/STATUS
POINTER

02

Dt

DO

0

0

,0

0

0

0

------..
_I

-I
-I
-I
-I
-I
-I
-I

W :

R

W

R

W

R

:

:

o :

1 1

R

R

1 1

R

R

R

R

I1

2

I

2'

MSB

LSB
Read Registers

W

R

W

R

4
'Ch. B only

W

R

W

R

W

R

7

1

MSB

LSB
Write Registers

210311-5

Figure 4. Command/Status Register Architecture (Each Serial Channel)

External/Status Latches
The MPSC continuously monitors the state of four external/status' conditions:
1.. CTS-clear-to-send input pin.
2. CD-carrier-detect input pin.
3. SYNDET-sync-detect input pin. This pin may be
used as a general-purpose input in the asynchronous
communication mode.
4. BREAK-a break condition (series of space bits on
the receiver input pin).

A change of state in any of these monitored conditions
will cause the associated status bit in RRO (Appendix
A) to be latched (and optionally cause an interrupt).

Error Reporting
Three error conditions may be encountered during data
reception in the asynchronous mode:
1. Parity. If parity bits are computed and transmitted
with each character and the MPSC is set to check
parity (bit 0 in WR4 is set), a- parity error will occur
whenever the number of "I" bits within the character (including the parity bit) does not match the odd/
even setting of the parity check flag (bit 1 in WR4).

2-170

inter

AP-134

2. Framing. A framing error will occur if a stop bit is
not detected immediately following the parity bit (if
parity checking is enabled) or immediately following ,
the most-significant data bit (if parity checking is not
enabled).
3. Overrun. If an input character has been assembled
but the receiver buffers are full (because the previously received characters have not been read by the
system processor), an overrun error will occur.
When an overrun error occurs, the input character
that has just been received will overwrite the imme, diately preceding character.

TransmitterIReceiver Initialization
In 'order to operate in the asynchronous mode, each
MPSC channel must be initialized with the following
information:
1. Clock Rate. This parameter is specified by bits 6 and
7 ofWR4. The clock rate may be set to 16,32, or 64
times the data-link bit rate. (See Appendix A for
WR4 details.)
2. Number of Stop Bits. This parameter is specified by
bits 2 and 3 of WR4. The number of stop bits may be
set to 1, 1'/., or 2. (See Appendix A for WR4
details.)
3. Parity Selection. Parity may be set for odd, even, or
no parity by bits 0 and 1 of WR4. (See Appendix A
for WR4 details.)
4. Receiver Character Length. This parameter sets the
length of received characters to 5, 6, 7, or 8 bits. This
parameter is specified by bits 6 and 7 of WR3. (See
Appendix A for WR3 details.)
5. Receiver Enable. The serial-channel receiver operation may be enabled or disabled by setting or clearing
bit 0 of WR3. (See Appendix A for WR3 details.)
6. Transmitter Character Length. This parameter sets
the length of transmitted characters to 5, 6, 7, or 8
bits. This parameter is specified by bits 5 and 6 of
WR5. (See Appendix A for WR5 details.) Characters
of less than 5 bits in length may be transmitted by
setting the transmitted length to five bits (set bits 5
and 6 of WR5 to 1).
The MPSC then determines the actual number of
bits to be transmitted from the character data byte.
The bits to be transmitted must be right justified in
the data byte, the next three bits must be set to 0 and
all remaining bits must be set to I. The following
table illustrates the data formats for transmission of
I to 5 bits of data:

Number of
Bits Transmitted
(Characte'r Length)
1
2
3
4

07 06 05 04 03 02 01 00
1 1 1 1 0 0 0 c
1 1 1 0 0 0 c c
1 1 0 0 0 c c c
1 0 0 0 c c c c
0 0 0 c c c c c
5
7. Transmitter Enable. The serial channel transmitter
operation may be enabled or disabled by setting or
clearing bit 3 of WR5. (See Appendix A for WR5
details.)

For data transmissions via a modem or RS-232-C interface, the following information must also be specified:
1. Request-to-Send/Data-Terminal-Ready. Must be set
to indicate status of data terminal equipment. Request-to-send is controlled by bit 1 of WR5 and data
terminal ready is controlled by bit 7. (See Appendix
A for WR5 details.)
2. Auto Enable. May be set to allow the MPSC to automatically enable the channel transmitter when, the
clear-to-send signal is active and to automatically enable the receiver when the carrier-detect signal is active. Auto Enable is controleld by bit 5 of WR3. (See
Appendix A for WR3 details.)
During initialization, it is desirable to guarantee that
the external/status latches reflect the latest interface
information. Since up to two state changes are internally stored by the MPSC, at least two Reset External/
Status Interrupt commands must be issued. This procedure is most easily accomplished by simply issuing this
reset command whenever the pointer register is set during initialization.
An MPSC initialization procedure (MPSC$RX$INIT)
for asynchronous communication is listed in Appendix
B. Figure 5 illustrates typical MPSC initialization parameters for use with this procedure.

call MPSC$RX$INIT(41,

1,1,0,1, 3,1,1,

3,1,1,0,1);

initializes the 8274 at address 41 as follows:
X16 clock rate
1 stop bit
Odd parity
8-bit characters
(Txand Rx)

Enable transmitter
and receiver
Auto enable set
DTR and RTS set
Break transmission disabled

Figure 5. Sample 8274 Initialization Procedure
for Polled Operation·

2-171

inter

AP-134

Polled Operation
In the polled mode, the processor must monitor the
MPSC status by testing the appropriate bits in the read
register. Data avaibible, status, and error conditions are
represented in RRO and RRI for channels A and B. An
example of MPSC-polled transmitterireceiver routines
are given in Appendix B. The following routines are
detailed:
1. MPSC$POLL$RCV$CHARACTER-This procedure receives a character from the serial data link.
The routine waits until the character-available flag in
RRO has been set. When this flag indicates that a
character is available, RRI' is checked for errors
(overrun, parity, or framing). If an error is detected, the character in the MPSC receive buffer
must be read and discarded and the error routine
(RECEIVE$ERROR) is called. If no receive errors
have been detected, the character is input from the
8274 data port and returned to the calling program.
MPSC$POLL$RCV$CHARACTER requires three
parameters-the address of the 8274 channel data
port (data$port), the address of the 8274 channel
command port (cmd$port), and the address ofa byte
variable in which to store the received character
(character$ptr).
2. MPSC$POLL$TRAN$CHARACTER-This procedure transmits a character to the serial data link.
The routine waits until the transmitter-buffer-empty
flag has been set in RRO 'before writing the character
to the 8274.
MPSC$POLL$TRAN$CHARACTER
requires
three parameters-the address of the 8274 channel
data port (data$port), the address of the 8274 channel command port (cmd$port), and the character of
data that is to be transmitted (character).
3. RECEIVE$ERROR-This procedure processes receiver errors. First, an Error Reset command is written to the affected channel. All additional error processing is dependent on the specific application. For
example, the receiving device may immediately request retransmission of the character or wait until a
message has been completed.
RECEIVE$ERROR requires two parameters-the
address of the affected 8274 command port
(cmd$port) and the error status (status) from 8274
register RR 1.

Interrupt-Driven Operation
In an interrupt-driven environment,. all receiver operations are reported to the system processor by means of
interrupts. Once a character has been received and assembled, the MPSC interrupts the system processor.
The system processor must then read the character
from the MPS<:: data buffer and clear the current interrupt. During transmission, the system processor starts

serial I/O by writing the first character of a message to
the MPSC. The MPSC interrupts the system 'processor
whenever the next character is required (i.e., when the
transmitter buffer is empty) and the processor responds
by writing the next character of the message to the
MPSC data- port for the appropriate channel.
By using interrupt-driven I/O, the MPSC proceeds independently of the system processor, signalling the
processor only when characters are required for transmission, when characters are received from the data
link, or when errors occur. In this manner, the system
processor may continue execution of other tasks while
serial I/O is performed concurrently.

Interrupt Configurations
The 8274 is designed to interface to 8085- and 8086type processors in much the same manner as the 82S9A
is designed. When operating in the 8085 mode, the 8274
causes a "call" to a prespecified, interrupt-service routine location. In the 8086 mode, the 8274 presents the
processor with a one-byte interrupt-type number. This
interrupt-type number is used to "vector" through the
8086 interrupt service table. In either case, the interrupt service address or interrupt-type number is specified during MPSC initialization.
-To shorten interrupt latency, the 8274 can be programmed to modify the prespecified interrupt vector so
that no software overhead is required to determine the
cause of an interrupt. When this "status affects vector"
mode is enabled, the following eight interrupts are differentiated automatically by the 8274 hardware:
-1. Channel B Transmitter Buffer Empty.
2. Channel B External/Status Transition.
3. Channel B Character Available.
4. Channel B Receive Error.
5. Channel A Transmitter Buffer Empty.
6. Channel A External/Status Transition.
7. Channel A Character Available.
8. Channel A Receive Error.

Interrupt Sources/Priorities
The 8274 has three interrupt sources for each channel:
1. Receiver (RxA, RxB). An interrupt is initiated when
a character is available in the receiver buffer or when
a receiver error (parity, framing, or overrun) is detected.
2. Transmitter (TxA, TxB). An interrupt is initiated
when the transmitter buffer is empty and the 8274 is
ready to accept another character for transmission.

2-172

inter

AP-134

3. External/Status (ExTA, ExTB). An interrupt is initiated when one of the external/status conditions
(CDE, CTS, SYNDET, BREAK) changes state.
The 8274 supports two interrupt priority orderings (selectable during MPSC initialization) as detailed in Appendix A, WR2, CH-A.

Interrupt Initialization

3. External/Status Interrupts. External/Status interrupts can be separately enabled by bit 0 of WR I. (See
Appendix A for WRI details.)
4. Interrupt Vector. An eight-bit interrupt-service routine location (8085) or interrupt type (8086) is specified through WR2 of channel B. (See Appendix A
for WR2 details.) Table 3 lists interrupt vector addresses generated by the 8274 in the "status affects
vector" mode.
5. "Status Affects Vector" Mode. The 8274 will auto-

In addition to the initialization parameters required for
polled operation, the following parameters must be supplied to the 8274 to specify interrupt operation:
I. Transmit Interrupt Enable. Transmitter-buffer-empty interrupts are separately enabled by bit I of WRI.
(See Appendix A for WRI details.)
2. Receive Interrupt Enable. Receiver interrupts are
separately enabled in one of three modes: a) interrupt
on first received character only and on receive errors
(used for message-oriented transmission systems), b)
interrupt on all received characters and on receive
errors, but do not interrupt on parity errors, and c)
interrupt on all received characters and on receive
errors (including parity errors). The ability to separately disable parity interrupts can be extremely useful when transmitting messages. Since the parity error bit in RRI is latched, it will not be reset until an
error reset operation is performed. Therefore, the
parity error bit will be set if any parity errors were
detected in a multi-character message. If this mode is
used, the serial I/O software must poll the parity
error bit at the completion of a message and issue an
error reset if appropriate. The receiver interrupt
mode is controlled by bits 3 and 4 of WRI. (See
Appendix A for WRI details.)

matically modify the interrupt vector if bit 3 of WR I
is set. (See Appendix A for WRI details.)
6. System Configuration. Specifies the 8274 data transfer mode. Three configuration modes are available:
a) interrupt-driven operation for both channels, b)
DMA operation for both channels, and c) DMA operation for channel A, interrupt-driven operation for
channel B. The system configuration is specified by
means of bits 0 and I of WR2 (channel A). (See
Appendix A for WR2 details.)
7. Interrupt Priorities. The 8274 permits software specification of receive/transmit priorities by means of
bit 2 of WR2 (channel A). (See Appendix A for
WR2 details.)
8. Interrupt Mode. Specifies whether the MPSC is to
operate in a non-vectored mode (for use with an external interrupt controller), in an 8086-vectored
mode, or in an 808S-vectored mode. This parameter
is specified through bits 3 and 4 of WR2 (channel
A). (See Appendix A/or WR2 details.)
An
MPSC
interrupt
initialization
procedure
(MPSC$INT$INIT) is listed in Appendix C.

2-173

AP-134

Table 3. MPSC-Generated Interrupt Vectors in "Status Affects Vector"Mode

V7

V6

V5

V4

V3

V2

V1

VO

V7

V6

8086
Interrupt Type

V5

V4

V3

V2

V1

VO

Original Vector
(Specified during
Initialization)
Interrupt
Condition

8085
Interrupt Location

V7

V6

V5

V4

V3

0

0

0

V7

V6

V5

0

0

0

V1

VO

Channel B Transmitter
Buffer Empty

V7

V6

V5

V4

V3

0

0

1

V7

V6

V5

0

0

1

V1

VO

Channel B External/Status
Change

V7

V6

V5

V4

V3

0

1

0

V7

V6

V5

0

1

0

V1

VO

Channel B Receiver
Character Available

V7

V6

V5

V4

V3

0

1

1

V7

V6

V5

0

1

1

V1

VO

Channel B Receive Error

V7

V6

V5

V4

V3

1

0

0

V7

V6

V5

1

0

0

V1

VO

Channel A Transmitter
Buffer Empty·

V7

V6

V5

V4

V3

1

0

1

V7

V6

V5

1

0

1

V1

VO

Channel A External/Status
Change

V7

V6

V5

V4

V3

1

1

0

V7

V6

V5

1

1

0

V1

VO

Channel A Receiver
Character Available

V7

V6

V5

V4

V3

1

1

1

V7

V6

V5

1

1

1

V1

VO

Channel A Receive Error

Interrupt Service Routines
Appendix C lists four· interrupt service procedures, a
buffer transmission procedure, and a buffer reception
procedure that illustrate the use of the 8274 in interrupt-driven environments. Use of these procedures assumes that the 8086/8088 interrupt vector is set to 20H
and that channel B is used with the "status affects vector" mode enabled.
I. TRANSMIT$BUFFER-This procedure begins serial transmission of a data buffer. Two parameters
are required-a pointer to the buffer (buf$ptr) and
the length of the buffer (buf$length). The procedure
first sets the global buffer pointer, buffer length, and
initial index for the transmitter-interrupt service routine and initiates transmission by writing the first
character of the buffer to the 8274. The procedure .
then enters a wait loop until the I/O completion
status is set by the transmit-interrupt service routine
(MPSC$TRANSMIT$CHARACTER$INT).
2. RECEIVE$BUFFER-This procedure inputs a line
(terminated by a line feed) from a serial I/O port.
Two parameters are required-a pointer to the input
buffer (buf$ptr) and a pointer to the buffer length
variable (buf$length$ptr). The buffer length will be
set by this procedure when the complete line has
been input. The procedure first sets the global buffer
pointer and initial index for the receiver interrupt
service routine. RECEIVE$BUFFER then enters a
wait loop until the I/O completion status is set by
the receive interrupt routine (MPSC$RECEIVE$CHARACTER$INT).

3. MPSC$TRANSMIT$CHARACTER$INT-This
procedure is executed when the MPSC Tx-bufferempty interrupt is acknowledged. If the current
transmit buffer index is less than the buffer length,
the next character in the buffer is written to the
MPSC data port and the buffer pointer is updated.
Otherwise, the transmission complete status is posted.
4. MPSC$RECEIVE$CHARACTER$INT-This procedure is executed when a character has been assembled by the MPSC and the MPSC has issued a character-available interrupt. If no input buffer has been
set up by RECEIVE$BUFFER, the character is ignored. If a buffer has been set up, but it is full, a
receive overrun error is posted. Otherwise, the received character is read from the MPSC data port
and the buffer index is updated. Finally, if the received character is a line feed, the reception complete
status is posted.
5. RECEIVE$ERROR$INT-This procedure is executed when a receive error is detected. First, the error conditions are read from RRI and the character
currently inthe MPSC receive buffer is read and discarded. Next, an Error Reset command is written to
the affected channel. All additional error processing
is application dependent.
6. EXTERNAL$ST A TUS$CHANGE$INT-This
procedure is executed when an external status condition change is detected. The status conditions are
read from RRO and a Reset External/Status Interrupt command is issued. Further error processing is
application dependent.

2-174

inter

AP-134

DATA LINK INTERFACE
Serial Data Interface
Each serial I/O channel within the 8274 MPSC interfaces to two data link lines-one line for transmitting
data and one for receiving data. During transmission,
characters are converted from parallel data format (as
supplied by the system processor or DMA device) into
a serial bit stream (with START and STOP bits) and
clocked out on the TxD pin. During reception, a serial
bit stream is input on the RxD pin, framing bits are
stripped out of the data stream, and the resulting character is converted to parallel data format and passed to
the system processor or DMA device.

Data Clocking
As discussed previously, the frequency of data transmission/reception on the data link is controlled by the
MPSC clock in conjunction with the .programmed
clock divider (in register WR4). The 8274 is designed to
permit all four serial interface lines (TxD and RxD for
each channel) to operate at different data rates. Four
clock input pins (TxC and RxC for each channel) are
available for this function. Note that the clock rate divider spcified in WR4 is used for both RxC and TxC on
the appropriate channel; clock rate dividers for each
channel are independent.

Modem Control
The following four modem interface signals may be
connected to the 8274:
I. Data Terminal Ready (DTR). This interface signal
(output by the 8274) is software controlled through
bit 7 of WRS. When active, DTR indicates that the
data terminal/computer equipment is active and

ready to interact with the data communications
channel. In addition, this signal prepares the modem
for connection to the communication channel and
maintains connections previously established (e.g.,
manual call origination).
2. Request To Send (RTS). This interface signal (output by the 8274) is software controlled through bit I
of WRS. When active, RTS indicates that the data
terminal/computer equipment is ready to transmit
data. When the RTS bit is reset in asynchronous
mode, the signal does not go high until the transmitter is empty.
3. Clear To Send (CTS). This interface signal (input to
the 8274) is supplied by the modem in response to an
active RTS signal. CTS indicates that the data terminal/computer equipment is permitted to transmit
data. The s.tate of CTS is available to the programmer as bit S of RRO. In addition, if the auto enable
control is set (bit S of WR3), the 8274 will not transmit data bytes until CTS has been activated. If CTS
becomes inactive during transmission of a character,
the current character transmission is completed before the transmitter is disabled.
4. Carrier Detect (CD). This interface signal (input to
the 8274) is supplied by the modem to indicate that a
data carrier signal has been detected and that a valid
data signal is present on the RxD line. The state of
CD is available to the programmer as bit 3 of RRO.
In addition, if the auto enable control is set (bit S of
WR3), the 8274 will not enable the serial receiver
until CD has been activated. If the CD signal becomes inactive during reception of a character, the
receiver is disabled, and the partially received character is lost.
In addition to the above modem interface signals, the
8274 SYNDET input pin for channel A may be used as
a general-purpose input in the asynchronous communication mode. The status of this signal is available to the
programmer as bit 4 of status register RRO.

2-175

inter

AP-134

APPENDIX A
COMMAND/STATUS DETAILS FOR ASYNCHRONOUS
COMMUNICATION
logic and all control registers for the channel. Four extra system clock cycles should
be allowed for MPSC reset time before
any ad,ditional commands or controls are
written into the channel.
Command 4 Enable Interrupt on Next Receive Character-if the Interrupt-on-First-Receive
Character mode is selected, this command
reactivates that mode after each complete
message is received to prepare the MPSC
for the next message.
Command 5 Reset Transmitter Interrupt Pending-if
the Transmit'Interrupt mode is selected,
the MPSC automatically interrupts data
when the transmit buffer becomes empty.
When there are no more characters to be
sent, issuing this command prevents further transmitter interrupts until the next
character has been completely sent.
Command 6 Error Reset-error latches, Parity and
Overrun errors in RRI are reset.
Command 7 End of Interrupt-resets. the interrupt-inservice latch of the highest-priority internal device under service.

Write Register 0 (WROj:

COMMAND/STATUS POINTER
REGISTER POINTER

r

0

o1
1

o•

. NULL CODE
NOT USED IN ASYNCHRONOUS MODES

RESET EXrfSTATUS INTERRUPTS
CHANNEL ReSET
ENABLE INTERRUPT ON NEXT Rx

CHARACTER
RESET TxlNT PENDING
ERROR REseT

BID OF INTERRUPlICh. AHI,)

NOT USED IN ASYNCHRONOUS MODES

210311-6

Write Register 1 (WR1):
02,01,00 Command/Status Register Pointer bits
determine which write-register' the next
byte is to be written into, or which readregister the next byte is to be read from.
After reset, the first byte written into either channel goes into WRO. Following a
read or write to any register (except WRO)
the pointer will point to WRO.
05,04,03 Command bits determine which of the basic seven commands are to be performed.
Command 0 Null-has no effect.
Command 1 Note used in asynchronous modes.
Command 2 Reset External/Status Interrupts-resets
the latched status bits of RRO and reenables them, allowing interrupts to occur
again.
Coinmand 3 Channel Reset-resets the Latched Status
bits of RRO, the interrupt prioritization

00

01

02

2-176

External/Status Interrupt Enable-allows
interrupt to occur as the result of transitions on the CO, CTS or SYNOET inputs. Also allows interrupts as the result
of a Break/Abort detection and termination, or at the beginning of CRC, or sync
character transmission when the Transmit
Underrun/EOM latch becomes set.
Transmitter Interrupt/OMA Enable-allows the MPSC to interrupt or request a
OMA transfer when the transmitter buffer
becomes empty.
Status Affects Vector-(WR1, 02 active
in channel B only.) If this bit is not set,
then the fixed vector, programmed in
WR2, is returned from an interrupt acknowledge sequence. If the bit is set, then
the vector returned from an interrupt acknowledge is variable as shown in the Interrupt Vector Table.

inter

Ap·134

Write Register 1 (WR1):

Write Register 2 (WR2): Channel A
MSB

[D7[

I

LSB

MSB
0

[ DS [ D4 : D3 [ D'[ D, [ DO [

D7

:

0

I I
DS

I

D4 : D3

D'[ D' : DO [

'--..,-J
'--..,-J

I

'--..,-J
0

0

BOTH INTERRUPT

0

,

A DMA. B INT

1

0

EXT INTERRUPT
ENABLE

TxINTERRUPT/

, ,

OMA ENABLE

STATUS AFFECTS
VECTOR(CH B ONL V)

,

VARIABLE

0

VECTOR
FIXED

1

= PRIORITY RIIA>RxS>TxA>
rxa>EXTAo>EXTU"

o-

VECTOR

(N ULL CODE CH A)

PRIORITY RICA >TxA >RxB

~

0

~

0

0

0

,

>

rxS>EXTA">eXTO"

0

8085 MODE 1

RxiNTIDMA DISABLE

0

1

8085 MODE 2

CONDITION

,

0

8086188 MODE

1

1

ILLEGAL

RxiNT ON FIRST CHAR OR SPECIAL

,

0

,

INT ON ALL Rx CHAR (PARITY AFFECTS
VECTOR)OR SPECIAL CONOITION

1

INT ON ALL Rx CHAR (PARITY DOES
NOT AFFECT VECTOR) OR SPECIAL

CONDITION

1

0

,

BOTHDMA
ILLEGAL

WAIT ON Rx, 0

=

=

MUST BE ZERO

WAIT ON 1x
1

MUSTBEZERO

PIN 10='S"YN"DEf e

o
WAIT ENABLE 1

ENABLE. 0

VECTORED INTERRUPT

NON VECTORED INTERRUPT

DISABLE

NOTE:

PIN 10

= RTS e
210311-8

"External Status Interrupt-only if EXT Interrupt Enable

210311-7

(WR1; DO) is set.

D4,D3

00
o1

1 0

1 1

DS

D6
D7

Receive Interrupt Mode.
Receive Interrupts/DMA Disabled.
Receive Interrupt on First Character Only
or Special Condition.
Interrupt on All Receive Characters of
Special Condition (Parity Error is a Special Receive Condition).
Interrupt on All Receive Characters or
Special Condition (Parity Error is not a
Special Receive Condition).
Wait on ReceivelTransmit-when the following conditions are met, the RDY pin is
activated, otherwise it is held in the HighZ state. (Conditions: Interrupt Enabled
Mode, Wait Enabled, CS ~ 0, AO = Oil,
and Al = 0). The RDY pin is pulled low
when the transmitter buffer is full or the
receiver buffer is empty and it is driven
High when the transmitter buffer is empty
or the receiver buffer is full. The RDY A
and RDYB may be wired or connected
since only one signal is active at anyone
time while the other is in the High Z state.
Must be Zero.
Wait Enable--enables the wait function.

Dl,DO

00

o1
1 0
1 1
D2

o

2-177

System Configuration-These specify the
data transfer from MPSC channels to the
CPU, either interrupt or DMA based.
Channel A and Channel B both use interrupts.
Channel A uses DMA, Channel B uses interrupt.
Channel A and Channel B both use
DMA.
Illegal Code.
Priority-this bit specifies the relative priorities of the internal MPSC interrupti
DMA sources.
(Highest) RxA, TxA, RxA, RxB,
TxBExTA, ExTB (Lowest).
(Highest) RxA, RxB, TxA, TxB, ExTA,
ExTB (Lowest).

AP-134

D5,D4,D3

OXX
100

101

110

D6

Interrupt Cod~specifies the behavior of
the MPSC when it receives an interrupt
acknowledge sequence from the CPU. (See
Interrupt Vector Mode Table.)
Non-vectored interrupts-intended for
use with an external interrupt controller
such as the 82S9A.
8085 Vector Mode I-intended for use as
. the primary MPSC in a daisy-chained priority structure.
8085 Vector. Mode 2-intended for use as
any secondary MPSC in a daisy-chained
priority structure.
8086/88 Vector Mod~intended for use
as either a primary or secondary in a daisy-chained priority structure.
Must be Zero.

Write Register 3 (WR3):
MSB

LSB

R.ENABLE

L-_ _ _ _ NOT USED IN

ASYNCHRONOUS
MODES

L - - - - - - - - - - A U T O ENABLES

D7

R. 5 BITS/CHAR

o

Pin 10 = RTSB'
Pin 10 = SYNDETB.

R.7 BITS/CHAR
R. 6 BITS/CHAR
R. 8 BITs/CHAR

Write Register 2 (WR2): Channel B
MSB

210311-10

DO

LSB

I~:~:~:~:~:~: ~:~I

os

\

Vector

210311-9

D7-DO

Interrupt vector-this register contains
the value of the interrupt vector placed on
'the data bus during acknowledge sequences.

D7,D6
00

o1
10
1 1

2-178

Receiver Enabl~a one enables the receiver to begin. This bit should be set only
after the receiver has been initialized.
Auto Enables-a one written to this bit
causes CD to be an automatic enable signal for the receiver and CTS to be an automatic enable signal for the transmitter. A
zero written to this bit limits the effect of
CD and CTS signals to setting/resetting
their corresponding bits in the status register (RRO).
.
. Receiver Character length.
. Receive 5 Data bits/character.
Receive 7 Data bits/character.
Receive 6 Data bits/character.
Receive 8 Data bits/character.

inter

AP-134

Write Register 4 (WR4):

Write Register S (WRS):
MSB

LSB

1 D71 D6

! D51

D4

I I I I I
D3

D2

Dl

1 . ENABLE PARITY
o ~ DISABLE PARITY

DO

[NO T USED IN
AS YNCHRONOUS MODES
,--RTS

1 . EVEN PARITY

o

ODD PARITY

NOT USED IN
AS YNCHRONOUS MODES
T. ENABLE

o

0

o

1

1 STOP BIT

1

0

1.5 STOP BITS

1

1

ENABLE SYNC MODES

SE ND BREAK

0

Xl CLOCK

o

1

X16CLOCK

o

X32 CLOCK

0

Tx 5 BITS OR LESSICHAR

0

1

Tx 7 BITSICHAR

1

0

T. 6 BITSICHAR

1

1

Tx 8 BITSICHAR

2 STOP BITS

NOT USED IN ASYNCHRONOUS MODES

o

0

DT R

210311-12

DI

X64 CLOCK

210311-11

DO

DI

D3,D2
00

oI
I 0
I I

D7,D6

00
o1
I 0
I I

Parity-a one in this bit causes a parity bit
to be added to the programmed number of
data bits per character for both the transmitted and received character. If the
MPSC is programmed to receive 8 bits per
character, the parity bit is not transferred
to the microprocessor. With other receiver
character lengths, the parity bit is transferred to the microprocessor.
Even/Odd Parity-if parity is enabled, a
one in this bit causes the MPSC to transmit and expect even parity, and zero causes it to send and expect odd parity.
Stop Bits.
Selects synchronous modes.
Async mode, I stop bit/character.
Async mode, 11/ . stop bits/character.
Async mode, 2 stop bits/character.
Clock mode---selects the clock/data rate
multiplier for both the receiver and the
transmitter. If the Ix mode is selected, bit
synchronization must be done externally.
Clock rate = Data rate X 1.
Clock rate = Data rate x· 16.
Clock rate = Data rate X 32.
Clock rate = Data rate X 64.

D3

D4

D6,D5
00
o1
I 0
I I

Request to Send-a one in this bit forces
the RTS pin active (low) and zero in this
bit forces the RTS pin inactive (high).
When the RTS bit is reset in asynchronous
mode, the signal does not go inactive until
the transmitter is empty.
Transmitter Enable-a zero in this bit
forces a marking state on the transmitter
output. If this bit is set to zero during data
. or sync character transmission, the marking state is entered after the character has
been sent. If this bit is set to zero during
transmission of a CRe character, sync or
flag bits are substituted for the remainder
of the CRC bits.
Send Break-a one in this bit forces the
transmit data low. A zero in this bit allows
normal transmitter operation.
Transmit Character length.
Transmit 5 or less bits/character.
Transmit 7 bits/character.
Transmit 6 bits/character.
Transmit 8 bits/character.

Bits to be sent must be right justified, least-significant
bit first, e.g.:
D7 D6 D5 D4 D3 D2 D I DO

o 0 B5 B4 B3 B2 BI BO

2-179

Ap·134

Read Register 0 (RRO):
Msa

Inl PENDING (CHA ONLY)
L-.._ _ _

L..-_ _ _ _ _

T. BUFFER EMPTY
CARRIER DETECT

' - - - - - - - - - SYNDET
'--_ _ _ _ _ _ _ _ _ CTS

L-.._ _ _ _ _ _ _ _ _ _

EXTERNAL STATUS
INTERRUPT MODE

NOT USED IN
ASYNCHRONOUS MODES

L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ BREAK

210311-13

DO

DI

D2

D3

D4

Receive Character Available-this bit is
set when the receive FIFO contains data
and is reset when the FIFO is empty.
Interrupt Pending-This Interrupt-Pending bit is reset when an EOI command is
issued and there is no other interrupt request pending at that time. In vector
mode, this bit is set at the falling edge of
the second INTA in an INTA cycle for an
internal interrupt request. In non-vector
mode, this bit is set at the falling edge of
RD input after pointer 2 is specified. This
bit is always zero in Channel B.
Transmit Buffer Empty-This bit is set
whenever the transmit buffer is empty except when CRC characters are being sent
in a synchronous mode. This bit is reset
when the transmit buffer 'is loaded. This
bit is set after an MPSC reset.
Carrier Detect-This bit contains the state
of the CD pin at the time of the last
change of any of the External/Status bits
(CD, CTS, Sync/Hunt, Break!Abort, or
Tx Underrun/EOM). Any change of state
of the CD pin causes the CD bit to be
latched and causes an ExternaVStatus interr~ This bit indicates current state of
~he CD pin immediately following a Reset
External/Status Interrupt command. '
SYNDET-In asynchronous modes, the
operation of this bit is similar to the CD
status bit, except that it shows the state of
the SYNDET input. Any High-to-Low
transition on the SYNDET pin sets this
bit, and causes an ExternaVStatus interrupt (if enabled). The Reset ExternaV

Status Interrupt command is issued to
clear the interrupt. A Low-to-High transition clears this bit and sets the External/
Status interrupt. When the External/
Status interrupt is set by the change in
state of any other input or condition, this
bit shows the inverted state of the
SYNDET pin at time of the change. This
bit must be read immediately following a
Reset External/Status Interrupt command
to read the current state of the SYNDET
input.
'
D5

D7

2-180

Clear to Send-this bit contains the inverted state of the CTS pin at the time of
the last change of any of the External/
Status bits (CD, CTS, Sync/Hunt, Break/
Abort, or Tx Und~/EOM). Any
change of state of the CTS pin causes the
CTS bit to be latched and causes an External/Status interrupt. This bit indicates the
inverse of the current state of the CTS pin
immediately following a Reset ExternaV
Status Interrupt command.
Break-in the Asynchronous Receive
mode, this bit is set when a Break sequence (null character plus framing error)
is detected in the data stream. The External/Status interrupt, if enabled, is set
when break is detected. The interrupt
service routine must issue the Reset External/Status Interrupt command (WRO,
Command 2) to the break detection logic
so the Break sequence termination can be
recognized.

inter

AP-134

Read Register 1 (RR1):
MSB

LSB

lool~I~I~loo:~:~lool

IL~"

NT

NOT USED IN ASYNCHRONOUS MODES

PARITY ERROR
R. OVERRUN ERROR
CRC1FRAMING ERROR
NOT USED IN ASYNCHRONOUS MODES

210311-14

The Break bit is reset when the termination of the
Break sequence is detected in the incoming data stream.
The termination of the Break sequence also causes the
External/Status interrupt to be set. The Reset External/Status Interrupt command must be issued to enable
the break detection logic to look for the next Break
sequence. A single, extraneous null character is present
in the receiver after the termination of a break; it
should be read and discarded.
DO
All sent-this bit is set when all characters
have been sent. It is reset when characters
are in the transmitter. In synchronous
modes, this bit is always set.

04

Parity Error-if parity is enabled, this bit
is set for received characters whose parity
does not match the programmed sense
(Even/Odd). This bit is latched. Once an
error occurs, it remains set until the Error
Reset command is written.
Receive Overrun Error-this bit indicates
that the receive FIFO has been overloaded
by the receiver. The last character in the
FIFO is overwrittenand flagged with this
error. Once the overwritten character is
read, this error condition is latched until

05

Read Register 2 (RR2):
MSB
I V7 : V6 :
~

LSB

vs :

V4" : V3" : V2" : VI": VO"I

____________, ,____________-JJ'

"Variable In
L.;1;;.nt;.;.e;;.rru;;.:p;.;t_________ Status Affects
Vector

Vector Mode (WR1; D2)

210311-15

06

RR2

reset by the Error Reset command. If the
MPSC is in the "status affects vector"
mode, the overrun causes a Special Receive Error Vector.
Framing Error-in async modes, a one in
this bit indicates a receive framing error.
It can be reset by issuing an Error Reset
command.
Channel B

2-181

07-00

Interrupt vector--contains the interrupt
vector programmed into WR2. If the
"status affects vector" mode is selected; it
contains the modified vector. (See WR2.)
RR2 contains the modified vector for the
highest priority interrupt pending. If no
interrupts are pending, the varil!-ble bits in
the vector are set to one. May be read
from Channel B only.

inter

Ap·134

APPENDIX B
MPSC-POLLED TRANSMITIRECEIVE· CHARACTER
ROUTINES

MPSC$RX$INIT: .procedure (cmd$port,
clock$rate,stop$bits,parity$type,parity$enable,
rx$char$length,rx$enable,auto$enable,
tx$char$length,tx$enable,dtr,brk,rts) :
declare cmd$port
clock$rate
stop$bits
parity$type
parity$enable
rX$char$length
rx$enable
auto$enable
tx$char$length
tx$enable
dtr
brk
rts

output(cmd$port)=30H:

byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte;

j" channel reset "j

output(cmd$port)=l4H:
j" point to WR4 *j
j" set clock rate, stop bits, and parity information ";
output(cmd$port)=shl(clock$rate,6) or shl(stop$bits,2) or shl(parity$type,l)
or parity$enable:
output(cmd$port)=13H:
j* point to WR3 "j
j" set up receiver parameters "j
output(cmd$port)=shl(rx$char$length,6) or rx$enable or shl(auto$enable,S);
output(cmd$port)=ISH:
j" point to WRS "j
j" set up transmitter parameters "j
output(cmd$port)=shl(tx$char$length,S) or shl(tx$enable,3) or shl(dtr,7)
or shl(brk,4) or shl(rts,l);
end MPSC$RX$INIT:
210311-16

2-182

intJ

Ap·134

~IPSC$POJ.I.$RCV$CIIAHACTER:

procedure (da ta$por t, cmd$ por t, ch.u ~c t.'r Sptr) I,·,t.-·:

byte,
byte,
cmd$port
character$ptr pointer,
based character$ptr byte,
character
byte;
status

declare dataSport

declare char$avail
rcv$error

literally '1',
literally '70H':

/* wait for input character ready ./
while (input(crnd$port) and char$avail) c> 0 do: end:

/* check for errors In received character
output(crnd$port)=l;
if (status:=lnput(crnd$port) and rcv$error)
then do;
character=input(data$port) :
call RECEIVE$ERROR(crnd$port,status):
return OJ

end:
else do;
character=input(data$port) :
return OFFH:

*/
/* point to RRl */
/* read character to clear MPSC */

1* clear receiver errors

*/

/* error return - no character avail */

/* good return - character avail */

end;

end MPSC$POLL$RCV$CHARACTER;

MPSC$POLL$TRAN$CHARACTER: procedure(data$port,crnd$port,character):
declare data$port
crnd$port
character

byte,
byte,
byte;

declare tx$buffer$ernpty literally '4';

/* wait for transmitter buffer empty ~/
while not (input(crnd$port) and tx$buffer$ernpty) do: end:
/* output character */
output(data$port)=character:
end MPSC$POLL$TRAN$CHARACTER:

RECEIVE$ERROR: procedure(crnd$port,status):
declare crnd$port
status
ou tput (crnd$por t) = 3011:

byte,
byte;
/* error reset */

/ • ••• other application dependent
error processing should be placed here

*/

end RECEIVE$ERROR;
210311-17

2-183

inter

AP-134

TRANSMlT$BUFFER: procedure(buf$ptr,buf$lenqth)
declare
buf$ptr
bu f$leng th

pointer,

byte,

;* set up transmit buffer pointer and buffer length in global variables for
interrupt service */
tX$buffer$ptr=buf$ptr,
transmit$length=buf$length,
transmit$status=not$completej

output(data$port)=transmit$buffer(O) ,
transmit$index=l,

;* setup status for not complete *;
;* transmit first character *;
;* first character transmitted *;

;* wait until transmission complete or error detected *;
while transmit$status = not$complete do, end,
if transmit$status <> complete
.
then return false:
else return true;

end TRANSMIT$BUFFER,

RECElVE$BUFFER: procedure (buf$ptr,buf$length$ptr),
declare
buf$ptr
pointer,
buf$length$ptr pointer,
buf$length
based buf$length$ptr byte,

;* set up receive buffer pointer in global variable for interrupt service *;
rx$buffer$ptr=buf$ptr;
receive$index=O:

receive$status=not$complete;

;* wait until buffer received *;

;* set status to not complete *;

while receive$status = not$complete do; end;
buf$length=receive$length;
if receive$status = complete
then return true:
else return false~

end RECElVE$BUFFER,
210311-16

2-184

Ap·134

APPENDIX C
INTERRUPT-DRIVEN TRANSMIT/RECEIVE SOFTWARE

declare

/" global variables for buffer manipulation "/
pointer,
rx$buffer$ptr
/" pointer to receive buffer "/
receive$buffer based rx$buffer$ptr(l28) byte,
receive$status
byte initial (0),
/" indicates receive buffer status */
receive$index
byte,
/* current index into receive buffer */
byte,
/* length of final receive buffer */
receive$length
pointer,
tX$buffer$ptr
/" pointer to transmit buffer "/
transmit$buffer based tx$buffer$ptr(l2S) byte,
transmit$status
byte initial (0) ,
/" indicates transmit buffer status "/
byte,
/* current index into transmit buffer */
transmit$index
byte,
/* length of buffer to be transmitted */
transmit$length

cmd$port
data$port
a$cmd$port
b$cmd$port
line$feed
not$complete
complete
overrun

channel$reset
error$reset

reset$ext$status

1
1
1
1
1
1
1
1

terally
terally
terally
terally
terally
terally
teraqy
terally

'4 3H' ,
'4lH' ,
'42H' ,
'4 3H' ,
"OAH" ,

"'0"',

'OFFH',
""1"',

1 terally 'lSH',
1 terally '30H',
1 terally 'lOH',

210311-20

2-185

intJ

Ap·134

MPSC$INT$INIT: procedure (clock$rate,stop$bits,parity$type,parity$enable,
rx$char$length,rx$enable,auto$enable,
tX$char$length,tx$enable,dtr,brk,rts,
ext$en,tx$en,rx$en,stat$affects$vector,
config,priority,vector$int$mode,int$vector) ;
declare
clock$rate
stop$bits
pari ty$type
parity$enable
rX$char$length
rx$enable
auto$enable
tx$char$length
tx$enable
dtr
brk
rts
ext$en
tx$en
rx$en
stat$aff$vector
config .
priority
vector$int$mode
int$vector

byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte;

output (bScmd$port) =channel$reset;

/* 2-bit
/* 2-bit
/* I-bit
/* I-bit
/* 2-bit
/* I-bit
/* I-bit
/* 2-bit
/*'l-bit
/* I-bit
/* I-bit
/* l-bit
/* I-bit
/* l-bit
/* 2-bit
/* l-bit
/* 2-bit
/* I-bit
/* 3-bit
/* a-bit

code for clock rate divisor */
code for number of stop bits */
parity type */
parity enable */
receive character length */
receiver enable */
auto enable flag */
transmit character length */
transmitter enable */
status of DTR pin */
data link break enable */
status of RTS pin */
external/status enable */
Tx interrupt enable */
Rx interrupt enable/mode */
status affects vector flag */
system config - int/DMA */
priority flag */
interrupt mode code */
interrupt type code */

/* channel reset */

output(b$cmd$port)=14H;
/* point to WR4 */
/* set clock rate, stop bits, and parity information */
output (b$cmd$port)=shl(clock$rate,6) or shl(stop$bits,2) or shl(parity$type,l)
or parity$enable;
output (bScmdSport) =13H;
/* point to I'IR3 */
/* set up receiver parameters */
output(b$cmd$port)=shl(rx$char$length,6) or rx$enable or shl(auto$enable,5);
output (b$cmdSport)=ISH;
/* point to WRS */
/* set up transmitter parameters */
output(b$cmd$port)=shl(tx$char$lenqth,S) or shl(txSenable,3) or shl(dtr,7)
or shl(brk,4) or shl(rts,l);
output(bScmdSport)=12H;
/* set up interrupt vector */
output (b$cmd$port) =int$vector;

/* point to WR2 */

output(aScmd$port)=12H;
/* point to WR2, channel A */
/* set up interrupt modes */
output(a$cmd$port)=shl(vector$int$mode,3) or shl(priority,2) or config;
autput(b$cmdSport)=llH;
/* point to WRl */
/* set up interrupt enables */
output(b$cmdSpart)=shl(rx$en,3) or shl(statSaffSvectar,2) or shl(tx$en,l)
or ext$en:
end MPSC$INT$INIT;
210311-21

2-186

inter

AP-134

MPSC$RECEIVESCIIARACTER$INT: procedure interrupt 22H:

;* ignore input if no open buffer */
if receivc$status <> not$complete then return;
/* check for receive buffer overrun */

if receive$index = 128
then receive$status=overrunj
else do:
/* read character from MPSC and place in buffer - note that the
parity of the character must be masked off during this step if
the character is less than 8 bits (e.g., ASCII) */
receive$buffer (receive$index) ,character=input (data$port) and 7:'1l:
receive$index=receive$index+l;
/* update receive buffer index */
/* check for line feed to end line */

if character = line$feed
then do; receive$length=receive$index; receiveSstatus=completej end:

end:

end MPSC$RECElVE$CHARACTER$INT:

MPSC$TRANS~IIT$CHARACTER$INT:

procedure interrupt 20H:

/* check for more characters to transfer */

if transmit$index
then do:

<

transmit$length

/* write next character from buffer to MPSC */

output(data$port)=transmit$buffer(transmit$index) :
transmit$index=transmit$index+l:
/* update transmit buffer index */
end;
c]se transmit$status=complete;

end MPSC$TRANSMIT$CHARACTER$INT:

RECEIVE$ERROR$INT: procedure interrupt 23H:
declare
temp

byte:

output(cmd$port)=l:
receive$status=input(cmd$port) :
temp=input(data$port) :
output(cmd$port)=error$reset:

/* temporary character storage */
/* point to RRl */
/* discard character */
/* send error reset */

/* *,** other application dependent

error processing should be placed here

*** */

end RECElVE$ERROR$INT:

EXTERNAL$STATUS$CHANGE$INT: procedure interrupt 21H:
transmit$status=input(cmd$port)
output(cmd$port)=reset$ext$status:

/* input status change information *1

/* *** other application dependent
error processing should be placed here

**:to

*/

end EXTERNAL$STATUS$CHANGE$INT:
210311-19

2-187

intJ

AP-134

APPENDIX D
APPLICATION EXAMPLE USING SDK-86
This application example shows the 8274 in a simple
iAPX-86/88 system. The 8274 controls two separate
asynchronous channels using its internal interrupt controller to request all data transfers. The 8274 driver
software is described which transmits and receives data
buffers provided by the CPU. Also, status registers are
maintained in system memory to allow the CPU to
monitor progress of the buffers and error conditions.

THE HARDWARE INTERFACE
Nothing could be easier than the hardware design of an
interrupt-driven 8274 system. Simply connect the data
bus lines, a few bus control lines, supply a timing clock
for baud rate and, voila, it's done! For this example, the
ubiquitous SDK-86 is used as the host CPU system.
The 8274 interface is constructed on the wire-wrap area
provided. While discussing the hardware interface,
please refer to Diagram I.
Placing the 8274 on the lower 8 bits of the 8086 data
bus allows byte-wide data transfers at even I/O addresses. For simplicity, the 8274's CS input is generated
by combining the M/IO select line with address line A7
via a 7432. This places the 8274 address range in multiple spots within the 8086 I/O address space. (While
fine for this example, a more complete address decoding is recommended for actual prototype systems.) The
8086's Al and A2 address lines are connected to the AO
and Al 8274 register select inputs- respectively. Although other port assignments are possible because of
the overlapping address spaces, the folloWing VO port
assignments are used in this example:

Port Function

I/O Address

Data channel A
Command/status A
Data channel B
Command/status B

OOOOH
0002H
0004H
0006H

To connect the 8274's interrupt controller into the system an inverter and pull-up resistor are needed to convert the 8274's active-low, interrupt-request output,
INT, into the correct polarity for the 8086's INTR interrupt input. The 8274 recognizes interrupt-acknowledge bus cycles by connecting the INTA (INTerrupt
Acknowledge) lines of the 8274 and 8086 together.

The 8274 ReaD and WRite lines directly connect to the
respective 8086 lines. The RESET line requires an inverter. The system clock for the 8274 is provided by the
PCLK (peripheral clock) output of the 8284A clock
generator.
On the 8274's serial side, traditional 1488 and 1489 RS232 drivers and receivers are used for the serial interface. The onboard baud rate generator supplies the
channel baud rate timing. In this example, both sides of
both channels operate at the same baud rate although
this certainly is not a requirement. (On the SDK-86,
the baud rate selection is hard-wired thru jumpers. A
more flexible approach would be to incorporate an
8253 Programmable Interval Timer to allow softwareconfigurable baud rate selection.)
That's all there is to it. This hardware interface is completely general-purpose and supports all of the 8274
features except the DMA data transfer mode which requires an external DMA controller. Now let's look at
the software interface.

SOFTWARE INTERFACE
In this example, it is assumed that the 8086 has better
things to do rather than continuously run a serial channel. Presenting the software as a group of callable procedures lets the designer include them in the main body
of another program. The interrupt-driven data transfers
give the effect that the serial channels are handled in
the background while the main program is executing in
the foreground. There are five basic procedures: a serial
channel initialization routine and buffer handling routines for the transmit and receive data buffers of each·
channel. Appendix D-l shows the entire software listing. Listing line numbers are referenced as each major'
routing is discussed.
The channel initialization routine (INITIAL 8274),
starting with line #203, simply sets each channel into a
particular operating mode by loading the command
registers of the 8274. In normal operation, once these
registers are loaded, they are rarely changed. (Although
this example assumes a simple asynchronous operating
mode, the concept is easily extended for the byte- and
bit-synchronous modes.)

2-188

(
CONTROL
LINES
CONNECTOR

ADDRESS
BUS EXPANSION
CONNECTOR

»
"P
....

~

(Xl

co

I

(.0)
~

EXPANSION EXPANSION

SOCKET
BAUD RATE
GENERATOR

I

SOCKET

•

IL'T'""~_""'"

LED DISPLAY

210311-22
(For detailed description on SDK-B6. refer to SDK-B6 MCS-86 System Design Kit Assembly Manual.)

inter

AP-134

SDK·86
EXPANSION
BUS

22

Rii
WR

PClK

48

21'

SO

27

04

Rii

RTSA

WR

RxDA

CoA

RESET

14

13

12

14

10

15
16

03

17

02

18

01

19

DO

23

MilO

DB7

DTRA

oB6
oB5

751489
8274
TxoB

DB4
RTSB

DB3
oB2

RxDfI

OBI

CTSB

CHANNEL

B

DBa
COB
CS
DTRB

A7
25

Al
A2

CHANNEL
A

INTA
ClK

12

07

OS

TxDA
INT

CTSA

36

RST

06

751488

40
VCC
28

INTR

INTA

SV

8

24

AO

TxCA

Al

RxCA
TxCB

210311-23

Figure 0-1. 8274/S0K-86 Hardware Interface

The channel operating modes are contained in two tables starting with line # 163. As the 8274 has only one
command register per channel, the remaining seven
registers are loaded indirectly through the WRO (Write
Register 0) register. The first byte of each table entry is
the register pointer value which is loaded into WRO
and the second byte is the value for that particular register.
The indicated modes set the 8274 for asynchronous operation with data characters 8 bits long, no parity, and
2 stop bits. An XI6 baud rate clock is assumed. Also
selected is the "interrupt on all RX character" mode
with a variable interrupt vector compatible with the
8086/8088. The transmitters are enabled and all model
control lines are put in their active state.

In addition to initializing the 8274, this routine also sets
up the appropriate interrupt vectors. The 8086 assumes
the first lK bytes of memory contain up to 256 separate
interrupt vectors. On the SDK-86 the initial 2K bytes
of memory is RAM and therefore must be initialized
with the appropriate vectors. (In a prototype system,
this initial memory is probably ROM, thus the vector
set-up is not needed.) The 8274 supplies up to eight
different interrupt vectors. These vectors are developed
from internal conditions such as data requests, status
changes, or error conditions for each channel. The initialization routine arbitrarily assumes that the initial
8274 vector corresponds to 8086 vector location 80H
(memory location 200H). This choice is arbitrary since
the 8274 initial vector location is programmable.

2-190

AP-134

Finally, the initialization routine sets up the status and
flag in RAM. The meaning and use of these locations
are discussed later.
Following the initialization routine are those for the
transmit commands (starting with line # 268). These
commands assume that the host CPU has initialized the
publicly declared variables for the transmit buffer
pointer, TX_POINTER_CHx, and the buffer length,
TX_LENGTH_CHx. The transmit command routines simply clear the transmitter empty flag, TX EMPTY CHx, and load the first character of the buffer into
the transmitter. It is necessary to load the first character in this manner since transmitter interrupts are generated only when the 8274's transmit data buffer becomes empty. It is the act of becoming empty which
generates the interrupt not simply the buffer being empty, thus the transmitter needs one character to start.
The host CPU can monitor the transmitter empty flag,
TX_EMPTY_CHx, in order to determine when
transmission of the buffer is complete. Obviously, the
CPU should only call the command routine after first
checking that the empty flag is set.
After returning to the main program, all transmitter
data transfers are handled via the transmitter-interrupt
service routines starting at lines # 360 and # 443. These
routines start by issuing an End-Of-Interrupt command
to the 8274. (This command resets the internal-interrupt controller logic of the 8274 for this particular vector and opens the logic for other internal interrupt requests. The routines next check the length count. If the
buffer is completely transmitted, the transmitter empty
flag, TX_EMPTY_CHx, is set and a command is
issued to the 8274 to reset its interrupt line. Assuming
that the buffer is not completely transmitted, the next
character is output to the transmitter. In either case, an
interrupt return is executed to return to the main CPU
program.
The receiver' commands start at line # 314. Like the
transmit commands, it is assumed that the CPU has
initialized the receive-buffer-pointer public variable,
RX_POINTER_CHx. This variable points to the
first location in an empty receive buffer. The command
routines clear the receiver ready flag, RX_READY_
CHx, and then set the receiver enable bit in the 8274
WR3 register. With the receiver now enabled, any received characters are placed in the receive buffer using
interrupt-driven data transfers.

2-191

The received data service routines, starting at lines
# 402 and # 485, simply place the received character in
the buffer after first issuing the EO! command. The
character is then compared to an ASCII CR. An ASCII CR causes the routine to set the receiver ready flag,
RX_READY _CHx, and to disable the receiver. The
CPU can interrogate this flag to determine when the
buffer contains a new line of data. The receive buffer
pointer, RX_POINTER_CHx, points to the last received character and the receive counter, RX_COUNTER_CHx, contains the length.
That completes our discussion of the command routines and their associated interrupt service routines. Although not used by the commands, two additional service routines are included for completeness. These routines handle the error and status-change interrupt vectors.
The error service routines, starting at lines #427 and
# 510, are vectored to if a special receive condition is
detected by the 8274. These special receive conditions
include parity, receiver overrun, and framing errors.
When this vector is generated, the error condition is
indicated in RRI (Read Register I). The error service
routine issues an EOI command, reads RRI and places
it in the ERROR_MSG_CHx variable, and then issues a reset error command to the 8274. The CPU can
monitor the error message location to detect error conditions. The designer, of course, can supply his own
error service routine.
Similarly, the status-change routines (starting lines
#386 and #469) are initiated by a change in the modem-control status lines CTS/, CD/, or SYNDET/.
(Note that WR2 bit 0 controls whether the 8274 generates interrupts based upon changes in these lines. Our
WR2 parameter is such that the 8274 is programmed to
ignore changes for these inputs.) The service routines
simply read RRO, place its contents in the ST A TUS_
MSG_CHx variable and then issue a reset external
status command. Read Register 0 contains the state of
the modem inputs at the point of the last change.
Well, that's it. This application example has presented
useful, albeit very simple, routines showing how the
8274 might be used to transmit and receive buffers using an asynchronous serial format. Extensions for byteor bit-synchronous formats would require no hardware
changes due to the highly programmable nature of the
8274's serial formats.

AP-134

8274 APPLICATION BRIEF PROGRAM
ISIS-II 11:5-86 I1ACRO ASSEltllLEF V2 1 ASSEI'BlV IF IW..tE ASYOCB
OBJECT IIJIlIA.E PLfUD IN Fl.AS'/N(B OBJ'
ASSEI1BLEF INI'(l(ED IN _
Fl AS'III(B SFC

LOC 08J

LINE

, ....
1

2

4
5

6
7
B
9

19
11
12
13

14
1~

16
17
18
19
29
21
22
2l
24
~

26
27
28
29
38

.

, . . . . . . . . . .fM ................................................. . .

.•

9274 fl'PtlCATlm Bl!IEf _

.

"
"
"
"
,.
"
"

11£ 8274 IS INITIALIZ£O FBI! SIIRE AS'rIDROOJS SERIAL
FIRI'IIT fIf) VECTMED INTERRlJPH>RIVEN DATA WINSFERS.
THE INITIALI1RTIm ROOTINE ALSO LOIf)5 THE 8B86'S INTERRIJ'T
VECTBI! TIIILE FRIll THE COO£ SEMNT INTO LOW RIll m THE
5Di(-86. TI£ TmEltITTEF fIf) RECEIVER ARE LEFT ENfIItEI).

;'
"
"
"

THE CPU PllSSES IN I'IElDV TI£ POINTER IF A
IIlFFER TO TRtIISItIT fIf) THE BYTE LEI«lTH IF THE IIlFFER. '
TI£ DATA TRIIfSFER PROCEED USING INTERRII'T-IlRIVEN TRIIfSFERS,
A STATUS BIT IN 1£101' IS SET II£N IF IIlFFERS IS E/FTV,

;' FIM! TmEltIT,

" FBI! RECEIVE. THE CPU PASSES TI£ POINTER IF A IIlFFER TO FILL, •
;'
;' THE IIlFFER IS FILLED lWTlL A 'CR_CII!' CllM:TER IS RECEIVEO, •
;' A STATUS BIT IS SET fIf) TI£ CPU I1fIII READ THE Rl( POINTER TO •
" DETERltll£ THE LOCATlm OF THE LAST ClRft::TER,

"
;"ALL
ROOTII£S ARE ASSIJIED TO EXIST IN THE SRI£ COO£ SEMNT.' •
;' au '5 TO THE SERVICE ROOTINE~ ARE RSSIJIED TO BE 'SIfJRT' OR •
• INTRRSWENT (mLY TI£ RElWI fIlDRESS IP IS m THE STACK),

'*.. ......

........................***..........................

2-192

210311-24

Ap·134

1IC5-1J1.i

Ift:RQ

LOC OOJ

ASSEIIIlER

RSYI(8

LINE
11
J2
33
34
35
36
37
18
39
49
41
42
43
44
45
46
47
4B
49
51!
51
52
53
54
55
56
57
58
59
68
61

5tI.m:
/fIlE

,PUllLIC

ASII«:B ,IUIlI.E NfI1E

DECL~TIOOS

PL6!.IC
PUllLIC
PUllLIC
PUllLIC
PUllLIC

FOR COItIfH) ROUTINES

INITIfL-B274
TX-CIJI'IINLCNB
TX-Cll'ltfHUJIA
Rx...CIIItItAII)_CIIl
RX_COIl1fHWIA

, INITIlllZATIOO ROOTINE
, IX BLfFER CIlltlAND CHAIilEL
, IX BLfFER COIt1fIN() C!mil
,RX BLfFER ctIItIfINI) CNANI£L
,RX BLfFER (0_ UifIflEL

B
A
B
A

; PleLlC DECLfRlTIONS FOR STATUS YfRIABlES
PUllLIC
PUllLIC
PUBLIC
PUllLIC
PL6!.IC
PUllLIC
PUllLIC
PUBLIC
PUBLIC
PL6!.IC

PlLREfilY_CNB
~X-REflO'''-CHA

Tx...EIt'TUHB
Tx...EIf'TY_CHA
Rx...ctX.IlT_CHB
Rx...COl.IlI-CHA
ERROR..IISG..CNB
EI1RtlR..I!SG_CHR
STATUSJISG_CHB
STATUS_HSG_CHR

,~X REAllY FLAIl (Ie
,R't READY FLAIl CIIA
, IX El1PTV FLAIl CIIB
, TX EtI'TY FLPIl CHA
,RX BUFFER COl.tHE~ CHB
,RX BLfFER COONTER CHA
,ERROR FLAG CHB
,EJ1R(ll FLAG CHA
,STATUS FLAIl CHB
,STATUS FLPIl eHA

; PUllLIC DECLARRTIOOS FOP VARIABLES PASSED TO TI£ TRfflSHIT
,IN) RECEIVE COII'iN)S.
PlRIC
PlRIC
PUllLIC
PUllLIC
PUllLIC
PlRIC

62

63

IX_POINTER-CHB
Tx...LEI«iTILCHB
TX-POINTER-CIIA
Tx...LEI«iTH_CHA
Rx...POINTEILCNB
Rx...POINTEP_CIIA

' TX 81.1'FEP
•TX LEI~TH
, TX BUFFER
' TX LEI«iTH
.I/X Bl.fFEP
,PX BLfFER

POINTER FOR (HB
OF BUFFER FOR Cill
POINTER FOP (HA
OF BUFFEF FOP OIA
PO INTER FOR (HB
POINTEF FOP ellA

64

B&eIJ
99!l2
9002

9984

65
66
67
6B
69
79

71
72
73
74
75
7.

9ee6

77

9200

78·
i9
89
St
82

9500

8)

; 110 PORT AS5lGIf£NTS
,CIflNNEL A PORT ASSIIlIftENTS
tlATA_PORI-CHA
Ill'ItfH)J>OI1T_CHA
STATUS~T _CHA

0
2
ta91IH'_POPUHA

. MTA liO POPT
,COPIIANO PIlI'T
,STATUS PORT

[(OJ

4

Eoo
E(lIJ

6

,toATA 1.'0 POPT
,CIlII1AH!' PIlRT
,STAfl.IS PIlI'T

OCoH

.A5(11 (~ (HAI'ACTEP (O['E
• INT \{(TI)< BASE A[HES:.
,STAPT LOCATION Ftjl (O[f

EflU
EflU
EOO

,CIfHlEL B PORT A5SIGII1ENTS
DATA-PCl1UHB
COItfH>_PORUHB
STATUS_PORT..I:HB

COI'/IAI{o_PIlRT_CIIl

,HIS[ SY5TEIt EfllIATES
CP_CllR

EOI.I

INY-TltRLBASE EOO
COOLSTAFT
Eoo

2~

500H

84
8S +1 IEJECT
86
a, ,m1 ASSSIIlNHENTS FOP DATA SEGMENT

88
(!9

I·ATA

;EGHENT

91!

210311-25

2-193

intJ

AP-134

K:S-So; tilCl1\I ASSEKelER

RSI'lK8

LOt OSJ

L1HE
~1

92
?3
~4

SOUP(E
,!/ECTOP INTERI'UPT TABlE - ASSUME /lIITIA\. s'174 IHTEPPI.lPT
,!/E(1OP IS NltI6EP 00 ,@"OOH', FOf E~H ','EOOf, THE TABLE
,CONTIlINS STAPT LOCATION I'/l' (CI!oE SEij~ENT PEr,I5Tl' VALUE
,THE TABLE IS L(IfI[,E[, FP(,M PF'OM

9'j

021le

%

0298_
02Il2_
0204 0008
Il296 0000

0200_
020A 0000
029C _
020E_
0210_
0212_
0214_
0216_
0218_
021A _
S21C _
021E _

-,q~

!j!I

198
101
102
183
104

las

106
107
100
Ie!'
119

111
112
113
114
liS
116
117

119
126
121
122

8224 _
0226 _
022898
8229 00
II22A 98
0228 00

1l22C_
022E eeee
Il238 eeee

0232_
0234
0235
8236
1Ill?

00
00
98
00

124
125
126
127
128
129
138
131

m
iI'S
134
135
E6
137

BB
B~

140
141
142
143

144

INUABILBASE
,T:: INTEP",!'T YECTOf FOP eNS

ON
[~

STS_VE(j()J1_CHB ON
STS_CS_CHS
DI<

,STATUS IHTEmn 'IECTeI' FOP eNS

RlLYECTll1_CHe
I1X_CS_CHB

,P:': IHTEPP'-I'T. IE Tel' FQP (NS

OW

ow

ERR_!/ECHI'_CHS ow
ERR_CS_CHe
DI<

,E!>POP IHTEl'PUPT l/ECTDP F,JP CNS

TU'ECTll1_CH!l
T,-CS_CHA

,TX INTEPRUPT VECTOP FOP (HA

OW
ON

STS_YECTIJLCHR [>W
STS_CS_ClIl
ON

,STATUS INTERRI.I'T !/E(TOP FOP (HA

RlL YECTOUHA
PUS_ClIl

,11X INTEPJ1UPT YECTeI' FOP (NA

liB

m
0220_
8222 _

0116

TUETOIUHB
TUS_eHe

[~

ow

ERR_YECTOR..CHA ow
ERR_CS_CIIA
ON

• ,EIIro> INTERRUPT I/ECTll1 FOP eHA

, "ISC I1fI1 LOCRTIOHS FOP CHANl£L STATUS 1M, POINTEPS
,CHRNIf:L B POINTERS RHO STATUS
TX_POINTER_CHe .w
TUEM;TH_CHe ow
I1X_POINTER_CHB ow
RUOIJNUHB
ON
TX_EllPTY_CHS
os
RlLREfIlY_CHB
os
STATUS_HSG_CH8 os
ERRORJ1SG_CH8 ll!I

8

e
e

B

e
e

B

e

,T"
' TX
,PX
,PX

BUFFER POINTEII FOP (He
BUFFEP LENGTH FC4' CHS
BI.lFFEP POINTEI' FOP [HS
LENGTH WJNTEP FOF eHS
, r. .: DONE FLAt:I
,PEf'DY FLA!, '1 IF (P_(HF PE(EIVE[', ELSE 0,
,STATUS CHANGE IlESSA6E
,ERI'OP STATUS LOCATIOO 'e IF NO EFPeI",

,CIft1NNEL A PO INTEl'S fINO STRTUS
TX_POIHTEF_CHA ON
TUENGTH_CHA ow
I1X_POINTEP_CHA ow
PlLCOUNUHA
ow
TlLEllPTY_CIfl
DEI
RlLREAOY-CHA
os
STATUSJl5(j_CHA os
ERROP_I1SG_CIfl os

' TX BUFFEP POIHTEP FOP CNA
' T:: BUFFEP LENGTH FOP (NA
,PX BlfFEP POIHTER FOP [HA
, PX lEl';TH COOJNm" FOR ,:HA
,TX [M FLAG
,PEfI)Y FLAG (I IF (P_CHP PEcmn, ELSE 0
,STATUS CHANGE I1ESSA6E
,EPFOR STRR'S L(~ATlON ". IF IlO mop,

145

DATA
146
147
148 +1 I£JECT

ENOS

210311-26

2-194

inter
~ICS-80 H~O

LOC OBI

AP-134

fiS:il1BlEF

ASYNCB

LINE

SC WPi NOT FECJlJIFE[' FOP AS'IN(
9.8

C14AHNEL A PAFRKETEFS

•WIll - WTEFRIJPT 011 ALL
C/Il\STFA DB
1.12H

P:~

Oil'. T:·: [NT EHABLE

179

.1111~

100

DB

181

182

.WR' - I1X 8 BlTSlINF. PX [.ISABLE
DB
J. OCI!H

183
184

.l1li4 - X16 wx:r. 2 ,Teo BITS. NO PRPITI'
DB
4.4CH

- YECTI*ED INTEWtfT FOF 8886
2.31!H

18'5

.III/S - ['TF A\TlVE. IX e BITS/CHP. rl. EHft ...... ,

195
196

".t

197

"
. ,*

m

19S
L"9
200

m

..

IHITIFlIZATlOO CO_ FOR THE 82;4 - THE 8174
IS SETlP OCCOl1!>ING TO THE PftI'AltETEFS STOI'EV IH
PFOIf ABO'.{ STAI'T1HO AT CHSTPI! F~ (HAMlEL • AII(.
CPlSTRA FOP OIfHEL A

.**....................................u ..............................u ........................

292

0516

26J

0518C79609Il26866
eS1E 1lC9E8282
0522 C7_3596
0528 1lC9E8682
952CC_4995
8532 1lC9E!1A82
853'; C795OC82m6
9S3C 9CeE8f192
8548 C79619828C95
8S46 9C8Ei2e2
9:i4Il C786141l2B996
esse 9C8E1682
!1554 C7861982CD86
85SA BC8E1A82
95SE C7951Ce2F99.
9564 9C8E1E82

9568 BF9995

9568
8S6E
8571
8574
8577

M9698
ES2EE18
BF9C8S

IIA828e
E82588

057A98E18E18
8570
_ II22B82
A2l782
8S83 A22A82
8S86 A2l682
8589 Rl2682

esse Al3282
8SBF Beel
8591 1122982

8594 R23582

8597
859A
8590
859E

A228Il2
A23482
FB
C3

859F 8A8S
8SA1 lC88
esAl 7484

264
2'l5
266
287
298
289
219
211
212
21,
214
215
216
217
219
219
228
221
222

m

224
22S
226

227
228
229
239
231
232
233
214
2lS
236
237
238

m

248
241
242
243
244
245
246
247
248
249
2S8

INITIAU274
•CIl'Y IHTERRtf'T VECTOP IP fH> CS VALUES
11)'/
TllVECTOR-CHB, OFFSET XI1T1118
11)'/
TllCS.i1I8, CS
lIlY
STS-VECTOI"-CHB. OFFSET STAlhlI
STS_CS_CIl!. CS
lIlY
lIlY
RllVECTOIUHB, OFFSET RCVlle
11)'/
RllCS_CHB, CS
lIlY
ERR_VECTOIUIl8, OFFSET ERRI!e
PX_CS_CNB, CS
lIlY
lIlY
TllVECTOIUHA, OFFSET XPlTIHA
TllCS_CltfI, CS
lIlY
lIlY
STS_VECTOP_CIf!. OFFSET STAIHA
lIlY
STS_CUHA, C5
lIlY
RllVECTOP_CIIA. OFFSET RC'IINA
RllCS_CltfI, CS
lIlY
lIlY
ERR..VECTl11_CHA. OFFSET ERRIIIA
ERR_CS_CHA. CS
lIlY

F~OI1

PRON TO PAI1
· l:~ MTA VE[lOF' CHB
· SIATlJS VEm", (HB
· RX DATA VEC TOR CHe
•ERROl' VE(!OIl CHB
· TX MTA VEC TOP Clifl

•STATUS VECTOR CHA
,PX MTA VECTOP CIIA
· EPROP VECTOR (HA

,Ctf'I SETlP TA8I.E _TEPS IHTO 82;4
tIOV
lIlY
CIlL
IfJ'/

lIlY
CIlL

01, OFFSET OI>STR8
OX, COIfItfIHO_POPLCII!
SETUP
01, OFFSET CItlSTIIR
Ox, COIfItfIHOJ'Of'UHA
SETlP

,INITJFlI2E STATUS MES
IfJ'/

/tOY
/tOY
lIlY
NlY

lIlY
IIOV
IIOV

/tOY
IfJ'/

/tOY
IIOV

ClIP
JE

Fl, lOll
Fl, 8
OOOE

,COPY (I'B PARAI£TERS
.IHITIIlIZE Ch!\
,copy CHA _TEllS

FLAGS

AX. 8
ERROP_ItSG.-CII!, Fl
ERROPJISGJ,II, Fl
STATUS_I\S6_CII!, Il
STATUS_IISG_OO Fl
RlLClUILCH8, AX
RlLCOONT_OO A:<
Ill, 1
RK-REAI''-CII!, Fl
RX..REfIlIY_CHA, Fl
Tx..EIIPTY-CHII, At
TX..EII'TV_CltfI, Fl

STI
RET
SETlP' /tOY

AI{)

, IHITJIlIZE CNB

· CLEAR
· CLEAR
· CLEAP
· CLEAR
,CLEAP
,ClEAP
,SET
,SET
· SET
•SET

ERPOP FLAG (II!
EiIFOP FLAG elf!
STATIJS FLAG CHe
STATUS FLAG CIIA
R:~ COUHT~ CHI!
PX cruffER CHA

I>X
RX
r,
T,

OOOE FLAG CHe
DON: FLAG CNA

OOOE FLAG CII!
OOOE FLAG CNA
,ENA8I.E IHTERPlPTS
· RETtPII - OONE HITH SETUP
,PAPrtETEiI Ctf'IING i1OUTJr£

210311-28

2-196

intJ
LOC 08.1

e5f\5 EE
1l5A64:
e5A7 EBFr5
acJA? c]

AP-134

LINE

SW~fE

251

OJT

[,:~.

2'52

IH(
JI1P

[,I

,POINT AT

5ET'-~

.ljI)

2Sj
2:~

00tIE

it

.(lJ.lTPtJT

~ET

·rl(~

255
256 t1

257
258
259
'268
261
262
26j
264

265

Pt1~'Hf1ETEF
N£~:T

PfV:i1MEiEF

lOtto Ii

-

SO

~'ETlJF'~j

IE.lECT
.•uu ................................. u .... "............. >tu ................... t.u.t.
, ..
,.
1:-: C_L B C_, 1<1:~ITII£ - ~[1I-'TWE IS (fUEl' TO
,.
TFffl5lt1T A BLHER HE E_CHB

269

292

,.
"
,.

.'

VX
['I

A:,

TX OfllHI A COHltAN(l ROl~IJE - R(l'-~INE IS CALLE[' TO
TRPHSHIT A BlfFEF Tf( .1HER STAPTU., AlH'ESI,
r,,_POIHTER_CHA, fflD THE BIJFFEF LEH(;TH, TUEI(;THJHA.
II-,ST BE INIlIALI<:ED ~I THE (ALLING PI<1:~"':AI1
BOTH ITEH5 ARE WORt· 'IARIABLE5

"• ..........,...................................... 1- .............. ,. .......... u.t
Ti:_COIflINIUffi

e:;(B 51J

29~

F'USH

A:~

BSC157

294

DI

8"J:F8IIe5
I!5Vl EE

29~

PUSH
PUSH
/lOy
I10Y
I'IOV
1'10'1

300

OUT

DX, fl

B5D2 :il

)Ill

e5!>4 SB
B5b5 (3

POI'
POP
POP
FET

r'i:

302
302
304

9SC2 52

295

85(3 (606149200
95C9_
Il5C8 8BjE2CB2

2~i'

e....,J Sf

296

m

305
]£16
39T
JOO
]99

319

,SAVE

~EljISTEPS

v:':
T:UHPTY_CHA,. ,CLEAP EI\OT',' FLA<.;
rflTR_PORLCHA
,;EH.I' PC~T POIIHEP
[,I, T:UOINTER_CHA
,GET TX BIJFFER POINTEP (HA
AL. [N!
,GET Fir;";T CHAHlCTEP TOT:,:

t·:"

,t)JTPIJT IT TO 8274 HI r.!T IT STRPiEf,

~I

IV:
,PETI."H

, ................ ,...... ** ........:u ................... t."t:u.~ ........... U;.t, .... +
...
•,
/IX CO/ltllN, FOF Clff
1!';E6
B5E8
B5E9
8l£B
B5EC
8l£D
85EE

31,
114

59
S2
00!62m00
C;86.268_
8A868e
B003
EE
SOC1
EE
5A

~15

PUSH

A:·:

,16
317

I'USH
HOY
HOY
HOY
HOY

l'X

m

)19
328
321
;22
324
325

CJ

326

)27
;28
329
ne
;31
332

m

:;34
335
336
137
338

POP

. I1ET

359
368
361
362
363
364

365
366

.,

.'.,
.'.,

RX COIIIfII(l FOP CHANI£L A - THE (ALllllG PCfJTINE ~U5T
INITIALIZE PX_POINTEF_CHA TO POlllT AT TriE PEo:tIVE
BUFFEP B£fOl1E CALLING THIS POUTINE

.............................................. "' ..........., ... ttuu''''*Ut .................

RlLCCI1IfH)_CHfI
PUSH

PlISH
1111
HOY
HOY

I'0O\I

OUT

HOI'
OUT
POP
POP

fl·:
· SfIIE PEGISTEPS
OX
RX-P£ADY-CHA. e . (LEAP PX REAC'V FUI(j
~UOUHUHA. 8 . (LEAP PX COUNTER
OX, ea1MIM)_POPUHA
.PQIIIT AT CC!l'lftN[l POPT
AI.. )
. SET UP FOI'~,
~X. AI.
AL iC1H
·WP: - 8 B.IT~ 'CliP. ENABLE Pc'
DX, AL
OX
f!);

RET

·PETtIIN

+1 IEJECT

,.**.......***..........*.*•• "'..........u.**"'*.uu .................... u ............ 4
"

SIfRT OF

.'" -

INTE~RUPT

SEII'II(£

~II£S

.

i .........................................................................u ..... to

,ChIIfEl. B TRfr6MIT DATR SEII'IICE POUlIN[
~TI~

PUSH

PUSH
PUSH
CALL
If«:

DEC

861B 883E2002

368

JE
HOY
HOY

861f BAB5
8621 EE

369
378

HOI'
OOT

367

.I'ET~

,....."'**.........."'.....** ............................ u.·... t ..................... +.

346
347
348
349

~

B68E FF862002
8m FFeE2292
8616 74BE
8618_

OUT
POP

14Il
341
342
J4)
144
345

351
lS2
3';3
lS4
355
JS6
357
868852
1lt>B957
_59
_
E892e1

em

m

J'j8

· SfIIE i1[GISTEPS

9 . (LEAP P": PEf(oV FLHIj
"K.COl~LCHf!. 9 . cLEI1P f'X CO~TEP
OX. C!H1f1h1),f1)I1UHB
. PQINT NT ';,JI'MAI1{· F('PT
AL. 3
· SET UP Fill' fI>:
~X. AL
AI.. eelH
·WI', - 8 BITS. ~HP. ENABLE P>:
DX. AI.
0,
AX
~X_~E~UIll·

I'0O\I

;2;

sa

B5EF
I!';EF 59
W8 52
WI C686J59200
W6 'C71lt>3292B008
85FC BAB2e9
8SFF Bee)
Ilt>Bl EE
Ilt>B2 secl
B684EE
e.;es 5A
8686 sa
1lt>B7 C3

U."' .. .t:U"h.U· .......... U"' .. tt++•• U.~.H.+Uff·HIU ...... t .. +.'.'Ulh

PX_COtll1/K·j)i!I

~x
.SAI'E I1EGISTEFS
01
AX
· 5E~ EOI CO __ TO 82,'
EOI
TX_POINTEILM · POINT TO NEXT CH~ACTEP
TILLEOOnUNB · [lfe lEOOTH CDUNTER
XIB
· TEST IF 0CJIf'
OX. DATA-POF!UH8
.I«IT (o(Q; - (£T NEXT (HAPf!CTEP
0(. TX-POINTEP_ChII
AL. (DIl
· PUT CIfllACITR IN Al
OX. AL
· OUTPUT IT TO 82,4

210311-30

2-198

inter

AP-134

1£5-86 I'iUO ASSfI'iBlER

ASYI«:S

LOC OOJ

LINE

8622
9623
8624
9625
8626
8629
8618
862C
8631
8632
8633
8634

58
51'
sa
CF
IIA868II
B828
EE
C6862BB281
58
51'
sa
CF

SOUlCE

J71
372
373
374
375
376
377
378
379
388
381
382
383
3B4

POP
POP
POP

XIS.

IRET
/tOIl

AX

.RESTIJIlE REGISTEIIS

01
DX

I10Y

,RETI.I1N TO FOREGROOND
OX. CMRf)_~LCIi!I
• ALL CII'lPKTERS HAYE BEElI SEND
At. 2BN
· ~ESET TRANSIUTTE~ IHTERI1UPT PEl{llfI/j

WI

DX. RL

I10Y

TllEtfTY-CtIl. I . 00f: - SO SET TX ElIPTY Fllll CItS
AX
· RESTORE FEGISTEFS.
01

POP
POP
POP
IRET

OX

· FE~ TO FIlPEGFC'.'I{I

• ClRt£L S STATUS CIIfIIa SERVltE ROUTINE

3B5
B63'552

8636
8637
B63B
9638
863E
B63F
8642
8644

57
59
EBDSBB
BR9688
EC
A22A02
Bel9
EE
804~ 58
9646 51'
8647 sa
0648 IF

8649
864A
864B
864C
864F

52
57
58
E&100
BelC482

e653 8A9400
Il656 EC
865~ IlOO5
\10559 FF862402
005(' FF86268Z
0661,(00

386
387

3B9
3B9
399

STAINS· PUSH
PUSH
PUSH
CRI.l
I10Y

391

194

IN
IfJV
lillY
WI

395

POP

3%

POP

m

393

m

POP

398
;99

lPET

499
491
492
493
404
485
486
407
400
489
410
411

IIO¥
tIO'I

IN
HOY
IIle
Iff:
[tIP

;'5eE

m

,HE

!l6b5 (686<90201
\lo56ASA0600
8661. B003
866F EE
8670 Bet8
"..2 EE
867; 58
86~4 SF

414
415
41"

MOV

~OY

I10V
I1JT
HOY

m

418
419
42(j
421

OI)T

RIB

FUI'
POP

06;'5 SA

m

POF'

8676 CF

4.,

1Ft.

424
4i5
4::15
%j~

52

4"

EOI
; SEND EOI COIMlI> TO 8274
OX. CO/IIfH)_PORT _tItS
.REf[, RR0
AL. OX
STATUS_H5G..CIiI. At
· PUT RF0 IN STATUS I'iS51G:
At. lell
· SEI(> PESET STATUS INT COMMfiHC' TO 8m
DX. RL

AX
DI
DX

· RESTIlPE PEGISTEPS

96j$ 50

4Z~

(1I5j~ ES~4eo

42~

(ALL

0O;e MOi<10

43e

tV.1!

· 5AI~ I1EGISTEFS

DX

vi

Al:

EOI
· seN{> EOI COIf1AHC1 TO 82~4
01. R)UOINTEUHB
· GET F:, CHS ~J.HEF POINTEP
VX. DATA-POPUHB
At. DX
· ,EAI' (HAfIft(TEP
lOll. RI.
· STOPE IN BUFFEP

RX_POINTEF _INS · BUPIP THE B'flEP FOIIIT,P
FllrOllNT _IHS
· B'.tIP THE (QI.IlTE'
fl. Cfl_CHF
· TEST IF LAST [HAP~CTEF TO BE 'Em··jEI,'
RI8
Ri._fEAI·Y-CH5. 1 . rES. SET ~EAI'\' FLAG
DX. (OIII\fIII'_POFLCiii
.tljINTAl (~!I)P(lPi
AL. ,
· POWT AT HP,
r·x. At
At. OCell
.[·ISABLE i1'A
[.~. At
A>:
.EITHEP HAV. ~ESTOPE PE';!'TEP,.
~I
v:~

· F'ETL~'N TO

· CHflI'I£L £ ERFOP 3EFVI(E
EPPlllF Fi-"'.H
PUSH

"

•SAVE REGISTERS

AX

· rlfHEl. B RECEIVED MIA SEI1\IICE FOIJTlNE
PeVIHS PUSH
PUSH
PUSH
tALL

412

86tj]

OX
DI

~1)FE,pOIJNr,

F~JTlNE

I':,
· 511'",£ PE6ISTePS
NA
HI
· 5fl~' tOT (O'''HAU(' TO
I·::· ':'lMI1fiI.·_'O,jJHE

2-199

S2,~4

210311-31

inter

AP-134

PlCS-% IR:RO A5SE111lER

ASOCS

LOC !BJ

LINE

967F B881
8681 EE
8682 EC

431
432
433
434
435
436
417
438
439
448
441
442
443
444
44S
446
447
448
449
458
451
452
453

8683 R22B82
8686 11838
8688 EE

11689 58
868R !it

8688 CF

8611:: 52
868D 57
868E 58
868F E87E88
~ FF862C82
8696 FF8E2E82
~74IIE

1169C_
1169F 8113E2C82
II6R3 8R85
96fI5 EE
86A6 58
116R7 5F
_!it
86119
_ CF
8R8288
1I6/llll828
II6RF EE
8688 C686348281
8685 58
8686 5F
8687 SA
Il6IIS CF

8689 52
968A 57
8688 58

II6eC E85188
Il6BFBIlIiI288
86C2 EC
il6C A23682

SOME
lIlY
Ill!
I~

lIlY
lIlY
OOT

POP
POP
lRET

468
461
462
46:;
464
40"')

466
46,
468
469
4,8
471
4<2

lIIITINR: PUSH
PUSH
PUSH

CRLL
II«:
DE~

JE
lIlY
lIlY
lIlY

Our

POP
POP
POP

XIA·

IRET
lIlY
lIlY
Ill!
lIlY
POP

POP
POP
IRET

STAJNR PUSH
PUSH
PUSH

OX
,SAYE REGISTERS
PI
AX
EOI
;SEII) EOI ~ TO 82,4
tXJ'OINTEP_CIfI ,POINT TO NEXT Clfl!KTEJ1
nUEN&TlLClII · DEC LEI«lTH cruHTEJ1
XIA
· TEST IF 001£
ox, IlftTAJ>a!LCIfl
· MIT 001£ - GET NEXT
01, TXJ'OIHTER..CIfI
fL, IDIl
,PUT ~TER IN fL
ox,fL
.IlITPUT IT TO 8274
AX
· RESTORE ilEGISTERS
PI
DX
· PEl1.I1N TO FOREGm.I(l
DX. C(HfNlJ>a!UHA
,ILL CIIRRIICTEJ1S HfI\'E
fl. 28H
,PESET T_IlTER INTEmIPT
DX.fL
TX-fI1PTY-CIfi. 1 ,001£ - 51) SET TX E1f>TY FLffJ
AX
•RESTORE REGISTEI15
PI
DX
,RETUfIN TO FOPEGF(IJ('

DX.
AX
EOI

OOV

[Iii.

474
475

IN
lIlY
lIlY

fl. ~~
STATlIS_I15IJ_ClI\.
fl. Iliff
ox. fL
AX
PI

~jj'

1m

96C9 58

478

POP

86CA 5F

4(9

Pt4'

SA
96CC CF

'4M

POP
IPET

481

482
48,
484

~Ol~IHE

.SEN:' EOJ CCHIIlIl! TO
ru1NRI{,_POPUHA
·REA!l PI10

S2~4

C_

AL
· flJT m IN 5TATlIS NESSAf£
· SEll' PESET STATUS /HT
TO ,.m
· PESTC*f PEGlSTEJ1S

(HfH£l A RE(EI'lEI' lolTA SEF'VICE fIOUTlHE

II(,'IINR flJSN

v,

486
...S,

PUSH

vI

flJSH
(ALL

fC~

EOI

flO"'"

['j.

498

CHB

D~

485

4es
48!'

BEEN 5EHl'
PEll>II«l

[oj

-it3-

8OC8 EE

OfIRIICTElI

.5A\IE PEGISTEI15

CfLL

4;r,)

eml 52
96CE S<
9OI:F ~"l
80W E8~
116[1, SS,E882
86NBAE1880

,RE/I) RRI
ERRaU15G..CII!, fL
· SAYE IT IN ERRCR FLAG
fL, 38H
.5£M) RESET ElIm1 ClHR() TO 82,4
i»<,fL
AX
,RESTORE PEGISTEI15
OX
,REMN TO FORE~

,CHfIf£L A SlAM 0Rr.£ 5a1\I/cE

96C6 8818

86('8

,POINT AT RRI

,CIfH£L AT_IT IlftTA 5a!VICE flOUT/HE

454
455
4S6
457
458
4S9

fL, 1
01<. fL
fL, OX

11.lI'

· SAYE PEGISTEf'5
SEN[' EOI COItlAHI' Tn 2~~'
P;':. POINTtUIlA
· GET p;: eHfl BUFFEP P,lIHTE'

t':;. DATA_Pl"UIfl

210311-32

2-200

inter

AP-134

HCS-s.; 1'11(110 ASSEHBLER

ASVNCB

LOC OBJ

L1N£

EC
8600 BIleS
8600 FF!163692
1l6£1 FF863262
1l6£53COO
!l6E775IJE
!l6E9 C6!16356261
Il6EE BR6Z66
1l6F1 8663
1l6F; EE
1l6F4 B6C6
86F6 EE
1l6F758
Il6FB Sf
661'9511
Il6FA CF
06I)ft

871!O 58
876E SA
871lF CF

8718 56
8711 52
8712_
9715 se3ll
8m EE
8716 SA

.REfORT.OI\

lIN
OUT

fl., 1

,POIHT AT W1

EOI ClJII1fM1 TO 8274

OX, fI.

IN
HO'I
/tOY

,REIID I1Rl
ERROR..It56..CHA. AL
.5A'IE IT IN Ew(IP FLff:i
11., 36H
• SEt«> RESET EI1!I(JI COI9'/IH{\ TO 8274
OX, fI.
AX
,~ESTOI1E ~EGISTER5
OX

OUT
POP
POP

528
521
522
523
524

• STO~E IN 8I.fFEF
Ttf 8I.fFER POINIE~
,BIAlP THE CMTEF
. TEST IF LAST (HfRAm~ TO BE REmVEl"

RX_W.INUHA

OUT

569
1l6F852
Il6FC 56
Il6FD E81009
6766 BA6200
6763 8001
6785 EE
6766 EC
. 6767 A23762
879A 8036
876C EE

ox

4n
492
493
4901

fl., OX

IRET

525

;ENKI"-IHTERRlfT POOllhl: - SfHDS EOI Cl1tItANO TO 8274
, THIS COIWlHD II.IST ALWAI'S TO ISSl(O ON CHAN£L A

526
527

EOI.

528

PIJSIf
PUSH

AX
. SAVE REGISTEPS
OX
ox, C_ _ POPT _CHfI
,fl.WAVS FOP ClRINEL A ",
fI.,3lIH
OX. fl.

529
539
531
532

lIN
• HOY
OUT

POP

OX

6719 58

53l

AX

671A CJ

534
535
536
537
536
539

POP
RET

; END OF COI:E ROUTlhI:

ABC

ENOS

END

ASSEtRY CIWLETE, NO ERRORS FCU«>

210311-33

REFERENCES
1. 8274 Multiprotocol Serial Controller (MPSC) Data
Sheet, Intel Corporation, California, 1980.
2. Basics of Data Communication, Electronics Book
Series, McGraw-Hill, New York, 1976.

3. Telecommunications and the Computer, J. Martin,
Prentice-Hall, New Jersey, 1976.
4. Technical Aspects of Data Communications, J. McNamara, DEC Press, Massachusetts, 1977.
5. Miscellaneous Data Communications StandardsEIA RS-232-C, EIA RS-422, EIA RS-423, EIA
Standard Sales, Washingto.n, D.C.

2·201

APPLICATION
NOTE

AP-145

November 1986

Synchronous Communication with
the 8274 Multiple Protocol
Serial Controller

SIKANDAR NAQVI
APPLICATION ENGINEER

Order Number: 210403-001
2-202

inter

AP-145

INTRODUCTION
The INTEL 8274 is a Multi-Protocol Serial Controller,
capable of handling both asynchronous and synchronous communication protocols. Its programmable features allow it to be configured in various operating
modes, providing opimization to given data communication application.
This application note describes the features of the
MPSC in Synchronous Communication applications
only. It is strongly recommended that the reader read
the 8274 Data Sheet and Application Note AP134
"Asynchronous Communication with the 8274 MultiProtocol Serial Controller" before reading this Application Note. This Application note assumes that the reader is familiar with the basic structure of the MPSC, in
terms of pin description, Read/Write registers and
asynchronous communication with the 8274. Appendix
A contains the software listings of the Application Example and Appendix B shows the MPSC ReadIWrite
Registers for quick reference.
The first section of this application note presents an
overview of the various synchronous protocols. The
second section discusses the block diagram description
of the MPSC. This is followed by the description of
MPSC interrupt structure and mode of operation in the
third and fourth sections. The fifth section describes a
hardware/software example, using the INTEL single
board computer iSBC88/45 as the hardware vehicle.
The sixth section consists of some specialized applications of the MPSC .. Finally, in section seven, some use. ful programming hints are summarized.

SYNCHRONOUS PROTOCOL
OVERVIEW
This section presents an overview of various synchronous protocols. The contents of this section are fairly
tutorial and may be skipped by the more knowledgeable
reader.

Bit Oriented Protocols Overview
Bit oriented protocols have been defined to manage the
flow of information on data communication links. One
of the most widely known protocols is the one defined
by the International Standards Organization: HDLC
Opening
Flag
Byte

Address'
Field (A)

(High Level Data Link Control). The American Standards Association's protocol, ADCCP is similar to
HDLC. CCITT Recommendation X.25 layer 2 is also
an acceptable version of HDLC. Finally, IBM's SDLC
(Synchronous Data Link Control) is also a subset of the
HDLC.
In this section, we will concentrate most of our discussion on HDLC. Figure I shows a basic HDLC frame
format.
A frame consists of five basic fields: Flag, Address,
Control, Data and Error Detection. A frame is bounded by flags-opening and closing flags. An address field
is 8 bits wide, extendable to 2 or more bytes. The control field is also 8 bits wide, extendable to two bytes.
The data field or information field may be any number
of bits. The data field mayor may not be on an 8-bit
boundary. A powerful error detection code called
Frame Check Sequence contains the calculated CRC
(Cycle Redundancy Code) for all the bits between the
flags.
ZERO BIT INSERTION

The flag has a unique binary bit pattern: 7E HEX. To
eliminate the possibility of the data field containing a
7E HEX pattern, a bit stuffing technique called Zero
Bit Insertion is used. This technique specifies that during transmission, a binary 0 be inserted by the transmitter after any succession of five contiguous binary I's.
This will ensure that no pattern of 0 I I I I I lOis ever
transmitted between flags. On the receiving side, after
receiving the flag, the receiver hardware automatically
deletes any 0 following five consecutive I's. The 8274
performs zero bit insertion and deletion automatically
in the SDLC/HDLC mode. The zero-bit stuffing ensures periodic transitions in the data stream. These
transitions are necessary for a phase lock circuit, which
may be used at the receiver end to generate a receive
clock which is in phase to the received data. The inserted and deleted O's are not included in the CRC checking. The address field is used to address a given secondary station. The control field contains the link-level control information which includes implied acknowledgement, supervisory commands and responses, etc. A
more detailed discussion of higher level protocol functions is beyond the scope of this application note. Interested readers may refer to the references at the end of
this application note.

Data
Field

Control"
Field (C)

Figure 1. HOLC/SOLC Frame Format
"Extendable to 2 or More Bytes.
• "Extendable to 2 Bytes.

2-203

Frame
Check
Sequence

Closing
Flag
Byte

inter

AP-145

The data field may be of any length and content in
HOLC. Note that SOLC specifies that data field be a
multiple of bytes only. In data communications, it is
generally desirable to transmit data which may be of
any content. This requires that data field should not
contain characters which are defined to assist the transmission protocol (like opening flag 7EH in HOLC/
SOLC communications). This property is referred to as
"data transparency". In HOLC/SOLC, this - code
transparency is made possible by Zero Bit Insertion discussed earlier and the bit oriented nature of the protocol.

sync. Bisync has two starting sync characters per message while monosync has only one sync character. For
the sake of brevity, we will only discuss Bisync here.
All the discussion is valid for Monosync also. Any exceptions will be noted. Figure 2 shows a typical Bisync
message format.
The Bisync protocol is defined for half duplex communication between two or more stations over point to
point' or multipoint communication lines. Special characters control link access, transmission of data and termination of transmission operations for the system. A
detailed discussion of these special control characters
(SYN, ENQ, STX, ITB, ETB, ETX, OLE, SOH,
ACKO, ACKI, WACK, NAK and EOT, etc) is beyond
the scope of this Application Note. Readers interested
in more detailed discussion are directed to the references listed at the end of this Application Note.

The last field is the FCS (Frame Check Sequence). The
FCS uses the error detecting techniques called Cyclic
Redundancy Check. In SOLCIHOLC, the CCITTCRC must be used.
NON-RETURN TO ZERO INVERTED (NRZI)

NRZI is a method of clock and data encoding that is
well suited to the HOLC protocol. It allows HOLC
protocols to be used with low cost asynchronous modems. NRZI coding is done at the transmitter to enable
clock recovery from the data at the receiver terminal by
using standard digital phase locked loop techniques.
NRZI coding specifies that the signal condition does
not change for transmitting a I, while a 0 causes a _
change of state. NRZI coding ensures that an active
data line will have transition at least every 5-bit times
(recall Zero Bit Insertion), while contiguous O's will
cause a change of state. Thus, ZBI and NRZI encoding
makes it possible for a phase lock circuit at the receiver
end to derive a receive clock (from received data) which
is synchronized to the received data and at the same
time ensure data transparency.

Byte Synchronous Communication
As the name implies, Byte Synchronous Communication is a synchronous communication protocol which
means lual lue uansmiiting station is synchronized LO
the receiving station through the recognition of a special sync character or characters. Two examples of Byte
Synchronous protocol are the IBM Bisync and MonoSYNC

SYNC

SOH

HEADER

As shown in Figure 2, each message is preceded by two
sync characters. Since the sync characters are defined
at the beginning of the message only, the transmitter
must insert fill characters (sync) in order to maintain
synchronization with the receiver when no data is being
transmitted.
TRANSPARENT TRANSMISSION

Bisync protocol requires special control characters to
maintain the communication link over the line. If the
data is EBCDIC encoded, then transparency is ensured
by the fact that the field will not contain any of the
bisync control characters. However, if data does not
conform to standard character encoding techniques,
transparency in bisync is achieved by inserting a special
character OLE (Oata Link Escape) before and after a
string of characters which are to be transmitted transparently. This ensures that any data characters which
match any of the special characters are not confused for
special characters. A-n example of a transparent block is
shown in Figure 3.
'
In a transparent mode, it is required that the CRC
(BCC) is not performed on special characters. Later on,
we will show how the; 8274 can be used to achieve
transparent transmission in Bisync mode.

STXTEXT

ETXOR ETB

CRC1

CRC2

ETX

BCC

Figure 2. Bisync Message Format

OLE

STX

Enter transparent mode

TRANSPARENT TRANSMISSION

OLE

return to normal mode

,Figure 3. Bisync Transparent Format

2-204

intJ

AP-145

each

BLOCK DIAGRAM

channel:

TxDRQA, TxDRQB, RxDRQA,
that TxDRQB and RxDRQa..£.ecome
IPO and IPI respectively in non-DMA mode. IPI is the
Interrupt Priority Input and IPO is the Interrupt Priority Output. These two pins can be used for connecting
multiple MPSCs in a daisy chain. If the Wait Mode is
programmed, then TxRDQA and RxDRQA pins become RDYB and RDYA pins. These pins can be wireOR'ed and are usually hooked up to the CPU RDY
line to synchronize the CPU for block transfers. The
INT pin is activated whenever the MPSC requires CPU
attention. The INTA may be used to utilize the powerful vectored mode feature of the 8274. Detailed discussion on these subjects will be done later in this Application Note. The RESET pin may be used for hardware
r~et while the clock is required to click the internal
logic on the MPSC.
RxDRQ~ote

This section discusses the block diagram view of the
8274. The CPU interface and serial interface is discussed separately. This will be followed by a hardware
example in the fifth section, which will show how to
interface the 8274 with the Intel CPU 8088. The 8274
block diagram is shown in Figure 4.

CPU Interface
The CPU interface to the system interface logic block
utilizes the AD, AI, CS, RD and WR inputs to communicate with the internal registers of the 8274. Figure 5
shows the address of the internal registers. The DMA
interface is achieved by utilizing DMA request lines for

TxDA

CHANNEL A
TRANSMITTER

DBO·7

TxCA

CHANNEL A
WRITE
REGISTERS
ClK
-RESET
RDYBITxDRQA

I

DCDA

!!

CTSA
CHANNEL A
CONTROL
lOGIC

RTSA
SYNDETA

RDYAIRxDRQA

...
"'
" v~~_
IPOITxDRQB
IP1IRxDRQB
INT

'"
SYSTEM
INTERFACE
CONTROL
lOGIC

INTA

~

DTRA

CHANNEL A
READ
REGISTERS

~VL->'-------I CHANNEL A
RECEIVER

~

AO

A,

TxDB

+f

TxCB
DCDB
CHANNElB

CTsa
{

SYSTEM INTERFACE

SYNDETB
RTSB
_

omB
RXCB
RxDB
NETWORK INTERFACE

210403-1

Figure 4. 8274 Block Diagram

2-205

inter

AP-145

CS

A1

AD

0
0

0

0
0

CHA
CHA

DATA READ
STATUS REGISTER
(RRO,RR1)

CHA DATA WRITE
CHA COMMAND/PARAMETER
(WRO-WR7)

0
0

0
1

1
1

CHB
CHB

DATA READ
STATUS REGISTER
(RRO,RR1,RR2)

CHB DATA WRITE
CHB COMMAND/PARAMETER
(WRO-WR7)

1

X

X

HIGHZ

1

Read Operation

Write Operation

HIGHZ

Figure 5. Bus Interface

Serial Interface

Transmit and Receive Data Path

On the serial side, there are two completely independent channels: Channel A and Channel B. Each chan. nel consists of a transmitter block, receiver block and a
set of read/write registers which are used to initialize
the device. In addition, a control logic block provides
the modem interface pins. Channel B serial interface
logic is a mirror image of Channel A serial interface
logic, except for one exception: there is only one pin for
RTSB and SYNDETB.
A a given time, this pin is either RTSB or SYNDETB.
This mode is programmable through one of the internal
registers on the MPSC.

Figure 6 shows a block diagram for transmit and receive data path. Without describing each block on the
diagram, a brief discussion of the block diagram will be
presented here.
TRANSMIT DATA PATH

The transmit data is transferred to the twenty-bit serial
shift register. The twenty bits are needed to store two
bytes of sync characters in bisync mode. The last three
bits of the shift register are used to indicate to the internal control logic that the current· data byte has been
shifted out of the shift register. The transmit data in the

CPU 10

TxDA

TIICA

210403-2

Figure 6. Transmit and Receive D.ata Path

2-206

inter

AP-145

transmit shift register is shifted out through a two bit
delay onto the TxData line. This two bit delay is used
to synchronize the internal shift clock with the external
transmit clock. The data in the shift register is also
presented to zero bit insertion logic which inserts a zero
after sensing five contiguous ones in the data stream. In
parallel to all this activity, the CRC-generator is computing CRC on the transmitted data and appends the
frame with CRC bytes at the end of the data transmission.

RECEIVE DATA PATH

The received data is passed through a one bit delay
before it is presented for flag/sync comparison. In bisync mode, after the synchronization is achieved, the
incoming data bypasses the sync register and enters directly into the three bit buffer on its way to receive shift
register. In SDLC mode, the incoming data always
passes through the sync register where the data pattern
is continuously monitored· for contiguous ones for the

FIRST DATA CHARACTER

FIRST NON·SYNC
CHARACTER (SYNC MODES)

INTERRUPT
ON FIRST RECEIVE
CHARACTER

VALID ADDRESS
BYTE (SDLC)
INTERRUPT ON
ALL RECEIVE
CHARACTERS
PARITY ERROR

RX OVER-RUN ERROR

FRAMING ERROR

SPECIAL
RECEIVE
CONDITION
INTERRUPT

END OF FRAME
(SDLCONLY)

DCD TRANSITION

MPSC
INTERRUPTS

CTS TRANSITION

SYNC TRANSITION

TX UNDER-RUN/EOM

BREAK/ABORT DETECT

TRANSMIT
INTERRUPT

TX BUFFER EMPTY

210403-3

Figure 7_ MPSC Interrupt Structure

2-207

intJ

AP-145

zero deletion logic. The data then enters the three bit
buffer and the receive shift register. From the receive
shift register, the data is transferred to the three byte
deep FIFO. The data is transferred to the top of the
FIFO at the chip clock rate (not the receiver clock). It
takes three chip clock/periods to transfer data from the
serial shift register to the top of the FIFO. The three bit
deep Receive Error FIFO shifts any error condition
which may have occurred during a frame reception.
While all this is happening, the CRC checker is checking the CRC on the incoming data. The computed
CRC is checked with the CRC bytes attached to the
incoming frame and an error generated under a nocheck condition. Note that the bisync data is presented
to the CRC checker with an 8-bit delay. This is necessary to achieve transparency in bisync mode as will be
·shown later in this Application Note.

MULTI-PROTOCOL. SERIAL
CONTROLLER (MPSC) INTERRUPT
STRUCTURE
The MPSC offers a very powerful interrupt structure,
which helps in responding to an interrupt condition
very quickly. There are multiple sources of interrupts
within the MPSC. However, the MPSC resolves the
priority between various interrupting sources and interrupts the CPU for service through the interrupt line.
This section presents a comprehensive discussion of all
. the 8247 interrupts and the priority resolution between
these inter~pts.
All the sources of interrupts on the 8274 can. be
grouped into three distinct categories. (See Figure 7.)
I. Receive Interrupts
2. Transmit Interrupts
3. External/Status Interrupts.
An internal interrupt priority structure sets the priority
between the interrupts. There are two programmable
options available on the MPSC. The priority is set by
WR2A, D2 (Figure 8).
PRIORITY

WR2A:D2

Highest

0

RxA
RxA

1

Lowest

TxA RxB TxB EXTA EXTB
RxB TxA TxB EXTA EXTB

Figure 8. Interrupt Priority

Receive Interrupt
All receive interrupts may be categorized into two distinct groups: Receive Interrupt on Receive Character
and Special Receive Condition Interrupts.

RECEIVE INTERRUPT ON RECEIVE
CHARACTER

A receive interrupt is generated when a character is
received by the MPSC. However, as will be discussed
later, this is a programmable feature on the MPSC. A
Rx character available interrupt is generated by the
MPSC after the receive character has been assembled
by the MPSC. It may be noted that in DMA transfer
mode too, a receive interrupt on the first receive character should be programmed. In SDLC mode, if address search mode has been programmed, this interrupt
.will be generated only after a valid ad4ress match has
occurred. In bisync mode, this interrupt is generated on
receipt of a character after at least two valid sync characters. In monosync mode, a .character followed after at
least a single valid sync character will generate this in·
terrupt. An interrupt on first receive character signifies
the beginning of a valid frame. An end of the frame is
characterized by an "End of Frame" Interrupt (RRI:
D7).* This bit (RRI:D7) is set in SDLC/HDLC mode
only and signifies that a valid ending flag (7EH) has
been received. This bit gets reset either by an "Error
Reset" command (WRO: D5D4D3 = 110) or upon reo
ception of the first character of the next frame. In multiframe reception, on receiving ·the interrupt at the
"End of Frame" the CPU may issue an Eri'or Reset
command which will reset the interrupt. In DMA
mode, the interrupt on first receive character is accompanied by a RxDRQ (Receiver DMA request) on the
appropriate channel. At the end of the frame, an End of
Frame interrupt is generated. The CPU may use this
interrupt to jump into a routine which may redefine the
receive buffer for the next incoming frame.
• NOTE:
RRI:D7 is bit D7 in Read Register 1.
SPECIAL RECEIVE CONDITION INTERRUPTS

So far, we have assumed that the reception is error free.
But this is not 'typical' in most real life applications.
Any error condition during a frame reception generates
yet another interrupt-special receive condition interrupt. There are four different error conditions which
can generate this interrupt.
(i) Parity error
(ii) Receive Overrun error
(iii) Framing error
(iv) End of Frame
(i) Parity error: Parity error is encountered in asynchronous (start-stop bits) and in bisync/monosync protocols. Both odd or even parity can be programmed. A
parity error in a received byte will generate a special
receive condition .interrupt and sets bit 4 in RRI.

2-208

AP-145

(ii) Receive Overrun error: If the CPU or the OMA
controller (in OMA mode) fails to read a received character within three byte times after the received character interrupt (or OMA request) was generated, the receiver buffer will overflow and this will generate a special receive condition interrupt and sets bit 5 in RR1.
(iii) Framing error: In asynchronous mode, a framing

error will generate a special receive interrupt and set bit
06 in RR1. This \lit is not latched and is updated on
the next received character.
(iv) End of frame: This interrupt is encountered in
SOLC/HOLC mode only. When the MPSC receives
the closing flag, it generates the special receive condition interrupt and sets bit 07 in RR1.
All the special receive condition interrupts may be reset
by issuing an Error Reset Command.
CRC Error: In SOLC/HOLC and synchronous modes,
a CRC error is indicated by bit 06 in RR1. When used
to check CRC error, this bit is normally set until a
correct CRC match is obtained which resets this bit.
After receiving a frame, the CPU must read this bit
(RRl:06) to determine if a valid CRC check had occurred. It may be noted that a CRC error does not
generate an interrupt.
It may also be pointed out that in SOLC/HOLC mode,

receive DMA requests are disabled by a special receive
condition and can only be re-enabled by issuing an Error Reset Command.

Transmit Interrupt
A transmit buffer empty generates a transmit interrupt.
This has been discussed earlier under "Transmit in Interrupt Mode" and it would be sufficient to note here
that a transmit buffer empty interrupt is generated only
when the transmit buffer gets empty-assuming it had
a data character loaded into it earlier. This is why on
starting a frame transmission, the first data character is
loaded by the CPU without a transmit empty interrupt
, (or OMA request in OMA mode). After this character
is loaded into the serial shift register, the buffer becomes empty, and an interrupt (or OMA request) is
generated. This interrupt is reset by a "Reset Tx Interrupt/DMA Pending" command (WRO: 05 04 03
101).

External/Status Interrupt
Continuing our discussion on transmit interrupt, if the
transmit buffer is empty and the transmit serial shift
register also becomes empty (due to the data character
shifted out of the MPSC), a transmit under-run interrupt will be generated. This interrupt may be reset by
"Reset ExternaVStatus Interrupt" command (WRO:
05 04 03 = 101).

The External Status Interrupt can be caused by five
different conditions:
(i) CO Transition
(ii) CTS Transition
(iii) Sync/Hunt Transition
(iv) Tx under-run/EOM condition
(v) Break/Abort Oetection.
CO, CTS TRANSITION

Any transition on these inputs on the serial interface
will generate an ExternaVStatus interrupt and set the
corresponding bits in status register RRO. This interrupt will also be generated in OMA as well as in Wait
Mode. In order to find out the state of the CTS or CO
pins before the transition had occurred, RRO must be
read before issuing a Reset ExternaVStatus Command
through WRO. A read of RRO after the Reset External/
Status Command will give the condition of CTS or CO
pins after the transition had occurred. Note that bit 05
in RRO gives the complement of the state of CTS pin
while 03 in RRO reflects the actual state of the CO pin.
SYNC HUNT TRANSITION

Any transition of the SYNOET input generates an interrupt. However, sync input has different functions in
different modes and we shall discuss them individually.
SOLC Mode

In SOLC mode, the SYNOET pin is an output. Status
register RRl, 04 contains the state of the SYNOET
pin. The Enter Hunt Mode initially sets this bit in RO.
An opening flag in a received SOLC frame resets this
bit and generates an external status interrupt. Every
time the receiver is enabled or the Enter Hunt Code
, Command is issued, an external status interrupt will be
generated on receiving a valid flag followed by a valid
address/data character. This interrupt may be reset by
the "Reset External/Status Interrupt" command.
External SYNC Mode

The MPSC can be programmed into External Sync
Mode by setting WR4, 05 04 = 11. The SYNOET
pin is an input in this case and must be held high until
an external character synchronization is established.
However, the External Sync mode is enabled by the
Enter Hunt Mode control bit (WR3: 04). A high at the
SYNOET pin holds the Sync/Hunt bit (RRO,04) in
the reset state. When external synchronization is established, SYNOET must be driven low on second rising

2-209

AP-145

edge of RxC after the rising edge of RxC on which the
last bit of sync character was received. This high to low
transition sets the Sync/Hunt bit and generates an external/status interrupt, which must be reset by the Reset External/Status command. If the'SYNDET input
goes high again; another External Status Interrupt is
generated, which may be cleared by Reset External/
Status command.

In SDLC Receive Mode, an Abort sequence (seven or
more I's) detection on the receive data line will generate an External/Status interrupt and set RRO,D7. A
Reset External/Status command will clear this interrupt. However, a termination of the Abort sequence
will generate another interrupt and set RRO,D7 again.
Once again, it may be cleared by issuing Reset External/Status Command. '

Mono-Sync/Bisync Mode

This concludes our discussion on External Status Interrupts.

SYNDET pin acts as an output in this case. The Enter
Hunt Mode sets the Sync/Hunt hit in RO. Sync/Hunt
bit is reset when the MPSC achieves character synchronization. This high to lo,\\, transition will generate an
external status interrupt. The SYNDET pin goes active
every time a sync pattern is detected in the data stream.
Once again, the external status interrupt may be reset
by the Reset External/Status command.

Interrupt Priority Resolution
The internal interrupt priority between various interrupt sources is resolved by an internal priority logic
circuit, according to the priority set in WR2A. We will
now discuss the interrupt timings during the priority
resolution. Figures 9 and 10 show the timing diagrams
for vectored and non-vectored modes.

Tx UNDER-RUN/END OF MESSAGE (EOM,>

The transmitter logic includes a transmit buffer and a
transmit serial shift register. The CPU loads the character into the transmit buffer which is transferred,into
the transmit shift register to be shifted Ollt of' the
MPSC. If the transmit buffer gets empty, a transmit
buffer empty interrupt is generated (as discussed earlier). However, if the transmit buffer gets empty and the
serial shift register gets empty, a transmit under-run
condition will be created. This generates an External
Status Interrupt and the interrupt can be cleared by the
Reset External Status command. The status register
RRO, D6 bit is set when the transmitter under-runs.
This bit plays an important role in controlling a transmit operation, as will be discussed later in this application note.
.'
BREAK/ ABORT DETECTION

In asynchronous mode, bit D7 in .RRO is set when a
break condition is detected on the receive data line.
This also generates an External/Status interrupt which
may be reset by issuing a Reset External/Status Interrupt command to the MPSC. Bit D7 in RRO is reset
when the break condition is terminated on the receive
data line and this causes another External/Status interrupt to ge .generated. Again, a Reset External/Status
Interrupt command will reset this interrupt and will
enable the break detection logic to look. for the next
break sequence.

VECTORED MODE

We shall assume that the MPSC accepted an internal
request for an interrupt by activating the internal INT
signal. This leads to generating an external interrupt
signal on the INT pin. The CPU responds with an interrupt acknowledge (INTA) sequence. The leading
edge of the first INTA pulse sets an internal interrupt
ac~nowledge signal (we will call it Internal INTA). Internal INTA is reset by the high going edge of the third
INTA pulse. The MPSC will not accept any internal
requests for an interrupt during the period when Internal INTA is active (high). The.MPSC resolves the priority during various existing internal interrupt requests
during the Interrupt Request Priority Resolve Time,
which is defined as the time between the leading edge of
the first INTA and the leading edge of the second
INTA from the CPU. Once the internal priorities have
been resolved, an internal Interrupt-in-service Latch is
set. The external INT is also deactivated when the Interrupt-in-Service Latch is set.
The .lower priority interrupt requests are not accepted
internally until an EOI (WRO: DS D4 D3 = III Ch. A
only) command is issued by the CPU. The EOI command enables the lower priority interrupts. However, a
higher priority interrupt request will still be accepted
(except during the period when internal INTA is active) even though the Internal-in-Service Latch is set.

2-210

AP-145

INTERNAL INT
ACCEPTED

J

'.:...1

EXTERNAL
INT

~~_ _ _ _ _ _ _ _ _ _ _ _~~
\

\~--------------_\~------------~~-------+
IPO
INTA

INTERNAL
INTA

I

:;"...".-_ _ _ _ _ _ _ _ _ _
NO_IN_TE_\...JN:
r./INTERRUPTS ACCEPTED
:.;
INT·IN·SERVICE

Y

(INTERNAL LATCH)

EOICOMMA.~ND~

________________________________

~

210403-4

Figure 9. 8274 in 8085 Vectored Mode Priority Resolution Time

INTERNAL INT
ACCEPTED
EXTERNAL INT -----""'\

\
IPI

\
\
I

POINTER 2
SPECIFIED

~~OINTERNALINTERRUPTS-\
-------1..f
ACCEPTED
I

I

--",~---+---+-----

1...

j4-PRIORITY
I
RESOLVE
TIME
INT.IN.SERVICE=____________________....J
(INTERNAL LATCH)

EOICOMMAND------------------------------------------~~----....J

210403-5

Figure 10. 8274 Non Vectored Mode Priority Resolve Time

2-211

AP-145

Thi~her

priority request will generate another external INT and will have to be handled by the CPU according to how the CPU is set up. If the CPU is set up
to respond to this interrupt, a new INTA cycle will be
repeated as discussed earlier. It may also be noted that
a transmitter buffer empty and receive character available interrupts are cleared by loading a character into
the MPSC and by reading the character received by the
MPSC respectively.
NON-VECTORED MODE

Figure 10 shows the timing of interrupt sequence in
non-vectored mode. The explanation of non-vectored is
similar to the vector mode, except for the following
exceptions.
- No internal priority requests are accepted during
the time when pointer 2 for Channel B is specified.
- The interrupt request priority resolution time is the
time between the leading edge of pointer 2 and leading edge of RD active. It may be pointed out that in
non-vectored mode, it is assumed that the status
affects vector mode is used to expedite interrupt response.
,On getting an interrupt in non-vectored mode, the CPU
must read status register RR2 to find out the cause of
the interrupt. In order to do so, first a pointer to status
register RR2 is specified and then the status read from
RR2. It may be. noted here that after specifying the
pointer, the CPU must read status register RR2 otherwise, no new interrupt requests will be accepted internally.
Just like the vectored mode, no lower internal priority
requests are accepted until an EOI command is issued
by the CPU. A higher priority request can still interrupt the CPU (except during the priority request inhibit
time). It is important to note here that if the CPU does
not perform a read operation after specifying the pointer 2 for Channel B, the interrupt request accepted before the pointer 2 was activated will remain valid and
no other request (high or low priority) will be accepted
internally. In order to complete a correct priority resolution, it is advised that a read operation be done after
specifying the pointer 2B.

EOI Command

The EOI command as explained earlier, enables the
lower priority interrupts by resetting the internal InService-Latch, which consequently resets the IPO output to a low state. See Figures 9 and 10 for details. Note
that before issuing any EOI command, the internal interrupting source must be satisfied otherwise, same
source will interrupt again. The Internal Interrupt is
the signal which gets reset when the internal interrupting source is satisfied (see Figure 9).
This concludes our discussion on the MPSC Interrupt
Structure.

MULTI-PROTOCOL SERIAL
CONTROLLER (MPSC) MODES OF
OPERATION
The MPSC provides two fully independent channels
that may be configured in various modes of operations.
Each channel can be configured into full duplex mode
and may operate in a mode or protocol different from
the other channel. This feature will be very efficient in
an application which requires two data link channeis
operating in different protocols and possibly at different
data rates. This section presents a detailed discussion
on all the 8274 modes and shows how to configure it
into these modes.

Interrupt Driven Mode
In the interrupt mode, all the transmitter and receiver
operations are reported to the processor through interrupts. Interrupts are generated by the MPSC whenever
it requires service. In the following discussion, we will
discuss how to transmit and receive in interrupt driven
mode.
.
TRANSMIT IN INTERRUPT MODE

The MPSC can be configured into interrupt mode by
appropriately setting the bits in WR2 A (Write Register
2, Channel A). Figure 11 shows the modes of operation.
WR2A

IPI and IPO

So far, we have ignored the IPI and IPO signals shown
in Figures 9 and 10. We may recall that IPI is the
Interrupt-Priority-Input to the MPSC. In conjunction
with the IPO (Interrupt Priority Output), it is used to
daisy chain multiple MPSCs. MPSC daisy chaining will
be discussed in detail later in this application note.

2-212

D1

DO

0
0

0

1
1

0

1
1

Mode
CH A and CH B in Interrupt Mode
CHA in DMA and CH B in Interrupt
Mode
CH A and CH B in DMA Mode
Illegal

Figure 11_ MPSC Mode Selection for
Channel A and Channel B

inter

AP-145

We will limit our discussion to SDLC transmit and re·
ceive only. However, exceptions for other synchronous
protocols will be pointed out. To initiate a frame trans·
mission, the first data character must be loaded from
the CPU, in all cases. (DMA Mode too, as you will
notice later in this application note). Note that in
SDLC mode, this first data character may be the ad·
dress of the station addressed by the MPSC. The trans·
mit butTer consists of a transmit butTer and a serial shift
register. When the character is transferred from the
butTer into the serial shift regiser, an interrupt due to
transmit butTer empty is generated. The CPU has one
byte time to service this interrupt and load 'another
character into the transmitter butTer. The MPSC will
generate an interrupt due to transmit butTer underrun
condition if the CPU does not service the Transmit
ButTer Empty Interrupt within one byte time.
This process will continue until the CPU is out of any
more data characters to be sent. At this point, the CPU
does not respond to the interrupt with a character but
simply issues a Reset Tx INT/DMA pending com·
mand (WRO: D5 D4 D3 = 101). The MPSC will ulti·
mately underrun, which simply means that both the
transmit butTer and transmit shift registers are empty.
At this point, flag character (7EH) or CRC byte is
loaded into the transmit shift register. This sets the
transmit underrun bit in RRO and generates "Transmit
Underrun/EOM" interrupt (RRO: D6 = I).
You will recall that an SDLC frame has two CRC bytes
after the data field. 8274 generates the CRC on all the
data that is loaded from the CPU. During initialization,
there is a choice of selecting a CRC·16 or CCITT·CRC
(WR5: D2). In SDLC/HDLC operation, CCITT·CRC
must be selected. We will now see how the CRC gets
inserted at the end of the data field. Here we have a
choice of having the CRC attached to the data field or
sending the frame without the CRC bytes. During
transmission, a "Reset Tx Underrun/EOM Latch"
command (WRO: D7 D6 = 11) will ensure that at the
end of the frame when the transmitter underruns, CRC
bytes will be automatically inserted at the end of the
data field. If the "Reset Tx Underrun/EOM Latch"
command was not issued during the transmission of
data characters, no CRC would be inserted and the
MPSC will transmit flags (7EH) instead.
However, in case of CRC transmission, the CRC trans·
mission sets the Tx Underrun/EOM bit and generates a
Transmitter Underrun/EOM Interrupt as discussed
earlier. This will have to be reset in the next frame to
ensure CRC insertion in the next frame. It is recom·
mended that Tx Underrun/EOM latch be reset very
early in the transmission mode, preferably after loading
the first c4aracter. It may be noted here that Tx Under·
run EOM latch cannot be reset if there is no data in the
transmit butTer. This means that at least one character
has to be loaded into the MPSC before a "Reset Trans·
mit UnderrunlEOM Latch" command will be accepted
by the MPSC.

When the transmitter is underrun, an interrupt is gen·
erated. This interrupt is generated at the beginning of
the CRC transmission, thus giving the user enough
time (minimum 22 transmit clock cycles) to issue an
Abort command (WRO: D5 D4 D3 = 00 I) in case if
. the transmitted data had an error. The Abort Com·
mand will ensure that the MPSC transmits at least
eight I's but less than fourteen I's before the line re·
verts to continuous flags. The receiver will scratch this
frame because of bad CRC.
However, assuming the transmission was good (no
Abort Command issued), after the CRC bytes have
been transmitted, closing flag (7EH) is loaded into the
transmit buffer. When the flag (7EH) byte is trans·
ferred to the serial shift register, a transmit butTer emp·
ty interrupt is generated. If another frame has to be
transmitted, a new data character has to be loaded into
the transmit buffer and the complete transmit sequence
repeated. If no more frames are to be transmitted, a
"Reset Transmit INT/DMA Pending" command
(WRO: D5 D4 D3 = 101) will reset the transmit buffer
empty interrupt.
For character oriented protocols (Bisync, Monosync),
the same discussion is valid, except that during trans·
mit underrun condition and transmit underrun/EOM
bit in set state, instead of flags, filler sync characters are
transmitted.
CRC Generation

The transmit CRC enable bit (WR5: DO) must be set
before loading any data into the MPSC. The CRC gen·
erator must be reset to all I's at the beginning of each
frame before CRC computation has begun. The CRC
computation starts on the first data character loaded
from the CPU and continues until the last data charac·
ter. The CRC generated is inverted before it is sent on
the Tx Data line.
Transmit Termination

A successful transmission can be terminated by issuing
a "Reset Transmit Interrupt/DMA Pending" com·
mand, as discussed earlier. However, the transmitter
may be disabled any time during the transmission and
the results will be as shown in Figure 12.
RECEIVE IN INTERRUPT MODE

The receiver has to be initialized into the appropriate
receive mode (see sample program later in this applica·
tion note). The receiver must be programmed into Hunt
Mode (WR3: D4) before it is enabled (WR3: DO). The
receiver will remain in the Hunt Mode until a 'flag (or
sync character) is received. While in the SDLC/Bi·
sync/Monosync mode, the receiver does not enter the
Hunt Mode unless the Hunt bit (WR3, D4) is set again
or the receiver is enabled' again.

2·213

AP-145

used to start a DMA transfer or a block transfer sequence using WAIT to synchronize the data transfer to
received or transmitted data.

SDLC Address byte is stored in WR6. A global address
(FFH) has been hardwired on the MPSC. In address
search mode (WR3: D2 = I), any frame with address
matching with the address in WR6 will be received by
the MPSC. Frames with global address (FFH) will also
be received, irrespective of the condition of address
search mode bit (WR3: D2). In general receive mode
(WR3: D2 = 0), all frames will be received.
Transmitter
Disabled during

External Status Interrupts

Any change in CD input or Abort detection in the received data, will generate an interrupt if External Status
Interrupt was enabled (WRI: DO).

Result
Special Receive Conditions

1. Data Transmission Tx Data will send idle
characters' which will be
zero inserted.
2. CRC Transmission 16 bit transmission,
corresponding to 16 bits of
CRC will be completed.
However, flag bits will be
substituted in the CRC field.
3. Immediately after Abort will still be
issuing ABORT
transmitted-output will be
command.
in the mark state.

The receiver buffer is quadruply buffered. If the CPU
fails to respond to "receive character" available interrupt within a period of three byte times (received
bytes), the receiver buffer will overflow and generate an
interrupt. Finally, at the end of the received frame, an
interrupt will be generated when a valid ending flag has
been detected.
Receive Character Length

The receive character length (6, 7 or 8 bits/character)
may be changed during reception. However, to ensure
that the change is effective on the next received character, this must be done fast enough such that the bits
specified for the next character have not been assembled.

Figure 12. Transmitter Disabled
During Transmission

'NOTE:
Idle characters are defined as a string of 15 or more
contiguous ones.
Since the MPSC only recognizes single byte address
field, extended address recognition will have to be done
by the CPU on the data passed on by the MPSC. If the
first address byte is checked by the MPSC, and the
CPU determines that the second address byte does not
have the correct address field, it must set the Hunt
Mode (WR3: D2 = I) and the MPSC will start searching for a new address byte preceded by a flag.
Programmable Interrupts

The receiver may be programmed into anyone of the
four modes. See Figure 13 for details.
WR1,CHA
D4

D3

0
0
1

0
1
0

1

1

CRC Checking

The opening flag in the fraine resets the receive CRC
generator and any field between the opening and closing flag is checked for the CRC. In case of a CRC
error, the CRC/Framing Error bit in status register 1 is
set (RRI: D6 = I). Receiver CRC may be disabled/enabled by WR3,D3. The CRC bytes on the received
frame are passed on ,to the CPU just like data, and may
be discarded by the CPU.
Receive Terminator

An end of frame is indicated by End of Frame interrupt. The CPU may issue an "Error Reset" command
to reset this interrupt.

Rx Interrupt Mode

Rx INT IDMA disable
Rx INT on first character
INT on all Rx characters
(Parity affects vector)
INT on all Rx characters
(Parity does not affect vector)

DMA (Direct Memory Access) Mode
The 8274 can be interfaced directly to the Intel DMA
Controllers 8237A, 8257A and Intel I/O Processor
8089. The 8274 can be programmed into DMA mode
by setting appropriate bits in WR2A. See Figure 11 for
details.

Figure 13. Receiver Interrupt Modes

All receiver interrupts can be disabled by WRI: D4 D3
= 00. Receiver interrupt on first character is normally
2-214

inter

AP-145

TRANSMIT IN DMA MODE

After initializing the 8274 into the DMA mode, the
first character must be loaded from the CPU to start
the DMA cycle. When the first data character (may be
the address byte in SDLC) is transferred from the
transmit buffer to the transmit serial shift register, the
transmit buffer gets empty and a transmit DMA request (TxDRQ) is generated for the channel. Just like
the interrupt mode, to ensure that the CRC bytes are
included in the frame, the transmit under-run/EOM
latch must be reset. This should preferably be done after loading the first character from the CPU. The
DMA will progress without any CPU intervention.
When the DMA controller reaches the terminal count,
it will not respond to the DMA request, thus letting the
MPSC under-run. This will ensure CRC transmission.
However, the under-run condition will generate an interrupt due to the Tx under-run/EOM bit getting set
(RRO: D6). The CPU should issue a "Reset TxInt/
DRQ pending" command to reset TxDRQ and issue a
"Reset External Status" command to reset Tx Underrun/EOM interrupt. Following the CRC transmission,
flag (7EH) will be loaded into the transmit buffer. This
will also generate the TxDRQ since the transmit buffer
is empty following the transmission of the CRC bytes.
The CPU may issue a "Reset TxINT/DRQ pending"
command to reset the TxDRQ. "Reset TxINT/DRQ
pending" command must be issued before setting up
the transmit DMA channel on the DMA Controller,
otherwise the MPSC will start the DMA transfer immediately after the DMA channel is set up.
RECEIVE IN DMA MODE

The receiver must be programmed in RxINT on first
receive character mode (WRl: D4 D3 = 0 1). Upon
receiving the first. character, which may be the address
byte in SDLC, the MPSC generates an interrupt and
also generates a Rx DMA Request (Rx DRQ) for the
appropriate channel. The CPU has three byte times to
service this interrupt (enable the DMA controller, etc.)
before the receiver buffer will overflow. It is advisable
to initialize the DMA controller before receiving the
first character. In case of high bit rates, the CPU will
have to service the interrupt very fast in order to avoid
receiver over-run.
Once the DMA is enabled, the received data is transferred to the memory under DMA control. Any received error conditions or external status change condition will generate an interrupt as in the interrupt driven
mode. The End of Frame is indicated by the End of
Frame interrupt which is generated on reception of the
closing flag of the SDLC frame. This End of Frame
condition also disables the Receive DMA request. The

End of Frame interrupt may be reset by issuing an "Error Reset" command to the MPSC. The "Error Reset"
command also re-enables the Receive DMA request. It
may be noted that the End of Frame condition sets bit
D7 in RR1. This bit gets reset by "Error Reset" command. However, End of Frame bit (RRl: D7) can also
be reset by the flag of the next incoming frame. For
proper operation, Error Reset Command should be issued "after" the End of Frame Bit (RRI: D7) is set. In
a more general case, "Error Reset" command should be
issued after End of Frame, Receive over-run or Receive
parity bit are set in RR 1.

Wait Mode
The wait mode is normally used for block transfer by
synchronizing the data transfer through the Ready output from the MPSC, which may be connected to the
Ready input of the CPU. The mode can be programmed by WR 1, D7 DS and may be programmed
separately and independently on CH A and CH B. The
Wait Mode will be operative if the following conditions
are satisfied.
(i) Interrupts are enabled.
(ii) Wait Mode is enabled (WR1: D7)
(iii) CS = 0, Al = 0
The RDY output becomes active when the transmitter
buffer is full or receiver buffer is empty. This way the
RDY output from the MPSC can be used to extend the
CPU read and write cycle by inserting WAIT states.
RDY A or. RDYB are in high impedance state when the
corresponding channel is not selected. This makes it
possible to connect RDY A and RDYB outputs in wired
OR configuration. Caution must be exercised here in
using the RDY outputs of the MPSC or else the CPU
may hang up for indefinite period. For example, let us
assume that transmitter buffer is full and RDIAJs active, forcing the CPU into a wait state. If the CTS goes
inactive during this period, the RDY A will remain active for indefinite period and CPU will continue to insert wait states.

Vectored/Non-Vectored Mode
The MPSC is capable of providing an interrupt vector
in response to the interrupt acknowledge sequence from
the CPU. WR2, CH B contains this vector and the
vector can be read in status register RR2. WR2, CH A
(bit DS) can program the MPSC in vectored or nonvectored mode. See Figure 14 for details.

2-215

inter

AP-145

In both cases, WR2 may still have the vector stored in
it. However, in vectored mode, the MPSC will put the
vector on the data bus in response to the INTA (Interrupt Acknowledge) sequence as shown in Figure 15. In
non-vectored mode; the MPSC will not respond to the
INTA sequence. However, the CPU can read the vector by polling Status Register RR2. WR2A, 04 and 03
can be programmed to respond to 8085 or 8086 INTA
sequence. It may be noted here that IPI (Interrupt Priority In) pin on the MPSC must be active for the vector
to appear on the ·data bus.

The V~ctor stored in WR2B can be modified by the
source of the interrupt. This can be done by setting the
Status Affect Vector bit (WRI: 02). This powerful feature of the MPSC provides fast interrupt response time,
by eliminating the need of writing a routine to read the
status of the MPSC. Three bits of the vector are modified in eight different ways as shown on Figure 16. Bits
V4, V3, V2 are modified in 8085 based system and bits
V2, VI, VO are modified in 8086/88 based system.
In non-vectored mode, the status affect vector mode
can still be used and the vector read by the CPU. Status
register RR2B (Read Register 2 in Channel B) will contain this modified vector.

Interrupt Mode,

WR2A,05
0
1

STATUS AFFECT VECTOR

Non-vectored Interrupt
Vectored Interrupt .

Figure 14. Vectored Interrupt

05
0
1
1
1
1
1
1

WR2A
04
X
0
0
0
0
1
1

03
X
0
0
1
1
0
0

IPI

Mode

1st INTA

2ndiNTA

3rd INTA

X
0
1
0
1
0
1

Non-Vectored
8085-1
8085-1
8085-2
8085-2
8086
8086

HI-Z
11001101
11001101
HI-Z
HI-Z
HI-Z
HI-Z

HI-Z
V7 V6 V5 V4 V3 V2 V1 VO
HI-Z
V7 V6 V5 V4 V3 V2 V1 VO
HI-Z
V7 V6 V5 V4 V3 V2 V1 VO
HI-Z

HI-Z
00000000
HI-Z
00000000
HI-Z

-

-

Figure 15. MPSC Vectored Interrupts
(8085
(8086)

..

V4
V2
0
0
0
0
1
1
1
1

V3
V1
0
0
1
1
0
0
1
1

V2
VO
0
1
0
1
0
1
0
1

Channel

Interrupt Source

B

Tx Buffer Empty
EXT /STAT Change
RX CHAR Available
Special Rx Condition
Tx Buffer Empty
EXT/STAT Change
RX CHAR Available
Special Rx Condition

A

Rx Special Condition: Panty Error, Framing Error, Rx Over-run Error, EOF (SOLC).
EXT/STAT Change: Change in Modem Control Pin Status: CTS, OCD, SYNC, EOM, Break/Abort Detection.

Figure 16. Status Affect Vector Mode

2-216

inter

AP-145

DUAL PORT ACCESS
CONTROL

8273,8274

8255A

8254·2

8259A

SERIAL
I/O

PARALLEL
I/O

PIT
COUNTERS

INTERRUPT
CONTROL

LED'S

MULTI BUS
ADDRESS BITS
ADR14/·17/

CHANNEL C

210403-6

Figure 17. Functional Block Diagram-iSBC® 88/45

APPLICATION EXAMPLE
This section describes the hardware and software of an
8274/8088 system. The hardware vehicle used is the
INTEL Single Board Computer iSBC 88/45-Advanced Communication Controller. The software
which exercises the 8274 is written in PLM 86. This
example will demonstrate how 8274 can be configured
into the SOLC mode and transfer data through OMA
control. The hardware example will help the reader
configure his hardware and the software examples will
help in developing an application software. Most software examples closely approximate real data link controller software in the SOLC communication and may
be used with very little modification.

iSBC® 88/45

board and the schematics, refer to Hardware Manual
for the iSBC 88/45, Advanced Communication Controller. iSBC 88/45 is an intelligent slave/multimaster
communication board based on the 8088 processor, the
8274 and the 8273 SOLC/HOLC controller. Figure 17
shows the functional block diagram of the board. The
iSBC 88/45 has the following features.
.. 8 MHz processor
.. 16K bytes of static RAM (12K dual port)
o Multimaster/Intelligent Slave Multibus Interface
.. Nine Interrupt Levels 8259A
o Two serial channels through 8274
o One Serial channel through 8273
.. S/W programmable baud rate generator
o Interfaces: RS232, RS422/449, CCITT V.24

A brief description of the iSBC 88/45 board will be
presented here. For more detailed information on the

2-217

" 8237A OMA controller
.. Baud Rate to 800K Baud

AP·145

INI.TIALlZE_B274· PROCEDURE PUBLIC,

1***************************************************************.********1
1*

1*
1*
1*
1*
I.

1*
I.

1*
1*

*1
I N I TI ALI ZE THE 9274 FOR SDLC MODE

*1

*'

I.

*1

2.

RESET CHANNEL
EXTERNAL INTERRUPTS ENABLED
3. NO WAIT
4. PIN 10 = RTS
S. NON-VECTORED INTERRUPT-BOB6 MODE
6. CHANNEL A DMA. CH B INT
7. TX AND RX = 9 BITS/CHAR
9. ADDRESS SEARCH MODE
10.CD AND CTS AUTO ENABLE
11. XI CLOCK
12. NO PARITV
13. SDLC/HDLC MODE
14. RTS AND 'DTR
IS. CCITT - CRC
16. TRANSMITTER AND RECEIVER ENABLED
17.7EH = FLAG

*I

*1
*1
*I

*1
*1
*1
I.
*1
I.
*1
1*
*1
1*
*1
1*
*1
1*
*1
1*
*1
1*
*1
1*
*1
1************************************.*************.*. **t.************* •• /
I.

. DECLARE C .BVTE,

1* TABLE TO INITIALIZE THE 9274 CHANNEL A AND B
1* FORMAT IS: WRITE REGISTER. REGISTER DATA
1* INITIALIZE CHANNEL A ONLV

*1
*1
*1

DECLARE TABLEJ4_A(*l BVTE DATA
(OOH.1SH.'
1* CHANNEL RESET *1
00H.90H.
1* RESET TX CRC *1
02H.II~
1* PIN 10=RTSB. A DMA. B INT *1
04H.20H.
1* SDLC/HDLC MODE. NO PARITY *1
07H.07EH.
1* SDLC FLAG *1
OIH.OOH.
1* RX DMA ENABLE *f
OSH.OEBH.
1* DTR. RTS. 9 TX OITS. TX ENABLE. *1
1* SDLC CRC. TX CRC ENABLE *1
06H.S5H.
1* DEFAULT ADDRESS *1
03H.OD9H.
1* 9 RX OITS. AUTO ENAOLES. HUNT MODE.
1* RX CRC ENABLE *1
OFFH),
1* END OF INITIALIZATION TABLE *1

*1

DECLARE TABLE_74_B(*l BVTE DATA
(02H.00H.
1* INTERRUPT VECTOR *1
OIH.ICH.
1* STATUS AFFECTS'VECTOR *1
OFFH),
1* END *1

1* INITIALIZE THE 9274 *1
C=OI
DO I~HILE TAOLEJ4_B (C l <:> OFFH,
OUTPUT (COMMAND_B_74)
TABLEJ4_B (C).
C=C+li
OUTPUTlCOMMAND_Bj4l ~ TABLEJ4_B(C),
C=C+li
END,

C=O,
DO WH·ILE TABLEJ4_A(Cl <> OFFH,
OUTPUT(COMMAND_AJ4)
TABLEJ4_A(C).
C=C+l;
OUTPUT (COMMAND_AJ4)
C=C+l;
END.
RETURN.
END INITIALIZE_9274'
210403-7

Figure 18. Typical MPSC SOLC Initialization Sequence

2-218

inter

AP-145

For this application, the CPU is run at 8 MHz. The
board is configured to operate the 8274 in SDLC operation with the data transfer in DMA mode using the
8237A. 8274 is configured first in non-vectored mode in
which case the INTEL Priority Interrupt Controller
8259A is used to resolve priority between various interrupting sources on the board and subsequently interrupt the CPU. However, the vectored mode of the 8274
is also verified by disabling the 8259A and reading the
vectors from the 8274. Software examples for each case
will be shown later.
The application example is interrupt driven and uses
DMA for all data transfers under 8237A control. The
8254 provides the transmit and r~ceive clocks for the
8274. The 8274 was run at 400K baud with a local
loopback Gumper wire) on Channel A data. The board
was also run at 800K baud by modifying the software
as will be discussed later in the Special Applications
section. One detail to note is that the Rx Channel
DMA request line from the 8274 has higher priority
than the Tx Channel DMA request line. The 8274 master clock was 4.0 MHz. The on-board RAM is used to
define transmit and receive data buffers. In this application, the data is read from memory location 800H
through 810H and transferred to memory location
900H to 910H through the 8274 Serial Link. The operation is full duplex. 8274 modem control pins, CTS and
CD have been tied low (active).

on first receive character has been programmed although Channel A is in the DMA mode.

Interrupt Routines
The 8274 interrupt routines will be discussed here. On
an 8274 interrupt, program branches off to the "Main
Interrupt Routine". In main interrupt routine, status
register RR2 is read. RR2 contains the modified vector.
The cause of the interrupt is determined by reading the
modified bits of the vector. Note that the 8274 has been
programmed in the non-vectored mode and status affects vector bit has been set. Depending on the value of
the modified bits, the appropriate interrupt routine is
called. See Figure 19 for the flow diagram and Figure
20 for the source code. Note that an End of Interrupt
Command is issued after servicing the interrupt. This is
necessary to enable the lower priority interrupts.
Figure 21 shows all the interrupt routines called by the
Main Interrupt Routine. "Ignore-Interrupt" as the
name implies, ignores any interrupts and sets the FAIL
flag. This is done because this program is for Channel
A only and we are ignoring any Channel B interrupts.
The important thing to note is the Channel A Receiver
Character available routine. This routine is called after
receiving the first character in the SDLC frame. Since
the transfer mode is DMA, we have a maximum of
three character times to service this interrupt by enabling the DMA controller.

Software
The software consists of a monitor program and a program to exercise the 8274 in the SDLC mode. Appendix A contains the entire program listing. For the sake
of clarity, each source module has been rewritten in a
simple language and will be discussed here individually.
Note that some labels in the actual listings in the Appendix will not match with the labels here. Also the
listing in the Appendix sets up some flags to communicate with the monitor. Some of these flags are not explained in detail for the reason that they are not pertinent to this discussion. The monitor takes the command from a keyboard and executes this program, logging any error condition which might occur.

8274 Initialization
The MPSC is initialized in the SDLC mode' for Channel A. Channel B is disabled. See Figure 18 for the
initialization routine. Note that WR4 is initialized before setting up the transmitter and receive parameters.
However, it may also be pointed out that other than
WR4, all the other registers may be programmed in any
order. Also SDLC-CRC has been programmed for correct operation. An incorrect CRC selection will result
in incorrect operation. Also note that receive interrupt

2-219

IF V2V1V0
IF V2V1V0
IF V2V1V0
IF V2V1V0
IF V2V1V0
IF V2V1V0

~
~
~

0, CALL-IGNORE - INTERRUPT
1, CALL IGNORE - INTERRUPT
2, CALL CHB Rx CHAR
~ 3, CALL IGNORE - INTERRUPT
~ 4, CALL IGNORE - INTERRUPT
~ 5, CALL CHA - EXTERNAL CHANGE
INTERRUPT
IF V2V 1V0 ~ 6, CALL CHA Rx CHAR
IF V2V1V0 ~ 7, CALL CHA Rx SPECIAL

210403-8

Figure 19. Interrupt Response Flow Diagram

Ap·145

1**************************1

1* MAIN INTERRUPT ROUTINE *1

1.*****************.*******1
OUTPUTCCOMMANDJlJ41 = 2,
TEMP - INPUTtSTATUS_B_74I AND 07H,

1* SET POINTER TO 2*1
1* READ INTERRUPT VECTOR *1
1* CHECK FOR CHA INT ONLY*I

1* FOR THIS APPLICATION CH B INTERRUPTS ARE IGNORED*I
DO CASE TEMP,
1* \/2Vl\10 • 000*1
IGNORE_INTI
CALL
IGNORE_INT.
1* \/2\11\10 = 001*1
CALL
1* V2\11\10 = 010*1
CALL
CHBJlX_CHAR'
1* Vi2V1VO ,. 011*1
CALL
IGNORE_INT.
IGNORE_I NT,
1* V2VIVO = 100*1
CALL
1* V2VIVO = 101*,
CHA_EXTERNAL_CHANGE,
CALL
CHA_RX_CHARJ
1* V2Vl\10 = 110*1
CALL
CHA_RX_SPEC IAL.
1* \/2V1VO • 111*'
CALL
END.
1* END OF INTERRUPT FOR B274 *1
OUTPUTCCOMMAND_AJ4I -3BH,
RETURN,
END INTERRUPT_B274.

210403-9

Figure 20. Typical Main Interrupt Routine

1******************************************************1
1* CHANNEL A EXTERNAL/STATUS CHANGE INTERRUPT HANDLER *1

1***********-******************************************1

CHA_EXTERNAL_CHANGE:

PROCEDURE.

TEMP· INPUTCSTATUS_AJ41.
1* STATUS REel 1*1
IF (TEMP AND END_OF_TX_MESSAOEI = END_OF_TX_MESSAGE rHEN
TXDONE_S=DO~E.

ELSE DO.
TXDONE_S-DONE.
RESULTS_S-FAIL.
END.
OUTPUTtCOMMAND.JIJ41 • IOH.
RETURN.
END CHA_EX~ERNAL_CHANgE.

1* RESET EXT/STATUS INTERRUPTS *1

1**********************************************************1

1* CHANNEL A SPECIAL RECEIVE CONDITIONS INTERRUPT HANDLER *1

1************._********************************************1
CHAJlX;..SPECIAL:

PROCEDURE.

OUTPUTtCOMMAND_AJ4I • I.
TEMP = INPUTCSTATUS.JIJ41.
IF (TEMP AND END_oFJRAMEI = END_oFJRAME THEN
DO,
IFCTEMP AND 040HI = 040H THEN,
RESULTB_S l1li FAILI
1* CRe ERROR *1
RXDONE_S = DONE.
OUTPUTCCOMMAND_A_74I = 30H. I*ERRoR RESET*I
END.
ELSE DO.
IF (TEMP AND 20H I = 20H THEN DO,
RESULTS_S = FAIL,
1* RX OVERRUN ERROR*I
RXDONE_S - DONE.
OUTPUTCCOMMAND.JIJ41 = 30H. I*ERRoR RESET*I
END,
.
ENOl

RETURN.
END C!'tA_RX_SPECIAL,

1***********····****************.***.**.**1
1* CHANNEL A RECEIVE CHARACTER AVAILABLE *1
1**.********.*•• * •• ***** ••••• ** ••• ******** 1
CHA_RX_CHAR: PROCEDURE.
OUTPUTCSINGLE_MASKI = CHO_SEL,
RETURN,
END CHA_RX_CHAR.

I*ENABLE RX DMA CHANNEL_I

210403-10

Figure 21. 8274 Typical Interrupt Handling Routines

2-220

intJ

AP-145

It may be recalled that the receiver buffer is three bytes
deep in addition to the receiver shift register. At very
high data rates, it may not be possible to have enough
time to read RR2, enable the DMA controller without
overrunning the receiver. In a case like this, the DMA
controller may be left enabled before receiving the Receive Character Interrupt. Remember, the Rx DMA
request and interrupt for the receive character appears
at the same time. If the DMA controller is enabled, it
would service the DMA request by reading the received
character. This will make the 8274 interrupt line go
inactive. However, the 8259A has latched the interrupt
and a regular interrupt acknowledge sequence still occurs after the DMA controller has completed the transfer and given up the bus. The 8259A will return Level 7
interrupt since the 8274 interrupt has gone away. The
user software must take this into account, otherwise the
CPU will hang up.

be followed up by error recovery procedures which obviously are beyond the scope of this Application Note.
The transmission is terminated when the End of Message (RRO, D6) interrupt is generated. This interrupt is
serviced in the Channel A External/Status Change interrupt procedure. For any other change in external
status conditions, the program is aborted and a FAIL
flag set.

The procedure shown for the Special Receive Condition
Interrupt checks if the interrupt is due to the End of
Frame. If this is not TRUE, the FAIL flag is set and
the program aborted. For a real life system, this must

Main Program
Finally, we will briefly discuss the main program. Figure 22 shows the source program. It may be noted that
the Transmit Under-run latch is reset after loading the
first character into the 8274. This is done to ensure
CRC transmission at the end of the frame. Also, the
first character is loaded from the CPU to start DMA
transfer of subsequent data. This concludes our discussion on hardware and software example. Appendix A
also includes the software written to exercise the 8274
in the vectored mode by disabling the 8259A.

CHA_5DLC_TEST PROCEDURE BYTE PUBLICi
CALL
ENABLE_INTERRUPTS_Si
CALL
INIT_8274_SDLC_Si
ENABLEi
OUTPUHCOMNAND A 741 = 28Hi
RESET TX INT'DMA
OUTPUHCOMNAND-B-741 = 28Hi
BEFORE INITIALIZING a;:37*'
CALL
INIU237oS,
OUTPUHDATA_A]41 = 55H,
'*LOAD FIRST CHARACTER FROM *'
,*CPU *'
TO ENSURE CRC TRANSMISSION, RESET TX UNDERRUN LATCH *'
OUTPUHCOMMAND A 741 = OCOHi
RXDONE_S, TXDONEj=NOT _DONE,
CLEAR ALL FLAGS
RESULTS S=PASSi
FLAG SET FOR MaN ITOR
DO WHILE TXDONE_S=NOT _DONE, '" DO UNTIL TERMINAL COUNT
ENDi

''**

*'

''**

*'*'
*'

'*

DO WHILEIINPUHSTATUS A 741 AND 04HI 0 04Hi
'* WAIT FOR CRC TO GET TRANSMITTED *'
'* TEST FOR TX BUFFFER EMPTY TO VERIFY THIS"
ENDi
DO WHILE RXDONE_S=NOT_DONE;
DO UNTIL TERMINAL COUNT *'
ENDi
CALL
STOP _8237 _Si
END CHA_SDLC_TESTi

'*

210403-11

Figure 22. Typical 8274 Transmit/Receive Set-Up in SOLe Mode

2-221

intJ

AP-145

Vee

CPU

INT~o(1-~------~r---------------1I--------------

INTAP---------~--~~----------~--;_-------------, OTHERS

8085 CPU

8085 INTERRUPT
MODEl

IAPX-88/86
CPU

8088/86
INTERRUPT MODE

8085 INTERRUPT
MODE 3
8088/86
INTERRUPT MODE

8088/86
INTERRUPT MODE

210403-12

Figure 23. 8274 Daisy Chain Vectored Mode
It may be pointed out that lOP to IPI delay time speci-

SPECIAL APPLICATIONS

fication is 100 ns.

In this section, some special application issues will be
discussed. This will be useful to a user who may be
using a mode which is possible with the 8274 but not
explicitly explained in the data sheet.

MPSC Daisy Chain Operation
Multiple MPSCs can be connected in a daisy-chain
configuration (see Figure 23). This feature may be useful in an application where multiple communication
channels may be required and because of high data
rates, conventional interrupt controller is not used to
avoid long interrupt response times. To configure th.e
MPSCs for the daisy chain operation, the interrupt pnority input pins (IPI) and interrupt priority output pins
(IPO) of the MPSC should be connected as shown. The
highest priority device has its IPI pin connected to
ground. Each MPSC is programmed in a vector~d
mode with status affects vector bit set. In the 8085 baSIC
systems, only one MPSC should be programmed in the
8085 Mode 1. This is the MPSC which will put the call
vector (CD Hex) on the data bus in response to the first
INTA pulse (see Figure 15). It may be pointed out that
the MPSC in 8085 Mode I will provide the call vector
irrespective of the state of IPI pin. Once a higher priority MPSC generates an interrupt, its IPO pin goes .inactive thus preventing "ower priority MPSCs from mterrupting the cpu. Preferably the highest priority MPSC
should be programmed in 8085 Mode 1. It may be recalled that the Priority Resolve Time on a given MPSC
extends from the falling edge of the first INTA pulse to
the falling edge of the second INTA pulse. During this
period, no new internal interrupt requests are accepted.
The maximum number of the MPSCs that can be connected in a daisy chain is limited by the Priority Resolution Time. Figure 24 shows a maximum number of
MPSCs that can be connected in various CPU systems.

Number of 8274s
Priority
System
Resolution Time Daisy Chained
Configuration . Min (ns)
(Max)
8086-1
400
4
8086-2
500
5
8086
800
8
8088
800
8
8085-2
1200
12
1920
8085A
19
NOTE:
Zero wait states have been assumed.

Figure 24. 8274 Daisy Chain Operation

Bisync Transparent Communication
Bisync applications generally require that data transparency be established during communication. This requires that the special control characters may not be
included in the CRC accumulation. Refer to the Synchronous Protocol Overview section for a more detailed
discussion on data transparency. The 8274 can be used
for transparent communication in Bisync communications. This is made possible by the capability of the
MPSC to selectively turnon/turnoff the CRC accumulation while transmitting or receiving. In bisync transparent transmit mode, the special characters (DLE,
DLE SYN, etc) are excluded from CRC calculation.
This can be easily accomplished by turning off the
transmit CRC calculation (WR5: D5 = 0) before loading the special character into the transmit buffer. If the
next character is to be included in the CRC accumulation, then the CRC can be enabled (WR5: D5 = 1). See
Figure 25 for a typical flow diagram.

2-222

inter

Ap·145

210403-13

210403-14

Figure 25. Transmit in Bisync Transparent Mode

Figure 26. Receive in Bisync Transparent Mode

During reception, it is possible to exclude received
character from CRC calculation by turning off the Re·
ceive CRC after reading the special character. This is
made possible by the fact that the received data is presented to receive CRC checker 8 bit times after the
character has been received. During this 8 bit times, the
CPU must read the character and decide if it wants to
be included in the CRC calculation. Figure 26 shows
the typical flow diagram to achieve this.
It should be noted that the CRC generator must be

enabled during CRC reception. Also, after reading the
CRC bytes, two more characters (SYNC) must be read
before checking for CRC check result in RRl.

Auto Enable Mode
In some data communication applications, it may be
required to enable the transmitter or the receiver when
the CTS or the CD lines respectively, are activated by
the modems. This may be done very easily by programming the 8274 into· the Auto Enable Mode. The auto
enable mode is set by writing a 'I' to WR3,D5. The
function of this mode is to enable the transmitter automatically when CTS goes active. The receiver is~
abled when CD goes active. An in-active state of CTS
or CD pin will disable the transmitter or the re~eiver
respectively. However, the Transmit Enable bit
(WR5:D3) and Receive Enable bit (WR3:DI) must be
set in order to use the auto enable mode. In non-auto
mode, the transmitter or receiver is enabled if the corresponding bits are ~in WR5 and WR3, irrespective of
the state CTS or CD pins. It may be recalled that any
transition on CTS or CD pin will generate External/
Status Interrupt with the corresponding bits set in
RR I. This interrupt can be cleared by issuing a Reset
External/Status interrupt command as discussed earlier.
Note that in auto enable mode, the character to be
transmitted must be loaded into the transmit buffer af-

ter the CTS becomes active, not before. Any character
, loaded into the transmit buffer before the CTS became
active will not be transmitted.

High Speed DMA Operation
In the section titled Application Example, the MPSC
has been programmed to operate in DMA mode and
receiver is programmed to generate an interrupt on the
first receive character. You may recall that the receive
FIFO is three bytes deep. On receiving the interrupt on
the first receive character, the CPU must enable the
DMA controller within three received byte times to
avoid receiver over-run condition. In the application
example, at 400K baud, the CPU had approximately
60 Il-s to enable the DMA controller to avoid receiver
buffer overflow. However, at higher baud rates, the
CPU may not have enough time to enable the DMA
controller in time. For example, at 1M baud, the CPU
should enable the DMA controller within approximately 24 Il-s to avoid receiver buffer overrun. In mo~t applications, this is not sufficient time. To solve thIS problem, the DMA controller should be left enabled before
getting the interrupt on the first receive character
(which is accompanied by the Rx DMA request for the
appropriate channel). This will allow he DMA controller to start DMA transfer as soon as the Rx DMA
request becomes active without giving the CPU enough
time to respond to the interrupt on the first receive
character. The CPU will respond to the interrupt after
the DMA transfer has been completed and will find the
8259A (see Application Example) responding with interrupt level 7, the lowest priority level. Note that the
8274 interrupt request was satisfied by the DMA controller, hence the interrupt on the first receive character
was cleared and the 8259A had no pending interrupt.
Because of no pending interrupt, the 8259A returned
interrupt level 7 in response to the INTA sequence
from the CPU. The user software should take care of
this interrupt.

2-223

intJ

AP-145

PROGRAMMING HINTS·

Transmit Under-Run/EOM Latch

This section will describe some useful programming
hints which may be useful in program development.

In SDLC/HDLC, bisync and monosync mode, the
transmit underrun/EOM must be reset to enable the
CRC check bytes to be appended to the transmit frame
or transmit message. The transmit under-run/EOM
latch can be reset only after the first character is loaded
into the transmit buffer. When the transmitter underruns at the end of the frame, CRC check bytes are
appended to the frame/message. The transmit under~
run/EOM latch can be reset at any time during the
transmission after the first character. However, it
should be reset before the transmitter under-runs otherwise, both bytes of the CRC may not be appended to
the frame/message. In the receive mode in bisync operation, the CPU must read the CRC bytes and two more
SYNC characters before checking for valid CRC result
in RRI.

Asynchronous Operation
At the end of transmission, the CPU must issue "Reset
Transmit Interrupt/DMA Pending" command in WRO
to reset the last transmit empty request which was not
satisfied. Failing to do so will result in the MPSC locking up in a transmit empty state forever.

Non-Vectored Mode
In non-vectored mode, the Interrupt Acknowledge pin
(INTA) on the MPSC must be tied high through a pullup resistor. Failing to do so will result in unpredictable
response from the 8~74.

Sync Character Load Inhibit

When receiving data in SDLC mode, the CRC bytes
must be read by the CPU (or DMA controller) just like
any other data field. Failing to do so will result in receiver buffer overflow. Also, the End of Frame Interrupt indicates that the entire frame has been received.
At this point, the CRC result (RRI:D6) and residue
code (RRI:D3, D2, Dl) may be checked.

In bisync/monosync mode only, it is possible to prevent
loading sync characters into the receive buffers by setting the sync character load inhibit bit (WR3:DI = I).
Caution must be exerciSed in using this option. It may
be possible to get a CRC character in the received message which may match the sync character and not get
transferred to the receive buffer. However, sync character load inhibit should be enabled during all pre-frame
sync characters so the software routine does not have to
read them from the MPSC.

Status Register RR2

In SDLC/HDLC mode, sync character load inhibit bit
must be reset to zero for proper operation.

HOLC/SOLC Mode

ChB RR2 contains the vector which gets modified to
indicate the source of interrupt (see the section titled
MPSC Modes of Operation). However, the state of the
vector does not change if no new interrupts are generated. The contents of ChB RR2 are only changed when a
new interrupt is generated. In order to get the correct
information, RR2 must be read only after an interrupt
is generated, otherwise it will indicate the previous
state.

Initialization Sequence
The MPSC initialization ·routine must issue a channel
Reset Command at the beginning. WR4 should be defined before other registers. At the end qf the initialization sequence, Reset External/Status and Error Reset
commands should be issued to clear any spurious interrupts which may have been caused at power up.

EOICommand
EOI command can only be issued through channel A
irrespective of which channel had generated the interrupt.

Priority in OMA Mode
There is no priority in DMA mode between the following four singals: TxDRQ(CHA), RxDRQ(CHA),
TxDRQ(CHB), RxDRQ(CHB). The priority between
these four signals must be resolved by the DMA controller. At any given time, all four DMA channels from
the 8274 are capable of going active.

2-224

AP-145

APPENDIX A
APPLICATION EXAMPLE: SOFTWARE LISTINGS

PL/M-86 COMP ILER

leBe e8/4:t 6274 CHANNEL. A SDL.e TEST

SERIES-III PL/M-Bb V2.0 COMPILATION OF MODULE INIT_B274_S
OBJECT MODULE PLACED IN : FI: SINI74. OBJ
COMPILER INVOKED BY:
PLMBb. Bb : FI: SINI74. PLM TlTLE( ISDC BB/4' B274 CHANNEL
A SDLC TEST) COMPACT NOINTVECTOR ROM

1**· •• ••••••• •• •• •••••• • ••• •••• ••••• ·*****•••••••• 1
1*

1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*

./

*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1

INITIALIZE THE B274 FOR SDLC MODE
I. RESET CHANNEL
2. EXTERNAL INTERRUPTS ENABLED
3. NO WAIT
4. PIN 10 aRTS
5. NON-VECTORED INTERRUPT-BOBb MODE
b. CHANNEL A DMA, CH B INT
7. TX AND RX • B BITSICHAR
9. ADDRESS SEARCH MODE
10. CD AND CTS AUTO ENABLE
11. XI CLOCK
12. NO PARITY
13. SDLC/HDLC MODE
14. RTS AND DTR
I'. CCITT - CRC
lb. TRANSMITTER AND RECEIVER ENABLED
17.7EH • FLAG

, •••••••••••• **•••• **••••••••••••••••••• **** •••••• 1
INIT _B274_S:

DO,

.INCLUDE (: FI: PORTS. PLMl

, ••••••••••••• **** ••••••••••••••••••••••••• **.,
~

1*

~

ISBC 8B/45 PORT ASSIGNMENTS

/.

*1
*/

, •••••••••••••••••••••••••••••** ••••• **.*******1
2

DECLARE LIT LITERALLY 'LITERALLY"

3

DECLARE CHO_ADDR
CHO_COUNT
CHI..ADDR
CHI_COUNT
CH2_ADDR
CH2_COUNT
CH3..ADDR
CH3_COUNT
STATUS_37
COMMAND_37
REQUEST _REG_37
SINGLEJ1ASK
MODE,ftEQ_37

1* 8237A-~

PLII1-B6 COMPILER

PORTS

*'
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

'OaOH',
'oa1H',
'OB2H'.
'OB3H',
'OB4H',
'OS'H' ,
'OB6H' ,
'OB7H',
'OBSH',
'OBBH',
'OB9H' ,
'OBAH',
'OBBH',

ISBC BB/4, B274 CHANNEL A SDLC TEST
CLR_BYTE_PTR_37
TEMP _REG _37
MASTER_CLEAR_37
ALL_MASK_37

LIT
LIT
LIT
LIT

'oaCH',

LIT
LIT
LIT

'090H' ,
'091H',
'092H',

'OBDH',
'08DH'.
'OeFH',

1* B254-2 PORTS *1
4

DECLARE CTR_OO
CTR_OI
CTR_02

210403-15

2-225

intJ

AP-145

CONTROLO_54
STATUSO_'4
CTR_IO
CTR_II
CTRI2
CONTROL 1_'4
STATUS I_54

LIT
LIT
LIT
LIT
LIT
LIT
LIT

'093H',
'093H',
'09SH',

LIT
LIT
LIT
LIT

'OAOH',
'OAtH',
'OA2H',
'OA3H',

LIT
LIT
LIT
LIT
LIT
LIT

'ODOH'.
'ODIH'.

LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

'OEOH·.
·OEOH'.
'OEOH·.
'OEOH',

'Oq9H~,

'OqAH',

'09BH'.
'09DH';

1* 8255 PORTS *1

,

DECLARE PORTA_"
PORTB_"
PORTC_'5
CONTROL_55
1* 8274 PORTS *1

I.

;.

DECLARE DATA.J\]4
DATAJI]4
STATUS_A_74
COMMAND_A]4
STATU9J1:...74
COMMAND_B]4

'OD2H',

'OD2H'.
'OD3H'.
'OD3H',

1* 8259A PORTS *1

DECLARE STATUS..p0LL_59
ICWI_'9
OCW2_59
OCW3_59
OCWI_59
ICW2.:,.59
ICW3_'9
ICW4_'9

7

1* 9274 REGISTER BIT ASS I QNI'1ENTS
1* READ REGISTER o *1

9

oi

DECLARE RX.JIIIAIL
I NT ..PEND I Ng
TX_EMPTY
CARR J ERJ)ETECT

SYNC_HUNT
CLEAR_TO_SEND

PLIM-9b COMPILER

LIT
LIT
LIT
LIT
LIT
LIT

'OElH',

·OEIH'.
'OEIH'.
'OElH',

*I
·OIH'.
'02H'.
'04H',
'OBH',

·IOH'.
'20H'.

iSBC 99/45 9274 CHANNEL A SDLC TE;BT
END_OF _TX_MESSAGE LIT
BREAK_ABORT
LIT

'40H'.
'BOH'i

1* READ REIH STER I . ,

9

DECLARE ALL_SENT
PAR ITY _ERROR
RX_OVERRUN
CRC_ERROR
END_OF _FRAME

LIT
LIT
LIT
LIT
LIT

'OlH',

LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

'OOH' ,
'OIH',
'02H',
'03H'.
'04H',
'05H',
·ObH'.
'07H',

'IOH'.
'20H'.
'40H',
'80H',

I . READ REgISTER 2 *1

10

DECLARE TX_B_EMPTY
EXT JI_CHANgE
RX_B_AVAIL
RX_B_SPECIAL
TX_A_EMPTY
EXT _A_CHANgE
RX_A_AVAIL
RX_A_SPECIAL

210403-16

2-226

AP-145

1* 8237 0 IT ASSIGNMENTS *1

11

12
13
14
15
16
17
18

DECLARE CHO_SEL
CHI_SEL
CH2_SEL
CH3_SEL
WRITE _XFER
READ_X FER
DEMAND _MODE
SINGLE_MODE
BLOCK_MODE
SET_MASK
I
2
2
2
3
3
2

DELAY _S: PROCEDURE PUBLIC,
DECLARE D WORD,
0=01
DO WHILE D<800H,
D=0+11
END.
END DELAY _5,

2

DECLARE C

19
20

LIT
, LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

I N IT _827 4 _SDLC _5.

·OOH·.
·OIH·.
·02H·.
·03H·.
'04H',

·08H'.
·OOH'.
'40H',
·80H·.
'04H';

PROCEDURE PUBLIC,

DYTE,

SE-.lECT

PL/M-86 COMPILER

iSDC 88/45 8274 CHANNEL A SDLC TEST

1* TABLE TO INITIALIZE THE 8274 CHANNEL /It AND B *1

1*
1*
21

2

FORMAT IS: WRITE REGISTER. REGISTER DATA
INITIALIZE CHANNEL ONLY

*1

*'

DECLARE TASLE_74_AC.' BYTE DATA
(OOH.18H.
1* CHANNEL RESET *1
OOH.80H.
1* RESET TX CRe *1
PIN lO=RTSD. A OMA. B INT *1
02H.llH.
04H.20H.
1* SDLt tHOLt MODE. NO PARITY *1
07H.07EH.
1* SDLt FLAG *1
OIH.OBH.
1* RX OMA ENABLE *1
O'H.OEBH.
1* DTR. RTS. S TX BITS. TX ENABLE. TX CRt ENABLE *1
I
. DEFAULT ADDRESS *1
06H.5'H,
03H.OD9H.
1* 8 RX BITS. AUTO ENABLES. HUNT MODE. *1
1* RX CRe ENABLE *1
OFFH),
1* END OF INITIALIZATION TABLE *1

'*

22

2

DECLARE TABLE_74_B (*) BYTE DATA

(02H,OOH.
01H. lCH.
OFFH)I

1* INTERRUPT VECTOR *1
1* STATUS AFFECTS VECTOR *1
END */~

'*

1* INITIAL.IZE THE 8254 *1

23

2

24

2

2'

2

26

2

27

2

28
?9
30
31
32

3
3

OUTPUT (CONTROLO_54) =36HI
OUTPUTCCTR_OO) ... LOW(20JI
OUTPUTCCTR_OO) =:I HIGH(20);

'*

3
3
3

'*

BAUD RATE
1* BAUD RATE

40010'. BAUD*I
400lo'.:BAUD*1

INITIALIZE THE 8274 *1

C=O,
DO WHILE TABLE_74_B (C) <> OFFH,
CUTPUTCCOMHAND_B_74)
TABLE_74-.8 CC).
C=C+l.
OUTPUT CCOMMAND_B_74 J :::I TABLE_74_BCC);
C=C+l1
END.

210403-17

2·227

intJ

AP-145

33
34
35
36
37
3B
39
40

3
3
3
3
3
2

41
42
43

2
1

2

2

2

CaO.
DO WHILE TABLE]4.ACC) <> OFFH.
OUTPUTC COMMAND. A ]4 )
TABLE]4-",CC),
C-e+1;
OUTPUTCCOMMAND.A.74) - TABLE_74_A(C) I
C=C+ll
END.
CALL
DELAY.S.
RETURN,
END INIT.B274.SDLC.SI
END INIT.B274.S,

PL/M-B6 COMP ILER

ISDC BB/4:1 B274 CHANNEL A SDLC TEST

MODULE INFORMATION:
CODE AREA SI ZE
CONSTANT AREA SIZE
VARIABLE AREA SIZE
MAX IMUM STACK SIZE
213 LINES READ
o PROGRAM WARNINGS
o PROGRAM ERRORS

= OOABH

16BD
OD
3D
6D

- OOOOH
a 0003H
• 0006H

END OF PL/M-Bb COMPILATION

PL/M-B6 COMP ILER

ISBC BB/4:1 8274 CHANNEL A SDLC TEST

SERIES-III PL/M-B6 V2.0 COMPILATION OF MODULE INIT.B237.CHA
OBJECT MODULE PLACED IN : Fl: SINI37. OBJ
COMPILER INVOKED BY:
PLMB6. B6 : Fl: SINI37. PLM TITLEC iSDC BB/45 B274 CHANNEL A SDLC
TESTI COMPACT NOINTVECTOR ROM
1 •• * ••
1*

·.····****···..·**•••*.** ••••••***••••••••••••••••*••*•••••••••••

'*
1*

B237

INITIALIZATION ROUTINE

FOR DI'IA TRANSFER

**1
*1
*1
*1

1**********·*•• ·****.*****.*.*********••••• ****.*******.*.****** •• **.*.**1
INIT.B237 .CHA:

DOl

'NOLIST
12

INIT.B237.S:

PROCEDURE PUBUC,

13
14

2
2

.5

2

OUTPUT CI'IASTER.CLEAR.37)-OI
OUTPUTCCOI'lMAND.37J - 20H.
OUTPUT (ALLJ1ASK_3? ) -

16
17
18
19
20
21
22
23
24
20
26

2
2
2
2
2
2
2
2
2
2
2

OUTPUTCI'IODE.REG.37) • CSINGLEJ10DE OR WRITE.XFER OR CHO.SEL),
OUTPUTCI'IODE.REG.37) • CSINGLE.I'IODE OR READ.XFER OR CHI.SEL).
OUTPUTC CLRJlYTE.PTR.37 J - O.
OUTPUTCCHO.ADDR) = 00,
1* RECEIVE BUFF AT 900H *1
OUTPUTCCHO.ADDR) = 09HI
OUTPUTCCHO_COUNT) •

OFHI

"ASK AL.L REGUESTS *1

OHI

OUTPUTCCHO.CO_UNTI = 011
OUTPUTCCH1-",DDR) = 00,
OUTPUTCCH1.ADDR) - OBHI
OUTPUT(CH1_CDUNT)

'*

1* EXTENDED WRITE *1

1* TRANSI'IIT BUFF AT BOOH *1

= 010HI

OUTPUTCCH1.COUNTI • OOH,

210403-18

2-228

intJ

AP-145

27

2

2B

2

29

2

I . ENABLE TRANSFER . ,
OUTPUT COMPILATION OF MODULE INTR~_8274_5
OUJEC I f'iODULE PLACED HJ Fl SINTP OD~
C0l1PILEH INVOKED DY
PLM86 At.
Ft SINTR PLM TI1LE.(lSBC 88/45 8274 CHANNEL
A SDLe TEST) COMPACl NOINTVECTOR RnM
: .. 1:1"10 11 • • • 11- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

..-..,
ii-

** ••••• • *1
'fIt/

82"74 INTERRUPT ROUTINE

"

'I
I

" *. ott .. * ........... ** *** **** ..... ** ... * *+* •• -If ******
-It ..

INTR_S27'4_S
00·
toNOL 1ST
DECLARE TEMP a'r'TE.
DECLARE \RESULTS S,TXDONE S,RXDONE 5) BYTE EXTERNAL,
DECLARE INT_VEe POINTER AT (140), DECLARE INT VEe STORE POINTER.
DECLARE MASK_59-0VTE,
'OFFH' ,
LIT
DECLARE DONE
'OOH'.
NOT DONE
LIT
PASS
LIT
'OFFH',
FAIL
'DOH',
LIT

l~

13
14
15
16
17

1****************************1
1* IGNORE INTERRUPT HANDLER *1

1*.******"'****.**************1
IGNORE_INT

18
19

2

20

2

21

2

PROCEDURE,

RESULTS_5 = FAll.
RETURN,
END IGNORE_INT,

210403-19

2-229

inter

AP-145

1** •••• ***.** •• *.*********.* •• **.* •• *** ••••• ** •••••••• *1

1* CHANNEL A EXTERNAL/STATUS. CHANGE INTERRUPT HANDLER *1

1**********************.*********.*.*.****.************1
22
23
24
25
2b
27
28,
29
30
31
32

CHA_EXTERNAL_CHANGE:

2
2

2
2
3
3
3
2
2
2

PROCEDURE.

TEMP = INPUTCSTATUS_A_74l,
1* STATUS REG 1*1
IF (TEMP AND END_OF _TX_MESSAGEl
END_OF _TX_MESSAGE THEN
TXDONE_S=DONE,
ELSE DO,
TXDONE_S=DONE,
RESULTS_S=FAIL,
END,
OUTPUTCCOMMAND_A_74l a 10H, 1* RESET EXT/STATUS INTERRUPTS
RETURN;
END CHA_EXTERNAL_CHANGE;

*'

$E,JECT
Pl.lr1·8b COMP ILER

lEne 89/45 8274 CHANNEL A SOLe TEST

1*********.***** ••• **********.*******.*********************1

I' CHANNEL A SPECIAL RECEIVE CONDITIONS INTERRUPT HANDLER *1

1*****.**********.********** •• ** •• ***.*.*******************1
CHA_R X_SPEC I AL

33
3.
35
36
37
38
39
40
41
42
43
,4.
46
47
48
49
50
51
52

2
2
2

:3
3
3
3
3
2
3
4
4
4
4
3
2
2

PROCEDURE,

OUTPUT (COMI1AND_A_74 l = 1;
TEMP = INPUT(STATUS_AJ4l;
IF (TEMP AND END_OF _FRAMEl = END_OF ]RAME THEN
DO,
IF (TEMP AND 040H I
040H THEN
RESULTS_S = FAIL,
1* CRC ERROR
RXDONE_S • DONE.
OUTPUTC COMMAND_A_74 I
30H, I*ERROR RESET-I
END;
ELSE DO,
IF  04H.
1* WAIT FOR CRC TD ClET TRANSMITTED *1
1* TEST FDR TX BUFFFER EMPTY TO VERIFY THIS*I
END.
DO WHILE RXDONE_S*NOTJ)ONE.
1* DO UNTIL TERMINAL COUNT*I

47

2

CALL

STOP _8237 _S.

4B

2

CALL

DISABLE_INTERRUPTS_S.

49

2

CALL

VER I FY _ TRANSFER_S.

'0

2

RETURN RESUL TS_S.

"'2

2
1

1* DO UNTIL TERMINAL COUNT*I

ENOl

END CHA_SOLC _TEST.
END STEST.

MODULE INFORMATION:
CODE AREA SIZE
CONSTANT AREA SIZE
VARIABLE AREA SIZE
MAUMUI! STACK SIZE
198 LINES READ
o PROIIRAM WARNINQS
o PROIIRAI! ERRORS

= 0063H
- OOOOH
- 0003H
• 0004H

99D
00
3D
40

END OF PL/M-B6 COMPILATION

PLIM-86 COMPILER

iSBC 88/4:1 S274 CHANNEL A SDLC TEST

SERIES-III PL/M-86 V2,0 COMPILATION OF MODULE VECTORJ10DE
OB.JECT MODULE PLACED IN : Fl: VECTOR, OB.J
COMPILER INVOKED BV:
PLMB6,86: Fl: VECTOR, PLM TITLEC ISBC B8/4:1 8274 CHANNEL A SDLC TEST)

1•••** ••••••••• **••• ** ••••••••••••••••••••••••••••••••••• **••••••***1
n
H
1*
1*
1*

n

8274 INTERRUPT HANDLINO ROUTINE FOR
8274 VECTOR MODE
STATUS AFFECTS VECTOR

*1
*1
*1

H

/ ••••••••** ••••••••••••••••••••••••••••••••••••••••••••••••••••••••• ,
210403-23

2-233

intJ

AP-145

1*
1*
1*
1*

THIS IS AN EXAMPl.E OF HOW B274 CAN BE USED IN VECTORED MODE.
THE lSDCBB/45 BOARD WAS REWIRED TO DISABLE THE PIT .B259A AND
ENABLE THE B274 TO PLACE ITS VECTOR ON THE DATABUS IN RESPONSE
TO THE INTA SE()UENCE FROM THE BOBB. OTHER MODIFICATIONS INCLUDED
1* CHANGES TO 8274 INITIALIZATION PROORAM (SINI74) TO PROORAM 9274
1* INTO VECTORED MODE (WRITE REGISTER 2A D5~1).
VECTOR_MODE:
_NOLIST
12
13
14

*'

*1
*1
*1
*1

*1 .

DO,

DECLARE TEMP BYTE,
DECLARE (RESUL TS_S. TXDONE. RXDONE) BYTE EXTERNAL,
DECl.ARE DONE l.ITERAl.LY ·OFFH'.
NOT_DONE LITERALLV 'OOH',
PASS
LITERALLY ·OFFH'.
FAIL
LITERALLY 'DOH'.

/********.****************.*.**.**********************.*.*.***** •• *.*.*.,

1*
1*
I
15
16
17
IB

TRANSMIT INTERRUPT CHANNEL A INTERRUPT WIL.L. NOT DE SEEN IN THE *1
OMA OPERATION.
*1

.*********** •• ********************* •• ***********.******.* .****.********1
TX_INTERRUPT _CHA: PROCEDURE INTERRUPT B4,
OUTPUT(COMMAND_A_74) ,- 001010008.
OUTPUT CCOMMAND_A_74) • 0011100001
END TX_INTERRUPT _CHA,

2
2

2

I-RESET TXINT PENDINQ_I

/*Eol*1

1*********.*.***********************************************************1
'*
EXTERNALISTATUS INTERRUPT PROCEDURE: CHECKS FOR END OF MESSAgE *1

1*
,1*
1*

ONLY. IF THIS IS NOT TRUE THEN THE FAIL FLAG IS SET. HOWEVER.
A USER PROGRAM SHOULD CHECK FOR OTHER EXTISTATUS CONDITIONS
Al.SO IN RRI AND THEN TAKE APPROPRIATE ACTION BASED ON THE
APPLICATION.

*1
*1
*1

1*
*1
1***********************************************************************1
19
20
21

2

22
23

2
2

24

3

I

2

EXT _STAT _CHANGE_CHA: PROCEDURE INTERRUPT 95,
TEMP
- INPUT( STATUS_A_74)'
IF (TEMP AND END_OF _TX_MESSAQE)
END_OF _TX_MESSAQE THEN
TXDONE = DONE.
El.SE DO,
TXDONE =- DONE.

=

PLIM-B6 COMP Il.ER

25
26

3
3

27
2B
29
30

2
2
2
2

iSBC BB/4S e274 CHANNEl. A SDLC TEST

RESUL TS_S - FAIL,
END,
OUTPUTCCOMMAND_A_74) • 0001000001
OUTPUT(COMMAND_A]4) = 0011 I OOOB ,
RETURN,
END EXT_STAT _CHANGE_CHAI \

I*RESET EXT STAT INT*I

I*EOI*I

1*******************.*******************.*******************************1
1*
RECEIVER CHARACTER AVAILABLE INTERRUPT WILL APPEAR ONLY ON FIRST*I
1*

RECEIVE CHARACTER.

SINCE DMA CONTROLLER HAS BEEN ENABLED BEFORE *1

1*
THE FIRST CHARACTER IS RECEIVED. THE RECEIVER REOUEST IS
*1
1*
SERVICED BY THE DMA CONTROLLER.
*1
1***************************************************** ****************.*/
31

I

32

2

33
34

2
2

RX_CHAR_AVAILABLE_CHA: PROCEDURE INTERRUPT 86.
OUTPUT (COMMAND_A_74) • 001110008;
/*EOI*/
RETURN,
END RX_CHAR_AVAILAOLE_CHA; .
• EJECT

210403-24

2-234

AP-145

PL/M-Bb COMPILER

lSDC 88/45 8214 CHANNEL A SOLe TEST

/ *.* ..............................* ................... * ....... * ••••••••••••• /

'*

/*
/.

SPECIAL RECEIVE CONDITION INTERRUPT SERVICE ROUTINE CHECKS FOR */
END OF FRAME OIT ONLY.

SEE SPECIAL SERVICE ROUTINE FOR NON-

*'

VECTORED MODE FOR CRC CHECK AND OVERRUN ERROR CHECK
*/
/* •••••••••••••••••••••••••• ** ••••• * ••••• **** •••• * •• *.* ••••••••••••••••• /
35

SPEC IAL_RX_CONDITlON3HA. PROCEDURE INTERRUPT B7.

36
37
39
39
40
41
42
43
44
45
46
47

2
2
2
2
2
3
3
3
2
2
2
2

4B
49
50
51
52
53
54
95

I
2
2

56

2
2
2
2
2

QUTPUT(COMMANO A 74) • I.
TEMP
INPUTCSTATUS-.AJ4).
IF (TEMP AND END OF FRAME)

I_POINTER 1*'

=

RXDONE

END_OF _FRAME THEN

= DONE;-

ELSE DO,
RXDONE = DONE,
RESUL T5 5 = FAIL.
END,
OUTPUTCCOMMAND_A_74) z:: 001100000.
OUTPUT CCOMMAND_A_74) Q 001110000.
RETURN,
END SPECIAL_RX_CONDITION_CHAi

,.ERROR RESET_'
I*E01*1

ENABLE_INTERRUPTS: PROCEDURE PUBLIC.

DISABLE,
CALL SETS INTERRUPT< 94.
CALL SETSINTERRUPT<95.
CALL SET. INTERRUPT (86.
CALL SETSINTERRUPT<97.
RETURN,
END ENABL.E_INTERRUPTS,

TX_INTERRUPT _CHA),
EXT _STAT _CHANQE_CHAI'
RX_CHAR_AVAI L.ADL.E_CHA) I
SPECIAL_RX_CONDITION_CHA),

1***..*******···············*···**···**·····**··*····*...* •••**.* ...........1

END VECTOR_MODE,

/ ••• * •••••••••••••••••••••••••••••••••••• *•• ***.* •••• *** •••••••••••••••••• *./

MODULE INFORMATION:
CODE AREA SI ZE
=
CONSTANT AREA SIZE =
VARIABL.E AREA SIZE.
MAX IMUM STACK SIZE =
226 LINES READ
o PROGRAM WARNINGS
o PROGRAM ERRORS

012EH
OOOOH
000lH
OOIEH

3020
00
10
300

END OF PLIM-B6 COMPILATION

210403-25

2-235

Ap·145

APPENDIX B
MPSC READ/WRITE REGISTER DESCRIPTIONS
WRITE REGISTER 0 (WRO)
MSB

LSB

1071061051041031021011001

I
o
o
o
o
1
1
1
1

o
o
1
1

0
1
0
1

L.OMMANO STATUS POINTER
REGISTER POINTER

00 01
1
1
0
0
1
1

0
1
0
1
0
1

NULL COOE
SENO ABORT (SOLC)
RESET EXT STATUS INTERRUPTS
CHANNEL RESET
ENABLE INTERRUPT ON NEXT RX CHARACTER
RESET TXINT OMA PENOING
ERROR RESET
ENO OF INTERRUPT (Ch. A only)

NULLCOOE
RESET RX CRC CHECKER
RESET TX CRO GENERATOR
RESET TX UNOERRUN EOM LATCH

210403-26

WRITE REGISTER 1 (WR1)

I
o
o
1

EXT INTERRUPT
ENABLE
Tx INTERRUPT
OMAENABLE
STATUS AFFECTS VECTOR 1 VARIABLE VECTOR
(CHB ONLY)
0 FIXED VECTOR
(NULL COOE CH A)
0 RxINT/OMA OISABLE
1 RxlNT ON FIRST CHAR OR SPECIAL CONOITION
OINT ON ALL Rx CHAR (PARITY AFFECTS VECTOR) OR
SPECIAL CONOITION
1 INT ON ALL Rx CHAR (PARITY OOES NOT AFFECT
VECTOR) OR SPECIAL CONOITION

1 WAIT ON Rx, 0 WAIT ON Tx
MUST BE ZERO
WAIT ENABLE, 1 ENABLE, 0 OISABLE
210403-27

2-236

AP-145

WRITE REGISTER 2 (WR2): CHANNEL A

o

0 8085 MODE 1
1 8085 MODE 2
0 8086/88 MODE
1 ILLEGAL

o
1

1

- J ~~~T~:~fol~lg~~~:JRUPT
-

_

MUST BE ZERO

1 PIN 10 SYNDET6
PIN 10 RTSB

o

210403-28
'External Slatus Interrupt only if EXT Interrupt Enable (WR1: DO) is set.

WRITE REGISTER 2 (WR2): CHANNEL B
MSB

WRITE REGISTER 3 (WR3)
LSB

LSB

Inl~I~lwl~I~I~I~1

ADDR SRCH MODE (SDLC)

-

Rx CRC ENABLE

INTERRUPT
VECTOR"

ENTER HUNT MODE

210403-29

AUTO ENABLES

o

0 RxS BITS/CHAR
1 Rx7 BITS/CHAR

o

Rx6 BITS/CHAR

1 Rx8 BITS/CHAR

210403-30

2-237

AP-145

WRITE REGISTER 4 (WR4)

WRITE REGISTER 5 (WR5)

1 ENABLE PARITY
o DISABLE PARITY

Tx CRC ENABLE

EVEN PARITY
ODD PARITY

o
o
1
1

o
o
1
1

o
o
1
1

o
1
o
1

0
1
0
1

0
1
0
1

RTS

'----- rgk8~SgE)16

ENABLE SYNC MODES
1 STOP BIT
1.5 STOP BITS
2 STOP BITS

' - - - - - - Tx ENABLE

8 BIT SYNC CHAR
16 BIT SYNC CHAR
SOLC/HOLC(Olllll10)FLAG
1 EXTERNAL SYNC MODE

' - - - - - - - SENO BREAK

o

0

1

0

o

Xl CLOCK
X16CLOCK
X32 CLOCK
X64CLOCK

1

1

1

TxS BITS OR LESS/CHAR
Tx7 BITS/CHAR
TxB BITS/CHAR
TxB BITS/CHAR

OTR
210403-31

210403-32

WRITE REGISTER 6 (WR6)
MSB

WRITE REGISTER (WR7)
MSB

LSB

1071061051041031021011001

.

L

LSB

1071061051041031021011001

.

LEAST SI:NIFICANT
SYNC BYTE (AOORESS
IN SOLC/HOLC MOOE)

L

MOST SI:NIFICANT
SYNC aYTe (7EH
IN SOLC/HDLC MODE)

210403-33

210403-34

READ REGISTER 0 (RRO)
MSB

LSB

107 106 1OSI 04 103 102 101100 1

L=

Rx CHAR AVAILABLE
INT PENOING (CHA ONLY)
Tx BUFFER EMPTY
CARRIER OETECT
SYNC/HUNT

CTS
}
TxUNDERRUN/EOM

EXTERNAL
STATiiS
INTERRUPT MOOE

BREAK/ABORT
210403-35

2-238

inter

AP·145

READ REGISTER 1 (RR1): (SPECIAL RECEIVE CONDITION MODE)

:c

MSB

LSB

1071061051041031021011001

o

o
o

LALLSENT
I FIELO BYTE
PREVIOUS BYTE

0 0
0 1

2
0

1

0

0

o 1 1
1 0 0
1 0 1
1 1 0

I FIELO BYTE
2NO PREVIOUS BYTE

!}

0
0
0
0

111

3
7

RESIOUE OATA
BITS CHAR
MOOE

5
8

1

' - - PARITY ERROR
Rx OVERRUN ERROR
-

CRC/FRAMING ERROR

'--- ENO OF FRAME (SOLC HDLC MODE)

210403-36

READ REGISTER 2 (RR2) CHANNEL B ONL V
MSB

LSB

!V7! v61 vsl V4-!V3-!v2-!v1-! vo-I
\"

,;

1

INTERRUPT

-VARIABLES IN
STATUS AFFECTS
VECTOR MODE

L..
______

VECTOR

210403-37

REFERENCES
1. IBM Document No. GA27-3004-2: General Information-Binary Synchronous Communications

2. Application Note AP134: Asynchronous Communication with the 8274 Multiple Protocol Serial Controller.
Intel Corp., Ca.

3. 8274 MPSC Dat~ Sheet, Intel Corporation, Ca.
4. iSBC 88/45 Hardware Reference Manual, Intel
Corp., Ca.
S. Computer Networks and Distributed Processing by
James Martin. Prentice Hall, Inc., N.J.

2-239

APPLICATION

AP-222

NOTE.

October 1989

Asynchronous and SOLC
Communications with 82530

DFG TECHNICAL MARKETING

Order Number: 231262-004
2-240

intJ

AP-222

INTRODUCTION

I. SCC Port Definition

INTEL's 82530, Serial Communications Controller
(SCC), is a dual channel, multi-protocol data communications peripheral. It is designed to interface to high
speed communications lines using asynchronous, byte
synchronous, and bit synchronous protocols. It runs up
to 1.5 Mbits/sec, has on-chip baud rate generators and
on-chip NRZI encoding and decoding circuits-very
useful for SOLC communication. This application note
shows how to write I/O drivers for the 82530 to do
initialization and data links using asynchronous
(ASYNC) and SOLC protocols. The appendix includes
sections to show how the on-chip baud rate generators
could be programmed, how the modem control pins
could be used, and how the 82530 could be interfaced
to INTEL's 80186/188 processors.

The Figure 1 shows how the 4 ports (2 per channel) of
the SCC can be defined. Note that the sequence of ports
in the ascending order of addresses is not the one that is
normally expected. In the ascending order it is: command (B), data (B), command (A) and data (A). In an
80186 - 82530 system, the interconnection is as follows:

This article deals with the software for the following:

The SCC has 16 registers on each of the channels (A
and B). For each channel there is only one port, the
command port, to access all the registers. The register
#0 can be always accessed directly through the command port. All other registers are accessed indirectly
through register #0; First, the number of the register to
be accessed is written to the register # 0 - see the statement, in Figure 2: 'output (ch_Lcommand) = re~
no and Ofb'. Then, the desired register is written to or
read out. The Figure 2 shows 4 procedures: rra and
wra, for reading and writing channel A registers; rrb
and wrb, for reading and writing channel B registers.
The read procedures are of the type 'byte' - they return
the contents of the register being read. The write procedures require two parameters - the register number and
the value to be written.

1.
2.
3.
4.
5.
6.
7.
8.
9.

SCC port definition
Accessing the SCC registers
Initialization for ASYNC communication
ASYNC communication' in polling mode
ASYNC communication in interrupt mode
Initialization for SOLC communication
SOLC frame reception
SOLC frame transmission
SOLC interrupt routines

The description is written around illustrations of the
actual software written in PLM86 for a 80186 - 82530
system.

80186 pins

PGSn
A1
A2

GS
DIG
AlB

RD

RD

WR

WR

82530 pins

2. Accessing the SCC Registers

1*----·---·--.. ------ ------- .--- -- .•. --- - ----.-- ---- --.----- ------------------------*1
declare ch_b_command
eh_b_data
eh_a_command
c:h_a_data

literally
literally
literally
literally

'pc55
'pes5
'pcs5
'pes5

1*
1*
1*
+ 6'. 1*

+ 0',
+ 2',
+ 4',

scc
sec
sec
sec

channel_b
ehannel_b
channel __a
ehannel_a

command word*/
d.lta word *1
command word
data word

*1
*1
1*--------- ----------------------.--------------------.-----------------------*1
231262-1

Figure 1. see Port Definition

2-241

intJ

AP-222

I*-----------------------------------~--------------------------------------*1

1*

read .elected scc register

*1

rra: procedure (reg_no) byte,
declare reg_no bvtei
i~ (reg_no and Of h) <> 0
then output(ch_a_command)
reg_no and
return input(ch_a_command),
end rra,

O~h;

rrb: procedure (reg_no) bVte,
declare reg_no byte;
if (reg_no and Of h) <> 0
then output (ch_b_command)' = reg_no and O'h,
return input(ch_b_command),
end rrb;

1*

write selected scc register

*1

wra: procedure (reg_no,' value),
declare reg_no byte,
declare value bvte;

<> 0
then output (ch_a_command)
reg_no and O'h;
output (ch_a_command) .. value,
end wra,
i f .(reg_no and Of h)

wrb: procedure (reg_no, value),
declare reg_no byte,
declare value byte,
if (reg_no and Of h) <> 0
then output (ch_b_command) - reg_no and OFh,
output (ch_b_command) .. value,
end wrb;

1*--------------------------------------------------------------------------*1
231262-2
Figure 2. Accessing the see Registers

2-242

inter

AP-222

3. Initialization for ASYNC Operation
In the following example, channel B of the SCC is used
to perform ASYNC communication. Figure 3 shows
how the channel B is initialized and configured for
ASYNC operation. This is done by writing the various
channel B registers with the proper parameters as
shown. The comments in the program show what is
achieved by each statement. After a software reset of
the channel, register #4 should be written before writing to the other registers. The on-chip Baud Rate Generator is used to generate a 1200 bits/sec clock for both
the transmitter and the receiver. The interrupts for
transmitter and/or receiver are enabled only for the
interrupt mode of operation; for polling, interrupts
must be kept disabled.

4. ASYNC Communication in Polling
Mode
Figure 4 shows the procedures for reading in a received
character from the 82530 (sec_in) and for writing out
a character to the 82530 (scc_out) in the polling mode.
The sec_in procedure returns a byte value which is the
character read in. The receiver is polled to find if a
character has been received by the SCC. Only when a
character has been received, the character is read in
from the data port of the SCC channel B.
The scc_out procedure requires a byte parameter
which is the character being written out. The transmit-

1* ---.----.-----.-- -'- -.--- ---.- ---....----.------------------------ -------.------------* I

1* scc ch B register initialization for ASVNC mode
call
call
call
call
call
call
call
call
call
call
call
call
call
call

wrbC09, 01000000b),
wrb (04. 11001110b),
wrbC02. 00100000b);
wrb (03. 11000000b),
wrb(05, 01100000b),
wrbC06. OOOOOOOOb),
wrbC07. OOOOOOOOb),
wrb(09. OOOOOOOlb),
wrb(10. OOOOOOOOb)1
wrb(11. 010l0110bli
wrb(12. 000 11000tiI,
wrbC13. OOOOOOOOb),
wrb(14. 00000011b)1
wrb(15. OOOOOOOObl1

*/

/* channel B reset */
/* 2 stop, no parity. brfl
/* vector
20h *1

=

= 64x */

1* rx B bits/char, no auto-enable *1
/* tx B bits/char */

1* vector includes status *1
1* rxc = tXt = BRG • trxc = BRG out */
1* to generate 1200 baud. x64 @ 4 mhz *1
1* BRG source = SYS eLK. enable BRG *1
1* all ext status interrupts off *1

1* enables *1
call wrb(03.
call wrb (05.

11000001b),
11101010b) I

1* scc-b receive enable *1
1* sc c-b transmi t enab Ie. dtr on. rts on *1

1* enable interrupts - only for interrupt driven ASYNC 110 *1
call wrbC09.
call wrb(Ol.

00001001b),
00010011b),

1* master IE. vector includes status *1
1* tx • rx. ext interrupts enable */

/ *--------------------------------. --------------------------------------------* I
231262-3

Figure 3. Initialization for ASYNC Communication

2-243

AP-222

1*---------. ------------.... ----.-----. ---- --------.... ----- ----------- ------------* I
1* scc data character input from channel B *1
scc_in: procedure byte;
declare char byte;
do while (input(ch_b_commandl and lh) = Oi endi
char
input(ch_b_datali
1* if rx data character is available
return chari
1* then input it to buffer *1

=

1*

sec data character output to channpl B

*1

*1

sec_out: procedure (char)i
declare char byte;
do while (input(ch_b_command) and 4hl = 01 end;
output(ch_b_datal = char; 1* if tx buff empty then transfer the
1* data character to tx buff *1

*1

1*-------_·_·_--------------------_·_------------------------·-·----·---------------*1
231262-4

Figure 4. ASYNC Communication In Polling Mode

ter is polled for being ready to transmit the next character before writing the character out to the data port of
see channel B.

Includes Status' (VIS) mode. is set - WR9 =
XXXOXXOI. Vectors and the associated events are:
Vector

Typical calls to these procedures are:

Procedure

Event Causing Interrupt

20h

txintrj

ch

22h

esLb

chj - extemal/status change

24h

rxintr b

ch

26h

srcj

ch

b - special receive condition

5. ASYNC Communication in Interrupt
Mode

28h

!xintr a

ch

a - transmit buffer empty

2ah

esLa

ch

a - external! status change

In contrast to polling for the receiver and/or the transmitter to be ready with/for the next character, the
82530 can be made to interrupt when it is ready to do
receive or transmit.

2ch

rxintr_a

cIL-a - receive character available

2eh

src

ch

abc_variable = scc~n;
call scc_out (xyz-variable);

The on-chip interrupt controller of the see can be
made to operate in the vectored mode. In this mode, it
generates interrupt vectors that are characteristic of the
event causing the interrupt. For the example here, the
vector base is programmed at 20h and 'Vector

a

b - transmit buffer empty
b - receive character available

a - special receive condition

NOTE:
Odd vector numbers do not exist.

Figure 5 shows the interrupt procedures for the channel
B operating in ASYNe mode. The transmitter buffer
empty interrupt occurs when the transmitter can accept
one more character to output. In the interrupt procedure for transmit, the byte char_out_S30 is output.
Following this, is an epiloge that is common to all the

2-244

Ap·222

interrupt procedures; the first statement is an end of
interrupt command to the 82530 - note that it is issued
to channel A - and the second is an End of Interrupt
(EOI) command to the 80186 interrupt controller
which is, in fact, receiving the interrupt from the 82530.

The receive buffer full interrupt occurs when the receiver has at least one character in its buffer, waiting to be
read in by the CPU.
The esLb is not enabled to occur and src_b cannot
occur in the ASYNC mode unless the receiver is overrun or a parity error occurs.

1*-----------·-------------·-------------·-----------·---------------·-----------*1
1*

channel B interrupt procedures
procedure

call w... aCOO,38h).
output (eoiT_18b)
... etu ... n;
end txint ... _b.
p... ocedure

inte ...... upt 20h.

8000h.

rxint ... _b:

p ... ocedu ... e

call w... aCOO,38h);
output (eoi ... _186)
.... tu ... n;
end ... xint ... _bl
p ... ocedu ... e

8000h;

reset highest IUS *1
non specific EOI *1

1*

reset ESI

*1

1*
1*

reset highest IUS *1
non specific EOI *1

inter ... upt 24h;

BOOOh;

1* ... eset highest IUS *1
1* non specific EOI *1

inter ... upt 26h;

call wrb(00,30h).
call w... aCOO,3Bh).
output (eoir_186)
return.
end s ... c_b;

1*
1*

inter",upt 22h;

call w... bCOO, 10h);
call w... a(00,38h);
output (eoi ... _186)
... eturn;
end esi_b;

*1

= BOOOh.

1*

e ...... o... reset

*1

1*
1*

reset highest IUS *1
non specific EOI *1

1*---------------------------------------------------------------------------*1
231262-5

Figure 5. ASYNC Communication in Interrupt Mode

2-245 .

inter

AP-222

ed on the RxDA pin, it goes from the Hunt to the Sync
mode. It receives the frame and the end of frame interrupt (src_b, vector = 2eh) occurs.

6. Initialization for SOLC
Communication
Channel A of the SCC is programmed for being used
for SDLC operation. It uses the DMA channels on the
80186. Figure 6 shows the initialization procedure for
channel A. The comments in the software show the
effect of each statement. The on-chip Baud Rate Generator is used to generate a clock of 125 kHz both for
reception and transmission. This procedure is just to
prepare the channel A for SDLC operation. The actual
transmission and reception of frames is done using the
procedures described further.

8. SOLC Frame Transmission

7. SOLC Frame Reception
Figure 7 shows the entire set-up necessary to receive a
SDLC frame. First the DMA controller is programmed
with the receive buffer address (@rx_butl), byte count,
mode etc and is also enabled. Then a flag indicating
reception of the frame is reset. An Error Reset command is issued to clear up any pending error conditions. The receive interrupt is enabled to occur at the
end of frame reception (Special Receive Condition);
lastly, the receiver is enabled arid put in the Hunt mode
(to detect the SDLC flag). When the fi\"St flag is detect-

Figure 8 shows the procedure for transmitting ~ SDLC
frame once channel A is initialized. The DMA controller is initialized with the transmit buffer address
(@tx_buff(l» - note, it is the second byte of the transmit buffer - and the byte count - again one less than the
total buffer length. This is done because the first byte in
the buffer is output directly using an I/O instruction
and not by DMA. Then the flag indicating frame transmitted is reset. The events following are very critical in
sequence:
a. Reset external status interrupts
b. Enable the transmitter
c. Reset transmit CRC
.d. Enable. transmitter underrun interrupt
e. Enable the DMA controller
f. Output first byte of the transmit block to data port
g. Reset Transmit Underrun Latch

I*----------------------------------------------~---------------------------*1

scc_init_a:

1*

procedure;

scc ch A register initialization for SOle mode
call
call
caU
call
call
call
call
call
call
call
call
call
call

1*

1111'41(09.
1111' a (04.
1111'41(01.
1111' a (03,
1111' a (05.
1111'01(06.
1111' a (07.
1111'.( 10.
1111'.( 11.
1111'41 ( 12.
1111'41 ( 13.
l111'a (14.
1111'41 ( 15.

enables

10000000b) ;
00100000b )1
01100000b) ;
11000000b) I
011 OOOOOb ) I
01010101b )1
011U110b)1
10000000b) I
01010110b) I
00001110b) I
OOOOOOOOb ) ;
0000011 Ob ) ;
OOOOOOOOb ) I

*1

1* channel A reset *1
1* SOlC mode *1
1* OMA for Rx *1
1* e bit Rx char. Rx disable *1
1* e bit Tr char. Tx disable *1
1* node address *1
1* SOle flag *1
1* preset eRe, NRZ encoding *1
1* rxc • txc = BRG trxc = BRG out *1
1* to .enerate 125 Kbaud. xl @ 4 mhz *1

.

1*
1*

BRG source = SVS ClK. OMA for Tx
all ext status interrupts off *1

*1

*1

call 1111'01(14. 00000111b) ;
call 1111'01(01. 11100000b) I
call 1111'01(09. 00001001 b);

1*
1*
1*

enable : BRG *1
enable : drell. *1
master IE. vector include. .tatus

*1

end scc_init_a;
1*------------------------------------------------7--------~----------------*I

231262-6

Figure 6. Initialization for SOLe Communication

2-246

intJ

AP-222

1*------------- ------------.. ------------.-----. -- .----------------------------- --* 1
rx_inl.t: procedurel
declare dma_O_mode literally '1010001001000000b';
dest=M( inc I. sync"src, TC. noint. priDrity. byte *1

1* src=IO.

outword (dma_O ._dp 1)
1 D..,16 «!r x _b uff);
outwDrd(dma_O_dph)
high16«!rx_buff);
outword(dma_O_spl) .. ch_a_data;
Dutword(dma_O_sph) = 0;
outword(dma_O_tc)
blDck_length + 2;
Dutword (dma_o_cw) = dma_O_mode Dr 0006h;

1* +2 fDr CRC *1
1* start DMA channel 0 *1

1* reset frame received flag *1

call wra(QO.30h)1
call wra(Ol. I1111DDlb);
call wra(Q3. 1101QDOlbl;

1

1* errDr reset *1
1* sp. cond intr only,

1*

ext int enable *1
enable receiver, enter hunt mDde *1

*---------------------------.------------.------------- -----------.-----------* 1
231262-7

Figure 7. SDLC-DMA Frame Reception

1*-------------------------------_·_-------------------·------------------------*1

tx_init:

procedure;

declare dma_l_mode literally 'OODI011DIODOOODOb';
1* src=M( inc I, dest=IO, sync=dest. TC. noint, nopriDr. byte *1
IOUI16«ttx_buff( 1) I;
outword (dma.J_.sp I I
outword(dma_l_sph)
high16«!tx_buff(11);
outword(dma_l_dpll = ch_a_data;
outword(dma_l_dph)
.0;
outword(dma_l_tc)
block_length - 1;
1* -1 for first byte *1
'rame_tx
call
call
call
call

= .0;

1* 'reset 'rame transmitted flag *1

wra(DD. OODIDDODb) ;
wra(Q5, QllD1Dllb);
wra(DD, 10101DODb);
wra(15. 01DDOOOOb) ;

outword(dma_l_Cl'/) .. dllla_l_mode
output(ch_a_data)
tx_buff(OI/
call wra(QD, 11DOOOOObl;

=

1*
1*
1*
1*
01'

reset ESl *1
enable transmitter *1
reset tx CRe, TxINT pending *1
TxU int *1
enable
DOD6h;
1* start DMA channel
*1
1* first byte - address field ~I
1* Reset Tx Underrun latch *1

1*------- ----- ---- -- ---'.--. -,--- - ----------------- ----------- ------------

------* 1
231262-8

Figure 8. SDLC-DMA Frame Transmission

2-247

intJ

AP-222

1*--------------------------------------------------------------------------*1
1* channel A interrupt procedures *1
i n.terrup t 2Sh I
call wra(OO,38h)1
output (eoir_1Sh)
returnl
end txintr_al
procedure

• 8000hl

interrup~

=

procedure
call wra(OO,38h)1
output (eoir_1Sh)
returnl
end rx int-r _al

2ahi

1* reset ESI *1
1* read in status *1
1* set frame transmitted flag *1

call wra(OO,10h)1
tx_stat = rra(O);
frame_tx
Offhl
call wra(OO,38h)1
output (eoir_1Sh)
returnl
end es i_al

1* reset highest IUS *1
1* non specific EOI *1

• SOOOhl

1* reset highest IUS *1
1* non specific EOI *1

interrupt 2chl
• SOOOhl

1* reset highest IUS *1
1* non specific EOI *1

interrupt 2ehl

=

rx_stat
rra(l)1
call wra(OO,30h)1
call wra(03,11000000b)1
frame_recd = Offhl
call wra(OO,3Sh)1
output (eoir_1Sh)
returnl
end src_al

• 8000hl

1* error reset *1
1* disable rx *1
1* set frame received flag *1
1* reset highest IUS *1
1* non specific EOI *1

1*--------------------------------------------------------------------------*1
231262-9

Figure 9. SDLC-DMA Interrupt Routines

2·248

inter

AP-222

The frame gets transmitted out with all bytes, except
the first one, being fetched by the SCC using the DMA
controller. At the end of the block the DMA controller
stops supplying bytes to the SCC. This makes the transmitter underrun. Since the Transmitter Underrun
Latch is in the reset state at this moment, the CRC
bytes are appended by the SCC at the end of the transmit block going out. An External Status Change interrupt (esLa, vector = 2ah) is generated with the bit for
transmitter underrun set in RRO register. This interrupt occurs when the CRC is being transmitted out and
not when the frame is completely transmitted out.

9. SOLC Interrupt Routines
Figure 9 shows all the interrupt procedures for channel
A when operating in the SDLC mode. The procedures
of significance here are esi_a and src_a.
The end of frame reception results in the src_a procedure getting executed. Here the status in register RRI
is stored in a variable rx_stat for future examination.
Any error bits set in status are reset, receiver is disabled
and the flag indicating reception of a new frame is set.

examination and the flag indicating transmission of the
frame is set.
End of frame processing is required after both of these
interrupt procedures. It involves looking at
rx_stat and tlL-stat and checking if the desired operation was successful. The buffers used, may have to be
recovered or new ones obtained to start another frame
transmission or reception.

CONCLUSIONS
This article should ease the process of writing a complete data link driver for ASYNC and SDLC modes
since most of the hardware dependent procedures are
illustrated here. It was a conscious decision to make the
procedures as small and easy to understand as possible.
This had to be done at the expense of making the procedures general and not dealing with various exception
conditions that can occur.

REFERENCES

The esi_a procedure is executed· when CRC of the
transmitted frame is just going out of the SCC. Reset
External Status Interrupt command is executed, the external status is stored in a variable tx_stat for future

2-249

1. 82530 Data Sheet, Order #230834-001
2. 82530
SCC
Technical
Manual,
#230925-001

Order

inter

AP-222

APPENDIX A
82530-BAUD RATE GENERATORS
The 82530 has two Baud Rate Generators (BRG) on
chip-one for each channel. They are used to provide
the baud rate or serial clock for receive and transmit
operations. This article describes how the BRG can be
programmed and used.

Step 1: Baud Rate Time Constant (BRTC)
The, BRTC is determined by a simple formula:
BRTC =

The BRG for each channel is totally independent of
each other and have to be programmed separately for
each channel. This article describes how anyone of the
two BRGs can be programmed for operation. To use
the BRG, four steps have to be performed:

Serial Clock Frequency
,

2 X (Baud Rate X Baud Rate Factor)

Example:
For Serial Clock Frequency
Baud Rate

1. Determine the Baud Rate Time Constant (BRTC)
to be programmed into registers WRl2 (LSB) and
WRl3 (MSB).

Baud Rate Factor

2. Program in register, WRII, to specify where the
output of the BRG must go to. .

BRTC

3. Program the clock source to the BRG in register
WRI4.

=

=

4 MHz

= 9600
16

4000000
2 X (9600 X 16)

- 2

, = 13.021 - 2 = 11.021

4. Enable the BRG.

I~I~I~I~I~I~I~I~I

~ I! I,~coo,·=me

II o

0""",
1 TRxC OUT = TRANSMIT
CLOCK
1 0 TRxC OUT
BR GENERATOR OUTPUT
1 1 TRxC OUT = DPLL OUTPUT
TRxC 0/1

..!!.. J!..

TRANSMIT CLOCK

~~

TRANSMIT CLOCK
...!....!.. TRANSMIT CLOCK
...!. ~ TRANSMIT CLOCK

a

RTxC PIN

= TR!,C PIN
= BR GENERATOR OUTPUT
= DPLL OUTPUT

r-!!-r!!.. RECEIVE CLOCK = RTxC PIN
r-!!-r!- RECEIVE CLOCK = TRxC PIN
~r!!c..!..~

RECEIVE CLOCK = BR GEN,ERATOR OUTPUT
RECEIVE CLOCK = DPLL OUTPUT

L -______________

RTxCXTAUNOXTAL
231262-10

Figure 1. Write Register 11

2-250

- 2

inter

Baud
Rate

AP-222

9600
4800
2400
1200
600
300

1
206.333
414.667
831.333
1664.667
3331.333
6664.667

Table 1 BRTC - Baud Rate Time Constant
Baud Rate' Factor
32
16
11.021
4.510
24.042
11.021
50.083
24.042
50.083
102.167
206.333
102.167
414.667
206.333

Since only integers can be written into the registers
WRI2/WR13 this will have to be rounded off to 11
and it will result in an error of:

64
1.255
4.510
11.021
24.042
50.083
102.167

IDd~I~I~I~I~I~IDd

~~

fraction
0.021
- - X 100 = - - X 100 = 0.19%
11.021
BRTC

L

This error indicates that the baud rate signal generated
by the BRG does not provide the exact frequency required by the system. This error is more serious for
smaller baud rate factors. For asynchronous systems,
errors up to 5% are considered acceptable.

0
0
0
0
1
1
1
1

Note that for BRTC = 0, BRG output frequency = 1/4 x
Serial Clock Freq.

Table 1 shows the BRTC for a 4 MHz serial clock with
various baud rates on the Y-axis and baud rate factors
on the X - axis. The constant that is really programmed
into registers WRI2/WR13 is the integer closest to the
BRTC value shown in the table.

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

L

BR GENERATOR ENABLE
BR GENERATOR SOURCE
DTR/REQUEST FUNCTION
AUTO ECHO
LOCAL LOOPBACK

NULL COMMAND
ENTER SEARCH MODE
RESET MISSING CLOCK
DISABLE DPLL
SET SOURCE = BR GENERATOR
SET SOURCE = RTxC
SET FM MODE
SET NRZI MODE

231262-11

Figure 2. Write Register 14

WRl4 / bit DI = 0 --+ Clock comes from pin
RTxC

Step 2: BRG Output

The output of the BRG can be directed to the Receiver,
Transmitter and the TRxC output. This is programmed
by setting bits D6 D5, bits D4 D3, and bits D1 DO in
register WRII to 10. See Figure 1. The output of the
BRG can also be directed to the Digital Phase Locked
Loop (DPLL) for the on-chip decoding of the NRZI
encoded received data signal. This is done by writing
100 into bits D7 D6 D5 of register WRl4 as shown in
Figure 2.

WR14 / bit DI = I --+ Clock comes from System
Clock (PCLK)
On RESET WR14 / bit D1 = O.
It should be noted that for the case of Bit D 1

= 0, the

Step 3: BRG Source Clock

clock comes either from:
a. Clock on pin RTxC - if WR11 / D7 = 0
or b. Crystal on pins RTxC &. SYNC
- ifWR11 / D7 = 1

Register WRl4 is used to select the input clock to the
BRG. See Figure 2.

Step 4: BRG Enable

This is the last step where bit DO of WRl4 is set to start
the BRG. The BRG can also be disabled by resetting
this bit.

2-251

inter

Ap·222

APPENDIX B
MODEM CONTROL PINS ON THE 82530
bits for CD and/or CTS must als~ be set in WR15 for
the interrupt to be enabled.

Introduction
This article describes how the CTS and CD pins on the
82530 behave and how to write software to service
these pins. The article explains when the External
Status Interrupt occurs and how and when to issue the
Reset External/Status Interrupt command to reliably
determine the state of these pins.
Bits D3 and D5 of~ster RRO show the inverted state
of logic levels on CD and CTS pins respectively. It is
important to note that the register RRO does not always
reflect the current state of the CD and CTS pins. Whenever a Reset External/Status Interrupt (RESI) command is issued, the (inverted) states of the CD and the
CTS pins get updated and latched into the RRO register
and the register RRO then reflect the inverted state of
the CD and CTS pins at the time of the write operation
to the chip. On channel or chip reset, the inverted state
of CD and CTS pins get latched into RRO register.
Normally, a transition on any of the pins does not necessarily change the corresponding bit(s) in RRO. In certain situations it does and in some cases it does not. A
sure way of knowing the current state of the pins is to
read the register RRO after a RESI command.
There are two cases:
I. External/Status Interrupt (ESI) enabled:
II. Polling (ESI disabled).
Case I: External Status Interrupt (ESI) Enabled

Whenever ESI is enabled, an interru~n occur whenever there is a transition on CD or CTS pins - the IE

In this case, the first transition on any of these pins will
cause an interrupt to occur and the corresponding bit in
RRO to change (even withoutthe RESI command). A
RESI command resets the interru.E!.!ine and also latches in the current state of both the CD and the CTS pins.
If there was just one transition the RESI does not really
change the contents of RRO.
If there are more' than one transitions, either on the
same pin or one each on both pins or multiple on both
pins, the interrupt would get activated on the first transition and stay active. The bit in RRO corresponding
only to the very first transition is changed. All subsequent transitions have no effect on RRO. The first transition, in effect, freezes all changes in RRO. The first
RESI command, as could be ex~ed, latches the final
(inverted) state of the CD and CTS pins into the RRO
register. Note that all the intermediate transitions on
the pins are lost (because the response to the interrupt
was not fast enough). The interrupt line gets reset for
only a brief moment following the first RESI command. This brief moment is approximately 500 ns for
the 82530. After that the interrupt becomes active
again. A second RESI command is necessary to reset
the interrupt. Two RESI commands resets the interrupt
line independent of the number of transitions occurred.
Whenever operating with ESI enabled, it is recommendable to issue two back-to-back RESI commands
and then read the RRO ~ster to reliably determine
the state of the CD and CTS pins and also to reset the
interrupt line in case mUltiple transitions may have occurred.

SUBSEQUENT
TRANSITIONS

RESET

231262-12

State Diagram

2-252

AP-222

State 2

Case II: Polling RRO for CD and CTS Pins

If RRO is polled for determining the state of the CD
and CTS pins, then the External/Status Interrupt (ESI)
is kept disabled. In this case the bits in RRO may not
change even for the first transition. The best way to
handle this case to always issue a RESI command before reading in the RRO register to determine the state
of CD and CTS pins. Note, however, if two back-toback RESI commands were to be issued every time before reading in the RRO register, the first subsequent
transition will change the corresponding bit in RRO.
The state di~ above illustrates how each transition
on CD and CTS pins affect the 82530 and what effect
the RESI command has.

State 0

Interrupt is active (if enabled). Any further transitions have no effect. A RESI command leads to
state I, temporarily making the interrupt inactive.

CONCLUSIONS
Register RRO does not always reflect the current (inverted) state of the CD and CTS pins. The most reliable
way to determine the state of the pins in interrupt or
polling mode is to issue two back-to-back RESI commands and then read RRO. While polling, the second
RESI is redundant but harmless. When issuing the
back-to-back RESI commands to 82530 note that the
separation between the two write cycles should be at
least 6 CLK + 200 ns; otherwise the second RESI will
be ignored.

It is entered on reset. No ESI due to CTS or CD are

pending in this state. Any transition on CTS or CD
pins lead to the state I accompanied by an immediate change in the RRO register.

State 1
Interrupt is active (if enabled). If a RESI command
is issued, state 0 is reached where interrupt ~ain
inactive. However, a further transition on CTS or
CD pin leads to state 2 without an immediate change
in RRO register.

2-253

AP-222

APPENDIX C
THE 82530 SCC - 80186 'INTERFACE AP BRIEF
INTRODUCTION

INTERFACE OVERVIEW

The object of this document is to give the 82530 system
designer an in-depth worst case design imalysis of the
typical interface to a 80186 based system. This document has been revised to include the new specifications
for the 6 MHz 82530. The new specifications yield better margins and a I wait state interface to the CPU (2
wait states are required for DMA cycles). These new
specifications will appeaI' in the 1987 data sheet and
advanced specification information can be obtained
from your local Intel sales office. The following analysis includes a discussion of how the interface TTL is
utilized to meet the timing requirements of the 80186
and the 82530. In addition, several optional interface
configurations are also considered.

The 82530 - 80186 interface requires the TIL circuitry
illustrated in Figure 1. Using five 14 pin TIL packages,
74LS74, 74AS74, 74AS08, 74AS04, and 74LS32, the
following operational modes are supported:
•
•
•
•
•

Polled
Interrupt in vectored mode
Interrupt in non-vectored mode
Half-duplex DMA on both channels
Full-duplex DMA on channel A

A brief description of the interface functional requirements during the five possible BUS operations follows
below.

DATA (D?-De)

IIZS38
...

DB?
S'i'DI6

T~DA

RXDA

39

.n
12
DB.

iI

.8

rI!li
Il1!7IIRli
T)(DI
RKDI

ftJII!I

1mI9
,IREU

IRES.

2.
27
2.
28

~L

B

•

mI9 2.
IfI'lJIJ
n'D 22
9J" 2.

.

I'!1!7IIRI

2.

G.D

a.

UCC

E.

~EL

= ••
••

I.

'l1I"fQ

•••••

ftlmi
IffimI 12
!VImI I I
1!'f1Ili .7

8S DI6
2 DB ..

••u

E2

H.-1E8

•

HOtES:

ua
IRQ!

PULLED HUH tHROUGH 6K OHM
-

'0?4ASe4

~"L-

______________________

74LS?4

- 74AS88
-

us -

INtB

DRaB

H UI
U2
US
U4

?o4AS14
?o4AS?4

74LS82

~

u.
231262-18
F~gure

1. 82530-80186 Interface

2-254

AP-222

125HS/16
CLKOUT
AD .... '5
DT.I R
ALE

60186

1m
15EFI

PC'S

1m

62580
DATA

===:::::~:::)~

TCLCL

Oll!-00 vtLjp

~

L.
nl'lTjIII, Ul'liiD

I

~C====

I
TCLDX
- - -....."'... ,... :............. ,................... :................................. ,................
..r.:-:-::-=

I

TCL.... V

' .

,

~::::::!:::::::::::::::~r1::::<~L~~:::::::::::::::::::::::::::::::::::r::f:::::::~~~~<::::·

mil?I'~~I~"":!':'~'~
.

"

'

.

231262-19

Figure 2. 80186-82530 Interface Read Cycle
UNITS, 125 HS/16
CLKOUT

: lx . . .,-0'" V?LIb x:::=====:J!Miu!Okm:==!=====:::::)C===
'

====~:
DT/R

80166

"

ALE

WR

iiEH

ADDRESS
62580
DATA

231262-20

Figure 3. 80186-82530 Interface Write Cycle

READ CYCLE: The 80186 read cycle requirements are
met without any additional logic, Figure 2. At least one
wait state is required to meet the 82530 tAD access
time.

is inverted to assure that WR is active low before the D
Flip-Flop is clocked. No wait states are necessary to
meet the 82530's WR cycle requirements, but one is
assumed from the RD cycle.

WRITE CYCLE: The 82530 requires that data must be
valid while the WR pulse is low,~ure 3. A D FlipFlop delays the leading edge of WR until the falling
edge of CLOCKOUT when data is guaranteed valid
and WR is guaranteed active. The CLOCKOUT signal

INTA CYCLE: During an interrupt acknowledge cycle, the 80186 provides two INTA pulses, one per bus
cycle, separated by two idle states. The 82530 expects
only one long INTA ~e with a RD pulse occurring
only after the 82530 lEI/lEO daisy chain settles. As

2-255

AP-222

UNITS:

T,

T,

T....

2T
IJlLE ST.-.TES

125 NSt'12

T1

CLKOUT
AD

80186

0-15

DT/R
INTA
DEN

~!~,~2jr,:.",,·~t~:,=

.. ··T·· .. ········· .. ·········· .. ·······I· .. · .... · .. ·...............................
1 ............. .
·············1 .. ········ ...... ···· .. ···· .... ·····1 .... ·· .. ···· .... ········ .. ·· .. ·· .. ··· .. · .. ·· .... ···········1···· .... ···· .. ·· .. ·

·····1···· .. ···· ........ ·········· .. ·····1 .... ·· .. ·· .... ·········· .. ······ .. ··· .. ····· .... ········ .. ·1···· .... ···· .. ·· .. ·

CLK

"fNTA
82530

RD
VECTOR

...... ·1..

.. ...... I ..
''''1''
--,..--1-1---,1 .................. ··1·· .... ·1·· .. ·· .................................................. ···1 .. · ..~
.... T ....
tIC
I
1
1

i

.::::::::::i::;:r:::::::::::::::::::::>~·~~::::::::::::::::::::::::::::::::t;;~:~~~:·;·:;;~i~~~QiR··· . ~
1

I

I

1
231262-21

Figure 4. 82530-801861NTA Cycle

illustrated in Figure 4, the INTA signal is sampled on
the rising edge of CLK (82530). Two D Flip-Flops and
two TTL gates, U2 and US, are implemented to generate the proper INTA and RD pulses. Also, the INT
signal is passively pulled high, through a I k resistor,
and inverted through U3 to meet the 80186's active
high requirement.
DMA CYCLE: Conveniently, the 80186 DMA cycle
timings are the same as generic read and write operations. Therefore, with two wait states, only two modifications to the DMA request signals are necessary.
First, the RDYREQA signal is inverted through U3
similar to the INT signal, and second the DTR/REQA
signal is conditioned through a D Flip-Flop to prevent
inadvertent back to back DMA cycles. Because the
82530 DTR/REQA signal remains active low for over
five CLK (82530)'s, an additional DMA cycle could
occur. This uncertain condition is corrected when U4
resets the DTR/REQ signal inactive high. Full Duplex
on both DMA channels can easily be supported with
one extra D Flip-Flop and an inverter.
RESET: The 82530 does not have a dedicated RESET
input. Instead, the simultaneous assertion of both RD
and WR causes a hardware reset. This hardware reset
is implemented through U2, U3, and U4.

need not be as extensive as the typical interface used in
this analysis. Two alternative configurations are discussed below.
8288 BUS CONTROLLER: An 80186 based system
implementing an 8288 bus controller will not require
the preconditioning of the WR signal through the D
Flip-Flop U4. When utilizing an 8288, the control signal IOWC does not go active until data is valid, therefore, meeting the timing requirements of the 82530. In
such a configuration, it will be necessary to logically
OR the IOWC with reset to accommodate a hardware
reset operation.
NON·VECTORED INTERRUPTS: If the 82530 is to
be operated in the non-vectored interrupt mode (B step
only), the interface will not require UI or US. Instead,
INTA on the 82530 should be pulled high, and pin 3 of
U2 (RD AND RESET) should be fed directly into the
RD input of the SCC.
Obviously, the amount of required interface logic is application dependent and in many cases can be consider·
ably less than required by the typical configuration,
supporting all modes of SCC operation.

DESIGN ANALYSIS
ALTERNATIVE INTERFACE
CONFIGURATIONS
Due to its wide range of applications, the 82530 interface can have many varying configurations. In most of
these applications the supported modes of operation

This design analysis is for a typical microprocessor system, pictured in Figure 5. The Timing analysis assumes
an 8 MHz 80186 and a 6 MHz 82530 being clocked at
4 MHz. The 4 MHz clock is the 80186 CLKOUT di·
vided by two by a flip-flop (U6). Also, included in the
analysis are bus loading, and TTL·MOS compatibility
considerations.

2·256

inter

AP-222

ADDRESS
LATCH

roo-

MICROPROCESSOR

,..-~

l/L
I'-r

ADDRESS BUS

"ALE

f-f--

r--

'"

~RO~

r--- -

7

7

'"

'"

'7

f-f--

~

~

ROM

RAM

u.,
.........".

I/O

roo-

Vt

'--

I-

DATA BUS

f"f

DATA
TRANSCEIVER

231262-22

Figure 5. Typical Microprocessor System

Bus Loading and Voltage Level
Compatabilities

TIMING ANALYSIS

The data and address lines do not exceed the drive capability of either 80186 or the 82530. There are several
control lines that drive more than one TTL equivalent
input. The drive capability of these lines are detailed
below.
WR: The WR signal drives U3 and U4.
• 101 (2.0 mAl > iii (-0.4 mA + -0.5 mAl
loh (- 400 /LA) > lih (20 /LA + 20 /LA)

PCS5: The PCS5 signal drives U2 and U4.
• 101 (2.0 mAl > iii (-0.5 mA + -0.5 mAl
loh (- 400 /LA) > lih (20 /LA + 20 /LA)

Certain symbolic conventions are adhered to throughout the analysis below and are introduced for clarity.
1. All timing variables with a lower case first letter are
82530 timing requirements or responses (i.e., tRR).
2. All timing variables with Upper case first letters are
80186 timing responses or requirements unless preceded by another device's alpha-numeric code (i.e.,
Tclcl or '373 Tpd).
3. In the write cycle analysis, the timing variable,
TpdWR186-WR530 represents the propagation delay between the leading or trailing edge of the WR
signalleav~he 80186 and the WR edge arrival at
the 82530 WR input.

Read Cycle

\

INTA: The INTA signal drives 2(Ul) and U5.
• 101 (2.0 mAl > Iii (-0.4 mA + -0.8 mA + -0.4 mAl
loh (- 400 /LA) > lih (20 /LA + 40 /LA + 20 /LA)

All the 82530 I/O pins are TTL voltage level compatible.

1. tAR: Address valid to RD active set up time for the
82530. Since the propagation delay is the worst case
path in the assumed typical system, the margin is calculated only for a propagation delay constrained and not
an ALE limited path. The spec value is 0 ns minimum.
• 1 Tclcl - Tclav(max) - '245Tpd(max)
2(U2) Tpd(min) - tAR (min)

+

Tclrl(min)

+

= 125 - 55 - 20.8 + 10 + 2(2) - 0 = 63.2 ns margin
2-257

AP~222

• 3 Tclcl + 1(Tclclwait state) - Tclav(max) - '373
Tpd(max) - '245 Tpd - Tdvcl(min) - tAD

2. tRA: Address to RD inactive hold time. The ALE
delay is the worst case path and the 82530 requires 0 ns
minimum.

= 375
margin

• 1 Tclcl - Tclrh (max) + Tchlh(min) + '373 LE
Tpd(min) - 2(U2) Tpd(max)
= 55 - 55

+5 +8

+ 125 - 55 - 20.8 -14.2 - 20 -3::!5 = 65 ns

Write Cycle

- 2(5.5) = 2 ns margin

3. tCLR: CS active low to RD active low set up time.
The 82530 spec value is 0 ns minimum.

1. tAW: Address required valid to WR active low set
up time. The 82530 spec is 0 ns minimum.

• 1 Tclcl - Tclcsv(max) - Tclrl(min) - U2
skew(RD - CS) + U2 Tpd(min) .

•

= 125 - 66 - 10 - 1 + 2 = 50 ns margin

= 125 - 55 - 5 - 20.8
= 170.6 ns margin

4. tRCS: RD inactive to CS inactive hold time. The
82530 spec calls for 0 ns minimum.

• Tclch(min) - Tcvclx(max) + Tchlh(min) + '373 LE
Tpd(min) - TpdWR186=WR530(HIGH) [U2 Tpd(max) +
U3 Tpd(max) + U4 Tpd(max))

= 35 - 1 - 5.5 = 28.5 ns margin
5. tCHR: CS inactive to RD active set up time. The
82530 requires 5 ns minimum.

= 55 - 55
margin

• 1 Tclcl + 1 Tchcl - Tchcsx(max) + Tclrl(min) - U2
skew (RD - CS) + U2 Tpd(min) - tCHR

Trlrh(min)

= (250-50)

+

+ 5 + 8 - [5.5 + 3 + 7.11 = -2.6 ns

3. tCLW: Chip select active lo~ to WR active low hold
time. The 82530 spec is 0 ns.

+ 55 - 35 - 10 - 1 + 2 - 5 = 131 ns margin

1 Tclcl - Tclcsv(max) + Tcvctv(min) - U2 Tpd(max)
+ TpdWR186=WR530(LOW) [Tclcl - Tcvctv(min) + U3
Tpd(min) + U4 Tpd(min))
.
•

6. tRR: RD pulse active low time. One 80186 wait state
is included to meet the 150 ns minimum timing requirements of the 82530.
•

+ [125 - 5 + 1 + 4.41 - 0

2. tWA: WR inactive to address invalid hold time. The
82530 spec is 0 ns.

• . Tcscsx(min) - U2 skew(RD - CS) - U2 Tpd(max)

= 125

Tclcl - Tclav(max) - Tcvctv(min) - '373 Tpd(max)
[Tclcl - Tcvctv(min) +
tAW

+ TpdWR186 - WR530(LOW)
U3 Tpd(min) + U4 Tpd(min)) -

= 125 - 66 + 5 - 5.5
183.9 ns margin

1(Tclclwait state) - 2(U2 skew) - tRR

+ 1(125) - 2(1) - 150 = 173 ns margin

+ [125 - 5 + 1 + 4.41 =

4. tWCS: WR invalid to Chip S~lect invalid hold time.
82530 spec is 0 ns.
'

7. tRDV: RD active low to data valid maximum delay
for 80186 read data set up time (Tdvcl = 20 ns). The
margin is calculated on the Propagation delay pllth
(worst cas~).
• 2 Tclcl + 1(Tclclwait state) - Tclrl(max) - Tdvcl(min)
- '245 Tpd(max) - 82530 tRDV(max) - 2(U2) Tpd(max)

• Tcxcsx(min) - U2 Tpd(max) TpdWR186=WR530(HIGH) [U2 Tpd(max)
Tpd(max) + U4 Tpd(max)]
= 35

+ U3

+ 1.5 - [5.5 + 3 + 7.11 = 20.9 ns margin

5. tCHW: Chip Select inactive high to WR active low
set up time. The 82530 spec is 5 ns.

= 2(125) + 1(125) - 70 - 20 - 14.2 - 105 - 2(5.5)
= 154 ns margin
8. tDF: RD inactive to data output float delay. The
margin is cai<,:ulated to DEN active low of next cycle.

• 1 Tclcl + Tchcl(min) + Tcvctv(min) - Tchcsx(max) --:
U2 Tpd(max) + TpdWR186=WR5~0(LOW) [Tclcl Tcvctv(min) + U3 Tpd(min) + U4 Tpd(min)1 - tCHW

• 2 Tclcl + Tclch(min) - Tclrh(max)
2(U2) Tpd(max) - 82530 tDF(max)

= 125 + 55 + 5 - 35 - 5.5
5 = 264 ns margin

+

Tchctv(min) -

= 250 + 55 -55 + 10 - 11 - 70 = 179 ns margin
9. tAD: Address required valid to read data valid maximum delay. The 82530 spec value is :h5 ns maximum.

+ [125 -5 + 1 + 4.41 .

6. tWW: WR active low pulse. 82530 requires a minimum of 60 ns from the falling to 'the rising edge of WR.
This includes one wait state.

2-258

intJ

AP-222

* Twlwh [2Tclcl - 40] +·1 (Tclclwait state) - TpdWRI
186-WR530(lOW) [Tclcl - Tcvctv(min) + U3 Tpd(max)
+ U4 Tpd(max)] + TpdWR/186=WR/530(HIGH) [U2
Tpd(min) U3 Tpd(min) + U4 Tpd(min)] - tWW

should never exist. 82530 drivers should insure that at
least one CPU cycle separates INTA and WR or RD
cycles.

= 210 + 1(125) - [125 - 5 + 4.5 + 9.2] - [1.5 + 1
+ 3.2] - 60 = 135.6 ns margin

4. tWI: WR inactive high to INTA active low minimum hold time. The spec is 0 ns and the margin assumes CLK coincident with INTA.

7. tDW: Data valid to WR active low setup time. The
82530 spec requires 0 ns.
* Tcvctv(min) - Tcldv(max) - '245 Tpd(max) +
TpdWR186-WR530(lOW) [Tcici - Tcvctv(min) + U3
Tpd(min) + U4 Tpd(min)]

* Tclcl - Tcvctx(max) - TpdWR1B6 - WR530(HIGH)
[U3 Tpd(max) + U4 Tpd(max)] + Tcvctv(min) + Ul
Tpd(min)

= 125 - 55 - [5.5 + 3 + 7.1] + 5 + 10 = 69.4 ns
margin

= 5 - 44 - 14.2 + 125 - 5 + 1.0 + 4.4 = 72.2 ns
margin
8. tWD: Data valid to WR inactive high hold time. The
82530 requires a hold time of 0 ns.

5. tIR: INTA inactive high to RD active low minimum
setup time. This spec pertains only to 82530 RD cycles
and has a value of 55 ns. The margin is calculated in
the same manner as tIW.

* Tclch - skew {Tcvclx(max) + Tcvctx(min)l + '245
OE Tpd(min) - TpdWR186-WR530(HIGH) [U2 Tpd(max)
+ U3 Tpd(max) + U4 Tpd(max)]

6. tRI: RD inactive high to INTA active low minimum
hold time. The spec is 0 ns and the margin assumes
CLK coincident with INTA.

= 55 - 5 + 11.25 - [5.5 + 3.0 + 7.1] = -50.6 ns
margin

* Tclcl - Tclrh(max) - 2 U2 Tpd(max) + Tcvctv(min)
+ Ul Tpd(min)
= 125 - 55 - 2(5.5) + 5 + 10 = 74 ns margin

INTACycle:
1. tIC: This 82530 spec implies that the INTA signal is
latched internally on the rising edge of CLK (82530).
Therefore the maximum delay between the 80186 asserting INTA active low or inactive high and the 82530
internally recognizing the new state of INTA is the
propagation delay through UI plus the 82530 CLK period.
.

* Ul Tpd(max) + 82530 ClK period
=45+250=295ns
2. tCI: rising edge of CLK to INT A hold time. This
spec requires that the state of INTA remains constant
for 100 ns after the rising edge of CLK. If this spec is
violated any change in the state of INTA may not be
internally latched in the 82530. tCI becomes critical at
the end of an INTA cycle when INTA goes inactive.
When calculating margins with tCI, an extra 82530
CLK period must be added to the INTA inactive delay.
3. tIW: INTA inactive high to WR active low minimum setup time. The spec pertains only to 82530 WR
cycle and has a value of 55 ns. The margin is calculated
assuming an 82530 WR cycle occurs immediately after
an INTA cycle. Since the CPU cycles following an
82530 INTAcycle are devoted to locating and executing the proper interrupt service routine, this condition

7. inD: INTA active low to RD active low minimum
setup time. This parameter is system dependent. For
any SCC in the daisy chain, tlID must be greater than
the sum of tCEQ for the highest priority device in the
daisy chain, tEl for this particular SCC, and tEIBO for
each device separating them in' the daisy chain. The
typical system with only 1 SCC requires tIID to be
greater than tCEQ. Since tEl occurs coincidently with
tCEQ and it is smaller it can be neglected. Additionally, tEIEO does not have any relevance to a system with
only one SCC. Therefore tIID > tCEQ = 250 ns.
• 4 Tclcl + 2 Tidle states - Tcvctv(max) - tiC [Ul
Tpd(max) + 82530 ClK period] + Tcvctv(min) + U5
Tpd(min) + U2 Tpd(min) - tliD
= 500 + 250 - 70 - [45 + 250]
= 148 ns margin

+5

+ 6 + 2 - 250

8. tIDY: RD active low to interrupt vector valid delay.
The 80186 expects the interrupt vector to be valid on
the data bus a minimum of 20 ns before T4 of the second acknowledge cycle (Tdvcl). tIDY spec is 100 ns
maximum.
• 3 Tclcl - Tcvctv(max) - U5 Tpd(max) - U2
Tpd(max) - tIDV(max) - '245 Tpd(max) - Tdvcl(min)
= 375 - 70 - 25 - 5.5 - 100 - 14.2 - 20 = 140.3
ns margin

2-259

AP-222

9. tIl: RD pulse low time. The 82530 requires a minimum of 125 ns.

• Tcicl + 2(Tclclwait state) - Tcvctv(min) TpdWR186-WR530(LOW) [Tclcl - Tcvctv(min) + U3
Tpd(max) + U4 Tpd(max)] - Tdrqcl - tWRI

• 3 Tclcl - Tcvctv(max) - U5 Tpd(max) - U2
Tpd(max) + Tcvctx(min) + U5 Tpd(min) + U2 Tpd(min)
- til (min)

=375 - 5 - [125 - 5 + 4.5 + 9.21 - 25 - 200 =
11.3 ns margin
NOTE:
If one wait state DMA interface is required, external
logic, like that used on the DTRREQ signal, can be
used to force the 82530 REQ signal inactive.

= 375 - 70 - 25 - 5.5 + 5 + 6 + 1.5 - 125 =
162 ns margin

DMACycle
Fortunately, the 80186 DMA controller emulates CPU
read and write ~ycle operation during DMA transfers.
The DMA transfer timings are satisfied using the above
analysis. Because of the 80186 DMA request input requirements, two wait ,states are necessary to prevent
inadvertent DMA cycles. There are also CPUDMA intracycle timing considerations that need to be addressed.
1. tDRD: RD inactive high to DTRREQ (REQUEST)
inactive high delay. Unlike the READYREQ signal,
DTRREQ does not immediately go inactive after the
requested DMA transfer begins. Instead,. the DTRREQ
remains active for a maximum of 5 tCY + 300 ns. This
delayed request pulse could trigger a second DMA
transfer. To avoid this undesirable condition, a D Flip
Flop is implemented to reset the DTRREQ signal inactive low following the initiation of the requested DMA
transfer. To determine if back to back DMA transfers
are required in a source synchronized configuration,
the 80186 DMA controller samples the service request
line 25 ns before T1 of the deposit cycle, the second
cycle of the transfer.

4. tREC: CLK recovery time. Due to the internal data
path, a recovery period is required between SCC blls
transactions to resolve metastable conditions internal to
the SCC. The DMA request lines are,masked from req1,lesting service until after the tREC has elapsed. In
addition, the CPU should not be allowed to violate this
recovery period when interleaving DMA transfers and
CPU bus cycles. Software drivers or external logic
should orchestrate the CPU and DMA controller operation to prevent tREC violation. In this example circuit, tREC could be improved by clocking the '530 with
a 6 MHz clock.

Reset Operation
During hardware reset, the system RESET signal is asserted high for a minimum of four 80186 clock cycles
(1000 ns). The 82530 requires WR and RD to be simul- '
taneously asserted low for a minimum of 250 ns.
• 4 Tclcl - U3 Tpd(max) - 2(U2) Tpd(max) + U4
Tpd(min) - tREC
= 1000 - 17.5 - 2(5.5) + 3.5 - 25Q ns = 725 ns
margin

• 4 Tclcl - Tclcsv(max) - U4Tpd(max) - Tdrqcl(min)
= 500 - 66 - 10.5 - 25 = 398.5 ns margin

82530 VALID ACCESS LOGIC

2. tRRI: 82530 RD active low to REQ inactive high
delay. Assuming source synchronized DMA transfer,
the 80186 requires only one wait state to meet the tRRI
spec of 200 ns. Two are included for consistency with
tWRI.

Due to the unique internal data path of the 82530, an
intra-access recovery time must be provided to settle
any internal metastable conditions. This internal metastble condition gives rise to the Clock Recovery
(tREC) specification required by the 82530. This tREC
is measured from the risi~dge of a RD or WR to the
falling edge of the next RD or WR intended for the
82530, and equates to 6 CLK's + 130 ns. Effectively,
this specification implies that the system must provide
1130 ns (6 MHz 82530) between every CPU or other
DMA access to the 82530. (Figure 1.)

• 2 Tclcl + 2(Tclclwait state) - Tclrl(max) - 2(U2)
Tpd(max) - Tdrqcl - tRRI
=2(125) + 2(125) - 70 - 2(5.5) - 200 = 219 ns
margin
3. tWRI: 82530 WR active low to REQ inactive high
delay. Assuming destination synchronized DMA transfers, the 80186 needs two wait states to meet the tWRI
spec. This is because the 80186 DMA controller samples requests two clocks before the end of the deposit
cycle. This leaves only 1 Tclcl + n(wait states) minus
WR active delay for the 82530 to inactivate its REQ
signal.

Systems that only allow CPU access to the 82530 are
not significantly impacted by this clock recovery time.
In CPU access only designs, the software designer ·can
insert NOP's to guarantee the tREC idle time in between successive CPU RD or WR cycles to the 82530.
Unfortunately, systems that contain more than one direct memory access device, interfacing with the 82530,
will require external hardware to arbitrate 82530 accesses and thereby guaranteeing the tREC restriction.

2-260

intJ

AP-222

82530

CS

!I

--.-I

{ " Non 82530 Sus Cyclo

Rii
WR

\

or--oJ

'-~

82530 Clock Recovery Time

231262-23

Figure 1

EXTERNAL VALID ACCESS
HARDWARE
To accommodate this clock recovery specification, external hardware has been designed for the 82530 systems containing several DMA devices accessing, the
82530 (ie., a CPU and a DMA controller). This logic
has been tailored for an 80186 environment but can
easily be modified to fit 8086 or 80286 systems.

LOGIC STATE MACHINE

The TTL logic pictured in Figure 2 implements the
state machine with some assorted gates, a flip-flop, and
a shift register. PCS from the 80186 should be qualified
with RD + WR to eliminate switching glitches during
Tl. The 'J..S74 and 'L~OO perform rising edge detection
to reset the shift register. The shift register clocks out
the tREC period to enable CS and the additional 2
CLK's (82530 I to satisfy the 82530 3 wait state requirement. The 80186 should be programmed to use
the internal wait state generator (3 wait states for the
82530 and an 8 MHz 801861 and the external READY
signal.

There are two basic functions that need to be performed by the external logic. The first is to mask the CS
signal from reaching the 82530 until the tREC intra-access idle time has elapsed. The second task is to generate a not ready condition to the CPU or DMA device
until the tREC period has expired and the minimum
wait state requirement for the particular access has
been satisfied. The simple state machine, Figure 2, illustrates the required operation.

Note of caution: This hardware logic has not been verified on a bread board in an actual system. The hardware designer should verify that this logic fulfills his
particular system timing requirements. '

+5V

7404

PC5530

UCS

cs
>=_______-=

1 74AS32

"""tr.;..;..;;.;.......~

U6

U3
74AS02

ARDY

231262-24

Figure 2

2-261

Other Components

3

APPLICATION
NOTE

AP-166

April 1989

Using the 8291A GPIB
Talker /Listener

Order Number: 230832-001
3-1

inter

AP-166

INTRODUCTION
This application note explains the Intel 8291A GPIB
(General Purpose Interface Bus) Talker/Listener as a
component, and shows its use in GPIB interface design
tasks.

DEVICE A
ABLE TO
TALK. LISTEN.
AND
CONTROL

1111'1

The first section of this note presents an overview of
IEEE 488 (GPIB). The second section introduces the
Intel GPIB component family. A detailed explanation
of the 8291A follows. Finally, some application examples using the component family are presented.

111

-'--

r
DATA BUS

(f-

(e.g. calculalor)

DEVICEB
ABLE TO
TALK AND
LISTEN

i-'-----'

(e.g. digital
muilimeler)

(-DEVICEC
ONLY ABLE
. TO LISTEN

r-

DATA BYTE
TRANSFER
CONTROL

i-'-----'

(e.g. signal
generalor)

(
DEVICE D
ONLY ABLE
TO TALK

GENERAL
INTERFACE
MANAGEMENT

'1/

-

(e.g. counler)

}DI01 ... 8

Data InpuVOulpul

DAV

Dala Available

NRFD
NDAC

Nol Ready for Data
Nol Data Accepled

IFC
ATN
SRO

Inler!ace Clear
Allenlion
Servlce Requesl

REN

Remole Enable
End or Idenllfy

EOI

230832-1

Figure 1. Interface Capabilities and Bus Structure
3-2

inter

AP-166

OVERVIEW OF IEEE 488/GPIB

Electrical Signal Lines

The GPIB is a parallel interface bus with an asynchronous interlocking data exchange handshake mechanism. It is designed to provide a common communication interface among devices over a maximum distance
of 20 meters at a maximum speed of 1 Mbps. Up to 15
devices may be connected together. The asynchronous
interlocking handshake dispenses with a common synchronization clock, and allows intercommunication
among devices capable of running at different speeds.
During any transaction, the data transfer occurs at the
speed of the slowest device involved.

As shown in Figure 1, the GPIB is composed of eight
data lines (008-001), five interface management lines
(IFC, ATN, SRQ, REN, EOI), and three transfer controllines (DAV, NRFD, NDAC).
The eight data lines are used to transfer data and commands from one device to another with the help of the
management and control lines. Each of the five interface management lines has a specific function.
ATN (attention) is used by the Controller to indicate
that it (the controller) has access to the GPIB and that
its output on the data lines is to be interpreted as a
command. ATN is also used by the controller along
with EOI to indicate a parallel poll.

The GPIB finds use in a diversity of applications requiring communication among digital devices over
short distances. Common examples are: programmable
instrumentation systems, computer to peripherals, etc.

SRQ (service request) is used by a device to request
service from the controller.

The interface is completely defined in the IEEE
STD.-488-1978.

REN (remote enable) is used by the controller to specify the command source of a device. A device can be
issued commands either locally through its front panel
or by the controller.

A typical implementation consists of logical devices
which talk (talker), listen (listeners), and control GPIB
activity (controllers).

EOI (end or identify) may be used by the controller as
well as talker. A controller uses EOI along with ATN
to demand a parallel poll. Used by a talker, EOI indicates the last byte of a data block.

Interface Functions
The interface between any device and the bus may have
a combination of several different capabilities (called
·functions'). Among a total of ten functions defined, the
Talker, Listener, Source Handshake, Acceptor Handshake and Controller are the more common examples.
The Talker function allows a device to transmit data.
The Listener function allows reception. The Source and
Acceptor Handshakes, synchronized with the Talker
and Listener functions respectively, exchange the handshake signals that coordinate data transfer. The Controller function allows a device to activate the interface
functions of the various devices through commands.
Other interface functions are: Service request, Remote
local, Parallel poll, Device clear and Device trigger.
Each interface may not contain all these functions. Further, most of these functions may be implemented to
various levels (called 'subsets') of capability. Thus, the
overall capability of an interface may be tailored to the
needs of the communicating device.

IFC (interface clear) forces a complete GPIB interface
to the idle state. This could be considered the GPIB's
"interface reset." GPIB architecture allows for more
than one controller to be connected to the bus simultaneously. Only one of these controllers may be in command at any given time. This device is known as the
controller-in-charge. Control can be passed from one
controller to another. Only one among all the controllers present on a bus can be the system controller. The
system controller is the only device allowed to drive
IFC.

3-3

inter

AP-166

SOURCE

NRFD SIGNAL LINES GOES HIGH

YES

r-_ _......_ _.,ONLY WHEN ALL ACCEPTORS ARE READY
DATA IS VALID AND MAY
NOW BE ACCEPTED

DATA IS NOT TO BE CONSIDERED
VALID AFTER THIS TIME

NO

230832-2
NOTE:
Flow diagram outlines sequence of events during transfer of data byte. More than one listener at a time can accept data
because of logical connection of NRFD and NDAC lines.

Figure 2. Handshake Flowchart

3·4

intJ

AP-166

Ton/Ion is a method where the ability of the GPIB
interface to talk or listen is determined by the device
and not by the GPIB controller. With this method,
fixed poles can be easily designated in simple systems
where reassignment is not necessary. This is appropriate and convenient for certain applications. For example, a logic analyzer might by interfaced via the GPIB
to a line printer in order to document some type of
failure. In this case, the line printer simply listens to the
logic analyzer, which is a talker.

Transfer Control Lines
The transfer control lines conduct the asynchronous interlocking three-wire handshake.
DAV (data valid) is driven by a talker and indicates
that valid data is on the bus.
NRFD (note ready for data) is driven by the listeners
and indicates that not all listeners are ready for more
data.

The controller addresses devices through three commands, MTA (my talk address), MLA (my listen address), and MSA (my secondary address). The device
address is imbedded in the command bit pattern. The
device whose address matches the imbedded pattern is
enabled. Some devices may have the same logical talk
and listen addresses. This is allowable since the talker
and listener are separate functions. However, two of the
same functions cannot have the same address.

NDAC (not data accepted) is used by the listeners to
indicate that not all listeners have read the GPIB data
lines yet.
The asynchronous 3-wire handshake flowchart is
shown in Figure 2. This is a concept fundamental to the
asynchronous nature of the GPIB and is reviewed in
the following paragraphs.

In primary addressing, a device is enabled to talk (listen) by receiving the MTA (MLA) message.

Assume that a talker is ready to start a data transfer.
At the beginning of the handshake, NRFD is false indicating that the listener(s) is ready for data. NDAC is
true indicating that the listener(s) has not accepted the
data, since no data has been sent yet. The talker places
data on the data lines, waits for the required settling
time, and then indicates valid data by driving DAV
true. All active listeners drive. NRFD true indicating
that they are not ready for more data. They then read
the data and drive NDAC false to indicate acceptance.
The talker responds by deasserting DAV and readies
itself to transfer the next byte. The listeners respond to
DAV false by driving NDAC true. The talker can now
drive the data lines with a new data byte and wait for
NRFD to be false to start the next handshake cycle.

Secondary addressing extends the address field from 5
to 10 bits by allowing an additional byte. This additional byte is passed via the MSA message. Secondary addressing can also be used to logically divide devices into
various subgroups. The MSA message applies only to
the device(s) whose primary address immediately precede it.

INTEL'S® GPIB COMPONENTS
The logic designer implementing a GPIB interface has,
in the past, been faced with a difficult and complex
discrete logic design. Advances in LSI technology have
produced sophisticated microprocessor and peripheral
devices which combine to reduce this once complex interface task to a system consisting of a small set of
integrated circuits and some software drivers. A microprocessor hardware/software solution and a high-level
language source code provide an additional benefit in
end-product maintenance. Product changes are a simple matter of revising the product software. Field
changes are as easy as exchanging EPROMS.

Bus Commands
When ATN and DAV are true data patterns which
have been placed by the controller on the GPIB, they
are interpreted as commands by the other devices on
the interface. The GPIB standard contains a repertory
of commands such as MTA (My Talk Address), MSA
(My Secondary Address), SPE (Serial Poll Enable), etc.
All other patterns in conjunction with ATN and DAV
are classified as undefined commands and their meaning is user-dependent.

Intel has provided an LSI solution to GPIB interfacing
with a talker/listener device (829IA), a controller device (8292), and a transceiver (8293). An interface with
all capabilities except for the controller function can be
built with an 8291A and a pair of 8293's. The addition
of the 8292 produces a complex interface. Since most
devices in a GPIB system will not have the controller
function capability, this modular approach provides the
least cost to the majority of interface designs.

Addressing Techniques
To allow the controller to issue commands selectively
to specific devices, three types of addressing exist on the
GPIB: talk only/listen only (ton/Ion), primary, and
secondary.

3-5

AP-166

Current states of the 8291A can be determined by examining the device's status read registers. In addition,
the 8291A contains 8 write registers. These registers are
shown in Figure 3. The three register select pins RS3RSO are used to select the desired register.

Overview of the 8291 A
GPIB Talker/Listener
The Intel 8291A GPIB Talker/Listener operates over a
clock range of 1 to 8 MHz and is compatible with the
MCS-85, iAPX-86, and 8051 families of microprocessors.

The data-in register moves data from the GPIB to the
microprocessor or to memory when the 8291A is addressed to listen. When the 8291A is addressed to talk,
it uses the data-out register to move data onto the
GPIB. The serial poll mode and status registers are
used to request service and program the serial poll
status byte.

A detailed description of the 8291A is given in the data
sheet.
The 8291A implements the following functions: Source
Handshake (SH), Acceptor Handshake (AH), Talker
Extended (TE), Service Request (SRQ), Listener Extended (LE), Remote/Local (RL), Parallel Poll (PP2),
Device Clear (DC), and Device Trigger (DT).

Read Registers

A detailed description of each of the registers, along
with state diagrams can be found in the 8291A data
sheet.

Register Select
Code

r--.__- .__- .__- r__- r__~__~__-,RS2
I DI7 I DI6 I DIS I DI4 I DI3 I DI2 I Dll

DIO I 0

Write Registers

RSI RS0r-~__- .__~__~~~~__r -_ _~~
0

0 I D07 I D06 I DOS I D04 I D03 I D02 I DOl I 000 I

DATA IN

ICPT I APT I GET I END I DEC I ERR I

DATA OUT
BO

BI

I 0

I CPT I APT I GET I EN~ I DEC I ERR I

0

INTERRUPT STATUS 1
liNT I SPAS I LLO I REM I SPC I LLOC I REMC I ADSC I 0

o I

0

I

0

INTERRUPT ENABLE 2
S2

SI

1 I S8 I RSV I S6 I SS I S4 I S3

I 0

SERIAL POLL STATUS 2

I ton I Lon

BI

I DMAO I DMAd SPC I LLOC I REMC I ADSC I

INTERRUPT STATUS 2
S8 I SROS I S6 I S5 I S4 I S3

BO

INTERRUPT ENABLE 1

S2

SI

SERIAL POLL MODE

I EOI I LPAS I TPAS I LA I TA I MJMNI

o

0

I TO

I LO I

ADDRESS STATUS

0

I

0

I

0

I

0

I ADMI I ADMO I

ADDRESS MODE

ICPT71 CPT61cPTSI CPT41 CPT31 CPT21 CPTI I CPTO I 1

0

1 I CNT21CNTII CNIO ICOM41cOM31cOM21cOMlicOMOI

COMMAND PASS THROUGH

AUXMODE

liNT I DTO I DLO IADS-0IAD4-0IAD3-0IAD2-OIAD1-01 1

OIARSIDTI

ADDRESS 0

DL IADSIAD41AD31AD21ADli
ADDRESS 011

I X I DTI I DLI IADS-lIAD4-1IAD3-1IAD2-1IAD1-11

1 I EC7 I Ecsl ECS I EC4 I EC3 I EC2 I ECI I ECO I

ADDRESS 1

EOS

Figure 3. 8291A Registers

3-6

AP-166

address I registers allow reading of these programmed
addresses plus trading of the interrupt bit. The EOS
register is used to program the end of sequence character.

Address Mode.
The address mode and status registers are used to program the addressing modes and track addressing states.
The auxiliary mode register is used to select a variety of
functions. The command pass through register is used
for undefined commands and extended addresses. The
address 0/1 register is used to program the addresses to
.which the 8291A will respond. The address 0 and

Detailed descriptions of the addressing modes available
with the 8291A are described in the 8291A data sheet.
Examples of how to program these modes are shown
below.

1. MODE: Talker has single address of 01 H
Listener has single address of 02H
CPU Writes to:

Pattern

Comment

Address Mode Register
Address 0/1 Register
Address 0/1 Register

0000 0001
0010 0001
11000010

Select Mode 1 Addressing
Major is Talking. Address = 01 H
Minor is Listener. Address = 02H

2. MODE: Talker has single address of 01 H
Listener has single address of 02H

CPU Writes to:

Pattern

Comment

Address Mode Register
Address 0/1 Register
Address 011 Register

0000 0001
0100 0010
1010 0001

Select Mode 1 Addressing
Major is Listener. Address = 02H
Minor is Talking. Address = 01 H

Note that in both of the above examples, the listener will respond to a MLA message with five least significant bits
equal to 02H and the talker to a OIH.
3. MODE: Talker and listener both share a Single address of 03H
CPU Writes to:

Pattern

Address Mode Register
Address 0/1 Register
Address 0/1 Register

0000 00Q1
0000 0011
11100000

Comment
Select Mode 1 Addressing
Talker and Listener Address
Minor Address is disabled

= 03

4. MODE: Talker and listener have a primary address of 04H and a secondary address of 05H
CPU Writes to:

Pattern

Comment

Address Mode Register
Address 0/1 Register
Address 0/1 Register

0000 0010
0000 0100
1000 0101

Select Mode 2 Addressing
Primary Address = 04H
Minor Address is disabled

5. MODE: Talker has a primary address of 06H. Listener has a primary address of 07H
CPU Writes to:

Pattern

Comment

Address Mode Register
Address 0/1 Register
Address 0/1 Register

0000 0011
0010 0110
1100 0111

Select Mode 3
Talker Address = 06
Listener Primary = 07

The CPU will verify the secondary addresses which could be the same or different.

3-7

intJ

AP-166

APPLICATION OF THE 8291A

LISTENER FUNCTIONS

This phase of the application note will examine programming of the 8291A, corresponding bus commands
and responses, CPU interruption, etc. for a variety of
GPIB activities. This should provide the reader with a
clear understanding of the role of the 8291A performs
in a GPIB system. The talker function, listener function, remote message handling, and remote/local operations including local lockout, are discussed.

LISTEN-ONLY (Ion). In listen-only mode the 8291
will not respond to the My Listen Apdress (MLA) message from the controller. The sequence of events is as
follows:
I) The Interrupt Enable registers are programmed.
2) Lon is selected.
3) EOS character is programmed.
4) "Pon" local message is sent.
5) CPU waits for BI and reads the byte from the datain register.
.

Talker Functions

Note that enabling both ton and Ion can create an internal loopback as long as another listener exists.

TALK-ONLY (ton). In talk only mode the 8291A will
not respond to the MTA message from a controller.
Generally, ton is used in an environment which does
not have a controller. Ton is also employed in an interface that includes the controller function.

Addressed Listening
(via the MLA Message)

When the 8291A is used with the 8292, the sequence of
events for initialization are as follows:
I) The Interrupt/Enable registers are programmed.
2) Ton is selected.
3) Settling time is selected.
4) EOS character is loaded.
5) "Pon" local message is sent.
6) CPU waits for Byte Out (BO) and sends a byte to
the data out register.

The GPIB controller will direct the 8291A to listen by
sending a MLA message containing the 8291A's listen
address. The sequence of events is as follows:
I) The Interrupt Enable registers are programmed.
2) The serial poll mode register is loaded as desired.
3) Talker and listener addresses are loaded.
4) "Pon" local message is sent.
5) The CPU waits for an interrupt. When the controller has sent the MLA message for the 8291A, the
ADSC bit will be set.
6) The CPU reads the Address Status Register to determine if the 8291A has been addressed to listen
(LA = I).
7) CPU waits for an interrupt for BI or ADSC.
8) When BI is set, the CPU reads the data byte from
the data-in register.
9) The CPU continues to poll the status registers.
10) When unaddressed, ADSC will be set and LA reset.

Addressed Talker (via MTA Message)
The GPIB controller will direct the 8291A to talk by
sending a My Talk Address (MTA) message containing
the· 8291A's talk address. The sequence of events is as
follows:
I) The interrupt enable and serial poll mode registers
are programmed.
.
2) Mode 1 is selected.
3) Settling time is selected.
'4) Talker and listener addresses are programmed.
5) Power on (pon) local message is sent.
6) CPU waits for an interrupt. When the controller
has sent the MTA message for the 8291A an interrupt will be generated if enabled and the ADSC bit
will be set.
7) CPU reads the Address Status register to determine
if the 8291A has been addressed to talk (TA = I).
8) CPU waits for an interrupt from either BO or
ADSC
9) When BO is set, the CPU writes the data byte to
the data out register..
10) CPU continues to poll the status registers.
11) When unaddressed ADSC, will be set and T A reset.

Remote/Local and Lockout
Remote and local refer to the source of control of a
device connected to the GPIB. Remote refers to control
from the GPIB controller-in-charge. Local refers to
control from the device's own system. Reference should
be made to the RL state diagram in the 2891A data
sheet.
Upon "pon" the 8291A is in the local state. In this state
the REM bit in Interrupt Status 1 Register is reset.
When the GPIB controller takes control of the bus it
will drive the REN (remote enable) line true. This will
cause the REM bit and REMC (remote/local change)
bit to be set. The distinction between remote and local
modes is necessary in that some types of devices will
have local controls which have functions which are also
controlled by remote messages.

3-8

inter

Ap·166

These two methods are called Serial and Parallel Poll.
The controller performs one of these two polling methods after a slave device requests service. As implied in
the name, a Serial Poll is when the controller sequentially asks each device if it requested service. In a Parallel Poll the controller asks all of the devices on the
GPIB, if they requested service, and they reply in parallel.

In the local state the device is allowed to store, but not
respond to, remote messages which control functions
which are also controlled by local messages. A device
which has been addressed to listen will exit the local
state and go to the remote state if the REN message is
true and the local rtl (return to local) message is false.
The state of the "rtl" local message is ignored and the
device is "locked" into the local state if the LLO remote message is true. In the Remote state the device is
nQt allowed to respond to local messages which control
function that are also controlled by remote messages. A
device will exit the remote state and enter the local
state when REN goes false. It will also enter the local
state if the GTL (go to local) remote message is true
and the device has been addressed to listen. It will also
enter the local state if the rtl message is true and the
LLO message is false or ACDS is inactive.

Serial Poll
When the controller performs a Serial Poll, each slave
device sends back to the controller a Serial Poll Status
Byte. One of the bits in the Serial Poll Status Byte indicates whether this device requested service or not. The
remaining 7 bits are used defined, and they are used to
indicate what type of service is required. The IEEE-488
spec only defines the service request bit, however HP
has defined a few more bits in the Serial Poll Status
Byte. This can be seen in Figure 4.

A device will exit the remote state and enter RWLS
(remote with lockout state) if the LLO (local lockout)
message is true and ACDS is active. In this mode, those
local messages which control functions which are also
controlled by remote messages are ignored. In other
words, the "rtl" message is ignored. A device will exit
RWLS and go to the local state ifREN goes false. The
device will exit RWLS and go to LWLS if the GTL
message is true and the device is addressed to listen.

When a slave device needs service it drives the SRQ line
on the GPIB bus true (low). For the 8291A this is done
by setting bit 7 in the Serial Poll Status Byte. The CPU
in the controller may be interrupted by SRQ or it may
poll a register to determine the state of SRQ. Using the
8292 one could either poll the interrupt status register
for the SRQ interrupt status bit, or enables SRQ to
interrupt the CPU. After the controller recognizes a
service request, it goes into the serial poll routine.

Polling
The IEEE-488 standard specifies two methods for a
slave device to let the controller know that it needs
service.

rf
I

The first thing the controller does in the serial poll routine is assert ATN. When ATN is asserted true the
controller takes control of the GPIB, and all slave de-

SERVICE REQUESTED

0: SERvICE NOT REQUESTED

8

7

L-

6

•

•

•

•

•

1

I

DEVICE DEPENDENT STATUS BITS----1

TYPICAL HP UF-1SE: 1:

SERVICE REQUESTED

0: SERVICE NOT REQUESTED
8

NOT USED

7

6

•

W

•

•

DEVICE DEFINED
1: OPERATION COMPLETE

0:

BUSY

11:

ERROR

10:

NORMAL

1-.-------1

Figure 4_ The Serial Poll Status Byte

3-9

,

230832-3

AP-166

vices on the bus must listen. All bytes sent over the bus
while ATN is true are commands. After the controller
takes control, it sends out a Universal Unlisten (UNL),
which tells all previously addressed listeners to stop listening. The controller then sends out a byte called SPE
(Serial Poll Enable). This command notifies all of the
slaves on the bus that the controller has put the GPIB
in the Serial Poll Mode State (SPMS). Now the controller addresses the first slave device to TALK and puts
itself in the listen mode. When the controller resets
ATN the device addressed to talk transmits to the controller its Serial Poll Status, Byte. If the device just
polled was the one requesting service, the SRQ line on
the GPIB goes false, and bit 7 in the serial ppll status
byte of the 8291A is reset. If more than one device is
requesting service, SRQ remains low until all of the
devices requesting service have been polled, since SRQ
is wire-ored. To continue the Serial Poll, the controller
asserts A TN, addresses the next device to talk then
reads the Serial Poll Status Byte. When the controller is
finished polling it asserts ATN, sends the univeral untalk command (UNT), then sends the Serial Poll Disable command (SPD). The flow of the serial poll can be
seen from the example in Figure S.

B. CONTROLLER RECOGNIZES SRQ AND
ASSERTS ATN

The 8292's SPI pin 33 interrupts the CPU. The CPU
reads the 8292's Interrupt status register and finds the
SRQ bit set. The CPU tells the 8292 to 'Take Control
Synchronously' by writing a OFDH to the 8292's command register.
C. THE CONTROLLER SENDS OUT THE
FOLLOWING COMMANDS: UNIVERSAL
UNLISTEN (UNL), SERIAL POLL ENABLE (SPE),
MY TALK ADDRESS (MTA)

(MTA is a command which tells one of the devices on
the bus to talk.)
The CPU in the controller waits for a BO (byte ,out)
interrupts in the 8291A's interrupt status I register before it writes to the Data Out register a 3FH (UNL),
18H (SPE), OIOXXXXX (MTA). The X represents the
programmable address of a device on the GPIB. When
the 8291 A in the slave device receives its talk address,
the ADSC bit in the Interrupt Status register 2 is set,
and in the Address Status Register T A and TPAS bits
are set.

0) DEVICE A REQUESTS SERVICE (SRQ)
I) ASSERT ATN
2) UNIVERSAL UNLISTEN (UNL)
3) SERIAL POLL ENABLE (SPE)
4) DEVICE A TALK ADDRESS (MTA)
5) RELEASE ATN
6) DEVICE A STATUS BYTE (STD) (RQS SET)
7) ASSERT ATN
8) DEVICE B TALK ADDRESS (MTA)
9) RELEASE ATN
10) DEVICE B STATUS BYTE (STB) (RQS
CLEAR)
11) ASSERT ATN
12) DEVICE C TALK ADDRESS (MTA)
13) RELEASE ATN
14) DEVICE C STATUS BYTE (STB) (RQS
CLEAR)
15) ASSERT ATN
16) UNIVERSAL UNTALK (UNT)
17) SERIAL POLL DISABLE (SPD)
18) GO PROCESS SERVICE REQUEST

D. CONTROLLER RECONFIGURES ITSELF TO
LISTEN AND RESETS ATN

The CPU in the controller puts the 8291A in the listen
only mode by writing a 40H to the Address Mode register of the 8291A, and then a OOH to the Aux Mode
register. The second write is an 'Immediate Execute
pon' which must be used when switching addressing
modes such as talk only to listen only. To reset ATN
the CPU tells the 8292 to 'Go To Standby' by writing a
OF6H to the command, register. The moment ATN is
reset, the 8219A in the slave device sets SPAS in Interrupt Status 2 register, and transmits the serial poll
status byte. SRQS in the Serial Poll Status byte of the
8291A slave device is reset, and the SRQ line on the
GPIB bus becomes false.
E. THE CONTROLLER READS THE SERIAL
POLL STATUS BYTE, SETS ATN, THEN
RECONFIGURES ITSELF TO TALK

Figure 5. Serial Polling

The CPU in the controller waits for the Byte In bit (BI)
in the 8291A's Interrupt Status I register. When this bit
is set the CPU reads the Data In register to receive the
Serial Poll Status Byte. Since bit 7 is set, this was the
device which requested service. The CPU in the controller tells the 8292 to 'Take Control Synchronously'
which asserts ATN. The moment ATN is asserted true
the 8291A in the slave device resets SPAS, and sets the

The following section describes the events which happen in a serial poll when 8291A and 8292 are the controller, and another 8291A is the slave device. While
going through this section the reader should refer to the
register diagrams for the 8291A and 8292.
A. DEVICE A REQUESTS SERVICE
(SRQ BECOMES TRUE)

The slave devices rsv bit in the 2819A's serial poll mode
register is set.
3-10

inter

AP-166

Serial Poll Complete (SPC) bit in the Interrupt Status 2
register. The controller reconfigures itself to talk by setting the TO bit in the Address Mode register and then
writing a OOH to the Aux Mode register.

The S bit is the sense bit. If the "ist" (individual status)
local message value matches the sense bit, then the
829lA will give a true response to a parallel poll. Bits
P3-PI identify which data line is used for a response.
For example, assume the programmer decides that the
system containing the 829lA shall participate in parallel poll. The programmer, upon system initialization
would write to the Aux Mode Register and reset the U
bit and set the S bit plus identify a data line (P3-PI
bits). At "pon," the 8291A would not respond true to a
parallel poll unless the parallel poll flag is set (via Aux
Mode Register command).

F. THE CONTROLLER SENDS THE COMMANDS
UNIVERSAL UNTALK (UNT), AND SERIAL POLL
DISABLE (SPD) THEN RESETS THE SRQ BIT IN
THE 8292. INTERRUPT STATUS REGISTER

The CPU in the controller waits for the BO Interrupt
status bit to be set in the Interrupt Status I register of
the 829lA before it writes 5FH (UNT) and 19H (SPD)
to the Data Out register. The CPU then ,,(rites a 2BH
to the 8292's command register to reset the SRQ status
bit in the Interrupt Status register. When the 829lA in
the slave device receives the UNT command the ADSC
bit in the Interrupt Status 2 register is set, and the T A
and TPAS bits in the Address Status register will be
reset. At this point the controller can service the slave
device's request.

When a status condition in the user system occurs and
the programmer decides that this condition warrants a
true response, then programmers software should set
the parallel poll flag. Since the S bit value matches the
"ist" (set) condition a true response will be given to all
parallel polls.
An additional method of parallel polling reading exists
known as a PPI implementation. In this case the controller sends a PPE (parallel poll enable) message. PPE
contains a bit pattern similar to the bit pattern used to
program the "Ipe" local message. The 829lA will receive this as an undefined command and use it to generate an "Ipe" message. Thus the controller is specifying
the sense bits and data lies for a response. A PPD (parallel poll disable) message exists which clears the bits
SP3P2Pl and sets the U bit. This also will be received
by the 829lA and used to generate an "Ipe" false local
message.

Note that in the software listing of AP-66 (USING
THE 8292 GPIB CONTROLLER) there is a bug in
the serial poll routines. In the 'SRQ ROUTINE' when
the CPU finds that the SRQ bit in the interrupt status
register is set, it immediately writes the interrupt Acknowledge command to the 8292 to reset this bit. However the SRQ GPIB line will still be driven true until
the slave device driving SRQ has been polled. Therefore, the SRQ status bit in the 8292 will become set and
latched again, and as a result the SRQ status bit in the
8.292 will still be set after the serial poll. The proper
time to reset the SRQ bit in the 8292 is after SRQ on
the GPIB becomes false.

The actual sequence of events is as follows. The contro~le~ sends a PPC (parallel poll configure) message.
ThiS IS an undefined command which is received in the
CPT register and the handshake is held off. The local
CPU reads this bit pattern, decodes it, and sends a
VSCMD message to the Aux Mode Register. The controller then sends a ppe message which is also received
as an undefined command in the CPT register. The
local CPU reads this, decodes it clears the MSB and
writes this to the Aux Mode Register generatin~ the
"Ipe" message.

Parallel Poll
The 8291A supports an additional method for obtaining status from devices known as parallel poll (PPOL).
This method limits the controller to a maximum of 8
d~vices at a time since each device will produce a single
bit response on the GPIB data lines. As shown in the
state diagrams, there are three basic parallel poll states:
PPIS (parallel poll idle state), PPSS (parallel poll standby state), and PPAS (parallel poll active state).

The controller then sends ATN and EOI true and the
8291A drives the appropriate· data line if the "ist" (parallel poll flag) is true. The controller will then send a
PPD (parallel poll disable) message (again, an undefined command). The CPU reads this from the CPT
register and uses it to write new "Ipe" message (this'
"Ipe" message will be false). The controller then sends a
PPU (parallel poll unconfigure) message. Since this is
also an undefined command, it goes into the CPT register. When the local CPU decodes this, the CPU should
clear the "ist" (parallel poll flag),

In PPIS, the device's parallel poll function is in the idle
state and will not respond to a parallel poll. PPSS is the
standby state, a state in which the device will respond
to a parallel poll from the controller. The response is
initiated by the controller driving both ATN and EOI
true simultaneously.
The 8291A state diagram shows a transition from PPIS
to PPSS with the "Ipe" message. This is a PP2 implementation for a parallel poll. This "Ipe" (local poll enable) local message is achieved by writing
OilUSP3P2PI to the Aux Mode Register with u=o.
3-11

AP-166

In this example, the 8292 was removed from its socket
and the OPTA and OPTB pins of the two 8293 transceiver reconfigured to modes 0 and 1. Optionally, the
mode pins could have been left wired for modes 2 and 3
and the 8292 left in its socket with its SYC pin wired to
ground. This would have produced the same effect.

APPLICATION EXAMPLES
In the course of developing this application note, two
complete and identical; GPIB systems were built. The
schematics and block diagrams are contained in Appendix 1. These systems feature an 8088 CPU, 8237 DMA
controller, serial I/O (8215a and 8253), RAM,
EPROM, and a complete GPIB talker/listener controller. Jumper switches were provided to select between a
controller function and a talker/listener function. This
system design is based on the design of Intel's SDK-86
prototypi{lg kit and thus shares the same I/O and
memory addresses. This system uses the same download software to transfer object files from Intel development systems.

The first action performed is sending IFC. Generally,
this is done when a controller first comes on line. This
pulse is at least 100 /los in duration as specified by the
IEEE-488 standard.
The software checks to see if active listeners are on line. '
For demonstration purposes, the HP 9835A will flag
the operator to indicate that listeners are on line.
The HP 9835A then configures and performs a parallel
poll (PPOL). The parallel poll indicates I bit of status
of each device in a group of up to 8 devices. Such information could be used by an application program to determine whether optional devices are part of a system
configuration. Such optional devices might include
mass storage devices, printers, etc., where the application software for the controller might need to format
data to match each type of device. Once the PPOL
sequence is finished, the HP 9835A offers the user the
opportunity to execute user commands from the keyboard. At this time the HP 9835A sits in a loop waiting
for an SRQ condition. When the operator hits a key on
the keyboard, the HP 9835A processor is interrupted
and vectors to a service routine where the key is read
and the appropriate routine is executed. The HP 9835A
will then return to the loop checking for the SRQ true.
For this application, the valid keys are G, D, R, H, and
X. Pressing the "G" key causes the GET command to
be sent across the bus. A message to this effect is printed in the CRT and the HP 9835A returns. The "D" key
causes the SDC message to be sent with the 8291A
being the addressed device. Again, an appropriate mesage is output on the HP 9835A CRT. The "R" key
causes the GTL message to be sent. The CRT displays
"REMOTE MESSAGE SENT." The "H" key causes a
menu to be displayed on the HP 9835A CRT screen.
This menu lists the allowed commands and their functions. NO GPIB commands are sent. The "X" key allows the operator to send one line of data across the
bus. The line of data is terminated by a carriage return
and line feed produced by pressing the "CONTINUE"
key on the HP 9835A.

Two Software Drivers
Two software drivers were developed to demonstrate a
ton/lon environment. These two programs (BOARD 1
and BOARD 2) are contained in Appendix 2.
In this example, one of the systems (BOARD 1) initially is programmed in talk-only mode and synchronization is achieved by waiting for the listening board to
become active. This is sensed by the lack of a GPIB
error since a condition of no active listener produces an
ERR status condition. Board 1 upon detecting the presence of an active listener transmits a block of 100 bytes
from a PROM memory across the bus. The second system (BOARD 2) receives this data and stores it in a
buffer, EO! is sent true by the talker (BOARD 1) with
the last byte of data. Upon detection of Eo!, BOARD
2 switches to the talk only mode while BOARD 1 upon
terminal count switches to the listen only mode.
BOARD 2 then detects the presence of an active listener and transmits the contents of its buffer back to
BOARD 1 which stores this data in the buffer. EO!
again is sent ,with the last byte and BOARD 2 switches
back to listen-only. BOARD 1 upon detecting EO!
then compares the contents of its buffer with the contents of its PROM to ensure that no data transmission
errors occurred. The process then repeats itself.

8291A with HP 9835A
An example of the 8291A used in conjunction with a
bus controller is also included' in this application note.
In this example, the 8291A system used in previous
experiments was connected via the GPIB to a HewlettPackard 9835A desktop computer. This computer contains, in addition to a GPIB interface, a black and
white CRT, keyboard, tape drive for high quality data
cassettes, and a calculator type printer. The software
for the HP9835S is shown in Appendix 3. The user
should refer to the operation ,manuals for the
HP 9835A for information on the features and programming methods for the HP 9835A.

The characters are stored in the sequence entered into a
buffer whose maximum size is 80 characters. Pressing
the "CONTINUE" key terminates storing characters
in the,array and all characters including the carriage
return and line feed are sent. EOI is then sent true with
a false byte of OOH. This false byte is due to the 1975
standard which allows asynchronous sending and reception of EO!. (The 8291A supports the later 1978
standard which eliminates this false byte.)

3-12

inter

Ap·166

After any key command is serviced control returns to
the loop which checks for SRQ active. Should SRQ be
active, then the keyboard interrupt is disabled and a
message printed to indicate that SRQ has been received
true.

Next, the GET bit is examined and if true, the CRT
screen connected to the serial channel on the 8291A
system prints a message to indicate that the trigger
command has been received. A similar process occurs
with the DEC and REMC status bits.

The controller then performs a parallel poll.

Address Status Chagne (ADSC) is checked to see if the
8291A has been addressed or unaddressed by the controller. If ADSC is false, then the software checks the
keyboard at the CRT terminal. If ADSC is set, then the
T A and LA bits are read and evaluated to determine
whether the 8291A has been addressed to talk or listen.
The DMA controller is set to start transfers at the start
of the character buffer and the type of transfer is determined by whether the 8291A in in TADS or LADS.
We only need to set up the DMA controller since the
transfers will be transparent to the system processor.
The keyboard from the CRT terminal is then checked.
If a key has been hit, then this character is stored in the
character buffer and the buffer printer set to the next
character location. This process repeats until the received character is a line feed. The line feed is echoed to
the CRT, the serial poll status byte updated and the
SRQ line driven true. This allows the 8291A system to
store up to one line of characters before requesting a
transfer to the controller. Recall that upon receiving an
SRQ, the controller will perform a serial poll and subsequently address the 8291A to talk. The 8291A system
then goes back to reading the status register thus repeating the process.

This is an example of how parallel poll may be used to
quickly check which group of devices contains a device
sending SRQ. The eight devices in a group would, of
course, have software drivers which allow a true response to a PPOL if that device is currently driving
SRQ true. This would be a valuable method of isolation
of the SRQ source in a system with a large number of
devices. In this application program, only the response
from the 8291A is of concern and only the 8291A's
response is considered. It does, however, demonstrate
the technique employed. If a true response from the
8291A is detected, then a message to this effect is printed on the HP 9835A CRT screen. From this process,
the controller has identified the device requesting service and will use a serial poll (SPOL) to determine the
reason for the service request. This method of using
PPOL is not specifically defined by the IEEE-488 standard but is a use of the resources provided.
The controller software then prints a message to indicate that it is about to perform a serial poll. This serial
poll will return to the controller the current status of
the 2819A and clear the service request. The status byte
received is then printed on the CRT screen of the
HP 9835A. One of the 8291A status bits indicates that
the 8291A system has a field (on line or less) of data to
transfer to the HP 9835A. If this bit is set, then the
HP 9835A addresses the 8291A system to talk. The
data is sent by the 8291A system is then printed on the
CRT screen of the HP 9835A. The HP 9835 then enables the keyboard interrupts and goes into its SRQ
checking loop.

CONCLUSION
This application note has shown a basic method to view
the IEEE 488 bus, when used in conjunction with Intel's 8291A.
The main reference for GPIB questions is the IEEE
Standard 488-1978. Reference 8291A's data sheet fOT
detailed information on it.

Appendix 4 contains the software for the 8291A system
which is connected to the HP 9835A via the GPIB.
This software throws away the first byte of data it receives since this transfer was used by the HP 9835A to
test when the 8291A system came on line.

Additional Intel GPIB products include iSBX-488,
which is a multimode board consisting of the 8291A,
8292, and 8293.

REFERENCES

Next; both status registers are read and stored in the
two variable STAT 1 and STAT 2. It is necessary to
store the status since reading the status registers clears
the status bits.

8291A Data Sheet
8292'Data Sheet
8293 Data Sheet
Application Note #66 "Using the 8292 GPIB Controller"
PLM-86 User Manual
HP 9835A User's Manual
IEEE-488-1978 Standard

Initially, six status bits are evaluated (END, GET,
CPT, DEC, REMC, ADSC). Some of these conditions
require that additional status bits be evaluated.
If END is true, then the 8291A system has received a

block from the HP 9835A and the contents of a buffer
is printed on the CRT screen. Next, the CPT bit is
checked. PPC and PPE are only valid undefined commands in this example.
3-13

intJ

AP-166

APPENDIX A
SYSTEM BLOCK DIAGRAM WITH 8088

3-14

inter

AP-166

APPENDIX B
SOFTWARE DRIVERS FOR BLOCK DATA TRANSFER

PL/M--86 COl1P ILER

DOARD I

ISIS--II PLlI1-86 'J!!
COMPILATIUI, OF MODULE BOARD 1
DeJECT MODl'LE F'LACED IN
F1
nRDI
or;",
COMPILER II-IVOKED BY:
PLl1Bo.
FI:
BRDI.
SRC SYMBOLS MEDIUM

1*
i

*

1*
/..

1*

,*

1*
1*

!.~

1*
1*

1*
1*
1*
1*

1*

BOARD 1 TPT PROGRAM
.*1
TH I S U Of-/; D TAL~.S Ttl THE OTHER 1leAR Ll fl"
~I
TRANSFERR!NG A BLOCI-I OF DATA VIA THE 8237
<0,
COUPLED I.ITH THE 8291A
THE 8291A IS PROGRAM- *1
MED TO SEND EOI I.HEN RECOGNIZING THE LAST
*1
DATA BiTE'S BIT PATTERN.
WHILE DATA IS BEING *1
TRANSFERRED, THE PROCESSOR PERFORMS
110 READS *1
OF THE (,237 CC'Jtn REGIS1ERS TO SIMULATE. BUS
*1
ACTIVITy, AND TO DEl ERMINE WHEN TO TURN THE
*1
LINE ARC1UND. AFTER THE 8237 HAS REACHED
*1
TERMINAL COUNT, THE 8291A. IS PROGRAMMED TO
*1
THE L.lSTENER STATE At,D WAITS FOR THE BLOCK
*1
TO BE TR"'NSMITTED /lACK FROM THE SECOND BOARD. *1
THIS D':'TA IS FL_ACED IN A SECOND BUFFER AND
*1
ITS CotHErns cor1PARED WITH THE ORIGINAL DATA *1
TO CHECK FOR INTERFACE WTEGR ITY.
*1

BOARDI:
DO,

1* PROCEDURES *!

co:

2
3

2

4
5

;;;
3

6

2
2

7

PROCEDURE (X XX)
DECLARE XXX BYTE.
SERSSTAT LITERALLY
'OFFF2H'.
SER~DATA
LITERALLY
'OFFFOH',
TXRDY
LITERALLY
'01H',
DO 1.HILE 'INPUT
(SERSSTATl AND TXRDY)
END;
OUTPUT (SERSDATA)
xxx;
END CO;

9

TXRDY;

=

, '"
B

<>

SETUP BUFFERS *1
DECLARE BUFF2 (100)
BYTE;
1* RAM STORAGE AREA
DECLARE BUFF! (lOa) BYTE DATA

*J

(1,2,3,4,5,6.7,8,9,10H,
IIH,
21H.
3tH.
4tH.
5tH.
61H,
7tH,
81H·

l~H,

22H,
32H,
42H.
52H,
62H.
72H.
82H,

13H.
23H.
33H.
43H.
53H.
63H.
73H,
83H.

14H.
24H.
34H.
44H.
54H.
64H.
74H,
84H.

15H,
25H,
35H.
45H.
55H.
65H.
75H,
85H.

16H.
26H.
36H.
46H.
56H.
66H.
76H.
86H.

IlH.
2lH.
37H.
47H.
57H.
67H.
77H.
S7H.

18H.
28H.
38H.
48H.
5SH.
68H.
78H.
8SH.

19H.
29H.
39H.
49H.
59H.
69H.
79H.
89H.

20H.
30H.
40H.
50H.
60H.
70H.
80H.
90H.

230832-5

3-15

intJ
PL/M-86

10

AP·166

COliP ILER

!l1J/~RDl

Q1H, 92H, 93H, 94H, 95H, 96H, 97H, 98H,
DECLARE !lIJFF3(17)
!lYTE DATA
(O[)H, OAH. 'COf1PARE ERROR', OD" C.4fO,
,."

11

8~3?

POPT ADDRESSES

ODH),

1* ROM STORAGE AREA *1

DDRESS VARIABLES 
1* WAIT FOR EOT RECEIVED */

(STATUS$2)

·=DMA$REQ$L.

1*

*1

*1

ONE,

230832-8

. 3·18

infef

AP-166

PLlM-S<,> COMPll..EP

[WAF.l'

CMPM.~.~

70

,"

rC~PARE

I1ATC:H=CMPB
71

IF r1ATCH
.",'

73
74
75

THE HIO BIJFFERS CONTENTS *1
'.@BUFFI.

100);

SE'm ERROR MESSI'GE IN BUt=FER 3

DO 1=1) ro 10;
CALL CO
(BUFF 3
END;

1
2
.2

@DUFF2,

OKAY THEN GOTO START91;

(I)

*1

);

(;OTO START91;

7<:.
77

MODULE INFORMATION:

CODE AREA SIZE
CONSTANT AREA SIZE
VARIABLE AREA SIZE
MAXIMUM STACK SIZE
243 LINES READ
o PROGRAM CRflCR (5l
END OF PL/t1-80

=OlOBH
=0075H
=0070H
=OOOoH

4750
1170
1120
00

COMPILATION

230832-9

3-19

intJ

AP-166

PL/M-86 Cot1P ILER

1l0ARD2

ISIS-II PL/M-86 VI. I COt1PILATION OF MODULE BOARD2
OBJECT t10DULE PLACED IN
FI- BRD2, OBJ
COMPILER INVO"'ED BY:
PLM86
Fl
BRD2, SRC
/. BOARD 2 TPT PRO~RAM

*/

1*
*1
1* THIS BOARD LISTENS TO THE OTHER BOARD (I)
*1
1* AtJD Dt1A'S DATA INTO A BUFFER, I,HILE WAITING *1
1* FOR THE END jtHERRUPT BIT TO IlECOt1E ACTIVE *1
;* l'PON END ACTIVE, THE DATA IN THE BUFFER IS *1
1* SENT 6AC~ TO THE FIRST BOARD VIA THE GPID
*1
1* ~HEN THE BLOC'" IS FINISHED THE 8291A IS *1
1* PROGRAt1MED BAC'" INTO THE LISTENER MODE
*1
BOARD2
DO;

1* 8237 PORT ADDRESSES *1
2

DECLARE
CL.EAf'SFF
STARTSOSLo
STARTSOSHI
OSCOUNTSLO
OSCOUNTSHI
SET$MODE
Ct1D'I>37
SEHMAS'"

1* 8237 COMMAND
3

-

DATA BYTES

I*MASTER CLEAR *1

*i

DECLARE
LI TERALLY
RDSTRANSFER
LITERALLY
WRSTRANSFER
ADDRUA
LITERALLY
ADDRSlll
LITERALLY
tJORt1STIME
LITERALLY
TCSLOI
LITERALLY
TC$HII
LITERALLY
LITERALLY
TCSL02
TCSHI2
LITERALLY
TC
l.ITERALLY

I. 8291,0.
4

'OFFDDH' ,
'OFFDOH' ,
'OFFDOH',
'OFFDIH',
'OFFDIH',
'OFFDBH',
OFFD8H' ,
'OFF-DFH' ,

LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLV
LITERALLv

'48H ,
'44H',
'OOH',
'OIH',
'20H' ,
'OFFH',
'OOH',
'990',
'OOH',
'OIH' ,

PORT ADDRESSES *1

DECLARE
PORTSOUT
PORHIN
STATUSSI
STATUSS2
ADDRSSTATUS
COt1t1ANDSt10D

LITERALLY
LITERALLY
l.ITERALLY
LITERALLY
LITERALLY
LITERALLY

'OFFCOH' ,
'OFFCOH',I* DATA IN *1
'OFFCIH', 1* INTR STAT I *1
'OFFC2H', 1* INTR STAT ~ *1
'OFFC4H', 1* ADDR STAT
*1
'OFFC5H', 1* Ct1D PASS THRU *1

230832-10

3-20

inter

AP-166

PL IM-Bb Cot1P 1 LCR

5

Rur,r'D2
ADDRSO
EOSSREG

LITERALLY
LITERALLY

/. 829tA

COMMAND - DATA BYTES *1

EOS REGISTER *1

'BSH',
'tOH',
'~OH',
'O~H/,

'OOH',
'IOH',
'20H',
'BOH "
'40',
'ODH',
'23H .,
'A4H',
'02H',.
'OIH',
'(j4H' ,

START91,

b

OUTPUT
;.
7

(STATUSS2)

I~IT

8~37

=CLEAR'

1*

END INITILIZATION STATE *1

FOR LISTENER FUNCTION

0'

INIT37L,
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPLUT

8
9
10
II
12
13
14

/...
I~

2

I1~IT

'*

(CLEARSFF)
=CLEAR,
TOGGLE MASTER RESET *1
(Cr1DS37l
=NORMSTlr1E,
iSETSr10DE)
=WRSTRAr~SFER,
1* IlLOC¥. XFER MODE *1
(SETSMASK)
=CLEAR,
(STARTSOSLO)
=ADDRSIA,
(STARTSOSHI)
=ADDRSIIl,
(OSCOUIHSLO)
=TCSLO I;
(OSCOUNTSHI>
=TCSHI1,
8291A

DO

I~HILE

*1

FOR LISTENER FUNCTIONS

OUTPUT
(COMI1ANDSMOD)
=RESET,
OUTPUT
(ADDRSSTATUS)
=MOD!SLO,
OUTPUT
(COMMAND$MOD)
:PON,
DO I~HILE \ INPUT
(STATUSS!)
AND Ill)
END,
I~
WAIT FOR III INTR *1
XYZ= INPUT
(PORTSIN),
OUTPUT
(STATUSS2)
=DI1ASREQSL;

1* IJAIT urHIL EOl RCVD
22

1*

DECLARE
ENDSEOI
LITERALLY
DNE L ITER ALL Y
FOIl
L lTER4l.LY
RESE"T
L ITER ALL Y
CLEAR
1.I TERALL Y
Dt1ASREQSL L ITER ALL Y
DMASREQST LITERALLY
MODISTO
LITERALLY
MODULO
LITERALLY
EOS LI1ERALLY
PRESCALEf< L I TERAl.I_ Y
HIGH$SPEED LITERALLY
XY!
IlYTE,
110
LITERALLY
III
LITERALLY
ERR
I I TERALLY

16
17
lB
19
20
2!

'OFFC6H',
'OFFC7H',

(INPUT

AI~D

=0,

*1

END WTR-IlIT SET

(STATUSSI)

AI~D

ONE)

<>

ONE,

230832-11

3-21

AP-166

PL/M··8e.

CClMPIL.ER

BOARD2
END.

24

INIT37T.
1* INIT 8237 FOR TA'_KER FUNCTION
OUTPUT
OUTPUT
OUTPUT
(IUTPU·r
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

25
26
27

28
29
30
31
32

1*
33
34
35
36

1
1
1"

37
38
39
40
41
42
43
44
45
46

=ENDSEOI, 1* EOI ON EOS SENT
=r10D1STO; 1* TALK ONLY *1
=PRESCALER.
=HIGHSSPEED;

DO LIH I LE
 =CLEAR;
(STARTS()SLO I '
=ADDRS1A.
(STARTSOSHI)
=ADDRS1B.
(OSCOUNTSLO)
=TCSL02.
(OSCOUtHSHI I
=TCSHI2.

( INPUT

(CMOS37)

ANO TC)

<>

TC.

GOTO STARr91.
END;

MODULE W""ORMATION
CODE AREA SIZE
CONSTANT AREA SIZE
VARIABLE AREA SIZE
MAXIMur1 STACK SIZE
152 LINES READ
o PROGRAM ERROR (S)

=0122H
=OOOOH
=OOOIH
=OOOOH

2900
00
10
00

230832-12

3-22

inter

Ap·166

APPENDIX C
SOFTWARE FOR HP 9835A

10

REM S£lirl 11.

St

TERFACE CLEAR
20
ABORTIO 7
30
REM FORCE E
RRORS UNTIL LIST
ENERS ACTIYE
40 Freerr:
OUT
PUT 70~ US IIlG ",I
,KM; "liM

(\~

..

OF:Mllle. 5EPIAL PO

17'0 51" .:t=E: IUAIlD r
Stotld,f.S)

l~

180
IF Srq=O TH
EN (,010 I eo o:-ti

"3'::0

330 PRINT CHR. (
12), "St.atus = ";

L RESPONSE MESSA

THEtl GOTO Pc ')r
539 GOTO' Eo', en
531 Rcvr:
REM R

510t

2313

5~O

Ppo 11 byt e=P

2.68--P~o11b1~e=:E:
IHAND (Ppol1 b1u-,
0,
279 IF Ppol1b,t
.=0 THEN GOTO .,
291
2BO PRINT "SP
NOT FROf1 8291"
281
PRItH "COtH!
AND = ?
(HIT
'H' FOP L1STl"

110
! reSr:loons.e ·:.r.
bit 4
120 PPlllY CHF"
12'. "PARAllEL PO
I I COIIFIGUPED"
130 REM El~ABlE
~EYBOARD IllYERRU
PT
140 PRIIH ·COrll1
AllD
?
(HIT
'H' FOP LIST,"
150 r.e~en:
au "ID GOSUB 610
160 STATUS 7; S'
o.t.l, StQt2, Stat3,

=

290

IF D tEo .... 0

12),"SELECTIVE It
E ..... I CE CLEAR ~.Etn

EADY TO RCY CHAR
S FROM GPIB
540 DIM GUB01
550 ENTER 794 U
SING "~,T~;Gt
560 PRINT CHRfI
12) ,C$
570 PRINT "COMM
RtiD = '?
(HIT
'H' FOR L1STl"
589 COTO key eon
599 REM IHTERRU
PT SERYICE ROUTI
NES
600 REM GET KEY
BOARD DATA
610 ~hatke'i:
DI
M KnSOl
€ 2D K$=V-BDt
630 IF K$="G"

POlL(7)
240 PRlllY "PARA
LLEL POLL B','lE =
.. ; Ppcfl1 b~..t ...
2'50 PPltlT ___ _

(10"

.

340 :1 t.;r=BIIlAtI
It ISt;::t. l'

GE"
220 REM EXECUTI
NG PARAllEL POll

SO
PRIIlT CHRrr
12J, "LISTEUE~S A
RE Oil L1I1E
90
~El-l COIIFIGU
RE PPOll
100 PPOll COli,:
GURE 70';; MOOCH)·::

S HIlUS 7'04;

OF:=- l.to.
200 PPItlT CHR$ (
12). "SP0 PECEIVE
D" '
210 PRIIlT "SEIID
ING PARAllEL POL

-;'0
IF Err=1 TH
EN COTO FrcE'rr

690 FR IIH CHRf(
12). "GROUP E~:ECU
TE TRIGGEP SEln"
700 PRIIH
710 PRINT "COml
AUD = ?
(HIT
'H' FOP L1STl"
720 RETURII
730 Doc:
RESET
794
740 PRINT CHR$ (

Stat

l.,r,

50 Chkst.st:
ST
RTUS 71 St. Go t 1 , 51 0.
t2,Sta.t3,Sto.t4
60
Err=S.tot;.:o A
liD

R 704

TO GET STATUS

GOTO t:eYEn

HEN

300 PB291:
PRill
T "SRO IS FROM U

640

GOT a

~50

780 Po?M:

650

EIITERPRI SE"
310 PRlIlY "PEPF

Ge~

IF Kt="D"

@@

850 PRINT
hit
koY
resul \"
860 PRINT

IF K$="R" T

HEN GOTO Rel'1

660 IF I:$="H"
HEll GOTO He).
670 IF KS="X" T
HEN GO TO X.it
690 Ge\l
TRI~-:'E

230832-13

LOCAL

704
790 PR IIH CHRt l
12" "REMOTE "ESS
AGE SENT"
B00 PRINT·"
810 PRINT "COMM
AND = ?
(HIT
'H' FOR lISTl"
B20 RETURII
B30 HoI.: . PRINT
CHRt (IZ)
840 PRINT
@@@
@ OPERATOR ALlOU
ABLE COMMANDS @@

HEN COTO Dec

CC 8.=91 ••• THE

PRIIlT'·~

760 PRIUT "COMM
(HIT
AND = ".
'H' FOP LJST1~
770 F.ETUf'I,

Send GET

1'1

E'fSo.'Je,"

870

PRINT
Send D€.C

1"1

essd'Je"

230832-14

B~0

PRINT

940 X"d t I DIM A
U80l
950 PRIIH CHRf (
12), "Enter data

Send P.EM,

DC l'IE'ssaSle"

890

PRINT
Xl'li ts ked:
to :: ~

Odrd

1 npu~

91"
900

PRINT "

to send o.nd h1t

CONTlIIUE"
960 IIIPUT At
970 OUTPUT 794;
AS
97: EOI 7;0
980 PRINT "COMM
AND = ?
(HIT
'H' FOR LIST)"
990 RETURN
1909 EIlD

H

Prints thi
s to.ble"

910
920
90

'"

,:i0

PRINT
PRlNT
a.head,

TRY'

it

RETUPII

3-23

230832-15

Ap·166

APPENDIX D
SOFTWARE FOR HP 8088/HP 983SA VIA GPIB

PL/M-B6 COMPILER,

HPID

ISIS-II PL/M-B6 VI. 1 COMPILATION OF MODULE HPID
OBJECT MODULE PLACED IN :Fl:HPIB.oBJ
COMPILER INVOKED BY: PLMB6 :FI:HPIB.SRC LAROE

HPIB:
1*

PARAMETER DECLARATIONS
*1

DO.
2

DECLARE
ADDR.HI
LITERALLY
'OIH',
ADDR.LO
LITERALLY
'OOH',
ADSC
LITERALLY
.'OIH',
BI
LITERALLY
'OIH',
Bo
, LITERALLY
'02H',
CHAR.CoUNT BYTE,
CHAR
BYTE,
CHARS(SO)
BYTE,
CLEAR
LITERALLY
'OOH',
CPT
LITERALLY
'SOH',
CRLF
LITERALLY
'OAH',
DEC
LITERALLY
'OSH',
DMA.ADR.LSTN
POINTER,
DMA.ADR.TALK
POINTER,
DMA.WRD.LSTN(2) WORD AT
(eDMA.ADR.LSTNI,
DMA.WRD.TALK(2) WORD AT
(eDMA.ADA.TALK),
DMA.REO$L
LITERALLY
'IOH',
DMA.REO.T
LITERALLY
'20H',
DNE
LITERALLY
'IOH',
END.EOI
LITERALLY
'SSH' ,
LITERALLY
'ODH',
EoS
ERR
LITERALLY
'04H',
QET
LITERALLY
'20H',
I
BYTE,
LISTEN
LITERALLY
'04H',
MLA
LITERALLY
'04H',
MODE. I
LITERALLY
'OIH',
NO$DMA
LITERALLY
'OO,H',
NO.RSV
LITERALLY' OOH' ,
NORM$TIME
LITERALLY
'20H',
PON
LITERALLY
'QOH',
PPC
LITERALLY
'05H',
PPE.MASK
LITERALLY
'60H',
PPOLL$CNFQ.FLAQ LITERALLY
'OIH',
PPOLL$EN$BYTE
BYTE,
PRI$BUF(BOI BYTE AT
(eCHARS),
RD$XFER
LITERALLY
'4SH',
RESET
LITERALLY
'02H',
REMC
LITERALLY
'02H',
RSV
LITERALLY
'40H',
RXRDY
LITERALLY
'02H' ,

3-24

230832-16

intJ

Ap·166

PL/M-B6 COMPILER

HPIB

SROS
LITERALLY
'40H',
STATl
BVTE,
STAT2
BVTE.
TALK
LITERALLV
'02H'.
TASORSLA
BVTE.
TRO
LITERALLV
'41H'.
TC
LITERALLV
'OlH'.
TCSHI
LITERALLV
'~OH'.
TCSLO
LITERALLV
'OFFH'.
TXRDV
LITERALLV
'OlH'.
UDC
BVTE.
WRSXFER
LITERALLV
·44H'.
XVZ
BVTE,
1*

PORT DECLARATIONS
*1

3

DECLARE
ADDRsO
ADDRSSTATUS
CLEARSFF
CMDS37
COMMANDSMOD
COUNTSHI
COUNTSLO
CPTSREG
EOSSREG
PORTSIN
PORTSOUT
SERSDATA
SERsSTAT
SETsMASK
SETSMODE
SPOLLSSTAT
STARTSHI
STAR TSLO
STATUSSl
STATUSS2
1*

,
4

6
7
B

c~t

DECLARE
DECLARE
DECLARE
DECLARE
DECLARE

LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV

message.' list *1
GETSMSG(ll) BVTE DATA (ODH.OAH. 'TRIGGER'.OAH.ODH),
DECSMSG(16) BVTE DATA (ODH,OAH. 'DEVICE CLEAR'. OAH. ODH),
REMCSMSG(10) BVTE DATA (ODH.OAH. ·REMOTE'.ODH.OAH),
CPTSMSG(22) BVTE DATA (ODH,OAH. 'UNDEF CMD RECEIVED'.OAH,ODH),
HUHSMSG(ll) BVTE DATA (ODH,OAH. 'HUH ???'.ODH,OAH),

1* called

9

REOSER:

'OFFC6H',
'OFFC4H',
'OFFDDH',
'OFFDBH'.
'OFFC'H'.
'OFFD1H'.
'OFFD1H'.
'OFFC5H'.
'OFFC7H'.
'OFFCOH'.
'OFFCOH'.
'OFFFOH'.
'OFFF2H'.
'OFFDFH'.
'OFFDBH'.
'OFFC3H'.
'OFFDOH'.
'OFFDOH',
'OFFC1H' •
'OFFC2H',

p~Dc.du~.s

*1

PROCEDURE,
230832-17

3-25

Ap·166

PL/M-B6 COMPILER

HPIB

10

2

OUTPUT

11

12

2
3

DO WHILE (INPUT (SPOLL.STATI AND SRBSI-SRBS,
END,

13

2

14

2

l'
16

1

2

17
lB
19
20
21
22
23
24
2'

3
2
2
1
2
3
3

2

2

26
27
2B
29
30
31
32
33
34
35
36
37
3B
39
40
41
42
43
44

2
2

45
46

,OUTPUT (SPOLL.STATI 0NO.RSV,
END REBSER,
CO: PROCEDUREeXXXI,
DECLARE
XXX
BVTE,
DO WHILE (INPUT (SER.STATI AND TXRDVI<>TXRDV,
END,
OUTPUT (SER.DATAI=XXX,
END CO,
HUH:
PROCEDURE,
DO 1=0 TO 10,
CALL CO (HUH.MSG( I I l.i
END,
END HUH,
CI:

3
3
3
3
3
3
3
3
3
4
5
4
4
3
3
2

PROCEDURE,
IF (INPUT (SER.STATI AND RXRDVI=RXRDV THEN
DO,
1l1li0;

STORE.CHAR:

END,
END CI,
TALK.EXEC:

2

(SPOLL.STATI~TRB'

CHAR.COUNT=O,
CHAR-(INPUT (SER.DATAI AND 7FHI,
CHAR.COUNT=CHAR.COUNT+l,
CALL CO (CHAR I ,
CHARS( I I-CHAR,
1=1+1,
IF CHAR <> CRLF THEN
DO,
DO WHILE (INPUT (SER.STATI AND RXRDVI <>RXRDV,
END,
GOTO STORE.CHAR,
END,
CALL REBSER,

PROCEDURE,

OUTPUT (STATUS.21=CLEAR,
1*

manipulate address bits for DMA controller
'*1

47
4B
49

2
2

2

DMA.ADR.TALK= (eCHARS I ,
DMA.WRD.TALK(1 I-SHL(DMA.WRD.TALKCl I. 41,
DMA.WRD.TALK CO I=DMA.WRD.TALK (0 I +DMA.WRD.TALKC 1 I,

50

2

OUTPUT (CLEAR.FFI oCLEAR,
230832-18

3-26

AP-166

PL/M-86 COMPILER
51
52
53
54
55
56
57
58

HPIB

2

2
2
2
2

OUTPUT CCMD37)=NORMSTIME,
OUTPUT CSETSMODE)~RDSXFER,
OUTPUT CSETSMASK)=CLEAR,
OUTPUT CSTARTSLO) =DMASWRDSTALKCO) ,
OMASWROSTALKCO)=SHRCOMASWROSTALKCO).8),
OUTPUT CSTARTSHI)=DMASWRDSTALKCO),
OUTPUT CCOUNTSLO)=CHARSCOUNT,
OUTPUT CCOUNTSHIl=O,

59
60

2
2

OUTPUT CEOS$REQ)=EOS,
OUTPUT CCOMMAND$MOD)=ENOSEOI,

61
62
63

2
3
2

DO WHILE CINPUT CSTATUS$I) AND SO)=O,
END,
OUTPUT CPORT$OUTl=OAAH,

64
65
66
67
68
69

2
3
4
3
3
2

DO WHILE CINPUT CSTATUSS!) AND ERRl=ERR,
DO WHILE CINPUT CSTATUSSI) AND BOl~O,
END,
OUTPUT CPORTSOUTl=OAAH,
END,
OUTPUT CSTATUSS2l=DMA$REOST,

70

2

END TALKSEXEC,

2
2

2

71

LISTEN$EXEC:

PROCEDURE,

72
73
74
75
76
77
78
79
80
81
82
83
84
85

2
2
2
2
2
2
2
2
2
2
2
2
2
2

OUTPUT CSTATUSS2l=CLEAR,
OUTPUT CCLEAR$FFl=CLEAR,
OUTPUT CCMD$37)=NORM$TIME,
OUTPUT CSET$MODEl=WR$XFER,
OUTPUT CSET$MASKl=CLEAR,
DMA$ADR$LSTN=C@CHARS),
DMA$WRD$LSTNC!l=SHLCDMA$WRDSLSTNCll.4l,
DMA$WRD$LSTN(Ol=DMA$WRD$LSTN(O)+DMA$WRO$LSTNC!l,
OUTPUT CSTARTSLOl=DMA$WRD$LSTNCOl,
DMASWRDSLSTNCO)=SHRCOMASWRDSLSTNCOl.8l,
OUTPUT CSTART$HI)=DMA$WRD$LSTNCOl,
OUTPUT CCOUNTSLOl=TCSLO,
OUTPUT CCOUNTSHIl=TCSHI,
OUTPUT CSTATUS$2l=DMA$REO$L,

86

2

END LISTEN$EXEC,

87

PRINTER:

PROCEDURE,

88

2

1=0,

89
90
91
92
93

2
3
3
3
2

DO WHILE PRI$SUFCIl <>CRLF,
CALL CO CPRISSUFCI»,
END,
CALL CO CPRI$SUFCI)l,

94

2

END PRINTER,

1=1+1;

230832-19

3-27

inter

AP-166

PL/M-86 COMPILER

9!1

HPIB

ADSC.EXEC:

PROCEDURE.

96

2

TA.OR.LA=INPUT (ADDR.STATUSI.

97
98
99
100

2
2
2
2

IF (TA.OR.LA AND TALKI=TALK THEN
CALL TALK.EXEC,
IF (TA.OR.LA AND LISTENI-LISTEN THEN
CALL LISTEN.EXEC.

101

2

102
103
104
105
106

1
2
3
3
2

OET.EXEC:

107
108
109
110
111

1
2
3
3
2

DEC$EXEC:

112
113
114
115
116

1
2
3
3
2

REMC.EXEC:

117

END ADSC.EXEC,
PROCEDURE,
DO 1=0 TO 10,
CALL CO (OET.MSO(III,
END,
END OET.EXEC.
PROCEDURE.
DO 1=0 TO 15,
CALL CO (DEC.MSO(III,
END,
END DEC.EXEC,
PROCEDURE,
DO 1=0 TO 9.
CALL CO (REMC.MSO  0.5 volts
implies the device is Not Ready For Data).
The Intel 8293 GPIB transceiver chips ensure that all
relevant bus driver/receiver specifications are met. Detailed bus electrical specifications may be found in Section 3 of the IEEE Std 488-1978. The Standard is the
ultimate reference for all GPIB questions.

GPIB Message Protocols
GPIB Connector

The GPIB is a very flexible communications medium
and as such has many possible variations of protocols.
To bring some order to the situation, this section will
discuss a protocol similar to the one used by Ziatech's
ZT80 GPIB controller for Intel's MULTIBUSTM computers. The ZT80 is a complete high-level interface
processor that executes a set of high leve1.instructions·
that map directly into GPIB actions. The sequences of
commands, addresses and data for these instructions
provide a good example of how to use the GPIB (additional information is available in the ZT80 Instruction
Manual). The 'null' at ·the end of each instruction is for
cosmetic use to remove previous information from the
010 lines.

The GPIB connector is a standard 24-pin industrial
connector such as Cinch or Amphenol series 57 MicroRibbon. The IEEE standard· specifies this connector, as
well as the signal connections and the mounting hardware.
The cable has 16 signal lines and 8 ground lines. The
maximum length is 20 meters with no ·more than two
meters per device.

3-36

inter

AP-66

DATA-Transfer a block of data from device A to de·
vices B, C ...
I) Device A Primary (Talk) Address
Device A Secondary Address (if any)
2) Universal Un listen
3) Device B Primary (Listen) Address
Device B Secondary Address (if any)
Device C Primary (Listen) Address
etc.
4) First Data Byte
Second Data Byte

2) Go To Local
3) Null

LOCAL-Reset all devices to Local
I) Stop asserting REN
LLKAL-Prevent all devices from returning to Local
I) Local Lock Out
2) Null

SPOLL-Conducts a serial poll of devices A, B, ...
1) Serial Poll Enable
2) Universal Unlisten
3) ZT 80 Primary (Listen) Address
ZT 80 Secondary Address
4) Device Primary (Talk) Address
Device Secondary Address (if any)
5) Status byte from device
6) Go to Step 4 until all devices on list have been polled
7) Serial Poll Disable
8) Null

Last Data Byte (EOI)
5) Null

TRIGR-Tfigger devices A, B ... to take action
1) Universal Unlisten
2) Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
3) Group Execute Trigger
4) Null

PPUAL-Unconfigure and disable Parallel Poll re·
sponse from all devices
1) Parallel Poll U nconfigure
2) Null
ENAPP-Enable Parallel Poll response in devices A, B,

PSCTL-Pass control to device A
1) Device A Primary (Talk) Address
Device A Secondary Address (if any)
2) Talk Control
3) Null

1) Universal Unlisten
2) Device Primary (Listen) Address
Device Secondary Address (if any)
3) Parallel Poll Configure
4) Parallel Poll Enable
5) Go to Step 2 until all devices on list have been con·
figured.
6) Null

CLEAR-Clear all devices
1) Device Clear
2) Null

DISPP-Disable Parallel Poll response from devices A,
B, ...
1) Universal Unlisten
2) Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
3) Disable Parallel Poll
4) Null

REMAL-Remote Enable
1) Assert REN continuously
GOREM-Put devices A, B, ... into Remote
1) Assert REN continuously
2) Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
3) Null

This Ap Note will detail how to implement a useful
subset of these controller instructions.

GOLOC-Put devices A, B, ... into Local
1) Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.

3·37

intJ

Ap·66

from the CPU; the other seven control various features
of the 8291.

HARDWARE ASPECTS OF THE
SYSTEM

The 8291 interface functions will be software configured in this application example to the following subsets for use with the 8292 as a controller that does not
pass control. The 8291 is used only to provide the
handshake logic and to send and receive data bytes. It
is not acting as a normal device in this mode, as it never
sees ATN asserted.
SH I Source Handshake
AH I Acceptor Handshake
T3
Basic Talk-Only
LI
Basic Listen-Only
SRO No Service Requests
RLO No Remote/Local
PPO No Parallel Poll Response
DCO No Device Clear
DTO No Device Trigger

8291 GPIB Talker/Listener
The 8291 is a custom designed chip that implements
many of the non-controller GPIB functions. It provides
hooks so the user's software can implement additional
features to complete the set. This chip is discussed in
detail in its data sheet. The major features are summarized here:
- Designed to interface microprocessors to the GPIB
- Complete Source and Acceptor Handshake
- Complete Talker and Listener Functions with extended addressing
- Service Request, Parallel Poll, Device Clear, Device
Trigger, Remote/Local functions
- Programmable data transfer rate
- Maskable interrupts
- On-chip primary and secondary address recognition
- 1-8 MHz clock range'
- 16 registers (8 read, 8 write) for CPU interface
- DMA handshake provision
- Trigger output pin
. - On-chip EOS (End of Sequence)

If control is passed to another controller, ¢e 8291 must
be reconfigured to act as a talker/listener with the following subsets:
SH I Source Handshake
AH I Acceptor Handshake
T5
Basic Talker and Serial Poll
L3
Basic Listener
SRI Service Requests
RLI Remote/Local with Lockout
PP2 Reconfigured Parallel Poll
DCI Device Clear
DTt Device Trigger
CO Not a Controller

The pinouts and block diagram are shown in Figure 5.
One of eight read registers is for data transfer to the
CPU; the other seven allow the microprocessor to monitor the GPIB states and various bus and device conditions. One of the eight write registers is for data transfer

Pin Configuration

Block Diagram

Vee

T/RI
T/R2

EOi
N6Ac
NiiFD

DO

DiY
6iOi
D'i07
Illl!l!
0i0s
Di04
6i'03
Di02
i5i01
SRO
ill
ii'EN

D5

iFC

D6
D7

RS2

Dl
D2

D3

GPIB CONTROL

I

I
I

T/RCONTROL

231324-5

RSI

_ _ _ _ _.1

TO NON·INVERTING
BUS TRANSCEIVERS

R~O

231324-4

Figure 5. 8291 Pin Configuration and Block Diagram

3-38

AP-66

Most applications do not pass control and the controller is always the system controller (see 8292 commands
below).

The status register is used to pass Interrupt Status information to the master CPU (Aa = 1 on a read).
The DBBOUT register is used to pass one of five other
status words to the master based on the last command
written into DB BIN. DBBOUT is accessed when Aa
= a on a Read. The five status words are Error Flag,
Controller Status, GPIB Status, Event Counter Status
or Time Out Status.

8292 GPIB Controller
The 8292 is a preprogrammed Intel 8a51A that provides the additional functions necessary to implement a
GPIB controller when used with an 8291 Talker/Listener. The 8a41A is documented in both a user's manual and in AP-41. The following description will serve
only as an outline to guide the later discussion.

DBBIN receives either commands (Aa = 1 on a Write)
or command related data (Aa = a on a write) from the
master. These command related data are Interrupt
Mask, Error Mask, Event Counter or Time Out.

The 8292 acts as an intelligent slave processor to the
main system CPU. It contains a processor, memory,
. I/O and is programmed to perform a variety of tasks
associated with GPIB controller operation. The on-chip
RAM is used to store information about the state of the
Controller function, as well as a variety of local variables, the stack and certain user status information.
The timer/counter may be optionally used for several
time-out functions or for counting data bytes transferred. The I/O ports provide the GPIB control signals,
as well as the ancillary lines necessary to make the
8291, 2, 3 work together.

8293 GPIB Transceivers
The 8293 is a multi-use HMOS chip that implements
the IEEE 488 bus transceivers and contains the additionallogic required to make the 8291 and 8292 work
together. The two option strapping pins are used to
internally configure the chip to perform the specialized
gating required for use with 8291 as a device or with
8291192 as a controller.
In this application example the two configurations used
are shown in Figure 7a and 7b. The drivers are set to
open collector or three state mode as required and the
special logic is enabled as required in the two modes .

The 8292 is closely coupled to the main CPU through
three on-chip registers that may be independently accessed by both the master and the 8292 (UPI-41A).
.Figure 6 shows this Register Interface. Also refer to
Figure 12.

A

t..

r--lA-r--

-'!

!'

~

~

r- !----1\

-

-5---..
a:

a:

"'Clr----"'
hi CI F='\ ...~

CPU

1-"-1 U

I'--

CS AO

a
a
a
a
1

a
1
a
1
X

'--

AO
CS.
RD
WR

'-

I STATUS I
I DBBIN I UPI-41A
I DBBOUT I
231324-48

RD

WR

REGISTER

a
a
1
1
X

1
1
a
a
X

READDBBOUT
READ STATUS
WRITE DBBIN (DATA)
WRITE DBBIN (COMMAND)
NO ACTION

Figure 6. UPI-41A Registers

3-39

Ap·66

a. 8293 Mode 2

b. 8293 Mode 3
+5

MOOE2
OPTA

ATNO

+5

im:

OPT.

NOA~~--------------~

NOAC*

NRFO ~----------------I-l

NRFD*

DiY

DiD,

T/1I1
IFC~--'-----------~

IFC*

..........!..I

SYC ~~+-----------

, REN ~++------------I--I

01°2
REN*

01°3
SRa*

ATN*

EOI*

0106*

0107*

0108*

231324-7

231324-6

Figure 7

Although it is not a common occurrence, the GPIB
specification allows the Controller to set up a data
transfer between two devices and not directly participate in the exchange. The controller must know when
to go active again and regain control. The chip set accomplishes this through use of the "Continuous Acceptor Handshake cycling mode" and the ability to detect
EOI or EOS at the end of the transfer. See XFER in the
Software Driver Outline below.

8291/2/3 Chip Set
Figure 8 shows the four chips interconnected with the
special logic explicitly shown.
The 8291 acts only as the mechanism to put commands
and addresses on the bus while the 8292 is asserting
ATN. The 8291 is tricked into believing that the ATN
line is not asserted by the ATN2 output of the ATN
transceiver and is placed in Talk-only mode by the
CPU. The 8291 then acts as though it is sending data,
when in reality it is sending addresses and/or commands. When the 8292 deasserts ATN, the CPU software must place the 8291 in Talk-only, Listen-only or
Idle based on the implicit knowledge of how the controller is going, to participate in the data transfer. In
other words, the 8291 does not respond directly to addresses or commands that it sends on the bus on behalf
of the Controller. The user software, through the use of
Listen-only or Talk-only, makes the 8291 behave as
though it were addressed.

If the 8292 is not the System Controller as determined
by the signal on its SYC pin, then it must be able to
respond to an IFC within 100 JLsec. This is accomplished by the cross-coupled NORs in ~e 7a which
deassert the 8293's internal version of CIC (Not Controller-in-Charge). This condition is latched until the
8292's firmware has received the IFCL (interface clear
received latch) signal by testing the IFCL input. The
firmware then sets its signals to reflect the inactive condition and clears the 8293's latch.

3-40

.

/

inter

Ap·66

+5

MOOE 3

ATNO
Ji!C[

OAV

DiW

T/ftl

T/Rl

MOr.lI

Imrl

-~
V

~

~

Hr-

l5I02

iim

He-

EOI

ffi03

T/ft2

Di"04
He-

i5i05

iFC

OAV*

01
01

~e-

8291

OPTA
OPTB

01

01
01 05*

Hr0106

NRFO

He0107

fmAC

01 06*
01

Rr0108

~r-DI 08*

EOI
ATN
ATN

,SRQ

MODE 2

n

NDAC

DAY

~

NRFD

SIR

T/Rl
IFC
SYC
REN

8292

IFC

V

SYC
REN

I

SRQ

SAO

ATNl

ATNI

EOi2

ATN
EOl2
ATNO

t

T'C

~
SI"

TIC

~
Td-SR

Ii

COUNT

=L>H=
SR

T/R2

IFCL

WC[

CLTH
CIC

CLTH
CIC

OPTB

NDAC*
NRFO*
IFC*
REN*
SRO*
ATN*

~JT

EOi

A'ffm

OPTA

EOI*

T C

~
231324-8

Figure 8. Talker/Listener/Controller

3-41

inter

AP-66

In order for the 8292 to conduct a Parallel Poll the
8291 must be able to capture the PP response on the
010 lines. The only way to do this is to fool the 8291
by putting it into Listen-only mode and generating a
DAV condition. However, the bus spec does not allow
a DAV during Parallel Poll, so the back-to-back 3-state
buffers (see Figure 7b) in the 8293 isolate the bus and
allow the 8292 to generate a local DAV for this purpose. Note that the 8291. cannot assert a Parallel Poll
response. When the 8292 is not the controller-in-charge
the 8291 may respond to PPs and the 8293 guarantees
that the DIO drivers are in "open collector" mode
through the OR gate (Figure 7b).

Figure 9 shows the card's block diagram. The
ZT7488/18 plugs into the STD bus, a 56 pin 8 bit microprocessor oriented bus. An 8085 CPU card is also
available on the STD bus and will be used to execute
the driver software.

ZT7488/18 GPIB Controller

NDAC is connected to COUNT on the 8292 to allow
byte counting on data transfers. The example driver
software will not use this feature, as the software is
simpler and faster if an internal 8085 register is used for
counting in software.

Ziatech's GPIB Controller, the ZT7488/18 will be used
as the controller hardware in this Application Note.
The controller consists of an 8291, 8292, an 8 bit input
.port and TTL logic equivalent to that shown in Figure 8.

DATA BUS
DO·07

ADDRESS

AQ.A2

=u
Lo--

WT'
SVS RESET'

129'

BUFFERS

10 EXp·

~
1'-....... r---

3-STATE

~

~~

CARD
SELECT
DECODER

SELECT
o--c DECODER

ADDRESS

AS·A7

"---ADDRESS

A3 ....

PORT

INTERFACE

-

fLo--

r--

LOGIC

-

--Y
' - - c-

DMA
CONNEC TOR

""---

-r-

8292

BUFFERS

IORO-

J2

-

-

-~

-

.-L

~

CLOCK-

RD'

The 8291 uses I/O Ports 60H to 67H and the 8292 uses
I/O Ports 68H and 69H. The five interrupt lines are
connected to a three-state buffer at I/O Port 6FH to
facilitate polling operation. This is required for the
TCI, as it cannot be read internally in the 8292. The
other three 8229 lines (SPI, IBF, OBF) and the 8291's
INT line are also connected to minimize the number of
I/O reads necessary to poll the devices.

INTERRUPT
PORT

II
i-'

r--

TRANSCEIYERS

r;:::

J,

BPI B

co NNECTOR

;=...
""--

231324-9
'INDICATES ACTIVE LOW LOGIC

Figure 9. ZT7488/18 GPIB Controller

3-42

inter

AP-66

READ REGISTERS

PORT #

WRITE REGISTERS

'I0-17---'-1-01-6-.1-0-15-.1-0-14-;1.--01-3-;1-0-12----r1-0-11--,-O-10---, 6H I 0071 0061 005 1 0041 003 1 002 1 001 I 000 1
DATA IN

DATA OUT

I CPT 1 APT I GET 1 END 1 DEC 1 ERR 1 BO

BI

61 H I CPT 1 APT I GET 1 END I DEC 1 ERR 1 BO 1 BI

1

INTERRUPT MASK 1

INTERRUPT STATUS 1
liNT ISPAsl LLO 1REM ISPAsclLLoclREMclAoscl 62H
INTERRUPT STATUS 2
I S8 ISRosl S6 I S5 I

S4

INTERRUPT MASK 2

1 S3 1 S2

63H

S1

SERIAL POLL STATUS

S8 1 rsv 1 S6 1 S5 1 S4 1 S3 1 S2 1 S1
SERIAL POLL MODE

I ton lion 1 EOIILPASI TPAS I LA I TA IMJMNI 64H 1 TO 1 LO 1 0 1 0 I 0 1 0
ADDRESS MODE
ADDRESS STATUS

I

IAOM11AOMOI

ICPT71 CPT61CPT51 CPT41 CPT3 I CPT21 CPT1 I CPTO I 65H ICNT21CNT11 CNTO ICOM41 COM31COM21COM11COMOI
COMMAND PASS THROUGH

AUXMODE

x

I OTO I OLO IA05-01 A04-0 IA03-0IA02-0IA01-01

x

IOT1 IOL1 IA05-1IA04-1IA03-1IA02-1IA01-11

ADDRESS 0/1

ADDRESS 0
ADDRESS 1

EOS

Figure 10_ 8291 Registers

1

r--At
8,
AI

n

RD

- -----'="--------------------------,
O,tt-

iOif

B2~O~--~~-~-----~---------~

A3~03

13
::

WA

MEMw

mw

°4tt+M--=.::.---I-~----_I_1r_--------_+__,

-~

T_
RESET'-----'---Irl++i----t-t-t-...,V.:>o----I+-----------,
IO/M~ -----'

IN~.::
I~A~1===~~$$======~~~==~=====t~~------_l_t_l-__.

l

07.00_"

m
~

1J ~l~~ RST RD WR

RST RD W RIGjg~~~

- . . D7·DO

INTI----II

--qCS

r'

HOLOHLDAeLK

L..,

DACKD

>-----<

DROO -

8257·5

~
~~~A
I~~
CLK

ill .. ~
T9:

-

DACK

OREO

8291

I~ -~

AD

=~~
CS

~:~~rr

2142

f--

CS

~~N

~~=~

07-00
COUNT 8292

I;-

~ ~~~2
~

~,:; V'- -

CLK

~:tl

SROII~~~~~~~~~~;SRO
,~~

hR'ii""iR

IBFt

Tel

~~~
~

=r
I

8259-5:11>

~ :i:~

I

~ ~gH

IrsvcT

W

--vt

21.2
CS

AO-

(

..

~

..
c~

:c c
:.:....._-=-=----l

AtS-A:::.O_ _ _ _ _ _ _---':.:.:.:.::'--'.:-=-_ _ _ _---'_ _ _ _ _ _ _ _ _ _ _ _

231324-10

Figure 11. DMA/lnterrupt GPIB Controller Block Diagram
3-43

AP~66

,The application example will not use OMA or interrupts; however, the Figure 11 block diagram includes
these features for completeness. ,

ister. Note the two letter mnemonics to be used in later
discussions. The CPU must not write into the '8292
while IBF (Input Buffer Full) is a one, as information
will be lost.

The 8257-5 OMA chip can be used to transfer data
between the RAM and the 8291 Talker/Listener. This
mode allows Ii faster data rate on the GPIB and typically will depend on the 8291's EOS or EO! detection to
terminate the transfer. The 8259-5 interrupt controller
is used to vector the five possible interrupts for rapid
software handling of the various conditions.

Direct Commands
Both the Interrupt Mask (1M) and the Error Mask
(EM) register may be directly written with the LSB of
the address bus (AO) a "0". The firmware uses the MSB
of the data written to differentiate between 1M and EM.

8292 COMMAND DESCRIPTION

LOAD INTERRUPT MASK

This section discusses each command in detail and relates them to a particular GPIB activity. Recall that
although the 8041A has only two read registers and one
write register, through the magic of on-chip firmware
the 8292 appears to have six ,read registers and five
write registers. These are listed in Figure 12. Please see
the 8292 data sheet for detailed definitions of each reg-

This command loads the Interrupt Mask with 07-00.
Note that, D7 must be a "1" and that interrupts are
enabled by a corresponding "1" bit in this register. IFC
interrupt cannot be masked off; however, when the
8292 is the System Controller, sending an ABORT
command will not cause an IFC interrupt.

READ FROM 8292
PORT #
WRITE TO 8292
INTERRUPT STATUS
COMMAND FIELD
C
OBF
69H 11 I
I SYC IERRI SRO lEVi X IIFCR I IBF
lop I C I C I C
D7
Do
ERROR FLAG·
INTERRUPT MASK
X IUSERI X I X I TOUTs I TOUT2I TOUT1I 6SH 11 I SP1 1 TCI ISYCIOBFII IBFI I 0 I SRO I
X
D7
Do
CONTROLLER STATUS·
ERROR MASK
ICSBSI CA I X I X ISYCSI IFC I REN I SRO I, 6SH 101 0 IUSERI o I 0 I TOUT41 TOUTsl TOUT 11
EVENT COUNTER·
GPIB (BUS) STATUS·
6SH I DI D
D I D I D I D I D
D
I REN IDAVI EOI I X I SYC I IFC I ANTI I SRO
EVENT COUNTER STATUS·
TIMEOUT"
D
6SH I DI D I D I D I D I D
D
D
D
D I D IDI D I D I D
TIME OUT STATUS·
D
D
6SH ·Note: These registers are accessed by a special
utility command.

Figure 12.8292 Registers

3-44

infef

Ap·66

When the 8292 has completed the command, IBF will
become a "0" and will cause an interrupt if masked on.

LOAD ERROR MASK

This command loads the Error Mask with D7-DO.
Note that D7 must be a zero and that interrupts are
enabled by a corresponding "I" bit in this register.

WTOUT-Write to Time Out Register
(Command = OEIH)
The byte written following this command will be used
to determine the number of increments used for the
time out functions. Because the register is 8 bits, the
maximum time out is 256 time increments. This is
probably enough for most instruments on the GPIB but
is not enough for a manually stepped operation using a
GPIB logic analyzer like Ziatech's ZT488. Also, the
488 Standard does not set a lower limit on how long a
device may take to do each action. Therefore, any use
of a time out must be able to be overridden (this is a
good general design rule for service and debugging considerations).

Utility Commands
These commands are used to read or write the 8292
registers that are not directly accessible. All utility
commands are written with AO = 1, D7 = D6 = D5
= I, D4 = O. D3-DO specify the particular command.
For writing into registers the general sequence is:
1) wait for IBF = 0 in Interrupt Status Register
2) write the appropriate command to the 8292,
3) write the desired register value to the 8292 with AO
= 1 with no other writes intervening,
4) wait for indication of completion from 8292 (lBF =
0).

The time out function is implemented in the 8292's
firmware and will not be an accurate time. The counter
counts backwards to zero from its initial value. The
function may be enabled/disabled by a bit in the Error
mask register. When the command is complete IBF will
be set to a "0" and will cause an interrupt if masked on.

For reading a register the general sequence is:
1) wait for IBF = 0 in Interrupt Status Register
2) write the appropriate command to the 8292
3) wait for a TCI (Task Complete Interrupt)
4) Read the value of the accessed register from the 8292
with AO = O.

REVC-Read Event Counter Status
(Command = OE3H)
This command transfers the content of the Event
Counter to the DBBOUT register. The firmware then
sets TCI = 1 and will cause an interrupt if masked on.
The CPU may then read the value from the 8292 with
AO = O.

WEVC-Write to Event Counter
(Command = OE2H)
The byte written following this command will be loaded into the event counter register and event counter
status for byte counting. The internal counter is incremented on a high to low transition of the COUNT (Tl)
input. In this application example NDAC is connected
to count. The counter is an 8 bit register and therefore
can count up to 256 bytes (writing 0 to the EC implies a
count of 256). If longer blocks are desired, the main
CPU must handle the interrupts every 256 counts and
carefully observe the timing constraints.

RINM-Read Interrupt Mask Register
(Command = OE5H)
This command transfers the content of the Interrupt
Mask register to the DBBOUT register. The firmware
sets TCI = 1 and will cause an interrupt if masked on,
The CPU may then read the value.

RERM-Read Error Mask Register
(Command = OEAH)

Because the counter has a frequency range from 0 to
133 kHz when using a 6 MHz crystal, this feature may
not be usable with all devices on the GPIB. The 8291
can easily transfer data at rates up to 250 kHz and even
faster with some tuning of the system. There is also a
500 ns minimum high time requirement for COUNT
which can potentially be violated by the 8291 in continuous acceptor handshake mode (i.e., TNDDVI +
TDVND2 - C = 350 + 350 = 700 max). When
cable delays are taken into consideration, this problem
will probably never occur.

This command transfers the content of the Error Mask
register to the DBBOUT register. The firmware sets
TCI = 1 and will cause an interrupt if masked on. The
CPU may then read the value.

RCST-Read Controller Status Register
(Command = OE6H)

3-45

Ap·66

This command transfers the content of the Controller
Status register to the DBBOUT register. The firmware
sets TCI = I and will cause an interrupt if masked on.
The CPU may then read the value.

Operation Commands. It is not meant to replace the
complete controller state diagram in the IEEE Standard.

RST-Reset (Command
RTOUT-Read Time Out Status Register
(Command = OE9H)
This command transfers the content of the Time Out
Status register to the DBBOUT register. The firmware
sets TCI = I and will cause an interrupt if masked on.
The CPU may then read the value.
If this register is read while a time-out function is in
process, the value will be the time remaining before
time-out occurs. If it is read after a time-out, it will be
zero. If it is read when no time-out is in process, it will
be the last value reached when the previous timing occurred.

RBST-Read Bus Status Register
(Command = OE7H)
This command causes the firmware to read the GPIB
management lines, DAV and the SYC pin and place a
copy in DBBOUT. TCI is set to "I" and will cause an
interrupt if masked on. The CPU may read the value.

=

OF2H)

This command has the same effect as an external reset
applied to the chip's pin #4. The 8292's actions are:
I) All outputs go to their electrical high state. This
means that SPI, TCI, OBFI, IBFI, .CLTH will be
TRUE and all other GPIB signals will be FALSE.
2) The 8292's firmware will cause the above mentioned
five signals to go FALSE after approximately 17.5
f.Ls (at 6 MHz).
3) These registers will be cleared: Interrupt Status, Interrupt Mask, Error Mask, Time Out, Event Counter, Error Flag.
4) If the 8292 is the System Controller (SYC is TRUE),
then IFC will be sent TRUE for approximately
100 f.LS and the Controller function will end up in
charge of the bus. If the 8292 is not the System Controller then it will end up in an Idle state.
5) TCI will not be set.

RERF-Read Error Flag Register
(Command = OE4H)
RST.

SYC

This command transfers the content of the Error Flag
register to the DB BOUT register. The firmware sets
TCI = I and will cause an interrupt if masked on. The
CPU may then read the value.
This register is also placed in DB BOUT by an lACK
command if ERR remains set. TCI is set to "I" in this
case also.

r---------~----~

I
IABO~~T. ~YC - - - . .

lACK-Interrupt Acknowledge
(Command = Al A2 A3 A4 1 AS 1 I)

I

L ____

I
I

LOCAL

~Y!!..E~0!:IT.R2!:..L~ _ _ _ _

I

-.J

231324-11

This command is used to acknowledge any combinations of the five SPI interrupts (AI-AS): SYC, ERR,
SRQ, EV, and IFCR. Each bit AI-AS is an individual
acknowledgement to the corresponding bit in the Interrupt Status Register. The command clears SPI but it
will be set again if all of the pending interrupts were not
acknow ledged.

Figure 13.8292 Command Flowchart

RSTI-Reset Interrupts (Command

=

OF3)

This command clears all pending interrupts and error
flags. The 8292 will stop waiting for actions to occur
(e.g., waiting for ATN to go FALSE in a TCNTR command or waiting for the proper handshake state in a
TCSY command). TCI will not be set.

If A2 (ERR) is "I", the Error Flag register is placed in
DBBOUT and TCI is set. The CPU may then read the
Error Flag without issuing an RERF command.

ABORT-Abort all operations and Clear Interface
(Command = OF9H)

Operation Commands

If the 8292 is not the System Controller this command
acts like a NOP and flags a USER ERROR in the Error Flag Register. No TCI will occur.

The following diagram (Figure 13) is an attempt to
show the interrelationships among the various 8292
3-46

Ap·66

If the 8292 is the system Controller then IFC is set
TRUE for approximately 100 J.Ls and the 8292 becomes
the Controller-in-Charge and asserts ATN. TCI will be
set, only if the 8292 was NOT the CIC.

sets ATN FALSE and TCI TRUE. This command is
used as part of the Send, Receive, Transfer and Serial
Poll System commands (see next section) to allow the
addressed talker to send data/status.

STCNI-Start Counter Interrupts
(Command = OFEH)
Enables the EV Counter Interrupt. TCI will not be set.
Note that the counter must be enabled by a OSEC command.

If the data transfer does not start within the specified
Time-Out, the 8292 sets TOUT2 TRUE in the Error
Flag Register and sets SPI (if enabled). The controller
continues waiting for a new command. The CPU must
decide to wait longer or to regain control and take correcti ve action.

SPCNI-Stop Counter Interrupts
(Command = OFOH)

GSEC-Go To Standby and Enable Counting
(Command = OF4H)

The 8292 will not generate an EV interrupt when the
counter reaches o. Note that the counter will continue
counting. TCI will not be set.

This command does the same things as GTSB but also
initializes the event counter to the value previously
stored in the Event Counter Register (default value is
256) and enables the counter. One may wire the count
input to NDAC to count bytes. When the counter
reaches zero, it sets EV (and SPI if enabled) in Interrupt Status and will set EV every 256 bytes thereafter.
Note that there is a potential loss of count information
if the CPU does not respond to the EV/SPI before another 256 bytes have been transferred. TCI will be set
at the end of the command.

SREM-Set Interface to Remote Control
(Command = OF8H)
If the 8292 is the System Controller, it will set REN
and TCI TRUE. Otherwise it only sets the User Error
Flag.
SLOC-Set Interface to Local Mode
(Command = OF7H)

TCSY-Take Control Synchronously
(Command = OFDH)

If the 8292 is the System Controller, it will set REN
FALSE and TCI TRUE. Otherwise, it only sets the
User Error Flag.

If the 8292 is not in Standby, it treats this command as
a Nap and does not set TCI. Otherwise, it waits for the
proper handshake state and sets ATN TRUE. The 8292
will set TOUT3 if the handshake never assumes the
correct state and will remain in this command until the
handshake is proper or a RSTI command is issued. If
the 8292 successfully takes control, it sets TCI TRUE.

EXPP-Execute Parallel Poll
(Command = OF5H)
If not Controller-in-Charge, the 8292 will treat this as a
Nap and does not set TCI. If it is the Controller-inCharge then it sets lOY (EO! & ATN) TRUE and
generates a local DAV pulse (that never reaches the
GPIB because of gates in the 8293). If the 8291 is configured as a listener, it will capture the Parallel Poll
Response byte in its data register. TCI is not generated,
the CPU must detect the BI (Byte In) from the 8291.
The 8292 will be ready to accept another command
before the BI occurs; therefore the 8291 's BI serves as a
task complete indication.
GTSB-Oo To Standby (Command = OF6H)
If the 82~2 is not the Controller-in-Charge, it will treat
this command as a Nap and does not set TCI TRUE.
Otherwise, it goes to Controller Standby State (CSBS),

This is the normal way to regain control at the end of a
Send, Receive, Transfer or Serial Poll System Command. If TCSY is not successful, then the controller
must try TCAS (see warning below).
TCAS-Take Control Asynchronously
(Command = OFCH)
.If the 8292 is not in Standby, it treats this command as
a Nap and does not set TCI. Otherwise, it arbitrarily
sets ATN TRUE and ECI TRUE. Note that this action
may cause devices on the bus to lose a data byte or
cause them to interpret a data byte as a command byte.
Both Actions can result in anomalous behavior. TCAS
should be used only in emergencies. If TCAS fails, then
the System Controller will have to issue an ABORT to
clean things up.

3-47

inter

AP-66

GIDL-Go to Idle (Command = OFIH)

In order to use polling with the 8292 one must enable
TCI but not connect the pin to. the CPU's interrupt pin.
TCI must be readable by some means. In this application example it is connected to bit 1 port 6FH on the
ZT7488/l8. In addition, the other three 8292 interrupt
lines and the 8291 interrupt are also on that port (SPIBit 2, IBFI-Bit 4, OBFI-Bit 3, 8291 INT-Bit 0).

If the 8292 is not the Controller in Charge and Active,
then it treats this command as a NOP and does not set
TCI. Otherwise, it sets ATN FALSE, becomes Not
Controller in Charge, and sets TCI TRUE. This commarid is used as part of the Pass Control System Command.

These drivers assume that only primary addresses will
be used on the GPIB. To use secondary addresses, one
must modify the test for valid talk/listen addresses
(range macro) to include secondaries.

TCNTR-Take (Receive) Control
(Command = OFAR)
If the 8292 is not Idle, then it treats this command as a

NOP and does not set TCI. Otherwise, it waits for the
current Controller-in-Charge to set ATN FALSE. If
this does not occur within the specified Time Out, the
8292 sets TOUTI in the Error Flag Register and sets
SPI (if enabled). It will not proceed until ATN goes
false or it receives an RSTI command. Note that the
Controller in Charge must previously have sent this
controller (via the 829l's command pass through register) a Pass Control message. When ATN goes FALSE,
the 8292 sets CIC, ATN and TCI TRUE and becomes
Active.

INIT

INITIALIZATION

Talker/Listener
SEND SEND DATA
RECV
RECEIVE DATA
XFER
TRANSFER DATA
Controller
TRIG
DCLR
SPOL
PPEN
PPDS
PPUN
PPOL
PCTL
RCTL
SRQD

SOFTWARE DRIVER OUTLINE
The set of system commands discussed below is shown
in Figure 14. These commands are implemented in software routines executed by the main CPU.
The following section assumes that the Controller is the
, System Controller and will not Pass Control. This is
valid assumption for 99 + % of all controllers. It also
assumes that no DMA or Interrupts will be used. SYC
(System Control Input) should not be changed after
Power-on in any system-it adds unnecessary complexity to the CPU's software.

a

GROUP EXECUTE TRIGGER
DEVICE CLEAR
SERIAL POLL
PARALLEL POLL ENABLE
PARALLEL POLL DISABLE
PARALLEL POLL UNCONFIGURE
PARALLEL POLL
PASS CONTROL
RECEIVE CONTROL
SERVICE REQUESTED

System Controller
REME .REMOTE ENABLE
LOCL
LOCAL
IFCL
ABORTIINTERFACE CLEAR

Figure 14. Software Drive Routines

3-48

AP-66

Set internal counter to 3 MHz to match the clock input
coming from the 8085 by writing 23H to Port 65H.
High speed mode for the handshakes will not be used
here even though the hardware uses three-state drivers.

Initialization
8292-Comes up in Controller Active State when SYC
is TRUE. The only initialization needed is to enable the
TCI interrupt mask. This is done by writing OAOH to
Port 68H.

No interrupts will be enabled now. Each routine will
enable the ones it needs for ease of polling operation.
The INT bit may be read through Port 6PH. Clear
both interrupt mask registers.

8291-Disable both the major and minor addresses because the 8291 will never see the 8292's commands/addresses (refer to earlier hardware discussion). This is
done by writing 60H and OEOH to Port 66H.

Release the chip's initialization state by writing 0 to
Port 65H.

Set Address Mode to Talk-only by writing 80H to Port
64H.

INIT:
Enable-8292
Enable TCI
Enable-8291
Disable major address
Disable minor address
ton
Clock frequency
All interrupts off
Immediate execute pon

;Set up In. pins for Port 6FH
;Task complete must be on
;In controller usage, the 8291
;1s set to talk only and/or listen only
;Talk only is our rest state
;3 MHz in this ap note example
;Releases 8291 from init. state

Talker/Listener Routines
SEND DATA
SEND 

  

This system command sends data from the CPU to one
or more devices. The data is usually a string of ASCII
characters, but may be binary or other forms as well.
The data is device-specific.

This routine assumes a non-null listener list in that it
always sends Univeral Unlisten. If it is desired to send
data to the listeners previously addressed, one could
add a check for a null list and not send UNL. Count
must be 255 or less due to an 8 bit register. This routine
also always uses an EOS character to terminate the
string output; this could easily be eliminated and rely
on the count. Items in brackets ( ) are optional and will
not be included in the actual code in Appendix A.

My Talk Address (MTA) must be output to satisfy the
GPIB requirement of only one talker at a time (any
other talker will stop when MTA goes out). The MTA
is not needed as far as the 8291 is concerned-it will be
put into talk-only mode (ton).

3-49

inter

AP-66

SEND:

Output-to-829l MTA, UNL
Put EOS into 8291
While .20H s:: listener s:: 3EH
output-to-829l listener
Increment listen list pointer
Output-to-8292 GTSB
Enable-829l
Output EOI on EOS sent
If count < > 0 then.
While not (end or count
0)
(could check tout 2 here)
Output-to-829l data
Increment data buffer pointer·
Decrement count
Output-to-8292 TCSY
(If tout3 then take control async)
Enable 8291
No output EOI on EOS sent
Return

;We will talk, nobody listen
;End of string compare character
;GPIB listen addresses are
;"space" thru ">" ASCII
;Address all listeners
;8292 stops asserting ATN, go to standby
;Send EOI along with EOS character
;Wait for EOS or end of count
;Optionally check for stuck bus-tout 2
;Output all data, one byte at a time
;8085 CREG will count for us
;8292 asserts ATN, take control sync.
;If unable to take control sync.
;Restore 8291 to standard condition

231324-12

Figure 15. Flowchart for Receive Ending Conditions

3-50

inter

AP-66

CONTROLLER
8291.8292

LSTN
"I"

CTLR

DEVICE

TALK
"a"

TALK
"R"

DEVICE

LSTN

TALK

"+"

"K"

DEVICE

TALK
"/I"

231324-13

Figure 16. SEND to "1", "2", ">"; "ABCO"; EOS

= "0"

RECEIVE DATA

RECV    
This system command is used to input data from a
device. The data is typically a string of ASCII characters.

totally regular to facilitate analysis by a GPIB logic
analyzer like the Ziatech ZT488. Otherwise, the bus
would appear to have no listener even though the 8291
will be listening.

This routine is the dual of SEND. It assumes a new
. talker will be specified, a count of less than 257, and an
EOS character to terminate the input. EOI received
will also terminate the input. Figure 15 shows the flow
chart for the RECV ending conditions. My Listen Address (MLA) is sent to keep the GrIB transactions

Note that although the count may go to zero before the
transmission ends, the talker will probably be left in a
strange state and may have to be cleared by the controller. The count ending of RECV is therefore used as an
error condition in most situations.

3-51

intJ

AP-66

RECV:

Put EOS into 8291
If 40H ::;: talker ::;: 5EH then
Output-to-829l talker
Increment talker pointer
Output-to-829l UNL, MLA
Enable-829l
Holdoff on end
End on EOS received
lon, reset ton
Immediate execute pon
Output-to-8292 GTSB
While not (end or count
0
(or tout2))
Input-from-829l data
Increment data buffer pointer
Decrement count
(If count = 0 then error)
Output-to-8292 TCSY
(If Tout3 then take control a~ync.)
Enable-829l
No holdoff on end
~o end on EOS received
ton, reset Ion
Finish handshake
Immediate execute pon
Return error-indicator

;End of string compare 'character
;GPIB talk addresses are
;"@" thru "II" ASCII
;Do this for consistency's sake
;Everyone except us stop listening
;Stop when EOS character is
;Detected by 8291
;Listen only (no talk)
;8292 stops asserting ATN, go to standby
;wait for EOS or EOI or end of count
;optionally check for stuck bus-tout2
;input data, one byte at a time
;Use 8085 C register as counter
;Count should not occur before end
;8292 asserts ATN take control
;If unable to take control sync.
;Put 8291 back as needed for
;Controller activity and
;Clear holdoff due to end
;Complete holdoff due to end, if any
;Needed to reset Ion

CONTROLLER
1211,'212

TALK

LSTN

"A"

"I"

CTL.

TALK
"A"

DEVICE
LSTN
"1"

TALK

TALK

"Q"

"0"

TALK

"R"

LSTN
"2"

DEVICE

TALK

"11"

DEVICE

DEVICE
LSTN

">"

LSTN
">"'

TALK

TALK

"Nt

231324-15

"fI"

231324-14

Figure 17" RECV from "R"j EOS = ODH

Figure 18. XFER from" II" to "1", "2", "+"j
EOS = ODH
3"52

inter

AP-66

This is accomplished through the use of the 8291's continuous acceptor handshake mode while in listen-only.

TRANSFER DATA

XFER  
This routine assumes a device list that has the ASCII
talker address as the first byte and the string (one or
more) or ASCII listener addresses following. The EOS
character or an EOI will cause the controller to take
take control synchronously and thereby terminate the
transfer.

This system command is used to transfer data from a
talker to one or more listeners where the controller
does not participate in the transfer of the ASCII data.

XFER:

Output-to-8291: Talker, UNL
While 20H :::; listen :::; 3EH
Output-to-8291: Listener
Increment listen list pointer
Enable-8291
lon, no ton
Continuous AH mode
End on EOS received
Immediate execute PON
Put EOS into 8291
Output-to-8292: GTSB
Upon end (or tout2) then
, Take control synchronously
Enable-8291
Finish handshake
Not continuous AH mode
Not END on EOS received
ton
Immediate execute pon
Return

;Send talk address and unlisten
;Send listen address
;Controller is pseudo listener
;Handshake but don't capture data
;Capture EOS as well as EOI
;Initialize the 8291
;Set up EOS character
;Go to standby
;8292 waits for EOS or EOI and then
;Regains control
;Go to Ready for Data

Controller
GROUP EXECUTE TRIGGER

TRIG 
This system command causes a group execute trigger
(GET) to be sent to all devices on the listener list. The
intended use is to synchronize a number of instruments.

TRIG:

Output-to-8291 UNL
While 20H :::; listener :::; 3EH
Output-to-8291 Listener
Increment listen list pointer
Output-to-8291 GET
Return

;Everybody stop listening
;Check for valid listen address
;Address each listener
;Terminate on any non-valid, character
;Issue group execute trigger

3-53

inter

AP-66

CONTROLLER

CONTROLLER
8291.8292

LSTN

LSTN

TALK
"A"

"'"

EfRl
....

TALK

"A"

~

TALK
"Q"

DEVICE

;~,'----------1
LSTN
"2"

TALK
"R"

DEVICE
LSTN

DEVICE

DEVICE
LSTN

TALK
"K"

TALK
"A"

LSTN

TALK

"'>"

"I\."

231324-16

231324-17

Figure 19. TRIG "1", "+"

Figure 20. DCLR "1", "2"

DEVICE CLEAR

DCLR < Listener list>
This system command causes a device clear (SDC) to
be sent to all devices on the listener list. Note that this

is not intended to clear the GPIB interface of the device, .but should clear the device-specific logic.

DCLR:

Output-to-829l UNL
While 20H s: listener s: 3EH
Output-to-829l Listener
Increment listen list pointer
Output-to-829l SDC
Return

;Everybody stop listening
;Check for valid listen address
;Address each listener
;Terminate on any non-valid character
;Selective device clear

SERIAL POLL

SPOL 
This system command sequentially addresses the designated devices and receives one byte of status from each.

The bytes are stored in the buffer in the same order as
the devices appear on the talker list. MLA is output for
completeness.

3-54

AP-66

SPOL:

Output-to-8291 UNL, MLA, SPE

;Unlisten, we listen, serial poll enable
;Only one byte of serial poll
;Status wanted from each talker
;Check for valid transfer
;Address each device to talk
;One at a time

While 40H ::;; talker ::;; 5 EH
Output-to-8291 talker
Increment talker list pointer
Enable-8291
lon, reset ton
Immediate execute pan
Output-to-8292 GTSB
Wait for data in (BIl
Output-to-8292 TCSY
Input-from-8291 data
Increment buffer pointer
Enable 8291
ton, rese~ lon
Immediate execute pan
Output-to-8291 SPD

;Listen only to get status
;This resets ton
;Go to standby
;Serial poll status byte into 8291
;Take control synchronously
;Actually get data from 8291

;Reset lon
;Send serial poll disable after all
devices polled

Return

CONTROLLER
8291,8292
TALK
"A"

LSTN

"'"

4;?-

~,1:!,."'"Cl"'<:;,,,"'J;,"":!."".. '"":·~.:,~.:.m::,~,
i!

TALK
"A"

DEVICE

::-!
•.•7l.
LSTH
"1"

;..

R

;~.

DEVICE

~

v

LSTN
"1"

DEVICE
~:·~:i:

... :kJ·:y t':',·

DEVICE

;: .. ~,:;.;.

~

TALK
"Q"

v~
I·-:i··"]

LSTN
''2"

TALK
"R"

j)
DEVICE

DEVICE

LSTN

V

"."

LSTN

DEVICE

TALK
"K"

DEVICE

LSTN

V

">"

LSTN

231324-18

231324-19

Figure 21. SPOL "Q", "R", "K", "/\"

Figure 22. PPEN "2"; iP3P2P1

= 0111B

PARAI,..LEL POLL ENABLE

PPEN < Listener list>

< Configuration Buffer pointer>

This system command configures one or more devices to respond to Parallel Poll, assuming they implement subset
PPI. The configuration information is stored in a buffer with one byte per device in the same order as
3"55

AP-66

devices appear on the listener list. The configuration byte has the format XXXXIP3P2Pl as defined by the IEEE
Std. P3P2Pl indicates the bit # to be used for a response and I indicates the assertion value. See Sec. 2.9.3.3 of the
Std. for more details.

PPEN:

Output-to-829l UNL
While 20H s;: Listener s;: 3EH
Output-to-829l listener
Output-to-829l PPC, (PPE or data)
Increment listener list pointer
Increment buffer pointer
Return'

;Universal unlisten
;Check for valid listener
;Stop old listener, address new
;Send parallel poll info
;Point to next listener
;One configuration byte per listener

PARALLEL POLL DISABLE

PPDS

This system command disables one or more devices from responding to a Parallel Poll by issuing a Parallel Poll
Disable (PPD). It does not deconfigure the devices.
PPDS:

Output-to-829l UNL
While 20H 'S;: Listener s;: 3EH
Output-to-829l listener
Increment listener list pointer
Output-to-829l PPC, PPD
Return

;Universal.Unlisten
;Check for valid listener
;Address listener
;Disable PP on all listene.rs

CONTROLLER

CONTROLLER

8291.8292

L~~N

~

8291,8292
TALK
"A"

LSTN
"I"

~

TALK

~~!t~

"A"

. :;'., . .

DEVICE

I!..

~¥.,

TALK

LSTH

"Q"

"1"

DEVICE
V

LSTH

TALK

"2"

"ROO

"...
.:: .~: ~

~.".

::~:.~

"...

TALK
''0''

DEVICE
LSTH

TALK

"2"

"R"

DEVICE

. ···'r",:'o/;>t;·j

:.~ >':;':~~1:.~ ~"::.' ~::

LSTN

TALK
"K"

DEVICE

"-

.y;;>
V

LSTH

"-::-"

TALK
"A"

231324-21

231324-20

Figure 23. PPDS "1", ".+", ">"

Figure 24. PPUN
3-56

AP-66

PARALLEL POLL UNCONFIGURE
PPUN

This system .command deconfigures the Parallel Poll response of all devices by issuing a Parallel Poll Unconfigure
message.
PPUN:

Output-to-8291 PPU
Return

;Unconfigure all parallel poll

CONDUCT A PARALLEL POLL
PPOL

This system command causes the controller to conduct
a Parallel Poll on the GPIB for approximately 12.5
!J.sec (at 6 MHz). Note that a parallel poll does not use
the handshake; therefore, to ensure that the device
knows whether or not its positive response was ob-

served by the controller, the CPU should explicitly acknowledge each device by a device-dependent data
string. Otherwise, the response bit will still be set when
the next Parallel Poll occurs. This command returns
one byte of status.

PPOL:

Enable-8291
lon
Immediate execute pon
Output-to-8292 EXPP
Upon BI
Input-from-8291 data
Enable-8291
ton
Immediate execute pon
Return Data (status byte)

;Listen only
;This resets ton
;Execute parallel poll
;When byte is input
;Read it
;Talk only
;This resets lon

PASS CONTROL
PCTL < talker>

to become a normal device and the CPU must handle
all commands passed through, otherwise control cannot be returned (see Receive Control below). The controller will go idle.

This system command allows the controller to relinquish active control of the GPIB to another controller.
Normally some software protocol should already have
informed the controller to expect this, and under what
conditions to return control. The 8291 must be set up
PCTL:

If 40H ::; talker ::; 5EH then
if talker < > MTA then
output-to-8291 talker, TCT
Enable-8291
not ton, not lon
Immediate execute pon
My device address, mode 1
Undefined command pass through
(Parallel Poll Configuration)
Output-to-8292 GIDL
Return

;Cannot pass control to myself
;Take control message to talker
;Set up 8291 as normal device
:Reset ton and lon
:Put device number in Register 6
:Required to receive control
;Optional use of PP
lPut controller in idle

3-57

inter

AP-66

CONTROLLER

CONTROLLER

8211,1212

8291,8292

~
• i'
"r

I~I~

TALK
"A"

0101

TALK

"I'"

"A"

DEVICE

DEVICE

LaTH

TALK

"1"

"0"

0102

"'"

0103

DEVICE

+

LSTN
"2"

DEVICE
LITH

TALK
"R"

DEVICE
TALK
"K"

"+"

"Q"

';t

TALK
"R"

''2''

, TALK

LSTH

DEVICE
LITH

,

LSTN

LSTH

TALK
"K"

"."
',:

DEVICE

DEVICE

LITH

TALK

">-

"1\"

LSTN

LITN

"'"

231324-22

CTLR

">"

TALK
"A"

Figure 25. PPOL
231324-23

RECEIVE CONTROL
Figure 26. PCTL ','cn

RCTL
This system command is used to get control back from
the current controller-in"charge if it has passed control
to this inactive controller. Most GPIB systems do not
use more than one controller and therefore would not
need this routine.

whereby the controller-in-charge sends a data message
to the soon-to-be-active controller. This message should
give the current state of the 'system, why control is be"
ing passed, what to do, and when to pass control back.
Most of these issues are beyond the scope of this Ap
Note.

To make passing and receiving control a manageable
event, the system designer should speCify a protocol

3-58

intJ

AP-66

RCTL:

Upon CPT
If (command=TCT) then
I f TA then
Enable-8291
Disable major device number
ton
-Mask off interrupts
Immediate execute pon
Output-to-8292 TCNTR
Enable-8291
Valid command
Return valid
Else
Enable-8291
Invalid command
Else
Enable-8291
Invalid command
Return invalid

;Wait for command pass through bit in 8291
;If command is take control and
;We are talker addressed
;Controller will use ton and Ion
;Talk only mode
;Take (receive) control
;Release handshake

;Not talker addr. so TCT not for us
;Not TCT, so we don't care

SYSTEM
CONTROLLER

CONTROLLER

8291,8292

8291,8292
LSTN
"I"

fF

CTLR

"

~

LSTN
"!"

~

TALK
"A"

Z

w
II:

DEVICE

t-.

v

DEVICE
LSTN
"1"

"0"

.DEVICE
LSTH
"2"

TALK
"R"

LSTN

TALK

"2"

"R"

TALK
"K"

LSTH

TALK
"A"

LSTN

DEVICE

t-.

DEVICE

.....

LSTN

LSTN
"#"

~~

TALK
"C"

LSTN
"

.

TALK
"K"

"."

DEVICE

v

TALK
"0"

DEVICE

t-.

v

LSTH
"1"

TALK

DEVICE

">"

TALK

"""

231324-25

Figure 28. REME

CONTROLLER

231324-24

Figure 27. RCTL

3·59

AP-66

SERVICE REQUEST

SRQD
This system command is used to detect the occurrence of a Service Request on the GPIB. One or more devices may
assert SRQ simultaneously, and the CPU would normally conduct a Serial Poll after calling this routine to determine
which devices are SRQing.

SRQD:

SRQ then
Output-to-8292 IACK.SRQ
Return SRQ
Else return no SRQ

If

;Test 92 status bit
;Acknowledge it

System Controller
REMOTE ENABLE

REME
This system command asserts the Remote Enable line (REN) on the GPIB. The devices will not go remote until they
are later addressed to listen by some other system command.

REME:

Output-to-8292 SREM
Return

;8292 asserts remote enable line

LOCAL

LOCL
This system command deasserts the REN line on the GPIB. The devices will go local immediately.

LOCL:

Output-to-8292 SLOC
Return

;8292 stops asserting remote

3-60

ena~le

intJ

AP·66

SYSTEM
CONTROLLER

SYSTEM
CONTROLLER

8291,8292
LS1N

"'"

R

LSTN
"I"

TALK
"A"

~

TALK

"A"

g

I~
DEVICE

DEVICE

lSTN

TALK

LSTN

TALK

"1"

"Q"

"1"

"Q"

TALK
"Rn

lSTN

TALK
"K"

LSTN

DEVICE

DEVICE
LSTN
"2"

DEVICE
lSTN
"+"

DEVICE

DEVICE
lSTN

">"

TALK
"A"

"2"

DEVICE
LSTN

TALK
"A"

">"

231324-26

TALK
"A"

231324-27

Figure 29. LOCL

Figure 30. IFCL

INTERFACE CLEARI ABORT

IFCL
This system command asserts the GPID's Interface
Clear (IFC) line for at least 100 microseconds. This
causes all interface logic in all devices to go to a known
state. Note that the device itself mayor may not be

reset, too. Most instruments do totally reset upon IFC.
Some devices may require a DCLR as well as an IFCL
to be completely reset. The (system) controller becomes
Controller-in-Charge.

IFCL:

Output-to-8292 ABORT
Return

;8292 asserts Interface Clear
;For 100 microseconds
The 8291 and 8292 provide sufficient interrupts that
one may return to do other work while waiting for such
things as 8292 Task Completion, 8291 Next Byte In,
8291 Last Byte Out, 8292 Service Request In, etc. The
only difficulty lies in integrating these various interrupt
sources and their matching routines into the overall
system's interrupt structure. This is highly situationspecific and is beyond the scope of this Ap Note.

INTERRUPTS AND DMA
CONSIDERATIONS
The previous sections have discussed in detail how to
use the 8291, 8292, 8293 chip set as a GPID controller
with the software operating in a polling mode and using
programmed transfer of the data. This is the simplest
mode of use, but it ties up the microprocessor for the
duration of a GPID transaction. If system design constraints do not allow this, then either Interrupts and/or
DMA may be used to free up processor cycles.

The strategy to follow is to replace each of the WAIT
routines (see Appendix A) with a return to the main
code and provide for the corresponding interrupt to
bring the control back to the next section of GPID

3-61

AP-66

MAIN CODE

INTERRUPT CODE

GPIB SUBROUTINE

USER:

SEND:

ACTIVATE
SEND ..

=

__

(WAIT 0)
·INT:

~ G~O?

~

(WAIT 0)
___INT: _ _
__--------.
GPIBBO?- -......I - - - - - - = = = - - - - - - - - - - _ ( W A I T 0)
INT:

=

~

_____ =

~

__

GPIBBO?-

..

=..

(WAIT T)

BO~

.____INT: GPIB
GPIB TCI?

ETC.

ETC.

231324-28

Figure 31. GPIB Interrupt and Co-Routine Flow of Control
be found on the GPIB. The Ziatech ZT488 GPIB analyzer is used to single step the bus to facilitate debugging the system. It also serves as a training/familiarization aid for newcomers to the bus.

code. For example WAlTO (Wait for Byte Out of
8291) would be replaced by having the BO interrupt
enabled and storing the (return) address of the next
instruction in a known place. This co-routine structure
will then be activated by a BO interrupt. Figure 31
shows an example of the flow of control.

This example will set up the function generator to output a specific waveform, frequency and amplitude. It
will then tell the counter to measure the frequency and
Request Service (SRQ) when complete. The program
will then read in the data. The assembled source code
will be found at the end of Appendix A.

DMA is also useful in relieving the processor if the
average length of a data buffer is long enough to overcome the extra time used to set up a DMA chip. This
decision will also be a function of a data rate of the
instrument. The best strategy is to use the DMA to
handle only the data buffer transfers on SEND and
RECV and to do all the 'addressing and control just as
shown in the driver descriptions.

ZTI488/18

CONTROLLER

Another major reason for using a DMA chip is to increase the data rate and therefore increase the overall
transaction rate. In this case the limiting factor be, comes the time used to do the addressing and control of
the GPIB using software like that in Appendix A. The
data transmissio'n time becomes insignificant at DMA
speeds unless extremely long buffers are used.

LSTN
"In

CTLR

TALK
"A"

HP 5328A

COUNTER
TALK

lSTN

"'"

Refer to Figure 11 for a typicar DMA and interrupt
based design using the 8291, 8292, 8293. A system like
this can achieve a 250K byte transfer rate while under
DMA control.

"Q"

HP 3325A

FUNCTION
GENERATOR
lSTN
"2"

TALK
"R"

APPLICATION EXAMPLE
ZT488

GPIB ANALYZER

This section will present the code required to operate a
typical GPIB instrument set up as shown in Figure 32.
The HP5328A universal counter and the HP3325 function generator are typical of many GPIB devices; however, there are a wide variety of software protocols to

231324-29

Figure 32. GPIB Example Configuration
3-62

intJ
SEND
LSTN: "2", COUNT:
;SETS UP FUNCTION
;COUNT EQUAL TO #
;EOS CHARACTER IS

AP-66

15, EOS: ODH, DATA: "FU1FR37KHAM2VO (CR)"
GEN. TO 37 KHZ SINE, 2 VOLTS PP
CHAR IN BUFFER
(CR)
ODH
CARRIAGE

=

=

SEND
LSTN: "1", COUNT: 6, EOS: "T" DATA: "PR4G7T"
;SETS UP COUNTER FOR P:INITIALIZE, F4: FREQ CHAN A
G7:0.1 HZ RESOLUTION, T:TRIGGER AND SRQ
;COUNT IS EQUAL TO # CHAR
WAIT FOR SRQ
SPOL TALK: "Q", DATA: STATUS 1
;CLEARS THE SRO_IN THIS EXAMPLE ONLY FREQ CTR ASSERTS SRQ
RECV TALK: "Q", COUNT: 17, EOS: OAH,
DATA: "+
37000.0E+O" (CR) (LF)
;GETS 17 BYTES OF DATA FROM COUNTER
;COUNT IS EXACT BUFFER LENGTH
;DATA SHOWN IS TPYICAL HP5328A READING THAT WOULD BE RECEIVED
The ultimate reference for GPIB questions is the IEEE
Std 488 -1978 which is available from IEEE, 345 East
47th St., New York, NY, 10017. The ultimate reference
for the 8292 is the source listing for it (remember it's a
pre-programmed UPI-4IA) which is available from INSITE, Intel Corp., 3065 Bowers Ave., Santa Clara, CA
95051.

CONCLUSION
This Application Note has shown a structured way to
view the IEEE 488 bus and has given typical code sequences to make the Intel 8291, 8292, and 8293's behave as a controller of the GPIB. There are other ways
to use the chip set, but whatever solution is chosen, it
must be integrated into the overall system software.

3-63

AP-66

APPENDIX A

ISIS-II 8080/8085 MACHO ASSE,",BLER, V3.0
CON'rHOLLER SUBROU'rINES

GPI~

LOC

08J

LINE

SQUllCE STATEMEN'r

$'rI'rLE ('GPIR CON'rROLLER SUBROU'rINES')

2
3
4
5

()PIa CONTROLLER SUBROUTINES

Ii

for intel 8291, 8292 on ZT 748q/IR
Bert Forbes, Ziatech Corporatinn .
2410 Broad Street
San Lui s Ohispo, CA, USA 934~1

1000

7
8
9
18
11
12
13
14
IS

0060

~j ~RT91

General Definitions" Equates
8291 Control Values
ORG

10001l

EQU

;. I'or ZT748S/IS w/8085

,8291 Base Port

18

19 ;
20 DIN
21 DOUT

Reg .0 Data in " Data out
EOU
PRT91+B ; 91 Data in reg
EQU
PRT91 +~ ; 91 Data out req

22
0961
0061
0002
0001
0010
008B
B062

0064
0080
0049
00C0
0001
001i4
0020
0092
0091

0065
0023

23
24
25
26
27
28
29
30

IH'r"l

Req ,
EQU
EQU

BOM

EQU

;
~HTI

~IM

ENDMK
CPT

EOU
EOU
EOU

1 Interrupt 1 Constants
PRT91+1 ; tNT Req 1
PRT91+1 lINT Mask Reg.
~2
; 91 80 I'IITRP Mask
01
; 91 BI INTRP Mask
18H
;91 E"'D INTRP Mask
RAH
; 91 cornman" ,pass thru int hit·

31;

Req 12 Interrupt 2

32 INT2
33
34 ;
35 ADRMD
31i TON
37 LON
38 TLON
39 MODEl
40
41 I
42 ADRST
43 EOIST
44 TA
45 LA
46 I
47 ,
48 AUXMD
49 CLKRT

EQU

PRT91+2

Reg '4 Address ~ode Constants
E(lU
PRT91+4 ; 91 ad"ress mode register .'
EQU
SOH
;91 talk only mode & not listen only
48H
;91 listen only, not ton
EOU
EQU
BeBH
r9l talk' listen only
EQU
9.11
rmode I addressinq for device
Reg 14
EQU
EOU
EOU
EOU

Reg '5
EQU
EOU

(Read)
Address Status Reqister
PRT91+4 ; reg 14
20H
2

1

rlistener active

(Write) A.uxillary Mode Reqlster
PRT91+S r91 ;tuxll1ary mode reqister
23H
;91 3 Mhz clock input

231324-30

3-64

intJ
BOB]
AAAfi
eB8~

A801
8002
808]
BB04
080S
OB0F
OB07
88AO
88Al
83fi5

Ap·66

50 FNHSK
51 SDEOI
~2 AXRA
5] HOHSK
54 HOEND
55 CAHCY
56 EDEOS
57 EOIS
58 VSCMD
59 NVCMD
fi8 AXRB
~1 CPTEN
~2 ,
6] 1
~4 CPTRG
fiS
~fi

B8fi~

,,

896B
0301
AA02
9884
90~B

~0fiB

0869
8069
0018
8892
0~28
00~B

9868
9968
9868
0968

89F8
B8Fl
geF2
B8F]
88F4
90FS
0BF6
09F7
BBFB
08F9
801'A
99FC
99FD
B0FE

]

4
8
AFH
87H
8A8H
AIH

IS

flninsh handshake command
senti EOl wi th next hyte

aux. req A pattern

hold off honrlshake an oil bytes
hal .... off handshake on enti
conti nuous AH eyell nq

end on FoOS received
output EOI on EOS sent
valid command pass throuqh

;91 invalid command pass through
JAux. reg. B pattern
1command pass thru enable

(Reod)
PRT91+5

Reg 17
EQU

EOS
Character Req 1 ster
PRT91+7

8292

CONTROL VALUES

PRT92

EOU

PRT91+8 ; 8292 Base Port

INTMR
INTM

EgU
EQU

PRT92+8 ,92 INTRP '''ask Reg
A/lBH
;TCI

ERRM

TOUT 1
TOUT2
TOUT3
EVREG
TOREG

EOU
EQU
EOU
EOU
EQU
EQU

PRT92+0
31
82
04
PRT92+0
PRT92+9

CMD92

EOU

PRT92+1 ,92 Command Reqister

EVBrT
IBFBT
SROBT

EOU
EOU
EQU
EOU

PRT92 +1 ; 92 Interrupt Status Reg
92
2AH

; Event Counter Bi t
; Input Ruffer Full Bit
;Seq bit

ERFLG
CLRST
BUSST
EVCST
TOST

EQU
EOU
EOU
EOU
EOU

PRT92+0
PRT92+8
PRT92+0
PRT92+8
PRT92+0

192
,92
,92
,92
,92

,

8292

OPERATION COMMANDS

EOU
EOU
EOU
EOU
EOU
EQU
EOU
EOU
EOU
EQU
EOU
EOU
£OU
EOU

0F8H
8FIH
AF2H
BF3H
AF4H

71
72 EOSR

0068
00AO

7-

191
,91
,91
191
,91
191
,91
;91
;91

Address 0/1 reg. constants

90fi7

0068

Reg
EOU

A~

83H
1

'6

8060
80E0

67 ADRAI
fi8 D'rm.l
~9 DTDL2
78
7]
74
75
76
77
78
79
80
81
82
83
B4
BS
86
87
88
89
99
91
92
93
94
95
95
97
9B
99
100
101
102
103
104
US
196
187
108
199
119
111
112
113
114
115
116
117
118
119
128
121
122

0]

EOU
EOU
EOIl
EOU
EOU
EOU
EOU
EOU
EQU
EOU
EOU
EOU

,,
,,
,
,,,
,
,

,
,INTST

,
,,

~PCNI
GIDL
RSET
RSTI
aSEC
EXPP
aTSB
SLOC
SREM
ABORT
TCNTR
TCASY
TCSY
STCNI

,,

Reg
EQU
EOU
EOU

PRT91+fi
6AH
;Disable major talker & 1 istener
AEOH
,Disable minor talker & listener

IBM

8F5H

AF6H
BF7H
9FBH
9F9H
8FAH
eFCH
9FDH
9FEH

t (CS7)

; 92 Error Mask Req

; 92
;92
;92
; 92
,92

'rime Out for Pass Control
Time Out for Standhy
Time Out for Take Control Sync
Event Counter P&eurto Req
Time Out Pseudo Req

Error Flaq Pseurlo Reg
Controller Status Pseudo Reg
aPIB (Bus) Status Pseudo Reg
Event Counter Status Pseudo Reg
Time Out Status Pseudo Req

;Stop Counter Interrupts
;Go to idle
;Reset
;Reset Interrupts
;Goto standby, enable counting
;Execute parallel poll
;Goto standby
;Set local mode
;Set interface to remote
;Abort all operation, clear interface
;Take control (Receive control)
;Take control asyncronously
;Take control syncronously
;Start counter interrupts

231324-31

3-65

inter
A8EI
80E2
88E3
80E4
80E5
80E6
80E7
A8E9
88EA
8888

Ap·66

123
124
125
126
127
128
129
130
131
132
133
IH
135

,
WOUT
WEVC
REVC
RERF
RINM
RCST.
R8ST
RTOUT
RERM
lACK

13~

8292

UTILITY COMMANDS

EQU

OEIH
8E2H
0E3H
8E4H
0E5H
0E6H
0E7H
0E9H
0EAH
8BH

EOU
EOU
EQU
EOU
EOU
EOU

EQU

EQU
EOU

;Wr j te to timeout req
;Write to event counter
;Read event counter status
;Read error flag reg
; Read interrupt mask reg
,Read controller status req
;Read GPtB BUs' status reg

;Read'timeout status reg
;Read error mask reg

; Interrupt Acknowledqe

137

BAAl
B041
B021

0S3F
3908
B004
B018
B019

08B5
B"10
BA60

0U5
0809

138
139
148
141
142
143
144
145
146
147
148
149
150
151
152
153
IS4
ISS
156
157
158
159

PORT F BIT ASSIGNMENTS

,
PRTF
TCIF
SPIF
OBFF
18FF
SOF

,
MM·
MTA
I'lLA
UNL
GET
SOC
SPE
SPD
PPC
1~0 PPD
HI PPE
H2 PPU
163 TCT
164
1~5

EQU

PRT91+AFH

EQU

82M

,ZT14RR port fiF 'for interrupts
;Task complete interrupt
'

EOU
EOU
EQU
EQU

84H
0BH
10H
AIH

;Special interrupt
,92 Output (to CPU) Buffer full
,92 Input (from CPU) Buffer empty
,91 Int line (BO in this easel

GPIB 'lESSAGgs (COMMANDS)
EQU
EOU
EQU
EQU
EOll
EOU
EOU
EOU
EQU
EQU
EQU
EQU
EOU

1
MMHAH
MDA+20H
3FH
08
84H
IBH
19H
05
10H
60H

ISH
09

;M.y device address is 1

;M.y talk address is 1

(~A·)

,My listen address is 1 (MIM)
;Unlversal unlisten
;Group Execute Tr iqqer
;Device Clear
,Serial poll enable
,Serial poll disable
;Parallel poll confiqure
;ParAllel poll disable
;Parallel poll disahle
,Parallel poll unconfiqured
;'fake control (pass control)

MACRO DEFINI'rIONS

H~

H7
168 ,
169 SETF
170

171

172
173
174
175
176
177
178
179
lR0
181
182
183
184
185

,
WAITO
WAITL.

MACRO
ORA
END.,
, MACRO
LOCAL
IN
ANI
JZ

;Sets flaC]s on A reqister
A

;Wait for last 91 byte to be none
WAITL
INTI
BOM
WAITL

ENDM

,
WAITI
WAITL.

MACRO
LOCAL
IN
MOV
ANI

186

JZ

181
188 ,
189'WAITX
190
191 WAITL.
192

ENDM

193

JNZ

194
195

END'"

MACRO
LOCAL
IN
ANI

,Get IntI status
;Check for hyte out
:If not, try aqaln
;until it is
;Wait for 91 hyte to be input

WAITL
INTI
B,A
8IM
WAITL

;Get INTI stlltus
,Save status in B
;Check for byte In
; If not, just try aqaln
,until it is '

;Walt for 92's Tel to go false
WAITL
PRTF
TCIF
WAITL

231324-32

3-66

intJ

1090 3EAA
le02 D3~8
1004 3E'~
1900 030~
10~9 3EE0
lA~A

03fi~

U~C 3E80
100E 03~4
leU 3E23
HH2 03<;5

1014
1015
1017
1019
101S

AF
0301
03.2
03~5

C9

AP-66

196 WAITT
MACRO
WAITL
197
~OCA~
198 WAIT~:
PRTF
IN
:Get task complete int,etc.
ANI
199
TCIF
:h1ask 1 t
200
JZ
WAIT~
:Wa i t fa r til sk to be com pI ete
201
ENOM
202
LOWER, UPP~R, LABEL
203 RANGE
MACRO
204
:Checks for value in ranqe
205
: hranches to 1 ahel if no t
200
;in ranqe. Falls throuqh if
207
; lower (= ( CH) eL) ) (= upper.
208
:Get next byte.
MOV
A,M
209
~OWER
CPI
210
~BE~
211
JM
UPPER+!
212
CPI
JP
~"BE~
213
214
ENDM
215 ;
216 C~RA
MACRO
217
XRA
A
;A XOR A "'"
218
ENDM
219
220
A.II of the followin!) routines have these com'l11on
221
assumptions about the state of the 87.91 & Q297. upon entry
222
to the routine and will exit the routinE" in an identical state.
223
224
225
BO is or has he en set,
8291 :
22.
All interrupts are rnasketi off
227
'rON morle, not LA
228
No holdoffs in effect or enabled
229
No holdoffs waitinq for finish cornmantJ
230
231
8292:
ATN asserted (active controller)
232
note: RC'rL is an exception--- it,expects
233
to not be active controller
234
Any previous task is complete & 92 is
235
ready to receive next command.
23.
R~85:
Pointer reqisters (DE,HL) enrJ one
237
heyond last le'la1 entry
238 * *.* * ** '* * '* *. * * * •• '* '* * '* ill * '* '* '* * '* '* '* '* '* '* *. *ill 'III '* '* '* * * '* '* '* '* '* '* *. * '* '* '*
239
240
241
I'ITIA~IZATION IlOU'rINE
242
INPu'rs:
243
None
244 OUTPU'rS:
r.lone
24~
CA~~R :
None
24. OES~'qOYS :
A,I"
247
A, IH'r,., ;F.:nahle Tel
248 NIT:
MVI
249
ou'r
I~TMR
;Output to 92 1 s lntr. mask req
250
MVI
A,OTO~1 ;nisa~le major talker/l istener
251
o~'r
AORAI
252
MVI
",DTOL2 ;Disahle minor talker/listener
AORAI
253
ou'r
254
A,TON
WI
;'rlilk only mocie
255
ou'r
ADR"O
25<;
MVI
A, C~~RT ;3 ~HZ for nelay timer
7.57
ou'r
AUX~D
258
CLflA
259+
X~.~
A
;A XOR A =0
2~~
ou'r
IN'I'I
2~1
ou'r
INn
,Disahle all 91 ml!sk hi ts
202
OUT
AUX"D
; Imme" i.iI te execute PO~
263
RET
264
2.5 * * * ............ *.. * *.* * .. * ..... * * .. **. * .. * ........ ** .. * * ............ * ............ .
2~~
2~7

268
209

SENO ROU'rINE

231324-33

3-67

inter

Ap·66

270
271
272
273
274
'27S
276

,
INPU'rs,
,
,
,
,

277 ,

1I1C 3£41
10lE D3~9
1021
1022
1124
1127
1129
IA2a
192C

DBfil
£692
CA20lB
3E3F
D369
78
D3~7

278
279
2B0
281
282
2B3
284

,
,
,
,

HL listener list pointer
DE data buffer pointer

C
ou'rpUTS.
CALLS,
DESTROYS.

SEND.

A,MTA

MVI
oU'r
WAITO
IN
2~S+??A3Bl'

28~+

ANI

287+
288
289

JZ
MVI
OUT
MOV
OUT

29B

291
292
293 SE~Dl.
294+
295+

,

IA2E
112F
!A31
1034
1~3~

IA39
1038'
IA3D
1040
1941
1143
1044

7F.
FE20
FA471A
FE3F
F2471A
DB61
E692
CA3919
7£
D36A
23
C32EIO

1047 DBfil
1049 E602
1I4B CA4710
1H4£
i0SB
!eS2
IAS4

3EFfi

305+??A~A2.

,Send M'rA to turn off Iny

DOUT

,previous talker

INTI
BOM

,Get Inti status
,Check for byte out

??A~Al

;If not, try aqaln

A,U~L

DOUT

A,B
EOSR

,Senti universal unllsten
Ito stop previous listeners
;Get EOS character
,Output i t to 82ql

;whlle listener ..•••
,Check next listen address
;Checks. tor value In ranqe
; branches to label if not
; in ranqe. Falls throu'Jh if

RANGE

20H,3EH,SEND2

MOV

A,M
29H
SEND2

29~+

297+
298+
299+
300+
301+
302+
3A3+
304

count-- 8 will caule no "'Ita to be sent
b FoOS ch.llracter-- software detected
none
none
A, C, DF.!, HL, F

,lower

(=

(

(H) (L)

CPI

JM

CPI

JP
"IAITO
IN
ANI
JZ
>lOV
OUT
INX

386+
307+
308
309
310
311
J~P
312
313 SEND2. WAITO
314+710933. IN
31S+
A~I
31H
JZ
317
318
319
MVI

INn
ROM

n3AA?
A,M
DOU'r
H

SENDI
INTI
BOM
71~9~3

;Get this listener
;Output to GPIA

;Increl'tent listener list pointer
;Loop till non-valid listener
;Enab1e 91 enrUnt) conditions
;Wait for 1stn addr accepted
;Get IntI status
,Check for byte out

;If not, try aqaln
;WAITO required for early versions
;of 8292 to Avoid GTC;B before OAe

A,GTSB

;Goto stan"lhy

CMD92

,

MVI

A,AXRA+EOIS

322
323
324+??AA04.
325+
326+
327
328+7100B5.
329+
33B+
331
332 ,
333 ,

OUT

AUX~D

1064 79

334
335

~OV

1165 B7
1065 CA88lB
IA69 l~
105A D3~0
10fiC BR

33~+

10S~

DB6F
C2S~18

E~02

IA5D DBSF
105F E692
1061 CASDlA

337
338 SEND3.
339
340
341
342

upper.

,wai t for previous listener sent
;Get tntl status
,Check for byte out
;If not, try again

OUT

lASB
10SA

(=

3EH+1
SEND2

320
321

D369
3EBB
D36S

)

;Get next byte ..

WA[TX
I~

ANI

PRTF
TCIF

J~Z

??A~A4

WAITT
IN
ANI
,lZ

PRTF
TCIF
??~095

delete next
SETF
ORA
JZ
LDAX
OUT
CMP

;Sttnci EOI with EOS character

,Watt for Tel to qo false

A,C

;walt for Tel on GT~A
;Get task complete int,etc.
;Mask It
;Walt for task to be complete
instructions to make count of O=2SFi

,Oet count
;Set flaqs

'A
SENM

; If count:9, send no data

D

,Get data byte

DOUT
B

;Output to GPIB
;Test EOS ••• this is faster
;anti uses less code than u!llin1
;91

1

s ENO or EOl bits

231324-34

3-68

inter
lA~D

CA7F lA

1070 DB~l
1972 E~~2
U74 CA7Bl0
1~77

13

lB7B BD
1879 C2~910
U7C C3BB10
U7F 13
lAB~

~D

10Bl DB~l
lOB) E~n
lAB5 CAB1l9
19B8 n,'D
19BA D3~9
10BC 3EBA
19BE D)~5

AP-66

343
344 SEND4:
345+??AIH'f;:
341;.
347+
348
349
35B
Hl
352 SEND5:
353
354

JZ

SEND~

;If char =

IN
ANI

INTl

;Get IntI statu'S

wl\rro
JZ
INX
DCR
J~Z
J~P

INX

OCR

1997 DB~F
1999 EI;02
199B CA97U
199E C9 '

, qo finish

for byte out

BO~

;C~eck

?'?A01'J~

o

;If n")t, try aq"dn
; Inr:reJ?\ent huffer pointer

C
SEND3
SENDo

,Decrement count
; I f count < ) ~, qo senrj

D
C

;Else qo finish
; fo r consi steney

"

;

WAI'fO
,'rhis ensures that the strlnrJard entry

355+??0AH7:
356+
357+
35H
359 SEND":
363

31H

I~

BO~

??0""'7

MVI
OU'f

A,TCSY
CIID92
A, AXRA
AUXIID

I\IIVI
OUT

3"2

IN'1'1

ANI

JZ

3~3

1099 DB~F
1992 E~92
U94 C29310

F.O~

;./AITX
3'i4 +77111"98: IN
3~5+
3~~+

A~I

31;7
366+?7;31"')9 :
369+
370+

371
372
373

;Get lnt! status
;Check for byte out
; If not, try a1ain
;assumptions for the next su'">routine are met
;Take control syncronously

;Reset send EOI on EOS
;Wait for TCI false

PRTF
TCIF

.JNZ
WAIT'r
IN
I\NI

TCIF

JZ

??9909

??9::'A8

PRTF

;Wait for TCI
;Get task complete int,etc.
;Mask it
;Wait for task to "e complete

RET
,._-*--._.*
.. _* ••• _._-* ... _--_ ... --... __ ... ______ ... __ .. _______ ._. __ _

374
RECE IVE ROU'rINE
375
376
377 ; INPU'r:
HL talker pointer
378
DE (lata buffer pointer
379
C count (max buffer size) " implil!s 251}

m

385 ; RETURNS:
38'5

109F 7B
lMO D3~7

3B7
388
389 I
399 RECV:
391
392
393+
394+
395+

EOS character
Fills buffer pointen at hy nE
None

B

;DU'rpUT:
382 ;CALLS:
383 ,DESTROYS:
384 I

MOV
ou'r
RI\NGE

A, BC, DE,

7E
FE40
FA3911
FE5F
F23911

lOAD 03150

lOAF 23
10BO
19S2
19B4
lOB7
10B9

DBl;l
E"02
CAB9lA
3E3F
DH0

10BS DBl;l
10BD E692
10BF CABB10

397+
398+
399+
40B+
401+
492+
403
4A4
405
406
407+??9BlA:
408+
499+
410
411
412
413+??""11:
414+
415+

F

A,B
;Get Ens character
EOSR
;Output it to 91
40H, SEH, RECVf)
;Checks for value in range

:branches to label if not
;In ranqe. Falls throuqh if

39~+

!BA2
!BAl
UA5
!BA8
10M

HL,

A=0 normal termination--Eos "Ietf"cted
A=4A £rror--- count overrun
A(4A or A>SEH Error--- ba~ talk ad"ress

; lower (= ( (H) (L) )
;Get next byte.
MOV
CPI
.JM

CPI
.JP
ou'r
INX
""Al'rO
IN
A'II
.JZ
MVI
ou'r
...,1\1 TO
IN

ANI
JZ

(=

upper.

A,M
49H
RECV6
5EH+1
RECVIl

DOUT
H

INTI
BOM
??aB1B
It.,UNL
DOUT
INTI
BOM

119Bl1

;valid if 40H(= talk (::oSEH
;Output talker to GPla
;Incr pointer for consistency
;Get IntI status
;Check for byte out

; If not, try aqain
;Stop other listeners
;Get IntI status
; Check for byte out
;If not, try aqain

231324-35

3-69

AP-66

UC2 3E21
IBC4 03~8
18C6 3E86
18C8 D3~5
IleA
IeCC
10CE
1001
1003

DBfil
E5A2
CACA10
3e4M
03~4

10D5 AF
1006 0355
1008 3EF~
UOA OH9
100C 086F
}HOE E632
10E8 C20C10
10E3
18E5
IBEA
18Ee
10EO
IBEF
lBF2
IBFJ
lBF5
l0F8
10FA
UFB
lAFC
lBFO
1180
1182

DB6F
E~02

OB51
47
E618
C20511
78
E681
CAEA10
OB60
12
13
00
C2EAlO
8640
C31711

1105'78
1186 E601
1108 C21011
118B DB61 '
IUD C30611
1110 OB60
1112 12
1113 13
1114 0D
1115 0600
1117 3EFO
1119 0359
ll1B DB6F
ll1D E602
I11F C21Bll
1122 DB6F
1124 E682
1126 CA2211

1129
112a
112D
, 112F
1131
1133

3E88

'1135
1136
1138
.1139

AF
0365
78
C9

03~5

3E80
D364
3E03
0365

41~

~VI

417
418
419
428
421+170912:
422+
423+
424
425
425
427+
428
429
430
431
432+??0013:
433+
434+ '
435
43H17A014:
437+
439 RECVl:
448
441
442
443
444
445
446
447
448
449
458
451
452
453 ,
454 RECV2:
455 RECV3:
456
457
458
459 RECV4:
460
461
462

ou'r
~VI

A,MLA
J For completeness
oou'r
A, AXRA+HOE"ID+EDEOS
;gnt1 when

or

ou'r
WAITO
IN
ANI
JZ

AUX!'1D

;EOS

INTI

~VI

A., LON

;Get IntI status
;Check for byte out
;If not, try ag~in
;Listen only

ou'r
CLRA

ADRPlJ)

BOM
??0!U2

XHA

A

OUT
",VI
ou'r
WAITX

AUXMD

IN

ANI
JNZ
WAITT
IN
~NI

IN
MOV

ANI
JNZ
MOV

ANI
JZ
IN
STAX
INX
DCR
JNZ
MVI

JMP

A,GTSB

CMD92

Eat & Hoinoff

; Immed late XEO PON
,A XDR A =0

;Goto standhy
;Wait for TeI=0

PRTF
TCIF
??0IH3
PRTF
TCIF
INTI
B,A

;wait for Tel=l
;Get task complete int,eto.
;Mask;

it

;Get 91 lnt status (END 'lor BI)
;Save it In 8 for BI check later

or

ENDMK

;ctteck for EOS

RECV2
A,a
BIOI
RECV1
DIN

,Yes end--- go wait for BI
;NO, retrieve status &
;check for BI
;NO, 1')0 wait for either END or BI
;YES, .81--- qet data
;Store it in buffer
; Increment buffer pointer
;Decrement counter
;If count < > A go back & walt
;Else set error indicator
;And qo· take control

o
D
C

RECV1
B,40H
RECV5

MOV
ANI
JNZ
IN
JMP
I!oI
STAX
INX

A,B

OCR

C

81M

RECV4
INTI
MECV3
DIN
D

D

EOI

;Retreive status
;Check for BI
;If B~ then ~o input data
;Else wait for last BI
;In loop
;Get data byte
;Store it in buffer
;Iner elata pointer
;Decrement count, but l,)nore it
;Set normal completion indicators

4~3
8,9
"'VI
464 ,
465 RECV5: MVI
A, TCSY
;Take control synchronously
466
ou'r
CMD92
467
WAITX
,Walt for TCI=~ (7 tcy)
468+??0015: IN
PRTF
469+
ANI
TCIF
478+
JNZ
17M915
471
WAITT
;Wait for Tel .. }
472+??0U 6: IN
PRTF
;Get task complete int,etc.
473+
, ANI
TCIF
;""Iask it
474+
JZ
??IJIH6
;Wlt i t fo r task to be complete
475
476 :i£ timeQut
is to be checked', the above WAITT should
477 ;be o:nitted & the appropriate code to look for Tel or
478 ;TOU'r3 inserted here.
479
480
MVI
A, AXR.l\
;pattern to clear 91 END conrHtions
481
ou'r
AUXMD
;
482
MVI
A,TON
;This bit pattern alrea"y in "A483
OUT
ADRMD
;Output TON
484
MVI
A,FNHSK ;Finish handshake
485
OUT
AUXMD
486
CLRA
487+
XRA
A
;A XOR A =0
488
ou'r
AUXMD
; IlI1med iate execute PO~-Reset LO~
489
MOV
A,B
;Get completion character
490 RECV6:
RET

3-70

231324-36

inter

AP-66

*._.*.,

491 ,
492 J •• *.,., * * * * '* * '* -* '* '*., III '* * *
_* *._.111: * * * * * * * * * * *., *.* .. * .... '* * *_ • ., *
493
XHi< ROU'UNE
494
495 ,
49~ ,INPU'rS:
HL rJevice list pointer
497
B EOS character
49B ;OU'fPUTS:
None
499 ,CALLS:
None
590 ;DESTROYS:
A, HL,
591 ; RETURN'S:
A=3 normal, A ( ) 0 har'l talker
532
5q3 ,
594 ; NOTE:

535
506
507
~P8

113A
113B
1130
1149
1142
1145
1147
1148
114A
114C
114F
1151

1153
1154
1156
1159
115B

7E
FE40
FABB11
FE SF
F28B11
0350
23
OB51
£602
CA4B11
3E3F
0360

7£
FE28
FAGC11
FE3F
F26C11

115E
1160
1162
1165
1166

0861
£602
CA5El1
7E
0359
l1~B 23
1169 C35311

116C
116E
1179
1173
1175
1177
1179
117a
117C
117E
117F
1181
11B3

0861
E602
CA6Cl!
3EB7
0355
3E40
0364
!IF

0365
78
0367
3EF5
0359

589
510 ,
511 XFER:
512+
513+
514+
515+
5H+
517+
51R+
519+
520+
521+
522
523
524
525+119017:
526+
527+
528
529

539 XFER1:
531+
532+
533+
534+
535+
536+
537+
53B+
539+
549+
541
542+??9018:
543+
544+
545
546
547
548
_ 549 XFER2:
550+110919:
551+
552+
553
554
555
555
557
558+
559
560
551
552
563

RANGE

MOV
CPI
JM

CPI
.TP

OUT
INX

XFER will not work if the talker
uses EOI to terminate the transfer.
Intel will be making hardWare
modifications to the 9291 th?lt will
correct this problem. Until that time,
only EOc:i may be used without possible
loss of the last rtata byte transfered.
4f1H, SEH, XFER4
;Check for val id talker
;Cheeks fot' value in ranqe
;branches to label if not
;in ranqe. Falls throu'lh if
; lower (= ( CH) tLl ) (= upper.
;Get next byte.
A,M
40H
XFER4
5EN+l
XFER4
IlOUT
; Senti it to GPIB
H
;Iner pointer

"'AI'rO
IN

IN'r1

ANI

80M

JZ

;Get IntI status
;Check for byte out
,If not, try again
;Universal unl isten

MVI

??AA17
A,UNL

OUT

OOUT

RANGE

2f1H,3EH,XFER2
:Check for valid listener
;Checks for val ue in range
;branches to label if not
;in range. Falls through if

MOV
CPI

A,M
2AH
XFER2
lEH+l
XFER2

,lower

<= (

(H) (L)

)

<=

"pDer.

;Get next byte.
JM

CPI

JP
WAITO
IN

ANI
JZ
MOV

ou'r
INX

INTI
80M

:Get IntI status
;Check for byte out

??0018
A,M

;If not, try again

IlOUT

:Get 1 istener

JMP
WAITO

XFER1

:Incr pointer
;Loop until non-valin listener

IN
ANI

INTI

;Get IntI status

80M

;Check for byte out

JZ

1?""19

,If not, try again

~VI

A, AXRA+CAHCY+EDEOS
:Invisible hanrlshake
AUX"10
;Continuous ~H mode
A,LOS
:Listen only

OUT
MVI

ou'r

H

AOR~O

CLRA

XRA
OUT

AUX~O

; Immed. XEQ PON

MOV

A,B

;Get EOS

aU'f

EOSR

MVI

A,GTSB
CM092

;Output it to 91
;Go to standby

OUT

A

,A XtJR A ."

231324-37

3-71

inter
118~

08~F

1187 E~02
1189 C28511

AP-66

564
565+110020:
556+
567+
5~8

118C
118E
1190
1193
1195
1197
119A
119C

D86F
£602
CA8C11
0861
E~U

CM311
3EFO
OH9

11A5
11A7
11M
11AC
11AE
1180
1182
1184

DB6F
£602
CAI\511
3E80

118~

03~4

03~5

3£03
0355
3£80

1188 AF
1189 0355
1188 C9

11C0
11CI
11C3
11C6
lIC8

7E
FE28
FA0911
FE3F
F20911

11C~

11CO
11CF
1102
1103
1105
1106

0861
£5n
CACB11
7£
0360
23
C3C011

1109
110B
1100
11£0
11E2

OB61
EoA2
CAD911
3E08
OH0

11E4 0851
11E~ E6n2

WAITT
IN
ANI

PRTF
TCU'
?1011128
;Wait- for TCS
;Get task cl')mplete tnt,etc.
;Mask 1 t

I~

I~TI

ANI
,lZ
MVI

ENDMK
XFER3

;Mask 1 t

A,TCSY

57~

ou'r

;'rake control syncronously

C'I092

JZ

PRTF
TCIF
??0921

;Wait for task to be complete
;Get END status bit

WAITX

578+1700122:
579+
580+
581
582+710023:
583+
584+
5~5

586
587
588
589
590
591
592+
593
594 XFf<4:
~5

118C 3E3F
118E 03~0

JNZ

569+110321 :
570+
571+
572 XFER3:
573
574
575

577
119£ D85F
11A0 E692
11A2 C29E11

WAITX
IN
ANI

I~

ANI

JNZ
WAITT
IN
A~I

JZ
'"'VI

ou'r
MVI

ou'r

PRTF
TCIF
119322

;Wait for TCI
PRTF
TCIF
710023
A,AXRA
AUX'ID

;Wait for task to be complete
;Not cont AJt 0 rEN'O on EOS

A,FNHSK 1Finish handshllke
AUX~D

",VI

A,TON

ou'r

ADRMD

CLRA
XRA
OUT
RET

;Get task complete jnt,etc.
;Mask it

;Talk only
,Normal return A=G

A
AUX~D

;A XOR A =0
;Immediate XEQ PON

,

.

596 ; *.***. * **** * ***** ***.* '!'*** **~** ** *** ** * **'*. *** *** __
597
598
599
TRIGGER ROUTINE
500
501 ;
602 iI~PU'rS:
HL listener list pointer
603 ;OUTPU'rS:
None
604 ;CALLS:
None
50S ,OESTROYS:
A, HL, F
686
607 ,
608 TRIG:
MVI
A,UNL
;
6A9
ou'r
DOUT
;Send universal unl isten
619 TIUGl:
RANGE
20H,3EH,TRIG2
;Check [or valid listen
611+
,Checks for value in ranqe
~12+
;branches to label if not
~13+
lin ranqe. Falls through if
614+
,lower (= ( (M) (L) ) (- upper.
615+
;Get next byte.
6H+
MOV
A,M
617+
CPI
208
618+
J~
TRIG2
619+
CPI
3EH.I.
62A.
JP
TRIG2
621
WAITO
;Walt for LNL to finish
~22.710024.
IN
INn
;Get IntI status
~23+
liN I
BOM
;Chetek for byte out
624+
JZ
?10924 ;If not, try a~ain
625
'IOV
A,M
,Get listener
626
DOUT .
ou'r
; Send Ll stener to GPIB
627
INX
H
;Iner. pointer
628
JMP
TRIG)
,Loop until non-valid char
629 TRIG2: WIIITO
,Wait fl')r last listen to finish
630+??0025.
IN
INn
;Get IntI st .. tus
631+
liN I
ROM
,Cheek for byte out
632+
JZ
110B25 ,If not, try a~ain
633
·WI
... ,GET
;Senn qroup execute tril')'ger
634
OUT
DOUT
Ito all addresset! listeners
635
WAITO
IN
G36+??9B2fi:
INTI
;Get IntI status
637+
ANI
aOM
;Check for hyte out

3-72

231324-38

inter
11E8 CAE411
11EB C9

AP-66

638+
639
648 ,

JZ

??U26

,If not, try again

RET

641 , ••••• _••••••••••••••• _-_ •••••• _ •••• _- •••••

642
643
644
645
646
647
648
649
~51

11EC 3E3F
11EE D3~0

UF8
UFl
llF3
llF6
11F8

7£
FE28
FA0912
FE3F
F2B912

lll'B
llFD
llFF
12B2
12B3
12B5
1206

DB61
E682
CAF811
7E
D36B
23
C3FBll

12B9
12BB
12BD
1218
1212

DB61
E682
CA8912
3£94
0368

1214
1216
1218
121B

DB61
E682
CA1412
C9

,
,DEVICE CLEAR ROU'rINE
,
,
,
,INPUTS,
HL listener pointer
,OUTPUT:
None
,CALLS:
None
,DESTROYS:
A, HL, F
,
DCLR:
MVI
A,UNL
OUT
DOUT
DCLR1: RANGE
28H,3EH,DCLR2

651
652
653
654
655+
656+
657+
658+
659+
661+
661+
662+

OIDV

A,M

CPI

288
DCLR2
3EH+1
OCLR2

JM

~63+

CPI

664+
665

JP

667+

WAITO
IN
ANI

6~8+

JZ

6~6+118827:

INT!
BOM
??8827

,Cheeks for value in range
,branches to label 1 f not
; in range. '''lIS throuqh if
,lower (= ( (H) IL) ) (- uPper.
;Get next byte.

;Get IntI status
,Check for byte out
;If not, try again

669
MOV
A,M
678
OUT
DOUT
;Send listener to GPIB
671
INX
H
672
Ji'lP
DCLR1
673 DCLR2: WAITO
674+178128: IN
INT1
;Get Intl status
675+
ANI
BOM
,Check for byte out
JZ
676+
778828 ;If not, tryaqain
677
MVI
A,SDC
,Sen~ device clear
678
OUT
DOUT
,To all addressed listeners
679
WAITO
689+118829: IN
INT1
;Get IntI status
681+
ANI
BOH
,Check for byte out
682+
JZ
118929 ,If not, try again
683
RET
684
685 ;,._._-----.-._._._. _____ •••• ________ e __ e ______ .e •• __
fi86
687

121C 3E3l'
121£ 0361
1228
1222
1224
1227
1229

DB61
E6B2
CA2812
3E21
0368

1228
122D
122F
1232
1234

DBG1
E692
CA2B12
3El8
D361

1236 D861

SERIAL POLL ROUTINE
~88 ,
689 ,INPUTS:
HL talker list pointer
698
DE status buffer pointer
691 ;OUTPUTS:
Fills buffer pointed to by DE
692 ,CALLS:
None
~93 ,DESTROYS:
A, BC, DE, HL, F
694
695 SPOL:
MVI
A,U~L
,Universal unllsten
696
OUT
DOUT
697
WAITO
698+178038: IN
INTl
,Get Inti status
699+
ANI
BOM
,Check for byte out
7BB+ .
JZ
??8B38 ,If not, try again
781
MVI
A,MLA
, My I I sten add ress
702
OUT
DOUT
703
WAITO
784+178031 :
IN
INTI
;Get IntI status
785+
ANI
BOM
,Check for byte out
786+
JZ
118131 ,If not, try aqain
787
MVI
A,SPE
,Serial poll enable
788
OUT
DOUT
,To be formal about 1 t
789
WAITO
718+178832: IN
INT1
,Get IntI status

,

231324-39

3-73

AP-66

1238 EI'jA2

123A

CA3~12

711+

II~I

BOflo)

;Check for byte out

712+
71 3 SPOLl:
714+
715+

.1Z
RANGE

??AA12

;If not, try again

40'H,SP.H,SPOL2

71fl+

1230
123E
1240
1243
1245
1248
1249
124B
124C
124£

7PFE4A
FA9412
FE5F
F29412
7E
03~0

23
3E40
D364

1250 0861
1252 E502
1254 CA5012
1257 IIF
1258 D3~5
125A 3EF6
125C 0369
125E D86F:
12~0 E502
12~2 C25E12
1265 DBGF
1267 £602
1269 CM512
126C
126£
126F
1271
1274
1276

DB~1

47
E6n
CII6C12
]EFD
D3S9

1278 DB6F
12711 E602
127C C27812
127F
1281
1283
1286
1288
1289
12811
128C

DB6F
£602
CA7Fl2
DB60
12
13
3£80
D364

128E AF
128F D365
1291 C33D12
1294 3E19
1296 D360
1298 DB61
129A £6~2
129C CA9812
129F IIF
12AO D365
12A2 C9

717+
71A+
719+
720+
721+
722+
723+
724
725
726
727
728
729
739+710033:

731+
732+
733
734+
735
736
737
738
739+170034:
748+
741+
742
743+1?A035:
744+
745+
746
747+170035:
748+
749+
759+
751
752
753
754+?10037:
755+
756+
757
758+170338:
759+
760+
761
762
763
764
765
766
767+

; lower

MOV
CPI

J'"

CPI
JP
·~OV

oU'r
oU'r

ADRMD

WAITO
IN
ANI

80~

??0033
II

oU'r
~VI

WAITX
IN
ANI

JNZ
WAITT
IN
ANI

JZ
WAITI
IN
HOV
ANI

JZ
MVI

AUXMD
A,GTSB
CMD92

PRTF
TCIF
170035
IN'rl
B,A
aIM
170036
A,TCSY

A~I

PRTF
TeIF
170037

JNZ
WAIT'r
IN
ANI
.1Z
IN
STAX
INX
MVI

ou'r

(H) (L)

) (s upper.

;Get talker
,Sen'" to GPIB

;Incr tl'llker list pointer
;Listen only

;wait for talk atidress to complete
;Get IntI status
,Check for byte out
;If not, try again
;Pattern for Imme~iate XEQ PON
III XOR A cB
;Goto standby

PRTF
TCIF
170B34

Cl'ID92

WAITX
IN

(

;Wait for Tel false

ou'r

;Wait for Tel
;Get task complete int,etc.
,Mask it
;Walt .fnr task to he complete
;Wait for status hyte input
,Get INTI st .. tus
;Save status in B
,Cheek for byte in
IIf not, just try again
;Tltke control sync

;Wait for Tel false

PRTF
TCIF
170038
DIN
D
D

A,TON
ADRMD
A

,Walt for TCI
,Cet task complete int,ete.
;Mask it

;walt for task to be complete
;Get serial pOll status byte
;Store it In buffer
; Incr pointer

;Talk only for controller.
;

,A XOR A

~n

IIUXMD

; Immed 1 ta te XI:':Q PON

JMP

SPOLI

,CLR LA
ICO on to next device on list

MVI
OUT
WAl'fO'
IN

A,SPO

,Serial poll disable

A~I

777+

JZ
CLRA
XRA
OUT
RET

783 I

INTI

CLRA
XRA

778
779+
780
781
782 I
784

H

JZ

CLRA
XRA

769
770
771 ,
772 SPOL2:
773
774
775+??a039:
776+

40H
SPOL2
5tH+i
SPOL2
A,M
DOU'r
A,LO~

ou'r

(=

,Get next hyte.
A,M

INX
!'IVI

ou'r

H8

;Check for valid to!!llker

;·Cheeks for value In ran'1e
: hrllnches to 1,,")el if not
:in ranqe. Falls throuqh if

DOUT

;We know 80 was set (WAITO above)

INTI
BOM
??B039

:Get IntI status
,Check for byte out
;If not, try 8'1ain

A

;A XOR A cA
; Immed late XEQ PON to cl ear LA.

AUXMD

** .*.**** .**** .... **** ** ***.* ** ***** ** ••••• "'''''''''* .. *. * ...
231'324-40

3-74

intJ

Ap·66

785

PARALLEL POLL ENABLE Rou'rINE

78~

12A3 ]~3F
12A5 D360

12A7
12A8
12M
12AO
12AF

7E
FE20
FA0812
FE3F
F20812

12B2
12B4
12B6
12B9
128A

OB61
£692
CAB212
7£
0359

128C
128£
12Cn
12C3
12C5

OB61
£602
CABC12
]E05

12C7
12C9
12Cd
12CE
12CF
1201
1203
1204
1205

0861
CAC712
1/\
Ffi6B
0360
23
13
C3A712

1208
120/\
120C
12DF

0861
£602
CA0812
C9

O]~0

E~~2

787
788

INPUTS:

HL listener 11st pointer

789

OUTPU'rS:

None

rJE confi'luration byte pointer

79B CALLS:
791 DESTROYS:
792
791
794 PEN:
MVI
795
au'r
795 PPEN1:
RANGE
797+
798+
799+
800+
891+
8A2+
MOV
803+
CPI
804+
J~
895+
CPI
806+
JP
897
WAITO
898+110049:
IN
809+
ANI
819+
JZ
811
MOV
812
OUT
813
'~AITO
814+??0041 :
IN
815+
ANI
816+
JZ
817
'~VI
8111
Ou'r
819
WAITO
820+1?0042 :
IN
821+
ANI
822+
JZ
823
LDAX
824
ORI
825
ou'r
826
INX
827
INX
828
JMP
829 PPEN2: I~AITO
839+119343:
IN
ANI
831+
832+
JZ
833
RET

None
A, OF-, HL,

F

A,U~L
;Universal unl isten
DOU'r
20H,3EH,PPElIJ2
;Check for valid listener

,Checks for value in ranqe
:branches to label if not
lin ran"e. Falls throUtlh If

,lower

(=

(

(HI (LI

I

(=

upper.

;Get next byte.
A,~

2AH
PPEN2
3EH+l
PPEN2
IN'rl
80M
??nA4A

A,M
oou'r
IN'rl
80M

1?9041
A,PPC
DOUT

INT1
80M

110042

o

PPE
OOUT

;Valid wait 91 data out req
;Get IntI status
;Check for hyte out
: If not, try aqain
;Get listener
;Get IntI status
;Check for byte out
;If n~t, try again
;parallel poll confiqure

;Get IntI status
;Check for byte out
rIf not, try again
;Get matchin'l confiquratlon byte
;Met'l'e with parallel poll enable

H

;Incr pointers

PPENl

;Loop until Invalirl listener char

INTl

;Get IntI status
;Check for byte out
;If not, try again

o
80~

??U43

:~~

12£0 3£3F
12E2 0350

12E4
12E5
12E7
12EI\
12£C

7E,
FE20
FAF012
F£3F
F2FD12

12£F OBfil
12Fl £602
12F3 CAEF12

;PARALLEL POLL OISA8LE ROU'rINE
8]6 ,
837 ,INPU'rS:
HL listener list pointer
838 ,OU'rpUTS:
None
839 ,CALLS:
None
849 ,DESTROYS:
A, HL, F
841 ,
842 PPOS:
A,U'iL
I'1VI
;Universal unl isten
84]
ou'r
DOUT
844 PPDS1:
RANGE
23H, 3eH, PPDS2
; Check for val id Ii stener
845+
,Checks for value in ranqe
84~+
; branches to lahel if not
847+
; in ran'le .. Falls throuqh if
848+
; lower (= ( (ti) eLl ) (= upper ..
849+
;Get next hyte ..
859+
MOV
A,M
851+
• 20H
CPI
852+
J~
PPOS2
853+
CPI
]EH+l
854+
lP
PPDS2
855
WAITO
856+??0044 :
IN
IN'fl
;Get IntI status
857+
MI
BO~
;Check for hyte out
,JZ'
858+
??3"44
;If not, try aqain

231324-41

3-75

intJ
12F6
12F7
12F9
lUA

7E
0368
23
C3F.412

12FO 0861
12t"F F.~H2
1391 CAFOl2
13114 3EAS
139~ 0359
1398 0861
13ell E~82
13ec CA8S13
13BF 3£7~
1311 OH9
1313
IllS
Ill7
131A

0861
E602
CA1313
C9

Ap·66

859

~OV

8~9

OUT
INX
J'IP
WAlTa
IN
ANI
.1Z

~~I

M2
863 PPOS2:

86H11A~45:
8~5+

8511+
867
8~8
S~9
87w+nB~4r,:

A,M
DOUT

,Get 1 i stener

~

,Iner pointer
,Loop until invalid listener

PPDSI
INn
80'1
n8A4~

~VI

A,PPC

ou'r
WAlTa
IN
ANI

DOUT

;Get IntI St"tU5
,Check for byte out
,If not, tryaqain
;parallel poll confiC'JuE'e

INTI
,Get IntI status
871+
80~
,Check for hyte out
872+
JZ
119846 ;If not, try aqat"
A,PPD
873
"VI
,Parallel poll disable
874
OUT
DOUT
875
WAlTa
876+119847:
IN
IN'U
,Get Inti status
877+
·ANI
BOIo\
,Check for byte out
878+
JZ
??8847 , If not, try aqain
879
RET
888
881
PARALLEL POLL UNCONFIGURE ALL ROU'rINE
882
883
884 I INPUTS:
None
885 ,OUTPUTS:
None
886 ICALLS:
None
887 ,DESTROYS:
A, F
888 I
889 PPUN:
~VI
A,PPU
,Parallel poll unconfiqure
899
DOUT
ou'r
891
WAlTa
892+??3048:
IN
INTI
;Get IntI status
893+
ANI
80'1
;Cheek for byte out
894+
JZ
??8B48 ,If not. try 8'1ain
895
RET
895
897 , ********* * ***** ** ***** ***** *** **.* * ** ** * * •• ****** *
898 I
899 ICONDUCT A PARALLEL POLL
988
9al
9A2 ,INPu'rs:
~one
903 IOUTPUTS:
None
984 ,CALLS:
None
985 I DESTROYS:
A, ft, ..
9A6 ,RETURNS:
A= par"llel poll status byte

,

IllS 3£15
1310 0368
131F
1321
1323
1326

0861
£6B2
CAIF13
C9

,
,

1327 3£4B
1329 0354
1326 AF
132C 0365
132£ 3EF5
1339 03~9
1332
1334
1335
1337
133A
133C

0861
47
£Ul
CA3213
3ES8
0364

133£ AF
133F 0355
1341 OB~8
1343 C9

m~POL:

A,LON
"IVI
,Listen only
989
ou'r
AI)R"D
918
CLRA
I Immed late X£O paN
911+
XRA
A
IA XOR A -9
912
OUT
AUXMO
,Reset TO'"
",VI
913
A,EXPP ;Execute parallel poll
914
OUT
CMD92
915
WAITI
,Wait for completion= BI on 91
916+n8A49: IN
INTI'
,Get INTI status
917+
MOV
8,A
rSave status in e
918+
ANI
~IM
ICheck for byte In
919+
JZ
nBW49 ,If not, iust try aqain
928
MVI
A,TO~
ITaik only
921
OUT
ADR'ID
922
CLRA
I Immed late XEQ PON
923+
XRA
A
rA XOR A -"
924
ou'r
,Reset LO'"
AUX"D
925
IN
DIN
IGet PP byte
926
RET
927 ,
928 ; ***** •••• **** * * *** * * ***.* ** *** *** ********* ***.
929 ,PASS CONTROL ROU'rINE
938 I
931 IINPu'rs:
HL pointer to talker
932 ,0u'rpUTS:
None

3-76

231324-42

AP-66

1344
1345
1347
134A
134C
134F
1351
1354

7E
FE40
FA8A13
FE5F
F28A13
FE41
CABA13
03<;0

1356 0861
1358 EG~2
135A CA5~13
1350 3E09
135F 03<;"
1361 OB61
1363 E602
13~5 CMl13
1368 3EOl
136A 0364
13'5C
1360
13<;F
1371
1373
1375

AF
0365
3EOl
0356
3EAl
D3~5

1377 JEFI
1379 D3~9
1378 DB~F
1370 E602
137F C27B13
1382
1384
1385
1389
138A

OB6F
E602
CA8213
23
C9

933 ;CALLS:
934 ,DESTHOYS:
935 PCTL:
RANGE
936+
937+
938+
939+
940+
941+
MOV
942+
CPI
943+
J."
944+
CPI
945+
JP
946
CPI
947
JZ
94 R
OUT
949
WAITO
95A+??A}tS::J :
IN
951+
A~I
952+
JZ
953
'1VI
OU'f
954
WAITO
955
956+71121051 :
IN
957+
A"I
958+
JZ
959
'1VI
960
ou'r
951
CLRA

to

la~el

ran~e

if not

lin ranqe. Falls through if
; lower (= ( (M) eLl ) (= upper.
;Get next byte.
A,M
40~

PCTLI
5EH+l
PCTLI
MTA
PC'fLl
DOUT
INn
BOM
170050
A,TCT
DOUT
I!'J'U
80M
170351
A,MODEl
ADRMD

;Is it my talker

ad~ress

;Yes, just return
;Senrt on GPIB

;Get IntI status

;Check for byte out
;If not, try again
;Take control meSS8Qe
;Get IntI status

;Check for hyte out
;If not, try again
;Not talk' only or listen only
;Enable ql anrlress mone 1

XRA

A

OUT

AUXto!.O; Immed iate XEO PON

'~VI

ou'r

A,MDA
ADRAI

96~

MVI

; A XOR A =0
;My device adrlress

;enabled to talk and listen
A,AXR8+CPTE""
;Command pass thru enable

967
Du'r
AUX"'10
968 ;*****··optional PP configuration goes here**** •• **
9~9

MVI

970
971
972+??9952 :
973+
974+
975
97ti+??(/JA53:

977+
978+
979
9S0 PCTLl:
981
982 ,

A,GIDL

ou'r

CMD92

WAITX
IN
ANI

PRTF
TCIF

JNZ

??~:;'52

WAITT
IN
ANI

PRTF
TCIF

JZ
INX
RET

??0A53
H

;q2 go idle commanrl

;Wait for TCI
;Get task c~mplete int,etc.
;Mask it
;Wait for task to he complete

************************ ••• ****.t ••• ******

;RECEIVE CONTROL ROUTINE

986
987 ; INPUTS:
988 ,OU'fPUTS:
989 ;CALLS:

None
None
None

990 ;DP.STROYS:

A, F

991 ,RETURNS:
992 ,
993 ,NOTE:
994

THIS CODE MUST BE TIG~TLY WTEGRATED IN'fO ANY USp.~
SOFTWARE THA'f FUNCTIONS tilTH 'fHP. "291 A~ A DEVICE.

995

E680
CACF13
1)865
FE09

;b~anches

9~2+

983 ;

D8~1

; Is i t a val id talker

;Checks for value in

963
964
965

::~

138B
1380
138F
1392
1394

None
A, HL, F
4121H, 5EH, PCTLI

996
997
998
999
HHl0 ;
1031 RCTL:
1002
1003
1004
1005

A= invalid fnot take control to us or cP'r bit not on)
( > " = val id take control-- 92 will nnw be in control
NORMALLY SQI'
"1.5Tl
SF.Nn4

A '''''lEt
A IJCF

"!lFB

5PO

"AFR
"'Aen

SQOHT
'rc,sy
'ro"l

11RC

TM IGI

;t~!l4

'flAITX
XF't:qll

,

,+

A~!-I2

1193

PCTLI

A llJ9

RF./OtE

A "ltF)
1\ lA70
A An19
A A"291
I\. A!lFC

RTou'r

A 12A7
A 'Hl~F
A lA9F
A 13P.3
A 0~E9

SF.~DS

A HJ7F

SPi';

SAQr)

A 1'''113

A 1]00

'fell!'

A A"A2

A~qll

TOi~EG

llC~

rRJG2
rrlF.VC

A Ant;B
A 1109
A A1F:2

, nu,,)
,
A

RECV

+

11ari

NO ERflORS

231324-47

3-81

inter

Ap·66

APPENDIX B
Analyzer was used. This analyzer acted as a talker, listener or another controller as needed to execute the
tests. The sequence of outputs are shown with each test.
All numbers are hexadecimal.

Test Cases for the Software Drivers
The following test cases were used to exercise the software routines and to check their action. To provide
another device/controller on the GPIB a ZT488 GPIB

Send Test Cases
B=
C=
DE=
HL='
3E70:
3EBO:
GPIB output:

Ending B=
EndingC=
Ending DE=
Ending HL=

44
30
3EBO
3E70
20 30 3E 3F
11 44
41 ATN
3FATN
20ATN
30ATN
3EATN
11
44EOI

44
2
3EBO
3E70

44
0
3EBO
3E70

41 ATN
3FATN
20ATN
30ATN
3EATN
11
44EOI

41 ATN
3FATN
20ATN
30ATN
3EATN

44
2E
3EB2
3E73

44
0
3EB2
3E73

44
0
3EBO
3E73

Receive Test Cases
B=
C=
DE=
HL=
3E70:
GPIB output:

ZT4BB Data
In

EndingA =
Ending B =
EndingC =
Ending DE=
Ending HL=

44
30
3E80
3E70
40
40ATN
3FATN
21 ATN
1
2
3
4
44
0
0
2B
3EB5
3E71

44
30
3EBO
3E70
50
50ATN
3FATN
21 ATN
1
2
3
4
5,EOI
0
0
2B
3EB5
3E71

44
30
3EBO
3E70
5E
5EATN
3FATN
21 ATN
1
2
3
44,EOI

44
30
3EBO
3E70
5F

44
4
3EBO
3E70
40
40ATN
3FATN
21 AT~
1
2
3
4

44
4
3EBO
3E70
40
40ATN
3FATN
21 ATN
11
22
33
44

44
0=256
3EBO
3E70
40
40ATN
3FATN
21ATN
1
2
3
44

0
0
2C
3E84
3E71

5F
44
30
3EBO
3E70

40
40
0
3EB4
3E71

0
0
0
3E84
3E71

0
0
FC
3EB4
3E71

3-B2

AP-66

Serial Poll Test Cases
C=
DE=
HL=
3E70:

30
C=
3E80
DE=
3E70
HL=
40
3E70:
50
GPIB output:
5E
5F
GPIB output: 3F ATN
output: 21 ATN
EndingC =
output: 18 ATN
Ending DE=
output: 40 ATN
Ending HL=
input': 00
output: 50 ATN
input': 41
output: 5E ATN
input': 7F
output: 19 ATN
°NOTE: leave ZT488 in single step mode even on input
EndingC = 30
Ending DE = 3E83
Ending HL= 3E73
Ending 3E80: 00 41 7F

30
3E80
3E70
5F
3FATN
21 ATN
18ATN
19ATN
30
3E80
3E70

Pass Control Test Cases
HL=
3E70:
GPIB output:

Ending HL=
EndingA =

3E70
40
40 ATN
09ATN
-ATN
3E71
02

3E70
41 (MTA)

3E70
5F

3E70
41 (MTA)

3E70
5F

Receive Control Test Cases
GPIB input
Run Receive Control
GPIB Input
EndingA=

10 ATN
ATN

o

40ATN
09ATN

41 ATN
09ATN

ATN

ATN
09

o

3-83

inter

AP-66

Parallel Poll Enable Test Cases
OE=
HL=
3E70;
3E80;
GPIB output:

Ending OE=
Ending HL=

3E80
3E70
20 30 3E 3F
01 02 03
3FATN
20ATN
05ATN
61 ATN
30ATN
05ATN
62ATN
3EATN
05ATN
63ATN
3E83
3E73

3E80
3E70
3F

3E70
20 30 3E 3F
3FATN
20ATN
30ATN
3EATN
05ATN
70ATN
3E73

3E70
3F
3FATN
05ATN
70ATN

3FATN

3E80
3E7Q

Parallel Poll Disable Test Cases
HL=
3E70;
GPIB output;

Ending HL=

3E70

Parallel Poll Unconflgure Test Case
GPIB output:

IS ATN

Parallel Poll Test Cases
Set 010#
Ending A

1 2 3· 4, 5
6 7
1 2 4 8 10 20 40

8
80

None
0

SRQTest
Ending A =

Set SAO momentarily
02

3-84

AesetSAO
00

infef

Ap·66

Trigger Test
HL=
DE=
BC=
3E70:
_GPIB output:

3E70
3E80
4430
20 30 3E
3FATN
20ATN
30ATN
3EATN
08ATN
3E73
3E80
4430

Ending HL=
DE=
BC=

3F

Device Clear Test
HL=
DE=
BC=
3E70:
GPIB output:

3E70
3E80
4430
20 30 3E
3FATN
20ATN
30ATN
3EATN
14ATN
3E73
3E80
4430

Ending HL=
DE=
RC=

3F

XFERTest
44
3E70:
40 20 30 3E
40ATN
3FATN
20ATN
30ATN

B=
HL=
3E70:GPIB output:

3EA~N

o

GPIB input:

1
2
3
44

o

Ending A =
B=
HL =

44
3E74

3-85

3f

intJ

Ap·66

Application Example
GPIB Output/Input
41 ATN
3FATN
32ATN

GPIB output:

4~

55
31

46
52
33

37
4B
48
41
4D
32
56
4F
ODEOI
41 ATN
3FATN
31 ATN

50

46
34

47
37
54EOI
SRO
3FATN
21 ATN
18ATN
51 ATN
.40SRO
19ATN
51 ATN
3FATN
21 ATN

GPIBinput:
GPIB output:

GPIB input:
GPIB output:

3-86

inter

AP-66

20

GPIB input:

2B

20
20
20
33
37
30
30
30
2E

30

45
. 2B
30

00

OA
XXATN

GPIB output:

3-87

AP-66

APPENDIX C
REMOTE MESSAGE CODING
Bus Signal Line(s) and
Coding That Asserts the
True Value of the Message

C
D NN
I ,D
I DRD A E S I R
Y a I
o AFA TOR F E
P s 0
Message Name e s 8 7 6 5 4 3 2 1 VDC N I Q C N
T

Mnemonic'
ACG
ATN
DAB
OAC
OAV
OCL
END
EOS
GET
GTL
lOY
IFC
LAG
LLO
MLA

addressed command group
M AC Y 0 0
attention
U UC X X X
(Notes 1, 9) M DO 0
0
data byte
8 7 6
. data accepted
U' HS X X X
data valid
U HS ·X X X
device clear
M UC Y 0 0
end
U ST X X X
end of string
(Notes 2, 9) M DO E E E
8 7 6
group execute trigger
M AC Y 0 o
M AC Y 0 0
go to local
identify
U UC X X X
interface clear
U UC X X X
listen address group
M AD Y 0 1
local lock out
M UC Y 0 0
my listen address
(Note 3)
MAOY01

o

MTA

my talk address

(Note 4)

M AD Y 1 0

MSA

my secondary address

(Note 5)

M SE Y 1 1

NUL
OSA
OTA
PCG
PPC
PPE

null byte
other secondary address
other talk address
primary command group
parallel poll configure
parall,el poll enable

(Note 6)

M
M
M
M
M
M

PPO

parallel poll disable

(Note 7)

M SE Y 1 1

PPR1
PPR2

parallel poll response 1
parallel poll response 2

(Note 10)

U ST X X X
U ST X X X

}

3-88

DO 0 0 0
SE (OSA =
AD (OTA =
- (PCG =
AC Y 0 0
SE Y 1 1

0 X XXXXXX
X X X X X XXX
0 0 0 0 0 XXX
5 4 3 2 1
X X X X X XXO
X X X X X 1XX
1 0 1 o 0 XXX
X X X X X XXX
E E E E E XXX
5 4 3 2 1
0 1 0 0 0 XXX
0 000 1 XXX
X X X X X XXX
X X X X X XXX
X X X X X XXX
1 000 1 XXX
L L L L L XXX
543 2 1
T T T T T XXX
543 2 1
S S S S S XXX
543 2 1
0 0 0 0 0 XXX
SCG A MSA)
TAG A MTA)
ACG V UCG V LAG
0 0 1 o 1 XXX
0 SPPPXXX
321
1 0 ODD XXX
4 321
X X X X 1 XXX
X X X 1 X XXX

1 X X X X
1 X X X X
0 X X X X
X
X
1
0
0

X
X
X
1
X

X
X
X
X
X

X
X
X
X
X

X
X
X
X
X

1
1
X
X
1
1
1

X
X
1
X
X
X
X

X
X
X
X
X
X
X

X
X
X
1
X
X
X

X
X
X
X
X
X
X

1 X X X X

1 X X X X
X X X X X

V TAG)
1 X X X X
1 X X X X
1 X X X X

1 1 X X X
1 1 X X X

intJ

AP-66

REMOTE MESSAGE CODING (Continued)
Bus Signal Line(s) and
Coding That Asserts the
True Value of the Message
T

Y
P
Mnemonic

Message Name e

PPR3
PPR4
PPR5
PPR6
PPR7
PPR8
PPU
REN
RFD
ROS
SCG
SOC
SPD
SPE
SRO
STS

parallel poll response 3
(Note 10)
parallel poll response 4
parallel poll response 5
parallel poll response 6
(Note 10)
parallel poll response 7
parallel poll response 8
parallel poll unconfigure
remote enable
ready for data
request service
(Note 9)
secondary command group
selected device clear
serial poll disable
serial poll enable
service request
status byte
(Notes 8, 9)

TCT
TAG
UCG
UNL
UNT

take control
talk address group
universal command group
unlisten
untalk

}
}

U
U
U
U
U
U

M
U
U
U

M
M
M
M
U

M
M

M
(Note 11)

..

M
M
M

C
I
a
s
s

D
I

D NN
I DRD A E S I R
0 AFA T 0 R F E
0
876 5 4 3 2 1 VDC N I Q C N

ST X
ST X
ST X
ST X
ST X
ST 1
UC y
UC X
HS.X
ST X
SE Y
AC Y
UC Y
UC Y
ST X
ST S
8
AC Y
AD Y
UC Y
AD Y
AD Y

X X X X 1 X
X X X 1 X X
X X 1 X X X
X 1 X X X X
1 XX X X X
X XX X X X
00101 0
X X X X X X
X XX X X X
1 X X X X X
1 1 X X X X
0 0 001 0
0 0 1 100
001100
XX X X X X
X S S S S S
6 5 4 3 2
0 0 o 1 o 0
1 0 X X XX
0 0 1 X X X
0 1- 1 1 1 1
1 o 1 1 1 1
..

X XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XOX
XXX
XXX
XXX
XXX
XXX
XXX
XXX

1
1
1
1
1
1
1
X
X
0
1
1
1
1
X
0

1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X

X X
X X
X X
X X
X X
XX
X X
X X
X X
X X
X X
X X
X X
X X
1 X
X X

XXX
XXX
XXX
XXX
XXX

1
1
1
1
1

X
X
X
X
X

X
X
X
X
X

X
X
X
X
X
1
X
X
X
X
0
1
0
X
S
1
1
X
X
1
1

X
X
X
X
X

X
X
X
X
X
X
X
1
X
X
X

X
X
X
X
X
X
X
X
X
X

The 1/0 coding on ATN when sent concurrent with multiline messages has been added to thiS revIsion for Interpretive convenience .

NOTES:
1. 01-0B specify the device dependent data bits.
2. El-EB specify the device dependent code used to indicate the E08 message.
3. Ll-L5 specify the device dependent bits of the device's
listen address.
4. Tl-T5 specify the device dependent bits of the device's
talk address.
5. 81-85 specify the device dependent bits of the device's
secondary address.
6. 8 specifies the sense of the PPR.

S

Response

o

0

1

1

PPR Message

P3

P2

P1

o

o

o

PPR1

1

1

1

PPR8

7. 01-04 specify don't-care bits that shall not be decoded
by the receiving device. It is recommended that all zeroes
be sent.
B. 81 -86, SB specify the device dependent status. (0107
is used for the RaS message.)
9. The source of the message on the ATN line is always
the C function, whereas the messages on the 010 and EOI
lines are enabled by the T function.
10. The source of the messages on the ATN and EOllines
is always the C function, whereas the source of the messages on the 010 lines is always the PP function.
11. This code is provided for system use, see 6.3.

Pl-P3 specify the PPR message to be sent when a parallel poll is executed.

3-89

Modem Products

4

APPLICATION
BRIEF

AB-24

May 1989

89024 Modem Customization
for V.23 Data Transmission

BRIAN D. WALSH
APPLICATIONS ENGINEER
INTEL CORPORATION

Order Number: 292058-001

4-1

AB-24

INTRODUCTION

V.23 Modem IC

This application brief will illustrate the steps involved
in customizing a modem application using the 89024
modem chip set. Specifically, it will show how one may
add V.23 capability to an 89024 modem design as embodied in the MEK II (Intel Modem Evaluation Kit)
running software version 3.2.

The TCM3105 (Ul02) is a CMOS V.23 modem in a
16-pin package that consumes only 40 mW. It requires
an external 4.4336 MHz crystal connected between pins
15 and 16 to derive timing. A resistor divider sets the
carrier detect threshold by adjusting the voltage at pin
10. Bias distortion may be minimized by adjusting the
voltage at pin 7. Pins 5, 13 and 12 together set the
various modes of operation. These pins are connected
to pins 6, 9 and 12 respectively of 74LS373 (U18) and
are controlled through bits 2, 3 and 4 and executing a
"STore" instruction to any even address of external
memory (since this is the only external memory to be
used). The modes of interest to us are:

GENERAL DESCRIPTION
This design consists of using the 89026 processor to
control a separate V.23 Data Pump IC (Texas Instruments TCM3105) to support V.23 modulation in addition to the currently supported V.22bis/V.22/V.21/
BeIl2121BeIl103.
The modem is placed in V.23 mode using the
"AT&A 1" command and is returned to normal operation with the "AT&AO" command. The originating
modem dials normally using "AT" commands and then
2 seconds after completion of dialing, the modem sends
75 bps V.23 carrier. The answering modem, upon detecting a ring signal, goes off hook and sends 1200 bps
V.23 carrier. The originate modem sends data at 75 bps
and receives data at 1200 bps, whilj! the answer modem
sends at 1200 bps and receives at 75 bps. Both respond
to "escape" at 1200 bps and command mode is always
at 1200/1200 bps. The V.23 transmit level is fixed.
Backward channel CCITT circuits -are not supported,
data is always transmitted from pin 2 and received at
pin 3.
This application brief d~es not address the issues of
V.2S calling tones or V.2S calling station identification.

HARDWARE DESCRIPTION
The MEK II is modified by adding a Texas Instru'ments TCM310S FSK Modem IC. This Modem chip
does not have an on-chip 4-wire to 2-wire hybrid circuit, so we use a dual op-amp MCI4S8 for this purpose.
In order to control the TCM310S we use 3 additional
outputs of the 74LS373 latch that is already used to
latch the /JS and AA signals from the microcontroller
address/data bus. A 74LSI57 2- to I-line data selector
is used to select the source of received data and the
source of "energy detect" signal to the microcontroller.

fF,

TCt.l310S pl~ 12-TXR2
CTCt.l310S pin 13-TXRl
pinS -TRS

~tTCt.l310S

76S43210
xxx 111 xx - Transmit Disabled
xxxOO lxx - TX 1200 bps. RX 75 bps (V.23 Answer mode)
xxxOl0xx -TX 75bps.RX 1200 bps (V.23 Originate mode)
292058-1·

74LS157 Data Selector
This IC is always enabled and the select signal is connected to the 6th output (bit 5) of the 74LS373 latch
(U18). "SToring" a "0" to bit 5 of the latch selects
"normal" mode of operation, while "SToring" a "I" to
bit 5 selects V.23 mode. During "normal" mode. Receive Data (RXD) is routed from the 89026 microcontroller to the DTE and Energy Detect (ED) is routed
from the 89027 AFE to the microcontroller. During
V.23 mode RXD goes from the TCM3105 to the DTE
and ED goes from the TCM3105 to the microcontroller. Transmit Data (TXD) is always connected from the
DTE to both the 89026 and the TCM3105.

MC1458 Dual Op-Amp
This IC is configured as an active hybrid circuit, converting the 4-wire transmit and receive signals to 2-wire
to drive the line transformer. The transmitted signal is
also summed, but since only one of the transmitters will
be active at a time, this will not be a problem. The
89027 has pin 10 tied low so as to disable the AFE's onchip hybrid.
A schematic diagram of these changes is shown in Fig.
ure I.'

4-2 .-

inter

AB-24

EXISTING MEK-II

V.23 ADDITIONS

18 ED

ED ..9'-.-....._ - - '

HYB 10

4Y 12
89027

3Y 9
89026

2Y 7

RXO 29

WR

TXD 27

TXD
RXD

292058-2

Figure 1. Schematic Diagram

4-3

intJ

AB-24

SOFTWARE DESCRIPTION
We choose the "&A" command as one that is not currently used by major "AT" compatible modem vendors. We
will use S23 bit 3 as the bit to indicate that V.23 mode has been selected, since this bit is unused in "AT" modems.
"&AI" will cause S23 bit 3 to be set to a "I" and &AO or just "&A" will cause it to be cleared. The modem software
will examine this bit to determine whether V.23 mode has been selected.
Note that source code will always be written in capital letters and that the assembler ignores the rest of a line after a
semi-colon (;). When giving modified source code I will usually "comment out" the original code by adding a semicolon to the beginning of the line. This is an excellent practice to facilitate the documentation of changes.
By convention we name the source files: nmxxx.SRC (where n.m is the software version and xxx is the generic file
name). Since we are using software version 3.2 the files that we will be changing are:
32AAD.SRC
32CMD.SRC
32CPM.SRC
32HND.SRC
32DATA.SRC

register assignment definitions ($INCLUDEd with all source files)
Command Decoder
Call Progress Monitor routines
Handshake routines
Data Mode routines

Decoding AT&Al Command and Setting the S23 Bit
All of these changes will be done to the 32CMD.SRC file.
Since many commands simply modify S-register bits, we can take advantage of the "COMMON~EOI5TE~
OPERATIONS:" code by adding our command to the necessary tables and allowing it to be decoded as a registermodifying command.
Add as the last entry in TABLE_I:

I

DCB

(3· 32) + (523-50)

This will tell the common routine that this command affects bit 3 of 523. The table is set up so that it only occupies
one byte per entry, with the bit number in the upper 3 bits and the register number in the lower 5 bits.
Add the command to the command list and the command vector table:

AND_CMD5:

DCB
DCB
DCB

DCB
DCB
DeB

·CJLPR5DG'
"MXFWZT',
"MXAFWZT',

o

o

was like this
added &A command betw X and F

AND_G_CMD-Gl, AND_M_CMD-Gl, AND_X_CMD-Gl, AND_F_CMD-G2
AND_G_CMD-Gl, AND_M_CMD-Gl, AND_X_CMD-Gl, AND_A_CMD-Gl
AND_F_CMD-G2

The command vector table is the address offset of the command label from that of the first command (01 EQU ~
CMD). In the interests of saving space this offset table is only I byte per entry and so it has to be split into 2 groups
as the range of addresses of command labels is more than 255 bytes. When modifying command code it is worth
checking the list file to make sure that the CMDJU_TBL: entries do not get bigger than OFFH and wrap around
through 0, causing those commands to branch to the wrong address.

4-4

inter

AB·24

Fix the branch vector calculator and the dial command offset calculator because the Ist group of commands are now
33 instead of 32:

GENERATE_BRANCH_VECTOR:
ADD TEMP_CMD_3, #G1
CMPB TEMP_CMD_2, #32
CMPB TEMP_CMD_2, #33
D_R_CMD:
SUBB
SUBB

ADD OFFSET TO 1ST CMD GROUP
FIRST 32 CMDS FIT IN
FIRST 33 CMDSFIT IN

CPM_CONTROL, TEMP_CMD_2, #36
CPM_CONTROL, TEMP_CMD_2, #37

Add the command label with the rest of the register modifying commands:

LCMD:
AND_A_CMD:
AND_C_CMD:

added &A command for V.23 operation

Updating the Output Pins to Control the TCM3105 and Data Selector
The 10_CONTROL: section of code in file 32CMD.SRC runs all the time and could be considered the "background routine". This is where the RS232 leads are updated, the health of the other routines is checked and the
74LS373 latch (UIS) is written and is thus an appropriate place for the TCM3105 chip and the Data Selector (Data
Mux) to be updated.

4-5

inter

AB-24

Add the following code after END_IS_UPDATE:

V_23_UPDATE:
ANDB TEMP_CMD_l, #llOlllllB
ORB TEMP_CMD_l, #OOOlllOOB
JBC S23, 3, END_V_23_UPDATE

MUX TO NON-V.23 POSN
SET V.23 CHIP OFF
JMP IF NOT IN V.23 MODE

JBC CNTRL_C, 1, END_V_23_UPDATE
ANDB TEMP_CMD_l, #lllOOlllB
ORB TEMP_CMD_l, #OOOOOIOOB

JMP IF NOT IN HND OR DATA MODE
SET V.23 CHIP TO ANS MODE

JBC S14, 7, NOT_ORIG_MODE
ANDB TEMP_CMD_l, #lllOlOllB
ORB TEMP_CMD_l, #OOOOlOOOB

JMP IF S REG SET TO ANS MODE
SET V.23 CHIP TO ORIG MODE

NOT_ORIG_MODE:
JBC CNTRL_C, 0, END_V_23_UPDATE
JBS CNTRL_C, 2, END_V_23_UPDATE
ORB TEMP_CMD_l, #OOlOOOOOB

JMP IF NOT IN DATA MODE
JMP IF CMD FUNCTS ENABLED
DATA MODE, SO MUX TO V.23 POSN

The next instruction in the source code STores the contents of TEMP_CMD_I to PORT3, and so updates the
Data Mux.
In order to ensure that the Data Mux gets set before the "OK" message is sent when entering the on-line escape state
(response to "+ + + "), add a line of code after the three "ORB" instructions:

VALID_ESCAPE_SEQUENCE:
ORB CNTRL_F, #OOOlOOOOB
ORB CNTRL_C, #OOOOOIOOB
ORB MSG_RQST, #OOlOOOOOB
JBS S23, 3, ESCAPE_DETECT_END
; IO_CONTROL FOR MUX SETUP

ENABLE ESCAPE STATE
ENABLE CMD FUNCTIONS
SEND "OK" MESSAGE WITH MSG RQST
TRICK TO FORCE 1 MORE PASS THRU
BEFORE GOING TO COMMAND DECODER

4-6

inter

AB-24

After a dial command is executed by the Command routine, it will activate the Call Progress routines.
The V.23 Call Progress Monitor Routines
The 32CPM.SRC routines check for call progress signals on the phone line and also for answer tone from the remote
answering modem. Since a V.23 modem will answer with a 1300 Hz tone (1200 bps mark frequency), the AFE
receive filter must be set to V.22 answer mode so as to pass this frequency to the energy detect circuitry.
Add three lines of code at the label

SET~NSWE~CONT:

SET_ANSWER_CONT:
ANDB CPM_FLAG, #lllOllllB ; FLAG ANSWER PROCESSING FOR HOUSEKEEPING
JBC S23, 3, SET_ANSWER_CONT_1
LDB AFE_BYTE3, #OlOOOOOOB
SET_ANSWER_CONT_1:

IF V23 MODE THEN
SET FILTER TO QAM ANS FOR
1300Hz CARRIER DETECTION

SJMP SIGNAL_MONITOR_INIT
The CPM routines will hand over control to the Handshake routines which we need to modify for V.23 handshake.
The V.23 Handshake Routines
The Handshake mode 32HND.SRC is entered for the first time after successful completion of the Call Progress
routines. The first time that HANDSHAKE_MODE: is called, it goes through the Initialization code before the
main routine is executed, thereafter the Initialization is skipped. The Main routine is entered at a rate of 600 times
per second or more and consists of checking for Energy Detect and then branching to the routine address saved in
T~TN_ADDR. The logical flow of the handshaking is controlled by changing the contents of T~RTN_
ADDR to the address of the routine to be executed the next time Handshake is called.

292058-3

Figure 2
4-7

AB·24

The Initialization required for V.23 consists of starting the S7 wait-for-carrier timer, starting a 2 second timer and
loading a return address for the next time the routine executes. The following lines of source code are added
(identified by "V23" at the start of the comment field) to the Handshake Initialization:

HANDSHAKE_INIT :
ANDB MODE_STATUS, #lOllllllB
JBC S23, 3, NOT_V23_INIT
V23_HND_INIT:
ADDB S7_TIMER, TIME_BASE_SECOND, S7
ADDB TX_TIMER, TIME_BASE_lOOMS, #20D
LD
TX_RTN_ADDR,
#V23_HND_WAIT
SJMP HND_INIT_END

CLEAR INIT FLAG
V23
V23
V23
V23 INIT S7 DCD TIMER
V23 INIT 2 SEC TIMER
V23
V23
V23
V23

After the initialization code is executed once, the software will keep branching to V23_HND_WAIT: until the
2-second timer has expired, then it will initiate a "CONNECT" message. While the Connect message is being sent,
the software will branch to V23_HND_MESSAGE:, then it will set up the Data mode and thereafter the Data
Mode will be called instead of the Handshake mode.

V23_HND_WAIT:
V23
CMPB TIME_BASE_lOOMS, TX_TIMER
V23 TIMER EXPIRED YET?
JNE V23_HND_END
, V23
V23_HND_MESSAGE_INIT:
V23
LDB MESSAGE_REQUEST, #OOlOOOOlB
V23 START CONNECT MESSAGE
LD
TX_RTN_ADDR,
#V23_HND_MESSAGE
V23
SJMP V23_HND_END
V23
V23
V23_HND_MESSAGE:
V23
JBS MESSAGE_REQUEST, 5, V23_HND_END
V23 MESSAGE SENT YET?
V23_HND_MESSAGE_END:
V23
V23
ANDB COPY_PORT4, #lOllllllB
V23 DCD HIGH AFTER CONNECT
V23_SET_UP_DATA_MODE:
V23
This is where we need to set up for going to data mode
ORB
CNTRL_C, #OOOOOOllB
V23 GO TO DATA ~ODE
ANDB AFE_BYTE4, #OOllllllB
V23 TXMITTER OFF, AFE OFF
CLRB DM_FLAGS
V23 CLEAR FLAGS FOR DM
ORB
MODE_STATUS, #lOOOOOOOB
V23 INIT DATA MODE
V23_HND_END:
V23
LJMP HANDSHAKE_MODE_END
V23
V23

4-8

intJ

AB-24

V.23 Data Mode
The modifications required in the Data Mode consist of checking for V23 mode and skipping past:
Initialization
Send space disconnect (twice)
Receive space disconnect
Loss of carrier disconnect
Retrain request
Test mode

DATA_MODE_INIT :
; DM FLAGS ALREADY CLEARED IN HANDSHAKE MODE
ANDB MODE_STATUS,#7FH
CLEAR INITIALIZE FLAG
JBS S23, 3, DATA_MODE_INIT_END
; IF V23 THEN INIT DONE
DISCONNECT_INIT:
ANDB DM_FLAGS, #llllllOlB
JBS S23, 3, HANG_UP

CLEAR DISCONNECT INIT FLAG
V23 FORGET SPACE DISCONNECT

SEND_SPACE:
JBC S21, 7, HANG_UP
JBS S23, 3, HANG_UP

IF BREAK_DISCONNECT DISABLED
V23 FORGET BREAK

CHECK_DISCONNECT:
CHECK_BREAK:
JBS S23, 3, SET_BREAK_TIME

CHECK FOR LONG SPACE DISC
V23 FORGET BREAK

CHECK_CARRIER_LOSS:
JBS PORTO, 7, CHECK_CARRIER_LOSS_END ; SKIP IF ED IS HIGH
ORB DM_FLAGS, #OlOOOOOOB
; SET CDLOSS FLAG
ADDB EDOFF_TIME,TIME_BASE_IOOMS,SlO ; CDOFF THRESHOLD IN REGISTER
INCB EDOFF_TIME
PUT AN OFFSET IN TIME FOR PROPER
OPERATION DURING TM EXIT
JBS S23, 3, CARRIER_LOSS_END
; ALL DONE IF V23 MODE
QAM_RETRAIN:
JBS S23, 3, SJMP_CHECK_TEST_MODE

SKIP RETRAIN IF V23 MODE

CHECK_S16_STATUS:
EXAMINE S16 REGISTER FOR ANY TEST MODES AND SET FLAG
JBS S23, 3, CHECK_S16_STATUS_END
; SKIP RETRAIN IF V23 MODE

4-9

inter

AB·24

Assembling the Source Files
The source files can be assembled by issuing the following commands at the DOS prompt:

ASM96
ASM96
ASM96
ASM96

32CMD.SRC
32CPM.SRC
32HND.SRC
32DATA.SRC

Linking the Object Files
Link the object files by issuing the following command at the DOS prompt:

RL96 32HND.OBJ, 32INIT.OBJ, 32CMD.OBJ, 32CPM.OBJ, 32DATA.OBJ,
32S0FT.OBJ, 32HSI.OBJ, 32HSO.OBJ, 32RX.OBJ TO 32ATR
Programming the EPROMs
After the code has been linked and located, the code must be split into low and high byte segments for programming
into EPROMS. The following IPPS session illustrates that process (IPPS prompts are not shown):
'

IPPS
I 80

FORMAT 32ATR
3
2
1

o to

32ATR.LO
1 to 32ATR.HI


invoke IPPS
initialize file format
filename resulting from linking
logical unit is byte
input file is in wordS (2 bytes)
output file is in bytes
low order bytes to one file
high order bytes to another
press ftenterft to exit formatting
the following assumes that an
INTEL PiUP 20lA programmer is
connected to the PC

TYPE
27128
COPY 32ATR.LO TO PROM
COPY 32ATR.HI TO PROM
EX

display available EPROM types,
specify EPROM type
insert blank EPROM into programmer
copy low byte file to' prom
insert blank EPROM into programmer
copy low byte file to prom
exit IPPS

Custom routines can now be tested by placing EPROMS into target hardware.

REFERENCES
1. "FSK Modems: TCM310S Designers Information" from Telecommunications Circuits Data Book, 1986. By
Texas Instruments.
'
2. MEKII 89024 Enhanced Modem Evaluation Kit Users Manual, 1987. By Intel Corp.
3. 89024 Modem Reference Manual, 1987. By Intel Corp.
4. Developing MCS-96 Applications Using the SBE-96. Application Note AP-273 (Order Number 280249-001). By
Intel Corp.

4-10

ISDN Products

5

APPLICATION
NOTE

AP-282

January 1989

29C53 Transceiver Line
Interfacing

JAGTINDER

s.

BOLARIA

TELECOM PRODUCT MARKETING

Order Number: 270209-003
5-1

inter

AP-282

INTRODUCTION
TERMINAL

Presently, the majority of the transmission from the
telephone to the Central Switching system is analog.
For this purpose the circuitry interfacing to the twisted
pair line is optimized to operate between 300 and 3400
Hz. The essential line interface functions consist of isolation, over voltage protection, signaling, power feeding
and a ringing signal insertion. With the advent of ISDN
(Integrated Services Digital Network) these functions
have to be reassessed.

-

SWITCH

~IIE

ailE

ISDN is implement~d with digital transmission from
the subscriber to the switch, which in turn offers the
user various data services in addition to the voice service. CCITT has various recommendations' for the implementation of the ISDN network. Of these, 1.430 details the basic rate access i.e. the physical communications between a terminal and the first level of switching.
For 1.430, Intel offers a transceiver which is capable of
operating at either end of the loop, namely the 29C53.

270209-1

Figure 1. Voltage Feeding

POWER FEEDING
Figure 1 shows the CCITT recommended technique of
phantom power feeding as described in section 9 of
1.430. The current splits evenly between the two secondary windings. This in turn produces equal and opposite fluxes in the transformer, that cancel each other
out, thus preventing the core from saturating. The
equality of the fluxes in the secondary will depend on
the longitudinal balance of the transformer and the
transmission line.
'

The 29C53 is a four wire (two for transmit and two for
receive) transceiver operating over the "S" loop. The
data transmitted by the 29C53 at the switch and the
terminal is at a rate of 192 kb/s; the effective data
throughput is 144 kb/s. This data consists of two bearer
channels of 64 kb/s each (Bl + B2) and a 16 kb/s D
channel. The 29C53, additionally, incorporates some
protocol processing for the D channel. This transceiver
has four interfaces, namely the microprocessor port, a
general purpose I/O port, the SLD port and the "S"
loop interface. It is the loop interface requirements that
are addressed by this application note.

The scheme shown on Figure 1 may be wasteful of
power when feeding short lines. One way around this
would be to have a constant current feed, which will
make the power consumption'independent of the length
of li~e. Figure 2 shows such an implementation.

This note will analyze the line interface requirement at
both the line card and the te~inal, and will offer general implementations. These implementations will address power feeding, the protection circuitry, the line
transformers and power extraction. Throughout this
brief, the approach has been to present various alternate concepts which may assist the designer in addressing a specific application.
'

-

TERMINAL

SWITCH

~IIE

ailE

LINE INTERFACE
Both at the line card and the terminal, there is a need to
provide isolation for the circuitry from the line itself.
As well as isolation, it is also necessary to protect the
equipment from any overvoltage conditions on the line.
Additionally the system may be designed to provide
phantom power feeding i.e. the switching system delivers power to the terminal over the "S" loop. Unlike its
analog counter part the digital line card does not need
to send a ringing signal owing to the fact that all signaling is accommodated via the D channel.

Figure 2. Current Feeding

5-2

270209-2

intJ

Ap·282

One way of reducing the power dissipation over the
loop is to provide a variable voltage source, instead of
the traditional fixed voltage. This can be accomplished
by using a DC to DC converter, or a switching regulator. The feedback circuit of the switching regulator can
be used to ensure that the regulator provides just
enough voltage to maintain a pre-defined feed current
down any length of line. The DC to DC converter can
have a built in threshold detector, which would be used
to release the line in case excessive currents are being
drawn.

gether through the cable plant and a switching network. The cable plant consists of multiple pairs of
transmission lines, either suspended on poles, or buried
in the earth. In either case, transient energy can be coupled from lightning (or other electromagnetic events)
and conducted to the switch or the terminal. The other
major source of transient energy is the commercial AC
power system, where high currents that accompany
faults can induce overvoltage in the lines, or the power
lines can fall and make contact with the telephone lines.
The latter is sometimes referred to as a mains or power
cross.

In the event of mains power loss, it is often required to
maintain a minimal voice service powered off the line.
Figure 3 shows the block diagram of a digital telephone, illustrating the necessary components required
to maintain a voice service.

29C48

'--~:---r-

It is gen~rally agreed, as shown in Figure 4, that two or
more levels of protection are required. The primary
protector is usually placed on the line at a distance
greater than 2Sm from the line card. The impedance of
the line will ensure that the primary protector will operate first and the secondary protector will not be exposed to the full surge. If the primary protector is to be
placed closer to the secondary, then a small resistor can
be inserted in series with the line between the primary
and the secondary protector (1). A SO 3W resistor or a
positive temperature coefficient resistor may be used.
During a surge, the voltage drop across the resistor will
increase allowing the voltage across the primary protector to build up thus driving it to conduction.

I[
I[

The primary protection can be a gas discharge tube,
such as the General Instrument three terminal
PMT3-(310). These devices consist of spaced metallic
gaps enclosed in a combination of gases at low pressure.
In the event of a surge, the gap breaks down, diverting
the transient and thus rerouting the energy. These de- .
vices can be operated a number of times and present a
capacitance of less than S pF. Since the templates in
Figures 10 and II of 1.430 specify a low output capacitance for the terminal and the network terminator, the
low output capacitance feature of the gas discharge
tube makes it ideal for ISDN i.e. it will have a minimal
effect on the line drivers.

SOCS1

270209-3

Figure 3. Digital Telephone

The 80CSI is a low power microcontroller while the
29C48 is an SLD compatible combo (codec and filter).
The gains through the 29C48 can be set externally or
programmed by the microcontroller via the SLD interface. The 29C48 is designed to allow insertion of sidetone and DTMF (dual tone multi-frequency); both
these features are presently used to provide feedback to
the user.

The secondary protection can be provided by Schottky
diodes chosen for the low voltage drop and capacitance
across them. The diodes are placed between the power
supplies and the loop interface pins on the 29CS3, thus
forming a diode bridge across the line. This will ensure
that the voltage on these pins does not exceed the power supplies by more than approximately 300 mY, thus
fulfilling the specification that the voltage on any pin

PROTECTION
Next, let us examine the question of protection. A telecommunication system comprises subscribers linked to-

5-3

AP-282

-

-

TERMINAL

SWITCH

,..-JWrl--+--.... LX+

'~~;';-310

~

V220MA49
- 4CRL2

Figure 7 shows these circuits. The pulse shape is then
, optimized by considering the transient response of the
equivalent circuits.

Commercially available pulse transformers exist which
are compatible with the 29C53. Some examples are given in Table 1. Most manufacturers will modify their
design to meet the requirements of a particular application.

The pulse response of the transformer is characterized
by a finite rise time, a decaying top period and finite fall
time as depicted in Figure 7d. The fastest rise time that

RL - Load impedance
c - Shunt capacitance
L - Leakage inductance
Lp - Primary inductance

0) RISE PERIOD

~

--1J

b)TOP AND 'DECAY PERIOD
d) PULSE RESPONSE

c) FALL PERIOD
270209-8

Figure 7. (a) Equivalent Circuits for Rise Period
(b) Top and Decay Period (c) Fall Period (d) The Pulse Response

5-7

inter

Ap·282

TABLE 1. Manufacturers of Pulse Transformers
Location

Winding Ratio

Part No.

AlE Magnetics

Manufacturer

St. Petersburg, FL
(813) 347-2181

1.8:1
2.5:1

325-0228
325-0172

Schott Corporation

Nashville, TN
(615) 889-8800

·1.8:1
2.5:1

11207
11124

CTM Magnetics

Tempe,AZ
(602) 967-9447

1.8:1
2.5:1

22087
25585

Pulse Engineering

San Diego, CA
(619) 268-2400

1.8:1
2.5:1

64994
64996

A DC to DC converter is ,required to convert the line
voltage to 5V for the local circuitry. In order to obtain
the lowest losses in the conversion process, it is necessary to use a high efficiency regulator, specifically, a
switched mode .regulator. Basically, th~re are three
types of switched mode power supplies, the forward,
the push pull and the flyback converter (3). This section is devoted to the flyback implementation of a DC
to DC converter. The flyback is the most suitable converter lor this application, as it provides the highest
achievable efficiency and the simplest drive circuitry.
Figure 9 shows a block diagram of a flyback converter.

POWER EXTRACTION
The same transformer can be used at both the line card
and the terminal, and the same ,protection scheme can
be used at both ends of the loop. The need now arises to
provide power to the terminal. There are a number of
ways of providing power to the terminal, for instance a
secondary cell can be used as battery back-up in conjunction with a main supply. There is also some scope
for trickle charging secondary cells from the line or
from a small solar cell array, but the drawback with
secondary cells tends to be their short life span. This
disadvantage can be offset by using special purpose primary cells as a back-up supply, these do not need any
charging circuitry and can be expected to have life expectancy twice that of the secondary cells. Finally, the
power can be fed from the switch, in which case a regulator is required at the terminal to extract the power off
the line. Figure 8 illustrates this approach.

TERMINAL

OUT

LINE

>:*

SWITCH

270209-10

Figure 9. Flyback Converter

270209-9

Figure 8. Power, Extraction

5-8

l
~

c
--.
111

?
c

..

.

»"tI

, 0
co 0
01

I\)
CC)
I\)

g
fl
:::I

~

it-.
R9
51Ktl

270209-13

intJ

AP-282

current. The current through the regulating diode is
proportional to the voltage difference between the output and the reference. This device is available from
Texas Instruments and Motorola amongst others. Figure II illustrates its function.

In the flyback inductor, energy is inductively stored
during the switch on period, and then passed to the
load during the switch off, or the flyback period. During the switch on period, the output diode does not
conduct so that the energy in the choke (although appearing as a transformer, this element will be referred
to as the choke in accordance with its function) builds
up with rising current. While the switch is off the choke
voltage reverses in polarity causing the output diode to
conduct whereupon the inductive energy is discharged
into the output capacitor to form a DC voltage. Regulation is achieved by modulating the oscillator duty cycle,
which effectively varies the switch on/off periods. In
Figure 9 the diode bridge ensures the correct polarity
for the converter while the opto-isolator completes the
input to output isolation.

.....
...
RIO
VOUT
TL431

R9

27020S-11

Figure 11. Regulator

Figure 10 shows a discrete circuit implementation of a
DC to DC converter. This circuit was designed to regulate a 5V output for 20-60V input voltage. This implementation provides a maximum power of at least 450
m W. The DC to DC converter consists of an oscillator,
a pulse width modulator incorporating an error amplifier and isolating stage, the start up circuitry and the
flyback converter. When T5 is on, the choke stores energy and reverse biases diodes D8, D9 and D 10. While
T5 is off, the choke voltage is negative, hence diodes
D8, 9 and 10 are all forward biased and thus build a
DC voltage on their respective capacitors. Note that
due to the reverse winding technique, the voltage in the
output windings are opposite in polarity to the switch
winding. The 5V output is regulated by comparing it to
a reference voltage, the error in the comparison is then
used to modify the transistor T5 on time in such a way
so as to keep the 5V output constant.

For the regulator diode, the output voltage is given by:
Vout = (1 + R10 IRs) Vref
where Vref is typically 2.5V.
If R10 = Rs
then Vout = 5V

The current through the regulating diode will increase
or decrease with a respective change in the output voltage. This change in current is coupled to the output of
the oscillator through the opto-isolator. The opto-isolator used is a Hewlett Packard 6N139, which has Darlington transistor stage providing high current gain that
results in a lower power dissipation in the opto-isolator.
The current through the isolator differentiates the output of the oscillator through capacitor C3. This differentiated signal is then squared off to define the switching transistor T5 on period. T5 is an IRFDllO MOSFET and is available from International Rectifier. The
isolator current and hence the output voltage control
the amount of differentiation or the transistor T5 on
period as illustrated in Figure 12. Thus regulation is
achieved, as the on period is reduced with increasing
'
output voltage and vice versa.

The diode bridge DI-D4 ensures a certain polarity of
the DC voltage for th.e converter, this is necessary in
case the network uses polarity reversal for signaling.
The decoupling capacitor CI serves a secondary function of bypassing any induced surge current. One half
of the Schmitt NAND gate CD4093 is used to form a
25 KHz oscillator.
At the output, the opto-isolator in conjunction with the
regulating diode TIA31 is used to generate an error

OSCILLATOR OUTPUT

Jl..J -

~

-

Figure 12. Pulse Width Modulation

5-10

-

~

a b c '

TO T5

27020S-12

AP-282

The two transistors T2 and T3 provide a low source
impedance driving stage for the switching transistor.
The fast current sinking and sourcing will ensure fast
switching of transistor T5.

The resistor R6 and transistor T4 provide current overload protection. Transistor T4 will conduct when the
voltage across R6 exceed 0.6V or conversely, the current through it is greater than 150 mAo With T4 conducting, the drive to the MOSFET is nulled by the
associated NAND gate.

At full load, the incomplete energy transfer mode exhibits a lower peak switching transistor current, while
the complete mode at lower power assures a smaller
core. The inductance required to achieve this is 6.5 mH
for the switch winding. The core used was an
RM6CA400-3B7. The number of turns required to
achieve this inductance is 130 and for a 20-60V line
voltage, 50 turns are required for a + 5V output, hence
use 50 turns for the - 5V too. The self bias winding uses
70 turns. The transformer was wound with 130 turns of
34AWG, followed by 50 bifilar turns of 32AWG and
finished off with 70 turns of 32AWG. The dot scheme
in Figure 10 should be adhered to. The bobbin is then
immersed in varnish such as the Dolph's BC356 to dispel any moisture and to provide a protective coating.
Alternatively, a commercially available DC to DC converter transformer such as the 326-0533 can be purchased from AlE Magnetics.

The transformer choke is a three winding transformer
consisting of the switching winding, the output winding, which is split for the + 5V and - 5V and the selfbias winding. The transformer is designed for complete
energy transfer under no load conditions and incomplete energy transfer under full load conditions. Figure
13 shows the wave forms of the two modes.
.

At start up, the converter is powered by the linear regulator OS, RI and TI, which sets the power supply at
5.3V. After start up the self bias winding forces the
voltage on C4 to be between 7 and 15 volts, which will
back bias diode 06, thus turning off the linear regulator. Under this condition the power supply provides a
selfbias voltage to keep it running, while little power is

The input capacitance of the MOSFET IRFDIIO is a
maximum of 200 pF. Without the buffer stage the
MOSFET will stay in the linear region longer before
saturating, thus resulting in 'a slower switching speed.
The slow switching in tum will result in a lower overall
efficiency for the converter.

TS DRAIN VOLTAGE

LfLJ

TS DRAIN-SOURCE
A
_
CURRENT - - / L--....../"

(0)

270209-14

Figure 13. (a) Current Voltage Waveforms for Complete Energy Transfer
(b) Waveforms for Incomplete Energy Transfer

. 5-11

inter

AP-282

GATE VOLTAGE
DRAIN VOLTAGE

5V SECONDARY
CURRENT
100 MAIDV
270209-15

GATE VOLTAGE
DRAIN VOLTAGE

5VPRIMARY
CURRENT
50 MAlOY
270209-16

Figure 14. Converter Oscillograms

dissipated in the start up regulator. Transistor TI is selected so that the base-collector can sustain the high
voltage stress when it is off. The - 5V supply will only
be regulated if the load on that winding is the same as
that on the + 5V winding. If this is not possible, it may
be necessary to use a linear post regulator to obtain a
regulated - 5V supply.

placed as close to the gate lead as possible. These precautions will avoid undesired oscillations in the MOSFET. The output stage uses Schottky diode and low
ESR capacitors to reduce. power dissipation. In th~
event of any undesired EMI radiation the transformer
can be placed in an electromagnetic container and the
converter can.be enclosed in a copper container.

Figure 14 shows the volt-current oscillograms for a 30V
line voltage and 400 mW output power. This shows the
flyback converter working in the incomplete energy
transfer mode. The results obtained in the lab gave fin
overall efficiency of better than 67% and a power supply ripple of less than 25 mV. The no load power consumption was less than 50 mW. Regulation of the out.
put voltage was better than 150 mY.

Ilf

/

The design ~as wire wrapped to illustrate the concept
of power extraction and can of course, be optimized for
better performance. Special care should be paid to the
layout; Figure 15 shows good layout principles. Use
star ground connections to avoid current loops in the
ground.

MAGNETIC rlELDS
DUE TO FORWARD
AND RETURN
CURRENTS CANCEL

All lead lengths going to the switching MOSFET
should be minimized and in particular the gate lead.
The resistor in series with the MOSFET should be

270209-17

Figure 15. Good Layout Principles
5-12

intJ

AP-282

When there is power, the two MOSFETS will be on
and appear as a small on resistance, which has to be
included in the line transformer design analysis. When
there is no power, the MOSFETS appear as back to
back diodes, thus stopping any AC flow. The VN0300
MOSFETS manufactured by Siliconix may be used,
when on they present a 1.2n resistance each. Note that
in order to ensure that the MOSFETS conduct it is
necessary to have a IOV supply in the system. If this is
not possible the MOSFETS can be replaced by a Reed
relay which presents a lower on resistance and capacitance but has the disadvantage of consuming more
power. A low power relay could not be located hence a
vendor was requested to customize one. Figure 17
shows the isolation technique using the Wabash
1992-2-1 25 mW relay which will operate at 3.8V and
release at 0.5V.

POWER FAILURE CONSIDERATIONS
Without power the line interface pins of the 29C53 appear as diode drops across the line. This means that the
transmitter of the Network Terminator and the powered on terminals in a multidrop configuration will be
terminated by a diode instead of the usual 50n. In the
event of a failure, it therefore becomes necessary to isolate the offending terminal from the line. This can be
done by providing a switch in the transmit path that is
normally closed and opens when no power is applied.

L X + I - - - - -.....
TRANSMIT

E

2.9C53

LX-

LX+

1-------...
I
I

1-_ _ _ _-6'
2.9C53

LR+ t--.JVV\r--....

5V

II

LR-I--~~=::.....r

LXLR+

270209-18

~i

C

I

Figure 16. Isolation of Equipment In
Case of Power Failure

c

In the receive path, it is only necessary to increase the
impedance seen by the line. One way to implement this
principle is to use a MOSFET bilateral switch in the
transmit path and to place series resistors in the receive
path, such that the impedance seen by the line is greater
than 25oon. Figure 16 illustrates this approach. A
noteworthy point is that the series resistors in the receive path not only provide terminal isolation in case of
failure but also protect the terminal from current
surges.

LR-I-----270209-19

Figure 17. Power Failure Isolation

5-13

intJ

AP-282

The protection circuits and the transformer, however,
can only be provided in discrete form at the present
time. The concepts presented in the protection section
emphasized low capacitance and maximum protection.
The section took an overkill approach and as ,such a
subset of the discussed ideas should suffice most applications. The transformer designed pointed out the relevant parameters to consider and can be used as it is or
modified to the particular application. Of course the
ISDN transformer is also commercially available.

CONCLUSION
Specific implementations have been provided for the
general aspects of line interfacing at both the line card
and the terminal end. These solutions can be taken as
they are and placed in the particular application or
used to aid a system design.
The fixed voltage or constant current feed are both simpler and more economical to realize in discrete form;
however the constant current variable voltage scheme
may be more suitable in an integrated form. The power
converter discussed was based on a low cost simple implementation and it is certainly possible to optimize it
to obtain conversion efficiencies in the 75% range. As
an alternative to discrete implementations, a low power
switch mode power supply is commercially available
from Fairchild and Motorola, to name two.

REFERENCES
1. Protecting against surge voltages in short and long
branch circuits. By Shamiwaz M. Khan, Communications Systems Equipment Design, December 1984
2. Transformers for electronic circuits. By Nathan R.
Grossner, McGraw Hill
'3. Design of solid state power supplies. By Eugene R.
Hnatek, Von Nostrand Reinhold Company

5-14

APPLICATION

AP-400

BRIEF

September 1989

ISDN Applications with
29C53 and 80188

HERBERT WEBER
TELECOM OPERATIONS

Order Number: 270247-004

5-15

intJ

AB-400

TERMINAL ADAPTOR (TA)
A terminal adaptor, or "TA", is the link between existing non-ISDN equipment like terminals; facsimile,
printers and the ISDN network. The function of this
application is to effectively replace equipment such as a
modem. Usually provided as a separate box, it processes RS232 or X.21 data and places it on the 4 wire'S'
loop. No change at the terminal is 'required to make it
ISDN compatible.

• Upper portion of link access procedure (CCITT
1.440) handling:
- Multiple logic channels
- Sequence control
- Error correction (retransmission)
, -, Flow control

The design is based on a 29C53 transceiver for the
ISDN connection and an 80188 microprocessor in combination with an 82530 communications controller for
the data connection. Benefits of the application are:
• Data rates up to 19.2 Kb/s using an RS232 interface
or up to 48 Kb/s using an X.21 interface.
• Compact design and low cost.
• Virtually error free transmission.

EPLD
• Interface conversion, serial to/from SLD
• B-channel assignment

29C53
• Physicallevei interface (CCITT 1.430) ,
• Lower portion of the link access procedure:
- Zero insertion/deletion
- CRC generation and checking
- Flag appending and detection

Link Setup
The user sets up a call in the same manner as a Hayes'
modem user does, i.e. a command is transferred to the
adaptor via the RS232 interface. The command takes
the form of an ASCII string in which the first 2 characters are "AT".
The 80188 accepts the command and begins the call
setup procedure by communicating the call's destination to the NT (or CO). This is achieved by passing call
setup messages to a link level protocol, which is passed
to the NT over the physical level (S bus). The partitioning of the tasks is as follows:

• D-channel message buffering
The 80188 passes the information for the D-channel
.messages via the parallel bus into the FIFO's of the
29C53.
The NT grants a B-channel (if available) to the TA and
the channel is now ready for data transfer.

Data Transfer
An indication is given to the user's terminal via the
RS232 or X.21 port that communication may commence. Any subsequent data, from the terminal, is
treated as follows:

82530
Full duplex, dual channel serial communications controller capable of working in asynchronous, bit or byte
synchronous modes. The 82530 receives commands
from the terminal's RS232 or X.21 interface and passes
them on to the 80188.

Data from the terminal passes via the 82530 to RAM
via one of the 80188 DMA channels.
The 80188 fetches the data from RAM, depacketizes
and packetizes it before sending it back to the 82530
where a protective HDLC protocol is added.

80188
After having received the dialing information from the
keyboard, the 80188 sets up the call via the 29C53 Dchannel by sending the appropriate CCITT message up
the link.
• Call setup message generation (CCITT 1.451).

From the 82530 the data reaches the EPLD to be inserted into the Bl or B2 channel on the SLD bus. The
29C53 sends it out over the "S" interface.

'Hayes is a registered trademark of Hayes Microcomputer
Products. Inc.

5-16

intJ

AB-400

SLD

P3/4

AID
.II

RS 232C
300 - 19 200 blt/s

oR
X.21
600 - 48 000 blt/s

~

:nJ.

~
HDLC

I

29C53

..

CHANNEL
SELECT

c::::

4W 'S' Interface

I~

CS

INT1
PCSI

r-

INTO

82530
SEL

....

D/C ....

~

.

~

,

~

a-

PCSS

.

....

iAPX188
AID

UCS
LCS

...

,.

...

,.

AID

AID

EPROM

RAM
270247-1

Figure 1. Terminal Adaptor

5-17

intJ

AB-400

ISDN PHONE WITH BUILT IN TERMINAL ADAPTOR (TA)
Figure 2 shows the concept of an ISDN phone with
hookup to standard sync/async terminals. No change
at the terminal is required to make it ISDN compatible.
The design is based on a 29C53 transceiver for the
.ISDN connection, a 29C48 combo for the voice connection and an 80188 microprocessor in combination with
an 82530 communications controller for the data connection. Benefits of the application are:
• Data rates up to 19.2 kb/s using an RS232 interface
or up to 48 kb(s using an X.21 interface.
• Compact design and low cost.
• Virtually error free transmission.

- Error correction (retransmission)
- Flow control
EPLD

• Interface conversion, serial.to/from SLD
• B-channel assignment

29C53
• Physical level interface (CCITT 1.430)
• Lower portion of the link access procedure:
- Zero insertion/deletion
- CRC generation and checking
- Flag appending and detection

Link Setup
Applies both for speech and data links. The 80188 accepts the command and begins the call setup procedure
by communicatirig the call's destination to the NT (or
CO). This is achieved by passing call setup messages to
a link level protocol, which is passed to the NT oyer the
physical level (S-bus). The partitioning of the tasks is as
follows:

• D-channel message buffering
The 80188 passes the information for the D-channel
messages via the parallel bus into the FIFO's of the
29C53.
The NT grants a B-channel (if available) to the TA and
the channel is now ready for data transfer.

8279

Information Transfer

The 8279 keyboard and display controller scans the telephone number pad and supports a small telephone display. Calls are initiated either through the terminal
keyboard using an extended Hayes Smart Modem command set or via the telephone number pad.

VOICE

The voice transfer is supported by the 29C48 which
transmits the voice on either the Bl or B2 channel
(controlled by the EPLD) into the 29C53 and onward
to the S-bus.

82530
Full duplex, dual channel serial communications controller capable of working in asynchronous, bit or byte
synchronous modes. The 82530 receives commands
from the terminal's RS232 or X.21 interface and passes
them on to the 80188.

DATA
An indication is given to the user's terminal via the
RS232 or X.21 port that communication may commence. Any subsequent data, from the terminal, is
treated as follows:

80188

Data from the terminal passes via the 82530 to RAM
via one of the 80188 DMA channels.

After having received the dialing information from either keyboard, the 80188 sets up the call via the 29C53
D-channel by sending the appropriate message up the
link.
.

The 80188 fetches the data from RAM, depacketizes
and packetizes it before sending it back to the 82530
where a protective HDLC protocol is added.

• Call setup message generation (CCITT 1.451)
• Upper portion of link access procedure (CCITT
1.440) handling:
- Multiple logic channels
- Sequence control

From the 82530, the data reaches the EPLD to be inserted into the Bl or B2 channel on the SLD bus. The
29C53 sends it out over the "S" interface.

5-18

intJ

AB-400

OJ-

29C48

...""

SLD

SLD

P3/4

81/82

RS 232 C
300 - 19200 blt/s
OR
X.21
600 - 48000 bit/s

~

:rJ.I.

~
HDLC

:!

29C53
AID

.. ..

c:::
c:::

4W ·S· Interface

:!

CS

CHANNEL
SELECT

INn
PCSI

f-

INTO

82530
SEL

D/C

PCSS

...

....

"l ~

....

.. !I>

.. .

" II'

IAPX188
AID

UCS
LCS

,

,.

"l ~

"l

AID

AID

AID

EPROM

RAM

"l

PCS4
INT3

I
CS INT
OUT ........ DISPLAY

8279

RL . - . . KEY80ARD
270247-2

Figure 2. ISDN Phone With Built In Terminal Adaptor

5-19

inter

AB-400

PERSONAL COMPUTER INTERFACE
Like the terminal adaptor, the ISDN PC adaptor
provides a link to the ISDN network. The ISDN CoProcessor shown in Figure 3 implements the hardware
functions required to support the CCITT I-series "S"
interface.

29C48
Voice conversion and interface to the four wire handset
is performed by this software programmable integrated
Codec/filter combo. Designed for ISDN terminal applications it offers programmable gain in transmit and
receive direction for user loudness control and adaptation to local network requirements as well as sidetone
insertion and tone injection for locally produced feedback signals.

The ISDN Co-Processor is using the 80188 microprocessor in combination with an 82530 serial communications controller for data processing, dual port RAM as'
interface and buffer to the host bus, the 29C48 Codec/
filter for voice support and the 29C53 transceiver for
the ISDN connection.

The 29C48 can access either Bl or B2 channel by setting the B Sel pin accordingly.

The ISP188 ISDN Software Package is optimized for
this hardware configuration.

29C53

82530

"S" bus transceiver and D channel controller in a single
chip. The 29C53 provides the physical level interface to
the "S" bus in accordance to CCITT 1.430 and the
lower portion of the link access protocol. Activation,
deactivation, zero insertion/deletion, CRC generation
and checking and flag appending and detection are performed by the 29C53, the higher level portions of
LABD are executed on the 80188 and passed on to the
29C53 via the parallel bus into the FI'FO's.

Full duplex, dual channel serial communications controller. One of the two channels is attached to either of
the B channels and operates at 64 kb/s. The s~ond
channel is available to external datacom equipment via
an optional serial port, or for connection to the second
B channel.

B channel access is via the SLD serial port. Voice signals are directly passed on to the 29C48. Data is
extracted and injected by the EPLD (Erasable, Programmable Logic Device) which performs the B channel assignment and the interface conversion to the
82530.

Co-Processor
The PC adaptor is an intelligent communications subsystem designed to function as a slave processor board
in the PC. This relieves the host processor of much of
the communications function.

RAM

DUAL PORT RAM

80188

ROM

270247-4

Figure 3. Personal Computer Interface

5-20

intJ

AB·400

FULL FEATURE ISDN LINE CARD

:
:

4W 'S' Interface

:
:

I
I

I
I

PCt.!1

29C53

PCt.!2

LINE CARD
CONTROLLER
CS INT

HOLC

TOt.! BACKPLANE

CONTROL/
.......... SIGNALING

SLO

29C53

4W 'S' Interface

7

PACKET NETWORK

PCS4

~=~~~~~t~JINT3
ucs
LCS

PCSO.1

PSC2.3

270247-3

Figure 4. Full Feature ISDN Line Card
4. The 80188 determines whether the data is for signaling (S-packet) or is a message to be sent out over the
packet (P-packet) switched network.
Signaling information can be processed locally or
sent via the Iinecard controller.
If the data is of "P" type, meant for the packet
switched network, it is DMA'd into the 82530 serial
communications controller which performs the necessary HDLC transmission, again without any CPU
involvement.
5. The 80188 software is responsible for sending out
acknowledgements for received messages from the
29C53's D-channel and can thus support large window sizes.
.

The addition ofISDN line cards to a PABX provides
the user with access to the ISDN network. While the
analog line card provides access for standard telephone
as well as for modems, ISDN terminal adaptors, terminals and phones are connected to the ISDN line card
via a 4 wire 'S' loop. The described application provides
all functions to separate voice and switched data (Bchannels) from signaling and packetized data (D-channel).
The 29C53 and 80188 together handle the processing of
D-channel protocols and messages as follows:
1. The 29C53 executes all bit level HDLC processing,
puts the "raw" messages into its FIFO and raises the
interrupt signal.
2. A special status register in the 29C53s allows the
80188, through a single status read operation, to determine which of the 29C53s is requiring interrupt
servicing, i.e. has D-channel messages(s) in its FIFO.
3. The 80188 accesses the FIFO concerned and the
data is transferred to RAM.

B-channel information is directly passed from the "S"
loop over the 29C53 and line card controller to the
switch backplane.
For transmission in the opposite direction, the procedure is equivalent to the one described above.

5-21

inter

AB·400

OTHER AVAILABLE TELECOM LITERATURE
Order Number

Title
29C53AA Reference Manual
29C53 Line Card Evaluation Kit
(LEK) Manual
29C53 Terminal Evaluation Kit
(TEK) Manual

5-22

296399-001

PCM Codec /Filter
and Combo

6

APPLICATIONS INFORMATION
.
2910A/2911A/2912A
CODECINTERFACE

CLOCK INTERFACE

The 2912A PCM Filter is designed to directly interface to the 2910A and 2911 A Codecs as shown below. The transmit path is completed by connecting
the VFxO output of the 2912A to the coupling capacitor associated with the VFx input of the 2910A
and 2911 A codecs. The receive path is completed
by directly connecting the codec output VFR to receive input of the 2912A VFRI. The PDN input of the
2912A should be connected to the PDN output of
the codec to allow the filter to be put in the powerdown standby mode under control of the co dec.

To assure proper operation, the ClK input of the
2912A should be connected to the same clock provided to receive bit clock, ClKR of 2910A or 2911 A
Codec as shown below. The ClKO input of the
2912A should be set to the proper voltage depending on the standard clock frequency chosen for the
codec and filter.

DIGITAL

2910A

~

SIG. - - - - - - - - - - - - - - - - - - - - - - - - - ,
SIGR - - - - - - - - - - - - - - - - - - - , r - - - - - + - V O D

POWER SUPPLY

CONTROL INPUTS
} FROM SYSTEM

LINE

~

j

ANALOG INPUT AND
GAIN ADJUSTMENT

OUTPUT TO

ELECTRONIC HYBRIDS
PCM FRAME SYNCH

AND BIT CLOCKS
POWER AMPLIFIER INPUT

POWER AMPLIFIER OUTPUT

.-+-----'

~-:::-::_+--+_INPUT FROM PCM HIGHWAY

{

TO TRANSFORMER HYBRIDS

GRDA

GRDD

~

-:!-:

~:::DJ:=-~ES

'-----------------------'=--_ v ••
11) DECOUPllNG CAPACITORS

V-

GRDA

270219-1

Figure 1. A Typical 2910A Co dec and 2912A Filter Configuration

6-1

October 1986
Order Number: 270219-001

inter

2910A/2911A/2912A

10) The optimum grounding configuration is to maintain separate digital and analog grounds on the
circuit boards, and to carry these grounds back
to the power supply with a low impedance connection. This keeps the grounds separate over
the entire system except at the power supply.

GROUNDING, DECOUPLING, AND
LAYOUT RECOMMENDATIONS
The most important steps in 'designing a low noise
line card are to insure that the layout of the circuit
components and traces results in a minimum of
cross coupling between analog and digital signals,
and to provide well bypassed and clean power supplies, solid ground planes, and minimal lead lengths
between components.

11) The voltage difference between ground leads
GRDA and GRDD (analog and digital ground)
should not exceed two volts.' One method of
preventing any substantial voltage difference between leads GRDA and GRDD is to connect two
diodes back to back in opposite directions
across these two ground leads on each board.

1) All power source leads should be bypassed to
ground on each printed circuit board (PCB), on
which codecs are provided. At least one electrolytic bypass capacitor (at least 50 I-lF) per board
is recommended at the point where all power
traces from the codecs and filters join prior to
interfacing with the edge connector pins assigned to the power leads.

12) Codec-filter pairs should be aligned so that pins
9 through 16 of the filter face pins 1 through 12
of the codec. This minimizes the distance for analog connections between devices and with no
crossing analog lines.

2) When using two-sided PCBs, use both corresponding pins on opposite sides of the board for
the same power lead. Strap them together both
on the PCB and on the back of the edge connector.

13) No digital or high voltage level (such as ringing
supply) lines should run under or in parallel with
these analog VF connections. If the analog lines
are on the top (component side) of the PC
board, then GRDD, GRDA, or power supply
leads should be directly under them, on the bottom to prevent analog/digital coupling.

3) Layout the traces on codec- and filter-equipped
boards such that analog signal and capacitor
leads are separated as widely as possible from
the digital clock and data leads.

14) Both the codec and filter devices should be
shielded from traces on the bottom of the PCB
by using ground or power supply leads on the
top side directly under the device (like a ground
plane).

4) Connect the codec sample and hold capacitor
with. the shortest leads possible. Mount it as
close to the codec CAP1 X, CAP2X pins as possible. Shield the capacitor traces with analog
ground.

15) Two +5V power supply leads (Vecl should be
used on each PCB, one to the filters, the other
to the codecs. These leads should be separately
decoupled at the PCB where they then join to a
single 5V supply at the backplane connector.
Decoupling can be accomplished with either a
series resistor/parallel capacitor (RC lowpass)
or a series RF choke and parallel capacitor of
each 5V lead. The capacitor should be at least
10 p,F in parallel with a 0.1 p,F ceramic. This
filters both high and low frequencies and accommodates large current spikes due to switching.

5) Do not layout any board traces (especially digital) that pass between or near the leads of the
sample and hold capacitor(s) since they are in
high impedance circuits which are sensitive to
noise coupling.
6)

Keep analog voice circuit leads paired on their
layouts so that no intervening circuit leads are
permitted to run parallel to them and/or between them.

7) Arrange the layout for each duplicated line; trunk
or channel circuit in identical form.
8)

Line circuits mounted extremely close to adjacent line circuits increase the possibility of interchannel crosstalk.

9)

Avoid assignment of edge connector pins to any
analog signal adjacent to any lead carrying digital (periodic) Signals or power.

16) Both grounds and power supply leads must have
low resistance and inductance. This should be
accomplished by using a ground plane whenever possible. When narrower traces must be
used, a minimum width of 4 millimeters should
be maintained. Either multiple or extra large plated through holes should be used when passing
.the ground connections through the PCB.

6-2

intJ

2910A/2911A/2912A

17) The 2912A PCM filter should have all power
supplies bypassed to analog ground (GRDA).
The 291 OAl2911 A Codec + 5V power supplies
should be bypassed to the digital ground
(GRDD). This is appropriate when separate
+ 5V power supply leads are used as suggested
in item 15. The - 5V and + 12V supplies should
be bypassed to analog ground (GRDA). Bypass
capacitors at each device should be high frequency capacitors of approximately 0.1 to 1.0
/iF value. Their lead lengths should be minimized by routing the capacitor leads to the appropriate ground plane under the device (either
GRDA or GRDD).

18) Relay operation, ring voltage application, interruptions, and loop current surges can produce
enormous transients. Leads carrying such signals must be routed well away from both analog
and digital circuits on the line card and in backplanes. Lead pairs carrying current surges
should be routed closely together to minimize
possible inductive coupling. The microcomputer
clock lead is particularly vulnerable, and should
be buffered. Care should also be used in the
backplane layout to prevent pickup surges. Any
other latching components (relay buffers, etc.)
should also be protected from surges.
19) When not used, the AUTO pin should float with
minimum PC board track area.

ZERO TRANSMISSION LEVEL POINTS
2910A/2912A 0 dBmO
TRANSMIT

FILTER

ENCODER

DIGITAL
MILLIWATT
CODES
(OR EQUIV.)

5.B5 dBm
t.52Vrms

2.85 d8m

1.08 Vlms

DECODER

RECEIVE

POWER

FILTER

AMPLIFIERS

5.85 dSm
1.52 VIrna

5.63 dBm
1.48 Vrma

SINGLE ENDED, 600 n

5.85 dBm
1.S2Vrms
BALANCED, 600
11.9 dam
3.04Vrms

n

270219-2

2911A12912A 0 dBmO
TRANSMIT
FILTER

ENCODER

RECEIVE
ALTER

DECODER

POWER
AMPLIFIERS

rnGITAL
MILLIWATT

2.88 dSm

5.88 dBm

1.08 Vrms

1.S2Vrms

CODES
(OR EQUIV.)

5.66 dBm
1.49Vrms

5.88 dBm
1.52 V,ms

SINGLE ENDED, 600n
5.88 dBm

1.52Vrms
BALANCED, 600

n

11.9dBm
3.05 Vlma

270219-3

6-3

APPLICATION

AP-142

NOTE

November 1986

Designing Second-Generation
Digital Telephony Systems
Using the Intel 2913/14
Codec/Filter Combochip

ROBERT E. HOLM
. TELECOM TECHNICAL SUPPORT
JOHN HUGGINS
TELECOM DESIGN ENGINEERING

Order Number: 210314-002

6-4

AP-142

Note: See data sheet· for latest specifications. Values given in this application
note are for reference only, and were considered correct at the time of publication (Feb. 1982).
each feature and specifications for timing and performance levels. This application note, in conjunction with
the data sheet, describes in more detail how the new
and improved features help in the design of second-generation linecards first by comparing the two generations
of components to see where the improvements have
been made, and then by discussing specific design considerations.

1.0 INTRODUCTION
This application note describes the features and capabilities of the 2913 and 2914 codec/filter combochips,
and relates these capabilities to the design and manufacturing of transmission and switching linecards.

1.1 Background
1.2 Comparison of First- and SecondGeneration Component
Capabilities

The first generation of per line codecs (Intel
29IOA/IIA) and filters (Intel 2912A) economically integrated the analog-digital conversion circuits and
PCM formatting circuits into one chip and the filtering
and gain setting circuits into another chip. These two
chips helped to make possible the rapid conversion to
digital switching systems that has taken place in the last
few years.

The combochip represents a higher level of component
integration than the devices it replaces and, because of
the economics of LSI (replacing two chips with one),
ultimately will cost significantly less at the component
level. But comparison of the combochip block diagram
with first-generation single-chip codec and filter reveals
few major functional differences. Figure 1 compares the
first-generation codec and filter chips to the combochip. Both provide rigidly specified PCM capabilities of
voice signal bandlimiting and nonlinear companded
A/D and D/A conversion. The first on-chip reference
voltage was introduced in the 2910/2911 single-chip
codecs and is included in the combochip. The provision
of uncommitted buffer amplifiers for flexible transmissidn level adjustment and enhanced analog output drive
was a feature of the now standard 2912 switched-capacitor PCM filter is available on the combochip. Like-

The second generation of Intel LSI PCM telephony
components, the 2913/14 Combochip, extends the level
of integration of the linecard by combining the codec
and filter functions for each line on a single LSI chip.
In the process of combining both functions, circuit design improvements have also improved performance,
reduced external component count, lowered power dissipation, increased reliability, added new features, and
maintained architectural transparency.
The 2913 and 2914 data sheet contains a complete des~ription of both parts, including detailed discussions of

PCM BANDPASS

ENCODE S/H

"ORA-LAW
ENCODING

TIMESLOT
CONTROL

ciw

OZ
... 0

oC"
ZOo
oCw

00:
......
I
I

TRANSFORMER TRANSMISSION
DRIVER
LEVEL CONTROL

PCM
LOWPASS

SINGLE'CHIP PCM FILTER

SINGLE-CHIP PCM CODEC

COMBO CHIP
~---------------------------------------------

210314-1

Figure 1. LSI Partitioning of Codec/Filter Functions

6-5

inter

AP-142

diagnostic software, the bulk of the production costs
are in the high-volUlne linecards. The combochip addresses these cost pressures and defers the appetite for
new integrated functions to a future generation of PCM
components.

wise, independent transmit (AID) and receive (D/A)
analog voice channels which permit the two channels to
be timed from independent (asynchronous) clock sources is common to the first- and second-generation devices. Finally, the ability to multiplex signalling bits on a
. bit-stealing .basis from th~ digital side of the device has
been duplicated on the combochip.

Figure 2 contains the block diagram of the 2913/14
combochip which illustrates not only the basic companding and filtering functions but also some of the
changes and new features contained in the second-generation devices, such as internal auto zero, separate
ADC and DAC for transmit and receive sections, respectively, precision gain setting (ReV section), and input/output registers for both fixed and variable data
rates. Table 1 lists many of the features that are important to Iinecard design and performance. A direct comparison between first-and second-generation products

Data traffic-conscious systems manufacturers now provide dedicated codec, filter, and subscriber interface
functions on a per-subscriber basis, which in turn puts
intense cost pressures on these functions. The functional duplication of first-generation components addresses
the needs of the system manufacturer who wants to
cost reduce existing fixed-architecture system designs.
Whereas the bulk of the system development costs (and
time) are in the switching machine call processing and

Table 1_ Comparison between 2913/14 Combochlp and the
2910A/11A/12A Single-Chip Codecs and Filters
Features
Power

Operating

2910A/11A plus 2912A

2913114

280-310mW

140mW

Standby
Pins
Board Area Including Interconnects
Data Rates.

-Fixed

PSRR

0.33
Same

None

64 Kbps -+ 2.048 Mbps

-p.-Law

2910

-A-Law

2911

+ 2912
+ 2912

Strap Selectable

30dB

>35dB

NotSpec'd

> 35dB

Trim Using Pot Necessary .

Precision Resistors
Eliminate Trim Req.

Direct

Yes

Yes

Timeslot Assign

Yes

No

Yes

Yes

15 dBrncO Transmit
11 dBrncO Receive

15 dBrncO Transmit
11 dBrncO Receive

See Data Sheet

See Section 2.0

> 10 KHz
Gain Setting

On-Chip VREF
ICN - Half Channel Improvement
SID -

20-24

Normalized = 1.0

1 KHz

Operating Modes

5mW

38-40
1.536, 1.544, 2.048 Mbps

-Variable
Compal]ding Law

33mW

Half Channel Improvement

See Data Sheet

See Section 2.0

PDN Pin

Frame Sync Removal or PDN Pin

Signalling

2910-8th Bit

2914-8th Bit

Auto Zero

External

Internal

S&HCaps

External Transmit
Internal Receive

Internal

Test Modes

None

GT -

Half Channel Improvement

Power Down (Standby)

Encoder Implementation
Filter/Gain Trim

-

Resistive Ladder
Fuse Blowing

6-6

± 0.2 dB

Design Tests
Manufacturing Test
On-Line Operational Tests
Capacitive Charge Redistribution
Ladder
Fuse Blowing

± 0.04 dB

intJ

AP·142

XUIT
SECTION

AUTO
ZERO

D,
VFxl+

SAMPLE
AND HOLD
AND OAe

YFxl -

SUCCESSIVE
APPROXIMATION
REGISTER

COMPARATOR

OUTPUT
REGISTER

lSx/CClKX
SIG.IASEL

as'_I-;:=~
ANAloa
TO
DIGITAL
CONTROL

LOGIC

1 - - - - - - - -.....- - - 4 - -FS,
t------------i_-CLKx

RCV
SECTION
ClKSEL

as.

PIm
LOOP

PWAO+

_-+-,.--,

PWAO-

_-+--+__-'

D.

'-----1--510fl;

Yee

VIII

QRDO

GRDA

210314-2

(a) Combochip Block Diagram
Vee
PWRO +, PWROGSR
PDN
CLKSEL
LOOP
SIGR
DCLKR
DR
FSR
GRDD
Vee

Power (-5V)
Power Amplifier Outputs
Receive Gain Control
Power Down Select
Master Clock Frequency
Select
Analog Loop Back
Receive Signaling Bit Output
Receive Variable Data Clock
Receive PCM Input
Receive Frame
Synchronization Clock
Digital Ground
Power (+5V)

GSx
VFxl-, VFxl +
GRDA
NC
SIGx

Transmit Gain Control
Analog Inputs'
Analog Ground
No Connect
Transmit Signaling Input

ASEL
TSx
DCLKx
Dx
FSx

IL- or A-law Select
Timeslot Strobe/Buffer Enable
Transmit Variable Data Clock
Transmit PCM Output
Transmit Frame
Synchronization Clock
Transmit Master Clock
Receive Master Clock

CLKx
CLKR
(b) Combochip Pin Names

Figure 2. Block Diagram of 2913/14 Combochip

6-7

intJ

Ap·142

shows the significant improvement in the combochip
both in performance levels and system flexibility.

Table 3. 2914 Factors which Increase Llnecard
Manufacturing Yields and Efficiency

• Higher Reliability
-Fewer connections and components
-More integrated packaging
-More margin to specs
-Lower power
-NMOS proven process
-Less sensitive to parameter variations

2.0 DESIGN CONSIDERATIONS
The key point with the 2913/14 is that it will result in a
linecard that performs better and costs less than any
two-chip codec/filter solution. The lower cost results
from many factors, as seen in Table 2. Both direct replacement costs and less tangible design and manufacturing time savings combine to yield lower recurring
and nonrecurring costs. As an example, the wider margins to transmission specs and the higher power supply
rejection ratios of the 2913/14 will both shorten the
design time needed to build and test the linecard prototype and reduce the reject rate on the manufacturing
line.
.

• Fewer Manufacturing Steps
-No gain trimming
-On chip VREF
-Wide power supply tolerance
-On chip test modes
-Wide margins to spec

Table 2. 2913/14 Factors which Lower the Cost
of Linecard Design and Manufacturing

• Lower LSI Cost (2914 vs. 2910/11
2912)
• Fewer External Components
• Less Board Area
• Shorter DesignlPrototype Cycle
• Better Yields/Higher Reliability
• Lower Power/Higher Density

+
Table 4. Design Factors for 2914 which Reduce
Linecard PCB Area

• Integrated Packaging
-2914 vs. 2910/11 + 2912
= 1/3 board area
-2913 takes even less space
• Fewer Interconnects/Components
-Codec/filter combined
-On-chip reference voltage
-On-chip auto zero
-On-chip capacitors
-No gain trim components
-No voltage regulators

Part of the recurring cost of linecard production is the
efficiency of the manufacturing line in turning out each
board. This is measured in both parts cost and time.
Average manufacturing time is strongly effected by the
line yield, i.e., the reject rate reliability. A linecard using the 2913/14 has many labor-saving features, which
also increases the reliability -of the manufacturing process. Some of these features are detailed in Table 3.
The combination of fewer parameters to trim (gain, reference voltage, etc.), tolerance to wider power supply
variations, and on-chip test modes make the linecard
very manufacturable compared to first-generation designs.

• Efficient Layout (Facilitates Auto Insertion)
-Analog/digital sections separated on
chip
-Digital traces can cross under chip
-Two power supplies only
-Low power/high density

Probably the most obvious improvement in linecard design based around the 2913/14 is the reduction in linecard PCB area needed compared to two-chip designs.
The combination of the codec and filter into a single
package alone reduced the LSI area by one-third. Table
4 shows many of the other ways in which board area is
conserved. In general, it reduces to fewer components,
more on-chip features, and layout of the chip resulting
in-an efficient board layout which neatly separates the
analog and digital signals both inside the chip and on
the board.

6-8

intJ

AP-142

Table 5 2913/14 Operating Mode Options Add Flexibility to Linecard Design
Option

Results of Mode Selection

Mode Control Pins

2914 (24 Pin)
Companding Law
Power Down

Data Rate

Test Modes

+ Signalling

2913 (20 Pin)
I
I A-Lawl/L-Law, no Signalling

SIGX/ASEL

A-Law or /L-Law

PDN

Transmit & Receive Side Go To Standby Power (5 mW)

FSx & FSR Removed

Same (12 mW)

FSx Removed

Transmit Side Goes to Standby (110 mW)

FSR Removed

Receive Side Goes to Standby (70 mW)

= Vee/GRDDlVss
DCLKR = Vss

1.536/1.544/2.048 Mbps in Fixed Data Rate Mode

- Vee/GRDDlVss
DCLKs = Clock

Variable Data Rate Mode from 64 Kbps to 2.048 Mbps,
No Signalling

LOOP

= Vee

Implements Analog Loopback

I No Loopback Capability

PDN = Vss

Provides Access to Transmit Codec Through ASEL and TSX
Pins

DR = Vss

Provides Access to RCV Filter Input at DCLKR and Transmit
Filter Outputs at ASEL and TSX Pins

without significant system timing, control, or software
modifications. To this end, two distinct user-selectable
timing modes are possible with the combochip. For
purposes of discussion, these are designated (a) fixed
data rate timing (FDRT) and (b) variable data rate timing (VDRT).

Many of the factors discussed-which result in efficient, cost-effective linecard designs-are discussed in
more detail both in the 2913/14 data sheet and in the
following sections of this note.

2.1 Operating and Test Mode
Selection

FDRT is identical to the 2910/2911 codec timing in
which a single high-speed clock serves both as master
clock for the codec/filter internal conversion/filtering
functions and as PCM bit clock for the high-speed serial PCM data bus over which the combochip transmits
and receives its digitized voice code words. In this
mode, PCM bit rates are necessarily confined to one of
three distinct frequencies (1.536 MHz, 1.544 MHz, or
2:048 MHz). Many recently designed systems employ
this type of timing which is sometimes referred to as
burst-mode timing because of the low duty cycle of
each timeslot (i.e., channel) on the time division multiplexed PCM bus. It is possible for up to 32 active combochips to share the same serial PCM bus with FDRT.

A key to designing with the 2913/14 combo is the wide
range of options available in configuring, either with
strap options or in real time, the different modes of
operation. The 2913 combochip (20 pins) is specifically
aimed at synchronous switching systems (remote concentrators, PABXs, central offices) where small package size is especially desirable. The 2914 combochip (24
pins) has additional features which are most suitable for
applications requiring 8th-bit signalling, asynchronous
operation, and remote testing of transmission paths
(e.g., channel banks). Once the specific device is selected, there is a wide range of operating modes to use in
the card design, as seen in Table 5. This table lists the
optional parameters and the pins which control the operating mode. The result of selecting a mode is listed for
both the 2913 and 2914.

VDRT (sometimes referred to as shift register timing),
by comparison, utilizes one high-speed master clock for
the combochip internal conversion/filtering functions
and a separate, variable frequency, clock as the PCM
bit clock for the serial PCM data bus. Because the serial
PCM data rate is independent of internal conversion
timing, there is considerable flexibility in the choice of
PCM data rate. In this mode the master clock is permitted to be 1.536 MHz, 1.544 MHz, or 2.048 MHz,
while the bit clock can be any rate between 64 KHz and
2.048 MHz. In this mode it is possible to have a dedicated serial bus for each combochip or to share a single
serial PCM bus among as many as 32 active combochips.

The purpose of offering these options is to ensure that
the 2913/14 combo will accommodate any existing
linecard design with architectural transparency. At the
same time, features were designed in to facilitate design
and manufacturing testing to reduce overall cost of development and production.

2.2 Data Rate Modes
Any rapid conversion scenario presumes 'that the combochip will fit existing system architectures (retrofit)
6-9

inter

AP-142

Thus, the two predominant timing configurations of
present system architectures are served by the same device, allowing, in many cases, linecard redesign without
modification of any common system hardware or software. Additional details relating to the design of systems using either mode are found in section 3.0.

2.3 Margin to Performance
Specifications
The combochip benefits from design, manufacturing,
and test experience with first-generation PCM products
on the part of the system manufacturer, component
suppliers, and test equipment suppliers. The sub-millivolt PCM measurement levels "and tens of microvolts
accuracy requirements on the lowest signal measurements often result in tester correlation problems, yield
losses, and excess costs for system and PCM component manufacturers alike. Thus additional performance
margin built into the PCM components themselves will

have its effect on line circuit costs even though the system transmission specifications may not reflect the improved performance margin.
Half channel measurements have been made of the
transmission parameters-gain tracking (GT), signal to
distortion ratio (SID), and idle chan~el noise (ICN).
Gain Tracking-Figure 3 shows the gain tracking data
for both the transmit and receive sides of the combo
using both sine wave testing (CCITT G712.11 Method
2) and white noise testing (CCITT G712.11 Method I).
The data shows a performance very nearly equal to the
theoreticafiy best achievable using both test techniques.
. End to end measurements, although not spec'd, also
show a corresponding good performance with errors
less than or equal to the sum of the half channel values.
Signal to Distortion Ratio-:.This is a measure of the
system linearity and the accuracy in implementing the
companding codes. Figure 4 shows the excellent perfor-

Gain Tracking Error Versus Signal Level
2914 Combo AID
Sinusoidal Test (CCITT G712.11 Method 2)

Gain Tracking Error Versus Signal Level
2914 Combo DIA
Sinusoidal Test (CCITT G712.11 Method 2)

iii

iii
~

ffi

.5

.g"'"

0

L-- 1

I

~

-1

ffi

L~~~r

1

1

1

1

I

1

I

-1

I

--p +3
IdBmO

~

I

1

I

I
---I

.5

";<'"
u
: -.5
...

;'-,...

-55 -50 -410- - - - - - - 1--....1

...~ -.5

a:
o
a:

:

~--I---I---I---I

I

~

I
I

a:
oa:

1

-----------1 INPUT
I'
1
1
1
I 1LEVEL
-55 -50 -40--- - - - - - --'0+3
1--":
dBmo
Ll

I

i

I

I
1

I
1

I

1
I

-2

-2

210314-4

210314-3

Gain Tracking Error Versus Signal Level
2914 Combo DIA
White Noise Test (CCITT G712.11 Method 1)

Gain Tracking Error Versus Signal Level
2914 Combo AID
White Noise Test (CCITT G712.11 Method 1)
I
1
1

iii
~

a:

1

o

~ .5

iii

I

~

-l

~ 0

;<

1---1---+--.
-55 -so

~ -.5

1

'" -1

r~

"

I
I
-2

I
-40

INPUT
I LEVEL
0 +3

~

INPUT
ILEVEL
-55 -50 -40
0 +3
, - - - - - - - - - ----'dBmO
1
1

0

8.. -.5
...a:

1

'" -1

~

1

!...------- ______ I

~ .5
w

r------~-----ldBmO

I!:

C

o

'- _ _ _ _ _ _ _ _ _ _ _ _ J

w

I

L_

a:

1

1_-'

I
1

I

-2

1

210314-6

210314-5

Figure 3. 2914 Half Channel Gain Tracking Performance Measurements
for Both Sine and Noise Testing
6-10

intJ

AP-142

-

..,iii

0" 40

ii0:
li

30

In

20

AID SINEWAVE TEST

~
o

;;

/

~~
DIA SINEWAVE TEST

...

r

;!

O

~ O~----+--r~r-'--.-----.-----r~~.-45 -40 -35 -30 -25

-15

-5

0

5

-45 -40 -35 -30 -25

INPUT LEVEL (dBmO)

or-

210314-7

iii

iii
:!. 40

ii
~ 30

0:

o

ii

Z 30

AID WHITE NOISE TEST

o

;:

~
o

In

20 /

0:

o
Ii;
;;

FULL CHANNEL SPEC _

~
o

fi~~n~

2~ /

""- FULL CHANNEL SPEC

..
...

r

10

5

•

-5

210314-8

:!. 40

;;
;;!
l)

-15

INPUT LEVEL (dBmO)

O

0

~-~'---45'--4-r0-_'3r5-_'30--_'~-----_lT5-----_r5L,0r-'5-

o

o

INPUT LEVEL (dBmO)

0~-.--.--r--r-'--.-----.-----rL,r-'­
~

-45 -40 -35 -30 -25

-15

-5

INPUT LEVEL (dBmO)

210314-9

210314-10

Figure 4. 2914 Half Channel Signal to Distortion Ratio (SID) Performance Measurements
,
for Both Sine and Noise Testing
Power Supply Rejection-Circuit innovation in the internal combochip design has resulted in significant improvements in power supply rejection in the 5 to 50
KHz range (Figure 7), and it is this frequency band
which usually contains the bulk of the switching regulator noise. These higher frequencies, outside the audio
range as they are, are not objectionable or even detectable in the transmit direction except to the extent that
they alias into the audio range as a result of internal
sampling processes in the transmit filter and AID converter. Sampling techniques in the combochip minimize
this aliasing. In the receive direction, excess high frequency noise which propagates onto the subscriber loop
can interfere with signals in adjacent wires and is thus
objectionable even without aliasing. The symmetrical
true differential analog outputs of the combochip are an
improvement from earlier designs which failed to maintain true power supply symmetry through the output
amplifiers. Not only does the differential design improve transmission performance, but it also reduces the
need for power supply bypass capacitors, thereby saving component cost on the Iinecard.

mance of the 2914 for both the transmit (AID) and
receive (DI A) channels using sine wave and noise testing. The margin is greater than 3 dB above the half
channel spec which means that a larger error budget is
available to the rest of the channel.
Statistical Analysis-A statistical analysis of G.T. and
SID measurements over many devices shows a very
tight distribution, as seen in Figure 5. There are several
consequences resulting from this highly desirable distribution: (1) the device performance is controllable, resulting in high yields, (2) the device circuit design is
tolerant of normal process variations, thereby ensuring
predictable production yields and high reliability, and
(3) understanding of the circuit design and process fundamentals is clearly demonstrated-largely as a result
of previous telephony experience with the Intel NMOS
process.
Idle Channel Noise-The third transmission parameter
is idle channel noise (ICN). Figure 6 gives half channel
ICN measurements which show a substantial margin to
specification.

6-11

AP-142

2
I
MINIMAX
I/c-ENVELOPE
I

:!
II:

0

1

f5

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