1990_Intel_Microcommunications_Volume_II_Applications 1990 Intel Microcommunications Volume II Applications

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Intel the Microcomputer Company:
When Intel invented the microprocessor in 1971, it created the era of
microcomputers. Whether used in embedded applications such as automobiles
or microwave ovens, or as the CPU in personal computers or supercomputers,
Intel's microcomputers have always offered leading-edge technology. Intel continues
to strive for the highest standards in memory, microcomputer components, modules
and systems to give its customers the best possible competitive advantages.

MICROCOMMUNICATIONS
APPLICATIONS

1990

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors
which may appear in this document nor does it make a commitment to update the information contained
herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before· placing your order.
The following are trademarks rof Intel Corporation and may only be used to identify Intel Products:
376,386,387,486, 4-SITE, Above, ACE51 , ACE96, ACE186, ACE196,
ACE960, BITBUS, COMMputer, CREDIT, Data Pipeline, DVI, ETOX,
FaxBACK, Genius, i, t, i486, i750, i860, ICE, iCEL, ICEVIEW, iCS, iDBP,
iDIS, 12 1CE, iLBX, iMDDX, iMMX, Inboard, Insite, Intel, intel, Inte1386,
intaiBOS, Intel Certified, Intelevision, inteligent Identifier, inteligent
Programming, Intellec, Intellink, iOSP, iPAT, iPDS, iPSC, iRMK, iRMX,
iSBC, iSBX, iSDM, iSXM, Library Manager, MAPNET, MCS,
Megachassis, MICROMAINFRAME, MULTIBUS, MULTICHANNEL,
MULTIMODULE, MultiSERVER, ONCE, OpenNET, OTP, PR0750,
PROMPT, Promware, QUEST, QueX, Quick-Erase, Quick-Pulse
Programming, Ripplemode, RMX/80, RUPI, Seamless, SLD, SugarCube,
TooITALK, UPI, Visual Edge, VLSiCEL, and ZapCode, and the
combination of ICE, iCS, iRMX, iSBC, iSBX, iSXM, MCS, or UPI and a
numerical suffix.
MDS is an ordering code only and is not used as a product name or trademark. MDS@ is a registered
trademark of Mohawk Data Sciences Corporation.
·MULTIBUS is a patented Intel bus.

>

CHMOS and HMOS are patented processes of Intel Corp.
Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its
FASTPATH trademark or products.
.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
@INTELCORPORATION 1989

CUSTOMER SUPPORT
INTEL'S COMPLETE SUPPORT SOLUTION WORLDWIDE
Customer Support is Intel's complete support service that provides Intel customers with hardware support,
software support, customer training, consulting services and network management services. For detailed information contact your local sales offices.
After a customer purchases any system hardware or software product, service and support become major
factors in determining whether that product will continue to meet a customer's expectations. Such support
requires an international support organization and a breadth of programs to meet a variety of customer needs.
As you might expect, Intel's customer support is quite extensive. It can start with assistance during your
development effort to network management. 100 Intel sales and service offices are located worldwide-in the
U.S., Canada, Europe and the Far East. So wherever you're using Intel technology, our professional staff is
within close reach.

HARDWARE SUPPORT SERVICES
Intel's hardware maintenance service, starting with complete on-site installation will boost your productivity
from the start and keep you running at maximum efficiency. Support for system or board level products can be
tailored to match your needs, from complete on-site repair and maintenance support to economical carry-in or
mail-in factory service.
Intel can provide support service for not only Intel systems and emulators, but also support for equipment in
your development lab or provide service on your product to your end-user/customer.

SOFfWARE SUPPORT SERVICES
Software products are supported by our Technical Information Service (TIPS) that has a special toll free
number to provide you with direct, ready information on known, documented problems and deficiencies, as.
well as work-arounds, patches and other solutions.
Intel's software support consists of two levels of contracts. Standard support includes TIPS (Technical Information Phone Service), updates and subscription service (product-specific troubleshootmg guides and;
COMMENTS Magazine). Basic support consists of updates and the SUbscription service. Contracts are sold in
environments which represent product groupings (e.g., iRMX® environment).

CONSULTING SERVICES
Intel provides field system engineering consulting services for any phase of your development or application
effort. You can use our system engineers in a variety of ways ranging from assistance in using a new product,
developing an application, personalizing training and customizing an Intel product to providing technical and
management consulting. Systems Engineers are well versed in technical areas such as microcommunications,
real-time applications, embedded microcontrollers, and network services. You know your application needs;
we know our products. Working together we can help you get a successful product to market in the least
,
possible time.

CUSTOMER TRAINING
Intel offers a wide range of instructional programs covering various aspects of system design and Implementation. In just three to ten days a limited number of individuals learn more in a single workshop than in weeks of
self-study. For optimum convenience, workshops are scheduled regularly at Training Centers worldwide or we
can take our workshops to you for on-site instruction. Covering a wide variety of topics, Intel's major course
categories include: architecture and assembly language, programming and operating systems, BITBUS™ and
LAN applications.
.

NETWORK MANAGEMENT SERVICES
Today's networking products are powerful and extremely flexible. The return they can provide on your investment via increased productivity and reduced costs can be very substantial.
Intel offers complete network support, from definition of your network's physical and functional design, to
implementation, installation and maintenance. Whether installing your first network or adding to an existing
one, Intel's Networking Specialists can optimize network performance for you.

Table of Contents
Alphanumeric Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AP-302 Microcommunications Overview .....................................

viii
ix

SECTION ONE-DATA COMMUNICATIONS COMPONENTS
CHAPTER 1
Local Area Networks
CSMA/CD Access Method
AP-235 An 82586 Data Link Driver ..........................................
AP-236 Implementing StarLAN with the Intel 82588 ......................... ~..
AP-320 Using the Intel 82592 to Integrate a Low-Cost Ethernet Solution into a PC
Motherboard ....................................................... ;...
AP-274 Implementing EthernetiCheapernet with the Intel 82586 .............. ..
AP-324 Implementing Twisted Pair Ethernet with the Intel 82504TA, 82505TA, and
82521 TA . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-327 Two Software Packages for the 82592 Embedded LAN Module .. . . . . . . ..
AP-331 Using the Intel 82592 to Implement a Non-Buffered Master Adapter for ISA
Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

1-1
1-81
1-155
1-200
1-289
1-308
1-386

CSMA/CD Access Method Evaluation Tools
AP-326 PS592E-16 Buffered Adapter LAN Solution for the Micro Channel
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-328 PC592E Buffered LAN Adapter Solution for the IBM PC-XT and AT . .. . . ..

1-468
1-519

CHAPTER 2
Wide Area Networks
AP-401 Designing With the 82510 Asynchronous Serial Controller. . . . . . . . . .. .. . .
AP-31 0 High Performance Driver for 82510 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .
AP-36 Using the 8273 SDLC/HDLC Protocol Controller . . . . . . . . . . . . . . . . . . . . . . ..
AP-134 Asynchronous Communication with the 8274 Multiple-Protocol Serial
Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-145 Synchronous Communication with the 8274 Multiple Protocol Serial
Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-222 Asynchronous and SDLC Communications with 82530 . . . . . . . . . . . . . . . . ..

2-1
2-81
2-112
2-164
2-202
2-240

CHAPTER 3
Other Components
AP-166 Using the 8291A GPIB Talker/Listener.............................. ..
AP-66 Using the 8292 GPIB Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1
3-31

SECTION TWO-TELECOMMUNICATION COMPONENTS
CHAPTER 4
Modem Products
AB-24 89024 Modem Customization for V.23 Data Transmission ................

4-1

CHAPTERS
ISDN Products
AP-282 29C53 Transceiver Line Interfacing. . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . ..
AP-400 ISDN Applications with 29C53 and 80188 .............................

5-1
5-15

CHAPTER 6
PCM Codec/Filter and Combo
Applications Information 291 OAl2911 Al2912A ...............................

6-1

AP-142 DeSigning Second-Generation Digital Telephony Systems Using the Intel
2913/14 Codec/Filter Combochip.........................................

6-4

vii

Alphanumeric Index
AB-24 89024 Modem Customization for V.23 Data Transmission ...................... .
AP-134 Asynchronous Communication with the 8274 Multiple-Protocol Serial Controller .. .
AP-142 Designing Second-Generation Digital Telephony Systems Using the Intel 2913/14
Codec/Filter Combochip ....................................................... .
AP-145 Synchronous Communication with the 8274 Multiple Protocol Serial Controller ... .
AP-166 Using the 8291A GPIB Talker/Listener ..................................... .
AP-222 Asynchronous and SDLC Communications with 82530 ........................ .
AP-235 An 82586 Data Link Driver ................................................ .
AP-236 Implementing StarLAN with the Intel 82588 .................... ; ............ .
AP-274 Implementing EthernetlCheapernet with the Intel 82586 ...................... .
AP-282 29C53 Transceiver Line Interfacing ......................... " .............. .
AP-302 Microcommunications Overview ........................................... .
AP-31 0 High Performance Driver for 82510 " .......................................•
AP-320 Using the Intel 82592 to Integrate a Low-Cost Ethernet Solution into a PC
Motherboard .............................................•....................
AP-324 Implementing Twisted Pair Ethernet with the Intel 82504TA, 82505TA, and
.
82521TA .................................................................... .
AP-326 PS592E-16 Buffered Adapter LAN Solution for the Micro Channel Architecture ... .
AP-327 Two Software Packages for the 82592 Embedded LAN Module ................ .
AP-328 PC592E Buffered LAN Adapter Solution for the IBM PC-XT and AT ............. .
AP-331 Using the Intel 82592 to Implement a Non-Buffered Master Adapter for ISA
Systems ...................... , ........... ; ........•..........................
AP-36 Using the 8273 SDLC/HDLC Protocol Controller ...............-............... .
AP-400 ISDN Applications with 29C53 and 80188 ..................... : ..........•...
AP-401 Designing With the 82510 Asynchronous Serial Controller ..................... .
AP-66 Using the 8292,GPIB Controller ............................................. .
Applications Information 2910Al2911A12912A ....... : ............................. .

viii

4-1
2-164
6-4
2-202
3-1
2-240
1-1
1-81
1-200
5-1
ix
2-81
1-155
·1-289
1-468
1-308
1-519
1-386
2-112
5-15
2-1
3-31
6-1

Ap·302

Kobayashi's macro vision hints at the obstacles confronting the future of C&C. When taken to the micro
level, to silicon itself, one begins to understand the'
complexities that are involved. When Intel invented the
microprocessor fifteen years ago, the first seeds of the
personal computer revolution were sown , marking an
era that over the last decade has dramatically influenced the way people work and live. PCs now proliferate in the office, in factories, and throughout laboratory
environments. And their "intimidation" factor has lessened to where they are also becoming more and more
prevalent in the home, beginning to penetrate a market
that to date has remained relatively untapped.

OVERVIEW
Imagine for a moment a world where all electronic
communications were instantaneous. A world where
voice, data, and graphics could all be transported via
telephone lines to a variety of computers and receiving
systems. A world where the touch of a finger could
summon information ranging from stock reports to
classical literature and bring it into environments as
diverse as offices and labs, factories and living rooms.
Unfortunately, these promises of the Information Age
still remain largely unfulfilled. While computer technology has accelerated rapidly over the last twenty
years, the communications methods used to tie the wide
variety of electronic systems in the world together have,
by comparison, failed to keep pace. Faced with a tangle
of proprietary offerings, high costs, evolving standards,
and incomplete technologies, the world is still waiting
for networks that are truly all-encompassing, the missing links to today's communications puzzle.

Thanks to semiconductor technology, the personal
computer has raised the level of productivity in our
society. But most of that productivity has been gained
by individuals at isolated workstations. Group productivity, meanwhile, still leaves much to be desired. The
collective productivity of organizations can only be enhanced through more sophisticated networking
technology. We are now faced with isolated "islands
of automation" that must somehow be developed
into networks of productivity.

Enter microcommunications-microchip-based digital
communications products and services. A migration of
the key electronics communications functions into silicon is now taking place, providing the vital interfaces
that have been lacking among the various networks
now employed throughout the world. Through the evolution ofVLSI (Very Large Scale Integration) technology, microcommunications now can offer. the performance required to effect these communications interfaces
at affordable costs, spanning the globe with silicon to
eradicate the troublesome bottleneck that has plagued
information transfer during recent years.

But no amount of computing can meet these challenges
if the corresponding communications technology is not
sufficiently in step. The Information Age can only grow
as fast as the lowest common denominator-which in
this case is the aggregate communications bandwidth
that continues to lag behind our increased computing
power. Such is the nature of the communications bottleneck, where the growing amounts of information we
are capable of generating can only flow as fast as the
limited and incompatible communications capabilities
now in place. Clearly, a crisis is at hand.

"There are three parts to the communications puzzle,"
says Gordon Moore, Intel Chairman and CEO. "The
first incorporates the actual systems that communicate
with each other, and the second is the physical means
to connect them-such as cables, microwave'technology, or fiber optics. It is the third area, the interfaces
between the systems and the physical links, where silicon will act as the linchpin.. That, in essence, is what
microcommunications is all about."

BREAKING UP THE BOTTLENECK
Three factors have contributed to this logjam: lack of
industry standards, an insufficient cost/performance
ratio, and the incomplete status of available communications technology to date.
• Standards-One look at the tangle of proprietary
systems now populating office, factory, and laboratory environments gives a good indication of the
inherent difficulty in hooking these diverse systems
together. And these systems do not merely feature
different architectures-they also represent completely different levels of computing, ranging from
giant mainframes at one end of the scale down to
individual microcontrollers on the other.
The market has simply grown too fast to effectively
accommodate the changes that have occurred. Suppliers face the dilemma of meshing product differentiation issues with industry-wide compatibility as

THE COMMUNICATIONS
BOTTLENECK
Visions of global networks are not new. Perhaps one of
the most noteworthy of these has been espoused by Dr.
Koji Kobayashi, chairman of NEC Corporation. His
view of the future, developed over the nearly fifty years
of his association with NEC, is known as C&C (Computers and Communications). It defines the marriage of
passive communications systems and computers as
processors and manipulators of information, providing
the foundation for a discipline that is changing the basic character of modern society.

ix

intJ

•

•

AP-302

they develop their strategies; opting for one in the
past often meant forsaking the other. And while
some standards have coalesced, the industry still
faces a technological Tower of Babel, with many
proprietary solutions vying to be recognized in leadership positions.
Cost/Performance Ratio-While various communications technologies struggle toward maturity,
the industry has had to cope with tremendous costs
associated ,with interconnectivity and interoperation. Before the shift to microelectronic interfaces
began to occur, these connections often were prohibitively expensive.
Says Ron Whittier, Intel Vice President and Director of Marketing: "Mainframes offer significant
computing and communications power, but at a
price that limits the number of users. What is needed is cost-effective communications solutions to
hook together the roughly 16 million installed PCs
in the market, as well as the soon-to-exist voice/
data terminals. That's the role of microcommunications-bringing cost-effective communications solutions to the microcomputer world."
Incomplete Technology-Different suppliers have
developed many networking schemes, but virtually
all have been fragmented and unable to meet the
wide range of needs in the marketplace. Some of
these approaches have only served to create additional problems, making OEMs and systems houses
loathe to commit to suppliers who they fear cannot
provide answers at all of the levels of communications that are now funneled into the bottleneck.

The distances over which information may be transmitted via a WAN are essentially unlimited. The goal of
ISDN is to take what is largely an analog global system
and transform it into a digital network by defming the
standard interfaces that will provide connections at
each node.
These interfaces will allow basic digital communica-'
tions to occur via the existing twisted pair of wires that
comprise the telephone lines in place today. This would
bypass the unfeasible alternative of installing completely new lines, which would be at cross purposes with the
charter of ISDN: to reduce costs and boost performance through realization of an all-digital network.
The second category, Local Area Networks, represents
the most talked~about link provided by microcommunications. In their most common form, LANs, are comprised of-but not limited to-PC-to-PC connections.
They incorporate information exchange over limited
distances, usually not exceeding five kilometers, which
often takes place within the same building or between
adjacent work areas. The whole phenomenon surrounding LAN development, personal computing, and distributed processing essentially owes its existence to microcomputer technology, so it is not surprising that this
segment of networking has garnered the attention it has
in microelectronic circles.
Because of that, progress is being made in this area.
The most prominent standard-which also applies to
WANs and SANs-is the seven-layer Open Systems Interconnection (OSI) Model, established by the International Standards OrgaI)ization (ISO). The model provides the foundation to which all LAN configurations
must adhere if 'they hope to have any success in the
marketplace. Interconnection protocols determining
how systems are tied together are defined in the first
five layers. Interoperation concepts are covered in the
upper two layers, defining how systems 'can c:ommunicate with each other once they are tied together.

THE NETWORK TRINITY
Three principal types of networks now comprise the
electronic communications marketplace: Wide, Area
Networks (WANs), Local Area Networks (LANs), and
Small Area Networks (SANs). Each in its own fashion
is turning to microcommunications for answers to its
networking problems.

In the LAN marketplace, a large number of networking
products and philosophies are available today, offering
solutions at various price/performance points. Diverse
approaches such as StarLAN, Token Bus and Token
Ring, Ethernet, and PC-NET, to name a few of the
more popular office LAN architectures, point to many
choices for OEMs and end users.

WANs-known by some as, Global Area Networks
(GANs)-are most commonly associated with the
worldwide analog telephone system. The ,category also
includes a number of other segments, such as satellite
and microwave communications, traditional networks
(like mainframe-to-mainframe connections), modems,
statistical multiplexers, and front-end communications
processors. The lion's share of nodes-electronic network connections-in the WAN arena, however, resides in the telecommunications segment. This is where
the emerging ISDN (Integrated Services Digital Network) standard comes into focus as the most visible
portion of the WAN marketplace.

A similar situation exists in the factory., While the
Manufacturing Automation Protocol (MAP) standard
is coalescing around the leadership of General Motors,

x

inter

AP-302

Boeing, and others, a variety of proprietary solutions
also abound. The challenge is for a complete set of interfaces to emerge that can potentially tie all of these
networks together in-and among-the office, factory,
and lab environments.

the LAN segment, which should grow from 34.5% of
the total silicon microcommunications market in 1985
to 44.5% of the expanded pie in 1989.
Opportunities abound for microcommunications suppliers as the migration to silicon continues. And
perhaps no VLSI supplier is as well-positioned in this
marketplace as Intel, which predicts that 50% of its
products will be microcommunications-related bY1990.
The key here is the corporation's ability to bridge the
three issues that contribute to the communications bottleneck: standards, cost-performance considerations,
and the completeness of microcomputer and microcommunications product offerings.

The final third of the network trinity is the Small Area
Network (SAN). This category is concerned with communications over very short distances, usually not exceeding 100 meters. SANs most often deal with chip-tochip or chip-to-system transfer of information; they are
optimized to deal with real-time applications generally
managed by microcontrollers, such as those that take
place on the factory floor among robots at various
workstations.

INTEL AND VLSI: THE
MICROCOMMUNICATIONS MATCH

SANs incorporate communications functions that are
undertaken via serial backplanes in microelectronic
equipment. While they represent a relatively small market in 1986 when compared to WANs and LANs, a
tenfold increase is expected through 1990. SANs will
have the greatest number of nodes among network applications by the next decade, thanks to their preponderance in many consumer products.

Intel innovations helped make the microcomputer revolution possible. Such industry "firsts" include the
microprocessor, the EPROM, the E2PROM, the
microcontroller, development systems, and single board
computers. Given this legacy, it is not surprising that
the corporation should come to the microcommunications marketplace already equipped with a potent arsenal of tools and capabilities.

While factory applications will make up a large part of
the SAN marketplace probably the greatest contributor
to growth will be in automotive applications. Microcontrollers are now used in many dashboards to control
a variety of engine tasks electronically, but they do not
yet work together in organized and efficient networks.
As Intel's Gordon Moore commented earlier this year
to the New York Society of Security Analysts, when
this technology shifts into full gear during the next decade, the total automobile electronics market will be
larger than the entirel semiconductor market was in
1985.

The first area centers on industry standards. As a VLSI
microelectronic leader, Intel has been responsible for
driving many of the standards that are accepted by the
industry today. And when not actually initiating these
standards, Intel has supported other existing and
emerging standards through its longtime "open systems" philosophy. This approach protects substantial
customer investments and ensures easy upgradability
by observing compatibility with previous architectures
and industry-leading standards.

MARKET OPPORTUNITIES

Such a position is accentuated by Intel's technology relationships and alliances with many significant names
in the microcommunications field. Giants like AT&T
in the ISDN arena, General Motors in factory networking, and IBM in office automation all are working
closely with Intel to further the standardization of the
communications interfaces that are so vital to the
world's networking future.

Such growth is also mirrored in the projections for the
WAN and LAN segments, which, when combined with
SANs, make up the microcommunications market pie.
According to Intel analysts, the total silicon microcommunications market in 1985 amounted to $522 million.
By 1989, Intel predicts this figure will have expanded to
$1290 million, representing a compounded annual
growth rate of 25%.

Cost/performance considerations also point to Intel's
strengths. As a pioneer in VLSI technology, Intel has
been at the forefront of achieving greater circuit densities and performance on single pieces of silicon: witness
the 275,000 transistors housed on the 32-bit 80386, the
highest performance commercial microprocessor ever
built. As integration has increased, cost-per-bit has decreased steadily, marking a trend that remains consistent in the semiconductor industry. And one thing is

And although the WAN market will continue to grow
at a comfortable rate, the SAN and LAN pieces of the
pie will increase the most dramatically. Whereas SANs
represented only about 12.5% ($65 million) in 1985,
they could explode to 22.5% ($290 million) of the larger pie by 1989. This growth is paralleled by increases in

xi

AP-302

certain: microcommunications has a healthy appetite
for transistors, placing it squarely in the center of the
VLSI explosion.

That leadership extends beyond products. Along with
its own application software, Intel is promoting expansion through partnerships with many different independent software vendors (ISVs), ensuring that the necessary application programs will be in place to fuel the ,
gains provided by the silicon "engines" residing at the
interface level. And finally, the corporation's commit-'
ment to technical support training, service, and its
strong force of field applications engineers guarantees
that it will back up its position and serve the needs that
will continue to spring up as the microcommunications
evolution becomes a reality.

But it is in the final area-completeness of technology
and products-where Intel is perhaps the strongest. No
other microelectronic vendor can point to as wide an
array of, products positioned across the various, segment: that comprise the microelectronic marketplace.
Whether it be leadership in the WAN marketplace as
the number one supplier of merchant telecommunications components, strength in SANs with world leadership in microcontrollers, or overall presence in the
LAN arena with complete solutions in components,
boards, software, and systems, Intel is a vital presence
in the growing microcommunications arena.

Together, all the market segment alluded to in this article comprise the world of microcommunications, a
world coming closer together every day as the web of
networking solutions expands-all thanks to the technological ties that bind, reaching out to span the globe
with silicon.

xii

Local Area Networks

1

APPLICATION
NOTE

AP-235

November 1986

An 82586 Data Link Driver

CHARLES YAGER

Order Number: 231421-002
1-1

inter

AP-235

INTRODUCTION
This application note describes a design example of an
IEEE 802.2/802.3 compatible Data Link Driver using
the 82586 LAN Coprocessor. The design example is
based on the "Design Model" illustrated in "Programming the 82586". It is recommended that before read'ing this application note, the reader clearly understands
the 82586 data structures and the Design Model given
in "Programming the 82586".
'
"Programming the 82586" discusses two basic issues in
the design of the 82586 data link driver. The first is
how the 82586 handler fits into the operating system.
One approach is that the 82586 handler is treated as a
"special kind of interface" rather than a standard I/O
interface. The special interface means a special driver
that has the advantage of utilizing the 82586 features to
enhance performance. However the performance enhancement is at the expense of device dependent upper
layer software which precludes the use of a standard
I/O interface.
The second issue "Programming the 82586" discusses
is which algorithms to choose for the CPU to control
the 82586. The algorithms used in this data link design
are taken directly from "Programming the 82586".
Command processing uses a linear static list, while receive processing uses a linear dynamic list.
The application example is written in C and uses the
Intel C compiler. The target hardware for the Data
Link Driver is the iSBC 186/51 COMMputer, however
a version of the software is also available to run on the
LANHIB Demo board.

1.0 FITTING THE SOFTWARE INTO
THE OSI MODEL
The application example consists of four software modules:

OSI REFERENCE
MODEL LAYERS
APPLICATION
PRESENTATION

• Data Link Driver (DLD): drives the 82586, also
known as the 82586 ~andler.
• Logical Link Control (LLC): implements the IEEE
802.2 standard.
• User Application (UAP): exercises the other software modules and runs a specific application.
• C hardware support: written in assembly language,
supports the Intel C compiler for I/O, interrupts,
,_ and run time initialization for target hardware.
Figure 1 illustrates how these software modules combined with the 82586, 82501 and 82502 complete the
first two layers of the OSI model. The 82502 implements an IEEE 802.3 compatible transceiver, while the
82501 completes the Physical layer by performing the
serial interface encode/decode function.
The Data Link Layer, as defined in the IEEE 802 standard documents, is divided into two sublayers: the Logical Link Control (LLC) and the Medium Access Control (MAC) sublayers. The Medium Access Control
sublayer is further divided into the 82586 Coprocessor
plus the 82586 Handler. On top of the MAC is the LLC
software module which provides IEEE 802.2 compatibility. The LLC software module implements the Station Component responses, dynamic addition and deletion of Service Access Points (SAPs), and a class 1 level
of service. (For more information on the LLC sublayer,
refer to IEEE 802.2 Logical Link Control Draft Stan, dard.) The class 1 level of service provides a connectionless datagram interface as opposed to the class 2
level of service which provides a connection oriented
level of service similar to HDLC Asynchronous Balanced Mode.
On top of the Data Link Layer is the Upper Layer
Communications Software (ULCS). This contains the
Network, Transport, Session, and Presentation Layers.
These layers are not included in the design example,
therefore the application layer of this ap note interfaces
directly to the Data Link layer.

_-----------------EuA~P~U~~~~~~UL~E~~=~

~~~RAP~:'::IotUNlCAlION

---------"-,-,~:'~~~AC-~t-, ~~~ ~~~~~~ ~LOGICAL
M

SESSION

, / ' ,',',',','

UNK CONTROL
82586 HANDLER
DATA LINK COPROCESSOR
ENCODE/DECODE (ESI)

TRANSPORT
NETWORK
DATA LINK
PHYSICAL

,

':,',',"

"

TRANSCEIVER CABLE

HARDWARE CONNECTOR

Figure 1. Data Link Driver's Relationship to 051 Reference Mode 1
1-2

SOFTWARE

AP-235

} APPLICAnON

DATA LINK

TERMINAL EMULATOR
AND
STATION MONITOR

OLD MODULE
82586

PHYSICAL

231421-2

Figure 2. Block Diagram of the Hardware and Software
The application layer is implemented in the User Application (UAP) software module. The UAP module operates in one of three modes: Terminal Mode, Monitor
Mode, and High Speed Transmit Mode. The software
initially enters a menu driven interface which allows
the program to modify several network parameters or
enter one of the three modes.

The C_Assy_Support module has a run time start off
function which loads the DLD data segment into a
global variable SEGMT_. This data segment is used
by the 82586 Handler for address translation purposes.
The ·82586 uses a flat address while the 80186 uses a
segmented address. Any time a conversion between
82586 and 80186 addresses are needed the SEGMT_
variable is used.

The Terminal Mode implements a virtual terminal with
datagram capability (connectionless "class I" service).
This mode can also be thought of as an async to IEEE
802.3/802.2 protocol converter.

Pointers for the 80186 in the large model are 32 bits,
segment and offset. All the 82586 link pointers are 16
bit offsets. Therefore when trading pointers between the
82586 and the 80186, two functions are called:
Offset (ptr), and Build_Ptr (offset). Offset (ptr) takes a
32 bit 80186 pointer and returns just the offset portion
for the 82586 link pointer. While Build_Ptr (offset)
takes an 82586 link pointer and returns a 32 bit 80186
pointer, with the segment part being the SEGMT_
variable. Offset () and Build_Ptr() are simple functions written in assembly language included in the C_
Assy_Support module.

The Monitor Mode provides a dynamic update on the
terminal of 6 station related parameters. While in the
monitor mode, any size frame can be repeatedly transmitted to the cable in a software loop.
High Speed Transmit Mode transmits frames to the cable as fast as the software possibly can. This mode demonstrates the throughput performance of the Data Link
Driver.

In the small model, Offset ( ) and BuilLPtr( ) are not
needed, but the variable SEGMT..:... is still needed for
determining the SCB pointer in the ISCP, and in the
Transmit and Receive Buffer Descriptors.

The UAP gathers network statistics in all three modes
as well as when it is in the menu. In addition, the UAP
module provides the capability to alter MAC and LLC
addresses and re-initialize the data link.. (Figure 2
shows a combined software and hardware block diagram.)

3.0 THE 82586 HANDLER

2.0 LARGE MODEL COMPILATION

3.1 The Buffer Modei

All the modules in this design example are compiled
under the Large Model option. This has the advantages
of using the entire 1 Mbyte address space, and allowing
the string constants to be stored in ROM. In the Large
Model it is important to consider that the 82586's data
structures, SCB, CB, TBD, FD, and RBD, must reside
within the same data segment. This data segment is
determined at locate time.

The buffer model chosen for the 82586 Handler is the
"Design Model" as described in "Programming the
82586". This is based on the 82586 driver as a special
driver rather than as a standard driver. Using this approach the ULCS directly accesses the 82586's Transmit and Receive Buffers, Buffer Descriptors and Frame
Descriptors. This eliminates h.lffer copying. Transmit
and receiver buffer passing is done entirely through
pointers.
1-3

AP·235

The only hardware dependencies between the Data
Link and ULCS interface are the buffer structures. The
ULCS does not handle the 82586's CBs, SCB or initiali-'
zation structures. To isolate the data link interface from
any hardware dependencies while still using the design
model, another level of buffer copying must be introduced. For example, when the ULCS,transmits a frame
it would have to pass its own buffers to the data link.
The data link then copies the data from ULCS buffers
into 82586 buffers. When a frame is received, the data
link copies the data from the 82586's buffers into the
ULCS buffers. The more copying that is done the slower the throughput. However, this may be the only way
to fit the data link int,o the operating system. The 82586
Handler can be made hardware independent by adding
a receive and transmit function to perform the buffer
copying.

rupts the handler. The handler passes a FD pointer to
the ULCS. Linked to the FO is one or more RBDs and
RBs. The ULCS extracts what it needs from the FD,
RBDs and RBs, and returns the FD pointer back to the
handler. The handler places the'FD and RBDs back
into Jhe free RFA pool.

3.2 The Handler Interface
The handler interface provides the following basic functions:
•
•
•
•
•

The 82586 Handler allocates buffers from two pools of
memory: the Transmit pool, and the Receive pool as
illustrated in Figure 3. The Transmit pool contains
Transmit Buffer Descriptors (fBDs) and Transmit
Buffers (TBs). The Receive pool contains Frame Descriptors' (FOs), Receive, Buffer Descriptors, (RBDs),
and Receive Buffers (RBs).

Figure 4 lists the Handler Interface functions.
On power up, the initialization function is called. This
function initializes,the 82586, and performs diagnostics.
After initialization, the handler is ready to transmit and
receive frames, and add ~d delete multicast addresseS.
To send a frame, the ULCS gets one or more transmit
buffers from the handler, fills them with data, and calls
the send function. When a frame is received, the handler calls a receive function in the ULCS. The ULCS
receive function removes the information it needs and,
returns the receive buffers to the handler. The addition
and deletion of multicast addresses can be done "on the
fly" any .time after initialization. The receiver doesn't
have to be disabled when this is done.

UPPER LAYER
COMMUNICATIONS SOFTWARE
SEND

G~'·1
POOL

~
TB

I

initialization
sending and receiving frames'
adding and deleting multicast addresses
getting transmit buffers
returning receive buffers

RECEIVE

0

~~

DATA

I

TAIL
< ......

Any frames addressed to active SAPs are passed directly to them. The Station Component will not respond to
SAP addressed frames. Therefore it is the responsibility
of the SAPs to recognize and respond to frames addressed to them. When a SAP transmits a frame, it
builds the IEEE 802.2 frame itself and calls the Handler's Send_Frame() function directly. The LLC
module is not used for SAP frame transmission. The
only functions which the LLC module implement are
the dynamic addition and deletion of DSAPs, multiplexing the frames to user SAPs, and the Station Component command recognition and responses. This is
one implementation of the IEEE 802.2 standard. Other
implementations may have the LLC module do more
functions, such as SAP command recognitions and responses. A list of the functions included in the LLC
module is as follows:

~

IOSAP I SSAP I CONTROL I D;";-I

LLC Functions

231421-14

IniLLlc()

. Description

Initializes the DSAP
address table and calls
IniL586()
Add_Dsap_
Add a DSAP address to
Address (dsap, pfunc) the active list
dsap - DSAP address
pfunc - pOinter to the
SAP function
Delete a DSAP address
Delete-DsapAddress (dsap)
dsap - DSAP address
Recv-Frame (pfd)
Receives a frame from
the 82586 Handler
pfd - Frame Descriptor
Pointer
Station-Component- Generates a response to
Response (pfd)
a frame addressed to the
Station Component
pfd - Frame Descriptor
Pointer

Figure 16. IEEE 802.2 Class 1 Frame Format

From Figure 15 it can be seen that there are no LLC
class 1 VI responses because information frames are not
acknowledged at the data link level. The only command frames that may require responses are XID and
TEST. If a command frame is addressed to the Station
Component, it checks the control field to see what type
of frame it is. If it's an XID frame, the Station Cotnponent responds with a class 1 XID response frame. If it's
a TEST frame, the Station Component responds with a
TEST frame, echoing back the data it received. In both
cases, the response frame is addressed to the source of
the command frame.

1-14

inter

Ap·235

4.1 Adding and Deleting LSAPs

Terminal Mode - implements a virtual terminal with
datagram capability (connectionless "class 1" service).
This mode can also be thought of as an async to IEEE
802.2/802.3 protocol converter.

When a user process wants to add a LSAP to the active
list, the process calls Add_Dsap-Address(dsap,
pfunc). The dsap parameter is the actual DSAP address, and the pfunc parameter is the address of the
function to be called when a frame with the associated
DSAP address is received.

Monitor Mode - allows the station to repeatedly transmit any size frame to the cable. While in the Monitor
Mode, the terminal provides a dynamic update of 6
station related parameters.

The LLC module maintains a table of active dsaps
which consists of an array of structures. Each structure
contains two members: stat - indicates whether the address is free or inuse, and (*p_sap_func)() contains
the address of the function to call. The index into the
array of structures is the DSAP address. This speeds up
processing by eliminating a linear search. Delete_
Dsap-Address (dsap) simply uses the DSAP index to
mark the stat field FREE.

High Speed Transmit Mode - sends frames to the cable
as fast as the software possibly can. This mode demonstrates the throughput performance of the Data Link
Driver.
Change Transmit Statistics - When Transmit Statistics
is on several transmit statistics are gathered during
transmission. If Transmit Statistics is off, statistics are
not gathered and the program jumps over the section of
code in the interrupt routine which gathers these statistics. The transmission rate is slightly increase when
Transmit Statistics is off.

5.0 APPLICATION LAYER
For most networks the application layer resides on top
of several other layers referred to here as ULCS. These
other layers in the OSI model run from the network
layer through the presentation layer. The implementation of the ULCS layers is beyond the scope of this
application note, however Intel provides these layers as
well as the data link layer with the OpenNET product
line. For the purpose of this application note the application layer resides on top of the data link layer and its
use is to demonstrate, exercise and test the data link
layer design example.

Print All Counters - Provides current information on
the following counters.
Good frames transmitted:
Good frames received:
CRC errors r~ceived:
Alignment errors received:
Out of Resource frames:
Receiver overrun frames:

Each time a frame has been successfully transmitted the
Good frames transmitted count is incremented. The
same holds true for reception. CRC, Alignment, Out of
Resources, and Overrun Errors are all obtained from
the SCB. Underrun, lost CRS, SQE error, Max retry,
and Frames that deferred are all transmit statistics that
are obtained from the Transmit command status word.
82586 Reset is a count which is incremented each time
the 82586 locks up. This count has never normally been
incremented.

There can be several processes sitting on top of the data
link layer. Each process appears as a SAP to the data
link. The UAP module, which implements the application layer, is the only SAP residing on top of the data
link layer in this application example. Other SAPs
could certainly be added such as additional "connectionless" terminals, a networking gateway, or a transport layer, however in the interest of time this was not
done:

5.1 Application Layer Human Interface
The UAP provides a menu driven human interface via
an async terminal connected to port B on the iSBC
186/51 board. The menu of the commands is listed in
Figure 17 along with a description that follows:
T - Terminal Mode
X - 'High Speed Transmit Mode
P - Print All Counters
A - Add a Multicast Address
S - Change the SSAP Address
N - Change Destination Node Address
R - Re-Initialize the Data Link

M - Monitor Mode
V - Change Transmit Statistics
C - Clear All Counters
Z - Delete a Multicast Address
D - Change the DSAP Address
L - Print All Addresses
B - Change the Number Base

Figure 17. Menu of Data Link Driver Commands

1-15

inter

AP-235

Clear All Counters - Resets all of the counters.

reinitialized, and the selftest diagnostic and loopback
tests are executed. The results of the diagnostics are
printed on the terminal. The possible output messages
from the 82586 selftest diagnostics are:

AddlDelete Multicast Address - Adds and Deletes
Multicast Addresses.
Change SSAP Address - Deletes the previous SSAP
and adds a new one to the active list. The SSAP in this
case is this stations LSAP. When a frame is received,
the DSAP address in the frame received is compared
with any active LSAPs on the list. The SSAP is also
used in the SSAP field of all transmitted frames.

Passed Diagnostic Self Tests
Failed: Self Test Diagnose Command
Failed: Internal Loopback Self Test
Failed: External Loopback Self Test
Failed: External Loopback Through Transceiver Self
Test

Change DSAP Address - Delete the old DSAP and add
a new one. The DSAP is the address of the LSAP
which all transmit frames are sent to.

Change Base - Allows all numbers to be displayed in
Hex or Decimal.

Change Destination Node Address - Address a new
node.

5.2 A Sample Session

Print All Addresses - Display on the terminal thestation address, destination address, SSAP, DSAP, and all
multicast addresses.

The following text was taken directly from running the
Data Link software on a 186/51 board. It begins with
the iSDM monitor signing on and continues into executing the Data Link Driver software.

Re-initialize Data Link - This causes the Data Link to
completely reinitialize itself. The 82586 is reset and

iSDM 86 Monitor, Vl.O
Copyright 1983 Intel Corporation
.G DOOO:6
**********************************************************.*****

• 82586 IEEE 802.2/802.3 Compatible Data Link Driver •

•

•

***.*******************.***.*********.***.***** ••••••••••• ** ••••

Passed Diagnostic Self Tests
Enter the Address of the Destination Node in Hex -> 00AA0000179E
Enter this Station's LSAP in Hex - > 20
Enter the Destination Node's LSAP in Hex - > 20
Do you want to Load any Multicast Addresses? (Y orN) -> Y
Enter the Multicast Address in Hex - > OOAAOOllllll
Would you like to add another Multicast Address? (Y or N) -> N
This Station's Host Address is: 00AA00001868
The Address of the Destination Node is: 00AA0000179E
This Station's LSAP Address is: 20
The Address of the Destination LSAP is: 20
The following Multicast Addresses are enabled: OOAAOOllllll
1-16

inter

AP-235

CO!11lllands are:
T - Terminal Mode

M - Monitor Mode

x-

v-

High Speed Transmit Mode

Change Transmit Statistics

P - Print All Counters

C - Clear All Counters

A - Add a Multicast Address

Z - Delete a Multicast Address

S - Change the SSAP Address

D - Change the DSAP Address

N - Change Destination Node Address

L - Print All Addresses

R - Re-Initialize the Data Link

B - Change the number Base

Enter a command, type H for Help - > P
Good frames transmitted:

24

Good frames received:

1

CRC errors received:

o

Alignment errors received: 0

Out of Resource frames:

o

Receiver overrun frames·:

0

82586 Reset:

o

Transmi t underrun frames:

0

Lost. CRS:

o

SQE errors:

9

Maximum retry:

o

Frames that deferred:

4

Enter a command, type H for Help --> T
Would you like the local echo on? (Y or N) --> Y
This program will now enter the terminal mode.
Press 'C then CR to return back to the menu
Hello this is a test.

*'

,"C CR
Enter a command, type H for Help --> M
Do you want this station to transmit? (Y or N) --> Y
Enter the number of data bytes in the frame --> 1500
Hit any key to exit Monitor Mode.
of Good
Frames
Transmitted
#

32

#

of Good
Frames
Received

o

CRC
Errors

Alignment
Errors

00000

I' CR "'
Enter a command, type H for Help --> X
Hit any key to exit High Speed Transmit Mode.

*'

I' CR
Enter a command, type H for Help --> R
Passed Diagnostic Self Tests
1-17

00000

Receive
No
Resource Overrun
Errors Errors
00000

00000

inter

AP-235

5.3 Terminal Mode
The Terminal mode buffers characters received from
the terminal and sends them in a frame to the cable.
When a frame is received from the cable, data is extracted and sent to the terminal. One of three events
initiate the UAP to send a frame providing there is data
to send: buffering more than 1500 bytes, receiving a
Carriage Return from the terminal, or receiving an interrupt from the virtual terminal timer.
The virtual terminal timer employs timer 1 in the 80130
to cause an interrupt every .125 seconds. Each time the
interrupt occurs the software checks to see if it received
one or more characters from the terminal. If it did, then
it sends the characters in a frame.
The interface to the async terminal is a 256. byte software FIFO. Since the terminal communication is full
duplex, there are two half duplex FIFOs: a Transmit
FIFO and a Receive FIFO. Each FIFO uses two func-'
tions for I/O: Fifo_ln() and Fifo_Out(). A block
diagram is displayed in Figure 18.
The serial I/O for the async terminal interface is always
polled except in the Terminal mode where it is interrupt driven. The Terminal mode begins by enabling the
8274 receive interrupt but leaves the 8274 transmit interrupt disabled. This way any characters received from
the terminal will cause an interrupt. These 'characters
are then placed in the Transmit FIFO. The only time
the 8274 transmit interrupt is enabled is when the ReFunction
FIFO_T_IN()
FIFO_T_OUT( )
FIFO_R_IN( )
FIFO_R_OUT( )

ceive FIFO has data in it. The receive FIFO is filled
from frames being received from the cable. Each time a
transmit interrupt occurs a byte is removed from the
Receive FIFO and written to the 8274. When the Receive FIFO empties, the 8274 transmit interrupt is disabled.
The flow control implemented for the terminal interface is via RTS and CTS. When the Transmit FIFO is
full, RTS goes inactive preventing further reception of
characters (see Table 1). If the Receive FIFO is full,
receive frames are lost because there is no way for the
data link using class 1 service to communicate to the
remote station that the buffers are full. Lost receive
frames are accounted for by the Out of Resources
Frame counter.
The Async Terminal bit rate sets the throughput capability of the station in the terminal mode because the
bottle neck for this network is the RS232 interface. Using this fact a simple test was conducted to verify the
data link driver's capability of switching between the
receiver's No Resource state and the Ready State. For
example if station B is ~ending frames in ·the High
Speed Transmit mode to station A which is in the Terminal mode, frames will be lost in station A. Under
these circumstances station A's receiver will be switching from Ready state to' Out of Resources ~tate. The
sum of Good frames received plus Out of Resource
frames from station A should equal Good frames transmitted from station B; unless there were any underruns
or overruns.

Table 1 FIFO State Table
Next State
Present State
EMPTY
IN USE
IN USE
FULL
FULL
IN USE
IN USE
EMPTY
EMPTY
IN USE
FULL
IN USE
IN USE
FULL
IN USE
EMPTY

Action
Start Filling Transmit Buffer
Shut Off RTS
Enable RTS
Stop Filling Transmit Buffer
Turn on Txlnt
Stop Filling FIFO from Receive Buffer
Start Filling FIFO from Receive Buffer
Turn Off Txlnt

SEND FRAMES

RECEIVE FRAMES

ASYNC
TERMINAL

231421-15

Figure 18
1-18

inter

AP-235

Recv_Data_l() will discard any UI frames received
unless it is in the Terminal Mode. When in the Terminal Mode, Recv_Data_l() skips over the IEEE 802.2
header information and uses the length field to determine the number of bytes to place in the Receive FIFO.
Before a byte is placed in the FIFO, the FIFO status is
checked to make sure it is not full. Recv_Data_l()
will move all of the data from the frame into the Receive FIFO before returning.

5.3.1 SENDING FRAMES

The Terminal Mode is entered when the Terminal_
Mode() function is called from the Menu interface.
The Terminal_Mode( ) function is one big loop, where
~ach pass sends a frame. Receiving frames in the Ter·
minal Mode is handled on an interrupt driven basis
which will be discussed next.
The loop begins by getting a TBD from the 82586 handler. The first three bytes of the first buffer are loaded
with the IEEE 802.2 header information. The loop then
waits for the Transmit FIFO to become not EMPTY,
at which point a byte is removed from the Transmit
FIFO and placed in the TBD. After each byte is removed from the Transmit FIFO several conditions are
tested to determine whether the frame needs to be
transmitted, or whether a new buffer must be obtained.
A frame needs to be transmitted if: a Carriage Return is
received, the maximum frame length is reached, or the
send_frame flag is set by the virtual terminal timer. A
new buffer must be obtained if none of the above is true
and the max buffer size is reached.

When a frame is received by the 82586 handler an interrupt is generated. While in the 82586 interrupt routine the receive frame is passed to the LLC layer and
then to the UAP layer where the data is placed in the
Receive FIFO by Recv_Octal_Data_l(). Since
Recv_Data_l() will not return until all of the data
from the frame has been moved into the Receive FIFO,
the 8274 transmit interrupt must be nested at a higher
priority than the 82586 interrupt to prevent a software
lock. For example if a frame is received which has more
than 256 bytes of data, the Receive FIFO will fill up.
The only way it can empty is if the 8274 interrupt can
nest the 82586 interrupt service routine. If the 8274
could not interrupt the 82586 ISR then the software
would be stuck in Recv_Data_l() waiting for the
FIFO to empty.

If a frame needs to be sent the last TBD's EOP bit is set
and its buffer count is updated. The 82586 Handler's
Send_Frame() function is called to transmit the
frame, and continues to be called until the function returns TRUE.

5.4 Monitor Mode
The Monitor Mode dynamically updates 6 station related parameters on the terminal as shown below.

The loop is repeated until a 'C followed by a Carriage
Return is recieved.

The Monitor_Mode() function consists of one loop.
During each pass through the loop the counters are
updated, and a frame is sent. Any size frame can be
transmitted up to a size of the maximum number of
transmit buffers available. Frame sizes less than the
minimum frame length are automatically padded by the
82586 Handler.

5.3.2 RECEIVING FRAMES

Upon initialization the UAP module calls the Add_
Dsap--Address(dsap, pfunc) function in the LLC module. This function adds the UAP's LSAP to the active
list. The pfunc parameter is the address of the function
to call when a frame has been received with the UAP's
LSAP address. This function is Recv_Data_lO.
Recv_Data_l() looks at the control field of the
frame received and determines the action required.

The data in the frames transmitted in the Monitor
Mode are loaded with all the printable ASCII characters. This way when one station is in the Monitor Mode
transmitting to another station in the Terminal Mode,
the Terminal Mode station will display a marching pat~
tern of ASCII characters.

The commands and responses handled by Recv_
Dat~l() are the same as the Station Component's
commands and responses given in Figure 15. One difference is that Recv-.Dat~l() will process a UI
command while the Station Component will ignore a
UI command addressed to it.
# of Good
Frames
Transmitted

# of Good
Frames
Received

CRC
Errors

Alignment
Errors

No
Resource
Errors

Receive
Overrun
Errors

32

a

00000

00000

00000

00000

1-19

intJ

AP-235

5.5 High Speed Transmit Mode
The High Speed Transmit Mode demonstrates the
throughput performance of, the 82586 Handler. The
Hs-'Cmit_Mode() function operates in a tight loop
which gets a TBD, sets the EOF bit, and calls Send_
Frame( ). The flow chart for this loop is shown in Figure 19.
The loop is exited when a character is received from the
terminal. Rather than· polling the 8274 for a receive

buffer full status, the 8274's receive interrupt is used.
When the Hs-'Cmit~ode( ) function is entered, the
hs~tat flag is set true. If the 8274 receive interrupt
occurs, the hs_stat flag is set false. This way the loop
only has to test the hs_stat flag rather than calling
inb( ) function each pass through the loop to determine
whether a character has been received.
, The performance measured on an 8 MHz 186/51 board
is 593 frames per second. The bottle neck in the
throughput is the software and not the 82586. The size
of the buffer is not relevant to the transmit frame rate.
Whether the buffer size is 128 bytes or 1500 bytes,
linked or not, the frame rate is still the same. Therefore
assuming a 1500 byte buffer at 593 frames per second,
the effective data rate is 889,500 bytes per second.
This can easily be demonstrated'by using two 186/51,
boards running the Data Link software. The receiving
stations counters should be cleared then placed in the
Monitor mode. When placing it in the monitor mode,
transmission should not be enabled. When the other
station is placed in the High Speed Transmit Mode a
timer should be started. One can use a stop watch to
determine the time interval for transmission. The frame
rate is determined by dividing the number of frames
received in the Monitor station by the time interval of
transmission.

231421-16

Figure 19. High 'Speed Transmit Mode
FlowChart

1-20

inter

AP-235

APPENDIX A
COMPILING, LINKING, LOCATING, AND RUNNING THE
,
SOFTWARE ON THE 186/51 BOARD
*********

*""******

Instructions for using the 186/51 board

Use 27128A for no wait state operation, 27128s can be used but wait states will have to be added.
Copy HLBYT and LO.BYT files into EPROMs
PROMs go into U34 - HI.BYT and U39 - LO.BYT on the 186/51 board

JUMPERS REQUIRED

WIRE WRAP

Jumper the 186/51 board for 16K byte PROMs in U34
and U39 Table 2-5 in 186/51 HARDWARE REFERENCE MANUAL (Rev-DOl)

E36-E47IN
E39-E44IN
E79-E45IN

186/51(E5)

E151-E152 OUT
E152-E150 IN
E94-E95IN
E100-E1061N
E107-E113IN
E133-E134IN

186/51 (5)/186/51

E199-E203 OUT
E203-E191 IN
E120-E119IN
E116-E1121N
E111-E1071N
E94-E93IN

USE SDM MONITOR
The SDM Monitor should have the 82586's SCP
burned into ROM. The ISCP is located at OFFFOH.
Therefore for the SCP the value in the SDM ROM
should be:
ADDRESS
FFFF6H
FFFF8H
FFFFAH
FFFFCH
FFFFEH

also change interrupt priority jumpers - switch 8274
and 82586 interrupt priorities
E36-E44 OUT
E39-E47 OUT
E37-E45 OUT

E43-E50 IN
E46-E47IN
E90-E4BIN

E43-E47 OUT
E46-ESOOUT
E44-E4BOUT

DATA
XXOOH
XXXXH
XXXXH
FFFOH
XXOOH

To run the program begin execution at ODOOO:6H

1-21

inter

AP-235

I.E. G DOOO:6
GOOD LUCK!

-

..........

submit file for compiling one module:

••••••••••

run
cc86.86 :F6:%O LARGE ROM DEBUG DEFINE(DEBUG) include(:F6:)

exit
••••••••••

submit file for linking and locating:

.,.. ........

run
l1nk86

:F6:assy.obj, :F6:dld.obj, :F6:llc.obj, &

:F6:uap.obj, lclib.lib to :F6:dld.lnk segsize(stack(4000h)) notype
10c86 :F6:dld.lnk to :F6:dld.loc&
initcode (ODOOOOH) start (begin) order(classes(data, stack, code)) &
addresses(classes(data(3000H), stack(OCBOOH), code(OD0020H)))
oh86 :F6:dld.loc to :F6:dld.rom
exit

••••••••••

submit file for burning EPROMs using IPPS:

ipps
i

86

f :F6:dld.rom (OdOOOOh)
3
2
1

o to

:F6:1o.byt

Y

1 to :F6 :h1. byt,
y

t 27128
9

c :F6:lo.byt t p
n

C :F6:hi.byt t p
n

exit

1-22

••••••••••

inter

AP-235

IPCO/USR/CHUCK/CSRC/DLD. H

.

1 •••••••• *** ••••••••••••••••••••••••••* ••••••••••••••• •••••••••••••••••••

·••

*

••••••••_••••••••••••••••••••••••••••••••••••••••••••••••••**** •••••••••••1

.dofino INUSE

o

.CI.'ine EWTV

I
2

.dofino
.dofino
.d •• in.
.dofino
.define

FULL
FREE

I

TRUE

I

FALSE
NULL

o
OIFFFF

.define RBUF _SIZE
.deflne TBUF _SIZE
.define ADD....L£N
ed.'in. f'IIUL TI_ADDR_CNT

I:2B /. ,..cI1vI bu.f .... sizl . /
128 /* 't"Anl.it bu'fl" t1z1 *1
6
16

'"ped., unsigned short int u_Iho1't'

'*

"'Ilults '1"011 T'lt_LinkO:

laadld into Self_T'lt chI'"

.d.fin. PASSED

.deflne
.doflno
.doflno
.doflne
/* F .... m.
ed,'in.
ed.'in.

ed"ine

edl'ine
ed"ine

FAILEDJlIAQNOSE
FAILED..L/'BK_INTERNAL
FAILED_LPBK...EXTERNAL
FAILED..L/'BK_TRANSCEIYER

*'

CallYUndl
UI
XlD
TEST
P.J' _BIT
C_RJlIT

ed"in.

*'

0
3
4

'*

0103
OlAF
0lE3
OlIO
0101

OSAP_CNT

I

a

*' *'*'

/* UnnUllbll"ld Information F,.. ... I
ElchAn •• Identification

1* R.llat. Loopblc Ie T.lt
1* Poll/Fin.1 8it POlltion

'*
S

COlMland/R •• pon •• bit in SSAP

*'

*'

I . Numbe" of .llowabl. DSAPsl mu.t b• • Multipl.
of 2**N, • nd DSAP .dd" •••••••• ign.d must b •

divi.ibl. bU 2*.(S-N).
(I .•. the N L.SB. must b. 0) *'

*'

_d.fin.

DSAP _SHIFT

:I

I · DSAP _SHIFTS mu.t .qu.l S-N

.d.fin.

XlD_LENQTH

6

I. Numb.,. a. Info b,t •• '01' KID R.spon ••

'* S".t.m

Con.igu1"etion Pointe,. SCP

.t"uet BCP

•,.••• *'

*'

'*

u_short .,.bull
82:586 bus ,ddth, 0 - 16 bit.
1 - S bit • • ,

231421-17

1-23

intJ

AP·235

IPCD/USR/CHUCK/CBRC/DLD. H

'*

u_oh01't JunH2J,
u_shol"' :l.epl,
low.,.. 16 bit. D' i.ep .dd" ••• *1
u_.hort t.cph,
/. uPP." B bit. of i.ep .dd.,. ••• *1
),

'* Int ....... di.". S,.t.m Configul'ation Point.,. ISCP *'
ot1'uct ISCP (

)

b.'a",. tt. fit,. ....
.'t."
,....••cant1"ol
d inl *'
.,.t
blocll . /
.v.te.. cont'rol blocll . ,

U_.hD ... t off •• t

/ ••• t to 1 bl\l cpu
c 1•• .,..d ltV 82:t86
J
/ . of, •• t of

u_,hort ba •• 1
u_,ho ... ' .....a

J
J

u_'ho"t lIu ... ,

,

'* b••• of

CA,

1* Sv.hm Cont1'ol Blod SCB *1

ot1'uct SCB

u_.hort .tat,
u_.ho"t
u_'hort: cll1_off •• t,
u_.ho,., 1"._o •••• t,

,.d,

U_.hD'I"t '1"C_.,,1'"

u_.ho"t .In_err.,
u_,ho ... t
u_,ho,., DY1' _e,.r'J

'*'*
'*'* o••••tt
'* CRt

"',C_."''I"''

),

stT'uct

CB

u_sho1't
u_sho ... t
u_sho ... t
u_shoT't
u_sho ... t:

s,.t.
cad,
linkl,
p."'1I11

pa"tn:z,

*' 0' *'
*'

accu.ulated
/. Al itn ..ent ."1'ora
F1'atn•• last becaus.
no R.sau ... c ••
Ov .... 1'un .1'T'a1'.

'*'*

*/

*'

o' fh'".t 'ra... d.,c1'ipta1' in RFA ./

.1''1''01''

'* Statu.
0'
Ca .... nd
/*

*'

Statu. ",o1"d
COlllmand word . /
O•••• o. fi".t co. . .nd block in elL

Co. . .nd

*'

*'

1* link flold *1

'* Para•• t.,.. *'

U_ShDT't p.T'il3J
u_shoT't ,aT'1I4,
u_sho,.t p.T'1I8,
u_sho1't p ......6'

st,.uct ",,_CB(

u_sho,.t stat,
u_ahoT't c.d,
u_oh01't link'

0' COII••nd
'* Status
Co.and ./
/*

*1

1* Link fleld *1 ,
u_shaT't ac_cnta I . NUllbeT' 0' Ie .ddT' ••••• • ,
ch.r .cJdd,.[ADDJ,EN*HULTl-l\DDR_CNTJ,
HC .ddre . . n •• *1

'*

),

1* Tnn . . U Buffe1' D"c1'lph1' TBD *1

.t1'uct TID

(

231421-18

1-24

intJ

AP-235

IPCD/USR/CHUCK/CSRC/DL.D. H

1* Nu_b.,. of bvte. hi buffer *1
1* of'set to next TBD
1* 10wel' 16 bits of buffer add1"ess *1
u_thort buff_hi
1* upp .... B bit. of bu'f.r addl'ess *1
.truet TB _bu" J t r '
1* not used b .. the 586: u •• d b\l the

u_shart act_cntJ
u_shart 1inkl

*'

u_short buff_II

.oft .... ". to savi .dd,.las translation
routine.
*1
1* Tl'ansmi t Bu,f.1's *1
.t'l"uct T8

<

Cho1lT data [TBUF _SIZEl;

),

1* F,..III DeSCTiptor FD *1
st1"uc:t

FD
u_sho,.t

.t.t,

*'

1* Status Word of FD *1
1* EL and S bit.

u_short al_s,
u_short linlll
u_shoT't 1'bd_o'f •• t,

1* link to next FD *1

1* Rlceivl buflfer descriptor offset *1

char d •• t_.ddrCADD_L.ENll/*Destination address *1
chaT' src_addrCADD_LEN]; 1* Source .dd1"ess *1
u_thort length,
1* Length field *1
),

.truet

RDD (

u_short
u_shol't
u_shol't
u_short
u shol't

1* Actual number of bUtes received *1
1* Of'.et to nell t RBD *1
1* Lower 16 bits of buffe" add,.ess *1
1* upper 8 bits of buffe" add,. ••• *1
1* SiZR of buffe ... *1
1* not used b~ the 586: used bU the

IiIct_cnti

I inlo
buff _I;

buff_hi
.izes
si',.uct RD *buff -Itr;

soft..,.re to save add,.es5 translation
routine.

*1

/* Receive Buffers *1

.t,.uct RD

ch.,. data[RBUF _SIZE];
),

struct

FRAI'IE_STRUCT
(

unsigned char
unsigned chaT'
unsigned chaT'

d •• pi
.sap;
cmdl

),

1* De.tination' Service Access Point *1
1* SOUT'c. SeT'V1Ce Access PDlnt *1
ISO Data Link Command *1

'*

1* L.6AP Addres. Tlilble *1
.true t LAT (

stat;

1* INUSE Dr FREE *1

231421-19

1-25

intJ

AP-235

IPCO/USR/CHUCK/CSRC/DLO. H

int

<.p_I.p_func) (),/* Point.,. to LSAP function, ••• oci.t.d
11111 th d •• p .dd,. ••• *1

_t'ruet "AT
cha,.
chI'''

•• '
'* "vltic
actual
1*

stat,

lNUSE

add,.tADDJ.ENl,

1*

Add,. ••• Tabl.

FREE *1
AIle add ...... *1

01"

*'

.},

.truet FLAilS {
.

unsigned dial_don.
unsilned st.t_on:

J

unstgned "' •••
unsigned ...... t..."end

1
1
1

t_....

unligned Ipbk_t •• t:
unsilned Ipbk_IIod.:
}

Ideflne
Ideflne
Idefine
Ideflne
Ideflne
Ideflne
Ideflne

,

ELBIT
EOFBIT
SBIT
IBIT
CBIT
BBIT
DKBIT

I
1

I
I
I
I
I

dlagno •• co_and cOlllpl.t.
'* n.twoT'k
diagnostic statistician/a"
t
t
*1

/*

/. don't ", ••• IIIhen this bit is ••
/* " ••• , IIhen this bit ts •• t *1
/. loopback , •• t flag . /
1* laopback lIod. an/of' *1

*1

*1

O,BDDD
O,BDDD
0,4000
0,2000

o,aooo
0,4000
0,2000

1* SCI p.tt .... n • • /
CX

o,aooo

FR

0,4000
0,2000
0,1000
0,0080
0,0100
0,0010
0,0040
0,0700
0,0070
0,0040

Ideflne
Ideflne
Ideflne
Ideflne
Ideflne
Ideflne
Ideflne
Ideflne
Ideflne
Ideflne
Idoflne

RESET
CU_START
RU_START
RU-",BORT
CUJlASK
RUJlASK
RUJlEAOV

Ideflne
Ideflne
Ideflno
Ideflne
Idoflno
Idoflne
Idoflno
Idoflne

NDP
IA
CDNFlllURE
MC_SETUP
TRANSI1IT
TDR
DUMP
DIAIINDSE

CNA
RNR

0,0000
0,0001
0.0002

0.0003
0,0004
0.0005
0,0006
0,0007

231421-20

1-26

inter

AP-235

IPCO/USR/CHUCK/CSAC/OLO. H

Idofino
Idofino
Idofino
Idofino
Idofino
IUfino
Idofino
Idofino
'dofino

CIIDJ1ASK
010007
NOERRBlT
012000
CDLLIIASK
OIOOOF
DEFERIIASK
010080
NDCRSIIASK
010400
UNDERRUNIIASII
010100
SGEIIASII
010040
IIAXCDLIIASK
010020
OUT_OF_RESOURCES 0,0200

Idofino
Idofino
Idoflno
Idofln.
Idofi no
Idofino
Idofino
Idofino
Idofino
Idofino
Idofino
Idofino
Idofino
IUfino
Idoflno
.de'tn.
Idofino
.dofino
.doflno
Idofino
Idoflno
'dofino
.doflno
'dofln.
.doflno
'dofino
Idoflno
Idoflno
Ido'ino

FIFO_LIII
BYTE_CNT
SRDY
SAV.JIF
ADDRJ.EN
ACJ.DC
PREAII_LEN
INT_LPBCK
EXTJ.PBCK
LIN"'pRIO
ACR
BOF JET
IFS
SLOT_TIllE
RETRY_NUll

010800
010008
010040
010080
0101000
010800
012000
014000
018000
010000
010000
010080

I.

OlbODO
oloaoo
OIFooo

, . IFS

PR"

0.0001
010002
010004

u.o FIFO 11 .. of B . ,

, . no p"io,.ttv

*'

ti ••
us.e *'
'*
.10t tl •• :51. i2 u•• ,
/ . r.tl'V nUllb.,. 1!t *'
9.6

*/

BCJ)JS
IlANCHESTER
TONOSRS
OloooB
NCRC_INS
010010
CRC_Ib
010020
IT_STUFF
010040
PAD
010080
CRSF
010000
CRS_SAC
010800
CDTF
010000
, . no collision d.tect 'Ut.,.
CDT_SAC
018000
IIINJRKJ.EN 010040
I . 64 b .. t ••• /
KINJ)ATAJ.EN IIINJRKJ.EN - IB
1* a.lu ••• Ethernet/IEEE 802.3
41,. •••• with 6 bVt •• of .dd,. •••

*,

*'
231421-21

....

1-27

intJ

AP-235

IPCO/USR/CHUCK/CSRC/DLD. C

1**•••••••••••••••••••••••••••••••••••••** ••** ••••••** ••••••••••**** •••••
*
*
82586 tMndleT'
..
*•••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••****••••**1
*
..

.define
Idefine
'define
Idefine

CB_CNT
FD_CNT
RBD_CNT
TBD_CNT

B
16

64
16

'*/. Nu_be,.
0'of availabl. Co....nd Blocks d•• c1'ipto".
NUllbe" of availabl. Receive
'* Nu_beT' of available Tran•• Buff.,. d•• c,,.iptors *'

Idefine INTERNAL.J.OOPB/ICK
'define EXTERNAL.J.OOPB/ICK
.define NO.J.OOPB/ICK

.do.lne TI~Rl_CTL
.define TUIER1_CNT
Idefine TI~2_CTL
Idefine TlI'IER2_CNT

1* I/O *1
Int
in..,'),

*1
availabl. Fr ••• D•• cT'ipto.,.. *1
Bu".",
it

Nu ....,.

/*

014000
018000
010000

OIFFSE
OIFFSB
0lFF66
OIFF60

*'
*'*'

'*

/ . input wO'l'd : in.(add1" ••• )
output IIDT'd: Dutw(addr •••• Value) *1

void

Dutil",

void

intt_intvC), /* initlaliz. the inter1"upt v.eta,. t.b1.
enable')'
enab1. 80186 int.,.,.upts
di •• ble').
, . di •• bl. 80186 inteor ... upts

void

void

*1

'*

*'

'* o.t• •paint.or
e, ..ent value *'
I. NULL

*1

1* tleCorD "tvpe" D' d.finitions *1

Ide.ine Cat.

out.CO.CB,O)

,- the cOlMland to i.su • • Channel Attention *1

'*

.de'lne ESI.J.OOPB/ICK out"tOICB.OI
put the ESI In Loopbuk *1
Idefine NO..ESI.J.OOPB/lCK· out.tOI,ca. BI
take the ESI out of Loopback *1

'*

*'

.de.tne EOJ_SOl30
outb COIEO, 0163)
1* End D' Jnt.l' ... upt
.deflne TI~1_EOIJlO1B6 out,.tOIFF22.01041 1* EOI for Tillor 1 on the lB6 *1
ad.'in. TJ"ER1~aJ_aol30 outbCOIEO,OI64) '-EOI 'Gor 186·s Tim .... l on the 13~ *1

231421-22

1-28

AP-235

IPCO/USR/CHUCIVCSRC/DLD. C

, ...........,.0..-..,
tnt Self_Telt'

u_Ihol"t temp'

alloc.tion . . . . . . . . . . . . . . . . ,

'*/. t ••po".1"\1

used fa,," diagnoltil::: pUl'pOI ••

.to...... • ,

Id."n. LPBKjRAI1E_SIZE
4
.her
Ipbk_'rell.tLPBKjRAIEJlIZEJ •
0."1 OxAA, aI'S, OIM),
*d.'ine whaami_io_add
O.OOFO
ch."
... hoamiCADDJ.ENl,

unligned long

u_,hort;:
u_short
unligned long
u_Iho1't
U_IhoT't

un' i lined 1Dnl

u_sho"t

'*,*

*'

<

*'

1/0 .ddT-." of HOlt Add,. ••• Prom
Ram aT"'.'" \alh.,.. hOlt .dd,. ••• is .ta,..d . /

DOod_l.it_cntl
unde"ru"_cnt,
no_e,.,_cnt •
. def.r_ent,
.,e_e,.. ... _ent'
•• ,_col_ent,
.... Cy_,,. ••• _cnt'
,. ••• t_entl

'*'* SVita
.. Configur.tion Point.,.: Rail Initialization
struet
lep •
010000, 0.0000, O.IFF6,
'* stl'uct
ilcp;
Intel' ••
SI,I.t .... Configu,..tion Paint.,. *'
.t,.uet sca sebJ
'* Swat .... Cant,.ol Block -,
st,.uet
'*
Blacll.
SCP

*1
010000),

buIV • 1.
pll'p-:>o' ••• 1 ; . Off •• tC •• cb),
pilcp->b ••• l • SEQMT « 4.
phep->b . . .2 • (SEllIn» 121 • OxOOOF ,

*'

'* '*

pNULL a BuildJ't,.(NULLII
" build. NULL paint.,. - 8086 tvp.: 32 bih "
BuildJU.C)J
inlt Receive Fr.,.. A" ••
Build_CbC)1
lnit Ca ••and Blacl!: lilt *1
ma_cb. clld - O.
/ . multic •• t addre ••••
inlt */

".pho".

leb .• tat • OJ

foT' ( i • O.

i

<-

OxFFOO,

i++)

231421-25

1-31

inter

AP-235

IPCD/USR/CHUCK/CBRC/DLD. C
if (Icb .• tat •• (ex I CNA)>>
br •• 1I1

If (I :>OIFFOOI
Fata1C It DLD: inlt - Dld not get an int:.,.,.upt •• ter Re.et/CA\n"),
1* Aell: the r ••• t Int.,. ... upt . ,
ocb.cmd - (CX I CNAII
CAl
Walt_Sc b () I
En.b 1o_586_Int () I

Icb. cbl_off •• t - Df, •• tC'cIt(01),
Icb.

,.'8_0"5.' - Off •• tC"dCOl),

,*

link ICIt to eb and ,d lilt. *1

1* move the ~T'O. bVt •• into ... hoa ... ! aT'''.''

f.,.

*'

01 I (ADDJ.ENI 1++1
.. h .... 1[ (ADD_LEN - 1 I - Il - Inb ".h •• ml_I._add + 1*211
(I •

'*

Inltiallzati.n tho Multica.t Add,.. . . T.bl.

foT' (pmat . . . .8tCO]1

pmet

<-

IcmetCt1ULTJ-"DDR_CNT -

*'
III p•• t++)

pmat->.tat - FREE.
C.nflgu,..( INTERNALJ.DDPBACKII

1* Put 586 in int.,.nel loopback *1

S.tAdd,. ••• C),

'*

run diagnostics *1

If (Solf_T•• t

!- PABBEDI

".turneS.I._Te,t).
C.nfigu,..(NO_LDDPBACKII

'*

C.n.igu,.. the 82586

*,

Bui Id..Rf.( I

<

.truet
struet
struet

FD
RBD
RB

unsigned long

f.,. (pfd

*pfdl
.prltd.

.,bu',
baddJ

= &fdlOll ,p.d

(~

&fdIFD_CNT -

III pfd++1

pfd->stat = pfd->el_5 • Oi
pfd-:>Unk - Df'ut(pfd+lll
pfd->1"bd_o .. , •• t • NULL,

231421-26

1-32

AP-235

IPCD/USR/CHUCK/CSRC/DLD. C

*'

1* point to &'dCFD_CNT - 1] *1
1* last I'd link is NULL
1* l •• t fd h •• EL bit •• t *1
1* point to first 'd
pfd->rbd_of, •• t - O" •• tC&rbdCO])s
1* link fir.t fd to first Tbd

end_I'd Ii:I --pfds
pfd->11nk • NULL,
pfd-:>el_s • ELBJTs
b.gin_fd =- pld • II:fd[Oll

= a.:,.bd[O],

for (pI"bd
bad d

SEQ"T

IS

«

*'

pbu". &!,.bu'[Ol,

prbd

buff _1 • b.dd,

pT'bd->bu" _h • badd »
prbd->bu" ,...pt,. - pbufl

prbd->act_cnt..

16,

OJ

prbd->linll .. Of, •• tCprbd + 1)1

prbd->.il . . . RBUF_SIZEJ
.nd_1'bd III: --pTbd.
p,.bd->l inll .. NULLJ
p1'bd-)sil' J. ELBITJ

1* la.t rbd paint. to NUL.L
1* la.t rbd hal .1 bit •• t

*'*'

b.gin_rbd = lt1'bd[Ols

Build_Cbe)
{

.truct
.truct
struct

'*

Build • • tacle of

'r"

callm.nd blacks *1

CD .pcbJ
TBD *ptbdJ
TD
*pbu'J

unsigned

long

b.ddJ

for (pcb - Ircb[OJ; pcb <- 'cb[CB_CNT pcb->st.t - 0;
pcb->cllld • ELBIT;
pcb->l ink • Off •• t(pcb + 1).

1l;

pcb++) (

--pcb,
begin_cbl ... end_cbl - pNULLJ
pcb->link - NUL.L.
cb_tos • &cbtOl,

1* Build a stack of transmit buffer descriptors *1
'or (ptbd

a

IItbd[OJ,

pb,...

IS

Cctbu'[Ol;

ptbd

<=-

Cctbd[TBD_CNT - ll;
ptbd++,

pbu'++) -(

ptbd->ut_cnt • TBUF _SIZE,
ptbd->link - Dfh.tlptbd + II,
badd

a

SEIII1T

«

4,

231421-27

1-33

inter

AP-235

IPCD/UBR/CHUCII/CBRC/DLD. C

badd +- Off •• t(pbufJ,
ptbd->bu" _1 - badd.
ptbd->buff _h - b.dd
ptbd->bu" .,JItr • pbu',

»

--ptbd.
ptbd->link •

NULL.

tbd_tol • • tbd[OlJ

stl'uct

CB

16.

'*

1* l . . t tbd link is NULL *1
Set the Top 0' the Stack *1

.get_CbC) 1* ,..tul'n • painte,.. to • fre. command block *1

(

.t1"uct

CB .pcb,

if' (OffsetCpcb • cit tal) - . NULL)
,...tu1'nCpNULLJ,
cb_tos III Cst,.uct CB .> Build_Pt,.C.pcb->link)i
pcb->1 ink -= NULL,

return(pcb),
1* Put. Command Block beck onto the fre. lilt

*'

Put_CbCpcb)

.tT'uct

CB .pcb,

(

pcb-:>st.t .. 0,
pcb->1 ink • Offset (cb_tol) J

cb_tol - pcb,

stl'lJct TBD

*g.t_TbdC)

(

,tT"uct

TID

'* ,..tU1'n
• pOinte"
d."1'ipto1' *'

to • fre. t,.ansmit bu"e,.

*ptbd.

flags. r ••• t_s.m• • tJ
Di.abl._5B6_IntC ),

if (Cptbd • tbd_tosJ !- pNULL) <
tbd_tas. Cstl"uct TBD . , Bu:lld_Pt1'(ptbd->link),
ptbd->link z NULL.

Enab le_SSiI_lnt (),
flags. ", ••• t_s.m• • OJ
if, (fl.g •. ", ••• tJend

1)

Reset_586C ) J
",etu",nCptbdJJ
)

231421-28

1-34

inter

AP-235

IPCD/U5R/CHUCK/CSRC/DLD, C

.truct

THll

<

stT"UC

t

*ptbd.
*p ,

THO

, . find the end of the tbd li.t retUl'nltd.

=

for (p

ptbd;

p->11nk

!- NULL.,

P->Act_cnt • TBUF_SIZE,
p->11nk • O'f •• tCtbd_tal)'
tbd_tos

=

stTuct

CB

P

:III

ptbd is the beginning */

CstT'uct TBD .) Butld_PtT'Cp->l:lnk»

, . c1 ..... EOFBIT and update

.i,.

J

on l •• t tbd *1

ptbd,

.pcb;

Mifdef DEBUO
;f «pcb. Oet_CbC»
•• pNULL)
Fatal("dld. C - SetAdd" ••• - couldn't get .. C8\""),

•• 1 ••
pcb

Iond i f

III

Get_Cb();

1* DEBUO *1

bCDP,,« (cher .)ltpcb->p."ml • •whoemiI:Ol, ADD_L.EN),

pcb->cmd

:II

1* move the P1'OIl

addre •• to IA cmd

IA I EL.BtTi

*'

I.lue_CU_'md Cpc"),

faT' Cstat

:=II

FAL.SE,

.t.t •• FALSE, ) (

fo1' (i=O; i<=OxFFOO. 1++)
if Cscb.clld
0)

break,
i f <1 > OxFFOO) <
Buge"DL.D: 9cb commend nat c1 •• r\""),
CA;

else

stat = TRUE;
23142,1-29

1-35

inter

Ap·235

IPCO/USR/CHUCK/CSRC/DLD.C
)

Issue_CU_CmdCpcbl 1* Gueue up a com.and and i.sue a
other co...nds a~e queued *1
.t~uct
CD *pcb;

.ta~t

CU co. .and if no

(

Dhable_5B6_IntC II'
if Cbegin_cbl aa pNULLI (
1* if the list is inactive sta~t CU *1
begin_cbl = end_cbl a pcb,
scb.cbl_off.et a Off.etCpcbl,
Wait_Scb(J,
scb. c.d - CU_START'
Set_Ti.eoutCI,
1* .et deadman time~ fo~ CU *1
CAl
)

el.e (
end_cbl->link a Off.etCpcbl,
.nd_cbl - pcb,
)

Enable_i586_lntC I,
)

In7C I
(

outbCOIEO. 01671;

1* EOI 80130 *1

)

Isr6C '(
W~it.C·\nlnte~ru-pt

outbCOIEO. 01661,

6\n"I,
1* EOI 80130 *1

)

Isr5C I
(
W~iteC"\nlnt.~rupt

outbCO.EO. 016511

5\n"l;
1* EOI 80130 *1

)

1* Deadman
ls~
(

Ti.e~

_Tim.outC I

1*

lnte~~upt S.~vice

Int.~~upt

-Routine *1

4 *1

R.s.t_TimeoutCI,
i. Cflags.~eset_sema _. 11
flag •. ~ ••• t-p.nd • 1,
.1.e
R•• et_586C II
TIMERljEOJ_801S61
TIMER1_EOI_801301
)

1*
1*

Int.r~upt
Inte~~upt

0 i. Ua~t in UAP Module *1
2 i. Ti.er in UAP Module *1
231421-3Q

1-36

intJ

Ap·235

IPCO/USR/CHUCK/CSRC/DLD. C

ioriO
(

W"itIC"\nlntll""upt l\n""
autb (OlEO. 016111

I. EOI 80130 . ,

'* 586 Int.rrupt ••rvici rautine:
U_Iho,.t
• ,,.uti;

Intl1"1'upt 3 . ,

Itat_Icb •
CB

.pcb.

Watt_ScbC).

leb. cmd -

Clt.t_lcb • leb.ltat) II (eX I CNA I FR : RNRh

CAl
If (stat_scb •

(FR I RNRII

Rlcv_Int_P"ac ••• tng C) I
if Cltat_lcb .. CNA) (

1* Ind of cb p"ac ••• ing *1

RII.t_Tilllout().
1* cl •• l" d •• dman ti.I"
pcb. BuildJt,.Clcb. cbl_o-p ••• t)1

*1

_lfdof DEBUQ
if (billin_cbl •• pNULL)(
BUll C"DLD: bl.in_cbl •• NULL in int'''l''upt TDutinl\n lll

) •

.,..tu1'n.
if «pcb-:>.t.t .. OICOOO) !- 018000)

Fatal ("DLD: C bit not •• t a,. B bit •• t in intll""upt 'routine\n").
_ond If I . DEBUQ . ,
..... ttch (pcb->cmd .. CMD_"ASK) (

c ••• TRANSMIT:

'* thilIqlcondition
b i t . 0 and th.,., ....... no
111111 occu" an the fi"st

if
callisianl -> Iq. IrY"o"
t"ans"is.ian if
th." .....". no colli.ions, a,. if the p".vious t"an •• it
command ".ach.d the rna. colli.ion count, and th. cU'r".nt
transmi •• ion had no colli.ion.

*'

if «pcb->stat •

(SOEMASK : MAXCOLMASK I COLLI1ASKII == 01

++5,._."" _tnt;
if (pcb->stat • DEFERI1ASKI

++d.'." _cntl

231421-31

1·37

inter

AP-235

IPCO/USR/CHUCK/CSRC/DLD. C

i f (pob-:>.tat • NOERRBIT)

++good_Imtt_cntl
.1 •• "
I ' (pob-:>.tat •

NDCRSI'IASK)

++no_c,.,_cn"a
i f (pob-:>.t.t • UNDERRU_SK)

++und.,.,.u"_cnt,
I f (pob-:>.tat • I1AXCOLI1ASK)

++•• x_col_cnt.

>

if (pcll-:>p.'I"lIl f. NULL)
Put_Tbd (Bui ld-"t~ (pob-:>puftll)).
b ..... lu

on. DIAQNOSE:
flilill. dial_dane· 1,
If «pob-:>.tat • NOERRBITl •• 0)
S.1f _T . . t • FAILEDJ)JAONOSE.
b,. •• 11I

d.fault:

if (pcb-:>linll •• NULL)

begin_cbl • pNULL,

begin_obi •

Build-"t~(pob->l1n~).

seb. cbl_of, •• t • pcb->linlu
Welt_SebC),
leb. elld - CU_START'

>

CA.
Walt_Sob (II
Set_Ti .. eoute).

,*

START d •• dman timer

*'

i f « pob-:>olOd • CI'IDJ1ASK) •• I'IC_SETUP)
pcb->cmd • OJ 1* cl •• .,. Me_SETUP elftd WO'l"',

tltis will implement.
lock •••• phD,.. 10 that it .. an't be reus.d until
i t is completed

el,.
Put_CbCpcb),
di •• bleO,
EOJ_80130.

'* Don't
".tU1'"
• ene".1 pu,"po ••

*'

It'. not' •
black 'rom, ,,. •• CD list *1

tIC_SETUP Cllld bloc-II.
comm.~d

/ . di •• ble cpu tnt 10 that the '86

i.,.

will not n •• t ttl

231421-32

1-38

intJ

AP-235

IPCD/USR/CHUCK/CBRC/DLD. C

Recv_lntJT"Dc ••• tnll« )
(

Itruet
.truet

.q,.

FD
RBD

.,fdl

'* point.
to
point. to

'*
/*

*prbd;

the Frame D"cl"iptD1'" *1
thl 1 •• t .... bd for thl ''' •• 1
pointa to the fi,.,t rbd 'or thl ,,. •••

*'*'

'01' Cpfd .. blgift_.dl p.d !- pNULLJ p.d • blgin_fd)
If Cp'd->.tat • CBIT! (
blgin_'d. C.truct FD *J Bu:lld-Pt'l"Cpfd->l:LnIlJ,
p,.bd • "t"uet RID .) Bu:lldJ't,.Cpfd->,.bd_of ••• tJJ
if Cprbd !- pNULL) (
chick to ••• i • • buff • .,. is attached

'*

*'

.Ifdof DEBUg
if Cpl"bd ,- '111"_1'bd)
Fatal ("DLD: prbd !- '1IIln_1"bd in Rlcv_lntJ,.oc ••• ing\n")1

. . ndif 1* DEBUg *1

'a,. (Il • p,.bdl (q,-).ct_,nt &.: EOFBIT) !- EDFBITI
II -

Cstruct RBD *1 BulldJ'trCII->linkll.

blll"_1"bd - C,truet RID .) Bu:lld-Pt1"CIl-:>link)1
11,-:>1 inll • NULLJ

>

I' Cpfd->stat • DUT_DFJlESDURCEBI

Put_F..... _RFA Cp fd ) I
,I •• -(
if thl DL.D il in a loopbaclr te.t,

'* (.la••. lpblr-JRade ••
i'

checlr the .,. ...e ,.ecv *1

1)

L.aopb.clr_Chec Ir (pfd) I
.1 ••
1* if it' • • flultic •• t .dd,. ••• check to ••• if it'.

in the lDultic •• t .dd,..,. t.ble, i. not di.c.,.d the ,,. .... e *1

If C IIpfd->dost_addr[Ol .011 PutJnoJlFACpfd I.
el.e
(
Recvj,. ... eCp.d)1
++,.ecv_'l"' ••• _cntl

011 •• C!ChockJlultlc ... tCpfdlll

>

.15.

0(

Ru_St.,.tC), 1* If RU h•• lone into no ,. •• ou,.ce., ..... t."t· it *1
b" •• lu

L.oopbac Ir_Chee II (pfd)

1* Called b\l Recv_lntJl... oce •• lngJ checlr • • dd,. •••

.nd d.ta 0' potential loapbaclr 'T' ••• *1
.tT'uct

FD

st1"uct RHD
.t"uct RB

*p.dJ
*prbdl
*pbu"

231421-33

1-39

inter

AP-235

IPCO/USR/CHUCK/CBRC/DLD. C
if ( b,.p«ch.", .) .pfd-),,,,cJlddrCOl • •who.mitO). ADDJ.EN) !- 0 ) (
PutjreoJlFAC p.d I.

>

r.turn,

,T'bd • Cst,.uct RID .) BUild1tT'Cpfd->l'bd_oP, •• t),

'*

point to .... ceive
bU".1" d.,c1'ipto1' *1 '
pbu' • (st'l'uet RS .) pT'bd->bu"Jtr, 1* point to ..... c.iv. bu".",
If C bCIRpCCch.,. *1 pbu', "lpbk_....... tOl.

*'

L.PBKjRAIIE_BtzEI !- 01 (

Putj"'.JlFACpfd I •

.,.etv.,.",

'lagl. Ipblc_t •• t -

I, ..

Putj"'.JlFACp.dl.

'*

p •••• d laopback t •• t

'* ,..tu,.nl t'l'ue

CheckJ1ultic •• tCp'd)
,t"uet
FD .p'd,
,true",

'0,.

*'

i . . .ultic.,' add".,1 tl in MT

*'

HAT .p ..at,

Cp ... t ...... ttOl. p•• t <. " ... ttMUL.TI..,ADDR_CNT - 11, pmat++1
i' C p ... t->st.t •• lNUBE ....
(bcmp«cha1' .) .p.d-)d •• t_addTCOl, .pmat->.dd'l'tOl. ADDJ-EN) ··0»
b'l" •• k,

i' Cpmat > ..... ttMULTI_ADDR_CNT - I])
,..tu,.n CFAL.SE I.
,,*tu,.nCTRUE),

T. . t.J-ink ()
(

Self_T •• t - PASSED,

Diagnos.e ),
i' CB.I. _Tnt •• FAILED,..DIADNOBEI
,..turn,
Ru_St.,.te),
, . sta ... t up the RU foT' loapbacll t •• ta
'I."s. Ipbll_ItDd • • 11 /* "D into loopb8cll Itod. */

'*'* ••

*'

*' *'

'Iags. Ipbk_t •• t • 01
t loob.ck t •• t to 'al ••
S.nd.-Lpbk_Fl"8111.C)1
int."'n81 loopb8Ck t •• t
i ' (.Iag •. Ipbk_t •• t •• 0) (
B.lf _Tnt· FAlLED.J-PBK_INTERNAL.
flag •. IpbkJlod • • 01
",.tUf'n'

'18.S. Ipbk_t •• t • O.
/* •• t .... nal loopback t.st
Configu",.CEXTERNAL.-LDOPBACK).
S.nd-.L,pbll_F,.8111.C ),
i. cn.g •. Ipbk_hst - 0) (
B.I._T.st • FAILED.J-PBKjEXTERNAL.

w'

ESI in Ipbk

*'
231421-34

1-40

inter

AP-235

IPCO/USR/CHUCK/CSRC/DLD. C
flilg •. Ipbll_rIIode .. 0;

return,
'lags. Ipbk_t ... t .. 0;
1* •• ternal loopbilck test through transceiver *1
NO_ESI_LODPBACKI
SendJ.p b "_Fr.... ( ) J
if (flags. Ipbk_t •• t _. 0)
So If _To.t = FAlLED_LPBK_TRANSCElYER.

Send_Lpbkjr ••• C)
{

struct

*ptbdJ

TBD

II

Int
flor (1 • OJ

i

<

BJ

i++)

<

*'

1* .end Ipbk fr .... S tim •••
b •• t .,fort del iv.,."

lince it's

_Udof DEBUg
if ((ptbd ~ got_Tbd 0) == pNULLl
FatalC"dld - SendJ.pblc_F".lIe - couldn't get. TBD\"");
ptbd .. get_Tbd(),

_end!' 1* DEBUg *1
ptbd->act- ptbd->buff,-Pt,., Iclpbk_',..ameI:Ol, LPBKjRAME_SIZE);

Diagnose( )
{

.truct

CB

.pcb;

_I,dof DEBUg
if «pcb - got_CbO)
pNULLl
Fatal("dld - Diagnol. - couldn't get III CB'n");

".lse
.end:i f

pcb

= Oet_CbOI

1* DEBUQ *1
flags. diag_dane - OJ
S.lf _Test .. FALSE,
pcb->cmd = DIAGNOSE

ELBITJ

Issue_CU_Cmd (pcb),

"'hile (flags. diag_dane a·O)

231421-35

1-41

inter

AP-235

IPCD/USR/CHUCK/CSRC/DLD. C

Can.tIU""« laop.l •• )

u_.ho"t 100p.lell'

,'-rue'

CB

.pclt,

.ifd.' DEBUg
if Ilpcb • got_Cbll) •• pNULL)
FatalC"dld - Con.ilu"" - cQuldn't I.t • CI\n"),
•• 1••

pcb. g.t_Clte),

•• nd if

1* DEBUg *1

pl:b-),.".1 • O.08OC.
pcb-)par-=Z: • 0.2600 I 100p'18.,

pcb-),.",.3 • 016000.
pcb-)parm4 • O.F200,

pcb-),.1'".' • 0.0000,
if 1I •• pU_, •• NDJ.DDPIACK)
pcb-)p.,..• • 0.0040,

.1 ••
pc 11'-),.",.6 • 0.0006,

pcb-)clld

• CONFICIURE

*'

1* loopbaclt ' .... m. i l l ••• but •• than
the lIintMuli ,,. ••• l.ngth

ELI IT •

)

1* S.nd a

''''.111.

*'

to thl cab1" p•••• ,oint.,. to the d•• tination .dd ......
and a ,oint.r to the ,i,..,t ,,..n •• U. buf"'" d'lc1'I,tol'.

Slndjr ••• e,tbd, p.dd) /. ,..tU,.nl '.1 •• if it tan't I.t • CO.llland black . /
.truct
. TID
*ptbd.
chat'
.p.dd,
(

.truet

CI

.pcb.
l.n,th.

if ((pcb. g.t_Cbll) •• pNULL)
'1 •••. ,.. ••• t_. . . . - 0,
if ( '1 •••. " ••• tJ.nd •• 1»
R••• t_~()J
, 1'.tu1'nCFALSEh
pcb->par .. l • D. . . . tlptbdl.

231421-36

1-42

inter

Ap·235

IPCO/USR/CHUCK/CSRC/Dl.D. C

'*

*'

mav. d •• tination .dd,. ••• to cD",•• nd block
bcaplJ«cha,. .).p,b->p.,.1II2. (char .)p.dd, ADDJ.EN),

'* calculate

the l.ngth ".1d IIv.au_ing up all the

fo1' Clongth - O. ptbd->Unk !- NULL.

bu".",

*'

ptbd - DulldJ't1'Cptbd->Unkll

l.ngth +- ptbd->.ct_cntl

l.ngth +- cptbd->act_cnt Ie OI3FFF)J

i.

/* check to •••

'* .dd

,._,u1,..d.

p.dding 1,

the l •• t bu'f.,.

*'

do not do p.dding an loopback *1

1* thia .. 111 nat wa1'k I f "INJlATA.J.EN > TDUF_SIZE *1
If CCl.ngth < "INJlATA.J.ENI.. 1* . . . u •• ' • 4 b~t. CRC *1
CbctlpClcwha.m:HO:J, (,h.,. .)p.dd. ADD.-LEN) !- 0»

J 'lu._CU_Cmd (pcb),

'la.l. ,. ••• t_••••• 0,
If Cfl.g •. ,.. . . t..JI.nd
R••• t_586C

11

)J

,..tu1'nCTRUE),
)

AddJlultlc •• t_Add,. ••• CplNl)
ch.,.
.p •• '

pm. - point.,. to multic.lt .dd" ••• *'
'*/. ,..tu'I'n:l."1
.a1 •• ,. •• n. the Multic •• .dd ......
*1
t:

tablo ia full

(

'* thenthe".turn
multica.t .dd,. •••
i,

i, •

duplicate of ane .11· •• dU in the ftAT,

*1

for (pm.t • m.t, pmat <- ... tU'ULTI~DR_CNT - 111 pmat++)
if ( p •• t->.t.t -- INUBE ••
(bemp( .p •• t->.dd,.[Ol, (char .) p.a, ADD..LEN) -.0»

r.tu'rnCTRUE)1

<

'01" (pmat - .... t, p.At c- . . . ttt1ULTJ,J\DDR_CNT - 111 p... t++)
i 9 (pmet->stet .- FREE) (

plII.t->stat - INUSEI

bcap~C

.p •• t->add1'[OJ.

Cch.,. *1 p••• ADD.J.ENI.

b,. •• k,

231421-37

1-43

intJ

AP-235

IPCO/USR ICHUCK/CBRC/DLD. C

If

(pm.' :> ..... ttI1ULTIJlDDR_CNT - III (
fl1ag •. r.s.t_..... = O.
if ('lags ....... t..JI.nd -- 1)

Reset_'S6() J
returnCFALSEJ,

SetJ1ultic •• tjlddr ••• C),
'lags. r ••• t_•••• - OJ
if ('1 •••. ,. ••• tJend •• 1)
R••• t_5B6( ),

retu1"nCTRUEJ,

Deletlt_"ultic •• t_Add'l" ••• Cp •• '
cha'"
(

1* returning ,.1 . . . . . . na the lIultica.t: .-dd,. •• s

*,..,

... a nat found

*'

<- ... tntULTI_ADDR_CNT - 111 p . .t++)
pm.'-:>s'.' - INUSE ••
(bell, ( .pfNt->add,,[O], (char.) pilla, ADD.-LEN) . - 0»
p •• t->.tet • FREE,

'01' (p ...at - .at' , •• t
if (

bre.k.
if (p ... ' :> .... ttI1ULTIJlDDR_CNT - III (

.1ag •. r ••• t_. . . . . 0,
if ('lag8. 'I" • • • t...,P.nd .- 1)
Re.e'_5B6( I,
return CFALSE) J

S.tJ'lultica.t-.Add,. ••• C),
'1 ..... ,. ••• t'_••••• OJ
if ('lags. ,. ••• tJ.nd •• 1)
R••• t_586( ),

retu1"nCTRUEJ,

SetJ1ulticast_Addr ••• ( )
(

.t,.uct
.truet

"AT
"A_CB

*p.atJ
*p.a_cbJ

i • 0;
pma_cb • 8cma_cbf
whil. (pma_cb->cmd !- 0)
p ..a_cb-:>llnk • NULL.

J

1* if the f1A_Ca i. inus., .... it until i t ' . f" ••

*,
231421-38

1-44

AP-235

IPCD/USR/CHUCK/~SRC/DLD.

C

'01' «pmat • met' pilat <- Icmat[t1ULTI.-ADDR_CNT - 11, p... t++)
if C pmat-).t.t •• INUSE) (
bCDPU C 'p ... _cb-:> .. c __ ddr[ iJ. 'p ... '-:>.ddr[Ol. ADD_LEN).

i +- ADD..J-EN.

pm._cb->ltc_cnt - il
p ..._cb-:>clOd - "C_SETUP I ELBIT.

'* R.turn
Fra .. e D•• cl'iptor and Receive Buf'."
D•• c1'ipto",. to the Fr •• Receive Fr ••• A,. • • • /

PutJr •• ..RFACpfd)

FD
RDD

It1'UCt

.prbd.

,..tu1'ned
'*'* points
to
of
*' *'
/. indicat •• ..,hethe,. to r •• t.,.t RU *'
points to beg inning of

ell.l
ru_'t.'I"t_'Pl.I_fd,

end

RBD 1 tst

,..tu1'ned RBD lilt

ru_,t.rt_'l·lI_rbd,
'18gl. r ••• t_...... 1,

ru_start_'lal_'d • ru_st.,.t_'l.l_rbd • FALSE,
pfd-).l_s ... ELBIT,
pfd->st.t =- 0;
p,.bd • (struct RDD .) Build-pt,.Cp'd->rbd_o'f •• t), /. pick up the link to the rbd
pfd-)Unll • p'd-)rbd_of, •• t - NULL,

*'

'*p,.og,.am.

Di •• bl._586_IntCh this command is onl\l n.c.I •• ,." in a multitasking
Ho .... v.,. in thil lingl. t.sk envi,.an •• nt thil "autin. il a,.ig1nal1\1
called f,.om ilr _586 ( ). therefa". int.,.,.upts are al"e.dv disabl.d *1

i f Cbogin_.d -- pNULL'
begin_.d • end_fd .. p'd.
else (
end_.d->linll .Df's.t(pfdh
end_.d->.l_• • OJ
end_'d • ptldJ
rU_lt.,.t_'lag_fd • TRUEJ

if Cprbd !- pNULL)
'Dr Cq

m

1* if there il a rbd .ttached to the fd then
find the beginning and .nd of the rbd lilt *1

prbd. q-:>Unk !- NULL. q . Bu!ldJ"rCq-:>Unk))

q,->act_cnt • OJ
1* no .. pt"bd points to the beginning of the rbd Ust and
II. paint' to the end of the l'st *1
q-:>Iizo • RBUF JlIZE I ELBIT.
q,->act_cnt • OJ

231421-39

1-45

AP-235

IPCO/USR/CHIICK/CSRC/DLD. C

'*c"•• t •"".r.
• n...

i l nothinl on the lilt
I i i ' */

if

~

'egin_"bd - p"b ••
end_I'lId - "
if Cprbd !- q)

,.u_I,."'_.I •• _,,bd • TRUE,

'*

if

,t. ..... il 110". than an. ,.bd

.... tu,.n.d

.t.,.,

'*

the RU . /

*'

if the ".bd Iii' al1· •• d" •• ,.ts add on
tb. n .... .,..tu"n ..... bd.
.nd_'I"bd->link • D" •• tC,,.II&I);

.nd_"bd-:>.I •• - R8UF _SIZE,
.nd_1". . . .

ctl

1"U_It.,.t_'l •• _"bd • TRUE,
}

If

'*

C~u_ota~t_flag_fd

....

~u_ota~t_flag_~bd)

Ru_8t.,.t ( ).
Enable_:I86_lntC h

t.

Dl •• bl*_586_lnt() t. u •• d above . ,

fla,l. r ••• t_...... O.
if (fl •••. ,. ••• 'J.nd •• 1»
R••• t_586C ),

RuJltutc)

<

if «Icb. stat. RU-"ASK) . - RUJ'EADY)

If CCbe.ln_fd-)otat • CIIT) -

,...tu,.n •

'*then return

if the RU i . al,. •• d" '" •• dV'
*/

CIIT>

.... in_'d-:>"bd_o., •• t - Dff •• tCb •• :l.n_"bdh /* link the ".ginning of the I'bd
Uot to the Unt fd *1
Icb. ,,'a_of, •• t • O" •• tCb.gin_.d)J
w..it_Scb( ),
.cb. cfltd • RU_START,
CAl

Sa.t ..a",eJte •• t ()

<

scb. cllld • RESET,
CAl

Wdt_ScbClI
J •• U.Jt ••• t_CMd.( )

<

WaitJlcbC )1
acb. ctld • CU_START'
CAl

231421-40

1·46

AP-235

IPCO/UBR/CHUCK/CSRC/DLD. C

out .. ( OxFF'E, 0)

J

Dut .. ITlIlER1_CNT. 01,
'Qutw(OxFF5E. OICOO.),
whil. «in ... (OJlFF~) • 0.00:20) -

0)

*'

1* if PIa. Cnt bit il •• t before eNA
:h •• t, 596 emd de.dlocked

if C(Ieb .• tat Ie CNA) . - eNA)
b,. •• lu

if

(Ieb . • t.t

• eNA !- eNA)

Fat:alC"DLD: 1 •• ue.ft ••• t_Clldl - Co ..Mnd d •• dlocll dU1'ing "'It.ltt procedure\""),

R.I.t_Ti •• out C) I
leb. emd - CNlu
CA,

'*

Acll"o,lI1.d.1I CNA inter1"upt

*'

Wait_Scbl I,

1*

e •• cute

• 1' • • • t, Configul"l, S.tAdd"' •••• and rlC_S.tup.
R.e.iv. Unit And the COII•• nd Unit *1

th.n r •• te,,'I: the

Ro . . t_'SIoII
(

MT
i,

++,. ••• 'I:_C"'I:;
Di.abl._SB6_lntC ),
ESJ_LOOPBACK,

Soft".-r.,jt ••• t () J

fo1' C :f. • OJ i <- OIFFOO, i++)
if DIFFOOI

'*

Fatale "DLD: inl'1: - Did not I.t an int,,,,",upt . f t .... Soft ...". R•• ltt'n"),
Aell the 1' • • • t

Jnt.1'1'upt _,

Wait_ScbO,
Icb. cmd • (eX t CNA),

CA,
WaitJlcbC I,

IUdo. DEBUg
if ( b •• in_cbl •• pNULL)
F.t.l("DLD: b •• tn_cbl • NULL tn R.let_5B6 H
londi f

),

I. DEBUg . ,

231421-41

1-47

Ap·235

IPCO/USR/CHUCK/CSRC/DLD. C

1* Canflgun t h 586 *1

*' t.,..,

1* Eth.,.net default ,.,. •••

del.ul t pa ......

lt.,.,

Conftllu'r,1 il not n.c •••• ,." IIIh.n ulin.

,..,_cb. link - NULL,

,.,.,.1 •

"'I_cb.
OxOBOC,
1'.,_cb. p.,..2 • 012.00,
"1'_CIt. parm3 • 016000.
"I'_CIt. p.,.114 • OxF200,

,.I,_cb. p.,. ..5 •
, ".,_clt. p.,....
".,_clt. cmd

0.0000,

010040.

• CONFIOURE , ELIJTJ

leb. cb1_off •• t • O, ••• 1;("'.,_cb. Itat),

J •• UIJf ••• t_CMdIC h
1* Set the Individual Add,. •••

*'

bcopU«ch.,. .) Ie,..,_cb. p.,.1ft1, &lIIh'01 .. 1[01, ADD-.L,EN), 1* lIIove thl

'''011

add,..sl to IA cmd

*'

1"UI_R.•• et_CfldIC ),

'* ,.,load
i

the multic'lt .dd,. •••••

- ".,-",a_clt. st.t •

,. •• .JII._clt. 1 ink •
'a~

*'

o.

N~LI

Cp..at ...... teOl'

p ..at

<- ..... tCI'lULTI_IIODR_CNT

if ( pmat->Itat •• INUSE ) (
badd~[Ol.

IIODJ.EN),

r".JII"_clt. mc_tnt • I,
,. •• .In._cb. c.d • I'1CJlETUP I ELBJTJ

Icb. cb l_olPleto: • Off •• to:(Ic,. •• .JI._cb. stat),
Issu._Reset_elld.( )J
1* R•• t:.,.t the ColIftftI.nd Unit and the Receiv. Unit

*' "

flag •. 1" ••• t_. . . . . O.
flag •. ,.e.etJend • O.

ND..ESI.J-OOPBIICK,
R.cv_lntJ»1"Dc.ssing ( »J

Icb. cbl_o'fI.et • begin_cbl'
Walt_B

•• 1 • • • 2.
nll\lt •••
IIIhtl. (nll,., •• -- . . . . 1++ -

••:2++),

.... tu1'nC.--.l - *--12),

231421-43

1-49

AP-235

IPCD/USR/CHUCK/CSRC/LLC. C

*******·.*****·············***···**····**··**.****.*****••*•••••••,.

**1 ....***** ••

IEEE e02.2 Logical Link Cont1'ol Lave..
(Station Component)

..

..

**•••**************.***.*.*.*.**************••• *.***** *.**** ••*****.**********1
.include "dld. h"
•• t .... "

ch.,.

.pNULL,

.xt.,..n

struet

ext.,.n

chaT'

TID ..o.t:_TltdC),
*8uildJt"()J

" •• donl" cha,.
xid_f .... m.tXIDJ.,ENQTHl. -C O. O. XID. O.Bl. Ox01. 0),
1* DSAP, SSAP, KID. xid cl ••• 1 ,. •• pon •• *1

.t,.uct LAT lattDSAP _CNTl,
Init..Llc()
{

.t1'uct

LAT

fOT (plat. 1e1attOl, plat

<-

8clattDSAP_CNT -

ll,

plat++'

plat->.tat • FREE,
,..turn( Init_586(»'
1* Function fa,. .dding .. ne ... DSAP *1

AddJ) •• p.-Addr.I.(d •• p, ,func)

int dsap,

(*pfunc)

'*

DBAP .Ult be divisible b .. :Z*.CB-N), IIIh.,..
2**N • DSAP _CNT. Ci .•. N LSBs must b. 01The function ..,ill ,..tuT'n FALSE if do •• not
m•• t the .bov. "eq,uiT'enl.nt.~ aT' the lo •• p
Add" ••• T.ble i . full, at' the add "e •• h ••
• l"e.d .. been us.d. NULL DSAP add",e •• i.
'I"e •• "v.d '01" the St.tion Companent *1

()I

{

.t"uct

LAT

if (Cd •• p « CS-DSAP_SHIFT) .. OxOOFF) ! - 0 II d •• p -- 0)
,..tu1'n (FALSE),

1* Check 'OT" duplic.te d •• ps. *1
if ( (plat - .. lateds .. p » DBAP_SHIFTl)->stat
P lat->stat • INUSE,
plat->p_s.p_'unc • pfunc;
1'.tu1'n (TRUE),

-= FREE)

{

.Ise
retuT'nCFALSE);

1* Function faT' deleting DBAP • • ,
neleteJ) •• p..AddT' ••• Cd •• p) I. I. th. speci.ied connection e.i.t., i t i • • ev."ed.
I. the connection do •• not •• is.t, th. co_and Is ignoT'ed. *1

231421-44

1-50

inter

AP-235

IPCO/USR/CHUCK/CSRC/LLC. C

Recv_FrameCpfd)
struct FD

struct
.truct

struct

*pfdl
*prbdi
.pf.;
.platl

RBD

FRAME_STRUCT
LAT

p1"bd • (stl'uct RBD *) Build1trCpfd-)T'bd_offset)i
pfl • • (struct FRAI'1E_ST~UCT *) prbd-)buff_ptl'l

if (pfd->1'bd_off •• t

,- NULL) ( 1* The,.. has to be
to the fd,
too shoT't.

if (pf.->d •• p -- 0) (

iI

rbd attached

or .15e the fl'ilme
*1

i~

1* if the frame is addressed to the Station

Component,

then,. respon •• me" b. required

*,

if ( ! (pf.-:> ••• p &.: C.-R_BIT) ) (/* if the '"am. received is a response.
inst •• d of ill command, then reJlI'ctl it.

aecau •• this Bafh,a .... doe. not implement
DUPLICATE_ADDRESS_CHECK. -> no response
fram •• should be ... ecy'd *1
Stati an_Component_Response (pfd) I

'* nat add,. •••• d to St.tion Component.

*1
1* check to ••• if the d •• p addressed 1s lIc:tivI *1
oliO I f ((pfl->d •• p <:<: (S-DSAP _SHIFT> .. O.OOFF)
0 ....
. (plat - .. laU(pfl->dup) » DBAP_SHIFTl)->stat .- INUSE ) {
(*plat'-)p_,.p_func) (pfld).
1* call thl function ••• ociated
with the ds.p rlclived . ,

retU1"nl

>

Put_F1" •• _RFAtpfd)i

1* .,..tu,.n the pfd 1f nat given to the use,. saps *1

Station_ComponentJt.lpon •• (pfd)
st,.uct

FD
*p,., • • •ptfsi
*blgin,..ptbd. *q.

Itruct FRAME_BTRUCT
st,.uct TSD
struct RBD

.ptbd.

*pT'bdl

=

prbd
(Itruct RBD .) BulldJ'trCpfd->rbd_ofhot),
p,., • • (ItT'Uct FRAME_STRUCT .) p,.bd->bu"_pt,. •.
• ",1 tch Cprh->cmd ..

~P

J'_BIT>

{

case

XID:

231421-45

1-51

AP-235

IPCO/USR/CHUCK/CSRC/LLC. C

while «ptbd •

O.t_Tbd()

. - pNULL) I

ptbd->oct_cnt - EOF81T I XID_LENgTH,
bcop .. «chaT' *) ptbd->buffJtT, aclid_f,..m.r;Ol, XJD-.LENQTH);
pUs. (.t~uct FRAI'IE_STRUCT *1 ptbd->buff ..... t~,

ptfs-')cmd - p,,"s->c.d.

c...

ptfs->d •• p • pT'f.-> ••• p I C_R_BITi J* .,..tUT'n the , .......
to the sende,.. *1
ptfs-> ••• p • O.
while' !SendJ"AlieCptbd, Build_Ptf'Cpfd->.,.,_ add,.»)1
br •• k,
TEST:

fo,. Cpl'bd •

CstT'uct RBD .) Bul1dJltl'Cpfd->rbd_off •• t),
II. •

beginJtbd •
p~bd

whil. Uptbd • Oet_Tbd()

•

pNULL,

prbd !-. pNULL,

8ui1d--"t~(p~bd->link))

•• pNULL).J

1f (II. !- pNULL)
q->Unlc • Off •• tCptbd),
el ••
b.ginJtbd :. ptltd,

ptbd->act_cnt • p,.bd->.ct_cnti
bcoPIJ«ch." .) ptbd->buffJtT'.
II.

ptfs •

D

(char.) prbd-:>buffJt1",
ptbd->act_cnt Ie O.3FFF).

ptltdJ
,.tf'uc:t FRAME_STRUCT

*>

beginJtbd-'>buff .. ptr;

ptf.->cmd - p,.f.->Clldi
ptf,->d •• p • P1"II'->55., I C_R_BITI

1* l'etu.,.n the frame to
the send • .,. *1
ptfs->ssap • 0;
whi le( !Sl!'ndJra•• (beginJtbd, Build_Pt,.Cpfd-:>."c_addT')).
b.,. ••• 1

231421-46

1-52

inter

Ap·235

IPCD/USR/CHUCK/CSRC/UAP. C

, ..****.............**** •••••••••••••••• ***•••••••••••••••• *.*****.********.***
*..
Use" Application Pl'ogl'am

*
..
..

Asunc to IEEE B02. 2/802. :3 Protocol Converte"

LF
CR
BS
BEL
SP

**1

*'

1* ASCII Ch.,.ect.,..
ESC
O,IB

IIdoUno
.deftne
IIdofino
lido Uno
IIdoHno
IIdofino

..

**···.·.***........ *

*
••••••••••••
***.......................***••••••** ••••••••

OIOA
0,00
0,09
0,07
0,:/0

.de"n. DEL
IIdoHne CTL_C

Ox7F
0,03

1* Hard ....,.. *1
IIdofino CH.JI_CTL
O,OODE
lido Uno CH_A_CTL
O,OODC
lido Uno CH.JI_DAT
O,OODA
IId,'ino CH-A_DAT
O,OODS
IIdoUn. UART_STATJlSK
0,70

'*

°

Intl"'1'upt ca.es fat' 8274 *1
IIdofine UART_TX_B
.dofino UART_RECV_B
O,OB
IIdoUne UART_RECV_ERR_B O,OC
.doUno EXT_STAT_INTJI 0,04
IId.fln. EXT_STAT_INT-A 0,14
char

fifD_t[25bJJ

ch.,.
'l'o_,,[256JI
ch.,.
...,..C5J, ..,rbC5JJ
unsigned
char
In_'::I.'o_1o. out_hfo t.

u_lhort

In_'lfo_1', aut_fifo_t'. actual;

t_buf _stat. ,. _bu' _stat;
cbufCB01J
1 in.,[Sl],

1* Command line buff.,. *1
1* Hanitor ,",od. displilU lin.

*'

unsignld
cha,.
dsap, ss.p, Sind_flag, local_.choi
ch.,.
DI.t_Add,.[ADD,J.ENll
cha,.
Multi_Add,.CADD_L.ENll

'*

int tmstati
teT'min.l made status: for l.aving terminal mode *1
int dh,x, monitor _fl1ag, hs_,tat;
1* fllags *1
Ilt.,.n
Ixtlrn

struct TOO
char

*get_TbdO,

extl ... n

st,.uc't: FLAGS

flagsl

Ixte ... n
ext.,.n

char
cha,.

.BuildJ't~( )i

lid_,,.ameClJ
whoamitl;

231421-47

1-53 .

inter

AP-235

IPCD/UBR/CHUCK/CBRC/UAP. C

•• t.,,"
•• t.,,"
•• t.,.n

stl'uct
st'l'uct
ch.r

•• t."n
•• tern
e.t.rn

unsigned long
u_short
u_sho"t

•• t.,,"
•• t.,."

elt.,,"
•• t.,.n

IlAT
LAT
*pNULL,

unsigned long

u_sho"t
u_short

e.t.,,"

unsigned long
u_sho,.t

•• t.,.n

struct

'*

BCB

rute],
latl:l.
gOOd_lilt t_cnt,
unde",.u"_cntJ
no_c,.,,_cnt;
defe,,_cnt.
.",._."1' _tnt,
",.x_col_cnt.
".cy_f"••• _cnt.
,.. ••• t_cnt'

seb,

Macro' t\lp.' of definitions

'define
'define
'define
'deflne
'define
'define
'define
'define
'define
'define
'define
'define

*'

RTB_DNB Dutb ICHJI_CTL. 01011), Dutb ICH_B_CTL. ""bCIIJ ...rbCIIJ 10102)
RTB_DFFB Dutb ICHJI_CTL. 01011), DutbCCHJl3TL ...rbCIIJ ...rbCIIJ ..OIFD)
RTB_DNA DUtb CCH.J\_CTL. 01011), Dutb CCH_A_CTL ..... CIIJ_. . CIIJ 10102)
RTB_DFFA DutbCCH.J\_CTL. 01011), DutbCCH.J\_CTL ...r.CSJ·.... CIIJ ..OIFD)
UART_TX..pIJI Dutb ICH_B_CTL. 0101), Dutb CCHJI_CTL ...rbCI J...rbC IJI

1211),

'*

Dutb (OxEA, OaOO),
Timer 1 lnt.rl'Uptl' eve,.., . 12~ .ee: *1
send_'Uag • FALSE,
e: • inb(0IlE2); 1* ,. •• d the 80130 lnt.".".upt M •• "..,I.t.,. *1
OUtbCOIE2, OIOOFB • c); 1* ",,.ite to the 80130 int.,.,.upt .. alk ,..giste,. *1

231421-48

1-54

intJ

AP-235

IPCD/U5R/CHUCK/CSRC/UAP. C

Di •• ble_Timer_lnt( )
(

tnt

Ci

c = inbCOxE2);
autb COxE2, 0.0004 Ie),

COCc)
cha,.

el

while ( CinbCCH_B_CTL) •
autb (CH_B_DAT, c) I

4) . - 0 ),

CHI
(

11th! 1. C Cinb (CH_I_CTLJ Ie 1) • • 0 lJ
rotuTnCinbCCH_BJ)ATI 110 0.7FI,
R•• dCpmsg,

ent.

pact)

che,.
.pmag'
unsigned cha"

ent, .pact,

unsigned ch.,..
I,
ch.,.
c. buft2001,
fiaT" ( i •

0,

c •

(c

!- CR) , . (c != LF) It&.

(:i

C 198),

) {

c • Ci () 81 Ox7FI
If Ce •• DS II e == DEL)
if Ci > 01 (

--1,

CaCDSI,

lIse

CaCSPI,

>= BPI
CoC, ),
bufC 1++1 -

CaCBSI,

if Ce

(I

=-

81 ••
if (Cc

CAl II (c
buft 1++1 • CRI

1;11.

L.F»

{

bu.t i++l • L.FI
}

.1s. CaCBELl

J

}

CaCCRl, CaCLFJI
If C i > entl

.pac t = cnt,

1151

.p.et • 1,
i

<: .pact

.pmag++ •

buftil,

fo1' (1 .0,

J

i++)

231421-49

1-55

Ap·235

IPCO/USR/CHUCK/CSRC/UAP. C

unligned char

1.

R•• d (lIcbufCOl. eo. ..ctual) I
I • SHpllocbuf[O]J,
returnC cbu'[ i l),
Wl"iteCp"'lg)

,hal'

.p.",

",hile '.pmlg !- '\0') -(
if
111
'\n')
ColCRJ,
Co(.pmll++"

'*p.'••

'*

FataICpm'g)
",rit. _ ......... to the Ic,..en then atop *1
che,.
*pmlg'

Wl"ite("Fatal: 1111
W,.iteCpm.g),
foT'(, J "

DugCpmsg)
ch.,.

'/* "rtte • m•••••• to the .e,.. •• n then continue *1

*pmsg,

WrtteCIlBug;

N);

WriteCpm •• ',

'*

A,.cii_To_Ch.,.Cc)

cha"

« '0' <-

c)

i f « 'A' C-

c)

if

convlT't ASCII-H •• to Cha,. *1

CI

returnC Ii -

...

(c

'0",
••

(c

<- '9'»
(-

'F'))

returnee - 0.37),

If «la' (c c) •• (c (1'lturn(c - OaS?),

Ifl/»

,..turnCOaFF',
Low.", _Ca.1 (c)
ch.r

<

«'.' (-

c)

if «'A' C-

c)

if

..

(c

<- '1'»

••

(c

<-

,..turn (c) I
,.,turn(c + 0.20';

'l'»

1"etu1'nCO',

231421-50

1-56

inter

AP-235

IPCO/USR/CHUCIVCSRC/UAP. C

Ch.,,_To.-Asci!(c. c:h) 1* convert c:h." to ASCII-He. *1
unsigned char
Co th[]1

unsigned char

ii

i = (c II: a.FO) » 4.
if (i < 10)
cheOl ... i + Ox30;

al ••

cheal = i + 0.37.
j = (c " OxOF) ;
i f (1 < 10)
chell CI i + 0130;

else
ch[ll = i
cht2J ;;:: '\0',;
Slcip(pmsg)
ch.T'

+ 0,37,

'*

skip blank. *1
.pmagi

11

tnt

fo,. (i ..

01

.p ... g

raturnCi);
R•• d_lnt ()

<

=-

t

,

J

i++.

pmsg++) I

1* Read a 16 bit Integer *1
wd. wh. wdl. whl, Ji
i. dan •• hex. doveT",

foT' (dane -= FALSEi done •• FALSE!
R•• dC&':cbu.pC01. 80. &cactuaUI
i ,. SlcipC&':cbuftOl)1

haverl
) (

for Che .... dover'" hover" FALSE. laid ... wh .. wdl .. whl ... 0;
(J • AscU,_To_CharCcbu'Ci]»
(. 15; i++) ..
I

jf

(J :> '1)
hex = TRUE;

wd
... h
if

= wd*tO + J;
= wh*16 + Ji
(llald

<

wdl)

dav .... -

TRUEI

if (wh <: ... hl)
hover ,. TRUEI
IaIdl •

Wdi

... hl •

"'hi

)

1F [cbufU] •• 'H'

II cbuf[i] ...... 'h' : I c:buf[ll •• CR ::
c:buf[ll == LF I: cbu"[il ......
'h' )
'H' II cbu"[ 1 J

i f (cbu"[ iJ
ho. l1li TRUE,
• f (hex == TRUE .... haver ~= FALSE)
done = TRUE,
i f (hex
FALSE
dover •• FALSE)
don .... TRUEI
.~

..

t

')

{

~~

....

231421-51

1-57

AP-235

IPCD/USR/CHUCK/CSRC/UAP, C

if C ~don.) (
WT'ti;e("\" Th1s nUMb." i . too Ittl. \" It ha. to b. le.1 than 65S3b. \n"),

W"tte(-'n Ent .....numb." --)

P),

)

el ••

WT'ttl(" 111 ••• 1 Ch.,..act.,.," Ent." a numbe", __ >"),

)

If (h.l)

,...tu1'n<-..")'

,..tu1'n(lIId )i

(valul, b••• , Id, chi wtdth) /. con".", an int •• _", to an ASCII It'l"ing *1
unligned 10nl
valUl1
u_short
b •••• width.
eha'"
che 1, Id,

Jnt_To~.c1i

fOT" (i - O. i < ,ddt'" 1++) (
J • "alul X b ••• ,
If (J < 10)
ch[i] - J + 0130,
81s1 ch[il • J + 0.37,
valUI • valul I b ••• ,

'aT' 'Ci • width - I. ch[tl _. '0' Me i ,. O. 1--)
chCiJ •
ch[lIIIidth] •

Id.
'\0'.

W1'it.j.ong_lntCdw,
unlignld long

u_Iho,.t

u_,ho,.t
ch.,.

t)

db..

ii

JI
ch[111,

If'(dhn)
In1:_To-"lc i i (dill.

lb.

81 ••

Int_ToJlsc i i (dOl. 10.
fo~

(J • OJ ch[ J] !- '\0',
lin.[i] • chtJ]'

Wrtt._Sho1't_lnthh
u_short .., li
u_ahol"t J'
c:h....
ch[61.
un_ilned 10nl
dill •

'.

'ch[O]. B),

" 'ch [0].
i--, J++)

1011

i)

dl.u

III.

i f (dbOl)

Jnt_To_AacU(dw,

16,

'0', .c:h[O],

4)1

.1.8

231421-52

1-58

inter

AP-235

IPCD/UBR/C/iUCK/CBRC/UAP. C
Int_To.-Alcitcdl.b 10, '0', "chCO],
for  ""

cnt) /* P.'&I -

*'

point.,. to the output m• • • • • • • ,

1* add - paint.,. to the ad dr •••

/. cnt - numb." of b\lt •• in thl addr ••• *1

ch.",

*P.SII' addt], c:ntl

'01' C I

;

)

(

WritlCplIlg)J
R•• dCltcbufCO], 80 • • • ctu.l) i
for (J - •• ipU.cbufC01), i
i <: a*cnt I i++.
if (C'O' <- cbufCJ1) lele (cbuf[J] <- '9'»
cbuftil a cbuf[Jl - '0',

.0,

els.
,I ••

if (C'A' <- cbu.tJl) , . Ccbuf[Jl
cbuftiJ • cbuftJl - 0137;

i' «'.' <-

<-

J++)

0(

'F'»

cbufCJ]) Ie.. (cbuftJl <:- 'f'))

cbufCl1 -

cbufCJl - 0.'7,

else (
Writ.(" Il1.g.1 Ch.".ct."\n")l
by-.alll
)

if (i :>= :Z*cnt br •• lli

1)

.par (1 .. 0, :I. <- tnt - 1, i++)
add[(cnt - 1) - il
tbuft:Z*l] « 4
";II

J

cbu '[2*i + 1J;

IWrit._Addr(padd, tntl
char
padd[ J. cnt;

i. c[3JI
fOr (

J

cnt )0

i

cnt--) (

231421-53

1·59

inter

Ap·235

IPCD/USR/CHUCK/CSRC/UAP. C

t • p.ddtcnt-llJ
C;h." _To_Asc it (i. lcetOl),
Wrt hClocCO] II
e[Ol •

"n',

ttll • '\0',
W,.tte(lcc[Ol);
)

<

at'ruct

FD

.,,,,.. .pt •••

.truet FRME_STRUCT
• truet TID
.t,.uet RID
char
tnt

*ptbd. *lIe,I"-Itbd. *ql
.prbd,

.,,,bu"
cnia

p1'bd =- CstTuct ABD .) Build.-pt1'Cpfd-:>,.bd_off •• th
pr'. - CatT'uct FRAtfE_STRUCT .) BUildJltrCprtuf->bu"Jtr),

... iteh Cprh->e1ld 10 ~P J JIlT>
<
ca..
01:
if Cllonitor_.lag)
b1' •• k.
1* Don't put d.t. in fifo unless in t.,.minal ,mod. *1
pTbu' •

(cha", .) ,,.,.,

'* •.,i,

p,..bu' +- 3,
ent • 3,
pfd->1.ngth -

ove'" the h •• d.,. info and point to the d.t. *1

3.
far ,(' prlld !- pNULL' tnt - o. p"bu' - (ch." .) p,.bd->buffJtrO)-(
fa,. ( f cnt < (prbd->."t_cn't II OI03FFF) ... ,'d->length':> 0,

ent++, p,..bu'++, pf'->length--) -(

whileC,,_bu'_stat •• FULL),
Fifo_R_ln (*'T'bu')J
pT'bd • Bui ld_ptr (pT'bd->l ink) I
II1II- 0 • ., pT'bd
!~ pNULL)
F.t.l("U.p: R.cv_D.t __ l(p'd) ")1

if (p'd-:>l.ngth

•• "dil 1* DEBUG *1
}

b,.e.lu

cas.

XID·

==

\IIhil. (ptbd - Oet_TbdO)
,NULL),
ptbd->act_cnt • EOFBIT I XIDJ-ENgTH,
bCOPItI (ch.r -) ptbd-:>bu"-pt"~ 8clid_fT'ant.[Ol~ XID_LENGTH);
,tfs =- c,t,.uct FRAPE_STRUCT .) ptbd->buffJtri
,tf.->cmd •

'1".->C."
,r'&->, •• , I C_R_BlTI 1* r.turn
the frame
to the sender *1
ptf.-:> ••• p - ".'1
while( !S.nd,Jr ..... ('tbd, - Sui ldJtr(pfd->,rc_addr»);

,tf.->dsap a

231421-54

1-60

AP-235

IPCO/USR/CHUCK/CSRC/UAP. C

case

TEST:
for (prbd •

(st'l"uc't RBO .) Bui 1 d1t,. Cpfd-:>rbd_offslrt),
q, -= begin-ptbd • pNULL, prbd ~. pNULL,

pl'bd • Bui Id_Ptr CpT"bd->l ink») (
...hil. CCptbd • aat_TbdO) ... pNULL),

If (q !- pNULLI
q-:>lInk - Offset (ptbd I.
el ••
begln..JItbd • ptbd.

ptbd-:>act_cnt • prbd-:>.ct_cnti
bCDPlltech.,. .) ptbd->buff_pt1',

(eh.,.

*)

p"bd->bu'f_ptr,

ptbd-:>act_cnt 8r O1lll3FFF);

!I - ptbd.
ptfo •

(.truet FRA"E_BTRUCT *1 begln..JItbd-:>buH..JItr.

ptfs->c.d • pr'.->cltd,

*,

C~JUTJ
, . ,..tut'n the f,..me to
the •• nd.,.
ptf'-)llap • , •• pl
!.Ifh Ue( !Sendj,..me Cbeg in...ptbd, Bui Id_Pt,. (pfd-:>src_addr) )) I

pt,.->d •• p • ,"'.-)II.p I

b,. •• lu

>
Put_Fr •• _RFA(pfd) I

'*

Fifo_T_OutC)
{

'*

ratu,.n the fra"'e

*'

c.alled b\l main p1'og"a", *1

c • fi'D_tCout_'l'o_t++lJ

'*

Di.able_Uart_lntC "
if (aut_fltflo_t •• in_,t'o_t)
if the fifo is ."'pt\l
t_bu._stet .. EMPTV,
,top fI:i.lling r,..nl",it Bu'f.,. D.,c,.iptar.
el..
if the fifla III.' full .nd il nalal d,..ining *1
,i' (t_bu'_lot~t .D FUL.L •• aut_flifla_t - SO ... in_fli'D_t) <
tu,.n Dn
tha spigot *1

'*

'*

*'

'*

*'

ATB_DND.
t_buf _,t.t • INUSEI

Eneble_U.,.t_lnt( ),
,.eturn(c ),
1* c.lled b\l UiII1't receive intaT'1'upt *1

F1fo_T_ln(c)

cha,.

c.

fiflD_tl:in_'i'D_t++l == Ci
If (t_buf _"tot == EI!PTYI

231421-55

1-61

inter

AP-235

IPCO/UBR/CHlJCII/CSRC/UAP. C

.1..

'_bu._.ta' • JNUSE, 1* .t .... , filling T,...nlilit Buffer D.scriptor *1
1* if th.,.. are onlv 20 locationa l.,t, turn of' the .pilot
If Ct_bu'_stat •• INUBE •• in_'lfo_t + l!O out_'lfo_" (
RTS3IFF8.
'-'ul _Itat • FUL.L,

'*

Fifo_R_Oute)

<

called ltV ,,..nl.i'l: int ....rupt

if (out_fifo_r ••

1"_'1'0_")

r _bu, _stat • E"TYJ

'*

*'

*'

if the fi'a i , ••ptv

*'

'* the "fa ".1 full and ,. nOIll d,..inlng *1
C,,_bu'_stet - FULL . . out_'I'o_" - SI - in_fifo_")

.1..

if

If
l' _bu' _,tat • INUSEf
,..turnCC )i

Fifo_R_InCcl
cha...

CJ

'*

cell •• bU Recv.J)4lte_lC) *1

'l'o_"l:ln_"'o_",++) - CI
Dheblo_U. . t,;,lntC II
If C,,_bu'_stat -- EI'I'TV)
UART _TX_EI_B.
CoCO).
I. pri . . th internpt *1
r _bu, _,tat. JNU8E.

el..

if

'*

*'

if the bu",,,, i. full. indicat. it
C1'Ju,_,tat - lNUSE •• 1"_"'D_" _. out_'i'o_1')
r_bu,_,tat • FULLJ

Eneblo_U. . t_lntC ).

outbCCH_B_CTL. 21.

'* point to RR2 In 8274 *1

u .. UART_TXJI:
'if (,,_buf_Itat •• EI1PTY)

UART_TXJlIJI.
RESET_TX_INT •
• 1 ••

ouU CCHJlJlAT. Flfo--,,_OuU».
b ..... ~J

231421-56

1·62

AP-235

IPCO/UBR/CHUCK/C8RC/UAP. C
c . . . UARTJlECV_ERRJI:
Dutb (CHJt_CTL.

1),

'*

paint to RRI in 8274

.t.t • inb CCH_B_CTL) J

*'

DutbICHJI_CTL. 01301,
i f I.tat .. 0.0010)

W,..:lt.C"\nP.,..it" E"raT' Detected\"");
if

C .t.t

.. 0.00201

Wl'ite''''nDve.,.run ET'l'or Detected\n");
i f I .t.t .. 0.0040)

Wl'i t. C• \nF"ellling Error Detected\"")J
b,. •• lu

c •

inbCCH_BJ)AT),

if (hi_stat •• TRUE) (
hs_stat • FALSE.
br •• lu

i' (local_echo)
CoCc"
:1,"

(c.

••

'*

'*

Flag to t.,.minet. High Spe.d Transmit mode . ,

*'

echo the cha" back to the t.,.lft1n.l, could cause
a ,,..namit overrun if TI inte"1'upt i . enabled

eTL. C)

t.atat • -FALSE;

.1 ••
Fiflo_T_In(c),

bre.k,
c . . . EXT_STAT_INTJI:
Du1:bICHJI_CTL. 0.101,
bl' •• II.
c ••• EXT_STAT_INTJI:
DutbICHJI_CTL. 0.101,
break;

)

EOl_80130_8274,
EOIJ1274,
I.,.;!C)
{

.end_fleg • TRUE.
aut .. (OxEA,

125);

DutbeGIEA, 0.00),
Dutb 101EO. 0162),

'*

Tim.,. 1 inte1'rupta eve ... " .12' •• c . ,
1* EOI 80130 *1

231421-57

1-63

AP-235

/PCO/UBR /CHUCIVCSRC /UAP. C

LoadJ."p!)
(

'aT'C, J)

0(

R•• d-"ddT'CtI\n\nEnt.,. this Btatlon'. LaAP in He. --:> ", ..... p,
i f C!AddJl.apJlddnIOC."p. R.cvJlata_lIl (

1),

WT'tteC"'n\nE","oT': LSAP Add ...... mu.t: be on. o' thl 'ollotdnl: 'n"',
Writ.C"'"
20H, 4OH. 6OH. BOH, AQH. COM, EOH \n")'

>
Load-"ultic . . tC I
(

'a,.

«

I

I

)

(

R•• d~ddl"( "'nEnte ... the Multic •• t Add,. ••• in HI. __)11,
,,"ul UJlddr[OJ. ADDJ.ENI.
If CCMultlJlddr[Ol • 01011 •• 01

.10. (

W,.tt.C"\nSo"'''~1

thl LSI of the "ultic •• t Add" • • • •u.t 'e l\n"),
If C!Add-"ultlca.t_Addr.IOI ..Mult1J1ddr[OJII (
W1"iteC"\n\nSo,.",. Multica.t Add,. ••• Table i • • ull "nil),
b..... lu
)

,I •• -C,
W,.ttitC"'n\nWauld .. ou Itll. to edd anath.,. Multic •• t Add,. ••• ?"),
Write' If CV aT' N) -::> "h
if I !V•• CII
b,. •• k,

RIIIIDVI-"ultica.tC)
(

.ar (

i

I

)

0(

R•• d-"dd"C "\nEnt.,. thl

"ultic,.'

Add,. ••• the' \IOU .. ant to delete in H•• --)." ,
,,"ult1_Addr[OJ. ADDJ.ENI'
If CCMuUIJlddr[Ol .. 0.011 •• 01
,
W"iteC -'nBa,.,.", the LBB af the "ultic •• t Add,. •• 1 mUlt b. 1 \n")J
.1 . . ( If ('!Deleh-"ult1c . . tJlddnIlC,,"ultIJlddr[Olll (
. WTiteC"\n\nBa,.,. .. , tihet "ultic •• t Add" ••• da •• n't e.ilt!\n").1
b,. •• ki
)

et .. (

Wrtt.C"\n\nWauld Vou l:U:. ta del.te .nother "ultic.lt Add" ••• ?"),
WTtteC" (Y D" Nt --> ")J
if C!V. . III
b,..ekf

231421-58

1-64

inter,

AP-235

IPCD/USR/CHUCK/CSRC/UAP. C

Pl'int--'dd" ••••• C)
{

.truc:1:
lnt

MAT .p ... ii1

.t.ti

Write''''" This Stations Hast Addr ••• 1s:

")1

Write_AddrCIc..,hoa",i[Ol. ADD_LEN);
W,.tte("\n The "Add" ••• a' the D•• tination Node is;
Write.,AddrC.D. . t_Addr[Ol. ADD_~EN)I

Writee"\" Thil Station. LSAP Address is: ");
W"ite_Add,.' •••• p. I),
WriteC 'I ," The Add"I". D' the D•• tination LSAP is:
W"ite..Addr'lcd •• p, 1);

.t.t • FALSEJ
'or Cpmat

/ill

,

...

at[O]s

pilat

<-

&!matCI'IULTI_ADDR_CNT -

"),

");
1 JJ

Pnlilt++)

if (p •• t:-:>.1:.t •• JNUSE) (

.t.t • TRUE.
b,. •• lu
)

If Cshtl

{

Wl'ite''''n The .alloliling Multica.t Addresses .re enabled:
'01'" (p ... t a bateOl; plII.t <- &cmatCI'IULTJ_ADDR_CNT if (p ••1:->.t.1: •• INUSEJ (
Write.,Addr C.pmet->edd,.[Ol.. ADDJ.ENI.

lJ;

OIl;

pmat++)

Writee"

"),

el ••

WriteC"'" There .,.. no Multic •• t Add"esses enabl.d. \n H

);

In1 t_DataLinlf ( )
{

int
if

stat;

= Init_Llc(») •• PASSED)
W,.lteC"\n\nP •• sed Di_gnostic Self T •• t_\n\n\n H

«~tilt

);

.1 ••
jfCst.t =m

FAI~EDJlIAQNDSEI

W,.tt.(H\n'nF.il.d: Self Test Diilgnos. Commilnd'n'"),

else

i f Cstat a. FAI~EDJ.PBK_INTERNALl
W,.it.("\n\nFail.d: Int.,."ill Loapbilck S.lf T •• t\n"),

.ls.
ilC.tat

~a

FAI~ED_~PBKJ:XTERNA~)

W,.,t.("'n\nF.il.d: Ext'1'n.l Loopb.ck S.lf Test\n");
.1se
ifCstat

=-

FAI~ED_~PBK_TR"'NSCEIVERI

W,.tte("\n\nFili,lld: Ext.,.n.1 Loopback Th,.ough T,.anacltvl,. Self TIst\n'").

outb (OxEO. 01.31) I
outbCOxE2, 01.20).

l*initaUII 80130 pic 1* lCW2 *1

ICWl *1

231421-59

1-65

inter

AP-235

IPCO/USR/CHUCK/CSRC/UAP. C
Dutil (0IE2. 0110) I
Dutil (01£2. 0.00) I

1*
1*
1*
1*

outb IO.E2. 0.101,
outb COIE2. O.FFII

ICW3
ICW.
ICW"
m•• 1I:

*1
*1
*1
all inte"l"upts *1

out1llCOxFF20. 010020),

outbCO.EE. 0.341,
outb CO.ES. OIBSII
QutbCOxEB. 0.08), 1* BYBTJCK. •• t 'or 1 ... ee *1
outb CO.EE. 01701'
outb(O.E/.. 1251,
outb(OIEA, O.OOh /. Tillie,. 1 int.",.upt. eve"" . 12' sec *1

1* Inl ttali I.
outb (CHJI_CTL.
outbCCH-,,_CTL.
outb(CHJI_CTL.
outb(CHJI_CTL.
outbCCHJI_CTL.

the B274 *1
0.1011 outbCCHJI_CTL. 0.2Sh outbCCHJI_CTL. 0.301,
0.381,
211 outbCCHJI_CTL . . .~bC21 .0.141,
II, outbCCHJI_CTL •.• ~bCll ·0.151,
51! outbeCHJI_CTL. . .~bC51 • O.EAI,

W,. it.e Ii\n'n\"\"'n\n\"\n\n\n'n\"");
W,. i t. c..
• ..
W1"it.C"
.. 825B6 IEEE 802. 2/B02. 3 Compatibl. Date L.ink DT"iv." *'n");
W,. i t. ( II
• • • • • • • • • • _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .________ \ nil) ;
WT"i t. (It\n\n\n\n\"\n\n") I

******.................*.......................**•• \"'" );

In! tJlat"LinkC I,
dhe • • FALSE.J

manito,. _'la. - TRUE;
R•• d..AddrC"\n\nEnte1" the Add,. ••• 0' the D•• tination Nade in He.

--> ",

IoDnt_Add,.C01. ADD....LENI,
Load_L •• p ( ) I

,R •• d_Add1"'("\"\nEnt.,. the D•• tination Nad. 's LSAP in He.

--> ".

Wl'it.C"\n\nDa "au ....nt to Load an.., Multica.t Add,. ••••• ?

(Y 01" N» __ >"),

IId •• pI

1);

i f (V . . el)

Laad_"ulth: •• t (
PT'lnt~ddres.es(

int

, Itruet
ch.,.

),

);

f"allle_ent, buf _entl
TBD

*ptbd. *q. *b.ginJtbd,
.pbu •• Ci
'

W1"it.C"\" Would 'OU 1ill. the local echo an? CY

Q1'

N)-->")J

ifCVes() »

231421-60

1-66

AP·235

IPCO/USR/CHUCII/CSRC/UAP. C

local_echo" TRUEJ
.1 ••
local_echo:;. FALSE.

Writ.("\" This program w1ll

nOlAf ant.,. the terminal mode. \n\n");
WT'ite("\n Pres. "'C th.n CR to r.turn back to the menu\n\n");

1* Initialize Fifo vilT'iabl •• */

aut_fifD_t

=:I

in_fifo_t .. aut_fifo_\", • in_fifo_"

t_buf _stoillt =- EMPTY,

.a

01

,. _bu' _stat .. EMPTY,

EOI_BOI30_B2741

Enable_Ua,.t_JntC ),
Enab la_Tim.,. _tnt () J
manito," _flag III FALSE.

tm5tat = TRUE;
lIIhile (tmstat)
far ('Tame_cnt -

01

framll_cnt

<

MAXjRAME_SIZEI

.,h:ll. «ptbd .. Oat_TbdC)) •• pNULL);
pbuf -

(ch .... *) ptbd-:>buffJltT'1

bu' _cnt =- 0;
if! ('''tlme_cnt . - 0) (

'*

q,

-= ptbd) {

1* get iii limit buff.,. from the
data link *1

1* point to the buffer *1

if this is the fir.t bu'fer, add on IEEE 802.2
headel" info1'mation *1

begtn,JItbd D ptbd;
*pbuf++ III d •• pl
*pbuf+'" - •• apl
*pbu'++ • UJI
bu' _cnt • 3,

Il->link =- OfFsetCptbd)1 1* if this isn't the first bufFer
link the previous buFfer \ltith the new one *1
1* fill up • datil IJ.nk .mit buffer f,.om IIs~nc transmit fife *1
for C ; buf _tnt < TBUF _SIZE leI.. frame_tnt < MAX_FRAME_SI2'EJ
bu' _cnt ...., pbuf++, ,rame_cnt++> {
if (fT'.me_cnt !. 0 &-Ie send_flag)

else

br •• kJ

4IIhile Ct_bu._stilt == EMPTV);
1* wait until fifo has data *1
if C(c • *pbuf • Fifo_T_DutO) .... CR) {
+"'bu' _cnt i ++pbufi ++f,..me_cnt.
br ••• '

==

if Cc
CR : I bu._cnt < TBUF_5~ZE II send_flag)
ptbd-)act_cnt • bu' _cnt t EOFBIT;
send_flag ::II FALSE;
br.ak.
while(!SendJ'T"ameCbeginJltbd, &-D.st_Addr[O]».

< 1*

1* keep

last buffer in list *1

tT'~ing until
successful *1

231421-61

1·67

AP-235

IPCD/UBR/CHUCK/CBRC/UAP. C

Di •• ble_UaT"'_lntC h
Di.able_Tilll." _In\:()1
monito,. _flag =: TRUEs

.truet

*8uildJ"' ..... (cnt)
cnt.

TDD

u ..shart
u __ hart

"'ruet
char

.pOl'

(

bu' _ent. '"ame_ent. if
TBD

.ptbd,

*Il'

*bellinJtbdl

.pbu';

J

J

Cl. ptlld)

whil. «ptlld - Oet_TlldC»

... pN'-A..L); 1* get .. amit buff.,. ""om the
data link

,bu' = (cha,. .) ptbd->buffJt~J

bu'_ent

a

01

·ifl (fir ••• ent _. 0) (

'*

*'

1* paint to the buffe,. *1

if this i . the 'j,.8t buff.,.,
h •• de ... infDrmation */

add

on

IEEE 802.2

beginJtb" • ,tbdl
.,bu'++ •

dsap •

• pbu'++ • • s.p'
.,bu'++ • UJI

bu' _ent • 3.
}

q->11n. - Of'.eteptbd),; 1* if! this i,n't the fiT,.t buff."

else

link the p".viGu, buf,.,. with the new one
'*for fill
d.t. link
buff.r lIith ASCII ,ha,,_ct.,.. *1
(; bu'_tnt < TBUF_SJZE Srlc cnt > 0;

*1

XIIlit

up •

i++, buf _cnt++, pbuf++, cnt--,

fT'.me_cnt++)

.pbuf • il
H

(1

> Ox7EI

i

Ox1F.

=

)

if (cnt =... 0) { 1* lest buffer in list *1
ptbd->.ct_cnt - buf _cnt I EOFBIT;

breaks

Monitor _"ode'»
{

u_short
IImi t. cnt, i;
struct TBD
*BuildJrameC), *ptbd',
Writ.(" Do

"OU .... nt

thi. station to transmit? (V or N) -_>

I»;

1f eVes()>>

231421-62

1-68

Ap·235

IPCD/USR/CHUCK/CSRC/UAP. C

'or (amit • FALSEJ .... i t •• FALSE; ) (
Writee"\" Ent.,. thl nu.bl,. of deta bVt •• in the ,,.aml -> "),
t n t . Read_lntC)i
I f Cent> 204111
Writ. ("\" Sa,"'rv, the numb,,. has to b. I ••• than 2046!\"")'
11.1
.mit • TRUE,

Wt'tteC"\" Hit .nV .... to IX i t "onttar ,",odl. \n\n")1

• FrI
0' •••

Writ,C"
W,.itIC"

• of! Qood
F,. ••••
Writ,C'1 T,..n ... itt,d

CRC
Er1"O,..

Goad

Alillnment

E,.",or.

Rlclived

No

Rlceive'n"),

R•• ou,.'1
E",,,,o,,.

Ova,.,.un\n") J

E,.,.ors\"");

1* "01234'67B901234'67B901234'67B901234'67B901234'67B901234567B901234'67B9012345679
.1111'11.1

XI •••• I •••
•••• 11 ••

2'

i (791
linot I J • 0.20,
linot79J • CR.
lineCSO] • '\0',

for U

1111

.11111 ••

11
• OJ

33

••••

44

.XXI

57

.1 I •

71 *1

t++)

=-

",hllo CllnbCCH,JI_CTLI " II
foT' Ci • O. i (72J t++)
line[l] =all O.:zO,

01 (

WritlJ,.onl_lntC good_Illlli '_tnt,
W"i tl_Lanl_lnt '-r:.cv_• .,. ...._cn't.
W1"it._Sho1"t_IntClcb. C1'C_'1"1"I.
W,.it._Sho1't_IntClcb .• In_.,,,,,,
W1" i t._Sho"t_Int (Icb. "IC_,,."I,
W"it._Short_IntClcb.ovT'_'1"1"',
W~lto C.lInotOJ I,
If C... ltI (

11) I

2S),
33h
44),
~7) I

11)1

ptbd - BulldJnmo(entl,
"'h 11. ( !S.nd,.Fr.m.C ptbd, IrD •• t_Add,,[Ol»J
• CI

Itruct

n.

TBD

*ptbdi

hl_Itat == TRUEi
EDl_BOI30_B274'
Enabl._U ... t_lntC

)J

231421-63

1-69

intJ

AP-235

IPCO/USR/CHUCK/CBRC/UAP. C

whll. Ih,_"t .. "

<

while _(ptbd - Oet_TlldC»

•• , pNULL),

'*

'*

get . . . . tt buffa" frail

tho dd. link *1
ptbd->act_cnt 1- EOF81TJ
.et the End D' Frame bit *1
whileC!Send_F,..meCptbd, IcD•• tJdd,..I:OJ»; 1* Send F.......,

}

eh.,.
ehtl1::1, b8'., d.idth, ... idth,
unlt"ned
long
temp'

11

-

i

OJ

1--)

'"am.'"

W,.itll(" R.e.iv .... overrun
for Cl • I, i <= 12 - I,,;,..~t ••

II~.

'&"'+'

CaCSP),
temt. = ~;::... ".,,. ....
.&nt_TD~5C i i Cti,.p. b •• e. ' " Itch [0]. ",tdth);
for ( i • width - Ii i >- 01 i--)
Ca(chCil),
Writee","," 82586 R••• t: 1'\.
for «i • 1; i <... ~.,
Wl.d.:h. i++)

1".,

CcfSP':
t Itm~

1' • • • '_cnt,

z.

Int_To_Asc:Li Ct.mp. b.... ' , I leeh [0]. width) I
fol' (:I. =- width - 11 i )= 0; i--l
Co(chtiJ)1

WriteC"

Transmit. IInd"l'f'un ..... m•• :

fn ... t j Ilol 1;
ColSP),

.i. ...=- 11 -

<idth.

t.mp - underru"_cnt,
Int_To_Asciiet •• p. b•• e •. '

'a,.

( i ,. width Colc:h[i])'

1;

i

Writ.' "\"\" loo," C.Rt:I:
f.n

~i ... 11
CO(SP)I

i

<=-

>=-

&leh[O],

i.

")1

i :> ..

I

"

no

Ca(cht1J)1

t++)
Sec.h[Ol.

"--1

W.. ite'" SOE .1'1'01'.: "),
t"or (i = 11 i <- 2' - width;
Ca(SP),

temp = _,a_arr _cnti
Int_TD_Asc i i (temp, bllse,
for ( i = "idth - 1; i

,=

CDCc:hl:l]li
~rJ,teC

for

i

<=

21 -

lIIidth);

i++)
~ch[O],

• '.

width) i

i--)

\11

"\n\n Haximum retru:

(i. • 11
CoCSP),

... ldt"~;

;--'

26 - width,

tl"'P .. no_c,.,_cnt.
Int_To_Alcii.U.,.p. b •• a;
'01' (1 .... idth -

"

OJ

">;

i++)

II),

lIIidthi

i++)

tamp D max_col_cnt'
Jnt'_To-AsclHtempI base. ' " 'chtO], lIIidth);
for Ci 1:1 lIIidth - I, i >- 0, i--)
CDC ch [i l) I

WriteC" Fram •• th.t deferred:
far Ci • 1, i (- l ' - d1llidthi

I'),
1++)

Co(SP),

[nt_To_AsciHd.fe'T'_cnt.
for (i := dwidth - I. i
CaCch[ll),

bilse.

>-

OJ

I

I,

lr:c:hCOl,

dwidth)i

i--)

Write ("\n\n Commands. are: \r,\n"),
Write ( .. T - Termin.l Hode

231421-65

1-71

Ap·235

IPCO/USR/CHUCK/CSRC/UAP. C
W,.it.
W'r1t.
Writ,
WT.:L t.
W,.ite
W1'lt.

X P' P (" A «" S -

'High SpI.d T,.an.llit Hade
Print All Counter,
Add. Multi, •• t Add ......
Changl thl aSAP Addt'I'.
(" N - Cheng. D,.tination Nod. Add" •••
(" R - RIl-InitlaUzI the Dat, Link

(I.

int

Y - Change T.... n •• i,t Statistics'n" h
C - CI ••,. All Caunt.,.,'n"',
.
Z
D
L
8

- Dllltl • Multica.t Add,. •• ,,\""),
- Chang_ th .. DSAP Add,. ••• \" .. "
- p,.int All Add,. ••••• \" .. "
- Chang' the numb.,. Base'n" h

1:1

Init_Uop(l,
P~int..H.lp (I,

faT' CH) (

W,.it.

e"\"\"

Ent,,. a co•• and. tuP' H foT' Help

--> ");

c • R.ad_Cha,.«) I
.witch CLDWll'_C •• ICc»
CI"

'h';
P~int..H.lp

e),

bl' •• lu

ca •• 'm':
Hanita",-"odaC)1
br •• k,
ca.e 't':
Terminal_Mode C) J
br ••• ,

ca •• ' K':
Hs_Xmit_"adl( .,
b..... II,

ca •• 'v':
Wl'it""," T,..n.mit Statistics .T'. no ...

(:~~::'c::~~\~nW::l~) \IOu

if
Ill ••

if

")i

lik. to changl i t ? CY 0,. N)

W1'ite(lIof'. \n Would 1I0U l:Lke to chan.e it ? CV 0,. N)

ev .. e» (
i' (flagl .• tat_on

••

--»

")i

--> ");,

1)

fl •••.• tat_an • O.

elle 'la ••.• tat_an • 1.
bT'.alu

ca •• 'p':
P1'int_entC ).
b1' •• kJ

ca •• 'c':
Clear _entC),
bT' •• lu
ca., 'a':

Load_l'Iultica.tC'1
bT'eaks
case '1':

Remove-"ultica.tC ),
break.
cas. 's':

231421-66

1-72

AP-235

/PCO/USR/CHUCK/CSRC/UAP. C

De lete_Osap_Adllres!t( ssap);
L08d_Lsap ( );

case

break;
'd I:
Read Addr(lI\n\nEnter the De.tination Node's LSAP

in Hex

--> ",

&dsap.

1).

break.
cas. 'n';
Read_Addl'( n\n\nEntl'r the Addr ••• of the Oe.tination Node in Hex
&COeost_Addr[Ol,

--> ",

ADD_LEN);

case '1':
Pri nt_Addr ••••• ();
bT'l!'ak,

c .... '1":
50ftware_R •• et( )i
Init_OataLink () I
Add_Osap_Address (ssap,

Recv_Oata_l);

break;
case 'b I:
Writ.("\" Th. c:uT'rl!'nt base is ");
if (dhe. =a TRUE)
W"ite'''Hex. \n Would "ou like to Change i t ? (Y or N) --> ");
else
Write("Decimal. \n Would IJDU like to change i t 7 (Y Dr N) __ >

It).

if (Yes(»
{
1f (dhe. ::a.... TRUE)
dhex = FALSE;
e1s11 dhex == TRUE.

bre ... ;
default:
Wrlt .. ("'" Unknown command'n")J
break;

231421-67

1-73

inter

AP·235

IPCO/USR/CHUCK/CSRC/ASSY. AS"

name

c: ••• V lupport

.tack
Itletap

•• gmlnt "tee k
label
word

.tack

ends

DLD_DATA

•• III"'lnt public:

e.t,."
SEQI'tT_: word
DLDJlATA

end •

• eg",.nt public

UAP_DATA
UAP_DATA
OLD_CODE

UAPSODE

elt.,."

••• ",en1; pubUc

'CODE'

ends

•• gment public
'CODE'
J.,._Ua'rt_: f.", 1 • .,.:2_: f.", M.l"_:

.lgmln1; public

public
public

11,,7_: fa"

f.,.

'CODE'

inllll_' outw_, init_intv_, In.llll_,· di •• bll_, Buil(_Ptr
Dff •• t_, begin. lnb_, Dutb_

oqu
oqu

tOP + bJ
tOP + SJ

•• s.ume

CS: Dei_CODE

••• u".

f.".
f."

1sT' _T1meout_: far, 1sT' _586_:
1 .... 6_: fa", 111'~_: '1111', 1.,,1_:

ends

UAP _CODE

1
."'1
8'1'512

'DATA'

ends

I.t.,."
e.t,."

OLD_CODE

'DATA'
data !leament addr •••

J

OS: DLDJlATA

,+
initialilation progTam fo,. the 82586 data link driv ....

•u
mav

mav
mov

DLD_DATA ; get b ••• of dg1'DUp and
SeQMT_, a.
i p••• the segmlnt value to thv c prDgram
ds, ex

81,

call Main_

~

go to th. c p'l'D91'am

hlt

inb

proc
push
.. DV

pUBh
.. DV

in
pDp
IIDV

fn
8P
DP. SP
DX
DX • • I"g 1
A~. DX
DX
SP. OP

231421-68

1-74

inter

AP-235

1-75

inter
IPCD/USR/CHUCK/CSRC/ASBY. AS"
pU5h

mov
m.v
m.v
pop
rot
Offset_ endp
•• rve_int_isT'
push
push

push
push
push
push

push
puah

mov
m.v

....

call

BP
BP. SP
AX • • ,.gl
BP. BP
BP

proc

AX. DLDJ)ATA
DS.· AX
EB. AX

Is,. _5B6_

p.p
p.p
p.p
p.p
p.p
pop
pop
pop
iret
serve_tnt_is"

EB
DB

•• rve_int_B274

proc

push

f ..

AX
BX
CX
DX
BI
DI
DS
ES

01
SI
DX
CX

ax

AX
endp

far

AX

push

ex

push
pU15h
push
push
push
push

CX
DX
SI
DI
DS
ES

IOOV
IDOV

AX. UAI' J)ATA
DB. AX
EB. AX

m.v
call

Isr_U.,.t_

pop
pop
pop
pop
pop

ES
DB
DI

81
DX

231421-70

1-76

inter

Ap·235

IPCO/USR/CHUCIVCSRC/ASSY. ASM
pap
pap
pap

CX
ax
AX

t,..t
•• rve_tnt_B274

endp

serve_tnt_timeout
push

AX

push
push

ax
CX

push

DX

prac

push
push

SI
01

puoh
push

DB
ES

may
may
mav

AX. OLOJIATA
DB. AX
ES, AX

pap
pap
pap
pap
pap
pap
pap
pap

E5
OS

01
51

OX
CX
ax
AX

irat
•• rve_tnt_timeDut

serve_int1_ta1"
push
push

push
push
push
push
push

'a,.

endp

pToe

AX
ax
CX
OX
51

01

push

05
E5

may
may
Olav

AX. OLOJIATA
OB. AX
ES. AX

call

IST'7_

pap
pap
pap
pap
pap
pap
pap
pap

E5
05

01
51

OX
CX
ax
AX

231421-71

1-77

AP-235

IPCO/U6R/CHUCK/C5RC/A6BY. ABM

iT-.t
•• rv._int7_i!l"

5.1've_1 nt6_i 51"
push
push
push
push
push
push
push
push

mov
mov

.ndp

for

prot
AX
BX
CX
DX
SI
DI
DB
EB
AX.
D5.
EB.

DLD_DATA
AX
AX

call

15r6_

pop
pop
pop
pop
pop
pop
pop
pop

ES
DS
DI
BI
DX
CX
BX
AX

lret
sel"vI_int6_i5"
•• rvI_int5_is"

Indp

proc

for

push
push
push
push
push
push
push
push

AX
BX

mov

AX. DLD_DATA
DS. AX
EG. AX

mov
mov

ex

DX
51
DI
DS
ES

call

IST'5

pop
pop
pop
pop
pop
pop
pop
pop

ES
DS
DI
81
DX

iret
servI_int5_isr

ex

BX
AX
endp

231421-72

1-78

Ap·235

IPCO/USR/CHUCK/CSRC/ASSV. ASH

s.rv __ int:il_isr

push
IODY
OlDY
mDY

AX.
DS.
ES.

pufth
pU5h

push
push
push
push

,..

Pl'DC

AX
BX
CX
DX
91
D1
DS
ES

push

UAP _DATA
AX
AX

c.11

]51'2_

pDp
pDP
PDP
pDp
pDp
pDp
PDP
pDp

ES

OS
D1
91
DX

ex

BX
AX

h,.t
... rv._int2_isl'

endp

•• r"e_intl_ 10 •

pl'DC

push

push
puah
push
push
push
push

far

AX
BX

ex

pUlh

DX
51
D1
DB
EB

mDY
mDY
mDV

AX. DLDJlATA
DS. AX
ES. AX

call

ISI'1

PDP
PDP
pDp
pDP
pDP
pDP
pDp
PDP

EB
DS
D1
91
DX

ex

BX
AX

u,.t

5erve_intl_isr

"ndp

en.bl,,_ p,.OI:

far

st1

231421-73

1-79

Ap·235

IPCO/UBR/CHUCK/CBRC/ABBV. AB'"
,..t

en.bl._ endp

proc

di •• ble_

fa,.

eli
nt
disablo_

init_intv_

endp

proc

push
push

DB
AX

,or
moy

AX.
DB.

J

fn

AX
AX

Jnte""upt t\lpe. fo1' the 186/81 CDMMpute,..

moy
moy
moy
moy
moY
moy
moy
moY
moy
moy
moY
moY
moy
,"oy
may
may

DB:IIID'rd ptr
DS: word ptr
DB: word ptr
DS:WDrd ptr
DS:wo1"'d ptr
DS: IIIDT'd ptr
DS:IIIDT'd ptr
DS:word ptr
DS:WDT'd ptr
DS:WD'I"d ptr
DS:\IIord ptr
DS:wol'd ptr
DS:ward ptr
DS: wo,.d ptr
DB: W01'd ptr
DS:word ptr

pap
pap
ret

AX
DS

init_in'tv_

BOh,
B2h.
B4h.
B6h.
BBh.
BAh.
BCh.
BEh.
90h.
92h.
94h.
96h.
9Bh.
9Ah.
9Ch.
9Eh.

off •• t •• rve_int_S:274
DO_CODE

•

offset •• "va_intl_is"

Int 0
Int 1

DO_CODE

offset s.'I"ve_int2_is,..

tnt 2

DO_CODE

offset •• rve_tnt_1s"
DO_CODE

•

off.et s.'I've_int_timeout
DO_CODE

off.et •• ,.ve_int5_is.,.
DO_CODE

Int 4

•

offset serve_into_isl'
DO_CODE
off •• t •• ,.ve_int7_i.,.
DO_CODE

lnt 3

lnt S
Int 6

•

int 7

endp

DO_CODE ends
nd

It.-gin, 6 .. : dld_d.t •. ... : st.e'k: stir top

231421-74

1-80

APPLICATION
NOTE

AP-236

November 1986

Implementing StarLAN with
the Intel 82588

ADIGOLBERT
DATA COMMUNICATIONS OPERATION

SHARAD GANDHI
FIELD APPLICATIONS-EUROPE

Order Number: 231422-003
1-81

inter

AP-236

1.0 INTRODUCTION
Personal computers have become the most prolific
workstation in the office, serving a wide range of needs
such as word processing, spreadsheets, and data bases.
The need to interconnect PCs in a local environment
has clearly emerged, for purposes such as the sharing of
file, print, and communication servers; downline loading of files and application programs; electronic mail;
etc. Proliferation of the PC makes it the workstation of,
choice for acCessing the corporate mainframe/s; this
function can be performed much more efficiently and
economically when clusters of PCs are already interconnected through Local Area Networks (LANs). According to market surveys, the installed base of PCs in
business environments reached about 10 million units
year-end '85, with only a small fraction connected via
LANs. The installed base is expected to double by
1990. There is clearly a great need for locally intercon'necting these machines; furthermore, end users expect
interconnectability across vendors. Thus, there is an urgent need for industry standards to promote cost effec, tive PC LANs.
A large number of proprietary PC LANs have become
available for the office environment over the past several years. Many of these suffer from high installed cost,
technical deficiencies, non-conformance to industry
standards, and general lack of industry backing. StarLAN, in Intel's opinion, is one of the few networks
which will emerge as a standard. It utilizes a proven
network access method, it is implemented with proven
VLSI components; it is cost effective, easily'installable
and reconfigurable; it is technically competent; and it
enjoys the backing of a large cross section of the industry which is collaborating to develop a standard (IEEE
802.3, type IBASE5).

1.1 StarLAN
StarLAN is a I Mb/s network based on the CSMA/
CD access method (Carrier Sense, Multiple Access
with Collision Detection). It works over standard,
unshielded, twisted pair telephone wiring. Typically,
the wiring connects each desk to a wiring closet in a
star topology (from which the IEEE Task Force working on the standard derived the name StarLAN in
1984). In fact, telephone and StarLAN wiring can coexist in the same twisted pair bundle connecting a desk to
the wiring closet. Abundant quantities of unused phone
wiring exist in most office environments, particularly in
the U.S. The StarLAN concept of wiring and networking concepts was originated by AT&T Information Systems.

tions needed for such networks. Besides inplementing
the standard CSMA/CD functions like framing, deferring, backing off and retrying on collisions, transmit-,
ting and receiving frames, it performs data encoding
and decoding in Manshester or NRZI format, carrier
sensing and collision detection, all up to a speed of 2
Mb/s (independent of the chosen encoding scheme).
These functions make it an optimum controller for a
StarLAN node. The 82588 has a very conventional microcomputer bus interface, easing the job of interfacing
it to any processor.

1.3 Organization of the Application
Note
This application note has two objectives. One is to describe StarLAN in practical terms to prospective implementers. The other is to illustrate designing with 82588,
particularly as related to StarLAN which is expected to
emerge as its largest application area.
Section' 2 of this Application Note describes the Star, LAN network, its basic components, collision detection, signal propagation and network parameters. Sections 3 and 4 describe the 82588 LAN controller and its
role in the StarLAN network. Section 5 goes into the
details of designing a StarLAN node for the IBM PC.
Section 6 describes the design of the HUB. Both these
designs have been implemented and operated in an actual StarLAN environment. Section 7 documents the
software used to drive the '82588. It gives the actual
procedures used to do operations like, configure, transmit and receive frames. It also shows how to use the
DMA controller and interrupt controller in the IBM
PC and goes into the details of doing I/O on the PC
using DOS calls. Appendix A shows oscilloscope traces
of the signals at various points in the network. Appendix B describes the multiple point extension (MPE) being considered by IEEE. Appendixes C and D talk
about advanced usages of the 82588; working with only
one DMA channel, and measuring network delays with
the 82588.

1.4 References
For additional information on the 82588, see the Intel
Microcommunications Handbook. StarLAN specification are currently available in draft standard form
through the IEEE 802.3 Working Group.

2.0StarLAN
StarLAN is a low cost 1 Mb/s networking solution
aimed at office automation applications. It uses a star

1.2 The 82588
The 82588 is a single-chip LAN controller designed for
CSMA/CD networks. It integrates in one chip all func1-82

AP-236

topology with the nodes connected in a point-to-point
fashion to a central HUB. HUBs can be connected in a
hierarchical fashion. Up to 5 levels are supported. The
maximum distance between a node and the adjacent
HUB or between two adjacent HUBs is 800 ft. (about
250 meters) for 24 gauge wire and 600 ft. (about 200
meters) for 26 gauge wire. Maximum node-to-node distance with one HUB is 0.5 km, hence IEEE 802.3 designation of type lBASE5. 1 stands for 1 Mb/s and
BASE for baseband. (StarLAN doesn't preclude the use
of more than 800 ft wiring provided 6.5 dB maximum
attenuation is met, and cable propagation delay is no
more than 4 bit times).

5) Off-the-shelf, Low cost RS-422, RS-485 drivers/receivers compatible with the StarLAN analog interface requirements.

2,1 5tarLAN Topology
StarLAN, as the name suggests, uses a star topology.
The nodes are at the extremities of a star and the central point is called a HUB. There can be more than one
HUB in a network. The HUBs are connected in a hierarchical fashion resembling an inverted tree, as shown
in Figure 1, where nodes are shown as PCs. The HUB
at the base (at level 3) of the tree is called the Header
Hub (HHUB) and others are called Intermediate HUBs
(IHUB). It will become apparent, later in this section,
that topologically, this entire network of nodes and
HUBs is equivalent to one where all the nodes are connected to a single HUB. Also StarLAN doesn't limit
the number of nodes or HUBS at any given level.

One of the most attractive features of StarLAN is that
it uses telephone grade twisted pair wire for the transmission medium. In fact, existing installed telephone
wiring can also be used for StarLAN. Telephone wiring
is very economical to buy and install. Although use of
telephone wiring is an obvious advantage, for small
clusters of nodes, it is possible to work around the use
of building wiring.

2.1.1 TELEPHONE NETWORK

Factors contributing to low cost are:
1) Use of telephone grade, unshielded, 24 or 26 gauge
twisted pair wire transmission media.
2) Installed base of redundant telephone wiring in most
buildings.
3) Buildings are 'designed for star topology wiring.
They have conduits leading to a central location.
4) Availability of low cost VLSI LAN controllers like
the 82588 for low cost applications and the 82586 for
high performance applications.

StarLAN is structured to run parallel to the telephone
network in a building. The telephone network has, in
fact, exactly the same star topology as StarLAN. Let us
now examine how the telephone system is typically laid
out in a building in the USA. Figure 2 shows how a
typical building is wired for telephones. 24 gauge
unshielded twisted pair wires emanate from a Wiring
Closet. The wires are in bundles of 25 or 50 pairs. The
bundle is called D inside wiring (DIW). The wires in
these cables end up at modular telephone jacks in the
wall. The telephone set is either connected directly to

HUB LEVEL 1

231422-2
'Maximum of 5 HUB levels.
'pes or DTEs can connect directly at any level.

Figure 1. StarLAN Topology

1-83

AP-236

the jack or through an extension cable. Each telephone
generally needs one twisted pair for voice and another
for auxilliary power. Thus, each modular jack has 2
twisted pairs (4 wires) connected to it. A 25 pair DIW
cable can thus be used for up to 12 telephone connections. In most buildings, not all pairs in the bundle are
used. Typically, a cable is used for only 4 to 8 telephone
connections. This practice is followed by telephone
companies because it is cheaper to install extra wires
initially, rather than retrofitting to expand the existing
number of connections. As a result, a lot of extra, unused wiring exists in a building. The stretch of cable
between the wiring closet and the telephone jack is typically less than 800 ft. (250 meters). In the wiring closet
the incoming wires from the telephones are routed to
another wiring closet, a P ABX or to the central office
through an interconnect matrix. Thus, the wiring closet
is. a concentration point in the telephone network.
There is also a redundancy of wires between the wiring
closets.

2.1.2 StarLAN AND THE TELEPHONE
NETWORK

StarLAN does not have to run on building wiring, but
the fact that it can significantly adds to its attractiveness. Figure 3 shows how StarLAN piggybacks on telephone wiring. Each node needs two twisted pair wires
to connect to the HUB. The unused wires in the 25 pair
DIW cables provide an electrical path to the wiring
closet, where the HUB is located. Note that the telephone and StarLAN are electrically isolated. They only
use the wires in the same bundle cable to connect to the
wiring closet. Within the wiring closet, StarLAN wires
connect to a HUB and telephone wires are routed to a
different path. Similar cable sharing can occur in connecting HUBs to one another. See Figure 4 for a typical
office wired for StarLAN throu~h telephone wiring.

231422-3

Figure 2. Telephone Wiring in a Building

WIRING CLOSET

800 f1

.........

" - - - BUNDLES or - - . /
.
25 - 50 PAIRS

~2 lWlSTED PAIRS

24 GAUGE. UNSHIELDED

231422-4
• StarLAN and telephones share the same bundle, but are electrically isolated.
'SlarLAN uses the unused wires in existing bundles.

Figure 3. Coexistence of Telephone and StarLAN
1-84

AP-236

WIRING CLOSET

WIRING CLOSET

ROOM

#1

ROOM

#2

ROOM

#3

WIRING CLOSET

TELEPHONE
WIRES TO PBX

WIRING CLOSET

231422-5

Figure 4. A Typical Office Using Telephone Wiring for StarLAN

1-85

inter

AP-236

2.1.3 StarLAN AND Ethernet
StarLAN and Ethernet are similar CSMAlCD networks. Since Ethernet has existed longer and is better
understood, a comparison of Ethernet with StarLAN is
worthwhile.
1. The data, rate of Ethernet is IOMb/s and that of StarLAN.is 1 Mb/s.
2. Ethernet uses a bus topology with each node connected to a coaxial cable bus \ via a 50 meter transceiver cable containing four shielded twisted pair
wires. StarLAN uses a star topology, with each node
connected to a central HUB by a point to point link
through two pairs of unshielded twisted pair wires.
3. Collision detection in Ethernet is done by the transceiver connected to the coaxial cable. Electrically, it
is done by sensing the energy level on the coax cable.
Collision detection in StarLAN is done in the HUB
by sensing activity on more than one input line connected to the HUB.

4. In Ethernet, the presence of collision is signalled by
the transceiver to the node by a special collision detect signal. In StarLAN, it is signalled by the HUB
using a special collision presence signal on the receive data line 'to the node.
5. Ethernet cable segments are interconnected using repeaters in a non-hierarchical fashion so that the distance between any, two nodes does not exceed 2.8
kilometers. In StarLAN, the maximum distance between any two nodes is 2.5 kilometers., This is
achieved by wiring a maximum of five levels of
HUBs in a hierarchical fashion ..

2.2 Basic StarLAN Components
A
1.
2.
3.

StarLAN network has three basic components:
StarLAN node interface
StarLAN HUB
Cable

ETHERNET

STAR LAN
231422-6

Figure 5. Ethernet and StarLAN Similarities

1-86

inter

AP-236

2.2.1 A StarLAN NODE INTERFACE

Figure 6 shows a typical StarLAN node interface. It
interfaces to a processor on the system side. The processor runs the networking software. The heart of the
node interface is the LAN controller which does the job
of receiving and transmitting the frames in adherence
to the IEEE 802.3 standard protocol. It maintains all
the timings-like the slot time, interframe spacing
etc.-required by the network. It performs the functions of framing, deferring, backing-off, collision detection which are necessary in a CSMA/CD network. It
also does Manchester encoding of data to be transmitted and clock separation-or decoding-of the Manchester encoded data that is received. These signals before going to the unshielded twist pair wire, may under- .
go pulse shaping (optional) pulse shaping basically
slows down the fall/rise times of the signal. The purpose of that is to diminish the effects of cross-talk and
radiation on adjacent pairs sharing the same bundle
(digital voice, Tl trunks, etc). The shaped signal is sent
on to the twisted pair wire through a pulse transformer
for DC isolation. The signals on the wire are thus differential, DC isolated from the node and almost sinusoidal (due to shaping and the capacitance of the wire).
NOTE:
Work done by the IEEE 802.3 committee has shown
that no slew rate control on the drivers is required.
Shaping by the transformer and the cable is sufficient
to avoid excessive EMI radiation and crosstalk.
The squelch circuit prevents idle line noise from affecting the' receiver circuits in the LAN controller. The
squelch circuit has a 600 mv threshold for that purpose.
Also as part of the squelch circuitry an envelope detector is implemented. Its purpose is to generate an envelope of the transitions of the RXD line. Its output serve

as a carrier sense signal. The differential signal from the
HUB is received using a zero-crossing RS-422 receiver.
Output of the receiver, qualified by the squelch 'circuit,
is fed to the RxD pin.of the LAN controller. The RxD
signal provides three kinds of information:
I) Normal received data, when receiving the frame.
2) Collision information in the form of the collision
presence signal from the HUB.
3) Carrier sense information, indicating the beginning
and the end of frame. This is useful during transmit
and receive operations.
2.2.2 StarLAN HUB

HUB is the point of concentration in StarLAN. All the
nodes transmit to the HUB and receive from the HUB.
Figure 7 shows an abstract representation of the HUB.
It has an upstream and a downstream signal processing
unit. The upstream unit has N signal inputs and 1 signal output. And the downstream unit has 1 input and
N output signals. The inputs to the upstream unit come
from the nodes or from the intermediate HUBs
(IHUBs) and its output goes to a higher level HUB.
The downstream unit is connected the other way
around; input from an upper level HUB and the outputs to nodes or lower level IHUBs. Physically each
input and output consist of one twisted pair wire carrying a differential signal. The downstream unit essentially just re-times the signal received at the input, and
sends it to all its outputs. The functions performed by
the upstream unit are:
1. Collision detection
2. Collision Presence signal generation
3. Signal Retiming
4. Jabber Function
5. Start of Idle protection timer

PULSE
TRANSFORMER
8 BIT BUS

< >
< >

TELEPHONE
JACK

PULSE
SHAPING
~----t (OPTIONAL)

82S88

CONTROL

RxD

SYS ClK

SQUELCH

+ '
ENABLE
CIRCUITS
231422-7

Figure 6. 82588 Based StarLAN Node
1-87

inter

AP·236

the HUB associated with this function and their operation .is described in section 6.

231422-8

Figure 7. A StarLAN HUB
co~li.sion detect~on in the HUB is done by sensing
activity on the Inputs. If there is activity (or transItions) on more than one input, it is assumed that more
than one node is transmitting. This is a collision. If a
collision is detected, a special signal called the Collision
Presence Signal is generated. This signal is generated
and sent out as long as activity is sensed on any of the
input lines. This signal is interpreted by every node as
an occurrence of collision. If there is activity only on
one input, that signal is re-timed--or cleaned up of any
accumulated jitter-and sent out. Figure 8 shows the
input to output relations of the HUB as a black box.

The
t?~

If a node transmits for too long the HUB exercises a
function to disable the node from interfering
with traffic from other nodes. There are two timers in

J~bber

IDLE
IDLE
IDLE

VALID
MANCHESTER

The last function implemented by the HUB is the start
of Idle prot~ction timer. During the end of reception,
the HUB Will see a long undershoot at its input port.
This undershoot is a consequence of the transformer
discharging accumulated charge during the 2 microseconds of high of the idle pattern. The HUB should implement a protection mechanism to avoid the undesirable effects of that undershoot.
Figure 9 shows a block diagram of the HUB. A switch
position determines whether the HUB is an IHUB or a
. HI:IUB (Header HUB). If the HUB is an IHUB, the
sWitch decouples the upstream and the downstream
units. HHUB is the highest level HUB; it has no place
to send its output signal, so it returns its output signal
(through the switch) to the outputs of the downstream
unit. There is one and only one HHUB in a StarLAN
network and it is always at the base of the tree. The
returned signal eventually reaches every node in the
network through the intermediate nodes (if any). StarLAN specifications do not put any restrictions on the
number of IHUBS at any level or on number of inputs
to any HUB. The number of inputs per HUB are typically 6 to 12 and is dictated by the typical size of clusters in a given networking environment.

COLLISION PRESENCE
IDLE
IDLE

VALID MANCHESTER

IDLE

VALID MANCHESTER
IDLE
VALID MANCHESTER

COLLISION PRESENCE
IDLE
IDLE

COLLISION
PRESENCE

COLLISION
PRESENCE

HUB
COLLISION
PRESENCE

VALID MANCHESTER

IDLE

231422-9

Figure 8. HUB as a Black Box

1-88

intJ

AP-236

TRANSMIT PAIR

#1

~II

~II
TRANSMIT PAIR

RECEIVE PAIR

'-3
'-3

+

TO HIGHER
LEVEL HUB

JABBER

+

#N

#

PROTECTION
TIMER

1

HHUB

IH~""B----I,--R_i_~_~A_INL_G KhJII
...

11

E

11

RECEIVE PAIR

#

N

231422-10

Figure 9. StarLAN HUB Block Diagram

Although it is outside the scope of the IEEE 802.3
IBASE5 standard, there is considerable interest in using fiber optics and coaxial cable for node to HUB or
HUB to HUB links especially in noisy and factory environments. Both these types of cables are particularly
suited for point-to-point connections. Even mixing of
different types of cables is possible (this kind of environments are not precluded).

2.2.3 StarLAN CABLE

Unshielded telephone grade twisted pair wires are used
to connect a node to a HUB or to connect two HUBs.
This is one of the cheapest types of wire and an important factor in bringing down the cost of StarLAN.
Although the 24 gauge wire is used for long stretches,
the actual connection between the node and the telephone jack in the wall is done using extension cable,
just like connecting a telephone to a jack. For very
short Star LAN configurations, where all the nodes and
the HUB are in the same room, the extension cable
with plugs at both ends may itself be sufficient for all
the wiring. (Extension cables must be of the twisted
pair kind, no flat cables are allowed).

NOTE:
StarLAN IEEE 802.3 !BASES draft calls for a maximum attenuation of 6.5 dB between the transmitter
and the corresponding receiver at all frequencies between 500 KHz to 1 MHz. Also the maximum allowed cable propagation delay is 4 microseconds.

2.3 Framing

The telephone twisted pair wire of 24 gauge has the
following characteristics:
Attenuation

: 42.55 db/mile

@

Figure 10 shows the format of a 802.3 frame. The beginning of the frame is marked by the carrier going
active and the end marked by carrier going inactive.
The preamble has a 56 bit sequence of 101010 . . . .
ending in a O. This is followed by 8 bits of start of frame
delimiter (sfd) - 10101011. These bits are transmitted
with the MSB (leftmost bit) transmitted first. Source
and destination fields are 6 bytes long. The first byte is
the least significant byte. These fields are transmitted
with LSB first. The length field is 2 bytes long and gives
the length of data in the Information field. The entire
information field is a minimum of 46 bytes and a maximum of 1500 bytes. If the data content of the Informa-

1 MHz

DC Resistance : 823.69 fl./mile
Inductance
Capacitance
Impedance

0.84 mH/mile
0.1 fLF/mile
92.6D, -4 degrees

@

1 MHz

Experiments have shown that the sharing of the telephone cable with other voice and data services does not
cause any mutual harm due to cross-talk and radiation,
provided every service meets the FCC limits.
1-89

AP-236

tion field is less than 46. padding bytes are used to
make the field 46 bytes long. The Length field indicates

The frames can be directed to a specific node (LSB of
address must be 0). to a group of nodes (multicast or
grnnp-LSB of address must be I) or all nodes (broadcast-alI address bits must be 1).

hnw mlll'h rp"l cl"t" i. in thp TnfnrmMinn fj,,1cl. Th" l"st

32 bits of the frame is the Frame Check Sequence
(FCS) and contains the CRC for the frame. The CRC is
calculated from the beginning of the destination address to the end of the Information field. The generating polynomial (Autodin II) used for CRC is: .

2.4 Signal Propagation and Collision
Figure 11 will be used to illustrate three typical situations in a StarLAN with two IHUBs and one HHUB.
Nodes A and B are connected to HUBI. nodes C and D
to HUB2 and node E to HUB3.

+ X26 + X23 + X22 + XI6 + XI2 + Xii +
xlO + XB + X7 + X5 + X4 + X2 + X + 1

X32

No need for Figure N.

CARRIER ON

+

7

1

6

6

2

t.4AX=1500
t.4IN = 46

CARRIER OFF
I
4 ..

I PREAt.4BLE I SFD I DA I SA I LEN IINFORt.4ATION I FCS
,.

SFD ~ Start of Frame Delimiter
DA ~ Destination Address .
SA ~ Source Address

LEN

~

I

FRAt.4E LENGTH ~
t.4AX=1518
t.4IN=64

Length

FCS ~ Frame Check Sequence
All numbers indicate field length in octets.

Figure 10. Framing

1-90

231422-11

inter

Ap·236

231422-12

Situation # 1. A Transmitting

231422-13

Situation # 2. A & B Transmitting

231422-14

Situation # 3. A, B & C Transmitting
HUB1, HUB2 are IHUBs
HUB3 is the HHUB
Fa, Fb, Fe-Frames from nodes A, B & C
Fx-Collision Presence Signal

Figure 11. Signal Propagation and Collisions

1-91

inter

AP-236

Backoff method ........ Truncated binary exponential
Encoding ..... .' ...................... Manchester

2.4.1 Situation # 1
WhpnpVPT nnop A tnm.mit. ~ fr~me Fa, it will reach
,HUB 1. If node B is silent, there is no collision. HUB I
will send Fa to HUB3 after re-timing the signal. If
nodes C, D and E are also silent, there is no collision at
HUB2 or HUB3. Since HUB3 is the HHUB, it sends
the frame Fa to HUBI, HUB2 and to node E after retiming. HUBI and HUB2 send the frame Fa to nodes
A, Band C, D. Thus, Fa reaches all the nodes on the
network including the originator node A. If the signal
received by node A is a valid Manchester signal and not
the Collision Presence Signal (CPS) for the entire duration of the slot time, then the node A assumes that it
was a successful transmission.

2.4.2 Situation # 2
If both nodes A and B were to transmit, HUBI will
detect it as a collision and will send signal Fx (the Collision Presence Signal) to the HUB3-Note that HUBI
does not send Fx to nodes A and B yet. HUB 3 receives
a signal from HUB I but nothing from node E or
HUB2, thus it does not detect the situation as. a collision and simply re-times the signal Fx and sends it to
node E, HUB2 and HUBI. Fx ultimately reach all the
nodes. Nodes A and B detect this signal as CPS and
call it a collision.

Clock tolerance ................ ±0.01 % (100 ppm)
Maximum jitter per segment .............. ± 62.5 ns

3.0 LAN CONTROLJ-ER FOR StarLAN
One of the attractive features of StarLAN is the availability of the 82588, a VLSI LAN controller, designed
to meet the needs of a StarLAN node. The main ·requirements of a StarLAN node controller are:
1. IEEE 802.3 compatible CSMA/CD controller.
2. Configurable to StarLAN network and system parameters.
3. Generation of all necessary clocks and timings.
4. Manchester data encoding and decoding.
5. Detection of the Collision Presence Signal.
6. Carrier Sensing.
7. Squelch or bad signal filtering.
8., Fast and easy interface to the processor.
82588 performs all these functions in silicon, providing
a minimal hardware interface between the system processor and the StarLAN physical link. It also reduces
the software needed to run the node, since a lot of functions, like deferring, back off, counting the number of
collisions etc., are done in silicon.

2.4.3 Situation # 3
In addition to nodes A and B, if node C were also to
transmit, the situation at HUBI will be the same as in
situation # 2. HUB2 will propagate Fc from C towards
HUB3. HUB3 now sees two of its inputs active and
hence generates its own Fx signal and sends it towards
each node.
These situations should also illustrate the point made
earlier in the chapter that, the StarLAN network, with
nodes connected to multiple HUBs is, logically, equivalent to all the nodes connected to a single HUB (Yet
there are some differences between stations connected
at different HUB levels, those are due to different delays to the header hub HHUB).

3.1 IEEE 802.3 Compatibility
The CSMA/CD control unit on the 82588 performs the
functions of deferring, maintaining the Interframe
Space (IFS) timing, reacting to collision by generating a
jam pattern, calculating the back-off time based on the
number of collisions and a random number, decoding
the address of the incoming frame, discarding a frame
that is too short, etc. All these are performed by the
82588 in accordance to the IEEE 802.3 standards. For
inter-operability of different nodes on the Star LAN network it is very important to have the controllers strictly
adhere to the sam\! standards.

3.2 Configurability of the 82588
2.5 StarLAN System and Network
Parameters
Preamble length (incl. sfd) .................. 64 bits
Address length .................. : ......... 6 bytes
FCS length CRC (Autodin II) ............... 32 bits
Maximum frame length ................. 1518 bytes
Minimum frame length .................... 64 bytes
Slot time ................ " .......... 512 bit times
Interframe spacing ............. ',' ...... 96 bit times
Minimum jam timing .................. 32 bit times
Maximum number of collisions .................. 16
Backoff limit ................................. 10

Almost all the networking parameters are programmable over a wide range. This means that the StarLAN
parameters form a subset of the total potential of the
82588. This is a major advantage for networks whose
'standards are being defined and are in a flux. It is also
an advantage when carrying over the experience gained
with the component in one network to other applications, with differing parameters (leveraging the design).
The 82588 is initialized or' configured to its working
environment by the CONFIGURE command. After
the execution of this command, the 82588 knows its
system and net~ork parameters. A configure block in
1-92

Ap·236

memory is loaded into the 82588 by DMA. This block
contains all the parameters to be programmed as shown
in Figure 12. Following is a partial list of the parameters with the programmable range and the Star LAN
value:
StarLAN
Parameter
Range
Value
Preamble length 2,4, 8, 16 bytes
8
Address length o to 6 bytes
6
CRCtype
16,32 bit
32
Minimum frame
length
6 to 255 bytes
64
Interframe
12 to 255 bit times
spacing
96
Slot time
1 to 2047 bit times
512
Number of
retries
oto 15
15

StarLAN
Value

Parameter

Range

Data encoding

NRZI, Man.,
Diff. Man.
Code viol.,
Bitcomp.

Collision
detection

Manch.
Code Viol.

Beside these, there an: many other options available,
which mayor may not apply to StarLAN:
Data sampling rate of 8 or 16
Operating in Promiscuous mode
Reception of Broadcast frames
Internal loopback operation
External loopback operation
Transmit without CRC
HDLC Framing

BIT
BYTE

7

o

2

6
I

I

I
I

_1
I

I BYTE

SERIAL
MODE

CHNG

4

5

_ I BYTE
SMPLG
RATE

3

COU~T (L.S.B)
i

J

I
I

OSC
RANGE

4
5

BOF
METD

EXP

PREAM LEN
I
I
PRIO

I

I

I~TER

6
I
I

I
I

I
I

I

7

9

PAD

10

COT
SRC

BIT
STUFF

11

I

MINIMUM

I

I

I

I

I

I

I

I

I
ADD lEN

I

I

I

I
LIN PRIO

I

SPACING
I
I

I

I
I

I
I

I
I

MAN
/NRZ·

CRS
SRC
FRAME

I

(~)

BC
DIS

PRM

CRSF

lENGTH

I

I

SllOT TIME

TON
NCRS

CDTF

I

I
I

I

NCRC
INS

I

I

I

CDBBC

I

I

I

OIF.MAN
/MAN

I FRAME
I
I
I I
SLOT TIME (l)

CRC16

I

lENGT~
NO SRC
ADD INS

RETRY NUMBER

8

i

FIFO ILiMIT

I
I

I

I

i

COU~T (M.S.B) I

I

INT
LP.BCK

I

I

i

BUFFER
I
EXT
LP.BCK

o

2

3

I

I
I

I
I

I

I

CONFIG PARAMETER FORMAT
231422-15

Figure 12. Configuration Block

1-93

AP-236

time, Back off time, Number of collisions, Minimum
frame length, etc. These timers are started and stopped

3.3 Clocks and Timers

e~!0:ne.ti~?-!!y 1)y th~ R'~RR.

H::4UiH;:~ LWU ",l\.n...~~, uji~ fur thi: upcrutiGu. of
the system interface and another for the serial side.
, Both clocks are totally asynchronous to each other.
This permits transmitting and receiving frames at data
rates that are virtually independent of the speed at
which the system interface operates.

The 02.300

3.4 Manchester Data Encoding and
Decoding
In StarLAN the data transmitted by the node must be
encoded in Manchester format. The node should also
be able to decode Manchester encoded data when receiving a frame--a process also known as clock recovery. The 82588 does the encoding and decoding of data
bits on chip for data rates up to 2 Mb/s.

The serial clock can be generated on chip using just an
external crystal of a value 8 or 16 times the desired bit
rate. An external clock may also be used.
The 82588 has a set of timers to maintain various timings necessary to run the CSMA/CD control unit.
These are timings for the Slot time, Interframe spacing

DATA

I

1

I0 I

1

Besides Manchester, the 82588 can also do encoding
and decoding in NRZI and Differential Manchester
formats. Figure 13 shows samples of encoding in

I

1

I0 I

1

I

0

I0 I0 I

1

I

NRZ
NRZI
MANCHESTER
DIFFERENTIAL
MANCHESTER

Encoding
Method

231422-16

Mid Bit Cell
Transitions

Bit Cell Boundary
Transitions

NRZ

Do not exist.

Identical to original data.

NRZI

Do not exist.

Exist only if original data
bit equals o.
Dependent on present
encoded signal level:
to 0 if 1
to 1 if 0

Manchester

Exist for every bit of
the original data:
from 0 to 1 for 1
from 1 to 0 for 0

Exist for consequent equal
bits of original data:
from 1 to 0 for 1 1
from 0 to 1 for 0 0

Differential
Manchester

Exist for every bit of
the original data.
Dependent on present
Encoded signal level:
to 0 if 1
t01 if 0

Exist only if original data
bit equals o.
Dependent on present
Encoded signal level:
to 0 if 1
to 1 if 0

Figure 13. 82588 Data Encoding Rules

inter

AP-236

these three formats. The main advantage of NRZI over
the other two is that NRZI requires half the channel
bimdwidth. for any given data rate. On the other hand.
since the NRZI signal does not have as many transitions as the other two. clock recovery from it is more
difficult. The main advantage of Differential Manchester over straight Manchester is that for a signal that is
differentially driven (as in RS 422). crossing of the two
wires carrying the data does not change the data received at the receiver. In other words. NRZI and Differential Manchester encoding methods are polarity insensitive (Even though NRZI. Differential Manchester
are polarity insensitive. the 82588 expects a high level
in the RXD line to detect carrier inactive at the end of
frames).

periodic intervals. When the 82588 decodes this signal.
it fails to see mid-cell transitions repeatedly at intervals
of 2.5 bit times and hence calls it a code violation. The
edges of CPS are marked for illustration as a. b. c.
d •... 1. Let us see how the 82588 interprets the signal if
it starts calling the edge 'a' as the mid-cell transition for
'I'. Then edge at 'b' is '0'. Now the 82588 expects to see
an edge at ••• but since there is none. it is a Manchester
code violation. The edge that eventually does occur at
'd' is then used to re-synchronize and. since it is a falling edge. it is taken as a mid-cell transition for '0'. The
edge at 'e' is for a 'I' and then again there is no edge at
•••. This goes on. with the 82588 flagging code violation
and re-synchronizing again every 2.5 bit times. When a
transmitting node sees this CPS signal being returned
by the HUB (instead of a valid Manchester signal it
transmitted). it assumes that a collision occurred. The
82588 has two built-in mechanisms to detect collisions.
These mechanisms are very general and can be used for
a very broad class of applications to detect collisions in
a CSMA/CD network. Using these mechanisms. the
82588 can detect collisions (two or more nodes transmitting simultaneously) by just receiving the collided
signal during transmission. even if there was no HUB
generating the CPS signal.

3.5 Detection of the Collision
Presence Signal
In a StarLAN network. HUB informs the nodes that a
collision has occurred by sending the Collision Presence Signal (CPS) to the nodes. The CPS signal is a
special signal which contains violations in Manchester
encoding. Figure 14 shows the CPS signal. It has a 5 ms
period. looking very much like a valid Manchester signal except for missing transitions (or violations) at

10 1

ENCODING

1 01

K

1

J

10 1

CPS

abc

EDGES:

d

e f

9

k I

h

! - 5 . us PERIOD-I

I 2t I t i t = 0.5 .us
• MISSING MID-CELL TRANSITION

82588
DECODING

1

0

.rt.r1.
abc

d

o

1

1..JL..1'
d

e f

9

1

0

.rt.r1.
J

kim
O·

1

1..JL..1'
J

kim

Figure 14.82588 Decoding the Collision Presence Signal

1-95

231422-17

Ap·236

Collision also if:
RxD stays low for 25 samples or more
A mid cell transition is missing

3.5.1 COLLISION DETECTION BY CODE
VIOLATION

If during transmission, the 82588 sees a violation in the
"encoding (Manchester, NRZI or Differential Manchester) used, then it calls it a collision by aborting the
transmission and transmitting a 32 bit jam pattern. The
algorithm used to detect collisions, and to do the data
decoding, is based on finding the number of sampling
clocks between an edge to the next one. Suppose an
edge occurred at time 0, the sampling instant of the
next edge determines whether it was a collision (C), a
long pulse (L)-with a nominal width of 1 bit time-, or
a short pulse (S)-nominal width of half a bit time. The
following two charts show the decoding and collision
detection algorithm for sampling rates of 8 and 16
when using Manchester encoding. The numbers at the
bottom of the line indicate sampling instances after the
occurrence of the last edge (at 0). The alphabets on the
top show what would be inferred by the 82588 if the
next edge were to be there.

Sampling rate = 8 (clock is 8x bit rate)

C C S S S L L L L L C C

I I I I I I I I I I I I

o

23456"78910111213

Collision also if:
RxD stays low for 13 samples or more
A mid cell transition is missing
Sampling rate = 16 (clock is 16x bit rate)

CCCCCSSSSSCLLLLLLLLLCCCC
111111111111111111111111111

o

2

4

6

8

A single instance of code violation can qualify as collision. The 82588 has a parameter called collision detect
filter (CDT Filter) that can be configured from 0 to 7.
This parameter determines for how many bit times the
violation must remain active to be flagged as a collision:
For StarLAN CDT Filter must be configured to 0that is disabled.
3.5.2 COLLISION DETECTION BY SIGNATURE
(OR BIT) COMPARISON
"

This method of collision detection compares a signature
ofthe transmitted data with that of the data received on
the RxD pin while transmitting. Figure 15 shows a
block diagram of the logic. As the frame is transmitted
it flows through the CRC generation logic. A timer,
called the Tx slot timer, is started at the same time that
the CRC generation starts. When the count in the timer
reaches the slot time value, the current value of the
CRC generator is latched in as the" transmit signature.
As the frame is returned back (through the HUB) it
flows through the CRC checker. Another timer-Rx
slot timer-is started at the same time as the CRC
checker starts checking. When this timer reaches the
slot time value, the current value of the CRC checker is
latched in as the receive signature. If the recdved signature matches the transmitted one, then it is assumed
that there was no collision. Whereas, if the signatures
do not match, a collision is assumed to have occurred.

10 12 14 16 18 20 22 24 26

TRANSMITTED
FRAME

TX CRC

TRANSMIT CHANNEL

!.
Tx SLOT
TIMER

TX SIGNATURE
LATCH

+
Rx SLOT
TIMER

COMPARE·

RX SIGNATURE
LATCH

f
RECEIVED
FRAME

RX CRC

RE CEIVE CHANNEL

=

• MATCH NO COLLISION
NO MATCH COLLISION

=

Figure 15. Collision Detection by Signature Comparison
1-96

231422-18

AP-236

b) Half a slot time + 16 bit times elapse and the opening flag (sfd) is not detected.
c) Carrier sense goes inactive after an opening flag is
received with transmitter still active.

Note that, even if the collision were to occur in the first
few bits of the frame, a slot time must elapse before it is
detected. In. the code violation method, collision is detected within a few bit times. However, since the signature method compares the signatures, which are characteristic of the frame being transmitted, it is more robust. The code violation method can be fooled by returning a signal to the 82588 which is not the same as
the transmitted signal but is a valid Manchester signal-like a I MHz signal. Both methods can be used
simultaneously giving a combination of speed and robustness.

These mechanisms add a further robustness to the collision detection mechanism of the 82588. It is also possible to OR an externally generated collision detect signal
to the internally generated condition by bit comparison
(see Figure 17).

3.6 Carrier Sensing

NOTE:
In order to reliably detect a collision using the collision by bit comparison mode, the transmitter must
still be transmitting up to the point where the receiver
has seen enough bits to complete its signature. Otherwise, the transmitter may be done before the RX signature is completed resulting in an undetected collision. A sufficient condition to avoid this situation is to
transmit frames with a minimum length of 1.5 • slottime (see Figure 16).

A StarLAN network is considered to be busy if there
are transitions on the cable. Carrier is supposed to be
active if there are transitions. Every node controller
needs to know when the carrier is active and when not.
This is done by the carrier sensing circuitry. On the
82588 this circuit is on chip. It looks at the RxD (receive data) pin and if there are transitions, it turns on
an internal carrier sense signal. It turns off the carrier
sense signal ifRxD remains in idle (high) state for 13/8
bit times. This carrier sense information is used to mark
the start of the interframe space time and the back off
time. The 82588 also defers transmission when the carrier sense is active.

3.5.3 ADDITIONAL COLLISION DETECTION
MECHANISM

In addition to the collision detection mechanisms described in the preceding sections, the 82588 also flags
collision when after starting a transmission any of the
following conditions become valid:
a) Half a slot time elapses and the carrier sense of
82588 is not active.

When operating in the NRZI encoded mode, carrier
sense is turned off if RxD pin is in the idle state for 8 bit
times or more (see Figure 18).

82588

PD

TX

HEADEND
PD

RX

CONDITION FOR RELIABLE CDBBC
TLMIN_FRAMCLENGTH

> SLOLTIME+ 2*PD

t SLOLTIME ~ 2*PD

231422-75

Figure 16. Limitation of CDeeC Mechanism

1-97

inter

Ap·236

COLLISION DETECTION BY BIT COMPARISON (CDBBC)
(CONrIGURE BYTE B, BIT 3)
COLLISION DETECTION SOURCE (INTERNAL, EXTERNAL)
(CONrIGURE BYTE 10, BIT 7)

231422-76

Figure 17. Mode 0, Collision Detection

3.7 Squelching the Input
Squelch circuit is used to filter idle noise on the receiver
input. Basically two types of squelch may be used: Voltage and time. Voltage squelch is done to filter out signals whose strength is below a defined voltage threshold (0.6 volts for StarLAN). It prevents idle line noise
from disturbing the receive circuits on the controller.
The voltage squelch circuit is placed right after the receiving pulse transformer. It enables the input to the
RxD pin of the 82588 only when the signal strength is
above the threshold.

If the signal received has the proper level but not the
proper timing, it should not bother the receiver. This is'
accomplished by the time squelch circuit on the 82588.
Time squelching is essential to weed out spikes, glitches
and bad signal especially at the beginning of a frame.
The 82588 does not tum on its carrier sense (or receive
enable) signal until it receives three consecutive edges,
each separated by time periods greater than the fast
time clock high time but less than 13/8 bit-times as
shown in Figure 18.

MANCHESTER
DATALFu-

CARRIER

b

--------~

I

I

I.

--+-E-D~-E-S-j.J

.'---1

13/BBTxB
25/16BTx 16

-----u--

DATALFu-

CARRIER

b

HI~H. :r .1

I

I

--+-E-D~-E-S-j...l

1

OR 1.1- - -

231422-77

Figure 18. Carrier Sensing

1-98

intJ

AP-236

shows that it has an 8 bit data bus, read, write, chip
select, interrupt and reset pins going to the processor
bus. It also needs an external DMA controller for data
transfer. A system clock of up to 8 MHz is needed. The
read and write access times of the 82588 are very
short-95 ns-as shown by Figure 20. This further facilitates interfacing the controller to almost any processor.

The carrier sense activation can be programmed for a
further delay by up to 7 bit times by a configuration
parameter called carrier sense filter.

3.8 System Bus Interface
The 82588 has a conventional bus interface making it
very easy to interface to any processor bus. Figure 19

SE~IAl

CLOCK
X2/RxC

Xl/TxC

RTS

RESET - - +

00-7
STANDARD
BUS
INTERFACE

R5

JI--I\

+ - - CTS
Tx 0

\r-v"

WR

SERIAL
INTERFACE

82588

cs

28 PIN
PLASTIC/CERAMIC

INT

+--RxD
TClK

DRQO
DMA [ DACKO--+
INTERFACE DRQl
DACKI

(MODE 0)

CRS} CSMA/CD
INTERFACE
COT

t

ClK

SYSTEM CLOCK

231422-20

Figure 19. Chip Interface

-

80n.
(MIN)

.

95n •

I

(MIN)

55n.(MAX)

DATA

-75ns(MIN)

\

.

95n •
(MIN)

-on'

ll

(MIN)
DATA

231422-21

Figure 20. Access Times

1-99

inter

AP-236

The 82588 has over 50 bytes of registers, and most are
accessed only indirectly. Figure 21 shows the register
access mechanism of the 82588. It has one I/O port and
.2 uIviA cilannei pons. Tilese are tile windows into the
82588 for the CPU and the DMA controller. An external CPU can write into the Command register and read
from the Status registers using I/O instructions and
asserting chip select and write or read lines. Although
there is just one I/O port and 4 status registers, they
can be read out in a round robin fashion through the
same port as shown in Figure 22. Other registers like
the Configuration, Individual Address registers can be

accessed only through DMA. All the internal registers
can be dumped into memory by DMA using the Dump
command. The execution of some of the commands is
oescrioeo in section 4. :See the !s~:)1S!s Keterence Manual
for details on these commands.

3.9 .Debug and Diagnostic Aids
Besides the standard functions that can be used directly
for StarLAN, the 82588 offers many debug and diag-

82588 REGISTER SET

~

_-II---f~--I---"L-.~--

I

t

COMMAND

STATUS

I

~

WRITE ONLY

READ ONLY

CONFIGURATION
IA
MULTICAST

READ
&

WRITE

Tx CRC
Rx CRC

IMPLICIT REGISTERS
(OVER 50 BYTES)
231422-22

Figure 21. Register Access

1-100

AP·236

4 Status registers are accessed through one read port
POINTER

L

o:J

STATUS 0

1-----1
STATUS 1

--+ I READ PORT

STATUS 2
STATUS 3

231422-23

The pointer can be changed using a command or can be automatically incremented.

READ_STATUS_588: PROCEDURE;

COMMAND 15 *f
RELEASE POINTER, INITIAL = 00
f*

OUTPUT (CS_588) = 15;
STATUS_588(0)=INPUT (CS_588)
STATUS_588(1)=INPUT (CS_588)
STATUS_588(2)=INPUT (CS_588);
STATUS_588(3)=INPUT (CS_588);
RETURN
END READ_STATUS_588;

f*

of

f* REFRESH STATUS REGISTER IMAGE *f
/* . IN MEMORY.

READING 4 STATUS REGISTERS
Figure 22. Reading the Status Register

± 62.5 ns at 1 Mbs for both 8X, 16X Manchester encoded data.

nostics functions. The DIAGNOSE command of the
82588 does a self-test of most of the counters and timers
in the 82588 serial unit. Using the DUMP command,
all the internal registers of the 82588· can be dumped
into the memory. The TDR command does Time Domain Reflectometery on the n.etwork. The 82588 has
two loopback modes of operation. In the internal loopback mode, the TXD line is internally connected to the
RXD one. No data appears outside the chip, and the
82588 is isolated from the link. This mode enables
checking of the receive and transmit machines without
link interference. In the external loopback mode, the
82588 becomes a full duplex device, being able to receive its own transmitted frames. In this mode data
goes through the link and all CSMA/CD mechanisms
are involved.

Jitter ~ ± variation of an edge from its nominal position.
Jitter can occur on every edge.

I dW I dW I

r:+= :

______ ____
:._._L
=F-:

___ ________ __ •
~

~.

~

1-1.- - - W - - - - - - I ,1

231422-78
x8

x16

± V'6

±1/16

NRZI
(Code Violations Enabled)

±1/16BT

±3/32 BT

NRZI
(Code Violations Disabled)

±3/16 BT

±3/16 BT

Manchester

3.10 Jitter Performance
When the 82588 receives a frame from the HUB, the
signal has jitter. Jitter is the shifting of the edges of the
signal from their nominal position due to the transmission over a length of cable. Many factors like, intersymbol interference (pulses of different widths have different delays through the transmission media), rise and
fall times of drivers and receivers, cross talk etc., contribute to the jitter. StarLAN specifies a maximum jitter of ± 62.5 ns whenever the signal goes from a
NODE/HUB or HUB/HiJB. Figure 23 shows that the
jitter tolerance of the 82588 is exactly the required

I dW I dW I

Figure 23. 82588 Jitter Performance

4.0 THE 82588
This chapter describes the basic 82588 operations.
Please refer to the 82588 reference manual in Intel Microcommunications Handbook for a detailed description. Basic operations like transmitting a frame, receiving a frame, configuring the 82588 and dumping the
register contents are discussed here to give a feel for
how the 82588 works.

1-101

inter
4~1

AP-236

status registers to fmd out if the transmission was successful. If a collision occurs during transmissiQn, the
82588 aborts transmission and generates the jam sequence, as required by ,IEEE 802.3, and informs the
CPU through interrupt and the status registers. It also
starts the back-off algorithm.

Transmit and Retransmit
Operations

To transmit a frame, the CPU prepares a block in the
memory called the transmit data block. As shown in
Figure 24, this block starts with a byte count field, indicating how long the rest of the block is. The destination
address field contains the node address of the destination. The rest of the block contains the information or
the data field of the frame. The CPU also programs the
DMA controller with the start address of the transmit
data block. The DMA byte count must be equal to or
greater than the block length. The 82588 is then issued
a TRANSMIT command-an OUT instruction to the
command port of the 82588. The 82588 starts generating DMA requests to read in the transmit data block by
DMA. It also determines whether and how long it must
defer on the link and after that, it starts transmitting
the preamble. The 82588 constructs the frame on the
fly. It takes the destination address from the memory,
source address from its own individual address memory
(previously programmed), data field from the memory
, and the CRC, is generated on chip, at the end of the
frame.

To re-attempt transmission, the CPU must reinitialize
the DMA controller 7to the start of the transmit data
block and issue a RETRANSMIT command to the
82588. When the 82588 receives the retransmit command and the back-off timer has expired, it transmits
.again. Interrupt and the status register contents again
indicate the success or failure of the (re)transmit attempt.
.
The main difference between transmit and retransmit
commands is that retransmit does not clear the internal
count for the number of collisions occurred, whereas
transmit does. Moreoever, retransmit takes effect only
when the back-off timer has expired.

. 4.2 Configuring the 82588
To initialize the 82588 and program its network and
system parameters, a configure operation is performed.
It is very similar to the transmit operation. Instead of a
transmit data block as in transmit command, a configure data block-shown in Figure 12-is prepared by
the CPU in the memory. The first two bytes of the
block specify the length of the rest of the block, which
specify the network and system parameters for the
82588. The DMAcontroller is then programmed by
the CPU to the beginning of this block and a CONFIGURE command is issued to the 82588. The 82588 reads
in the parameters by DMA and loads the parameters in
the on-chip registers.

I. Prepare Transmit Data-Block in Memory
2. Program DMA Controller
3. Issue Transmit Command on the Desired
Channel
BYTE
COUNT
DESTIN.
ADDRESS

INFORMATION

U

Similarly, for programming the INDIVIDUAL ADDRESS and MULTICAST ADDRESSes, the DMA
controller is used to load the 82588 registers. '

231422-25

Transmit Data Block

4.3 Frame Reception

4. Interrupt is received on completion of command or if the command was aborted or
there was a collision. The status bytes 1 and
2 indicate the Jesult of the operation.
6
TX
'OEr

COll

5

HRT MAX
BEAT COll
TX
OK

4

2

o
STAnJS 1

NUM. or COlliSIONS

I lOST I lOST IUNDER
CRS
CTS RUN STAnJS 2

231422-26

TransmIt & Retransmit Results Format
Figure 24. Transmit Operation

At the conclusion of transmission the '82588 ,generates
an interrupt to the CPU. The CPU can then read the

Before enabling the 82588 for reception the CPU must
make a buffer available for the frame to be received.
The CPU must program the DMA controller with the
starting address of the buffer and then issue the lULENABLE command to the 82588. When a frame arrives at the RxD pin of the 82588, it starts being received. Only if the address in the destination address
matches either the Individual address, Multicast address or if it is a broadcast address, is the frame deposited into memory by the 82588 using DMA. The format
of storage in the memory is shown in Figure 25. At the
end, a two byte field is attached which shows the status
of the received frame. If CRC, alignment or overrun
errors are encountered, they are reported. An inter-

1-102

inter

AP-236

RECEIVED FRAME

1. Prepare a Buffer for Reception

2. Program DMA Controller
3. Issue Receiver Enable Command
When a frame is received, it is deposited in the
memory. Receive status bytes (2) are appended to
the frame in the memory, byte count written in the
status registers 1, 2, and an interrupt is generated.
RECEIVE
STATUS

SRT
FRM

DESTIN.
ADDRESS

SOURCE
ADDRESS

NO
EOF
RCV
O.K.

CRC
ERR

ALG
ERR

STATUS REG. 1
STATUS REG. 2

INFORMATION

OVER
RUN

~

BYTE
COUNT

A

RECEIVE
STATUS
./

231422-27

Figure 25. Receive Operation (Single Buffer)

rupt from 82588 occurs when all the bytes have been
transferred to the memory. This informs the CPU that
a new frame has been received.
If the received frame has errors, the CPU must recover
(or re-use) the buffer. Note that the entire frame is deposited into one buffer. The 82588 when NOT configured for the external loopback mode, will detect collisions (code violations) during receptions. If a collision
is detected, the reception is aborted and status updated.
CPU is then informed by an interrupt (if the collided
frame fragment is shorter than the address length, no
reception will be started), and no interrupt will happen.

4.3.1 Multiple Buffer Frame Reception
It is also possible to receive a frame into a number of
fixed size buffers. This is particularly economical if the
received frames vary widely in size. If the single buffer
scheme were used as described above, the buffer required would have to be bigger than the longest expected frame and would be very wasteful for very short
(typically acknowledge or control) frames. The multiple buffer reception is illustrated in Figure 26. It uses
two DMA channels for reception.

@BUFFER 1
@BUFFER 2
@BUFFER 3

·
·
··

@BUFFER N

Buffer
Pointer
Table
(Managed by CPU)

231422-28

Figure 26. Multiple Buffer Reception

1-103

intJ

AP-236

As in single buffer reception, the one channel, say channel 0, of the DMA controller is programmed to the
start of buffer I, and the R25RR i~ p.n~hlprl fnr rprP!'tlr'!!
with the chaining bit set. As soon as the first byte is
read out of the 82588 by the DMA controller and written into the first location of buffer 1, the 82588 generates an interrupt, saying that it is filling up its last available buffer and one more buffer must be allocated. The
filling up of the buffer 1 continues. The CPU responds
to the interrupt by programming the other DMA channel--channel I-with the start address of the second
buffer and issuing an ASSIGN ALTERNATE buffer
command with an INTACK (interrupt acknowledge).
This informs the 82588 that one more buffer is available on the other channel. When buffer 1 is filled up
(the 82588 knows the size of buffers from the configuration command), the 82588 starts generating the DMA
requests on the other channel. This automatically starts
filling up buffer 2. As soon as the first byte is written
into buffer 2, the 82588 interrupts the CPU again asking for one more buffer. The CPU programs the channel of the DMA controller with the start address of
buffer 3, issues an ASSIGN ..LTERNATE buffer command with INTACK. This keeps the buffer 3 ready for
the 82588. This switching of channels continues until
the entire frame is received generating an end of frame
interrupt. The CPU maintains the list of pointers to the
buffers used.

°

Since a new buffer is allocated at the time of filling up
of the last buffer, the 82588 automatically switches to
the new buffer to receive the next frame as soon as the
last frame is completely received. It can start receiving
the new frame almost immediately, even before the end
of frame interrupt is serviced and acknowledged by' the
CPU. If a new frame comes in, and the previous frame

interrupt is not yet acknowledged, another interrupt
needed for new buffer allocation is buffered (and not
lnlilt)

A Col Clnnn

'!lie!

thoIlIo rt ...cot nneo

----J' - - - - - - - - _ .....---

---~ ...

......... -

........ : ....
-O""'-, +"................
-

t~ ......l ....... n .. nl .... ...I ....... ...I
..... - -...~ ... u··& ...

terrupt line goes active again for the buffered one.
If by the time a buffer fills up no new buffer is available,
the 82588 keeps on receiving. An overrun will occur
and will be reported in the received frame status. How. ever, ample time is available for the allocation of a new
buffer. It is roughly equal to the time to fill up a buffer.
For 128 byte buffers it is 128 x 8 = 1024 ms or approximately 1 millisec. You get 1 ms to assign a new
buffer after getting the interrupt for it. llence the process of multiple buffer reception is not time critical for
the system performance.

This method of reception is particularly useful to guarantee the reception of back-to-back frames separated by
IFS time. This is because a new buffer is always available for the new frame after the current frame is received.
Although both the DMA channels get used up in re-.
ceiving, only one channel is kept ready for reception
and the other one can be used for other commands until
the reception starts. If an execution command like
transmit or dump command is being executed on a
channel which must be allocated for recepfion, the
command gets automatically aborted when the AS~
SIGN ALTERNATE BUFFER command is issued to
the channel used for'the execution command. The interrupt for command abortion occurs after the end of
frame interrupt.

1-104

AP-236

the 82588 command register and knowing the results (if
any) through the status registers.

4.4 Memory Dump of Registers
All the 82588 internal registers can be dumped in the
memory by the DUMP command. A DMA channel is
used to transfer the register contents to the memory. It
is very similar to reception of a frame; instead of data
from the serial link, the data from the registers gets
written into the memory. This provides a software debugging and diagnostic tool.

4.5 Other Operations
Other 82588 operations like DIAGNOSE, TDR,
ABORT, etc. do not require any parameter or data
transfer. They are executed by writing a command to

5.0 StarLAN NODE FOR IBM PC
This chapter deals with the hardware-the StarLAN
board-to interface the IBM PC to a StarLAN Network. This is a slave board which takes up one slot on
the I/O channel of the IBM PC. Figure 27 shows an
abstract block diagram of the board. It requires the
IBM PC resources of the CPU, memory, DMA and
interrupt controller on the system board to run it. Such
a board has two interfaces. The IBM PC I/O Channel
on the system or the parallel side and the telephone
grade twisted pair wire on the serial side. Figures 28, 29
show the circuit diagram of the board.

PULSE
TRANSFORMER

TELEPHONE
JACK

8 BIT BUS
82588

TxD

PULSE

JIII.:;""'--1 SHAPING
SYSTEM
BUS

CONTROL

< >

RxD

SYS CLK

SQUELCH

+
ENABLE
CIRCUITS
231422-29

Figure 27. 82588 Based StarLAN Node

1-105

5

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.

OSC

D

I

+D?
+D.
+DO
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'DO
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+D'
+De

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AS

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£.
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81

-DACK.l
t::I

-DACKa

'AS
+A.

A24
A2&
A2.
A2?

+A?
'A.
+AS
+A4

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All

~ll

fli

0

U4

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a

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~
0

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'8

&
4

REG

REG

~ .....
.8

ua

""
Irr~~Q·

,.
II
8

II

'2

EN
UO

o
•
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U2

704L5125

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8

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9

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6

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15

~

TK. 2a
RK.

2

, .........

~&

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A22
A2.

..., ...

CLK

~ 1*

5
4

i!R

1974L832

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ca
c

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2'iiF2
231422-80

intJ

AP-236

to 82588 for commands and status, address 30lH accesses an on board control port that enables the various

5.1 Interfacing to the IBM PC 1/0
Channel

1ntprrnnt tIInti OM A linpl;l

IBM PC has '8 slots oil the system board to allow expansion of the basic system. All of them are electrically
identical and the I/O channel is the bus that links them
all to the 8088 system bus. The I/O channel contains
an 8 bit bidireCtional data bus, 20 address lines, 6 levels
of interrupt, 3 channels of DMA control lines and other
control lines to do I/O and memory read/write operations. Figure 30 shows the signals and the pin assignment for the I/O Channel.

spaces from 300H to 30FH. This was done to keep simplicity and minimum component count. Registers address decoding is done using a PAL (16L8) and an external NAND gate (U8).

Hex Range
OOO-OOF
020-021
040-043
060-063
080-083
OAX'
OCX
OEX
200-20F
210-217
220-24F
278-27F
2FO-2F7
2F8-2FF

Rear Panel
SIGNAL NAME
GNO

...,...

SIGNAL NAME
81

Al

~

1/0 CH CK

+RESET DRV

+07

+5V

+06

+IRQ2

+05

-5VOC

+04

+ORQ2

+03

-12V

+02

-CARD SLCTD

+01

+12V

+00

GNO

+1/0 CH ROY

810 Al0

-MEMW

+AEN

-MEMR

+A19

-lOW

+A18

-lOR

+A17

-OACK3

+A16

+ORQ3

+A15

-OACKl

+A14

+DROl

+A13

-OACKO

3AO-3A9
3BO-3BF
3CO-3CF
3DO-3DF
3EO-3E7
3FO-3F7
3F8-3FF

+Al1

820 A20

+IRQ6

+Al0

+IRQ7

+A9

+IRQ5

+A8

+IRQ4

+A7

+IRQ3

+A6

-OACK2

+A5

+T/C

+A4

+ALE

+Al

+5V

+A2

+OSC
GNO

300-31F
320-32F
378-37F
380-38C··
380-389"

+A12

CLOCK

\.

831 A31

+AO

....;;..

\

Usage
DMA Chip 8237 A-5
Interrupt 8259A
Timer 8253-5
PP18255A-5
DMA Page Registers
NMI Mask Register
Reserved
Reserved
Game Control
Expansion Unit
Reserved
Reserved
Reserved
Asynchronous Communications
(Secondary)
Prototype Card
Fixed Disk
Printer
SDLC Communications
Binary Synchronous Communications
(Secondary)
Binary Synchronous Communications
(Primary)
IBM Monochrome Display/Printer
Reserved
Color/Graphics
Reserved
Diskette
Asynchronous Communications
(Primary)

• At power-on time, the Non Mask Interrupt into the
8088 is masked off.
This mask bit can be set and reset through
system software as follows:
Set mask: Write hex 80 to I/O Address hex AO
(enable NMI)
Clear mask: Write hex '00 to I/O Address hex AO
(disable NMI)
•• SDLC Communications and Secondary Binary
Synchronous Communications cannot be used
together because their hex addresses overlap.

+Al

...;..

PUP." thnnn-h nnhr turn g,.L

d~~;e;r~r~-;e~~d: -th~-~rd ;;~--~llth~ -1-6'add;es~;s

COMPONENT SIDE

231422-31

Figure 39.1/0,Channel Diagram
5.1.1 REGISTER ACCESS AND DATA BUS
INTERFACE

Figure 31. I/O Address Map
The CPU accesses the StarLAN adapter card through 2
I/O address windows. Address 300H is used to access

1-108

inter

AP-236

M-A9---+
AO---.

~ CS_ (to 588)

LOGIC
U2, U8

AEN---+

~ LDPRL (to DMA, INTERRUPT enable lines)

IOW_---+

'-----'

231422-56

Register Access

Format of Following Equations Will Be According To
The Following Specifications:
INVERT
SIGNAL ACTIVE LOW
II:

LOGIC AND

#

LOGIC OR

A9NANDA8
CS_

=I

LDPORT_
BUSEN_

=I

(A9

( IAEN

=I

II:

IA9NANDA8

II:

( lAEN

=DACKl_

A8)

II:

II:

II:

IA7

IA9NANDA8

DACK2_

II:

II:

IA6

IA5

II:

II:

IA4

II:

lAO )

IA7

II:

IA6

IA5

II:

IA4

II:

(I ( IAEN

II:

IA9NANDA8

II:

IA7

II:

II:

The signal CS_ decodes address 300H, it is only active
when AEN is inactive meaning CPU and not DMA
cycles. LDPORT_ has exactly the same logic for address 301H, but it is only active during I/O write cycles. The I/O port sitting on address 30lH is write
only. The data BUS lines DO to D7 are buffered from
the 82588 ·to the PC bus using an 74LS245 transceiver
chip.

II:

AO
IA6

IIOWR_ )

II:
II:

IA5

II:

IA4»;

The Bus transceiver is enabled if: A DMA access is
taking place, or I/O ports 300H to 30FH are being
accessed.
5.1.2 Control Port
As mentioned the StarLAN adapter port has. a 4-bit
write only control port. The purpose of this port is to
selectively enable the DMA and INTERRUPT request
lines. Also it can completely disable the transmitter.
Control Port Definition

I ENDRQ1 I

ENDRQ3

I

EN INTER

I TXEN

TO 588

231422-57

Data Bus Interface

ENDRQl, ENDRQ2 : "I" Enable DMA requests.
: "I" Enable INTERRUPT
ENINTER
request.
: "I" Enable the transmitter.
TXEN
On power up all bits default to "0".

1-109

intJ

AP-236

5.1.3 CLOCK GENERATION
The 82588 requires two clocks for operation. The system clock and the serial clock. The serial clock can be
generated on chip by putting a crystal across Xl and
X2 pins. Alternatively, an externally generated clock
:can be fed in at pin XI (with X2 left open). In both
cases, the frequeQcy must be either 8 or 16 times (sampling factor) the desired bit rate. For StarLAN, 8 or 16
MHz are the correct values to generate I Mbls data
rate. A configuration parameter is used to tell the
82588 what the sampling factor is. An externally supplied clock must have MOS leve~s (~.6V -3.9V). ~pec~­
cations for the crystal and the CIrcuIt are shown In FIgure 32.
The system clock has to be supplied externally. It can
be up to 8 MHz. This clock runs the parallel side of the
82588. Its frequency does not have any impact on the
read and write access times but on the rate at which
data can be transferred to and from the 82588 (Maximum DMA data rate is one byte every two system
clocks). This cI~ck doesn't require MOS levels.
The 1/0 channel of the IBM PC supplies a 4.77 MHz
signal of 33% duty cycle. This signal could be used as a
system clock. It was decided, however, to generate a
separate clock on the StarLAN board to be independent of the 1/0 channel clock so that this board can
also be used in other IBM PCs and also in some other
compatibles. The 8 MHz system clock is generated us-

ing a DIP OSCILLATOR which have the required 50
ppm tolerance to meet StarLAN. This clock is converted to MOS levels by 74HCTOO and fed into both the
system and' serial clock inputs.
5.1.4 DMA INTERFACE
The 82588 requires either one or two DMA channels
for full operation. In this application, one channel is
dedicated for reception and the other is used for transmissions and the other commands. Use of only one
DMA channel is possible' but may require more complex' software, also some RX frames may be lost during
switches of the DMA channel from the receiver to the
transmitter (Those frames will be recovered by higher
layers of the protocol). Also using only .0J?e pMA
channel will limit the 82588 loopback functionalIty. So
the recommendation is to operate with two DMA channels if available. APPendix C describes a method of operating with only one DMA channel without loosing
RX frames.
'
The IBM PC system board has on~ 8237A DMA controller. Channel 0 is used for doing the refresh of
DRAMs. Channels I, 2 and 3 are available for add-on
boards on the I/O Channel. The floppy disk controller
board uses the DMA channel 2 leaving exactly two
channels (I and 3) for the 82588. The situation is worse
if the IBM PC/XT is used, since it uses channel 3 for
the Winchester hard disk leaving just the channel I for

Series Resonance
-Frequency Will Drift by About 400 PPM from Nominal
-No Capacitors Needed
-Doesn't Meet StarLAN Requirements

CRYSTAL

Meeting StarLAN 100 PPM Requirements
-Use Parallel Resonance Crystal
-Recommended For Precise Frequencies
-82588 X-TAL ,Oscillator Stability ± 35 PPM (0-70°C)

.=h
0
--

I

i
i-

Crystal: Load Capacitance
= 20 pF
Shunt Capacitance = 7 pF Maximum
Series Resistance = 30n Maximum
Frequency Tolerance = 50 PPM (0-7fY'C)
CI, C2 -+ 27 pF or 39 pF, 5%
Figur, 32. Crystal Specifications

1-110

C1

82588

C2
231422-81

intJ

AP-236

the 82588. On the other hand, the IBM. PCIAThas 5
free DMA channels. We will assume that 8237ADMA
channels I and 3 are available for the 82588 as in the
case of the IBM PC.
Since the channel 0 of 8237A is used to do refresh of
DRAMs all the channels should be operated in single
byte transfer mode. In this mode, after every transfer
for any channel the bus is granted to the current highest priority channel. In this way, no channel can hog
the bus bandwidth and, more important, the refresh of
DRAMs is assured every 15 microseconds since the refresh channel (number 0) has the highest priority. This
mode of operation is very slow since the HOLD is
dropped by the 8237A and then asserted again after
every transfer. Demand mode of operation is a lot more
suitable to 82588 but it cannot be used because of the
refresh requirements.

5.1.5 INTERRUPT CONTROLLER

The 82588 interrupts the CPU after the execution of a
command or on reception of a frame. It uses the 8259A
interrupt controller on the system board to interrupt
the CPU. There are 6 interrupt request lines, IRQ2 to
IRQ7, on the I/O channel. Figure 34 shows the assignment of the lines. In fact, none of the lines are completely free for use. To add any new peripheral which
uses a system board interrupt, this interrupt needs to
have the capability to share the specific line, by driving
the line with a tri-state driver. The 82588 StarLAN
adapter board can optionally drive interrupt lines
IRQ3, IRQ4 or IRQ5 (An 74LSI25 driver is used).
Number

Usage

NMI

Parity
Timer
Keyboard
Reserved
Asynchronous Communications
(Secondary)
SDLC Communications
SSC (Secondary)
Asynchronous Communications
(Primary)
SDLC Communications
SSC (Primary)
Fixed Disk
Diskette
Printer

0
1
2
3

Whenever the 82588 interfaces to the 8237A in the single transfer mode, there is a potential 8237A lock-up
problem. The 82588 may deactivate its DMA request
line (DREQ) before receiving an acknowledge from the
DMA controller. This situation may happen during
command abortions, or aborted receptions. The 8237A
under those circumstances may lock-up. In order to
solve this potential problem, an external logic must be
used to insure that DREQ to the DMA controller is
never deactivated before the acknowledge is received.
. Figure 33 shows the logic to implement this function.
This logic is implemented in the 16L8 PAL.
The 82588 DREQ lines are connected to the IBM/PC
bus through tri-state buffers which are enabled by writing to 1/0 port 301H. This function enables the use of
either .one or two DMA channels and also the sharing
of DMA channels with other adapter boards.

4

5
6
7

,Figure 34. IBM PC Hardware Interrupt Listing

588REO~
.
DREO
DACK

RESET----------'

588 REO---.l

DREO---.l
231422-82

Figure 33. DMA Request Logic

1-111

inter

AP-236

5.2 Serial Link Interface

5.2.1 TRANSMIT PATH

A ..... _: .... ",1 Ct ......1 "ltrt.T "'..:I ................. l... ........ ...:1 : ....................... ,..+ ... ...:1 +........... ...
... ... Jl".OW-....... u .........
...............................
.., .................... u
.... v ..............................................

Thp

~.L.L

twisted pair wiring using an extension cable (typically
up to 8 meters-25 ft.). See Figure 35. One end of the
cable plugs into the telephone modular jack on the StarLAN board and the other end into a modular jack in
t,he wall. The twisted pair wiring starts at the modular
jack in the wall and goes to the wiring closet. In the
wiring closet, another telephone extension cable is used
to connect to a StarLAN HUB. The transmitted signal
from the 82588 reach the on-board telephone jack
through a RS-422 driver with pulse shaping and a pulse
transformer. The received signals from the telephone
jack to the 82588 come through a pulse transformer,
squelch circuit and a receive enable circuit.

~, L.L.L.L.U..u.&.&.U

~inO'lp

pnrlpti

tr~nQ.m1t Qion~l

nn thp Iyn nin 1q

~~;;v~rt;d-t~-~' diff~;~tial sig~al a~d the rise a~d fall

times are increased to 150 to 200 ns before feeding it to
the pulse transformer (this pulse shaping is not a requirement, but proves to give good results). Am26LS30
is a RS-422 driver which converts the TxD signal to a
differential signal. It also has slew rate control pins to
increase to rise and fall times. A large rise and fall time
reduces the possibility of crosstalk, interference and radiation. By the other hand a slower edge rate increases
the jitter. In the StarLAN adapter card, the first approach was used. The 2~LS30 converts /l square pulse
to a trapezoidal one-see Figure 36. The filtering effect
of the cable further adds to reduce the higher frequency
components from the waveform so that on the cable the
signal is almost sinusoidal. The pulse transformer is for
DC isolation. The pulse transformers from Pulse Engineering-type PE 64382-was used in this design. This
is a dual transformer package which introduces an additional rise and fall time of about 70-100 ns on the
signal, helping the former discussed waveshaping.
5.2.2 IDLE PATTERN GENERATION

INTO IBM PC

WIRING
PANEL

IN THE WIRING CLOSET
231422-33

StarLAN requires transmitters to generate an IDLE
pattern after the last transmitted data bit. The IDLE
pattern is defined to be a constant high level for 2-3
microseconds. The purpose of this pattern is to insure
that receivers will decode properly the last transmitted
data bits before signal decay. Currently the 82588 needs
one external component to generate the IDLE. The operation principle .is to have an external shift register
(74LSI64) that will kind of act as an envelope ,detector
of the TXD line. Whenever the TXD line goes low

Figure 35. Path from StarLAN Board to HUB

82588

TxD

26LS30

\

150n.
RISE/FALL
TIMES

•

II~

~)
231422-34

Figure 36. Wave Shaping
1-112

inter

AP-236

(first preamble bit), the output of the shift register
(third cell) will immediately go low, enabling the RS422 driver, the shift register being clocked by TCLKwill time the duration of the TXD high times. If the
high time is more than 2 microseconds, meaning that
the 82588 has gone idle, the transmitter will be disabled
(See Figure 37). Another piece of this logic is the ORing of the output of the shift register with TXEN-signal which comes from the board control' port. This signal completely disables the transmitter. The other purpose of this enable signal, is to make sure that after
power-up, before the 82588 is configured, the RS-422
drivers won't be enabled (TCLK_ is not active before
the configure command). See Figures 28, 29 for the
complete circuit.
5.3 RECEIVE PATH

The signal coming from the HUB over the twisted pair
wire is received on the StarLAN board through a lOOn
line termination resistor and a pulse transformer. The
pulse transformer is of the same type as for the transmit
side and its function is dc isolation. The received signal
which is differential and almost sinusoidal is fed to the
Am26LS32 RS-422 receiver. As seen from Figure 38
the pulse transformer feeds two RS-422 receivers. The
one on the bottom is for squelch filtering and the one
above is the real receiver which does real zero crossing
detection on the signal and regenerates a square digital
waveform
from
the
sinusoidal
signal
that

is received. Proper zero crossing detection is very essential; if the edges of the regenerated signal are not at zero
crossings, the resulting signal may not be a proper
Manchester encoded signal (self introduced jitter) even
if the original signal is valid Manchester. The resistors
in the lower receiver keep its ·differential inputs at a
voltage difference of 600 mY. These bias resistors ensure that the output remains high as long as the input
signal is more than -600 mY. It is very important that
the RxD pin remains HIGH (not LOW or floating)
whenever the receive line is idle. A violation of this may
cause the 82588 to lock-up on transmitting. Remember,
that based on the signal on the RxD pin, the 82588
extracts information on the data being received, Carrier
Sense and Collision Detect. This squelch of 600 mY
keeps the idle line noise from getting to the 82588. Figure 39 shows that when the differential input of the
receiver crosses zero, a transition occurs at the output.
It also shows that if the signal strength is higher than
-600 mY, the output does not change. (This kind of
squelching is called negative squelching, and it is done
due to the fact that the preamble pattern starts with a
going low transition). Note that the differential voltage
at the upper receiver input is zero when the line is idle.
The output of the squelch goes to a pulse stretcher
which generates an envelope of the received frame, The
envelope is a receive enable signal and is used to AND
the signal from the real zero crossing receiver before
feeding it to the RxD pin of the 82588.

-u::BL
18- 22
TX - FAST CLOCKS

'''--wm.J - - - - - - - - - RS-422

ENABLE-----,~)_______________________________________C_E_LL__~!

231422-83

Figure 37. Idle Generation

1-113

inter

AP-236

FILTERING OF
IoIlm-l F"RF"nllF"Nr.v Nnl<:;F"

:101! ·~I '-. . .I·~.~--,----or

ftl'!"I"t:"nII'!"O '''1:''01'\
0. . . . . . . . . . . . . " , . . . . . 0. ....

CROSSING

>--------------+ DATA

t

TERMINATION

>-----1

TIME
SQUELCH

ENVELOPE
IDLE
DETECT

CARRIER

(OPTIONAL)

INPUT
, DATA

------~

-'I!!!!!!!!!!!!!'"

CARRIER -

~----------------

_ _ _ _ _--'
3 EDGES

b-

1.6}Ls

Figure 38. Input Ports

600
400

...J

...'"

;:

200

%

...""
"-

mV

0

a

-200

.......
""

-600

"-

-400

~::l

"'11.

... -

0%
D::

FILTERED-OUT
BY SQUELCH

,,,t

I

LJ1S

VOL~~__________________________

VOHtmu
•
u'
VOL

-r------------

Figure 39. Squelch Circuit Output

1-114

231422-35

231422-84

inter

AP-236

5.4 80188 Interface to 82588

5.5 iSBX Interface to StarLAN

Although the 82588 interfaces easily to almost any
processor, no processor offers as much of the needed
functionality as the 80186 or its 8 bit cousin, the 80188.
The 80188 is 8088 object code compatible processor
with DMA, timers, interrupt controller, chip select logic, wait state generator, ready logic and clock generator
functions on chip. Figure 40 shows how the 82588, in a
StarLAN environment interfaces to the 80188. It uses
the clock, chip select logic, DMA channels, interrupt
controller directly from the 80188. The interface components between the CPU and the 82588 are totally
eliminated.

Figure 41 shows how to interface the 82588 in a StarLAN environment to the iSBX bus. It uses 2 DMA
channels-tapping the second DMA channel from a
neighboring iSBX connector. Such a board can be used
to make a StarLAN to an Ethernet or a SNA or DECNET gateway when it is placed on an appropriate SBC
board. It may also be used to give a StarLAN access to
any SBC board (with an iSBX connector) independent
of the type of processor on the board.

1-115

cl

4

D

SYSTEn RESET
BIUBB

..

8Ea "'4

jj

"2

RESET "1
DRQ818
BRQ. 19

."

a'
I:
;

..

AD?
AD6
AD6
AD"

17
16
13
11

....•••

ESET

IDLE
lfR'f' "')(21

.•"•• h

....
?
!....

Rn 5
eLI< OUT

......, :S'
Ol

INTI

H.le

T)lt"~~~~

'"

.

~

."

U'

iil'

p.)
Co)
CJ)

U3

iS'

B

co
J\)

~

+5U

.4

,.0

704LS191

~10

..

I

Q.~

B
•
C
D

4

I?

~.co
§

QB
QC
QD

2
'"
1

LIJ

1
D....U 5

nA'
Ul

5

••
•••.5
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231422-86

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AP-236

6.0 THE StarLAN HUB

6.1 A. StarLAN Hub for the. IBM/PC

The function of a StarLANHUB is described in section
2.0. Figure 42 shows a block diagram of a HUB. It
receives signals from the nodes (or lower level HUBs)
detects if there is a collision, generates the collision
presence signal, re-times the signal and sends it out to
the higher level HUB. It also receives signals from the
higher level HUB, re-times it and sends it to all the
nodes and lower level HUBs connected to it. If there is
no higher level HUB, a switch on the HUB routes the
upstream received signal down to all the lower nodes.
The functions performed by a HUB are:

Figure 43 shows the implemention of a 5/6 port HUB
for the IBM/PC.
The idea of the following design is to show a HUB that
plugs into the IBM/PC backplane. This HUB not only
gets its power from the backplane, but also enables the
host PC to be one NODE into the StarLAN network.
This embedded node scheme enables further savings
due to the fact that aU the analog interface for this port
is saved (receiver, transmitter, transformer, etc).
This kind of board would suit very much a smaU cluster topology (very typical in departments and small offices) where the HUB board would be plugged into the
FILE SERVER PC (pC/XT, PC/AT).

"Receiving signals, squelch
• Carrier Sensing
'Collision Detection
'Collision Presence Signal Generation
'Signal Retiming
"Driving signals on to the cable
'Jabber Function
'Receive protection Timer

The HUB design doesn't implement the Jabber and the
protection timers as called by the IBASE5 draft standard. Those functions are optional and were not closed
during the writing of this AP-NOTE. This HUB does
implement the RETIMING circuit which is an essential requirement of StarLAN..
Figures 44 to 49 show a complete set of schematics for
the HUB design.

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RECEIVE PAIR # N
231422-40

Figure 42. Star LAN HUB

1-118

inter

AP-236

PHONE JACKS

231422-87
• Low Cost HUB, Uses IBM/PC Power Supply
• 82588, Embedded Port Savings
Transformers
422 Drivers
• Functional StarLAN Cluster, For Low Cost/Small Topologies

Figure 43, IBM/PC Resident HUB

1-119

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231422-93

inter

AP-236

The time squelch for the NODE board is implemented
by the 82588 (see section 3.7) this circuit makes sure
that pulses that are shorter than a specified duration
will be filtered out.

6.1.1 HUB. INPUT PORTS
Figure 38 shQWS a block diagram of an input port. Dif-.
ferently than the implementation in Figure 29 the HUB
input port is potentially more complex than the NODE
input port. The reason being that the HUB is a central
resource arid much more sensitive to noise. For example, if the NODE input port would falsely interpret
noise on an IDLE. line as valid signal, the worst case
situation would be that this noise would be filtered out
by the 82588 time squelch circuitry, on the HUB by the
other hand, this false carrier sense could trigger a COLLISION and a good frame (on another input) potentially discarded.

The other components of the block diagram were explained in section 3.0.
The HUB design doesn't implement the HIGH FREQUENCY FILTER and TIME SQUELCH. In the
HUB design as an output of each input port, two signals are available: Rn, En, (RA, RB ... , EA, EB ... ).
The Rn signals are the receive data after the zero crossing receivers. The En lines are CARRIER SENSE signals. The HUB design supports either 5 or 6 input
ports, dependent upon if it is configured as IHUB or
HHUB. Port RE, EE (Figure 49) is bidirectional, configurable for either input or output. Port RF, EF_ is
the embedded 82588 port, and doesn't require the ana. log circuitry (EF is inverted, being generated from the
. RTS_ signal).

As shown in Figure 38 immediately after the termination resistor, there is a HIGH FREQUENCY FILTER
circuit. The purpose of this circuit is to eliminate high
frequency noise components keeping noi~e jitter into
the allocated budget (about ± 30 ns). A 4 MHz two
pole butterworth filter is being recommended by the
IEEE 802.3 IBASE5 task force (see Figure 50).

·"I!f !110~ XX ::~TED

RXVE...RI-_...._ _ _ _ _ _ _ _

231422-94

Figure 50. Receiver High Frequency Filter

1-126

inter

AP-236

6.1.2 COLLISION DETECTION
Rn and En signals from each channel are fed to a 16L8
PAL, where the collision detection function is per·
formed.

Collision Detection in the Star LAN HUB is performed
by detecting the presence of activity on more than one
input channels. This means if the signal En is active for
more than one channel, a collision is said to occur. This
translates to the PAL equations:

COLLISION DETECTION:
COT = ! (EA & !EB & !EC & !ED & !EE & EF_ #
! EA & EB & IEC & !ED & !EE & EF_ #
!EA&!EB&EC&!ED&!EE&EF_ #
!EA&!EB&!EC& ED&!EE&EF_ #
! EA & IEB & !EC & lED & EE & EF_ #
!EA&!EB&!EC&!ED&!EE&!EF_ #
! EA & !EB & !EC & !ED & !EE & EF_);

(only EA active)
(only EB active)
(only EC active)
(only ED active)
(only EE active)
(only EF active)
(none of the inputs active)

COLLISION DETECTION SR·FF:
COLLEN_ = ! (COT # COLLEN );

(set with collision)

COLLEN_ = ! ( RESET_ # COLLEN_ #
( !CDT & !EA & !EB & !EC & !ED & !EE & EF_);
( reset when all inputs inactive)
RECEIVE DATA OUTPUT:
RCVDAT = ( (RA # !EA ) & ( RB # !EB ) & ( RC # !EC) &
(RD # !ED) & (RE # lEE) & (RF # EF_»;
(output is high ifno active input)

1·127

AP·236

The COLLEN signal once triggered will stay active until all inputs go quiet. This signal is used externally to .
either enable passing RCVDAT or the collision presence signal (CPS) to the retiming logic. An external
multiplexer using 3 nand gates is used for this function.
Note that in this specific implementation the. CPS/
RCVDAT mUltiplexer is before the retiming logic,
which is different from Figure 42 diagram. StarLAN
provides enough BIT-BUDGET delay to allow the CPS
signal to be generated through the retiming FIFO. In
this HUB implementation it was decided to use this
option to make sure that the CPs startup is synchronized with the previously transmitted bit as required by
the lBASE5 draft.
'
6.1.3 THE LOCAL 82588

As described before, the purpose of the local 82588 is to
enable the Host IBM/PC to also be a node into the
Star LAN network. The interface of this 82588 is exactly similar to the one explained in section 5. The RTS_
signal serves as the carrier EF_ signal, and TXD as
RF signal. This local node interfaces to the HUB without any analog interface which is a significant saving.
6.1.4 THE COLLISION PRESENCE SIGNAL

The Collision Presence Signal (CPS) is generated by the
HUB whenever the HUB detects a collision. It then
propagates the CPS to the higher level HUB. The CPS
signal pattern is shown in Figure 51. Whenever a StarLAN node receives this signal, it should be able
to detect within a very few bit times that a collision
occurred. Since the, nodes detect the occurrence of a '
collision by detecting violations in Manchester encoding, the CPS must obviously be a signal which violates

Manchester encoding. Section 3.5 shows that the CPS
has missing mid-cell transitions occurring every two
and a half bit cells. These are detected as Manchester
code violations. Thus, the StarLAN node is presented'
with collision detection indications every two and a half
ms. This results in fast and reliable detection of collisions. CPS has a period of 5 ms.
One may wonder why such a strange looking signal was
selected for CPS. The rationale is that this CPS looks
very much like a valid Manchester signal-edges are
0.5 or 1.0 microsec. apart-resulting in identical radiation, cross-talk and jitter characteristics as a true Manchester. This also makes the re-timing logic for the signals simpler-it need not distinguish between valid
Manchester and CPS. Moreover, this signal is easy to
generate.
A few important requirements for CPS signal are: a) it
should be generated starting synchronized with the last
transmitted bit cell. CPS is allowed to 'start either low
or high, but no bit cell of more than 1 microsecond is
allowed (Avoid false idles, very long "low" bits). b)
once it starts, it should continue until all the input lines
to the HUB die out. Typically, wheh the collision occurs, the multiplexor in the HUB switches from RCV
signal to the CPS. This switch is completely asynchronous to the currently being transmitted data, and by
such may violate the requirement of not having bit cells
longer than 1 /Ls. In order to avoid those long' pulses,
the output of the CPS/RCVDAT multiplexer is passed
through the retiming circuitry which will correct those
long pulses to their nominal value. The reason for restriction b) is to ensure that the CPS is seen by all nodes
on the network since it is generated until every node
has finished generating the Jam pattern.

I 2t I t I 2t I 2t It i t = 0.5 }-'S
~5}-'s PERIOD---I
• MISSING MID-CELL TRANSITION

231422-42

• Collision Presence Signal (CPS) is generated by the HUB when it detects more than one input line active.
• CPS violates Manchester encoding rules-due to missing mid-cell transitions-hence is detected as a collision by the DTE (82588).
Choice of Collision Presence Signal
• It is a Manchester look-alike signal-edges are 0.5 or 1.0 /Ls apart.
- Identical radiation, crosstalk and jitter characteristics
- Eases ietiming of the signal in the HUB
• It is easy to generate--1.5 TTL pack, or in a PAL
Figure 51. Collision Presence Signal

1-128

AP-236

CPS is generated using a 4-bit shift register and a flipflop as shown in Figure 52. It works off a 2 MHz clock.
A closer look at the CPS waveform shows that it is
inverse symmetric within the 5 /ks period. The circuit is
a 5-bit shift register with a complementary feedback
from the last to the first bit. The bits remain in defined
states (01100) till collision occurs. On collision the bits
start rotating around generating the pattern of
0011011001, 0011011001, 00110 ... with each state
lasting for 0.5 /ks.

a result of jitter, may no longer be decodable. The process of either re-aligning the edges or reconstructing the
signal or even re-generating' the signal so that it once
again "looks new" is called re-timing. StarLAN requires for the signal to be re-timed after it has travelled
on a segment of cable.· In a typical HUB two re-timing
circuits are necessary; one for the signals going upstream towards the higher level HUB and the other for
signals going downstream towards the nodes.
6.1.6 RETIMING CIRCUIT, THEORY OF

o

OPERATION

o
COLLISION
, - - -..... PRESENCE
SIGNAL
Q

COLLISION

231422-43

Figure 52. Collision Presence
Signal Generation

6.1.5 SIGNAL RETIMING
Whenever the signal goes over a cable it suffers jitter.
This means that the edges are no longer separated by
the same 0.5 or 1.0 /ks as at the point of origin. There
are various causes of jitter. Drivers, receivers introduce
some shifting of edges because of differing rise and fall
times and thresholds. A random sequence of bits also
produces a jitter which is called intersymbol interference, which is a consequence of different propagation
delays for different frequency harmonics in the cable.
Meaning short pulses have a longer delay than long
ones. A maximum of 62.5 ns of jitter can accumulate in
a StarLAN network from a node to a HUB or from a
'HUB to another HUB. The following values show what
are the jitter components:
Transmitter skew
Cable Intersymbol interference
Cable Reflections
Reflections due to receiver
termination mismatch
HUB fan-in, fan-out
Noise
Total

± 10 ns
± 9 ns

± 8 ns
±5 ns
±5 ns
±25.5

±62.5 ns

It is important for the signal to be cleaned up of this
jitter before it is sent on the next stretch of cable because if too much jitter accumulates, the signal is no
longer meaningful. A valid Manchester signal would, as

This section will discuss the principles of designing a
re-timing circuit. Figure 53 shows the block diagram of
a re-timing circuit. The data coming in is synchronized
using an 8 MHz sampling clock. Edges in the waveform
are detected doing an XOR of two consecutive samples.
A counter counts the number of 8 MHz clocks between
two edges. This gives an indication of long (6 to. 10
clocks) or short (3 to 5 clocks) pulses in the received
waveform. Pulses shorter than 3 clocks are filtered out.
Every time an edge occurs, the length-(S)hort or
(L)ong-of the pulse is fed into the FIFO. Retiming of
the waveform is done by actually generating a new
waveform based on the information being pumped into
the FIFO. The signal regeneration unit reads the FIFO
and generates the output waveform out of 8 MHz clock
pulses based on what it reads, either short or longs. In
summary every time a bit is read from the fifo, it indicates that a transition needs to occur, and when to fetch
the next bit. When idle the output of the retiming logic
starts with a "high" level.
FIFO
empty

S
S
L
L

Output

...... 1111
0000
1111
00000000
11111111

It can be seen that the output always has edges separated by 4 or 8 clock pulses---D.5 or 1.0 /ks.
The FIFO is primarily needed to account for a difference of clock frequencies at the source and regeneration
end. Due to this difference, data can come in faster or
slower than the regeneration circuit expects. A 16 deep
FIFO can handle frequency deviations of up to 200
ppm for frame lengths up to 1600 bytes. The FIFO also
overcomes short term variations in edge separation. It
is essential that the FIFO fills in up to about half before
the process of regeneration is started. Thus, if the regeneration is done at a clock slightly faster than the
source clock, there is always data in the FIFO to work
from. That is why the FIFO threshold detect logic is
necessary, which counts 8 edges and then enables the
signal regeneration logic.
.

1-129

intJ ,
Example:
Input Waveform

AP-236

... 11110001111000000011111111110001111100 ...

I

Input into
the FIFO

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Regenerated Output:
... 1 11110000111100000000111111110000111 ...
Output:
FIFO:
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INPUT
DATA ---:-+

INCREt.lENT EDGE !
COUNTER

efl FO ACCOt.lt.lODATES fOR fREQ.
DR 1m (SPEC 100 PPt.l)

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(1 500 BYTES x 8) x 200 PPt.l

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EDGE
DETECTOR

SYNCHRONIZER

8t.lHztLOCK



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DISCRlt.lINATOR

LOAD!
fifO

fifO
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DETECT

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SHORT/LONG
INfO

fiFO

FIFO OUTPUT
ENABLE SIGNAL
REGENERATION

-

SIGNAL
REGENERATION

--+ OUTPUT
231422-95

Figure 53. Retiming Block Diagram

6.1.7 RETIMING CIRCUIT IMPLEMENTATION
The retiming circuit implementation can be seen in Figures 47, 48. Both figures implement exactly the same
function, one for the upstream, and the other for the
downstream. The retiming circuit was implemented using about 8 SSI, MSI TTL components, one fifo chip
and one PAL. The purpose of implementing this function with discrete components was to show the implementation details. The discussion of the implementation will refer to Figure 47 for unit numbers.
The signal UPIMP which is an output of the HUB
JilUltiplexing logic, is asynchronous to the local clock.
This signal is synchronized by two flip-flops and fed
into an edge generation logic (basically an XOR gate
that compares the present sample with the previous
one). On every input transition a 125 ns pulse will be

generated at the output of the edge detector (U28). This
pulse will reset the 74LSI61 counter that is responsible
for measuring pulse widths (in X8 clock increments).
The output of the pulse discriminator will reflect the
previous pulse width every time a new edge is detected.
The following events will take place on every detected
edge:
1. U26 which is the threshold detector will shift one
"I" in. The outputs of U26 will be used by the control PAL to start the reconstruction process.
2. The output of U23 which specifies the last pulse
width will be input into the control PAL for determining if it was a long or short pulse. The result of
this evaluation will be the LSIN signal which will be
loaded into the fifo (U22).
U22 is the retiming FIFO, it is 16x4 fifo, but only one
bit is necessary to store the SHORT/LONG information.

1-130

inter

AP-236

CONTROL LOGIC PAL functions (U25):

Terminal count of the reconstruction
counter, indicating that reconstruction
of a new bit will get started.
Output of the FIFO indicating, that the
FIFO is empty and that IDLE generation can get started.

CNTTC:

Signals definition:
INPUTS:
PDO.. PD3:

THRESH:
CNTEN:

CNTEND:
OUTDAT:

OR:
Outputs of the pulse descriminator, indicate the width of the last measured
pulse.
Output of the edge detector, pulse of 125
ns width, indicates the occurrence of an
edge in the input data.
Output of the threshold logic, indicates
at least one bit was already received.
Output of the Threshold logic, indicates
7 bits have been loaded into the FIFO,
and that signal reconstruction can begin.
The same signal as before delayed by one
clock.
Output of the retiming logic, is feedback
into the PAL to implement a clocked
T-FF.
Resets the retiming logic.

LDFIFO_ = ! ( PDl

PD2

#

#

OUTPUTS:
LDFIFO_:

Loads SHORT/LONG indications into
the FIFO.
Indicates SHORT/LONG
Loads FIFO SHORT/LONG output
into the reconstruction counter.
Together with the external U21 flip-flop
and OUTDAT implement a clocked
T-FF.

ODAT:

Loading the FIFO will be done every time there is an
edge, we have passed the one bit filter threshold level,
and the pulse width is longer than two 8X clocks. This
one bit threshold level serves as a time domain filter
discarding the first received preamble bit.

PD3 )

&:

!EDD_

&:

THRESH ) ;

Whenever there is an edge, we are above the first received bit threshold
and the pulse width is longer than '1" the fifo is loaded.

LSIN

=!

(PD3

(PD2

#

&:

PD~)

#

(PD2

&:

PD1»;

Every pulse longer than 6is considered to be a long pulse.

CNTPE_

=!

( (CNTEN

&:

!CNTEND)

#

CNTTC ) ;

The reconstruction counter is loaded in two conditions:
Whenever CNTEN comes aati ve, meaning the FIFO threshold of seven was exceeded.
Whenever the terminal count of U24 is acti ve meaning a new pulse is going to be reconstructed.

ODAT

= !RESET_

#
#
#

(!CNTPE_
CNTPE_
(!CNTPE_
(

&:
&:
&:

!OUTDAT)
OUTDAT)
lOR)

(A)
(B)

(C)

Minterm (A) and (B) implement a T-FF, whenever CNTPE. is 'low"
ODAT will toggle. The external U21is part of this flip-flop.
Minterm (C) insures the output of the flip-flop will go inactive
'high' when the FIFO is empty. RESET. causes the output to go
"high" on ini tial1zation.

1-131

inter

AP-236

U24 as mentioned is the reconstruction counter. This
counter is loaded by the control logic with either 8 or
12, it counts up and is reloaded on terminal count. Essentially generating at the output nominal length longs
and shorts.

will be started, and Tl will time out after 25 to 50 ms.
T2 will time-out after 51 to lOOms. During T2 time,
after Tl expired, the HUB will send the CP-PATTERN informing any jamming stations to quit their
transmissions. If on T2 time-out there are still jamming
ports, their input is going to be disabled. A disabled
port, will be reenabled whenever its. input becomes
again active and the downward side is idle.

U22 is the retiming FIFO, and its function as mentioned is to accommodate frequency skews between the
incoming and outgoing signal.
U27 is the IDLE generation logic. The purpose of this
logic is to detect when the FIFO is empty, meaning that
no more data needs to be transmitted: On detection of
this event this component will generate 2 ms of IDLE
time. On the end of IDLE the whole retiming logic will
be reset.
6.1.8 DRIVER CIRCUITS

The signal coming out of the RETIMING LOGIC is
fed into 26LS30s and pulse transformers to drive the
twisted pair lines (See section 5,0 for details).
6.1.9 HEADER/INTERMEDIATE HUB SWITCH

As seen on Figure 43 this hub can be configured as
either an intermediate hub, or a Header one. One of the
phone jacks, more specifically JACK #5 is either an
input port or an output one. In order to implement this
function, an 8 position DIP SWITCH (SWI) is used.
The phone jacks are marked with UD, DD notation,
meaning upstream data, and downstream data respectively. As specified in the StarLAN IBASE5 draft
NODES transmit data on UD pair, and HUBS on the
DD pair. Switch SWI has the function to invert UD,
DD in PHONE JACK # 5 to enable it to be either
input or output port.

The following is an explanation of the requirement that
the downward side be idle to reenable an input port.
Consider the case of Figure 54. The figure shows a two
port HUB. Port A has two wires Au, Aci for the up and
down paths. Port B has Bu, Bd respectively. Port C is
the output port, that broadcasts to the other HUBs
higher in the hierarchy. Consider the case as shown,
where Bu and Bd are shorted together. Suppose the case
that port Au is active. Its signal will propagate up in the
hierarchy through Cu and come down from Cd to Ad,
and Bd. Due to the short between Bd and Bu the signal
will start a loop, that will first cause a collision and jam
the network forever. This kind of fault is taken care of
by the jabber circuitry. Tl and T2 will expire, causing
the jabber logic to disable Bu input. Upon this disabling
Bu is going to go Idle and be a candidate for future
enabling. Suppose now that Au is once again active. If
the reenable condition would not require Cd to be
IDLE, Bu would be reenabled causing the same loop to
happen once again. Note that in this case Cd will be
active before Bu causing this port to continue to be
disabled and avoiding the jamming situation (Figure
55) gives a formal specification of the jabber function).

6.1.10 JABBER FUNCTION

This design does not implement the jabber unit but it is
described here for completeness. IEEE 802.3 does not
mandate this feature, but it is "Strongly Recommended". The jabber function in the HUB protects the network from abnormally long transmissions by any node.
Two timers TI, T2 are used by the JABBER function ..
They may be implemented either as local timers (one
for each HUB port) or as global timers shared by all
ports. After detecting an input active, tim~rs 11, T2

1-132

231422-96

Figure 54. Jabber Function

inter

AP-236

Power On

.... Walt for Input active.

____

.:!~~EE ~~TEI!.

___ _

• stort_Jobber TIme 1

.... Input Is active, activate timers Tl, T2 •
If Input goes Idle, then It was a

• start_Jobber TIme 2

normal transmission. Otherwise If

jabber Timer 1 expires, the transmissIon
Is Illegal. Start generating collision
pott.rn In stat. JABBER JAM •
.... Variable probation_alternative indicates
two possible ways of implementing the function.
Implementation of either one Is allowed.
«Jobb.rTlm. Ldon.+ INPUT(UPPER) = Idl.)
.INPUT(X) = ocllv.
'-----;==::;~=~;+~(;pr;o~bo~I:;o::n-~oJternotive * INPUT(X) = idle}

Condilions for going to stat. JABBER SHUTOFF
- 12 expires.
-INPUT(UPPER) = Idl•• INPUT (X) = ocllv.
It maans thot the current HUB was

SHUTOFF by a higher hierarchy one.
This one will olso SHUTOFF with the

purpose that a jamming Input be
DISABLED

-INPUT (X)

at the lowest possible level.

=Idl.

Two alternatives are allowed:

Go bock to JABBER IDLE. or
go to the SHUTOFF stat ••
On slot. JABBER SHUTOFF. th.
Input Is disabled.
Input will be reenabled If input is active,
and the upper port Is quiet.

231422-99

Figure 55. Jabber State Diagram
6.1.11 HUB RECEIVER PROTECTION TIMER

On the end of a transmission, during the transition
from IDLE to high impedance state, the transmitter
will exhibit an undershoot and/or ringing, as a consequence of transformer discharge. This undershoot/
ringing will be transmitted to the receiver which needs
to protect itself from false carriers due to this effect.
One way of implementing this protection mechanism is
to implement a blind timer, which upon IDLE detection will "blind" the receiver for a few microseconds.
Causes of the transmitter undershoot/ringing:
1. Difference in the magnitudes of the differential output voltage between the high and the low output
stages.
2. Waveform assymmetry due to transmitter jitter.
3. Transmitter and receiver inductance (transformer
L).

All the described elements will contribute to energy
storage into the transfonner inductor, which will discharge during the transition of the driver to high impedance.
The blinding timer is currently defined to be from 20 to
30 microseconds for the HUBs, being from 0 to 30 microseconds for the nodes (optional). The 82588 has
built-in this function. It won't receive any frames for an
inter-frame-spacing (IFS) from the idle detection.
6.1.12 HUB RELIABILITY

Since the StarLAN HUBs form focal points in the network, it is important for them to be very reliable, since
they are single points of failure which can affect a number of nodes or can even bring down the whole network. StarLAN !BASES draft requires HUBs to have
a mean time between failures (MTBF) of at least 5
years of continuous operation.

4. Two to three microseconds of IDLE pattern.

1-133

AP-236

7.0 SOFTWARE DRIVER

7.1.1 DOING 1/0 ON IBM PC

The software needed to drive the 82588 in a StarLAN
environment is not different from that needed in a generic CSMA/CD environment. This section goes into
specific procedures used for operations like TRANSMIT, RECEIVE, CONFIGURE, DUMP, ADDRESS
SET-UP, etc. A special treatment will be given to interfacing with the IBM PC-:--DMA, interrupt and I/O.

The safest way to use the PC monitor as an output
device and the keyboard as the input device is to use
them through DOS system calls. The following is a set
of routines which are'handy to do most of the I/O:
key$stat
-to find out if a new key has been
pressed
keyin$noecho -to read a key from the keyboard
-to display a character on the screen
char$out
msg$out
-to display a character string on the
screen
-to read in a character string from the
line$in
keyboard

Since all the routines were written and tried out in
'PLM-86 and ASM-86, all illustrations are in these languages.
The following software examples are pieces of an 82588
exerciser program. This program's main purpose was to
exercise the 82588 functionality and provide the functions of traffic generation and monitoring. By such the
emphasis was on speed and accuracy of statistics gath,
ering. '

The exact semantics and the protocol for doing these
functions through DOS system calls is shown in the
listing in Figure 56. Refer to the DOS Manual for a
more detailed description. To make a DOS system call,
register AH of 8088 is loaded with the call Function
Number and then, a software interrupt (or trap) 21 hex
is executed. Other 8088 registers are used to transfer
any parameters between DOS and the calling program.
The code is written in Assembly language for register
access. Let us see an example of the 'msg$out' routine:

7.1 Interfacing to IBM PC
The StarLAN board interfaces to the CPU, DMA controller and the interrupt controller on the IBM PC system board. The software to operate the 82588 runs on
the system board CPU. The illustrated routines in this
section show exactly how the software interface works
between the system resources on the IBM PC and the
StarLAN board.

lds dX,STRING_POINTER
mov ah,09h
int 21h

load pointer to string in reg. ds:dx
9
function number for string o'p
DOS System Call

=

These procedures are called from another module, written in a higher level language like PLM-86. The parameters
are transferred to the ASM-86 routines on the stack.
Examples of using the I/O routines:

=

KEY_STATUS
key$stat;
NEW_KEY = keyin$noecho;
call line$in(@LINE_BUFFER) ;
call char$out (CHAR_OUT) ;
call msg$out(@('THIS IS A MESSAGE.$'));

"
/*
"
/*
/*
/*

1-134

*'0'
*'*'

INQUIRE KEYBOARD STATUS
INPUT NEW KEY
STRING INPUT
"
TO OUTPUT CHAR_OUT ON SCREEN*,
OUTPUT STRING
NOTE $ TERMINATOR

intJ

AP-236

/ ... -------------- ------ -------------------------- - --- -- -------------------- -_ ... I

Deolara.tions for external IBM PC 110 routines

1*

.. I

/. ------:-- ---------------------------------------------------;--- ------------- ... I

keySstat: prooedure byte external:
end keyS stat :

I

* key status routine • /

::si~;$~~~~~O~~~oedure byte external:
oharSout: prooedure(ohar) external:
deolare ohar byte:
end charS out :

/* oonsole input routine . . I

I' oonsole output routine 'I

msgsout: prooedure(msgSptr) external:
declare msgSptr painter:
end msgSout:

I ' oonsole string output routine

l1neUn: prooedure(lineSptr) external:
deolare l1neSptr pOinter:
end l1neSin:

I ' console string input routine

Assembly Language implementation of the routines
STITLB(IBM/PC

DOS CALLS PROCEDURES)

HAIlE

DOSPROCS

OOROUP
CGROUP

GROUP
GROUP

DATA
DATA

SEGMENT WORD PUBLIC 'DATA'
ENDS

Dos
CoDE

EQU

DATA
CODE

21R

SEGMENT WORD PUBLIC 'CODE'
ASSUME CS: CGROUP, DS : OOROUP

231422-58

CHAR$OUT: PROCEDURE(CHAR) EXTERNAL:
DECLARE CHAR BYTE:
END CHAR$OUT:
Outputs character to the screen.
DOS system call 2
CHAR
CHAROUT

CHAROOT

EQU
PUBLIC
PUSH
MOV
MOV
MOV
INT
POP
RET

[BP+41

PROC
NEAR
CHAROUT
BP
BP,SP
DL,CHAR
AH.2
DOS
BP
2
ENDP

STACK.
+------+

!

CHAR

!

x

+------+
lIP 10 I
+------+

x-1

lIP hi

x-2

!
+------+
IBP 10 !

x-3

+------+

IBP hi I x-4

<--SP

+------+

KEYINSNOECHO: PROCEDURE BYTE EXTERNAL:
END KEYIN$NOECHO:
Reads character withcut echOing to display
KEYINNOECHO PROC
PUBLIC
MOV
INT
RET
KEYINNOECHO ENDP

NEAR

KEYINNOECHO
AH,8
DOS

(DOS call 8)

Figure 7-56. I/O Routines for IBM/PC

Figure 56. 1/0 Routines for IBMIPC

1-135

(continued)

231422-59

intJ

AP-236

IISGSOUT: PROCEDtJRE(IISGSPTR) EXTERNAL;
DECLARE IISGSPTR POllITER;
END IISGSOUT;
/. NOTE: IIESSAG]! IS TERliINATED WITH A DOLLAR SIGN • /
IISGSPTR is double word pOinter SEG:OFFSET
IISG_L
IISG-H.
HSGOUT
PUBLIC
PUSI!
1I0V

IIOV
PUSI!
IIOV
1I0V

IIOV
INT
POP
POP
IISGOUT

RET

-.v

~

[BP+41
[BP+61

PROC
IISGOUT

NEAR

BP
BP,SP
DX,IISGJ.
OS
AX,IISU
DS,AX
AII,9
DOS
'OS
BP

(DOS oall 9)

4

ENDP

LINE SIN : PROCEDURE(LINESPTR) EXTERNAL;
DECLARE LINESPTR POINTER;
END LlNESIN
[BP+41
[BP+61

LlNEIN

PROC
NBAR
PUBLIC· LINEIN
PUSI!
BP
IICV
BP,SP
PUSI!
OS
IICV
AX,LlNE_H
IICV
DS,AX
IICV
DX,LlNEJ.
IIOV
AII,10
INT
DOS
POP
OS
POP
BP
4
RET
ENDP

(DOS oall 10)

231422-60

KEYSSTAT: PROCEDURE BYTB EXTERNAL;
END !tEYS STAT;
Indioates whether any keyboard key was pressed.
!tEYSTAT
PUBLIC

IICV

INT
RET
KEYSTAT

Com

PROC
NEAR
KEYSTAT
AII,l1
DOS

(DOS oall 11)

ENDP

ENDS
END

231422-61

Figure 56. I/O Routines for IBM/PC (Continued)

7.2 Initialization and Declarations
Figure 57 shows some declarations describing what addresses the devices have and also some literals to help
understand the other routines in this section.

Figure 58 shows the initialization routines for the IBM
PC and for the 82588. It also shows some of the typical
values taken by the memory buffers for Configure,
lA_Set, Multicast and transmit buffers.
.

1-136

intJ

AP-236

Following are some literal declarations that are used in the procedure examples
Following are some literal

prooedure examples

deolarations

that

are

used

in

the

deolare

cS_5BB
brd_port
pic_mask
p1c_oow2
dma.Jnask
dm!Lmode
dma31ff
dma_addr_l
dma_bo_l
dm!LaddrJLl
dma_addr_3
dm!Lbo_3
dma_addrh_3
dma_on...l
dmB._oD_3

dm!LofLl
dma_off_3
enable_B8B
seoLp1oo
t~d1r
r~d1r

dma_rx_mode_l
dma_=_mode_3
dm!Ltx_mode_l
dma_tXJ\ode_3

literally '0300h'
/' B25BB COMIIAND/ STATUS
'/
literally '0301h'
/' DIIA/INTERUPT BNABLE PORT
literally '021h'
/' B259A IIASS: REGISTER
literally '02Ch'
/' 8259A COMIIAND WORD 2
literally 'Oab'
/' 8237A IIASS: REGISTER
literally 'Obh'
/' B237A HODE REGISTER
literally 'Och'
/' 8237A 1ST/2ND BYTE FLOP
literally '02h'
/, 8237A ClIANIIEL 1 ADDR. REG.
11 terally '03h'
/' 8237A ClIANIIEL 1 BYTE COUNT
literally '083h'
/' ClIANIIEL 1 PAGE REGISTER
literally '06h'
/' 8237A ClIANIIEL 3 ADDR. REG.
literally '07h'
/' 8237A ClIANIIEL 3 BYTE COUNT
literally '082h'
/' CI!AlINEL 3 PAGE REGISTER
literally 'Olh'
/' START ClIANIIEL 1
literally , 03h '
/' START CIIAlIIIEL 3
literally '05h'
/' STOP ClIANIIEL 1
literally '07h'
/, STOP ClIANIIEL 3
literally 'Odfh'
/' UNIIASS: INTERRUPT LEVEL 5
literally '065h'
/' SPECIFIC EOI LEVEL 5
literally
'1 '
/' MEHORY TO 82588
literally
'0'
/, 825BB TO HEHORY
literally '045h'
/' RlI: ON ClIANIIEL • 1
literally , 047h '
/' RlI: ON CIIAlIIIEL • 3
literally '049h'
/' TX ON ClIANIIEL • 1
literally '04bh'
/' TX ON ClIANIIEL i 3

'/
,/
'/
'/
'/
'/
,/
'/
'/
'/
'/
'/
'/
'/
'/
,/
'/
'/
'/
'/
'/
'/
'/
'/

231422-62

Figure 57. Literal Declarations

Initialization Routines

Initialization routines
/' SYSTEH INITIALIZE '/
sys_1n1t: procedure;
oall set$1nterrupt Cl3,1ntr_58B);
/' BASE B, LEVEL 5
'/
output(p1o_maak) - 1nput(p1o_mask) and enable_B88; /' ENABLE 588 INTERR. '/
output(p1o_oow2) seo1_p1co;
/' ACXS PENDING INTBRR'/
wr_ptr, rd.-ptr, fifoont-O;

/' RESET STATUS FIFO

'/

, •••• *** •••••••••••••••••••••••••••••••••••••••••••• ,
/' CONVERT SEG:OFFSET FORIIAT TO 20 BIT ADDRBSSES
/' FOR ALL THE BUFFERS
/

'/
'/
/

...................................................

1aset_dm!Laddr
cnf_dma_addr
dmp_dm!Laddr
mC_dma_addr
tX_dm!Laddr
do 1-0 to 7 ;

- convert_20b1t_addr (@:l.a_set_bufL5B8(0) ) ;
- conv.ert_20b1t_addr(@Conf:l.g_BB8(0»;
oonvert_20b1t_addr (lIldumpJrufL588 (0» ;
- convert_20b:l.t_addr (@mult:l.oastJrufL5B8(0)) ;
- oonvert_20b1t_addr(@t~ffer_5B8(0» ;

rx_dm!Laddr(1)-oonvert_20b1t_addr(@r~buffer(1)

end;
output (brd_port)-Offh;

.buff(O»;

/' ENABLE DIIA AND INTERRUPT DRIVERS ,/

end ays_1n1 t ;
B25BB initialization
1n1t_588: prooedure:
conf1g_58B(00)
conf1g_588(01)
conf1g_588(02
conf1g_5B8(03)
conf1g_588(04)
oonf1g_58B(05)
oonf1g_58B(06)
conf:l.g_588 (07)
conf:l.g_58B(08)
conf:l.g_588(09)
conf:l.g_58B(l0)
oonf:l.g_588(1l)

- 10;
= 00:
- OOOOlOOOb;
- buff_len/4;
- OOlOOllOb;
- OOOOOOOOb:
- 96;
- 0;
- 1l1lOOlOb;
- OOOOOlOOb;
- 10001000b;
- 64:

/' TO CONFIGURE ALL 10 PARAHBTERS

'/

/'
/'
/'
/'
/,
/'
/,
/'
/'
/'

'/
'/
'/
,/
'/
'/
'/
'/
,/
'/

HODE 0, 8 HBZ CLOClt, 1 HE/S
RECEIVE BUFFER LENGTH
NO LOOPBACX, ADDR LEN - 6, PREAMBLE - 8
DIFFERENTIAL MANCHESTER - OFF
IFS - 96 TCLK
SLOT TIME - 512 TCLK
HAll:. NO. RETRIES - 15
MANCHESTER ENCODING
INTERNAL CRS AND CDT, CRSF - 0
HIN FRAME LENGTH - 64 BYTES - 512 BITS

Figure 58. Initialization Routines

1-137

231422-63

inter

AP-236

1a...set_buff_555(O)
1a...setJlufC588(l)
1a_setj>ufC555(2)
1a_setJluff_585(3)
1a...setJluff_588(4)
1a...setJluff_588(5)
1a...set_uf:C588(6)
1a...setJlufC5BB(7)

-

6;
0;
OOOh
041h
OOOh
OOCh
OOOh
OOOh

mult1oast_bufC5BB(OO)
mult1oastJlufC5BB(Ol)
mult1oastJlufC58B(02)
mult1oastJlufC5BB(03)
mult1oasLbuff.5BB(04)
mult1oastJluff.5BB(OS)
mult1oe.stJlufC55B(06)
mult1oastJlufC5BB(07)
mult1oastJluff.5BB(OB)
mult1oastJluff.5BB(09)
mult1oastJlufC5BB(10)
mult1oastJluff.58B(1l)
mul tioe.stJlufC5BB (lB)
mult1oastJlufCS88(13)

- 12;
- OOh
- llh
- 12h
- 13h
- 14h
- 15h
- 1Bh
- 21h
- 2ah
- 2Sh
-24h;
- 25h;
- Bah;

tzJ>uffer.5BB(OO) - t,,-frame.len mad 256;
tzJ>uffer_5BB(Ol) - t"-frame.len / 256;
;~~~:~=ggm:~
INITIAL DESTINATION ADDRESS - 110(1) ' /
tzJ>uffer_58B(04) - 01Sh;
tzJ>uffer.5BB(05) - 014h;
tzJ>uffer.5B8(06) - 015h;
tzJluffer.588(07) - 016h;

: gm;

/'

. end 1n1 t.5B8;

231422-64

Figure 58. Initialization Routines (Continued)

fourth parameter = pointer to a 20 bit
addre'ss of the
memory buffer
(=@CONFIG.588.ADDR)

7.3 General Commands
Operations like Transmit, Receive, Configure, etc. are
done by a simple sequence of loading the DMA controller with the necessary parameters and then writing
the command to the 82588.

The second statement writes l2h to the command register of the 82588 to execute a Configure command on
channell.

Example: Configure Command

When the command execution is complete (successfully
or not), 82588 interrupts the 8088 CPU through the
8259A, on the system board. This executes the interrupt service routine, described in section 7.5, which
takes the epilogue action for the command.

To configure the operating environment of the 82588.
This command must be the first one to be executed
after a RESET.

oall
DMA.LOAD(1,1,12,@CONFIG.588.ADDR) ;
output (CS.588) = 12h;
The first statement is the prologue to' the configure
command to the 82588 which calls a routine to load
and initialize the DMA controller (or the desired operation. This routine is described in section 7.4. The parameters for DMA_LOAD are:

first parameter = 82588 ohannel
number ( = 1)
seoond parameter = direotion ( = 1,
memory > > 82588)
third parameter = length of DMA
transfer ( = 12)

Most operations are very similar in structure to Configure. The 82588 Reference Manual describes them in
detail. Figure 59 shows a listing of the most commonly
used operations like:

CONFIGURE

INDIVIDUAL·ADDRESS (IA)
SET·UP
TRANSMIT
MULTICAST·ADDRESS (MC)
SET·UP
DIAGNOSE
RECEIVE (RCV)-ENABLE
DUMP
RECEIVE (RCV)-DISABLE
TDR
. RECEIVE (RCV) -STOP
RETRANSMIT
READ-STATUS

1-138

AP·236

1a_set: prooedure publ1o:

/' COl!MAND - 01 ,/

00.11 clmlLload(om(Lohannel, tx_d1r, 8,@1aset_clma_addr) :
/'

SE~

DIIA Cl!AllllEL 0 01\ 1 W TRANSFER FROII IIEIIORY

W THE 82588. 1aset_dma_addr VARIABLE SWRES THE
20

BI~

POINTER W THE INDIVIDUAL ADDRESS BUFFER

'/

if omuffer_5BB(00) • low(buffer_len);
tlLbuffer_5BB(01) • h1gh(buffer_len);
oall dmlLload( Omd.-ohe.nnel, tlLd1r , 1536 ,@tlLdmlLaddr) ;
1£ omd..ohe.nnel then output (OS_8B8) • 14h;
elsa output(os_5B8) • 04h;
end transm1 t ;

231422-65

Figure 59. General Commands

1-139

AP-236

tdr: prooedure publiO;

/" COIIMAND - 05 */

if OlIld_ohannel then output (os_6B8) - lSh;
else output(os_588) - 05h;
end tdr;
/* ---------------------------------------------------------------:--;---------*'

dump_S8B: prooedure publ1o;

'" COIIMAND - 08 "'

oall. dm",--load( amd_ahannel, rZ-dir ,84, Cld.mp_~addr) ;
i f amcLOOannel then output (os_688) - lSh;
else autput(os_588) - OSh;
end dump_S88;

'* --------------------------------..-----------------------------------------*

diagnose: prooedure publ1o;

I

/" COIIMAND - 07 "/

i f OlIld_ohallllel then output (os_588) - 17h;
else output(os_58B) - 07h;

end diagnose;

/ * --------------------------.... ----------------------------------------------rov_enable: procedure (ohannel ,buffer_no ,len) publio;

*'

/" COIIMAND - 08 "/

deolare ohannel ~e;
deolare len word;
deolare buffer~o ~e;
oall dma_load(OOannel, rz_dir,len,iI1'Z-dm",--addr(buffer_no));
;is~~~~~~S~~~) o~t~:; (os_S88) - 18h;

/ * --------------------------------------------------------------------------* /
rev_disable: prooedure publio;

/* COIIMAND - 10 ./

enable_rov-O;
output (os_S88) -OalL;
end rev_disable;

231422-66

/. -------------------------------------------------------------------------- */

rev_stop: prooedure publio;

'" COIIMAND - 11 "/

ene.b18_rcv-O;
output(os_58B)- Ohh;

end rev_stop;

/. ----------------------------------------------------------T--------------- *'
retransmit: prooedure publio;

'" COIlllA1lIl - 12 "'
oall dmaJoad(amd_ohannel, tz_dir, 1538, ct1:z-dm",--addr) ;
i f amcLohannel then output (os_688) - 100; .
. else output(os_58B) - Ooh;

end retransmit;

'*--------------------------------------------------------------------------*'
abort: procedure publio;

'" COIIMAND - 13 "'

:ir:~~~s~:~~;( ~~;
end abort;

'* --------------------------------------------------------------------------*'

reset_SB8: procedure publio;

'" COIIMAND - 14 "'

enable_rev-O;
output(os_SB8) - 1eh;
oall oonfig;
end resat_s88;

231422-67

F.igure 59. General Commands (Continued)

1·140

inter

AP-236

7.4 DMA Routines
DMA_LOAD procedure is used to program the
8237A DMA controller for all the operations requiring
DMA service. It also starts or enables the programmed
DMA channel after programming it. Figure 60 shows

the listing of this procedure. It accepts 4 parameters
from the calling routine to decide the programming
configuration for the 8237A. The parameters for
DMA_LOAD are: Channel; direction, buff_len, and
buff_addr.

Convert1ng a pOinter SEG:OFFSET to a 20 llit address
oonvert_2Dllit_addr: procedure(ptr) dword publio:

deola.re

ptr

po1nter,

ptr_addr

pOinter.

f;~d20~~~e~w~~~_addr) (2)

word:

ptr_addr-@ptr :
ptr_20llit-shl((ptr_20llit :-wrd(l» ,4)+wrd(0):
return(ptr_20ll1t) :
end oonvert_20ll1t_addr:
IBII/PC DIIA loading prooedure
dmB.-lcad: prooedure (ohannel. direction • buff_len .lluff_addr) reentrant publio:
deolare
deolare
deolare
deolare
deolare

channel byte:
direction byte:
bufClen word: .
llufCaddr pcinter:
(wrd llased llufCaddr)(2)

/' CIIANIIEL •• 0 or 1
'/
/' O-RX, 588 -. MEII: lon, IIEII -. BBB ,/
/, BYTE COUNT
'/
/' BUFFER ADDR IN 20 BITS FORM
'/

word;

channel-channel and 1:

/' GET LEAST SIGNIFICANT BIT

'/

if ohannel-O then
do:

/' EXECUTE COIIIIAND ON CIIANIIEL 1

'/

/' CLEAR FIRST/LAST FLIP-FLOP

'/

~~t~;~:~!:6f)

- 0:

then output(dma_mode)-dma_rJUllcde_l: /' DIRECTION BIT, TELLS
else output (dma.Jllcde)-dma_tx--",ode_l :
/' TRANSIlIT OR RECEIVE
cutput(dma_addr_ll - lcw (wrd(O»:
/' LOAD LSB ADDRESS BYTE
cutput(d.ma.-addr_l) - high(wrd(D»:
/, LOAD IISB ADDRESS BYTE
cutput(dmB.-addrlLl) - low (wrd(l»:
/' LOAD PAGE REGISTER
output (dma_llo_l)
- low (buff_len):
/' LOAD LSB BYTE COUNT
cut put (dlna.-llc_l)
- high(bufClen):
/' LOAD IISB BYTE COUNT
cutput(dmB.-mask) - dmB.-on..l:
/' START CllANllBL.l
end:
else do:
/' SAllE AS BEFORE FOR CllANllBL 3

'/

'/
'/
,/
'/
,/
'/
'/
,/

~~t~~;~~o!:6f)

- 0:
then cutput(dma.Jllode)-dmB.-rJUllcde_3:
else cutput(dma_mode)-dma_tx--",ode_3:
cutput(dma_addr_3) - lcw (wrd(O»:
cutput(dma_addr_3) - high(wrd(O)):
cutput(dmB.-addrh_3) - low (wrd(l»:
cutput(dmaJ>c_3)
- low (llufClen):
cut put (dmaJ>c_3)
- high(llufClen):
cutput(dma_mask) - dmB.-cn..3:
end:

end dma...load:

231422-68

Figure 60. DMA Routine

1-141

inter

Ap·236

. One peculiarity about this procedure is that in order to
speed up the DMA step-up, this procedure doesn't get a
pointer to the buffer, but a pointer to a 20 bit address in
the 8237 format. The 8088/8086 architecture define
pointers as 32 bits seg:offset entities, where seg and offset are 16 bit operands. By the other hand the IBM/PC
uses an 8237A and a page register, requiring a memory
address to be a 20 bit entity. The process of converting
a seg:offset pointer to a 20 bit address is time

consuming and could negatively affect the performance
of the 82588 driver software. The decision was to make
the pointer/address conversions during initialization,
considering that the buffers are static in memory (essentially removing this calculation from the real time '
response loops).
Figure 61 is a listing of the DMA-LOAD procedure
for the 80188 or 80188 on-chip DMA controller. It has
the same caller interface as the 8237A based one.

dma_Ioad: procedure(channel ,direction, trans_Ien,'buff_addr) reentrant:
/* To load and start the

80186 DMA controller for the desired operation */

dma_rx~ode
literally '1010001001000000b': /* rx channel */
/* src=IO, dest=M(inc), sync=src, TC" noint, priority, byte */

declare

dma_t~ode
literally '000011010000000b': t* tx, channel */
/* src-M(inc), dest-IO, sync-dest, TC, noint, noprior, byte */

declare

declare
declare
declare
declare

channel byte:
direction byte:
trans_len word:
buff_addr pointer:

'*

/* channel
/*

o -

*/

rx, S88 -> mem: I - tx, mem -> S88 */
/* byte count
*/
/* buffer pointer in 20 bit addr. form
*/

declare (wrd based buff_addr)(2) word:
do case channel and OOOOOOOlbl
do case direction and OOOOOOOlb:
do:
t* channel 0, S88 to memory */
output (dma_O_dpl) =wrd(O):
out put (dma_O_dph) - wrd(l):
output(dma_O_spl) - Ch...A388:
output (dma_O_sph) - 0:
output (dma_O_tc)
- trans_len:
output (dma_O_cw)
- dma.J'~ode or 0006h; /* Start DMA chI
end;
do;
1*
output(dma_O_dpl)
output (dma_O_dph)
ou tpu t (dma_O_spl)
outpu~(dma_O_sph)

'ou tpu t (dma_O_t c)
output (dma_O_cw)
end;
end;

° *1

channel 0, memory to' 588 */
- cl!....,,-S88;

=

0:

- wrd(O);
-wrd(!);
~

trans_len;

-

dma_t~ode

or 0006h: /* Start DMA chI 0 *t
231422-69

Figure 61. 80186 DMA Routines

1-142

inter

AP-236

do case direction and 00000001b;
do;
f* channell 588 to memory *f
output(dma_l_dpl)
wrd(O);'
output (dma_l_dph)
wrd(l);
output(dma_l_spl) = clLb_588;
outputCdma_l_sph) _ 0;
outputCdma_l_tc)
= trans_len;
output (dma_l_cw)
= dma_r~ode or 0006h; f* Start DMA chi 1 *f
end;
do;
f*
output (dma_l_dpl)
output (dma_l_dph)
output(dma_l_spl)
output (dma_l_sph)
ou t pu t (dma_l_t c)
output (dma_l_cw)
end'

end;

channel 1, memory to 588 *f
- clLb_588;

=

o·

- ~d(O);
- wrd(l);
trans_len;
dma_t~ode

or 0006h; f*

Star~

DMA chi 1 *f

.

end;

231422-70

Figure 61. 80186 DMA Routines (Continued)

7.5 Interrupt Routine
The interrupt service routine, 'intr_588', shown in
Figure 62, is invoked whenever the 82588 interrupts.
The main difficulty in designing this interrupt routine
was to speed its performance. Fast status processing
was a basic requirement to be able to handle back to
back frames.

The interrupt handler will read 82588 status, and put
them into a 64 byte long EVENT_FIFO. Those
statuses are going to be used in the main loop for updating screen counters. All the statistics are updated as fast
as possible in the interrupt handler to fulfill the backto-back frame processing requirement.
The interrupt handler is not reentrant, interrupts are
disabled at the beginning and reenabled on exit.

1-143

AP-236

Interrupt service routine
intx_S8e : procedure interrupt 13;

deolare stat
event

byte.
byte,

i
(stO,.tl,st2,st3)
rx_stO
rx_st 1

byte,
byte,
byte.

byte;

/ ' FOLLOWING LITERALS HAVE THE PURPOSE OF ENAllLE ACTING
ON EITHER CHANNEL 1 OR 3 SELECTIVELY

"

declare
literally 'if omd_ohannel
then output(dma_mask)-dma_off_3;
else output(dma._mask)-dma_off_l'.
literally 'if rx_ohannel
then output(dma_mask)""dma_off_3;
else output(dme._mask)-dma._off_l'.

'if cmd_channel
then output(oB_688) .. lCh;
else output(os_5SB)"Ooh·.
'1f cmd_Channel
then output(os_68B)-14h;
else output(os_68B)",,04h';
;, DISABLE INTERRUPTS
*/
/. NO IN'l'ERR. NESTING
*/
I' RLS 68B PTa. START 0 *1

disable;
output(cs_688)

-Ofh:

event_fifo(wr_ptr). atO. stO ... 1nput(os_588):
event_f1fo(wr_ptr). stl. stl-input(os_668);
event_flfo(wr_ptr) . st2, st2-1nput (os_688) ;
event_flfo(wr_ptr). st3, st3 ... 1nput(OS_688);

/'
/'
/'
/'

wr_ptr-(wr_ptr+l) and Ofh;
flfocnt-(flfoont+1) and Ofh:

/' INCREMENT FIFO
/' COUNTERS

'/

event-stO and Ofh;

/' GET EVENT- FIELD

'/

output (os_S88)-80h:

/' ACKNOWLEDGE 82688
/' INTERRUPT

'/

READ 82588 STATUS
REGISTERS, PASSING
THEM TO THE MAIN
PROGRAM ON THE FIFO

'/

'/
,/
,/
'/

'/

231422-71

do oase event;
ev_oo
eV_01
ev_02
eV_03
ev_04

~t op_cmd_dma.;
st op_cmd_dma;
stop_omd_dma:
do:
stop_cmd_dma:

1* NOP COMMAND
I * lA_SETUP, STOP DMA

*I

/' CONFIGURE, STOP DNA
I * MULTICAST. STOP DMA
I' TRANSMIT DONE

'/
*I
*1.

*I

/' CHECK IF THERE WAS A COLLISION AND IS NOT THE
MAX COLLISION

'/

stat-(st2 and lOOOOOOOb) or (stl and OOlOOOOOb):
U (stat-60h)
then do;
I * RETRANSMIT
*I
call dma._load(cmd_channel, tx_d1r, 1536,@tx_dma._addr) ;
1ssue_rtx_cmd ;
,/
I· UPDATE STATISTICS
tota.l_tx_count .. total_tx_count+1 ;
coll_ont(l7) - ooll_ont(17) + 1; I'TOTAL COLLII'I
bzuLtx_oount .. bad._tx_oount + 1;
end;
else do;
i f in_loop
/' EXECUTING TRANSMISSIONS IN LOOP ' /
then do:
/ '" RE ISSUE TRANSMIT COMMAND
*/
oall dma_loadCcmd_ohannel. tX_dlr .1536,@t]cdma_addr
1ssue_tx_cmd:
total_ t::lcoount-total_tx_count+ 1:
end;
U (st2 and OOlOOOOOb) - 0
1* BAD TRANSMIT$o/
then do;
bad_t:lCOOunt .. bad_tx_oount + 1;
/' INCREMENT UNDERRUN COUNTER
'/
tmp-sor( tmp: -st2, 1) :

;~~~iMi~~~i ~iss~bmBR

end;

tmp-scr(tmp,l) :
lost_ots-lost_cts plus 0;
/' INCREMENT LOST CRS COUNTER
tmp-sor(tmp, 1):
lost_ors-lost_crs plus 0;
if (stat-OAOh) /, INC COLLISIONS COUNTER
then ooll_ont(l7) - ooll_ont(17) + 1:
end:

/' INCREMENT DEFER COUNTER
tmp-sol( (tmp: -stl) ,1):
tx_defer-tx_defer plus 0;

end;

'/
'/

'/

'/

231422-72

Figure 62. Interrupt Routine

1-144

inter

AP-236

ev_OS: stop_cmd_dma;
Bv_06: stop_cmd_dma;
ev_07: stop_cmd_dme.;
ev_08:

/.. TDR COMMAND

I

STOP DMA

/, DUMP COI!HANll, STOP DHA
/' DIAGNOSE CHD, STOP DHA
I" RECEIVED FRAME

.. /

'/
' /
.. /

do;
stop_rx_dma;
i-(current_buff+l) and OOOOOlllb; /' INC BUFFER NO. MOD 8'/
if ena.ble_rov<)O
/- IF RECEIVER IS ON
If.j
then do;

/.. PREPARE NEXT BUFFER • /

can dma_load(rx_channel,rx_dir,l632,@1'x_dma_addr(i));
if rJcchannel then output(os_6SS)- 16h:
else output(os_688)-08h;
rX_Duffer(i) .chaln_cnt-O;
end;

else 06011 rov_disable j

/, DISABLE RECEIVER

/, FIND ADDRESS OF END OF CURRENTLY RECEIVED BUFFER
/, BY CALC1lLATING IT WITH THE 82688 BYTE COtlNT REGS.
r,,-bufCoff-(shl(double(st2) ,8) or double(stl));
/' READ STATUS BYTES FROM MEMORY
rx_stO-rx_bufferCcurrent_buff). buf:f'Crx_huff_off-2);
rx_st l-rx_buffer(ourrent_huff) . buffCrx_buff_off-l) ;
/, UPDATE ACTUAL BUFFER SIZE
rx_buffer( current_buff) . actual_size-rx_Duff_Off;
r::Z:_Duffer( current_buff) . etC-rx_sta;
rx_buffer(ourrent_buff). Btl-rx_Btl;
ourrent_huff-1;
/' UPDATB TOTAL RECEIVED BUFFERS

total_rcv _count-total_xcv_oount+ 1 :
/' UPDATE STATISTICS
if (n_stl and OOlOOOOOb)-O

'/
'/
'/
'/

'/

'/
'/

then do;
bad_rov_count-bad_rov_count+l;
/' INCREMENT NO END OF FRAME COUNTER
tmp-scr(tmp: -r,,_stO, 7);

,/

nO_Bof-no_eof plus 0;
/, INCREMBNT

SHORT FRAME COUNTER

tmp-sor( tmp, 1) ;
srt_frm-srt_frm plus 0;

/' INCREMENT RX OVERRUN COUNTER
tmp-scr(tmp:-rx_stl,l) ;

'/

'/

rx_over-rx_over plus 0;-·
/, INCREMENT ALIGNMENT ERROR COUNTER
tmp-sor(tmp, 2);

'/

alg_err-alg_Brr plUS 0;
/, INCREMENT eRC ERROR COUNTER
tmp-scr(tmp,1) ;
orc_err-oro_err plus 0;

'/

end;
end'

ev_09
ev_-10
ev_ll
ev_12

231422-73
/'

BV_09 REQUESTS ASSIGNMBNT OF A NEW BUFFER

'/

call allocate_new_buffer(not(rol(st3,l)) and OOOOOOOlb);
stop_rx_dma;
1* RECEIVE DISABLE
*1
stop_rx_dma;
I" STOP RECEIVE
.. /
do;
/.. RE-TRANSMIT DONE
.. 1
stat-(st2 and lOOOOOOOb) or (stl and OOlOOOOOb);

i f (stat-BOh)

then do:

/.. RETRANSMIT

*1

call dma_load(l, tx_dir,l636,@t,,_dma_addr);

1ssue_rtx_cmd;
colLcnt(l7) - ooll_cnt(l7) + 1;

total_tx_oount-total_tx_oount+1 ;
bad._tx_count-bad_tx_oount +1;
end;
else do:
if in_loop

then do;
1 * LOOP RETRANSMISSIONS
*/
call dma_load( cmd_channel, tx_d.1r, 1536.@tx_dIna_a
1ssue_t~cmd;

total_tx_oount-total_tx_oount+1 ;
end;
i f (stat-OAOh) /' MAX COLLISION

'/

then do;
coll_ont(l6) - ooll_cnt(l6)+l;
oolLcnt(l7) - coll_cnt(l7)+1;·

bad._tx_oount-bad_tx_count +1;
end;
I" UPDATE SPECIFIC COLLISION COUNTER

else

.. 1

coll_ont(stl and Ofh)
- ooll_cnt(stl and Ofh) + 1;

end;

ev_13:

:~::::i~~

end;
stop_cmd_dma;
stop_Omd_dma;

end:
/..

ACKNOWLEIXig 82S9A

/' EXECUTION ABORTED

'/

/' DIAGNOSE FAILED

,/

INTERRUPT

output(pio_ocw2)- seoi_pico;

/, SPECIFIC EOI FOR 8269

end intr_688;

'/
'/

231422-74

Figure 62, Interrupt Routine (Continued)

1-145

Ap·236

. APPENDIX A
STARLAN SIGNALS

1-146

Ap·236

82588

nco

RTS

(1)------

5pF

5 pF

(2)---

24 GAUGE
800 FT TWISTED PAIR WIRE
IN 25 PAIR BUNDLE

(.)~

231422-47
231422-55

Figure 63. StarLAN Signals

1-147

inter

AP-236

Eye Diagram (58ils), DIW Cable
Manchesler Encoded Signal
Transmission Distance ~ 0.8 Kit.
0
0
0
N

0
0

'"
0
0
0

>8
5'"

.",

'"z

0
0..
",0

'"
'"
Q:

(!)

~o
00

>?
0
0
0

.
0
0

'"I
0
0
0
N

I

0.0

0.2

0.4

0.6

O.S

1.0

TIME (~SEC)
231422-48

Figure 64. Received Signal Eye Diagram

1-148.

intJ

A~-236

APPENDIX B
802.3 1BASES MULTI-POINT EXTENSION (MPE)
As previously stated, one of the most important advantages of StarLAN is being able to work on already installed phone wires. This advantage is considerably diminished in Europe where numerous constraints exist
to the using of those wires:

Recently the StarLAN 802.3 !BASES task force has
been considering the extension of the StarLAN base
topology. This extension called MULTI POINT EXTENSION (MPE) is going to be developed to address
the previously described marketing requirements.

I. Wire belongs to local PTTs.
2. Not enough spare wires.

Currently no agreement has been reached by the
StarLAN task force on the MPE exact topology and
implementation. Multiple approaches have been presented, but no consensus met. It was decided though
that the MPE is going to be an addendum to the STAR
topology, and that its final specification will happen
after the approval of the current !BASES STAR topology (July 1986).

This same issue is raised when talking about small businesses where in a lot of cases no wiring closets and/or
spare wires are available.
In summary, in a lot of cases rewiring will be necessary,
in which case the STAR topology may not be the most
economical one.

1-149

__..._ - - THROUGH A HUB UPGRADABLE
TO THE FULL STAR LAN TOPOLOGY
(2500 m. MAX END-TO-END)
HUB COST ELIMINATED
IN SMALL TOPOLOGIES.
LOWER COST PER PORT
(UP TO 8 STATIONS PER PORT)

HUB

l

...
CONNECTION OPTIONAL,
NOT NEEDED FOR SMALL
TOPOLOGIES

"II

cO·
e

...
(II

en

PI

iii:

~
(J1

o

):0
"U
,

e

a:
"0

-~

I\,)
CI)

s·0
::J

en

en
LOWER COST.
TERMINALS ATTRACTIVE

o·

::J

FEWER CONNECTIONS TO
WIRING CLOSETS
231422-97

inter

AP-236

APPENDIX C
SINGLE DMA CHANNEL INTERFACE
In a typical system, the 82588 needs 2 DMA channels
to operate in a manner that no received frames are lost
as discussed in section 5.1.3. If an existing system has
only one DMA channel available, it is still possible to
operate the 82588 in a way that no frames are lost. This
method is recommended only in situations where a second DMA channel is impossible to get.
Figure 66 shows how the 82588 DMA logic is interfaced to one channel of a DMA controller. Two DRQ
lines are ORed and go to the DMA controller DRQ
line and the DACK line from the DMA controller is
connected to DACKO and DACKI of the 82588. The
82588 is configured for multiple buffer reception
(chaining), although the entire frame is received in a
single buffer. Let us assume that channel CH-O is used
as the first channel for reception. After the ENAble
RECeive command, CH-O is dedicated to reception. As
long as no frame is received, the other channel, CH-1,
can be used for executing any commands like transmit,
multicast address, dump, etc., by programming the
DMA channel for the execution command. The status
register should be checked for any ongoing reception,
to avoid issuing an execution command when reception
is active.

OROO
OROl
OACKO .
OACKl
82588

..,

OROn

lished, as shown in Figure 67. After this, the received
bytes start filling up the on-chip FIFO. The 82588 activates the DRQ.line after 15-FIFO LIMIT + 3 bytes
are ready for transfer in the FIFO (about 80 microseconds after the interrupt). The CPU should react to the
interrupt within 80 p.s and disable the DMA controller.
It should also issue an ASSIGN ALTERNATE BUFFER command with INTACK to abort any execution
command that may be active. The FIFO fills up in
about 160 p.s after interrupt. To prevent an underrun,
the CPU must reprogram the DMA controller for
frame reception and re-enable the DMA controller
within 160 p.s after the interrupt (time to receive about
21 bytes). No buffer switching actually takes place, although the 82588 generates request for alternate buffer
every time it has no additional buffer. The CPU must
respond to these interrupts with an ASSIGN ALTERNATE BUFFER command with INTACK. To keep
the CPU overhead to a minimum, the buffer size must
be configured to the maximum value of 1 kbyte.
If a frame transmission starts deferring due to the reception occurring just prior to an issued transmit command, the transmission can start once the link is free
after reception. A maximum of 19 bytes are transmitted
(stored in the FIFO and internal registers) followed by
a jam pattern and then an execution aborted interrupt
occurs. The aborted frame can be transmitted again.
If the transmit command is issued and the 82588 starts
transmitting just prior to receiving a frame then transmit wins over receive-but this will obviously lead to a
collision.

OACKn
OMA
CONTROLLER
231422-49

Figure 66. 82588 Using One DMA Channel

If a frame is received, an interrupt for additional buffer
occurs immediately after an address match is estab-

Note that the interrupt for additional buffer is used to
abort an ongoing execution command and to program
the DMA channel for reception just when a frame is
received. This scheme imposes real time interrupt handling requirements on the CPU and is recommended
only when a second DMA channel is not available.

1-151

intJ

Ap·236

REQUEST
ALT BUFF
INTERRUPT

ASSIGN
ALT BUFF
WITH INTACK

1

82588

~;

1

-.-J

I

I

:':==~~_-_!::B_O_~S_ _ _--;.·II____

,-

1

ADDRESS MATCH
ON FRAME
RECEPTION

1

. DMA CONTROLLER
MUST BE DISABLED
PRIOR TO THIS

rFIFO FULL

•
!::160~S-----+l'1

1

DMA CONTROLLER
MUST BE PROGRAMMED
FOR RECEPTION AND
ENABLED PRIOR TO THIS

231422-50
Figure 67. Timing at the Beginning of Frame Reception for Single DMA Channel Operation

1-152

AP-236

APPENDIX D
MEASURING NETWORK DELAYS WITH THE 82588
Knowing networks round-trip delays in local area networks is an important capability. The round-trip delay
very much defines the slot time parameter which by
itself has a direct relationship to network efficiency and
throughput. Very often the slot-time parameter is not
flexible, due to standards requirements. Whenever it is
flexible, optimization of this number may lead to significant improvement in network performance.
Another possible usage of the network delay knowledge
is in balancing the inter-frame -spacing (IFS) on broadband networks. On those networks, stations nearer to
the HEAD-END hear themselves faster than farther
ones. Effectively having a shorter IFS than stations far
from the HEAD-END. This difference causes an inbalance in network access time for different stations at
different distances from the HEAD-END. Knowing
the STATION/HEAD-END delay allows the user to
reprogram the 82588 IFS accordingly, and by that balance the effective IFS for all the stations.

The 82588 has an internal mechanism that allows the
user to measure this delay in BIT-TIME units. The
method is based on the fact that the 82588 when configured for internal collision detection, requires that the
carrier sense be active within half a slot-time after
transmission has started. If this requirement is not fulfilled the 82588 notifies that a collision has occurred.
Thus it is possible to configure the 82588 to different
slot time values, then transmit a long frame (of at least
half a slot-time). If the transmission succeeds, the network round-trip delay is less than half the programmed
slot-time. If a collision is reported, the delay is longer.
The value of the round-trip delay can be found by repeating this experiment process while scanning the slottime configuration parameter value and searching the
threshold. A binary search algorithm is used for that
purpose. First the slot-time is configured for the maximum (2048 bits) and according if there was a collision
or not, the number changed for the next try. (See Figure 68)

1-153

Ap·236

8
2

5
8
8

TX

PROPAGATION DELAY
HEADEND

RX

• SCHEt.lE IS BASED ON THE F"ACT THAT THE 82588 EXPECTS RX CARRIER
TO BE ACTIVE ArTER 1/2 SLOT TIt.lE

=

K APPROXIt.lATION F"ACTOR

231422-98

Figure 68. Network Delay Measurement using the 82588

1-154

APPLICATION
NOTE

AP-320

November 1988

Using the Intel 82592 to Integrate
a Low-Cost Ethernet Solution
into a PC Motherboard

MICHAEL ANZILOTTI
TECHNICAL MARKETING ENGINEER

Order Number: 290189-001
1-155

AP-320

the LAN solution; e.g., system memory and DMA.
This leaves the 82592, the serial interface, and some
control logic as the only components required to complete a motherboard LAN solution.

1.0 INTRODUCTION
During the past several years office networking has become an increasingly efficient method of resource sharing for companies looking to increase productivity
while reducing cost. Networking allows multiuser access to a data base of files or programs v,ia a network
file server; it allows sharing of expensive peripherals;
e.g., laser printers; and it offers a greater degree of data
security by centralizing the hard disk and backup facilities. This type of network allows a user to concentrate
his resources; e.g., a high-capacity, high-performance
hard disk, at the network file server, allowing the other
nodes, or PC workstations, on the network to function
with limited or no mass data storage capability.

1.1 Objective
This Application Note presents the general concept of
integrating a Local Area Networking into a PC moth- '
erboard, and how the 82592 ,suits this purpose. The
design of the 82592 Embedded LAN Module, which
plugs into an Intel SYP301 motherboard (or any standard PC AT style motherboard), is explained in detail-providing a demonstration of an integrated Ethernet LAN solution.

As I,.ocal Area Networks (LANs) have become more
common in the office and in industry, some clear market development trends have emerged. Possibly the
most significant development in the LAN marketplace
is the concern for cost reduction. This need is driven by
intense competition between network vendors for market share. Today's .LAN marketplace requires low-cost,
simple network solutions that do not sacrifice performance. Another significant development in the LAN
marketplace is the acceptance of Ethernet, or a derivative (e.g.; Cheapernet or Twisted Pair Ethernet), as the
industry standard for high-performance LANs. Because of Ethernet's popularity, there is a great need for
cost 'reduction in this market.

1.2 Acknowledgements
For their contributions to this Application Note, and
for their work in developing the architecture of the
82592 Embedded LAN Module, I would like to acknowledge, and thank, Uri Elzur, Dan Gavish, and
Haim Sadger, of the Intel Israel System Validation
group; and Joe Dragony, of Intel's (Folsom) Data
Communications Focus Group.

2.0 THE EVOLUTION OF LAN
SOLUTION ARCHITECTURES

Personal computers (PCs) have also seen significant
changes over the past several years. PCs have become
firmly entrenched in the office. Their popularity, coupled with a highly competitive market, has compelled
PC vendors to both reduce costs for their LAN solutions and to attempt to distinguish their product from
the competition's. The means of this cost reduction
range from eliminating expensive hardware, such as
disk drives and their associated hardware,. to using
highly integrated VLSI devices that implement the
functions of a PC in a combination chip set containing
several devices. Differentiation has been achieved by
integrating peripheral functions, normally contained on
an external adapter card, into the main processor
board, or motherboard, of the PC. Video Graphics Array (VGA) and LAN connections are examples of this
strategy.
.
The Intel 82592 LAN controller is uniquely suited for
integration into a PC AT style motherboard. It meets
the demands of today's market by providing the PC
vendor (1) a means of reducing cost while maintaining
high performance, and (2) a path for differentiation. An
82592 integrated into a PC motherboard provides a
very low cost and very simple implementation because
,it uses the host system's existing resources to' complete

LAN solutions have undergone an evolution in architecture--from expensive and complex to more cost-efficient and streamlined. A definite trend in office networking can be seen, as these solutions permit the host
system to perform functions that were previously included in the LAN solution.
The first LAN solutions were usually intelligent buffered adapter cards, with a CPU, large memory requirements (up to 512 kB), firmware, a LAN controller, and
a serial interface. As networking became more prevalent in the office environment-linking PCs and workstations via Ethernet-this complex architecture
evolved into simpler and more streamlined nonintelligent, buffered adapters. In this architecture the CPU is
no longer part of t~e LAN solution; its processing power is supplied by the host system. This architecture does
not need memory to support a local CPU. Memory is
only needed to supply a buffer space to store data before moving it to system memory or onto the serial link.
The memory requirement for nonintelligent, buffered
architectures is typically 8 kBytes to 32 kBytes. The
firmware to boot the CPU is also no longer needed. The
evolution to a nonintelligent, buffered architecture has
resulted in significant cost savings and reduced complexity.

1-156

inter

AP-320

Significant increases in speed and processing power
have been made to PCs during the past several years.
This trend to higher performance host systems has allowed further streamlining of the LAN solution's architecture, resulting in even greater cost reduction and
simplification. This is accomplished by using host system resources whenever possible. A nonintelligent, nonbuffered architecture is the result. In this architecture,
the host system's memory and DMA are used by the
LAN controller. The complexity associated with buffered LAN solutions (e.g., supplying a dual-port arbitra-

tion scheme for local memory access by both the CPU
and the LAN controller) is reduced; this complexity is
removed from the LAN solution and returned to the
host system, which is designed for these complex tasks.
The result of this architectural optimization is a very
simple, low component count, cost-efficient solution for
a LAN connection. The 82592 Embedded LAN Module is the realization of this optimization. The trend to
optimization of LAN architectures is shown in Figure
1.

Intelligent Buffered Adapter

EJ

290189-1

Nonintelligent Buffered Adapter
Nonintelligent Non-Buffered Architecture
Embedded Module

290189-3

290189-2

Figure 1. Architectural Optimization of LAN Solutions

1-157

i~

AP-320

3.0 THE 82592 LAN CONTROLLER
3~1

• Internal and externalloopback
• Internal register dump
• A TDR mechanism
• Internal diagnostics

General Features

The 82592 is a second generation, CMOS, advanced
CSMA/CD LAN controller with a l6-bit data path.
Along with 'its 8-bit version, the 82590, it is the followon design to the 82588 LAN controller. The 82592 is
upwards software compatible from the 82588. The
82592 has two modes of serial operation, High Speed
Mode and High Integration Mode. In High Speed
Mode (up to 20 Mb/s) the 82592 couples with the Intel
82C50l to provide an all CMOS kit for IEEE 802.3
Ethernet applications. In this mode the 82592 can also
serve as the controller for Twisted Pair Ethernet (TPE)
applications. In High Integration Mode (up to 4 Mb/s)
the 82592 performs Manchester and NRZI encoding/
decoding, collision detection, transmit clocking, and receive clock recovery on chip; in this mode it can serve
as a controller for StarLAN and other midrange LANs.

For further information on the 82592, please refer to
the Intel Microcommunications Handbook.

3.2 Unique Features for Embedded
LAN Applications
The 82592 has several unique features that enable implementing a high-performance embedded LAN solu,tion with minimal cost and complexity.

The 82592 provides several features that' allow an efficient system interface to a wide variety of Intel microprocessors (e.g., iAPX 188, 186, 286,and 386) and industry standard buses (e.g., the IBM PC I/O channel
or the PS/2™ Micro ChanneI™). To issue a command to the 82592 (e.g., TRANSMIT or CONFIGURE) the CPU only needs to set up a block in memory
that contains the parameters to be transferred to the
82592, program the DMA controller to point to that
location and issue the proper opcode to the 82592. The
82592 and DMA controller perform the functions
needed to complete the command, with the 82592 interrupting the CPU when the command is complete. The
82592 has a high-performance, 16-bit bus interface, operating at up to 16 MHz. It also implements a specialized hardware handshake with industry standard DMA
controllers (e.g., the Intel 8237, 82380, and 82370) or
the Intel 82560. This allows for back-to-back frame reception, and automatic retransmission on collision'without CPU intervention. The 82592 FIFOs (Rx and
Tx) can have their 64 bytes divided into combinations
of 32/32, 16/48, 48/16, or 16/16.
The 82592 features a Deterministic Collision Resolution (DCR) mode. When a collisiori is detected while in
this mode, all nodes in a deterministic network enter
into a time-division-multiplexed algorithm where each
node has its own unique slot in which to transmit. This
ensures that the collision is resolved within a calculated
worst-case time. The 82592 also features a number of
network management and diagnostic capabilities; for
example,
• Monitor mode
• A 24-bit timer

Peripherals on a motherboard must compete for access
to the system bus. Because there is no local buffer for '
intermediate buffering of data, data transfers take place
in real-time over the system bus to the system memory.
A LAN controller must have a large internal data storage area to be able to wait for access to the system bus
while serial data is being received or transmitted. Without sufficient internal data storage, a LAN controller
cannot take advantage of the cost efficiency and simplicity of a non-buffered architecture. The 82592 has a
total of 64 bytes of FIFOs. This expanded FIFO section
allows the 82592 to tolerate long system bus latencies.
For example,' during a Receive (with the Rx FIFO
length configured to 48 bytes) the 82592 can tolerate up
to 38.4 ,""S of bus latency-the time from a DMA request to reception of a DMA Acknowledge from the
DMA controller-before the possibility of a data overrun occurring in a 10 Mb/s Ethernet application. Once
access to the system bus has been obtained, the 82592's
high-performance, l6-bit bus interface provides efficient data transfer over the system bus, thus reducing
the bus utilization load for a LAN connection on the
host system.
The 82592 features a specialiied hardware handshake
with industry standard DMA controllers. This hardware handshake between the 82592 and the DMA controller (on signal lines DRQ and EOP) relays the status
of a Receive or Transmit and allows for back-to-back
frame reception and automatic retransmission on collision without CPU intervention. This allows the 82592
and the DMA controller to perform these time-critical
operations in real-time without depending on the CPU
via an interrupt service routine, and without the time
delays inherent in such routines. For the 82592 Embedded LAN Module, this hardware handshake is enabled
by configuring the 82592 to the Tightly Coupled Interface (TCI) mode. Figure 2 shows details of the 82592's
TCI signals.

• Three l6-bit event counters

1-158

inter

AP-320

Transmit/Receive Status Encoding on ORQ and EOP
ORQ

EOP

0

Hi·Z

Idle

Status Information

1

Hi·Z

DMA Transfer

0

0

Transmission or Reception Terminated OK

1

0

Transmission or Reception Aborted

Tightly Coupled Interface Timings

DRQO,
DRQl
DACKO,
DACKl

~

'\.

'\.

--T23

-

T1D4

--I

§~

wR,Rfi

EOP
..... T1DS

Symbol

Parameter

I-

I2901e~-4

Max

Units

45

ns

CL = 50 pF

65

ns

CL = 50 pF

WR or RD Low to EOP Active

45

ns

Open Drain 1/0 Pin

EOP Float after DACKO
or DACK1 Inactive

40

ns

Open Drain 1/0 Pin

t23

WR or RD Low to DRQO
or DRQ1 Inactive

tl04

WR or RD High to DRQO
or DRQ1 Inactive

t105
t106

Min

..... T1DS

2.5

Figure 2. TCI Encoding and Timings

1·159

Notes

intJ

AP-320

These three features (FIFO depth, high-performance
bus interface, and TCI) allow the 82592 to operate successfully in a high-performance motherboard LAN
application. The application of these features will be
discussed further in Section 4.

schematics. The module consists of an 82592, two
20LIO PALs, and two 8-bit LS573 address latches that
combine to provide a 16-bit address latch. The module
contains no DMA unit or local memory.
The 82592 Embedded LAN Module is a simple; lowcost, low component count solution because it uses the
available system resources (DMA and memory) to provide for those functions normally added to a LAN solution. Removing DMA and local memory from a LAN
solution reduces cost and, complexity. Two host DMA
channels, one for receive and one for transmit, are
needed to support the module. The DMA interface
from the 82592 (through PAL B) is the standard combination ofDRQ, DACK and EOP. These three signals
also provide the TCI between the 82592 and the DMA
controller. The size of the memory buffer needed to
support the module depends'on the specific application
and the amount of free memory available; the buffer
size can be specified by the programmer.

4.0 SYP301 INTERFACE
This section will discuss the details of the Interface of
the 82592 Embedded LAN Module to the Intel
SYP301. The basic architecture will be presented, demonstrating that the 82592 Embedded LAN Module is a
low-cost, low component count Ethernet solution for
networking office PCs or .workstations.
The Intel SYP301 is compatible with the IBM PC
ATTM. It features an Intel 80386TM microprocessor,
running at 16 MHz, as its CPU. Its system bus is compatible with the standard PC AT I/O-channel bus.

4.1 Basic Architecture
Figure 3 shows the basic architecture of the 82592 Embedded LAN Module, and Figure 4 shows the module's

JI

ADDRESS BUS AO-15

,

LATCH

"
DATA BUS 00-15

LTCwt
DRQO
DRQl
DACK
EOP
INT

+

JI

(RECEIVE)
(TRANSMIT)
(BOTH CHANNELS)

DMA INTERfACE

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I~
cs

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INTRQ

....

lORD

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ADDRESS BUS AO-2 A5-9
PAL A
lORD

82592

"

OE

"

..

..

IOWR

lORD
IOWR

lolA BUS 00-15"
I'

290189-5

Figure 3. 82592 Embedded LAN Module Basic Architecture

1-160

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82592

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290189-48

N
0

inter

Ap·320

The two PALs (PAL A and B) provide two major junctions for the module: (1) address decode (PAL A), and
(2) interpreting the TCI from the 82592 (PAL B). PAL
A decodes addresses for CS to the 82592, OE for the
address latches, and an Enable/Disable of the LAN
module. PAL B interprets the TCI of the 82592. When
PAL B detects EOP from the 82592 during reception of
a frame (BOP indicates the last byte of the receive
frame) it loads the memory address of the last byte of

the receive frame (the byte count) into the Address
Latch at the time it is written into memory. This allows
back-to-back frame reception without CPU intervention, and will be covered in detail in Section 4.2. For
Auto-Retransmit on collision, PAL B passes the EOP
signal from the 82592 to the DMA controller, reinitializing the DMA controller for retransmission. This process will be discussed in more detail in Section 4.3. Both
sets of PAL equations are listed in Table 1.

Table 1. PAL Equations
PAL20L 10 MMI-PAL A (Version 1.1)

AEN A2 RESET NC AO IOWBAR A5 A6 A7 AS A9 GND IORBAR 501LB Al 59CTS OE2BAR
OE1BAR LANRSTBAR NC NC ENLANBAR 592CSOBAR VCC

=592CTS
592CSOBAR =AEN •
OE2BAR =AEN • A9
OE1BAR =AEN • A9

IF (VCC) 501LB
IF (VCC)
IF (VCC)
IF (VCC)

IF (VCC) 1ANRSTBAR
IF (VCC) ENLANBAR

A9 • AS • A7 • A6 • A5·. A2 • Al • AO • ENLANBAR
• AS • A7 • AS • 'A5 • A2 • Al • AO • IORBAR • ENLANBAR
• AS • A7 • AS • A5 • A2 •. Al • AO • IORBAR • ENLANBAR

=!EN
• A9 • AS • A7 • A6 • A5 • A2 • Al • AO •
ENLANBAR

IOWBAR •

=LANRSTBAR •

ENLANBAR + AEN • A9 • AS • A7 • A6 • A5 • A2 • Al
• AO • IOWBAR

PAL20L 10 MMI-PAL B (Version 1.1)

592DRQO RESET DACK7BAR DACKSBAR lORBAR 592DRQl 592EOPBAR ENLANBAR AEN NC
IOWBAR GND 592INT NC DRQSBAR DRQ7 DRQS DISDACK IRQ10 NC MSEOPBAR LTCW
.
592DACKBAR VCC
IF (VCC) LTCW = IORBAR + 592EOPBAR + DACK7BAR
IF (ENLANBAR • 592EOPBAR • DACKSBAR) MSEOPBAR
IF (VCC) 592DACKBAR
IF (VCC) DISDACK
IF (VCC) DRQ7 =
IF (VCC) DRQSBAR
IF (VCC) i5RQ6
IF (ENLANBAR)

=DACKSBAR •

= IOWRBAR •

=592EOPBAR •

DACKSBAR

DISDACK • ENLANBAR + DACK7BAR • ENLANBAR

DISDACK • RESET + 592DRQO • DISDACK • RESET

+ 592DRQO • IOWRBAR ~

RESET

592DRQl + 592EOPBAR • DACK7BAR

=592DRQO

• RESET + DACK6BAR • DRQSBAR • RESET

=DRQSBAR
IRQ10 =592INT

NOTE:
The suffix BAR added to the above signal names indicates an active low signal. A signal in these equations' with a line
drawn above it indicates this Signal is to be in a low state for the equation.

1-162

intJ

Ap·320

4.2 Back-to-Back Frame Reception

TCI signals of the 82592 (PAL B loads the address
latch with the address of the last byte of the received
frame) and the structure of the received frame transferred from the 82592 to memory. Figure 5 shows the
format of an 82592 receive frame in TCI mode. After
the information fields are written to memory, the Status
and byte count of the received frame are appended to
the frame in memory. These four bytes (two bytes of
Status and two bytes of byte count) are the last four
bytes of the receive frame written to memory. The high
byte of the byte count is the last byte transferred from
the 82592 to memory. As this last byte is transferred to
memory, the 82592 asserts the EOP signal. When PAL
B detects the assertion of EOP by the 82592, it loads
the address of the last byte of the receive frame into the
Address Latch as this byte is written into memory. This
action ensures that there will always be a pointer (the
contents of the Address Latch) to the byte count of the
last frame stored in the RFA buffer in system memory.
Based on the value of the byte count, the beginning
address of the receive frame in memory can be calculated; i.e., Byte Count Address Pointer - Byte Count =
Beginning of Frame. The byte count of a previous receive frame would reside one address location before
the first byte of the current receive frame. That frame,
and any additional receive frames that may have preceded it, can have their start addresses recovered by the
same calculation used to recover the last frame received. This process allows frames to be continually
stored in the RFA buffer without CPU intervention,
and to be recovered by the CPU for processing. Figure
6 illustrates the process of back-to-back frame reception.

The architecture of the 82592 Embedded LAN Module
allows it to receive back-to-back frames without CPU
intervention. It uses a contiguous Receive Frame Area
(RFA) buffer in host system memory where receive
frames can be continuously stored. This sequential storage of receive frames can continue until the buffer space
is exhausted. The size of the RFA buffer can be specified by the programmer. Its size will be programmed as
the byte count of the Rx DMA channel. The Base Address Register contents of that channel serve as the
start address of the RFA buffer. The receive frames will
be stored sequentially in the RFA buffer based on the
contents of the Current Address Register of the Rx
DMA channel. The module's architecture, and the
82592 receive frame memory structure, allows the CPU
to recover the addresses of each Receive frame in memory for processing. The CPU can also reinitialize the
RFA buffer (by reinitializing the Rx DMA channel) as
the RFA buffer fills up and its contents are processed.
Alternatively, configuring the Rx DMA channel to
Auto-Initialize mode will allow the Rx buffer to automatically wrap around, back to the beginning of the
buffer, when its end is reached. This creates a virtual
"en'dless" circular buffer. When using this approach,
care must be taken to avoid writing over unprocessed
Rx frames-either by the addition of a hardware Stop
Register, or by guaranteeing that the Rx frames can be
processed faster than the buffer can wrap around.
Back-to-back frame reception without CPU intervention-and eventual recovery of the frames for processing by the CPU-is based on PAL B's decoding of the
14

15

12

13

11

10

9

8

7

5

6

DESTINATION ADDRESS SECOND BYTE

4

o

2

3

DESTINATION ADDRESS FIRST BYTE

DESTINATION ADDRESS LAST BYTE
SOURCE ADDRESS FIRST BYTE

SOURCE ADDRESS SECOND BYTE

I
SOURCE ADDRESS, LAST BYTE
INFORMATION (LENGTH FIELD, HIGH)

I

I

I

INFORMATION (LENGTH FIELD, LOW)

I

.I

I

I

I

I

~

INFORMATION LAST BYTE
CRC BYTE o·

CRCBYTE l '
CRC BYTE 3'

CRC BYTE 2'

X

X

X

X

X

X

X

X

SHORT
FRAME

X

X

X

X

X

X

X

X

0

X

X

X

X

X

X

X

X

NO
EOF

TOO
LONG

1

NO
SFD

NOADD
MATCH

I·A
MATCH

Rx
CLD

0

Rx
OK

LEN
ERR

CRC
ERROR

ALG
ERROR

0

OVER
RUN

BYTE COUNT LOW

X
BYTE COUNT HIGH
X
X
X
X
X
X
X
'The CRC bytes are transferred to memory only when the deVice IS so configured

Figure 5. Receive Format for the 82592 in 16·Bit Mode (Tightly Coupled Interface Enabled)

1-163

i~

AP-320

Example No.1

Example No.2

First Frame
Received

Second Frame
Received

I Rev

Rev

Frame AreaIn Host Memory

In

I

1--+

Frame Area

~ost

RCV Frame Area

Memory

In Host Memory

Frome 1

Frame 1

Latch

Example No.3
nth Frame
Received

Frame 1

Status

Status

Slalus

Byte Count

Byte 'Count

Byte Count

Remainder of

Frame 2

Additional
RCV Frames

RFA Buffer

290189-6

Frame n

Slatus

I

Latch

1-----+

I

Byte Count
Status

Remainder of
RFA Buffor

r

Latch

J-----.

290189-7

Byte Count
Remainder of

RFA Buffor

290189-8

NOTES:

'

The 82592 a'ppends the byte count to the'end of each RCV frame.
PAL 'B' loads the latch with the memory address of the last byte of each RCV frame.
Based on latch contents and the byte count of each frame, the CPU recovers the RCV frames.

Figure 6. Back-to-Back Frame Reception

4.3 Automatic Retransmission on
Collision
Automatic 'retransmission on collision detection is ac·
complished by the T<;!I between the 82592 and the host
8237 OMA controller and requires no CPU interven·
tion. The transmit channel of the 8237 should be configured for Auto·Initialize mode. The transmit block
(data to be transmitted) starts at the location pointed to
by the Base Address Register of the Tx OMA channel.
Ouring a Transmit command, the 82592 riMA requests begin at the start of the transmit block and work
sequentially through the block (by incrementing the
contents of the 8237's Current Address Register) until
the transmission is complete. Should a collision occur,
the 82592 asserts the EOP signal and ORQ' to the
8237 (these signals pass through PAL B) causing the
8237 to auto-initialize back, to the beginning of the
transmit block (the Current Address Register is loaded
with the value in the Base Address Register). Internal-

ly, the 82592 generates a Retransmit command and begins making DMA requests to the 8237, which is now
pointing to the beginning of the transmit block. The
82592 also enters into a back-off algorithm (counting to
a random number to resolve the collision). When the
back-off algorithm is complete, and the 82592 regains
access to the serial link, retransmission is attempted.
The 82592 will repeat this process until the retransinission is completed successfully or until the maximum
allowable number of collisions per Transmit command
is reached-at that point all retransmit attempts stop.
No CPU involvement is required to carry out a retransmission. The process of automatic retransmission is
shown in Figure 7.
NOTE:
"For Auto-Initialization of the S237, the signal ORQ
must be asserted to'the 8237 along with assertion of
EOP. With the 82380 and 82370 OMA controllers,
Auto-Initialization can be triggered by asserting the
EOP signal alone.

1-164

AP-320

Prior to Transmission
BAR = CAR
Transmit DMA Channel In
Auto-Initialize Mode

During Transmission
CAR Increments

BAR/CAR~

BAR ~ , - - - - - - - - ,
Transmit
Buffer in
System
Memory

CAR~

Collision:
82592 EOP Asserted to 8237
CAR Reset to BAR
(by 8237's Auto-Initialize)
BAR/CAR ---+
Transmit
Buffer in
System
Memory

Transmit
Buffer in
System
Memory

After Back Off the 82592
Retransmits from Beginning of
Transmit Buffer.
No CPU Intervention is
Required for Retransmission

BAR = Base Address Register
CAR = Current Address Register

Figure 7. Automatic Retransmission on Collision

4.4 Target Systems for Integration
The 82592 Embedded LAN Module is designed to be
implemented on an Intel SYP301 motherboard; thereby
demonstrating a low-cost LAN connection for a workstation. The SYP301 has an IBM PC AT style bus architecture with a 32-bit Intel 80386 as the main processor. The interface between the 82592 LAN Module and
the SYP301 is based on standard interface signals
(DRQ, DACK, EOP, IRQ, lOR, lOW, etc.) so the
basic architecture of the module can be implemented on
PC AT based systems. This design has been successfully tested in PC AT style systems produced by several
manufacturers. For some PC;:: AT based systems, and
PS/2 Micro Channel systems, the module's design may
require some modification. IBM PC and PC XT based
systems do not have sufficient DMA bandwidth to support the non-buffered architecture of this module.
4.4.1 PC AT BASED DESIGNS

High-integration chip sets replace a large number of
discrete. VLSI, LSI, and TTL components with several
integrated VLSI devices that duplicate a large portion
of the PC's functionality. PC AT compatible systems
using such chip sets may lack support for the automat~c
retransmission feature of the 82592 LAN Module. ThIs
is because many manufacturers of such chip sets have
integrated the EOP function but e~iminated th.e .~O~
input. This lack of an EOP input dIsables auto-Initialization of the DMA controller for retransmission. In

this case retransmission can be performed in one of two
ways.
• Should a collision occur while transmitting the preamble, the 82592 (when configured to automatic r~­
transmission mode) will automatically retransmIt
without CPU intervention or auto-initialization of
the DMA. This is effective for shorter network topologies where collisions are normally detected early in the frame.
• Should a collision occur after the preamble, the
82592 will interrupt the CPU and the CPU will initiate the retransmission.
For a PC AT style architecture, logic must be implemented to accommodate DRAM refresh. DRAM refresh cycles typically occur at 15 ,...S intervals. In a standard PC AT, any DMA user should limit the time of a
DMA burst to 15 J-LS; this is to ensure that the system
bus is free for the refresh to take place. Any designer
using burst mode DMA must consider this requirement
when implementing a design.
4.4.2 PS/2 MICRO CHANNEL ARCHITECTURE
DESIGNS

The IBM PS/2 and other compatibles using the Micro
Channel architecture have a different host interface to
the 82592 Embedded LAN Module; however, the basic
architecture of the module is still applicable. As in the
SYP301 solution, the TCI between the 82592 and a

1-165

inter

AP-320

control PAL loads the address latch with a pointer to
the last receive frame. Based on the contents of the'
latch and the 82592 receive memory structure, the
frames are recovered for prpcessing by the CPU. The
differences between a PC AT architecture and a Micro
Channel architecture require different control signal
decoding. The Micro Channel requires a 24-bit address
latch, as opposed to a 16-bit latch in the 301, and to
acquire the system DMA it requires different arbitration logic to drive a 4-bit arbitration level on the Micro
Channel. The Micro' Channel also does not have an
EOP input; therefore, auto-initialization of the Tx
DMA channel and support of automatic retransmission
without CPU intervention must be provided by using
one of the alternative methods recommended in the
previous section.
4.4.3 EMBEDDED CONTROL DESIGNS

The 82592 Embedded LAN Module architecture can
also be applied to an embedded control application that
contains some DMA functions. For an embedded application using an 8237, 82380 or 82370 DMA controller,
the. basic architecture of the 82592 Embedded LAN
Module can be used. For an interface to DMA devices
that do not feature the EOP signal 'as an input (for
example, DMA units on board a CPU), the alternative
methods for retransmission given earlier can be used.

5.0

SERIAL INTERFACE MODULE

The serial interface for the Intel SYP301 82592 Embedded LAN Module is implemented as a separate module.
Since the 82592 Embedded LAN Module is intended to
be integrated into a system motherboard, implementing
the serial interface as a separate module-perhaps as a
very small PC board that plugs into a 'socket-allows
for easy interchangeability b\'tween different serial interface media. This modularity allows the system board
manufacturer to avoid committing his motherboard to
only one type of medium, and thus requiring a major
.redesign for each different serial interface..
Modularity in the data communications field is encouraged by the Open Systems Interconnect (OSI) ref~rence
model. The 82592 is designed to operate through the
lower half of the Data Link Layer (see Figure 8), implementing CSMA/CD Medium Access Control and interfacing directly with the Physical layer below it. By
interfacing the 82592's standard CSMA/CD interface
signals~a serial module (TxD, RxD, TxC, RxC,
CDT, CRS, and others) different Physical Link modules can be implemented without any change to software. Examples of serial interface modules that could
. be interchanged by simply plugging a new module into
the motherboard are Ethernet/Cheapernet, Twisted
Pair Ethernet (TPE), StarLAN, Broadband Ethernet,
and many proprietary CSMA serial media. Figure 9
shows the schematics of an Ethernet module; and Figure 10 those of an .EthernetiCheapernet module.

OSI
Reference Model Layer.

7

Application

6

Presentation

5

Session

4

Transport

3

Network

2

Data Link
Physical

"

,"
,,

......

,

"

"

LLC
Logical Link Control

2.-------~------~
MAC

....
.... ....

Medium Access Control

PLS
Physical Signaling

290189-10

Figure 8. The 82592 Embedded LAN Module Relationship to the OSI Reference Model

1-166

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290189-47

inter

AP-320

6.0 PERFORMANCE COMPARISON

7.0 SOFTWARE EXAMPLES

Figure II compares the performance of the 82592 Embedded LAN Module with the PC586E nonintelligent,
buffered adapter. The PC586E is an 'Intel evaluation
board based on the Intel 82586 LAN Coprocessor. It
contains 16 kB of local memory, has a 16-bit bus interface, and has a high-performance arbitration scheme
providing both the CPU and the 82586 LAN controller
zero wait state access to local memory. The PC586 has
been characterized in the industry as one of the highest
performance nonintelligent, buffered adapters available.

The following examples are from a driver written for an
82592 Embedded LAN Module operating in an Intel
SYP301. The driver was written by Joe Dragony, Intel
Data Communications Technical Marketing Engineer.
The excerpts will cover (I) declarations of program
constants and variables, (2) initializing the Embedded
LAN Module hardware and buffer space, (3) assembly
and transmission of a frame, and (4) processing received frames. A brief description of each of these processes is followed by excerpts from the code. The driver
uses the Xerox Internetwork Packet Exchange (IPX)
protocol and serves as a software interface between the
82592 Embedded LAN Module hardware and the IPX.

A perfornlance comparison, using Novell's Perform 2
utility, shows that the 82592 Embedded LAN Module,
operating as a workstation accessing a file server, outperforms the PC586E. For all tests the host system was
an Intel SYP301. The SYP301 was run in both standard mode, a nominal 16 MHz", and in its reduced
speed mode, 6 MHz. In all cases the SYP301 system
DMA operates at 4 clocks per cycle at 4 MHz. The file
server was a Novell 286A, an 8 MHz, zero wait state
system, using a PC586E as the LAN adapter. The tests
recorded are for one node on the network (the worksta, tion under test). For write tests to the file server's hard
disk, the performance numbers are generally the same.
This is due to limitations in accessing the, file server's
hard disk. This slow access causes a bottleneck. For the
read tests the workstations are accessing files stored in
cache memory, thus removing 'the bottleneck for this
test. Without this limitation, the 82592 Embedded
LAN Module accesses the file server at a higher rate
than the PC586E: at full speed, 318 kB/s vs
282.3 kB/s; and at reduced speed, 202.8 kB/s vs
195.2 kB/s.

Exerciser Software for the 82592 Embedded LAN
Module is also available from Intel. Detailed documentation for both the exerciser program and the network
driver are available upon request from Intel.

7.1 Declarations
Table 2 shows declarations of program variables and
equates of program constants. This section is included
to help the reader understand the following program
excerpts.
"NOTE:
The benchmark program Landmark CPU Speed Test,
@ 1986 by Landmark Software, shows an effective
throughput of 14.3 MHz for a SYP301 in standard
mode; and 5.4 MHz in reduced speed mode.

•

Standard
Write

~

Standard

III

Reduced

Write

~

Reduced
Read

Read

Kilobytes per Second
290189-11

NOTES:
Novell Perform 2 Version 2.3
File Server: '2B6A. B MHz, Zero-Wait-State with PC5B6E LAN Adapter
Node System: SYP301 (One Node on Network)
Reduced Speed Mode: Equivalent to 5.4 MHz AT
Standard Mode: Equivalent to 14.3 MHz AT
301 System DMA: 4 MHz, Four Clocks per Transfer

Figure 11_ 82592 SYP301 Embedded LAN Module vs PC586E Buffered Adapter

1-169

inter

Ap·320

Table 2. Declarations
$'*define(slow) local label
jmp
short 'label
Habel:
)

%*define(fastcopy) local label (
shr cx, 1
rep movsw
jnc Habel
movsb
,iabel:
)

'*define(inc32 m) (
add word ptr %m[D], 1
adc word ptr 'm[2], 0
name

LANOnMotherboardModule

CGroup

group

asswne
Code

cs: CGroup, ds: CGroup

segment word public 'CODE'

public
public
public

DriverSendPacket
DriverBroadcastPacket
DriverPoll

public

LANOptionName

extrn
extrn
extrn
extrn

rpXGetECB: NEAR
rpXReturnECB: NEAR
rpXReceivePacket: NEAR
rpXReceivePacketEnabled: NEAR
l;PXHoldEvent: NEAR
rpXServiceEvents: NEAR
rpXrntervalMarker: word
MaxPhysPacketSize: word
ReadWriteCycles: byte
rpXStartCriticalSection: NEAR
rPXEndCriticalSection: NEAR

extrn

extrn
extrn
extrn

extrn
extrn
extrn

290189-16

1-170

intJ

AP-320

Table 2. Declarations (Continued)
:;;;;;; i;;;;;;:;;;;;

E'!'1ates
....................
.. " " " " " " "

,."

CR
LF
BAD

BPORT
lRQLOC
DMAOLOC
DMA6LOC
TransmitHardwareFailure
PackstUnDalivarable
PacketOvertlow
ECBProcessing
'l"xTimaOutTicks

e'!'1
e'!'1
a'!'1
e'!'1
e'!'1
8'!'1
8'!'1
a'!'1
a'!'1
a'!'1
s'!'1
s'!'1

ODh
OAh
OFFh
0
19
23
2S
OFFh
OFEh
OFDh
OFAh
20

Latch definitions
'l"anC&ntLo
a'!'1 301h
'l"enCentHi
e'!'1 302h
Enablas for 10cent
EnLAN
B'!'1 303h
Dis LAN
e'!'1 304h
8259

definitions

lnterruptControlPort
lnterruptHaskPort

e'!'1
e'!'1

ExtraInterruptContro1Port

equ

EOl

e'!'1

020h
OAlh
OACh
020h

;for sacondary S2S9A

8237 definitions
DMAc:lDdstat
DMAraq
DMASnglmsk
DMAmode
DHAff
DMAtmpclr
DMAclrmak
DMASllmsk
DMA6paga
DMA6addr
DMA6wdcount
DMA7pags
DMA7addr
DMA7 ..dcount
DMAtx6
DMAt,,7
DMArx6

DHArx7
DMA6m.sk
DMA6unmsk
DHA7mak
DMA7unmak
DMAena

S'!'1
a'!'1
a'!'1
s'!'1
a'!'1
s'!'1
s'!'1
s'!'1
e'!'1
s'!'1
s'!'1
s'!'1
s'!'1
e'!'1
e'!'1
a'!'1
e'!'1
e'!'1
e'!'1
a'!'1
B'!'1
a'!'1
e'!'1

ODOh
OD2h
OD4h
OD6h
ODSh
ODAh
ODCh
ODEh
089h
OCSh
OCAh
OSAh
OCCh
OCEh
01Ah
01Bh
006h
007h
006h
002h
007h
003h
Oh

demand mode, autoinit, read transfer
demand moda, autoinit, read transfer
demand mode, no autoinit, writQ transfer

demand mode, no autoinit, write transfer

290189-17

1-171

AP-320

Table 2. Declarations (Continued)
NetWareType

equ

llllh

: 82592 COlIU1Iands
C NOP
C-SWPl
C-SELRS"l"
C-SWPO
C-IASET
C-CONl!":IG
C-KCSE"l"
C-TX
C-TOR
C-OtlMl?
C-OIAG
C-RXENB
C-ALTBUF
C-RXDISB
C-STPRX
C-RETX
C-ABORT
C-RST
C-RLSPTR
C-F:IXPTR
·C:INTACK

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

OOh
10h
OFh
Olh
Olh
02h
03h
04h
05h
l6h
07h
l8h
09h
lAb

lBh
OCh
OOh
OEh
OFh
lFh
BOh

..............................

"""""""""""""""
Data Structures
...............................
"",
""""""""""."

even

..

hardware structure
io addrl
io:range1
.i.o addr2
decode_range2
IDem addrl
mem:rangel
mem addr2
_:range2
int usedl
int-linel
int-used2

int-line2
dma-usedl
dma-chanl
dma-used2
dma-chan2
hardware_structure

struc
dOl
?
dOl
dOl
?
dw
?
dOl
?
dw
dw
dw
?
db
db
db
db
db
db
db
db

?
?
?
?
?
?

ends

ecb structure
struc
-link
esr address
in use
coiiipletion_code

dd
dd

0

db
db

0
0

0
290189-18

1-172

intJ

Ap·320

Table 2. Declarations (Continued)
socket nWllber
ip,,_workspace
driver_workspace
immediate address
fragment count
fragment:descriptor_list
eob_structure
ends
fragment_descriptor
fragment_address
fragment_length
fragment_descriptor
:r:x buf stz:uctUl:ti

dw
db
db
db
dw
db

0

4
12
6

(0)
(0)
(0)

1
6

dup (7)

struc
dd
7
dw
?
ends

struc

- rx-dest addr
rz-source adelr

db
db

dup (7)
dup (7)

r,,:physical_length
rx checksum
r":length

dw
dw
dw

rx tran control
r",:hdr_type
rx. deat net
r,,-dest-node
rx-dest-socket
rZ-SQurce net

db
db
db
db

7
7
7
7
7
4 dup (7)
6 dup (7)

dw
db
db

rx-source-node

rx-source-socket
dw
rX_buf:structure
ends

tci status
-status 0
deadl
status 1
dead2
bc 10
de&"d3
bc hi
tCi_st&"tus

dup
dup
dup

4 dup (7)
6 dup (7)
7

struc
db
db
db
db
db
db
db

7
7
7

ends

ip,,_header_structure
struc
checksum
dw
?
packet_length
dw
7
transport_control
7
db
packet_type
db
7
destination network db
4 dup (7)
destination-node
db
6 dup (7)
destination-socket
dw
7
aQuJ:'ce network
4 dup (7)
db
source-node
db
6 dup (?)
source-socket
dw
ipx_header:structure
ends
iii;;;;;;;:;:;;;;;:;;;;;;;

Variables
iii;:;;;;::;;;:::::;:;;;;;

even

290189-19

1-173

intJ

AP-320

Table 2. Declarations (Continued)
tz atart t1Dla
adapte,,_To
confiq
aend list
buffer_segment
tx:ecb

dv
dw
dv
dd
dv
dd
dd

confiq block

db

rx acb

0
?
?

;points to liat of ECBs to be sent

0
?
?

?

Orh,00h,4~h,80h,26h,00h,60h,00h,OF2h,00h,00h,40h,OF5h,0Oh,3Fh, 87h,OFOh,ODFh

temp_flaq
int_mask_"eqiste"
old_ir'Lvector
int vecto" add"
int-bit
int-mask
ccmiDand_req
"ead_in_length
confiq_dmaO_1oc
confiq_dmal_loc
confiq_i"'Ll0c
config_bport
tx_sctive_flaq
f"ame status
atatuslO
statuall
status20
status2l

o

db
dw
dd
dw
db

?
?
?
?
?

db

dw
dw
db
db
db
dw
db
db

300h

;82592 port 0 addresa

?
?
?
?
?

o
o
o
o

db

db

o
o

db

db

even
'lP buf
'lP_length
'lP_buf_offaet
'lP_offaet_sdjust
'lP_buf_stsrt
'lP_buf"'psqe
t,,_byte_cnt
"" buf atart
rz:bufJ,aqe
rx buf head
here rx buf tail
r,,:bufJ,tr
",,_buf_stop
r"_buf_length
r,,_buf_segtMnt
curr_rx_lenqth
"z liat

num of

frames

reset rx buf
padding -

dw
dw
dw
dw
dw
dw
dw
dw
dw
d.
dw
dw
dw
dw
dw
dw
dw
dw
' dv
dw

5000 dup (0)
1388h
cgroup: 'lP_buf

o
o

o
o
o
o
o

o
o

o
o
o
o

;twice the required size

;Al-AU of General Purpose Buffer EA
;Al7-A23 of General Purpoae Buffar EA
;IPX packet length plus header length
;Al-Al6 of General Purpose Buffer EA
;A17-A23 of General Purpoae Buffar EA
;current rx bead, buffer has been flushed to
ivalue read fram 10 cent latches
;u.ad during rz list generation
;point to reset tha DNA controller

;calculated at init for use by IPXReceivePackat

180 dup (0)

o
o

'0

Define Hardware Configuration
290189-20

infef

Ap·320

Table 2. Declarations (Continued)
ConfigurationID

db

SDriverConfiguration

'NetWareDriverLAN WS

LABEL

reserved1
db
node addr
db
reserved2
db
node addr type
db
max data size
dw
(512, 1024, 2048, 4096)
Ian deBe offset
dw

byte
4 dup (0)
6 dup (-0)

o
o

inon-zero means is a real driver.

;address is determined at initialization
1024 ;largest read data request will handle
LANOptionName
OAllh
; Bogus Type Code

lan-hardware id

db

traiisport tiDie
reserved "3
major version

dw
db
db

minor- vez:sion

db

fla!Lbits
selected_configuration

db
db

o
o

db
dw

01
eonfigurationO

;transport time

1

11 dup (0)
Olh ;Bogus version number

OOh
:board configuration (interrupts, IO

addressBs, etc.)

number_of_configs
config-pointers
LANOptionName
configurationO
db

dw
db
dw
db

o
o,
o
o"

db

db
db

db

'Intel LAN-On-Motherboard Module',O,'$'

d"

300h, 16, 0, 0

;10 ports and ranges

0

0

:m&mOry decode
;interrupt lavel 10
:DMA channels 6 and 7

OFFh, 10, 0, 0
OFFh, 6, OFih, 7
0,0
'IRQ 10, 10 Addr

= 300h,

DMA 6 and 7, For Evaluation Only', 0

;**.****~********************************************* .*

..

Error Counters

i.--........................-.._...........-.._.*._...

A ••

Public DriverDiagnosticTable,DriverDiagnosticText

DriverDiagnosticTable

LABEL

DriverDebugCount

dw

D~ive~Ve:r:sion

db
db

StatistiesVersion
- Tota1TxPacketCount
TotalRxPacketCount
NoECBAvailableCount
PacketTxTooBigCount
PacketTxTooSmallCount
PacketRzOve:r:£1owCount

PacketRxTooBigCount
PaeketRxTooSmallCount
PacketTxHiscErrorCount
PacketRzMiscErrorCount
RetryTxCount
ChecksumErrorCount

dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
d"
dw

byte
DriverDebugEnd-DriverDiagnost'ic-:able

01,00
01,00
0,0
0,0
0
-1
-1
0
0
0
-1
-1
0
-1

inot used
; not used

inot used
;not used

;not used
290189-21

1-175

Ap·320

Table 2. Declarations (Continued)
HardwareRXMismatchCount
NumberOfCUstomvariables
DriverDebUgEndl

dw
dw

LABEL

0
(DriverDiagno8tic~ext-DriverDebugEndl)/2

byte

.......................................

"""1"",., •• " " " " . " . " " " . " , ,
Driver Specific Error counts

.......................................

""""""""""""""""""""
rx errors
underruns

no_cta
no era
rx-aborts

no-S90 int
false 590 int
lost

rx -

stop:tx

ten cent latch crash

rx disb failure
t,,-abort failure
rxbuff ovflw
tx:U.meout

dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
d"
dw

0
0
0
0
0
0
0
0
0
0
0
0
0
0
LABEL

DriverDiagnostic~ext

db
db
db

db
db

db
db
db
db
db
db
db
db
db
db

byte

'RxErrorCount',O
'OnderrunCount',O
'LostC~SCount' ,0
'LostCRSCount',O
' RxAbortCount I

I

0

'NoS90InterruptCount' ,0
'FalseS90InterruptCount',O

'LostOUrReceiverCount',O
'QuitTransm1ttingCount',O
'TencentLatchCrashCount',O

'RxDisableFailureCount',O
'TxWontAbort',O

'ReceiveBufferOverflow',O
'TxTimeoutErrorCount',O

0,0

DriverDebugEnd

LABEL

word
290189-22

1-176

inter

AP-320

7.2 Initialization Routine
This routine, Driver Initialize, initializes the Embedded
LAN Module hardware and the system hardware needed to support the module. It also sets up the system
memory structure to support the module.
7.2.1 HARDWARE INITIALIZATION AND 82592
CONFIGURATION

Initialization of the Embedded LAN Module hardware
begins with generating an individual address for the station, initializing the interrupt line and interrupt vector,
and enabling the module by writing to port address
303h. After initializing the memory structure, the
82592 is directly programmed. This programming includes configuring the 82592 and initializing it with the
station's individual address. The 82592 is configured in
two steps. The first specifies a l6-bit-wide system bus
interface by issuing a Configure command to the 82592,

with OOh as the byte count; i.e., no parameters passed to
the device. Then a second Configure command is issued; it does the following.
• The 82592 is put in High Speed Mode to support
Ethernet serial bit rates.
• It is placed in TCI mode for interface to the Embedded LAN Module architecture.
• All network parameters (e.g., Frame Length, Slot
Time, and Preamble Length) are set up for default
Ethernet values.
FollowiIig this initialization llnd configuration of the
module's hardware, the 8259A Programmable Interrupt Controller's-interrupt line for the module is enabled, allowing the interrupt-driven events frame reception and completed transmission. Then a Receive Enable command is issued to the 82592. Table 3 contains
the code for hardware initialization.

Table 3. Hardware Initialization
segment ' CODE'

public
OriverInitialize, DriverUnHook
no card massage
db CR,LF, 'No adapter installed in PC$'
configJailure_Dlessage
db CR, LF, 'Cqnfiquration Failure$'
iaset failure message
db CR,LI', 'IA Setup Fail.ure$'
ConfigDatauncie'rrUnHeSS
db CR , LF, , Configuration underrun$'
Driver Initial.iza
assumes:
OS, ES are set to CGroup (= CS)

DI points to where to stuff node: address
Interrupts are ENABLED
'lha Real. 'rilDe Ticks variabl.a is being set, and the
entire US system is initial.ized.

returns:
If initialization is clone OK:
AXhasaO

Xf board malfunction:
AX gets offset (in CGroup) of ' $' -terminated error string
DriverInitial.ize PROC
NEAR.
mov
MaxPhysPacketSize, 1024
cl.i
c:l.d

ax, cs
cis, ax
moves, ax
get DOS tizn& and use :for address.
mov
ah,02Ch

mov
mov

int
mav
mav

mov
mov
mev
mov
mev
mov
movsw

2lh
bx, OFFSET CGroup: nod.a_ ac1dr
byte ptr c:group: [bx], OOh
byte ptr cgroup: [bx+l], OAAh
byte ptr cgroup: [bx+2], ch
byte ptr cgroup: [bx+3], dl.
byte ptr cgroup: [bx+4], db
byte ptr cgroup: [bx+S], 7Eh
si, bx ,
; stuff address at point IPX indicated

DlOVSW

mavs",

ati
initia,U.ze the configuration tabl.e
!nOv
a1, selected_configuration
cbw
shl
ax, 1
; multiply ·by two
add
az,OFESET CGROW:config.J'Ointers

iax contains the offset value

290189,-23

1-177

inter

AP-320

Table 3. Hardware Initialization (Continued)
IIIDV
IIIDV

mov
mov
mov
mov
mov
mov
mov
mov
mov

bx,ax
bx, [bal
Config,hz
al, [ba+DMAOLOC]
config_dmaO_loc,al
al, [ba+DMA6LOCl
config_dmal_loc,al
al, [bxURQLOCl

;of the default configuration
; list

config_i~loc,al

aa,[ba+BPOM]
command_reg, 300h

Set~heInterruptVector:

SBT UP THlii

push
mov
mov
call
pop
mov
out
hlow

d1
al,

DI'l'BRRUP~ VBC~ORS

config_ir~loc

OFFSE~ CGroup: DriverISR
SetInterruptVector
di
dx, BnLAN
dx, a1
;enable LAN on MB module

hz,

IDOV

dx, command_reg

mov
out

al, C RS~
dx, aT

; reset the 82592 controller

;generate 20 bit addreas for DMA controller from configure block location
;this i8 necessary to accomodate the page register used in the PC DNA
call

set_up_buffers

:set up DMA channel for configure,command
ax, aa
xor
DMAff, al
out
;data i8 don't care
hlow
al, DMAena
mov
DMAcmdstat, al
out
ax, gp_buf_stsrt
mov
'slow
out
DMA6addr, al
al, ah
mov
'slow
DMA6aclclr, al
out
ax, gp_buf.J>age
mov
blow
DNA6page, al
;DNA page value
out
ax, 1
mov
'slow
DNA6wdcount, al
;make two transfers
out
al, ah
mov
blow
DMA6wdcount, al
out
al, DMAtx6
mov
: setup channel 6 for tx mode
hlow
DHAmode, al
out
al, DMA6Wl111Sk
mov
290189-24

1·178

intJ

AP-320

Table 3. Hardware Initialization (Continued)
%slow
out
XOI:'

DMAsnglmsk, a1
ax, ax

mov

di, 9P buf offset

the
atoaw
stOB'"
%slow
mov
mov

out
%slow

-

;mov zeroes into the byte count field of the

-;buffer to put the 82592 into 16 bit mode

dx, command rag
al, C CONFXG
dx, 81

;configure the 82592 for 16 bit mode
:issua configure command

wide_modB_wait_100p:
xor
al, a1
%slow

out

dx, al

;point to register

°

%slow

in
and
cmp
jz
loop
mov
jmp

°

a1, dx
;read register
a1,ODFh
;dioregard exec bit
al, 82h
i is configure finished?
do config
wide-mode wait loop
ax, OFFSET CGroup: no card message
init_exit
--

do_confiq:

mov
out
xor

al, C IN'rACK
dx, aI

;clear interrupt

ax, ax

%slow

out
mov

DMAff, a1

idata is don't care

ax, gp_buf_start

%slow

out
mov
%slow
out
mov

DMA6addr f

a1

al, ah
DMA6addr, a1
ax, 9P_bufJ'age

%slow

out

DMA6page, al

;DMA page value

%slow

mov
out

al, DMAtx6

;setup channell for tx·mode

DMAmode, a1

%slov

mov
out

ax, 8
DMA6wdcount, &1

%slow

mov
out
%810"
mov

out
mav
mov
mov
mov

al, ah
DMA6wd.count, a1
al, DMA6unmsk

DMAsnglmsk, a1
ax, d.s
es, ax
8i, offset cgroup:config block
di, 9P_buf_offset
290189-25

1·179

,inter

AP-320

Table 3. Hardware Initialization (Continued)
mav

ex, 18

rep movab
mav
mav

dx, command_reg

out

dx,

a1, C CONFIG

configure the 82592

a1

%slow

zor

ex, ex

config wait 100p:
%a10" a1, a1
"or
%slow

out
..10..
in
and
cmp
jz

100p
mav
jmp

c:bI:, a1

;point to register 0

a1, c:bI:
a1, ODFh

;read register 0
:discard·extranaous bits

a1, 82h
; is configure finished?
config done
config_wait_1oop
ax, OFFSET CGroup: config_fai1ure_message
init_exit

config done:
c1ear interrupt caused by configuration
mav
a1, C IN'rACK
out
cix, a1
do an lA_setup

mov
mov

di, gp_buf_offset
al, 06h
:address byte count

stoab
mov
stosb

a1, DOh

mov
mov

8i, OFFSET CGROUP : node addr
cx, SIZE node_addr
-

rep movsb

out

DMAff, a1

;data is don't care

%slow

mov
out
mov
'a1,?"

out

mav

h10w
out

ax, gp buf start
DMA6addr, 81
al, ah
DMA6addr, a1
ax, gp_bufJ>age
DMA6page, a1

:DMA page value

%slow

mov
out
%&10w
mav
out

a1, DMAtx6
DMAmode, 81

:setup channell for tx mode

ax, 3
DMA6wdcount, a1

%slow

mov

a1, ah

out

DMA6wdcount, a1

%slow

mov·
out

a1, DMA6unmsk
DMAsng1mak, a1
290189-26

1-180

inter

Ap·320

Table 3. Hardware Initialization (Continued)
IIIOV

dx, cOlnIl\and reg

IIIOV

al, C IASETc!x, aT

out
xor

;set up the 82592 individual ac1c1ress

ex, ex
:cz is used by the loop instruction below. this
:causea the loop to be executed 64k times max

ia wait loop:
- xo:out

blow
in
and
cmp

jz
loop

a~, a1
dx, a1

al, c!x
al, ODFh
al, alh
ia done

:discard extraneous bits

; is command finished?

IIIOV

ia_wAit_loop
ax, OFFSET CGroup: iaset failure message

jmp

init_exit

--

ia_done:
mov

a~,

C_DnACK

out
dz, a1
:clear interrupt from iaset
;initialize the receive DNA channel
xo:
al, a1
out
DMAff, al
mov

blow
out
mav

blow
out
IIIOV

%slow
out
IIIOV

hlow
out
IIIOV

%slow
out
mov

ax, rz_buf_start

:set dma up to point to the beginning of rx buf

DMA7ac1c1r, al
al, ah

DMA7ac1c1r, al
ax, rz_buf"'paqe

:set rz page register

DllA7paqe, al
al, DKArx7

DMAmoc1e, al
ax, rx_buf_length

;set wordcount to proper value

DMA7wc1count, al
a1, ah,

'slow

out
mov

OMA7wdcount, a1

al, dma7unmsk

:unmask receive DNA channel

%slow
out

DMAsnglmsk, 81

;unmask our interrupt channel
in
al, InterruptHaskPort
mov
bl, OFBh
and
al, bl
blow
out

InterruptMaskPort, a1

;enable the receiver
mav
dz, command_reg
mov
al, C RXENB
out
c!x, aT
xor
ax, as.

ienable receives

290189-27

1-181

inter
Table 3. Hardware Initialization (Continued)
mov

ex, 1

init exit:
ret
ConfigDataUnderrun:
mov
ax, orrsJ:~ CGro"p: ConfigDataUnclerrunMaas
:imp
init_axit
ZASet"poataunderrun:
mov
ax, orrSE~
:imp
init_exit
Driverlnitiali.a

CG~o"p:

ZASet"pDataUnderrun

andp

SetlnterruptVector
Sat the interrupt vector to the interrupt procedure' a address
aave the old vector for tha unhook procedure
assumes: bz has the ISR off.et
al has the IRQ lavel
intarrUpts are disabled
.SetlnterruptVector
PROC
!lEAR
mask on the appropriate interrupt mask
push
ax
xchg
ax, ex
raov
dl, 1
iget the appropriata bit location
shl
d1, c1
iset the interrupt bit variable
mov
eIl.int_bit, ell.
not
raov
int mask, ell.
; set th8 interrupt mask variable
raov
az,-IntarruptMaakPort
II10V
int_mask_register, ax
pop
ax
cld
cbw
ex, ex
xor
IIIOV

as, ex

shl
shl

al, 68h
lint 4
ax, 1
'ax, 1

xchg

az, eli

add

IIIOV
IIIOV

IIIOV

mov
mov
xchg
stos"

mov

;adding 8 converts int number to int type, i.e.,
12, int 5 = ,type 13 etc.

= type

;two shifts • mul by 4 to create offset of vector

int vector addr, di
;save this address,for unhook
ax,-as: IdYl
;save old interrupt vector
word ptr old_i~vector, ax
ax, es: ldil + 2
word ptr old_i~vector + 2, ax
ax, bx
;bx has tha ISR offsat
ax, os
290189-28

stos"

ret
SetlnterruptVector

endp
290189-29

1-182

inter

AP-320

• No page break occurs. The buffer size is not adjusted, the Tx/GP buffer area will be in the first 1200
bytes of the 10 kB buffer, and the Rx area will use
the remainder.
• A page break occurs, and the buffer is divided so
that one fragment is smaller than 1200 bytes. This
fragment is too small to be used and both the
TxlGP and Rx areas will be placed in the larger
segment.
• A page break occurs that divides the 10 kB buffer
into two segments both larger than 1200 bytes. The
software then places the Tx/GP area in the smaller
segment, and the Rx area in the larger.

7.2.2 INITIALIZING SYSTEM MEMORY

A buffer is constructed in system memory to support
the Embedded LAN Module architecture. This buffer
is divided into a receive buffer area and a transmit/general-purpose buffer area. This buffer (Tx/GP) is used as
the transmit buffer and as the parameter block for
82592 commands that require parameters.
The combined size of the buffer areas requested by the
program is 10 kB. The TxlGP buffer should be at least
1200 bytes long. The Rx buffer should be at least 5 kB
long. The amount of memory requested is twice the size
of the minimum Rx buffer length because of the possibility of a DMA page break occurring at some point in
the 10 kB buffer area. A page break can occur because
the SYP301 (or any PC AT based architecture) uses a
static page register to supply the upper address bits
(A17-A23 for a 16-bit DMA channel) during a DMA
cycle. These upper bits of the address cannot be incremented. The software checks for a page break and adjusts the buffer size if one is found. There are three
possible page break scenarios.

These three scenarios are shown in Figure 12. In no
case is the Rx area less than 5 kB-half the total buffer
size. Once these calculations are m~de, the transmit
and receive DMA channels, along with their page registers, are programmed to point to their respective areas
in the buffer (Tx/GP and Rx). With the memory now
initialized, configuration and initialization of the 82592
can begin.

Buffer

Buffer

Buffer

Start

Start

Start

A

Transmit and

General Purpose
Buffer Space.

A

A

Unusable Portion
(Less than

Transmit and
General Purpose

1200 Byte.)

Buffer Space.

DMA

1200 Bytes

boundary

1200 Byte.

B

",-buLstart

B

Transmit and
General Purpose
Buffer Space.

DMA

Wasted Space

boundary

age, dz
9P_buf..l'age, 1

290189-30

1-184

inter

AP-320

Table 4. Buffer Memory Initialization (Continued)
mov

gp buf sta:t, ax
rz-buf'-start, OOOOh
rx-buf-head, DOOGh
d:&-; 1 ; next page
r%_buf-page, dx
rX_buf...,page, 1.
ax, 1
dx, 0
bz, ex
; save number of bytes to page break

mov
mov
aCd

!nOv
shl
shl
ada

mov

mov

ex, 12

shl

dx, a1

mov

rx_ buf_segment, dx

sub
mov

gp_length, bx
ex, 9P_length
rz_buf_length, ex
ex, 258h
ex, 1
cz., ax
rx_buf_stop, ex
buffers_set

mov
sub
shl

add.
mov
jmp

rx first:

- mov
shl

rz_buf"'page, dx
rz_ buf-page, 1

mov

rx buf start, ax

mov

rx-]:)uf-head, ax

shl

rx-buf-head, 1

mav

rx:buf:langth, ex

mev

:ex buf stop, OFB9Eh
; 1200 bytes from end of buffer
gp-buf-st.art., DOOOh
1 ;next paqe
gp_buf""page, dx
gp_ buf""page, 1

mov
add
. mov
shl
acld
shl.

mev
add
sub
shl

dx-;

ex, 1
ex, 1

gp_offset._adjust, ex
gp buf offset, ex

dx;

1 dx, 1

shl

ax, 1.

ado

dz, 0
oz, 12
dx, a1

mov
shl
mov
jmp

rX_buf_segment,dx
buffers_eet

copacetic:
mav gp_buf_start, ax
add ax, 258h
mov l:X bUf start, ax
mov rx-buf-head, ax
ehl. rx-bUf-head, 1
sub 9P:1Qn~h, 258h
mov ex, w_l.engtb
mav

shl.
mav
mav

rx_buf_length, ex
dz, 1
rx_buf-PBqe, dz
gp_bu.£-page, dx

;Al-Al6 of gp buffer, gp buffer is first
; 1200 bytes for gp buffer at front of buffer space
; rx buffer starts 1200 bytes in

; convert segment to byte address

290189-31
sh1

ade
mav
shl

mav
mav
sub
sh1

add
mav

ax, 1
;convert offset to byte address
; adjust segment for shift
dx, 0
ex, 12
dx, e1
; load variable for transfers to IPX
l:X_buf_segment, dx
ex, rx_ buf_l.ength
; setup marker for low rx buffer space, >600 words
ex, 258h
cz, 1
ax, ex
l:X_buf_stop, ax

buffers set:

ret-

290189-32

1-185

AP·320

area. The construction of the frame is based on .the
ECB's address information and fragment list. The
transmit DMA channel is now initialized to point to
the beginning of the transmit frame in the Tx/GP area,
and the byte count for that channel is also initialized. A
Transmit command is now issued to the 82592. A separate routine monitors the transmission for a time-out
error. When an interrupt from the 82592 indicates that
the transmission attempt is complete (whether successful or unsuccessful), or if a time-out error has occurred,
the proper completion code is inserted into the fraine's
ECB, and the ECB is passed back to IPX. If additional
ECBs remain in the transmit queue the processing of
the next ECB will begin. Table 5 contains the code used
for assembly and transmission of frames.

7.3 Assembly and Transmission of
Frames
Frame assembly and transmission ,is accomplished by
the interaction of the software driver and IPX through
the use of IPX Event Control Blocks (ECBs). To transmit a frame, a transmit ECB is prepared that contains
address information and a list of fragments in memory
containing the frame to be transmitted. This ECB is
placed in a queue for assembly and transmission of the
frame. If the queue is empty, or when the ECB reaches
the ~ront of the queue, a routine is called that processes
the ECB for transmission. This routine determines the
length of the frame (padding the frame if necessary)
and then constructs the frame in the Tx/GP buffer

Table s. Assembly and Transmission of Frames
Ddver Sand Packat
Assumes

ES:SI points to a fully prepared Event Control Block
DS
CS
Iftterrupts an DISABLED b\l.t JDay be reenabled tempoZ'arily if necessary

=

don't naad to save any registar.
DrJ.varBroaclc••tPackat:
DdvarSendl'ackat
PROC
NEAR
cU.
; disabla the interrupts
mov cz, word ptr send_list + 2
jczz AddToFrontOfList
saarch to the end of the list, and add there.
mov di, word ptr send_list
AddToListLoop:
mov da, ex
mov cx, ds: word ptr [di).link
jczz AddLiatBndFound
IIIOV
di, de: word ptr [di).link
jmp AddToListLoop
AddListEndFound :
mav .s: vom
moves: word
mov de: word
mov de: word

mov
mov

az, cs
ds, ax

ptr
ptr
ptr
ptz:

+

2

[ai] .link, ex
[s1) .link + 2, cz
'[di) . link, s1
[di].l1nk + 2, a.

;move null pOinter to newest SCB's
;link field

; sat ds back to entry condition

ret
AddTol'rontOfList:
mov a.:word ptr[s1].l1nk, ox
mov as:word ptr[d].link + 2, ox
mov word ptr .and list, ai
mav worc:l ptr .end.:list + 2, .s
dz:op through to Start Sand
DriverSendl'acket

endp

Start Send
assumes:

BS: SI
points to the BCB to ba sant.
intarllUpts are disabled
start sand

public
oli

PROC
NEAR
start sand
- ; dis.ble the interrupts

290189-33

1-186

inter

AP-320

Table 5. Assembly and Transmission of Frames (Continued)
cld
save SCB address in vsriable tx_ecb to liberate regist~rs
mov word ptr tx_ecb, si
mov word ptr tx_ecb + 2, es
push de
;save da for future uae
get XPX packet length out of the first fragment (XPX header)
lds bx, es: dword ptr [sil.fragment_dascriptor_list
mov ax, ds: [bxl.packet_length
pop ds
; restore de to CGROUP
push ax
;save length for later use in 590 length field
zchg al, ah
;byte swap for 592 length field calculation
add ax, 18
;add in the overhead bytes DA,SA,CRC,length
mov

padding, 0
ax, 64
ja
long enough
mov paddIng, 64
;minimum length frame
sub padding, ax
;pad length
!DO?
ax, 64
long_enough:
sub ax, 10
;SA and CRC are done automatically
cmp

inc
and
mev

ax
a1, OFEh
iframe must be even
tx byte ant, ax

mov

di;gp buf offset

mev bx, C8
maves, bx

-

move the byte count into the transmit buffer
stosw

move the destination address from the tx BCB to the tx buffer
mov

bx, ai

lea
mov

8i, [bxl.immediate address
de,word ptr tx_ecb-+ 2

movsw
movs..,

movsw
mov ax,es
mav cis,ax

; qet back to the coda (Dqroup) section

now the 590 length field
pop ax
xchq ah, al
inc ax
imake Bure E-Net length field is even
and al, OFBh
xchq ah, al
s~osw

1ds
mav
lea

ai, tx ecb
ax, ds: [sil.fragment count
bx, [sil.fragment_dascriptor_list

move_frag_loop:

push ds

; save the segment

ez, ds: [bxl.fragment_length
lds si, ds: [bxl.fragment_address
%fasteopy
; qet the segment back
pop de
add bx, 6
dec ax
jnz move_frag_loop

mev

290189-34

1-187

inter

AP-320

Table 5. Assembly and Transmission of Frames (Continued)
;start transmitting
mov
mov

;add any
mov
add
ahr
rep
mov
ZOE'

out
mov
blow
out

mov
%2110.
out

ex, cs
da, ex
~ired padding
ex, 4
;maka s~ra frame ends with a NOP
cx, padding
ex, 1
stosw
t,,_active_flag, 1
ax, az
DMAff, al
idat. is don't care, AX has been zeroed
ax, 9P_buf_start

DMA6addr, 81 \

a1, ah
DMA6addr, al
ax, w_bufJ'age

mov
%slow
out DNA6page, al
iDHA page value
talow
mov al, DMAtx6
; setup channel 1 for tx mode
out . DMAmode, a1
mov ax, tX_byte_cnt
add ax, 4
;add two for byte count, two for tx chain fetch
shr ax, 1
iconvert to word value and account for odd
ade ax, 0
;byte DNA transfer
out DNA61fdcount, al
%slow
mav

out
blow
mov
out

al, ah
DMA6wdcount, a1

Il10''

a1, DMA6unmsk
DMAsnglmsk, a1
dx, command reg

mev

a1, C TX

-

out dx, al
mov ax, IPXlntervalMarker
:mov tx start time, ax
',inc32 -~otal:rxPacketCount
ret

; ; ••• *****.** •••••• ******** ••• **********.,******.***.*************
Driverpoli
Poll the driver to see

i~

there is anything to do

Is there a transmit timeout? 7£ 80, abort transmdssion and return
ECB with bad completion code. Check to aee if frames

a~ ~eued.

If they are set up ES:SI and call DriverSendPacket.

;**********************************************************************
DriverPoll
c1i

PROC

290189-35

1-188

inter

AP-320

Table 5. Assembly and Transmission of Frames (Continued)
amp
jz

mav
sub

amp
jb

tx active flag, 0

Ho~WaitingonTx
dx, IPXlntervalMarker

cIz, tz start time
cIz, TxTimeOutTicks
NotTimedOutYet

Thia tranamit is taking too long so let'. terminate it now
Issue an abort to the 82592
mov
out

dx, command :ego
al, C ABORTdz, a1

inc

tx timeout

II10V

iabort transmit

les

si-;- tz eob
es: [aTl.completion_code, TransmitHardwareFailure
coda of a failed tz
II10V
ax, ea: word ptr [ail.link
II10V

mav

word ptr sand list, ax

II10V

ax, es: word ptr [ail.link + 2
word ptr send_list + 2, ax

II10V

:stuff completion

Finish the transmit
moves: [ai].in use,

call IPXHoldEvent
:make sure that execution unit didn't lock up because of abort errata
II10V
II10V

out
II10V

islow
out
II10V

islow
out
II10V

blow
out
II10V

cIz,
al,
cIz,
al,

command_reg
C_SlIPl
al
C_SELRST

cIz, al
al, C_SIIPO
cIz. al
al, C_RXENB
cIz, al
tx_active_flag, 0

See if any frames are queued
mov cx, word ptr send_list + 2
jcxz queue_empty
moves, ex
mov ai, word ptr send_list
call sta"_send
queue_empty:
NotWaitingOnTx:
NotT.imedOutYet:
ret
290169-36

1-189

inter

Ap·320

Table 5. Assembly and Transmission of Frames (Continued)
DriverPoll

endp

:*********************************** ••• **************** ••••••••••
Interrupt Procedure
j

***** •• *****.********************************,*******************

even
RxErrorType~eck:

BufferOverflow,
ino
rx buff ovflw
jmp
int_ezit
not 590 int:
-inc- no 590 int
jq> int_exIt
Dr1verISR
publio
push
push
push
push
push
push
push

PROC
DriverISR

far

ax
bx
cx
de

s1
di

bp

push dB
push es
old
int"'poll_loOp:
cli
oall IPXStartCriticalSection
mov al, EOI

;tell AES we're busy

out

%nta~~ptControlPort,

out

ExtralnterruptControlPort, al

mav

mov
mov
mov

ax,

a1

CIS

de, ax

;DS pOints to C/DGroup

de, command_reg
a1, 0
de, al
;aet status reg

out
"slow
in
al, de
teat al, SOh
jz
not_590_int
and
mov

ah, al

al, NOT 20h

amp

ah, OoSh

t~

point to reg 0

;ignore the EXEC bit
isava the status in AH

;did I receive a frame?
290189-37

1·190

intJ

Ap·320

Table 5. Assembly and Transmission of Frames (Continued)
cmp
:I z
cmp

jz

rcvoll_lOop:
and al,~:r 20h
;ignore the EXEC bit
JIIOV
ah, al
;save the status in AH
cmp ah, ODBh
:did I receive a frame?
jx
zcvdJ>acket
cmp ah, 84h
;did I finish a transmit?
jx
sentJ>acket~mp
cmp ah, Beb
;did I finish a retransmit?
jx
sentJ>acket~mp
inc false_SgO_int ;unwanted interrupt
jmp int_exit
sentJ>8cket~mp:

jmp sentJ>aCket
bad rc,;:
-inc
jmp

rx errors

RXZrzcr:rypeCheck

int_exit_jmp:
jmp int_exit
;When the address bytes are being read it is pcssible that another frame
;could come in and cause a coherency problem with the ten-cent latches.
;1 am dealing with this possibility by reading :renC8ntHi twice and making
;aure the values match. If they don't the read is re~ne.
rcvd.J>acket:
cli
JIIOV

in
Il\OV

JIIOV

dx, :renCentHi
;read high address byte of last frame received
al, dx
ah, a1
;save it in ah
dx, :renCentLo
;read low address byte of last frame received
al, dx

in
JIIOV
>:X buf tail,'ax
;this is the last location containing rx data
:Read :renCeDtHi-again to make sure it hasn't changed ..... ,.
mov dx, :renCentHi
;read high address byte again
in
al, dx
cmp al, ah
jz
addr ok
;Z8ad the latches again
jmp rcvd:packet
addr_ok:
this ia a valid address
mov ax, Z'x buf tail
this is the last location containing rz data
mav rZ_bufJ»t:r:7 ax
is most of the buffer already used?
czap rx_buf_8top, ax
ja
BufferOlC
mov

BufferOK:
cmp

ja
inc
jmp

reset rs buf, 1

-ax, >:x_buf_head
process_new_frames
ten cent latch crash
int:...it-

do next frame:
procass:naw_frames:
JIIOV
bz, rx_bufJ>tr
aub bz, 6
moves, Z'z_huf_sagment

end of current frame to process
set bx up to point to beginning of the status
this is necessary because latches hold SA not
offset relative to CGROUP
290189-41

1-194

inter

AP-320

Table 6. Receive Frame Processing (Continued)
mov
test
jnz
mov
mov
clec
ancl
sub

al, es:[bx] .status1
81,20h
goocl_rx
cl, es: [bx] .bc 10
ch, es: [bx] .bc:hi
ex

cl, Ofeh
hz, ex
amp rx buf heBcI, bx
je
hancl_off-packet_jmp
mev rx_bufJ>tr, bx
sub rx_bufJ>tr, 2
to clo next frame:
dO_next_frame
hancl_offJ>&Cket_jmp:
jmp hancl_offJ>Bcket

;teat for good receive

:cx has actual number of bytes reacl
: toss byte count & status
: rouncl up
:bx points to first location of frame
:this was the first frame in the sequence

- jmp

goocl_rx:
c~, es:[bx] .be 10
mov ch, es: [bx].bc-hi
mov curr_rx_length; ex
dec cx
ancl cl, Ofeh
sub bx, ex
mov rx_bufJtr, bx
sub rx_buf-ptr, 2
sub ex, 14
amp ex, 1024 + 64
jbe not_too_big
inc PacketRxTooBigCount
jmp clo_next_frame
not too big:
-amp- ex, 30
jae not_too_small

mav

iCX

has actual number of bytes read

; toss byte count , status
; round up

:bx points to first location of frame

=

:rx_buf-ptr
last location of n-l frame
: sub length of 802.3 header

inc PacketRxTooSmallCount
jmp clo next frame
not_t.oo_small: -

mav ax, es:[bx] .rx length
xchg al, ah
inc

get

rpx length

ax

ancl al; Ofeh
xchg al, ah
amp ax, es:[bx].rx-physical_length
to do next frame
xchg a1; ah
amp ax, 60 - 14

; same as 802.3 length?

jne

ja
mov
len_ok:
amp
jz

; at least mdn length minus header
; yes, continue
; no, round up

len ok
a",-60 - 14
ax, cx

: match physical length

not_inconsistent

; yes, continue

inc HarclwareRxMismatchCount
jmp cIo_next_frama
not inconsistent:
-'inc32 TotalRxPacketCount
mov

ax, 12

mul

num_of_frames

Double Word Increment

290189-42

1-195

inter

Ap·320

Table 6. Receive Frame Processing (Continued)
mov

di, ax

mav
add

rx list [di], bx
rx-list [di] , 14

:first location of ethernet frame
:first location of ipx packet

mov

ax~ rx_buf_segment

mav
mav

rx list [di + 2], ax
ax; word ptr es:[bx].rx length

xchg a1,ah

-

mav
mav
mav

rx list [di + 4], ax
ax; word ptr es: [bx]."",_source_addr
word ptr rx list [di + 6], ax

mov

ax, word ptr as: [bx] . rx source addr -I- 2

mav

+

0

word ptr rx_list [di.+ i], ax-

mav

ax, word ptr es:[bx].rx source addr -I- 4

mav

word ptr rx_list [di

add

num of fratrLas, 1

+ 10], ax-

CII9i' . rx buf-head, bx

je
CII9i'

je
jmp

hand_off-paeket
num of f:cames, 50
hand_off-packet
do_next_frame

hand_off-packet :
mav ai, rx list[di]
mav as, rx-list[di -I- 2]
mav cx, rx:list[di + 4]
les bx, rx_list[di -I- 6]
cli
push da
call IPXReceivePacket
pop ds
sub

num of frames, 1

jz

adjust-rx head
di,.12- jmp hand_off-packet
adjust rx head:
sub

mo;
add
mov

ax,
ax,

rx but tail
2 rx buf head, ax

-

-

;ast rx_buf_head to new value for next receive

:inter:cupt

int exit:
-push cs

pop
CII9i'

jnz

ds
tx_active_flag, 0
finish_exit

ve:cify that our receiva:c is still going.
mov

mav
out
%slow

in
test
jnz
jmp

dx, ccmmand_reg
al, 60h
dx, a1

;point to status byta 3

al, dx
al, 20h
finish exit
LostOUrReceive:c

finish exit:

eli

290189-43

1-196

Ap·320

Table 6. Receive Frame Processing (Continued)
call
mov
mov
out.

'81o"

xor

out
%alo",

IPXEndCriticalSect.ion
dz, coltlltand_reg
al, C_INTAClt
dx, 81
; issue interrv.pt acknowledge to the 590

al, a1.
dx, a1

; set status reg to point to reg 0

in
al, dx
test al, SOh
jnz intJ"'nding
c:mp reset rx buf, 1

jnl:
moy
Qut
,"slow
out
mov
mov
shl

no_Z'z.:buf_reset
al, dma7msk
CMA8nglmsJc, a1
CHAff, a1

ax, rx bu! start
rx but-heaCi, ax
:cx-buf-head, 1

out

OMA7addr, a1

mov

al, ah

;mask receive DMA

ch~nnel

:data i" don't care
; set dma up to point to the beginning of rx buf

tslow
Qut

mov
'slow

out
mov

'slov
out
mov

'slow
out
mov

mov

DMA'7adc1r, a1

al, OMArx7
DMAmacie, a1
ax, l:X_buf_l.enqth

; set up

rx buf

DMA7wdcount, a1
al, ah
DMA7wdeount, a1
dx, DMAsnglmsk

a1., DHA7unm.sk

IbloW'
out.

dx, a1

mov

dx, command_reg

mov

al, C RXENB
dx, aT

out
mov

reset_Z'z_buf,

no rx buf reset:

- eli -

call 'IPXServiceEvents
pop as
pop ds-

pop
pop
pop
pop
pop
pop

bp
di
si
cIx
ex
b"

pop

ax

290189-44

aU
iret
LostOurReceiver:
inc l.ost rx
1l\OY
al., C RXENB
mov dx, command reg
out d:c., al.
jmp finish_ ent

too_big:
.inc PacketRxOverfl.oWCount
jmp int_ent
int..,pending:
jmp intJ'oll_loop

290189-45

1-197

inter

AP-320

APPENDIX A
Expanding the 82592 Embedded LAN
Module Architecture to a Low-Cost ,
Non-Buffered Adapter

ADAPTER BLOCK DESCRIPTIONS
DMA Machine

The basic architecture ef the 82592 Embedded LAN
Medule can be expanded and applied to. a lew-cest,
nen-buffered adapter. This requires adding a DMA
unit and seme legic fer a bus master handshake. Such
an adapter would centain no. lecal bUffer memery. Its
cest advantage weuld ceme frem using existing system
memery, as the embedded medule dees. This adapter is
less cemplex than mest existing designs because it does
net require arbitratien legic fer access to. lecal memery.
This adapter becemes a bus master when data transfers
take place, either to. the 82592 (Tx) from system memery er frem the 82592 (Rx) into. system memery.
The same features ef the 82592 that make it successful
in embedded applicatiens make it well-suited fer nenbuffered adapters. As with the embedded medule, there
is no. intermediate buffering ef data in a lecal memery,
therefere data transfers to. and frem system memery
take place in real time. The 82592's large FIFO area
allews it to. telerate leng system bus latencies during
memery access. The 82592's high-perfermance, 16-bit
bus interface allews the adapter to. efficiently transfer
data to. and frem system memery when it gains access
to. the system bus. The TCI ef the 82592 will interface
with the adapter's centrellegic and DMA unit to. previde back-te-back frame receptien and autematic retransmissien en cellisien (both witheut CPU interventien). Figure 13 is a bleck diagram ef the basic architecture ef the embedded medule medified fer a nen-buffered adapter applicatien. The bleck titled "Centrel
PALs and Latch" tegether with the 82592 is the cere ef
the embedded medule architecture. One additienal
PAL (PAL C) has been added to. the basic architecture
to. effer mere legic fer deceding additienal cemponents
added to. the adapter. The address latch has alSo. been
,expanded to. 24 bits. The three shaded blecks (DMA
Machine, Master Legic, and Centrel PALs and Latch)
show the mest likely path fer integration on this adapter, providing a three-chip solutien ef ASIC, 82592, and
82C501. 'The 82C37 is commen in many ASIC cell Iibraries, effering a migratien path for this integration.

• 8237 DMA Controller. Serves as the core' fer the
DMA machine. Performs addressing and centrol fer
data transfers between the 82592 and hest system
memery.
• 8-Bit Page Counter. Provides the addressing bits fer
the upper bits ef address (A17-A23)'
• 8·Bit Register. Serves as the base register fer the
upper bits of the Tx DMA channel fer reinitializatien for automatic retransmission.
• 8-Bit Multiplexer. Selects between the upper bits of
Rx- er Tx-channel DMA.
• 8-Bit Latch. Latches the upper bits of address frem
the 8237 (AS-A IS).

Master Logic
• Master PAL. Implements a "master" handshake
with the hest system bus to gain access to. the bus as
a bus master.
• Timers (2). Contrels the maximum time the adapter
can held the bus, and the minimum time it must
wait befere attempting to. regain bus access.

Control PALs and Latch (Together
with 82592 and 82C501)
The basic architecture of the 82592 Embedded LAN
Medule.

Transceivers
Used to. buffer the adapter legic frem the hest system
bus, fer drive purpeses. Address consists.ef24 bits; and
Data, 16 bits.

1-198 .

1::
WR

DNA Woellin.

I

'I
c0

..

iii
CII

>

l-

e(

5 IolHz

I~

~
N

::t:

:2

I!
Q

0

IolRD
IolRW
lORD
10WN

0
C'oI

'I ;.)

·1_8

2

I

,.

2

}Z

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I

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I

I

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iii

l

u

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0

lORD
IOWR

fom:OA

a.

LANHIB
2. C: > IUPHIB
If the TSMS program is to be run on the iSBC 186/51,
steps required are:
1. C:>SBC
2. C: > IUPSBC

4.2 Capabilities and Limits of the
TSMS Program
The TSMS program initializes the LANHIB Ethernet!
Cheapernet station by executing 82586's Diagnose,
Configure, lA-Setup, and MC-Setup commands. The
program asks a series of questions in order to set up a
linked list of these 82586 commands. After initialization is completed, the program automatically starts the
82586's Receive Unit (monitoring capability). Transmissions are optional (traffic simulation capability).
The TSMS program has two modes of operation: Continuous mode and Interactive Command Execution
mode. The program automatically gets into the Continuous mode after initialization. The Interactive Command Execution mode can be entered from the Continuous mode. Once entered in the  Y
Enter byte number (1 - 11) _a> 4
Enter byte 4 (4H)
A6H
Any more bytes? (Y or N) _a> Y
Enter byte number (1 - 11) _a> 11
Enter byte 11 (BH) _a> 6
Any more bytes? (Y or N)
N
Configure the 586 with the prewired board addres~ _a> N
Enter this station's address in Hex ••> 000000002200
You can enter up to 8 Multicast Addresses.
Would you like to enter a Multicast Address? (Y or N) ==> N
You entered 0 Multicast Address(es).

._>

-->

Would you like to transmit?
Enter a Y or N
Y
Enter a destination address in Hex

-->

==>

000000002200

Enter TYPE _a> 0
How many bytes of transmit data?
Enter a number =-> 2
Transmit Data is continuous numbers (0, 1, 2, 3, ••• )
Change any data bytes? (Y or N) ==> N
Enter a delay count -=> 10000000000
The number is too big.
It has to be less than or equal to 65535 (FFFFH).
Enter a number _a> 60000
setup a transmit terminal count? (Y or N)
Enter a transmit terminal count ==> 500

==>

Y

Destination Address: 00 00 00 00 22 00
Frame Length: 20 bytes
Time Interval between Transmit Frames: 30.18 miliseconds
Network Percent Load generated by this station:
.0'
Transmit Frame Terminal Count: 500
Good enough? (Y or N)

==>

Y

Receive Unit is active.

292010-16

Figure 14. External Loopback Execution

1·216

inter

AP-274

---Transmit Command Block--0000 .at 033E
8004
FFFF
034E
2200
0000
0000
0000
Hit  to countinue
transmission started!

**************************** station Configuration *************************
Host Address: 00 00 00 00 22 00
Multicast Address(es): No Multicast Addresses Defined
Destination Address: 00 00 00 00 22 00
Frame Length: 20 bytes
Time Interval between Transmit Frames: 30.18 miliseconds
Network Percent Load generated by this station:
.0 %
Transmit Frame Terminal Count: 500
82586 Configuration Block: 08 00 A6 00 60 00 F2 00

00

06

***************************** station Activities ***************************
1# of Good
Frames
Transmitted
500

1# of Good
Frames
Received
500

CRC
Errors

Alignment
Errors

a

a

No
Resource
Errors

a

Receive
Overrun
Errors

a

292010-17

Figure 14. External Loopback Execution (Continued)

1-217

inter

AP-274

Traffic Simulator and Monitor Station Program

Initialization bequn
Configure command is set up for default values.
Do you want to change any bytes? (Y or N) .~> Y
Enter byte number (1 - 11) _a> 9
Enter byte 9 (9H) _a> 1
Any more bytes? (Y or N) ._> N
Confiqure the 586 with the prewired board address =z> Y
You can enter up to 8 Multicast Addresses.
Would you like to enter a Multicast Address? (Y or N) ==> N
You entered 0 Multicast Address(es).
Would you like to transmit?
Enter a Y or N =-> N
Receive unit is active.

**************************** Station Configuration ************************
Host Address: 00 AA 00 00 18 6D
Multicast Address(es): No 'Multicast Addresses Defined
82586 configuration Block: 08 00 26 00 60 00 F2

01

00

40

*.* •••••••••••••••• ********** Station Activities ********** •••••• **.*******

*

*

of Good
of Good
CRC
Frames
Frames
Errors
Transmitted Received
o
100
0
Enter command (H for help) ==>,D

Alignment
Errors

o

No
Resource
Errors

o

Command Block or Receive Area? (R or C) ..-> R
Frame Descriptors:
4000 at 036C AOOO at 0382 AOOO at 0398 AOOO at 03AE
0000
0000
0000
0000
0382
0398
03AE
03C4
03DA
03E4
03EE
03F8
2200
2200
2200
2200
2200
2200
2200
2200
0000
0000
0000
0000

Receive
OVerrun
Errors

o

AOOO at 03C4
0000
036C
0402
2200
2200
0000
292010-18

Figure 15. Frame Reception In Promiscuous Mode

1-218

Ap·274

0000
0000
0000
0000

0000
0000
0000
0000

0000
0000
0000
0000

Receive Buffer Oescriptors:
C064 at 030A C064 at 03E4 C064 at 03EE
03F8
03EE
03E4
OFEO
09F6
040C
0000
0000
0000
050C
050C
050C

0000
0000
0000
0000

0000
0000
0000
0000

C064 at 03F8
0402
15CA
0000
050C

C064 at 0402
030A
1BB4
0000
050C

Oisplay the receive buffers? (Y or N) ==> Y
Receive Buffers:
Receive Buffer 0
002C:014C 00 01
002C:015C 10 11
002C:016C 20 21
002C:017C 30 31
002C:018C 40 41
002C:019C 50 51
002C:01AC 60 61

:
02
12
22
32
42
52
62

03
13
23
33
43
53
63

04
14
24
34
44
54

05
15
25
35
45
55

06
16
26
36
46
56

07
17
27
37
47
57

08
18
28
38
48
58

09
19
29
39
49
59

OA
1A
2A
3A
4A
5A

OB
1B
2B
3B
4B
5B

OC
1C
2C
3C
4C
5C

00
10
20
30
40
50

OE
lE
2E
3E
4E
5E

OF
1F
2F
3F
4F
5F

03
13
23
33
43
53
63

04
14
24
34
44
54

05
15
25
35
45
55

06
16
26
36
46
56

07
17
27
37
47
57

08
18
28
38
48
58

09
19
29
39
49
59

OA
1A
2A
3A
4A
5A

OB
1B
2B
3B
4B
5B

OC
1C
2C
3C
4C
5C

00
10
20
30
40
50

OE
1E
2E
3E
4E
5E

OF
1F
2F
3F
4F
5F

03
13
23
33
43
53
63

04
14
24
34
44
54

05
15
25
35
45
55

06
16
26
36
46
56

07
17
27
37
47
57

08
18
28
38
48
58

09
19
29
39
49
59

OA
1A
2A
3A
4A
5A

OB
1B
2B
3B
4B
5B

OC
lC
2C
3C
4C
5C

00
10
20
3D
40
50

OE
1E
2E
3E
4E
5E

OF
1F
2F
3F
4F
5F

03
13
23
33
43
53
63

04
14
24
34
44
54

05
15
25
35
45
55

06
16
26
36
46
56

07
17
27
37
47
57

08
18
28
38
48
58

09
19
29
39
49
59

OA
1A
2A
3A
4A
5A

OB
lB
2B
3B
4B
5B

OC
1C
2C
3C
4C
5C

00
10
20
30
40
50

OE
1E
2E
3E
4E
5E

OF
1F
2F
3F
4F
5F

Hit  to countinue
Receive Buffer 1
002C:0736 00 01
002C:0746 10 11
002C:0756 20 21
002C:0766 30 31
002C: 0776 40 41
002C:0786 50 51
002C:0796 60 61

:
02
12
22
32
42
52
62

Hit  to countinue

I

Receive Buffer 2
002C:0020 00 01
002C:0030 10 11
002C:0040 20 21
002C:0050 30 31
002C:0060 40 41
002C:0070 50 51
002C:0080 60 61

:
02
12
22
32
42
52
62

Hit  to countinue
. Receive Buffer 3
002C:130A 00 01
002C: 131A 10 11
002C:132A 20 21
002C:133A 30 31
002C:134A 40 41
002C:135A 50 51
002C:136A 60 61

:
02
12
22
32
42
52
62

Hit  to countinue
292010-19

Figure 15. Frame Reception in Promiscuous Mode (Continued)

1-219

inter

AP-274

Receive Buffer 4
002C:18F4 00 01 02
002C:1904 10 11 12
002C: 1914 20 21 \22
'002C: 1924 30 31 32
002C:1934 40 41 42
002C:1944 50 51 52
002C:1954 60 61 62

03
13
23
33
43
53
63

04
14
24
34
44
54

05
15
25
35
45
55

06
16
26
36
46
56

07
17
27
37
47
57

08
18
28
38
48
58

09
19
29
39
49
59

OA
1A
2A
3A
4A
SA

OB
1B
2B
3B
4B
5B

OC
1C
2C
3C
4C
5C

OD
1D
2D
3D
4D
5D

OE
lE
2E
3E
4E
5E

OF
IF
2F
3F
4F
SF

Hit  to countinue
Enter command (H for help) ==> E

****************************

station Co figuration

*************************

Host Address: 00 AA 00 00 18 6D
Multicast Address(es): No Multicast Addresses Defined
82586 cop figuration Block: 08 00 26 00 60 00 F2

*****************************
II of Good
Frames
Transmitted

a

station Activities

*Frames
'of Good

CRC
Errors

Alignment
Errors

Received
100

0

0

01' 00

40

**************************
No
Resource
Errors
0

Receive
OVerrun
Errors
0
292010-20'

Figure 15. Frame Reception in Promiscuous Mode (Continued)

1-220

inter

AP-274

Traffic Simulator and Monitor Station Program

Initialization begun
Configure command is set up for default values.
Do you want to change any bytes? (Y or N) ==> N
configure the 586 with the prewired board address ==> Y
You can enter up to 8 Multicast Addresses.
Would you like to enter a Multicast Address? (Y or N) ==> N
You entered 0 Multicast Address(es).
Would you like to transmit?
Enter a Y or N ==> Y
Enter a destination address in Hex ==> FFFFFFFFFFFF
Enter TYPE ==> 0
How many bytes of transmit data?
Enter a number ==> 100
Transmit Data is continuous numbers (0, 1, 2, 3, ••• )
Change any data bytes? (Y or N) ==> N
Enter a delay count ==> 0
setup a transmit terminal count? (Y or N) ==> N
Destination Address: FF FF FF FF FF FF
Frame Length: 118 bytes
Time Interval between Transmit Frames: 159.4 microseconds
Network Percent Load generated by this station: 35.7 %
Transmit Frame Terminal Count: Not Defined
Good enough? (Y or N) ==> Y
Receive Unit is active.
---Transmit Command Block--0000 at 033E
8004
FFFF
034E
FFFF
FFFF
FFFF
0000
Hit  to countinue

292010-21

Figure 16. 35.7% Network Load Generation

1-221

inter

AP-274

transmission started I

****************************

station configuration

************************

Host Address: 00 AA 00 00 l86D
Multicast Address(es): No Multicast Addresses Defined
Destination Address: FF FF FF FF FF FF
Frame Length: 118 bytes
Time Interval.between Transmit Frames: 159.4 microseconds
Network Percent Load generated by this station: 35.7 %
Transmit Frame Terminal Count: Not Defined
82586 Configuration Block: 08 00 26 00 60 00 F2 00 00

*****************************

station Activities

**************************

Alignment
Errors

# of Good
# of Good
CRC
Frames
Frames
Errors
Transmitted Received
10459
0
0
Enter command (H for help) ==> H

40

No
Resource
Errors

o

o

Receive
Overrun
Errors

o

- Commands are:
D - Display RFD/CB
S - setup CB
C - SCB Control CMD
P
Print SCB
N
- ESI Loopback Off
ESI Loopback On
L
A
Toggle Number Base
Z
Clear Tx Frame Counter
Y
Clear Rx Frame Counter
E
Exit to continuous Mode
Enter command (H for help)
Enter command block type
Command block type:
N - Nop
I C - Configure
M T - Transmit
R D - Diagnose
S H - Print this message

==>

S

(H for help)

H

==>

S

IA setup
MA setup
TDR
Dump status

Enter command block type (H for help)
Enter command (H for help)

==>

==>

C

Do you want to enter any SCB commands? (Y or N)
Enter. CUC ==> 1
Enter RES bit ==> 0
Enter RUC ==> 0
Issued Channel Attention

==>

Y

Enter command (H for help) ==> D
292010-22

Figure 16.35.7% Network Load Generation (Continued)

1-222

inter

AP-274

Command Block or Receive Area? (R or C)
---Dump status Command Block--AOOO at 0364
8006
FFFF
27D6
Dump status Results
at 27D6
00 E8 3F 26 08 60
AA 00 40 20 00 00
62 63 3F BO 00 00
00 00 00 00 00 00
DC 05 00 00 OC 04
82 03 6C 03 F8 03
06 80 FF FF 64 03
00 00 D6 27 00 01
20 00 40 06 30 01
00 00 6A 03 OE 00
00 00 00 00 00 CO

00
00
00
00
DC
64
00
00
00
6C
00

Enter command (H for help)

FA
00
00
00
05
80
00
28
00
28
00

00
FF
00
00
E4
D6
D2
00
90
00
00

==>

S

00
FF
00
00
03
27
02
00
00
00
00

==>

40
FF
00
00
DA
E8
00
00
10
74

C

FF
FF
00
00
03
21
00
00
01
03

6D
B5
FF
70
DA
FF
00
30
00
00

18
9E
85
03
03
FF
00
26
00
00

00
EE
08
06
78
4E
00
00
6C
00

00
CF
FC
00
05
03
00
00
03
00

Enter command block type (H for help) ==> T
Enter a destination address in Hex ==> FFFFFFFFFFFF
Enter TYPE ==> 0
How many bytes of transmit data?
Enter a number ==> 100
Transmit Data is continuous numbers (0, I, 2, 3, ..• )
Change any data bytes? (Y or N) ==> N
Enter a delay count

==>

0

Setup a transmit terminal count? (Y or N)

==>

N

Destination Address: FF FF FF FF FF FF
Frame Length: 118 bytes
Time Interval between Transmit Frames: 159.4 microseconds
Network Percent Load generated by this station: 35.7 %
Transmit Frame Terminal Count: Not Defined
Good enough? (Y or N)

==>

Enter command (H for help)

Y

==>

C

Do you want to enter any SCB commands? (Y or N)
Enter CUC ==> 1
Enter RES bit ==> 0
Enter RUC ==> 0
Issued Channel Attention

==>

Y

292010-23

Figure 16.35.7% Network Load Generation (Continued)

1-223

inter

Ap·274

**************************** station Configuration *,***********************
Host Address: 00 AA 00 00 18 60
Multicast Addressees): No Multicast Addresses Defined
Destination Address: FF FF FF FF FF FF
Frame Length: 118 bytes
Time Interval between Transmit Frames: 159.4 microseconds
Network Percent Load generated by this station: 35.7 %
Transmit Frame Terminal Count: Not Defined
82586 configuration Block: 08 00 26 00 60 00 F2 00 00

40

***************************** Station Activities **************************
# of Good
Frames
Transmitted
106020

# of Good
Frames
Received
0

CRe
Errors

Alignment
Errors

0

0

No
Resource
Errors
0

Receive
Overrun
Errors
0
292010-24

Figure 16. 35.7% Network Load Generation (Continued)

5.0 IN CASE OF DIFFICULTV
This section presents methods of troubleshooting ("debugging") a LANHIB board. When a LANHIB board
is powered up with the TSMS program stored in
EPROMs, it should display "TRAFFIC SIMULATOR AND MONITOR STATION PROGRAM"
message on a terminal screen. If the message is not
displayed, the board has to be debugged. Section 5.1
describes basic- 80186/82586 system troubleshooting
procedures. Section 5.2 is for troubleshooting 82501
and 82502 circuits. After the 80186/82586 system is
debugged, the 82501/82502 circuits have to be tested.

and the other debugs the 80186/82586 system. The
waveform of the TRXCB output of the 82530 determines which path to be taken. If the 82530 is getting
programmed properly, there should be 153.6 KHz
(1/f = 6.51 p.s) clock on this output pin. If there is a
clock, the problem is probably in the RS-232 interface.
If there is no clock, then the system has to be debugged
using a logic analyzer.

'5.2 Troubleshooting 82501/82502
Circuits
If the TSMS program runs on the LANHIB but the
82586 is not able to transmit or receive, there must be a
problem in 82501/82502 circuits. The flow chart in
Figure 19 will guide troubleshooting in these circuits.
An oscilloscope is required.

5.1 Troubleshooting 80186/82586
System
Shown in Figure 17 is a flow chart for troubleshooting
80186/82586 system. The procedure requires an oscilloscope. A logic analyzer is needed if problems appear '
to be serious. The procedures will de~ug the board to
the point where the 82530 is initialized properly. If the
82530 can be initialized properly, ROM and RAM interfaces must be functioning. Board initialization routines (INIl86.PLM) linked to the TSMS program requires ROM and RAM accesses. Since the '82586
shares most of the system with the 80186, no special
debugging is required for the 82586. Wiring of all
82586 parallel signal pins should, however, be checked.
The flow chart branches to two major paths after the
first decision box. One path debugs the RS-232 channel

The board should be configured to Cheapernet and disconnected from the network. Two terminators will be
required to terminate a "T" BNC connector providing
an effective load resistance of 250 to the 82502.
The 82586 must have the system and transmit clocks
running upon reset. Since the transmit clock is generated by the 82501, the 82501 transmit clock output pin
(pin 16) should be checked. The TSMS program executes 82586's Diagnose, Configure, lA-Setup, and MCSetup commands during initialization. If the 82586 has
active CRS (Carrier Sense) signal, it cannot complete
execution of these commands. The 82501 should, therefore, be checked if it is generating inactive CRS signal
to the 82586 after power up. The LANHIB powers up
the 82501 i~ non-Ioopback mode.

1-224

AP-274

After making sure that the 82501 is generating proper
signals to the 82586, the TSMS program is restarted
with an initialization shown in Figure 20. The 82586 is
configured to EXT-LPBK= 1, TONO-CRS= I, and
MIN-FRM-LEN=6. The chip is also loaded with a
destination address identical to the source address. If
there are no problems in the 82501/82502 circuits, the
station will be receiving its own transmitted frames. If
problems exist, the station will only be transmitting.
Since the 82586 is configured to TONO-CRS (Transmission On NO Carrier Sense), the chip will keep trans-

(
-

YES

mitting regardless of the state of carrier sense. The
82501/82502 circuits can then be probed with an oscilloscope at the locations indicated in Figure 21. Probing
will catch problems like wiring mistakes, missing load
resistors, etc.
Once the station is debugged, it can be connected to the
network. If there is a problem in the network, the
82586's TDR command can be used to find the location
and nature of the problem.

)

START

I

IS "TRAffiC SIMULATOR AND
MONITOR STATION PROGRAM"
MESSAGE ON CRT?

NO

(HAVE AN OSCILLOSCOPE READY)

(

START DEMO

)
~

CHECK CLOCK WAVEFORM ON THE
TRXCB PIN(PIN 26) OF THE 82530
NO
USING AN OSCILLOSCOPE.
IS IT 153.6KHz(l/f=6.51 J.Lsec.}
SQUARE WAVE?

CHECK RS-232 DRIVER &
RECEIVER CHIPS. ARE THEY
CONNECTED PROPERLY? NOTE
THAT THE 1488(75188)
REQUIRES +12V & -12V AND
THAT THE 1489(75189}
REQUIRES ONLY +5V.

"-

CHECK RS-232 DCE & DTE
CONNECTIONS. THE LANHIB IS
A DCE AND AN ASCII TERMINAL
IS A DTE. ONLY PIN2(TXD}.
3(RXD}. AND 7(GROUND} ARE
USED.

"-

CHECK CONFIGURATION OF THE
ASCII TERMINAL. BAUD RATE
SHOULD BE SET TO 9600.
ALSO 8 BITS/CHAR. NO PARITY.
AND 2 STOP BITS/CHAR.

(

"START DEMO

(A LOGIC ANALYZER
MAY BE REQUIRED.)

CHECK CLOCK WAVEFORM ON THE
FOLLOWING PINS:
1. CLKOUT PIN(PIN 56} OF B0186
THIS SHOULD BE 8 MHz 50% DUTY
CYCLE MOS CLOCK.
2. CLK PIN(PIN 32} OF 82586.
THIS CLOCK IS PROVIDED BY 80186.
3. CLK PIN(PIN 20} OF 82530.
THIS SHOULD BE 4 MHz CLOCK.

"-

CHECK SIGNAL LEVELS OF THE FOLLOWING
80186 INPUT PINS.
1. RES PIN(PIN 24} SHOULD BE HIGH
AFTER POWER UP RESET.
2. NMI PIN(PIN 46) SHOULD BE LOW.
3. SRDY PIN(PIN 49} SHOULD BE HIGH.
4. ARDY PIN(PIN 55) SHOULD BE HIGH.
5. HOLD PIN(PIN 50} SHOULD BE LOW.
82586 IS NOT INITIALIZED YET.

ctJ

)
292010-25

Figure 17. Flowchart for 80186/82586 System Troubleshooting

1-225

AP-274

CONNECT A LOGIC ANALYZER ON THE
MULTIPLEXED BUS.
1. CONNECT ADI5-ADO, ALE, RD, WR, ROMHI
ROMLO, RAMHI, RAMLO, AND CS PIN(PIN 33)
OF 82530.
2. USE CLKOUT OF 80186 TO CLOCK THE
LOGIC ANALYZER. SAMPLE DATA ON RISING
EDGES.
3. TRIGGER THE LOGIC ANALYZER ON ALE
BECOMING HIGH.

~

CHECK RS-232 DRIVER lie
RECEIVER CHIPS. ARE THEY
CONNECTED PROPERLY? NOTE
THAT THE 1488(75188)
REQUIRES + 12V lie -12V 'AND
THAT THE 1489(75189)
REQUIRES ONLY +5V.

SHOWN IN FIGURE 18 IS AN EXAMPLE OF A
LOGIC ANALYZER TRACE. COMPARE WHAT'S
OBTAINED TO THE ONE IN FIGURE 18.
II' DIFFERENT. POSSIBLE PROBLEMS ARE:
1. HIGH BYTE EPROM AND LOW BYTE EPROM
ARE SWAPPED.
2. ADDRESS/DATA LINES ARE NOT CONNECTED'
PROPERLY.
3. ADDRESS DECODE PAL IS NOT PROGRAMMED
PROPERLY.

.1CHECK RS-232 DCE lie DTE
CONNECTIONS. THE LANHIB IS
A DCE AND AN ASCII TERMINAL
IS A DTE. ONLY PIN2(TXD),
3(RXD), AND 7(GROUND) ARE
USED.

etc.

.1-

CHECK II' 82530 IS GmlNG INITIALIZED PROPERLY
ON THE LOGIC ANALYZER. TRY OTHER LOGIC
ANALYZER TRIGGERING EVENT, 8.g. CS PIN(PIN 33)
OF 82530 BECOMING LOW.
,
MAKE SURE THERE IS 153.6 KHz(l/f= 6.51 },S8C.)
SQUARE WAVE ON TRXCB(PIN 26) OF 82530.

CHECK CONFIGURATION OF THE
ASCII TERMINAL. BAUD RATE
SHOULD BE SET TO 9600.
ALSO 8 BITS/CHAR, NO PARITY,
AND 2 STOP BITS/CHAR •

.1-

(

START DEMO

)

292010-26

292010-27

Figure 17. Flowchart for 80186/82586 System Troubleshooting (Continued)

1-226

AP-274

. - - - - - - - - AD15-ADO
. - - - - - - - ALE
,-----RD#

.,.....-,

jjj

1r~

~~~: 1rn~EA" .~m ~.
~~~L~~

Sa=

(PIN 33) OF 82530

009700 41 01001111
00980041 01001111
009900 41 01101111
TRIG 0041 11101111 · .... LOGIC ANALVZER IS TRIGGERED ON ALE HI.
0101 FF FO 01001111 · .... 80186 JUMPS TO FFFOH AFTER RESET.
010206 EA 00101111 • .... JMP INSTRUCTION (DIRECT INTERSEGMENT)
010306 EA 00101111
SEGMENT OFFSET = 0006H
010406 EA 00101111
SEGMENT SELECTOR = FFCOH
010506 EA 00101111
(80186 INSERTS 3 WAIT STATES BEFORE
010606 EA 00101111
UMCS REGISTER IS PROGRAMMED.)
010706 EA 11101111
0108 FF F201101111
0109 CO 40 00101111
0110 CO 00 00101111
0111 CO 00 00101111
0112 CO 00 00101111
0113 CO 00 00101111
0114 CO 00 11101111
0115 FF F401101111
0116 FF FF 00101111
0117 FF FF 00101111
0118 FF FF 00101111
0119 FF FF 00101111
0120 FF FF 00101111
0121 FF FF 11101111
0122 FF F6 01101111
012300 40 00101111
0124000000101111
0125 00 00 00101111
0126 00 00 00101111
0127000000101111
0128 00 00 11101111
0129 FC 06 01101111 ..... JUMPED TO FC06H
0130 2E FA 00101111
0131 2E FA 00101111
0132 2E FA 00101111
0133 2E FA 00101111
0134 2E FA 00101111
0135 2E FA 11101111
0136 FC 08 01101111
0137 16 8E 00101111
0138 16 8E 00101111

=

Figure 18. Example of Logic Analyzer Trace.

1·227

292010-28

AP-274

(

START

)

1
DISCONNECT COAX. PUT TERMINATORS ON
BOTH ENDS OF "T" CONNECTOR. MAKE SURE
THE BOARD IS CONFIGURED TO CHEAPERNET.

UPON POWER UP, DOES
82501 GENERATE:
1. 10 101Hz Tx C AND R x C ..N;..O_ _.,
r-_ _ _ _-"'YE;;.;S~
TO 82586?
2. INACTIVE CRS
RUN TSMS PROGRAM.
TO 82586?

I

I

I

.....

'--~-~...----WHEN A TRANSMISSION IS

~ ATIEMPTED, DOES THE TSMS' ~
PROGRAM DISPLAY "NO
CARRIER SENSE" MESSAGE?

POWER DOWN AND RESTART TSMS PROGRAM
WITH 82586 CONFIGURED
TO:
1. EXT-LPBK = 1
2. TONO-CRS 1
3. MIN-FRM-LEN 6
EXECUTE LOOPBACKS BY
USING DESTINATION ADDR
SAME AS SOURCE ADDR.
TRANSMIT ONLY A FEW
DATA BYTES.

=

82501/82502 CIRCUITS
MUST BE WORKING O.K.
IF THE STATION IS STILL
NOT RECEIVING, CHECK
STATION'S DESTINATION
AND SOURCE ADDRESSES,
CONFIGURATION OF 82586.

=

I

MAKE SURE THE 82501 IS
POWERED UP IN NONLOOPBACK MODE.

I

AN EXAMPLE EXECUTION
IS SHOWN IN FIGURE 20.
IF THE STATION IS NOT
RECEIVING WHILE IT'S
TRANSMITIlNG, THERE IS
A PROBLEM. PROBE
SIGNALS AT LOCATIONS
SHOWN IN FIGURE 21.
IT'S PROBABLY A WIRING
PROBLEM.

I
(

BOARD SHOUtD BE FUNCTIONAL.

)
292010-29

Figure 19. Flowchart for 82501/82502 Circuits Troubleshooting

1-228

AP-274

Traffic Simulator and Monitor Station Program
Initialization begun
configure command is set up for default values.
Do you want to change any bytes? (Y or N) =~> Y
Enter byte number (1 - 11) ==> 4
Enter byte 4 (4H) ==> A6H
Any more bytes? (Y or N) ==> Y
Enter byte number (1 - 11) =-> 9
Enter byte 9 (9H) ==> 08H
Any more bytes? (Y or N) ==> Y
Enter byte number (1 - 11) ==> 11
Enter byte 11 (BH) ==> 6
Any more bytes? (Y or N) ==> N
Configure the 586 with the prewired board address ==> N
Enter this station's address in Hex ==> 000000002200
You can enter up to 8 Multicast Addresses.
Would you like to enter a Multicast Address? (Y or N) ==> N
You entered 0 Multicast Address(es).
would you like to transmit?
Enter a Y or N ==> Y
Enter a destination address in Hex

==>

000000002200

Enter TYPE ==> 0
How many bytes of transmit data?
Enter a number ~=> 2
Transmit Data ie continuous numbers (0, 1, 2, 3, •.• )
Change any data bytes? (Y or N) ~~> N
Enter a delay count ==> 0
setup a transmit terminal count? (Y or N) ==> N
Destination Address: 00 00, 00 00 22 00
Frame Length: 20 bytes
Time Interval between Transmit Frames: 159.4 seconds
Network Percent Load generated by this station: 11.0 %
Transmit Frame Terminal Count: Not Defined
Good enough? (Y or N)

==>

Y
292010-77

Figure 20. TSMS Initialization for 82501/82502 Circuits Troubleshooting

1-229

l
12V

TI

+12V
OV

10V
ISOLATED

:~;:'i~

I
I

t

5V

t

,

II

1 M.I1,1/4W, 750V(MIN)

I
"1'1

~

~

....

aI

TXD

0'

, ~.

~ ~
o ~

....

co

m~"\

7

iFi
c

I

TXC
RXD

I

RXC

27

\,,=

26

16 TXC

~I
~

~
c

COT

;: I

RTS

10

240.11 .

·~lIf·

\

*

240.11

8

91

Vss AVss

16

t"7ol
5

Vee AVec

2 TRMT

VDD

3 TRMT

CXTD

50.11

14

78.11

15 I~

5V
25

9 RXD

23

8 RXC

RCV 4

82586
CRS

TRMT

~t;-

.O.017~

o,l~F

31
30

82501
ESI

V
\
78.11

6 CRS

\

28

RCV 5

15 TEN

CLSN

CLSN

12

11

BNC

''T'' CONNECTOR

43.11 4

RCV

82502
ETC

CXRD

~

12
100.11
FUSIBLE
1/8W

43.11

~

5 RCV

NC~

\

\

·~II~·

CL5N
HBD
43.11
6 CLSN

~
"a
I
N

..........

50.11
TERMINATOR

1143.11 7

78.11

1

Numbers are probing sequence.

lit

*

l/~~
~.22J'F

5V

0°
NOTE:

•

7 cor

r- LPBK

LPBK COMMAND
FROM I/O PORT

t~
0.22J'F

I~

,....

h

1
243.!l
0.5"

'7
292010-30

inter

Ap·274

APPENDIX A
LANHIB SCHEMATICS
PARTS LIST
PAL EQUATIONS
DIP SWITCH SETTINGS
WIRE WRAP SERVICES

1-231

PARTS
REFERENCES
Ul
U2
US.

U4

US
U6.U7
U9
U9
UI9
Ull
U12. U27

U29
ula
UI ...
UI6
Ul6
UI7
U19~

U22.

r\)

~

U2-:-

U2 ...
U25
U29
US9
ual
U.. 2
RI-RS. R6
R19.

Re. R12

R9. Ria
RII
Rla-R16
RI?

RI9
R21. R22
RPI
R2a-R26
CL C2
C3
C4. C5
C6
C?
CILCI2
cia
C9. C9
CRI
CR2. eRa
'II
'12

IC. 6"'K-Blt EPROM
IC
IC. SRAM
IC. 2S6-Blt PROM
IC
IC
IC
IC
IC. 1M-Bit EPROM (0 tional>
Resistor. 10K ohm. 11'41.L 5;(

82sall
1-489
1-488
27210
COItL

M R.
CODE
OBD
OBD
OBD
OBD
OBD
INT
INT
OBD
OBD
OBD
OBD
OBD
INT
PE
INT
PE
INT
OBD
HIT
TI
OBD
INT
OBD
OBD
INT
OBD

COItL
COML
COItL
COML
COML

OBD
OBD
OBD
OBD
OBD

COML
COML

OBD
RCD
OBD
ODD
OBD
OBD
ODD
OBD
ODD
OBD
ODD
OBD
OBD
OBD
OBD
OBD
OBD
OBD

~~:T

NO

74532

?4LS94,
74LS24S

74Fa7a
7 ...LSa?S
811186
82586

16L8
7 ...LS1I2
74LS7-4
74AS?4
?4LS165

925111
PE6 ... 192
92502
PE6 ...S69
276"'-29
7
NOTES:

I

I.

2.

1

I

I'"

§
§

12M

POWER SUPPLY COtlHECTIOItS.

6

...

I ~2~F

-12U

2
I
2
I
I
I
I
I
I

3
2
I

2~F

2. 2uF
I20U

R20

R...
RS
Ri'.

DESCRIPTION
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
Pulse Transror •• r Pack
IC
DC/DC Convert.er

U20

u26

l

LIST

I

THE BOARD REQUI~ES +SU. +12U. AND·-12U.
MULTIBUS PO~ER PINS FOR THESE VOLTAGES AND
GROUND ARE SHOUN ABOVE.

EACH Ie SHOULD HAVE A 0.1u'f' CAPACITOR BETUEEN
POIIER PIN AND GROUND PIN.
PARTS LIST DOES
NOT INCLUDE DECOUPLIHG CAPACITORS.

3.

nTR.
CODE

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292010-79

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DATA

292010-80

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DATA

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ADDRESS

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Ul
(J1

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292010-81

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AS
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21
24
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104
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102
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IDS
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102
101

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HM6264P-lS

~~t9
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Al2
All
AtB
AS
A8
A7
AG
AS
A4
Aa
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DATA

D7
D.
DS
D4
Da
D2
Dl
D.

18
17
16
15
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12
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D.
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292010-82

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ADDRESS

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292010-83

inter

AP-274·

OPTlotIAL 1ttEG (64)(..16) WOIID-NIDE EPRDI1

-

ADDRESS (A16 AU

21218
LA1691
01& 8
1&
A1686 14 014 4
A1486
19
019
Ala 94 12
012 6
A1293
011 1
11
A1192
Ie
018
Ale 91
08
9
A9 28 8
0818
A8 28 A1
0112
A? 21 A6
0613
A6 26 6
A6 26 4
.. 4 24 9
OS 16
AS 23 2
0211
A2 22
0118
I
AI 21
011 ~9
e
S9

DATA (DiS-DB)
ml&
D14
DIS
m12
mu
Die
D9
D8
D1
D6

~&:: ~:

"'fi.I

aH/C
U92

n
ROI1BUS

D8
D2
ml
De

m!~

'PI

292010-84

Module Addr_dec
Title "LANHIB Address Decode Logic
Kiyoshi Nishide
Intel Corp.

March, 1986'

"Declarations
PALl
AO. A14, A15
A16. A17. Al8
A19. BHE
HLDA. 52
RAMLO, RAMHI
ROMLO. ROMHI
ROM
RI04

device

'P16L8' ;

pin
pin

I, 2, 3;
4 •. 5. 6;
7. 8;
9, 11;

pin
pin

pin
pin
pin
pin

18. 17;
19, 12;

13 ;
16 ;

Equations
!ROMHI = A15 &: A16 &: A17 &: A18 II: A19 &: (HLDA # 52) II: RI04;
!ROMLO = !A15 &: A16 II: A17 II: A18 II:A19 II: (HLDA # 52) II: RI04;
!ROM = A17 &: A18 II: A19 II: (HLDA # 52) II: !RI04;
!RAMHI
!A14 &: !A15 II: !A16 &: !A17 II: !A18 &: !A19 II: !BHE II: (HLDA # 52);
!RAMLO = !AO &: !A14 II: !415 II: !A16 II: !A17 II: !A18 &: !A19 II: (HLDA # 52) ;
End Addr_dec
PAL Equations

1-238

inter

AP-274

3. To select the 2764-20 EPROMs or 27210 EPROM:

DIP SWITCH SETTINGS FOR
VARIOUS OPERATIONS

SW3
87654321 .

"I" indicates ON (Switch is closed).
"0" indicates OFF (Switch is open).
"X" indicates Don't Care.

2764-20 EPROMs
27210 EPROM

1. To configure the board to Ethernet or Cheapernet:

SW3
87654321

4. Dip Switch Setting Examples:

SW3
SW4
87654321 87654321

Comment

Ethernet
XXOOOOOO
Cheapernet XX111111 Transceiver Cable should
not be connected.

1) To run the TSMS Program OX111111 XXXX0010
from the 2764-20 EPROMs
in Cheapernet Configuration

2. To run the TSMS program or the Data Link Driver
program'

SW4
87654321

Comment

TSMS Program XXXXOO01 TSMS program uses
the 82530 in
or
Asynchronous Polling
Data ~ink Driver
mode. Data Link Driver
Program
program uses the
825830 in
Asynchronous Polling
and Vectored Interrupt
modes.

OXXXXXXX
1XXXXXXX

2) To run the TSMS Program OXOOOOOO XXXX0010
from the 2764-20 EPROMs
in Ethernet Configuration

S) To run the TSMS Program
or the Data Link Driver
program from the 27210
EPROM in Cheapernet
Configuration

1X111111 XXXXOO01

~)To run the TSMS Program

1XOOOOOO XXXXOO01

or the Data Link Driver
program from the 27210
EPROM in Ethernet
Configuration

5. Dip Switch SW2 programs the number of wait states
for the 82586 (see Table 3).

1-239

inter

AP-274

COMPANIES OFFERING WIRE WRAP. SERVICES
AUGAT
Interconnection Systems Division
40 Perry Avenue
P.O. Box 1037
Attleboro, MA 02703
(617) 222·2202
100935 South Wilcrest Drive
Houston, TX 77099
(713) 495·3100

Automation Delectronlcs Corporation
1650 Locust Avenue
Bohemia, NY 11716
(516) 567·7007

dataCon, Inc.
Eastern Division
60 Blanchard Road
Burlington, MA 01803
(617) ~73.5800
Mid·Western Division'
502 Morse Avenue
Schaumburg, IL 60193
(312) 529·7690
Western Division
20150 Sunburst Street
Chatsworth, CA 91311·6280
(818) 700·0600

South·Western Division
1829 Monetary Lane
Carrollton, TX 75006
(214) 245·6161
European Division
In der Klinge 5
D·7100 Heilbronn, West Germany
(01731) 217 12

DATAWRAP
37 Water Street
Wakefield, MA 01880
(617) 938·8911

Elma/EMS
A Division of Sandberg Industries
Berkshire Industrial Park
Bethel, CT 06801
(203) 797-9711
1851 Reynolds Avenue
Irvine, CA 92714
(714) 261·9473
3042 Scott Boulevard
Santa Clara, CA 95054
(408) 970·8874

WRAPEX Corporation
96 Mill Street
Woonsocket, RI 02895
(401) 769·3805

1-240

inter

AP-274

APPENDIX B
SOFTWARE LISTINGS-TSMS PROGRAM AND
LANHIB INITIALIZATION ROUTINE

1-241

AP·274

1*****************************************************************************1
1*
1*
1*

R/

r,.affic SimulatoT'/MonitoT' Station P1"ogram
for 186/586 High IntRgration Baa,.d and

iSBC 186/51

1*
1*
1*
1*
1*
1*

Vu.

December 17, 1984

1.0

IH~oshi Nishide

Intel COT'poT'ation

f/

*1

*1
*1
*1
*1
*1
*1

1*****************************************************************************1
1* This software

c~n be conditlonallv compiled to work on the iSBC 186/~1 Dr
on the LANHIB.
If ' •• tCSDCI8651), is added to the compiler call statement,
this source program will be compiled for the iSBC18651. *1

tsms:
do;

2

daclare main label publiCi
1* literals *1

$IF SBCI8651
declare lit
true

Ii terall V
lit
false
lit
forever
lit
ISCP$LOC$LO
lit
ISCP.LOC.HI
lit
SCB.BASE.LO
lit
SCBUASESHI
lit
CA.PORT
lit
BOARD.ADDRESS.BASE lit
INTSTVPE.586
lit
INTSTVPE.TIMERO
lit
INTSCTL.TIMERO
lit
INT$7
lit
PIC$MASK.130
lit
PIC.MASK.18b
lit
ENABLE.S86
lit
ENABLE.SBb.18b
lit
PIC$EOI$130
lit
EOI$CMDO.130
lit
EOI$CMD4S130
lit
PIC.EOI$IBb
lit
EOI$CMDO.IBb
lit
PIC$VTR$18b
lit

'literally
'1',

I,

'0',
',-,h i 1 It 1',

'OFFFOH',
'0',
'0',
'0',
'OeBH',

'OFOH',
'20H',
'30H',

'OFF32H',
'27H',
'OE2H',

'OFF28H',
'OFEH',
'OEEH',
'OEOH',

'60H',
'64H',

'OFF22H',
'0',

'OFF20H',
292010-31

Traffic Simulator/Monitor Station Program

1-242

AP-274

TIMERO.CTL
TIMERO.COUNT
MAX.COUNTtA
CA
ESItPORT
NO.LOOPBACK
LOOPBACK

lit
lit
lit
lit
lit
lit
lit

'OFF56H',
'OFF50H',

'OFF52H',
'0',

'oeBH',
'B',
'O'i

.ELSE
:3

d .. cla .... lit

literall~

true
false

foreve"

ISCP.LOC.LO
ISCP.LOC.HI
SCBtBASE.LO
SCB.BASE$HI
CA.PORT
BOARD.ADDRESS.BASE
INTtTVPE$5B6
INTtTVPE$TIMERO
INTtCTL.TIMERO
PIC.MASK.IB6
ENABLE$5B6
ENABLE.5B6.IB6
PIC.EOI.IB6
EOItCMDO$IB6
EOItCMD4.IB6
TIMERO.CTL
TIMERO.COUNT
MAXtCOUNT.A
CA
ESItPORT
NO.LOOPBACK
LOOPBACK

'literally',

lit ' 1',
lit '0',
lit 'whi Ie 1',

IH

lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit
lit

'03FFBH',

'0'.
'0',
'0',
'BaCOH',
'SISOH',
'12',

'B',
'OFF:32H',
'OFF28H',

'OEFH' ,
'OEEH',
'OFF22H',
'12',

'B',
'OFF56H',

'OFF50H',
'OFF52H',
'0',
'BIOOH',

'I' ,
'O'i

.ENDIF
.IF NOT SBCIB651
1*
4

S~.t.m

Configuration Pointer *1

declare scp structure
(
s~.bus

b~te,

unused (5) but.,

iscp'addr$lo word,
iscp'addr$hi word
)

at (OFFFF6H) data (0, 0, 0, 0, 0, 0,

ISCP$LOC.LO, ISep$LOe'HI) i

$ENDIF
1* Intermediate System Configuration Painter *1

292010-32

Traffic Simulator/Monitor Station Program (Continued)

1-243

inter
5

Ap·274

declare iscpSptr pointer.
isep based iscp.ptr structure
(

busV bvte.
unused bVte,
scb$o \aiD I' d ,

,*

set to 1 bU CPU before its first CA to 5Bb.

cleared bV 586 after reading lnfo from It *1
1* unused *1
1* offset of sgstam'control block *1

scb$b (2) ,"ord 1* base of svstem control block *1
),

1* System Control Block *1
declare 5tb structure
(

status word.

1* cause(s) of intel"',rupt,

1*
'cblSoffset word. 1*
rp ..$offset ,"ord. 1*
ereSerrs word,
1*
1*
alnSerrs lIIord,
1"scSerrs word,
1*
cmd lIIord.

Dvrn'erT& lUord

int acks.
of' set of
of' set of
ere error

CU state,

RU state *1

CU cmd. RESET bit. RU cmd *1
'irst command block in CBL *1
first packet descriptor in RPA *1

e"counterd so far *1
alignment 'errors *1
no resources *1
1* overrun errors *1

),

1* B25Bb Action Commands *1
1* NOP *1
7

declare nap structure
(

cmd word,

link.offset ,"ord
),

1* Individual Address Setup *1
B

declare iaSsetup structure
(

statuI lIIord,
cmd word,

link.offset ,"ord.
iaSaddress (6) byte
),

,*
<;I

Con'igure *1

declare configure structure
(

,

statuI \IID'rd,
cmd lIIord,

link.offset ,"ord.
bvt.Scnt byte.
info (11) bVt.
),

292010-33

Traffic Simulator/Monitor Station Program (Continued)

1-244

inter

AP-274

1* Multicast
10

d.cla~.

Add~es.

Setup *1

me.setup structure
(

status

lUDT"d,

cmd ward,

link.offset word,
me.byt •• count word,
mcSadd~ess

(48) byte

1* only 8 Me

add~e.s ••

a~e

allowed *1

),

1* Transmit *1
1* This transmit command is made of one transmit buffeT descriptor and one
buffe~.

1518 bytes long
11

*1

declare transmit structure
(

status word,
cmd lIIord,

link'offset word,
bdSoffset
destSad~

type

wo~d.

(6) byte.

wo~d

),

1* Transmit BuFfer Descriptor *1

12

declare tbd structure
(

act.count \IIord,
link.offset word,
adO lIIord,

adl

wo~d

),

1* TT"ansmit Buffer *1

13

d.cla~e

14

decla~e

tlSbuffe~

tdr

(1518) byte,

.t~ucture

(

status

laJOT'd,

cmd word,
linkSoffset word.

result la.IDT"d
),

1* Diagnose *1
15

declare diagnose structure
(

292010-34

Traffic Simulator/Monitor St~tion Program (Continued)

1-245

inter

AP-274

status lIIord,
cmd ward,

linkSoffset word
),

1* Dump Status *1
16

declare dump structure
(

status lIIord,

cmd word,
link.offset word,

b u ffSp tr

1001'

d

),

1* Dump Are. *1
17

dec!.,.. dumpSarea (170) buts,
1* Frame Descriptor *1

1* Receive frame area is made of 5 RFDs. 5 RBDs. and 5 1514 butes long
buffers. *1
18

declare rfd (5) structure
(

status w01"d,

elSs word.
linkSoffset word.
bdSoUnt word.
destS.dr (3) word.
src$adr (3) word,

tupe word
),

1* Receive Buffor Descriptor *1
19

declare rbd (5) structure
(

act.caunt lIIo1'd,

n •• tSbdSlink word.
adO word,
ad1 lIIord,

size wo,.d
),

1* Receive Buff.r *1

20

declare rbuf (5) structure
(buff.r (1514) bUte),

21

declare status ward,

I*'global variable. *1
1* UART status *1

292010-35

Traffic Simulator/Monitor Station Program (Continued)

1-246

AP-274

ae tua 1 word,
c$buf (80) b~te.
dh,,. b~te.
ch bvte at (@c$buf).
char.count b'lte,
receive'caunt dCliord,

1* actual number of chars UART transferred *1
1* buffer fOT a line of chaT'S *1

1* number base switch *1

count dCliord,
pt"eamble word,
add~es.$length

b~te.

ad.loc bvte.
CT'C

but.,

goback b~te.
reset bvt.,
delav word,
curScb'of'set word,

current.frame bvte,

1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*

counte,. for received frames *1
counter for transmitted frames *1
preamble length in word *1
add~ess length in byte *1
add~ess location cont~ol of B2~8b *1
c~c length *1
if set, go back to Continuous Mode *1
reset flag *1
dela" conunt for tranmission dela~ *1
offset of current command block *1
offset of frame descriptor Just used *1

1*

t~ansmit

no.transmission bVte,

stop.count dWDT'd,

te~minal

f~ame

count *1

stop b~te.
mc'count bvte,
z b~te.
9 b~tei

1* external procedures *1

O!O!
23

1
2

~ead:

Ca,
(b,

24

2

end

25
2b

1
2

w~ite:

Ca, b, c, d,
c) wD~d,
d, e) PQinte~.i

p~ocedu~e

decla~e

e)

exte~n.l.i

~ead;

decla~e

p~ocedure (a,

b,

(iii,

c)

(b,

d) pointer;

c, d) exte~nai;

wo~d,

27

2

end

28
29

1

2

csts: p~ocedu~e blJte
end c StS1

w~ite;

1* utilitv

exte~nal;

p~ocedures

*1

offset: procedure (ptr) word.i

30

1* This

p~ocedu~e

absolute
and then
31

2

32

2

point.~ va~iable (selector:offset), caluculates an
subt~acts the 82586 SCB o'fset from the absolute address,
the result as an offset value for the 82586. *1

takes a

.dd~e5s,

~etu~ns

declare (ptr, ptr$loc) pointer,
base586 dword,
w based ptrSloc (2) word;
pt~$loc

=

@pt~,

1* 8258b SeB Base

Add~ess

(20-bit wlde in this l8b based

syst~m)

*1
292010-36

Traffic Simulator/Monitor Station Program (Continued)

1-247

inter
33
34

2
2

35

2

AP-274

base59b s (shl!doubh (iscp. scbSb(Il>. Ib) and OOOFOOOOH) + iscp. scbSb(O),
return 101d«shl!double (..,(1)). 4) + lOW)) - base58b),
end offseti

writeln:

3b

procedure (a.

b,

c', d)i

1* This procedure writes a line and put a CR/LF at the end. *1
37

2

dec lare (a,
(b,

39
39

2
2

40

2

1IIOT,d,'

d) painter;

·call ",rite(., b,

c,

d');

call .. rite(O. @(ODH. OAH). 2. @statusl,
end write!n;

cr$lf:

41

c)

procedure;

1* This procedure .. rites a CR/LF. *1
42

2

43

2

call Idrite (0. @(ODH. OAHI. 2. @statusl,
end crSlf,
pause: procedure;

44

1* This procedure breaks a program fl.old. and ... its for a char to be tuped. *1
45
47

2
2
2

49

2

4b

call write(O. @(ODH. OAH. 'Hit (CR> to countinue·l. 23. @statusl,
cali read(l. @cSbuf. 90. @actual. istatusl,
call crSIf,

skip: procedure but.,

49

1* This procedure skips all leading blank characters and returns the first
non-blank character. *1
'0

'1

2
2
2

dec loire i bUte,
i

- 0;

do Idhile (c'buf '),

20. @status);

end read$b i ti

yes:

74

*1

word;

procedure byte;

1* This procedure reads a character and determines if it is a y(~) or NCn),

75

2

76

2
3
3
3
3

77

7B
BO
'B1
B2

3

B3

3

B4

2

dec laTe b b'Jte;

do forever;
b = read.chaT;
if (b
'V') or (b
'1:1'> the~ return true;
else
if (b = 'N') or (b
'n') then return false;
else
call writeCO, @(ODH, OAH, ' Enter a Y 01' N ==)
end;

=

=

=

~),

22. @status);

end yes;
cha1'$to$int: procedu1'e

B5

(c)

blJtei

1* This procedure converts a blJte of ASCII integer to an intege1'

B6

2

B7
B9
90
91

2
2
2
2

.,

*1

declare c b1jtei
if ('0'

<= c) and (c <= '9') then 1'etu1'n (c -

30H)i

else

if('A' <= c) and (c

(=

'F') then 1'etu1'n (c - 37H)i
292010-38

Traffic Simulator/Monitor Station Program' (Continued)

1-249

intJ
92
93

2
2

94

2

AP·274

if ('a' <= c) and (c
else return OFFHi

57H);

end char$to.inti
i.ntstoSasci:

95

'f') then return (c -

(=

procedure (value,

base.

Id.

1* This p,.oce.du,.. conv.,.t. an int.,.g..,.

<

bufadl"'. width),

OFFFFFFFFH to an .,';,..,u of ASCII

codes.

Input variables are:

96

97
98
99
101
102
103
104
lOS
lOb
107
108
109
110

2

2

declare value dword.
bufadr pOinter,
(i, J' base, Id, width) bljte,
ch.,,.s based buf.,d,. (1) bute.
do i

3

3
3
3

3
2
2
3

3
3
2
2

valure = integer to be converted,
base = number base to be used for conversion,
Id = leading ch.r.cter to be filled in,
buledr = buffer address of the arra~,
.. idth = .i Ie of a,.,.au. *1

=

1 to .. idth.
J - value mod base;
if J < 10 then cha,.. ( .. idth - i) = J + 30H.
else cha,.s ( .. idth - i) = J + 37H.
value
v.alue j base;
Ig

endJ

i = 0.

do while ch.rs (1) chars (i) - IdJ
i = i + 1;
end;

char.count

m

'O"and

< .. idth

- 1.

width - ii

end jnt.to.asci,
out.word: p'rocedura (w.ptl'.' distance),

111

1* An intege,. at (selecto,. of ... pt,.): (offset of ... pt,. + distance) is p,.;nted
•• ., 4 digit hex.,decimal numb.,..
*1

112

2

decla,.e chars(4) byte.
IIISptr point .... ,

dhtance byte •
.. besed ... pt,. (1) wo,.d.

113
114

2
2

115

2

11b

call intSto.asciC .. (distance). lb. '0'.' I!cha,.s(O).
call ..,.ib(O. I!cha,.s(OI. 4. i!statusll

4);

end outtlalOrdi

..,.ita.int:

p,.ocedu,..(d ...

t).

1* An ;ntege,.· (d .. ) i. p,.inted in hexadecimal (t

= 1)

0,. in decimal (t

a

01. *1

292010-39

Traffic Simulator/Monitor Station Program (Continued)

1-250

intJ
117

2

AP-274

dw

d.cla~e

dwo~d,

chars e 10) byte.
t byte,
118
119
120
121
122
123

2
2
3
3
3
2

124
12:1
126

3
3
3

127

2

if

t then

do;

call intStoSasciCdw. 16, 0, @cherseO), 8»)
call writeCO, C!chat's(S-cha",ScDunt), ch~r'cQunt, @status);
end;

else
do;

12e

call intStoSasciCdw, 10. 0, @charsCO), 10);
call writ.CO, echars(10-charScDunt), char'count,

@.tatus);

end ",,.it •• int;

out'dec'hex:

pracedureCdw);

1* This procedure prints an integer in decimal and hexadecimal.

129

2

130
131
132
133

2
2
2
2

134

2

call writ.tinted"" O)i
call ..riteeo. @e' e'). 2. I!status),
call ..rite.inted ... I),
calfwrite(O. @(/H)'), 2, 8status);
end out_dec.heli

..rite.offset:

135

proceduree"'ptr),

1* This procedure takes a pointer variable.

and prints it in hexadecimal.
136

2

137
138
139
140

2
:2
2
2

141

2

*1

declare dUl dwordJ

converts it to a 82586 type offset.

*1

declare UI'ptr pointer.
til lIIo'rdj

call ",.rit.,CO, @(' at '), 4, @status);
.. = offsete"'ptr),

call DutS",ord(@w, 0);
call ~rite(O, @(/
' ) , 2, @status);
end IIIrite$offset;
IIIrite$addr~ss:

142

procedure Cptr);

1* This procedure takes a pointer variable and prints i t in thr
'selector:offset' format.
*1

143

2

144

2

declare (ptr, ptr$loc) pointer,
III based ptr.loc (2) word;
ptr'loc = I!ptr,

292010-40

Traffic Simulator/Monitor Statlon.Program (Continued)

1-251

inter
145
146
147
148

2
2
2
2

149

2

Ap·274

call
call
call
call

out$word

(@w(I). 0),
Ie': '), 1. @status);
out$word(@w(O). 0),
writeCO, @(' ' ) , 1. @status)i

",riteCO.

end write'address;
print$wds:

150

proc~dure(w'ptr,

no'words);

1* This procedure pr.ints no'words number of words starting at wSptr.

151

2

152
153
154
155
156
157
158
159
160
161

.2
2
3
3
4
4

162

2

declare "'$ptr pointer.
(i, nO'IIIDT'ds) bVtei
if no$words

<>

0 then

do;

call cr$]f,
do i = 0 to no.words - 1;
call outSwordCwSptr, i ) ;
if i = 0 then
call write'Dffse~(w'ptr);
call cr$lf;

4

4
4
3

*1

end;
end;

end pT"intSlllds;

163
1* This procedure prints len number of

164

2

165
166
167
168
169
170
171

2
2
3
3
3
3
2

172

2

173

decla,..e (len, i) bljte,
chars (2) b~te.
st,.Sptr pOinter,
str based str$ptr (1)

b~t.s

starting at strSptr.

*1

b~te,

if len <> 0 then
do i
0 to (len - 1),
call intSto$asciCstrCi), 16, '0', @chars(O),
call writ,,(O. @chars(O). 2. @status),
call ",,.iteCO, @e'
'), 2. @status);

=

2);

end;
call cr$lf,

print$buff:

procedure (ptr.

cnt),

1* This procedure prints cnt number of buffer contents starting at ptr.

174

2

*1

declare ptr painter,
bt based ptr (1) buteo
(i. J) b~te.

cnt aa.ardi
292010-41

Traffic Simulator/Monitor Station Program (Continued)

1-252

inter
175
176
177
178
179
180
181
182
183
184
185
187
188
189

2
2
3
3
4
4
4'
4
4
3
:3
3
:3
2

190
191
192

:3
3
:3

193

2

AP-274

i

-

16 then

sh1"(cnt,

do J -

4) -

Ii

0 to is

call ~rit ••• ddr ••• (ebt(16*J»'
call print.str(lbt(16*J)' 16),
if (J = 20) or (J
40) or (J = 60) or (J
call pause;

=

= 80)

then

end;
i
i + 1;
If cnt-16*i <> 0 then call ~rlte.addre •• (lbt(16*i»,
call print •• tr(ebtlI6*il, cnt-16*i),

=

call ~rlte.addr ••• (lbt(O)I'
call print •• tr(lbt(O), cnt),
end;

end prlnt.buff.

,..ad.jnt:

194

>

if cnt
do;

p'rocedul"e (limit) dl&Jordi

1* This procedure reads integer characters and forms an integer.

integer is bigger than 'limit' Dr an
an .1"1"01" message is p,.inted.
*1
195

2

196
197
198
199
200
201
202
203
205
206
208
210
211
214
215
216
217
218

2
3
3
:3
3
3
3
4
4
4
4
4
4
4
4
4
4
3

219
220

3
3

221
223

4
4

declare (l&Jd. ""h, limit) d\llord.
(i. J • • , dane. he., dover,

Dv.rflo~

If thp
erroT' is encounterred. then

have,.) b"te;

do forever;
call read(l, leSbuf, eo. tactual. @st.tus),
i. II = skip;
hex. done, dove,., hover = falseJ
~d, ~h = 0,
J
char.to.int(c.buf(i)l,
do ~hile J <= 15,
if J > 9 then he. = t,.uei
if not dover then
If ~d > 429496729 then dover
true,
else if (~d
429496729) and (J > 5) then dover
true,
~d = ~d*10 + J'
if not hover then if ~h > OFFFFFFFH then hover = true,
wh = ",h*16 + Ji
i - i + 1;
J = char.to.lnt(c.buf(i»,
end;
If «c.buf(i) <> 'H') and (cSbuf(i) <> 'h') and (c.buf(l) <> ODli) and
(c.buf(i) <> OAH) and (cSbuf(i) <> ' .» or (i = k) then
call ~ri teln(O, I(ODH, OAH, ' II ltPgal character'), 20, .status),
else
do;
i f (c.buf(l) = 'W) or (c.buj>(1l = 'h') then hllx = true;
if he. then

=

=

=

=

292010-42

Traffic Simulator/Monitor Station Program (Continued)

1-253

intJ

AP-274

224
225
227
228
229
230

4
5
5
4
4
4

do.

231

4

call writeCO,

232
233
234
235
236

4
4
4
3
3

call DutSdecShex(limit);

237

2

hove~

if not

<=

and (wh

limit) then return

wh~

end;

else

if not dover and (wd <= limit) ~hen return wd;
call writeinCO, @(ODH, OAH, , The number is too big. '), 25,
(!StktU5) i

It has to be less than ar eq,ual to '),

(!('

3i"
(!StLctU5) ;

call lIJritelnCO.

2

@:status);
==)

'),

20, (!statu-a.);

end read' inti
proc ed ure (wh ere);

1* This procedure puts an address
location 'where'. *1

239

1,

@C' Enter a number

end;

put'address:

238

@('. ' ) ,

end;

call blriteCO,

declare where painter,
(i. J. m, 'err)

t~ped

in hexadecimal to the specified

b~te,

addr based where (I) byte.
240
241
242
243
244
245
246
247
249

2
3
3
3
3
3
4
4
4

250
251
252
254
255
256
257
258
259
260
261
262
263
264
265
266
267

5
5
5
5
5
4
4
4
3
3
4
4
4
4
3
3
3

268

2

do

f01"eVeTi

=

err
false;
call read(!, @cSbuf,
i

eo,' @actual, @status);

= skipi

m = addressSlengthl

do while (m (> 0) and not err.
J = char.to.int(c.buf(i)),
if J
OFFH then err = true.
else
do;
.ddr(m-I)
shlCJ. 4).
J = char.to'int(c'buf(i+l)),
if J D OFFH then err
true,
else addr(m-I) = addr(m-l) or J'

=

=

=

end;

i =
+ 21
m = m - 1;

end;
i f not err then
do;

m = c'buf(i),
if (m
ODH) or (m
,then return;

=

= OAH)

or (m = 'h') or (m

'H") or (m

,

.)

end;

'call ..riteln(O. (I (ODH. OAH. ' Illegal character' h 20. @status),
call "'1'ite(O, @(' Enter an address in Hex
29, .status);

==> ').

end;

end put.address;

292010-43

Traffic Simulator/Monitor Station Program (Continued)

1-254

intJ
269

AP-274

percent:

procedure;

1* This procedure calculates and prints a network percent load generated
blJ this sta'tion.
The eq,uatian used in this procedure was obtained
from actual measurements. *1

270

2

271

2
2

272
274
275

2

2

declare i word,
(J. k) d.. ord.
pcent (3) b~te,

J = (tbd.act.count and 3FFFH)*B,
if not ad.loc then k
(2*addres •• length + 2 + cre + preamble)*B,
else k = (ere + preamble>*Si
if dela~ <> 0 then

=

.IF NOT SBCIB651
276

lo .. «1000*(J + k»/(lB05 + k + 5*double(delay) + J»'
.ELSE
i

= lo .. «1000*(J + k»/(2021 + k + 5*double(delay) + J)l,

.ENDIF
277

2

else

.IF NOT SBCIB651
lo .. «1000*(J + k»/(lBI0 + k + J»'
.ELSE

= Io .. «1000*(J + k»/(2026 + k + J»l
.ENDIF
27B
279
2BO
2Bl
2B2

2
2
2
2
2

2B3

2

2B4

call jnt.toSasci(i,

10, 0, @pcentCO), 3);
call "'Tite(O, @pcentCO), 2, estatus);
call w... iteCO, @:('. '), 1. @status)j
call write(O. @pcent(2). 1. @status)'
call wT'itelnCO, (!( I X'), 2, (lstatus);

end percent;

print.net .. ork.addr:

procedure (ptr),

1* This station's address is printed with its least signlficant bit
in the most right position.
*1

2B5

2

declare ptr pOinter,
addr based ptr (1)
char (6) b~te.
i

b~te.

b~te,

292010-44

Traffic Simulator/Monitor Station Program (Continued)

1-255

inter
28b
287
288
289

2
3
3
2

290

2

291

AP-274

= 1 to address.length;
chaT(i-l) = addrCaddress$Ienqth-i);

do i
end;

call prinUstr CC!char CO). addressSlength),
end

print'net~ork'addr;

print'parameters:

procedure;

1* This procedure prints transmission parameters. *1
292

2

dec lare

1&1

dword,

stgs Cb)
293
294
295
29b
297
298
299
300
301
302
303
304
305

2
2

b~te,

call writeCO.

C!e' Destination Address:

'), 22, (!status),

2

if not adSloc then
call printSnetworkSaddrC@transmit.destSadrCO»,

2

else

2

2
2

2
2
2

2
2
2

call printSnetworkSaddrC@txSbufferCO»,
if nat ad'loc then

w = Ctbd.actScount and 3FFFH) + addressSlength
else w Q Ctbd.actScount and 3FFFH) + cre,

*

2 + 2 + erc,

call writ.CO. @(' Frame Length: '), 15, .status);
call write.lnth." 0);
call writelnCO. @C' b~te5·>. b. C!status),
call 1I.IriteCO, @(' Time InteT'val between Transmit Frames:
if delay <> 0 then
do;

'),

40, @status);

SIF NOT SBCIBb51
30b

- 1)

*

5,

+ CdoubleCdelay> - 1)

*

5,

w = IBIO +

3

CdoubleCdela~)

SEI.SE
w

= 202b

SENDIF
307
308
309
310
311
312
313
314
315

3
3
3
4
4
4
4
4
3

316
317
31B
319
320
321
322

4
4
4
4
4
3
2

call 1nt.to'asciCw.

if w
do,

>=

10, 0,

@stgs. 6);

10000 then

call lII",iteCO, (lstg.COh 2, @status);
call w1'iteCO, IC'. '), 1, .status);

call writeCO. @stgs(2), 2, @status),
call writelnCO, C!C' miliseconds'),

12, @status)J

endJ
else

do,
call writeCO. @stgsIO), 5. @status),
call writeCO. @C'. 'I. 1. @status),
call writeCO. @stgs(5), 1. C!status),
call IaJriteln(O,

(!('

micl'oseconds'),

13, @status);

end;
end;
.lse

292010-45

Traffic Simulator/Monitor Station Program (Continued)

1-256

inter

AP-274

$IF NOT SBC1B651
call writeln(O.

(!('

159.4 miCl'DSeConds'),

19.

C!status);

@('

172. B micTDseconds'),

19.

@status)i

$ELSE
call writeln(O.

$ENDIF
323

2

call writeCO.

324
325
326
32B
3:Z9

2
2
2
2
2

call percent.;

330

2

end print.parameters;

@('

Netlllork Percent Load generated blJ this station:

'),

49.

@:statu5);

call ul'rite(O, @(' Transmit Frame Terminal Count: '), 32. @status)i
if stop then cal} w1'iteSint(stapScount, dhex);
else call IdriteCO. @('Not Defined'), 11, C!status)j
call crSl.,;

printf,scb:

331

procaduTei

1* print. the SeB *1

332
333

2
2

334

2

335

call "'TitelnCO. (!(ODH. OAH, '*** System Control Block ***'), 30, @status);
call printS.... ds«!scb. status, 8);
end pTintSscbJ

waitSscb:

proceduT"e;

1* This pTocedure provids a wait loop for the
become cleared.
*1

336

2

337
33B
. 339
340
341
342
343
344
345
346

2
2
3
3
2
2
3
3
3
3

347

2

34B

sen command word to

dec lare i word;
i = 0;
do while (scb. cmd
i

=i

<:>

0) and (i

<

BOOOH);

+ 1;

end;
if scb. cmd <:> 0 then
do;
call ,."ite(O, @(ODH, OAH,
e.l1 blJ'ite$intCi, 0);
call cr$lf;
end;

' Wait Time

').

15,

@status);

end waitSseb;
startStimerO:

procedure.

1* B01B6 timerO is sta"ted.

*1

292010-46

Traffic Simulator/Monitor Station Program (Continued)

1-257

inter
349

2

350

2

AP.-274

output (TIMEROSCTL)

OEOOOH,

isr: procedure interrupt INTSTYPES586 reentrant.

351

1* interrupt .ervice routine for 82586 interrupt *1

352

2

declare

i

byte.

1* Enable 82586 Interrupt *1

SIF SBC18651
output (PICSEDISI30)

D

EDISCMDOSI30 •

• nab lei

SEL.SE
353
354

2

2

output· (PICSEOlSI86) .. EOISCMDOSIB6.
enolble.
SENDIF
1* Frame Received Interrupt has the highest priority *1

355
356'
357
358
359
360
361
362
363
364
365
367
368
369

2
2
3
3
3
3
3
3
4
4
4
4
3
3

370
371
372
373
374
375
376
377
378
379
380
382

2
2
3
3
3
3
3
3
3
4
4
4

i ' (scb. status and 4000H)

4000H then

do;

disabh.
sob. cmd .. 4000H.
output (CASPORT) = CA.
c.l1 .. aitSscb.
i' rfd(currentS'r.me), status D OAOOOH then
do.
receiv •• count = receive.count + 1;
current.frame = current.frame + 1;
if CUTTent.fr.me • 5 then current.frame

0;

endJ

return;
endJ

i' (scb. status and 2000H)

2000H then

do.
disable.
scb. cmd .. 2000H.
output(CASPORT) - CA.
call ..aitSscb.
enable.
if (transmit. status and OAOOOH) = OAOOOH then
do;

caunt = count + 1;
if (stop and (count = stopScount»

then return.

e1.e'

do.

292010-47

Tra.ffic Simul~tor/Monltor Station Program (Continued)

1-258

inter
3B3
3B4
3B5
3B6
3B7
3BB
3B9
390
391
392

Ap·274

transmit. status = 0;
if dela~ = 0 then

:I

5
5
6
6
6
6
6
6
5

do;

disable;
scb. cmd = 0100H.
output(CASPORT)
call waitSscbi
retuTni

CA.

end;

else
do;

393
394
395
396
397
39B
399
400
401
402
403
404
405
406
407
40B
409
410
411
412
'413
414
415
416
417
41B
419
420
421
422
423
424
425
426
427
42B
429
430
431
432
433
434
435
436
437
43B

6
6
6
5
4
3
3
4
4
4
4
4
4
4
3
3
4
4
4
4
4
4
4
4
3
3
4
4
4
4
4
4
4
4
3
3
4
4
4
4
4
4
4
4
3
2

call startStim.rO.
end;

end;
end;
if (transmit. status and 0020H)
0020H then
do;
transmit. status = 0;
disable,
scb.cmd
0100H.
output (CASPORT) = CA,
call waitSscbi
return;
end.
if (transmit. status and 0400H)
0400H then
do;
call ,.rrite(O, @(ODH, ' No Carrier Sense! I,

=

=

=

transmit. status

=

disable;
scb. cmd
0100H.
output (CASPORT)
call ",aitSscb.
return;

=

ODH)' 20, @statu!;.);

OJ

= CA.

end;
if (transmit. status and 0200H) = 0200H then
do;

call "'rite(O. @(ODH.
transmit. status = OJ
disable;

'Lost Cle .. r to Send! '. ODH). 22. @status).

=

scb. cmd
0100H.
output (CASPORT) = CA.
call waitSscbi
return;
end;

if (transmit. status and 0100H) = 0100H then

do.
call writeCO,

@(ODH,

transmit. status

= 0;

disable;
scb. cmd = 0100H.
output (CASPORT)
call wai'tSscbi

'DMA Underl"un! I,

ODH),

16, @status)j

= CA.

t"etu'rn;

end;
end;

if (scb. status and BOOOH)

BOOOH then
292010-48

Traffic Simulator/Monitor Station Program (Continued)

1-259

AP·274

439
440
441
442
443
444
445
446
447
44e
449
450
,451

2

do,

3
3
2

end;
i f Cscb.status

2

do;

disable,
scb. cmd = BOOOH,
Dutput CCA.PORT)
call .... U.scb'

3
3
3

= CA,

and 1000H) .. 1000H than

disable,
scb. cmd a 1000H,
output CCA.PORT) - CA,
call ..ait.ub,
call ..rUaCO. ICODH• • Receive Unit became not read,. '. ODH). 33.

3

3
3

3
3

·.&tatu~)'

and,

452

3

453
454
455
456
457
45e
459
460
461
462
463
464
465
466

2
3
3
4
'4
4
4
4
4
4
4

3

end,

467

2

end isr,

2

3

46e

i f rasat than

do,

.if
do,

isc~bus,

and,

then

call .. rit.lnCO. ICODH. OAH. 'Re •• t faUed. '). 16. 'status),
disable, .
scb. cmd - 008OH,
output CCA.PORT) • CA,
call .... i t •• cb'
output CCA.PORT) - CA,
c .. 11 writ.1nCO. IC' Soft... r. Re.et E •• cuted!'). 25. Istatus),

el •• r ••• t .".1 •• ,

tx.i.r: procedure interrupt INT.TYPE.TIMERO,
1* interrupt survic. routine for 80186 timer interrupt_I

469
470
471

:I

2
:I

scb. cmd - OIOOH,
outputCCA.PORT) - CA,
caU ..Bi t'scb,
.IF SBCle651
outputCPIC.EOI.130) - EOIfCMD4.130.
en .. ble,
outputCPIC.EOI.l86) = EOI.CMDO.le6,
, .ELSE

472

:I

473

2

outputCPIC.EOI.le6)

a

EOI.CMD4.1e6,

fEND IF
end tx.isY"
292010-49

Traffic Simulator/Monitor Station Program (Continued)

1·260

inter

AP-274

SIF SBCI8b51
i5r$7:

procedure interrupt INT$7i

1* The 80130 generates an interrupt 7 if the original lnterrupt 15 not

active

an~

more when the first interrupt acknowledge is received. *1

call writeCQ,

@(ODH,""lnterrupt 7',

OOH),

13, @status);

end i sr$7i

SENDIF
474
475

1

2

47B
479

2
2
2
2

4BO

:1

47b

477

read.byte: procedure (k) blJtei
dec lare k word;
call writeCO,

OAH,

call writeCO, @(' ==)
return readSint(OFFH);

' Enter blJte '),

14, @status);

'),

5, @status);

end read$byte;

1nit.lab$timerO:

4BI

(!(ODH,

call QutSdecShe,(k),

procedure;

1* This procedure initializes the 80186 timer O.

482

2

dec lare i

*1

byte;

SIF SBCIBb51
Qutput(INT$CTLSTIMERO) = B,
call writeCO,

@(ODH,

OAH,

delay = readSfnt(OFFFFH),
if (delay < 100) and (delay

Enter a delay count ==> '), 27, @status)i

<> 0) then

do;
call cr$If;
call crSl fj

call loopSchar(35,

call Ulrite(O,

@('

'*');

WARNING '), 9, @.tatu.),

call 100p$char(35, '*')i
call writeln(O, @(ODH, OAH, 'A delalj count between 0 and 100 malj be verlj "
~dangerous when this station starts'), 80, @status);
call writeln(O, @('to receive many frames separated onl\1 by the
'IFS period (9. b microseconds). '), 75, @status);
call writeln(O. (!( 'If this station never receives a frame. then "
'ignoTe this warning. '), 65, @status);
call loop$char(79, '*');
\
end;

Qutput(MAXSCDUNTSA)
call c1'$lf;

Qutput(PICSMASKS1Bb)

= delay,
= 3EH,
292010-50

Traffic Simulator/Monitor Station Program (Continued)

1-261

inter

AP-274

$EISE
483
484
485
48b
487
488

2
2
2
2
2
2

output(INT$CTL$TIMERO) = OCH;
call WT'lte(O, @(ODH, OAH, ' Enter a delalj count
delay = read$.nt(OFFFFH);
output (MAX$COUNT$A) = delay;

==> '),

27, @statub);

call cr.lf;

out put(PIC$MASK$18b), = ENABLE$58b$18b;
$ENDIF

489

2

end initS1B6$timerOi

490
491

1
,2·

setup.ia'parameters:
declare i byte;

492

2

call w,..iteCO, @(ODH, OAH,

493
494
495
49b
497

2
2
3
3
2

if yes then
do i = 0 to address$length - 1;
ia$setup. ia$address(!)
!nput(BOARO$ADDRESS$BASE + 10 - 2

498

3

499
500

3
3

501

2

end setup.is'parameters;

502
503

1
2

setup.me.parameters: procedure;
declaT"~ (J,
k, done) btjtei

504
505

2
2

J = 0;
call writelnCO, (!(ODH, OAH,

50b
507

2
2

508
509
510
511
512
513
514
515
51b

2
3
3
4
4
4
4
4
5

done = false;
call writeCO, @(' Would lJou like to enter a Multicast Address?',
, fY or N) ==> '), 59, @status);
do ~hile not done;
if yes then

517
518
519

5
5
4

520

5

procedure;
Configure the 58b ~ith the pre~ired'
, board address ==> '), 57, @5tatu~)j

*

i);

end;

else
do.
call writeCO,

@(OOH, OAH, ' Enter this station"s address',
I
in Hex =~> '),43, @statu~)J
call put$address(@ia$setup. ia$address(O»;
end;

do;

I

You can enter up to 8 Multicast Addresses. '),
45, @status).

k = J * address$length;
J = J + 1;
call cr$lf.
i f J = 9 then
do;
call write(O. @(' You

done

=

call

~rite(O,

alread~

entered B Multicast addresses.
43, @!.tatus);

I),

true;

end;
else
do.
@(' Enter a Multicast Address

==> '),

31, @status);
292010-51

Traffic Simulator/Monitor Station Program (Continued)

1-262

inter

AP-274

call putSaddressC@mcSsetup.mcSaddressCk»;

521
522

5
5

523
524
525
526
527
529
530
531
532
533

5
4
3
3
2
2
2
2
2
2

534

2

end setup.me.parameters;

535
536

1
2

setup'configure'parameters: procedure;

537
538
539
540
541
542
543
544
545
546
547
548
549

2
2
2
2
2
2
2
2
2
2
2
2
2

cQnfigur •. b~t.'cnt = l1i
configure. in'o(O)
8;
con.igure. infoCl)
0;
configure. info(2)
26H;
configure. info(3)
Oi
configure. in'o(4) = 96;
configure. info(5)
0;
configure. in'o(6) = OF2Hi
configure. in'o(7)
OJ
configure. info(8)
0;
configure. in'o(9) = 64;
J = 0;
call \IITiteCO, @(ODH, OAH.
, values.', ODH, OAH,

550
551
552

2
3
4

do urhile 'Ies;
do .. hile J = 0;
. call writ.CO. @CODH. OAH • • Enter byte number C1 - 11)

553
554
555
556
557
559
560
561

4
4
4
4
3
3
3
3

562
563
564
565
567
568
571

3
2
2
2
2
2
2

573

2

call writ.CO,

(!(ODH,

OAH,

'More Multicast Addresses?',
,

(V Dr N) ==)

'),

42,

@status);

endi

end;

t,.uei

else don.
end;

if J = 9 then
= J - Ii
me'caunt = address'length * Ji
mc$setup.mcSbvt.Scaunt = me'count;
call '-I",iteCO,

@(ODH.

DAH,

You entered

I

'),

15.

@status);

call ..riteSintC J. 0);
call lIIT"ltelnCO.

declare Ck.

J)

C!(

I

Multicast Addressees>' '),

23.

@status);

byte;

=

Configure command is set up for default',
' Do you urant to change an" bytes?',
, (Y or N) ==:> '), 99, @status);

I

==>

'I. 34.

@status)i

J = r.adSint(11);
if J = 0 then
call ..riteCO. @CODH. OAH • • lllegal byte number').

end;
if J

=1

J = Oi
call ..,rite(O, @(ODH, OAH,
end;

preamble

22. @status);

=

then configure. byteScnt
readSbyteCJ);
else configure. infoCJ - 2) = readSbyteCJ);

=-

shiel,

=

Any more bytes? (Y ar N) =="<>

shr«canfigure. infD (2) and 30H),

addressSlength
configure. info(2) and 07H;
if addressSlength
7 then addressSlength = 0.
adSloc = shrC Cconfigure. info(2) and 08H). 3);
if shrCCconfigure. info(7) and 20H). 5) then crc
if shr( (configure. info(7) and 10H), 4) then cre

i),

3;'!,
(!status)

j

4)+1);

=

2;

else crc

4.

0;

end setup'cDnfigure'parameters;
292010-52

Traffic Simulator/Monitor Station Program (Continued)

1-263

intJ
574
575

1
2

576
577
578
579
580
581

2
3
3
3
3
4

AP-274

setupSt x'parameter 5:
declaT"1!'

(511e.

i)

prot edure,

UJordi

do forever;
no.transmission = false;
transmit. bdSoffset = offset (@tbd. act'count);
if not ad'loc then
do;
call IIJriteCO,
I

call

@eODH,

OAH,

Enter a destination address in Hex

==> '),

42, @statu!.);

put$add~e5s(@t~ansmit, dest$ad~(O»,

582
583
584

4
4
3

585
586
587
588
589
590
591

3
3'
3
4
4
4
3

call crSlfl
if not ad$loc then
do;

592
593
594
595
596
597
598
599
600
601
602
603

3
3
3
3
3
4
4
4
4
5
5
4

call writeCO, @(/ Enter a number
size = readSint('1518);

604

4

call ..~iteln(O,
@(ODH, OAH, ' Transmit Data is continuous numbers (0, 1, 2, 3, I,
) '), 57, @sta1.us),
call ..~ite(O, @(' Change an~ data bVt ... ? (V or N) ==> '). 'j't,

605
606

4
5

do while yes;
call .. ~ite(O, @(ODH. OAH.

607
608
609
610
611
612
613
614

5,
5
5
5
5
5
5
5

615
616
617

5
4
3

end;
else

618

3

call

end;
else call writelnCO,

@(/

82586 i5 configured to pick up OA.

and TVPE

call IIJrite(O,
t~ansmit,

tvpe

end;
call \.fritelnCO,

(!(ODH.

'~om

OAH,

TX

buf'.~.

' Ente'r TYPE

IA. '.

'), 64, @status),

==> '),.

18,

@status);

='~ead$int(OFFFFH),

(!(ODH.

OAH,' How manlj b\ltes of transmit data?'),

3S,

~sti:ltus)

==> '),

20,

;

@status);

tbd.act$count = size o~ eOOOH,
if size <> 0 then
do,
tbd. link$offset = OFFFFH,
tbd,adO = offset (@t'$buffe~(d»,
tbd. adl = 0,
do i = 0 to 1,517,
tx$bufferCi) = il
endl

et.1.b1.ub);

' Enter a b~te numbe~ ==> ').
2,./,

i

-

call
call
call
call
call

@status);

readSint(size);
..~ite(O, @(ODH, OAH. 'Bvte '). e, @status),
out$dec$he.(i),
writeCO, @(' cury.ently contains '), 20, @status);
out$dec$he.(t.$buffe~(i»,

writeCO,

@('. '),

1, @status);

t.$buffe~(i) = ~ead$b~te(i)'
call .. ~ite(O. @(ODH. OAH. ' AnV

mD~e

bytes?

(y o~

N) ==> ').
32, es1.atus),

end;
t~ansmit.

bd$offset - OFFFFH,

c~$lf,

292010-53

Traffic Simulator/Monitor Station Program (Continued)

1-264

inter

AP-274

619
620

3
3

call init$186.time~Oi
call l.l'riteCO. @(ODH, OAH,

621
622
623
624

3
3
4
4

if yes then
do;

625
626
627
628
629
630
631

4
4
3
3
3
3
3

632
634

3
3

635

2

end setupStxSparameters;

636
637

1
2

loop.char: procedure (i.
declare (i, J. k) blJtei

638
639
640

2
3
3

641

2

end loopSchari

643

2

declare

644
645
646
647

2
2
2
2

648
649
650
651
652
653
654
655

2
2
2
2
2
2
2
2

' Setup a transmit terminal count?',

(Y or N)

==> '),

49. @status)l

stop = true;
call un"ite (0. @(ODH. OAH.

' Enter a transmit',
, terminal count ==~ '),
stop'count = Tead'int(OFFFFFFFFH),

39, @status);

end;

else stop = false;
call cT'I',
call crSlfi

call printSparameters;
call wTite(O. @(ODH. OAH.

' Good enough? (V DT N) ==) '). 29,
@stat.U5)';

642

if

~e5

end;

do k

= 1 to ii
call u..rite(O.

init:

2
2

J)i

@J'

I.

@status);

end;

procedure;
i

byte;

call
call
call
call

crSlf;
loop'chaT(13. OAH),
loop'chaT( 15. ' '),
wTiteln(O, @('TRAFFIC SIMULATOR AND MONITOR'.
, STATION PROGRAM '). ,46. @status),
call loop'chaT(7, OAH),
Initialization begun'), 23, @status);
call wTiteln(O. @(ODH. OAH,
call cr.lf.
reset = true;
cUT'cb'offset
OFFFFH,
Dutput(ESI'PORT) - NO.LOOPBACK,
output(ESISPORT)
LOOPBACK,
dhex = false;

=

=

1* set up

656
657

then return;

inte~~upt

logic *1

call set'inteTTupt '), 20, 
enff initi

procedure;

727
728

2
2

call writeln(O, @(ODH,
call ",riteln(O, (!(ODH,

OAH,
OAH,

Commands are: '),
5 - Setup CD

16, @status);
D - Di'splay "FD/CO'I,

729

2

call ",riteln(O, (!(' P - Print SCD

C - SCD Control CMD'I,

730

2

call ",riteln(O,

N - ESI Loopback Uff'I,

45,

@!!:.Latus)i
~~,

@st.atuS)i

(!(' L - ESI Loopback On

731

2

call wrlteln(O, @(' A - Toggle Number Base'), 23,

732
733
734

2
2
2.

call wl'ite'lnCO,
call writelnCO,
call writelnCO,

735

2

end pT'int$helpi

736
737

1
2

enterSscb$cmd: procedure;
declare i btjtei

@(/
@(/

(!("

45,

Z - Clear Tx Frame Counter'), 27, @status),
Y - Clear Rx Frame Counter'), ~7, C!$Jtatus);
E - Exit t!J Continuous Mode'), 28, @status),

".

1* enter a command into the SCD *1
738
739
740
741
742

2
2
2
3
3

743
744
745
746
747
748
749
750
751

3
3
4
4
4
4
4
3
2

752
754
755
756
757
759
760
761
762
763
764

2
2
2
2
2
2
2
2
2
2
2

call cr$if;
if 5cb.cmd <> 0 then
do;
call wl'itelnCO, @(' sea command lIIord is nat cleared'), 32, (tstatus);
call ",rite(O. (!(' Tru a Channel Attention? (V or NI
'I.
39, @!.tatus)i

==>

output(CASPORTI a CA;
call writ.lnCO, @e' Issued channel attention'),
call crSlf;
1"etU1"n;

25. @status);

end;
end;
call

w~ite(O,

@(' Do

~ou

want to ente1"

an~

SeD commands? (Y 01" N)
53.

if not

~e

•. then

==)

@statu~

'),

I;

~&tu,.n;

call ..,~ite(O, @(ODH, OAH, ' Ente~ cue ==:> "), '17. @.tatus);
1
raadSint(4l,
scb. cmd
scb. cmd or shlCdoubleCil, 81,
if i = 1 then scb.cblSoffset
curScbSoffset;
call ..,~it.(O, @(ODH. OAH, ' Ente~ RES bit ==> '), 21, @status);
i = ~ead.b i t;
5cb. cmd = scb. cmd or shl(i, 7)i
tall ",rite(O. @(ODH. OAH. 'Enter RUC
'I. 17. @st"tusl,
i = ~ead.int(4);
scb. cmd = scb. cmd o~ shl(i, 4);

=

=

=

==>

292010-57

Traffic Simulator/Monitor Station Program (Continued)

1-268

intJ
765

2

766
767
76B
769

2
2
2
2

770

2

AP-274

if «(scb. cbl.offset = offset (@transmit. statusII
and «scb. cmd and 0100HI
0100HI I Dr «scb. cmd and 0010HI
OOIOHI I
and not «scb. cmd and OOBOHI
OOBOHI
th.n goback = 1;
call lIIritelnCO, (teODH. OAH, I Issued Channel Attention '), 27. @statlls)'
call cr.H,
output(CA$PORTI = CA,

=

end enterSscbScmdi
print.t~peShelp:

771

=

=

call
call
call
call
call
call

procedure;

writelnCO. @(ODH.
writelnCO, @( • N
IIIritelnCQ. @(' C
writeinCO, @(' T
UJriteinCO, @( , D
writeln(O. @(' H

772
773
774
775
776
777

2
2
2
2
2
2

77B

2

end

779
7BO

1
2

setupScb: procedure;
declare Ct, valid) byte;

7Bl
7B2
7B3

2
2
3

7B4
7B5

3
3

7B6

3

7B7
7BB
7B9
790
791
792
793
794
795
796
797
79B
799
BOO
BOI
B02
B03
B04
B05

3
3
3
3
2
2
3
3
3
3
3
2
2
3
3
3
3
3
3

--

OAH. OAH. 'Command block t~pe: • I. 22. @statuf.);
IA Setup' I. 35. @statu5)i
Nap
I
Configure
M - MA Setup' I. 35, @statu~) ,
30, @statu5);
TDR'I.
Transmit
R
Dump Status ') I 3B. @statu5)j
Diagnose
S
Print this message I), 23. @statusl,

-

printSt~pe$help,

valid = false;
do lIIhile not valid;
call wT'iteCO. @(OOH,
t

=

read$char;
<> 'H'I
(t <> 'N')
(t <> 'D')
(t <> ' I')
(t <> 'S')
call write(O,
i f (t

OAH,

J

Enter command block type (H for',
, help) ==) '), 45, @status)i

and ( t <> 'h'l and (t .:> 'T'I
and (t <> In' ) and (t <> 'R'I
and (t <> 'd ' I and (t <> 'e' )
and (t <> ' i ') and (t <> 'M')
and (t <> 's ') then
, Illegal command
@(ODH. OAH.

and (t ..::> ' t ' l
and (t <> 'T' ')
and (t <> 'e ')
and (t <> 'm')
block

t~pe')

and
and
and
and

• 29,
~&1.iJ1.UE»i

else
if ( t

=

'H'I Dr

else valid

=

(t

'h') then call

printSt~peShelp,

t~ue;

end;
if (t = 'N') o~ (t = 'n') then
do;
curScbSoffset = offset (@nop. status),
nap. status = 0;
nap. cmd
BOOOH,
nap. linkSoffset = OFFFFH,
end;
if (t = ' 1') D~ (t = ' i ') then

=

dOi

= offset (@ia$setup. status);
iaSsetup. status = 0;
iaSsetup. cmd
BOOIH,
iaSsetup. link.offset
OFFFFH,

cu~Scb$affset

=

call

=

setup$ia$pa~amete~s;

end;

292010-58

Traffic Simulator/Monitor Station Program (Continued)

1-269

AP-274

if (t = 'e')

813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852

2
2
3
3
3
3
3
3
2
2
3
3
3
3
3
3
2
2
3
3
3
3
3
3
2
2
3
3
3
3
3
3
2
2
3
3
3
3
3
3
2
2
3
3
3
3
3

853

2

end setupSCbi

854
855

1
2

display.command.block:
declare (i. J) byte.
"'h pOinter,
5.1 aelector,

806
807
808
809
810
811
812

01'

= 'e') then

(t

do;

cur$cbSoffset = offset  '). 46, @status);
if yes then
do.
ca 11 cr$lf;
call writeln(O, @(' Transmit Buffer: '), 17, @status)j
UI = tbd.act$count and 3FFFH.
call print$buff(@tx$buffer(O). "'),
end;
end;
end;
if cur$cb$of'set = offset (@iaSsetup. status) then
do;
call write(O. @('---IA Setup Command Block---'), 28. @status);
call p,.intSwds (@iaSsetup. status, b);
end;
if curScbSoffset = offset (@configure. status) then
d OJ

call write(O. @('---Configure Command Block---'), 29. @status);
call print$wds(@configure. status. 9);
end;

if cur$cb$of'set

= of'set

(@mc$setup. status) then

do;

call write(O. @('---MC Setup Command Block---'). 28. @status)i
i = 4 + mc$count/2;
292010-60

Traffic Simulator/Monitor Station Program (Continued)

1-271

Ap·274

913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
92"
930
931
932
933
934

3
3
4
4
4
4
4
3
3
2
2
3
3
3
3
4
4
4
4
5

if mc.count > 24 then
do;

call printSwdsC@mc$setup. status,

16»)

call pause;
i = i - 16.

call print$wds(@mc$setup.mcSaddress(S),

i)j

end;

else call print$wds(@mcSsetup. statusJ"

i)i

endi

if cur.cb.offset = offset (@dump, status) then
do;
call wTite(O, @( '---Dump Status Command Block---'), 31, @status);
call print$wds(@dump. status, 4);
if dump, status = OAOOOH then

do.
call laIriteln(O,

@(ODH,

OAH,

' Dump Status Results'),

22,

@st.atus)

call writeSoffset(@dump$area(O»i
call CT"Slfi

= 0 to 9;
call pl'intSstT«(!dumpSarea(16*i),
end;
call print'str(@dumpSarea<160). 10);
call crSlfi
do i

5

4

q35

4

'>'36
937

4
3

938

2

end display'command$block;

939
940

1
2

displav$receiveSarea: procedure;
declare (i, k, J, 1) bvte,
chars(4) byte;

941
942
943
944

2
2
2
3

945
946
947
948
949
950

3
3,
2
2
3
4

95:

4

953
954
955
956
957

4
4
3
3
2

16),

end;
end;

call write]n(O, C!(ODH, OAH, ' Frame Descriptors: '), 21, @status);
if ad!U oc then
do;
call wrlhln(O. @(OCH. OAH • • CA. SA. and TYPE are In buffer, '. OIJB.
OAtH, 36, @!.tBttlS);
J = 3;
end;
el5e J • address'length ~ 4;
do k = 0 to J;
do I
0 to 4;
call outSword(@rfd(l)' status. k);
i f k = 0 then call wrlte'offset«!rfd(i), statu.);
else call 100pSchar(IO• • '),

=

end;

call cr.lf;
end;

call writelnCO,

.(ODH,

OAH,

OAH,

' Receive Buffer Descripto1"'s: '),

~J,

tSt.£ttU5) ,;

958
959
960
961
963
964

2

3
4
4
4
4

do k = 0 to 4;
do i = 0 to 4,
call out'word(@rbd(i),act'count. k),
if k = 0 then call writeSoff.et(@r'bd(!),act'cou"t,.
else call loopSchar(10, ' ');
end;

292010-61

Traffic Simulator/Monitor Station Program (Continued)

1-272

intJ

AP-274

965
966
967

3
3
2

~l.t-

2
2
2
3
3
3

~o1Il

J. crSl fi

end;

call I.&Irite(Q, @(ODH,

OAH,

OAH,

I

Displa\l th,. reCtHve',
(Y ar N) ==> ' l ,

bU4l'E-:";i.f
I

970
971
972
973
974
q7~

'J
3

977
979

3
3

990
991

\IRS

=

k = rbd(i).attStount and 3FFF~,
call print'buffCC!l"hll.e(ii. DufferCO),
call P8US":

d i sp Ialj'cbS,.pa:
det lare ~ blJte;

2

2
2

k)i

endi

1

993

(~d.at.us);

call ..,,.itelnCO, @(ODH, OAH.
Receive Bu-ffers. ')' 19, @status),
do i
n t ... .;,
call writeCO, @(ODH. DAH.
Receive Buffer '), 18. @c;,t::~.,,"·'
call IIIrit.$intCi. O)i
call writ.InCO, @(' : ' ) , 2. @status':

end displavSreceive$area,

2

46.

then return;

2

992
.'':;':

if not

proCedU,.ei

callI t:.IT'iteCO,

@(OOH,

OAH,

Command Block or Receive Area':'

,~

98:>
996
997
989
989
.L=-t

3
3
3
2

992

2

993
994

1
2

995

2
:;:

gobac k

.2

tall cl'Slf;
i f (b <> 'W) and (b <> 'h ') and ( b <> '9' ) and ( b (> 's' ) and
(b <> 'D') and (b '-- 'd' ) and ( b <> 'P') and (b .;." 'p
.'"d
10
'r:') and (b <> 'c ') and (b <:> 'E') and (b <> 'e ') and
(b <> 'L') and (b <> ' I ' ) and (b <> 'N') .. nd (b <> 'n' ) and
(b <> 'Z' ) and (b c.::.- '2'1) and ( b <> 'V') and ( b <> '\.I') and
(b <> 'A') and (b <> 'a' ) then
tall I&I"ite(O. (!(' Illegal command' ), 16, @status);
i f (b = 'W) or (b = 'h' ) then tall print"help,
It ,b '= 'A') or (b = 'a') then

-.-:Jt.,

997
999

3

2

2

01

"'

;=> '),

47. @statu!."
= read'chari
do while (i <:> 'R') and (i ...::... '1"') and (i (> 'C') ancJ (i <) 'c')J
call I&IritelnCO, @CODH, OAH, ' :i:ll~gal command'), 18, @status',
call write(Q, @C' Enter R or C ==> '), 18, @:status);
i = read$chari
i

enu,

if (i = 'R'I or (i :II 'r') then call Glspla1J$receive$iireai
else call di5pla~'command$block;

FoT'!'''":essScmd:

declare \",
b

procedure;

i \ blJte;

= 0,
= readSchar;

--

999
1000
1002
1003
11)04

,,:C,

2
2
2
2
2

.,

1006

3

1007
1009

3
2

if dhlu

do;

t.hen

=

dh.x
false;
call writeCO.

@(,'

Counters are displayed in decimal, '), 3!:J.

end;
@.1se
292010-62

Traffic Simulator/Monitor Station Program (Continued)

1-273

Ap·274

do;

1009
1010
1011
'012

3
3

dhex

=

truei

call wTite(O,

@('

CaunteT!. aT'e displaved in heAcide,=i",al. '), :39,
~ •.

3
2

end;
if (b = 'L') or (b = '1') then
do;

~01':

"!

1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1035
1037
1039
1041
1043

:;

3
3
"2
2
3
3
3
2
2
3
3
3
2
2
3
3
3
3
2
2
2
2
2
2

1044

2

end process$c:md.

1045
1046

I

2

getout: procedure;
declare b byte,

1047
1048
1049

2
2
2

b = read'char,

1050
1051
1052
1053
1054
1055
1056
1058

2
3
3
4
4
4
4
4

do forav.,..;
i f cst. then
do,
disable;
call process$cmd,

: , ' 'Ir ' ;

=

Qutput(ESI$PORT)
LOOPDACK.
call writeCO, @(' ESI is in Loopback Mode. '), 25, @status);
end;
if (b =

'N'~

DT"

(b

=

'n')

then

output(ESI$PORT) = NO$LOOPDACK.
call lIIT'iteCO.

end;

if (b
do;

=

'Z') or (b

count = 0;
call writeCO,
end;

if (b

=

@('

ESI

=

'I')

@('

is NOT in Loopback Mode. '), ·29.

@status);

then

Transmit Frame Counter is cleared. '), 35, estatus);

'V') Dr (b = '':1') then

do;

receive.count = 0;
scb.aln'errs, SCb.Tsc'eTl"S, scb. avrn.errs = 0;
call writeCO, @(' Receive Frame Counter is cleared. '), 34, @status);

SCb.CTc'errs,
end;

if (b

'e') or
'S') or
if (b s 'Pi) or
(b
'0· ) or
if
i f (b = 'E') or
call cr$U.

i f (b

goback = 0,
call .. rite(O.

=

Ie I )
(b
(b
's' )
(b = 'p' )
(b
'd ' )
(b
'e' )"

@(ODH, OAH.

then
then
then
then
then

call enteT"'scbScmd;
call setup$cb,
call print$scb.
"call display$cb$rpa,
1,
gob.ck

=

' Entu"command (H for help) ==:> 'I,

34,
@statu5)J

_nab lei
if gabac. then returni
call .. rite(O, (i!(ODH, OAH,

' Enter command (H foT' help)

==> ').

34.

@!JtiJtU5)J

1059
1060

3

1061

2

4

end;
end,

end ,.tout.

292010-63

Traffic Simulator/Monitor Station Program (Continued)

1-274

inter

AP-274

1062
1063

2

1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077

2
2
2
2
2
2
2
2
2
2
2
2
2
2

1078
1079
1080
1081
1082
1083
1085
1086
1087
1088
1089
1090
1091
1092
1093

3
3
3
3
2
2
2
2
2
2
2
2
2
2
2

1094

2

1095

2

1096

2

I

1097
1098
1099
1100
1101
1102
1103
1104
1105

update: proceduTe;
dec lal'l i byte;
call cr$lf;
call loop.char (10. OAH) ,
call loopSchar(28, '*')j
call "'TiteeO, @( I Station Configuration '), 23. @:status);
call Ioop$char(27. '*');
call cr.lf,
call crSlfi
call IIIriteCO, (!(I Host Address: '), 15, @:status);
call printSnetwDT'kSaddT(@ia$setup. ia$address(O»i
i = OJ
call lIIT'ite(O, @e' Multicast Address(es): '), 24, @:statuS)i
if mc$s.tup.mc$b~te'count = 0
then call writelnCO, @('Na Multicast Addresses Deofined '), 30.
else
do while i ( me.setup mc$b~te$count;
call printSnetwDTk$addT(@mcSsetup.mc$sddT'essCt»;
call 100p.char(24 • • '),
i
i + 6;
end;

@status)i

=

call IIIriteCO, @CODH). I. @statusl;
if not no.transmission then call print.parameters;
call "'riteCO, (!( I 82586 Configu1'ation Block: '), 28, @status)j
call print.strC@tonfigure. infoCO), 10),
call cr.If,
call IoopScha1'(29, '*/)j
call \lJrite(O. e(' Station Activities'), 20, @status);
call1oopScha1'(29, '*')i
call c1'Slfi
call c ... If,
call w1'iteln(O.
@C'
of GDod
of Good
CRC
Alignment
No
Rp.teive'),
73. @Stcstu5);
call w'riteln(O,
Resource
UV~1'run').
E1'ro1'S
@(' Frames
Frames
Er1'ors
73, @StC'ttU5)j
call writelnfO,
E1'rurs
E1"t"ort. '),
ee/TT'ansmitted Received
72. (!status),

*

*

end update;

main:

I

call initi
enable;
do IaIhile reset;

2

end;

I

disable;
scb. cmd = 0100H,
outputCCA.PORT)
call wait$scbi
enable;

1

1
1
1
1

CA,

292010-64

Traffic Simulator/Monitor Station Program, (Continued)

1-275

intJ
li06
1107
1108
110'1
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
113'1
1140
1141
1142
1143
1144
1145
1146
1147
1148
114'1
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166

2
1
1
1
1
1
1'
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
3
3
2
2
2
2
2
2
2
2
1
1
2
2
3
4
4
4
4
4
4
4
3
3
3
2
2
3
3
3
3
2

AP-274

do while (diagnose.statu5 and BOaOH) () BeaOHi
end;
call cr$lf;

if diagnose status

OAOOOH
Diagnose failed! '),
OAOOOH
@(' Configul"e failed!'),
1 f la.setup. status (> OAOOOH
then call writelnCO. @(' IA Setup failed! '),
if me.setup. status (> OAOOOH
then call writelnCO. @(/ Me Setup failed! '),
<~

then cail writelnCO.
If configure. status
then call wrltelnCO.

scb. cbI.offset

@e'

<>

= nffset

17 • • status);
'18,

@status);

17

C!status);

17

@status),

(@transmit. status);

call urriteln(O, @(ODH, OAH,
disable.
5tb. cmd == OOIOHi
Dutput(CA$PORT) = CA;
call wait.5cb;
enab Ie;

I

Receive Unit is active. '), 26, @statut.);

Dutput(ESI$PORT) - NO$LOOPBACK;
call cr$l fi
if not no$transmission then
do;
call write(O. @('---Transmit Command Block---'), 2e. @status);
call printSwds(@transmit. status. e);
call crSlfi
curScbSoffset = offset C@transmit. status);
call pauslf;
do z = 1 to &0;
call time(250);
endi
call writeln(O, (!(ODH, OAH. 'transmission st .. rt.d! '), 23, @status);
call c,.$If;
disable;

scb, cmd = 0100H;
output (CAtPORT)

CA;

call UJait$scbi
enable;
end;
call update;
do fo,.ever;
call write(O,' @(ODH. I ' ) , 2. @status);
d.o IJ = 0 to Si
do case 1ji
call I&Irite$int(CDunt. dhex)i
call I.IJriteSint(receive.count, dhex);
call I&Irit •• int(scb. crc.errs. dhex);
call writeSint(scb. aInSerrs. dhex);
call I&Irite$intCscb. rlc.errs. 'dhex),
call I&Irite$int(scb. DvrnSerrs, dhex)i
end;
~har.count
13 - char.count;
call loop$char(char.cDunt, , ' ) i
end;
if csts then

=

do;

disable;
call getout;
call update;

292010-65

end;
end;
end tsms;

MODULE INFORMATION:
CODE AREA SIZE
= 23C3H
CONSTANT AREA SIZE
OF85H
VARIABLE AREA SIZE = 265EH
MAXIMUM STACK SIZE
OO'l2H
19'14 LINES READ
o PROGRAM WARNINGS
o PROGRAM ERRORS

'11550
39730
'1822D
1460

DICTIONARY SUMMARY:
15'1KB MEMORY AVAILABLE
23KB MEMORY USED
(14X)
OKB DISK SPACE USED
END OF PL/M-86 COMPILATION

292010-66

Traffic Simulator/Monitor Station Program (Continued)

1-276

Ap·274

/*******************9~k~**.*************************** .********************.w.,

1*
1*
'.
Iii

186/5B6 High Integration Board init!31j.ation Routine
(This driver is configured for Ethernet/Cheapernet Desi~n
5(j t Demo Board)

.'"
1*

Vel'.

1*
1*

Ki~oshi

,

,

2.0

Nishide

1981,

Mal'ch

14,

Intel

~utpD~atiDn

<·1
*1
*1
*1

*1

'·1
*1
*1

/ **************'*.*1: iI tc. . . . . ********************************************* ..... w .. "
1* rhe conditional compilatIon ya"a",eter 'EPROM27128, determines board r(OM
size.
If it is true, the 80186'5 ~alt ~tat~ aenerator 15 programmed to
o wait state for upper 64K-byte memory locations.
if ~~ i& false,
the
wait gtate generator is programmed to 0 wait state for uppe~ t~8K-byt~
memory locaclan~
*1

ini186:
do;
~eclare hib_ir label public
declare main label external
decla~e menu laD~l eyternal

1* literals *1

5

declare lit
UMCS_reg

literally
lit
:..~r.S_l"eCJ
lit
PACS_reg
lit
MPCS_reg
lit
INT_MASK_reg
lit
ISCP$LOC$LO
lit
ISCP$LOC$HI
lit
!:cr. . CH_B_CMO
lit
SCC Ct1 ii ~.'TII
lit
Iii.
SCC:CH:A:CMO
SCC_CH_A _OIlT'.
ilt
Nt u_
lit
CR
lit
LF
lit
BS
lit
SP
lit
lit
OM
DEL
11t
BEL
lit

'li teral1~ "
'OFFAOH',
'OFFA2H',
'OFFA4H',
·OFrN:-J.l',

'OFF28H',
'03FF8H'.
'0'.
'8300H',
'B302H',
'c;:.":J04H',
, 8306H "

'0',

'OOH' ,
'OAH' ,
'OBH' ,
'20H'.
'3Fn" ,

'07FH',
'07H',

292010-67

186/586 High Integration Board Initialization Routine

1-277

inter

Ap·274

declare acp structure

6

(

_V.bUB bvta.
unu •• d (:U b"tel

iscp'addrSlo word.
iscp'addr.hi word
I

at (OFFFF6HI data (0. O. O. O. O. O. ISCP.LDC.LO. ISCPSLOC$H.,.
7

output(INT_mask_regl • OFFH. 1* mask all interrupts *1

8

2

'I

2

and initSintSclt.

10

1
2

rra: procedure (reg_nol bVte.

11
12

2

14

2

IS

2

end ,.raJ

16
17

1
2

rrb: procedure (reg_no I bvte.

18

20

2
2

21

2

22

declare rag_no bvte.
i9 (rag_no and OFHI <> 0 then output(SCC_CH_A_CMDI
return input(SCC_CH~_CMDI.

declare ,.eg_"o b"te,

if Crag_no and OFHI <>0 than output CSCC_CH_D_CMDI
return inputCSCC_CH_B_CMDI.

and OFH.

end 1',.bJ

procedure (reg_"o, value);
declare (reg_no, value) byte;

~ra:

2~

;:

24
26

2
2

27

if Creg_no and OFHI <> 0 then output C6CC_CH_A_CMDI a reg_no and OFH.
output CSCC~CH_A_CMDI • value.

2

end laIra;

2B
2"

;;

W1'b: procedure (reg_"o, value);
declare (reg_no, value) byte;

30
32

2
2

33

2

34
3~

= reg_no

if (reg_no and OFHI ~> 0 then output
output C6CC_CH_B_CMDI = value.

C6CC_CH~_CMDI

= reg_no and

O~H.

end tu,.bJ

initSSCC'D: procedure.
<:

call wrbCO'l. 01000000bl.

1* channel B reset *1
292010-68

186/586 High Integration Board Initialization Routine (Continued)

1-278

inter
36
37
38
39
40
41
42
43
44

2
2
2
~

2
2
2
2
2

46

2
2

47

2

4~

48

AP-274

1* 2 stop. no parit~. brf = 16x *1
1* rx 8 bits/chal'. no auto-enable *1
1* tx 8 bits/char *1

wrb 104.
wrb (03,
wrbl05.
wrbe 10.
wrbe II.

010011 lOb ).
11000000b) ,
01100000b) ,
OOOOOOOOb ) ,
01010110b) ,
IIIrb( 12, OOOOIOllb),
wrb( 13, OOOOOOOOb ) ;
lIIrb (14, 00000011 b),
wrb( 15, OOOOOOOOb ),

call
call
c.::.l1
call
call
call
call
call
call

call wrbe03.

call IIIrb(05.

1* rxc = txc
1* baud rate

DRG.

= 9600
source = SYS

trlc

DRG out *1

*1

CLK. enable DRG *1
1* BRG
1* all ext status interrupts off *1

11000001b) ,
11101010b),

1* scc-b receive enable *1
1* scc-b transmit enab 1 e, dtr on. rts on *1

end init$SCC$B;
,Sin:

procedure blJte public;

49
51

3
2

do whlle einputeSCC_CH_O_CMD) and I)
return e inputeSCC_CH_B_DATA))'

52

2

end cSin;

53
54

I
2

declare char blJtei

55
57

3
2

58

2

end C$Duti

59
60

I
2

r .. ad: pl"oceduT'e (fileSid,
declare fileSid ward,
msgSptr pointer.
count lIIord.

cSout:

0;

end;

0;

end;

procedul'e (char) publiCi

do while e,nputeSCC_CH_B_CMD) and 4)
outputeSCC_CH_B_DATA) = char,

msgSptr,

count, actual'ptr,

statusSptY') publiCi

actual'ptr pointer,
status$ptr pointer.
msg based msg$ptr el) b~te.
buf (200) b~te.
actual based actualsptr word,
status based status$ptr word,
i word,
ch b~te,
1* This procedure implements the ISIS read p~ocedure. All control characters *1
1* except LF, BS, and DEL a1'e ignored. If BS Dr DEL is encountered. a
*1
1* backspace is done.
*1

61
62
63
64
65
66

2
2
2
3
3

3

status = 0;
i, ch = 0;
do while (ch <> CR) and (ch <> LF) and ei
ch = c$in and 07FHi
if ech
OS) or ech
DEL) then
do;

=

<

198),

=

292010-69

186/586 High Integration Board Initialization Routine (Continued)

1-279

inter
67
loB
69
70
71

72
73
74
75
76

Ap·274

> '0

l~ I

4
4
5
5

then

-do.
i .. i - I .

cd!
call
call
call
call

'5
5

5
5

cSoutCDELI.
cSoutCBBI.
cSDutCSPI.
cSoutCDELI.
cSoutCBSI.

and.

5

ehe

4

call cSoutCBELI.
77
7B

4
3

79
BO
Bl
B2
B3
B4

3
4
4
4
4
3

B5
B6
B7
BB
B9
90

3
4
4
4
4
3

91
92
93
95
96
97
9B

3
2

99

2

and.

else
H

ch

>-

SP than'

do.
call cSoutCchl.
bu~Ci) • chI
i .. i + I.
end.
81 . .

if Cch - CRI or Cch • LFI then
do.
bufOI .. CR.
bu~Ci + II - LF.
i .. i + 2.
end.

else
call cSoutCBELI.

2
2
2

3
3

endl

call cSDutCCRI.
if i > count than i
count.
actual -= i;
do i
0 'to actual - I.
msgCiI .. buf(U.
- end.

=

=

end read;

CltS: procedura bvte publiCI

100

return «lnput(SCC_CH_B_CMDI and II

<>

01.

101

2

102

2

end csts;

103
104

1
2

..rit.: procedure (hlo!Sid. msgSptr. count. statu.Sptrl publiCI
declare (fileSid. countl .. ord.
(msgSptr. status'ptrl pointer;
msg ba.ed msgSptr (II bvte.
Itatul based .tatusSptr .. ord.
ch bvte.
i word;

105

2

1* This procedure implements the ISIS ..rit. *1

status = 0;
292010-70

186/586 High Integration Board Inltlallzatlo,n Routine (Continued)

1-280

intJ
106
107
lOB
1'09

AP-274

2
2
3
3

i

=

0;

do whlle i < count;
ch = msg(i)i
if

((ch

:>= SP) and (ch ( DEll) or (ch

CR)

or

(c

h

LF)

or

(ch

NUll

then
110
III

3
3

112
113

3
3

114

2

115

call c$out(ch);
else
i

call c$out(GM);
+ 1;

= i

end;

end write;

hi b

i r:

$IF EPROM2712B
output IUMCS_reg)

OF03BH,

1* Starting Address
no wait state *1

OFOOOOH,

output (UMCS_reg)

OE03BH,

1* Starting Address

OEOOOOH,

$ELSE

no wait state *1
$ENDIF
116
117

output(LMCS_reg)
output(PACS_reg)

03FCH,
OB3CH,

1* 16K,
1* PBA

no wait state *1

= BOCOH.

no wait state for

PSCO-3 *1

liB

OBFH,

call init$int$clti

119
120
121
122

1* Peripherals in 110 space. no At 8( A2
provided, 3 wait states +01' PSt4-6 *1

call

ini t$SCC$B,

go to main;
end

ini186;

292010-71

186/586 High Integration Board Initialization Routine (Continued)

1-281

inter

AP-274

THE 82530 SCC

APPENDIX C
80186 INTERFACE AP BRIEF

INTRODUCTION

INTERFACi: OVERVIEW

The object ofthis document is to give the 82530 system
designer an in-depth worst case design analysis of the
typical interface to a 80186 based system. This document has been revised to include the new specifications
for the 6 MHz 82530. The new specifications yield better margins and a 1 wait state interface to the CPU (2
wait states are required for DMA cycles). These new
specifications will appear in the 1987 data sheet and
advanced specification information can be obtained
from your local Intel sales office. The following analysis 'includes a discussion of how the interface TTL is
utilized to meet the timing requirements of the 80186
and the 82530. In addition, several optional interface
configurations are also considered.

The 8253'0 - 80186 interface requires the TTL circuitry
illustrated in Figure 1. Using five 14 pin TTL packages,
74LS74, 74AS74, 74AS08, 74AS04, and 74LS32, the
following operational modes are supported:
•
•
•
•
•

Polled
Interrupt in vectored mode
Interrupt in non-vectored mode
Half-duplex DMA on both channels
Full-duplex DMA on channel A

A brief description of the interface functional requirements during the five possible BUS operations follows
below.
.

DATA (D7-D8)

B25a8
.7

••
••••••
.,
••
.2

<4 DB?
37 DB6

S

THIIA

RHIIA

'fI!lmi

DI&

Jm!eli

38 DB'"

.. ..
2
89
I

~

••
82
Bl

1!T!li
~

m!

••
ao

JI'1!71mIli
fKlIB
litX1l8

3'" A... l'

aa

nu

I.

7
6

"lIEGB
"REBB
lEI
lEO

28

CHAHIIEL
A

II

17
I.
I•

.0
"
.7

CHANNEL

'rIIll9 2.
Ift'i!9 2.
'fVli9 2'

82 DI''f'

••
••

I.
I.
I.
12

1:'I'D
'fR
liYII7IImW

uee

Lt<

ON.

HOtES'

B

.,

2'
2'

•••
S!

.ou

H - PULLED HIGH THROUGH 6K OH"
UI - " ..LS?"
U2 - 14Ase8

U3 - ? ..AS''''
U4 - 1"'AS14

us - ?4LS82

74Ase4
IIRGe

"

U3

~'~'----------------------~
292010-72

Figure 1. 82530-80186 Interface

1-282

AP-274

UN ITS,

125NS/19

CLKOUT
AD

0-15
I

DT/R

ALE

90196

TCLJ)X

----~~--------~------------------------~------~
..~
~r_+-

___~~r-_o_oo_o_oo_oo_oo_o_oo_oo

~~_ _ _ _~~_ _ _ __ _

__
o_oo_oo_oo_oo_o_o0_00_00_0_00_00_00_0_00_00_0_0

TCLRH

92590

DATA

292010-73

Figure 2. 80186-82530 Interface Read Cycle

UNITS,

125 NS/19

CLKOUT

DT/R

90196

---------+-------- ""..-+-______________________~-,-----~/o

°

0.00.0 . . 0.000

-i--+______________-!---i;-_ _°i'o

- - - - - - _ _ f _ . ' - -_ _

o

0 - 0- 0
'-0
0-0
0 -.
0-0.0 - '0

ADDRESS
92590

DATA

TPDHR/S86-WR/S30 (HIGH)

292010-74

Figure 3. 80186-82530 Interface Write Cycle

READ CYCLE: The 80186 read cycle requirements are
met without any additional logic, Figure 2. At least one
wait state is required to meet the 82530 tAD access
time.
WRITE CYCLE: The 82530 requires that data must be
valid while the WR pulse is low,§ure 3. A D FlipFlop delays the leading edge of- WR until the falling
edge of CLOCKOUT when data is guaranteed valid
and WR is guaranteed active. The CLOCKOUT signal

°

is inverted to assure that WR is active low before the D
Flip-Flop is clocked. No wait states are necessary to
meet the 82530's WR cycle requirements, but one is
assumed from the RD cycle.
INTA CYCLE: During an interrupt acknowledge cycle, the 80186 provides two INTA pulses, one per bus
cycle, separated by two idle states. The 82530 expects
only one long INT A ~e with a RD pulse occurring
only after the 82530 lEI/lEO daisy chain settles., As

1-283

inter

AP-274

UNITS: 125 NS/12

T.

T.

T..

2T
IDLE S'l'A'l'ES

TI

T'
2

ToO

CLKOUT

AD "-15
80186

Dulf
TII'l'1i
RN

: ~: :::::.: :::: ::::::: ::: :::: :::::::: :::::::: :::::::: ::::::: ::: ::::::::: ::: :t:~~';:: ::rECfO~

~:::t:~~~~:

=It,;~lF·;;<'~l,==

··············1···································1············
.. ·················· .. ··········
................. .
·············1···· .. ········ .. ···················1·· .. ··· ...........................
·········,' ....
......···········1·
·········1···················

CLK

........ I..

.. ...... I ..

TII'l'1i
82530
Q

VECTOR

292010-75

Figure 4. 82530-801861NTA Cycle

illustrated in Figure 4, the INTA signal is sampled on
the rising edge of CLK (82530). Two D Flip-Flops and
two TTL gates, U2 and U5, are implemented to generate the proper INTA and RD pulses. Also, the INT
signal is passively pulled high, through a I k resistor,
and inverted through U3 to meet the 80186's active
high requiremep.t.
DMA CYCLE: Conveniently, the 80186 DMA cycle
timings are the same as generic read and write operations. Therefore, with two wait states, only two modifications to the DMA request signals are necessary.
First, the RDYREQA signal is inverted through ·U3
similar to the INT signal, and second the DTR/REQA
signal is conditioned through a D Flip-Flop to prevent
inadvertent back to back DMA cycles. Because the
82530 DTR/REQA signal remains active low for over
five CLK (82530)'s, an additional DMA cycle could
occur. This uncertain condition is corrected when U4
resets the DTRlREQ signal inactive high. Full Duplex
on both DMA channels can easily be supported with
one extra D Flip-Flop and an inverter.
RESET: The 82530 does not have a dedicated RESET
input. Instead, the simultaneous assertion of both RD
and WR causes a hardware reset. This hardware reset
is implemented through U2, U3, and U4.

need not be as extensive as the typical interface used in
this analysis. Two alternative configurations are discussed below.
8288 BUS CONTROLLER: An 80186 based system
implementing an 8288 bus controller wilL not require
the preconditioning of the WR signal through the Ii
Flip-Flop U4. When utilizing an 8288, the control signal IOWC does not go active until data is valid, therefore, meeting the timing requirements of the 82530. In
such a configuration, it will be necessary to logically
OR the lowe with reset to accommodate a hardware
reset operation.
NON-VECTORED INTERRUPTS: If the 82530 is to
be operated in the non-vectored interrupt mode (B step
only), the interface will not require UI·or U5. Instead,
INTA on the 82530 should be pulled high, and pin 3 of
U2 (RD AND RESET) should be fed directly into the
RD input of the SCC.
Obviously, the amount of required interface logic is application dependent and in many cases can be considerably less than required by the typical configuration,
supporting all modes of sec operation.

DESIGN ANALYSIS
ALTERNATIVE INTERFACE
CONFIGURATIONS
Due to its wide range of applications, the 82530 interface can have many varying configurations. In most of
thes~ applications the supported modes of operation

This design analysis is for a typical microprocessor system, pictured in Figure 5. ,The Timing analysis assumes
an 8 MHz 80186 and a 4 MHz 82530. Also, included in
the analysis are bus loading,. and TTL-MOS cOmpatibility considerations.

1-284

Ap·274

ADDRESS
LATCH

r--

MICROPROCESSOR

l;t

ADDRESS BUS

[\r

r---

~
ALE

c--i--

.---

--...£Q!:!!.RObJ!!,!L

"'-..7'

""

:>

. "()7

7'

c--'---

~

~

ROM

RAM

~

1/0

r-'----

---

l;t
f\

.~

DATA BUS

DATA
TRANSCEIVER

292010-76

Figure 5. Typical Microprocessor System

Bus Loading and Voltage Level
Compatabilities

TIMING ANALYSIS

The data and address lines do not exceed the drive capability of either 80186 or the 82530. There are several
control lines that drive more than one TTL equivalent
input. The drive capability of these lines are detailed
below.
WR: The WR signal drives U3 and U4.
101 (2.0 rnA) > Iii (-0.4 rnA + -0.5 rnA)
loh (-400 ,.A) > lih (20,.A + 20,.A)

Certain symbolic conventions are adhered to throughout the analysis below and are introduced for clarity.
1. All timing variables with a lower case first'letter are
82530 timing requirements or responses (i.e., tRR).
2. All timing variables with Upper case first letters are
80186 timing responses or requirements unless preceded by another device's alpha-numeric code (i.e.,
Tclcl or '373 Tpd).
3. In ~ writ~cIe analysis, the timing variable
TpdWR186-WR530 represents the propagation delay between the leading or traili~dge of the WR
signalleav~he 80186 and the WR edge arrival at
the 82530 WR input.

•

PCS5: The PCS5 signal drives U2 and U4.
• 101 (2.0 rnA) > Iii (-0.5 rnA + -0.5 rnA)
loh (-400 ,.A) > lih (20 p.A + 20 ,.A)

Read Cycle

INTA: The INTA signal drives 2(Ul) and U5.
101 (2.0 rnA) > Iii (-0.4 rnA + -0.8 rnA + -0.4 rnA)
loh (-400 ,.A) > lih (20 ,.A + 40,.A + 20,.A)
•

All the 82530 1/0 pins are TTL voltage level compatible.

1. tAR: Address valid to RD active set up time for the
82530. Since the propagation delay is the worst case
path in the assumed typical system, the margin is calculated only for a propagation delay constrained and not
an ALE limited path. The spec value is 0 ns minimum.
• 1 Tclcl - Tclav(max) - '245 Tpd(max)
2(U2) Tpd(min) - tAR(min)
= 125 - 55 - 20.8

1-285

+

10

+

+ Tclrl(min) +

2(2) - 0 = 63.2 ns margin

inter

AP·274
*3 Tclcl + 1(Tclclwait state) - Tclav(max) - '373
Tpd(max) - '245 Tpd - Tdvcl(min) - tAD

2. tRA: Address to RD inactive hold time. The ALE
delay is the worst case path and the 82530 requires 0 ns
minimum.
• 1 Tclcl -' Tclrh (max) + Tchlh(min)
Tpd(min) - 2(U2) Tpd(max)
=

55 - 55

+ 5 + B - 2(5.5)

=

= 375
margin

+ '373 LE

+ 125 - 55 - 20.8 -14.2 - 20 -325

=

65 ns

,

Write Cycle

2 ns margin

3. tCLR: CS active low to RD active low set ,up time.
The 82530 spec value is 0 ns minimum.

1. tAw: Address required valid to WR active low set
up time. The 82530 spec is 0 ns minimum.

• 1 Tclcl - Tclcsv(max) - Tclrl(min) - U2
skew(RD - CS) + U2 Tpd(min)

•

=

125 - 66 - 10 - 1

+2

=

50 ns margin

= 125 - 55 - 5 - 20.B
=

4. tRCS: RD inactive to CS inactive hold time. The
82530 spec calls for 0 ns minimum.
•

Tcscsx(min) - U2 skew(RD - CS) - U2 Tpd(max)

=

35 - 1 ~ 5.5 = 28.5 ns margin

• Tclch(min) - Tcvctx(max) + Tchlh(min) + '373 LE
Tpd(min) - TpdWR186=WR530(HIGH) [U2 Tpd(max) +
U3 Tpd(max) + U4 Tpd(max)]
= 55 - 55
margin

• 1 Tclcl + 1 Tchcl - Tchcsx(max) + Tclrl(min) - U2
skew (RD - CS) + U2 Tpd(min) - tCHR
125

+ 55 - 35 - 10 - 1 + 2 - 5

=

1 Tclcl - Tclcsv(max) + Tcvctv(min) - U2 Tpd(max)
+ TpdWR1B6=WR530(LOW) [Tclcl - Tcvctv(min) + U3
Tpd(min) + U4 Tpd(min)1
'
•

= 125 - 66 + 5 - 5.5
183.9 ns margin

+ 1(Tclclwait state) - 2(U2 s~ew) - tRR

= (250-50) +

= 173 ns margin

1(125) - 2(1) - 150

+ [125 - 5 + 1 + 4.41 =

4. tWCS: WR invalid to Chip Select invalid hold time.
82530 spec is 0 ns.
'
-

7. tRDV: RD active low to data valid maximum delay
for 80186 read data set up time (Tdvcl = 20 ns). The
margin is calculated on the Propagation delay path
(worst case).

• Tcxcsx(min) - U2 Tpd(max) TpdWR1B6=WR530(HIGH) [U2 Tpd(max)
Tpd(max) + U4 Tpd(max)]

• 2 Tclcl + 1(Tclclwait state) - Tclrl(max) - Tdvcl(min)
- '245 Tpd(max) -; 82530 tRDV(max) - 2(U2) Tpd(max)
=
=

+ 5 + 8 - [5.5 + 3 + 7.11 = -2.6 ns

3. tCLW: Chip select active low to WR active low hold
time. The 82530 spec is 0 ns.

131 ns margin

6. tRR: RD pulse active low time. One 80186 wait state
is included to meet the 150 ns minimum timing requirements of the 82530.
* Trlrh(min)

+ [125 - 5 + 1 + 4.41 - 0

170.6 ns margin

2. tWA: WR inactive to address invalid hold time. The
82530 spec is 0 ns.

5. tCHR: CS inactive to RD active set up time. The
82530 requires 5 ns minimum.

=

Tclcl - Tclav(max) - Tcvctv(min) - '373 Tpd(max)

+ TpdWR186 - WR530(LOW) [Tclcl - Tcvctv(min) +
U3 Tpd(min) + U4 Tpd(min)1 - tAW

= 35

+ U3

+ 1.5 - [5.5 + 3 + 7.11 = 20.9 ns margin

5. tCHW: Chip Select inactive high to WR active low
'
set up time. The 82530 spec is 5 ns.

2(125) + 1(125) - 70 - 20 - 14.2 - 105 - 2(5.5)
154 ns margin

8. tDF: RD inactive to data output float delay. The
margin is calculated to DEN active low of next cycle.

• 1 Tclel + Tchel(min) + Tcvctv(min) - Tehesx(max) U2 Tpd(max) + TpdWR1B6=WR530(LOW) [Telel Tevetv(min) + U3 Tpd(min) + U4 Tpd(min)] - tCHW

• 2 Tclcl + Tclch(min) - Tclrh(max)
2(U2) Tpd(max) - 82530 tDF(max)

=-125 + 55 + 5 - 35 - 5.5
5 = 264 ns margin

=

'250

+ 55 -55 + 10 - 11- 70

=

+ Tchctv(min) 179 ns margin

9. tAD: Address required valid to read data valid maximum delay. The 82530 spec value is 325 ns maximum.

+ [125 -5 + 1 + 4.41 -

6. tWW: WR active low pulse. 82530 requires a minimum of 60 ns from the falling to the rising edge of WR.
This includes one wait state.

1-286

inter

AP-274

• Twlwh [2Tclcl - 40] + 1 (Tclclwait state) - TpdWRI
186-WR530(lOW) [Tclcl - Tcvclv(min) + U3 Tpd(max)
+ U4 Tpd(max)] + TpdWR/186=WR/530(HIGH) [U2
Tpd(min) U3 Tpd(min) + U4 Tpd(min)] - tWW

should never exist. 82530 drivers should insure that at
least one CPV cycle separates INTA and WR or RD
cycles.

= 210 + 1(125) - [125 - 5 + 4.5 +
+ 3.2] - 60 = 135.6 ns margin

4. tWI: WR inactive high to INT A active low minimum hold time. The spec is 0 ns and the margin assunies CLK coincident with INTA.

~.2]

- [1.5 + 1

7. tDW: Data valid to WR active low setup time. The
82530 spec requires 0 ns.
• Tcvctv(min) - Tcldv(max) - '245 Tpd(max) +
TpdWR186-WR530(lOW) [Tcici - Tcvclv(min) + U3
Tpd(min) + U4 Tpd(min)]

• Tclcl - Tcvctx(max) - TpdWR186 - WR530(HIGH)
[U3 Tpd(max) + U4 Tpd(max)] + Tcvctv(min) + Ul
Tpd(min)
= 125 - 55 - [5.5 + 3 + 7.1] + 5 + 10
margin

= 5 - 44 - 14.2 + 125 - 5 + 1.0 + 4.4 = 72.2 ns
margin

=

69.4 ns

8. tWD: Data valid to WR inactive high hold time. The
82530 requires a hold time of 0 ns.

5. tlR: INTA inactive high to RD active low minimum
setup time. This spec pertains only to 82530 RD cycles
and has a value of 55 ns. The margin is calculated in
the same manner as tIW.

• Tclch - skew (Tcvctx(max) + Tcvctx(min)l + '245
OE Tpd(min) - TpdWR186-WR530(HIGH) [U2 Tpd(max)
+ U3 Tpd(max) + U4 Tpd(max)]

6. tRI: RD inactive high to INTA active low minimum
hold time. The spec is 0 ns and the margin assumes
CLK coincident with INTA.

= 55 - 5 + 11.25 - [5.5 + 3.0 + 7.1] = -50.6 ns
margin

•

Tclcl - Tclrh(max) - 2 U2 Tpd(max)

=

125 - 55 - 2(5.5)

+ Ul Tpd(min)

INTACycle:
1. tiC: This 82530 spec implies that the INTA signal is
latched internally on the rising edge of CLK (82530).
Therefore the maximum delay between the 80186 asserting INTA active low or inactive high and the 82530
internally recognizing the new state of INTA is the
propagation delay through VI plus the 82530 CLK period.
•
=

Ul Tpd(max) + 82530 ClK period
45

+ 250

=

295ns

2. tel: rising edge of CLK to INTA hold time. This
spec requires that the state of INTA remains constant
for 100 ns after the rising edge of CLK. If this spec is
violated any change in the state of INTA may not be
internally latched in the 82530. tel becomes critical at
the end of an INTA cycle when INTA goes inactive.
When calculating margins with tCI, an extra 82530
CLK period must be added to the INTA inactive delay.
3. tIW: INTA inactive high to WR active low minimum setup time. The spec pertains only to 82530 WR.
cycle and has a value of 55 ns. The margin is calculated
assuming an 82530 WR cycle occurs immediately after
an INTA cycle. Since the CPV cycles following an
82530 INTA cycle are devoted to locating and executing the proper interrupt service routine, this condition

+ 5 + 10

=

+ Tcvclv(min)

74 ns margin

7. tIID: INTA active low to RD active low minimum
setup time, This parameter is system dependent. For
any sce in the daisy chain, t1ID must be greater than
the sum of tCEQ for the highest priority device in the
daisy chain, tEl for this particular SCC, and tEIEO for
each device separating them in the daisy chain. The
typical system with only 1 sec requires t1ID to be
greater than tCEQ. Since tEl occurs coincidently with
tCEQ and it is smaller it can' be neglected. Additionally, tEIEO does not have any relevance to a system with
only one sec. Therefore t1ID > tCEQ = 250 ns.
• 4 Tclcl + 2 Tidle states - Tcvclv(max) - tiC [Ul
Tpd(max) + 82530 ClK period] + Tcvclv(min) + U5
Tpd(min) + U2 Tpd(min) - tliD
=
=

500 + 250 - 70 - [45 + 250] + 5 + 6 + 2 - 250
148 ns margin

8. tlDV: RD active low to interrupt vector valid delay.
The 80186 expects the interrupt vector to be valid on
the data bus a minimum of 20 ns before T4 of the second acknowledge cycle (Tdvcl). tIDV spec is 100 ns
maximum.
• 3 Tclcl - Tcvclv(max) - U5 Tpd(max) - U2
Tpd(max) - tlDV(max) - '245 Tpd(max) - Tdvcl(min)
= 375 - 70 - 25 - 5.5 - 100 - 14.2 - 20 = 140.3
ns margin

1-287

inter

AP·274

9. tIl: RD pulse low time. The 82530 requires a minimum of 125 ns.

= 375 - 70 - 25 - 5.5 + 5 + 6 + 1.5 - 125 =
162 ns margin

3. tWRI: 82530 WR active low to REQ inactive high
delay. Assuming destination synchronized DMA transfers, the 80186 needs two wait states to meet the tWRI
spec. This is because the 80186 DMA controller samples requests two clocks before the end of the deposit
cycle. This leaves only 1 Tclcl + n(wait states) minus
WR active delay for the 82530 to inactivate its REQ
signal.

DMACycle

• Tclcl + 2(Tclclwait state) - Tcvctv(min) TpdWAI86-WA530(LOW) [Tclcl - Tcvctv(min) + U3
Tpd(max) + U4 Tpd(max)1 - Tdrqcl - tWAI

• 3 Tclcl - Tcvctv(max) - U5 Tpd(max) - U2
Tpd(max) + Tcvctx(min) + U5 Tpd(min) + U2 Tpd(min)
- tII(min)

Fortunately, the 80186 DMA controlier emulates CPU
read and write cycle operation during DMA transfers.
The DMA transfer timings are satisfied using the above
analysis. Because of the 80186 DMA request input requirements, two wait states are necess~o prevent
inadvertent DMA cycles. There are also CPUDMA intracycle timing considerations that need to be addressed.
1. tDRD: RD inactive high to DTRREQ (REQUEST)
inactive high delay. Unlike the READYREQ signal,
DTRREQ does not immediately go inactive after the
requested DMA transfer begins. Instead, the DTRREQ
remains active for a maximum of 5 tCY + 300 ns. This
delayed request pulse could trigger a second DMA
transfer. To avoid this undesirable condition, a D Flip
Flop is implemented to reset the DTRREQ signal inactive low following the initiation of the requested DMA
transfer. To determine if back to back DMA transfers
are required in a source synchronized configuration,
the 80186 DMA controller samples the service request
line 25 ns before T1 of the deposit cycle, the second
cycle of the transfer.
• 4 Tclcl - Tclcsv(max) - U4Tpd(max) - Tdrqcl(min)
= 500 - 66 - 10.5 - 25 = 398.5 ns margin
2. tRRI: 82530 RD active low to REQ inactive high
delay. Assuming source synchronized DMA transfer,
the 80186 requires only one wait state to meet the"tRRI
spec of 200 ns. Two are included for consistency with
tWRI.

=375 - 5 - [125 - 5 + 4.5 + 9.21 - 25 - 200 =
11.3 ns margin
NOTE:
If one wait state DMA interface is required, external
logic, like that used on the DTRREQ signal, can be
used to force the 82530 REQ signal inactive.
4. tREC: eLK recovery time. Due to the internal data
path, a recovery period is required between SCC bus
transactions to resolve metastable conditions internal to
the SCC. The DMA request lines are marked from requesting service until after the tREC has elapsed. In
addition, the CPU should not be allowed to violate this
recovery period when interleaving DMA transfers and
CPU bus cycles. Software drivers or external logic
should orchestrate the CPU and DMA controller operation to prevent tREC violation.

Reset Operation
During hardware reset, the system RESET signal is asserted high for a minimum of four 80186 clock cycles
(1000 ns). The 82530 requires WR and RD to be simultaneously asserted low for a minimum of 250 ns.
• 4 Tclcl - U3 Tpd(max) - 2(U2) Tpd(max) + U4
Tpd(min) - tREe
= 1000 - 17.5 - 2(5.5) + 3.5 - 250 ns = 725 ns
margin

• 2 Tclcl + 2(Tclclwait state) - Tclrl(max) - 2(U2)
Tpd(max) - Tdrqcl - tRRI
=2(125) + 2(125) - 70 - 2(5.5) - 200 = 219 ns
margin

1-288

APPLICATION
NOTE

AP-324

June 1989 .

Implementing Twisted Pair
Ethernet with the Intel 82504TA,
82505TA, and 82521TA .

WILLIAM WAGER
TECHNICAL MARKETING ENGINEER

Order Number: 292057-001
1-289

infef

AP-324

ABSTRACT

1.0 INTRODUCTION

The market for Local Area Networks (LANs) has been
growing rapidly for several years, and LANs based on
the ANSI/IEEE 802.3-1985 standard have proven to
be the most popular. These networks are called
.CSMA/CD LANs because of their Medium Access
Control method (MAC)-Carrier Sense Multiple Access with Collision Detection. Intel has been a contributor to both the standardization and the widespread
acceptance of CSMA/CD LANs since their conception.

This Ap Note is intended to aid system designers who
have some knowledge of IEEE 802.3 standards, but
limited experience with analog design. System designers
designing Twisted Pair Ethernet LANs with Intel's
TPE products and Ethernet LAN controllers will find
this and other Intel Ap Notes useful (see also: AP-274,
Implementing Ethernet/Cheapernet with the Intel
82586, Kiyoshi Nishide; and AP-320, Using the Intel
82592 to Integrate a Low-Cost Ethernet Solution into a
PC Motherboard, Michael Anzilloti).

The two most prevalent types of CSMA/CD LANs are
called, in IEEE terminology, IOBASE5 (aka Ethernet,
Yellow Cable, or Thick Wire) and IOBASE2 (Cheapernet or Thin Wire Ethernet). Ethernet operates over a
customized coaxial cable configured as a bus and restricted to a maximum length of 500 meters-point-topoint. Ethernet transmits data at 10 Mb/s on a baseband network. Cheapernet uses the more common RO58 cable and has a maximum point-to-point distance of
185 meters; its data transmission rate is also 10 Mb/s.
Other types of CSMA/CD networks are IOBROAD36
(IO-Mb/s Broadband, 3600m on Coax) and IBASE5 (1
Mb/s Baseband, 500m on standard telephone wire).

Intel has introduced the 82504TA Transceiver Serial
Interface (TSI), the 82505TA Multiport Repeater controller (MPR), and the 82521 Serial Supercomponent
(SSC). These products simplify designing Twisted Pair
Ethernet LANs based on the emerging 10BASE-T standard. These LANs are compatible with existing ANSI/
IEEE 802.3 networks at the Physical Signaling layer
and the MAC portion of the Data Link layer. This
means that a Twisted Pair Ethernet LAN built with
these products will be software compatible with current
802.3 networks and can connect to other 802.3 networks through the standard Attachment Unit Interface
(AUI) port of a Multiport Repeater.

The cost of the cable and its installation and reconfiguration has been a factor in the acceptance of CSMA/
CD LANs. The members of the IEEE 802.3 Working
Group, including Intel, have recognized this, and we
are addressing this issue. We are· preparing a new
CSMA/CD standard (IOBASE-T) that operates at
10 Mb/s with a 100m point-to-point range and uses
unshielded, twisted-pair wiring-the common telephone wire already installed in most buildings: Besides
using a less expensive wire type, 10BASE-I0 (TPE)
uses a star topology that can operate concurrently with
normal telephone traffic, and other services, in a parallel cable plant.

A Twisted Pair Ethernet LAN comprises several ele-'
ments: data terminal equipment (DTR), medium attachment units (MAU), multiport repeaters (MPR),
and the cable plant. More complex networks, which
interconnect with existing 802.3 networks, are made
possible by using the 802.3-standard AUI port of the
MPR. Figure 1 illustrates a network that uses all these
elements..

Besides its active participation in the IOBASE-T Task
Force, Intel is now marketing products based on the
work of the task for(;;e. With these products-the
82504TA Transceiver Serial Interface, the 82505TA
Multiport Repeater controller, and the 82521 Serial Supercomponent-our customers can design high-speed
LANs that operate over unshielded twisted pair wiring,
which is usually already installed. These networks can
coexist with existing CSMA/CD networks; that is, they
can be integrated into a single network interfacing with
already installed Ethernet or Cheapernet networks.
Furthermore, Intel is committed to maintaining compatibility and conformity with the emerging standard.

Figure 1 shows three types of DTE and MAU combinations. Two have embedded MAUs, the other has an
external MAU connected to the DTE node by a standard AUI cable. Embedded MAU designs either use
the 82504TA, and its associated circuitry, or the
82521 TA SSC. The multiport repeaters are designed
around the 82505TA, they also contain one 82504TA.
Each of the eleven twisted pair ports contains an embedded MAU. The cable plant is standard telephone
wire, 4- or 25-pair unshielded twisted pair (26 to 22
gauge). Each segment uses two twisted pairs for data, .
one for transmission and one for reception, and the unused pairs can carry other services as well. In a TPE
design the maximum node-to-repeater distance is 100
meters.

1-290

Ap·324

10 Mb/s Star Wired 100m Cable Length

MPR

292057-1

Figure 1. Typical TPE Network

1-291

Ap·324
The transmit circuitry incorporates the predistortion
algorithm adopted by the lOBASE-T Task Force. This
algorithm improves overall system jitter performance
by reducing the amount of jitter induced by the twisted
pair. The line drivers will drive at full amplitude during
"thin" (50 ns) pulses and the first half of "fat" (100 ns)
Manchester pulses. They will reduce their drive level to
33% during the second half of "fat" Manchester'pulses.
This prevents the twisted pair from overcharging during the fat pulses. Without this predistortion, the overcharge would cause a delay in the zero crossing following the "fat" bit, resulting in more induced jitter. Figure 2 shows the idealized output waveform for the predistorted signal at the transmitter.

2.0 SYSTEM DESCRIPTION

2.1 Network Description
The network shown in Figure 1 is a typical representation of TPE networks designed with Intel TPE products. The network follows the lOBASE-T draft standard specifications wherever possible. We recommend
that network designers follow the same practice. Table
1 compares the TPE network features to the earlier
10 Mb/s standards, and Table 2 compares TPE networks based on the Intel products to those based on the
most likely outcome of the lOBASE-T Task Force deliberations.

MAD Line Receiver: The MAD line receiver is also dc
isolated by a transformer. It must have a matched differential impedance such that the return loss is at least
15 dB from 5 MHz to 10 MHz. The line receiver must
operate properly in the presence of a signal having a
350 mV to 2.8V differential. It must detect the start of
Idle within 1.8 bit times, and must include a squelch
circuit that rejects, as noise, any signals less than
250 mY, and accepts signals greater than 350 mV having a pulse width greater than 20 ns.

2.1.1 MEDIUM ATTACHMENT UNIT (MAU)

The MAD (i.e., the transceiver) provides the required
circuitry for interfacing with the twisted pair wire. It
performs several functions; e.g., line driving with predistortion, line reception, and collision detection. Multiport repeaters and DTEs can contain embedded
MADs or attach to external MADs.
MAD Line Drivers: The transmitter is designed to
drive a 960 properly terminated cable and must meet
all its specifications under this load (unless otherwise
specified). A transformer provides dc isolation from the
twisted pair, and the transmitter has a matched source
impedance of 960 ± 20%. It will achieve a drive level
of 2.2V to 2.8V peak differential. The power spectrum
amplitude will be less than - 30 dB at, or above,
30 MHz from its 10 MHz value. The signal is Manchester encoded like 10BASE5 and lOBASE2.

Collision Detection: The MAD detects collision by noting simultaneous activity on the transmit and receive
pair. No provision is made for receive-based collision
detection. When a transmitting station detects a collision it begins the normal 802.3 collision sequence of
jam, random backoff, and retransmit. When a repeater
detects a collision it also begins a jam and it enforces
the minimum frame length of 96 bits.

Table 1. Comparison of Network Features
Feature
Wire
Topology

TPE

10BASE5

10BASE2

Unshielded TP

Yellow Coax

Thin Coax

Star

Bus

Bus

100m

500m

185m

Software

Existing

Existing

Existing

Controller

82586/8259x

82586/8259x

82586/8259x

Data Rate

10 Mb/s

10 Mb/s

10 Mb/s

CSMAlCD

CSMAlCD

CSMAlCD

Segment Length

Access Method

Table 2. Differences between Current TPE and Expected 10BASE·T
Feature
Squelch
Collision Detect

CurrentTPE

10BASE-T

Single Pulse

Multiple Pulse

Tx and Rx Active

Tx and Rx Active for 5 Bits

Link Integrity

None

Single Linkbeat

Jabber Function

None

Watchdog Timer

DO -- 01 Loopback

None

Supported

1-292

Ap·324

Coax Cable
Tx Waveform

o

o

o

TPE
Tx Waveform

292057-2

Figure 2. Predistortion Waveform
2.1.2 MULTIPORT REPEATER

The Multiport Repeater is the central point in the starconfigured network. It is usually located in a telephone
closet or some other central wiring point. The link segments (repeater to node wiring) can then' be run using
available twisted pairs in the existing telephone cable
plant or a dedicated parallel cable plant. The repeater
conforms to the ANSI/IEEE 802.3c-1988 standard
for repeaters. It has eleven twisted-pair ports (embedded MAUs) and one AUI port.
A block diagram of an 82505TA-based repeater is
shown in Figure 3. It uses one 82505TA, one 82504TA,
eleven TP port processors, two 74LS529 latches, a
74LA154 decoder, and an AUI interface processor. The
82505T A handles the repeater state functions such as
automatic preamble regeneration, minimum frame
length enforcement, signal retiming, collision detection
and jam, and control for the LED status indicators.
The 82504TA handles Manchester decoding and clock
recovery for the incoming data packet. The AUI interface processor contains the DO line drivers and the DI
and CI line receivers as required by the ANSI/IEEE
802.3-1985 standard for AUI connectors. The
72LS 154 decoder disables the transmitter on the receiving port, and the 72LS259 latches control the status
LEDs.
.
During normal transmission without contention (i.e.,
no collisions) the repeater detects the transmitting port
and immediately begins automatic preamble regeneration (APR) to all other ports. It routes the incoming
data to the Manchester decoder and begins loading its
internal FIFO. When the FIFO reaches its threshold

the repeater ceases APR and begins to send data from
the FIFO. This data is Manchester encoded and retimed before it is rebroadcast. When a collision occurs,
the repeater stops broadcasting from the FIFO and begins transmitting a jam pattern. It continues to jam
until the collision ceases and at least 96 bits have been
transmitted to each port (minimum frame length enforcement).
The repeater also supports autopartitioning and jabber
protection. These two features prevent faulty nodes
from bringing the network down. When such a fault is
detected, the port in question is removed from the network, and the remainder of the network resumes normal operation. The repeater continually monitors the
faulty port, and when the fault is fixed the port is reconnected to the network.
2.1.3 DATA TERMINAL EQUIPMENT

Data Terminal Equipment (DTE) includes usernodes,
file servers, and other devices that can originate and
accept data packets. A TPE network uses the same controllers as other 802.3 networks. These are Intel's
82586, 82590, and 82592, as well as any future Intel
Ethernet controllers. This ensures a design continuity
that allows for migration from Ethernet or Cheapnet
designs to Twisted Pair Ethernet. The only part of the
design that requires redesign is that between the controller and the connector.
I~tel's product line supports two DTE designs. Over
the twisted· pair they are functionally equivalent; however, they differ in the way they interface to the host

1-293

inter

AP·324

'82505 MPR
82504 TSI

AUI INTERFACE

AUIRxO
AUICRS

TRxO

AUICOT

TRxO

TPS

TPS

TRMT

MCV

MCV'

TRMT

CRS

CRS

TPEN

RxC

RxC

RxO

RxO

POC
TRO'"
TCS'"

LEOF

LE08
TP PORT 1'"
LED7

POC
. TR01'"

LEO'"

TCS1'"

292057-3

Figure 3. Repeater Block Diagram

LAN controller. Figure 4 shows the first DTE design.

Table 3. Pin Assignments for MOl Connector

It is based on the 82504TA, and comprises the

82504TA, the interface logic, the twisted pair.transmitters, and the twisted pair receivers. This circuit contains an embedded MAU; i.e., it connects directly to
the twisted pair wire. The second DTE design, shown
in Figure 5, also contains an embedded MAU. It is
built around the 82521TA Serial Supercomponent and
interfaces directly with the LAN controller and the
twisted pair. The complete twisted pair design consists
of an 82521TA and the qonnector. External MAUs,
which interface a standard Ethernet AUI node to the
twisted pair, are also allowed. External MAUs are part
of Intel's future product plans.
2.1.4 LINK SEGMENT

A link segment connects two twisted pair Medium Attachment Units (MAUs); it comprises two Medium Dependent Interface connectors (RJ-45, 8-pin standard
telephone connectors), two pairs of twisted pair wire
(note to exceed 100m) and a crossover. The connector's
pin assignments are shown in Table 3.

Pin

Signal

1
2

Transmit Data + (TO + )
Transmit Data- (TO-)
Receive Data + (AD + )
Not Used
Not Used
Receive Data - (RD - )
Not Used
Not Used

3
4

5,
6

7
8

The crossover function connects the TD outputs of one
MAU to the RD inputs of the other. This function can
be implemented externally or embedded within a
MAU. If the function is embedded, then the signal
names on the connector refer to the remote.MAU. That
is Pin 1 (TD +) on a MAU with an embedded crossover is connected to the Transmit Data (+) of the remote MAU, and to its own Receive Data (+). The
crossover function is defined by the following connections between MAU A and MAU B.

1-294

inter

AP-324

OTE

= High

CLK(20 MHz)

TRxO

RO+

TPS

z

82504TA

:3;

Transceiver

'- C

Serial
Interface

iJe
c_
G> 0

RO-

TRMT

Analog
Front End

TRMT

TO+

... "
.., C

TO-

~o

'0
1lII G>

'" 0~

TPEN
POC

292057-4

Figure 4. 82504TA Based DTE Block Diagram

'-

.

CTS

G> "

TxC

TxC

Co>

TxO

TxO

e~
_N
o

III

ON

_co

RxC

RxC

c

•

'-CO
G>1lI

.eN
~CO

TO+

TD+

TD-

TO-

CTS
'-

Ill;:!

82521TA
RO+

RO+

RO-

RO-

-

....., "c
I

G>

~8

292057-5

Figure 5. 82521TA Based DTE Block Diagram

1·295

inter

Ap·324

MAUA

MAUB

TD+ 1

3RD+
6RD'1 TD+
2TD-

TD- 2

RD+ 3
RD- 6

Cheapernet networks they have an implicit software
compatibility. That is, Twisted Pair Ethernet designs
based on the 82586 (8259x) will be software compatible
with Ethernet/Cheapernet design based on the 82586
(8259x).

When an embedded crossover function is used in a
DTE to repeater connection, the crossover must be embedded in the repeater MAU. in general, repeater
MAUs have an embedded crossover, and DTE MAUs
do not. With proper use of the crossover function repeaters can be cascaded through twisted pair ports, and
two DTEs can be connected in a point-to-point network. Repeaters can be cascaded in two' ways. First,
one twisted pair port on a repeater can be designed to
have a switched (optional) crossover function. This enables a DTE connection on that port when the crossover is active, or a repeater connection when the crossover is disabled. Secondly, twisted pair ports with embedded crossovers can be connected by using a third
external crossover.

2.2 Interoperation with Existing
802.3 Networks
Twisted Pair Ethernet networks that use Intel's Ethernet controllers and TPE products are fully compatible
with existing 802.3 networks at the Medium Access
Control and Physical Signaling levels. Therefore, TPE
networks can be integrated with existing 802.3 networks to form one large network. The IEEE 802.3c1988 standard allows connecting different types of
lO-Mb/s networks. Because the repeater definition extends to a DTE type AUI connection on each port, the
type of wiring is determined by the choice of MAU.
Optionally, a repeater can have embedded MAUs on
any of its ports. The only requirement is that functionality at the Medium Dependent Interface point (e.g.,
'
coax tap or twisted pair connector) be maintained.
The 82505TA Multiport Repeater provides embedded
MAUs on 11 of the 12 ports, and an AUI connection
on the remaining port. This allows creating local twisted pair subnetworks that are connected to an Ethernet
backbone. Care must be taken not to violate the system
topology rules of 802.3 networks. The most important
of these are: (1) only one active signal path is allowed to
exist between any two stations on the network and (2)
no more than four repeaters are allowed in the signal
path between any two stations on the network. There is
an overall limit of 1024 stations on a network (repeaters
do not count as stations).

Two minor software configuration changes are required
when the 82504TA and 8252ITA are used. These
changes will not 'be necessary in future Twisted Pair
Ethernet products. Both these changes can be handled
by the application-specific soft~are driver for the TPE
application.
• Manchester Encoding. The Ethernet controller
needs to be configured for Manchester encoding.
For the 82586, bit 2, byte 14 of the CONFIGURE
command must be set to 1. For the 8259x, bit 2, byte
9 of the CONFIGURE command must be set to 1.
• External Loopback. The 82504TA and the 8252ITA
do not support the external loopback mode of the
Ethernet controllers. Software packages that used
this mode will fail without a workaround. Normally,
this is only an issue for diagnostics that use this
mode during self-test. This problem can be avoided
by modifying the software driver to look for external
loopback mode, and to do its own software loopback
when appropriate (based on a destination address
check).

3.0 NETWORK SYSTEM COMPONENT
DESIGN
The design of various TPE network system components
is presented, here. DTEs with embedded MAUs are
shown first, and then the repeater design is shown.

3.1 Designing a DTE Node Based on
the 82504TA
Figure 4 has shown a DTE node with an embedded
MAU based 011 the 82504TA. It showed the Ethernet
LAN controller, the 82504TA, the analog front-end,
and the connector. As in previous Ethernet designs, the
LAN controller provides the MAC services such as
transmission deferral, collision backoff and retransmission, CRC generation and checking, and address checking. It also provides the host interface. The 82504TA,
in conjunction with the analog front-end, provides both '
the Physical Signaling and Physical Medium Attachment services. These include carrier sense, collision detect, Manchester decoding, clock recovery, line driving,
and line receiving. The analog front-end handles the
line driving and receiving functions from the 82504TA.
3.1.1 HOST TO ETHERNET LAN CONTROLLER

2.3 Software Compatibility
Because the twisted pair networks use the same controller chips (82586 and 8259x) as current Ethernet and

The interface of the Ethernet LAN Controller is discussed in previous Intel Ap Notes, AP-274 and
AP-320.

1-296

intJ

AP-324

3.1.2 82504TA TO ETHERNET LAN
CONTROLLER

The 82504TA to controller interface consists of the di·
rect connection of TxC, TxD, RxC, RxD, and RTS.
The CRS signal to the controller is generated by a logical AND (a 74F08 is used) of CRS from the 82504TA
and RTS. CDT is the NAND of TPS and an inverted'
RTS; both the NAND function and invert function are
done by a 74FOO.
For clocking the 82504TA a clock oscillator is recommended. Many that meet the requirements of the device
are available commercially. It must meet the following
specifications.
Frequency Tolerance ..................... ~0.01 %
Rise and Fall Times ........................ ~ 5 ns
Duty Cycle ...................... 40/60% or better
Output .......................... TTL compatible
The 82586 and the 82504TA have two specification incompatibilities. These are data sheet incompatibilities
only, and will not affect performance. Work is in progress to ensure that the 82586 and 82504TA specifications are fully compatible.
• TxD setup time. The 82504TA requires a 10 ns setup time from TxD to the TxC edge. The 82586 specifies that TxD will change within 40 ns of the previous TxC edge. Therefore, if the TxC duty cycle is
not exactly 50% the TxD setup time is violated.
However, the 82586 actually places the TxD edge
approximately 25 ns from the previous TxC edge,
and it never exceeds 30 ns. The next revision of the
82586 data sheet will correct this specification problem.
• TxC duty cycle. The 82504T A does not specify the
TxC duty cycle; however, the worst case would be
better than 40/60% based on the high- and low-time
specifications and signal rise and fall times. The
82586 data sheet requires a 45/55% duty cycle for
Manchester encoding. In fact, the tight duty cycle is
only important when control of the TxD duty cycle
is important. The 82504TA can tolerate the worst
case TxD duty cycle generated by the 82586 with a
worst case TxC, therefore there is no problem. The
82586 specification will become a recommendation
in the next revision of the data sheet.

3.1.3 ANALOG FRONT-END
The analog front-end is shown in Figure 6. It consists
of two main sections, Transmit and Receive. The trans-

mit section contains the interface, the line drivers, the
EMI filter, and the line coupling devices. The receive
section consists of the line coupling devices, the EMI
filter, the line receivers, and the squelch circuitry. The
line coupling devices and EMI filter are similar for both
the transmit and receive sections, and will be described
in a common section.
The 82504TA to Line Driver Interface. The 82504TA
to line driver interface consists of the four signals from
the 82504TA (TRMT, TRMT, PDC, and TPEN), a
quad XOR (e.g., 74F86), and quad line drivers. The
design shown here uses an octal line driver
(74ACT244) with the drivers paired. The four pairs are
configured using a voltage summing circuit to give two
differential drivers, one at 67% power, and the other at
33%. During "thin" pulses and the first half of "fat"
pulses, the two differential drivers act in unison to give
100% power. During the second half of "fat" pulses,
the 33% driver is inverted to provide only 33% power
as required by the predistortion algorithm.
The circuit operates as follows. The TPEN signal is the
enable signal for the drivers. It is asserted by the
82504TA whenever the node is transmitting. During
idle, it is deasserted, and the driver enters the tri-state
mode. The Manchester data~rovided by the
82504TA on the TRMT and TRMT lines, and each
signal is fed into two XOR gates. One of the XORs for
each signal has one input grounded, therefore it acts as
a non-inverting buffer. The output of these XOR gates
feeds the two line drivers composing the 67% differential driver. Therefore, the 67% driver is always driving
the exact Manchester pattern. The other XOR gates are
also fed by the PDC signal. This signal is low for "thin"
pulses and the first half of "fat" pulses, and it is high
for the second half of "fat" pulses. These XOR gates
feed the 33% differential driver. The combination of
the PDC signal and the XOR gates ensures that the
33% driver follows the 67% drivers when 100% power
is required, and inverts when 33% power is required.
The design of this circuit is intended to present a constant driver impedance during packet transmission.
This is vital since variations in the matching of driver
impedance to the twisted pair cable impedance will
cause reflections resulting in added jitter.
High.Voltage Protection. To prevent damage to the active devices caused by high-voltage transients from the
twisted pair line, protection should be provided. We
recommend placing a pair of diodes on each of the four
differential signals (two transmit and two receive) as
shown in Figures 7 and 8. The diodes connect to the

1-297

inter

AP-324

74F86

74ACT244
22A

TRt.tT

q

A

FILTER

0

and
LINE
COUPLING
DEVICES

PDC

TRt.tT

2

B

....
0

If) .....

22A·

«t-

"""
I

0

...., CI)
c::
a::: c::
0

1.19
TPEN

U

0
"""
If)
C'I

00

NE521

74F08

FILTER

3

and

TRxD

LINE
COUPLING
DEVICES

6

TPS
4
2

V

= 300 mV @ Vee = 5V

74F175

14
20t.tHz __~t-____~~____~~____~____~
CLOCK
292057-6

Figure 6. Analog Front End

± 5V power supplies. Tliese should be placed at the
interface between the active devices and the low pass
filters so the active circuits are protected and the filter
attenuates the transients.
Filter Design. The main function of the low-pass filter
is to remove the high-frequency components of the
transmitted signal without affecting the in-band frequencies (5 MHz to 10 MHz). The high frequency components can create electromagnetic interference (EMI)
above the levels permitted by FCC regulations. The design should provide minimum inband loss and minimum-in-band ripple while providing maximum atten-

uation of frequencies above 30 MHz with appropriate
roll-off in the transition band.
The Group Delay variation is another critical factor in
the design of the filter. The group delay is defined as
the variation in signal phase with the frequency. The
group delay variation is the derivative of the group delay. The group delay variation defines the difference in
propagation delay through the filter for the frequencies
of interest. These differences in propagation delay cause
amplitude and phase distortions in the signal, which
translate into jitter.

1-298

inter

AP-324

+5V
33pF

39pF

91 pF

A'

A

-5V
+5V

r~
~1

~1

~1
8'

8
39 pF

33pF

91 pF

-5V

High Voltage
Protection

Filter
292057-7

Figure 7. Tx Filter Section

+5V
91 pF

39 pF

33pF

C

C'

o

0'
91 pF

39pF

33pF

-5V

High Voltage
Protection

Filter
292057-8

Figure 8. Rx Filter Section

1-299

inter

AP-324

The impedance of the filter must be matched to both
the transmitter i~pedance and the line impedance.
Also, balance and grounding should be tightly controlled for proper operation. Due to these considerations we recommend a differential filter built syrnmetrically on each line of the differential pairs with the impedance matched at each end.

proper balance between the two ends of the transformers, the windings should be identical. To provide appropriate impedance matching in the frequency range of
interest, the transformers should have appropriate primary and secondary induc~nce (200 I-'-H typical) and
minimal interwindjng capacitance « 20 pF).

Filters that provide all these characteristics are presented in Figures 7 (transmit) and 8 (receive). Their characteristics meet the requirements of the twisted pair environment. The requirements are as follows.
Type .................... 7 Pole, Balanced Elliptical
I/O Impedance ...... 960 ± 15% (5 MHz to 10 MHz)
3 dB Frequency ................ 17 MHz to 19 MHz
50 dB Frequency ....................... 2 30 MHz
In-Band Ripple ........................... :s; 1 dB
Line Coupling Devices. The line coupling devices,
shown in Figure 9, include the transformers, common
mode chokes, and common mode noise filters. The
transformers provide ac coupling between the line and
the circuitry while providing dc isolation. The recommended minimum isolation is 2250 Vde. To provide

The common mode choke is provided to reject common
mode radio frequency and electromagnetic interference
picked up from the unshielded telephone lines. It
should provide 1000 Vde isolation between the windings. The common mode choke has four windings, each
one connected with proper polarity, in series with the
receive and transmit twisted pairs. The balance of the
choke is very important in order to provide proper
noise cancellation while passing through the differential
signal unaffected. We recommend a common mode to
differential balance of 30 dB at all frequencies up to
20 MHz.
The common mode noise filter removes undesirable
high-frequency common mode signals picked up on the
line, or generated by the transmitter. These signals are
mainly generated by fast rise and fall times and signal
crosstalk in the transmitter.

.-.--

Common Mode Common Mode
Choke
Noise filter

2

292057-9

Figure 9. Line Coupling Devices

1-300

inter

AP-324

Line Receivers. The incoming receive signal passes
through the line coupli~g devices and the low pass filter. From there it is fed into a gated line receiver controlled by the squelch circuitry. The line receiver converts the received differential signal to TTL levels and
feeds it to the 82504TA. The receiver can be designed
using a zero crossing detector (e.g., NE521) and gated
with the TPS signal with a 74F08. A lOOn load resistor
is placed on the 74F08 output to reduce jitter induced
by the difference in the threshold mismatch between
the 82504TA input and the 74F08 output circuits.
Squelch Circuit. The, squelch circuit differentiates noise
from valid incoming data on the receive pair. It does
this by detecting signals that are above a preset voltage
level for a sufficient period. When there is no signal on
the receive pair, the squelch circuit disables the line
receiver, and deasserts the TPS signal to the 82504TA.
When a signal above the threshold arrives, TPS is asserted, and the line receiver is enabled. The squelch
circuit ensures that the receive circuits in the 82504TA
are operating only during packet reception. The
squelch circuit should meet the following specifications.
Reject ................................ < 250 m V
Accept ..................... > 350 mV and> 30 ns
The circuit shown in Figure 6 uses a high-speed comparator with an offset threshold. The output of this
comparator is fed to a retriggerable timing circuit that
controls the TPS signal to the 82504TA. To ensure recognition of the IDL (end of packet) signal, and to prevent midpacket deassertion of TPS, the timing circuit
should be set to detect positive pulses between 1.5 and
2.0 bit times (200 ns). The timing circuit can be implemented by using either a quad flip-flop (74FI75)
clocked from the 20 MHz clock generator or a retriggerable monostable multi vibrator with an appropriate
time constant. The first method provides better stability
and requires fewer discrete components. If the multi vibrator is used, then the selection of the timing components is critical. The timing capacitor must have very
low leakage with good temperature and aging stability.
The timing capacitor and resistor need to be as close as
possible to the IC to minimize stray capacitance and
noise injection.
Layout Considerations. The power and ground wiring
should conform to good high-frequency practice and
standards to minimize switching transients and parasitic interaction between various circuits. To achieve this,
the following guidelines are presented.
• Place bypass capacitors (usually 0.01 /-LF) on each
IC between Vee and ground. They should be located close to the Vee pins.

1-301

• Make power supply and ground traces as thick as
possible. This will reduce high-frequency cross coupling caused by the inductance of thin traces.
• Separate and decouple all of the analog and digital
power supply lines.
o Close signal paths to ground as close as possible to
their sources to avoid ground loops and noise cross
coupling.
• Connect all unused IC inputs (except as directed by
the manufacturer) to ground or Vee to avoid noise
injection or parasitic oscillations of unused circuits.
o Use high-loss magnetic beads on power supply distribution lines.
• Group each of the receive and transmit circuits, but
keep them separate from each other. Separate their
grounds.
" Layout all differential circuits symmetrically so
parasitic effects are also symmetrical.
" Layout the circuitry from the line connector to the
active circuitry (especially the EMI filter) on a
ground plane to prevent undesirable EMI effects.

3.2 Designing a Simplified DTE Node
Based on the 82521TA Serial
Supercomponent
A design for an 82521TA based DTE node within embedded MAU is shown in Figure 5. It includes all of the
functions described in Section 3.1, thereby relieving the
designer of those responsibilities. It is simple to use,
and it does not require mastering of pole-zero diagrams.
It is a direct interface from the Ethernet controller to
the RJ-45 connector.
Currently, the 82521 TA has the same specification incompatibilities with the 82586 as the 82504TA does,
and these will be resolved concurrently. There is one
added signal, Clear to Send (CTS), its implementation
is optional.
The layout of the 82521TA and the RJ-45 connector
should keep the TD +, TD, RD + , and RD signal lines
as short as possible. The power supply traces (Vee,
VEE, Voo, and ground) should be as thick as possible,
and bypass capacitors should be placed between each
power supply and ground. We also recommend laying
out the 82521TA on a ground plane.

intJ

Ap·324

The 82S0STA to Line Driver Interface. The 82505TA
to line driver interface consists of the fout signals from
the 82505TA (TRMT, TRMT, PDC, and TPEN), the
port enable (PEx) signal from the port disable control,
two NAND gates, a quad XOR (e.g., 74F86), and quad
line drivers. The design shown here uses an octal line
driver (74ACT244) with the drivers paired. The four
pairs are configured using a voltage summing circuit to
give two differential drivers, one at 67% power, and the
other at 33%. During "thin" pulses and the first half of
"fat" pulses, the two differential drivers act in unison to
give 100% power. During the second half of "fat" pulses, the 33% driver is inverted to provide only 33%
power as required by the predistortion algorithm.

3.3 Designing a Multiport Repeater
Using the 82505TA
Figure 3 shows the multiport repeater based on the
82505TA (with one 82504TA). The repeater contliins
11 twisted pair ports with embedded MAUs and 1 AUI
port. The 82505TA controls the operation of the repeater in accordance with ANSI/lEEE 802.3c-1988
repeater unit specifications; this includes signal retiming, automatic preamble generation, autopartitioning,
and jam signal generation. The 82504TA performs
Manchester decoding and clock recovery during an active incoming signal. Two addressable latches
(74LS259) are used to control the 16 LED indicators.
A 4-to-16 decoder (74LSI54) is used to disable the
transmitter of the receiving port during transmission
without contention. The Twisted Pair port functions
contain the line drivers, the line receivers, the filter, and
the isolation required for a twisted pair embedded
MAU. In addition, one AUI interface is present to provide access to existing (IEEE 802.3) 10 Mbls baseband
segments.
3.3.1 82505TA TO 82504TA INTERFACE AND
CLOCK GENERATION

The 82505TA to 82504TA interface is straightforward.
It consists of six signals directly connected between the
devices. The signals are TRxD, TPS, MCV, CRS, RxC,
and RxD. The interface is shown in Figure 3.
A single clock oscillator is recommended for clocking
the 82505TA and 82504TA. The requirements are identical to those shown for the DTE design using the
82504TA. They are:
Frequency Tolerance ..................... ~0.01 %
Rise and Fall Times ........................ ~ 5 ns
Duty cycle ...................... 60/40% or better
Output .......................... TIL compatible
3.3.2 TWISTED PAIR PORT DESIGN

The design of the twisted pair port circuits is nearly
identical to the analog front-end circuits of the DTE
design based on the 82504TA. It is shown in Figure 10.
The design consists of two mian sections, transmit and
receive. The transmit section contains the interface circuits, the line drivers, the EMI filter, and the line coupling-devices. Conversely, the receive section consists of
line coupling devices, an EMI filter, line receiver,
squelch circuit, and interface circuits. The line coupling
devices and noise filter are similar for both the transmit
and receive sections, and will be described in a common
section.

The circuit operates as follows .. The TPEN signal is
inverted and NAND'd with the individual port's Port
Enable signal. This generates the enable signal for that
port's drivers. It is asserted whenever the port is transmitting; i.e., when another port is receiving, or during a
collision jam. During idle it is deasserted, and the drivers enter the tri-state mode. The Manchester data is
provided by the 82505TA on the TRMT and TRMT
lines, and each signal is fed into two XOR gates. One of
the XORs for each signal has one input grounded,
therefore it acts like a non-inverting buffer. The output
of these XOR gates feeds the two line drivers composing the 67% differential driver. Therefore.. the 67%
driver is always driving the exact Manchester pattern.
The other XOR gates are also fed by the PDC signal.
This signal is low for "thin" pulses and the first half of
"fat" pulses, and it is high for the second half of "fat"
pulses. These XOR gates feed the 33% differential driver. The combination of the PDC signal and the XOR
gates ensures that the 33% driver follows the 67% drivers when 100% power is required, and inverts when
33% power is required.
The design of this circuit is intended to present a constant source impedance during packet. transmission.
This is vital since variations in the matching of driver
impedance to the twisted pair cable impedance will
cause reflec~ions resulting in added jitter.
High.Voltage Protection. To prevent damage to the active devices due to high voltage transients from the
twisted pair line, high-voltage protection should be provioed. We recommend placing a pair of diodes on each
of the four differential signals (two transmit and two
receive) as shown in Figures 7 and 8. The diodes connect to the ± 5V power supplies. These should be
placed at the interface between the active devices and
low pass filters so that the active circuits are protected,
and the filter attenuates the transients.
Filter Design. The main function of the low-pass filter
is to remove the high-frequency components of the
transmitted signal without affecting the in-band

1-302

infef

AP-324

74ACT2-4'"

m"T~~:q~[~~~~~~~~~~~~~r---~
I

FILTER

,,'

LINE
COUPLING
DEVICES

""o
U

",2

.
g-

... u

iii

,I •c

'" ug

g-

'"1::o

PEx

1----=::---'

g-

FILTER

co,
LINE

:;
~

+-------:+---"""+-..,....-r~ cg~~~~G

v = 300mV 0 Vee '" 5'1

20t.lHZ_-.l==========..J
CLOCK

292057-10

Figure 10. TP Port x

(5 MHz to 10 MHz) frequencies. The high frequency
components can create electromagnetic interference
(EMI) above the levels permitted by FCC regulations.
The design should provide minimum in-band loss and
minimum in-band ripple while providing maximum attenuation of frequencies above 30 MHz with appropriate roll-off in the transition band.
The Group Delay variation is another critical factor in
the design of the filter. The group delay is defined as
the variation in signal phase with the frequency. The
group delay variation is the derivative of the group d~­
lay. The group delay variation defines the difference.m
propagation delay through the filter for the frequencIes
of interest. These differences in propagation delay cause
amplitude and phase distortions in the signal, which
translate into jitter.
The impedance of the filter must be matched to both
the transmitter impedance and the line impedance.
Also balance and grounding should be tightly controll;d for proper operation. Due to these considerations we recommend a differential filter built symmetrically on each line of the differential pairs with the
impedance matched at each end.
Filters that provide all these characteristics are presented in Figures 7 (transmit) and 8 (receive): Their ~hara~­
teristics meet the requirements of the tWIsted paIr envIronment. The requirements are as follows.
Type .................... 7 Pole, Balanced Elliptical
I/O Impedance .......... 96.n ± 15% (5 to 10 MHz)

3 dB Frequency ................ 17 MHz to 19 MHz
50 dB Frequency ....................... :;;: 30 MHz
In-Band Ripple ............ .' .............. :,; 1 dB
Line Coupling Devices.' The line coupling' devices,
shown in Figure 9, include the transformers, common
mode chokes, and common mode noise filters. The
transformers provide ac coupling between the line and
the circuitry while prmdding dc isolation. The recommended minimum isolation is 2250 Vdc' To provide
proper balance between the two ends of the transformers, the windings should be identical. To provide appropriate impedance matching in the frequency ~ange ~f
interest the transformers should have appropriate Primary a~d secondary inductance (200 ,...H typical) and
minimal interwinding capacitance «20 pF).
The common mode choke is provided to reject common
mode radio frequency and electromagnetic interference
picked up from the unshielded telephone lines: It
should provide 1000 Vdc isolation between the wmdings. The common mode choke has four windings, each
one connected with proper polarity, in series with the
receive and transmit twisted pairs. The balance of the
choke is very important in order to provide proper
noise cancellation while passing through the differential
signal unaffected. We recommend a common mode to
differential balance of 30 dB at all frequencies up to
20 MHz.
The common mode noise filter removes undesirable
high-frequency common mode signals picked up on the
line, or generated by the transmitter. These signals are

1-303

inter

AP-324

'mainly generated by fast rise and fall times and signal
crosstalk in the transmitter.

• Close signal paths to ground as close as possible to
their sources to avoid ground loops and noise cross
coupling.
• Connect all unused IC inputs (except as directed by
the manufacturer) to ground or Vee to avoid noise
injection or parasitic oscillations of unused circuits.,
• Use high-loss magnetic beads on power supply distribution lines.
• Group each of the receive and transmit circuits, but
keep them separate from each other. Separate their
grounds.
• Layout all differential circuits symmetricalIy so
parasitic effects are also symmetrical.
• Layout the circuitry from the line connector to the
active circuitry (especially the EMI filter) on a
ground plane to prevent undesirable EMI effects.

Line Receiver. The incoming receive signal passes
through the line coupling devices and the low pass filter. From there it is fed into a gated line receiver controlled by the squelch circuitry. The line receiver converts the received differential signal to TTL levels and
feeds it to the MPR. The receiver can be designed using
a zero crossing detector (e.g., NE521) and gated with
the TCSx signal with a 74F08.
Squelch Circuit. The squelch circuit differentiates noise
from valid incoming data on the receive pair. It does
this by detecting signals above a preset voltage level.
When there is no signal on the receive pair, the squelch
circuit disables the line receiver, and deasserts the
TCSx signal to the 82505TA. When a signal above the
threshold arrives, TCSx is asserted, and the line receiver is enabled. The squelch circuit ensures that the receive circuits in the 82505TA are operating oniy during
packet reception. The squelch circuit should meet the
following specifications:
Reject ................................ <250 mV
Accept ..................... > 300 mV and > 30 ns
The circuit shown in Figure 10 uses a high-speed comparator with an offset threshold. The output of this
comparator is fed to a retriggerable timing circuit that
activates the TCSx pin of the 82505TA. To ensure recognition of the IDL (end of packet) signal, and to prevent mid packet deassertion of TCSx, the timing circuit
should be set to detect positive pulses between 1.5 and
2.0 bit times (200 ns). The timing circuit can be implemented by using either a quad flip-flop (74FI75)
clocked .from the 20 MHz clock generator or a retriggera!>le monostable multivibrator with an appropriate
time constant. The first method provides better stability
and requires fewer discrete components. If the multivibrator is used, then the selection of the timing components is critical. The timing capacitor must have very
low leakage with good temperature and aging stability.
The timing capacitor and resistor need to be as close as
possible to the IC to minimize stray capacitance and
noise rejection.
Layout Considerations. The power and ground wiring
should conform to good high-frequency practice and
standards to minimize switching transients and parasitic interaction between various circuits. To achieve this,
the following guidelines are presented.
• Place bypass capacitors (usually 0.01 /loF) on each
IC between Vee and ground. They should be located close to the Vee pins.
• Make power supply and ground traces as thick as
possible. This will reduce high-frequency cross coupling caused by the inductance of thin traces.
• Separate and decouple all of the analog and digital
power supply lines.

3.3.3 AUI PORT
The AUI port circuitry is shown in Figure 11. It comprises interface circuits, the DO line drivers, two quad
o flip-flops (74FI75), and terminated line receivers for
the, DI (squelch and data) and CI (squelch only) cir~
cuits.
The CI squelch line receiver feeds the 0-0 and clear
inputs for one of the quad 0 flip-flop circuits. When a
signal larger than the squelch offset is seen, the flipflops are cleared and AUICDT is asserted. This continues for as long as CI is active. During the start of idle,
the squelch teceiver output is held high, and the flipflops set in sequence. After four clocks, 150 ns to
200 ns, the last flip-flop is set, and AUICDT deasserts.
It remains deasserted during the entire idle period.
The 01 line receivers work in much the same way, except that activity on CI, or an active transmission will
inhiJ?it AUICRS. The data channel on 01 is processed
without a voltage offset, and is gated by AUICRS. In
this way, the least amount of jitter is added on the
AUIRxD line, and the data channel is not sensitive to
idle noise.
The DO line drivers are controlled by the TPEN and
PEl 1. The drivers should activate when both are asserted. A voltage divider is provided after the drivers to
achieve the proper driver levels.
3.3.4 PORT DISABLE CONTROL
The Port Disable Control, shown in Figure 12, is performed by a 74LS154 4-to-16 decoder. During transmission without contention, the address of the originating port is given to the decoder, and the control line
asserted. This in turn disables the transmitter to that
port. When a transmit based collision occurs, the controlline to the decoder is deasserted, and jam is broadcast on all ports.

1-304

inter

AP-324

NE521
CI+
CI-

~

c:I

:1l
AiTICDT
20 MHz
CLOCK

V=300mVOVCC =5V

~

L.

01+
L.

2u

.,c:

01-

G)

E
.E.,
c:

~

c:

I-

0
U

NE521

".

u

..'" ..'"
c:I

0

iii

c:I

L.

AUICRS

~

G)

..

::>

E

-<

.,
15
.,
.,"0::

.c:

W

1::
0
":;:;

20MHz
CLOCK

:;

AUIRXO

::;

74ACT244
10011
DO+

TRMT

10011
00-

TRMT

. .
c:I
....

c:I
....

PEll

'fiiEN

292057-11

Figure 11. AUI Port

1-305

intJ

AP-324

3.3.5 LED CONTROL

4.0 UPGRADE PATH TO THE FINAL
10BASE-T STANDARD

LED' control (Figure 13) is handled by two 8-bit addressable latches (74LS259). The controller cycles
through the addresses for the LEOs every 105 ms, and
will tum each one on or off. The three least significant
address bits (LO-L2) for the LED control are fed to
each 8-bit latch. The most significant address bit (L3)
controls the enable line to the two packages. When it is
strobed by LEDSTRB, the LEDCTRL signal determines the state of the LED.

As the IOBASE-T Task Force completes writing the
standard, Intel is finalizing its plans for a standardcompliant product. Our commitment is to provide an
upgrade to the final standard as soon as possible, while
minimizing the effort required by our customers to implement it. In addition, Intel will ensure that networks
designed with our current (prestandard) products will
coexist with lOBASE-T networks. That is to say, there
is no built-in -obsolescence with these current products.

74LS154
PDO
,:,.
CJ

PDl

0

iii
....
II)

....0
II)

a.

II)

0::

PD2
PD3
PDCTL

23

22
21
20
19
18

A

PEO
PEl

B

PE2

C

PE3
D

PE4

G1

PE5

G2

PE6
PE7

1::
0
a.
:;:;

PE8
PE9

:;
~

Qll

13

PE10
PEll
292057-12

,:,.
CJ

0

LO
Ll

iii
....
(I)

L2

II)

LEDCTRL

....0
a.

II)

0::

1::
0
a.

:E
::J

~

L3
LEDSTRB

inter

AP-324

Prestandard and standard-compliant networks will coexist at the AUI interface. Network sections based entirely on prestandard components will be able to connect to network sections based entirely on compliant
components through coax backbones, or through external MAUs connected to the AUI ports of the repeaters.
The simplest upgrade path will be a DTE designed with
the 82S21TA Serial Supercomponent. Here, the user
will merely have to substitute the standard-compliant
Supercomponent, and his design will work. At this time
we are planning to include a prestandard compatible
mode for the device, which will be a strapping option.
Since the 82S21TA has defined the pins required for
this mode, users can include either mode of operation
in their designs, or the ability to select between them.
Upgrading 82S04TA designs will be slightly more difficult, since the standard-compliant device will have
more functions integrated; e.g., line drivers, line receivers, and interface logic. These functions were not defined by IOBASE-T when the 82S04TA was designed,
therefore they were intentionally not included. This will
require that the system designer change the design for
DTE nodes based on the 82S04TA, but will allow reductions in the bill of material cost and board space
requirements for the design.
Intel intends the 82S0STA standard-compliant product
to incorporate the Manchester decoder and clock recovery functions; therefore, an 82S04TA will not be
needed in the repeater. Intel further intends the device
to be backward compatible with the previous version,
that is, the new controller can be plugged into an old
controller socket. The standard-compliant MPR will
also include the capability for parallel expansion, allowing repeater design with more than II twisted pair
ports.
Overall, the upgrade from the current products to standard-compliant products is easy, and incorporates low-

er cost, higher functionality, or both. The 82S21TA
SSC was designed to eliminate the effort (and the risk)
required for compliance. In both the case of the
82S04TA and 82S0STA, the upgrade will require minimal redesign, and will maintain or reduce the requirements of material, board space, and power consumption.

5.0 SUMMARY
In this Application Note, a 10 Mb/s Local Area Network has been introduced that uses standard telephone
twisted pair wiring and a star configuration for cost
savings and flexibility. It is based on the IEEE 802.3
standard for CSMA/CD medium access. It complies
with the standard at the MAC and PLS levels, and
follows the emerging 10BASE-T standard at the PMA
level. This network type is fully software compatible
with and can coexist with current Ethernet or Cheapernet networks. The hardware connection is made by including an 802.3 defined AUI port and complying with
the repeater standard ANSI/IEEE 802.3c-1988.
Intel has introduced three products for designing network components (DTEs and repeaters). DTE design
can be done with either the 82S21TA Serial Supercomponent or the 82S04TA Transceiver Serial Interface.
The Supercomponent contains all the circuitry required
between the Ethernet controller and the RJ-45 connector. It also provides a transparent upgrade path to a
standard compliant design. Multiport repeaters can be
designed using the 8250STA with an 82S04TA. It allows for II twisted pair ports and I AUI port.
Finally, upgrade paths to the upcoming IOBASE-T
standard for Twisted Pair Ethernet were presented.
This simplest path is for designs which use the supercomponent; however, all designs can be easily upgraded
to the standard when it is available.

1-307

APPLICATION
NOTE

AP-327

July 1989

Two Software Packages
for the 82592 Embedded·.
LAN Module

JOSEPH DRAGONY
APPLICATIONS ENGINEER
URI ELZUR
SYSTEM VALIDATION
INTEL CORPORATION

Order Number: 292062-001
1-308

intJ

AP-327

1.0 INTRODUCTION
This Application Note is a companion piece to AP-320,
Using the Intel 82592 to Integrate a Low-Cost Ethernet
Solution into a PC Motherboard. While AP-320 deals
mostly with hardware issues this Application Note
deals almost entirely with software. Two programs are
presented. One is written in "C" and the other is written in assembly language. The NetWare driver presented in this Application Note is a revised version. of the
code in section 7 of A~-320.

1.1. Objective
This Application Note was written to serve as a design
example to aid the user in developing software for the
Intel 82592 LAN Controller. Two programs are provided. The ELM Exerciser Program demonstrates the
embedded LAN architecture and provides the user a
tool for exercising the 82592 in a system environment.
This program is written mainly in the "C" programming language with assembly language used when necessary. The NetWare driver provides an example of an
interface to a widely used networking package. The
NetWare driver provides an avenue for evaluation of
the ELM concept in a real LAN environment. The
Net Ware driver code provides routines that accomplish
all of the common functions required by LAN interfaces. This code should be adaptable to drivers for network software packages other than NetWare without
too much effort. The NetWare driver is written completely in assembly language.

'1.2 Acknowledgements
We would like to thank Dror Avni, Gideon Prat, Zeev
Sperber and Koby Gottlieb of Intel Israel Design Center for their excellent support during the development
of the Exerciser software. We also thank Ben L. Gee of
San Jose, California and Drex Dixon of Novell for their
advice during the development of the NetWare driver
software.

2.0 ELM HARDWARE
The ELM is intended to demonstrate the concept of
embedded LAN connections. This concept could be implemented either directly on the motherboard of a microcomputer system or as a socket option similar to
todays math coprocessor sockets. The ELM illustrates
how little board space this concept requires, and also
makes it possible to evaluate the performance potential
of the nonbuffered architecture. The ELM is not intended as a final solution. Additional hardware features
such as a DMA stop register and DMA capable of
chaining noncontiguous buffers could simplify the driver software.

The ELM is implemented as a small printed circuit
board containing an 82592 Advanced CSMA/CD
LAN Controller, two PALs, and two latches. It is connected by a ribbon cable to an analog module, which
provides the interface to the media. There are two analog modules available. They are an Ethernet module
and an Ethernet/Cheapernet module. Using this approach, other analog modules, for example, StarLAN
or twisted Pair Ethernet, could be implemented without
modifying the digital module.
The ELM is designed to function in PC AT compatible
systems. It has been used in the Intel SYP301 system,
Compaq Deskpro 386-16, Compaq Portable 386-20,
Compaq Portable 286, and both 6- and 8-MHz IBM
PC AT machines. The ELM takes liberties with the
refresh cycles of the PC. It does not sense the system's
refresh request and can cause refresh cycles to be
missed occasionally. In a commercial implementation a
timer should be used to limit the amount of time the
ELM can control the bus. The ELM hardware and
driver software are used daily by one of the authors as
his connection to our department LAN and no problems have been caused by the lack of a refresh kickoff
timer. The module uses two of the system's 16-bit
DMA channels to provide transmit and receive DMA.
Channels 6 and 7 are used. The module also uses the
IntlO interrupt line. None of these hardware requirements are jumper selectable. The module also requires a
small modification to the system motherboard. A connection must be made to the EOP pin of the DMA
controller to allow autoinitialization to be controlled by
the module for retransmission in case of collision. This
can be accomplished by soldering a binding post to the
EOP pin of the secondary 8237A DMA controller. In
cases where a connection to EOP cannot be made, the
software would have to be altered to allow retransmission to be controlled by the CPU.
As well as providing all required address decoding, the
two PALs interpret the Tightly Coupled Interface
handshake signals from the 82592 and generate control
signals to the latches and the DMA controller. These
signals accomplish two things. First, at the end of a
received frame, the Tightly Coupled Interface generates
a handshake. The PALs convert this to a signal that
latches the last location of the frame just received. The
82592 transfers length and status information into the
memory as the last four words of a received frame.
Using this information it is possible to reconstruct a
string of frames in memory. This feature of the module
allows reception of back-to-back frames. Second, when
a collision occurs, the Tightly Coupled Interface generates a handshake, which the PALs use to send an EOP
to the system's DMA controller. This allows the ELM
to execute a retransmission without intervention by the
CPU. This feature serves two purposes. The CPU is
free to continue the processing it is'involved with, and
the node is also guaranteed fair and equal access to the
media. When the CPU must actually handle retrans-

1-309

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AP-327

mission it is unlikely that the station will be ready to
retry access to the link in a timely fashion.

memory containing the packet to be transmitted, The
driver routine DriverSendPacket is then called. DriverSendPacket processes the ECB and constructs the me. dia specific frame, which allows the information to be
transmitted to the target node on the Iletwork. When
the attempt to transmit the frame has been completed,
the driver stuffs a completion code into the proper position in the ECB and passes it back to IPX through a
call to the IPX routine IPXHoldEvent. IPX puts the
ECB in a queue and later does the processing required
to complete the operation.
.

Section 2 Design Documentation for
82592 Embedded LAN Module Novell
NetWare* Driver
3.0 OVERVIEW
The Novell NetWare* Driver for the 82592 Embedded
LAN Module (ELM) is the first NetWare driver internally generated by MCFG LAN Marketing. The purpose of the Embedded LAN Module project is to demonstrate the feasibility of an embedded Ethernet LAN
connection.By providing a driver for a very widely used
Network Operating System (the popular NetWare from
Novell, Inc.) we are attempting to provide an tool for
evaluating this concept under real network conditions.
This driver is a workstation shell driver. This section of
the Application Note is intended to be used in conjunc-.
tion with the program listing in Appendix C. It is presented as an adjunct to the comments in the source
code listing itself. Hopefully the text will shed the needed light where the source code comments fail to illuminate.
The first part of this section contains an overview of the
requirements of a NetWare driver to allow those unfamiliar with NetWare drivers to follow the discussion. A
bibliography is provided as an appendix for those who
desire more detailed information. The balance of the
section is a discussion of each routine the driver software. provides. Each routine is first explained from a
functional point of view. Then any hardware considerations are discussed. Where it is warranted, alternative
approaches to the routine are given.
This document is not meant to be a tutorial on writing
Novell NetWare driver software. It is a discussion of
the generation of a single driver for a particular piece of
hardware. This driver is a demonstration tool and is not
represented to be a commercial NetWare driver. Neither. the author nor .Intel Corporation accept any responsibility for the use or misuse of this driver or of this
documentation. For.complete information on NetWare
driver generation please contact Novell.
'
Novell's NetWare Network Operating System uses an
implementation of the Xerox Internetwork Datagram
Packet (IDP) protocol called the Internetwork Packet
Exchange (IPX) protocol. It provides the developer a
set of media independent services, and dictates a set of
services that the driver must provide. Information concerning transmit and receive operations are communicated between IPX and the driver by using Event Control Blocks (ECBs). For example, if Net Ware wants to
transmit a packet, a transmit ECB is prepared that contains address information and a list of fragments in
*NetWare is a registered trademark of Novell Incorporated

NetWare requires the driver to provide several routines
for its use. Some of these routines may not be required
by a driver and can be implemented as a simple return.
This driver implements the routines DriverDisconnect
and DriverOpenSocket as a return. The remaining routines are implemented and are listed below.

• DriverInitialize configures the LAN adapter hard.ware and any variables that need to be initialized at
start up time such as the node' address.
• DriverSendPacket and DriverBroadcastPacket are
implementect. as a single routine with two labels at
the entry point. This routine processes the transmit
ECB that is passed to it and make a best effort attempt to send it to the target node. It is not a guaranteed delivery routine.
• DriverISR is the interrupt service routine for the
driver and processes all interrupt events.
• DriverPolI checks to see if a transmit is in progress.
If there is no active transmit it returns. If a transmit
is underway DriverPolI checks to see if it has timed
out. If so, the transmission i~ aborted and its ECB is
returned with an error code.
• DriverCancelRequest searches the transmit queue
for the specified ECB and removes it from the
queue. It then stuffs the completion code and returns.
• DriverCloseSocket unlinks all pending ECBs for the
specified socket and returns them to IPX.
• DriverUnhook is used to disinstall the driver if no
active file server can be found during initialization.
This involves restoring the interrupt vector to its
original value and disabling the LAN adapter so it
will not affect system operation.
• SetInterruptVector is called by DriverInitialize to
insert the interrupt vector for the LAN adapter into
the correct location in the system's interrupt vector
table after saving any vector that is already there:

4.0 DRIVER SOFTWARE ROUTINES
4.1 Driverlnitialize
This is the first routine IPX calls when the driver software is being loaded. This routine is responsible for

1-310

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AP-327

initializing the LAN adapter hardware and any variables or memory structures required by the driver. It
also sets the interrupt vector in system RAM after saving any vector already there. When IPX calls this routine it specifies a point in memory for the initialization
routine to place the node address.
The first thing this driver does is set the IPX variable
"MaxPhysPacketSize" to 1024. This value is used when
attaching to a fileserver to negotiate the largest packet
size that will be passed between the two stations. This
allows transferring packets larger than the 576-byte default packet size between the fileserver and the workstation.
4.1.1 GENERATING A STATION ADDRESS
The next action generates a station address. Since the
ELM has no address PROM the driver generates the
address by using a combination of hard-coded numbers
and the value read from the system's real-time clock.
The real-time clock is read using function 2Ch of the
DOS interrupt 21h. The first two bytes of the address
are OOh and AAh, which are Intel's Ethernet code. The
next three bytes are the minutes, seconds, and hundredths of seconds read from the real-time clock. The
sixth byte is 7Eh, which' was a dysteieological choice on
the authors part. This technique gives a high likelihood
that several ELMs can be operated in a small network
without duplicate addresses occurring. A commercial
implementation of the ELM concept should be provided with a hard-coded address in PROM or EPROM on
the card. After the address bytes have been moved into
the drivers local variable array they are copied to the
location indicated by IPX in the DI register.
When the address initialization has been completed, the
driver initializes some parameters from the hardware
configuration table. This is mainly done as an example,
since there is only one possible hardware configuration
for this module. However, the code required to step
through the tables is provided.
4.1.2 INITIALIZING THE INTERRUPT VECTOR
Initializing the interrupt vector is the next action. The
interrupt number is read from the configuration variable confi~irq_loc and placed in the AL register.
The offset of the interrupt service routine is moved into
the BX register then SetlnterruptVector is called. SetInterruptVector first generates the mask variables for
the 8259A by writing a one into DL and then shifting it
left a number of times corresponding to the value
passed in AL. The unmask variable is then generated
by the negation of the value in DL. SetlnterruptVector
then saves the vector for the interrupt that the board
will use and inserts the vector for DriverISR in its
place. The routine then returns control to DriverInitialize.

Upon returning from SetInterruptVector the ELM is
enabled by a write to location 303h. The PALs decode
this write, and enable DMA and interrupts from the
ELM to the system (as well as reads and writes to and
from the 82592 registers). A Reset command is then
issued to the 82592.
4.1.3 INITIALIZING THE BUFFER VARIABLES
The driver must calculate the effective address of the
transmit and receive buffers to use the system DMA.
Since the PC architecture uses a static page register for
the upper address bits, checks must be made to ensure
that the buffers do not cross these hardware imposed
boundaries. This is accomplished through a call to
set_up_buffers. This routine sets up two buffers in
the lO-kB space allocated at load time. One buffer is
used fo~ a transmit buffer and as the parameter block
for commands th!!t require parameters. This buffer is
set up to be at least 1200 bytes long. All remaining
space is used for the receive buffer. The receive buffer is
implemented as a restartable linear buffer. This approach was taken to allow the use of the IPX routine
IPXReceivePacket, which requires the receive packet
to be contained in a single, contiguous buffer. IPXReceivePacket does most of the required receive processing itself which makes the driver simpler.
There are four basic conditions that can exist for the
buffer space with which the driver must work.
• The buffer space has no hardware boundary. See
figure 1.
• The buffer space contains a boundary, and the lower
section is too small to use (i.e., less than the 1200
bytes used for the transmit buffer). See figure 2.
• The buffer space contains a boundary, and the upper
section is too small to use. See figure 3.
• The buffer space contains a boundary, and both sections are usable. See figure 4.
In the first case the transmit and general purpose buffer
will be located in the first 1200 bytes of the buffer
space, and the receive buffer will occupy the remainder
of the space. In the second case the unusable fragment
is discarded by adding the length of the fragment to the
original starting address of the buffer. The total buffer
area is adjusted by subtracting the length of the fragment from the original length (lO-kB) of the original
total buffer area. The transmit buffer uses the first 1200
bytes of the buffer space. In the third case the starting
address remains the same and the total buffer area is
adjusted by subtracting the length of the unusable fragment from the original total buffer area. In these three
cases the required addressing variables can now be calculated. The fourth case adds one additional step. Since
both fragments are usable the larger fragment must be
determined. The receive buffer will be located in the
larger fragment. The receive buffer will be at least 5000
bytes and can be as large as 8800 bytes depending on
where DOS loads the driver.

1-311

infef

AP-327

_'andG~~Buftar

gpJ'",--

apace. 1200 byteS.

B

_Buller

TOIaI buffer space. 1200 bytes

IIuIIorEnd

292062-52

Figure 1. Buffer with No Hardware Boundary

Unusable PortiOn

~ 111M 1200 bytes)

OMA boundary

B

Traromil and General Purpose Buller
space. 1200 bytes.

c
_Buller

Total buner space - (A + B)

._._._. _ _ _ _ _ .... ____

nt.but_Slllp(12OObyteslrom.nd)

IlutIerEnd

292062-54

Figure 2. Buffer with Boundary and Unusable Portion at Top
BuI1er_
T"-'omG~PurposeBuffer
space. 12OObytes.

11'-""'--

B

_Buller

TotaI_r space • (A + C)

DMA boundary

C

Unusable Portion (.... than 1200 bytes)

Buller End

292062-53

Figure 3. Buffer with Boundary and Unusable Section at Bottom

1-312

inter

AP-327

BufferSIart

A
Transmi1 and General Purpose Buffer
space. 1200 bytes.

B
Potential Unusable Portion

DMA boundary

"'_bul_sIart

c
Receive Buffer
Total buffer space - (A -I- B)

-----------------------------------------

",_buLstop (1200 bytes from end)

Buffer End

292062-55

a
BufferSIart

A
Receive Buffer
Total buffer space - (B

-I-

C)

--------------------------------------

",_buLS1OP (1200 bytes from end)

Transmit and General Purpose Buffer
space. 1200 bytes.

C

Potential Unusable Portion
Buffer End

292062-56

b

Figure 4. Buffer with Boundary and Both Portions Usable

1-313

inter

AP-327

Once these initial calculations have been made set_
up_butTers uses this information· to generate the addressing information to be used to program the DMA
control channels and their respective page registers.
Since the 16-bit DMA channels are set up to provide
word moves only, the etTective address ofthe beginning
of the transmit and receive butTers must be shifted right
one place so only AI-AI6 are contained in the variable.
The least significant bit of the page register is not used
by the l6-bit DMA channels because A16 is generated
by the DMA controller. The receive channel requires
an artificial segment to be generated because the latches
contain an etTective address rather than an otTset to the
actual segment the butTer resides in. This artificial segment is used when the received packet is passed up to
IPX. Once the required variables have been initialized,
control is returned to DriverInitialize.
4.1.4 CONFIGURING THE 82592
With the DMA variables initialized, the driver can now
prepare to configure and initialize the 82592 Advanced
CSMA/CD LAN Controller. The transmit DMA
channel is used during configuration to allow the 82592
to read parameters from memory. To put the 82592
into 16-bit mode, the first operation to the 82592 after
reset must be a Configure command with zero in the
byte count of the parameter block. To do this the transmit DMA channel is set up to point to the beginning of
the transmit/general purpose butTer area. This is done
by first resetting the indexing flip-flop in the 8237 A,

and then enabling it by writing 10h to the command
register. This puts the 8237A into rotating priority, late
write, and normal (rather than compressed) timing.
Next the address of the first location of the transmit/
general purpose butTer is written to the 2-byte base address register of the 8237A (low byte first) and the
DMA page register. A "I" is written to the word count
register of the DMA controller. This allows two transfers to be made because the 8237A interprets this register as "transfer count - 1." The channel is then set up to
do the desired type of transfer by writing to the DMA
controller's mode register. Finally, the channel is unmasked by a ~rite to the 8237A mask register. After
moving "O's" into the first two words of the butTer
space, a Configure command is issued to the 82592.
DriverInitialize then enters a polling loop, reading register zero of the 82592 and waiting for the command to
complete. After the command has completed, an Interrupt Acknowledge is'issued to the 82592 to clear the
interrupt generated by the completion of the command.
All transfers that the 82592 makes through DMA will
be l6-bits wide from this point on.
The DMA channel is set up again as previously described; however, the word count is set to eight. This
allows the 82592 to read in its configuration parameters
from the transmit/general-purpose butTer area. The
configuration parameters are copied into the butTer
from the array confi~block by the CPU using a
MOVSB instruction with a REP prefix. CX contains an
18 decimal when the MOVSB is executed. When the

1-314

inter

AP-327

copy is completed a Configure command is issued and a
polling loop is entered to wait for command completion.
The parameters in the configure block set the 82592 to
function in the following manner. The serial mode is set
to high speed to allow Ethernet operation; both the
transmit and receive TCI modes are enabled;and slot
time, minimum frame length, preamble length are set to
the values required by Ethernet. After the command is
completed the generated interrupt is cleared.
4_1.5 SETTING THE STATION'S INDIVIDUAL
ADDRESS

The transmit DMA channel is again set up for use, this
time with a word count of three for use by the Individual Address Setup command. The node address is copied
from its place in memory to the Tx/GP buffer area, and
the IASetup command is issued to the 82592. After the
command is completed the interrupt is cleared by an
Interrupt Acknowledge command.
4.1.6 FINAL INITIALIZATION

The receive DMA channel is now initialized to point to
the beginning of the receive buffer. The word count is
set so the receive DMA cannot go beyond the end of
the assigned receive buffer area.
Next, the interrupt channel is unmasked to allow interrupt driven operation and a Receive Enable command
is issued to the 82592. The AX register is set to zero to
indicate successful completion of the initialization routine and control is returned to IPX. Should some part
of the initialization routine fail, AX would contain a
pointer to a $ terminated error message string in memory. On return of control IPX would display the specified message and terminate.

4_2 DriverSendPacket,
DriverBroadcastPacket
These two routines are treated as a single routine with
two labels at the entry point. The first action taken
when these routines are called is to disable interrupts
through a CLI command. The routine then determines
if any packets are queued for transmission. This is done
by checking the segment portion of the double-word
variable send_list to see if it is null. If it is, no frames
are queued and the packet is put in the first location in
the list. Flow then drops through to the start_send
routine, which does the actual transmission. (The
start_send routine will be detailed later.) If the transmit queue is not empty then DriverSendPacket searches
to the end of the queue and adds the packet there. The
routine then returns control to IPX. The queued packet

will be sent when it is reached in the list. The queue is
maintained as a linked list using a dedicated link field
in the transmit ECBs. The head is the ECB contained·
in the send_list variable and the tail is the ECB with a
null link field.
The start_send routine is a subfunction of DriverSendPacket. It is not called directly by IPX but it can be
called by DriverPoll in response to a transmission timing out when frames are queued for transmission. This
routine starts by clearing the interrupt and direction
flags through a CLI and CLD instruction respectively.
It then retrieves the length of the packet to be transmitted from the transmit ECB packet length field. The
packet length is compared to the minimum length required by Ethernet after a byte swap to allow arithmetic operations to be performed on it. If it requires padding the value is stored in the padding variable.
The byte count for the 82592 is then calculated and the
construction of the frame in the transmit buffer is begun. Since NetWare requires the Ethernet length field
be an even number start_send next increments the
byte count then performs a bitwise AND operation
with FEh. This ensures that the byte count is consistent
with the Ethernet length.
'
The first step in constructing the frame in memory is
to move the transmit byte count into the first word of
the transmit buffer. The byte count is stored low byte
first. The destination address is then copied from the
transmit ECB to the buffer by the CPU using MOVSW
instructions. It is not necessary to copy the source address to the transmit buffer since the 82592 is configured to do automatic source address insertion. After
ensuring that it is an even number, the length is moved
into the Ethernet header. Now the fragment list from
the transmit ECB must be processed. First the fragment count is moved into the AX register. This value
indicates the number of fragments the list contains. By
decrementing AX after each fragment is copied to the
buffer the completion of the fragment processing can be
determined. The address of the first fragment is loaded
into DS;SI, and the length of the fragment is loaded
into ex. The fragment is then copied into the buffer
through a REP MOVSW. If the fragment was an odd
length a MOVSB is done to finish the copy. The pointer
to the fragment descriptor list is indexed to the next
entry. AX is decremented and ifit is not zero the operations above are repeated until all the fragments have
been copied to the buffer. Once the fragment list is
completely processed any required padding is moved
into the buffer. The word following the last location in
the frame must be a zero since the 82592 in TCI mode
checks this location to see if it has a chain of frames to
transmit. A zero is interpreted as end of chain, a 04h is
interpreted as a new transmit command. This driver
does not implement transmit chaining.

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AP-327

The transmit DMA channel is now initialized and
transmit~ctiveJag is set to "I". The DMA address
registers and the page register are set to point to the
beginning of the transmit buffer. The channel mode is
set to move data from memory to the 82592. Four is
added to the transmit byte count that was calculated
earlier to allow the DMA controller to transfer the two
bytes of the byte count field and the transmit chain
word that completes a transmit in Tightly Coupled Interface mode. After this addition the transmit byte
count is shifted right one bit to convert it to a word
count. This value is then moved into the DMA controller's word count registers. Finally, the channel is unmasked.

4.4 DriverlSR
This routine services all interrupts generated by the "
ELM. It first calls IPXStartCriticalSection to tell the
Asynchronous Event Scheduler (AES) function of IPX
'that it should not execute until an IPXEndCriticalSection call is issued. This allows interrupts to be reenabled for sources other than IPX's AES which is executed in response to the system clock tick interrupt. DriverISR then saves the machine state by pushing the
general purpose registers, the index registers, the base
pointer and the ES and DS registers. Next the direction
and interrupt flags are cleared with a CLD and CLI
instruction, respectively. An EOI is then issued to each
of the two system interrupt controllers to clear them.
The DS and ES registers are then set to the same value
as the CS register because the driver is contained in a
single segment. The cause of the interrupt is now determined by reading register "0" in the 82592 .. A zero is
first written to the 82592 to set the internal pointer.
The value read from the 82592 is then compared with
the values representing a receive, transmit, and retransmit interrupt, then a jump is taken to the proper section
of the interrupt service routine. If the value does not
match one of the expected values, the variable false_
590_int is incremented 'and a jump to the label int_
exit is performed.

A Transmit command is now issued to the 82592. IPX
provides a time mark called IPXIntervalMarker that
represents the PC clock tick. The current value of this
variable is read and moved into tlL-start_time to be
used by the DriverPoll routine to check for transmit
timeouts. The TotalTxPacketCount variable is incremented and control is returned to IPX. The 82592 contains a programmable timer that could be used to generate transmit timeouts in an application that does not
have such a built-in mechanism. This routine,must return with interrupts disabled.

4.3 DriverPoll

4.4.1 RECEIVE CASE

DriverPoll is called at intervals by IPX to allow the
driver to check for transmit timeouts or other non-interrupt driven events, that need to be serviced. The first
thing done after disabling interrupts with a CLI is to
check if the transmit_active_flag variable is set. If it
is not set, a return is performed. If it is set, the tx_
start_time variable is subtracted from the current value of IPXIntervalMarker. If the result is less than the
value of TxTimeOutTicks, in this case 20, a return is
performed. If the transmit has timed out the transmission is aborted and a completion code of TransmitHardwareFailure is moved into the completion code
field of the ECB. The ECB is then unlinked from the
transmit queue and returned to IPX through a call to
IPXHoldEvent.
To accommodate errata No. three of the 82592 A-I
stepping, as stated in revision 1.2 (December, 1988) of
the 82592 Errata Sheet,. a Switch to PorU command is
issued to the device. This is followed by a Selective
Reset in Portl, followed by a switch back to PortO. The'
receiver is' then reenabled by a Receive enable command. The flag that indicated an active transmission is
then cleared. The transmit queue is then checked. If the
queue is not empty, the ES:SI register pair is set up
with the values from the queue, and start_send is
called. If the queue is empty control is returned to IPX.

If the value read from the 82592 indicates that a frame
has been received, a jump is made to the beginning of
the code that services receives. The first action is to
read the two latches that contain the address of the last
word that was transferred during the receive. This value is moved into the variables rlL-buf_tail and rx_
buf_ptr. This value is then compared with the value
stored in rlL-buf_stop by the set_up":""buffers routines to determine if most of the receive buffer has been
used and a reset is required. If most of the buffer has
been used the flag reset_rx_buf is set to indicate that
the buffer variables must be initialized before the interrupt service routine is exited. The value read from the
latches is then compared with the value in rlL-buf_
head. This value represents the last location that contains a received frame. If no frames have been received
it contains the address of the first location in the receive
buffer. If this comparison indicates that no new frame
has been received the ten_cent_IatcLcrash variable
is incremented and a jump is made to the label intexit.
If a frame, or frames, has been received the receive
buffer must be processed to allow the received frames
to be sent up to IPX in the order in which they were
received. This is accomplished by using the count and
status information that the 82592 deposits at the end of

1-316

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Ap·327

each frame when it is in TCI mode. Using the value
read from the latches as a base, the routine ProcessFrames indexes back through the chain of received
frames. The rx_buf_ptr variable keeps track of the
current position in the buffer. The status of the frame is
read from the end of the receive buffer and if it is good
a jump is done to the label good_rx. If the status is
bad, rlL.buf_ptr is adjusted to point to the end of the
previous frame in the buffer. This value is compared to
the value of rx_bufJead, which contains the location last processed by the receive routine or the beginning of the receive buffer if this is the first receive. If
the values are equal, all currently received frames have
been processed and a jump is made to the label hand_
off_packet. At the label good_rx three length checks
are made as required by the NetWare implementation
of Ethernet. First the frame is checked to see that is
does not exceed the maximum length of 1102 bytes
(1024 data size, 64 NetWare bytes, and 14 Ethernet
header bytes). Next it is checked to see that it is at least
the minimum size of 30 bytes. This 30 byte value is only
the IPX packet size, it does not count the Ethernet
header or the pad bytes required by Ethernet. The last
check ensures that the actual number of bytes received
agrees with both the Ethernet and IPX header length
fields. If the IPX length is less than the minimum
Ethernet frame length the total number of bytes received is expected to be 60. This represents Ethernet's
64 byte minimum frame length less the four CRC bytes,
which are not counted as receive bytes. If all these
checks pass, the frame is added to the list of received
frames by' storing its location, length, and source address in an array of structures called rx_list. Each entry consists of 12 bytes. These bytes are the location of
the frame in memory, the length of the frame, and the
address of the node that sent the packet.
When all received frames have been processed, all good
frames are passed up to IPXin the order they were received using calls to IPXReceivePacket. When all entries in rx_list have been. processed, the variable rlL.
bufJead is set to the value read from the latches at
the beginning of the interrupt service routine and stored
in rx_buf_tail. ProcessFrames then returns to the
point from which it was called and execution falls
through to int_exit.
4.4.2 TRANSMIT CASE

If the status read from the 82592 indicates that a transmit completion is the cause of the interrupt, a jump is '
performed to the label sent_packet.The first action is
to check that tx_active_flag is set. If it is not set no
transmit should have been taking place, so a jump is
made to the label int_exit., If tx_active_flag was set,
the status is read from the 82592. If the status is bad a
jump is made to tlL.error, which increments the appropriate counter and moves an error code to the AX
register before jumping to the FinishUpTransmit code.

If the status is good any retries contained in the status
register are added to the RetryTxCount variable, the
AX register is XOR'd to indicate a good transmission
and execution falls through to FinishUpTransmit. This
code inserts the proper completion code in the transmit
ECB, unlinks it from the transmit queue, and hands it
off to IPX by calling IPXHoldEvent. The transmit
queue is then checked to see is any frames are waiting.
If send~ist is not empty the next frame's ECB address
is put into the ES:SI register pair and a call is made to
start-send. On return execution jumps to int_exit.
4.4.3 EXITING THE INTERRUPT SERVICE
ROUTINE

At int_exit the driver makes a safety check to ensure
that the receiver is still enabled. This is done by checking the two bits in status register 3. If the receiver is
disabled, a Receive Enable is issued to the 82592. Next,
an Interrupt Acknowledge is issued to the 82592 and
the interrupt bit is polled to see if any new interrupts
have occurred. If a new interrupt has occurred, execution jumps back into the interrupt service routine at the
label int_poILloop. If no new interrupts have occurred, the reset_rlL.buf flag is checked to determine
if the receive buffer needs to be reinitialized. If reinitialization is required, a final check is made to see if any
new frames have been received. If a new frame has been
received ProcessFrames is called. On return the Receive DMA channel is masked and the receiver is disabled by issuing a Receive Disable command to the
82592. It is necessary to disable the receiver during the
reprogramming of the 8237 A because if there is an active request on a channel when it is unmasked the
8237A enters an undefined state which can result in a
system crash. The necessary variables are reinitialized
as well as the receive DMA controller. The receive
DMA channel is then unmasked and the receiver is
reenabled by issuing a Receive Enable command to the
82592. The interrupt enable flag in the processor is then
cleared through a CLI instruction and IPXEndCriticalSection is called to tell IPX that it is now free to run. A
call is made to IPXServiceEvents, and on return the
registers are popped to restore the machine state and
the interrupt service routine is exited.
This covers the main sections of code that make up this
driver. The routines that were not covered in detail are
generic in nature and can be understood by a reading of
the driver source code included as Appendix C.

Section 3. ELM Exerciser Program

5.0 OVERVIEW
The ELM Exerciser software is specifically written for
the Embedded LAN Module Demonstration board but
can accommodate other 82592 TCI (Tightly-Coupled-

1-317

AP-327

Interface) implementatiol)s, with minimal changes. The
~LM Exerciser software supports system and 82592
configuration, command execution and statistics display for the 82592 in the Embedded LAN hardware.

parameter. For the receive FIFO this determines the
number of bytes that may gather in the FIFO, before it requests the bus. The lower the FIFO limit,
the earlier the bus is requested and the 82592 will be
able to overcome a higher bus latency (the time it
takes from request asserted to actual bus transfers).
However, if the bus latency is short, fewer bytes will
be gathered in the FIFO and, before a request is
made. This increases the arbitration overhead per
transfer.
• The OSC RANGE and SMPLG RATE bits are set
to '0' as required in High Speed Mode. (Refer to the
82592 User Manual for more explanations on High
Speed Mode).

This section of the Application Note includes a description of the Exerciser, a discussion 0\1 design considerations for 82592 software drivers and some programming hints.

6.0 INITIALIZATION
System initialization begins with setting up all memory
structures. The 8259A PIC IRQlO is masked, to prevent unsolicited 82592 interrupts before initialization is
completed. Control is then transferred to the user. The
ELM hardware is enabled by a write to I/O Port 303h.
This is d'one using the "LAN En" coml)1and.To activate the 82592, the following sequence should' be executed. This sequence can be executed through the "Initialize" command or by executing each command separately. First the 82592 should be reset. This places the
device in the default configuration. The default bus
width is eight bits. Next a Configur~command is issued
to the 82592 with "0" in the byte count field. This
places the 82592 into 16 bit mode. The 82592 will now
use a 16-bit data bus for DMA transfers. For commands and status" only the low byte is used.

• The CHAINING bit is set to '0'. Together with
RxEOP set to '1' and TxEOP set to 'I', this causes
the 82592 to signal with the EOP# pin for all the
receive frames last byte (BC field)' and collided
transmit frames. The ELM logic uses EOP# with
DRQ lines to determine transmission status and to
latch the pointer to the byte count field into the
ELM latch.
• BUFFER LENGTH/TCI is set to "80h'. Together
with the chaining set to '0', RxEOP set to '1' and
TxEOP set to '1', this puts the 82592 in TCI mode.
In this mode the EOP # and DRQ pins signal the
completion and status of transmit and receive
events. This allows retransmission on collision by
auto initializing the DMA controller as well as reception of back to back frames without CPU intervention. When the device is not configured to TCI
mode, it requires CPU acknowledgement' after each
received frame. In TCI mode the status is stored in
memory, so the 82592 does not need immediate
CPU attention. If this parameter is programmed to
COh, the 82592 will not generate an interrupt upon
frame reception. The ELM Software packages use
this interrupt to invoke the RCV ISR. Note that
'Params3' fields are described in the manual using
decimal numbers. They should be translated into a
Hexadecimal base for programming, e.g. inter frame
spacing of 96 bits is programmed as '60h'.

The ELM Software Package uses the 82592 in a configuration different from the 82592 default configuration.
Whenever a parameter is used that varies from the default, an explanation is given. The 82592 configuration
is presented in code example one. The Configure command is issued through channel 0, which is used for
memory read I/O write cycles. ,
'ByteCnt' is a word-wide field containing the number of
parameter bytes in the CONFIGURE command (excluding the 'ByteCnt' field). The maximum length is 15
bytes. The 82592 will execute 9 DMA word wide transfers (1 for ByteCnt and 8 for parameters) but will ignore the last (the 16th) byte.
The following 'Paramsl' fields are different from the
default:
• The FIFO limit field is set to OFh.This configures
the FIFO's as two equal 32 byte banks for receive
and transmit. For, this configuration, this parameter
is internally multiplied by 2 to generate the actual
FIFO limit. This parameter configures the transmit
side, so transmit FIFO limit equals 2 • OFh = 30.
The receive FIFO limit is then 32 - 30 = 2. This
means that the 82592 will issue a bus request after
the first word has been written into it. Note that this
configuration is provides the maximum bus latency
(Refer to the 82592 User Manual for more detailed
explanation). The system bus request mechanism of
the transmit and receive FIFO's is tuned using this

The 'Params4' Max Retry' field is set by default to
'OFh'. In the case of a frame transmission attempt that
has experienced 15 retries, the NUIIL-Coll status is set
to '0', instead of 16. Namely, the first attempt and 15
retransmissions have collided so the Num_Coll should
be 16. Instead the 82592 will set this field to '0'. This is
further discussed in the transmit section.
The 'Params7' Monitor Interrupt field is set to '1'. This
prevents Monitor interrupts. This bit can remain in its
default state, since the Monitor Mode is, disabled.
The following 'Params8' fields are different from the
default:
'
,

1-318

• 'Params8' CLK divider is not used.

inter

AP-327

CODE EXAMPLE 1

CONF.CONF_Ptr->ByteCnt
CONF.CONF_Ptr->Params1
CONF.CONF_Ptr->Params2
CONF.CONF_Ptr->Params3
CONF. CONF _Pt r- > Params4
CONF. CONF_Ptr->Params5
CONF.CONF_Ptr->Params6
CONF. CONF _Pt r- > Params 7
CONF.CONF_Ptr->Params8

=
=
=
=
=
=
=
=
=

OxOOOF;
Ox804F;
OxOO26;
OxOO60;
OxOOF2 ;
Ox4000;
OxOOFF;
Ox873F;
OxFFFO;

/* 15 BYTES */
/* TCI, Tx FIFO LIMIT = 32 */
/* PREAMBLE LEN =7 */

9.6 uS INTERFRAME, 512 SLOT */

/~'

/* RETRY =15 NO PROMISCUOUS */

/* minimum frame 64 "~I
/* NO AUTO RE-XMT ON COLLISION */
/* NO MONITOR INT */
/~' RX & TX EOP, 32B RX & TX FIFO */

• RxEOP and TxEOP are set to '1' to enable the TCI
signaling as explained above.
• Status length is set to 6 bytes. Together with the
TCI mode configuration, this causes the Frame
Counter to be presented in the STATUS 2_0 register. The 7 LSBs of STATUS 2_0 count the number
of frames received after the Receive Enable command was issued. Both good and bad frames are
counted. The frame counter value is valid when the
MSB of Status 2_0 is set. Comparison of the ISR
frame counter with the number reported by the
frame count contained in Status 2_0 can aid in the
ISR software debug.

7.0 TRANSMIT
Transmission is very simple with the 82592. The data is
stored in memory. The DMA is initialized to point at
the first byte of the data. After the 82592 is given a
Transmit command (code 04h, when using channel
O),it will request DMA data transfers, acquire the link
as soon as the first byte is stored in the internal transmit FIFO and transmit the data. When transmission is
completed, the status field is updated and the INT pin
is asserted. However, if a collision occurs, retransmission is performed external to the 82592 by the ELM
logic. The ELM hardware uses the EOP# signal to
force the 8237 A DMA controller to point to the first
byte of the frame (DMA is in autoinitialize mode). The
82592 issues a data request to the DMA controller and
starts transmission again. This is done without CPU
intervention. The IEEE 802.3 time gap of9.6 uSec for a
retransmit attempt (for the first slot) is easily met. Retransmission is attempted until the internal 82592 maximum retry counter expires. In the ELM example, 15
retries will be attempted. Our laboratory experiments
indicate that most collisions are resolved within less
than 15 retries. In the case of errors the software driver
should intervene.
The 82592 is configured for TCI. This causes the 82592
to use its EOP# pin and thus, enables the external
ELM hardware to detect transmit collision events. The
ELM hardware uses both the EOP# and DRQ lines to
force the DMA to autoinitialize for the retransmissions.

The configuration used in the Exerciser software (TCI
mode) causes the 82592 to search for a command byte
after the last data byte. This byte should always be so
it will be interpreted by the 82592 as a NOP command.
If the least significant 3 bits in this byte are 100 binary,
the 82592 will interpret this byte as a Transmit command and treat the following bytes as the byte count
field of a new frame. The 82592 will then attempt to
transmit it. XMT chaining is not used in the Exerciser
software. The ELM retransmission mechanism uses the
8237A DMA autoinitialize capability. If a chain of
frames is stored in the transmit buffer, there will be no
way to handle automatic retransmission for all the
frames but the first one. There is no way to cause the
8237A DMA controller to jump to the first byte of the
n-th frame, required for a retransmission when chaining is used. However, transmit chaining is possible
when using the 82560/82561 DMA controller.

°

In case of a fatal transmission error, the 82592 will
signal the event to the CPU through the interrupt and
status mechanism. The CPU will issue another Transmit command with the same data (or issue a higher
layer activity when not in the ELM Exerciser software
environment). The CPU will control the number of
times it retransmits the same frame. In case this number exceeds the ELM MAX_RETRY (default = 15.
This is a SW variable, not the 82592 internal max retry
counter) transmission is stopped and the following message is printed on the screen: "ERROR no. 1 ". The
ELM Exerciser software 'MAX_RETRY' default value is 16.
Transmission of an exact number of frames in the range
of 1-32000 or an endless number of frames is
supported. The background transmit command, found
in the EXECUTE menu, communicates with the transmit interrupt service routine (ISR) The XMT_LOOP
flag variable is reset by the background routine immediately before transmission and set by the transmit ISR.
This handshake allows transmission of 1 frame at a
time. The background transmit command polls the
XMT_LOOP flag until it is found to be set. The display is updated periodically. To stop the transmission
loop hit any key on the keyboard.

1-319

AP-327

an endless number of frames, while transmission is performed in parallel and its status stored in this special
internal queue. This optional pending event will be presented in the STATUS register after each CPU interrupt acknowledge sequence. The 82592 will use one receive event to report all the frames received from the
first INT assertion until its acknowledgement. The
82592 will not wait for the CPU to acknowledge the
interrupt; nor will the 82592 generate new interrupts by
toggling its INT pin. New 82592 interrupts for all
events will be generated after the CPU agknowledges
the previous INT request.The CPU can do so by issuing a command to the 82592 with the ACK bit (bit 7),
in the 82592 command byte, ~et.

8.0 INTERRUPT SERVICE ROUTINE
When an execution command has been completed, or a
frame has been received, the 82592 will assert its INT
pin. This is true if the BUFFER LENGTH/TCI parameter of the Configure command was 80h. If programmed to COh, the 82592 will not generate an interrupt upon frame reception. The ELM Exerciser software uses this interrupt to invoke the receive ISR). The
82592 INT pin drives IRQlO of the system bus. IRQlO
is connected to the slave PIC on the motherboard. The
slave PIC output drives one of the master PIC inputs.
If the 82592 INT pin is asserted, the slave .PIC generates (if not masked) an Int signal to the Master PIC
. which transfers (if not masked) the signal to the CPU.
Both PICs have experienced an INT event. This requires that an EOI be issued to both PICs before exiting the ISR.
The 82592 will present the event that caused interrupt
generation in its status register number 0, along with bit
7 set to indicate an unacknowledged interrupt event.
The content of the status registers will not be altered
until the CPU acknowledges the interrupt. When configured to TCI mode, the 82592 will store one more
event in an internal queue. This allows the reception of

At program initiillization, the assembly language procedure "ini_int" is executed. It saves the local environment pointers (private stack and segment registers) and
replaces the current 72h INT Vector in the interrupt
table, with a pointer to the int_hnd routine. The int_
hnd routine is the routine invoked upon any 82592 interrupt. The original 72h interrupt vector, is saved in a
place known to be empty in the DOS interrupt vector
table (62h). The ELM Exerciser software will restore
the original vector before exiting to DOS at the end of
the execution.

CODE EXAMPLE 2

;************************************************************
INI~INT : SET CONDITIONS TO WORK WITH 8259A COMMUNICATION INT
IRQIO IS CONNECTED TO 82592 INT PIN
INT VEC 72h IS JUMP TARGET FOR IRQIOMASKING IRQIO IS DONE
,
AT THE CALLING LEVEL
;************************************************************

push bp
mov bp,sp
jlush es
push bx
.
mov bx, _mstck2
mov cs:lss, bx
mov bx, _mstckl
mov cs:lsp, bx
mov cs:lds, ds
mov cs:les, es
mov al,vec
call sys35
mov al,62h
call sys25
mov al,vec
. mov bx, offset int_hnd
push cs
pop es
call sys25
pop bx
pop es
mov sp,bp
pop bp
ret
_inLint endp

;save local stack segment
;save local stack pointer
;save local data segment
;save local extra 'segment
;hex communication interrupt no.
;es:bx ,hold returned address
;save for later retrieve in vec 62
;hex int no. of irqlO (LAN)
;address of interrupt handler routine
;es-segment of interrupt handler
;install via DOS system call

1-320

intJ

AP-327

The assembly language procedure "int.hnd" is invoked
when the 82592 interrupts the CPU using IRQI0. First
it checks whether this is the first entry of "int.hnd" or
if the interrupt service routine has been reentered while
the previous interrupt was still being processed. The
section on the interrupt service routine discusses interrupt nesting. In the ELM Exerciser Software, 82592
interrupt nesting is prevented. Therefore, the above test
should always return a "no nesting" answer. Then the
host process environment is stored in memory and the
local environment is restored (see the section "Interfacing with DOS"). Next, the machine state is saved by
pushing the general purpose . registers (AX, BX, cx

and OX) and the index registers (SI and 01). The execution until now is considered critical, in the sense that
it should not be interrupted. The processor hardware
prevents any new interrupts of the same level or lower
in priority from interrupting the execution.
The routine "irqlO_mask" masks interrupt request 10
of the 8259A PIC. This is the interrupt generated by
the 82592. This prevents the 82592 from causing nested
interrupts. Now an STI instruction can be issued. This
will enable processing of other interrupts by the processor in a timely fashion. An optional approach is discussed later in the section on interrupt nesting.

CODE EXAMPLE 3

.************************************************************
,

INT_HND: INTERRUPT HANDLER FOR IRQIO (VEC 72)
DEALS WITH THE LOWER LEVEL OF THE TREATMENT, AND CALLS
THE CHANDLER
;************************************************************

inc cs:counter
cmp cs:counter, I
jne inter
first_entl:
mov cs:hsp,sp
mov cs:hss,ss
mov cs:hes,es
mov cs:hds,ds
mov sp,cs:lsp
mov sS,cs:lss
mov dS,cs:lds
mov eS,cs:les
inter:
push bp
mov bp,sp
push ax
push bx
push cx
push dx
push si
push di
call _irqiO_mask
sti
push ax
mov aX,20h
out OAOh,al
mov aX,20h
out 20h,al
pop ax

;saves sS,sp,ds,es only for the first entry

;save registers of host process in memory

;pop local registers from memory

;end of interrupt to 8259A Slave
;end of interrupt to 8259A Master

11:

1-321

inter

AP-327

CODE EXAMPLE 3 (Continued)

exit:
call _parazit_rcv
cli
:enter a critical section must disable int only
:if eoi is before this section
call _irqlO_unmask
,pop di
pop si
pop dx
pop cx
pop bx
pop ax
mov sp,bp
pop bp
dec cs:counter
;nesting check
cmp cs:counter,O
jnz inexit
last:
mov sp,cs:hsp
:pop host registers from memory
mov sS,cs:hss
mov ds,cs:hds
mov es,cs:hes
inexit:
sti
ext_int:
iret
inLhnd endp
Before program control is transferred to the "c" routine "c~ntO" the two 8259A PICs are acknowledged.
The "c_intO" routine reads the 82592 status from the
6 byte status register. To make sure Status byte is the
first byte read and that the following bytes are read in
order, a RLS_PTR (OFh) command, with as a pointer value (points to Status_O), is issued. If no command
is issued to the 592 during the Status read sequence,
each successive read to the 82592 will increment the
internal status pointer and guarantee properly ordered

°

°

status bytes. Now the 82592 Interrupt can be acknowledged. This allows the next event to be presented in the
status register, and the INT pin to be asserted. Since
the PIC is masked all further interrupts from the 82592
will be ignored until the ISR has been exited. The
'INTJROC_Stat' variable holds the interrupt event
presented in STATUS_O. For receive and transmit
events, a lengthy processing is required. It is described
below.

1-322

inter

Ap·327

CODE EXAMPLE 4

far c_int()
(

register a; /* for a faster detection of the INT event */
write_592(OxOF) ;
get_592_status () ;
outp(ADDR_592,Ox80) ;
a = STAT_REG_Stat[O] ;
if (a &: Ox80)

/*
/*
/*
/*
/*

RLS_PTR to 0 command */
IN operation from the 82592 */
acknowledge to 82592 */
Status byte 0 holds the event */
INT bit active */

(

a &:= OxOF;
switch (a)

/* clear irelevant bits */

(

case 8:
INT_PROC_Stat = "RCV-; /* last INT event for screen display */
inLrcv() ;
/* call the RCV ISR */
break;
case 4:
INT_PROC_Stat = "XMTn;
int_xmt() ; /* TRANSMIT event */
break;
case 12:
INT_PROC_Stat = "ReX"; /* Re-TRANSMIT event */
inLxmt() ;
break;
case l:
INT_STAT_RDY = TRUE; /* Individual Address */
INT_PROC_Stat = lilA "; /* executed */
break:
case 2:
INT_STAT_RDY = TRUE: /* Configure executed */
INT_PROC_Stat = "CNF":
break:
case 5:
INT_STAT_RDY'= TRUE: /* TDR executed */
INT_PROC_Stat = "TDR";
break:
case 6:
INT_STAT_RDY = TRUE; /* Dump Executed */
INT_PROC_Stat = nDMpn:
break;

1-323

inter

AP-327

CODE EXAMPLE 4 (Continued)

case 7:
INT_RDY
TRUE; /* Diagnose Passed */
INT_PROC_Stat
nDgP";
break:

=

case 10:
INT_STAT_RDY
INT_PROC_Stat
break;

=

=TRUE; /*
= nRxD";

RCV Aborted */

case 13:
INT_STAT_RDY
INT_PROC_Stat
break;

= TRUE;

/* Execution aborted */

= nExA";

case 15:
INT_STAT_RDY
INT_PROC_Stat
break;

=TRUE;n /*
=DgF ;

default:
INT_STAT_RDY
INT_PROC_Stat
break;

= TRUE;

=• ?

Diagnose Failed */

n:

/* end switch */
I /* end i f */
/* exit interrupt handler */
Before leaving the "intJnd" interrupt service routine,
the 82592 interrupt is unmasked in the 8259A PIC. The
machine state is then restored by popping the registers
pushed on the stack at the entry of the interrupt handier. The nesting control 'counter' variable is decremented and finally the host process environment is restored.
8.1 RCV Interrupt Service Routine: "lnLrcv( )"

The RCV interrupt service routine handles the reception of one or more frames. All the frames received are·
stored in memory in successive addresses by the 8237A
DMA controller. After the 82592 has completed reCeiving a frame it interrupts the CPU. The 82592 will continue to receive frames as long as the DMA continues
to service its requests to store data in memory.

The "int~cv( )" routine implements a cyclic RCV
buffer handling. The buffer size is configurable. The
ELM Exerciser software uses 16 KB, a smaller size can
be used if interrupt latency is small enough. The maximum receive buffer size for this architecture is limited
to 120 kB due to the physical page register implementation of the PC-AT DMA subsystem. In the ELM it is
further limited to 64 kB due to the fact that AO through
A 15 are latched in the TCI latches. If A 1 through A 16
are latched then the full 128 kB that the DMA can
access could be ·used as a receive buffer. To allow maximum buffer size, the ELM Exerciser software locates
its r~eive buffer at the beginning of a physical address
segment, i.e. address of type xxOOOOh, (which of
course is not a must). This allows a simplification in
address calculation because the lowest 16 bits can be
directly used for address calculations: There is no need
to add a displacement from the beginning of the physical address segment.

1-324

inter

Ap·327

The receive ISR starts with the frame received last
(pointed by the latch) and processes received frames,
backwards. The last received frame byte count field is
used to find the byte count field of the next to last
frame. After the pointer to the beginning of the frame
has been reproduced, the received frames can be processed. This goes on until the first frame has been
found. The frames can then be processed in the order in
which they were received.

As seen in figure 5, the 82592 appends the frame's
status and byte count fields, after the last data byte. In
the case of odd frame length (data field in bytes), the
592 will leave one byte empty so the status and byte
count are stored on a word boundary when the 82592 is
set to 16 bit mode.

Throughout the RCV ISR session, the length of the
current frame is being subtracted from the "Cur-Latchabs" variable (pointer to the current frame Byte Count
field), to obtain the previous frame's byte count field.
When the 'Cur-Latch-abs' variable points to the byte
preceding the first byte received in this session of the
ISR, the receive ISR has completed processing all the
frames received in this session.

READING THE LATCH

8.2 Execution Algorithm

The first action taken in the receive ISR is to read the
16-bit latch. It holds the low 16 bit physical address of
the byte count field of frame number N, the last completely received frame (latcLcontent = 470h in the
example of figure I). Note that more than I frame can

D15

DO

~

previous RD_POINTER_abs

DA2

DAI

Rev Start

r"
r"

Frame #1

XXXX
DA2

BC High
DAI

192h

Frame #2

~

XXXX

BC High

-----------

-----------

DA2

DAI

IEBh

r

Frame #N-l

XXXX
DA2

BC High
DAI

)"'"

Latch
D15

F~ame #N

DO

~

30Eh

IJ

Latch_content
Cur_Iatch_c~ntent J
F_Iatch_abs J
Old_latch_content J

xxx x

BC High

470h

Rev End

Figure 5. Memory Organization of RCV Frames

1-325

292062-1

inter

AP-327

be handled by "int_rcvO" in one session. It is not necessarily the very same frame, designated 1, that its reception completion has generated the INT signaUn
this program, the latch is read twice. The latch is read
in two 8 bit accesses since 16-bit I/O is not supported
, so the latch content can be altered in between. As the
DMA can work in parallel with INT processing, it can
capture the bus during the receive ISR latch read operation. If a frame was completed exactly at this time, a
new byte count field pointer. is loaded into the latch.
The second receive ISR read operation will then get
half of the new BC field pointer). If the read operations
yield the same result, the data is valid. In case of mismatch, the read operations are repeated. Latch read
action is very short compared with frame reception, so
there will be no need for more than two iterations. This
can alsobe accomplished by doing a word read at the
low byte of the two latches. Since the ELM does not
return MEMCSI6 the processor will execute two back
. to back byte reads at consecutive I/O locations. These
two reads are locked thus pointer integrity is guaranteed.
FALSE ALARM

A "false alarm" is detected by the fact that the latch
content is equal to its value in the previous service sequence. If the latch was not updated no frame was received since the last receive ISR invocation. If exactly
the butTer size bytes were stored in memory from the
last time a receive was serviced, this test may indicate
wrong results. However, the butTer size should be big
enough to accommodate the longest CPU latency in
servicing interrupts.

BYTE COUNT AND STATUS

The frame length is read from the byte count field (two
words). The general status maintained by the ELM Exerciser software is updated from the status field attached to the end of the frame before the byte count
field. Then the frame q:tay be copied to the user's application receive area. By now one frame has. been received and processed (FRTT_CNT = I).Note that
the byte count field includes the number of the destination address field bytes, source address field bytes, information field (type field included) and two status
bytes. The'Byte Count field itself (four bytes) plus two
bytes of the status field are not included in the calculation. In 16-bit mode, the 82592 extends the status and
byte count fields to words instead of bytes This is treated in more detail in the 82592 User Manual. The previous frame's byte count field has now been located (byte
count + 6) bytes.previous to the current one. See figure
5.
DATA CHECK.

This utility allows checking the received data. The basic assumption is, of course, that the data is known in
advance so we have a reference to compare with. In the
ELM case, the data transmitted is sequential (word
wide), in case the user did not change the default transmission data blocks. This is illustrated in the following
code example.

CODE EXAMPLE 5

/***********************************************

*
*
*
*
*
*

checkS the data words to be sequential data
0,1,2, if data length is longer than 4. *
length
4·data
0000 0000 *
length
5 data
0000 0001 00 *
length
6 data
0000 0001 0000 *
length
7 data
0000 0001 0002 00 *

=
=
=

=

*

=
=
=
=

***********************************************/
/* RD_POINTER_seg.Ptr is pointing to the first byte of the frame
Cur_Latch_abs is pointing to the byte count of the previous frame
Prev_latch_abs is pointing to the byte count of the current frame
*/

1-326

inter

AP-327

CODE EXAMPLE 5 (Continued)

find_boundary (f_byte)
unsigned int f_byte; /* offset of first byte in frame */
(

/* Don't compare last 5 words, 2* BC, 2* STATUS + last word is zero */
if_byte < Prev_Iatch_abs)
return«Prev_1atch_abs - f_byte - 10)/2);
else if(f_byte > Prev_Iatch_abs)
{

H(

(Prev_Iatch_abs - Sixteen_I) > 10)
(

wrap_required = TRUE;
return«RD_END_abs - f_byte)/2);
else

I

return«(RD_END_abs - f_byte)/2) - (10 - (Prev_Iatch_abs Sixteen_I) ) ) ;

I
else

I

RX_CHECK = TRUE; RX_CHECK_DT = Oxa5a5; RX_CHECK_BNUM = Oxa5a5;

I
wrap()
(

wrap_around = TRUE;
bound_dist == find_boundary(Sixteen_1) ;
local.temp.xoffset = Sixteen_I;

I
check_data (f_byte)
unsigned int f_byte; 1* offset of first byte in frame */
(

int i ,j ;
int far * tmp;
unsigned int tmpl, delta, dt1en;
/* reset flags */
wrap_around = wrap_required = FALSE;
/* first find buffer boundary cross point from first DA word if any */
bound_dist = find_boundary(f_byte) ;
/* second find DA and compare to IA */
loca1.tmp = mk_pointer(Prev_latch_abs, -(Cur_Byte_Count + 4»;
if (*(local.tmp++)

!=IASU.IASU_Ptr -- laAdd1)

{

RX_CHECK = TRUE; RX_CHECK_DT =
return;

* (local.tmp)

I
if (bound_dist- __ 0)
wrap() ;

1-327

; RX_CHECK_BNUM = Oxaa1;

intJ

AP-327

CODE EXAMPLE 5 (Continued)

if (*(local.tmp++) 1= IASU.IASU_Ptr -> laAdd2)
{

RX_CHECK = TRUE; RX_CHECK_DT = * (local.tmp) ;,RX_CHECK_BNUM = Oxaa2;
return;

l
if (bound_dist- __ 0)
wrap() ;
i f (*(local.tmp++) I=IASU.IASU_Ptr -> IaAdd3)
{

RX_CHECK
return;

= TRUE; RX_CHECK_DT

= * (local.tmp) ; RX_CHECK_BNUM = Oxaa3;

l
/* second, disregard SA */
if (bound_distwrap() ;
local.tmp ==;
i f (bound_di stwrap() ;
local.tmp ++;
if (bound-distwrap() ;
local.t)llp ==;

--

0)

-- 0)
-- 0)

/* third'check if frame includes data 1= 0 using LEN field */

==

if (bound_dist0)
wrap() ;
if ((dtlen = *(local.tmp++»

== 0)

{

RX_CHECK = TRUE; RX_CHECK_DT = * (local.tmp) ; RX_CHECK_BNUM = Oxaa6;
return;

l
/* if frame includes data 1= 0 compare all bytes till boundary cross */
i

= 0;

if (bound_dist > 0)
[

for (i=O; i SRT_FRM +=' 1;
if (*(tmp_ptr) Be Ox0040)
SCB. SCB_Ptr -> NO_EOF += 1;
if (*(tmp_ptr) Be Ox0020)
SCB.SCB_Ptr -> TOO_LNG += 1;
if (*(tmp_ptr) Be Ox0008)
SCB.SCB_Ptr -> NO_SFD += 1;
if (*(tmp_ptr) Be/Ox0004)
SCB.SCB_Ptr -> NAD_MCH += 1;
if (*(tmp_ptr) Be Ox0002)
SCB. SCB_Ptr -> lA_MCH += 1;
if (*(tmp_ptr) Be Ox0001)
SCB.SCB_Ptr -> RCV_CLD += 1;
tmp_ptr = mk_pointer(Cur_Latch_abs, -4);
if(*(tmp_ptr) Be Ox0020)
{

SCB.SCB_Ptr -> RCV_OK += 1;
UPDATE_RXCNT
TRUE;
}

=

1-330

inter

Ap·327

CODE EXAMPLE 6 (Continued)

if(*(tmp_ptr) & Ox001D)
(

rut-ERR = TRUE;
if (*(tmp_ptr) & Ox0010)
SCB.SCB_Ptr -> LEN_ERR += 1;
if (*(tmp_ptr) &'Ox0008)
SCB.SCB_Ptr -> CRCErrs += 1;
if (*(tmp_ptr) & Ox0004)
SCB.SCB_Ptr -> A1inErrs += 1;
if (*(tmp_ptr) & Ox0001)
SCB.SCB_Ptr -> OvernErrs+= 1;
FRTT_CNT = 1;
/* Frames Received This Time count.Compi1e with DEB_PRT
switch, to monitor number of frames received each int_rcv invocation */
Prev_1atch_abs = Cur_Latch_abs; /* for Data Check */
RD_POINTER_seg.Ptr = mk_pointer(Cur_Latch_abs, -(Cur_Byte_Count + 6));
Cur_Latch_abs = RD_POINTER_seg.Addr.xoffset; /* previous frame BC pointer
308h */
RD_POINTER_seg.Ptr = mk_pointer(Cur_Latch_abs, 2) ; /* frame N 1st byte 310h
*/
tmp = RD_POINTER_seg.Addr.xoffset;
/******* Data Check ********
RD_POINTER_seg.Ptr points to the' first byte of the frame
Cur_Latch_abs points to the byte count of the previous frame */
if (CheckEnab1e == ON)
check_data(tmp) ;
while ((k = more_to_read(tmp)) != 0)

/* MAIN LOOP */

(

cbc_h = * (mk_pointer(Cur_Latch_abs,O));
Cur_Byte_Count = * (mk_pointer(Cur_Latch_abs, -2));
Cur_Byte_Count = (cbc_h ~ 8) + (Cur_Byte_Count & OxOOFF) ;
if ((Cur_Byte_Count % 2) == 1)
Cur_Byte_Count++;
tmp_ptr = mk_pointer(Cur_Latch_abs, -6);
if (*(tmp_ptr) & OxOOEF)
(

rut-ERR = TRUE;
if(*(tmp_ptr) & Ox0080)
SCB.SCB_Ptr -> SRT_FRM += 1;
if(*(tmp_ptr) & Ox0040)
SCB.SCB_Ptr -> NO_EOF += 1;
if(*(tmp_ptr) & Ox0020)
SCB.SCB_Ptr -> TOO_LNG += 1;
1f(*(tmp_ptr.) & Ox0008)
SCB. SCB_Ptr -> NO_SFD += 1;
if(*(tmp_ptr) & Ox0004)
SCB.SCB_Ptr -> NAD_MCH += 1;
if(*(tmp_ptr) & Ox0002)
SCB.SCB_Ptr -> IA_MCH += 1;
if(*(tmp_ptr) & Ox0001)
SCB.SCB_Ptr -> RCV_CLD += 1;

I '

tmp_ptr = mk_pointer(Cur_Latch_abs, -4);

1-331

intJ

AP-327

CODE EXAMPLE 6 (Continued)

if(*(tmp_ptr) & ox0020)
(

SCB.SCB_Ptr -> RCV_OK += 1;
UPDATE_RXCNT = TRUE;

I

if(*(tmp_ptr) & Ox001D)
(

RX_ERR = TRUE;
if (*(tmp_ptr) & Ox0010)
SCB.SCB_Ptr -> LEN_ERR += 1;
if(*(tmp_ptr) & OxOOOB)
SCB.SCB_Ptr -> CRCErrs += 1;
if (*(tmp_ptr) & Ox0004)
SCB.SCB_Ptr -> AlinErrs += 1;
if (*(tmp_ptr) & Ox0001)
SCB.SCB_Ptr -> OvernErrs+= 1;

I
Prev_latch_abs = Cur_Latch_abs;:
/* for Data Check */
RD_POINTER_seg.Ptr = mk_pointer(Cur_Latch_abs, -(Cur_Byte_Count + 6));
Cur_Latch_abs = RD_POINTER_seg.Addr.xoffset;
RD_POINTER_seg.Ptr =.mk_pointer(Cur_Latch_abs, 2);
tmp= RD_POINTER_seg.Addr.xoffset;
/******* Data Check ********
RD_POINTER_seg.Ptr points to the first byte of the frame
Cur_Latch_abs points to the byte count of the previous frame*/
if(CheckEnable == ON)
check_data(tmp) ;
FRTT_CNT++ ;
if (FRTT_CNT >1250)
break;
. /* GUARD BAND * /
I ; /* MAIN LOOP END */
RD_POINTER_seg.Ptr = mk_pointer(F_Latch_abs, 2) ;
RD_POINTER_abs = RD_POINTER_seg.Addr.xoffset; /* next int_rcv session 1st
byte 472h */
RxCount += FRTT_CNT;
copy_data() ;
/* from RCV buffer to user's application *1
INT_STAT_RDY = TRUE;
/* for screen status update */
return;
/* end of int_rcv() */

I
address calculation

In code example 3, the routine "mLpointer(address,
delta)" is used. This routine handles a 16-bit physical
address to pointer conversion (see Code Example 7)
and the buffer internal address calculation (which are
not straightforward).
As noted before, the RCV buffer is a cyclic buffer.
When calculating an address starting from one address
and adding/subtracting some 'delta' value, the buffer
boundaries can be crossed. Overlapping the buffer .

boundaries is further illustrated in Figure number 6.
When subtracting the byte Count of frame N, which
starts in (1) and ends in (2), a direct decrement will not
give the right results. If we calculate backwards and fall
out of the receive area, (address region within which
the buffer for all frames resides) ~'mk-pointerO" adds
the length of the receive area to get the right address. If
we go in the other direction, "mk_pointer" subtracts
the receive area length. Due to receive area alignment
into a physical address segment, the case in which the
address we get is lower than RCV~REA--START
is impossible.

1-332

intJ

AP-327

CODE EXAMPLE 7

/***************************************

*
*

mk_pointer transforms a 16 bit *
abs to a pointer within the RCV_AREA

*

***************************************/
int far *
mk_pointer(abs,delta)
unsigned int abs;
int delta;
(

unsigned int The_length;

=

The_length
(unsigned) DECRCVBLEN; /* buffer length */
RD_POINTER_seg.Addr.xoffset
abs + delta;
if(RD_POINTER_seg.Addr.xoffset > RD_END_abs)

=

{

/* check if going backwards */

(delta <0)
RD_POINTER_seg.Addr.xoffset += The_length;
/* check if going forward */
i f (delta> 0)
RD_POINTER_seg.Addr.xoffset
The_length;

if

-=

1

/* if result is before RCV buffer starts in the segment. */

/* impossible result for aligned RCV_AREA */
return(RD_POINTER_seg.Ptr) ;

Rev Start

c

A

A

c

B

A
Rev End

n
The frames begin at RD_POINTER and end at F_LATCH.

Figure 6. Overlapped Buffer Boundary

1-333

292062-2

intJ

Ap·327

Another address calculation is performed to determine
whether there is "more_to_readO" (see code example
8) i.e., whether.all the frames received this time were
processed and whether the next frame to be read is
valid. Cases of invalidity ate detected by this routine.
This error is denoted "SW_OVERRUN", for software
overrun errors. In case the interrupt handling was too
slow, the DMA could have over written received
frames which were not processed yet. In this case, a
valid byte count field can be replaced by arbitrary data.
This will mislead the backwards address calculation. It
may also cause a detectable address error, where the
previous frame byte count field is located in an area
known to be outside the last valid receive area. The
following variables are used in this calculation:

detect a frame that is wrapped-around the end of the
receive buffer.
RD-POINTER-abs, labeled OLD LATCH in figure 7,
always points to the first byte of the next frame to be
processed in the next "int~cvO" invocation. It is updated at the end of each service cycle; to hold F-latchabs + 2. (Note: 'RD-POINTER-abs' is not equivalent
to 'RD-POINTER-seg.Ptr' ,which serves as a template
for various pointer calculations.)
The following scenarios are possible for such intermediate results.
Legal intermediate results should fall in the "A" area if
the results are in "A", namely between RD-POINTER
(start of this session RCV-AREA) and F-LATCH
(First Latch, end of this session RCV-AREA). Note
that F-LATCH may be greater or smaller than RDPOINTER. See Figure 7A.

Cur-Latch-abs, labeled CUR LATCH in figure 7, is
used to hold the address of the current frame's byte
count in memory, while the ISR processes them. At the
beginning, it holds the last frame's byte coupt (frame
n), then it will hold frame n-I's byte count address and
soon.

If however, the result falls in "B" or "C" areas it is not
legal. This may happen if the buffer was too small and
the 82592 had overrun it in reception. This would occur
if the whole buffer was filled and then more frames
were received, before being processed by the ISR. See
figure 7B.
.

F-latch-abs, labeled NEW LATCH in figure 7, holds
the address of the byte count of the last received frame
(frame N) in this "int~cvO" invocation. It is used to

Rev Start
A

c

c

A
Rev End,

n

][

~ Data received In this session
292062-3

Figure 7a_ Legal "CUR_LATCH" Values

1-334

AP-327

Rev start

C

B

A

Rev End

m

1I

292062-4

Figure 7b. More Frames TO READ

Before Corruption

After Corruption

Frame 1
Frame 2

Frame 2

Frame 3

Frame 3

Frame 4

Frame 4

Frame 5
Start

Frame 5
Start
292062-5

Figure 8. Receive Buffer Corrupted by Overrun

Frame # 5 erases the byte count infonnation stored by
frame # 1. When we calculate our way backwards we
will not find the byte count field of frame # I and read
instead a data word of frame # 5. This data may be
interpreted wrong and cause an avalanche in the frame
reconstruction process. This event can be detected by
the above test.

POINTER (the beginning of the current ReV-AREA)
and prevent write access to areas previously written by
592/DMA and not serviced yet. In case the maximum
delay of the system is detennined and known, one can
allocate a big enough buffer to accommodate that delay
in the ISR. eRe should be stored in memory and
checked by the S/W to assure data integrity.

This can be completely avoided if a stop register is implemented in hardware. This register would hold RD-

1-335

inter

AP-327

CODE EXAMPLE 8

/************************************

* checks whether more frames to *

*

be read as indicated by the latch

*

************************************/
more_to_read{tmp)
unsigned int tmp;
(

unsigned int cur_content, f_content, rd_content;

=
=

cur_content
tmp; /* Cur_Latch_abs [flow chart: cur latch] */
f_content
F_Latch_abs; /* [flow chart: new latch] */
rd_content
RD_POINTER_abs; /* [flow chart: old latch] */
if (f _content > rd_content)

=

(

if{ (cur_content> rd_content) &:&: (cur_content <= f_content))
return{l) ;
if ({cur_content < rd_content)
(cur_content> f_content))
,
(

. SW_OVR++;
RX_ERR
TRUE;

I

=

return{O) ;

I
i f (f_content
(

< rd_content)

if ({cur_content> rd_content)
(cur_content <= f_content))
return{l) ;
if ({cur_content < rd_content) &:&: (cur_content> f_content))
(

SW_OVR++ ;
RX_ERR
TRUE;

I

=

return{O) ;

1-336

inter

AP-327

CODE EXAMPLE 9

far parasite_rcv()
{

int i;
unsigned int

j;

i f ((i=latch_read ())
(

!= 0)

LATCH_ERROR++ ;

return;

I

if((RxCount != 0) && (latch_content != Old_latch_content))
(
PARASITE++ ;

int-rcv() ;

I

Frames may be received during execution of the receive
ISR. These frames are handled before the receive ISR is
exited. This saves the interrupt latency involved and the
context switching overhead. Therefore, it will increase
the overall performance of the code. For all interrupt
events, the "parasite_rcv" routine is invoked, before
exiting the "intJnd" routine (see code examples 9
and 3). The routine "parasite_rcv" checks whether a
frame has been received using the address latch for indication. It compares the current 'latcLcontent' with
the latest value known to this ISR invocation (stored in
'Old-Iatch-content'). Obviously, a different value will
indicate that a new frame has been received from the
time this ISR has been invoked until it is about to be
exited.
In the case of an odd frame length (data field in bytes),
the 592 will leave one byte empty so the status and byte
count are stored on a word boundary (when the 82592
is set to 16 bit mode).
8.3 Transmit Interrupt Service Routine: "inL
xmt{ )"

The transmit ISR is simpler than the receive ISR. It
mainly deals with status update and software generated
retransmissions. First, collision status is checked.
Num_ColI is the number of times this frame has experienced a collision during a transmission attempt.
Num_ColI is equal to, or greater than 0, and smaller
or equal to the configuration parameter Max Retry.
FRM_COLL is an indication generated by the ELM
Exerciser software based on the status reported by the
82592. All the other status reports reflect the 82592
status report, with no further processing. FR~
COLL ,contains the number offrames that have experi-

enced at least one collision. COLL indicates that the
last transmission attempt has experienced a collision;
but, transmission was stopped due to other fatal
events). MAX_COLL indicates that the 82592 has attempted to transmit this frame "Max Retry" times plus
1. All these attempts have experienced collisions.
The events of transmit deference, heartbeat and frame
too long are merely registered and transmission is considered successful. A frame too long error may indicate
a hardware error that caused the 82592 to load an incorrect value into its byte count counter; e.g., 700h was
loaded into the 82592 byte count counter. However,
700h is greater than the maximum allowed length of an
Ethernet frame. This could have happened because of a
hardware or software malfunction.
The events of underrun, lost CRS, lost CTS, late collision or Max-Coll indicate a fatal error with which the
82592 cannot cope. The decision taken here is to retransmit in these cases. However, this decision can be
left for a higher software layer, where such a layer exists.A status report mismatch is fixed for the MA~
COLL status. There is a special case when the 82592 is
configured for 15 retries. After 15 retries it increments
the internal counter to hold (15 + I)MODI6 and hence
NUIIL-Coll holds zero. In this case 16 is added to
Num_CoII. A frame transmission that has been completed successfully still may have suffered from collisions. Hence, this field should be checked even in TX_
OK cases.
Next, the statistics update flag is set ('INTJTAT_
RDY').
The last section of this code handles the counter load
for XMT LOOP cases.

1-337

inter

AP-327

CODE EXAMPLE 10

'****************************
* XMT interrupt service *
'****************************

TxCount++;

,. update XMT frame counter "
,. for all events, do
SCB.SCB_Ptr->Num_COLL += (STATUS.STATUS_Ptr-> Status_l_O & OxOOOF) ;
if( (STATUS.STATUS_Ptr -> Status_LO & OxOOOF)
(STATUS.STATUS_Ptr -> Status_l_O & Ox0020) )
SCB. SCB_Ptr->FRM_COLL++;
if(STATUS.STATUS_Ptr -> Status_Ll & OxOOBO)
SCB.SCB_Ptr->COLL += 1;
status report, only',
if(STATUS.STATUS_Ptr-> Status_l_O & OxOODO)

0,

'0
[

if(STATUS.STATUS_Ptr->Status_l_O
SCB.SCB_Ptr->TX_DEF += 1;
if(STATUS.STATUS_Ptr->Status_l_O
. SCB. SCB_Ptr->HRT_BEAT += 1;
if(STATUS.STATUS_Ptr->Status_LO
SCB.SCB_Ptr->FRTL += 1;
TX_ERR = TRUE;
,. for status

&

OxOOBO)

& Ox0040)
& Ox0010)

display purposes .,

I

r

Fatal errors, ELM Software Package initiates another transmission of

0'

the frame
if! (STATUS.STATUS_Ptr->Status_Ll & OxOOOF)
(STATUS.STATUS_Ptr->Status_LO & Ox0020»
[

if (STATUS. STATUS_Ptr-> Status_Ll & Ox0001)
SCB.SCB.Ptr->UndernErrs+= 1;
if(STATUS.STATUS_Ptr->Status_l_l & Ox0004)
SCB.SCB_Ptr->LOST_CRS+= 1;
if(STATUS.STATUS_Ptr->Status_l_l & Ox0002)
SCB.SCB_Ptr->LOST_CTS+= 1;
if(STATUS.STATUS_Ptr->Status_l_l & OxOOOB)
SCB.SCB_Ptr->LTCOL += 1;
if(STATUS.STATUS_Ptr-> Status_l_O & Ox0020)
[

SCB. SCB_Ptr- > MAX_COLL += 1;
if( !(STATUS.STATUS_Ptr->Status_1_0 & OxOOOF))
SCB.SCB_Ptr->Num_COLL += Ox10;

I

r

FLAG_RE_XMT = TRlJE;
signals Re_XMT. is required .,
INT_STAT_RDY = TRUE;
TX_ERR = TRUE;
" for status display purposes
return;

0'

rI xmt

ok .,
if (STATUS.STATUS_Ptr->Status_l_1 & Ox0020)
(

SCB.SCB_Ptr->TX_OK += 1;
UPDATE_TXCNT = TRUE;
RETRY_CNT = 0;

I

inter

Ap·327

CODE EXAMPLE 10 (Continued)

/ •••••••••• statistics ••••••••••••••• /

=

INT_STAT_RDY
TRUE;
/......... if xmt loop •••••••••••••••• / TermCount - ;
/. reload running counter '/
if«XMT_FOREVER
TRUE) && (TermCount
0))
TermCount
Ox7FFF;
i f (TermCount > 0)
XMT_LOOP
TRUE; /. set condition for next frame transmission, if
transmission in loop is requested ./

=
=

==

==

return;

I

9.0 SOFTWARE DESIGN HINTS
9.1 Segment Boundaries

The PC AT DMA subsystem uses an 8-bit page register
which allows 24 bit addressing. The page register divides the 16 MB memory space into 128KB physical
segments in the 16-bit channels. This is because the
address 0 through 15 generated by the 8237A drive
address I through 16 of the system. in the 16-bit channels the page register is used to generated address 17
through 23. If a buffer is allocated so that it lies in two
physical segments, a special logic should take care of
segment boundary crossing and update the page register. To prevent this complicated logic, memory buffer
allocation should prevent physical segment boundary
crossing.
9.2 Set Pointer

The internal status registers of the 82592 are read in
sequence. One of the ISR operations is reading the
status. One should make sure that the first byte of
status is read first. The background utilities can be interrupted while reading the status. In that case, the internal 82592 status register pointer is not set to O. However, the background software will now get the status
pointer set to 0, while it expected it to be different.
Hence, during status read in the background, the interrupts should be disabled.
9.3 Interfacing with DOS'

The 82592 can interrupt the program at any instant.
Since the ELM Exerciser software is run under the
DOS, the 82592 may interrupt a DOS system call. DOS
saves a small stack for its own use. It does not support
other uses for this stack. Calling routines or passing

parameters by using the DOS stack may cause a stack
overflow error and consequently a system collapse. In
order to prevent this from happening, a private stack
was constructed. Its size is dependent upon the routine
calls within the ISR and upon the stack required for
passing parameters to or from called routines.
9.4 Screen Operations

It is not advisable to use DOS screen operations from
within the ISR.This may cause the system to collapse,
due to DOS not being reentrant. Within the ISR, one
can use a software flag to indicate that data for screen
update is available. In the main program outside the
ISR, DOS services or direct BIOS calls can be made.
9.5 Nested Interrupts

The first check made when interrupt processing starts
is whether this is a nested interrupt. A memory variable
"counter" is incremented every time execution of int_
hnd starts and decremented just before exiting. If
"counter" is greater than I, then this is not the first
entry, it is a nested interrupt. In the code example, the
processing continues at the label "inter." This demonstrates that, since we are using the local environment,
execution has to continue using the current stack pointer and it should not be set to initial value. In this case,
local.environment restoration is skipped.
Another method to prevent interrupt nesting is by not
issuing the "STI" command in the "int_hnd" routine.
This blocks the CPU interrupt input and prevents external interrupt sources from preempting the "int_
hnd" execution. The drawback of this approach is that
it can significantly enlarge the interrupt latency of other devices. These devices may not be designed to cope
with long interrupt latencies.

.1-339

Ap·327

APPENDIX A
LIST OF USEFUL DOCUMENTS
Documents used in the development of the NetWare
driver.
1) Advanced NetWare V2.1 Internetwork Packet Exchange Protocol (IPX) with Asynchronous Event
Scheduler (AES) Revision 1.00. Copyright Novell,
Inc.
'
2) Net Ware V2.1 Driver Specification for Network Inter-

face Cards Copyright Novell, Inc.
3) Advanced Net Ware Theory of Operations Version 2.1
Copyright Novell, Inc.

Other Useful Documents
4) Internet Transport Protocols (Xerox Corporation;
Xerox System Integration Standard; Stamford, Connecticut; December,1981; XSIS-028112)
5) Local Area Network (LAN) Component User's Manual1988 Edition Copyright Intel Corporation
6) AP-320 Using the Intel 82592 to Integrate a Low Cost
Ethernet Solution into a PC Motherboard Copyright
Intel Corporation, 1988
7) 82590-82592 Advanced LAN Controller A-I Step Er, rata version 1.2, December, 1988

1-340

intJ

AP-327

APPENDIX B
ELM EXERCISER FLOWCHARTS
ELM Exerciser Program RCV ISC Flow Chart
START

y

292062-6

1-341

AP-327

ELM Exerciser Program RCV ISC Flow Chart (Continued)

292062-7

ELM Exerciser Program Transmit ISR Flow Chart

UPDATE· TOTAL

# of COLLISIONS

(NUM-COLL)

UPDATE COUNTER:
DEFERRED DURING XMT
HEART BEAT
FRAME TOO LONG

FATAL ERRORS
UNDER RUN
LOST CRS
LOST CTS
LATE COLLISION
MAX COLLISION
UPOATE COUNTERS
SC_T SW RETRANSMIT FLRS
EXIT

SET XMT LOOP

to ALLOW NEXT
FRAME XMT
EXIT
292062-8

1-342

intJ

Ap·327

NetWare Driver Flowcharts
Driver Broadcast Packet
Driver Send Packet

Drop Through

to StarLSend
292062-9

1-343

AP-327

Start Send

Calculate Padding

Calculate Byte Count to
Move Into Tx Buffer Space
Get Destination Address From
ECB to Move Into Buffer
Move ENet Length Field
Into Buffer
Get Fragment Count
Into AX Register
Get Length and Location of
f'lrst Fragment (or Next)
Copy to Tx Buffer
Decrement Fragment Count

292062-10

1-344 -

inter

AP-327

Driver Poll

IPX Hold Event

292062-11

1-345

inter

Ap·327

DriverlSR

292062-12

1·346

inter

Ap·327

rcvd_packet

292062-13

1-347

inter

AP-327

Process Frames

292062-14

1-348

inter

AP-327

Process Frames (Continued)

292062-15

1-349

inter

AP·327

SenLPacket

Put proper completion
code in transmit ECB then
unlink it from send_list
and return It to IPX

No

292062-16

1-350

inter

Ap·327

APPENDIX C
NETWARE DRIVER SOURCE CODE LISTING
NetWare Driver Source Code Listing
$mod186
;********************************************************************

lIt!!! FOR EVALUATION PURPOSES ONLY!!!!!!
NetWare(Rl Driver for the LAN-On-MotherQoard Module
This shell driver is written for use in SYP301 systems.
Joe Oragony

DFG Technical Marketing

REVISION 3.11
Last revision: Date 04-12-89

Time 16:30

;**********************************************************************

'*define(slowl local label
jmp
short 'label
Uabel:

'*define(waitl local label (
mov ex. 03Fh
'label:
nop
loop 'label

'*define(fastcopyl local label (
shr ex, 1
rep movsw

jnc Uabel
movsb

Uabel:

'*define(inc32 ml (
add word ptr tm[Ol. 1
ado word ptr 'm[21. 0
292062-17

1-351

intJ

AP-327

NetWare Driver Source Code Listing (Continued)
name

LANOnMotherboardModule

CGroup

group

assume

Code

Code, mombo_init

cs: CGroup, ds: CGroup

segment word public 'CODE'
public
public
public
public
public
public
public
public

Dri verSendPacket
DriverBroadcastPacket
DriverOpenSocket
DriverCloseSocket
DriverPoll
DriverCancelRequest
DriverDisconnect
SDriverConfiguration

public

LANOptionName

extrn
extrn
extrn
extrn
extrn
extrn
extrn
extrn
extrn
extrn
extrn

IPXGetECB: NEAR
IPXReturnECB: NEAR
-IPXReceivePacket: NEAR
IPXReceivePacketEnabled: NEAR
IPXHoldEvent: NEAR
IPXServiceEvents: NEAR
IPXlntervalMarker: word
MaxPhysPacketSize: -word
ReadWriteCycles: byte
IPXStartCriticalSection: NEAR
IPXEndCriticalSection: NEAR

iii;;;;;;;;;;;;;;;;;

Equates
iii;;;;;;;;;;;;;;;;;

equ 1
TRUE
FALSE
equ
CR
equ ODh
LF
equ OAh
equ OFFh
BAD
BPORT
equ
IRQLOC
equ
DMAOLOC
equ
DMA6LOC
equ
TransmitHardwareFailure
Packet UnDeliverable
equ
PacketOverflow
equ
ECBProcessing
equ
TxTimeOUtTicks
equ

0

19
23
25

equ
OFEh
OFDh
OFAh
20

OFFh

292062-18

1-352

AP-327

NetWare Driver Source Code Listing (Continued)
Latch definitions
TenCentLo
equ 301h
TenCentHi
equ 302h
Enables for lOcent
EnLAN
equ 303h
DisLAN
equ 304h
B259

definitions

InterruptControlPort
InterruptMaskPort
ExtralnterruptControlPort
EOl

equ
equ
equ
equ

020h
OAlh
OACh
020h

:for secondary B259A

8237 definitions
DMAcmdstat
DMAreq
DMAsnglmsk
DMAmode
DMAff
DMAtmpclr
DMAclrmsk
DMAallmsk
DMA6page
DMA6addr
DMA6wdcount
DMA7page
DMA7addr
DMA7wdcount
DMAtx6
DMAtx7
DMArx6
DMArx7
DMA6msk
DMA6unmsk
DMA7msk
DMA7unmsk
DMAena

equ ODOh
equ OD2h
equ OD4h
equ OD6h
equ ODBh
equ ODAh
equ ODCh
equ ODEh
equ OB9h
equ OCBh
equ OCAh
equ OBAh
equ OCCh
equ OCEh
equ OlAh
equ OlBh
equ 006h
equ 007h
equ 006h
equ 002h
equ 007h
equ 003h
equ OlOh

idemand mode, autoinit, read transfer

; demand mode, autoinit, read transfer
;demand mode, no autoinit, write transfer
idemand mode, no autoinit, write transfer

292062-19

1·353

Ap·327

NetWare Driver Source Code Listing (Continued)
82592 Commands
C_NOP
C_SWPl
C_SELRST
C_SWPO
C_IASET
C_CONFIG
C_MCSET
C_TX
C_TDR
C_DUMP
C_DIAG
C_RXENB
C_ALTBUF
C_RXDISB
C_STPRX
C_RETX
C_ABORT
C_RST

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
~_RLSPTR
C_FIXPTR equ
C_INTACK equ

OOh
lOh
OFh
Olh
Olh
02h
03h
04h
05h
16h
01h
18h
09h
lAh
lBh
OCh
ODh
OEh
OFh
lFh
80h

;;\;;;;;;;;;;;;;;;;;;;;;;;;;;; ;

Data Structures

ii;;;;;;;;;;;;;;;;;;;;;;;:;;;;
even
hardware structure

-

io_addrl
io_rangel
io_addr2
decode_range2
mem_addrl
mem_rangel

mem_addr2
mem_range2
int_usedl
int linel
int_used2
int 11ne2
dma_usedl
dma_chanl
dma_used2
dma_chan2

-

hardware_structure

struc

dw
dw
dw
dw
dw
dw
dw
dw
db

?

db
db

db
db
db
db
db

?

ends
292062-20

1-354

intJ

AP-327

NetWare Driver Source Code Listing (Continued)
ecb_structure

struc

dd
0
dd
0
db
completion_code
db
0
socket_number
dw
ipx_workspace
db
transmitting
db
0
driver_workspace
db
11
immediate_address
db
6
dw
fragment_count
fragment_de script or_ list
db
6
ecb_structure
ends
link

esr_address
in_use

fragment_descriptor
fragment_ address
fragment_length
fragment_descriptor

(0)

dup (0)
dup (0)
dup

(1)

struc

dd
dw
ends

rx_buf_structure
struc
rx_dest addr
db
rx_source_addr
db
rX-9hysical_length dw
rx_checksum
dw
rx_length
dw
rx_tran_control
db
rx_hdr_type
db
rx_dest_net
db
rx_dest_node
db
rx_dest socket
dw
rx_source_net
db
rx_source_node
db
rx_source_socket
dw
rx_buf_structure
ends

-

-

tci_status
statusO
deadl
statusl
dead2
bc_lo
dead3
bc_hi
tci_status

dup

dup

(1)

6 dup ( 1)

dup

( 1)

6 dup (1)

dup

( 1)

6 dup (1)

strue

db
db
db
db
db
db
db
ends

1
292062-21

1-355

inter

AP-327

NetWare Driver Source Code Listing (Continued)
ipx_header_structure
struc
checksum
dw
packet_length
dw
transport_control
db
packet_type
db
destination_network db
db
6
destination_node
dw
destination_socket
db
4
source_network
db
6
source_node
dw
source_socket
?
ends
ipx_header_structure

dup
dup

(1)

dup
dup

(1)

(1 )

(1)

;;;;;;;:;:;;:;;;;;;;;;;;;;;

Variables
ii;;;;;:;;;;;;;;;;;;;;;;;:;
even

tx_start_time
adapter_io
con fig
send_list
buffer_segment
rx_ecb

tx_ecb
config_block

dw
dw
dw
dd
dw
dd
dd
db

°
:points to list of ECBs to be sent

°
1

?
?

OFh,OOh,48h,80h,26h,OOh,60h,OOh,OF2h,OOh,OOh,40h,OF7h,OOh,3Fh, 87h,OFOh,OFFh

db
temp_flag
int_mask_register dw
dd
old_irq_vector
dw
int_vector_addr
db
int_mask
db
int_unmask
dw
command_req
dw
read_in_length
db
config_dmaO_loc
db
config_dmill_loc
db
config_irq_loc
dw
config_bport
db
tx_active_flag
frame_status

db

statuslO
statusll
status20
status21

db
db
db
db

o

1

300h

:82592 port

° address

?

°°
°o
o
o
292082-22

1-356

inter

AP-327

NetWare Driver Source Code Listing (Continued)
even

gp_buf_offset
gp_offset_adjust
gp_buf_start
gp_bufyage
tx_byte_cnt
rx_buf_start
rx_bufyage
rx_buf_head
rx_buf_tail
rxJ>uf_ptr
rx_buf_stop
rx_buf_length
rx_buf_segment

curr_rx_length
rx_list
nurn_of_frames
reset_rx_buf
padding

dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw

5000 dup (0)
1388h
cgroup:gp_buf

;twice the required size

o
o

o
o
o
o
o

o
o
o
o
o

;A1-A16 of General Purpose Buffer EA
;A17-A23 of General Purpose Buffer EA
;1PX packet length plus header length
;A1-A16 of General Purpose Buffer EA
;A17-A23 of General Purpose Buffer EA
;current rx head, buffer has been flushed to here
;value read from 10 cent latches
;used during rx list generation
:point to reset the DMA controller'

;calculated at in it for use by IPXReceivePacket

o
180 dup (0)

o

o
o

Define Hardware Configuration
ConfigurationID

db

SDr1verConfiguration

LABEL

reservedl

db
db
db

node_addr
reserved2

node_addr_type
max_data_s1ze
lan_desc_offset
lan_hardware_id
transport_time
reserved_3

major_version
minor_version
flag_bits
selected_configuration
number_of_configs
config_pointers

db

dw
dw
db
dw
db
db
db
db
db
db
dw

'NetWareDriverLAN WS
byte
4 dup (0)
6 dup (0)
a
inon-zero means is a real driver.
o
;address is determined at initialization
1024 ;largest read data request will handle
LANOptionName
OAAh
;Bogus Type Code
1
;transport time
11 dup (0)

Olh ;Bogus version number
OOh

o
;board configuration (interrupts, 10 addresses, etc.)
01
conf1gurationO
292062-23

1-357

inter

AP-327

NetWare Driver Source Code Listing (Continued)
LANOpt ionName'
confiqurationO
db
dw
db
dw
db
db
db
db

db

'Intel LAN-On-Motherboard Module',O,'$'

dw

300h, 16, 0,

a
a, a
a
a , a

;~mory

a

;IO ports and ranges

decode

;~nterrupt level 10
OFFh, 10, 0, 0
;DHA channels 6-and 7
OFFh, 6, OFFh, 7
0,0
'IRQ la, IO Addr - 300h, DHA 6 and 7, For Evaluation Only',

a

;********************************************************

Error Counters

-'.********************************************************
Public DriverDiagnosticTable,DriverDiagnosticText
DriverDiagnosticTable

LABEL

dw
DriverDebugCount
db
DriverVersion
db
StatisticsVersion
dw
TotalTxPacketCount
dw
TotalRxPacketCount
dw
NoECBAvailableCount
dw
PacketTxTooBigCount
PacketTxTooSmallCount
dw
PacketRxOverfloWCount
dw
dw
PacketRxTooBiqCount
dw
PacketRxTooSmallCount
dw
PacketTxMiscErrorCount
PacketRxMiscErrorCount - dw
dw
RetryTxCount
ChecksumErrorCount
dw
HardwareRxMismatchCount dw
NumberOfCustomVariables dw
DriverDebugEndl

LABEL

byte
DriverDebugEnd-DriverDiagnosticTable
01,00

oi,oo
0,0
0,0

a
-1
-1

;not used

;not used

a
a
a
-1

;not used

-1

;not used

a
-1

;not used

a
(DriverDiagnosticText-DriverDebugEndl)/2

byte 292062-24

1-358

AP-327

NetWare Driver Source Code Listing (Continued)
i;i:;;;;;;;;;;;;:;;;;;;;:;;;;;;;;;;;;;;
Driver Specific Error counts

.......................................

""""""""""""""""",,,,,
rx_errors
underruns
no_ets
no_ors
rx_aborts
no_590 int
false_590 int
lost rx
stop_tx
ten cent latch_crash
rX_disb_failure
tx_abort failure
rx_buff_ovflw
tx_timeout

-

-

dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw

0
0
0
0
0
0
0
0
0
0
0
0
0
0

DriverDiagnosticText

db
db

db
db
db
db
db
db
db
db
db
db

LABEL

, RxErrorCount' ,

byte

°

'Underruncount',O
'LostCTSCount',O

'LostCRSCount',O
'RxAbortCount',O

'N0590InterruptCount',0
'False590InterruptCount' ,0
'LostOurRece1vercou~t',O

'QuitTransmittingCount',O
'TencentLatchCrashCount',O

db
db

'RxDisableFailureCount',O
'TxWontAbort',O
'ReceiveBufferOverflow',O
'TxTimeoutErrorCount',O

db

0,0

DriverDebugEnd

LABEL

word
292062-25

1-359

Ap·327

NetWare Driver Source Code Listing (Continued)
;****.*._-*-_.*.* ••• * ••

_*_ .... _... __ .. *.**--**.* ••• ****************

Interrupt Procedure

;_ •. _*.*.*_ •• * •••• *_ .. __ .. *-_ .. *._---*_.*_ ..... _.. *._-**.* .. _* •••• _.
even
~xErrorTypeCheck:

BufferOyerflow:
inc
rx_buff_oYflw
jmp
int_exit

not_590_int:
inc no_590_int
jmp int_exit
OriYerISR
public

PROC
OriYerISR

far

call IPXStartCriticalSection
;tell AES we're busy
pusha
push ds
;save machine state
push es
cld
;read current interrupt mask
in al, InterruptMaskPort
;mask our channel
or al, int_mask
'slow
;write it to the 8259A
out InterruptMaskPort, al
moy a1, EOI
out InterruptContro1Port, a1
;issue E01's to the 8259A's
out ExtralnterruptControlPort, al
;e,nable interrupts to be friendly
sti
mov ax, cs
;OS points to C/OGroup
mov ds, ax
;ES also
mov es, ax
mov dx, command_reg
mov a1, 0
;set status reg to point to reg 0
out dx, al
'slow
in a1, dx
;read status from 82592
test al, 80h
;cheek if the INT bit is set
jz
not_590_int
292062-26

1-360

inter

AP-327

NetWare Driver Source Code Listing
int_poll_loop:
and aI, NOT 20h
mav

ah, a1

cmp

ah, OD8h
rcvdyacket
ah, 84h

jz
cmp
jz
cmp
jz
inc
jrnp

(Continued)

;ignore the EXEC bit
isave the status in AH
;did I receive a frame?
;did

finish a transmit?

ah, aCh
;did I finish a retransmit?
sent-packet_jmp
false_590_int ;unwanted interrupt
int_exit

sent-packet_jmp:
jmp sentyacket
bad_rev:
inc

rx_errors

jmp

RxErrorTypeCheck

int_exit_jmp:
jmp int_exit
;When the address bytes are being read it is possible that another frame
;could come, in and cause a coherency problem with the ten-cent latches.
; I am dealing with this possibility by reading TenCentHi twice and making
;sure the values match. If they don't the read is redone.
rcvd-packet:
eli
mav

dx, TenCentHi ;read high address byte of last frame received

in

aI, dx

mav

ah, a1

;save it in ah

mov
in

dx, TenCentLo ; read low address byte of last frame received
aI, dx
;this is the last location containing rx data
;Read TenCentHi again to make sure it hasn't changed .•.•.••
mov dx, TenCentHi
;read high address byte again
aI, dx
in
;da values match?
cmp aI, ah
;if so, proceed
jz addr_ok
;else, read the latches again
jmp rcvdyacket
addr_ok:
;this is a valid address
mov ax, rx_buf_tail
;this is the last location containing rx data
moV rx_buf_ptr. ax
lis most of the buffer already used?
cmp rx_buf_stop, ax
;if not, proceed
ja BufferOK
;else, set flag for exit routin'e
mov reset- rx_buf. 1
BufferOK:
cmp

ax, rx_huf_head
;have we really received a frame?
ja process_new_frames
; if so, process it
inc ten_cent_latch_crash ;else, increment error count and exit

jmp

int_exit
292062-27

1-361

Ap·327

NetWare Driver Source Code Listing (Continued)
process_new_frames:

call ProcessFrames
int_exit:
push cs
pop ds
cmp 'tx_active_flaq. 0
jnz finish_exit
verify that our receiver is still qoinq.
mov
mov
out
'slow
in
test
jnz
jmp

dx, co~and_req
aI, 60h
:point to status byte 3
dx, a1
:read status byte 3
;check to see if, receiver is enabled
; i f SO, proceed
;else, take eorre~tive action
LostOurReceiver

aI, dx
a1. 60h

intyendinq:
jmp 1nt_po1l_1oop

finish_exit:
cli
mav

mov
out
'slow
xor

out
'slow
in
test
jnz
cmp
jnz
mov
out
mov
in

dx, command_reg

a1. C_INTACK
dx. al

:issue interrupt acknowledqe to the 590

a1, A1

;clear a1

dx. al

;set status req to point to req 0

; read status 0
a1, dx
lis INT bit set1
al. 80h
int-pendinq ;if so. service pendinq interrupt
;do we need to reinitialize receive DMA channe11
reset_rx_buf. 1
no_rx_buf_reset
al, dma7msk
:mask receive DMA channel
DMAsnqlmsk. al
;read hiqh address byte of last frame received
dx. TenCentHi
al, dx
moV ah,. a1
:save it in ah
:read low address byte of last frame received
mov dx. TenCentLo
in a1. dx
;de we have a new frame1
cmp ax. rx_buf_head
jna no_new_frames
;this is the last location containinq rx data
'mov rx_buf_tail. ax
:set pointer for use durinq buffer processinq
mov rx_buf-ptr. ax
call ProcessFrames
292062-28

1-362

AP-327

NetWare Driver Source Code Listing (Continued)
no_new_frames:
mov dx. command_reg
;issue rx disable to kill any active requests
mov al. C_RXDISB
out dx. al
mov al. C_SWP1
out dx. al
mov al. C_SELRST
out dx. al
'slow
mov al. C_SWPO
out dx. al
out DMAff. al
;data is don·t care
mov ax. rx_buf_start
;set dma up to point to the beginning of rx bUf
mov rx_buf_head. ax
shl rx_buf_head. 1
out DMA7addr. a1
mov al. ah
'slow
out DMA7addr. al
mov al. DHArx7
'slow
;set proper mode for receive
out DMAmode. a1
mov ax. rX_buf_1ength ;set up rx buf

'slow
out

mav
'slow
out
mov
mov
'blow
out
mav
mov
out
mov

DMA7wdcount, al

a1, ah

DMA7wdcQunt. al
dx. DMAsnglmsk
al. DMA7unmsk
dx. al
dx, command_req
al. C_RXENB
dx. al
reset_rx_buf. 0

;make sure receiver is enabled
;clear the flag

no_rx_buf_reset:
eli
call IPXEndCriticalSection
in al. InterruptMaskPort
and al. int_unmask
'slow
out InterruptMaskPort. al
pop eB
pop dB
papa
sti

iret
292062-29

1-363

AP-327

NetWare Driver Source Code Listing (Continued)
LostOUrReceiver:
inc lost rx
mov al, C_RXENB
mov dx, command_reg
out dx, al
jmp finish_exit
too_big:
inc PacketRxOverflowCount
jmp int_exit
sentJlacket:
eli
cmp tx_&ctive_flag, 0
jz
false_tx_int
;shouldn't have been transmitting
in
al, dx
mov statuslO, al
'slow
in
al, dx
mov statusll, al
test statusll, 20h
jz
tx_error
mov al, statuslO
;extract the total number of retries from
and ax, OFh
;the status register and add to retry count
add RetryTxCount, ax
xor ax, ax
;status - 0, good transmit
FinishUpTransmit:
les si, send_list
cmp es: [sil.transmitting, TRUE
jnz ecb_cancelled

;if the transmitting flag is not set
;then an ECB has been cancelled and

moves: [sil.completion_code, al
mo~

mov
mov
mov

ax, es: word ptr [sil.link
~ord ptr send_list, ax
ax, es: word ptr [sil.link + 2
word ptr send~list + 2, ax

mav

es: [si] . in_use .. 0

;this is a fresh one

;,finish the transmit

call IPXHoldEvent
ecb_caneelled:
push cs
pop ds
mov ex, word ptr send_list + 2
mov tx_aetive_flag, c1
jcxz int_exit_jmpl
;segment of next SCB in list
mov es, ex
;offset of next SCB in list
mav si, word ptr send_ list
call start_send
jmp f~nish_exit
int_exit_jmpl:
jmp int_exit
292062-30

1-364

inter.

AP-327

NetWare Driver Source Code Listing (Continued)
false_tx_int:
jmp int_exit
tx_error:
;Max collisions??
test statuslO. 20h
jnz QuitTransmittinq
;Tx underrun1?
test statusll. Olh
lost_cts
jz
inc underruns
lost_cts:
;did we lose clear to send??
test statusll. 02h
jz
lost_crs
inc no_cts
lost_crs:
;did we lose carrier sense??
test statusll. 04h
jz
hmmm
inc no_era
hmmm:
mov al. TransmitHardwareFailure
jmp FinishUpTransmit
QUitTransmittinq:
mov al. statuslO
and ax. OFh
add RetryTxCount,. ax
inc stop_tx
mov al. TransmitHardwareFailure
jmp FinishUpTransmit
DriverISR

endp

ProcessFrames:

a routine to process received frames and hand them
off to IPX

Assumes: rx_buf_tail and rx_bufytr have been set up with the value
read from the ten cent latches.
Returns: nothinq
292062-31

1-365

inter

Ap·327

NetWare Driver Source Code Listing (Continued)
ProcessFrames

proc

near

do_next_frame:

sti
mov
sub

bx, rx_buf-ptr
bx, 6

maves, rx_buf_se9ment

lend of current frame to process

;set bx up to point to beginning of the status
;this is necessary because latches hold EA not

;offset relative to CGROUP
mov al, es:[bxl.status1
test al,20h
;test for good receive
jnz good rx
inc

rx_errors

mov c1, es: [bxJ.bc_10
;cx has actual number of bytes read
mov ch, es: fbxJ.bc_hi
; toss byte count , status
dec cx
; round up
and cl, Ofeh
;bx points to first location of frame
sub bx, cx
cmp rx_buf_head, bx
hand_off-yacket_jmp ; this was the first frame in the sequence
je
cmp rx_buf_head, bx
;this frame is a fragment in the beginning of
ja check_rx_queue
;the receive buffer
mov rx_bufytr, bx
sub rx_buf-ytr, 2
to_do_next_frame:

jmp do_next_frame
hand_off-packet_jmp:
jmp hand_off-packet ~~
check_rx_queue:

cmp

num_of_frames, 0

;have any frames been processed?

jne
jmp

hand_off-yacket_jmp
process exit

;if yes, give them to IPX
;if not, go back to ISR

good rx:
mov cl, es:[bxJ.bc_lo
mov ch, es:[bxJ.bc_hi
mav
dec

curr_rx_lenqth, ',ex
ex

and

cl, Ofeh

sub

bx, ex

cmp rx_buf_head, bx
ja check_rx_queue
mov rx_buf-ptr, bx
sub rx_buf-ytr, 2
sub

ex, 14

cmp
jbe
inc
jmp

cx, 1024 + 64
not_too_big
PacketRxTooBigCount
do_next_fram,e

;cx has actual number of bytes read
;toss byte count , status
;round up

;bx'points to first location of frame

;rx_buf_ptr = last location of n-l frame
;sub length of 903.2 header

not_too_big:

cmp

ex, 30

jae
inc

not too_small
PacketRxTooSmallCount
292062-32

1-366

inter.

AP-327

NetWare Driver Source Code Listing (Continued)
not._t.oo_srnall:
mov ax, es:[bxl.rx_length
xchg aI, ah
inc

and
xchg
cmp
jne
xchg
cmp
ja
rnov
len_ok:
cmp
jz

inc
jrnp

get· IPX length

ax

al. Cfeh
al. ah
same as 802.3 length
ax. es:[bxl.rx-Fhysical_length
to_do_next_frarne
al. ah
;at least min length minus header
14
ax. 60
;yes, continue
len_ok
;no, round up
ax. 60 - 14
;match physical length

ax, ex
not_inconsistent

;yes, continue

HardwareRxMisrnatchCount

do_next_frame
not_inconsistent:

\inc32

TotalRxPacketCount

Double Word Increment

mav

ax, 12

mul
mov
add

nurn_of_frames
di, ax
rx_Iist [dil. bx
rx_list [dil. 14

mav

ax, rx_buf_segment

rnov
mov
xchg
mov
mov

rx_list [di + 21. ax
ax. word ptr es:[bxl.rx_length
al. ah
rX_Iist. [di + 41. ax
ax. word ptr es:[bx).rx_source_addr + 0

mav

rx_~i5t

;first location of ethernet frame
;first location of ipx packet

[di + 6], ax

mav

word ptr

mov

ax, word ptr es:[bx).rx_source_addr + 2

mov

word pt.r rx_list [di + 81. ax

moV

ax, word ptr es:[bx).rx_source_addr +

rnov
add

word ptr rx_list [di + 101. ax
nurn_of_frames. 1

cmp

nurn_of_frames, 50

je
cmp
je
jrnp

hand_off-Facket.
rx_buf_head. bx
hand_off_packet.
do_next_frame

;prevent list overflow

292062-33

1-367

AP-327

NetWare Driver Source Code Listing (Continued)
hand_off-packet:
;offset in receive buffer space
mov si, rx_list[dl]
moves, rx_list[di + 2] :receive buffer bogus segment
mov cx, rx_list[di + 4] ;IPX packet length
lea bx, rx_list[di + 6] ;pointer to immediate address
cli
push ds
call IPXReceivePacketEnabled ;since packet is contiguous let IPX do
;the work
pop ds
;decrement count
sub nurn_of_frames, 1
;if all frames are processed adjust head
jz adjust_rx_head
sub di, 12
jmp hand_off_packet
adjust_rx...:head:
mav

add
mav

ax, rx_buf_tail
ax, 2
rx_buf_head, ax

process_exit :
ret
ProcessFrames

;otherwise index to next list entry
;and loop to process next frame
:location of last location used in receive
:index to next word location
;set rx_buf_head to new value for next receive

; interrupt
endp

Driver Send Packet
Driver Broadcast Packet
Assumes

ES:SI points to a fully prepared Event Control Block
OS = CS
Interrupts are DISABLED but may be reenabled temporarily if necessary
don't need to save any registers
DriverBroadcastPacket:

NEAR
PROC
DriverSendPacket
; disable the interrupts
cli
moves: [siJ,transmitting, FALSE ;make sure the flag is initially clear
mov cx, word ptr send_list + 2
lit will be used later to prevent a
jcxz AddToFrontOfList
;cancelled ECB from being given to IPX twice
;search to. the end of the list, and add there.
mov di, word ptr send_list
AddToListLoop:
mav ds, ex
mov cx, ds: word ptr [diJ.link + 2
jcxz AddListEndFound
mov di, ds: word ptr [di].link
jmp AddToListLoop
292062-34

1-368

inter

AP-327

NetWare Driver Source Code Listing
AddListEndFound:
mov es: word
mov es: word
mov ds: word
mov ds: word
mov ax, es
mov ds, ax
ret

ptr
ptr
ptr
ptr

lsi] • link. ex
lsi] • link + 2, ex
[di] .link, si
[di].link + 2, es

(Continued)

imove null pointer to newest SCB's
:link field

iset ds back to entry condition

AddToFrontOfList:
mov es:word ptr[si].link, cx
mov es:word ptr[si].link + 2, cx
mov word ptr send_list, 51
mav word ptr send_list + 2, es
;drop through to Start Send
DriverSendPacket

endp

Start Send
assumes:

points to the ECB to be sent.
ES: SI
interrupts are disabled

PRoe

start_send

public
cli
cld
mav

NEAR

start_send

; disable the interrupts
es:

[s1] .transmitting, TRUE

;save SCB address in variable tx_ecb to liberate registers
mav

mav
push
;get IPX
Ids
mov
pop
push
xchg
add

mov
cmp
ja
mov
sub
mov

word ptr tx_ecb, 81

word ptr tx_ecb + 2, es
ds
;save ds for future use
packet length out of the first fragment (IPX header)
bx, es: dword ptr [si].fragment_descriptor_list
ax, ds: [bx].packet_length
ds
:restore ds to CGROUP
ax
;save length for later use in 590 length field
al, ah
;byte swap for 592 length field calculation
lB
;add in the overhead bytes DA,SA,CRC,length
ax"

padding, 0
ax, 64
long_enough
padding, 64
padding, ax
ax, 64

:minimum length frame

;pad length
292062-35

1-369

inter

AP-327

NetWare Driver Source Code Listing (Continued)
long_enough:
sub ax, 10
inc ax
and aI, OFEh

iSA and eRe are done automatically

mev

;frame must be even
tx_byte_cnt, ax

mov

di,gp_buf_offset

mav bx, os
maves, bx

;move the byte count into the transmit buffer
stosw
imove the destination address from the tx ECB to the tx buffer

mav bx, si
lea si, [bxJ. immediate_address
mav ds,word ptr tx_ecb + 2
movsw
movsw

movsw
mav
mav

get back to the code (Dgroup) section

ax,es
ds,ax

;now the 590
pop ax
xchg ah,
inc ax
and al,
xchg ah,
stosw
Ids si,
mov ax,
lea bx,

length fieid
al
;make sure E-Net length field is even

OFEh
al
tx_ecb

ds: [5i] . fragment_count
[siJ.fragment_deseript'or_list

move_frag_loop:
push ds

; save the segment

mov ex, ds:· [bxJ • fragment_length
Ids si, ds: [bxJ.fragment_address
%fasteopy
; get the segment back
pop ds
add bx, 6
dec

ax

jnz

move_frag_loop

;start transmitting
mav ex, cs
mav ds, ex

;add any required padding
mav

ex, 4

add

ex, padding

;make sure frame ends with a NOP

shr

ex, 1

rep

stDSW

mav
xor
out

tx_active_flag,
ax, ax

DMAff, al

mav

ax, 9P_buf_start

;data is don't care, AX has been zeroed

'slow

out

DMA6addr, al
292062-36

1-370

inter

AP-327

NetWare Driver Source Code Listing (Continued)
mav

tslow
out
mov
tslow
out
'slow
mov
out
maV

add
shr
adc
out
'slow
mov
out
'slow
mov
out

aI, ah

DMA6addr, al
ax, gp_buf-page
DMA6page. al
al. DMAtx6
DMAmode, a1

;DMA page value

;setup channell for tx mode

ax, tx_byte_cnt

ax, 4

;add two for byte count, two for tx chain fetch
;convert to word value and account for odd
;byte DMA transfer
DMA6wdcount, al
ax, 1
ax, 0

al. ah
DMA6wdcount. al
al. DMA6unmsk
DMAsnglmsk. al

maV

dx, command_reg

mov
out

al. C_TX
dx. a1

mev

ax, IPXlntervalMarker

mav

tx_start_time, ax

'inc32
ret
start_send

TotalTxPacketCount

Iget a fix on the time that transmission
istarted and save it for later' use ,

;increment counter

endp

DriverOpenSacket:
DriverDisconnect:
ret
292062-37

1-371

inter

AP-327

NetWare Driver Source Code Listing (Continued)
i*****************************************************

--------_._----**

Driverpoll
Poll the driver to see if there is anything to do
Is there a transmit timeout? If so, abort transmission and return
ECB with bad completion code. Check to see if frames are queued.
I f they are set up ES:SI. and call DriverSendPacket.
i*****************************************************

--_._----_.*----*

DriverPoll
PROC
NEAR
cmp tx_active _flag, 0
jz
NotWaitingOnTx
mov dx, IPXlntervalMarker
sub dx, tx_ start_time
cmp dx, TxTimeOUtTicks
jb
NotTimedOutYet
This'transmit is taking too long so let's terminate it now
Issue an abort to the 82592
mav

dx, command_reg

mov aI, C_ABORT
; abort transmit
out dx, al
inc tx_timeout
les si, tx_ecb
moves: [sil.completion_code, PacketUnDeliverable
mov ax, es: word ptr [sil.link
mav

word ptr send_list, ax

mov
mov

ax, es: word ptr [sil.link + 2
word ptr send_list + 2, ax

;stuff completion code of a failed tx

Finish the transmit
mov e~: [sil.in_use, 0
call IPXHoldEvent
292062-38

1-372

Ap·327

NetWare Driver Source Code Listing (Continued)
;make sure that execution unit didn't lock up because of abort errata

mov
mov
out
hait
mov
out
'wait
mov
out
'wait
mov
out
mov

dx, command_reg
al, C_SIIPl
dx, al
al, C_SELRST
dx, al
aI, C_SIIPO
dx, al
aI, C_RXENB
dx, al
tx_aetive_flaq, 0

;See if any frames are queued

mov ex, word ptr
jexz queue_empty
mov es, ex
mav' ai, word ptr
call start_send
queue_empty:

NotWaitinqOnTx:
NotTimedOutYet:
ret
DriverPoll

endp
292062-39

1-373

intJ

Ap·327

NetWare Driver Source Code Listing (Continued)

Driver Cancel Request

Assumes on entry:
ES:SI is.pointer to ECB· we want to cancel
OS is setup
Interrupts are DISABLED

Assumes any registers may be destroyed.
Returns completion code in AL:
00
Buffer was located and canceled.
FF
Buffer was not found to be in use by the driver

DriverCancelRequest

PROC

NEAR

;first, see 1f it is the one we are currently sending_

mav
dx, es
word ptr send_list. si
cmp
NotFirstOne
jnz
word ptr send_list + 2, dx
cmp
NotFirstOne
jnz
;we need to cance'l the first entry. first, unlink i t
;from the send list.
ax, es: word ptr [sil.link
moV
word ptr send_list, ax
mov
cx, es: word ptr [sil.link + 2
mov
word ptr send_list + 2, cx
mov
es: [sil.completion_code, OFch
mov
es: [si]. in_use, 0
mov
ax, ax
xor
ret
;we need to search down the send list

NotFirstOne:
mov
cx, word ptr send_list + 2
mov
di, word ptr send_list
ScanTheSendListLoop:
jcxz
NotFound
;move to the next link
es, cx
mov
bx, di
mov
cx, es: word ptr (bx].link + 2
mov
di, es: word ptr (bxl.link
mov
;next node is pointed to by CX:DI
iprevious node is pointed to by ES:BX
isee if we found it
cmp

dl, 5i

jnz

ScanTheSendListLoop

cmp

ex, dx

jnz

ScanTheSendListLoop
292062-40

1-374

inter

Ap·327

NetWare Driver Source Code Listing (Continued)
;we found it. now unlink it.
. push
ds
ds, cx
mov
mov
mov
mov
mov
mov
mov
pop
xor
ret
NotFound:
mov

ax, ds: word ptr [sil.link
es: word ptr [bxl.link, ax

ax, ds: word ptr [sil.link + 2
es: word ptr [bxl . link + 2, ax
ds: [sil .completion_code, O.FCh
ds: [sil.in_use, 0
ds
ax, ax

aI, OFFh

ret
DriverCancelRequest

endp

Driver Close Socket
Assumes on entry:
OX has socket number

OS is setup
Interrupts are DISABLED
Assumes any registers may be destroyed.

DriverCloseSocket PROC NE~
mov
cx, word ptr send_list + 2
jcxz
les

DriverCloseExit
si, send_list

DriverCloseLoop:
cmp
es: [sil.socket_number, dx
jnz
push
call
pop
jmp

DriverToNext
dx·
DriverCancelRequest
. dx
OriverCloseSocket

DriverToNext:
moV
cx, es: word ptr [sil.link + 2

jcxz
les
jmp

DriverCloseExit
si, es: [sil.link
OriverCloseLoop
292062-41

1-375

Ap·327

NetWare Driver Source Code Listing (Continued)
DriverCloseExit:
ret
DriverClosesocket
Code

endp

ends

segment 'CODE'
DriverInitialize, DriverUnHook
db CR,LF,'No adapter installed in PC$'
db CR,LF, 'Configuration Failure$'
config_failure_message
CR,LF,'IA Setup Failure$'
db CR,L~,'configuration underrun$'
ConfigDataUnderrunMess
public

no_card_message

Driver Initialize
assumes:

OS, ES are set to CGroup (== CS)
DI points to where to stuff node address
Interrupts are ENABLED
The Real Time Ticks variable is being set, and the
entire AES system is 'initialized.
returns:

If initialization is done OK:
AX has a 0
If board malfunction:
AX gets offset (in CGroup) of '$'-terminated error string

NEAR
DriverInitialize PROC
mov
MaxPhysPacketSize, 1024
eli

cld
mav
mov
mev

ax, cs
ds, ax'

es, ax

;get DOS time and use for address.
mov
ah,02Ch
int
21h
mov
bx,. OFFSET CGroup: node_addr
moV
byte ptr cgroup:[bxl, OOh
moV
byte ptr cgroup:[bx+1], OAAh
byte ptr cgroup: [bx+2]. ch
mev
byte ptr cgroup: [bx+3], dl
mov
byte ptr cgroup: [bx+4] , dh
moV
byte ptr cgroup: [bx+S], 7Eh
moV
si, bx
mov
292062-42

1·376

AP-327

NetWare Driver Source Code Listing (Continued)
;stuff address at point IPX indicated

movsw
movsw

movsw
sti
;initialize the configuration table
mav

al,selected_configuration

cbw
shl
add
mov
mov

; multiply by two
ax,l
:ax contains the offset value
ax,OFFSET CGROUP:config_pointers
;of the default configuration
bx,ax
;list
bx, [bxj

mav

Confiq,bx

mov
mov
mov

aI, [bx+DMAOLOCj
config_dmaO_loc,al
aI, '[bx+DMA6LOC)

mov
mov

config_dmal_loc,al
aI, [bx+IRQLOC)

mav

confi9_irq_loc,al

mov
mov

ax, [bx+BPORT)
command_reg, 300h

Set The Interrupt Vector:
SET UP THE INTERRUPT VECTORS
push
mov
mov
call

di
aI, config_ir'Lloc
bx, OFFSET CGroup: DriverISR
Set Interrupt Vector

pop
mov
out

di
dx, EnLAN
dx, al

'slow
mov
mov
out

;enable LAN on MB module

dx, command_req
aI, C_RST
dx, al

;

reset the 82592 controller

;generate 20 bit address for DMA controller from configure block location
;this is necessary to accomodate the page register used in the PC DMA

;set up OMA channel for configure command

xor
out

ax, ax
DMAff, al

:data 1s don't care

%slow
mav

aI, DMAena

out
mav

DMAcmdstat, al
ax, 9P_buf_start

%slow
out
mov

DMA6addr, al
aI, ah

292062-43

1-377

intJ

AP-327

NetWare Driver Source Code Listing

(Continued)

'slow
out

mov
\slow
out
mav
hlow
out
mov
blow
out
mov

DMA6addr, al

ax, gp_buf-page
DMA6page, al
ax, 1
DMA6wdcount, al

;DMA page value

;make two transfers

aI, ah
DMA6wdcount, al
aI, DMAtx6

isetup channel 6 for tx mode

'slow
out

mav
'slow
out
xor
mov
stosw
stoaw
blow
mov
mov
out

DMAmode, al

aI, OMA6unmsk
DMAsnglmsk, al
ax, ax
di, gp_buf_offset ;mov zeroes into the byte count field of the
;buffer to put the 82592 into 16 bit mode

dx, command_reg
al, C_CONFIG
dx, a1

;configure the 82592 for 16 bit mode
; i'ssue configure command

'slow
wide_mode_wait_loop:
xor
a1, a1
'slow
dx, al
out
'slow
in
and
cmp
jz
loop
mov
jmp
do_config:
mov
out
xor
hlow
out
mav

%slow
out
mav

hlow
out
mov

IPoint to register 0

al, dx
; read register 0
;disregard exec bit
al,ODFh
aI, 82h
; is configure finished?
do_config
wide_mode_wait_loop
ax, OFFSET CGroup: no_card_message
init_exit

al, C_INTACK
dx, al
ax, ax
DMAff, al

;clear interrupt

;data is don't care

ax, 9P_buf_start

DMA6addr, al
al, ah

DMA6addr, al
ax, gp_buf-page
292062-44

1·378

AP-327

NetWare Driver Source Code Listing (Continued)
'slow

out
%slow
mov
out
%slow
mav
out
hlow
mav
out
%slow
mav
out
mav

DMA6page, al

iDMA

page value

isetup channell for tx mode

aI, DMAtx6
DMAmode, al
ax, B
DMA6wdcount, al
aI, ah
DMA6wdcount, al

al, DMA6unmsk
DMAsnglmsk, al
ax, ds

maves, ax

mov
mov
mav
rep movsb
mov
mov
out
hlow
xor

si, offset cgroup:config_block
di, gp_buf_offset
ex, 18
dx, command_reg
aI, C_CONFIG
dx, al

configure the 82592

cx, cx

config_wait_loop:
%slow
xor
aI, al
, 'slow
out
, %slow
in
and
cmp
jz
loop
mov
jmp

dx, al

;point to register 0

al, dx
;read register 0
al, ODFh
;discard extraneous bits
aI, 82h
; is configure finished?
can fig_done
config_wait_loop
ax, OFFSET CGroup: config_failure_message
init_exit

config_done:
;clear interrupt caused by configuration
mov
aI, C_INTACK
out
dx, al
;da an lA_setup
mov
di, gp_buf_offset
mov
aI, 06h
;address byte count
stasb
mov
aI, OOh
stosb
mov
si, OFFSET CGROUP:node_addr
ex, SIZE node_addr
mov
rep movsb

292062-45

1-379

intJ

Ap·327

NetWare Driver Source Code Listing (Continued)
out
hlow
mav

out
mav
hlow
out
mciv
'slow
but
'slow
mov
out
'slow

;data is don't care

DHAff, al
ax, gp_buf_start

DHA6addr, al
aI, ah
DHA6addr, al
ax, qp_buf.Jlaqe
;DMA paqe value

DMA6paqe, al

;setup channell for tx mode

aI, DMAtx6
DMAmode, al

mav

ax, 3

out

DMA6wdcount, al

'slow
mov
out
hlow
mov
out

mav
mov
out
xor

aI, ah
DMA6wdcount, al
aI, DHA6unmsk
DHAsnqlmsk, al
dx, conunand_reg
;set up the 82592 individual address
aI, C_IASET
dx, al
cx, cx
;cx is used by the loop instruction below. this
;causes the loop to be executed 64k times max

ia_wait_loop,
xor
aI, a1
out
dx, a1
'blow
aI, dx
in
aI, ODFh
and

cmp
jz
loop
mov
jmp
ia_done,
mov
out

;discard extraneous bits
is command finished?

ia_wait_loop
ax, OFFSET CGroup, iaset_failure_messaqe
init_exit

aI, C_INTACK
dx, a1

:clear

int~rrupt

from iaset

;initialize the receive DMA channel
xor
aI, a1
out
DMAff, al
mov
ax, rx_buf_start ;set dma up to point to the beginning of rx buf
blow
out
DMA7addr, al
mev
aI, ah
blow
out
DMA7addr, al
:set rx page register
mov
292062-46

1-380

inter

AP-327

NetWare Driver Source Code Listing (Continued)
"slow
out
mov
"slow
out
mov
"slow
out
mov
"slow
out
mov
'slow
out

DMA1page, al
al, DMArx1
DMAmode, al

;set wordcount to proper value
DMA7wdcount, al
al, ah
DMA1wdcount, al
al, dma7unmsk

;unmask receive DMA channel

DMAsnglmsk, al

;unmask our interrupt channel
in
al, InterruptMaskPort
and
aI, int_unmask
blow
out
InterruptMaskPort, al
;enable the receiver
mev
dx, command_reg
mev
al, C_RXENB
eut
dx, al
xer
ax, ax
cx, 1
mev

DriverInitialize

;enable receives

endp
292062-47

1-381

inter

AP~327

NetWare Driver Source Code Listing (Continued)
Set up Buffers:
This routine generates the page and offset addresses for the 16 bit
DMA. It checks for a page crossing and uses the smaller half of the
buffer area for Tx and general purpose if a crossing'is detected. If
no crossing is detected the general purpose/transmit buffer is placed
at the beginning of the buffer area. This routine also generates a
seqment 'address for the receive buffer which allows the value read
from the "10 cent" latches to be used as read for the offset passed
to IPXReceivePacket. This saves some arithmetic steps when tracing
back through the rx buffer chain.

proc

near

mov ax, offset cgroup: gp_buf
mov qp_buf_offset, ax
mov bx, cs
mov dx, cs
shr ax, 1
mov cx, 3
shl bx, cl
;get upper 3 bits for page register
rol dx, cl
;c1ear all but the lowest 3 bits
and dx, 0007h
laX contains EA of first location in buffer
add ax, bx
;if addition caused a carry add it to page
adc dx, 0
;of buffer to page break
mov cx, OFFFFh
;cx contains the number of bytes to page break
sub ·ex, ax
cmp cx, 01388h
intel_hop
jb
;it's cool, whole buffer space is in one page
jmp copacetic
intel_hop:
cmp cx, 0258h
;low fraqment ·is a usable size, check upper fragment
ja low_ok
;move pointer past the page break to discard fragment
add ax, ex
sub qp~length, cx;adjust length variable to reflect shorter length
mov qp_offset_adjust, cx
shl qp_offset_adjust, 1 ;convert to byte format
mov cx, qp_offset_adjust
add qp buf offset, cx
;adjust qp_buf starting point to reflect change
jmp copacetic
;both buffers will be in the'same page, rx buf shortenec
low_ok:
cJ!lP
jb
mov
jmp

cx, 1130h
high_ok
gp_length, cx;adjust length variable, discard upper buffer fragment
copacetic
;both buffers will be in the, same page" rx buf shortened

high_ok:
cmp
ja
mov
shl
mov

;now since both fragments are, usable we have to fi'nd the
ex, 09C4h
;actual page break. the large' half will be the receive
rx_first
;buffer and the small half will be the gp-tx buffer.
gp_buf-page, dx
qp_buf-page, 1
gp_buf_start, ax
292062-48

1-382

inter

AP-327

NetWare Driver Source Code Listing (Continued)
mov
mov
add

rK_buf_start, OOOOh
rK_buf_head, OOOOh
inext page
dK, 1

mav

rx_buf_page, dx

shl
shl
adc

rx_buf_page,
ax, 1
dx, 0

mav

bx, ex

mav

ex, 12

shl

dx, cl

;save number of bytes to page break

mev

rx_buf_seqment,dx

sub
mov

qp_lenqth, bK
CK, qp_lenqth

mav

rx_buf_length, ex

sub

CK, 258h

shl

ex, 1

add

ex, ax

mav

rx_buf_stop, ex

jmp

buffers_set

rx_first:

mov

rx_buf-paqe, dx

shl
mav

rK_buf-paqe, 1
rx_buf_start, ax

mav

rx_buf_head, ax

shl

rx-puf_head, 1

mov
mov
mov
add
mov
shl
add
shl
mov
add
sub
shl
shl
adc

rK_buf_lenqth, CK
rx_buf_stop, OFB9Eh ;1200 bytes from end of buffer
qp buf start, OOOOh
dx, 1
;next page
qp_buf-paqe, dK
gp_buf-paqe,
CX, 1
ex, 1
qp_offset_adjust, CK
gp_buf_offset, cx
dx, 1
dx, 1
ax,
dx, a
ex, 12
dx, cl

mav
shl
mav

rx_huf_segment,dx,

jmp

buffers_set

copacetic:

mov
add

qp_buf_start, ax
ax, 258h

;A1-A16 of gp buffer, gp buffer is first
;1200 ~ytes for qp buffer at front of buffer space
;rx buffer starts 1200 bytes in

mav

rx_buf_start, ax

mav

rx_buf_head, ax

shl
sub
mov
mov

rK_buf_head, 1
qp_lenqth, 258h
cx, qp_ienqth
rK_buf_lenqth, CK
292062-49

1-383

intJ

AP-327

NetWare Driver Source Code Listing (Continued)
;convert segment to byte address

shl

dx, 1

mov

rx_buf_page, dx

mov

gp_buf-page, dx

shl
adc

ax, 1
dx, 0

mev

ex, 12

shl
mav
maV
Bub

dx, el
;load variable for transfers to IPX
rx_buf_segment, dx
ex, rx_huf_length
ex, 258h
:setup marker for low rx buffer space, >6UO words

shl
add
mev

ex, 1
ax, ex
rx_buf_stop, ax

:convert offset to byte address
;adjust segment for shift

buffers_set:
ret

Set Interrupt Vector
Set the interrupt vector to the interrupt procedure's address
save the old vector for the unhook procedure
assumes: bx has the ISR offset
al has the IRQ level
interrupts are disabled

Set InterruptVeetor
PROC
NEAR
;mask on the appropriate interrupt mask
push

ax

xchg
and
.hl

ax, ex
ex, 07h
dl, 1
dl, cl

mqv

int_mask, dl

not
mov

dl

mov

mev
mov
in
or
hlow
out
pop

;get the appropriate bit location
;set the interrupt bit variable

;set the interrupt mask variable
ax, InterruptMaskPort
int_mask_reqister, ax
aI, InterruJ?tMaskPort
aI, int_mask
InterruptMaskPort, a1
ax

eld
cbw

xor
ex, ex
moves, ex
add

aI, 68h
oint 4

;addinq 8 converts int number to int type, i.e.,
B

type 12, int 5 - type 13 etc.
292062-50

1-384

inter

Ap·327

NetWare Driver Source Code Listing (Continued)
shl
shl
xchg
mav
mav
mav
mov
mov
xchg

ax,
;tWD shifts ~ mul by 4 to create offset of vector
ax,
ax, di
int_vector_addr, di
;save this address for unhook
ax, es: [diJ
;save old interrupt veetor
word ptr old_ir~vector, ax
ax, es: [dil + 2
word ptr ~ld_ir~vector + 2, ax
ax, bx
;bx has the I5R offset

stosw
mav

ax, cs

stosw

ret
5etInterruptVector

endp

Driver Unhook
Assumes
DS = C5 = IPX segment
Interrupts are DI5ABLED
Assumes any registers but D5, 55, 5P may be destroyed
This procedure restores the original interrupt vector
This procedure will never be called if DriverInitialize
did not complete successfully.

DriverUnhook
PROC
NEAR
in
aI, InterruptMaskPort
or
aI, int_mask
"slow
out

InterruptMaskPort, al

xor

ax, ax

mov
mov
mov
mov
mov
mov
ret

es,
bx,
ax,
es:
ax,

;es is set to vector table segment
ax
word ptr int_vector_addr
word ptr old_ir'Lvector
[bxl, ax
;restore old interrupt offset
word ptr old_irq_vector + i
es: [bx + 2l, ax
; restore old interrupt segment

DriverUnhook

mombo_init
end

endp

ends

292062-51

1·385

APPLICATION
NOTE

AP-331

August 1989

U,sing the Intel 82592
to Implement a
Nonbuffered Master Adapter
for ISA Systems

JOSEPH DRAGONY
APPLICATIONS ENGINEER

Order Number: 292066-001
1-386

intJ

AP-331

1.0 INTRODUCTION

1.1 Objective

The modern office has become increasingly computerized due to the availability of reasonably priced, yet
very powerful, microcomputers. One of the rapidly
growing uses of these powerful computers is desktop
publishing. This technology allows text and graphics
output to be generated that rivals the quality of work
that could only be produced by very expensive phototypesetting equipment a few years ago. Another major
application is Computer Aided Design (CAD). One
thing that both of these applications have in common is
that the output devices they require are still relatively
expensive. Networking has enabled sharing these expensive peripherals, such as sophisticated laser printers,
plotters, and FAX equipment, that would not be practical if attached to a single user machine. Since these
peripherals are seldom in constant use by a single user,
sharing them throughout an office over a LAN allows
much better utilization of each unit. Through print
spooling, the sharing of the equipment is transparent to
the user except for the short walk to the print station to
retrieve any spooled jobs. The cost reduction aspects of
networking are beginning to be reflected in the network
hardware itself. Media 'cost has been reduced, first from
Ethernet to Cheapernet. Now the move to Twisted Pair
Ethernet (TPE) lowers medium costs even further. The
increased market for LAN adapters is also driving cost
reduction in the adapter market. The 82592 Nonbuffered Master (NBM) is a simple, cost effective integrated LAN adapter for Industry Standard Architecture
(ISA) workstations which addresses this need for cost
reduction, coupled with high performance.

The objective of this Application Note is to present the
NBM592 architecture using the 82592. The implementation that will be described here uses readily available
off-the-shelf devices. This low level of integration is
presented as a starting point. Gate array or other ASIC
technology could be used to reduce the parts count of
this architecture while lowering cost and possibly increasing performance. The software aspects of this solution will also be discussed. A NetWare* shell driver is
the vehicle for illustrating the programming of the
NBM.

The NBM592 takes advantage of the increased bandwidth capabilities of the bus and memory subsystems in
current ISA computers, commonly known as "AT"
type computers. It is based on the Intel 82592 Advanced CSMA/CD LAN Controller. The NBM592 has
its own DMA, which consists of an 82C37 A DMA controller and support logic implemented in PALs and
TTL. Part of this logic implements the master handshake which allows the NBM592 to take control of the
host bus. This DMA is used to transfer data from the
network directly into' the host memory subsystem. The
NBM contains no local buffer memory. This allows the
cost of local buffer memory to be trimmed from the
cost of the adapter. The low cost and very high performance of this adapter architecture make it uniquely
suited to todays market.
Because the NBM592 is derived from the Embedded
LAN Module (ELM) the reader might find the following Application Notes helpful. AP-320 Using the Intel
82592 to Integrate a Low-Cost Ethernet Solution into a
PC Motherboard, and AP-327 Two Software Packages
for the 82592 Embedded LAN Module. These publications are available from the Intel Literature Department.

1.2 Acknowledgements
I acknowledge and thank Dan Gavish of the Intel Israel System Validation group, David Bar-On of Moran
Systems, Haifa, Israel, and Yosi Mazor of Intel MCFG
LAN Marketing for their efforts in the definition, development, and debugging of the hardware. I also
thank Ben L. Gee of San Jose, California for his work
in modifying the Embedded LAN Module driver to run
on the NBM592 hardware.

2.0 HARDWARE OVERVIEW
The NBM592 is an extension of the ELM architecture.
The NBM592 differs from the ELM in the fact that it
contains its own DMA resources. The NBM592 also
contains logic to implement the ISA bus master handshake, which allows the NBM592 to operate as a master adapter on the ISA bus. This allows the adapter to
transfer data from the network directly into host memory at higher speeds than the system DMA channels
are capable of.
The NBM592 was specifically designed' to work in 6and 8-MHz IBM PC AT machines. Although the
NBM592 has been tested successfully in a variety of
other machines, a thorough worst-case timing analysis
would be required to ensure proper functioning in clone
machines using integrated chipsets. To implement the
master handshake logic in a gate array or other ASIC,
this analysis would need to be done for all of the current motherboard chip sets to ensure clone compatibi1~
ity.
Figure 1 contains a block diagram of the NBM592 circuitry. The circuitry in the shaded area marked DMA
logic and the TCI address latches from the area marked
CSMA/CD logic would be good candidates for integration into gate array or other dense ASIC logic. The cost
reduction benefits would depend.on the level of integration ..

'NetWare is a registered trademark of Novell Incorporated.

1-387

l
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292066-1

inter

AP-331

2.1 DMA Functional Block

2.4 System Bus Interface

The DMA functional block is comprised of an 8-MHz
82C37A DMA controller, page registers for the upper
addresses in DMA cycles, a receive ring buffer overflow
prevention circuit (stop register), a watchdog timer that
limits NBM592 DMA bursts to less than 15 us, and a
wait state generator for DMA cycles. Also contained in
this block are two latches that store the address of the
last memory location containing receive data.

The system interface for the NBM592 is I/O mapped.
It uses 16 bytes of read/write I/O space. The 82592
command and status registers, 82C37A registers, page
registers, and stop register are all accessible in this
l6-byte address space. The IA ROM contents can also
be read in this window.

3.0 DMA OPERATION
2.2 CSMA/CD Functional Block

3.1 Better System Bus Utilization

The CSMAlCD functional block is implemented by
the 82592 Advanced CSMA/CD LAN Controller. This
device supports all industry standard CSMA/CD
LANs, such as IEEE lOBASE5, lOBASE2,
lOBROAD36, 10BASE-T, and IBASE5. The 82592
also supports proprietary CSMA LANs from 1 to 20
Mb/S such as the IBM PC Network. The 82592 also
implements the CSMA/DCR protocol that provides
deterministic collision resolution on CSMA LANs.
This feature can be used when the worst case time for
accessing the medium must be known.
The 82592 also implements a Tightly Coupled Interface
(TCI) to industry standard DMA controllers that allows back-to-back frame reception and retransmission
on collision to be done without CPU intervention.
When the 82592 is configured to TCI mode it generates
four additional DMA requests after the last byte of the
frame has been transferred to memory. The first two of
these transfers are used to 'move the status for the current reception into memory. The second two transfers
write the number of bytes transferred into memory. By
using this byte count value it is possible to reconstruct
the chain of packets in memory so they can be handed
off to the 'higher layers of the software. This will be
discussed more fully in the software section of the Application Note.

The NBM592 operates as a DMA master on the I/O
channel of the host computer. This means that all address and control signals are generated by the NBM592
while it is actively transferring data. The NBM592
DMA block is based on the 8-MHz 82C37A DMA
controller. By providing its own DMA the NBM592 is
able to transfer data between the network and memory
at a higher rate than the system DMA channels would
allow. Two of the four available channels of the on
board 82C37A are used by the NBM592. In the default
configuration Channel 0 is used as the transmit channel
and Channel 1 the receive channel. Channels 2 and 3
are not used. The transmit and receive channels may be
exchanged by using jumpers. The 82C3 7A provides address lines A 16 through A 1. Address lines SA 16-SA9
on the ISA bus are latched from the multiplexed address/data bus of the 82C37A by ADSTB. Address
lines SA8-SAl are driven by the A7-AO outputs of the
82C37A through a transceiver. AO is pulled low during
DMA transfers because all transfers are word aligned.
The upper address bits are provided by the page registers, which are programmed during initialization. IClO
is the page register used for the Transmit channel, and
ICII is the page register used for the Receive channel.
This architecture allows DMA transfers across a
128-kB memory space for both transmit and receive.

2.3 Analog Interface

3.2 System Bus Arbitration

The analog interface for the NBM592 consists of a separate daughterboard that attaches to the NBM592
through an SBX connector. By using this approach it is
possible to support IEEE lOBASE5, lOBASE2,
lOBase-T, lBASE5, and other proprietary network
standards by simply removing one daughterboard from
the digital assembly and installing a different analog
interface. There are currently three analog interface
modules, an Ethernet module, a Cheapernet module,
and a Twisted Pair Ethernet (TPE) module, which is
based on the Intel 82521 Serial Supercomponent.

When the 82592 needs to perform DMA cycles it asserts its request to the on-board 82C37A. The 82C37A
then asserts its HRQ pin. This pin is connected to the
DRQ6 line in the I/O channel. When DACK6 is returned the NBM592 drives the MASTER line in the
I/O channel low, waits one clock and then drives the
address bus. One clock later the NBM592 drives the
control lines. The NBM592 may then perform DMA
cycles for' up to 15 /J-s. This time limitation exists to
ensure that the system can access the bus to perform
refresh cycles.

1-389

inter

AP-331

If a collision occurs during transmit, the NBM592 must
be able to reinitialize the DMA controller to point back
to the beginning of the transmit buffer. This reinitialization must be done without CPU intervention to be
ready to retransmit the frame within the 9.6 ,""S Interframe Spacing (IFS) time. The NBM592 does this by
performing the TCI handshake with the 82592 to determine when a collision has occurred. The EOP pin on
the 82C37A is then activated by the TCI logic. Since
the 82C37A has been programmed to autoinitialize
mode it resets its address to the beginning of the transmit buffer. After the IFS time and the random backoff
time, if any, the 82592 will begin to make DMA requests and the frame will be retransmitted.

by the CPU. This prevents corruption of the receive
buffer structure during extremely heavy network traffic
conditions. The stop register can be tested on power up ,
by reading the overflow bit. The lower five bits of the
stop register are used to select the IA PROM address.
The OVERFLOW line is pulled up to Vcc' to allow
removing the overflow ,comparator and register IC8
and IC9 for ,a lower cost version of the board. If the
stop register circuitry is removed it would be advisable
to use the linear restartable buffering approach that was
used in the ELM driver. In this approach, as frames are
received, the driver software checks to see how much of
the ,receive buffer remains available. When most of the
buffer has been consumed the software reinitializes the
DMA controller to point back to the beginning of the
buffer space, and reception can resume. '

3.4 Receive DMA Channel

3.5 Wait State Generator

The receive DMA channel in the NBM592 uses a ring
buffer. This is done by programming channel 1 of the
82C37A to autoinitialize mode. When the DMA channel reaches the end of the receive buffer space, it autoinitializes to the beginning of the receive buffer space
and continues reception there. This approach ensureS
that the maximum possible buffering capacity is always
available to the adapter., The integrity: of the receive
buffer is protected by a stop register, which is discussed
in detail in section 3.4.1. A pair of latches is used to
store the last address in memory that contains receive
data. These latches are triggered by the TCI handshake
at the completion of a receive operation. At that instant
the latches are clocked and the address on the A16-Al
lines are latched. When the NBM592 receives a packet
it appends four words of information. The upper bytes
of these four words are not used. The lower bYtes contain the status of the reception and the byte count of the
frame. The byte count, along with the value from the
TCI latches, is used to recover the received frame chain
from the receive buffer. This process is discussed in
section 7.3.1.

The DMA circuitry also contains an optional wait state
generator. Zero to three DMA wait states can be selected by a jumper that controls the wait state generator
(IC23). Timing calculations show that one wait state is
needed for a 6 MHz AT, and that no wait states are
needed for an 8-MHz AT. The basic DMA transfer
~e is 3 clocks, two clocks for the command (RD or
WR) and one clock for address setup time. Wait states
extend the command. The address setup time can be
extended to two clocks by programming the 82C37A to
normal write cycle. In this case a wait state should be
added.

3.4.1 Stop Register

4.1 Transmit EOP

The Stop register (IC9) holds the stop address for the
receive ring buffer. This implementation uses a
256-byte resolution. A finer resolution would require
additional components. The CPU loads it with a new
value as each receive buffer is processed. The value
in the stop register is compared by IC8 to the corresponding address lines during DMA receive cycles
(DMA_MW). When the contents of the latch and the
address bus contain the same value, the OVERFLOW
signal is activated. The OVERFLOW signal is latched
by PAL 4, and the interrupt line is asserted. The
OVERFLOW bit can be read by the CPU by an I/O
read at offset OEh from the base address of the adapter.
The bit appears on the DO' data line. When
OVERFLOW is active, the Receive channel of the
DMA is 1W. BADTX is EOP • DRQ delayed by one
pal. DMA_MW is not delayed by the PALs; thus timing requirements are met and DISDACK is generated
properly.

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4.2 Separate Receive and Transmit
Page Registers

4.6 DRAM Precharge Time

An address setup time of 120 ns is required before asserting the command (Read or Write). This is done by
adding a I-clock delay to the first command in each
burst, and asserting an additional wait state to this first
command. The signal EN_CMD is generated by
PAL3. EN_CMD is activated two clocks after
DACKO or DACKI, and remains active until the end
of the cycle. A wait state is added to this first command
by the qualification of the RD_O~WR signal by
EN_CMD. The EN_CMD controls the enable line of
the command bus buffer. This buffer drives SAO and
BHE, which are part of the address and must be active
before command. These lines are driven by the PALs.

4.3 Extra Wait State
The 82C37A lOW signal can be active after the end of
the 82C37A S4. This will cause an extra wait state to be
inserted. This can be eliminated by using the 82C37A
MEMW signal for the wait state generator instead of
the 82C37A lOW. This line will always go inactive before the end of S4. This prevents the insertion of extra
wait states.

4.4 TCI·Direction
When the TCI latch is read by the CPU the data buffer
direction line that is driven from the RD line is in the
wrong direction. This is because the DMA controller
clear mask register can be accessed by writing to the
same address. To prevent this the RD line has been
disabled.
When addressing the DMA clear mask register the
37 CS is deactivated. This prevents access to this register: The local RD signal is driven by lORD during
slave cycles.

4.5 Bus Contention
Since the 82C37A specification does not guarantee that
the mid address (strobed by ADSTB) will float before
the command is active, contention can occur on these
lines. The solution is to delay the command (Read or
Write) until after each ADSTB cycle. This is done by
generating EN_CMD, which disables the command
for one clock and adds one wait state in addition to
those added by the wait state generator. This is implemented in PAL3.
The high data buffer is enabled by EN~DDR, which
is active only during master cycles. This prevents the
NBM592 from enabling the high data buffer (SDI5SD8) during slave accesses to odd I/O addresses. If this
was not done, contention with low data multiplexed
into the high data by the motherboard would occur.

There is a problem with the worst case timing of the
82C37A when more than one transfer cycle is executed.
The problem is that the worst case time between two
commands can be lower than the precharge time required by the DRAMs. If extreme values are taken for
two delay parameters, (maximum value for inactive
time and minimum value for active time) the DRAM
precharge time will be violated. We assume that for the
same signal the difference between those two parameters does not exceed 30 ns. This satisfies the precharge
time for the DRAM chips. The required precharge time
is 100 ns. For the address setup time, the assumption is
that command is activated after the address is stable
(i.e., the address setup time is greater than zero). The
address path to the memory chips consists of the delay
through the 74LS245 transceiver on the NBM plus the
delay of the 74FI58 in the host system. The total delay
is 19 ns. The command path to RAS consists of one
74LS244 on the NBM plus a 74FIO and a 74FOO in the
host'system. This path totals 9 ns. The required setup
time specified for the DRAM chips is 0 ns. Therefore, a
10 ns setup time from the 82C37A will satisfy the required setup time. The same analysis holds for read and
write cycles.
The 82C37A worst case timing does not guarantee that
the Read command signal will stay active after the
Write command is deactivated. For proper board operation the Read must stay active after the deactivation of
the Write signal.

5.0 DATA PATH
The data path includes the 82592, the interface to the
analog circuit, the 16-bit address latch for the TCI address (IC2 and 4), the 16-bit data transceiver for buffering data (IC3 and 5), and the IA PROM which contains the station address (IC6). 82592 connections and
signal names are the same as in the ELM. The low
address latch latches its data directly from the 82C37A
lines in order to minimize the loading on the bus. The
high address latch latches its data from the system's SA
lines.
'
The Station IA is read from the PROM, which is enabled by PROM_CS. To read the IA PROM, the
CPU first preJoads the stop register with the address of
the byte to be read. The CPU then reads from I/O
address 30Ah. In the current design the 82592, the
DMA, and all the other circuitry is clocked by the same
8-MHz clock. In future versions the 82592 can be
clocked by a 16-MHz clock. In this case, the 8-MHz
clock to the rest,ofthe board will be generated by dividing the 16-MHz clock by 2, in the unused flip-flop of
ICI5A. This requires jumper changes. There is an option of driving the 82592 clock from a 16 MHz clock.
The clock can be divided by 2 to produce the local
8-MHz Clk to the 82C37. The local oscillator could be
eliminated by using a IO-MHz 82C37A and using a

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Table 1. NBM592 I/O Map
Address

DMA
Register

300h

Write

Read

0

Base and Current
Address No. 0

Current Address No. 0

301h

8

Command Register

Status Register

302H

1

Base and Current
Word Count No. 0

Current Word Count No. 0

303h

9

Request Register

304h

2

Base and Current
Address No. 1

305h

A

Single Mask

306h

3

Base and Current
Word Count No. 1

307h

B

Mode Register

308h

4

592 PortO

Current Word Count No. 1

592 Port 0

309h

C

Byte Pointer FF

30Ah

5

Page Register 0 (Tx)

IAPROM

30Bh

D

Master Clear

Temporary Register

30Ch

6

Page Register 1 (Rx)

30Dh

E

LowTCI Byte
High TCI Byte

30Eh

7

Stop Register

30Fh

F

Write Mask Register

Overflow Flag

buffered version of the TxC signal generated by the
82C50lAD on the analog module to clock all NBM592
circuitry.

and SMEMWR are buffered by the system. The lORD
and IOWR signals are inputs and are buffered by the
PALs. AEN is an input to the decode PAL.

Provisions have been made for a boot EPROM (IC25).
This optional device is accessed during the system boot
process. The BIOS searches for a remote boot ROM,
and if one is found the ROM initialization code is executed. IC24 serves as its address decoder. EPROM size
and memory allocation are jumper selectable (see APPENDIX B for details). If a remote boot is not needed,
both IC24 and IC2S can be omitted.

The NBM592 can used IRQ 10, II, 12, 14, or IS.
IRQlO is the default interrupt request, driven by the
82592 interrupt signal OR'd with the overrun latch.
The interrupt line is jumper selectable. Jumper locations to select the various lines are given in the jumper
tables.

6.0 PC AT 1/0 CHANNEL INTERFACE
The board was designed to occupy no more than 16
I/O addresses; to meet this restriction, during slave
mode access to the 82C37A SAO is routed to A3 and
during DMA cycles A3 is routed to SA4.
The NBM592 uses a 16-bit DATA path. All signals in
the data path are buffered. SA lines are decoded directly by the PAL, and driven by the DMA through buffers. LA lines are driven by the latches. MEMRD and
MEMWR lines are driven by the DMA. SMEMRD

The master handshake requires the use of one host
DMA channel. In the NBM592 host DMA channels 5,
6, or 7 can be used. The channel is used in cascade
mode to allow the NBMS92 to master the host bus. The
default connectio~ is channel 6 with channels 5 or 7
available through jumper selection (see APPENDIX B
for details) .. The MASTER signal is activated by the
PALs when the board DMA is active.

6.1 Refresh Watchdog Timer .
There are two watchdogs on the NBM592. The watchdogs are driven from the local 8-MHz clock. Watchdog
No.1 is used to ensure that the refresh mechanism will
be able to gain control of the bus when it needs to.

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Refresh cycles occur approximately every 15 /Ls. When
a refresh request occurs the DMA must release the bus
within 15 /Ls. This 'is done by using a time constant of
12 /Ls in the watchdog. When a refresh request is sensed
the watchdog starts to run. The watchdog timer will
expire after approx. 12 /Ls. This corresponds to W5 •
W6 at 8-MHZ, the 3 extra /Ls will be spent transferring
bus control between the two DMAs. After the bus is
relinquished, the request is regenerated one clock after
DACK6 is inactivated. Analysis and lab inspection
show that while working with no wait-states, 82592
bursts do not exceed 12 /Ls. Therefore, this circuitry
may be removed from future versions of the board.

6.2 Floppy Disk Watchdog Timer
Watchdog No.2 i~ an optional floppy disk watchdog
(SPARE-I). The purpose of this watchdog is to avoid
the possibility of bus starvation to the floppy disk during DMA bursts by the NBM592. DRQ2 is used to
sense activity of the floppy drives. The watchdog drops
the 82592 request with a delay after a floppy DMA
request is encountered. This watchdog is disabled by a
jumper, as it is redundant. This is an optional feature
and is not used in the present implementation.
The + 12-V line in the ISA bus provides power to the
analog module.
The Reset line from the bus is used to reset the
NBM592 circuitry during system initialization.

7.0 SOFTWARE
The software discussion in this Application' Note is
based on a driver intended to be used with Novell
NetWare V2.1. The driver is based on the driver that
appears in AP-327, Two Software Packages for the
82592 Em.bedded LAN Module. There are two major
differences between the driver in AP-327 and the driver .
in this Application Note. First, this driver uses a ring
buffer approach, as opposed to the linear restartable
buffer used in the ELM. Secondly, this driver uses macros for conditional blocks to allow the code to be written in a manner resembling a high-level language. This
makes the code more readable for those with limited
assembly language experience.
While this driver 'is written to run with a specific networking package, it contains all the functions that
would normally be required by any networking package. Once a good understanding of the code is gained it
should be possible to modify most of the procedures to
operate under another networking package. The main
differences will be the format of the communicating
structures between the driver and the lowest layer of
the networking software. The procedures that will be
discussed in detail in this Application Note are DriverInitialize, DriverSendPacket, DriverlSR, and Driver-

Poll. These four procedures are the backbone of the
driver and represent the most important code for understanding the functionality of the NBM592. Procedures called from within the primary procedures will
also be covered.
The source code for the procedures discussed below is
included as APPENDIX E.

7.1 Initialization
In our software example, initialization is carried out by
the procedure Driverlnitialize. This procedure is called
by the networking software when it is loaded. This procedure initializes the hardware and any software variables that must be initialized at run time. The transmit
and receive buffer variables are initialized through a
call to SetUpBuffers. Driverinitialize also calls the procedure SetInterruptVector to initialize the proper entry
in the system interrupt vector table, after first saving
the vector that is already there.
7.1.1 Driverlnitialize

The first function that Driverinitialize performs is to
set the variable MaxPhysPacketSize to 1024. This value
is used to negotiate the maximum size of the frames
that will be transferred between the fileserver and the
workstation.
Next, the base I/O address is read from the configuration table and this value is added to the offset value for
each register in the NBM592 I/O space. This includes
the 82C37 A registers, the stop register, the TCI latches,
and the IA PROM address.
The CPU now reads the Master DMA channel number
from the configuration table and calculates the required
variables. This is the host DMA channel that will be
used to implement the master handshake between the
NBM592 and the host.
The next operation is to read the station address from
the address PROM. This is done by first writing the
address of the byte to be read to the Stop register and
then reading from the IA PROM port. The value written into the stop register is used to drive the address
inputs of the IA PROM. The code to read the PROM
is implemented as a loop, with the value written to the
latch staring at zero and incrementing through five to
read the six bytes of station address. These six bytes of
address are stored in the array node_addr and also are
written into a location in IPX's space. The location
IPX wants the address written to is passed in the DI
register when Driverlnitialize is called.
After the station address has been read and stored, Driverinitialize loads the AL register with the number of
the interrupt line that the NBM592 will use, loads the
BX register with the offset of the procedure DriverISR,

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and calls the procedure SetlnterruptVector. Details of
this routine are provided in section 7.1.2. After SetInterruptVector retu,rns, a call is made to the procedure
SetUpBuffers. SetUpBuffers initializes all the buffer
management variables. Details of this procedure appear
in section 7.1.3.
After SetUpBuffers returns, DriverInitialize is ready to
configure the DMA channels that the NBM592 will
use. One host DMA channel and two of the on-board
DMA channels will be configured. The host DMA
channel is configured to cascade mode. This allows the
onboard DMA to use this channel for arbitration in the
ISA bus. The onboard DMA controller is configured
for extended write, active low DREQ, and rotating priority. The transmit DMA channel in the onboard controller is programmed next. The channel is configured
to autoinitialize mode to allow retransmission on collision without CPU intervention. This channel wilf be
used to transfer the configuration and address parameters to the 82592.

Now that the 82592 is' initialized, the receive DMA
channel can be set up. This channel is also programmed
to autoinitialize mode and the word count is set to the
size of the receive buffer-I. This will cause the DMA
to wrap around to the beginning of the receive buffer
when it reaches the end. This results in a ring buffer.
The receive stop register is programmed with a value
near the end of the buffer. The receiver is enabled by
issuing a Receive Enable command to the 82592. The
AX register is zeroed to indicate that the initialization
completed successfully and control is returned to IPX-.
The, hardware is now ready for operation.
7_1.2 SetlnterruptVector

The' 82592 operates in the 8-bit-bus mode after reset. It
is put into the 16-bit-bus mode by giving it a Configure
command with zero in the byte count field. This is the
first command that the driver issues to the 82592. The
transmit channel is set up to point to the beginning of
the'transmit buffer area. The word count is set to I
because the'82C37A interprets this register as transfersto-be-made - 1. A Configure command is now given to
the 82592. DriverInitialize n9w enters a polling loop to
determine when the command has been completed. The
software can tell when the command is complete by
reading the 82592 StatusO register and testing to see if
the interrupt bit is set. This loop will be repeated a
maximum of 65,536 times. If, the command has not
completed by that time, a pointer to an error message is
moved into the AX register and control is returned to
IPX. At that point the error message will be displayed
and the loading of the driver will be aborted.
After the first Configure command has completed, another Configure must be done to actually load the desired parameters into the 82592. The transmit channel
is set up to point to the beginning ofthe transmit buffer
space and the word count is set to eight. This will allow
the nine required transfers to be made. The byte count
and configuration parameters are copied into the transmit buffer area and a Configure command is issued to
the 82592. Once again a polling loop is entered to wait
for command completion.
To set the station address the transmit channel is set up
to point to the beginning of the transmit buffer and the
word count is programmed to 3. The byte count and
station address are copied into the transmit buffer and
an IA Setup command is issued to the 82592. The
82592 is again polled for command completion.

The CPU reads the value of the interrupt line to be
used from the configuration table. It puts this value in
the AL register. The offset of the Interrupt Service
Routine (ISR) is placed in the BX register and SetlnterruptVector is called. This procedure calculates the
mask and unmask variables for the interrupt channel
that will be used for the driver. This channel is then
masked to prevent any unwanted interrupts. The CPU
now calculates the address in the interrupt vector table
where the vector will be stored. After saving the vector
that is already at the location to be used SetInterruptVector installs the interrupt vector for the NBM592.
The procedure ends in a return that passes control back
to Driver initialize.
The next initialization task is to set up the transmit and
receive buffer space to accommodate the architecture of
the NBM592 DMA subsystem. This is done by a call to
SetUpBuffers.
7.1.3 SetUpBuffers
The NBM592 DMA architecture is essentially the same
as the ISA DMA subsystem. It is made up of an
82C37A supplying AI6-Al and a page register supplying AI7-A23. AO is pulled low when DMA transfers
are being made because all transfers are done on word
boundaries. Because of the fact that no carry can be
generated from A 16 to A 17, the buffers must be located
such that no 128-kB boundary exists in them. If the
address of the 82C37A is allowed to roll over from
FFFFh to OOOOh the page register will remain unchanged. This will cause memory locations at the very
bottom of the 128-kB page to be overwritten. SetUpBuffers prevents the occurrence of this problem by
checking to see if a boundary exists in the buffer area
and then allocating the buffer space to the transmit and '
receive buffers accordingly. It is strongly recommended
that commercial implementations of the NBM concept
use counters instead of latches for the upper address
bits. This would eliminate the problems associated with
the page register implementation and would simplify
buffet setup and processing.

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The SetUpBuffers procedure in this Application Note is
an improved version of the procedure presented in AP327. Although the general approach is the same, several
changes have been made to accommodate the ring buffer implementation.

7.2 DriverSendPacket
Transmission on the network is accomplished by the
procedure DriverSendPacket. When the IPX wants to
send a packet to the fileserver or another station, it
prepares a Transmit ECB and calls DriverSendPacket.
The address of the ECB is passed in the ES:SI register
pair. The procedure checks to see if frames are already
queued for transmission. If frames are queued, DriverSendPacket adds the new ECB to the end of the queue
and returns control to IPX. If no frames are queued for
transmission, execution falls through to the procedure
StartSend.
7.2.1 StartSend

The procedure StartSend is responsible for actually
building the frame in the transmit buffer, setting up the
DMA controller, and issuing the Transmit command to
the 82592. This routine also calculates any padding
needed to bring the frame up to minimum Ethernet
length. '
The first action that StartSend takes is to set the transmitting flag in the driver workspace area of the ECB.
This flag is used to ensure that only valid transmit
ECBs are returned to IPX by the transmit ISR. If a
transmit request is cancelled and then the interrupt for
the cancelled transmit occurs, the code could erroneously return a packet that had never been transmitted.
Having this flag available prevents this.
If the IPX packet plus the Ethernet overhead bytes do
, not add up to a frame size of 64 bytes StartSend calculates the number of padding bytes required and stores
this value in memory for later use. After the padding
calculations have been done StartSend begins to build
the transmit frame in memory. The frame begins with
the 82592 byte count. This includes the IPX packet, the
Ethernet header and CRC bytes, and the chaining byte
at the end of the frame. In this application the chaining
byte will always be zero, since chaining is not supported.
The transmit ECB contains a fragment list which describes the length and location of each fragment in
memory that makes up the frame to be sent. This list ·is
processed by StartSend with the fragments being copied
in order into the transmit buffer. After the copy is complete any required pad bytes are moved into the end of
the buffer.

After the transmit frame has been built in memory the
DMA controller and page register are programmed
with the address of the beginning of the transmit buffer.
The word count for the frame is written to the DMA
controller and then it is unmasked. Writing a Transmit
command to the 82592 causes it to begin making DMA
. requests and transmission begins. The starting time of
the transmission is saved in memory and StartS end returns control to the calling code.

7.3 DriverlSR
DriverISR is the interrupt service procedure. It calls
the procedures RcvdPacket or SentPacket after it has
determined the source of the interrupt.
The first task in the Interrupt Service Routine (ISR) is
to save the machine state. This is done by pushing all
the registers on the stack as soon as the ISR is entered.
Once the machine state is saved the program is free to
use all of the processor's registers for its own purposes.
The segment registers are then set so they all point to
the same segment since the driver is implemented as a
.COM program. In this memory model code and data
share the same segment.
The ISR code next issues an End Of Interrupt (EOI) to
the two 8259A Programmable Interrupt Controllers
(PIC). This allows the PICs to accept interrupts from
other sources. Since the PICs are configured in the edge
triggered mode they can be cleared before the 82592
interrupt has been cleared. In a system that uses level
triggered interrupts, the interrupt from the 82592
would have to be cleared first. If this architecture were
migrated to the PS/2TM it would require the 82592 to
be acknowledged first because the PS/2 systems use
level triggered interrupts.
DriverlSR now checks to see what event caused the
interrupt. This is accomplished by comparing the status
read from the StatusO register of the 82592 to the event
codes for receive, transmit and retransmit. The value
read from StatusO is AND'd with ODFh prior to the
comparison to mask the state of the Exec bit. This simplifies the comparison step. If the event code is not
receive, transmit, or retransmit, the driver increments
an error counter called false_590_int and proceeds to
the exit code. If the event code is receive;, the procedure
RcvdPacket is called. If the event code'is transmit or
retransmit, the procedure SentPacket is called. Upon
return the driver proceeds through the exit code.

7.3.1 RcvdPacket
The driver's first action upon entering the RcvdPacket
procedure is to read the TCI address latches. These two
8-bit latches contain A 1-A 16 of the ending address of

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the last frame received. This address is used as the
starting point for the buffer reconstruction process. It is
saved in a variable called rx_buff_tail. The last four
words of the receive buffer contain status and length
information for the packet. By subtracting the length of
the current buffer from the current address read from
the TCI latches, the end of the previous frame can be
found. By repeating this process the complete chain of
unprocessed frames can be reconstructed. The status
bytes are used to determine whether the frame should
be processed or discarded. The procedure Normalize
Pointer is used to account for the possibility that the
packet is wrapped around in the receive ring buffer
while the status and length bytes are being read.
Each packet contains two length fields. One is contained in the IPX header and the other is contained in
the Ethernet header. The length of the packet is validated by doing several length checks. The length of the
Ethernet header' is subtracted from the total bytes received prior to doing the length checks. The first length
check determines if the packet exceeds the 1088 byte
maximum length for this driver (1024 data bytes and 64
NetWare bytes). The next length check determines if
the frame is shorter than the miniinum dictated by IPX
(30 bytes plus padding). The final check makes sure
that,the IPX length and the actual number of bytes
received agree. If any of these length checks fail, the
appropriate error counter is incremented and the frame
is discarded. If all the length checks pass, the packet is
added to a list of good received frames by putting a
pointer to the first byte of the frame into the array rlLlist and incrementing the variable num_of_frames.
Since the length of rx~ist is limited to 30 entries a
check is made to see if this is the last entry in rx_list.
This cycle is repeated, until all frames have been processed, or all entries in rlL-list have been used. When
one of these two events occur the driver enters a small
loop of code that takes care of handing the received
packets off to IPX.
The handoff loop is controlled by the variable nuIIL.
of_frames. Mter each frame is hamled off to IPX
num_oLJrames is decremented. When, num_of_
frames reaches zero there are no more frames to hand
off and the loop terminates. The list is processed by
reading the offset of the first byte of the frame from
rx_list. This offset is used to read the socket number
from the IPX header of the frame. The socket number
is used as a parameter for a call to the IPX routine
IPXGetECB. If there is an ECB available for that socket IPX passes a pointer back to the driver. If an ECB is
available the loop calls the procedure DeliverPacket,
which does the processing necessary to transfer a packet from the. driver to IPX. If no ECB is available, the
next frame is processed.

After all frames have been processed the stop register is
checked to see if a receive overflow occurred. If an
overflow occurred the variable rx_buff_overflow is
incremented. The stop register is then updated by writing the value of rx_buf_tail- 256 into it. The value of
receive buffer head is then updated by writing the value
of rlL-buf_tail + 2 into it. The variable rlL-buf_
head now points to the first byte of the next receive
buffer. Execution now returns to DriverISR.
7.3.2 SentPacket

The first action taken in the SentPacket procedure is to
test the software flag tx_active_flag. If this flag is not
set then a transmit had not been initiated and the trallsmit interrupt is erroneous. In this case, control simply
returns to DriverISR. If tx_active_flag is set the driver reads the status of the transmission from the 82592.
The driver tests the status to see if the transmission
completed successfully. If an error occurred the status
is tested to determine the type of failure, and the corresponding error counter is incremented. If the transmit
completed successfully, this code is skipped. Next the
driver extracts the total number of collisions the frame
experienced and adds this value to the variable RetryTxCount. The driver writes a completion code for
the transmission into the ECB, unlinks it from the
transmit queue, and returns it to IPX through a call to
IPXHoldEvent. The driver now checks the transmit
queue to see if any packets are awaiting transmission. If
there is a packet in the queue, the driver loads the ES:SI
register pair with the address of the ECB and calls
StartSend. If no packets are queued, control is returned
to DriverISR.
7_3.3 Exiting DriverlSR

After control is returned to DriverISR the driver
checks to make sure that the receiver is enabled. If it is
not, then a Receive Enable command is issued to the
82592. DriverISR then Issues an Interrupt Acknowledge to the 82592. This clears the interrupt that caused
entry into the DriverISR code and allows any new interrupt that may have occurred during processing to
move into the 82592 StatusO register. DriverISR reads
this register to determine if a new interrupt occurred. If
a new interrupt is detected then execution loops back to
the beginning of the ISR and the new interrupt is processed. If no new interrupt is detected a call is made to
IPXServiceEvents to tell IPX it has events to process,
the machine state is restored to its condition when DriverISR was entered, and an IRET instruction returns
control to the code that was executing when the interrupt occurred.

1-396

AP-331

7.4 DriverPoll
The procedure DriverPoll is called by IPX to allow the
driver to check for timed-out transmits and any other
non-interrupt-driven events that need to be handled.
DriverPoll first checks to see if tx_active_flag is set.
If it is not, then control is returned to IPX. If tx_active_flag is set, then the driver checks to see if the
current transmission has timed out. This is done by
reading IPXIntervalMarker, subtracting tlL-start_
time from the value read, and comparing the result
with TxTimeOutTicks. If the result of the subtraction is
greater than TxTimeOutTicks, the transmission is
aborted by issuing an Abort command to the 82592.

DriverPoll then writes a bad completion code into the
ECB for the packet, unlinks the ECB from the transmit
queue, and returns the ECB to IPX through a call to
IPXHold Event. The 82592 is then given a Selective
. Reset command to put it in a known state. All configuration parameters are maintained when a Selective Reset is done but the Receive, Execution, and FIFO machines are all put in a known state. A Receive Enable
command is given to the 82592 to reenablethe receiver.
DriverPoll then checks the transmit queue to see if any
packets are queued. If a packet is awaiting transmission, the ES:SI register is loaded with the address of the
ECB and StartSend is called. If no packets are waiting
control"is simply returned to IPX.

1-397

intJ

AP·331

APPENDIX A
SPECIAL CONSIDERATIONS
FOR A-1 STEPPING ANOMALIES
write arrives, or when the current'DMA burst ends
(this is identified by the DACK signal going inactive).
This function is implemented in ICI5B and PAL2.

There are a few anomalies in the operation of the A-I
stepping of the 82592 that require workarounds in the
NBM592. They are discussed below.

ReceiveEOP
When bad frames are received, the 82592 signals this to
the hardware by not dropping the DREQ signal during
EOP. This can cause the 82C37A to issue another·
DMA cycle. This extra cycle can corrupt the receive
buffer chain. The NBM592 contains an Extra DMA
Read Elimination circuit to prevent this extra read cycle. The DREQ signal is disabled during the time that
the EOP is active. The DREQI # signal to the 82C37A
is qualified by the EOP signal to eliminate another cycle. The EOP goes active after the activation of the
RD# pin, this deactivates DREQI#, thus the DMA
will not issue another transfer. The EOP signal to the
DMA controller is blocked during receive cycles. This
is done because the receive channel is reinitialized when
the upper limit of the receive buffer is reached, not at
the end of each receive.
NOTE:
The NBM592 does not discard bad received frames.

Transmit EOP
The NBM592 also contains an Extra DMA Write
Elimination circuit for the Transmit channel. In some
case, when EOP and DREQ are driven active, the,
82C37A can execute an extra write cycle. This redundant cycle can be wrongly interpreted by the 82592.
The NBM592 contains a circuit that eliminates this extra cycle, if it occurs. To disable the extra write, a signal
DISDACK # is generated. This signal, when active,
disables the DACK to the 82592, causing the 82592 to
ignore the write cycle. This signal is activated whim at
the rising edge of the 82592 WR # signal (at DMA
cycles), a bad Transmit event is identified. A BAD_
TX # signal is generated when the DRQ signal is active
during the occurrence of the 82592 EOP #. The DISDACK # signal is deactivated when either the next

In many cases the extra write cycle does not occur. The
DISDACK signal, in this case, would cause the elimination of the next write cycle. This write cycle would be
the first cycle of the next frame, which would cause
undefined data to be sent instead of the next frame.
This problem was remedied by canceling the DISDACK signal at the end of the current burst. This is
done by connecting the preset signal of the DISDACK
flip-flop to the DMA controller's DACKO signal. Thus
if the extra write occurs, it is eliminated.

Transmit Error EOP
When a collision occurs after all the transmit data has
been transferred to the FIFO, the 82592 does not issue
the bad transmit EOP. This will cause the DMA controller to continue with the retransmit cycle from the
current address, instead of autoinitializing to the beginning of the transmit buffer. One solution to this problem is to program the 82C37A count register to the
actual transmit count. This will cause the 82C37A to
autoinitialize. This solution can cause a problem with
good transfers. The 82592, when tJ.'ansmitting in TCI
mode, can transmit a chain of frames. After the end of
a good transmit the 82592 issues another DMA cycle to
read the next memory location in the transmit buffer. If
the first three bits of that location are binary 100, then
the 82592 attempts to transmit another frame. With the
proposed solution to errata No.1, the 82592 will read
the chained command from the byte-count field of the
Transmit buffer. To prevent" an extra frame transmission, the NBM592 uses the 82592 EOP signal, which is
active during the' chain command read, to force the DO
line high. This is done by generating a KIL_DATA#
signal which disables the bidirectional data buffers. A
pull-up resistor on the local DO forces this line to 'I',
thus ensuring that the value read by the 82592 will not
be binary 100.

1-398

inter

AP-331

APPENDIX B
JUMPERS
Jumpers are provided to allow selection of interrupt line used, DMA wait states, and the host DMA channel used for
the master handshake. The tables below show how to set the jumpers in each jumper block as required for your
configuration.

INTERRUPT JPl
IRQI0 (default)
IRQ12
IRQ13
IRQ14

pins
pins
pins
pins

1-6
3-8
4-9
5-10

HOST DMA CHANNEL JP2
pins 1-7 and 2-8
DRQ5
DRQ6 (default)
pins 3-9 and 4-10
pins 5-11 and 6-12
DRQ7
EPROM SIZE JP3
8 kB
16 kB
32 kB

pin
pin
pin
pin
pin
pin

1-7
2-8
1-7
2-8
1-7
2-8

not connected
not connected
connected
not connected
connected
connected

EPROM ADDRESS JP4
Address
C8000
CAOOO
CCOOO
CEOOO
DOOOO
D2000
D4000
D6000
D8000
DAOOO
DCOOO
DEOOO
EOOOO

A19
1-8
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

A18
2-9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

Jumpers
A17
A16
3-10
4-11
C
C
C
C
C
C
C
C
C
NC
C
NC
C
NC
C
NC
NC
C
NC
C
NC
C
C
NC
NC
C

A15
5-12
NC
NC
NC
NC
C
C
C
C
NC
NC
NC
NC
C

A14
6-13
C*
C*
NC*
NC*
C*
C*
NC*
NC*
C*
C*
NC*
NC*
C*

A13
7-14
C**
NC**
C**
NC**
C**
NC**
C**
NC**
C**
NC**
C**
NC**
C**

• When using a 32 kB EPROM this jumper is not used for address selection. Pin 13 should be connected to JP6.

*. When using a 16 kB or 32 kB EPROM this jumper is not used for address selection. Pin 14 should be connected
to JP5.

I/O ADDRESS SELECT JPI0
300h-30Fh
pins 1-2 connected
310h-31Fh
pins 1-2 not connected
WAIT STATES JP11
o WS
1 WS (use for 6 MHz AT)
2 WS
3 WS

pins
pins
pins
pins

1-5
2-6
3-7
4-8
1-399

inter

AP-331

APPENDIX C
PAL EQUATIONS
PAL 1
PALl
module PALl flag '-R3'
title 'NBMS92 - PAll X023'
IC18 device 'P20LIO' ;
SAO

pin 1; tlin

SAl

pin 2;

SA2

pin 3; "in

SA3

pin 4; lIin

lORD_BAR

pinS; ttin

IOWR_BAR

pin 6; "in

LIMIT_LATCH_BAR

pin 7; !lin

BOARD_CS_BAR

pin 8; , "in

EN_ADDR_BAR

pin 9; ''in

EPROM_CS_BAR

pin 10; ''in

NCl

pin 11; "not used

NC2

pin 13; "not used

LD_RX_BAR

pin 14; "out

LD_TX_BAR

pin 15; "out

LD_LIMIT_BAR

pin 16; "out

OE1_BAR

pin 17; "out

OE2_BAR

pin 18; "out

i592CSO_BAR

pin 19; "out

i37CS_BAR

pin 20; "out

PROM_CS_BAR

pin21; "out

DO

pin22; "out

RD_BAR

pin23; "out

"in

H,L,x=l,O,.X.;
292066-2

1-400

AP-331

Equations

!LD_TX_BAR= !BOARD_CS_BAR & SA3 & !SA2 & SAl & !SAO & !lOWR_BARi "0AH
!LD_RX_BAR = !BOARD_CS_BAR & SA3 & SA2 & !SAl & !SAO & !I0WR_BAR; "QCH
!LD_LIMIT_BAR = IBOARD_CS_BAR & SA3 & SA2 & SAl & !SAO & !lOWR_BAR; "OEH
!.OECBAR =!BOARD_CS_BAR & SA3 & SA2 & ISAl & ISAO & !lORD_BARi "OCH
!OE2_BAR = !BOARD_CS_BAR & SA3 & SA2 & !SAl & SAO & !IORD_BAR; "ODH
li592CSO_BAR = !BOARD_CS_BAR & SA3 & !SA2 & !SAl & !SAO & EPROM_CS_BAR; "OSH
!i37CS_BAR = !BOARD_CS_BAR & EPROM_CS_BAR &( (!SA3) # (SAO & SAl) # (lSA2 & SAO»;
enable DO =IBOARD_CS_BAR & SA3 & SA2 & SAl' & !SAO & !lORD_BAR; "0EH
!DO = LIMIT_LATCH_BAR;
!PROM_CS_BAR = !BOARD_CS_BAR & SA3 & !SA2 & SAl & !SAO & nORD_BAR; "0AH
enable'RD_BAR = EN_ADDR_BAR;
!RD_BAR =!lORD_BAR # !EPROM_CS_BAR;
end PAll
292066-3

1-401

AP-331

PAL2
module PAL2 flag '-R3'
title 'NBi592 -pal2 REV X024'
IC19 device 'P20LlO' ;
RD_BAR

pin 1; "in

NCI

pin 2; "in (spare)

i592EOP_BAR

pin3; "in

i592DREQO

pin 4; "in

i592DREQl

pin 5; "in

DAKO_BAR

pin6; "in·

DAKl_BAR

pin 7; "in

RESET

pin 8; "in

WATCHDOG_BAR

pin9; "in

DISDACK_BAR

pin 10; "in

i592DRQODD

pin 11; "in

LIMIT_LATCH_BAR

pin 13; "in

LTCW

pin 14; "out

DREQO_BAR

pin 15; "out

DREQl_BAR

pin 16; "out

i592DACK_BAR

pin 17; "out

MSEOP_BAR

pin 18; "out

KILL_DATA_BAR

pin 19; "out

DAKO

pin 20; "out

WD_TICBAR

pin 21; "out (for internal use)

WD_RX_BAR

pin 22; "out (for internal use)

BADTX_BAR

pin 23; "out
292066-4

1-402

AP-331

Equations
DAKO = !DAKO_BAR;
LTCW = !RD_BAR & !i592EOP_BAR & lDAK1_BAR;
!WD_TX_BAR = i592DREQO & !DAKO_BAR & IWATCHDOG_BAR & !RESET # !WD_TX_BAR
& !WATCHDOG_BAR & !RESET;"Arm when DACK active"
IWD_RX_BAR = i592DREQl & IDAK1_BAR & !WATCHDOG_BAR & !RESET # !WD_RX_BAR
& !WATCHDOG_BAR & lRESETi"Arm when DACK active"
!DREQ1_BAR = i592DREQl & DAK1_BAR & WD_RX_BAR & LIMIT_LATCH_BAR #
i592DREQl & i592EOP_BAR & WD_RX_BAR & LIMIT_LATCH_BAR;
!DREQO_BAR = i592DREQO & i592DRQODD & !RESET & WD_TX_BAR # lDREQO_BAR &
DAKO_BAR & !RESET & WD_TX_BAR; " KEEP TIL DACK
li592DACK_BAR = !DAK1_BAR# lDAKO_BAR & DISDACK_BARi
enable MSEOP_BAR =!i592EOP_BAR & !DAKO_BAR;
MSEOP_BAR = 0; "EOP TX UNIT
IBADTX_BAR = !i592EOP_BAR & i592DREQO; "DREQ active at EOP
!KILL_DATA_BAR = !DAKO_BAR & 1i592EOP_BAR;
endPAL2
292066-5

1-403

intJ

Ap·331

PAL 3
module PAL3 flag '-R3'
title 'NBiS92 - PAL3 REV X024'
IC20 device 'P20LIO' ;
DMA_MW_BAR

pin 1; "in

CIS_BAR

pin 2; "in·

IOWR_BAR

pin 3; "in

DACK6_BAR

pin 4; "in

DASTB

pinS; "in

DDASTB

pin 6; "in

FLOPPY

pin 7; "in

RESET

pin 8; "in

WS

pin9;"in

W6

pin 10; "in

DHALDA_BAR

pin 11; "in

NO

pin 13; "in (spare)

MASTER_BAR

pin 14; "out

WR_BAR

pin 15; "out

EN_CMD_BAR

pin 16; "out

NC3

pin 17; "I/O (spare)

LPBK_BAR

pin 18; "out

WATCHDOG_BAR

pin 19; "out

QRD_OR_WR

pin 20; "out

SAO

pin 21; "I/O

EN_ADDR_BAR

pin 22; "out

A3

pin 23; "out

H,L,x=l,O,.x.;
292066-6

1-404

AP-331

Equations

enable SAO = !EN_ADDR_BAR;
SAO =0;
enable WR_BAR = EN_ADDR_BAR;
WR_BAR = IOWR_BAR;
enable MASTER_BAR = IDACK6_BAR;
MASTER_BAR = 0;
!WATCHDOG_BAR =FLOPPY & !RESET
"ARM by FLOPPY WATCHIX>G

# W5 & W6 & !RESET
"ARM by 15 ~ WATCHDOG

#!WATCHDOG_BAR & IDACK6_BAR & !RESET; "DROP after release
QRD_OR_WR = (IDMA_MW_BAR # !WR_BAR) & IEN_CMD_BARi
IEN_ADDR_BAR = !DACK6_BAR & !DHALDA_BARi
!EN_CMD_BAR = !DASTB & IDDASTB & !DACK6_BAR;
enable A3 = EN_ADDR_BAR;
A3=SAOi
LPBK_BAR = !CTS_BAR;
endPAL3
292066-7

1-405

intJ

AP-331

PAL 4
modulePAU
title 'MBN592 - PAU REV X023'
IC21 device 'P20LIO' ;
AEN

pin 1; "in

SA9

pin 2;

SA8

pin 3; "in

SA7

pin 4; "in

SA6

pin 5; "in

SAS

pin 6; "in

SA4

pin 7; "in

RESET

pin 8; "in

RANGE

pin 9; ·"in

EPROM_CS_BAR

pin 10; "in

OVERFLOW_BAR

pin l1i "in

i592INT

pin 13; "in

EN_DATA_BAR

pin 14; "out

IRQ10

pin 15; "out

BOARD_CS_BAR

pin 16; "out

EN_CMD_BAR

pin 17; "in

KILL_DATA_BAR

pin 18; "in

HLDA37

pin 19; "out

LD_LIMIT_BAR

pin 20; "in

EN_ADDR_BAR

pin 21; "in

LIMIT_LATCH~BAR

pin 22;. "out

BHE_BAR

pin 23;

"in

H,L,X=1,0,.X.;
QADD=[X,x,SA9,SA8,SA7,SA6,SA5,SA4];
292066-8

1-406

intJ

Ap·331

Equations

enable EN_CMD_BAR = Oi
enable LD_LIMIT_BAR = Oi
enable EN_ADDR_BAR = Oi
enable KILL_DATA_BAR= Oi
lBOARD_CS_BAR = (!AEN & SA9 & SAS & !SA7 & !SA6 & !SAS & EN_ADDR_BAR &: ISA4 &
!RANGE) # ( !AEN & SA9 & SAS & !SA7 & !SA6 & !SAS & EN_ADDR_BAR & SA4 & RANGE }i
!LIMIT_LATCH_BAR = ( IOVERFLOW_BAR # !LIMIT_LATCH_BAR & LD_LIMIT_BAR ) &
IRESETi
!EN_DATA_BAR

=

!EN_ADDR_BAR

&

!EN_CMD_BAR

&

KILL_DATA_BAR

!BOARD_CS_BAR# !EPROM_CS_BARi
HLDA37 = !EN_ADDR_BARi
enable BHE_BAR =!EN_ADDR_BARi
BHE_BAR=Oi
IRQ10 = iS92INT # !LIMIT_LATCH_BARi
endPAU
292066-9

1-407

#

l

+5V

SIP2 10K

1

z

0
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D'

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it

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JP4

~II

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a.

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13
14

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DI
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a.

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SA17
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SA14
SA13

SMEMRO.

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0
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m
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0
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II
9
10
11
12
13
14

2
4
8
II
11
13
111
17
3
II
7
II
12
14
,.
111
1

1
1
1
1
1
1
1

REFRESH WATCHDOG
1

10C
100
2A 20A
~ 2CLR20B

,g..

74LSII1I8
PO p-o~
PI
P2
P3
P4
PS
PII
P7
00
01
02
03
04
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111

iil

T

wo

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~
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ENT

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SA4
SAIl
SAil
SA7
SAil
SAil
SAID
SAil
SA12
SA13 1
SA14 2

10 I'D
9 AI
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7A3
8 A4

liAS
4
3
25
24
21
23
2

All
A7

01
02
03
04
05

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011
Q7

011

11
12
13
111
III
17
111
III

DO

01
02

D3
D4
OS
Oil
07

o

(0-7)

-

M
All
AID
Atl
A12

~A13

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II
3

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II

UIISP

SA2

a.

1101HZ

~
rti""

74LS1S3

EPROM ADD DEC

SAO
SAl

:::r

20C
200

4

+SV

272511

:E
!!l.
n

I

r-+

Ii"

U4

U18
IIMHZ
5920ACK.
OR02

74LS3113
lA
lOA

~ lCLR10B

4---l Vpp

.,....!
JP3

U211

EPROM
-

292066-11

l

~

~H:iii

1~

20L'QA

WATCHDOG_
DISDACK.

II
10

5112DIlClOOD "
LIMIT I.ATC~
'3
..

z

0
:I
0-

582DREQ1
I»J(Q.

5
II

DAlCl.
RESET
5112DREQO

7
II
4

5e2EOPlItO_

3
1

2

-..

~
1,0
11 1
112
l!!i
18
17

18
14
13

02
03

011
OS

oe

'4
22

LTCW
WD RXWD TX_
DREClO_
KILL DATA.
MSEOP.

2'
15
111
18

07'7
011 111
04 20
01

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SSl2DACK.
DRECI,.

DAl(O

23

BADTX-

11

12

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CD
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9

DPRQ

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CUi

CLK
13

II

011

'"

08

II

lSI

02

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1

U3B

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A3

15
18

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22

EN ADOR-

110 010 '4
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O4bo

_

WR_
LPBK_

10

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12

u"
l1liHZ

12

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we

OIIIIRD

t
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13
14

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74LS174
2D
4D

4
11

MASTER_
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RD...JILWR

7415184
A
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I

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4
5

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3
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W. S. GENERATOR

u;-s-

292066-12

cl
~1I~:Z3
20L1OA

7
II

-¥
S

lORD_
IOWR_
EPROM CS_

z

o:::l

C"
C

8
10
SAO
SA1
SA2

:::::
CD
ii!

SA3

+!
1
2
3
4

17
02
03
19
112 04
1:1
OS
lIS
08
110 07
111 08
11
09
12
010
13
1<4-

RD.

22
21
20
111
18
17
16
1S

DO
PROW CS.

37 CS.
SII2CSO.
OE:Z.
0E1.
lJ) LIMIT_

LD TX.
L.D RX.

14

Co

i!:
I»
en

.,iD

,
./>.

~

»
Co
I»

"C

.,iD
oo
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~

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PALl

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T
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a

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:
r

~

SA (0-1n

SA (0-191

RESET

AEN
EPROW CS.

OVERFLOW.
S921NT

~

~l

SA9
SAIl

SA7
SA8
SAS
SA4

20L1OA
06
12
02
2
3
13
03
1<44
04
S
1:1
OS
16
8
08
7
17
07
16
8
01
1
11
09
10 110 010
11 111
13 112
II
151

-

l>

l'
Co)
Co)

-"
16
22
21
20
19
18

17
23
1S
14

BOARD CS.
LIMIT LATCH_

EN AODR.
LD LIMIT_
HLDA37
KILL OAT".
EN CWD.
SHE_
IRQ10

-

EN DATA_

~

UII
PAL.

292066-13

l

+5V
~r-

.--

..Ii: !!'

82592
CSNA/CO
CONTROLLER

U13

z

28 RXC.
31 TXO
30 RXO

RXC.
TXO
RXO

0

-.
:::I

cr

C

CTS.
CRS.
COTTXC.

CD
CD

a.

33 CTS.
35 CRS_
34 COT_
25 TXC.
NC
~
.!! NC

3l:

III

..>
....
!!!.
CD

RO-

a.

5112DACK.
5112CSORESET

WR_

III

"'C
~

.J:,..
~

I\)

CD

CO
N
U1
ID

e RD-

..

+~

!'J

~
21

<:7

14
1

0
~

N

0..

iii

0

~

PROM CS.

C)
CD
:::I
CD

PUllUP

.
..

2L

0

32
38
37
38
311
9

10

011 11

0..

iii

RTS.
015
014
013
012
01.1
010
OS

o 13

III

07
08
05
04
03
02
01

20

DO

~

o
o
~

14
15
18
17
111

o

U2
11/18

~ ClKSRC
~5 FREQ

8
7

ClK

82S123
07
08
05
04
03
02
01
DO

9

7
8
5
4
3
2
1

PA4
PA3
PA2
PAl
PAD

PA (0-4)

»"tI
I

Co)
Co)

U14

5920REOO
5920REQI
51121 NT
592EOP.

(0-7)

o.t.LE XO-438

~
2 D,PR
Q

211
27
41
42

"4 14
"3 13
.0.2 12
11
"I
"0 10

07
08
05
04
03
02
01
00

o

101HZ DSC

'"~

ORal
ORQO
INT
CSI/EOP.

(8-15)

I.A. ROM

011

OS 12

o
o

'"

~

15 CS

a: oi'"
0:

4 WR2 o.t.CK3 CS.
40 RESET

RTS.
015
014
013
012
011
010

N

......

-

5

3 C~
8
CLR
I
U3A

JPII~

8IotHZ

~
1

~
¢

292066-14

i
z0

::l
C"
C

-...
CD
CD
Co

-

TCI

SA (0-19)

3:

III
III

...iii

LTCW
OE2.

~

..

III
"C
CD

1111

C

!.
III

-

-

A (0-7)

A4
All
A8
A7

tD

...CD
J!l

-I

il -»
Co

0

:::r

AD
AI
A2
A3

c

g

DO

DO

01
02
03
04
05
08
07

01
02
03
D4

05
08
07

2
3
4
5
II
7
II

II

74LS245
- 111 III
A1
A2
112 17
A3
113 111
A4
114 15
AS
as 14
AS
1111 13
A7
B7 12
AS
&II II
OIR

+v Ii

I

ATOO
ATOI
AT02
AT03
AT04
AT05
ATOll
AT07

U211

Ril.
EN ADOR.

0

tD

III
III
17
18
15
14
13
12

EN OATA.

::::
c

2
3
4
5
II
7
II
II
II
1 DC

LSB DATA BUFFER

U27

...

~
(.)

SAil
SAl0
SAIl
SA12
SA13
SA14
SA15
SAIII

MSB lATCH
74ALS573
lQ
10
20
2Q
3D
3D
4D
4Q
50
50
80
IIQ
70
7Q
110
IIQ
ENe

DE,.

2
3
4

5
II
7
II
II
II
I

74ALS573
lQ
10
20
2Q
3D
3D
4D
4Q
50
50
80
8Q
70
7Q
80
IIQ
ENe
De

III
111
17
18
15
14
13
12

U24

o (0-7)
o (8-15)
ATD (0-15)

TCI

LSB lATCH

DO

01
02
03
04
D5
011

07

011

2

011

3
4
5

DID
OIl
012
013
014
015

II

7
II

II

74LS2045
AI
III
A2
112
A3

A4
AS
AS

A7
AS

+a Ii

111
17
18
B3
114 15
as 14
BII 13
B7 12
&II II

>'tI
I

...

(,,)
(,,)

AT08
ATOll
AT010
ATOll
AT012
AT013
AT014
ATOIS

OIR
U19

IASB DATA BUFFER

D (0-7)
D l8-15}
ATD (0-15)

--

292066-15

74LS1I74

DO
01
D2
03
D4
Oll
011
07

z

0

:::I

-.
C'

5.

LD TX*

C1)

CAKO_

C1)

2
3
4
1I
II
7
II
II
11
1

Co

III
C1)

Co

..

~
C1)

"'0

III
CD

-

.

~

LD RX-

C1)

OAK'.

J!I

::u
C1)

....in

.g...
13
15

....1.l..

.g..
111

CLK

oc '

1Yl
1Y2
1Y3
1Y4
2Yl
2Y2
2Y3
2Y4

~
7

2G

SA (0-19)

SAl II
SAl II
SA17
SA4

-

cl
-

IoIWR.

WRO.

5

t--2

U25

74LS1I74
2 10
10
320
20
4 30
3Q
5 4Q
4Q
II lID
SO
7 lID
IIQ
II 70
70
8 110
IIQ
11 CLK
1 OC

111
111
17
111
111
14
13

LA17
LAla
LAla
LA20
LA21
LA22
LA23

~
a

!!"

rll-

-

SAIl
SAil
SAl0
SA" .
SA12
SA13
SA14
SIIlli

PA (0-4)

STOP REGISTER

II"
0
0

DO
01
02
D3

3

"C

D4

III
III

05
011
07

0

LD LIMIT_

74LS1I74
2 10
10
320
20
4 3D
3Q
5 .0
4Q
II lID
SO
7 lID
IIQ
II 70
70
II lID
110
'1 eLK

~

OC..

"~

»
"0

0

I

;;:

W

W
-"

iii

OVERFLOW COMPARATOR

U12

C1)

.....

IIQ

1... 1
1... 2
1...3
1...4
10
2Al
2A2
2A3
2A4

la
111
14
12

RCV PAGE REGISTER
DO
01
02
03
D4
DlI
011
07

~ '9.
.j>.

CD

IIQ

.70

2
4
II
II
1

MOST SIG. ADD. BUFFER

o (0-7)

C1)

en
0'

SO

LA17
LAlli
LAlli
LA20

--

EN CWD_

::u
C1)

"C

3Q
4Q

.0
50
110
70
aD

EN AOOR.
OMA w_
, DMIotRO

III

III

10
2Q

LA17
LAla
LAlli
LA2D
LA21
LA22
LA23

U20

3:

.»...

10
20
3D

74LS244
111
la
17
111
15
14
13

..

-'

XNT PAGE REGISTER

111

111
17
111
15
14
13
12

PAD
P... l
PA2
PA3
PA4

PAD
PAl
PA2
PA3
PA4

2
4
II
II
11
13
15
17
3
5
7
II
12
14
111
111
1

74LS81111
PO p..0
Pl
P2
P3
P4
P5
PII
P7
00
A'
02
03
04
05
all

19

OVERFLOW

Q7

G

U22

292066-16

-

0<1

_ _ -.

A (0-7)
D (0-7)

z

0

:I
0C

=
...
CD
CD

a.

s:::

DI
IIJ

...
CD

~ DI~

UI

-...

'tI
CD

C

s:::

•

D (0-7)

SAS
SAID
SAil
SAI2
SA13
SA14
SAUl

18
18
17
18
15
1.
13

74573
lQ
lD
2Q
2D
3D
3D
4Q
4D
50
5D
lID
liD
7Q
7D

SAU.

12

8Q

DREQO.
DREQI.

2
3
4
5
II
7
II

eo e

ENC

MID. ADD. LATCH

ri-!-

11237
DBO
M
OBI
"I
DB2
A2
DB3
A3
DB4
M
DB5
A5

32
33
34
35
37

M
"I
A2
A3
M

M
"I
A2
A3
M

311
38
40

AS
"II

AS

AS
",7

DO
Dl
02
03
D4
05
D8

DD
Dl
02
D3
D4
D8

30
28
211
27
28
23
22 DBS

07

D7

21

OS

DB7

II ADSTB HRQ 10
18 DRQD AEN ~

oc ~

III

1 JP7 3
2
4 '

II

HLDA37

RESET
37 CS.

l

.... _

A (0-7)

U21

/1.7

I

AS
1..7

111
17
18
15
1.
13
12

74245
Bl
"I 2
B2
A2 3
B3
A3"
B4
". 5
B5
AS II
B8
"II 7
B7
"7 II

11

B8

All

CIR

ADD. XCVR.

SAl
SA2
SA3
SA4
&AS

SAil
SA7

sa

SAil

H 1",..._-.

G~

I~ ~~ ~~i~~:!i=~~!I~~~~~~!;t:;;l::;U;30;;~~;:~::J:::~~~;;::::

13 RST
11 CS

CLK 12
DAKO 25
OAKI 24
DRQ2 iOR
1
DRQ3 lOw
2
EOP 38

DRQ •
OACK 1
OACK2

~ RDY

---*
........,!!.

READY'

1~7

JP8

1iiR

4

1

3

DIIIA 18 ..

):0

IotRD

3

2

4

OIotIlRD

l'

...
Co)
Co)

Ul

EN ADDR.
DACKO..

-.

1l1otH2

.

RD_

RD.

r

MSEOP.

0
0

:I

..... IL.

0

CII

=;-

'

...iii'

lNXXXX
CRNNN

+5 V

~

%"
~
a
~ii:~ii:.~~!!:~ii:

~ii~iii~a:2"'~ii

SIP1C

L-____------~----+_~~~~~
10Kt

RNNN

XXXXI

...•

ASTB

z

SI 5
292066-17.

inter
Parts List
Reference
IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
IC9
IC10
IC11
IC12
IC13
IC14
IC15
IC16
IC17
IC18
IC19
IC20
IC21
IC22
IC23
·IC24
IC23
SPARE1
SPARE2
SIP1
SIP2
SIP3
JP1
JP2
JP3
JP4
JP5
JP6
RR1
RR2
RR3
C1
C2
C3-C20
P18

AP·331

Vee

Gnd

Pins

1,44,43
20
20
20
20
16
31
20
20
20
20
20
20
20
14
14
16
24
24
24
24
14
14
20
28
16

21,22,23
10
10
10
10
8
20
10
10
10
10
10
10
10
7
7
8
12
12 .
12
12
7
7
10
14
8

44 (PLCC)
20
20
20
20
16
40
20
20
20
20
20
20
20
14
14
16
24
24
24
24
14
14
20
28
16
10
10
10
10

Type
82592
74ALS573
74LS245
74ALS573
74 LS245
82S123
82C37A
74LS688
74ALS574
74ALS574
74ALS574
74ALS573
74LS245
74LS244
74LS74
74LS393
74AS174
PAL20L10
PAL20L 10
PAL20L10
PAL20L10
OSC8MHz
. 74LS164
74LS688
27256
74LS163
DIP SWITCH
10K
10K
10K
10 pin jumper
12 pin jumper
10 pin jumper
3 pin jumper
16 pin jumper
12 pin jumper
13K%W.
1K%W
1K%W
100,...F/16V
100,...F/16V
0.1,...F
IBM CONN. 803,829
801,810,83162

1
1
1

1-416

inter

AP-331

APPENDIX E
FLOWCHARTS AND PROGRAM LISTINGS

292066-18

Driver Broadcast Packet-Driver Send Packet

Decrement Fragment Count

292066-19

Start Send

1-417

intJ

AP-331

IPX Hold [vent

292066-20

Driver Poll

1-418

Ap·331

292066-21

DriverlSR

1-419

inter

AP-331

292066-22

RcvdPacket

1-420

inter

Ap·331

292066-23

1-421

inter

AP-331

292066-24

Deliver Packet

1-422

inter

AP-331

292066-25

Sent Packet

1-423

AP-331

$mod186
$nogen
;********************************************************tittttttt __ _

IIIII! FOR EVALUATION PURPOSES ONLY IIIIII
NetWare Driver for the Intel Non Buffered Master adapter.
Written by Ben L Gee.
Based on Joe Dragony's driver for the LAN-On-Motherboard Module.
;*******~.**********************.*****************

•• ** ttttttt,ttttt*_

name Shell_Module
false equ 0
true equ 1
$ include (relid.ine)
$inelude(smaero.ine)
het (V2_l, 1)
het (V2_0, 0)
'*define(slow) local label
jmp short 'label
Uabel:

'*define(fasteopy) local label (
shr ex, 1
rep movsw
jne Uabel
movsb
Uabel:

'*define (ine32 m) ,(
add word ptr 'mID], 1
ade word ptr tm[2], D
292066-26

1-424

inter

AP-331

;;;;;I;;;i;;;II;;;;;;;;;;;;;;;

Data Structures
iii;;;;;;;;;;;;;;;;;;;;;;;;;;;
ECBStructure struc
Link
dd 0
ESRAddress
dd 0
InUseFlag
db 0
CompletionCode
db 0
SocketNumber
dw 0
IPXWorkspace
db 4 dup (0)
Transmitting
db 0
DriverWorkspace db 11 dup (0)
ImmediateAddress db 6 dup (0)
dw 1
FragmentCount
FragmentDescriptorList db 6 dup (1)
ECBStructure ends
FragmentDescriptor struc
FragmentAddress dd
FragmentLength
FragmentDescriptor ends

?

rx_buf_structure strue
rx_dest_addr
rx_source_addr
rx-physical_Iength
rx_checksum
rx_length
rx_tran_eontrol db 1
rx_hdr_type
rX_dest_net
rx_dest_node
rX_dest_socket
rx_source_net
rx_source_node
rx_source_socket dw 1

dw ?

db6 dup (1)
db 6 dup (1)
dw 1
dw
dw 1
db 1
db4
db 6
dw
db 4
db 6

dup
dup

(1)
(1)

dup (1)
dup (7)

rx_buf_strueture ends
tei_status strue
statusO db
db
statusl db?
db1
bc_Io
db1
bc_hi
db 1
tci_status ends

db
db 1

292066-27

1-425

inter

AP-331

ipx_header_structure struc
checksum
dw
packet_length
dw
transport_control
db
packet_type
db 7
destination_network
db 4 dup (7)
destination_node db 6 dup (7)
destination_socket
dw 7
source_network
db 4 dup (7)
source_node
db6 dup (7)
source_socket
dw ?
ipx_header_structure ends

CGroup group Code, mombo_init
assume cs: CGroup, ds: CGroup
Code

segment word public 'CODE'
public
public
public
public
public
pubUc
public
public
public

DriverSendPacket
OriverBroadcastpacket
Dri~erOpenSocket

DriverCloseSocket
DriverPoll
DriverCancelRequest
DriverOisconnect
SDriverConfigurstion
DriverISR

public LANOptionNams
extrn
extrn
extrn
extrn
extrn
extrn
extrn
extrn

extrn
extrn
extrn

IPXGetECB: NEAR
IPXReturnECB: NEAR
IPxReceivePacket: NEAR
IPXRece1vePacketEnabled: NEAR
IPXHoldEvent: NEAR
IPXServiceEvents: NEAR
IPXlntervalMarker: word
MaxPhysPacketS1ze: word
ReadWritecycles: byte
IPXStartCriticalSection: NEAR
IPXEndCriticalSection: NEAR

292066-28

1-426

inter

AP-331

Define Hardware Configuration
ConfigurationID db 'NetWareDriverLAN WS
SDriverConfiguration LABEL byte
db 4 dup (0)
db 6 dup (0)
db 0
db 0
address is determined at initialization
node_addr_type
dw 1024 I largest read data request wi~l handle (512, 1024, 2048, 4096)
max_data_size
dw LANOptionName
lan_desc_offset
db 'LanType
lan_hardware_id
dw 1

transport_time

; transport time

db 11 dup (0)
reserved_3
db tMajorVersion
major_version
db tMino'rVersion
minor_version
dbO
flag_bits
selected_configuration db
; board configuration '(interrupts, 10 addresses, etc.)
number_of_configs
db 10
config-pointers
dw CFGO, CFG1. CFG2, CFG3, CFG4
dw CFG5, CFG6, CFG7. CFG8, CFG9
LANOptionName

'db' Intel '
db 'Non Buffered Master'
db' (For Evaluation Only)'
db' VtMajorVersion.tMinorVersion'
db ' (tVersionDate)'
db O. ' $'

Hardware Setting table ,structure

HardwareStructure struc
dw
H_IOBase
dw
H_IOLength
dd
H_Auxl
tif (tV2_1) then (
db
)fi
H_RAMsegment
dw
dw
H_RAMSize
Uf (tv2_1) then (

unsigned

db

)fi

H_Aux2
H_IRQUsedFlag
H_IRQ
"_Aux3
H_DMAOUsedFlag
H_DMAO

dd
db
db
dw
db
db
292066-29

1·427

inter

Ap·331

H_DMA1UsedFlaq db ?
H_DMAl
db ?
'if ('V2_11 then
H_Flaql
db ?
H]laq2
db
If!
H_Descrlptlon db
HardwareStructure ends

'*deflne(CFG(pl,p2,p3,p4,ml,m2,m3,m4,11,12,13,14,dl,d2,d3,d4,fl,f2,msql) ( label byte
dw 'pl, 'p2, -'p3, tp4
tif (tV2_1I then ( db 0 ) £1
dw 'ml
dw 'm2 * 16 I f !
tif (tV2_01 then
dw tm2 If!
tif ('V2_11 then
tif ('V2_1) then ( db 0 I fi
dw 'm3
tif (tV2_01 then ( dw tm4 * 16
f!
f!
tif ('V2_11 then I dw tm4
db '11, '12, '13, '14, 'dl, td2, 'd3, 'd4
tif I"V2_11' then ( db tfl, U2 ) f!
''If ('pl ne 01 then (
db 'I/O Base - "pl'
'if l"p3 ne 0) then
db ' and tp4'
If!
'If (Itm2 ne 0) or (tl1 ne 0) or ,"dl ne 0» then (
db "
)£1

f!
'If '''m2 ne 0) then ,
db 'RAM Base - tml'
'If l'm4 ne 01 then (
- db ' and 'm3'
)f!
'if «'11 ne 01 or ,'dl ne 01) then (
db '
) fi
)f!
'If I'il ne 0) then (
db ' INT - t12'
'If ,'i3 ne 0) then
db ' and \14'
)£1

'if Itdl ne 0) then
db "
If!
)f!
292066-30

1-428

AP·331

tif (tell ne 0) then (
cIb ' DMA = tel2'
tif (tel3 ne 0) then
elb ' anel 'el4'
) fi
f1

elb 'msq,

CFGO
CFG1
.CFG2
CFG3
CFG4
CFG5
CFG6
CFG1
CFGS
CFG9

°

flaqs
Memory Int
DMA
I/O
tCFG(300h,16,O,O,O,0,O,O,-1,lO,O,O,-l,6,O,O,O,0,")
tCFG(310h,16,O,0,0,O,O,0,-l,ll,O,0,-1,1,O,O,0,0,")
tCFG(300h,16,0,O,0,0,O,O,-1,12,0,O,-1,5,O,O,0,O,")
tCFG(310h,16,O,0,0,0,0,O,-1,14,0,O,-1,6,0,O,0,O,")
tCFG(300h,16,O,0,0,0,0,0,-1,15,0,0,-1,1,O,0,O,0,")
tCFG(310h,16,O,0,0,0,0,0,-1,10,0,0,-1,5,0,0,0,0,")
tCFG(300h,16,O,O,O,0,0,0,-1,11,0,0,-1,6,0,0,0,0,")
tCFG(310h,16,0,0,0,0,0,0,-1,12,0,0,-1,1,0,0,O,O,")
tCFG(300h,16,O,0,O,O,O,O,-l,14,O,0,-1,5,O,0,O,O,")
tCFG(310h,16,O,O,O,O,O,O,-1,15,O,O,-l,6,0,O,O,O,")

even

;*********************************************************

Error Counters

i-*----*·**-----*-*---**-**·_-*------_· __ ·_*· __ ·_*------Public DriverDiaqnosticTable, DriverDiaqnosticText

DriverDiaqnosticTable LABEL byte
elw DriverDebuqEnel-DriverDiaqnosticTable
DriverDebuqCount
cIb tMajorVersion, 'MinorVersion
DriverVersion
cIb 01, 00
StatisticaVeraion
elw 0, 0'
TotalTxPacketCount
elw 0, a
TotalRxPacketCount
elw a
NOECBAvailab1eCount
not useel
elw -1
PacketTxTooBiqCount
not useel
PacketTxTooSmallCount elw -1
PacketRxOverflowCount elw a
elw a
PacketRxTooBiqCount
PacketRxTooSmallCount elw a
not useel
PacketTxMiscErrorCount elw -1
PacketRxMisoErrorCount elw
elw 0
RetryTxCount
I not useel
elw -1
ChecksUmErrorCount
HarelwareRxMismatchCount elw 0
NumberOfCustomVariables elw (DriverDiaqnosticText-DriverDebuqEnel1)/2

°

DriverDebuqEnel1 LABEL byte
292066-31

1-429

intJ

AP-331

I;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Driver Specific Error counts
i;;:;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;ll:

false_59a int
no_ers
no_ets

-

lost_rx

MaxCollisions
no_59a_int
rx_buff_ovflw
ten_cent latch_crash
tx_timeout
underruns

-

.dw
dw
dw
dw
dw
dw
dw
dw
dw
dw

a
a
a
a
a
a
a
a
a
a

DriverDiaqnosticText LABEL byte

db
db

'False59alnterruptCount',
' LostCRSCount' , 0
'LostCTSCount' , a
'LostOurRecelverCount', 0
, MaxCollisionsCount', 0
'No590InterruptCount', a
'ReceiveBufferOverflow',a
, TencentLatchCrashCount',
, TxTimeoutErrorCount', a
'UnderrunCount', a

db

a, a

db
db
db
db

db
db
db
db

a

a

DriverDebuqEnd LABEL word
even

I;;;;;;;;;;;;;;;;;;;

Equates
I;;;;;;;;;;;;;;;;;;;

CR
LF

equ ODh
equ aAb

TransmitHardwareFailure equ aFFh
Packet UnDeliverable
equ OFEh
equ OFDh
PacketOverflow
equ OFAb
ECBProcessinq
equ 10
TxTimeOutTicks
Adapter I/O ports
Addr592
IA_PROMyort
AddrLatchLow
AddrLatchHiqh
LimitReqister

dw
dw
dw
dw
dw

aSh
aah
ach
Odh
Oeh

+
+
+
+
+

IOBase
IOBase
IOBase
IOBase
IOBase

(I/O)
(I)

(I)
(I)
(I/O)
292066-32

1-430

inter
8259

AP-331

definitions

InterruptControlPort
equ
InterruptMaskPort
equ
ExtralnterruptControlPort
equ
ExtralnterruptMaskPort
equ
EOI
egu 020h

020h
021h
OAOh
OAlh

8237 definitions
; Command Register
RotatingPriority
ExtendedWrite
ActiveLowDREQ

equ OlOh
equ 020h
equ 040h

; Mode Register
WriteTransfer
ReadTransfer

AutoInitialization
DemandMode
CascadeMode

equ
equ
equ
equ
equ

OOOOOlOOb
OOOOlOOOb
OOOlOOOOb
OOOOOOOOb
llOOOOOOb

even

OOlh
005h
007h
009h

+
+
+
+

IOBase (I/O)
IOBase (0)
IOBase (0)
IOBase (0)

DMAcmdstat
DMAsnglmsk
DMAmode
DMAff

dw
dw
dw
dw

XmtDMApage
XmtDMAaddr
XmtDMAwdcount

dw OOah
dw OOOh
dw 002h

+ IOBase (0)
+ IOBase (I/O)
+ IOBase (I/O)

RcvDMApage
RcvDMAaddr
RcvDMAwdcount

dw OOch
dw 004h
dw 006h

+ IOBase (0)
IOBase (1/0)
+ IOBase (I/O)

MasterDMAcmdstat
MasterDMAsnglmsk
MasterDMAmode
MasterDMAff

equ
equ
equ
equ

MasterDMApage
MasterDMAaddr
MasterDMAwdcount

dw
dw OcOh
dw Oc2h

XmtDMAtx
XmtDMAmsk
XmtDMAunmsk

db DemandMode + AutoInitialization + ReadTransfer
db 4
db 0

RcvDMArx
RcvDMAmsk
RcvDMAunmsk

db DemandMode + AutoInitialization + WriteTransfer + 1
db 4" + 1
db 0 + 1

ODOh
OD4h
OD6h
ODSh

292066-33

1-431

inter-

Ap·331

MasterDMAmodevalue
MasterOMAmsk
MasterOMAunmsk

db CascadeMode
db 4
db 0

82592 commands
C_NOP
equ OOh
C_SWP1
equ 10h
equ OFh
C_SELRST
C_SWPO
equ 01h
C_IASET
equ 01h
C_CONFIG
equ 02h
C_MCSET
equ 03h
equ 04h
C_TX
C_TDR
equ 05h
C_DUMP
equ 16h
equ 07h
C_DIAG
equ 18h
C_RXENB
C_ALTBUF
equ 09h
equ lAb
C_RXOISB
C_STPRX
equ 1Bh
equ OCh
C_RETX
C_ABORT
equ OOh
equ OEh
C_RST
equ OFh
C_RLSPTR
equ 1Fh
C]IXPTR
C_INTACK
equ 80h
I;;;;;;;;;;;;;;;;;;;;;;;;;;

Variables
;;;;:;;;;;;;;;;;;;;;;;:;;;;
even

gp buf size
equ 600
in words
max_rx_buf_size equ 2200
in words
gp_buf
dw gp_buf_size + max_rx_buf_size dup (1)
gp_buf-pointer dd 1
gp buf start
dw
A1-A16 of General Purpose Buffer EA
gp_buf-page
dw ?
A17-A23 of General Purpose Buffer EA
tx_byte_cnt
dw 1
IPX packet length plus header length
rx_buf_start
dw 1
A1-A16 of Receive Buffer EA
rx_buf-page
dw
A17-A23 of Receive Buffer EA
rx_buf_head
dw ?
current rx head, buffer has been flushed to here
rx_buf_taU
dw 1
value read from 10 cent latches
rx_buf_length dw
word size of rx_buf
rx_buf_segment dw 1
calculated at init-for use by IPXReceivePacket
rx_buf_first
dw ?
offset from rx_buf_segment of start of rx_buf
rx_buf_limit
dw
offset from rx_buf_segment of limit of rx_buf
rx_buf_size
dw ?
byte size of rx_buf
Logica12Physical dw ?
add this to convert from rx_buf_segment to rx_buf-psge
rx_list
dw 30 dup (1)
292066-34

1·432

inter

AP-331

paddinq
SencIList
tx Btart_time
tx_active_flaq

dw ?
dd 0
dw 0
db 0

paints to list of ECBs to be sent

.;***************************************************.**************

Interrupt Procedure
;*t _____ ** _______ * ___

*_______ ***_* ______________

*. ___

***************

even

DriverISR PROC far
pusha
push ds
push es
may ax, cs

DS points to C/DGroup
ES also

mov ds, ax
moves, ax

mav al, EOI
aut InterruptControlPart, al
out ExtraInterruptContralPart, al
mav dx. Addr592
may al, 0
set status req to paint to req 0
out dx, al
'slow
in al, dx
test al, BOh
Ufz
590 int
inc no
,
'else
'do
iqnare the EXEC bit
and al, NOT 20h
save the status in AU
maY ah, al
did I receive a frame?
cmp ah, ODBh
Ufe
call RcvdPacket
'else
did I finish a transmit?
cmp ah, B4h
'He
call SentPacket
'else
cmp ah, Bch ' 1 did I finish a retransmit?
Ufe
call SentPacket
'elae
inc falae_590_int ; unwanted interrupt
tendH
'endif
'endH

-

292066-35

1:433

AP-331

push cs
pop ds
cmp tx_active_flag, false
tife
: verify that our receiver is still going.
mov dx, Addr592
mov al, 60h
: point to status byte 3
out dx, al
blow
in .. 1, dx
test'al, 60h
Ufz

inc
mov
mov
out
hndif
'endif

lost_rx
al, C_RXENB
dx, Acidr592
dx, al

mov dx, Addr592
mov al, C_INTACK
out dx, al
blow
xor al, al
out dx, al
hlow
in al, dx
test al, BOh
hhUenz
tendif

issue interrupt acknowledge to the 590

set status reg to point to reg 0

call IPXServiceEvents
pop es
pop ds
popa
iret
DriverISR endp
even

RcvdPacket proc near
When the address bytes are being read it is possible that·
another frame could come in and cause a coherency problem
with the ten-cent latches. I .. m dealing with this
possibility by reading AcidrLatchHigh twice and making
sure the'values match. If they don't the read is redone.
cli
mov dx, AddrLatchHigh
read high address byte of last frame received
in al, dx
292066~36

1·434

Ap·331

'do
save it in bh
mov bh, al
read low address byte of last frame received
mov dx, AddrLatchLow
in al, dx
mov bl, a1
; Read AddrtatchHigh again to make sure it hasn't changed •••••••
mov dx, AddrtatchHigh
; read high address byte again
in al, dlt
cmp a1, bh
'lwhilene
shl bx, 1
; convert to byte address
sub bx, Logical2fhysical I bx - magic - physical - (physical-logical)
logical
this is the last location contai,ning rlt data
mov ai, bx
normalize si
call Norma1izefointer
was it already a valid pointer 1
bx, a1
if not, big trouble •••
Ufne
inc ten cent latch_crash
'elsel
'do
moves, rx_buf_segment
mov ch, ea: [ail
get bc_hi
sub si, 2
call Normalizefointer
mov cl, es: [si]
aub si, 2
call NormalizePointer
get statual
mov ah, es: [ail
sub si, 2
call Norma11zePointer
; get atatuaO
mov a1, es: [si]

cmp

I cx haa actual number of bytes read
dec cx'
; toss byte count , atatus
round up
and c1, Ofeh
si points to first location of frame
Bub si, ex
call Normal1zePo1nter
aave in bx
mov bx, a1

test for good receive
bad receive
inc facxetRxH1acErrorCount
jmp ahort Sk1pThiaFrame
good rece1ve
telidif

test ah, 20h

'lfz

sub cx, 14
cmp cx, 1024 + 64

sub length of 802.3 header

Ufa
inc PacketRxTooBigCount
jmp short SkipThisFrame
'endif
292066-37

1-435

intJ

AP-331

cx, 30
Ufb
inc PacketRxTooSmallCount
jmp short SkipThisFrame
'endif

Chip

lea si, [bx].rx_length
call NormalizePointer
mov ax, es: [si]
get IPX length
xchg al, ah
inc ax
and al, Ofeh
xchq al, ah
lea 8i, [bx].rx-physical_length
call NormalizePointer
cmp ax, es: [si]
; same as 802.3 lenqth
Ufne
inc HardwareRxHismatchCount
jmp short SkipThisFrame
'endif
xchg al, ah
at least min lenqth minus header
cmp ax, 60 - 14
tifbe

mov ax, 60 - 14
'endif

DO,

round up

match physical lenqth
cmp ax, ex
'ifne
inc HardwareRxHismatchCount
'else
mov di, num_of_frames
add di, di
mov rx li.t[dil, bx ; first location of ethernet frame
cinc num_of_frames
cmp num_of_frames, length rx_list
je hand_off-packet
.endif
Sk!pThisFrame:
movai, bx
cmp rx_buf_head, ai
first frame of sequence 1
yes, go process list
je hand_off-packet
sub si, 2
call NormalizePointer
• forever
no, continue processing frames
hand_off-packet:
~end1f

cli
mov di, num_of_frames
add di, di
Ufnz
'do
sub di, 2
mov ai, rx_list'(dil
lea si, [si].,rx_dest_socket
292066-38

1-436

intJ

AP-331

call NormalizePointer
maves, rx_buf_segment

mov ax, es: (si)
call IPXGetECB
Ufnz
call DeliverPacket
hndif
dec num_of_frames
'whilenz
'endif
; update the limit reqister
mov dx, LimitReqister
1n al, dx
test aI, 1

\ifnz
inc rx_buff_ovflw
hndif
mov si, rx_buf_tail
sub 31, 256
call NormalizePo1nter
mav ax, 51
add ax, Loqical2Physical
mov al, ah
out dx, al

just for the record

move new limit value to ax
convert to physical address
only need bits Al5 •• A8
store it in the limit reqister

mav 51, rx_buf_tall

add si, 2
call Normal1zePointer
mov rx_buf_head, 8i
ret

set rx_buf_head to new value for next receive

RcvdPacket endp
even

DellverPacket proc near
push di
mav di, rx_list[di)
mov bp, si
xchq si, di

copy ecb offset to bp
es:di
ecb
ds:s! - packet

may ds, rx_buf_segment

assume ds: noth1nq
add d, 6
lea d1, (d1).Immed1ateAddress
call NormalizePointer
movsw
call NormalizePointer

skip destination address

movsw

call NormalizePointer
movsw

add si, 4
call NormalizePointer
mov dx, ds: (si)

; skip etype and checksum
; qet lenqth from IPX header
292066-39

1-437

AP-331

xchq dh, dl
sub si, 2
call NormalizePointer
moy di, bp·

point to checksum

disburse the packet
ds:si = packet data source
es:bp - ECB
ax
fraqment count
dx
- amount of data in source
bx
- pointer to the FraqmentDescriptorList
cx
= size of this fraqment
moy cx, es: [bp).FraqmentCount
lea bx, [bp).FraqmentDescriptorList
'do
push es
push cx
moy cx, es: [bx].FraqmentLenqth
les di, es: [bx).FraqmentAddress
moy ax, rx_buf_l1mit
sub ax, si
cmp ax, ex
lifb
xchq cx, ax
cx = amount to copy
sub ax, ex
ax - amount not copied
cmp dx, cx
Ufb
moy ex, dx
'endif
sub dx, ex
'fastcopy
moY si, rx_buf_first
mov ex, ax
tendif
cmp dx, cx
Uib

mov ex, dx
tendif
sub dx, cx
'fastcopy
pop cx
pop es
add bx, 6
Uoop
292066-40

1~438

inter

AP-331

; deliver the ECB
mov si, bp
moves: [sij.CompletionCode, 0
push cs
pop ds
assume ds: CGroup
'inc32 TotalRxPacketCount
call IPXHoldEvent
pop di
ret
DeliverPacket endp

even

input:
si = pointer into rx_buf
output:
si a valid pointer into rx_buf
no other registers modified
NormalizePointer proc near
cmp si, cs:
Ufae
cmp si,
tifb
ret
%endif
sub si,
ret
tendif
add si, cs:
ret

rx_buf_first
cs: rx_buf_limit

cs: rx_buf_size

rx_buf_size

NormalizePointer endp
even
SentPacket proc near

eli
cmp tx_active_flag, true
tHe
in al, dx
mov ah, al
hlow
in aI, dx
xch9 ah, al
test ah, 20h
Ufz
292066-41

1·439

AP-331

Max collisions?1
test al, 20h
Ufnz
inc MaxCollisions
'endif
test ah. Olh
Tx underrun?1
Ufnz
inc underruns
'endif
did we lose clear to aend??
test ah. 02h
Ufnz
inc no_cts
\endif
did we lose carrier sense??
test ah. 04h
Ufnz
inc no_crs
'endif
may al, TransmitHardwareFailure
'else
; extract the total number of retries from the status
and ax. OFh
register and add to retry count
add RetryTxCount. ax
xor ax, ax
status - O. good transmit
'endif
may cx. word ptr SendList[2]
'ifcxnz
segment of next sca in list
offset of next sca in list
mov si, word ptr SendList[O]
cmp es: [si].Transmitting. true I if not canceled
Ufe
mayes: [si].CompletionCode. al
movax. ea: word ptr [si].Link[O]
mav ward ptr SendList[O]. ax
moyax. e8: word ptr [si].Link[2]
moY word ptr SendList[21. ax
; finish the transmit
moves: [si].InUaeFlag. 0
call IPXHoldEyent
'endif
'endif

mav 8a, ex

mav tx_actiye_flag. false
may cx. ward ptr SendListl2]
'ifcxnz
segment of next sca in list
mav ea, ex
offset of next sca in list
maY si. word ptr SendList[O]
call StartSend
'endif
tendif
ret
Sent Packet endp .

292066-42

1·440

intJ

Ap·331

Driver Send Packet
Driver Broadcast Packet
Assumes

es: 51 points too a fully prepared Event Control Block
DS - CS
Interrupts are DISABLED but may be reenabled temporarily if necessary
don't need to save any reqisters
even

DriverBroadcastPaeket:
DriverSendPacket PROC NEAR
moves: [sil.Transmitting. false

mov cx. word ptr SendList[2)
Ufcxnz
; search to the end of the list. and add. there.
mov di. word ptr SendList[Ol
'do
mov ds, ex
mov cx. ds: word ptr [dil.Link[21
jcxz AddListEndFound
mov di. ds: word ptr [d11.Link[Ol
'forever

AddListEndFound:
mov es: word
mov es: word
mav ds: word
mov ds: word
mav ax. es
mov ds. ax
ret
'endif

ptr
ptr
ptr
ptr

[sil.Link [01.
[sil .Link [2).
[di).Link[O).
[dl).Llnk[2).
;

move null pointer to newest SCB's
l1n~ field

cx
ex
si
es

set ds back to entry condition

moves: word ptr[si).Link[O). cx
moves: word ptr[si).Link[2). cx
mov word ptr SendList[O). s1
mov word ptr SendL1st[21. es
; drop through to Start Send
DriverSendPacket endp

Start Send
assumes:

es: SI
points to the ECB to be sent.
interrupts are disabled
292066-43

1-441

inter

AP-331

even

StartSend PROC NEAR
old
moves: (si].Transmittinq, true
push ds
I save ds for future use
I qet IPX packet le~qth out of the first fraqment (IPX header)
lds bx, es: dword ptr (si].FraqmentDescriptorList
mov ax, ds: (bx].packet_lenqth
; restore ds to CGROUP
pop ds
save lenqth for later use in 590 lenqth field
push ax
byte swap for 592 lenqth field calculation
xchq al, ah
add in the overhead bytes DA, SA, CRC, lenqth
add ax, 18

I

mov paddinq, 0
cmp ax, 64
Ufb
minimum lenqth frame
mov paddinq, 64
pad lenqth
sub paddinq, ax
moV ax, 64
tendif
sub ax, 10
SA and CRC are done automatically
inc ax
and al, OFEh
frame must'be even
mov tx_byte_cnt, ax
lea ~:. qp_buf-pointer
I move the byte count ~nto the transmit buffer
stosw
I move the destination address from the tx ECB to the tx buffer
mov bx, si
lea si, [bx].ImmediateAddress
mov dB, word ptr SendList[2]
movsw

movsW
mOVSN

mav ax, cs

qat'back to the code (Dqroup) section

mov dB, ax

; now the 590 lenqth field
pop ax
xchq ah, al
inc IIX
make sure E-Net lenqth field is even
and al, OFEh
xchq ah, al
stosw
lds si, SendList
movax, ds: (ai].FraqmentCount
lea bx, [ail .,FraqmentDescriptorList
'do
push ds,
; save the seqment
mov cx, ds: [bx].FraqmentLenqth
lds si, ds: [bx].FraqmentAddress
Hastcopy
pop ds
; qet the seq~nt back
292066-44

1-442

AP-331

add bx,
dec ax
'whllenz
; start transmitting
mov ex, cs
mov ds, ex

; add any required padding
; make sure frame ends with a NOP
add cx, padding
shr cx, 1
rep stosw
mov tx_active_flag, true

mav ex, 4

mov dx, DMAff
out dx, al
mov
mov
out
mov
out

dx,
al,
dx,
al,
dx,

data is don't care

XmtDMAaddr
byte ptr gp_buf_start[Oj
al
byte ptr gp_buf_start[lj
al

mov ax, gp_bufJ>age
mav dx, XmtDMApage
out dx, al

DMA page value

mov al, XmtDMAtx; setup ohannel 1 for tx mode
mov dx, DMAmoda
out dx, al
ax, tx_byte_cnt
ax
ax, 1
dx, XmtDMAwdcount
out dx, al
hlow
mav d, ah
out dx, al

mov
inc
shr
mov

convert to word value and account for odd
byte DMA transfer

mov al, XmtDMAunmsk
mov dx, DMAsnglmsk
out dx, al
mov dx, Addr592
mov al, C_TX
out dx, al
mov ax, IPXIntervalMarker
mov tx_start_time, ax
tinc32
TotalTxPacketCount
ret
StartSend endp
292066-45

1-443

AP-331

DriverOpen5Dcket:
DriverDiscDnnect:
ret
;**********************************************************************

DriverpDll
PDll the driver to, see if there is anything to, do,
Is there a transmit timeDut? If so" abDrt transmissiDn and return
ECB with bad cDmpletiDn cDde. Check to, see if frames are queued.
If they are set up es: 51 and call DriverSendPacket.
;**********************************************************************

even

DriverPDll PROC NEAR
cmp tx_active_flag, true
Ufe

mDv dx, IPXIntervalMarker
sub dx, tx_start_time
cmp dx, TxTimeOutTicks

tHa
This transmit is taking tDD IDng
mDV tx_active_flag, false
1

; Issue
mDV dx,
mDV al,
Dut dx,

so,

let's terminate it nD,w

an abDrt to, the 82592
Addr592
abDrt transmit'
C_ABORT
al

inc tx_timeout
mDV cx', wDrd ptr SendList [2]
tifcxnz
mav es. ex
segment of next 5ca in list
mov si, word ptr 5endList[O)
offset of next sca in list
cmp es: (ai).Transmitting, true
if not canceled
Ufe

moves: [si].CDmpletionCode, TransmitHardwareFailure
mDvax, es: wDrd ptr [si).Link[O)
mov wDrd ptr 5endLiat(0), ax
mDvax, es: wDrd ptr [si).Link[2)
mDV wDrd ptr SendL1st[2], ax

stuffcDmpletion cDde Df
a f~iled tx

; Finish the transmit
mOVes: [si).InUseFlag, 0
call IPXHDldEvent
tend i f
'endif
292066-46

1-444

inter

Ap·331

; make sure that execution unit didn't lock up because of abort errata
mov dx, Addr592
mov al, C_SlIPl
out dx, al
mov al, C_SELRS'l'
hlow
out dx, al
mov al, C_SIIPO
hlow
out dx, al
mov al, C_RXENB
'slow
out dx, a1
: See if any frames are queued
mov ex, word ptr SendList[2]
Ufcxnz
moves, cx
: segment of next SCB in list
mov si, word ptr SendList[O] ; offset of next SCB in list
call StartSend
hndif
hndif
tendif
ret
Dri verPoll endp

Driver Cancel Request
Assumes on entry:
es: SI is pointer to ECB we want to cancel
DS is setup
Interrupts are DISABLED
Assumes any registers may be destroyed.
Returns completion code in ALI

00
FF

Buffer was located and canceled.
Buffer was not found to be in use by the driver

even

DriverCancelRequest proc near
: first, see if it is the one we are currently sending.
mav dx, es

cmp word ptr SendL1st[0], s1
Ufe
cmp word ptr SendList[2], dx
Ufe
we need to cancel tbe first entry.
from the send list.
movax, es: word ptr [si].Link[O)

first, unlink it

292066-47

1-445

inter

AP~331

mov word ptr SendList[O). ax
mov ex. es: word ptr [si).Link [2)
mov word ptr SendList[21. ex
mov e8: [si).CompletionCode. OFCh
mov es: [si).InUseFlag. 0
xor ax. ax
ret
\endif
'endif
; we need to search down the send list
movex. word ptr SendList[2)
mov di. word ptr SendList(O)
'do
'do
jexz Not Found
; move to the next link
mov ea, ex
mov bx. di
movex. es: word ptr [bx).Link(2)
mov di. es: word ptr (bx).Link(O)
next node is pointed to by CX:DI
; previous node is pointed to byes: BX
; see if we found it
emp di. si
hhUenz
cmp ex. dx
hhUen,z
; we found it. now unlink it.
push ds
mav ds, ex
movax. ds: word ptr (si).Link(O)
moves: word ptr (bx).Link(O). ax
movax. ds: word ptr [si).Link(2)
moves: word ptr [bx).Link(2). ax
mov ds: (si).CompletionCode. OFCh
mov ds: [si).InUseFlag. 0
pop ds
xor ax, a~
ret
NotFound:
mov al. OFFh
ret
DriverCaneelRequest endp
292066-48

1-446

intJ

AP-331

Driver Close Socket
Assumes on entry:

DX has socket number
DS is setup
Interrupts are DISABLED
Assumes any registers may be destroyed.

even

DriverCloseSocket proc near
mov cx. word ptr SendList[2]
jcxz DriverCloseExit
les si. SendList
~do

cmp es: [si].SocketNumber. dx
Ufe
push dx
call DriverCancelRequest
pop dx
jmp DriverCloseSocket
~endif

mov cx. es: word ptr lsi] .Link[2]
jcxz DriverCloseExit
les si. es: [si].Link[O]
Horever
DriverCloseExit:
ret
DriverClosesocket endp

Code

ends

mombo_init

~egment

'CODE'

public Driverlnitialize,
no_card_message
db CR,
config_failure_messagedb CR.
iaset_failure_message db CR,

DMAPageRegisters
con fig_block
dw 15
db 48h
db BOh
db OOlOOllOb

DriverUnHook
LF, 'No adapter installed in PC$'
LF. 'Configuration Failure$'
LF. 'IA Setup Failure$',

6
7
5
1
2
3
db 87h, 83h. 81h. 82h. Bfh. Bbh. 89h. 8ah

2:
3:

; 0 •• 1: byte count
High-Speed Mode. Fifo Limit - 8
TCI mode

4:
292066-49

1-447

AP-331

db
db
db
db
db
db
db
db
db
db
db
db
db

OOh
96
OOh
OF2h
OOOOOOOOb
OOh
64
1111011lb
OOh
3Fh
87h
ODOh
OFFh

5:
6:

Interframe Spacing

7:
8:
9:

10:'
11:

12:
13:
14 :
15:
16:
17:

Minimum Frame Size
Auto Restransmit

db
db

InterruptB1t
InterruptMask
even

dd 1
OldIRQVector
InterruptMaskRegister dw 1
InterruptVectorAddress dd

Driver Initialize
assumes:
DS, ES are set to CGroup (-- CS)
DI points to where to stuff node address
Interrupts are ENABLED
The Real Time Ticks variable is being set, and the
entire AES system is initialized.
returns:

If initialization is d~ne OK:
AX has a 0
If board malfunction:
AX gets offset (in CGroup) of '$'-terminated error string

DriYerInitialize PROC NEAR
moy MaxPhysPacketSize, 1024
cld
c11
; initialize the configuration table
mov al, selected_configuration
cbw
shl ax, 1
; multiply by two
mov bx, ax
moY bx, config-pointers/bx]
mov ax, [bx] .R_IOBase
add Addr592, ax
add AddrLatchLow, ax
add AddrLatchRigh, ax
292066-50

1-448

. AP-331

add
add
add
add
add
add
add
add
add
add
add
add

L!m!tRegister, ax
DMAcmdstat, ax
DMAsnglmsk, ax
DMAmode, ax
DMAff, ax
XmtDMAaddr, ax
XmtDMAwdcount, ax
XmtDMAPage, ax
RcvDMAaddr, ax
RcvDMAwdcount, ax
RcvDMAPaqe, ax
IA_PROM-port, ax

; setup the dma registers
moval, [bxJ.H_DMAO
cbw
mav si, ax

mov cl, DMAPaqeReqisters[siJ ; qet the page register address
xor ch, ch
: save it
mov MasterDMAPage, ex
and
add
add
add
add
add

aI, 03h
MasterDMAmsk, al
MasterDMAunmsk, al

MasterDMAmodevalue, al
ax, ax
ax, ax
~dd MasterDMAaddr, ax
add MasterDMAwdcount, ax
; load the node address
lea si, node_addr
xor ax, ax

tarqets are es:s! and es:di
ah = prom address

mav ex, size node_addr

'do
mov al, ah

mov dx, L1m1tReg1ster
out dx, al
mov dx, IA_PROM-port
in aI, dx
stosb
xchg si, di
stosb
inc ah
Hoop

set prom address

read prom value
store it at es:di .
and at es:s!
increment prom address

SET UP THE INTERRUPT VECTORS
moval, [bxJ.H_IRQ
mov bx, OFFSET CGroup: Dr!verISR
call Set Interrupt Vector
292066-51

1-449

intJ

AP-331

mov dx, Addr592
mov aI, C_RST
; reset the 82592 controller

out dx, a1

qenerate 20 bit address for DMA controller from
configure block location this is necessary to
accomodate the paqe reqiater used in the PC DMA
call SetUpBuffers
; configure the master channel for cascade mode
mov al, MaaterDMAmak
mov dx, MasterDMAsnq1msk
out dx, al

disable the channel

mov aI, MasterDMAmodevalue
mov dx, MasterDMAmode
out dx, al

qet the mode reqister address
set the mode

mov ai, MasterDMAunmsk
mov dx, MasterDMAsnqlmsk
out dx, a1
; set up DMA channel for
mov al,

; enable the channel
confiqu~e

command

XmtD~sk

mav dx, DMAsnqlmsk

out dx, al

disable the channel

mav a1, RcvDMAmsk
mov dx, DMAsnqlmsk
out dx, al

disable the channel

mov dx, DHAFF
out dx, a1

; data is 'don't care

mov al, ActlveLowDREQ + ExtendedWrlte + RotatinqPriority
mov dx, DMAcmdstat
out dx, a1

mov
mov
out
mov

dx,
aI,
dx,
a1,

XmtDMAaddr
byte ptr qp_buf_start[OJ
a1
byte ptr qp_buf_start[l]

out dx, a1

mov ax, qp_bufJ'aqe
mov dx, XmtDMApaqe
out dx, al

DMA paqe value

mov ax,
mov dx, XmtDMAwdcount
out dx, al

make two transfers
292066-52

1-450

inter

AP·331

mov a1, ah

hlow
out dx, 0.1
maY 0.1, XmtDMAtx
maY dx, DMAmode
out dll, al

setup tll mode

may al, XmtDMAunmsk
may dll, DMAsnglmak
out dll, al
maY zeroes into the byte count field
of the buffer to put the 82592 into
16 bit made

les di, gp_buf.J'ointer
stosw
stosw

may dx, Addr592
may al, C_CONFIG
out dx, 0.1

configure the 82592 for 16 bit made
; issue configure command

hlow
xor ex, ex
'do
xor 0.1, al
point to register 0

out dx, 0.1

hlow
al, dx
in
and al, ODFh
emP al, 82b
%!oopne

read register 0
disregard exec bit
is configure finished1

Ufne
maY ax, OFFSET CGroup: no_card_message
ret
hndif
maY al, C_INTACK
out dx, al
maV

clear interrupt

dx, DMAff
data 1. don't care

out dx, al

maY
maY
aut
mov
out

dx, XmtDMAaddr
al, byte ptr gp_buf_start[O)
dx, al
al, byte ptr '1P_buf_start [1)
dx, 0.1

mov ax, '1P_buf.J>age
may dx, XmtDMApage
out dx, al
maY al, XmtDMAtx
maY dx, DMAmode
aut dx, 0.1

DMA page value

setup channel 1 for tx mode

292066-53

1-451

AP-331

mov ax,
mov dx,
out dx,
'slow
mav aI,
out dx,

8

XmtDHAwdcount
a1
ah
a1

mov aI, XmtDHAunmsk
mov dx, DHAsnqlmsk
out dX', a1
mov
1es
mov
rep
mov
mov
out

8i, offset cqroup' config_b1ock
di, qp_bufJlointer
ex, 18
movsb

dx, Addr592
aI, C_CONFIG
dx, a1

xor ex, cx
'do
xor aI, a1
blow
out dx, al
blow
in aI, dx
and aI, ODFh
cmp aI, 82h
'loopne

configute the 82592

point to register 0
read register .0
discard extraneous bits
is configure finished?

Ufnz

mav ax, OFFSET CGroup, confiq_failura_messaqe
ret
'endif
; clear interrupt caused by· configuration
mov aI, C_INTACK
out dx, al
; do an lA_setup
les di, 9P_bufJlointer
add.resa byte count
mov al, 06h
stosb
mov al, COh
stosb
mov si, OFFSET CGROUP, node_addr
mov ex, SIZE node_addr
rep movsb
mav dx, DHAff
out dx, al

data is don't care
292066-54

1-452

inter
mov
mov
out
mov
out

dx,
aI,
dx,
aI,
dx,

AP-331

XmtDMAaddr
byte ptr gp_buf_startIOl
al
byte ptr 9P_buf_startlll
al

mov ax, gp_bufJlage
mov dx, XmtDMApage
out dx, al
mov aI, XmtDMAtx
mov dx, DMAmode
out dx, al
mov ax,
mov dx,
out dx,
hlow
mov al,
out dx,

DMA page value

setup channel 1 for tx mode

3

XmtDMAwdcount
al
ah
al

mov al, XmtDMAunmsk
mov dx, DHAsnglmsk
out dx, al
mov dx, Addr592
mov aI, C_IASET
out dx, al
xor cx, cx
'do
xor al, al
out dx, al
'slow
in aI, dx
and al, ODFh
cmp al, 8lh
Uoopne

set up the 82592 individual address

discard extraneous bits
is command finished?

Ufne
mov ax, OFFSET CGroup: iaset_failure_message
ret
'endif
moy al, C_INTACK
out dx, al

; clear interrupt from iaset

;initialize the receive DMA channel
mov dx, DHAff
out dx, al
mov dx, RcvDMAaddr
maY al, byte ptr rx_buf_startIOl

set dma up to point to the
292066-55

1-453

inIJ

AP-331

out dx, al
mov al, byte ptr rx buf_startI1]
out dx, al

beginning of rx_buf

set rx page register

mov ax, rx_buf-page
mov dx, RcvDMApage
out dx, ax
mov al, RcvDMArx
mov dx, DMAmode
out dx, a1
mov dx,
mov ax,
dec ax
out dx,
mov al,
blow
out dx,

RcvDMAwdcount
rx_buf_length
al
ah
al

I initialize the limit register
mov aX, rx_buf_limit
sub ax, 2
mov bx, rx_buf_seqment
shl bx, 4
add ax, bx
mov aI, ab
mov dx, LimitRegister'
out dx, a1

mov aI, RcvDMAunmsk
mov dx, DMAsnglmsk
out dx, al
I 'enable the receiver
mov dx, Addr592
mov al, C_RXENB
out dx, al

compute physical address

unmask receive DMA channel

enable receives

at!

xor ax, ax
mov cx, 1
ret
Driverlnitialize endp
292066-56

1-454

AP-331

,. __ .a ..•. __ •___ ._____ •••• _* __ • __ • __ •• _._-_._-_._ •• -.-*-*---_ .. _.----_.-.-._Set Interrupt Vector
Set the interrupt vector to the interrupt procedure's address.

Save the old vector for the unhook procedure.
assumes:

cs:bx is the ISR routine

al has the IRQ level 10 •• 15
interrupts are disabled
;** •• _-----_ •••••••••

_*----**--_._.*----*------_._----*-*-----*._-----_._.---

Set Interrupt Vector proe near

I mask on the appropriate interrupt mask
push ax
xchq ax, ex

mov dl, 1
sub
shl
mov
not
mov

cl,
dl, el
InterruptBit, dl
dl
InterruptMask, dl

in al, BxtralnterruptMaskPort
and al, dl
hlow
out BxtralnterruptMaskPort, al
mov InterruptMaskReqiater, BxtralnterruptMaskPort
; also mask on level 2 of first controller

in al, InterruptMaskPort
and al, not 4

blow
out InterruptMaskPort, al
pop ax

cld
ebw
xor ex, ex
mov ea, cx
add
shl
shl
mov

al,
ax,
ax,
di,

70h - 8
1
1
ax

mov word ptr Inter 7uptVeetorAddress[01, di
mov word ptr InterruptVectorAddress[21, as
292066-57

1-455

AP-331

mov
mov
mov
mov

ax, es: [di] [0]
word ptr OldIRQVector[O], ax
ax, es: [di] [2]
ward ptr OldIRQVector[2], ax

mav ax, bx
stosw
mav ax, c.
stos"

ret
Set Interrupt Vector endp

Set up Buffers:
This routine generates the page and offset addresses for the 16 bit
DMA. It checks for a page crossing and uses the smaller half of the
buffer area for Tx and general purpose if a crossing is detected. If
no crossing is detected the general purpose/transmit buffer is placed
at the beginning of the buffer area. This routine also generates a
segment address for the receive buffer which allows the value read
from the "10 cent" latches to be used as read for the offset passed
to IPXReceivePacket. This saves same arithmetic steps when tracing
back through the rx buffer chain.

gp_length
gp_offset_adjust

dw gp_buf_size + max_rx_buf_size
dw 0

SetUpBuffers proc near
mov
mov
mov
shr
mov
shl
rol
and
add
adc
xor
sub

ax,
bx,
dx,
ax,
cx,
bx,
dx,
dx,
ax,
dx,
cx,
cx,

offset cgroup: gp_buf
cs
cs
1

3

cl
cl
0007h
bx

get upper 3 bits for page register
clear all but the lowest 3 bits
ax contains A16 •• Al of first location in buffer
if addition caused a carry add it to page
of buffer to page break
cx contains the number of wards to page break

o
cx
ax

cmp ex,

Ufae
jmp copacetic
tendif

I

it's cool, whale buffer space is in one page
292066-58

1-456

inter

AP-331

cmp cx, 9P_buf_size
tUbe
move pointer past the paqe break to discard fraqment
adjust lenqth variable to reflect shorter lenqth
both buffers will be in the same paqe, rx buf shortened

add ax, ex

sub 9P_length, cx
jmp copacetic
'endU
cmp ex, max_rx_buf_size
Ufae
mav 9P_lenqth, cx
jmp.copacetic
'endU

adjust lenqth variable, discard upper buffer fraqment
both buffers will be 1n the same paqe, rx buf shortened

now since both fraqments are usable we have to find the
actual page break. the large half will be the receive
buffer and the small half will be the gp-tx buffer.
cmp cx, (gp_buf_size + max_rx_buf_size) I 2
, Ufbe
; transmit buffer first
mov 9P_buf-paqe, dx
mav gp_buf_start, ax
mov rx_buf_start, OOOOh
next paqe
inc dx
mov rx_buf-paqe, dx
mov ax, gp_length
sub ax, ex

mov rx_buf_lenqth, ax
'else
; receive buffer first
mav rx_buf-paqe, dx
mav rx_buf_start, ax

mov rx_buf_lenqth, cx
mav qp_buf_start, OOOOh
inc dx
mov 9P_buf-paqe, dx
'end!f
jmp SetUpBuffers_exit

next paqe

copacetic:
mav 9P_buf_start, ax
add ax, gp_buf_slze
mav rx_buf_start, ax

mov
sub
mov
mov
mav

A1-A16 of qp buffer, qp buffer 1s first
allocate qp_buf at front of buffer space
rx b~ffer starts 1200 bytes in

cx, gp_length
cx, gp_buf_size
rx_buf_length, cx
rx_buf'-page, dx

9P_buf-paqe, dx

SetUpBuffers_exit:
mov ax, gp_buf_start
mav dx, 9P_buf-paqe
shr dx, 1
rcr ax, 1

shr dx,
292066-59

1-457

inter

Ap·331

rcr ax, 1
shr dx, 1
rcr ax, 1
I ax - a19 •• a4 of gp_buf
mav dx, cs
sub ax, dx
sh1 ax, 4
mov bx, gp_buf_start
shl bx, 1
and bx, Ofh
or ax, bx
; compute offset within cgroup
mov word ptr CJP_buf-pointer[O], ax
mav word ptr gp_bufJlointer.[2], cs
mov ax, rx_buf_1ength
shl ax, 1
mov rx_buf_size, ax
mov ax, rX_buf_start
mov dx, rx_bufJlage
shl ax, 1
rc1 dx, 1
push ax
xar al, a1
mov cx, 12
'do
sh1 ax, 1
rcl dx, 1
Uoop
pop ax
mov ah, eOh
sub dx, eOOh
mav rx_buf_segment, dx
mov rx_buf_first, ax
mov rx_buf_head, ax
add ax, rX_buf_size
mav rx_buf_limit, ax
mav
shl
sub
mov
ret

ax, rX_buf_start
ax, 1
ax, rx_buf_first
Logica12Physica1, ax

get the physical word
address of rx_buf
convert to byte address
save bits A19 •• A8

compute the closest segment
baundry to rx_buf
increment offset by BOOOh bytes
decrement segment by BOOh paragraphs

logical to physical mapper

SetUpBuffers endp
292066-60

1-458

Ap·331

Driver Unhook
Assumes

OS - cs - IPX segment
Interrupts are DISABLED
Assumes any registers but OS, SS, SP may be destroyed
This procedure restores the original interrupt vector
This procedure will never be called if DriverInitialize
did not complete successfully.

DriverUnhook PROC NEAR
mov dx, InterruptMaskRegister
in al, dx
or al, InterruptBit
blow
out dx, al
las bx, InterruptVectorAddress
mov ax, word ptr OldIRQVactor[O)
mov es: [bx), ax; restore old interrupt offset
mov ax, word ptr OldIRQVactor[2)
; restore old interrupt segment
mav es: [bx) [2), ax
ret
DriverUnhook endp
mombo_init ends
end
292066-61

1-459

AP-331

i********************************************··******* ***************

SMacro.inc:

A set of macros that allows assembly code to be

written in a structured fashion resemblin9 a hi9h
level lan9uage.
Written by Ben L Gee. San Jose, Ca.
~his

(408)578-1123

code may be used freely as 'long as the authors name appears

in the l1stln9.

;**********************************************************************

het (lev, 0)
het(number,O)
t'define (ifa) (
het (lev, Uev+1)
\set(number, tnumber+l)
het (level%lev, ,number)
iif (%lev eq 1) then (het(num,
%if (Hev eq 2) then (tset (num,
tif (%lev eq 3) then (het(num,
%if (%lev eq 4) then (het(num,
\if (%lev eq 5) then (het(num,

%level0lH) )
.level02H) )
Uevel'03H»
Uevel04H) )
%level05H»

f1
fi
fi
fi
fi

jna anum

"define (ifae)
'set (lev, Uev+,1)
'set (number, tnumber+l)
het (levelUev, tnumber)
\if (Hev eq 1) then (het(num,
iif (Ueveq 2) then (tset (num,
tif (Hev eq 3) then (het (num,
'if (Heveq 4) then (het(num,
Hf (Ueveq 5) then (het (num,
jnae anum

"define (lfb)
het(lev, Hev+1)
het (number, 'number+l)
%set(leveltlev, 'number)
Uf (%lev eq 1) then (het(num,
\if (Uev eq 2) then (het (num,
Uf (Uev eq 3) then (het (num,
Hf (Hev eq 4) then (het (num,
Hf (Hev eq 5) then (het(num,
jnb Hnum

Uevel0lH) )
Uevel02H»
Hevel03H»
Uevel04H»
%level05H) )

UevelOlH) )
Uevel02H) )
Uevel03H) )
%level04H) )
Hevel05H) )

fi'
fi
f1

fl
fi

f1
f1
fi
f1
fi

292066-62

1-460

Ap·331

'·define (ifbe) (
'II set (lev, Uev+l)
\set(number, 'number+1)
'set (leveHrlev, 'number)
tif (Uev eq 1) then (het(nurn,
tif (Uev eq 2) then ('set (nurn,
tif (%lev eq 3) then ('set (nurn,
tif (Uev eq 4) then (het (nurn,
tif ('lev eq 5) then ('set (num,
jnbe Unurn

'·define (ife)
het (lev, Uev+1)
\set(number, 'number+1)
het (level%lev, 'number)
tif ('lev eq 1) then ('set (nurn,
tif (Uev eq 2) then "set (nurn,
Hf (%lev eq 3) then ('set (nurn,
Hf (Uev eq 4) then (het (nurn,
Hf (%lev eq 5) then ('het (nurn,

Ueve101H)
Uevel02H)
Uevel03H)
Uevel04H)
Uevel05H)

)
)
)
)
)

Uevel01H)
Ueve102H)
Uevel03H)
Uevel04H)
Uevel05H)

)
)
)
)
)

Uevel01H)
Uevel02H)
Uevel03H)
Uevel04H)
%level05H)

)
)
)
)
)

fi
fi
fi
fi
f1

Uevel01H)
Uevel02H)
Uevel03H)
Uevel04H)
Uevel05H)

)
)
)
)
)

fi
fi

fi
fi

fi
fi
fi

fi
fi

fi
fi
fi

jnc l'nurn

'.define (ifcxnz)
'het(lev, Uev+l)
'IIset(number, 'number+1)
het (leveHrlev, 'number)
tif (Uev eq 1) then ('set
Hf (Uev eq 2) then ('set
tif (Uev eq 3) then ('set
lsif (Uev eq 4) then ('set
'if (Uev eq 5) then ('set

(nurn,
(nurn,
(nurn,
(nurn,
(nurn,

jcxz Unurn

,"define (ifnc)
'set (lev, !Uev+l)
het (number, 'number+1)
'set (level'lev, 'number)
tif (Uev eq 1) then ('set (nurn,
tif (Ueveq 2) then ('set (nurn,
tif (Ueveq 3) then ('set (nurn,
tif ('lev eq 4) then ('set (nurn,
tif (Ueveq 5) then ('set (nurn,
je Unurn

fi

fi
fi

292066-63

1-461

AP-331

%*define(ife) (
'set (lev, Uev+l)
'set (number, 'number+l)
'set (levelUev, 'number)
%if (Uev eq 1) then "set (nurn,
%if (%lev eq 2) then ('set (nurn,
%if (Ueveq 3) then- ('set (nurn,
'if (%leveq 4) then (%set (nurn,
' i f ('Hev eq 5) then ('set (nurn,

Uevel01H) )
Uevel02H) )
Uevel03H) )
'IIlevel04H»
Uevel05H»

fi

Uevel01H)
Uevel02H)
Uevel03H)
Uevel04H)
'IIlevel05H)

)
)
)
)
)

fi
fi
fi

%level01H) )
Uevel02H) )
Uevel03H»
%level04H»
UevelO5H»

fi

Uevel01H)
Uevel02H)
Uevel03H)
Uevel04H)
Uevel05H)

fi
fi
fi
fi
fi

fi
fi

fi
fi

jne Unurn

%*define (ifne)
het(lev, Uev+1)
tset(number, 'number+l)
%set (level,lev, 'number)
%if (Ueveq 1) then ('set (nurn,
%if (Uev eq 2) then- ('set (nurn,
%if (Uev eq 3) then ('set (nurn,
\if (Uev eq 4) then ('set (nurn,
%if (Uev eq 5) then ('set (nurn,

fi
fi

je Unurn

t*define (Hz)
'set (lev, 'Hev+l)
'set (number, 'lsnumber+l)
'set (leveU1ev, 'number)
Uf ('Hev eq 1) then ('set (nurn,
%if (%leveq 2) then ('set (nurn,
%if ('Heveq 3) then ('set (nurn,
%if (Ueveq 4) then ('set (nurn,
'if ('lev eq 5) then ('set (nurn,

fi
fi
fi
fi

jnz l%nurn

'*define (ifnz)
tset (lev, Uev+l)
'bet (number, 'number+l)
'"et (leve l% lev, 'number)
%if ('Hev eq 1) then ('set (nurn,
%if (Ueveq 2) then ('set (nurn,
' i f ('Heveq 3) then ('set (nurn,
%if (%leveq 4) then "set (nurn,
Uf (Uev eq 5) then ('set (nurn,
jz Unum

)
)
)
)
)

292066-64

1-462

inter

AP-331

"*define (else) (
'Hf (Hev eq 1) then (het(t, Hevel01H) ) fi
'liif (Hev eq 2) then ('set(t, %level02H) ) fi
fi
'Hf (%lev eq 3) then ("set (t, %levelO3H»
Hf (Hev eq 4) then ('set (t, Hevel04H) ) fi
'Hf (%lev eq 5) then (het(t, %levelO5H»
"set (number, "'number+1)
'set (leveUlev, 'number)
Uf (%lev eq 1) then ('set (nurn,
Uf (Hev eq 2) then (het(nurn,
Hf (%lev eq 3) then ("set (nurn,
'Hf (Hev eq 4) then ("set (nurn,
Uf (%lev eq 5) then ("set (nurn,

fi

UevelOlH»

fi

HevelO2H»

fi

UevelO3H»
UevelO4H»
%levelO5H»

fi
fi

fi

jrnp short anum
Ut:
)

"*define (elsel)
Hf (%lev eq 1) then
Uf (Uev eq 2) then
Uf (%lev eq 3) then
\if (%lev eq 4) then

("'set (t, UevelOlH» fi
!'set (t, UevelO2H»
fi
("set(t, Uevel03H) ) fi

("'set (t, Uevel04H) )
\if (Hev eq 5) then ("set(t, Uevel05H) )
"set (number, 'number+1)
"set \leveUlev, 'number)
tif (%lev eq 1) then ('set (nurn, %levelOlH)
Hf (%lev eq 2) then ("set (nurn, %level02H)
\if (%lev eq 3) then ("set (nurn, %level03H)
' i f (Uev eq 4) then ("set (nurn, %level04H)
tif (%lev eq 5) then ("set (nurn, %level05H)

fi

fi

)
)
)
)
)

fi

fi
fi
fi
f1

jrnp Unum
at:

"*define (endif)

"if (Ueveq 1) then
tif (%leveq 2) then
Uf ('lev eq 3) then
Uf (Uev eq 4) then
Uf (%lev eq 5) then
Unum:
"set (lev, %lev-I)

("set
("set
('set
('set

(nurn,
(nurn,
(nurn,
(nurn,

%levelOlH) ) fi
%levelO2H»
fi
%levelO3H»
fi
%level04H) ) fi

('set (nurn, 'llevel05H) ) fi

292066-65

1-463

intJ

AP·331

t*define (do) (
'set (lev, Uev+l)
'bet (number, "number+l)
"set (leveUlev, 'number)
tif (Heveq 1) then (tset (num,
(Heveq 2) then (het(num,
tif (Heveq 3) then ("set (num,
tif ('lev eq 4) then ('set (num,
Hf ('lev eq S) then ("set (nurn,
Unum:

UevelOlH)
Uevel02H)
Uevel03H)
Uevel04H)
Hevel05H)

)
)
)
)
)

(tset (num,
(tset (nurn,
(tset(num,
(tset (num,
(tset (num,

UevelOlH)
UevelO2H»
Uevel03H)
Uevel04H)
'level05H)

) f1

(tset (nurn,
(tset (num,
(tset(num,
(tset (nurn,
(tset (num,

UevelOlH» fi
Uevel02H) ) fi
UeveI03H» f1
UeveI04H» fi
Uevel05H) ) fi

(tset (nurn,
(tset (num,
(het (num,
(het (nurn,
(tset (num,

UevelOlH) ) fi
Uevel02H) ) fi
Uevel03H) ) fi
UeveI04H» fi
UeveI05H» fi

('set (nurn,
("set (nurn,
('set (nurn,
"tset (nurn,
(het(nurn,

'leveIOlH»
Uevel02H)
Uevel03H)
Uevel04H)
UeveIOSH)

"if

t*def1ne(forever)
Hf ('lev eq 1) then
Hf (Uev eq 2) then
"if (Uev eq 3) then
Uf (Uev eq 4) then
tif (Hev eq 5) then
jmp Unurn
tset(lev, Hev-l)

t*define (whilea)
tif (Hev eq 1) then
tif ('lev eq 2) then
tif (Hev eq 3) then
tif ('lev eq 4) then
Uf (neveq 5) then
ja Unurn
tset (lev, %lev-l)

t*define(whileae)
tif (Uev eq 1) then
tif (Uev eq 2) then
tif (Uev eq 3), then
tif (nev eq 4) then
tif ('lev eq 5) then
jae Unum
tset (lev, Hev-l)

fi
fi
fi
fi
fi

fi

) fi
) f1
) fi

t*define (whileb)

'Hf (Uev eq

1) then
(Uev eq 2) then
('Hev eq 3) then
(Uev eq 4) then
(nev eq 5) then
jb Unurn
tset (lev, Hev-l)

tif
Uf
Uf
tif

fi

)
)
)
)

fi
f1
fi

fi

292066-66

1-464

AP-331

'*def1ne(whilebe) (
Hf ('Heveq 1) then
Hf "lev eq 2) then
tif (Ueveq 3) then
'Hf (Heveq 4) then
tif (Uev eq 5) then
jbe Unurn
'set (lev, 'Hev-1)

'*define (whilee)
'Hf (Uev eq 1) t.hen
'Hf (Hev eq 2) then
tif (Uev eq 3) then
tif (Hev eq 4) then
Hf (Uev eq 5) then
je Unum
'set (lev, Hev-1)

'*def1ne(whilecxzl
Hf (%leveq 1) then
tif (%leveq 2) then
tif (%leveq 3) then
Hf ('IIleveq 41 then
Hf ('Heveq 5) then
jcxz Unum
'set (lev, Hev-1)

'*define(whilenc)
tif (Heveq 11 then
' i f ('leveq 2) then
tif (Ueveq 3) then
Hf (Ueveq 4) then
Hf (Ueveq 5) then
jne l'nurn
'set (lev, Uev-l)

'*define(whilee)
tif ('IIleveq 1) then
tif (\leveq 2) then
tit ("lev eq 3) then
tif (Ueveq 4) then
Hf ("lev eq 5) then
je Unum
"set (lev, 'lev-1)

('set (nurn,
('set (nurn,
('set (nurn,
(het (nurn,

UevelO1H» fi
'Uevel02H) ) f i
UevelO3H» f i
UevelO4H» fi
('set (nurn, 'UevelO5H» f1

('set (nurn,
('set (nurn,
('set (nurn,
('set (nurn,
('het(nurn,

UevelO1H»
UevelO2H»
Hevel03H) )
'levelO4H»
UevelO5H»

fi
fi

fi
fi

fi

('set (nurn, UevelO1HI) fi
(het(nurn, Hevel02H) I fi
('set (nurn, UevelO3H» fi
"set Inurn, 'IIlevel04H) ) fi
('set (nurn, HevelO5H» fi

("set (nurn,
("set (nurn,
('bet (nurn,
("set (nurn,
('bet (nurn,

%levelO1H»
'UevelO2H»
UevelO3H»
%levelO4H»
Uevel05H) )

f1

"set (nurn,
("set (nurn,
("set (nurn,
("set (nurn,
('het(nurn,

UevelO1H»
UevelO2H»
'levelO3H»
UevelO4H»
UevelO5H»

fi
fi
fi

fi
fi
fi

fi

fi
f1

292066-67

1-465

inter
'*define(whilene) (
tif "leY eq 1) then
tif (Uey eq 2) then
tif (Ueyeq 3) then
tif (neY eq 4) then
tif (neY eq 5) then
jne Unurn
'set (leY. UeY-l~

'*define (whilez)
tif ('ley eq 1) then
tif (Uey eq 2) then
tif (Uey eq 3) then
tif ('ley eq 4) then
tif (Uey eq 5) then
, jz l"num
""et (ley. Uey-1)

'*define(whilenz)
tif (Uey eq 1) then
tif ('Heyeq 2) then
tif (Ueyeq 3) then
..i f ('Heyeq 4) then
tif (Ueyeq 5) then
/jnz Unum

AP-331

(tset(nurn.
""et (nurn.
( ....et(nurn.
"set (nurn.
(' .. et (nurn.

UeyelO1H»
UeyelO2H»
neyelO3H»
neyelO4H»
UeyelOSH»

fi
fi
fi
f1
f1

" .. et (nurn. Ueyel01H) ) £1
(het(purn, Ueyel02H) ) £1
(' .. et (nurn, UeyelO3H» fi
" ..et (nurn. UayalO4H» f1
("set (nurn, UevelOSH) ) fi

(het(num.
(het(num,
(het(num.
("set (num,
"set (num,

UeyelO1H» fi
Uevel02H) ) fi
Ueyel03H) ) £1.
UeyelO4H» £1
UeyelOSH» fi

(het(num,
(het (num,
"set (num,
('set (num,
(het(nurn,

Ueyel01H» fi
Uevel02H» f1
'HeyelO3H» f1
'Heyel04H) ) fi
UeyelOSH» f1

(het(num,
(het(num,
('set (num,
(het(num,
('_et (num,

UeyelO1H»
Ueyel02H»
Ueyel03H»
UevelO4H»
'Hevel05H) )

' ..et(leY ... ley-l)
)

'*define(loop)
tif ('Heyeq 1) then
tif ('ley eq 2) then
tif (Uey eq 3) then
tif ('ley eq 4) then
tif ('Hey eq 5) then
loop Unum
' .. et(leY, Uey-l)

'*define Iloope)
tif (Uey eq 1) then
tif (Uey eq 2) then
tif (Uey eq 3) then
tif (UeYeq.4) then
tif ('Hey eq 5) then
loope Unum
..etlley, 'Hey-1)

f1
fi
f1
f1
fi

)

292066-68

1-466

AP-331

'*define (loopz)
' i f ('leveq 1) then
'llif ('lev eq 2) then
' i f ('lev eq 3) then
tif (Hev eq 4) then
IIdf (Uev eq 5) then
loopz Hnurn
tset(lev, 'lev-1)

t*deflne(loopne)
Hf (nev eq 1) then
Hf (neveq 2) then
tif ('lev eq 3) then
Hf ('lev eq 4) then
tif ('lev eq 5) then
loopne Hnurn
tset (lev, Uev-!)

"'*define (loopnz)
tif (%lev eq 1) then
"'if (Uev eq 2) then
'Hf (Hev eq 3) then
tif ('Islev eq 4) then
Hf (nev eq 5) then
loopnz Unum
'set (lev, Uev-1)

'level01H) )
tlevel02H) )
Uevel03H) )
Uevel04H) )
('set (nurn, Uevel05H) )

fi
fi

(tset (nurn,
(het (nurn,
(het(nurn,
(het (nurn,
(tset (nurn,

%level01H)
nevel02H)
Uevel03H)
'Islevel04H)
%level05H)

)
)
)
)
)

fi
f1
f1

('IIset(nurn,
(tset(nurn,
(tset (nurn,
(tset (nurn,
("'set (nurn,

Uevel01H)
'level02H)
'Islevel03H)
'level04H)
Uevel05H)

)
)
)
)
)

fl'

(tset(nurn,
(tset(nurn,
(tset (nurn,
(tset(nurn,

fi
fi

fi

fi

f1

fi

f1
fi
fi

)

i·····················································......

292066-69

; Relid.inc Include file eoDtaining revision information

fill' the NBMS92 driver software.

; Written by Ben L. Gee San Jose, Califomia
j •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••

"*derme(MajIll'Vellion)(I)
"*derme(MioorVellion)(OO)
..*define(VeniODOate)(890129)
"*detine(LanType)(171)

; DOl yet assigned

; 890124 use eateDded write cIma mode
; 890129 correcI BCB cancel bug
292066-70

1-467

APPLICATION
NOTE

AP-326

July 1989

PS592E-16
Buffered Adapter LAN Solution
for the Micro Channel Architecture

DARYOOSH KHALILOLAHI
TECHNICAL MARKETING ENGINEER

Order Number: 292060-001
1-468

AP-326

1.0 INTRODUCTION

2.2 Terminology

As the performance of personal computers increases,
their role in the office environment expands. This expansion, coupled with the rapid increase in the number
of personal computers, makes interconnection an indespensible option. Sharing expensive peripherals (such as
high quality printers) reduces the cost. Sharing a single
data base improves data control and security. Having
electronic mail capabilities improves communication.
Proliferation of personal computers as the workstations
of choice provides yet another new application for networking. Clusters of workstations connected in Local
Area Networks (LANs) can improve productivity by
leveraging other station's (in the same or other clusters)
computing and storage capabilities. In such an environment the network throughput of workstation nodes is
increasingly important.

In the PAL equations and schematics a "_" at the end
of a signal name indicates that the signal is active low,
"#" stands for logical OR, "&" stands for logical
AND, and "!" stands for logical inversion. In the schematics any signal name starting with the letter "L" indicates that the signal is latched on the board or that all
the signals used in generating this signal are latched.

The best choices for Local Area Networks are those
that provide reliability, low cost, ease of expansion, and
the backing of major VLSI manufacturers. In recent
years IEEE 802.3 lOBASE5 (Ethernet), IOBASE2
(Cheapernet), and Twisted Pair Ethernet (TPE)
lOBASE-T have emerged as popular choices.
The PS592E is a 16-bit nonintelligent, 32-KByte, buffered slave adapter. It interfaces IBM Micro Channel
(Personal System 2 models 50, 60, 70 and 80) computers to an Ethernet or Cheapernet based network.The
82592 LAN Controller and 82561 DMA Controller are
used to receive and transmit frames between the network and local memory. The board can perform default
cycle (zero wait-state, 200 ns) memory data transfers
on the Micro Channel. The board comes with two interchangeable network serial interface modules for
Ethernet and Cheapernet applications. A TPE network
module will be available in the near future.
A menu driven exerciser software and a NetWare driver are provided with the demo board.

2.0 OBJECTIVE
This application note describes how the Intel 82561 and
82592 are used to build a high-performance, cost-effective LAN adapter that implements the traditional buffered architecture. The last chapter describes an easy
migration to a 32-bit adapter design.

2.1 Acknowledgements
I ackowledge and thank Yosi Mazor and Joe Dragony,
of Intel's (Folsom, Calif.) Data Communications Focus
Group, and Adi Golbert of Intel's (Israel) architecture
definition group for their work in developing the hardware and the software and their contribution to this
application note.

3.0 ORGANIZATION
Chapter 4 provides an overview of the 82561 and 82592
functionality. The reader needs a basic knowledge of
these components to better understand the following
chapters. Chapter 5 provides a functional description of
the PS592E. In this chapter, the design is divided into
three architectural subsections (host interface, memory
subsystem, and network interface). PAL·equations and
schematics are broken down according to the architectural division. Chapter 6 is the software chapter; samples from the Novell NetWare driver are given. Chapter 7 provides the performance benchmarks for the
board. Chapter 8 shows how the design can be modified
(including new PAL equations) to upgrade it to a 32-bit
adapter. The appendix gives a brief description for most
of PS592E internal signals.

4.0 COMPONENT OVERVIEW
4.1 82592 LAN Controller
The CHMOS 82592 is CSMA/CD controller with a 16bit data path. It can be configured to support a wide
variety of industry standard networks, including Ethernet, Cheapernet, TPE, PCNet, and StarLan. The 82592
consists of three subsystems: parallel, serial, and FIFO.
The parallel subsystem provides an 8- or 16-bit interface to the external bus. The 82592 supports memory
transfers (at up to 16 MB/s), accepts commands from
the processor that controls the bus, and provides status
to it. The 82592 can support simultaneous transmission
and reception including autoretransmit, transmit frame
chaining, and back-to-back frame reception. The serial
subsystem consists of a highly flexible CSMA/CD unit,
a data encoder/decoder, collision detect and carrier
sense logic, and a clock generator. In high- integration
mode it supports NRZI, Manchester, or Differential
Manchester encoding and decoding at bit rates up to 4
Mb/s. In high-speed mode the 82592 is capable of 20Mb/s Manchester or NRZI encoding. The FIFO subsystem consists of a transmit FIFO, a receive FIFO,
and control logic (with prqgrammable threshold). A total of 64 bytes of FIFO can be divided between receive
and transmit. This can be done in any of four possible
combinations (16/48, 32132, 48/16, 16/16 byte resolution).

1-469

inter
4.2 82561 Host
controller

AP-326

Int~rface

and Memory

The CHMOS 82561 is a high-performance DMA controller designed to work in a tightly coupled fashion
with the 82592 in a PC AT or PS/2 adapter application.
Two independent DMA channels support transfers of
up to to MB/s to/from the local SRAM/LAN Controller. Up to 32 KB of ring buffer memory can be I/O
or memory mapped into the address space. Host accesses to the local memory can be made with zero wait
states. These accesses can be 16- or 32-bit wide. The
82561, without CPU intervention, supports all of the
82592 tightly coupled functions. It can also reclaim bad
receive buffers.
The 82592/82561 is an ideal choice for 16 or 32-bit
buffered adapters. The combination provides ease of design, high performance, low component count, low
power requirements, and competitive cost.
NOTE:
The 82560 and 82561 have similiar functionality. The
only exception is that the double-host bus mode of the
82561 supports 32-bit-wide local memory. The 82592/
82560 combination is equally suitable for a 16-bit-wide
buffered adapter design. The 82561 is used in the
PS592E design to demonstrate a 32-kB (8k X 32) buff~
ered memory implementation.

5.0 IMPLEMENTATION
The board is divided into three sections (Figure I), the
host interface, the memory subsystem, and the network
subsystem. Both the 82592 and 82561 operate on the

to-Mhz clock generated by the serial side. In the following sections of this chapter a component (designated
by its U No. on the board and the schematic) is defined
as part of a subsystem if one or more of its, output pins
are in that subsystem. The host CPU generates a request to the 82561 to access any port (including
SRAM) on the board. SRAM accesses are 16-bit wide.
All other transfers are 8-bit wide. The local memory is
accessed either directly (nonpipeline mode) or through
the data latches (pipeline mode). The data transfers between the local memory and the 82592 are 16 bits wide
and are controlled by the 82561. During DMA transfers low and high banks of memory are accessed alternately.

5.1 Host interface
This subsystem consists of the POS ID register (U2),
POS configuration register (U3), the command register
(Ul), the status register (U4), the address decoder
(U14, U25, U24, U29, U23, and US), the address latches (U9 and U12), the data latches/transceivers (U32,
U22, U26, and U16), and their control (U31 and U21),
the request generator (USP, U24, U30, U23, U21, US,
and U19), and the controller (U7) and its support logic
(U20, U23, U30, and U13).
5.1.1 ADDRESS DECODING

After power-up the host reads the POS Read Identification register of the board, and if it is what the host
expects, the host will configure the board. The ID resides in location 16 and 17 of the on-board 32-byte
PROM. The first six Bytes of the PROM hold the
board's network address. The PAL equation for the
PROM chip select is given in section 5.2. For a complete list of the ports accessed by the 82561 GCS_
output see the table in section 5.1.4.

Address
Decode
and
Control

Logic

------~

+-_,-!1~6-+1

16

I

:
I
I
I

[-------CSM;/CDL~k--------·

I
I

I
I
I

I
I
I
I
I

: L----:r---I

._--I

,
"

~--~--~ ~--~~~

:,

L-~~__~~L_-_-_-_-_-_-_-_~
__

!

,

292060-3

Figure 1. PS592E/16 Block Diagram

1-470

(
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2
4

4-

GND
TXD

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8
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15
17

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21

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22

23

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RTS.
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LPSK.

RXC.
GND
GND
RXD
+SV
CHRESET

CoN2
3
7
11
2
4
8
II

FCC

--

+13
15
10
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1
12

292060-4

inter

Ap·326

MICRO-CHANNEL
MICRO-CHANNEL
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II

IRQ3.

~

CHD
eWD. 34
CHRDYRRT
CDSFDBK_ ~
31
ON 37
DO' 38
D0338
D0440
ON 4'
CHRESET.42
RESERV",

+5V

~

CDDS,,,,,,"

OND
IRQI.

?4Fa.

CHCK. ~

DO
01
D7

43

*"
*"

OND
AI4
A'3
AI2

-

MICRO-CHANNEL
RESERVEI
RESERV.EI

+'2V
COCHRDV

CD CHRD 38

~~

CHD
AI7
AI8
A"

~

at

'IND 3,

DS18RTN'"
REFRESH_

GND

.RG07 21
OND2S1

'2V

~

PSBUS A

ADDRESS 0-23

A20
All
AI8

IRooe ~

""-1.20

ON

I

IRQD5

MICRO-CHANNEL

DO? 42

A23
A22
A2'

OND1?

...,418

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ARlO' ~
ARlO

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DO 4'

""518

PSBUS B

""318

~

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D0238

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OND

OND 13

A171.

BURST_
-12YD 23

Te.

~
~

A231
A227
A2, I
ONDa
A20 10

ADDRESS 0-23

7

AlII

AUD'!,~~~ t!.-

CDSETUP.
MAD£24

;'

~
~~ ~
48

SBHE.

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+5V

IRQ"

ClIO
CWD.
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D,
D.
04

DATA 0-15
eND
CHRESET

eND
DB
DI
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0'2
0'4
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OND

~

~

tlRQ12 S7
GN SB

:=~:;' ~
~

4
U24

*~

001 48
ONDSO
01251
D1452
D'S S3
ON S4
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+,2V

3
CND

IRata_
OND

83I1-SB

292060-5

Figure 2b. PS592E·16 Digital Assembly Schematics (Continued)

1-472

...but

,

~4ALS311

ENINT3
•

2

UMC,-

A14
A13
A12
All
AID

AS
All

T

orlolD"-

.-niP.

3
4

5

8
7
II
9
10
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74ALS1I41
10
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2D
2Q
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4Q
5D
50
liD
8Q
70
7Q
8D
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23

22
21
20
19

III
17

III
15
14

LA14
LA13
LA12
LAll
LAID
LA9

ENINTa

2[U13

ENINT12

3

IRQ3.

8

IRQ7.

8

IRQDo

74AL5311
4

~
74AL538
9

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l

12
131 U13

IRQ12.

II

----.!.! C
-----,-

~

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•
liTE.

0-23

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OC

U12

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All
A5

2 lD
3 2D
4 3D

M

540

A3
A2
AI
AD

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8D
8 7D
II 8D
10 9D
II 10D
13 C
8
7

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23

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LA7

~~

~

50

20
19

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LA3

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7Q

t-~~

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14

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:

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LCDSETUP.

Co)

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9

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r-_-,1"'0-l1

CRI

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8

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74FOO

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292060-6

~

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+ov

.......
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LA'O
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LA'2
LA'3
LA' 4

LADDRESS 0-14

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co

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ADDRESS 0-23

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292060-7

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LOCAL DATA 0-15

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292060-8

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17
18
15
14
13
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LD17
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LD23

01
02
03
04
05
08
07

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17
18

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14
13

t-+,
23
1

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18
17
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8
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2
3

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8
7
8
9
I
19

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A3
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A7

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81
82
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B5

88
B7

B8

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18
17
16
15
I ..
13
12
II

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LD25
LD2B
LD27
LD28
LD29
LD30
LD31

OIl
012
013
014
015

20~48
19
18
17
18
15
I ..
13

S2
S3
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5
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6
S6
7
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8
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A
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SWEN.

WOE.

(!)

DATA 0-15

S
LOCAL DATA 0-15

LOCAL DATA 16-31
292060-10

intJ

AP-326

. The board has one POS configuration register (address
102 h). The contents of this register are shown below.

achieved by configuring the 82561 to its pipeline mode.
The following is the PAL equation for writing into the
command register.

Bit 0: Enable/Disable the adapter ,
Bit 1-3 : Mapping window (four below and four above
1 Megabyte)
Bit 2
0
0'

Bit3

0
0
0
0

1
1
0
0

Bit 1

0
1
0
1
0
1
0

The status register is five bits wide. The three least significant bits of this read only register are the contents of
the command register. The two most significant bits are
generated by the network module and determine the
type of the network module installed.

Memory window
OCOOOO h to OC7FFF h
OC8000 h to OCFFFF h
000000 h to OOFFFF h
008000 h to OOFFFF h
FCOOOO h to FC7FFF h
FC8000 h to FCFFFF h
FOOOOO h to F07FFF h
F08000 h to FOFFFF h

Bit 4
0
0

Bit 4-7: Selective Interrupt level. Bit 4 when set selects
IRQ3_; Bit 5 selects IRQ7_; Bit 6 selects
IR,Q9_; Bit 7 selects IRQI2_.

Bit 3
0
1
0
1

Ethernet
Cheapernet
Reserved
TPE

The reserved combination is for future use.
The following is the PAL equation for reading the
status register.

The following PAL equations are for reading from and
writing to the POS configuration register.
POSRDCNF_ = I (IGCS_&ILAO&LA1&ILA2&!lORD_
&ILCDSETUP_);

RDST_ = 1(IGCS_&IL561WIN_&ILSBHL&IIORD-l;

POSLDCNF_ = I (IGCS_&ILAO&LA1&ILA2&IIOWR_
&ILCDSETUP_);

5.1.2 DATA TRANSCEIVERS/LATCHES

The upper 256 bytes of the address space (Base + 7FOO
to Base + 7FFF) are used to acccess the command
register and the 82561 register ports. All accesses in
this range must be byte accesses. An active SBHE_
(odd byte) is interpereted as a request for accessing the
command register and an inactive SBHE_ (even byte)
for 8256'1.2592 accesses.
.
The remainder of the 32-kB memory window is shared
by the local SRAM, PROM, and an optional 8-or 16kB EPROM. The sharing is accomplished by a paging
scheme implemented in a 3-bit command register. Bit 0
and I of the command register are decoded as shown in
the following table.
Bit 1

0
0
1
1

BitO

0
1
0
' 1

EPROM access
RAM access
PROM access
reserved

Bit 2 of the command register determines the mode for
accessing the buffer memory. When this bit is 0 the
host accesses to the local SRAM are made with 3 or 4
waits.tates. These are referred to as nondefault cycles in
the Micro Channel documents. When this bit is I, the
host accesses to the local SRAM are made without any
wait states. This'is referred to as default cycles. This is

Bit 3 of the command register determines the mode in
which the host accesses the local SRAM. When 0 the
access is in nonpipeline mode (wait states asserted).
When I, the access is in the pipeline mode (Microchannel default cycles). This bit, and bit 0 of the 82561 host
mode register should be set to the same value before a
memory access is attempted.
In the nonpipeline mode the data transceivers/latches
act as simple transceivers. The cycles are extended by
pulling CHRDY low until the transfer (to/from) local
memory is completed. AI, which is the second least
significant bit of host address, determines which 16-bit
bank of memory is being accessed. All non-SRAM accesses are in the nonpipeline mode.
In the pipeline mode the data transcieverllatches act as
data latches. In this mode a read ahead / write behind
operation is performed by the 82561 after every oddword access requested by the host CPU. These accesses
are to sequential locations in the local SRAM. In this
mode no wait states are asserted (default cycle on the
Micro Channel). Tlie direction of the pipeline transfer
is determined by the value of bit I of the 82561 host
mode register, therefore the direction cannot be
changed on the fly. In read cycles, after the current
transfer the 82561 updates the buffer with the contents
of the next local memory address. This is referred to as

1-478

inter

AP-326

"read ahead" (in anticipation of the next host read request). In write cycles, the data is copied from the data
latch to' the local memory after the host has finished
writing to the data latch. This is referred to as "write
behind". Pipeline transfers are made after the host requests accessing an odd word, they are double-word
wide (both memory chip selects are activated).

The following PAL equations realize the above table.
HFOU and HFI U are the unqualified HF line. They are
qualified using the host's status and command lines before they become 82561 input requests.
HFl U = «LRDWR & LCDSFDBK) & (!L561 WIN_ #
!RAM)) #
(!LCDSETUP_ & LRDWR);
HFOU = «LRDWR & LCDSFDBK) & ((!L561 WIN_ &
!LSBHE_) # (L561WIN_
& RAM & !PIPELlNE) # (L561WIN_& RAM &
LA1)
# (L561 WIN_ & !RAM))) # (ILCDSETUP_ &
LRDWR);

The control signals to the transcievers/latches are generated by the following PAL equations.
Gl_

GL

= I «IMEMREQ_ & PIPELINE & ILREAD_ &
ILAl & ICMD_)
(IXVR1_ & ICMD_)
(IIORD_ & PIPELINE & IXVR2_));

#
#

= I «IHFO_ & HF1_ & PIPELINE & ILREAD_ &
LA 1 & !CMD_)
#
(IHFO_ & HF1_ & !PIPELINE & IXVR2_ &
!CMD_)
#
(1I0RD_ & PIPELINE & !XVR2-l);

CAB_ =! (1I0WR_ & !XVRL);
CBA1_ = ! (!CMD_& PIPELINE & ILWRITE_& ILAl &
RAM & L561 WIN_ & LCDSFDBK);
CBAL = I (IHFO_ & HF1_ & !CMD_ & PIPELINE &
ILWRITL&LA1);
DIR_

SX

= I «PIPELINE & !XVR2_ & 1I0RD_)
#
(I(!HFO_ & HF1_) # !PIPELlNE) & !LWRITE_
);
= (IMEMREQ_ & PIPELINE # IIORD_ &
PIPELINE & !XVR2_);

NOTE
1. The request is qualified earlier (with status line decode) in the case of pipeline cycles. In the pipeline
mode the 82561 provides half-clock glitch protection
(on its HF inputs). In nonpipeline cycles the request is
qualified later (with CMD_), when the address decode is free of any glitch.
2. CRI, R4, and C36 are added to delay the low-tohigh transition of the signal. The 82561 spec requires
100-ns inactive time on its HF inputs. The CMD inactive time can be as short as 80 ns. During back-toback nonpipeline write cycles this can cause the 82561
to miss the deassertion of the first request. The added
circuitry guarantees that the HF inputs of the 82561
will be inactive for at least 100 ns.

5.1.5 MEMORY CONTROLLER AND ITS
SUPPORT LOGIC

5.1.3 ADDRESS LATCHES
The host address and status are latched using the falling edge of CMD_. The latches become transparent
when CMD_ goes inactive.

5.1.4 REQUEST GENERATOR
Active SO--"SI_ and CDSFDBK_ or CDSETUP_
initiate a Host request. "CYCACT" indicates an active
request. The following table shows the complete list of
Host requests to the 82561.

To access any port on the board the host generates a
request to the 82561. SO_ and SI_ are decoded to
determine if the request is a read or a write. The interrupt from the 82561 activates one of the four interrupt
lines on the Micro Channel, depending on the POS configuration. In the non pipeline mode CDCHRDY is
pulled low immediately after the cycle starts. In the
pipeline mode the CDCHRDY is high when the cycle
starts.

CYCACT LCDSETUP_ L561WIN_ RAM SBHE_ HF1_ HFO_
1
0
1
X
X
X
1
Idle
O·
0
GCS_ cycle: Command/Status
1
1
X
0
0
GCS_ cycle: ROM·
0
X
0
0
1
SRAM cycle
1
X
1
0
1
0
X
1
1
82561 cycle
0
GCS_ cycle: POS registers
0
X
X
X
0
0
• ROM refers to either PROM or EPROM. Bit 1 of the command register determines which.

1-479

inter

Ap·326

Nonpipeline Cycles

292060-1

5.1.5.1 Nonpipeline Cycles

5.1.5.2 Pipeline Cycles

In all nonpipeline cycles (SRAM or otherwise)
CDCHRDY is pulled low within 30 ns after the status
(SO_ or SI_) becomes active. It remains low until the
82561 HRDY output goes to 1, then it goes to I.

During SRAM pipeline cycles CDCHRDY stays high.
It goes low after the cycle is over (HF_ removed). This
is when the 82561 performs read ahead or write behind
operations. Read ahead means that the next double
word of data is copied from the local memory into the
data latches in anticipation of the next two requests.
Write behind means that two words of data are first
latc:hed in the data latches and then the 82561 copies
them (two words at a time) into the local memory. The
memory address in this mode is provided by the host
address register, which is incremented by one after every 82561 transfer. To change the direction of the
transfer the 82561 Host mode register should be accessed first and its bit 1 changed.

The memory address provided by the 82561 in the nonpipline mode is the same as the host CPU address except that its three most significant bits (12, 13, and 14)
are logically ORed with the three least significant bits
of the 82561 host address register. The low bank of
memory is accessed for even-word addresses and the
high bank for odd-word addresses.
BEO"':"

BE1_

=! «LRDWR & LCDSFDBK & !CMD_ &
!L561WIN_l
# ( LCDSFDBK & LRDWR & !CMD_ &
!(RAM& LA1))
# (!LCDSETUP# ));

LPIPECYC = (LCDSFDBK & L561 WIN_ & RAM &
PIPELINEl;

=! ((LRDWR & LCDSFDBK & !CMD_l &
(L561WIN_& RAM & LA1));

CYCLE_ = ! «!(LREAD_ & LWRITE_ & CMD_l &
!LCDSETUP- l #
(!CMD_ & LCDSFDBK));

1-480

AP-326

Pipeline Cycles

''--_--If

'-----h

-~

82561 HRDY

CDHRDY
292060-2

'CDHRDY is Pulled low only if the next CPU request is to the board (while the local bus cycle is being completed).
EPROMCS_ = ! (IGCS_&IIORD_&IPROM&L561WIN_);

5.2 Memory Subsystem
The memory subsystem consists of the network address
PROM (V2), the low bank of SRAM (V 17 and
V27),the high bank of SRAM (V18 and V28),the data
bus transcievers (VII and V6), an optional EPROM
(VIO), part of a PAL (VIS), and the controller (V7).
All controls are generated by the 82561 except for chip
select for the PROM and the EPROM. Note that the
second term of the "PROMCS" is for recognizing the
host's request to access the POS identification registers
that reside in locations 16 and 17 of the PROM.

1-481

PROMCS_

= I ((IGCS_&IIORD_) & (PROM&L561 WIN_ #

LCDSETUP

= I (LCDSETUP_);

ILA 1&ILA2&ILCDSETUP-l);

The data bus transceivers isolate the low- and highword data paths of the local SRAM. This is needed
because during pipeline read ahead or write behind operations the accesses to the SRAM are double word
wide.

LAuurct.::a~

(

U-I'"

LOCAL DATA 16-31
MADDRESS 0-12

.... '2
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2
23
2'
24
25
3
4
5

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NJ
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107 '11
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1015 , .
10
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103'3
102'2
10'

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LD28
LOU
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L02.
L025
LD24

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23 At'

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25
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4
5

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7

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R"D
R>oInters
LANOptionName

byte

4 dup (0)
6 dup (0)
1
;non-zero means is a real driver.
0
;address is determined at initialization
1024
;largest read data request'will handle
LANOptionName
OAAh
; Bogus Type Code
1
;transport time
11 dup (0)
Olh
;Bogus version number
OOh

0
0

;board configuration (int., 10 add., etc.)
01
configurationO

' Intel PS592E Evaluation Driver$'

db

;10 ports and ranges
configurationO dw 4 dup (0)
db 0
;memory decode
dw 0, 0
db 0
;memory decode (secondary, not used)
dw 2 dup (0)
;interrupt level
.
db 4 dup (0)
:DMA
db 4 dup (0)
db 2 dup (0)

Count

dw
db

.,

OFFFFh

o

'Self Configuring Adapter

.,

Error Counters

jVVVVVVVVVVVVVVVVVVVVVVVi

Public DriverDiagnosticTable,DriverDiagnosticText
DriverDiagnosticTable

LABEL

DriverDebugCount
DriverVersion
,StatisticsVersion
TotalTxPacketCount
TotalRxPacketCount
NoECBAvailableCount
PacketTxTooBigCount
PacketTxTooSmallCount
PacketRxOverflowCount
PacketRxTooBigCount
PacketRxTooSmallCount
PacketTxMiscErrorCount
PacketRxMiscErrorCount
RetryTxCount
ChecksurnErrorCount
HardwareRxMismatchCount
NurnberOfCustomVariables
DriverDebugEndl

LABEL

dw
db
db
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw

byte
DriverDebugEnd-DriverDiagnosticTable
01,00
01,00
0,0
0,0

o

-1
-1

jnot used

-1
-1

;not used
:not used

-1

:not used

jnot used

o
o
o

o

byte

o

(DriverDiagnosticText-DriverDebugEnd1)/2
•
292060-18

1·494

inter

Ap·326

Table 1 (Continued)

,

,

.A~AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA.

Driver Specific Error Counters
;

iVvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv;
rx errors
underruns

no_cts
no ers

rx-aborts
no-590 int
false 590 int
false-rx Tnt
false-tx- int
lost rx stop=tx
rx disb failure
tx-int count
rx -buff ovflw
tic:::tirneout

dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

DriverDiagnosticText

LABEL

byte

db
db
db
db
db
db
db
db
db
db
db
db
db
db
db

'RxErrorCount' ,0
'UnderrunCount',O
'LostCTSCount',O
'LostCRSCount',O
'RxAbortCount',O
'N0590InterruptCount',O
'False590InterruptCount',0
'FalseRxlnterruptCount',O
'FalseTxlnterruptCount',O
'LostOurReceiverCount',O
'QuitTransrnittingCount',O
'RxDisableFailureCount',O
'TxlntCount',O
'ReceiveBufferOverflow',O
'TxTirneoutErrorCount',O

db

0,0

DriverDebugEnd

LABEL

word
292060-19

1-495

AP·326

6.2 Identification
The first step in the initialization is the identification of
the system and the board. If no mismatch is found, then
the POS configuration register is read. The PS592E
identification number (assigned by IBM) is 60F9. If

mismatch is found or no card enable bit is found, then
an error message is given and the initialization routine
is exitecI. If no problem is found, then the "Set Interrupt Vector" routine is called to set the vector to the
address of the interrupt routine and save the old vect()r.
Table 2 contains the code for the identification process.

Table 2

,

.AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAftAAAAAAAAAAAAAAAAA.

'

Driver Initialize
assumes:
OS, ES are set to CGroup (== CS)
01 paints to where to stuff node address
Interrupts are ENABLEO
The Real Time Ticks variable is being set, and the
entire AES system is initialized.
No registers or flags need to be preserved
returns:
If initialization is done OK:
AX has a 0
If board malfunction:
AX gets offset (in CGroup) of '$'-terminated error string
;

.'

;

;vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvVVVVVVVVVVVVVVVVVi

Oriverlnitialize PROC
NEAR
mov MaxPhysPacketSize, 1024
cld
iFirst, find out the system we are in ....
OFC04h (3 slots)
,Model 50
OFC05h (8 slots)
,Model 60
,Model 70
?????h (3 slots)
OF800h (8 slots)
,Model 80

mov
int

ah, OCOh
ISh

cli

jc
cant get id
mov ah, eS:[bx+l)
mov aI, es:[bx+2)
cmp ax, OFC04h
jnz eight_slots
mov num of slots, 03h
jmp slots_set
eight_slots:
mov num of slots, 08h
cant get id:- slots set:
add nurn of slots, OSh
mav dl,-num_qf_slots

,model byte
,5ubmodel byte
iis it a model 50?

,model 50 just has three slots
,models 60 and 80
,for now, default to eight slots
;add OSh so we can use this in compare operation

;Next, find out which slot of the system we are in ....
mov' curr slot, D8h
next slot:
mov aI, curr slot
out POSPort,-al
mov dx, CardIDLo
in

aI, dx

cmp
je
inc

aI, IDValLo
next_byte
curr slot

cmp

curr-slot, dl

~e
card-not found
Jrnp next:::slot
next byte:
mov dx, CardIDHi
in
aI, dx
cmp aI, IDValHi
je
its_us
inc curr slot
cmp curr:::slot, dl
je
card_not_found
jmp next_slot

islot number

,Output slot 10 to Channel Position Select Reg.

~

Read the low byte of card 10.
If it matches our low byte ...
check the next byte
Otherwise, index to the next slot and check there.
Make sure we don't check beyond num_of_slots.
Check next slot.
Read high byte.
Compare with expected high byte.
If it's a match we can cont.inue.

Otherwise, index to the next slot and check there.
Make sure we don't check beyond nim_of_slots.
Check next slot.
292060-20

1-496

inter

AP-326

Table 2 (Continued)
card not found:
xor -aI, al
out POSPort, a1
;take system out of setup
mov ax, offset cgroup:no_card_message
jmp init_exit
;Next, read the POS register on the PS592E to determine setup and
;fi11 in the variables for later use ...
bogus pas data:
mav ax, offset cgroup:pos_data_error_message
jmp init_exit
its_us:
mov
in
mov
xor

dx, POSCnf
aI, dx
pas_byte, al

;save the value in a register

aI, a1

out POSPort, al
mov aI, pas byte
mov bx, 0 try_next_Ioc:
shl aI, 1
jc
set int
inc bxcmp bx, 03h
ja
bogus-pos_data
jmp try_next_Ioc
set_int:
mov aI, irq_array[bx)
mov irCLchannel, al
mov aI, pas_byte
cbw
and ax, 06h
mov bx, ax
mov ax, mem_array[bx1
mov adapter_base, ax

;if bx reaches 3 without finding a set POS bit
;then POS register was 1) not initialized or
;2) not read correctly so abort

iremove all extraneous bits

;bx will index into array of memory offsets
;get the value into ax
;set the variable
.

;set up registers then call set_vector
push di
mov aI, irq_channel
mov bx, OFFSET CGroup:DriverISR
call SetlnterruptVector
pop di
292060-21

1-497

AP-326

two configure commands. The first one puts the 82~92
into 16 bit mode and the second one does the following:
Puts the 82592 in High Speed Mode to support
Ethernet serial bit rates.
All netwo~k parameters are set up for default
Ethernet values.

6.3 Hardware Initialization
The 82561 configuration registers are set appropriately
(enable memory mapped accesses, DMA 82588 Tel,
double host bus mode, etc.). The command register is
set to read the address PROM and store its value. Then
the commimd register· is set to enable RAM access.
Then the transmit channel is set and 82592 is issued

Table 3 shows the intialization code.

Table 3

,

82561 Initialization section

;VVVVVVVVVVVVVVVVVVVVVVVVVVVVV~VVVVVVV

mov

ax, adapter_base

moves, ax

mov
%slow
mov
mov
mov
mov
mov

;reset the 82561

es:byte ptr id_reg, OOh

es:byte ptr master mode, 031h ;DMA has priority, double bus width
;late write, 0 i/o/mem wait state
es:byte ptr control_reg, Olh
es:byte ptr himm_int_mask_reg, 082h ;high assert,edge trig,drive,int on tx
es:byte ptr dma_mode_reg, 040h ; 588 TCI, discard bad frames
es:byte ptr select_reg+4, OCOh ;enable access, memory mapped,

mov es:byte ptr command_reg, 02h ;enable address PROM
mov aI, es:byte ptr mem_space
mov byte ptr ds:[di), al
;read address from PROM and store in
mov byte ptr node addr, al
mov a1, es :byte ptr mem_space+1 ; local variable "node_addr"
mov byte ptr ds:[di+l], a1
mov byte ptr node_addr[l], al
mov aI, es:byte ptr mem_space+2
mov byte ptr ds:[di+2], al
mov byte ptr node_addr[2], al
mov aI, es:byte ptr mem_space+3
mov byte ptr ds:[di+3], al
mov byte ptr node_addr[3], al
mov aI, es:byte ptr mem_space+4
mov byte ptr ds:[di+4], al
mov byte ptr node_addr[4], al
mov aI, es:byte ptr mem_space+5
mov byte ptr ds:[di+5], al
mov byte ptr node_addr[5], al
mov es:byte ptr command_reg ,Olh ;enable RAM

Receive Channel

,

Initial~zation

Receive is set up to use channel O. Receive buffer is 28K
at location zero of adapter memory

s~arting

;vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv~vvvvvvvvvvvvvvvvvvvvvvv

mov
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov

es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte

ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr

b.:..c_addrO_reg, OOh
b_c_addrO_reg+4, OOh
b_c_addrO_reg+8, OOh
la_lim itO_reg , OOh
10_limitO_reg+4, OOh
10_limitO_reg+8, OOh
up_limitO_reg, OFFh
up_limitO_reg+4, 01Sh
up_limitO_reg+8, OOh
stopO_reg, OFDh
stopO_reg+4, OlSh
stopO_reg+8, OOh

;receive buffer starts at location.
;zero in the adapter memory
;lo_limitO_reg points to beginning
;of adapter memory
;up_limitO_reg points to the last
;word of the 28K receive buffer
;stopO_reg points to the location
;two words before the end of the
;receive buffer
292060-22

1-498

intJ

AP-326

Table 3 (Continued)

,

.~~~~AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

AAAAAAAAAAAAA

Transmit Channel Initialization
Transmit is set up to use channel 1. Transmit buffer is "4k
starting directly above the receive buffer. Transmit buffer
stops 256 bytes before the end of adapter memory because the
B2561 registers and control registers are mapped there.
~vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvyvvvvvv

mov
mov·
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov

es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte
es:byte

ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr

b_c_addr1_reg, OOh
b_c_addr1_reg+4, 01Ch
b_c_addr1_reg+B, OOh
lo_limit1_reg, OOh
lo_limitl_reg+4, 01Ch
lo_limit1_reg+B, OOh
up_limit1_reg, 07Fh
up_Iimitl_reg+4, OlFh
up_Iimitl_reg+B, OOh
stop1 reg, 07Dh
stop1-reg+4, OlFh
stopl=reg+8, OOh
dma_ctrll_reg, 14h

mov
mov

tx buf head, 7000h
rx=buf=head, OOOOh

;transmit buffer starts at location
;7000h (word 3BOOh) in the adapter
imemory
;lo_limitl_reg points to location
;7000h in the adapter memory
;up limitl reg points to the last
;adapter memory location before the
;561 mapping begins
;stop register points to the spot
;2 words before the 561 space
;enable channel

mov ax, OOh
mov di, rx buf head
mov cx, 3F7Fh rep stosw
;set up-for configure command
mov es:byte ptr portO, C RST
mov di, tx buf head
;the 82592 must be given a configure comma~d
xor ax, ax;with zero in the byte count field to put
stosw
;the 82592 into 16 bit mode
stosw

mov es:byte ptr portO, C_CONFIG ;configure the 82592 for 16 bit mode
xor ex, ex
wide mode wait loop:
mov es:byte ptr portO, OOh
%slow
mov aI, as:byte ptr portO
;read register 0
and al,ODFh
;disregard exec bit
cmp aI, 92h
lis configure finished?
jz
do_config
loop wide_mode_wait_loop
mov ax, offset cgroup:no_response_message
jmp init_exit
do_config:
mov es:byte
mov es:byte
mov es:byte
mov es:byte
mov es:byte
mov es:byte

ptr
ptr
ptr
ptr
ptr
ptr

portO, C INTACK
dma_ctrII_reg, 04h
b_c_addrl_reg, OOh
b_c_addrl_reg+4, OlCh
b_c_addrl_reg+8, OOh
dma_ctrll_reg, 14h

mov si, offset cgroup:config_block
mov di, tx buf head
mov cx, 9 rep movsw
mov es:byte ptr portO, C_CONFIG

xor

ex, ex

;clear interrupt in 592
;disable channel
transmit buffer starts at location
7000h (word 3BOOh) in the adapter
memory
;enable channel

;configure the 82592
292060-23

1-499

intJ

AP-326

Table 3 (Continued)
config_w~it_loOP:
mov es:byte ptr portO, OOh
%slow
iread register 0
mov aI, es:byte ptr portO
;discard extraneous bits
and aI, ODFh
,;is, configure finished?
cmp aI, 92h
conf ig_done
jz
loop config_wait_loop
mov ah, al
mov ax, offset cgroup:config_failure_m~ssage
jmp init_exit
config_done:
clear interrupt caused by configuration
mov es:byte ptr portO, C INTACK
mov es:byte ptr int_ctrl=stat_reg, Olh
do an lA_setup
mov es:byte ptr dma_ctrll_reg, 04h
mov es:byte ptr b c addrl reg, OOh
mov es:byte ptr b=c=addrl=reg+4, OlCh
mov es:byte ptr b_c_addrl_reg+8, OOh
mov es:byte ptr dma_ctrll _reg, l6h
mov
mov

;clear 561 external interrupt
;disable channel
; tra'nsmi t buf fer starts at location
;7000h (word 3800h) in the adapter
: memory
;enable channel

di, tx buf head

ax, 06h

-;address byte count

stosw

mav
mov

si, OFFSET CGROUP:node_addr
cx, 03h

rep movsw

mov

es:byte ptr portO, C_IASET

xor

ex, ex

;set up the 82592 individual address
;cx is used by the loop instruction below. this
;causes the loop to be executed 64k times max

ia wait loop:
- mov- es:byte ptr portO, OOh
%slow
mov aI, es:byte ptr portO
;discard ext'raneous bits
and aI, ODFh
is command finished?
cmp aI, 9lh
ia done
jz
loop ia=wait_Ioop
mov ah, al
mov ax, offset cgroup:iaset_failure_message
jmp init_exit
,ia done:

mov
mov

es:byte ptr portO, C_INTACK
es:byte ptr int_ctrl_stat_reg, Olh

;clear 561 external interrupt

;urunask our interrupt channel

mov
in
mov
and
%slow
out
mov

dx,
aI,
bl,
aI,

int_mask_reg
dx
int unmask
bl -

dx, al
es:byte ptr himm_int_mask_reg, 04h

;enable the receiver
mov es:byte ptr dma c'trlO reg, 3Eh
mov es:byte ptr portO, C_RXENB
xor

ax, ax

mov

ex, 1

in it exit:

;enable channel

;make sure interrupts are enabled
;return control to IPX

sti

ret
Driverlnitialize

;enable slave interrupt

endp
292060-24

1-500

inter

Ap·326

6.4 Interrupt Routines
First the current status of the machine is saved and the
interrupt mask bits are set appropriately. Then the type
of Interrupt is identified and the control is transferred

to the appropriate routine. Transmit and receive interrupts are handled by the 82561, other interrupts are
passed to the CPU. Table 4 shows the Interrupt routines.

Table 4

Interrupt Service Procedure
DMA channel 0 is the transmit channel
DMA channel

,

is the receive channel

BX is set to point to the current receive or transmic buffer head
after the cause of the interrupt has been determined.

;vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv

DriverISR
public

PROC
far
DriverlSR

pusha
push ds
push es
call lPXStartCriticalSection ;tell AES we're busy
mov ax, cs
;DS points to C/DGroup
mov ds, ax
;segment of adapter memory base
mov es, adapter_base
mov dx, int_mask_reg
;get mask state of 8259
in
aI, dx
;set mask bit for our channel
or
aI, int_mask
;write new mask to 8259
out dx, al
mov aI, EOl
out PriIntControlPort, al
;is our assigned interrupt in the secondary 8259?
cmp at_flag, Oh
jz
below 8
out SeclntControlPort, al ;if so, clear secondary too
below 8:
cld
mov aI, es:byte ptr
int_poll_loop:
;enable interrupts to be friendly
sti·
idid I receive a frame?
test aI, RxChannel
jnz rcvd_packet_jmp
;did
finish a transmit?
test aI, TxChannel
jnz sent_packet_jmp
;is there an error condition?
test aI, Ext Interrupt
jnz other 588 int
inc false-590-int
;unwanted interrupt
jmp int_exitsent_packet_jmp:
jmp sent_packet
rcvd_packet_jmp:
jmp rcvd_packet
other 588 into
inc false 590 int
mov es:byte ptr portO, C_INTACK
mov es:byte ptr int_ctrl_stat_reg, Olh
mov es:byte ptr portl, C_lNTACK
jmp int_exit
292060-25

1-501

inter

AP-326

6.4.1 RECEIVE

An interrupt on the receive channel is either due to
receiving a frame or due to hitting the stop register. The
location pointed to by the receive buffer head is exam·
ined to check if a complete frame was received. This
location is initalized to FF h (by the 82561). After receiving a frame the byte count is copied to this location.
Assuming the value read is not FF h (a full frame was
received), the routine checks the size of the frame. If
the frame is too short, too long or does not match the
phsical length, "buffer crash" routine is called. In this

routine the receive error count is increased, the DMA
channel is disabled, the DMA address registers are reprogrammed and then the channel is reenabled. If the
frame length is O.K., then routine that processes the
received frame is called. At the end the buffer head is
incremented to point to the beginning of the next frame
in the buffer. The stop register is then updated. A check
is performed to findout if a wrap around was done duro
ing the reception of the last frame. If so, then the buffer
head is appropriately modified. Table 5 shows the driver code for this section.

TableS
;

............................... ,."" .............. '''' ............. ;

;

RECEIVE EVENT

,vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv;

buffer crash:

inc

rx errors

mav
mev

eS:byte ptr portO, C_RXDISB
eubyte ptr portl, C_SELRST

mev

es :byte ptr elma_ctrIO_reg, 2Eh

mev
mav

es:byte
es: byte
eSlbyte
eSlbyte

mev

8S

ptr
ptr
ptr
ptr

b_c_addrO_reg, QOh
b c addrO reg+4, DOh
b:c::a.ddrO:reg+8, DOh
la_IimitO_reg, OOh

ibyte ptr lO_limitO_reg+4, DOh

mav
mev
mav

es:byte ptr lo_limitO_req+S, DOh
eSlbyte ptr up_limitO_r~g, OFFh
es:byte ptr up_limitO_reg+4, DISh
-maY es;byte ptr up_limitO_reg+9, ,DOh
mov es:byte ptr stopO_reg, aFOh
mev eSlbyte ptr BtopO_reg+4, OlBh
moves, byte ptr stopO _..:::eg+8, OOh
mov rx buf head, OOOOh
mov estbyte ptr dma_ctrlO_reg, 3Eh
mov es:byte ptr porta, C_RXENB
mov eSfbyte ptr portO, C_SWPI
moves: byte ptr portO, C_SWPO
jmp int_exit

false rXf
inc false_rx_int
jmp int_exit

1disable channel
;receive buffer starts at location
; zero in the adapter memory
;10 limitO reg points to beginning

; of-adapter memory
;up_limitO_reg points to the last
;word of the 2BK receive buffer
;stopO_reg points to the location
; two words before the end of the
;receive buf,fer
;enable channel

; i f not, increment counter and

rcvd-packet:
mov ax, rx buf head
;get index into rx buffer
mov rx buf~tr-; ax '
;get index into rx buffer
mav eS:byte ptr int_ctrl_stat_reg, Oeh Jack 561 interrupt
mov bx, rx buf head
;get index into rx buffer
mov ax, estword ptr mem_space(bx] ;word moves are required when accessing
mav cx, es:word ptr mem_space(bx] + 2
mav ah, cl
;make sure we really received a frame
cmp ax, OFFFFh
jz
false rx
do next frame I - mov- curr_rx_length, ax
lax contains total length of the frame buffer
; index bx to point to beginning of data
add bx, 4
;toss byte count & status
dec ax
and aI, Ofeh
;round up
;sub length of 802.3 header
sub ax, 14
cmp ax, 1024 + 64
jbe not_too_big
inc packetRxTooBigCount
jmp buffer_crash
not_too_bigl
cmp ax, 30
jae not_too_small
inc PacketRxTooSmallCount
jmp buffer_crash
not too small:
-mov- dx, eS:[bx].rx_Iength ;qet IPX length
xchg dl, dh
inc dx
and dl, Ofeh
xchg dl, dh
cmp dx, 8S: [bx] .rxyhysieal_length :same as 802.3 lengt.h
,je
fields match
jmp buffer:crash
fields match:
xchg dl, dh
at least min length minus header
cmp dx, 60 - 14
yes, continue
ja
len_ok
no, round up
mov dx, 60 - 14

292060-26

1-502

intJ

AP-326

Table 5 (Continued)
len_ok:
cmp

ax, dx

; match physical length

jz

not_inconsistent

; yes, continue

inc
jmp

HardwareRxMismatchCount
buffer crash

not_inconsistent:

%inc32 TotalRxPacketCount
call ProcessRxFrame
mav

add
add
and
add
%slow
mov
cmp
jb
sub
mov
no wrap:
- shr

ax, curr rx length

ax, 10 - ax, 3
aI, OFCh
rx_buf_head, ax

; Double Word Increment
;get original byte count back
;add overhead bytes to receive length
;round up to nearest. double word
; boundary
;rx_buf_head points to next frame buffer

ax, rx buf head
ax, 7000h no_wrap
ax, 7000h
rx_buf_head, ax

ax, 2
;convert byte address to doubleword address
;calculate the stop value
ax, 4
;check for negative value (stop was at 1st 16 bytes)
jns set_stop
;mask to generate required stop value
and ax, IBFFh
set_stop:
mov new_s top_va I , ax
;load bx for use as pointer
mov bx, rx buf head
;get byte count LSB
mov ax, word ptr es:mem_space[bx]
mov cx, word ptr es:mem_space[bx] + 2 ;get byte count MSB
;combine them in cxi
mov ch, al
mov ax, new stop val
mov es:byte-ptr stopO_reg, al
;update the stop register
mov es:byte ptr stopO_reg + 4, ah . ;by writing new values
mov es:byte ptr stopO reg + 8, OOh ;to all three bytes
cmp cx, OFFFFh
;Is there another received frame to be
je
int_exit
; processed?
mov ax, cx
;receive loop expects count to be in ax
jmp do_next_frame
sub

int exit:
-push cs
pop ds
finish_exit:
moves, adapter_base
mov aI, es:byte ptr int_ctrl_stat_reg
test aI, himm_int_mask
;check for new interrupt
;if we do, service it
jnz int_pending
;mask interrupts so we can unmask our
cli
;channel without reentrancy problems
mov dx, int_mask_reg
;get mask state of 8259
in
aI, dx
;clear mask bit for our channel to
and aI, int_unmask
;enable new interrupts from adapter
%slow
;write new mask to 8259
out dx, al
IPXEndCriticalSection
;tell
IPX it can run
call
;restore machine state
pop es
pop ds
popa
ireturn
iret
too_big:
inc PacketRxOverflowCount
jmp int_exit
int_pending:
jmp int_poll_loop
292060-27

1-503

inter
S.4.2 TRANSMIT

After acknowledging the 82561 transmit interrupt, the
routine checks if the transmit flag is set. If it is set,
th,e routine reads the status registers of the 82561. If the
transmit OK bit is not set, there was a problem with

the transmit. In this case, other bits are read to deter·
mine the exact cause of the problem so that the appropriate action can take place. If transmit was successfull
the routine updates the retry count and returns the TX
EeB to IPX with a good completion code. Table 6
.
shows the code for transmit.

TableS

TRANSMIT EVENT
:vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv:
sentJ>acket:
eli
mov eS:byte ptr int_ctrl_stat_reg, 30h lack 561 interrupt
cmp tx active flag, 0
bogus tx Tnt
;shouldn't have been transmitting
jz
inc tx lnt count
mov al~ es,byte ptr statl_588_reg
mov result!, a1
mov aI, eS:byte ptr stat2_588_reg
mov result2, a1
test aI, 20h
jz
tx error
iextract the total number of retries from
mov a1-; resultl
;the status register and add to retry count
and ax, OFh
add RetryTxCount, ax
jstatus ; 0, good transmit
xor ax, ax

FinishUpTransmit:
les si, send list
cmp es:byte ptr [sil.transmitting, TRUE
jnz not active
mav es:-[si].completion_code, a1
mav ax, eSI word ptr [si].link
mav word ptr send_list, ax
mev ax, es: word ptr [sil.link + 2
mav word ptr send_list + 2, ax
;finish the transmit
moves: [si].in_use, 0
call IPXHoldEvent
not active:
,
-push cs
pop ds
mav cx, word ptr send_list + 2
mav tx active flag, cl
jcxz int_exit_Jmpl
maves, ex
;segment af next SeB in list
mav si, word ptr send list
;offset af next seB in list
call start send
jmp finish_exit

int exit jmp1:
-jmp -int_exit
bagus_tx.:.,.int:
inc false tx int
jmp int_exi ttx_errar:
test resultl, 20h
;Max collisions??
jnz QuitTransmitting
test result2, Olh
~Tx underrun??
jz
lost ets
inc underruns
mav aI, TransmitHardwareFailure
jmp FinishUpTransmit
lost ct.:
test result2, 02h
;did we lose clear to send??
jz
lost crs
inc no cts
mov al~ TransmitHardwareFailure
jrnp FinishUpTransmit
lost ers:
test result2, 04h
;did we lose carrier sense??
jz
late coll
inc no crs
mav al~ TransmitHardwareFailure
jmp FinishUpTransmit
292060-28

1-504

inter

AP-326

Table 6 (Continued)
late coll:
test result2, OSh
;did we have a late collision?
jz
hmmm
inc no ers
mov al; TransmitHardwareFaiIure
jmp FinishUpTransmit
hmmm:
mov aI, TransmitHardwareFaiIure
jmp FinishUpTransmit
QuitTransmitting:
add RetryTxCount, OFh
inc stop_tx
mov aI, TransmitHardwareFailure
jmp FinishUpTransmit
DriverISR

endp
292060-29

1-505

inter

AP-326

LAN

/

Under / r r Test

IBM PS/2T1ot
Model 50 I!c 70
with
PS592E-16
Adopter

Novell 286A
8-MHz,OWS
with
PC5B6E
Adopter

I

I

.. Novell Perform2 Ver 2.3
~ File Server: Novell 286A with PC586E Adopter
.. Workstotlon Node: IBM PS/2 Model 50 ond io (One Node on Network)
Doto Throughput of Workstotlon Node to Flleserver

.....
o
z

~
a::

e.....a::

PS/2
Model 50
PS/2
Model 70

Q.

300

350

Kilobytes per Second

292060-30

, Figure 3. PS5292E/16 Performance Benchmarks

7.0 PERFORMANCE

8.0 PS592E-32

The PS592E provides very high performance compared
to many commercial adapters. The result of the performance experiment is shown in Figure 2. The PS592E
can perform default cycles (200 ns) on the Micro Channel. This is done when the board is configured for pipeline mode. Without this feature each host access would
take about 500 ns, resulting in less efficient use of the
host bus bandwidth. In addition to reducing the host
bandwidth consumption, performing the default cycles
(200 ns) on the Micro Channel improves the network
performance by about 10% over non-default cycles.
The experiment was performed using the standard
Perform2 with one station and the file server (no collision).

This chapter shows how the'PS592E-16 design can be
modified to provide an adapter for the 32-bit Micro
Channel I/O slots (Models 70 and 80). The design is so
similar to the 16"bit design that only the differences
. (PAL equations and schematics) are specified.

8.1 Architecture
The data path between tlie Micro Channel and the data
latches/transceivers is 32-bit wide. The low word (DOD15) goes to U32 and U22 and the high word (D16D31) goes to U26 and U16. The component count is
the same as in the 16-bit design. The complete set of the
PS592E-32 schematic is given.

1-506

AP·326

8.2 Schematics

8.3 PAL Equations

Besides the 32-bit data path, two other minor modifications are made to the schematics.
1. U5 is changed from a 3-input NAND gate to a 4-input NAND gate. Half of it is used to generate the
CDDS32_ signal (indicating 32-bit data transfers)
to the Micro Channel. An extra input is added to the
CDDS16_logic (PIPELINE_, pin II ofUt). Only
the memory transfers in the pipeline mode can be 32bit wide. Nonpipeline memory transfers remain 16bit wide on the low word (DO-DI5), and non-memory transfers remain 8-bit wide on the low Byte (DOD7).
NOTE:
1. Our Netware driver uses the pipeline mode to transfer the frame data and nonpipeline mode to transfer
other frame information (byte count, status, etc.).
Since most of the time is spent in transfering frame
data, the restriction (pipeline mode for data transfer
only), does not reduce performance. However, if a designer would like to extend the 32-bit transfers to nonpipeline cycles he can do so. To do this, (BEO_ #
BEI_) and (BE2_ + BE3_) should be generated
on the board and latched (BEn_ are the Byte enable
signals on the Micro Channel).
.
2. CBA2_ signal (which was generated in U31) is removed and CBAI_ is renamed CBA_. CBA2_ was
the latch signal for the high word data latch/transciever (U26, U16) in the 16-bit version. It is not needed
because the data is latched 32 bits at a time. The extra
pins of U31 are used to generate SWEN_ in the PAL.
SWEN_ is the enable signal to the local bus transceivers (U6 and Uti).

8.3.1 HOST REQUEST

The equation for unqualified HFO is modified. A request to the 82561 is generated each time the host CPU
requests access to local memory (double word). Thus,
LAI is removed as the qualifier.
HFOU

=

((LRDWR & LCDSFDBKl & ((!L561WIN_ &
!LSBHE_l # (L561WIN-ll #
(ILCDSETUP_ & LRDWRl;

8.3.2 DATA LATCH/TRANSCEIVER CONTROLS

CBAI_ is renamed CBA_, and LAI is removed from
the equation, because the data is latched 32 bits at a
time (independent of LAI). CBA2_ is removed.
CBA- = ! (!CMD_ & PIPELINE & !LWRITL & RAM &
L561WIN_ & LCDSFDBKl;

For the same reason, data latch/transciever enable signals are modified to be independent of LA I during
pipeline memory accesses.
G1_ = ! ((!MEMRE~ & PIPELINE & ILREAD_ &
!CMD-l
(!XVR1_&!CMD_l
(IIORD_ & PIPELINE & !XVR2_»;
GL = ! ((!HFO_ & HF1_ & PIPELINE & !LREAD_ &
!CMD_l
(!HFO_ & HF1_ & !PIPELINE & !XVR2_ &
ICMD_l
(IIORD_ & PIPELINE & !XVRL»;

3. Only the low 24 bits of address are decoded (no
change from the PS592E-16). If the software code is
that of the 80386, then the higher 8 bits should also be
decoded and the result should be latched.

1-507

#
#

#

#

+sv

-

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.01"F -: .01"F
:-0.01"F-: .01"F
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0.01UF-:
... ce ' I' cIa ~ ... Cll' ... C12'

0.01uF-:
C13 '

0.01uF
0.01uF
0.01uF
C14 ... ,
C15 ;; ...
C18.'

0:01uF
C17

(

DND

"

0.01uF-: :-0. 01 uF-: 0.01uF
0.01uF-: :-0.01uF :-0.01uF
Cl .... ...
020' "
022' I'
023'
Cl.' I'
021'" I'

!!

+IIV

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Gl

cg

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024

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i

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4
8

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-1 4a
D"50
01 51
12VO 52
RESERVED
saHE

GND

51.
t.I 10.
+12V

~
~~

..'to. I;ji'*"

~
:~:~~~
CHCK ~

+5V

so. 32

11001 ..
110015

GND
A23
A2.
A21

eND ~
IRQO. .
IAQOII ~
.RQ07 • a
GND21

-12V

MICRO CHANNEL

A

A1815
""5111
ON017
A14111

PSBUS B

ARBO
ARBOI ~

PSBUS

GND

aND 13

A17, ...

A3

..oLo

REFRESH.

~
~

A231
A2'7
A211
GIlD.
A2010

PREEMPT...

-

i:1-

eND
IRQ12.

OND

830-158

292060-32

Figure 4. PS592E·32 Digital Assembly Schematics (Continued)

1-509

(
MICRO-CHANNEL
RES.
RES •
~
RES.
~
RES.
GNO
~
016
64
017
65
016
66
GNO
022
68
023
69
RES.
~
GNO
~027
72
028
73
74

g..

."

iFi
c

;

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en
CD
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2!
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o

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,

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PSBUS B ~~~

()

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3

01129
A30
A31
GNO
RES.
RES.

In

o

3

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(1)

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-

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3
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en

.

ADDRESS 0-23
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()

III
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0

a

5

4D

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50
7 eo
B 70
9 eo
10 90

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2Q

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22
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20

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17

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LA' 2
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50

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74ALS38
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13

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IR:012.

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LSBHE.

A2
A1
NJ

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LA7
LAO

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1..A3
1..A2
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2

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4

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20
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1
2

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4

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2

3

,

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-

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----

SSHE·

R

74ALS3e
ENINT3

18

LCDSFOBK

LCDSETUP.

W

[ADDRESS 0 , 4
LRE'AO •
LWRITE_

'4
1N4148

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292060-35

1

HFO.
HFh

IOWR_
CSH·

•

11

ClIO.

18

IN

3

PIPELINE

LREAD.

4

LWRITE·

~

e

>

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10
13
12
II

N

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en

en

LAI4
LAI3
LAI2
LAII
LAIO
LAII

UI
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m

~

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!2

LAII

!!!!.

LA7
LA8
LAS
LA4

~

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en
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LA2

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intJ

AP-326

APPENDIX A
Signal Name
ABOVE

Description
POS register bit that determines
mapping below or above 1 Meg.
data latch clock (direction: local
memory to latch)
data latch DO-DI5 clock (direction: host to latch)
data latch D16-31 clock (direction: host to latch)
local SRAM chip selects (low
and high banks)
CDEN
POS register bit for card enable
active host cycle enveloping sigCYCACT
nal
partial active host cycle envel'
oping signal
direction signal for data latchDIItes/trasceivers
ENINT3,7,9,12
POS register bits determining
the selected interrupt signal
EPROMCS_
EPROM chip select signal
general chip select (output of
82561)
data latch DO-DI5 ,transceiver
tristate enable
data latch D16-D31 transceiver
tristate enable
HFOU,HFIU
unqualified, active high host request signal
active low host request signals
to the 82561
IORD_I MWIt- read from non-SRAM port or
'write to SRAM (output of
82561)
IOWItwrite to non-SRAM port (output of 82561)
INTOUT
Interrupt output of the 82561

Signal Name
LAO-LAI4
LCDSETUP_
LCDSFDBK

, Description
latched host address lines
latched card set up signal
latched card select feedback signal
load command register
LDO-LD31
local data bus
loopback signal
LPBKLPIPECYC
latched pipeline cycle signal
LREAD,LWRITE
latched read and write signals
latched byte high enable
L56IWIN_
latched 82561 subwindow
MAO-MAI2
memory address lines (output of
82561)
MEMREQ_
memory request' from the host
memory output enable (output
of 82561)
POSLDCNF_
load POS configuration register
POSRDCNF_
read POS configuration register
command register bit determinPROM
ing PROM vs EPROM paging
PROMCS_
PROM chip select
command register bit determinRAM
ing RAM vs. ROM paging
read f!om the status, register
unlatched read or write (decode
RDWR
of SO_ and SI_)
SX
select between latched and real
time data
transceiver!latch enable signals
(output of 82561)
561BEO_, 56IBE1_ low word and high word enable
signals (input to 82561)
IORDY output of 82561
561IORDY

1-518

APPLICATION
NOTE

AP-328

August 1989

PC592E
Buffered LAN Adapter Solution
for the IBM PC-XT and PC-AT*

DARYOOSH KHALILOLAHI
TECHNICAL MARKETING ENGINEER
TSVIKA KURTS
SYSTEM VALIDATION GROUP

'IBM, PC-XT and PC-AT are trademarks of International Business Machines.

Order Number: 292063-001
1-519

inter

AP-328

1.0 INTRODUCTION

2.2 Terminology'

In recent years IBM PC·AT*s and compatibles have
become the most popular personal computers. Judged
by the amount of adapter hardware and application
software developed for them, the trend seems likely to
continue in the near future. Introduction of the Extend·
ed Industry Standard Architecture (EISA) is another
reason supporting this prediction.

The following table shows the terminology used in this
document.

The role of local area networks (LANs) expands as the
role of the personal computers in the office environ·
ment increases. Some examples of the benefits provided
by networking are sharing expensive peripherals (to re·
duce the cost); sharing a single data base (to improves
data control and security), and having electronic mail
capabilities (to improve communication).
The best choices for Local Area Networks are those
that provide low cost, reliable operation, ease of expan·
sion, and the backing of major VLSI manufacturers.
The 82592/82560 is an ideal choice for 16·bit, buffered
adapter applications. The high level of integration re·
duces the component count and the design cycle. The
combination provides high performance and competi·
tive cost.
The PC592E is a 16·bit, nonintelligent, buffered slave
adapter design. It interfaces the IBM PC·AT or PC·
XT* or compatibles to an Ethernet network. The 82592
LAN Controller and 82560 host interface and DMA
Controller are used to receive and transmit frames be·
tween the network and local memory (16 kB). The
PC592E can perform zero wait state memory data
transfers on the PC bus. The design permits the use of
interchangeable network serial interface modules for
Ethernet*', Cheapernet and TPE applications.

2.0 OBJECTIVE
This application note demonstrates how to use the Intel
82560 and 82592 to build a high·performance, cost·ef·
fective PC·AT LAN adapter that implements the tradi·
tional buffered architecture.

2.1 Acknowledgements
We acknowledge and thank Yosi Mazor and Joe Dra·
gony, of Intel's (Folsom, Calif.) Data Communications
Focus Group, for their work in developing the hard·
ware and the software and their contribution to this
application note.

Symbol

#

&

Description
at the end of a signal name indicates
active low
logical OR
logical AND
logical INVERSION

3.0 ORGANIZATION
Section 4 provides an overview of the 82560 and 82592
functionality. The reader needs a basic knowledge of
these components to better understand the following
chapters. Section 5 provides a functional description of
the PC592E. In this section, the design is divided into
three architectural subsections (host interface, memory
subsystem, and network interface). PAL equations and
schematics are broken down according to the architec·
tural division. The last section provides the perform·
ance benchmarks for the board. Appendix A provides a
brief description of most PC592E internal signals. Ap·
pendix B provides the complete sets of PAL equations.

4.0 COMPONENT OVERVIEW
4.1 82592 LAN Controller
The CHMOS 82592 is a CSMA/CD controller with a
16·bit data path. It can be configured to support a wide
variety of industry standard networks, including Ether·
net, Cheapernet, TPE, PCNet, and STARLAN***.
The 82592 also supports Deterministic Collision Reso·
lution (DCR) applications. The 82592 consists of three
subsystems: parallel, serial, and FIFO. The parallel
subsystem provides an 8· or 16·bit interface to the ex·
ternal bus. The 82592 supports memory transfers (at up
to 16 MB/s); it accepts commands from the processor
that controls the bus and provides it with status infor·
mation. The 82592 can support simultaneous transmis·
sion and reception including autoretransmit, transmit
frame chaining, and back·to·back frame reception. The
serial subsystem consists of a highly flexible CSMA/
CD unit, a data encoder/decoder, collision detect and
carrier sense logic, and a clock generator. In high inte·
gration mode it supports NRZI, Manchester, or Differ·
ential Manchester encoding and decoding at' bit rates
up to 4 Mb/s. In high speed mode the 82592 is capable
of 20·Mb/s Manchester or NRZI encoding. The FIFO
subsystem consists of a transmit FIFO, a receive FIFO,
and control logic (with programmable threshold). A to·
tal of 64 bytes of FIFO can be divided between receive
and transmit.

'IBM, PC·AT and PC·XT are trademarks of International Business Machines Corp. '
"Ethernet is a trademark of Xerox Corp.
"'STARLAN is a trademark of AT&T.

1·520

!

infef

AP-328

4.2 82560 Host Interface and Memory
Controller

5.1 Hardware Configurable Options

The CHMOS 82560 is a high-performance DMA controller designed to work in a tightly coupled fashion
with the 82592 in a PC-XT, PC-AT or MCA adapter
application.
Two independent DMA channels support a transfer
rate of up to 10 MB/s to/from the local SRAM. Up to
16 kB of ring buffer memory can be I/O or memory
mapped into the address space. Host accesses to the
local memory can be made with zero wait states. These
accesses can be byte or word wide. The 82560 implements all of the 82592 tightly coupled functions: back
to back frame reception, bad receive buffer reclaimation, auto retransmit upon collision, and transmit
chaining.

5.0 IMPLEMENTATION
The board is divided into three sections (see figure 1),
the host interface, the memory subsystem, and the network subsystem. Both the 82592 and 82560 operate on
the IO-MHz Ethernet clock generated by the serial side.
In the rest of this section a component (designated by
its unit No. on the board and the schematic) is defined
as part of a subsystem if one or more of its output pins
are in that subsystem. To access any port on the board
(including SRAM), the host CPU generates a request
to the 82560. When in a 16-bit slot the board supports
16-bit hosts (PC-AT), otherwise it supports 8-bit hosts
(PC-XT). To enable the board the most significant bit
(bit 3) of the command register should be set to 1. In
the 16-bit configuration SRAM accesses can be word
(zero wait state or nonzero wait state) or byte wide
(nonzero wait state). All other transfers (non-SRAM)
are byte wide. In the 8-bit configuration SRAM accesses can be either with zero added wait state (pipeline
mode) or with 3 to 4 added wait states (nonpipeline
mode). The reader is referred to the table and listing in
Section 5.2.3 for a complete set of host memory cycles.

The board has seven jumpers and one switch. These can
be set to change the board configuration.
5.1.1 MEMORY MAPPING WINDOW

E 1 through E6 are used to select the lower portion of
the address window. The letter E followed by a number
refers to a unique jumper node. These two jumpers are
used to select the lower portion of the memory address
window. El, E2, E3 select the least significant bit
(MAPO) of the three bit address selector. E4, E5, E6
select the next bit (MAP1).
E7 through E9 select the most significant bit (MAP2)
of the address selector. MAP2 determines the upper
portion of the address window; namely below I Megabyte or above 1 Meg. Together with MAPO and MAP1,
these three jumper selections determine which one of
the eight 16-kB windows of host memory address is
chosen.
a) Below 1 Megabyte
memory window
OCOOOO to OC3FFF
OC8000 to OCBFFF
000000 to 003FFF
008000 to OOBFFF

MAP2
0
E9/E8
0
E9/E8
0
E9/E8
0
E9/E8

MAP1
0
E6/E5
0
E6/E5
1
E4/E5
1
E4/E5

MAPO
0
E3/E2
1
E1/E2
0
E3/E2
1
E1/E2

MAP1
0
E6/E5
0
E6/E5
1
E4/E5
1
E4/E5

MAPO
0
E3/E2
1
E1/E2
0
E3/E2
1
E1/E2

b) Above 1 Megabyte

The data transfers between the local memory and the
82592 are 16 bits wide and are controlled by the 82560
DMA channels.

1-521

memory window
FCOOOO to FC3FFF
FC8000 to FCBFFF
FOOOOO to F03FFF
F08000 to FOBFFF

MAP2
1
E7/E8
1
E7/E8
1
E7/E8
1
E7/E8

(factory
default)

intJ

AP-328

address decoder (U1 and V2) and its latch (V4); the
data latches/transceivers (V8 and V9), the high memory bank to D7 -0 data transceiver (VlO), and their control (V5); the host request generator (U2); and the
memory and peripheral controller (U6).

5.1.2 INTERRUPT
A switch is used to determine the interrupt line selected
as shown below.
PC bus Interrupt
Switch position
IROp
IR07
IR09
IR012

1 (factory default)

2
3
4

5.2.1 .cOMMAND AND STATUS REGISTERS
The command register is four bits wide.

3

I

5.1.316- OR a-BIT HOST SUPPORT

Jumper E16 through E18 is used to select the source of
the BHE_. In a 16-bit sI0t'E16/E17 should be selected. This connects the SBHE_ from the PC bus to the
BHE_ of the board. In an 8-bit slot E18/E17 should
be selected. This connects the inverted SAO to the
BHE_ of the board. The factory default is E16/E17
(PC-AT).

2

BOARDEN

I

PIPELINE

I

1

0

PROM

RAM

After power up; or reset, the board is disabled. When
disabled, the board recongnizes only host requests to
access its command and status registers.
Bit 0, Bit 1: Determine the memory port being accessed.
Bit 1
Bit 0

o

PCXT is a signal on the board that can be read by the
host (through the status register) to determine if the
board is plugged into a 16- or 8-bit slot. This signal is
connected to the GND pin of the D connector (pin 18)
of the 16-bit I/O channel. A l-kohm pull-up resistor
connects the node to the + 5-V supply. Therefore in a
16-bit slot PCXT will be read as 0, otherwise it will be
read as 1.

o

o

1

o

1

EPROM access
RAM access
PROM access
Reserved

Bit 2: Determines the mode for accessing the buffer
memory. When 0 the host accesses to the local
SRAM are made with added wait states. When I,
and the 82560 is configured for the pipeline
mode, the host accesses to the local SRAM are
made with no added wait states '(pipelined data
transfers). This bit and the bit 0 of the 82560 host
mode register should always be set to the same
value before an SRAM memory access is attempted.
Bit 3: Is the board enable bit. After power up, or reset,
this bit should be set to 1 in order to access the
on-board ports (SRAM, ,PROM, EPROM, 82560
regisiers, and 82592 registers).

5.1.4 CLOCK SOURCE
Jumper E19 , E20, E21 selects the source of the clock
for the 82592 and the 82560.
Jumper position
Clock source
E19/E21
lO-MHz serial clock from the serial
unit connected to TXC of 82592 (fac,tory default)
E20/E21
external crystal connected to Xl of
82592

The following is the PAL (VII) equation for writing to
the, command register.

= !( !GCS_ & !L560WIN_ & !IOWR_l

5.2 Host Interface

LDCMD_

This subsystem consists of the command register (U4),
the status register (U12), and their control (U11); the

The status is seven bits wide read only register.

6

5

4

3

2

PCXT

MODT1

MODTO

BOARDEN

PIPELINE

1-522

o
PROM

RAM

intJ

AP-328

The four least significant bits are the contents of the
command register.

!L560WIN_

= (SAI3

Bit 4, Bit 5: Are generated by the network module and
determine the type of network module installed.
Bit 5
Bit 4
o
0
Ethernet
o
Cheapernet
Reserved
o

!MEMCSI6_

= ( !LSBDEC_

&

SAl2

&

SAll

« SAIO « SA9 & SA8 «
SA7)

TPE

The reserved combination is for future use.
Bit 6: Is read to determine if the board is plugged into
an 8- or 16-bit slot. In a 16-bit slot a 0 is read,
otherwise a I is read.
The following is the PAL (Vll) equation for reading
the status register.

RDST_

= !( !GCS_

& !L560WIN_ & !IORD_)

& LMSBDEC
RAMEN & L560WIN_ &
!SAO & !BHE_)
enable (ZEROWS_) = (RAM & !LSBDEC_ &
LMSBDEC & BOARDEN &
PIPELINE « L560WIN_)
ZEROWS_
= !L560IORDL
&

5.2.3 DATA TRANSCEIVERS/LATCHES
Bit 2 of the command register determines the mode in
which the host accesses the local SRAM.
In the non pipeline mode the data transceivers/latches
act as simple transceivers. The cycles are extended by
pulling IOCHROY low until the transfer to/from local
memory is completed. All non-SRAM accesses are in
non pipeline mode.

5.2.2 ADDRESS DECODER
The highest bits of the address (LA23 - 20) are decoded
in V2. The output is the MSBOEC signal, which is
latched on the falling edge of the BALE in V4. The
latched signal (LMSBOEC) is input to the other PAL
(VI). SA19-14 are decoded in this PAL for the lower
portion (within I Megabyte) of the address mapping.
The output is LSBOEC.
Three signals from the board provide the handshake
required by the host:

IOCHRDY. MEMCSI6_. and ZEROWS_.
The relevant PAL equations (of VI and V2) are given
below. The reader is referred to the appendix A for the
decription of internal signals.

RAMEN
MSBDEC

= (RAM & BOARDEN)
= ( !LA20 & !LA21 &

!LA22

&

!LA23 & !MAP2) #

(LA 20 & LA21 & LA22 & LA23
& MAP2)

!LSBDEC_ = ( (SAI9 & SAl8 & !SAl7
!SAI6 & !SAI5 & !SAI4
!MAPI & !MAPO) #
(SAI9 &
& SAI5
MAPO) #
(SAI9 &
& !SAI5·
!MAPO) #
(SAI9 &
& SAI5
MAPO))

&
&

SAl8 & !SAI7 & !SAI6
& !SAI4 & !MAPI &
SAI8 & !SAl7 & SAl6
& !SAI4 & MAPI &
SAl8 & !SAI7 & SAl6
& !SAI4 & MAP I &

In pipeline mode the data transciever/latches act as
data latches. In this mode a read ahead or write behind
operation is performed after every host request to the
82560. These accesses are to sequential locations in the
local SRAM. In this mode no wait states are asserted.
The direction of the pipeline transfer is determined by
the value of bit I of the 82560 host mode register. In
read cycles, after the current transfer, the 82560 updates the buffer with the contents of the next local
memory address. This is called "read ahead" (in anticipation of the next host read request). In write cycles the
data is copied from the data latch to the local memory
after the host has finished writing to the data latch.
This is called "write behind."
In the 8-bit configuration, during odd byte memory accesses the transceiver VIO becomes transparent. Thus
the data path would be from/to the high bank of
SRAM (V13), through UIO, to the low byte of data bus
(07-00).
In the non pipeline mode V8 and V9 serve as simple
data transceivers. All non-SRAM accesses use the even
byte (07 - 00). In the 16-bit configuration the value of
SAO and SBHE. determines which bank of memory (or
both) should be accessed.
The following table shows different types of memory
cycles and the expected value of the transceiver and
data latch (74ALS646) control signals. B is the host
side and A is the local bus side. When SX is I, stored
data is selected. When 0, real time data is selected. X
stands for don't care.

1-523

inter

AP-328

cycle Pipeline PCXT BHE_ SAO MEMW_ MEMR_ G1L G1H_ G2_ CBA1_ CBA2_ SX
1
1
1
0
0
0
0
1
0
0
0
0
1
2
1
0
0
1
1
0
0
1
0
0
0
1
X
X
1
0
3
0
0
0
4
0
0
1
X
1
0
0
0
X
5
0
0
0
0
X
X
0
0
1
0
0
1
0
1
6
0
1
0
1
7
1
0
1
0
0
1
1
0
1
0
0
0
0
0
1
8
1
0
9
1
0
1
1
0
0
1
1
10
0
1
0
X
X
0
1
1
0
t
0
X
1
1
0
11
0
0
1
X
0
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle

1 : PCAT pipelined (word-wide) memory write
2 : PCAT pipelined (word-wide) memory read
3 : PCAT nonpipelined even-byte memory access
4 : PCAT nonpipelined odd-byte memory access
5 : PCAT nonpipelined word-wide memory access
6 : PCXT pipelined even-byte memory write
7 : PCXT pipelined even-byte memory read
8 : PCXT pipelined odd-byte memory write
9 : PCXT pipelined odd-byte memory read
10 : PCXT nonpipelined even-byte memory access
11 : PCXT nonpipelined odd-byte memory access

The control signals to the transcievers/latches are generated by the PAL U5, which realizes the above table.

lGIL_

=(MEMREQ

& PCXT & SAO_ & lMEMR_l # (lPCXT & PIPECYC & MEMR_l #
( lXCVL & SAO_l # (lHFO_ & lHFLl # (lXCV2_ & HFLl

lG2_

= (PIPECYC & lMEMR_l # (lXCVL
= (PCXT & MEMREQ & lSAO_l

lCAB_

= ( !IOWR_

lCBAl_

=(PIPECYC

lGIH_

&

lBHE_l # (lXCV2_

& HFLl

& lXCV2_ & HFLl

&

lMEMW_

&

lPCXTl # (MEMREQ

& PIPELINE &

lMEMW_

SAO_l
lCBA2_
SX
lDIR_

= (PIPECYC

=(MEMREQ
=( lXCV2_

& lMEMW_l

& PIPELINE #

lIORD_

& HFL & lIORD_l

& PIPELINE &

# (lMEMW_l

1-524

lXCV2_

& HFl_l

& PCXT &

inter

Ap·328

5.2.4 HOST REQUEST GENERATOR

The following table shows how different ports on the board are accessed. BOARDSEL refers to the board address
decoded, that is the logical AND of LSBDEC and LMSBDEC. X stands for don't care.
BOARDSEL L560WIN_ BOARDEN RAM SBHL* HF1_ HFO_
X
X
X
X
0
1
1
Idle
X
X
0
0
0
GCS_ access: Command/Status
0
GCS_ access: ROM *.
0
X
0
0
1
1
X
1
0
SRAM access
0
X
1
0
1
82560 register access
• In the a·bit configuration, inverted SAO serves as SBHE_.
•• ROM refers'to either PROM or EPROM. Bit 1 of the command register determines which.

The following PAL equations realize the above table. HFO_ and HF1_ are the request lines to the 82560.

mFO_

mFL

=

=

( !MEMW_
( !MEMW_
( !MEMW_
( !MEMR_
( !MEMR_
( !MEMR_

&: L560WIN_
&: L560WIN_
&:!L560WIN_
&: L560WIN_
&: L560WIN_
&:!L560WIN_

( !MEMW_
( !MEMW_
( !MEMR_
( !MEMR_

&:
&:
&:
&:

&:
&:
&:
&:
&:
&:

BOARDSEL
BOARDSEL
BOARDSEL
BOARDSEL
BOARDSEL
BOARDSEL

&:
&:
&:
&:
&:
&:

BOARDEN &:
BOARDEN &:
!BHE_) #
BOARDEN &:
BOARDEN &:
!BHE_)

REQEN)
#
!PIPELINE) #
REQEN) #
!PIPELINE) #

!RAM &: BOARDSEL &: BOARDEN) #
BOARDSEL &: !L560WIN_) #
!RAM &: BOARDSEL &: BOARDEN) #
BOARDSEL &: !L560WIN_)

5.2.5 MEMORY AND PERIPHERAL
CONTROLLER

To access any port on the board the host generates a
request to the 82560. The 82560 will then synchronize
the request and perform arbitration (with any active
local DMA request). It then asserts the proper memory
or peripheral control signals.
The 82560 also supports the interrupt function. The
interrqpt initiated by either the 82592 or the 82560 is
passed to the host system through one of the four interrupt lines (depending on the position of the switch).
In nonpipeline mode 10CHRDY is pulled low immediately after the board address is decoded. It goes high a
programmable number of clock transitions after the
host cycle starts. The 82560 register bit that can affect
it are: HRDY delay, HRDY delay reference source, 10
and access delays. The reader is referred to the 82560
data sheet for more details. In pipeline mode the 10CHRDY remains high until after the request is removed. Then the 82560 HRDY output goes low while
the local bus cycle is being completed. 10 CHRDY will
, be pulled low while the board address decode is 'active
and 82560 HRDY output is low. In either case the
10CHRDY is tristated until the board address is de·
coded.

enable (IOCHRDy) = (LSBDEC & LMSBDEC)
IOCHRDY = !560I0RDY_
# (!LSBDEC_ & LMSBDEC &. lBOARDEN . &
L560WIN_)
# (!LSBDEC & LMSBDEC & !BOARDEN & !BSAO)
5.2.5.1 Nonpipeline cycles

In ALL nonpipeline cycles (SRAM or otherwise) 10CHRDY is pulled low within 30 ns after the address on
the PC bus becomes valid. It remains low until the
82560 HRDY output goes high, then it goes high.
The memory address input to the 82560 in th~ nonpipline mode is the same as the host CPU address shifted
by one bit (SAl goes to AO input of 82560). During
byte-wide memory accesses byte enable inputs of the
82560 (BEO_ and BE1_) determine which bank of
SRAM is being accessed.
The output address of the 82560 is the same as its input
address, except that its three most significant bits (12,
13, and 14) are logically OR'd with the three least sig·
nificant bits of the 82560 host address register. The low
bank of memory is accessed for even-byte addresses and
the high bank or odd-byte addresses.

1-525

inter

AP-328

',,--. ___--II
82560 HRDY

''----II

IDCHRDY

292063-3

programmable). Autoretransmit, back-to-back frame
reception, and bad receive buffer reclamation are all
performed without CPU intervention. '

5.2.5.2 Pipeline Cycles
. During SRAM pipeline cycles IOCHRDY stays high.
It goes low after the cycle is over (HF_ removed). This
is when the 82560 performs read· ahead or write behind
operations. Read ahead means that the next word (or
byte in the case of 8-bit configuration) of data is copied
from the local memory into the data latches in anticipation of the next request. Write behind means that data
is first latched in the data latch(s) and then the 82560
copies the data into the local memory. The memory
address in this mode is provided by the host address
register, which is incremented by one after each 82560
transfer. To change the direction of the transfer the
82560 Host mode register should be accessed first and
its bit 1 changed.

The 82560 in the 82592 TCI mode supports transmit
chaining. DMA channels are also used to configure the
82592 and to read its 69 bytes of internal information
through the dump command.
The arbitration between the two DMA requests, and
between the host request and the DMA request, are
performed by the 82560 local bus arbiter function. .
Transmit buffer size (including the configuration block)
can be about two kilobytes. It should stop 128 bytes
before the end of the adapter memory. The last 128
bytes of address (highest addresses) are for accessing
the 82560 and the command and the status registers.

5.3 Memory Subsystem
The receive memory buffer can occupy the rest of the
local memory. It can be arranged as a ring buffer and
managed by the 82560. The lower limit register of the
82560 holds the starting address of the ring, and its
upper limit register holds the ending address of the
ring. The 82560 performs the wraparound without
CPU intervention. The stop register of the 82560 points
to the last receive buffer location processed by the host
CPU. The 82560 generates an interrupt to the host if
the current address register of the channel reaches the
stop register of that channel.

The memory subsystem consists of the network address
PROM (U15), the low bank of SRAM (U14), the high
bank of SRAM (U13), an optional EPROM (U16),
control PAL (UU, U5), and the 82560 memory controller (U6).
All controls are generated by the 82560, except for chip
select for the EPROM and the PROM.

EPROMCS_ = !( !GCS_ & !IORD_ & !PROM &
L560WIN_l
PROMCS_ =!( !GCS_ & !IORD_ & PROM &
L560WIN_l

For more information about DMA transfers and the
format of the transmit and receive frame, the user is
referred to the 82560/82561 Technical Reference ManualOrder #290198.

5.4 Network Interface
The network interface consists of the 82592 LAN controller (U7), the 82560 DMA controller (U6), and a
plug-in analog module (Ethernet, CNet, or TPE).
5.4.1 DMA TRANSFERS
Two independent DMA channels of the 82560 are used
to transmit and receive frames. Each word-wide DMA
transfer can have a duration of 200 to 500 ns (82560

5.4.2 SERIAL INTERFACE
The 82592 CSMA/CD controller is used in the highspeed mode. The 82C501AD performs Manchester encoding and decoding; it also provides a watchdog timer,
collision detection, and transmit/receive clack generation. Using the loopback modes, the transmitted data is
routed to the receive path (at the 82592, the
82C501AD, or on the wire). This feature is useful for
controller and physical layer diagnostics.

1-526

inter

AP-328

5.5 Schematics
015-08

07-00

PC BUS

LATCH/
XVR

SRAM
High Bank

PALS

1
-'--

XVR

-SRAM
Low Bank

LATCH/
XVR

I
592

560

I
COM/
STATUS
REG.

P
R
0
M

E
P
R
0
M
292063-4

Figure 1. PC592 Block Diagram

1-527

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30
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~

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292063-5

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292063-6

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292063-9

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19
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17
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---_.-

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(5 HEET 3)
5 HEET 3)

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(5 HEET 8)

REQEN
IOCHRDY

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(5 HEET 2)

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292063-11

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292063-21

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intJ

Ap·328

6.0 PERFORMANCE

state cycles should improve the network performance
by about 12% over wait state cycles.

The PC592E design is expected to provide very high
performance compared to many commercial adapters.
When the board is configured for. pipeline mode, it can
perform zero wait state cycles on the PC-AT bus. Without this feature each host access would be with three or
four additional wait states, resulting in a less efficient
use of the host bus bandwidth. In addition to reducing
the host bandwidth consumption, performing zero wait

Network performance can be influenced by how fast
the station can retransmit after a collision. Measurements show that an 82592/82560 design in the 82588
TCI mode can retransmit 4.8 /LSec after collision. In
the 82592 TCI mode this time is reduced to 2.1 ,...Sec.
The 82592 built in FIFOs reduce the possibility of underruns and overruns.

1-539

inter

AP-328

APPENDIX A

APPENDIX A
Signal name
BALE

BHE
BOARDEN
CAB
CBAI
CBA2CSL -; CSH_
DIREPROMCS
GCS
GlLGIHG2 HFO ,HFl
IOCHRDY IORD / MWR
IOWRINT LA23-LA20
LDCMD
LDO-LD15
LMSBDEC
LPBK
LSBDEC
L560IORDY
L560WIN MAPO,MAPI
MAP 2
MAO-MA12
MEMR
MEMREO
MEMW
MODTO,MODTl
MOE
MSBDEC
MEMCS16
PCXT
PIPECYC
PIPELINE
PROM
PROMCS
RAM
RAMEN

RDST
REOEN
RESET
5BHE
SX 5AI9-SAO
XVRI ,XVR2 .
ZEROW5
56 0 IORDY_

Description

-------------------------------------------------------------

address latch enable (from the PC bus)
byte high enable (input of 82560)
board enable (command register bit 3)
data latch clock (direction: local memory to latch)
data latch 07-00 clock (direction: host to latch)
data latch D15-D7 clock (direction: host to latch)
SRAM chip select outputs of 82560 (loW and high bank)
direction signal for data latches/transceivers
EPROM chip select signal
general chip select (output of 82560)
data D7-DO latch/transceiver tristate enable
data 015-D8 latch/transceiver tristate enable
byte swap transceiver tristate enable
active low host request signals to the 82560
IOCHROY to the PC bus
read from non-SRAM port or write to SRAM (output of 82560)
write to non-SRAM port (output of 82560)
interrupt output of the 82560
unlatched host address lines
load command register
local data bus
latched most significant bit decode
loopback signal
least significant bit address deccode
latched (falling edge of BALE), inverted 560 HRDY output
latched 82560 subwindow
Jumper selections for lower portion of the address mapping
JUmper selection that determines mapping below or above 1 Meg.
memory address lines (output of 82560)
memory read (from the PC bus)
memory access requested by the host CPU
memory write (from the PC bus)
network module identifier (bits 4 and 5 of the status register
memory output enable (output of 82560)
most significant bit decode (output of U2)
memory chip select 16 (to the PC bus)
8-bit vs. 16-bit configuration
pipeline cycle
pipeline mode (comamnd register bit 2)
command register bit determining PROM vs EPROM paging
PROM chip select
command register bit determining RAM VS. ROM paging
RAM and board enabled
read from the status register
memory request enabled (output of Ull)
reset (from the PC bus)
byte high enable (from the PC bus)
select between latched and real time data
latched PC address lines
transceiver/latch enable signals (output of 82560)
zero wait state cycle (to the PC bus)
buffered (inverted) HROY output of 82560
292063-13

1-540

inter

AP-328

APPENDIX B

.... ........•.......... -........ -... __ ...... _.-.- ........•...............
_

Module UI
5/3/89
Ti tie 'MEMCSI6
REV 4.0
Daryoosh Khalilolahi,
Intel Corporation
PAL20LBB (15ns)'
PC592PI

-

LMSBDEC
BHL
RAMEN
MAPO
MAP I
SA7
SA8
SA9
SAIO
SAl1
SAl 2
GND

'P20L8' :

Device
Pin
Pin
pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

VCC
MEMeS I 6_
LSBDEC_
L56OWIN_
SAO
SAI9
SAI8
SAt7
SAI6
SAI5
SAI4
SAI3

"I"

I:
2:
3:
4:
5:
6:
7:

"I"

" I"
"I"

Itl"

"I"
"I"
"I"
"I"
"I"

8:

9:
10 :
It:
12 :

"1"

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

24:
22:
15:
21:
20:
23:
19 :
18 :
17:
16 :
14 :
13:

"0"
"0"
"0"

"I"
"I"
"I"
"I"

"I"

III"
"I"
"I"

" SIGNAL DEFINITIONS:
"INPUTS: LMSBDEC
"
SAO
RAMEN
MAPO,MAPI
SA7-SAt9
BHL

%
%
%
%
%
%

latched'most significant bits (LA23-LA20) decode
host address input
RAM selection anded with board enable
Jumper selection for the mapping window.
Latched address lines from the PC bus
Byte high enable

"OUTPUTS: MEMeS 16_
LSBDE<=L560W1N_

% MEMCS16_ for the below 1 Meg. windows
%'Least signifiacnt bit address decode
% 82560/command subwindow addre.s decode

EQUATIONS
" the corresponding addre •• lines are compared with MAPO and MAPI to generate
" the least significan,t bits address, decode.
- «SAt9
(SA19
(SAt9
(SAt9
(SA19

I LSBDE<=-

&
&
&
&
&

SA18
SAI8
SA18
SA18
SAt8

&
&
&
&
&

ISA17
I SAt 7
ISA17
ISA17
ISAt7

&
&
&
&
&

ISAt6
I SA16
SA16
SA16
SA16

&
&
&
&
&

I SAlS
SA15
ISAlS
SA15
SAIS

&
&
&
&
&

I SAl4
ISA14
ISA14
ISA14
ISA14

*'
*'
*'

& IMAPl & IMAPO)
& IMAPI & MAPO)
& MAPI & IMAPO)
& MAPl & MAPO»:
& MAPI & MAPO»:

"If SA7 through SA13 are all one, assuming that higher bits of address match,
" the address is for accessing the 82560 or cOlIlDand/status register.
IL560W1N-

s

(SA13 & SA12 & SAil & SAIO & SA9 & SA8 & SA7):

" a 16 bit memory transfer is recognized if the address for SRAM access is
" matched and both SAO and BHL are low.
IMEMCSI6_ -

(LMSBDEC & RAMEN & I SAO & I BHL & L560W1N-) &
«SA19 & SAlS & ISAl7 & ISA16 & ISA15 & ISAl4 &
(SA19 & SAlS & ISA17 & ISAt6 & SAlS & ISA14 &
(SA19 & SAIS & ISA17 & SAl6 & ISAIS & ISA14 &
(SA19 & SA18 & ISA17 & SA16 & SAl5 & ISA14 &

IMAPI
IMAPI
MAPI
MAPI

&
&
&
&

IMAPO) *'
MAPO) *'
IMAPO) *'
MAPO»:

end Ul:
292063-22

1-541

inter
**.** ••

Ap·328

_._.*.**.*._- ••.... *--.-.... _-_ ... -------_ ... _.. _-_ ........ ,..... .

Module , U2
Ti tIe
unlatched address decode and host interface
Daryoosh Khalilolahi, Intel Corporation
PAL20LBB (15ns)'
PC592P2

Device

RAM
LSBDEC"":'
L560WHL
LA20
LA21
LA22
LA23
BHIL
MAP 2
MEMN_
MEMIL.
GND

Pin
Pin
pin
Pin'
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

REV 5.0

5/10/89

'P20LB' ;

1;
2;
3;
4;
5;
6;

Pin
vee
REQEN
Pin
Pin
MEMREQ
pin
BOARDEN
PIPELINE Pin
Rin
LMSBDEC
Pin
MSBDEC
RAMEN
Pin
BFO_
Pin
HF1_
Pin
ZEROWS_
Pin
L560IORDYJ'in

"I"
"I"

"I"

"I"
"I"
"I"
Itl"
"I"

7;

8;
9;
10;

,. I
I"

II

II

"1"

11;

12;

24;
H;

"I"
"0"
"I"
"I"
"I"

22;

"0"
"0"

17;
16;
13 ;
23;
15;
2();
21 ;
19;
14;

"0"
"0"
"0"
"I"

"Definitions
BOARDSEL'· ILSBDEC-& LMSBDEC;
" SIGNAL DEFINITIONS:
"INPUTS: RAM
LSBDEC
"
LMSBDEC
L560WIN_
LA20-LA23
BHlL
MAP2
MEMt\!...

MEMIL
PIPELINE
BOARDEN
L560IORDY_
"OUTPUTS: MSBDEC
HFO_,HFl_
"
ZEROWS_
IOCHiIDY
MEMREQ

RAM selected
% least significant bits address decode
% latched most significant bit address decode

%

% 560/command register sUUwind~
% unlatched address lines

byte high enable
jumper selection for
memory write command
memory read command
% command register bit
% command register bit
% latched and inverted
%
%
%
%

%
%
%
%
%

below/above 1 Meg.
2-, indicating pipeline mode
3, board enabled
82560 HRDy output

Most significant bits address decode
host request to the 82560
0 wait state output to the PC bus
output to the PC bus
host request to access SRAM

E~ATIONS

" HFO_ is asserted during SRAM and GCS (general purpose chip select) cycles.
(IMEMN_ & L560WHL &
(1MEMt\!... & L560WIN- &
(IMEMN_&IL560WIN_&
( IMEMIL & L5.6OWIN- &
(IMEMIL& L560WIN-&
(IMEMIL &IL56OWIN- &

BOARDSEL
BOARDSEL
BOARDSEL
BOARDSEL
BOARDSEL
BOARDSEL

&
&
&
&
&
&

BOARDEN &
BOARDEN &
IBHlL) •
BOARDEN &
BOARDEN &
IBHIL);

REQEN)
•
IPIPELINE).
REQEN) , •
IPIPELINE).

" HF1_ is asserted during 560/592 register accesses'and also GCS accesses.
" That Is all non-SRAM cycles.
IHF1_ - (IMEMW_ & IRAM & BOARDSEL &' BOARDEN) •
( IMEMW_ & BOARDSEL & IL56OWIN_) #
292063-23

1-542

intJ

Ap·328

&

( !~ & !RAM
BOARDSEL & BOARDEN) ~
(!~ & BOARDSEL & IL56OWIN_);
.. 0 Wait states cycles are performed only when accessing the SRAM and in the
" pipeline mode.
enable ZEROWS_ ZEROWS_

=

(RAM & BOARDSEL & BOARDEN & PIPELINE & L56mWIN_);

L560IORDY_;

MEMREQ - L56OWIN_& BOARDSEL & BOARDEN & RAM;
" most significant bits of address are compared with jumper node MAP2.
MSBDEC

((ILA20 & ILA21 & ILA22 & ILA23 & IMAP2) ~
(LA20 & LA21 & LA22 & LA23 & MAP2));

=

RAMEN = RAM & BOARDEN;
end U2;

*** •••• *.** •• ** •••••• ******************.************************.*****
Module US
Title 'Local bus control
REV 5.0 7/7/89
Daryoosh Khali10lahi,
Intel Corporation
PAL20LS (25 ns)'
Device

PC592P3
PCXT
SAO_
BUlL
HFO_
MEMR....
MEMN_

MEMREQ
HFL
IORD_
I OWL
XCVL
GND

Pin
Pin
pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

'P20L8' ;

nln

1;
2;
3;
4;
5;
6;
7;
8;
9;
10;
11;

VCC
GIL_
G2_

"In
"I"
I'I"
ItI"
"1 11

CAB_

SX
DlL
GIlL
CBA1_
CBAL
PIPELINE
unused
XCV2_

., I"
"I"
"I"
"I"
"I"

12;

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

24;
22;
21;
20;

"0"
"0"

19;

"0"
,"0"

18;

"0"

15;
17;

"0"

16;
14;

tlO"
II I"

23;
13;

"I"
"I"

"0"

"Definition
PIPECYC

-

(HFL & IHFO_ & PIPELINE);

"The following table shows different types of memory cycles and the expected
"value of the transceiver and data latch (74ALS646) control signals. B is the
"host side and A is the local bus side. When SX is 1, stored data is selected.
''When O. real time data is selected. X stands for don't care.
::cyc 1 e
1
2
3

4
5
6
7
8
9
10
11

Pipeline

--------

PCXT

BHlL

1

0
0
0
0
0
1
1
1

0

1

1

0

0
0

1
1

0

1
1
0
0
0

1
1

0
0
1
0
0
1
1

1

SAO
0
0
0
1
0
0
0
1
1
0
1

MEMN_ MEMR....
0
1
X
X
X

1
0

X
X
X

0
1

1
0
1
0

X

X
X

0
1

.x

GIL- GIlL G2_ CBAl_ CBA2_ SX
0
0
0
1

0
0
0
0

1
0
1

0
0
1
0
0
1
1
0
0
1
0

1
1
1
1

1
1
1
0
0
1
0

0
1
1
1
1
0
1
1
1
1
1

0
1
1
1
1
1
1
0
1
1

1

1
1
0
0
0
1
1
1
1
0
0

292063-24

1-543

infef

AP-328

.. cycle 1
, cycle 2
cycle 3
cycle 4
cy,cle 5
cycle 6
cycle 7
cycle 8
cycle 9
cycle 10
cycle 11,

PCAT pipel ined (word-wide) memory wri te
PCAT pipel ined (word-wide) memory read
PCAT nonpipelined even-byte memory access
PCAT nonpipelined odd-byte memory access
PCAT nonpipelined word-wide memory access
PCXT pip~lined even-byte memory write
PCXT pipelined even-byte memory read
PCXT pipelined odd-byte memory write
?CXT pipelined odd-byte memory read
PCXT nonpipelined even-byte memory access
: PCXT nonpipelined odd-byte memory access

" SIGNAL DEFINITION
"INPUTS:
"

.."OUTPUTS:

PCXT
SAO_
MEML
MEMN_
IORD_
lo.vIL
XCVl_
XCV2_
HFO_,HFl_
PIPELINE

% Jwnper slecting 8 bit or 16 bit machine
% inverted address line 0

GIL
GIlL

% Data transceiver/latch tristate enable (07-00)
% Data transceiver/latch tristate enable (DI5-D8)

GL

CAB_

CBAl_
CBA2_
SX
DIlL

% MEML from the PC bus

% MEMN_ from the PC bus

% IORD-fMEMWR- output of the 82560

% lo.vIL output of the 82560

%
%
%
%

XCVl_ output of the 82560
XCV2_ output of the 82560
host requests to the 82560
command register bit for 0 added W.S. cycles

% local bus transceiver enable signal
% Local data latch clock

%
%
%
%

latch host data (07-00)
latch host da~a (015-08)
Real time vs. latched data select
Data transceiver/latch direction

EQUATIONS
IGIL

- (MEMREQ & PCXT & SAO_ & lMEML) # (I PCXT & PI PECYC & MEML)
( IXCVl_ & SAO_) # ( IHFO_ & IHFl_) # (IXCV2_ & HFl_) ;

IGIIL

e

IG2_

- (PCXT & MEMREQ & I SAO_) ;

(PIPECYC & IMEML)

#

(IXCVl_& IBHE-)

*

#

(IXCV2_& HFl_);

- ICAIL - (I lo.vIL & IXCV2_ & HFL);
ICBAL - (PIPECYC & lMEMN_ & IPCXT)

*

(MEMREQ & PIPELINE &IMEMN_ & PCXT & SAO_)

ICBAl_ - (P I PECYC & IMmml.J;
SX

(MEMREQ & PIPELINE

*

IIORD_& PIPELINE & IXCV2_& HFl_);

IDIIL - (IXCV2_ & HFL & 1-IORD_)

*

(!MEMN_J;

end U5;
*************************************.***************************.******

Module U11
Title 'Local ports control
REV 3.0
5/3/89
Daryoosh Khalilolahi, Intel Corporation
PAL16L8B-2 (25ns)'
PC592P4

Device

'P16L8';
292063-25

1-544

inter

AP-328

LSBDEC_
IORDY_
BSAO
PCXT
GCS_
L56OWlN_
lCJNIL
IORD_
BOARDEN
GND

P
P
P
P
P
P
P
P
P
P

n
n
n
n
n
n
n
n
n
n

VCC
EPR

IOCS7

t"T---nU C -

RESET

: J'

CD

CO

en
....
0

III It

A3-A,

L::::t==:1~ so

•

~~~Y E~
ALE

6

ADDRESS AZ3-0

INTA -

DT/R
DEN

J,.

C)

CD

I\)

"D

....

()

0

l>

Is

II

1----+--.....

82288
231928-3

cl
READY
NA

ClK2~~::t:::~~=fl==;9E;,;~~~;;~~~~~~~
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ole
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LATCHES

7445373

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HIoI651629-2

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2Kx8 SRAM

2Kx8SRAM

~

~

AI0-?07_0
023-16

AI0-?07_0
015-8

l>

07-0

-g

0
0

o

I

...."""o

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I '111119

DT/P. DEN

A14-:"'1IA13-007_0

~

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A13-0
07-0

ID7-D
TXD
RXD

RESET ...= - INTR

231928-4

intJ

AP·401

The required recovery time between successive commands is 123 ns for the 82510, this is well within the
331.75 ns provided by the Basic I/O interface.

with the PC software). Also since in the PC family the
interrupt request pin of the UART is gated by the
OUT2 pin, The OUT2 pin must be available in the
16450 compatibility mode, consequently the user is restricted to an external clock source when using the
82510 in the IBM PC compatible mode. The default pin
out is given in Figure 6 and the configuration is given in
Table 1. The default register values are given in the
82510 register map shown in Figure 2 in section 3.1.1.

Write Cycle:
Addven to Write Low = 132.75 ns
82510TAVWL

= 7ns

Write Active Time

= 300.5 ns

82510 TWLWH

= 231 ns

Data to Write High

= 289.5 ns

Table 1.82510 Default Configuration
INTERRUPTS
Auto Acknowledge
All Interrupts Disabled

82510 TnvwH

= 90ns

RECEIVE
NOTE:
The interface sho~iJ. in Figure 5 uses a different address decoding scheme than that used for the IBM
PC/PC AT families, for the serial ports. Therefore,
the interface in Figure 5 can not be used in PC/PC
AT compatible designs.

Stand Ctl. Char. Recogn. disabled
Digital Phase Locked Loop (DPLL) disabled
3/16 SamplinsMajority Vote Start bit
Non J-Llan (Normal) mode

BkD, FE, OE, PE Int. enabled

3.2 Reset

FIFO
The 82510 can be reset either through hardware (Reset
pin) or Software (reset command via Internal Command Register-ICM). Either reset would cause the
82510 to return to its default wake up mode. In this
mode the register contents are reset to their default values and the device is in the 16450 compatible configuration. The Reset pulse must .be held active for' at least
eight system clocks, the system clock should be running
during reset active time.

Rx FIFO Depth = I
Tx FIFO Threshold

=0

AUTO ECHO Disabled
LOOP BACK Configured
for Local Loopback
CLOCK OPTIONS

3.2.1 DEFAULT MODES FOR 16450
COMPATIBILITY
Upon reset the 82510 will return to its Default Wake
Up mode. The default register bank is bank zero. The'
registers in bank zero are identical to the 16450 register
set, and provide complete software compatibility with
the 16450' in the IBM PC environment. The registers
in the other banks have default values, which configure
the 82510 for 16450 emulation. The recommended system clock (for PC compatibility) is 18.432 MHz, this
allows the baud rates generation to be done in a manner
compatible with the PC software. The PC software calculates baud rates based on a source frequency of
1.8432 MHz. The 82510 system clock (18.432 MHz) is
divided by two before being fed to BRG A and then is
again divided by five (BRG B default). This causes the
frequency to be divided by ten before being fed into
BRG A. 18.432 divided by ten yields 1.8432 MHz, so in
effect the BRG A is generating baud rates from a
source frequency of 1.8432 MHz (which is compatible
. '16450 is the PC AT version of the INS 8250A.

2-12

Baud Rate = 57.6K
Rx Clock = 16 x
Rx Clock Source = BRG B
Tx Clock = 16 x
Til Clock Source = BRG B
BRG A Mode

= BRG

BRG A Source = Sys. Clock
BRG B Mode = BRG
BRG B Source = BRG A Output
TRANSMIT
Manual Control of RTS
1 Stop Bit
No Parity
5 Bit Character

inter

AP-401

EXTERNAL CLOCK
04

03

05

02

06

01

07

DO
A2

TXD

VSS
OUT2

A1
AO

Vee

iii

Rii
Viii

DSR

cs

OCD

RESET

eLK

231928-7

NOTE:

Crystal Oscillator is always divided by two.
Figure 8. Disable Divide by Two

RTS
CTS

If the Crystal Oscillator is being used to supply the

OTR

231928-5

Figure 6. Default Pin Out Configuration
of the 82510

3.3 System Clock Options
The term "System Clock" refers to the clock which
provides timings for most of the 82510 circuitry. The
82510 has two modes of system clock usage. It can
generate its system clock from its On-Chip Crystal Oscillator and an external crystal, or it can use an externally generated clock, input to the device through the
CLK pin. The selection of the system clock option is
done during reset. The default system clock source is an
externally generated clock, which can be reconfigured
by a strapping option on the RTS pin. During Reset,
the RTS pin is an input; it is internally pulled high, if it
is externally driven low, then the 82510 expects to use
the Crystal Oscillator for system clock generation, otherwise it is set up for using an external clock source.
This can be done by using an open collector inverter to
RTS, the input of the inverter is the Reset signal. The
82510 has a pull up resistor in the RTS circuitry so no
external pull up is needed. In the crystal oscillator
mode the CLK/Xl pin is automatically configured to
Xl, and the OUT2/X2 pin is configured to X2. In the
External Clock mode, the CLK/Xl is configured to
CLK and the OUT2/X2 is configured to OUT2.

system clock, then the clock frequency is always divid. ed by two before being fed into the rest of the 82510
circuitry. If, however an external clock source is being
used to supply the system clock, then the user has two
options:
1. Use the System Clock after division by two, e.g. if a
8 MHz clock is being fed into the CLK pin, then the
actual frequency of the 82510 system clock will be 4
MHz (default).
2. Disable Division by two and use the direct undivided clock, e.g. if an 8 MHz clock is being fed into the
CLK pin, then the actual frequency of the 82510
system clock is also 8 MHz.
The divide by two option is the default mode of operation in the External Clock mode of the 82510. A strapping option can be used to disable the Divide By :Two
operation (For Crystal Oscillator Mode Divide By Two
must always be active). During Reset, the DTR pin is
an input; it is internally pulled high, if it is externally
driven low then the Divide By Two operation is disabled. The strapping option is identical to the one used
on RfS for selection of the System Clock source.
The 82510 system clock must be chosen with care since
it influences the wait state performance, Baud Rate
Generation (if being used as source frequency for the
BRGs), the power consumption, and the Timer counting period. The power consumption of the 82510 is dependent upon the system clock frequency. If using the
system clock as a source for the Baud Rate Generator(s), then the system clock frequency must be a baud
rate multiple in order to minimize frequency deviation.
For standard baud rates a multiple of 1.8432 MHz can
be used, in fact the 18.432 MHz maximum frequency
was chosen with this particular criteria in mind.

231928-6

1 ms is needed for Oscillator startup
Figure 7. Crystal Oscillator Strapping Option
2-13

intJ

AP-401

BACF(6)

SCLK---"

BRGA
FSt.! + COUNTER
+ LOGIC

DEF'

CLK/X1-~~

BBCF'(7-6)

SCLK .....-

RXt.!
16X
CLOCK

CLCF'(6)

BRGB
F'St.! + COUNTER
+ LOGIC

___..

CLK/X1-+.......~

TXt.!
16X
CLOCK

'---CLCF'(4)

TXt.!

Tx Ct.! BIT~_ _- ;
OF' CLCF'

\------------------~~1X

Rx Ct.! BIT _ _ _- ;
IN CLCF"

l--------------------~1X

r

CLOCK
RXt.!

CLOCK
231928-8

Figure 9. Timing Flow of the 82510

2-14

intJ

AP-401

3.3.1 POWER DOWN MODE

3.3.1.2 Idle Mode

The 82510 has a "power down" mode to reduce power
consumption when the device is·not in use. The 82510
powers down when the power down command is issued
via the Internal Command Register (ICM). There are
two modes of power down, Power Down Sleep and
Power Down Idle.

The 82510 is said to be in the Idle mode when the
Power Down command is issued and the system clock
is still running (i.e. the system clock is generated externally and not disabled by the user). In this mode the
contents of all registers and memory cells are preserved,
however, the power consumption in this mode is greater than in the Sleep mode. Reading FLR will take the
82510 out of this mode.

3.3.1.1 Sleep Mode

NOTE:
The data read from FLR when exiting Power Down is
incorrect and must be ignored.

This is the mode when even the system clock of the
82510 is shut down. The system clock source of the
82510 can either be the Crystal Oscillator or an external clock source. If the Crystal Oscillator is being used
and the power down command is issued, then the
82510 will automatically enter the Sleep mode. If an
external clock is being used, then the user must disable
the external clock in addition to issuing the Power
Down command, to enter the Sleep mode. The benefit
of this mode is the increased savings in power consumption (typical power consumption in the Sleep
mode is in the range of hundreds of microAmps. However, upon wake up, if using a crystal oscillator, the
user must reprogram the device. The data is preserved
if the external clock is disabled after the power down
command, and enabled prior to exiting the power down
mode. To exit this mode the user can either issue a
Hardware reset, or read the FIFO Level Register (FLR)
and then issue a software reset (if using a Crystal Oscillator). In either case the contents of the 82510 registers
are not preserved and the device must be reprogrammed prior to operation.

4.0 INTERRUPT BEHAVIOR

4.1 FIFO Usage
The 82510 has two independent four bytes transmit and
receive FIFOs. Each FIFO can generate an interrupt
request, when the FIFO level meets the Threshold requirements. The FIFOs can have a considerable impact
on the performance of an asynchronous communications system. For systems using high baud rates they
can provide increased interrupt-to-service latency reducing the chances of an overrun occurring. In systems
constrained for CPU time, the FIFOs can increase the
CPU Bandwidth by reducing the number of interrupt
requests generated during asynchronous communications. It can reduce the interrupt load on the CPU by
up to 75%. By choosing the FIFO thresholds which
reflect the system bandwidth or service latency requirements, the user can achieve data rates and system
throughput, unattainable with traditional UARTs.

NOTE:
If the Crystal Oscillator is being used then the user

must allow about 1 ms for the oscillator to wake up
before issuing the software reset.

Table 2. The Power Down Modes
Mode
Sleep

Idle

Clock Source

Exit Procedure

Power Consumption

Data Preservation

CrystalOscill.
Automatically
Disabled

H/W Reset or
Read FLR and
Issue S/W Reset

100-900/LA

Not Preserved
Must be Reprogrammed

External Clock
Must be Disabled
by User

Enable External
Clock, Read FLR
and Issue S/W Reset
H/W Reset

100-900 !LA

Not Preserved
Must be Reprogrammed

External Clock
Running

H/W Reset
Read FLR

1-3mA

All Data Preserved
Does Not Need to be
Reprogrammed

2-15

AP-401

4.1.1 INTERRUPT·TO-SERVICE LATENCY

Going back to equation (2):

The interrupt·to·service latency is the time delay from
the generation of an interrupt request, to when the interrupt source in the 82510 is actually serviced. Its
primary application is in the reception of data. In traditional UARTs the CPU must read the current character in the Receive Buffer before it is overrun by the next
incoming character. The Rx FIFO in the 82510 can
buffer up to four characters, allowing an interrupt-toservice latency of up to four character transmission
times. The character transmission time is the time period required to transmit one full character at the given
Baud Rate. It is dependent upon the baud rate and is
given by equation (1):

Int._to_service latency < Buffer size x lO/baud rate
Int_to_service latency = # of Channels X (# of
into sources per channel)
X Time required to service interrupt

(I) Character Transmission Time

=

Int_to_service latency

=

4 X 2 X Time required to
service interrupt

The Time required to service interrupt has been calculated to be 100 f.Ls for a slightly optimized service routine. RMX86 interrupt service time is given as 250 f.Ls
and for other operating systems it should be slightly
higher.
Int_to_service
latency
= 4x2xlO0 s

Num. of Bits per Character Frame
Baud Rate

= 800 f.Ls
82510 max Baud Rate
(four byte FIFO)
82510 max Baud Rate
(one byte FIFO)

The Transmit and Receive FIFO thresholds should be
selected with consideration to two factors the Baud
rate, and the (CPU Bandwidth allocated for Asynchronous Channels is dependent upon the number of channels supported since it does not include the overhead of
supporting other peripherals) number of Asynchronous
Serial ports being supported by the CPU. In order ,to
avoid overrun, the interrupt-to-service delay must be
less than the time it takes to fill the 82510 Rx FIFO.
The relationship is given by equation (2):
(2) Int_to_service-Iatency < FIFO Size X

=

=

4 X 10/800 f.Ls
50K bits/sec
I X 10/800 f.Ls
12.5K bits/sec

4.2 Interrupt Handling
The 82510 has 16 different sources of interrupt, each of
these sources, when set and enabled, will cause their
respective block interrupt requests to go active. The
block interrupt request, if enabled, will set the 8251O's
INT pin high, and will be reflected as a pending interrupt in the General Interrupt Register (GIR) if no other
higher priority block is requesting service. If a higher
priority block interrupt is also active at the same time,
then the General Interrupt Register will reflect the higher priority request as the source of the 82510 interrupt.
The lower priority interrupt will issue a new edge on
the interrupt pin only after the higher priority interrupt
is acknowledged and if no other priority block requests
are present. Both the block interrupts and the individual sources within the blocks are ma