1990_Intel_Microcomputer_Boards_and_Systems 1990 Intel Microcomputer Boards And Systems

User Manual: 1990_Intel_Microcomputer_Boards_and_Systems

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LITERATURE
To order Intel Literature or obtain literature pricing information in the U.S. and Canada call or write Intel
Literature Sales. In Europe and other international locations, please contact your local sales office or
distributor.
INTEL LITERATURE SALES
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Mt. Prospect, IL 60056-7641

In the U.S. and Canada
call toll free
(800) 548-4725

CURRENT HANDBOOKS
Product line handbooks contain data sheets,application notes, article reprints and other design information.

TITLE

LITERATURE
ORDER NUMBER

SET OF 11 HANDBOOKS

231003

(Available In U S and Canada only)

EMBEDDED APPLICATIONS
8-BIT EMBEDDED CONTROLLERS
16-BIT EMBEDDED CONTROLLERS
16/32-BIT EMBEDDED PROCESSORS
MEMORY
MICROCOMMUNICATIONS

270648
270645
270646
270647
210830
231658

(2 volume set)

MICROCOMPUTER SYSTEMS
MICROPROCESSORS
PERIPHERALS
PRODUCT GUIDE

280407
230843
296467
210846

(Overview of Intel's complete product lines)

PROGRAMMABLE LOGIC

296083

ADDITIONAL LITERATURE
(Not Included In handbook set)

AUTOMOTIVE SUPPLEMENT
COMPONENTS QUALITY/RELIABILITY HANDBOOK
INTEL PACKAGING OUTLINES AND DIMENSIONS

231792
210997
231369

(Packaging types, number of leads, etc)

INTERNATIONAL LITERATURE GUIDE
LITERATURE PRICE LIST (U.S. and Canada)

E00029
210620

(Comprehensive list of current Intel Literature)

MILITARY

210461

(2 volume set)

SYSTEMS QUALITY/RELIABILITY

231762

Intel the Microcomputer Company:
When Intel invented the microprocessor in 1971, it created the era of
microcomputers. Whether used in embedded applications such as automobiles
or microwave ovens, or as the CPU in personal computers or supercomputers,
Intel's microcomputers have always offered leading-edge technology. Intel continues
to strive for the highest standards in memory, microcomputer components, modules
and systems to give its customers the best possible competitive advantages.

MICROCOMPUTER
BOARDS AND

SYSTEMS
HANDBOOK

1990

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors
which may appear in this document nor does it make a commitment to update the information contained
herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
The following are trademarks of Intel Corporation and may only be used to identify Intel Products:
376,386,387,486, 4-SITE, Above, ACE51 , ACE96, ACE186, ACE196,
ACE960, BITBUS, COMMputer, CREDIT, Data Pipeline, DVI, ETOX,
FaxBACK, Genius, i, t i486, i750, i860, ICE, iCEL, ICEVIEW, iCS, iDBP,
iDIS, 121CE, iLBX, iMDDX, iMMX, Inboard, Insite, Intel, intel, Inte1386,
intelBOS, Intel Certified, Intelevision, inteligent Identifier, inteligent
Programming, Intellec, Intellink, iOSP, iPAT, iPDS, iPSC, iRMK, iRMX,
iSBC, iSBX, iSDM, iSXM, Library Manager, MAPNET, MCS,
Megachassis, MICROMAINFRAME, MULTIBUS, MULTICHANNEL,
MULTIMODULE, MultiSERVER, ONCE, OpenNET, OTP, PR0750,
PROMPT, Promware, QUEST, QueX, Quick-Erase, Quick-Pulse
Programming, Ripplemode, RMX/80, RUPI, Seamless, SLD, SugarCube,
TooITALK, UPI, Visual Edge, VLSiCEL, and ZapCode, and the
combination of ICE, iCS, iRMX, iSBC, iSBX, iSXM, MCS, or UPI and a
numerical suffix.
MDS is an ordering code only and is not used as a product name or trademark. MDSCI!> is a registered
trademark of Mohawk Data Sciences Corporation.
*MULTIBUS is a patented Intel bus.
CHMOS and HMOS are patented processes of Intel Corp.
Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its
FASTPATH trademark or products.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
@INTELCORPORATION 1989

CUSTOMER SUPPORT
INTEL'S COMPLETE SUPPORT SOLUTION WORLDWIDE
Customer Support is Intel's complete support service that provides Intel customers with hardware support,
software support, customer training, consulting services and network management services. For detailed information contact your local sales offices.
After a customer purchases any system hardware or software product, service and support become major
factors in determining whether that product will continue to meet a customer's expectations. Such support
requires an international support organization and a breadth of programs to meet a variety of customer needs.
As you might expect, Intel's customer support is quite extensive. It can start with assistance during your
development effort to network management. 100 Intel sales and service offices are located worldwide-in the
U.S., Canada, Europe and the Far East. So wherever you're using Intel technology, our professional staff is
within close reach.

HARDWARE SUPPORT SERVICES
Intel's hardware maintenance service, starting with complete on-site installation will boost your productivity
from the start and keep you running at maximum efficiency. Support for system or board level products can be
tailored to match your needs, from complete on-site repair and maintenance support to economical carry-in or
mail-in factory service.
Intel can provide support service for not only Intel systems and emulators, but also support for equipment in
your development lab or provide service on your product to your end-user/customer.

SOFIWARE SUPPORT SERVICES
Software products are supported by our Technical Information Service (TIPS) that has a special toll free
number to provide you With direct, ready information on known, documented problems and deficiencies, as
well as work-arounds, patches and other solutions.
Intel's software support consists of two levels of contracts. Standard support includes TIPS (Technical Information Phone Service), updates and subscription service (product-specific troubleshootmg guides and;
COMMENTS Magazine). Basic support consists of updates and the subscription service. Contracts are sold in
environments which represent product groupings (e.g., iRMX@ environment).

CONSULTING SERVICES
Intel provides field system engineering consulting services for any phase of your development or application
effort. You can use our system engineers in a variety of ways ranging from assistance in using a new product,
developing an application, personalizing training and customizing an Intel product to providing technical and
management conSUlting. Systems Engineers are well versed in technical areas such as microcommunications,
real-time applications, embedded microcontrollers, and network services. You know your application needs;
we know our products. Working together we can help you get a successful product to market in the least
possible time.

CUSTOMER TRAINING
Intel offers a wide range of instructional programs covering various aspects of system design and implementation. In just three to ten days a limited number of individuals learn more in a single workshop than in weeks of
self-study. For optimum convenience, workshops are scheduled regularly at Training Centers worldwide or we
can take our workshops to you for on-site instruction. Covering a wide variety of topics, Intel's major course
categories include: architecture and assembly language, programming and operating systems, BITBUS™ and
LAN applications.

NETWORK MANAGEMENT SERVICES
Today's networking products are powerful and extremely flexible. The return they can provide on your investment via increased productivity and reduced costs can be very substantial.
Intel offers complete network support, from definition of your network's physical and functional design, to
implementation, installation and maintenance. Whether installing your first network or adding to an existing
one, Intel's Networking Specialists can optimize network performance for you.

Table of Contents
Alphanumeric Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xii

MULTIBUS® II PRODUCTS
CHAPTER 1
MULTIBUS® II Single Board Computers
iSBC 486/ 125DU and 386/133 Single Board Computers . . . . . . . . . . . . . . . . . . . . . . .
iSBC 386/116 and 386/120 MULTIBUS II Single Board Computers. . . . . . . . . . . . . .
iSBC 286/100A MULTIBUS II Single Board Computer..........................
iSBC 186/100 MULTIBUS II Single Board Computer...........................
MULTIBUS II PC Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1
1-5
1-13
1-22
1-31

CHAPTER 2
MULTIBUS® II Memory Expansion Boards
iSBC MM01, MM02, MM04, MM08 High Performance Memory Modules. . . . . . . . . .
iSBC MM01 FP, MM02FP, MM04FP, MM08FP High Performance Memory
Modules ...............................................................
iSBC MEM/320, 340 Cache-Based MULTIBUS II RAM Boards. . . . . . . . . . . . . . . . . .
iSBC MEM/601 MULTIBUS II Universal Site Memory Expansion Board. . . . . . . . . . .

CHAPTER 3
MULTIBUS® 111/0 PRODUCTS
MULTIBUS 11110 Product Fami!y............................................
CHAPTER 4
MULTIBUS® II System Packaging and Development Accessories
SYSTEM PACKAGING
iSBC PKG/606, iSBC PKG/609 MULTIBUS II Cardcage Assemblies. . . . . . . . . . . . .
iSBC PKG/902, iSBC PKG/903 MULTIBUS II iLBX II Backplanes. . . . . . . . . . . . . . . .
SYP 500 MULTIBUS II System Chassis ......................................
DEVELOPMENT ACCESSORIES
iSBC CSM/001 Central Services Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC Central Services Module/002..........................................
iSBC LNK/001 Board MULTIBUS II to MULTIBUS I Link Board..................
MULTIBUS II High Performance SBC General Purpose Test Fixture (GPTF) . . . . . . .

2-1
2-5
2-9
2-13

3-1

4-1
4-5
4-8
4-10
4-15
4-17
4-22

CHAPTERS
MULTIBUS® II Architecture
MULTIBUS II Bus Structure. . . . . . . . . . . . . . . . . .. . . . . .. . . . . .. .. . . . . . . . . . . . . . . . .
MULTIBUS® II APPLICATION NOTES
Designing a Central Services Module for MULTIBUS II .........................
MULTIBUS II Interconnect Design Guide ...................... : . . . . . . . . . . . . . .
MULTIBUS II Simplifies Partitioning of a Complex Design. .. . . . . . . . . . . . .. . .. . . ..
MIX Architecture Design Guide. . . . . . . . . . . . . . . . . . . . .. .. . .. . . . . . . . . . .. . . . . . . ..
MULTIBUS® II TECHNICAL PAPERS
Enhancing System Performance with the MULTIBUS II Architecture .............
Increasing System Reliability with MULTIBUS II Architecture. . . . . . . . . . . . . . . . . . ..

5-1
5-15
5-45
5-128
5-174
5-221
5-225

iSBXTM BUS PRODUCTS
CHAPTER 6
iSBXTM Expansion Modules
iSBX GRAPHICS MODULES
iSBX 279 Display Subsystem ...............................................
iSBX PERIPHERAL CONTROLLERS
iSBX 217C 1/4-lnch Tape Drive Interface MULTIMODULE Board. . . . . . . . . . . . . . . .
iSBX 218A Flexible Disk Controller. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . .

vii

6-1
6-4
6-6

Table of Contents (Continued)
iSBX DIGITAL AND ANALOG I/O BOARDS
iSBX 311 Analog Input MULTIMODULE Board. . . . . . . . . . . . . . . • . . . . . . . . . . . . .. . .
iSBX 328 Analog Output MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBX 350 Parallel I/O MULTIMODULE Board.. . . . .. . .. . . .. . .. . .. . ... . . . .. . ...
iSBX 488 GPIB MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBX SERIAL COMMUNICATION BOARDS
iSBX 351 Serial I/O MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBX 354 Dual Channel Serial 110 MULTIMODULE Board ..... . . . . . . . . . . . . . . . . .
iSBX ARCHITECTURE
iSBX I/O Expansion Bus .. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-10
6-13
6-16
6-19
6-22
6-26
6-29

CHAPTER 7

Real-Time Systems and Software
REAL-TIME SYSTEMS
System 120 ....... ,.'................. '.....................................
System 310 AP .......•......•............................................
System 310 AP 386 Upgrade. . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . .
System 320 ..............................................................
System 520 ..............................................................
OPERATING SYSTEM SOFTWARE
iRMK Real-Time Kernel. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . ..
iRMX Operating System Family ................. ; . . . . . . . . . . . . . . . . . . .. . . . . . . .
iRMX I Operating System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel System V/386 Product Family..........................................
Software Migration from iRMX 86 to iRMX 286 . . . . . .. ... ... . . . . . . . . . . . . . . . .. . .
SOFTWARE DEVELOPMENT TOOLS
AEDIT Source Code and Text Editor ...................... .'..................
iPAT Performance Analysis Tool............................................
iRMX Source Control System. . . . . . . . .. . .. . .. . . . . .. . .. . . . .. . . . . . . . . . .. . . . . . .
iRMX Toolbox............................................................
iRMX Virtual Terminal ......................................................
iRMX X.25 Communications Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . .. . ..
iSDM System Debug Monitor ................. ~ ..................... ; . . . . . ..
Soft-Scope II Source-Level Debugger. . ... . . . . . . . . . . . .. . . . . . . . . . . . . . .. .. . . ...

7-1
7-5
7-7
7-9
7-11
7-14
7-21
7-40
7-57
7-61
7-92
7-94
7-98
7-100
7-102
7-104
7-106
7-110

MULTIBUS® I PRODUCTS
CHAPTERS
MULTIBUS® I Single Board Computers
iSBC 386/12 and iSBC 386/12S Single Board Computers .............. :.......
iSBC 386/21/22/24/28 and 386/31/32/34/38 Single Board Computers. . . . . . . . .
iSBC 286/12, 286/14,286/16 Single Board Computers........................
iSBC 286/10A Single Board Computer.. .. . . . . . . . . . . . . .. . . .. . .. . . . . . . .. . .. . . .
iSBC 186/03A Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 86C/38 Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 86/35 Single Board Computer .........................................
iSBC 86/14 and iSBC 86/30 Single Board Computers..........................
iSBC 86/05A Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 88/25 Single Board Computer.........................................
iSBC 80/30 Single Board Computer .........................................
iSBC 80/24A Single Board Computer. . . . . . .. . .. . .. . .. . . . . . . . . . . . . .. .. . . . . . . .
iSBC 80/10B Single Board Computer........................................
iSBC 337 A MULTIMODULE Numeric Data Processor. . . . . . . . . . . . . . . . . . . . . . . . . .

viii

8-1
8-9
8-18
8-25
8-30
8-39
8-43
8-48
8-53
8-59
8-65
8-71
8-77
8-82

Table of Contents (Continued)
CHAPTER 9
MULTIBUS® I Memory Expansion Boards
DRAM EXPANSION BOARDS
iSBC MM01, MM02, MM04, MM08 High Performance Memory Modules. . . . . . . . . .
iSBC MM01 FP, MM02FP, MM04FP, MM08FP High Performance Memory
Modules ...............................................................
iSBC 012EX, 01 OEX, 020EX, and 040EX High Performance RAM Boards. . . . . . . . .
iSBC 012CX, 01 OCX, 020CX iLBX RAM Boards ...............................
iSBC314 512K Byte RAM MULTIMODULE Board.............................
iSBC 304 128K Byte RAM MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 302 8K Byte RAM MULTIMODULE Board ...............................
,SBC 301 4K Byte RAM MULTIMODULE Board ...............................
EPROM EXPANSION BOARDS
iSBC 429 Universal Site Memory Expansion Board ............................
iSBC 428 Universal Site Memory Expansion Board ............................
iSBC 341 28-Pin MULTIMODULE EPROM. . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . .

9-1
9-5
9-9
9-13
9-17
9-21
9-24
9-26
9-29
9-32
9-36

CHAPTER 10
MULTIBUS® I Peripheral Controllers
iSBC 221 Peripheral Controller..............................................
10-1
iSBC 214 Peripheral Controller Subsystem ...................................
10-4
iSBC 208 Flexible Diskette Controller. . . . . . . . . .. . . . . . . . . . . .. . .. . . . . . . .. . . . . . .
10-7
iSBC 215 Generic Winchester Controller ................................... :. 10-11
iSBC 220 SMD Disk Controller.............................................. 10-16
See Chapter 6 for iSBX Peripheral Controllers

CHAPTER 11
MULTIBUS® I Serial Communication Boards
iSBC 548/549 Terminal Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
iSBC 188/56 Advanced Communicating Computer .. . . . . . . . . . . . . . . . . . . . . . . . . . .
11-5
iSBC 544A Intelligent Communications Controller ............................. 11-14
iSBC 534 Four Channel Communication Expansion Board . . . . . . . . . . . . . . . . . . . . .. 11-20
iSBC 88/45 Advanced Data Communications Processor Board ................. 11-24
See Chapter 6 for iSBX Serial Communication Boards

CHAPTER 12
MULTIBUS® I Digital and Analog I/O Boards
iSBC 519A Programmable I/O Expansion Board ..............................
iSBC 517 Combination I/O Expansion Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 556 Optically Isolated I/O Board.......................................
iSBC 569 Intelligent Digital Controller. . . . . .. . . . . . . .. . .. . . . . . . . .. . . . . ... . . . . ..
iSBC 589 Intelligent DMA Controller .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
iSBC 88/40A Measurement and Control Computer ... . . . . . . . . . . . . . . . . . . . . . . . ..
iSBC 108A1116A Combination Memory and I/O Expansion Boards. . . . . . . . . . . . ..
See Chapter 6 for iSBX Digital and Analog I/O Boards

12-1
12-3
12-7
12-10
12-13
12-17
12-22

CHAPTER 13
MULTIBUS® I System Packaging and Power Supplies
SYP 341 Cardcage Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-1
SYP 342 Peripheral Module ................................................ 13-3
iSBC 604/614 Modular Card cage Assemblies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-5
iSBC 608/618 Cardcages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
iSBC 661 System Chassis. ... . . . . . . . . . . . .. . . . . . . . . . .. . . .. . . . . . . . . . . .. . . . . .. 13-12
iSBC 640 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-15
iCS 80 Industrial Chassis Kit 635, Kit 640 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-18
ix

Table of Contents (Continued)
CHAPTER 14
MULTIBUS® I Architecture
MULTIBUSSystemBus .................................................... 14-1
iLBX Execution Bus .................................... ,'.................. 14-13
See Chapter 6 for iSBX 1/0 Expansion Bus

SYSTEMS PRODUCTS

CHAPTER 15
ISA Boards and Systems
ISA BOARDS AND SYSTEMS
Intel386 MicroComputer Model 302.. . .. . .. . . . . .. . . .. . . . . .. . . .. . .. . . .. . . . . . ..
Intel386 MicroComputer Model 302-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . .
Intel386 MicroComputer Model 303. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel486 MicroComputer Model 401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel386 MicroComputer Model 300SX .................................•... "
Intel386 MicroComputer Model301Z ........................................
SOFnNAREPRODUCTS
Intel Software Products.:..................................................
ISA BOARDS AND SYSTEMS SUPPORT
Intel OEM Support ........................................................
Value-Added Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

15-1
15-3
15-5
15-8
15-11
15-14
15-16
15-20
15-22

LOCAL AREA NETWORK PRODUCTS

CHAPTER 16
Local Area Network Boards and Software
OpenNET Local Area Network Family. .. .. .. . . . . .. . .. . . . . . . . . . . . . . .. . . .. .. . ..
16-1
iSBX 586 Ethernet Data Link Engine.. . .. .. . . .. . . . . .. . . . . . . . . . .. . .. . . .. . .. . .. 16-16
iSBC552A and iSXM552A IEEE 802.3 Compatible Network Interface Adaptor. . . .. 16-18
iSBC 186/51 Communicating Computer ..............................-........ 16-21
See Chapter 3 for MULTIBUS II Networking Board Products

BITBUSTM PRODUCTS
CHAPTER 17
Distributed Control Modules
BITBUS STARTER KIT
BITBUS Starter Kit ....•...................................................
BITBUS OPERATING SYSTEM SOFTWARE
iDCX 51 Distributed Control Executive .......................................
BITBUS LANGUAGES AND TOOLS
DCS100 BITBUS Toolbox Host Software Utilities..............................
DCS110 Bitware DCS120 Programmers Support Package .................... "
8051 Software Development Packages......................................
ICE-51 00/044 In-Circuit Emulator...........................................
BITBUS Software Development Environment.................................
BITBUS BOARDS
iSBX 344A BITBUS Intelligent MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . . . . . ..
iPCX 344A BITBUS IBM PC Interface Board..................................
iRCB 44/1 OA BITBUS Digital I/O Remote Controller Board . . . . . . . . . . . . . . . . . . . ..
iRCB 44/20A Analog I/O Controller .........................................
iRCX 910/920 Digital/Analog Signal Conditioning Isolation and Termination
Panels ............................................................... "
iRCX 900 Isolation Module ......... .' ......................... ,.............
BITBUS COMPONENTS
8044 BITBUS Enhanced Microcontroller .........................•...........

17-1
17-5
17-13
17-20
17-25
17-28
17-32
17-36
17-44
17-50
17-59
17-67
17-71
17-73

Table of Contents (Continued)
8044AH/8344AH/8744AH High Performance 8-Bit Microcontroller with On-Chip
Serial Communication Controller . . . .. .. . . .. . .. . .. • . . . .. . . . . . . . . . .. .. . . .. .. 17-94

SERVICE AND SUPPORT
CHAPTER 18
Service and Support
iRUG Description .........................................................
Intel Systems Customer Service. . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18-1
18-2

Alphanumeric Index
8044 BITBUS Enhanced Microcontroller·............................................
8044AH/8344AH/8744AH High Performance 8-Bit Microcontrollerwith On-Chip Serial
Communication Controller ......................................................
8051 Software Development Packages.............................................
AEDIT Source Code and Text Editor. .. . .. . .. . . . .. . .. . .. . .. . ... .. ... . . . .. .. . . .. . . . . .
BITBUS Software Development Environment........................................
BITBUS Starter Kit. . . . . .. ... .. . . . . . ... .. . ... . .. . . . . .. . .. . .. ... . ... .. . . . . . . . .. . . . .
DCS100 BITBUS Toolbox Host Software Utilities .............. ;.: ....................
DCS110 Bitware DCS120 Programmers Support Package.............................
Designing a Central Services Module for MULTIBUS II . .. . . . .. . .. . .. . .. . . . . . .. . . .. . . ..
Enhancing System Performance with the MULTIBUS II Architecture ... . . . . . . . . .. . . . . . ..
ICE-51 00/044 In-Circuit Emulator..................................................
iCS 80 Industrial Chassis Kit 635, Kit 640 . . . .. . .. . .. . . .. . .. .. .. .. .. .. . .. . . . .. . . .. . ...
iDCX!51 Distributed Control Executive..............................................
iLBX Execution Bus .................................................. : .......... ,
Increasing System Reliability with MULTIBUS II Architecture ............ : . . . . . . . . . . . . ..
Intel OEM Support .............................................................. ,
Intel Software Products .......................................................... ,
Intel System V1386 Product Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel Systems Customer Service ...................................................
Intel386 MicroComputer Model 300SX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Intel386 MicroComputer Model301Z ...............................................
Intel386 MicroComputer Model 302 ................................................
Intel386 MicroComputer Model 302-20 .............................................
!nte1386 MicroComputer Model 303 ................................................
Intel486 MicroComputer Model 401 ................................................
iPAT Performance Analysis Tool.. .. . .. .. . . .. . .. .. .. . . .. .. . . .. .. .. . . . . .. .. . . .. .. . . .
iPCX 344A BITBUS IBM PC Interface Board.........................................
iRCB 44/10A BITBUS Digital 1/0 Remote Controller Board ......................... .'..
iRCB 44/20A Analog 110 Controller ........................ ; . . . . . . . . . . . . . . . . . . . . . ..
iRCX 900 Isolation Module........................................................
iRCX 910/920 Digital/Analog Signal Conditioning Isolation and Termination Panels......
iRMK Real-Time Kernel...........................................................
iRMX I Operating System ................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iRMX Operating System Family. .. .. .. .. .. . .. . .. . . . .. . . .. . . . . . . .. . .. .. . .. .. .. .. . . ..
iRMX Source Control System.. .. .. . .. .. .. . . . .. . . .. . . . . .. .. .. .. .. . . .. .. . . . . .. . .. . . .
iRMX Toolbox ...................................................................
iRMX Virtual Terminal ............................................................
iRMX X.25 Communications Software. .. . .. . . . .. . .. . . .. .. ... .. . . .. . .. . .. . . . ... ... ..
iRUG Description ........ , ................................... " . .. . .. . . . . .. ... .. .
iSBC 012CX, 010CX, 020CX iLBX RAM Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 012EX, 01 OEX, 020EX, and 040EX High Performance RAM Boards. . . . . . . . . . . . . . . .
iSBC 108A1116A Combination Memory and 1/0 Expansion Boards .................... ,
iSBC 186/03A Single Board Computer .............................................
iSBC 186/100 MULTIBUS II Single Board Computer..................................
iSBC 186/51 Communicating Computer ............................................
iSBC 188/56 Advanced Communicating Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 208 Flexible Diskette Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 214 Peripheral Controller Subsystem .... . .. . . . .. . . .. . . . . .. . . . . . .. . . . . . .. . .. .. .
iSBC 215 Generic Winchester Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
iSBC 220 SMD Disk Controller. . .. . .. .. . .. . . .. . . . .. . . .. .. .. . .. .. .. . .. . . . . . . .. . . . ...
iSBC 221 Peripheral Controller ....................................................
iSBC 286/100A MULTIBUS II Single Board Computer................................
iSBC 286/10A Single Board Computer.............................................
xii

17-73
17-94
17-25
7-92
17-32
17-1
17-13
17~20

5-15
5-221
17-28
13-18
17-5
14-13
5-225
15-20
15-16
7-57
18-2
15-11
15-14
15-1
15-3
15-5
15-8
7-94
17-44
17-50
17-59
17-71
17-67
7-14
7-40
7-21
7-98
7-100
7-102
7-104
18-1
9-13
9-9
12-22
8-30
1-22
16-21
11-5
10-7
10-4
10-11
10-16
10-1
1-13
8-25

Alphanumeric Index (Continued)
iSBC 286/12,286/14,286/16 Single Board Computers...............................
iSBC 301 4K Byte RAM MULTIMODULE Board......................................
iSBC 302 8K Byte RAM MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 304 128K Byte RAM MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 314 512K Byte RAM MULTIMODULE Board....................................
iSBC 337A MU LTIMODULE Numeric Data Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC341 28-Pin MULTI MODULE EPROM..........................................
iSBC 386/116 and 386/120 MULTIBUS II Single Board Computers.....................
iSBC 386/12 and iSBC 386/12S Single Board Computers. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 386/21/22/24/28 and 386/31/32/34/38 Single Board Computers ...............
iSBC 428 Universal Site Memory Expansion Board . . .. . . . . . . . . . . . . .. . .. . .. . .. .. . . .. ..
iSBC 429 Universal Site Memory Expansion Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 486/125DU and 386/133 Single Board Computers..............................
iSBC 517 Combination 110 Expansion Board ........................................
iSBC 519A Programmable 110 Expansion Board.....................................
iSBC 534 Four Channel Communication Expansion Board. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
iSBC 544A Intelligent Communications Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
iSBC 548/549 Terminal Controllers................................................
iSBC 556 Optically Isolated 110 Board..............................................
iSBC 569 Intelligent Digital Controller...............................................
iSBC 589 Intelligent DMA Controller................................................
iSBC 604/614 Modular Cardcage Assemblies ..... .. .. . . . .. . . .. . . . .. . . . . . . . .. . . . . . . .
iSBC 608/618 Cardcages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 640 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
iSBC 661 System Chassis. . .. . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . .. .... . .. ..
iSBC 80/10B Single Board Computer ..................... '..........................
iSBC 80/24A Single Board Computer. . . . . . . . . . . .. .. . . . . . . . . . . . . . . .. . . . . . . .... . . . . . .
iSBC 80/30 Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 86/05A Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 86/14 and iSBC 86/30 Single Board Computers. .. . . . . . . . . . . . . .. . . . . . . . .. .. . .. .
iSBC 86/35 Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 86C/38 Single Board Computer .................. ; . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 88/25 Single Board Computer. . . . . . . . . . . . .. . .. .. . . . . . . . . . .. . .. . .. . . . .. .. . .. ..
iSBC 88/40A Measurement and Control Computer...................................
iSBC 88/45 Advanced Data Communications Processor Board . . . . . . . . . . . . . . . . . . . . . . ..
iSBC Central Services Module/002. . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . .. . . . . . . .. .. . . . . . .
iSBC CSM/001 Central Services Module. . . . . .. . .. . . . . . .. . . . . . . . .. . . . . .. . . . ... . . .. ..
iSBC LNK/001 Board MULTIBUS II to MULTIBUS I Link Board ........................
iSBC MEM/320, 340 Cache-Based MULTIBUS II RAM Boards. . . . . . . . . . . . . . . . . . . . . . . . .
iSBC MEM/601 MULTIBUS II Universal Site Memory Expansion Board .................
iSBC MM01, MM02, MM04, MM08 High Performance Memory Modules.................
iSBC MM01, MM02, MM04, MM08 High Performance Memory Modules. . . . . . . . . . . . . . . . .
iSBC MM01 FP, MM02FP, MM04FP, MM08FP High Performance Memory Modules. . . . . . .
iSBC MM01 FP, MM02FP, MM04FP, MM08FP High Performance Memory Modules. . . . . . .
iSBC PKG/606, iSBC PKG/609 MULTIBUS II Cardcage Assemblies. . . . . . . . . . . . . . . . . . . .
iSBC PKG/902, iSBC PKG/903 MULTIBUS II iLBX II Backplanes ......................
iSBC552A and iSXM552A IEEE 802.3 Compatible Network Interface Adaptor............
iSBX 217C 1/4-lnch Tape Drive Interface MULTIMODULE Board ......................
iSBX 218A Flexible Disk Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBX 279 Display Subsystem . . . . .. . .. . .. . . .. . . .. . . . .. . . . . . .. . . . . . . . . . . . . .. . . .. . .. .
iSBX 311 Analog Input MULTIMODULE Board.......................................
iSBX 328 Analog Output MULTIMODULE Board.....................................
iSBX 344A BITBUS Intelligent MULTIMODULE Board ................................
iSBX 350 Parallel 110 MULTIMODULE Board. . .. .. . . . . . . .. . . .. . .. . . .. . . . . .. .. . . . . . ..
xiii

8-18
9-26
9-24
9-21
9-17
8-82
9-36
1-5
8-1
8-9
9-32
9-29
1-1
12-3
12-1
11-20
11-14
11-1
12-7
12-10
12-13
13-5
13-8
13-15
13-12
8-77
8-71
8-65
8-53
8-48
8-43
8-39
8-59
12-17
11-24
4-15
4-10
4-17
2-9
2-13
2-1
9-1
2-5
9-5
4-1
4-5
16-18
6-4
6-6
6-1
6-10
6-13
17-36
6-16

Alphanumeric Index (Continued)
iSBX 351 Serial 110 MULTIMODULE Board ......•..•.....•.....•.....•..........•..
iSBX 354 Dual Channel Serial 1/0 MULTIMODULE Board. . . . . . . . . • . . . . • . . . . • . • . . . . . . •
iSBX 488 GPIB MULTIMODULE Board. . . . . .•. . .• . .. . . .. .•. .. ... . .•. .•. .•. . .••. .•. .
iSBX 586 Ethernet Data Link Engine ................•.....•..•.... " ...•....' . . . . . . • ..
iSBX 1/0 Expansion Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . • . . . . . . • . • . . . . . . . • . • . . •
iSDM System Debug Monitor......................................................
MIX Architecture Design Guide ...................•.................•........•....•
MULTIBUS II Bus Structure ...................... ; ............... '. . . . . . . . . . . . . . . . .
MULTIBUS II High Performance SBC General Purpose Test Fixture (GPTF) .... :........
MULTIBUS 111/0 Product Family. . . . . . . . . . . . . • . . . . . . . . . . . . . . . . •• . . . . . • . . . . .• . . . . . . •
MULTIBUS II Interconnect Design Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . • . . . . . • •
MULTIBUS II PC Subsystem ............................•..................•.....•
MULTIBUS II Simplifies Partitioning of a Complex Design ....... '.......................
MULTIBUS System Bus. . .. .. .. .•. .. . .. .. . . .. . . . . . . .. . ... .. . ... . .. .•. ... . .•.. .•. .
OpenNET Local Area Network Family..............................................
Soft-Scope II Source-Level Debugger ..............................................
Software Migration from iRMX 86 to iRMX 286. . .. . . .. . .. . .. .•. . .. . .. .•. .•. .•. . . .. . . .
SYP 341 Cardcage Module.. .. .. .. . . . .. . . .. . .. . . . . .. . . . .. . .. . .. . .. . .. . .. . .. . . . .. . .
SYP 342 Peripheral Module . . . . . . . . . . . . . . . . . • . . . . . • . . . . . . . . . . • . . . . . . • . . . . . • . . . • . • •
SYP 500 MULTIBUS II System Chassis. . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . • . . . . . . . . • . . . .
System 120 . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . • . . . . • . . . . . . • . . . . . . . . • . • . . . . . • . . . . ..
System 310 AP . . . . . . . . . . . . . . . . . . . . • . . . • . . . . . . . . • . . . . . . . . . • . . . . • . . . . . . . . • . • . . . • . .
System 310 AP 386 Upgrade......................................................
System 320 . . . . . . . . . . . . . . . . . . . . . . . . • . . • . . • . . . . . . . . • . . . . . . . . . • . . . . . . . • . . • . • • . . . . .
System 520 . . . . . .. . . . . . .. .. .. .. . . .•. . . .. .. . . . .. .. . .. . .. .. . . ... .. .• . .. . .. . .• . . .. •
Value-Added Distribution .........................................................

xiv

6-22
6-26
6-19
16-16
6-29
7-106
5-174
5-1
4-22
3-1
5-45
1-31
5-128
14-1
16-1
7-110
7-61
13-1
13-3
4-8
7-1
7-5
7-7
7-9
7-11
15-22

MULTIBUS® II
Single Board Computers

iSBC®486/125DU AND 386/133* SINGLE BOARD COMPUTERS

ADDING i486'M AND 386'M CPU POWER TO MULTIBUS® /I
The iSBC® 4861125DU (Development Unit) and iSBC 386/133' Single Board Computers
provide immediate access to the i486™ and 386'· 32-bit microprocessors on MULTIBUS II,
the industry standard multiprocessing system bus. The iSBC 486/125DU board enables the
system architect to prototype and validate an i486 processor-based system today.
Boasting the 33MHz 386 processor and a feature set compatible with its predecessors,
the iSBC 386/133 board offers an immediate performance boost for current MULTI BUS II
designs. The iSBC 4861125DU and iSBC 386/133 boards are also fully compatible.
Design and ship systems in volume today using iSBC 386/133 boards, and easily
upgrade them to i486 CPU performance later.

FEATURES
iSBC® 4861125DU
• i486'" CPU operating at 25MHz with onchip FPU and cache
• 8MB on-board DRAM with parity
iSBC®486/125DU AND iSBC®386/133
• 82258 ADMA with 16-byte "blasf' mode
• Two 32-pin JEDEC EPROM Sites with
Built-in-self-test (BIST)
• iLBX'· II Interface
• Two RS-232 asynchronous serial ports
• One iSBX'" connector
• 3 programmable interval timers, 15
levels of interrupt

-Intef

The

iSBC®386/133
• 386'· CPU operating at 33MHz
• 387'· Numeric Coprocessor
• 64KB SRAM zero wait-state cache
• 1-16MB on-board DRAM with parity
• Full 32-bit MULTIBUS II (IEEE/ANSI
1296) Parallel System Bus interface
• Connector for on-board CSM option
• Full Operating Systems Support: iRMX®
II and UNIX" System V/386 operating
systems, and iRMKTM I real-time kernel

,sec 3861133 board IS also manufactured under product code pSBC386J133 by Intel Puerto RIco. Inc

------------------------~--------------------~S~ep~ffim~be-"~989

Order Number 281007·001

1-1

iSBC®386/133 FEATURES
386'" MICROPROCESSOR SPEED AND
PERFORMANCE

ON-SOARD CSM (CENTRAL SERVICES
MODULE) CAPABILITY

The iSBC 3861133 Single Board Computer features
the highest speed 386'" microprocessor available
today-33MHz. It also includes a 387'" floating-point
coprocessor running at 33M Hz. The 121-pin,
extended math coprocessor socket could also house
a WEITEK 3167 floating-point unit (FPU) instead of the
387 FPU.

An iSBC CSM/002 connector on the iSBC 3861133
provides an on-board CSM option. The iSBC
CSM/002 module performs all CSM functions
required by the IEEE/ANSI1296 Specification. It also
provides a battery-backed time-of-day clock, periodic
alarm function, and 28 bytes of non-volatile RAM. The
iSBC 3861133 with CSM module is installed in slot
zero of a MULTIBUS II chassis and requires only one
slot.

HIGH-SPEED ON-BOARD MEMORY
For optimum CPU performance, the iSBC 3861133
board includes a 64K Byte cache memory resulting
in zero wait-state read accesses on cache hits. The
iSBC 3861133 board provides 1-16MB of parity
protected, fast-page DRAM memory. The memory
interface is designed to support up to 64M bytes,
allowing for further memory expansion when 4 Mbit
DRAM modules become available.
This board also includes two 32-pin JEDEC sites for
up to 512KB of EPROM using 27020, 2 Mbit EPROM
devices. These sites, as shipped, contain BIST (BuiltIn-Self-Test) and IDX (Initialization and Diagnostics
eXecutive) power-up diagnostics residing in two preprogrammed 27010 EPROMs.

82258 ADMA COPROCESSOR WITH 16BYTE "BLAST" MODE
The 82258 Advanced DMA coprocessor provides 4
DMA channels. Two channels are allocated to data
transfers tolfrom the iSBX'" bus interface. The
remaining two channels handle data transfers
between the MPC and on-board memory. Special
logic on the board allows the 82258 to transfer data
to and from the MPC 4-bytes ('1Iy-by") or 16-bytes
("blast' mode) at a time; or at a sustained rate of
13.3M bytes/sec or 20.0M bytes/sec.

BALANCED SET OF ON-BOARD I/O: TWO
SERIAL PORTS, iSBXTM CONNECTOR
Through extensive use of surface mount technology,
the iSBC 3861133 board has increased the on-board
I/O features over previous MULTIBUS II CPU boards.
It provides two serial ports based on Intels 82530
Serial Communications Controller and one iSBX
connector, capable of supporting a single- or doublewide, 8- or 16-bit iSBX MULTIMODULp· board.

FULLY COMPATIBLE WITH iSBC®
3861116,120 AND ISBC®4861125DU .
The iSBC 3861133 board is fully compatible with the
INTEL386 family of MULTIBUS II boards, namely the
iSBC 3861116,3861120 and 4861125DU. Table 1 shows
that the iSBC 3861133 ieature set, with the exception
of PSB access to on-board memory, is a super set of
the iSBC 3861116, 120 feature set and matches that of
the iSBC 4861125DU. Your 16M Hz and 20MHz
designs may be upgraded to 33MHz for an
immediate system performance boost with a simple
board swap.

PLUG-AND-PLAY WitH SYSTEM 520
Conforming to the MULTIBUS II Systems Architecture
(MSA), this board integrates cleanly into the System
520. All you need is the ·System Integration Toolkit'
(SIT kit) that contains all the firmware necessary to
operate in the System 520 enviroment. Install the
firmware, plug the iSBC 386/133 into an empty slot,
and start the system. itS that simple.

COMPREHENSIVE DEVELOPMENT AND
OPERATING SYSTEM SUPPORT
Operating system support includes the iRMX@ II RealTime operating system and UNIX System Vl3a6.
operating system. The iRMK'" I real-time kernel is
available for 32-bit embedded applications. All three
include MULTIBUS II transport for full message
passing support. To ease MULTIBUS II modules
development, Intel offers both the iRMX arid UNIX
operating system versions of the System 520
Development System which can support oD-target
and/or cross-hosted software development in one
chassis.

iLBXTM 1/ INTERFACE FOR MEMORY
MAPPED I/O EXPANSION
The iLBXTM II interface on P2 provides expansion for
64M Bytes of off-board memory or memory mapped
1/0. It operates at 8M Hz and is completely
compatible with the iLBX II interface on the iSBC
2861100A and the iSBC MEM 3xx memory modules.

1-2

ISBC®486/125DU FEATURES
DEVELOPMENT VEHICLE FOR FAST TIME
TO MARKET WITH 1486'" CPU

HIGH·SPEED MEMORY INTERFACE
OPTIMIZES i486'" CPU PERFORMANCE

The iSBC 4861125DU Development Unit provides the
system architect the opportunity to start designing
today an i486™ processor-based system uSing an
industry standard, off-the-shelf board. These units are
currently available in limited sample quantities.

The iSBC 4861125DU board comes with 8 MBytes 01
byte-parity protected DRAM. On-board memory
access is optimized via a two way interleaved
memory design using fast page DRAMs. The iSBC
4861125DU board fits in a single MULTIBUS " slot.

i486'M MICROPROCESSOR: THE HIGHEST
PERFORMANCE COMPATIBILITY
PROCESSOR

COMPLETELY COMPATIBLE WITH THE
iSBC® 3861133

The heart of the iSBC 4861125DU board is the i486'·
microprocessor, the newest and fastest member of
the popular INTEL386TH 32-bit processor family. It is
binary compatible with 386 microprocessors and
offers two to three times the performance. The i486
microprocessor provides the highest level 01
performance through a state-ol-the-art design
containing a pipelined architecture, 8KB cache, and
a high-performance local bus interface. Frequent
instructions execute in one cycle. The performance is
further enhanced by an on-chip floating-point unit
(FPU) that is binary compatible with the 387 numerics
coprocessor.

As shown in Table 1, all the I/O and MULTIBUS "
architecture support features of the iSBC 386/133
are also provided on the iSBC 4861125DU for full
compatibility with the iSBC 3861133. Both boards are
supported by the iRMX, iRMK and UNIX operating
systems.

TABLE 1
INTEL386'" architecture based MULTIBUS II CPU Boards' Feature Set Comparison:

iSBC" 4861125DU

486'"125

On chip

On chIp

iSBC'" 386/133

386'"/33

387"'/33

64KB

ISBC'" 3861120

386'"120

387"'120

64KB

iSBC'" 3861116

386'"/16

387"'/16

64KB

WORLD WIDE SERVICE AND
SUPPORT
Should these or any Intel board ever need
service, Intel maintains a world wide network of
service and repair facilities to keep you and your
customers up and running. For unique
applications requiring customization of our
products, the Intel Custom Board and Systems
Group is available to modify, integrate and test
Intel boards and system components to your
requirements.

...
...
...
...

...
...
...

...

2
2
1(8751)
1(8751)

... ... ... ... ...
... ... ... ... ...
...
...
... ...
...
...
... ...

...
...
...
...

INTEL QUALITY-YOUR GUARANTEE
The iSBC 3861133 and iSBC 486/125DU boards
are designed and manufactured to meet Intel's
strict standards, assuring their reliability and high
quality.

1-3

SPECIFICATIONS
CPU CLOCK RATE
iSBC 386/133:
iSBC 486/125DU:

ELECTRICAL CHARACTERISTICS
386m CPU @ 33.3MHz
387m FPU @ 33.3MHz
i486'" CPU @ 25MHz

NOTE: Does not include power for iSBX module, or
added iSBC MMOx modules.

CACHE MEMORY
iSBC 386/133:
iSBC 486/125DU:

64K bytes
wait state on read hit
8K bytes on-chip
wait state on read hit

o
o

DMA CLOCK RATES/MAXIMUM
BANDWIDTH *
82258 ADMA
10MHzl20 MB per second
'assumes transfer between local DRAM and MPC.

ON-BOARD DRAM MEMORY
Model
iSBC 486/125
iSBC 386/133
iSBC 386/133
iSBC 386/133
iSBC 386/133

DC Power Requirements (Typical): + 5V, 13A
±12V, 200mA

Supplied
DU
F01
F02
F04
F08

8MB
1MB
2MB
4MB
8MB

• Single-bit parity error detection per byte
• iSBC 386/133 only: Memory expansion possible
with one additional iSBC MMOxFP module.
Maximum on-board memory capacity=16MB
(64MB wI 4Mbit DRAMs)
NOTE: Model suffixes F02 and F08 require two
MULTIBUS II card slots.
'iSBC 486/125DU with 8MB fits in one
MULTI BUS II slot.

For the second iSBC MMOx module, add:
iSBC MM01-FP or iSBC MM04-FP +5V, 0.71A
iSBC MM02-FP or iSBC MM08-FP + 5V, 0.96A

REFERENCE MANUAL
iSBC 386/133 Single Board Computer User's Guide
(order number 457629-001)
iSBC 486/125DU Single Board Computer User's
Guide (order number 459600-001)

ORDERING INFORMATION
Order Code

Description

SBC486125DU

25MHz 486 CPU-based
Development Unit wI 8MB D,RAM

SBC386133F01

33M Hz 386 CPU
DRAM
SBC386133F02 33MHz386 CPU
DRAM
SBC386133F04 33M Hz 386 CPU
DRAM
SBC386133F08 33MHz 386 CPU
DRAM
SBCMM01 FP
SBCMM02FP
SBCMM04FP

EPROM MEMORY
Two JEDEC sites provide following capacity:

Devices

Capacity

27010
27020

256K byte (supplied)
512K byte

INTERFACES
• MULTIBUS II PSB: 32-bit Parallel System Bus
(ANSI/IEEE 1296) interface
with full message passing
capability
• iSBX Bus:
Compliance Level:
D16/16 DMA
• iLBX II Bus:
Compliance Level: PRQA
• Serial 1/0:
RS232C DTE ASYNC

SBCMM08FP

wi 2MB

board

wi 4MB

board

wi 8MB

1MB, 85ns memory expansion
module
2MB, 85ns memory expansion
module
4MB, 85ns memory expansion
module
8MB, 85ns memory expansion
module
CSM Option Module

SIT133KIT

System 520 firmware for iSBC
386/133

For more information or the number of your nearest
Intel sales office, call 800-548-4725 (good in the U.S.
and Canada).
'

• Channel A & B: RS232C compatible DTE
Asynchronous interface
• 9-pin D-shell shielded connector
• Configurable baud rates:
300,600,1200,2400,4800,9600,19200, and 38400

PHYSICAL DIMENSIONS
233 mm (9.18 inches)
220 mm (8.65 inches)
19.2 mm (0.76 inches)

board

SBCCSM002

SERIAL I/O PORT

Height:
Depth:
Front Panel Width:

board w/1 MB

1-4

intel®iSBC® 386/116 AND 386/120* MULTIBUS® II
SINGLE BOARD COMPUTERS

•
•
•
•

•

DMA Controller Providing 4 High
• 82258
Performance DMA Channels
MULTIBUS®II Parallel System
• 32-Bit
Bus (IEEE 1296) Interface with Full

High Performance 32-bit 386TM
Processor Operating at 16 MHz or
20 MHz
80387 Numerics Co-Processor
Providing IEEE 754 Floating Point
Instruction Set, Operating at 16 MHz or
20 MHz
64K byte Static RAM Cache Providing
Zero Wait State Reads
1,2,4 or 8M Bytes of On-Board DualPorted Dynamic RAM Memory with
Parity Error Detection, Expandable to
16M Bytes
One RS 232C Serial 1/0 Port

Message Passing Capability
16-Bit iSBXTM Bus (IEEE P959)
• 8-,Interface
with DMA for I/O Expansion
Resident Firmware to Support Built-In• Self-Test
(BIST) Power-Up Diagnostics
MULTIBUS II Interconnect Space for
• Software
Configurability and
Diagnostics

The iSBC 386/116 and 120 MULTIBUS II Single Board Computers are based on Intel's 386 high performance
32-bit microprocessor. The 386 CPU maintains software compatibility with the entire 8086 microprocessor
family and delivers new performance standards for microcomputer-based systems. Four versions of the iSBC
386/116 and 120 boards are offered: the M01, which contains 1M byte of DRAM; the M02, which contains 2M
bytes of DRAM; the M04, which includes 4M bytes of DRAM; and the M08 which contains 8M bytes of DRAM.
An optional memory expansion module can be added to expand the iSBC 386/116 or 120 board's resident
memory to a maximum of 16M bytes.
The 64K byte static RAM cache ~nables the 386 CPU to execute at its full potential performance, while the
MULTIBUS II bus provides an interface for reliable, high performance mUltiprocessing.

280631-1

The iSBC~ 386/116 and iSBC® 386/120 are also manufactured under product code piSBC@ 386/116 and iSBC® 386/120
by Intel Puerto Rico, Inc.

1-5

November 1989
Order Number: 280631-002

inter

ISBC· 386/116 AND 386/120 MULTIBUS. II SINGLE BOARD COMPUTERS

executing at sustained rates of 4 and 5 million 32-bit
instructions per second, respectively. This performance is made possible through a state-of-the-art design combining advanced VLSI semiconductor technology, a pipelined architecture, address translation
caches and a high performance local bus interface.

FUNCTIONAL DESCRIPTION
Overview
The iSBC 386/116 and 120 boards utilize Intel's 386
32-bit microprocessor. The advanced capabilities of
the MULTIBUS II architecture coupled with the high
performance and compatibility features of the 386
CPU, provide the designer with a superior 32-bit solution for multiprocessing applications. By using the
MULTIBUS II architecture, multiprocessing systems
are enhanced through advanced bus features including: 21-board distributed arbitration, virtual interrupts, hardware-assisted message passing, bus parity for high reliability, and software configurability using interconnect address space. The MULTIBUS II
parallel system bus (iPSB) interface on the iSBC
386/116 and 120 boards support full message passing and dual-port architectures and is fully compatible with other SBCs based on the MULTIBUS II
(IEEE 1296) bus specification.

The 386 processor provides a rich, generalized register and instruction set for manipulating 32-bit data
and addresses. Features such as scaled indexing
and a 64-bit barrel shifter ensure the efficient addressing and fast instruction processing. Special
emphasis has been placed on providing optimized
instructions for high-level languages and operating
system functions. Advanced functions, such as
hardware-supported multitasking and virtual memory
support, provide the foundation necessary to build
the most sophisticated multitasking and multiuser
systems. Many operating system functions have
been placed in hardware to enhance execution
speed. The integrated memory management and
protection mechanism translates virtual addresses
to physical addresses and enforces the protection
rules necessary for maintaining task integrity in a
multiprocessing environment.

The iSBC 386/116 and 120 boards are offered in
four versions: M01, M02, M04 and M08 which contain 1, 2, 4 and 8M bytes of resident DRAM memory
respectively. This memory is physically located on
an expansion board, and can be accessed directly
from the iSBC 386/116 or 120 board's local bus or
by another CPU over the iPSB bus. This dual-port
memory can be expanded to a maximum of 16M
bytes though the addition of a second Intel iSBC
MM01, MM02, MM04 or MM08 (1, 2, 4 or 8M byte)
memory expansion module. Parity error detection is
included on all resident DRAM memory.

The 386 CPU provides access to the large base of
software developed for the 8086 family of microprocessors. Binary code compatibility allows execution of existing 16-bit applications without recompilation or reassembly, directly in a virtual 8086 environment. Programs and even entire operating systems
written for 8086 family processors can be run as
tasks under 32-bit operating systems written for the
386 CPU.

Architecture

80287 NUMERIC CO-PROCESSOR

The iSBC 386/116 and 120 logic consists of eight
resource modules and three interfaces connected .
together over an on-board local bus. The resources
include the 386 CPU, the 80387 numeric co-processor, the 82258 DMA controller, the dual-port DRAM
memory, the SRAM cache memory, the EPROM
memory with BIST software, the programmable timers and the interrupt 'controllers. Interfaces included
are the iPSB parallel system bus, the iSBX 110 bus
and the RS 232C serial 110 interface. A block diagram of the iSBC 386/116, 120 board is shown in
Figure 1. The following text describes each of the
resources and interfaces.

The 80387 is a high-performance floating-point coprocessor that takes numerics functions which
would normally be performed in software by the 386
microprocessor and Instead executes them in hardware. The instruction set executed by the 80387 is
compatible with the IEEE 754 floating point standard, with high-precision 80-bit architectures and full
support for single, double and extended precision
operations. The 80387 executes floating point operations at a rate of 1.5M Whetstones per second at
16 MHz, and 1.86M Whetstones per second at
20 MHz.

82258 ADVANCED DMA CO-PROCESSOR
386TM PROCESSOR

The 82258 is a high performance 4 channel DMA
co-processor. Unlike other DMA devices, the 82258
has processing capabilities. Its command chaining
feature and data manipulation capabilities (compare,
verify, translate), allow the 82258 to execute simple

Intel's 386 CPU is the central processor for the iSBC
386/116 and 120 boards. This is the first 32-bit
member of Intel's 8086 family of microprocessors.
At 16 MHz and 20 MHz, the 386 is capable of

1-6

'r---------MEMoRYsuaSYSTEM-------------,

r---------"
PROCESSOR
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,

CD
C
CD

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0'
n

:I!"

SUBSYSTEM

MATH CO·
f--PROCESSOR
80287

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3

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QI

.......

....
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82258
ADMA

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ADDRESS

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I

.----

.DD

-----------------I

TIMERS

iii
c:

MESSAGE
PASSING
COPROCESSOR

••

en@l

=
~
Z

L-IINTERRUPT
CONTROL

-------------i---------l

IPSB
DUAL·PORT
BUFFERS

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BUFFERS
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L _ _ _ _ _ _ _ _ --.J

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ADDRESS
BUFFERS

~~:

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0

o@l

DRAM
WITH
PARITY

EPROM

DMAI
DDRES

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...........
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CACHE
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en1:11

!L___ : ____________________~___ -~J

CIl

TAG
MEMORY

I~III

:::I"

.!..i

II
II
II,I
II

DATA

iii'

SERIAL
I/O
8751
MICRO·
CONTROL

r
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1:11

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:zJ

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I
II

o
o
==
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II

L_____I...!p~~E~~E _____ ---------L==-=--=-_--=--=JJ

c:
-f

m
:zJ

en
PARALLEL SYSTEM BUS

280631-2

inter

iSBC® 3861116 AND 386/120 MULTIBUS® II .SINGLE BOARD COMPUTERS

input/output programs without processor intervention. This allows the 386 CPU more time for general
purpose processing, thus improving total system
performance. The 82258 shares ownership of the
on-board local bus via the 386 processor's HOLD,
HOLD ACKNOWLEDGE co-processor protocol. The
maximum percentage of on-board local bus utilization by the 82258 is user programmable.

The DRAM is accessible from both the on-board local bus and the iPSB bus. The amount of memory
accessible from the iPSB bus and the iPSB address
. aliasing values are dynamically configurable via interconnect space registers.
CACHE MEMORY
The cache memory on the iSBC 386/116 and 120
boards allow zero wait-state accesses to memory
when the data requested is resident in the cache
memory. The static RAM cache has 16,384 32-bit
data entries with 8-bit "tag" fields. Each 32-bit
DRAM memory location maps to one (and only one)
cache data entry. The "tag" fields are used to determine which 32-bits of DRAM memory currently resides in each cache data entry. The combination of
a direct mapped cache data array and a tag field
ensures data integrity and accurate, high performance identification of cache "hits".

The four 82258 channels are allocated to iSBC 386/
116 or 120 on-board resources as shown in Table 1.
Special logic on the boards allows the 82258 to
transfer data to and from the message passing coprocessor (MPC) 32-bits at a time using single cycle
mode. Using this mode, the 82258 (which operates
at 8 MHz on 386/116 and 10 MHz on 386/120) can
load or unload an MPC solicited message (from or to
resident DRAM) at a sustained rate of 10.7M bytes
and 13.3 Mbytes per second, respectively.
Table 1. DMA Channel Allocation
Channel

Function

0
1
2
3

iSBX DMA support
iSBX DMA support
MPC Solicited Message Receive
MPC Solicited Message Transmit

Data integrity is maintained for cache "misses"
(DRAM memory RE~Ds not in the cache) and
DRAM memory WRITEs through a simple, yet effective replacement algorithm. 386 CPU generated
cache READ "misses" cause the data field of the
cache entry corresponding to the addressed memory to be filled from the DRAM array and the tag field
to be updated. All iPSB or ADMA READs are treated
as cache "misses", except that the cache is not updated. All WRITE "hits", local and iPSB generated,
cause the cache data field to be updated. WRITE
"misses" do not update the cache. The cache memory size and replacement algorithm are deSigned to
optimize both the probability of cache "hits" and local bus utilization.

DUAL-PORTED DYNAMIC RAM
The iSBC 386/116 and 120 boards include 1, 2, 4 or
8M bytes of DRAM depending upon the version.
This memory can be extended to a maximum of 16M
bytes through the addition of an Intel iSBC MM01,
MM02, MM04 or MM08: 1, 2, 4 or 8M byte memory
expansion module. The DRAM refresh control, dualport control and parity generation/checking logic is
physically located on the baseboard, while the actual DRAM components are located on low-profile surface mount expansion boards. Each iSBC 386/116
or 120 board is shipped with one expansion memory
module installed and may be expanded to contain
two total memory expansion modules. The memory
expansion module mechanics are shown in Figure

EPROM MEMORY
Two 32-pin JEDEC EPROM sites capable of supporting up to 512K bytes of EPROM (using 27020
EPROMs) are supplied on the iSBC 386/116 and
120 boards. These sites, as shipped, contain built-inself-test power-up diagnostics residing in two preprogrammed 27512 EPROMs. These EPROMs may
be replaced by the user. Jumper configurations allow the use of 2764,27128, 27256, 27512, 27010,
and 27020 EPROMs.

2.·
'NOTE:
Only one single-sided memory module (MM01 or.
MM04) installed onto the iSBC 386/116 or 120
board will fit within one MULTIBUS II slot. A double-sided module (MM02 or MM08) or any stack of
two modules will require two MULTIBUS II slots.

8254 PROGRAMMABLE TIMERS
The iSBC 386/116 and 120 boards contain an Intel
8254 component which provides three independent
programmable 16-bit interval timers. These may be
used for real-time interrupts or time keeping operations. Outputs from these timers are routed to one of
the two 8259A interrupt contr~lIers to provide software programmable real-time interrupts.

Parity error detection is provided on a byte-by-byte
basis. The parity logic normally generates and
checks for odd parity with detected errors signaled
via an on-board LED and a CPU interrupt. Even parity can be forced to generate a parity error for diagnostic purposes.
1-8

inter

iSBC® 386/116 AND 386/120 MULTIBUS® II SINGLE BOARD COMPUTERS

iSBC 386/1 XX BOARD

''"':':~~l

J
4.25"

CONNECTOR
OUTLINE

.---------.
I

10--._----------'--.

SIDE VIEW
MEMORY
MODULE

iSBC386/1XX M01 OR M04

iSBC386/1XX M02 OR M08

MEMORY
MODULES

iSBC(J!)386/1XX M01 OR M04
WITH EXPANDED MEMORY

iSBC (J!) 386/1 XX M02 OR M08
WITH EXPANDED MEMORY
280631-3

NOTE:
1. The iSBC 386/1XX MOl or M04 fits within one MULTISUS" slot. The iSSC 386/1XX M02 or M08, or any iSSC 3861
lXX with a stack of two memory modules will require two MULTISUS" slots.

Figure 2. iSBC® 386/116 and 120 Boards Memory Module Mechanics

1-9

inter

iSBC® 386/116 AND 386/120 MULTIBUS® II SINGLE BOARD COMPUTERS

INTERRUPT CONTROL

IPSB BUS INTERFACE

Two Intel 8259A programmable interrupt controllers
on the iSBC 386/116 and 120 boards are used in a
master-slave configuration for prioritizing up to 15
separate on-board interrupt sources. The devices
and functions are listed in Table 2.

The MULTIBUS II parallel system bus interface is
implemented by Intel's MPC (message passing coprocessor) and a pre-programmed 8751 microcontroller. This interface supports full arbitration, transfer and error checking features as defined in the
iPSB specifications. In addition, the interface supports advanced features of the iPSB bus including
hardware message passing and autoconfiguration
through geographic addressing.

The MULTIBUS II iPSB bus utilizes virtual interrupts
(called unsolicited messages) for board-to-board
Signaling. The bus interface component (MPC)
qlleues-up incoming virtual interrupts from the iPSB
bus and generates a single message interrupt
(MINT) Signal. This signal is connected into one of
the 8259A interrupt controllers for prioritization and
interruption of the host 386 CPU. Error conditions
occurring on the iPSB bus will cause the MPC to
generate an error interrupt (EINT) signal. This signal
is connected to another 8259A interrupt input.
Other interrupt sources come from the 82258 DMA
controller, the 8254 timers, the iSBX interface, the
8751 serial port, and the DRAM parity checker.
SERIAL I/O INTERFACE
One RS 232C compatible serial I/O port is provided
via the Intel 8751 microcontroller. This port is configured as a data terminal equipment (DTE) asynchronous serial port. Mechanically, the serial port exits
through the iSBC 386/116 or 120 board's front pan-el via a 9-pin D-shell connector.

The MPC component contains nine 32-byte buffers
which are used to decouple iPSB bus traffic from
iSBC 386/116 or 120 local bus traffic through the
concept known as message passing. These nine
buffers are utilized as follows: four buffers queue-up
incoming unsolicited messages, one buffer stores an
out-going unsolicited message, two buffers are used
to double-buffer an out-going solicited message, and
two buffers are used to double-buffer an incoming
solicited message. These buffers are capable of
transferring data packets over the iPSB bus at its
maximum transfer rate. Unsolicited messages include address and type fields and 28 bytes of userdefined data, and are transferred over the iPSB bus
in 900 ns. Solicited messages are automatically divided into small packets, with each packet containing address and type fields and 32 bytes of user-defined data. Each solicited message packet is transferred over the iPSB bus in 1000 ns.

Table 2. 8259A Interrupt Sources
Device

Function

Number of
Interrupts

MPC-MINT

Signals arrival of virtual interrupt over
iPSB bus, solicited input complete,
transmit FIFO not full or transmit error

MPC-EINT
82258DMA

Signals error condition on the iPSB bus
Transfer complete

1
1

8254 Timers

Timers 0, 1, 2 outputs, function
determined by timer mode

8751 Serial Port
iSBX Interface

Serial diagnostic port requests
Function determined by iSBX bus
multi module board

DRAM Parity Checker

Signals parity error

1-10

inter

ISBCCBl 386/116 AND 386/120 MULTIBUSCBl II SINGLE BOARD COMPUTERS

The 8751 component implements the IPSB geographic addressing feature called Interconnect
space. Read-only registers are used to hold information such as board type and revision level. Software
configurable registers are used for auto-configurabllity, local or remote diagnostics and software controlled reset. In addition, the 386 CPU executes power-up built-in self tests of the various resources on
the iSBC 386/116 and 120 boards. The results of
these tests are reported via registers in interconnect
space. After successfully completing its BIST routines, the 386 CPU must clear the reset-not-complete register. If, after 30 seconds, the reset-notcomplete has not been cleared, the 8751 resets the
local bus and holds it in a reset state. In this way,
only a few components on the iSBC 386/116 or 120
board must be functional to allow the iPSB bus to
operate.

EXPANSION MODULES
iSBC
iSBC
iSBC
iSBC

MM01-1M
MM02-2M
MM04--4M
MM08-8M

byte
byte
byte
byte

MAXIMUM CAPACITY-16M BYTES

EPROM Memory
Default -

128K byte using two pre-programmed
27512 EPROMs
Capacity - Two 24-, 28- or 32-pin JEDEC-compatible devices

ISBXTM BUS INTERFACE

EPROM

One iSBX connector, capable of supporting one single- or double-wide, 8- or 16-bit iSBX MULTIMODULE board, is provided on the iSBC 386/116 and
120 boards for the addition of an optional I/O module. Two DMA channels from the 82258 can be used
with iSBX modules which require DMA support.

2764
27128
27256
27512
27010
27020

Memory Capacity
16 KB
32 KB
64KB
128 KB
256 KB
512 KB

SPECIFICATIONS
Timers
Word Size

Capability

- Threeindependentlyprogrammed
16-bit interval timers

Instruction
- 8-, 16-,24-,32-, 40-bit
Data
- 8-, 16-, 32-bit
Floating Point Data- 80-bit

Input Frequency- 1.25 MHz ± 0.1 %
Output Period - 1.6 /Ls to 52.4 ms

Clock Rates

Interrupt Capability

386™ CPU
80387 Numeric Co-processor
82258 DMA

386/116 386/120
16 MHz 20 MHz
16 MHz 20 MHz
8 MHz 10 MHz

Incoming Interrupts- 255 individual and 1 broadcast from iPSB bus 12 local
sources (see Table 2)
Outgoing Interrupts- 255 individual and 1 broadcast to IPSB bus

Dual-Port DRAM Memory

Serial Port Interface

DEFAULT CAPACITY

RS 232C Electrical
Asynchronous, DTE only
9-pin D-shell connector
Baud rates: 9600, 4800, 2400, 1200, 300, 110 bits/
sec

iSBC 386/116 M01-1M byte
iSBC 386/116 M02-2M byte
iSBC 386/116 M04--4M byte
iSBC 386/116 M08-8M byte
iSBC 386/120
iSBC 386/120
iSBC 386/120
iSBC 386/120

M01-1M
M02-2M
M04--4M
M08-8M

byte
byte
byte
byte

isex Interface
One 8- or 16-bit, single- or double-wide iSBX module
Compliance Code- D16/16 DMA
Capability

1-11

inter

iSBC® 386/116 AND 386/120 MULTIBUS® II SINGLE BOARD COMPUTERS

iPse Interface

ORDERING INFORMATION

Capability- Requesting and replying agent supporting 8-, 16-, 24- and 32-bit transfer~, parity bit generation and checking, unsolicited and solicited message passing,
and autoconfiguration through intercon·
nect space.

Part Number

Physical Dimensions
Length:
220 mm (8.6 in.)
Width:
233 mm (9.2 in.)
Front Panel Height: 19.2 mm (0.76 in.)

Power Requirements
SV: 11.14 Amps
12V: 0.046 Amps
-12V: 0.041 Amps
Voltage tolerance ± S%

Temperature Range and Airflow
Requirements
Storage Temperature:
- 40·C to + 70·C
Operating Temperature: O·C to + SS·C
Airflow:
200 LFM minimum

Description

SBC386116M01 16 MHz 386 CPU-based MULTIBUS II CPU board with 1M byte
memory
SBC386116M02 16 MHz 386 CPU-based MULTIBUS II CPU board with 2M byte
memory
SBC386116M04 16 MHz 386 CPU-based MULTIBUS II CPU board with 4M byte
memory
SBC386116M08 16 MHz 386 CPU-based MULTIBUS II CPU board with 8M byte
memory
SBC386120M01 20 MHz 386 CPU-based MULTIBUS II CPU board with 1M byte
memory
SBC386120M02 20 MHz 386 CPU-based MULTIBUS II CPU board with 2M byte
memory
SBC386120M04 20 MHz 386 CPU-based MULTIBUS II CPU board with 4M bYte
!f1emory
SBC386120M08 20 MHz 386 CPU-based MULTIBUS II CPU board with 8M byte
memory
SBCMM01
1M byte memory expansion module
2M byte memory expansion mod·
SBCMM02
ule
SBCMM04
4M byte memory expansion module
8M byte memory expansion modSBCMM08
ule
iSBC 386/116 and 386/120 Single
4S1833
Board Computer Users Guide

1·12

iSBC® 286/100A* MULTIBUS®II
SINGLE BOARD COMPUTER

•
•
•

•
•

8 MHz 80286 Microprocessor with
Optional 80287 Numeric Data
Co-Processor

MULTIBUS® II Interconnect Space for
• Software
Configurability and Self-Test

MULTIBUS® II PSB (Parallel System
Bus) Interface with Full Message
Passing Capabilities and up to 4
Gigabytes of Memory Addressability on
the Bus

Firmware Supports Self-Test
• Resident
Power-Up Diagnostics and On-

Diagnostics

Command Extended Self-Test
Diagnostics

•

High-Speed Memory Expansion with
MULTIBUS II iLBX II (Local Bus
Extension) Interface Addresses up to
16 MBytes of Local andlor Dual Port
Memory

Two Programmable Serial Interfaces,
one RS232C (DCE or DTE), the other
RS232C or RE422A/RS449 Compatible

28-pin JEDEC Sites for up to 128
• Two
KBytes of Local Memory Using SRAM,
NVRAM, EEPROM, and EPROM

•

Two iSBX Bus Interface Connectors for
1/0 Expansion Bus
Four DMA Channels Supplied by the
82258 Advanced DMA Controller with 8
MBytes/sec Transfer Rate

24 Programmable 1/0 Lines
Configurable as SCSI Interface,
Centronics Interface, or General
Purpose 1/0

The iSBC 286/1 OOA Single Board Computer is part of Intel's family of MULTIBUS II CPU boards that utilizes
the advanced features of the MULTIBUS II System Architecture. It is ideally suited for a wide range of OEM
applications. The combination of the 80286 CPU, the Message Passing Coprocessor (MPC), the MULTIBUS II
Parallel System Bus (PSB bus), and the Local Bus Extension (iLBX II bus) makes the iSBC 286/100A board
suited for high performance, multiprocessing system applications in a multi master environment. The board is a
complete microcomputer system on a 220mm x 233mm (8.7 x 9.2 inch) Eurocard form factor with pin and
socket DIN connectors.

280076-1
'The iSBC'" 286/100A is also manufactured under product code pISBC'" 286/100A by Intel Puerto RICO, Inc.

1-13

October 1989
Order Number: 280076-005

ISBC~

288/100A MULTIBUS~ II

Overview

Architecture

The iSBC 286/100A Single Board Computer com·
blnes the 80286 microprocessor with the Message
Passing Component (MPC) on a single board within
the MULTIBUS II system architecture. This offers a
message passing based high performance multipro·
cessing solution for system Integrators and design·
ers. Figure 1 shows a typical MULTIBUS II multipro·
cessing system configuration. Overall system per·
formance Is enhanced by the Local Bus Extension
(iLBX II) which allows 0 wait state high speed memo·
ry execution.

All features of the MULTIBUS II architecture are fully
supported by the iSBC 286/100A board Including
the Parallel System Bus (PSB), Interconnect space,
Built·ln·Self·Tests (BIST) diagnostics, and full meso
sage passing. These features are described in the
following sections. In addition to taking advantage of
the MULTIBUS II system architecture, the iSBC
286/100A board has complete single board comput·
er capability including two ISBX bus expansion con·
nectors, 80287 numeric data coprocessor option,
advanced DMA control, JEDEC memory sites,
SCSI configurable parallel interface, serial 1/0, and
programmable timers. Figure 2 shows the iSBC
286/100A board block diagram.

1ImI.·

280076-2

Figure 1. Typical MULTIBUS~II Multiprocessing System Configuration

- . - . IPAIW.UI. .n.....

280076-3

Figure 2.ISBC~ 2861100A Board Block Diagram

1·14

inter

ISBC® 286/100A MULTIBUS® II

tween agents on the PSB bus. The arrival of a solicited message is negotiated between the sending
and receiving agents. Data is sent in "packets" with
each packet containing four bytes of control information and up to 28 bytes of data. There is no specific limit to the number of packets that may be sent
in a single message, but the total message may not
transfer more than 16 Mbytes.

Central Processing Unit
The central processing unit for the iSBC 286/100A
board is the 80286 microprocessor operatinQ at
8.0 MHz clock rate. The 80286 runs 8086 and 80186
code at substantially higher speeds (due to a parallel
chip architecture) whil~ maintaining software compatibility with Intel's 8086 and 80186 microprocessors. Numeric processing power may be enhanced
with the 80287 numeric data coprocessor. The
80286 CPU operates in two modes: real address
mode and protected virtual address mode. In real
address mode, programs use real addressing with
up to one megabyte of address space. In protected
virtual address mode, the 80286 CPU automatically
maps 1 gigabyte of virtual address per task into a 16
megabyte real address space. This mode also provides the hardware memory proteclion for the operating system. The operating mode is selected via
CPU instructions.

The iSBC 286/100A also includes a feature called
the PSB window register that allows the user to selectively access under software control any 256K
byte block of memory within the 4 Gigabytes of
memory space on the PSB bus interface.

INTERCONNECT SPACE SUPPORT
Interconnect space is one of four MULTIBUS II address spaces, the other three being memory space,
110 space, and message space. Interconnect space
allows software to initialize, identify, configure, and
diagnose the boards in a MULTIBUS II system. The
Interconnect template consists of 8-bit registers, organized into functional groups called records. There
are three types of records, the header record, function records, and the End of Template record.

PSB Bus Interface
The iSBC 286/100A board has a Message Passing
Coprocessor (MPC) component on the base board
that contains most of the logic required to operate
the Parallel System Bus (PSB bus) interface. Some
of the key functions provided by the MPC include
bus arbitration, transfer control, parity generation
and checking, and error detection and reporting.

The header record provides board and vendor ID
information, general status and control information,
and diagnostic control. The function records allow
the user to configure and/or read the
iSBC 286/100A board's hardware configuration via
software. The End of Template record identifies the
end of the interconnect template.

Data transfers between processors via the PSB bus
is defined in the MULTIBUS II architecture through a
transfer protocol, a reserved address space, and an
information/data block. This interprocessor communication convention is known as message passing.
Operations occurring within the reserved address
space are called message space operations.

BUILT IN SELF'TEST (BISn
DIAGNOSTICS
MULTIBUS II's Built in Self Test (BIST) diagnostics
improve the reliability and error reporting and recovery capability of MULTIBUS II boards. These confidence tests and diagnostics not only improve reliability but also reduce manufacturing and maintenance costs for the OEM user. The yellow BIST LED
(LED 1) on the front panel provides a visual indication of the power-up diagnostics status.

Message passing allows PSB bus agents to transfer
variable amounts of data at rates approaching the
maximum bandwidth of the bus. Message passing
permits a sustained transfer rate of 2.2 Mbytes
per second, and a single message may transfer up
to 16 Mbytes from one agent to another. The MPC
fully supports message space operations, executes
PSB bus arbitration and executes the message
passing protocol independent of the host CPU, leaving the host free to process other tasks.

Error Reporting and Recovery
The MPC supports both solicited and unsolicited
message passing capability across the PSB. An unsolicited message can be thought of as an intelligent
interrupt from the perspective of the receiving agent
because the arrival of an unsolicited message is unpredictable. Attached to an unsolicited message is
one of 255 possible source addresses along with 28
bytes of data attached to the message data field. A
solicited message moves large blocks of data be-

The MULTIBUS II Parallel System Bus and the
iLBX II bus provides bus transmission and bus parity
error detection signals. Error information is logged in
the MPC and a bus error interrupt is generated. Information on the error source for reporting or recovery purposes is available to software through the
iSBC 286/1 OOA board interconnect space registers.

1-15

iSBC® 286/100A MULTIBUS® II

cal on-board bus including 16 data lines and DMA
for maximum data transfer rates. MULTIMODULE
boards designed with 8-bit data paths and using the
8-bit iSBX bus connectors are also supported. A
broad range of iSBX bus MULTIMODULE options
are available' from Intel. Custom iSBX bus MULTIMODULE boards designed for MULTIBUS or proprietary bus systems are also supported provided the
IEEE P959 iSBX bus specification is followed.

INTERRUPT CONTROL
In a MULTIBUS II system, external interrupts (interrupts originating off the CPU board) are messages
over the bus rather than signals on individual lines.
Message based interrupts are handled by the MPC.
Two on-board 8259A Programmable Interrupt Controllers (PICs) are used for processing on-board interrupts. One is used as the master and the other as
the slave. Table 1 includes a list of devices and functions supported by interrupts.
-

NUMERIC DATA CO-PROCESSOR
The 80287 Numeric Data Co-Processor can be installed on the iSBC 286/100A board by the user.
The 80287 Numeric Data Co-Processor is connected to dedicated processor signal lines which are
pulled to their inactive state when the 80287 Numeric Data Co-Processor is not installed. This enables
the user to detect via software that the 80287 socket
is occupied. The 80287 Numeric Data Co-Processor
runs asynchronously to the 80286 clock. The 80287
Numeric Data Co-Processor operates at 8 MHz and
is driven by the 8284A clock generator.

iSBX® BUS MULTIMODULETM
ON-BOARD EXPANSION
Two iSBX bus MULTIMODULE connectors are provided, one 16- or 8-bit and the other 8-bit. Through
these connectors additional on-board I/O functions
may be added. The iSBX bus MULTIMODULE
boards optimally support functions provided by VLSI
peripheral components such as additional parallel
and serial I/O, analog 1/0, and graphics control. The
iSBX bus connectors on the iSBC 286/100A board
provides all signals necessary to interface to the 10-

Table 1. Interrupt Devices and Functions
Device
MULTIBUS® II Interface

Function
Message-based Interrupt Request from the
PSB Bus via 84120 Message Interrupt
Controller

Number of Interrupts
1· Interrupt from up to
256 sources

8751 Interconnect Controller

BIST Control Functions

82530 Serial Controller

Transmit Buffer Empty, Receive Buffer
Full and Channel Errors

8254 Timers

Timers 0, 1, 2 Outputs; Function Determined
by Timer Mode

8255A Parallel I/O

Parallel Port Control

iLBX II Bus Interface

Indicates iLBXTM II Bus Error Condition

PSB Bus Interface

Indicates Transmission Error on PSB Bus

iSBX Bus Connector

Function Determined by iSBX Bus
MULTIMODULE Board

Edge Sense Out

Converts Edge Triggered Interrupt to a Level

Bus Error

Indicates Last PSB Bus Operation
Encountered an Error

Power-Fail

External/Power-Faillnterrupts

1-16

1
1 Interrupt from
10 Sources

inter

ISBC® 286/100A MULTIBUS® II

ports. As shipped, these ports are configured for
general purpose I/O. Programmed PAL (Programmable Array Logic) devices and the octal transceiver
74LS640-1 are provided to make it easy to reconfigure the parallel interface to be compatible with the
SCSI (Small Computer System Interconnect) peripheral interface. Alternatively, the parallel interface
may be reconfigured as a Centronics compatible line
printer by adding one PAL and reconfiguring jumpers. Both interfaces may use the 82258 DMA controllers for data transfers.

DMA CONTROL
Four DMA (Direct Memory Access) channels are
supplied on the iSBC 286/100A board by the 82258.
The 82258 is an advanced DMA controller designed
especially for the 16-bit 80286 microprocessor. It
has four DMA channels which can transfer data at
rates up to 8 Megabytes per second (8 MHz clock) in
an 80286 system. The large bandwidth allows the
user to handle very fast data transfer or a large number of concurrent peripherals.

The SCSI interface allows multiple mass storage peripherals such as Winchester disk drives, floppy disk
drives, and tape drives to be connected directly to
the iSBC 286/100A board. A sample SCSI application is shown in Figure 3. The SCSI interface is compatible with SCSI controllers such as the Adaptek
4500, DTC 1410,Iomga Alpha 10, Shugart 1601 and
1610, Vermont Research 8403, and Xebec 1410.

MEMORY CAPABILITIES
The local memory of the iSBC 286/1 OOA board consists of two groups of byte-wide sites. The first group
of two sites are reserved for EPROM or ROM and
are used for the BIST power-up diagnostic firmware.
The second group of two sites support JEDEC standard 28-pin devices.

The Centronics interface requires very little software
overhead since a user-supplied PAL device is used
to provide necessary handshake timing. Interrupts
are generated for printer fault conditions and a DMA
request is issued for every character.

PARALLEL PERIPHERAL INTERFACE
The iSBC 286/100A board includes a parallel peripheral interface that consists of three 8-bit parallel

SCSI BUS

280076-4

Figure 3. Sample SCSI Applications

1-17

ISBC@ 286/100A MULTIBUS@ II

SERIAL 1/0

SOFTWARE SUPPORT

The 82530 Serial Communications Controller (SCC)
is used to provide two channels of serial 1/0. The
SCC generates all baud rate clocks and provides
loopback capability on both channels. Channel B is
RS232C only and is configured as a DCE. Channel A
is factory-default configured for DCE RS232C operation. Channel A may be reconfigured by the user for
.
DTE or RS422 operation.

The iRMX II Operating System software provides the
ability to execute all configurable layers of the iRMX
II software in the MULTIBUS II environment. The
iRMX.1I Operating System also supports all 80286
component applications.

The 82258 ADMA can be programmed to support
both channels A and B to perform movement of
large bit streams or blocks of data.

For on-target MULTIBUS II development, use the
iSBX 218A or a SCSI controller and a floppy or Win,chester drive, or port iRMX application software developed on the System 310, Series 11/111, IV to MULTIBUS II hardware.
Language support for the iSBC 286/100A boards
real address mode includes Intel's ASM 86,
PLIM 86, PASCAL and FORTRAN as well as many
third party 8086 languages. Language support for
virtual address mode operation includes ASM 286,
PLIM 286, PASCAL and C. Programs developed in
these languages can be down-loaded from the Development System to the iSBC 286/100A board via
the iSDM 286 System Debug Monitor. The iSBX
218A can be used to load iRMX software developed
on a System 310. The iSDM 286 monitor also provides on-target program debugging support including breakpoint and memory examination features.

PROGRAMMABLE TIMERS
The iSBC 286/1 OOA board p~ovides three independent, fully programmable 16-bit interval timersl event
counters utilizing the Intel 8254 Programmable Interval Timer. Each counter is capable of operating in
either BCD or binary modes. Three of these timersl
counters are available to the system designer to
generate accurate time intervals under software
control. The outputs may be independently routed to
the 8259A Programmable Interrupt Controller to
count external events. The system software configures each timer independently to select the desired
function. Seven functions are available as shown in
Table 2. The contents of each counter may be read
at any time during system operation.

Table 2. Programmable Time Functions
Function

Operation

Interrupt on
Terminal Count

When terminal count is reached, an interrupt request is generated. This function is
extremely useful for generation of real-time clocks.

Programmable
One-Shot

Output goes low upon request of an external trigger edge or software command and
returns high when terminal count is reached. This function is retriggerable.

Rate Generator

Divide by N counter. The output will go low for one input clock cycle, and the period
from one low going pulse to the next is N times the input clock period.

Square-Wave
Rate Generator

Output will remain high until one-half the count has been completed, and go low for
the other half of the count.

Software Triggered
Strobe

Output remains high until software loads count (N). N counts after count is loaded,
output goes low for one input clock period.

Hardware
Triggered Strobe

Output goes low for one clock period N counts after rising edge counter trigger input.
The counter is retriggerable.
.

Event Counter

On a jumper selectable basis, the clock input becomes an input from the external
system. CPU may read the number of events occurring after the counter "window"
has been enabled or an interrupt may be generated after N events occur in the
system.

1-18

inter

ISBC@ 286/100A MULTIBUS@ II

The MULTIBUS II Interconnect Space Registers allow the software to configure boards eliminating
much of the need for jumpers and wire wraps. The
ISDM 286 Monitor can initialize these registers at
configuration time using user-defined variables. The
monitor can also automatically configure memory
boards, defining the addresses for each board sequentially in relation to the board's physical placement in the card cage. This feature allows for swapping, adding, and deleting of memory boards on a
dynamic basis.

1/0 CAPABILITY
Parallel:

SCSI, Centronics, or general purpose
I/O

Serial:

Two programmable channels using one
82530 Serial Communications Controller

Timers:

Three programmable timers using one
8254 Programmable Interrupt Controller

Expansion: One 8/16-bit iSBX. MULTIMODULE
connector and one 8-bit iSBX MULTIMODULE connector

SPECIFICATIONS
INTERRUPT CAPABILITY
WORD SIZE
Instruction- 8-, 16-, 24-, 32-, or 40-bits

Potential Interrupt Sources-255 individual and 1
broadcast

Data

Interrupt Levels

8- or 16-bits

SYSTEM CLOCK
-8.0 MHz

CPU

16 vectored requests
using two 8259As and
the 80286 NMI line

Serial Communications Characteristics

Numeric Co-Processor- 8.0 MHz

Asynchronous Modes:
CYCLE TIME

5-8-bit character; odd, even, or parity; 1, 1.5, or
2 stop bits

Basic Instruction: 8.0 MHz-375 ns; 250 ns (assumes
instruction in queue)

Independent transmit and receive clocks, 1X,
16X, 32X, or 64X programmable sampling rate

NOTE:
Basic instruction cycle is defined as the fastest instruction time (i.e., two clock cycles)

Error Detection: Framing, Overrun and Parity

Break detection and generation

Bit Synchronous Modes:

Memory Capacity (Maximum)
EPROM:

2732, 8K bytes; 2764, 16K bytes;
27128, 32K bytes; 27256, 64K bytes;
27512, 128K bytes

EEPROM:

2817A, 4K bytes

RAM:

2186, 16K bytes

NOTE:
Two local sites must contain BIST or user-supplied
boot-up EPROM.

SDLCIHDLC flag generation and recognition

Automatic zero bit insertion bit and detection

Automatic CRC generation and detection (CRC
16 or CCITI)

Abort generation and detection

I-field residue handling

SDLC loop mode operation

CCITI X.25 compatible

Byte Synchronous Modes:

1-19

Internal or external character synchronization (1
or 2 characters)

Automatic CRC generation and checking (CRC
16 or CCITT)

IBM Bisync compatible

ISBC@ 286/100A MULTIBUSQI) II

Baud
Rate

Common Baud Rates

Timers

Synchronous
(x1 Clock)

Asynchronous
(x16 Clock)

Input Frequencies: 1.23 MHz ± 0.1 % or 4 MHz
± 0.1 % (Jumper Selectable)

Time Constant

36
49
126
254
510
1022
1363
2046
8190

64K
48K
19.2 K
9600
4800
2400
1800
1200
300
110

6
14
30
62
83
126
510
1394
Output Frequencies/Timing Intervals
Dual Timer/Counter
(two timers cascaded)
Max
Min

Single Timer/Counter

Real-Time Interrupt
Programmable One-Shot
Rate Generator
Square-Wave Rate Generator
Software Triggered Strobe
Hardware Triggered Strobe
Event Counter

Min

Max

500ns
500ns
18.8 Hz
18.8 Hz
500ns
500ns

53.1 ms
53.1 ms
2 MHz
2 MHz
53.1 ms
53.1 ms
5.0 MHz

INTERFACES
PSB Bus:
iLBX II Bus:
iSBX Bus:

1.00 ms
1.00ms
0.000290 Hz
0.000290 Hz
·1.00ms
1.00 ms

57.9 min
57.9 min
1 MHz
1 MHz.
57.9 min
57.9 min

CONNECTORS
All signals TIL compatible
All signals TIL compatible
All signals TIL compatible

SERIAL 1/0
Channel A:

RS232C/RS422
compatible,
configurable as a data set or
data terminal
RS232C compatible, configured
Channel B:
as a data set
Timer:
All signals TIl compatible
Interrupt Requests: All signals TIL compatible

1-20

Location

Function

Part #

P1
P2

PSB Bus
iLBXTM II Bus

603-2-IEC-C096-F
603-2-IEC-C096-F

inter

iSBC® 286/100A MULTIBUS® "

PHYSICAL DIMENSIONS

ENVIRONMENTAL REQUIREMENTS

The iSBC 286/100A board meets all MULTIBUS II
mechanical specifications as represented in IEEE
1296 specification.

Temperature: (Inlet air) at 200 LFM airflow over
boards
Non-operating--40·C to + 70·C
Operating--() to + 55·C
Non-operating-95% RH @ 55·C
Humidity:
Operating-90% RH @ 55·C

Double-High Eurocard Form Factor:
220 mm (8.7 in.)
Depth:
233 mm (9.2 in.)
Height:
Front Panel Width: 20 mm (0.784 in.)
Weight:
653 g (1 lb. 7 oz.)

ELECTRICAL CHARACTERISTICS
The maximum power required per voltage is shown
below. These numbers do not include the power required by the optional memory devices, SCSI PALs,
or expansion modules.
Voltage
(volts)

Max/Typical Current
(amps)

Max Power
(watts)

BTU

GramCalorie

+5
+12
-12

10.31/8.25A
50/40 mA
46/37 mA

54.39W
630mW
580mW

3.13
0.04
0.03

774.2
9.0
8.3

REFERENCE MANUALS

ORDERING INFORMATION

ISBC 286/100A Single Board Manual Computer User's Guide (#149093)

Order Code
SBC286/100A

Manual may be ordered from any Sales Representative, Distribution Office, or from the Intel Literature
Department, 3065 Bowers Ave., Santa Clara, CA
95051

1-21

Description
MULTIBUS II 80286 based Single
Board Computer

iSBC® 186/100* MULTIBUS® II
SINGLE BOARD COMPUTER

•
•
•
•
•

8.0 MHz 80186 Microprocessor with
Optional High Speed 8087-1 Numeric
Data Coprocessor
Optional 82258 Advanced DMA
Controller Providing Four Additional
High Peformance DMA Channels
On-Board 512K Bytes DRAM
Conflgurable as Dual Port Memory
MPC (Message Passing Coprocessor)
Single Chip Interface to the Parallel
System Bus with Full Message Passing
Capability
Four (Expandable to Eight) 28-Pln
JEDEC Sites for PROM, EPROM, or
EEPROM

•

24 Programmable 1/0 Lines
Conflgurable as SCSI Interface,
Centronics Interface, or General
Purpose 110

•
•

Two Programmable Serial Interfaces,
One RS 232C and the Other RS 422A
with Multidrop Capabilities

•

8- or 16-bit iSBXTM IEEE 959 Interface
Connector with DMA Support for 110
Expansion

Resident Firmware Supporting a Reset
Operating System, a Program Table,
and Build-In-Self-Test (BIST)
Diagnostics Including Initialization and
Power-Up Tests

The iSBC@ 186/100 Single Board Computer is a member of Intel's family of microcomputer modules that
utilizes the advanced features of the MULTIBUS@ II system architecture. The 801 B6-based CPU board takes
advantage of VLSI technology to provide economical, off-the-shelf, computer based solutions for OEM applications. All features of the iSBC 186/100 board, including the single chip bus interface (message passing
coprocessor), reside on a 220mm x 233mm (8.7 inches x 9.2 inches) Eurocard printed circuit board and
provide a complete microcomputer system. The iSBC 186/100 board takes full advantage of the MULTIBUS II
bus architecture and can provide a high performance single CPU system or a powerful element for a highly
integrated multi-processing application.

280263-1

"The iSBC" 186/100 is also manufactured under product code piSBC" 186/100 by Intel Puerto Rico, Inc.

1-22

October 1989
Order Number: 280263-002

iSBC® 186/100 MULTIBUS II BOARD

memory and the bus interface (see Table 1). With
the addition of an Advanced DMA (ADMA) 82258
controller, ADMA requests may be generated by either the iSBX interface, the SCSI interface, the bus
interface controller, orthe serial interface (see Table
2). The addition of the ADMA controller also allows
the serial ports to be used in a full-or half-duplex
multidrop application.

FUNCTIONAL DESCRIPTION
Overview
The iSBC 186/100 MULTIBUS II Single Board Computer utilizes the 8 MHz 80186 microprocessor to
provide a range of solutions for various low cost
OEM and end-user applications. Intel's commitment
to offering high performance at a cost effective level
are evident in the design of the iSBC 186/100 Single
Board Computer. The integration of the functions of
a general purpose system (CPU, memory, 1/0 and
peripheral control) into a single board computer imply that the total system's board count, power and
space requirements, and costs are reduced. Combining these cost advantages with the advanced features of the MULTIBUS II system architecture, the
iSBC 186/100 board is ideal for price sensitive MULTIBUS II multi-processing or single CPU applications. Some of the advanced featues of the MULTIBUS II architecture embodied in the iSBC 186/100
board are distributed arbitration, virtual interrupt capabilities, message passing, iPSB bus parity, and
software configurability and diagnostics using interconnect address space.

An additional high performance 8087-1 Numeric
Data Coprocessor may be installed by the user to
significantly improve the iSBC 186/100 board's numerical processing power. Depending on the application, the high speed 8087-1 will increase the performance of floating point calculations by 50 to 100
times.
Table 1. Basic DMA Configuration

80186

Local Bus

DMA Channel 0

Output DMA iPSB Bus
Interface
Input DMA iPSB Bus
Interface

DMA Channel 1

Memory Subsystem
Architecture

The 1M byte memory space of the 80186 is divided
into three main sections. The first section is the
512K bytes of installed DRAM, the second section is
the window into the global 4G bytes memory space
of the PSB bus (PSB memory window address
space) which starts at 512K bytes and goes up to
either 640K bytes or 768K bytes, and the third section is designated for local ROM going from the ending address of the PSB memory window address
space up to, if desired, 1M byte (see Figure 2).

The iSBC 186/100 CPU board supports the PSB bus
features of interconnect address space, Built-InSelf-Test (BIST) diagnostics, solicited and unsolicited message passing, and memory and 110 references. In addition to supporting the PSB bus architecture, other functions traditionally found on Intel
single board computers are included in the iSBC
186/100 board. These traditional capabilities include
iSBX bus expansion; high speed 8087-1 numeric coprocessor; advanced DMA control; JEDEC memory
site expansion; SCSI; Centronics; or general purpose configurable parallel 1/0 interface; serial 1/0;
and programmable timers on the 808186 microprocessor. Figure 1 shows the iSBC 186/100 board
block diagram.

The iSBC 186/100 board comes with 512K bytes of
DRAM installed on the board. This memory can be
used as either on-board RAM or Dual Port RAM by
loading the start and end addresses into the appropriate interconnect registers. The lower boundary
address to the PSB memory window may begin at
any 64K byte boundary and the upper boundary address may end at any 64K byte boundary. Refer to
the iSBC 186/100 Single Board Computer User's
Guide for specific information on programming address spaces into interconnect registers.

Central Processing Unit and DMA
The 80186 is an 8.0 MHz 16-bit microprocessor
combining 'several common system components
onto a single chip (i.e., two Direct Memory Access
lines, three Interval Timers, Clock Generator, and
Programmable Interrupt Controller). The 80186 instruction set is a superset of the 8086 and maintains
object code compatiblity while adding additional instructions.

The memory subsystem, supports 128K bytes or
256K bytes access to the PSB memory address
space. The PSB memory window base address is
fixed at address 512K. The position of the window in
the iPSB memory address space is programmable
and thus allows the CPU to access the complete 4G
byte memory address space of the MULTIBUS II
PSB bus.

In the basic configuration, Direct Memory Access
(DMA) requests are available between the local
1-23

inter

ISBC@ 186/100 MULTIBUS II BOARD

MEMORY SUBSYSTEM

CPU SUBSYSTEM

I
I

8087
Subsection

80186 CPU
Subsection

CPU
Buffers

DRAM
Array
Subsection

Memory
Buffers

--1

r-- -

'II

I/O SUBSYSTEM

I
I
I

8259A
Interrupt
Subslctlon

r-.

I/O Cycle
Interrupt
Subsection

'"
CD

II<

~
CD

82530
Serial I/O
Subsection ,.

ISBX™
Subsection

PSB
Window
Subsection

J" Subsection
Dual-port

8255A
PPI
Subsection

EPROM
Array
Subsection

DMA SUBSYSTEM

0--:

1.
I·

-+l

82258
ADMA
Subsection

DMA
Buffers

PSB SUBSYSTEM
~

Message
Passing
Coprocessor

+-+

8751
Interconnect
Mlcrocontroller

T
[

PARALLEL SYSTEM BUS

I
280263-5

Figure 1.ISBC@ 186/100 CPU Board Block Diagram
The ROM space consists of four 28-pin JEDEC
sockets which take EPROMs, EEPROMs or ROMs
with 28-pin packages, An iSBC 341 28-pin MULTIMODULETM EPROM board can be plugged into 2 of
the JEDEC sockets and provide up to 512K bytes of
ROM memory. Device capacities, which are jumper
selectable, are supported from BK x 8 up to 64K x B.
Once the device capacity is selected, the capacity is
uniform for all sockets.
I/O access from the iSBC 186/100 CPU board
across the PSB bus is accomplished by mapping
64K bytes of local 110 access one to one to the PSB
110 address space. However, only the upper 32K
bytes are available to access the PSB 110 address
space because the lower 32K bytes on the iSBC
186/100 board are reserved for local on-board 110.

On-Board, Local Functions
PROGRAMMABLE TIMERS AND INTERRUPT
.
CONTROL
The 80186 microprocessor on the iSBC 1B6/100
board provides three independent, fully programmable 16-bit interval timers/event counters. In conjunction, two 8259A Programmable Interrupt Controllers
(PIC) on the iSBC 186/100 board are used in a master/slave configuration for processing on-board'interrupts. At shipment, the B01 B6 interrupt controller
and one PIC are connected as slaves to the master
PIC. The first timer on the 80186 microprocessor is
routed to the master Programmable Interrupt Controller and the second CPU timer is routed to the
slave PIC. This architecture thus supports software

1-24

intJ

iSBC® 186/100 MULTIBUS II BOARD

Table 2. DMA Configuration with ADMA Option
80186

Local Bus

DMA Channel 0
DMA Channel 1

Serial Channel B DMA
Serial Channel B DMA or Paraiiel Port

ADMA82258
DMA Channel 0
DMA Channel 1
DMA Channel 2

Input DMA Bus Interface
Output DMA Bus Interface
Half-duplex Fast Serial Interconnect 1
Channel A or Interrupt 1 from iSBX Bus if Used with an iSBC 341
EPROM MULTIMODULE Board
Fuii-duplex Fast Serial Interconnect 1
Channel A or iSBX Bus DMA Channel if Used with an iSBC 341
EPROM MULTIMODULE board.

DMA Channel 3

NOTE:
When a MULTIMODULETM expansion board is installed and DMA support is required, then an ADMA controller must also be
installed. For additional optional configurations see the iSBC 1861100 Single Board Computer User's Guide.

PSB
MEMORY
MAP

D~anB
:::::;....--MB II
MEMORY

1024K

ISBC"
1861100
MEMORY
MAP
ONBOARD
EPROM

768K
PSB
MAYBE____
WINDOW
640K
512K

BASE ADDRESS IS ANY
MULTIPLE OF 128K OR 256K

---

MBII
WINDOW

I',

/....,.....0"..

BASE ADDRESS IS ANY

" "-

ONBOARD
DRAM

/_OF""""'-' .•'"'OW "'.

512KB

,//
..,/
0

0
280263-3

Figure 2. Memory Mapping Diagram

1-25

intJ

iSBC® 186/100 MULTIBUS II BOARD

programmable timer interrupts. In addition, directvectored interrupt capability of the serial communication controller (SCC) may be used. Figure 3 depicts the interrupts in- terms of their priorities.
Interrupt Services
80186 Timer 0
8087-1 Error Interrupt
Message Interrupt
iPSB Bus Error Interrupt
82530 SCC Interrupt
82258 ADMA Interrupt
80186 Slave PIC Interrupt
8259 Slave PIC Interrupt
PPI 0 Interrupt
iSBX Bus Interrupt 0
iSBX Bus Interrupt 1
Interconnect Space Interrupt
80186 Timer 1 Interrupt
PPI 1 Interrupt
Ground

The Centronics interface requires very little software
overhead since a user supplied PAL device is used
to provide necessary handshake timing. Interrupts
are generated for printer fault conditions and a DMA
request is issued for every character.

Interrupt Priority
Master Level 0
1
2
3
4
5
6
7
Slave 0
1
2
3
4
5
6&7

Figure 3. iSBC® 186/100
Interrupt Priority Scheme

PARALLEL/SCSI PERIPHERAL
INTERFACE

SERIAL I/O LINES
The iSBC 186/100 board has one 82530 Serial
Communciations Controller (SCC) to provide 2 channels of serial I/O. The SCC generates all baudrate
clocks and provides loopback capability on both
channels. Channel A is configured for RS 422A multidrop DTE application. Channel B is RS 232C only
and is configured as DTE.
The multidrop configuration may either full-or halfduplex. A full-duplex multidrop configuration with a
single master driving the output lines allow a slave to
monitor the data line and to perform tasks in parallel
with tasks performed on another slave. However,
only the selected slave may transmit to the master.
A half-duplex multidrop configuration is more strict in
its protocol. Two data lines and a ground line are
required between a master and all slaves in the system and although all units may listen to whomever is
using the data line, the system software protocol
must be designed to allow only one unit to transmit
at any given instant.

The iSBC 186/100 board includes an 8255A parallel
peripheral interface that consists of three 8-bit parallel ports. As shipped, these ports are configured for
general purpose I/O. Programmed PAL devices
(Programmable Array Logic) and the bi-directional
octal transceiver 74LS245 are provided to make it
easy to reconfigure the parallel interface to be com'patible with the SCSI (Small Computer System Interconnect) peripheral interface. Alternatively, the iSBC
186/100 board provides the jumper configuration facilities for operating the parallel interface as an interrupt driven interface for a Centronics compatible line
printer by adding one PAL and reconfiguring jumpers. Both interfaces may use the 82258 DMA controller for data transfers if desired.

BUILT-IN-SELF-TEST DIAGNOSTICS
On-board built-in-self-test (BIST) diagnostics are implemented using the 8751 microcontroller and the
80186 microprocessor. On-board tests include initialization tests on DRAM, EPROM, the 80186 microcontroller, and power-up tests. Additional activities performed include iDX, the Initialization and Diagnostics eXecutive which provides initialization at
power-up and a program table which allows users to
add custom code in EPROM while still maintaining
full use of the factory supplied BISTs.
Immediately after power-up and the 8751 microcontroller is intialized, the 80186 microprocessor begins
its own initialization and on-board diagnostics. Upon
successful completion of these activities, the iDX invokes the user-defined program table. A check is
made of the program table and the custom programs that the user has defined for his application
will then execute sequentially.

The SCSI interface allows multiple mass storage peripherals such as Winchester disk drives, floppy disk
drives, and tape drives to be connected directly to
the iSBC 186/100 board. A sample SCSI application
is shown in Figure 4. The SCSI interface is compatible with SCSI controllers such as Adaptek 4500,
DTC 1410, Iomega Alpha 10, Shugart 1601 and
1610, Vermont Research 8403, and Xebec 1410.

1-26

iSBC® 186/100 MULTIBUS II BOARD

SCSI BUS

ISBC~

1861100

BOARD

MULTIBUS~ II PARALLEL SYSTEM BUS

280263-4

Figure 4. SCSI Application
and independent hardware vendors. Custom iSBX
bus MULTIMODULE boards designed for MULTIBUS or proprietary bus systems are also supported
as long as the IEEE 959 iSBX bus specification is
followed.

BISTs improve the reliability, error reporting, and recovery capability of MULTIBUS II boards. In addition,
these test and diagnostics reduce manufacturing
and maintenance costs for the user. A yellow LED
(labeled 'BIST) ori the front panel indicates the
status of the initialization checks and the power-up
tests. It is illuminated if any of the initialization
checks fail and remains off if the board successfully
completes its tests. The LED also illuminates when
the BIST tests start and stays on until the test complete successfully. The results of the BIST diagnostics are stored in the last 6 registers of the Header
Record in Interconnect space.

PSB BUS INTERFACE SILICON
The MPC (message passing coprocessor) provides
all necessary PSB bus interface logic on a single
chip. Services provided by the MPC include memory
and 1/0 access to the PSB by the 80186 processor,
bus arbitration, exception cycle protocols, and transfers as well as full message passing support. Dual
port architecture may be implemented using tHe
message passing coprocessor.

iSBXTM BUS MULTIMODULETM
EXPANSION
One 8-or 16-bit iSBX bus MULTIMODULE connector
is provided for 1/0 expansion. The iSBC 186/100
board supports both 8-bit and 16-bit iSBX modules
through this connector. DMA is also supported to
the iSBX connector and can be configured by programming the DMA multiplexor attached to the
82258 DMA component. The iSBX connector on the
iSBC 186/100 board supports a wide variety of standard MULTIMODULE boards available from Intel

Interconnect Subsystem
The interconnect subsystem is one of the four MULTIBUS II address'spaces, the other three being
memory space, 1/0 space, and message space. The
purpose of interconnect space is to allow software
to initialize, identify, configure, and diagnose the
boards in a MULTIBUS II system. All Intel MULTIBUS II boards support interconnect space.

1-27

ISBC~

186/100 MULTIBUS II BOARD

The interconnect space is organized into a group of
8-bit registers called a template. The interconnect
registers are organized into functional groups called
records. Each register belongs to only one record,
and there are three basic types of interconnect records: a header record, a function record, and an End
of Template (EOT) record. The 80186 on the SBC
186/100 board accesses its own template via the
interconnect address space on the PSB bus.
The header record provides board and vendor 10
information, general status and control information,
and diagnostic status and control information. The
function record contains parameters needed to perform specific functions for the board. For example,
an PSB memory record contains registers that define the start and end address of memory for access
across the PSB bus. The number of function records
in a template is determined by the manufacturer.
The EOT record simply indicates the end of the interconnect template.

Cycle Time
BASIC INSTRUCTION: 8.0 MHz - 500 ns for minimum code read

Memory Capacity
LOCAL MEMORY
NUMBER OF SOCKETS: four 28-pin JEOEC sites
Memory
Capacity
EPROM
EPROM
EPROM
EPROM

8K
16K
32K
64K

Chip Example

x8
x8
x8
x8

2764
27128
27256
27512

ON·BOARD RAM
There are two types of registers in the MULTIBUS II
interconnect space, read~only and software configurable registers. Read-only registers are used to hold
information such as board type, vendor, firmware
level, etc. Software configurable registers allow read
and write operations under software control and are
used for auto-software configurability and remotel
local diagnostics and testing. Software can be used
to dynamically change bus memory sizes, disable or
enable on-board resources such as PROM or
JEOEC sites, read if an iSBX Board or PROM are
installed as well as access the results of Built-InSelf-Tests or user installed diagnostics. Some of the
interconnect registers on the iSBC 186/100 board
perform functions traditionally done by jumper
stakes. Interconnect space support is implemented
with the 8751 microcontroller and iPSB bus interface
logic.

SPECIFICATIONS
Word Size

512K bytes 64K x 4 bit Dynamic RAM

110 Capability
Serial:
- Two programmable channels using one 82530
Serial Communications Controller
-

19.2K baud rate maximum in full duplex in asynchronous mode 'or 1 megabit per second in full
duplex in synchronous mode
Channel A: RS 422A with OTE multidrop capability
Channel B: RS 232C compatible, configured as
OTE

Parallel: SCSI, Centronics, or general purpose

1/0
Expansion: One 8-or 16-bit IEEE 959 iSBX MUL~
TIMOOULE board connector supporting OMA

Serial Communications Characteristics

INSTRUCTION: 8-, 16-, '24-,32-, or 40-bits
ASYNCHRONOUS MODES:
• 19.2K baud rate maximum in full duplex

DATA: 800r 16-bits

System Clock

• 5-8-bit character; odd, even, or parity; 1, 1.5, or 2
stops bits

CPU: 8.0 MHz

• Independent transmit and receive clocks, 1X,
16X, 32X, or 64X programmable sampling rate
• Error detection: Framing, Overrun, and Parity

NUMERIC COPROCESSOR: 8.0 MHz (part number
8087-1)

• Break detection and generation

1-28

inter

iSBC@ 186/100 MULTIBUS II BOARD

BIT SYNCHRONOUS MODES:
• 1 megabit per second maximum in full duplex

Interfaces

• SOLC/HOLC flag generation and recognition
• Automatic zero bit insertion and detection
• Automatic CRC generation and detection (CRC
16 or CCITT)

PSB BUS:

As per IEEE/ANSI 1296 MULTIBUS /I bus architecture specification

• Abort generation and detection

ISBX BUS:

• I-field residue handling
• SOLC loop mode operation

As per IEEE 959 specification

• CCITI X.25 compatible

CONNECTORS
Location
P1

BYTE SYNCHRONOUS MODES:
• Internal or external character synchronization (1
or 2 characters)

• Automatic CRC generation and checking (CRC
16 or CCITT)
• IBM Bisync compatible

Function
PSB Bus

Part #
603-2-1 EC-C096-F

Physical Dimensions
The iSBC 186/100 board meets all MULTIBUS /I
mechanical specifications as presented in the MULTIBUS /I specification (#146077)

Timers
DOUBLE-HIGH EUROCARD FORM FACTOR:

Three programmable timers on the 80186 microprocessor

Depth:

INPUT FREQUENCIES:

Frequencies supplied by the internal 80186 16 MHz
crystal
Serial chips:

220 mm (8.7 in.)

233 mm (9.2 in.)
Height:
Front Panel Width: 20 mm (0.784 in.)
Weight:
743 g (26 oz.)

crystal driver at 9.8304 MHz divide
by two

Environmental Requirements

iSBX connector: 9.8304 crystal driven at 9.8304
MHz

Temperature: Inlet air at 200 LFM airflow over all
boards
Non-operating: -40' to + 70'C

Interrupt Capacity
POTENTIAL INTERRUPT SOURCES:

Operating: O' to + 55'C
Non-operating: 95% RH @55'C, noncondensing

255 individual and 1 broadcast

Operating: 90% RH @ 55'C, non-condensing

Humidity:

INTERRUPT LEVELS:

Electrical Characteristics

12 vectored requests using two 8259As, 3 grounded
inputs, and 1 input to the master PIC from the slave
PIC

The maximum power required per voltage is shown
below. These numbers do not include the power required by the optional memory devices, SCSI PALs,
or expansion modules.

INTERRUPT REQUESTS:

All signals TIL compatible

1-29

Voltage
(Volts)

Max Current
(Amps)

Max Power
(Watts)

+5
+12
-12

6.5mA
50mA
50mA

34.13W
0.06W
0.06W

intJ

ISBC@ 186/100 MULTIBUS II BOARD

Reference Manuals

ORDERING INFORMATION

iSBC 186/100 Single Board Computer User's Guide
(#148732)

SBC186100

Part Number Description
MULTIBUS II 80186-based Single
Board Computer

Manuals may be ordered from any Sales Representative, Distribution Office, or from the Intel Literature
Department, 3065 Bowers Avenue, Santa Clara, CA,
95051.

1-30

THE MULTIBUS®II PC SUBSYSTEM

PC/AT* COMPATIBILITY COMES TO MULTlBUS®1I SYSTEMS
The Intel MULTIBUS®II PC Subsystem combines the power of the 386™ microprocessor,
the multi-processing capabilities of the MULTI BUS II architecture and the large base of
DOS compatible software into a high performance IBM PC/AT compatible two board set.
When used with a standard PC/AT' compatible keyboard and VGA compatible monitor
this subsystem provides an excellent foundation for a human interface with color graphics
for MULTIBUS II systems. Running off-the-shelf software packages it is sUitable for data
acquisition or process monitoring applications, and can be easily customized uSing a
variety of available PC compatible products.

FEATURES
CPU BOARD
• Fully IBM PC/AT compatible subsystem
running at 16 Mhz 386 32-bit CPU.
• Includes socket for Intel 80387 or
Weitek numeric co-processor chip, 64 K
of high speed SRAM cache, 2 serial
ports, 1 parallel port, keyboard and
floppy drive controllers.
• Completely MUlTIBUS II systems
architecture compatible Including
ADMA, MPC and 8751 Interconnect
controller.

PERIPHERAL COMPANION BOARD
• ST-506/ST-412 compatible Hard Disk
Controller
• VGA graphics controller, with VGA,
CGA, EGA, and mono-graphics
software compatibility
• Built-in CSM functionality

in1:er---------September. 1989

Intel Corporation 1989

Order Number 280673·002

1-31

FEATURES
PART OF THE MULTIBUS®II FAMILY
Now PC/AT* compatibility has come to a MULTI BUS
II CPU. The MULTIBUS II Parallel System Bus is the
bus of choice for Real Time multiprocessing. Its
advanced bus architecture includes such features as
a high speed (32 Mbyteslsec) Parallel Systems Bus
(PSB) with message passing and bus parity
detection, virtual interrupts, simplified systems
configuration through interconnect space, and
extensive power-up testing. Now our MULTIBUS II
family is even more complete with DOS
complementing iRMX(!l, iRMK"', and UNIX'
operating systems, and bringing with it a complete
human interface including keyboard controller and
VGA graphics.

386 MICROPROCESSOR SPEED AND
PERFORMANCE
The iSBC 386/PC16 CPU board features a 3861'11 CPU
running at 16 Mhz and 64 K of ) wait state (read hit)
. cache memory for 32-bit speed and performance.
Performance can be even further enhanced by
adding an Intel 80387 or Weitek math co-processor in
the provided socket.
As much as 16 M-byte of DRAM can be provided onboard using memory expansion modules. For full
IBM PC/AT software compatbility the iSBC 386/PC16
comes with an Award BIOS and runs either PC-DOS'
or MS-DOS'. As a 386™ microprocessor-based PC
platform, UNIX V/386 can also be easily ported to this
board.

INTEGRATES EASILY INTO A MULTIBUS®II
SYSTEM
The ISBC 386/PC16 PCU board was designed to
integrate easily into a MULTIBUS II system. Hardware
support includes the MULTIBUS II Message Passing
Co-processor (MPC), 8751 interconnect space
controller, and 82258 ADMA controller to provide full
message passing support. It can also access global
memory and 110 on the Parallel Systems Bus.
Conforming too the MULTIBUS II Systems
Architecture (MSA) the SBC 386/PC16 includes
firmware support for BISTs (Built-In Self Tests), lOX
(Initialization and Diagnostics eXecutive), and DOS
MULTI BUS II Transport Protocol. A DOS Transport
Call Library, provided on a floppy disk, allows user
implementation of message passing based
communication and data sharing with other
MULTI BUS II CPUs and peripherals.

BACKPLANES AND ADAPTOR BOARD
Rounding out the complement of products in the Intel
MULTIBUSS II PC Subsystem family are 2 and 4 slot
backplanes for the Ps/aPC bus (the PC bus brought
out on the MULTIBUS II P2 connector) and an
Adaptor Board. Intended for development purposes,
the iSBC PCSYS/900 Adaptor Board plugs into a
MULTIBUS II card cage or chassis and
accommodates either four "half size" PC/XT" add-on
cards or two "half size" PC/XT and either two PC/AT
"full size" or two PC/XT '1ull size" add-on boards.

HIGH RELIABILITY

FULL COMPLEMENT OF PC
PERIPHERALS
To minimize the need for add-in cards, the iSBC 3861
PC16 CPU board includes 2 serial ports, 1 Centronics
compatible parallel port, keyboard controller, and
floppy disk controller.
The iSBC PCSYS/100 Peripheral Companion Board
adds to that a hard disk controller, and a VGA
graphics controller which is software compatible with
EGA, CGA, and Hercules" monochrome graphics
modes. In addition, it provides built-in MULTI BUS II
Central Services Module Functionality.

'UNIX is a Irademark of AT&T
'PC-DOS. PC/XI. and PC/AT are trademarks of International BUSiness Machines
'MS-DOS IS a trademark of Microsoft
'Hercules IS a trademark of Hercules Computer Technology, Inc.

1-32

Intel has designed the MULTIBUSS II PC Subsystem
for high reliability. Extensive use of CMOS circuitry
keeps the boards running cooler, and since excess
heat can cause premature failure, running longer.
DIN pin and socket connectors ensure reliable
connectivity with the backplane, and parity error
checking in the DRAM circuitry and on the Parallel
Systems Bus improves overall system integrity.
Furthermore the boards conform to Intels strict
design and manufacturing standards.

WORLD WIDE SERVICE AND SUPPORT
Should this or any Intel board ever need service, Intel
maintains a world wide network of service and repair
facilities to keep you and your customers up and
running. In addition, should you need system level
design support, our international Systems
Engineering organization is available to integrate Intel
boards and systems components into your products.

SPECIFICATIONS
MULTIBUS®II PC SUBSYSTEM CONFIGURATION GUIDE
When the iSBCI!l386/PC16FOx CPU is used with the iSBC PCSYS/100 Peripheral Companion Board and/or the
iSBC PCSYS/900 Adaptor Board either an iSBC PCSYS/602 two-slot or iSBC PCSYS/604 four-slot backplane
is required to bus the AT signals between the P2 connectors. Please use the following guide when ordering to
select the correct backplane.
386/PC16FOx Only ...................... None required, however the iSBC PCSYS/602 2-slot backplane provides a
connector which facilitates connecting the floppy drive.
386/PC16FOx and PCSYS/100 ............ Order ISBC PCSYS/602 2-slot Backplane
Peripheral Companion Board
386/PC16F01 or F04 and ................ Order ISBC PCSYS/602 2-slot Backplane
PCSYS/900 Adaptor Board
386/PC16F02 or F08 and ................ Order iSBC PCSYS/604 4-slot Backplane
PCSYS/900 Adaptor Board
386/PC16FOx, PCSYS/100 ............... Order iSBC PCSYS/604 4-slot Backplane
Peripheral Companion Board and
PCSYS/900 Adaptor Board
NOTE: If stacking multiple memory modules, order ISBC PCSYS/604 4-slot backplane.

Multlbuan

PC Bus

S03861PC CORE

MuJl.bus II Interlace

Figure 1: iSBC 386/PC16 Functional Block Diagram

4 XT "hoff sIZe" or
2 XT "half size" and
elher 2 XT or AT
-full size- add-on
boards

•

~~IY

Board

Another
Mul~bus

Board

Another
Muilibus II
Board

LBX II Sub·bus

Parallel System Bus

Figure 2: MULTIBUS@II PC Subsystem Block Diagram

SPECIFICATIONS
CPU BOARD-SBC 386/PC16

P2IaPC BACKPLANES-SBC PCSYS/602
AND SBC PCSYS/604

CPU
386 microprocessor running at 16Mhz

• Available in 2 and 4 slot versions

DRAM Memory
32-bit parity protected memory:
Model
Supplies
SBC 386PC16 F01
1 Mb
SSC 386PC16 F02
2Mb
SBC 386PC16 F04
4Mb
SBC 386PC16 F08
8Mb
Note: Model suffixes F02 and F08 require two
MULT/BUS 1/ card slots, Model suffixes F01 and F04
require only one MULT/BUS 1/ card slot.
Memory expansion modules-one may be added'
to base models above
Model
Supplies
SBC MM01 FP
1 Mb
SBC MM02FP
2Mb
SBC MM04 FP
4Mb
SBC MM08 FP
8Mb
SRAMcache
Capacity:
64K
Speed:
o wait state on read hit
2 wait states on write
3 wait states on read miss
EPROM Memory
Two 32-pin JEDEC sites containing 256 K of EPROM
memory with Awards BIOS and MSA firmware.
Two additional 32-pin JEDEC sites provided for user
EPROM or EEPROM memory. Circuitry is provided to
write as well as read EEPROM memory.

PERIPHi:RAL COMPANION BOARDSBC PCSYSIfOO
Hard Disk Controller
• PC/AT Compatible Winchester Controller
• Supports up to two ST-506/ST-412 drives
Graphics
• Supports VGA, EGA, CGA, and Hercules
Compatible graphics
• Four text mode resolutions: 40 x 25, 80 x 25,
132 x 25, 132 x 43
• Three graphics mode resolutions: 640 x 480 with
16 colors, 960 x 720 with 4 colors, and 1280 x 960
monochrome

ADApTOR BOARD-SBC PCSYS/900
• Fully accommodates a total of four half or 3/4
length PCIXT and PC/AT add-in cards in the
follOWing combinations: either four PC/XT or two
PC/AT and two PC/XT add-in cards
• With restrictions, in some configurations two full
size PC/AT or PC/XT add-in cards can be
accommodated
• Adaptor board is 3 MULTIBUS II bard slots wide

ENVIRONMENTAL REQUIREMENTS
Storage Temperature:
Operating Temperature:
Storage Humidity:
Operating Humidity:

-40° to 70°C (0° to
158°F)
O°C to 55°C (32 0 to
131°F)
5%-95% non-condensing
at 55°C
8%-90% non-condensing
at 55°C

.ORDERING INFORMATION
SBC386PC16F01
SBC386PC16F02
SBC386PC16F04
SBC386PC16F08
SBCPCSYS100

S301K3
SBCPCSYS602
SBCPCSYS604
SBCPCSYS900
SBC MM01 FP
SBC MM02 FP
SBC MM04 FP
SBC MM08 FP

CSM
• ASSigns card slot and arbitration IDs at initialization
• Generates system clock for all agents on the PSB
• Provides system wide reset signals for power-up,
warm reset, and power failure
• Detects bus timeouts
1-34

386-based PC compatible CPU
board with 1 Mb of DRAM
3S6-based PC compatible CPU
board with 2 Mb of DRAM
386-based PC compatible CPU
board with 4 Mb of DRAM
386-based PC compatible CPU
board with 8 Mb of DRAM
Companion board with VGA
graphics, HD controller and
CSM functionality
101-key enhanced AT-style
keyboard
2-slot Backplane for the P2/aPC
bus
4-slot Backplane for the P2/aPC
bus
Adaptor Board
1 Mb Memory Expansion
Module
2 Mb Memory Expansion
Module
4 Mb Memory Expansion
Module
8 Mb Memory Expansion
Module

MULTIBUS® II
Memory Expansion Boards

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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I
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I
I
I
I
I
I
I
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I
I
I
I

• +.-.I®
In'ell

iSBC® MM01, MM02, MM04, MM08*
HIGH PERFORMANCE MEMORY MODULES

High Speed Parity Memory
• Provides
Expansion for Intel's iSBC® 386/2X,

to Provide up to 16M Bytes
• of High Speed
Memory for MULTIBUS I
Stac~able

iSBC 386/3X and iSBC 386/1XX
CPU Boards

•
•

and MULTIBUS II CPU Boards

•
•

Available in 1M, 2M, 4M, and 8M Byte
Sizes
32 Bits Wide with Byte Parity

Supports 32-Bit, 16-Bit and 8-Bit Data
Paths
Supports Independent Read/Writes

• Easily Installed

The iSBC MM01, iSBC MM02, iSBC MM04, and iSBC MM08 DRAM memory modules are members of Intel's
complete line of iSBC memory and I/O expansion boards. The MM-Series of memory modules use a dedicated interface to maximize CPU/memory performance. The iSBC MM series of memory modules have been
designed to provide both the on-board and expansion memory for the iSBC 386/2X, the iSBC ~86/3X and the
iSBC 386/1 XX CPU Boards.
The modules contain (respectively) 1M byte, 2M, 4M, and 8M bytes of read/write memory using surface
mounted DRAM components (see Figure 1).
Due to the high speed interface of the memory modules, they are ideally suited in applications where memory
performance is critical.
'

280346-1

Figure 1. iSBC® MM08 Memory Module
·The iSBCI!> MM01, MM02, MM04, MMOB Memory Modules are also manufactured under product code piSBCI!> MM01,
MM02, MM04, MMOB by Intel Puerto Rico, Inc.

2-1

September 1989
Order Number: 280346-002

inter

ISBC~

MM01, MM02, MM04, MM08 MODULES

FUNCTIONAL DESCRIPTION

Installation

The iSBC MMxx memory modules provide high performance, 32-bit parity DRAM memory for the MULTIBUS I and MULTIBUS II CPU boards. These CPU
boards come standard with one MMxx module installed, with memory expansion available through
the addition of a second stackable iSBC MMxx module.

The iSBC MMxx memory modules are easily installed by the user. Each module includes a'i necessary connectors, screws, and other hardware for installation, either as a second stacked module or as a
replacement fora module with less memory.

SPECIFICATIONS
Memory Access Capabilities

Word Size Supported

The dynamic RAM memory of the memory modules
is accessed through the dedicated memory module
interface.

8-, 16-, or 32-bits

Memory Size

The MM memory module is designed for direct
transfer of data between the CPU and the memory
module without accessing the MULTIBUS interface.

iSBC
iSBC
iSBC
iSBC

MM01/MM02/MM04/MM08
Memory Size

MM01
MM02
MM04
MM08

1,048,576 bytes
2,097,152 bytes
4,194,304 bytes
8,388,608 bytes

Access Time (All Densities)

The iSBC MM01, iSBC MM02, iSBC MM04, and
iSBC MM08 modules can be stacked on the CPU
baseboard in any combination.

Read/Write -

107 ns (max)

The MMxx-series memory modules run with the
iSBC 386/2X and iSBC 386/116 Boards at 16 MHz,
and with the iSBC 386/3X and iSBC 386/120
Boards at 20 MHz. Wait state performance information with each of these CPU baseboards is contained in the Hardware Reference Manual for the
specific CPU baseboard.

Data Bus Structure
The MMxx-series memory modules use a 32-bit wide
data path with storage for byte parity that can accommodate 8-bit byte, 16-bit or 32-bit word data
transfers. In addition, the data path is capable of
independent byte operations. This means that one
byte can be written while the other three bytes (or
any other combination) can be read.

Cycle Time (All Densities)
Read/Write -

200 ns (min)

Parity
Power Requirements

One parity bit is provided for each of the four, 8-bit
bytes in the 32-bit wide data path. For special applications, the parity bits can serve as data bits making
possible 9-, 18-, or 36-bit data transfers.

Voltage -5 VDC ±5%
Memory addressing for the iSBC MMxx memory
modules is controlled by the host CPU board over
the memory module interface. The maximum system
RAM size is 16M Bytes.

Memory Function
The module protocol supports standard dynamic
RAM READ, WRITE, RAS· only REFRESH cycles,
and CAS· before RAS· REFRESH.

2-2

intJ

iSBC® MM01, MM02, MM04, MM08 MODULES

Top View

ISBC®MMxx
MEMORY MODULE

4.25"
7.05"

CPU BASEBOARD

CONNECTOR

OUTLINE
r------..
.. _-----_ ..
I

4.175"

280346-2

Side View
iSBC® MMxx
MEMORY MODULE

STANDOFF

0.847"
(:1:0.023)

CPU BASEBOARD
280346-3

Single iSSC® MMxx Memory Module

Side View
ISBC® MMxx
MEMORY MODULES
STIFFENER

1.564"
(:1:0.033)

0.525 INCH STACKING CONNECTOR
STANDOFFS
0.625 INCH BASEBOARD CONNECTOR

CPU BASEBOARD
280346-4

Stacked iSSC® MMxx Memory Modules

2-3

intJ

iSBC@ MM01, MM02, MM04, MM08 MODULES

Environmental Requirements

ORDERING INFORMATION

Operating Temperature -

Part Number

Storage Temperature -

O·C to 60·C
40·C to

+ 75·C

Description

iSBCMM01

1M Byte RAM Memory Module

iSBCMM02

2M Byte RAM Memory Module

Cooling Requirement - 3 cubic feet per minute of
airflow at an ambient temperature of O·C to 60·C

iSBCMM04

4M Byte RAM Memory Module

iSBCMM08

8M Byte RAM Memory Module

Operating Humidity without condensation

The Memory Modules ship with the required hardware (connectors, mounting screws, stand-ofts, etc.)
to stack a second module on the module already
mounted on the base CPU board.

To 95% relative humidity

Physical Dimensions
Module Alone:
Width -

4.250 inches (10,795 cm)

Length -

4.175 inches (10,604 cm)

Height -

0.500 inches (1,270 cm)

Weight -

iSBC MM01 IMM04: 2.5 ounces (70.0 gm)
iSBC MM02/MM08: 3.5 ounces (110.0 gm)

2-4

intel®
iSBC® MM01FP, MM02FP, MM04FP, MM08FP*
HIGH PERFORMANCE MEMORY MODULES

•
•

High Speed Parity Memory
• Provides
Expansion for Intel's iSBC® 386/2X,
iSBC 386/3X and iSBC 386/1XX CPU
Boards

•
•

Available in 1M, 2M, 4M, and 8M Byte
Sizes

Stackable to Provide up to 16M Bytes
of High Speed Memory for MULTIBUS I
and MULTIBUS II Boards
Supports 32-Bit, 16-Bit and 8-Bit Data
Paths

Independent Read/Writes
• Supports
Easily Installed
•

32 Bits Wide with Byte Parity

The iSBC MMOX and iSBC MMOXFP DRAM memory modules are members of Intel's complete line of iSBC
memory and 1/0 expansion boards. The MM-Series of memory modules use a dedicated memory interface to
maximize CPU/memory performance.

Figure 1. ISBC® MM08FP Memory Module

281010-1

The iSBC'" MM01 FP, MM02FP, MM04FP, MMOBFP memory modules are also manufactured under product code piSBC'"
MM01FP, MM02FP, MM04FP, MMOBFP by Intel Puerto Rico, Inc.

2-5

September 1989
Order Number: 281010·001

intJ

iSBC® MM01FP, MM02FP, MM04FP, MM08FP MODULES

FUNCTIONAL DESCRIPTION

Memory Function

The iSBC MM-Series provide high performance, 32bit parity DRAM memory for the MULTIBUS I and
MULTIBUS II boards. These CPU boards come standard with one MM-Series module installed, with
memory expansion available through the addition of
a second stackable iSBC MM-Series module.

The module protocol supports standard dynamic
RAM READ, WRITE, RAS· only REFRESH cycles,
and CAS' before RAS· REFRESH.

Installation

The iSBC MM-Series memory modules are easily installed by the user. Each module includes all necessary connectors, screws, and other hardware for installation, either as a second stacked module or as a
replacement for a module with less memory.

Memory Access Capabilities
The dynamic RAM memory of the memory modules
is accessed through the dedicated memory module
interface.

SPECIFICATIONS

The MM memory module is designed for direct
transfer of data between the CPU and the memory
module without accessing the MULTIBUS interface.

Word Size Supported
MM01/MM02/MM04/MM08
Memory Size

8-, 16-, or 32-bits

The iSBC MM01, iSBC MM02, iSBC MM04, and
iSBC MM08 modules can be slacked on the CPU
baseboard in any combination.

Memory Size
iSBC
iSBC
iSBC
iSBC

Data Bus Structure
The MM-Series memory modules use a 32-bit wide
data path with storage for byte parity that can accommodate 8-bit byte, 16-bit or 32-bit word data
transfers. In addition, the data path is capable of
independent byte operations. This means that one
byte can be written while the other three bytes (or
any other combination) can be read.

MM01
MM02
MM04
MM08

1,048,576
2,097,152
4,194,304
8,388,608

bytes
bytes
bytes
bytes

Access Time (All Densities)
Read/Write -

107 ns (max)-MMOX

Read/Write -

88 ns (max)-MMOXFP

Power Requirements
Parity

Voltage -5 VDC ±5%

Memory addressing for the iSBC MM-Series memory
modules is controlled by the host CPU board over
the memory module interface. The maximum system
RAM size is 16M Bytes.

2-6

inter

ISBC@ MM01FP, MM02FP, MM04FP, MM08FP MODULES

Top View

7.05"

f
l

CPU BASEBOARD

r-------'"

CONNECTOR
OUTLINE

4.25"

ISBC(Q)MMxx
MEMORY MODULE

'--------'

281010-2

Side View
ISBC(Q) MMxx
MEMORY MODULE

STANDOFF

0.B47"
(:to.023)

CPU BASEBOARD
281010-3

Single ISBC® MMxx Memory Module

Side View
ISBC(Q) MMxx
MEMORY MODULES
STIFFENER

1.564"
(:to.033)

0.525 INCH STACKING CONNECTOR
STANDOFFS
0.625 INCH BASEBOARD CONNECTOR
CPU BASEBOARD
281010-4

Stacked ISBC® MMxx Memory Modules

2-7

intJ

iSBC®MM01FP, MM02FP, MM04FP, MM08FP MODULES

Environmental Requirements

ORDERING INFORMATION
Part Number

Operating Temperature --'- O°C to 60°C

+ 75°C

Storage Temperature -

40°C to

Operating Humidity without condensation

To 95% relative humidity

iSBC MM02FP 2M Byte Fast Page Memory Module
iSBC MM03FP 4M Byte Fast Page Memory Module
iSBC MM04FP 8M Byte Fast Page Memory Module
The Memory Modules ship with the required hardware (connectors, mounting screws, stand-ofts, etc.)
to stack a second module on the modl,lle already
mounted on the base CPU board.

Physical Dimensions
Module Alone:
Width -

4.250 inches (10,795 cm)

Length -

4.175 inches (10,604 cm)

Height -

0.500 inches (1,270 cm)

Weight -

Description

iSBC MM01 FP 1M Byte Fast Page Memory Module

iSBC MM01/MM04: 2.5 ounces (70.0 gm)
iSBC MM02/MM08: 3.5 ounces (11 0.0 gm)

2-8

iSBC® MEM/320, 340*
CACHE-BASED MULTIBUS® II RAM BOARDS

•
•
•

32-bit MULTIBUS® II Parallel System
Bus (PSB) and Local Bus Extension II
(iLBXTM II Bus) Interface Support

• MULTI BUS

Zero Wait State Over iLBXTM on a
Cache Hit, One Wait State for Cache
Misses and Writes at 8 MHz

•

Dual Port Memory with Four Versions
Available:
2M Bytes
iSBC MEM/320
4M Bytes
iSBC MEM/340

Memory Initialization at
• Automatic
Power-Up and at Power-Fail Recovery

II Interconnect Space for
Dynamic Memory Configuration and
Diagnostics

•

Built-In-Self-Test (BIST) Diagnostics
On-Board with Both LED Indicators and
Software Access to Error Information

Byte Parity Error Detection

The iSBC MEM/320, 340 are cache"based memory boards that support the MULTIBUS II architecture. They
have 32-bit architecture throughout, supporting 8-, 16-, and 32-bit central processors. The iSBC MEM/3XX
(generally refers to this family of boards) memory boards are dual-ported, with access to the interfaces of both
the MULTIBUS II Parallel System Bus (PSB bus) and the iLBXTM II (Local Bus Extension).
In addition to the 32-bit memory transfer, the iSBC MEM/3XX high-speed cache control subsystem, standard
on these boards, improves performance by allowing zero wait state read access over the iLBX II at 8 MHz
when data requested is in the cache memory.

260071-1

-The iSSCI!> MEM/320, 340 is also manufactured under product code piS SCI!> MEM/320, 340 by Intel Puerto Rico, Inc.

2-9

Oct9ber 1989
Order Number: 280071-003

ISBC4l> MEM/320, 340 BOARDS

FUNCTIONAL DESCRIPTION
General
The ISBC MEMl320, 340 high·speed cache-based
memory boards are physically and electrically com·
patlble with the MULTIBUS II PSB bus standard and
the new iLBX " bus (Local Bus Extension) as out·
lined in the Intel MULTIBUS " specification. Figure 1
illustrates a typical multiprocessing MULTIBUS "
system configuraton.

Architecture
The four main subsystems of the iSBC MEM/3XX
boards are the cache controller subsystem, the
cache memory subsystem, the DRAM memory subsystem, and the interconnect space subsystem (see
Figure 2). The following sections describe these
subsystems and their capabilities in more detail.

reduces read access timers. The 8K Bytes of 45
nsec SRAM allows zero walt state read accesses
over the ILBX " bus when data requested is In the
cache memory (cache hit). A cache hit takes only
two iLBX " bus clocks (250 nsec at 8 MHz).
Each entry In the 8K Byte cache memory subsystem
consists of a data field of 32·bits and a tag field of up
to 9·bits (depending on board DRAM size). Each
byte in the main memory DRAM array directly maps
to one and only one entry on the cache array. This
direct mapped cache array along with tag labels en·
sure data integrity and accurate identification of
cache hits. The cache memory size and simple but
effective replacement algorithm is designed to opti·
mize both the probability of cache hits and the CPU
bus utilization. On any miss or write access, the con·
tents of one cache entry are updated to maintain
conSistency with the corresponding entry in the
DRAM memory array.

Dual Port DRAM Capabilities
Cache Memory Capabilities
The cache memory system is designed around the
32·bit architecture of the main memory system and

The MEM/320 and MEM/340 modules respectively
contain 2M Bytes and 4M Bytes of read/write memo
ory using 256K dynamic RAM components.

IITIIUS"

280071-2

FIgure 1. typical MULTIBUS e II System Configuration

CACHE
CONTROLLER
SUBSYSTEM

280071:-3

Figure 2.ISBce MEM/3XX Board Block Diagram
2-10

intJ

ISBC@ MEM/320, 340 BOARDS

The dual port capability of the iSBC MEM/3XX
boards allows 32-bit access from either the PSB bus
interface or the iLBX II bus interface (see Figure 1).
Due to the simple arbitration nature of the iLBX II
bus interface and the cache mernorysubsystem, the
iSBC MEM/3XX family allows optimal access to
20M Bytes of DRAM on the iLBX II bus.

1. EPROM Checksum:
This test performs a checksum test on its internal
EPROM to check operation of the 8751 microcontroller.
Cache Data Test:
The microcontroller performs a sliding ones test
on the cache memory in hit-only mode.
3. Cache Address Test:
This test verifies that the cache address path is
working properly.

System Memory Size
Using this series of memory boards the maximum
system memory capacity based on one CPU board
and 19 memory boards is 76M Bytes on the P~B
bus. The memory partitioning Is independent for the
PSB bus interface and the iLBX II bus interface.

4. Refresh Check:
This test performs RAM test on a small portion of
DRAM with an elapsed time between the write
operation and the verification of the data.
5. Dynamic RAM Address Test:
This test performs Address Rippled RAM test on
the board memory (MI~S ONLY operation mode).
6. DynamiC RAM Dat~ Test:
This test runs an AA-55 data pattern to check the
DRAM data path.
7. Parity Test:
Tllis test injects parity errors in the DRAM array
and then verifies that the board detects these
errors.

The start address can be on any 64K Byte boundary
on the PSB bus and any 64K B.yte boundary on the
iLBX II bus. Software config4res the start and ending
addresses through the interconnect space. No Jumpers are needed.

Interconnect Space Capabilities
The iSBC MEM/3XX board module has a set of interconnect registers which allow the system software to dynamically configure and test the sJa,tus of
the memory board, replacing hardwired jumper functions. This interconnect subsystem also provides
control and access to the Built-In-Self-Test (BIST)
features. During power-up reset, the iSBC
MEM/3XX board initializes the memory and cache,
sets all interconnect registers to their default values
and performs a self-test. Error information from both
Built-In-Self-Test (BIST) a[ld parity checking is indicated in front panel LEOs and recorded in interconnect space registers accessible to software.

These tests are described in detail in the User's
Manual, Section 9-23.

Memory Initialization and Reset
Memory is initialized automatically during power-up.
All bytes are set to 00.

Error Detection Using Byte Parity
Built-In-Self-Test (BIST)

Parity will detect all singl~ bit parity errors on a byte
parity basis and many muiltiple bit errors. LED 2 (labelled Parity) is used to indicate parity errors. LED 2
is turned on when a parity error is detected and
turned off when the parity status register within interconnect space is cleared. This same LED turns on
and off during power-up to verify operatoin of the
LED.

Self-test/diagnostics have been built into the heart
of th~ MULTIBUS II system. These confidence tests
and diagnostics improve reliability and reduce manufacturing and maintenance costs. LED 1 (lab~lIed
BIST) is used to indicate the status of the BUilt-In
Self Test. It is turned on when the BIST starts running and is turned off when the BrST completes successfully. The Built-In-Self-Test perforrned by the
on-board microcontroller at power-up or at software
command are:

Error information is recorded in interconnect space
so it is accessible to software for error reporting.

2-11

inter

iSBC® MEM/320, 340 BOARDS

SPECIFICATIONS

ENVIRONMENTAL REQUIREMENTS
Temperature: (inlet air) at 200 LFM airflow over
boards
Non-Operating: -40 to +70"C
Operating: 0 to + 55°C

Word Size Supported
8-, 16-,24-, and 32-bits

Humidity:

Memory Size
2 Megabytes (iSBCMEM/320) board
4 Megabytes (iSBC MEM/340) board

Non-operating: 95% RH @ 55°C
Operating: 90% RH @ 55°C

Physical Dimensions
The iSBC MEM/3XX boards meet all MULTIBUS II
mechanical specifications as presented in the ANSII
IEEE 1296 MULTIBUS II specification.

Access Times (All Densities)
MULTIBUS II Parallel System Bus-PSB (@
10 MHz)

Double High Eurocard Form Factor:

Read: 562 ns (avg.)
775 ns (max.)

Depth: 220 mm (8.6 in.)
Height: 233 mm '(9.2 in.)
Front Panel Width: 20 mm (0.784 in.)

Write: 662 ns (avg.)
775 ns (max.)

Weight:
iSBC MEM/320 board: 6720 gm (24 oz.)
iSBC MEM/340 board: 10080 gm (36 oz.)

NOTE:
Average access times assume 80% cache hit rates
ILBXTM II Bus-Local Bus Extension (at 8 MHz)

Reference Manuals

Read: 250 ns (min.)
275 ns (avg.)
375 ns (max.)

iSBC MEM/3XX Board Manual (# 146707)

Ordering Information

Write: 375 ns, (avg.)
375 ns '(max.)

Part Number
SBCMEM320

Base Address
SBCMEM340
PSB Bus-any 64K Bytes boundary
iLBX II Bus-any 64K Bytes boundary

Power Requirements
Voltage: 5V DC ± 5%
Product

Current

iSBC MEM/320
, Soard

3.5 A (typ)
6.0 A (max)

iSBC MEM/340
Board

4.1 A (typ)
6.7 A (max)

2-12

Description
2M Byte Cache Based
MULTIBUS II RAM Board
4M Byte Cache Based '
MULTIBUS II RAM Board

iSBC® MEM/601
MULTIBUS® II UNIVERSAL SITE
MEMORY EXPANSION BOARD
•

Supports EPROM, ROM, EEPROM,
SRAM, and NVRAM

•

Optional On-Board Support for Lithium
Battery Backup Memory Protect

•

Sixteen Sites Configured as Two Banks
of Eight 28-Pin JEDEC Sockets

•

Start Addresses for Each Bank
Independently Assignable Anywhere on
64K Byte Boundaries Within the 4G
Byte PSB Memory Address Space

MULTIBUS® II Software Interconnect
Support for Dynamic Memory
Configuration and Diagnositics

•

Fully Supports Either MULTIBUS II 32Bit Parallel System Bus (PSB) or 32-Bit
Local Bus Extension (iLBXTM II) Bus

•

Automatic Memory Initialization at
Power-Up

The iSBC® MEM/S01 MULTIBUS II Universal Site Memory Board is a member of Intel's line of product
offerings that utilize the advanced features of the MULTIBUS II system architecture. The iSBC MULTIBUS II
Universal Site Memory Board expands system memory capacity and interfaces across either the MULTIBUS II
Parallel System Bus (PSB) or the high speed Local Bus Extension bus (iLBX II).

280261-1

2-13

October 1989
. Order Number: 280261.001

iSBC@ MEM/601

types described in Table 1 and is configurable via an
arrangement of push-in jumpers dedicated to each
'of the four groupings of 4 sites. Devices of the same
density and speed must reside within each bank and
devices of the same type must reside within each
group.

FUNCTIONAL DESCRIPTION

General
The iSBC MEM/601 board contains two banks of
eight standard 28-pin 600 mil DIP sockets. Either 28or 24-pin devices may be inserted on the board. The
actual capacity of the board is determined by the
type and quantity of components installed by the
user. The iSBC MEM/601 board is completely compatible with four different types and densities of devices (see Table 1). In addition, the board can be
accessed by either the MULTIBUS II Parallel System
Bus (PSB) or Local Extension Bus (iLBX II).

Memory Address Decoding
The memory array is divided into two separate addressable banks. The addressing for each bank is
independently software-configurable through MULTIBUS II interconnect space and is on 64K byte
boundaries. Software must insure that the address
space of one bank does not overlap the address
space of the other bank otherwise memory errors
would result. '

Memory Array
The sixteen universal memory sites on the iSBC
MEM/601 board are partitioned into two banks of 8
sites each. Within each bank the 8 sites are further
partitioned into 2 groups of 4 sites each (see Figure
1). Each group of 4 sites can support the device

Built-In-Self-Test and Interconnect
Subsystem
Self test and diagnostics have been built into the
heart of the MULTIBUS II system. These confidence

CONfiGURATOR
GROUP 1

CONfiGURATOR
GROUP 2
GROUP 1

GROUP 2

28 PIN
SOCKET
1

28 PIN
SOCKET

GROUP 3

GROUP 4
CONF"IGURATOR
GROUP 4

CONF"IGURATOR
GROUP 3

280261-2

Figure 1.ISBC® MEM/601 Sixteen, 28-Pin Universal Site Memory Array
Table 1. Memory Devices Supported by the ISBC® MEM/601 Board
Type
EPROM
ROM
EEPROM
SRAM
Maximum Memory Capacity

2Kx8

4Kx8

8Kx8

16Kx8

32Kx8

64Kx8

2716

2732A

2764

27128

27256

27512

Yes

2817A

Yes

2864A

Yes

+5VOnly

TC5516

Yes

TC5565

Yes

TC55257

Yes

NMOS and CMOS

32KB

64KB

128 KB

256KB

512 KB

1 MB

2-14

inter

iSBC® MEM/601

tests and diagnostics improve reliability and reduce
manufacturing and maintenance costs. LED 1 (labeled BIST), is used to indicate the status of the built
in self test. It is turned on when the BISTs start running and is turned off when the BISTs have successfully executed. Error information from the BISTs is
recorded in the interconnect registers accessible to
software. The built in self tests are peformed by the
on-board microcontroller at power-up or on command.

off board power source or from the optional on
board lithium battery. The memory content of the
CMOS RAMs is protected during power-up and power-down by the protect signals from the PSB bus.

Parallel System Bus Interface
The PSB bus interface supports memory space and
interconnect space and provides the capability of 8-,
16-, 24-, and 32-bit transfers. The PSB interface can
be dynamically activated through the status register
of the interconnect space under software control or
can be jumper selectable. After a cold reset the PSB
is enabled and the Local Bus Extension (iLBX II) bus
is disabled.

The iSBC MEM/601 board interconnect subsystem
consists of an 8751 microcontroller for Built-In-SelfTest (BIST), program storage, status, control registers, and interconnect control logic. The interconnect subsystem receives requests to interconnect
space across either the PSB bus or the iLBX II bus
depending on which interface is enabled. The interconnect subsystem is used by the software to configure the hardware.

Local Bus Extension Interface
The iSBC MEM/601 board provides 8-,16-,24-, and
32-bit transfers across the Local Bus Extension
(iLBX II) interface. The iLBX II bus interface is enabled by the status register of the interconnect
space and can therefore be dynamically changed
through software. It is also jumper selectable. After a
cold reset, the iLBX II interface is disabled. The PSB
bus interface is always disabled when the iLBX II bus
is enabled.

Battery Backup
The iSBC MEM/601 board supports jumper selectable on-board or off board battery backup operation
for CMOS SRAMs. Memory protection for the two
memory banks can be supported with + 5V from an

BANK A I BANK B

I
I

MEMORY
AR7AY
I

SIXlEEN 28-PIN
UNIVERSAL SITES

280261-3

Figure 2_ iSBC® MEM/601 Block Diagram

2-15

intJ

ISBC® MEM/601

SPECIFICATIONS

ENVIRONMENTAL REQUIREMENTS

Word Size 8-, 16-, 24-, and 32-bits

Temperture: Inlet air at 200 LFM airflow over boards
Non-operating: -40·C to + 70·C
Operating:
O·C to + 55·C

Memory Size
Sockets are provided for up to sixteen JEDEC compatible 28-pin devices which can provide up to 1.0M
Byte of EPROM/ROM/SRAM memory.

Humidity:
Non-operating: 95% RH
Operating:
90% RH

Access Times

Physical Dimensions

Read Cycle Without
Replier Busy
Write Cycle Without
Replier Busy
Read/Write with
Agent Error

PSBBus

ILBXTM II Bus'

300ns

250 ns

300ns

250 ns

100ns

10ms

Double High Eurocard Form Factor
Depth:
220 mm (8.6 in.)
Height:
233 mm (9.2 in.)
Front Panel Width: 20 mm (0.784 in.)
Weight as shipped from factory: 543g (19 oz.)

Reference Manuals
#149149-iSBC MEM/601 Memory Board User's
Guide

"Access times across the iLBX II bus assumes an 8.0 MHz
bus clock. The actual formula is as follows:

55·C
55·C

The iSBC MEM/601 board meets all MULTIBUS II
mechanical specifications as presented in the MULTIBUS II specification (IEEE/ANSI1296).

NOTES:
Access times are calculated without device speed included. True access times across either bus must include device access time and must be in 100 ns increments for the
PSB bus. Above calculations assume 1 bus cycle. Refer to
the iSBC MEM/601 Memory Board User's Guide for exact
formula to determine access times for specific operating
configurations.

T = 2{C)

@
@

Manuals may be ordered from any Intel Sales Representative, Distributor Office, or from the Intel literature Department, 3065 Bowers Ave., Santa Clara,
CA., 95051.

D where: T is iLBXII Bus access time
C Is 1If, f = iLBX II Bus clock
speed
D is Device access time

Ordering Information
Power Requirements
Current with 2764A EPROMs installed

Part Number
SBCMEM601

+ 5V: 4.5A

Current with 2864A EEPROMs installed
5.5A

+ 5V:

At 3V and 300 rnA hours lithium battery rating, the
expected retention time for standard CMOS SRAM
memories will be approximately 24-36 hours.

2-16

Descrlpton
MULTIBUS II Universal Site
Memory Expansion Board

MULTIBUS® II I/O Products

MULTIBUS®II 1/0 PRODUCT LINES

expansion Modules

<.-----iS8X"'--rI-.------,)
...
IISIIX'" Mo

<.--___

Bu_8 _ _ _
MI....,Xr-

A SPECTRUM OF 110 FOR MULTIBUS®II DESIGNS
Intel's wide range of MULTIBUS"'I\ I/O products is designed to help you easily complete
your application. These boards include a variety of standard I/O products, such as
terminal controllers, wide area network controllers, Ethernet controllers, SCSI peripheral
controllers and Digital I/O boards. Intel also offers a choice of development methods for
designing custom I/O boards. Now you can design low-cost, non-intelligent I/O boards
based on the MULTIBUS \I Penpherallnterface (MPI) silicon, or you can quickly and
easily design high-performance, 386™ CPU-based I/O boards based on the Modular
Interface eXtension (MIX) architecture. These products are described on the following
pages.

CONTENTS

Introduction

• Wide Area Network
Controllers
• Ethernet Local Area Network
Controllers
• Peripheral Controllers
• Parallel 1/0

I/O Development Products
• MULTIBUS \I Silicon Products
• Modular Interface eXtension
(MIX) Architecture
• Modular Interface eXtension
(MIX) I/O Platform Family
• Firmware Development Package

MULriSUS"'II General
Information

Standard 110 Products
• Asynchronous Terminal
Controllers

Product and Literature
Guide

irneo-------------------September. 1989
Order Number 281009-001

Cllntel CorporatLon 1989

3-1

1/0 DEVELOPMENT PRODUCTS

MULTlBUS®1/ SILICON PRODUCTS
Inte!s MULTIBUS II bus interface device product
family has been created to aid the designer in
interfacing application modules to the MULTI BUS II
Parallel System Bus (PSB). The IEEE/ANSI1296
specification defines a set of synchronous state
machines which are clocked by a central bus clock.
Adherence to this type of specification is simple and
proveably correct. This architectural discipline has
resulted In unprecedented compatibility between
MULTIBUS II products from all vendors. Intel offers a
silicon implementation of the IEEE/ANSI1296 state
machines with the 82389 Message Passing
Copro?es~or (MPC) component to provide a high
capability Interface targetted for intelligent board
pro.ducts. The MULTIBUS II Peripheral Interface (MPI)
omits the block data transfer capabilities of the MPC
and is targeted for non-intelligent, lower cost board
products.
.
The MULTIBUS II Peripheral Interface (MPI) is a
MULTI BUS II bus interface device providing PSB
interface for non-intelligent I/O applications. The MPI
!s a replier in I/O and Interconnect space and can be
Implemented with a minimum of additional logic. The
MPI supports the standardized signalling methods of
the MULTIBUS II architecture with the ability to send
~nd receive unsolicited messages (without data) as
Interrupts. An on-board CPU or microcontroller (such
as an 8751) is not required for applications using the
MPI. Interconnect space may be implemented using
a single PAL or PROM.

Figure 1: Comparing MPI and MPC Capability

The 82389 Message Passing Coprocessor (MPC) is
the premier MULTI BUS II bus interface device for
intelligent applications. It provides a complete, full
function interface to the PSB, including arbitration,
dual. port memory recognition and the standardized
Signalling and data transfer methods of the
MULTIBUS II architecture. The MPC component
requires the support of an 8751-type microcontroller,
and a DMA device is recommended for high
performance data transfers. The MPC, in
combination with the iSBC CSM/002 module or
additional on-board logic, provides complete Central
Services Module support for use in a slot 0 system
location.
Solicited
Messages
Unsolicited
Messages
Bus
Arbltretlon
IIC Space
Support
Minimum
Support
Required
10 be
IEEE 1296
Compliant

MPI
Parity
Agent Error
Replier
State MIC
Drlversl
Buffers

MPC

MULTIBUS®II BUS INTERFACE SILICON PRODUCTS
Interconnect Space
The MPI component supports IEEE/ANSI1296
compliant interconnect space. Its registers are only
accessed via the Parallel System Bus. The MPI
includes the interface logic to support an external
local memory device or PAL to implement most of the
interconnect registers. Registers 34 through 38 are
internal to the MPI.
110 Space
The MPI component enables an I/O board to act as a
replier in I/O space (as seen in figure 2). Board
address space is programmed through interconnect
space which allows multiple MPI-based boards to be
used in a MULTIBUS II system with no jumpers. The
width of the local I/O data bus can be 8 or 16 bits.
Addresses and data for the local I/O is provided on a
multiplexed bus.
Message Space

MPI-MULTIBUS®II PERIPHERAL
INTERFACE
The MULTIBUS II Peripheral Interface, MPI, IS a
single chip, "replier only" Parallel System Bus
interface device. The MPI implements a IEEE/ANSI
1296 Replier State Machine, seen in Figure 2. All
error conditions are monitored and generated If
appropriate.

The MPI component enables an I/O board to send
and receive interrupt packets, either in standard or
Broadcast mode, without data. (Data transfer is
carried out in I/O space.) Up to eight local interrupts
may generate an interrupt packet onto the PSB; the
highest priority interrupt level is encoded into this
interrupt packet. The MPI entirely controls the access
arbitration procedure for the PSB bus and the
interrupt packet transfer. The MPI can receive
interrupt packets from the PSB and uses them to
, generate a local interrupt signal.

MPI FEATURES
• Replier in I/O Spac
- 2 KBytes address on each board
- 8/16 bus data width agents
• No application CPU required
• No support microcontroller required
• Supports up to 8 local interrupt sources
o Sends/Receives broadcast messages
• Sends/Receives unsolicited messages
(without data)
- Complete arbitration protocol
• Fair and High Priority modes are supported
• ANSI/IEEE 1296 compliant
• 124-pin plastic PGA package.

The MPI interface supports parity signals when
required and is capable of processing all error signals
present on the bus. '

MPI SPECIFICATIONS
Power Supply Voltage: 0 - 5 V
Operating Temperature: 0 - 70°C
Storage Temperature: - 65 to + 150°C
Vcc = 5.0 V + 10%

DESCRIPTION
The MPI component is a 16-bit integrated CMOS
interface component compliant with the IEEE/ANSI
1296 standard and is compatible with other board
products using the 82389 Message Passing
Coprocessor. It supports data transfer in I/O space,
as defined by the IEEE Specification. It is particularly
suited to the design of low cost, non-intelligent I/O
boards. Since the MPI component incorporates all
the interface logic, except for five high current buffer
drivers, it simplifies and accelerates I/O board design.
The local interface is designed to provide a simple
interface to I/O board components. The MPI also
includes configuration registers which are
programmed from the PSB to suit a variety of
applications.

SC2'=L

SC3'aL and
SC2'aH and
REPRDY=L and
AGENT STATUS ERROR=L

SC2'aH and
(SC3'=H or
REPRDYaH or
AGENT STATUS ERROFjaH)

Figure 2: State-Flow Diagram for Replying Agents, from IEEE/ANSI1296 Specification

MULTIBUS®II BUS INTERFACE SILICON PRODUCTS
• Processor Independent Interface to the Parallel
System Bus
• Supports co-existance of dual port and message
passing communication protocols
• Dual Buffer Input and Output DMA capabilities

MPC 82389 INTERFACES
The three primary interfaces to the MPC (PSB,
Interface Host, CPU Interface and Interconnect
Interface) all function asynchronously to one another.
This is accomplished through the use of internal
latches and FIFOs that allow references to occur
simultaneously on all interfaces. In addition to the
three primary interfaces, the MPC 'contains a DualPort interface which provides compatibility with
shared memory system implementations and
software.

82389-MULTIBUS®II-MESSAGE PASSING
COPROCESSOR
The 82389 MPC is a highly integrated VLSI CMOS
device that maximizes the performance of a
MULTIBUS II based multiprocessor system. The MPC
implements the full message passing protocol as well
as the functions (arbitration, transfer and exception
cycle protocols) of the PSB bus interface control as
defined in the IEEE/ANSI Standard 1296 .
. The 82389 MPC is designed to interface with an 32-,
16- or 8-bit processor. It provides support for
message passing, interconnect space, memory, and
I/O references on the PSB. In addition, the 82389
MPC component is designed to simplify
implementation of dual port memory functions for
those designs which will co-exist with the message
passing communications protocol.

MPC FEATURES
•
•
•
•

Single Chip Interface for the Parallel System Bus
1.5 u CMOS Technology
149-pin Ceramic PGA Package (15 x 15 Grid)
Optimized for Real-Time Response (Maximum 900
ns for 32-byte Interrupt Packet)

Figure 3: MPC Bus Interfaces

3-4

The PSB Interface
The PSB Interface is the synchronous,
communications pathway in a MULTIBUS II system.
The PSB is a full 32-bit interface to other boards in
the MULTIBUS II chassis. The PSB interface supports
PSB arbitration, data transfer and error handling.

MULTIBUS®II BUS INTERFACE SILICON PRODUCTS
The Host CPU Interlace
The Host CPU Interface is a set of addressable
registers and ports that is the private pathway for the
local microprocessor on the MULTI BUS II board. The
Host CPU interface connects a 32-, 16- or 8-bit
processor to the MPC. The Host CPU Interface
supports direct references to memory, I/O, and
interconnect address space on the PSB. The Host
CPU Interface also supports DMA operations. The
MULTIBUS II PSB and the MPC are defined to be
processor independent.
The Interconnect Intel1ace
The Interconnect Interface provides a path for added
board functionality that is independent from the host
CPU. The Interconnect Interface is an 8-bit
communication interface which requires the MPC to
be connected to a microcontroller or a simple state
machine. A microcontroller will perform tasks such as
board configuration at start-up and local diagnostics.
All interconnect bus signals are asynchronous to the
bus clock and to the local bus signals.
The Interconnect space of an agent is the only
required bus space by the IEEElANSI1296
specification and has a 512-byte register range.

The Dual Port Interface
The Dual Port interface supports shared memory
accesses between agents on the PSB. The MPC
contains programmable address recognizers and
PSB cycle control. In order to fully implement dualport memory, some additional dual-port memory
controller logic is required.

MAJOR MPC OPERATIONS
The MPC standardizes the signalling and data
transfer between multiple intelligent agents within a
MULTIBUS II system. The traditional address spaces
of memory and I/O were considered Inadequate to
accomplish this standardization task, so a new
address space, called message space, was added.
The movement of information in message space is
called message passing. The MPC supports two
types of messages: solicited and unsolicited.
Solicited messages are used to transfer large
amounts of data. Up to 16 MBytes (less 1 byte) of data
can be transferred in a single solicited message
transmission sequence. Solicited message transfers
require the receiving agent to explicitly allocate a
buffer. Data is packetized and reconstructed by the
MPC to optimize PSB utilitzation and maintain
deterministic performance. Buffer negotiation
between sending and receiving agents is handled
using unsolicited messages.
Unsolicited messages are short, fixed-length
messages that can arrive unexpectedly. Unsolicited
messages can be transmitted without explicit buffer
allocation and without the cooperation of sending and
receiving agents on the PSB. Unsolicited messages
are often referred to as intelligent or virtual interrrupts,
since they are used as a signaling mechanism
between boards, replacing traditional system (hardwired) interrupts and freeing the CPU from having to
poll for information. In addition to interrupt
generation, unsolicited messages allow for up to 28
bytes of user data.

MPC SpecHlcaUons
Operating Temperature (under Bias) ..1O°C to +85°C
Storage Temperature ..............65°C to + 150°C
Voltage on Any Pin .............. O.5V to Vec + O.5V
Power Dissipation .... '" ................... 2.5 W
D.C. and A.C. Specifications are available in the
82389, Message Passing Coprocessor Datasheet.
(See Ordering Information)

3-5

MIX ARCHITECTURE

Single Module

Module Stacking

One SIOI
(Baseboard plus one module)

Three SIOI8
(Baseboerd plus three modules)

MIX HIGH-PERFORMANCE ARCHITECTURE FOR BUILDING TAILORED AfULTIBUS®II
110 SOLUTIONS
Intels Modular Interface eXtension (MIX) architecture
provides a 32-bit asychronous bus technology
designed for high,performance on-board 110
expansion. It is optimized for the 386T11
microprocessor family and the MULTIBUS II system
architecture. The MIX bus is implemented using a ,
130-contact surface mount connector and supports
stacking of from one to three MIX 110 modules. The,
110 module interface to the MIX bus is open. with
specifications and documentation available from 'Intel
for the development and implementation of MIX 110
modules.

The MIX architecture lets system designers make
tradeoffs between the level of 110 performance. and
the number and types of 110 functions. USing MIX
modules. a range of 110 solutions can be
implemented: from a single-module single-slot high
performance 110 controller to a three-module threeslot 110 server subsystem. Now the system designer
can select the right combination of 110 and CPU
horsepower to effectively manage the system 110
requirements.
'

MIX ARCHITECTURE FEATURES
• Full compatibility with the MULTIBUS II (IEEElANSI
1296) Systems Architecture (MSA).
• Support for stacking of 1. 2. or 3 modules on the
MIX baseboard. A MIX baseboard with a single
MIX module fits into a single MULTIBUS II card
slot.
• MIX bus data width of 32. 16. or 8 bits.
• Partitioning of 110 SBC architecture into a CPU &
MULTIBUS II core and 110 module.

3·6

• Multimaster bus ownership for support of intelligent
or non-intelligent MIX 110 modules.
• Support for like or unlike MIX module stacking with
dynamic Built-in Self Test (BIST) and interconnect
capabilities.
• Complete documentation available for building MIX
110 modules.

MIX ARCHITECTURE FEATURES
MULTIBUS®II COMPATIBILITY

Data Paths

The MULTI BUS II Systems Architecture is optimized
for efficiently interconnecting multiple intelligent
microprocessor-based subsystems. The MULTI BUS II
architecture also accommodates many types of local
bus extensions for solving local communication
requirements within subsystems.

MIX supports 8, 16, and 32 bit physical data paths on
MIX modules. The MIX baseboard data path is 32
bits.

The MULTIBUS II Parallel System Bus (PSB) provides
the main communication backbone for the total
system, while other elements of the architecture solve
the system integration issues such as initialization,
diagnostics, and standardized subsystem to
subsystem signalling and data transfer.
The MIX architecture adds a subsystem bus
technology that provides a solution for high
performance 1/0 and brings the capability of a high
performance 1/0 server subsystem to the MULTIBUS
II architecture.

PHYSICAL DECOUPLING OF CPU
FROM 110
MIX uses a baseboard plus modules approach to
physically decouple the CPU technology of the
baseboard from the 1/0 technology of the module.
This decoupling has two benefits for 1/0 design. First,
it allows the CPU and 1/0 technology to evolve
independently so that new technology can be more
easily incorporated into system designs. Second, it
allows a baseboard to change personality by adding
or substituting 1/0 modules. This provides 1/0
flexibility while preserving the software investment.

CONNECTING CPU AND 110 VIA A HIGH
PERFORMANCE BUS INTERFACE
The MIX architecture provides the high performance
bus interface for coupling the CPU baseboard with
the 1/0 modules. Elements of the MIX architecture
and bus interface include:
Signal Set

The MIX bus consists of 130 signal, power, and
ground connections. There are two types of signals:
dedicated and bussed. Dedicated signals belong to
specific modules in the MIX stack, while bussed
signals are shared by all modules.
Address Capability
The MIX bus supports the full 4 gigabyte physical
addressing capability of the 386"" microprocessor
and other compatible microprocessors.

MIX Bus Transfers
The baseboard can perform memory, 1/0, and DMA
transfers on the MIX bus. The baseboard can also
perform a bus vectored interrupt transfer cycle. Bus
master modules can perform memory transfers with
the baseboard memory.
Arbitration
The MIX bus uses a simple round robin arbitration
scheme between the baseboard and master modules
to insure that all modules and the baseboard have
guaranteed access times to shared baseboard
memory and have a guaranteed percentage of the
shared memory bandwidth.
Interrupts
Each MIX module has one dedicated interrupt line.
Each module also has an option line that can be used
as an interrupt line.
DMA
The MIX bus supports DMA transfers bet~een
modules and the baseboard memory. Both singlecycle (fly-by) and two-cycle DMA transfers are
supported.
Configuration Support
MIX configuration support has been designed to be
compatible with the MULTI BUS II interconnect space
architecture. MIX modules are viewed as baseboard
functions by agents on the parallel system bus. The
baseboard microcontroller reads the interconnect
information stored in the EEPROM of each module
present in the MIX stack to build the function record
in baseboard interconnect space.
Built-in Self Test (BIST) Support
MIX provides the capability for BIST code resident in
module EPROM to be downloaded and executed as
an extension of the baseboard BIST.

OPEN INTERFACE FOR 110 MODULE
DEVELOPMENT
MIX provides an excellent platform for building
MULTIBUS 111/0 solutions. A complete set of
manuals, design specifications and design examples
for building MIX 110 modules is available from Intel.

3-7

MIX BUS INTERFACE SPECIFICATIONS
General
Bus Type:
Theoretical Bandwidth:
Typical Bandwidth:
Bus Overhead:
Interrupt Sources:
Bus Vector Support:
Arbitration Scheme:
Module Maximum:
Length of Bus Hold:
Flag Byte Support:

Data Path

Asynchronous
22 MBytels
10 MBytels
7% Xchange/Refresh
Any Module
Yes
Fairness (Rd-Robin)
3 (master or slave)
8 microsec (typical)
Yes

8, 16, and 32 bit
MIX Connector:
Connector Type:
Connector Pads:
MIX Expansion Module:
Module Height:
Module Depth:
Module Area:
Max Configuration:

Lines
130 total signal, power and ground lines:
Number Functional Group
37
Address
32
Data
7
Transfer Control
6
Arbitration
3
Interrupt
6
DMA
3
Option
7
Configuration
9
+5 VDC
13
GND
2
+12 VDC
2
-12 VDC
3
Reserved

Surface Mount
130

8.9 inches
3.75 inches
33 square inches
1 Baseboard
3 Modules

MIX Bus Power Limits
Voltage
(VDC)

+ 5 ( + 5%, - 2%)
+12 (+5%,-5%)
-12 (+5%,-5%)
Module Power Limits
Nominal
Voltage
(VDC)

+ 5
+12
-12
Thermal Limit (all sources):
20 Watts max per module

Baseboard Address Range
Memory 4 Gigabytes
1/0
64 Kilobytes
Module Address Range
Memory 256 Megabytes
1/0
1 Kilobyte

3-8

Total
Current
(Amps)
9.0
1.5
1.5
Max Current
per Module

(Amps)
3.0
0.5
0.5

MIX 1/0 PLATFORM FAMILY

A 386™ CPU-BASED CORE FOR BUILDING INTELLIGENT MULTIBUS®II
110 SOLUTIONS
The Intel Modular Interface eXtension (MIX) I/O
Platform Family provides the 386" microprocessor
core, hardware development modules, and
documentation needed to build high performance
custom 1/0 solutions for MULTIBUS II systems
The MIX 386/020 Baseboard combines a 386"
microprocessor, Advanced Direct Memory Access
(ADMA) controller, and Message Passing

Coprocessor (MPC) to provide a significant amount of
silicon muscle for handling I/O processing. In
addition, with 1 megabyte of on-board DRAM and up
to 16 megabytes of DRAM expansion, the baseboard
provides enough memory to accommodate on-board
execution of large amounts of I/O software. Add to
that the 1/0 expansion capabilities of the MIX
Interface and you have a versatile, high-performance
engine for handling 1/0 processing.

MIX 3861020 BASEBOARD FEATURES
• 386'· microprocessor operating at 20 MHz.
• 1 megabyte of on-board fast page mode DRAM
with panty checking.
• Memory expansion up to an additional 16
megabytes of fast page mode DRAM with parity
checking.
• 82258 ADMA for handling data transfers between
the baseboard DRAM and the MPC and also
between the baseboard DRAM and the MIX
modules. Two cycle, fly-by, and burst mode
transfers are supported.

• Full 32-bit MULTIBUS II Parallel System Bus
interface provided by the 82389 Message Passing
Coprocessor (MPC)
• MULTI BUS II systems architecture compatible
firmware Including Built-In Self-Test' (BIST) code for
the baseboard plus the capability to download and
execute BIST code for the attached MIX modules.
• MIX bus interface capable of supporting one, two
or three attached MIX 1/0 modules.

3-9

MIX 386/020 BASEBOARD FEATURES
386TH MICROPROCESSOR CORE

ADMA FOR FAST MEMORY TRANSFERS

The MIX 386/020 Baseboard obtains its I/O
processing power from a 386'" microprocessor
operating at 20 MHz. All the programming features of
the 386'" microprQcessor are supported.

The MIX 386/020 Baseboard uses the 82258 ADMA
operating lilt 8 MHz, DMA Address Generator (DAG)
gate array for 32-bit, 4 gigabyte addressing, and fast
page mode DRAM control logic to handle high speed
data transfers between baseboard DRAM and both
the MPC and MIX modules.

The Protected Virtual Address Mode (PVAM) of the
386'" microprocessor provides the MIX 386/020
Baseboard with a full 4 gigabytes of addressability.
The top gigabyte is used for baseboard EPROM and
MIX Module memory access. The lower 3 gigabytes
are divided between baseboard DRAM and Parallel
System Bus access. PVAM operation also provides
support for the 386™ microprocessor protection,
virtual memory and paging mechanisms.
In addition, the 386'" microprocesspr has a self-test
capability which is utilized in the board's power up
BIST testing. This function can be disabled via a
.
board jumper option.

The 82258 ADMA provides four independent
channels for DMA service; two channels are used to
service the MIX stack and two are used to service the
Message Passing Coprocessor (MPC). Three transfer
modes are supported: burst, single-cycle (fly-by), and
two cycle. To the MIX bus, burst mode transfers look
like single cycle transfers. Burst mode transfers
between the baseboard DRAM and the MPC or MIX
modules have a maximum transfer rate of 14.2
megabytes per second.

MULTIBUS®II SYSTEMS ARCHITECTURE
SUPPORT

FROM 1 TO 17 MEGABYTES OF MEMORY
The DRAM block of the baseboard consists of an
asynchronous fast page mode DRAM controller,
address multiplexor, data transceivers with parity
detection and generation, 1 megabyte of baseboard
DRAM, and DRAM expansion using the MMxx
interface. The MIX 386/020 is designed to accept one
or two MMxx DRAM modules. A total of 17
megabytes of DRAM memory is obtained with the
installation of two iSBC MM08FP memory modules.
Baseboard DRAM (both on-board and on MMxx
modules) is directly accessible to bus masters on the
MIX bus.
Byte parity protection is used for DRAM error
checking on the board. The transceivers generate
parity for memory write cycles and check parity for
memory read cycles.
The CPU block of the baseboard requires fast page
mode DRAMS, which provide zero wait state
performance for code prefetching by the 386'"
microprocessor, and one walt state performance for
all other DRAM accesses.

3-10

The MIX 386/020 Baseboard utilizes the 82389
Message Passing Coprocessor (MP.C) to provide a
full 32 bit interface to the MULTI BUS II Parallel
System Bus. Firmware is also provided that contains
baseboard Built-In Self Tests (BIST) and Initialization
and Diagnostics eXecutive (IDX) code. Also included
is the capability to download BIST code from MIX
module EPROM and execute the code to test the
modules in the MIX stack.

A POWERFUL ENGINE FOR
I/O PROCESSING
The MIX 386/020 supports a stack of 1,2 or 3 MIX
I/O modules. The MIX bus supports 32, 16 and 8 bit
data transfers and allows MIX modules to be either
masters or slaves on the MIX bus.
A custom gate array device on the baseboard
controls the baseboard interface to the MIX bus and
implements the MIX bus arbitration logic. The gate
array implements the standard MIX round-robin
arbitration algorithm which provides guaranteed
access to the MIX bus by the baseboard and module
bus masters. The capability to modify certain
arbitration parameters is also provided.

MIX 386/020 BASEBOARD FEATURES

MIX Bus

EPROM

MIX
Interface

ADMA

Figure 4: Block Diagram of MIX 386/020 Baseboard

MIX 3861020 BASEBOARD SPECIFICATIONS
Clock Rates
386"'DX Microprocessor 20 MHz
82258 ADMA 10 MHz
8751 Microcontroller 12 MHz
82C54 Timer (Programmable)

Device Drivers
Check the latest release of the following operating
systems for details:
iRMX II Operating System
UNIX' System V/386 Operating System

EPROM Memory
Two 32-pin Sites

Physical Characteristics
Standard MULTIBUS II board.

DRAM Memory

Power Requirements
Maximum values are at nominal voltage plus 5% and
at an ambient temperature of 0 degrees C.
Power
Nominal
Current
Voltage
(amps)
(watts)
(VDC)
Max
Max
31.5
+ 5
6.0
+12
0.0
0.0
-12
QO
0.0

1M byte installed on the baseboard.
Memory may be increased by installing up to two
iSBC MMOXFP Memory Expansion Modules, up to a
total of 17 MB. Separate versions are orderable with 1,
2 or 5M bytes already installed.

Interrupt capabilities
14 programmable interrupts
Interfaces
• P1, Full PSB.
• P2, power only.
• MMxx local memory expansion.
• MIX

Note: Power requirements do not include installed MIX
110 modules.

3-11

MIX 1/0 PLATFORM FAMILY

A KIT FOR DEVELOPING MIX I/O MODULES
A requirement for many MULTIBUS " designs is the
incorporation of special 110. This is 110 that may be
unique to the application or require an I/O controller
not readily available in the market. To date, such a
requirement typically would have necessitated the
non-trivial task of designing a dedicated MULTIBUS"
1/0 controller. With the Modular Interface eXtension
(MIX) interface and the MIX Module Developme.nt Kit,
the task of developing a MULTIBUS " 110 solution is
simplified.

The MIX bus is a straight-forward, well documented
interface for developing MIX 1/0 modules. In addition,
the MIX Module Development Kit provides all the
hardware, documentation and optional consulting
support needed to easily develop your own MIX 1/0
module that stacks on the MIX baseboard. This
combination greatly simplifies the task of developing
your complete 1/0 solution for MULTIBUS " systems.

MIX MODULE DEVELOPMENT KIT FEATURES
• MIX 386/020 Baseboard used as both the
development vehicle and the platform for the final
production module
• A set of MIX development modules to facilitate the
MIX module development process, including a test
module, breadboard module, and debug module.

3·12

• Complete documentation set providing all the
information needed to develop a MIX module
• Optional Intel Field Systems Engineer consulting to
help you better focus your development team and
save development time.

MIX 1/0 PLATFORM FAMILY
MIX MODULE DEVELOPMENT KIT CONTENTS:
MIX 386/020 Baseboard
Developing custom 1/0 modules using the MIX
386/020 baseboard, provides an implementation
method that offers both quick tlme-to-market and
reduced risk. Time-to-market is faster because two
thirds of the total I/O controller design is already
provided by the baseboard. Risk is reduced,
because with the MIX 386/020 baseboard, Intel has
already solved the problems of designing the CPU
core and providing the interface to the MULTI BUS II
Parallel System Bus.

The MIX Module Development Kit Makes
MULTIBUS®III/O Development Easy
The elements of the MIX Module Development Kit
help to faCilitate your engineering teams development
process.
To develop a MIX module, your engineers would start
out as usual with the hardware team designing the
hardware logic on paper or on a CAD system and the
software team developing the preliminary design for
the module firmware and application software. Once
the preliminary hardware design is completed, the
MIX MOD2 Breadboard Module would be used to
build a prototype wire-wrap version of the design.
Since the Breadboard Module mounts on the
baseboard MIX connector, module interaction with
the baseboard can be easily checked out.

Documentation Package
A complete set of manuals, specifications and design
examples for building a MIX module. This
documentation package provides all the information
you need to successfully develop a MIX module.
Optional Field Systems Engineer Consulting
Intel Systems Engineers have the experience and
engineering expertise that can save you valuable
development time. Consulting support for MIX
module hardware, software, or firmware development
is available as an optional component of the Module
Development Kit.

With a wire-wrap version of the module, the software
team can use the MIX MOD1 Test Module to test out
the early application software interaction with the
baseboard and the wire-wrap design. Because of the
stacking capability of MIX, the Test Module and
Breadboard Module can both be mounted to the
baseboard in a stacked configuration.

MIX Development Modules
All the MIX development modules are designed to
stack on top of the MIX baseboard or another MIX
module.

Once the breadboard design has been checked out,
the engineering team would build the production
version of the module. Using the MIX MOD3 Debug
Module, the final module can be mounted on the
baseboard with its components side up for easy
probe access and hardware debug.

• MIX MOD1 Test Module
Used for testing of MIX module hardware and
software designs. The test module contains a serial
interface and an iSBX'" connector for communicating
with the MIX baseboard.

Finally, using the Test Module and the Debug Module
in a stacked configuration, the engineering team can
debug both the final hardware and software to
complete the design.

• MIX MOD2 Breadboard Module
Used for wire-wrapping and building a prototype
module design. The breadboard module provides three
separate wire-wrap areas, each surrounded by power
and ground connections. In addition, stake pins are
provided which give access to the signals from the
MIX interface.
• MIX MOD3 Debug Module
Used to mount a MIX module with its component side
up (that is, flipped over from its normal mounting
orientation). This allows access to the module'S
components for easy probe connection and debug.

3-13

FIRMWARE DEVELOPMENT PACKAGE
FIRMWARE DEVELOPMENT PACKAGE
FEATURES:
• Source Code and Binary files for:
Master Test Handler, Console Controller, Bootstrap
Loader, Initialization & Diagnostic Executive, and
Core Function Set.
• Complete Documentation: Overview manual,
Specifications, BIST Writer's Guide
• DOS generation environment
• Available in C language
• Distributed via DOS diskettes, including make files
compatible with PolyMake*
• Designed to facilitate customization
'PolyMake is a trademark of Palytran Corp.

FIRMWARE DEVELOPMENT PACKAGE
The MULTIBUS II Firmware Development Package
(FOP) makes the benefits of MSA (MULTIBUS II
Systems Architecture) available at a fraction of the .
cost of developing a proprietary implementation
uSing the MULTIBUS II specifications. FOP enables
developers to fully realize a multiple processor design
by providing a standard solution for system
initialization and bootload. In addition,. a standard
Built In Self Test (BIST) architecture is provided to
offer several levels of diagnostic compatibility.
Developing MSA via FOP will reduce implementation
time and simplify adherence to the MSA specification.

3-14

FIRMWARE DEVELOPMENT PACKAGE FEATURES
OVERVIEW MANUAL

AVAILABLE IN C LANGUAGE

The FOP Overview Manual details the architecture of
MSA firmware, explaining the rationale for module
partitioning as well as the capabilities and limitations
of the various modules.

Recognizing the need for portability and the
popularity of C, the FOP software is available in the C
language.

SOURCE FILES
FOP is a source product. All files necessary to
duplicate the MSA firmware functions for diagnostics,
initialization, and booting are included in the
package.

BINARY FILES
Binary files of each module are included and may
make the generation of unmodified modules
unnecessary. These object modules also serve as
references in validating the development
environment.

DISTRIBUTED VIA DOS DISKETTES
Covering the most popular development
environment, the distribution media affords easy
portability.

INCLUDES MAKE FILES FOR GENERATION
FOP includes a file that may be used with the
PolyMake* utility to greatly ease the regeneration
process. Only files having modifications are
recompiled, which eases the
generation process and significantly reduces the time
required.

BUILT IN SELF TEST (8IST) EXAMPLES

DESIGNED TO FACILITATE
CUSTOMIZATION

Examples of actual BIST code commonly used on
Intel MULTIBUS II hardware are included for
reference.

FOP IS an open product, which IS partitioned and
organized to faCilitate any changes and extensions
necessary to support your hardware.

BIST WRITER'S GUIDE

HARDWARE REQUIREMENTS FOR
DEVELOPMENT

A BIST Writer's Guide is included to aid the process of
learning the BIST interfaces and to show the typical
organization of BIST code on Intel hardware. USing
the guide, the first time SIST writer will quickly come
up to speed. Master Test Handler (MTH), Local Test
Handler (LTH), and power-up Test Handler (PTH)
interfaces to the Initialization and Diagnostics
Executive (lOX) are covered.

SPECIFICATIONS PACKAGE
Detailed external specifications for each module are
included. These documents are suitable for
implementation purposes and were actually used in
the development of base FOP firmware.

Any open system that supports MSA, e.g., the Intel
System 520, will provide an adequate hardware
environment for firmware validation.

PACKAGE CONTENTS
The product package contains source and object for
the modules called out above on DOS diskette,
external specifications, and an overview manual.
• PolyMake

3-15

a trademark of Polytron Corp

ASYNCHRONOUS TERMINAL CONTROLLERS

FAMILY OF MULTIBUS®II TERMINAL CONTROLLERS
Asynchronous Terminal Controllers must address
such application requirements as terminal access,
remote modem access and computer to computer
communication while meeting price and performance
criteria. The Intel MULTIBUS II terminal controller
family addresses these application needs with three
boards: iSBC MP1/450, iSBC 186/450 and MIX
386/450. These boards are application compatible,
offering a range of price/performance options. The
iSBC MPI/450 is a non-intelligent I/O board that
provides asynchronous serial I/O port extensions to a
host CPU board. The iSBC 186/450 is an intelligent
dedicated terminal controller that efficiently performs
terminal functions within the system. The MIX
386/450 is a high performance terminal controller,
utilizing the power of 386™ CPU performance and the
flexibility of Modular Interface eXtension (MIX)
stacking.

All three boards have been designed stressing
compatibility across the product line. In respect to
hardware, all physical connections, ego cabling and
connectors, are interchangeable between the boards.
The result is that the three boards follow the same
front panel design with connectors, each clearly
marked with the individual product name. The use of
common components result in protocol compatibility:
This compatibility is extended into the software
structure as well. Standard software support for all
three boards maintains a consistent application
interface. By adhering to these hardware and
software standards, the boards achieve a high
degree of interoperability.

STANDARD TERMINAL CONTROLLER FEATURES
• Full duplex asynchronous transmission using the
82510 UART
• 12 ports per board, RS232C compatible
• 8 signal support, RJ45 (Phone Jack Style) shielded
connectors

3-16

• Performance ranging from 110 baud to 19.2k baud
• Asynchronous Terminal Control Software (ATCS) for
interrupt processing, character handling and
modem support

ASYNCHRONOUS TERMINAL CONTROLLERS
MULTI· TERMINAL ACCESS

MODEM SUPPORT

Twelve serial I/O ports are provided by each board.
Each port IS based on the 82510 USART component
and supports full duplex asynchronous transmissions
An on-chip baud rate generator allows for
independent baud rates on each channel For
applications requiring more than 12 ports, the number
of ports can be expanded in three ways by adding
more MPI boards (ISBC MPI/450), by adding more
intelligent boards (ISBC 186/450), or by mounting
additional MIX450 modules onto the MIX baseboard.
The customer may choose their configuration based
on price and performance requirements of their
application.

Each channel proVides for 8 Signal support. Software
handshaking (DTR,RTS and CTS), Carner Detect
(DCD), Ring Indicator (RI), Data Relay (RXD and
TXD) and Signal Ground (SG) are supported. ThiS
support allows for access to remote dial up modems
and computer to computer communications.

CONSISTENT APPLICATION INTERFACE
Asynchronous Terminal Control Software (ATCS)
proVides a standard application Interface for all Intel
Terminal Controllers ATCS optimizes the interrupt
processing and character handling on an Intelligent
terminal controller board, offloading thiS task from the
application CPU. ATCS supports full duplex and
prOVides such features as support for multiple hosts,
dynamiC line SWitching, and modem support. ATCS
achieves these features and high performance by
prOViding Input and output buffers of 2K per line
(port). These buffers Increase senal data throughput
on output and allow Input bursts to be absorbed.
Dependent on the CPU, thiS capability can result In
Simultaneous Input and output up to 19.2k baud
rates. ATCS code IS designed to support up to 36
channels per server and multiple ATCS servers may
reSide In the system

EASE OF CABLING
Intel's Terminal Controllers utilize the RJ-4S "phone
jack" style connector, which provides shielding and
lock In mating. IndiVidual connectors are directly
plugged Into the front panel mount, hence a break
out box is not reqUired. Changing terminal
configurations is qUick and easy with thiS versatile
connection and the identical front panel mounts on
the boards. Cables are available through commercial
vendors in both shielded and unshielded
speCifications. Intel recommends shielded cables for
application use.

I
Application
CPU

I
~

MIX 450
MIX 450
MIX 386/450

ATCS

r,SBC'" 186/450
,SBC'" MPI/450

ATCS Server

Driver

ATCS Server

1/0

Space

1/0

Space

I
I

t
+ MULTIBUS'" PSB +
I\~---------,';
,
II

Figure 5: Terminal Controller Configuration Example.

3-17

ASYNCHRONOUS TERMINAL CONTROLLERS

iSBC®MPI1450 TERMINAL CONTROLLER

EXTENSION OF APPLICATION CPU

The iSBC MPI/450 is a non-intelligent 12 channel, RS
232-C compatible, asynchronous terminal controller.
The iSBC MPI/450 utilizes the MULTIBUS II
Peripheral Interface (MPI) component to add
additional 1/0 capability to an application CPU.

The iSBC MPI/450 provides 12 offboard
asynchronous channels to the application CPU,
allowing low cost ports to be easily added to the
system. The application CPU accesses the MPI ports
via the PSB 1/0 space, therefore any intelligent board
may host the iSBC MP1/450. The number of MPI
boards that can be supported is dependent upon the
host CPU bandwidth and application requirements.

iSBC®MPI1450 FEATURES

MPI FEATURES

• Extension of application CPU by providing
offboard asynchronous ports using the 82510
UART
• Slave MULTIBUS II Parallel System Interface
provided by the MULTIBUS II Peripheral Interface
(MPI)
• 12 ports per board, RS232C compatible
• 8 signal support, RJ45 (Phone Jack Style) shielded
connectors
• Performance dependent upon application CPU
bandwidth

The MPI component provides the iSBC MPI/450 with
the capability to generate unsolicited messages
without data. This feature allows the host CPU boards
to interact with the iSBC MPI/450 when prompted by
a message rather than requiring continually polling.
An interrupt register is provided for servicing the
82510 USARTs, whether a polling or message
technique is used.

3-18

ASYNCHRONOUS TERMINAL CONTROLLERS
iSBC®MPI/450 CONTROLLER SPECIFICATIONS
Interfaces
P1
Senal

Physical Characteristics
Standard MULTIBUS" board

Slave PSB
12 channels, RS232C, 8-pin
RJ-45 connectors, 82510
Controller

Power Requirements
(Excluding user-installed memory devices)
Nominal
Voltage
(VDC)

Device Drivers
Check the latest release of the following operating
systems for details:
iRMX " Operating System
UNIX' System V/386 Operating System

Current
(amps)

Power
(watts)

Max
1.55
.15
.15

Max

+ 5
+12
-12

7.75

1.8
1.8

12 SERIAL CHANNELS

RS232C
Interface

• • • • • •

RS232C
Interface

_li
Serial
Controller

•

Se"al
Controller

• •

111
I

il"-

t t
Interrupt
Control
"'Ii

11"-

..
,

II'"

MPI
Interface

...

"'Ii

II'"

I
A

MULTIBUS· 11 PSB

Figure 6: Block Diagram of iSBC"'MPI/450 Terminal Controller

3-19

A S V N C H RON 0 U S T E R'M I N ALe 0 N T R 0 L L E R S

iSBC®1861450 TERMINAL CONTROLLER

PERFORMANCE

The iSBC 186/450 is a high performance intelligent
terminal controller. The 80C186 CPU, 512K RAM and
ATCS served software allow this board to offload the
terminal 1/0 processing from the MULTIBUS II
application CPUs.

The performance for the 12 channels of the iSBC
186/450 with the ATCS software can be measured at
19.2k baud sustained output, and 19.2k baud input in
2k byte bursts for all channels in a full duplex mode.
If additional channels are required, they may be
added by introducing additional iSBC 1861450'8 as
additional standalone terminal controllers or by
adding additlonallSBC MPI/450 boards into the
system and utilizing the iSBC 186/450 as a server.

iSBC®1861450 FEATURES
• 80C186-based microprocessor operating at 12.5
MHz.
• 512K RAM, 128K or 256K EPROM
• Full MULTIBUS II Parallel System Bus interface
provided by the Message Passing Coprocessor
(MPC)
• 12 ports, RS232C compatible
• 8 signal support. RJ45 (Phone Jack Style) shielded
connectors
• Asynchronous Terminal Control Software (ATCS) for
interrupt processing, character handling and
modem support
• Multiple host support including dynamic line
switching
• Resident firmware to support Built-In-Self-Tests
(BIST), host-to-controller software download

TERMINAL CONTROLLER SUPPORT
The iSBC 186/450 takes the role of dedicated terminal
controller In the system by offloadlng the application
CPU of the task of handling terminal interrupts and
character processing. This controller can also be the
server for the non-intelligent iSBC MPI1450 boards,
using the ATCS software resident on the ISBC
186/450 to dnve the MPI-based 1/0 ports

SUPPORT FOR MULTIPLE HOSTS
The ATCS software has the ability to service multiple
hosts. The same terminal may be connected to
multiple clients and dynamic line switching is
supported by the ATCS software.

FIRMWARE
The iSBC 186/450 contains two 32 pin EPROM sites
with firmware that includes Built-In-Self-Tests (BISTS)
and host-to-controller download code for soft-loading
the ATCS software onto the board.

ASYNCHRONOUS TERMINAL CONTROLLERS
12 seRIAL CHANNeLS

RS232C
Interface

• • • • • • •

RS232C
Interface

Serial
Controller

• • • • • • •

Serial
Controller

2JeDeC
Sockets
ePROM

800186

MULTIBU~

512Kbytes
DRAM

MULTIBUS~

PSB
Interlace

11 PSB

Figure 7: Block Diagram for iSBC® 186/450 Terminal Controller

iSBC®1861450 CONTROLLER SPECIFICATIONS
Clock Rate
80C186 Microprocessor

12.5 MHz

EPROM Memory
Two 32-pin sites.
Supports either 128K bytes or 256K bytes

DRAM Memory
512K bytes installed on the board
Interrupt Capabilities
5 levels with 5 on-board sources
Interfaces
P1
Serial

Full PSB
12 channels, RS232C, 8-pin RJ-45
connectors, 82510 Controller

Device Drivers
Check the latest release of the following operating
systems for details:
iRMX II Operating System
UNIX' System V/386 Operating System

Physical Characteristics
Standard MULTIBUS II board
Power Requirements
(Excluding user-installed memory devices)
Nominal
Current
Power
Voltage
(amps)
(watts)
(VOC)
Max
Max
20
+ 5
4
3.6
+ 12
.3
-12
.3
3.6

ASYNCHRONOUS TERMINAL CONTROLLERS

MIX 450 TERMINAL CONTROLLER

SUPPORT FOR MULTIPLE HOSTS

The MIX 450 terminal module, when combined with
the 386T• CPU-based baseboard, provides high
performance terminal server capability for MULTI BUS
" systems. The MIX 450 module, as a single module
on the MIX baseboard, is a powerful 12 port terminal
I/O controller. The module can also be stacked three
high to expand the terminal support to 36 ports.
Stacking the MIX 450 with other MIX modules allows
the system designer to build to a multi-function I/O
server with terminal capabilities.

The ATCS software has the ability to service multiple
hosts. The same terminal may be connected to
multiple clier;1ts. Dynamic line switching is also
supported.

MIX 450 FEATURES
• 12 ports per board, RS232C compatible
• 8 signal support, RJ45 (Phone Jack Style) shielded
connectors
- • Asynchronous Terminal Control Software (ATCS) for
interrupt processing, character handling and
modem support
• Multiple host support including dynamic line
. switching
• Resident firmware to support Built-In-Self-Tesis
(BIST)

PERFORMANCE
The MIX 386/450 supplies the highest performance
of the terminal controllers offered by Intel. The MIX
386/450 can support 12 channels in fully sustained,
simultaneous input and output transmission at 19.2k
baud. Two additional modules can be added to the
MIX stack for up to 36 channels.

FIRMWARE
The MIX 450 module contains two 32 pin EPROM
sites with firmware that includes Built-In Self Tests
(BISTs). Upon power-up, the MIX baseboard copies
the MIX 450 BIST code up from the module to the
baseboard, where it is executed during initialization.
The MIX baseboard firmware provides the capability
of downloading the ATCS software.

MIX ARCHITECTURE
Intel's Modular Interface eXtension (MIX) architecture
provides a high-performance terminal controller with
built-.in high performance, on-board I/O expansion. It
is optimized for the i386(tm) microprocessor family
and the MULTIBUS" System Architecture. The MIX
bus allows for easy expansion of terminal support by
stacking one to three additional MIX I/O modules.
The I/O module interface to the MIX bus is open, with
specifications and documentation available from Intel.

3-22

ASYNCHRONOUS TERMINAL CONTROLLERS

to.
110 Control

...
MIX Data

"
~c
c

8
!S

..
,.

to.

MIX Address

110 Data

MIX 450
Module
Control
Block

Firmware
Block

MIX
Interface
Block

h.
MIX Control
~

110 Address

r:,

Timer
Block

~
A

Serial
Block

IV"""

Figure 8: MIX 450 Terminal Controller Module Block Diagram

MIX 450 SPfCIFICATIONSt
tFor Baseboard specifications, refer to the section on
the MIX 3861020 Baseboard

EPROM Memory
Two 32-pin JEDEC sites:

Device Drivers
Check the latest release of the following operating
systems for details.
iRMX II Operating System
UNIX' System V/386 Operating System

EEPROM
128 bytes installed on the module

Physical Characteristics
Standard MIX Module

Interlaces
Serial

Power Requirements
Current
Nominal
Voltage
(amps)
(VOC)
Max
3.0
+5
0.02
+12
0.02
-12

Clock Rates
82C54 Programmable Interval Timer 1.15 MHz

MIX

12 channels, RS232C, 8-pin RJ45
connector, 82510 Controller
Bus slave

Power
(watts)
Max
15.0
0.24
0.24

'1 MULTIBUS®II WIDE AREA NETWORK CONTROLLERS

A CHOICE OF HIGH PERFORMANCE SYNCHRONOUS CONTROLLERS.
Intel provides two synchronous board solutions
targeted towards Wide Area Network Applications.
Both boards provide the hardware platforms that
support commercial Wide Area Network protocols.
The two boards provide price and performance
options that can be tailored to individual application
needs.
The iSBC 186/410 is a standalone communications
controller. Within a MULTIBUS II system, the iSBC
186/410 can optimize overall performance by
assuming control of the Wide Area Network
administration, reducing the primary system CPU
overhead.

For applications requiring high speed synchronous
control and mainframe communication, the MIX
386/420 provides an optimal solution. The MIX
386/420 combines the intelligence and performance
of the MIX 386 Baseboard with the focused
synchronous control of the MIX 420 module. The
Modular Interface eXtension (MIX) Architecture allows
the user,to stack up to three modules on the
baseboard. This feature can be used to expand up to
six channels of high speed synchronous control or to
add other 1/0 capabilities.

WIDE AREA NETWORK CONTROLLER FEATURES
• On board Built-In-Self-Test (BIST) with diagnostics

• Two high performance Wide Area Network
Controllers address a range of price and
performance requirements
• Intelligent controllers based on 80C186 and 386™
microprocessors with compatible synchronous
serial controllers (82530 and 85C30)

3-24

MULTIBUS®II WIDE AREA NETWORK CONTROLLERS

iSBC®1861410 WIDE AREA NETWORK
CONTROLLER
The iSBC 186/410 MULTI BUS II Serial
Communications Board is an intelligent 6-channel
communications processor that addresses the needs
of many standard communication applications. The
board brings flexibility to the application with its
multiple serial channels as well as I/O expansion
through the SBX connections.

iSBC®1861410 FEATURES
• 8 MHz 80C186 Microprocessor
• SIX Serial Communication Channels, Two RS232C
or RS422A, Four RS232C Only, Front Panel
Connections
• 82258 DMA Controller Provides 4 Independent
DMA Channels
• 512K Bytes DRAM Provided, Four 28 Pin JEDEC
Sites available for EPROM
• Two ISBX Connector provided for I/O Expansion

The iSBC 186/410 is designed to support serial
communication within the system. The iSBC 186/410
board supports asynchronous, byte synchronous,
and bit-synchronous (HDLC/SDLC) communications
on the two full/half duplex RS232C or RS422A
channels. On the remaining four channels, only
asynchronous mode (RS232C) IS supported in either
full or half duplex operation. Each serial channel can
be individually programmed for different baud rates
to allow system configurations with differing terminal
types.

3-25

MULTIBUS®II WIDE AREA NETWORK CONTROLLERS

Interrupt

Control
(2-8250As)

ISflXTM
MulUmodule
Connector

ISflXTM
MuRimodule
Connector

Figure 9: Block Diagram of iSBC@ 186/410 WAN Controller

iSBC®,8614,0 WAN CONTROLLER SPECIFICATIONS
Clock Rates
80C186 Microprocessor
82258ADMA
8751 Microcontroller
82C54 Timer

8MHz
8MHz
12 MHz
(Programmable)

EPROM Memory
Four 28-pin Socket
DRAM Memory

512K bytes

Interrupt Capabilities
14 programmable interrupts
Interfaces
P1
Serial
iSBX

Full PSB
4 Channels, RS-232C only
2 Channels, RS-232C or RS-422A
2 Single Wide

Device Drivers
Check the latest release of the following operating
systems for details:
iRMX I and iRMX 11 Operating Systems
UNIX' System V/386 Operating System

Serial Communications Characteristics
Synchronous:
internal or external character
synchronization on one or two
synchronous characters.
Asynchronous: 5-8 data bits and 1,1-1/2 or 2 stop
bits per character; programmable
clock factor; break detection and
generation; parity, overrun, and
framing error detection.
Serial I/O:
RS232C or RS422A compatible,
configured DTE only; 4 ch. RS232C
IBM compatible only, configured
DTE only.
Physical Characteristics
Standard MULTIBUS 11 board

Power Requirements
Nominal
Voltage
(VDC)
+5
+12
-12

Current
(amps)
Max
8.22A.
150mA
150mA

Power
(watts)
Max
43.16W
1.89W
1.89W

MULTIBUS®II WIDE AREA NETWORK CONTROLLERS

MIX 420 WIDE AREA NETWORK MODULE

MIX 420 FEATURES

The MIX 420 module combines two high speed
synchronous channels with the 386T• CPU-based MIX
baseboard to build a high performance Wide Area
Network (WAN) platform. The MIX 420 modules can
be stacked to a maximum level of three modules for
expansion up to six channels. The MIX 420 can be
stacked with other MIX modules, allowing the system
designer to build a multi-function I/O server with WAN
capabilities.

• Two Independent High Speed Synchronous
Channels using a 10 MHz 85C30 Serial
Communication Controller (SCC).
• High Performance communications capable of 64
kbit/second, with AOMA, and Bypass (slave) speed
modes.
• Flexible communications with an 82C54
Programmable Interface Timer and either channel
interrupts or hardware interrupts using the 82C59
component.
• "Smart Cable" interface using AT&T General
Purpose Synchronous (GPSYNC) Standard
• Designed as a hardware platform for Synchronous
Protocol Support, including SOLC/HOLC, SNA,
Bisync/Async, SNA, X.25, X.21, X.21 BIS, LU6.2
• Firmware containing Built-In Self Test (BIST) code.

3-27

MULTIBUS®II WIDE AREA NETWORK CONTROLLERS
UTILIZING THE MIX ARCHITECTURE

HIGH PERFORMANCE WIDE AREA
NETWORK CONNECTION
The MIX 420 Module provides two independent Wide
Area Network interfaces using the 85C30 SCC with
resulting transfer rates up to 64 Kblt/sec on each
channel simultaneously. Speed is enhanced with an
8 MHz, 82258 AOMA, which supports full duplex
OMA access to each serial channel. A Bypass (slave)
mode is also supported where the CPU handles the
transfers, bypassing the AOMA. This mode allows for
the MIX 420 to act as a slave module reducing
software complexity or allows for the designer to
check the hardware functions of the board.

VERSATILE PROTOCOL SUPPORT
The MIX 420 module provides a hardware platform
for synchronous communication protocols. The
85C30 based channels provide standard hardware
support for SOLC/HOLC, Bisync and Async. The
"Smart Cable" interface provided by the AT&T
GPSYNC cable addresses the high level protocols by
controlling the electronic specification level via an
intelligent cable. This interface allows the designer to
switch protocols by merely addressing the software
issues and swapping to a new cable. The cable will
address the electronic difference between the
interfaces such as X.21 RS232, AS449, \/.35, \/.36 or .
X.24. Finally, the symmetrical design offers channel
independence allOWing for unique protocols and
baud rates to be run simultaneously on the module.

3-28

The MIX 386/420 utilizes the Modular Interface
eXtension (MIX) architecture. The MIX architecture
provides an intelligent base CPU to be combined
with specific I/O modules to create a communication
platform. Specifically the MIX 386 baseboard
provides a 20 MHz 80386 CPU and 1 to 17 MBytes
Fast Page Memory. Modular stacking allows for up to
three modules to be stacked per baseboard, allowing
for up to six high speed synchronous channels
through the use of the MIX 420 Module.

FIRMWARE
Two 32 pin EPROM sites reSide on the MIX 420 for
firmware. Included in the firmware is Built-In-Self-Test
(BIST) to check basic functionality of the module and
MIX interface. Upon power up, the MIX baseboard
copies the MIX 420 BIST from the module to the
baseboard where it is executed during initialization.

MUL TIBUS®WIDE AREA NETWORK CONTROLLERS

SERIAL

Figure 10: Block Diagram for MIX 420 Module

MIX 420 SPECIFICATIONSt
tFor baseboard specifications, refer to the section on
the MIX 386/020 Baseboard.

Programmable Saud Rates
110 K bitisec-64 K bit/sec
Interrupts
Mode
Channel
. Device

Level
2
8

Programmable Interval Timer
82C54
EPROM Memory
Two 32-pin JEDEC sites
EEPROM
128 bytes installed
DMA
82258ADMA

Device Drivers
Check the latest release of the following operating
systems for details:
iRMX II Operating System
UNIX' System V/386 Operating System
Physical Characteristics
Standard MIX module
Power Requirements
Current
Nominal
Voltage
(amps)
(VDC)
Max
3.0
+ 5
.02
+12
-12
.02

8MHz

Interfaces
Serial 2 Channels, AT&T GPSYNC Interface,
RS-232,
AS 449, 11.36, 11.36, X.24, X.21, 85C30
Controller, 10 MHz
MIX
Bus Slave

3-29

Power
(watts)
Max
15.0
0.24
0.24

MULTIBUS®II WIDE AREA NETWORK SOFTWARE

MULTIBUS®II X.25 SOFTWARE

IMPLEMENTATION

X.25 is an international standard synchronous bitorientated serial communications protocol based on
CCITT Recommendations. The protocol provides
connection oriented communications, ie virtual
circuits. The basic unit of transfer is a packet of data.
Performance can range with the speeds of the
communication lines varying from 110 baud to 256k
and above.

The X.25 package is currently available on the iSBC
186/410. The software can co-exits with the
Asynchronous Terminal Controller Software (ATCS),
allowing the iSBC 186/410 to support two X.25 lines
and four terminals. Driver support for the iRMX II
operating system is also available.

X.25 SOFTWARE FEATURES:
• Conforms to CCITT Recommendations 1976, 1980,
1984
• Supports LAPX and LAPB protocols at frame level
• Supports Permanent Virtual Circuits (PVC's)
• Supports Switched Virtual Circuits in the following
Modes: Incoming-only, Outgoing-only and Two-way.
• Supports Networks services such as reverse
charging, closed user groups, etc.
• Supports x.32 Dial-up features
• Operating parameters of each line can be
dynamically changed (e.g. Baud rates, packet size,
timeouts, etc.)
• Modular architecture allows optIOnal functionality to
be added (e.g. X.3/X.28, PAD, X.29, QLLC, SNA)

3-30

INSTALLATION AND SUPPORT
Included with the MULTI BUS II X.25 product is on-site
installation performed by Intel Customer Support.
This service insures that the software is tested and
fully functioning. If further service of the network is
desired,
a support contract may be ordered.

CUSTOMIZATION
Intel Customer Support is available and trained to
customize the X.25 to fit various applications.
Customization may include parameters such as
performance tunihg, specific OS drivers or
application specific requests.

MULTIBUS®II ETHERNET CONTROLLERS

A FAMILY OF MULTIBUS®II ETHERNET LAN CONTROLLERS WITH OpenNEr"
NETWORKING SOFTWARE SUPPORT
The Intel MULTI BUS II Ethernet LAN controller family
provides a range of price and performance for
handling MULTI BUS II Ethernet communication
requirements. The iSBC® 186/530 is an 80186 CPUbased Ethernet LAN controller that provides a costeffective LAN connection for many MULTIBUS II
designs.

subsystems. A MIX-based 1/0 subsystem that
includes the MIX 560 Ethernet module can span the
range from a single MIX 560 module mounted on a
MIX baseboard to a MIX 560 module mounted in a
stack of three MIX 1/0 modules to provide a tailored
MULTI BUS II 1/0 solution that includes Ethernet
communications.

For high performance, the Modular Interface
eXtension (MIX) 560 Ethernet module provides
Ethernet 1/0 capabilities to MIX-based 1/0

Intel's iNA 960 networking software provides ISO
network and transport layer support for both the iSBC
186/530 and the MIX 386/560.

ETHERNET LAN CONTROLLER FEATURES
• A choice of Ethernet LAN controllers providing a
range of price and performance.
• Intelligent controllers based on the 80186 and 386
microprocessors and the 82586 LAN Coprocessor.
• Connection to IEEE 802.3 I Ethernet networks for.
MULTI BUS II systems.

• Support for downloading of networking software
over either the MULTIBUS II Parallel System Bus or
the Ethernet network.
• ISO Network and Transport (ISOIOSI Layers 3 and
4) networking software support provided by Intel's
iNA 960 software.
• iNA 960 networking software executing on the
LAN controllers provides a consistent transport
interface to host CPU boar~s.

3-31

MULTIBUS®II ETHERNET CONTROLLERS
iSBC®186/530 CONTROLLER
SPECIFICATIONS
Clock Rate
'80186 Microprocessor

8MHz

EPROM Memory
Four 28-pin sites.
An additional four 28-pin JEDEC sites may be
obtained by installing an iSBC 341 MULTIMODULE.
DRAM Memory
512K bytes installed on the board

Interrupt capabilities
5 levels with 5 on-board sources

iSBC®,86/530 ETHERNET CONTROLLER
The iSBC 186/530 MULTIBUS II Ethernet Controller is
a dedicated IEEE 802.3 compatible front-end
processor. The boards 8 MHz 80186, 512K DRAM,
and host-to-controller software download capability
allows the board to off-load LAN communications
functions and 1/0 software processing from one or all
of a MULTI BUS II system's host CPU boards.

iSBC®,86/530 ETHERNET CONTROLLER
FEATURES
• Provides IEEE 802.31 Ethernet compatible
networking capability for MULTIBUS II systems.
• Resident firmware to support Built-In Self Test
(BIST), Initialization and Diagnostic eXecutive (IDX),
and host-to-controller software download.
• Four 28-pin JEDEC sites, expandable to 8 sites
with iSBC 341 MULTIMODULE'" for a maximum of
512K bytes of EPROM .
• One RS232C serial port for use in debug and
testing.
• MULTIBUS II Parallel System Bus interface with full
message passing capability.

3·32

Interfaces
P1
Ethernet
Serial

Full PSB
1 channel, 15-pin connector,
82586 LAN Coprocessor
1 channel, RS232C, 25-pin
connector, 8031 Controller

Device Drivers
Check the latest release of the following operating
systems for details:
iRMX I and iRMX II Operating Systems
UNIX' System Vl386 Operating System
Physical Characteristics
Standard MULTIBUS II board
Power Requirements
(Excluding user-installed memory devices)
Nominal
Voltage
(VOC)
+ 5
+12
-12

Current
(amps)
Max
8.8
0.05
0.05

Power
(watts)
Max
44.0
.6
.6

MULTIBUS®II ETHERNET CONTROLLERS

MIX 560 ETHERNET MODULE
The MIX 560 Ethernet Module combines an 82586
LAN Coprocessor, 82501 Ethernet Serial Interface,
and 64K bytes of high speed SRAM data buffer to
provide high performance Ethernet Modular Interface
eXtension (MIX) I/O capabilities. The MIX 560 can be
used either in a MIX module stack, to provide
Ethernet capabilities to a MULTIBUS " MIX I/O server

subsystem, or as a single module on the MIX
baseboard, to provide a high performance MIXbased Ethernet controller. Stacking the MIX 560
Ethernet module with other MIX I/O modules allows
the system designer to manage the system I/O
requirements with a tailored MULTIBUS" I/O
subsystem that includes Ethernet communications.

MIX 560 ETHERNET MODULE FEATURES
• 82586 LAN Coprocessor operating at 10 MHz.
82501 Ethernet Serial Interface.
• 64K bytes of SRAM data buffer for handling
communications from the MIX baseboard to the
Ethernet Interface.
• Support for 128K-265K EPROM.

• Firmware containing Built-In Self Test code.
• LED for 82586 Activity.
• Serial interface for system console or debug.

3-33

MIX 560 FEATURES

ETHERNET INTERFACE

FIRMWARE

The Ethernet interface is implemented using the
82586 Ethernet Coprocessor, the 82501 Ethernet
Serial Interface controller, and the standard slide-lock
15' pin IEEE 802.3 connector. The 82501 is software
configurable to either Ethernet V1.0 or IEEE 802.3
(Ethernet V2.0). IEEE 802.3 is the default. The
Ethernet interface operates at a fixed rate of 10 Mbits
per second. An Ethernet station address PROM is
also provided.

The MIX 560 module contains two 32 pin sockets,
accommodating either two 27512 or two 27010
EPROMS. Firmware provided for the MIX 560 module
includes MIX 560 Built-In Self Test (BIST) code and
the software load commands.

SERIAL INTERFACE
The serial interface is implemented using the 82510
Asynchronous Serial Controller, an RS232 driverl
receiver, and a serial port connector. The connector is
an IBM-compatible 9-pin DTE interface (only 3 pins
are used). The port is intended for use as the system
console or as a debug port. The serial interface
supports baud rates up to 19.2K.

TIMERS
Two 16-bit interval timers are provided by an 82C54
for generating timed, independent interrupts at the
MIX interface. A third timer, also provided by the
82C54, is used as a 16 bit prescaler to the other two
timers. The timers are used by Intel's iNA 960
Networking Software.

STATIC RAM
The MIX 560 contains 64K bytes of Static RAM
(SRAM). The memory is shared between the MIX
interface and the 82586. Networking software
executing on the MIX baseboard can use the SRAM
as a buffer to send and receive data over the Ethernet
interface as well as issue commands to, and receive
status from, the 82586 Ethernet Coprocessor.

3-34

The MIX 560 BIST code resides in EPROM on the
module. On power up, the MIX baseboard copies the
MIX 560 BIST code from the module to the
baseboard where it is executed during initialization.
The MIX 560 BIST contains 12 tests for exercising the
module and verification of functionality. The MIX 560
firmware provides LAN software load commands for
the MIX baseboard. The firmware will both upload
and download software to the MIX baseboard using
either the MULTIBUS II Message Passing
Coprocessor or the Parallel System Bus shared
memory. The firmware commands also provide the
ability to read and set the Ethernet station address
and start execution of LAN software code on the MIX
baseboard.

MIX 560 FEATURES

Buffer

I/OADDR

MIX
ADR
Buffer

NETADR

82588
ADR
Latch

I/O SUBSYSTEM

ETHERNET SUBSYSTEM
CONTROL BLOCK
NETADR

Flag
Word
Reg

Timer
8254

Serial
82510

I"""""

82588
LAN
Coprocessor

82C501
Ethernet
Controller

.....

L..-.-

MIX
Interface

EEPROM

MEMORY
SUBSYSTEM

EPROM

Buffer

I/O Data

SRAM

NETDAT

Buffer

Figure 11: MIX 560 Module Block Diagram

MIX 560 SPECIFICATIONSt
tFor Baseboard speCifications, refer to the section on
the MIX 3861020 Baseboard

Clock Rates
82586
EPROM Memory
Two 32-pin JEDEC sites:

Device Drivers
Check the latest release of the following operating
systems for details:
iRMX II Operating System
UNIX' System V/386 Operating System

SRAMMemory
64K bytes installed on the module

Physical Characteristics
Standard MIX module

EEPROM
128 bytes installed on the module

Power Requirements
Nominal
Current
Voltage
(amps)
(VDC)
Max
3.0
+ 5
+12
0.02
-12
0.02

10 MHz

PROM
6 bytes for Ethernet node address
Interfaces
Ethernet
Serial
MIX

1 channel, 15-pin connector,
82586 LAN Coprocessor
1 channel, RS232C, 9-pin
(IBM-compatible) connector,
82510 Controller
Bus slave

Power
(watts)
Max
15.0
0.24
0.24

The MIX 560 module also passes fused + 12 VDC
through the Ethernet connector to an external
transceiver. The transceiver may require up to an
additional 0.5 Amps (max) of + 12 V.

3-35

MULTIBUS®II ETHERNET CONTROLLERS
CONFIGURABLE AT THE OBJECT
CODE LEVEL
Consisting of linkable object modules, the iNA 960
software can be configured to implement a range of
capabilities and Interface protocols. iNA 960 has a
large installed base and has been used reliably in a
variety of systems from IBM PC XTIATs to VAXNMS
to IBM mainframes.

BASED ON INTERNATIONAL STANDARDS
Based on the ISOIOSI seven layer model for network
communications, iNA 960 Implements ISO 8073
Transport Class 4 providing reliable full-duplex
message delivery service on top ofthe internet
capabilities offered by the network layer. The iNA 960
network layer is an implementation of the ISO 8473
Network Class 3 Connectionless Network Protocol
and supports ISO 9542 End System to Intermediate
System Network Dynamic Routing. iNA 960 also
supports ISO 8602 Connectionless Transport Protocol
(Datagram).

iNA 960 OpenNETTM NETWORKING
SOFTWARE FEATURES:

PRECONFIGURED iNA 961

• Certified ISOIOSI Transport and Network Layer
Software
• ISO 8072/8073 Transport Class 4
• ISO 8602 Connectionless Transport
• ISO 8348/8473 Connection less Network
• ISO 9542 End System to Intermediate System
(ESIIS) Dynamic Routing
• Comprehensive Network Management Functions
• Remote Boot Server for diskless workstations
• Data Link Drivers for iSBC 552A, ISBX 586, iSBC
554, ISBC 186/51, iSBC 186/530, and MIX 386/560

FULLY COMPLIANT ISO/OSI TRANSPORT
AND NETWORK LAYER SOFTWARE
iNA 960 is a complete Network and Transport
(ISOIOSI Layers 3 and 4) software system plus
a comprehensive set of network management
functions, Data Link (aS I Layer 2) drivers for IEEE
802.3 Ethernet and IEEE 802.4 Token Bus (MAP),
and system environment features.

FLEXIBLE AND HIGHLY CONFIGURABLE
iNA 960 is a mature, flexible, and ready-to-use
software bUilding block for OEM suppliers of
networked systems for both manufactUring and office
applications (e.g., MAP and TOP).
This software is highly configurable for designs based
on the 82586 and 82588 LAN controllers, 82501 and
82502 Ethernet serial Interface and transceiver, and
the Intel 86 family of microprocessors.

3-36

iNA 960 contains the preconfigured iNA 961 software
modules which include support for the iSBC 552A,
iSBC 554, iSBC 186/530, and the MIX 386/560.

REMOTE BOOT SERVER SUPPORT
iNA 960 provides basic boot server capabilities that
will transmit predefined images to diskless network
nodes that request them.

MULTI-5ERVERICONSUMER SUPPORT
iNA 960 supports the powerful MULTIBUS "feature
of multiple host and communications boards. This is
Ideal for LAN load balanCing and redundant networks
for fault-tolerant systems.

MULTIBUS®II PERIPHERAL CONTROLLERS

A CHOICE OF PERIPHERAL CONTROLLERS
Intel's product line of MULTI BUS II Peripheral
Controllers addresses the diverse interfaces of
peripheral communications. The iSBC 186/224A, a
Multi-Peripheral Controller Subsystem, provides
support for up to four ST506/412 Winchester disk
drives, up to four SA450/460 floppy drives and
quarter inch QIC-02 streaming tape

drives. The iSBC 3861258, a versatile highperformance SCSI peripheral controller, provides
performance tuning capability for peripheral devices
Individually for optimum system performance.
Additionally, the iSBC 386/258 can complement the
host by offloading it with its powerful 386T>!
microprocessor.

PERIPHERAL CONTROLLER FEATURES:
• Multiple peripheral interface support
Small Computer Systems Interface (SCSI)
ST506/412 Winchester Disk Drive Support
SA450/460 Floppy Drive Support

QIC-02 one quarter inch Streaming Tape Drive
Support
• Full PSB interface with complete Message Passing
Support
• On-board Built-In-Self-Test (BIST) with Diagnostics

3-37

MULTIBUS®II PERIPHERAL CONTROLLERS
iSBC®186/224A PERIPHERAL
CONTROLLER SPECIFICATIONS
Clock Rate
80C186 Microprocessor

5 MHz

EPROM Memory
Two 28-pin sites.
, DRAM Memory
128K bytes installed on the board
Mass Storage Device Drives
Winchester
ST506/412 compatible 5-1/4" drives with up to 1024
cylinders. Qualified manufacturers include:
Quantum, CMI, CDC, Maxtor, Memorex, Atasi.
Densities range from 10 to 140 MB.

iSBC®186/224A MULTI·PERIPHERAL
CONTROLLER SUBSYSTEM
The iSBC 186/224A Multi-Peripheral Controller
Subsystem provides peripheral 110 control for a
variety of OEM applications and supports the full
message passing protocol of the MULTIBUS "
System Architecture. The iSBC 186/224A controller
serves as a complete peripheral 110 subsystem and it
supports the predominant types of storage media:
Winchester disks, floppy disks and quarter-inch
streaming tapes. On-board firmware for the board
provides improved Winchester disk operation through
multiple data track cacheing.

ISBC®186/224A FEATURES
• 80C186 Microprocessor at 5 MHz
• Controls up to Four ST506/412 Winchester Disk
Drives, Four SA450/460 Floppy Drives, and Four
QIC-02 Streaming Tape Drives.
• 128K Bytes of On-Board SRAM for multiple track
cacheing on high speed Winchester data access.
• BUllt-ln-Self-Test (BIST) Diagnostics On-Board
• Full Message Passing interface to the Parallel
System Bus.

Floppy
SA450/460 compatible 51/4" drives. Qualified
manufacturers include: Teac and Shugart. Sizes
include half height, full height, 48 TPI and 96 TPI.
Tape
QIC-02 compatible, 1/4" streaming tape drives.
Qualified manufacturers include: Archive, Cipher,
and Tandberg.

Interfaces
P1
ST506/412
SA450/460
QIC-02

Full PSB
50 pin D-type
25 pin D-type
25 pin D-type

Device Drivers
Check the latest release of the following operating
systems for details:
iRMX I and iRMX " Operating Systems
UNIX' System V/386 Operating System
Physical Characteristics
Standard MULTIBUS " board.
Power Requirements
Nominal
Current
(amps)
Voltage
(VDC)
Max
7.0
+5
0.05
+12
-12
0.05

3-38

Power
(watts)

Max
35.0
.6
.6

MULTIBUS®II PERIPHERAL CONTROLLERS

iSBC®386/258 SCSI PERIPHERAL
CONTROLLER
The iSBC 386/258 is a high-performance peripheral
controller that combines powerful I/O performance
and access to SCSI peripherals for MULTI BUS II
applications.
Minicomputer-level 1/0 performance is achieved by
utilizing the 386'" microprocessor and a large data
cache. The added power of the 386'· processor gives
the iSBC 386/258 the potential of off-load tasks from
other system CPUs as an I/O server. The SCSI
standard has achieved wide acceptance because of
its extensive capabilities and excellent performance.

ISBC®386/258 FEATURES
•
•
•
•
•
•
•
•

16 MHz 386'· microprocessor
1 or 4 MByte data buffer
CSM002 module support
Common Command Set (CCS) SCSI peripheral
support
Asynchronous SCSI to 1.5 MBytes/sec,
synchronous to 4.0 MBytes/sec
Two Versions: single ended SCSI port only or Dual
SCSI ports
Firmware support for BIST, lOX, slave test handler,
and downloader
258 Peripheral Communications Interface (258PC I) firmware

COMPLETE SCSI CAPABILITY
The iSBC 386/258 supports communication with up
to seven other peripheral adapters and up to 56
possible devices. Vendor-unique features of

peripherals can be accessed uSing the pass through
capability. Also supported is the ability to be a bus
Initiator, and the use of disconnect/reconnect.
Peripherals that support the SCSI standard today
include magnetic hard disk, magnetic tape, floppy
disk drive, optical disk, and line printers.

HIGH PERFORMANCE
I/O critical applications are accelerated by the
combination of a 16 MHz 386'" processor, a large
data buffer for cachelng (1 or 4 MBbytes), and the 4.0
MBytes per second synchronous transfer rate for
SCSI.

FIRMWARE SUPPORT
The iSBC 386/258 includes EPROMs with firmware
support for BIST (Built-in Self-Test), lOX (Initialization
and Diagnostics Executive), Power up and slave
handler, a downloader, and a peripheral
communications interface.
The 258-PCI firmware establishes a high level
software protocol to facilitate the exchange of data
between host drivers and SCSI-based peripheral
devices. It also insulates host drivers from knowledge
of SCSI bus management. The 258-PCI server
manages up to 64 outstanding commands and
permits multiheaded I/O operations with up to 56
SCSI peripheral devices.
The 258-PCI server also allows tuning of the cache
configuration, command ordering/seek. optimization,
and reporting of usage statistics, like the number of
cache hits and misses, total number of reads, writes,
and errors.

MULTIBUS®II PERIPHERAL CONTROLLERS

Figure 12: Block Diagram for iSBC® 386/258 Peripheral Controller

iSBC®386/258 PERIPHERAL CONTROLLER SPECIFICATIONS
Clock Rates
38670 OX Microprocessor
82258ADMA
8751 Microcontroller

16 MHz
8 MHz
12 MHz

EPROM Memory
Two 32-pin Sockets

DRAM Memory
1M or 4M byte installed on the baseboard
Interrupt Capabilities
14 programmable interrupts
Interfaces
• P1, Full PSB
• P2, SCSI: ANSI X3.131-1986, Single-ended or
dual versions available.
• iSBX Bus Interface
• Serial I/O Port: RS-232-C (subset)interface (DTE).
9-pin D-shell shielded connector.

Device Drivers
Check the latest release of the following operating
systems for details:
iRMX II Operating System
UNIX' System V/386 Operating System·
Physical Characteristics
Standard MULTI BUS II board.
Power Requirements
Typical values for power are at the nominal
voltageand at an ambient temperature of 25 degrees
C. Maximum values are at nominal voltage plus 5%
and at an ambient temperature of 0 degrees C.
Nominal
Voltage
(VDC)
+ 5
+12
-12

Current
(amps)
Max
11.0
5~

5.0

Does not include power for installed iSBX
MULTI MODULE boards

Power
(watts)
Max
55
60
60

MULTIBUS®II PARALLEL I/O

iSBC®MPI/519 72 CHANNEL DIGITAL 110
BOARD
The iSBC MPI/519 is a digital I/O Interface board
which provides 72 parallel channels of TTL level I/O
In Multlbus II I/O space. The board IS capable of
receiving Interrupts from other MULTIBUS II agents,
as well as generating Interrupts from up to 8 sources.
It IS one of a family of MPI (Multibus II Peripheral
Interface)-based I/O boards.

iSBC®MPI1519 FEATURES:
• 72 channels of TTL level I/O In banks of 24
channels each
• Banks conflgurable for general purpose Industrial
I/O or as Centronics compatible ports
• Output lines may be read back to verify output
status
• Socketed buffer drivers and resistor networks for
configuring I/O as high or low true
• 8 Interrupt request lines
• PreCision Interval pulse triggering on one of three
I/O lines

FUNCTIONAL DESCRIPTION
The iSBC MPI/519 is a digital I/O board suitable for
applications such as industrial automation, printer
Interface, or for low cost inter-chassis communications
requIring multiple parallel I/O lines.
The iSBC MPI/519 board is based on the MULTI BUS
II Peripheral Interface (MPI) component which
provides all the logiC required to interface to the
Parallel System Bus (PSB), allows the board to be a
replier in I/O and interconnect space, and supports
the sending and receiving of Interrupt messages.

3-41

MULTIBUS®II PARALLEL 1/0
72 DIGITAL 110 CHANNELS

CENTRONICS COMPATIBLE

The 72 channels of TTL (5v) level I/O are arranged in
three banks of 24 I/O each (Figure 13). Each bank is
implemented' using two Intel 82C55 Programmable
Peripheral Interface (PPI) components (Figure 14).
Port A of each PPI is connected to the front panel
through bidirectional buffers. They can be software
configured as input or output on a byte basis.
Sockets in front of the buffers are provided for the
user to add pull-up, pull-down or voltage dividing
resistor networks (2.2 K-ohm pull-up resistors 'are
provided). To allow data readback, Port B of each PPI
is connected directly to the output side of the Port A
buffers, for use in board diagnostics or to ensure the
integrity of critical data.

Each bank may be used as a Centronics compatible
port. Bank one can automatically generate the data
strobe, eliminating an extra bus transaction.

8 INTERRUPT REQUEST LINES
Input interrupts coming from external sources
through the front panel are implemented through an
82C59 Programmable Interrupt Controller (PIC) and
cause the iSBC MPI/519 to send an unsolicited
interrupt message. Up to eight input interrupts are
supported. The interrupt source is encoded in the
interrupt message. One input interrupt can be
configured as a broadcast interrupt, which is sent to
all agents. This interrupt is useful to synchronize
processors or to alert all processors to an external
system event. Output interrupts, received by the iSBC
MPI/519 from other agents, cause a 82C54
programmable interval timer to output a precise
interval pulse. These pulses can be from 1 msec to 6.5
msec. in length. There is one output line for output
interrupts on each I/O bank.

Each bank also has an additional 8 bits I/O
implemented through Port C, for use as general
purpose I/O or as input and output interrupts.
I/O signals may be interfaced to industry standard
signal conditioning and isolation modules through
termination panels such as Intel's iRCX910 or
OPTO-22's PB24.

r-J1

8
8
4

1/0

r+-

1
1

1rP--

8
~

8
/8
~

....-.

lf!.+

Input
Interrupt
Control

j.-

Interlace

Output
Interrupt
Control

1/0

Lf.i...,

r-J3

r-f

r"j2

PSB
MPI
Interlace

Interlace

Lfi+

"'--

......"......~

,D8
f

1/0
Interlace
I

Figure 13: Block Diagram for iSBC@ MPI/519 Board

3-42

. . -.....7

MULTIBUS®II PARALLEL 1/0

82C55

PortA

LSB

Port B

PortC

To Output
Interrupt Control
Port A

~--MSB

Port B

PortC

To Input
Interrupt Control

Figure 14: Block Diagram of one iSBC® 519 I/O Bank

iSBC®MPI1519 DIGITAL 110 BOARD SPECIFICATIONS
Interfaces
P1
Centronics

Slave PSB
Each of the three 1/0 banks can be
used as a Centronics compatible
interface. Bank 1 is configurable to
minimize handshaking and bus
transactions when used as a printer
interface.
I/O connector:3 Positronics ODD44F500TX

Physical Characteristics
Standard MULTIBUS II board
Power Requirements
Nominal
Current
Voltage
(amps)
(VDC)
Max
3
+5

Power

I/O Buffer and Resistors Supplied
Bidirectional
Unidirectional
Resistor
. Buffers
Buffers
Networks
74ALS645
74ALS09
2.2 K-Ohm
Other Components Supported
Bidirectional
Buffers

Unidirectional
Buffers

Resistor
Networks

74ALS638-7 4AS638
74ALS639-7 4AS639

74ALSOO-7 4ASOO
74ALS08-74AS08

9 or 10 pin SIPs
all values
supported

74ALS640-7 4AS640
74ALS643-7 4AS643

74ALS32-7 4AS32
74ALS37 -7 4AS37
74ALS38-7 4AS38
or equivalent

or eqUivalent

(watts)

Max
15

3-43

MULTIBUS®II ARCHITECTURE STANDARDS
ENVIRONMENTAL REQUIREMENTS

DEVICE DRIVERS

Operating Temperature: 0 to 55°C @ 200 LFM
airflow
.
Non-operating: -40 to 70°C
Humidity: 0 to 85% non-condensing

Ch!3ck the latest release of the following operating
systems for details:
.
iRMX I Operating System
iRMX II Operating System
UNIX' System V/386 Operating System

INTERFACES
FullPSB
A full PSB interface is implemented with the 82389
MPC component. This interface is Intel's
implementation of the IEEE/ANSI1296 specification
cast in Silicon. All boards with a full PSB interface
have the feature set of the MPC component
descnbed in the silicon section.

COMPREHENSIVE DEVELOPMENT AND
OPERATING SYSTEM SUPPORT

Operating system support includes the iRMX II RealTime operating system and UNIX' System V/386.
The iRMK I real time kernel is available for 32-bit
embedded applications. All three-IRMX, iRMK and
UNIX operating systems include MULTIBUS II
transport for full message passing support. To ease
MULTIBUS II modules development, Intel offers both
SlavePSB
the iRMX and UNIX versions of the System 520
A slave PSB Interface is implemented with the MPI
Development System which can support on-target
component. The MPI is a cost and function reduced
andlor cross-hosted software development in one
"little brother" of the MPC component. All boards with . chassis.
the slave PSB interface have the feature set of the
MPI component described in the silicon section.

WORLD WIDE SERVICE AND SUPPORT

MMOx Memory Expansion
The MMOx interface uses a custom surface mount
connector to add expansion local memory to a CPUbased product. The connector allows up to two
.
modules to be added to a baseboard. Memory
modules are single-sided (1MB or 4MB) or doublesided (2MB or 8MB). A board with a single-sided
module consumes a single MULTI BUS II slot, all other
combinations require two MULTIBUS II slots (Note: If
two MIX modules are used, then two slots are used).

Should this or any Intel board ever need service Intel
maintains a world wide network of service and r~pair
facilities to keep you and your customers up and
running. For unique applications requiring
customizatlon of our products, the Intel Systems
Group is available to modify, integrate and test Intel
boards and system components to your
requirements.

INTEL QUALITY-YOUR GUARANTEE

MIX
The MIX interface is described in the MIX architecture
section.

All MULTIBUS II 1/0 products are designed and
manufactured to meet Intel's high quality standards.
Intel quality is then verified by rigorous testing in our
state-of-the-art Environmental Test Laboratory.

PHYSICAL CHARACTERISTICS

'UNIX is a trademark of AT&T in the U.S.A. and other
countries.

Standard MULTIBUS®II Format
(Double 6U Eurocard)
Height: 23.3 cm (9.18 inches)
Depth: 22.0 cm (8 65 Inches)
Width:
1.92 cm (0 76 inches)
MIX Expansion Module:
Module Height: 8.9 inches
Module Depth: 3.75 inches
Module Area:
33 square inches
iSBX'" Modules:
Single-Wide
Double-Wide
Height:
2.1 cm (0.827 inches) 2.1 cm (0.827 inches)
Depth:
7.24cm (2.85 Inches) 7.24cm (2.85 inches)
Width:
9.4cm (3.7 inches) 19.05cm (7.5 inches)

3-44

LITERATURE AND PRODUCT GUIDE
Product

Description

Manual Number

MULTIBUS®/1 SILICON PRODUCTS
82389
MPI

Message Passing Coprocessor
Datasheet for 82389 Message Passing Coprocessor
MULTIBUS " Peripheral Interface

176526
290145

MIX DEVELOPMENT KIT
MIX386020-1
MIX386020-1 F01
MIX386020-1 F04
MIXMDKIT-1
MIXMDKIT-1 F01
MIXMDKIT-1 F04
MIXMDKIT-1S
MIXMDKIT-1 F01 5
MIXMDKIT-1 F04S

MIX baseboard w 1MB
MIX baseboard w 1MB + 1MB module
MIX baseboard w 1MB + 4MB module
Kit with baseboard w 1MB
Kit with baseboard w 1MB + 1MB module
Kit with baseboard w 1MB + 4MB module
Same as MIXMDKIT-1 w SE support
Same as MIXMDKIT-1 F01 w SE support
Same as MIXMDKIT-1 F04 w SE support

503353
503353
503353
500731
500731
500731
500731
500731
500731

MIX EXPANSION MODULES
MIX 450
MIX 420
MIX 560
MIX MOD1
MIX MOD2
MIX MOD3

MIXSC10

MIX Terminal Controller Module
MIX WAN Module
MIX Ethernet Module
Test Module
Breadboard Module
Debug Module
Ten MIX Stacking Connectors

FIRMWARE DEVELOPMENT

I MSABASEFDP

I Firmware Development Package

500799
500798
459622

I Included

TERMINAL CONTROLLERS
SBCMPI450
SBC186450
MIX386450-1
MIX386450-1 F01
MIX386450-1 F04

MPI-based terminal controller
Mid-range terminal controller
MIX Terminal Controller with 1MB
MIX Terminal Controller with 2MB
MIX Terminal Controller with 5MB·

502200
502238
503353 + 500799
503353 + 500799
503353 + 500799

WIDE AREA NETWORK CONTROLLERS
SBC186410

MIX386420-1
MIX386420-1 F01
MIX386420-1 F04

Mid-range WAN board
MIX WAN board with 1MB
MIX WAN board with 2MB
MIX WAN board with 5MB

148941
503353 + 500798
503353 + 500798
503353 + 500798

LOCAL AREA NETWORK/ETHERNET CONTROLLERS
SBC186530
MIX386560-1
MIX386560-1F01
MIX386560-1 F04

Mid-range Ethernet board
MIX Ethernet Board with 1MB
MIX Ethernet Board with 2MB
MIX Ethernet Board with 5MB

149226
503353 + 459622
503353 + 459622
503353 + 459622

PERIPHERAL CONTROLLERS
SBC186224A
SBC386258SM01
SBC386258SM04
SBC386258DM04

Multi-peripheral controller Subsystem
Single-ended SCSI Controller w 1 MB
Single-ended SCSI Controller w 4 MB
Differential SCSI Controller w 4 MB

PARALLEL CONTROLLERS

I SBCMPI519

I Digital 1/0 Board

138272
149861
149861
149861

I 502201
3-45

LITERATURE AND PRODUCT GUIDE
Product

Description

Manual Number

SOFTWARE PRODUCTS
INA960J
X.2S

Networking software
Communications software

462250

OTHER MULTIBUS®II TECHNICAL LITERATURE

ANSI/IEEE 1296

MIX Module Design Specification
Ap Note On: "Simple 1/0 Design Example Using ... MIX .. "
Interconnect Interface Specification
MULTIBUS II Transport Protocol Specification
Initialization and Diagnostics
Bootstrap
A MULTI BUS II OVERVIEW, Article Reprints and Technical
Papers
Order from: IEEE, 345 E. 47th Street, NY, NY 10017

3-46

500729
28'1004
149299-001
149247-002
454077-001
455975-001
280684~002

MULTIBUS® II
System Packaging and
Development Accessories

inter

iSBC® PKG/606
iSBC PKG/609
MULTIBUS® II CARDCAGE ASSEMBLIES

• Available in Two Sizes to Hold Up to 6
or 9 MULTIBUS® II Boards

•

All Lines Fully Terminated per the iPSB
MULTIBUS II Specification

•

Assembly Uses Aluminum Extrusion
Construction for Strength and Rigidity

•

Uses a 6 Layer Parallel System Bus
(iPSB) Backplane

Designed to Mount Inside a Chassis or
Other Enclosure

• Accommodates Intel iSBC® PKG/902
and iSBC® PKG/903 2 and 3 Slot
iLBXTM II Backplanes

The iSBC PKG/606/609 series of cardcages are designed to mount and interconnect up to 6 or 9 MULTIBUS II
boards for small to medium size advanced MULTIBUS II microcomputer systems. The cardcages are compact
in size and easily mount in standard or custom enclosures. Extra-wide support extrusions and heavy duty
endplates help make the iSBC PKG/606/609 cardcage assemblies especially suited for installation in systems
located in high vibration or high shock environments. Installed in the cardcage assembly is a 6 layer iPSB
backplane that utilizes separate power and ground planes and fully terminates all signal lines. This layout
minimizes system noise and ensures reliable operation even in a fully loaded, multiprocessor-based system.

280075-1

4-1

September 1986
Order Number: 280075-002

intJ

iSBC® PKG/606 iSBC PKG/609

FUNCTIONAL DESCRIPTION

Mechanical Features
The card cages accommodate up to 6 (iSBC
PKG/606) or 9 (iSBC PKG/609) MULTIBUS II
boards spaced at 0.8 inch centers. The assemblies
are designed to hold "double high" (6U) Euro formfactor boards (233.4 mm high x 220 mm deep) or a
mixture of "single high" (3U) and "double high"
boards using additional hardware (not supplied).
Each installed board is held in place by two screws
supplied as part of the board retainer hardware.
The cardcage frame is built using five support extrusions and two aluminum end plates as shown in figure 1. Both cardcages are 10.S" wide and 10.1"
deep and vary in height according to model (see
specifications section).
The cardcages are designed to mount inside chassis
or other enclosures and may be installed so that the
MULTIBUS II boards load either horizontally or vertically in the unit. All assembly hardware is countersunk ~lIowing the cardcages to be mounted flush
against any internal chassis surface.
A Parallel System Bus (iPSB) backplane is mounted
to the P1 side of the assembly, and one or more
iLBXTM II backplanes (not supplied) can be mounted
to the P2 side.

capacitive loading on the bus. Mounted on the backplane are 6 or 9, 96-pin, female DIN connectors (depending on model), bus termination resistors, decoupiing capacitors, and power terminals. Press-fit technology is used throughout. The PC board is UL recognized for flammability. The card cages themselves
are UL recognized components.
Single In-line Package (SIP) style resistors are used
to terminate all address, clock, data, and control
lines. Each termination consists of two resistors
which connects the line to + VCC and ground. Different size resistors are used according to the type
of driver connected to the line in an operating
system.
.
The DIN type connectors are female, 96 pins, fully
gold plated, and meet IEC standard 603-2-IECC096F. The connectors are mounted on 0.8" centers to match Intel's iPSB (Parallel System Bus)
MULTIBUS II backplanes and are keyed to ensure
proper mating to the MULTlBUS II board. The connector can provide up to 9 amps of current at + SV
to each MULTIBUS II board in addition to the current
available over the iLBX II backplane.
Screw terminals on the backplane are provided for
connection to + SV, ± 12V power and ground. In addition, an extra + SV terminal is provided for connection to a backup battery for memory protection during power fail conditions. These terminals, each of
which can handle up to 2S amps of current at SS·C,
provide a 'simple and highly reliable connection
method to the system power supply.

Electrical Features
The iPSB backplane uses a 6 layer design with separate power and ground layers and a signal routing
scheme which minimizes ringing, crosstalk, and

The first slot position is designed to accept the Central Services Module (CSM) MULTIBUS II board. All
other slots can accept any combination of
MULTIBUS II boards.

END PLATE
(1 OF 2)
IPSB BACKPLANE
(9 SLOT SHOWN)

L
.1
r-(25.68CM.)~

-PI ,DE

SUPPORT
EXTRUSION _
(1 OF 5)

.'
-,
::

..::
.1

SLOT 0
(Jl)

10.11 IN

.'; I

ILBXNII
MOUNTING
LOCATION
-P2SIDE

-I

L-l0.47IN. - '
(26.59 CM.)

SUPPORT

/
/

ir".EXTRUSION

V- CARD GUIDE

'SEE SPECIFICATIONS

280075-2

Figure 1. Cardcage Assembly Dimensions (iSBC® PKG/609 shown)
4-2

inter

iSBC® PKG/606 iSBC PKG/609

SPECIFICATIONS

Mechanical
Specification
Board Capacity
Dimensions Height
Width
Depth
Weight

iSBC® PKG/606 Cardcage

iSBC® PKG/609 Cardcage

6
15.20 cm (5.98 in.)
26.59 cm (10.47 in.)
25.93 cm (10.21 in.)
4 Ibs. (1.8 kg)

9
21.20 cm (8.38 in.)
26.59 cm (10.47 in.)
25.93 cm (10.21 in.)
5 Ibs. (2.3 kg)

Board Spacing

0.8 in. (20.3 cm)

Mounting Hole Locations

See Figure 2

Construction Materials,
Cardcage Frame

Aluminum extrusions and end plates, nylon card guides

Construction Method
iPSB Backplane

Six layer backplane with separate VCC and ground layers;
all connectors, power terminals, and resistor/capacitor
sockets are press-fit into the backplane

Connector Type

96 pin "DIN" female, gold plated, meets IEC standard
603-2-1 EC-C096-F
Quantity of Power Terminals and Current Rating:

Electrical
iPSB Backplane- Meets Intel MULTIBUS II specification No. 146077 for board
dimensions, layout, signal line
termination, and transmission
characteristics
Power Connections- Type: Screw terminal block,
AMP PIN 55181-1, Winchester PIN 121-25698-2, or
equivalent

.73IN~ ~
(1.85 CM)

Quantity

FRONT
9.01 IN
(22.89 CM)

iSBC® PKG/609
Cardcage

Current
Current
Quantity
(amps)
(amps)
54
12
12
12
78

4
1
1
1
5

1.49 IN
(3.78 CM)

-.l
f

BOTTOM
VIEW

M.)

JiV-

:-0

BACKPLANE
MOUNTING
LOCATION

3
1
1
1
4

+5
+12
-12
+5BB
GND

6.28 IN

Voltage

iSBC® PKG/606
Cardcage

.188 IN (4.78 MM)
DIA. (4 PL)

7------REAR

280075-3

Figure 2. Mounting Hole Locations
4-3

81
18
18
18
135

iSBC® PKG/606 iSBC PKG/609

Operating Environment:
0-55·C (at 25 amps per power terminal);
0-70·C (at s 18 amps per power terminal);
0% to 95% relative humidity, non-condensing;
0-10,000 ft. altitude.
Reference Manual- MULTI8US II Cardcage Assembly and iLBX II 8ackplane User's Guide, PIN
146709-001 (supplied).

Mating Connection: No. 6 locking spade or ring
tongue lug

Maximum current available per slot:
Voltage

Current

+ 5V
+12V
-12V
+588

9A
2A
2A
2A

ORDERING INFORMATION
Part Number

Description

iSBC PKG/606

6 slot MULTIBUS II Cardcage
Assembly

iSBC PKG/609

9 slot MULTI8US II Cardcage
Assembly

4-4

iSBC® PKG/902
iSBC® PKG/903
MULTIBUS® II iLBXTM II BACKPLANES
•

Provides iLBXTM " Interconnect for
Fastest CPU/Memory Data Transfers

•

Uses a 6 Layer, Fully Terminated
Backplane

•

Designed to Mount In MULTIBUS® "
Cardcage Assemblies

•

Includes a 10 Pin Connector for
BITBUSTM Applications

•

Meets All Electrical and Mechanical
Requirements of the MULTIBUS® "
Specifications

•

Available in 2 Slot (iSBC® PKG/902)
and 3 Slot (ISBC® PKG/903) Sizes

The iSBC PKG/S02 and iSBC PKG/S03 series of iLBX II backplanes are designed to mount on the P2 side of
Intel's MULTIBUS II cardcage assembly or other double Euro (6U) cardcage. One or more backplanes may be
installed in a system to allow high speed data transfers between the CPU and memory boards installed in the
system. The iLBX II backplane uses a 6 layer PCB with separate power and ground planes and full termination
on all signal lines. This design minimizes system noise and ensures reliable operation in all applications.

•• _ ••

.~.~

_ _ _ _ • __ w • •

_WW~_W.~~.

~~.~~WW.

__ _

_wW~~~~.~_._._~_

280074-1

4-5

October 1986
Order Numbe~: 280074-002

intJ

iSBC® PKG/902 iSBC® PKG/903 BACKPLANES

of driver connected to the line in an operating system. The SIP style resistors help make the board
compact in size and allows the designer to mount
several backplanes directly adjacent to one another
in a system without having to skip slots.

,-,...-

.110 IN. DIA. (4PL) / "
(2.8MM)

r--

Mounted on the rear of the backplane is a 10-pin
BITBUS connector. This connector serves as the serial communication interface for any iSBX 344 BIT~
BUS controller boards installed in the system.

ua:
.....

a:3

C'iui

:1-

.....

The DIN type c~nnectors are female, 96 pins, fully
gold plated, and meet IEC standard 603-2-IECC096F. The_ connectors are mounted on O.S" centers to match Intel's iPSB (Parallel System Bus)
MULTIBUS II backplanes and are keyed to ensure
proper mating to the MULTIBUS II board. The connector can provide up to 6 amps of current at + 5V
to each MULTIBUS·II board in addition to the current
available over the Parallel System Bus backplane.

N'"
:J~

-o

Screw terminals on the backplane are provided for
connection to + 5V power and ground. These terminals, each of which can handle up to 25 amps of
current, provide a simple and highly reliable connection method to the power supply.

01-'-

-I

280074-2

Dimensions

iSBC PKG/902

SPECIFICATIONS

IN 1.55 .80
CM 3.94 2.03

Mechanical and Environmental

iSBC PKG/903 IN 2.35 1.60
CM 5.97 4.06

Connector Spacing: 20.3 cm (O.S in)
Number of Slots: iSBC PKG/902: 2 slots

Figure 1.iLBXTM II Board Dimensions
(iSBCCIi> PKG/903 Shown)

iSBC PKG/903: 3 slots
Board Dimensions: See Figure 1
Weight: iSBC PKG/902-'O.2 kg (S oz)

FEATURES

iSBC PKG/903-0.3 kg (12 oz)

Mechanical and Electrical

Connectors:
DIN: 96-pin female, gold plated, meets IEC standard 603-2-IEC-C096-F

The iSBC PKG/902 and iSBC PKG/903 iLBX II
backplanes use a 6 layer printed circuit board (PCB)
with separate power and ground layers and a signal
lead routing scheme which minimizes ringing, 9rOSStalk, and capacitive loading on the bus. Mounted on
the PCB are two (is\3C PKG/902) or three (iSBC
.. PKG/903) 96 pin DIN connectors, one 10-pin BITBUS connector, terminating resistors, decoupling
capacitors, and power terminals. The resistors and
capacitors are mounted into sockets, and all parts
are press-fit into the backplane. The PCB is UL recognized for flammability.

BITBUS: 10-pin male, gold plated, T&B Ansley 6091012M, or equivalent
Constructed Method: Six layer backplane with separate VCC and Ground layers
All connectors, power terminals, and resistor/cap~citor
sockets are press-fit into the
backplane
Mounting Hole Location: See Figure 1
Operating Environment: 0·C-70·C ambient temperature; 0% to 90% relative
humidity, non-condensing;
o ft.-10,OOO ft. altitude

Single In-line Package (SIP) style resistors are used
to terminate all address, clock, data, and control
lines. Each termination consists of two resistors
which connects the line to + vee and ground. Different size resistors are used according to the type
4-6

inter

iSBC® PKG/902 ISBC® PKG/903 BACKPLANES

Electrical
Backplane Electrical
Characteristics and
Line Terminations:

REFERENCE MANUAL
Per Intel MULTIBUS II
specification 146077,
Sec. II, iLBX II

MULTIBUS II Cardcage Assembly and iLBX Backplane User's Guide, PIN 146709-001 (not supplied)

ORDERING INFORMATION

Power Connections
Type: Screw terminal block: AMP PIN 55181-1;
Winchester PIN 121-25698-2; or equivalent
Mating Connection: No. 6 locking spade or ring
tongue lug
Quantity: 2(VCC, Ground)
Current Rating: iSBC PKG/902: 12 amps; iSBC
PKG/903: 18 amps (Power and
Ground)
Maximum Current
6 amps (over the iLBX II backAvailable Per Slot:
plane)

Part Number
iSBC PKG/902
iSBC PKG/903

4-7

Description
2 slot iLBX II Backplane
3 slot iLBX II Backplane

SYP 500
MULTIBUS® II SYSTEM CHASSIS

•
•
•

•
•
•
•

Full Enclosure MULTIBUS@ II Design
Development Tool or OEM Chassis
Office and Industrial Applications
3 Full Helght/6 Half Height Peripheral
Bays

8 Slot MULTIBUS@ II Cardcage
Assembly
3 Slot ILBXTM II Backplane
535 Watt Power Supply
Fully Tested: Low-Noise, Shockl
Vibration and Electrostatic Resistant

The SYP 500 System Chassis is a MULTIBUS II design tool enabling product designers to begin work immediately on MULTIBUS II development projects. It is also ideal for OEM applications. Two front mounted LEOs
indicated "Power On" and "Status" (PSB busy) while a keyswitch provides external "reset" capabilities for the
chassis. The voltage selector, power-on switch and cardcage opening are located in the rear of the chassis.
Three peripheral bays, two of which are accessible from the front of the chassis, support up to three industry
standard 5.25" full-height or six half-height peripherals. An eight slot cardcage, Parallel System Bus and iLBX
II backplane assembly are integrated with a 535 Watt power supply.

. intel'
II111111111111111111
!Ii
'" .

-iii'"

-4

...

280153-1

4-8

October 1989
Order Number: 280153-002

inter

SYP500

The chassis has been fully tested to ensure low-audible noise emission, resistance to electrostatic discharge and resistance to appropriate levels of vibration and shock in both office and industrial environments.

FUNCTIONAL DESCRIPTION
Mechanical Features
Intel's SYP 500 MULTIBUS II Chassis is a full enclosure, off-the-shelf design development tool and
OEM chassis. Designers and systems integrators
can integrate their MULTIBUS II board set with tape,
Wini or floppy peripherals into a complete system.
The SYP 500 has three full-height 5.25" peripheral
bays. Peripheral power cables, office and industrial
environment cooling, and peripheral mounting
brackets for industry standard full- or half-height peripherals are provided with the chassis. Access via
the front panel allows two of the bays to be configured with removable media peripherals e.g. tape and
floppy drives.

SPECIFICATIONS:
Electrical Parameters
Maximum Amperage:
Voltage

+5V
+12V
-12V

This chassis includes an eight-slot MULTIBUS II
cardcage assembly with 0.8" centers (slot width).
The cardcage is made with heavy duty endplates
and extra-wide support extrusions to ensure adequate support for most applications. For industrial
applications, this chassis is mountable into any 19"
vertical rack.

Current

75A
10A
2.5A

Designed to r:neet: UL 478
CSA C22.2 No. 154
FCC Class B
VDE Level B
IEC 435

Two backplanes are installed in the cardcage assembly: the system backplane and the auxiliary
backplane. The system backplane is the Parallel
System Bus (iPSB) for communications between up
to eight MULTIBUS II boards. This backplane utilizes
separate power and ground planes and fully terminates all Signal lines. The auxiliary backplane, on the
other hand, provides direct high speed interconnection between a processor board and memory
boards. It contains three iLBX slots. One of these
slots has a 10-pin BITBUS connector that serves as
a serial interface for any iSBX 344 BITBUS controller
board installed in the system. This cardcage conforms to the published MULTIBUS II specification.

Operational Parameters
AC Power Input:

90-132 VAC or
180-264 VAC at
47 HZ-63 Hz
Operating Temperature Range: 1Q°C to 55°C
Storage Temperature:
-40°C to 60°C
Operation Humidity:
10% to 85% relative, non-condensing

Electrical Features
The SYP 500 chassis has a 535 Watt switching power supply with selectable AC power input of 115V or
220V at 47 HZ-63 Hz. The AC input power is externally selectable with a slide switch mounted on the
rear of the chassis. A power distribution board is installed in the chassis to allow easy connection to all
peripheral bays through six plugs mounted on the
power distribution board.

4-9

iSBC® CSM/001 *
CENTRAL SERVICES MODULE

•

iSBC® CSM!001 Central Services
Module Integrates MULTIBUS® II
Central System Functions on a Single
Board

•
•

MULTIBUS® II Parallel System Bus
Clock Generation for all Agents
Interfaced to the MULTIBUS II PSB Bus

•
•

System-wide Reset Signals for Powerup, Warm Start, and Power Failure!
Recovery
System-wide Time-out Detection and
Error Generation
Slot 1.0. and Arbitration 1.0.
Initialization

•

MULTIBUS II Interconnect Space for
Software Configurability and
Diagnostics

.. Built-In Self Test (BISn Power-up
Diagnostics with LED Indicator and
Error Reporting Accessible to Software
via Interconnect Space

•
•
•

General Purpose Link Interface to
Other Standard (MULTIBUS I) or
Proprietary Buses
Time-of-day Clock Support with Battery
Back-up on Board
Double-high Eurocard Standard Form
Factor, Pin and Socket DIN Connectors

The iSBC CMS/001 Central Services Module is responsible for managing the central system functions of clock
generation, power-down and reset, time-out, and assignment of 1.0.s defined by the MULTIBUS II specification. The integration ot these central functions in a single module improves overall board area utilization in a
multi-board system since these functions do not need to be duplicated on every board. The iSBC CSM/001
module additionally provides a time-ot-day clock and the general purpose link interface to the other standard
(MULTIBUS I) or proprietary buses.

280070-1

"The iSBC" CSM/001 is also manufactured under product code piSBC" CSM/OOI by Intel Puerto Rico, Inc.

4-10

September 1989
Order Number: 280070-003

iSBC CSM/001 MODULE

system wide time out detection and error-generation.
The System Interconnect Space subsystem controls
1.0. initialization and software configurable interconnect space. The Link Board interface subsystem
provides an interface to the MUlTIBUS I Link board
or links to other buses. The last two subsystems are
of the Time-of-Day clock and the PSB bus interface.
These areas are illustrated in Figure 2.

FUNCTIONAL DESCRIPTION
Overall
The iSBC CSM/001 Central Services Module integrates MUlTIBUS II central system functions on a
single board. Each MUlTIBUS II system requires
management of these central system functions as
defined in the MUlTIBUS II specification. Figure 1
illustrates a typical multiprocessing MUlTIBUS II
system configuration. To perform its central system
functions, the iSBC CSM/001 Central Services Module has a fixed slot 1.0. and location in the backplane. The iSBC CSM/001 board additionally provides an interface to the MUlTIBUS I Link board and
a time-of-day clock.

CENTRALIZED SYSTEM-WIDE
CONTROL SUBSYSTEM
Parallel System Bus Clock Generation
The CSM generates the Parallel System Bus clocks.
The Bus Clock (BClK*) 10 MHz signal and the Constant Clock (CClK*) 20 MHz signal are supplied by
CSM to all boards interfaced to the Parallel System
Bus. These boards use the Bus Clock 10 MHz signal
for synchronization, system timing, and arbitration
functions. The Constant Clock is an auxiliary clock.
The frequency of the Bus Clock and Constant Clock
can be halved via jumpers for diagnostic purposes.

Architecture
The iSBC CSM/001 board is functionally partitioned
into 6 major subsystems. The Central System Wide
Control subsystem includes MUlTIBUS II PSB bus
clock generation and system wide reset signal generation. The Time-Out Control subsystem provides

280070-2

Figure 1. Typical MULTIBUS® "System Configuration

280070-3

Figure 2. Block Diagram of ISBC® CSM/001 Board

4-11

iSBC CSM/001 MODULE

type, so that this information is available to the system software. The CSM software configurable interconnect space allows write 'operations to support
board configuration and diagnostics under software
control. The CSM also uses interconnect space for
system wide functions such as providing a time/date
record (from time-of-day clock), software access to
diagnostics and software control of the system wide
functions.

Reset Control and Power-Faill
Recovery
The CSM sends a system-level reset/initialization
signal to all boards interfaced to the Parallel System
Bus. The CSM assigns slot 1.0. and arbitration 1.0. to
these boards during this initialization process. It provides this signal upon pressing of the reset switch,
restoration of system power or a software request
for reset received via the CSM interconnect space.
The reset switch may be jumper-configured to cause
a power-up or warm reset, with cold reset the default
configuration. The reset switch is located on the
front panel. Additionally, 'warm reset and cold reset
signals can be input through the P2 connector.

BUILT-IN-SELF-TEST (BIST)
DIAGNOSTICS
Self-test/diagnostics have been built into the heart
of the MULTIBUS II system. These confidence tests
and diagnostics improve reliability and reduce manufacturing and maintenance costs. LED 1 (labeled
BIST) is used to indicate the status of the Built-InSelf-Test. It is turned on when the BIST starts running and is turned off when the BIST completes successfully: In addition, all error information is recorded in· interconnect space so it is accessible to software for error reporting.

The CSM power supply interface is accomplished
via the ACLO input of the P2 connector. ACLO is an
open c;:ollector input from the power supply which
provides advance warning of imminent power fail. If
battery backup is not required, a jumper is provided
on the CSM to disable the power fail signal ACLO.

TIME-OUT SUBSYSTEM

The Built-In-Self-Tests performed by the on-board
microcontroller at power-up or at software command
are:

The TIMOUT* (Time-Out) signal is provided by the
CSM whenever it detects the failure of a module to
complete a handshake. This TIMOUT* signal is received by all boards interfaced to the PSB bus and
may be disabled via the interconnect space.

1. PROM Checksum Test-Verifies the contents of
the 8751 microcontroller.
2. RAM Test-Verifies that each RAM location of
the 8751 microcontroller may store O's and 1's by
complementing and verifying twice each RAM location.

INTERCONNECT SUBSYSTEM
The CSM Interconnect subsystem provides arbitration 1.0., and slot 1.0. initialization, software configurable interconnect space, and on-board diagnostics
capability.

3. Real Time Clock Chip RAM Test-Verifies that
reads and writes to the RAM locations on Real
Time Clock Chip are functional.
4. Real Time Clock Test-Reads and writes all RAM
locations of the RTC chip. Not run at power-up
due to destructive nature.

At reset, the CSM supplies each board interfaced to
iPSB bus with its slot 1.0. and its arbitration 1.0. The
slot I. D. assignment allows user or system software
to address any board by its physical position in the
backplane.

5. Arbitration/Slot 1.0. Register Test-Verifies that
arbitration and slot 1.0.s can be read and written
from on-board.

The interconnect space has both read-only and soft- .
ware configurable facilities. The read-only registers
hold information such as vendor number and board

4-12

6.8751 Status Test-Verifies that input pins of the
8751 are at correct level.
7. Clock Frequency Test-Tests accuracy of 'Real
Time Clock to 0.2% against bus clock.

inter

Isec CSM/001 MODULE

and provides a memory and I/O access window to
MULTIBUS I from the MULTIBUS II Parallel System
Bus. Only one iSBC LNK/001 board can be connected to the iSBC CSM/001 module.

CSM LINK INTERFACE
The CSM Link Interface and the MULTIBUS I iSBC
LNK/001 board provides a bridge between MULTIBUS I and MULTIBUS II systems. Hybrid systems
can be built for development or target. The CSM
Link Interface uses the P2 connector on the iSBC
CSM/001 module for transferring commands and
data from MULTIBUS II to a MULTIBUS I Link board.
The MULTIBUS I Link board (iSBC LNK/001) is purchased separately from the iSBC CSM/001 board
and includes the cable which connects the iSBC
CSM/001 board and the MULTIBUS I Link board
(see Figure 3).

TIME-OF-DAY CLOCK SUBSYSTEM
The Time-Of-Day Clock subsystem consists of a
clock chip, battery, and interface circuitry. The clock
provides time keeping to 0.01 % accuracy of fractions of seconds, seconds, minutes, hours, day, day
of week, month, and year. This information is accessible via the interconnect space. The battery backup for the clock chip provides 2 years of operation.

The CSM Link Interface supports 8- or 16-bit transfers via a 16-bit address/data path. The iSBC
LNK/001 board resides in the MULTIBUS I system

280070-4

Figure 3. iSeC® CSM/001 Link Interface

SPECIFICATIONS

Link Cable

System Clocks

The Link cable uses a 64-conductor ribbon cable for
interconnecting the CSM board to the Link Board.
The maximum length for the cable is 1 meter.

BCLK* (Bus Clock)

10MHz

CCLK* (Constant Clock)
LCLK* (Link Clock)

20 MHz
10 MHz

Interface Specifications
Location
P1
P2

Jumper option available to divide these frequencies
in half

4-13

Function
PSB Bus
Link and Remote
Services

Part #
603-2-1 EC-C096F
603-2-IEC-C064-F

inter

Isec CSM/001 MODULE

PHYSICAL DIMENSIONS

BATTERY CHARACTERISTICS

The iSBC CSM/001 board meets all MULTIBUS II
mechanical specifications as presented in the MULTIBUS II specification.

3V nominal voltage; capacity of 160 milliamp hours
minimum.

Double-High Eurocard Form Factor:

BATTERY DIMENSIONS

Depth:
Height:
Front Panel Width:
Weight:

Outside dimension
Height

220 mm. (8.7 in.)
233 mm. (9.2 in.)
20 mm. (0.78 in.)
4820 gm. (16.5 oz.)

20 mm-23mm
1.6 mm-3.2 mm

REFERENCE MANUALS
iSBC CSM/001 Board Manual (#146706-001)

ENVIRONMENTAL REQUIREMENTS
Temperature: (inlet air) at 200 LFM airflow over
boards
Non-operating: - 40 to + 70·C
Operating:
0 to + 55·C
Humidity:
Non-operating: 95% RH @ 55°C
Operating:
90% RH @ 55°C

Manuals may be ordered from any Sales Representative, Distributor Office, or from the Intel Literature
Department, 3065 Bowers Ave., Santa Clara, CA
95051.

ORDERING INFORMATION
Part Number
iSBC CSM/001

POWER REQUIREMENTS
Voltage (volts)

Current (amps)

+5
+5VBB

6A(max.)
1A (max.)

4-14

Description
MULTIBUS II Central Services
Module

MULTIBUS®II CENTRAL SERVICES MODULE*

COST REDUCED CENTRAL SERVICES MODULE
The iSBC@ CSM/002 module is a small, surface mount circuit board which performs all
central service module (CSM) functions as required by the IEEE/ANSI1296 MULTIBUS@ "
specification. This credit card sized module mounts on a compatible base board such as
the iSBC 386/258, iSBC 386/133, or iSBC 4861125DU single board computer. The
combined host board and CSM module require only one card slot. The small size and
high functionality of the iSBC CSM/002 module is achieved by taking advantage of silicon
support for CSM functions on the MPC (Message Passing Coprocessor) bus interface
component. This module reduces system cost while remaining software compatible with
the previous iSBC CSM/001 board.
'

FEATURES
• Full IEEE/ANSI1296 Compliance for
CSM Functions:
-Arbitration and Slot 10 Initialization
- BCLK and CCLK Generation
- PSB Bus Timeout Monitoring
-Reset Sequencing for Warm and Cold
Resets
-Power Fail Indication and Recovery
• Software compatible with the iSBC
CSM/001 board, but saves a card slot

• Battery Backup Time-of-day Clock
• Slot 0 Detection Circuit
• Clock Based Alarm Function for
Periodic Interrupt
• 28 Bytes Non-volatile RAM
• Chassis 10 for Crate-to-Crate
Addressing
• Low Battery and Oscillator Failed
Warnings

• The MULTI BUS II Central Services Module, ISBCCSM002 (s also manufactured under product code pSBCCSM002 by Intel of Puerto RICO, Inc
and sSBCCSMOOS by Inlel Singapore, Ltd

in+-I·_ _ _ _ _ _ _ _-----::-~

• lae

4-15

September, 1989
Order Number 280694-001

FEATURES
WHAT IS A CENTRAL SERVICES
MODULE?
The Central Services Module centralizes a variety of
bus management tasks in a Multibusil> 11 based
system, reducing system overhead:
• Sequencing of reset signals on the PSB backplane.
• Assignment of card slot and arbitration·IDs.
• Supplies a 10 MHz. system-wide clock signal
(BCLK).
'
• Monitors the PSB bus for time outs, and signals a
bus error when a parity error is detected.

FULL IEEE 1296 COMPLIANCE
The iSBC CSM/002 module meets all timing
requirements for Central Services Module functions
according to the MULTIBUSiI> II specification. This
ensures reliable, clean system clock signals and
correct reset sequencing for system power-on, powerfail, and front panel warm and cold resets. When
used in a system where the power supply is capable
of generating an ACLO ,indicator, the CSM module
will signal a non-maskable interrupt to the host CPU
shortly before the power goes down,

COMPACT SIZE: NO LONGER REQUIRES
A SEPARATE CARD SLOT
The iSBC CSM/002 module reduces total system cost
by supporting all CSM functions in an inexpensive,
credit card sized module, This module mounts
component side down onto compatible baseboards
like the iSBC 386/258, iSBC 3861133, or iSBC
4861125DU single board computers which have builtin CSM connectors, The combined host board and
CSM module occupy only one card slot The iSBC
CSM/002 module is fully software compatible with the
earlier iSBC CSM/001 board, and is a direct
replacement. Only one CSM module is required per
system,

PROGRAMMAtiC INTERFACE
All access to the above functions is via a set of
function records contained in interconnect address
space, These registers are resident on the host in slot
zero, but are accessible to any agent on the PSB,
This allows other boards to query reset status, bus
errors, system time, NVRAM contents, and many
other centralized functions.

WORLDWIDE SUPPORT AND SERVICE
Assistance in developing and supporting MULTIBUStI>
II applications is available through Intel's network of
field application engineers, system engineers,
customer training centers and service centers.

INTEL QUALITY-YOUR GUARANTEE
The iSBC CSM/002 module is designed and
manufactured in accordance with Intel's high quality
standards, Quality is verified by rigorous testing in
Intel's state-of-the-art Environmental Test Laboratory.

ORDERING INFORMATION
ORDER CODE: SBCCSM002
DOCUMENTATION:' iSBC CSM/002 Hardware
Reference Manual PIN
459706-001
AP NOTE: "Design of a Cost Reduced Central
Services Module for MULTIBUStI> II"
For more information or the number of your nearest
Intel sales office, call 800-548-4725 (good in the U.S,
and Canada).

TIME OF DAY CLOCK FUNCTIONS
A battery backed up time-of-day clock is supplied on
the iSBC CSM/002 module. This feature is software
compatible with the existing Time and Date
commands supported by various Intel supplied
operating systems, In addition a new periodic alarm
function is now available. This feature allows the user
to generate an interrupt to the local processor based
on the system clock. Intervals can be selected
ranging from one second to one year, One example
of how to use this might be to schedule a disk
backup to tape at 1:00am on Friday of each week,

NON-VOLATILE RAM FUNCTIONS
A two byte chassis 10 is stored in an interconnect
register in order to identify a particular backplane
segment in a network which consists of a large
number of nodes distributed in multiple chassis. In
addition, there are 28 bytes of user definable nonvolatile RAM available, One application might be for a
bootstrap password to prevent unauthorized access
to a system,
4-16

iSBC® LNK/001 * BOARD
MULTIBUS® II TO MULTIBUS® I LINK BOARD
•

Development Vehicle Making
MULTIBUS® I iSBC® Boards Accessible
to MULTIBUS® II Board Designers

• 32K Bytes of MULTIBUS® I 1/0 Mapped
into MULTIBUS® II 1/0 Space
Configurable from MULTIBUS® II
Interconnect Space

• On Board 128K Byte Dual Port DRAM
Memory
•

16M Bytes of MULTIBUS® I Memory
Mapped into MULTIBUS® II Memory
Space Configurable from MULTIBUS® II
Interconnect Space

•

Conversion of MULTIBUS® I Interrupts
to MULTIBUS® II Interrupt Messages

•

MULTIBUS® I Form Factor Board

• Connects to MULTIBUS® II Central
Services Module (iSBC CSM/001 Board)
via a 3 Foot Flat Ribbon Cable

The iSBC® LNK/001 board maps MULTIBUS I memory and 1/0 space into the MULTIBUS II iPSB bus and
converts MULTIBUS I interrupts into MULTIBUS II interrupt messages. Up to 16M Bytes of MULTIBUS I
memory and up to 32K Bytes of MULTIBUS Ilia is addressable from MULTIBUS II through the iSBC LNK/001
board. Additionally. 128K Bytes of dual port DRAM memory resides on the iSBC LNK/001 board for use by
both MULTIBUS I and MULTIBUS II systems. MULTIBUS II OEM product designers can now speed hardware
and software development efforts by using the iSBC LNK/001 board to access standard or custom MULTIBUS I products.

280135-1

'The ,SSC" LNK/OOI is also manufaclured under product code p,SBC" LNK/OOI by Intel Puerto Rico. Inc.

4-17

September 1989
Order Number: 280135-1103

inter

iSBC® LNK/001

MULTIBUS I system. A MULTIBUS II agent requesting a memory transfer involving the iSBC LNK/001
board is directed through the CSM to the iSBC
LNK/001 Dual Port memory or a MULTIBUS I slave.
If the access address is within the MULTIBUS II Dual
Port window, the transaction is acknowledged by the
iSBC LNK/001 board and returned to the MULTIBUS II iPSB through the CSM. In the.event the address is outside the MULTI BUS II Dual Port window,
the transaction is directed to the MULTIBUS I system. Here the iSBC LNK/001 board enters arbitration for the MULTIBUS I system bus to complete the
requested transaction. Once the iSBC LNK/001
board is the owner of the MULTIBUS I system bus,
data is transferred to or from the iSBC LNK/001
board/Central Services Module connection. The
MULTIBUS I slave acknowledges the transfer and
the iSBC LNK/001 board passes the acknowledge
on through the Central Services Module to the MUL- .
TIBUS II iPSB.

GENERAL DESCRIPTION
The iSBC LNK/001 board makes MULTIBUS I products accessible to MULTIBUS II designers. The
iSBC LNK/001 board resides in the MULTIBUS I
system and connects to the Central Services Module (iSBC CSM/001 board) via a 3 foot flat ribbon
cable. The ribbon cable connects the P2 connector
of the iSBC LNK/001 board to the P2 connector on
the Central Services Module. The iSBC LNK/001
board supports:
a. 128K Bytes of Dual Port DRAM,
b. 16- and 24-bit addressing into 16M Bytes of MULTIBUS I memory with 8- and 16-bit data paths,
c. 8- and 16-bit addressing into 32K Bytes of MULTIBUS I I/O with 8- and 16-bit data paths,
d. MULTIBUS I interrupt to MULTIBUS II interrupt
message conversions of up to eight levels of non
bus-vectored interrupts via an 8259A programmable interrupt controller, and

MULTIBUS II I/O operations are always directed to
the MULTIBUS I I/O slaves and consequently require arbitration for the MULTIBUS I system bus.

e. initialization tests and Built-In-Self-Test (BIST) using interconnected address space.

APPLICATIONS

INTERCONNECT MAPPING

The primary application of the iSBC LNK/001 board
Is in the design development environment. The iSBC
LNK/001 board allows designers to start their development efforts by leveraging existing MULTIBUS I
products or to begin modular design efforts and preserve investments in custom products. In either
case, the use of leverage with existing MULTIBUS I
hardware and software allows designers to begin
their MULTIBUS II product designs.

The function record of the iSBC LNK/001 board, a
function record within the Central Services Module
interconnect template, appears as a board within a
board (see Table 1). The actual iSBC LNK/001
board configuration is done through unique interconnect registers using the same slot 10 as the Central
Services Module. The iSBC LNK/001 function record begins at an offset of 256 from the start of the
CSM template and the EOT (End Of Template) byte
is attached as the last function of the iSBC LNK/001
function record.

MEMORY AND 1/0 READ/WRITE
SEQUENCE

Dual Port 128K Byte DRAM Memory

The iSBC LNK/001 board establishes a master/
slave relation between a MULTIBUS II system and a

A dynamic RAM Dual Port, resident on the iSBC
LNK/001 board, provides a 128K Byte media for

280135-2

Figure 1. Sequence Diagram
4-18

intJ

iSBC® LNK/001

dress register value. This memory block, configurable on any 64K Byte boundary within the MULTIBUS
I memory address space, is set via interconnect accesses to the iSBC LNK/001 function records from
the MULTIBUS II system (see Table 1). The first
16M Bytes of MULTIBUS II memory space can be
mapped in the 16M Bytes of MULTIBUS I memory
address space (see Figure 3).

MULTIBUS I and MULTIBUS II agents to pass data
efficiently. With both buses sharing the Dual Port
memory the need for the MULTIBUS II system to
continuously arbitrate for MULTIBUS I system access is eliminated. Consequently, each bus can continue operating at its respective speed when accessing the iSBC LNK/001 Dual Port memory.

MULTIBUS® I Memory Addressability

MULTIBUS® I 1/0 Addressability

The MULTIBUS I system views the iSBC LNK/001
Dual Port as a contiguous 128K Byte memory block
mapped into the 16M Bytes of MULTIBUS I memory
address space starting at the Dual Port Start Ad-

Up to eight 4K Byte blocks of MULTIBUS II I/O
space can be mapped into MULTIBUS I 1/0 space

Table 1. Function Record Overview iSBC® LNK/001 Board
Offset

. Description

Offset

Description

0-255

iSBC CSM/001 Header and
Function Record
Board Specific Record Type
Record Length
Vendor 10, Low Byte
Vendor 10, High Byte
Link Version Number
Hardware Revision Test Number
Link General Status
Link General Control
Link BIST Support Level
Link BIST Data In
Link BIST Data Out
Link BIST Slave Status
Link BIST Master Status
Link BIST Test 10
MBI Dual Port Start Address

271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288

MBI Dual Port End Address
MBII Dual Port Start Address
MBII Dual Port End Address
MBII Memory Start Address
MBII Memory End Address
1/0 4K Segment Control
MBllnterrupt Enable
Link Interrupt 0 Destination Address
Link Interrupt 1 Destination Address
Link Interrupt 2 Destination Address
Link Interrupt 3 Destination Address
Link Interrupt 4 Destination Address
Link Interrupt 5 Destination Address
Link Interrupt 6 Destination Address
Link Interrupt 7 Destination Address
Interrupt Source Address
Link Status Register
EOT (End of Template) .

256
257
258
259
260
261
262
263
264
265
266
267
268
269
270

MULTIBUS" II

:::>

BUS AND

MESSAGE
CONTROL
LOGIC

LINK
DUAL

PORT
RAM

1-----1

I-----.!!!

~------~

280135-3

Figure 2. Link Board Dual Port Drawing
4-19

inter

iSBC® LNK/001

MULTIBUS~'II
4GB
MBII
MEM
MULTIBUS@I

16MB! -_-_- .....~,....,....I16MB

- -

DUAL

PORT

~,,",,""""" DUAL

-"""""",,...,..,..-1 PORT

---_"""';..0;...'-10
MEMORY MAPPING
~'?"T"'" 64KB

which the interrupt message is being sent. Each of
the eight MULTIBUS I interrupt lines can be programmed to generate a unique MULTIBUS II destination address. These destination addresses are initialized through interconnect space by programming
the iSBC LNK/001 Interrupt Destination Address
Registers. The message source address is also configurable via interconnect space by writing to the Interrupt 0 Source Address Register with a base value.
Once the base value of source Address 0 is established, Source Address 1 through 7 are set for incrementing values by the 8751A interconnect processor. The iSBC LNK/001 board recognizes MULTIBUS II Negative Acknowledge agent errors
("NACK") and performs an automatic retry algorithm.

,/
,/

32KB~

Initialization Tests and BIST
_~--.32KB

Self test and diagnostics have been built into the
MULTIBUS II system. The BIST LED is used to indicate the result of the Built-In-Self-Test and turns on
when BIST starts running and turns off when it has
successfully executed. BIST test failure information
is recorded in the interconnect space and is accessible to software for error reporting.

./
,/

o
1/0 MAPPING

280135-4

Figure 3. MULTIBUS® I Memory
and I/O Mapping Diagram

PHYSICAL CHARACTERISTICS

(see Figure 3). MULTIBUS II 1/0 accesses must be
from 32K Byte to 64K Byte in order to be mapped
into MULTIBUS I 1/0 address space. These blocks
are specified through an interconnect access to the
"1/0 4K Segment Control" register (see Table 1).
Each bit in the register represents a 4K Byte block of
1/0 addresses. When a bit (or bits) is set, the 4K
Byte block of MULTIBUS II 110 space represented
by that bit will be dedicated to MULTIBUS I 110
space.

Form Factor
The iSBC LNK/001 board is a MULTIBUS I form factor board residing in a MULTIBUS I system. Physical
dimensions are identical to all standard MULTIBUS I
boards.

Connection to MULTIBUS® II Bus
The iSBC LNK/001 board connects to the iSBC
CSM/001 board in the MULTIBUS II system via a 60
pin conductor flat ribbon cable. The physical connection is made on the P2 connector of both the
iSBC LNK/001 board and the iSBC CSM/001 board.
The cable termination requirements and DC requirements for the signal drivers and receivers are detailed in the iSBC CSM/001 USERS GUIDE, Section
6.6.4. The maximum length of the cable is 3 feet.
The cable and the connectors are shipped unassembled to allow user flexibility.

Interrupt to Message Conversion
As the iSBC LNK/001 board receives non-bUS vectored interrupts from the MULTIBUS I system, the
on-board 8259A programmable interrupt controller
(PIC) prioritizes the MULTIBUS I interrupts and initiates the MULTIBUS II unsolicited interrupt message
generation process. Up to 8 levels of non-bus vectored interrupts are supported by the iSBC LNK/001
board.
The iSBC LNK/001 board generates the MULTIBUS
II interrupt messages and is the Interrupt Source.
The iSBC LNK/001 board is assigned a Source 10
through interconnect space when the MULTIBUS II
system is powered up or when the user programs
the source 10 register via interconnect space. The
Interrupt Destination is the MULTIBUS II board to

SOFTWARE SUPPORT
To take advantage of iSBC LNK/001 Dual Port architecture, existing software device drivers may require modification. Device driver changes depend on
the specific application and vary in complexity depending upon the device driver.
4-20

intJ

ISBC® LNK/001

SPECIFICATIONS

ENVIRONMENTAL REQUIREMENTS

16- and 24-bit Address Paths
8- and 16-bit Data Paths
Block transfers are not supported

Temperature: Inlet air at 200 LFM airflow over
boards
Non Operating: -40°C to +75°C
Operating: O°C to + 55°C
Non Operating: 0 to 95% RH @ 55°C
Humidity:
Operating: 0 to 95% RH @ 55°C

Cable Characteristics

POWER REQUIREMENTS

The cable is a 60 pin conductor flat ribbon cable with
a maximum length of 3 feet. The P2 connector to the
iSBC LNK/001 board is a 30160 pin board edge
connector with 0.100" pin centers, KEL-AM Part
Number RF30-2853-5. The connector to the P2 DIN
connector on the iSBC CSM/001 board is 3M Part
Number 3338-000.

Voltage: + 5V
Current: 7.14 Amps

Word Size

REFERENCE MANUALS
iSBC LNK/001 Users Guide (#148756-001)
iSBC CSM/001 Users Manual (#146706-001)

Interface Specifications
Location
P1
P2

Manuals may be ordered from any Sales Representative, Distributor Office, or from the Intel Literature
Department, 3065 Bowers Ave., Santa Clara, CA.
95051.

Function
MULTIBUS IEEE 796 System Bus
Cable connection to P2 connector of
iSBC CSM/001 board

ORDERING INFORMATION

PHYSICAL DIMENSIONS

Part Number Description
iSBC LNK/001 MULTIBUS II to MULTIBUS I iSBC
LNK/001 Interface Board

The iSBC LNK/001 board meets all MULTIBUS I
mechanical specifications as presented in the MULTIBUS I specification.
Depth: 17.15 cm (6.75 in.)
Height: 1.27 cm (0.50 in.)
Front Panel Width: 30.48 cm (12.00 in.)
Weight: Estimated 565 g (20 oz.)

4-21

MULTIBUS® II
HIGH PERFORMANCE SBC
GENERAL PURPOSE TEST FIXTURE (GPTF)
• Single Board Computer Tester for
MULTIBUS@ " Boards In a Systems
Environment
• Tests up to Four MULTIBUS " Boards
Simultaneously in a Range from
Ambient Temperature to 70·C
- Voltage and Temperature Margins
are Software Controlled
• Multiprocessor, Multltestlng Functional
Tester with Totally Automated Test
Sequence, Requiring Minimum Human
Intervention
• Po~erful Command Language for
Troubleshooting and Evaluation

• One STBL (System Test Board Level)
Test is Included. Additional Test
Programs are Available for Intel
MULTIBUS " Boards
• GPTF Includes Video Monitor for Error
Message Display and Status of Testing,
Also, a Comprehensive Installation
Guide and Users Manual
• Bus Drawer Feature on P2 Connector
Allows User Flexibility to Test Boards
with Different Types of P2 Interfaces
• Available in Either USA, Japan or
International Power Configuration
• Safety Features Including Thermal Cut
Out at 90·C

280189-1

4-22

October 1988
Order Number: 280189..Q02

MULTIBUS® II GPTF

The Hot Box Test Chamber has slots for testing
one to four UUT's simultaneously. Both the + 5V
and temperature can be varied by the Control Computer (or the user) to test the boards in a worst case
condition. The + 5V voltage can be margined
± 10%, and the temperature can be raised from
room temperature to 70·C.

TESTER OVERVIEW
The MULTIBUS II General Purpose Test-Fixture
(MULTIBUS II GPTF) is a state-of-the-art high performance tester used to test MULTIBUS II boards in
a typical systems environment. The System Test
Board Level or STBL, as it is usually referred to, is
done using the MULTIBUS II GPTF. The STBL is
used to validate that the iSBC board will perform in a
system environment under a variety of temperature
and voltage conditions. The MULTIBUS II GPTF is a
fully automated tester with minimum operator intervention required. It can test from one to four boards
of the same type at a time. A full range of keyboard
commands are available for troubleshooting. The
human interface is through the Front Panel and the
CRT terminal. The MULTIBUS II GPTF requires the
use of a Televideo 955 terminal which is included
with the GPTF order.

The Control Computer System is located in the
rear of the GPTF and is a MULTIBUS I based system. Its function is to control and manage the Test
Computer System. This system controls the AC
power to the Test Computer System, has the capability to margin the DC voltages to the UUT, controls
the heat chamber heater coils, reset and interrupt
lines to the iSBC CSM/001 board, and controls the
110 to the CRT video display, front panel, and the
secondary storage. The Control Computer contains
an 8-slot MULTIBUS I backplane and five iSBC
boards.

The users manual is written at the operator's level
and thus does not require a technician to perform
tests. The users manual is written in two parts; operator's instructions and technician's troubleshooting
section. An installation guide is also furnished.

The secondary storage consists of a 3.5" , 40 Mbyte
winchester hard drive and a 5.25", 48 TPI floppy
drive. Both iRMX86™ and PC-DOSTM format floppy
diskettes can be used. The hard drive and the floppy
drive are controlled by the Intel iSBC 214 Peripheral
Controller board. Additional 3.5" and 5.25" Peripheral Controller board. Additional 3.5" and 5.25" peripheral bays are designed in for future Intel use.

The MULTIBUS II GPTF does not require any special Test EPROMs to do the STBL. The STBL can
be loaded and stored in the hard drive using either
the floppy drive or downloaded from an Intel Series
III Development System. Once the STBLs are loaded into the hard drive, reconfiguration time (when
testing different types of boards) is typically limited
to exchanging the bus drawer. The STBLs for the
most part use the Built-In Self Tests (BISTs) which
are part of the MULTIBUS II Board Product Firmware, to test the Unit Under Test (UUT).

Variable P2 Interface capability in the MULTIBUS II
architecture allows for variable use of the P2 connector on iSBC boards. The iLBXTM II connector is
used on some boards, like the iSBC 286/100 and
the iSBC MEM/3XX boards, SCSI is used on boards
like iSBC 386/258 etc. The MULTIBUS II GPTF has
the bus drawer feature in the Test Computer System
to support the variable P2 interface. Each bus drawer is designed for a specific P2 interface. For example, the CODE1 bus drawer, shipped with the GPTF,
supports iLBX II. The bus drawers are easy to install-slide it in and tighten the two thumb screws.
Only two types are shipped with the product. All the
parts of the bus drawer are generic except the P2
connector itself. Each bus drawer is coded so that it
can be recognized by the STBL software.

The MULTIBUS II GPTF adheres to MULTIBUS II
architecture and follows the Intel Interconnect Interface Specification (liS) and the Intel Initialization and
Diagnostics eXecutive (IDX).

HARDWARE OVERVIEW
The MULTIBUS II GPTF is uniquely designed for
ease of maintainability with three enclosures. The
front enclosure is the heat chamber that houses the
UUTs. Behind the heat chamber are the two computer systems; the Test Computer System and the
Control Computer System. Each system has its own
power supply.

SOFTWARE OVERVIEW
The MULTIBUS II GPTF runs on iRMX 86 software
specially configured for the GPTF. The operating
system resides on the hard drive Control Computer
System. The DIR command will assist in locating the
various directories on the hard drive.

The Test Computer System, which is MULTIBUS II
based, is located immediately behind the heat chamber. It is the slave system to the Control Computer
System. Its function is to perform the testing and
report test status back to the Control Computer System. The Test Computer System contains three
HOST MULTIBUS II boards which always reside in
the GPTF.

The Tester Control Program (TCP), also iRMX 86based Operating System, resides on the hard drive
and runs on the Control Computer System (iSBC

4-23

inter

MULTIBUSI!> II GPTF

186/51 board). The TCP resembles a mini operating
system. It supports a range of keyboard commands
which are useful to run STBL and to troubleshoot
suspect boards. A set of ten command strings can
be stored in the STBL software and may be invoked
at run time by the operator.

ler, as defined in the lOX. The Host firmware under
the control of the TCP performs the testing of the
UUTs.
The STBL can have tests of three different types.
TYPE 1 tests run on the HOST only, TYPE 2 tests
run on UUT only and TYPE 3 tests have both UUT
and HOST code and can run on both. When testing
more than one UUT.. the TYPE 2 tests are executed
in parallel by the UUTs. A given STBL can have any
mixture of these three types of tests.

Using TCP commands, the operator can control the
functions of the GPTF. TCP also responds to the
front panel buttons, (START & QUIT) thus, making
the GPTF automated. The CRT displays dedicated
fields to indicate corresponding status of the testing
such as: UUT board 10, UUT power supply status,
voltage margin as percent of nominal voltage, and
slot location of UUT.

TESTER BLOCK DIAGRAM
Figure 1. shows a block diagram of the tester, in a
level of detail sufficient to understand basic tester
operation. The top of the sketch shows the MULTIBUS II system where testing takes place. On the left
are the UUT slots, and on the right the host boards.
Both iPSB and iLBX II busses are shown. The iLBX II
backplane is physically installed in a removable bus
drawer. Important communication paths shown are:
a fast parallel path between host processor and control computer, and serial channels to the terminal
and Series III development system. Details omitted
for clarity include the heaters; most cabling; temperature sensors; + 5B and heater relays.

The TCP operates in two modes, PRODUCTION
TEST MODE (default) and TROUBLESHOOTING
MODE. These modes allow the GPTF to be operated in a fully automated mode or a manually controlled mode. The PRODUCTION TEST MODE is
turned off while troubleshooting with just a simple
keyboard command.
The TCP works in conjunction with the firmware on
the Host CPU board in the Test Computer System.
The firmware is usually referred to as Host Firmware
(HFW). Apart from communicating with the TCP, the
HFW is an implementation of the Master Test Hand-

SERIES III

DEVELOPMENT
AND :y~~::;OAD

,-"

TELEVIDEO
950

OPERATOR'S

~_....II
~-----*~~~~----------~
I

I TERMINAL
I
I
CONTROL COMPUTER
I
IL _________________________
TERMINAL CABLE _ REQUIRED FQR OPERATION
I
~

DOWNLOAD CABLE - REQUIRED FOR DOWNLOAD ONLY

280189-2

Figure 1. Tester Block Diagram

4-24

MULTIBUS® " GPTF

SPECIFICATIONS
Size:

25" W x 3B" D x 24.5" H

Weight: 90 Ibs.
Power Ratings

USA Units

International Units

Japan Units

Nominal Voltage Rating
Current Rating
Frequency Rating

110 volts
30 amperes
60 hertz

220 volts
15 amperes
50 hertz

100 volts
30 amperes
50/60 hertz

FUSE RATINGS

HEATER COIL RATINGS

Power Ratings

USA/Japan

International

Power Ratings

USA/Japan

International

F1-Heater Coil
1 Fuse
F2-Heater Coil
2 Fuse
F3-MULTIBUS I
Power Supply Fuse
F4-MULTIBUS II
Power Supply Fuse

10A@250V

5A@250V

Heater Coil 1
Heater Coil 2

1000W 110V
660W 110V

1000W 220V
660W220V

6A@ 250V

3A@ 250V

7A@ 125V

4A@250V

15A @250V

10A@250V

Heater Coil 1 is to your right when you face the GPTF.

POWER SUPPLY RATINGS
Power Ratings

USA/Japan

1. Control Computer System Power Supply
2. Test Computer System Power Supply·
'''Input V"

the rnput voltage and the "Output W"

International

'Input V

OutputW

Input V

OutputW

90-132V
90-132V

220W
750V

1BO-264V
1BO-264V

220W
750W

the output power.

The power outlet should be of proper rating. THIS
APPLIES TO BOTH USA AND INTERNATIONAL
UNITS. PLEASE USE THE FOLLOWING GUIDELINES:

POWER PLUGS
USA-The MULTIBUS II GPTF comes with a factory
installed power plug which is a TWIST LOCK 30A,
125V PLUG.
INTERNATIONAL AND JAPAN-The MULTIBUS II
GPTF is shipped WITHOUT a power plug because
of the varied nature of the power outlets in other
countries. CHOOSE A PLUG WHICH MEETS THE
ELECTRICAL REQUIREMENTS OF THE TESTER.
The GPTF is rated at 15A for INTERNATIONAL use
and 30A for JAPAN.

INTERNATIONAL-A 15A drop with a receptacle of
equivalent rating.
USA AND JAPAN-A 30A drop with a receptacle of
equivalent rating.

4-25

MULTIBUS® II
Architecture

The MULTIBUS® II Bus Structure
John Hyde
Multibus " Marketing Manager
Intel Corporation, Hillsboro, OR, 97123

Introduction
Many people equate the phrase "Multibus II" with
the Parallel System Bus defined within the IEEElANSI
1296 specification. While this over simplification is often
useful, the failure to appreciate that It Is a contraction
of a more embracing architecture can lead one astray
when comparing the Multibus II bus structure with other
buses. Comparisons between the Multibus II Parallel
System Bus and other buses are often completed in
isolation, without full regard to the framework in which
the Multibus II architecture was defined. This chapter
rebuilds this framework, describes its hierarchical
structure and detailS how its features are required for
multiple microprocessor designs of today.
Customer needs define the new bus structure.
Intel Corporation had had many years experience
with the Multibus standard before embarking upon the
requirements for a "next generation" bus structure. The
first Multibus standard bus was introduced in 1974 and
it was fundamentally a CPU/Memory bus. It evolved
along with microprocessor technology to become a multimaster shared memory bus capable of solving most real
time applications of the 1980s. The silicon trends
throughout the 1980s were dramatic with DRAM densities
increasing by a factor of two every three years, so
projecting exactly what customers would require in the
late 1980s and through to the 1990s was particularly
difficult. Intel therefore set up a consortium with eighteen
of its larger customers and other industry leaders who
could see the potential within the single board computer
industry, to define the scope and possibilities of what
was to be called "Multibus II".
It was known that the rate of silicon integration
would allow a complete computer system including CPU,
Program Memory, Data Memory, Input/Output and bus
interface to be fabricated upon a single board. With
such a large transistor budget to be spent upon
implementing a single board computer, where would be
the optimal places to best utilize the technology? Sell
test and diagnostics could now be considered - with so

5-1

much silicon on a board it would be prudent to use some
of the transistor count to TEST the remainder of the
board. Since board manufacturers are integrating more
and more VLSI silicon onto their boards, the user needs
some reassurance that the basic board functionality is
intact before they load their value added code - the user
is demanding on board diagnostics for these highly
integrated boards. The bus interface itself, not a
traditional candidate for high integration silicon circuitry,
could use transistors for added sophistication IF this
sophistication could make the single board computers
easier to use. A trend began to develop; transistors
added to improve ease of use filtered to the top of the
implementation list.
With the increased silicon densities available
semiconductor manufacturers tumed their focus upon
increased capability peripheral components. Their use
on single board computers served to compound the
boards complexity and the single board computer'user
was "rewarded" by having to wade through lengthy
reference manuals and innumerable jumper options often arriving at the final solution only by trial and error.
Memory mapping options, arbitration priorities, interrupt
levels and scores of other ''tunable'' parameters
contributed to the hassle, leaving the systems engineer
confused and amazed. Often the only solution was to
locate a board which had already been properly
configured and was operating and then copy off the
jumper list.
Board manufacturers built in numerous options
so that their products could be used in the broadest
possible spectrum of applications. The number of options
offered was not the core of the problem - but managing
them was. Options allow interrupt routing, memory
mapping, EPROM size selection, timing and other user
installed components. When the jumper count exceeded
200, it no longer made sense to monopolize board real
estate since an inexpensive microcontroller could be
used to manage the resources more effectively.
A system bus requires standardized system-wide

configuration information to be made accessible to
software, opening it to opportunities for centralized control
and coordination. Ideally the end-user of these products
will be completely unaware of the configuration process.
They simply remove the board from it's shipping
container, install the proper firmware, plug it into any
free slot in the backplane, and apply power. Things
work the first time around with no mess, no fuss, and no
configuration errors.
The consortium therefore placed focus on the
system aspects of a single board computer design. The
developing model for a typical system built from these
highly capable single board computers was based upon
functionally partitioned subsystems interacting across a
standardized communications channel. This precipitated
a change in philosophy for the traditional system
development from the single board computer outward to
a higher level systems perspective, specified tops-down
and bound together by rigid interfaces.
The consortium quickly reached consensus that
no single bus could be used to satisfy all aspects of a
design of this type - too many variables would have to
be compromised, so a multiple bus structure was
defined in a similar fashion to its Multibus I (IEEE 796)
predecessor. Figure 1 shows the four sub-buses defined
by the consortium: the iSBX® bus was retained for
incremental 1/0 expansion, a local CPU/Memory
expansion bus was proposed and two versions of a
SYSTEM bus (serial and parallel) were defined. The
concept of a SYSTEM bus is an important one to grasp
- all open buses to date were basically CPUlMemory
buses with little regard f~r system aspects. To have an
open bus SPECIFICALLY designed to be a system bus
was a bold step.
Functional panltlonlng as a solution for non·
obsolescence
Before detailing the attributes of each of the defined
buses that make up the Multibus I! systems architecture
it is important to appreciate the model developed for the

Incremental
VOBus

Local Expansion Bus

P1
System Bus
(Parallel andlor Serial)

Figure 1. Since no single bus could solve the defined
problem set, a multiple bus solution was proposed
bus. Figure 2 shows a typical collection of systems
connected to a local area network or LAN. This type of
networked systems solution is very popular with systems
builders since it boasts a large array of benefits. The
solution is functionally partitioned - separate systems
are used to tackle different facets of an overall problem.
These systems are independent from each other and
deCisions made to optimize each of them for their
individual task may be made in isolation with respect to
the other systems in the network. This degree of freedom
gives the systems architect an unquestioned edge when
engineering tradeoffs are being made. The choice of
hardware, options and software may be made with the
sole goal of solving the small part of the overall problem
currently in focus. Each system is typically tuned for its
task using specially configured hardware and software
and it is not uncommon to see multiple different operating
systems within a single network. Systems that MUST
respond in real time, for example, would use Intel's
iRMX® Real Time operating system or their iRMJptimal
system solution. The majority of 1his chapter will detail
the system bus, but the other buses are discussed so
that a context for decisions made will be evident.
The Incremental I/O bus needs to be simple. Its
role is to allow the addition of a small piece of input!
output onto a single board computer to customize it for a
particular application. Performance is not an issue but
low interfacing costs are. More extensive I/O would be
added on the local expansion bus or on the system bus
if an accompanying microprocessor was appropriate.

The Local CPU/Memory Expansion bus will always
be dependent upon microprocessor technology. The
interface between a CPU and its memory needs to be
tightly coupled if we are to extract the maximum
performance levels from a given microprocessor family.
This bus will evolve with microprocessor technology
and will typically exist for only two to four years before it
has to be redesigned. If the CPU element requires more
MIPs then additional identical microprocessors could be
closely coupled on this local expansion bus; if these
microprocessors had on-Chip or local caches, as many
of the higher performance offerings do, then this multiple
microprocessor CPU/Memory bus must be cache
coherent.
A major requirement of the SYSTEM bus is a
technology independent communications media. Since
this bus will remain constant throughout multiple
generations of microprocessors it mu~t be decoupled
from the microprocessor technology used on the single
board computer. This loosely coupled approach, whereby
each single board computer subsystem is independent,
will enjoy all of the benefits of the systems networked on
a Local Area Network. Global system functions such as
initialization, diagnostics and configuration must be
added in a standardized way to this long-lived system
bus.
Physical Standards
A reasonably large card size with ample power is
key to making the best use of the available levels of
silicon integration. While no real data has proven that
edge connectors should not be used, there is a definite
trend towards gas-tight pin-and-socket connectors. A
double Eurocard format, IEEElANSI, 1101 Standard,
with dual 96 pin DIN connectors was chosen for the
Multibus II standard. A 'U' shaped front panel, licensed
from Siemens, West Germany, was chosen for its
enhanced EMI and RFI qualities.
The Incremental I/O Bus
The ,large array of existing iSBX (IEEE 894)
modules for the Multibus I family of products encouraged
its adoption within the Multibus II standard. The iSBX
strategy has proven itself with customers and vendors
alike.
The Local Expansion Bus
The exact bus used for local expansion will vary
according to the specific requirements and performance
levels required in a subsystem design. As far as the
IEEElANSI1296 specification is concerned, this is an
open option and ANY bus that is suitable may be used.
Intel initiated a standard called iLBX® II which was
optimized for a 12MHz 80286 microprocessor although
other manufacturers have implemented this using
members of the 68000 family. Siemens have
implemented Multibus I on the P2 connector and called

5-4

Address Space

Memory

Address

Sequence

Transfer

Block

Numoorof

Space Size

Type

Width (bits)

Transfers

Repling Agents

2"32 bytes

ReadIWrite

8,16,24,32

Supported

One

with increment

CPUlMemory
Space

Input/Output

2"16 8-bit ports

8,16,24,32

ReadIWrite

Supported

One

without inaement
Message
System
Space

2"8 -1 Agents

Write Only

1 Broadcast
Interconnect

Supported

One or All

without inaement

2"98-bit

ReadIWrite

Not supported

One

registers each agent

FIgure 6. The MuHlbus® II System Bus has two address spaces each subdIvIded Into two sectIons
it the AMS bus. Intel has also offered the PC/AT® bus
as a subsystem option on a range of PC compatible
products - while this subsystem bus is low performance,
it is a low cost method to add dumb I/O to a Multibus "
subsystem. The IEEE 896 committee is currently working
upon cache coherent extensions to Futurebus; this bus,
discussed in Chapter 7, would be a good candidate for a
high performance local expansion bus.

requirements and Message Space to fulfill the
standardized communications requirements. Figure 6
shows the four address spaces available on the Multibus
" system bus - note that the traditional CPU/Memory
space is retained for compatibility with existing buses
and to aid migration of existing applications into the
Multibus " environment. The system bus is optimized
for system space operations but CPU/Memory space
operations can perform well in their limited single cycle
mode.
Intel's implementation of the Multibus " Parallel
System Bus is contained in their VLSI bus interface
device, the Message Passing Coprocessor (MPC or
82389), whose functional block diagram is shown in
Figure 7. The MPC bus controller is a 70,000 transistor
single chip device designed to minimize the board area
required by the bus interface circuitry, By standardizing
the bus interface in publicly available Silicon, all users of

The System Bus
The CPU/Memory bus defined on most buses is
inadequate to support "systems-level" requirements so
a SYSTEM SPACE was added to the definition of the
Multibus " System Bus. [A good analogy here, from the
software world, is the User/Supervisor Spaces common
in advanced operating systems]. This system space is
divided into two portions - Interconnect Space to fulfill
the initialization, diagnostics and configuration

LOCAL CPU BUS
8, 16, 24, 32 BITS

Bua

COnnec:t

Spa..
Control

I-

Arbitration

Bu. Speed

Bu. WIdth

Malchklg

""d

and

Bun.,klg

Bun_g

Bua
Control

Bua
Interrupt
Bunerklg

Porlly
_alion

and
Checkklg

Duol Port

-ory
Control

Bua
Error
IIeportklg

L.-.-..

BUS INTERFACE

MPC

MULTIBUS® II Parallel System Bus (IEEElANSI 1296)
FIgure 7. Intel's Implementation of the IEEE 1296 specification Is cast In silicon as the 82389 component.

5-5

the Multibus II standard can look forward to lowering
costs and ensured compatibility. This standardization in
silicon is similar to Intel's work with IEEE 754 floating
point standard implemented in the 8087, 80287 and
80387 components and the IEEE 802.3 Ethemet®
standard implemented in the 82586 and 82588
components.
The 70,000 transistors which make up the MPC
bus controller implement a variety of functions as shown
in Figure 8. As seen from Figure 8 most of the MPC bus
cClntrolier deals with message space, either interrupt
messages or data transfer messages, or with
interconnect space.

Local
Memory

r
Dual Port Control
Interconnect
Mlcrocontroller

Host
CPU

Local

110
On board bus

I+-

MPC

HOff-board Buffersl

LHigh Current Drive Buffers

Traditional Bus Functions
Bus Control
Bus Arbitration
Dual Port Memory Control
Off-Board References
Interrupts

4,000
1,000
2,000
1,000
20,000

Advanced Bus Functions
Parity Generation/Detection
Interconnect Space
Bullt-In-Self-Test
Message Passing

1,000
6,000
1,000
34,000

Total

70,000

Figure 8. The majority of the 70,000 transistors
within the MPC support the System Space functions
of the Parallel System Bus
The MPC bus controller contains almost all of the
logic needed to interface any microprocessor to the
Parallel System Bus - indeed all of today's popular 32bit microprocessors are available on Multibus II products.
One of the few required external components are the
high current bus drivers as shown in Figure 9. Optional
external logic to support dual-port memory selection
and off-board memory and I/O references may be
included if traditional bus functionality is required. All of
Intel's Multibus II boards also includes a microcontroller
(8751) to implement interconnect space but some
members of the Multibus Manufacturers Group have
chosen to implement this using the host microprocessor
or a simple state machine.
The alternate system bus, the Serial System Bus
or SSB, is currently defined but is not implemented in
silicon. The goal of this bus was to reduce the cost of
coupling multiple boards together and it was specified
as a 2Mb/sec serial link. All software interfaces to an
SSB chip would be identical to that of the MPC parallel
bus controller so NO SOFTWARE CHANGES would be
necessary to use the serial system bus. Performance
would be much less using this serial system bus but, for
many deSigns, this would be acceptable. Other deSigns,
however, would benefit from a 200Mb/sec link and Intel
has joined others on the IEEE 1394 serial bus

PSB

Figure 9. The MPC Integrates all of the System Bus
functions Into a single VLSI component
standardization committee to deliver this. This group of
multiple vendors is driving for a standard which will
allow ALL systems to interoperate. Implementation of
the SSB interface chip is on hold pending resolution and
recommendation from this IEEE committee.
Inte~onnect

Space
Interconnect address space is a fundamental Rart
of the IEEElANSI 1296 specification and it addresses
three major customer requirements: Board identification,
initialization, configura,tion and diagnostics. Interconnect
space is implemented as an ordered set of eight-bit
registers on long word (32 bit) boundaries - in this way
little endian microprocessors such as the 8086 family
and big endian microprocessors such as the 68000
,family access the information in an identical manner.
One objective of interconnect address space is to allow
higher level software to gain information concerning the
environment in which it operates, independent of who
manufactured the board, the functions it contains, and
the card slot it is in. To accomplish this goal, a
comprehensive ,Interconnect Interface Specification
which builds upon the concepts introduced within the
IEEElANSI 1296 specification has been published by
Intel Corporation and is available from the Multibus
Manufacturers Group.
Board identification registers are read-only,
locations containing information on the board type, its
manufacturer, what components are installed, and other
board specific functions. Configuration registers are
read/write registers which allow the system software to
set and change the configuration of many hardware
options. In most cases hard wired jumper options can
now be eliminated in favor of software control. Diagnostic
registers are used for the starting, stopping, and status
reporting of self-contained diagnostic routines supplied

5-6

with each board. These diagnostics are commonly
known as Built-in Self Tests (BISTs).
Interconnect space is based on the fundamental
principle that you can locate boards within a backplane
by their physical slot position. This concept, known as
geographic addressing, is a very useful tool during
system-wide initialization. Each board in the system
contains firmware which conforms to a standardized
header format as shown in Figure 10. At boot time, the
system software will scan the backplane to locate its
resources before loading device drivers. This approach
eliminates the need for reconfiguring the software every
time a new board is introduced to the backplane. It also
solves the problem of how to configure multiple controller
and processor boards in large multiprocessing systems.
Slot independence is achieved by having all boards in
the system carry their own initialization and diagnostic
functions on-board in firmware. Operating systems can
generate a map of where resources are located during
initialization time, and then use this list as the basis of
message passing addresses.

Vendor defined

Board Name

Vendor 10

NOTE: Location 32 must return OFFH
Figure 10. All IEEEfANSI 1296 compatible boards
contain an Interconnect Space Header Record
In addition to the header record, a board
manufacturer may also supply additional function records
which make other features of the board accessible to
the user through interconnect space. An example is
shown in figure 11. Function records begin with a byte
specifying the record type, followed by the number of
bytes which the function record contains. The data
contained in a function record is organized by the
manufacturer according to published specifications which
accompany the board. Many types of function records
have already been defined. Some examples include
memory configuration, parity control, serial 110, and·

5-7

End ofTemplate

~~~~~~~

Function Record
FunctJon Record

FunctJon Record
Function Record
Unked
Ust
Format

[

F=======j

Funcbon Record

Header Record
Vendor 10

Figure 11. Extended records within Interconnect
Space give System Soflware knowledge of the
hardware
other commonly used functions. If there is no existing
record type which adequately describes a given function,
new record types can be defined, up to a maximum of
1020 different record types. System sofuvare will search
for a particular record by starting with register number
32 (end of the header record; start of the first function
record), and scanning the record type field, then counting
bytes to the next function record until either the correct
record is found or an "End of Template" record ( hex
value OFFh ) is encountered.
Diagnostic Philosophy within Interconnect Space
Intel has taken the usefulness and standardization
of interconnect space one step further by embracing a
standard diagnostic philosophy. Each intelligent board
should have the capability to test itself and report error
status in interconnect space if problems exist. There
are two occasions when diagnostic testing can be
invoked. A subset of the complete on-board diagnostics
will be run during power-on initialization, and more
extensive testing can be invoked from an operators
console. Following power-on, most boards will go
through a series of initialization checks, where the basic
functioning of the MPC bus controller and microcontroller
is verified. These checks are followed by a power-on
test suite which is controlled automatically by each local
microprocessor. If a hardware failure is detected at this
point, a yellow LEO on the front panel will illuminate so
that the failing module can easily be identified and
replaced by an operator, additionally test results are
posted in interconnect space to be read. across the
backplane. Note that a CPU board when scanning
interconnect space can now discover the operational
status of boards in the backplane as well as their identity.
If further testing is desired, extended diagnostics
can be invoked by placing a diagnostic request in the
BIST registers of interconnect space. USUally one board
will operate as a Master Test Handler, and will request
services from other boards in the system which function

as Slaves while under test. A menu of available tests is
accessible via interconnect space. This test philosophy
can be applied on-site by the end-user or service
representative, or remotely executed via modem from a
regional repair center. In most cases, downtime can be
minimized by sending out a replacement board, thus
avoiding an expensive repair call.
The firmware content of Multibus II boards is
much greater than on previous industry,standard buses.
In addition to the 8751 microcontroller, there are likely to
be EPROMs on board which contain the extended
diagnostics, test handlers, reset initialization sequencing,
debug, monitors, and numerous other functions. The
location of diagnostic firmware on a board will depend
on the complexity of the code and the speed at which it
runs. For simple replier agents, it may be that the onboard EPROM of the 8751 microcontroller contains
enough program store for rudimentary diagnostic
functions as well as the interconnect core firmware. In
contrast, most requestor/replier boards (those capable
, of becoming bus masters) are more complex, and most
diagnostic code is run by the microprocessor from onboard EPROM. In this case, the 8751 serves primarily
as the communications interface for diagnostics.
Interconnect Space - The Manufacturers Perspective
From the perspective of a board deSigner,
interconnect is a mixed blessing.
The board
manufactu'rer is certain to enjoy the benefits of reduced
support costs, easier fault isolation in field repairs, and
enhanced customer satisfaction, but these advantages

do not come for free. One would anticipate longer
development times, increased parts count on-board,
and configuration in firmware to increase the amount of
effort it takes to prepare a Multibus II board for market.
Indeed this is so. In order to minimize this development
time Intel has produced an Applications Note which
details the steps and discusses the options available for
a full featured interconnect space implementation. The
core microcontroller code is also provided on a DOS
diskette and is designed to be user extensible. It is now
straightforward to add these advanced capabilities to
any Multibus II board design.
The Message Passing Mechanism
While the previously described features make more
reliable systems easier to build using the MuHibus II
standard, it is the innovative message passing scheme
that gives the parallel system bus its high performance
in a multiple microprocessor application. The underlying
theory behind message passing is simple - it decouples
activities between the host microprocessor's local bus
and the system bus. This decoupled-bus approach
provides two major advantages. First, it allows increasing
parallelism of operation - resources that would otherwise
be held in traditional wait states while arbitration occurs
are freed, and second, one bus bandwidth does not limit
the transfer rate of another. The local microprocessor
bus and the system bus can perform full speed
synchronous transfers independently and concurrently.
The decoupling is achieved within the M PC bus controller
using high speed FIFO circuitry as shown in Figure 12.

Local Bus

lNTERAUPT

our

IM'teARUPf

TRANSMrr

ASCElV&

_ _ _...._ _~PSB
Figure 12. DecoupUng of the local bus from the system bus Is achieved with nine very high speed FIFOs

5-8

Nine 32 byte FIFO's are integrated into the
MPC bus controller. Five of them are used for Interrupt
messages (one transmit and four receive) and four are
used for the transfer of data blocks (two transmit and
two receive). To understand the impact of message
passing, let us consider a simple example of transferring
a 1K block of data from CPU A to CPU B as shown in
Figure 13. We will first use a shared memory method
and then a message passing method.
To use a concrete example lets assume that A
is a 186 based board and can transfer data at 1 MBlsec
. and B is a 386™ based board that can receive data at
10 MBlsec. We will ignore DMA controller setup. DMA
controller A will put a destination address onto the system
bus and the address decode logic on board B will
respond. We wait for the address to propagate through
the dual- port controller on board B and then wait for the
access time of the memory on board B. Data is
transferred and once accepted by board B a ready
Signal will be generated and DMA controller A will move
on and generate the next address. This address-waitdata cycle repeats until the full 1KB of data is transferred.
The overall speed of the transfer will be 1 MB/sec (the
slower of the two boards) so it will take 1 msec to
transfer the complete 1K buffer. If the system bus was
required by an aHernate CPU then the current data
transfer would be delayed or the aHernate CPU would
have to wait.
Now lets consider the message passing case.
This time we have to set up both DMA controllers. CPU
A could probably transfer data faster than 1 MB/sec into

CPUA
1 Mbls8C

CPUB
10 Mbls8C

6 EJ

IMam~16

IMemo~ I ~

PSB

Figure 13. Let us move a 1KByte block of data from
Board A to Board B

a local 110 port ( the MPC bus controller) but we will
ignore this potential performance improvement. The
speed of this transfer will still be 1 MB/sec, the speed of
the slower board, and the total transfer time will still be 1
msec. What did we gain then for the overhead of setting
up two DMA controllers?
Let us look in detail at what is happening inside
the MPC bus controller. Figure 14 shows a fragment of
each board with different areas of each MPC bus
controller highlighted. Data is being DMA'ed into MPCA at 1 MB/sec and flows into one of the transmit FIFOpairs. Once 32 bytes have been received the MPC
automatically switches to the alternate transmit FIFO
and starts to fill that. The full transmit FIFO empties

Part of CPU Board A

Part of CPU Board B
Loc&IBus

LOta.BU$

Data at 1~MB/sec

Packets
at40MB/sec

•
System Bus

Figure 14. Looking closely at the message based data transfer mechanism

5-9

across the system bus into a receive FIFO in MPC-B.
This transfer of a 32 byte packet occurs at the full bus
bandwidth of 40 MBlsec. A data packet has a two clock
cycle header which describes the source, destination
and type of this packet which reduces the effective data
transfer rate to 32 MB/sec. The packet th~refore takes
1 microsecond to pass between the two MPC bus
controllers. Bus arbitration is done in parallel with the
packet transfer so this does not add to the transit time.
Once the packet is inside of MPC-B then DMA-B empties
its receive FIFO at 10 MBlsec.
The transmit FIFO-pair of MPC-A alternate
between filling from local memory and emptying into
MPC-B until the full 1K of data has been transferred. No
programming, save the initial setup, is required. If we
look at the system bUs activity we see that 1 microsecond
packets are being transferred at 32 microsecond intervals
- the bus is only busy for 3% of the total data transfer.
We have gained 97% bus availability. Compare this
with the 0% bus availability in the shared memory case.
Message passing frees up system bus bandwidth to
enable many other single board computer pairs to
interchange data at no loss in performance. In a multiple
microprocessor application the most precious resource
will be system bus bandwidth and the Multibus II
message passing scheme gives you more, much more.
We gain a lot more than system bus bandwidth
using message passing. Note that CPU A transferred
data from its local memory into a local 110 port (the MPC
bus controller). CPU A did not have to understand the
memory layout or restrictions of memory on CPU B this also allowed CPU B to do its own memory
management and buffer allocations. Similarly CPU B
has no concern over how CPU A does its memory
management. We have isolated the data away from
known memory locations and do not have to deal with
semaphore flags or similar mechanisms. This simplifying
step makes intercommunicating with multiple
microprocessors as straight forward as communication
with a single microprocessor. This isolation of concerns
regarding the local environments of each board, through
the use of a standardized data transfer mechanism, is
especially important in the general case where each
board is running a different operating system (probably
on a different microprocessor). A real time operating
system can now simply exchange data with, say, UNIX
using this standardized message passing mechanism.
Message passing also standardizes inter-CPU signalling
since interrupts are special lYPEs of packet (more
later).
This short explanation has over-simplified the
transfer - some setup is required so that the sending
MPC bus controller knows the message address of the
receiving MPC bus controller etc. This overhead is more
than compensated for by the ignored increase in local
transfer data rates. I also simplified the issue by having
a receiving board much faster than the transmitting

board (10 MBlsec vs. 1 MB/sec) - if I had transferred
data in the opposite direction (from B to A) then MPC-A
would have rejected some packets because its receive
FIFOs would be full and caused MPC B to retry some
data transfers. No data would ever be lost but bus
activity would have increased. The MPC bus controller
uses a logarithmic backoff algorithm on retries so the
bus activity increase would not be excessive. Altemately
MPC B could be preprogrammed to use a lower packet
duty cycle if it had known that MPC A would always be
slower.
Having the underlying architectural support to
permit multi-CPU solutions is, of course, only the first
step. To build systems we need software. Intel, working
with other vendors, has defined a Transport Protocol
specification above the MPC bus controller which
provides services such as large block transfers and
acknowledged transactions. Data fragmentation at the
sender or receiver is detailed so that large data buffers
are neither assumed or required. The implementation is
effiCient across all CPU architectures; indeed, Intel has
supplied implementations on the iRMX Real Time
Operating System, the iRMK Real Time Kemel and the
UNIX System V.386 operating systems; these are
compatible with offerings from Digital Research
(FLEXOS®), Microbar (VRTX®) and Tadpole
Technologies (UNIX68K) ..

Message Space Details
The MPC bus controller introduces a hardware
recognized data type called a packet as shown in Figu're
15. The MPC contains FIFO circuitry such that these
packets may be moved very efficiently between MPCs data is moved on subsequent clock edges of the 10MHz
synchronous bus; this defines the maximum bus
occupancy of a packet to be one microsecond. Each
MPC bus controller has an address in message space
and these are used in the message header (source and
destination fields).

Figure 15. The MPC bus controller Introduces a
hardware-recognised data type called a packet

5-10

Seven different packet types are currently defined
and are summarized in Figure 16. These divide into two
catagories; unsolicited, or interrupt packets and solicited,
or data transfer packets. The data fields within a packet
are user defined and the length may vary from zero to a
maximum of 32 bytes (28 for an unsolicited packet) in
four-byte increments. Note that a packet with no data
bytes will only consume 2 clocks or 200nsec of system
bus time.
Unsolicited Packets.
Unsolicited packets, as the name implies, are
always a surprise to the MPC bus controller. Their
arrival is unpredictable so each MPC has four FIFOs in
which it can queue unsolicited pacl'
Even parity on SC<3..O>'

Figure 19, The Status/Control lines are encoded to
preserve lines on the system bus

5-12

ArbHratlon
All boards request use of the bus through a
common bus request line, BREQ·. A distributed
arbitration scheme is defined which grants the bus to
the numerically highest requesting board as identified
on lines ARBO ..5. Two arbitration algorithms are
supported: fairness, which gives each board an even
portion of the available bus bandwidth, and priority,
which permits a high priority request (such as an interrupt)
to be guaranteed the next access to the system bus.

In order to progress quickly through this diSCUSSion,
an assumption that the requestor always issues valid
requests will be made. Error handling for invalid requests
will be added later. Figure 21 summarizes the deSign
task. The logic required to map the multiple Signals and
protocols from the Multibus II parallel system bus into
the simple read strobe, write strobe and chip select of
an I/O device must be designed. In this example features
will be kept at a design minimum but all essential circuitry
will be discussed in detail.

Power
There are ample power and ground lines defined
and these are spread over the length of the P1 connector
to minimize ground shift and other problems.
Typical Bus Cycle
The parallel system bus is particularly easy to
interface to. This section will cover the sequencing of a
typical REPLIER interface as an illustration of the bus
timing. The IEEE!ANSI 1296 specification details
numerous state machines that track bus activity and are
implemented to guarantee compatibility. An I/O replier
need only implement a single "Replying Agent" state
machine. This is shown in Figure 3.5-5 in the IEEE!
ANSI 1296 standard and repeated here in Figure 20 for
reference. Remember that an application CPU (a
REQUESTOR) will start the cycle that the REPLIER will
respond to.

REPRDY=L
AND
ADDR=H

REPRDY=H

SC3'= LAND
SC2"=HAND
REPRDY=L AND
AGENT STATUS ERROR=L
SC2"=HAND
(SC3':HOR
REPRDY=HOR
AGENT STATUS ERRDR=H)

Figure 20. The IEEElANSI1296 Specification detailS
numerous state machines. A replier Is shown here,

5-13

•

~
1/1

COntrol

III
III

Status

!!!

STATE
MACHINE

WR
CS

10 DEVICE

REPRDY

Data

Figure 21. The deslg n of a REPLIER Is fundamentaly
a bus monitor.
The replying agent state machine is fundamentally
a bus monitor. State transitions in figure 20 occur at the
falling edge of bus clock. The state machine remains in
the wait-for-request state until it detects the start of a
requestor cycle on the system bus (SCO' LOW) then it
moves into an address decode state. If this requestor
cycle is not ours (local decode signal ADDR is LOW)
then return to the wait-for-request state. If the requestor
cycle is detected as ours (ADDR is HIGH) then transition
to a new state controlled by a local ready signal
(REPRDY). If not ready (REPRDY is LOW) then wait
until ready. Once ready then wait until the requestor is
ready (SCS' is LOW) and provide/consume valid data.
Check to see if this is a muHi-byte transfer (SC2* is
HIGH) and if it is not return to the wait-for-request state.
If a multi-byte transfer is detected then decide to
accept or to ignore the data in the remainder of the
cycle. If the additional data cannot be handled then
signal an agent status error (Continuation error) and
wait for the requestor to terminate the cycle. If a multibyte transfer can be supported then oscillate between
the replier wait state and the replier handshake state
where data is strobed. Eventually the requestor will
signal the last data element (SC2 set LOW) and retum
to the wait-for-request state.

At the start of each requestor cycle that status
lines (SC1* through SC6*) detail the type of cycle; 801*
signals a locked transfer, 5C2* and 5C3* encode the
data width, SC4* and SCS* encode the address space
and SC6* signals a READ or WRITE cycle. A replier
must latch these status lines with the address bus and
use the information to control its subsequent cycle. A
complete list of the Status/Control decoding is shown in
Figure 19.
An I/O replier has certain responsibilities that must
be adhered to. A requestor expects an I/O replier to
generate status information and to signal when ready so
that the requestor may proceed with the cycle. The
cycle will only terminate once both requestor and replier
have signalled that they are ready (the IEEElANSI1296
includes a time out feature which prevents the bus from
hanging if both ready signals are not generated). A
replier drives SC4* LOW to indicate READY and status
information is driven on lines 5CS" through SC7*; 5CS"
must also be driven and identifies parity across lines
SC4* through SC7*. If a replier is supplying data to a
re~uestor then correct data parity must also be driven
onto the system bus.

Summary
The Multibus II Parallel System Bus was
DESIGNED to implement all of the "systems features"
of a single board computer based system. The bus does
have some CPU/Memory attributes but these were only
included for compatibility and to aid migration into the
Multibus II environment - ~mparing these CPU/Memory
features in isolation with those of other buses is a
complete disservice to the Multibus II architecture and
misses the complete design goals and motivation set
forth for this standard.
The silicon revolution forced the design of the
Multibus II Parallel System Bus - technology was
advancing faster than our abilities to use it so we had to
find new implementation strategies to benefit from these
advances. Functional partitioning was chosen as the
vehicle to embrace the technology; by partitioning the
problems into smaller and smaller sub-problems we
reach a point where the sub-problems are
implementable. The Multibus II consortium chose this
path and executed with precision; transistors were
applied at strategic points to simplify implementations
and encourage ease-of-use. The Multibus II architecture
is completely defined, documented and available.

5-14

APPLICATION
NOTE

AP-422

October 12, 1987

Designing
a Central Services Module
for MULTIBUS®II

JORY RADKE
MODULES DEVELOPMENT ENGINEER

©Intel Corporation, 1987

Order Number: 280634-001

5-15

AP-422

PURPOSE
This paper describes and presents methods for implementing the functions provided by the Central
Services Module, as defined in the IEEE 1296 specification, and is intended to assist the sytem designer in
understanding and effecting these functions. Function options and other design considerations are
discussed. It is assumed the reader is familiar with the terms and definitions used in the IEEE 1296
specification and with basic logic design prinicples.

5-16

AP-422

1.0

INTRODUCTION

Depending on system requirements, the CSM may
additionally provide:

The IEEE 1296 specification, based on the Intel®
MULTIBUS® II bus architecture, defines certain
general system-wide functions to be provided by a
Central Services Module (CSM). These systemwide functions include power-on and power-fail
reset sequences, clock generation, bus timeout
detection and signal generation, and the assignment of cardslot and arbitration identification
(ID) to each board (agent). The communication
path between the CSM and the other agents in the
system environment is via the Parallel System
Bus (PSB) interface.
The implementation of the defined CSM ensures
uniformity in providing a single source for those
system-wide functions required in an open-hus
architecture, such as that established in the IEEE
1296 specification. Centralizing system-wide functions reduces system cost and frees board area for
other functions since only one board in the system
need contain the CSM logic. The IEEE 1296 specification stipulates that only the agent in cardslot 0
contain the active CSM functions although other
system agents may contain CSM functions.

2.0 CSM FUNCTIONS AND PSB SIGNALS
The following paragraphs identify and briefly
describe the system-level services and functions
supplied by the CSM and the PSB signals generated, monitored or used to implement these services. An asterisk following the signal name indicates that the particular signal or group of signals
are active when at their electrical low.

2.1

CSM Functions

The IEEE 1296 specification defines the minimum
required functions of a CSM as:

•
•

Other system-wide resources, such as a time of day
clock or interface to another bus system, may be
conveniently implemented with the CSM on the
same PSB agent. We shall see that the CSM functions require very little board area to implement.

2.2

•
•

Generation of system clock signals
Generation of reset sequences for both cold and
warm start and power failure indication
Cardslot and arbitration ID initialization
Timeout signal generation for PSB data
transfer cycles.

5-17

PSB Signals Used by the CSM

The CSM utilizes signals from each of the five
signal groups defined in the IEEE 1296 specification. These signals are identified and their use by
the CSM is described briefly in table 2-1.

3.0

FUNCTIONAL OVERVIEW

The following sections discuss how to add the CSM
functions to a PSB agent. The agent could contain
only the CSM and interconnect relier modules or additional functional modules as well. The design example
provided in section 4, (excepting the PSB buffers),
requires less than six percent of the area on a standard
MULTmus II board. The CSM module cannot be
added to agents which employ Intel's Message Passing
Coprocessor, due to the current and capacitive loading
requirements of the PSB signals in table 2-1 which the
MPC drives directly.
This paragraph provides' a functional overview of the
design and discusses signal requirements. A detailed
design example is illustrated and discussed in paragraph 4. Additional design considerations are described in paragraph 5.
Functionally partitioning the CSM functions results in
the block diagram shown in figure 3-1. The signal terminations identified on the righthand side of the diagram are the actual PSB pin assignments identified in
the IEEE 1296 specification.

3.1
•
•

Power-fail recovery reset
Bus ownership timeout.

Clock Generator (CLKGEN) Function

Listed in table 3-1 and depicted in figure 3-2 are the
timing relationships between the BCLK* and
CCLK* signals as specified in the IEEE 1296
specification. The circuits used to develop and
supply the BCLK* and CCLK* signals must

AP-422

Table 2-1.

PSB Signals Used by the CSM

Signal
Name

CSM Function

Group

BREQ*

Arbitration Cycle

Bus Request. All agents that require access to the PSB
assert the BREQ* signal. The CSM monitors this signal as part of its bus timeout function.

ARB<5 .. 0>*

Arbitration Cycle'

Arbitration lines. The CSM uses these lines during a
reset sequence to assign a cardslot ID and an arbitration ID to each agent in the system.

AD<20 .. 1>*

Address/Data Bus

Address/Data lines. See figure 2-1. Each Address/Data
line is connected to the LACHn* pin of a cardslot. The
LACHn* signal is used to latch the cardslot and arbitration IDs to each agent (except cardslot 00) during a
reset sequence.

SC<4 •• 2,0>*

System Control

System Control lines. The CSM monitors these control
signals between agents to sense bus timeout during
data transfer cycles.

TIMOUT*

Exception Cycle

Bus Timeout. TIMOUT* is asserted by the CSM to
signal that an agent is taking too much time to.
respond to a handshake.

BUSERR*

Exception Cycle

Bus Error. An agent activates BUSERR* to indicate
its detection of a data integrity problem during a
transfer. The CSM monitors this signal as part of its
bus timeout function.

BCLK*

Central Control

10MHz Bus Clock. Driven only by the CSM to provide
all system timing references.

CCLK*

Central Control

20MHz Central Clock. Driven only by the CSM as an
auxiliary clock for use as an additional timing reference
among bus agents.

RST*

Central Control

Reset. Driven only by the CSM as a system-level initialization signal.

DCLOW*

Central Control

DC Power Low. Driven only by the CSM as a warning to
system agents of an imminent power failure. Part of
the CSM reset generation function.

PROT*

Central Control

"
power-fail
Protect. Driven only by the CSM during
sequences. Part of the reset generation function.

5-18

AP·422

CARDSLOT 1

CARDSLOT 2

CARDSLOT n

• • • •
...

AD*

LACHn*

:..

AD1*

...

LACHn*

AD*
~'

AD2*

AD*

LACHn*

ADn*

ADDRESS/DATA BUS SIGNAL GROUP
BACKPLANE CONNECTIONS

Figure 2·1. Backplane Connection of LACHn*

guarantee t2 (high time), t4 (low time), and t5
(period). The circuits must also guarantee t6 (clockto-clock) and the correct phase relationship
between clock signals. Signal parameters tl (rise
time) and t3 (fall time) must be met by the buffer
device driving the clock signals onto the PSB bus
interface.

resets. The WARM and COLD inputs represent usercontrolled signals for use in generating warm or
cold resets. They might be supplied from a system
front panel or via a status register in the agent's
interconnect space. BCLKI * is an input to clock
the synchronous RST* signal.

Note:
The BCLK2* and CCLK2* signals are only
required for backplanes containing more than 12
cardslots.
'

Tables 3-2 through 3-4 and figures 3-3 through 3-5
list and depict the timing specifications for the
cold, warm and power-fail recovery resets, respectively.

The CSM clock functions can be implemented by
use of a crystal oscillator, frequency divider, 'and
two or more bus drivers.

The IEEE 1296 specification defines three types of
reset sequences for the CSM: cold, warm and recovery. The RST*, DCLOW* and PROT*
signals are used to encode the reset type. The
DCLOW* and PROT* signals are defined as
being asynchronous while the RST* signal is
defined as being synchronous.

There are various system and user defined
parameters beyond the scope ofthis article which
can be added to the design and implementation of
the RSTGEN function. Exploring the flexibility
presented by such additional factors as the characteristics of the ACLOW* signal, whether or not
to support battery backup, the ramp-up time of the
power supply, the number of front panel or user
inputs, or which options to permit when multiple
resets occur simultaneously are left for the design
engineer's consideration.

The ACLOW* input is only from the power
supply in systems supported by battery backup
(VBB) and is required for power fail and recovery

The RSTGEN function described above can be
implemented using voltage monitors, timers and
basic control logic.

3.2 Reset Generator (RSTGEN) Function

5-19

AP·422

CLKGEN

BCLK1*
COLD
" WARM
-- ACLOW*

RSTGEN
RST*
BCLK1*
BREO*

CCLK2*
CCLK1*
BCLK2*
BCLK1*

6A
6C
4A
4C

PROT*
DCLOW*
RST*

2B
23B

TIMOUT*

ARB*

24A, 24C, 25A
25C, 26A, 26C

TOGEN

BUSERR*
SC(4 .. 2,0>*

RST*
BCLK1*
DCLOW*
PROT*

IDGEN

AD(2o .. 1>*

SC (4 .. 2,0>*
BUSERR*
BREO*

Figure 3-1.

CSM Functional Block Diagram

, 5-20

16A-14C,
13A-12C,
12A-11A,
1oA-BC,BA,
7B, 7A
32B, 29C-29A
23C
23A

AP-422

Table 3-1.

Parameter
t1

t2
t3
t4
t5
t6

CSM Clock Timing Specification

BCLK*

Parameter Description
Rise Time
High Time
Fall Time
Low Time
Period
Clock-to-Clock

Min

Max

2.0
52.1
2.0
52.1
100.1

48.0

48.0
99.9
0

+10

CCLK*
Min

Max

2.0
27.0
2.0
27.05
50.05

23.0

23.0
49.95

~-----------------t5------------------~

BCLK*

O.55V

Figure 3-2.

Clock Timing Relationships at CSM Connector P1

5-21

Units
ns
ns
ns
ns
ns
ns

AP·422

Table 3·2. CSM Cold Reset Timing Specifications

Parameter

Parameter Description
DC power setup to DCLOW*
Cold reset duration
Warm reset duration

t2
t3

Min

Max

Units

1.0

ms
ms
ms

2.5
50.0

95% of Nominal
Voltage for all Supplies

POWER
SUPPLY

DCLOW*

PROT*

RST*

Cold Start Indication

Figure 3·3. Cold Reset Timing on the PSB

5-22

AP·422

Table 3-3. CSM Warm Reset Timing Specification

Parameter
t1

Parameter Description

Min

Max

Units

RST* pulse width

50.0

DCLOW*

PROT*

------~~----+----t1----------~

,--------------------

Warm Start Indication

Figure 3-4. Warm Reset Timing on the PSB

5-23

AP-422

Table 3-4.

Parameter
t1
t2
t3
t4

t5
t6
t7
t8

CSM Power Fail and Recovery Timing Specification

Parameter Description

Min

DC power hold from DCLOW*
PROT* delay from DCLOW*
DC power setup to DCLOW*
RST* delay from DCLOW*
RST* setup from DCLOW*
RST* active from PROT*
DCLOW* pulse width
PROT* hold from DCLOW*

6.5
6.0
1.0
6.5
0.5
50.0
7.5
2.0

Max

Units

ms
ms
ms
ms
ms
ms
ms
ms

6.25

7.0

2.5

95% of Nominal

,j()t.

POWER
SUPPLY

DCLOW*

PROT

~-------------t7------------~~

*
\~-------t5------~~

RST*

Power Failure Recovery Indication

Figure 3-5.

Power-Fail Recovery Timing on the PSB

5-24

AP-422

3.3

during a Transfer Cycle. The transition from one
state to the next is assumed to be synchronous
with BCLK$.

Timeout Generator (TOGEN)
Function

TIMOUT* signal generation for both the
Transfer Cycle and the bus ownership cases will be
considered. Since all input and output signals are
synchronous, BCLK* is required.

In the IDLE state, Transfer Cycles are not in progress. The conditions for entering the IDLE state
are: system reset (RST* low) OR exception cycle
(BUSERR* low) OR EOT handshake in reply
phase (SC2* AND SC4* low AND SCO* high).

3-3.1 TRANSFER CYCLE TIMEOUT

The IEEE 1296 specification defines a Transfer
Cycle timeout period as 10,000·12,500 counts of
BCLK* (nominally 1·1.25ms). A timer or counter
and control logic can be used to implement this
function. If test frequencies are desired for
BCLK$, then a counter may be a more desirable
solution so the Transfer Cycle timeout period
(TOP) will be a function of BCLK$ and not fixed
at 1 ms.
Timing of the Transfer Cycle begins on the first
clock of a request phase; indicated by SCO$
active. Once initiated and unless one of the follow·
ing conditions is satisfied, the Transfer Cycle TOP
will have expired and the CSM must assert
TIMOUT$:
a. SC2$ AND SC4$ low AND SCO$ high
during a reply phase. This condition indio
cates requestor end of transfer (EOT) and
replier ready handshake, which termi·
nates Transfer Cycle timing.
b. BUSERR* low. This signal unconditionally initiates an Expection Cycle
which ends the Transfer Cycle and stops
the counter.
c. SC3$ AND SC4* low AND SC2* AND
SCO$ high during a reply phase. This
condition indicates handshake without
EOT and the Transfer Cycle TOP needs
to be restarted.

The condition for transitioning to the START state
is the start of a Transfer Cycle (SCO* low). The
START state is used to initialize the Transfer
Cycle TOP counter before transition to the WAIT
state. The START state always transitions to the
WAIT state.
In the WAIT state, either Transfer Cycle TOP
expires or a condition where handshake without
EOT occurs. If the Transfer Cycle TOP has
expired, transition is to the TO state and the signal
TIMOUT* is activated. If handshake without
EOT occurs (SC3* AND SC4$ low AND SC2*
AND SCO* high), transition is back to the START
state to reinitialize the Transfer Cycle TOP counter and then returns to the WAIT state.
The TO state always transitions back to the IDLE
state. Thus, in this design, TIMOUT$ is asserted
for one BCLK$.

3.3.2 BUS OWNERSHIP TIMEOUT

The IEEE 1296 specification identifies the bus
ownership timeout as system defined. A timer or
counter and control logic can also be used to
implement this function.

d. RST$ low. This condition terminates all
bus activity.

Timing of bus ownership begins with the assertion
of BREQ* low and ends when BREQ* high OR
RST* low. Ifneither ofthese two conditions occur
before the TOP expires; then the signal
TIMOUT* is asserted.

The state-flow diagram in figure 3-6 symbolizes
the control logic necessary to assert TIMOUT$

The state-flow diagram in figure 3-7 symbolizes
the control logic necessary to assert TIMOUT$

5-25

AP-422

en
~

~en

~I ~en
*
~I
.*
~I
TOP

OTHERWISE

Figure 3-6. State-Flow Diagram for Monitoring Transfer Cycle Timeout

Figure 3-7. State-Flow Diagram for Monitoring Bus Ownership Timeout

5-26

AP-422

for bus ownership. The IDLE state is transitioned
to whenever BREQ* high OR RST* low. Once
BREQ* low, a transition to the WAIT state is
made. If BREQ* fails to go high before TOP
expires, transition is to the TO state and the signal
TIMOUT* is activated.
In implementing the Transfer Cycle and bus
ownership timeout functions, it may be desirable to differentiate between the two signals via a
status register in the agent's interconnect space.
Requesting agents on the PSB bus could then
determine which type of reset occurred.

3.4

Cardslot and Arbitration 10
Assignment Generator (IOGEN)
Function

The total number of cardslot and arbitration IDs to
be assigned is determined by the number of agents
in a system (up to a maximum of 21). Also, the
implementation logic requirements are reduced
when the system contains fewer agents, but for
this discussion the maximum number of agents is
assumed.
The default assignment of cardslot and arbitration IDs are listed in table 3-5. The CSM timing
relationships shown in figure 3-8 are duplicated
Table 3-5.

from the IEEE 1296 specification for reference.
Not indicated in the table or figure is the requirement that each ID be setup one BCLK* before
and held one BCLK* after the BCLK* in which
LACHn* is active.
The LACHn* for each cardslot equals its corresponding ADn* and assuming the ID assignments will be made in ascending numerical order
(ADl* ... AD20*), a shift register would be a
satisfactory method for driving the Address/Data
lines. The IDs themselves lend nicely to sequential
logic or a table scheme. The remaining circuit
requirements are control logic to provide at least
eight counts of BCLK* delay following RST*
going active before ID assignment begins (per
IEEE 1296 specification), and to coordinate the
Address/Data line shift register with the ID
sequencer logic. The agent's Address/Data line
buffer control logic must allow the CSM to enable
the buffers on the PSB during ID assignment.
3.4.1 EIGHT COUNT BCLK* DELAY

A simple way to implement an eight count
BCLK* delay before ID assignment begins is
symbolized in the state-flow diagram shown in
figure 3-9. Waiting until DCLOW* ~ND PROT*

Default Cardslot and Arbitration ID Values

Cardslot

ADn*

Cardslot ID ARB<5 •• 0>*

Arbitration ID ARB<5 .• 0>*

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

LHHHHH
LHHHHL
LHHHLH
LHHHLL
LHHLHH
LHHLHL
LHHLLH
LHHLLL
LHLHHH
LHLHHL
LHLHLH
LHLHLL
LHLLHH
LHLLHL
LHLLLH
LHLLLL
LLHHHH
LLHHHL
LLHHLH
LLHHLL
LLHLHH

HLLLLL
HLLLLH
HLLLHL
HLLLHH
HLLHLL
HLLHHL
HLLHHH
HLHLLL
HLHHLL
HLHHHL
HLHHHH
HHLLLL
HHLLLH
HHLLHH
HHLHHH
HHHLLL
HHHLLH
HHHLHH
HHHHLL
HHHHLH
HHHHHL

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

5-27

AP-422

RST.

\~----+---+--f)-------t---ARBITRATION ID

ARB5*

ARB (4 .. 0>*

LACHn*

Figure 3-8.

Cardslot and Arbitration ID Assignment Timing

Figure 3-9.

State-Flow Diagram for Delaying ID Assignment

5-28

AP-422

are inactive before starting the counter ensures
that the power source has stabilized following
power-up and recovery resets. Since a warm reset
occurs only during normal system operation and is
indicated by RST*, the RST* low condition is
used to transition to the first count state.
By using RST* high to keep the counter in the
IDLE state, the IDEN state can be used in Arbitration and Address/Data line PSB buffer control
because the CSM is the only driver of these lines
during a reset sequence. The implemented buffer
control circuit will necessarily depend on the type
of agent the CSM resides on and the type of buffers
used.

3.4.2 ID SEQUENCER LOGIC

The state-flow diagram in figure 3-10 symbolizes
the control logic necessary for controlling the ID
sequencer. The sequencer is in an IDLE state until
the BCLK* counter of figure 3-9 is in the IDEN
state; then SETUP, LATCH and HOLD states are
necessary for each ID. Assuming the Address/
Data PSB buffers are enabled during the LATCH
state, the shift register driving the Address/Data
lines with the LACHn* signal could be timed in
either the SETUP or HOLD states. The sequencer
continues through the SETUP, LATCH, and

HOLD states until all of the IDs have been
assigned.

4.0

DESIGN EXAMPLE

The CSM functions previously described in the
functional overview (excepting bus ownership
timeout) have been implemented in the design
example presented and described in the paragraphs to'follow.
Because the agent hosting the CSM determines the
type of line receivers and drivers used, the functional block diagram (figure 3-1) is modified to
include a parallel system bus interface (PBI) function (see figure 4-1). The PBI function defines the
buffer structure for CSM input! output operations,
electrically isolates the other CSM circuits from
the PSB interface, and further modularizes the
design.
The circuits assembled to perform the CSM functions in the design example are shown schematically in figure 4-2. The remainder of this section
describes signal processing for each of the major
functional groups and references are made to figure 4-2 by sheet number only. For usability, the
figure is located at the end of this section following
figure 4-8. For simplicity, the decoupling capacities have been omitted from the schematic.

ALWAYS

~-<
(f)

Figure 3-10.

State-Flow Diagram for Controlling ID Assignment

5-29

AP-422

ClKGEN

BClK
CClK
AGENT
PSB
INTERFACE

23C

BUSERR*
COLD
WARM
AClOW*

RSTGEN

PROT
DClOW
RST
BClKIN

TIMOUT
BUSERR

BCLKIN

PBI

TOGEN

RST

CClK2*
CClKl*
BClK2*
BClKl*
PROT *
DClOW*
RST*
TIMOUT*

SC<4 2,0>*
ARB(5.0>*

SC<4 2,0)
AD(20 1>*

BCLKIN
RST
DClOW

ARB<5.O>

6A
6C
4A
4C
lB
2B
23B
5A

32B, 29C-29A
24A, 24C, 25A
25C, 26A, 26C
16A-14C,
13A-12C,
12A-llA,
10A-BC, BA,
7B,7A

IDGEN
AD(20 1)

Figure 4-1.

4-1

CSM Overall Block Diagram

PSB Buffer Interface (Sheet 1)

The majority of the P8B interface signals are buffered using 74F240 packages. The 74F240 circuitry
meets the P8B loading and drive specifications
and are satisfactory for this design example. The
ARB<5 .• 0>* lines are specified to operate
open-collector and the 74838 gates used meet this
requirement. The BUSERR* input is buffered
through a spare 74A81004 gate simply to keep the
part count down.

Since the C8M is the only driver of the clock, reset
and timeout signals, their buffer enables are tied
active. The AD<20 .• 1>* lines are only driven
by the C8M during reset sequences and the
ADEN* signal from the IDGEN circuit is used to
enable these lines. Also provided by the IDGEN
circuit is the IDEN signal to enable the 74838
gates during ID assignments. BCLK1* is
buffered through a 74A81004 gate as BCLKIN
and provides the on-board timing for the synchronous logic.

5-30

AP-422

4.2

CLOCK GENERATOR (CLKGEN)
(Sheet 2)

The 40MHz oscillator, 74AS163 package and two
74AS1004 gates form the CLKGEN circuit. Dividing the 40MHz to 20MHz and lOMHz in the same
package controls clock-to-clock skew. Since all
clock signals are driven by the same 74F240 package (sheet 1) and assuming a less than 0.5ns samepackage skew from both the 74AS163 and 74F240
packages, the worst case clock-to-clock is Ins
(ignoring trace layout considerations). The IEEE
1296 specification defined clock-to-clock skew is
listed in table 3-1 as parameter t6. By using the
74AS1004 gates in the 20MHz path to delay
CCLK, the clock-to-clock minimum and maximum times are met:
clock-to-clock min

=2 x mintpd 74AS1004 - worst
case package skew
= 2ns
-Ins
= Ins

clock-to-clock max =2 x maxtpd 74ASI004 + worst
case package skew
=8ns
+ Ins
=9ns

on sheet 3 form the RSTGEN circuit. The timing
for DCLOW and ARST are provided by the CT
inputs on the TL7705A power supply monitors,
which are adjustable to meet different power
supply ramp-up times. The timing provided at the
CT input can be determined by adding the power
supply ramp-up time from the monitor threshold at
90 percent VCC to the minimum pulse width of
DCLOW or ARST. (Note that the pulse width for
ARST should also include the pulse width for
DCLOW.) For this example, a 5ms ramp-up from
4.5- to 4.75-Vdc was assumed.
The 74AS74 packages synchronize SRST (later
developed into RST*) for the PSB interface and
SDCLOW for the state machine in the IDGEN
circuit.
The RIDCLOW* and RIRST* signal inputs to
the TL7705A packages are generated in the
PALl6R4B simply to reduce the part count. The
P ALl6R4B equations, shown in figure 4-3, are basically that of OR gates.

4.4

Timeout Generator (TOGEN)
(Sheet 3)

Trace routing and loading on the clock signals are
critical to proper CSM operation. The loading and
trace layout should be kept as close to identical as
possible to minimize skew. If analysis reveals that
skew is greater than allowed, additional steps
would need to be taken to reduce it.

The 74S779 counters and part of the PALl6R4
implement the Transfer Cycle timeout function.
UsingtheTIMOUT, S1 andCET* outputs of the
PAL16R4 as the state bits in figure 3-6, the state
assignments provided in table 4-1 control the
counters and assert TIMOUT.

Note that in the design example, the counter will
reach a count ofOFH (15) after power-up before the
circuit starts to produce the proper BCLK* and
CCLK* waveforms.

In the configuration shown on sheet 3, the counters provide 10,240 counts of BCLK* and when
combined with the state machine, yield a timeout
period of 10,243 counts ofBCLK*. The count can
be fine tuned by adjusting the inputs to the counters. The equations for the P ALl6R4 are shown in
figure 4-3.

4.3

Reset Generator (RSTGEN) (Sheet 2)

As described in paragraph 3.2, the RSTGEN function is influenced by the power supp~y used and
system configuration. For simplicity, the design
example assumes the following:
•
•
•
•

No battery back-up capability
Equal ramp-up time on all power supply levels
ACLOW* input from the power supply signalling eminent power failure
Two active high debounced inputs for cold and
warm reset invocation by the system user.

The TL7705A and 74AS74 packages on sheet 2 and
part of the P AL16R4B programmable logic device

5-31

4.5

Cardslot and Arbitration I D Generator
(IDGEN)

The 63RA481A® PROM (ID sequencer) on sheet 3
and the 74LSl64 AD* shift registers and
P ALl6R8 on sheet 4 form the IDGEN circuit. Note
that to keep the part count down, the shift register
for driving AD<17 .. 20>* is implemented in
the PAL16R8. Also implemented in the PAL16R8
is the IDEN state machine depicted in figure 3-9.
The implemented IDEN state machine only provides one BCLK* delay instead of eight, but the
ID sequencer provides the additional counts

AP-422

Table 4-1. TOGEN State Assignments

State

TIMOUT

CET*

0
0
0
1

0
0
1
1

1
0
0
1

IDLE

START
WAIT
TO

chip name PAL16R4
BCLKIN SRST SCQ SC2 SC3 SC4 BUSERR /ACLOW /TOP GND
JOE /RIRST /RIDCLOW S1 /CET TIMOUT RST COLD WARMVCC
equations
:=

/TIMOUT

/TOP * /TIMOUT * CET

+ /TIMOUT * /S1

+ TIMOUT * Sl * /CET
+ /SCQ * SC2 * SC4
+ BUSERR
+ RST
:=

/S1

TIMOUT * S1 * /CET

+ /SCQ * SC2 * SC4
+ BUSERR
+ RST

+ /SCQ * SC3 * SC4 * /TOP * /TIMOUT * Sl * CET
+ /TIMOUT * /Sl * /CET

CET

:= /RST
/RST *
/RST *
/RST *
/RST *
/RST *

+
+
+
+
+

RIDCLOW:=

* /SC2 * /BUSERR * /TOP * /TIMOUT * CET
SCQ * /BUSERR * /TIMOUT * /Sl
/SC4 * /BUSERR * /TOP * )TIMOUT * CET
SCQ * /BUSERR * /TOP * /TIMOUT * CET
/SC4 * /BUSERR * /TIMOUT * /Sl * CET
/SC2 * /BUSERR'* /TIMOUT * /Sl * CET

COLD

+ ACLOW
RIRST

•-

COLD

+ WARM
/RST

/SRST

Figure 4-3.

Equations for TOGEN PAL 16R4B

5-32

AP-422

required by sequencing through unused cardslot
IDs. (The signal IDEN2 is identical to IDEN and
is used to furnish additional DC drive for the ID
sequencer.)

LATCH output inactive low. The ID sequencer
remains in the last HOLD state until IDEN
becomes inactive low and is then reset to the IDLE
state.

Six outputs of the ID sequencer are used to drive
the ARB<5 •. 0>* lines and the remaining two
outputs are assigned the signal names LATCH
and HOLD. The IDLE state, shown in figure 3·10,
is indicated when all of the ID sequencer outputs
are low; the SETUP state by the ARB<5 .• 0>*
outputs changing to a new ID; the LATCH state
when the LATCH output is active high and the
HOLD output is inactive low; the HOLD state
when the HOLD output is active high and the

The state·flow diagrams in figures 3·9 and 3·10 are
modified as shown in figures 4·4 and 4·5. These
modifications take advantage ofthe design imple·
mented to supply the eight counts of BCLK*
delay before assigning IDs and to initialize the
74LS164 AD* sq.ift registers.
The AD* shift registers are clocked during the
HOLD state of the ID sequencer. Two passes are
needed through these registers, one to latch card·

LASL ID

Figure 4-4.

Modified State-Flow Diagrams for ID Assignment

RST + DCLOW

Figure 4-5.

Modified IDEN State-Flow Diagram

5·33

AP-422

slot IDs and one to latch arbitration IDs. The AD*
shift registers are initialized at zero while IDEN is
inactive low. During the HOLD state of unused card:
slot ID 26 and the HOLD state of cardslot ID 20,
the SDATA (Serial Data) output of the P AL16R8A
is active high so that a one is shifted into the AD*
shift registers at the beginning of each pass.

the AD<20 •• 1>* buffers (sheet 1) onto the PSB
bus during the LATCH state.
Figure 4-6 shows the timing produced by the
IDGEN circuit. The equations for the PAL16R8
are shown in figure 4-7. The PROM ID code information is provided in figure 4-8.

The LATCH output from the ID sequencer is
inverted to produce ADEN*. This signal enables

I I" I
I I" I
-lJ I I Ii I
...LJ..rt1! I
I I
I I II ':': II
I I I: I
I I I 1, I
I I I II" I
I I I" I
I I I ~ I, I
I

SDCLOW-+,

I
I

I I

I I I
I I I I I I I
I I I I I I I I I I I I
IDEN
I
LATCH
I I I~l I~I I~I I
HOLD
~If': ~
~
I
SCLK
I 1'1' I I'l' I I'l' I I'l\SDATA
I I I, I I I I I I I I I
A01
I I II I I ,I I I I I I I
I I I 'I I I I I I I I I
AOEN*
I I I" I I I I WI I \..1...1 I I \.W I I
I IV/ I rSLOT2~ lOX I SLOt1 16 XI sLdT2 115 XISLOh 16 x:t::
ARB(S .. O>* I
I I 1//1 I I I Wi I I I I I I I
A01*
I I
1\02*
:
: : : : : :
:
I I :
A03*
I
I 1 - 8 BCLKS--\ I I I I I I I
RST

1':

If' : If'+=

:t::

~;:

Figure 4-6. IDGEN Timing Diagram

5-34

AP-422

chip name PAL16R8
BCLKIN RST SDCLOW HOLD LATCH AD16 IC7 IC8 IC9 GND
JOE AD17 AD18 AD19 AD20 SCLK SDATA IDEN2 IDEN VCC
equations
/IDEN
:= SDCLOW
+ /RST
/IDEN2

SDCLOW

+ /RST
/SCLK

:= /HOLD
+ LATCH
+ SCLK
+ /IDEN

/SDATA

/AD20

+ IDEN
+ IDEN
/AD20

+
+
+
+
+
/AD19

/AD18

* IDEN * SCLK
SCLK * SDATA
/SCLK * /SDATA

HOLD * /LATCH
/AD20 * /AD19 *
/AD20 * /AD19 *
LATCH * /AD20 *
/HOLD * /AD20 *
/IDEN

:= /AD20 * /AD19
+ /IDEN
+ HOLD * /LATCH *
+ /AD19 * /AD18 *
+ LATCH * /AD20 *
+ /HOLD * /AD20 *

jAD20 * /AD18 * /AD17
/AD17
/AD19 * /AD17
/AD19 * /AD17

:= /IDEN
/AD19 * /AD18
HOLD * /LATCH
/AD20 * /AD18
LATCH * /AD20
/HOLD * /AD20

/AD17
/AD20 * /AD19 * /AD17
/AD17
/AD19 * /AD18
/AD19 * /AD18

+
+
+
+
+
/AD17

* /AD19 * /AD18 * /AD17
/AD18
/AD17
/AD18 * /AD17
/AD18 * /AD17

*
*
*
*
*

/AD18

+
+
+
+
+
+
+

/IDEN
LATCH * /AD20 * /AD19 * /AD17
/HOLD * /AD20 * /AD19 * /AD17
/AD16 * /AD20 * /AD19 * /AD17
HOLD * /LATCH * /AD20 * /AD19 * /AD18 * AD17
/AD20 * /AD19 * AD18 * /AD17
/AD20 * AD19 * /AD18 * /AD17
AD20 * /AD19 * /AD18 * /AD17

Figure 4-7.

Equations for IDGEN PAL16R8A

5-35

AP-422

ADDRESS
00000000
00110101
00110110
00110111
00111000
00111001
00111010
10111010
00100001
01100001
10100001
00100010
01100010
10100010
00100011
01100011
10100011
00100100
01100100
10100100
00100101
01100101
10100101
00100110
01100110
10100110
00100111
01100111
10100111
00101000
01101000
10101000
00101001
01101001
10101001
00101010
01101010
10101010
00101011
01101011
10101011
00101100
01101100

. DATA
00110101
00110110
00110111
00111000
00111001
00111010
10111010
00100001
01100001
10100001
00100010
01100010
10100010
00100011
01100011
10100011
00100100
01100100
10100100
00100101
01100101
10100101
00100110
01100110
10100110
00100111
01100111
10100111
00101000
01101000
10101000
00101001
01101001
10101001
00101010
01101010
10101010
00101011
01101011
10101011
00101100
01101100
10101100

COMMENTS
;initial state
;setup state for cardslot id 21
;setup state for cardslot id 22
;setup state for cardslot id 23
;setup state for cardslot id 24
; setup state for cardslot id 2-5
;setup state for cardslot id 26
;hold state for cards lot id 26
;setup state for cardslot id 1
;latch state for cardslot id 1
;hold state for cardslot id 1
;setup state for cardslot id 2
;latch state for cardslot id 2
;hold state for cards lot id 2
;setup state for cardslot id 3
;latch state for cardslotid 3
;hold state for cards lot id 3
; setup state for cardsl~t id 4
;latch state for cards lot id 4
;hold state for cardslot id 4
;setup state for cardslot id 5
;latch state for cardslot id 5
;hold state for cardslot id 5
;setup state for cardslot id 6
;latch state for cardslot id 6
;hold state for cardslot id 6
;setup state for cardslot id 7
;latch state· for cardslot id 7
;hold state for cards lot id 7
;setup state for cardslot id 8
;latch state for cardslot id 8
;hold state for cardslot id 8
;setup state for cardslot id 9
;latch state for cardslot id 9
;hold state for cardslot id 9
;setup state for cards lot id 10
;latch state for cardslot id 10
;hold state for cardslot id 10
;setup state for cardslot id 11
;latch state for cards lot id 11
;hold state for cardslot id 11
;setup state for cards lot id 12
;latch state for cardslot id 12

Figure 4-8. IDGEN PROM Conlent (Sheel1 of 3)

5·36

AP-422

ADDRESS

DATA

10101100
00101101
01101101
10101101
00101110
01101110
10101110
00101111
01101111
10101111
00110000
01110000
10110000
00110001
01110001
10110001
00110010
01110010
10110010
00110011
01110011
10110011
00110100
01110100
10110100
00011110
01011110
i0011110
00011101
01011101
10011101
00011100
01011100
10011100
00011011
01011011
10011011
00011001
01011001
10011001
00011000
01011000
10011000
00010111

00101101
01101101
10101101
00101110
01101110
10101110
00101111
01101111
10101111
00110000
01110000
10110000
00110001
01110001
10110001
00110010
01110010
10110010
00110011
01110011
10110011
00110100
01110100
10110100
00011110
01011110
10011110
00011101
01011101
10011101
00011100
01011100
10011100
00011011
01011011
10011011
00011001
01011001
10011001
00011000
01011000
10011000
00010111
01010111

Figure 4-8.

COMMENTS

ihold state for cards lot id 12
isetup state for cardslot id 13
ilatch state for cardslot id 13
ihold state for cardslot id 13
isetup state for cardslot id 14
ilatch state for cardslot id 14
ihold state for cardslot id 14
isetup state for cardslot id 15
ilatch state for cardslot id 15
ihold state for cardslot id 15
isetup state for cardslot id 16
ilatch state for cardslot id 16
ihold state for cards lot id 16
isetup state for cardslot id 17
ilatch state for cardslot id 17
ihold state for cardslot id 17
isetup state for cardslot id 18
- ilatch state for cardslot id 18
ihold state for cardslot id 18
isetup state for cardslot id 19
ilatch state for cardslot id 19
ihold state for cardslot id 19
isetup state for cardslot id 20
ilatch state for cardslot id 20
ihold state for cardslot id 20
isetup state for arbitration id 1
ilatch state for arbitration id 1
ihold state for arbitration id 1
isetup state for arbitration id 2
ilatch state for arbitration id 2
ihold state for arbitration id 2
isetup state for arbitration id 3
ilatch state for arbitration id 3
ihold state for arbitration id 3
isetup state for arbitration id 4
ilatch state for arbitration id 4
ihold state for arbitration id 4
isetup state for arbitration id 5
ilatch state for arbitration id 5
ihold state for arbitration id 5
isetup state for arbitration id 6
ilatch state for arbitration id 6
ihold state for arbitration id 6
isetup state for arbitration id 7

IDGEN PROM Content (Sheet 2 of 3)

5-37

AP·422

ADDRESS

DATE

COMMENTS

01010111
10010111
00010011
01010011
10010011
00010001
01010001
10010001
00010000
01010000
10010000
00001111
01001111
10001,111
00001110
01001110
10001110
00001100
01001100
10001100
00001000
01001000
10001000
00000111
01000111
10000111
00000110
01000110
10000110
00000100
01000100
10000100
00000011
01000011
10000011
00000010
01000010
10000010,
00000001
01000001
10000001
end

10010111
00010011
01010011
10010011
00010001
01010001
10010001
00010000
01010000
10010000
00001111
01001111
10001111
00001110
01001110
10001110
00001100
01001100
10001100
00001000
01001000
10001000
00000111
01000111
10000111
00000110
01000110
10000110
00000100
01000100
10000100
00000011
01000011
10000011
00000010
01000010
10000010
00000001
01000001
10000001
10000001

;latch state for arbitration id 7
;hold state for arbitration id 7
;setup state for arbitration id 8
;latch state for arbitration id 8
;hold state for arbitration id 8
;setup state for arbitration id 9
;latch state for arbitration id 9
;hold state for arbitration id 9
;setup state for arbitration id 10
;latch state for arbitration id 10
;holdstate for arbitration id 10
;setup state for arbitration id 11
;latch state for arbitration id 11
;hold state for arbitration id 11
;setup state for arbitration id 12
;latch state for arbitration id 12
;hold state for arbitration id 12
;setup state for arbitration id 13
;latch state for arbitration id 13
;hold state for arbitration id 13
;setup state for arbitration id 14
;latch state for arbitration id 14
;hold state for arbitration id 14
;setup state for arbitration id 15
;latch state for arbitration id 15
;hold state for arbitration id 15
;setup state for arbitration id 16
;latch state for arbitration id 16
;holdstate for arbitration id 16
;setup state for arbitration id 17
;latch state for arbitration id 17
;hold state for arbitration id 17
;setup state for arbitration id 18
;latch state for arbitration id 18
;hold state for arbitration id 18
;setup state for arbitration id 19
;latch state for arbitration id 19
;hold state for arbitration id 19
;setup state for arbitration id 20
ilatch state for arbitration id 20
ihold state for arbitration id 20

Figure 4·8.

IDGEN PROM Content (Sheet ~ of 3)

5-38

AP-422

CCLK

2
4
6
8

BCLK

~
BUSERR*

.~~~~------~

18 CCLK1*
Y1*
16 CCLK2*
Y2*
14 BCLK1*
Y3*
12 BCLK2*
Y4*

P1 C6, P1. A6

BCLK<1,2)*

BCLKIN
2,3 ,4

BUSERR

=-----------------------------------------------~~~~----__e. 3

74AS1004
U1

PROT
DC LOW
RST
TIMOUT

P1 C4, P1. A4

74AS1004

G*
74F240
U2

11>2

P1.C23

A1
A2
A3
A4

17
15
13
11
19

A1
A2
A3
A4

Y1*
Y2*
Y3*
Y4*

PROT*

3
5
7
9

DCLOW*

P1 B1

RST*

P1. 82

TIMOUT*

P1 823
P1. AS

G*
74F240
U2

SC<4 2,0

P1 A29,P1.B29
P1 .C29,P1 B32
AD<;10 1)
AD1
AD2
AD3
AD4

2
A1
4
A2
6
A3
8
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16 AD2*
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16 AD18*
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14 AD19*
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Figure 4-2.

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CSM Functional Scbematic Diagram (Sheet 2 of 4)

5-40

74AS74
U17

SRST

Ap·422

2
1

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2
3
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6
7
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14
15
16
17
18
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1/01
1/02
1/03
1/04
1/05
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~
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CSM Functional Schematic Diagram (Sheet 3 of 4)

5-41

ARB

74F240

Figure 5-2.

CSM Clock Jumper

5-43

BClK1N

>0------

AP-422

5.2

System Diagnostic Options

For system test and diagnostic purposes, it may be
desirable to provide for the capability of selecting
other signal frequencies to exercise the clock
drivers. For example, outputs from the frequency
divider used in the design example could be selectivefy jumpered as inputs to the BCLK* and
CCLK* line drivers.

A bus timeout disable function may also be desirable. Such a function can be implemented by providing an additional input to the TOGEN state
machine driven by either the interconnect controller or jumper selectable.

5.3

CSM Functions on the Backplane

By removing the PBI function and interfacing
directly to an agent's PSB interface, the design
example in paragraph 4 could be added to almost
any type of MULTIBUS II agent. As mentioned
in paragraph 3.0, this agent might be a CPU board
or a simple 1/0 replier device, which may contain
other I.entralized system services. .
The IEEE 1296 specification does not preclude putting slot 0 on the reverse side of the backplane. The
minimal functionality described here will fit onto a
small printed circuit card mounted on the reverse of
the backplane - this does, of course, require a backplane designed for this application but if you are trying to squeeze an "extra" slot into a 19 inch rack, this,
can be accomplished.

5-44

APPLICATION
NOTE

AP-423

January 1, 1988

The MUL TIBUS®II
Interconnect Design
Guide

Jory Radke - Modules Development Engineer
Roger Finger - MULTIBUS® II Technical Marketing Manager

©Intel Corporation, 1988

Order Number: 280640-001

AP-423

PREFACE
THE ORIGINS OF INTERCONNECT

Interconnect arose out of a need to make complex technology easier to use. Advanced computer boards of
the early 1980's were becoming more sophisticated and complex. Wiring options permitted interrupt
routing, memory mapping, EPROM size, and the use of other user installed components. When the jumper
count hit 300, it no longer made sense to waste this board space because an inexpensive controller or
co-processor could be used to manage resources more intelligently. What evolved was a concept of selfconfiguration on a scale that had never before been attempted - the standardization of an entire industry.
Our Message Passing Coprocessor (MPC) design team was composed of a group of senior design engineers
and architects at the Intel factory in Hillsboro, Oregon and a second group of engineers in Swindon,
England who had experience with custom and semi-custom design of Application Specific Integrated
Circuit (ASIC) components. The bus interface was partitioned into the primary functions of bus and DMA
control, message passing, and interconnect. At Intel, this was implemented with the 82258 Advanced
DMA Controller (ADMA) and an 8751 Microcontroller as "partner chips" to the MPC. In the vendor
community, all sorts of creative solutions then began to appear. The simplest designs used PROMs or
Programmable Array Logic (PAL) to implement the barest subset of the interconnect design specification.
To reduce cost of the board, other interconnect designs were based on using the CPU as the interconnect
controller. By far the most common approach with intelligent boards was to go with the 8751 (or
equivalent) and the MPC. The direct interface between these two controllers predisposes one to selecting
these components. But what about firmware?
Early endeavors in micro controller firmware led to mixed results. Suddenly there were no jumpers to play
, with and if you wanted to change something, you had to reach inside the firmware. A new set oftools were
needed. These tools turned out to be software utilities, operating system services, intelligent device drivers,
debuggers, and a system confidence test. With each new board produced, we learned a little more about this
amazing environment that had been created as a result of interconnect. An example is the Firmware
Communication Record found on many Intel boards. It was originally provided as a "scratch pad" of
register space with no dedicated function. To date, it has been used for downloading of code to remote
agents, the passing of initialization parameters to I/O controllers, a backplane debugger console, and for
issuing requests for bootstrap.
'
Gradually a core of firmware routines developed which would be reusable on many board types. Jory
Radke had the responsibility to develop the firmware on several Intel boards during the period between
1985 and 1986. To make his job easier, he developed a set oftable driven configuration routines that provide
the basic core functions of interconnect. Being an avid (did I say rabid?) macro fan, Jory exploited every
conceivable feature of the ASM~51 and RL51 development tools. The result is the firmware that you see
today.
In the waning days of 1987, I was preparing for my Intel sabbatical when I first heard of Jory's work. I was
so enthused by the possibility of a "universal" solution to-the interconnect problem that Jory and I
approached management about commissioning this project. John Hyde and Len Schulwitz obtained the
necessary approvals and the writing began in earnest. Many Intel employees use their sabbatical time to
write books, spend time with the family, or to travel to new places. I had already been selected to participate
in a new "Intel China Ambassador" program and was about to travel all over the Asia Pacific region.
Portions of this document were written in Alaska, Hawaii, Japan, and China - usually at an altitude of
about 30,000 feet. The bulk was written in one marathon 10 hour layover in Tokyo's N arita airport. I wish
to thank the many people throughout the world who lent me the,ir personal computers, thereby enabling

5-46

AP-423

this Application Note to get written. Also, thanks to the spec writers who gave us a reasonably clear view of
what we were building, but left enough latitude for creativity.
Our foremost concern is for compatibility between vendor products. On February 22, 1988 this concept was
put to the test. The occasion was the BUSCON Trade Show in Anaheim, California where 15 MULTIBUS®
II vendors demonstrated their products - all operating in the same chassis! Both interconnect and
message passing were proven to work between a wide selection of products. MULTIBUS II had achieved,
in two years of production, what other busses have yet to accomplish.
As this firmware propagates its way into new vendor products and in-house designs, yet another
generation of compatible products will be born. We hope you find it useful in your own designs.
Roger Finger
MULTIBUS® II
Technical Marketing Manager
Jory Radke
Modules Development Engineer

5-47

AP-423

CHAPTER 1
INTERCqNNECT ADDRESS SPACE ON MUL TIBUS® II
1.1

WHO SHOULD READ THIS
DOCUMENT?
.

The primary audience of this document consists of
companies and individuals who are in the process
of designing their own MULTIBUS II boards for
use with other compatible products. It is assumed
that the reader has already studied the Interconnect Interface Specification and has a good working knowledge in the operation of interconnect
space on existing Intel products. In addition,
portions of the IEEE 1296 specification and the
MPC User's Guide are referenced in some detail. A
complete bibliography of recommended reading
material is contained in Appendix A.
This design package consists of two related items.
The first item is the document you are now reading
which is a user's guide to the overall design
process. The second item, is a diskette containing
copyrighted software to be used in generating new
firmware for your interconnect subsystem. This
package is not intended for users to change the
content of micro controllers already installed on
Intel boards. '

1.2

CONFIGURATION ISSUES IN
MICROCOMPUTER BASED
SYSTEMS

Over the past few years, microcomputer designs
have progressed dramatically in capability and
performance. In contrast, little progress has been
made in enhancing ease-of-use. Until recently,
board users have had to deal with the added
complexity of modern single-board computers by
wading through lengthy reference manuals and
innumerable jumper options - often arriving at
the final solution only by trial and error. System
integrators often found that the firmware revision
number penciled in on the EPROMs they installed
did not match the device driver revision and
consequently, nothing works! Worse yet, things
might work for a little while and then fail; resulting in wasted time debugging the problem to
determine what went wrong. Memory mapping

options, arbitration priorities, interrupt levels, and
scores of other "tunable" parameters contribute to
the fray, leaving the system designer befuddled
and confused. Often, the only way out of this mess
was to locate a board that was already properly
configured and copy off the jumper list.
Board designers build in numerous options so their
products can be used in the broadest possible spectrum of applications. The number of options
offered is not the core of the problem, but managing them is. MULTIBUS II addresses this problem
with a special address space known as "interconnect". Now for the first time, system-wide configuration information has been made accessible to
software; thereby opening opportunities for centralized control and coordination. In most
cases, the end user of these products will be completely unaware of the configuration process. They
simply remove the board from its shipping container, install the proper firmware, plug it into a
free cardslot in the backplane, and apply power.
Things work the first time around with no mess, no
fuss, and no configuration errors.
Interconnect is great for end users; it eliminates
most of the common configuration errors, speeds
up the installation process, and facilitates diagnostics and repair. When considered in the context of
an overall system architecture that includes message passing, interconnect is one ofthe foundation
building blocks distinguishing MULTIBUS II as
an environment capable of satisfying the most
demanding of applications.

1.3

OVERVIEW OF INTERCONNECT
ADDRESS SPACE

Interconnect address space is a fundamental part
of the IEEE 1296 specification, which defines
MULTIBUS II. Interconnect address space was
included in the IEEE 1296 specification to solve
three major problems: board identification, configuration, and diagnostics. The board identification
registers are read-only locations containing board
information such as type, manufacturer, compon-

5-48

AP-423

ents installed, and other board specific functions.
The configuration registers are read/write registers which allow the system software to set and
change the configuration of many on-board hardware options. In most cases, hard-wired jumper
options can now be eliminated in favor of software
control. The diagnostic registers are used for the
starting, stopping, and status reporting of self-contained diagnostic routines supplied with each
board. These diagnostics are commonly known as
Built-in Self Tests (BISTs).

1.3.1 Geographical Addressing
Interconnect is based on the fundamental principle that you can locate boards within a backplane
using a system of cardslot numbering. This concept, known as geographical addressing, is a very
useful tool during system-wide initialization. Each
board in the system contains firmware which
conforms to a standardized header format (figure
1-1).

Figure 1-1.

At boot time, the system software will scan the
backplane to locate its resources before loading in
the device drivers. This approach eliminates the
need for reconfiguring the software every time a
new board is introduced into the backplane. It also
solves the problem of how to configure multiple
instances of controller and processor boards in
large multiprocessing systems. Cardslot independence is achieved by having all boards in the
system carry their own initialization and diagnostic functions on-board in firmware. Operating
systems can generate a map of where resources are
located during initialization and then use this map
as a base address list for message passing.

1.3.2 Microcontrollers in the Bus Interface
Most MULTIBUS II designs are based on a highly
integrated bus interface controller known as the
Message Passing Coprocessor (MPC). Special provisions have been made in the bus interface silicon
to enable board designers to implement intercon-

Interconnect Overview

5-49

AP-423

nect in a cost effective manner. A typical
MULTIBUS II interface consists of the MPC, a
small number of bus transceivers, and a microcontroller such as the Intel 8751 or equivalent (figure
1-2). It is the microcontroller (in association with
the MPC) that has the responsibility for all interconnect functions.

local CPU and to the Parallel System Bus (iPSB).
Figure 1-3 shows that these two interfaces are
addressed in slightly different ways. A complete
interconnect address on the iPSB consists of a
cardslot ID plus a register offset. These values are
combined into a single 16-bit address field written
to the iPSB by the MPC when an interconnect
cycle is requested.

AS.SEEN FROM THE iPSB BUS:
BIT 15

BIT 10

BIT2

SSSSS

RRRRRRRRR

SLOT

ZEROS

AS SEEN FROM THE LOCAL CPU:

Figure 1-2_

Hardware Support for Message
Passing

Microcontrollers are ideally suited for this type of
work because they are independent self-contained
computing devices and require no external support
chips outside of a clock crystal. Their architecture
provides separate address spaces for on-chip ROM
(4 kbytes) and RAM (128 locations), as well as
three 8-bit bidirectional I/O ports. The ROM locations are used for program stor~ge, constants, and
read-only registers within the interconnect template. The RAM locations are used for read/write
registers and as temporary storage. Port pins
provide the interface to the real world; sampling
test points, latching address terms into comparators, and controlling other devices on the board.

1.3.3 Addressing of Interconnect
Before discussing how to address interconnect
registers on various boards, it is important to note
that all interconnect implementations are dualported. Dual porting consists of an interface to the

PORT 30H:

PORT 34H:

Iss s S S R R R

PORT 3CH:

I D D D D D D DO IICDAT

Figure 1-3.

R RR RR Raa

IIC ADDR LO
IIC ADDR HI

Interconnect Addressing

To generate an interconnect request, the local CPU
writes the lower 8-bits of the interconnect address
to a reserved I/O location (IC ADDR LO - usually
30H), and writes the upper 8-bits of the interconnect address to a second reserved location (IC
ADDR HI - usually 34H). If it is an interconnect
read operation, then the data can be read from a
third reserved location (IDAT - usually 3CH). A
write operation to the IDAT location will generate
an interconnect request bus cycle on the iPSE.
One special case involves a CPU attempting to
·program its own on-board interconnect registers.
As the CPU drives an interconnect address onto
the bus, its transceivers wait for a handshake from
the replier board. But since an CPU cannot hand. shake with itself, such a transaction would be invalid and an error generated. Whenever a' CPU is
programming its own interconnect registers, a
cardslot address of 31(lFH) should be used. This
instructs the MPC to pass the request directly to
the local microcontroller without going through
the iPSB interface.

AP-423

Another special case is when sub-buses such as the
Local Bus Extension (iLBX'M), are attached to the
primary agent. Interconnect facilities should be
provided for these boards and the addressing on
the sub-bus begins with cardslot number 24 (Le. the
primary agent), and proceed upwards to cardslot
number 30.

1.3.4 Data Structures in Interconnect
The objective of interconnect address space is to
allow higher level software to gain information
about the environment in which they operate
independent of who manufactured the board, what
functions it contains, and what cardslot it resides
in. To accomplish this goal, an Interconnect Interface Specification has been published and forms

the basis for much of the information in this guide.
If you have not yet read this document, you should
do so before beginning your design effort.
Interconnect functions implemented on Intel's
single board computers go beyond the requirements of the IEEE 1296 specification. This specification mandates that all conforming products
include an Interconnect Header Record. The
header record consists of information regarding
board type, its manufacturer, what firmware is
installed, and other relevant information. An example header record is shown in figure 1-4. In addition to the header record, the manufacturer may
also supply additional function records which
make other features of the board accessible
through interconnect.

HEADER RECORD
VENDOR ID, LOW BYTE
VENDOR ID, HIGH BYTE
BOARD ID,CHARACTER 1
BOARDID,CHARACTER2
BOARDID,CHARACTER3
BOARDID,CHARACTER4
BOARD ID, CHARACTER 5
BOARDID,CHARACTER6
BOARDID,CHARACTER7
BOARDID,CHARACTER8
BOARDID,CHARACTER9
BOARD ID,CHARACTER 10
RESERVED
RESERVED
RESERVED
RESERVED
TEST REVISION NUMBER
CLASSID
RESERVED
RESERVED
RESERVED
RESET STATUS REGISTER
PROGRAM TABLE INDEX
NMI ENABLE REGISTER
GENERAL STATUS
GENERAL CONTROL
BIST SUPPORT LEVEL
BIST DATA INPUT
BIST DATA OUTPUT
BIST SLAVE STATUS.
BIST MASTER STATUS
BISTTEST ID

Figure 1-4.

PROTECTION RECORD
32
33
34
35

PROTECTION RECORD TYPE
RECORD LENGTH
PROTECTION LEVEL REGISTER
RESERVED

iPsa CONTROL RECORD
36
37
38
39

iPSB CONTROL RECORD TYPE
RECORD LENGTH
iPSB SLOT ID NUMBER
IPSB ARBITRATION ID NUMBER

LOCAL PROCESSOR RECORD
40
41
42
43
44

LOCAL PROCESSOR RECORD TYPE
RECORD LENGTH
LOCAL PROCESSOR CONTROL
LOCAL PROCESSOR STATUS
RESERVED

END OF TEMPLATE RECORD
45

END OF TEMPLATE RECORD TYPE

Function Rec~rds in the Interconnect Core Firmware

5-51

AP-423

Function records begin with a byte specifying the
record type followed by the number of bytes that
make up the record. The manufacturer must publish a description of these function records in their
reference documentation. Many types of function
records have already been defined. Some examples
include memory configuration, parity control,
serial liD, and other commonly used functions. If
the existing record types do not adequately describe a function, a new record type can be defined
- up to a maximum of 1020 different record types
are allowed.
The system software initiates the search for a spespecific function record at interconnect register 32,
which is the first function record following the
header record. The program first checks the record
type field and then counts bytes to the next record
type field until either the correct function record is
found or the End of Template (EDT) record (hex
value OFF) is encountered.

1.3.5 Access Rights and Protection
Records
Because the interconnect registers are dual-ported,
each has a set of static and dynamic access rights
that determine which operations will be allowed
on either the local or iPSB bus interface. All
interconnect registers can be read from either bus,
however, static access rights may place restrictions on whether a register can be written to from
either interface. The term "static" is used because
these access privileges are predetermined by the
'designer of the interconnect firmware and will not
change during system operation. In other situations it may be desirable to allow a register to be
modified during system initialization; then locked
against further changes during normal system
operation. This capability is essential since many
of the functions contained in interconnect are so
vital to correct system operation that some means
of protecting them from malicious or inexperienced users is required.
Dynamic access rights are determined by protection records which are used to prevent other
boards from modifying a local interconnect
resource. When activated, all subsequent records
become read only so other users can read from
interconnect registers, but cannot write to them.

1.3.6 Diagnostic Philosophy of

MULTIBUS® II
The diagnostic philosophy of MULTIBUS II is
that each board should have the capability to test
itself and report error status when problems exist.
There are two occasions when diagnostic testing is
invoked. A subset of the complete on-board diagnostics is run during power-on initialization and
more extensive testing c!ln be invoked from the
operator's console. Following power-on, most
boards go through a series of initialization checks
where the basic functioning of the MPC and
microcontroller are verified. Initialization is followed by a power-on test suite automatically invoked by each board. If a hardware failure is
detected at this point, a yellow LED on the front
panel will illuminate so that the ,failing module
can be easily identified and replaced.
Iffurther testing is desired, extended diagnostics
can be invoked by placing a diagnostic request
packet in the interconnect BIST registers. Usually
one board acts as the Master Test Handler and
requests services from other system boards functioning as Slaves when under test. A menu oftests
is available via interconnect. This test philosophy
can be applied on-site by the end·user, service
representative, or remotely executed via modem
from the regional repair center. In most cases,
downtime is minimized by sending out a replacement board and thus avoiding an expensive repair
call.
The firmware content of MULTIBUS II boards is
much greater than that found on previous industry
standard buses. In addition to the 8751 Microcontroller, MULTIBUS II boards normally host
EPROMs that contain extended diagnostics
(BISTs), test handlers, reset initialization sequencing, debug monitors, and many other functions.
The location of diagnostic firmware on a board
(figure 1-5) is dependent on code complexity and
execution speed. For simple replier agents, the
microcontroller's on-board EPROM may have
enough program storage space for diagnostic functions as well as the interconnect firmware. In
contrast, the majority of the requestor/replier
boards (i.e. capable of becoming bus masters), are
more complex and most diagnostic code is run on
the CPU from on-board EPROM. In this case, the
microcontroller primarily serves as the communication interface for the diagnostics.

5-52

AP-423

1.5

c c

RESET INITIALIZATION
DIAGNOSTICS
TEST HANDLERS
DEBUG MONITORS
BOOTSTRAP LOADER

Although many implementations of interconnect
are possible, it was necessary to restrict the scope
of this guide to satisfying the broadest and more
typical range of users - designs based on the MPC
component in association with an 8751 Microcontroller (or equivalent). This design guide is intended as a generic sol ution that meets the needs of
most of these users.

ON-BOARD EPROM

f c

For software development, it will be necessary for
you to obtain an IBM® PC (model XT, AT, or
compatible) plus the appropriate Intel programming languages and a PROM programmer to
transfer your code into the microcontroller. An incircuit emulator is not required for this project;
however, some users will find it expedient to make
use of such a tool since it simplifies debugging and
eliminates the need for PROM programming while
the code is being developed. A complete list of
hardware and software requirements may be
found in Chapter 2. Any departure from the recommended development tools or practices is outside
the scope of this document and may lead to
unpredictable results.

INTERCONNECT
SUBSYSTEM

8751 MICROCONTROLLER

Figure 1-5. Firmware Content of
MULTIBUS® " BOARDS

1.4

ASSUMPTIONS REGARDING YOUR
OPERATING ENVIRONMENT

INTERCONNECT - THE
MANUFACTURER'S
PERSPECTIVE

From the perspective of a board designer, interconnect is a mixed blessing. The board manufacturer
is certain to enjoy the benefits of reduced support
costs, easier fault isolation in field repairs, and
enhanced customer satisfaction - but these advantages do not come free. One would anticipate
longer development time, increased on-board
part count, and the firmware configuration to
increase the amount of effort it takes to prepare a
MULTIBUS II board for market. And indeed this
is so. If a competent design team were to tackle the
interconnect subsystem (including diagnostics, hardware, and firmware design), it would not be unreasonable to allow six man-months for the job.
Given that this represents an extraordinary investment for the manufacturer, the primary goal of
this design package is to reduce the amount oftime
required to include interconnect in your design
from six months to only six days! Another goal is
to guarantee compatibility and interoperability of
your products by placing common core functions
in user extensible firmware in such a way that it is
easy to customize the design to fit your own
particular needs.

5-53

1.6

DESIGN METHODOLOGY - AN
OVERVIEW

The process of designing an interconnect subsystem invariably begins with a high level discussion of what function you intend to support. While
the header record is quite easily defined, decisions
as to what function records to include should be
carefully considered in terms of how much flexibility to give your users, what functions they
might be interested in, and how much external
hardware will be required. Some of the function
records listed in the Interconnect Interface Specification are already implemented in the core firmware
and require minimal effort to support. Other functions may be quite complex and could potentially
require extensive TTL circuitry external to the
micro controller. As with all engineering designs,
you should spend a significant portion of your time
making sure that you have a clean workable
specification before proceeding into the implementation phase.
The second step in interconnect design is to determine what circuitry is required to gain access to
the information in interconnect that you intend to

AP-423

present to the user. This consists oflocating all test
points, control circuitry, latches, and transceivers
external to the microcontroller. Most likely this
determination will be made at a point where the
overall schematic for the board is near completion
and before you begin the layout and develop the
prototype. At this stage, all dedicated I/O addresses will be defined and rudimentary PAL
equations for the control points will be written.
The third step of interconnect design consists of
evaluating your on-chip resource requirements
based on the function records being implemented.
At this stage, you will write the functional routines
and identify the RAM, ROM, and port requirements for the micro controller. If your original
interconnect specification was over ambitious or
inappropriately defined, you will discover at this
point that you may be forced into external PROM,
static RAM, or port expansion logic; and may wish
to scale back your design or change over to the
8752 Microcontroller (having 8 kbytes of ROM and
256 bytes of on-chip RAM). Once you know your
resource requirements and have written the functional routines, you are now ready to integrate
your custom code with the cote interconnect firmware.
The fourth step in the design process consists of
loading the tables with data based on the interconnect template you specified in step one, plus the
external declarations for the routines you wrote in

step three. The object code supplied on the diskette
with this guide contains a table driven collection of
routines that provide the core interconnect functions. These give the user some commonly used
function records (figure 1-4) and provide the opportunity for users to add their own routines to this
core. Generating the firmware consists of assembling your code and then allowing the table generators to integrate this code into the core module
through an ASM-51 macro expansion process.
Once complete, the entire package is integrated
using RL51 (a relocation linker) to resolve any
external references and produce a unified object
module for loading into the microcontroller
EPROM.
The final step in the process is to program the
microcontroller and test every imaginable function and event sequence within interconnect. It is
at this stage that the use of an in-circuit emulator,
logic analyzer, or oscilloscope may be desirable to
help in localizing logic faults or timing related
problems. In most cases, debug time is fairly short
since the core routines are supplied already and
are known to be good.
Once the interconnect subsystem is totally tested,
the board can be forwarded to the device driver
development team and/or system integrator for
initialization software development and further
functional testing.

5-54

AP-423

CHAPTER 2
PREPARATION FOR USE
2.1

HARDWARE AND SOFTWARE
REQUIREMENTS

2.2

Before proceeding with your interconnect design
using this guide, the hardware, software, and
optional equipment listed below are required (at a
minimum).
Hardware Requirements:
o

IBM® PC (model XT, AT, or compatible) configured with at least 640 kbytes of internal
memory and a 10-Mbyte (or larger) hard disk.
Intel PROM Programmer, model iUP 201, plus
the 8751 Microcontroller Personality Module
and a serial cable. The IBM PC must have a
spare serial port to interface with the PROM
Programmer. (Note that other brands of
PROM Programmers can be used, but the
batch files and object module produced by
Intel's development tools are not guaranteed to
be compatible.)

LOADING SOFTWARE ONTO YOUR
SYSTEM

Before starting, it is assumed that you will have
already loaded the ASM-51 and RL51 program
files in a common subdirectory of the hard disk
and have indicated the route to that subdirectory
in a PATH command entered into the
AUTOEXEC.BAT file (in the root directory). This
will allow you to call these program files from any
point in the file structure without having to identify the directory search path to these files.
Install the software supplied with this design
guide onto your hard disk by inserting the interconnect firmware diskette into drive A or B. After the
C> prompt, type A (or B): to change the default
drive. Next type INSTALL and then press Enter.
The computer will read from the drive specified
and immediately start executing the install. bat
batch program. When this batch program completes processing, you will find the following added to the subdirectory structure of your
hard disk:
ICFW

Software Requirements:
c

DOS Operating System, version 3.0 or greater

iPPS PROM Programming Software, version
2.2 or greater·

•

ASM-51 Macro Assembler version 2.2 or
greater

•

RL51 Relocation/Linkage package version 3.0
or greater.

Optional Equipment:
•
•

ICET" 51 (or ICE 5100) In-Circuit Emulator
with IBM PC Interface Card
Oscilloscope.

5-55

ICU
IC.P28
IC.DCL

DOC
CORE.DOC
PUBLIC.DOC
SRC

OBJ
CORE.LIB

ASMMOD.BAT
LNKUSR.BAT
DFT.MOD
USER.MOD
TABLE.MOD
EETGEN.A51
TABGEN.A51
TABLE.MAC
GLOBAL. MAC
USEFUL.EQU

LST
(no files)

Batch files are supplied to automate the firmware
generation process. These files make some assumptions about your hard disk directory structure. It is

AP-423

important to note that all batch files must be called
from the \ICFW\SRC directory path, otherwise
the DOS command processor will not look beyond
your current directory in its search for a file name.
Edit the path command in your AUTOEXEC.BAT
file to include the \ICFW directory.

2.3

displayed, then type CD\ICFW\SRC and
press Enter to change to the correct directory
path.
b. Run the following batch programs in the order
listed:
ASMMOD
ASMMOD
ASMMOD
LNKUSR

INTERCONNECT THE EASY WAY

While interconnect is a complex topic, there is an
_easy way to get a functional interconnect subsystem operational without detailed knowledge of
the internal design. To do this, view the file
\ICFW\SRC\ TABGEN.A51 using the TYPE command or a text editor and notice that the data fields
for vendor II), board ID, hardware test revision,
and class ID have been left blank (looking ahead,
this is figure 5-1). Consult the Interconnect Architectural Specification to determine what information to place in these fields. Once you have obtained this information, perform -these steps at
your computer console:
a. Type CD and then press Enter to -display the
current directory. If \ICFW\SRC is not being

dft
user
table
test

The result is a PROMmable object code file
(TEST.LNK) that is placed in \ICFW\SRC\OBJ
subdirectory. The TEST.LNK object code is ready
to burn into the micro controller EPROM and provides a complete interconnect header record as
well as protection, iPSB control, and local processor records.
The core hardware design consists of the minimum interconnect implementation as shown in
figure 4-1. This' basic combination of hardware
and firmware can be used during prototyping as
the starting point for most interconnect designs.

5-56

AP-423

CHAPTER 3
THEORY OF OPERATION
3.1

MPC TO MICROCONTROLLER

requested to review chapters 4 and 5 of the MPC
User's Manual before continuing further.

HARDWARE INTERFACE
Most MULTIBUS® II designs use the Message
Passing Coprocessor (MPC) component with an
8751 Microcontroller to implement the Parallel
System Bus (iPSB) interface. This combination
minimizes the number of devices required to implement a full-featured bus interface and provides
. flexibility in adapting the design to the broadest
possible range of functional specifications. The
hardware interface between the MPC and the
microcontroller is shown in figure 3-1.

8751
~

•
IAD<7 .. 0>
•
"

IREQ*
IRD*
IWR*
lAST

3.2

MPC INTERCONNECT BUS
REGISTERS

The MPC component contains a set of special
function registers that are only accessible via the
lAD bus. These registers (figure 3-2) can be catagorized into five functional groups: interconnect reference registers, slot and arbitration ID registers,
configuration registers, diagnostic registers, and
the no access registers.
The MPC interconnect reference registers serve as
the basic communications interface between the
microcontroller and the MPC. Whenever the local
CPU or iPSB agent generates an interconnect
request cycle, the registers actually being accessed
(IC ADDR HI, IC ADDR LO, IDAT) physically
reside in the MPC rather than in the microcontroller. The MPC asserts the IREQ* signal to
interrupt the micro controller which responds by
initiating a dialogue of read/write commands to
the MPC interconnect reference registers.

MPC

i.....--

Figure 3-1.

MPC to Interconnect Pathway

The MPC is designed to sit directly on the microcontroller's multiplexed Interconnect Address/Data
bus (IAD<7 .. 0». When an interconnect cycle is
initiated, the IREQ* signal from the MPC interrupts the microcontroller with a request for services. The microcontroller then performs a series of
read and write operations to a group of MPC
interconnect bus registers to satisfy the interconnect request and complete the operation. In terms
of hardware control, the micro controller acts as
the bus master on this interface; generating the
read and write signals, and supplying an Interconnect Address Strobe (lAST) based on its own
Address Latch Enable (ALE) signal. The reader is

5-57

The second functional group of MPC interconnect
registers are concerned with the cardslot and
arbitration ID assignments made by the Central
Services Module (CSM) during reset initialization.
Note that the Interconnect Interface Specification
describes an iPSB Control Record which includes
registers for both arbitration and cardslot ID. This
allows a CPU to determine in what cardslot it is
residing.
The third functional group of MPC interconnect
registers control configurable features on the MPC
such as dual-port address boundaries, arbitration
priority, Reset-Not-Complete (RSTNC) control,
error reporting, and fail-safe counter functions. In
most implementations, these registers are passed
through an interconnect function record to make
them user accessible and configurable.

AP-423

,-----------------

---.-

REFERENCE REGISTERS
OE1 H
OE2H
OE3H
OEOH
OE1 H
OEOH

INTERCONNECT SLOT ADDRESS (IC ADDR HI)
INTERCONNECT REGISTER ADDRESS(IC AD DR LO)
INTERCONNECT DATA (IDAT)
INTERCONNECT STATUS (ISTAT)
INTERCONNECT COMPLETE (ICMPL)
INTERCONNECT REFERENCE ARBITRATION (IARB)

OE6H SLOT ID (SID)
OE7H ARBITRATION ID (AID)

CONFIGURATION REGISTERS
OE8H
OE9H
OEAH
OEBH
OECH
OEFH
OEDH
OEEH
OF5H

DUAL-PORT LOWER ADDRESS LOW BYTE (LALB)
DUAL-PORT LOWR ADDRESS HIGH BYTE (LAHB)
DUAL-PORT UPPER ADDRESS LOW BYTE (HALB)
DUAL-PORT UPPER ADDRESS HIGH BYTE (HAHB)
GENERAL PARAMETERS (GEN)
REFERENCE ERROR (RERR)
SOLICITED INPUT FAIL-SAFE COUNTER (SIFSC)
SOLICITED OUTPUT FAIL-SAFE COUNTER (SOFSC)
REFERENCE FAIL-SAFE COUNTER (REFFSC)

ADDRESSES OOH THRU 07FH

Figure 3-2.

MPC Interconnect Registers

The fourth functional group of MPC interconnect
registers control retry and diagnostic functions.
These parameters can be used for performance
tuning and confidence testing, but are not frequently accessed by users. In general, they can be
programmed during initialization with default
values and then ignored.
Finally, there is a group of addresses between 0
and 7FH for which the MPC guarantees a tristate
condition (no access). Interconnect designers can
take advantage of this feature by using these
addresses to decode registers and latches residing
directly on the lAD bus. This technique provides a
convenient way to generate an 8-bit bidirectional

bus using user defined addresses as chip enable
terms. The reader is encouraged to read all of
Chapter 7 in the MPC User's Guide before proceeding.

3.3

PARTITIONING OF FUNCT!ONS
BETWEEN THE MICROCONTROLLER,
CPU,AND MPC

Because of the close association of the CPU and
the microcontroller to the MPC, a number of interdependencies arise - especially during initialization and diagnostic testing. Some of the more
complex functions such as dual-port memory control and fail-safe counters actually cross com-

5-58

AP-423

ponent boundaries. Thus, one must view the complete interface as a functional subsystem. The
following discussion highlights the more
important interdependencies regarding the interconnect subsystem.

contiguous memory is supported when using the
MPC dual-port functions.

3.3.3 Message Retry Operations
When message traffic is arriving faster than the
local CPU can receive it, the MPC FIFO buffers
will overflow and some form of flow control must
be initiated. The MPC has a special retry mechanism for this condition that is controlled through
registers accessible to the microcontroller. Retry is
enabled by setting a bit in the MPC Diagnostic
Parameters Register and the delay between retries
is selected in the Retry Algorithm Register. The
Accumulated Retry Count Register indicates how
many Negative Acknowledge (NACK) errors have
occurred for a given message attempt. The
Accumulated Retry Count Register is used with
the Retry Algorithm Register to tune system performance by selecting the most effective retry
interval.

3.3.1 MPC Diagnostic Testing
A special feature of the MPC is its ability to
simulate message passing operations to itself without presenting data to the iPSB bus interface. This
mode is termed "MPC Loopback Testing" and is
enabled by the iPSB Diagnostic Register in the
iPSB Control Record. This causes the microcontroller to set the Reset-N ot-Complete Out
(RSTNCOUT) bit in the MPC General Parameter
Register. The result is that any messages the local
CPU loads into the MPC transmit buffers are
routed directly to the MPC receive buffers. While
this is happening, the MPC Buffered Address/
Data bus (BAD<31..0>*) is active and it is necessary for the micro controller to tristate the iPSB
buffer logic by preventing the iPSB Transceiver
Output Enable (BTROE*) signal from going
active low. Note that MPC loop back testing is only
allowed while RSTNC* is being asserted by the
host agent.

3.3.4 Fail-Safe Counter Functions

3.3.2 Dual-Port Memory Control
When another iPSB agent selects your board to
participate as a replier in a memory reference, the
address recognition function for dual-port memory
is performed by the MPC based on the starting and
ending addresses programmed into the MPC interconnect registers during initialization. When an
address match is found, the MPC will drive the
SEL* signal to your dual-port memory controller
and wait for a COM* or ERR* signal to be
returned before completing the cycle. During this
transaction, the MPC provides all parity generation and checking, system control, and wait-state
signal generation services to the iPSB bus interface. Valid address selection may occur on any
64-kbyte boundary within the 4-Gbyte memory space;
however, it is advisable to include value checking
in your microcontroller firmware to ensure that the
user doesn't enable more memory than is physically present on the board. Only one bank of

5-59

When the MPC issues an iPSB buffer request,
there is no guarantee that a buffer grant will be
returned in a reasonable amount of time. If enabled, the MPC Reference Fail-Safe Counter will
cause an error interrupt if no buffer grant is
received by the end of a timeout period (typically
1.5 seconds). Likewise, a similar fail-safe timeout
exists for reference operations in the unlikely
event that they are unable to acquire the iPSB bus
due to arbitration or Bus Clock (BCLK) problems.
In either case, the micro controller acts as a programmable timebase by writing to the MPC failsafe counter addresses on a periodic basis in
response to an internal timer interrupt (figure 3-3).
When the MPC starts the buffer request or reference operation, it enables the fail-safe timeout and
waits for the operation to complete. If the microcontroller is able to write to a MPC fail-safe
counter address four times before the bus cycle
completes; then a timeout interrupt is asserted to
alert the CPU to the problem. Note that fail-safe
counter functions should be disabled during debugging since breakpoints set by human intervention
may prevent the MPC from completing an operation before a timeout occurs.

AP-423

3.4
TIMER INTERRUPT TO
MICROCONTROllER
MICROCONTROllER WRITES
TO MPC FAil-SAFE COUNTERS

In a MULTIBUS II backplane, the RST* signal is
used for the system-wide reset. Additionally, the
DCLOW* signal designates power-fail indication and the PROT* signal designates an early
warning battery back-up control. One of the options available to the board designer is to use combination logic in association with the microcontroller to further define three catagories of reset
conditions: cold-start, warm-start, and local reset.
In figure 3-4, the reset circuitry that gives a board
the capability to distinguish between these events
is shown. The reset control logic (in the
P AL16R4B) signals a cold-start whenever reset is
accompanied by a low power condition and signals
a warm-start in all other cases. Local resets are
generated by an interconnect operation to the
micro controller, which then pulses the CPU reset
line.

MPC
I-'--.j

ISOLICITED IN

ISOLICITED OUT I
IREFERENCE I

Upon buffer request, MPC enables Fail-Safe
Counters. If no buffer grant within four microcontroller write operations; then signal timeout
error to local CPU (typical timeout values - 1.5
sec.)

Figure 3-3.

MULTIBUS® II RESET
CONDITIONS

MPC Fail-Safe Counters

CPU

8751
CPURES P3.1
UCINT* P3.2

RESET PAL
BClK
DCLOW*
RST*

r--

r---s UCRST

" BUS
BTR
VEL
LED

-I>

===-

B§l

r--

15K ....

MPC

"""
IREO*

BAD<31 .0>* BUS

'-IWR*
IRD*
lAST
RST
1-...-

~ U~~~T*

a.B

Figure 4-1.

Interconnect Core Hardware Design

4.2.1 Microcontroller Input Options
On boards that contain user-supplied optional
devices, it is desirable to include an interconnect
status register to report whethe.r or not the device is
present. If present, system software can program
the device with the appropriate driver. Some
common examples include the Single Board Extension Bus (iSBX'M) MULTIMODULE'· compatible board products, numeric processors, and DMA
controllers.
A technique used to detect a board's presence is to
identify a port pin that ties to ground and then
have the microcontrollerread that pin. TheP1 and
P2 lines of the 8751 Microcontroller are internally pulled up, which makes module not presentfor
these lines always read a logical" 1". Verifying if a
chip is present is more difficult since the com-

5-67

ponent needs the ground pin for its own power
consumption. The preferred technique here is to
ask the user to install a jumper and in that way, the
microcontroller can report correct status.
Figure 4-2 schematically diagrams various techniques used to input to an 8751 Microcontroller. A
typical technique is to require the microcontroller
to read jumper inputs. (Although MULTIBUS® II
has reduced the number of jumpers required, it
hasn't eliminated them.) In cases where jumpers
are unavoidable (such as chip select jumpers and
component present indicators), it would be helpful
to report the state of those jumpers with an interconnect status register. An example is the EPROM
size register found on many Intel boards. If you
have only a small number of jumpers, then a direct
connection to one of the microcontroller' s port pins
will suffice. For boards with a larger number of

AP-423

POO
P01
P02
P03
P04
PO 5
PO 6
P07
P10
P11
P12
P13
P14
P15
P16
P17
8751

MPC

IAD<7..0> BUS

,SBX"

mov RO,
movx A
setb

OOh
iilRO,
P2.S

EPRO MSIZE
a1 '------<>

a2~

y3
y4

a3 '------0
84---0

JEDE CSIZE

v6 86
v7 87
v8 88 I

g* r'"--

Microcontroller Input Options

jumpers, buffering will be necessary. The buffer
output enable term is generated by a port pin in
association with the microcontroller's IRD*
signal. In the example shown, a read instruction to
P2.5 will input data from the jumpers. This could
be coded in ASM-51 as:
P2.S

v1
v2

9
Figure 4-2.

clrb

READJ UMPERS

VERIFY
CHIP
PRESENT

P2.0
P21
P22
P23
P24
P25 ~
P26
P27

RXD
P30
TXD
P31
INTO* P32
INT1* P3.3
TO
P34
T1
P35
IWR* P36
P37
IRD*
ALE/PROG*

VERIFY
MODULE
PRESENT

;activate CS for jumper
; input buffer
;load dummy address
;read jumper inputs
;deselect buffer

4.2.2 Microcontroller Output Options

Outputs from the micro controller are used at
various control points throughout MULTIBUS II
boards. Simple functions such as the LED's can
use a direct connection to a microcontroller port
pin. More complex functions will require a connection to the buffered lAD bus. As a general rule,
whenever more than two loads are on the lAD bus,

it will need buffering. The MPC must be connected
directly to the lAD bus to ensure proper timing.
The schematic in figure 4-3 diagrams some typical
applications.
4.2.3 LED Outputs

Nearly all MULTIBUS II boards contain one or
more LED indicators on the front panel. These
provide a visual indication of board activity and
status. Typically, the red LED is provided as a user
programmable indicator and is illuminated by the
setting or clearing of a bit in a control register. A
green LED is often used to indicate CPU activity.
If the green LED is present, drive it with 1m
Address Latch Enable (ALE) signal or equivalent.
The yellow LED, if present, is lit during diagnostic
testing and represents the ORed condition of the
following bits in the BIST Slave Status Register:
BIST running + BIST failed + RSTNC timeout..

5-68

AP-423

DIRECT CHIP SELECTS
AND OUTPUT ENABLES
COMPARATOR LOGIC

Pl0
Pll
P12
P13
P14
P15
P16
P17

-{>

PO 1
PO 2
roo
PO 3
P04
PO 5
P06
PO 7

P30
RXD
P31
TXD
INTO* P32
INT1* P33
P34
TO
T1
P35
IWR*
P36
IRD*
P37
ALE/PROG*

1 5K

r---

2
~

RAMDIS
P>OI
NEWADDR* .......
PLE
IWR*

-r

'----

MPC

IAD<7 •.0> BUS

ADDRESS MATCH
P>OOUT

LED OUTPUTS

P20
P21
P22
P23
P24
P25
P26
P27
8751

74AS885

RED LED

r-BIAD<7 .. 0> BUS

'--

PAL BASED

ENABLE LATCH

ADDR~ECODE

OR~ER

~
~
CS3

ALE

CS*

NOTE THEIADBUSANDCONTROLSMAY
NEED BUFFERING IFTWO OR MORE
LOADS ARE PRESENT

Figure 4-3.

Microcontroller Output Options

4.2.4 Output Enables and Chip Selects
A microcontroller port pin can be used for a bus
transceiver, ALE, or a direct chip select enable.
When used as a direct chip select, care must be
taken to guarantee proper timing and maintaining
the state relationships with the other board occupants. A common application of this technique is a
memory enable and disable signal. Direct chip
selection is also used to enable the iPSB bus
transceivers (via signal BTROE*) in the core
interconnect design.

signals can be generated using this technique.
Some designs use the chip selects to enable secondary latches and buffers. The ASM-51 coding for the
circuit shown in figure 4-3 could look something
like this:
mov
mov

ICDATA

RO.

latch_addr

movx iilRO.

;Get value being written
; load the address of the
; latch
;Generate chip select and
;write data

4.2.6 Comparators
4.2.5 Address Decode on the lAD Bus
The lAD bus address can be mapped to generate
chip selects using simple "1 of n" decoders gated
by a ALE signal. As an alternative, a PAL-based
decoder can be used. A variety of chip select

5-69

Comparators are often used for address boundary
checks in association with Local Bus Extension
(iLBXTM) or local memory. A comparator logic example is shown in figure 4-3. A select term can be
generated on greater than, less than, or equal to

AP-423

the data placed on the lAD bus. The set point for
the comparison is latched-in during the data phase
of the microcontroller's PO bus. In this way, a port
pin (the NEW ADDR* signal) can combine with
the microcontroller's IWR* to control when the
address comparison is enabled. The ASM-51 code
to load a new address into the comparator could
look like this:
mov A.
clrb
mov
RO.
movx IilRO.
setb

4.3

ICDATA
NEII_ADDR
aOh
A
NEII_ADDR

numerous port expansion techniques exist. Your
choice of which technique is best in your particular
design will be based on such factors as on board
space requirements, cost, bidirectionality, and
ease of programming. An example of interfacing a
complex peripheral to the lAD bus is shown in
figure 4-4. The ASM-51 coding for this circuit is
very straight forward since device selection is
based on an lAD bus address.

; Get the new set poi nt
;This is the PLE signal
;Durrny address
;Output the new address
;Latch it in

mov

RO.

;This is the address of
;the device
;Input from the device
;Save the data

IO..ADDR

movx A.
IilRO
mov
ICDATA. A

BIDIRECTIONAL I/O ON THE lAD

mov

RO.

IO_ADDR

mav

ICCNTR

movx

IilRO.

;This is the address of
;the device
;load a control value for
; output
;Output to the devi ce

BUS
Even a modest implementation of interconnect
can easily exceed the available port resources of
the microcontroller, especially when a byte wide
data path is required. For these applications,

P10
P11
P12
P13
P14
P15
P16
P17

MPC

P20
P21
P22
P23
P24
P25
P26
P27
8751,

PO 0
PO 1
P02
P03
P04
P05
P06
PO 7

RXD
P30
TXO
P31
INTO* P32
INT1* P33
TO
P34
T1
P35
IWR* P36
IRD* P37
ALEIPROG*

7~5

IAD<7 .. 0> BUS

A B
RD* DIR

BIAD <7. 0> BUS
ADDRESS DECODE PAL
OR "1 OF N" DECODER

CSO

ALE

~
IV
Figure 4-4.

~
~

DEVICE
__ liD
r--

CS3

CS*
RD*
WT*

---

Bidirectional I/O on the lAD Bus

5-70.

AP-423

CHAPTER 5
DEFINING THE INTERCONNECT TEMPLATE

5.1

WHAT GOES INTO
INTERCONNECT?

5.1.2 Getting Started: The Interconnect
Worksheet

The design implementation phase of your interconnect subsystem begins with a careful evaluation of
what functions to include. Common core functions
are supplied on the accompanying diskette and
you can add supplemental records to the interconnect template for board-level features you intend to
support. Many frequently used function records
are already defined in the Interconnect Interface
Specification and the reader is requested to review
this document before proceeding. If none of the
furnished function records meet your needs, you
can to create your own function record using one of
the record types available for vendor definition or
board specific functions.

Unless you are using the supplied interconnect
template without modification, it is a two-step
process to complete the configuration tables. In the
first step, you will fill-in a worksheet with information about default values, RAM usage, read/write
and edit routine n umbers, and oth~r details. Figure
5-1 is an example of such a worksheet. While
completing these tables, you might notice opportunities to reduce code size by making use of
generic read, write, and edit routines. In the second
step, the information in the worksheet is copied
into a series of tables used by the configuration
macros.

If your function record is likely to have broad

5.2

industry appeal and could be used by other vendors to support similar functions, you may wish to
fill out the petition application included with the
reader comment sheet at rear of this guide. Your
petition will be evaluated based on suitability for a
general class of hardware, industry standardization, and feedback from the MULTIBUS® II user
community, and if accepted, published in the next
revision to Interconnect Interface Specification.

THE INTERCONNECT HEADER
RECORD

The interconnect template begins with a standard
Interconnect Header Record. This record contains
fields that require specific values supplied by the
user. You should fill-in this information in as we
proceed through this chapter. For a detailed discussion concerning each register, consult Appendix A
of the Interconnect Interface Specification.

5.1.1 Core Functions Supplied
The interconnect firmware supplied with this
guide contains a group ofrecords common to most
MULTIBUS II boards containing a CPU, regardless of their specific function. These include an
Interconnect Header Record, a Protection Record,
the iPSB Control Record, a Local Processor
Record, and an End of Template (EOT) Record.
Some users may wish to generate a minimal
interconnect template on the first pass to verify the
operation of their base hardware before adding
their own advanced functions. This approach
simplifies debugging and allows new features to be
added incrementally.

5-71

5.2.1 Vendor ID Register (0-1)
Licensed MULTIBUS II vendors are assigned two
vendor ID numbers - an odd number for conforming templates and an even number for templates not conforming to the IEEE 1296 specification. You should enter your odd vendor ID
number, since this template will be conforming.
Nonlicensed users who are building custom
MULTIBUS II boards should use 65533
(OFFFDH) as their vendor ID.

AP-423

GAR

RAM

DFT

RRT

ERT

WRT

CONST

VENDOR 10, LOW BYTE

VENDOR ID, HIGH BYTE

BOARD I D, CHARACTER 1

BOARD 10, CHARACTER 2

BOARD I D, CHARACTER 3

o
o
o
o
o

BOARD ID, CHARACTER 5
BOARD ID, CHARACTER 6
BOARD I D, CHARACTER 7

BOARD 10, CHARACTER 8

BOARD I D, CHARACTER 9
BOARD ID, CHARACTER 10

0
0

I NTEL RESERVED

HARDWARE TEST REV NO.

CLASS 10

RFU

RESET STATUS RGTR
PROGRAM TABLE INDEX

OOOH

OOOH
OOOH

?
?

OOOH

o
o
o
o
o
o
o
o
o
o
o
o
o
o

OOOH

?
?
?
?
?

OOOH

003H

001 H OOOH

1
1

OOOH

001H

NMI ENABLE RGTR

OOOH

001 H 001 H OOOH

38H

GENERAL STATUS

OOOH

003H

BOARD 10,

CHAR~CTER

EET

VAR

HEADER RECORD -- - - - -- - - - - - -- - - - - - -- - -- - - - - --- -- -- - - - ---- - -- - -OOOH OOOH ?
OOOH ?

OOOH

OOOH?

OOOH

?
?
?
?
?
?
?
?
?

OOOH

?
?
?

?
?
?
?

?
?
OOOH ?
OOOH ' ?
OOOH ?
OOOH RST
001H PTI
002H NMI_EN
OOOH GEN_STS
003H GEN_CTL
004H BIST_SL
001H BIST_DI

001H 'OOOH

OOOH
OOOH

?
?
?
?
?

OOOH

DOH

OOOH
OOOH
OOOH
OOOH
OOOH
OOOH
OOOH
OOOH
OOOH
OOOH

GENERAL CONTROL

OOOH

001 H 001 H 002H

BI ST - SUPPORT - LEVEL
BIST-DATA-IN

OOOH

001H

005H

OOOH

18H,07H,04H

OOOH

001H

OOOH

DOH

BIST-DATA-OUT
BIST-SLAVE-STATUS

OOOH

001H

OOOH

DOH

010H

001H

OOOH

OOH

001H
001H

78H

?
?

BIST_DO
BIST_SS

BIST-MASTER-STATUS

020H

001H

OOOH

50H

005H

BIST_MS

BIST-TEST-ID

OOOH

001H

002H

OOOH

01H,OFEH

006H

BIST_TlD

PROTECTION RECORD TYPE

RECORD LENGTH

o
o

002H

OOOH

OOOH??

OOOH

PROTECTION LEVEL RGTR

OOOH

004H

001H

007H

UACRS

OOOH

OOOH??

PSB CONTROL RECORD TYPE

RECORD LENGTH

o
o

PSB SLOT ID NO.
PSB ARBITRATION 10 NO.
PSB ERROR RGTR

PROTECTION RECORD - - - - --- - --- - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - -OOBH OOOH OOOH??
OOOH PROT_OFF

o
o
o
o

•0
1

Figure 5-1.

OFEH

OOOH

PSB CONTROL RECORD - - - - - - -- - - - - - - - - ------ - --- - - - - - - - - - - -- - - - --006H OOOH OOOH??
OOOH PSB_CTL_OFF

PSB CONTROL/STATUS RGTR
PSB DI AGNOSTI CS RGTR

003H

006H

OOOH

OOOH
OOOH

002H
002H

OOOH
003H

?
7

OOOH

002H

001H

01FH

005H

001 H 004H

OOOH

002H

004H

OOOH

OOOH?

OOOH

?
?

OOOH
OOSH

?
?

OFFH

009H

63H

OOAH

PSB_CS

OOBH

PSB_DIAG

OOOH

Interconnect Configuration Worksheet (Sheet 1 of 2)

5-72

AP-423

ERT
WRT
CONST
EET
VAR
REGISTER NAME
GAR RAM
DFT
RRT
••••••••••••••••••••••••••• LOCAL PROC RECORD •••••••••••••••••••••••••••••••••••••••••••••
LOCAL PROC RECORD TYPE
RECORD LENGTH
LOCAL PROC CONTROL

a
a
a
a
a

013H
003H

OFFH

OOOH
OOOH
006H

OOOH
OOOH

?
?
OFEH

OOOH
OOOH

?
?
?

OOOH
001H 006H
OOCH
LOCAL PROC STATUS
OOOH 007H OOOH ?
OOOH
?
RFU
OOOH OOOH OOOH ?
?
OOOH
•••••••••••••••••••••••• END OF TEMPLATE RECORD •••••••••••••••••••••••••••••••••••••••••••
EOT RECDRD TYPE

Figure 5-1.

OOOH

OOOH??

OOOH

EDT_OFF

Interconnect Configuration Worksheet (Sheet 2 of 2)

5.2.2 Board 10 Registers (2-11)

5.3

These 10 registers contain the ASCII product code
as described in your user's manual. You should
avoid the use of non printing ASCII characters so
the system software can display the product code
verbatim on a CRT screen. If the product code is
less than 10 characters, pad the remaining register
fields with ASCII null characters (zeros).

There is virtually no limit to the number and
variety of function records that users can add to
the core firmware - provided the following
common sense guidelines are met:

5.2.3 Hardware Test Revision Number
Register (16)
This register is part of a system of control for
matching the firmware revision to the automatic
test equipment used with that board. The master or
local test handler software uses this as a mechan·
ism for revision control of diagnostics.

5.2.4 Class 10 Register (17)
Determine your class ID from the list supplied in
the Interconnect Interface Specification. The class
ID occupies the most significant nibble (4 bits) of
the register and the subclass ID occupies the least
significant nibble.

5.2.5 BIST Support Level Register (26)
The BIST Support Level Register defines the sup·
port level of the diagnostics on·board. This will
determine which commands can be issued to your
board via the BIST Data Input Register.

5·73

OPTIONAL USER FUNCTIONS

a. A maximum of 256 interconnect registers are
allowed due to the page limit length of the config·
uration tables. Most boards will need fewer than
100 registers.
b. The microcontroller you are using has certain
resource limitations - the most pressing of which
is on·chip RAM. Nested stack operations also
require RAM, so you must avoid recursive pro·
cedures and nesting of calls beyond four levels in
any of the USER code modules. Normally, it is
preferable to pass parameters in registers rather
than on the stack.
c. An interconnect request must complete opera·
tions within l·ms to avoid an iPSB timeout. The
actual time available to complete a USER routine
is less than 0.5·ms because interconnect is dual
ported and a local access can temporarily lockout
an iPSB request. A timing analysis of your design
will be done prior to PROMming the code (refer to
paragraph 5.8.2).
d. Caution must be exercised whenever the
potential for deadlock of a resource exists. Solu·
tions to this problem include prioritization, report·
ing of error status, or timeout to guarantee that
system hang does not occur.
e. User read, write and edit routines must follow
the naming convention described in this chapter to

AP-423

guarantee that the macro expansion works properly. Any global variable names used within existing core modules are considered reserved and
should not be used in your own procedures (ASM51 and/or RL51 will report duplicate symbol
errors). A list of existing public variables may be
found in program file ICFW\SRC\USER.MOD.

5.4

COMPLETING THE
INTERCONNECT CONFIGURATION
WORKSHEET

If you decided that a user-defined function record
is to be incorporated in the interconnect template,
then you must define the access rights, default
values, and complete the remaining worksheet
entries needed by the micro controller firmware to
support those features. You then write the functional read, write, and edit routines and tag them
with appropriate labels. The new function
record(s) must be inserted ahead of the EaT record
of the core interconnect template.
.

As discussed in Chapter 3, the interconnect firmware uses a series of tables to associate a register
with· the correct read, write, and edit routine
numbers. The information you supply here will be
loaded into those tables during the code assembly
process. In figure 5-2, an example of a completed
interconnect configuration worksheet for the core
firmware is shown. The parameters that must be
supplied for each interconnect register identified
on the configuration worksheet are described
below.

5.4.1 Global Access Rights
All interconnect registers are readable from both
the locahnd the iPSB bus. The state ofthe Global
Access Rights (GAR) bit determines whether the
register can be written to by another iPSB agent. If
this bit is 0, then the register ·is read only on the
iPSB bus and edit routine EDOOH is used. A register will be locally read/writable only if an edit
routine other than EDOOH is supplied for this
entry. If the GAR bit is 1, then this register is
read/writable on both interfaces and an edit routine must be supplied.

values that never change. These values should be
stored in microcontroller ROM. In cases where the
contents of an interconnect register are variable,
either a byte or a bit of RAM must be allocated to
store data, unless the data can be read directly
from a port. The microcontroller's bit manipulatiqn features can be used when a full8-bit register
is not required. The RAM entry in the worksheet
must specify whether to reserve a bit location
(RAM = 2), a byte location (RAM = 1), or no memory
at all (RAM =0). If RAM memory is requested, then
a name for the public variable for that location
must be supplied (refer to paragraph 5.4.9).

5.4.3 Default Value
The Default Value (DFT) is a hex number placed in
this register during a cold or recovery reset. If this
is a static register, then the default value represents the permanent contents of that register. The
default value is also placed into dynamic registers
following a cold reset; however, the register contents may subsequently change due to reprogramming or environmental changes (e.g., reading a value from a port).

5.4.4 Read Routine Entry
Read routines contain the code that actually perform the work in satisfying an interconnect read
request. Eight read routines are used in the interconnect core firmware. These are listed below and all
are user callable. Read routines are sequentially
. numbered from OOH to nnH and contain no numbering gaps. A single read routine may be referenced by several different interconnect registers. If
you are adding a new read routine, the first available Read Routine (RRT) number would be RD08H.
The value supplied for the RRT is the two digit hex
portion of the read routine number.
ROOOh
RDOlh
ROO2h
ROO3h
ROO4h
ROOSh
ROO6h
RD07h

5.4.2 RAM Usage
The micro controller RAM is a precious resource
and must be managed as efficiently as possible.
Some registers in interconnect may contain static

5-74

Load Defaul t Value into ICDATA
Get RAM Access Rights
PSB Control/Status Register
General Status Register
Protection Level Register
MPC General Parameter Register
Local Processor Control· Register
Local Processor Status Register

Generic
Generic
Specific
Specific
Specific
Specific
Specific
Specific

AP-423

;*****************************************************
NAME:

TABGEN

(TABLE GENERATION)

DESCRIPTION:

USES ENTAB MACRO TO ASSOCIATE EACH IC
REGISTER WITH:
GAR - GLOBAL ACCESS RIGHTS
RAM - RAM USEAGE (WHETHER OR
NOT UC RAM I S NEEDED)
OFT
DE FAUL T VALUE
RRT
READ ROUINTE NUMBER
EET
ED IT ENTRY NUMBER
SYMBOL FOR RAM/B IT
VAR
VARIABLE

UPDATE HISTORY: 5-14-87 JR UPDATE FOR lOX

;.**********•• ********** ••• *********.******.*****.****
GR
A A
R M OFT

RRT EET VAR
; - ---- - - -- - - - - HEADER RECORD
%ENTAB(O,O,OOlH,OOOH,OOOH,7)
;VENDOR 10, LOll BYTE
%ENTAB(O,O,OOOH,OOOH,OOOH,1)
;VENDOR 10, HIGH BYTE
%ENTAB(O,O,OOOH,OOOH,OOOH,7)
; BOARD 10, CHARACTER 1
%ENTAB(O,O,OOOH,OOOH,OOOH, 7)
; BOARD 10, CHARACTER 2
%ENTAB(O,O,OOOH,OOOH,OOOH,7)
; BOARD 10, CHARACTER 3
%ENTAB(O, O,OOOH, OOOH, OOOH, 7)
; BOARD 10, CHARACTER 4
%ENTAB(O,O,OOOH,OOOH,OOOH,7)
; BOARD 10, CHARACTER 5
%ENTAB(O,O,OOOH,OOOH,OOOH, ?)
; BOARD 10, CHARACTER 6
%ENTAB(O,O,OOOH,OOOH,OOOH,7)
; BOARD 10, CHARACTER 7
%ENTAB(O,O,OOOH,OOOH,OOOH,7)
; BOARD 10, CHARACTER 8
%ENTAB(O,O,OOOH,OOOH,OOOH,7)
;BOARD ID, CHARACTER 9
; BOARD 10, CHARACTER 10
%ENTAB(O,O,OOOH,OOOH,OOOH,7)
%ENTAB(O, O,OOOH, OOOH,OOOH,?)
; 1NTEL RESERVED
%ENTAB(O,O,OOOH,OOOH,OOOH,7)
; 1NTEL RESERVED
%ENTAB(O,O,OOOH,OOOH,OOOH, ?)
; I NTEL RESERVED
%ENTAB(O,O,OOOH ,OOOH,OOOH, 7)
; 1NTEL RESERVED
%ENTAB(O,O,OOlH,OOOH,OOOH,7)
;HARDWARE TEST REV NO_
%ENTAB(O,O,OOOH,OOOH,OOOH, ?)
;CLASS 10
%ENTAB(O,O,OOOH,OOOH,OOOH,7)
;RFU
%ENTAB(O,O,OOOH, OOOH,OOOH,?)
;RFU
%ENTAB(O,O,OOOH, OOOH,OOOH, 7)
;RFU
GROFT RRT EET VAR
%ENTAB(O,l,003H,OOlH,OOOH,RST_STS) ;RESET STATUS RGTR
%ENTAB(l,l,OOOH,OOlH,OOlH,PTI)
;PROGRAM TABLE INDEX
%ENTAB(l,l,OOOH,OOlH,002H,NMI_EN)
;NMI ENABLE RGTR
%ENTAB(O,l,OOOH,003H,OOOH,GEN_STS)
;GENERAL STATUS
%ENTAB(l,l,OOOH,OOlH,003H,GEN_CTL)
; GENERAL CONTROL
%ENTAB(O, l,OOOH, 001H,004H, BIST_SL) ;BI ST-SUPPORT-LEVEL
%ENTAB(l,l,OOOH,OOlH,OOlH,BIST_DI)
;BIST-DATA-IN

Figure 5-2_

ENTAB Macro Source Code Listing (Sheet 1 of 2)

5-75

AP-423

%ENTAB(O,l,OOOH,OOlH,OOlH,BIST_DO)
;BIST'DATA'OUT
%ENTAB(O, l,010H ,001 H,OOlH,BIST_SS) ;BIST·SLAVE·STATUS
%ENTAB(l,l,020H,OOlH,005H,BIST_MS) ;BIST'MASTER'STATUS
%ENTAB(O,l,OOOH,OOlH,006H,BIST_TID)
;BIST'TEST' 10
; ••••••••••• PROTECTION RECORD •••••••••••••••••••••••
GROFT RRT EET VAR
%ENTAB(O,O,OOBH,OOOH,OOOH,PROT_OFF) ;PROTECT REC TYPE
%ENTAB(O,O,002H,OOOH,OOOH,7)
;RECORD LENGTH
%ENTAB(O,2,OOOH,004H,007H,UACRS)
;PROTECT LEVEL RGTR
%ENTAB(O,O,OOOH,OOOH,OOOH,7)
;RFU
; • • • • • • • • • •• PSB CONTROL RECORD ••••••••••••••••••••••
GROFT RRT EET VAR
%ENTAB(O, 0, 006H ~ OOOH, OOOH, PSB_CTl_OFF)
;PSB CR TYPE
%ENTAB(O,O,006H,OOOH,OOOH,7)
; RECORD LENGTH
%ENTAB(O,O,OOOH,002H,OOOH,7)
;PSB SLOT ID NO.
%ENTAB(l,O,OOOH,002H,OOBH,7)
;PSB ARB 10 NO.
%ENTAB(l,O, OOOH,002H,009H, 7)
; PSB ERROR RGTR
%ENTAB(l,l,OlFH,005H,OOAH,PSB_CS) ;PSB CONT/STAT RGTR
%ENTAB(l,l,OOOH,002H,OOBH,PSB_DIAG)
;PSB DIAG RGTR
%ENTAB(O,O,OOOH,OOOH,OOOH,7)
;RFU
; • • • • • • • • • • •• LOCAL PROC RECORD ••••••••••••••••••••••
GROFT RRT EET VAR
%ENTAB(O,O,013H,OOOH,OOOH,7)
;LOCAL PROC RECORD TYPE
%ENTAB(O,O,003H,OOOH,OOOH,7)
;RECORD LENGTH
%ENTAB(O,O,OOOH,006H,OOCH,7)
;LOCAL PROC CONTROL
%ENTAB (0,0, OOOH, 007H, OOOH, ?)
; LOCAL PROC STATUS
%ENTAB(O,O,OOOH,OOOH,OOOH,7)
;RFU
; ••••••••• END OF TEMPLATE RECORD
GROFT RRT Ep VAR
%ENTAB(O ,0, OFFH, OOOH, OOOH , EaT_OFF)
SEJECT

Figure 5-2.

;EOT RECORD TYPE

ENTAB Macro Source Code Listing (Sheet 2 of 2)

5.4.5 Edit Routing Table

5.4.6 Write Routine Number

The purpose of the Edit Routine Table (ERT)
parameter in the worksheet is to associate each
register with the correct edit routine number.
There are six edit routines supplied within this
firmware:

The Write Routine (WRT) parameter specifies
which write routine number to jump to once access
rights and value checking are complete. A given
edit routine can jump to any write routine (there is
no requirement for the edit routine number to
match th~ write routine number). In the generic
routines, 'several edit routines can reference the
same write routine using different constant lists
based on register number. In the specific routines,
it is sometimes more expedient to jump directly to
the edit routine rather than going through the

eDOOh
EDOlh
ED02h
ED03h
ED04h
ED05h

Used for Read·Only Registers
Check that RFU Bits Match a Mask
Range Checking Between Two ~onstants
PSB ARB ID Register
PSB Diagnostic Register
Greater Than Check (»

Generic
Generic
Generic
Specific
Specific
Generic

5-76

AP-423

write jump table. In this case, a "?" should be
entered for the WRT. Seven write routines are
supplied, therefore, the first available number
assignment for user code is WR07R.
IIROOh
IIR01h
IIR02h
IIR03h
IIR04h
IIR05h
IIR06h

IIrite
IIrite
IIrite
IIrite
IIri te
IIrite
IIrite

to
to
to
to
to
to
to

a RAM Based Register
a MPC Based Register
PSB Control Register
Protection Level Register
PSB Control/Status Register
PSB Oiagnostic Control
Local Processor Control

Generic
Generic

Specific
Specific_
Specific
Specific
Specific

5.4.7 Constants for Value Checking
This column contains a list of constants (CONST)
used by the edit routines in value checking register
contents. During an edit routine, illegal values
cause error reports to the General Status Register
and the IC handler will exit without performing
the write operation. The advantage of using the
CONST is that edit routines can be made "sharable" because a different list of constants is used'
for each register. If no constants are req uired, a"?"
should be entered. This implies that your value
checking algorithm will use constants supplied by
the edit routine (i.e., specific to that register).

5.4.8 The Edit Entry Table
The Edit Entry Table (EET) number is a value
used as the index into the edit entry table during
table look up operations. The order of how EET
numbers get assigned is not important, however,
numbering must start at OR and run in sequence
until every register has an assigned EET number.
Two or more registers having the same attributes
share the same EET number. This is true if (and
only it) all of the columns match for the ERT, WRT,
and CONST values. When this occurs, there is an
opportunity for code compaction and the same
EET number will be assigned to two or more
registers.

5.4.9 Symbolic Reference to RAM
Locations
Whenever a dynamic register is defined (RAM = 1
or 2), an on-chip RAM bit or memory location is
reserved. Entries in the Symbolic Reference to
RAM (VAR) column represent the symbolic name
to be used for references to that RAM bit or
memory location. The VAR entry serves an important purpose - it reserves a location in on-chip

5-77

memory and declares a public symbol under the
name of that variable. Read, write and edit
routines can now reference that variable directly
without needing to know it's exact location.
One word of caution with respect to bit variable
declarations. If the RAM parameter in the worksheet is a byte location (RAM=l), then the value
listed as default will be loaded into the location
reserved for that symbolic name at initialization
time as expected (VAR=DFT). But if a bit location
was reserved (RAM=2), the current software has
no provision to load the reserved bit location with
its default value. Users are therefore advised to
initialize all reserved bit locations explicitly in
their INIT_USER routines. The public variable
specified by the VAR parameter will be in effect
and can be used as a symbolic reference for direct
addressing (e.g., setb/clrb var). An example of the
use of bit variables can be found in the RD04 and
WR03 routines contained in Appendix C.

5.5

LOADING THE MACRO TABLES

The interconnect worksheet was used as an intermediate step to allow the user to identify opportunities for code reduction through the use of generic
read, write, and edit routines. Now that the worksheet is complete, you must enter this data into
table generating macro files on your IBM® PC.
The macro assembler will use these tables to
generate the final interconnect firmware code.

5.5.1 The ENTAB Table
The program file \ICFW\SRC\TABGEN.A51
con tains a list of calls to the ENTAB configuration
macro (figure 5-2). This list determines the register
order in the interconnect template. Enter the
values for GAR, RAM, DFT, RRT, EET, and V AR
from the worksheet into this table.

5.5.2 The EETGEN Table
The program file \ICFW\SRC\EETGEN.A51 contains a list of calls to the EETGEN configuration
macro (figure 5-3). This list is used to build the edit
entry table. Enter the values for ERT, CONST, and
WRT from the worksheet into this table.

AP-423

; *****************************************************
NAME:

EELBL (EDIT ENTRY TABLE)

PURPOSE:

PROVIDE EDIT ROUTINE ADDRESSES,
VALUE CHECKING CONSTANTS, AND WRITE
ROUTINE ADDRESSES FOR THE IC MODULE

DESCRIPTION:

A ONE DIMENSIONAL LOOKUP TABLE THAT
SPECIFIES LOW BYTES OF ADDRESSES
THAT RESULT FROM EXPRESSIONS, i.e.
(ERXX'ERLBL), AND ALSO PROVIDES
CONSTANTS THRU THE USE OF SYMBOLS

UPDATE HISTORY: 5·14·87 JR UPDATED FOR lOX

i*****************************************************
ERT

CONST

WRT

%EEGEN(OOH,%(?), ?)

;READ ONLY REGISTERS

%EEGEN(01 H, %(OOH) ,OOH)

;PROGRAM TABLE INDEX

%EEGEN(01H, %(038H) ,OOH)

;NMI ENABLE

%EEGEN(01 H,%(078H) ,02H)

;GENERAL CONTROL
%EEGEN(05H,%(018H,07H,04H),OOH) ;BIST SUPPORT LVL
%EEGEN(01 H,%(050H), OOH)
;BIST MASTER STATUS
%EEGEN(02H, %(01H,OFEH), OOH) ;BIST TEST ID

0
1
2
3
4

5
6
7

%EEGEN(01H,%(OFEH),03H)

; PROTECT I ON LEVEL

%EEGEN(03H,%(?), ?)

;PSB ARB. 10

%EEGEN(01H ,%(OFFH), 01H)

;PSB ERROR

%EEGEN(01 H,%(063H) ,04H)

;PSB CONTROL STATUS

%EEGEN(04H,%(?), ?)

;PSB DIAGNOSTIC

%EEGEN(01 H,%(OFEH) ,06H)

; LOCAL PROC CONTROL

$EJECT

Figure,5-3.

EEGEN Macro Source Code Listing

5.5.3 The EXTERNS Macro: Generating
External Labels

%EXTERNS(06,07,08)

;Six edit routines
;Seven write routines
;Eight read routines

After completing the entries in the ENTAB and
EETGEN tables, the final step before code genera·
tion is to supply values to the EXTERNS macro so
that the correct number of external labels are
generated for your user routines. The EXTERNS
macro is used in the file \ICFW\SRC\TABLE.MOD.
Here you will find the call to EXTGEN, where you
must supply the highest number of your edit, write,
and read routines as parameters in that order:

5.6

PROGRAMMING TECHINQUES
FOR READ, WRITE, AND EDIT
ROUTINES

There are a group of user callable macro functions
supplied with the interconnect firmware in the file
\ICFW\SRC\GLOBAL.MAC. These are called by
entering a H%" symbol in front of the name and
supplying a list of parameters. This results in code

5-78

AP-423

expansion, which supplies the requested function.
The following macros are callable by users.
RD_MPC (de.t,.rc)
IIRT_MPC(de.t,src)
LOOKUP(table,off.et)
SUB (opr)
MOVBIT(dest_bit,src_bit)
GET_EEC

Read MPC Register
IIrite MPC Register
Retrieve parameter from
table
Subtract operand from
accumulator
Perform bit move
operation
Get Edi t Table Constant
(Data pointer must be
pointing to EETABLE.
Byte is returned in
Accumulator. You must
perform one LOOKUP be·
fore making this call.)

All user routines should be declared PUBLIC so
that the table generating macros can locate the
routines entry point. Place the user'routines you
write in the file ICFW\SRC\USER.MOD.

5.6.1 Retrieving the Constant List from the
EETABLE
While in a read, write, or edit routine, one or more
constants can be retrieved by using the global
symbol EET _ OFF as the offset into the
EETABLE for this register. For example, consider
this range checking algorithm in an edit routine:
ER05H: INC

EET_OFF

;Point to RFU Mask
; in EETABLE
%LOOKUP(#EETABLE,EET_OFF) ;Get It
A,ICDATA
ANL
; Check all RFUs=O
JNZ
ERR_5
;JMP if Illegal
%GET_EEC
; Get Don't Care Mask
; From EETABLE
ANL
A,ICDATA
;Mask off Don't Care
;Bits from ICDATA
MOV
TEMP,A
;Save Resul t
%GET_EEC
;Get Max Allowable
;lIri te Value
%SUB(TEMP)
;SUB Value Being
;lIritten
JC
ERR_5
; If ICDATA > Max
;Allowable, ERR
%GET_EEC
;Else Get IIrite
;Routine Offset
MOV DPTR,#IIRLBL
;Point to IIR
JMP
iilA+DPTR
;GOTO IIR
;Report Value ERR
ERR_5: AJMP VALERR

5-79

5.6.2 Handling of Value Errors
If a value error is detected in an edit routine, then
the write operation will not be performed and
instead, a jump to a public routine VALERR
should be executed. This routine updates the
General Status Register with the appropriate
Value Error and returns to the IC handler to complete the interconnect operation.

5.7

HOOKS FOR USER SUPPLIED
ROUTINES
Every board design is just a little bit different and
recognizing this fact, calls to user supplied
routines are provided at certain critical locations
in the code. These include initialization, polling,
and reset routines and timer based functions. As
delivered, these routines are nothing more than
program stubs. You can find them in the
\ICFW\SRC\USER.MOD file. The following discussion suggests some ideas for what you might do
with the user routine calls in your interconnect
design.
5.7.1INIT USER: Custom Initialization
Code
The INIT USER routine is only called on a cold
reset. It gives the user an opportunity to initialize
their I/O and modify defaults before entering the
mainline code. This routine also gives the user a
chance to modify the MPC register defaults after
the call to MPC_INIT. If you are using any bit
segments (RAM=2), they must be explicitly initialized at this time. A special feature has been added
to the INIT USER routine which disables the
RSTNC time-;;-utfunction based on a jumper input.
This helps out ICE'· users since these emulators
have difficulty dealing with external resets.

5.7.2 RST USER: Special Handling upon
Warm Reset
When RST_USER is called, you should reset any
I/O devices connected to the micro controller. If
dual-port memory is present, rewrite the upper and
lower address boundries to the MPC because the
internal MPC registers are all cleared after an
iPSB reset. In most cases, the contents of interconnect registers will remain unchanged.

5.7.3 POLL USER: Polled User Functions
The POLL USER routine is called from the mainline code. It polls user functions on each loop
through the mainline code (approximatly 39I1s).

AP-423

Typical uses are to scan for on-board errors and to
set the general error status bit in the General Status Register when errors are found.

5.7.4 USER TIMER: Timer Based Functions
The USER_TIMER routine is called every
1-ms as part of timer 0 interrupt routine.
USER_TIMER is similar to the POLL_USER,
except that the granularity of the timer
is predictable since the timer 0 interrupt has
the highest priority (other than reset). The
USER_TIMER routine is used for self-toggling
resets and other time based functions. A software
prescale counter can be maintained for timing
longer intervals.

5.8

core and user routines and where symbolic variables are located. Examine the link map to check
that the limits on RAM and ROM usage have not
been exceeded. A gap will be reported whenever
additional free space is available. The core firmware will create the following segments:
LINK MAP FOR TEST _LNKCMAIN)

LNKUSR file name
You will now find a PROMmable file with a .LNK
extension in the \ICFW\SRC\OBJ subdirectory.
There will also be a file in this subdirectory with a
.MAP extension. This file (a link map) will be used
in the next step to verify microcontroller resources.

5.8.1 Checking Microcontroller Resource
.
Utilization
The link map file contains information about how
much code and register space was requested by the

LENGTH

REG

OOOOH

0008H

RELOCATION

SEGMENT NAME
"REG BANK 0"

DATA

0OO8H

OOODH

UNIT

RW_SEG

DATA

001SH

0008H

UNIT

DATA_SEG

BIT_ADDR

BIT_ADDR_BYTE_SEG

*** GAP ***

001DH

0003H

DATA

0020H

0OO2H

BIT

0022H

OOOOH • 2 UN IT

BIT_SEG

***

0022H_2 OOOOH.6

The final step in code preparation is to assemble
all of your new user routines with ASM-51 and
then link to the core module using the RL51 linker.
Two batch files are supplied to automate the firmware generation process. To use these files, the
current directory must be the \ICFW\SRC subdirectory. Here you will find three files with a .MOD
file extension. These are the default module, the
tables, and your user code. To assemble these
modules enter:

The list files will be placed in the \ICFW\SRC\LST
subdirectory and the object files are placed in the
\ICFW\SRC\OBJ subdirectory. Next, the object
modules will be linked with the core library to produce a PROM image. Select a name for the output
file (e.g. TEST), and invoke the linker by entering:

BASE

----_ .... _----

GENERATING THE OBJECT
MODULE

ASMMOD dft
ASMMOD table
ASMMOD user

TYPE

GAP ***
STACK_SEG

IDATA 0023H

0OO8H

UNIT

CODE
CODE

OOOOH
004EH

004EH
0433H

ABSOLUTE
UNIT

CODE_SEG

CODE

0481H

OOBFH

UNIT

EDIT_SEG

CODE

OS40H

0067H

UNIT

WRITE_SEG

CODE

OSA7H

OOSAH

UNIT

READ_SEG

CODE

0601H

OOOAH

UNIT

USER_CSEG

060BH

09F3H
0OO2H

ABSOLUTE

CODE

OFFEH

***

GAP

***

5.8.2 Checking Critical Timing Paths
Figure 5-4 shows a state diagram of the microcontroller core firmware and includes the instruction
cycle counts for each of the major functions. In this
step, you will evaluate the impact user code has on
interconnect subsystem timing. All timing calculations are based on counting micro con troller
machine cycles to compensate for the different
crystal frequencies that may be used. To calculate
the elapsed time, multiply the cycle count by l/xtal
frequency (i.e., 0.909 p's at ll-MHz). Some microprocessors have specific timing requirements for the
pulse width of reset and and interrupt signals.
These should be checked against the timing values
given below:
Reset Timing:
Max. RES Latency from UCINT = 41 Cycles
Min. RES Inactive afterUCINT Inactive = 38
Cycles + RST _USER
NMITiming:
Max. Interrupt Latency = Mainline + IC
Handler= 39 + 136 Cycles

5-80

AP-423

EA CLEARED AT START
OF MAINLINE, SET AT END

*ADD CYCLES FOR USER SUPPLIED ROUTINES

Figure 5-4.

Microcontroller Cycle Count of Major Firmware Functions

Min. Interrupt Latency =Mainline =
39 Cycles

Max. Timer 0 Latency = IC Handler +
Mainline = 136 + 49 Cycles

The timer 0 interrupt occurs every 1 ms when using
the recommended ll-MHz crystal oscillator.
However, the timer 0 interrrupt is masked in both
the IC handler and the mainline code. Therefore,
the worst case timer 0 latency is calculated:

5-81

An iPSB timeout will occur if an incoming interconnect request is not completed with in 1 ms after
SCO* becomes active. Consider the case where a
local interconnect request is received just a
moment before the iPSB request. The microcon-

AP-423

troller might be in a timer 0 interrupt routine and would have to pass again through mainline code
before servicing the local request. Thus; the worst
case iPSB response can- be calculated:

STEP 1. Invoke iPPS.
STEP 2. Initalize default base to hex and the
file format to 80.
180

Worst Case iPSB Response = Mainline +
Timer 0 + mainline + Local IC Access +
mainline + PSB Access

STEP 3. Set PROM type to 8751.
T8751

For the core firmware without user code, the worst
case local firmware response is approximately 485
/JS at II-MHz. This leaves a total of 515 /JS for the
iPSB interconnect cycle to complete (including
MPC and write data delays) before a timeout
occurs.

STEP 4. Load data buffer with OFFH.
LBWOFFH
STEP 5. Copy object file to buffer. iPPS will
display a check sum.
C T B

5.8.3 Programming the 8751

STEP 6. Copy check sum displayed by iPPS
into address OFFEH. The low byte of
the 16-bit check sum loads to address
OFFEH and the high byte to address
OFFFH.
SOFFEH
OFFE:(low byte) (high byte)

One of the three initialization self-checks that the
microcontroller performs following a reset is the
PROM check sum test. The firmware, computes a
16-bit sum of all code bytes from 0 through (top of
the PROM memory -2). The actual check sum is the
two's complement of the sum. This value is programmed into the last two bytes of PROM space
and given the label CHECKSUM. The check sum
label is assigned in the default program file
\ICFW\SRC\DFT.MOD and is originally set to
address OFFEH. The address of this label can be
modified to accomodate other microcontrollers
with larger EPROM size (e.g. an 8752 Microcontroller), as long as the check sum always occupies
the last two bytes of code space.
The check sum is initially assembled with a data
value of OOOOH. After assembling and linking the
interconnect firmware, the actual check sum value
will be programmed into the PROM in a separate
step. The following procedure assumes that an
Intel iUP 201 PROM Programmer and iPPS software used. If you are using another brand pf
PROM programmer, you must guarantee that
their check sum algorithm matches the method
used here.

STEP 7. Save a copy of the complete object
file on your hard disk
C B T
STEP 8. Install a blank 8751 in the programmer and copy the buffer to
PROM.
CBTP
At this point you will have a programmed microcontroller, which is ready to install on the prototype board for functional testing. As an alternative, you can load the file created in step 7 above
into an ICE 51 In-Cicuit Emulator and test the
firmware directly without programming the 8751.
This method gives you access to internal variables
and tables in addition to hardware control of the
microcontroller.

5-B2

AP-423

CHAPTER 6
FUNCTIONAL TESTING OF THE
INTERCONNECT SUBSYSTEMS

6.1

TESTING THE INTERCONNECT
SUBSYSTEM

(unless disabled using the ICE'· compatibility
jumper).

Assuming you were successful in Chapters 4 and 5,
you now have a functional prototype of your interconnect subsystem ready for testing. Proper interconnect operation depends on complex interrelationships between the 8751 Microcontroller,
CPU, Message Passing Coprocessor (MPC), and
various TTL circuits. Since interconnect forms the
basis of higher level diagnostic services, we must
have complete confidence that the interconnect
subsystem is functioning properly before implementing the design. Evaluation of the interconnect subsystem is facilitated through the use of an
interconnect utility program and a systematic
approach to design testing.

6.2

POWER-ON AND INITIALIZATION
FUNCTIONS

When a prototype board is inserted into the backplane for the first time, there is a distinct possibility that a design error in the reset initialization
sequence could cause a bus error or Reset-NotComplete (RSTNC) condition. Either of these conditions prevents other boards from coming on-line.
Fortunately, these events can usually be detected
by watching the front panel LEDs cycle through
the power-on sequence.
Under normal reset conditions, the majority of
MULTIBUS® II boards first illuminate their
yellow BIST LED, progress on to illuminate the
green LED (run indicator) and leave no other
LEDs lit. If the Central Services Module (CSM) has
a BUSERR indicator, it will be lit to indicate a bus
error due to RSTNC condition. If the bus error
persists for more than a few seconds, then a strong
likelihood exists that your board has failed to clear
the RSTNC* bit. This is confirmed if, after 30
seconds, the CSM BUSERR condition disappears
due to the microcontroller clamping reset active
and forcing a reset complete indication to the iPSB

5-83

6.3

THE INTERCONNECT
CONFIGURATION UTILITY

In the \ICFW\ICU subdirectory is an interconnect utility (IC.P28) written in PL/M source code to
run on the iRMX'· 86/286 Operating Systems. The
executable object file .for this utility may be
obtained from the iRMX Users Group (iRUG), 5200
N.E. Elam Young Parkway, Hillsboro, OR 971249987. If you are not working in one of these programming environments, you will need to
adapt this code to your own environment by substituting the appropriate I/O and interconnect
system calls.
Before invoking the IC utility on your prototype, you must create the subdirectory
IUSER/BOARDS and enter into that directory
a file for the board. The file name you assign
must correspond with the ASCII description
contained in the 10 character board ID field
of the Interconnect Header Record. Slashes (I)
present in the description must be converted to
ASCII periods. For example, iSBC3861100 is converted to iSBC386.100. The actual values for each
interconnect register are entered into the template
plus any user comments you may wish to add for
that board. A typical configuration file listing is
shown in figure 6-1. The control characters that
appear in the file listing are used by the utility to
mark the display area and field boundaries.
•

The @ symbol is the screen delimiter. As the
user pages through the file and encounters this
s)'mbol, the utility will prompt the user for
input.

•

The; symbol is the register field delimiter. The
utility scans for an opening semicolon; then
fetches a register value for each character

AP-423

Reg
00
02
DC
10
11
12
16
17
18
19
1A
1B
1C
1D
1E
1F
iil
Reg
20
21
22
23
iil
Reg
24
25
26
27
28
29
2A
iil
Reg
2B
2C
2D
2E
2F
30
31
32
iil

Figure 6-1.

Value RW
;h h ; ro
i aaaaasaaa8i ro
;d d d d ; ro
:d; ro
i b ; ro
;b b b b ; ro
;b; rw
:b; rw
;b; ro
;b; rw
:b; rw
;b; rw
;b; rw
:b ; rw
:bi rw
:b; rw

F,unction
Vendor 10 Number
Board ID Number
PBA Number. Rev
Hardware Test Rev #
Class ID
Reserved
Program Table lildex
NMI Enable Register
Genera I Status
General Control
81ST Support Level
BIST Data In
BIST Data Out
BIST Slave Status
BIST Master Status
BIST Test ID

Conments

Protection Record
Protect i on Record Type
Record Length
Protect i on Level Reg
Reserved

Value

RW
ro
:b; ro
;b ; rw
:b; ro

Conments

Memory
Memory
Record
Memory
Memory
Memory
Memory
MM2 10

Value RW
i b ; ro
:b; ro
:b; ro
:b; ro
;b; rw
i b ; ro
:b; ro

Cornnents

Record Type
Record Type
Length
Size (bits 7 •• 0)
Size (bits 15 •• 8)
Cont ro I
Status

:b:

i PSB Cont ro I Record
Value
;b;
iPSB Control Record Type
Record Length
:b;
iPSB Slot ID Number
:b ;
iPSB Arbi trati on ID Number
:b;
iPSB Error Register
ib ;
iPSB Control/Status Register :b;
iPSB Diagnostic Register
;b;
Reserved
ib ;

RW
ro
ro
ro
rw
rw
rw
rw
ro

Comments

Configuration File Format for the IC Utility (Sheet 1 of 3)

5·84

AP-423

Reg
33
34
35
36
37
38
39
01
Reg
3A
3a
3C
3D
3E
3F
40
01
Reg
41
42
43
44
45
46
4A
01
Reg
4B
4C
40
4E
4F
50
51
01

Figure 6-1.

iPSa Memory Record Type
Value RW
iPSa Memory Record Type
:b ; ro
Record Length
:b i ro
iPSB Start Address (23 •• 16)
jb ; rw
iPSa Start Address (31 •• 24)
;b ; rw
iPSB End Address (23 •• 16)
;b; rw
i PSB End Address (31 •. 24)
;b; rw
ipsa Memory Control
:b; rw

COITJDents

Loca l Memory Record Type
Value
Loca l r~emory Record Type
;b:
Record Length
:b;
Local Start Address (23 •• 16) :b;
Local Start Address (31 •• 24) :b;
jb;
Local End Address (23 •• 16)
Local End Address (31. .24)
;b;
Local Control Register
;b ;

RW
ro
ro
ro
ro
rw
ro
rw

Comments

Memory Pari ty Record Type
Value
Memory Pari ty Record Type
:b ;
Record Length
;b ;
Parity Control Register
:b ;
Pari ty Status Reg i ster
;b ;
Bank Status Register
:b ;
Error Offset
;b b b b ;
Reserved
:b;

RW
ro
ro
rw
ro
ro
ro
ro

Comments

Cache Memory Record
Cache Memory Record Type
Record Length
Cache Size (bits 7 •• 0)
Cache si ze (bi ts 15 •• 8)
Cache Entry Si ze
Cache Cont ro l
Reserved

Value RW
;b; ro
;b ; ro
:b i ro
:bi ro
jb; ro
;b; rw
;b ; ro

Comments

Configuration File Format for the IC Utility (Sheet 2 of 3)

5·85

AP-423

Reg
52
53
54
55
56
57
58
59
SA
5B
5C
50
5E
SF
60
61
62
63

Firmware Conm Record Type
Firmware Conm Record Type
Record Length
Conmunications Byte 1
Conmunications Byte 2
Conmunications Byte 3
Conmunications Byte 4
Conmunications Byte 5
conmunications Byte 6
Comnunications Byte 7
Comnunications Byte 8
Comnun i cat ions Byte 9
Conmunications Byte 10
Conmunications Byte 11
Conmunications Byte 12
Comnunications Byte 13
Conmunications Byte 14
Conmunications Byte 15
Conmunications Byte 16

Value RII
ib; ro
:b; ro
jb; rw
jb; rw
jb ; rw
;b; rw
;b; rw
:b; rw
;b; rw
jb; rw
:b; rw
;b; rw
:b; rw
jb; rw
;b; rw
;b; rw
;b ; rw
:b; rw

Comnents

Host 10 Record Type
Host 10 Record Type
Record Length
Host 10 (bits 7 •• 0)
Host 10 (bits 15 .. 8)
Message Address
Reserved

Value

Corrments

Serial Cornn Record Type
Serial Conm Record Type
Record Length
Serial Data In
Serial Data Out
Serial Port Status
Serial Interrupt Enable
Serial Port Options
Reserved

Value

386/100 Specific Record
386/100 Spec Record Type
Record Length
On-board Control Register

Value

End Of Template Record
EaT Record Type

Value

iil

Reg
64
65
66
67

68
69

RII

;b; ro
;b; ro
i b ; rw
ib; rw

:b; rw
:b; ro

iil

Reg
6A
6B
6C
60
6E
6F
70
71

RII

Cornnents

jb; ro
i b ; ro
;b; ro
;b; rw
jb; ro
:b; rw
:b; rw
i b ; ro

iil

Reg
72
73
74

RII

Corrments

;b; ro
;b ; ro
jb; rw

iil

Reg
75
iii

Figure 6-1.

RII

Cornnents

i b ; ro

Configuration File Format for the IC Utility (Sheet 3 of 3)

5-86

AP-423

found until encountering the closing semicolon. Legal character type descriptors are:
b (binary)
d (decimal)
h (hexadecimal)
a (ASCII)

Can the registers be accessed from offboard as well as on-board?

The IC utility enables you to identify, examine,
and modify the configuration of a system board
from the comfort of your console (no jumpers to
move!). The utility locates the board ID character
fields in the Interconnect Header Record of the
board in the cardslot you select to configure. It
then searches the subdirectory IUSERIBOARDS
for the file having a file name that matches the
board ID. Specific interconnect registers may be
modified (provided access rights and value
checking are valid), however, an attempt to enter
illegal values into an interconnect register are
ignored and the existing register content is unaffected. Entries are displayed as they are made.
Once invoked, the IC utility prompts the user for
input and you will find it very easy to use. A sample screen output from this utility is shown in figure 6-2.

6.4

A TEST METHODOLOGY FOR
INTERCONNECT FUNCTIONS

Given a functional prototype board and an interconnect utility such as the one described above, we
now use these tools to verify correct operation of
the interconnect subsystem. One might assume
that this process would be quite simple and
straight forward - and usually, it is. But we are
now looking for more subtle conditions such as
timing related problems and secondary affects on
interconnect register content. While every board is
different, a test methodology that looks for all possible contingencies is an important step in design
verification. The following checklist is an example
of what to look for during evaluation testing of
interconnect using a prototype board:
Loo~

Look for dual-port operation on both local and
system buses:

for initialization conditions:
Do the correct default register values
appear after cold-start?
Do the front panel LEDs work properly?
Is RSTNC handled correctly? (also test
RSTNC recovery by disabling the CPU).

5-87

Do the function records all have correct
record type values and byte counts?
Are the read/write privileges working for
both on-board and off-board references?
Is the protection record function working
properly?
Look for proper register content and
function:
Do all the bit level functions in control
registers work as expected?
Are all the status registers reporting
correctly?
Look for secondary effects:
Changes to memory addressing registers
are only allowed when memory is
disabled.
Look for iPSB timeout conditions:
Saturate the local bus with interconnect
110 commands in a tight loop; then attempt an interconnect operation from
off-board.
Once you have accomplished this type of testing
methodology for each register on the prototype
board, you can have reasonable confidence that all
is well with the interconnect subsystem. Now you
can proceed forward with the development of
device drivers and extended diagnostics. If any
changes are made to the micro controller after its
initial release, be sure to update the revision
control field in the header record so users can
identify which version of the firmware they hold.

AP-423

INTERCONNECT CONFIGURATION UTILITY
Conmencing Board Search Routine:
Board Search Complete.

The following boards were found:
PBA #

Class

Intel Corporation CSM/001

147304·0003

Central Services Module

Intel Corporat i on

186/410

000000·0002

16·bit Conmunications Board

02*

Intel corporation 386/100

000000·0002

32·bit Processor Board

Intel Corporat i on MEM/310

Intel corporation

286/100A

000000 - 000 1 Memory Board
000000-0001 16-bit Processor Board

Intel Corporat i on

186/224A

000000-0001

Slot# Vendor 10

Board 10

06
07

16-bit Peripheral Controller

08
Options: , or Type First Letter):c2
Configuration File Attached.- Fi le: /user/boards/386.100
Reg

Function

Vendor 10 NlIIlber

Value

RII

Board 10 Number

386/100; ro

PBA Number, Rev

00000000; ro

Hardware Test Rev #

Class ID

F1 ; ro

Reserved

00000080; ro

16
, 17

Conments

0100; ro

02; ro

Program Table Index

00; rw

NMI Enable Regi ster

04; rw

General Status

80; ro

General Control

00; rw

BIST Support Level

00; rw

81ST Data In

00; rw

BI ST Data Out

00; rw

BIST Slave .Status

10; rw

BIST Master Status

30; rw

81ST Test 10

10; rw

lIould you l ike to make any changes?

Figure 6-2.

Interconnect Utility Screens (Sheet 1 of 2)

5-88

Ap·423

Reg

Protection Record

Protection Record Type

OB; ro
02; ro

Value

Record Length

Protection Level Reg

00; rw

Reserved

00; ro

Reg

Memory Record Type

Record Length

05; ro

Memory Size (bits 7 •• 0)

3F; ro

Memory Size (bits 15 •• 8)

00; ro

Memory Control

01; rw

Memory Status

A1; ro

MM2 10

22; ro

Value

COlIIIIents

Conments

01; ro

Would you like to make any changes?

Reg

iPSB Control Record

iPSB Control Record Type

06; ro
06; ro

Value

Record Length

iPSB Slot 10 Number

10; ro

iPSB Arbitration 10 Number

E8; rw
88; rw

iPSB Error Register

iPSB Control/Status Register

18; rw

iPSB Diagnostic Register

00; rw

Reserved

00; ro

Conments

Would you like to make any changes?

Figure 6·2.

6.5

Interconnect Utility Screens (Sheet 2 of 2)

SUMMARY AND CONCLUSION

MULTIBUS II is a system architecture composed
of standardized hardware and software modules.
Having successfully implemented the interconnect
subsystem on your board, you are ensured of the
functional compatibility and interoperability of
that board with other industry·standard MULTI·
BUS II products that use interconnect.

5·89

If you found this guide useful, you may also be
interested in other design guides available from
Intel. A list of documents available at the time of
this guide's publication are listed in Appendix A.
As the MULTIBUS II system architecture ma·
tures and proliferates, we look forward to supply·
ing additional design guides that encourage the
production of compatible hardware and software
products.

AP-423

APPENDIX A
BIBLIOGRAPHY OF RELATED READING

Interconnect Architectural Specification - Intel Order Number 149299-002.
MPC User's Guide - Intel Order Number 176526-001.
IEEE 1296 Specification (High Performance Synchronous 32-bit Bus Standard)
iSBCT. 386/116 Hardware Reference Manual- Intel Order Number 451833-001.
BUSCON Paper: An Architecture for Initializing Multibus® II Multiprocessor Systems.
Stephen Rogers, ,october 1987.
Computer Technology Review Quarterly: Interconnect Simplifies System Configuration.
Roger Finger, September 1987.
Intel Application Note AP-70, Using the Intel MCS® 51 Boolean Processing Capabilities.
John Wharton, 1980.
Embedded Controller Handbook 8751 Data Sheet - Intel Order Number 210918-005.
iUP 200/201A Programmer User's Guide - Intel Order Number 166608-001.
MCSTM Macro Assembler User's Guide for DOS Systems - Intel Order Number 122752-001.
MCSTM 51 Utilities User's Guide for DOS Systems - Intel Order Number 122747-001.
Intel Application Note AP-422, Designing a Central Services Module for MULTIBUS®II.
Jory Radke, 1987.

5-90

AP-423

APPENDIX B
FLOWCHARTS FOR IC CORE FIRMWARE

B.1.

Cold Reset Routine

5·91

AP-423

B.2.

Reset Interrupt Routine

5·92

AP-423

B.3.

Mainline Program Flow

5-93

AP-423

B.4. Timer 0 Interrupt Routine

5-94

AP-423

B.S. Ie Handler Interrupt Routine

5-95

Ap·423

APPENDIX C
READ, WRITE, AND EDIT ROUTINES

; *****************************************************
NAME:
PURPOSE:

CORRELATE IC REGISTER NUMBER TO MPC
REGISTER NUMBER

DESCRIPTION:

CORRELATES IC PSB CIS REGISTERS WITH
THE PROPER MPC REGISTER NUMBER,
STARTING WITH THE PSB SLOT 10
REGISTER.

UPDATE HISTORY:

i*****************************************************
IC_TO_MPC:

SID

;PSB SLOT 10

AID

;PSB ARB 10

RERR

;PSB ERROR

DOH

; DUMMY

DIAG

;PSB DIAGNOSTIC

SEJECT

C.1.

IC.TO.MPC Correlation

5·96

AP-423

; ***********************************"'.****************
NAME:

RDOOH

PURPOSE:

READ DEFAULT VALUE FROM DFTABLE

CALLED BY:

JUMPED TO FROM SERVICE

CALLS:

NONE

NEST LEVEL:

DESCRIPTION:

USES REGNUM TO INDEX INTO DFTABLE.

REG BANK:

ASSUMES I C_BANK, SELECTS NONE

INPUTS:

REGNUM

DESTROYS:

ACC, DPTR

RETURNS:

ICDATA

UPDATE HISTORY:

;**********************************.******************
RDOOH:

XLODKUP(#OFTABLE,REGNUM) ;GET DEFAULT FM TABLE
MOV

ICDATA,A

RET

;RET DEFAULT IN ICDATA
;RETURN TO IC HANDLER

SEJECT

C.2.

RDOOH Read DFTABLE

5-97

AP-423

,.***************************************************.*
NAME:

RD01H

PURPOSE:

READ RWTABLE VALUE

CALLED BY:

JUMPED TO FROM SERVICE

CALLS:

NONE

NEST LEVEL:

DESCRIPTION:

USES REGNUM TO INDEX INTO RATABLE.'
USES RWTABLE INDEX PORTION OF RA BYTE
TO INDEX INTO RWTABLE TO GET REGISTER
VALUE.

REG BANK:

ASSUMES IC_BANK, SELECTS NONE

INPUTS:

REGNUM

DESTROYS:

ACC, ADDR, DPTR

RETURNS:

ICDATA

UPDATE HISTORY:

;***.********.***************** ••***.*****************
RD01H:

XLOOKUP(#RATABLE,REGNUM) ;GET RAM/ACCESS BYTE
CLR
ACC.GAR ;MASK OFF GLOBAL ACCESS RIGHTS
ADD
A,#RWTABLE ;ADD TBL ADDR TO RAM OFFSET
MOV
ADDR,A
;SAVE RAM ADDR
HOV
A,QADDR
; READ 'RAM VALUE
HOV
ICDATA,A
;RETURN VALUE IN ICDATA
RET
;RETURN TO IC HANDLER

SEJECT

C.3. RD01H Read RWTABLE

5-98

AP-423

; ******************••• ***************************.****
NAME:

RD02H

PURPOSE:

READ MPC REGISTER FOR PSB
CONTROL/STATUS REGISTER

CALLED BY:

JUMPED TO FROM SERVICE

CALLS:

NONE

NEST LEVEL:

DESCRIPTION:

USES LOOKUP TABLE IC_TO_MPC TO XREF
IC ADDRESS TO MPC REGISTER NUMBER,
READS MPC REG AND RETURNS DATA IN
ICDATA.

REG BANK:

ASSUMES IC_BANK, SELECTS NONE

INPUTS:

NONE

DESTROYS:

ACC, DPTR, MPC_RNUM

RETURNS:

ICDATA

UPDATE HISTORY:

; .****************************************************
RD02H:

MOV

A,REGNUM

SUBB

A,#PSB_CTL_OFF+5

;GET REG NO. BEING ACCESSED
i IC_TO_MPC STARTS
;WITH SLOT 10 REG

%LOOKUP(#IC_TO_MPC,A)
%RD_MPC(ICOATA,A)
RET

;GET CORRES MPC REG NO.
iREAD MPC REG
i RETURN TO I CHANDLER

SEJECT

C.4.

RD02H Read MPC Register

5·99

AP-423

; *****************************************************
NAME:

RD03H

PURPOSE:

READ ROUTINE FOR GENERAL STATUS
REGISTER

CALLED BY:

JUMPED TO

CALLS:

NONE

NEST LEVEL:

DESCR I PTI ON:

USES LOOKUP TABLE IC_TO_MPC TO KREF
IC ADDRESS TO MPC REGISTER NUMBER,
READS MPC REG AND RETURNS DATA IN
ICDATA.

REG BANK:

ASSUMES IC_BANK, SELECTS NONE

INPUTS:

NONE

DESTROYS:

ACC, DPTR, MPC_RNUM

RETURNS:

ICDATA

F~OM

SERVICE

UPDATE HISTORY:

;*****************************************iI.**********
RD03H:

MOV
ICDATA,GEN_STS
:READ RAM
%MOVBIT(ICDATA.PFI,DCLO) :GET PWR FAIL STATUS
RET
: RETURN TO I CHANDLER

SEJECT

c.s.

RD03H Read General Status Register

5·100

AP-423

; ***************.*******.*********.*.*.***************
RD04H

NAME:
PURPOSE:

READ ROUTINE FOR PROTECTION LEVEL
REGISTER

CALLED BY:

JUMPED TO FROM SERVI CE

CALLS:

NONE

NEST LEVEL:

DESCRIPTION:

READS THE BIT UACRS AND PUTS IT IN
ICDATA

REG BANK:

ASSUMES IC_BANK, SELECTS NONE

INPUTS:

NONE

DESTROYS:

CARRY FLAG

RETURNS:

ICDATA

UPDATE HISTORY:

i*********************·*******************************
RD04H:

MOV

ICDATA,#CLEAR

;ICDATA

%MOVBI T(I CDATA .ACRS, UACRS)

;GET BIT

; RETURN TO I CHANDLER

RET
SEJECT

c.s.

RD04H Read Protection Level Register

5-101

Ap·423

,-••••••• _...........**••• _-_••••_••-•••

_._.**.__._.__.

NAME:

RDDSH

PURPOSE:

READ ROUTINE FOR PSB CONTROL/STATUS
REGISTER

CALLED BY:

JUMPED TO FROM SERVICE

CALLS:

NONE

NEST LEVEL:

DESCRIPTION:

COMBINES VALUES OF MPC GENERAL
PARAMETER REGISTER WITH VALUE
FROM RWTABLE FOR PSB_CS TO GET
COMPLETE REGISTER VALUE.

REG BANK:

ASSUMES IC_BANK, SELECTS NONE

INPUTS:

NONE

DESTROYS:

ACC, MPC_RNUM, CARRY FLAG

RETURNS:

ICDATA

UPDATE HISTORY:

,.it ••••••••••••••_ • • • • •_._••• _. __. . . . . . . ._._ ••••_ • •_ ••• _
RDDSH:

%RD_MPC(A,IIGEN]AR)
iREAD MPC GENL PARAM REG
MOV
I CDATA,PSB_CS
iREAD RAM
%/oIOVBIT(lCDATA.HPRO,ACC.PRY) iNOV MPC BITS TO
i ICDATA
%/oIOVBIT(ICDATA.RSTNC,ACC.RSTNCIN)
RET
iRETURN TO IC_HANDLER

SEJECT

C.7. ROOSH Read Control/Status Register

5·102

AP-423

; *******.**************.**.***************************
NAME:

RD06H

PURPOSE:

READ ROUTINE FOR LOCAL PROC CONTROL
REGISTER

CALLED BY:

JUMPED TO FROM SERVICE

CALLS:

NONE

NEST LEVEL:

DESCRIPTION:

IF PROC RESET AND RESET STATUS =
PRST, THEN SETS PRST = TRUE, ELSE
PRST = FALSE.

REG BANK:

ASSUMES IC_BANK, SELECTS NONE

INPUTS:

NONE

DESTROYS:

CARRY FLAG

RETURNS:

ICDATA

UPDATE HISTORY:

5·14·87 JR UPDATED FOR lOX

;

; *.**.*************** ••***.******.******.*******.*.***
RD06H:

MOV
JNB
MOV
CJNE

SETB
END_R6: RET

ICDATA,#CLEAR
;ICDATA = 0
RES,END_R6 ; I F NOT PROC RESET THEN DONE
A,RST_STS
;ELSE GET LAST RESET TYPE
A,#PRST_TYPE,END_R6
;IF NOT PRST THEN
;DONE
;ELSE SET PRST = TRUE
PRST
;RETURN TO IC HANDLER

SEJECT

C.B.

RD06H Read Local Processor Control Register

5·103

AP-423

;*******...*.*****************************************
NAME:

RD07H

PURPOSE:

READ ROUTINE FOR LOCAL STATUS
REGISTER

CALLED BY:

JUMPED TO FROM SERVICE

CALLS:

NONE

NEST LEVEL:

DESCRIPTION:

IF RESET STATUS = PRST TYPE, THEN
PRST STATUS = TRUE, ELSE PRST
STATUS = FALSE.

REG BANK:

ASSUMES IC_BANK, SELECTS NONE

INPUTS:

NONE

DESTROYS:

CARRY FLAG

RETURNS:

ICDATA

UPDATE HISTORY:

5·14·87 JR ADDED FOR IDX

i****'*************************************************
RD07H:

MOY
MOY
CJNE

SETB
END_R7: RET

ICDATA,#CLEAR
; ICDATA = O.
A, RST_STS
;GET LAST RESET TYPE
A,flPRST_TYPE,END_R7 ;IF NOT PRST THEN
;DONE
ICDATA.PRST_STS ;ELSE PRST_STS = TRUE
;RETURN TO IC HANDLER

SEJECT

C.9. RD07H Read Local Status Register

5-104

AP-423

,.********************.*.111 •••••• *.*********************

NAME:

WROOH

PURPOSE:

WRITE TO A RAM BASED IC REGISTER

CALLED BY:

JUMPED TO FROM EDIT ROUTINES

CALLS:

NONE

NEST LEVEL:

DESCRIPTION:

USES REGNUM TO INDEX INTO RATABLE.
USES RWTABLE INDEX PORTION OF RA BYTE
TO INDEX INTO RWTABLE, I/HERE ICDATA
IS THEN I/RITTEN TO.

REG BANK:

ASSUMES IC_BANK, SELECTS NONE

INPUTS:

REGNUM

DESTROYS:

ACC, DPTR, ADDR

RETURNS:

NOTHING, RETURNS TO ICHANDLER

UPDATE HISTORY:

;

;****************************.************************
WROOH :

"LOOKUP (#RA TABLE, REGNUM)

;GET RAM/ACCESS
; BYTE FOR REG

CLR
ADD

ACC.GAR

MDV

ADDR,A

MOV

iilADDR,lCDATA

A,#RI/TABLE

;EXTRACT RWTABLE INDEX
;ADD TABLE ADDR TO GET RAM

;ADDR
;PUT ADDR IN INDIRECT ADDR REG

RET

;I/R RI/TABLE REG
;RETURN TO IC HANDLER

$EJECT

C.10.

WROOH Write RAM Based IC Register

5-105

AP-423

; ****************.************************************
NAME:

IIRO'H

PURPDSE:

IIRITE ROUTINE FOR MPC BASED IC
REGISTERS

CALLED BY:

JUMPED TO FROM ED IT ROUTINES

CALLS:

NONE

NEST LEVEL:

DESCRIPTION:

USES LOOKUP TABLE IC_TO_MPC TO lIREF
IC ADDRESS TO MPC REGISTER NUMBER,
IIRITES MPC REG IIITH DATA IN ICDATA.

REG BANK:

ASSUMES IC_BANK, SELECTS NONE

INPUTS:

ICDATA

DESTROYS:

DPTR, MPC_RNUM

RETURNS:

NOTHING, RETURNS TO ICHDLR

UPDATE HISTORY:

;*--._.*••-••------_..•._._._*-------_......_...---_..
i

IIRO'H:

MOV
SUBB

A,REGNUM
iGET REQUESTED REG NO.
A,#PSB_CTL_OFF+5
i IC_TO_MPC STARTS
. iWITH PSB SLOT ID REG
'XLOOKUP(#I C_TO_MPC ,A) iGET CORRES MPC REG NO.
XWRT_MPC(A,ICDATA)
iWR MPC REG
, RET
iRETURN TO IC HANDLER

SEJECT'

C.11. WR01 H Write MPC Based IC Register

5-106

AP-423

; *****************************************************
NAME:

WR02H

PURPOSE:

WRITE ROUTINE FOR GENERAL CONTROL
REGISTER

CALLED BY:

JUMPED TO FROM EDIT ROUTINE

CALLS:

NONE

NEST LEVEL:

DESCRIPTION:

PROC RESET .. LOCAL RESET. IF LOCAL
RESET, THEN UPDATE RESET STATUS REG.
UPDATES GEN_CTRL IN RWTABLE BY
JUMPING TO WROOH.

REG BANK:

ASSUMES IC_BANK, SELECTS NONE

INPUTS:

ICDATA

DESTROYS:

NOTHING

RETURNS:

NOTHING, JUMPS TO WROOH

UPDATE HISTORY:

5·14·87 JR UPDATED FOR lOX

,.**********.******************************************
WR02H:

",",OVBIT(RES,ICDATA.LRST) ;UPDATE RST PORT PIN
JNC
END_W2
; I F NO LOCAL RESET THEN DONE
MOV
RST_STS,flLRST_TYPE ;ELSE UPDATE RESET
; STATUS
END_W2: SJMP
WROOH
SEJECT

C.12. WR02H Write General Control Register

5-107

AP-423

; *****************************************************
NAME:

WR03H

PURPOSE:

WR ITE ROUTI NE FOR PROTECTION LEVEL
REGISTER

CALLED BY:

JUMPED TO FROM EDIT ROUTINE

CALLS:

NONE

NEST LEVEL:

DESCRIPTION:

SETS DYNAMIC ACCESS RIGHTS AS
REQUESTED

REG BANK:

ASSUMES IC_BANK, SELECTS NONE

INPUTS:

ICDATA

DESTROYS:

CARRY FLAG

RETURNS:

NOTHING, RETURNS TO ICHOLR

UPDATE HISTORY:

; *****************.***********************************
WR03H:

XMOVBIT(UACRS,ICOATA.ACRS)iUACRS
RET

= ICOATA.ACRS

iRETURN TO IC HANDLER

SEJECT

C.13. WR03H Write Protection Level Register

AP-423

; **********.***********************************.******
NAME:

WR04H

PURPOSE:

WRITE ROUTINE FOR PSB CONTROL/STATUS
REGISTER

CALLED BY:

JUMPED TO FROM ED IT ROUTI NE

CALLS:

NONE

NEST LEVEL:

DESCRIPTION:

SINCE RST TYPE BITS MUST = 0 WHEN
WRITING THIS REGISTER, RSTNCOUT IS
CLEARED I N THE MPC GENERAL PARAM REG.
ALSO,

THE PRY BIT IN THE GEN PARAM

REG IS MODIFIED ACCORDING TO ICDATA
BIT HPRO.

SINCE THE GEN PARAM REG

SUPPORTS OTHER FUNCTIONS, A
READ/MODIFY/WRITE OPERATION IS USED.
REG BANK:

ASSUMES IC_BANK, SELECTS NONE

INPUTS:

ICDATA

DESTROYS:

ACC, CARRY FLAG, MPC_RNUM

RETURNS:

NOTHING

UPDATE HISTORY:

;

; *****************************************************
WR04H:

MOV

A,PSB_CS ;GET VALUE OF PSB CONT/STAT REG

%MOVBIT(lCDATA.RSTHO,ACC.RSTHO)

;SAVE RESET

;TYPE HISTORY BITS
%MOVBIl( ICDATA.RSTH1,ACC.RSTH1)
MOV
PSB_CS,ICDATA
%RD_MPC(A,#GEN]AR)

;UPDATE RWTABLE

;READ MPC GEN_PAR
CLR
ACC. RSTNCOUT
;QUIT DRVG RSTNC TO BUS
%MOVBIT(ACC.PRY,ICDATA.HPRO)
;UPDATE PRY BIT
%WRT_MPC(#GEN]AR,A)

;WR MODI FlED DATA
; BACK TO GEN PAR
;RETURN TO IC HANDLER

RET
$EJECT

C.14.

WR04H Write PSB Control/Status Register

5-109

AP-423

,. *****************************************************
NAME:

WROSH

PURPOSE:

WRITE ROUTINE FOR PSB DIAGNOSTIC
REGISTER

CALLED BY:

JUMPED TO FROM EDIT ROUTINE

CALLS:

NONE

NEST LEVEL:

DESCRIPTION:

UPDATES PSB_DIAG REG IN RWTABLE.

LOOPBACK MODE SELECTED, THEN TURNS
OFF BUS TRANSCEIVERS AND WRITES MPC
DIAG REG, ELSE WRITES MPC DIAG REG
AND ENABLES TRANSCEIVERS.
REG BANK:

ASSUMES IC_BANK, SELECTS NONE

DESTROYS:
INPUTS:

ICDATA

RETURNS:

NOTHING, RETURNS TO ICHDLR

UPDATE HISTORY:

;************************************************.****
WROSH: 'MOV
JB

PSB_DIAG,ICDATA
ICDATA.LBACK,BUSOFF

;UPDATE RWTABLE
; I F LOOPBACK
;SELECTED, THEN JUMP

%IIRT_MPC(#OIAG,ICDATA)
SETB

BTROE

JMP

END_WS

; ELSE WR MPC REG
; ENABLE BUS XCVRS
;DO NO MORE

BUSOF F: CLR
BTROE
%IIRT_MPC(fID IAG,ICDATA)

;DISABLE XCVRS
;WR MPC REG
;RETURN TO IC HANDLER

END:.,WS: RET
$EJECT

C.1S. WROSH Write PSB Diagnostic Register

5·110

AP-423

; *****************************************************
NAME:

IIRD6H

PURPOSE:

IIR ITE ROUTI NE FOR LOCAL PROC CONTROL
REGISTER

CALLED BY:

JUMPED TO FROM ED IT ROUTI NE

CALLS:

NONE

NEST LEVEL:

DESCRIPTION:

IF ICDATA BIT PRST SET. ASSERT RESET
TO PROC AND UPDATE RESET STATUS REG.

INPUTS:

ICDATA

REG BANK:

ASSUMES IC_BANK. SELECTS NONE

DESTROYS:

CARRY FLAG

RETURNS:

NOTHING

UPDATE HISTORY:

5·14-87 JR ADDED FOR lOX

; *****************************************************
IIR06H:

JNB
SETB

ICDATA.PRST .END_1I6; IF NO RESET THEN DONE
RES

;ELSE ASSERT RESET TO PROC
;UPDATE RESET
;STATUS REG

PRST_CNTR.#PRST_CNT

;LOAD PRST COUNTER
;RETURN TO IC HANDLER

SEJECT

C.1S.

WROSH Write Local Processor Control Register

5-111

AP·423

; *****************************************************
MACRO NAME:

GET_EEC (GET EDIT ENTRY CONSTANT).

SYNTAX:

GET_EEC

PURPOSE:

INDEX INTO EETABLE TO GET NEXT EDIT
ENTRY CONSTANT

DESCRIPTION:

EET_OFF IS INCREMENTED AND THE CODE
BYTE AT EET_OFF FROM DPTR (ASSUMED TO
BE POINTING TO EETABLE) IS MOVED TO
THE ACCUMULATOR.

INPUTS:

NONE, HOWEVER DPTR ASSUMED

= EETABLE

(INTR ROUTINES USING DPTR SHOULD
PUSH/POP).
DESTROYS:

ACC

RETURNS:

NEXT EET CONSTANT FROM LIST IN ACC

UPDATE HISTORY:

; *****************************************************
X*DEFINE(GET_EEC)(
SSAVE NOGEN
INC

EET_OFF

MOV

A,EET_OFF

MOVC

A,iilA+DPTR

SRESTORE
)

SEJECT

C.17.

Macro GET.EEC

5·112

AP-423

i************************************************·*·**
NAME:

VALERR

PURPOSE:

ROUTINE FOR REPORTING IC WRITE VALUE
ERRORS

CALLED BY:

JUMPED TO FROM ED IT ROUTI NES UPON
VALUE ERROR DETECTION

CALLS:

NONE

NEST LEVEL:

DESCR I PTI ON:

CHECKS FOR LOCAL OR GLOBAL ACCESS AND
UPDATES GENERAL STATUS REGISTER
ACCORDINGLY WITH VALUE ERROR STATUS.
RETURNS TO I CHDLR.

REG BANK:

ASSUMES 0, SELECTS NONE

INPUTS:
DESTROYS:
RETURNS:

NOTHING
GENERAL STATUS REG, UPDATED FOR VALUE
ERROR, TO ICHDLR

UPDATE HISTORY:

; **********************************.*****************.
VALERR: JB

MPC_STS.PORT ,LCVLER

; I F LOCAL ACCESS

ORL

GEN_STS,#GBL_VL_ERR

;SET GENERAL STATUS
; = GLOBAL VALUE ERROR

SJMP

ENDVAL

;THEN JUMP, ELSE

LCVLER: ORL

; RESTORE AND RETURN

GEN_STS,#LCL_VL_ERR

;SET GENERAL STATUS
LOCAL VALUE ERROR

;=
ENDVAL: RET

; RETURN TO I CHANDLER

SEJECT

C.18.

Report IC Write Value Error

5-113

AP-423

i*****************************************************
NAME:

ERDDH
GENERATE LOCAL STATIC ACCESS RIGHTS

PURPOSE:

ERROR
CALLED BY:

JUMPED TO BY SERVI CE

CALLS:

NONE

NEST LEVEL:

DESCRIPTION:

EDIT VECTOR D GETS EDIT ENTRY 0,
WHICH IS USED FOR LOCAL READ ONLY
REGISTERS.

ONCE HERE, THE GENERAL

STATUS REG IS UPDATED FOR LOCAL
STATIC ERROR.

THE ACCESS IS THEN

TERMI NATED.
REG BANK:

ASSUMES I C_BANK , SELECTS NONE

INPUTS:

NOTHING

DESTROYS:

NOTHING

RETURNS:

NOTHING, RETURNS TO ICHDLR

UPDATE HISTORY:

i*****************************************************
ERDOH:

ORL
RET

GEN_STS,#LCL_ST_ERR

;UPDATE GSR

;BACK TO IC HANDLER TO TERMINATE ACCESS

$EJECT

C.19.

EROOH Generate Local Static Access Rights Error

5-114

AP-423

i*****************************************************
NAME:

ER01H

PURPOSE:

CHECK ALL RFU BITS

CALLED BY:

JUMPED TO FROM SERVI CE

CALLS:

NONE

NEST LEVEL:

DESCRIPTION:

INDEXES INTO THE EDIT ENTRY TABLE TWO
TIMES, ONCE FOR THE EDIT CONSTANT AND
THEN A SECOND TIME FOR THE OFFSET TO
THE WRITE ROUTINE.
WITH ICDATA.
ALL RFU

ANDs CONSTANT

IF RESULT> 0, THEN NOT
JUMPS TO VALUE ERROR

ROUTINE, ELSE JUMPS INDIRECTLY TO
WRITE ROUTINE.
REG BANK:

ASSUMES IC_BANK, SELECTS NONE

INPUTS:

EET_OFF ,ICDATA

DESTROYS:

ACC, DPTR, EET_OFF

RETURNS:

NOTHING, JUMPS TO VALERR, ELSE WRITE
ROUTINE

UPDATE HISTORY:

i*****************************************************
ER01H:

INC
EET_OFF
; INC INDEX INTO EETABLE
%LOOKUP(#EETABLE,EET_OFF)
;GET CONSTANT
ANL

A,ICDATA

JNZ

ERR_1

;CHECK VALUE OF ICDATA
; JMP I F I LLEGAL VALUE
;GET WR ROUTINE OFFSET FM EET

%GET_EEC

ERR_1:

MOV

DPTR,#WRLBL

JMP

&lA+DPTR

AJMP

VALERR

;GET WR ROUTINE LABEL AODR
;JMP TO WR ROUTINE
;REPORT VALUE ERR
; (TOO FAR FOR REL JMP)

SEJECT

C.20.

ER01H Check for RFU Bits

5-115

AP-423

,.****************************************************.
NAME:

ER02H

PURPOSE:

CONST_' <= lCDATA <= CONST_2

CALLED BY:

JUMPED TO FROM SERVI CE

CALLS:

NONE

NEST LEVEL:

DESCRIPTION:

ICDATA BANDPASS FILTER.

IF VALUE OF

ICDATA IS WITHIN THE RANGE SPECIFIED
BY THE TWO CONSTANTS FROM THE EET,
THEN THE WRITE ROUTINE OFFSET FROM
EET IS JUMPED TO, ELSE A VALUE ERROR
IS REPORTED IN THE GENERAL STATUS
REG.
BYTES:

THUS EET MUST INCLUDE THREE
CONST_, :

SMALLEST LEGAL

VALUE FOR ICDATA, CONST_2:

LARGEST

LEGAL VALUE FOR ICDATA, AND AN WRITE
ROUTINE OFFSET
REG BANK:

ASSUMES IC_BANK, SELECTS NONE

INPUTS:

EET_OFF, ICDATA

DESTROYS:

ACC, DPTR, EET_OFF, TEMP

RETURNS:

NOTHING, JUMPS TO WRITE ROUTINE, ELSE
VALERR

UPDATE HISTORY:

,.**********.************.**************************.**

C.21.

ER02H ICDATA Between Two Values

5-116

AP-423

ER02H:

INC
MOV

TEMP,A

MOV

A,ICDATA

= EET-OFF+1

;GET CONST 1
; STORE CONST_1

; GET VALUE BE I NG IIR ITTEN
;SUB CONST_1 FM ICDATA

%SUB(TEMP)
JC

;EET OFF

EET_OFF

%LOOKUP(#EETABLE, EET_OF F)

;IF ICDATA < CONST_1 THEN

ERR_2

;VALUE ERR
;GET CONST 2

%GET_EEC
%SUB(lCDATA)
JC

;SUB ICDATA FM CONST_2
;IF ICDATA > CONST 2 THEN

ERR_2

;VALUE ERR
;GET IIR ROUTINE OFFSET

%GET_EEC

ERR_2:

MOV

DPTR, IIIIRLBL

JMP

@A+DPTR

AJMP

VALERR

;POINT TO IIR ROUTINE LABEL
;JMP INDIRECT TO IIR ROUTINE
; JMP TO VALUE ERR ROUT I NE

$EJECT

C.21.

ER02H ICDATA Between Two Values (Continued)

5·117

AP-423

;..__.•.._.__._._-_.__._.•••_------.-•.•-._--_.-.----*
NAME:

ER03H

PURPOSE:

EDIT ROUTINE FOR PSB ARB 10 REGISTER

CALLED BY:

JUMPED TO FROM SERVICE

CAUS:

NONE

NEST LEVEL:

DESCRIPTION:

CHECKS AU RFUs ~ 0, THEN CHECKS FOR
LEGAL ARB 10 BY COUNTING THE BIT
TRANSITIONS IN ICDATA.

REG BANK:

ASSUMES IC_BANK, SELECTS NONE

INPUTS:

NONE

DESTROYS:

ACC, TEMP

RETURNS:

JUMPS DIRECTLY TO WR01H, ELSE VALERR

UPDATE HISTORY:

;•••*_.*••••••_---_._.•.•_*....*---------_._--_._-_._.
ER03H:

MOV
ANL
JNZ
MOV
MOV
CLR
RLC
JNC
SETB

ID_TR:
ROT_A:

XRL
CLR
RLC
JNC

ERR_3:

DJNZ
AJMP

AJMP

; GET RFU MASK
A,ICDATA
;MASK ALL BUT RFUs
ERR_3
; I F NOT ALL RFUs = 0 THEN ERROR
TEMP,#TRANS_CNT
; LOAD TRANS CNTR
A,ICDATA
;GET VALUE BEING WRITTEN
C
A
;SEE IF MSB SET
; I F NO CARRY, THEN OK
ID_TR
ACC.3
.. ;ELSE SET BIT 3
;(ARB 10 IS ONLY 5 BITS)
A,ICDATA
; 10 BIT TRANSITIONS
C
-' ROTATE ZEROS INTO ACC
; LOOK FOR TRANS IT IONS
A
; IF CARRY BIT IS NOT SET
CHK_ACC
;THEN JMP
TEMP ,ROT_A ;ELSE TALLY UP ONE TRANSITION
VALERR
; I F TRANS_CNTR REACHES ZERO
;THEN ERROR
; I F ACC NOT ZERO
;THEN CONTINUE LOOKING
;ELSE' JUMP TO WR ROUTINE
WR01H

SEJECT

C.22. ER03H Edit PSB ARB ID Register

5-118

AP-423

;*****************************************************
NAME:

ER04H

PURPOSE:

EDIT ROUTINE FOR PSB DIAG REGISTER

CALLED BY:

JUMPED TO FROM SERVI CE

CALLS:

NONE

NEST LEVEL:

DESCRIPTION:

CHECKS ALL RFUs

D, THEN IF

LOOPBACK MODE BEING SELECTED,
CHECKS FOR RSTNC· ASSERTED.
REG BANK:

ASSUMES IC_BANK, SELECTS NONE

INPUTS:

NONE

DESTROYS:

ACC, DPTR

RETURNS:

JUMPS DIRECTLY TO WRD6H, ELSE VALERR

UPDATE HI STORY:

,
; *****************************************************
ERD4H:

MOV

A,#PSB_DIAG_MSK

ANL
JNZ

A,ICDATA

JNB

ICDATA.LBACK,END_E4

MOV

A,#RST_TYPE_MSK

;GET MASK FOR RESET

ANL

A,PSB_CS

; MASK ALL BUT RESET

ERR_4

;GET PSB DIAG RFU MASK
;MASK ALL BUT RFUs
; IF ALL RFUs NOT = 0

ERR_4

;THEN VALUE ERROR
; I F LOOPBACK NOT

;SELECTED, SET THE WR REG
;TYPE BITS
; TYPE FROM PSB CIS
; I F RSTNC HAS BEEN CLEARED
; THEN VALUE ERR
END_E4: AJMP

WROSH

ERR_4:

VALERR

AJMP

;WR REG
; REPORT VALUE ERROR

SEJECT

C.23.

ER04H Edit PSB Diagnostic Register

5·119

AP-423

; ••••••*** •••••••••••••••••••• **.*••• *.* •••• *•••• *•••*
NAME:
PURPOSE:

EROSH
EDIT ROUTI NE FOR REGISTERS
REQUIRING> THAN CHECK

CALLED BY:

JUMPED TO FROM SERVICE

CALLS:

NONE

NEST LEVEL:

DESCRIPTION:

CHECKS FOR ALL RFUs = O. MASKS OFF
ANY DON'T CARE BITS, CHECKS FOR IIRITE
DATA (lCDATA) <= MAX ALLOIIABLE VALUE.
IF BOTH CHECKS PASS, THEN JUMPS
INDIRECTLY TO IIRITE ROUTINE, ELSE
VALUE ERROR.
EET(2)

EET(1)

= DON'T

RFU MASK.

CARE MASK.

MAX ALLOIIABLE IIRITE VALUE.

EET(3)
EET(4)

IIRITE ROUTINE OFFSET.
REG BANK:

ASSUMES IC_BANK, SELECTS NONE

INPUTS:

ICDATA

DESTROYS:

ACC, TEMP, DPTR

RETURNS:

JUMPS INDIRECTLY TO IIRITE ROUTINE,
ELSE VALERR

UPDATE HISTORY:

;•••••••••••••••••••••••••••• *••••••••••••••••••••••••

C.24.

ER05H Edit Register for Greater Than Check

5-120

AP-423

EROSH:

;POINT TO RFU MASK IN EETABLE
INC
EET_OFF
%LOOKUP(#EETABLE,EET_OFF)
;GET IT
ANL

A,ICDATA

JNZ

ERR_5

%GET_EEC
ANL

;CHECK FOR ALL RFUs

;JMP IF ILLEGAL VALUE
; GET DON'T CARE MASK FROM EETABLE
;MASK OFF DON'T CARE BITS

A,ICDATA

; FROM ICDATA
;SAVE RESULT

MOV
TEMP, A
%GET_EEC

; GET MAX ALLOWABLE WR VALUE

%SUB(TEMP)
JC

ERR_S

;SUB VALUE BEING WRITTEN
;IF ICDATA > MAX ALLOWABLE VALUE,
;THEN ERR

%GET_EEC

ERR_S:

;ELSE GET WR ROUTINE OFFSET

MOV
JMP

DPTR,NWRLBL
Ci)A+DPTR

AJMP

VALERR

;POINT TO WR ROUTINE
;GO TO WR ROUTINE
;REPORT VALUE ERROR

SEJECT

C.24.

ER05H Edit Register for Greater Than Check (Continued)

5-121

AP-423

APPENDIX D
USER CALLABLE MACRO ROUTINES

,..*._._...._._. __..._._*-_.... _.__ ._-_._._-------_. __.
MACRO NAME:

RD_MPC

(READ MPC)

SYNTAX:

RD_MPC(DEST ,SRC)

PURPOSE:

READ REGISTER FROM MPC IC REGISTER
SET

DESCRIPTION:

THE VALUE CONTAINED IN OR BY SRC (MAY
BE CONSTANT OR DIRECT ADDRESS) MUST
BE A LEGAL MPC REGISTER ADDRESS.

THE

DEST, SRC

DESTROYS:
RETURNS:

MPC REGISTER DATA IN DEST

;. UPDATE HISTORY:
i •••

_-*..•-......-•.-•.•.•_..-...--*_.•.•.••..._.•..._.

%*DEFINE(RD_MPC(DEST ,SRC»(
SSAVE nogen
MOV
MOVX,

A,iilMPC_RNUM

%IF(%NES(A,%DEST»
MOV
)FI

THEN (

%DEST ,A

SRESTORE
)

SEJECT

0.1.

Macro RO_MPC

5·122

Ap·423

; ***.*************************************************
MACRO NAME:

IIRT_MPC

SYNTAX:

WRT_MPC(DEST ,SRC)

PURPOSE:

WRITE DATA TO MPC IC REGISTER

DESCRIPTION:

(WRITE MPC)

THE VALUE CONTAINED IN OR BY SRC (MAY
BE CONSTANT OR DIRECT ADDRESS) IS
WRITTEN TO THE MPC REGISTER SPECIFIED
BY DEST, WHICH MAY ALSO BE A CONSTANT
OR DIRECT ADDRESS.

INPUTS:

DEST, SRC

DESTROYS:
RETURNS:

NOTHING

UPDATE HISTORY:

;*****************************************************
%*DEFINE(WRT_MPC(DEST, SRC»(
SSAVE nogen
MOV
MPC_RNUM, %DEST
%IF(%NES(A,%SRC» THEN
MOV

A,%SRC

HI
MOVX
SRESTORE
)

SEJECT

0.2.

Macro WRT.MPC

5-123

AP-423

; .****************************************************
MACRO NAME:

LOOKUP

SYNTAX:

LOOKUPCTABLE,OFFSET)

PURPOSE:

RETRIEVE BYTE FROM TABLE.

DESCRIPTION:

THE SPECIFIED TABLE IS INDEXED BY THE
VAlUE OF OFFSET AND RESULTING ADDRESS
IS READ INTO THE ACCUMULATOR.

INPUTS:

TABLE, OFFSET

DESTROYS:

DPTR, ACC

RETURNS:

DESIRED BYTE IN ACC

UPDATE HISTORY:

i*****************************************************
%*DEF I HE (LOOKUP'(T ABLE ,OFFSET» (
$SAVE nogen
%1 F(%NES(A,%OFFSET»
MOV
)FI

A,%OFFSET

MOV

DPTR,%TABLE

MOVC

A,&lA+DPTR

THEN (

$RESTORE
)

$EJECT

0.3. Macro LOOKUP

5-124

AP-423

i*****************************************************
(SUBTRACT)

MACRO NAME:

SUB

SYNTAX:

SUB(OPR)

PURPOSE:

SUBTRACT OPERAND FROM ACC

DESCRIPTION:

THE CARRY FLAG IS CLEARD AND THE
VALUE SPECIFIED IN OR BY OPR IS
SUBTRACTED FROM THE ACCUMULATOR.

INPUTS:

OPR

DESTROYS:

ACC, CARRY FLAG

RETURNS:

RESULT IN C AND ACC

UPDATE HISTORY:

; *****************************************************
%*DEFINE(SUB(OPR) )(
$SAVE nogen
CLR

SUBB

A,%OPR

$RESTORE
)

$EJECT

0.4.

Macro SUB (Subtract)

5·125

AP·423

i*****************************************************
MACRO NAME:

MOVBIT

PURPOSE:

PERFORM A BIT MOVE OPERATION

DESCRIPTION:

THE SOURCE BIT IS MOVED TO THE CARRY
FLAG.

(MOVE BIT)

THE CARRY FLAG I S MOVED TO THE

DESTINATION B[T.
INPUTS:
DESTROYS:

CARRY FLAG

RETURNS:
UPDATE HISTORY:

:******************************************••********.
%*DEFINE(MOVBIT(DEST_BIT ,SRC_BIT»(
SSAVE

nogen
MOV

C,%SRC_BIT

MOV

WEST_BIT ,C

SRESTORE
)

SEJECT

0.5.

Macro MOVBIT

5-126

Ap·423

i*****************************************************
MACRO NAME:

GET_EEC (GET EDIT ENTRY CONSTANT)

SYNTAX:

GET_EEC

PURPOSE:

INDEX INTO EETABLE TO GET NEXT EDIT
ENTRY CONSTANT

DESCRIPTION:

EET_OFF IS INCREMENTED AND THE CODE
BYTE AT EET_OFF FROM DPTR (ASSUMED TO
BE POINTING TO EETABLE) IS MOVED TO
THE ACCUMULATOR.

INPUTS:

NONE, HOWEVER DPTR ASSUMED

= EETABLE

(INTR ROUTINES USING DPTR SHOULD
PUSH/POP).
DESTROYS:

ACC

RETURNS:

NEXT EET CONSTANT FROM LIST IN ACC

UPDATE HISTORY:

i*****************************************************
%*DEFINE(GET_EEC)(
$SAVE NOGEN
INC

EET_OFF

MOV

A,EET_OFF

MOVC

A,iilA+DPTR

$RESTORE
)

$EJECT

0.6.

Macro GET.EEC

5-127

APPLICATION
NOTE

AP Note-431

March 1989

Multibus II Simplifies
Partitioning of
a Comple.x Design,

FRANCOIS HUGUENIN
SENIOR FIELD APPLICATION ENGINEER
INTEL SWITZERLAND '
® Intel Corporation, 1989

Order Number 280691-001

5-128

AP-431
MULTIBUS II SIMPLIFIES PARTITIONING OF A COMPLEX DESIGN
Francois Huguenin
Senior Field Application Engineer
Intel Switzerland
PREFACE

Several years ago, prior to joining Intel, I wOlked at the
Swiss Federal Institute of Technology in the Group for
Automatic Control. As part of my job responsibilities
there, we made some real-time simulation studies in
the field of aircraft performance computers. The engine model was implemented on an 8086-based single
board computer. It also had special custom-made
hardware for displaying the instruments similar to
those in the original aircraft cockpit. During the course
of this work, we were able to demonstrate the
feasibility of using microcomputers in this application
field. A paper describing this work was then presented
at the AIAA Flight Simulation Technologies Conference, Long Beach, California in June 1980 [1].
While the use of microcomputers in aircraft simulation
has become quite common in recent years, this work
anticipated the impact of major cost reductions and
performance improvements which were to follow in
the flight simulation industry.
In more recent years, I have served as an Application
Engineer for Intel Corporation in the Swiss District. In
this role I am often confronted with the problem of how
to demonstrate the capabilities of a product in a way
which engineers can easily relate to and understand.
This was the case with MULTIB US II - an industry
standard bus, specially designed for the more rigorous
demands of multiprocessing. Since few applications
today are partitioned to take advantage of parallel
computing, my goal was to demonstrate how functional partitioning could be applied to a computationally
intensive application with relative ease. The goal of
breaking the "Von Neuman bottleneck" would be to
increase the aggregate computing power without a
substantial increase in overhead.

ment and debug tools, and then finally test for performance tuning on the fmal system once it is up and
running. As you read through this document you will
learn about the process of application development in
addition to the special demands of the aircraft simulation experiment.
I would like to thank Markus Schoenbucher and Christoph Graf of the Furrer & Gloor Company for their
great support during the weeks of implementation in
the labs. George Walker of WeDV deserves special
thanks for designing and debugging the iRMX® II part
of the application. I wish also to thank P. Marti, H. -R.
Aeschilrnann, K. Krizaj and B. Leiser of the Simulator
Maintenance Group at Swissair in Zurich who gave me
access in the early phase to all the important engine
data and most valuable inputs on the flight simulation
technology in general back in the late 70's. Finally I
especially want to thank Roger Finger from MULTIBUS II Application Engineering at the Intel factory in
Hillsboro, Oregon for his guidance in helping me get
this Ap Note done and for his corrections to my "Swiss
English".

For assistance on this project, I called upon the Furrer
& Gloor Company, a MULTIBUS manufacturer with
broad experience in industrial automation. With theii'
assistance I was able to modify the work done seven
years ago on aircraft simulation and convert it to
MULTIBUS II to demonstrate multiprocessing. This
application provides a good example of the typical
MULTIBUS II design cycle. We begin with the basic
architectural decisions, defme the message contents
between processors, show the use of software develop5-129

- Francois Huguenin

AP-431
1.0 INTRODUCTION

2.0 DESIGN PROBLEM OF THE
SIMULATION OF THE JET ENGINE

Aircraft simulation trains pilots at a substantial savings.
Flight crews can train around the clock, without regard
to ·weather conditions and airport congestion. This
important simulation model is a complex technical
system which includes several high-performance digital computers. One key part of the simulator is ,the
engine model: it is vital to the functioning of the entire
machine:

The General Electric CF6-5OC Fan Jet Engine which
is installed on all Swissair's DC-lO aircraft provides
our study model. This engine of the now "older"
generation delivers up to 75% of the thrust power
through the fan. The model designed during the years
1978 to 1980 is based on data made available by the
engine manufacturer General Electric, McDonnell
Douglas for the installed data (measurements made
during the certification of the DC-I0) and fmally from
CAE, the flight simulator manufacturer, with the actual
programs written in assembler for the SIGMA computer.

- For the flight model equations (thrust and torque)
- For the "man in the loop" process with the important flight deck instruments (the pilot reacts on the
settings and feedback from the engine instruments)
- For the f1igIit engineer with all subsystems which
are fed by the engines (hydraulics, electrical
power supply, air conditioning, anti-icing, etc.)

2.1 The engine model
In order to be as realistic as possible, the engine model
is very complex and has the following main characteristics:

The basic problem for good simulation is computing
speed, because the quality of the pilot's training is a
direct function of the flight simulator's update speed.
Previously most simulators were using more than one
processor based on a shared memory architecture. The
trend today is dictated by the ever-increasing complexity of modem aircraft which are using more and
more electronics on board. The new generation of
flight simulators has a collection of black boxes
(navigation computer, display units, engine control)
used dire<;:tly as in the original aircraft. In this complex
environment, the engine is a closed subsystem which
can be modeled without having to build a whole flight
simulator. This part of the machine has well-known
interaction points to the rest of the simulator. The work
which was done at the Swiss Federal Institute of Technology some years ago was to be part of an on-board
performance computer to calculate fuel optimal flight
trajectories [2]. The following implementation of the
engine model with MULTIBUS IT is based on these
results.
-

- It is multivariable, with secondary interdepen-

dencies.
- It has basically two states: the transient state

when coming up after ignition, and steady state
when being held at a stable working point.
- It is a function of many parameters which directly
influence the engine.
A cross section of the CF6-5OC engine is shown in
Figure 2.1.
Undoubtedly, the main problem of the model is the fuel
control unit, which controls the whole engine. This
unit also defines the transient behavior of the engine
startup and excursions of the wOlking point in the
steady state mode. Of course, some simplifications are
necessary for simulation. It was necessary to concentrate on the steady state model to reduce the modeling problem to a manageable task [1]. No startup

FAN 100STER STAGES

f N 11

VARIABLE' BYPASS VALVES

----+--+-__

HIGH PRESSURE COMPRESSOR CNzl

LOW P1tUSURE TURBINE (Nil

HIGH PltESSURE 'I'UIilIINE (Nt I
ANNUL"" CO"IUSTER

FIGURE 2.1:

THE CF6·S0C ENGINE LAYOUT

5-130

AP·431

POWE R
ANGL E

POWER
LEVER

N2
1

·1

•

T
m

INLET

CORE
SPEED

I
I

ALT
SWITCH
ON/OFF

•

CF6-50C
ENGINE MODEL

STEADY STATE

THRUST
FUEL
FLOW
EGT
EPR

I
FIGURE 2.2:

THRUST
FUEL FLOW

TONS/HOUR
TEMPERATURE
PRESSURE
RATIO

ENGINE MODEL STRUCTURE FOR STEADY STATE OPERATION

sequence of the engine was to be modelled, but this
approach has the great advantage of allowing the direct
use of the previously mentioned data tables from the
engine manufacturer. The model was exact in the
range for which the data tables were originally
measured. This reduced and more manageable model
is show in Figure 2.2.
A collection of modules are building the model with
some interactions between them. These subsystems

are:
- INLET:

r
r
r

FAN
SPEED

Reduction of mach, temperature
and pressure to standard values
sea level, standard day and
temperature
- POWER
Model of the power lever in the
LEVEL:
cockpit. From these, the pilot sets
the throttles
- N2
Simplified model of the fuel conTRANSIENT: trol unit (basically a fourth order
digital filter)
- NI:
Model of the FAN as function of
machandN2
- THRUST:
Model of the thrust as function of
NI andN2
Model of the fuel flow inside the
- FUEL
FLOW:
engine in tons per hour as function of N2, altitude and mach
Model of the engine temperature
- EGT:
as function of N2 and mach

- EPR:

Model of the engine pressure ration as function of mach and N2

The power plant of an aircraft is, as mentioned before,
a closed system and provides additional tasks besides
thrust for motion. The engine must provide fresh air
. for the cabin, and electric power for the cockpit,
kitchen, cockpit electronics, etc. It must also activate
and sustain the hydraulic subsystem for the control
surfaces of the wings, and feed the anti-icing system
for the wing tips, etc. The model, to be realistic, must
take into account that these additional tasks will also
have an appreciable influence on the state of the engine.
This can be demonstrated best with the fuel model as
shown in Figure 2.3. The fuel model is basically a
function of mach and N2 (referred core speed). This
gives the main data cUlVe and the basic fuel flow in
tons per hour and will be interpolated through a highspeed algorithm. When the aircraft is climbing, the
fuel flow will change according to a second data cUlVe
for correction with the value DELTA EWFAI. The
correction, due to the on or off switching of air conditioning, etc., will also be taken into account with
other data tables. The total fuel flow, as well as the fuel
used by the engine, finally can be calculated with all
the deltas. This model was validated with actual data
taken from the Aircraft Data System of the DC-IO [I].

5-131

AP-431

litttJI[. ~A o-illJT
~ KORR.

•

MACH

WFA

.•

I~UC' J

ALTITUD E

--+

AIRCOND. ~
HPX
5
ANTI·ICE

t~N: r~2

EXAMPLE OF THE FUEL SUBSYSTEM MODEL

interface. These new requirements introduce a need
for synchronization and communications across the
backplane. The implementation of the single processor system will be discussed fIrst, followed by the
multiprocessing extensions.

The task to be done now can be summarized as follows:
Every 20msec calculate a new state of all three
engines of the DC·lO based on the power lever
position of the cockpit and the subsystem
switches for air conditioning, anti· ice, etc.

2.3 The Uni-processor approach

The original engine model was designed around an
iSBC 86/12 Single Board Computer (without numeric
coprocessor) [1]. A small display unit was built as a
copy of the central instrument panel of the cockpit to
give feedback on the model's status [See Figure 2.4].
With a single processor, the software architecture is

What seems trivial in one sentence is in reality not! The
original engine model was designed around a single
processor modeling a single jet engine. The new
design will extend the model to three engines, and will
add an I/O subsystem to provide an improved human

SWITCHES

UP
I

~-r ~

3 --.

MACH
PRESSURE
ALTITUDE

LI EWFA2

EN2

2.2 The design problem

LEV1,2,3
-.

£j EWFA1

EN2

~~
EN2

FIGURE 2.3:

L~=

GRAPHIC DISPLAYS

ENGINE
MODEL
" ' - - - - -. . .

...,...----0
>
~

BARGRAPHS FOR
N1, EGT, EPR,
N2, FUEL FLOW
BCD DIGIT DISPLA Y
TOTAL FUEL
FUEL USED

THRUST ENGINES

""-----------'

TEMPERATURE

FIGURE 2.4:

THE ENGINE MODEL ARCHITECTURE FOR THE DC·10

5·132

AP-431
/'

-'\

ENGINE INIT
PANNEL_IN
LEV, SWITCHES
PANNEL OUT
BARGRAPHS
BCD DIGITS

COMMUNICATION
MESSAGES

'-1
I

I
I

--a:I.
..J

---.J

/'
BASE

BASE

INPUTS

OUTPUTS

ENGINE
MODEL #1

CPU #1

ENGINE
MODEL #1

I
./

CPU #3

CPU #2

FIGURE 2.5:

BASE

CPU #4

FUNCTIONAL PARTITIONING USING FOUR PROCESSORS

relatively simple: on every clock interrupt, the I/O unit
was activated to read input data (power level position,
on/off switches, etc.) and the engine model called three
times in sequence with the appropriate parameters.
Afterwards, some scaling took place to display the bar
graphs and fuel used digits [see Figure 2.4]. Using this
approach, the compute time depended on programming quality in the loop and therefore was optimized
using assembler coded routines. The complete computing cycle consists of: read the inputs, calculate the
engine model three times with the new state due to
input parameters, scale the results and output them to
the I/O unit.

Using the MULTmUS II technology [4] overcomes
the hurdles of designing a multiprocessing hardware
and is available off the shelf. The synchronization uses
messages, exchanged between the host and its partners
allowing a data exchange. This results in tbe architecture shown in Figure 2.5 where CPU #2, #3, #4 all have
a local implementation of the engine model. The host
or CPU #1 will handle all the coordination work and
some key functions for the transient model and display
scaling. The coupler board MBII/LNK-1 will handle
the input-output processing.

3.0 MULTIPROCESSOR SOFTWARE
DESIGN WITH iRMX II

2.4 The multiprocessor approach
To relieve the computational bottleneck and further
reduce the update time, additional processors are
needed. The basic question when using multiple
processors is how to partition the application (in this
case the modeling of all three DC-l 0 engines). For this
application, one processor for "each engine is appropriate because each engine model can be considered
as a closed system with well-known interaction points.
This results in a four-<:omputer system: one processor
must be a kind of "master" to coordinate the I/O and
simulate the flight simulator; the remaining three are
each modeling one engine of the DC-I0.
The data flow changes slightly compared to the one
processor approach. Because each processor is independent, each must be synchronized in some way.

The architecture chosen for the application is based on
a fully- configured iRMX II system as a host, complemented with three "EPROM"-based application
processors, one for each engine of the DC-lO. This
decision was made to minimize the amount of recoding
which would be necessary for the original engine
model. Software which was written a couple of years
ago can be reused without change. In the process, the
older iSBC 86/12 hardware will be upgraded to iSBC
286/100A boards for faster execution speed and Multibus II compatibility. Figure 3.1 shows the system
architecture of the new multiprocessing system.
Each of the four processors in this system has some
primary task to fulfill:

5-133

AP-431
EPROM BASED
APPLICATION PROCESSORS

DISKS
IRMX II HOST

INTERFACE

IRMX
APPLICATIONS
DEVELOPMENT
HI

PCI SERVER

DRIVERS

CF6·50C
ENGINE MODEL

F
PCI CLIENT
CCI CLIENT

6
M

TRANSPORT

TRANSPORT
-'--

FIGURE 3.1:

IPROTOCOL

HANDLER

I I~

IPSB

BASIC ARCHITECTURE OF THE SYSTEM

Host:

also be used as an on-target host for software
development.

This is the central control processor which runs a
complete real·time operating system. The iRMX II
operating system was configured with a human
interface, disk I/O subsystem ( PCI - Peripheral
Communications Interface ), and a message passing
,communications layer. The iRMX II console will
IRMX II REAL TIME

Applications Processors:
Each of the applications processors runs an EPROM
based program which contains the engine model
software. The only change which was required to

O.S.
BARGRAPHS

POWER LEVER

I VIDEO I

SWITCHES

FUELDIGrrs

APPLICATIONS
PROCESSORS

FIGURE 3.2:

THE APPLICATION SYSTEM ARCHITECTURE
5·134

AP-431

START CYCLE THROUGH
MESSAGE FROM MBII/LNK·1

END

JCYCLE

EVERY 50MSEC

TIME

PRE·
pROCESSING

I-

>
I0

CPU #2

0
!I)
!I)

I
I
I

~l
IDLE

....
III"""

IDLE

CPU #3

0
II:
CI.

COLLECT RESULTS FROM
APPS. PROCESSORS

POST·
PROCESSING

CPU #1

II:

SEND MESSAGES TO
APPS. PROCESSORS

CPU #4

.......

IDLE

I
I

IDLE

I
I
I
I
I

PARALLEL COMPUTING
TIME

FIGURE 3.3:

THE PROCESSOR ACTIVITY TIMING DIAGRAM

the original software was the addition of a message
passing communications interface. Since there is no
operating system on these boards, a low-level MPC
protocol handler is responsible for this function.

- Choice of the messages and their structure
- HOST startup sequence, iRMX II
related topics
- Use of the iRMX II communications layer
- "Application Processor" design

LNK-l:
3.2 Choosing a communications protocol

This board serves as a bridge to the low-cost I/O
subsystem and the master clock during simulation
time.
3.1 The 110 subsystem

As previously mentioned, the engine model also contains a display unit for control of the model. In order
to add this important function, a coupler board
manufactured by an independent MMG vendor
(MULTffiUS Manufacturers Group) was used as a
bridge to the I/O subsystem, as shown in Figure 3.2.
The I/O system interfaces to:
- A panel with the "on/off' switches for each en·
gine (anti-ice subsystem, etc.) as mentioned in
section 2.1.
- An NO converter to read and convert the position
of the throttles to a binary value.
- A video controller to display the state of the
engine as on the cockpit instruments.

The MULTIBUS II architecture defmes several types
of processor access to the parallel system bus [4.1]:
solicited message transfer, unsolicited message transfer, dual port memory access and interconnect address
access. Interconnect address space will be used for
configuration and initialization of the MULTIBUS II
system and will not be accessed following system
start-up. Dual-port memory as implemented on the
MBII/LNK-1 board is used in the design [3] an.d allows
use of unsolicited messages and memory transfer. The
transfer of information between the host and the application processors is expected to require high speed
transfers of numerous small blocks of data. For this,
message passing is ideal.
The decision as to what type of message transfer will
be used (solicited or unsolicited) will be based on how
much data has to be transferred among the processors.
As shown in Figure 2.5, there are basically three types
of messages to be transferred:

In the following sections we will discuss in detail the
various steps necessary to integrate the above design
into a real MULTffiUS II system:
5·135

- BASE:

This message contains the base
information, such as mach, pressure and altitude for the INLET

AP-431

- INPUTS: .

- OUTPUTS:

portion of the engine model [Figure 2.2]. This message is outbound from the host only.
This message contains the N2
variable (core speed) of the engine, as calculated from the
preprocessing in the Host. It also
contains the decoded switch infonnation from the panel of the
model "cockpit" for the "on/off'
switches of the subsystems, i.e.,
anti-ice, etc.
This message has much more
data to transfer back to the host
for th~ fmal processing: all main
computed data from the model
must be sent back to the host.

Once the structure of "what has to be transferred" is
defined, detailed analysis begins on the amount of data
to be transferred. In this application the number of
bytes to be transferred is relatively small, as follows:
BASE - 3 words; INPUTS - 7 words; OUTPUTS - 9
words. During the implementation phase it was quickly realized that it would be wise to define a flag word
to ease the debugging task. This flag word is an
overhead, but it allows identification of messages
being received for debugging.
The next choice to make is what kind of message:
unsolicited or solicited? Using solicited messages
means that a certain amount of data has to be sent
between the processors in order to be useful. In this
design, the use of a solicited message will mean only
overlIead and complexity in the software. Only a few
words need to be transferred. Therefore the choice is
to simplify and use unsolicited messages only. In a
case where a data transfer with more than 20 bytes is
needed, an unsolicited message may be sent twice.
This is faster than setting up an entire solicited transaction [4.3]. The big advantage is simplification of
application software and of the debugging task.

3.3 The final configuration
arid state cycle
Looking at the final configuration of the system as
shown in Figure 3.2, there will be a number of transfers
through the PSB for each simulation cycle. Each of
them will be started by the local processor sitting on
the EUROLOG local bus. This processor will read the
analog data, convert it to a binary value, read the switch
positions and pack it all in a MULTIBUS II message.
This will be sent to the host. The host will decode it
and do some pre-processing and send it to the appropriate application processor (or engine). After a
simulation step has been done locally, each of the

application processors will send the result back to the
host for encoding the display and some post-processing. Afterwards, the results will be sent back to the
MBII/LNK-l board using two unsolicited messages
for the display process because there are more than 20
bytes needed for this task. Therefore, a complete
simulation cycle will involve nine unsolicited transfers
among the various processors.

3.4 The cycle time analysis
The next task is to look at the activities of all processors
with respect to time. For this purpose, a "processor
activity timing" diagram, as shown in Figure 3.3, is set
up. The horizontal axis is time; the vertical has one
entry for each processor. During the work cycle, in this
case one simulation step based on the incoming unsolicited message from the MBII/LNK-l coupler
board, the main tasks of each of the processors is
estimated and shown with an arrow. Each outgoing or
incoming message is a transition vertical arrow to the
next processor and means the start or the end of an
activity.
Using this diagram, it is now possible to make a
quantitative analysis about the worldoad of each of the
processors. In this case we see that the CPU #2, #3 and
#4 are usually sitting idle waiting for messages. This
simply means that there is a lot of spare processing time
available. The diagram also shows that during some
time in the cycle there is true parallel processing happening, which confmns the design goal of shortening
the simulation calculation cycle. The compute time of
each of the application processors is usually bound to
the engine model calculation. This will be studied in
more detail in section 5.

3.5 The iRMX II host
As earlier mentioned,.there will be a human interface
(HI) job running under iRMX II which will monitor all
the simulation activities. This monitor program will
use the comm layer of iRMX II and be responsible for
the startup of the system.
One part of t~e monitor program will also be the preand post-processing for the engine model as mentioned
before. The startup sequence will include a board scan
in order to be able to locate the application processors
and define the necessary communications ports. The
monitor program will function as follows:
- Create the connections to the terminal
- Scan the backplane and check the BIST (Built-In
Self Test) status of each board
- If okay, then define the ports and sockets for the
iRMX communications layer
5-136

AP-431
HARDWARE
DEST. ADDRESS
SRC.
TYPE

TRANSPORT

ADDRESS

= OOH

NOT USED

PROTOCOL ID
TRANSMmON CNTL

DEST. PORT ID

MARKER TO
SYNC IIPPS

SOURCE PORT ID

DATA

USER DATA PART

IIPP~fC"'TION

1
1

MAX 18 aYTes
TRANSACTION ID

L ____ ~1

1
31

FIGURE 3.4:

TRANSACTION CNTL

'-.1_ _ _ _ _ _ _- '

+ ____
19 ....._ _ _ _ _....

THE iRMX II COMM·LAYER UNSOLICITED MESSAGE FORMAT

- Create a buffer pool to preallocate free memory
segments
- Create the. iRMX memory segments and release
them to the buffer pool
- Attach pool to port
- Ask for an amount of fuel in tons at the console
- Send the startup synchronization message to CPU
#2, #3 #4 and to the MBII/LNK -1 board
- Send the start command to the MBll/LNK-1
board and give it control
- Do every 50msec until no fuel available.
- Receive the message from the MBll/LNK1 board with the decoded power lever angle
and switches
- Make the preprocessing
- Send to each application processor the incoming data for a simulation step
- Collect the resulting messages
asynchronously (there might be a slower
board ... !)
- Mter having received all the results, make
, the post-processing
- Send the two result messages back to the
MBll/LNK-l board. This finishes the
"new state calculation" cycle.
- When no more fuel, stop everything and ask again
at the console for more fuel

of the PLjM 286 are used, especially the STRUCTURE DEFINITIONS which are very useful in this
kind of application programming. Portions of the code
are shown in Appendix B. Note that the transport
system calls are very easy to use.

4.0 THE APPLICATION PROCESSOR
DESIGN
The structure of the local software is, in principle,
simple, due to the task which must be performed and
can be split in two portions:
- A main program which will initialize the board
and the whole local software, and
- An interrupt handler to handle the incoming messages accordingly. In addition, the interrupt
handler calculates the new state of the engine and
contains the engine model which needs no
modification.
This leads to the design of several separate modules
with well-known tasks:

The coding of this monitor program is done in PLjM
286 using the iRMX II system calls. All the features
5-137

Init of the board upon cold reset,
(int. controller, MPC)
- INTERRUPT Activated on an MPC hardware
HANDLER: interrupt. Will initialize the engine model or calculate the next
state of the engine (so-calIed
simulation step).
- MAIN:

AP-431

4~I---~t-

r~~~~~~-~~~~~~~~

A ~

iRMXII

m
en

HOST

DST

NOT USED

TYPE

I
[

TRANSM.CTL

PROT.ID

DESTINATION PORT ID

Il.
~

MPC

SOURCE PORT 10
TRANSAC.CTL

, ,.

'
I

TO l'IESENO MESsAGE TO HOST

SRC

USER PROGRAMMING

TRANSAC.ID

EXOHANGE BRC AND DE$.T'

£J

EXCHANGE 1IORT 10'$
TO RISSEND MESSAGE
TOHOST

t__

DATA (0) ••••• DATA (17)
BYTE ARRAY

INITCF6
INPUTS

.-MPC_MESSAGE STRUCTURE

\
=11H

FIGURE 3.5:

- MPC-LOW

LEVEL
DRIVER:

I
I
j
I

___ JI

MARKER

I ENGINE

~
OUTPUTS

DATA PROCESSING ON THE MPC_DATA STRUCTURE

results. That is for the low-level hardware and
is absolutely logical.

Receive a message, transmit a
message, init the MPC, error
case.

The MPC low level driver routines can be directly
taken from the MPC User's Manual [4.2]. The
programming was done using 32 byte messages since
the structure of the application fits exactly in the unsolicited message format. However there are some
implications when receiving an iRMX II message sent
under the comm layer. The general format of the
message is shown in Figure 3.4. This explains that not
all available bytes can be used in the unsolicited message transfer since eight of them are used for the
transport protocol overhead, making the logical task
binding over the bus possible [4.3]. Therefore, the user
has to be careful when using the message formatted
under iRMX II and received locally without any
operating system software. Since only one single task
runs on the board (our interrupt handler), no port and
sockets are needed locally, but the host has a port and
a socket defined for accessing the application processor. To transmit the data back as described in the
design section above, the comm layer must "understand" what is coming back. The following operations
ensure this:

2. Exactly the same has to be done for the transport
part of the message structure. The DESTINATION_PORT_ID and the SOURCE_PORT_ID
have to be exchanged to allow the comm layer
software to receive the results correctly.
The second step seems trivial, but it took several hours
in front of the emulator to understand why the engine
variable Nl, a result of the simulation step, was always
the same value. We had not taken into account the
unsolicited message set up under iRMX II which has
the whole TRANSPORT PROTOCOL integrated.
Once this was discovered, we had no problems at all.
Therefore, all applications using no operating system,
kernel or executive locally, must have an "own"
protocol handler implemented. Main portions of the
documented code listings for total implementation of
the application processor can be found in Appendix C.
The "data processing" done flag in the MPC_MESSAGE data structure is shown in Figure 3.5. The
previously mentioned marker differentiates the kind of
message and is, in some sense, part of a "user application protocol". In this case it allows initialization of the
engine software or to make a simulation step.

1. The source and destination fields of the message
structure will have to be exchanged before
returning the message with the engine simulation
5-138

AP-431

MESSAGE INTERRUPT
FROMMPC
TIME IN MICROSECONDS

IDLE WAIT
FOR MPC_INT

INT. SERVICE
ROUTINE

IDLE

~TIME

I!OO to 1300 I]

RETURN

INTERRUPT
HANDLER

MPC_
TRANSMIT_MSG
ENGINE
MODEL

1,635-800

f==----- •••• ~
~

FIGURE 5.1:

SIMULATION STEP
VARIABLE I

THE APPLICATION PROCESSOR TIMING ANALYSIS

5.0 DEBUGGING AND PERFORMANCE
ANALYSIS
The debugging of the application for the local processor was done using the I2ICE 286 emulator. This
instrument allows a very efficient debugging, especially when using the macro facility to display data. Therefore a small library of macros was written to display
the incoming and outgoing messages. With this it was
possible to quickly locate the above mentioned problem of the missing ,TRANSPORT adaptation. The
whole application was debugged in the high speed
RAM of the emulator and afterwards relocated to be
EPROM resident. However, debugging a multiprocessor system is, by defmition, not simple because
of all the coordination involved. The debug session
around the application processor was based on the
following methodology:

Afterwards, an' analysis with the iPAT Performance
Analyzer was done to get more confidence about the
timing situation. Most impressive was the terrific
speed of the whole thing.
The iPAT performance analyzer offers many features
such as profile, coverage, usage, linkage mode, etc.[5].
In this kind of environment, the objective was to
measure how long the various elements of the cycle
are, so only the duration mode was of real use. Of first
interest was to check how much time is spent in a
routine and the latency from the MPC Interrupt
Hardware signal to the start of a particular routine.
Initially the cycle time of 50msec was chosen to have
enough spare time due to the use of the relatively slow
5MHz iSBC 86/12A. A time of about 15.5msec could
be achieved with the MULTIBUS I system.

Porting to the much faster iSBC 286/100A with 8MHz
speeds up the whole design. Depending on the switch
position for the engine subsystems [see Figures 2.3 and
2.4] the total cycle time is in the range of 1380 to 1490
RAM
microseconds. Figure 5.1 shows in detail the timing
- Loopback with same message to check the
situation of one cycle and how much time was spent in
MPC_TRANSMIT_MESSAGE routine
each of the routines. Note the overhead due to the
MULTIBUS II transport, and that the message passing
- When the loopback is okay, then add the full
handling is not very large. The MPC handling (receive
engine calculation and ... it runs!
A small log of a debug session with I2ICE 286 and the
and transmit the message) takes 180 microsec, and the
use of the predefined macros can be found in Appendix
swap for the transport adaptation takes 17 microsec,
D 1. It shows the big advantage of using symbolic
which means a total of around 200 microsec for the
"overhead". Therefore, the bottom line message is
debugging.
5-139
- Send a known message from the host
- Debug the MPC_RECEIVE_MESSAGE routine
step by step and get the known message to local

AP-431
very clear: There is enough spare time to add more
functions to the engine model. During the timing
analysis, 15 tons of "software fuel" was burned!

integrated and ported to the latest hardware technology.
- To adapt an existing MULTmUS I system to use
the benefits of the MULTIBUS II technology.
- To demonstrate the use of the iRMX II operating
system together with custom-made software and
'study its implications when the comm layer is
used.

6.0 SUMMARY AND CONCLUSIONS
The design and implementation of the engine simulation model has given the opportunity to discuss and study a couple of interesting problems around a MULTIBUS II application:

In addition, this application allowed discussion of ac-

- Given a task, how to partition an application to
use more than' one processor and assess the
problems around it.
- To demonstrate that the port of an existing
software written a couple of years ago can still be

tual implementation starting from the given problem
statement and ending with the final integration in a real
system using single board computers. The results
show the feasibility, including the important performance analysis.

5-140

AP-431

Appendix A
A.

Bibliography and related readings
1.

Francois Huguenin. Microcomputer Based Engine Model Used in Flight Simulation
Applications. AIAA Paper 81-0973, AIAA Flight Simulation Technologies Conference,
June 16-18, 1981, Long Beach, CA

F. Huguenin, P. Grepper. Four-Dimensional Helical Approach of Aircraft in an Air
Traffic Control Environment. AIAA Paper 79-1776R, Journal of Guidance and Control,
June 1981

Furrer+Gloor AG MULTIBUS II MMG
Furrer+Gloor Silbemstrasse 10
CH 8953 Dietikon ZH Switzerland
MBII/LNK-l Coupler Board User's Guide

Intel MULTIBUS II Documentation:
4.1 MULTffiUS II Specifications, order #146077C
4.2 MPC User's Manual, order #176526-001
4.3 MULTffiUS II Transport Specs, order #453508-001
4.4 iSBC 286/100A User's Manual, order #149093-001
4.5 iRMX II Nucleus User's Guide, order #461845-001
Nucleus Communication Services, section 12
5.
iPAT Analyst User's Guide, order #450583-002

5-141

AP-431

AppendixB
B.

Glossary of Terms
Application Terms:

T
p

m
HPX
EN2
EALT
EWFA

EVM

Temperature
Pressure
Mach
Horse Power Extraction
Engine Variable N2 calibrated
Engine Variable Altitude calibrated
Engine Variable Fuel Flow calibrated
Engine Variable Mach calibrated

MULTIBUS II Terms:
MPC

Message Passing Co-Processor (VLSI MULTIBUS II Interface)

Solicited Message Transfer

A data transfer through MULTffiUS II message space that
requires buffer nego,tiation. May be up to 16Mbytes long.

Unsolicited Message Transfer

Unsolicited messages arrive at a host unpredictably and can
have the effect of an interrupt. Message can have up to
20 bytes of user data.

Dual Port Memory access

A means of accessing shared memory between two processors.
Hardware arbitration is required.

Interconnect Address Access

Access to the MULTIBUS II interconnect address space for test
and/or configuration purposes.

Buffer Pool

A collection of memory buffers which are managed by the
iRMX II Operating System.

Transport Protocol

This is a generic term describing the function of the software
layer that implements the MULTIBUS II Transport Protocol
as dermed in the IEEE 1296 Specification.

5-142

AP-431
APPENDIXC

Documented portions of the iRMX II host monitor program
Note that all comments written in bold are added to the original listing portions.

~he

following code listing contains the most important parts
of the iRMX XX Host Monitor Program. Since this is a quite
large lisiting, it was choosen only to take out which is really
important.
B1. Declarations

word declarations make the interface to the exisiting
assembly coded routines. '

~hese

840
841
842
843
844
845
846

1
1
1
1
1
1
1

=
=
=
=
=
=
=

declare
declare
declare
declare
declare
declare
declare

std conditions word external:
state 1 word external:
state-2 word external:
state-3 word external:
result 1 word external:
result-2 word external:
result:3 word external:

~he following is an abstract of the definition for the messages
which are used between the processors in the system.

=
=
=

~his

847

1. standard conditions message from main to all
slaves

is the general unsolicited message structure to be used.
1

=
=
=

declare mpc message structure
( dest byte~
src byte,
type byte, not used byte, message_data (28) byte)
public:
-

~his

message will be used for synchronizing all processors
together.
848

=
=
=
=
=
=
=
=
=

declare std conditions msg structure
( header std conditions (4) byte,
transport (4) word,
std marker word,
evm-word,
ealt word,
,epO word,
eto word,
dummy std conditions (10) word) at
(@std:conditions):
5-143

Ap·431
These messaqes are to ~e used for the information transfer
the application processors.

~etween

Bote that the structures are overlayed to the word defined a lines
840 to 841 I
=
=

849

852

; 2.1 Enqine

=
=

declare state 1 msg structure
header state 1 (4) byte,
transport (4)" word,
.
messaqe_data (10) word) at (@state_l);

=
=

=
=
=
=

declare result 1 msq structure
( header-result 1 (4) byte,
transport (4)-word,
messaqe_data (10) word) at (@result_l);

; 3.1 Engine

5-144

Ap·431

The following three procedures are used for creating a port, and
to send and receive the messages under iRMX II control.
See also iRMX II system documentation.
1074

NEW$PORT: PROCEDURE (port$token$ptr,id,type);

1*******************************************1
1*

this procedure creates a port for access by iRMX II

*1
1075
1076
1077
1078

2
2
2
2

DECLARE
DECLARE
DECLARE
DECLARE

**
**
**
**

*1
1079
1081
10 82
1083
1084
1

3
3
3
3

1085

1086
1088
1089
1090
1091

2
3
3
3
3

1092

1093
1094

2
2

port$token$ptr POINTER;
id word;
type byte;
port$token based port$token$ptr token;

Create a new port: port$token$ptr is pointer
to port$token to be returned
id is: for data transport: port ID
for signal service: message ID
type is: port type

if type = data-port th$n do;
port$info.port$id = id;
port$info.type = type;
port$info.flags = 0;
port$token = rq$create$port
(queue$size,@port$info,@status);
end;
if type = signal-port then do;
msg$info.msg$id = id;
msg$info.type = type;
msg$info.flags = 0;
port$token
rq$create$port
(queue$size,@msg$info,@status);
end;
return;
end NEW$PORT;

5-145

Ap·431
••n4 • • ••••q. to the .PC

FORWARD$MSG: PROCEDURE (messaqe$pointer,port$id);
DECLARE messaqe$pointer POINTER;
DECLAREport$id BYTE;

1095
1096
1097

1098

1099

1100

transaction$id = rq$send(
own$port$tok,sockets(port$id),
messaqe$pointer, NIL, 0, 0,
@status);

1101

call

1102

count$out

1103
1104

2
2

END FORWARD$MSG;

2
2

DECLARE
transaction$id
status

WORD,
WORD;

call no$exc$mode;

1* set Exception Mode

full$~xc$mode;.

= count$out+1;

RETURN;

5·146

to 0 (No RMX Action)

1* Reset Exception
Handlinq *1
1* Update Counter for
messaqes sent *1

AP·431

r.a.ive ••••••g. fro. the KPC
WAIT$FOR$MSG: PROCEDURE (buffer$ptr) WORD:

1105

1106

DECLARE buffer$ptr pointer:

1107

DECLARE buffer$ptr_origin POINTER:

1108

DECLARE
info_buf

STRUCTURE (
flags
status
transaction$id
length
forward$port
socket
message(20)
reserve (4)

status

WORD,
WORD,
WORD,
DWORD,
TOKEN,
DWORD,
BYTE,
BYTE) ,

WORD:

1* set Exception Mode to 0
(No RMX Action) *1

1109

call no$exc$mode:

1110

buffer$ptr_origin = rq$receive(
own$port$tok, notimeout,
@info_buf, @status):

1111

call full$exc$mode:

1* Reset Exception
Handling*1

1112
1113

1* Update Counter for
Messages sent *1

2
2

count$in = count$in + 1:
socket = info buf.socket:

1*
**
**
**
**

We expect just a Control Message ==>
Copy contents of control message to buffer
provided by paramter buffer$ptr and return
sending host ID.

*1
1114
1115

2
2

1116

call movb(@info buf.message,buffer$ptr,20):
return socket$def.host$id:
END WAIT$FOR$MSG:

5-147

Ap·431
~he followinq oode section is the DO UNTIL BO_FUEL loop
with the iRKX II system calls used to transfer the data to and
receive them ~ack from the Appliaction processors.

1****************************************************************1
1*
*1
1* Wait for state in Messaqe from LINK
*1
1* copy MSG to Buffer =>
*1
1*
SWITCH DECODE,LEVER TO 2,N2 TRANSIENT *1
1* Send state_i Messaqe to Engine-simulators- *1
1* wait for Simulators having calculated ==>
*1
1*
' EGT FILTER, SKAL BARGRAPHS,SKAL DIGITS
*1
1* Send display- Message to Link
*1
1*
*1
1****************************************************************1
1366

DO WHILE nofuel=OJ

~he state_messaqe contains the data from the 1/0 s~system.
When received, one simulation step can ~e processed.

1* wait for STATE_IN Message, then Copy *1
1367

id = WAIT$FOR$MSG(@state_in_msg.state_in)i

Kake the preprocessing.
1368
1369
1370

3
3
3

CALL SWITCH DECODEi
CALL \LEVER TO N2 J
CALL N2_TRANSIENTi

set the marker word to 10K prior to send the data.
1371

1372

1373

1373
1) J

call ·movb
(@(10H),@state_1_msg.message_data,1)i
call movb
(@(10H),@state_2_msg.message_data, 1lJ
call movb
(@(10H),@state_3_msg.message_data, 1) i

call movb (@(10H), @state_3_msg.message_data,

5-148

AP·431
1374

1375

1376

call forward$msg(
@state 1 msg.message data,engine 1);
call forward$msg( @state_2_msg.message_data,engine_2);
call forward$msg ("
@state_3_msg.message_data,engine_3);

1*
**
**
**
**
**
**
*1

wait for all three having terminated:
Use logical variables all$done,done$1
f done$2,done$3.
When a Message arrives, copy it to local
buffers.

1377

all$done,done$1,done$2,done$3 = FALSE;

1378

DO WHILE NOT all$done;

1379

= WAIT$FOR$MSG(@intermediate);

1*
**

Message arrived: set corresponnding done

** flag and copy buffer
*1

1380
1382
1383

4
5
5

1384
1385
1387
1388

5
4
5
5

1389

1390
1392
1393

1394

1395
1396

5
5

if id = host$ids(engine 1) then do;
done$l = true;
call movb(@intermediate,
@result_1_msg.message_data,28);
end;
if id = host$ids(engine 2) then do;
done$2 = true;
call movb(@intermediate,
@result_2_msg.message_data,28);
end;
if id = host$ids(engine 3) then do;
done$3 = true;
call movb(@intermediate,
@result_3_msg.message_data,28);
end;
all$done = done$l AND done$2 AND done$3;
END;

Hake the postprocessing.
1397
1398
1399

3
3
3

CALL EGT FILTER;
CALL SKAI; BARGRAPHS;
CALL SKAL=DIGITS;
5-149

Ap·431

send results to MBII/LNK-1 Board with two
consecutive unsolicited messages

*/
set the marker word to 44H and 45H for identification
inside the KBII/LNK-1 Baord.
1400

1401

call movb (@(44H),
@display_on_line_msg_1.display_on_line,1);
call movb (@(45H),
@display_on_line_msg_2.display_on_line,1);

Send the two conscutive messages to the KBII/LNK-1 board.
1402

CALL FORWARD$MSG (

1403

CALL

@display_on_line_msg_1.display_on_line,
link_1) ;
FORWARD$MSG(
@display on line msg 2.display on line,
. - - lInk_1);

/*
** Update Message Counter for display on the
** console
*/
1404
1405
1406
1407

3
3
3
3

status - put$char(@pos$in,fb);
status = put$ddec(count$in,fb);
status = put$char(@(alloff,O),fb):
call put$line(nolf):

1408
1409
1410
1411

3
3
3
3

status = put$char(@pos$out,fb):
status = put$ddec(count$out,fb);
status = put$char(@(alloff,O),fb):
call put$line(nolf);

1412
1413
1414
1416
1417
1418
1419
1420
1421
1422
1423

3
3

4
4
4
4
4
4
4
3

ttime.systime=O;
call dq$decode$time(@ttime,@status);
if last$sec <> ttime.time(7) then do:
call movb(@pos$time,@outbuff,12):
call movb(@ttime.time,@outbuff(12),8);
call movb(@(alloff),@outbuff(20),4):
out$buff(24)=0:
call disp(@out$buff);
last$sec =.ttime.time(7):
end:
END:

5-150

AP-431

APPENDIXD
D.

Documented code listing ofthe application software based in EPROM

This appendix contains most of the listings generated for the application processor EPROM
resident software:
MAINOS
MPCDR3
C286I6
CF6SaL

: main module for cold start
: low-level MPC driver
: interrupt handling routine
: engine model module

Note also the last page of the LOCATE MAP which gives an idea on how much memory was
needed for this application.
IRtlX 8h 81118h/87/BB/IBh MACRO A9SEtlBLER V2.111 ASSEMBLY OF tlODULE tlAIN_tlODULE_2Bh
OBJECT tlODULE PLACED IN MAINIII5.0BJ
ASSEMBLER INVDfI'ED BY.

Lac

OBJ

ILANG; .. amB6 HAIN05.AB6 DEBUG SYMBOLS TYPE

LINE

SOURCE
name

main_module_28b

2
3

CF6-~IZIC

PROJECT

4
5
h

7
B
9

Hul Ucomputer

vl.1a fh add reset. not complete on entry point
vl.1II fh add in it. of aNfaald • • fuelu.ad

1118.1111.87
1113.IIII.B7
21.0B.81
e4.0B.87
1113. 1118. B7

v2.lIfh

change interrupt structure

vl.1fh

change e"t.rnal .eQment.

03. 0B. 87

vl.8fh

iniUal start up module

v2.1 eS/Sem DCW2 hats addr •• '!! ph:_cntUI

1111
II
12

IIII11CIII
0eC2

111I11III111
111111111111 (32
????????
J

1111118111 111111I11III111111I11III
III111B4 1II111111111111111111111
IIIIIIBB I11III111111111111111111
1111118C I11III111111111111111111
1111119111 111111111111111111111111
111111941111111110111111111111
""98 00000020
G!l1ZI9C m0001Z10G!10

IS
Ih
17
IB
19
2111
21
22
23
24
2S
2h
27
28 +1
29
3111
31
32
33
34
3S
3h
37
38
39
4111
41
42
43
44
4S
4b
47
48
49
50
51

This module cantains the cold reset start up of the sbc:296/101iM

and the interrupt proces.ing routine.

note that 1111 writt.n in CAPITAL is oriQinal software written
end of 1919, early 1990 I
all other is modification done to port thl!! oriQinal application
to Multibu. II

*Mogen
I 'nterrupt controller PIC

pic_cnU"
pic:_cnt11

equ
aqu

int.,point ..,.s

•• Qment at III

tVP __M

D'9

com"and part 1
command part 2

IIIh

dupe?)

• ma.te,. pic of iSBC 2B6/UIIiJA

type_32

typf!'_38
typlE!_19

dd
dd
dd
dd
dd
dd
dd
dd

int-pointers

end.

type_33
type_34
type_3S

type_36
type_31

53
54
55
5h
57
SB

Iclh
1IIc2h

f
I

III
III

a
III

i , III
i, I
ir 2 . . . . .0. int.rrupt
i r 3 i PSD tII• • • •O. .r,.or

III

E"at ..,.nal variables needed fo,. initialization
first time after reset

5-151

Ap·431
LCC

SOURCE

LINE

OBJ

59
60
61

62
63
64

EFG I 0'
eKlrrl
limtrn
eKtrn

SEGMENT COMMON
ewfaoldlwcrd
efuelusedrward

E"FG I 0

ENDS

deltat;word

65
66
67

.eject

_III ClIIIIII
???.,

69
70

STAC~SEB

STACKTOP

72.

STACV.SEG

74
7S
'76

iodatseg

SEGMENT public

iodatspg

ENDS

SEGMENT STACK
100 DUP'~I

,ALLOCATE 100 WORDS FOR

WORD

J OFFSET ADDRESS OF THE lOS

STAC~

I
0111CB

LABEL

ENDS

77
7B
79

; twa

e~tprnal

routine9

Bill

BI
B2
B3
B4
BS

eHtrn

mpC_lnlt:far

flY trn

mpC_l nterrupt I far

EFGCOD

B7
88
89
90
91
92

94
95

!lI0Be

96
97
9B

99
100
101
102

000050
0001 9A0C!J00----

10B
109
110
111
112
113
114
115
11.
117

0006 8020
,0008 E6C0
1i'100A 58

0009 FB
000C CF

SEGMENT PUBL I C
• GIVE ASSEMBLER I NIT I AL REG I STER TO SEGMENT CORRESPONDENCE

ASSUME

CS. EFGCOD,

interrupt_routine

OS:

IODATSE'G.

ES3 EFSIO.

S9. STACKSEB

prot:

This Interrupt routine will be activated by the MINT Ilnl!
of the MPC when the MPC has recei ved a message
This routtne call the lnterrupt handler wrItten in PLMBb
whIch Will calculate a new state of the engIne based on the
Incoming message. Aftl"rward!l the ... ~g,ult message WIll be forllM!d
; and send back to t.he host.

11113
104
105
106
107

I lnlttah:ation of the mpc
mpc interrupt routine
for handling 110 and engine

pU!lh
call

mpC_lnterrupt

• EOI handIlng for t.he 82S9A ControllE'r
moy

out
pop

al,2llJh
pic_cnt.lllJ.al

• non specific eoi
t wrt te to ocw2

stt

iret.

Int.errupt_routlne

enable interrupt.s
ret.urn from i "terrupt.

endp

liB
119
120
121
IZ:&:!

C1I01Z1D

start I
7.reset_i nterconnect

• RSTNC* Fli t reset t nst de 87:51
Mlcrocontroller

13:3
134

0032 8B----

01i!135 BEDS
21037 88----

003A BEC0
1Z103C 88----

0C!13F SEDI!J

1Z111J41 BCCB00

13:5
144
145
146
147
14B
149
15111

set up segmpnt reogi !lters of cpu

maY

MOV
MeV

151

MOV

152

MOV
MOV

15'J

154
155
IS6
157

AX.IODATSEG
ILOAD SEGMENT REG
DS,AX
,CS IS LOADED AUTOMATICALY BY RESET
AX, EFGIO
ES,AX
AX. STAC~SEG
SS,AX
SP.OFFSET 9TACKTOP ;SET SP TO T09

cpu now re.ady for work for the engine model
but first initialize the mpc

158

159
Ibl1l
Ib1

I11III49 26C71116111111111111111111111111 E
121050 26C706HHH011 E
111057 26C70601!J005046 E

1b2
Ib3
1b4
IbS
Ibb
1b7
IbB

0044 9AIt08B----

IIIIII:5E BAC000

111061 9017

169
17111
171
172

1 then set to zero fuel yariables

moY

••• ewfaald,"
eSlefuelused,B
e!lIdel tat. 180mB

• then imtialize master
moY

dV..plc_cntUI
al,000U!J1l1b

5-152

PI~

uf iSBC 2B6/U!l0A

, lewl
1 edge truJv.,..d, .lngle ",ode, c_ll

AP·431
LOC
1111116~

0064
C!l067
0Ab9
IZU!l6A

OBJ
EE
IlAC2ne
9020
EE
8010

1111I6C EE
006D BIIIFB
0116F EE

111117111 FB
II1II71 9111
II1II729111
011173 90

LINE
113
174
175
176
177
17B
179
IBII
lBl
lB2
193
lB4
IB5
IB6
lD7
lBB
ID.
190
191

SOURCE

out
may
aut

aut
maY
aut

dx,al
dK,pic_cntll
al,01Z11001!1021b

dx,al
al,BB011101b

dH,a.
al,0fbh

• address

icw2
•I ba!Je::otype

32 (Blllhl

special fully nested modll, buffered
master, normal eo!, Bb mode
J enable only i,.2 meBsaQI! interrupt.

d",.l

• and finally enable cpu interrupts

uti
idlul

nap
nap
nap

• do Moth! nQ but wat t for m•••• ge

5-153

Ap·431
iRHX 86 PL/I1-B6 V2.1 COMPILATION OF MODULE C2Bo_INT_HANDLER
OBJECT MODULE PLACED IN C286J6.0BJ
COMPILER INvarED ~VI
:LANG;plm86 C2B616.P86 DEBUG SYMBOLS LARGE TVF'E

c2S0_"nt_handlerl

dot

main contr"ol inlE"rrupt handler for the local engine
control. Will check for type of meoBsagE!', start up the model
and carry out onE!' gimulaliorl step at a time baRed on

inc:ommlng meossagEPs •

history
c:'Bbib
c~061 b

vl.l

c:286i5

vl.11J

c:i!8614
c:28614
c:286,4
c::i!8614
c28614

vl.3
vl.22
vl.2
vl.l
vl.B
v1.1
vl.S

v1.C!I

c~86i3

c2B61J
c:28612
c2B6il

2
3
4
S
b

vl.S

1114.1119.87

remae!!' eorrcu· "or std conditions
t'leta,. mpc_mellJSo.lge o;truc:turp ",ft~r transmit
and .. .,ter receiving for neNt time
ramo". error in adressing mpc_messsage !ltruc
normal made of opo; for i~ic:e test
engine and movb relloved for t.est
eMc:hange source'dest for retransmi t
chang£" dato.\ struture.
change for !ltd_condition. _!l,age
add o;ource id for the main processor

04.08 .. 87
04.08.87
0'3.08.87

remove l ypP5
initial verBion

mS.UJ.87
1Z11.UlI.S?

03.10.87
03.10.B7
21.08.87
11.08.87
IlIb.SS.S7
06.0B.87

add destlnat.lon id

vi."

declare
declare
dec.l.rEO
declare
dpC"'lare

std_conditlons word e~tern"l.
inputa word external I
outputR word external,
byte_dummy
byte,
word_dummy
word;

declare mpc_ml!.aage st.ructure
( dest
byta,
"
arc
byte,
type
byte,
not_used
byte,
prot_id
byte,
transm_ctr
byte,
destJ)ort_id word,
source..,port_, d word.
trans.ct_id
byte.
transact_ct,. byte,
"'P5a"ge_data (20) byte) public,

4 Byte Hardware-Header

'* a Byte RMX-Headar *'
'*

declare

20 Byte Utler-Data

"deN byte,

Declaration of external procedur.s

******U**'**"*'*'

engines procedure axternAI J
end engine,

II
1~

I
2

trlpc_recl'!' va_message I procedure -.xternal.
end "'pc_rae.1 ve_mpssaqe;

13
14

I
2

mpc_transmi t_lIIeasage= procedure external
pnd trlpc_transmi t_message,

,. St.ar t Mpr.-lnlerrupt-"'rocedure (MINT-Signal) . . . . . . . . . . 1
mpc_interruptl procedurp

publicI

fir"t empty the MPC FIFO Into ",pc_message 5tructure

if mpc_message. message_data (0). 12I1h

then
18
19

2
3

28
21
22

4
4

do,

we had a engine in:it mes.age . ,

call mo"b (Ii)mpc_message. mflssage_dat" (II) ,.i)std_condi tions, 20),
, . clear _thll IIIpc_message data structure after ret:p.ivfI
do index· I1J to 19;
mpc_message. m.....age_data (i ndex) - C!ll1Jhl
entl;
end.

5-154

Ap·431
24

1
2~

::;

elo:;"

norm. 1 message for one simulation 'Step ./

f mpc_message. message_data (0) do.

call mOllb

llZlh then

(~pc:_me9aagp..me.sage_data(0) .~ln"utB,=0)

,tSE"t

I'
30
31
32

33
34

::;

::;8
39

4
4
3

- mpc_message.de.tJ'0rt._id.
,. mpc_message. sDurcftJ)ort._i

mpc_messag •• "iource""pDrt_id • word_dummy,

"
"

transm! t: regu! ts back to host.

/. clear thp mpc_message data structure after transmit
do index'" 121 to 191
mpc_ml"ssagE'. messaoe_data Cindeu)" 1210h.

end:
endl

else
do,

ror reoault.'

carl/arming to the Comm Layer of iRMX lUI

ward_dummy
mpc_massage. deostJ)ort_ld

3
3

"'~I~pr

Transport Protocol adju'itment. to be

byte_dummy
.... mpc_massage.dest.
mpc_message. deBt • mpc_mestlage. sre:..
mpc_me"isage.src
- byte_dummy I

3
3

I . onp. "imulatlon oat!?!! 11

1& Error-proces51ngl Error in message_dataCII!J)
caslE! not Implemented in this version
end.

end mpc_i nterrupt I

end,

5-155

Ap·431
tRIIX 86 _/87/88/186 MACRO ASSEMBLER V2.11 ASSEMBLV OF I10DULE MPC_HANDLER.JIODULE
OB~ECT MODULE PLACED IN MPCDR3.D~
ASSEMBLER INVOKED BV,
tLANGlaslnB6 MPCDR3.A96 DEBUG SYMBOLS TVPE

LDC

DBJ

LINE

SOURCE

2
~

mpcdr"'3

vl.S CG/Se,. 21.8.97

r"ef.r-ence to mpc_lftes••ge via • BeQ ~

4
3
6
7
9
9
III

mpcdr3

vl.4 fh 07.1118.87

IIpcdr'S
mpcdr'3
IIIpcdr3
mpcdr:i:

vl.3
vl.l
vl.a
vl.l

chang_ ds regi ster far
ch • .nI~. cl to etc far loop
rotate message .. d
add mctl regi _tel"

mpc:dr2

vl.1II fh 03.118.97

mpcdrt

vl.0 fh 22.06.87

add mpc_init
add mpc cont,.ol

mpr:drm

vi." fh 19.1!16.Ab

nr-t o]tnlll v""'''inn

12
13
14
13
16
17
19
19
211
21
22
~3

fh
fh
fh
fh

!/J6.118.S7
06.08.97
05.09.97
1214.08.87

f.,.

make proc:edurAs fa,. type

Thi. module cont"ins the law levPI MPC h"",II!n; routine. needp.d
for this application. Several simplifications are assumed.
the rl!"ceive and t,.an •• lt mp9sage rouUnes are wort-Ing on 32 bytp
messages only. No length pro; ... allHning assumed. Further, the error
hand!ln.., 1"1 not implernpnted in this first rltlease of the lnw level
d ... iver.
all three routines are" direct implementation of the work
flow described In the rlpC user'. Guida and are coded 1n the large
modllPl for compatibility with the engine model and the plmS6
interrupt proce •• ing.

:4
23
~6

28 ....
-I
-I
-I
-I

1111111
III1IC
11111111

-I
-I

0000

-I
-I
-I
-I
-I
-I
-I
-I
-I
-I

III1I1C
111114
1111119

0020
111124
1111211
0024

-I

1111114

-I
-I
-I
-I
=1

1111311

011134
01131

00'3C

-I
-I
-I
-I

l1li111
1111114
IIIIB3

-I

-I
-I

011180
1111l1li
1111183

-I
-I

-I
-I
-I

-I

29
311
31
32
33
34
35
~.

37
3B
39
411
41
42
43
44
45
4.
47
4B
49
511
31
32
33
34
33
36
37
3B
59
611
61
62
63
64
65
66
67
loB
69
711
71

""clude (mpcaB6.def)
1 i 10 port addresse9 of MPC
mdata
IIstat
mrst
mct!

eou
eou
eou
eou
equ
equ
equ

IlIh
Ich
IIBh
IIl1h
lI
z. rABLIB.LIB 5
13/0
137
139
139
140
141

: TF' [FBWERt'NUt1ME.R

E'NGN

OUTPUTS EOU

THIS WORD
dw

1 dup (lZI)

F101Q-word c,"ly

I1Im00
)

004C 0000
004E 1i!I1!I00
005111 0IZJa0

0052

012152 00
011153 B0
0054 011101!1

121056 CiWICZIIZI

0058 0000
meSA 0000
B0se 001Z1m

005E 1!I1!J00

1210b0 0000
0062 0000

142
143
144
145
14/0
147
149
149
150
151
152
153
154
155
15/0
157
159

EWFAOLD DW

DEL TAT

DW
EFUELUSED
ENl
EQU
EN1L
EN1H
EN1A

08
DB

UW
OW
OW
DW
OW

EFR
EGT
EWFA
EFNA

EFUELUSEOI
EFIIELUSE02
EFUELUSED3

o
o

EFGto

S{\HPLING TIME
FUEL USED

II
THIS WORD

REFEF.D FAN SPEEDD

Nt DIGITAL DSIPLAV

ENG.f"'RESSURE RATIO
EXHAUST GAS TEMP.
FUEL-FLOW
THRUST

o
II
d ..
d ..
d ..

159

1/00
1/01

1 "OLD VALUE FUEL FLOW

ENDS

162 +1

0 _ Cl0111
?.,.,?

163
1/04
16S
166

9TACt
I

put absolute value he ....
• due to EPROM ve... luan

IN IDLE BYPASS MODEL CALCULATION
I BASED ON A SIMPLIFICATION A

SSUPTION
1110U EBUI9GI

0019
001C
B01F
011122
0025

EBlall00
E811101110
E91ltC!l0a
E80000
E8111000

E'
E
E
E
E

0028 IF
1110291117
0I!J2A CB

227
228
229
230
231
2'2
2'3
2'34
235
236
237
238
239
240
241

; NORMAL NON lOLl:: MODE a CALCULATE A NEW STATE OF
,

NORMnL21

242
243

ENGINE

SUBSYSTEMS

CALL
CALL
CALL
CALL
CALL

EPRSVS
NISVS
EWFASVS
EGTSYS
FNASVS

POP
POP
RET

OS
ES

ENDP

244

••••••• u ••••
*u* END
ENGlNE •

243

246
247
248
249

111028

Ef'R
Nl
FUEL FLOW
EST
THRUST

IDLEBYPASS

".,a •• unu •••

PRCe

230
002850
IIIIIJ2C 26C711J6l61!11!11!11!110
0033
011J36
0039
1IJ0JC

E8000111
E811111J011J
E8011J00
EBIIl0!!111l

!!I0lF 26BF1Il63611JG1
0044 C3

E
E
E
E

231
232
253
254
~5~

215b
257
258
259

260
261
2112

AX
EN2,4096

,SAVE

CALL
CALL
CALL
CALL

_PRSYS
EWFASVS
EGTSVS
FNASYS

INISYS SIMPLIFICATION ASSUMPTJON

POP
RET

EN2

,RECALL EN2

IDLEBVPASS

ENDP

263
264

265
~66
~67

EFGCOD

EN~

PUSH
MOV

ENOS
END

• 5-161

Tf~E

F.NGINE

AP·431
MODULE •

FUELFLOW_SVBTEM

BASE

OFFSET TYPE SYMBOL

BASE

OFFSET TVPE SYMBOL

BASE

OFFSET TYPE SYMflOL

GlGl41H
ilIZI41H
0041H
0A41H

GlMaH
IZIBZSH
0A29H

BYM
SVM
SVM

0A33H

AI'ICEH

BY'"'

GlGI41H
0041H
011J41H
1Z1041H

GlGI41H
0041H
0041H
00411-1

0C08H
0A0bM
IZIAA8H
0"80H

CONTI
EWF'AC
NEG2
TeAl

MEMORY MAP OF MODULE

MDDlLE START
Af"GMENT MAP

flTART

ADDRE~S

STOP

PI\RAGRAPH "" 0041 H

OFFSET •

U·NGTtt AL I GN NAME

001!19FH

0mAI!JH

INT _POINTE'RS

00::?0BH

00200H

001Z10H
IlI1Z1b4H
019Q)H
0003H
0C12H
00BIH

""'SEG
EFGIO

00~6'3"1

0111::'7011
004001-1

00'JFFH
00402H
010::1H
01091Z1H

A041111H
01030H
BIBeeH

CONT2
EWF'ASVS
START

TFAI

MAIN_MODULE_~B6

GlGlGlGl0U

0":::'0I21H

"'leaH
09CIZIH
0AbCH

BV'"
SYM
BVI1
SVM

G
G
G

024~FH

I 380H

1(I~440H

0~51EH

C'J0t)f'H

G
G
W

0~S20H

GI~543H

0024H

02:544H
0254CH

0:O:S4BH
B254CH

000S.,

W
W

0000H

000DH

OVERLAY

CLASS

SH\C~

SEG
IODATSEG

EFGCOD

CODE
EFGDAT
C:;:96 INT _HANDL
-ER_COOE
C~Bb_INT _",ANDL
-ER_DATA
STACt
MEMORY

conE
DATA
BTACt
MEMORY

5-162J

SVM
SVM
SVM
SYM

ENOf

NEGI
TACP
THPJ(

AP-431

APPENDIXE
El. I2ICE debug session sample
This shows a sample debug session using symbolic debugging with I2ICE 286.

Pirst include all user pre-defined macros for this application

*
*include

cf6.mac

.td def is a aacro for .etting the standard values for local
engIne test
*define proc std def = do
.*evm=Ot
.*epO=20783t
.*etO=303t
.*deltat=l8000t
.*end

* msg is a macro for displaying the content of the HPC MESSAGE
mpc
STRUCTURE
*define proc mpc_msg = do
.*write ' ,
.*write ' dest
=
mpc_message.dest
.*write ' src
= " mpc_message.src
.*write ' type
=' mpc_message.type
.*write ' not_used = , mpc_message.not_used
.*write • transport message passing part '
.*write ' protocol_id
=' byte .mpc_message.prot_id
.*write • transmit ion cntl = " byte .mpc message.transm ctr
.*write • dest port_id=' word .mpc=message.dest-port_id
.*write ' src-port_id
" word .mpc_message.sourc-port_id
.*write ' transaction_id
'byte .mpc_message.transact_id
.*write • transaction_cntl
byte .mpc_message.transact_ctr
.*write ' data field = •
.*word .mpc_message+12t length lOt
.*end

macro s makes a single step
*define proc s = do
.*istep
.*ASM $
.*end

*
aacro input cf& displays the inputs data structure
before and engine simulation step

5-163

Ap·431
*define
.*write
.*write
.*write
.*write
.*write
.*write
.*write
.*write
.*write
.*write
.*end

proc input cf6 = do
'flag word-=',:cf6 engine local.inputs
'EN2 ~',:cf6 engine local:EN2
'~N2L =',:cf6_engine_local.EN2L
'EN2H =',:cf6 engine local.EN2H
'EACPSW ~',:cf6 engine local.EACPSW
'EHPXSW =',:cf6=engine=local.EHPXSW
'EFAISW =',:cf6 engine local.EFAISW
'ECAISW =',:cf6-engine-local.ECAISW
'EBLESW =',:cf6-engine-local.EBLESW
'EREVSW =',:cf6=engine=local.EREVSW

*
macro output cf6 displays the outputs data structure
as a result of a simulation step

*
*define
proc output cf6 = do
.*write 'flag_word ~',:cf6_engine_local.outputs
.*write 'EWFAOLD =',:cf6_engine_local.EWFAOLD
.*write 'DELTAT =',:cf6_engine_local.DELTAT
.*write 'EFUELUSED =',:cf6 engine local.EFUELUSED
.*write-'ENl =i,:cf6 engine local.ENl
.*write 'EN1L =',:cf6 engine local.EN1L
.*write 'EN1H =',:cf6-engine-local.EN1H
.*write 'EN1A =',:cf6-engine-local.ENlA
.*write 'EPR =',:cf6 engine local.EPR
.*write 'EGT =',:cf6-engine-local.EGT
.*write 'EWFA =',:cf6 engine local.EWFA
.*write 'EFNA =',:cf6-engine-local.EFNA
.*end
-*
engines tate decode the full state of variables of the
engine model at any time
*DEFINE proc ENGINESTATE = do
.*BASE=decimal
.*WRITE 'Nl = ',EN1, , non scaled :',(enla/1696t)*2ot
.*WRITE 'EGT = ',EGT, , non scaled :',egt
.*WRITE 'EPR = ',EPR, , non scaled :',epr/3200t
.*WRITE 'N2 = ',EN2, , non scaled :',(en2/256t)*5t
.*WRITE 'FF = , , EWFA,' non scaled :', ewfa
.*WRITE 'FNA = ',EFNA,' non scaled :',(efna/378t)*lOoot
• *WRITE 'INLET ::::
EPO=',EPO,' ETO= ',ETO,' MACH = ',EVM
.*write ' ,
.*write ' switch status '
.*write 'acp =',EACPSW,' hpx =',EHPXSW,' fai =',EFAISW
.*write 'cai =',ECAISW,' ble =, , EBLESW,' reverse = " EREVSW
.*write ' fuel used for this step = ',efuelused
.*BASE=Hex
• * end
5-164

Ap·431
macro setn2 sets the en2 variable for a local test

*
*DEFINE
proc SETN2 = do
.*word .mpc_message+14t = %0
.*end
*
macro rst allows the reset not complete sequence to take place
see also main text
*define proc rst = do
.*reset regs
.*unithold
.*port(34h)=Of8h
.*port(31h)=Of8h
.*port(30h)=Oa4h
.*port(3ch)=000h
.*go from Offff:O forever
.*end

*
make a break at the end of the simulation step
*go til :c286 int handler#43
*Probe 0 stopped at :C286 INT HANDLER#41 + 1H because of execute
break
Clip~= F3
Trace Buffer Overflow
see what data are around after a full engine simulation step
using i2ice macros
incoming data packed in mpc message structure as before
engine simulation step donemessage strucuture as received by the HPC

dest
01
src
= 05
type
= 00
not used
00
transport message passing part
protocol id
02
transmitIon cntl
00
dest port idooio
srcyort_Id
= 0800
transaction id
00
transaction-cntl = 00
data field 0256:000EH 0010 14EO 0000 0001 0001 0000 0000 0000 0000 0000

5-165

Ap·431
input data
*input cf6
flag word = 0010
EN2 ;; 14EO
EN2L = EO
EN2H = 14
EACPSW = 0000
EHPXSW = 0001
EFAISW
0001
ECAISW = 0000
EBLESW = 0000
EREVSW = 0000
II::

output data

*
*output
cf6
flag word = 0000
EWFAOLD = 1411
DELTAT = 29C7
EFUELUSED = 001B
EN1 = 2CDB
EN1L = DB
EN1H = 2C
EN1A = 2605
EPR = 5346
EGT = 035B
EWFA = 5047
EFNA = 4BOA
full engine state

**enginestate
N1 =
11483
non scaled : 100
EGT = 859
non scaled : 859
EPR = 21318
non scaled : 6
N2 =
5344
non scaled : 100
FF =
20551
non scaled : 20551
FNA = 19210
non scaled : 50000
INLET ::::
EPO= 20783 ETO= 303
switch status
acp = 0 hpx = 1 fai = 1
cai = 0 ble = 0 reverse = 0
fuel used for this step = 27

5-166

MACH

= o

AP·431

continue the simulation

* forever
*go
?
?
?

/* end of this debug session */

5-167

AP-431

APPENDIXE
E2. iPAT analysis protocol

This shows the sample iPAT analysis session done to assess the perfonnance of the application
processor design.

* -------ipat analysis
*/*

-------*/

* the time base to 200 nsec in general
set

note that we are online with the simulation running
*qo
?ptimebase

200ns

define a macro for analysing
?

?define proc measure = do
.?pat init duration %0
.?histo=false
.?pat display
.?end
.
?

me.asure the time spendt in the mpc_receive_message routine
?measure (:mpc_handler_module.mpc_receive_messaqe)
Mode: DURATION
Event: :MPC HA.MPC RECEIVE MESSAGE
Time Range:-200ns TO 1sec PTIMEBASE = 200 ns
Status: OK
Time Interval: Bin Sum : Time
]
------------------+----------+--------]
< 200 ns :
0:
0 ns]
200 ns- 1200 ns+:
0:
0 ns]
1400 ns- 9200 ns+:
0:
0 ns]
9400 ns65 us+:
0:
0 ns]
65 us- 447 us+:
58: 5165 us]
------------------+----------+--------]
Time Min:
89.0 us
Time Max:
89.2 us
?

5-168

AP·431

measure the time spendt in the mpc_transmit_messaqe routine

Mode: DURATION
Event: :MPC HA.MPC TRANSMIT MESSAGE
Time Ranqe:-200ns TO 1sec PTIMEBASE = 200 ns
status: OK
Time Interval: Bin Sum : Time
]
------------------+----------+--------]
< 200 ns :
0:
0 ns]
200 ns- 1200 ns+:
0:
0 ns]
1400 ns- 9200 ns+:
0:
0 ns]
9400 ns65 us+:
0:
0 '-ns]
65 us- 447 us+:
58: 5316 us]
------------------+----------+--------]
Time Min:
91.6 us
Time Max:
91.8 us
?

measure the time spendt in the whole interrupt

routine

?measure (:c286_int_handler)
Mode: DURATION
Event: :C286 INT HANDLER
Time Ranqe: 200ns TO lsec
PTIMEBASE = 200 ns
status: OK
Time Interval: Bin Sum : Time
]
------------------+----------+--------]
< 200 ns :
0:
0 ns]
200 ns- 1200 ns+:
0:
0 ns]
1400 ns- 9200 ns+:
0:
0 ns]
9400 ns65 us+:
0:
0 ns]
65 us- 447 us+:
0:
0 ns]
------------------+----------+--------]
Time Min: 1409.2 us
Time Max: 1412.8 us
?

measure the ti~e spendt in the enqine model routine
note that the enqine model calculation time is variable dependinq
on the switch position of the subsystems
?measure (:cf6_enqine_local.enqine)

5-169

Ap·431
Mode: DURATION
Event: :CF6 EN.ENGINE
Time Range:-200ns TO lsee
PTIMEBASE = 200 ns
status: OK
Time Interval: Bin Sum : Time
]
------------------+----------+--------]
< 200 ns :
0:
0 ns]
200 ns- 1200 ns+:
0:
0 ns]
1400 ns- 9200 ns+:
0:
0 ns]
9400 ns65 us+:
0:
0 ns]
65 us- 447 us+:
0:
0 ns]
------------------+----------+--------]
Time Min: 633.0 us
Time Max: 636.6 us
?

measure the time spendt for copying the data from the
mpc_message_structure to the inputs buffer
?

?pat init duration :e286_int_handler#26 to :e286_int_handler#27
?pat displ'ay
Mode: DURATION
Event: :C286 INT HAN#26-#27
Time Range: 200ns TO lsee
PTIMEBASE = 200 ns
status: OK
Time Interval: Bin Sum : Time
]
------------------+----------+--------]
< 200 ns :
'0:
0 ns]
200 ns- 1200 ns+:
0:
0 ns]
1400 ns- 9200 ns+:
0:
0 ns]
9400 ns65 us+:
62: 1895 us]
65 us- 447 us+:
0:
0 ns]
------------------+----------+--------]
Time Min:
30.4 us
Time Max:
30.6 us
?

measure the time spendt for the transport protocol adaptation
?pat in it duration :e286_int_handler#30 to :e286_int_handler#35
?pat display
Mode: DURATION
Event: :C286 INT HAN#30-#35
Time Range: 200ns TO lsee
PTIMEBASE = 200 ns
Status: OK
5-170

Ap·431
Time Interval: Bin Sum : Time
]
------------------+----------+--------]
< 200 ns :
0:
0 ns]
200 ns- 1200 ns+:
0:
0 ns]
1400 ns- 9200 ns+:
0:
0 ns]
9400 ns65 us+:
50: 873 us]
65 us- 447 us+:
0:
0 ns]
------------------+----------+--------]
Time Min:
17.4 us
Time Max:
17.6 us
?

measure the total time used for the mpc interrupt processing
from hardware interrupt on.
Mode: DURATION
Event: :MAIN M.INTERRUPT ROUTINE
Time Range: 200ns TO lsec
PTIMEBASE = 200 ns
Status: OK
Time Interval: Bin Sum : Time
]
------------------+----------+--------]
< 200 ns : 0 :
0 ns]
200 ns- 1200 ns+:
0:
0 ns]
1400 ns- 9200 ns+:
0:
0 ns]
9400 ns65 us+:
0:
0 ns]
65 us- 447 us+:
0:
0 ns]
------------------+----------+--------]
Time Min: 1450.0 us
Time Max: 1453.6 us

profile the relative time spend by the three main routines
?
?pat init profile :mpc_handler_module.mpc_receive_messaqe,&
??:mpc_handler_module.mpc_transmit_messaqe,&
??:cf6_enqine_local.enqine
?pat display

Mode: PROFILE
PTIMEBASE = 10 us
Include calls
status: OK

5-171

Ap·431
Event
count 0%
10
20
----------------------------+---------+---------+------ENGINE
61:xxxxxxxxxxxxxxxxx
MPC TRANSMIT ME
61:xxxxxxxxxxxxxxxxx
MPC-RECEIVE MES
61:xxxxxxxxxxxxxxxxx
* Background*
182:xxxxxxxxxxxxxxxxxxxxxxxxxxx
----------------------------+---------+---------+------Total
365 0%
10
20
?histo=false
?pat display
Mode: PROFILE
PTIMEBASE = 10 us
Include calls
status: OK
Event
: Count: Time:Time Min:Time Avg:Time Max
----------------------------+--------------+--------+--------+-:CF6 EN.ENGINE
444: 318 ms: 710 us: 710 us: 720 us
:MPC-HA.MPC TRANSMIT : 444:
41 ms:
90 us:
90 us: 100 us
MPC RECEIVE-MESSAGE
: 444:
39 ms:
80 us:
80 us:
90 us
* Background*
: 1331:
22sec:
40 us:
16 ms:
50 ms
--------------------------------+----------+--------+--------+-Total
2663:
22sec
?
?

make the interrupt to routine activation measurents
mpc

interru~t

to start of the interrupt routine

?pat init duration interrupt to :c286_int_handler.mpc_interrupt
?histo = false
?pat display
Mode: DURATION
Event: *INT*-:C286 INT HANDLER#15
Time Range: 10us TO lsec
,

PTIMEBASE = 200 ns
status: OK,
Time Interval: Bin Sum : Time
]
------------------+----------+--------]
<
10 us :
0:
0 ns]
10 us11 us+:
0:
0 ns]
11 us19 us+:
70: 919 us]
19 us75 us+:
0:
0 ns]
75 us- 457 us+:
0:
0 ns]
------------~-----+----------+--------]

Time Min:
Time Max:

12.8 us
13.6 us

5-172

AP·431

mpc interrupt to start of mpc_receive_messaqe
?pat init duration interrupt to
:mpc handler module.mpc receive message
?pat-displayMode: DURATION
Event: *INT*-00l09DH
Time Range: 200ns TO 1sec
PTIMEBASE = 200 ns
status: OK
Time Interval: Bin Sum : Time
]
------------------+----------+--------]
< 200 ns :
0:
0 ns]
200 ns- 1200 ns+:
0:
0 ns]
1400 ns- 9200 ns+:
0:
0 ns]
9400 ns65 us+:
71:·1523 us]
65 us- 447 us+:
0:
0 ns]
------------------+----------+--------]
Time Min:
21.0 us
Time Max:
22.0 us
1
1
?

1/* end of test session */
?

1halt
*Probe 0 stopped at :MAIN MODULE 286 + 74H because of halt
Clips= F6 Trace Buffer-Overflow
*exit
I2ICE terminated

5-173

APPLICATION
NOTE

AP-433

May 1989

Simple I/O Design Example
using the MULTIBUS®II
Modular Interface eXtension
(MIX) Architecture

ERIK A. STEEB
OMSO TECHNICAL MARKETING ENGINEER

@INTEL CORPORATION, 1989

Order Number 281004-001
5·174

inter

AP-433

PURPOSE
This application note introduces the MULTIBUS!il II Modular Interface eXtension (MIX) architecture through the use of a simple
I/O design example. The example is intended as a "design primer" to assist an engineer in implementing a custom I/O design on
the MIX interface. It is assumed the reader is familiar with MIX architecture concepts, MULTIBUS II and the MULTIBUS II
System Architecture (MSA).

RELATED DOCUMENTS
oniernumber500729~1

MIX Module Design Specification
MIX 3861MOxPP Baseboard User's Guide

order number 500730'{)()1.

5-175

intel

AP-433

1. INTRODUCTION
Since its introduction, MULTIBUS(i) II has proven to be a
very good solution for high perronnance computing. The bus
is well sui1ed high peIfonnance applications due to its ability
to support multiple CPUs in a loosely coupled environment.
This capability is not only borne in hardware but in the
finnware and software as well.
In this loosely coupled multiprocessing environment, many
CPUs are able to interopemte on a common backplane. With
this ability comes the need for a system design which is
separated along functional boundaries. This means particular
I/O needs of the system are handled in a client/server fashion
instead of the tmditional master/slave method. The difference
in the two approaches lies in the ability of the I/O server to
support more than one host processor while the slave cannot.
The use of a functionally partitioned system allows for better
structured progmmming and ease ofupgmding system resources. However, the designers of special I/O are faced with the
challenge of more complex board designs. For MULTIBUS
II this means not only designing a board which supports
message passing and the multiple address spaces defined for
the bus, but also one with an intelligent CPU core ana a high
speed memory subsystem. These added requirements not only
increase the design complexity but can also greatly affect the
time to market of a product
Intel has developed an I/O stmtegy which eliminates the
bunlen of developing the compute engine and PSB interrace
of the I/O server, therefore easing the problems associated

with designing special I/O for MULTlBUS II. This is done
by decoupling the specific I/O technology from the CPU
technology in a baseboard/modulefashion as shown in Figure
1. With this design, an Intel baseboard is coupled with an 1/0
module supplied by Intel, the customer, or a third party.
Although the baseboard and module are separate boards, the
combination fqnns a single slot I/O server for MULTlBUS
II.
The modular design allows an engineer to focus his efforts on
the 1/0 needs of a product by integmting his special 1/0 design
with an intelligent MULTIBUS II I/O platfonn supplied by
Intel. This platfonn provides the necessary computational
power required of an 1/0 server but leaves the special 1/0
module design to the customer.
The stmtegy outlined above is known as the Modular Interface
eXtension (MIX) architecture. This document gives an application example and illustmtes a simple liD design which utilizes
the MULTIBUS II MIX architecture.

2. MIX APPLICATION EXAMPLE
Because the MIX architecture allows stacking of up to three
MIX modules on a high perronnance baseboard,price/peIformance scalability is offered along with ease of design for
MULTlBUS II, ease of upgmde potential, and support for
Intel opemting systems. Therefore, a MIX design fits well in
virtually any ~LTIBUS II application.
The use of MIX however is best suited for those applications
which require high perronnance and/or a large numberof1/0

b~~~d
AA

Figure 1. MIX Baseboard/Module Combination

5-176

Indicates Bare
Fab Area

Ap·433
connections which, when combined, demand CPU
bandwidth. The following example is given to illustrate the
demands which the MIX concept is designed to address.

2.1 Flight Simulation System
In flight simulation system designs, many computationally
intensive simulation tasks exist which demand very' high
pelfonnance and multiprocessing capabilities to achieve the
necessary real-time I/O processing. These requirements stem
from the system's need to accurately and quickly convert pilot
and ain:raft action into control and instrumentation reaction.
This application requires plenty of computational muscle, a
fast real-time kernel to handle the simulation tasks, and lots
of I/O bandwidth. In addition, a custom interface for cockpit
controls and instrumentation is required to handle all aspects
of the simulation process.
Consider simulating airflow over a wing. A processor must
not only compute the forces on the wing which result from
the fluid motion of air over its surface, but also detennine and
apply (m real-time) the proper amount of feedback pressure
to the pilot's control stick.

In addition to the simulation requirements of the system, a
flight data collection and storage mechanism, and possibly an
instructor interface, will be needed to handle on line customization of the flight variables and post-flight critiques.
These tasks demand multiprocessing capabilities in an environment which allows constant interaction among the
seperate processors completing the tasks. MULTlBUS II is
an excellent architecture for such system requirements due to
its 32 megabyte per second bus transfer rate, high perfor-

mance multiprocessor support, andmessage passing bus communication design. In addition, the MULTIBUS II Systems
Architecture fmnware architecture and operating systems
supported ease the system level integration requirements for
such a system.
A rough system configuration is shown in Figure 2 A single
iSBC 386/120 CPU running UNIX works in conjunction with
an iSBC 386!2S8 SCSI controller to provide data storage and
retrieval as well as an instructor interface. Another iSB~
386/120 controls the engine simulation and weather variation
functions, while a third handles radar and communications
simulation.
The MIX baseboard in this example controls the airflow
simulation as well as the instrumentation output and control
stick feedback I/O. The I/O interface to the actual simulator
instruments and control stick is accomplished via a slaveMIX
module which utilizes a high speed digital I/O link. This
module is the only hardware which must be designed by the
systems integrator.

In addition to the high perfonnance hardware functions this
solution provides, it also offers support for current Intel
system firmware and operating systems.
From afinnware point of view, all boards discussed ship with

Intel MSA compatible firmware. This allows ease of integration into a system environment in tenns of board and system
level diagnostics, boot mechanisms, and board-to-board communication suppon.
Ease of integrating the custornMIX module intothis firmware
architecture is also provided. Functions in the MIX baseboard
fmnware allowthe I/O module firmware to interact with the

8~
\/
iRM~1I
iSBCID386/258

110 Interface to cockpit instrumentation
and control stick feedback servos.

UNIX
iSBCID386/120

~~~--------.~~U-L-T-IB-U~~R~"-P-S-B~~--------~
Figure 2. Flight Simulator Example

5-177

inter

AP·433
provides three 8-bit parallel I/O ports programmable in three
modes. The speed requirements of the digital I/O interface are
met by utilizing the 82C55A CHMOS version of the chip.
This version offers much better timing specifications for
command widths and command recovery times as compared
to the NMOS 8255A. In addition, the CHMOS device consumes much less power than its NMOS relative.

baseboard finnware for diagnostics, boot, and operating requirements wilhout the need for modifying the baseboard
EPROM contents. This enables any standard or special I/O
modules to participate in BIST testing and boot procedures.
The demand for high performance software capabilities can
be easily realized with the use of the iRMKCil real-time kernel.
This 32-bit kernel includes the transport and message passing
support necessary for the intra-system communication used
in completing the system level task. In this example, the MIX
baseboard and each iSBC 386/120 perfonning simulation
tasks runs the iRMK kernel

For the serial interface, the module will utilize the 82510
Asynchronous Serial Controller. This chip is chosen over the
more common 82530 due to its proven high perfonnance and
its low power, CHMOS characteristics. In additi

"05'

IOCYC·=O'/.

,"sWAIT=1

'OCY~

~_O

.occ:'G(

.IOCSG

Va.a....: WO,IIXWAlT

Figure 7. MXWAIT Machine State Diagram

5-188

AP-433
Although the WO and Sx variables are only used as internal
variables to the PAL device, they must be assigned to actual
pins on the 22VI0 PAL device, bringing the number of output
pins on the device to ten. FurtheIJ1lore, the Sx and SWAIT
variables are defined in the PAL source as registered
(synchronous) outputs via the ":=" syntax.
From the asynchronous machine states, we can assign a truth
table as shown in Table 4. Note that Table 4 gives values for
CYC which is the logical state of the IOCYC* signal
(IOCYC*=O - CYC=I). Also "SW" represents the state of
SWAIT and WAIT represents the logical value ofMXWAIT
(i.e. WAIT=1 - MXWAIT*=O). This leads to the equations
for WO and MXWAIT as listed in the PAL source code in
AppendixB.
The synchronous machine follows a similar design, although
in the synchronous case there are six variables instead of four.
The PAL source for the synchronous machine is also listed in
AppendixB.

Current State

WO WAIT

Next
State
eye SW WO WAIT

.....................................
0
0
0
0
0
1
1
1
1

0
0
0
1
1
1
1
0
0

0
1
1
1
1
1
1
1
0

0
0
1
0
1
1
0
0
0

0
0
0
0
1
1
1
1
0

The hardware requirements of the module's serial EEPROM
block consist of a single device, a 128 byte 93C46 serial
EEPROM. This device is available in an eight pin skinny dip
package which may be connected directly to the MIX interface signals. Of the 8 pins, 2 are N/C C'no-connect") pins.
The firmware portions of the serial EEPROM are discussed
in Chapter 6 of this document.

5.7 Simulation
Because this module is an extremely simple design and is
being prototyped in a wire wrap version, hardware simulation
is considered supedluous. In this case, a trace routing or
device interaction problem will not cost additional fab
production cycles or considerable CAD problems.
The PAL devices however, are easily simulated using the
PALASM2 software. This software includes a state simulator
which allows the designer to set the trace mode for various
PAL signal outputs and encode various input signal states into
a line equation. By changing the input states, the designer can
examine the output conditions generated. This is true for both
the, asynchronous and synchronous PALs designed for this
module.
In the simulation for the IODCD PAL, we should investigate
both valid and invalid accesses to the peripheral chips. In the
PALASM source file for the I/O decode PAL (lODCD) in
Appendix B, there is a section maIked SIMULATION. The
mACE ON statement lists the signals which are to be
examined and the SETF statements are used to change the
states of the input signals.

0
1
1
1
1
1
0
0
0

Table. 4. WAIT State Machine Truth Tables
For the I/O Control PAL's 25 MHz clock source, a 50 MHz
crystal oscillator is routed through a D flip-flop which
provides a divide by 2 function. The output of the flip-flop is
then tied to the clock input pin of the PAL
The fmal piece of the I/O control block which must be
designed is the logic which supplies the address lines to the
peripheral devices. Because the devices require active high
address lines, we need only invert the MXA4* through
MXA2* signals and route them appropriately. Note that the
82510 is the only device which requires the MXA4* signal~

5.6 Configuration Data Block
The serial EEPROM on the MIX module provides a means
with which the baseboard microcontroller may download
configuration data during power up. This allows the
baseboard's interconnect space to reflect specific configuration data of the MIX modules present on the stack, while
allowing the rnicrocontroller fiIJ1lware to remain standard.

5-189

The first SETF statement sets up an address to the PAL of
bill, which corresponds to PPIl. Thenextstatement specifies
a word access is occurring, and finally an indication of a valid
I/O cycle is given. Finally, the IOCMD signal is activated to
indicate either an IORD* or IOWT* command is active. As
shown in the selective trace listing, these inputs result in no
chip selects since PPIl may only be accessed as a byte wide
device or in combination with PPIO.
The next group of statements changes the byte enables to a
byte access which results in the /CSPI signal being activated.
The next changes the address to 0xH which is the address of
PPIO. This leads to /CSPO and /GATBO being activated. Note
the widths of the gate signals during both read and write
accesses. They are longer during writes to provide the data
hold requirements of the peripheral devices. The remaining
portion of the simulation sets up the byte enables to represent
WORD and DWORD transfers to the PPls. The word transfer
results in the /CSPO,/CSPl,/GATBO, and IGAT32 signals
being activated, while the DWORD transfer also activates the
ICSP2 and ICSP3 signals. These accesses are therefore
equivalent to having 16 or 32-bit PPls.
The simulation for the I/O control PAL follows a similar
process. This simulation however, allows the designer to
simulate clock ticks as well as input signal state changes. The

Ap·433
simulation is set up by placing the PAL in a reset state. The
clockis cycled, then the reset is removed and an I/O read status
is set. The LCLSEL*, MXCYC*, and MXCMD* signals are
then set to simulate the states the PAL would normally

code while allowing PSB agents to determine the type of MIX
modules present via the baseboard's interconnect space. This
structure allows dissimilar MIX modules to stack together
without the need for modifying the baseboard's interconnect
configuration data. Module resident BIST code allows the
baseboard to test the hardware on the modules without the
need for custom fmnware on the baseboard. This allows
different modules to stack together without the necessity of
custom BIST code on the baseboard.

enCOlDlter. To check theMXBS 16* function, the PPIO address
is simulated on address lines/A6* through/A4*. The PAL is
clocked several times to examine the operation of the
MXWAIT* and MXBS 16* outputs. As shown in the selective trace listing, the WAIT state machines step through their
states as designed (MXWAIT* =0 corresponds to~AIT
= I), with the MXWAIT* signal active for four clock pulses.
Furthermore, the listing shows MXBS16* inactive
throughout the cycle. This is desirable since 32-bit accesses
are allowed for PPIO. Also we seeIOCYC* go active with the
MXCYC* signal and the 10RD* signal go active when
MXCMD* is activated. This occurs because the SWAIT
signal is already active when MXCMD* is activated.

6.1 Serial EEPROM
The requirement placed on modules for interconnect space is
the support of the National Microwire'I'M standard serial
EEPROM. This is a 128 byte device which is arranged in a
64 x 16 bit configuration which allows random access of 64
word registers over four signal lines. It is programmed to
contain two interconnect records which describe the configuration of the MIX module. Each interconnect register is a
two byte value. The MSB contains the register protection
information and the LSB contains the function's value. The
baseboard's 8751 microcontroller downloads this information during power up and appends it to its own interconnect
data. The MIX Module Design Specification describes the
format which the EEPROM finnware must follow in order to
function with the baseboard's 8751.

A second MIX transfer cycle is simulated to represent a full
speed transfer cycle. In this cycle, we want to assure the proper
WAIT machine function for command recovery and further
examine the MXBSI6* function. To do this, the address of
PPIl is presented to the PAL which should force MXBSI6*
to activate. We desire this since 32-bit cycles are only allowed
for the PPIO address offset. We also present active MXCYC*
and MXCMD* signals to the PAL very soon after the end of
the previous transfer cycle. This means MXCYC* has a short
inactive pme between cycles 1 and 2. This second simulation
changes the polarity of theMXWR signal to represent a write
request.

The standard format has two interconnect records, the
Hardware Extension Record and the Module Specific Record
as shown in Table 5. A custom module uses the standard
template as a guide to defining themodule'sinterconnect data.
Required values for the registers are included in Table 5.
Those registers listed as TBS in the value columnhaveregister
values "To Be Specified" by the module designer.

Once MXCYC* is activated we see both MXBSI6* and
MXWAIT* immediately activated. This ensures us we provide MXBSI6* and MXWAIT* within the allotted 40 ns. In
this cycle, when the command signal (MXCMD*) is activated
the 10WT* signal does not come on. This occurs because the
synchronous machine has not yet cycled through all of its
inactive states. In the selective trace listing we see the
synchronous machine continue through its inactive states
even though there is a valid transfer cycle occurring. Once the
machine reaches the 0001 state, 10WT* is activated. This has
the effect of holding off the write command until the
synchronous machine is ready to acknowledge it. Therefore,
this is the command recovery mechanism built into the WAIT
machine. '

This module defines its registers as shown in the "EX" column
of Table 5. The vendor ID, 0001 (0900,0901), represents the
Intel vendor number for MULTIBUS II. Intel administers the
assignment of specifiC'vendor numbers to MULTIBUS n
board manufacturers.
This Module's ID has been defined to be "TM_MIX_MOD",
with the "T' occupying register 6 and the "D" occupying
register OFH. Note that the AScn equivalent of the string is
placed in the Module ID registers.

With acceptable PAL code simulations completed we can
tum our attention to firmware requirements and module
prototyping.

6. MODULE FIRMWARE
The MIX architecture has several finnware requirements for
modules to assure proper interaction with MIX compatible
baseboards and other modules. These requirements place the
responsibility of supplying necessary configuration data and
BIST tests on the module. While the module is responsible
for supplying it, configuration data for the MIX modules is
treated as an extension of the baseboard's interconnect space.
This allows a MIX baseboard to use standard microcontroller

Because this module is a wire wrap prototype, all revision
level registers are given the value of O. Finally, since this
module was not designed with EPROM devices or self test
capabilities, its BIST support level is defined as O. This level
means either the module hardware is not tested during power
up or the baseboard firmware is responsible for supplying the
module BIST code. In the case of this module, the former is
true. A BIST support level of 0 implies that the Jump Table
Pointer registers are assigned a value of O.
Now that the registervalues are defined, the EEPROM device
must simply be programmed and installed on the module. All
download functions are handled by the baseboard
microcontroller and do not concern the module designer.

5-190

intel

AP-433

Access Rights
Local Global

Description

Value

...................................
.......................................... , ..............

..............

HARDWARE EXTENSION RECORD

0
1
2
3
4
5
6-0FH
10H
11H
12H
13H
14H

HIW Ext. Record Type
Record Length
HIW Ext. Type (LSB)
HIW Ext. Type (MSB)
Vendor 10, Low
Vendor 10, High
Module 10, Char 1-10
HIW Test Rev Level
Number of Records
RFU
RFU
RFU

RIO

RIO
RIO

RIO
RIO
RIO
RIO
RIO

RIO
RIO
RIO
RIO

0914H
0913H
0910H
0900H
TBS
TBS
TBS
TBS
0901H
0900H
0900H
0900H

RIO
RIO

RIO
RIW1

RIO
RIO
RIO
RIO

........................................... ,

0914H
0913H
0910H
0900H
0901H
0900H

2900H
0901H
OgOOH
0900H
0900H

..........

MODULE SPECIFIC RECORD
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H-3FH

Mod. Specific Record Type
Record Length
EPROM Entry Table Ptr., MSB
EPROM Entry Table Ptr., Byte 3
EPROM Entry Table Ptr., Byte 2
EPROM Entry Table Ptr., LSB
RFU
HIW Rev Level
BIST Test Support Level
RFU
RFU
RFU
Module Specific Info

RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
'RIO
RIO
RIO
RIO

RIO
RIO
RIO
RIO
RIO
RIO
RIO

09FOH
TBS
TBS
TBS
TBS
TBS
0900H
RIW1
TBS
RIW1
TBS
RIO
0900H
0900H
RIO
RIO
0900H
Module Defined

09FOH
0909H
0900H
0900H
0900H
0900H
0900H
2900H
2900H
0900H
0900H
0900H

Table 5. MIX Module Interconnect Template

The 93C64 device can be programmed using a standard
EEPROM programmer which supports the device. Because
the device is electrically erasable, it is possible for the
EEPROM to be programmed by the baseboard's
microcontroller. At the time of this module design, this support was not included in the baseboard 8751 fmnware.6.2
BIST Support Levels
The MIX architecture provides several BIST support levels
as described in the MIX Module Design Specification. inclusion of EPROMs and BIST finnware on modules allows
power up verification of the module hardware and provides
diagnostic capabilities when module hardware problems are
encountered.
This module does not incoIpOrate EPROM or BIST support
·initsdesign. This is defined as BISTsupportlcvelO. Although
level 0 allows the stipulation that the MIX baseboard carry
the module BIST code in its EPROM, this module design
assumes no power up testing is pelformed on the module
hardware. This option was chosen because of the simplicity
of the module hardware used in the design. Furthermore,
5-191

addition of moduleEPROMs would have further complicated
the I/O control block portion of the design, which would have
lessened the simple example intentions of this module design.

7. MODULE PROTOTYPING
Once the module is fully defmed and its schematic has been
completed, a final check of the modules electrical characteristics can be made. The main concern here is the power
requirements of the module. We should ensure the devices
used in this design meet the power consumption requirements
listed for the MIX intelface. Once we have assured these
characteristics, layout and actual wire wrapping and debug
can be done.

7.1 Electrical Considerations
Before the actual module assembly begins, we must check the
module design against the electrical specifications for the
MIX intelface. The two major issues here involve the drive
characteristics of the devices which connect to the MIX
signals and the total maximum power consumption of the

inter

Ap·433

module. Both of these parameters may affect how the module
operates with the MIX baseboard or other modules.
The drive characteristic check dcals with the type of driver
used on the MIX bus. The MIX specification states that no
module may use open collector devices to driye the MIX bus
signals. A quick check of the module device specifications
assure us, that the module meets this requirement.
The second area of concern is the power consumption of the
module. The MIX Module Design Specification states that
each module may consume up to 3 Amps of +5 VDC. Again,
by going through each device's spec sheet we can compute
the maximum and typical power consumption of the module.

In reviewing the components used for this module, we find
the maximum current draw on the +5 V power is just under
2.5 Amps for the entire module, including the LEOs. Although we find this simple module is surprisingly near the 3
Amp limit, a typical module design would not implement 32
LEOs which draw about 25 rnA each.

7.2 Wire Wrap Layout
Now that the electrical requirements of the MIX module are
verified, actual prototyping will be done. The layout portion
of the prototyping requires knowledge of the signal paths and
component interconnection. The schematic capture program
used in this design contains a program which generates a
netlist from the schematic outpuL With this netlist and the
MIX M002 Breadboard Module, we are ready to begin the
layouL

In laying out components for the MIX design, careful attention should be given to the trace length requirements given in
the MIX Module Design Specification. Although this is merely a wire wrap version of the fmal product, adhering to the
trace length rules may save some debugging headaches later.
The Breadboard module offe'rs the standard MIX module
width and MIX interface footprint, however, the board length
is much longer than a standard module. This added length is
provided to allow an engineer to prototype surface mount
designs using OlP components which require more design
area.
The module layout follows the signal paths between the MIX
interface and I/O devices. The tennination resistors and data
transceivers are placed nearest the MIX connector. The two
PAL devices and EEPROM also reside adjacent to the connector due to their direct connection to interface signals. The
PPI devices and 82510 are placed next. and the output drivers,
LEOs, and connectors are placed at the edges of the board.
This layout structure provides a natural signal propagation
from the MIX interface out to the edges of the module and
ensures the trace lengths are kept to a minimum. Once the
components are placed, they may bcconnected via wire wrap.

7.3 Module Debug
Once the module has been completely wired up, itis ready for
verification and debug. Although most designers are confident to immediately initiate a "smoke test", it is wiseto verify
the device connections with the netlist provided by the
schematic capture package. This is time consuming but is
easily done using a simple ohmmeter. Once this has been
checked out, the module may be installed on the baseboard
for fmal debug.
The fmal validation for this module was performed on a MIX
386/MOXPP Pre-production baseboard with a MIX MODI
Test Module in module slot 0 and the wire wrap module in
slot 1. In this stacking configuration, the wire wrap module's
I/O address space ranges from 0800H to OCOOH. This means
the I/O address offsets encoded in the IOOCO PAL are added
to the base address of 0800H to obtain the actual addresses
for the module's devices. For example, the baseboard 386
microprocessor would access PPIO at 098xH.
To facilitate ease of baseboard I/O access, fmnware was
placed on the MIX baseboard which contained a OMON 386
monitor confIgured (with the proper 82510 port address) to
run with MIX MODI in module slot o. This provides a serial
interface for the baseboard and removes theneed for additional system boards (except the CSMJOO1) for the module debug.

In debugging the board, we must check out several things,
access to the boards serial EEPROM, parallel port
functionality, and 82510 functionality. The serial EEPROM
interface is verified by reading the baseboards interconnect
space. OMON386 provides aninputinten:onnect(ii) function
which aids in this task. The MIX 3861MOxPP Baseboard
User's Guide shows the first HJW Extension Record should
begin at interconnect offset 65H. This register can be checked
for'a value of 14H. If the 14His found, the module ID registers
(6BH - 74H) can be read. If !he module's ID is present (in
ASCIT), the serial interface is functioning.
The parallel ports may be verified by using the LEOs designed
on the module's PPlport C or by using alogicanalyzer. Using
the LEOs requires setting up port C of the PPI as a simple
output port and then making output accesses to port C to
toggle the LEOs. To use a logic analyzer, direct accesses to
the PPIs may be checked, or the port outputs may be checked.
To verify the port A connector, ports A and B must be
configured as an output port since bits 0 and 1 of port B control
the direction and enable pin of the port A drivers.
The addressing scheme used in this module places the port A
data bus at xOH, the port B data bus at x4H, port C's data at
x8H, and the PPI's control port at xCH. For the PPI verification, all PPI ports are set up as simple output channels. This
is done by writing 80H to ports 098CH, 099CH, 09ACH, and
09BCH. As shown on sheet 10 of the schematic, port B bits
Oand 1 affect the function of the port A driver chip. Therefore,
a 3 is output to 0984H to enable the port A drivers and set their
direction as outputs. Oata is then oulput to both ports A and
C to verify the module operation.

5-192

Ap·433
The 82510 device may be similarly checked out. With the
module in slot 1, the 82510 internal registers begin at I/O
address 09COH. The chip can be verified by setting its 3S
internal registers to configure a loopback mode to verify data
transmit and receive data consistency.
Once the 82510, PPIs, and EEPROM operation have been
verifIed, a high level of design confidence is achieved, and
production cycles may proceed as needed.

8. CONCLUSIONS
Although this module design is a simple one and has been
done simply for display and example purposes, it conveys the

considerations required in a MIX module design effort. Furthennore, the control and data drivers blocks of the module
may be used as a design guide in many simple slave I/O
module designs.
The module schematics and PAL source codes have been
included in Appendices A and B as an aid to designing simple
I/O modules and as a basis formore complex module designs.

5-193

APPENDIX A
MIX MODULE SCHEMATICS

5-194

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PBT
PCO
PCl.
PC2
PC3
·PC4
PCS
PC6
PC7

1=
t:
~

""""."H-'"

". roc:ument Nu..... r

at.:-

T"-"IX-"OD~PI~ARL

•

••

"1>~1';

_'''''I
U2S
DD
01
D2
D3
04
as
as
07

B
AD
Al

WET

PAD
PAl
PA2
PA:!
PA4
PAS
PAS
PAl
paD
pal
pa2
pa3
pa4
pas
pas
pa?

BA. . . . . . . . ~

... ~

B~"'L

1=
~

PCO
PCl
PC2
PC3
PC4
PCS
PCS
PC?
~

......

C!'
~

t= !=
t= t=

c.J

~
~

!=
t::

DO
01
D2
D3
D4
DS
DS
07

ili B.WET
AD
Al

.,
7
7
7
7
7
7

.........-

......-........

a
1=
~
1=
t

PCO
PCl
PC2
PC3
PC4
PCS
PCS
PC?

PAD
PAl
PA2
PA3
PA4
PAS
PAS
PAl
paD
pal
pa2
PB3
pa4
pas
pas
pa?

[ .. rocu..nt
a
'K-"IX-"OD/PPI/PARH
I

Nu~.r

ate:

••

A
D

AP-433

....
.. ..

j
U
fMN..a..

~~!:I::!!"~~ ~~~!:I::!!".

J~~!:I::!!'"

.. """.........

~ ~

............... ~~

.. N .............

.. N ......" ....

.. N ...........

-'v"

I~M....a~...
J............

I~ ~

~....a~... ~ ............
~....a~...
M
rM...........
..,,".. .,.

.. 1'4,. ... .,. .. ,...

~ ~

......

-tNIIH'''' .. ,..

..filM .. "' .......

;

. "N..a... ~

~ .. ..........

~ ~

...
V

ll1ll

Jil::::;==lDiIl
.. NM .. .,. .......

ClCZClClCClCECl

:; J~"M"~_~.
ua ...... ........ uS;
• • lDllmIUDGI

UJ~

"NM Ut ......

[HLLL! !

~
5
~

J. . M.. ......
~
• • IIIDIDIUDIll

.. NM .. I111 .......
CZ:«C«a:ClCC

51
••• "ID.fDm
ua.."' J~N""~""''' us;
.. N ..... .,. .....
ClClClCCCECa:

I Ul.I.

~2J~1
•

..Ii

.Ii

•
5·204

•

.,,,,,~n

J"
Al
A2
A3
A4
AS

;co

RP9S
270

RP9C
270

RP90
270

RP9E
270

RP9F
270

RP9C:
270

RP9H
270

.. "'"1

C2
C3

J"AO
J3Al
J3A3

AI0
All

CI0
Cll

J3A9

A12
A13

C12
C13

A14
A1S

C14
C1S

J3A13

A16
A17

CLIO
C17

J3Al!!:

Ala
A19

Cla
C19

A20
A21
A22
A23
A24
A2S
A26
A27

C20
C21
C22
C23

AS
A9

C4
CS
C6
C7
ca
C9

A6
A7

RP9A
270

J3A!!:
J3A7

.,"''' "

"E.

.' ..... 7

J""'"
J" .. 2.

C24
C2S
C26
C27

J""23

A28
A29

C28
C29

J3A27

A30
A31

C30
C31

A32

C32

J3A2!!:

J3A29

.,,,,,,,,

"~IJL'"

z. Foc:ument Number
S
T"-HIX-HOD~PI;OUTPUT
o
••

.te:

inter

AP-433
a:

III

...... ........
5-206

intJ

AP·433

5-207

APPENDIX B
MIX MODULE PAL CODE

5-208

Ap·433

!'.U:le
.Pat:t:ern
Rev
Autllor
COIJ!Pany
Dat:e

:rocrr. .PAL
:U14
:1.02
:BRlX A 5mBB
:I.N!'e~ Cor,porat:~OD

:10/2/89
Hbnol~tlI~e H8mC1r~e•

.PAL22VlO-15

********** **********
*
***
*
rOCLlC ** 1
24 ** Vee
*
*
IIKIaO ** 2
23 !tit IIXBS16
*
*
IIXDC ** 3
22 ** 1IXJfA:r!'
*
*
llXHR ** 4
21 ** PlO
...
*
LCLSBL ** 5
20 ** SfIIAr!'
...

...

MKcrc
MKCMD

A6
AS

A4
Grld

** 6
*
** 7

!tit

*
18 **
*
17 *'"
*

...

** 8
*
** 9

IiI'II'

S2
Sl
SO

rORD

15 ** rOJl'J!
**'" 10
*
*
14 ** rocrc
** 11
*
*
13 ** MXRS!'
** 12
*
*
*"'** ... **************** ... *
It'

5-209

AP-433

; created by eas
; (C) - COPr.RIGBT INreL Cor,poration, 1989
l'Il'LB IOC1'L PAL
PAl'1'BRN U14
RBVISION 1. 02
AM'BOR BRlX A srmm
COMPANY I.NTeL Cor,poration
DArB 10/2/89

;Revision 1.02 corrects a problem in tbe Sync:l1roDOUS wait mac:l1ine
;wbic:l1 brougbt t:be mac:l1iDe back to t:b. 0000 state wben IOCrc went
;inactive.
CHIP'IO_CONmOL PAL22VlO
;PINS 1
2
IOCLX IIXNIO
;PINS 10

/AS

/A4

;PINS 19
S2

3
4
5
6
7
IIXDC IIXPIR /LCLSBL /lIXCrc /IIXCIID

,12

GND /NXRSl' /IOCrc /IOII1'

20
SJlAIl'

"0 /NXfIAIl' /IIXBS16

vee

/IORD

NC /A6

'25
INIl'

BQtlAl'IONS
IOCYC

IO_crcLB

IORD

IO crcLB

/IIXPIR
IIXCIID

* IIXCIID *

SJlAIl'

IOfl1'

IO CYCLE

IIXPIR
IIXCIID

* IIXCIID *

SJlAIl'

+ IoRD

+ Im

NXBS16. 1'RS1'
NXBS16

+
+

*
*

IOCrC

IO C~
IO- crcLB
IO:c.rCLB

*
*

; BS16* ass.rted any access

; except to PPI O.

5·210

Ap·433

......... SrNCBRfJNOUS POR'J!ION OF IiiAI'J! lIACBINB .........

INI'J!. Ra'!'l!'

= MXRS'J!

SO ... Sl
SO ... /S2
SO ... SfIAI'J!
Sl ... /S2 ... SJiiAI'J!

+
+
+

:=
+
+
+
+

/MXCIID ...

SO ... Sl
IsO ... Sl
ISO ... S2
Sl ... /S2

,. Global reset of register outputs

SO ...

SO ... /S2 ... /SJiiAI'J!
... /S2
... S2
... SJiiAI'J!
... SJiiAI'J!

+ SO ... S2 ... /SfIAI'J!
+ ISO ... /Sl ... S2 ... SJiiAI'J!
+ IsO ... /Sl ... SJiiAI'J! ... MXCIID

+
+
+

ISO ... SJiiAI'J!
SO ... Sl ... SfIAI'J!
SO ... /Sl ... S2 ... SJiiAI'J!
IO_Crcu ... IIXWAI'J! ... IsO ... /Sl ... /S2 ... /SJiiAI'J!

......... ASrNCBRONOUS POR'J!ION OF 1iiAI'J! lIACBINB .........

JlO

IO crCLB ... /SfIAI'J! ... WO
IO:crCLB'" SfIAI'J!'" MXIiiAI'J!

MXI'fllI'J!.1'RS'J!
.HXNaI'J!

IOCrc

IO CrcLB'"

+ IO:crCLB'"

SfIAI'J!'" HXNaI'J!

two

,.
,.,.

DBSCRIP'J!ION

robe IDCrC variable is used by the tri-state outputs for HXBS16'" and

IIXWAIr'" to t'ac.ilitate the "logical false before tri-state" rule.

5-211

AP-433

mAC1I ON

/llXBSls

/IORD /Iortr /IOCrc /llXCrc /NXCND

Sl S2 SllAZJ! "0 /NXIIAIJ!

SlI'l'8' /IOCLlC 1IXR8J! /IIXCND /r.cr.SBL /lIKCrc
CLOCKF

CLOCKI"
SlI'l'8' /lIXBSJ! /1IXlCl0 IIXDC /IIXPIR
SlI'l'8' /AS /AS /A4
CLOCKI"
CLOCK!'
SlID' r.az;SlIr.
CLOCK!'
CLOCK!'
SlID' IIKCrc
CLOCKr
CLOCK!'
CLOCK!'
CLOCK!'
CLOCK!'
CLOCK!'
CLOCKI"
CLOCK!'
CLQCD'
CLQCD'
CLOCKI"
CLOCK!'
CLoczcr
SlID' IIJCCJID
CLoczcr
CLOCKI"
CLoczcr
CLOCKI"
CLQCD'
CLOCKI"
CLOCK!'
CLOCK!'
CLQCD'
CLOCK!'
CLQCD'
SBD' /NXCIID
CLOCKI"
SlI'l'8' /NXerC
SlI'l'8' /lIXBSJ! /1IXlCl0 IIXDC NJCWR
SlI'l'8' /AS /AS A4
CLOCKF
SlID' NXCrc
CLOCK!'
SlID' IIJCCJID

: set, I/O read status
: set PPIO address

: select the module
: start a val1d ~cle
,. prov1de plenty of c:J.ocks

: 1ssue the command

: release the command
: end transfer ~cle
: set I/O vr1te status
: set: PPIl address
: beg1a transfer
: 1ssue cOllllllSnd

5-212

~cle

AP-433

CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
SB'n' /NXCND
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
SB'n' /NXC'rC
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
SB'n' /LCLSBL
CLOCKF
CLOCKF
1'RACB_OFF

: release command

: end cycle

: deselect module

5-213

l~~!~~~~~~ii
:;:~ ~

g~~

i..

l~~!~~~~~~ii
:;:~ ~

g~~

i'.

l~~!~~~~~~ii
~~ ~

g~~

ig
Ji~ ~7~ ~
":i i g
i i
~

IIIIIIIIIIII~~IIIIIIIIIIII~~ 111111111111~k. ~i! I!I
R~

~ nUUuun;

IUllIIIIUli .IIIUlinUli

~f~ IIi

IIIIIIIIIIII~ IIIIIIIIIIII~ IIIIIIIIIIII~ iii~1
.gfQ
-~

91
...
g

AP-433

Page :

""""""",
ttLLkLMtLk
tLLLkLMt kb
T,T,r,r.r.r.T.T.r;r.

c c a
PRRRRRRRRR
tttLtLLLLM
kkttLLtkkL
r.r.r,r;r.r·T.T,T"T.

/IORD

~~~~~b~~~~

~b~~~~~~~~

~~b~b~~~~~

r,r;kkkkkT,kt
T,kT.T.PRPRRR

RRRRRRRRRR PRRRPRRRRR RHRRHHHH'R
PRRRRRr,r.r. u r;r.ZEuLr.r.r,k Ur,r;r.LkkLt k
r;r;T.RPRRRPT· r,r.r.T.kkLZkk r.r.r.r;r,ttr.r. k
"""""""RRB R'R'tT,T,T,T,T,T,', 1',r;r;Z;T,T,T,T,r,Z;
PHANNRHHN. PRRRRRRRRR """",."",
kUEEEEtL" kT.PRRRRRRB PRRHHRHPRR
kkr;kr,r,T,kkt kT,r;r.r.LLkkk r;r.r.kT,r;r;r;r;k

c
/ICTIIr

/IOCrc
/llXCrc
/IDCCIID
SO
Sl
S2

sazr
"0

kPRRRRPT,kL
""""""",
PRRRPRPRRR

/.MXNarr

tkkT.r.r,UT,kk

Page :

/.NXBS16 r;r.LEtkkkkk

c c c
a c cg
""""""", ElflfIRlllIflRRR
r,r.r.r.kr;tr.r.r. kkEEEEtRRR
/ICTIIr
/IOCrc T.kT,kUr.r,r,T,U r.T.r.T.kr.kEr.~
/llXCrc T.kLkkT.LLLt kk~~~~M~ML
/IDCCIID LLtMLL~LLM LMML&LLRR.
RR""'fRRPRP' """"""",
SO
~'r.r,M~Mr.r.' r,r,MMr.r.EZER
Sl
EEET.r.r.r,T;,T;,M T;,T;,&~M~Mr.r.r,
S2
sazr T;,MT;,MMMT;,MtM tMMT;,T;,tEUr.r.
""""""", PRRRPRRRR
"0
/.MXNarr RRRRRRRRJlIl PRRRRPRRRR
/.NXBS16 tUT,r.ttT,r:.r,r. ~r.rTE~r.Mr.r.
/IORD

Page :

/IORD
/IOft

/IOCrc
/NXCrC
/IDCCIID
SO
Sl
S2

sazr

c c

"""""""DR n""""""",
ttttLLLLkt LtLLLLLLt~
ktLLLLkkLL LLLkLLLkLk
r,r;r,r,lj71r,r,tr,. r,r,',r;r;r,T,T;,T,k

~~~~~~~~~b

PRRRPRRRRR RRRRRRRRRB
PRRRRRRRRR RPRRRPRRRB
T,kr,r,r,r.r.r.kk r.r.r.r.kkr.r.r;R
LMLt~LL~ML

L~tMLML~LR

PRRPRRRRRP PRRRRRRRRR
RRPRRRIRR',T, r,r,t&r,r.T,MT,T;,
~,r.r.r.M Mr,Lr.r.r,r.r,T;,M
T,MRRRRRRRP p7,EMLLr.r,t u
T,UMT.LT,MT;,T.r. ~r.T;,'T;,~LT;,T;,M
RRRRRRRRRR J!RJlRJIRRRRT.
RRRRRFlflfIflfl """"""",
MMEEEtT,T;,MM T;,r.LT;,r.tr.r.~R

c cg c
c
PRRRRRRRRB RRRRRRRRR8' PRRRPRRRRR BB
RRRRPRRRRR RRRRPRRRRR BB

'RHHHHHRRB RRHRRRRRRB BH
JlJIJDllUllUlFl """"""", """"""", BB

PP""""""", """",""",P RRRRRRRRRB BB
ttMMT;,T;,MET,U r.'T;,T;,ktT;,M~M r.MT;,T,T;,t~T;,Mt .r.r.
~LL~tt~LL~

L~~~bttttt L&ttttbtt~ ~

tttbtbErz~

'tbbktbtk~

tMtLLtLLLt

bLkkkkLtLk bktkkLktLL
kLktbLtLLL tkLLLbktkL

~ktLtLLkL~

tk~ktttttk

LL
LL
L£

/.MXNarr •••••••••• •••••••••• •••••••••• ••
/.NXBS16 ••••••••••••••••••••••••••••••••

5-215

infel'
Title

AP-433
:IODCD PAL

Pattern :U15
Rev
:1.01
~uthor

:ERIK A STEEB

eonpany :INTeL eor,poration
Date
:5/24/89
Monolithic Hemories PAL22V10-15

**********
**********
...
* ......
*

SEL
eye
CMD

BEO

......
...

......

...
......
...
......
...
......
...

Vee

......

espo

...
......

......

eSP2

......

eSP3

BEl

......

BE2

......
...

BE3
A7
A6
AS

Gnd

...

......
...

......

...
......
...

......

...
......
...

......

...
......
...
...
...

...
......
...
... ...

esse

eSPl

GATB3
GATB2

*
9

......

GATBl

... ...
...

GATBO

...

...... GAT32
...
... ... A4
...

.....................................................................

5-216

AP-433

; created by eas
; (C) - COPYRIGHT INTeL Cor,poration, 1989
TITLE IODCD PAL
PATTERN U1S
REVISION 1. 01
AUTHOR ERIK STEEB
COMPANY INTeL Cor,poration
DATE 5/24/89
CHIP IO_DECODE PAL22V10
; PINS

;PINS

; PINS

STRING
STRING
STRING

1
2
3
4
5
6
7
8
WR /SEL /CYC /CMD /BEO /BEl /BE2 /BE3
12
GND

9
10 11
NC /A6 /AS

13
14
15
16
17
/A4 /GAT32 /GATBO /GATBl /GATB2

18
19
20
21
22
23 24
25
/GATB3 /CSP3 /CSP2 /CSPl /CSPO /CSSC vec INIT
CYCLE
GATE lID
GATE_wr:r

'SEL * CYC'
'SEL ... CYC ... /WR ... CMD'
'SEL ... CYC'" WR'

EQUATIONS

...

GATBO

= GATE

lID

...

GATBl

= GATE

lID

...

GATB2

= GATE

lID ... /A6 ...

GATB3

=GATE lID

... /A6 ...

GAT32

=GATE lID

... /A6 ... /AS ... /A4 ...

/A6 ...
+ GA'nrwr:r
/A6 ...
+ GATE-lID ... A6 ...
+ GATE-wr:r ... A6 ...

+ GATE:wr:r

...

/A6
/A6

+ GATE-wr:r ... /A6

...
...

+ GATE-wr:r ... /A6 ...

/AS ... /A4
/AS ... /A4
/AS
/AS
/AS
/AS

...

A4
A4

...

/BEl
/BEl

AS ... /A4 ... /BEl
AS ... /A4 ... /BEl
AS'"
AS ...

...
...

...

BED
BED

...

BED
BED

A4 ... /BEl ...
A4 ... /BEl ...

BED
BED

BE3 ...

BE2

+ GATE-wr:r ... /A6 ... /AS ... /A4 ... BE3 ... BE2
+ GATE-lID ... /A6 ... /AS ... /A4 ... /BE3 ... /BE2
+ GATE-wr:r ... /A6 ... /AS ... /A4 ... /BE3 ... /BE2

5-217

...

...
...
...

BEl
BEl
BEl
BEl

...
...
...
...

BED
BED
BED
BED

infel'
CSPO

Ap·433

= CYCLE

* IA6 * lAS * IA4 * BE3 * BE2 * BEl * BED
* IA6 * lAS * IA4 * lBE3 * IBE2 * BEl * BED
* IA6 * lAS * IA4 * lBE3 * lBE2 * lBEl * BED

= CYCLE

* IA6 * lAS * IA4 * BE3 * BE2 * BEl * BED
* IA6 * lAS * IA4 * lBE3 * IBE2 * BEl * BED
* IA6 * lAS * A4 * lBE3 * IBE2 * lBEl * BED

+ CYCLE
+ CYCLE

CSPl

+ CYCLE
+ CYCLE

CSP2
CSP3
. CSSC

= CYCLE

* IA6 * lAS * IA4
* IA6 * AS * IA4

'Ii

+ CYCLE

* IA6 * lAS * IA4
* IA6 * AS* A4

*
*

= CYCLE

+ CYCLE

= CYCLE

A6 * lAS * IBE3

BE3 * BE2 * BEl * BED
lBE3 * IBE2 * lBEl * BED
BE3 * BE2 * BEl * BED
IBE3 * IBE2 * lBEl * BED
IBE2

lBEl

BED

; DESCRIP'I!ION;:
;
;

NAME CHANGES

SCHEMA'I!IC

;
;
;
;
;
;
;
;

;
;
;
;
;
;
;
;
;
;
;
;
;
;

;
;

PIN LIS'I!

ILCLSEL
IMXCYC
IMXCMD

ISEL
ICYC
ICMD

MXWR
IMXBEx

lBE;c

IMXAx

fiR

IAJC

Read and write accesses distinquisbed in "GA'I!" equations to meet
82CSSA-2 data bold times for writes and HrX spec data off times
for reads.
Ilo DECODE SCHEME AS FOLLOWS:
Byte Parallel
Byte Parallel
Byte Parallel
Byte Parallel
Word Parallel
DWord Parallel
Serial Port

Port
Port
Port
Port
Port
Port

@ offset xxxOOO;cxx;c bina~ (first
@ offset xx;c001;cxx;c bina~ (first
@

offset xx;c010;cxx;c

bina~

(first

= O;cH)
= 1;cH)
=2;cH)
=

@ offset xx;cOll;cXXJC bina~ (first
3~)
@ offset xxxOOO;cxx;c (Combo of two byte ports)
@ offset xxx 0 0 O;cXXJC (Combo of four byte ports)
@ offset ;cxxlOXXJCxx
(first
4;cH & S;cH)

NO'I!E: Address lines IMXA9, IMXA8, and IMXA7 not used so decode
is mirrored eve~ 128 bytes.

5-218

Ap·433
SIMULATION
TRACE ON

/SEL /CYC /CMD w.R /CSPO /CSPl /CSP2 /CSP3 /CSSC

SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
TRACE OFF

SEL

/GATBO /GATBl /GATB2 /GATB3 /GAT32

; Set PPIl address read
; Word access
; Begin valid cycle

/w.R /A6 /AS A4

/BE3 /BE2 BEl BEO
CYC
CMD
/CMD

/CYC
/BEl
CYC

; end cycle
; Byte access
; Begin cycle

CMD
/CMD

/CYC

; end cycle
; Write access
; Begin cycle

w.R

CYC
CMD
/CMD

/CYC
/A4
CYC

; end cycle
; Set PPIO address
; Begin cycle

CMD
/CMD

; end cycle
; Word access
; Begin valid cycle

/CYC
BEl
CYC
CMD
/CMD

/CYC
/w.R BE3 BE2
CYC

; end cycle
; Dword access read
; Begin valid cycle

CMD
/CMD

/CYC
A6 AS
CYC

; end cycle
; Set invalid address read
; Begin valid cycle

CMD

/CMD

/CYC
/BE3 BE2 BEl /BEO
CYC

; end cycle
; Set invalid byte enable
; Begin valid cycle

CMD
/CMD

/CYC

; end cycle

5-219

infel

Ap·433

PAIASM SIMULATION, V2. 23 - MARKET RELEASE (2-1-88)
(C) - COPYRIGHT MONOLITHIC MEMORIES INC, 1988
PAIASM SIMULATION SELECTIVE TRACE LISTING
Title
Pattern
Revision

U15

Author
Conpany

ERIK STEEB
INTeL Cor,poration

1.01

Date

5/24/89

IODCD PAL

PAL22V10

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ENHANCING SYSTEM PERFORMANCE WITH
THE MULTIBUS® II ARCHITECTURE

Although the MULTIBUSI!) II architecture can accommodate systems with a wide range of performance, systems
that take advantage of its multiprocessing capabilities can
achieve new performance levels while maintaining reasonable price/performance ratios. Today, multiprocessing provides an easy path to increased functionality and processing
power largely because of the availability of inexpensive
.
memory and CPUs.

This product brief will discuss the MULTIBUS II multiprocessing capabilities and their user benefits. The eapabilities include:

The low cost of high-performance microprocessors and
RAM chips has drastically altered the cost dynamics of
systems design. The material cost ofa CPU and its memory are typically a small portion of the total system cost,
in sharp contrast to mini and mainframe computers where
the cost of the CPU and memory is the majority of system
cost. The decreased cost factor means today' s designer can
optimize a system's price/performance by dedicating a
CPU to each function in the system.

Higher Performance Through
Multiprocessing

• A 'high-speed local environment
• An efficient burst transfer capability
• A hardware-based message passing facility

The key to high performance in multiprocessing systems is
allowing all of the processors· to run concurrently in their
own private environments. For this to occur, each functional module must contain its own CPU, memory and
110 resources. It also means that the system bus is primarily used for passing commands and data between
modules.
A system using this approach might consist of a host processing board and intelligent disk controller, a terminal
concentrator and LAN controller boards (Figure 1). Each

Figure 1. Functional Partitioning is the Distribution of CPU,
Memory & I/O Resources to Support Different Functions in a System

5-221

functional module would contain the resources required to
perform its assigned function. Further. each module would
operate over its own private local bus which is decoupled
from the system bus. This enables the modules to operate
concurrently with each other and leaves the system bus open
for communication between the intelligent modules.

and a local memory bus extension. The MULTIBUS II
board form factor is the Burocard Standard 233mm by
220mm (9.l"X9.0"). chosen because it allows most functional modules to completely fit on one board. This factor
is critical to system performance because on-board
resources can be optimized to run at their full potential
without impacting the system bus. A smaller bo~rd size
would force a particular function onto multiple boards
with a resulting decrease in performance.

High-Speed Local Environment Optimizes
On-Board Resources
In multiprocessing systems. performance is optimized

Burst Transfers

when all execution code and data is accessed in a local
environment. The most important performance factors in
a local environment are the CPU clock speed. the number
of CPU clocks per instruction. the CPU instruction set.
and the number of memory wait states. While the CPU
choice dictates the CPU performance factors. the bus
architecture can assist in providing a good CPU-memory
and 1/0 environment.

A key development to optimizing the iPSB bus for multiprocessor communications is the high-speed burst transfer
capability. Since address information is transferred over
the bus only once for the entire burst. performance is
greatly enhanced.
The synchronous handshake capabilities of the iPSB
bus nearly double the speed of burst transfers compared
to traditional asynchronous handshakes (Figure 2). Burst

The MULTIBUS II architecture provides a high-speed local
environment through its moderate size board form factor

TRADmONAL ASYNCHRONOUS HANDSHAKE

FOR EACH DATA TRANSFER
IPSI SYNCHRONOUS HANDSHAKE
ADDRESS

DATAl

DATA <

DATAl

ADDRESS/DATA r---,'-_LL..--'----------'lLJr--'----_.lL...--'-_.LL..Jr--'--_.....
COMMAND
REQUESTOR READY

REPLIER READY

ACTIVE (LOW) INDICATES

~=~~~~::::;~=-it----1r----1r----/;;:REOUESTING
COM

PROVIDED VALID
OATA
BOARDNAS
DURING nMe WINDOW

I ----U--,L..-\:-1rt---::Z::~1t~:::::=~tt---~/ ACTIVE (LOW) INDICATES
IL-.:~u.+-==::::i.t===:fI.-----,L THE
IIEPLYING
BOAIID
HAS
ACCEPTED
DATA
DURING
nMEWINDOW

END OF SLOCK 1----H----~If'£----_fF----t+--__,
XFEII

ACTIVE (LOW) INDICATES
LAST OATA IN BLOCK
TRANSFER

~ TWO CLOCK EDGE TIIANSITIONS REQUIRED

CENTRAL CLOCK

FOil EACH DATA TRANSFER

SIGNAL VALID TillE WINDOWS

Figure 2. iPSB Synchronous Handshake Compared to Asynchronous Handshake

5-222

transfers allow boards to transfer blocks of data over
the iPSB bus at speeds up to 40 Mbytes/s. This speed
approaches the limit of what can be expected from TIL
technology when propagation across a 20-slot backplane
is required.
In the iPSB bus. a burst transfer consists of one address
clock followed by multiple data transfers. The receiving
board takes care of actual memory location placement
(ie .• aut~-increments the memory address. as necessary).
The actual speed of the burst transfer will depend on the
abilities of the communicating boards. For example. burst
transfers from an intelligent board to dual-port memory
will typically be only marginally faster than single-cycle
writes. due to the long access times from the system bus
side of dual-port memory boards.

various manufacturers will all be able to communicate
compatibly at tremendous speeds.
Message passing. as defined in the MULTIBUS II protocol. allows modules to communicate directly. In other
words. one module sends a message (data) over the iPSB
bus to the address of another module. This differs from
the normal CPU functions of reading or writing only
from memory or 1/0..
Since conventional CPUs do not contain facilities to perform direct CPU-to-CPU communication. additional hardware logic is required. The hardware can be thought of as
a coprocessor to the primary CPU. e.g .• a coprocessor that
adds the function of direct module-to-module communication at speeds many times that which the primary CPU
could perform. The coprocessor logic for message passing resides in the bus interface.

To achieve the true performance benefits of burst transfers. each board needs the ability to send and receive small
bursts at the full bandwidth of the system bus. This can be
accomplished by bus interface logic containing high-speed
buffers and the ability to format and send 32-bit-wide data
bursts.

An example best illustrates how message passing works
(Figure 3). Assume Board A wants to send 1 Kbyte of
data to Board B. First. the CPU on Board A would instruct
its message passing unit to send 1 Kbyte of data (with the
assistance of a DMA device). beginning at a particular
location in local memory. to Board B. Next. the message
passing coprocessor on Board A takes over so the CPU

In the MULTIBUS II architecture. the interface bus logic
to the iPSB is defined with burst capability in a messagepassing scheme. This ensures that boards developed by

ISBC' 3881100

ISSC' 318/100

2.
IPSB
t. OM" LOADS MPC (MESSAGE PASSINO COPROCESSORI
2. MPC CREATES U-8YTE PACKETS TO SEND OVEATHE IPSI IIJIC ON.cHIP
DOUIU 32-IVTE IUFFERING LETS IT 8E SENDING SIMULTANEOUSLY WITH
MORE DATA HING LOADED
3. DMIt. UNLOADS UPC. DOUBLE AICEIVE BUFFERS LET THE MPC BE
REClIVING SIMULTANEOUSLY WITH DATA IEtHO LOADED

BUS UTILIZATION'

I. LOCAL BUS"
2.IPS8
3. LOCAL BUSl2

• NOTE. TRANSFER TIMES ARE BASED ON ISBC' :1111100 IOARD PERFORMANCE

Figure 3. A Message Passing Example

5-223

Summary

can perform other processing. At this point, the DMA
device loads the data into the message pas)ing coprocessor
on Board A. Once enough data has been loaded (typic8Ily
32 bytes), the coprocessor arbitrates for the bus and sends
the first packet of data as a burst transfer to the messagepassing logic on Board B.

Five important performance benefits result from the
MULTIBUS multiprocessing capabilities and specifically from hardware-assisted message passing. First, all
single-cycle memorylIO transfers can be designed to occur
in local CPU environments. These environments are optimized for single-cycle transfers over their local memory
buses and usuidly run at few or no wait states, compared
to substantial wait.state delays over a system bus.

While the message passing logic on Board B is unloading
the first packet out of its high-speed buffers into local RAM,
the message-passing logic on Board A is reading the next
piece of data into its high-speed buffers. Meanwhile, the
system bus is free of traffic and available for another pair
of boards to communicate over.

Second, transfers over the iPSB bus can be done as burst
transfers between message-passing logic containing highspeed buffers, thereby transferring data at the maximum
bus data rate. Third, the iPSB bus is not in use between
data packets and is available for other traffic. Fourth,
each CPU does not need direct access into the other
board's local environment. That is, no dual port memory
(which is slower than single port memory) is required.
And fifth, each CPU is available to process other tasks
while the data transfer is occurring.

The message-passing logic on Board A continues to build
and send small packets of data to Board B's message-passing logic, and Board B continues to unload this data into
its local memory until the entire 1 Kbyte has been transferred. At the completion of the transfer, the messagepassing logic on both boards interrupts their respective
CPUs to notify them that the transfer is complete.

5·224

INCREASING SYSTEM RELIABILITY WITH THE
MULTIBUS® II BUS ARCHITECTURE
System reliability is more than just mechanical factors
like Eurocard and DIN connectors. It involves many
design factors often overlooked in traditional buses. The
MULTIBUSn bus architecture addresses the problem of
system reliability not only from a mechanical point of
view, but from protocol and electrical factors as well.
This product brief will discuss how the following
MULTIBUS n features resolve specific reliability problems while enhancing overall system reliability:

into lOOns increments with signals sampled at the end of
each period. This method avoids looking at the signal
while transitions caused by reflections and crosstalk are
occurring. Therefore, signals are vulnerable only during
the small sampling window.
Figure 1 shows the iPSB timing with the lOOns period
divided into three intervals: driver timing, bus propagation, and receiver timing. The 40ns driver timing interval
takes into account driver logic delays and the capacitive
loading for a maximum oqo loads spaced over 16.8
inches.

• Synchronous Timing
• Bus Parity
• Protocol Error Handling
• Bus Timeout
• Power Sequencing
• Eurocard/DIN Connectors
• Front Panel Design
• Backplane Design

INCREASING ELECTRICAL RELIABILITY

,..

Synchronous Timing for Enhanced Noise
Immunity

40ns

I 30ns 30nsl
• .. ·I"~I

,..

WINDOW

Traditional buses, such as MULTIBUS I and VME, are
based on asynchronous timing where the edges or transitions of the bus-control signals cause the bus to perform
its functions. Unfortunately, edge-sensitive ti!lling is susceptible to external disturbances and noise. If noise causes a
signal to look as though it made a transition, the transition
is misinterpreted and a failure results.
Figure 1. iPSB Timing, Showing Syncbr~Dous Sample
Driving Stable Data Window

The MULTIBUS n architecture addresses this problem by
using synchronous sampling of all signal lines. Both the
MULTIBUS n Parallel System Bus (iPSB) and the Local
Bus Extension (iLBX'" n bus) employ synchronous sampling for enhanced noise immunity. The iPSB serves as a
good example of the benefits of synchronous sampling.

The bus propagation interval accounts for 25ns of signal
transit time and 5ns of potential clock skew. A signal traveling on the backplane creates reflections on itself and crosstalk on other signals. The signal transit time allows the
signai to propagate down and back on the backplane. It
also allows time for crosstalk to subside. This guarantees
that the signals have stabilized in spite of distance and
interference from other signals.
-

In the iPSB bus, all signaIs (address, data, control, and
arbitration) are driven and sampled with respect to a 10
MHz bus clock. The 10 MHz clock breaks the bus activity

5·225

The receiver interval consists of a· 30ns receiver setup
time plus 5ns of hold time which extends into the next
cycle. This interval is the time the signal is stable prior to
sampling on the falling edge of the clock.

Guaranteed Electrical Compatibility
Synchronous sampling also has a less obvious benefit guaranteed electrical compatibility among boards. The
lOOns timing of the iPSB is based upon a worst-case
environment of 20 boards over a backplane length of
16.8 inches (0.8 inch separation). All derating for loading,
voltage margin, and skew is included. Thus, any number
of boiIrds, up to 20, are guaranteed to work together.

Thus, the MULTmUS n parallel bus timing creates a ,
65ns interval (driver timing plus bus.propagation) when
the bus is completely immune to noise or external disturbances. That means during 65 % of the time interval, noise
causing a transition or level change is simply ignored. It
is only during the 35ns receiver setup and hold interval
that the bus timing is vulnerable to noise. During this interval, however, the bus contains parity protection (to be
discussed in another section).

Electrical compatibility is much harder to achieve in
asynchronous buses. Because they are edge-sensitive,
asynchronous boards are naturally susceptible to changes
in signal edge rates and timing. When the number of boards
in a system change, edge rates and timing also change, in
some cases adversely affecting system reliability.

Comparable Performance at Higher
Speeds

The synchronous nature of the bus moves the point of
synchronization to the local bus of each board. When two
asynchronous CPUs communicate, synchronization between
them occurs between each CPU and its interface. This provides a. better electrical environment for dealing with
reliability problems caused by metastability.

A common complaint about synchronous buses is that fixed
time increments limit performance compared to asynchronous buses. This may be true at slower bus clock speeds.
However, at 10 MHz the differences diminish. If both an
asynchronous and a synchronous bus use similar TTL technology for the bus drivers and receivers over the same
backplane length, they possess roughly the same bus timing. In other words, the driver timing, bus propagation,
and receiver intervals of both buses will be approximately
the same with nearly equal performance. However, as
we've seen, a synchronous bus offers a significant
improvement in system ~liability that easily justifies
its use.

Bus Parity Versus Memory Parity
At this point, it is important to distinguish between BUS
parity and MEMORY parity. (See Figure 2.) Both allow
the detection .of errors. Memory parity protects data while
it is resident on a memory board. Bus parity, on the other
hand, protects address, control, and data while in transit
on the bus. In a sense, one complements the other in reliable systems. In both cases, it is possible to handle errors
.
via retry or other mechanisms.

MEMORY
DATA BYTE

I 1IIIIIIIpi

I
I

MEMORY
LOGIC

BUS INTERFACE
WIPARITY

ADDRESS
DATACONTAOL

, ,.
I

I---

PARITY BIT STORED WITH
DATA TO PROTECT DATA
WHILE STORED

MEMORY LOGIC CHECKS!
ADOS PARITY WHEN
ACCESSED OR STORED

BUS'INTERFACE ADOSICNECKS
PARITY FOR EACH TRANSFER
ON BUS

WITHPAAITY

Figure 2. Parity Protects Address Data and Control from Errors which could he Incurred on the iPSB Bus

5-226

Bus parity in the MULTIBUS II architecture provides
another level of electrical reliability by protecting me bus
from noise and external disturbances during the receiver
timing interval. It also protects the bus from failed interface components.

requested operation. As with other board-to-board errors,
the requesting board many retry with another request.
The last kind of error, called a negative acknowledge
error, occurs during a message transfer when resources
are not available in the receiving board. This is used for
flow control in the MULTIBUS II message passing protocol, a queue-based data movement protocol. Negative
acknowledge errors instruct the requesting board to retry
the operation at a later time, giving the replying board
time to process the data in its queue.

On the iPSB bus, the board driving the bus generates bus
parity. Address and data lines use byte parity, while controllines use nibble (4-bit) parity. All receiving boards
check parity during the receiver timing sampling interval.
If an error is detected, the BUS ERROR line is activated.
This stops activity on the bus and puts the bus int~ a predefined known state.

Bus Timeout

At this point, the system designer has a number of options:
retry the transfer, swap in a hot spare, log the error, ignore
it, or shut down the system gracefully. Which option he
chooses depends on his specific system requirements.
Basically, the protocol gives him the opponunity to
evaluate the situation and take appropriate action.

Another protocol reliability feature in the MULTIBUS II
architecture is the BUS TIMEOUT monitor in the Central
Services Module (CSM). If a bus transfer fails to complete
within a specified time (e.g., a failed board), the CSM,
which monitors all bus activity, activates the BUS TIMEOUT line. This stops all bus activity and places the bus in
a predefined known state for recovery. At this point, the
error is logged and normal bus activity can resume. As an
added feature, designers may define their own timeout
error handling policy.

PROTOCOL RELIABILITY
Board-to-Board Error Indications
Not all errors occur because of noise or component failure.
Sometimes they occur when one board asks another to do
something it is not capable of doing. Although traditional
buses typically ignore these kinds of errors, they can cause
system failure just as noise can. The MULTIBUS II architecture offers a solution.

POWER SEQUENCING
The iPSB bus protocol also contains a mechanism for
orderly handling of power-up and power-down sequencing. For normal power on/off and unexpected power failures, timing of the RESET, DCLOW, and PROTect signals
coordinate the sequencing. The combination of the RESET
and DCLOW lines signal whether the power-up operation
is a warm or cold start of the system.

In the iPSB bus protocol, when one board cannot perform
the request, it simply informs the requesting board and allows it to attempt a retry. Five types of error indications
are supponed: data, transfer width, continuation, notunderstood, and negative acknowledge.

Once the system is running, the DCLOW signal (driven
by the CSM) is used to indicate imminent loss of DC
power (Figure 3). At this time, the system has a predetermined time to save state information. After that interval,

A data error indicates that the replying board has detected
an error with the requested data, for example a memory
parity error. Data transfer errors occur when the replying
board does not support the requested data width. For
example, the requesting board might ask for a 32-bit
transfer from an 8-bit device. After the replying board indicates the error has occurred, the requesting board can retry
the transfer with an 8-bit width.

DCLOW

Although the iPSB bus protocol allows for burst transfers
(multiple data cycles following one address cycle), not all
boards need to support this capability. If a requesting board
attempts a burst transfer with a board which does not suppon bursts, the replying board will return a continuation
error. The requesting board can recover by simply retrying
with the necessary address cycles.

POWER I

SYSTEM

FAIUNG I

STOPS

~'----+--I

PROT - - - - ; . - - - - - - . .

~,'----I
I

TIME FOR SYSTEM TO SAVE
STATUS. DATA BEFORE
TOTAL POWER LOSS

Trying to write to a read-only memory board is a good
example of a transfer-not-understood error. This type of
error occurs when the replying board does not support the

Figure 3. Power Failure Control Lines

5-227

the CSM activates the PROTect line which prevents transitions on bus lines from affecting the system during
power loss.

blade. This connector approach offers advantages over the
board-edge style connectors. Among them are tighter
dimensional tolerances, reduced sensitivity to vibration,
improved protection from environmental contaminants, and
a larger number of cycles for insertion and removal.

MECHANICAL RELIABILITY

FRONT PANEL SYSTEM

The MULTIBUS II mechanical specification is based upon
the Eurocard form factor and DIN connectors. However,
unlike traditional bus architectures, it goes beyond these
mechanical standards with a front panel design that helps
the system designer solve EMI (Electro-Magnetic Interference) and ESD (Electro-Static Discharge) problems.

The MULTIBUS II front panel system (Figure 4), while
dimensionally compatible with standard Eurocard front
panels, offers several important advantages.
(Note thai while this front panellechnology is different from normal

Eurocard pracllce. the dimensioning IS such lhal MULI/BUS II boards
fit in any slandDrd Eurocard packizging )

Eurocard and DIN Connectors

Standard Eurocard front panels make it difficult to comply
with EMI and ESD regulations withoui the use of additional
shielding. Adjacent front panels form small, narrow slits
between boards which function like a slot antenna at some
frequencies. Through these narrow slits, EMI can enter or
exit the system and additional shielding is usually required.

The Eurocard family of mechanical specifications is noted
for its high reliability in rugged and industrial environments. The MULTIBUS II specification calls out the twoconnector 233mm by 220mm and single-connector lOOmm
by 220mm size boards. The two connector board contains
almost the same board area as the 6.75 by 12 inch MULTIBUS I board. That is, it is large enough to allow the implementation of single-board computers with 110, CPU, and
memory onboard, even for 32-bit CPUs.

To solve this problem, the MULTIBUS II front panel is
U-shaped. From an EMI point-of-view, this makes the
front panel electrically thicker. While the size of the slit
between adjacent boards is the same as the standard Eurocard front panel, the electrically thicker front panel attenuates EMI which satisfies FCC EMI regulations and
protects the system from external EMI.

The DIN 41612 (also known as IEC 603.2) connectors are
96-pin two-piece connectors where each pin consists of a
blade mating with two contact points on each side of the

DIN
CONNECTORS

RETAI~~:~~ - - f f h...."\

EJECT~~~

LABELING
----"""-

Figure 4. MULTIBUS II Front Panel System

5-228

The U-shaped front panel also adds structural rigidity to
the board and has captive retaining screws for securing
the board to the system. Shielded I/O connectors located
through the front panel eliminate the need for intermediary
cables and connectors. In addition, the front panel is at
chassis ground for protection against static discharge.

ground planes provide for good power distribution. Moreover, since they are in between each signal layer, they
reduce the opportunity for crosstalk due to coupling
between the signal layers.
On each signal layer, signal lines are laid out identically
to minimize signal skew across the backplane. To control
reflections, each signal line is passively terminated.

BACKPLANE DESIGN

Both power and ground connections are evenly distributed
across the connectors with 9 pins allocated for + 5 volts
and 15 for ground providing ample current and good
ground return paths.

Designed for reliability, the iPSB bus backplane consists
of six layers - three signal layers sandwiched between
three power and ground planes (Figure 5). The power and

SUMMARY

n
r----l

SIGNAL LAYER
(CONNECTOR SIDE)

Because the MULTIBUS II architecture addresses the problems of electrical, protocol and mechanical reliability, it
is superior to traditional buses in achieving overall system
reliability. Besides the mechanical reliability of its Eurocard form factor, DIN connectors, and backplane design,
the MULTIBUS II electrical protocol is highly immune to
noise and external disturbances because of its synchronous
sampling and bus parity. In addition, the agent error capability catches common operational errors. Other operational
concerns such as bus time-out and power sequencing are
fully specified.

InI

GROUND PLANE 11

INTERNAL SIGNAL LAYEn
POWER PLANE

GROUND PLANE 12

SIGNAL LAYER SOLDER SIDE

Figure S. Backplane Design

5-229

iSBXTM Expansion Modules

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iSBXTM 279* DISPLAY SUBSYSTEM

HIGH-SPEED GRAPHICSIWINDOWING FOR iRMX® " SYSTEMS
The iSBX® 279 is a complete graphics subsystem designed to provide users of Intel's
iRMX II real-time systems with advanced interactive graphics functions. Based on Intels
82786 Display Processor, the iSBX 279 efficiently off-loads bitmap and window
manipulation from the application CPU, preserving real-time system performance. Highspeed windowing, ASCII terminal emulation with system console support, and powerful
drawing commands are provided in a convenient system expansion package. Complete
software support, including iRMX II Device Driver, Application Interface Libraries for
C-286 and PLlM 286, and loadable fonts, provides a high-level, network transparent
interface, allowing application portability across Intels real-time platforms and shortening
application development time.

FEATURES:
•
•
•
•
•
•
•

Intel 82786 Display Processor
iRMX II Operating System Device Driver
High-Level Language Interface
System Console Support Kits
Windowed User Interface
Terminal Emulator
Standard Graphics Command
Interpreter
• Network Transparent Graphics Protocol

infel'---------September, 1989
Order Number 280667-001

c Intel Corporal1on 1989

6-1

FEATURES
INTEL 82786 DISPLAY PROCESSOR

TERMINAL EMULATOR

The Intel 82786 Display Processor is used to provide
nearly instantaneous'window manipulation. Together
with the iSBX 279 firmware and iRMX II software, this
allows multiple overlapping windows displaying
graphical information or terminal sessions to be
presented simultaneously.

The terminal emulator allows existing applications to
run in a window without modification. The terminal
emulator is compatible with the iRMX II Human
Interface, the AEDIT text editor, iRMX Virtual Terminal
software, and other terminal oriented programs that
can be configured to operate with a smart CRT. By
using the virtual terminal capability, it is possible to
access any host on an OpenNETTM network from a
single display.

iRMX /I OPERATING SYSTEM DEVICE
DRIVER
The iRMX II Interactive Configuration Utility provides
the screens needed to configure the iSBX 279. The
device driver is provided as part of the iSBX 279
upgrade kit. The device driver manages the deVice
interface and performs 1/0 on behalf of application
requests through devicelfile connections in the
iRMX II lOS. The device driver is compatible with
iRMX II Terminal Support. This speeds development,
by allowing the programmer to remain unaware of the
device interface, instead concentrating on the
application code needed for the target system.

HIGH-LEVEL LANGUAGE INTERFACE

STANDARD GRAPHICS COMMAND
INTERPRETER
The graphics command interpreter is an
implementation of the Computer Graphics Interface
(CGI), providing an interface that is consistent with
current ISO-CGM and ANSI-CGI standardization
efforts, while extending thiS Interface to include
window and bitmap manipulation functions. The
interface is fully compatible with Intel's existing iVDI
720 R1.8 interface providing a direct upgrade for
iSBC 186/78A applications.

NETWORK TRANSPARENT GRAPHICS
PROTOCOL

Application interface libraries are provided for C-286
and PLiM 286. The application interface is a rich set
of graphics and windowing primitives that provide
standard drawing functions with complete control of
bitmaps and windows. This allows the application
programmer to quickly begin writing sophisticate,d
real-time graphics applications using a portable
interface for iRMX II systems.

Using OpenNET it is possible to display images
stored on remote nodes, run interactive applications
from any node on the network, allow multiple
applications on several processors to share a single
display, and access other displays from a local
application processor. Network transparency allows
distributed applications to be controlled from a single
console.

SYSTEM CONSO/,.E SUPPORT KITS
The iSBX 279 is designed to be the system console
for iRMX II MULTIBUS® systems based on iSBC®
286/1X and iSBC 386/XX CPU's. EPROM's containing
System Confidence Tests, System Debug Monitor,
and Bootstrap Loader are provided to allow the iSBX
279 to operate as a system console.

WINDOWED USER INTERFACE
The user may interactively' MOVE, RESIZE, PUSH,
POp, and SELECT Windows using the mouse and an
easy-to-use menu provided for this purpose. Several
terminal sessions and interactive graphics
applications can be'managed from a single console.
Window and bitmap manipulation is performed locally
by the iSBX 279, allowing complex user-interface
operations to proceed in parallel with time-critical realtime tasks on the host-CPU.

6-2

INTEL QUALITY AND RELIABILITY
The components of the iSBX 279 subsystem are
designed and manufactured in accordance with
Intel's high quality standards. Quality is assured
through rigorous testing in our state-of-the-art
Environmental Testing Laboratory.

WORLDWIDE SERVICE AND SUPPORT
Intel provides support for repair or on-site service.
Development support options include phone support,
subscription service, on-site consulting, and customer
training.

SPECIFICATIONS
Display
640 x 480 Pixels
25M Hz Clock
60Hz Noninterlaced Frame Rate
31.5kHz HOrizontal Rate
Up to 256 Colors from Palette of 16.7 Million'

Memory
1 Megabyte Bitmapped Memory
Bitmap Depths of 1,2,4, or 8 Bits

Interfaces Supported

Physical Characteristics
~19.05cm.

IBM2 PC/AT' Keyboard (or compatible)

Width:

PC-MOUSE (or compatible) locator device

Length: 3 15 In

=800cm

NEC MuitiSync4 Analog-RGB MOnitor (or compatible)

0.80 In.
Height:
1.14 in.

=2.03 cm.
=2.89 cm.

ISBX 279 Only
With ISBC Host

Weight: 6.0 oz.

=170.1 gm.

ISBX 279 Only

8-bIt SBX Bus Interface (all Signals TTL compatible)

Electrical Requirements

7.5 In

Environmental Requirements

+ 5 VDC ± 5% @ '" 3.0 A

Operating Temperature:

+12 VCD ±5% @ '" 0.025 A

Storage Temperature:

-40°C to + 75°C

-12 VDC +5% @ '" 0.025 A

Humidity:

0% to 95%, non-condensing

OOC to 55°C @ 200 LFPM mimlnum air flow

ORDERING INFORMATION
Order Code
SBX279
SXM2791286K
SXM2791386K

Description
Display Subsystem (Board Only)
Complete iSBC 286/1 X System Upgrade (Includes SBX279)
Complete iSBC 386/XX System Upgrade (Includes SBX 279)

Note: iRMX " must be purchased separately. Kits include all software, firmware, and hardware needed to
begin using the iSBX 279 Display Subsystem immediately. Software Royalty included in each iSBX 279.

lSee the RGI279 Product Release Notes for restrictions on Window size/placement when displaYing 256 colors
218M IS a registered trademark of International BUSiness Machines, Inc
3PC/AT IS a trademark of International BUSiness Machines, Inc

4MultiSync

a trademark of NEe

6-3

ISBXTM 217C* %-INCH TAPE DRIVE
INTERFACE MULTIMODULETM BOARD
• ISBXTM Bus Module Provides Tape
Backup Capability for ISBC$ 215 ,
Generic Winchester Controller
• Conflgurable to Interface with up to
Four QIC-02 Compatible or 3M HCD-75
Compatible Tape Drives
• Implements the QIC-02 with Parity
Streaming Tape Interface Standard

• Supports Transfer Rates of 90K, 30K or
17K Bytes per Second Depending on
Tape Speed
• Supported by IRMXTM 86 and XENIX"
Operating Systems when Used on
. ISBC$ 215 Generic Winchester
Controller Board

• + 5 Volt Only Operation

The iSBX 217C %-Inch Tape Drive. Interface module is a member of Intel's family of IEEE 959 iSBX I/O
ExpanSion Bus products. This module is particularly useful for implementing cartridge tape back-up capability
directly on the iSBC 215 Generic Winchester Disk Controller via DMA. Jhe iSBX 217C bus board can also
provide a low-cost tape storage interface for any Intel single board computer, having an iSBX bus connector,
via' programmed I/O. The iSBX 217C module interfaces with up to four streaming tape drives. Typically, these
drives provide 20 to 45 megabytes of storage each. When used in conjunction with these drives and the iSBC
215 board, the module can transfer 20 megabytes of data from disk to tape in about fourteen minutes.
Alternatively, the iSBX 217C board can interface with up to four 3M Company HCD-75 compatible start/stop
tape drives, for those applications requiring access to individual data files on tape.

210817-1

·The iSB)(TM 217C is also man\lfactured under product code piSBXTM 217C by Intel Puerto Rico, Inc.
··XENIXTM is a trademark of Microsoft Corporation.

6-4

september 1989
Order Number: 210817-003

iSBXTM 217C

SPECIFICATIONS

Physical Characteristics
Width: 3.08 inches (7.82 cm)
Height: 0.809 inches (2.05 cm)
Length: 3.70 inches (9.40 cm)
Shipping Weight: 3.5 ounces (99.2 gm)
Mounting: Occupies one single-wide iSBC
MULTIMODULE position on boards

Compatibility
Host-Any iSBC signal board computer or peripheral controller with an iSBX connector. The iSBC 215
Generic Winchester Controller includes on-board
firmware to support the iSBX 217C under either the
iRMX 86 or XENIX Operating Systems. The firmware
on the iSBC 215A and iSBX 215B Winchester Controllers cannot support the iSBX 217C module.

Electrical Characteristics
I

Power Requirements:

Drives-Any QIC-02 or 3M HCD-75 interface compatible cartridge %-inch magnetic tape drive.

+ 5 VDC @ i.5A

Environmental Characteristics
Temperature: O°C to + 55°C (operating) @200 LFM;
- 55°C to + 85°C (non operating)

Transfer Rate

Humidity:

90K (one byte every 11 microseconds). 30K (one
byte every 33 microseconds) or 17K (one byte every
53 microseconds) depending on tape drive speed.

Up to 90% relative humidity without
condensation (operating); all conditions without condensation or frost
(non-operating)

Equipment Supplied

Reference Manual

iSBX 217C Interface Module
Reference Schematic

0146704- iSBX 217C Board Hardware Reference
Manual (NOT SUPPLIED)

Controller-to-drive cabling and connectors are not
supplied. Cables can be fabricated with flat cable
and commercially-available connectors as described
in the Hardware Reference Manual.

ORDERING INFORMATION
Order Code Description
SBX217C

, Nylon mounting bolts

6-5

Cartridge %-inch Tape Drive Interface

iSBXTM 218A *
FLEXIBLE DISK CONTROLLER
IEEE 959 iSBXTM Bus Compatible 8" or
• 5.25"
Floppy Diskette Controller
Module
Hardware and Software Compatible
• with
ISBX 218 Module
Most Single/Double Density
• Controls
and Single/Double Sided Floppy Drives
User Programmable Drive Parameters
• Allow
Wide Choice of Drives

Motor On/Off Latch Under Program
• Control
Drive-Ready Timeout Circuit for 5.25
• Inch
Floppy Drives
Phase Lock Loop Data Separator
• Assures Data Integrity
Read and Write on Single or Multiple
• Sectors
• Single + 5 Volt Supply Required

The Intel iSBXTM 218A Flexible Disk Controller module is a software and hardware compatible replacement for
the iSBX 218 module and provides additional features. The iSBX 218A module is a double-wide iSBX module
floppy disk controller capable of supporting virtually any soft-sectored, single/double density and single/double sided floppy drives. The controller can control up to four drives. In addition to the standard IBM 3740 and
IBM system 34 formats, the controller supports sector lengths up to 8192 bytes. The iSBX 218A module's wide
range of drive compatibility is achieved without compromising performance. The operating characteristics are
specified under user control. The controller can read and write either single or multiple sectors.

503810-1

·The ISBXTM 218A Is also manufactured under product code plSBXTM 218A by Intel Puerto Rico. Inc.

6-6

October 1881
Order Number. 50381Il-003

inter

iSBXTM 218A CONTROLLER

BLOCK DIAGRAM

FLEXIBLE
DISK
DRIVES

t
i

Jl CONNECTOR

I
I

FLEXIBLE DISK DRIVE INTERFACE LOGIC

'I'

,.
r---'\

r.I

LATCH
OPTIDNS

DMA
SIGNAL
GENERATOR

READ
WINDDW
GENERATOR

8272
FDC

'I'

TIMING
AND
PLL

IT'I'

READ
DATA
SHAPING

WRITE
PRECOMPENSATION

I""
I""

f--+

ADIIRESS, DATA, AND CONTROL BUS

ISBX-BUS

I
503810-2

Block Diagram of iSBXTM 218A Board

6-7

iSBXTM 218A CONTROLLER

SPECIFICATIONS

Equipment Supplied
iSBX 218A Controller
Reference Schematic
Controller-to-drive cabling and connectors are not
supplied with the controller. Cables can be fabricated with flat cable and commercially-available connectors as described in the iSBX 218A Hardware
Reference Manual.
Nylon Mounting Screws and Spacers

Compatibility
CPU-Any single board computer or I/O board implementing the iSBX bus interface and connector.
Deviee&-Double or single density standard (8")
and mini (5%") flexible disk drives. The drives may
be single or'double sided. Drives known to be compatible are indicated in the table to the right.
Standard (8")
Caldlsk
Remex
Memorex
MFE
Siemens
Shugart
Shugart
Pertee
CDC

Physical Characteristics

Mini (S%")

Shugart
143M
RFD4000
Shugart
SSO
Mieropolls
700
Pertee
FDD200-8 Siemens
SA8S0/800 Tandon
SA 860/810 CDC
FD6S0
MPI
9406-3

4S0/400
460/410
101S-IV
2S0
200-S
TM-100
9409
51/52/91/92

3.15 inches (8.0 cm)
0.83 inches (2.1 cm)
7.5 ounces (19.1 cm)
Length:
4.5 ounces (126 gm)
Weight:
Mounting: Occupies one double-wide iSBX MULTIMODULETM position on boards; increases board height (host plus iSBX board) to
1.13 inches (2.87 cm).

Width:
Height:

Diskette-Unformatted IBM Diskette 1 (or equivalent single-sided media); unformatted IBM Diskette
2D (or equivalent double-sided).

Data Organization and Capacity
Standard Size Drives
Double Density

Single Density

IBM System 34

Non-IBM

IBM System 3740

Non-IBM

Bytes per Sector

256 1 512 1 1024

20481409618192

128 1 256 1 512

10241204814096

Sectors per Track

1 15

Tracks per Diskette

Bytes per Diskette
(Formatted, per
diskette surface)

512,512
(256 bytes/ sector)
591,360
(512 bytes/sector)
630, 784
(1024 bytes/sector)

1 2

1 1

630,784

6-8

1 15

77
256,256
(128 byte/ sector)
295,680
(256 bytes/sector)
315,392
(512 bytes/sector)

1 2

1 1

315,392

inter

ISBXTM 218A CONTROLLER

Electrical Characteristics
Power Requirements: + 5VDC

Reference Manual
145911- iSBX 218A Flexible Disk Controller Hard-

1.7A max.

ware Reference
PLIED).

Environmental Characteristics

Reference manuals may be ordered from any Intel
sales representative, distributor office, or from Intel
Literature Department, 3065 Bowers Avenue, Santa
Clara, California 95051.

Temperature: O·C to +55· (operating); -55·C to
+ 85·C (non-operating).
Humidity:
Up to 90% Relative Humidity without
condensation (operating); all conditions without condensation or frost
(non-operating).

Drive Characteristics
Transfer Rate (K bytes/sec)

Manual (NOT SUP-

Standard Size

Mini Size

Double/Single Density

62.5/31.25

31.25/15.63

Disk Speed (RPM)

360

300

Step Rate Time
(Programmable)

1 to 16 ms/track in
1 ms increments

2 to 32 ms/track in
2 ms increments

Head Load Time
(Programmable)

2to 254 ms in
2 ms increments

4to 508 ms in
4 ms increments

Head Unload Time
(Programmable)

16 to 240 ms in
16 ms increments

32 to 480 ms in
32 ms increments

ORDERING INFORMATION
Order Code Description
SBX218A
Flexible Disk Controller

6-9

iSBXTM 311 *
ANALOG INPUT MUlTIMODULETM BOARD

•
•
•

Low Cost Analog Input Via iSBXTM Bus
Connector
8 Differential/16 Single-Ended, Fault
Protected Inputs
20 mV to 5V Full Scale Input Range,
Resistor Gain Selectable

(0 to +5V) or Bipolar (-5V to
• Unipolar
+ 5V) Input, Jumper Selectable
12-Bit Resolution Analog-To-Digital
• Converter
II! 18 KHz Samples Per Second

Throughput to Memory

The Intel iSBX 311 Analog Input MULTIMODULE board provides simple interfacing of non-isolated analog
signals to any iSBC board having an IEEE 959 iSBX I/O Expansion Bus connector. The single-wide iSBX 311
plugs directly onto the iSBC board, providing data acquisition of analog signals from eight differential or sixteen
single-ended voltage inputs, jumper selectable. Resistor gain selection is provided for both low level (20 mV
full scale range) and high level (5 volt FSR) signals. Incorporating the latest high quality IC components, the
iSBX 311 MULTIMODULE board provides 12 bit resolution, 11 bit accuracy, and a simple programming interface, all on a low cost SBX board.

280233-1

"The iSBXTM 311 is also manufactured under product code piSBXTM 311 by Intel Puerto RIco. Inc.

6-10

September 1989
Order Number: 280233-003

intJ

ISBXTM 311 BOARD

BLOCK DIAGRAM
ISBXTM 311 Analog Input MULTIMODULETM Board

HIOH
IMPEDANCE

BUfFER
AMP
•

'CHANNEL

ANALOG
INPUT

,">

'<,

INPUT
MULTI·
PLEXER

:~~~~'o--'ll'--

GAIN
SELECT

SAMPLE
&

SIGNALS

DATA
LINES

HOLD
AMP

OFFSET
ADJUST

•

INTR

OAIN
RESISTOR

• CHANNEL

INPUT
MULTI

START

PLEXER

CONVERSION

AND
CHANNEL
SELECTOR

LOGIC

280233-2

SPECIFICATIONS

Dynamic Error-±O.01S% FSR for transitions.

Inputs-8 differential. 16 single-ended. Jumper selectable.
Voltage Range-- 5 to + 5 volts (bipolar). 0 to + 5
volts (unipolar). Jumper selectable.

Gain TC (at Gain = 1): 30 PPM per degree centigrade (typical); 56 PPM per degree centigrade
(max).

Offset TC (In percent of FSRrC):
Galn-User-configurable through installation of two
resistors. Factory-configured ,tor gain of X1.

Gain
1
5
50
250

Resolutlon-12 bits over full scale range (1.22 mV
at 0-5V, 5 p.V at 0-20 mY).
AccuracyGain
1
5
50
250

Offset
0.0018
0.0036
0.024
0.116

Offset Is measured with user-supplied 10 PPMI"C gain resistors installed.

Accuracy at 2SoC
±0.035% ± 1!z LSB
±0.035% ± 1!z LSB
± 0.035% ± 1!z LSB
±0.035% ± 1!z LSB

Input Protectlon-±30 volts.
Input Impedance-20 MO (minimum).
Conversion Speed-50 ms (nominal).

NOTE:

Common Mode Rejection Ratl0-60 db (minimum).

Figures are in percent of full scale reading. At any fixed
temperature between 0" and 50·C, the accuracy Is adjustable to ± 0.035% of full scale.

sample and hold-sample time 15 ms.
Aperture-hold aperture time: 120 ns.

6-11

intJ

ISBXTM 311 BOARD

ConnectorsInterface

Environmental Characteristics

Pins
(aty)

Centers
In
cm

Jl 8/16
Channels
Analog

Mating
Connectors
3m 3415-000

0.1

Operating Temperature:

o· to 80·C (32· to 140"C)

Relative Humidity:

to 90% (without condensation)

0.254

Reference Manuals
142913- iSeX 311 Analog Input MULTIMODULE

Physical Characteristics

Board Hardware Reference Manual (order separately)

Width: 9.40 cm (3.7 inches)
Length: 6.35 cm (2.5 inches)

ORDERING INFORMATION

Height: 2.03 cm (0.80 inch) MULTIMODULE board
only

Order Code
SBX311

2.82 cm (1.13 inches) MULTIMODULE and
iSBC board
Weight: 68.05 gm (2.4 ounces)

Electrical Characteristics (from Isex
connector)
vee = ±5 volts (±0.25V). Icc = 250 mAmax

Vdd = +12 volts (±0.6V). Idd = 50 mAmax
Vss = -12 volts (±0.6V). Iss = 55 mAmax

6-12

Description
Analog Input MULTIMODULE Board

iSBXTM 328*
ANALOG OUTPUT MULTIMODULETM
BOARD
•

Low Cost Analog Output Via iSBXTM
Bus Connector

•

12-Bit Resolution

•

8 Channel Output, Current Loop or
Voltage in any Mix

0.035% Full Scale Voltage Accuracy
@ 25°C

•

4-20 mA Current Loop; 5V Unipolar or
Bipolar Voltage Output

Programmable Offset Adjust in Current
Loop Mode

The Intel iSBX 328 MULTIMODULE board provides analog signal output for any intelligent board having an
IEEE 959 iSBX I/O Expans'ion bus connector. The single-wide iSBX 328 plugs directly onto the host board,
providing eight independent output channels of analog voltage for meters, programmable power supplies, etc.
Voltage output can be mixed with current loop output for control of popular 4-20 mA industrial control elements. By using an Intel single chip computer (8041) for refreshing separate sample-hold amplifiers through a
single 12 bit DAC, eight channels are contained on a single SBX board for high density and low cost per
channel. High quality a~alog components provide 12 bit resolution, and slew rates per channel of 0.1 V per
microsecond. Maximum channel update rates are 5 KHz on a single channel to 1 KHz on all eight channels.

280234-1

'The iSBXTM 328 IS also manufactured under product code plSBXTM 328 by Intel Puerto Rico, Inc.

6·13

September 1989
Order Number: 280234-002

ISBXTM 328 BOARD

BLOCK DIAGRAM
iSBC@) 328 Analog Output MULTIMODULETM Board Block Diagram
aUFFER

r -_ _C::":;ARENTA,:,VOlTAGE

AMPLIFIER

LOOP

DIGITAL TO
ANALOG
INTEL"

11041.

•

PLEKER

}

----v--

ANALOG'
OUTPUT
MULTI

CONVERTER
12·81T
RESOLUTION

~YOLTAGETO

AUP

•

CURRENT

ANALOG

OUTPUT
8 CHANNEL

UPI"

SAMPLEIHOLD

CAPACITOR
MULTIPLEXER CONTROL

DEMULTI·
PLEXER

280234-2

Single Channel
Update Rate
- 5 KHz
Eight Channel
Update Rate
- 1 KHz
Output Impedance- 0.1 n. Drives capacitive loads
up to 0.05 microfarads. (approx. 1000 foot cable)
Temperature
-0.005%l"e
Coefficient

SPECIFICATIONS
Outputs

Voltage Ranges

- 8 non-isolated channels,
each independently jumpered for voltage output or
current loop output mode.
- 0 to + 5V (unipolar operation)
- 5 to + 5V (bipolar operation)

Current Loop
Range

Conipllance
Voltage

4 to 20 mA (unipolar operation only)
Output Current - ± 5 mA maximum (voltage
mode-bipolar operation)
Load Resistance - 0 to 250n with on-board
iSeX power. 1000n minimum
with 30 VDe max. external
supply

Resolution
Slew Rate

Refresh and Throughput Rates··
Refresh 1 channel (no new data):
80 ,...s
Refresh all 8 channels (no new data):
650 ,...s
Update and refresh 1 channel with new
150 ,...s
data: firmware program 2
for each additional channel
130 ,...s
Update and refresh 1 channel with new
data: firmware program 1 or 3
200,...s
for each additional channel
155,...s
Update and refresh all 8 channels
1,050 ms
(all new data): firmware program 2
per channel of new data
50,...s
Update and refresh all 8 channels
(all new data): firmware program 10r 3 1,280 ms
per channel of new data
80 ,...s

12V using on-board iSeX
power. If supplied by user, up
to 30 VDe max
- 12 bits bipolar or unipolar
- 0.1 V per microsecond minimum

"AII times nominal

6-14

inter

iSBXTM 328 BOARD

AccuracyMode

Ambient
Temp

Accuracy

Voltage-Unipolar, typical
Voltage-Unipolar, maximum
Voltage-Unipolar, typical
Voltage-Unipolar, maximum

±
±
±
±

0.025% FSR
0.035% FSR
0.08% FSR
0.19% FSR

@25°C
@25°C
@0° to 60°C
@ 0° to 60°C

Voltage-Bipolar, typical
Voltage-Bipolar, maximum
Voltage-Bipolar, typical
Voltage-Bipolar, maximum

±
±
±
±

0.025% FSR
0.035% FSR
0.09% FSR
0.17% FSR

@25°C
@25°C
@0° to 60°C
@00to60°C

Current Loop, typical
Current Loop, maximum
Current Loop, typical
Current Loop, maximum

±
±
±
±

0.07%
0.08%
0.17%
0.37%

@25°C
@25°C
@0° to 60°C
@0° to 60°C

Connectors-

FSR
FSR
FSR
FSR

Environmental Characteristics

Interface

Pins
(Qty)

J1 8/16
channels
analog

Centers
In
cm

Mating
Connectors

Operating Temperature: 0° to 60°C (32° to 140°C)
Relative Humidity:
to 90% (without condensation)

3m 3415-000
0.1

0.254

Reference Manuals
142914- iSBX 328 Analog Output MULTI-MODULE
Board Hardware Reference Manual (Order Separately)

Physical Characteristics
Width:

9.40 cm (3.7 inches)

Length: 6.35 cm (2.5 inches)
Height: 1.4 cm (0.56 inch) MULTIMODULE board
only

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

2.82 cm (1.13 inches) MULTIMODULE and
iSBC board.
Weight: 85.06 gm (3.0 ounces)

ORDERING INFORMATION

Electrical Characteristics

Order Code
SBX328

vcc = ±5V (O.25V),
Voo

Icc = 140 mA max

= ± 12V (± 0.6V), 100
(voltage mode)

= 45 mA max
= 200mAmax
(current loop
mode

Vss = -12V (± 0.6V), Iss = 55 mA max

6-15

Description
Analog
Board

Output

MULTIMODULE

iSBX™ 350*
PARALLEL 1/0 MULTIMODULE™ BOARD
•

iSBXTM Bus Compatible I/O Expansion

•

Accessed as 1/0 Port Locations

•

24 Programmable 1/0 Lines with
Sockets for Interchangeable Line
Drivers and Terminators

•

Single + 5V Low Power Requirement

•

iSBX Bus On-Board Expansion
Eliminates MULTIBUS® System Bus
Latency and Increases System
Throughput

•

Three Jumper Selectable Interrupt
Request Sources

The Intel iSBX 350 Parallel I/O MULTIMODULE Board is a member of Intel's line of IEEE 959 iSBX I/O
Expansion Bus products. The iSBX 350 module provides 24 programmable I/O lines with sockets for interchangeable line drivers and terminators. The iSBX board is closely coupled to the host board through the iSBX
bus, and as such, offers maximum on-board performance and frees MULTIBUS system traffic for other system
resources. In addition, incremental power dissipation is minimal requiring only 1.6 watts (not including optional
driver/terminators).

280235-1

'The ISBXTM 350 IS also manufactured under product code piSBX™ 350 by Intel Puerto Rico, Inc.

6-16

September 1989
Order Number: 280235-002

ISBXTM 350 BOARD

SPECIFICATIONS
Parallel 110 Port Operation Modes
Mode of Operation

Port

Unidirectional

Lines
(qty)

Input

Output

Control

Bidirectional

Unlatched

Latched &
Strobed

Latched

Latched &
Strobed

X(1)

NOTE:
1. Part of Port C must be used as a control port when either Port A or Port B are used as a latched and strobed input or a
latched and strobed output port or Port A is used as a bidirectional port.

Parallel Interface Connectors

Word Size

No. of
Centera Connector
Interface Palrsl
Vendor
(In.)
Type
Pins

Data: 8 Bits

1/0 Addressing

Parallel 110
25/50
Conneclor

8255A-5 Ports

ISBX 350 Address

PortA
PortB
PortC
Control
Reserved

XOorX4
X10rX5
X20rX6
X30rX7
X8toXF

Parallel 110
25/50
Connector

0.1

Female

0.1

Female
Soldered

Vendor
Part No.

3415·0001

with Ears

GTE 6AD01251A1DD
Sylvania

NOTE:
Connector compatible with those listed may also be used.

Line Drivers and Teminators

NOTE:
The first digit of each port 1/0 address is listed as "X"
since it will change dependent on the type of host iSBC
microcomputer used. Refer to the Hardware Reference
Manual for your host iSBC microcomputer to determine the
first digit of the port address.

1/0 Drivers-The following line drivers and terminators are all compatible with the 110 driver sockets on
the iSBX 350.
Driver

7438
7437
7432
7426
7409
7408
7403
7400

1/0 Capacity
24 programmable lines (see Table 1)

Access Time
Read: 250 ns max.

Characteristic

I,OC
I
NI
I,OC
NI,DC
NI
I,OC
I

Sink
Current (mA)

48
48
16
16
16
16
16
16

NOTE:
I = Inverting, NI = Non-Inverting, OC = Open Collector

Write: 300 ns max.

Port 1 has 25 mA totem pole drivers and 1 kn terminators.

NOTE:
Actual transfer speed is dependent upon the cycle
time of the host microcomputer.

1/0 Terminators-220n/330n divider or 1 kn pull
up - user supplied.

Interrupts
Interrupt requests may originate from the programmable peripheral interface (2) or the user specified
1/0 (1).
6-17

inter

ISBXTM 350 BOARD

Physical Characteristics

Environmental

Width:
Length:
Height·:

Operating Temperature: O·C to

Weight:

7.24 cm (2.85 in.)
9.40 cm (3.70 in.)
2.04 cm (0.80 in.) iSBX 350 Board
2.86 cm (1.13 in.) iSBX 350 Board
Host Board
.
51 gm (1.79 oz)

·See Figure 2

+ 55·C

Reference Manual
9803191-iSBX 350 Parallel I/O MULTIMODULE
Manual (NOT SUPPLIED)

Electrical Characteristics

Reference Manuals may be ordered from any Intel
sales representative, distributor office or from Intel
Literature Department, 3065 Bowers Ave., Santa
Clara. California 95051.
'

DC Power Requirements

ORDERING INFORMATION

Power
Requirements

Conllgunlllon

+5@320mA

Sockets XU3, XU4, XU5, and XU6 empty (as
shipped).

+5V@500mA

Sockets XU3, XU4, XU5, and XU6 contain
7438 buffers.

+5V@620mA

Sockets XU3, XU4, XU5, and XU6 contain
iSSC 901 termination devices.

Order Code Description
SBX350

6-18

Parallel I/O MULTIMODULE Board

iSBXTM 488*
GPIB MUlTIMODUlETM BOARD

•
•
•

•

Complete IEEE 488·1978 Talker/
Listener Functions Including:
- Addressing, Handshake Protocol,
Service Request, Serial and Parallel
Polling Schemes

Software Functions Built into VLSI
Hardware for High Performance, Low
Cost and Small Size

t:a Standard iSBX Bus Interface for Easy
Connection to Intel iSBCTM Boards

Complete IEEE 488·1978 Controller
Functions Including:
- Transfer Control, Service Requests
and Remote Enable

II IEEE 488·1978 Standard Electrical

Interface Transceivers
II Five Volt Only Operation

Simple Read/Write Programming

The Intel iSBX 488 GPIB Talker/Listener/Controller MULTIMODULE board provides a standard interface from
any Intel iSBC board equipped with an IEEE 959 iSBX 1/0 Expansion Bus connector to over 600 instruments
and computer peripherals that use the IEEE 488-1978 General Purpose Interface Bus. By taking full advantage
of Intel's VLSI technology the single-wide iSBX 488 MULTIMODULE board implements the complete IEEE
488-1978 Standard Digital Interface for Programmable Instrumentation on a single low cost board. The iSBX
488 MULTIMODULE board includes the 8291A GPIB Talker/Listener, 8292 GPIB Controller and two 8293
GPIB Transceiver devices. This board represents a significant step forward in joining microcomputers and
instrumentation using industry standards such as the MULTIBUS® system bus, iSBX bus and IEEE 488-1978.
The high performance iSBX 488 MULTIMODULE board mounts easily on Intel iSBX bus compatible single
board computers.
A simple user programming interface for easy reading, writing and monitoring of all GPIB functions is provided.
This intelligent interface minimizes the impact on host processor bandwidth.

143580-1

·The iSBXTM 488 is also manufactured under product code piSBXTM 488 by Intel Puerto Rico, Inc.

6-19

September 1989
Order Number: 143580-002

ISBXTM 488 BOARD

BLOCK DIAGRAM
iSB~TM
DEVICE
FUNCTION

I
I

488 MULTIMODULETM Board Block Diagram

I
I

SBX
CONNE

c~1

BLK

82111A
TALKER
LISTENER

82112

"
L.....

CONTROLLER

DECODE

"
v

82112
BUFFER

I
I
A

~
A

YoDREss,
SELECT.
IOAIW

8MHz
CLOCK

DMA

~INTR

OPII

TRANSCEIVER
I SUPPORT
LOGIC

OPIB INTERFACE
FUNCnONS

"
-v

"
I

82113
XCVR

L--

DATA

t\.....
A

TRANSFER

....
82113
XCVR

MOMT.

"
SYSTEM
CONTROL

"'-'

JUMPER
LOGIC

1-----TALKER
LISTENER
ADDRESS

....

143580-2

Installation

GPIB Functions Supported
IEEE 488-1978 Functlons(1)

The iSBX 488 MULTIMODULE board plugs directly
onto the female iSBX connector available on many
Intel iSBC boards. The MULTIMODULE board is
then secured at one additional point with nylon hardware (supplied) to insure the mechanical security of
the assembly. -

SPECIFICATIONS
Physical Characteristics
Width: 3.70 in (0.94 cm)
Length: 2.85 in (7.24 cm)
Height: 0.8 in (2.04 cm)
Weight: 3.1 oz (87.8 gm)

Function

ISBXTM 488
Supported
IEEE Subsets

Source Handshake (SH)
Acceptor Handshake (AH)
Talker(T)
Extended Talker (TE)
Listener (L)
Extended Listener (LE)
Service Request (SR)
Remote Local (RL)
Parallel Poll (PP)
Device Clear (DC)
Device Trigger (DT)
Controller (C)

SHO, SH1
AHO,AH1
TO through T8
TEO through TE8
LO through L4
LEO through LE9
SRO, SR1
RLO, RL1
PPO, PP1, PP2
DCO through DC2
DTO, DT1
CO through C28

NOTE:

GPIB Data Rate*

1. For detailed information refer to IEEE Standard Digital
Interface for Programmable Instrumentation published by
The Institute of Electrical and Electronics Engineers, Inc.

300K bytes/sec transfer rate with DMA host iSBC
board

1978.

6-20

ISBXTM 488 BOARD

50K bytesls transfer rate using programmed 1/0
730 ns Data Accept Time
*Data rates are iSBX board maximum. Data rates
will vary and can be slower depending on host
iSBC board and user software driver.

Environmental Characteristics
Operating Temperature: O· to 60·C (32· to 140·F)
Relative Humidity:
Up to 90% R.H. without
condensation.

Reference Manual

Electrical Characteristics

143154- iSBX 488 GPIB MULTIMODULE Board
Hardware Reference Manual (not supplied).

DC Power Requirements: Vee = +5 VDC ±5%
Ice = 600 milliamps maximum

ORDERING INFORMATION

GPIB Electrical and Mechanical
Specifications

Order Code Description
SBX488
GPIB MULTIMODULE

Conforms to IEEE 488-1978 standard electrical levels and mechanical connector standard when purchased with the iSBC 988 GPIB cable.

6-21

iSBXTM 351*
SERIAL 1/0 MULTIMODULETM BOARD

•
•
•
•

IEEE959 iSBXTM Bus Compatible I/O
Expansion
Programmable Synchronous/
Asynchronous Communications
Channel with RS232C or RS449/422
Interface
Software Programmable Baud Rate
Generator
Two Programmable 16-Blt BCD or
Binary Timer/Event Counters

•
•
•
•
•

Four Jumper Selectable Interrupt
Request Sources
Accessed as I/O Port Locations
Low Power Requirements
Single + 5V when Configured for
RS449/422 Interface
ISBX Bus On-Board Expansion
Eliminates MULTIBUS® System Bus
Latency and Increases System
Throughput

The Intel iSBX 351 Serial I/O MULTIMODULE board is a member of Intel's line of IEEE 959 iSBX I/O
Expansion Bus compatible products. The iSBX 351 module provides one RS232C or RS449/422 programmable synchronous/asynchronous communications channel with software selectable baud rates. Two general
purpose programmable 16-bit BCD or binary timers/event counters are available to the host board to generate
accurate time intervals under software control. The iSBX board is closely coupled to the host board through
the SBX bus, and as such, offers maximum on-board performance and frees MULTIBUS system traffic for
other system resources. In addition, incremental power dissipation is minimal requiring only 3.0 watts (assumes RS232C interface).

280238-1

"The iSBlCTM 351 is also manufactured under product code piSBX™ 351 by Intel Puerto Rico, Inc.

October 1989

6-22

Order Number: 280236-002

inter

ISBXTM 351

SPECIFICATIONS
110 Addressing
1/0 Address for

1/0 Address for

an a-Bit Host

a l6-Blt Host

Chip Select

Function

XO.X2.X4
orXS

YO. V4. VB
orVC

B251A
USART

Write: Data
Read: Data

Xl. X3. X5
orX7

V2. VS. VA
orVE

MCSOI
Activated (True)

Write: Mode or Command
Read: Status

XBorXC

ZOorZB

B253 PIT

Write: Counter 0
Load: Count (N)
Read: Counter 0

X90rXD

Z20rZA

MSC11 Activated
(True)

Write: Counter 1
Load: Count N
Read: Counter 1

XAorXE

Z40rZC

Write: Counter 2
Load: Count (N)
Read: Counter 2

XBorXF

ZSorZE

Write: Control
Read: None

NOTE:
X = The iSBX base address that activates MCSO & MSCl for an B-bit host.
V = The ISBX base address that activates MCSO for a lS-bit host.
Z = The iSBX base address that activates MCSl for a lS-bit host.
The first digit. X. V or Z. is always a variable. since it will depend on the type of host microcomputer used. Refer to the
Hardware Reference Manual for your host microcomputer to determine the first digit of the 1/0 base address.
The first digit of each port 1/0 address is listed as "X" since it will change depending on the type of host iSBC microcomputer used. Refer to the Hardware Reference Manual for your host iSBC microcomputer to determine the first digit of the I/O
address.

Word Size

Serial Communications

Data-8 bits

Synchronous-5-8-bit characters; internal character synchronization; automatic sync insertion; even.
odd or no parity generation/detection.

Access Time

Asynchronous-5-8-bit characters; break character
generation and detection; 1. 1%. or 2 stop bits; false
start bit detection; even. odd or no parity generation/detection.

Read-250 ns max
Write-300 ns max
NOTE:
Actual transfer speed is dependent upon the cycle
time of the host microcomputer.

Interval Timer and Baud Rate
Generator
Input Frequency (selectable):
1.23 MHz ±0.1% (0.813 ,""S period nominal)
153.6 kHz ± 0.1 % (6.5 ,""S period nominal)

6-23

inter

ISBXi'M 351

Sample Baud Rate
8253 PIT(1) ,
Frequency (kHZ,
Software selectable)
307.2
153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76

8251 USAAT Baud Aat. (Hz)(2)
Asynchronous

Synchronous

+16
19200

36400

+64
4800
2400
1200
600
300
150
75

9600
4800
2400

1200

19200
9600
4800
2400
1760

600
300

150
110

NOTES:
1. Frequency selected by 110 writes of appropriate HI-bit frequency factor to Baud Rate Reoister.
2. Baud rates shown here are only a sample subset of possible software-programmable rates available. Any frequency from
18.75 Hz to 614.4 kHz may be generated utilizing on-board crystal oscillator and 16-bit Program",able Interval Timer (used
here as frequency divider).

Output Frequency
' R....Time Interrupt
(Interval)

Rate Genet'IItor
(Frequency)
Single TImen1)

Min

Max

18.75 Hz

61~.4kHz

1.63",s

53.3ms

2.34 Hz

76.9 kHz

1~.O p.s

426.7ms

Dual Timen3) (Counters 0 and 1ln Series)

0.000286 Hz

307.2 kHz

3.,26 p.s

58.25 min

Dual Timer(4) (Counters 0 and 1 in Series)

0.0000358 Hz

38.4 kHz

26.0 p.s

7.77 hrs

Single TImen2)

NOTES:
1. Assuming 1.23 MHz clock input
2. Assuming 153.6 kHz clock input.

3. Assuming Counter 0 has 1.23 MHz clock input.
4. Assuming Counter 0 has 153.6 kHz clock input.

EIA Standard FtS44~/422 signals provided and supported.

Interrupts
Interrupt requests may originate from the USART (2)
or the programmable timer (2).

Clear to 'Send (CS)
Data Mode (oM)
Terminal Ready (TR)
Request to send (RS)
Receive Timing (Rt)
Receive Data (RD)
Terminal Timihg (TT)
Send Data (SO)

Interfaces
IEEE959 iSBX I/O Expansion Bus
Serial-configurable of EIA Standards RS232C or
RS449/422

Physical Characteristics

EIA Standard RS232C signals provided and supported.

Width:

Clear to Send (CTS)
Data Set Ready (DSR)
Data Terminal Ready (OTR)
Request to Send (RTS)
Receive Clock (RXC)
Receive Data (RXD)
Transmit Clock (DTE TXC)
Transmit Data (TXD)

7.24 em (2.85 inches)

L&ngth: 9.40 em (3.70 inches)
Height·: 2.04 cm. (q.80 inches)
iSBX 351 Board
2.86 em (1.13 inches)
iSBX 351 Board and Host Board
Weight 51 grams (1.79 ounces)'
·(See Figure 2)
6-24

ISBXTM 351

Reference Manual

Electrical Characteristics

9803190- iSBX 351 Serial I/O MULTIMODULE

DC Power Requirements
Mode

RS232C
RS449/422

Manual (NOT SUPPLIED)

Voltage

Amps
(Max)

+5V ±0.25V
+12V ±0.6V
-12V ±0.6V
+5V ±0.25V

460mA
30mA
30mA
530mA

Reference Manuals may be ordered from any Intel
sales representative, distributor office or from Intel
Literature Department, 3065 Bowers Ave., Santa
Clara, california, 95051.

ORDERING INFORMATION
Order Code Description
SBX351
Serial I/O MULTIMODULE Board

Environmental Characteristics
Temperature: 0·C-55·C, free moving air across the
base board and MULTIMODULE
board.

6·25

intel®
iSBXTM 354* DUAL CHANNEL SERIAL 1/0
MULTIMODULETM BOARD

•
•
•

Two RS232C or RS422A/449
Programmable Synchronous/
Asynchronous Communications
Channels
Programmable Baud Rate Generation
for Each Channel
Full Ouplex Operation

959 SBX Bus Compatible 1/0
• IEEE
Expansion
HOLC/SOLC, NRZ, NRZI or
• Supports
FM"Encodlng/Oecoding
Interrupt Options for Each
• Three
Channel
• Low Power Requirements

The Intel iSBXTM 354 Serial I/O MULTIMODULE board is a member cif Intel's line of IEEE 959 iSBX I/O
Expansion Bus products. Utilizing Intel's 82530 Serial Communications Controller component, the is'eX 354
module provides two RS232C or RS422A/449 programmable synchronous/asynchronous communications
channels. The 82530 component provides two independent full duplex serial channels, on chip crystal oscillator, baud-rate generator and digital phase locked loop capability for each channel. The iSBX board connects to
the host board through the iSBX bus. This offers maximum on-board performance and frees the MULTIBUS®
System bus for use by other system resources.

280045-1

'The ISBXTM 354 is also manufactured under product code piSBXTM 354 by Intel Puerto Rico. Inc.

6-26

September 1989
Order Number: 280045-004

inter

ISBXTM 354 MODULE

SPECIFICATIONS

Signals Provided

Word Size
Data-8 bits

Clock Frequency
4.9152 MHz

Serial Communications
Synchronous-Internal or external character synchronization on one or two synchronous characters
Asynchronous-5-8 bits and 1, 1% or 2 stop bits
per character; programmable clock factor; break detection and generation; parity, overrun, and framing
error detection

64000
48000
19200
9600
4800
2400
1800
1200
300

36
49
126
254
510
1022
1363
2046
8190

-Transmit Data
-Receive Data
-Clear to Send
-Data Set Ready
-Signal Ground
-Carrier Detect
-Transmit Clock (2)
-Receive Clock
-Ring Indicator

-Send Data
-Receive Timing
-Receive Data
-Terminal Timing
-Receive Common

Synchronous X1 Clock
82530 Count Value
(Decimal)

RS232CDCE

RS422A/449

Sample Baud Rate:

Baud Rate

RS232CDTE
-Transmit Data
-Receive Data
-Request to Send
-Clear to Send
-Data Set Ready
-Signal Ground
-Carrier Detect
-Transmit Clock (2)
-Receive Clock
-Data Terminal Ready
-Ring Indicator

110 Port Addresses
Port Address
8-Blt

Read Status Channel B
Write Command Channel B

Read Data Channel B
Write Data Channel B

Read Status Channel A
Write Command Channel A

Read Data Channel A
Write Data Channel A

Read Disable RS422A1449 Buffer
Write Enable RS422A1449 Buffer

Asynchronous X16 Clock
Baud Rate

82530 Count Value
(Decimal)

19200
9600
4800
2400
1800
1200
300
110

6
14
30
62
83
126
510
1394

Function

16-Blt

NOTES:
1. The "X" and "Y" values depend on the address of the
iSBX interface as viewed by the base board.
2. "X" corresponds with Activation of the MCSOlinterface
signal; "Y" corresponds with Activation of the MCS1/interface signal.

Power Requirements
INTERFACES

+5V at 0.5A
+12V at 50 rnA
-12V at 50 rnA

SBX Bus: Meets the IEEE 959 Specification, Compliance Level: 08 F

Physical Characteristics

Serial: Meets the EIA RS232C standard on Channels A and B. Meets the EIA RS422A1449 standard
on Channels A and B, Multi-drop capability on Channel A only.

Width: 2.85 inches
Length: 3.70 inches
Height: 0.8 inches
Weight: 85 grams
6-27

ISBXTM 354 MODULE

ENVIRONMENTAL
CHARACTERISTICS

REFERENCE MANUAL
146531-iSBX 354 Channel Serial 1/0 Board Hardware Reference Manual

Temperature: O·C to 55·C operating at 200 linear
feet per minute across baseboard and
MULTIMODULE board

Reference manuals may be ordered from any Intel
sales representative, distributor office, or from Intel
Literature Department, 3065 Bowers Avenue, Santa
Clara, CA 95051.

Humidity: To 90%, without condensation

ORDERING INFORMATION
Order Code Description
SBX354

Dual Channel 1/0 MULTIMODULE

6-28

iSBXTM 1/0 EXPANSION BUS
•

• IEEE 959-88 Industry Standard 110
Expansion Bus
• Provides Cost/Performance Effective
On-Board Expansion of System
Resources

Low-Cost "Vehicle" to Incorporate the
Latest VLSI 110 Technology into
Microcomputer Systems

• Supported by a Broad Range of Host
Single Board Computer Boards

• Supports Compatible 8- and 16-Bit Data
Transfer Operations
The iSBX bus enables users to add-on capability to
a system as the application demands it by providing
off-the-shelf standard MULTIMODULE boards in the
areas of graphics controllers, advanced mathematics functions, parallel and serial 110, and disk and
tape peripheral controllers. A full line of MULTIBUS
boards and iSBX MULTIMODULE boards are available from Intel and other third party sources in the
industry.

The iSBXTM I/O Expansion Bus is one of a family of
standard bus structures resident within Intel's total
system architecture. The iSBX bus is a modular, I/O
expansion bus capable of increasing a single board
computer's functional capability and overall performance by providing a structure to attach small iSBX
MULTIMODULETM boards to iSBC® base boards. It
provides for rapid incorporation of new VLSI into
iSBC MULTIBUS® systems, reducing the threat of
system obsolescence. The iSBX bus offers users
new economics in design by allowing both system
size and system cost to be kept at minimum. As a
result, the system deSign achieves maximum onboard performance while allowing the system bus
interface to be used for other system activities.

Its success as an industry standard has been reinforced by adoption of the SBX specification by the
Institute of Electrical & Electronic Engineers -IEEE

959-88.

6-29

October 1989
Order Number: 280255-002

intJ

ISBXTM I/O EXPANSION BUS

FUNCTIONAL DESCRIPTION
Bus Elements
The iSBXTM MULTIMODULETM system is made up
of two basic elements: base boards and iSBX MULTIMODULE boards. In an iSBX system, the role of
the base board is simple. It decodes I/O addresses
and generates the chip selects for the iSBX MULTIMODULE boards.
The iSBX bus supports two classes of base boards,
those with direct memory access (DMA) support and
those without. Base boards with DMA support have
DMA controllers that work in conjunction with ~n
iSBX MULTIMODULE board (with DMA capability) to
perform direct 110 to memory or memory to 110 operations. Base boards without DMA support use a
subset of the iSBX bus and simply do not use the
DMA feature of the iSBX MULTIMODULE board.

power lines. The iSBX bus provides nine control
lines that define the communications protocol between base board and iSBX MULTIMODULE
boards. These control lines are used to manage the
general operation of the bus by specifying the type
of transfer, the coordination of the transfer, and the
overall state of the transfer between devices. The
five address and chip select signal lines are used in
conjunction with the command lines to establish the
110 port address being accessed, effectively selecting the proper iSBX MULTIMODULE. The data lines
on the iSBX bus can number 8 or 16, and are used
to transmit or receive information to or from the iSBX
MULTIMODULE ports. Two interrupt lines are provided to make interrupt requests possible from the
iSBX board to the base board. Two option lines are
reserved on the bus for unique user requirements,
while several power lines provide + 5 and ± 12 volts
to the iSBX boards.

Bus Pin Assignments
The iSBX MULTIMODULE boards are small, specialized, 110 mapped boards which plug into base
boards. The iSBX boards connect to the iSBX bus
connector and convert iSBX bus signals to a defined
1/0 interface.

Bus Interface/Signal Line Descriptions
The iSBX bus interface can be grouped into six functional classes: control lines, address and chip select
lines, data lines, interrupt lines, option lines, and

The iSBX bus uses widely available, reliable connectors that are available in 18/36 pin for 8-bit devices
and 22/44 pin for 16-bit devices. The male iSBX
connector is attached to the iSBX MULTIMODULE
board and the female iSBX connector is attached to
the base board. Figure 2 shows the dimensions and
pin numbering of the 18/36 pin iSBX connector,
while Figure 3 does the same for the 22/44 pin iSBX
connector. A unique scheme allows the 16-bit female connector to support 8 or 16-bit male MULTIMODULE boards. Table 1 lists the signallpin assignments for the bus.

6-30

intJ
Pln(1)
43

iSBXTM 1/0 EXPANSION BUS

Mnemonic

Table 1 iSBXTM Signal/Pin Assignments
Pin(1)
Description
Mnemonic
MDATABit8

MD8
MDA

MDC

37
35

MDE

Description
MDATA Bit 9

MDATABitA

44
42

MD9
MDB

MDATABitC

MDD

MDATA Bit F
MDATABitD

MDATA Bit E
Signal Gnd

MDF

MDATABitF

GND

+5V

MDO

MDATABitO
MDATA Bit1

MD1
MD2

MDRaT
MDACKI

+5V
M DMA Request

34
32

MDATABit2

OPTO

27
25

MD3

MDATA Bit3
MDATABit4

MD4

OPT 1
TDMA

MD5

MDATABit5

26
24

21
19

MD6
MD7

MDATABit6
MDATABit7

MCSOI

M Chip Select 0

M Chip Select 1

GND

Signal Gnd

15
13

10RDI

110 ReadCmd

10WRTI

liD Write Cmd

18
16
14

MAO

MAddressO

MCS/1
+5V
MWAITI
MINTRO
MINTR1

MA1

M Address 1

MA2

M Address 2

MPSTI

RESET

Reset

MCLK

3
1

GND

Signal Gnd

+12V

6
4
2

Reserved
iSBX Multimodule
Board Present
M Clock

+5V
12V

M DMA Acknowledge
Option 0
Option 1
Terminate DMA
Reserved

+5V
MWait
M Interrupt 0
M Interrupt 1

NOTES:
1. Pins 37-44 are used only on S/16·bit systems.
2. All undefined pins are reserved for future use.

chip select. The full speed liD Write (Figure 5) operation is similar to the liD Read except that the base
board generates valid data on the lines and keeps
the write command line active for the specified hold
time.

Bus Operation Protocol
COMMAND OPERATION
The iSBX bus supports two types of transfer operations between iSBX elements: liD Read and I/O
Write. An iSBX board can respond to these liD
transfers using either full speed mode or extended
mode.

The extended Read operation (Figure 6) is used by
iSBX MULTIMODULE boards that aren't configured
to meet full speed specifications. It's operation is
similar to full speed mode, but must use a wait signal
to ensure proper data transfer. The base board begins the operation by generating a valid liD addres~
and chip select. After setup, the base board actIvates the Read line causing the iSBX board to generate a Wait signal. This causes the CPU on the
base board to go into a wait state. When the iSBX
board has placed valid Read data on the data lines,
the MULTIMODULE board will remove the Wait signal and release the base board CPU to read the data

For a full speed liD Read (Figure 4) the base board
generates a valid liD address and a valid chip select
for the iSBX MULTIMODULE board. After setup, the
base board activates the liD Read line causing the
iSBX board to generate valid data from the addressed liD port. The base board then reads the
data and removes the read command, address, and

6-31

iSBXTM 1/0 EXPANSION BUS

and deactivate the command, address, and chip select. The extended Write operation (Figure 7) is similar to the extended Read except that the Wait signal
is generated after the base board places valid Write
data on the data lines. The iSBX board removes the
Wait signal when the write pulse width requirements
are satisfied, and the base board can then remove
the write command after the hold time is met.

the base board. The PPU processes the interrupt
and executes the interrupt service routine. The interrupt service routine signals the iSBX MULTIMODULE board to remove the interrupt, and then returns
control to the main line program when the service
routine is completed.
Please refer to the Intel iSBX Bus Specification for
more detailed information on its operation and implementation.

DMA OPERATION
An iSBX MULTIMODULE system can support DMA
when the base board has a DMA controller and the
iSBX MULTIMODULE board can support DMA
mode. Burst mode DMA is fully supported, but for
clarity and simplicity, only a single, DMA transfer for
an 8-bit base board is discussed.

SPECIFICATIONS
Word Size
Data: 8, 16-bit

A DMA cycle (Figure 8) is initiated by the iSBX board
when it activates the DMA request line going to the
DMA controller on the base board. When the DMA
controller gains control of the base board bus, it acknowledges back to the iSBX board and activates
an 1/0 or Memory Read. The DMA controller then
activates an 1/0 or Memory Write respectively. The
iSBX board removes the DMA request during the
cycle to allow completion of the DMA cycle .. Once
the write operation is complete, the DMA controller
is free to deactivate the write' and read command
lines after a data hold time.

Power Supply Specifications
Table 3.

INTERRUPT OPERATION

Minimum
(volts)

Nominal
(volts)

Maximum
(volts)

Maximum
(current)'

+4.75

+5.0

+5.25

3.0A

+ 11.4

+12

+12.6

1.0A

-12.6

-12

-11.4

1.0A

GND

3.0A

NOTE:
'Per iSBX MULTI MODULE board mounted on base board.

The iSBX MULTIMODULE board on the iSBX bus
can support interrupt operations over its interrupt
- lines. The iSBX board initiates an interrupt by activating one of its two interrupt lines which connect to

Port Assignments
Table 2. iSBXTM MULTIMODULETM Base Board Port Assignments
16-Bit Base
Board Address (8-bit mode)

16-Blt Base
Board Address
(16-bit mode)

iSBXTM Connector
Number

Chip
Select

8-Bit Base
Board Address

iSBX1

MCSOI
MCS1/

FO-F7
FS-FF

OAO-OAF
OBO-OBF

OAO,2,4,6,S,
A,C,E
OA 1,3,5,7,9,
B,D,F

iSBX2

MCSOI
MCS11

CO-C7
CS-CF

080-0SF
090-09F

080,2,4,6,8
A,C,E
081,3,5,7,9,
B,D,F

iSBX3

MCSOI
MCS11

BO-B7
BS-BF

060-06F
060-06F

060,2,4,6,S
A,C,E
061,3,5,7,9,
B,D,F

6-32

inter

ISBXTM I/O EXPANSION BUS

DC Specifications
Table 4.ISBXTM MULTIMODULETM Board 1/0 DC Specifications
Output 1
Bus Signal
Name

Type 2
Drive

IOLMax
-Min (mA)

@Volts
(VOL Max)

IOHMax
-Min (p.A)

@Volts
(VOHMln)

Co (Min)
(pf)

MOO-MOF

TRI

1.6

0.5

-200

2.4

130

MINTRO-1

TTL

2.0

0.5

-100

2.4

MOROT

TTL

1.6

0.5

-50

2.4

MWAITI

TTL

1.6

0.5

-50

2.4

OPT1-2

TTL

1.6

0.5

-50

2.4

MPSTI

TTL

Note 3

Input1
Type2
Receiver

IlL Max
(mA)

@VINMAX
(volts)
TestCond.

IIHMax
(p.A)

@VINMAX
(volts)
TestCond.

CIMax
(pf)

TRI

-0.5

0.4

2.4

MAO-MA2

TTL

-0.5

0.4

2.4

MCSO/-MCS11

TTL

-4.0

0.4

100

2.4

MRESET

TTL

-2.1

0.4

100

2.4

Bus Signal
Name
MOO-MOF

MOACKI

TTL

-1.0

0.4

100

2.4

IOROI
IOWRTI

TTL

-1.0

0.4

100

2.4

MCLK

TTL

-2.0

0.4

100

2.4

OPT1-0PT2

TTL

-2.0

0.4

100

2.4

NOTES:
1. Per iSBX MULTIMODULE I/O board.
2. TIL = standard totem pole output. TRI = Three-state.
3. iSBX MULTIMODULE board must connect this Signal 10 ground.

6-33

Allinpuls: Max Vil = O.BV
Min VIH = 2.0V

_.
cf

"II

C
c

;;

! - - - 1 . 2 9 7 •. 0 1 5 - - - - - 1

~ .177fREF
I

I EJ

r--.&t7 .. 015--1 r-'O~ ~10

=;::.--r

~: :

.045 REF

!"
-"

(1)

I.-

S'
Ui

._
I

III

(')

I...

'-177

.045

REF

2* .1,
a-a

1.7~0:sc
1·lxl·oo&1 -:~~-,~-L~~

rl==-"-:11""v"'"(00&==>1

r'W ~'lB!!iJ.

..!
r--r-t------

SECTION

(i)

'0401~1
===:=:::::-~I~
i

.100~ iC--{

;:,

L~~:. ~

...... a

SECTION A-A

1.'75~

_1rt;:::i:::1£~_:i==~= = = 0 = : : : : : ; : : ' - 0l;-~~
1--0-0

:::-11..

U55-ffi--

O-OJ~
.. I

280255-3
All dimensions are in inches and unless otherwise specified tolerances are:

.xxp01 •.xxxp005.

><
i!
::::
o
m
><

o
z
OJ

o
o

:::J
:::J
CD

aU;

oo
~

::i'
c:

VIEW A·A

]j[-

~
-.------,- .. --l

"11

ca'
e::
iil

Ci)

045

N
N

.....
(l)

C11

""""
"'tI

:::::
SECTION

o
m
><
"D

c-c

S·

Cii

lJI

r--.Y""

»
Z

~ r10

:IllIt 1 r-~~ ~.• ~ ~

i!
oo
:::I
:::I

(1)

rt
.~

~JI
.035 REF

-0-0

D~ ~-o-=:J

r--

280255-8

Figure 7. ISlICe MULTIMODULElII Board Extended Write
SOURCE·

SIGNAL

lUX BD

MDRQT

8ASE 80

MDACKI

BASE 80

IDRDI

BASE BD

MEM WRITEI

.S8X 80

MDO-MDF

-----if f----------~

ISBX VALID READ DATA

280255-9

Figure 8.ISBXTII MULTIMODULETII Board DMA Cycle
(ISBXlII MULTIMODULETII to Base Board Memory)

6-37

inter

iSBXTM 110 EXPANSION BUS

Board Outlines
All dimensions are in inches and unless otherwise specified tolerances
are:
.""p.Ol, .xxxp005 .
•06 R
4 PLACES

2.050

.158 DIA.
PIN 1
LOCATION

1 PLACE

280255-10
COMPONENT SIDE

Figure 9. iSBXTM Board Outline
All dimensions are In inches and unless otherwise specHied tolerances
are:
.""p.Q1, .xxxp005 .

.2OJ:
; - - -_7'50_~'1
I
.. '
5.100

rr=

2.20_:

11:

3.800

.
"'

.!t

u
300

~ l-;3OO
REF

.151 DIA.
3 PLACES

PIN 1
LOCATION

280255-11
COMPONENT SIDE

Figure 10. Double Wide ISBXTM Board Outline

Environmental Characteristics

Reference Manuals

Operating Temperature: O·C to 55·C
Humidity: 90% maximum relative; non-condensing

210883-G02-MULTIBUS Architecture Reference
Book

6-38

Real-Time
Systems and Software

i RMX®

120

LOW-COST REAL-TIME 386"M SYSTEMS FROM INT.EL
The Intel System 120 delivers real-time capability to users demanding a low-cost system
for running time-critical applications, such as high-speed switching, process control, and
data acquisition. The System 120 combines the rich functionality of the worlds most
popular Real·Time Operating System with the power and speed of the 386'" 32-bit
microprocessor.
The System 120 makes available the ability to host, on a standard computing platform,
real-time applications that have previously been impractical with other AT-Bus systems.
Applications developed for the System 120 can be moved easily to Intels complete line of
MULTIBUS® I and MULTIBUS II products, giving the user a broad spectrum of price,
performance, and functions from which to choose.

FEATURES
• iRMX II: a complete real-time operating
system; more than a kernel
• Intel 386'" 16 MHz and 25 MHz AT-Bus
systems
• Development platform for iRMX®
applications
• Easy migration of applications to and
from MULTIBUS systems
• I/O expansion for PC-AT' and PC
boards
• iRMX II to DOS file exchange
• OpenNET'" networking support
• 387™ numeric coprocessor support
The 25·MHz System 120 IS shown at the top of the page
The 16·MHz System 120 IS shown here as an IRMX" development
platform with the addition of a monitor, video adapter, and keyboard.

infel'---------e Intel Corporation 1989

7-1

September, 1989

Order Number 280649-003

FEATURES
iRMX II: A COMPLETE REAL-TIME
OPERATING SYSTEM

, The System 120 is also available as a board-level
product. (Contact your local Intel office for special
,
ordering instructions.)

iRMX system software is used in more real-time
designs than any other operating system. There are
over 500,000 CPUs worldwide running the iRMX,
Operating System, making it the most widely
accepted standard real-time operating system for
microprocessor-based designs.

Intel offers PC-AT add-in boards for the System 120
that include: 2M-byte and 8M-byte 32-bit memory
boards, the OpenNet PCLlNK2 networking board
and the iPCX 344A BITBUS'" board. A standard
keyboard is also available.

The iRMX II Operating System provides a rich set of
real-time programming facilities not found in generalpurpose operating systems such as DOS, OS/2" or
UNIX". These include:

Table 1: System 120 Target Configurations
PRODUCT
CODE

• Pre-emptive, dynamic priority-based scheduling of
application tasks
• Bounded interrupt latency
• Multitasking support for real-time applications
• Inter-task communications through priority-based
mailboxes, semaphores, and regions
• Interrupt management with exception handling
• Cross or on-target development

CPU
386

SYP12016Z0
SYP12016Z40
SYP120Z5XO
SYP120Z5M40

RAM'
M-bytes

387

16 MHz
16MHz 16MHz
25 MHz
25 MHz 25 MHz

2
2
4
4

FLOPPY
DISK

HARD
DISK

1-2

M-bytes

40
M-bytes

'Subtract 384 K-bytes for RAM available to iRMX" Operating
System.

The iRMX II Operating System also offers high
performance and code integrity. iRMX typically
responds 100 times faster than general-purpose
operating systems, enabling real-time applications Ito
keep up with the rapid data and control flow of
machine and communications interfaces. Code
integrity is ensured through sophisticated memory
protection schemes.

The iRMX software supports a range of popular
display adapters, disk and tape controllers, and a
four/eight-channel I/O controller. Additional drivers
are available from third parties and from Intel's field
systems engineers.

EASY APPLICATION DEVELOPMENT
You can develop applications for AT bus, MULTIBUS I
and MULTIBUS II directly on the system using the
System 120 Development Toolkit. In addition to the
iRMX II Operating System, for the System 120, the
toolkit contains: PLIM 286 Compiler, ASM assembler,
AEDIT and a source level debugger, Soft-Scope' II
and an interface manager (JAM) that can be used as
a front end to applications. Intel also offers a number
of compilers (C, Fortran, Pascal), performance and
debug tools for
iRMXII.

Finally, the iRMX II Operating System is highly
configurable. Its modular design allows you to select
only those functions and device drivers that are
required. This keeps memory requirements to a
minimum. Guided by the many examples in the
System 120 Development Toolkit documentation, you
can add custom device drivers and applications to
the iRMX Operating System.

LOW COST PC-AT BASED
CONFIGURATIONS
The System 120 target mOdels are available with a
number of processor speed, memory, and mass
storage options to fit a range of applications. These
include a basic system with 8 open slots, and a
40M-byte hard disk system with a 387 math
coprocessor and floppy disk (see Table 1).

Table 2: System 120 Development Toolkits

PRODUCT
CODE

SYS120KITZ40
SYS120KITM40
SYS120RMXZ40
SYS120RMXM40

SOFTWARE
PUM 286
ASM
iRMX®1I
AEDIT
SOFTSCOPE
JAM

...
..

....

7-2

CPU

RAM

386
&
387

16 MHz
25 MHz
16 MHz
25 MHz

2
4
2
4

DISK
FLOPPY

HARD

....
...

40Mb

1_2Mb

..
..
..

FEATURES
APPLICATION MIGRATION TO HIGHER
PERFORMANCE SYSTEMS
Applications written for the System 120 can be easily
moved to the higher performance and functionality of
MULTIBUS I and MULTIBUS II deSigns. That's
because the System 120 iRMX II Operating System is
binary compatible with the MULTIBUS
implementation of iRMX II.
The iRMX II Operating System spans the entire Intel
systems product line, from the low-cost System 120
through the MULTI BUS I System 320, to the highend, mUlti-processing MULTI BUS II System 520.
Applications can easily be re-hosted on different bus
architectures, allowing you to create a group of
products satisfying a wide range of customer
performance requirements.

DOS APPLICATION COMPATIBILITY
The System 120 supports the DOS 3.X operating
system as well as iRMX II, enabling you to use
popular DOS applications to process data collected
in real time. Some common applications are already
available from software vendors. The applications
include data bases, menu systems, and device
drivers. The System 120 hard disk can be divided into
iRMX and DOS partitions, allowing users to boot from

either partition. A System 120 utility allows transfer of
iRMX files into a DOS environment. DOS execution
requires a customer-supplied version of DOS, a video
adapter, a monitor, and a keyboard.

WORLDWIDE SERVICE AND SUPPORT
The System 120 is fully supported by Intel's worldwide
staff of trained hardware and software support
engineers. Intel also provides field application
assistance, extensive iRMX Operating System
classes, maintenance services, and a help hotline.
Among many services, Intels systems engineers can
implement special user needs, such as new device
drivers.
The System 120 Development Toolkit comes with a
gO-day software warranty and a one-year hardware
warranty. System 120 target units come with a one
year hardware warranty. Other support packages are
optionally available; for more information please
contact your local Intel Sales Office.

INTEL QUALITY AND RELIABILITY
The System 120 is designed to meet the high
standards of quality and reliability that users have
come to expect from Intel products. The iRMX II
Operating System software has undergone
thousands of hours of testing and evaluation and is
one of the most stable operating systems in the
industry today.

7-3

SPECIFICATIONS
SYSTEM 120 16·MHZ BASE SYSTEM

ELECTRICAL

Central Processor

Intel 386, 16 MHz

AC Voltage/Frequency

Floating-Point
Coprocessor

Intel 387, 16 MHz··

Main Memory
Maximum RAM
Cycle Time
Data Bus Width
Error Detection

2M Bytes on CPU Board
16M Bytes
120 ns
32-Bits
Byte Parity

I/O

1 serial port
(asynchronous, RS232C,
9-pin connector)
1 parallel port (Centronics
compatible, 25-pin
connector)
2 32- or 8-bit slots
4 16-bit slots
2 8-bit slots

8 expansion slots:

DC Power
+5V
+12V
-12V
-5V

DIMENSIONS
Length
Width
Height

439 millimeters (17.3 inches)
541 millimeters (21.3 inches)
165 millimeters (6.5 inches)

WEIGHT
Base System:

SYSTEM 120 25·MHZ BASE SYSTEM

ELECTRICAL

Central Processor

Intel 386, 25 MHz

AC Voltage/Frequency

Floating-Point
Coprocessor

Intel 387, 25 MHz·'

Main Memory
Maximum RAM
Cycle Time
Data Bus Width
Error Detection

4M Bytes on CPU Board
24M Bytes
80 ns
32-Bits
Byte Parity

I/O

2 serial ports
(asynchronous, RS232C,
9-pin connector)
1 parallel port (Centronics
compatible, 25-pin
connector)
232-,16- or 8-bit slots
5 16- or 8-bit slots
1 8-bit slot

8 expansion slots

Switching power supply,
115 V/60Hz or 230 V/50 Hz
220 Watts
23.0 A maximum continuous
8.0 A maximum continuous;
12.0 A maximum for
12 seconds
0.5 A maximum continuous
0.5 A maximum continuous

DC Power
+5V
+12V
-12V
-5V

20 kilograms (44 Ibs)

Switching power supply,
115 V/60Hz or 230 V/50 Hz
220 Watts
23.0 A maximum continuous
8.0 A maximum continuous;
12.0 A maximum for
12 seconds
0.5 A maximum continuous
0.5 A maximum continuous

DIMENSIONS
Length
Width
Height

475 millimeters (18.7 inches)
541 millimeters (21.3 inches)
165 millimeters (6.5 inches)

WEIGHT
Base System:

• 'See tables 1 and 2 for configurations that apply

ORDERING INFORMATION
For more information or the number of your nearest
Intel sales office, call 800-548-4725 (good in the
U.S. and Canada).

7-4

20 kilograms (44 Ibs)

SYSTEM 310* AP

,.,.

SYSTEM 310 AP
The System 310 AP IS faster than many minicomputers. Powerful dedicated processors for
communications and mass storage inpuUoutput control allow the 8 MHz 80286 CPU to
concentrate on application software. The System 310 AP is open, which means you can
upgrade performance and/or functionality in the future without purchasing a new system.
The open system design protects your investment from becoming obsolete. Open
systems design also means easy system customization with Intel and third-party add-in
MULTIBUS® boards.

FEATURES
• 80286 Based System
• Open System MULTIBUS architecture
for upgradeability and growth
• iRMX® Operating System
• OpenNET'" Local Area Networking
• Total hardware and software support
from Intel's worldwide customer support
organization

·m_l"
I. I--e-

The System 310 AP IS also manufactured under product code pSYS310 by Intel Puerto Rlco,lnc
September, 1989
Order Number 280129-005

7-5

FEATURES
SYSTEM 310 AP-AN OPEN SYSTEM

A wide range of popular industry standard high-level
languages are supported for application
development. The iRMX facilities also include
powerful utilities for easy, interactive configuration and
debugging.

The Intel System 310 AP is based on the MULTIBUS
architecture, (IEEE 796) industry standard system
bus supported by over 200 vendors providing over
2000 compatible products.

OpenNETTM -NETWORKING CAPABILITY

The System 310 AP is an 80286 based open system
designed with expansion in mind. The system can be
expanded to accommodate up to 9MB of paritychecked RAM, all accessible with no wait states
across MULTIBUSs Local Bus Extension (LBXTM). For
terminal communications, the systems can be
expanded to a total of 18 RS232 serial ports.

Intel's OpenNET product family provides a complete set of
networking software and hardware that follows the
International Standards Organization (ISO) Open Systems
Interconnect (OSI) model.
OpenNET Network File Access Protocol adheres to the
IBM/Microsoft/Intel Core File Sharing Protocol
specification, providing transparent local/remote file access
and file transfer capability between Intels complete line of
systems products, as well as with MSNET* and VAX/
VMS'# based systems.

The System 310 AP supports 40MB-140MB of
Winchester disk storage. The 310 AP also supports a
320KB 5" floppy drive and a 60MB streaming tape
cartridge drive.

iRMX® OPERATING SYSTEM

The System 310 AP distributes the transport protocol
processing to intelligent Ethernet controllers that host Intels
OSI-compliant iNA 960 Class 4 Transport software, thereby
unburdening the system CPU for greater performance.

The iRMX operating system delivers real-time performance. Designed to manage and extend the
resources of the System 310 Ap, this multitasking
operating system provides configurable resources
ranging from interrupt management and standard
device drivers to data file maintenance commands for
human interface and program development.

INTEL SERVICE AND SUPPORT
The System 310 AP is backed by Intels worldwide service
and support organization. Total hardware and software
support is available, including a hotline number for when
you need help fast.

SPECIFICATIONS
SYSTEM/MODELS

310 AP-40B

310AP-41B

310AP-42

310AP-82B

310AP-142

Microprocessor

80286
8MHz

80286
8 MHz

80286
8MHz

80286
8 MHz

Numeric Coprocessor

80287

1MB

2MB

360KB

40MB

85MB

140MB

60MB

RAM Memory

Floppy
Mass Storage
Tape Backup
Serial I/O Ports
Parallel Ports
OpenNET

ENVIRONMENT
Operating Temperature
Wet Bulb Temperature
Relative Humidity
Altitude

ELECTRICAL
1Q°C to 35°C
26°C maximum
20% to 70%
noncondensing
Sea level to 8,000 feet

REGULATIONS
Meets or exceeds the following requirements:
Safety
US
UL114
Canada
CSA C22.2
TUV ICE 435
Europe
EMI/RFI
US and Canada
FCC Docket 20780Class A
Europe
VDE 0871 Class A
*

• MSNET IS a trademark of Microsoft
VAXlVMS IS a trademark of DIgital EqUipment Corporation

DC Power Output
AC Power Input

360 watt maximum
88-132 VAC or 180-264
VAC, 47-63 Hz (user
selectable)

DIMENSIONS
Height
Width
- Depth
Weight

7-6

6V2"
17"
22"
Approx. 55 Ibs

SYSTEM 310* 386 UPGRADE

Intel's System 310 386 Upgrade offers the user an upgrade path to the performance of
the 386'· microprocessor without sacrificing existing software and hardware investments.
This Customer Service Installed upgrade is designed for the System 310 and System
310AP series of microcomputer systems using iRMX II operating system.

STANDARD FEATURES
• 16 MHz 386'· Microprocessor
• 16 Bit 80287 Numeric Data Processor
• Memory Options:
1, 2, 4 and 8 MB
o wait state RAM
• Systems Confidence Test
(SCT) and boot firmware
• Installed by Intel Customer Service at
your location

intel' .

The ISXM386 kit IS also manufactured under product code pISXM386 kit by Intel Puerto RIco. Inc

=Intel Corporation 1989

7.. 7

Order

Num~:t~;ci~~~~

SPECIFICATIONS
The iSXMTH 386 Kit is designed to meet certain UL, FCC, CSA, IEC and VDE requirements when it is installed
into an INTEL System 310 and System 310AP. It is the responsibility of the customer to reconfirm that the
specific systems they have created from MULTIBUS elements continue to meet the required safety and
environmental specifications in the customer environment. Intel is not responsible for any changes made after
the product is accepted by Intel's customer.

SAFETY REQUIREMENT/EMI LIMITS

ORDERING INFORMATION

The iSXM 386 Kit IS designed to meet:

Your memory requirements will determine the product
order code:

Safety:
• UL 478 5th edition
• CSA C22.2 no. 154
• TUV IEC435 and VDE 0806

Memory Requirement

Order Code

1 MB RAM
2 MB RAM
4 MBRAM
8 MBRAM

iSXM386KIT-1
iSXM386KIT-2
iSXM386KIT-4
iSXM386KIT-8

RMI/EMI:
• FCC 47 CFR Part 15
Subpart J Class A
• VDE '0871 Level A

SYSTEM SOFTWARE

Actual compliance will depend on the modules,
peripherals and cable connectors which you install in
the system.

IRMX II Languages:
FORTRAN 286, C286
Assembler 286, PLIM 286
Intel believes that the information in this document is
accurate as of its publication date. Such information
is subject to change without notice. Intel is not
responsible for any inadvertent errors.

ELECTRICAL
Voltage and Maximum Current:
iSXM 386 KIT-l, 1 MB Memory

± 5 VDC
+ 12 VDC
- 12 VDC

± 5%
± 5%
± 5%

12.5 amps
0.025 amps
0.025 amps

2 MB Memory add .3 amps @5 VDC
4 MB Memory add .0 amps @5 VDC
8 MB Memory add .3 amps @5 VDC

BASE REQUIREMENTS
You must have a current copy of iRMX II Release 2.0
or later installed on your system before the system
can be upgraded. The - 4 and - 8 kits are
recommended for use on 80 MB or 140 MB
Winchester based systems only.

iRMX® SYSTEM 320*

iRMX® SYSTEM 320
Intel combines the power of its high performance 386'" microprocessor-based System
320, the widely used iRMX II real-time software, complete network service software and
comprehensive customer support capabilities to deliver, install and maintain a complete
system. The result is the iRMX System 320 gives you the performance and capabilities of
a minicomputer at less than half the cost. The system is especially suited for applications
requiring real-time response and resource control typically found in financial transaction,
industrial automation, medical and communications markets. The iRMX System 320 is
also appropriate as the development environment for module-based design.

iRMX® SYSTEM 320 FEATURES
• 80386 Based System
• iRMX Real-time Multitasking Operating
System
• Open System Architecture
• OpenNET Local Area Networking
• Complete Installation, Service and
Support
• Worldwide User Group Support
• Range of Configurations

inter .

The System 320 os also manufactured under product code pSYS320 by Intel Puerto RIco. Inc
September, 1989
Order Number 260502-002

7-9

FEATURES
iRMX® II-REAL-TIME SOFTWARE

products, as well as with MSNET* and VAXNMS*#
based systems.

The iRMX 11 operating system delivers real-time performance. Designed to manage and extend the resources of the System 320, this multitasking
operating system provides configurable resources
ranging from interrupt management and standard device drivers to data file maintenance commands for
human interface and program development. The
iRMX II facilities also include powerful utilities for easy,
interactive configuration. and debugging.

The System 320' distributes the transport protocol
processing to intelligent Ethernet controllers that host
Intel's OS I-compliant iNA 960 Class 4 Transport software, thereby unburdening the system CPU for
greater performance.

INSTALLATION SERVICE &SUPPORT
The Intel iRMX System 320 is backed by Intel's worldwide service and support organization. Installation is
available to quickly get the system up and running.
Total hardware and software support is available, including a hotline number for when the user needs
help fast. Intel also provides hands-on training workshops to give the user a thorough understanding of
the iRMX System 320. These workshops are conducted at Intel training centers or customer sites
worldwide.

SYSTEM 320-AN OPEN SYSTEM
The iRMX System 320 is based on MULTIBUS architecture, (IEEE 796) industry standard system bus
supported by over 200 vendors providing over 2000
compatible products, and on the iRMX II operating
system composed of modular layers, highly configurable for tailoring to. target applications. A wide range
of popular industry standard high-level languages are
supported for application development. Special configurations can be tailored by the user, by Intel's Custom System Integration group or by Intel's authorized
Value Added Distribution Centers.

WORLDWIDE USER GROUP SUPPORT
iRUG (iRMX User Group), provides members a user's
library of iRMX software tools and utilities, access to
the group bulletin board, receipt of regularly published newsletters and invitations to User Group Conferences. iRUG numbers over 42 local chapters in 20
countries worldwide.

OpenNETTM NETWORKING CAPABILITY
Intel's OpenNET product family provides a complete
set of networking software and hardware that follows
the International Standards Organization (ISO) Open
Systems Interconnect (OSI) model.

RANGE OF CONFIGURATIONS
Intel offers a wide range of configurations for the
iRMX System 320. Contact your local Intel represen. tative for fu rther information.

OpenNET Network File Access Protocol adheres to
the IBM/Microsoft/Intel Core File Sharing Protocol
specification, providing transparent local/remote file
access and file transfer capability between Intel's
complete line of systems

* MSNET IS a trademark of Microsoft
* * VAXNMS IS a trademark of Digital EqUipment Corporation

SPECIFICATIONS
ENVIRONMENT
Operating Temperature
Wet Bulb Temperature
Relative Humidity
Altitude

DIMENSIONS
Height
Width
Depth
Weight

1Q°C to 40°C
26°C maximum
85% at 40°C
Sea level to 10,000 feet

REGULATIONS

ORDERING INFORMATION

Meets or exceeds the following requirements:
Safety
US
Canada
Europe
EMIIRFI
US and Canada
Europe

For more information or the number of your nearest
Intel sales office, call 800-548-4725 (good in the U.S.
I and Canada).

UL478
CSA C22.2
IEC 435
FCC Class B Computing
Device
VDE Limit Class B

ELECTRICAL
DC Power Output
AC Power Input

8"
17.5"
22.25"
Approx. 55 Ibs

435 watt maximum
88~132 VAC or 176-264 VAC,
47-63 Hz, single phase
7-10

IRMX® II SYSTEM 5201

UNLOCK THE POWER OF MULTIBUS®II WITH AN INTEL ® OEM SYSTEM
The Intel System 520 and MULTIBUS II System Architecture (MSA) make it easy to unlock
the power of MULTI BUS II. The System 520 is the first in a family of high performance,
real-time OEM systems to combine Intel's open MSA architecture, the powerful 386'H
microprocessor, and UNIX' System V or the industry-leading iRMX®1I real-time
multitasking operating system. Together, they provide an easily scalable, recomposable
open bus system.
As an open OEM system, the System 520 allows users to add to the basIc system, or
purchase the system's contents separately and repackage them into another enclosure.
Intel's MSA provides this capability via a structured set of open, standard interfaces and
protocols that build on and are fully compatible with the MULTIBUS II (IEEE 1296) bus
standard. As a result, the System 520 provides new standards of ease of integration, ease
of use, and board compatibility for the OEM.

FEATURES
• 386 CPU-based performance
• Supports System V/386 UNIX or iRMX II
real-time operating system
• Easy 386 application processor
expansion
(1 to 4)
• High performance SCSI 110 subsystem

• OpenNET'M transparent remote file
sharing & virtual terminal between 386
processors and IEEE 802.3 networked
systems
• Hardware windowed graphics and
virtual terminal support
• iRMX II and System V/386 UNIX'
development systems available

intel°---------o Intel Corporation 1989

7-11

October. 1989
Order Number 280672·002

FEATURES
THE MULTIBUS®II SYSTEM
ARCHITECTURE (MSA)

A NETWORK IN THE SYSTEM
Using the MULTI BUS II backplane as an ultra-fast
network (40MBytes/sec), multiple peer-to-peer 386'"
CPU-based application processors operate as
independent "networked" iRMX or UNIX systems over
the MULTIBUS II Parallel System Bus (PSB). Each
application processor running Intel's OpenNEPM
network software will provide transparent distributed
file sharing, file transfer, and virtual terminal capability
among all application processors on the backplaneand among IEEE 802.3-based (1.25MBytes/sec)
OpenNET networked system nodes. Using the PSB
as a network makes the System 520 a high
performance "minicomputer" cluster condensed into
one multiprocessor system.

The System 520 is built around Intel's MULTIBUS II
System Architecture (MSA) to ease the development
and integration work of MULTIBUS II OEM system
designers. Intel's MSA delivers open system interface
and protocol standards that build on and extend the
basic MULTI BUS II (IEEE/ANSI1296) bus standard.
The MSA specifications define diagnostics, bUilt-in
self test, system initialization and boot loading, board
configuration, and message passing. The user
benefits from MSA because the level of vendor and
board compatibility has been raised above basic
electrical bus specifications to a set of powerful
programmatic interfaces that handle the bus specifics
with software. This provides OEMs quicker time to
market with faster system integration and shorter
design cycles.

The major advantage to the OEM is total network
extensibility inside and outside the system, using the
same OpenNET software. The key benefits are:
reduced cost compared to multiple uni-processor '
networked systems and servers, drastically reduced
physical space requirements, increased overall
network throughput and performance, and preserved
software investment.

EASY USER EXPANSION AND
RE-COMPOSABLE SYSTEMS
The MULTIBUS II System Architecture is used as the
foundation for integrating Intel's full line of Single
Board Computer (iSBC Graphics Interface
driven by Intel's iSBXTM 279 Graphics Board. The
graphics subsystem and its companion software
provide a windowed virtual terminal console with
graphics capabilities. With its on board processing
power and large graphics memory buffer, the iSBX
279 off-loads the application processors of the
display processing tasks. The user interfaces to the
System 520's subsystem are an RGB color monitor
(640 x 480), a mouse, and an AT-style keyboard
(purchased separately).

The System V/386 UNIX operating system delivers
full support for Intel's MULTIBUS II System
Architecture. Intel has built a complete System V/386
product family providing OEMs, system integrators
and computing manufacturers with industry standard
UNIX, OpenNEpM networking, system hardware, and
Ada development tools for the MULTIBUS II System
Architecture. Together, these elements deliver a rich,
. complete UNIX development environment.

7-12

FEATURES
iRMX® II: A FULL FEATURED REAL-TIME
OPERATING SYSTEM FOR MULTIBUS®II
Intels IRMX" Real-Time Multitasking Operating
System is a full featured, stand alone operating
enVIronment, designed to address the complete
range of real-time applications, from embedded
control designs to reprogrammable MULTIBUS"
multiprocessor systems. It provides complete
MULTIBUS" faCilities supporting MULTIBUS "
Transport message passing and Interconnect space
access. Using IRMX " software, engineers can
assemble a powerful, cluster of application
processors into a single, Integrated multiprocessor
system. The iRMX " system software manages all
message transmission and reception, making the
construction of real-time mUltiprocessor systems
easier.
The iRMX " Operating System provides a rich set of
real-time programming facilities not found in generalpurpose operating systems. Some of its key features
Include pre-emptive, dynamic priority-based
scheduling of application tasks; bounded interrupt
latency; multitasking support; Inter-task
communications and synchronization through prioritybased mailboxes, semaphores, and regions, and
Interrupt management with exception handling. By
combining these features With a modular design;
qUick response; and sophisticated memory
protection schemes, the OEM receives a highly
configurable, customlzable operating system With the
high performance and code integrity that real-time
applications require.

COMPLETE MULTIBUS®II DEVELOPMENT
ENVIRONMENT
The System 520 is also available as a bundled,
complete, networked development system for
MULTIBUS" modules development, software
development and testing of real-time applications.
The System 520 IS unique as a MULTIBUS "

development system, because its multiprocessor
cluster capability can support both on-target or crosshosted system and software development in one
chassis.

OpenNET'M NETWORKING CAPABILITY
Intel's OpenNET product family provides a complete
set of networking software and hardware that follows
the International Standards Organization (ISO) Open
Systems Interconnect (OS I) seven layer model. The
System distributes the ISO/OSI transport protocol
processing to intelligent Ethernet controllers hosting
Intel's OSI compliant iNA 960 Class 4 Transport
software. Intels OpenNET Network File Access (NFA)
protocol provides the upper layer functionality of
transparent local or remote file access and file
transfer between Intel's complete line of system
products, as well as MS-DOS Operating Systembased personal computers and VAXIVMS*
minicomputers. The OpenNet NFA protocol adheres
to the standard IBM*/Mlcrosoft*/lntel Core File
Sharing protocol specification.

WORLDWIDE SERVICE AND SUPPORT
The System 520 is fully supported by Intel's
worldWide staff of trained hardware and software
support engineers. Intel also provides field
application assistance, extensive operating system
classes, maintenance services, and a help hotline.
The System 520 OEM System products come with a
standard 90-day hardware warranty. The System 520
MULTIBUS" Development System products come
bundled With a one (1) year service warranty. This one
year warranty Includes: hardware installation and one
year of on-site maintenance, software installation of
the operating system and 48 hours of phone support.

INTEL QUALITY AND RELIABILITY
The System 520 is deSigned to meet the high
standards and reliability that users have come to
expect from Intel products.

SPECIFICATIONS
SYSTEM 520 CONFIGURATIONIOPTIONSTABLE 1
Product

System 520 OEM
Base Plus 110
System 520 OEM
Base Without Tape
System 520 OEM
Base With Tape
IRMX System 520
Development System
System V/386 520
Development System

V'
V'

7-13

V'
V'

iRMKTM VERSION 1.2 REAL-TIME KERNEL

A 32-81T REAL-TIME KERNEL
The iRMKTlI Version 1.2 Real-time Kernel is the 32-bit real-time executive developed, sold,
and supported by Intel, the Inte1386'" architecture experts. It reduces the cost and risk of
designing and maintaining software for numerous real-time applications such as
embedded control systems and dedicated real-time subsystems in multiprocessor
systems.

FEATURES
• 32-bit real-time multitasking kernel
• Rich set of real-time services
• Designed and optimized for the
Inte1386" and Inte1376" families
• Extremely fast execution with
predictable response times for time
critical applications
• Compact design, as small as 8K bytes
• Multiprocessor support
• Requires only the 80386 or 80376;
Provides optional support for 80387
and 80387SX Numeric Coprocessors
and other peripheral devices

o Intel Corporation 1989

• Works with any bus including the
MULTIBUS® I and MULTIBUS II
architectures
• Optional MULTIBUS II message passing
support provided
• Designed for easy customization and
enhancement
• Easily programmed into PROMs or
EPROMs
• Comprehensive development tool
support
• Supported by Intel

7-14

September, 1989
Order Number 280613·002

FEATURES
REAL-TIME SOFTWARE FROM THE
INDUSTRY LEADER
Intel has been the industry leader in microprocessorbased real-time computing since it invented the
microprocessor. No other company supplies the
range of real·time solutions that we do. Since 1977,
thousands of customers have used our iRMX® realtime operating systems.
Now Intel has put its real-time expertise into a 32-bit
kernel that supports the 80386 microprocessor and
the 80376 embedded controller. The iRMK Version 1.2
Kernel saves you the cost of designing, debugging,
and maintaining your own executive for real·time
systems. You can concentrate on writing your
application rather than on writing a kernel.

THE QUICKEST PATH FOR A WIDE RANGE
OF REAL-TIME APPLICATIONS
The iRMK Kernel's high performance and rich set of
real-time services make It ideal for a wide range of
real-time applications, including:
Data acquisition and analysis
Continuous process control
Discrete process control
Simulation
Medical instruments
Test instrumentation
Image processing
Automated test
Avionics and navigation
Field command control
Energy and environmental control
Radio control
Satellite communications
Terminals
Graphics work stations
Robotics
Signal processing
Laser printers
Front-end concentrators
Host communications

A RICH SET OF REAL-TIME SERVICES
The iRMK Version 1.2 Kernel provides a rich set of
services for real-time applications, including:
• Task management with system calls to create,
manage, and schedule tasks in a multitasking
environment. The Kernel offers pre-emptive' priority
scheduling combined with optional time-slice
(round robin) scheduling.
The scheduling algorithm used by the iRMK Kernel
allows tasks to be rescheduled in a fixed amount of
time regardless of the number of tasks.
Applications may contain any number of tasks.
An application can provide optional task handlers
to customize task management. These handlers
can execute on task creation, task switch, task

deletion, and task priority change. Task handlers
can be used for a wide range of functions
including saving and restoring the state of
coprocessor registers on task switch, masking
interrupts based on task priority, or implementing
statistical and diagnostic monitors.
• Interrupt management by immediately switching
control to user-written interrupt handlers when an
interrupt occurs. Response to interrupts is both fast
and predictable. Most of the Kernel's system calls
can be executed directly from interrupt handlers.
• Time management providing single-shot alarms,
repetitive alarms, and a real-time clock. Alarms can
be reset.
These time management facilities can solve a wide
range of real-time programming problems. Singleshot alarms, for example, can be used to handle
timeouts. If the timeout occurs, the alarm invokes a
user-written handler; if the event occurs before the
timeout, the application simply deletes the alarm.
Other uses for the Kernel's time management
facilities include polling devices with repetitive
alarms, putting tasks to sleep for specified periods
of time, or implementing a time-of-day clock.
• Semaphores, regions, and mailboxes for intertask
synchronization and communication. Semaphores
are used for intertask signalling and
synchronization. Regions are special binary
semaphores used to ensure mutual exclusion and
prevent deadlock when tasks contend for control of
system resources. A task holding a region's unit
runs at the priority of the highest priority task
waiting for the region's unit.
Mailboxes are queues that can hold any number of
messages and are used to exchange data between
tasks. Either data or pointers can be sent using
mailboxes. The Kernel allows mailbox messages to
be of any length. High priority messages can be
placed (jammed) at the front of the message
queue to ensure that they are received before other
messages queued at the mailbox
To ensure that high priority tasks are not blocked
by lower priority tasks, the Kernel allows tasks to
queue at semaphores and mailboxes in priority
order. The Kernel also supports first-in, first-out task
queuing.
• Memory pool manager that provides fixed and
variable block allocation. Memory can be divided
into any number of pools. Multiple memory pools
might be created for different speed memories or
for allocating different size blocks. Access to a
memory pool for fixed-sized allocation is always
deterministic.
The Kernel-supplied memory manager works with
flat, segmented, and paged addressing. Users can
write their own memory manager to provide
different memory management policies or to
support virtual memory.
7-15

FEATURES
SUPPORT FOR MULTIPROCESSING VIA
MULTIBUS®U ARCHITECTURE
The MULTIBUS II architecture is designed to optimize
multiprocessor designs. This bus:
• Implements a loosely coupled architecture in which
Interprocessor interrupts and data are exchanged
via messages transmitted as packets over the bus;
• Provides fast bus access;
• Allows interprocessor signalling at interrupt speeds
from as many as 255 sources;
• Provides data transfer rates of up to 32 megabytes
per second;
• Allows multiple communication sessions to occur
simultaneously between processors;
• Supports up to 21 CPU boards per chassis with
each board providing the proceSsor, memory, and
I/O needed for its portion of the application; and
• Provides registers-called Interconnect Space-on
each board that can be used for dynamic system
configuration.
Two optional modules allow iRMK Kernel applications
to make full use of the MULTIBUS II architecture. The
first module implements message passing allowing
the application to have direct access to the message
passing hardware or to use Intel's MULTI BUS II
transport protocol. The second module implements
interconnect space access to support dynamic
system configuration.
These modules can be used to implement high
performance multiprocessor designs that:
• Break a highly complex real·time application into
multiple lower complexity applications distributed
across multiple processors
• Distribute an application that's too CPU intensive
for a single processor between several processors
• Provide redundancy
• Dedicate processors to specific tasks
• Provide interoperation with any operating system
or controller board that uses Intel's MULTIBUS II
transport protocol, including the iRMX" 11.3, iRMK
1.2, and Intel System V/386 operating systems.

HARDWARE REQUIREMENTS AND
SUPPORT
The iRMK Kernel requires only an 80386
microprocessor or an 80376 embedded controller
and sufficient memory for itself and its application. Its
design, however, recognizes that many systems use
additional programmable peripheral devices and
coprocessors. The Kernel provides optional device
managers for:
• The 80387 and 80387SX Numeric Coprocessors
• The 82380 and 82370 Integrated System
Peripherals
• The 8254 Programmable Interval Timer
• The 8259A Programmable Interrupt Controller
7·16

An application can supply managers for other
devices and coprocessors in addition to or in
replacement of the devices listed above.
The iRMK Kernel was designed to be programmed
into PROM or EPROM, making it easy to use in
embedded designs.
The iRMK Kernel can be used with any system bus
including the MULTIBUS I and MULTIBUS II busses.
The optional MULTI BUS II message passing and
Interconnect Space access modules use the
Message Passing Coprocessor (MPC). The Kernel
provides managers to use the 82380/82370
Integrated System Peripherals or the 82258
Advanced DMA controller with the MPC for message
passing.

SUPPORT FOR THE INTEL386™ AND
INTEL376™ ARCHITECTURES
The iRMK Kernel provides 32·bit, protected mode
80386 and 80376 operation. By default, the Kernel
and its application execute in a flat memory space of
up to 4 gigabytes and in a single privilege level.
Applications can add support for any mixture of
additional protected mode features including:
•
•
•
•
•

Any model of segmentation
Memory paging
Virtual memory
Multiple privilege levels
Call and trap gates

These protected mode features can be used to
increase the reliability of the application by using the
processor's hardware to:
• Protect against attempts to write beyond segment
bounds (to catch, for example, situations like stack
overflow or underflow)
• Allow only privileged or trusted code to access key
routines and data
• Isolate bugs to single modules so that the rest of
the application and the Kernel are not corrupted
• Assign access rights to code and data
• Isolate address spaces
To use these features, the application manipulates the
processor's descriptor tables. Since the Kernel was
designed specifically to support 80386 and 80376
applications, it provides an optional Descriptor Table
manager that simplifies protected mode
programming. This manager provides system calls to
read and write descriptor table entries, to convert
addresses from linear to physical and vice versa, and
to get a segmenfs selector.

FEATURES
A MODULAR ARCHITECTURE FOR EASY
CUSTOMIZATION

COMPREHENSIVE DEVELOPMENT TOOL
SUPPORT

The iRMK Kernel was designed for maximum
flexibility so it can be customized for each application.
Each major function-mailboxes, for example-was
implemented as a separate module. The Kernel's
modules have not been linked together and are
supplied individually. You link the modules you need
for your application. Any module not used does not
need to be linked in, and does not increase the size
of the Kernel in your application. You can also replace
any optional Kernel module with one that implements
specific features required by your application. For
example, you might want to replace the Kernel's
memory manager with one that supports virtual
memory.

Intel provides a complete line of 80386 and 80376
development tools for writing and debugging iRMK
Kernel applications. These tools include:

Table 1 lists the Kernel's modules.
Table 1: iRMK" Version 1.2 Kernel Modules
Core
Functions

Optional
Modules

• Task manager • Mailbox manager
• Time
• Semaphore
manager
manager
• Interrupt
• Memory Pool
manager
manager
• Descriptor Table
manager
• MULTIBUS"
Message Passing
• MULTIBUS"
Interconnect
Space Access

Optional Device
Managers

• 80387 &
80387SX
• 82380 & 82370
·8254
• 8259A

DEVEL.OPING WITH THE iRMK'M
REAL-TIME KERNEL
iRMK Kernel applications can be written using any
language or compiler that produces code that
executes in the 80386's protected mode or on the
80376. This independence is achieved by using
interface libraries. These libraries work with the
idiosyncrasies of each lal)guage-for example, the
ordering of parameters. The interface libraries
translate the call provided by the language into a
standard format expected by the Kernel. Intel
provides interface libraries for our iC 386 and PLIM
386 languages. The source code for these libraries is
provided so you can modify them to support other
compilers.
Intel's 80386 Utilities are used to link the Kernel's
modules and to locate the Kernel in memory.
Applications written with a compiler that produces
OMF386 object module format can be linked directly
to the Kernel for the highest possible performance.
Alternately, applications written in OMF386 or another
object module format can access the Kernel through
a call gate mechanism included with the Kernel.
Because the Kernel is supplied as unlinked object
modules, applications can be developed on any
system that hosts the development tools that you will
use.

Software:

Debuggers:

PLIM 386 Compiler
iC 386 Compiler
ASM 386 Assembler
RLL 386 Utilities
ICET. 386 and ICE 376
P·MON 386
D·MON 386

These tools run on IBM' PC AT systems and
compatibles running PC· or MS·DOS' 3.X. The
languages and utilities also run on VAXNMS and
MicroVAXNMS' systems. The iRMK Version 1.2
Kernel software is available on IBM PC format 5%
inch, 360K byte diskettes.

INTEL SUPPORT, CONSULTING, AND
TRAINING
With the iRMK Kernel you get the Intel386
architecture and real·time expertise of Intel's customer
support engineers. We provide phone support, on· or
off· site consulting, troubleshooting guides, and
updates. The Kernel includes 90 days of Intels
Technical Information Phone Service (TIPS).
Extended support and consulting are also avaifable.

CONTENTS OF THE iRMK'" KERNEL

DEVELOPMENT PACKAGE

The iRMK Kernel comes in a comprehensive
package that includes:
• Kernel object modules
• Source for the Kernel·supplied 82380 and 82370
Integrated System Peripherals; 8259A PIC; 8254
PIT; and 80387 and 80387SX Numeric
Coprocessor device managers
• Source for PLIM 386 and iC 386 interface libraries
• Source for the call gate interface
• Source for sample applications showing:
-Structure of Kernel applications
- Use of the Kernel with application written in both
PLIM 386 and iC 386
-Compile, bind, and build sequences
-Sample initialization code for the 80386
microprocessor
-MULTIBUS" message passing
-Applications written to execute in a flat memory
space and in a segmented memory space
• User Reference Guide
• 90 days of Customer Support
'IBM IS a registered trademark of the International
BUSiness Machines Corporation.
, MS·DOS IS a trademark of Microsoft Corporation.
'VAX IS a registered trademark of Digital Equipment
Corporation. VMS is a trademark of Digital EqUipment
Corporation.
7-17

FEATURES

Application

UserSupplied
System
Routines'

Language Interface Libraries

Kernel
Supplied.
Device
Managers

Kernel
Optional
Modules

Kernel
Core
Modules

Hardware

Figure 1: iRMKTH Version 1.2 Real-Time Kernel Architecture
• User-supplied system routines would include Interrupt handlers, user-written device managers, and similar routines.

IRMX"11.3
Operating
System

iRMKMI.2
Real-Time
Kernel

·11

IRMK'"1.2
Real-Time
Kernel

Intel System V/386
Operating
System

MULTIBUS II Parallel System Bus
(IEEE1296)
Terminal
Concentrator

I
Disk
Controller

Figure 2: The optional MULTIBUS II message passing modules give the iRMKTH 1.2 Version Kernel full
multiprocessing capabilities for distributing applications among processors and interoperating with other
operating systems.

7-18

ISYSTEM CALLS
iRMK'" VERSION 1.2 KERNEL SYSTEM CALLS1
Kernel Initialization
KN_initlalize

KN_inltlalize_subsystem
Initialize Kernel
KN_lineaUo_ptr

Object Management
KN_token_to_ptr
KN_currenLtask

Returns a pointer to area
holding object
Returns a token for the current
task

Create a task
Delete a task
Suspend a task
Resume a task
Change prionty of a task
Return priority of a task

Interrupt Management
KN_seLinterrupt
KN_stop_scheduling
KN_starLscheduling

KN_reseLalarm
KN_deletELalarm
KN_geLtlme
KN_seLtlme
KN_tlck

Put calling task to sleep
Create and start virtual alarm
clock
Reset an existing alarm
Delete alarm
Get time
Set time
Notify kernel that clock tick has
occurred

Intertask Communication and Synchronization
KN_create_semaphore
KN_delete_semaphore
KN_send_unit
KN_receive_unlt
KN_creatELmailbox
KN_delete_mailbox
KN_send_data
KN_send_prionty_data

Create a semaphore
Delete a semaphore
Add a unit to a semaphore
Receive a unit from a
semaphore
Create a mailbox
Delete a mailbox
Send data to a mailbox
Place (Jam) prioritr message at
head of message queue
Request a message from a
mailbox

Memory Management
KN_create_pool
KN_delete_pool
KN_create-6rea
KN_deletELarea

Create a memory pool
Delete a memory pool
Create a memory area from a
pool
Return a memory area to a
memory pool
Get a memory pool's attributes

Descriptor Table Management
KN_geLdescriptor
_attributes
KN_seLdescriptor
-6ttributes
KN_initialize_LDT
KN_nulLdescriptor

Get a descriptor's attributes
Set a descriptor's attnbutes
Initialize local descriptor table

(LOn
Overwnte a descriptor with the
null descriptor

1 System

KN_translate_ptr

82380, 82370, and 8259A PIC Management
KN_initialize_PICs
KN_mask....slot

Specify interrupt handler
Suspend task switching
Resume task switching

Time Management
KN_sleep
KN_creatELalarm

KN_geLdatELselector
KN_geLcode_selector

Task Management
KN_create_task
KN_delete_task
KN_suspend_task
KN_resume_task
KN_seLpnority
KN_geLpriority

KN_ptUo_linear

calls Copyright<:> 1987,1988 Intel Corporation.

Allows application to be divided
into multiple subsystems when
application Interfaces to Kernel
through a call gate
Convert a linear address to a
pOinter
Convert a pointer to a linear
address
Get the selector for the data
segment
Get the selector for the code
segment
Converts a pointer that will be
based on a user·speclfled
selector

KN_new_masks
KN_geLslot

Initialize the PICs
Mask out interrupts on a
speCified slot
Unmask interrupts on a
speCified slot
Signal the PIC that the Interrupt
on a speCified slot has been
serviced
Change interrupt masks
Return the most important
active interrupt slot

82380, 82370, and 8254 PIT Management
KN_initializELPIT
KN_starLPIT
KN_geLPILinterval

Inltlalize a PIT
Start PIT counting
Return PIT interval

80387 and 80387SX Numeric Coprocessor
Management
Initialize an 80387 or 80387SX
Numenc Coprocessor

MULTIBUS® " Message Passing Management
KN_initiallze.JTlessage
_passing
KN_mp_working_storage
_size
KN_send_tp
KN_attach_receive
_mailbox
KN.:.canceUp
KN_send_dl
KN_attach_protocol
_handler
KN_cancel_dl

Initialize the message passing
module
.
Compute size of work space
needed for message passing
Send a transport message
Attach a receive mailbox
Cancel a solicited message or
request-response transaction
Send a data link message
Attach a protocol handler
Cancel a data link buffer
request

MULTIBUS® " Interconnect Space Management
KN_initialize_interconnect Initialize the interconnect
module
KN_geLinterconnect
Get the value of an interconnect
register
KN_seLinterconnect
Set the value of an interconnect
register
KN_locaLhosLiD
Get the host 10 of the local host

ORDERING INFORMATION
Order Code

Product

Contents

RMK

iRMK Version 1.2
Development Software

iRMK Version 1.2 Kernel

RMKDEVP
RMKDEVC

iRMK Version 1.2
Developer's Kit

IRMK Version 1.2 Kernel
PLIM 386 or iC 386 Compilers
ASM 386 Assembler
RLL 386 Utilities

SSC-430

Technical Information
Phone Support

CONSULT/DAILY
CONSULT/LT

Phone support
;Comments Magazine, Troubleshooting Guides
On- or off-site consulting on iRMK 1.2 Kernel or other Intel products by Intel systems
engineer. Available on a daily or long term basis.
iRMK Real-time Kernel

Customer Training Workshop

80386 Programming Using
ASM 386

Customer Training Workshop

80386 System Software

Customer Training Workshop

80386 System Hardware
Design

Customer Training Workshop

7·20

iRMX® OPERATING SYSTEM FAMILY

The iRMX® family of operating systems provides designers with the world's most
advanced real-time software for designs based on the Intel 8086/88, 80186/88, 80286,
386'", and 1486TO family microprocessors. The product of twelve years of real-time
expertise by Intel, IRMX software provides high-performance response to external events,
excellent support of special-purpose hardware, and sophisticated real-time programming
facilities.

A COMPLETE FAMILY OF REAL· TIME OPERATING SYSTEMS
•
•
•
•

Multiprocessing support
Multiple tasks and multiple jobs
Multiple users
On-target development

• Pnority based and/or round robin
scheduling
• User-extendable object oriented
architecture

SOFTWARE WITH A FUTURE
• Leading real-time microprocessor
software with over 6000 licenses sold
• Active iRMX Users Group (iRUG) with
worldwide chapters, a regular
newsletter, and an annual technical
convention
• Applications easily migrated from IRMX
I to IRMX II to IRMX III
• Application software from third-party
sources

• Future 8086, 80186, 80286, 386, and
1486 family processor support by iRMX
operating systems.
• Optional networking to systems running
the MS-DOS, VAXIVMS, UNIX, XENIX,
iNDX, iRMX I, iRMX II, and iRMX III
operating systems

____________________

i~·
0:>

Intel Corporation 1989

7-21

October, 1989
Order Number 280109-001

iRMX® OPERATING SYSTEMS
SUPPORT FOR THE FULL RANGE OF
REAL· TIME APPLICATIONS
The iRMX operating systems support the full range of
real-time applications, from embedded control
designs to reprogrammable systems which require
dynamic creation, deletion, and priority arbitration of
tasks. This flexibility makes it possible to save
substantial staff retraining and software maintenance
costs by using a single operating system for many
different real-time systems and subsystems. Users
have shown that the iRMX operating systems are
ideal for such applications as:
avionics
communications
data acquisition and analysis
energy management
factory automation
financial trader workstations
image processing
machine control

manufacturing test
medical instruments
process control
railroad control
missile controls
satellite
communications
simulation
transaction processing

REAL· TIME SOFTWARE FOR REAL· TIME
APPLICATIONS
Real-time applications are easier to develop with realtime software. Operating systems designed for
general business use typically lack essential real-time
features, so real-time application development is often
expensive, difficult, or even impossible. In contrast,
iRMX software is real-time software designed to make
the development of real-time applications easy and
successful. Attributes offered by the iRMX software
include:

High performance
For real-time applications, iRMX software is many
times faster than general purpose operating systems.
This high performance enables applications based on
the iRMX operating systems to keep up with the rapid
data and control flow of machine and communication
interfaces.
A rich set of real-time programming facilities
The iRMX software includes a rich set of real-time
programming facilities that are usually missing in
whole or in part from non-real-time operating
systems. These facilities include:
• preemptive, priority-based scheduling with round
robin (time slice) scheduling within a priority level
• interrupt management with standard or userdefined exception handlers
• support for multiple tasks
• inter-task communication through mailboxes and
semaphores
• deterministic program execution
• control of cntlcal resources through regions
Support for designs based on Intel systems,
single board computers, and components

7-22

Excellent support for special purpose hardware
Most real-time applications involve some special
purpose hardware, and gen~ral purpose operating
systems are often relatively monolithic and difficult to
interface to this hardware. The iRMX operating
systems are highly configurable, modular software
systems which easily support custom hardware.
Support for special purpose hardware includes:
• the ability to configure the operating system by
layer
.
• hooks for user-written handlers at key points
• the ability to add operating system extensions
• standard device driver interfaces
More reliable code through iRMX@ II and IRMX@ ",
memory protection
When the iRMX II or iRMX III software allocates
memory to a task, it assigns a combination of read,
write, and execute-only status to the allocated code
and data segments. If the code attempts to execute
outside of this range (e.g., stack overflow) or write to
a data segment marked read-only, the operating
system will issue a "protection" error. This flag can be
used to notify an operator of the exact location in the
code where the problem occurred. Bounds and
access rights checking, which is enforced by the
hardware, can catch, up to 90% of common coding
errors.

COMPLETE REAL· TIME OPERATING
SYSTEMS, NOT JUST A KERNEL
With comparable performance, the iRMX operating
systems provide many features that are extra-cost
items, or simply unavailable, in real-time kernels.
These features make the development of real-time
applications much easier and faster, but do not add
unnecessary overhead. In fact, all functional layers
above the nucleus are optional in the iRMX operating
systems. This flexibility allows you to include only
those features that your application requires.
The following is a brief description of the major
functional groups within the iRMX operating systems.

Nucleus
The Nucleus is the heart of the operating system and
controls all resources available to the system. The
nucleus provides key real-time features including:
• Support of multiple tasks
• Pnority based and time slice scheduling
• Dynamic priority adjustment
• Memory management
• Inter-task communication and synchronization
using mailboxes and semaphores
• Interrupt management with custom exception
handlers
• Time management
• Object management
• Addition of custom operating system extensions
• Inter-processor communication for mUlti-processor
systems

iRMX® OPERATING SYSTEMS
Basic I/O System (BIOS)
The Basic 1/0 System (BIOS) provides primitives to
read from and write to peripherals. The BIOS also
sets up the file structures used by the system and
provides access to all required peripherals through a
standard device driver interface. Both synchronous
and asynchronous system calls are supported. Many
device drivers are provided with the iRMX operating
systems, and custom device drivers and file drivers
may be added by the user.
Extended 110 System (EIOS)
The Extended I/O System (EIOS) provides similar
services to the BIOS, with simplified calls that give
less explicit control of device behavior and
performance. The software supports synchronous
system calls and provides automatic buffering of 1/0
operations. The EIOS also provides a logical-tophysical device connection, and allows 11 program to
specify a logical address for output.
Application Loader
The Application Loader is used to load programs
from mass storage into memory, where they execute.
Programs may be loaded under program or operator
control.
Bootstrap Loader
The Bootstrap Loader is used to load the operating
system or an iRMX application from mass storage
into memory, and then to begin the system's
execution.

Universal Development Interface (UDI)
The Universal Development Interface provides an
easy-to-use interface with a standard set of system
calls to allow programs and languages to be easily
transported to or from the iRMX operating systems to
other operating systems which support the UDI
standard. For example, UDllets IRMX host MS DOSbased tools.
System Debugger
The System Debugger is used to debug applications
and give a view into the system itself. A static
debugger provides a view of system objects. Sourcelevel debuggers are separately available.
Human Interface
The Human Interface allows multiple users to
effectively develop applications, maintain files, run
programs, and communicate with the operating
system. It consists of a set of system calls, a set of
commands, and a Command Line Interpreter.
Commands are available for file management, device
management, and system status. Features include
dynamic log-on, full line editing, user extensions, and
support for background jobs. In addition, the
Command Line Interpreter may be replaced for
special applications. For example, a Computer Aided
Tomography (CAT) scanner controlled by an iRMX
operating system could use a custom Command Line
Interpreter to allow the operator to direct the
movement of the scanner.

APPLICATION LOADER

USER APPLICATIONS

Figure 1: iRMX® Operating System Functional Elements

iRMX® I OPERATING SYSTEM
The iRMX I Operating System is the system first
developed for real-time operating system support of
the 8088 and 8086 microprocessors. It has become
today's most widely accepted real-time operating
system for microcomputers. Its features include:
• 16-bit operating system; uses 8086 instruction set
and 8086 compilers
.
• Microprocessors: 8088, 8086, 80186, 80188;
80286, 386, i486 (Real address mode)
• Math co-processors: 8087, 80287, 387TH
• Memory management: up to 1 MB, Real address
mode

• Applications can be written using C, FORTRAN,
Pascal, and PUM compilers and assembler
available from Intel.
• Ideal for embedded, nucleus-only applications,
optimized for speed and compactness
• Applications can be easily upgraded to iRMX 11and iRMX III-based designs
• For MULTIBUS I and custom designs
• Development on iRMX or MS DOS hosts
• iRMX-hosted development

iRMX® II OPERATING SYSTEM
The iRMX II operating system features include:
• 16-bit operating system; uses 80286 instruction set
and 80286 compilers
• Microprocessors: 80286, 386, i486
• Math co-processors: 80287, 387
• Dynamic memory management: up to 16 MB,
16-bit Protected address mode

• Applications can be written using C, FORTRAN,
Pascal, and PUM compilers and assembler
available from Intel.
• Applications can be easily upgraded to iRMX 111based designs or back ported to iRMX I.
• For MULTIBUS I, MULTIBUS II, AT-Bus, and
custom designs

iRMX® III OPERATING SYSTEM
The iRMX III operating system is a compatible
derivative of the iRMX II operating system. The 32-bit
functions let users gain the 32-bit power of the Intel
386 and i486 microprocessors. The iRMX III
operating system handles 32-bit math and segments
up to 4 gigabytes, retaining protection.
Binary compatibility with iRMX II lets iRMX II users
easily move their applications to 32-bits on iRMX III
with the 386 and 387 or i486 processors: Most 16-bit
applications run without change; selected parts of an
application can be moved to 32-bits while others
remain unchanged. Its features include:
• 32-bit operating system; uses full 386/387
instruction set
• Microprocessors: 386, i486

7-24

• Math co-processor: 387, 2-5 times faster than 286
CPU-based math co-processor
• Dynamic memory management: up to 4 GB,
segmented or flat, 32-bit Protected mode
• 32- and 16-bit tasks can run concurrently with full
inter-task communication·
• Applications can be written using C, FORTRAN,
and PUM compilers and assembler available from
Intel.
• Custom device drivers and custom interrupt and
exception handlers need to be 32 bits.
• For MULTIBUS I; MULTI BUS II; 386 CPU-based,
AT-bus personal computers; and custom designs.
• PC support includes all Intel300-series 386-based
AT platforms.

iRMX® FAMILY COMPATIBILITY

I iRMX®1

I iRMx®n

I iRMX® III

INTEL SYSTEMS
System 310 Family
System 320 Family

System 120 Family
System 320 Family
System 520 Family

System 120 Family
System 320 Family
System 520 Family
Systems 301, 302, 300SX

MULTIBUS®I SINGLE BOARD COMPUTERS
iSBC 86/C38
iSBC 86/05A
iSBC 86/12A
iSBC 86/30
iSBC 86/35
iSBC 186/03A
iSBC 186/51
iSBC 188/56
iSBC 286/1 OA"
iSBC 286112"
iSBC 286/14"
iSBC 286/16"
iSBC 386/12"
iSBC 386/12S"
iSBC 386/2X"
iSBC 386/3X"

iSBC 286/1 OA
iSBC 286/12
iSBC 286/14
iSBC 286/16
iSBC 386/12
iSBC 386/12S
iSBC 386/2X
iSBC 386/3X

iSBC 386/12
iSBC 386/12S
iSBC 386/2X
iSBC 386/3X

MULTIBUS®/1 SINGLE BOARD COMPUTERS
iSBC 28611 OOA
iSBC 386/116
iSBC 386/120
iSBC 386/258
iSBC 386/133
iSBC 486/125

iSBC 386/116
iSBC 386/120
iSBC 386/258
iSBC 386/133
ISBC 486/125

INTEL MICROPROCESSOR DESIGNS
8086,8088,80186,80188,
180286, 386, i486
80286",386", i486*
8259A Programmable Interrupt Controller
8254 or 8253 Programmable Interval Timer
8274, 8251A, and 82530 senal controllers
8255 parallel interface
Necessary memory
"Real address mode with 8086 instruction set

7-25

1386, i486

iRMX® AND MULTIBUS®II SYSTEMS
MULTIBUS®/1 HARDWARE AND
iRMX® SOFTWARE BUILD HIGHPERFORMANCESVSTEMS

Multiprocessor IRMX® Systems

With iRMX II and iRMX III software and other software
from Intels family of real-time software products,
engineers can design complex, high-capability
systems with a minimum of custom code. An
example is the system shown in figure 2. This system
has a single iSBC 386/258 peripheral controller
board that functions as both a boot server and file
server to multiple CPU boards in the system. File
transfers are handled via the iSBC 186/530 Network
Interface Adapter, which also provides an Ethernet
network connection. The iSBC 186/410 terminal
controller board uses communication software that is
downloaded from the system disk. The iSBxm 279
Display Subsystem, together with iRMX Virtual
Terminal software, provides access to any processor
in the system via a single console displaying multiple
windows.

MULTIBUS®II systems, which pass data over the bus
using high-speed messages, enable engineers to
easily assemble high-performance multiprocessor
systems. Bus arbitration problems are virtually
eliminated and slower speed 110 boards cannot slow
down data transfer across the bus since all data is
passed at the full bus bandwidth of 40 MBytes/
second.
Nucleus Communications Service

The Nucleus Communications Service provides the
software interface between application code and the
MULTIBUS II message-passing coprocessor. This
software simplifies the job of sending messages
between tasks on different boards and provides a
standard software interface to any other MULTI BUS II
board in the system.

To Local Terminals
or Modems

OpenNET m
Local Area Network

#3
#2
ISBC"
186/410
Bootserverl
Flleserverl
CPU

Main
System
Console

#1
ISBC"
386/133

.ISBC"
186/530

Terminal
Controller

Network
Interface
Adapter

MULTIBUS"II System Bus-40 MB/sec. Data Transfer Rate

Figure 2: MULTIBUS®II iRMX® II Multiprocessor System

7-26

CPU
Boards

ON-TARGET DEVELOPMENT
A CONVENIENT WAY TO DEVELOP REALTIME APPLICATIONS
Designers familiar with both cross development and
on-target development agree that on-target
development is an easy, reliable ~ethod fo~
..
developing applications. Testing IS greatly simplified,
and you need to become comfortable with only one
operating system.
The iRMX operating systems provide solid on-target
development capability-a capability entirely missing
from other real-time software for microprocessors.
Developers can use the full, rich feature set of the
iRMX operating systems for de.velopment,. and. then.
include only a minimum set of IRMX functions In their
final applications. As a result, your final application
receives the benefits of on-target development
without the overhead that general purpose operating
systems incur.
Included with the iRMX operating systems
• Interactive Configuration Utility (ICU)-a tool that
can be used to generate a custom version of the
operating system to match exact system
.
requirements. The ICU automates the. other:"'lse
time consuming and error prone configuration of
the system. The ICU accepts the user's system
parameters and requir~ments, then b.uilds a
command file to compile, assemble, link, and
locate necessary files.

• A Human Interface supporting multiple users
• Over 50 Human Interface commands for system
status, device management, and file r:nanagement
• A Command Line Interpreter supporting
background jobs and full line editing
• Hardware traps to catch up to 90% of typical
programming errors for iRMX II on iRMX
applications
• System Debugger
• Bootstrap loader with debug option
• Parameter and data validation of operating system
calls
• Universal Development Interface
• Numerous device drivers for Intel boards
Other development facilities are available
separately for use with the iRMX® operating
systems
•
•
•
•

Re-entrant languages
Assembly- and source-level debuggers
Development utilities
Graphics software for the iSBX'" 279 subsystem
graphics controller (iRMX II and iRMX III)
• iPAT Performance Analysis Tool
• In Circuit Emulators, hosted on an IBM PC-AT or
equivalent, to aid in hardware debugging and
software tracing
.
• A variety of user-supplied utilities and speCial
software available from the iRMX Users Group
(iRUG)

iRMX® LANGUAGES
FULL LANGUAGE SUPPORT FOR iRMX®
SYSTEMS
Intel has the languages you will need to develop a
wide range of high-performance applications. iRMX
languages include C, PUM, FORTRAN, Pascal, and
Assembler. iRMX language compilers run on an Intel
300 or 500 series microcomputer or System 120, and
can be used for MULTIBUS®I or II target systems or
embedded applications.
In addition to the wealth of languages available.
iRMX-based systems are complemented by utilities
with which to create and manage object modules.
For the iRMX II and iRMX III systems, utilities are
provided that allow system programmers to initialize

and manage the memory protection features of the
80286, 386, and i486 transparently to the
applications programmer. This latitude in
.
configurj:lbility allows programmers to team their .
efforts in order to achieve a shorter development time
than would otherwise be possible.
Because the high-level languages are actually
resident on the iRMX-based system and can be
licensed on a development license or pass-through
license OEMs can pass application software directly
on to e~d users. End users may then tailor the OEM's
system to better meet application needs by writing
programs using the same languages.

7-27

iRMX® LANGUAGES
Language./ndependent Application Development
Intel's Object Module Format (OMF) enables several
users to write different modules of an application in
different languages, then link them together. Users
can choose exactly the right language tools for
specific pieces of the application, rather than
compromising specialized tasks for the sake of one
project-wide language.
Fast, Lean Programs for Rapid Processing
iRMX operating system calls are made directly from
C, FORTRAN, Pascal (iRMX I and II), and PLIM. This
means that application developers can take full
advantage of the iRMX multi-tasking capability,
whereby multiple applications execute concurrently
on the operating system.
Application code can be easily transported across
processor architectures to yield increased
performance. For example, 8086 object code will
run on the 80286, 386, and i486 processors.

Standardized Math Support
All iRMX languages support floating point operations.
This ensures universal consistency in numeric
computation results and enables the user to take
advantage of the Intel 8087, 80287, and 387
Numeric Data Processors.

CLANGUAGE
The C programming language is known for its
flexibility and portability. It is a block-structured, highlevel language that is ideal for developing mUlti-user,
multitasking, virtual memory operating systems to run
in protected mode of the 80286, 386, and i486
processors.
Intel C compilers provide many substantial benefits to
software developers, including:
• Bullt·in functions. Allow highly optimized code
and eliminate the need for in-line assembly. With
built-ins you can enable interrupts or directly
control hardware I/O from the high level language.
• Symbolic debug information. Intel C compilers
provide extensive symbolic debug information
to speed development with an ICE or SoftScope debugger.
In addition, runtime libraries include the STOIO
library, conversion routines, string manipulation
routines, routines for performing 32-bit arithmetic and
floating-point operations, and routines that provide an
interface to the operating system.
The iC 86 compiler is a new generation C compiler
providing high performance for embedded
microprocessor designs. In addition to the features
above, this compiler has the ability to mix memory
models with "near" and "far" pointers. iC 86 is
compatible with other ANSI C standard compilers
and PLIM providing both standard C and PLIM
calling conventions and has four optimization levels.
iC 286 supports the 16 MB physical address space of
the 80286
7-28

and embles programs to use 80286 features such as
protection and virtual memory. It is upward
compatible with iC 86.
iC 386 supports the full 4 Gigabyte physical address
space of the 386 and enables programs to use new
80386 features, such as memory paging. It
manipulates bit fields, pointers, addresses, and
registers, enabling programs to take full advantage of
the fundamental concepts of the 386 and i486
microprocessors. It is upward compatible from iC 86
and iC 286.

FORTRAN LANGUAGE
FORTRAN has long been the industry-standard
programming language for numerical processing
applications. FORTRAN 86 meets the ANSI
FORTRAN 77 Language Subset Specification and
includes many features of the full standard. It
supports single-precision (32-bit), double-precision
(64-bit), double-extended-precision (80-bit), complex
(two 32-bit), and double-complex (two 64-bit) floatingpoint data ty"pes. Floating-point operations can be
performed with software or with numeric
coprocessors, such as the 8087,80287, and 387. In
addition, FORTRAN 86 has microprocessor
extensions for performing direct byte- or wordoriented port I/O, developing reentrant procedures,
and creating interrupt procedures.
• Features high-level support for floating-point
calculations, transcendentals, interrupt procedures,
and run-time exception handling
• Meets ANSI FORTRAN 77 sl,Jbset language
specifications
• Produces standard Intel 8086 object modules that
can be compiled separately, linked to programs
written in any Intel 8086 language.
• Supports the IEEE floating-point math standard
with 8087, 80287, and 387 coprocessors
• Supports arrays larger than 64K byte~

PASCAL LANGUAGE
The Pascal compilers provide a complete
implementation of the ISO proposed standard for
Pascal for 8086, 80186, 80286,386, andi486
microprocessors. In addition, the Intel Pascal
compilers contain extensions to standard Pascal that
tailor the resulting code to fit microcomputer
applications. There are extensions for interrupt
handling and port I/O. Predefined type extensions
also allow you to specify the precision of real, integer,
and unsigned calculations; check errors on 8087 or
80287 operations; and circumvent the type checking
on calls to non-Pascal routines.
The following characteristics are common to Intel
Pascal packages:
• Offers strict implementation of ISO standard Pascal
• Contains extensions to the ISO standard that are
essential for microcomputer applications
• Allows separate compilation with type-checking
enforced between modules
• Has compiler option to support full run-time rangechecking
• Supports large array operation

iRMX® LANGUAGES
PUM LANGUAGE

ASSEMBLERS

The PLiM language is a structured language created
specifically as a system development language for
Intel microcomputers. It provides the advantages of
a high-level language with the power of assembly
language. PLiM is an excellent alternative to C in, for
example, I/O-intenSive applications. PLiM does not
require a run-time environment and thus can produce
highly optimized code. In 80286, 386, and i486
systems, PLiM is ideal for developing mUlti-user,
multitasking, virtual-memory operation systems to run
in protected mode. It is easy to learn and use, yet It
allows complete access to the processor and it
produces code whose efficiency rivals that of
assembly language.

The Assemblers and Relocation/Linkage packages
provide the tools that assembly-language
programmers need to maintain complete control
over the 8086, 80186, 80286, 386, and i486
microprocessors. The assembly languages are
strongly typed, providing extensive checks on
variables and labels. ThiS helps catch many
programming errors long before the debugging
cycle. Macro facilities are also available to speed
and simplify your work.

The following characteristics are common to Intel
PLiM packages:
• Produces code whose efficiency rivals that of
assembly language
• Has a block-structured syntax that encourages
program modularity
• Requires fewer source statements than any other
high-level language
• Has built-in syntax checker
• Allows foreign character sets in comments and
strings
• Object code across multiple hosts is Identical
Three PLiM compilers are available: PLiM 86 for
16-bit real address mode applications; PLiM 286 for
16-bit protected mode applications; and PLiM 386 for
32-blt applications. The compilers are upwardly
compatible with each other. As a result, applications
can be easily upgraded from PLiM 86 to PLiM 286 to
PLiM 386 with only minor changes to the source
code.

AEDIT

The relocation and linkage packages make your
programs ready to run. They link programs together,
assign absolute addresses, gather modules into
libraries, and perform other system functions.
Assembler 86, 286 and 386:
• Are highly mnemonic and compact, and are
strongly typed to detect errors at assembly time
• Place high-level symbolic information In object
modules to enable symbolic debugging
• Have powerful text macro facility with three macro
listing oplions, including string functions, and can
expand conditional assembly pseudo-ops
The Relocation/Linkage Packages:
• Resolve PUBLIC/EXTERNAL references and
perform intermodule type checking
• Select required modules from libraries to satisfy
symbolic references and proVide fast, easy
management of object module libraries
• Simplify debugging by producing detailed maps
that show references between program modules

LIBRARIES:
LIB 8§/286 MODULES
IRMX I, IRMx@n,IRMx"IIIINTERFACE
COMPILER RUN TIME

SOURCE
FILE

LINK!
BIND

OBJECT
CODE

IRM~I
IRM~II
IRM~III
INTERACTIVE
CONFIGURATION
UTILITY

ISDMTM, 1M, SOFT-SCOPE'
DEBUGGERS

IRM~I, IRM~n, IRMX@III
OPERATING SYSTEM
LIBRARIES

IRM~I, iRM~n, iRMX@1II

BOOTSTRAP LOADERS

Figure 3: iRMX® Operating Systems Development Environment

PROM

SOFT·SCOPE* HIGH·LEVEL DEBUGGER
COMPLETE HIGH-LEVEL DEBUGGING
For real-time applications development professionals
want to focus on original source code for most
debugging operations. The Soft-Scope debuggers
do just that. They integrate the original source code
into the debugging process directly. All breakpoint
prompts and high-level stepping operations prompt
with original sOl!rce code rather than reporting what
line number the program has reached or what
assembly instruction is next.
Source Code Interface and On-Line Listings
The source code interface frees the programmer from
having to divide attention between the console and
program listings, eliminates the need to get a fresh
program listing each time a small change is made,
and reduces the time needed to make software
modifications.

Automatic Expansion of Data Types
Symbols declared in the program are accessible by
name for display and modification of contents. These
symbols include arrays, structures, static variables,
based variables, and stack-based variables (including
local variables, re-entrant variables, and passed
parameters). Memory can also be displayed with
absolute references or with register-relative
references.
Symbolic Display of All iRMX® System Objects
The VIEW command allows viewing the status of any
iRMX object including tasks, jobs, mailboxes,
semaphores, regions, and segments. With VIEW, the
stack of a task can be examined to determine which
iRMX call the task has made most recently. Any job's
object directory and the list of ready and sleeping
tasks can be examined.

Handling of 80286, 386"', and 1486'" Protection
Traps and Software Exceptions
Exception Handling: The exact source line which
causes an exception can easily be reached and
displayed. All environmental and programmer
exceptions are trapped and reported, without
causing a Soft-Scope debugger exit.
Most of the 80286/386/i486 hardware traps are
handled by the Soft-Scope debuggers, including
Bounds Check (INT 5), Invalid Opcode (INT 6),
Double Fault (INT 8), Stack Fault (INT 12), and
General Protection (INT 13). Upon encountering one
of these interrupts, the debugger breaks execution
with a message similar to the following:

<'General Protection fault (INT ,13)
[ Break near line #145 in TESTPROC
(:TESTMODULE) ]
145: ARRAYX(INDEX)=XYZj

In the above example, the General Protection trap
could have been caused by the variable INDEX
being too large for the segment which contained
ARRAYX, or by ARRAYX being based on an
undefined pointer. Because the debugger handles
these traps directly, other users in a multi-user system
wonl even be aware in most cases that there was a
hardware fault.
Soft-Scope debuggers are available for iRMX I,
iRMX II, and iRMX III designs. The Soft-Scope II and
Soft-Scope III debuggers are available directly from
Intel. The Soft-Scope I and Soft-Scope III debuggers
are available from Concurrent Sciences, inc.

Second Terminal Option
Because so many applications are screen-intensive,
the Soft-Scope Debuggers allow the option of using a
second terminal for all debugger 110, freeing the main
console for exclusive use by the application for
application output.
Multi-Tasking Support
The Soft-Scope debuggers support simultaneous
debugging of concurrent tasks when they are all
linked together as a Human Interface command and
each concurrent task is coded in a separate module.
The debugger loads and then allows the user to
suspend and resume execution of the tasks from the
command line with the SUSPEND and RESUME
commands. In this way the developer CCln observe
the effect of dynamic changes on the software under
test.

7-30

iSDMTM MONITOR
ASSEMBLY-LEVEL DEBUGGING
The user can use the iSDM monitor package to load
programs into the target system from the
development system, execute programs in an
instruction-by-instruction manner, and add custom
commands through the command extension
interface.

Powerful Debugging Commands
The iSDM Monitor contains a powerful set of
commands to support the debugging process on
Intel 16- and 32-bit microprocessors. Some of the
features included are: bootstrap of application
software; selective execution of program modules
based on breakpoints or single stepping requests;
examination, modification, and movement of memory
contents; examination and modification of CPU
registers, including NPX registers; and disassembly
of instruction set code. All results are displayed in
clearly understandable formats.
Two versions of iSDM are available. iSDM II supports
16-bit code debug on 80861186, 8088/188, 80286,
and 386 processors. iSDM III supports 16- and 32-bit
code debug on the 386 and i486 processors for
iRMX III applications.

Numeric Data Processor Support
ArithmetiC applications utilizing the 8087 or 80287
Numeric Processor ExtenSion (NPX) are fully
supported by the iSDM Monitor. In addition to
executing applications with the full NPX performance,
users may examine and modify the NPX's registers
using decimal and real number format.
This feature allows the user to feel confident that
correct and meaningful numbers are entered for the
application without having to encode and decode
complex real, integer, and BCD hexadecimal formats.

Command Extension Interface
The Command Extension Interface (CEI) allows the
addition of custom commands to the iSDM Monitor
commands. The CEI consists of various procedures
that can be used to generate custom commands. Up
to three custom commands (or sets of commands)
can be added to the monitor without programming
new EPROMs or changing the monitor's source code.
Program Load Capability
The iSDM loader allows the loading of 8086, 8088,
80186, 80188, 80286, 386, or i486 CPU-based
programs into the target system. It executes on an
iRMX development system and communicates with the
target system through a serial link, a parallel link, or a
fast parallel link.
Configuration Facility
The monitor contains a full set of configuration facilities
which allows it to be carefully tailored to the requirements of the target system. Pre-configured EPROMresident monitors are supplied by Intel for most
MULTIBUS®I and MULTIBUS II CPU boards. iRMX I
and iRMX II system users may use the configuration
facilities to include the Bootstrap Loader (V5.0 or
newer) in the monitor. iSDM can be easily configured
for custom hardware.
The iSDM III monitor IS preconfigured to be loaded
with iRMX III. The user can configure 1/0 devices to
be used by the monitor. iSDM III runs on any
hardware iRMX III runs on.
The iSDM Monitor does not require the use of a
development system. The monitor can be used by
simply attaching a·stand-alone terminal to the target
system.
iSDM II is available as a separate product. The iSDM
III monitor is included with the iRMX III operating
system.

iM III MONITOR
The iM III monitor is a 32-bit debugging tool for the
Intel 386 family processors: 386 and i486
microprocessors, and 387 co-processor. The tool
gives the user visibility into 386-or i486 CPU-based
hardware as the software executes. Although
developers use iM III primarily for software
debugging, they also find it useful for finding and
solving hardware problems.
The monitor is highly configurable, so that users can
shape it to fit the unique needs of their applications.
The basic monitor provides raw debugging facilities,
with a variety of ways to interact with the user's
application code. The default configuration in the
monitor package is ready to be programmed into
EPROMs. It supports debugging on Intel's 386- and
i486 CPU-based boards.
The package includes source code to let users
prepare their own custom debugging routines. And

configuration source code lets them configure the
monitor to work on their own target systems. The
custom code may be programmed into EPROMs or
built into boot-Ioadable files. The iM III monitor also
works with the Soft-Scope III high-level debugger.
Capabilities the iM III monitor gives its users include:
• Interact with the monitor from a terminal, from a
host computer, or from a program running on the
target system.
• Use a built-in set of monitor commands or replace
or add commands during execution.
• Change the console controlling the monitor at any
time.
• Redirect data from one console to another.
• Add functionality or change the user interface by
intercepting calls to the monitor.
• Switch from one task to another.
• Develop a high-level debugging program that uses
the monitor as a kernel.
7-31

AEDIT EDITOR
AEDIT is a full-screen editor designed specifically for
software engineers and writers. It has many features'
that make it ideal for progr.am editing. For example, it
lets you switch between files instantly, and its splitscreen windowing capability enables you to view two
files at once. It has a macro facility that you can use
to combine multiple functions into a single command.
These macros can be created in two ways: by using
AEDIT's "learning" mode to store your keystrokes or
by using the powerful macro language. You can also
use and modify the extensive library of macros
provided with the editor.
With these and other features, such as contextsensitive command menus and shell escape to the
operating system, AEDIT is the complete programediting tool.
• Allows full screen editing of source code and
documentation

• Provides a full range of editing support, from
document proces.sing to hexadecimal code entry
• Supports macros for repetitive or complex editing
tasks
• Provides a powerful macro language for
developing "smart" macros
• Supports dual-fi!e editing with optional spilt-screen
windowing
• Allows unlimited file size and line length
• Offers quick response with easy-to-use, contextsensitive command menus
• Is configurable and extensible for complete control
of the editing process, yet remains easy to learn
and use
• Supports documentation preparation with
paragraph filling and justification options
• Provides shell escape function for access to
operating system commands

iPATTM PERFORMANCE ANALYSIS TOOLS
iPATTM, Intel's Performance Analysis Tool, helps
engineers control the performance and reliability of a
software-driven system by showing, via histograms
and tables, the real-time execution activity of software
in terms of range names or addresses.
• Provides real-time performance and code
coverage analysis non-intrusively with 100%
sampling
• Displays Information using histograms or analysis
tables
• Accepts specification of ranges with addresses,
program symbolic names, or user-defined symbolic
names
• Performs disarm/arm analysis on called
subroutines, external interrupts, interrupt routines,
operating system functions, or any execution
address or range

7-32

• Hosted on PC/XT and PC/AT systems, using a
serial link for target communications
• Presents an easy-to-use human interface, including
function keys and color/monochrome graphics
• Available for 8086/88, 80286, and 386
microprocessors.
The iPAT products consist of DOS-hosted control and
display software, plus appropriate microprocessor
probes which replace the microprocessor In the
target system. The iPAT 386 also can be operated in
piggy-back fashion with the InteIICE-386/25 in-circuit
emulator in prototype systems at speeds up to 20
MHz. All iPAT products use an iPAT core base
system, which also can be attached to ICE-186 or
ICE-286 in-circuit emulators.

iRMX® TOOLBOX
ASSISTANCE FOR iRMX® PROJECT
DOCUMENTS
The iRMX toolbox is a set of utilities to provide
assistance to the software developer in text
processing and document preparation.

Text Formatting (SCRIPT)
The SCRIPT utility is a text formatting program that
streamlines document formatting and preparation.
Commands include facilities to do paging, centering,
left and right margins, justification, subscripts,
superscripts, page headers and footers, underlines,
boldface type, upper and lower case, etc.
Input text which has been prepared using the AEDIT
text editor can be formatted using the SCRIPT utility.

Spelling Verification (SPELL, WSORT)
The SPELL utility finds misspelled words in a text file.
The included dictionary can be expanded by the user
for specialized vocabularies. This utility can be used
interactively or in a batch mode.
File Comparisons (COMP)
The CaMP utility performs line oriented text file
comparisons showing changes between text, source,
or object files.
Sort (ESORT, HSORT)
Files can be sorted on multiple keys (or fields) in
ascending or descending order and the resultant
sorted files stored.

iRMX® SOURCE CONTROL SYSTEM
SOFTWARE VERSION MANAGEMENT
The iRMX Source Control System (SCS) provides an
integrated version control and generation
management system for users in an iRMX software
development cycle. This facility IS useful for large and
small software projects to assist in bringing more
control, order and methodology to the software
development process. SCS can be effectively used
on a single iRMX System or across the OpenNETTM
network. It can be utilized by developers using any of
the popular iRMX languages-PUM, Assembler,
FORTRAN, C, Pascal or other special language
requirements.

Controls Access to Source Files
With iRMX Source Control System the system
manager has certain privileged commands. These
commands can be useful to designate those team
members who can access the source files only for
object generation and those who can access the
source files for updating or changing. Other such
priVileged commands include the ability to archive a
specific version of source and combine several
versions of a source file.

7i'acks Changes to Source Files
The iRMX Source Control System keeps track of
changes made to any source files. These changes
are stored as backward deltas for disk economy and
fast access to the latest version. The project team can
now better interact and synchronize using the latest
updated version for integration and testing. The
specific versions of tools used to produce the source
code is also tracked.
Approachable and Efficient
The iRMX Source Control System has a tutorial, menu
interface, and on-line help facility that help make it
very approachable by the user.

7-33

iRMX® DEVELOPMENT PLATFORMS
ONE OPERATING SYSTEM; A CHOICE OF
BUS ARCHITECTURES
Intel has integrated iRMX development software into
systems based on the PC AT bus, MULTIBUS I, and
MULTIBUS II, all using the power of the Intel 38632bit microprocessor. These systems are available in
configurations suited for software development and
target systems.
Compatibility of iRMX-based software across buses
makes it easy to move applications among System
120, System 320, System 520, and user-built systems
based on AT-Bus, MULTI BUS I, and MULTI BUS II.
This flexibility lets the user select from a spectrum that
ranges from AT-bus price to minicomputer
performance and functions.

Assembler, AEDIT, and a source level debugger, SoftScope, and an interface manager that can be used
as a front end to applications.

DOS Application Compatibility
The System 120 supports the DOS 3.X and later
operating systems as well as iRMX II and III, enabling
you to use popular DOS applications to process data
collected in real time. Many common applications are
already available from software vendors. The
applications include data bases, menu systems, and
device drivers. The System 120 hard disk can be
divided into iRMX and DOS partitions, allowing users
to boot from either partition. A System 120 utility
allows transfer of iRMX files to a DOS disk. DOS
execution requires a customer-supplied version of
DOS, a video adapter, a monitor, and a keyboard.

SYSTEM 120

SYSTEM 320

The Intel System 120 IS a 386-based, PC/AT platform
that delivers real-time capability to users demanding
a low-cost system for running time-critical
applications. The System 120 combines a PC/AT bus
configuration of Intel\; iRMX real-time operating
system and an Intel 386-based PC/AT platform.

The System 320 is based on the MULTIBUS®I architecture (IEEE 796) industry standard system bus
supported by over 200 vendors providing 2000
compatible products and the iRMX® operatingsystems, composed of modular layers, highly
configurable for tailoring to target applications. A
Wide range of popular industry standard high-level
languages are supported for application
development. Special configurations can be tailored
by the user, by Intel\; Custom System Integration
group or by Intel\; authorized Value Added
Distribution Centers.

Low Cost PC/AT Based Configurations
The System 120 target models are available with a
number of processor speed, memory, and mass
storage options to fit a range of applications. These
include a basic system with 8 open slots, and a 40
MB hard disk system with a 387 math coprocessor
and floppy disk.
Intel offers PC/AT add-In boards for the System 120
that include: 2 MB and 8 MB 32-bit memory boards,
the OpenNET PCLlNK2 networking board and the
iPCX 344A BITBUS'M board. A standard keyboard is
also available.

Easy Application Development
You can develop applications for AT bus, MULTIBUS I
and MULTIBUS II directly on the system using the
System 120 Development Toolkit. In addition to the
IRMX II and iRMX III Operating Systems for the
System 120, the toolkit contains: PUM Compiler,
7·34

The System 320 consists of a system package which
contains a seven slot MULTI BUS cardcage, a power
supply, and three 5V4" full-height peripheral bays.
Available options include CPU, memory,peripheral
controller, operating systems, storage devices,
channel communications, host communications,
networks, productivity software and accessories.
The System 320 IS available in a wide range of
configurations based on the 386 microprocessor. All
386 based models include the 387 numeric
processor. The 386 based systems can be expected
to perform two to three times faster than the 80286
based System 310 models.

iRMX® DEVELOPMENT PLATFORMS
SYSTEM 520
The System 520 IS built around Intel's MULTIBUS®II
System Architecture (MSA) to ease the development
and integration work of MULTIBUS II OEM system
designers. MSA delivers open system interface and
protocol standards that bUild on and extend the basIc
MULTI BUS (IEEE/ANSI1296) bus standard. The MSA
specifications define diagnostics, bUilt-In self test,
system Initialization and boot loading, board
configuration, and message passing. The user
benefits from MSA because the level of vendor and
board compatibility has been raised above basic
electrical bus specifications to a set of powerful
programmatic interfaces that handle all of the details
of bus specifics with software. ThiS provides OEMs
qUicker time to market with faster system integration
and shorter design cycles.
Easy User Expansion and Re-Composable
Systems
The MULTIBUS II System Architecture is used as the
foundation for integrating Intels full line of Single
Board Computer (iSBC®) modules and iRMX II
system software into the System 520. OEMs have the
option to buy the contents of the system (I.e., the
boards, the firmware, the software, etc.) separately,
and re-compose all or part of the systems pieces into
a different configuration or enclosure.

The System is available with or without the iRMX
Operating System.

\
SYSTEM 120

A Network IN the System
Using the MULTI BUS II backplane as an ultra-fast
network (40 MB/sec), multiple peer-to-peer 386™- and
i486"'-based iRMX application processors operate as
independent "networked" iRMX systems over the
MULTI BUS II Parallel System Bus (PSB). Each iRMX
application processor running Intel's OpenNET'M
network software will provide transparent distributed
file sharing, file transfer, and virtual terminal capability
among all application processors on the backplane,
and IEEE 802.3-based (1.25 MB/sec) OpenNET
networked system nodes (See Figure 4). Using the
PSB as a network makes the System 520 a high
performance "minicomputer" cluster condensed into
one multiprocessor system.

The major advantage to the OEM is total network
extensibility inside and outside the system, using the
same OpenNET software The key benefits are:
reduced cost through the "replacement" of multiple
uni-processor networked systems and servers,
drastically reduced physical space requirements,
increased overall network throughput and
performance, and preserved software investment.
The customer can choose the combination of
packaging, CPU/system performance, and communications bandwidth suited for the application.

Easy user expansion and recomposability of the
System 520 is supported by a line of System
Integration Toolkits (SIT kits) that contain all the

firmware necessary to allow standard, off-the-shelf
MULTIBUS II boards to integrate cleanly into the
System 520. With these toolkit products, the OEM
can purchase the pieces needed and profit from
greater ease of use, ease of integration, and higher
levels of open standards.

SYSTEM :HERNET (IEEE

80::~TEM ;~~~:~t:g2'::(f.'i~l!lG~.:;~STEM 120

iRMX®1I Uniprocessor to Multiprocessor Application Migration

A Network IN The System . ..

MULTIBUS®" PSB (40 MB/sec.) Backplane "Network" Media
iRMX®/1 SYSTEM 520
Figure 4: A Network IN the System with an iSBC 386 and i486 board cluster; also shows iRMX II application
migration from networked System 120s to an iRMX II System 520 running OpenNET IN the System

7-35

OpenNETTM NETWORKING
COMPLETE OpenNErM SOLUTION FOR
REAL-TIME SYSTEMS
Many real-time applications require network
communication. Intel's iRMX-NET Release 3.0 delivers
a rich set of networking capabilities and a full range
of iRMX platform support for iRMX System 120
(AT-bus), 320 (MULTIBUS I) and 520 (MULTIBUS II)

Transparent Network File Access
iRMX-NET implements the NFA protocol to provide
transparent file access capabilities among iRMX,
DOS, VAXNMS, UNIX, XENIX and iNOX systems on
the OpenNET network. Remote files are accessed as
if they resided on the local iRMX system. iRMX-NET
can be configured as a network file consumer, file,
serv~r, or both, depending on the application's
requirements.
.
With the addition of iRMX-NET, the iRMX Human
Interface commands and system calls are
transparently extended to remote access as well.
Transparency means that applications using the iRMX
Human Interface commands or BIOS system calls do
not need to know whether the files they access reside
locally or on some remote system.

III

IBM" PC XT*

IBM" PCAT*

OSI Transport and Distributed Name Server with
Programmatic Interface
The iRMX-NET R3.0 product includes iNA 960 R3
OSI Transparent and Network software preconfigured
for a variety of Intel Network Interface Adapters.
iRMX-NET R3.0 also includes the iRMX-NET
Distributed Name Server software. The Distributed
Name Server software maintains and provides access
to a network directory database. The database is
distributed across the network with each system
m.ai~taining its own logical piece of the directory. The
Distributed Name Server software provides a full set
of network directory services and is used to perform
such tasks as logical name to network address
mapping for establishing network connections
between systems.
The combination of transparent network file access
with iRMX commands and system calls, plus direct
programmatic access to the iNA 960 Transport and
iRMX-NET Distributed Name Server software gives
the programmer a powerful set of capabilities for
developing real-time network applications.

Remote Boot for Diskless Systems
iRMX-NET R3.0 supports networked diskless systems
by providing network Boot Consumer, Boot Server
and File Server capabilities.

VAXNMS"

IIIIIID

iRMX'"System 320
MULTIBUS'"U
UNIX·

iRMX'"
System 520

Figure 5: OpenNET'Mlocal area network connections to iRMX@ systems.
7-36

iRMX® VIRTUAL TERMINAL
Virtual Terminal allows 10callRMX users to "Logon" to
a remote Intel iRMX node within an OpenNET
network or across the MULTIBUS II system bus. This
capability enables users to access all the available
resources on the remote system. In addition the IRMX
Virtual Terminal IS fully Interoperable with other
OpenNET Virtual Terminal products. Nowa PC, VAX,
or UNIX user can "connect" to a remote IRMX system
without the need to use a locally connected IRMX
terminal.

The iRMX Virtual Terminal server can be configured
to support from 1 to 32 VIrtual terminal connections
per system.
The administration utility allows the system manager
to disable, terminate or start the iRMX Virtual Terminal
server. The capability to report on the status of all the
Virtual terminal connections to the local server IS also
supported.

S 0 F TWA R E' S E R V ICE S
A FULL RANGE OF TECHNICAL SUPPORT
With the iRMX operating systems you're not alone
when you're developing a real-time application. Intel
has the best technical sales support in the real-time
business. If you need help, training, consulting, and
design adVice are readily available.

Standard Software Support
All Intel software products Include Intel's Software
Support for a 90 day period immediately following the
licensing and receipt of the product. Standard
Support Includes:
• Product updates
• Subscription Service and technical product
Information distributed via'
- Monthly issue of ;Comments newsletter
-Quarterly Troubleshooting Guides
-Software Problem Report (SPR) Service
• Technical Information Phone Service (iTIPS'M) tollfree hot line
• Membership In Insite'M User Program Library

Additional Services Available
• Consulting services on a long or short-term basIs
(Systems Engineering Support)
• Worldwide training workshops on a wide variety of
Intel products
• A full range of hardware maintenance services for
end users or OEMIVAR customers

7-37

iRMX® FAMILY PRODUCT SUMMARY
Ordering Codes

Product

iRMX® OPERATING SYSTEMS
iRMX I operating system
iRMX I operating system with AEOn: ASM 86, and PUM 86
iRMX I operating system with one-year software support
iRMX I operating system with AEOn: ASM 86, and PUM 86 and
one-year software support
iRMX I manual set
iRMX II operating system
iRMX II operating system with AEOn: ASM 86, ASM 286, PUM 286
iRMX II operating system with one-year software support
iRMX II operating system with AEOn: ASM 86, ASM 286, PL/M 286 and
one-year software support
iRMX lI'manual set
iRMX III operating system, assembler, utilities for AT bus
iRMX III operating system, assembler, utilities for AT bus and MULTIBUS
iRMX III manual set

RMXIJKIT
RMXIJKITS
SVRIJKIT
SVRIJKITS
RMXIDC
RMXIIKIT
RMXIIKITS
SVRliKIT
SVRIIKITS
RMXIIDC7
SVRIIIKIT
SVRIIIMBKIT
RMXIIIMNL

DEVELOPMENT TOOLS
iRMX864
R286EDI286
R86ASM86
R286ASM86
R286ASM286
D386ASM386
R86C86
R286C286
(Early 1990)
R86FOR86
R286FOR286
(Early 1990)
R86PLM86
R286PLM86
R286PLM286
D386PLM386
R86PAS86
R286PAS286
RMXIISFTSCP
(Early 1990)
SDMSC'
SVRIIPATKIT
RMX286TBL
RMXSCSKIT

AEOIT text editor for iRMX I operating system
AEOIT text editor for iRMX II and iRMX III operating systems
ASM/R&L 86 package for iRMX I operating system
ASM/R&L 86 package for iRMX II and iRMX III operating systems
ASM/R&L 286 package for iRMX II and iRMX III operating systems
ASM/R&L 386 package for iRMX III operating system
iC 86 package for iRMX I operating system
iC 286 package for iRMX II and iRMX III operating systems
iC 386 package for iRMX III operating system
FORTRAN 86 package for iRMX I operating system
FORTRAN 286 package for iRMX II and iRMX III operating systems
FORTRAN 386 package for iRMX II! operating systems
PUM 86 package for iRMX I operating system
PUM 86 package for iRMX II and iRMX III Qperating systems
PL/M 286 package for iRMX II and iRMX III operating systems
PUM 386 package for iRMX III operating system
Pascal 86 package for iRMX I operating system
Pascal 286 package for iRMX II and iRMX III operating systems
Soft-Scope II debugger for iRMX II
Soft-Scope III debugger for iRMX III
System Debug Monitor
System Debug Monitor and iPAT 286 performance analysis tool
iRMX Toolbox
Source Control

7-38

i R M X ® FA MIL V P R-O Due T SUM MAR V
THE iRMX® PRODUCT FAMILY

iRMX®
Operating
Systems

n
n
iRMX®1

iRMX®
Languages

n
n
IRMx"'n

iRMX®
Debuggers

iRMX®
Development
Utilities

iRMX®
Networking
Products

IRMX"'III

FORTRAN

PUM

n
n
Pascal

Assembler

n
n
n
n n n n
n
n

Soft-Scope'
High-Level
Debugger

1M III
Monitor

ISDM'"
Monitor

AEDIT
Editor

Tool Box

IRMX®-NET

Source Control
System

IPAT'" Performance
Analysis Tools

Virtual Terminal

iRMX®
Development
Platforms
-

System 120

System 320

Figure 6: iRMX® Family Product Chart

7-39

System 520

iRMX® I OPERATING SYSTEM
Real-Time Processor Management for
• Time-Critical
8086, 8088, 80186, 80188,
and 80286/386TM (Real Address Mode)
Applications
On-Target System Development with
• Universal
Development Interface (UDI)
System Size and Function
• Configurable
for Diverse Application Requirements
All iRMX® I Code Can Be (P)ROM'ed to
• Support
Totally Solid State Designs
Systems for the 8086,
• Configured
80286, and 386 Processors in the Intel

Multi-Terminal Support with Multi-User
• Human
Interface
Broad Range of Device Drivers
• Included for Industry Standard
MULTIBUS® Peripheral Controllers
Support of 8087, 80287, and 80387 .
• Processor Extension
Powerful Utilities for Interactive
• Configuration
and Real-Time
Debugging

System 300 Series Microcomputers
The iRMX I Operating System is an easy-to-use, real-time, multi-tasking and multi-programming software
system designed to manage and extend the resources of iSBC® 86, iSBC 186, iSBC 188, iSBC 286, and iSBC
386 Single Board Computers, as well as other 8086, 8088, 80186, 80188, and 80286/386TM (Real Address
Mode) based microcomputers. The Operating System provides a number of standard interfaces that allow
iRMX I applications to take advantage of industry standard device controllers, hardware components, and a
number of software packages developed by Independent Software Vendors (ISVs). Many high-performance
features extend the utility of iRMX I Systems into applications such as data collection, transaction processing,
and process control where immediate access to advances in VLSI technology is paramount. These systems
may deliver real-time performance and explicit control over resources; yet also support applications with
multiple users needing to simultaneously access terminals. The configurable layers of the System provide
services ranging from interrupt management and standard device drivers for many sophisticated controllers, to
data file maintenance commands provided by a comprehensive multi-user human interface. By providing
access to the standard Universal Development Interface (UDI) for each user terminal, Original Equipment
Manufacturers (OEMs) can pass program development and target application customization capabilities to
their use(s.

HUMAN INTERFACE

USER APPLICATIONS
210885-1

iRMX® VLSI Operating System

7-40

November 1988
Order Number: 210885-004

inter

IRMX® I OPERATING SYSTEM

The iRMX I Operating System is a complete set of
system software modules that provide the resource
management functions needed by computer systems. These management functions allow Original
Equipment Manufacturers (OEMs) to best use resources available in microcomputer systems while
getting their products to market quickly, saving time
and money. Engineers are relieved of writing complex system software and can concentrate instead
on their application software.

Process Management
To implement multi-tasking application systems, programmers require a method of managing the different processes of their application, and for allowing
the processes to communicate with each other. The
Nucleus layer of the iRMX I System provides a number of facilities to efficiently manage these processes, and to effectively communicate between them.
These facilities are provided by system calls that
manipulate data structures called tasks, jobs, regions, semaphores and mailboxes. The iRMX I System refers to these structures as 'objects".

This data sheet describes the major features of the
iRMX I Operating System. The benefits provided to
engineers who write application software and to users who want to take advantage of improving microcomputer price and performance are explained. The
first section outlines the system resource management functions of the Operating System and describes several system calls. The second section
gives a detailed overview of iRMX I features aimed
at serving both the iRMX I system designer and programmer, as well as the end users of the product
into which the Operating System is incorporated.

Tasks are the basic elements of all applications built
on the iRMX I Operating System. Each task is an
entity capable of executing CPU instructions and issuing system calls in order to perform a function.
Tasks are characterized by their register values (including those of an optional 8087, 80287, or 80387
Numeric Processor Extension), a priority between 0
and 255, and the resources associated with them.
Each iRMX I task in the system is scheduled for operation by the iRMX I Nucleus. Figure 1 shows the
five states in which each task may be placed, and
some examples of how a task may move from one
state to another. The iRMX I Nucleus ensures that
each task is placed in the correct state, defined by
the events in its external environment and by the
task issuing system calls. Each task has a priority to
indicate its relative importance and need to respond
to its environment. The Nucleus guarantees that the
highest priority ready-to-run task is the task that
runs. The nucleus can also be configured to allow
multiple tasks of the same priority to run in a roundrobin, time-slice fashion.

FUNCTIONAL DESCRIPTION
To take best advantage of 8086, 8088, 80186,
80188, and 80286/386 (Real Address Mode) microprocessors in applications where the computer is required to perform many functions simultaneously,
the iRMX I Operating System provides a multiprogramming environment in which many independent,
multi-tasking application programs may run. The
flexibility of independent environments allows application programmers to separately manage each application's resources during both the development
and test phases.

Jobs are used to define the operating environment
of a group of tasks. Jobs effectively limit the scope
of an application by collecting all of its tasks and
other objects into one group. Because the environment for execution of an application is defined by an
iRMX I job, separate applications can be efficiently
developed by separate development teams.

The resource management functions of the iRMX I
System are supported by a number of configurable
software layers. While many of the functions supplied by the innermost layer, the Nucleus, are required by all systems, all other functions are optional. The 1/0 systems, for example, may be omitted in
systems having no secondary storage requirement.
Each layer provides functions that encourage application programmers to use modular design techniques for quick development of easily maintainable
programs.

The iRMX I Operating System provides two primary
techniques for real-time event synchronization in
multi-task applications: regions and semaphores.

Regions are used to restrict access to critical sections of code and data. Once the iRMX I Operating
System gives a task access to resources guarded by
a region, no other tasks may make use of the resources, and the task is given protection against deletion and suspension. Regions are typically used to
protect data structures from being simultaneously
updated by multiple tasks.

The components of the iRMX I Operating System
provide both implicit and explicit management of
system resources. These resources include processor scheduling, up to one megabyte of system memory, up to 57 independent interrupt sources, all input
and output devices, as well as directory and data
files contained on mass storage devices and accessed by a number of independent users. Management of these system resources and methods for
sharing resources between multiple processors and
users is discussed in the following sections.

Semaphores are used to provide mutual exclusion
between tasks. They contain abstract "units" that
are sent between the tasks, and can be used to implement the cooperative sharing of resources.
7-41

iRMX® I OPERATING SYSTEM

SYSTEM ROOT JOB
JOB A

TASK Al

JOB B

TASKBl

TASK B2

MAILBOX

I TASK~
AM

MAIL·
BOXES

SEMAPHORE

I ~SKA3
QI!~ECT III RECTORY

MAILBOX AM
MAILBOX AN
TASK A3

OBJECT DIRECTORY
TASK B2

OBJECT DIRECTORY
MAILBOX RM.IQLA
SEMAPHORE RS.KlIl..I
TASK B2

001

(NON EX(STENTI

210885-2

210885-3

NOTES:
1. Task is created.
2. Task becomes highest priority ready task.
3. Task gets pre-empted by one with higher priority.
4. Task calls SLEEP or task waits at an exchange.
5. Task sleep period has ended, message was
sent to waiting task or wait has ended.
6. Task calls SUSPEND on self.
7. Task suspended by other than self.
8. Task suspended by other than self or a resume that did not bring suspension depth to
zero.
9. Task was resumed by other task.
10. Task is deleted.

Two example jobs are shown in Figure 2 to demonstrate how two tasks can share an object that was
not known to the programmer at the time the tasks
were developed. Both Job 'A' and Job 'B' exist within the environment of the 'Root Job' that forms the
foundation of all iRMX I systems. Each job posseses
a directory in which tasks may catalog the name of
an object. Semaphore 'RS', for example, is accessible by all tasks in the system, because its name is
cataloged in the directory of the Root Job. Mailbox
"AN" can be used to transfer objects between
Tasks 'A2' and 'A3' because its token is accessible
in the object directory for Job 'A'.

Figure 1. Task State Diagram

Table 1 lists the major functions of the iRMX I Nucleus that manages system processes.

Multi-tasking applications must communicate information and share system resources among cooperating tasks. The iRMX I Operating System assigns a
unique 16-bit number, called a token, to each object
created in the System. Any task in possession of this
token is able to access the object. The iRMX I Nucleus allows tasks to gain access to objects, and
hence system resources, at run-time with two additional mechanisms: mailboxes and object directories.

Memory Management
Each job in an iRMX I System defines the amount of
the one megabyte of addressable memory to be
used by its tasks. The iRMX I Operating System
manages system memory and allows jobs to share
this critical resource by providing another object
type: segments.
Segments are contiguous pieces of memory between 16 Bytes and 64 Kbytes in length, that exist
within the environment of the job in which they were
created. Segments form the fundamental piece of
system memory used for task stacks, data storage,
system buffers, loading programs from secondary
storage, passing information between tasks, etc.

Mailboxes are used by tasks wishing to share objects with other tasks. A task may share an object by
sending the object token via a mailbox. The receiving task can check to see if a token is there, or can
wait at the mailbox until a token is present.
Object Directories are also used to make an object
available to other tasks. An object is made public by
cataloging its token and name in a directory. In this
manner, any task can gain access to the object by
knowing its name, and job environment that contains
the directory.

The example in Figure 2 also demonstrates when
information is shared between Tasks 'A2' and 'A3';
'A2' only needs to create a segment, put the information in the memory allocated, and send it via the
Mailbox 'AM' using the RQ$SEND$MESSAGE sys-

7-42

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iRMX® I OPERATING SYSTEM
Table 1. Process Management System Calls

System Call
RQ$CREATE$JOB
RQ$DELETE$JOB
RQ$OFFSPRING
RQ$CATALOG$OBJECT
RQ$UNCATALOG$OBJECT
RQ$LOOKUP$OBJECT
RQ$GET$TYPE
RQ$CREATE$MAILBOX
RQ$DELETE$MAILBOX
RQ$SEND$MESSAGE

RQ$RECEIVE$MESSAGE

RQ$DISABLE$DELETION
RQ$ENABLE$DELETION
RQ$FORCE$DELETE
RQ$CREATE$TASK
RQ$DELETE$TASK
RQ$SUSPENDS$TASK
RQ$RESUME$TASK
RQ$SLEEP
RQ$GET$TASK$TOKENS
RQ$SET$PRIORITY
RQ$GET$PRIORITY
RQ$CREATE$REGION
RQ$DELETE$REGION
RQ$ACCEPT$CONTROL
RQ$RECEIVE$CONTROL
RQ$SEND$CONTROL
RQ$CREATE$SEMAPHORE
RQ$DELETE$SEMAPHORE
RQ$SEND$UNITS
RQ$RECEIVE$UNITS

Function Performed
Creates an environment for a number of tasks and other objects, as well as
creating an initial task and its stack.
Deletes a job and all the objects currently defined within its bounds. All
memory used is returned to the job from which the deleted job was created.
Provides a list of all the current jobs created by the specified job.
Enters a name and token for an object into the object directory of a job.
Removes an object's token and its name from a job's object directory.
Returns a token for the object with the specified name found in the object
directory of the specified job.
Returns a code for the type of object referred to by the specified token.
Creates a mailbox with queues for waiting tasks and objects with FIFO or
PRIORITY discipline.
Deletes a mailbox.
Sends an object to a specified mailbox. If a task is waiting, the object is
passed to the appropriate task according to the queuing discipline. If no task
is waiting, the object is queued at the mailbox.
Attempts to receive an object token from a specified mailbox. The calling
task may choose to wait for a specified number of system time units if no
token is available.
Prevents the deletion of a specified object by increasing its disable count by
one.
Reduces the disable count of an object by one, and if zero, enables deletion
of that object.
Forces the deletion of a specified object if the disable count is either 0 or 1.
Creates a task with the specified priority and stack area.
Deletes a task from the system, and removes it from any queues in which it
may be waiting.
Suspends the operation of a task. If the task is already suspended, its
suspension depth is increased by one.
Resumes a task. If the task had been suspended multiple times, the
suspension depth is reduced by one, and it remains suspended.
Causes a task to enter the ASLEEP state for a specified number of system
time units.
Gets the token for the calling task or associated objects within its
environment.
Dynamically alters the priority of the specified task.
Obtains the current priority of a specified task.
Creates a region, with an associated queue of FIFO or PRIORITY ordering
discipline.
Deletes the specified region if it is not currently in use.
Gains control of a region only if the region is immediately available.
Gains control of a region. The calling task may specify the number of system
time units it wishes to wait if the region is not immediately available.
Relinquishes control of a region.
Creates a semaphore.
Deletes a semaphore.
Increases a semaphore counter by the specified number of units.
Attempts to gain a specified number of units from a semaphore. If the units
are not immediately available, the calling task may choose to wait.

7·43

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iRMX® I OPERATING SYSTEM

tem call (see Table 1). Task 'A3' would get the message by using the RQ$RECEIVE$MESSAGE system
call. The Figure also shows how the receiving task
could signal the sending task by sending an acknowledgement via the second Mailbox 'AN'.

time response to events. Use of a pre-emptive
scheduling technique ensures that the servicing of
high priority events always takes precedence over
other system activites.
The iRMX I Operating system gives applications the
flexibility to optimize either interrupt response time
or interrupt response capability by providing two tiers
of Interrupt Management. These two distinct tiers
are managed by Interrupt Handlers and Interrupt
Tasks.
.

Each job is created with both maximum and minimum limits set for its memory pool. Memory required
by all objects and resources created in the job is
taken from this pool. If more memory is required, a
job may be allowed to borrow memory from the pool
of its containing job (the job from which it was created). In this manner, initial jobs may efficiently allocate memory to jobs they subsequently create, without knowing their exact requirements.

Interrupt Handlers are the first tier of interrupt service. For small simple functions, interrupt handlers
are often the most efficient means of responding to
an event. They provide faster response than interrupt tasks, but must be kept simple since interrupts
(except the 8086, 8088, 80186, 80188, 80286, and
386TM processors non-maskable interrupts) are
masked during their execution. When extended
service is required, interrupt handlers "signal" a
waiting interrupt task that, in turn, performs more
complicated functions.

The iRMX I Operating System supplies other memory management functions to search specific address
ranges for available memory. The System performs
this search at system initialization, and can be configured to ignore non-existent memory and addresses reserved for 1/0 devices and other application
requirements.
.

Interrupt Tasks are distinct tasks whose priority is
associated with a hardware interrupt level. They are
permitted to make an iRMX I system call. While an
interrupt task is servicing an interrupt, interrupts of
lower priority are not allowed to pre-empt the system.

Table 2 lists the major system calls used to manage
the system memory.

Interrupt Management
Real-time systems, by their nature, must respond to
asynchronous and unpredictable events quickly. The
iRMX I Operating System uses interrupts and the
event-driven Nucleus described earlier to give real-

Table 3 ~hows the iRMX I System Calls provided to
manage Interrupts.

Table 2. Memory Management System Calls
System Call
RO$CREATE$SEGMENT
RO$DELETE$SEGMENT
RO$GET$POOL$ATTRIBUTES
RO$GET$SIZE
RO$SET$POOL$MIN

Function Performed
Dynamically allocates a memory segment of the specified size.
Deletes the specified segment by deallocating the memory.
Returns attributes such as the minimum and maximum, as well as current
size of the memory in the environment of the calling task's job.
Returns the size (in bytes) of a segment.
Dynamically changes the minimum memory requirements of the job
environment containing the calling task.

Table. 3. Interrupt Management System Calls
System Call
RO$SET$INTERRUPT
RO$RESET$INTERRUPT
RO$GET$LEVEL
RO$SIGNAL$INTERRUPT
RO$WAIT$INTERRUPT
RO$EXIT$INTERRUPT
RO$ENABLE
RO$DISABLE

Function Performed
Assigns an interrupt handler and, if desired, an interrupt task to the specified
interrupt level. Usually the calling task becomes the interrupt task.
Disables an interrupt level, and cancels the assignment of the interrupt
handler for that level. If an interrupt task was assigned, it is deleted.
Returns the number of the highest priority interrupt level currently being
processed.
Used by an interrupt handler to signal the associated interrupt task that an
interrupt has occurred.
Used by an interrupt task to SLEEP until the associated interrupt handler
signals the occurrence of an interrupt.
Used by an interrupt handler to relinquish control of the System.
Enables the hardware to accept interrupts from a specified level.
Disables the hardware from accepting interrupts at or below a specified
level.

7-44

inter

iRMX® I OPERATING SYSTEM

tions. The BIOS allows 110 functions to overlap other system functions. In this manner, application
tasks make asynchronous calls to the iRMX I BIOS,
and proceed to perform other activities. When the
110 request must be completed before an application can continue, the task waits at a mailbox for the
result of the operation. Some system calls provided
by the BIOS are listed in Table 4.

INTERRUPT MANAGEMENT EXAMPLE
Figure 3 illustrates how the iRMX I Interrupt System
may be used to output strings of characters to a
printer. In the example, a mailbox named 'PRINT' is
used by all tasks in the system to queue messages
to be printed. Application tasks put the characters in
segments that are transmitted to the printer interrupt
task via the PRINT Mailbox. Once printing is complete, the same interrupt task passes the messages
on to another application via the FINISHED Mailbox
so that an operator message can be displayed.

The Basic 110 System communicates with peripheral devices through device drivers. These device drivers provide the System with four basic functions
needed to control and communicate with devices:
Initialize 110, Finish 110, Queue 110, and Cancel 110.
Using the device driver interface, users of non-standard devices may write custom drivers compatible
with the 110 System.
The iRMX I Operating System includes a number of
device drivers to allow applications to use standard
USART serial communications devices, multiple
CRTs and keyboards, bubble memories, diskettes,
disks, a Centronics-type parallel printer, and many of
Intel's iSBC and iSBXTM device controllers (see Table 8). If an application requires use of a non-standard device, users need only write a device driver to
be included with the BIOS, and access it as if it were
part of the standard system. For most common random-access devices, this job is further simplified by
using standard routines provided with the System.
Use of this technique ensures that applications can
remain device independent.

210885-4

Figure 3. Interrupt Management Example

Basic 110 System
The Basic 110 System (BIOS) provides the direct access to 110 devices needed by real-time applica-

Table 4. Key BIOS I/O Management System Calls
System Calls

Function Performed

RQ$A$ATTACH$FILE

Creates a Connection to an existing file.

RQ$A$CHANGE$ACCESS

Changes the types of accesses permitted to the specified user(s) for
a specific file.

RQ$A$CLOSE

Closes the Connection to the specified file so that it may be used
again, or so that the type of access may be changed.

RQ$A$CREATE$DIRECTORY

Creates a Named File used to store the names and locations of other
Named Files.

RQ$A$CREATE$FILE

Creates a data file with the specified access rights.

RQ$A$DELETE$CONNECTION

Deletes the Connection to the specified file.

RQ$A$GET$FILE$STATUS

Returns the current status of a specified file.

RQ$A$OPEN

Opens a file for either read, write, or update access.

RQ$A$READ

Reads a number of bytes from the current position in a specified file.

RQ$A$SEEK

Moves the current data pointer of a Named or Physical file.

RQ$A$WRITE

Writes a number of bytes at the current position in a file.

RQ$WAIT$IO

Synchronizes a task with the 110 System by causing it to wait for 110
operation results.

7-45

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IRMX® I OPERATING SYSTEM

Multi-Terminal Support

Logical file and device names are provided by the
EIOS to give applications complete file and device
independence. Applications may send data to the
'line printer' (:LP:) without needing to know which
specific device will be used as the printer. This logical name may, in fact, not be a printer at all, but it
could be a disk file that is later scheduled for printing.

The iRMX I Terminal Support provides line editing
and terminal control capabilities. The Terminal Support communicates with devices through simple drivers that do only character 1/0 functions. Dynamic
terminal reconfiguration is provided so that attributes
such as terminal type and line speed may be
changed without modifying the application or the
Operating System. Dynamic configuration may be
typed in, generated programmatically or stored in a
file and copied to a terminal 1/0 connection. ,

The EIOS uses the functions provided by the BIOS
to synchronize individual 1/0 requests with results
returned by device drivers. Most EIOS system calls
are similar to the BIOS calls, except that they appear
to suspend the operation of the calling task until the
1/0 requests are completed.

The iRMX I Terminal Support provides automatic
translation of control ch~racters to specific control
sequences for each terminal. This translation enables applications using standard control characters
to function with non-standard terminals: The translation requirements for each terminal can be stored in
terminal description files and copied to a connection, as described above.

File Management
The iRMX I Operating System provides three distinct
types of files to ensure efficient management of both
program and data files: Named Files, Physical Files,
and Stream Files. Each file type provides access to
1/0 devices through the standard device drivers
mentioned earlier. The same device driver is used to
access physical and named files for a given device.

Peripheral Device Drivers
Each device driver can be used to interface to a
number of separate and, in some cases, different
devices. The iSBC 215G Device Driver, supplied
with the system, is capable of supporting the iSBC
215G Winchester Disk Controller, the iSBC 220
SMD Disk Controller, and the iSBX 218A Flexible
Disk Controller (when mounted on an iSBC 215G
board). Each device controller may, in turn, control a
number of separate device units. In addition, each
driver may control a number of like device controllers. This capability allows the use of large storage
systems with a minimum of 1/0 system code to write
or maintain.

NAMED FILES
Named files allow users to access information on
secondary storage by referring to a file with its ASCII
name. The names of files stored on a device are
stored in special files called directories in a hierarchical file structure.

Extended 1/0 System
The iRMX I Extended 1/0 System (EIOS) adds a
number of 1/0 management capabilities to simplify
access to files. Whereas the BIOS provides users
with the basic system calls needed for direct management of 1/0 resources, many users prefer to
have the system perform all the buffering and synchronization of 1/0 requests automatically. The
EIOS allows users to access 1/0 devices without
having to write procedures for buffering data, or to
specify particular devices with constant device'
names.
By performing device buffering automatically, the
iRMX I EIOS optimizes accesses to disks and other
devices. Often, when an application task asks the
System to READ a portion of a file, the System is
able to respond immediately with the data it has
read in advance of the request. Similarly, the EIOS
will not delay a task for writing data to a device unless it is specifically told to, or if its output buffers are
filled.

The iRMX I BIOS uses an efficient format for writing
the directory and data information into secondary
storage. This structure enables the system to directly access any byte in a file, often without having to
do additional 1/0 to access space allocation information. The maximum size of an individual file is 4.3
billion bytes.

EASE OF ACCESS
The hierarchical file structure is provided to isolate
and organize collections of named files. To give operators fast and simple access to any level within
the file tree, an ATTACHFILE command is provided.
This' command allows operators to create a logical
name to a pOint in the tree so that a long sequence
of characters need not be typed each time a file is
.
referred to.

ACCESS PROTECTION
Access to each Named File is protected by the
rights assigned to each user by the owner of the file.
Rights to read, append, update, and delete may be
7-46

inter '

iRMX® I OPERATING SYSTEM

selectively granted to other users of the system. In
general, users of Named Files are classified into one
of two categories: User and World. Users are used
when different programmers and programs need to
share information stored in a file. The World classification is used when rights are to be granted to all
who can use the system.

Human Interface
The flexibility of the interface between computer
controlled machines and their users often determines the usability and ultimate success of the machines. Table 11 lists iRMX I Human Interface functions giving users and applications simple access to
the file and system management capabilities described earlier. The process, interrupt, and memory
management functions described earlier, are performed automatically for Human Interface users.

PHYSICAL FILES

Physical Files allow more direct device access than
Named Files. Each Physical File occupies an entire
device, treated as a single stream of individually accessible bytes. No access control is provided for
Physical Files as they are typically used for such applications as driving a printing device, translating
from one device format to another, driving a paper
tape device, real-time data acquisition, and controlling analog mechanisms.

MULTI·USER ACCESS

USing the multi-terminal support provided by the
BIOS, the iRMX I Human Interface can support several simultaneous users. The real-time nature of the
system is maintained by providing a priority for each
user, and using the event-driven iRMX I Nucleus to
schedule tasks. High-performance interrupt response is guaranteed even while users interact with
various application packages. For example, mUltiterminal support allows one person to be using the
iRMX I Editor, while another compiles a FORTRAN
86 or PASCAL 86 program, while several others load
and access applications.

STREAM FILES

Stream Files provide applications with a method of
using iRMX I file management methods for data that
does not need to go into secondary storage. Stream
Files act as direct channels, through system memory, from one task to another. These channels are
very useful to programs, for example, wishing to preserve file and device independence allowing data
sent to a printer one time, to a disk file another time,
and to another program on a different occasion.

Each terminal attached to the iRMX I multi-user Human Interface is automatically associated with a
user, a memory pool, and an initial program to run
when the terminal is connected. This association is
made using a file that may be changed at any time.
Changes are effective the next time the system is
initialized.

BOOTSTRAP AND APPLICATION LOADERS

Two utilities are supplied with the System to load
programs and data into system memory from secondary storage devices:

The initial program specified for each terminal can
be a special application program, a custom Human
Interface, or the standard iRMX I Command Line Interpreter (CLI).

The iRMX I Bootstrap is typically used to load the
initial system from the system disk into memory, and
begin its execution. Error reporting and debug switch
features have been added to the Bootstrap Loader.
When the Bootstrap Loader detects errors such as:
"File Does Not Exist" or "Device Not Ready", an
error message is reported back to the user. The debug switch will cause the Bootstrap Loader to load
the system but not begin its execution. Instead the
Bootstrap Loader will pass control to the monitor at
the first instruction to be executed by the system.

Specifying an application program as a terminal's initial program makes the interface between operators
and the computer system much simpler. Each operator need only be aware of the function of a particular application.
Specifying the standard iRMX I Human Interface CLI
as the initial program enables users of the terminals
to access all iRMX I functions. This CLI makes it
easy to manage iRMX I files, load and execute Intelsupplied and custom programs, and submit command files for execution.

The Application Loader is typically used by application programs already running in the system to load
additional programs and data from any secondary
storage device. The Human Interface layer, for example, uses the Application Loader to load the nonresident Human Interface Commands. The Application Loader is capable of loading both relocatable
and absolute code as well as program overlays.

7-47

inter

IRMX@ I OPERATING SYSTEM

Building Security
System
SYSTEM BUFFERS
AND DATA

APPLICATION CODE

OPERATOR
CONSOLE
APPLICAnONS

RAM

COMMON
UTILITIES

BACKGROUND
APPLICATION

HUMAN INTERFACE

BIOS

EIOS
WINCHESTER
DISK
DRIVER

FLOPPY
DISK
DRIVER

NUCLEUS
:PROM

BOOTSTRAP LOADER

210885-8

Data Communication
Controller·
SYSTEM
BUFFERS
DATA

RAM

PROM

16K BYTES
APPLICATION CODE
23K BYTES NUCLEUS CODE

210885-9

Figure 4. Typical iRMX® I Configurations
Many real-time systems require high performance
operation. To meet this requirement, all of iRMX I
can be put into high-speed P(ROM). This approach
eliminates the possibility of disk access times slowing down performance, while allowing system designers to take advantage of high performance
memory devices.

FEATURE OVERVIEW
The iRMX I Operating System is well suited to serve
the demanding needs of real-time applications executing on complex microprocessor systems. The
iRMX I System also provides many tools and featues
needed by real-time system developers and programmers. The following sections describe features
useful in both the development and execution environments. The description of each feature outlines
the advantages given to hardware and software engineers concerned with overall system cost, expandability with custom and industry standard options,
and long-term maintenance of iRMX I-based systems. The development environment features also
describe the ease with which the iRMX I Operating
System can be incorporated into overall system designs.

CONFIGURABILITY
The iRMX I Operating system is configurable by system layer, and by system call wi~hin each layer. In
addition all the 1/0 port addresses used by the System are configurable by the user. This flexibility gives
designers the freedom to choose configurations of
hardware and software that best suit their size and
functional requirements. Two example configurations are shown in Figure 4.
Most configuration options are selected during system design stages. Others may be selected during
system operation. For example, the amount of memory devoted to queues within a Mailbox can be specified at the time the Mailbox is created. Devoting
more memory to the Mailbox allows more messages
to be transmitted to other tasks without having to
degrade system performance to allocate additional
memory dynamically.

Execution Environment Features
REAL-TIME PERFORMANCE
The iRMX I Operating System is designed to offer
the high performance, multi-tasking functions required by real-time systems. Designers can make
use of VLSI devices such as the 8087, 80287 or
80387 Numeric Processor Extension.
7-48

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iRMX® I OPERATING SYSTEM

The chart shown in Table 6 indicates the actual
memory size required to support these different configurations of the iRMX I System. Systems requiring
only Nucleus level functions may require no more
than 1S Kbytes for the Operating System. Other applications, needing I/O managment functions, may
select portions of additional layers that fit their
needs and size constraints.

ment used to monitor job costs while developing
new device control specifications instructions. The
iSBC 544A Intelligent Terminal Interface supports
multiple user terminals without degrading system
performance to handle character I/O.
EXTENDABILITY
The iRMX I Operating System provides three means
of extensions. This extendability is essential for
support of OEM and volume end user value added
features. This ability is provided by user-defined op-

This configurability also applies to the Terminal Handier, Dynamic Debugger, and System Debugger.
The Terminal Handler provides a serial terminal interface in a system that otherwise doesn't need an
I/O system. Either one of the de buggers need to be
included only as debugging tools (usually only during
system development).
MULTI-USER ACCESS
Many real-time systems must provide a variety of
users access to system control functions and collected data. The iRMX I System provides easy-touse support for applications to access multiple terminals. It also enables multiple and different users to
access different applications concurrently.
Figure 5 illustrates a typical iRMX I application simultaneously supporting multi-terminal data collection
and real-time environments. Shown is a group of terminals used by machinists on a shop floor to communicate with a job management program, a building security system that constantly monitors energy
usage requirements, a system operator console capable of accessing all system functions, and a group
of terminals in the Production Engineering depart-

210885-10

Figure 5. Multi-Terminal and Multi-User
Real-Time System

Table 6. iRMXTM 86 Configuration Size Chart
System Layer
Bootstrap Loader
Nucleus
BIOS
Application Loader

Min. ROMabie
Size

Max.
Size

Data
Size

1.5K

6K·

10.5K

24K

26K

78K

1K
2K

10K

10.5K

12.5K

22K

15K

UDI

Terminal Handler

O.SK
1K

EIOS
Human Interface

System Debugger

20K

Dynamic Debugger

28.5K

Human Interface Commands

116K

Interactive Configuration Utility

S08K

'Usable by System after bootloadlng.

7-49

inter

iRMX® I OPERATING SYSTEM

Table 7. User Extension System Calls
Function Performed

System Call
RQ$CREATE$COMPOSITE

Creates a custom object built of previously defined objects.

RQ$DELETE$COMPOSITE

Deletes the custom object, but not the various objects from which it
was built.

RQ$INSPECT$COMPOSITE

Returns a list of Token Identifiers for the component objects from
which the specified composite object is built.

RQ$ALTER$COMPOSITE

Replaces a component object of a composite object.

RQ$CREATE$EXTENSION

Creates a new type of object and assigns a mailbox used for
collecting these objects when they are deleted.

RQ$DELETE$EXTENSION

Deletes an extension definition.

erating system calls, user-defined objects (similar to
Jobs, Tasks, etc.), and the ability to add functions
later in, the product life cycle. The modular, layered
structure of the System easily facilitates later additions to iRMX I applications. User-defined objects
are supported by the functions listed in Table 7.
USing standard iRMX I system calls, users may define custom objects, enabling applications to easily
manipulate commonly used structures as if they
were part of the original operating system.
EXCEPTION HANDLING

SUPPORT OF STANDARDS

The iRMX I Operating System supports the many
hardware and software standards needed by most
application systems to ensure that commonly available hardware and software packages may be interfaced with a minimum of cost and effort. The iRMX I
System supports the iSBC family of products built on
the Intel MULTIBUS I (IEEE Standard 796), and a
number of standard software interfaces such as the
UDI and the common device driver interface (See
Figure 6). The procedural interfaces of the UOI are
listed in Table 9.
The Operating System includes support for the 8087
Numeric Data Processor and equivalent instructions
and registers in the 80287 and 80387 Numeric Data

The System includes predefined exception handlers
for typical 1/0 and parameter error conditions. The
errors handling mechanism is both configurable and
extendable.

APPLICATIONS
SUPPORT

210885-11

Figure 6. IRMX@ I Standard Interfaces

7-50

inter

iRMX® I OPERATING SYSTEM

Processors. Standards such as an Ethernet communication interface are supported by optional software
packages available to run on the iRMX I System.

controllers. The particular boards and types of devices supported are listed in Table 8. The device controllers all adhere to industry standard electrical and
functional interfaces.

SPECTRUM OF CPU PERFORMANCE

In addition to the on-CPU board terminal drivers, the
iRMX I BIOS includes two iSBC board-level device
drivers to support multiple terminal interfaces:

The iRMX I Operating System supports a broad
range of Intel processors. In addition to support for
8086, 8088, 80186 and 80188-based systems, the
iRMX I system has been enhanced to support
80286/386, (16-bit, Real Address Mode)-based Systems. This new support enables the user to take advantage of the faster speed and higher performance
of Intel's 80286 and 386 based microprocessors
such as the iSBC 286/12 and iSBC 386/21 single
board computers. By choosing the appropriate CPU,
designers can choose from a wide range of performance options, without having to change application
software.

The iSBC 544A Intelligent Four-Channel Terminal Interface Device Driver provides support for multiple
controllers each supporting up to four standard
RS232 terminals. The iSBC 544A driver takes advantage of an on-board processor to greatly reduce
the system processor time required for terminal I/O
by locally managing input and output buffers. The
iSBC 544A firmware provided with the operating system can offload the system CPU by as much as 75%
when doing character outputting.
The iSBC 534 Four-Channel USART Controller Device Driver also provides support for multiple controller boards each supporting up to four standard
RS232 terminals.
.

COMPONENT LEVEL SUPPORT
The iRMX I System may be tailored to support specific hardware configurations. In addition to system
memory, only an 8086, 8088, 80186, 80188, 80286,
or 386 microprocessor, an 8259A Programmable Interrupt Controller (PIC), and either an 8253, 8254, or
82530 Programmable Interval Timer (Pin are required as follows:

The RAM disk feature in iRMX I makes a portion of
the memory address space look like a disk drive to
the I/O system.
Table 8. Supported Devices

• 8086 and 8088 systems need either:
- 8253/4 PIT and 8259A PIC (master) or
- 80130 firmware (PIC is master)

Module/Device
iSBC® 86/C38, 86/05A,
86/12A, 86/30, 86/35,
186/03A, 186/51, 188/56,
286/10A,286/12,386/21,
386/31
Peripheral Controller iSBC 186/03A SCSI, 208,
214, 215G, 220, 221,
iSBXTM 217C, 218A
Function
Single Board
Computer (Note 1)

• 80186 and 80188 systems where 186 PIC is
slave, needs either:
- 8253/4 PIT and 8259A PIC (master) or
- 80130 firmware (PIC is master)
where 186 PIC is master:
-

Use 186 PIT for the system clock; no external
PIT is needed
Can use either
186 PIC (master) only or
8259A180130 PIC (slave)

Terminal Controller/
HostComm.
Network Controller
Graphics
Microprocessor
(Note 1)
Math Coprocessor
(Note 1)

• 80286 systems need
- 8253/4 PIT and 8259A PIC
For systems requiring extended mathematics capability, an 8087,80287, or 80387 Numeric Data Processor may be added to perform these functions up
to 100 times faster than equivalent software. For applications servicing more than 8 interrupt sources,
additional 8259A's may be configured as slave controllers.

Serial Port
Interrupt Controller
Timer
Parallel Port/
Line Printer
RAM Disk

BOARD LEVEL SUPPORT

iSBC 188/56,534, 544A,
548, iSBX 351,354
iSBC 552A, 186/51
iSBX279
8086,8088,80186,80188,
80286,386
8087,80287,80387
8251A,8274,82530
8259A,80130,80186
8253,8254,80186
8255, iSBX 350
SRAM,DRAM

NOTE:
1. Supports 16-bit, real address mode, 8086/8087 instruction set, functions and registers.

The iRMX I Operating System includes device drivers to support a broad range of MULTIBUS I device
7-51

IRMX® I OPERATING SYSTEM

Development Environment Features

LANGUAGES

The iRMX I Operating System supports the efficient
utilization of programming time by providing important tools for program development. Some of the
tools necessary to develop and debug real-time systems are included with the Operating System. Others, such as language compilers, are available from
Intel and from leading Independent Software Vendors.

The iRMX I Operating System supports 31 standard
system calls known as the Universal Oevelopment
Interface (UOI). Figure 6 shows the iRMX I standard
interfaces to many compilers and language translators, including Intel's 8086 Macro Assembler and the
Pascal 86, PL/M 86, FORTRAN 86 and C86 compilers.

System Call

Table 9. UOI System Calls
Function Performed

MEMORY MANAGEMENT
OQ$ALLOCATE
OQ$FREE
OQ$GET$SIZE*
OQ$RESERVE$IO$MEMORY'

Creates a Segment of a specified size.
Returns the specified segment to the System.
Returns the size of the specified Segment.
Reserves memory to OPEN and AITACH files.

FILE MANAGEMENT
OQ$AITACH
,
OQ$CHANGE$ACCESS'
OQ$CHANGE$EXTENSION
OQ$CLOSE
OQ$CREATE
OQ$OELETE
OQ$OETACH
OQ$OPEN
OQ$GET$CONNECTION$STATUS'
OQ$FILES$INFO'
OQ$REAO
OQ$RENAME'
OQ$SEEK
OQ$TRUNCATE
OQ$WRITE

Creates a Connection to a specified file.
Changes the user access rights associated with a file or directory.
Changes the extension of a file name in memory.
Closes the specified file Connection.
Creates a Named File.
Oeletes a Named File.
Closes a Named File and deletes its Connection.
Opens a file for a j:larticular_type of access.
Returns the current status of the specified file Connection.
Returns data about a file Connection.
Reads the next seQuence of bytes from a file.
Renames the specified Name File.
Moves the position pointer of a file.
Truncates a file.
Writes a sequence of bytes to a file.

PROCESS MANAGEMENT
OQ$EXIT
OQ$OVERLAy*
OQ$SPECIAL
OQ$TRAP$CC

Exits from the current EiPplication job.
Causes the specified overlay to be loaded.
Performs special 110 related functions on terminals with special
control features.
Capture control when CNTRL/C is type.

EXCEPTION HANDLING
OQ$GET$EXCEPTION$HANOLER
OQ$OECOOE$EXCEPTION
OQ$TRAP$EXCEPTION

Returns a pointer to the program currently being used to process
errors.
Returns a short description of the specified error code.
Identifies a custom exception processing program for a particular
type of error.

APPLICATION ASSISTANCE
OQ$OECOOE$TIME
OQ$GET$ARGUMENT*
OQ$GET$SYSTEM$IO*
OQ$GET$TIME'
OQ$SWITCH$BUFFER

Returns system time and date in binary and ASCII character format.
Returns the next argument from the character string used to invoke
the apj:llication proJjram.
Returns the name of the underlying operating system supporting the
UOI.
Returns the current time of day as kept by the underlying operating
system.
Selects a new buffer from which to process commands.

'Calls available only through the UDI.

7-52

inter

iRMX® I OPERATING SYSTEM

Also included are other Intel development tools, language translators and utilities available from other
vendors. The full set of UDI calls (which includes the
URI system calls) is required to run a compiler.

INTERACTIVE CONFIGURATION UTILITY
The iRMX I Operating System is designed to provide
OEMs the ability to configure for specific system
hardware and software requirements. The Interactive Configuration Utility (ICU) builds iRMX I configurations by asking appropriate questions and making
reasonable assumptions. It runs on either an Intellec® Series IV development system or iRMX I development system that includes a hard disk and the
UDI. Table 11 lists the hardware and support software requirements of different iRMX I development
system environments.

These standard software interfaces (the UDI) ensure
that users of the iRMX I Operating System may
transport their applications to future releases of the
iRMX I Operating System and other Intel and independent vendor software products. The calls avail
able in the UDI are shown in Table 9.
The high performance of the iRMX I Operating System enhances the throughput of compilers and other
development utilities.

Table 11. iRMX® Development Environment
Intellec Series IV:
ASM 86 Assembler and Utilities
PLIM 86 Compiler
One hard disk and one diskette drive
iRMX I Development System:
ASM 86 Assembler and Utilities
PL/M 86 Compiler
. iSDM System Debug Monitor
640K Bytes of RAM
5M Byte On-Line Storage and one
double-density diskette drive
SYSTEM 86/300, 286/300, or 386/300 Series:
Microcomputer System Basic configuration

TOOLS
Certain tools are necessary for the development of
microcomputer applications. The iRMX I Human Interface includes many of these tools an non-resident
commands. They can be included on the system
disk of a application system, and brought into memory when needed to perform functions as listed in
Table 10.
Table 10. Major Human Interface Utilities
Command
BACKUP
COpy
CREATEDIR
DIR

ATIACHFILE

PERMIT
RENAME
SUBMIT
SUPER

TIME
VERIFY

Function
Copy directories and files from
one device to another.
Copy one or more files to one
or more destination files.
Create a directory file to store
the names of other files.
List the names, sizes, owners,
etc. of the files contained in a
directory.
Give a logical name to a
specified location in a file
directory tree.
Grant or rescind user access
to a file.
Change the name of a file.
Start the processing of a series
of commands stored in a file.
Change operator's ID to that of
the System Manager with
global access rights and
privileges.
Set the system time-of-day
clock.
Verify the structure of an
iRMX I Named File volume,
and check for possible disk
data errors.

Figure 7 shows one of the many screen displayed
during the process of defining a configuration. It
shows the abbreviations for each choice on the left,
a more complete description with the range of possible answers in the center, and the current (sometimes default) choice on the right. The bottom of the
screen shows three changes made by the operator
(lower case lettering), and a request for help on the
Exception Mode question. In response to a request
for help, the ICU displays an additional screen outlining possible choices and some overall system effects.
The ICU requests only information required as a result of previous choices. For example, if no Extended liD System functions are required, the ICU will
not ask any further questions about the EIOS. Once
a configuration session is complete, the operator
may save all the information in a file. Later when
small changes are necessary, this file can be modified. A completely new session is not required.

7-53

inter

IRMX® I OPERATING SYSTEM

REAL-TIME DEBUGGING TOOLS

PARAMETER VALIDATION

The iRMX I Operating System supports two distinct
debugging environments: Static and Dynamic. While
the iRMX I Operating System does support a multiuser Human Interface, these real-time debugging
aids are usually most useful in a single-user environment where modifications made to the system cannot affect other users.

Some iRMX I System Calls require parameters that
may change during the course of developing iRMX I
applications. The iRMX I Operating System includes
an optional set of routines to validate these parameters to ensure that correct numeric values are used
and that correct object types are used where the
System expects to manipulate an object. For systems based only on the iRMX I Nucleus, these routines may be removed to improve the performance
and code size of the System once the development
phase is completed.

System Debugger
The static debugging aid is the iRMX I System Debugger. This debugger is an extension of the iSDM
System Debug Monitor. The System Debugger provides static debugging facilities when the system
hangs or crashes, when the Nucleus is inadvertently
overwritten or destroyed, or when synchronization
requirements prevent the debugging of certain
tasks. The System Debugger stops the system and
allows you to examine the state of the system at that
instant, and allows you to:
- Identify and interpret iRMX I system calls.
-

Display information about iRMX I objects.

Examine a task's stack to determine system call
history.
'

START-UP SYSTEMS
Three ready-to-run start-up systems are included in
the iRMX I Operating System package for 8086,
80286, and 386-based MULTIBUS I systems. These
iRMX I start-up systems are fully configured, iRMX I
Operating Systems ready to be loaded into memory
by the Bootstrap Loader. The start-up systems are
configured to include all of the system calls for each
layer and most of the features provided by iRMX I
software. iRMX I start-up systems include UDI support so that users may run languages such as
PL/M-86, Pascal, FORTRAN, and software packages from independent vendors.
The start-up system for the 8086 processor is configured for Intel SYSTEM 86/300 Series microcomputers with a minimum of 384K bytes of RAM. The
following devices are supported.

iRMX® I Dynamic Debugger
The iRMX I Dynamic Debugger runs as part of an
iRMX I application. It may be used at any time during
program development, or may be integrated into an
OEM system to aid in the discovery of latent errors.
The Dynamic Debugger can be used to search for
errors in any task, even while the other tasks in the
system are running. The iRMX I Dynamic Debugger
communicates with the developer via a terminal handier that supports full line editing._
Nucleus
(ASC)
(PV)(ROD)
(MTS)
(DEH)
(NEH)
(EM)
(NR)

• iSBC 215G/iSBX 218 or iSBC 215G/iSBX 218A
or iSBC 214
• Line Printer
• 8251A Terminal Driver
• iSBC 544A, Terminal Driver

All Sys Calls [Yes/No]
Parameter Validation [Yes/No]
Root Object Directory Size [O-OFFOh]
Minimum Transfer Size [O-OFFFFH]
Default Exception Handler [Yes/No/Deb/Use]
Name of Ex Handler Object Mqdule [1-32 chs]
Exception Mode [Never/Program/Environ/AII]
Nucleus in ROM [YeslNo]

Enter Changes [Abbreviations?/
:pv = no
:rod = 48
:em?

= new-value]:

ASC

Figure 7. leu Screen for iRMX® I Nucleus

7-54

Yes
Yes
0014H
0040H
Yes
Never
No

intJ

iRMX® I OPERATING SYSTEM

80286/386 Microprocessors (16-bit, Real Address
Mode Only)

The start-up system for the 80286 processor is configured for Intel SYSTEM 286/300 Series microcomputers with a minimum of 512 Kbytes and a maximum of 896 Kbytes of RAM. The following devices
are supported.

8087 Numeric Data Processor Extension

• iSBC 208
• iSBC 215G/iSBX 218 or iSBC 215GliSBX 218A

8253 and 8254 Programmable Interval Timers

80287/387 Numeric Data Processor Extension
(8087 Functions and Registers)
8259A Programmable Interrupt Controller

• Line Printer for iSBC 286/1X

8251A USART Terminal Controller

• 8274 Terminal Driver

8255 Programmable Parallel Interface

• iSBC 544A Terminal Driver

8274 Terminal Controller

A start-up system is also provided for 386-based designs.

82530 Serial Communications Controller

The systems will run without hardware or software
configuration changes and can be reconfigured on a
standard system with at least 512 Kbytes of RAM.
Definition files are also included for iSBC 186/03A,
186/51 and 188/56 configurations.

ISBC® MULTIBUS BOARD AND SYSTEM
PRODUCTS

This start-up system may be used to run the ICU (if a
Winchester disk is attached to the system) to develop custom configurations such as those pictured in
Figure 5. As shipped, the Human Interface supports
a single user terminal. However, the Start-up System
terminal configuration file may be altered easily to
support from two to five users.

iSBC 186/51 Ethernet Controller

iSBC 86/C38, 86/12A, 80/05A, 86/30, 86/35, and
88/40A Single Board Computers
iSBC 186/03A Single Board Computer
iSBC 188/56 Communications Controller
iSBC 286/10A and 286/12 Single Board Computers
(Real Address Mode only)
iSBC 386/21 and 386/31 (16-bit, Real Address
Mode only)
iSBC 208 Diskette Controller
iSBC 214 and 215(G) Winchester Disk Controllers

SPECIFICATIONS

iSBX 218A Flexible Diskette Multi-Module Controller

Supported Software Products

iSBC 220 SMD Disk Hard Controller

R86ASM86

8086 Assembler and Utilities

iSBC 221 Disk Controller

R86C86

C 86 Compiler

iSBC 534 4-Channel Terminal Interface

R86PAS86

PASCAL 86 Compiler

R86FOR86

FORTRAN 86 Compiler

iSBC 544A Intelligent 4-Channel Terminal Interface
and Controller

R86PLM86

PLIM 86 Compiler

iSBC 548 Intelligent 8-Channel Terminal Controller

iRMX864

AEDIT Screen-oriented Editor

iSBC 552A Ethernet Controller
iSBX 350 Parallel Port (Centronics-type Printer Interface)

Supported Hardware Products

iSBX 351 and 354 Serial Communications Port

COMPONENTS

SYSTEM 86/300 Family

8086 and 8088 Microprocessors

SYSTEM 286/300 Family

80186 and 80188 Microprocessors

SYSTEM 386/300 Family

iSBX 279 Graphics Subsystem

7-55

intJ

iRMX® I OPERATING SYSTEM

ettes. The software includes one set of user manuals and 90 days of initial support. This support includes: "TIPS" Technical Information Phone Service; software updates that occur during the support
period; monthly ";Comments" magazine and quarterly Troubleshooting Guide; Software Problem Report Service; and membership in the Insite User's
Program Library.

USER MANUALS
The iRMX I Operating System is provided with one
five volume set of reference manuals:
Volume I
iRMX I INSTALLATION AND PROGRAMMER'S GUIDES
Volume II
iRMX I OPERATING SYSTEM USER
GUIDES
Volume III iRMX I SYSTEM CALLS
Volume IV iRMX I OPERATING SYSTEM UTILITIES
Volume V iRMX I INTERACTIVE CONFIGURATION UTILITY REFERENCE GUIDE
Additional sets of manuals may be ordered.

Training Courses
Training courses are available on the iRMX I Operating System, Intel languages, and Intel microprocessor architectures.

ORDERING INFORMATION

Please contact your local Intel Sales Office or authorized distributer for product order codes.

LICENSING
Before iRMX I software will be shipped, a customer
must sign (or have already signed) Intel's Software
License Agreement (SLA). Once the SLA is signed,
the customer is licensed to use the iRMX software
for application development. Customers who want to
"incorporate" portions of the iRMX I Object Code in
an application, will have to sign an Incorporation License which clearly spells out the terms and conditions under which incorporations can be made. Con'tact your local Intel office for more information and
for appropriate licensing.

iRMX I Operating System development software is
·available on both 5%" and 8" iRMX-format disk-

7-56

INTEL SYSTEM V/386 PRODUCT FAMILY

STANDARD UNIX· SUPPORTS MULTIBUS® SYSTEM ARCHITECTURES
The UNIX System V/386 operating system now delivers full support for Intel's MULTIBUS II
System Architecture. Intel has built a complete System V/386 product family providing
OEMs, System Integrators and Computing Manufacturers with industry standard UNIX,
OpenNET" networking, system hardware, and Ada development tools for the MULTIBUS II
System Architecture. Together, these elements deliver a rich, complete UNIX development
environment. System V/386 family products are also available for MULTI BUS I system
architectures.
The UNIX System V operating system is the core of the family. It provides portability of
applications and systems programs from one hardware architecture to another, and
robust development support. Integrated with Intel's System 520 MULTIBUS II system, the
UNIX operating system provides a powerful open system platform. The System V/386
product family is ideal as a base for developing custom multi-user systems, applications
and mUlti-purpose network servers requiring open system configurability and flexible
packaging.

FEATURES:
• Standard UNIX System V/386, Release
3.2
• System V Interface Definition, Issue 2
(SVID2) certified; de facto 386
Application Binary Interface conform ant
• Native 32-bit, 386" UNIX port
• 80287 and 387'· numeric coprocessor
support
• Integrated support for MULTIBUS II
System Architecture (MSA) Standards

• UNIX System V STREAMS & TLI-based
System V/OpenNET networking
• UNIX hosted and targeted Ada-386
compilation system support
• Complete documentation
• Worldwide service and support

intel",----·- - - - - - - - - ~

Intel Corporallon 1989

7-57

September, 1989
Order Number 280692-001

SYSTEM V/386 OPERATING SYSTEM
STANDARD UNIX OPERATING SYSTEM AND TOOLS
Intel has worked with AT&T and others to produce a powerful UNIX
System V technology base for the 386 microprocessor and
MULTIBUS systems. The System V/386 package contains the
complete, standard UNIX operating system and development
environment. The C Programming Language Utilities, System
Generation Utilities, the Advanced Programming Utilities, and
Productivity tools are included in the product, in addition to all
basic, runtime facilities.

STANDARD UNIX SYSTEM V FEATURES
Ongoing enhancements and improvements to System V/386
releases included are executable shared libraries, demand pagingl
virtual memory, reliable signals, the 2KB file system, file and record
locking, media independent UUCP, extensive terminal support
utilities, the terminfo database and tools, and multiple installation
and system administration tools. Support for international
environments, including full support for 8-bit code sets, alternate
date and time formats, and alternate character and conversion sets is also provided. In addition, MULTIBUS II
MSA support has been integrated into AT&Ts UNIX System V/386 source code package as a standard
feature, available from both AT&T and Intel. Conformance to final IEEE POSIX standards will be provided In
future releases.

MULT/BUS " SYSTEM ARCHITECTURE SUPPORT
Intel\; System V/386 product comes with complete support for the MULTIBUS II System Architecture (MSA) in
the UNIX kernel. MSA delivers open system interface and protocol standards that build on and extend the
basic MULTIBUS II (IEEE/ANSI1296) bus standard. MSA specifications define diagnostics control, built-in selftest, system initialization and boot loading, board configuration, transport message passing, and an OSI
Transport Interface. The UNIX system developer has available an application level interface and a kernel driver
level interface to MULTIBUS II transport message passing and interconnect space. Use of these MSA
interfaces masks the system bus specifics from the system and application developer, facilitating system
integration.

OSI STANDARD TRANSPORT
OSI transport services support the use of the MULTIBUS II backplane as an ultra-fast network. Multiple peerto-peer 386 application processors can operate as independent networked UNIX ·systems" over a Single
MULTIBUS II Parallel System Bus (PSB). Two UNIX application processors, each with its own hard disk, can be
installed in a UNIX System 520, and each processor provides a TLI-based application interface for complete,
transparent, inter-CPU and application communications. Large( system configurations with more processor
boards can also be built using these standard interfaces. System V/OpenNET utilizes TLI to provide
transparent, distributed file sharing, file transfer and Virtual Terminal facilities for networked UNIX systems.

SYSTEM V/386 "ABI" FOR UNIX BINARY APPLICATION PORTABILITY
The creation of a defacto standard ABI (Application Binary Interface) for the Intel 386 architecture makes
machine-independent execution of UNIX/386 binary applications a reality. This opens up the System V/386
operating system, so application developers no longer have to port applications and test them on different
System V/386 machines. It makes possible a world of off-the-shelf, shrink-wrapped, UNIX binary applications
for any and all 386 machines supporting the ABI standard.

SOURCE RELEASES
The complete MULTIBUS I and II source base IS available to AT&T and Intel-licensed customer sites. Device
driver source licenses and code are also available independent of the complete UNIX source base products.

SYSTEM V/OpenNET
COMPLETE OpenNET LAN SOLUTION FOR UNIX
SYSTEM V/386
UNIX STREAMS and TLI (Transport Level Interface) facilities are a
standard part of Intel System V/386. Intel has developed and is
delivering a STREAMSITLI-based version of OpenNET for
MULTIBUS UNIX systems, called System V/OpenNET. It provides
interoperation and communication with all OpenNET family
products, Including iRMX-NET, MSNET(PCLlNK2), VMS'NET,
XNXNET and iNDX OpenNET. The product comes packaged as a
complete hardwarelsoftware solution including an Ethernet
communications controller board, mail, virtual terminal, print
spooler, nameserver interface library (NSI), and network
management facilities. Support for TCP/IP networking is available
from independent sources. System V/OpenNET is available for
both MULTIBUS I and MULTIBUS II architectures.

THE UNIX SYSTEM 520
AN OEM MULTIBUS /I DISTRIBUTED SYSTEM
The Intel System 520 is part of a family of customizable MULTIBUS II
multiprocessor platforms designed for OEMs demanding the
highest levels of flexibility, configurabllity and compatibility. The
UNIX System 520 makes full use of Intels standard MSA, the Intel
386 microprocessor and the UNIX System V standard. This
powerful, compact MULTI BUS II system is available as a complete,
System V/386 networked development system, or as an
expandable, configurable OEM system or server. The System 520
allows users to add to the basIc configuration or to purchase and
integrate specific system contents separately.

STANDARD FEATURES:
•
•
•
•
•
•
•
•
•

High performance Intel 386 MULTI BUS II OEM system
System V/386, Release 3.2 mUlti-user operating system
Complete UNIX (SVID2) Software Development Extension
One 386 application processor
386 microprocessor-based SCSI disk controller
186/410 six-channel serial 1/0 controller
186/530 Ethernet controller
iSBX'· 279 Hardware Window console controller (no graphics)
Easy system expansion via Intel's MULTIBUS II System
Architecture (MSA) & iSBC'" board family
• OpenNET transparent remote file sharing & virtual terminal

SYSTEM V/386 SELF-TARGETED ADA*-386 COMPILATION SYSTEM
UNIX HOSTED ADA-3S6 DEVELOPMENT
Intel's System V/386 Self-Targeted Ada-386 Compilation System
comprises a rich set of Ada language tools for the programmer
wanting to develop Ada applications for the Intel System 520. This
UNIX hosted, self-targeted and validated Ada toolset contains the
Compiler & Library Tools, the Global Optimizer, the COFF Linker,
an Ada Execution Environment, an Ada Symbolic Debugger, as
well as other development environment tools for handling crossreferencing, source dependency, and source formatting. The
compiler and its tools create a flexible, project-oriented
development environment for commercial, industrial, and military
applications.

ORDERING INFORMATION
BACKED BY INTEL MANUFACTURING
AND CUSTOMER SUPPORT
All Intel software and hardware products are fully
supported by Intels worldwide staff of trained service
and support engineers. Intel also provides system
engineering and field applications consulting
services, worldwide training workshops, a full range
of maintenance services, and a software support
hotline. Custom board and system configurations, as
well as custom manufacturing, can also be provided
by Intel. Every product includes a standard 90-day
warranty replacement guarantee. Selected products

include an extended warranty package. The
complete UNIX System 520 development package
(SYS520R1DKITSV) is backed by a full, one-year
service and support package. See specific product
literature for more details.

LICENSING
Each copy of UNIX is licensed for use on a single
system, and Intel provides licenses for copying and
distributing MULTIBUS I1II versions of System V/386.
Licensing for the use of source code and distribution
of binary, derived works is also available.
7-59

ORDERING INFORMATION
SYSTEM 520 CONF/GURATION/OPTIONS- TABLE 1

Product

System 520 OEM *
Base Plus 110
System 520 OEM
Base *
System 520**
Development System

V'
V'

Add-'
In.
Add-'
In.

V'
V'

*Available in either floorstand or tabletop configurations
**iRMX and UNIX System V/386 options available
'Contact Intel for configuration availability information.

SYSTEM V/386 FAMILY ORDER CODES
The UNIX System 520 Products:
SYS520R1DKITSV
System V/System 520 MULTIBUS II Development System (h/w and s/w,
fioorstand)
System 520 MULTI BUS II Base Plus OEM System-(h/w only, floorstand)
SYP520R1BP
SYP520R1BPT
System 520 MULTIBUS II Base Plus OEM System-(h/w only, tabletop)
SYP520R1B
System 520 MULTI BUS II Base OEM System-(h/w only, floorstand)
SYP520R1BT
System 520 MULTI BUS II Base OEM System-(h/w only, tabletop)

System V1386, Release 3.2 Products:
MULTIBUS II UNIX binary tape and documentation
MULTIBUS I UNIX binary tape and documentation
MULTIBUS 11/1 UNIX source tape and documentation

SYSTEMV38611
SYSTEMV3861
SYSTEMVSRC

System V/OpenNET Products1:
pSVNET530KIT
SV-OpenNET with iSBC 186/530 on MULTIBUS II architecture
pSVNET552AKIT SV-OpenNET with iSBC 552A on MULTIBUS I architecture
System VI386 Self· Targeted Ada-386 Products:
U386ADA386SW UNIX hosted, Self-Targeted Ada-386 Compilation System for System
520 MULTIBUS II OEM Systems
U386ADA386SS
UNIX hosted, Self-Targeted Ada-386 Software
'These products are manufactured by Intel Puerto Rico.
For more information or the number of your nearest Intel sales office, call 800-548-4725
(good in the U.S.
and Canada).

7-60

intJ

APPLICATION
NOTE

AP-405

May 1987

Software Migration From
iRMX® 86 to iRMX® 286

MAYNE MIHACSI
OSD Technical Marketing

Order Number 280608-001 .

INTEL CORPORATION, 1987
7-61

AP-405

INTRODUCTION
The iRMX@ 286 operating system represents the evolution of the iRMX@ 86 operating system to the protected-mode
80286 and 80386 microprocessors. Therefore, the iRMX 286 operating system has most of the same features of its 8086
counterpart.
Many Intel customers are going to migrate their software from iRMX 86 to iRMX 286. Most customers should be
pleasantly surprised at the ease of migration between the two operating systems. This compatibility between the two
operating systems was a key objective of the iRMX 286 project. Thus in the majority of cases, an iRMX user should
encounter no changes or only trivial changes when porting their software to iRMX 286. In the other cases, iRMX users
with a little patience, work, and the help of this paper, should quickly have their application running on iRMX 286.
Before reading this migration note, it is strongly suggested that readers acquaint themselves with the fundamentals of the
80286 architecture.

iRMX® 286 SYSTEM ARCHITECTURE
There are inherent differences between iRMX 86 and iRMX 286 due to the differences in microprocessor architectures.
To take advantage of some unique 80286 features additional system calls have been added in the iRMX 286 operating
system. These new calls can be identified by an RQE$ in their preface, with the E denoting "extended", to take advantage
of the 80286's 16MB addressability.
Figure 1 lists the differences for each layer of iRMX 286.

iRMX@Layer

iRMX@ 286 Changes

Nucleus

BIOS

- Memory buffer protection

EIOS

New calls
- Memory buffer protection

Application Loader

- Only loads 80286 OMF records
- Only loads STL modules
- Newcalls

Human Interface

- Enhanced eLi
- New commands

UDI

- Newcalls

16MB address space
New hardware traps
Descriptor management
Privilege management
Round robin scheduling
Interrupt management
Newcalls

Bootstrap Loader

- New third stage interface

leu

- Single stage leu
Figure 1. iRMX@ 286 Architectural Differences

7-62

280608-001

AP·405
iRMX® 286 NUCLEUS
16 Megabyte Address Space
Today's applications have pushed beyond the 1MB memory limitation of the 8086 architectures. Many Intel customers
have chosen iRMX 286 simply because of its ability to address 16MB of memory. While the 80286 architecture allows for
accessing 24 physical address lines, to yield 16MB physical and 16MB virtual addressability, the operating system is not
automatically allowed the same abilities. As further generations of CPUs become available and memory becomes cheaper,
operating systems will strive toward hardware independence. One method used is accessing memory logically, not physically. In the iRMX 286 operating system all memory addresses are logical addresses available via a descriptor table. A
logical address may be thought of as a pointer consisting of a selector and an offset. The selector will point to an entry in a
descriptor table containing the 24-bit physical address. Therefore, tokens are affected by containing selectors that reference an entry in the descriptor table. No longer do tokens contain the physical address of an object.

New Hardware naps
Because the 80286 processor detects several types of exceptions and interrupts from exceptions, iRMX 286 also alerts
programs generating these exception conditions. These hardware traps will be generated from the following conditions:
INTERRUPr
VECTOR

8
9
10
11
12
13

FUNCTION
Double exception
Processor extension segment overrun
Invalid task state segment *
Segment not present *
Stack segment overrun or not present
General protection

*Seldom seen
Users porting iRMX 86 code to iRMX 286 should be aware that the working code in iRMX 86 might still contain errors
that will be "trapped" in iRMX 286.

Descriptor Management
While the 80286 CPU is in Protected Virtual Address Mode (PVAM), all application programs deal exclusively with
logical addresses. That is, the programs do not directly access actual physical addresses generated by the processor.
Instead, a memory-resident table, called a descriptor table, records the mapping between the segment address and the
physical locations allocated to each segment. Whenever the 80286 decodes a logical address, translating a full 32-bit
pointer into a corresponding 24-bit physical address, it implicitly references one of several descriptor tables. One table is
called the Global Descriptor Table (GDT) and provides a complete description of the global address space. Another table
is provided, the Local Descriptor Table (LDT), to describe the local address space for one or more tasks. To the application programmer, much of the internal operation and management of the descriptor tables are transparent. However, the
systems programmer will need to manage the descriptors to:
A. Gain access to undefined or allocated memory areas, and
B. Add device drivers to the system.
Several new calls were added to help manage descriptor tables:
1.

RQE$CREATE$DESCRIPI'OR

RQE$CHANGE$DESCRIPI'OR

3. RQE$DELETE$DESCRIPI'OR
For the applications programmer several features are available in iRMX 286.
1.

Of the maximum 8K objects available, all are indexed in the GDT with the operating system using the LDT.

2. While using an iRMX 86-style task switch, iRMX 286 runs as one 80286 hardware task.

7-63
280608·001

AP-405

Privilege Management
Some means of protection is required to prevent programs from improperly using code or data that belongs to the
operating system. The four privilege levels of the 80286 are numbered from 0 to 3, where 0 is the most trusted level. The
privilege level is an attribute assigned to all segments in a hierarchical fashion. Operating system code and data segments
are placed at the most privileged level (0) which is where iRMX 286 operates. (See Figure 2.)
The privilege levels apply to tasks and three types of descriptors:
1.

Main memory segments

Gates

Thsk state segments (not used in iRMX 286)

Of particular interest to discussions concerning iRMX 286 is the gate descriptor and its usage in application programs.
Of the four types of gates in the 80286 processor, iRMX 286 uses call gates. Once invoked, control is transferred using
only the selector portion. This address becomes fixed, allowing any program to invoke another. This prohibits tasks that
have not used these entry points from jumping into the middle of the operating system. The use of gates is fundamental to
the 80286 architecture and is reflected in other areas of iRMX 286.
All iRMX 286 system calls go through a call gate in order to invoke a given service procedure. In the iRMX 86 operating
system, all calls were through software interrupts, invoking an operating system extension handler, then finally the service
procedure. For iRMX code that was written for the iRMX 86 operating system, this will have little impact until it comes
time to build the system, unless a conflict exists between the old and new nucleus calls. (See next section.) Analogous to
the iRMX 86 operating system having a software interrupt at each level, iRMX 286 possesses call gates for each system
call at each layer of the operating system, eliminating the need for an operating system extension handler. Call gates can
be specified through system calls and the Interactive Configuration Utility (ICU). (See the example for RQE$SET$OS$
EXTENSION.)

TASK A

Figure 2. Example Privilege Level Assignments

7-64

280608'{)Ol

AP-405

IRMX@86

System
Calls

....

(

os
Software
Interrupt

Extension
Handles

)

Service
Procedures

iRMX@286
System Call

--------i..~

-------l.....

Service Procedure

System Call

- - - - - - . . . . . Call Gate - - - - - - . . . ,..~

Service Procedure

System Call

------.....

Call Gate - - - - - - . . ,..~

Service Procedure

Call Gate

Call Gates vs. Software Interrupts

Round Robin Scheduling
The iRMX 286 operating system schedules tasks based upon tasks competing for CPU resources. Th prevent the occurrence of one or more tasks waiting indefinitely, round robin scheduling is available on the iRMX 286 operating system.
One area that could benefit from this scheduling scheme is multi-user environments.
Round robin scheduling will permit equal priority tasks a finite time they may have control of the processor. Once the time
expires, the task with the same priority and ready will gain CPU control. Hardware interrupts and higher-priority tasks
can still bump any of the lower-priority tasks from running. This scheme allows all equal priority tasks an opportunity to
execute.
This scheduling is determined in the "nucleus" screen of the Interactive Configuration Utility (ICU). (See the iRMX 286
Interactive Configuration Utility Reference Manual for details.)

Interrupt Management
In the iRMX 286 operating system interrupt management has changed. In the iRMX 86 operating system an interrupt
vector table contains the address of an interrupt handler. In the iRMX 286 operating system this table has been called the
Interrupt Descriptor Thble (lDT) and is very similar to the GDT and LDT, except that it is referred to only when an
interrupt occurs. Interrupt IJddresses can be entered into the IDT when using the iRMX 286 SET$INTERRUPT nucleus
system call. Entering interrupts is still identical for both operating systems, however, with PLiM 286 not having a
SET$INTERRUPT built in, interrupts have become easier to use. (See the section on PLiM 286.) The following is a
description of the allocated interrupt entries. (Also see the section on BUILD 286 for another way to set interrupts.)

7-65
2S060S'()01

AP-405
Entry Number

o
1
2
3
4
5
6
7

8
9
10
11
12

13
14-15
16
17-55
56-63
64-127
128-255

iRMX® 286 Interrupt Allocation Description
Divide by zero
Single step (used by iSDMTM 286)
Power failure (non-maskable interrupt, used by iSDMTM 286)
One-byte interrupt instruction (used by iSDM 286)
Interrupt on overflow
Run-time array bounds error
Undefined opcode
NPX not presentlNPX task switch
Double fault
NPX segment overrun
Invalid TSS
Segment not present
Stack exception
General protection

NPXerror

8259A PIC master
8259A PIC slaves
* Available to users *

New Calls
GENERAL RULES

IMPORTANT
Here are some general rules to apply.
1. All iRMX 286 system calls beginning with RQ$ ... are 100% compatible with iRMX 86.
2.

All iRMX 286 system calls beginning with RQE$ ... are new to iRMX and exist only in iRMX 286.
a. All iRMXI86 system calls beginning with RQ$ ... for which there is a like iRMX 286 system call beginning
with a RQE$ ... use the function procedure of the RQE$ ... call.

All iRMX 286 system calls and user extensions use call gates.

All iRMX 86 BIOS, EIOS, and loader calls are 100% compatible with iRMX 286 calls.

All objects are identified by 16-bit tokens which represent an entry in the Global Descriptor Table (GDT).

The iRMX 286 system call RQE$SET$OS$EXTENSION must be used in place of
RQ$SET$OS$EXTENSION. This call dynamically attaches an operating system extension to a call gate.
A few specific system calls merit further discussion.

7-66
280608-001

AP-405
RQE$SET$OS$EXTENSION
This system call as mentioned in Rule 6 above will find the following usage.
DECLARE
. Typical PUM 286 statements
MY$OS$EXT: PROCEDURE EXTERNAL;

. Typical PUM 286 statements

END MY$OS$EXT;
CALL RQE$SET$EXTENSION (0141H, @MY$OS$EXT, @STATUS);
Where: 0141 H represents the entry number of the call gate from the GDT. This parameter is named
GATE$NUMBER.
@MY$OS$EXT represents the pointer to first instruction of MY$OS$EXT. This parameter is
named START$ADDR.
@STATUS represents a pointer to a word containing the condition code for this call. This parameter is named EXCEPT$PTR.

A user-written operating system extension can also be attached to a call by the Interactive Configuration Utility (ICU).
Example of an ICU screen:
OS Extension
(GSN) GDT slot number
(OCN) entry pOint name

[0140H-01 FFEH] 0141 H
[1-45 characters] MY$OS$EXT

Enter changes [Abbreviation ?I = NEW_VALUE]:
Do you need any more O.S. extensions?

This causes the GDT slot 141H to be configured as a call gate whose entry point is MY$OS$EXT.

RQE$CREATE$JOB
This call is an example of Rule 2a where two calls perform nearly the same function. In this case the extended versions of
POOL$MIN and POOL$MAX parameters are DWORDS instead of WORDS. This is to allow a memory pool of up to
16MB for tasks and objects. While RQ$CREATE$JOB will create a memory pool of up to 1MB, it will use the same
function procedure as RQE$CREATE$JOB. This is possible because the RQ$CREATE$JOB interface procedure changes
the word pool parameters to DWORDS by padding them with zeros, then calling the RQE$CREATE$JOB function
procedure.

RQ$CREATE$SEGMENT
This call's first parameters, SIZE, yields a different value than in iRMX 86.
In iRMX 86:
Where:
In iRMX 286:
Where:

Segment = RQ$CREATE$SEGMENT (SIZE, EXCEPT$PTR);
SIZE is a word containing the size, in bytes, of the requested segment in MULTIPLES OF
16 BYTES.
SEGMENT

= RQ$CREATE$SEGMENT (SIZE, EXCEPT$PTR);

SIZE is a word containing the actual memory size in bytes.

7-67
280608-001

inter

AP-405

RQ$GET$POOL$ATTRIB
In this case more parameters have been added.
In iRMX 86: RQ$GET$POOL$ATIRIB (ATIRIB$PTR, EXCEPT$PTR);
Where: ATIRIB$PTR is a pointer to the following structure.
Structure (POOLMAX WORD,
POOLMIN WORD,
INITIAL$SIZE WORD,
ALLOCATED WORD,
AVAILABLE WORD);
In iRMX 286:

RQE$GET$POOL$ATIRIB has a different structure though everything else is the same
Structure (TARGET$JOB TOKEN,
PARENT$JOB TOKEN,
POOLMAX DWORD,
POOLMIN DWORD,
INITIAL$SIZE DWORD,
ALLOCATED DWORD,
AVAILABLE DWORD,
BORROWED DWORD);

RQ$SET$INTERRUPT
Users should also be aware of the following when using this call in iRMX 286. When specifying interrupts in iRMX 286,
a special descriptor table called the Interrupt Descriptor Thble (IDT) is located at a user-specified address in memory. This
table is accessible through an entry in the Global Descriptor Thble (GOT). This makes an interrupt procedure entry point
to be directly accessed via a jump to the specific SELECTOR:OFFSET pointer in the IDT. All interrupts will have a
SELECTOR:OFFSET address just as in the iRMX 86 operating system. Therefore, the system calls syntax will remain
the same, except the parameter called INTERRUPT$HANDLER as shown below:
Example: iRMX 286
CALL RQ$SET$INTERRUPT (LEVEL, INTERRUPT$FLAGS, INTERRUPT$HANDLER,
INT$HANDLER$DS, EXCEPT$PTR);
Where INTERRUPT$HANDLER, the entry point to the interrupt handler, should be coded directly, i.e.,
@MY$HANDLER.
By referencing a handler directly, all other intermediate steps are unnecessary. (See the example in the PL/M 286 section.)

BASIC INPUT/OUTPUT SYSTEM (BIOS)
The BIOS of the iRMX 86 operating system is nearly identical to the iRMX 86 operating system BIOS. The same system
calls are available with no changes or additions. The significant differences between the two BIOS's are the 16MB
addressabiJity and memory protection available in the iRMX 286 operating system.

Protection
The memory protection offered by the iRMX 286 operating system BIOS protects the code and data by preventing any task
from reading or writing a segment of memory unless explicit access has been granted. It also prevents memory reads or
writes from crossing segment boundaries. Therefore any task using the'A$READ or A$WRITE BIOS system calls must
have read or write access privileges.
7-68 280608'()Ol

AP-405
Device Drivers
Not all iRMX 86 operating system device drivers have been included in the iRMX 286 operating system. Consult the
following list or the iRMX 286 Interactive Configuration Utility for the specific Intel-supplied drivers.
Intel Device Drivers Supplied With iRMX® 286 R. 2.0

iSBC® 215G
iSBC214
iSB)(TM 218A
iSBX 217C
iSBC220
iSBC208
iSBX251
iSBC 264
iSBX 350 Line Printer
Line Printer for 286/10

iSBC534
iSBC 544
Terminal Comm Cntlr
to include:
iSBC 188/48
iSBC 188/56
iSBC546
iSBC547
iSBC 548
8274
8251A
82530
RAM disk

iSBC 286110
iSBC 286/10A
iSBC 286/1 X
iSBC386/2X

Not included are the following device drivers:
iSBC204
iSBC206

SCSI
iSBC 226

EXTENDED INPUT/OUTPUT SYSTEM (EIOS)
The EIOS of the iRMX 286 operating system is nearly identical to the iRMX 86 operating system BIOS. The same system
calls are available with few changes and additions. The significant differences between the two EIOS's are the 16MB
addressability and memory protection available in the iRMX 286 operating system.

Protection
The memory protection offered by the iRMX 286 operating system EIOS protects the code and data by preventing any task
from reading or writing a segment of memory unless explicit access has been granted. It also prevents memory reads and
writes from crossing segment boundaries. The system calls S$READ$MOVE and S$WRITE$MOVE are two calls that
will send an exception code called E$BAD$BUFF whenever this occurs.

Extended Memory Pool
Since the iRMX 286 operating system supports the 16MB addressability of the 80286 processor, the memory pools
created by I/O jobs can also be as large as 16MB. The new system call providing this feature is called RQE$CREATE$
IO$1OB.

New Calls
Several new system calls have been added to the iRMX 286 operating system EIOS layer. They are:

1. RQE$CREATE$IO$1OB
POOLMIN and POOLMAX parameters changed to DWORDS for 16MB addressability.
2.

RQS$GET$DIRECTORY$ENTRY
Retrieve name of any file in a directory.

RQS$GET$PATH$COMPONENT
Retrieve name of any file as it is known in its parent directory.
7-69

280608·001

AP-405

iRMX® 286 APPLICATION LOADER
802860MF
Two utilities are supplied with the iRMX 286 operating system to load programs and data into system memory from
secondary storage devices. They are the bootstrap loader and the application loader. Typically the bootstrap loader is used
to load the initial system and begin its execution. The application loader will typically be called, by programs running in
the system, to load additional programs. The application loader can load I/O jobs up to 16MB. These programs must be in
the 80286 Object Module Format (OMF). This differs from the iRMX 86 operating system, which loads only 8086 OMF
records. Further, the 80286 records must be in STL format. (See a later section called BND 286 for a discussion of STL
format.)

New Calls
RQE$A$LOAD$IO$JOB
This calls memory pools changed to DWORD values from word. (See RQE$CREATE$JOB call in the Nucleus section.)

RQE$S$LOAD$IO$JOB
Same as above.

HUMAN INTERFACE
Enhanced Command Line Interpreter (CLI)
The new CLI provides line-editing features, as well as its own set of commands. With CLI commands, aliases
can be created, background programs ran, output redirected or redefmed for a terminal in the configuration file. The
commands are:

ALIAS
HISTORY

BACKGROUND
JOBS

KILL

CHANGEID
LOGOFF

SET

DEALIAS
SUBMIT

EXIT
SUPER

To include or customize features in the CLI, user extensions have been added to the Human Interface.

New Calls
ADDLOC

LOGOFF

SHUTDOWN

LOCK

UNLOCK

ZSCAN

Old Calls
The follOwing Human Interface commands have been revised:

BACKUP

DISKVERIFY

FORMAT

LOCDATA

RESTORE

7-70
280608-001

AP·405
UDI

New System Calls
The iRMX 286 UDI contains three system calls not contained in the iRMX 86 UDI. They are:
DQ$MALLOCATE
DQ$MFREE
DQ$GET$MSIZE
All of the calls have their counterparts in the iRMX 86 UOl, however, the new system calls use full pointers instead of
selectors and DWORD instead of WORD for memory block start address and size specifications, respectively.
These three calls are only supported in programs compiled in the compact or large segmentation models. Also, earlier
versions of these calls cannot be mixed. For example:
After using DQ$MALLOCATE to allocate memory, do not use DQ$FREE to free it.
Use DQ$MFREE instead.

BOOTSTRAP LOADER
Two Stage Loader
To facilitate loading an application so that it may execute has been known as "pulling it up by its bootstraps" or simply
"booting" the application. iRMX bootstrap loaders have been divided into stages, each possessing a unique purpose
and role.
In the iRMX 86 operating system, the bootstrap loader exists as only two stages. The first stage resides in PROM located
on the CPU's board. If supplied by Intel, it will occupy less than 8Kb of memory within the PROM. Once running, it will
identify the applications name and location, then load part of the second stage, passing control to it. The second stage
finishes loading itself, loads the application into memory, then passes control to the application. While the first stage is
user-configurable, the second stage is not. The second stage is only supplied by Intel and is present on all iRMX
formatted, named volumes.

New Third Stage
lri the iRMX 286 operating system, the bootstrap loader exists as three stages. The extra stage was added to be able to load
80286 OMF files. This will also permit loading 8086 OMF files with just the first and second stages. This means either
system can be booted without compromising the other. To allow for this, some files have to be renamed and some new
conventions adopted. (See below and Figure 3.)
1.

All 80286 OMF bootloader application systems must have the extension" .286".

2. The third stage bootstrap loader must have the same name as the application, less the extension.
3.

The third stage bootstrap loader must reside in the same directory as the bootloadable system.

File Name Conventions
Third Stage

System to be Loaded

ISYSTEM/RMX86

ISYSTEM/RMX86.286

ISYSTEM/RMX

ISYSTEM/RMX.286

IBOOT/RMX286

IBOOT/RMX286.286

This chart indicates to those wanting to boot the iRMX 86 operating system that their file ISYSTEM/RMX86 had better
be renamed to avoid confusion.

7-71
2B060B'()01

AP-405

INPUT
OR

'
!il
~

860MF

,
'

1st STAGE
ON-BOARD
PROM

IRMX" FORMATTED
VOLUME WITH
IRMX" 286
BOOTSTRAP 2nd STAGE

iRMX· FORMATTED
VOLUME WITH
iRMX· 286
BOOTSTRAP 2nd STAGE
m·0803

Figure 3.

When installing the iRMX 286 operating system on a system containing the iRMX 86 operating system, the "BS" option
of the format command will install ONLY the new second stage bootstrap loader on track 0 of the hard disk. The
installation process will also add new directories as required by the iRMX 286 operating system.

Memory Locations of the Three Stages
Bootstrap Loader Locations
Description

Default

Approx. Size

1st STAGE CODE

Application
dependent

12KB

BS1.CSD

2nd STAGE CODE
1stl2nd DATA
and STACK

OB8000H

8KB

BS1.CSD

3rd STAGE
(specific) CODE
DATA and STACK

OBCOOOH

16KB

BS3.CSD

3rd STAGE
(generic) CODE

OBCOOOH

8KB

BG3.CSD

3rd STAGE
(generic)
DATA and STACK

OB8000H

BG3.csd

7-72

Config. File

280608-001

AP-405

CONFIGURATION SIZE CHART

iRMXI!l286
Memory
Requirements

Operating
System
Layer
Nucleus
BIOS
EIOS
Application Loader
HI
UDI

34K
95K
19K
12K
36K
11K

Bootstrap Loader

leu

iRMXI!l86*
Code
Size

iRMX1!l286*
Code
Size

24K
78K
12.5K
10K
22K
8K
1.5K

27K
67K
16K
11K
26K
9.4K
32K

iRMXI!l86*
Data
Size

IRMXI!l286*
Data
Size

2K
1K
1K
2K
15K
OK
6K
308K

3.5K
19.5K
16.75K
2K
1K
0.1K
6K
384K

"These numbers reflect actual memory size required to support the different configurations of the operating systems.

FILE STRUCTURE
The file system of the iRMX 286 operating system provides for the same types of files as are on the iRMX 86 operating
system. In fact, both file systems can exist on the same volume using the same hierarchical file structure. This is made
possible through the installation of the iRMX 286 bootstrap loader's second stage onto the iRMX 86 operating system's
volume. This second stage will allow either operating system to be booted from the same volume. One fact should be
remembered: iRMX 286 uses the 80286 OMF, while iRMX 86 uses the 8086 OMF. This stops either operating system
from loading and executing the other's files or programs. Copying, deleting or other maintenance operations can still be
accomplished across the volume. iRMX 286 operating system will also read iRMX 86 back-up format files from another
volume. The following Figure 4 shows a file system with both operating systems installed, including the changes to its
structure. Remember, iRMX 286 can reside by itself or with iRMX 86 on the same volume.

Conventions
New file conventions have been adopted to differentiate between several types of files. They are:
*. P28
*.P86
*.A28
*.A86
*.GAT

PLIM 286 source files
PLIM 86 source files
ASM 286 source files
ASM 86 source files
Gate defmition files'

*.BLD -

Build, file for BLD 286

* .286

Bootable iRMX 286 system file

*.86

Bootable iRMX 86 system file

After booting iRMX 286, the following assignments are assumed:
: SYSTEM:

ISYS286

:UTIL:

IUTIL286

: LANG:

ILANG286

After booting iRMX 86, the following still apply:
: SYSTEM:

ISYSTEM

:UTIL:

IUTILS

: LANG:

ILANG

7-73

280608'()01

(
iRMX' 86.86
DIR

COPY

tDIR

COpy

I- AEDIT

SUPER

IS'

o-'="

.....
.:,.

....

'Denotes file additions
Diagram reflects the installation of iRMX' 286
upon an iRMX· 86 volume.

m·OSO?

AP·405
LANGUAGES: ASM 286
Because ASM 286 supports the 80286 in protected mode, ASM 286 has more changes than other languages. Often users
converting their programs to ASM 286 from ASM 86 will assemble the programs in ASM 286 and store the error
messages generated and change the code accordingly. A few notable changes are listed below.

Group Directive
ASM 286 does not possess a group directive as in ASM 86. By giving the segments the same name, they will be grouped
together into one segment at link time.

Example: ASM 86
DATAGRP GROUP DATA 1, DATA2
DATA 1 SEGMENT
ABYTE DBO
DATA1 ENDS
DATA2 SEGMENT
AWORDDWO
DATA2ENDS
ASSUME DS:DATAGRP
: ASM 286
DATA1 SEGMENT RW PUBLIC
ABYTE DBO
DATA1 ENDS
DATA1 SEGMENT RW PUBLIC
AWORDDWO
DATA1 ENDS
ASSUME DS:DATA1

In one module

In another module

Segment Directive
The fields of the SEGMENT directive are also different. ASM 286 does not use anything but para-aligned and
access-type.

Example: ASM 86
NAME SEGMENT [ALIGN-TYPE] [COMBINE-TYPE]
WHERE [ALIGN-TYPE] = PARA, BYTE, WORD, PAGE, INPAGE,
OR NONE
ASM286
NAME SEGMENT [ACCESS-TYPE] [COMBINE-TYPE]
WHERE SEGMENT IS ALWAYS PARA-ALIGNED AND
[ACCESS-TYPE] = READ-ONLY (RO),
EXECUTE-ONLY (EO).
EXECUTE-READ (ER), or
READ-WRITE (RW)
Class name is also not present in ASM 286

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Stack Segment
In ASM 286, stack segments are defined using the STACKSEG directive.

Example: ASM 286
,. MEANS 10 BYTES ON STACK·/

PROG_STACK STACKSEG 10;

The operator STACKSTART is used to define a label at the beginning of the stack to initialize the Stack Pointer (SP).
Example: ASM 286
MOV Sp, STACKSTART PROG_STACK

Selector Access
In ASM 286 the selectors used for the DS, SS, and ES in the ASSUME directive must have certain access types.
Example: ASM 286
ASSUME DS:EDATA
EDATA SEGMENT RW PUBLIC
WHEREDBO
EDATAENDS

Further, the ASSUME directive will not accept an assume for the code segment. The current code segment being assem'bled is automatically assumed into the CS. For more information regarding other changes in ASM 286 consult: ASM 286
Reference Manual (Appendix G). order #122671

LANGUAGES: PL/M 286
Users migrating their code to PLIM 286 should be aware of the following:

Pointer and Selector Variables
Pointer and selector variables cannot be assigned absolute values. All values must be assigned by reference to another
variable or through based-variables.
Example: PLIM 86
Declare
A$POINTER
Start: DO;
A$POINTER

POINTER;

= 0;

Example: PLIM 286
Declare
A$POINTER

POINTER;

Start: DO;
A$POINTER = NIL;

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Similarly selectors can be assigned values as follows:

Example: PUM 86
Declare token literally 'WORD',
A$TOKEN
TOKEN;
Start: DO;
A$TOKEN

= 0;

Example: PUM 286
Declare token literally 'SELECTOR',
A$TOKEN
TOKEN;
Start: DO;
A$TOKEN

= SELECTOR$OF(NIL);

The only relational operations allowed in PLIM 286 for pointers and selectors are "equals" and "not equals" .

Models of Compilation
In PLIM 86 the default is SMALL
In PLIM 286 the default is LARGE

Interrupt Vectors
In PLIM 286 all interrupt numbers on all interrupt procedures must be deleted. The required interrupt vectors will be
assigned by the 80286 system builder if not already defmed by the iRMX 286 operating system call RQ$SET$
INTERRUPT.
Consequently the PLIM 86 built-ins SET$INTERRUPT and INTERRUPT$PTR are unavailable in PLIM 286 and should
be removed. Also, all calls to interrupt procedures are not allowed. As the conversion process takes shape, all of these
changes tum out better than initially expected as the following example shows.

Example: PUM 86
1. DECLARE

ZERO
LITERALLY
'00001000b',
INTERRUPT_HANDLER POINTER;
· TYPICAL PUM 86 STATEMENTS

6. INTERRUPT_HANDLER: PROCEDURE INTERRUPT 56 PUBLIC REENTRANT;
· TYPICAL PUM 86 STATEMENTS
10.
CALL RQ$SIGNAL$INTERRUPT (ZERO, @STATUS);
11. END INTERRUPT_HANDLER;
12. INTERRUPT_TASK

: PROCEDURE PUBLIC REENTRANT;
· TYPICAL PUM 86 STATEMENTS

16.
17.

INTERRUPT_HANDLER = INTERRUPT$PTR (INTERRUPT_HANDLER);
CALL RQ$SET$INTERRUPT (ZERO, 1, INTERRUPT_HANDLER,
DATA$SEG$ADDRESS.BASE, @STATUS);
· TYPICAL PUM 86 STATEMENTS

21.
22.

CALL RQ$WAIT$INTERRUPT (ZERO, @STATUS);
END INTERRUPT_TASK;

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AP-405

Comments
Line
Number
2.
6.
16.
17.

Description
INTERRUPT_HANDLER was defined as a pointer
Interrupt entry 56 was "hard-coded"
INTERRUPT_HANDLER was assigned the location (address) of the first instruction of the
handler via the PLIM 86 built-in "INTERRUPT$PTR"
This call could have looked like: RQ$SET$INTERRUPT (ZERO, 1, INTERRUPT_PTR(lNTERRUPT_HANDLER), etc eliminating lines 2 and 16.

Example: PLIM 286
1. DECLARE

ZERO

LITERALLY

'00001000b';

· TYPICAL PLIM 286 STATEMENTS
5. INTERRUPT_HANDLER

: PROCEDURE INTERRUPT PUBLIC REENTRANT;
· TYPICAL PLIM 286 STATEMENTS

9.
10.

CALL RQ$SIGNAL$INTERRUPT (ZERO, @STATUS);
END INTERRUPTHANDLER;

11. INTERRUPT_TASK

: PROCEDURE PUBLIC REENTRANT;
· TYPICAL PLIM 286 STATEMENTS

15.

CALL RQ$SET$INTERRUPT (ZERO, 1, @INTERRUPT_HANDLER,
DATA$SEG$ADDRESS.BASE, @STATUS);
· TYPICAL PLIM 286 STATEMENTS

19.
20.

CALL RQ$WAIT$INTERRUPT (ZERO, @STATUS);
END INTERRUPT_TASK;

Comments
Line
Number
5.
15.

Description
Notice PLIM 286 does not need to identify the interrupt in this statement
The third parameter becomes simply a pointer to the first instruction of the handler.

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DEVELOPMENT TOOLS - BND 286
All iRMX 86 programs linked using LINK 86 will instead have to be bound using BND 286. BND 286 is used to create all
single-task application programs that will be dynamically loaded. (See Figure 5.) The following are tasks of the binder.
1. Creates a linkable or loadable module by combining input modules with other bindable modules.
2. Checks the type of variables and procedures.
3. Selects modules from libraries to resolve all symbolic references.
4. Combines logical segments by name, attribute, and privilege levels into physical segments that the processor can
manipulate efficiently.
5. Can create a module the application loader can load.

Linkable Modules
In a process called incremental linking, BND 286 combines linkable object modules, including library modules, output by
translators. The result is a file containing a linkable module.

Loadable Modules
A dynamically loadable module created by BND 286 is an executable module created by the combination of one or more
linkable modules. Loadable modules can be of two types:
1. Single-task loadable (STL)

2. Variable-task loadable (VTL)

,r-------,,
I

SOURCE
FILES

r-------,

I
I

,
L
_______ JI

OBJECT
('".OBJ'")

r-------~

LOADABLE
(EXECUTABLE)
[I~==~l--lJo~1
OBJECT
~
MODULE
WITH NOLOAD

-i TRANSLATOR r--I

'WITH LOAD

f--J--:: BND286
L________ J

1 OPERATING

SYSTEM
LOADER

:
I

L______ J

r-------.,

,
--!:

SIM286

I ________ J:
L

LINKED
OBJECT
MODULE
'"LINK'"

LIBRARY
FILE

r---

LEGEND:
-INPUT AND OUTPUT OF
SOFTWARE PRODUCTS

'---_II

I.--,

LIB286

I...- - - - l
I
I

PRINTED
MAPS

L ______ .J

m-0804

----- SOFTWARE PRODUCTS

Figure 5. BND 286 Application Program Development

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AP-405

STLModules
These modules are functionally similar to LTL-format records in the 8086 OMF. STL modules are designed to optimize
loader execution time because each contains only one executable task. iRMX 286 and XENIX 286 operating systems will
execute only files containing STL modules. BND 286 outputs STL modules when the FASTLOAD, RCONFIGURE, and
XCONFIGURE controls are specified. In iRMX 286 only, the RCONFIGURE control is used.

VTLModules
VTL modules are designed, when provided by BND 286, to also contain a single executable task, but in a format
structured for multiple tasks. BND 286 outputs VTL modules when the LOAD control is specified.

iRMX" 286 USAGE

r---·-1

•

:,BN0286 ~

CONSOLE
MESSAGES

7-80

_.1

IPiiiNTl

CONSOLE
MESSAGES

m'()805

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AP·405

BND 286 TO LINK 86 COMPARISON

BND 286 CONTROLS

LINK 86 CONTROLS

CONTROLFILE (pathname)

DEBUG/NODEBUG

SYMBOLS/NOSYMBOLS

ERROR PRINT (pathname)1
NOERRORPRINT

FASTLOAD/NOFASTLOAD

• LDTSIZE ([ + I number)

LOAD/NOLOAD

NAME (modulename)

OBJECT (pathname)1
NOOBJECT

PACKINOPACK

PRINT (pathname)1
NOPRINT

PUBLICS/NOPUBLICS

PUBLICS/NOPUBLICS/PUBLICSONLY

RCONFIGURE (dm,m)

BIND and MEMPOOL

RENAMESEG (old to new)

RESERVE (number)

SEGSIZE (name(size»

*TASKPRIVILEGE ( )

TYPE/NOTYPE

TYPEINOTYPE

*XCdNFIGURE

"Not used in iRMX 286

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The following is an example of BND 286 for a simple human interface Commonly Used System Program (CUSP) used on
an iRMX 286 Release 1.0 system.
BND286

EXAMPLE.OBJ,

EXAMPLE.L1B,

iRM~

IRMX286/L1B/UPIFC.L1B,

286 Libraries-

IRMX286/L1B/UDI.GAT,

iRMX 286 Library Privilege
& ----~
Gates

IRMX286/L1B/HPIFC.L1B,

IRMX286/LIB/HI.GAT,

IRMX286/L1B/LPIFC.L1B,

IRMX286/LIB/LOA.GAT,

IRMX286/L1B/EPIFC.L1B,

IRMX286/L1B/EIO.GAT,

IRMX286/L1BIIPIFC.L1B,

IRMX286/L1BIIOS.GAT,

IRMX286/L1B/NUCIFC.L1B,

IRMX286/L1B/NUC.GAT

RCONFIGURE (DM(10000H, 10000H»
(Analogous to BIND&MEMPOOL)
SEGSIZE (STACK(1024»
(Analogous to segsize)
OBJECT (EXAMPLE)
(A new control)
The following is an example of BND 286 for a simple human interface Commonly Used System Program (CUSP) on an
iRMX 286 Release 2.0 system. Notice all of the .GAT files and many of the .Lffi files are gone. All of these "missing"
files are now contained in the files RMXIFC.Lm and UDIIFC.Lffi for convenience.
BND286

EXAMPLE.OBJ,

EXAMPLE. LIB,

IRMX286/L1B/UDIIFC.L1B,

IRMX286/L1B/RMXIFC.LIB,

RCONFIGURE (DM(10000H,10000H»
(Analogous to BIND & MEMPOOL)
SEGSIZE (STACK(1024»
(Analogous to SEGSIZE)
OBJECT (EXAMPLE)
(A new control)

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AP·405
iRMX(R) XXX.BLD File
system_bid;
segment
nucdat.code(dpl = 0),
nucdat.data(dpl = 0),
memory
(reserve = (0 .. 0001 FFFH,
003AOOOH .. 0FFFFFFh»;

gate
Gate_CreateJob (entry =
RqCreateJob, dpl 0, wc

table

=0),

Idt1 (limit =00600h,dpl =0,
reserve = (2 .. 2, 4 .. 4AH,
4CH ..4EH, 51 H .. 59h,
122H .. 005FFh),
entry = ( O:nucdat.escape_ss,
3:nucdat.stack,
75:nucdat.jobdat,
79:nucdat.escape_ss,
80:nucdat.entry_code) );

task
rmxtask (dpl
Idt

=O,object = nucdat,
= Idt1, no ie);

table
gdt (limit = 00600H, dpl = 0,
reserve
(3 .. 3BH, 3DH .. 4EH,
51 H .. 53H, 55H .. 59H, OC1 H .. OC7H,
OE3H ..OE5H,OEAH .. OEFH,
101 H .. 103H, 00137h .. 00140h),
entry
(60:nucdat.data,
79:rmxtask,
80:nucdat.code,
84:ldt1,
90:Gate-AcceptControl,
91 :Gate-AlterComposite,

308:sdbcnf .code,
309:sdbcnf .data,
310:sdbcnf.newstack,
291 :bios_code,
292:bios_data,

table

idt(limit =00080h, dpl =0);

end

7-83
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inter

AP-405

DEVELOPMENT TOOLS - BLD 286
BLD 286 exceeds LOC 86 in capability and versatility. In many cases the use of BLD 286 is transparent to iRMX 286
users, due to the ICU 286 automatically generating the BUILD file. All iRMX 286 users, however, should possess an
understanding of the following key functions:
,A. Assigns physical addresses to entities, sets segment limits and access rights. (See XXX.BLD file)
B. Allows memory ranges to be reserved or allocated for specific entities. (See XXX.BLD file)

C. Creates one Global Descriptor Thble (GDT), one Interrupt Descriptor Thble (lOT), and one Local Descriptor
Thble (LDT). (See XXX.BLD file)
D. Creates gates. (See XXX.BLD file)
E. Creates task state segments and (task gates). (See XXX.BLD file)

Creates a bootloadable module. (See XXX.BLD file)

G. Creates object files containing exported system entries. (See XXX.BLD file)
H. Selects required modules from specified libraries automatically, as needed to resolve symbolic references.
I.

Performs reference-resolution and typechecking.

Detects and reports errors and warnings found during processing (in the XXX.MP2 file)

See Figure 6 for an example of BLD 286 program development.

Usage
BLD 286 is primarily used for building an application program that deals extensively with system interfaces to a hardware
environment. This could include configuring gates and/or segments that provide this interface, then place these interfaces
in a separate file for later exportation.
The types of executable output produced by BLD 286 are bootloadable, loadable, or incremental-built. Bootloadable
modules are absolutely-located object modules that are booted via a simple loader. Loadable modules consist of single- or
multiple-task modules used for dynamic loading. Incrementally-built modules are non-executable modules used interactively to build large systems.
Many users will only use BLD 286 when they produce a new configuration using the ICU. ICU 286 generates a file called
ICUBLD. CSD which invokes the builder using the file XXX.BLD as the builder definition me.
The following is a typical example of the contents of ICUBLD.CSD:

BLD286,

NUCLUS.LNK,

SDB.LNK,

IOS.LNK,

EIOS.LNK,

LOADER.LNK,

HI.LNK,

UDI.LNK

OBJECT (/BOOTI* * * .286)

& ( Where to put the
bootloadable file)

NODEBUG NOTYPE

(Produced by BND 286).-.1

BUILDFILE (* * * .BLD)

( Where to obtain the
build information)
7-84

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LIBRARIES

r--------,

80286

lTRANSLATORS~

'-________.J

TRANSLATED
OBJECT
MODULE(S)

t~I

BINDER
LINKABLE
MODULE(S)

BUILD
FILE

BUILDER
EXPORT
MODULE(S)

r-:::I
t-

80286
SYSTEM
BUILDER

J
t---

I---

INCREMENTALLY
BUILD
SYSTEM
IMAGE

BOOTLOADABLE
MODULE

LOADABLE
MODULE

1--

'CJ

• NOT USED BY iRMX'" 28 6
m-0801

Figure 6. BLD 286 Application Program Development
The build file contains a specific language used by BLD 286 to produce the system or system program_ BLD 286 takes all
linked input modules and assigns all of the access and protection attributes for each subsystem. A build file is created to
specify the characteristics of the relationships among the subsystems. Segment attributes, gates, descriptor tables, aliases,
and memory allocation are also described in the build file and read by BLD 286.

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..------l------1WITHNOBOOTLOAD LOADABLE
,-I
• (EXECUTABLEjl-_ _ _ _---,
r - - BLD286 I
OBJECT
r-""
WITH
MODULE
••• -BOOTLOAD

Lil,i -------1
EXAMPLE
LOADER

I
I

;

80286

r------,
Ii
i
'------• ..1

BOOTLOADER

SOURCE
FILES

r----'--.... ~------ ...
BO~~~~~BLE r--

OBJECT
MODULE
("_OBJ")

....

MODULE

LOADABLE
(EXECUTABLEj
OBJECT
MODULE

r------"\
I

OPERATING:

~ SYSTEM

.. _----....I
: LOADER

.------,

l.]
I

SIM286 I

.. _-----....

LINKED
OBJECT
MODULE
"LINK"

. --1---.

MAP286

I
I

L--r_J

'--_ _+-1_ _ : LIB286

r-------,

U,
' -_ _ _~'

PRINTED
MAPS

'-.- ......
LEGEND:
INPUT AND OUTPUT OF SOFTWARE PRODUCTS
-----SOFTWARE PRODUCTS

m-0806

Figure 7.

7-86
2B0608-001

AP-405

MAP 286
The 80286 mapper is a noninteractive utility that generates object module information that BND 286 and BLD 286 do not
produce. The utility is offered separately instead of having the builder and rinder performing identical functions. The user
should note that if debug information is contained in the invocation file, all of the maps will be produced.
MAP 286 will accept the following input:
A. Executable files containing a single executable module, and only one per invocation of MAP 286.
B.

Executable files containing a single bootloadable module.

C. One or more linkable or library files.
MAP 286 produces the following output maps:
For executable input files:
A. An output object file with or without debug information.
B. Table MAp, segment MAP, gate MAP, public MAP, symbol MAP, task MAP, and crossreference MAP.
For linkable input files:
A. Only a cross reference map including a module list.
In iRMX 286 the following is a typical invocation of the mapper on an executable file called
MAP

286

MYPROG

If debug information is in "MYPROG" all of the maps will be produced.

iRMX® 86 OPERATING SYSTEM PROGRAM MIGRATION
Compiling in PL/M 286
The following is an example of converting an iRMX 86 Commonly Used System Program (CUSP) called NGrE. To assist
readers, all of the conversion steps will be described.

Source Program
The program NGrE is written in PLIM 86 for use on iRMX 86 operating system. When invoked, the utility will echo a
line of keybo~rd input to the console.
The source code file name for NGrE is NGrE.P86. To adhere to PLIM 286 and iRMX 286 operating system file naming
conventions, the file should be renamed to NGrE.P28. Next, the file has to be changed to reflect changes in PLIM 286
and iRMX 286 library files. Finally the file is compiled and bound with BND 286. See the following examples for further
explanation.
STEP 1
Copy NGrE.P86 to NGrE.P28

< CR>

STEP 2
The NGrE.P28 file has to be edited to change
A. All '0' pointers to 'NIL'
B. All '0' selectors to 'SELECIDRS$OF(NIL),
Also notice all of the include files assume an iRMX 86 operating system and have to be changed to iRMX 286 libraries.
STEP 3
The new NGrE.P28 program is compiled and any errors are corrected.
7-87
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$title('iRMX 86 HI NOTE command')
$subtitle('module header')

1*****************************************************
******************
TITLE: note
ABSTRACT:
This module contains the main routine for the HI note command.
NOTE

message

Message will be printed on EO.

***********************************************************************1

hnote: DO;

$include(:sd:inc/hstand.lit)
$include(:sd:rmx86/inc/hgtchr.ext)
$include(:sd:rmx86/inc/hsneor.ext)
$include(:sd:inc/hutil.ext)
DECLARE
version(*) BYTE DATA ( 'program_version_number=F001',
'program_name=Note' ,0);
1
2
3
4
5

main: DO;
1* local variables
DECLARE
excep
WORD,
BYTE,
char
WORD,
count

6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

msg

STRUCTURE (
length
BYTE,
char(STRING$MAX) BYTE) ;

count = 0;
char = rq$C$get$char( @excep);
DO WHILE( (char := rq$C$get$char( @excep» <> 0);
IF count < LAST(msg.char) THEN
DO;
msg.char(count) = char;
count = count + 1;
END;
END;
msg.char(count) = cr;
count = count + 1;
THIS POINTER
msg. char ( count) = If;
NEEDS CHANGING.
count
count + 1;
msg.length = count;
CALL rq$C$send$EO$response( 0, 0, @msg, @excep);

1*
24
25

exit from command

CALL cusp$error ( excep, @(O), @( 0), ABORT);
END main;

END hnote;

PlM 86 Example

7-88

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AP·405

$title('iRMX 286 HI NOTE command')
$subtitle('module header')

/***********************************************************************
TITLE: note
ABSTRACT:
This module contains the main routine for the HI note command.
NOTE

message

Message will be printed on EO.

****************************************************** *****************1
hnote: DO;
$include(:sd:inc/hstand.lit)
$include(:sd:rmx86/inc/hgtchr.ext)
$include(:sd:rmx86/inc/hsneor.ext)
$include(:sd:inc/hutil.ext)
DECLARE
version(*) BYTE DATA( 'program_version_number=F001',
'program_name=Note' ,0);
1
2
3
4
5
6
7

8
9

10
11

12
13

14
15

16
17
18
19

20
21
22
23

main: DO;
/* local variables
DECLARE
excep
WORD,
char
BYTE,
WORD,
count
msg

STRUCTURE (
length
BYTE,
char(STRING$MAX) BYTE) ;

count = 0;
char = rq$C$get$char( @excep);
DO WHILE( (char := rq$C$get$char( @excep» <> 0);
IF count < LAST(msg.char) THEN
DO;
msg.char(count) = char;
count = count + 1;
END;
END;
msg.char(count) - cr;
count = count + 1;
THIS IS
msg.char(count) = If;
OK NOW.
count = count + 1;
msg.length = count;
CALL rq$C$send$EO$response( NIL, 0, @msg, @excep);

/l---,- -

/* exit from command */
24
25

CALL cusp$error( excep, @(O), @(O), ABORT);
END main;

END hnote;

PLM 286 Version Example

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Binding an iRMX® 286 Application
STEP 1

If a program was previously linked in iRMX 86, we then examine the original
LINK file used and notice the following:
PLM86 %O.P86 COMPACT ROM OPTIMIZE(3) NOTYPE PW(132)

LINK86
%O.obj,
/rmx86/hi/hutil.lib,
&
/lib/plrn86/plrn86.1ib,
&
/rrnx86/1ib/hpifc.lib,
&
/rrnx86/1ib/epifc.lib, &
/rmx86/1ib/ipifc.lib. &
/rrnx86/1ib/rpifc.lib &
to %.86
bind rnernpool(10000,OBOOOOH)
nosb noty

1. The library names will change
2. The pathnames to access the libraries will change
3. BIND and MEMPOOL will change
STEP 2

The following is the iRMX 286 Release 1.0 version of the file in Step 4.
Remember the libraries have changed names between iRMX 286 Release 1.0 and 2.0.
PLM286 %O.p28 COMPACT ROM OPTIMIZE(3) NO TYPE PW( 132)

bnd286

%O.obj,
&
/rrnx286/1ib/hutil.lib,
&
/rrnx286/1ib/plrn286.1ib,
&
/rrnx286/1ib/hpifc.lib, /rrnx286/1ib/hi.gat,
&
/rrnx286/1ib/epifc.lib. /rrnx286/1ib/eio.gat, &
/rmx286/1ib/ipifc.lib. /rmx286/1ib/ios.gat, &
/rrnx286/1ib/nucifc.lib, /rrnx286/1ib/nuc.gat &
renameseg(hi_code to code, hi_data to data) segsize (stack(lOOOH»
object(%O) rc(drn(12000, 1000000»
node bug noty

STEP 3

This is an example of the Step 4 file modified to run on iRMX 286 Release
2.0. Notice the reduction of library statements.
PLM286 %O.p28 COMPACT ROM OPTIMIZE(3) NOTYPE PW( 132)
bnd286

%O.obj,
&
/RMX286/hi/hutil.lib,
&
/RMX286/1ib/plrn286/plrn286.1ib, &
/ltMX2B6/lib/rmxifc.lib
&
renarneseg(hi_code to code, hi_data to data) segsize (stack(lOOOH»
object(%O) rc(dm(12000,lOOOOOO»
nodebug noty

Though these few migration examples reflect trivial modifications, larger
and more complex applications might require a little more attention. '

7-90

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AP-405
SUMMARY
The purpose of this application note is to provide insight and direction to those individuals contemplating using the iRMX
286 operating system. For those already familiar with the iRMX 86 operating system, this paper's focus is to provide the
pathway to a superior product.
The iRMX 286 operating system is a vast improvement over its previous counterpart. Some notable changes are round
robin scheduling, hardware-enforced protection, hardware-assisted debugging, and access to the 80386 processor. With
this operating system the capabilities of the 80286 processor can be fully utilized for multiple environments.
Since the iRMX product line was introduced, many applications, programs, and lines of code have been written to support
a tangible demand for real-time processing; in manufacturing, in medicine, and in finance, to name a few. As a result
more time is being spent on designing, writing, and testing software than ever before. The iRMX 286 operating system is
the preferred product for generating error-free programs while utilizing the highest CPU technology available in the OEM
modules market.

7-91

280608-001

AEDIT SOURCE CODE AND TEXT EDITOR

PROGRAMMER SUPPORT
AEDIT is a full-screen text editing system designed specifically for software engineers and
technical writers. With the facilities for automatic program block indentation, HEX display
and input, and full macro support, AEDIT is an essential tool for any programming
environment. And with AEDn: the output file is the pure ASCII text (or HEX code) you
input-no special characters or proprietary formats.
Dual file editing means you can create source code and its supporting documents at the
same time. Keep your program listing with its errors in the background for easy reference
while correcting the source in the foreground. Using the split-screen windowing capability,
it is easy to compare two files, or copy text from one to the other. The DOS system-escape
command eliminates the need to leave the editor to compile a program, get a directory
listing, or execute any other program executable at the DOS system level.
There are no limits placed on the size of the file or the length of the lines processed with
AEDIT. It even has a batch mode for those times when you need to make automatic string
substitutions or insertions in a number of separate text files.

AEDIT FEATURES
• Complete range of editing supportfrom document processing to HEX
code entry and modification
• Supports system escape for quick
execution of PC-DOS System level
commands
• Full macro support for complex or
repetitive editing tasks

• Hosted on PC-DOS [lnd RMX operating
systems
• Dual file support with optional splitscreen windowing
• No limit to file size or line length
• Quick response with an easy to use
menu driven interface
• Configurable and extensible for
complete control of the editing process

i n t : e l ' - - 7-92
-------C1lntel CorporatIon 1989

September, 1989
Order Number 280804·002

FEATURES
POWERFUL TEXT EDITOR

MACRO SUPPORT

As a text editor, AEDIT is versatile and complete. In
addition to simple character insertion and cursor
positioning commands, AEDIT supports a number of
text block processing commands. USing these
commands you can easily move, copy, or delete both
small and large blocks of text. AEDIT also provides
facilities for forward or reverse string searches, string
replacement and query replace.

AEDIT will create macros by simply keeping track of
the command and text that you type, "learning" the
function the macro is to perform. The editor
remembers your actions for later execution, or you
may store them in a file to use in a later editing
session.
Alternatively, you can design a macro using AEDIT's
powerful macro language. Included With the editor is
an extensive library of useful macros which you may
use or modify to meet your individual editing needs.

AEDIT removes the restriction of only inserting
characters when adding or modifying text. When
adding text with AEDIT you may choose to either
insert characters at the current cursor location, or
over-write the existing text as you type. This flexibility
simplifies the creation and editing of tables and
charts.

TEXT PROCESSING
For your documentation needs, paragraph filling or
justification simplifies the chore of document
formatting. Automatic carriage return insertion means
you can focus on the content of what you are typing
instead of how close you are to the edge of the
screen.

USER INTERFACE
The menu-driven interface AEDIT provides makes it
unnecessary to memorize long lists of commands
and their syntax. Instead, a complete list of the
commands or options available at any point is always
displayed at the bottom of .the screen. This makes
AEDIT both easy to learn and easy to use.

SERVICE, SUPPORT, AND TRAINING

FULL FLEXIBILITY
In addition to the standard PC terminal support
provided with AEDIT, you are able to configure AEDIT
to work with almost any terminal. This along with userdefinable macros and full adjustable tabs, margins,
and case sensitivity combine to make AEDIT one of
the most flexible editors available today.

Intel augments its development tools With a full array
of seminars, classes, and workshops; on-site
consulting services; field application engineering
expertise; telephone hot-line support; and software
and hardware maintenance contracts. This full line of
services will ensure your design success.

SPECIFICATIONS
HOST SYSTEM
AEDIT for PC-DOS has been designed to run on the
IBM' PC XT, IBM PC AT, and compatibles. It has
been tested and evaluated for the PC-DOS 3.0 or
greater operating system.

Versions of AEDIT are available for the iRMXTM-86 and
RMX II Operating System.

ORDERING INFORMATION
D86EDINL

AEDIT Source Code Editor Release
2.2 for PC-DOS with supporting
documentation

122716

AEDIT-DOS Users Guide

122721

AEDIT-DOS Pocket Reference

RMX864WSU

AEDIT for iRMX-86 Operating
System

R286EDI286EU AEDIT for iRMX II Operating System

7-93

iPATTM PERFORMANCE ANALYSIS TOOL

REAL-TIME SOFTWARE ANALYSIS FOR THE 8086188, 801861188,
80286, AND 80386
Intel's iPAT'" Performance Analysis Tool enables OEMs developing applications based on
the 8086/88, 80186/188, 80286, or 80386 microprocessors to analyze real-time software
execution in their prototype systems at speeds up to 20 MHz. Through such analysis, it is
possible to speed-tune applications with real-time data, optimize use of operating systems
(such as Intel's iRMX® II Real-Time Multitasking Executive for the 80286 and 80386, and
iRMKTM Real-Time Multitasking Kernel for the 80386), characterize response characteristics,
and determine code execution coverage by real-time test suites. Analysis is performed
symbolically, non-intrusively, and in real-time with 100% sampling in the microprocessor
prototype environment. iPAT supports analysis of OEM-developed software built using
8086,80286, and 80386 assemblers and compilers supplied by Intel and other vendors.
All iPAT Performance Analysis Tool products are serially linked to DOS computer systems
(such as IBM> PC AT, PC XT, and PS/2> Model 80) to host iPATcontrol and graphic display
software. Several means of access to the user's prototype microprocessor system are
supported. For the 80286 (real and protected mode), a 12.5 MHz iPAT-286 probe can be
used with the iPATCORE system. For the 8086/88 (MAX MODE designs only), a 10 MHz
iPAT-88 probe can be used with the iPATCORE system. iPATCORE systems also can be
connected to sockets provided on the ICE'"-286 and ICE-186 in-circuit emulators, or
interfaced to liCE in-circuit emulators with probes supporting the 8086/88, 80186/188, or
80286. The 20 MHz iPAT'"-386™ probe, also supported by the common iPATCORE system,
can be operated either in "piggyback" fashion connected to an Intel ICE in-circuit emulator
for the Inte1386'", or directly connected to a prototype system independent of an ICE.
iPAT-386 supports all models of 80386 applications anywhere in the lowest 16 Megabytes of
the 80386 linear address space.

IPAT FEATURES
• Up to 20 MHz real-time analysis
• Histograms and analysis tables
• Performance profiles of up to 125
partitions

• Code execution coverage over up to
252K
• Hardware or software interrupt analysis
• Simple use with function keys and
graphics
• Use with or without IntellCEs

intel·---------C1lntel Corporabon 1989

7-94

September, 1989
Order Number 280786·002

FEATURES
MOST COMPLETE REAL-TIME ANALYSIS
AVAILABLE TODAY

FROM ROM-LOADED TO OPERATING
SYSTEM LOADED APPLICATIONS

iPAT Performance Analysis Tools use in-circuit probes
containing proprietary chip technology to achieve full
sampling in real-time non-intrusively.

The software analysis provided by iPAT watches
absolute execution addresses in-circuit in real time,
but also supports use of various iPAT utilities to
determine the load locations for load-time located
software, such as applications running under iRMXII,
DOS, Microsoft Windows', or MS"OS/2.

MEETS THE REAL-TIME DESIGNER'S
NEEDS
The iPAT products include support for interactions
between real-time software and hardware interrupts,
real-time operating systems, "idle time," and full
analysis of real-time process control systems.

SPEED-TUNING YOUR SOFTWARE
By examining iPAT histogram and tabular information
about procedure usage (including or not Including
their interaction with other procedures, hardware,
operating systems, or interrupt service routines) for
critical functions, the software engineer can quickly
pinpoint trouble spots. Armed with this Information,
bottlenecks can be eliminated by means such as
changes to algorithms, recoding in assembler, or
adjusting system interrupt priorities. Finally, iPAT can
be used to prove the acceptibility of the developer's
results.

EFFICIENCY-AND EFFECTIVENESS IN
TESTING
With iPAT code execution coverage Information,
product evaluation With test sUites can be performed
more effectively and in less time. The evaluation team
can quickly pinpoint areas of code that are executed
or not executed under real-time conditions. By this
means, the evaluation team can substantially remove
the "black box" aspect of testing and assure 100%
hits on the software under test. Coverage information
can be used to document testing at the module,
procedure, and line level. iPAT utilities also support
generation of instruction-level code coverage
information.

ANALYSIS WITH OR WITHOUT
SYMBOLICS

USE STANDALONE OR WITH ICE
The iPAT-386, iPAT-286, and iPAT-86/88 probes,
together with an iPATCORE system, provide
standalone software analysis independent of an ICE
(in-circuit emulator) system. The iPATCORE system
and DOS-hosted software also can be used together
with ICE-386, ICE-286, and 12ICE-86/88, 186/188, or
2$6 in-circuit emulators and DOS-hosted software.
Under the latter scenario, the user can examine
prototype software characteristics in real-time on one
DOS host while another DOS host is used to supply
input or test conditions to the protype through an
ICE. It also is possible to use an iPATCORE and 121CE
system with Integrated host software on a single Intel
Series III or Series IV development system or on a
DOS computer.

UTILITIES FOR YOUR NEEDS
Various utilities supplied with iPAT products support
generation of symbolic information from map files
associated with 3rd-party software tools, extended
analysis of iPAT code execution coverage analysis
data, and convenience in the working environment.
For example, symbolics can be generated for maps
produced by most software tools, instruction-level
code execution information can be produced, and
IRMXII-format disks can be read/written in DOS
floppy drives to facilitate file transfer.

WORLDWIDE SERVICE AND SUPPORT
All iPAT Performance Analysis Tool products are
supported by Intel's worldwide service and support.
Total hardware and software support is available,
including a hotline number when the need is there.

If your application is developed with "debug"
symbolics generated by Intel 8086, 80286, or 80386
assemblers and compilers, iPAT can use themautomatically. Symbolic names also can be defined
within the iPAT environment, or conversion tools
supplied With the IPAT products can be used to
create symbolic information from virtually any
vendor's map files for 8086, 80286, and 80836
software tools.

REAL OR PROTECTED MODE
iPAT supports 80286 and 80386 protected mode
symbolic information generated by Intel 80286 and
80386 software tools. It can work with absolute
addresses, as well as base-offset or selector-offset
references to partitions in the prototype system's
execution address space.

7-95

FEATURES
CONFIGURATION GUIDE
For all of the following application requirements, the iPAT system is supported with iPAT 2.0 (or greater) or
iPAT/liCE 1.2 (or greater) host software, as footnoted.
Application Software
80386 Embedded
iRMK on 80386
iRMXII OS-Loaded or Embedded on
386
OS/2-Loaded on 386
iRMXII OS-Loaded or Embedded
80286 Embedded

DOS OS-Loaded 80286
OS/2 OS-Loaded 80286
80186/188 Embedded

DOS OS-Loaded 8086188
8086/88 Embedded

Option
#1
#1
#1
#1
#1
#1
#2
#3
#4
#5
#6
#1
#1
#1
#2
#3
#4
#5
#1
#1
#2
#3
#4
#5

iPAT Order Codes
iPAT386DOS1, iPATCORE
iPAT386DOS, iPATCORE
iPAT386DOS, iPAT~ORE
iPAT386DOS, iPATCORE
iPAT286DOS, iPATCORE
iPAT286DOS, iPATCORE
ICEPATKIT2
IICEPATKIT3
IIIPATD, iPATCORE3
IIiPATB, iPATCORE3
IIiPATC, IPATCORE3
iPAT286DOS, iPATCORE
iPAT286DOS, iPATCORE
ICEPATKIT2
IICEPATKIT3
IIIPATD, iPATCORE3
IIiPATB, iPATCORE3
IIiPATC, iPATCORE3
iPAT88DOS, iPATCORE
iPAT88DOS, iPATCORE
IICEPATKIT3
III PATD , iPATCORE3
IIIPATB, iPATCORE3
IIIPATC, iPATCORE3

Host System
DOS
DOS
DOS
DOS
DOS
DOS
DOS
DOS
DOS4
Series 1114
Series IV4
DOS
DOS
DOS
DOS,
DOS4
Series 1114
Series IV4
DOS
DOS
DOS
DOS4
Series 1114
Series IV4

Notes:
1. Operable standalone or with ICE-386 (separate product; separate host). iPAT-386 probe connects directly to
prototype system socket, or to optional 4 probe-to-socket hinge cable (order code TA386A), or to ICE-386
probe socket.
2. Requires ICE-186 or ICE-286 in-circuit emulator system.
3. Requires liCE in-circUit emulator system.
4. Includes iPAT/llCE integrated software (iPATIiCE 1.2 or greater), which only supports sequential iPAT and
ICE operation on one host, rather than in parallel on two hosts (iPAT 2.0 or greater).

7-96

SPECIFICATIONS
HOST COMPUTER REQUIREMENTS

ELECTRICAL CONSIDERATIONS

All iPAT Performance Analysis Tool products are
hosted on IBM PC AT. PC XT. or PS/2 Model 80
personal computers, or 100% compatibles, and use a
serial link for host-to-iPAT communications. At least a
PC AT class system is recommended. The DOS host
system must meet the following minimum
requirements:
• 640K Bytes of Memory
• 360K Byte or 1.2M Byte floppy disk drive
• Fixed disk drive
• A serial port (COM1 or COM2) supporting 9600
baud data transfer
• DOS 3.0 or later
• IBM or 100% compatible BIOS

The iPATCORE system power supply uses an AC
power source at 100V, 120V, 220V, or 240V over 47Hz
to 63Hz. 2 amps (AG) at 100V or 120V; 1 amp at 220V
or 240V.

PHYSICAL DESCRIPTIONS
Unit
,PATCORE
Power Supply
,PAT-386 probe
,PAT-286 probe
'PAT-86 probe
,PATCABlE (to
ICE-186/286)
IIIPATB,C,D
(liCE board)
Serial cables PC
AT/XT PS/2

Width
Inches Cm.
8.25 21.0
775 20.0
3.0
7.6
4.0 10.2
40 102
4.0

10.2

12.0 30.5

Height
Inches Cm.

length
Inches Cm.

1.75
4.25
0.50
1.12
112

4.5
11.0
1.3
2.8
2.8

36.0

91.4

12.0 30.5

1.3

iPAT-386, iPAT-286 and iPAT-86/88 probes are
externally powered, impose no power demands on
the user's prototype, and can thus be used to analyze
software activity through power down and power up
of a prototype system. For ICE-386, ICE-286,
ICE-186, and liCE microprocessor probes, see the
appropriate in-circuit emulator factsheets.

ENVIRONMENTAL SPECIFICATIONS
Operating Temperature: 10°C to 40°C (50°F to
104°F) ambient
Operating Humidity:
Maximum of 85% relative
humidity, non-condensing

13.75 35.0
11.0 28.0
4.0 10.1
6.0 15.3
6.0 153

144.0370.0

7-97

IRMX SOURCE CONTROL SYSTEM

iRMX® SOURCE CONTROL SYSTEM
The iRMX Source Control System (SCS) provides an integrated version control and
generation management system for users in an iRMX software development cycle. This
facility is useful for large and small software projects to assist in bringing more control,
order and methodology to the software development process. SCS can be effectively
used on a single iRMX System or across the OpenNE'P" network.

FEATURES
• Controls access to source files
• Tracks changes to source files
• Approachable and efficient

in~·
Cl

• Generates any version of project
• Supports range of iRMX language.s

______________________
Intel Corporation 1989

7-98

September, 1989
Order Number 280739-001

CONTROLS ACCESS TO SOURCE FILES
With IRMX Source Control System the system
manager (project leader) has certain privileged
commands. These commands can be useful to
designate those team members who can access
the source flies only for object generation and
those who can access the source files for updating
or changing. Other such privileged commands
include the ability to archive a specific version of
source and combine several versions of a source
file.

TRACKS CHANGES TO SOURCE FILES
The iRMX Source Control System keeps track of
changes made to any source files. These changes
are stored as backward deltas for disk economy
and fast access to the latest version. The project
team can now better interact and synchronize
using the latest updated version for integration and
testing, especially as projects grow increasingly
complex. The specific versions of tools used to
produce the source code IS also tracked.

APPROACHABLE AND EFFICIENT
The iRMX Source Control System has several
facilities that help make it very approachable by
the user. The tutorial leads the first time SCS user
through the structure and capabilities of the IRMX
Source Control System. The menu Interface helps
even the experienced SCS user learn and take
advantage of the powerful capabilities of SCS. An
on-line help faCility assists in quick reminders for
using the referenced commands.

The iRMX Source Control System makes efficient
use of the system storage area and the
development engineer's time.
The iRMX Source Control System can be used on
a single iRMX System or can be utilized by a
networked/distributed development team.

GENERATES ANY VERSION OF
PROJECT
The iRMX Source Control System can be of
particular use to both new active development
projects as well as the evolving enhancement and
maintenance of previous product releases. SCS
provides for generation of any version of a project
so that users can support (or test) different
releases of a project from one source data base.
Versions can be tagged for retrieval with symbolic
names, state attributes or programmer name.
Parallel development paths can be more easily and
automatically merged using SCS.

SUPPORTS RANGE OF iRMX
LANGUAGES
The iRMX Source COIitrol System can be utilized
by developers using any of the popular iRMX
languages-PLlM, Assembler, FORTRAN, 'C,'
PASCAL. The user can also configure support
other special language requirements.

SPECIFICATIONS
PREREQUISITE HARDWARE

ORDERING INFORMATION

iRMX System 320 with at least 2MB, random access
memory, 140MB winchester disk, and tape drive.

For more information or the number of your nearest
sales office call 800-548-4725 (good in the U.S. and
Canada).

PREREQUISITE SOFTWARE
iRMX 286 R2.0 and AEDIT for single node system
access. The above software prerequisite and
iRMXNET R2.0 are required for networked utilization.

ORDER CODE
RMXSCSSU

7-99

iRMX® TOOLBOX

IRMX"
SYSTEM
320

TERMINAL

The iRMX toolbox is a set of utilities to provide assistance to the software developer in the
housekeeping aspects of program development. These utilities offer facilities for text
processing and document preparation.
Sort facilities and a desk calculator are also included.

FEATURES:
•
•
•
•
•
•

Text formatting
Spelling verification
File comparisons
Sort
.
Floating point desk calculator
Pocket reference guide

imJ-------------------(lIntel Corporatlon 1989

7-100

September, 1989
Order Number 280737·001

FEATURES
TEXT FORMATTING (SCRIPT)

SORT (ESORT, HSORT)

The SCRIPT utility is a text formatting program that
streamlines document formatting and preparation.
Commands include facilities to do paging, centering,
left and right margins, justification, subscripts,
superscripts, page headers and footers, underlines,
boldface type, upper and lower case, etc.

Files can be sorted on multiple keys (or fields) in
ascending or descending order and the resultant
sorted files stored.

Input text which has been prepared using the AEDIT
utility can be formatted using the SCRIPT utility and
the output directed to a printer or stored on disk for
future manipulation. A short tutorial example IS
provided to help the first time user of this formatter.

SPELLING VERIFICATION
(SPELL, WSORT)
The SPELL utility finds misspelled words in a text file.
The included dictionary can be expanded by the user
for any additions as well as specialized vocabularies.
This utility can be used interactively or in a batch
mode. Another utility (WSORT) then can be used to
sort and compress the user created dictionary.

Another utility can be invoked to sort records or data
in ASCII lexical order.

FLOATING POINT DESK
CALCULATOR (DC)
The DC utility accepts lines of text as input. Each line
containing an expression is parsed, evaluated and
the result displayed on the console. Expressions can
contain embedded assignment statements and single
letter variables.

POCKET REFERENCE GUIDE
In addition to the User's Guide provided with iRMX
Toolbox, a reference guide in small pocket format
provides a handy reference to commands and
functions.

FILE COMPARISONS (COMP)
The COMP utility performs line oriented text file
comparisons showing changes between text or
source files. This utility can also compare object files.

SPECIFICATIONS
OPERATING ENVIRONMENT
iRMX 286 Operating System Release 2.0 or later
running on an Intel Series 300 System or equivalent
hardware with Numeric Data Processor (NDP)
support and at least 1MB of memory. The AEDIT
utility is required for use of the SCRIPT text formatting
program.

DOCUMENTATION
An iRMX 286 Toolbox Users Guide and Pocket
Reference Guide are shipped with the product.

ORDERING INFORMATION
Product Code: RMX286TLB
The product is shipped on a 5V4" iRMX formatted
floppy diskette.

7-101

iRMX® VIRTUAL TERMINAL

iRMX'

"1111 ~ ~YfEM

TERMINAL

;;::e,,*iii(""'k'\(¥W~

TERMINAL

Virtual Terminal is a network service of Intel's iRMX-NET network file access (NFA)
product. Virtual Terminal allows local iRMX users to "Logon" to a remote Intel iRMX node
within an OpenNET network. This capability enables users to access all the available
resources on the remote system. In addition the iRMX Virtual Terminal is fully
interoperable with DOS-NET Virtual Terminal and with the XENIX-NET Virtual Terminal.
Now a. PC or XENIX user can 'connect" to a remote iRMX system without the need to use
a locally connected iRMX terminal.

FEATURES
• User configurable
• Interoperable with Intel's OpenNET VT
products

• Administration utility included

intel"---------C

Intel Corporation 1989

7-102

September. 1989
Order Number 280141-001

USER CONFIGURABLE

ADMINISTRATION UTILITY

The iRMX Virtual Terminal server can be
configured to support from 1 to 32 virtual terminal
connections per system.

The administration utility allows the system
manager to disable, terminate or start the iRMX
Virtual Terminal server. The capability to report on
the status of all the virtual terminal connections to
the local server is also supported.

INTEROPERABILITY WITH OpenNET VT
PRODUCTS
The iRMX Virtual Terminal interoperates with both
the DOS-NET VT and XENIX-NET VT products.
A user on a PC who has the DOS-NET VT product
installed can "Logon" to an iRMX system on the
network.
A user on an iRMX system can "Logon" to a XENIX
system and a user on a XENIX system with the
XENIX-NET VT product can "Logon" to an iRMX
system.

SPECIFICATIONS
SOFTWARE PREREQUISITE

ORDERING INFORMATION

iRMX 286 Release 2.1 or later
iRMX-NET Release 2.1 or later

For more information or the number of your nearest
sales office call 800-548-4725 (good in the U.S. and
Canada).

HARDWARE PREREQUISITE
System 320 with NLAN option
or
System 310 with iSBC 552A

ORDER CODE
RMXNETVTSU

7-103

iRMX® X.2S COMMUNICATIONS SOFTWARE

"PAcKEr

,SWITCHED
,NETWORK

iRMX'
SYSTEM I
320,

\11:
iRMX'SYSTEM 320

iRMX® X.25 COMMUNICATIONS SOFTWARE
The iRMX K25 Communications Software provides routines to connect an iRMX System
320 to a Packet Switch Network (PSN), The iRMX X.25 software allows connections of
similar as well as dissimilar computer types that support the CCITT X.25198011984
recommendation.
The iRMX X.25 software has been designed to allow the programmer the greatest
flexibility in accessing packet-switch networks. In order to achieve this functionality, the
programmer has access to a full-function programmatic interface. The design of iRMX
X.25 allows not only host computer access as a Data Terminal Equipment (DTE) device,
but in addition as a Data Circuit-terminating Equipment (DCE) device. The DCE
configuration makes possible the programming of a complete packet-switch network
service.

SOFTWARE FEATURES
•
•
•
•

i~'

Application interface library
Interactive utility package
Conforms to CCITT X.25 1980
User Selectable X.25 variants

• User Configurable
-Four physical links supported
-Software configurable Baud Rates
-Configurable as DTE/DCE
-255 Configurable Virtual Circuits
(Permanent or Switched)

____________________

Cl Intel CorporatIon 1989

7-104

September, 1989
Order Number 280738-001

APPLICATION INTERFACE LIBRARY
Intel's software provides a three-level application
interface library. Library routines are grouped into
packet transfer services, network services, and
management services. The user can choose the
level of application interface which matches his
X.25 experience. Those new to X.25 may prefer to
start with network services routines, while
proficient users will work directly with the packet
transfer routines.

INTERACTIVE UTILITY PACKAGE
Several utility packages are included with the iRMX
X.25 Communication Software that make it very
approachable by the user. One of these tools is the
User Confidence Test (UCT). The UCT has two
modes of operation: a tutorial mode that
demonstrates the use of the interface routines to
help users quickly learn the calls to X.25; and, an
interpreter mode that provides facilities to confirm
the correct operation of iRMX X.25.
The UCT has been designed to assist users in
testing X.25 applications. In addition to the UCT is
CXTEST and CXPerform. Both of these utilities
allow the user to gain more familiarity with X.25.

The product includes user documentation with
detailed interface procedures, application
examples with source code,' and performance
tools.

USER CONFIGURABLE
A configuration utility is provided to assist users in
selecting the appropriate certification interface (see
list under specification) for their X.25 network.
Once the user has selected their required network
interface and specific parameters, the appropriate
X.25 software routines are downloaded into the
memory of the system's intelligent communication
subsystem. This download capability allows the
user application to run independently of the
communications subsystem.
Under program control user may change the
network configuration parameters. Some of these
parameters are line baud rates (300 baud to 64K
baud), packet size (maximum 1024 bytes
supported) and retransmission limits.
The X.25 Communication Software can also be
configured to support point-to-point interfaces via
a serial link and a pair of modems.

SPECIFICATIONS
NETWORK CERTIFICATIONS
The products and services incorporating versions of
X.25 have undergone extensive network certifications
around the world.
A list of the countries where the software is known to
have been successfully connected to the national
network is given below:

COUNTRY
Finland
France
Germany
Italy
Netherlands
South Africa
Spain
Switzerland
UK
USA
USA
USA

NETWORK
Datapak
Transpac
Datex-P
Itapac
Datanet-1
Saponet
Iberpac
Telepac
PSS
DDN
GTE Telenet
ATT Accunet

APPROVAL
Yes
N/A
#
N/A
#
Yes
N/A
N/A
Yes
Yes
Yes
#

N/A-these PTTs have no formal approval procedure
# - is being certified
Many Packet switching networks are derivatives of
early national implementations of the X.25 (1980)
recommendation. The X.25 product is believed to be
suitable for use on the following networks, based on
these derivations:

COUNTRY
Australia
Belgium
Canada
Denmark
Ireland
Israel
Luxembourg
Norway
Portugal
Singapore

NETWORK
Austpac
DCS
Datapac
Datapak
Eirepac
Isranet
Luxpac
Datapac
Telepac
Telepac

HARDWARE REQUIREMENTS:
System 320 with H4 Communications Option
supports up to four (4) links (2 links full DMA, 2 links
with transmit only DMA)

SOFTWARE PREREQUISITE:
iRMX 286 Release 2.0 or later

ORDER CODE:
System 320 Option HRX25SU (software)

ORDERING INFORMATION
For more information or the number of your nearest
sales office call 800-548-4725 (good in the U.S. and
Canada).

7-105

iSDMTM
SYSTEM DEBUG MONITOR

•
•
•
•

Supports Target System Debugging for
iSBC® 8086, 8088, 80186, 80188, 80286
and 386TM CPU-Based Applications
Provides Interactive Debugging
Commands Including Single-Step Code
Execution and Symbolic Displays of
Results
Supports 8087, 80287, and 80387
Numeric Processor Extensions (NPX)
for High-Speed Math Applications
Allows Building of Custom Commands
Through the Command Extension
Interface (CEI)

•
•
•
•

Supports Application Access to ISIS-II
Files
Provides Program Load Capability from
iSBC 8086, 80286 and 386 CPU-Based
iRMX® I and II Development Systems
and from an Intellec® Development
System
Contains Configuration Facilities which
Allow an Applications Bootstrap from
iRMX® File Compatible Peripherals
Modular to Allow Use from an Intellec®
Development System, from a StandAlone Terminal or from iRMX I or iRMX
II Based Systems

The Intel iSDMTM System Debug Monitor package contains the necessary hardware, software, cables,
EPROMs and documentation required to interface, through a serial or parallel connection, an iSBC 86/05A,
86/12A, 86/14, 86/30, 86/35, 88/25, 88/40A, 88/45, 186/03A, 186/51, 188/48, 188/56, 286/10A,
286/12/14/16, 386/2X, 386/3X, 386/1 XX or 8086,8088,80186 or 80188, 80286 and 386 CPU-based target
system to a Series III, or Series IV Intellec@ Microcomputer Development System or iRMX I or II Based System
for execution and interactive debugging of applications software on the target system. The Monitor can: load
programs into the target system; execute the programs instruction by instruction or at full speed; set breakpoints; and examine/modify CPU registers, memory content, and other crucial environmental details. Additional custom commands can be built using the Command Extension Interface (CEI). The Monitor supports the
OEM's choice of the iRMX I Operating System, the iRMX II Operating System, or a custom system for the
target application system. OEM's may utilize any iRMX supported target system peripheral for a bootstrap of
'the application system or have full access to the ISIS-II files of the Intellec System or the iRMX file system.

230882-1

7-106

October 1988
Order Number: 230882-005

iSDMTM MONITOR

FUNCTIONAL DESCRIPTION
Overview
The is OM Monitor extends the software development capabilities of an iRMX or Intellec system so
the user can effectively develop applications to ensure timely product availability.

based on breakpoints or single stepping requests;
examination, modification and movement of memory
contents; examination and modification of CPU registers, including NPX registers. All results are displayed in clearly understandable formats. Refer to
Table 1 for a more detailed list of the iSOM monitor
commands.

Numeric Data Processor Support
The iSDM package consists of four parts:
Arithmetic applications utilizing the 8087, 80287 or
80387 Numeric Processor Extension (NPX) are fully
supported by the iSDM Monitor. In addition to executing applications with the full NPX performance,
users may examine and modify the NPX's registers
using decimal and real number format.

• The loader program
• The iSDM Monitor
• The Command Extension Interface (CEI)
• The UDI Library Interface
The user can use the iSDM package to load programs into the target system from the development
system, execute programs in an instruction-by-instruction manner, and add custom commands
through the command extension interface. The user
also has the option of using just the iSOM Monitor
and the CEI in a stand-alone application, without the
use of a development system.

Powerful Debugging Commands
The iSDM Monitor contains a powerful set of commands to support the debugging process. Some of
the features included are: bootstrap of application
software; selective execution of program modules

This feature allows the user to feel confident that
correct and meaningful numbers are entered for the
application without having ·to encode and decode
complex real, integer, and BCD hexadecimal formats.

Command Extension Interface (CEI)
The Command Extension Interface (CEI) allows the
addition of custom commands to the iSDM Monitor
commands. The CEI consists of various procedures
that can be used to generate custom commands. Up
to three custom commands (or sets of commands)
can be added to the monitor without programming
new EPROMs or changing the monitor's source
code.

Table 1. Monitor Commands
Command

Function

B
C

Bootstrap application program from target system peripheral device
Compare two memory blocks
Display contents of memory block
Exit from loader program to iRMX or ISIS-II Interface
Find specified constant in a memory block
Execute application program
Input and display data obtained from input port
Echo console display to a file
Load absolute object file into target system memory
Move contents of memory block to another location
Display and execute single instruction
Output data to output port
Print values of literals
Load and execute absolute object file in target system memory
Display and (optionally) modify contents of memory
User defined custom commands extensions
Examine and (optionally) modify CPU and NPX registers
Display/Define 80286 compiler symbol information

0
E*

F
G
/

K
L*
M
N

0
P
R*
S
U,V,W
X

'Commands require an attached development system.

7-107

inter

ISDMTM MONITOR

Universal Development Interface
The Universal Development interface (UDI) consists
of libraries that contain interfaces to iRMX and ISIS
II I/O calls. A program running on an 8086, 8088,
80186, 80188, 80286, or 386 CPU-based system
can use UDI and access iRMX and ISIS II I/O calls.
The interface allows the inclusion of these calls into
the program; however, most of the calls require an
iRMX or Intellec host system. Table 2 contains a
summary of the major I/O calls.

quirements of the target system. Pre-configured
EPROM-resident monitors are supplied by Intel for
the iSBC 86/05A, 86/12A, 86/14, 86/30, 86/35,
88/25, 88/10A, 88/45, 186/03A, 186/51, 188/48,
188/56, 286/10A, 286/12/14/16, 386/2X/3X, and
386/1XX boards. The monitor must be configured by
the user for other 8086, 8088, 80186, or 80188 applications. iRMX I and iRMX II system users may use
the configuration facilities to include the Bootstrap
Loader (V5.0 or newer) in the monitor.

Variety of Connections Available
Program Load Capability
The iSDM loader allows the loading of 8086, 8088,
80186, 80188, 80286 or 386 CPU-based programs
into the target system. It executes on a development
system and c9mmunicates with the target system
through a serial or a parallel load interface.

Configuration Facility
The monitor contains a full set of configuration facilities which allows it to be carefully tailored to the re-

The physical interface between the development
system and the target system can be established in
one of three ways. The systems can be connected
via a serial link, a parallel link or a fast parallel link.
The cabling arrangement is different depending
upon the development system being used.
The iSDM Monitor does not require the use of a development system. The monitor can be used by simply attaching a stand-alone terminal to the target
system.

Table 2. Routines for Services Available to Target System Applications
Routine
DQ$ATIACH
DQ$CLOSE
DQ$CREATE
DQ$DELETE
DQ$DETACH
DQ$GET$CONNECTION$STATUS
DQ$OPEN
DQ$READ
DQ$RENAME
DQ$SEEK
DQ$SPECIAL
DQ$TRUNCATE
DQ$WRITE

Target System Function
Creates a connection to a specified file.
Closes the specified file connection.
Creates a file for use by the application.
Deletes a file.
Closes a file and deletes its connection.
Returns status of a file connection.
Opens a file for a particular type of access.
Reads the next sequence of bytes from a file.
Renames the specified file.
Moves the current position pointer of a file.
Defines options and actions for the program execution environment.
Truncates a file to the specified length.
Writes a sequence of bytes to a file.

7-108

inter

iSDMTM MONITOR

System Monitor EPROMs: (Continued)

SPECIFICATIONS

Intel Board

Hardware
• Supported iSBC Microcomputers:
Single Board
iSBC 86/05A
iSBC 86/12A
Single Board
iSBC 86/14
Single Board
Single Board
iSBC 86/30
Single Board
iSBC 86/35
Single Board
iSBC 88/25
iSBC 88/40A
Single Board
iSBC 88/45
Single Board
iSBC 186/03A
Single Board
iSBC 186/51
Single Board
iSBC 188/48
Single Board
Single Board
iSBC 186/56
iSBC 286/10A
Single Board
iSBC 286/12/14/16 Single Board
iSBC 386/2X/3X
Single Board
iSBC 386/1XX
Single Board

iSBC88/25
iSBC88/40A
Computer
Computer
Computer
Computer
Computer
Computer
Computer
Computer
Computer
Computer
Computer
Computer
Computer
Computer
Computer
Computer

iSBC 88/45
iSBC 186/03A

Two 27128 EPROMs

iSBC 188/48
iSBC 188/56
iSBC 286/10A
iSBC 286/12/14/16
iSBC 386/2X/3X

Two 27128 EPROMs

iSBC 38611 XX

Two 27256 EPROMs

iRMX and Intellec host to target system interface and target system monitor, suitable for use on iSBC 86, 88,
186, 188, 286, 386 computers, or other8086, 8088, 80186, 80188, 80286,
386 microcomputers. Package includes cables, EPROMs, software
and reference manual.
The OEM license option listed here
allows use on a single hostltarget
system and incorporation into their
applications. Each incorporation requires payment of an Incorporation
Fee.

Interface and Execution Software Diskettes:
2-DS/DD, iRMX-Format 5%"
2-SS/DD, iRMX-Format 8"
2-SS/DD, ISIS II-Format 8"

The iSDM package also includes 90
days of support services that include
Software Program Report Services.

System Monitor EPROMs:

iSBC86/12A

SUBMIT Files on the
Release Diskette

Two 27256 EPROMs

Part Number Description
SDMSC
Object Software

Cables:
4-RS232 Cable Assemblies (for iRMX/lnteUec
host system and standard terminals)
Hardware package for the cable assemblies

EPROM Description

Two 27128 EPROMs

ORDERING INFORMATION

iSDMTM Package Contents

Two 27128 EPROMs

iSBC 186/51

iSDM System Debug Monitor Installation and Configuration
iSDM System Debug Monitor User's Guide

• Supported Microcomputer Systems
8086/8088/80186/80188/80286/386/CPU
8087/80287/80387 NPX with Serial Controller:
8274 Serial Controller and 8253/8254 timer, or
8251A Serial Controller and 8253/8254 timer, or
82530 Serial Controller 4 KB RAM, and 32 KB
EPROM

Intel Board

Two 27128 EPROMs
Two 27128 EPROMs

Reference Manual (Supplied):

• Supported iSBXTM MULTIMODULE Boards:
iSBX 351 Serial liD MULTIMODULE Board
iSBX 354 Serial 1/0 MULTIMODULE Board

iSBC86/05A
iSBC86/14
iSBC86/30
iSBC86/35

EPROM Description
Two 27128 EPROMs

As with all Intel Software, purchase of
any of these options requires execution of a standard Intel Software license Agreement.
SDMRFX

7-109

Incorporation fee. Permits incorporation of a configured iSDM monitor into
a target system.

S 0 F T - S COP E * I ISO U R C E - LEV E L 0 E BUG G E R

SOURCE-LEVEL ON-TARGET DEBUGGER FOR IRMX® II APPLICATIONS
The SOFT-SCOPE" Debugger is an interactive debugging tool specifically designed for
software developed to execute with the iRMX " Operating Systems on Intel\:; broad set of
system and board-level products. It reduces the time required to debug real-time software
and allows the developer to debug at the most effective level, in the original source code
itself.

FEATURES:
•
•
•
•
•
•
•

Complete High-Level Debugging Functionality
Source Code Interface and On-line Listings
Automatic Expansion of Data Types
Symbolic Display of iRMX " Objects
Second Terminal Option for "Remote" Debugging
Multitasking Support
Handling of 80286/386'" protection Traps and Software Exceptions

• SOFT-SCOPE IS a Teglstered trademark of Concurrent Sciences, Inc

imJ-------------------C

Intel Corporation 1989

7-110

September, 1989
Order Number. 280637·002

FEATURES
COMPLETE HIGH·LEVEL DEBUGGING

MULTI· TASKING SUPPORT

For real-time applications running with iRMX \I
Operating Systems on Intel 80286/386 CPU boards,
software professionals want to focus on original
source code for most debugging operations. SOFTSCOPE \I does just that. It integrates the original
source code into the debugging process directly. All
breakpoint prompts and high-level stepping
operations prompt with original source code rather
than reporting what line number the program has
reached or what assembly instruction is next.

The SOFT-SCOPE \I Debugger supports
simultaneous debugging of concurrent tasks when
they are all linked together as a Human Interface
command and each concurrent task is coded in a
separate module. SOFT-SCOPE loads and then
allows the user to suspend and resume execution of
the tasks from the command line with the SUSPEND
and RESUME commands. In this way the developer
can observe the effect of dynamic changes on the
software under test.

SOURCE CODE INTERFACE AND ON·L1NE
LISTINGS

HANDLING OF 80286/386 PROTECTION
TRAPS AND SOFTWARE EXCEPTIONS

The source code interface frees the programmer from
having to divide attention between the console and
program listings, eliminates the need to get a fresh
program listing each time a small change is made,
and reduces the time needed to make software
modifications.

Exception Handling: The exact source line which
causes an exception can easily be reached and
displayed. All environmental and programmer
exceptions are trapped and reported, without
causing a SOFT-SCOPE debugger exit.

AUTOMATIC EXPANSION OF DATA TYPES
Symbols declared in the program are accessible by
name for display and modification of contents. These
symbols include arrays, structures, static variables,
based variables, and stack-based variables (including
local variables, re-entrant variables, and passed
parameters). Memory can also be displayed with
absolute references or with register-relative
references.

SYMBOLIC DISPLAY OF ALL IRMX II
SYSTEM OBJECTS
The VIEW command allows viewing the status of any
iRMX \I object including tasks, jobs, mailboxes,
semaphores, regions, and segments. With VIEW, the
stack of a task can be examined to determine which
iRMX \I call the task has made most recently. Any
job's object directory and the list of ready and
sleeping tasks can be examined.

SECOND TERMINAL OPTION
Because so many applications today are screenintensive, the SOFT-SCOPE Debugger allows the
option of using a second terminal for all debugger
110, freeing the main console for exclusive use by the
application for application output.

Most of the 80286/386 hardware traps are handled
by the SOFT-SCOPE \I Debugger, including Bounds
Check (INT 5), Invalid Opcode (INT 6), Double Fault
(INT 8), Stack Fault (INT 12), and General Protection
(INT 13). Upon encountering one of these interrupts,
the SOFT-SCOPE \I Debugger breaks execution with
a message similar to the following:

, .7

r------~

I FOUR 21 PIN SITES

INTERFACE~

o
o

ISBC'3t,

"tI

FOUR 21 PIN SITES

C
-I

:II

,LBX'· BUS/SYNCHRONOUS

III

iii'

....o

.......

o
»:II

ON· BOARD LOCAL BUS

C'I

co
en

III

I
I
I

POWERFAIL-

IS'
c::

RS232C
INTERFACE

MULTIBUS' SYSTEM BUS

280079-2

inter

ISBC® 286/10A SINGLE BOARD COMPUTER

SERIAL 1/0
A two channel serial communications interface using
Intel's 8274 Multi-Protocol Serial Controller (MPSC)
is contained on the iSBC 286/10 board. Two independent software selectable baud rate generators
provide the MPSC with all common communication
frequencies. The protocol (i.e., asynchronous, IBM"
bisync, or SOLC/HOLC), data format; control character format, parity and baud rate are all under program control. Software interfacing to the MPSC can
be via either a polled or interrupt driven routine. One
channel may be configured for an RS232C or
RS422/RS449 interface with the other channel
RS232C only. .
PROGRAMMABLE TIMERS
The iSBC 286/10A board provides three independent, fully programmable 16-bit interval timers/event
counters utilizing the Intel 8254 Programmable Interval Timer. Each counter is capable of operating in
either BCD or binary modes. Two of these timers/
counters are available to the systems designer to
generate accurate time intervals under software
control. Routing for the outputs of these counters is
jumper selectable. The outputs may be independently routed to the 8259A Programmable Interrupt
Controller or to the 8274 MPSC to count external
events or provide baud rate generation. The third
interval timer in the 8254 is dedicated to providing a
clock for the programmable baud rate generator in
the iSBC 286/10A board's MPSC serial controller.
LINE PRINTER INTERFACE
An 8255A Programmable Peripheral Interface (PPI)
provides a line printer interface, several on-board
functions, and four non-dedicated input bits. Drivers
are provided for a complete Centronics compatible
line printer interface.

Using the P2 interface, the iSBC 286/1 OA Board can
be configured to operate with either a standard iLBX
interface or with a high-performance, synchronous
interface.
The iSBC 286/10A Board as supplied is configured
to operate with a synchronous, P2 interface. This
high-performance interface is designed to connect
to Intel's new EX series of memory expansion
boards to yield a CPU to memory read/write time of
owait-states. The EX memory expansion boards are
available in sizes ranging from 512K bytes up to 4M
bytes and available in sizes ranging from 512K bytes
up to 2M bytes. Memory expansion boards from other manufacturers that meet the iLBX standard may
also be used. CPU to memory access time is usually
1 or more wait-states depending on the speed of the
memory used.
A total of four memory boards can be placed on the
iLBX or synchronous interface bus. With 4M byte
memory boards, this results in a total of 16M bytes
on the memory expansion bus.
ISBXTM BUS MULTIMODULETM ON-BOARD
EXPANSION
Two 8/16-bit iSBX MULTIMOOULE connectors are
'provided on the iSBC 286/10A microcomputer
board. The iSBX interface connectors on the iSBC
286/10A provide all signals necessary to interface
to the local on-board bus, including 16 data lines for
maximum data transfer rates. iSBX MULTIMOOULE
boards designed with 8-bit data paths and using the
8-bit iSBX connector are also supported on the iSBC
286/10A microcomputer board. A broad range of
iSBX MULTIMOOULE options are available from Intel. Custom iSeX modules may also be deSigned.

SPECIFICATIONS

MULTIMASTER CAPABILITIES

Word Size

The iSBC 286/10A board provides full system bus
arbitration control logic. This control logic allows up
to three iSBC 286/10A boards or other bus masters,
to share the system bus using a serial (daisy chain)
priority scheme and allows up to 16 masters to
share the MULTIBUS system bus with an external
parallel priority decoder.

Instruction-8, 16, 24, 32 or 40 bits
Oata-8 or 16 bits

System Clock
CPU-8.0 MHz
Numeric Processor-5.3 or 8.0 MHz (Jumper Selectable)

HIGH SPEED OFF-BOARD MEMORY
The iSBC 286/10A board can access off-board
memory either over the MULTIBUS (P1) interface, or
over the P2 interface. Memory transfers over the P2
interface are faster because the CPU board doesn't
have to arbitrate for access to the MULTIBUS interface

Cycle Time
Basic Instruction-8.0 MHz-375 ns; 250 ns (assumes instruction in queue)

8-28

inter

ISBC® 286/10A SINGLE BOARD COMPUTER

NOTE:
Basic instruction cycle is defined as the fastest instruction time (i.e., two clock cycles)

Interrupt Levels-16 vectored requests using two
8259As and the 80286's NMI line.

INTERFACES

Local Memory

MULTIBUS Bus-All signals TTL compatible

Number of sockets-Four 28-pin JEDEC sites, expandable to 8 sites using iSBC 341 JEDEC Expansion Module

iSBX Bus-All Signals TTL compatible

Maximum Size-256 KB

iLBX Bus-All signals TTL compatible

Compatible Devices-EPROM, up to 64K x 8 (Intel
27512)

Synchronous Interface-All signals TTL compatible
Serial I/O-Channel A: RS232C/RS422/RS449
compatible, DCE or DTE; Channel B; RS232C compatible, DCE only

Dual·Port Memory
Number of sockets-Four 28-pin JEDEC sites, expandable to 8 sites using iSBC 341 JEDEC Expansion Module

Timer-All signals TTL compatible
Interrupt Requests-All TTL compatible

Maximum Size-128 KB

Physical Characteristics

Compatible Devices-EPROM, up to 32K x 8 (Intel
27256)

Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.4 in. (1.0 cm)
Minimum Slot Spacing: 0.6 in. (1.5 cm)
Weight: 14 oz. (397 gm)

SRAM
iRAM, up to 8K x 8 (Intel 2186)
E2PROM, up to 2K x 8 (Intel 2817A)

1/0 Capability

Electrical Characteristics

Parallel-Line printer interface, on-board functions,
and four non-dedicated input bits

DC Power Requirements: +5V, 7.0A; ±12V, 50 mA
(serial /10)

Serial-Two programmable channels using one
8274 device

NOTE:
Does not include power for optional EPROM,
E2PROM, or RAM memory devices, or installed
MULTIMODULE boards

Timers-Three programmable timers using one
8254 device

Environmental Characteristics

Expansion-Two 8/16-bit iSBX MULTIMODULE
connectors

Operating Temperature: O·C to 60·C with 7 CFM airflow across board

Serial Communications
Characteristics
Synchronous-5-8 bit characters; internal or
HDLC/SDLC character synchronization; automatic
sync insertion; even or odd parity

Relative Humidity: to 90% (without condensation)
I

Reference Manual
147532-iJ01-iSBC@ 286/10A Hardware Reference
Manual (order separately)

Asynchronous-5-8 bit characters; break character
generation; 1, 1%, or 2 stop bits; false start bit detection; even or odd parity

ORDERING INFORMATION
Part Number
SBC286/10A

Interrupt Capacity
Potential Interrupt Sources-25, 5 fixed, 20 jumper
selectable
8-29

Description
Single Board Computer

iSBC® 186/03A *
SINGLE BOARD COMPUTER

•
•
•
•

8.0 MHz 80186 Microprocessor with
Optional 8087 Numeric Data Pro~essor
Eight (Expandable to 12) JEDEC 28-Pin
Sites
Six Programmable Timers and 27
Levels of Vectored Interrupt Control
MULTIBUS® Interface for System
Expansion and Multlmaster
Configuration

•

24 Programmable 1/0 Lines
Conflgurable as a SCSI Interface,
Centronics Interface or General
Purpose 1/0

•
•
•

Two iSBXTM Bus Interface Connectors
for Low Cost 1/0 Expansion
iLBXTM (Local Bus Extension) Interface
for High-Speed Memory Expansion
Two Programmable Serial Interfaces;
One RS 232C, the Other RS 232C or
RS 422 Compatible

The iSBC 186/03A Single Board Computer is a member of Intel's complete line of microcomputer modules
and systems that take advantage of Intel's VLSI technology to provide economical, off-the-shelf, computerbased solutions for OEM applications. The board is a complete microcomputer system on a 7.05 x 12.0 inch
printed circuit card. The CPU, system clock, memory, sockets, 1/0 ports and drivers, serial communications
interface, priority interrupt logic and programmable timers, all reside on the board.
The iSBC 186/03A board incorporates the 80186 CPU and SCSI interface on one board. The extensive use of
high integration VLSI has produced a high-performance single-board system. For large memory applications,
the iLBX local bus expansion maintains this high performance.

230988-1

"The iSBCII> 186/03A board is also manufactured under product code piSBCII> 186/03A and siSBCII> 186/03A by Intel
Puerto Rico, Inc. and Intel Singapore, Ltd.

8-30

September 1989
Order Number: 23098Il-006

intJ

iSBC® 186/03A COMPUTER

OVERVIEW

BITBUSTM MASTER CONTROLLER
The BITBUS interconnect environment is a high performance low-cost microcontroller interconnect
technology for distributed control of intelligent industrial machines such as robots and process controllers. The BITBUS interconnect is a special purpose
serial bus which is ideally suited for the fast transmission of short messages between the microcontroller nodes in a modularly distributed system.

Operating Environment
The iSBC 186/03A single board computer features
have been designed to meet the needs of numerous
microcomputer applications. Typical applications include:
• Multiprocessing single board computer
• BITBUS master controller

The iSBC 186/03A board can be implemented as
the MULTIBUS-based master controller CPU which
monitors, processes and updates the control status
of the distributed system. The iSBX 344 board is
used to interface the iSBC 186/03A board to the
BITBUS interconnect. Actual message transfer over
the iSBX bus can be accomplished by either software polling by the CPU or by using the on-chip
80186 DMA hardware instead of the CPU. Using
DMA, the CPU is only required to start the DMA process and then poll for the completion of the message transfer, thus dramatically improving the data
transmission rate and master control processor efficiency. The maximum transfer rates over the iSBX
bus for the iSBC 186/03A board are about 900 messages/second in polled mode and 2500 messages/
second in DMA mode. An 8 MHz iSBC 186/03A
board in DMA mode is 3 times as fast as a typical
5 MHz iSBC 86/30 board running in polled mode.
The iSBC 186/03A board in DMA mode provides the
highest performance/price solution for BITBUS
message transmission out of all of Intel's complete
line of 16-bit CPU modules.

• Stand-alone singe I board system
MULTIPROCESSING SINGLE BOARD
COMPUTER
High-performance systems often need to divide system functions among multiple processors. A mUltiprocessing single board computer distributes an applications processing load over multiple processors
that communicate over a system bus. Since these
applications use the system bus for inter-processor
communication, it is required that each processor
has local execution memory.
The iSBC 186/03A board supports loosely coupled
multiprocessing (where each processor performs a
specific function) through its MULTIBUS compatible
architecture. The IEEE 796 system bus facilitates
processor to processor communication, while the
iLBX bus makes high-speed data and execution
memory available to each CPU as shown in Figure 1.
This architecture allows multiple processors to run in
~arallel enabling very high-performance applicatIons.

SERIAL LINK
TO MAINFRAME

c:::J c:::J
ISBC'" 544
BOARD

ISBC'" 012CX RAM
BOARD

ISBC'" 186/03A
BOARD

ILBXBUS

MULTIBUS· SYSTEM BUS

230988-2

Figure 1. A Multiprocessing Single Board Computer Application
8-31

iSBC~

186/03A COMPUTER

INTERNAL MACHINE CONTROL

,-------------------,
I

MASTER CONTROLLER

~
~

¢>¢

ISBX" BUS

ISBX" 344
BITBUS"
INTERFACE
BOARD

BITBUS"
INTERCONNECT

_-_

.....

¢>¢

IRCB 44110

ISBX" BUS

......-.-=-...

r----......

TEMPERATURE
MONITORING
AND CONTROL _ _ _ _- - '

MOTOR

.... CONTROL

OPERATOR
INTERFACE
PUSH
BUTTONS

, . . . . - - - - - , OPERATOR
L...._ _ _- - ' DISPLAY

L ___________________

ICHANDLER

230988-3

Figure 2. Sample ISBC@ 186/03A BITBUSTM MaBter Application
If more memory is needed, an optional iSBC 341
memory site expansion board can be added to provide an additional four JEDEC sites. Two iSBX MULTIMODULETM boards can be added to the iSBC
186/03A board to customize the board's I/O capabilities. As shown in Figure 3, the iSBX connectors
can support a single-board system with the analog
input and output modules needed by machine or
process control systems.

STAND-ALONE SINGLE BOARD SYSTEM
A stand-alone single board system is a complete
computer system on one board. By reducing the system's board count, the single board system saves
space, power, and ultimately, costs. The on-board
resources need to be capable of performing all of
the basic system functions. These applications typically require terminal support, peripheral control, local RAM and program execution. In previous gener. ations of single board computers. these functions
could only be obtained with multiple board solutions.

FUNCTIONAL DESCRIPTION

The iSBC 186/03A board integrates all the functions
of a general purpose system (CPU, memory, I/O and
peripheral control) onto one board. The iSBC
186/03A board can also be customized as a single
board system by the selection of memory and iSBX
I/O options. The board's 8 JEDEC 28-pin sockets
can accommodate a wide variety of byte-wide memory devices.

Architecture
The iSBC 186/03A board is functionally partitioned
into six major sections: central processor, memory,
SCSI compatible parallel interface, serial I/O. interrupt control and MULTIBUS bus expansion. These
areas are illustrated in Figure 4.

8-32

intJ

ISBC® 186/03A COMPUTER

ISBX g 311
ANALOG INPUT
BOARD

230988-4

Figure 3. A Stand-Alone Single Board System Application

FOUR SITE

EXPANSION
:
l ____________
...!
I

MULTIBUS· SYSTEM BUS

230988-5

Figure 4. ISBell!> 186/03A Board Block Diagram

8-33

intJ

ISBC@ 186/03A COMPUTER

sired function. Available functions include: interrupt
on terminal count, programmable one-shot, rate
generator, square-wave generator: software triggered strobe, hardware triggered strobe and event
counter. The contents of each counter may be read
at any time during system operation.

CENTRAL PROCESSOR
The 80186 component is a high-integration 16-bit
microprocessor. It combines several of the most
common system components onto a single chip (i.e.
Direct Memory Access, Interval Timers, Clock Generator and Programmable Interrupt Controller). The
80186 instruction set is a superset of the 8086. It
maintains object code compatability while adding
ten new instructions. Added instructions include:
Block I/O, Enter and Leave subroutines, Push Immediate, Multiply Quick, Array Bounds Checking,
Shift and Rotate by Immediate, and Pop and Push
All.

MEMORY
There are eight JEDEC 28-pin memory sites on the
iSBC 186/03A board providing flexible memory expansion. Four of these sites (EPROM sites) may be
used for EPROM or E2PROM program storage,
while the other four (RAM sites) may be used for
static RAM or iRAM data storage or used as additional program storage. The eight sites can be extended to twelve by the addition of an iSBC 341
MULTIMODULE board. These additional sites will
provide up to 64K bytes of RAM using 8K x 8 SRAM
or iRAM devices. The EPROM sites (Bank B) are
compatible with 8K x 8 (2764), 16K x 8 (27128A),
32K x 8 (27256), 64K x 8 (27512) as well as 2K x 8
(2817A) and 8K x 8 (2864) E2PROMs. The RAM
sites (Bank A) are compatible with all bytewide
SRAM, iRAM or NVRAM devices. NVRAM usage requires additional circuitry in order to guarantee data
retention. Bank A can be reassigned to upper memory just below the assigned memory space for Bank
B to support additional EPROM or E2PROMs.

Use of the 80130 component is limited to the 3 timers and 8 levels of interrupts available. Direct processor execution of the 16K bytes of iRMX I Operating System nucleus primitives is not supported.
An optional 8087 Numeric Data Processor may be
installed by the user to dramatically improve the
186/03A board's numerical processing power. The
interface between the 8087 and 80186 is provided
by the factory-installed 82188 Integrated BLls Controller which completes the 80186 numeric data processing system. The 8087 Numeric Data Processor
option adds 68 floating-point instructions and eight
80-bit floating pOint registers to the basic iSBC 186/
03A board's programming capabilities. Depending
on the application, the 8087 will increase the performance of floating point calculations by 50 to 100
times.

Memory addressing for the JEDEC sites depends on
the device type selected. The four EPROM sites are
top justified in the 1 MB address space and must
contain the power-on instructions. The device size
determines the starting address of these devices.
The four RAM sites are, by default, located starting
at address O. The addressing of these sites may be
relocated to upper memory (immediately below the
EPROM site addresses) in applications where these
sites will contain additional program storage. The
optional iSBC 341 MULTIMODULE sites are addressable immediately above the RAM site addresses.

) TIMERS
The 80186 provides three internal 16-bit programmable timers. Two of these are highly flexible and
are connected to four external pins (two per timer).
They can be used to count external events, time external events, generate non repetitive waveforms,
etc. As shipped on the iSBC 186/03A board, these
two timers are connected to the serial interface, and
provide bau'd rate generation. The third timer is not
connected to any external pins, and is useful for
real-time coding and time-delay applications. In addition, this third timer can be used as a prescaler to
the other two, or as a DMA request source. The
80130 provides three more programmable timers.
One is a factory default baud rate generator and outputs an 8254 compatible square wave that can be
used as an alternate baud rate source to either serial
channel. The 80130's second timer is used as a system timer. The third timer is reserved for use by the
iRMX Operating System. The system software configures each timer independently to select the de-

Power-fail control and auxiliary power are provided
for protection of the RAM sites when used with static
RAM devices. A memory protect signal is provided
through an auxiliary connector (J4) which, when asserted, disables read/write access to RAM memory
on the board. This input is provided for the protection of RAM contents during system power-down sequences. An auxiliary power bus is also provided to
allow separate power to RAM for systems requiring
battery back-up of read/write memory. Selection of
this auxiliary RAM power bus is made via jumpers on
the board.

8-34

intJ

iSBC® 186/03A COMPUTER

essary handshake timing. Interrupts are gene~at~d
for printer fault conditions and a DMA request IS ISsued for every character. The interface supports
Centronics type printers compatible with models 702
and 737.

SCSI PERIPHERAL INTERFACE

The iSBC 186/03A board includes a parallel peripheral interface that consists of three 8-bit parallel
ports. As shipped, these ports are configured for
general purpose 1/0. The 'parall~1 interface m.ay ~e
reconfigured to be compatible with the SCSI disk Interface by adding two user-supplied and programmed Programmable Array Logic (PAL) devices,
moving jumpers and installing a user-supplied
74LS640-1 device. Alternatively, the parallel Interface may be reconfigured as a DMA controlled Centronics compatible line printer interface by adding
one PAL and changing jumpers. Refer to the iSBC
186/03A Hardware Reference Manual for PAL
equations and a detailed implementation procedure.

SERIAL 1/0

The iSBC 186/03A Single Board Computer contains
two programmable communications interfaces using
the Intel 8274 Multi-Protocol Serial Controller
(MPSC).
Two 80186 timer outputs are used as software selectable baud rate generators capable of supplying
the serial channels with common communications
frequencies. An 80130 baud rate timer may be jumpered to either serial port to provide higher frequency
baud rates. The mode of operation (Le., asynchronous, byte synchronous or bisynchronous pro.tocols), data format, control character format, panty,
and baud rate are all under program control. The
8274 provides full duplex, double buffered trans~it
and receive capability. Parity, overrun, and framing
error detection are all incorporated in the MPSC.
The iSBC 186/03A board supports operation in the
polled, interrupt and DMA driven in.terfaces t~rou~h
jumper options. The default configuration IS With
channel A as RS422A1RS449, channel B as
RS232C. Channel A can optionally be configured to
support RS232C. Both channels are default configured as data set (DCE). Channel A can be reconfigured as data terminal (DTE) for connection to a modem-type device.

The SCSI (Small Computer Systems Interface) interface allows up to 8 mass storage peripherals such
as Winchester disk drives, floppy disk drives and
tape drives to be connected directly to the ~~BC
186/03A board. Intel's iSBC 186/03A board utilizes
a single initiator, single target implementation of the
SCSI bus specification. Bus arbitration and deselect/reselect SCSI features are not supported. Single host, multiple target configurations ~an be used.
However, the iSBC 186/03A board Will stay connected to one target until the transaction is completed before switching to the second target. The iSBC
186/03A board's SCSI interface implements a 5 megabit/second transfer rate. A sample SCSI application is shown in Figure 5.
The Centronics interface requires very little software
overhead since a PAL device is used to provide nec-

SCSI BUS

Isec· l86/03A
BOARD

MULTI BUS· SYSTEM BUS

230988-6

Figure 5. Sample SCSI Application

8-35

intJ

iSBC® 186/03A COMPUTER

INTERRUPT CONTROL

MULTIBUS@ SYSTEM BUS-IEEE 796

The iSBC 186/03A board provides 27 on-board vectored interrupt levels to service interrupts generated
from 33 possible sources.

The MULTIBUS system bus is an industry standard
(IEEE 796) microcomputer bus structure. Both 8and 16-bit single board computers are supported on
the IEEE 796 structure with 20 or 24 address and 16
data lines. In its simplest application, the system bus
allows expansion of functions already contained on
a single board computer (e.g., memory and I/O).
However, the IEEE 796 bus also allows very powerful distributed processing configurations with multiple processors and intelligent slave, I/O and peripheral boards capable of solving the most demanding
microcomputer applications. The MULTIBUS system
bus is supported with a broad array of board-level
products, LSI interface components, detailed published specifications and application notes.

The interrupts are serviced by four programmable
interrupt controllers (PICs): one in the 80186 component, one in the 80130 component, one in the 8259A
component and one in the 8274 component. The
80186, 8259A and 8274 PICs act as slaves to the
80130 master PIC. The highest priority interrupt is
the Non-Maskable Interrupt (NMI) line which is tied
directly to the 80186 CPU. This interrupt is typically
used to signal catastrophic events (e.g. power failure). The PICs provide prioritization and vectoring for
the other 26 interrupt requests from on-board I/O
resources and from the MULTIBUS system bus. The
PICs then resolve the requests according to the programmable priority resolution mode, and if appropriate, issue an interrupt to the CPU.

Isax'·

MULTlMODULE'·
aOARD

230988-7

Figure 6.ISBC@ 186/03A Board Syatem Architecture

8-36

inter

iSBC® 186/03A COMPUTER

ILBXTM BUS-LOCAL BUS EXTENSION

Basic Instruction Cycle Time

The iSBC 1B6/03A board provides a local bus extension (iLBX) interface. This standard extension allows on-board memory performance with physically
off-board memory. The combination of a CPU board
and iLBX memory boards is architecturally equivalent to a Single board computer and thus can be
called a "virtual single board computer". The iLBX
bus is implemented over the P2 connector and requires independent cabling or backplane connection.

750 ns
250 ns (assumes instruction in the queue)
NOTE:
Basic instruction cycle is defined as the fastest instruction time (Le. two clock cycles plus instruction
fetch). Zero wait-state memory is assumed.
MEMORY CAPACITYI ADDRESSING
Four EPROM Sites

ISBXTM BUS MULTIMODULETM
ON-BOARD EXPANSION

Device
2764 EPROM
2712B EPROM
27256 EPROM
27512 EPROM

Two iSBX MULTIMODULE board connectors are
provided on the iSBC 1B6/03A microcomputer
board. Through these connectors, additional onboard 110 functions may be added. iSBX MULTIMODULE boards optimally support functions provided by VLSI peripheral components such as additional parallel and serial 1/0, analog 1/0, and graphics
control. The iSBX bus connectors on the iSBC
1B6/03A board provide all signals necessary to interface to the local on-board bus, including 16 data
lines for maximum data transfer rates. MULTIMODULE boards deSigned with B-bit data paths and using
the B-bit iSBX connector are also supported on the
iSBC 1B6/03A board. A broad range of iSBX MULTIMODULE options are available from Intel. Custom
iSBX bus modules may also be designed.

Capacity
32KB
64KB
12B KB
256KB

Address Range
FBOOOH-FFFFFH
FOOOOH-FFFFFH
EOOOOH-FFFFFH
COOOOH-FFFFFH

Four RAM Sites
Device

Capacity

Address Range

2KSRAM
BKSRAM
32KSRAM
21B6 RAM
2B17A E2PROM
2764 EPROM

BKB
32KB
12B KB
32KB
BKB
32KB

27128 EPROM

64KB

27256 EPROM

12B KB

0-01FFFH
0-07FFFH
0-1FFFFH
0-07FFFH
FOOOOH-F7FFFH'
FOOOOH-F7FFFH
(below EPROM Sites)
EOOOOH-EFFFFH
(below EPROM Sites)
COOOOH-DFFFFH
(below EPROM Sites)

SPECIFICATIONS

Four ISBC® 341 Expansion Sites

Word Size
Instruction-B, 16, 24 or 32 bits
Data-8 or 16 bits

System Clock
B.O MHz

Device

Capacity

2KSRAM
BKSRAM
32KSRAM
21B6 RAM
2B17A E2PROM

BKB
32 KB
12B KB
32 KB
BKB

Address Range
02000H-03FFFH
OBOOOH-OFFFFH
10000H-1 FFFFH
OBOOOH-OFFFFH
02000H-03FFFH··

NOTE:
All on board memory is local to the CPU (i.e. not dual-ported).
'Must use 8k x 8 decode option, there are four copies of
the E2PROM in the 8K x 8 address area.
"(May be mixed with 2K x 8 SRAM)

Numeric Data Processor (Optional)
BOB7-1

B-37

iSBC® 186/03A COMPUTER

Serial Communications Characteristics

REFERENCE MANUAL

Synchronous-

5-8 bit characters; internal or external character synchronization;
automatic sync insertion; break
character generation
Asynchronous- 5-8 bit characters; 1, %, or 2
stop bit; false start bit detection.

iSBC® 186/03A Single Board Computer Hardware
Reference Manual-Order Number 148060

PHYSICAL CHARACTERISTICS
Width: 12.00 in. (30.48 cm)
Length: 7.05 in (17.90 em)
Height: 0.50 in. (1.78 cm)
Weight: 13 ounces

Interface Compliance
MULTIBUS- IEEE 796 compliance: Master 016
M24116 VO EL
iSBX Bus- Two 8/16 bit iSBX bus connectors allow use of up to 2 single-wide modules or 1 single-wide and 1 doublewide module. Intel iSBX bus compliance: 016/16 OMA
iLBXIntel iLBX bus compliance: PM 016
SerialChannel A: Configurable as RS 422A
or RS 232C compatible,
configurable as a data
set or data terminal
Channel B: RS 232C compatible,
configured as data set
Parallell/Q- SCSI (ANSI-X3T9, 2/82-s) compatible or Centronics 702 or 737 compatible (requires user supplied PALs and
74LS640-1)

ENVIRONMENTAL CHARACTERISTICS
Operating Temperature: O°C to 60°C at 6 CFM airflow over the board.
Relative Humidity: to 90% (without condensation)

ELECTRICAL CHARACTERISTICS
The maximum power required per voltage is shown
below. These numbers' do not include the power required by the optional memory devices, SCSI PALs,
battery back-up or expansion modules.

Voltage
(volts)
+5
+ 12
-12

ORDERING INFORMATION
Part Number
SBC 186/03A

Description
186-based Single Board Computer

8-38

Max. Current
(amps)
5.4
0.04
0.04

Max Power
(watts)
27
0.48
0.48

ISBC® SGC/3S* SINGLE BOARD COMPUTER

CMOS 80C86-BASED MULTIBUS®I SINGLE-BOARD COMPUTER
The ISBC® 86C/38 Single-Board Computer is a high-performance, low-power MULTIBUS®I
CPU board based on advanced CMOS (complementary metal oxide semiconductor)
technology. The board features Intel's 8 MHz 80C86 microprocessor-which provides the
highest performance possible with static CMOS devices-a full megabyte of zero wait state
DRAM memory, and power consumption of typically less than 8 watts when operating at full
speed. The board's high performance, low power consumption, low heat generation and
high reliability make it ideal for embedded real-time applications in harsh industrial
environments.

STANDARD FEATURES:
• Advanced CMOS 8 MHz 80C86
microprocessor
o 1 Mbyte of dual-port, zero wait state
DRAM with panty
o Sockets for up to 512 Kbytes of standard
32-pln JEDEC EPROM devices
• Real-time clock/calendar with on-board
battery backup

I."m_I'
I "e- .

• Temperature-sensing device socket
• Optional 8087 numeric data processor
with iSBC 337A MULTIMODULE'·
• Upward-compatible with iSBC 86/35
• iRMX® Real-Time Operating System
support

The ,SSC' BBC/3B Soard IS also manufaclured under producl code p,SSC' BBC/3B by Inlel Puerlo

~'co. Inc
September, 1989
Order Number 280630·002

8-39

FEATURES
CMOS TECHNOLOGY FOR LOW POWER,
LOW HEAT

MORE MEMORY

The Intel iSBC'1> 86C/38 has been implemented
entirely in CMOS, from the 80C86 CPU and EPLDs to
the descrete logic and peripheral components. CMOS
means low power consumption and low heat
generation.
When running at full speed (8M Hz), the iSBC 86C/3S
typically requires less than 8 watts of power. However,
a power-saving Slow Mode further reduces power
consumption to about 4 watts when operating speed
is reduced to 1 MHz.

UPWARD-COMPABILITY WITH ISBC 86/35
DESIGNS

Slow Mode operation is especially useful during
temporary or emergency conditions when battery
power is called into use. In a power-fail situation, for
instance, Slow Mode operation allows the
uninterrupted processing of an application on battery
power.
The iSBC 86C/38 generates so little heat that it can
operate without any air flow. This allOws elimination of
fans and other expensive cooling equipment and
operation of the iSBC 86C/38 in a sealed enclosure,
protected from harsh environments.

HIGH RELIABILITY
The iSBC 86C/38 features improved reliability on
several levels. First, CMOS technology is inherently
more reliable than NMOS technology: because
devices run at lower junction temperatures, they last
longer.
Parity error checking in the DRAM circuitry improves
system integrity by detecting memory errors.

The amount of on-board memory has been doubled in
the iSBC 86C/38 from earlier iSBC 86/35 board
models. The iSBC 86C/38 comes with a full megabyte
of zero wait state dynamic RAM, supporting the full
8086 address space. A full megabyte of on-board
memory also eliminates the need to add DRAM
modules, preserving the economy of a single-slot
solution.

The iSBC 86C/38 provides complete hardware and
software compatibility with Intel iSBC 86/35 designs.
All features supported on the iSBC 86/35 board run on
the iSBC 86C/38 board with no changes. This includes
full access to the MULTIBUS 116 Mbyte memory
address range and support for MULTIBUS I
multi master, 8087 math coprocessor, iSBC 86/35 I/O
devices, iSBX connectors and interrupt capability.

PERFECT FOR REAL-TIME EMBEDDED
APPLICATIONS
Real-time process control and industrial automation
applicaitons frequently require the CPU and control
system to be physically located on the factory floor or
in the field. These environments are typically harsh, full
of dust, dirt, electrical noise and widely fluctuating I
temperatures.
Because the iSBC S6C/38 generates so little heat and
can operate without cooling, it can be placed in a
sealed enclosure, protected from harsh factory
environments. It also offers excellent noise immunity
and tolerance to extreme temperatures.

Finally, improved pin and socket I/O connectors with
locking tabs assure secure connections of cables to
the board.

8-40 .

FEATURES

Comoctar
J1

MULTlBUS·

s,a..... BUI

Figure 1: iSBC®86C/38 Block Diagram

8-41

SPECIFICATIONS
Central Processor
80C86 CPU
8 MHz
Numberic Processor
8 MHz
iSBC 337A MULTIMODULE

Timers

Three programmable
timer/counters using one
82C54 device

Interfaces
MULTI BUS Bus
iSBX Bus
Parallel I/O
Serial I/O

Cycle Time
Basic Instruction

8 MHz500ns
(assumes instruction in
queue)
Note: Basic instruction cycle is defined as the fastest
instruction time (i.e. four clock cycles)

All signals TTL compatible
All signals TTL compatible
All signals TTL compatible
RS-232-C

POWER REQUIREMENTS/,
CONSUMPTION
BMHz

1MHz

Maximum:
+5V
+12V
-12V

1.56 A, 7.8 Watts
.06 A, .72 Watts
.08 A, .96 Watts

.8 A, 4.0 Watts
.06 A, .72 Watts
.08 A, .96 Watts

Typical:
+5V
+12V
-12V

.82 A, 4.1 Watts
.04 A, .48 Watts
.06 A, .72 Watts

.7 A, 3.5 Watts
.04 A, .48 Watts
.06 A, .72 Watts

DRAM Memory
On-board parity memory

1 Mbyte, 0 Wait States at
8MHz
Note: Power fail battery backup capability via
P2 connector.

EPROM Memory
Number of sockets

Four 32-pin JEDEC Sites
(compatible with 28-pin
and 32-pin devices)
Device access speeds
265ns (minimum) to 640ns
(maximum)
Maximum memory
512 Kb with 27010 (1 M
bit) EPROMS
Note: EPROM. E2PROM (read only), and Static RAM
devices are supported.

110 CAPABILITY
Parallel Channel Three 8-bit parallel ports (50 pin
socket connectors) using an
82C55A
Serial Channel One RS-232,C channel using an
82C51 device with speeds from 110
to 19.2 Kb
Isax Expansion Two 8/16-bit iSBX interface
connectors for single or double
wide iSBX MULTIMODULE boards
Real Time Clock/Calendar
An OKI MSM6242 provides real time clock/calendar
capability with clock operation in either 12 or 24 hour
format. The clock/calendar is sustained up to 10,000
hours by an on-board BR2325 lithium battery.

Note: Does not include power for iSBC modules, iSBX
modules or EPROM memory.

ENVIRONMENTAL REQUIREMENTS
Operating Temperature
Relative Humidity
Storage Temperature

0° to +60°C at zero LFM
airflow
0 to 95% noncondensing
- 40 ° to + 70°C

PHYSICAL CHARACTERISTICS
Dimensions
Width:
12.00 in (30.48 cm)
Depth:
7.05 in. (17.91 cm)
Height:
.375 in. (.96 cm)
Recommended Minimum Cardcage Slot Spacing
.6 in (1.5 cm) without iSBC 337A or iSBX
MULTIMODULE
1.2 in (3.0 cm) with iSBC 337A or iSBX
MULTIMODULE
Approximate Weight
21.5 oz (609.5 gm)

REFERENCE MANUAL
454554-iSBC 86C/38 Single Board Compuer User's
Guide

Temperature Sensing
Temperature sensing is an optional capability, allowing
system designers to choose the appropriate level of
temperature sensing for their application. A socket is
on-board which supports four-pin temperature sensor
devices.
Inte"upt Capacity
Potential Interrupt Sources 37 jumper selectable
Interrupt Levels
9 using the 82C59A device
and the 80C86 NMIline
Note: Bus Vetored Interrupt capability is supported.
8-42

ORDERING INFORMATION
SBC 86C38

Single Board Computer

iSBC® 86/35*
SINGLE BOARD COMPUTER

•
• iSBC®
•
•

iSBXTM Bus Connectors
• Two
Programmable Parallel I/O Lines
• 24Programmable
Synchronous/
• Asynchronous RS232C
Compatible

8086 (8086-2) Microprocessor with 5 or
8 MHz CPU Clock

Optional Numeric Data Processor with
337A MULTIMODULETM
Upward Compatible with iSBC 86/30
Single Board Computer

Serial Interface with Software
Selectable Baud Rates

•
•

512K Bytes of Dual-Port Read/Write
Memory Expandable On-Board to 640K
or 1M Bytes

•

Sockets for up to 128K Bytes of JEDEC
24/28-Pin Standard Memory Devices

Three Programmable 16-Bit BCD or
Binary Timers/Event Counters
9 Levels of Vectored Interrupt Control,
Expandable Off Board to 65 Levels

The iSBC 86/35 Single Board Computer is a member of Intel's complete line of OEM microcomputer systems
that take full advantage of Intel's technology to provide economical, self-contained, computer-based solutions
for OEM applications. The board is a complete computer system containing the CPU, system clock, dual port
read/write memory, nonvolatile read only memory, I/O ports and drivers, serial communications interface,
priority interrupt logic and programmable timers.

210219-1

'The ISBC" 86/35 is also manufactured under product code plSBC 86/35 and slSBC 86/35 by Intel Puerto RIco, Inc., and Intel Singapore, Ltd.

8-43

November 1989
Order Number: 210219-005

inter

iSBC® 86/35 SINGLE BOARD COMPUTER

FUNCTIONAL DESCRIPTION

port of the data structures required for today's struc·
tured, high level languages as well as assembly Ian·
guage.

Overview
The iSBC 86/35 board .combines the industry stan·
dard 8086 CPU with up to a megabyte page of board
resident, dual ported system memory. By placing the
direct memory addressing capability of the 8086
CPU on board, MULTIBUS@ access to system memo
ory can be eliminated, significantly improving system
throughput.

Central Processing Unit
The central processor for the iSBC 86/35 board is
Intel's 8086-2 CPU. A clock rate of 8 MHz is support·
ed with a jumper selectable option for 5 MHz. The
CPU architecture includes four 16-bit byte address·
able data registers, two 16-bit index registers, all ac·
cessed by a total of 24 operand addressing modes
for comprehensive memory addressing and for sup·

Instruction Set
The 8086 instruction repertoire includes variable
length instruction format (including double operand
instructions), 8-bit and 16-bit signed and unsigned
arithmetic operators for binary, BCD and unpacked
ASCII data, and iterative word and byte string manip·
ulation functions.
For enhanced 5 or 8 MHz numerics processing ca·
pability, the iSBC 337A MULTIMODULE Numeric
Data Processor extends the architecture and data
set. Over 60 numeric instructions offer arithmetic,
trigonometric, transcendental, logarithmic and expo·
nential instructions. Supported data types include
16-, 32-, and 64-bit integer, and 32- and 64-bit float·
ing pOint, 18-digit packed BCD and 80·bit temporary.

210219-2

Figure 1.ISBC@ 86/35 Block Diagram

8-44

intJ

iSBC® 86/35 SINGLE BOARD COMPUTER

sible I/O configurations, sockets are provided for interchangeable I/O line drivers and terminators, allowing the selection of the appropriate combination
of optional line drivers and terminators with the required drive/termination characteristics. The 24 programmable I/O lines and signal ground lines are
brought out to a 50-pin edge connector.

Architectural Features
A 6-byte instruction queue provides pre-fetching of
sequential instructions and can reduce the 750 ns
minimum instruction cycle to 250 ns for queued instructions. The stack-oriented architecture readily
supports modular programming by facilitating fast,
simple, inter-modular communication, and other programming constructs needed for asynchronous realtime systems. The memory expansion capabilities
offer a 1 megabyte addressing range. The dynamic
relocation scheme allows ease in segmentation of
pure procedure and data for efficient memory utilization. Four segment registers (code, stack, data, extra) contain program loaded offset values which are
used to map 16-bit addresses to 20-bit addresses.
Each register maps 64K bytes at a time and activation of a specific register is controlled explicitly by
program control and is also selected implicitly by
specific functions and instructions.

Serial 110
A programmable communications interface using
the Intel 8251A Universal Synchronous/ Asynchronous Receiver/Transmitter (USART) is contained on
the iSBC 86/35 board. A software selectable baud
rate generator provides the USART with all common
communication frequencies. The mode of operation
(Le., synchronous or asynchronous), data format,
control character format, parity, and baud rate are all
under program control. The 8251A provides full duplex, double buffered transmit and receive capability.
Parity, overrun, and framing error detection are all
incorporated in the USART. The RS232C command
lines, serial data lines and signal ground line are
brought out to a 26-pin edge connector.

RAM Capabilities
The iSBC 86/35 microcomputer contains 512K
bytes of dual-port dynamic RAM which may be expanded on-board by adding a RAM Multimodule
board as an option. The on-board RAM may be expanded to 640K bytes with the iSBC 304 MULTIMODULE board mounted onto the iSBC 85/35
board. Likewise, the iSBC 86/35 microcomputer
may be expanded to 1 Megabyte with the iSBC 314
MULTIMODULE board option.

Programmable Timers
The iSBC 86/35 board provides three independent,
fully programmable 16-bit interval timers/event
counters utilizing the Intel 8253 Programmable Interval Timer. Each counter is capable of operating in
either BCD or binary modes. Two of these timers/
counters are available to the systems designer to
generate accurate timer intervals under software
control. Routing for the outputs and gate/trigger inputs of two of these counters is jumper selectable.
The outputs may be independently routed to the
8259A Programmable Interrupt Controller and to the
I/O terminators associated with the 8255A to allow
external devices or an 8255A port to gate the timer
or to count external events. The third interval timer
in the 8253 provides the programmable baud rate
generator for the iSBC 86/35 board's RS232C
USART serial port. The system software configures
each timer independently to select the desired function. The contents of each counter may be read at
any time during system operation.

The dual-port controller allows access to the onboard RAM (including RAM MULTIMODULE board
options) from the iSBC 86/35 board and from any
other MULTIBUS master via the system bus. Segments of on-board RAM may be configured as a private resource, protected from MULTIBUS system
access.

EPROM Capabilities
Four 28-pin JEDEC sockets are provided for the use
of Intel 2764, 27128, 27256, 27512, EPROMs and
their respective ROMs. When using 27512, the onboard EPROM capacity is 256K bytes. Other JEbEC
standard pinout devices are also supported, including byte-wide static RAMs.

Parallel 110 Interface

isBXTM MULTIMODULETM On-Board
Expansion

The iSBC 86/35 Single Board Computer contains 24
programmable parallel I/O lines implemented using
the Intel 8255A Programmable Peripheral Interface.
The system software is used to configure the I/O
lines in any combination of unidirectional input/output and bidirectional ports indicated in Table 1. In
order to take advantage of the large number of pos-

Two 8/16-bit iSBX MULTIMODULE connectors are
provided on. the iSBC 86/35 microcomputer.
Through these connectors, additional on-board I/O
functions may be added. The iSBX connectors on
the iSBC 86/35 board provides all signals necessary
to interface to the local on-board bus, including 16
data lines for maximum data transfer rates. iSBX
8-45

ISBC® 86/35 SINGLE BOARD COMPUTER

MULTIMODULE boards designed with 8-bit data
paths and using the 8-bit iSBX connector are also
supported on the iSBC 86/35 microcomputer. A
broad range of iSBX MULTIMODULE options are
available from Intel. Custom iSBX modules may also
be deSigned for use on the iSBC 86/35 board.

system in the event of a power failure. Additionally,
an active-low TTL compatible memory protect signal
is brought out on the auxiliary connector which when
asserted, disables read/write access to RAM memory on the board. This input is provided for the protection of RAM contents during system powerdown
sequences. An auxiliary power bus is also provided
to allow separate power to RAM for systems requiring battery backup of read/write memory. Selection
of this auxiliary RAM power bus is made via jumpers
on the board.

Multimaster Capabilities
The iSBC 86/35 board provides full MULTIBUS arbitration control logic. This control logic allows both
serial (daisy chain) and parallel priority schemes.
The serial scheme allows up to three iSBC 86/35
boards/bus masters to share the MULTIBUS system
bus; while up to 16 masters may be connected using
the parallel scheme and external decode logic.

SPECIFICATIONS
Word Size
INSTRUCTION -

Interrupt Capability

DATA -

The iSBC 86/35 board provides 9 vectored interrupt
levels. The highest level is the NMI (Non-Maskable
Interrupt) line which is directly tied to the 8086-2
CPU. This interrupt is typically used for signaling catastrophic events (e.g., power failure). The Intel
8259A Programmable Interrupt Controller (PIC) provides control and vectoring for the next eight interrupt levels. A selection of four priority processing
modes is available for use in designing request processing configurations to match system requirements for efficient interrupt servicing with minimal
latencies. Operating mode and priority assignments
may be reconfigured dynamically via software at any
time during system operation. The PIC accepts interrupt requests from all on-board I/O resources and
from the MULTIBUS system bus. The PIC then resolves requests according to the selected mode
and, if appropriate, issues an interrupt to the CPU.
Any combination of interrupt levels may be masked
via software, by storing a single byte in the interrupt
mask register of the PIC. In systems requiring additional interrupt levels, slave 8259A PICs may be interfaced via the MULTIBUS system bus, to generate
additional vector addresses, yielding a total of 65
unique interrupt levels.

8, 16, 24, or 32 bits

8,16 bits

System Clock
5 MHz or 8. MHz ± 0.1 % Oumper selectable)

Cycle Time
BASIC INSTRUCTION CYCLE
8 MHz - 250 ns (assumes instruction in the queue)
5 MHz -

400 ns (assumes instruction in the queue)

NOTE:
Basic instruction cycle is defined as the fastest instruction time (Le., two clock cycles). Jumper selectable for 1 wait-state on-board memory access.

Memory Capacityl Addressing

Interrupt requests to be serviced by the iSBC 86/35
board may originate from 28 sources. All interrupt
signals are brought to the interrupt jumper matrix
where any combination of interrupt sources may be
strapped to the desired interrupt request level on the
8259A PIC or the NMI input to the CPU directly.

Power-Fail Control and
Auxiliary Power
Control logic is included to accept a power-fail interrupt in conjunction with the AC-Iow signal from the
Power Supply to initiate an orderly shut down of the
8-46

ON-BOARD EPROM
Device
Total Capacity
32K bytes
2764
27128
64K bytes
27256
128K bytes
27512
256K bytes

Address Range
F8000-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH
DOOOO-FFFFFH

ON-BOARD RAM
Total Capacity
Board
iSBC86/35
512K bytes

Address Range
0-7FFFFH

WITH MULTIMODULETM RAM
Total Capacity
Board
640K bytes
iSBC304
1M bytes
iSBC314

Address Range
8-9 FFFFH .
8-FFFFFH

intJ

iSBC® 86/35 SINGLE BOARD COMPUTER

Serial Communications Characteristics

Electrical Characteristics

SYNCHRONOUS-5-8 bit characters; internal or
external character synchronization; automatic sync
insertion

DC POWER REQUIREMENTS
Current Requirements
(All Voltages ±5%)

Configuration

ASYNCHRONOUS-5-8 bit characters; break character generation; 1, 1%, or 2 stop bits; false start bit
detection

Without EPROM(1)

MULTIBUS®-AII signals TTL compatible
iSBXTM BUS-All signals TTL compatible
PARALLEL I/O-All signals TTL compatible
SERIAL I/O-RS232C compatible, configurable as
a data set or data terminal

+12V

-12V

5.1A

25mA

23mA

660mA

With 32K EPROM(3)
(using 2764)

5.6A

25mA

23mA

With 64K EPROM
(using 27128)

5.7A

25mA

23mA

With 128K EPROM
(using 27256)

5.8A

25mA

23mA

RAM only(2)

Interfaces

+5V

NOTES:
1. Does not include power for optional ROM/EPROM, IW
drivers, and I/O terminators.
2. RAM chips powered via auxiliary power bus in powerdown mode.
3. Includes power required for 4 ROM/EPROM chips, and
I/O terminators installed for 16 I/O lines; all terminator inputs low.

TIMER-All signals TTL compatible
INTERRUPT REQUESTS-All TTL compatible

Physical Characteristics
Width:
Height:
Depth:

12.00 in. (30.48 cm)
6.75 in. (17.15 cm)
0.70 in. (1.78 cm)
Weight: 14 oz. (388 gm)

Environmental Characteristics
OPERATING TEMPERATURE - O°C to 55°C
200 linear feet per minute (LFM) air velocity
RELATIVE HUMIDITV sation)

to 90% (without conden-

Reference Manual
146245-002 - iSBC 86/35 Hardware Reference
Manual (NOT SUPPLIED)

ORDERING INFORMATION
Part Number
SBC86/35

8-47

Description
Single Board Computer

iSBC® 86/14* AND iSBC® 86/30*
SINGLE BOARD COMPUTERS

•
• 86/12A
•

8086 Microprocessor with 5 or 8 MHz
CPU Clock
Fully Software Compatible with iSBC®
Single Board Computer

••

Optional Numeric Data Processor with
iSBC® 337 A MULTIMODULETM

•
32K/128K bytes of Dual-Port Read/
• Write
Memory Expandable On-Board to
•
256K bytes with On-Board Refresh
for' up to 64K bytes of JEDEC
• Sockets
•
24/28-pin Standard Memory Devices

•

24 Programmable Parallel I/O Lines
Programmable Synchronousl
Asynchronous RS232C Compatible
Serial Interface with Software
Selectable Baud Rates
Two Programmable 16-Bit BCD or
Binary Timers/Event Counters
9 Levels of Vectored Interrupt Control,
Expandable to 65 Levels
MULTIBUS® Interface for Multlmaster
Configurations and System Expansion

Two iSBXTM Bus Connectors

The iSBC 86/14 and iSBC 86/30 Single Board Computers are members of Intel's complete line of OEM
microcomputer systems which take full advantage of Intel's technology to provide economical, self-contained,
computer-based solutions for OEM applications. The CPU, system clock, read/write memory, nonvolatile read
only memory, I/O ports and drivers, serial communications interface, priority interrupt logic and programmable
timers, all reside on the boards.

280007-1

'The iSBC" 8614 and iSBC" 86/30 are also manufactured under product code piSBC 86/14, piSBC 86/30 or siSBC 86/14, siSBC 86/30 by Intel
Puerto RICO, Inc. or Intel Singapcre, Ltd.

8-48

september 1989
Order Number: 280007-005

inter

iSBC® 86/14 AND iSBC® 86/30 SINGLE BOARD COMPUTERS

For enhanced numerics processing capability, the
iSBC 337A MULTIMODULE Numeric Data Processor extends the architecture and data set. Over 60
numeric instructions offer arithmetic, trigonometric,
transcendental, logarithmic and exponential instructions. Supported data types include 16-, 32, and 64bit integer, and 32- and 64-bit floating point, 1B-digit
packed BCD and BO-bit temporary.

FUNCTIONAL DESCRIPTION
Central Processing Unit
The central processor for the iSBC 86/XX' boards is
Intel's 8086-2 CPU. A clock rate of 8 MHz is supported with a jumper selectable option of 5 MHz. The
CPU architecture includes four 16-bit byte addressable data registers, two 16-bit memory base pointer
registers and two 16-bit index registers, all accessed
by a total of 24 operand addressing modes for comprehensive memory addressing and for support of
the data structures required for today's structured,
high level languages as well as assembly language.

Architectural Features
A 6-byte instruction queue provides pre-fetching of
sequential instructions and can reduce the 750 nsec
minimum instruction cycle to 250 nsec for queued
instructions. The stack-oriented architecture readily
supports modular programming by facilitating fast,
simple, inter-module communication, and other programming constructs needed for asynchronous realtime systems. The memory expansion capabilities
offer a 1 megabyte addressing range. The dynamic
relocation scheme allows ease in segmentation of
pure procedure and data for efficient memory utilization. Four segment registers (code, stack, data, extra) contain program loaded offset values which are
used to map 16-bit addresses to 20-bit addresses.
Each register maps 64K bytes at a time and activation of a specific register is controlled explicitly by
program control and is also selected implicitly by
specific functions and instructions.

NOTE:
iSBC B6/XX designates both the iSBC 86/14 and
iSBC 86/30 CPU boards.

Instruction Set
The 8086 instruction repertoire includes variable
length instruction format (including double operand
instructions), B-bit and 16-bit signed and unsigned
arithmetic operators for binary, BCD and unpacked
ASCII data, and iterative word and byte string manipulation functions.

280007-2

Figure 1_ iSBC® 86/XX Block Diagram
8-49

inter

ISBC® 86/14 AND iSBC® 86/30 SINGLE BOARD COMPUTERS

RAM Capabilities

Programmable Timers

The iSBC 86/14 and iSBC 86/30 microcomputers
contain 32K bytes and 128K bytes of dual-port dynamic RAM, respectively. In addition, on-board RAM
may be doubled on each microcomputer by optionally adding RAM MULTIMODULE boards. The dualport controller allows access to the on-board RAM
(including RAM MULTIMODULE options) from the
iSBC 86/XX boards and from any other MULTIBUS
master via the system bus. Segments of on-board
RAM may be configured as a private resource, protected from MULTIBUS system access.

The iSBC 86/XX boards provide three independent,
fully programmable 16-bit interval timers/event
counters utilizing the Intel 8253 Programmable Interval Timer. Each counter is capable of operating in
either BCD or binary modes. Two of these timers/
counters are available to the systems designer to
generate accurate time intervals under software
control. Routing for the outputs and gate/trigger inputs of two of these counters is jumper selectable.
The outputs may be independently routed to the
8259A Programmable Interrupt Controller and to the
I/O terminators associated with the 8255A to allow
external devices or an 8255A port to gate the timer
or to count external events. The third interval timer
in the 8253 provides the programmable baud rate
generator for the iSBC 86/XX boards' RS232C
USART serial port. The system software configures
each timer independently to select the desired function. The contents of each counter may be read at
any time during system operation.

EPROM Capabilities
Four 28-pin sockets are provided for a maximum onboard EPROM capacity is 64K bytes. Other JEDEC
standard pinout devices are also supported, including byte-wide static RAMs.

Parallel 110 Interface
iSBXTM MULTIMODULETM On-Board
Expansion

The iSBC 86/XX Single Board Computers contain
24 programmable parallel I/O lines implemented using the Intel 8255A Programmable Peripheral Interface. The system software is used to configure the
I/O lines in any combination of unidirectional input!
output and bidirectional ports. In order to take advantage of the large number of possible I/O configurations, sockets are provided for interchangeable 1/
line drivers and terminators, allowing the selection
of the appropriate combination of optional line drivers and terminators with the required drive/termination characteristics. The 24 programmable I/O lines
and Signal ground lines are brought out to a 50-pin
edge connector.

Two 8/16-bit iSBX MULTIMODULE connectors are
provided on the iSBC 86/XX microcomputers.
Through these connectors, additional on-board I/O
functions may be added. iSBX MULTIMODULE
boards optimally support functions provided by VLSI
peripheral components such as additional parallel
and serial I/O, analog I/O, small mass storage device controllers and other custom interfaces to meet
specific needs. By mounting directly on the single
board computer, less interface logiC, less power,
simpler packaging, higher performance, and lower
cost result when compared to other alternatives
such as MULTIBUS form factor compatible boards.
The iSBX connectors on the iSBC 86/XX boards
provide all sign'als necessary to interface to the local
on-board bus, including 16 data lines for maximum
data transfer rates. iSBX MULTIMODULE boards
designed with 8-bit data paths and using the 8-bit
iSBX connector are also supported on the iSBC 86/
XX microcomputers. A broad range of iSBX MULTIMODULE options are available from Intel. Custom
iSBX modules may also be designed for use on the
iSBC 86/XX boards.

Serial 1/0
A programmable communications interface using
the Intel 8251A Universal Synchronous/Asynchronous Receiver/Transmitter (USART) is contained on
the iSBC 86/XX boards. A software selectable baud
rate generator provides the USART with all common
communication frequencies. The mode of operation
(i.e., synchronous or asynchronous), data format,
control character format, parity, and baud rate are all
under program control. The 8251A provides full duplex, double buffered transmit and receive capability.
Parity, overrun, and framing error detection are all
incorporated in the USART. The RS232C command
lines, serial data lines and signal ground line are
brought out to a 26-pin edge connector.

Multimaster Capabilities
For those applications requiring additional processing capacity and the benefits of multiprocessing (i.e.,
several CPUs and/or controllers logically sharing
system tasks through communication of the system

8-50

iSBC® 86/14 AND iSBC® 86/30 SINGLE BOARD COMPUTERS

bus), the iSBC 86/XX boards provide full MULTIBUS
arbitration control logic. This control logic allows up
to three iSBC 86/XX boards or other bus masters,
including iSBC 80 family MULTIBUS compatible 8-bit
single board computers to share the system bus using a serial (daisy chain) priority scheme and allows
up to 16 masters to share the MULTIBUS system
bus with an external parallel priority decoder. In addition to the multiprocessing configurations made
possible with multimaster capability, it also provides
a very efficient mechanism for all forms of DMA (Direct Memory Access) transfers.

for the protection of RAM contents during system
power-down sequences. An auxiliary power bus is
also provided to allow separate power to RAM for
systems requiring battery back-up of read/write
memory. Selection of this auxiliary RAM power bus
is made via jumpers on the board.

SPECIFICATIONS

Word Size
Instruction: B, 16, 24, or 32 bits

Interrupt Capability

Data: B, 16 bits

The iSBC 86/XX boards provide 9 vectored interrupt
levels. The highest level is the NMI (Non-Maskable
Interrupt) line which is directly tied to the 80B6 CPU.
This interrupt is typically used for signaling catastrophic events (e.g., power failure). The Intel 8259A
Programmable Interrupt Controller (PIC) provides
control and vectoring for the next eight interrupt levels. A selection of four priority processing modes is
available for use in designing request processing
configurations to match system requirements for efficient interrupt servicing with minimal latencies. Operating mode and priority assignments may be reconfigured dynamically via software at any time during system operation. The PIC accepts interrupt requests from all on-board I/O resources and from the
MULTIBUS system bus. The PIC then resolves requests according to the selected mode and, if appropriate, issues an interrupt to the CPU. Any combination of interrupt levels may be masked via software, by storing a single byte in the interrupt mask
register of the PIC. In systems requiring additional
interrupt levels, slave B259A PICs may be interfaced
via the MULTIBUS system bus, to generate additional vector addresses, yielding a total of 65 unique
interrupt levels.

System Clock
5.00 MHz or 8.00 MHz ± 0.1 % Oumper selectable)

Cycle Time
BASIC INSTRUCTION CYCLE
B MHz: 750 ns
250 ns (assumes instruction in the queue)

5 MHz: 1.2 fJ-s
400 ns (assumes instruction in the queue)
NOTE:
Basic instruction cycle is defined as the fastest instruction time (i.e., two clock cycles).

Memory Cycle Time
RAM:

750 ns

EPROM: Jumper selectable from 500 ns to B75 ns

Memory Capacity1Addressing

Interrupt requests to be serviced by the iSBC B6/XX
boards may originate from 2B sources. All interrupt
signals are brought to the interrupt jumper matrix
where any combination of interrupt sources may be
strapped to the desired interrupt request level on the
8259A PIC or the NMI input to the CPU directly.

ON-BOARD EPROM
Device
2716
2732A
2764
2712B

Power-Fail Control and Auxiliary
Power

Total Capacity
BK bytes
16K bytes
32K bytes
64K bytes

Address Range
FEOOO-FFFFFH
FCOOO-FFFFFH
FBOOO-FFFFFH
FOOOO-FFFFFH

ON-BOARD RAM

Control logiC is also included to accept a power-fail
interrupt in conjunction with the AC-Iow signal generation capabilities to initiate an orderly shut down of
the system in the event of a power failure. Additionally, an active-low TIL compatible memory protect
signal is brought out on the auxiliary connector
which, when asserted, disables read/write access to
RAM memory on the board. This input is provided

Total Capacity Address Range
Board
iSBC B6/14
32K bytes
0-07FFFH
128K bytes
0-1FFFFH
iSBC86/30

B-51

inter

iSBC@ 86/14 AND iSBC@ 86/30 SINGLE BOARD COMPln'ERS

1/0 Capacity
Parallel: 24 programmable lines using one 8255A
Serial: 1 programmable line using one 8251A

Electrical Characteristics
DC POWER REQUIREMENTS

iSBX MULTIMODULE: 2 iSBX boards

Serial Communications
Characteristics

Without EPROM1
RAM only2
With 8K EPROM3
(using 2716)
With 16K EPROM3
(using 2732A)
With 32K EPROM3
(using 2764)

Synchronous: 5-8 bits characters; internal or external character synchronization; automatic sync insertion
Asynchronous: 5-8 bit characters; break character
generation; 1. 1%. or 2 stop bits; false start bit direction

Interfaces
MULTIBUS: All signals TIL compatible
iSBX Bus: All signals TIL compatible
Parallel I/O: All signals TIL compatible

Current Requirements
(All Voltages ±5%)

Configuratl,on

+5V

+12V

-12V

5.1A
600mA
5.4A

25mA

23mA

25mA

23mA

5.5A

25mA

23mA

5.6A

25mA

23mA

NOTES:
1. Does not include power for optional ROM/EPROM, I/O
drivers, and I/O terminators.
2. RAM chips powered via auxiliary power bus in powerdown mode.
3. Includes power required for 4 ROM/EPROM chips. and
I/O terminators installed for 16 I/O lines; all terminator inputs low.

Serial I/O: RS232C compatible. configurable as a
data set or data terminal

Environmental Characteristics

Timer: All Signals TIL compatible

Operating Temperature: O·C to 55·C
Relative Humidity: to 90% (without condensation)

Interrupt Requests: All TIL compatible

Physical Characteristics

Reference Manual

Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.70 in. (1.78 cm)
Weight: 14 oz (388 gm)

144044-002: iSBC 86/14 and iSBC 86/30 Hardware
Reference Manual (NOT SUPPLIED)

ORDERING INFORMATION
Environmental Characteristics

Part Number Description
SBC 86/14
SBC 86/30

Operating Temperature: O·C to 55·C
Relative Humidity: to 90% (without condensation)

8-52

Single Board Computer
Single Board Computer

iSBC® 8S/0SA *
SINGLE BOARD COMPUTER

•
•
•
•
•
•

•

8086/10 (8086-2) Microprocessor with 5
or 8 MHz CPU Clock
Software Compatible with 8086, 8088,
80186,80286 Based 16-bit Single Board
Computers

•
•
•

Optional Numeric Data Processor with
iSBC® 337 A MULTIMODULETM
8K bytes of Static RAMi Expandable
On-Board to 16K Bytes
Sockets for up to 256K Bytes of JEDEC
24/28-Pin Standard Memory Devicesi
Expandable On-Board to 512K Bytes

Programmable Synchronous/
Asynchronous RS232C Compatible
Serial Interface with Software
Selectable Baud Rate
24 Programmable Parallel I/O Lines
Two Programmable 16-Blt BCD or
Binary Timers/Event Counters
9 Levels of Vectored Interrupt Control,
Expandable to 65 Levels
MULTIBUS® Bus Interface for
Multimaster Configurations and System
Expansion

Two iSBXTM Bus Connectors

The iSBC 86/05A Single Board Computer is a member of Intel's complete line of OEM microcomputer systems which take full advantage of Intel's technology to provide economical, self-contained, computer-based
solutions for OEM applications. The CPU, system clock, read/write memory, nonvolatile read only memory,
I/O ports and drivers, serial communications interface, priority interrupt logic and programmable timers, all
reside on the board. The large control storage capacity makes the iSBC 86/05A board ideally suited for
control-oriented applications such as process control, instrumentation and industrial automation.

143325-1

'The iSBC" 86/05A IS also manufactured under product code piSBC" 86/05A or sISBC" 86/05A by Intel Puerto RICO, Inc. or Intel Singapore. Ltd.

8-53

September 1989
Order Number: 143325-004

iSBC® 86/05A SINGLE BOARD COMPUTER

FUNCTIONAL DESCRIPTION
Central Processing Unit
The central processor for the iSBC 86/05A board is
Intel's 8086-2 CPU. A clock rate of 8 MHz is supported with a jumper selectable option of 5 MHz. The
CPU architecture includes four 16-bit byte addressable data registers, two 16-bit memory base pointer
registers and two 16-bit index registers. All are accessed by a total of 24 operand addressing modes
, for comprehensive memory addressing and for support of the data structures required for today's structured, high level languages as well as assembly language.

Instruction Set
The 8086 instruction repertoire includes variable
length instruction format (including double operand
instructions), 8- and 16-bit signed and unsigned
arithmetic operators for binary, BCD and unpacked
ASCII data, and iterative word and byte string manipulation functions.

Memory Configuration
The iSBC 86/05A microcomputer contains 8K bytes
of high-speed 8K x 4 bit static RAM on-board. In
addition, the above on-board RAM may be expanded to 16K bytes with the iSBC 302 MULTIMODULE
RAM option which mounts on the iSBC 86/05A
board. All on-board RAM is accessed by the 8086-2
CPU with no wait states, yielding a memory cycle
time of 500 ns.
The iSBC 86/05A board also has four 28-pin, 8-bit
wide (byte-wide) sockets, configured to accept
JEDEC 24/28-pin standard memory devices. Up to
256K bytes of EPROM are supported in 64K byte
increments with Intel 27512 EPROMs. The iSBC
86/05A board also supports 2K x 8, 4K x 8, 8K x 8,
16K x 8 and 32K x 8 EPROM memory devices.
These sites also support 2K x 8 and 8K x 8 bytewide static RAM (SRAM) devices and iRAM devices, yielding up to 32K bytes of SRAM in 8K byte increments on the baseboard.
When the addition of the iSBC 341 MULTIMODULE
EPROM option, the on-board capacity for these devices is doubled, providing up to 512K bytes of
EPROM and 64K bytes of byte-wide SRAM capacity
on-board.

For enhanced numerics processing capability, the
iSBC 337A MULTIMODULE Numeric Data Processor extends the architecture and data set. Over 60
numeric instructions offer arithmetic, trigonometric,
transcendental, logarithmic and exponential instructions. Supported data types include 16-, 32-, and
64-bit integer, and 32- and 64-bit floating point, 18digit packed BCD and 80-bit temporary.

Parallel 1/0 Interface
The iSBC 86/05A Single Board Computer contains
24 programmable parallel I/O lines implemented using the Intel 8255A Programmable Peripheral Interface. The system software is used to configure the
I/O lines in any combination of unidirectional input/output and bidirectional ports indicated in Table
1. In order to take advantage of the large number of
possible I/O configurations, sockets are provided for
interchangeable I/O line drivers and terminators, allowing the selection of the appropriate combination
of optional line drivers and terminators with the required drive/termination characteristics. The 24 programmable I/O lines and signal ground lines are
brought out to a 50-pin edge connector.

Architectural Features
A 6-byte instruction queue provides pre-fetching of
sequential instructions and can reduce the 740 ns
minimum instruction cycle to 250 ns for queued i'1structions. The stack-oriented architecture readily
supports modular programming by facilitating fast,
simple, inter-module communication, and other programming constructs needed for asynchronous realtime systems. The memory expansion capabilities
offer a 1 megabyte addreSSing range. The dynamic
relocation scheme allows ease in segmentation of
pure procedure and data for efficient memory utilization. Four segment registers (code, stack, data, extra) contain program loaded offset values which are
used to map 16-bit addresses to 20-bit addresses.
Each register maps 64K bytes at a time with activation of a specific register controlled explicity by program control and selec~ed implicity by specific functions and instructions. All Intel languages support
the extended memory capability, relieving the programmer of managing the megabyte memory space
yet allowing explicit control when necessary.

Serial 1/0
A programmable communications interface using
the Intel 8251A Universal Synchronous/Asynchronous Receiver/Transmitter (USART) is contained on
the iSBC 86/05A board. A software selectable baud
rate generator provides the USART with all common
communication frequencies. The mode of operation
(Le., synchronous or asynchronous), data format,
control character format, parity, and baud rate are all
under program control. The 8251A provides full duplex, double buffered transmit and receive capability.
Parity, overrun, and framing error detection are all
8-54

inter

iSBC® 86/05A SINGLE BOARD COMPUTER

8K BYTES RAM

ISBC' 337A

PROCESSOR

(ISBC" 302)
I
I ________
(4x2168)
1..
.1D

Nu.,~~:IC

I
I
:

1.. __ ..!~t71. __ .J

MULTIBUS· SYSTEM BUS

143325-2

Figure 1. iSBC® 86/05A Block Diagram
incorporated in the USART. The RS232C compatible interface in conjunction with the USART, provides a direct interface to RS232C compatible terminals, cassettes, and asynchronous/synchronous
modems. The RS232C command lines, serial data
lines and signal ground line are brought out to a 26pin edge connector.

or to count external events. The third interval timer
in the 8254 provides the programmable baud rate
generator for the iSBC 86/05A board RS232C
USART serial port. The system software configures
each timer independently to select the desired function. The contents of each counter may be read at
any time during system operation.

Programmable Timers

iSBXTM MULTIMODULETM On-Board
Expansion

The iSBC 86/05A board provides three independent, fully programmable 16-bit interval timers/event
counters utilizing the Intel 8254 Programmable Interval Timer. Each counter is capable of operating in
either BCD or binary modes. Two of these timers/
counters are available to the systems designer to
generate accurate time intervals under software
control. Routing for the outputs and gate/trigger inputs of two of these counters is jumper selectable.
The outputs may be independently routed to the
8259A Programmable Interrupt Controller and to the
I/O terminators associated with the 8255A to allow
external devices or an 8255A port to gate the timer

Two 8/l6-bit iSBX MULTIMODULE connectors are
provided on the iSBC 86/05A microcomputer.
Through these connectors, additional on-board I/O
and memory functions may be added. iSBX MULTIMODULE boards support functions such as additional parallel and serial I/O, analog I/O, mass storage
device controllers BITBUSTM controllers, bubble
memory, and other custom interfaces to meet specific needs. By mounting directly on the single board
computer, less interface logic, less power, simpler

8-55

iSBC® 86/0SA SINGLE BOARD COMPUTER

packaging, higher performance, and lower cost result when compared to other alternatives such as
MULTIBUS form factor compatible boards. The iSBX
connectors on the iSBC 86/05A board provide all
signals necessary to interface to the local on-board
bus, including 16 data lines for maximum data transfer rates. iSBX MULTIMODULE boards designed
with 8-bit data paths and using the 8-bit iSBX connector are also supported on the iSBC 86/05A microcomputer. A broad range of iSBX MULTIMODULE options are available from Intel. Custom iSBX
modules may also be designed for use on the iSBC
86/05A board.

Any combination of interrupt levels may be masked
via software, by storing a single byte in the interrupt
mask register of the PIC. In systems requiring additional interrupt levels, slave 8259A PICs may be interfaced via the MULTIBUS system bus, to generate
additional vector addresses, yielding a total of 65
unique interrupt levels.
Interrupt requests to be serviced by the iSBC
86/05A board may originate from 24 sources. All interrupt signals are brought to the interrupt jumper
matrix where any combination of interrupt sources
may be strapped to the desired interrupt request level on the 8259A PIC or the NMI input to the CPU
directly.

Multimaster Capabilities
For those applications requiring additional processing capacity and the benefits of multiprocessing (Le.,
several CPUs and/or controllers logically sharing
system tasks through communication of the system
bus), the iSBC 86/05A board provides full MULTIBUS arbitration control logic. This control logic allows up to three iSBC 86/05A boards or other bus
masters to share the system bus using a serial (daisy chain) priority scheme and allows up to 16 masters to share the MULTIBUS system bus with an extemal parallel priority decoder. In addition to the multiprocessing configurations made possible with multimaster capability, it also provides a very efficient
mechanism for all forms of DMA (Direct Memory Access) transfers.

Interrupt Capability

Power-Fail Control and Auxiliary
Power
Control logic is also included, to accept a power-fail
interrupt in conjunction with a power-supply having
AC-Iow signal generation capabilities to initiate an
orderly shut down of the system in the event of a
power failure. Additionally, an active-low TIL compatible memory protect signal is brought out on the
auxiliary connector which, when asserted, disables
read/write access to RAM for systems requiring battery backup of read/write memory. Selection of this
auxiliary RAM power bus is made via jumpers on the
board.

SPECIFICATIONS
Word Size

The iSBC 86/05A board provides 9 vectored interrupt levels. The highest level is the NMI (Non-Maskable Interrupt) line which is directly tied to the 8086
CPU. This interrupt is typically used for signaling catastrophic events (e.g., power failure). The Intel
8259A Programmable Interrupt Controller'(PIC) provides control and vectoring for the next eight interrupt levels. A selection of four priority processing
modes is available for use in designing request processing configurations to match system requirements for efficient interrupt servicing with minimal
latencies. Operating mode and priority assignments
may be reconfigured dynamically via software at any
time during system operation. The PIC accepts interrupt requests from all on-board I/O resources and
from the MULTIBUS system bus. The PIC then resolves requests according to the selected mode
and, if appropriate, issues an interrupt to the CPU.

Instruction: 8, 16, 24, or 32 bits
Data: 8, 16 bits
System Clock
5.00 MHz or 8.00 MHz ± 0.1 % Oumper selectable)

Basic Instruction Cycle
At 8 MHz: 750 ns
250 ns (assumes instruction in the
queue)
At 5 MHz: 1.2 sec.
400 ns (assumes instruction in the queue)

NOTE:
Basic instruction cycle is defined as the fastest instruction time (Le., two clock cycles).

8-56

iSBC® 86/05A SINGLE BOARD COMPUTER

Memory Cycle Time

SERIAL COMMUNICATIONS
CHARACTERISTICS

500 ns cycle time (no wait states requires a memory
component access time of 250 ns or less)
RAM: 500 ns
EPROM: Jumper selectable from 500 ns to 875 ns

SYNCHRONOUS -

ASYNCHRONOUS- 5-8 bit characters; break
character generation; 1, 1%,
or 2 stop bits; false start bit direction.

Memory CapacityI Addressing
JEDEC 24/28 Pin Sites
Device
2K x 8
4K X 8
8K X 8
16K X 8
32K X 8
64K X 8

Total Capacity

Address Range

8K bytes
16K bytes
32K bytes
64K bytes
128K bytes
256K bytes

FEOOO-FFFFFH
FCOOO-FFFFFH
F8000-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH
COOOO-FFFFFH

INTERFACES

With iSBC® 341 MULTIMODULETM
EPROM/SRAM
Device
2K x 8
4K X 8
8K X 8
16K X 8
32K X 8
64K X 8

Total Capacity
16K bytes
32K bytes
64K bytes
128K bytes
256K bytes
512K bytes

5-8 bit characters; internal or
external character synchronization; automatic sync insertion.

MULTIBUS Bus:

All signals TTL compatible

iSBX BUS Bus:

All signals TTL compatible

PARALLEL 1/0:

All signals TTL compatible
RS232C
compatible,
configurable as a data
set or data terminal

Address Range
FCOOO-FFFFFH
F8000-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH
COOOO-FFFFFH
80000-FFFFFH

SERIAL 1/0:

All signals TTL compatible

TIMER:

INTERRUPT REQUESTS: All TTL compatible

ON-BOARD STATIC RAM

Physical Characteristics

8K bytes -

Width:

0-1 FFFH

16K bytes- 0-3FFFH (with iSBC 302 MULTIMODULE Board)

12.00 in. (30.48 cm)

Height: 6.75 in. (17.15 cm)
Depth:

0.70 in. (1.78 cm)

Weight: 14 oz (388 gm)

1/0 CAPACITY
PARALLEL
SERIAL

24 programmable lines using one 8255A.

1 programmable line using
one 8251A.

iSBX MULTIMODULE- 2
iSBX
single
wide
MULTIMODULE board or 1
iSBX double-width MULTIMODULE board.

8-57

ISBC@ 86/05A SINGLE BOARD COMPUTER

ELECTRICAL CHARACTERISTICS

ENVIRONMENTAL
CHARACTERISTICS

DC Power Requirements

Operating Temperature: O·C to SS·C
Relative Humidity: to 90% (without condensation)

Configuration
Without EPROM(1)
RAMonly(2)
With 8K EPROM(3)
(using 2716)
With 16K EPROM(3)
(using 2732)
With 32K EPROM(3)
(using 2764)

Current Requirements
(All Voltages ±5%)
+5V
+12V -12V
4.7A
120mA
S.OA

2SmA

23mA

2SmA

23mA

4.9A

2SmA

23mA

4.9A

2SmA

23mA

REFERENCE MANUAL
Order no. 147162·002-iSBC 86/05A Hardware
Reference Manual (NOT SUPPLIED)

ORDER INFORMATION
Part Number
Description
SBC 86/0SA 16·bit Single Board Computer with
8K bytes RAM

NOTES:
1. Does not include power for optional ROM/EPROM, I/O
drivers, and I/O terminators.
2. RAM chips powered· via auxiliary power bus in power·
down mode.
3. Includes power required for 4 ROM/EPROM chips, and
I/O terminators installed for 16 I/O lines; all terminator in·
puts low.

8-S8

iSBC® 88/25*
SINGLE BOARD COMPUTER

•
•
•
• iSBC®
•
•

•

8-Bit 8088 Microprocessor Operating at
5 MHz

One Megabyte Addressing Range

Two iSBXTM Bus Connectors

•
•
•
•

Optional Numeric Data Processor with
337A MULTIMODULETM
4K Bytes of Static RAM; Expandable
On-Board to 16K Bytes
Sockets for up to 64K Bytes of JEDEC ,
24!28-Pin Standard Memory Devices;
Expandable On-Board to 128K Bytes

Programmable Synchronous!
ASYflchronous RS232C Compatible
Serial Interface with Software
Selectable Baud Rates
24 Programmable Parallel I/O Lines
Two Programmable 16-Bit BCD or
Binary Timers!Event Counters
9 Levels of Vectored Interrupt Control,
Expandable to 65 Levels
MULTIBUS® Interface for Multimaster
Configurations and System Expansion

The iSBC 88/25 Single Board Computer is a member of Intel's complete line of OEM microcomputer systems
which take full advantage of Intel's technology to provide economical, self-contained, computer-based solutions for OEM applications. The CPU, system clock, read/write memory, nonvolatile read only memory, I/O
ports and drivers, serial communications interface, priority interrupt logic and programmable timers, all reside
on the board. The large control storage capacity makes the iSBC 88/25 board ideally suited for control-oriented applications such as process control, instrumentation and industrial automation.

143847-1

The iSBC" 88/25 is also manufactured under product code pISBC" 88/25 or slSBC 88/25 by Intel Puerto RICO, Inc. or Intel Singapore, Ltd.

8-59

September 1989
Order Number: 143847-004

iSBC® 88/25 SINGLE BOARD COMPUTER

FUNCTIONAL DESCRIPTION

ASCII data, and iterative word and byte string manipulation functions.

Central Processing Unit

For enhanced numerics processing capability, the
iSBC 337A MULTIMODULE Numeric Data Processor extends the architecture and data set. Over 60
numeric instructions offer arithmetic, trigonometric,
transcendental, logarithmic and exponential instructions. Supported data types include 16, 32, and 64bit integer, and 32 and 64-bit floating pOint, 18-digit
packed BCD and 80-bit temporary.

The central processor for the iSBC 88/25 board is
Intel's 8088 CPU operating at 5 MHz. The CPU architecture includes four 16-bit byte addressable data
registers, two 16-bit memory base pointer registers
and two 16-bit index registers, all accessed by a total of 24 operand addressing modes for comprehensive memory addressing and for support of the data
structures required for today's structured, high level
languages, as well as assembly language.

Architectural Features
A 4-byte instruction queue provides pre-fetching of
sequential instructions and can reduce the 750 ns
minimum instruction cycle to 250 ns for queued instructions. The stack-oriented architecture readily
supports modular programming by facilitating fast,
simple, inter-module communication, and other programming constructs needed for aSYflchronous realtime systems. The memory expansion capabilities

Instruction Set
The 8088 instruction repertoire includes variable
length instruction format (including double operand
instructions), 8-bit and 16-bit signed and unsigned
arithmetic operators for binary, BCD and unpacked

MULnluS' SYSTEM BUS

143847-2

Figure 1. iSBC® 88/25 Block Diagram

8-60

inter

ISSC® 88/25 SINGLE SOARD COMPUTER

offer a 1 megabyte addressing range. The dynamic
relocation scheme allows ease in segmentation of
pure procedure and data for efficient memory utilization. Four segment registers (code, stack, data, extra) contain program loaded offset values which are
used to map 16-bit addresses to 20-bit addresses.
Each register maps 64 Kbytes at a time and activation of a specific register is controlled explicitly by
program control and is also selected implicitly by
specific functions and instructions.

Parallel 1/0 Interface
The iSBC 88/25 Single Board Computer contains 24
programmable parallel 110 lines implemented using
the Intel 8255A Programmable Peripheral interface.
The system software is used to configure the 1/0
lines in any combination of unidirectional input/output and bidirectional ports indicated in Table 1. In
order to take advantage of the large number of possible 1/0 configurations, sockets are provided for interchangeable 1/0 line drivers and terminators, allowing the selection of the appropriate combination
of optional line drivers and terminators with the required drhle/termination characteristics.

Memory Configuration
The iSBC 88/25 microcomputer contains 4 Kbytes
of high-speed static RAM on-board. In addition, the
. on-board RAM may be expanded to 12 Kbytes via
the iSBC 302 8 Kbyte RAM module which mounts on
the iSBC 88/25 board and then to 16 Kbytes by adding two 4K x 4 RAM devices in sockets on the iSBC
302 module. All on-board RAM is accessed by the
8088 CPU with no wait states, yielding a memory
cycle time of 800 ns.

The 24 programmable 1/0 lines and signal ground
lines are brought out to.a 50-pin edge connector.

Serial 110
A programmable communications interface using
the Intel 8251A Universal Synchronous/Asynchronous ReceiverlTransmitter (USART) is contained on
the iSBC 88125 board. A software selectable baud
rate generator provides the USART with all common
communication frequencies. The mode of operation
(i.e., synchronous or asynchronous), data format,
control character format, parity and baud rate are all
under program control. The 8251A provides full duplex, double buffered transmit and receive capability.
Parity, overrun and framing error detection are all
incorporated in the USART. The RS232C compatible interface on each board, in conjunction with the
USART, provides a direct interface to RS232C compatible terminals, cassettes and asynchronous and
synchronous modems. The RS232C command
lines, serial data lines and signal ground line are
brought out to a 26-pin edge connector.

In addition to the on-board RAM, the iSBC 88125
board has four 28-pin sockets, configured to accept
JEDEC 24/28-pin standard memory devices. Up to
64 Kbytes of EPROM are supported in 16 Kbyte increments with Intel 27128 EPROMs. The iSBC
88125 board is also compatible with the 2716, 2732
and 2764 EPROMs.
With the addition of the iSBC 341 MULTIMODULE
EPROM option, the on-board capacity for these devices is doubled, providing up to 128 Kbytes of
EPROM capacity on-board.

Table 1. Input/Output Port Modes of Operation
Mode of Operation
Unidirectional
Port

Lines
(qty)

Input
Latched

2
3

8
8
4
4

X
X
X
X

Output

Latched &
Strobed

X
X

Latched

X
X
X
X

Bidirectional

Control

Latched &
Strobed

X
X

X
X(l)
X(l)

NOTE:
1. Part of port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input or a
latched and strobed output port or port 1 is used as a bidirectional port.

8-61

inter

ISBC~ 88/25 SINGLE BOARD COMPUTER

several.CPUs andlor controllers logically sharing
system tasks through communication of the system
bus), the iSBC 88/25 board provides full MULTIBUS
arbitration control logic. This control logic allows up
to three iSBC 88/25 boards or other bus masters,
including iSBC 80 and iSBC 86 family MULtlBUS
compatible Single board computers to share the system bus using a serial (daisy chain) priority scheme
and allows up to 16 masters to share the MULTIBUS
system bus with an external parallel priority decoder.
In addition to the multiprocessing configurations
made possible with multimaster capability, it also
provides a very efficient mechanism for all forms of
DMA (Direct Memory Access) transfers.

Programmable Timers
The iSBC 88/25 board provides three independent.
fully programmable 16-bit interval timerslevent
counters utilizing the Intel 8253 Programmable Interval Timer. Each counter is capable of operating in
either BCD or binary modes. Two of these timersl
counters are available to the systems designer to
generate accurate time intervals under software
control. Routing for the outputs and gate/trigger inputs of two of these counters is jumper selectable.
The outputs may be independently routed to the
8259A Programmable Interrupt Controller and to the
I/O terminators associated with the 8255A to allow
external devices or an 8255A port to gate the timer
or to count external events. The third interval timer
in the 8253 provides the programmable baud rate
generator for the iSBC. 88/25 board RS232C
USART serial port. The system software configures
each timer independently to select the desired function.

Interrupt Capability
The iSBC 88/25 board provides 9 vectored interrupt
levels. The highest level is the NMI (Non~Maskable
Interrupt) line which is directly tied to the 8088 CPU.
This interrupt is typically used for signaling catastrophic events (e.g., power failure). The Intel 8259A
Programmable Interrupt Controller (PIC) provides
control and vectoring for the next eight interrupt levels. A selection of four priority processing modes is
available for use in designing request processing
configurations to match system reqUirements for efficient interrupt servicing with minimal latencies. Operating mode and priority assignments may be reconfigured dynamically via software at any time during system operation. The PIC accepts interrupt requests from all on-board 110 resources and from the
MULTIBUS system bus. The PIC then resolves requests according to the selected mode and, if appropriate,.issues an interrupt to the CPU.

ISBXTM MULTIMODULETM On-Board
Expansion
Two 8-bit iSBX MULTIMODULE connectors are provided on the iSBC 88/25 microcomputer. Through
these connectors, additional on-board 110 functions
such as additional parallel and serial I/O, analog
1/0, mass storage device controllers and other custom interfaces may be added. By mounting directly
on the single board computer, less interface logiC,
less power, simpler packaging, higher performance,
and lower cost result when compared to other alternatives such as MULTIBUS form factor compatible
boards. The iSBX connectors on the iSBC 88/25
provide all signals necessary to interface to the local
on-board bus. A broad range of iSBX MULTIMODULE options are available from Intel. Custom iSBX
modules may also be designed for use on the iSBC
88/25 board.

Interrupt requests to be serviced by the iSBC 88/25
board may originate from 24 sources. All interrupt
signals are brought to the interrupt jumper matrix
where any combination of interrupt sources may be
strapped to the desired interrupt request level on the
8259A PIC or the NMI input to the CPU directly.

Multimaster Capabiiities
For those applications requiring additional processing capacity and the benefits of multiprocessing (i.e.,

8-62

iSBC® 88/25 SINGLE BOARD COMPUTER

Power-Fail Control and Auxiliary
Power

Memory CapacityI Addressing

Control logic is also included to accept a power-fail
interrupt to initiate an orderly shut down of the system in the event of a power failure. Additionally, an
active-low TTL compatible memory protect signal is
brought out of the auxiliary connector which, when
asserted, disables read/write access to RAM memory on the board. This input is provided for the protection of RAM contents during system power-down
sequences. An auxiliary power bus is also provided
to allow separate power to RAM for systems requiring battery backup of read/write memory. Selection
of this auxiliary RAM power bus is made via jumpers
on the board.

ON-BOARD EPROM
Device
Total Capacity
2716
8 Kbytes
16 Kbytes
2732
2764
32 Kbytes
27128
64 Kbytes

Address Range
FEOOO-FFFFFH
FCOOO-FFFFFH
F8000-FFFFFH
FOOOO-FFFFFH

WITH iSBC 341 MULTIMODULE EPROM
Device
2716
2732
2764
27128

SPECIFICATIONS

Total Capacity
16 Kbytes
32 Kbytes
64 Kbytes
126 Kbytes

Address Range
FCOOO-FFFFFH
F8000-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH

ON-BOARD RAM
4 Kbytes-O-OFFFH

Word Size
Instruction-8, 16, 24, or 32 bits
Data-8 bits

WITH iSBC 302 MULTIMODULE RAM
12 Kbytes-0-2FFFH

System Clock

WITH iSBC 302 MULTIMODULE BOARD AND
TWO 4K x 4 RAM CHIPS

5.00 MHz or 4.17 MHz ±0.1 % Gumper selectable)

16 Kbytes-O-3FFFH

NOTE:
4.17 MHz required with the optional iSBC 337 module.

I/O Capacity
Parallel-24 programmable lines using one 8255A
Serial-1 programmable line using one 8251A
iSBX Multimodule-2 iSBX MULTIMODULE boards

Cycle Time
BASIC INSTRUCTION CYCLE

Serial Communications Characteristics

At 5 MHz-1.2 /A-s
-400 ns (assumes instruction in the
queue)

Synchronous-5 8-bit characters; internal or external character synchronization; automatic sync insertion
Asynchronous-5 8-bit characters; break character
generation; 1, 1%, or 2 stop bits; false start bit detection

NOTES:
Basic instruction cycle is defined as the fastest instruction time (Le., two clock cycles).

Memory Cycle Time
RAM-800 ns (no wait states)
EPROM-Jumper selectable from 800 ns to 1400 ns

8-63

inter

ISBC@ 88/25 SINGLE BOARD COMPUTER

Interfaces
Multibus: All Signals TIL compatible

Electrical Characteristics
DC POWER REQUIREMENTS

iSBX Bus: All signals TIL compatible

Current Requirements
(All Voltages ±5%)

Configuration

Parallel I/O: All Signals TIL compatible

Without EPROM(l)
RAM only(2)

Timer: All signals TIL compatible

With 8K EPROM(3)
(using 2716)
With 16K EPROM(3)
(using 2732)
With 32K EPROM(3)
(using 2764)

Interrupt Requests: All TIL compatible

Physical Characteristics
Width: 12.00 in. (30.48 cm)

+12V

-12V

25mA

23mA

4.3A

25mA

23mA

4.4A

25mA

23mA

4.4A

25mA

23mA

+5V
3.8A

Serial 1/0: RS232C compatible, configurable as a
data set or data terminal

104mA

NOTES:
1. Does not include power for optional ROM/EPROM, 110
drivers and 110 terminators.
2. RAM chips powered via auxiliary power bus in powerdown mode. Does not include power for optional RAM.
3. Includes power required for 4 ROM/EPROM chips, and
110 terminators installed for 16 110 lines; all terminator inputs low.

Height: 6.75 in. (17.15 cm)
Depth: 0.70 in. (1.78 cm)
Weight: 14 oz. (388 gm)

Environmental Characteristics
Operating Temperature: O·C to 55·C
Relative Humidity: to 90% (without condensation)

Reference Manual
143825-001-iSBC 88/25
Manual (NOT SUPPLIED)

Hardware

Reference

ORDERING INFORMATION

8-64

Part Number

Description

SBC 88/25

8-bit Single Board Computer
with 4 Kbytes RAM

iSBC® 80/30*
SINGLE BOARD COMPUTER
Central Processing Unit
Programmable Synchronousl
• 808SA
•
Asynchronous
RS232C Compatible
16K Bytes of Dual Port Dynamic Readl .
• Write
Serial Interface with Fully Software
Memory with On-Board Refresh
Selectable Baud Rate Generation
Sockets for up to 8K Bytes of Read
• Only
12 levels of Programmable Interrupt
Memory
• Control
for 8041A/8741A Universal
• Sockets
Programmable 16-Bit BCD or
Peripheral Interface and
• Two
Binary Counters
Interchangeable line Drivers and line
Terminators
Power Bus, Memory Protect,
• Auxiliary
and Power-Fail Interrupt Control logic
24 Programmable Parallel 1/0 lines
• with Sockets for Interchangeable line
for RAM Battery Backup
Drivers and Terminators

•

Full MUlTIBUS® Control logic

The iSBC 80/30 Single Board Computer is a member of Intel's complete line of OEM computer systems which
take full advantage of Intel's LSI technology to provide economical self-contained computer-based solutions
for OEM applications. The CPU, system clock, read/write memory, nonvolatile read only memory, universal
peripheral interface capability, I/O ports and drivers, serial communications interface, priority interrupt logic,
programmable timers, MULTIBUS control logic, and bus expansion drivers all reside on the board.

280219-1

'The iSBC® 80/30 board is also manufactured under product code piSBC® 80/30 and siSBC® 80/30 by Intel Puerto Rico,
Inc. and Intel Singapore, Ltd.

8-65

September 1989
Order Number: 280219-003

inter

ISBC@ 80/30 SINGLE BOARD COMPUTER

ther the CPU or via the MULTIBUS. Memory space
assignment can be selected independently for onboard and MULTIBUS RAM accesses. The on-board
RAM, as seen by the 8085A CPU, may be placed
anywhere within the 0- to 64K-address space. The
iSBC 80/30 provides extended addressing jumpers
to allow the on-board RAM to reside within a one
megabyte address space when accessed via the
MULTIBUS. In addition, jumper options are provided
which allow the user to reserve 8K- and 16K-byte
segments of on-board RAM for use by the 8085A
CPU only. This reserved RAM space is not accessible via the MULTIBUS and does not occupy any system address space.

FUNCTIONAL DESCRIPTION
Central Processing Unit
Intel's 8-bit n-channel 8085A CPU, fabricated on a
single LSI chip, is the central processor for the iSBC
80/30. The 8085A CPU is directly software compatible with the Intel 8080A CPU. The 8085A contains
six 8-bit general purpose registers and an accumulator. The six general purpose registers may be addressed individually or in pairs, providing both single
and double precision operators. The minimum instruction execution time is 1.45 microseconds. The
8085A CPU has a 16-bit program counter. An external stack, located within any portion of iSBC 80/30
read/write memory, may be used as a last-in/first- .
out storage area for the contents of the program
counter, flags, accumulator, and all of the six general purpose registers. A 16-bit stack pOinter controls
the addressing of this eternal stack. This stack provides subroutine nesting bounded only by memory
size.

EPROMIROM Capacity
Sockets for up to 8K bytes of nonvolatile read only
memory and provided on the iSBC 80/30 board.

Parallel 1/0 Interface
The iSBC 80/30 contains 24 programmable parallel
110 lines implemented using the Intel 8255A Programmable Peripharal Interface. The system software is used to configure the 110 lines in any combination of unidirectional inputloutput and bidirectional ports. Therefore, the liD interface may be customized to meet specific peripheral requirements. In
order to take full advantage of the large number of
possible liD configurations, sockets are provided for
interchangeable I/O line drivers and terminators.
Hence, the flexibility of the liD interface is further
enhanced by the capability of selecting the appropriate combination of optional line drivers and terminators to provide the required sink current, polarity,
and drivel termination characteristics for each application. The 24 programmable 110 lines and Signal
ground lines are brought out to a 50-pin edge connector that mates with flat, woven, or round cable.

Bus Structure
The iSBC 80/30 has an internal bus for all on-board
memory and 110 operations and a system bus (i.e.,
the MULTIBUS) for all external memory and 110 operations. Local (on-board) operations do not tie up
the system bus, and allow true parallel processing
when several bus masters (i.e., DMA devices, other
single board computers) are used in a multimaster
scheme. A block diagram of the iSBC 80/30 functional components is shown in Figure 1.

RAM Capacity
The iSBC 80/30 contains 16K bytes of dynamic
readlwrite memory. All RAM read and write operations are performed at maximum processor speed.
Power for the on-board RAM may be provided on an
auxiliary power bus, and memory protect logic is included for RAM battery backup' requirements. The
iSBC 80/30 contains a dual port controller, which
provides dual port capability for the on-board RAM
memory. RAM accesses may occur from either the
iSBC 80/30 or from any other bus master interfaced
via the MULTIBUS. Since on-board RAM accesses
do not require the MULTIBUS, the bus is available
for any other concurrent operations (e.g., DMA data
transfers) requiring the use of the MULTIBUS. Dynamic RAM refresh is accomplished automatically

Universal Peripheral Interface (UPI)
The iSBC 80/30 provides sockets for a user supplied Intel 8041A/8741A Universal Peripheral Interface (UPI) chip and the associated line drivers and
.terminators for the UPl's I/O ports. The
8041A18741A is a single chip microcomputer containing a CPU, 1K bytes of ROM (8041 A) or EPROM
(8741 A), 64 bytes of RAM, 18 programmable I/O
lines, and an 8-bit timer. Special interface registers
included in the chip allow the 8041 A to function as a

8-66

inter

iSBC® 80/30 SINGLE BOARD COMPUTER

......

USER DESIGNATED

SERIAL

PERIPHERALS

DATA

CaMP...nlLE
DEVICE

INTERFACE

42 PROOItAIIIMAIU

PARALLEL 110 UNES

2 INTERRUPT
REQUEST LlNfS

.I"TERRUPT
REQUEST

LINES

MULTIIUS

280219-2

Figure 1. iSBC® 80/30 Single Board Computer Block Diagram
The 8251A provides full duplex, double buffered
transmit and receive capability. Parity, overrun, and
framing error detection are all incorporated in the
USART. The RS232C compatible interface on each
board, in conjunction with the USART, provides a
direct interface to RS232C compatible terminals,
cassettes, and asynchronous and synchronous modems. The RS232C command lines, serial data
lines, and signal ground line are brought out to a 26pin edge connector that mates with RS232C compatible flat or round cable.

slave processor to the iSBC 80/30's 8085A CPU.
The UPI allows the user to specifiy algorithms for
controlling user peripherals directly in the chip,
thereby relieving the 8085A for other system functions. The iSBC 80/30 provides an RS232C driver
and an RS232C receiver for optional connection to
the 8041A18741A in applications where the UPI is
programmed to handle simple serial interfaces.

Serial 1/0
A programmable communications interface using
the Intel 8251 A Universal Synchronous/ Asynchronous Receiver/Transmitter (USART) is contained on
the iSBC 80/30. A software selectable baud rate
generator provides the USART with all common
communication frequencies. The USART can be
programmed by the system software to select the
desired asynchronous or synchronous serial data
transmission technique (including IBM By-Sync).
The mode of operation (Le., synchronous or asynchronous), data format, control character format,
parity, and baud rate are all under program control.

Multimaster Capability
The iSBC 80/30 is a full computer on a single board
with resources capable of supporting a great variety of
OEM system requirements. For those applications
requiring additional processing capacity and the
benefits of multiprocessing (Le., several CPUs and/
or controllers logically sharing system tasks through
communication over the system bus), the iSBC
80/30 provides full MULTIBUS arbitration control
logic. This control logic allows up to three iSBC 80/
8-67

ISBC® 80/30 SINGLE BOARD COMPUTER

30's or other bus masters to share the system bus in
serial (daisy chain) priority fashion, and up to 16
masters to share the MULTIBUS with the addition of
an external priority network. The MULTIBUS arbitration logic operates synchronously with a MULTIBUS
clock (provided by the iSBC 80/30 or optionally connected directly to the MULTIBUS clock) while data is
transferred via a handshake between the master
and slave modules. This allows different speed controllers to share resources on the same bus, and
transfer via the bus proceed asynchronously. Thus,
transfer speed is dependent on transmitting and receiving devices only. This design prevents slow
master modules from being handicapped in their attempts to gain control of the bus, but. does not restrict the speed at which faster modules can transfer
data via the same bus. The most obvious applications for the master-slave capabilities of the bus are
multiprocessor configurations, high speed direct
memory access (DMA) operations, and high speed
peripheral control, but are by no means limited to
these three.

Programmable Timers
The iSBC 80/30 provides three independent, fully
programmable 16-bit interval timerslevent counters
utilizing the Intel 8253 Programmable Interval Timer.
Each counter is capabile of operating in either BCD
or binary modes. Two of these timerslcounters are
available to the systems designer to generate accurate time intervals under software control. Routing
for the outputs and gateltrigger inputs of two of
these counters is jumper selectable. The outputs
may be independently routed to the 8259A Programmable Interrupt Controller, to the 110 line drivers associated with the 8255A Programmable Peripheral
Interface, and to the 8041A18741A Universal Programmable Interface, or may be routed as inputs to
the 8255A and 8041A18741A chips. The gate/trigger inputs may be routed to 110 terminators associated with the 8255A or as output connections from
the 8255A. The third interval timer in the 8253 provides the programmable baud rate generator for the
iSBC 80/30 RS232C USART serial port. In utilizing
the iSBC 80/30, the systems designer simply configures, via software, each timer independently to meet
system requirements.

Interrupt Capability
The iSBC 80/30 provides vectoring for 12 interrupt
levels. Four of these levels are handled directly by
the interrupt processing capability of the 8085A CPU
and represent the four highest priority interrupts of
the iSBC 80/30. Requests are routed to the 808SA
interrupt inputs, TRAP, RST 7.5, RST 6.5, and RST
5.5 (ir:t decreasing order of priority) and each input
generates a unique memory address (TRAP: 24H;
RST 7.5: 3CH; RST 6.5: 34H; and RST 5.5: 2CH). An
8085A jump instruction at each of these addresses
then provides linkage to interrupt service routines
located independently anywhere in memory. All interrupt inputs with the exception of the trap interrupt
may be masked via software. The trap interrupt
should be used for conditions such as power-down
sequences which require immediate attention by the
8085A CPU. The Intel 8259A Programmable Interrupt Controller (PIC) provides vectoring for the next
eight interrupt levels., Operating mode and priority
aSSignments may be reconfigured dynamically via
software at any time during system operation. The
PIC accepts interrupt requests from the programmable parallel and serial 110 interfaces, the programmable timers, the system bus, or directly from peripheral equipment.
Interrupt requests may originate from 18 sources.
Two jumper selectable interrupt requests can be automatically generated by the programmable peripheral interface when a byte of information is ready to
be transferred to the CPU (Le., input buffer is full) or
a byte of information has been transferred to a peripheral device (i.e., output buffer is empty). Two
jumper selectable interrupt requests can be automatically generated by the USART when a character
is ready to be transferred to the CPU (i.e., receive
channel buffer is full), or a character is ready to be
transmitted (i.e., transmit channel data buffer is
empty). A jumper selectable request can be generated by each of the programmable timers and by the
universal peripheral interface, eight additional interrupt request lines are available to the user for direct
interface to user designated peripheral devices via
the system bus, and two interrupt request lines may
be jumper. routed directly from peripherals via the
parallel 110 driverlterminator section.

8-68

intJ

iSBC® 80/30 SINGLE BOARD COMPUTER

Power-Fail Control

Serial Communications Characteristics

Control logic is also included to accept a power-fail
interrupt in conjunction with the AC-Iow signal from
the iSBC 635 Power Supply or equivalent.

Synchronous: 5-8 bit characters; internal or external
character, synchronization; automatic sync insertion.

SPECIFICATIONS

Asynchronous: 5-8 bit characters; break character
generation; 1, 1%, or 2 stop bits; false start bit detection.

Word Size

Interfaces

Instruction: 8, 16, or 24 bits
Data: 8 bits

Parallel I/O: All Signals TIL compatible

Cycle Time

Interrupt Requests: All TIL compatible
Timer: All signals TIL compatible

MULTIBUS: All Signals TIL compatible

Serial I/O: RS232C compatible, data set
configuration

Basic Instruction Cycle: 1.45 JAoS
NOTE:
Basic instruction cycle is defined as the fastest instruction (Le., four clock cycles).

System Clock (8085A CPU)
2.76 MHz ±0.1%

Memory Addressing
Auxiliary Power

On-Board ROM/EPROM: 0-07FF (using 2708 or
2758 EPROMs); O-OFFF (using 2716 EPROMs); 01FFF {using 2716 EPROMs; 0-1 FFF (using 2732
EPROMs).

An auxiliary power bus is provided to allow separate
power to RAM for systems requiring battery backup
of read/write memory. Selection of this auxiliary
RAM power bus is made via jumpers on the board.

On-Board RAM: 16K bytes of dual port RAM starting
on a 16K boundary. One or two 8 K-byte segments
may be reserved for CPU use only.

Memory Protect

On-Board Read Only Memory: 8K bytes (sockets
only)
On-Board RAM: 16K bytes

An active-low TIL compatible memory protect signal
is brought out on the auxiliary connector which,
when asserted, disables read/write access to RAM
memory on the board. This input is provided for the
protection of RAM contents during system powerdown sequences.

1/0 Capacity

Physical Characteristics

Parallel: 42 programmable lines using one 8255A
(241/0 lines) and an optional 8041 Al8741 A (181/0
lines)

Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)

'Memory Capacity

Depth: 0.50 in. (1.27 cm)
Weight: 18 oz. (509.6 gm)

Serial: 2 programmable lines using one 8251A and
an optional 8041A18741A programmed for serial operation

8-69

iSBC® 80/30 SINGLE BOARD COMPUTER

Electrical Characteristics
DC POWER REQUIREMENTS
Current Requirements
Configuration
Without EPROM(1)
With 8041/8741(2)
RAMonly(3)

Vee = +5V
±5% (max)
Icc

= 3.5A

Voo = +12V
±5% (max)
IDD

= 220mA

Vaa = -5V
±5% (max)
Iss

= -

3.6A

220mA

3S0mA

20mA

2.SmA

VAA = -12V
±5% (max)
1M = 50mA
SOmA

NOTES:
1. Does not include power required for optional EPROM/ROM, 8041A18741A I/O drivers, and I/O terminators.
2. Does not include power required for optional EPROM/ROM. I/O drivers and I/O terminators.
3. RAM chips powered via auxiliary power bus.

Environmental Characteristics

ORDERING INFORMATION
Part Number Description
SBC 80/30
Single Board Computer with 16K
bytes RAM

Operating Temperature: O·C to SS·C

Reference Manual
98006118- iSBC 80/30 Single Board Computer
Hardware Reference Manual (NOT
SUPPLIED)

8-70

iSBC® 80/24A *

SINGLE BOARD COMPUTER

•

Compatible Replacement for
• Upward
iSBC 80/20-4 Single Board Computer
iii 8085A-2 CPU Operating at 4.8 or 2.4

•
•
•
•

MHz
Two iSBXTM Bus Connectors for iSBX
MULTIMODULETM Board Expansion
8K Bytes of Static Read/Write Memory
Sockets for Up to 32K Bytes of Read
Only Memory
48 Programmable Parallel I/O Lines
with Sockets for Interchangeable Line
Drivers and Terminators

•
•
•
•

Programmable Synchronous/
Asynchronous RS232C Compatible
Serial Interface with Software
Selectable Baud Rates
Full MULTIBUS® Control Logic for
Multimaster Configurations and System
Expansion
Two Programmable 16-Bit BCD or
Binary Timers/Event Counters
12 Levels of Programmable Interrupt
Control
Auxiliary Power Bus, Memory Protect,
and Power-Fail Interrupt Control Logic
Provided for Battery Backup RAM
Requirements

The Intel 80/24A Single Board Computer is a member of Intel's complete line of OEM microcomputer systems
which take full advantage of Intel's LSI technology to provide economical, self·contained computer·based
solutions for OEM applications. The CPU, system clock, iSBX bus interface, readlwrite memory, read only
memory sockets, 110 ports and drivers, serial communications interface, priority interrupt logic, and programmable timers all reside on the board. Full MULTIBUS interface logic is included to offer compatibility with the
Intel OEM Microcomputer Systems family of Single Board Computers, expansion memory options, digital and
analog 110 expansion boards, and peripheral and communications controllers.

142927-1

"The iSBC~ aO/24A Board is also manufactured under product code
Rico, Inc, and Intel Singapore, Ltd.

8-71

piSBC~

aO/24A and

siSBC~

aO/24A by Intel Puerto

October 1989
Order Number: 142927-005

intJ

iSBC® 80/24A SINGLE BOARD COMPUTER

FUNCTIONAL DESCRIPTION

Memory Addressing
The SOSSA-2 has a 16-bit program counter which
allows direct addressing of up to 64K bytes of memory. An external stack, located within any portion of
read/write memory, may be used as a last-in/firstout storage area for the contents of the program
counter, flags, accumulator, and all of the six general purpose registers. A 16-bit stack pointer controls
the addressing of this external stack. This stack provides subroutine nesting bounded only by memory
size.

Central Processing Unit
Intel's S-bit SOSSA-2 CPU is the central processor
for the iSBC SO/24A board operating at either 4.S or
2.4 MHz. The SOS5A-2 CPU is directly software compatible with the Intel SOSOA CPU. The SOS5A-2 contains .six S-bit general purpose registers and an accumulator. The six general purpose registers may be
addressed individually or in pairs, providing single
and double precision operators. Minimum instruction
execution time is S26 nanoseconds.

Memory Capacity
iSBXTM MULTIMODULETM On-Board
Expansion

The iSBC SO/24A board contains SK bytes of static
read/write memory using' an SK x 8 SRAMs. All
RAM read and write operations are performed at
maximum processor speed. Power for the on-board
RAM may be provided on an auxiliary power bus,
and memory protect logic is included for RAM battery backup requirements.

Two S-bit iSBX bus MULTIMODULE connectors are
provided for plug-in expansion of iSBX MULTIMODULE boards.

Four sockets are provided for up to 32K bytes of
nonvolatile read only memory on the iSBC SO/24A
board .

.m..

PROGRAMMABLI

COMPATIIILI!
DEvtCE

PARALLEL

110 LINES
.....L

DATA

;:.o::....~~IN'1't:R'ACE

POWER FAIL

I.TERllUPT~~ ~~

MULT1BUS. SYSTEM BUS

142927-2

Figure 1.ISBC® 80/24A Single Board Computer Block Diagram

S-72

inter

iSBC® 80/24A SINGLE BOARD COMPUTER

tion control logiC. This control logic allows up to
three iSBC 80/24A boards or other bus masters to
share the system bus in serial (daisy chain) priority
fashion, and up to 16 masters to share the MULTIBUS system bus with the addition of an external
priority network. The MULTIBUS arbitration logic operates synchronously with a MULTIBUS clock (provided by the iSBC 80/24A board or optionally connected directly to the MULTIBUS clock) while data is
transferred via a handshake between the master
and slave modules. This allows different speed controllers to share resources on the same bus since
transfers via the bus proceed asynchronously. Thus,
transfer speed is dependent on transmitting and
receiving devices only. This design provides slow
master modules from being handicapped in their attempts to gain control of the bus, but does not restrict the speed at which faster modules can transfer
data via the same bus. The most obvious applications for the master-slave capabilities of the bus are
multiprocessor configurations, high speed direct
memory access (DMA) operations, and high speed
peripheral control, but are by no means limited to
these three.

Parallel 110 Interface
The iSBC 80/24A board contains 48 programmable
parallel I/O lines implemented using two Intel 8255A
Programmable Peripheral Interfaces. The system
software is used to configure the I/O lines in any
combination of unidirectional input! output and bidirectional ports. Therefore, the I/O interface may be
customized to meet specific peripheral requirements. In order to take full advantage of the large
number of possible I/O configurations, sockets are
provided for interchangeable I/O line drivers and terminators. Hence, the flexibility of the I/O interface is
further enhanced by the capability of selecting the
appropriate combination of optional line drivers and
terminators to provide the required sink current, polarity, and drive/termination characteristics for each
application. The 48 programmable I/O lines and signal ground lines are brought out to two 50-pin edge
connectors that mate with flat, woven, or round cables.

Serial 110 Interface
A programmable communications interface using
the Intel 8251A Universal Synchronous/Asynchronous Receiver/Transmitter (USART) is contained on
the iSBC 80/24A board. A software selectable baud
rate generator provides the USART with all common
communication frequencies. The USART can be
programmed by the system software to select the
desired asynchronous or synchronous serial data
transmission technique (including IBM Bi-Sync). The
mode of operation (i.e. synchronous or asynchronous), data format, control character format, parity,
and baud rate are all under program control. The
8251A provides full duplex, double buffered transmit
and receive capability. Parity, overrun, and framing
error detection are all incorporated in the USART.
The RS232C compatible interface, in conjunction
with the USART, provides a direct interface to
RS232C compatible terminals, cassettes, and asynchronous and synchronous modems. The RS232C
command lines serial data lines, and signal ground
line are brought out to a 26-pin edge connector that
mates with RS232C compatible flat or round cable.

Programmable Timers
The iSBC 80/24A board provides three independent, fully programmable 16-bit interval timers/ event
counters utilizing the Intel 8254 Programmable Interval Timer. Each counter is capable of operating in
either BCD or binary modes. Two of these timers/
counters are available to the systems designer to
generate accurate time intervals under software
control. Routing for the outputs and gate/trigger inputs of two of these counters is jumper selectable.
The outputs may be independently routed to the
8259A Programmable Interrupt Controller, to the I/O
line drivers associated with the 8255A Programmable Peripheral Interface, or may be routed as inputs
to the 8255A chip. The gate/trigger inputs may be
routed to I/O terminators associated with the 8255A
or as output connections from the 8255A. The third
interval timer in the 8254 provides the programmable baud rate generator for the RS232C USART serial port. In utilizing the iSBC 80/24A board, the systems deSigner simply configures, via software, each
timer independently to meet system requirements.
Whenever a given time delay or count is needed,
software commands to the programmable timers/
event counters select the desired function. The contents of each counter may be read at any time during
system operation with simple read operations for
event counting applications, and special commands
are included so that the contents of each counter
can be read "on the fly".

Multimaster Capability
For those applications requiring additional processing capacity and the benefits of multiprocessing, the
iSBC 80/24A board provides full MULTIBUS arbitra-

8-73

inter

iSBC® 80/24A SINGLE BOARD COMPUTER

Interrupt Capability

Programmable Interrupt Modes

The iSBC 80/24A board provides vectoring for 12
interrupt levels. Four of these levels are handled directly by the interrupt processing capability of the
8085A-2 CPU and represent the four highest priority
interrupts of the iSBC 80/24A board. Requests are
routed to the 8085A-2 interrupt inputs-TRAP, RST
7.5, RST 6.5, and RST 5.5 (in decreasing order of
priority), each of which generates a call instruction to
a unique address·(TRAP: 24H; RST 7.5: 3CH; RST
6.5: 34H; and RST 5.5: 2CH). An 8085A-2 JMP instruction at each of these addresses then provides
linkage to interrupt service routines located independently anywhere in memory. All interrupt inputs with
the exception of the trap interrupt may be masked
via software. The trap interrupt should be used for
conditions such as power-down sequences which
require immediate attention by the 8085A-2 CPU.
The Intel 8259A Programmable Interrupt Controller
(PIC) provides vectoring for the next eight interrupt
levels. As shown in Table 3, a selection of four priority processing modes is available to the systems designer for use in designing request processing configurations to match system requirements. Operating
mode and priority assignments may be reconfigured·
dynamically via software at any time during system
operation. The PIC accepts interrupt requests from
the programmable parallel and serial 1/0 interfaces,
the programmable timers, the system bus, iSBX bus,
or directly from peripheral equipment. The PIC then
determines which of the incoming requests is of the
highest priority, determines whether this request is
of higher priority than the level currently being serviced, and, if appropriate, issues an interrupt to the
CPU. Any combination of interrupt levels may be
masked, via software, by storing a single byte in the
interrupt mask register of the PIC. The PIC generates a unique memory address for each interrupt
level. These addresses are equally spaced at intervals of 4 or 8 (software selectable) bytes. This 32 or
64-byte block may be located to begin at any 32 or
64-byte boundary in the 65,536-byte memory space.
A Single 8085A-2 JMP instruction at each of these
addresses then provides linkage to locate each interrupt service routine independently anywhere in
memory.

Mode

Operation

Fully nested

Interrupt request line priorities
fixed at 0 as highest, 7 as
lowest.

Autorotating

Equal priority. Each level, after
receiving service, becomes
the lowest priority level until
next interrupt occurs.

Specific
priority

System software assigns
lowest priority level. Priority of
all other levels based in
sequence numerically on this
assignment.

Polled

System software examines
priority-encoded system
interrupt status via interrupt
status register.

Interrupt Request Generation
Interrupt requests may originiate from 23 sources.
Two jumper selectable interrupt requests can be
generated by each iSBX MULTIMODULE board.
Two jumper selectable interrupt requests can be automatically generated by each programmable peripheral interface when a byte of information is ready
to be transferred to the CPU (i.e., input buffer is full)
or a byte of information has been transferred to a
peripheral device (i.e., output buffer is empty). Three
jumper selectable interrupt requests can be automatically generated by the USART when a character
is ready to be transferred to the CPU (i.e., receiver
channel buffer is full), a character is ready to be
transmitted (I.e., th~ USART is ready to accept a
character from the CPU), or when the transmitter is
empty (i.e., the USART has no character to transmit). A jumper selectable request can be generated
by each of the programmable timers. Nine interrupt
request lines are available to the user for direct interface to user designated peripheral devices via the
MULTIBUS system bus. A power-fail signal can also
be selected as an interrupt source.

Power-Fail Control
A power~fail interrupt may be detected through the
AC-Iow signal generated by the power supply. This
Signal may be configured to interrupt the 8085A-2
CPU to initiate an orderly power down instruction sequence.

8-74

inter

ISBC@ 80/24A SINGLE BOARD COMPUTER

SPECIFICATIONS

Serial Communications Characteristics
Synchronous -

5-8 bit characters; internal or external character synchronization;
automatic sync insertion
Asynchronous- 5-8 bit characters; break character generation; 1, 1%, or 2 stop
bits; false start bit detectors

Word Size
Instruction- 8, 16 or 24 bits
Data
-8 bits

Cycle Time
Interfaces
BASIC INSTRUCTION CYCLE

MULTIBUS

- All signals TTL compatible
- All signals TTL compatible
- All signals TTL compatible
- RS232C compatible, configurable as a data set or data terminal
Timer
- All signals TTL compatible
Interrupt Requests- All TTL compatible

826 ns (4.84 MHz operating frequency)
1.65 ,...s (2.42 MHz operating frequency)

iSBXBus
Parallel I/O
Serial I/O

NOTE:
Basic instruction cycle is defined as the fastest instruction (i.e., four clock cycles).

Memory Addressing
System Clock (8085A-2 CPU)

ON-BOARD EPROM

4.84 or 2.42 MHz ± 0.1 % (jumper selectable)

O-OFFF using 2708, 2758 (1 wait state)
0-1 FFF using 2716 (1 wait state)
0-3FFF using 2732 (1 wait state)
using 2732A (no wait states)
0-7FFF using 2764A (no wait states)

Auxiliary Power
An auxiliary power bus is provided to allow separate
power to RAM for systems requiring battery backup
of read/write memory. Selection of this auxiliary
RAM power bus is made via jumpers on the board.

ON-BOARD RAM
EOOO-FFFF

Memory Protect

NOTE:
Default configuration-may be reconfigured to top
end of any 16K boundary.

An active-low TTL compatible memory protect signal
is brought out on the auxiliary connector which,
when asserted, disables read/write access to RAM
memory on the board. This input is provided for the
protection of RAM contents during system powerdown sequences.

Memory Capacity
ON-BOARD EPROM

Physical Characteristics

32K bytes (sockets only)

Width:
Height:
Depth:
Weight:

ON-BOARD RAM
8K bytes

8-75

12.00 in. (30.48 cm)
6.75 in. (17.15 cm)
0.50 in. (1.27 cm)
12.64 oz. (354 gm)

inter

iSBC® 80/24A SINGLE BOARD COMPUTER

Electrical Characteristics
DC POWER REQUIREMENTS
Current Requirements
, Configuration

Vee = +5V
±5% (max)

Voo = +12V
±5% (max)

Vaa = -5V
±5% (max)

VAA = -12V
±5% (max)

Without
EPROM(1)

2.66A

40mA

20mA

120mA

RAMOnly(2)

O.01A

With
iSBC530(3)

2.66A

140mA

With4K
EPROM(4)
(using 2708)

3.28A

300mA

With4K
"EPROM(4)
(using 2758)

3.44A

40mA

20mA

With8K
EPROM(4)
(using 2716)

3.44A

40mA

20mA

With 16K
EPROM(4)
(using 2732A)

3.46A

40mA

20mA

With'32K
EPROM(4)
(using 2764A)

3.42A

40mA

20mA

180mA

20mA

NOTES:
1. Does not include power for optional EPROM, I/O drivers, and I/O terminators.
2. RAM chips powered via auxiliary power bus.
3. Does not include power for optional EPROM, I/O drivers, I/O terminators. Power for iSBC 530
Adapter is supplied via serial port connector.
4. Includes power required for four EPROM chips, and I/O terminators installed for 16 I/O lines; all
terminators inputs low.
'

Environmental Characteristics

ORDERING INFORMATION

Operating Temperature: O·C to 55·C

Part Number Description
SBC 80/24A Single Board Computer

Reference Manual
148437-001- iSBC 80/24A Single Board Computer
Hardware Reference Manual (NOT
SUPPLIED)

8-76

iSBC® 80/10B*
SINGLE BOARD COMPUTER

•
•
•1
•
•

8080A Central Processing Unit

One iSBXTM Bus Connector for iSBXTM
MULTIMODULETM Board Expansion
K Byte of Read/Write Memory with
Sockets for Expansion up to 4K Bytes

Sockets for up to 16K Bytes of Read
Only Memory
48 Programmable Parallel I/O Lines
with Sockets for Interchangeable Line
Drivers and Terminators

•

Programmable Synchronous/
Asynchronous Communications
Interface with Selectable RS232C or
Teletypewriter Compatiblity

•
•
•
•

Single Level Interrupt with 11 Interrupt
Sources
Auxiliary Power Bus and Power-Fail
Interrupt Control Logic for RAM
Battery Backup
1.04 Millisecond Interval Timer
Limited Master MULTIBUS® Interface

The Intel iSBC 80/1 OB board is a member of Intel's complete line of OEM microcomputer systems which take
full advantage of Intel's LSI technology to provide economical, self-contained computer-based solutions for
OEM applications. The CPU, system clock, iSBX bus interface, read/write memory, read only memory sockets,
I/O ports and drivers, serial communications interface, bus control logic, and drivers all reside on the board.

2B0217-1

'The iSBC" BOll0B is also manufactured under product code piSBC" BOll0B by Intel Puerto Rico, Inc.

8-77

September 1989
Order Number: 280217-003

iSBC® 80/10B COMPUTER

......,

-'A~0

COIIPATIIlLE
DEVICE

YROl

DAYAICONTAOL
tNTERFACE

INTERFACE

BAUD RATE'

1 CM MSEC

DRIYERI

SELECTOR

INTERYAL

TERMINATOR

(JUMPERS)

nliER

INTERFACE

l J

----,

7, ,

...

ROMIEPROM

(SOCKETS TO

CQIIMUNICAnONS

(SOCKETS)

4K. I)

INTERFACE IUSART)

()

I
I

Isa.. IUS

MULTIMODULE

CONNECTOR

I
I

L_-J~ __I\-

I
I
I

_.J

,ill

INTERRUPT SELECTOR

I.lUMPERS)

PROGRAMMABLE
PERIPHERAL
INTERFACES

CPU

()
MULnaus
INTERFACE

PROGRAMMABLE

ON-BOARD SYSTEM IUS

I
I
I
I
I

POWEA
'AIL

INTERRUPT

SELECTED

1k.,RAM

'Yr~

'f~~~()---

PARALLEL 110 LINES

IIIUX

USER DESIGNATED

UK MULTIMOOUlE
10ARD

....OQ........l~O

O_·'Al

DATAICON
INTERFACE

USER

DESIGNATED
PERIPHERALS

MULT,8USO SYSTEM IUS

....
280217-2

Figure 1. iSBC® 80/10B Single Board Computer Block Diagram

FUNCTIONAL DESCRIPTION

Memory Addressing

Intel's 8-bit n-channel MOS 8080A CPU, fabricated
on a single LSI chip, is the central processor for the
iSBC 80/10B board. The 8080A contains six 8-bit
general purpose registers and an accumulator. The
six general purpose registers may be addressed individually or in pairs, providing both Single and double precision operators. A block diagram of iSBC
80/10B board functional components is shown in
Figure 1.

The 8080A has a 16-bit program counter which allows direct addressing of up to 64K bytes of memory. An external stack, located within any portion of
read/write memory, may be used as a last-in/firstout storage area for the contents of the program
counter, flags, accumulator, and all of the six general purpose registers. A 16-bit stack pointer controls
the addressing of this external stack. This stack provides subroutine' nesting bounded only by memory
size.

iSBXTM Bus MULTIMODULETM Board
Expansion
One iSBX bus connector interface is provided to accomplish plug-in expansion with any iSBX MULTIMODULE board.

8-78

iSBC® 80/10B COMPUTER

a direct interface to teletypes, CRTs, RS232C compatible cassettes, and asynchronous and synchronous modems. The RS232C or TIV command lines,
serial data lines, and signal ground lines are brought
out to a 26-pin edge connector that mates with
RS232C compatible flat or round cable.

Memory Capacity
The iSBC 80/10B board contains 1K bytes of read/
write static memory. In addition, sockets for up to 4K
bytes of RAM memory are provided on board. Read/
write memory may be added in 1K byte increments.
Sockets for up to 16K bytes of nonvolatile read-onlymemory are provided on the board. All on-board
RAM, ROM or EPROM read operations are performed at maximum processor speed.

Interrupt Capability
Interrupt requests may originate from 11 sources.
Two jumper selectable interrupt requests can be automatically generated by the programmable peripheral interface when a byte of information is ready to
be transferred to the CPU (i.e., input buffer is full) or
a byte of information has been transferred to a peripheral device (Le., output buffer is empty). Three
jumper selectable interrupt requests can be automatically generated by the USART when a character
is ready to be transferred to the CPU (Le., receive
channel buffer is full), a character is ready to be
transmitted (Le., the USART is ready to accept a
character from the CPU), or when the transmitter is
empty (Le., the USART has no character to transmit). These five interrupt request lines are all maskable under program control. Two interrupt request
lines may be interfaced directly to user designated
peripheral devices; one via the MULTIBUS system
bus and the other via the I/O edge connector. One
jumper selectable interrupt request may be interfaced to the power-fail interrupt control logic. One
jumper selectable interrupt request may originate
from the interval timer. Two general purpose interrupt requests are jumper selectable from the iSBX
interface. These two signals permit a user installed
MULTIMODULE board to interrupt to 8080A CPU.
The eleven interrupt request lines share a single
CPU interrupt level. When an interrupt request is
recognized, a restart instruction (RESTART 7) is
generated. The processor responds by suspending
program execution and executing a user defined interrupt service routine.

Parallel I/O Interface
The iSBC 80/10B board contains 48 programmable
parallel I/O lines implemented using two Intel 8255A
programmable peripheral interfaces. The system
software is used to configure the I/O lines in any
combination of unidirectional input/output, and bidirectional ports. In order to take full advantage of the
large number of possible I/O configurations, sockets
are provided for interchangeable 110 line drivers and
terminators. The flexibility of the I/O interface is further enhanced by the capability of selecting the appropriate combination of optional line drivers and
terminators to provide the required sink current, polarity, and drive/termination characteristics for each
application. The 48 programmable I/O lines and signal ground lines are brought out to two 50-pin edge
connectors that mate with flat cable or round cable.

Serial I/O Interface
A programmable communications interface using
the Intel 8251A Universal Synchronous/Asynchronous Receiver/Transmitter (USART) is contained on
the board. A jumper selectable baud rate generator
provides the USART with all common communications frequencies. The USART can be programmed
by the system software to select the desired synchronous or asynchronous serial data transmission
technique (including IBM Bi-Sync). The mode of operation (Le., synchronous or asynchronous), data
format, control character format and parity are all
under program control. The 8251A provides full duplex, double-buffered transmit and receive capability. Parity, overrun, and framing error detection are all
incorporated in the USART. The inclusion of jumper
selectable TIV or RS232C compatible interfaces on
the board, in conjunction with the USART, provides

Power-Fail Control
A power-fail interrupt may be detected through the
AC-Iow signal generated by the power supply. This
signal may be configured to interrupt the 8080A CPU
to initiate an orderly power down instruction sequence.

8-79

iSBC® 80/10B COMPUTER

Interval Timer

1/0 Capacity

A 1.04 millisecond timer is available for interval interrupts or as a clock output to the parallel 110 connector. The timer output is jumper selectable to the programmable parallel interface, the parallel 1/0 connector (J1), or directly to the 8080A CPU.

Parallel:

48 programmable lines

Serial:
MULTIMODULE:

1 transmit, 1 receive
1 iSBX Bus MULTIMODULE
Board

SPECIFICATIONS

Serial Communications Characteristics
Synchronous:

Word Size
Instruction: 8, 16, or 24 bits
'
Data: 8 bits

5-8 bit characters; internal or external character synchronization;
automatic sync insertion

Asynchronous: 5-8 bit characters; break character
generation; 1, 1%, or 2 stop bits;
false start bit detectors

Cycle Time
Interrupts

Basic Instruction Cycle: 1.95 J.tS

Single-level with on-board logic that automatically
vectors the processor to location 38H using a restart
instruction (RESTART 7). Interrupt requests may
originate from user specified 1/0 (2); the programmable peripheral interface (2); the iSBX MULTIMOD·
ULE board (2); the programmable communications
interface (3); the power fail interrupt (1); or the interval timer (1).

NOTE:
Basic instruction cycle is defined as the fastest instruction (i.e., four clock cycles).

Memory Addressing
On-Board ROM/EPROM
O-OFFF using 2708, 2758
0-1FFF using 2716
0-3FFF using 2732

Interfaces

On-Board RAM
3COO-3FFF with no RAM expansion
3000-3FFF with 2114A-5 expansion

MULTIBUS:

All signals TIL compatible

iSBX Bus:
Parallel 1/0:

All signals TIL compatible
All signals TIL compatible

Serial 1/0:

RS232C or a 20 mil current
loop TIY interface Oumper selectable)

Interrupt Requests:

All TIL compatible (active-low)

Memory Capacity
On-Board ROMIEPROM
16K bytes (sockets only)

Clocks

On-Board RAM
1K byte with user expansion in 1K increments to
4K byte using Intel 2114A-5 RAMs.

System Clock: 2.048 MHz ± 0.1 %
Interval Timer: 1.042 ms ± 0.1 % (959.5 Hz)

Off-Board Expansion
Up to 64K bytes using user specified combina-'
tions of RAM, ROM, and EPROM.

Physical Characteristics
Width:

12.00 in (30.48 cm)

Height: 6.75 in. (17.15 cm)
Depth: 0.05 in. (1.27 cm)
Weight: 14 oz. (397.3 gm)

8-80

iSBC® 80/10B COMPUTER

Electrical Characteristics
DC Power Requirements
Voltage
Vcc
Voo
Vee
VAA

=
=
=
=

+5V ±5%
+12V ±5%
-5V ±5%
-12V ±5%

Without
EPROM(1)

=
=
lee =
IAA =

Icc

100

2.0A(4)
150 mA
2mA
175 mA

With 2708
EPROM(2)

With 2758, 2716,
or 2732 EPROM(3)

Power Down Requirements
(RAM and Support Circuit)

3.1A
400mA
200mA
175mA

3.46A
150mA
2mA
175mA

84mA + 140!"AlK(2114A-5)
Not Required
Not Required
Not Required

NOTES:
1.
2.
3.
4.

Does not include power required for optional ROMIEPROM, 1/0 drivers, or 1/0 terminators.
With four Intel 2708 EPROMS and 2200/3300 for terminators, installed for 48 input lines. All terminator inputs low.
Same as #2 except with four 2758s, 2716s, or 2732s installed.
Icc shown without RAM supply current. For 2114-5 add 140 mA per K byte to a maximum of 560 mAo

Environmental Characteristics

ORDERING INFORMATION

Operating Temperature: O·C to SS·C

Part Number Description
iSBC80/10B Single Board Computer

Reference Manual
9803119-01- iSBC 80/10B Single Board Computer
Hardware Reference Manual (NOT
SUPPLIED).
.

8-81

iSBC® 337A
MULTIMODULETM NUMERIC
DATA PROCESSOR
• Supports Seven Data Types Including
Single and Double Precision Integer
and Floating Point
• Fully Supported In the Multi-Tasking
Environment of the IRMXTM I Operating
System

• High Speed Fixed and Floating Point
Functions for ISBC@ Boards
• Extends Host CPU Instruction Set with
Arithmetic, Logarithmic,
Transcendental and Trigonometric
Instructions
• MULTIMODULETM Option Containing
8087 Numeric Data Processor

The Intel iSBC(8) 337A MULTIMODULETM Numeric Data Processor offers high performance numerics support
for iSBC 86 and iSBC 88 Single Board Computer users, for applications including simulation, instrument
automation, graphics, signal processing and business systems. The coprocessor interface between the 8087
and the host CPU provides a simple means of extending the instruction set with over 60 additional numeric
instructions supporting seven additional data types.

280077-1

8-82

September 1989
Order Number: 280077-002

intJ

iSBC 337A MULTIMODULE BOARD

The iSBC 337A MULTIMODULE Numeric Data Processor (NDP) provides arithmetic and logical instruction extensions to the 86/88 families. The instruction
set consists of arithmetic, transcendental, logical,
trigonometric and exponential instructions which can
all operate on seven different data types. The data
types are 16-, 32-, and 64-bit integer, 32- and 64-bit
floating point, 18 digit packed BCD and 80-bit temporary.

All synchronization and timing signals are provided
via the coprocessor interface with the host CPU.
The two processors also share a common addressldata bus. The NDP component is capable of
recognizing and executing NDP numeric instructions
as they are fetched by the host CPU. This interface
allows concurrent processing by the host CPU and
the NDP. It also allows NDP and host CPU instructions to be intermixed in any fashion to provide the
maximum overlapped operation and the highest aggregate performance.

Coprocessor Interface

High Performance and Accuracy

The coprocessor interface between the host CPU
and the iSBC 337A MULTIMODULE provides easy
to use and high performance math processing. Installation of the iSBC 337A is simply a matter of removing the host CPU from its socket, installing the
iSBC 337A MULTIMODULE into the host's CPU
socket, and reinstalling the host CPU chip into the
socket provided for it on the iSBC 337A MULTIMODULE (see Figure 1).

The 80-bit wide internal registers and data paths
contribute significantly to high performance and minimize the execution time difference between single
and double precision floating point formats. This 80bit architecture provides very high resolution and accuracy.

OVERVIEW

This precision is complemented by extensive exception detection and handling. Six different types of
exceptions can be reported and handled by the
NDP. The user also has control over internal precision, infinity control and rounding control.

HOST CPU

CONNECTOR FOR
INTERRUPT REQUEST
FROM ISBC· JJ7A

280077-2

Figure 1. iSBC® 337A MULTIMODULE Installation

8-83

iSBC 337A MULTIMODULE BOARD

SYSTEM CONFIGURATION
As a coprocessor to the Host CPU, the NDP is wired
in parallel with the CPU. The CPU's status and
queue status lines enable the NDP to monitor and
decode instructions in synchronization with the CPU
and without any CPU overhead. Once started, the
NDP can process in parallel with and independent of
the host CPU. For resynchronization, the NDP's
BUSY signal informs the CPU that the NDP is executing an instruction and the CPU WAIT instruction
tests this signal to insure that the NDP is ready to
execute subsequent instructions.
The NDP can interrupt the CPU when it detects an
error or exception. The interrupt request line is routed to the CPU through an 8259A Programmable Interrupt Controller. This interrupt request signal is
brought down from the iSBC 337A MULTIMODULE
to the single board computer through a single pin
connector (see Figure 1). The signal is then routed
to the interrupt matrix for jumper connection to the
8259A Interrupt Controller. Other iAPX designs may
use a similar arrangement, or by masking off the
CPU "READ" pin from the iSBC 337 A socket, provisions are made to allow the now vacated pin of the
host's CPU socket to be used to bring down the interrupt request signal for connection to the base
board and then to the 8259A.

FUNCTIONAL DESCRIPTION
The NDP is internally divided into two· processing
elements, the control unit (CU) and the numeric execution unit (NEU), providing concurrent operation of
the two units. The NEU executes all numeric instructions, while the CU receives and decodes instructions, reads and writes memory operands and executes processor control instructions.

the NDP control unit determines when a 8086-2 instruction is being fetched. The CU taps the bus in
parallel with the CPU and obtains that portion of the
data stream.
After decoding the instruction, the host executes all
opcodes but ESCAPE (ESC), while the NDP executes only the ESCAPE class instructions. (The first
five bits of all ESCAPE instructions are identical).
The CPU does provide addressing for ESC instructions however.
An NDP instruction either will not reference memory,
will require loading one or more operands from
memory into the NDP, or will require storing one or
more operands from the NDP into memory. In the
first case, a non-memory reference escape is used
to start NDP operation. In the last two cases, the CU
makes use of a "dummy read" cycle initiated by the
CPU, in which the CPU calculates the operand address and initiates a bus cycle, but does not capture
the data. Instead, the CPU captures and saves the
address which the CPU places on the bus. If the
instruction is a load, the CU additionally captures the
data word when it becomes available on the local
data bus. If data required is longer than one word,
the CU immediately obtains the bus from the CPU
using the request/grant protocol and reads the rest
of the information in consecutive bus cycles. In a
store operation, the CU captures and saves the
store address as in a load, and ignores the data
word that follows in the "dummy read" cycle. When
the NDP is ready to perform the store, the CU obtains the bus from the CPU and writes the operand
starting at the specified address.

Numeric Execution Unit
The NEU executes all instructions that involve the
register stack. These include arithmetic, logical,
transcendental, constant and data transfer instructions. The data path in the NEU is 80 bits wide (64
fraction bits, 15 exponent bits and a sign bit) which
allows internal operand transfers to be performed at
very high speeds.

Control Unit
The CU keeps the NDP operating in synchronization
with its host CPU. NDP instructions are intermixed
with CPU instructions in a single instruction stream.
The CPU fetches all instructions from memory; by
monitoring the status signals emitted by the CPU,

When the NEU begins executing an instruction, it
activates the NDP BUSY signal. This signal is used
in conjunction with the CPU WAIT instruction to resynchronize both processors when the NEU has
completed its current instruction.

8-84

inter

iSBC 337A MULTIMODULE BOARD

SPECIFICATIONS

Environmental Characteristics

Physical Characteristics

Operating Temperature-O°C to 55°C with 200 linear feet/minute airflow

Width- 5.33 cm (2.100")
Length- 5.08 cm (2.000")
Height-1.82 cm (0.718")
iSBC 337 A board + host board
Weight-17.33 grams (0.576 oz.)

Relative Humidity-Up to 90% R.H. without condensation.

Reference Manual
147163-001-iSBC 337A MULTIMODULE Numeric
Data Processor Hardware Reference Manual (NOT
SUPPLIED WITH MULTIMODULE BOARD).

Electrical Characteristics
DC Power Requirements
Vee = 5V ±5%
Icc = 475 mA max.
Icc = 350 mA typo

ORDERING INFORMATION
Part Number
SBC 337A

8-85

Description
MULTIMODLE
Processor

Numeric

Data

MULTIBUS® I
Memory Expansion Boards

•In'ell
+.-I®

iSBC® MM01, MM02, MM04, MM08*
HIGH PERFORMANCE MEMORY MODULES

High Speed Parity Memory
• Provides
Expansion for Intel's iSBC® 386/2X,

to Provide up to 16M Bytes
• Stackable
of High Speed Memory for MULTIBUS I
and MULTIBUS II CPU Boards

iSBC 386/3X and iSBC 386/1XX
CPU Boards

•
Independent Read/Writes
• Supports
Easily Installed
•

Supports 32-Bit, 16-Bit and 8-Bit Data
Paths

in 1M, 2M, 4M, and 8M Byte
• Available
Sizes
• 32 Bits Wide with Byte Parity

The iSBC MM01, iSBC MM02, iSBC MM04, and iSBC MM08 DRAM memory modules are members of Intel's
complete line of iSBC memory and I/O expansion boards. The MM-Series of memory modules use a dedicated interface to maximize CPU/memory performance. The iSBC MM series of memory modules have been
designed to provide both the on-board and expansion memory for the iSBC 386/2X, the iSBC 386/3X and the
iSBC 386/1 XX CPU Boards.
The modules contain (respectively) 1M byte, 2M, 4M, and 8M bytes of read/write memory using surface
mounted DRAM components (see Figure 1).
Due to the high speed interface of the memory modules, they are ideally suited in applications where memory
performance is critical.

280346-1

Figure 1. iSBC® MM08 Memory Module
·The iSBC® MM01, MM02, MM04, MM08 Memory Modules are also manufactured under product code piSBC® MM01,
MM02, MM04, MM08 by Intel Puerto Rico, Inc.

9-1

September 1989
Order Number: 280346-002

inter

iSBe® MM01, MM02, MM04, MMOB MODULES

FUNCTIONAL DESCRIPTION

Installation

The iSBC MMxx memory modules' are easily installed by the user. Each module includes all necessary connectors, screws, and other hardware for installation, either as a second stacked module or as a
replacement for a module with less memory.

SPECIFICATIONS
Memory Access Capabilities

Word Size Supported

The dynamic RAM memory of the memory modules
is accessed through the dedicated memory module
interface.

8-, 16-, or 32-bits '

Memory Size

The MM memory module is designed for direct
transfer of data between the CPU and the memory
module without accessing the MULTIBUS interface.

iSBC
iSBC
iSBC
iSBC

MM01/MM02/MM04/MM08
Memory Size

MM01
MM02
MM04
MM08

1,048,576
2,097,152
4,194,304
8,388,608

bytes
bytes
bytes
bytes

Access Time (All Densities)

The iSBC MM01, iSBC MM02, iSBC MM04, and
iSBC MM08 modules can be stacked On the CPU
baseboard in any combination.

Read/Write -

107 ns (max)

Cycle Time (All Densities)
Read/Write -

200 ns (min)

Parity
Power Requirements

Voltage -5 VDC ±5%
Memory addressing for the iSBC MMxx memory
modules is controlled by the host CPU board over
the memory module interface. The maximum system
RAM size is 16M Bytes.

Memory Function
The module protocol supports standard dynamic
RAM READ, WRITE, RAS· only REFRESH cycles,
ana CAS· before RAS· REFRESH.

9-2

intJ

iSBC® MM01, MM02, MM04, MM08 MODULES

Top View

ISBC®MMxx
MEMORY MODULE

4.25"
7.05"

CPU BASEBOARD

CONNECTOR
OUTLINE

Ir-------~I

~-------~

L....----.-I
11-'---4.175" - - - t . 1

.1
280346-2

Side View
ISBC®MMxx
MEMORY MODULE

0.B47"
(:to.023)
CPU BASEBOARD

280348-3

Single iSBC® MMxx Memory Module

Side View
iSBC@MMxx
MEMORY MODULES
STIFFENER

1.564"
(:to.033)

0.525 INCH STACKING CONNECTOR
STANDOFFS

0.625 INCH BASEBOARD CONNECTOR
CPU BASEBOARD

280346-4

Stacked iSBC® MMxx Memory Modules

9-3

ISBC® MM01, MM02, MM04, MM08 MODULES

Environmental Requirements

ORDERING INFORMATION

Operating Temperature -

Part Number

Storage Temperature -

O·C to 60·C
40·C to

+ 75·C

Description

iSBCMM01

1M Byte RAM Memory Module

iSBCMM02

2M Byte RAM Memory Module

Cooling Requirement - 3 cubic feet per minute of
airflow at an ambient temperature of O·C to 60·C

iSBCMM04

4M Byte RAM Memory Module

iSBCMM08

8M Byte RAM Memory Module

Operating Humidity without condensation

The Memory Modules ship with the required hardware (connectors, mounting screws, stand-ofts, etc.)
to stack a second module on the module already
mounted on the base CPU board.

To 95% relative humidity

Physical Dimensions
Module Alone:
Width -

4.250 inches (10,795 cm)

Length -

4.175 inches (10,604 cm)

Height -

0.500 inches (1,270 cm)

Weight -

iSBC MM01/MM04: 2.5 ounces (70.0 gm)
iSBC MM02/MM08: 3.5 ounces (110.0 gm)

9-4

-ntel®

iSBC® MM01FP, MM02FP, MM04FP, MM08FP'
HIGH PERFORMANCE MEMORY MODULES

•

Provides High Speed Parity Memory
Expansion for Intel's iSBC® 386/2X,
iSBC 386/3X and iSBC 386/1XX CPU
Boards

•

Available in 1M, 2M, 4M, and 8M Byte
Sizes
32 Bits Wide with Byte Parity

•

II Stackable to Provide up to 16M Bytes

of High Speed Memory for MULTIBUS I
and MULTIBUS II Boards
Supports 32-Bit, 16-Bit and 8-Bit Data
Paths
II Supports Independent Read/Writes
Easily Installed

•

The iSBC MMOX and iSBC MMOXFP DRAM memory modules are members of Intel's complete line of iSBC
memory and I/O expansion boards. The MM-Series of memory modules use a dedicated memory interface to
maximize CPU/memory performance.

Figure 1. iSBC® MM08FP Memory Module

281010-1

The iSBC@ MM01FP, MM02FP, MM04FP, MMOBFP memory modules are also manufactured under product code piSBC@
MM01 FP, MM02FP, MM04FP, MMOBFP by Intel Puerto Rico, Inc.

9-5

September 1989
Order Number: 281010-001

inter

iSBC@ MM01FP, MM02FP, MM04FP, MM08FP MODULES

FUNCTIONAL DESCRIPTION

Memory Function

The iSBC MM-Series provide high performance, 32bit parity DRAM memory for the MULTIBUS I and
MULTIBUS " boards. These CPU boards come standard with one MM-Series module installed, with
memory expansion available through the addition of
a second stackable iSBC MM-Series module.

The module protocol supports standard dynamic
RAM READ, WRITE, RAS' only REFRESH cycles,
and CAS' before RAS' REFRESH.

Installation
The iSBC MM-Series memory modules are easily installed by the user. Each module includes all necessary connectors, screws, and other hardware for installation, either as a second stacked module or as a
replacement for a module with less memory.

Memory Access Capabilities
The dynamic RAM memory of the memory modules
is accessed through the dedicated memory module
interface.

SPECIFICATIONS

The MM memory module is designed for direct
, transfer of data between the CPU and the memory
module without accessing the MULTISUS interface.

Word Size Supported
MM01/MM02/MM04/MM08
Memory Size

8-, 16-, or 32-bits

The iSBC MM01, iSBC MM02, iSBC MM04, and
iSBC MM08 modules can be stacked on the CPU
baseboard in any combination.

Memory Size
iSBC
iSBC
iSBC
iSBC

Data Bus Structure
The MM-Series memory modules use a 32-bit wide
data path with storage for byte parity that can accommodate 8-bit byte, -16-bit or 32-bit word data
transfers. In addition, the data path is capable of
independent byte operations. This means that one
byte can be written while the other three bytes (or
any other combination) can be read.

MM01
MM02
MM04
MM08

1,048,576 bytes
2,097,152 bytes
4,194,304 bytes
8,388,608 bytes

Access Time (All Densities)
Read/Write -

107 ns (max)-M!\IIOX

Read/Write -

88 ns (max)-MMOXFP

Power Requirements
Parity

Voltage -5 VDC ±5%

Memory addressing for the iSBC MM-Series memory
modules is controlled by the host CPU board over
the memory module interface. The maximum system
RAM size is 16M Bytes.

9-6

inter

iSBC® MM01FP, MM02FP, MM04FP, MM08FP MODULES

Top View

.. ------- ..
I

7.05"

CONNECTOR
OUTLINE

CPU BASEBOARD

4.25"

ISBC®MMxx
MEMORY MODULE

--------.....

281010-2

Side View
ISBC®MMxx
MEMORY MODULE

STANDOFF

0.847"
(:to.023)

CPU BASEBOARD

281010-3

Single iSSC® MMxx Memory Module

Side View
ISBCt!> MMxx
MEMORY MODULES
STIFFENER

1.564"
(:to.033)

0.525 INCH STACKING CONNECTOR
STANDOFFS

0.625 INCH BASEBOARD CONNECTOR
CPU BASEBOARD

281010-4

Stacked iSSC® MMxx Memory Modules

9-7

ISBC@ MM01FP, MM02FP, MM04FP, MM08FP MODULES

Environmental Requirements

ORDERING INFORMATION

Operating Temperature -

Part Number

ooe to 600 e

+ 75°e

Storage Temperature -

400 e to

Operating Humidity without condensation

To 95% relative humidity

iSBC MM02FP 2M Byte Fast Page Memory Module
iSBC MM03FP 4M Byte Fast Page Memory Module
iSBC MM04FP 8M Byte Fast Page Memory Module
The Memory Modules ship with the required hardware (connectors, mounting screws, stand-offs, etc.)
to stack a second module on the module already
mounted on the base CPU board.

Physical Dimensions
Module Alone:
Width -

4.250 inches (10,795 cm)

Length -

4.175 inches (10,604 cm)

Height -

0.500 inches (1,270 cm)

Weight -

Description

iSBC MM01 FP 1M Byte Fast Page Memory Module

iSBC MM01/MM04: 2.5 ounces (70.0 gm)
iSBC MM02/MM08: 3.5 ounces (110.0 gm)

9-8

intel®
iSBC® 012EX, 010EX, 020EX, and 040EX*
HIGH PERFORMANCE RAM BOARDS

•o

•
•
•
•

Wait States at 8 MHz Performance
with the iSBC® 286/10A,
iSBC 286/12 Board

•
•

Dual Port Capability Via MULTIBUS®
and High Speed Synchronous Interface
Configurable to Function Over
iLBXTM Bus

On-Board Parity Generator/Checker
Independently Selectable Starting and
Ending Addresses
16 Megabyte Addressing Capability
512K Byte, 1024K Byte, 2048K Byte,
and 4096K Byte Densities Available

The iSBC 012EX, iSBC 010EX, iSBC 020EX, and iSBC 040EX RAM memory boards are members of Intel's
complete line of iSBC memory and I/O expansion boards. The EX boards are dual ported between the
MULTIBUS interface and one of two types of dedicated memory buses. The dedicated buses are the iLBX bus
and a high speed interface. The EX series of RAM-boards can be configured to be accessed over the iLBX
bus, as well as MULTIBUS bus, to provide memory support for the iSBC 286/10 board, iSBC 186/03A, or iSBC
386/12. The EX boards are default configured to run over the MULTIBUS interface and the high speed
interface. This provides 0 wait state 8 MHz memory support for the iSBC 286/10A and iSBC 286/12 boards.
The EX RAM-boards generate byte oriented parity during all write operations and perform parity checking
during all read operations. An on-board LED provides a visual indication that a parity error has occurred.
The iSBC 012EX, iSBC 010EX, iSBC 020EX, and iSBC 040EX boards contain 512K bytes,1M byte, 2M bytes,
and 4M bytes of read/write memory using 256K dynamic RAM components.

280142-1

'The iSBC® 012EX, 010EX, 020EX and 040EX Boards are also manufactured under product code piSBC® or siSBC®
012EX, 010EX, 020EX and 040EX by Intel Puerto Rico, Inc. and Intel Singapore, Ltd.

9-9

September 1989
Order Number: 280142-002

iSBC@ 012EX, 010EX, 020EX, 040EX BOARDS

FUNCTIONAL DESCRIPTION

SELECTABLE ENDING ADDRESS

General

The ending address is selectable as memory size
minus select options of 0, 128K, 256K, or 512K on
all of the EX boards.

The iSBC 012EX, 010EX, 020EX, and 040EX RAM
boards are physically and electrically compatible
with the MULTIBUS interface standard, IEEE-796,
as outlined in the Intel MULTIBUS architecture specification.

PARITY INTERRUPT CLEAR
The I/O address of the Parity Interrupt Clear circuitry
is jumperable to anyone of 256 addresses.

Dual Port Capabilities

SPECIFICATIONS

The "EX" series of RAM-Boards can be accessed
by the MULTIBUS interface, and either the iLBX
Bus, or the high speed synchronous interface (see
Figures 1 and 2). The EX series require jumper and
PAL configuration to be accessed over iLBX Bus.

Word Size Supported
8- or 16-bits.

Intel's iLBX interface is an unarbitrated bus architecture which allows direct transfer of data between, the
CPU and the memory boards without accessing the
MULTIBUS bus. Due to the unarbitrated nature of
the iLBX interface, significant improvements in memory access times compared to the MULTIBUS bus
accesses result. The EX Boards provide 1 wait state
performance at 6 MHz and 2 wait states at 8 MHz
over the iLBX board. The EX Memory Board Hardware Reference Manual should be consulted for details.

Memory Size
524,288 bytes (iSBC 012E~ board)
1,048,576 bytes (iSBC 01 OEX board)
2,097,152 bytes (iSBC 020EX board)
4,194,304 bytes (iSBC 040EX board)

Access Times (All densities)
MULTIBUSI!I SYSTEM BUS

The high speed synchronous interface, like the iLBX
Bus, is a bus architecture which allows direct transfer of data between the CPU and the memory
boards without accessing the MULTIBUS -bus. This
high speed interface runs synchronously with the
iSBC 286/10A and iSBC 286/12 to provide 0 wait
state performance at 8 MHz.

Write Byte-

System Memory Size

Write Byte-

Read/Full Write- 375 ns (max)
375 ns (max)

HIGH SPEED SYNCHRONOUS INTERFACE
Read/Full Write- 167 ns (max)

Maximum system memory size with this seri~s of
boards is 16 megabytes. Memory partitioning is independent for the MULTIBUS interface and the iLBX
interface.

132 ns (max)

ILBXTM BUS
Read/Full Write- 295 ns (max)
Write Byte-

Address Selection/Memory

116 ns (max)

Cycle Times (All densities)

SELECTABLE STARTING ADDRESS

MULTIBUSI!I SYSTEM BUS

A 256K boundary select is implemented on the iSBC
012EX board. A 512K boundary select is implemented on the iSBC 010EX board. A 1M boundary is implemented on the iSBC 020EX and iSBC 040EX
boards.

Read/Full Write- 625 ns (max)
625 ns (max)
Write Byte-

9-10

intJ

iSBC® 012EX, 010EX, 020EX, 040EX BOARDS

HIGH SPEED SYNCHRONOUS INTERFACE

ENVIRONMENTAL REQUIREMENTS

Read/Full Write- 250 ns (max)

Operating
Temperature: O°C to 60°C airflow of 5 cubic feet per
minute

Write Byte

250 ns (max)

Storage
Temperature: -40°C to

iLBXTM BUS
Read/Full Write- 437.5 ns (max)
Write Byte

Operating
Humidity:

437.5 ns (max)

+ 75°C

To 90% without condensation

Memory Partitioning

PHYSICAL DIMENSIONS

Maximum System memory size is 16M Bytes for the
MULTIBUS. iLBX bus and the high speed interface.

Width:

12 inches (30.48 cm)

Height:

6.75 inches (17.15 cm)

Thickness: 0.50 inches (1.27 cm)
Weight:

BASE ADDRESS
Board

Base Address

iSBC 012EX Board

any 256K boundary in
first 4 megabytes

iSBC 01 OEX Board

any 512K boundary in
first 8 megabytes

iSBC 020EX Board

any 1M boundary

iSBC 040EX Board

any 1M boundary

iSBC 012EX board: 6.8 ounces
(1910 gm)
iSBC 010EX board: 9.0 ounces
(2550 gm)
iSBC 020EX board: 13.5 ounces
(3830 gm)
iSBC 040EX board: 18.0 ounces
(5100 gm)

REFERENCE MANUALS
147783-001- iSBC 012EX/iSBC 010EX/iSBC
020EX/iSBC 040EX Hardware
Reference Manual

Power Requirements
Voltage-5 VDC ±5%

144456-001-lntel iLBX Specification
Product

Current

iSBC 012EX Board

3.2A (typ)
4.9A(max)

ORDERING INFORMATION

iSBC 01 OEX Board

3.4A (typ)
5.0A (max)

Part Number

Description

iSBC012EX

512K byte RAM board with parity

iSBC 020EX Board
iSBC 040EX Board

3.7A (typ)
5.2A(max)

iSBC010EX

1M byte RAM board with parity

iSBC020EX

2M byte RAM board with parity

3.9A (typ)
5.5A(max)

iSBC 040EX

4M byte RAM board with parity

EXASYNCX86

PALs and jumper configuration for
.
iLBX mode

9-11

inter

iSBC® 012EX, 010EX,.020EX, 040EX BOARDS

MULTI BUS • INTERFACE

280142-2

Figure 1. TyplcallLBXTM System Configuration

512K,1024K,
2056K, 4096K
BYTES ARRAY

280142-3

Figure 2. iSBC® EX Memory Board Block Diagram

9·12

inter

iSBC® 012CX, 010CX, AND 020CX*
iLBXTM RAM BOARDS

•

Dual Port Capability via MULTIBUS®
and iLBX Interfaces

•
•
•

Single Bit Error Correction and Double
Bit Error Detection Utilizing Intel 8206
ECC Device

•
•
•

512K Byte, 1024K Byte, and 2048K Byte
Versions Available
Control Status Register Supports
Multiple ECC Operating Modes

Error Status Register Provides Error
Logging by Host CPU Board
16 Megabyte Addressing Capability
Supports 8- or 16-bit Data Transfer and
24-bit Addressing
Auxiliary Power Bus and Memory
Protect Logic for Battery Back-Up RAM
Requirements

The iSBC 012CX, iSBC 010CX and iSBC 020CX RAM memory boards are members of Intel's complete line of
iSBC memory and I/O expansion boards. The dual port feature of the CX series of RAM·boards allow access
to the memory of both the MULTIBUS and iLBX bus interfaces.
In addition to the dual port features the "CX" series of RAM· boards provide Error Checking and Corrections
Circuitry (ECG) which can detect and correct single bit errors and detect, but not correct, double and most
multiple bit errors.
The iSBC 012CX board contains 512K bytes of read/write memory using 64K dynamic RAM components. The
iSBC 010 CX and iSBC 020 CX boards contain 1024K and 2048K bytes of read/write memory using 256K
dynamic RAM components.

231023-1

·The iSBCI!) 012CX, 010CX, and 020CX Boards are also manufactured under product code piSBC® and siSBC 012CX,
010CX, and 020CX by Intel Puerto Rico, Inc. and Intel Singapore, Ltd.

9·13

September 1989
Order Number: 231023·003

iSBC® 012CX, 010CX AND 020CX iLBXTM RAM BOARDS

Extension) interface as outlined in the Intel iLBX
Specification (see Figure 1).

FUNCTIONAL DESCRIPTION

General

Dual Port Capabilities

The iSBC 012CX, 010CX, and 020CX RAM boards
are physically and electrically compatible with the
MULTIBUS interface standard, IEEE-796, as outlined in the Intel MULTIBUS specification. In addition
the CX series of RAM-boards are physically and
electrically compatible with the iLBX bus (Local Bus

The "cx" series of RAM-boards can be accessed
by either the MULTIBUS interface or the iLBX interface (see Figure 2). Intel's iLBX interface is an unarbitrated bus architecture which allows direct transfer
of data between the CPU and the memory boards

231023-2

Figure 1. Typical iLBXTM System Configuration

512K
1024 K, 2058 K

BYTESARRAV

I
I

231023-3

Figure 2. iSBC® 012CX/010CX/020CX Block Diagram
9-14

inter

ISBC® 012CX, 010CX AND 020CX ILBXTM RAM BOARDS

without accessing the MULTIBUS bus. Due to the
unarbitrated nature of the iLBX interface significant
improvements in memory access times result, typically a 2-6 Wait State improvement over MULTIBUS
memory access.

SPECIFICATIONS
Word Size Supported
8- or 16-bits

System Memory Size

Memory Size

Maximum system memory size with this series of
boards is 16 megabytes. Memory partitioning is independent for the MULTIBUS interface and the iLBX
interface.

524,288 bytes (iSBC 012CX board)
1,048,576 bytes (iSBC 010CX board)
2,097,152 bytes (iSBC 020CX board)

For MULTIBUS operations, on-board jumpers assign
the board to one of four 4-megabyte pages. Each
page is partitioned into 256 blocks of 16K bytes
each. The smallest partition on any board in this series is 8K bytes. Jumpers assign the base address
(lowest 16K block) within the selected 4-megabyte
page.

Access Times (All densities)
MULTIBUS® System Bus
Read/Full Write- 380 ns (max)
Write Byte

The iLBX bus memory partitioning differs from the
MULTIBUS bus partitioning in that the iLBX bus address space consists of 256 contiguous blocks of
64K bytes totaling 16 megabytes. As with the
MULTIBUS bus partitioning, the base addresses are
set with on-board jumpers.

530 ns (max)

iLBXTM Local Bus
Read/Full Write- 340 ns (max)
Write Byte

Error Checking and Correcting (ECC)

440 ns (max)

Cycle Times (All densities)

Error checking and correction is accomplished with
the Intel 8206 Error Checking and Correcting device.
This ECC component, in conjunction with the ECC
check bit RAM array, provides error detection and
correction of single bit errors and detection only of
double bit and most multiple bit errors. The ECC circuitry can be programmed via the Control Status
Register (CSR) to various modes while error logging
is supported by the Error Status Register (ESR).
Both CSR and ESR communicate with the master
CPU board through a single I/O port.

MULTIBUS® System Bus
Read/Full Write- 490 ns (max)
Write Byte

885 ns (max)

iLBXTM Local Bus
Read/Full Write- 375 ns
Write Byte

Battery Back-Up/Memory Protect

740 ns

NOTE:
If an error is detected, read access time and cycle
times are extended to 255 ns (max)

An auxiliary power bus is provided to allow separate
power to the RAM array for systems requiring backup of read/write memory. An active low TIL compatible memory protect signal is brought out on the
auxiliary bus connector which, when asserted, disables read/write access to the RAM board. This input is provided for the protection of RAM contents
during system power-down sequences.

9-15

iSBC® 012CX, 010CX AND 020CX iLBXTM RAM BOARDS

Memory Partitioning

Environmental Requirements

Maximum System memory size is 16M Bytes for
both MULTIBUS and iLBX BUS. MULTIBUS partitioning is by Page, Block and Base, while the iLBX
BUS is by Block and Base only.

Operating Temperature: O°C to 55°C airflow of 200
linear feet per minute
Operating Humidity:
To 90% without condensation

Page Address

Physical Dimensions

MULTIBUS@- 0-4 megabytes; 4-8 megabytes, 812 megabytes; 12-16 megabytes
iLBXTM BUS- N/A

Width:

30.4B cm (12 inches)

Height:

17.15 cm (6.75 inches)

Thickness: 1.27 cm (0.50 inches)
Weight:

Base Address
MULTIBUS@ System Bus-Any 16K byte boundary
within
the
4M-byte
page.
iLBXTM Local Bus

Any 64K byte boundary
selectable on board
boundaries to 8M-bytes
and some 64K-byte
boundaries in the first
megabyte. Others available if PAL programming is changed.

iSBC 012CX board: 6589 gm (23.5
ounces); iSBC 010CX board: 5329 gm
(19.0 ounces); iSBC 020CX board: 6589
gm (23.5 ounces)

Reference Manuals
145158-003-iSBC@ 02BCX/iSBC@ 056CX/iSBC@
012CX Hardware Reference Manual
- 144456-001-lntel iLBXTM 010CX, 020CX
Specification

ORDERING INFORMATION
Power Requirements
Voltage-5 VDC ± 5%
Product

Current

Standby
(Battery Back-Up)

iSBC@012CX
Board

4.4A (typ.)
6.8A (max.)

2.2A (typ.)
2.4A (max.)

iSBC@010CX
Board

4.8A (typ.)
7.0A (max.)

2.1A (typ.)
2.3A(max.)

lSBC@020CX
Board

5.3A (typ.)
7.5A (max.)

2.2A (typ.)
2.4A (max.)

9-16

Part Number

Description

iSBC012CX
iSBC010CX

512K byte RAM board with ECC
1M byte RAM board with ECC

iSBC020CX

2M byte RAM board with ECC

iSBC® 314*
512K BYTE RAM MULTIMODULETM BOARD

•
•
•
•

Memory Expansion for the
• On-Board
iSBC® 86/35 Single Board Computer
Provides 512K Bytes
• ofiSBCDual314PortModule
RAM Expansion for the
iSBC 86/35 Board
Mechanical and Electrical
• Reliable
Interconnection

Completes iSBC 86/35 Memory Array
ProvlCiing a Full Megabyte Page of
System Memory
Increases System Throughput by
Reducing Accesses to MULTIBUS®
Global Memory
Low Power Requirements
Battery Backup Capability

The iSBC® 314 512K byte RAM MULTIMODULE board provides simple, low cost expansion to double the onboard RAM capacity of the iSBC 86/35 Single Board Computer host to one megabyte. This RAM MULTIMODULE option offers system designers a si'mple, practical solution to expanding and improving the memory
capability and performance of the iSBC 86/35 board. The iSBC 314 memory is configured on-board and can
be accessed as quickly as the standard iSBC 86/35 memory, eliminating the need for accessing additional
memory via the MULTlBUS system bus.

280000-1

·The iSBC® 314 Board is also manufactured under product code piSBC® 314 by Intel Puerto Rico, Inc.

9-17

September 1989
Order Number: 280000-003

intJ

ISBC® 314 BOARD

MEMORY LATCHES
(FROM HOST)

REPLACEMENT
MEMORY ADDRESS
DECODE PAL
(SUPPUED WITH ISac·

MULTIMODULE'"
OPTION)

Figure 1. Installation of the MULTIMODULETM RAM Module on the Host Single Board Computer

FUNCTIONAL DESCRIPTION

SPECIFICATIONS

The iSSC 314 MULTIMODULE board measures
2.40" by 5.75" and mounts above the RAM array on
the iSSC 86/35 Single Soard Computer. The iSSC
314 board contains sixteen 256 Kbit x 1 dynamic
RAM devices and three sockets; two for the memory
latches and one for the Intel 8203 dynamic RAM
controller. The addition of the iSSC 314 memory
MULTIMODULE board to the iSSC 86/35 board
makes possible a one megabyte single board solution.

Word Size
8 or 16 bits (16-bit data paths)

Memory Size
512K bytes RAM

System Cycle Time (8 MHz, 2 Wait
States) ,

To install the module, the latches and controller
from the host iSSC 86/35 board, are removed and
inserted into sockets on the iSSC 314 board. The
module is then mounted onto the host board. Pins
extending from the controller and latch sockets
mate with device sockets underneath (see Figure 1).
Additional pins mate to supply other Signals to complete the electrical interface. The module is then secured at three additional points with nylon hardware
to ensure the mechanical security of the assembly.

750 ns (read); 750 ns (write)
NOTE:
1 wait state achieved with jumper change on iSSC
86/35 board.

Memory Addressing
iSSC 314 module with iSSC 86/35 board -1 M byte
(total capacity); O-FFFFFH. (See Figure 2, Memory
Allocation)

To complete the installation, one socketed PAL is
replaced on the iSSC 86/35 board with the one supplied with the MULTIMODULE kit. This is the PAL
which allows the host board logic to recognize its
expanded on-board memory compliment.

Interface
The interface for the iSSC 314 MULTIMODULE
board option is designed only for the iSSC 86/35
host board.
9-18

iSBC® 314 BOARD

Wait-State Performance

Auxiliary Power

A significant performance advantage of 2 wait-states
is achieved when accessing memory on-board the
iSBC 86/35 versus the performance of 6 wait-states
when accessing memory off-board over the MULTIBUS. The iSBC 314 puts an additional 512K bytes of
system memory on-board the iSBC 86/35 reducing
the execution time by as much as 70%.

The low power memory protection option included
on the iSBC 86/35 board supports the iSBC 314
module.

Physical Characteristics
Width: 2.4 in. (6.10 cm)
Length: 5.75 in. (14.61 cm)
Depth': 0.72 in. (1.83 cm)
Weight: 0.13 oz. (59g)

Memory Allocation
Segments of the combined hostlMULTIMODULE
RAM may be configured to be accessed either from
off-board or on-board resources. The amount of
memory allocated as either public or private resource may be configured in a variety of sizes. The
address range boundaries for the 1 megabyte of
RAM array of the iSBC 314 and iSBC 86/35 board
combination are shown in Figure 2 for accesses
from both on-board and off-board resources.

NOTE:
'Combined depth including host board.

RAM
ACCESS
FROM
1M

ON·BOARD

FFFFFH

RAM
ACCESS
FROM
OFF-BOARD

960K

1-----1 ~m~

(lM·64K)

960K

t-----1 :::::: }

896K

1-----1 ~~~~~~

(IM-128K)

896K

1-_ _--1 ~~~~~

512K

1------1 ~~~~~~

EFFFFH

ENDING
ADDRESS

ISBC· 314 MODULE
512KBYTES

512K I--_ _.... ~~~~~~

ISace 88J35 BOARD
512KBYTES

128K·

20000H
lFFFFH

ooooOH

258K

40000H
3FFFFH

128K

20000H
lFFFFH

64K

10000H
OFFFFH

OOOOOH

BEGINNING
ADDRESS

NOTE:
280000-3
All memory above this boundary may be disabled under software control to allow access to MULTIBUS® system bus.

Figure 2. Address Range Selection
9-19

inter

iSBC® 314 BOARD

Electrical Characteristics
DC Power Requirements·

·Additional power required by the iSBC 314 MULTIMODULE is:
Typical: 60 mA @ + 5V
Maximum: 140 mA

ORDERING INFORMATION
Part Number Description
SBC314
512K byte Memory MULTIMODULE
option for iSBC 86/35 board

+ 5V

Environmental Characteristics
Operating Temperature: O·C to + 55·C
Relative Humidity:
to 90% (without
condensation)

Reference Manual
All necessary documentation for the iSBC 314 MULTIMODULE board is included in the iSBC 86/35
Hardware Reference Manual (NOT SUPPLIED).
Order Number: 146245-002

9-20

iSBC® 304*
128K BYTE RAM MUlTIMODUlETM BOARD

•

iSBC® 304 Module Provides 128K Bytes
of Dual Port RAM Expansion for the
iSBC 86/30 or iSBC 86/35 Board

•

On-board Memory Expansion
Eliminates MULTIBUS® System Bus
Latency and Increases System
Throughput

The iSBC® 304 module provides simple, low cost memory expansion for the iSBC 86/30 and iSBC 86/35
Single Board Computers. The iSBC 304 provides 128K bytes RAM expansion to the iSBC 86/35 giving a total
capacity of 640K bytes RAM memory. The RAM MULTIMODULE option offers flexibility in defining and implementing Intel single board computer systems. RAM MULTIMODULES expand the memory configuration onboard, eliminating the need for accessing the additional memory via the MULTIBUS system bus.

I
210329-1

'The

iSBC~

304 Board is also manufactured under product code

piSBC~

304 by Intel Puerto Rico, Inc.

9-21

October 1989
Order Number: 210329-003

inter

ISBCQl) 304 MULTIMODULE BOARD

FUNCTIONAL DESCRIPTION
Each MULTIMODULE contains dynamic RAM devices and sockets for the dynamic RAM controller. To
install the module, the latches and controller from
the host CPU board are removed and inserted into
sock'ets on the RAM MULTIMODULE. The module is
then mounted onto the host board. Pins extending
from the controller and latch sockets mate with device sockets underneath (see Figure 1). Additional
pins mate to supply other signals to complete the
electrical interface.

The module is then secured at three additional
points with nylon hardware to ensure the mechanical
security of the assembly.
To complete the installation, one socketed PROM is
replaced on the host CPU board with the one supplied with the MULTIMODULE kit. This is the
MULTIBUS address decode PROM which allows the
host board logic to recognize its expanded on-board
memory compliment.

MEMORY LATCHES
IFROM HOST)

REPLACEMENT
MEMORY ADDRESS
DECODE PROM
ISUPPLlEO WITH Isac'
MUL TlMODULE" OPTIONI

.. j
NYLON MOUNTING
HARDWARE 13 PLACES)
(SUPPLIED WITH Isac'
MULTI MODULE" OPTIONI

210329-2

Figure 1. Installation of the MULTIMODULETM RAM on the Host Single Board Computer

9-22

ISBC 302 is also manufactured under product code piSBCIII> 302 by Intel Puerto Rico, Inc.

9-24

September 1989
Order Number: 280225-002

intJ

iSBC® 302

FUNCTIONAL DESCRIPTION

Memory Addressing

The iSBC 302 MULTIMODULE and mounts above
the RAM area on the iSBC 86/05A or iSBC 88/25
Single Board Computer. The iSBC 302 MULTIMODULE board contains four 4K x 4 static RAM devices
and sockets for two of the RAM devices on the iSBC
80/05A board. With the iSBC 302 MULTIMODULE
mounted on the iSBC 88/25 board, the two sockets
on the iSBC 302 MULTIMODULE may be filled with
4K x 4 static RAMs. The two sockets on the iSBC
302 module have extended pins which mate with
two sockets on the base board. Additional pins mate
to the power supply and chip select lines to complete the electrical interface. The mechanical integrity of the assembly is assured with nylon hardware
securing the module in two places.

Memory addressing for the iSBC 302 MULTIMODULE board is controlled by the host board via the
address and chip select signal lines.

Physical Characteristics
Width: 2.6 in. (6.60 cm)
Length: 2.3 in. (5.84 cm)
Height: 0.56 in. (1.42 cm) iSBC 302 board
board
Weight: 1.25 oz. (35 gm)

+ Base-

Electrical Characteristics
DC Power Requirements: 720 rnA at + 5V incremental power

SPECIFICATIONS

Word Size

Environmental Characteristics

8/16 bits
Operating Temperature: O°C to
Relative Humidity:

Memory Size

+ 55°C

to 90% (without condensation)

16,384 bytes of RAM

Reference Manuals

Cycle Time

All necessary documentation for the iSBC 302 MULTIMODULE board is included in the CPU board
Hardware Reference Manuals (NOT SUPPLIED).
iSBC 86/05A -Order No. 147162-002

Provides "no wait state"memory operations on the
iSBC 86/05A board at 5 MHz or 8 MHz or the iSBC
88/25 at 5 MHz.
5 MHz cycle time 8 MHz cycle time -

iSBC 88/25 -Order No. 143825-002

800 ns
500 ns

ORDERING INFORMATION
Part Number Description
SBC 302
8K byte RAM MULTIMODULE

9-25

iSBC® 301*
4K·BVTE RAM
MULTIMODULETM BOARD
• On-Board Memory Expansion to 8K
Bytes for ISBC~ 88/40A Single Board
Computers

• Provides 4K Bytes of Static RAM
Directly On-Board

The Intel iSBC 301 4K-byte RAM MULTIMODULE Board provides simple, low cost expansion to double the
RAM capacity on the iSBC 88/40A Single Board Computer to 8K bytes. Because memory is configured onboard, it can be accessed as quickly as the existing iSeC 88/40A memory, eliminating the need for accessing
the additional memory via the MULTIBUS system bus.

280224-1

·The iSBC. Board is also manufactured under product code piSBC. 301 by Intel. Puerto Rico, Inc.

9-26

September 1989
Order Number: 280224-002

iSBC® 301

board and inserted into the socket on the iSBC 301
board. The add-on board is then mounted into the
vacated RAM socket on the host board. Pins extending from the RAM socket mate with the device's
socket underneath (see Figure 1). Additional pins
mate to the power supply and chip select lines to
complete the electrical interface. The MULTIMODULE board is then secured at two additional points
with nylon hardware to insure mechanical security of
the assembly.

FUNCTIONAL DESCRIPTION
The iSBC 301 Board mounts above the RAM area
on the iSBC 88/40A single board computer. It expands the on-board RAM capacity from 4K bytes to
8K bytes. The iSBC 301 MULTIMODULE board contains four 1K byte static RAM devices and a socket
for one of the RAM devices on the iSBC 88/40A
board. To install the iSBC 301 MULTIMODULE
board, one of the RAMs is removed from the host

NYLON MOUTING
~_~ HARDWARE
(2 PLACES)

""
- - -_ _

(SUPPLIED WITH
isaees> 301 OPTION)

280224-2

Figure 1. Installation of iSBC® 301 4K Byte RAM MULTIMODULETM Board

9-27

inter

ISBC® 301

SPECIFICATIONS

Electrical Characteristics
DC Power Requirements:

Word Size

10 mA at +5 Volts incremental power

8 bits

Environmental Characteristics
Operating Temperature: O°C to + 55°C
Relative Humidity:
to 90% (without condensation)

Memory Size
4096 bytes of RAM

Reference Manuals

Access Time
Read: 140
200
Write: 150
190

ns
ns
ns
ns

(from
(from
(from
(from

READ command)
ALE)
READ command)
ALE)

All necessary documentation for the iSBC 301
MULTIMODULE board is included in the CPU board
Hardware Reference Manual (NOT SUPPLIED)
iSBC 88/40A-Order No. 147049-001

Memory Addressing

SPECIFICATIONS
Part Number Description
SBC 301
4K Byte RAM MULTIMODULE Board

Memory addressing for the iSBC 301 4K-Byte-RAM
MULTIMODULE Board is controlled by the host
board via the address and chip select signal lines
and is contiguous with the host board RAM.
iSBC 88/40A and iSBC 301 board: 00000-01FFF

Physical Characteristics
Width: 1.20 in. (3.05 cm)
Length: 3.95 in. (10.03 cm)
Height: 0.44 in. (1.12 cm) iSBC 301 Board
0.56 in. (1.42 cm)
iSBC 301 Board + host board
Weight: 0.69 oz. (19 gm)

9-28

iSBC® 429 UNIVERSAL SITE MEMORY EXPANSION BOARD

CMOS MULTIBUS®I MEMORY EXPANSION BOARD SUPPORTS LATEST
MEMORY TECHNOLOGY
The iSBC® 429 board provides a wide range of memory expansion capabilities for
MULTIBUS designs. Up to 4 MBytes of memory can be installed using EPROM, Flash
memory, SRAM, E2PROM or Static NVRAM.
,The CMOS implementation of the iSBC 429 makes it ideal for low power applications.
All of Intel's Single Board Computers can communicate with the iSBC 429 using the
MULTIBUS System bus. Alternatively, the iSBC 429 may be optionally configured to use the
iLBXTM bus for faster access to the iSBC 186/03A, 286110A, 286112 series or 386/12 series of
Single Board Computers.

FEATURES:
• Supports EPROM, Page Mode EPROM,
E2PROM, Flash Memory, SRAM and
Static NVRAM
• Thirty-two standard 32-pin JEDEC sites
(supports both 28-pin and 32-pin
devices) up to 4MByte capaGity
• ILBX Bus or MULTIBUS Configurability
• Low power CMOS design
• Battery Backup/Memory Protect support
• Assignable anywhere within a 16
Megabyte address space on 4K byte
boundaries

inl:el-'- - - - - - - - - September, 1989

Order Number 280668-001

9-29

FEATURES
iLBX Bus

MEMORY ACCESS

The iSBC 429 board can be configured via jumpers to
communicate with either the MULTIBUS interface or
the iLBX Bus interface. Significant memory access
time improvements can be realized using the iLBX Bus
interface versus the MULTI BUS interface, due to its
dedicated, unarbitrated architecture. Additional
information on the iLBX Bus is available in the iLBX
Specification, order number 145695-Rev. A.

The iSBC 429 board has jumper-selectable access
times for each bank which allows the board to be
tailored to the performance of the particular devices
which are installed in the iSBC 429 board. The iSBC
429 accepts devices with an access time ranging from
150 ns with a minimum granularity of 99 ns and results
in a board access time from 182 ns to 1667 ns. Each
bank can be configured for access time.

CMOS DESIGN

INHIBITS

For embedded control applications which are sensitive
to power consumption, the iSBC 429 was designed
with CMOS components and it will support many
CMOS memory devices. Unpopulated, the iSBC 429
requires 5.25 watts at 5 volts.

Inhibit signals are provided on the iSBC 429 board to
allow ROM to overlay RAM for bootstrapping or
diagnostic operations. Each bank of the iSBC 429
board can be overlayed with the system RAM by
jumpers provided on the board. (i.e. If banks are
overlapped, inhibits can be used to select the
appropriate bank.)

FLASH MEMORY SUPPORT
The iSBC 429 board supports Intel's new CMOS Flash
Memory devices. These new memory devices offer the
most cost-effective and reliable alternative for
updatable non-volatile memory. Memory contents can
be erased and reprogrammed on-board during
subassembly test, in-system during final test, and insystem after sale.

MEMORY BANKS
The thirty-two sites on the iSBC 429 board are
partitioned into two banks of 16 sites each. Both banks
are independently configurable to any of the device
types supported on the board. Each bank can support
up to 2 Megabytes using 27010 devices.

MEMORY ADDRESSING
The address space of each bank can be
independently configured for starting address and
size. The starting address can be on any 4 KByte
boundary within the 16 MByte MULTI BUS address
space. The,size of each bank is a multiple of 64
KBytes.
.

MODE OF OPERATION
The iSBC 429 board can operate in one of two modes:
the 8 bit only mode or the 8116 bit mode. The 8 bit
mode provides the most efficient memory
configuration for systems handling 8 bit data only. The
8116 bit mode allows the iSBC 429 board to be
compatible with systems employing 8 bit and 16 bit
masters. The mode of operation is selected by onboard jumpers and is available for both MULTIBUS
and iLBX Bus configurations.

9-30

BATTERY BACKUP
The iSBC 429 board supports battery backup
operation via a connector on the board. An auxiliary
power bus is provided to allow separate power to the
memory array for systems requiring battery backup.
Selection of this auxiliary power bus is made via
jumpers on the board.
An active-low TTL compatible Memory Protect signal is
brought out on the auxiliary connector which, when
asserted, disables access to the memory array. This'
input is provided for the protection of Memory contents
during system power-down sequences.

SPECIFICATIONS
MEMORY DEVICES SUPPORTED BY THE ISBC 429
Size
Type

8Kx8

16Kx8

32Kx8

64Kx8

128Kx8

256Kx8

4x 16Kx8

8x 16Kx8

EPROM

2764

27128

27256

27512

27010

27020

"
-

27513

27011

ROM

,,1

Page Mode
EPROM

"
-

2864A

27F64

E2PROM2
Flash
Memory3

27F256
28F256

"
SRAM
"
"
denotes that the iSBC 429 board will support the device indicated, but that it is not currently available
Static
NVRAM4

1 ",,"

from Intel.
2 Five Volt only, Enhanced
3 12 Volt Vp only
4 Static NVRAM devices exceed the height specification for MULTIBUS. The iSBC 429 will occupy more than
one slot with these devices installed.

WORD SIZE

POWER REQUIREMENTS

8 or 8116 bits

Vcc=5 volts ±5%
Vpp=12 volts ±5%
Icc =1.2 amps, maximum, without any memory devices
in the board.

MEMORY SIZE
Sockets are provided for up to thirty-two 32-pin or 28pin devices which can provide up to 4 Megabytes of
EPROM/ROM/SRAM/Flash Memory.

ACCESS TIME
Access time is jumperable from 182 ns to 1667 ns with
a granularity of 99 ns to optimize performance for the
devices which are installed and is equivalent for
MULTI BUS and iLBX Bus.

PHYSICAL CHARACTERISTICS
Width -12.00 inches (30.48 cm)
Depth - 7.05 inches (17.91 cm)
Height - .5 Inches (1.27 cm)

ENVIRONMENT
Operating Temperature - O°C to + 60°C (Convection
cooling)
Relative Humidity - 90% non-condensing

ORDERING INFORMATION
PART NUMBER
SBC429

DESCRIPTION
Universal Site Memory
Expansion Board

REFERENCE MANUAL
457317-001 - iSBC 429 Hardware Reference Manual
(NOT SUPPLIED)

9-31

iSBC® 428 UNIVERSAL SITE
MEMORY EXPANSION BOARD
•

Supports EPROM, ROM, E2PROM,
SRAM, IRAM and NVRAM

•

iLBXTM BUS or MULTIBUS® Selectable

•

Provides Support for Battery Backupl
Memory Protect

•

Sixteen 28-Pin Universal Sites

•

Assignable Anywhere within a 16 Mbyte
Address Space on 256K Byte
Boundries

•

Jumper Selectable Base Address on
4K Byte Boundaries

The iSBC@ 428 Universal Site Board is a member of Intel's complete line of Memory and 110 Expansion
boards. The iSBC 428 Universal Site Memory Expansion Board interfaces directly to the iSBC 80, iSBC 88, or
iSBC 86 Single Boad Computers via the MULTIBUS@ System Bus to expand system memory requirements,
while system memory requirements for iSBC 286 Single Board Computer can interface via either the MULTIBUS or the high speed iLBXTM Bus.

281013-1

9-32

October 1989
Order Number: 281013-001

intJ

iSBC® 428

FUNCTIONAL DESCRIPTION

Mode of Operation
The iSBC 428 board can operate in one of two
modes: the 8 bit only mode or the 8/16 bit mode.
The 8 bit mode provides the most efficient memory
configuration for systems handling 8 bit data only.
The 8/16 bit mode allows the iSBC 428 board to be
compatible with systems employing 8 bit and 16 bit
masters. The mode of operation is selected by on
board jumpers and is available for both MULTIBUS
and iLBX Bus configurations.

General
The iSBC 428 board contains sixteen 28 pin sockets. The actual capacity of the board is determined
by the type and quantity of components installed by
the user. The iSBC 428 board is compatible with five
different types and densities of devices: the 2K by 8
thru 64K by 8 EPROM/ROM devices, 2K by 8 thru
8K by 8 "Five Volt Only, Enhanced" E2PROM devices, 512 by 8 thru 16K by 8 NVRAM (Non-Volatile
RAM) devices, 2K by 8 thru 32K by 8 SRAM devices,
and 8K by 8 IRAM (Integrated RAM) devices. In addition the board can 'be accessed by either the MUTIBUS System Bus or Intel's new high speed iLBX
Bus.

Memory Access
The iSBC 428 board has jumper selectable access
time, which allows the board to be tailored to the
performance of the particular devices which are installed in the iSBC 428 board. The board can be
configured via jumpers to accept devices with an access time range of 50 ns to 500 ns with a granularity
of 50 ns and results in a board access time from
225 ns to 775 ns.

iLBXTM Bus
The iSBC 428 board can be configured via jumpers
to communicate with either the MULTIBUS interface
or the iLBX Bus interface., Significant memory access time improvements can be realized over the
iLBX Bus interface (versus the MULTIBUS interface)
due to its dedicated, unarbitrated architecture. Additional information on the iLBX Bus is available in the
iLBX Specification # 144456.

Interrupt
The iSBC 428 board has the capability of generating
an interrupt for the write and erase operations of
E2PROMs. The interrupt can be configured in two
ways: one, to signal completion of the E2PROM
write cycle, or two, allow polling, by the system to
determine the status of the E2PROM during the
write programming time.

Memory Banks
The sixteen sites on the iSBC 428 board are partitioned into two banks of 8 sites each. Within each
bank the 8 sites are futher partitioned into 2 groups
of 4 sites each. Each group of 4 sites is configurable
to each of the six device types described above via
a "Configurator". The "Configurator" is an arrangement of push-on jumpers which configures each, of
the four groups of 4 sites. Within each bank devices
of the same density must reside and within each
group devices of the- same type must reside (i.e.,
SRAM or EPROM).

Inhibits
Inhibits are provided on the iSBC 428 board to allow
ROM to overlay RAM for bootstrapping or diagnostic
operations. Each bank of the iSBC 428 board can be
overlayed with the system RAM by jumpers provided
on the board.

Battery Backup
The iSBC 428 board supports battery backup operation via a connector on the board. An auxiliary power
bus is provided to allow separate power to the mem-'
ory array for systems requiring battery backup. Selection of this auxiliary power bus is made via jumpers on the board.

Memory Addressing
Addressing of the iSBC 428 board is by pages.
There are 64-256K pages which are jumpers selectable. Each of the two banks are independently addressable and can reside in any page. Actual beginning and ending addresses within a page are a function of the actual device size and, as with the pages,
are determined by jumpers. Because of the paging
based memory addressing architecture more than
one iSBC 428 board can be placed in a system.

An active-low TTL compatible Memory Protect signal is brought out on the auxiliary connector which,
when asserted, disables access to the memory array. This input is provided for the protection of Memory contents during system power-down sequences.

9-33

inter

ISBC«> 428

Devices Supported
Listed below are the current and future devices supported by the iSBC 428 board.
Size
Type

512x8

2Kx8

4Kx8

8Kx8

16Kx8

32Kx8

64Kx8

Comments

EPROM
ROM
EEPROM
SRAM
NVRAM
IRAM

2716

2732A

2764

27128

27256

27512

X
X
X
X

X
X
X

2817A

X
X

2186

5V. Enhanced
NMOS & CMOS

X-Denotes that the iSSC 42B board will support the device indicated but that it is not currently available from Intel.

BANK A ,BANK B

I
'I

MEMORY
AR7AY

I
SIxm:N 28-PIN
UNIVERSAl SITES

, 281013-2

ISBCQ!) 428 Block Diagram

9-34

intJ

iSBC® 428

SPECIFICATIONS

Physical Characteristics

Word Size
8 or 8/16 bits

Length: 30.48 cm (12 inches)
Width: 17.15 cm (7.05 inches)
Depth: 1.27 cm (0.5 inches)

Memory Size

Environment
Operating Temperature: O°C to + 55°C
Relative Humidity:
90% non-condensing

Sockets are provided for up to sixteen 28 pin devices which can provide up to 512K bytes of EPROM/
ROM/SRAM.

ORDERING INFORMATION

Access Time

Order Code

Jumperable from 225 ns to 775 ns with a granularity
of 50 ns and is equivalent for both MULTIBUS and
the iLBX Bus.

SBC428

Power Requirements
vee = 5 volts ±5%
lee = 2.0 amps, maximum, without any memory devices in the board.

9-35

Description
Universal Site Memory Expansion
Board

iSBC® 341

28-PIN MULTIMODULETM EPROM
•. On-board Memory Expansion for
ISBC® 86/05A, iSBC 88/25,
iSBC 186/03A, iSBC 286/10A,
iSBC 286/12' Series, and iSBC 88/40A
Microcomputers
•

Supports JEDEC 24/28-Pin Standard
Memory Devices, Including EPROMs,
Byte-Wide RAMs, and E2PROMs

•

Sockets for Up to 256K Bytes of
Expansion with Intel 27512 EPROMs

•

On-Board Expansion Provides "No Wait
State" Memory Access with Selected
Devices

•

Simple, Reliable Mechanical and
Electrical Interface

The iSBC 341 28-pin MULTIMODULE EPROM board provides simple, low-cost expansion of the on-board
EPROM capacity of the iSBC 86/05A, the iSBC 88/25, iSBC 186/03A, iSBC 286/10A, iSBC 286/12 Series
Single Board Computers and the iSBC 88/40A Measurement and Control Computer. Four additional 28-pin
sockets support JEDEC 24/28-pin standard devices, including EPROMs, byte-wide static and psuedo-static
RAMs.
The MULTIMODULE expansion concept provides the optimum mechanism for incremental memory expansion. Mounting directly on the microcomputer, the benefits include low cost, no additional power requirements
beyond the memory devices, and higher performance than MULTIBUS-based memory expansion.

280214-1

9-36

October 198B
Order Number: 2B0214.(1()1

iSBC® 341 BOARD

FUNCTIONAL DESCRIPTION

POWER REQUIREMENTS
Devlces(1)

The iSBC 341 28-pin MULTIMODULE EPROM option effectively doubles the number of sockets available for EPROM on the base microcomputer board
on which it is mounted. The iSBC 341 board contains six 28-pin sockets. Two of the sockets have
extended pins which mate with two of the sockets
on the base board. Two of the EPROMs which
would have been inserted in the base board are then
reinserted in the iSBC 341 sockets. Additional interface pins also connect chip select lines and power.
The mechanical integrity of the assembly is assured
with nylon hardware securing the unit in two places.

Max Current

5V ± 5%

420 rnA
SOOmA
SOOmA

2716
2732A
2764

NOTE:
1. Incremental power drawn from host board for four additional devices.

Auxiliary Power
There are no provisions for auxiliary power (battery
backup) on the iSBC 341 option.

Through its unique interface, the iSBC 341 board
can support 8- or 16-bit data paths. The data path
width is determined by the base board-being 8 bits
for the iSBC 88/40A and iSBC 88/25 microcomputers, and 8/16 bits for the iSBC 86/05A,
iSBC 186/03A, iSBC 286/10A, and iSBC 286/12
Series Single Board Computers.

Physical Characteristics
Width: 3.4 in. (8.64 cm)
Length: 2.7 in. (6.86 cm)
Height: 0.78 in. (1.98 cm)·
Weight: 5 oz. (141.5 gm)
·Includes height of mounted memory devices and
base board.

SPECIFICATIONS
Word Size

All necessary mounting hardware (nylon screws,
spacers, nuts) is supplied with each kit.

8 or 8/16 bits (determined by data path width of
base board).

Environmental Characteristics
Operating Temperature: O·C to +55·C

Memory Size

Relative Humidity:

256K bytes with available technology (JEDEC standard defines device pin-out to 512-bit devices).

Reference Manuals

Device Size EPROM Max iSBC® 341 Capacity
(Bytes)
Type
(Bytes)
2Kx8
4Kx8
8Kx8
16Kx8
32Kx8
64Kx8

2716
2732A
2764
27128
27256
27512

to 90% (without condensation)

All necessary documentation for the iSBC 341 mod·
ule is included in the CPU board Hardware Refer·
ence Manuals (NOT SUPPLIED)

8K
16K
32K
64K
128K

iSBC
iSBC
iSBC
iSBC
iSBC
iSBC

~56K

Access Time

186/03A - Order No. 148060·001
86/05A - Order No. 147162·002
88125 - Order No. 143825·002
88/40A - Order No. 147049-001
286/10A - Order No. 147532·001
286/12 - Order No. 147533·001

Varies according to base board and memory device
accpss time. Consult data sheet of base board for
details.

Manuals may be ordered from any Intel sales repre·
sentative, distributor office, or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

Memory Addressing

ORDERING INFORMATION

Consult data sheet of base board for addressing
data.

Part Number
SBC341
9-37

Description
28·Pin MULTIMODULE EPROM

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MULTIBUS® I
Peripheral Controllers

iSBC® 221* PERIPHERAL CONTROLLER

MULTIBUS®I CONTROLLER FOR
HIGH PERFORMANCE, HIGH CAPACITY PERIPHERALS
The iSBC® 221 is a multifunction peripheral controller that provides access to highperformance, high-capacity disk drives (hard, flexible, and streaming tape). 110 bound
applications and/or those requiring high disk capacity will especially benefit from this fast,
reliable controller. The iSBC 221 can replace the Intel iSBC 214 without changing the
operating system device driver or the disk drives.

FEATURES:
• Support for ESDI and ST506/412 hard
disk drives, SA 45X/46X/475 flexible
disk drives, and QIC-02 streaming tape
drives
• Multiple track caching via 128K onboard data buffer
• Dual bus structure
• 10 MHz 80186 Microprocessor
• Mirror backup/restore between tape
and hard drive
• On-board self-test diagnostics
• Error-checking and correcting code
logic
• Support for 4,096 cylinders and 16
heads

I"m_I'
•• --e-

The ISBCi!l 22115 also manufactured under product code plSBO!' 221 by Inlel Puerto RIco. Inc
September, 1989
Order Number 280410·002

10-1

FEATURES

Figure 1: Simplified Block Diagram of iSBC 221 Peripheral Controller

011

Peripheral
Acce..
Control
U54

8D196
CPU
U63

o
""

Interrupt

Controller
825.

u..

DAM OM

IIULTIBUS 8 P1 Connector

0011

UBI

MULTIaUS8 P2 Connector

Figure 2: Connectors and Major Components of iSBC 221 Peripheral Controller

WORLDWIDE SERVICE
AND SUPPORT

INTERFACE SUPPORT
Hard Disk
(up to 2)
Flexible Disk
(up to 4)

Streaming Tape
(up to 4)

Interface

Transfer Rate

EDSI

up to 10 Mbitlsec
5 Mbltlsec

ST506/412
SA 475

2501500 Kbitlsec

SA 460/465

1251250 Kbitlsec

SA 450/455

1251250 Kbitlsec

QIC-02

901112.5 Kbitlsec
(typical)

HIGH PERFORMANCE
I/O-bound applications are
accelerated by the combination
of the ESDI standard, a 128K
data buffer, a 10 MHz 80 186
microprocessor, and a dual bus
structure. The dual bus structure
allows the iSBC 221 to
concurrently transfer data
between the controller and the
peripheral devices and between
the controller and the host.

Intel provides support for board
repair or on-site service.
Development support options
include phone support,
subscription service, on-site
consulting and customer
training.

QUALITY AND
RELIABILITY TESTING
The iSBC 221 is designed and
manufactured in accordance
with Intel's high quality
standards. We then verify quality
through rigorous testing in our
state-ol-the-art Environmental
Test Laboratory.

10-2

SPECIFICATIONS
PHYSICAL CHARACTERISTICS
Length:
Width
Approximate
Weight:
.

12.0in (304.8 mm)
6.75 in. (171.5 mm)
24 oz (680 g)

ORDERING INFORMATION
Order Code

Description

SBC221

Peripheral Controller

POWER REQUIREMENTS
+ 5 VDC @ 4.5A maximum
±12V@ 0.5A

ENVIRONMENTAL REQUIREMENTS
Operating Temperature: 0 to 55° @ 200 LFM
-55 to 85°C
Non-operating:
Humidity:
0 to 90% non-condensing

REFERENCE MANUAL
ISSC 221 Peripheral Controller User's GUide Order
#451210

DEVICE DRIVERS
Check the latest release of the following operating
systems for details:
XENIX'
iRMX I
IRMX II
UNIX'
iRMXl1i
• XENIX is a trademark of Microsoft, Inc.
UNIX is a trademark of American Telephone and
Telegraph, Inc.

10-3

iSBC® 214~
PERIPHERAL CONTROLLER SUBSYSTEM
•

Based on the 80186 Microprocessor

•

Supports 20 or 24-Bit Addressing

•

Controls up to Two ST506/412 5%"
Hard Disk Drives

•

On-Board Diagnostics and Hard Disk
ECC

•

Controls up to Four Single/Double
Sided and Single/Double Density 5%"
Flexible Disk Drives

. ' Incorporates Track Caching to Reduce
Winchester Disk Access Times
.

•

Controls up to Four QIC-02 Streaming
Tape Drives

•

iRMXTM and UNIX* Operating System
Support

The iSBC 214 Subsystem is a single-board, multiple device controller that interfaces standard MULTIBUS®
systems of three types of magnetic storage media. The iSBC 214 Peripheral Controller Subsystem supports
the following interface standards: ST506/412 (Hard ,Disk), SA 450/460 (Flexible Disk), and QIC-02 (%"
Streaming Tape).
The board combines the functionality of the iSBC 215 Generic Hard Disk Controller and the iSBC 213 Data
Separator, the iSBXTM 218A Flexible Disk Controller, and the iSBX 217C %" Tape Drive Interface Module.
The iSBC 214 Subsystem emulates the iSBC 215G command set, allowing users to avoid rewriting their
software.
The iSBC 214 Peripheral Controller Subsystem offers a single slot solution to the interface of multiple storage
devices, thereby reducing overall power requirements, increasing system reliability, and freeing up backplane
slots for addtional functionality. In addition, the new iSBC 214 Subsystem can be placed in a 16 Megabyte
memory space.

280089-1

·UNIX is a trademark of Bell Laboratories.
·The iSBCI!!> 214 is also manufactured under product code piSBC@ 214 by Intel Puerto Rico, Inc.

10-4

October 1989
Order Number: 280089-002

iSBC® 214

The iSBC 214 represents a new Peripheral Controller Subsystem architecture which is designed
around a dual bus structure and supported by realtime, multitasking firmware. The 80186 controls the
local bus and manages the interface between the
MULTI BUS and the controller. It is responsible for
high speed data transfers of up to 1.6 megabytes
per second between the iSBC 214 Subsystem and
host memory. The 80186 and the multitasking firmware decode the command request, allocate RAM
buffer space, and dispatch the tasks.

ripheral devices. It is this dual bus system that allows the iSBC 214 Subsystem to provide simultaneous data transfers between the controller and the
storage devices, and between the controller and the
MULTIBUS. (See Figure 1).
The iSBC 214 Subsystem implements an intelligent
track caching scheme through dynamic allocation of
buffer space. This provides reduced access times to
the Winchester disk and improved system performance. Operating systems with file management designed to handle sequential data can be supplied
directly from the cache without incremental access
to the disk.

A second bus, the I/O Transfer Bus, supports data
transfers between the controller and the various pe-

00106
1/0 PROCESSOR

DMA
CONTROLLER

LOCAL
BUS
INTERFACE

MULTIBUS'
INTERFACE

I-

ROM

.......

WINCHESTER
DISK
INTERFACE

1/0 TRANSFER
BUS
INTERFACE

FLEXIBLE
DISK
INTERFACE

RAM

QIC.Q2
TAPE
INTERFACE

ISac' 214 PERIPHERAL CONTROLLER SUBSYSTEM

280089-2

Figure 1. Block Diagram iSBC® 214 Peripheral Controller Subsystem

10-5

inter

iSBC® 214

SPECIFICATIONS

Ordering Information

Compatibility

Order Code
Description
SBC214
Peripheral Controller Subsystem.

CPU-any MULTIBUS computer or system mainframe.

Electrical Characteristics

Hard disk-Any ST506/412 compatible, 5.25" disk
drive.

Power Requirements:

Flexible disk-Any SA450/460 compatible, 5.25"
disk drive.

Environmental Characteristics

+ 5 VDC

4.5A max.

Temperature: 10°C to 55°C with airflow of 200 linear
feet per minute (operating); -55°C to
+ 85°C (non-operating).
Up to 90% relative humidity without
Humidity:
condensation (operating); all conditions without condensation or frost
(non-operating).
Occupies one slot or SBC system
Mounting:
chassis or cardcage/backplane.

Tape drive-Any QIC-02 compatible, .25" streaming
tape drive.
Controller-to-drive cabling and connectors are not
supplied with the controller. Cables can be fabricated with flat cable and commercially-available connectors as described in the iSBC 214 Hardware Reference Manual.

Physical Characteristics

Reference Manual

Width: 6.75 in. (17.15 cm)
Height: 0.5 in. (1.27 cm)
Length: 12.0 in. (30.48 cm)
Shipping Weight: 19 oz. (540 g)

134910:

10-6

iSBC 214 Peripheral Controller Subsystem Hardware Reference Manual
(not supplied). Reference Manual
may be ordered from any Intel sales
representative, distributor office or
from Intel Literature Department,
3065 Bowers Avenue, Santa Clara,
CA 95051.

iSBC® 208*
FLEXIBLE DISKETTE CONTROLLER

•
•
•
•

Compatible with All ISBC® 80, ISBC 86,
and ISBC 88 Single Board Computers
Controls Most Single and Double
Density Diskette Drives
On-Board SBX Bus for Additional
Functions
User-Programmable Drive Parameters
allow Wide Choice of Drives

Phase Lock Loop Data Separator
Assures Maximum Data Integrity
Read and Write on Single or Multiple
Sectors
Single

+ 5V Supply

Capable of Addressing 16M Bytes of
System Memory

The Intel iSBC 208 Flexible Disk Controller is a diskette controller capable of supporting virtually any sott-sectored, double density or single density diskette drive. The standard controller can control up to four drives with
up to eight surfaces. In addition to the standard IBM 3740 formats and IBM System 34 formats, the controller
supports sector lengths of up to 8192 bytes. The iSBC 208 board's wide range of drive compatiblity is
achieved without compromising performance. The operating characteristics are specified under user program
control. The controller can read, write, verify, and search either single or multiple sectors. Additional parallel or
serial I/O capability can be added to the iSBC 208 board via the SBX bus (IEEE 959) connector.

280228-1

'The iSBC" 208 is also manufactured under product code piSBC" 208 or siSBC" 208 by Intel Puerto Rico, Inc., or Intel Singapore, Ltd.

10-7

September 1989
Order Number: 280228-002

iSBC® 208

BLOCK DIAGRAM
iSBC® 208 Flexible Disk Controller Block Diagram

STANDARD DRIVES

MINI· DRIVES
C51/o",

II"'

)

J1
CONNECTOR

J.
CONNECTOR

n
~

ISB.
CONNECTOR

f-f.-

1237
DMAC

i II 0-

I
BUS
CONTROLLER

I
TIMING

AU.
PORT

PLL

i l'

:::D

!
SEOMENT
REOISTER

ADDER

"I'

DECODE

ADDRESS
BUFFER

C24'1

.utor office, or from Intel
Literature Department, 3065 Bowers Avenue, Santa,
Clara, CA 95051.

ORDERING INFORMATION
Order Code Description
SBC208

10-10

Flexible Disk Controller

iSBC® 215*
GENERIC WINCHESTER CONTROLLER

•
•
•

Controls up to Four 5%" , 8" or 14"
Winchester Disk Drives from Over Ten
Different Vendors
Compatible with Industry Standard
MULTIBUS® (IEEE 796) Interface
Supports ANSI X3T9/1226 Standard
Interface

Diagnostics and ECC
• On-Board
Full Sector Buffering On-Board
• Capable
Directly Addressing 16 MB
• of SystemofMemory
Removable Back-up Storage Available
• Through
the iSBXTM 218A Flexible Disk
Controller and the iSBX 217C %" Tape
Interface Module

•
8089 I/O Processor Provides
• Intel
Intelligent DMA Capability

Software Drivers Available for iRMXTM
and Xenix* Operating Systems

Using VLSI technology, the iSBC 215 Generic Winchester Controller combines three popular Winchester
controllers onto one MULTIBUS board: the iSBC 215A open loop controller, the iSBC 215B closed loop
controller, and an ANSI X3T9/1226 standard interface controller. The combined functionality of the iSBC 215
supports up to four 5%",8" or 14" Winchester drives from over 10 different vendors. Integrated back-up is
available via two SBX bus modules; the iSBX 218A module for floppy disk drives and the iSBX 217C module
for %" tape units.
From the MULTIBUS side, the iSBC 215 appears as one standard software interface, regardless of the drive
type used. In short, the iSBC 215 allows its user to change drive types without rewriting software. The iSBC
215 is totally downward compatible with its predecessors, the iSBC 215A and 215B controller; allowing existing iSBC 215A and 215B users to move quickly to the more powerful iSBC 215. In addition, the iSBC 215
directly addresses up to 16 megabytes of system memory.

210618-1

Xenix is a trademark of Microsoft Corp.
·The iSSCI!> 215 is also manufactured under product code piSSC® 215 by Intel Puerto Rico, Inc.

10-11

September 1989
Order Number: 210618-003

isec® 215
BLOCK DIAGRAMS
r---------~---------------l
I
J3
J4
I

ISBce
MICROCOMPUTER

I
I
I

I
I

I
I
I

lOP

I
I
I

LOCAL
IUS

MULTIBur
INTERFACE

MULTIBUS·
BUS

INTERFACE

I
I

I
I
I
I

SYSTEM
MEMORY
110 COMMUNICA·
TlONS ILOCKS

ROM

RAM

L________1~~2~~E~E~~~~~T~ ~~R~L~~ ~

_______

210618-2

Figure 1. Block Diagram of ISBCII!l215 Generic Winchester Disk Controller

10-12

inter

iSBC® 215

Interface with Shugart/Quantum/RMS Drives

210618-3

NOTE:
1. Shugart SA1000 or RMS Data Express.'

'Data Express is a trademark of Rotating Memory Systems.

Interface with Memorex/Shugart Drlv.es

210618-4

Interface with ANSI Drive

L.....-~---'CONTAOLAND ~

r-____________

-=-===._~..~.=.=.D=M=A=IT=.====~_===============~_.J

210618-5

Interface with PRIAM Drives
L....._~_--' CONTROL AND L..._~,..----'
READtWRITE

READtWRITIE

CONTROL

210618-6

Figure 2. Controller to Drive Interfacing

10-13

intJ

iSBC® 215

SPECIFICATIONS

Equipment Supplied '

Compatibility

iSBC 215 Generic Winchester Controller
Refere,nce Schematic

CPU-Any MULTIBUS computer or system mainframe.
Disk Drives-Winchester Disk Drives; both openloop and closed-loop head positioner types. The following drives are known to be compatible:

Open-Loop
Shugart SA 1000 Series
Shugart SA 4000 Series
Memorex 100 Series
Quantum Q2000 Series
Fujitsu 2301, 2302
CDC 9410
RMS 5Y4" Series
Rodine 5Y4" Series
Ampex 5Y4" Series
CMI 5Y4" Series

Controller-to-drive cabling and connectors are not
supplied with the controller. cables can be fabricated with flat cable and commercially-available connectors as described in the iSBC 215G Hardware
Reference Manual.

Physical Characteristics
Width:

6.75 in. (17.15 cm)

Height:
Length:

0.5 in. (1.27 cm)
12.0 in. (30.48 em)

Shipping Weight: 19 oz. (0.54 kg)
Mounting:

Occupies one slot of iSBC systern' chassis or cardcage/backplane

With an SBX board mounted, vertical height increases to 1.13 in. (2.87 cm).

Closed-Loop

Priam 8" and 14" Drive Series

ANSI
3M 8430 Series
Kennedy 6170 Series
Micropolis 8" Series
Pertec Trackstar Series
Priam 8" Series
Megavault (SLI) 8" Series

SBX Boards
iSBXTM 218A Flexible Disk Controller
iSBXTM 217C Y4" Tape Interface

Electrical Characteristics
Power Requirements
+ 5 VDC@4.52A max
-5 VDC@0.015A max1
. +12 VDC@0.15A max2
-12' VDC@0.055A max1,2

NOTES:
1. On-board regulator and jumper allows -12 VDC
usage from MULTIBUS.
2. Required for some SBX boards.

10-14

inter

iSBC® 215

Data Organization
Sectors/Track(1)
Bytes/Sector

128

256

512

1024

Priam 8"
Priam 14"
RMS/Shugart 8" IQuantuml Ampes/Rodine/CM1
Fujitsu/Memorex
Shugart 14"
CDC Finch
3M (ANSI)
Megavault (ANSI)
Kennedy (ANSI)
Micropolis (ANSI)
Pertec (ANSI)

72
107
54
64
96
64
82
73
74
71
85

42
63
31
38
57
41
51
43
43
44
52

23
35
17
21
31
23
29
21
23
25
29

12
18
9
11
16
12
16
12
12
13
15

NOTE:
1. Maximum allowable for corresponding selection of bytes per sector.

Drives per Controller
5%" Winchester Disk Drives-Up to four RMS, CMI,
Rodine or Ampex drives.
8" Winchester Disk Drives-Up to four ANSI, Shugart, Quantum or Priam drives; up to two Memorex,
CDC, or Fujitsu drives.
14" Winchester Disk Drives-Up to four Priam drivers; up to two Shugart drives.
Flexible Disk Drives-Up to four drives through the
optional iSBX 218A Flexible Disk Controller connected to the iSBC 215 board's iSBX connector.
%" Tape Drives-Up to four drives through the optional iSBX 217C %" Tape Interface Module connected to the iSBC 215 board's iSBX connector.

Humidity-Up to 90% relative humidity without condensation (operating); all conditions without condensation or frost (non-operating).

Reference Manual
144780-iSBC 215 Generic Winchester Controller
Hardware Reference Manual (NOT SUPPLIED)
Reference manuals may be ordered from any Intel
sales representative, distributor office, or from Intel
Literature Department, 3065 Bowers Avenue, Santa
Clara, CA 95051.

ORDERING INFORMATION
Order Code Description
SBC215G

Environmental Characteristics
Temperature-O° to 55°C (operating); -55°C to
+ 85°C (non-operating)

10-15

Generic;: Winchester Controller

iSBC® 220*
SMD DISK CONTROLLER

•
•
•
•

Controls up to Four Soft Sectored SMD
Interface Compatible Disk Drives
12 MB to 2.4 GB per Controller
Compatible with all ISBC®, 80, iSBC® 88,
and ISBC® 86 Single 'Board Computers
Intel 8089 I/O Processor Provides Two
High Speed DMA Channels as well as
Controller Intelligence

•
•
•
•
•

Software Drivers Available for iRMXTM
and XENIX· Operating Systems
On-Board Diagnostic and ECC
Full Sector Buffering On-Board
Capable of Addressing 1 MB of System
Memory
SMD Interface Available on Winchester,
CMD, SMD and Large Fixed-Media
Drives

The iSBC 220 SMD Disk Controller brings very large mass storage capabilities to any iSBC BO, iSBC BB, or
iSBC 86 MULTIBUS@ system. The controller will interface to any soft sectored disk drive conforming to the
industry standard SMD interface. Using simplified cable connections, up to four drives may be connected to
the iSBC 220 Controller Board to give a total maximum capacity of 2.4 gigabytes. The Intel BOB9 I/O Processor
simplifies programming through the use of memory-based parameter blocks. A linked list technique allows the
user to perform multiple disk operations.
'XENIX is a registered trademark of Microsoft.

143283-1

'The ISBC" 220 Is also manufactured under product code piSBC" 220 or siSBC 220 by Intel Puerto Rico, Inc, or Intel Singapore, Ltd,

10-16

October 1989
Order Number: 143283..(103

intJ

iSBC® 220 SMD CONTROLLER

BLOCK DIAGRAMS

r-------------------------lI

I
I
I
I

I....
I

lOP

I
I

lOP
LOCAL

ADD::~TA
LOCAL

IU.
INTERFACE

DIS",

INTERFACE

I
I
I

I
I

JI
IL ________________________________
...,. ... IMD~.....

143283-2

Figure 1. Simplified Block Diagram of ISBC@ 220 SMD Disk Controller

TERMINATOR

READlWRITE
CABLE

CONTROL
CABLE

r------

--I
I

~""-~""'-.....

I
I

I
I
I
IL ________ _

P2
INOTUSEDI
_ _ _ _ _ _ ~~~O~~~ _ _ _ _ _

I
I
I
I
I

MULTIIUS'·
CONNECTOR

MULTlBUS·

143283-3

Figure 2. Typical Multiple Drive System

10-17

inter

ISBCI8l 220 SMD CONTROLLER

SPECIFICATIONS

Data Organization and Capacity

Compatibility

Bytes per Sector(2): 128 256· 521 1024
Sector per Track(2): 108 64 35 18

CPU: Any MULTIBUS computer on system mainframe
Disk Drive: Any soft sectored SMD interface-compatible disk drive

Equipment Supplied
iSBC 220 SMD Disk Controller
Reference schematic
Controller-to-drive cabling and connectors are not
supplied with the controller. Cables can be fabricated with flat cable and commercially-available connectors as described in the iSBC 220 SMD Disk
Controller Hardware Refer~nce Manual.

Physical Characteristics
Width: 6.75 in (17.15 cm)
Height: 0.5 in (1.27 cm)
Length: 12.0 in. (30.48 cm)
Shipping Weight: 19 oz. (0.54 kg)
Mounting: Occupies one slot of iSBC system chassis or cardcage/backplane

NOTE:
2. Software selectable.
Table 1. Drive Characteristics (Typical)
Disk (spindle) Speed 3600 rpm
Tracks per Surface 823
Head Positioning
Closed loop servo type, track
following
Access Time
Track to Track
6 ms
Average
30 ms
Maximum
55 ms
Data Transfer Rate 1.2 megabytes/second
Storage Capacity
12 to 2.4 gigabytes

Environmental Characteristics
Temperature: O·C to 55·C (operating); -55·C to
+ 85·C (non-operating)
Humidity: Up to 90% relative humidity without condensation (operating); all conditions without condensation or frost (non-operating)

Reference Manual
121597-iSBC 220 SMD Disk Controller Hardware
Reference Manual (NOT SUPPLIED)

Electrical Characteristics

Reference manuals may be ordered from any Intel
sales representative, distributor office, or from Intel
Literature Department, 3065 Bowers Avenue, Santa
Clara, CA 95051.

Power Requirements:
+ 5 VCD @ 3.25A max
-5 VDC @ 0.75A max(1)
NOTE:
1. On-board voltage regulator allows optional
-12 VDC usage from MULTIBUS.

ORDERING INFORMATION
Order Code Description
SBC220
SMD Disk Controller

10-18

MULTIBUS® I
Serial Communication Boards

iSBC® 548/549* TERMINAL CONTROLLERS

HIGH PERFORMANCE TERMINAL CONTROLLER BOARDS FOR
MULTIBUS®I
The iSBC® 548 and iSBC® 549 are intelligent terminal controllers for MULTIBUS®I
applications. The iSBC 548 provides basic multiuser support with 8 channels of RS 232
Ansychronous interface. The iSBC 549 combines 4 serial channels with a real-time clock
and a line printer interface. Acting as intelligent slaves for communication expansion,
these boards provide high performance, low cost solutions for multi-user systems.

FEATURES:
iSBC 548 FEATURES
• Supports eight channels asynchronous
RS232 interface
iSBC 549 FEATURES
• Supports four channels asynchronous
RS232 interface
• Line printer interface
• Real-time clock/calendar with battery
backup

.Init_r
'ell

STANDARD iSBC 548/549 FEATURES
• 8 MHz 80186 Microprocessor
• Supports transfer rates up to 19.2K
Baud
• 128 K Bytes Zero Wait State DRAM (32K
Dual Port)
• Supports Full Duplex Asynchronous
Transmissions
• Jumper selectable memory mapping,
I/O mapping and MULTIBUS Interrupts

The ,SBe· 548/549 's also manufactmed under product code p,SBe· 548/549 by Intel Puerto R,co. Inc

September, 1989

Order Number 280674-002

11-1

FEATURES
CHANNELS

AD0-AD15

Figure 1: iSBC® 548 Functional Block Diagram
PRINTER

CONNECTOR
(1001)

LDAT0LDDAT7
DSRS-DSR8

ADe-AD15

Figure 2: ISBC® 549 Functional Block Diagram

18018611

FIRM·
WARE

iSBC"' 548
CONTROLLER

ISBC® 386112
HOST

CLUSTER
CONTROLLER
MULTIBUS'" SYSTEM BUS

MULTIBUS'" SYSTEM BUS

Figure 3: Terminal/Cluster Controller Application
11·2

iSBC"' 549
CONTROLLER

FEATURES
ASYNCHRONOUS RS232 INTERFACE
SUPPORT
The iSBC@ 548/549 Asynchronous RS232 Internal
support is presented in DTE Configuration. 82530
Serial Communications Controllers (SCCs) provide
channels of half/full duplex serial 1/0. Configurability
of the 82530 allows handling all asynchronous data
formats regardless of data size, number of start or
stop bits, or parity requirements. The synchronous
transmission features of the 82530 are not supported.
An on-chip baud rate generator allows independent
baud rates on each channel. The serial lines can be
brought to the back-panel via 40-pin connectors and
ribbon cable.

LINE PRINTER INTERFACE
The iSBC 549 incorporates a standard line printer
interface compatible with IBM' or Centronics' line
printers. Intelligent buffering on the iSBC 549 allows
the CPU to offload printing tasks and return to higher
priority jobs.

REAL· TIME CLOCK/CALENDAR
Multibus systems will benefit from the real-time clock
present on the iSBC 549 in applications requiring
time stamp operations, unattended boots and other
calendar requirements. The clOCk/calendar circuit is
backed up by a non-rechargeable battery which
keeps the clock/calendar operating for six months
with all other power off.

8 MHZ 80186 MICROPROCESSOR
The 80186 central processor component provides
high-performance, flexibility, and powerful processing.
The 80186/82530 combination with on-board PROMI
EPROM sites, and dual-port RAM provides the
intelligence and speed to manage multi-user
communications.

MEMORY
The iSBC 548/549 have three areas of memory onboard: dual-port RAM, private RAM, and EPROM.
Each board contains 128K bytes of on-board RAM,
32K bytes of dual-port RAM can be addressed by
other MULTI BUS boards. The dual port memory is
configurable in a 16M byte address space on 32K
byte boundaries as addressed from the MULTIBUS
port. The starting address is jumper selectable.
The second area of memory is 96K bytes of private
RAM which is addressable by the 80186 on-board.
The third area of memory is EPROM memory
expansion. Two 28-pin JEDEC sockets are provided.
These sockets come populated with two EPROMs
which contain the controller firmware. The boards
can support 2764, 27128 and 27256 EPROMs, giving
a total capacity of 64K bytes. The EPROM runs with
zero wait states if EPROMs of access times 250 ns or
less are used. No jumper changes are needed to
access different size EPROMs.

WORLDWIDE SERVICE AND SUPPORT
Intel provides support for board repair or on-site
service. Development options include phone support,
subscription service, on-site consulting, and customer
training.

QUALITY AND RELIABILITY
The iSBC 548 and iSBC 549 are designed and
manufactured in accordance with Intel's high quality
standards. We then verify quality through rigorous
testing in our state-of-the-art Environmental Test
Laboratory.

TRANSFER RATES UP TO 19.2K BAUD
Collectively, each board has dual-port RAM providing
an on-board buffer to handle incoming and outgoing
messages at data rates up to 19.2K baud. The
resident firmware supports asynchronous RS232
serial channels, provides modern control and
performs power-up diagnostics. Each serial channel
can be individually programmed to different baud
rates to allow system configurations with differing
terminal types.

• IBM IS a trademark of International BUSiness Machines
* Centronics IS a registered trademark of CentroniCS, Inc

11-3

SPECIFICATIONS
SERIAL COMMUNICATIONS
CHARACTERISTICS

ENVIRONMENTAL CHARACTERISTICS
Temperature -

Asynchronous only
6-8 bit character length
1, 1V2, or 2 stop bits per character
Parity
Programmable clock
Break Generation
Framing error detection

Humidity -

PHYSICAL CHARACTERISTICS
Width
Length
Height
Weight

Baud Rates
The on-board firmware can automatically detect
and set baud rates of 150,300,600,1200,4800,
9600 and 19200. Other baud rates can be set by
the host.

iSBC 549
30.34cm (12.00 in)
16.87cm (6.75 in)
1.27 cm (.5 in)
358 gm (12.5 oz)

Maximum Power Required per Voltage
Current
Power
Voltage
(Volts)
(Amps)
(Watts)
iSBC 548
+ 5
3.49
17.5
+12
.14
1.7
-12
.11
1.3
iSBC 549
+ 5
3.26
16.3
+12
.07
.8
-12
.06
.7

These signals are supported by the iSBC 548/549
Controller and on-board firmware. All signals may
not.be supported by the host operating system.

MEMORY
On-Board RAM - 128K bytes total
Private RAM - 96K bytes
Dual Port Ram - 32K bytes, can be addressed from
MULTIBUS interface at any 32K
boundary between 80000H and
F8000H or between F80000H and
FF8000H.
On-Board
Capacity
16K
32K
64K

iSBC 548
30.34cm (12.00 in)
16.87cm (6.75 in)
1.27 cm (.5 in)
400 gm (14 oz)

POWER REQUIREMENTS

Serial RS232C Signals Supported
CD Carner Detect
, RXD Receive Data
TXD Transmit Data
DTR Data Terminal Ready
SG Signal Ground
DSR Data Set Ready
RTS Ready to Send
CTS Clear to Send
RI Ringer Indicator

EPROM OptionsComponents
2764
27128
27256

0 to 55°C at 200 Linear Feet/Minute
(LFM) Air Velocity
5% to 90% non-condensing (25 to
70° C)

ORDERING INFORMATION
Order Code Description
SBC548
SBC549

8 Channel High Performance Terminal
Controller
4 Channel High Performance Terminal
Controller with Line Printer/Clock

REFERENCE MANUALS
iSBC 546/547/548/549 High Performance Terminal
Controller Hardware Reference Manual-Order
Number 122704
For more information or the number of your nearest
Intel sales office, call 800-548-4725 (good in the U.S.
and Canada).

Start
Address
FCOOOH
F8000H
FOOOH.

MULTIBUS SYSTEM BUS. INTERFACE
The iSBC 548/549 boards meet MULTIBUS (IEEE
796) bus specifications 016 M24 116 VO E.

DEVICE DRIVERS
Check the latest release of the iRMX I, II & III
operating systems for details.

11-4

'iSBC® 188/56*
ADVANCED COMMUNICATING COMPUTER
Single Board Computer or
• iSBC®
Intelligent Slave Communication Board
Serial Communications Channels,
• 8Expandable
to 12 Channels on a Single
MULTIBUS® Board
8 MHz 80188 Microprocessor
• Supports
Interface on 6
• Channels,RS232C
RS422A/449 or RS232C
Interface Configurable on 2 Channels
Supports Async, Bisync HDLC/SDLC,
• On-Chip
Baud Rate Generation, Half!

On-Board DMA Channels for Serial
• 71/0,280188
DMA Channels for the
iSBX Bus Interface
MULTIBUS Interface for System
• Expansion
and Multimaster
Configuration
iSBX Connectors for Low Cost I/O
• Two
Expansion
256K Bytes Dual-Ported RAM On-Board
• Two
28-pin JEDEC PROM Sites
• Expandable
to 6 Sites with the iSBC

Full-Duplex, NRZ, NRZI or FM
Encoding/Decoding

•

341 MULTIMODULE Board for a
Maximum of 192K Bytes EPROM
Resident Firmware to Handle up to 12
RS232C Async Lines

The iSBC 188/56 Advanced Communicating Computer is an intelligent 8-channel single board computer. This
iSBC board adds the 8 MHz 80188 microprocessor-based communications flexibility to the Intel line of MULTIBUS OEM microcomputer systems. Acting as a stand-alone CPU or intelligent slave for communication expansion, this board provides a high performance, low-cost solution for multi-user systems. The features of the
iSBC 188/56 board are uniquely suited to manage higher-layer protocol requirements needed in today's data
communications applications. This single board computer takes full advantage of Intel's VLSI technology to
provide state-of-the-art, economic, computer based solutions for OEM communications-oriented applications.
'The iSBC'" 188/56 is also manufactured under product code piSBC 188/56 or siSBC 188/56 by Intel Puerto Rico, Inc. or Intel Singapore, Ltd.

280715-1

'IBM is a registered trademark of International Business Machines
'UNIX is a trademark of Bell Laboratories
'XENIX is a trademark of Microsoft Corporation

11-5

October 1989
Order Number: 280715-003

intJ

ISsC® 188/56 ADVANCED COMMUNICATING COMPUTER

OPERATING ENVIRONMENT
The iSBC 188/56 board features have been designed to meet the needs of numerous communications applications. Typical applications include:
1. Terminal/cluster controller
2. Front-end processor
3. Stand-alone communicating computer

Terminal/Cluster Controller
A terminal/cluster controller concentrates communications, in a central area of a system. Efficient
handling of messages coming in or going out of the
system requires sufficient buffer space to store
messages and high speed I/O channels to transmit
messages. More sophisticated applications, such as
cluster controllers, also require character and format
conversion capabilities to allow different types of terminals to be attached.
'
The iSBC 188/56 Advanced Communicating Computer is well suited for multi-terminal systems (see
Figure 1). Up to 12 serial channels can be serviced
in multi-user or cluster applications by adding two
iSBX 354 MULTIMODULE bo'ards. The dual-port
RAM provides a large on-board buffer to handle

incoming and outgoing messages at data rates up to
19.2K baud. Two channels are supported for continuous data rates greater than 19.2K baud. Each serial
channel can be individually programmed for different
baud rates to allow system configurations with differing terminal types. The firmware supplied on the
iSBC 188/56 board supports up to 12 asynchronous
RS232C serial channels, provides modem control
and performs power-up diagnostics. The high performance of the on-board CPU provides intelligence
to handle protocols and character handling typically
assigned to the system CPU. The distribution of intelligence results in optimizing system performance
by releasing the system CPU of routine tasks.

Front-End Processor
A front-end processor off-loads a system's central
processor of tasks such as data manipulation and
text editing of characters collected from the attached terminals. A variety of terminals require flexible terminal interfaces. Program code is often dynamically downloaded to the front-end processor
from the system CPU. Downloading code requires
sufficient memory space for protocol ,handling and
program code. Flow control and efficient handling of
interrupts require an efficient operating system to
manage the hardware,and software resources.

ISIX'" 354
BOARD

c:::::::::J

c::=:::::J

ISace 188168
BOARD

ISIC. 388/12 BOARD

IRiAREI

SYSTEM
PROCESSOR
MULTIIUS. SYSTEM IUS

280715-2

Figure 1. Terminal/Cluster Controller Application
11-6

intJ

iSBC® 188/56 ADVANCED COMMUNICATING COMPUTER

The iSBC 188/56 board features are designed to
provide a high performance solution for front-end
processor applications (see Figure 2). A large
, amount of random access memory is provided for
dynamic storage of program code. In addition, local
memory sites are available for storing routine programs such as X.25, SNA or bisync protocol software. The serial channels can be configured for links
to mainframe systems, point-to-point terminals, modems or multidrop configurations.

MULTIBUS interface can be used to access additional system functions. Floppy disk control and
graphics capability can be added to the iSBC standalone computer through the iSBX connectors.

ARCHITECTURE
The four major functional areas are Serial I/O, CPU,
Memory and OMA. These areas are illustrated in Figure 4.

Stand-Alone Application
Serial 110

A stand-alone communication computer is a complete computer system. The CPU is capable of managing the resources required to meet the needs of
multi-terminal, multi-protocol applications. These applications typically require multi-terminal support,
floppy disk control, local memory allocation, and
program execution and storage.

Eight HOLC/SOLC serial interfaces are provided on
the iSBC 186/56 board. The serial interface can be
expanded to 12 channels by adding 2 iSBX 354
MULTIMOOULE boards. The HOLC/SOLC interface
is compatible with IBM· system and terminal equipment and with CCID's X.25 packet switching interface.

To support stand-alone applications, the iSBC
166/56 board uses the computational capabilities of
an on-board CPU to provide a high-speed system
solution controlling 6 to 12 channels of serial I/O
(see Figure 3). The local memory available is large
enough to handle special purpose code, execution
code and routine protocol software. The

•

Four 82530 Serial Communications Controllers
(SCC) provide eight channels of half/full duplex serial I/O. Six channels support RS232C interfaces. Two channels are RS232C/422/449 configurable and can be tri-stated to allow multidrop networks.
The 82530 component is designed to satisfy several
serial communications requirements; asynchronous,

o
o

ISax'" 354

IS8X'" 354

BOARD

BOARO

c::=:::::J r:=:=:J
ISBC'" 188/56
r---.r---,

BOARD

MULTI8US" SYSTEM BUS

280715-3

Figure 2_ Front-End Processor Application
11-7

inter

iSBC@ 188/56 ADVANCED COMMUNICATING COMPUTER

byte-oriented synchronous (HOLC/SOLC) modes.
The increased capability at the serial controller point
results in off-loading the CPU of tasks formerly asSigned to the CPU or its associated hardware. Configurability of the 82530 allows the user to configure
it to handle all asynchronous data formats regardless of data size, number of start or stop bits, or
parity requirements. An on-chip baud rate generator
allows independent baud rates on each channel.

Central CPU
The 80188 central processor component provides
high performance, flexibility and powerful processing. The 80188 component is a highly integrated microprocessor with an '8-bit data bus interface and a
16-bit internal architecture to give high performance.
The 80188 is upward compatible with 86 and 186
software.

The clock can be generated either internally with the
SCC chip, with an external clock or via the NRZ1
clock encoding mechanism.
All eight channels can be configured as Data Terminal Equipment (OTE) or Data Communications
Equipment (OCE). Table 1 lists the interlaces supported.
Table 1. ISBC® 188/56 Interface Support
Connection

Synchronous

Asynchronous

Modem to Direct Modem to Direct
Point-to-Point
Multidrop
Loop

Channels
o and 1

Channels
' oand 1

N/A

The 80188/82530 combination with on-board
PROM/EPROM sites, and dual-port RAM provide
the intelligence and speed to manage multi-user,
multi-protocol communication operations.

Memory
There are two areas of memory on-board: dual-port
RAM and universal site memory. The iSBC 188/56
board contains 256K bytes of dual-port RAM that is
addressable by the 80188·on-board. The dual-port
memory is configurable anywhere in a 16M byte address space on 64K byte boundaries as addressed
from the MULTIBUS port. Not all of the 256K bytes
are visible from the MULTIBUS bus side. The
amount of dual-port memory visible to the

··AIIS channels are denoted by X.

80188

EXECUTION

CODE

STAND-ALONE
'PROCESSOR

MULTlBUS" SYSTEM BUS

280715-4

Figure 3. Stand-Alone Application
11-8

inter

ISBC® 188/56 ADVANCED COMMUNICATING COMPUTER

MULTIBUS side can be set (with jumpers) to none,
16K bytes, or 48K bytes. In a multiprocessor system
these features provide local memory for each processor and shared system memory configurations
where the total system memory size can exceed one
megabyte without addressing conflicts.

On-Board DMA
Seven channels of Direct Memory Access (DMA)
are provided between serial I/O and on-board dual
port RAM by two 8237-5 components. Each of channels 0, 1, 2, 3, 5, 6, and 7 is supported by their own
DMA line. Serial channels 0 and 1 are configurable
for full duplex DMA. Configuring the full duplex DMA
option for Channels 0 and 1 would require Channels
2 and 3 to be interrupt driven or polled. Channel 4 is
interrupt driven or polled only.

The second area of memory is universal site memory providing flexible memory expansion. Two 28-pin
JEDEC sockets are provided. One of these sockets
is used for the resident firmware as described in the
FIRMWARE section.

Two DMA channels are integrated in the 80188
processor. These additional channels can be connected to the iSBX interfaces to provide DMA capability to iSBX MULTIMODULE boards such as the
iSBX 218A Floppy Disk Controller MULTIMODULE
board.

The default configuration of the boards supports
16K byte EPROM devices such as the Intel 27128
component. However, these sockets can contain
ROM, EPROM, Static RAM, or EEPROM. Both sockets must contain the same type of component (i.e.
as the first socket contains an EPROM for the resident firmware, the second must also contain an
EPROM with the same pinout). Up to 32K bytes can
be addressed per socket giving a maximum universal site memory size of 64K bytes. By using the iSBC
341 MULTIMODULE board, a maximum of 192K
bytes of universal site memory is available. This provides sufficient memory space for on-board network
or resource management software.

OPERATING SYSTEM SUPPORT
Intel offers run-time foundation software to support
applications that range from general purpose to
high-performance solutions.

SERIAL
COMMUNICATIONS
CONTROLLERS
SCC(4)

CHANNELS

CHANNEL

7-2

1-0

RS232C

RS232CI
4221449

256KRAM

MULTIBUS· SYSTEM BUS

280715-5

Figure 4. Block Diagram of iSBC® 188/56 Board

11-9

intJ

iSBC® 188/56 ADVANCED COMMUNICATING COMPUTER

The iRMX Operating System provides a rich set of
features and options to support sophisticated standalone communications applications on the iSBC
188/56 Advanced Communicating Computer. If the
iSBC 188/56 board is acting as an intelligent slave
in a system environment, an iRMX driver resident in
the host CPU is available.

multiple persons running independent, terminal-oriented jobs.

FIRMWARE

The System Debug Monitor (SDM) supports target
system debugging for the iSBC 188/56 Advanced
Communicating COMMputer board. The monitor
contains the necessary hardware, software and documentation required to interface the iSBC 188/56
target system to an Intel microcomputer development system for d~bugging application software.
The XENIX' Operating System includes a software
driver for the iSBC 188/56 board (and up to two
iSBX 354 MULTIMODULE Boards) acting as an intelligent slave for multi-user applications requiring

The iSBC 188/56 Communicating COMMputer
board is supplied with resident firmware that supports up to 12 RS232C asynchronous serial channels. In addition, the firmware provides a facility for a
host CPU to download and execute code on the
iSBC 188/56 board. Simple power-up confidence
tests are also included to provide a quick diagnostic
service. The firmware converts the iSBC 188/56
COMMputer board to a slave communications controller. As a slave communications controller, it requires a separate MULTIBUS host CPU board and
requires the use of MULTIBUS interrupt line to signal
the host processor. Table 2 summarizes the features of the firmware.

Table 2. Features of the iSBC® 188/56 Firmware
Feature

Description

Asynchronous Serial
Channel Support

Supports the serial channels in asynchronous ASCII mode.
Parameters such as baud rate, parity generation, parity
checking and character length can be programmed
independently for each channel.

Block Data Transfer
(On Output)

Relieves the host CPU of character-at-a-time interrupt
processing. The iSBC 188/56 board accepts blocks of data for
transmission and interrupts the processor only when the entire
block is transmitted.

Limited Modem Control

Provides software control of the Data Terminal Ready (DTR)
line on all channels. Transitions on the Carrier Detect (CD) line
are sensed and reported to the host CPU.

Tandem Modem Support

Transmits an XOFF character when the number of characters
in its receive buffer exceeds a threshold value and transmits an
XON character when the buffer drains below some other
threshold.

Download and
Execute Capability

Provides a capability for the host CPU to load code anywhere in
the address space of the iSBC 188/56 board and to start
executing at any address in its address space.

Power Up
Confidence Tests

On board reset, the firmware executes a series of simple tests
to establish that crucial components on the board are
functional.

11-10

inter

ISBC® 188/56 ADVANCED COMMUNICATING COMPUTER

There are 5 levels of interrupts internal to the 80188
processor. Another 8 levels of interrupts are available from the 80130 component. Of these 8, one is
tied to the programmable interrupt controller (PIC) of
the 80188 CPU. An additional 8 levels of interrupts
are available at the MULTIBUS interface. The iSBC
188/56 board does not support bus vectored interrupts. Table 3 lists the possible interrupt sources.

INTERRUPT CAPABILITY
The iSBC 1BB/56 board has two programmable interrupt controllers (PICs). One is integrated into the
B01BB processor and the other in the B0130 component. The two controllers are configured with the
B0130 controller as the master and the B01BB controller as the slave. Two of the B0130 interrupt inputs
are connected to the B2530 serial controller components to provide vector interrupt capabilities by the
serial controllers. The iSBC 1BB/56 board provides
22 interrupt levels. The highest level is the NMI
(Non-Maskable Interrupt) line which is directly tied to
the B01 B8 CPU. This interrupt is typically used for
signaling catastrophic events (e.g. power failure).

SUPPORT FOR THE 80130
COMPONENT
Intel does not support the direct processor execution of the iRMX nucleus primitives from the 80130
component. The 80130 component provides timers
and interrupt controllers.

Table 3. Interrupt Request Sources
Function

Number of
Interrupts

MULTIBUS Interface
INTO-INT7

Requests from MULTIBUS resident peripherals or other
CPU boards.

82530 Serial Controllers

Transmit buffer empty, receive buffer full and channel
errors 1 and external status.

Internal 80188
Timer and DMA

Timer 0, 1, 2 outputs and 2 DMA channel interrupts.

80130 Timer Outputs

Timer 0, 1, 2 outputs of 80130.

Interrupt from Flag
Byte Logic

Flag byte interrupt set by MULTIBUS master (through
MULTIBUS® I/O Write).

Bus Flag Interrupt

Interrupt to MULTIBUS® (Selectable for INTO to INT7)
generated from on-board 801 B8 110 Write.

SBX Connectors

Function determined by iSBX board.

SBXDMA

DMA interrupt from iSBX (TDMA).

Bus Fail-Safe Timeout
Interrupt.

Indicates iSBC 188/48 board timed out either waiting for
MULTIBUS access or timed out from no acknowledge
while on MULTIBUS System Bus.

Latched Interrupt

Converts pulsed event to a level interrupt. Example:
8237A-5 EOP.

OR-Gate Matrix

Concentrates up to 4 interrupts to 1 interrupt (selectable
by stake pins).

Ring Indicator
Interrupt

Latches a ring indicator event from serial channels 4, 5,
6,or7.

NOR-Gate
Matrix

Inverts up to 2 interrupts into 1 (selectable by stake
pins).

Device

11-11

8 per 82530
Total = 32
5

4 (Two per
Connector)
2

inter

ISBC® 188/56 ADVANCED COMMUNICATING COMPUTER

EXPA~SION

SPECIFICATIONS

EPROM Expansion

Word Size

Memory may be expanded by adding Intel compatible memory expansion boards. The universal site
'memory can be expanded to six sockets by adding
the iSBC 341 MULTIMODULE board for a maximum
total of 192K bytes of universal site memory.

Instruction-8, 16, 24 or 32 bits
Data Path-8 bits
Processor Clock
82530 Clock
·8 MHz
4.9152 MHz

DMAClock
4MHz

Dual Port RAM

. iSBXTM 1/0 Expansion Bus (IEEE 959)
Two 8-bit iSBX bus connectors are provided on the
iSBC 188/56 board. Using iSBX modules additional
functions can be added to extend the 110 capability
of the board. In addition to specialized or custom
designed iSBX boards, there is a broad range of
iSBX boards from Intel including serial and parallel
110, analog 110, and IEEE 488 GPIB, boards.
The· serial 110 SBX boards available include the
iSBX 354 Dual Channel Expansion MULTIMODULE
board. Each iSBX 354 MULTIMODULE board adds
two channels of serial 110 to the iSBC 188/56 board
for a maximum of twelve serial channels. The 82530
serial communications controller on the MULTIMODULE board handles a large variety of serial
communications protocols. This is the same serial
controller as is used on the iSBC 188/56 board to
offer directly compatible expansion capability for the
iSBC 188/56 board.

iSBC 188/56 Board-256 bytes
As viewed from the 80188-64K bytes
As viewed from the MULTIBUS System BusChoice: 0, 16K or 48K

EPROM
iSBC 188/56
On Board
Size
Address Ranlle
Capacity
Board Using:
2732
2764
27128
27256
27512

8K bytes
4K
8K 16K bytes
16K 32K bytes
32K 6.4Kbytes
64K 128K bytes

FEOOO-FFFFFH
FCOOO-FFFFFH
F8000'-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH

Memory Expansion
MULTIBUS® INTERFACE
The iSBC 188/56 board can be a MULTIBUS master
or intelligent slave in a multimaster system. The
iSBC 188/56 board incorporates a flag byte signalling mechanism for use in multiprocessor environments where the iSBC 188/56 board is acting as an
intelligent slave. The mechanism provides an interrupt handshake from the MULTIBUS System Bus to
the on-board-processor and vice-versa.
The Multimaster capabilities of the iSBC 188/56
board offers easy expansion of processing capacity
and the benefits of multiprocessing. Memory and
110 capacity may be expanded and additional functions added using Intel MULTIBUS compatible expansion boards.

EPROM with
ISBC 341
Board Using:

Capacity

Address Range

2732
2764
27128
27256

24K bytes
48K bytes
96K bytes
192K bytes

F8000-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH
COOOO-FFFFFH

1/0 Capacity
Serial-8 programmable lines using four 82530 components
SBX Bus-2 SBX single-wide boards

11-12

inter

iSBC® 188/56 ADVANCED COMMUNICATING COMPUTER

Serial Communications Characteristics

SERIAL RS232C SIGNALS

Synchronous-Internal or external character synchronization on one or two synchronous characters

CD
CTS
DSR
DTE TXC
DTR
RTS
RXC
RXD
SG
TXD
RI

Asynchronous-5-8 bits and 1, 1%. or 2 stop bits
per character; programmable clock factor; break detection and generation; parity. overrun. and framing
error detection.

Baud Rates
Synchronous
X1 Clock

Carrier
Clear to Send
Data Set Ready
Transmit Clock
Data Terminal Ready
Request to Send
Receive Clock
Receive Data
Signal Ground
Transmit Data
Ring Indicator

RS422A1449 SIGNALS

Baud Rate

82530 Count Value
(Decimal)

64000
48000
19200
9600
4800
2400
1800
1200
300

36
49
126
254
510
1022
1363
2046
8190

Receive Common
Receive Data
Receive Timing
Send Data
Terminal Timing

RC
RD
RT

SO
TT

Environmental Characteristics
Temperature: 0 to 55°C at 200 Linear Feet/Min.
(LFM) Air Velocity
Humidity:

Asynchronous
X16Clock

to 90%. non-condensing (25°C to
70°C)

Physical Characteristics

Baud Rate

82530 Count Value
(DeCimal)

19200
9600
4800
2400
1800
1200
300
110

6
14
30
62
83
126
510
1394

Width:
Length:
Height:
Weight:

30.48 cm (12.00 in)
17.15 cm (6.75 in)
1.04 cm (0.41 in)
595 gm (21 oz)

Electrical Characteristics
The power required per voltage for the iSBC 188/56
board is shown below. These numbers do not include the current required by universal memory sites
or expansion modules.

Interfaces
iSBXTM BUS
The iSBC 188/56 board meets IEEE 959 compliance level 0818 DMA

Voltage
(Volts)

Current
(Amps)typ.

Power
(Watts) typo

+5
+12
-12

4.56A
0.12A
0.11A

22.8W
1.5W
1.3W

Reference Manual
iSBC 188/56 Advanced Data Communications Computer Reference Manual Order Number 148209.

MULTIBUS@ SYSTEM BUS
The iSBC 188/56 board meets IEEE 796 compliance level MasterlSlave 08 M24 116 VO EL.

ORDERING INFORMATION
Order Code
SBC188/56

11-13

Description
8-Serial Channel Advanced Communicating Computer

iSBC® 544A*
INTELLIGENT COMMUNICATIONS CONTROLLER

•
•
•
•
•

ISBC® Communications Controller
Acting as a Single Board
Communications Computer or an
Intelligent Slave for Communications
Expansion
On-Board Dedicated 8085A
Microprocessor Providing
Communications Control and Buffer
Management for Four Programmable
Synchronous/ Asynchronous Channels
Sockets for Up To 8K Bytes of EPROM
16K Bytes of Dual Port DynamiC Read/
Write Memory with On-Board Refresh
Extended MULTIBUS® Addressing
Permits Board Partitioning into
16K-Byte Segments in a 1-Megabyte
Address Space

Programmable Parallel I/O Lines
• Ten
Compatible with Bell 801 Automatic
Calling Unit
Levels of Programmable
• Twelve
Interrupt Control
Individual Software Programmable
• Baud
Rate Generation for Each Serial
I/O Channel
Independent Programmable
• Three
Interval Timer/Counters
Interface Control for Auto Answer and
• Auto
Originate Modem

The iSBC 544A Intelligent Communications Controller is a member of Intel's family of MULTIBUS® singleboard computers, memory, 110, and peripheral controller boards. The iSBC 544A board is a complete communications controller on a single 6.75 x 12.00 inch printed circuit card. The on-board SOS5A CPU may perform
local communications processing by directly interfacing with on-board read/write memory,' nonvolatile read
only memory, four synchronous/asynchronous serial 110 ports, RS232/RS366 compatible parallel 110, programmable timers, and programmable interrupts.

280239-1

'The isec- 544A Is also manufactured under product code piSeC- 544A or siSC- 544A by Intel Puerto Rico. Inc.• or Intel Singapore. Ltd.

11-14

September 1989
Order Number: 280239-002

intJ

iSBC® 544 COMMUNICATIONS CONTROLLER

BLOCK DIAGRAM

PROGRAMMABLE 1/0

-r - -------1
• INTERRUPTS'
RECEIVER READY
TRANSlimER READY

I INTERRUPTS·

RINO INDICATOR
CARRIER DETECT

I
I

tlK ••

DYNAMIC
RAil

I
I
I
I
I

MULTIBUS

260239-2

iSBC® 544A Intelligent Communications Controller Block Diagram

11-15

inter

ISBC@ 544 COMMUNICATIONS CONTROLLER

SPECIFICATIONS

Memory Capacity

Serial Communications Characteristics

On-Board ROM/PROM installed ROM or EPROM

Synchronous -

5-8 bit characters; automatic
sync insertion; parity.

On-Board Static RAM -

Asynchronous -

5-8 bit characters; break character generation; 1, 1%, or 2
stop bits; false start bit detection; break character detection.

On-Board Dynamic RAM (on-board access) 16K bytes. Integrity maintained during power failure
with'user-furnished batteries (opt,ional)

Frequency (KHz)(1)
Baud Rate (Hz)(2)
(Software
Selectable)
Synchronous Asynchronous

153.6
76.8
38.4
19.2
9.6
4.B
6.9B

3B400
19200
9600
4800
69BO

+64

9600
4BOO
2400
1200
600
300

2400
1200
600
300
150
75
110

Memory Addressing
On-Board ROM/PROM - O-OFFF (using 2716
EPROMs or masked ROMs); 0-1FFF (using 2732A
EPROMs)
On-Board Static RAM -

808SA CPU
Word Size -

B, 16 or 24 bits/instruction; B bits of
data

Cycle Time -

1.45/P.s ± 0.01 % for fastest executable instruction; i.e., four clock cycles.

Clock Rate -

2.76 MHz

On-Board Dynamic RAM (MULTIBUS@ access) any 4K increment OOOOO-FFOOO which is switch and
jumper selectable. 4K, BK or 16K bytes can be made
available to the bus by switch selection.

1/0 Capacity
Serial - 4 programmable - channels using four
8251A USARTs
Parallel - 10 programmable lines available for Bell
B01 ACU, or equivalent use. Two auxiliary jumper
selectable Signals

110 Addressing
On-Board Programmable I/O

System Access Time
Dual port memory -

256 bytes: 7FOO-7FFF

On-Board Dynamic RAM (on-board access) 16K bytes: BOOO-BFFF.

NOTES:
1. Frequency selected by I/O writes of appropriate 16-bit
frequency factor to Baud Rate Register.
2. Baud rates shown here are only a sample subset of possible software programmable rates available. Any frequency from 18.75 Hz to 614.4 KHz may be generated utilizing
on-board crystal oscillator and 16-bit Programmable Interval Timer (used here as a frequency divider).

± 0.1 %

256 bytes on B155

On-Board Dynamic RAM (MULTIBUS access) 4K, BK, or 16K bytes available to bus by swtich selection

Baud Rates

+16

4K, or 8K bytes of user

740 ns

NOTE:
Assumes no refresh contention.

11-16

Port

Data

Control

USARTO
USART 1
USART2
USART3
8155 PPI

DO
02
04
06
E9 (PortA)
EA (Port B)
EB (Port C)

01
03
05
07
EB

inter

iSBC® 544 COMMUNICATIONS CONTROLLER

Interrupts

Timers

Address for 8259A Registers (Hex notation, 1/0
address space)
E6
E6
E7
E6
E7
E6

Interrupt request register
In-service register
Mask register
Command register
Block address register
Status (polling register)
~OTE:

Several registers have the same physical address:
Sequence of access and one data bit of the control
word determines which register will respond.
Interrupt levels routed to the 8085 CPU automatically vector the processor to unique memory locations:
24 TRAP
3C RST 7.5
34 RST 6.5
2C RST 5.5

Addresses for 8253 Registers (Hex notation, 1/0
address space)
Programmable Interrupt Timer One
D8
Timer 0
BDGO
D9
Timer 1
BDG1
DA
Timer 2
BDG2
DB
Control register
Programmable Interrupt Timer Two
BDG3
DC
Timer 0
DD
Timer 1
BDG4
DE
Timer 2
TINT1
DF
Control register
Address for 8155 Programmable Timer
E8
Control
Timer (LSB)
TINTO
EO
Timer (MSB)
TINTO
Input Frequencies - Jumper selectable reference
1.2288 MHz ± 0.1 % (0.814 /Ls period nominal) or
1.843 MHz ± 0.1 % crystal (0.542 /Ls period, nominal)

Output Frequencies (at 1.2288 MHz)
Function

Single
TimerICounter

Dual TimerlCounter
(two timers cascaded)

Min

Max

Min

Max

Real-Time Interrupt Interval

1.63/Ls

53.3/Ls

3.26/Ls

58.25 min

Rate Generator (frequency)

18.75 Hz

614.4 KHz

0.00029 Hz

307.2 KHz

11-17

inter

iSBC® 544 COMMUNICATIONS CONTROLLER

Interfaces

Memory Protect

Serial 110 - EIA Standard RS232C signals provided and supported:

An active-low TIL compatible memory protect Signal
is brought out on the auxiliary connector which,
when asserted, disables read/write access to RAM
memory on the board. This input is provided for the
protection of RAM contents during the system power-down sequences.

Carrier Detect
Clear to Send
Data Set Ready
Data Terminal Ready
Request to Send
Receive Clock

Receiver Data
Ring Indicator
Secondary Receive Data*
Secondary Transmit Data *
Transmit Clock
Transmit Data
DTE Transmit clock
• Optional if parallel 110 port is not used as Automatic Calling Unit.

Bus Drivers

Parallel 1/0 - Four inputs am:!' eight outputs (includes two jumper selectable auxiliary outputs). All
signals compatible with EIA Standard RS232C. Directly compatible with Bell Model 801 Automatic
Calling Unit, or equivalent.

Function

Characteristic

Sink
Current (mA)

Data
Address
Commands

Tri-state
Tri-state
Tri-state

50
15
32

NOTE:

Used as a master in the single board communications
computer mode.

On-Board Addressing

Physical Characteristics

All communications to the parallel and serial 110
ports, to the timers, and to the interrupt controller,
are via read and write commands from the on-board
8085A CPU.

Width:

30.48 cm (12.00 inches)

Depth:

17.15 cm (6.75 inches)

Thickness:

1.27 cm (0.50 inch)
3.97 gm p 4 ounces)

. Weight:

11-18

inter

iSBC® 544 COMMUNICATIONS CONTROLLER

Electrical Characteristics
DC Power Requirements
Current Requirements
Configuration
With 4K EPROM
(using 2716)

Vee

Icc

Without EPROM

+5V ±5%
(max)
3.4A max

Voo

± 12V ±5%
(max)

IDD

350 mA max

VBB

= -

Iss

5V(3) ± 5%
(max)

5mAmax

VAA

-12V ±5%
(max)

IAA

200 mA max

3.3Amax

350mAmax

5mAmax

200 mA max

RAM only(1)

390 mA max

176 mA max

5mAmax

RAM(2) refresh
only

390 mA max

20 mA max

5mAmax

NOTES:
1. For operational RAM only, for AUX power supply rating.
2. For RAM refresh only. Used for battery backup requirements. No RAM accessed.
3. VBB is normally derived on·board from VAA, eliminating the need for a VBB supply. If it is desired to supply VBB from the
bus, the current requirement is as shown.

Environmental Characteristics
Operating Temperature: O°C to 55°C (32°F to 131°F)
Relative Humidity: To 90% without condensation

Reference Manual

Reference manuals are shipped with each product
only if designated SUPPLIED (see above). Manuals
may be ordered from any Intel sales representative,
distributor office or from Intel Literature Department,
3065 Bowers Avenue, Santa Clara, California 95051.

ORDERING INFORMATION

502160 - iSBC 544 Intelligent Communications
Controller Board Hardware Reference Manual (NOT
SUPPLIED)

Order Code
SSC 544A

11-19

Description
, Intelligent Communications Controller

iSBC® 534*
FOUR CHANNEL COMMUNICATION EXPANSION BOARD

•

Serial 110 Expansion Through Four
Programmable Synchronous and
Asynchronous Communications
Channels

Software Programmable
• Individual
Baud Rate Generation for Each Serial
110 Channel
Independent Progammable 16-Bit
• Two
Interval Timers
Maskable Interrupt Request
• Sixteen
Lines with Priority Encoded and
Programmable Interrupt Algorithms

Selectable Interface Register
• Jumper
Addresses
16-Bit Parallel 110 Interface Compatible
• with
Bell 801 Automatic Calling Unit
RS232C/CCITT V.24 Interfaces Plus 20
• mA Optically Isolated Current Loop
Interfaces (Sockets)
Programmable Digital Loopback for
• Diagnostics
Control for Auto Answer and
• Interface
Auto Originate Modems

The iSBC 534 Four Channel Communication Expansion Board is a member of Intel's complete line of memory
and 1/0 expansion boards. The iSBC 534 interfaces directly to any single board computer via the MULTIBUS
to provide expansion of system serial communications capability. Four fully programmable synchronous and
asynchronous serial channels with RS232~ buffering and provision for 20 mA optically isolated current loop
buffering are provided. Baud rates, data formats, and interrupt priorities for each channel are individually
software selectable. In addition to the extensive complement of EIA Standard RS232C signals provided, the
iSBC 534 provides 16 lines of RS232C buffered programmable parallel 1/0. This interface is configured to be
directly compatible with the Bell Model 801 automatic calling unit. These capabilities provide a flexible and
easy means for interfacing Intel iSBC based systems to RS232C and optically isolated current loop compatible
terminals, cassettes, asynchronous and synchronous modems, and distributed processing networks.

280238-1,

'The iSBC* 534 is also manufactured under product code piSBC* 534 or siSBC" 534 by Intel Puerto Rico, Inc. or Intel Singapore, Ltd.

11-20

September 1989
Order Number: 280238-002

0
0

"j;
C

::a

"TI

.
0

s::
0

::r
III
::I
::I

!e.

Rs=c
COMPAnBLE
DEVICE

CURRENT
LOOP
OEVICE

RS232C
COIiPATUll.E
DEVICE

CURRENT
LOOP
DEVICE

RS232C
COMPAnBLE
DEVICE

~~~.~

~~~~
.. -"
"y"
..
SEi~~':LE

~":u:

CURRENT

Rsmc

LOOP
DEVICE

COMPAnaLE.

LOOP

DEVICE

CURRENT

Co)
~

0
0

s::
::I
5'

s:::
s:::

!
~ S'
::I

~
} L;/

III

>C
'tI
III
::I
III

(;

»
-I

ID
0

III

:0:-

iil
3

c:
z

to
0

PROGRAMMABLE
nMERS

::I

3
3

to
0

iii'

,j>.

HINES

aUNES

280238-2

ISBC® 534 COMMUNICATION BOARD

SPECIFICATIONS

Interfaces-RS232C Interfaces

Serial Communications Characteristics

EIA Standard RS232C Signals provided and supported:

Synchronous- 5-8 bit characters; internal or external character synchronization; automatic sync insertion.
Asynchronous- 5-8 bit characters; break character
generation; 1, 1%, or 2 stop bits;
false start bit detection.

Receive data
Ring indicator
Secondary receive data
Secondary transmit data
Transmit clock
Transmit data

Carrier detect
Clear to send
Data set ready
Data terminal ready
Request to send
R~ceive clock

Parallel 1/0-8 input lines, 8 output lines, all signals
RS232C compatible

Sample Baud Rates(1)

1/0 Addressing

Frequency(2)
Baud Rate (Hz)
(kHz, Software
Selectable)
Synchronous Asynchronous

153.6
76.8
38.4
19.2
9.6
4.8
6.98

38400
19200
9600
4800
6980

+ 16

+ 64

9600
4800
2400
1200
600
300

2400
1200
600
300
150
75
110

The USART, interval timer, interrupt controller, and
parallel interface registers of the iSBC 534 are configured as a block of 16 110 address locations. The
location of this block is jumper selectable to begin at
any 16-byte 110 address boundary (Le., OOH, 10H,
20H, etc.).

1/0 Access Time

NOTES:
1. Baud rates shown here are only a sample subset of possible software programmable rates available. Any frequency from 18.75 Hz to 614.4 kHz may be generated utilizing
on-board crystal oscillator and 16-bit programmable interval timer (used here as frequency divider).
2. Frequency selected by 1/0 writes of appropriate 16-bit
frequency factor to Baud Rate Register.

400
400
400
400

ns
ns
ns
ns

Compatible Opto-Isolators
Function

Interval Timer and Baud Rate
Generator Frequencies

Supplier

Part Number

Driver

Fairchild
General Electric
Monsanto

4N33

Receiver

Fairchild
General Electric
Monsanto

4N37

Input Frequency (On-Board Crystal Oscillator)1.2288 MHz ± 0.1% (0.813,...s period, nominal)

Function

Real-Time
Interrupt
Interval

Single Timer
Min

Max

1.63 !Ls

53.3 ms

Dual/Timer
Counter
(Two Timers
Cascaded)
Min

Max

3.26 !Ls

58.25
minutes

USART,registers
Parallel 110 registers
Interval timer registers
Interrupt controller registers

Physical Characteristics
Width:

12.00 in. (30.48 cm)

Height: 6.75 in. (17.15 cm)
Depth:

0.50 in. (1.27 cm)

Weight: 14 oz. (398 gm)

Rate
Generator 18.75 Hz 614.4 kHz 0.0029 Hz 307.2 kHz
(Frequency)

11-22

inter

ISBC® 534 COMMUNICATION BOARD

Electrical Characteristics

Reference Manual

Average DC Current

502140-iSBC 534 Hardware Reference Manual

Voltage

Vee
VDO
VAA

= +5V
= +12V
= -12V

(NOT SUPPLIED)

Without
With
Opto-Isolators Opto-lsolators(1)

1.9A, max
275mA, max
250mA, max

1.9A, max
420mA, max
400mA, max

NOTE:
1. With four 4N33 and four 4N37 opto-isolator packages
installed in sockets provided to implement four 20 mA current loop interfaces.

ORDERING INFORMATION
Order Code Description

Environmental Characteristics

SBC534

Operating Temperature: O·C to + 55·C

11-23

Four Channel Communication Expansion Board

iSBC® 88/45*
ADVANCED DATA COMMUNICATIONS
PROCESSOR BOARD

•
•
•
•

•

Three HDLC/SDLC Half/Full-Duplex
Communication Channels-Optional
ASYNC/SYNC on Two Channels
Supports RS232C (Including Modem
Support), CCITT V.24, or RS422A/449
Interfaces
On-Board DMA Supports 800K Baud
Operation
Self-Clocking NRZI SDLC Loop Data
Link Interface
- Point-to-Point
-Multidrop
Software Programmable Baud Rate
Generation

(8088-2) Microprocessor Operates
• 8088
at 8 MHz
337A Numeric Data Processor
• iSBC®
Option Supported
16K Bytes Static RAM (12K Bytes Dual• Ported)
28-Pin JEDEC Sites for EPROM/
• Four
RAM Expansion; Four Additional 28-Pin

•
•

JEDEC Sites Added with iSBC® 341
Board
Two SBX Bus (IEEE 959) Connectors
MULTIBUS® Interface Supports
Multimaster Configuration

The iSBC 88/45 Advanced Data Communications Processor (ADCP) Board adds 8 MHz, 8088 (8088-2) 8-bit
microprocessor-based communications flexibility to the Intel line of MULTIBUS OEM microcomputer systems.
The iSBC 88/45 ADCP board offers asynchronous, synchronous, SDLC, and HDLC serial interfaces for gateway networking or general purpose solutions. The iSBC 88/45 ADCP board provides the CPU, system clock,
EPROM/RAM, serial 1/0 ports, priority interrupt logic, and programmable timers to facilitate higher-level application solutions.

210372-1

·The iSBCaI> 88/45 is also manufactured under product code piSBCII!> 88/45 or siSBCII!> 88/45 by Intel Puerto Rico, Inc. or
Intel Singapore, Ltd.

11-24

September 1989
Order Number: 210372-003

infef

iSBC® 88/45 BOARD

BLOCK DIAGRAM
r-;-]
~

AolD

AIIl

/'----:."""
••::::.-::-:ES:::-S~
••,.,.O::-:
••:::-F--~I :~~~I::~~
ADO AD7 DATA

....

STATIC

12K DUAL PORT

4K lOCA.L

1237,\ 5
....

DUAL
POAT
ACCESS
CONTROL

2tlIT
SLAVE

ADDRESS
DECODE

"- _ _ _ /1

BUFFER

IIULTIBUS
ADORESSINTS

0\0A,./·,lDAI7

CHANNEL C

ICONNECTOR JII

210372-7

Block Diagram of the iSBC® 88/45 ADCP Board

SPECIFICATIONS

Memory Cycle Time

Word Size

RAM: 500 ns (no wait states)
EPROM: jumper selectable from 500 ns to 625 ns.

Instruction: 8, 16, 24, or 32 bits
Data: 8 or 16 bits

On-Board RAM'
KBytes

System Clock

Hex Address
Range

000O-3FFF
16 (total)
1000-3FFF
12 (dual-ported)
'Four iSBC 88/45 EPROM sockets support JEDEC 24/28-

8 MHz: ±0.1%
NOTE:
Jumper selectable for 4 MHz operation with iSBC
337 Numeric Data Processor module or ICE-88
product.

pin standard EPROMs and RAMs (3 sockets); iSBC 341 (4
sockets)

Environmental Characteristics

Cycle Time

Temperature: O'C to + 55'C, free moving air across
the base board and MULTIMODULE board

Basic Instruction Cycle at 8.00 MHz: 1.25 P.S, 250 ns
(assumes instruction in the queue)

Humidity: 90%, non-condensing

NOTE:
Basic instruction cycle is defined as the fastest instruction time (Le., two clock cycles).

Physical Characteristics
Width: 30.48 cm (12.00 in)
Length: 17.15 cm (6.75 in)
Height: 1.50 cm (0.59 in)
Weight: 6.20 gm (22 oz)

11-25

intJ

iSBC® 88/45 BOARD
Serial RS422A1449 SignalsCS
CLEAR TO SEND
OM
DATA MODE
RC
RECEIVE COMMON
RD
RECEIVE DATA
RS
REQUEST TO SEND
RT
RECEIVE TIMING
SC
SEND COMMON
SO
SEND DATA
SG
SIGNAL GROUND
TR
TERMINAL READY
TI
TERMINAL TIMING

Configurations
ISBC® 88/45 Supported Configurations
Connection

Synchronous

Asynchronous

Modem Direct Modem' Direct
Point-to-Point
Multidrop
Loop

N.A.

C
(Only)

'Modem should not respond to break.
• 'Channels A. B. and C denoted by X.

Electrical Characteristics
Memory CapacityI Addressing

OC Power Dissipation-28.3 Watts

On-Board EPROM"
Device

Total
KBytes

Hex Address
Range

2716
2732A
2764
27128

8
16
32
64

FEOOO-FFFFF
FCOOO-FFFFF
F8000-FFFFF
FOOOO-FFFFF

DC Power Requirements
Current Requirements
Configuration
(All Voltages ±5%)
-12V
+5V
+12V
Without EPROM(1)
5.1A
20 rnA 20 rnA
With 8K EPROM
+0.14A
(Using 2716)
With 16K EPROM
+0.20A
(Using 2732A)
With 32K EPROM
+0.24A
(Using 2764)
With 64K EPROM
+0.24A
(Using 27128)

With optional
iSBC® 341 MULTIMODULETM EPROM
Device

Total
KBytes

Hex Address
Range

2716
2732A
2764
27128

16
32
64
128

FCOOO-FFFFF
F8000-FFFFF
FOOOO-FFFFF
EOOOO-FFFFF

NOTE:
1. AS SHIPPED-no EPROMs in sockets. no iSBC 341
module. Configuration includes terminators for two
RS422A1449 and one RS232C channels.

'Four iSBC 88/45 EPROM sockets support JEOEC 24/28pin standard EPROMs and RAMs (static and iRAM. 3 sockets); iSBC 341 sockets also support EPROMs and RAMs.

Timer Input Frequency-8.00 MHz ±0.1%

Serial Communication Characteristics
Supported
Interface
8274(1) RS442A1449
RS232C
CCITIV.24
8274 RS232C
CCITTV.24
8273(3) RS442A1449
RS232C
CCITTV.24

Channel Device
A

Interfaces
IEEE 959 SBX 1/0 Bus Expansion

Serial RS232C SignalsCTS
CLEAR TO SEND
DSR
DATA SET READY
DTE TXC TRANSMIT CLOCK
DTR
DATA TERMINAL READY
FG
FRAME GROUND
RTS
REQUEST TO SEND
RXC
RECEIVE CLOCK
RXD
RECEIVE DATA
SG
SIGNAL GROUND
TXD
TRANSMIT DATA

Max. Baud
Rate
BOOK SOLC/HOLC
125K Synchronous
50K Asynchronous
125K Synchronous(2)
50K Asynchronous
64K SOLC/HOLC(3)
9.6K SELF CLOCKING

NOTES:
1. 8274 supports HOLC/SOLC/SYNC/ASYNC multiprotocol
2. Exceed RS232C/CCITT V.24 rating of 20K baud
3. 8273 supports HOLC/SOLC

11-26

intJ

ISBC@ 88/45 BOARD

Reference Manual

BAUD RATE EXAMPLES (Hz)
8254
Synchronous
Timer Divide
KBaud
CountN
10
26
31
52
104
125
143
167
417
833
EQUATION

800
300
256
154
76.8
64
56
48
19.2
9.6
8,000,000
N

Asynchronous
+16 +32 +64
KBaud
50.0
19.2
16.1
9.6
4.8
4.0
3.5
3.0

25.0
9.6
8.06
4.8
2.4
2.0
1.7
1.5

12.5
4.8
4.03
2.4
1.2
1.0
0.87
0.75

- - - - 500K 250K 125K
N

-N- -N-

143824-iSBC 88/45 Advanced Data Communications Processor Board Hardware Reference Manual
(not supplied).
Reference manuals may be ordered from any Intel
sales representative, distributor office or from Intel
Literature Department, 3065 Bowers Avenue, Santa
Clara, CA 95051.

ORDERING INFORMATION
Order Code Description
SBC88/45
iSBC 88/45 Advanced Data Communications Processor Board

Line Drivers (Supplied)
Device

Characteristic

Qty

Installed

1488
1489
3486
3487

RS232C
RS232C
RS422A
RS422A

3
3
2
2

1
1
2
2

11-27

MULTIBUS® I
Digital and Analog
I/O Boards

iSBC® 519A
PROGRAMMABLE I/O EXPANSION BOARD
Expansion via Direct MULTIBUS®
Interface

•

Provides 16 Maskable Interrupt
Request Lines

72 Programmable 1/0 Lines with
Sockets for Interchangeable Line
Drivers and Terminators

•

Jumper Selectable 0.5, 1.0, 2.0, or
4.0 ms Interval Timer

•

Provides Eight Maskable Interrupt
Request Lines with Priority Encoded
and Programmable Interrupt Algorithms

• 1/0
•
•
•

Provides Full 16-Bit 1/0 Addressability

Provides 3 iSBX Multimodule
Connectors

The iSBC 519A Programmable 1/0 Expansion Board is a member of Intel's complete line of iSBC memory and
1/0 expansion boards. The iSBC 519A interfaces directly to any iSBC single board computer via the system
bus to expand input and output port capacity. The iSBC 519A provides 72 programmable 1/0 lines. The
system software is used to configure the 1/0 lines to meet a wide variety of peripheral requirements. The
flexibility of the 1/0 interface is further enhanced by the capability of selecting the appropriate combination of
optional line drivers and terminators to provide the required sink current, polarity, and driveltermination characteristics for each application. Address selection is accomplished by using wire-wrap jumpers. The board
operates with a single + 5V power supply.

280230-1

12-1

October 1989
Order Number: 280230-002

iSBC® 519A BOARD

FUNCTIONAL DESCRIPTION
The 72 programmable I/O lines on the iSBC 519A
are implemented utilizing three Intel 82C55A programmable peripheral interfaces. The system software is used to configure the 1/0 lines in combinations of undirectional input/output and bidirectional
ports. In order to take full advantage of the large
number of possible 1/0 configurations, sockets are
provided for interchangeable 1/0 line drivers and terminators. The 72 programmable 1/0 lines and signal
ground lines are brought out to three 50-pin edge
connectors that mate with flat, round, or woven cable.

Interval Timer

SBX Expansion Bus (IEEE 959)
Capabilities
Three SBX bus connectors are provided on the iSBC
519A board. Up to three single-wide or one doublewide and one single-wide IEEE 959 SBX board can
be added to the iSBC 519A board. A wide variety of
expansion options are available.

Physical Characteristics
Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.50 in. (1.27 cm),
1.16 in. (2.95 cm) with iSBX modules
Weight: 14 oz. (397.3 gm)

Typical 1/0 read access time is 350 nanoseconds.
Typical 1/0 readlwrite cycle time is 450 nanoseconds. The interval timer provided on the iSBC 519A
may be used to generate real time clocking in systems -requiring the periodic monitoring of 1/0 functions. The time interval is derived from the constant
clock (BUS CCLK) and the timing interval is jumper
selectable. Intervals of 0.5, 1.0, 2.0, and 4.0 milliseconds may be selected when an iSBC single board
computer is used to generate the clock. Other timing
intervals may be generated if the user provides a
separate constant clock reference in the system.

Eight-Level Vectored Interrupt
Two Intel 82C59A programmable interrupt controllers (PIC) provide vectoring for interrupt levels. As
shown in Table 1, a selection of three priority processing algorithms is available to the system design~
er so that the manner in which requests are serviced
may be configured to match system requirements.
Priority assignments may be reconfigured dynamically via software at any time during system operation.

Electrical Characteristics
Average DC Current
Without Termlnatlon(1) With Termlnatlon(2)
Icc = 1.5A max

NOTES:
1. Does not include power required for operational 110 drivers and 110 terminators.
2. With 18 2200/3300 input terminators installed. all terminator inputs low.

Environmental Characteristics
Operating Temperature: O·C to

Auto-rotating

Specific priority

+ 55·C

Reference Manual
9800385B-iSBC iSBC 519A Hardware Reference
manual (NOT SUPPLIED)
Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

Table 1. Interrupt Priority Options
Algorithm
Fully nested

3.5Amax

Operation
Interrupt request line priorities
fixed.
Equal priority. Each level, after
receiving service, becomes the
lowest priority level until next
interrupt occurs.
System software assigns lowest
priority level. Priority of all other
levels are based in sequence
numerically on this assignment.

ORDERING INFORMATION
Order Code Description
SBC519A

12-2

Programmable 1/0 Expansion Board

iSBC® 517*
COMBINATION 110 EXPANSION BOARD
•

48 Programmable 110 Lines with
Sockets for Interchangeable Line
Drivers and Terminators

•

Synchronousl Asynchronous
Communications Interface with RS232C
Drivers and Receivers

•

Eight Maskable Interrupt Request Lines
with a Pending Interrupt Register

•

1 ms Interval Timer

The iSBC 517 Combination 110 Expansion Board is a member of Intel's complete line of iSBC memory and I/O
expansion boards. The board interfaces directly with any iSBC single board computer via the system bus to
expand serial and parallel I/O capacity. The combination I/O board contains 48 programmable parallel I/O
lines. The system software is used to configure the I/O lines to meet a wide variety of system peripheral
requirements. The flexibility of the 110 interface is significantly enhanced by the capability of selecting the
appropriate combination of optional line drivers and terminators to provide the required sink current, polarity,
and drive/termination characteristics for each application. A programmable RS232C communications interface is provided on the iSBC 517. This interface may be programmed by the system software to provide
virtUAlly any asynchronous or synchronous serial data transmission technique (including IBM Bi-Sync). A
comprehensive RS232C interface to CRTs, RS232C compatible cassettes, and asynchronous and synchronous modems is thus on the board. An on-board register contains the status of eight interrupt request lines
which may be interrogated from the system bus, and each interrupt request line is maskable under program
control. The iSBC 517 also contains a jumper selectable 1 ms interval timer and interface logic for eight
interrupt request lines.

280229-1

·The iSBC 517 is also manufactured under product code piSBC 517 by Intel Puerto Rico, Inc.

12-3

September 1989
Order Number: 280229-002

iSBC® 517 EXPANSION BOARD

BLOCK DIAGRAM
USER DESIGNATED PERIPHERALS

~NTER.UPT

REQUEST
LINES

r-----lI"----,

ADDRESS BUS

DATA IUS
CONTROL BUS

}O:~~~E
280229-2

NOTE:
Interrupts originating from the programmable communications interface and programmable peripheral interface are jumper selectable.

iSBC® 517 Combination I/O Expansion Board Block Diagram

SPECIFICATIONS
Parallel 110 Port Operation Modes
Mode of Operation
Unidirectional
Ports

Input

Lines
(qty)

Output

Bidirectional

Unlatched

Latched &
Strobed

.Latched

Latched &
Strobed

Control

-3

X(1)

X(2)

NOTES:
1. Part of port 3 must be used as control port when either port 1 or port 2 are used as a latched and strobed input or a
latched and strobed output port or port 1 is used as a bidirectional port.
2. Part of port 6 must be used as a control port when either port 4 or port 5 are used as a latched and strobed input or a
latched and strobed output port or port 4 is used as a bidirectional port.

12-4

ISBelS) 517 EXPANSION BOARD

1/0 Addressing
Port

8255
No.1
Control

8255
No.2
Control

USAAT
Data

USART
Control

Address

NOTE:
X is any hex digit assigned by jumper selection.

I/O Transfer Rate

Timer Interval

Parallel-Read or write cycle time 760 ns max
Serial-(USART)
Frequency
(kHz)
(Jumper
Selectable)

153.6
76.8
38.4
19.2
9.6
4.8
6.98

1.003 ms ±0.1% when 110 baud rate is selected
1.042 ms ± 0.1 % for all other baud rates

Baud Rate (Hz)
Synchronous

38400
19200
9600
4800
6980

Asynchronous
(Program
Selectable)
+16
9600
4800
2400
1200
600
300

Line Drivers and Terminators
1/0 Drivers-The following line drivers and terminators are compatible with all the 1/0 driver sockets on
the iSBC 517.

+64
2400
1200
600
300
150
75
110

Serial Communications Characteristics
Synchronous-5-8 bit characters; internal or exter·
nal character synchronization; automatic sync insertion.

Driver

Characteristics

Sink Current (mA)

7438
7437
7432
7426
7409
7408
7403
7400

I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

48
48
16
16
16
16
16
16

NOTE:
I = Inverting; Nt

Asynchronous-5-8 bit characters; peak characters
generation; 1, 1%, or 2 stop bits; false start bit detectors.

= non-inverting; OC = open-collector.

Ports 1 and 4 have 25 mA totem-pole drivers and
1 kn terminators.
Line Terminators-220n/330n divider or 1 kn pullup-user supplied

Interrupts
Eight interrupt request lines may originate from the
programmable peripheral interface (4 lines), the
USART (2 lines), or user specified devices via the
1/0 edge connector (2 lines) or interval timer.

Bus Drivers
Function
Data
Commands

Characteristics Sink Current (mA)
Tri-state
Tri-state

Interrupt Register Address
X1
XO

Interrupt mask register
Interrupt status register

Physical Characteristics
Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.50 in. (1.27 cm)
Weight: 14 oz. (397.3 gm)

NOTE:
X is any hex digit assigned by jumper selection.

12-5

50
25

ISBC~

517 EXPANSION BOARD

Electrical Characteristics

Reference Manual

Average DC Current
Vee = +5V ±5%
Voo = + 12V ±5%
VM = -12 ±5%
lee = 2.4 mA max
100 = 40 mA max
1M = 60 mA max

9800388B-iSBC 517 Hardware Reference manual
(NOT SUPPLIED)

NOTE:
Does not include power required for optional lID
drivers and lID terminators. With eight 2200/3300
input terminators installed, all terminator inputs low.

Manuals may be ordered from any Intel sales repre.
sentative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

ORDERING INFORMATION
Order Code Description
SBC517
Combination lID Expansion Board

Environmental Characteristics
Operating Temperature-O°C to +55°C

12·6

iSBC® 556*
OPTICALLY ISOLATED 1/0 BOARD
• Up to 48 Digital Optically Isolated
Input/Output Data Lines for
MULTIBUS® Systems

• Provisions for Plug-In, Optically
Isolated Receivers, Drivers, and
Terminators

• Choice of
- 24 Fixed Input Lines
-16 Fixed Output Lines
- 8 Programmable Lines

• Voltage/Current Levels
-Input up to 48V
-Output up to 30V, 60 rnA
• Common Interrupt for up to 8 Sources

• + 5V Supply Only
The iSBC 556 Optically Isolated 1/0 Board provides 48 digital input/output lines with isolation between
process application or peripheral device and the system CPU board(s). The iSBC 556 contains two 8255A
programmable interface devices, and sockets for user supplied optically isolated drivers, receivers, and input
resistor terminators, together with common interrupt logic and interface circuitry for the system bus. Input
signals can be single-ended or differential types with user defined input range (resistor terminator and optoisolated receiver selection), allowing flexibility in design of voltage and threshold levels. The output allows user
selection of Opto-Isolated Darlington Pair which can be used as an output driver either as an open collector or
current switch.

280231-1

"The iSBC" 556 is also manufactured under product code piSBC" 556 by Intel Puerto Rico, Inc.

12-7

October 1...
Order Number: 2802310002

ISBCI6> 556 BOARD

Table 1. 110 Ports Opta-Isolator Receivers, Drivers, and Terminators
Port No.

X =110
Base
Address
X+O
X+1
X+2
X+4
X+5
X+6
X+7

Type
of

110
Input
Output'
Input!
Control
Input
Output
lIiputl }
Output
Control

Unes
(qty)

Resistor
Terminator
Pac-Rp 16-Pln DIP
Bourns 4116R-OO
or Equivalent

Dual
Opta-Isolator
8-PlnDIP
Monsanto
MCT66
or Equivalent

Driver
7438
or
Equivalent

8
8
8

B
8

1 if input

Pull-Up
ISBC~902

2 if input

SPECIFICATIONS

1/0 Interface Characteristics

Number of Lines

Line-to-Line Isolation: 235V DC or peak AC
Input/Output Isolation: 500V DC or peak AC

24 input lines
16 output lines
8 programmable lines: 4 input - 4 output
Terminator PAC

Dl __

USER·SUPPLIED
DUAL OPTO·ISOLATOR

USER·SUPPLIED

'j--l

----

RESISTOR

: III-PIN DIP

(+) IS8C

1-)

L _____ -'

L_-J

J)--*!*EP~!:
Rp determines voltage and current range.

12-8

280231-2

inter

ISBC® 556 BOARD

1/0 Addressing
Port
Address

8255 #1

A'
x+o

I
1

I
I

Control

X+1
X+2
X+3
Where: base address is from OOH to 1 FH Oumper selectable)

Physical Characteristics
Width:

X+4

I
I

B
X+5

I
J

C
X+6

Control
X+7

Environmental Characteristics
Temperature:

12.00 in. (30.48 cm)

O°C to 55°C

Relative Humidity: 0% to 90%, non-condensing

Height: 6.75 in. (17.15 cm)
Depth:

8255 #2

0.50 in. (1.27 cm)

Reference Manual

Weight: 12 oz. (397.3 gm)

502170- iSBC 556 Hardware Reference Manual
(Order Separately)

Electrical Characteristics

Average DC Current
Vee = + 5V ± 5%, 1.0A without user supplied isolated receiver/driver
lee = 1.6A max with user supplied isolator receiverl
driver

ORDERING INFORMATION
Order Code Description
SBC556

12-9

Optically Isolated 110 Board

iSBC® 569*
INTELLIGENT DIGITAL CONTROLLER

•

Single Board Digital I/O Controller with
up to Four Microprocessors to Share
the Digital Input/Output Signal
Processing

•
•
•

3 MHz 8085A Central Control Processor

•

Three Sockets for S0411S741A
Universal Peripheral Interface (UPI-41A)
for Distributed Digital I/O Processing
Three Operational Modes
- Stand-Alone Digital Controller
- MULTIBUS® Master
-Intelligent Slave (Slave to MULTIBUS
Master)

•
•
•
•
•
•

2K Bytes of Dual Port Static
Read/Write Memory

Sockets for up to SK Bytes of Intel
2758,2716,2732 Erasable
Programmable Read Only Memory
48 Programmable Parallel I/O Lines
with Sockets for Interchangeable Line
Drivers or Terminators
Three Programmable Counters
12 Levels of Programmable Interrupt
Control
Single

+ 5V Supply

MULTIBUS Standard Control Logic
Compatible with Optional iSBC 80 and
iSBC® 86 CPU, Memory, and I/O
Expansion Boards .

The Intel iSBC® 569 Intelligent Digital Controller is a single board computer (SOS5A based) with sockets for
three 8041A18741A Universal Peripherals Interface chips (UPI-41 A). These devices, which are programmed
by the user, may be used to offload the SOS5A processor from time consuming tasks such as pulse counting,
event sensing and parallel or serial digital 110 data formatting with error checking and handshaking. The iSBC
569 board is a complete digital controller with up to four processors on a single 6.75 inches x 12.00 inches
(17.15 cm x 30.4S cm) printed circuit board. The SOS5A CPU, system clock, readlwrite memory, non-vol~tile
memory, priority interrupt logic, programmed timers, MULTIBUS control and interface logic, optional UPI processors and optional line driver and terminators all reside on one board.

280232-1
"The iSBC" 569 is also manufactured under product code piSBC" 569 by Intel Puerto Rico, Inc.

12-10

October 1989
Order Number: 280232-002

inter

iSSC® 569 CONTROLLER

BLOCK DIAGRAM

.....
CPU

DUAL

P.ttAsT '--_~_....J

MULTI'US

280232-2

iSBC® 569 Intelligent Digital Controller Block Diagram

1/0 Capacity

SPECIFICATIONS
8085ACPU
Word Size: 8, 16 or 24 bits
Cycle Time: 1.30,...s ± 0.1 % for fastest executable
instruction; i.e., four clock cycles.
Clock Rate: 3.07 MHz ± 0.1 %

Parallel-Timers-Three timers, with independent
gate input, clock input, and timer output user-accessible. Clock inputs can be strapped to an external
source or to an on-board 1.3824 MHz reference.
Each timer is connected to a 8259A Programmable
Interrupt Controller and may also be optionally connected to UPI processors.
UPI-I/O-Three UPI-41A interfaces, each with two
8-bit I/O ports plus the two UPI Te.st Inputs. The 8bit ports are user-configurable (as inputs or outputs)
in groups of four.

System Access Time
Dual port memory-725 ns

Serial-1 TTL compatible serial channel utilizing SID
and SOD lines of on-board 8085A CPU.

Memory Capacity
On-board ROM/EPROM-2K, 4K, 8K, or 16K bytes
of user installed ROM or EPROM.

On-Board Addressing

On-board RAM-2K bytes of static RAM. Fully accessible from on-board 8085A. Separately addressable from system bus.

All communications to the UPI-41A processors, to
the programmable reset latch, to the timers, and to
the interrupt controller are via read and write commands from the on-board 80S5A CPU.

Off-board expansion-up to 64K bytes of EPROMI
ROM or RAM capacity.

12-11

intJ

ISBC® 569 CONTROLLER

Memory Addressing

+ 5.0V Current Requirement

Type

On-board ROM/EPROM-O-07FF (using 2758
EPROMs); O-OFFF (using 2716 EPROMs or 2316
ROMs); 0-1 FFF (using 2732 EPROMs); 0-3FFF (using the 2364 ROMs)

2758
2716
2316E
2732
2364

On-board RAM-8000-87FF System access-any
2K increment 00000-FF800 (switch selection); 1K
bytes may be disabled from bus access by switch
selection.

1ROM

2ROM

100mA
100mA
120mA
40mA
40mA

125mA
125mA
240mA
55mA
55mA

Line Drivers and Terminators
I/O Addre,ssing
Source

Addresses

8253
UPIO
UPI1
UPI2
PROGRAMMABLE RESET
8259A

OEOH-OE3H
OE4H-OE5H
OE6H-OE7H
OE8H-OE9H
OEAH-OEBH
OECH-OEDH

I/O /Drivers-The following line drivers are all com,patible with the 110 driver sockets on the iSBC 569
Intelligent Digital Controller.

Timer Specifications
Input Frequencies-jumper selectable reference

Driver

Characteristics

Sink Current (mA)

7438
7437
7432
7426
7409
7408
7403
7400

I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

48
48
16
16
16
16
16
16

NOTE:
I = inverting; NI

Internal: 1.3824 MHz ±0.1% (0.723 /Ls,
nominal)
External: User supplied (2 MHz maximum)

non-inverting; OC

open collector.

I/O Terminators-220n/330n divider or 1 kn pullup (DIP) - user supplied

Output Frequencies (at 1.3824 MHz)
Min 1

Function

Environmental Characteristics

Max 1

Real-time
interrupt interval

1.45/Lsec 47.4 msec

Rate Generator
(frequency)

21.09 Hz 691.2 KHz

Operating Temperature : 0° Ct055° C(32° Fto 131°F)
Relative Humidity: To 90% without condensation

Reference Manual

1. Single 16-bit binary count

502180- iSBC 569 ,Intelligent Digital Controller
Board Hardware Reference Manual (NOT
SUPPLIED)

Physical Characteristics
Width:
Depth:

Reference manuals are shipped with each product
only if designated SUPPLIED (see above). 'Manuals
may be ordered from any Intel sales representative,
distributor office or from Intel Literature Department,
3065 Bowers Avenue, Santa Clara, California 95051.

30.48 cm (12.00 inches)
17.15 cm (6.75 inches)

Thickness: 1.27 cm (0.50 inch)
Weight:

3.97 gm (14 ounces)

ORDERING INFORMATION

Electrical Characteristics
DC Power Requirements-+ 5V @ 2.58A with no
optional devices installed. For each 8741 A add 135
mA. For each 220/330 resistor network, add 60 mA.
Add the following for each EPROM/ROM installed.

Order Code
SBC569

12-12

Description
Intelligent Digital Controller

iSBC® 589*
INTELLIGENT DMA CONTROLLER

•
•
•
•
•

Configurable as Either an Intelligent
Slave or MULTIBUS® Master
5 MHz 8089 I/O Processor
MULTICHANNELTM DMA I/O Bus
Interface with Supervisor, Controller or
Basic Talker/Listener Capabilities
Two 8/16-Bit iSBXTM Bus Connectors
DMA Transfer Rates Up to 1.25 Mbytes
per Second

•

User Command Interface Firmware
Package Provides High Level I/O
Commands

•
•

8 Kbytes of High-Speed Dual-Ported
Static Read/Write Memory
Sockets for up to 32 Kbytes of Read
Only Memory or Additional Byte-Wide
Static RAMs

I!!I Three Programmable Timers

The iSBC 589 Intelligent DMA Controller is a member of Intel's complete line of MULTIBUS microcomputer
systems which take full advantage of VLSI technology to provide economical computer based solutions for
OEM applications. The iSBC 589 board is a general purpose, programmable, high-speed DMA controller on a
single 6.75 x 12.00 inch printed circuit board. Using the board's dual-port RAM and standard EPROM resident
firmware, the on-board Intel 8089 110 Processor can perform memory to memory block transfers and complex
110 operations via two iSBX connectors and the MULTICHANNEL 110 bus at DMA transfer rates up to
1.25 Mbytes per second. Acting as an intelligent slave, the iSBC 589 board enhances the system's overall
performance by relieving the host CPU of time consuming 110 operations. The board's unique combination of
performance, on-board intelligence and flexible hardware 110 interfaces make the iSBC 589 board the ideal
solution for applications with specialized 110 requirements such as high-speed data acquisition, graphics,
instrument automation and specialized peripheral control, that previously would have necessitated an expensive custom designed 110 controller.

210354-1

'The iSBC" 589 Is also manufactured under product code piSBCO> 589 by Intel Puerto Rico. Inc.

12-13

October 1989
Order Number: 210354-0112

inter

ISBC~

589

BLOCK DIAGRAM

MULTICHANNEL
,
BUS

MULTIBUS
INTELLIGENT
SLAVE/MULTlMASTER
INTERFACE

MULTlBUS
SYSTEM BUS

210354-2

1/0 Addressing

SPECIFICATIONS
8089 lOP
WORD SIZE
Instruction-16 to 40-bits

Interface

I/O Addresses

SBX Connector # 1
SBX Connector # 2
MULTICHANNEL
Interval Timer
Other On-Board Devices

FFBO thru FF9F
FFAO thru FFBF
FFDO thru FFEE
FFCB thru FFCE
FFCO thru FFC6
FFFO thru FFFE

Data-B, i6-bits
SYSTEM CLOCK

Memory Capacity

5.0 MHz ± 0.1%
ON-BOARD EPROM
CYCLE TIME

Device
2716
2732A
2764

2.2 /Ls for the fastest instructions

Total Capacity
B Kbytes
16 Kbytes
32 Kbytes

Address Range
FEOOO-FFFFFH
FCOOO-FFFFFH
FBOOO-FFFFFH

System Access Time
ON-BOARD RAM

Dual-Port Memory- 550 ns (worst case, without
contention from on-board access)

Total Capaclty- B Kbytes

I/O Capacity

On-Board Address- 00000-01 FFFH

MULTICHANNEL I/O Bus- 1 MULTICHANNEL
port which supports Band 16-bit transfers and can
be configured as a Basic Talker/Listener, Controller
or Supervisor

MULTIBUS
Address-Jumper
B Kbyte boundaries. Default is 0H.

ISBXTM MULTIMODULETM- Two (2) iSBX MULTIMODULE boards
12-14

selectable - on

intJ

iSBC® 589

I/O Transfer Rates (Microseconds/Transfer) .
MULTICHANNEL
MULTICHANNEL
SBX
MULTIBUS (Shared)
MULTIBUS (Bus lock)
On-Board RAM

2.0
2.4
2.2
1.8

MULTJBUS®

iSBXTM
2.0
2.0
2.4
2.2
1.8

Shared

Buslock

2.4
2.4
2.8

2.2
2.2

2.4
2.0

On-Board
RAM
1.8
2.0
2.2
2.0
1.6

2.2

Timers
Input Frequencies-Jumper selectable at 1.25 MHz, 625 kHz or 312.5 kHz
Output Frequencies/Timing IntervalsFunction

Real-Time Delay
Programmable One-Shot
Rate Generator
Square-Wave Rate Generator
Software Triggered Strobe
Hardware Triggered Strobe

Dual Timer/Counter
(Two Timers Cascaded)

Single Timer/Counter
Minimum

Maximum

Minimum

Maximum

1.6 p.s
1.6 p.s
4.76 Hz
4.76 Hz
1.6 p.s
1.6 p.s

210 ms
210 ms
625 kHz
625 kHz
210 ms
210 ms

3.2 p.s
3.2 p.s
7.3 x 10- 5 Hz
7.3 x 10- 5 Hz
3.2 p.s
3.2 p.s

1.37 x 104 sec
1.37 x 104 sec
312.5 kHz
312.5 kHz
1.37 x 104 sec
1.37 x 104 sec

Physical Characteristics

Environmental Characteristics

Width:

12.00 in. (30.48 cm)

Operating Temperature- O°C to

Height:

7.05 in. (17.9 cm)

Relative Humidity

Depth

0.50 in. (1.27 cm)

Weight:

16 oz. (453.6 gm)

12-15

+ 55°C

to 90% (without condensation)

ISac- 589

Electrical Characteristics

Reference Manuals

DC POWER REQUIREMENTS

142996- iSBC 589 Intelligent DMA Controller
Board Hardware Reference Manual (Not
Supplied)

Configuration

Current Requirements

(+ 5V + 5% Maximum)

Without EPROM

4.7 Amps

Without 8K EPROM
(Using Four 2716s)

5.4 Amps

With 8K EPROM·
(Using two 2732As)

5.0 Amps

With 16K EPROM
(Using Four 2732As)

5.3 Amps

With 32K EPROM
(Using Four 2164s)

5.3 Amps

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051

ORDERING INFORMATION
Order Code Description
SBC589

·Factory Default Configuration

12-16

Intelligent DMA Controller Board

iSBC® 88/40A

MEASUREMENT AND CONTROL COMPUTER

•
•
•
•

High Performance 4.8/6.67 MHz 8088
8-Bit HMOS Processor
12-Blt KHz Analog-to-Digital Converter
with Programmable Gain Control
16-Blt Differential/32 Single-Ended
Analog Input Channels
Three iSBXTM Bus Connectors for
Analog, Digital, and other I/O
Expansion

• iSBC®

4K Bytes Static RAM, Expandable via
301 MULTIMODULETM RAM to
8K Bytes (1K Byte Dual-Ported)

•

Four EPROM/E2PROM Sockets for up
to 64K Bytes, Expandable to
128K Bytes with iSBC® 341 Expansion
MULTIMODULETM

•

MULTIBUS® Intelligent Slave or
Multimaster

The Intel iSBC 88/40A Measurement and Control Computer is a member of Intel's large family of Single Board
Computers that takes full advantage of Intel's VLSI technology to provide an economical self-contained
computer based solution for applications in the areas of process control and data acquisition. The on-board
8088 processor with its powerful instruction set allows users of the iSBC 88/40A board to update process
loops as much as 5-10 times faster than previously possible with other 8-bit microprocessors. For example,
the high performance iSBC 88/40A can concurrently process and update 16 control loops in less than 200
milliseconds using a traditional PID (Proportional-Integral-Derivative) control algorithm. The iSBC 88/40A
board consists of a 16 differential/32 single ended channel analog multiplexer with input protected circuits,
AID converter, programmable central processing unit, dual port and private RAM, read only memory sockets,
interrupt logic, 24 channels of parallel 110, three programmable timers and MULTIBUS control logic on a single
6.75 by 12.00-inch printed circuit card. The iSBC 88/40A board is capable of functioning by itself in a standalone system or as a multimaster or intelligent slave in a large MULTIBUS system.

280220-1

12-17

September 1989
Order Number: 280220-002

intJ

ISBC® 88/40A COMPUTER

BLOCK DIAGRAM

LOCAL BUS

USE.

...--"":'':'''-J.....,
IOU CPU
4 ••".17 MHz

IAnERY
IAC'UP

STATIC RAM
3KCI1'5A)

(.MHzOPTI

....,---_......1 1

L-:-----',
I o:.:~:=,,~ ,
I
I

r---;~-,

I'
:

.....M
EXPANSION

EXPANSION

L __ ..; ____ J

IL. _________ .JI

ISBC337A

ISBC301

PORT 8 SOCKETS
ACCEPT 55Y. 300 rnA

UNEDAIYERS
J3

ANALOG INPUTS

PARALLEL DIGITAL 110

....._ _ _ _---' I
ADDtTIONAL FOUR
21·PIN SOCKETS

I
I

-----------...1
ISIC3.1

280220-2

Figure 1. ISBC@ 88/40A Measurement and Control Computer Block Diagram
LOCAL
BUS

HIGH

IMPEDANCE
BUfFER
AMP

PROGRAMMABLE
GAIN SELECT

ANALOG

INPUT

I OFFSET

SIGNALS

ADJUST

SIGNAL--4'
GROUND

PSEUDO DIFFERENTIAL GROUND

280220-3

Figure 2. iSBC@ 88/40 Analog Input Section

12·18

inter

ISBC® 88/40A COMPUTER

SPECIFICATIONS
Parallel 110 Port Operation Modes
Mode of Operation
Unidirectional
Port

Lines
(qty)

Input

Output

Latched

Latched &
Strobed

Latched

Bidirectional

Control

Latched &
Strobed

X(1)

Word Size

MEMORY ADDRESSING

I nstructlon-8 , 16, or 32 bits
Data-8 bits

On-Board ROM/EPROM
FEOOO-FFFFF (using 2716 EPROMs) .
FCOOO-FFFFF (using 2732 EPROMs)
F8000-FFFFF (using 2764 EPROMs)
FOOOO-FFFFF (using 27128 EPROMs)

Instruction Cycle Time (minimum)
8088 Clock Rate

Instruction

4.8 MHz 6.67 MHz 8.0 MHz
In Queue
417 ns
Not in Queue 1.04 ns

300ns
750ns

250 ns
625 ns

Number of
Clock Cycles
2
5

On-Board ROM/EPROM (With iSBC 341
MULTIMODULE EPROM option installed)
FCOOO-FFFFF (using 2716 EPROMs)
F8000-FFFFF (using 2732 EPROMs)
FOOOO-FFFFF (using 2764 EPROMs)
EOOOO-FFFFF (using 27128 EPROMs)

MEMORY CAPACITY
On-Board ROM/EPROM/E2PROM
Up to 64K bytes; user installed in 2K, 4K, 8K or 16K
byte increments or up to 128K if iSBC 341 MULTIMODULE EPROM option installed. Up to 8K bytes of
E2PROM using Intel 2816As or 2817As may be
user-installed in increments of 2, 4, or 8 bytes.

OOOOO-OOFFF
00000-01 FFF (if iSBC 301 MULTIMODULE RAM option installed)

On-Board RAM

4K bytes or 8K bytes if the iSBC 301 MULTIMODULE RAM is installed. Integrity maintained during
power failure with user-furnished batteries. 1K bytes
are dual-ported.

Jumpers allow 1 K bytes of RAM to act as slave RAM
for access by another bus master. Addressing may
be set within any 1 K boundary in the 1-megabyte
system address space.

Off-Board Expansion

Slave RAM Access

Up to 1 megabyte of user-specified combination of
RAM, ROM, and EPROM.

Average: 350 ns

On-Board RAM (CPU Access)

12-19

iSSCI!!) 88/40A COMPUTER

INTERVAL TIMER

Analog Input

Output Frequencies

16 differential (bipolar operation) or 32 single-ended
(unipolar operation).

Single Timer

Function
Real-Time
Interrupt
Interval

Min

Max

0.977 p.s

64ms

Dual Timers
(Two Timers
Cascaded)

FuJI Scale Voltage Range--5 to +5 volts (bipolar), 0 to + 5 volts (unipolar).

69.9 minutes
maximum

NOTE:
Ranges of 0 to 10V and ± 10V achievable with externally supplied ± 15V power.
'GaIn-Program selectable for gain of 1, 5, 50, or
250.

Rate
15.625 Hz 1024 KHz 0.00024 Hz
Generator
minimum
(Frequency

Resolutlon-12 bits (11 bits plus sign for ± 5, ± 10
volts).

CPU CLOCK

Accuracy-Including noise and dynamic errors.

4.8 MHz ±0.1% or 6.67 MHz ±0.1%. (User selectable via jumpers);
8.0 MHz (with user installed 24 MHz oscillator)

Gain

25°C

1
5
50
250

±0.035% FSR o
±0.06% FSR'
±0.07% FSR'
±0.12% FSR'

1/0 Addressing
NOTE:

All communications to parallel I/O ports, iSBX bus,
A/D port, timers, and interrupt controller are via read
and write commands from the on-board 8088 CPU.

FSR = Full Scale Range ± % LSB. Figures are in percent
of full scale reading. At any fixed temperature between O'C
and SO'C, the accuracy is adjustable to ± 0.05% of full
scale.

Interface Compatability

Gain TC (at gain = 1)-30 PPM (typical), 56 PPM
(max) per degree centigrade, 40 PPM at other gains.

Parallel 1/0-24 programmable lines (8 lines per
port); one port includes a bidirectional bus driver. IC
sockets are included for user installation of line drivers and/or I/O terminators and/or peripheral drivers
as required for interface ports.

Interrupts
8088 CPU includes a non-maskable interrupt (NMI).
NMI interrupt is provided for catastrophic events
such as power failure. The on-board 8259A PIC provides 8-bit identifier of interrupting device to CPU.
CPU multiplies identifier by four to derive vector address. Jumpers select interrupts from 26 sources
without necessity of external hardware. PIC may be
programmed to accommodate edge-sensitive or level-sensitive inputs.

OffsetTC(in % of FSRI'C)

Gain
1
5
50
250

Offset TC (typical)
0.0018%
0.0036%
0.024%
0.12%

Sample and Hold-Sample Time: 15 p.s
Aperature-Hold Aperature Time: 120 ns
Input Overvoltage Protection: 30 volts
Input Impedance: 20 megohms (min.)
Conversion Speed: 50 p.s (max.) at gain = 1
Common Mode Rejection Ratio: 60 dB (min.)

12-20

ISBC~

88/40A COMPUTER

Physical Characteristics

Environmental Requirements

Width: 30.48 cm (12.00 in.)
Length: 17.15 cm (6.75 in.)
Height: 1.78 cm (0.7 in.)
2.82 cm (1.13 in.) with iSBC Memory Expansion, MULTIMODULES, iSBX Numeric Data
Processor or iSBX MULTIMODULES.

Operating Temperature: 0° to +60°C with 6 CFM
min. air flow across board
Relative Humidity:
to 90% without condensation

Equipment Supplied

Electrical Requirements

iSSC 88/40A Measurement and Control Computer
Schematic diagram

Power Requirements

REFERENCE MANUALS
Current

Voltage
+5V
+5VAux
+12V
-12V

Maximum

Typical

5.5A
150mA
120mA
40mA

4A
100mA
80mA
30mA

147049- SSC 88/40A Measurement and Control
Computer Hardware Reference Manual
(Order Separately).
Manuals may be ordered from an Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

NOTES:
1. The current requirement includes one worst case (active-standby) EPROM current
2. If +5V Aux Is supplied by the isec BB/40A board, the
total + 5V current is the sum of the + 5V and the + 5V
Aux.

ORDERING INFORMATION
Order Code Description
SBC8840A

12-21

Measurement and Control Computer

iSBC® 108A/116A
COMBINATION MEMORY AND
I/O EXPANSION BOARDS

•

8K or 16K Bytes of Read/Write Memory
(ISBC 108A, ISBC 116A Boards
Respectively) Sockets for up to 32K
Bytes of EPROM

•
•

Auxiliary Power Bus and Memory
Protect Control Logic Provided for
Battery Backup RAM Requirements
RAM and EPROM Assignable Anywhere
within a One Megabyte Address Space

•

48 Programmable I/O Lines with
Sockets for Interchangeable Line
Drivers and Terminators

•
•
•

Synchronous/Asynchronous
Communications Interface with RS232C
Drivers and Receivers
Eight Maskable Interrupt Request Lines
with a Pending Interrupt Register
1 ms Interval Timer

The iSBC 10BA and iSBC 116A,Combination Memory and 110 Boards are members of Intel's complete line of
MULTIBUS memory and lID expansion boards. Both boards interface directly to a host single board computer
via the MULTIBUS interface to expand RAM, EPROM serial 110 and parallel 110 capacity. This mixture makes
the iSBC 10BA and 116A combination boards ideal for small microcomputer systems where the on-board
resources of a single board computer are insufficient for incrementing the memory and lID capacities of larger
multiple board ~ystems.

281011-1

12-22

October 1989
Order Number: 281011-001

iSBC 108A/116A

RS232C
COMPATIBLE
DEVICES

USER DESIGNATED PERIPHERALS

2
INTERRUPT
REQUEST
LINES

4B PROGRAMMABLE
I/O LINES

...--"';;:'----w

DATA BUS
CONTROL BUS

281011-2

Figure 1. iSBC® 108A/116A Combination Memory and I/O Expansion Board Block Diagram
I/O Port Operation Modes
Mode of Operation
Unidirectional
Port

Lines
(qty)

Input
Unlatched

Output

Latched &
Strobed

Latched

Bidirectional

Control

Latched &
Strobed

NOTES:
1. Part of port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input or a
latched and strobed output or port 1 is used as a bidirectional port.
2. Part of port 6 must be used as a control port when either port 4 or port 5 are used as a latched and strobed input or a
latched and strobed output or port 4 is used as a bidirectional port.

12·23

isec 108A/116A
Memory Word Size

Frequency
Baud Rate (Hz)
(kHz)
Asynchronous
(Jumper
(Program
Synchronous
Selectable)
Selectable)

S bits only. 16-bit single board computers may use
this memory only for the storage of S-bit data.

Memory Addressing
EPROM-Up to 4K, SK, 16K or 32K bytes of readonly-memory may be located anywhere within a one
megabyte address range. The base address must
be located on a 4K byte boundary. EPROM addresses may not cross 32K byte boundaries.
. RAM-8K (iSBC 10SA) or 16K (iSBC 116A) bytes of
RAM may be located anywhere in a one megabyte
address range. The base address must be located
on a 4K byte boundary. RAM addresses may not
cross 32K byte boundaries.

38400
19200
9600
4800
6980

""" 64
4S00
2400
1200
600
300
150
75
110

Serial Communications Characteristics
Synchronous-5-8 bit characters; internal or external character synchronization; automatic sync insertion.

Memory Response Time
Access (ns)

Cycle (ns)

RAM

450 Max'

5S0Max*

EPROM/ROM

450 Max

635 Max

Memory

""" 16
19200
9600
4800
2400
1200
600
300

307.2
153.6
76.8
3S.4
19.2
9.6
4.S
6.98

Asynchronous-5-S bit characters; break characters generation; 1, 1%, or 2 stop bits; false start bit
detectors.

'Wlthout refresh contention.

Interrupts
I/O Transfer Rate
Parallel-Read or write acknowledge time 575 ns
max.

Eight interrupt request lines may originate from the
programmable peripheral interface (4 lines), the
USART (2 lines) or user specified devices via the
110 edge connector (2 lines), or interval timer.

Serlal-(USART)

Interrupt Register Address
XX1
XXO

Interrupt mask register
Interrupt status register

NOTE:
XX is any two hex digits assigned by jumper selection.

Timer Interval
1.003 ms ± 0.1 % when 110 baud rate is selected.
1.042 ms ± 0.1 % for all other baud rates.

1/0 Addressing
Port

8255A
No.1
Control

8255A
No.2
Control

USART
Data

USART
Control

Address

XX4

XX5

XX6

XX8

XX9

XXA

XX7

XXB

XXCorXXE

XXDorXXF

NOTE:

xx is any two hex digits assigned by jumper selection.
12-24

inter

iSBC 108A/116A

Auxiliary Power

Physical Characteristics

An auxiliary power bus is provided to allow separate
power to RAM for systems requiring battery backup
or readlwrite memory. Selection of this auxiliary
RAM power bus is made via jumpers on the board.

Width:
Height:
Depth:
Weight:

Memory Protect
An active-low TIL compatible memory protect signal
is brought out on the auxiliary connector which,
when asserted, disables readlwrite access to RAM
memory on the board. This input is provided for the
protection of RAM contents during system powerdown sequences.

Electrical Characteristics
Average DC Current
VDD

Sink Current (mA)

7438
7437
7432
7426
7409
7408
7403
7400

I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

48
48
16
16
16
16
16
16

Characteristic

Sink Current (mA)

Data
Commands

Tri-State
Tri-State

32
32

Vee

VAA

250mA

2.9A

70mA

4 2708s and
8 Terminators

520mA

3.6A

180mA

70mA

4 2716s and
No Terminators

250mA

3.3A

70mA

4 2732s and
No Terminators

250mA

3.5A

70mA

Aux. Power
RAM Accessed

17SmA

0.45A

3mA

Aux. Power
No RAM Access

20mA

0.45A

3mA

Operating Temperature: O·C to

+ 55·C.

Reference Manuals
9800862: iSBC 108A1116A Board Hardware Reference Manual (NOT SUPPLIED)

1/0 Termlnators-220fl/330fl divider or 1 kfl pullup user supplied.

Function

Environmental Characteristics

NOTE:
I = Inverting, NI = Non-Inverting, OC = Open Collector.

Bus Driver

Vcc

No EPROM or
Terminators

1/0 Drivers-The following line drivers and terminators are all compatible with the 110 driver sockets on
the iSBC 108A1116A board. Ports 1 and 4 have
25 mA totem-pole drivers and 1 kfl terminators.
Characteristic

+12 ±5% +5 ±5% -5 ±5% -12 ±5%

Line Drivers and Terminators

Driver

12.00 in. (30.48 cm)
6.75 in. (17.15 cm)
0.50 in. (1.27 cm)
14 oz. (397.3 gm)

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

ORDERING INFORMATION
Order Code Description
SBC108A
Combination Memory and I/O Expansion Board with 8 Kbytes RAM
SBC116A
Combination Memory and I/O Expansion Board with 16 Kbytes RAM

12-25

MULTIBUS® I
System Packaging and
Power Supplies

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SYP341 CARD CAGE MODULE

A 16·SLOT MULTIBUS®I CARD CAGE MODULE FOR FLEXIBLE,
EXPANDABLE SYSTEMS CONFIGURATIONS
Intels SYP341 Card Cage is a standard module designed to provide, along with the
companion SYP342 Peripheral Module, a basic platform for the integration of large
capacity systems. Intels modular packaging scheme allows for integration into standard
19 inch rack-mount cabinets or NEMA-type enclosures.

FEATURES
• 16-slot MULTIBUS I backplane with
integrated priority and interrupt circuitry.
• Accepts standard 7 x 12 inch
MULTIBUS I boards and up to seven
10 x 12 inch boards.
• Meets EIA, 19 inch rack standard.
• 4-layer backplane construction.
Interleaved bus signal traces. Dedicated
power and ground layers.
• 24-bit addressing supported on all slots.
• Extended gold pins for all P2 signals.
Supports iLBX bus cables.
• Backplane generated bus clock.
• MULTI BUS reset and interrupt switches
with power"on and status indicators.
• 750 watt multiple output switching
power supply. Switch selectable 110/220
VAC.
• Forced air cooling. Provides 300 Ifm
across boards.

in1:el"---------Cllntel CorporalLon 1989

13-1

September, 1989

Order Number 280641·002

SPECIFICATIONS
ENVIRONMENTALS

WORLDWIDE SERVICE AND SUPPORT

Ambient Temperature
Operating
Non-Operating
Relative Humidity
Operating
Non·operating
Altitude
Operating
Non-Operating

Intel provides support for Intel and non·lntel boards
and peripherals as well as on-site service.
Development support options include phone support,
subscription service, on-site consulting, and customer
training.

0 to 55 D C
- 40 to 80 D C
80% at 40 D C
95% at 55 D C

QUALITY AND RELIABILITY

Sea Level to 10,000 feet
Sea Level to 40,000 feet

The SYP341 is designed, tested and manufactured in
accordance with Inters industry leading quality and
reliability standards.

ELECTRICAL
DC Power Output
+5v
+12v
-12v
AC Power Input

750 watt maximum
100.0 A maximum
10.0 A maximum
10.0 A maximum
9()'132 VAC or 180-264 VAC
47·63 Hz

REGULATIONS
Meets the following safety requirements:
US
UL478 5th Edition
recognized
Canada
CSA C22.2 No. 220 certified
Europe
IEC 380 and IEC 950
Power Supply meets the following EMIIRFI
requirements:
US
FCC Class B Conducted
emissions
Europe
VDE Limit Class B
Conducted emissions

PHYSICAL CHARACTERISTICS
Dimensions
Standard Rear Mount Power Supply
Height
488.1 mm (19.22 in)
Width
4B2.7 mm (19.00 in)
Depth
501.6 mm (19.75 in)
Weight
23.9 kilograms (53 Ibs)
Optional Mounting:
Side Mounted Power Supply
Width
597.0 mm (23.50 in)
Depth
355.7 mm (14.00 in)

Backplane Slot Spacing
Slots 5, 13 - 1.B"
Slot 1 - 1.4"
Slots 2-4, 6·12, 14·16 - O.B"
Slots 6-12 accommodate 10 x 12 inch boards

ORDER CODES
SYP341V1-Configured 110 VAC
SYP341V2-Configured 220 VAC

13·2

SYP342 PERIPHERAL MODULE

·.~_1.·

j ...· i . ,

a""
-• "•- •• aa",,"
','-

:~J
,.

Olilf< series signal conditioning/termination
panels and field wiring. For smaller systems with
only one or two iSBC 604/614 cardcages (4 to 8
slots), up to two iCS 910, iCS 920, or iCS 930 signal
conditioning/termination panels can be mounted
vertically over the area where the second or third

Equipment Supplied
iCS 80 industrial chassis, three fans for cardcages,
one fan for power supply, 4-slot cardcage with MULTIBUS backplane, control panel with switches, indicators, keylock, power distribution barrier strip, A.C.
power fuse, line filter, 115V power cable, and logic
for interrupt and reset buttons. An installation package is also provided, including a NEMA cabinet

13-20

iCSTM 80

mounting kit, power supply extension cables, and
RETMA cabinet mounting screws, 100/120/2201
240 VAC operation.

Output Power
Voltage

Software
See the RMX/BO Real-time Multi-tasking Executive
specifications for industrial related applications. In
addition, system monitors for most of the Intel single
board computers are available in the INSITE (Intel's
Software Index and Technology Exchange) User's
Program Library.

Height: 39.3 cm (1S.7")
Width: 4B.S cm (19.0") at front panel
43.S cm (17.4") behind front panel
Depth: 30.0 cm (12.0") with all protrusions
Weight: 16.B kg (37.0 Ib) without power supplies

Electrical Characteristics
The iCS BO chassis provides mounting space for the
iSBC 640 power supply. Unless otherwise stated,
electrical specifications apply to both power supplies
when installed by user in iCS BO chassis.

Power,Max:

Input
Voltage

S.6Amax

103 VAX

2.BAmax

206 VAX

4.SA
30.0A
USA
USA

+14Vto
+ S.BV to
-S.BVto
-14Vto

+16V
+ 6.6V
-6.6V
-16V

Output Transient Response-Less than SO p.s for
± SO% load change

Temperature (Ambient)
Operating:
O·C to SO·C (32·F to 122·F)
Non-Operating: - 40·C to + BS·C
Humidity:
Up to 90% relative, noncondensing at 40·C

with
ISBC640

ISBC640

Output Ripple and Nolse-10 mV (iSBC 640 supply) peak-to-peak, maximum (D.C. to SOO kHz)

(Ambient at iCS BO air intake, bottom of chassis)

Current
(Including Fans)

ISBC640

Remote Sehslng-Provided for + S Voc output line
regulation.

Environmental Characteristics

Frequency: 47 Hz to 63 Hz Voltage (Nominal)
Voltage (Single Phase, Jumper Selectable)
iCS BO Kit 640: 100, 120, 220, 240 VAC (±10%)

Overvoltage
Protection

Combined Line/Load Regulatlon-± 1 % at
±10% static line change and ±SO% static load
change, measured at the output connector (±0.2%
measured at the power supply under the same conditions).

Physical Characteristics

Input Power

+12V
+SV
-SV
-12V

Output
Current
(Max)

Maximum Watts Dissipation (load plus losses)SOOW (iSBC 640 supply)

Installation
Complete instructions for installation are contained
in the iCS BO Site Planning and Installation Guide,
including RErMA and NEMA cabinet mounting, and
field Signal, ground wiring and cooling suggestions.

Warranty
The iCS BO Industrial Chassis is warranted to be free
from defects in materials and workmansip under normal use and seivice for a period of 90 days from
date of shipment.

ORDERING INFORMATION
Part Number

Description

iCS BO Kit 640 iCS BO system consisting of:
iCS 80 Industrial Chassis
iSBC 640 Power Supply

SBOW

13-21

MULTIBUS® I
Architecture

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MULTIBUS® SYSTEM BUS

•
•
•
•

•
•
•

IEEE 79688 Industry Standard System
Bus
Supports Multiple Processor Systems
with Multi-Master Bus Structure
8-Blt, 16-Blt, and 32-Bit Devices Share
the Same MULTIBUS® System
Resources
Foundation of Intel's Total System
Architecture: MULTIBUS®, ILBXTM,
BITBUSTM and iSBXTM Buses

•

16 Mbyte Addressing Capability
Bus Bandwidth of Up to 10 Megabytes
Per Second
Supported by a Complete Family of
Single Board Computers, Memory,
Digital and Analog 1/0, Peripheral
Controllers, Graphics and Speech
Recognition, Packaging and Software
Supported by Over 200 Vendors
Providing Over 2000 Compatible
Products

The MULTIBUS® System bus is one of a family of standard bus structures resident within Intel's total system
architecture. The MULTIBUS interface is a general purpose system bus structure containing all the necessary
signal lines to allow various system components to interact with one another. This device interaction is built
upon the master-slave concept. The "handshaking" between master and slave devices allows modules of
different speeds to use the MULTIBUS interface and allows data rates of up to 5 million transfers per second.
The MULTIBUS system bus can support multiple master devices (16) on a 18 inch backplane and can directly
address up to 16 megabytes of memory. As a non-proprietary, standard system bus, the MULTIBUS interface
has become the most prominent 8/16-bit microcomputer system bus in the industry with over 200 vendors
supplying over 2000 MULTIBUS compatible products. Its success as the industry standard has been reinforced by adoption of the MULTIBUS specification by the Institute of Electrical and Electronic Engineers(IEEE 79688 System Backplane Bus). MULTIBUS-based systems have been designed into applications, such
as, industrial automation and control, office systems and word processing, graphics systems and CAD/CAM,
telecommunications systems and distributed processing.

280294-1

14-1

July 1989
Order Number: 280294-001

MULTIBUS® SYSTEM BUS

FUNCTIONAL DESCRIPTION
Architectural Overview
The MULTIBuse system bus is the physical framework and the conceptual foundation of Intel's total
system architecture. It is a general purpose system
bus used in conjunction with the single board computer concept to provide a flexible mechanism for
inter-module processing, control and communication. The MULTIBUS interface supports modular
CPU, memory and 1/0 expansion in flexible, cost effective microcomputer system configurations. These
configurations implement single board computers
and expansion modules in a multiple processor approach to enhance system performance. This en- '
hanced performance is achieved through partitioning of overall system functions into tasks that each
of several processors can handle individually. When
new system functions are added (peripherals) more
processing power can be applied to handle them
without impacting existing processor tasks.

Structural Features
The MU!-TIBUS interface is an asynchronous, multiprocessing system bus deSigned to perform S-bit
and 16-bit transfers between single board com put-

ers, memory and 1/0 expansion boards. Its interface
structure consists of 24 address lines, 16 data lines,
12 control lines, 9 interrupt lines, and 6 bus exchange lines. These signal lines are implemented on
single board computers and a mating backplane in
the form of two edge connectors resident on 6.75"
x 12.00· form factor PC boards. The primary 86-pin
P1 connector contains all MULTIBUS signal lines
except the four address extension lines. The auxiliary 60-pin P2 connector contains the four MULTIBUS
address extension lines, and reserves the remaining
56 pins for implementing' the iLBX Execution Bus
into the MULTIBUS system architecture.

Bus Elements
The MULTIBUS'system bus supports three device
categories: 1) Master, 2) Slave, 3) Intelligent Slave.

A bus master device is any module which has the
ability to control the bus. This ability is not limited to
only one master device. The MULTIBUS interface 'is
capable of supporting multiple masters on the same
system through bus exchange logic. Once access
has been acquired by a master device, it has a period of exclusive control to affect data transfers
through a generation of command signals, address
signals and memory or 1/0 addresses.

REMOTE CONTROL MODULES
BITBUS'·

280294-2

Figure 1_ MULTIBuse System Architecture
14-2

inter

MULTIBUS® SYSTEM BUS

A bus slave device is a module that decodes the
address lines on the MULTIBUS and acts upon the
command Signals from the bus masters. Slave devices are not capable of controlling the MULTI BUS
interface.

Bus Interface/Signal Line Descriptions
The MULTIBUS system bus signal lines are grouped
into five classes based on the functions they perform: 1) control lines, 2) address and inhibit lines, 3)
data lines, 4) interrupt lines, 5) bus exchange lines.
Figure 2 shows the implementation of these signal
lines.

The intelligent slave has the same bus interface attributes as the slave device but also incorporates an
on-board microprocessor to control on-board memory and 1/0 tasks. This combination of on-board processor, memory and 1/0 allow the intelligent slave to
complete on-board operations without MULTIBUS
access.

The MULTIBUS control lines are broken down into
five sub-groups: clock signals (2), commands (4), acknowledge (1), initialize (1), and lock (1). The two
clock signals provide for the generation of a master

110 SLAVE
10WC" AND 10RC.
DATO.

DATF*

ADRO"

ADRF*

COMMAND
DATA
ADDRESS

BUS MASTER
1/0 COMMANDS

DATA

BHEN*

INTERRUPTS
TRANSFER ACKNOWLEDGE

ADDRESS

CLOCK

BHEN"
~

INTA*
INIT ..

INTERRUPTS
TRANSFER ACKNOWLEDGE
CLOCK
INTERRUPT ACKNOWLEDGE
INITIALIZE
MEMORY COMMANDS

ltACK*
CCLK ..
INTA"
INIT*

MEMORY SLAVE'

r---

INIT*
CLOCK
TRANSFER ACKNOWLEDGE

BHEN ..
ADRO .. ·ADR11*
DATO*·DATF ..
MWTC .. ANDMRDC ..

ADDRESS
DATA
COMMAND
INHIBITS

~}
INH2*

TO
OTHER
SLAVES

280294-3

Figure 2. MULTIBUS® Interface Signal Lines

14-3

· intJ

MULTIBUS® SYSTEM BUS

clock for the system and the synchronization of bus
arbitration logic. The four command lines are the
communication links between the bus masters and
bus slaves, specifying types of operations to be performed such as reads or writes from memory or 1/0.
The transfer acknowledge line is the slave's acknowledgement that a requested action of the master is complete. The initialize signal is generated to
reset the entire system to a known state. The lock
signal is used by an active bus master to lock dualported for mutual exclusion.
The address and inhibit lines are made up of 24 address lines, two inhibit lines, and one byte control
line. The 24 address lines are signal lines used to
carry the address. of the memory location or the 110
device that is being referenced. These 24 lines allow
a maximum of 16 million bytes of memory to be accessed. When addressing an 110 device, sixteen address lines are used to address a maximum of 64
thousand devices. The two inhibit lines are used to
allow different types of memory (RAM, ROM, etc.)
having the same memory address to be accessed in
a preferred priority arrangement. The byte control
line is used to select the upper byte of a 16-bit word
in systems incorporating 16-bit memory and 110
modules.
The MULTIBUS interface supports sixteen bi-directional data lines to transmit or receive information to
or from a memory location or an 110 port.
The MULTIBUS interrupt lines consist of eight interrupt request lines and one interrupt acknowledge
line. Interrupts are requested by activating one of the
eight interrupt request lines. The interrupt acknowledge signal is generated by the bus master when an
interrupt request is received. It effectively freezes interrupt status and requests the placement of the interrupt vector address onto the data lines. There are
six bus exchange lines that support two bus arbitration schemes on the MULTIBUS system bus. A bus
master gains control of the bus through the manipulation of these Signals. The bus request, bus priority,
bus busy, and bus clock signals provide for a slot
dependent priority scheme to resolve bus master
contention on the MULTIBUS interface. Use of the
common bus request signal line can save arbitration
time by providing for a higher priority path to gain
control of the system bus.

Figures 3 and 4 show the basic timing for a read and
write data transfer operation. A MULTIBUS data
transfer begins by having the bus master place the
memory or 1/0 port address on the address bus. If
the operation is a write, the data is also placed on
the data lines at this time. The bus master then generates a command (110 read or write, or memory
read or write) which activates the appropriate bus
slave. The slave accepts the data if it is a write operation, or places data on the data bus if it is a read. A
transfer acknowledge is then sent to the bus master
by the bus slave, allowing the bus master to complete its cycle, removing the command from the
command line, and then removing the address and
data from the MULTIBUS interface.

INTERRUPT OPERATIONS
The MULTIBUS interface supports two types of interrupt implementation schemes, Non-Bus Vectored
and Bus Vectored. Non-Bus vectored interrupts are
interrupts handled on the bus master which do not
require the MULTIBUS interface for transfer of the
interrupt vector address. The interrupt vector address is generated by the interrupt controller on the
master and transferred to the processor over the local bus when an interrupt request line is activated by
a slave module over the MULTIBUS interface. Bus
vectored interrupts are interrupts which transfer the
interrupt vector address along the MULTIBUS data
lines from the slave to the bus master using the interrupt acknowledge command signal for synchronization. When an interrupt request occurs, the interrupt control logic on the bus master intetrupts the
processor, generating an interrupt acknowledge
command that freezes the interrupt logic on the bus
for priority resolution and locks the MULTIBUS system bus. After the bus master selects the highest
priority active interrupt request lines, a set of interrupt sequences allow the bus slave to put its interrupt vector address on the data lines. This address
is used as a pointer to interrupt the service routine.

BUS EXCHANGE TECHNIQUES
The MULTIBUS system bus can accommodate sev,eral bus masters on the same system, each one taking control of the bus as it needs to affect data
transfers. The bus masters request bus control
through a bus exchange sequence.
The MULTIBUS interface provides for two bus exchange priority techniques: a serial technique and a
parallel technique. In a serially arbitrated MULTIBUS
system, requests for system bus access are ordered
by priority on the basis of bus slot location. Each
master on the bus notifies the next lower priority
master when it needs to use the bus, and it monitors
the bus request status of the next higher priori-

Bus Operation Protocol
DATA TRANSFER OPERATION
The data transfer operation of the MULTIBUS system bus is a straight-forward implementation of an
asynchronous master-slave handshaking protocol.

14-4

MULTIBUS® SYSTEM BUS

60-pin P2 (Auxiliary), have specific pin/signal assignments. Because of this, the designer must insure
that the MULTIBUS backplane being designed is
compatible (pin-for-pin) with these two connectors.
Tables 1 and 2 show the pin/signal assignments for
the P1 and P2 edge connectors. The MULTIBUS interface connection is accomplished via a rigid backplane that has connectors that mate to the P1
(43/86-pin) board edge connector and allows for
connectors that mate to the P2(30/60-pin) board
edge connector. Figure 5 shows a typical
MULTIBUS backplane. Figure 6 displays the connector and pin numbering convention. Figure 7
shows the standard MULTIBUS form-factor printed
wiring board outline.

ty-master. Thus, the masters pass bus requests
along from one to the next in a daisy chain fashion.
The parallel bus arbitration technique resolves system bus master priorities using external hardware in
the form of a priority resolution circuit. This parallel
arbitration logic is included in many commercially
available cardcages.

Mechanical Implementation
BUS PIN ASSIGNMENTS
Printed circuit boards (6.75" x 12.00") designed to
interface to the MULTIBUS system bus have two
connectors which plug into the bus backplane.
These connectors, the 86-pin P1 (Primary) and the

Please refer to Intel's MULTIBUS specification and
iLBX bus specification for more detailed information.

Table 1. MULTIBUS® Pin/Signal Assignment-(P1)
(Component Side)

Mnemonic
Power
Supplies

1
3
5
7
9
11

GND
+5V
+5V
+12V

Bus
Controls

(Circuit Side)

Description

Mnemonic

Description

2
4
6
8
10
12

GND
+5V
+5V
+12V

GND

SignalGND
+5Vdc
+5Vdc
+ 12Vdc
Reserved, bussed
Signal GND

GND

SignalGND
+5Vdc
+5Vdc
+12Vdc
Reserved, bussed
Signal GND

13
15
17
19
21
23

BCLK'
BPRN*
BUSY'
MRDC"
10RC"
XACK"

Bus Clock
Bus Pri.ln
Bus Busy
MemReadCmd
I/O Read Cmd
XFER Acknowledge

14
16
18
20
22
24

INIT*
BPRO'
BREO'
MWTC"
10WC'
INH1*

Initialize
Bus Pri. Out
Bus Request
Mem Write Cmd
I/O Write Cmd
Inhibit 1 (disable RAM)

Bus
Controls
and
Address

25
27
29
31
33

LOCK"
BHEN*
CBRO"
CCLK*
INTA"

Lock
Byte High Enable
Common Bus Request
Constant Clk
Intr Acknowledge

26
28
30
32
34

INH2'
AD10*
AD11*
AD12*
AD13'

Inhibit 2 (disable PROM
or ROM)
Address
Bus

Interrupts

35
37
39
41

INT6*
INT4'
INT2*
INTO'

Parallel
Interrupt
Requests

36
38
40
42

INT7*
INT5*
INT3*
INT1*

Parallel
Interrupt
Requests

Address

43
45
47
49
51
53
55
57

ADRE*
ADRC*
ADRA*
ADR8*
ADR6*
ADR4*
ADR2*
ADRO'

44
46
48
50
52
54
56
58

ADRF*
ADRD*
ADRB'
ADR9*
ADR7*
ADR5*
ADR3*
ADR1*

Address
Bus

14-5

Address
Bus

MULTIBUSI8> SYSTEM BUS

Table 1. MULTIBUS® Pin/Signal Assignment-(P1) (Continued)
(Component Side)

Mnemonic
Data

Power
Supplies

59
61
63
65
67
69
71
73

DATE"
DATC·
DATA·
DAT8·
DAT6·
DAT4°
DAT2·
DATO·

GND

SignalGND
Reserved, bussed
-12Vdc
+5Vdc
+5Vdc
Signal GND

-12V
+5V
+5V
GND

79
81
83
85

Description

Data
Bus

(Circuit Side)

Description

Mnemonic
60
62
64
66
68
70
72
74

DATFo
DATD·
DATB·
DAT9·
DAT7·
DAT5·
DAT3·
DATP

76
78
80
82
84
86

GND

NOTE&

Data
Bus

SignalGND
Reserved, bussed
-12Vdc
+5Vdc
+5Vdc
SignalGND

-12V
+5V
+5V
GND

All Reserved pins are reserved for future use and should not be used if upwards compatibility is desired.
·The Reserved MULTI BUS P2 connector pin/signal assignments are contained in Intel's iLBX Bus Specification.

Table 2. MULTIBUS® Pin/Signal Asslgnment-(P2)
Pin

(Component Side)
Mnemonic

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

14·6

(Circuit Side)
Mnemonic

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

MULTIBUS® SYSTEM BUS

Table 2. MULTIBUS® Pin/Signal Assignment-(P2) (Continued)
(Component Side)

Mnemonic
41
43
45
47
49
51
53
Address

55
57

ADR16*
ADR14*

(Circuit Side)

Description

Mnemonic

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

42
44
46
48
50
52
54

Address Bus

56
58

Reserved, Bussed

Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

ADR17*
ADR15*

Address Bus
Reserved, Bussed

NOTES:
All Reserved Pins are reserved for future use and should not be used if upwards compatibility is desired.
·The Reserved MULTIBUS P2 connector pin/signal assignments are contained in Intel's iLBX Bus Specification.

SPECIFICATION

Bus Devices Supported

Word Size

16 total devices-(Master, Slave, Intelligent Slave)

Data: 8- and 16-bit

Bus Bandwidth

Memory Addressing

10 megabytes/sec: 16-bit
5 megabytes/sec: 8-bit

24-bits: 16 megabyte-direct access

I/O Addressing
16-bit: 64 Kbytes

Bus Exchange Cycle

Maximum Bus Backplane Length

200 ns-Best Case; 300 ns-Worst Case (assuming
no bus master is currently active on the bus.)

18 inches

Electrical Characteristics
BUS POWER SUPPLY SPECIFICATIONS
Table 3
Standard(1)
Parameter

Ground

+12

-12

Mnemonic

GND

+5V

+12V

-12V

P1-1 ,2,11,12,
75,76,85,86

P1-3,4,5,6,
81,82,83,
84

P1-7,8,

P1-79,80

Bus Pins

Tolerance

Ref.

±1%

Combined Line & Load Reg

Ref.

0.1%

Ripple (Peak to Peak)

Ref.

Transient Response
(50% Load Change) .

50mV

100 J.Ls

NOTE:
,
1. Point of measurement is at connection point between motherboard and power supply. At any card edge connector a
degradation of 2% maximum (e.g. voltage tolerance ±2%) is allowed.

14-7

MULTIBUS~

SYSTEM BUS

BUS TIMING

ADR(n)*

STABLE ADQRESS

MRDC* OR IORC*.

STABLE DATA

DATA(n)*

XACK*

NOTES:
280294-4
1. Address Setup Time: 50 Nanoseconds Minimum.
2. Time Required for Slave to Get Data Onto Bus in Accordance with Setup Time Requirement. XACK· can be Asserted
as soon as Data is on Bus.
3. Time Required for Master to Remove Command.
4. Address and Data Hold Time; 50 Nanoseconds Minimum.
5. XACK· and Data Must be Removed from the Bus a Maximum of 65 Nanoseconds after the Command is Removed.

Figure 3. Memory or 1/0 Read Timing

----<-...(i)

STAtILE ADDRESS

~~--------------~.,
STABLE DATA

MWTC. OR lOWC.

NOTES:
1. Address and Data Setup; 50 Nanoseconds Minimum.
2. Time Required for Slave to Accept Data.
3. Time Required for Master to Remove Command from Bus.
4. Address and Data Hold Time; 50 Nanoseconds Minimum.
5. XACK· Must be off the Bus 65 Nanoseconds after Command.

Figure 4. Memory or 1/0 Write Timing

14-8

280294-5

r-----------------------------------------------------------------------------------~I~

n
~

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PI

"11

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c
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!"

• J2A •

J3A.

J4A.

• J5A.

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....

_._n. -••--.- .. - • ...••....
..........................................
.
........................................
...
......................

JI.JI

00.0_000 • • • • • • • • • • • • • •

~g:~~CTOR------

0000000 J&

::- 0000000 JI

POWER
CONNECTOR

~
n
o

...........................................

O.OOOOOOJ1

.-.-OOOOOOOJ'

:I\"

iii
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CD

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3

iii

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iii
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en8

280294-6

Parts Usl
1 PWB Termination Backplane
27 Post Wafer Connectors (0.156" Pin Centers) (J6 and J8)
4 Edge Board Connectors, 43/86 Pins on 0.156" Centers (J2-J5)
12 Wire Wrap Posts
410 Pin, 2.2K, 9 RES, 1.5W Resistor Packs (RP1-RP4)
1 10 Pin, 1K, 9 RES, 1.5W Resistor Pack (RP5)
1 10 Pin, 1.1 K, 9 RES, 1.5W Resistor Pack (RP6)
1 1K Resistor, YaW, ±5% (R1)
1 2.2K Resistor, YaW, ±5% (R5)
22200 Resistors, %W, ±5% (R9, R11)
23300 Resistors, %W, ±5% (R10, R12)
25100 Resistors, YaW, ±5% (R7, R8)

~
~

III

c
en

MULTIBUS. SYSTEM BUS

Physical Characteristics (Continued)

(A POSSIBLE CONNECTOR CONFIG'URATIONI

COMPONENT SIDE

IS
II

2
SOLDER SIDE

59
2

60
SOLDER SIDE

280294-7

Figure 6. Connector and Pin Numbering

14-10

inter

MULTIBUSI6> SYSTEM BUS

PHYSICAL CHARACTERISTICS (Continued)
CD

ODS'II -

r-1-------------------+_

.L:>YJ.NO:>

,,-

..
iii

z
z

I
u

~
~:z:
a:

:il...

......
"'",

eu
ue
~E

....
.L:>Y.LNO:>

1,- -

\.+--------------+

- --

-I:S--

~-----------~------------~:~:·I ~.
o

51 ~

Figure 7. Standard Printed Wiring Board Outline

14-11

-~ill

~-- -'EI

)(
.. ~

-0

OLE

inter

MULTIBUSII> SYSTEM BUS

Backplane Connectors
Table 4. Connector Vendors
II' Of

Plna

Centers
Inchea

Multlbus
Connector
(P1)

43/88

0.158

Multibus
Connector
(P1)

43/88

0.158

Auxiliary
Connector
(P2)

30/80

0.1

Auxiliary
. Connector
(P2)

30/60

0.1

Function

Connector
Type

Vendor

Vendor II'

Intel II'

Soldered(1 )

VIKING
ELFAB

2KH43/9AMK12
BS1582D43PBB

102247·001

Wire wrap(1, 2)

ELFAB
ELDAC

BW1582D43PBB
3370880540201

102248·001

ELFAB
EDAC

BW1562A43PBB
337086540202

102273.001(3)

Soldered(1)

ELFAB
EDAC

BS1020A30PBB
345060524802

102238·001

Wire wrap(1, 2)

TI
VIKING

H421121·30
3KH30/9JNK

N/A(3)

EDAC
ELFAB

345060540201
BW1020D30PBB

102241·001

NOTES:
.
1. Connector heights are not guaranteed to conform to Intel packaging eqUipment.
2. Wirewrap pin lengths are not guaranteed to conform to Intel packaging equipment.
3. With mounting ears with 0.128 mounting holes.

. Environmental Characteristics

Reference Manuals

Operating Temperature: O·C to 80·C; free moving
air across modules and
bus
Humidity:
90% maximum (no con·
densation) .

210883-002- MULTIBUS Architecture Reference
Book

14·12

iLBXTM EXECUTION BUS
•

High Bus Bandwidth
- 9.5 Mbytes/sec. for 8-Blt Transfers
-19 Mbytes/sec. for 16-Bit Transfers

•

16 Mbyte Addressing Range

•

8 and 16-Blt Data Transfers

•

Supports up to 5 ILBXTM Compatible
Devices Per Bus

•

Primary and Secondary Master Bus
Exchange Capabilities

•

Standard 60-Pln MULTIBUS® P2
Connector

The iLBXTM Execution Bus is one of a family of standard bus structures resident within Intel's total system
architecture. The Local Bus Extension (iLBX) Bus is a dedicated execution bus capable of significantly increasing system performance by extending the processor board's on-board local bus to off-board resources. This
extension provides for arbitration-free, direct access to high-performance memory. Acting as a "virtual"
iSBCQ!), up to 16 megabytes of processor addressable memory can be accessed over the iLBX bus and appear
as though it were resident on the processor board. The iLBX Bus preserves advantages in performance and
architecture of on-board memory, while allowing memory configurations larger than possible on a single board
computer. High throughput and independence from MULTIBUS® activities make the iLBX bus an ideal solution
for "working store" type program memory and data processing applications requiring large amounts of high
performance memory. Such applications include graphics systems, robotics, process control, office systems,
and CAD/CAM.

280215-1

14-13

September 1988
Order Number: 280215-001

inter

iLBXTM EXECUTION BUS

FUNCTIONAL DESCRIPTION

Structural Features

Architectural, Overview
The iLBX bus is an architectural solution for supporting large amounts of high performance memory. It is
the first structure that allows the CPU board selection to be decoupled from the on-board memory requirement, and still maximizes the processor's performance potential. It eliminates the processor's
need to access its off-board memory resources
solely over the MULTIBUS system bus. Architectural
consistency with the Single board computer approach including iLBX memory can be maintained by
dual port access of memory resources between the
iLBX bus and the MULTIBUS system bus. This allows for global access by other processors and liD
devices while still providing high, speed local CPU
operations. This sUb-system created by the iLBX bus
of a single board computer and a maximum of 4
memory cards can be perceived architecturally as a
"virtual Single board computer". The implementation
of iLBX bus "virtual modules" makes it possible to
create functional modules with a new level of flexibility and performance in implementing a wide range of
memory capabilities. With future needs in mind, the
iLBX bus has the capability of accessing a full 16
megabytes of memory.

The iLBX bus uses a non-multiplexed 16-bit configuration capable of 8 and 16-bit transfers. Used in conjunction with the MULTIBUS interface, the iLBX bus
resides on the MULTIBUS form factor P2 connector
and supercedes the MULTIBUS interface definitions
for the P2 signals. The iLBX bus uses the standard
60-pin MULTIBUS P2 connector and occupies 56 of
the P2 connector pins with 16 data lines, 24 address
lines plus control, command access, and parity signals. The four MULTIBUS address extension lines
on the MULTIBUS/iLBX P2 connector retain the
standard MULTIBUS interface definition.

Bus Elements
The iLBX bus supports three distinct device categories: 1) Primary Master, 2) Secondary Master, 3)
Slave. These three device types may be combined
to create several iLBX local busses ranging (in size)
from a minimum of two to a maximum of five devices
per iLBX bus. There is only one Primary Master in
any given implementation of iLBX bus, and its presence is required along with the attachment of at
least one Slave device. To provide alternate access
over an iLBX bus, one optional Secondary Master

REMOTE CONTROL MODULES

280215-2

Figure 1. MULTIBUSI8l System Architecture
14-14

intJ

ILBXTM EXECUTION BUS

may be incorporated to create a "two-master" local
bus subsystem. By limiting the iLBX bus to two masters (a Primary and a Secondary), bus arbitration is
reduced to a simple request and acknowledge process, with privileged use of the bus maintained by
the Primary Master, and limited access granted to
the Secondary Master when needed.
The Primary Master executes the role of iLBX bus
"supervisor" by controlling the general operation of
the bus and managing Secondary Master accesses
to the Slave memory resources.
The Secondary Master Device is an option providing
alternate access to the Slave resources on the iLBX
bus. Secondary master devices are typically DMA
driven. This feature is provided for implementation
flexibility when occasional DMA transfers in and out
of iLBX memory resources can optimize the overall
system performance. The Secondary Master essentially duplicates the Primary Master's data transfer
capability, but must rely on the Primary Master to
grant access. Once access is granted, the Secondary Master controls the bus, and drives all signal
lines until the operation is complete and control is
passed back to the Primary Master.
The Slave devices contain the memory resources
used by the Primary Master. and the optional Secondary Master. Each iLBX implementation can contain a maximum of four Slave devices. Using 64K
RAM technology on four slave devices with ECC can
provide for over 2 megabytes of "on-board" high
performance memory. With 256K RAM chips, each
iLBX bus could contain slave devices with memory
totalling 8 megabytes. A,S memory technology, increases, the iLBX bus is designed to incorporate it in
rapid fashion because it is capable of directly accessing a full 16 megabytes of memory on its highperformance Slave devices.

Bus Interface/Signal Line Descriptions
The iLBX bus interface is divided into four functional
classes of Signal lines: address and data lines, control lines, command lines, and bus access lines. The
40 address and data lines defined by the iLBX Bus
Specification consist of 16 data lines and 24 address
lines.
There are 16 bi-directional data lines exclusively
used to handle 8-bit and 16-bit data transfers between the active bus master and the selected slave
device. The iLBX bus uses these data lines for all
data transfers, and are driven by tri~state drivers.
The 24 address lines on the iLBX bus provide the
ability to directly address 16 megabytes of memory.
These single-direction address lines are exclusively

driven by the active bus master. The iLBX bus master uses them to select a specific slave device.
Three control lines specify the type of data transfer
between master and slave devices, while the three
command lines initiate, control, and terminate the
transfer. There are also three bus access lines used
to transfer bus control between master devices.

Bus Pin ASSignments
The iLBX bus uses the standard SO-pin MULTIBUS
P2 connector. The physical location of each pin assignment and its corresponding function is listed in
Table 1. The four MULTIBUS address extension
lines (pins 55-58 on the P2 connector) retain the
standard MULTIBUS interface functions.

Bus Operation Protocol
The operation protocol for the iLBX bus is a straightforward set of procedures consisting of three basic
operations: bus control access, write data to memory, read data from memory. These operations use
asynchronous protocol with positive acknowledgment.

Bus Access
The iLBX bus is shared by at most two masters; one
Primary Master and one optional Secondary Master,
each providing an alternate access path to iLBX bus
memory resources. The mechanism for obtaining
bus access is a simple request and acknowledge
process communicated between masters. Each
master i,s a bus controller of similar capabilities, responsible for data transfer operations between devices, but the Primary Master has the added responsibility of controlling iLBX bus accesses.
The Primary Master has default control of the iLBX
bus. If the Secondary Master needs access to the
bus, it must initiate a request and wait for acknowledgment from the Primary Master. The choice 'of
when to surrender control of the bus rests with the
Primary Master, but if no data transfer is in progress,
the Primary Master normally relinquishes control immediately to the Secondary Master.

Data Transfer Operation
The iLBX bus supports two types of data transfer
operations: write data to memory and read data from
memory. These data transfer operations facilitate
the passing of information between the active bus
master and the selected slave device. The operation
of these two transfer types is very similar; the only
differences being the direction of the data transfer
and the device driving the data lines.

14-15

inter

ILBXTM EXECUTION BUS

For either type of data transfer, the active bus master first initiates the transfer operation by placing the
memory address on the address lines (AB23-ABO)
and a control configuration on the control lines to
select the slave device. Once the slave device is
selected, the type of data transfer becomes the key
factor. With the write operation, the active master
maintains control of the data lines and provides valid
data within the speCified time. Upon accepting a
data element, the slave sends a receipt acknowledgment signal to the master which completes the data
transfer operation.
With the read operation, the slave device drives the
data lines and places valid data on the data lines
before sampling by the active master. The slave acknowledges the master to signal the end of the data
transfer, and the master completes the operation.

The iLBX Bus Specification includes provisions for
both optimized and non-optimized data transfers.
Optimized operation uses pipelining and Signal overlapping techniques to manage the data transfer timing relationships between the active bus master and
the selected. slave. The use of signal overlapping
requires that every device attached to the iLBX bus
provide a means of varying the timing of the slave
request and acknowledge Signals. The non-optimized operation uses fixed signal sequences, instead of signal overlapping, to assure a valid data
transfer, and a device does not need a variable request or acknowledge to read data-valid timing on
the iLBX bus. Please refer to the iLBX Bus Specification for detailed descriptions of these transfer operations.

Table 1. ILBXTM Bus Pin Assignments, P2 Edge Connector
Component Side
16-BltPln

Mnemonic

Solder Side

Signal Name

16-BII Pin

Mnemonic

Signal Name

1
3
5
7
9
11
13
15
17

DBO
DB2
DB4
DB6
GND
DB9
DB11
DB13
DB15

Data Line 0
Data Line 2
Data Line 4
Data Line 6
Ground
Data Line 9
Data Line 11
Data Line 13
Data Line 15

2
4
6
8
10
12
14
16
18

DB1
DB3
DB5
DB7
DB8
DB10
DB12
DB14
GND

Data Line 1
Data Line 3
Data Line 5
Data Line 7
Data Line 8
Data Line 10
Data Line 12
Data Line 14
Ground

19
21
23
25
27
29
31
33
35

ABO
AB2
AB4
AB6
GND
AB9
AB11
AB13
AB15

Address
Address
Address
Address
Ground
Address
Address
Address
Address

Line 9
Line 11
Line 13
Line 15

20
22
24
26
28
30
32
34
36

AB1
AB3
AB5
AB7
AB8
AB10
AB12
AB14
GND

Address Line 1
Address Line 3
Address Line 5
Address Line 7
Address Line 8
Address Line 10
Address Line 12
Address Line 14
Ground

37
39
41
43

AB16
AB18 ,
AB20
AB22

Address Line 16
Address Line 18
Address Line 20
Address Line 22

38
40
42
44

AB17
AB19
AB21
AB23

Address Line 17
Address Line 19
Address Line 21
Address line 23

45
47
49
51

GND
BHEN
ASTBo
SMRQ·

Ground
Byte High Enable
Address Strobe
Secondary
Master Request
Access Lock

46
48
50
52

ACK·
R/W
DSTB*
SMACK·

GND.

Slave Acknowledge
Read Not Write
Data Strobe
Secondary Master
Acknowledge
Ground

MULTIBUS@ Address
Extension Line 22
MULTIBUS@ Address
Extension Line 20
Reserved

ADR23·

ADR21·

TPAR·

LOCK·

ADR22 "

ADR20·

RES

Line 0
Line 2
Line 4
Line 6

14-16

MULTIBUS@ Address
Extension line 23
MULTIBUS@ Address
Extension Line 21
Transfer Parity

inter

ILBXTM EXECUTION BUS

Mechanical Implementation

SPECIFICATIONS

Because the iLBX bus uses the P2 connector of the
MULTIBUS form factor, the iLBX bus "shares" a
MULTIBUS chassis with the MULTIBUS backplane
system bus in the system design. The iLBX mechanical specifications are synonymous with the MULTIBUS specifications for board-to-board spacing,
board thickness, component lead length, and component height above the board. The iLBX bus interconnection can use either flexible ribbon cable or a
rigid backplane. The iLBX bus interconnect maximum length is limited to 10 cm (approximately 4
inches); that is sufficient to span 5 card slots across
two connected chassis. Figure 2 shows an iLBX bus
cable assembly.

Word Size
Data: 8 and 16-bit

Memory Addressing
24-bits-16 megabyte-direct access

Bus Bandwidth
9.5 megabytes/sec: 8-bit
19 megabytes/sec: 16-bit

280215-3

Figure 2. TypicallLBXTM Bus
Interface Cable Assembly

Electrical Characteristics
DC SPECIFICATIONS
Table 2
Signal
Name

Driver
Type

Termination
(to +5 Vdc
At Master

DS1S-0
TRI-STATE 10Kn
TRI-STATE 10Kn
TPAR"
AS23-0
TRI-STATE None
R/W
TRI-STATE None
TRI-STATE None
SHEN
TRI-STATE None
LOCK"
TTL
10Kn
SMRO"
SMACK" TTL
None
tASTS"
TRI-STATE 10Kn
tDSTS"
TRI-STATE 10 Kn
Open Coli.
330n
ACK"
..
tAt slave. additional senes RC termination to

Min Driver Requirements
High
Load Cap.
Low
O.SmA
9mA
7SpF
O.SmA
7SpF
9mA
120pF
O.4mA
20mA
0.2mA
8mA
7SpF
8mA
7SpF
0.2mA
0.2mA
8mA
7SpF
O.OSmA
2mA
20pF
O.OSmA
2mA
20pF
0.2mA
9mA
7SpF
0.2mA
9mA
7SpF
N.A.
20mA
4SpF
GND (100 n. 10 pF) •
14-17

Max Receiver Requirements
High
0.1SmA
0.1SmA
0.10mA
O.OSmA
O.OSmA
O.OSmA
O.OSmA
O.OSmA
O.OSmA
O.OSmA
O.OSmA

Low
2mA
2mA
SmA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA

Load Cap.
18 pF
18pF
30pF
18pF
18 pF
18pF
18 pF
18 pF
18 pF
18 pF
18pF

ILBXTM EXECUTION BUS

BUS TIMING

TR~STATE
PRIMARY DRIVERS
MASTER

_
-========~S:3t--f~~======

SECONDARY MASTER _ _ _ _ _ _ _ _ _ _ _~==~-----TR~STATE DRIVERS

280215-4

Figure 3. IL8XTIII Bus Granting Timing Chart
16·Blt Transfer Timing
I

AB23toA80

~
I

BHEN

~r----~r-----~

I I

-r/jT'771'T'ZT'771'T'ZMl4

vzmllll/l4r-II---.. .Wmzmm;mmmx
.
_ _ _ _I_ _~III

~r7I!"TZTlI!"T2T'7V"TZT'7V"T7T'771"TZ"'71"Tl>/?(
I

'IllllllL
YlllllZ

DB15toDBO

DSTB*

280215-5

Figure 4. Write Data·to-Memory

14·18

ILBXTII EXECUTION BUS

BUS TIMING (Continued)
16-Blt Transfer TImIng (Continued)

7l¥.------t----wmm
"

AB23 to ABO

BHEN

R/W

ASTB*

W1ll/IlM :
I

I I

IfllllIl4

----------~

YllL

W7llllllllfl/////////XM:-~'lllllll
I

Wv!!ll!lTdlZWX'--;-:--'XlllllZ
I

I~--------~----~

DB151DDBO

DSTB*

ACK*

280215-6

fIgure 5. Read Data-from-Memory

14-19

":::r

II l
...
-

TYPICAL EJECTOR HOLE 109
2 PLACES

n
:::r
ID
ID

CD
::!.

C'II
C!:

;

16· BIT

r=
UI

C'II

COMPONENT SIDE

m
><
....

1/1

;:,

..... ...DIa.
t\,
""" a.
0

."
::1

;:,
CD

....
....
z

....
u
....c
z

u·

u
c
0

iI:

m
><
m

...0

....

a.
n
~
C

-I

oeR

lOPL

:;:

ra.
0
c

!IE

;:,
CD

I II I

...'"
0

0.,. _

-:'"0

DETAIL

-l 1-

100

DETAIL

00.. -r!o

--TYPICAL

050 TYP

RADIUS PERMISSIBLE

~
.30

.045

280215-7

6
Z
m
C
en

intJ

ILBXTM EXECUTION BUS

Cables and Connectors

Environmental Characteristics

Table 3. Cable and Receptacle Vendors
iLBXTM Bus Compatible Cable
Vendor
T & BAnsley
T & BAnsley
3M
3M
Berg
Belden
Spectrastrip

Vendor Part No.
171·60
173·60

3365/60
3306/60
76164·060
9L28060
455-240-60

Conductors
60
60
60
60
60
60
60

OPERATING
Temperature: O·C to 60·C
Relative Humidity: 0% to 85%; non-condensing

Reference Manuals
210883-002-MULTIBUS Architecture Reference
Book

iLBXTM Bus Compatible Receptacles
Vendor

Vendor Part No.

Pins

Kelam
T &BAnsley

RF30-2803-5
A3020
(609-6025 Modified)

60
60

14-21

ISA Boards and Systems

INTEL386™ MICROCOMPUTER MODEL 302

INTEL 25 MHZ 386rM PERFORMANCE
IN AN ISA COMPATIBLE
Running at 25 MHz, the Intel 386" MicroComputer Model 302 offers OEMs state-of-the-art
performance in an ISA-compatible design. A 64KByte cache provides effective 0 wait state
execution, without the high cost of fast-access main memory. Memory capacity is extensive,
beginning with 4MB on-board, expandable to 24MB via two 32-bit expansion slots.
Additionally, the Model 302 is designed to pass FCC Band VDE B levels of EMI/RFI
regulations, a significant test at 25 MHz.
Based on the ISA architecture, the Model 302 is compatible with such software products as
MS-DOS, OS/2, and UNIX'. Furthermore, ISA hardware products from a multitude of
vendors plug into eight 1/0 expansion slots.

STANDARD FEATURES:
• Intel 386 microprocessor running at
25 MHz
• 64Kbyte cache (0 w.s. performance)
• 0, 2, 4, or 8MB main memory
• Phoenix Technologies ROM BIOS
• High reliability chassis
• 8 1/0 expansion slots

•
•
•
•
•
•
•

220-watt power supply
2 32-bit 110 expansion slots
2 serial ports
1 Centronics parallel port
5 half-height, 5%" penpheral bays
FCC-class BNDE Level B
ULlCSAlTUV

OPTIONS:
• Intel 387 math coprocessor running at
25 MHz
• 1.2MB floppy drive

• 8-16MB extended memory
• 40MB Winchester drive
• 4 MB and 8 MB add-in memory cards

in1:el'--------;------May, 1988

Order Number 280984-001

15-1

SPECIFICATIONS
BASE SYSTEM
Central Processor

ELECTRICAL
Intel 386 microprocessor,
25 MHz

AC Voltage/Frequency
DC Power
+5v
+ 12v

Floating-Point Processor Intel 387 microprocessor,
25 MHz
Main Memory
RAM
Extended Memory
Maximum RAM
Cycle Time
Data Bus Width
Error Detection
Cache
I/O

Floppy Disk Option
Step Rate
Head Settling Time

0, 2, 4, or 8 MB, on-board
8t016MB
24MB
80 ns
32-Bits
Bit Parity
64K Bytes, Direct map with
write through
2 serial ports (asynch,
RS232C, 9-pin
connector) AT
Compatible)
1 parallel port (Centronics
compatible, 25-pin
connector, AT
Compatible)
8 expansion slots
2 32-bit, 16-bit, or 8-bit
slots
1 8-bit slot
5 16-bit or 8-bit slots

UL 478 5th Edition
CSA C22.2 No. 154
IEC 435 & VDE 0806
FCC 47 CFR Part 15
Subpart J, Class B
VDE 0871 Level B

ENVIRONMENT

To 85%
To 95%

Altitude
Operating:

To 10,000 feet

Static Discharge:

Kv max

35 pounds (15.9 kg)

Factory services include product repair or exchange,
spare part sales, and advanced service diagnostics.

5.25" footprint
1.2 MB high density
3 milliseconds
15 ms max

Ambient Temperature
System On:
System Off:
Relative Humidity
System On:
System Off:

18.7 inches (47.5 cm)
21.3 inches (54.1 cm)
6.4 inches (16.3 cm)

Field services include product installation,
configuration, and maintenance.

Meets or exceeds the following requirements:

Europe

Length
Width
Height
Approximate Weight
(Base system)

WORLDWIDE SERVICE AND SUPPORT

REGULATIONS

EMIIRFI
US and Canada

PHYSICAL CHARACTERISTICS

1 year warranty. '

Winchester Disk Option 5.25" half height
40.8 MB formatted
Access Time
28 ms typ

Safety
US
Canada
Europe

-12v
-5v

Switching power supply,
115 V/60Hz or 230 V/50 Hz
220W
23.0 A maximum continuous
8.0 A maximum continuous;
12.0 A maximum surge
15 seconds
0.5 A maximum continuous
0.5 A maximum continuous

15.6 to 40°C
- 34 to 60 0 C

15-2

INTEL386™ MICROCOMPUTER MODEL 302-20

THE HIGH-PERFORMANCE 20 MHZ 386'" STANDARD
The Intei386'· MicriJComputer Model 302-20 provides an excellent price-performance
mix for the OEM building high-performance computer-based products. The Model 302-20
mother- board contains a 20 MHz 386'· microprocessor-the industry-standard
workhorse of 386 computing-a socket for an Intel 387" math coprocessor or Weitek
1167 math coprocessor, and 2 MB of interleaved main memory, expandable to 16 MB. For
fast time to market, the Model 302-20 is available as an FCC certified system product.

FEATURES
• 20 MHz 386 microprocessor
• Zero wait state performance
• Socket for 387 math coprocessor or
Weitek1167
• Phoenix ROM BIOS
• Eight standard fSA 1/0 slots
• Two serial ports, one parallel port
• Five half-height 51/4" peripheral bays

-ntel'

'Same product _

by IDle! Po""" RIco, Inc

«: InlE::1 CorpOld.liOn 1989

15-3

September, 1989
Order Number 280977-002

SPECIFICATIONS
BOARD
Central Processor

ELECTRICAL
Intel 386 microprocessor,
20 MHz

Floating-Point Processor Intel 387 math
coprocessor, 20 MHz
Weitek 1167,20 MHz
Memory
Standard
Maximum
Cycle Time
Data Bus Bandwidth
Error Detection
I/O

Options

2 MB on-board SIMM
16 MB on-board SIMM
80 ns
32 bits
Parity
2 serial ports (asynch,
RS232C, 9-pin
connector)
1 parallel port (Centronics
compatible, 25-pin
connector)
8 expansion slots
7 16-bit or 8-bit slots
1 8-bit slot
4 MB SIMM memory
8 MB SIMM memory

SYSTEM
Peripherals
Power Supply
Options

Floppy drive, 5%,', HH
'=our spare HH, 5%" bays
220W
Customer installed hard
drive

AC Voltage/Frequency
DC Power
+5V
+12V
-12V
-5V

Switching power supply,
115 V/60Hz or 230 V/50
Hz
220W
23.0 A maximum continuous
8.0 A maximum continuous;
12.0 A maximum surge
15 seconds
0.5 A maximum continuous
0.5 A maximum continuous

PHYSICAL CHARACTERISTICS
Length
Width
Height
Approximate Weight
(Base system)

18.7 inches (47.5 cm)
21.3 inches (54.1 cm)
6.4 inches (16.3 cm)
35 pounds (15.9 kg)

WORLDWIDE SERVICE AND SUPPORT
Multiply your sales potential in new markets
throughout the world using Intels worldwide service
organization to install and maintain your system at
your customerS site.
'
,
'
Field services include product installation, on-site
maintenance, including third party peripherals, percall or carry-in repair. Network installation and
configuration services are also available.
Factory services include system-level, board or
peripheral repair or exchange. Spare part sales and
advanced service diagnostics are also available.

REGULATIONS

ORDERING INFORMATION

Meets or exceeds the following requirements:

For more information or the number of your nearest
Intel sales office, call 800-548-4725 (good in the U.S.
and Canada).

Safety
US
Canada
Europe
EMI/RFI
US and Canada
Europe

UL 478, 5th Edition
CSA C22.2 No. 220-1986
IEC950
FCC 47 CFR Part 15
Subpart J, Class B
VDE 0871 Level B

ENVIRONMENT
Ambient Temperature
Operating:
Relativ~ Humi'dity
Operating:

10°C to 35°C
' To 85%

Altitude
Operating:

To 10,000 feet

Static Discharge:

7.5 Kv max

15-4

INTEL386™ MICROCOMPUTER MODEL 303

33 MHZ AT-BUS PLATFORM FOR BUILDING HIGH·PERFORMANCE
386'" SYSTEMS
Based on the 33 MHz 386'" microprocessor, the InteI386'· MicroComputer Model 303
combines state-of-the-art performance, ISA compatibility, and unparalleled expansion
capability to deliver a microcomputer platform ideally suited for file server and other highperformance applications_Available In either board or system configurations, the Model 303
features 33 MHz performance, 10 I/O expansion slots, and full FCC emission compliance_

FEATURES
• 33 MHz 386 motherboard with 4 MB
RAM
• 10 I/O expansion slots
- Two 8116/32 bit
-Seven 8/16 bit
-One 8-blt

•
•
•
•
•

Full FCC Class B emission compliance
33 MHz 387'· math coprocessor socket
64 Kbyte cache with 0 wait states
Eight half-height 5_25" peripheral bays
300 watt power supply

ADDITIONAL SYSTEM·LEVEL FEATURES
• 170 MB SCSI hard drive
• 150 MB SCSI tape drive
• 1.44 MB 3_5" floppy drive

• 1.2 MB 5.25" floppy drive
• Power sequencing board

imJ-------------------prodUCfB .... manufactured by Intel Puerto Rlco_'lnc.

July, 1989

"Intel Corporation 1989

Order Number 280976-002

15-5

THE FASTEST 386'" ENGINE AROUND

FULL FCC EMISSION COMPLIANCE

At 33 MHz, the Intel386 MicroComputer Model 303 is
the fastest 386-based compute platform on the market
today. The high-speed 386 CPU can be augmented
by an 387 math coprocessor, also running at 33 MHz.
Performance is further enhanced by a 64 Kbyte cache
memory that provides zero wait state execution without
the cost of fast-access main memory.

The Model 303 baseboard has been designed for
emission suppression and complies fully with FCC
Class B emission requirements, a significant
accomplishment at 33 MHz. The Model 303 system
chassis also helps contain emissions. Emissions
reduction facilitates product integration where stringent
FCC-BNDE-B compliance is required.

EXPANSION FLEXIBILITY

WORLDWIDE SERVICE AND SUPPORT

The Model 303 motherboard was designed from the
ground up for OEM customization. Standard features
include 4 MB of main memory, ten I/O expansion slots,
two serial ports, one parallel port, one AT-style
keyboard connector, and one PS/2-style mouse
connector.

Multiply your sales potential in new markets throughout
the world using Intel's worldwide service organization
to install and maintain your system at your customer's
site.

On-board memory can be expanded to 8 MB using
SIMM memory technology. Additional add-in
memory-up to 32 MB-is available utilizing Intel's
proprietary 32-bit memory bus and Intel add-in
memory cards. The maximum memory configuration
is 40 MB of high-speed memory.

Field services include product installation, on-site
maintenance, including third-party peripherals, per-call
or carry-in repair. Network installation and configuration
services are also available.
Factory services include system-level, board or
peripheral repair or exchange. Spare parts sales and
advance service diagnostics are also available.

The high-speed CPU easily supports heavy peripheral
I/O traffic. The Model 303 system configuration
contains eight half-height peripheral bays to support
the increased storage demands of high-performance
applications such as servers, CAD/CAM, and graphics.
A power sequencing board supports smooth
simultaneous power-up of multiple peripherals. And,
the 303.5 watt power supply powers the loading of all
eight peripheral bays, as well as the ten I/O slots on
the baseboard.

SPECIFICATIONS
BOARD
CPU
Floating point
Motherboard Memory
Standard RAM
MaXimum RAM

110
386 microprocessor at
33 MHz
387 MHz socket
4 MBSIMM
8 MBSIMM

32-bit Add-in Memory (via 4, 8, 16 MB add-in cards)
Maximum add-in
memory
32MB
Maximum system
memory
40MB
Cycle Time
Error Detection

100 nsec
Byte Parity

64 KByte cache, 0 wait state execution on read hit
(direct mapped, posted write through)

•
•
•
•

2 serial ports (9 pin)
1 parallel port (Centronics compatible, 25 pin)
1 AT style keyboard connector
1 PS/2 style mouse connector

BOARD DIMENSIONS
13" x13.6"

ELECTRICAL
Input:
AC Voltage/Frequency 115 V/60 Hz 230 V/50 Hz
(externally configurable)
Output DC Voltage:
+5V
+12V

110 EXPANSION SLOTS
• 2 8116/32 bit slots (AT-32/1SA)
• 7 8116 bit slots (ISA)
• 1 8 bit slot (I SA)

-12V
-5V
Total Power Output:

35.0 A maximum
continuous
10.0 A maximum
continuous
(14A peak for 15 secon.ds)
0.5 A maximum
continuous
0.5 A maximum
continuous .
303.5 Watts (switching)

SYSTEM
Floppy Disk Options
Footprint
Capacity
Footprint
Capacity

3.5"
1.44 MB
5.25"
1.2 MB

SCSI Winchester Disk Option
Footprint
5.25"
170 MB
Capacity
Average Seek Time
14 ms
SCSI Tape Drive Option
Footprint
5.25"
150 MB
Capacity
Eight half height 5.25" peripheral bays (4 internal,
4 external)
Front mounted recessed reset switch

SYSTEM DIMENSIONS
Height
Width
Depth
Base System weight

24.4 Inches
6.8mches
27.75 inches
67 pounds
(without peripherals)

REGULATIONS
Meets or exceeds the following requirements:
Safety
U.S.
Canada
Europe
EMIIRFI
U.S. and Canada
Europe

UL 478 5th edition
CSA C22.2 No. 154
IEC 435 and VDE 0806

FCC47 CFR Part 15
Subpart J Class B
VDE 0871 Level B

15-7

PRELIMINARY
INTEL 486™ MICROCOMPUTER MODEL 401

BE THE FIRST IN YOUR MARKET
WITH A 25 MHZ 486™ MICROPROCESSOR-BASED SYSTEM
Intel's 486'" Microcomputer Model 401 is the fastest way to be the first to market with a
486 microprocessor-based compute platform. The Model 401 features ISA (Industry
Standard Architecture) compatibility, flexible expansion and customization, 386'" software
compatibility, state-of-the-art 25 MHz 486 microprocessor performance, and Intel's worldclass quality, service and support backing you up after the sale.

BOARD-LEVEL FEATURES

OPTIONS

• 486 microprocessor running at 25 MHz
• 8 Kbytes of 4-way set-associative onchip cache memory With zero waitstates
• High-performance main memory
structure With 8 MB of interleaved 80
nanosecond DRAMs
• 8 expansion slots (4 32-bit)
• On-board floppy disk controller
• Phoenix Technologies ROM BIOS

• 8 MB expansion memory boards
(expandable to 32 MB)
• 101-key enhanced keyboard
• Intel worldwide service!maintenance!
network support
• MS-DOS', MS-OS!2', and UNIX' V.3.2
software

SYSTEM-LEVEL FEATURES
• Eight half-height 5.25" peripheral bays
(4 internal, 4 external)
• 1.44 MB 3.5" flexible disk drive
• 1.2 MB 5.25" flexible disk drive
• 170 MB SCSI hard disk drive
• 150 MB SCSI tape drive
• Full FCC Class B emission compliance

imJ~-----------------e Intel Corporation 1989

15-8

September. 1989'
Order Number 28()986.001

FEATURES
A 486'" ENGINE PACKED WITH POWER.
The 486 Microcomputer Model 401 features all the
configuration flexibility an OEM could want. The
motherboard includes eight expansion slots, an onboard floppy disk controller, two serial ports, one
parallel port, a keyboard port, and a PS/2 mouse
port.
The power of the 25 MHz 486 microprocessor is
enhanced by a high-speed memory structure that
features interleaved 80-nanosecond DRAMs
supporting zero wait-state burst mode reads.

A COMPLETELY CONFIGURABLE TOWER
CHASSIS.
You can buy the Model 401 motherboard only; or, you
can buy a complete Model 401 system, partially or
fully integrated, ready for resale to your customers.

The 401 tower has eight half-height 5.25" peripheral
bays to support the massive storage demands of
high-performance applications such as servers,
workstations, CAD/CAM and graphics. The highspeed CPU easily supports the heavy I/O traffic, and
the 303.5 Watt power supply powers the loading of all
eight peripheral bays, as well as the eight I/O slots on
the baseboard.

SOFTWARE COMPATIBILITY.
The Model 401 runs industry-standard operliting
systems like MS-DOS, MS-OS/2, and UNIX,
preserving your existing software investment and
guaranteeing a smooth growth path from 386 to 486
architectures. Intel further reduces your software
development and support costs through extensive
hardware and software compatibility testing.

WORLDWIDE SERVICE AND SUPPORT.

The Model 401 system product comes in a tower
chassis that measures only 24.4" high and 6.8"
wide-short enough to fit under the most restrictive
table and slim enough to nest multiple 401s side by
side in a powerful network.

Multiply your sales potential in new markets
throughout the world using Intels worldwide service
organization to install and maintain your system at
your customerS site.

The cabinet design allows for hidden peripheral and
network cabling connections at the top rear of the
chassis with an easy access door. Ease-of-use
features include a power switch on the front bezel,
and recessed keylock and reset switches.

Support contracts are available for hardware/
software engineering assistance; repair and
maintenance for Intel and non-Intel systems and
peripherals; network design, installation and
maintenance; and training.
Factory services include system-level, board or
peripheral repair or exchange. Spare parts sales and
advance service diagnostics are also available.

SPECIFICATIONS
BOARD
CPU

BOARD DIMENSIONS
486 microprocessor at
25 MHz

Motherboard memory
Standard
Maximum

8 MB interleaved
32 MB

Burst mode

zero wait-state reads

Data bus resolution

32 bits

Cache memory

a Kbytes on-Chip 4-way set
associative cache

12.0" x 13.0" (30.4 cm x 33.0 cm)

ELECTRICAL
Input:
AC Voltage/Frequency 115V/60 Hz 230V/50 Hz
(externally configurable)
Output DC Voltage:
+5V
+12V
-12V
-5V

110 EXPANSION SLOTS
Eight add-in expansion slots
Four 8/16/32-bit
Three al16-bit
One8-bit

Total Power Output

110
Two serial ports (g-pin)
One parallel port (Centronics-compatible, 25-pin)
One AT-style keyboard connector
One PS/2*-style mouse connector
15-9

35.0 A maximum continuous
10.0 A maximum continuous
(14 A peak for 15 seconds)
0.5 A maximum continuous
0.5 A maximum continuous
303.5 Watts (switching)

SPECIFICATIONS
SYSTEM

REGULATIONS

Floppy Disk Options
Footprint
Capacity
Footprint
Capacity

3.5" half-height
1.44 MB
5.25" half-height
1.2 MB

Meets or exceeds the following requirements:

Hard Disk Drive
Footprint
Capacity

5.25" half-height
170 MB

Tape Drive
Footprint
Capacity

5.25" half-height
150 MB

Safety
USA
Canada
Europe
EMIIRFI
USA
Europe
Canada

SYSTEM DIMENSIONS
Height
Width
Depth
Base system weight

24.4 inches (62.0 cm)
6.8 inches (17.3 cm)
27.75 inches (70.,5 cm)
67 pounds (30.5 kg) (without
peripherals)

15-10

UL 478. Edition 5
CSA C22.2 No. 220
IEC 950 & IEC 380
FCC Class B; CFR 47 Part
15 Subpart J
VDE 0871 Level B
DOC; CRC c.1374. Class B

INTEL386™ MICROCOMPUTER MODEL 300SX

LOW COST 32-BIT COMPUTE PLATFORM BASED ON 386S)(",
MICROPROCESSOR TECHNOLOGY
The Intel386™ MicroComputer Model 300SX is a cost-effective 32-bit compute platform
based on the low-cost 386SXTM microprocessor. Available in several configurations at
either the board or system level, the Model 300SX provides excellent integration flexibility
for OEMs building custom 386SX systems. The Model 300SX features four slots for OEM
customization,2 MB of on-board RAM, and a high-performance disk subsystem.

FEATURES
•
•
•
•
•
•

16 MHz 386SX
2MB on-board memory
On-board floppy controller
Four 16-bit ISA slots
Two AT-style serial ports
VGA/EGA/CGAlHercules graphics
support

• Complete 32-bit software compatibility
• 387SX socket for math-intensive
operations
• Small footprint chassis (system)
• Worldwide Intel service and support

intel°---------*300 sx produClS art' manufactured by Intel Puerto ~co. Inc and SIngapore

Intel Corporation

1.)<.\ 1

September, 1989

Order Number 280955-002

BROAD CONFIGURATION FLEXIBILITY

HIGH·PERFORMANCE DISK SUBSYSTEM

Intel offers two board-level and three different systemlevel configurations of the Model 300SX, so you can
select the platform best suited to your needs. Board
or system, with or without peripherals or chassis, the
Intel386 MicroComputer Model 300SX is an excellent
foundation on which to build your high-performance
386SX product.

The Model 300SX frees a slot for use by the OEM by
providing an on-board floppy controller and an
embedded Winchester controller interface right on
the motherboard. A look-ahead cache boosts hard
disk access times to 12 msec. Optional peripherals
include a 3.5" 1.44 MB floppy and a 3.5" 40 MB
high-performance Winchester disk.

LOW-COST BOARD-LEVEL INTEGRATION

BUILT-IN GRAPHICS SUPPORT

The powerful Model 300SX compute engine is
available as a standalone motherboard for integration
into your custom system. The 300SX single-board
computer contains the following standard features:
• 2 MB SIMM memory
• 387SX socket for math-intensive operations
• VGA/EGA/CGA Mono.lHercules graphics interface
• PS/2 mouse port
• Two AT-style serial ports
• Parallel port
• TTL and analog video connectors

The Model 300SX contains on-board support for all
standard color graphics monitors- VGA, EGA, CGA,
Monochrome and Hercules-saving another slot you
don't have to use for a graphics board. Both analog
and TTL connector hardware are included on the
board.

LOW-COST 386SX"" TECHNOLOGY IN
A HIGH-PERFORMANCE SYSTEM

WORLDWIDE SERVICE AND SUPPORT
Multiply your sales potential in new markets
throughout the world using Intels worldwide service
organization to install and maintain your system at
your customerS site.

The Intel386 MicroComputer Model 300SX provides
more configuration options and high-performance
system features than any other 386SX platform. All
system configurations feature four 16-bit slots
available for OEM customization, 2 MB of on-board
RAM for running large applications, a highperformance disk subsystem, built-in graphics
support, and a small footprint chassis.

Field services include product installation, on-site
maintenance, including third party peripherals, percall. or carry-in repair. Network installation and
configuration services are also available.
Factory services include system-level, board or
peripheral repair or exchange. Spare part sales and
advance service diagnostics are also available.

SPECIFICATIONS
BOARD
CPU
Floating point math
Memory
Standard RAM
Maximum RAM
Cycle Time
Error Detection
I/O
2 serial ports
1 parallel port
1 mouse port
4 slots

SYSTEM
386SX microprocessor at
16 MHz

Floppy Disk Option
Footprint
Capacity

3.5", Va Height
1.44 MB

387SX socket
Winchester Disk Option
Footprint
Capacity
Average access
Effective access
with cache

2 MBSIMM
4 MBSIMM
125 ns
Byte Parity

3.5", V2 Height
40MB
19 msec
12 msec

Physical Characteristics
Height
6"
Width
14"
Weight
271bs

Async, RS 232 C, 9-pin
Centronics compatible,
25-pin
PS/2 compatible
16-bit ISA compatible

Physical Characteristics
Width
12"
Depth
10"
Weight
3.31bs

15-12

ORDERING INFORMATION

ELECTRICAL
AC Voltage/Frequency

Switching power supply,
115 V/60 Hz or 230V/
50 Hz; convenience
outlet

DC Power
+5V

145W
18.0 A maximum
continuous
4.2 A maximum continuous
6.0A maximum continuous
for 15 seconds

+12 V

-12 V
-5V

For more information or the number of your nearest
sales office, call 800-548-4725 (good in the U.S. and
Canada).

0.3 A maximum continuous
0.2 A maximum continuous

REGULATIONS
Meets or exceeds the following requirements:
Safety
U.S.
Canada
Europe
EMI/RFI
U.S. and Canada
Europe

UL 478 5th edition
CSA C22.2 No. 220
IEC 435 and VDE 0806

FCC47 CFR Part 15
Subpart J Class B
VDE 0871 Level B

15-13

INTEL386™ MICROCOMPUTER MODEL 301Z

HIGH·PERFORMANCE 32·BIT COMPUTE PLATFORM WITH
ISA COMPATIBILITY
. The Inte1386'" MicroComputer Model 301Z offers the power of the 386TO microprocessor
with the flexibility of the Industry Standard Architecture (ISA). This combination produces a
board or system platform suitable for building high-performance applications like computeraided design (CAD), computer-aided engineering (CAE), and advanced financial analysis, .
which require greater processing and memory capability. The Model 301Z features eight
slots, so you can customize the system using off-the-shelf boards, operating systems, and
application software.

STANDARD FEATURES:
•
•
•
•
•

Intel386 processor running at 16 MHz
2 MB zero wait state main memory
Eight 16-bit ISA slots
One serial, one parallel port
38?T" socket for math-intensive
operations
• Phoenix Technologies ROM BIOS
• Worldwide Intel service and support

June, 1988
..)rder Number 280827-005

15-14

BROAD CONFIGURATION FLEXIBILITY
Intel offers several configurations of the Model 301Z, so
you can select the platform best suited to your needs.
Board or system, with or without peripherals or
chassis, the Intel386 MicroComputer Model301Z is an
excellent foundation on which to build your highperformance 16 MHz 386 product.

COST-EFFECTIVE BOARD·LEVEL
INTEGRATION
The Model 301Z compute engine is available as a
standalone motherboard for integration into your
custom system. Two megabytes of on-board memory
running at zero wait states, and the ability to download
Phoenix BIOS into RAM, provide excellent
performance. For maximum configuration flexibility, the
301Z board offers 32-bit memory, expandable to 16
MB, and eight I/O expansion slots.
The 301Z single-board computer captures the full 32bit capabilities of the powerful 386 CPU without
sacrificing compatibility with the industry-standard 8
MHz ISA bus. Exhaustive testing of numerous add-in
boards, operating systems, and software assures
broad compatibility across a range of applications.

QUICK TIME·TO·MARKET SYSTEM
PLATFORM
The Intel386 MicroComputer Model 301Z provides a
large number of configuration options and highperformance features. All system configurations of the
Model 301Z feature eight slots (two 8-bit PC XT, two
8-bit PC XT or 32-bit memory expansion, and four 16bit ISA), serial and parallel ports, and expansion
capability for up to five half-height 5.25" peripheral
devices.

WORLDWIDE SERVICE AND SUPPORT
Multiply your sales potential in new markets throughout
the world using Intel's worldwide service organization
to install and maintain your system at your customer's
site.
Field services include product installation and on-site
maintenance, including third-party peripherals and
per-call or carry-in repair. Network installation and
configuration services are also available.
Factory services include system-level, board or
peripheral repair or exchange. We alsQ offer spare part
sales and advance service diagnostics.

SPECIFICATIONS
BOARD
CPU
Floating point math
Memory
Standard RAM
Maximum RAM
Cycle Time
Error Detection
I/O
One serial port
One parallel port
8 slots

ELECTRICAL
386 microprocessor at 16 MHz
387 socket
2 MB on-board
16 MB
125 ns
Byte Parity
Async, RS-232-C, 9-pin,
AT-compatible
Centronics-compatible, 25-pin,
AT-compatible
2 32-bit or 8-bit slots
2 8-bit slots
4 16-bit or 8-bit slots

Physical Characteristics
Width
13.8"
Depth
12.0"
Weight
36.8 oz

SYSTEM
Floppy Disk Option
Footprint
5.25"
Capacity
1.6 MB unformatted
Winchester Disk Option
Footprint
5.25"
Capacity
40.8 MB formatted
Average access
28 msec
Physical Characteristics .
Height
6.5"
Width
21.3"
'Weight
44 Ibs

AC Voltage/Frequency Switching power supply, 115
V/60 Hz or 230 V/50 Hz;
convenience outlet
DC Power
220W
23.0 A maximum continuous
+5v
+12v
8.0 A maximum continuous
11.0 A maximum total for 15
seconds
-12v
0.5 A maximum continuous
-5v
0.5 A maximum continuous

REGULATIONS
Meets or exceeds the following requirements:
Safety
UL 478 5th edition
U.S.
CSA C22.2 No. 154
Canada
IEC 435 and VDE 0806
Europe
EMIIRFI
FCC47 CFR Part 15 Subpart J
US and Canada
Class A
VDE 0871 Level A
Europe

15-15

INTEL SOFTWARE PRODUCTS

SOFTWARE PRODUCTS FOR FAST TIME-TO-MA-RKET
Intel has a wide range of software products and services to support the OEM. These
products include MS® OS/2, MS-DOS,® and Diagsoft diagnostics. All have been tested
and evaluated to meet Intel's high standards of compatibility and reliability. All are also
supported by Intel's online Product Assistance Network (iPAN) and Intel's Phone Action
Line Support (iPALS) services. Intel's OEM support program provides all the assistance you
need to get your products to market quickly.

FEATURES:
•
•
•
•
•
•

Industry-standard software
Improves OEM time-ta-market
Proven software reduces risk
Complete end user packages with documentation
Intel-supplied device drivers for integrated systems
End user break-the-seal license

imJ------------------September; 1988

Order Number 280952-001

15-16

MICROSOFT MS® OS/2 OPERATING SYSTEM
~
MICROSOFTDOS2
~

••I

PRESENTATION
MANAGER
INCLUDED

Microsoft MS OS/2
Release 1.1 is a singleuser operating system
for the Inte1386'"
MicroComputer family of
products, giving users
multitasking capabilities,
freedom from MS-DOS memory constraints, a
standardized user interface, interprocess
communication and dynamic data exchange. MS
OS/2 also gives you access to the wealth of MS-DOS
software using the MS-DOS compatibility mode
window.
The MS OS/2 Operating System has numerous
features that make it a superior choice for largememory applications. MS OS/2 provides an execution
engine tailored to Intel's 386 MicroComputer family of
products. It also eliminates the 640 Kbyte memory
constraints by allowing you to address up to 16MB of
user memory.
MS OS/2 also provides a standard human interfacepresentation manager-that transcends Microsoft
Windows/386® and the MS-DOS 4.01 visual shell. The
MS OS/2 presentation manager represents the state of
the art in graphical user interfaces for personal
workstations.

Intel's adaptation of MS OS/2 contains the basic
operating system kernel, presentation manager and
the basic set of MS OS/2 utilities to execute on Intel's
386 MicroComputer family of products. MS OS/2
supports the following features:
•
•
•
•
•
•
•
•
•
•
•
•

Multitasking
Presentation Manager
MS-DOS 4.01 compatibility
Intel386 architecture support
Dynamic data exchange
Extensive Microsoft documentation
16 MB addressability
Intel-supplied devic.e drivers
LAN Manager support (user-supplied)
Standard Applications Interface
Increased disk performance
Online Help facility

MS OS/2 CAPABILITIES
Capability

MS OS/2 1.1 MS·DOS
4.01

Multitasking
Multiuser
Application size
Existing MS-DOS apps.
Shared files
Presentation Manager
16MB addressability
EMS 4.0 support

Yes
No
Virtual
Yes
Yes
Yes
Yes
Not req.

MS OS/2 provides access to the full range of features
of the programming environment. Users have the
option of developing applications or device drivers
under Intel's adaptation of MS OS/2. Users desiring
this feature are encouraged to purchase the Microsoft
Software Development Kit (SDK) or Microsoft Device
Driver Development Kit (DDDK). Both are available
through Microsoft Corporation.

15-17

No
No
640 Kbyte
Yes
Within appls.
No (Shell)
No
Yes

MICROSOFT MS-DOS® OPERATING SYSTEM
VISUAL SHELL
INTERFACE
INCLUDED

of memory. The expanded memory support is fully
compatible with Intel's family of 386 MicroComputer
platforms.

The Microsoft MS-DOS
4.01 Operating System is
an updated version of
Microsoft MS-DOS 3.3
that supports larger disk
files/partitions, expanded
memory support for 386
systems and features an optional file directory
manage'r. MS-DOS 4.01 is fully compatible with MSDOS 3.3 and allows the user to migrate to a visual
shell environment that is compatible with the look and
feel of Microsoft Windowsl386 and MS OS/2
Presentation Manager.
MS-DOS 4.01 includes support for hard disk files
greater than 32MB, so the user is not required to
divide large hard disk drives into smaller partitions.
The new file management scheme increases
performance over that of MS-DOS 3.3. The maximum
amount of hard disk storage supported under MSDOS 4.01 is 2 Gbytes.
MS-DOS 4.01 emulates the expanded memory
specification (EMS 4.0) developed by Lotus, Intel,
Microsoft and AST Research, supporting up to 40 MB

The visual shell interface allows MS-DOS 4.01 to
experience the "look and feel" of the MS Windowsl386
and MS OS/2 interfaces. Under MS-DOS 4.01 the user
has the option of replacing the shell interface with MS
Windowsl386 (user-supplied) or the standard MS-DOS
command prompt.
The MS-DOS 4.01 package contains all the necessary
utilities and documentation to allow you to configure
MS-DOS 4.01 on the Intel386 MicroComputer family of
products. MS-DOS supports:
•
•
•
•
•
•
•
•
•
•

Hard disk support to 2 Gbytes
New system commands
File caching
GW-BASIC
Extended Memory Support to 40MB
Complete Microsoft documentation
Intel-supplied device drivers
MS-DOS 4.01 visual shell
Enhanced utilities (FORMAT, GRAPHICS etc.) .
User installation/configuration utility .

DIAGSOFT QAPLUS® SYSTEM DIAGNOSTICS
SYSTEM-LEVEL
PERFORMANCE
ANALYSIS

The QAPLUS diagnostic system also allows users to
perform all standard IBM PC/AT system-level tests.

The DiagSoft Quality
Assurance Advance
Diagnostics System
(QAPLUS) provides a
complete diagnostic
capability to assure the
proper operation of
Intel386 MicroComputer products. It contains a
complete diagnostic capability that tests the CP,:!
functionality and performs overall system analysIs. It
also allows you to isolate memory system faults to the
component level.
The QAPLUS diagnostics system provides a complete
performance analysis panel which reports on a. .
system's operation. The performance cha~actenstlcs of
the system are continuously computed uSing
dhrystone and whetstone benchmarking techniques.
The QAPLUS diagnostic system also allows users to
perform all standard,lBM PC/AT system-level tests.

15-18

QAPLUS contains an exhaustive RAM test, hard disk
analysis and a pre-formatting capability. With QAPLUS,
the user will be able to identify any service problems
and correct most common faults before initiating a
service call.
.
The QAPLUS package includes the diagnostic
program and user manual and is designed to run
under MS-DOS on Intel's 386 MicroComputer family of
products. The QAPLUS diagnostic system supports
the following features:
•
•
•
•
•
•
•
•

System Performance Panel
Complete video analysis
System configuration analysis
Logging capability
Complete RAM analysis
Hard disk low-level formatting
Multiple test capability
Extensive system tests

SPECIFICATIONS
SUPPORTED HARDWARE
Intel fully supports MS OS/2 Release 1.1, MS-DOS 4.01
and Diagsoft diagnostics on the Intel386 MicroComputer product family. All Intel's software products
are available in both 3.5" and 5.25" diskette media.
The Intel386 MicroComputer supported products are:
• Intel386 MicroComputer Model 301
• Intel386 MicroComputer Model301Z
• Intel386 MicroComputer Model 302

SERVICE/SUPPORTflRAINING
Intel provides OEMs with complete technical support
through the OEM Platforms Product Assistance
Network (iPAN) and the OEM Platforms Phone Action
Line Support (iPALS). OEM access to the iPAN and
iPALS support systems require a signed OEMlicense.
For time and performance critical development
projects, Intel offers MS OS/2 jointly with the Microsoft
University program. The training courses include MS
OS/2 system development kit (SDK) and the device
driver development kit (DDDK). Intel also has a staff of
factory trained software engineers which can be
contracted by the hour or over several months as part
of your project team. Call your local Intel sales office
for course information or software engineering
services.

ORDERING INFORMATION
Intel's MS OS/2 Release 1.1, MS-DOS 4.01 and
Diagsoft diagnostic software may be ordered with any
Intel386 MicroComputer platform. The system software
products are available in two forms: as a sample~ and
in bulk. Each bulk unit contains five single-user copies.
All bulk units require a license for purchase.
OEM LICENSE

Each single user copy is shrink wrapped
and contains MS OS/2 user manuals and
diskettes. MSOS2F requires a signed
license for purchase.
3.5" diskette media

MDOS2M MS-DOS release 4.01 in 3.5" diskette
media (720 KB format). Each MSDOSM
contains five single user copies of MSDOS release 4.01. Each single user copy
is shrink wrapped and contains MS-DOS
user manuals and diskettes. MSDOSM
requires a signed license for purchase.
MSOS2M

5.25" and 3.5" diskette media
DIAGSOFT Diagsoft diagnostic software on 3.5"
diskette media (720 KB format) and
5.25" diskette media (360 KB format).
Each DIAGSOFT contains five single user
copies of Diagsoft diagnostics. Each
single user copy is shrink wrapped and
contains DIAGSOFT user manuals and
diskettes. DIAGSOFT requires a signed
license for purchase.

OEM software distribution and
support agreement. Each license
provides for a site purchasing
agreement for software products,
and a single user access to iPAN
and iPALS.

OEMSAMPLER OEM software sampler package.
Each sampler includes MS-DOS
4.01, MS OS/2 1.1 and Diagsoft
diagnostics. Each package contains
1 copy of documentation, and both
3.5" and 5.25" diskette media. The
sampler does not require a signed
license for purchase.
5.25" diskette media

MSDOSF

MS-DOS release 4.01 on 5.25" diskette
media (360 KB format). Each MSDOSF.
contains five single user copies of MSDOS release 4.01. Each single user copy
is shrink wrapped and contains MS-DOS
user manuals and diskettes. MSDOSF
requires a signed license for purchase.

MSOS2F

MS OS/2 release 1.1 on 5.25" diskette
media (1.2 MB format). Each MSOS2F
contains five single user copies of MS
OS/2 release 1.1.

MS OS/2 release 1.1 on 3.5" diskette
media (1.44 MB format). Each MSOS2M
contains five single user copies of MS
OS/2 release 1.1. Each single user copy is
shrink wrapped and contains MS OS/2
user manuals and diskettes. MSOS2M
requires a signed license for purchase.

15-19

INTEL OEM SUPPORT

COMPLETE PRODUCT SUPPORT FOR FAST TIME TO MARKET
Intel's OEM support program provides Original Equipment Manufactures with all the
assistance they need to get their Inte1386'" MicroComputer products to market quickly.
Program components include an electronic bulletin board open 22 hours a day, six days a
week. Telephone assistance during normal business hours. Complete documentation in a
choice of formats, from electronic text to printed manuals. And, monthly product updates.
All designed to help you be successful, forJast time to market.

STANDARD FEATURES:
• Electronic access to Intel's OEM
Platforms engineering database
• Electronic bulletin board problem
resolution (open 22 hours a day, six days
a week)
• Electronic access to Intel's product
update bulletins (iPUB)
• Monthly subscription service to Intel's
product update bulletin (iPUB)
• Phone action line support (iPALS) during
normal business hours
• Product documentation in OEM·
requested format

intJ---------@

September; 1988
Order Number: 280954-001

Intel Corporation 1989

15-20

INTEL PRODUCT
ASSISTANCE NETWORK
(iPAN)
•
•
•
•

enhance the documentation to better reflect the OEM's
unique product line. Finally, printed manuals in bulk
quanities provides finished documentation that the
OEM can pass onto their customers immediately. Intel
OEM documentation is available to all Intel386
MicroComputer OEMs.

• On-line problem resolution, with
guaranteed response.
Electronic access to engineering database
Electronic access to Intel's Product Update Bulletins
Worldwide access through direct-dial or
COMPUSERVE
Access speeds up to 2400 baud

~
ill

The Intel Product Assistance Network (iPAN) is an
electronic information retrieval service that allows
OEMs to review our on-line product database, enter
questions, and tap into Intel's Product Update Bulletin
service. Questions are responded to within 24 hours.
The database also includes tips on workarounds and
product technical information.

•
•
•
•
•

iPUB is distributed electronically through iPAN and via
monthly mailings. Every OEM subscriber receives an
OEM binder and a one-year subscription to the
service. The iPUB notebook constitutes a
comprehensive resource for OEMs integrating Intel386
MicroComputer products.

INTEL PHONE ACTION LINE

dd SUPPORT (iPALS)
dii.Jd · Telephone assistance to Intel's

technical support
• 24-hour turnaround on questions Monday-Friday
• Expert assistance on Intel386 MicroComputer
products with the needs of OEMs in mind

SUPPORTED HARDWARE AND SOFTWARE

The Intel Phone Action Line Support (iPALS) is an
8-hour-a-day, five-day-a-week telephone action line for
OEMs of Inte1386T11 MicroComputer products. iPALS
personnel are trained to answer both technical and
business questions about Intel's product offerings, and
are committed to having a response to you within 24
hours. iPALS is available to any OEM that has signed a
license.

INTEL OEM
DOCUMENTATION
• Complete Intel386 MicroComputer
product documentation
• Choice of formats: camera-ready artwork, electronic
(ASCII) text, and printed user's gUides

• Monthly product updates
• Intel386 MicroComputer product
histories
Intel386 MicroComputer BIOS histories
Software available from Intel
Documentation updates
Hardware and software compatibility information
Spare parts order information

The Intel Product Update Bulletin (iPUB) is a monthly
subscription service that serves as official notification to
OEMs of engineering changes and technical
information on the Intel386 MicroComputer product
family. Information contained in iPUB includes board
and system product histories, software and hardware
compatibility information and spare parts order
information.

The iPAN database is available to any OEM that
purchases a license for Intel386TH MicroComputer
products. iPAN can be accessed using a 300, 1200 or
2400-baud modem and any standard terminal
communications software. All license holders receive a
complimentary COMPUSERVE introduction kit, iPAN
user's manual, and an iPAN user access code.
(COMPUSERVE connection time is the responsibility of
the OEM.)

INTEL PRODUCT UPDATE
BULLETIN (iPUB)

The Intel OEM support program is offered to any OEM
purchasing any of Intel's MicroComputer products:
• Intel386 MicroComputer Model 301
• Intel386 MicroComputer386 Model301Z
• Intel386 MicroComputer386 Model 302
• Intel386 MicroComputer baseboard products
• Software products (MS-DOS 4.01, MS OS/21.1,
DIAGSOFT diagnostics)

ORDERING INFORMATION
Service
iPAN
iPALS
iPUB

Description
Product Assistance Network
Phone Action Line Support
Intel Product Update
Bulletin
OEMOOC Intel386 MicroComputer

Intel provides OEMs with complete product
documentation, so their customers can become
productive on Intel products. Intel OEM documentation
is available in three convenient formats: camera-ready
artwork, electronic (ASCII) text, and printed manuals.
Camera-ready artwork lets you customize the
documentation by adding your own company logo.
Electronic format provides the freedom to alter or
15-21

Order Code
OEM LICENSE
OEM LICENSE
IPUB

386AT25QOC
386AITOOC
301Z00C
302DOC

VALUE-ADDED DISTRIBUTION

CUSTOMIZED PRODUCTS AND SERVICES FROM INTEL AND ITS
VALUE-ADDED DISTRIBUTORS
Intel's Value-Added Distribution program is designed to provide complete solutions for
companies requiring custom system configurations. From Intel you get leading-edge
technology, training and comprehensive product service. From Intel Value-Added
Distributors (VADs) you get engineering expertise, flexible manufacturing capabilities, and
customized solutions. Whether you need special systems software, personalized
packaging, integration of third-party components, precise delivery, or any number of
unique reguirements, Intel and its VAD partners can help you be successful.

COMPETITIVE ADVANTAGES
• Custom solutions based on Intel
technology
• Certified Value-Added Distribution
Centers staffed with design and
manufacturing experts
• Application Technical Specialists to help
tune designs

• Third-party hardware and software
selection assistance
• Project management expertise
• Integration design, testing and evaluation
• Custom inventory control, shipping,
service arrangements

INTEL TECHNOLOGY: THE BEST PLACE TO START
Intel advanced technology is the perfect foundation for building flexible, powerful, costeffective OEM systems products. But many companies need to create a customized .
solution for their customers. Working together with its Value-Added Distributors, Intel can
provide total turnkey solutions .

.intel°---------Apnl.1988
Order Number 280979-001

15-22

PRODUCT DESIGN SUPPORT
Design and integration support can begin as early as you want. Our nationwide network of sales offices and
technical support centers are staffed with Intel-certified Application Technical Specialists who are experts on Intel
architectures and on integrating Intel products into custom configurations. Your Application Technical Specialist
can work with you to evaluate your needs, make suggestions that will save you money, improve the quality of
your product and accelerate your production time to market.
If your design solution requires third-party add-in boards, peripherals or software, our VADs can help with
supplier qualification. They have established relationships with hundreds of suppliers and can quickly match your
needs with pre-qualified companies that conform to your quality standards. They can also test for your unique
peripheral requirements.
Project management assistance is also available. Our VADs can take on the coordination of your entire product
and provide drop-shipment to your customer's site. You make all the final decisions; they take care of the day-today details.
In short, your VAD Center representative or branch office sales person will sit down with you, listen to and
understand your needs, then work with you at whatever level you desire to come up with a creative, cost-effective
solution.

PRODUCTION AND MANUFACTURING EXCELLENCE
Together, Intel VADs have invested millions of dollars in state-of-the-art integration facilities and trained personnel.
These facilities are there to quickly help you turn your product ideas into a reality.
Intel's certificaiion program ensures that all our VADs conform to Intel's rigorous quality and reliability standards.
They employ the latest manufacturing and process control techniques to ensure top quality and a smooth
production flow. Their manufacturing facilities can adapt to your changing needs and can ramp up or cut back
production as your markets dictate.
They can also perform testing and certification to make sure your products operate safely and within prescribed
legal parameters. Custom diagnostics can also be generated by your VAD to assure proper performance levels
at your customers installation.

CUSTOM HARDWARE
Intel, through its VADs, can provide both board and system-level customization, including Inte1386'·
MicroComputer and MULTIBUS® board integration; custom motherboards and backplanes, iSBC® single-board
computer test and burn-in, integration of third-party peripherals, multiple processor design, even custom logos,
keycaps and chassis. You'll have the assurance that all the components are compatible, fully tested, and that
each system will perform as expected.

CUSTOM SOFTWARE
Our VADs' wide-ranging expertise in custom software includes iRMX® real-time software reconfiguration, iRMX
and UNIX' drivers, human interface software, communications software, PAL generation, custom diagnostics,
networking, and many other areas. They will make sure software and hardware are tightly integrated and serve
as a single, accountable source for the entire system.
And, of course, they can also supply you with off-the-shelf PC application software.

SPECIAL SERVICE OPTIONS
Intel's VADs will not only help you produce the highest quality product possible at the lowest possible cost; we
can also help with shipping, inventory management and other post-production matters. Many of our VADs will
warehouse finished product for you and deliver on demand-or, ship directly to your end user and install the
product in any corner of the world. That kind of flexibility saves you expensive, redundant shipping costs and
gets your product to its final destination much sooner.
For our OEM customers, we can also accommodate Just-In-Time delivery programs, service your end users
directly, set up leasing programs, and provide configuration consulting. And of course, Intel can provide you with
technical, sales and service support.

LET US BE YOUR SYSTEMS INTEGRATION PARTNER
If your success depends on suppliers who can provide complete solutions, call your local Intel sales office or
Intel distributor'today, and let us tell you more about our Value-Added Distributor program. Building on leadingedge Intel technology, our VADs can craft a custom solution for you that's just right for your unique needs.

15-23

ALMAC ELECTRONICS

MESA TECHNOLOGY

14360 S.E. Eastgate Way
Bellevue. Washington 98007
Carl Gulledge/Mark Thorstelnson
(206) 643-9992
The VAD facility is composed of a 12.000 square foot
production floor and engineering lab. Almac is well equipped
for medium to high run rate production and engineering
custom solutions. An excellent pre-sales support program has
been implemented. Specific expertise includes: systems
design. Integration. networks. third party peripherals. and
custom enclosures.

9720 Patuxent Woods Dr.
Columbia. Maryland 21046
Johnny Johnson
(301) 290-8150
SpeCialists in all types of OEM Industrial Integration.
Experience includes multiprocessing systems with heavy
emphasis on real-time embedded rackmount systems_ Inhouse MULTI BUS board design capability and system level
software. especially I/O drivers. wtth 9 years experience in
iRMX'" development.
Recognized experts in TEMPEST system integration and
government contracts. Design. manufacture and market their
own TEMPEST system products based on AT-bus (301/21).
MULTI BUS I (321 1. 3251) and MULTIBUS II (5211).

ARROWIKIERULFF ELECTRONICS
7524 Standish Place
5230 W 73rd St.
Rockville. Maryland 20855
Edina. Minnesota 55435
Keith Talbert/Andy ThomSOn
Chuck Klein
(301) 424-0244
(612) 830-1800
1502 Crocker Avenue
Hayward. California 94544
Scott Robertson
(415) 487-8416
Three facilities. each over 15.000 square feet. staffed by
engineers. engineering technicians. production technicians.
and buyers.
Highly qualified. dedicated Regional Sales people. ATS·s. and
Computer Products Specialists trained (and incentivized) to
close VAD business. Prefer requirements for complete project
management. Specific expertise Includes system design and
integration. board configuration and testing. cosmetic
modification. MULTI BUS custom enclosures. 386AT
development. custom configuration and integration.

HAMILTON·AVNET
10950 W Washington Blvd.
Culver City. California 90230
Lynn Johnson
(213) 558-7040

3688 Nashua Drive
Mississauga. Ontario
Canada L4V lM5
Darryl Armour
(416) 677-0690
10 F Centennial Drive
Peabody, Mass. 01960
Neal Malatzky
(508) 532-9609
Three VAD centers-LA. Boston. Toronto-65 specialists with
the ability to perform a full range of software and hardware
enhancement services. Strict ESD control procedures are
adhered to. Specific expertise Includes board modification and
test. system deSign and Integration. Full documentation is
available on all systems. Specialties Include real lime'
embedded systems. multlvendor networks. development
systems. peripheral integration and Industrial floor enclosures.
Complete implementation of quality procedures.

PIONEER STANDARD
4800 E. 131st St.
60 Crossroads Park West
Cleveland. Ohio 44105
Woodbury. New York 11797
Joe Betro/Mike Thompson
Dave Nash
(216) 587-3600
(516) 921-8700
A 60 personnel. 50.000 square foot new VAD center in
Cleveland. Dedicated VAD staff of adminstrators. senior buyers.
engineers. technicians. a.c. and sales. EXperts in systems
Integration. just-in-tlme project management and turnkey
solutions. Load operating systems and application packages.
,
option boards. peripherals. Analyzes and tests solutions.

'XENIX is a trademark of Microsoft
UNIX is a trademark of AT&T

MTISYSTEMS
38 Harbor Park Dr.
Port Washington. New York 11050
Tom Donofrlo/J.P' Altier
(516) 621-6200
Highly integrated. complex applications VAD. Expert iRMX.
UNIX. DOS application experience. In-house board design
capability. Rackmount and custom hardware. system
modification experience. Custom software expertise. UNIX
packages. X-windows. iRMX drivers. Complete networking
abilities. 301/302 models with multiple EGAs.

PIONEER TECHNOLOGIES
9100 Gaither Rd.
Gaithersburg. Maryland 20877
Mike EdlsonlTlm Olson
(301) 921-0660
A full service 20.000 square foot technical application center
offering project management from inception through proposal.
engineering. testing. and production/manufacturing. Pioneer's
technical staff brings about 20 years of experience with
microprocessor hardware. software. and system design and
integration. Pioneer offers complete system solutions. including
networking (supporting multiserver and remote boot). board
and system level (MBI or MBII). operating systems (iRMX.
XENIX·. DOS). custom software (diagnostics to drivers).
peripheral subsystems. mechanical redesign. 386 platforms
(model 301. 302) with iRMX. XENIXIUNIX·. or DOS. and
inventory control. kitting. and manufacturing.

WYLE LABORATORIES
7382 Lampson Avenue
Garden Grove. California 92641
Dave Hamilton
(714) 891-1717
A showcase VAD Center. Expanded to 12.000 square feet.
increased headcount to 14 people. Capable of proceSSing over
700 systems per month. Excellent at total configuration of
systems. Prefer system integration. peripheral enhancement.
test and system run-in. Experience in Intel iSBC board run rate
modifications.

ZENTRONICS
8 Tilbury Court
Brampton. Ontario
Canada L6T 3T4
Paul Malhi
(416) 451-9600
Newest Canadian VAD. A national distributor with a VAD Center
prOViding all types of systems interpretation. Prefer iRMX and
AT-bus. Inventory drives, controllers. monttors. etc. to provide
complete customer solution. In-house technical (800) hot·line
for customer assistance.

15-24

Local Area Network
Boards and Software

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OPENNETTM LOCAL AREA NETWORK FAMILY

iRMX® -NET

PCLlNK2

VMSNET

iRMX SYSTEMS

MS-DOS

VAXNMS·

OJL

~
1

SV-OpenNET'M

XNXNET

iNDX OpenNET

UNIX· SYSTEM V

XENIX· SYSTEMS

NRM SYSTEMS

OPENNEpM: THE COMPLETE OPEN NETWORK SOLUTION
The OpenNET family provides the OEM with complete Open Network solutions for an
enterprise-wide, multi-vendor network based on international standards.

FEATURES:
• Interoperability between the factory, office, and engineering environments
• Complete hardware and software network solutions
• On-going customer support through extensive training and application development

GUIDE TO THE OPENNETTM PRODUCTS

in1:el"---------C

Intel Corporation 1989

16-1

September, 1989
Order Number 280669·002

OpenNETTM OVERVIEW
OpenNETTM MEANS OPEN NETWORKS

Users are placing increasing demands for data
communications capabilities on their computing
applications. The OpenNET family of networking
products supplies those capabilities to let OEMs offer
solutions to communications-intensive requirements,
based on Intel's real-time computing products.

• Open to expansion
• Open to different hardware
-MULTIBUS®I
-MULTIBUS®II
- PC XT/AT Bus
• Open to different environments
'-Factory
-Office
-Lab
. - Engineering Workstation

• Open to multiple media
-IEEE 802.3/Ethernet
- Thin-wire Ethernet
-IEEE 802.4

-X.25

• Open to multi-vendor solutions

• Open to different Operating Systems
-iRMX
-MS-DOS'
-PC-DOS
-UNIX SYSTEM V'
-VAXIVMS'
-XENIX'
-INDX

• Open to future upgrades

16-2

OpenNETTM OVERVIEW
OpenNETTM ARCHITECTURE
Intel's OpenNET communications architecture applies
networking standards to offer an open network. Open
connectivity lets MULTIBUS-based systems talk to
systems such as IBM PCs and VAX minicomputers.

OpenNETT>1 DELIVERS INTERNATIONAL
STANDARDS
The OpenNET products use ISO and CCITT Data
Communications Standards tor the Physical, Data
Link, Network, and Transport layers of the Open
System Interconnection (OSI) model. The Session,
Presentation, and Application layers use the Server
Message Block (SMB) protocol promulgated by Intel,
Microsoft, and IBM. The 5MB protocol IS used by
Microsoft and IBM in their PC networks.

5MB: TRUE TRANSPARENT REMOTE FILE
ACCESS
The OpenNET Server Message Block protocol allows
applications to access remote files as If they were
local. ThiS consistent view of the file system .
throughout the network allows distributed processing
of existing applications Without change. The 5MB
protocol protects the user's data with file security
established by either the consumer or server system.

OpenNETTM WILL FOLLOW THE
STANDARDS, TRANSPARENTLY

The Boot Server system responds.to network boot
requests from diskless Boot Consumer systems and
downloads both the appropriate operating system
and communications software over the network to
boot the diskless system. With the diskless system
booted, the File Server system prOVides the diskless
system with network access to mass storage deVices.
The Boot Server and File Server can reside in
separate systems or in the same,system on the
network.

OpenNETT>1 VIRTUAL TERMINAL
CAPABILITY
The OpenNET product family supports a Virtual
Terminal (VT) capability. ThiS feature allows a terminal
or PC user to "login", over the network, as an
Interactive user under the remote nodes operating
system. VT is purchased separately as an optional
application program.

ALL OpenNETTM PRODUCTS BACKED BY
INTEL CUSTOMER SUPPORT
All Intel software products Include Intels Software
Support for a 90 day period Immediately following the
licenSing and receipt of the product.

STANDARD SOFTWARE SUPPORT
INCLUDES:
• Product updates

As the OSI standards evolve, Intel Will conform to
them. The user's application Will be protected from
the changing protocols because the OpenNET
Interface ('", \" on DOS or "/ /' on XENIX and UNIX)
will NOT change. This will allow applications to move
to the OSI standards With little or no modification. The
OpenNET products will allow the user to run all
current applications that use the OpenNET Interface
on either the 5MB or the OSI protocols.

• Membership in Inslte'M User Program Library

OpenNETT>1 SUPPORT FOR DISKLESS
WORKSTATION

ADDITIONAL SERVICES AVAILABLE
INCLUDE:

For certain real-time applications, it IS desirable that a
networked system not have a local mass storage
deVice such as a hard disk. One example IS harsh
environments such as factory floor process control,
where rotating media can cause system reliability
problems. Another example is financial workstallons,
where stock and market information must be updated
in real-time on a centralized file server and accessed
by diskless trader workstations.
.

• Consulting services on a long or short-term baSIS
(Systems Engineering Support)

• SubSCription Ser.vlce and technical product
information distributed via:
- Monthly issue of ;Comments newsletter
-Quarterly Troubleshooting Guides
-Software Problem Report (SPR) Service
• Technical Information Phone Service (ITIPSTM) tollfree hot line

• Worldwide training workshops on a wide variety of
Intel products
• A full range of hardware maintenance services for
end users or OEMNAR customers

16-3

iRMX®·NET OpenNETTM NETWORKING SOFTWARE

iRMX® AT·BUS
SYSTEM 120

iRMX\!J
MULTIBUS\!J I
SYSTEM 320

iRMX®
MULTIBUS® II
SYSTEM 520

-intal

1111111111111111

MULTIBUS\!J I

AT·BUS

COMPLETE OpenNETTlf SOLUTION FOR
REAL·TlME SYSTEMS '

MULTIBUS® II

TRANSPARENT NETWORK FILE ACCESS

Real-Time computer systems require a real-time
operating system. The iRMX operating system from
Intel is the worlds most popular operating system for
real-time systems.
Many real-time applications require network
communication. Intels iRMX®'NET Release 3.0
delivers a rich set of networking capabilities and a full
range of iRMX platform support:
• Transparent Network File Access
• Transport and Distributed Name Server Software
with Programmatic Access
• iRMX System 120 (AT-bus), 320 (MULTIBUS I) and
520 (MULTIBUS II) Connections
• Remote Boot for Diskless Systems
Networked iRMX systems serve in a wide range of
real-time application areas including data acquisition,
factory automation, financial workstations, military,
medical instrumentation, simulation and process
control.

16-4

iRMX-NET implements the NFA protocol to provide
transparent file access capabilities among iRMX,
DOS, VAXNMS, UNIX, XENIX and iNDX systems on
the OpenNET network. Remote files are accessed as
if they resided on the local iRMX system. iRMX-NET
can be configured as a network file consumer, file
server, or both, depending on the applications
requirements.
The iRMX operating system provides a rich set of
human interface commands and system calls for
accessing local files. With the addition of iRMX-NET.
these commands and system calls are transparently
extended to remote access as well. Transparency
means that applications using the iRMX Human
Interface commands or BIOS system calls do not
need to know whether the files they access reside
locally or on some remote system.

iRMX®·NET OpenNETTM NETWORKING SOFTWARE
OSI TRANSPORT AND DISTRIBUTED
NAME SERVER WITH PROGRAMMATIC
INTERFACE

REMOTE BOOT FOR DISKLESS SYSTEMS
iRMX-NET R3.0 supports networked diskless systems
by providing network Boot Consumer, Boot Server
and File Server capabilities.

The iRMX-NET R3.0 product includes iNA 960 R3
OSI Transport and Network software preconfigured
for a variety of Intel Network Interface Adapters.

IRMX~ II
MULTIBUS~

DOS
AT-BUS

Diskless System

Diskless PC

iRMX-NET R3.0 also includes the iRMX-NET
Distributed Name Server software. The Distributed
Name Server software maintains and provides access
to a network directory database. The database is
distributed across the network with each system
maintaining its own logical piece of the directory. The
Distributed Name Server software provides a full set
of network directory services and is used to perform
such tasks as logical name to network address
mapping for establishing network connections
between systems. .
The combi,natlon of transparent network file access
with iRMX commands and system calls, plus direct
programmatic access to the iNA 960 Transport and
iRMX-NET Distributed Name Server software gives
the programmer a powerful set of capabilities for
developing real-time network applications.

PRODUCT CODES

iRMX®SYSTEM 120, 320 AND 520
CONNECTIONS
iRMX-NET R3.0 provides networking support for the
full range of Intel real-time Systems, from the low-cost
AT-Bus System 120, through the MULTI BUS I System
320, to the high-end multiprocessing MULTIBUS /I
System 520. iRMX-NET R3.0 also supports iRMX
board-level designs built around Intel's family of host
CPU boards and Network Interface Adapters.
Consistent operating system and networking software
interfaces provide for easy development of network
applications that span the various iRMX platforms.

RMXINETSW

iRMX-NET Networking Software
for the iRMX 86 operating system.

RMXIINETSW

iRMX-NET Networking Software
for the iRMX /I operating system.

sSXM120NETKIT

Preconfigured iRMX-NET and
sPCLlNK2 for networking iRMX
and DOS on the System 120.

REAL-TIME BOARD AND SYSTEM LEVEL SUPPORT
iRMX\!l 86

SYSTEM

HOST
BOARD

NETWORK
INTERFACE
ADAPTER

iRMX SYSTEM BUS
280207-2

iSBC® 186/51 Block Diagram

SPECIFICATIONS

Memory CapacitylAddressing

Word Size

Six Universal MemorY Sites support JEDEC 24/28
pin EPROM, PROM, iRAM and static RAM.

Instruction: 8, 16, 24, or 32 bits
Data: 8, 16 bits

Example for EPROM:
Total Capacity
Device

System Clock

2732
2764
27128
27256

6.00 MHz ± 0.1%
Cycle Time

24K Bytes
48K Bytes
96K Bytes
192K Bytes

On-Board RAM
Board
Total Capacity

Basic Instruction Cycle
6 MHz- 1000 ns

iSBC 186/51

333 ns (assumes instruction in the queue)

NOTE:
Basic instruction cycle is defined as the fastest in·
struction time (i.e., two clock cycles).

128K Bytes

With MULTIMODULETM RAM
Board
Total Capacity

16·22

iSBC304

256K Bytes

Address Range
F8000-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH
COOOO-FFFFFH

Address Range
0-1FFFFH

Address Range
0-3FFFFH

intJ

iSBC® 186/51

I/O Capacity

Timers

Serial two programmable channels using one 8274.

Input Frequencies

SBX Bus two 8/16-bit SBX bus connectors allow
use of up to 2 single-wide modules or 1 single-wide
module and 1 double-wide SBX module.

Reference 1.5 MHz ± 0.1 % (0.5 JLs period nominal)
Event Rate: 1.5 MHz max.

Serial Communications Characteristics

Interfaces

Synchronous -

5-8 bit characters; internal or external character synchronization;
automatic sync insertion

Ethernet -IEEE 802.3 compatible
MULTIBUS® -IEEE 796 compatible

Asynchronous -

5-8 bit characters; break character after generation; 1, %, or 2
stop bits; false start bit detection

MULTIBUS® - Master D16 M24 116 VO EL

Compliance
iSBXTM Bus -IEEE P959 compatible

Baud Rates
Frequency
(KHz) (S/W
Selectable)

Serial I/O -RS-232C compatible, configurable as a
data set or data terminal,

Baud Rate (Hz)
Synchronous
+1

RS-422A1RS-449

Asynchronous
+16

+64

Physical Characteristics
Width: 12.00 in. (30.48 cm)

153.6

9600

2400

76.8

4800

1200

38.4

38,400

2400

600

19.2

19,200

1200

300

Height: 6.75 in. (17.15 cm)
Depth: 0.70 in. (1.78 cm)
Weight: 18.7 ounces (531 g.)

9.6

9,600

600

150

Environmental Characteristics

4.8

4,800

300

Operating Temperature: O°C to 55°C

2.4

2,400

150

1.76

1,760

110

Relative Humidity:

10% to 90% (without condensation)

2400

NOTE:
Frequency selected by I/O write of appropriate 16-bit frequency factor to baud rate register (80186 timer 0 and
80130 baud timer).

80186 Output Frequencies/Timing Intervals
Function
Real-Time Interrupt
Programmable One-Shot

Single
Timer/Counter

Dual (Cascaded)
Timer/Counter

Min

Max

Min

Max

667 ns

43.69 ms

667 ns

47.72 Minutes

1000 ns

43.69 ms

1000 ns

47.72 Minutes

Rate Generator

22.889 Hz

1.5 MHz

0.0003492 Hz

1.5 MHz

Square-Wave Rate Generator

22.889 Hz

1.5 MHz

0.0003492 Hz

1.5 MHz

1000 ns

43.69ms

1000 ns

47.72 Minutes

Software Triggered Strobe
Event Counter

1.5 MHz

16-23

intJ

iSBC® 186/51

Connectors
Interface

Double-Sided Pins

Centers (In.)

Ethernet

0.1

AMP87531-5

Serial 110

0.1

3M 3452-0001
Flat or
AMP88106-1 Flat

MaUng Connectors

Electrical Characteristics
D.C. Po~er Supply Requirements
Maximum Current
(All Voltages ± 5%)

Configuration

+12

-12

SBC 186/51 as shipped:
Board Total
With separate battery back-up
Battery back-up

7.45A
6.30A
U5A

40 rnA
40 rnA

With SBC-304 Memory Module
Installed:
Board Total
With separate battery back-up
Battery back-up

7.55A
6.30A
1.25A

40 rnA
40 rnA

NOTES:
1. Add 150 mA to 5V current for each device installed in the 6 available Universal Memory Sites.
2. Add 500 mA to 12V current if Ethernet transceiver is connected.
3. Add additional currents for any sax modules installed.

Reference Manual

ORDERING INFORMATION

122330-- iSBC 186/51 Hardware Reference Manual (NOT SUPPLIED)

Order Code Description
SBC18651

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

16-24

Communicating Computer

Distributed Control Modules

BITBUSTM STARTER KIT

A COMPLETE BITBUS'" NETWORK
YOU CAN HAVE UP AND RUNNING IN TWO HOURS
The BITBUS'" Starter Kit IS a complete hardware/software kit containing BITBUS analog
and digital boards, tailored application software, and all the accessories (e.g., power
supply and cables) required to set up a simple but functional BITBUS network. A first-time
user can construct a BITBUS network and execute sample application programs within
two hours of opening the box. He can then Incorporate this basIc network Into his own
distributed control application.

FEATURES:
o Self·contained BITBUS kit requiring only

an IBM PC or compatible host.
• BITBUS analog and digital boards, plus
PC Gateway to the BITBUS network
• Sample application software with built-in
installation, configuration, and
diagnostic software.
• No BITBUS experience necessary.

i~'
C

____________________
Intel CorporalLon 1989

17-1

September, 1989
Order Number 280638-001

SPECIFICATIONS
REAL-TIME INTERCONNECT FOR
DISTRIBUTED CONTROL

BUILT-IN INSTALLATION AND
DIAGNOSTIC SOFTWARE

The Intel BITBUS network provides the optimal
solution for building real-time distributed control
systems. The BITBUS serial bus architecture
overcomes many of the limitations inherent in
traditional industrial connection methods to give you
increased performance, reliability, and flexibility and
lower implementation costs.

Application software included with the BITBUS
Starter Kit provides network setup information, as well
as comprehensive error-checking software to verify
that the network is configured correctly. If there is an
error, the software directs you to the problem and
suggests a correction. Once the network is working
properly, the software steps you through optional
configurations, from a host-based centralized control
system to a node-based distributed control scheme.
Each configuration allows you to interact With the
network.

DESIGNED FOR FIRST-TIME BITBUS
USERS
The BITBUS Starter Kit is the ideal way for first-time
BITBUS users to learn about the BITBUS
architecture. Shortly after unpacking this kit, you can
be confidently executing your first BITBUS distributed
control application.

EVERYTHING YOU NEED
Based on standard Intel products, the BITBUS Starter
Kit includes the BITBUS analog board, the BITBUS
digital board, the PC Gateway into the BITBUS
network, power supply and cables. Supporting the
standard product are demonstration boards that the
user can manipulate to display analog or digital
functionality. .

17-2

SERVICE, SUPPORT AND TRAINING
Intel provides worldwide support for repair, on-site
service, netwolk design, and installation.
Development support options include phone support,
subSCription service, on-site consulting, and customer
training.

INTEL QUALITY AND RELIABILITY
The BITBUS Starter Kit is designed and
manufactured in accordance with Intels high quality
standards. We then verify quality through rigorous
testing in our state-of-the-art Environmental Test
Laboratory.

SPECIFICATIONS

C[]
BM
PC

iRCB 44/10
Digital Board

Analog
Demo Board

iRCB 44/20
Analog Board

Power
Supply

Figure 1: BITBUS Starter Kit

ORDERING INFORMATION
Product Code
BITBUSKIT

Qty

Product Content
Basic Starter Kit which includes the following items:
BITBUS Starter Kit User's Guide
HARDWARE
iPCX 344A-BITBUS IBM PC Interface Board-PC Gateway to
BITBUS Network
iRCB 4410A-BITBUS Digital I/O Remote Controller Board
iRCB 4420A - BITBUS Analog I/O Remote Controller Board
Digital Demonstration Board
Analog Demonstration Board
Power Supply, 25 Watt, UL, VDE, CSA approved
Required Cables, SRAMS, Jumpers, etc.
SOFTWARE
iDCS1 00- BITBUS Toolbox- The set of six software utilities
that simplify development of host application software
iDCS11 0 - Bltware - iDCX 51 interface library and declaration
flies
Starter Kit Application Software

BITBUSKITPLUS

Expanded version of the BITBUSKIT providing programming
languages used to develop host (8086 environment) and node
code (8051 environment) in addition to the basic BITBUS
network.

17-3

SPECIFICATIONS
Table 1. Standard BITBUS'· Interlaces
Interface

Specification

Electrical

RS485

Cable

1O-conductor flat ribbon or 1 to 2 wire shielded twisted pair

Back-plane connector

64-pln Standard DIN

Control-board form-factor

Single-height, Double-depth Eurocard

Data Link control

Synchronous Data-link Control (SDLC)

Data transfer rate

62.5K baud, 375K baud and 500K to 2.4M baud

Message formats

Compatible with IDCX format command/response/status

Common command
sequences

Integral Remote Access and Control (RAC) function

Operating systems

Interface libraries for iRMX 86, 88, 286R, MS-DOS, and ISIS (for iPDS
only)

Table 2. BITBUS'" Microcontrol/er Interconnect Modes Of Operation
Speed
Kb/S

Maximum Distance
Maximum # Repeaters
Between Repeaters Maximum # Nodes Per Between A Master And Any
Segment"
Slave
Mlft

Synchronous

500-2400

30/100

Self Clocked

375
62.5

300/1000
1200/4000

28
28

2
10

RELATED LITERATURE
iPCX 344A fact sheet
(Order #. 280414-002)
iRCB 44/10A fact sheet
(Order #: 280213-003)
iRCB 44/20A fact sheet
(Order #: 280721-2)
BITBUS Software Development Environment fact sheet
(Order #: 280622-001)

17·4

iDCX 51
DISTRIBUTED CONTROL EXECUTIVE
•
•

•

Supports MCS®-51 and RUPITM-44
Familes of 8-Bit Microcontrollers

•

Small-2.2K Bytes

•
•

Reliable
Simple User Interface

Real-Time, Multitasking Executive
- Supports up to 8 Tasks at Four
Priority Levels

•

Dynamic Reconfiguration Capability

Local and Remote Task Communication

•

Compatible with BITBUSTM/Distributed
Control Modules (iDCM) Product Line

The iDCX 51 Executive is compact, easy to use software for development and implementation of applications
using the high performance 8-bit family of 8051 microcontrollers, including the 8051, 8044, and 8052. Like the
8051 family, the iDCX 51 Executive is tuned for real-time control applications requiring manipulation and
scheduling of more than one task, and fast response to external stimuli.
The MCS-51 microcontroller family coupled with iDCX 51 is a natural combination for applications such as data
acquisition and monitoring, process control, robotics, and machine control. The iDCX 51 Executive can significantly reduce applications development time, particularly BITBUS distributed control environments.
The iDCX 51 Executive is available in two forms, either as configurable software on diskette or as preconfigured firmware within the 8044 BEM BITBUS microcontroller.

280176-1

Figure 1. IDCX 51 Distributed Control Executive
·XENIXTM is a trademark of Microsoft Corporation.

17-5

October 1987
Order Number: 280176-003

inter

iDCX 51

MICROCONTROLLER SUPPORT
The iDCX 51 Executive is designed to support the
MCS-51 and RUPI-44 families of 8-bit microcontrollers. MCS-51 microcontrollers that are supported include the 8051 .. 80C51 , 8052, 8031, 8032, and 8751
devices. The RUPI-44 microcontrbllers include the
8044, 8344, and 8744 devices. All of these microcontrollers share a common 8051 core.

ARCHITECTURE
Real-time and Multitasking

events: interrupts, timers, and messages ensuring
the application system always responds to the environment appropriately.

Task Management
A task is a program defined by the user to execute a
particular control function or functions. Multiple programs or tasks may be required to implement a particular function such as "controlling Heater 1". The
iDCX 51 Executive recognizes three different task
states as one of the mechanisms to accomplish
scheduling of up to eight tasks. Figure 2 illustrates
the different task states and their relationship to one
another.

Real-time control applications must be responsive to
the external environment and typically involve the
execution of more than one activity (task or set of
tasks) in response to different external stimuli. Control of an industrial drying process is an example.
This process could require monitoring of multiple
temperatures and humidity; control of fans, heaters,
and motors that must respond accordingly to a variety of inputs. The iDCX 51 Executive fully supports
applications requiring response to stimuli as they occur, i.e., in real-time. This real-time response is supported for multiple tasks often needed to implement
a control application.

The scheduling of tasks is priority based. The user
can prioritize tasks to reflect their relative importance within the overall control scheme. For in, stance, if Heater 1 must go off line prior to Heater 2
then the task associated ,with Heater 1 shutdown
could be assigned a higher priority ensuring the correct shutdown sequence. The RQ WAIT system call
is 'also a scheduling tool. In this example the task
implementing Heater 2 shutdown could include an
instruction to wait for completion of the task that implements Heater 1 shutdown.

Some of the facilities precisely tailored for development and implementation of real-time control application systems provided by the iDCX 51 Executive
are: task management, interrupt handling, message
passing, and when integrated with communications
support, message passing with different microcontrollers. Also, the iDCX 51 Executive is driven by

The iDCX 51 Executive allows for PREEMPTION of
a task that is currently being executed. This means
that if some external event occurs such as a catastrophic failure of Heater 1, a higher priority task associated with the interrupt, message, or timeout resulting from the failure will preempt the running task.
Preemption ensures the emergency will be responded to immediately. This is crucial for real-time control
application systems.

Running Task Executes RQWAIT or RQDELETE
READY

1..._--:::----::::_ _:--_-,-:,-:---:::--:---:--_---11
Event Occurs Assoc. wI Asleep Task wI
Higher Priority Than Running Task.

RUNNING

I
J

Event Occurs Assoc.
w/Asleep Task wI
Lower Priority
Than Running
Task

Event Occurs Assoc. wI Asleep Task wI
Higher Priority Than Running Task
ASLEEP

I
Running Task Executes RQWAIT

Figure 2. Task State Transition Diagram

17-6

280176-2

inter

iDCX 51

Interrupt Handling

REMOTE TASK COMMUNICATION

The iDCX 51 Executive supports five interrupt
sources as shown in Table 1. Four of these interrupt
sources, excluding timer 0, can be assigned to a
task. When one of the interrupts occurs the task associated with it becomes a running task (if it were
the highest priority task in a ready state). In this way,
the iDCX 51 Executive responds to a number of internal and external stimuli including time intervals
designed by the user.

The iDCX 51 Executive system calls can support
communication to tasks on remote controllers. This
feature makes the iDCX 51 Executive ideal for applications using distributed architectures. Providing
communication support saves significant application
development time and allows for more effective use
of this time. Intel's iDCM product line combines
hardware and software to provide this function.
In an iDCM system, communication between nodes
occurs via the BITBUS microcontroller interconnect.
The BITBUS microcontroller interconnect is a high
performance serial control bus specifically intended
for use in applications built on distributed architectures. The iDCX 51 Executive provides BITBUS support.

Table 1. iDCX 51 Interrupt Sources
Interrupt Source

Interrupt Number

External Request 0

OOH

Timer 0

01H

External Request 1

02H

Timer 1

03H

Internal Serial Port 1

04H

BITBUSTM/iDCM COMPATIBLE
A pre-configured version of the iDCX 51 Executive
implements the BITBUS message format and provides all iDCX 51 facilities mentioned previously:
task management, interrupt hanaling, and message
passing. This version of the Executive is supplied in
firmware on the 8044 BEM with the iDCM hardware
products: the iSBXTM 344A BITBUS Controller MULTIMODULETM; the iDCX 344A BITBUS controller
board for the' PC; and the iRCB boards.

Message Passing
The iDCX 51 Executive allows tasks to interface with
one another via a simple message passing facility.
This message passing facility can be extended to
different processors when communications support
is integrated within a BITBUS/iDCM system, for example. This facility provides the user with the ability
to link different functions or tasks. Linkage between
tasks/functions is typically required to support development of complex control applications with multiple sensors (input variables) and drivers (output
variables). For instance, the industrial drying process
might require a dozen temperature inputs, six moisture readings, and control of: three fans, two conveyor motors, a dryer motor, and a pneumatic conveyor. The data gathered from both the temperature
and humidity sensors could be processed. Two
tasks might be required to gather the data and process it. One task could perform a part of the analysis, then include a pointer to the next task to complete the next part of the analysis. The tasks could
continue to move between one another.

Designers who want to use the iDCX executive on
an Intel BITBUS board should purchase either
DCS 110 or DSC120 BITBUS software. Both of these
products include an interface library to iDCX 51 procedures and other development files. It is not necessary to purchase the iDCX 51 Executive.

SIMPLE USER INTERFACE
The iDCX 51 Executive's capabilities are utlilized
through system calls. These interfaces have been
defined for ease of use and simplicity. Table 2 includes a listing of these calls and their functions.
Note that tasks may be created at system initialization or run-time using the CREATE TASK call.
Other Functions such as GET FUNCTION IDS, ALLOCATE/DEALLOCATE BUFFER, and SEND MESSAGE, support communication for distributed architectures.

17-7

iDCX51

Table 2. iDCX 51 System Calls
Description

Call Name

TASK MANAGEMENT CALLS
RO$CREATE$TASK

Create and schedule a new task.

RO$DELETE$TASK

Delete specified task from systelT).

RO$GET$FUNCTION$IDS

Obtain the function IDs of tasks currently in the system.

RO$ALLOCATE

Obtain a message buffer from the system buffer pool.

RO$DEALLOCATE

Return a message buffer to the system buffer pool.

RO$SEND$MESSAGE

Send a message to specified task.

RO$WAIT

Wait for a message event.

MEMORY MANAGEMENT CALLS
RO$GET$MEM

Get available system memory pool memory.

RO$RELEASE$MEM

Release system memory pool memory.

INTERRUPT MANAGEMENT CALLS
RO$DISABLE$INTERRUPT

Temporarily disable an interrupt.

RO$ENABLE$INTERRUPT

Re·enable an interrupt.

RO$WAIT

Wait for an interrupt event.

TIMER MANAGEMENT CALLS
RO$SET$INTERVAL

Establish a time interval.

RO$WAIT

Wait for an interval event.

Another feature that eases application development
is automatic register bank allocation. The Executive
will assign tasks to register banks automatically unless a specific request is made. The iDCX 51 Executive keeps track of the register assignments allowing
the user to concentrate on other activities.

SYSTEM CONFIGURATION

gether, then when the system is initialized, all four
tasks will be put into a READY state. Then, the highest priority task will run.
The DCX 51 user can control several system constants during the configuration process (Table 3).
Most of these constants are fixed, but by including
an Initial Data DeSCriptor (100) in an ITO chain, the
system clock priority, clock time unit, and buffer size
can be modified at run-time.

The user configures an iDCX 51 system simply by
specifying the initial set of task descriptors and configuration values, and linking the system via the
RL 51 Linker and Locator Program with user programs.

This feature is useful for products that use the same
software core, but need minor modification of the
executive to better match the end application. The
initial data descriptor also allows the deSigner, who
is using an 8044 BEM BITBUS Microcontroller, to
modify the preconfigured (on-chip) iDCX 51 Executive.

Each task that will be running under control of the
executive has an Initial Task Description (ITO) that
describes it. The ITO specifies to the executive the
amount of stack space to reserve, the priority level
of the task (1-4), the internal memory register bank
to be associated with the task, the internal or external interrupt associated with the task, and a function
10 (assigned by the user) that uniquely labels the
task. The ITO can also include a pointer to the ITO
for the next task. In this wayan ITO "chain" can be
formeo. For example, if four ITO's are chained to-

Programs may be written in ASM 51 or PUM 51.
Intel's 8051 Software Development Package contains both, ASM 51 and RL 51. Figure 3 shows the
software generation process.

17-8

inter

iDCX51

Table 3. DCX 51 Configuration Constants
Description

Constant Name
RQ CLOCK PRIORITY

The priority level of the system clock.

RQ CLOCK TICK

The number of time cycles in the system clock basic time unit (a "tick").

RQFIRSTITD

The absolute address of the first ITO in the ITO chain.

RQ MEM POOL ADR

The start address of the System Memory Pool (SMP) in Internal Data RAM.

RQ MEM POOL LEN

The length of the SMP.

RQRAMIDD

The absolute RAM address of where iDCX 51 checks for an Initial Data
Descriptor (100) during initialization.

RQ SYS BUF SIZE

The size, in bytes, of each buffer in the system buffer pool.

WRITE
SOURCE CODE

ASSEMBLE/
COMPILE

, L1NK/
LOCATE

LOAD/EXECUTE

AEDIT
INSTALL EMULATOR
IN
ICETt.4 5100 SERIES, MICROCONTROLLER
ICETt.4 44, ICE 51, ..S_IT_E_-,
EMV 44, OR EMV51,
EMULATORS

r-":"!"-----, PROBE

TARGET
BOARD
IUP-200A/201A
WITH
UNIVERSAL PROM .------11-.. MCS® 51/
PROGRAMMER
INSTALL
RUPITt.444
EPROM
MICROIN CODE
CONTROLLER
SITE
INSTALL SRAM
IN CODE SITE

o="nu
D

SOnwARE TOOL
280176-3

NOTE:
·RL 51 is included with ASM51 and PLIM 51; OBJHEX and the BITBUS Monitor are part of the DCS100 BITBUS
Toolbox.

Figure 3. Software Generation Process

17·9

intJ

iDCX 51

cated from any remaining memory. These buffers
form the System Buffer Pool (SBP) that can be used
to create additional stack space or to locate messages sent between tasks.

SOPHISTICATED INTERNAL MEMORY
MANAGEMENT
The amount of internal memory available ranges
from 128 to 256 bytes depending on the type of microcontroller used.

Ouring run-time, the iOCX 51 Executive dynamically
manages this space. If a task is deleted, its stack
space is returned to the System Buffer Pool for use
by other tasks or as a message buffer.

Internal memory is used for the executive, stack
spare for "running" tasks, space for message buffers, and reserved memory for variables storage.
Other memory is used for register space. Except for
register space, the allocation of internal memory is
controlled by the executive, user-specified task/data
descriptors and system configuration constants.

As new tasks are dynamicallly created, the executive reserves the needed stack space. If no space is
available, the executive deallocates a buffer from
the System Buffer Pool and then allocates the needed stack space.

To optimize use of this limited resource, iOCX 51
provides dynamic (run-time) memory management.

INITIALIZATION AND DYNAMIC
MEMORY MANAGEMENT
At initialization (see Figure 4), the iOCX 51 Executive
creates the System Memory Pool (SMP) out of the
remaining initial free space (i.e. memory not used by
the iOCX 51 Executive or for register space). Next,
stack space is created for each of the initial tasks
that will be running on the system. If reserved memory is requested (using an 100), that memory is also
set aside. Finally, multiple buffers (size specified during iOCX 51 configuration or using an 100) are allo-

To send or receive a message, the executive allocates one or more buffers from the SBP for space to
locate the message. With iOCX 51, messages can
be optionally located in external (off-chip) memory.
The pre-configured executive in the 8044 BEM
BITBUS microcontroller, however, always locates
messages in internal memory.

RELIABLE
Real-time control applications require reliability. The
nucleus requires about 2.2K bytes of code space, 40
bytes on-chip RAM, and 218 bytes external RAM.

DCX 51 Initialization
Task 0
Task 1
Task 2
Task 3
Unallocated

STEPS:

InitIal
Free

Memory
Space

I
SBP

I
I

1. Create system memory pool from the initial free memory space.
2. Allocate stack space (space for 4 tasks shown).
3. Allocate user-reserved memory (per the 100).
4. Allocate equal-size buffers to form the system buffer
pool.

User
Memory

Figure 4. iDCX 51 Initialization of Internal Memory

17-10

iDCX51

Streamlined code increases performance and reliability, and flexibility is not sacrificed as code may be
added to either on-chip or external memory.

DEVELOPMENT ENVIRONMENT
Intel provides a complete development environment
for the MCS-51 and RUPI-44 families of microcontrollers. The iDCX 51 Executive is only one of many
of the software development products available. The
executive is compatible with the following software
development utilities available from Intel:
• 8051 Macro Assembler (ASM 51)
• PLIM 51 Compiler
• RL 51 Linker and Relocator Program
• LIB 51

The iDCX 51 architecture and simple user interface
further enhance reliability and lower cost. For example, the straightforward structure of the user interfaces, and the transparent nature of the scheduling
process contribute to reliability of the overall system
by minimizing programming effort. Also, modularity
increases reliability of the system and lowers cost by
allowing user tasks to be refined independent of the
system. In this way, errors are identified earlier and
can be easily corrected in each isolated module.

Intel hardware development tools currently available
for MCS-51 and RUPI-44 microcontroller development are:

In addition, users can assign tasks a Function ID
that allows tracking of the tasks associated with a
particular controllmonitorig function. This feature reduces maintenance and trouble shooting time thus
increasing system run time and decreasing cost.

• ICE-51 00/252 Emulator for the MCS-51 iamilyof
microcontrollers
• ICE-5100/044 Emulator for the RUPI-44 family of
microcontrollers (8044, 8344, 8744)
• iUP-200Al201 A PROM Programmer, 21 X software, and iUP programming modules

OPERATING ENVIRONMENT
The iDCX 51 Executive supports applications development based on any member of the high performance 8051 family of microcontrollers. The Executive
is available on diskette with user linkable libraries or
in the 8044 BITBUS Enhanced Microcontroller preconfigured in on-chip ROM. (The 8044 BEM is an
8044 component that consists of an 8051 microcontroller and SDLC controller on one chip with integral
firmware.)
When in the iDCM environment (Figure 5), the preconfigured iDCX 51 Executive can communicate
with other BITBUS series controller boards. The
BITBUS board at the master node can be associated with either an iRMXTM, PC-DOS or XENIX* host
system.

The DCX 51 Executive is also compatible with older
hardware development tools (no longer available),
which include:
• EMV-51 144 Emulation Vehicles
• ICE-51 144 In-Circuit Emulators
Table 4 shows the possible MCS-51 and RUPI-44
families development environments: host systems,
operating systems, available software utilities, and
hardware debug tools.

MASTER

REMOTE NODES
(SLAVES)

280176-4

Figure 5. iDeM Operating Environment
17-11

inter

iDCX51

SPECIFICATIONS

Reference Manual (Supplied)

Supported Microcontrollers

460367-001- iDCX 51 Distributes Control Executive User's Guide for Release 2.0.

8031
8051
8032
8744
8344

80C31
80C51
8751
8044
8052

ORDERING INFORMATION

Compatible DCM BITBUSTM Software
DCS 100 BITBUS Toolbox Host Software Utilities
DCS 110 BITWARE DCM44 Code for
ulation

~ITBUS

em-

Part Number
Description
Executive for 8051 Family of MicroDCX51SU
controllers. Single User License, Development Only. Media Supplied for
All Host Systems (Table 3).
Royalty (Incorporation) Fee for iDCX
DCX51RF
Executive. Set of 50 incorporations.
IDCX 51 RF does not ship with software (Order DCX 51SU).

Table 4. MCS®-S1/RUPITM-44 Families Development Environments
Host Systems
Development Utilities

PC/MS-DOS

iRMX®S6

iPDSTM

""
""
""

Intellec®
Series II

Series III/IV

""
""

""
""
""
""
""
""
""

SOFTWARE
ASM 51
PLIM 51

+ Utilities(1)
+ Utilities(1)

iDCX 51 Executive
HARDWARE
ICE-51 001044/252
iUP-200Al201 A
EMV-51 (2), EMV-44(2)

ICE-51(2), ICE-44(2)
iPDS

+ iUP-F87/44A PROM programmer

""
""

NOTES:
1. Utilities include RL 51, LIB 51, and AEDIT. Software for Series II systems is down-revision version.
2. These products are no longer available.

17-12

DCS100 BITBUSTM TOOLBOX
HOST SOFTWARE UTILITIES

•
•
•

Six Utilities Simplify Development of
Host Software for Controlling
BITBUSTM-Based Systems
Includes the BITBUSTM Monitor Which
Provides On-Line Monitoring and
Control of a BITBUSTM System
Reliable and Easy to Use

•

Universal BITBUSTM Interface and
BITBUSTM Interface Handler Libraries
Provide 32 System Managementl
Control Procedure

•
•

Compatible with Intel's C, PL/M and
ASM Languages
For DOS, iRMX® 86/286, XENIX·, and
iPDSTM Host Systems

The BITBUS Toolbox provides a set of utilities designed to simplify development of host system software for
controlling a BITBUS network. The Toolbox includes: two libraries of procedures that can be called from the
host code; an on-line program called the BITBUS Monitor which is invaluable for troubleshooting, monitoring,
and manually controlling a system; and code conversion/communication software to support applications
software development on a PC.
The procedure libraries contain common procedures used by the host to read or write data to remote node I/O
ports, download or upload programs and data, start and stop tasks (program modules) running on the nodes,
send and receive messages, and perform a variety of system status and control functions. By using these
libraries, the programmer's task of generating BITBUS host code is substantially reduced.

280732-1

"IBM, XT and AT are trademarks of International Business Machines Corporation.
"XENIX is a trademark of Microsoft Corporation.

17-13

October 1987
Order Number: 280732-001

inter

DCS100

THE BITBUSTM TOOLBOX-PRODUCT
DESCRIPTION
The BITBUS Toolbox is used to develop host code
for controlling a BITBUS network, and is an essential
tool for both centralized and distributed control applications.
With centralized control, the host code sends commands to a node to read and update the I/O. All the
decisions are made at the host. Normally, this kind
of system would require extensive host code. However, the Toolbox includes the UBI and BIH procedure libraries that can be called to perform simple or
, complex control procedures.
In addition to the Toolbox, all BITBUS boards include, in firmware, a set of procedures known as

Remote Access and Control (RAC). By sending simple messages to these procedures, basic I/O functions can be performed. The RAC procedures are
listed in Table 1.
With distributed control systems, programs run on
the remote BITBUS boards (nodes) and offload the
host system of most decision making responsibilities. Using UBI calls or the BITBUS Monitor, commands can be sent to the nodes to control tasks or
to periodically upload data for further analysis or
storage. The software tools in the BITBUS Toolbox
reduce the time and effort necessary to develop
host code for these applications.
In addition to the DCS100 BITBUS Toolbox, other
host code tools include a full set of host software
compilers, libraries, debuggers, and in-circuit emulators. The BITBUS Toolbox is described in detail in
the sections that follow.

Table 1_ Remote Access and Control Procedures
Function

Name
RESEl_STATION

Perform a software reset.

CREATE-TASK

Perform an RQ$CREATE$TASK system call.

DELETE-TASK

Perform an RQ$DELETE$TASK system call.

GET_FUNCTION_ID

Perform an RQ$GET$FUNCTION$IDS call.

RAC_PROTECT

Suspend or resume RAC services.

READ_I/O

Return values from speCified I/O ports.

WRITE-I/O

Write to the specified 1/0 ports.

UPDATE_I/O

Update the specified I/O ports.

UPLOAD_MEMORY

Return the values in specified memory area.

DOWNLOAD_MEMORY

Write values to specified memory area.

OR_IO

OR values into specified 1/0 ports.

AND_IO

AND values into specified I/O ports.

XOR_IO

XOR values into specified I/O ports.

READ_INTERNAL

Read values at specified internal RAM areas.

WRITE-INTERNAL

Write values to specified internal RAM areas.

NODE-INFO

Return device related information.

OFFLINE

Set node offline.

UPLOAD_CODE

Read values from code memory space.

DOWNLOAD_CODE

Write values to specified EEPROM memory.

17-14

inter

DCS100

The DCS100 BITBUS Toolbox includes six host software utilities. They include:

• OBJHEX Conversion Utility-Converts an object
file to hex format for downloading code.
• UDl2DOS-Converts Intel object code programs
to .exe format for execution on the PC.

• Universal BITBUS Interface (UBI)-a set of 28
procedures for implementing remote I/O and
controlling a BITBUS network.

Universal BITBUSTM Interface

BITBUSTM TOOLBOX UTILITIES

• BITBUS Interface Handlers (BIH)-four basic
procedures for sending/receiving messages over
a BITBUS network.
• BITBUS Monitor (BBM)-An on-line program with
36 commands that enable a user to configure,
troubleshoot, monitor, and manually control a
BITBUS network.

UBI is a library of 28 procedures called by the host
program to manage the I/O, download or upload
code and data, manage tasks on a node, send and
receive messages, and perform an assortment of
miscellaneous functions. These procedures are listed in Table 2, below.

• PC Bridge-Communications program for the PC
to support software development on a PC and
download into an iRMX or XENIX-hosted BITBUS
network.
Table 2. UBI Procedure Calls

1/0
BQ$AND$I/O
BQ$OR$I/O
BQ$XOR$I/O
BQ$WRITE$I/O
BQ$READ$I/O
BQ$UPDATE$I/O

AND I/O
OR I/O
Excl. OR 110
Write I/O
Read I/O
Write 110 and read back

MEMORY MANAGEMENT

BQ$ABS$LOAD
BQ$WRITE$CODE$MEM
BQ$READ$CODE$MEM
BQ$WRITE$INT$MEM
BQ$READ$INT$MEM
BQ$WRITE$EXT$MEM
BQ$READ$EXT$MEM

Download program to code memory
Write to code memory
Read code memory
Write to internal data memory
Read internal data memory
Write to external data memory
Read external data memory

TASK MANAGEMENT

BQ$CREATE$TASK
BQ$DELETE$TASK
BQ$GET$FUNCTION$IDS

Create task
Delete task
Read task function IDs

MESSAGE MANAGEMENT

BQ$FLUSH
BQ$RECEIVE$MESSAGE
BQ$SEND$MESSAGE

Clear an iSBX/iPCX interface
Receive a message
Send a message

17-15

inter

DCS100

Table 2. UBI Procedure Calls (Continued)
MISCELLANEOUS CALLS
BQ$DELAY
BQ$NODE$INFO
BQ$PROBE$SBX
BQ$PROTECT$RAC
BQ$RESET$DEVICE
BQ$RESYNC$NODE
BQ$SET$PORT
BQ$SET$SBX
BQ$SHELL .

Perform a time delay
Return node information
Check for BITBUS iSBX board
Lockout (protect) a node
Initiate a software reset
Set a node offline, prep. to resync
Set port 110 address
Set port 110 address
Shell escape and then return

The UBI utility includes libraries interfacing with
PL/M and C host code running within DOS, iRMX,
and XENIX environments. Also included are declaration files for the procedures.

READ or UPLOAD procedures) together with an error code. These error codes can help the host system take corrective action.

To use these procedures, the UBI calls are incorporated into the source code modules together with
parameters needed by the procedures (e.g. node
address, port address, memory location, task number, and data). The source module and UBI declaration files are then compiled and linked with the UBI
library.

BITBUSTM Interface Handlers (BIH)

When the call executes, the called procedure will be
performed, data will be returned (in the case of
T~ble

BIH is a library of four basic procedures for sending
and receiving messages between the host and network nodes. These procedures, listed in Table 3, are
most useful when generating custom UBI-like procedures. The BIH utility includes procedure libraries
and declaration files for DOS, iRMX 86/88/286, and
ISIS-PDS (iPDS)-based systems.

3. BIH Procedure Calls
Description

Call Name
CQ$DCM$INIT
CQ$DCM$RECEIVE
CQ$DCM$STATUS$CHECK
CQ$DCM$mANSMIT

Performs any initialization required by the
BITBUS Interface Handlers.
Receives one message from any BITBUS
node.
Determines whether a BITBUS message
is available to receive.
Transmits one message to any BITBUS
node. .

17-16

inter

DCS100

To use these libraries, the appropriate declaration
file is included with the host source code. The modules are then compiled and the resultant object
module is linked to the BIH library.

BITBUSTM Monitor
The BITBUS Monitor (BBM) is an on-line program
that is invaluable for troubleshooting and testing a
BITBUS system and can also be used to manually
control a system. BBM commands are listed in
Table 4.

Table 4. BITBUSTM Monitor Commands

1/0
AID
010
RIO
UIO
WID
XIO

MESSAGE MANAGEMENT

And 110
Or I/O
Read 110
Update I/O
Write to I/O
Exclusive OR I/O

MEMORY MANAGEMENT

LOAD
RCMEM
RIMEM
RXMEM
WCMEM
WIMEM
WXMEM

Download to code memory
Read code memory
Read internal memory
Read data memory
Write to code memory
Write to internal memory
Write to data memory

TASK MANAGEMENT

CTASK
DTASK
SYS

Create a task
Delete a task
Display node task status

DMSG
RMSG
SMSG
TMSG

Display a message
Receive a message
Send a message
Sends, receives, displays a message

MISCELLANEOUS COMMANDS

DELAY
EXIT
FLUSH
HELP
INCLUDE
LIST
LOCK
NODEINFO
PAUSE
RESET
RESYNC
SETPORT/
SETSBX
SHELL
SYMBOLS
UNLOCK
VERBOSE

17-17

Suspend Activity
ExitBBM
Clears an iSBX/iPCX interface
Provide on-line help
Open/execute a BBM file
Creates a copy of the BBM session
Lockout (protect) a node
Node information
Wait until
SW reset at a node
Set a node offline
Set port I/O address
XENIX/DOS shell escape from BBM
Display/create/change the value of
a user symbol
Unprotect
Controls echo and prompts

inter

DCS100

each node. The task management commands are
especially useful when developing/troubleshooting
multitasking control programs.

I/O ACCESS

Six commands are provided for writing to and reading from I/O ports 'on remote nodes. With these
commands, an operator can test the I/O connected
to a BITBUS node or monitor the status of an input
port. The I/O commands allow an operator to quickly isolate a problem at a remote node.

MESSAGE OPERATIONS

These four commands are used to send and receive
messages to and from tasks on remote nodes.

MEMORY ACCESS

MISCELLANEOUS COMMANDS

Seven memory access commands are provided.
These commands allow the operator to download
and upload both code (programs) and data (variables) between the host system and remote BITBUS
nodes. Internal RAM memory within the 8044BEM
microcontroller can also be accessed. In addition,
the BBM supports code download to both static
RAM and E2PROM devices. The memory access
commands are especially useful for on-target application development.

The BBM includes 15 commands that are used to
control the operating status of nodes, and to support
various troubleshooting functions. These commaflds
include:
The HELP command-an on-line facility that displays the complete BBM command directory or detailed information on using the commands.
The SHELL command-allows an operator to do a
shell escape to DOS or XENIX, perform the needed
operating system function, and return to the monitor.

The BITBUS Monitor enables the user to reference
a memory location by using a symbolic reference or
label. For example, if a task running on a node includes a program variable called "rate", the operator can modify this variable simply by typing:

The RESET, FLUSH, and RESYNC commandsused to clear a node that is hung.

WIMEM .rate 6CH

OPERATING ENVIRONMENT

In this case, the program will execute with a value of
6C hex for "rate".
Symbolic references can also be used for other
BBM parameters, such as node address, port address, and data. Symbolic access allows the user to
more easily test and modify programs at run time.

The BITBUS Monitor will run on DOS, iRMX 86/286,
XENIX and iPDS-based systems. Both 51f.1" and 8"
media is provided for iRMX and XENIX systems. The
iPDS version of the monitor does not include the
following BBM commands (or equivalent UBI calls):
DELAY, LIST, PAUSE, RCMEM, RESYSC, SETPORT, SYMBOLS, TMSG, VERBOSE, WCMEM.

TASK MANAGEMENT

PC Bridge

Four commands are available to monitor and control
the running of tasks on the nodes.
The DCX 51 real time multitasking executive found
on all BITBUS boards can support up to 7 user tasks
(in addition to the RAC task). Each of these tasks
have an initial Task Descriptor (ITO) which assigns a
function 10 to the task plus other important run-time
parameters used by the executive. By chaining ITDs
together, multiple tasks can become active upon
power up.

The PC Bridge is a communications program that
runs on a PC-DOS or MS-DOS system, and is used
to establish a communication link between the PC
and an Intel iRMX 86/286 or XENIX-based microcomputer system. The software engineer can use
the Bridge in two ways. First, he can develop host or
node programs on the PC-and download the code to
the host system or remote nodes. He can also use
the PC as a virtual terminal to the host system. The
PC Bridge effectively expands the development environment for the software engineer.

The BBM commands allow tasks to selectively be
made active (CTASK) or inactive (DTASK). In addition, the SYS command can be used to display
which nodes are present and operational in a system and display the function IDs for active tasks on

The link between the PC and the host microcomputer can either be over an RS232 cable (supplied) or
via a modem link. The PC Bridge transfers data at up
to 19.2K baud (asynchronous) and supports
XON/XOFF flow control.

17-18

intJ

DCS100

OBJHEX

Documentation (supplied)

OBJHEX is an object code to hex code conversion
utility similar to the OH51 hex converter supplied
with Intel "8051" languages. OBJHEX has the additional ability to retain the object module's sYlJlbol table during the conversion process. The table is
stored at the host system and enables the BITBUS
Monitor to symbolically access program memory.
OBJHEX runs on both DOS and iRMX86 (5%" , 8"
medial-based systems.

BITBUS Toolbox Overview and
Installation Guide
BITBUS Monitor User's Guide
Universal BITBUS Interface
User's Guide
BITBUS Interface Handlers User's
Guide
PC Bridge Communications Utility
User's Guide
BITBUS OBJHEX Conversion Utility
User's Guide

UDI2DOS
UDI2DOS converts Intel object code (8086 OMF) to
the .exe format so thal it will run within a DOS environment.

iii
:::I

::r:
iii

"1:1

0·':

><
W
..,::r:

III

C'I

A.m

:::I

X
X
B
B
X

X
X
X
X
X

X
A
X
X
X
X
X

149236-001
460237-001

Compatible Software

Order Number Description
BITBUS Toolbox Host Software
DCS100SU
Utilities, single-use license for development only. Includes RS232
cables to connect an Intel microcomputer system with an IBM'
PC-XT* or PC-AT*, and full documentation. See above for media
provided.
DCS100BY
BITBUS Toolbox Host Software
Utilities. Same as above, except
sold with a buyout license. Allows
incorporation of UBI and BIH procedure libraries-no additional incorporation fee is required.

(/)

Series II
IV
iPDS
IRMX5%"
8"
XENIX5%"
8"
DOS

148685-002

Order Codes

Media Provided

m
m

460236-001

Intel ASM, PL/M, and C languages
(8086/80286/80386 versions)

SPECIFICATIONS

460235-001
148686-002

A
X
X
X
X
X

A
X
X

NOTES:
A. iPDS uses Release 1 Toolbox.
B. Supports operation with XENIX. XENIX disks not required.

17-19

DCS110 BITWARE
DCS120 PROGRAMMERS SUPPORT PACKAGE
•

Supports Calls to the 8044BEM
Microcontroller On-Chip, Multitasking
.
DCX 51 Executive

•

Fully Compatible with Intel's ASM51
and PL/M51 Languages

•

DCS110 also Includes DCM44 Code to
Support Emulation/Debug of BITBUSTM
Node Code using Intel In-Circuit
Emulators

•

For DOS, iRMX®,IPDSTM, and Series
III/IV Development Environments

The DCS110 and DCS120 packages are designed to support software development of distributed control
BITBUS applications. Both products include a DCX51 interface library so that BITBUS application programs
can make calls to the DCX51 Executive. DCS110 also includes a DCM44 downloadable file that enables an
Intel in-circuit emulator such as the ICETM 5100/044 to emulate a BITBUS environment. By using an in-circuit
emulator together with DCS11 0, the developer can easily and quickly debug BITBUS application code.

..... - 0

.. .
._,~_....

•

280731-1

17-20

October 1987
Order Number: 280731-001

inter

DCS110/DCS120

DCX 51 ENVIRONMENT
The 8044BEM microcontroller, used on every
BITBUS board, includes in firmware a preconfigured
version of the DCX 51 Executive. DCX 51 provides a
variety of services to the application code, including:
task management; interrupt management; inter-task
communications; memory management; and timing
services. Up to 7 user tasks can run concurrently
under DCX 51. Each task has a unique Initial Task
Descriptor (lTD) that describes to the executive several run-time parameters (e.g. stack space, priority
level, etc.). By also specifying an Initial Data De-

scriptor (IDD), the executive can be partially reconfigured. Modifiable run-time constants include the
system clock rate, clock priority, internal memory
buffer size, and user (internal) memory size. DCX 51
calls are listed in Table 1.
By running applications under DCX 51, the designer
can make optimal use of the 8044BEM microcontroller. If a task needs to wait for a message, an interrupt, or a time period, DCX 51 will temporarily assign
access to the 8044 to another task. In this way, mUltiple tasks can access the microcontroller.

Table 1. DCX 51 Procedure Calls
Description

Call Name
Task Management Calls
RQ$CREATE$TASK

Create and schedule a new task.

RQ$DELETE$TASK

Delete specified task from system.

RQ$GET$FUNCTION$IDS

Obtain the function IDs of tasks currently in the system.

Intertask Communication Calls
RQ$ALLOCATE

Obtain a message buffer from the system buffer pool.

RQ$DEALLOCATE

Return a message buffer to the system buffer pool.

RQ$SEND$MESSAGE

Send a message to specified task.

RQ$WAIT

Wait for a message event.

Memory Management Calls
RQ$GET$MEM

Get available memory from the system memory pool.

RQ$RELEASE$MEM

Release memory to the system memory pool.

Interrupt Management Calls
RQ$DISABLE$INTERRUPT

Temporarily disable an interrupt.

RQ$ENABLE$INTERRUPT

Re-enable an interrupt.

RQ$WAIT

Wait for an interrupt event.

Timer Management Calls
RQ$SET$INTERVAL

Establish a time interval.

RQ$WAIT

Wait for an interval event.

17-21

inter

DCS110/DCS120

Interfacing to the DCX 51 Executive
To interface with the executive, DCS110 and
DCS120 both include a DCX 51 interface library plus
a set of "include" files. The interface library, which is
linked to the application modules, allow the code to
access DCX 51 procedures. The "include" files consist of DCX 51 declaration and macro definition files
that help simplify source code development. These
files are listed in Table 2.

DCS110 Bitware Software Package
In addition to the DCX 51 interface files, DCS110
also includes a DCM44 object file to support debug
of node code using an Intel in-circuit emulator.
DCM44 is the firmware found in all 8044BEM
BITBUS microcontr~lIers and together with an Intel

in-circuit emulator, successfully duplicates the
8044BEM ,environment. Emulators that are supported include the ICETM 5100/044, the ICE 44, and the
EMV 44.

Developing Applications Software
Using DCS110 or DCS120 software to develop
BITBUS applications software is a straightforward,
multi-step process as diagrammed in Figure 1. The
designer uses a text editor to write the application
code either in ASM 51 or PL/M 51. The source code
modules are then assembled/compiled along with
the DCX 51 "include" files. The final step is to link
together all of the modules, the DCX 51 interface
library, and the DCM441.LlB file. The linked/located
absolute object module can then be downloaded to
the target board or burned into EPROM.

Table 2_ DCS110/120 Files
Description

Filename
DCX 51 Support Files:
DCX51 I. LIB

Interface library to the DCX 51 executive. Provides the linker with the address of data
variables and entry points for DCX51 procedures called from other object modules.

DCX51 A. EXT
DCX51 A. LIT
DCX51P.LlT

External and literal declaration files. These files support DCX 51 calls from ASM 51
and PLIM 51 code.

DCXBOP.EXT
DCXB1P.EXT
DCXB2P.EXT
DCXB3P.EXT

DCX 51 External procedure declarations for PL/M 51 modules.using 8044 register
banks 0, 1, 2 or 3.

DCX51 A. MAC

Initial Task Descriptor (lTD) and Initial Data Descriptor (IDD) macro definitions.

APPL1.A51
APPL2.A51

Sample application, parts 1 and 2; template for generating ITDs and IDD.

DCM441.LlB

This file maps out reserved memory needed by the 8044BEM firmware and is linked
to other user object modules using the RL51 Linker.

DCM44 Firmware Files (DCS110 Only):
DCM44

DCM44 (BITBUS) code for InteIICETM/EMV emulators.

17-22

intJ

DCS110/DCS120

WRITE
SOURCE CODE

COMPILE/
ASSEMBLE

LINK

LOAD/EXECUTE

LEGEND:

(

FILE
)

r:::::J

DCSll0/120 FILE
SOFTWARE TOOL

DCS 110 ONLY
260731-2

Figure 1. DCS 110/120 Software Development Environment
DCS120BY

Development Environments
Both DCS110 and DCS120 are shipped with media
to support software development on PC/MS-DOS,
iRMX B6, iPDS, and Intellec® Series III/IV systems.
DCS110 is available with a single-use license for application development and debug. Designers planning to incorporte DCX 51 files in their application
should purchase the DCS120 "buyout" product.
Order Codes Description
DCS110SU
Bitware Software Package. Includes
DCM44 code to emulate a BITBUS
environment when using an Intel incircuit emulator and interface files to
support procedure calls to DCX 51.
Provided with documentation and
PC-DOS, iRMX B6 (5%" , 8"), iPDS,
and Series III/IV media. Single-use
license.

Programmers Support Package. Includes interface files to support procedure calls to DCX 51. Provided
with documentation and PC-DOS,
iRMX B6 (5%", 8"), iPDS, and Series IIIIIV media. Buyout license allows incorporation of software into
product-no additional incorporation
fee is required.

COMPATIBLE SOFTWARE TOOLS
DCS100

AEDIT

·XENIX is a trademark of Microsoft Corp.

17-23

BITBUS Toolbox Host Software Utilities for PC/MS-DOS, iRMX 86/286,
XENIX', iPDS, and Series IIIIIV host
systems.
Source Code and Text Editor for all
Intel host environments (consult
data sheet for order codes).

inter

DCS110/DCS120

8051 LANGUAGES

(Note: All products also include RL51 Linker/Relocator, LlB51 Librarian, and OH51 object to hex code
converter)
D86ASM51
ASM 51 Assembler for PC-.
DOS host system
R86ASM51
ASM 51 Assembler for iRMX
86 host system
186ASM51
ASM 51 Assembler for Series
III/IV host systems
ASM 51 -Assembler for iPDS
MC151ASM
and Series II host systems
PL/M 51 Compiler for PC-DOS
D86PLM51
host system
R86PLM51
PLIM 51 Compiler for IRMX 86
host system
186PLM51
PLIM 51 Compiler for Series
III/IV host systems
iMDX352
PL/M 51 Compiler for iPDS and
Series II host systems

IN-CIRCUIT EMULATORS AND PROM
PROGRAMMERS

(Note: + indicates that the product is no longer
available)
ICE51 00/044
In-Circuit Emulator for the RUPITM-44 Family (hosted on PC-'
DOS, and Series III/IV-see
data sheet for order codes)
ICE-44+
8044 In-Circuit Emulator (hosted on Series II-IV systems)
iPDSEMV44CON + Kit to add 8044 support to an
EMV-51/51 A emulator (iPDS
host)
iUP-200A,
Universal PROM programmer
iUP-201 A
(hosted on PC-DOS, iPDS, and
Series III/IV; see data sheet for
order codes)

17-24

8051 SOFTWARE DEVELOPMENT PACKAGES

COMPLETE SOFTWARE DEVELOPMENT SUPPORT FOR THE MCS®-51
FAMILY OF MICROCONTROLLERS
Intel supports application development for its MCS®-51 family of microcontrollers
with a complete set of development languages and utilities. These tools include a
macroassembler, a PLiM compiler, linker/relocator program, a librarian utility, and an
obJect-to-hex utility. Develop code In the language(s) you desire, then combine object
modules from different languages Into a single, fast program. These tools were designed
to work with each other, with the MCS-51 architecture, and with the IntellCE5100 in-circuit
emulator.

FEATURES
• Support for all members of the Intel
MCS-51 family of embedded
microcontrollers
• ASM-51 Macroassembler
• PLlM-51 high-level language
• Linker/Relocator program

o
o
o
o

Library utility
Object to hexadecimal converter
Hosted on IBM PC XT/AT V3 0 or later
Worldwide service and support

____________________

i~·

e Intel Corporation 1989

17-25

November, 1989
Order Number 280819·001

CREATE AND
COMPILE
WITH

MAINTAN

LIBRARIES WITH

CONVERT

TO HEX WITH

~F:l
ICE LOADABLE
CODe

E5;)
Figure 1: MCS®-51 Application Development Process

ASM-51 MACROASSEMBLER
ASM-51 is the macroassembler for the MCS-51 family
of microcontrollers. ASM-51 provides full and
accurate support for all of the specific components
instructions. It also provides symbolic access to the
many features of the MCS-51 family of
microcontrollers. Also provided is an "include" file with
all the appropriate component registers and memory
spaces defined.
The macro facility in ASM-51 saves development and
maintenance time. since common code sequences
need only be developed once.

PUM-51 COMPILER
PLlM-51 is a high-level language designed to support
the software reqUirements of the MCS-51 family of
microcontrollers. The PLlM-51 compiler translates PLI
M high-level language statements into MCS-51
relocatable object code. Major features of the PLI
M-51 compiler include:

• Structured programming for case of
maintenance and enhancement. The PLlM-51

• Data types facilitate various common
functions. PLlM-51 supports three data types to
facilitate various arithmetic. logic and address
functions. The language also uses BASED
variables that map more than one variable to the
same memory location to save memory space.

• Interrupt attribute speeds coding effort. The
INTERRUPT attribute allows you to easily define
interrupt handling procedures The compiler will
generate code to save and restore the program
status word for INTERRUPT procedures.

• Code optimization reduces memory
requirements. The PLlM-51 compiler has four
different levels of optimization for significantly
reducing the size of the program.

• Language compatibility saves development
time. PLlM-51 object modules are compatible with
object modules generated by all other MCS-51
language translators. This compatability allows for
easy linking of all modules and the ability to do
symbolic debugging with the IntellCE5100 incircuit emulator.

language supports modular and structured
programming. making programs easier to
understand. maintain. and debug.

17-26 .

RL-51 LlNKERlRELOCATOR

SERVICE, SUPPORT, AND TRAINING

Intel's RL-51 utility is used to link multiple MCS-51
object modules into a single program, resolve all
references between modules and assign absolute
addresses to all relocatable segments. Modules can
be written In either ASM-51 or PUM-51.

Intel augments Its MCS-51 architecture family of
development tools with a full array of seminars,
classes, and workshops; on-site consulting serVices,
field application engineering expertise; telephone hotline support; and software and hardware
maintenance contracts. This full line of services will
ensure your deSign success.

LIB-51
The Intel LIB-51 utility creates and maintains libraries
of software object modules. Standard modules can
be placed in a library and linked Into your
applications programs uSing RL-51. When using
libraries, the linker will link only those modules that
are required to satisfy external references.

OH OBJECT TO HEXADECIMAL
CONVERTER
The OH utility converts Intel OMF-51 object modules
Into standard hexadecimal format. This allows the
code to be loaded directly into PROM via non-Intel
PROM programmers.

ORDERING INFORMATION
D86ASM51 *

MCS-51 Assembler for PC XT or AT
system (or compatible), running DOS
3.0 or higher

D86PLM51 *

PUM-51 Software Package for PC
XT or AT system (or compatible),
running DOS 3.0 or higher

* Also includes: Relocator/Linker, Object-to-hex
converter, and Librarian.
For direct Information on Intels Development Tools, or
for the number of your nearest sales office or
distributor, call 800-874-6835 (U.S.). For Information
or literature on additional Intel products, call
800-548-4725 (U.S. and Canada).

17-27

ICETM-5100/044 IN-CIRCUIT EMULATOR

IN·CIRCUIT EMULATOR FOR THE RUPITM-44 FAMILY OF PERIPHERALS
The ICE-5100/044 In-Circuit Emulator is a complete hardware/software debug
environment for developing embedded control applications based on the Intel RUPITN-44
family of peripherals, including the 8044-based BITBUS'· board products. With highperformance 12 MHz emulation, symbolic debugging, and flexible memory mapping, the
ICE-5100/044 emulator expedites all stages of development: hardware development,
software development, system integration, and system test; shortening your project's time
to market.

FEATURES
•
•
•
•
•

Full speed to 12 MHz.
64KB of emulation mapped memory.
254 frames of execution trace.
Symbolic debug.
Serial link to an IBM PC XT, AT, 100%
compatible.
• Four address breakpoints with in-range,
out-of-range, and page breaks.
• On-line disassembler and single line
assembler.

•
•
•
•
•
•
•
•

Source code display.
ASM-51 and PLlM-51 language support.
Pop-up help.
DOS shell escape.
On-line tutorial.
Built-in CRT based editor.
System self-test diagnostics.
Worldwide service and support.

imJ-------------------C

Intel Corporation 1989

17-28

September, 1989
Order Number 280618·001

ONE TOOL FOR ENTIRE DEVELOPMENT
CYCLE

SYMBOLIC DEBUGGING FOR FAST
DEVELOPMENT

The ICE-51001044 emulator speeds target system
development by allowing hardware and software
design to proceed simultaneously. You can develop
software even before prototype hardware is finished.
And because the ICE-51001044 emulator precisely
matches the component's electrical and timing
characteristics, it's a valuable tool for hardware
development and debug. Thus, the ICE-51001044
emulator can debug a prototype or production
system at any stage in its development, without
introducing extraneous hardware or software test
tools.

Design team productivity IS enhanced by the use of
symbolic debug references to program line, highlevel statements, and module and variable names.
The terms used to develop programs are the same
used for system debugging.

HIGH-SPEED, REAL-TIME EMULATION
The ICE-51001044 emulator provides full-speed, realtime emulation up to 12 MHz. Because the emulator
is fully transparent to the target system, you have
complete control over hardware and software debug
and system integration.
64KB of zero wait-state emulation memory is
available to replace target system code memory,
allowing software debug to begin even before
prototype hardware is finished.

FLEXIBLE BREAKPOINTING FOR QUICK
PROBLEM ISOLATION
The ICE-51001044 emulator supports three different
types of break specifications: specific address breaks
on up to 64,000 possible addresses; range breaks,
both within and outside a user-defined range; and
page breaks, up to 256 pages on 256-byte
boundaries. 254 frames of execution trace memory
provide ample debug information, with each frame
divided into 16 bits of program execution address
and 8 bits of external event information. A maximum
of four tracepoints allows qualified trace for a variety
of debug conditions.

PATCH CODE WITHOUT RECOMPILING
Code-patching is easy with the ICE-51001044
emulator's single-line assembler. Machine code can
be disassembled to mnemonics for significantly
easier debugging and project development.

EASY TO LEARN AND USE
The ICE-51001044 is accompanied by a full tutorial
that explains all system functions and provides many
examples. Additional features such as on-line help, a
built-in CRT-based editor, and DOS shell escape
make the emulator fast and easy to use for both
novice and experienced users. You can develop your
own test suites or save frequently-used debug
routines as debug procedures (PROCs) that can be
invoked with a single command.

WORLDWIDE SERVICE AND SUPPORT
The ICE-51001044 emulator is supported by Intel's
worldwide service and support organization. In
addition to an extended warranty, you can choose
from hotline support, on-site system engineering
assistance, and a variety of hands-on training
workshops.

17-29

ELECTRICAL CONSIDERATIONS
The emulation processor's user-pin timings and loadings are identical to the 8044 component except as
follows.
• Up to 25 pf of additional pin capacitance is
contributed by the processor module and target
adaptor assemblies.

• Pins 18 and 19, XTAL1 and XTAL2, respectively,
have approximately 15 to 16 pf of additional
capacitance when configured for crystal operation.

• Pin 31, EA, has approximately 32 pf of additional
capacitance loading due to sensing circuitry.

PROCESSOR MODULE DIMENSIONS

DESIGN CONSIDERATIONS
Execution of user programs that contain interrupt
routines causes incorrect data to be stored in the
trace buffer. When an interrupt occurs, the next
instruction to be executed is placed into the trace
buffer before it is actually executed. Following
completion of the interrupt routine, the instruction is
executed and again placed into the trace buffer.

Figure 1. Processor Module Dimensions

SPECIFICATIONS
Host Requirements:
IBM PC-XI. AT or compatible
PC-DOS 3.0 or later
512K RAM
One floppy drive and hard disk

Physical Characteristics:
The ICE-51001044 emulator consists of the following
components:
.
Unit

Width

Height

Length

Inch Cm Inch Cm Inch

Controller
Pod
8.25 21.0 1.5
User Cable
Processor
Module"
3.8
9.7 1.5
Power Supply 7.6 18.1 4.0
Serial Cable
'with supplied ta(get adaptor.

17-30

3.8 13.5
39.0

34.3
99.0

3.8 4.0 10.2
10.2 11.0 28.0
144.0 1360.0

Electrical Characteristics:
Power supply
100-120V or 220-240V selectable
50-60 Hz
2 amps (AC max) @ 120V
1 amp (AC max) @ 240V

Environmental Characteristics:
Operating temperature: + 10°C to + 40°C (50°F to
104°F)
Operating humidity: Maximum of 85% relative
humidity, non-condensing

ORDERING INFORMATION
Order Code

DeSCription

pl044KITAD

Kit contains ICE-51 001044 user
probe assembly, power supply and
cables, serial cables, target adapter,
crystal power accessory, emulator
controller pod, emulator software,
DOS host communication, ASM-51
and AEDIT text editor (requires
software license).

pl044KITD

Kit contains the same components
as pI044KITAD, excluding ASM-51
and the AEDIT text editor (requires
software license).

pC044KITD

Conversion kit for ICE-51 00/452,
ICE-5100/451, or ICE-51 00/252
running PC-DOS 3.0 or later, to
provide emulation support for
MCS-51 components (requires
software license).

D86ASM51

ASM/RL 51 package for PC-DOS
(requires software license).

D86PLM51

PLIM/RL 51 package for PC-DOS
(requires software license).

D86EDINL

AEDIT text editor for PC-DOS.

For direct information on Intel's Development Tools, or
for the number of your nearest sales office or
distributor, call 800-874-6835 (U.S.). For information
or literature on additional Intel products, call
800-548-4725 (U.S. and Canada).
MCS IS a registered trademark and ICE IS a trademark of
Intel Corporation.
IBM and PC/AT are registered trademarks and PC/XT a
trademark of InternatIOnal BUSiness Machines Corporation.

17-31

BITBUSTM SOFTWARE DEVELOPMENT ENVIRONMENT

Intel has all the software tools you'll need to implement high-performance applications
using Intel BITBUS'M products. Tools include assemblers and compilers for host and
BITBUS node code development, debug monitors, in-circuit emulators, and specialized
BITBUS software. Intel's software tools are full-featured, easy-to-use, and help generate
reliable, easily maintained code in a minimum amount of time. Intel's complete solution
helps get your BITBUS-based distributed network quickly to market.

BITBUS NETWORK CONFIGURATIONS
A BITBUS network usually consists of a master (or supervisory) node and multiple remote
nodes as shown on figure 1. All BITBUS host interface boards and remote control boards
use the 8044 BITBUS Enhanced Microcontroller (8044BEM). The 8044BEM has built-in
communications software, memory management and 1/0 control procedures together
with a multitasking operating system. This built-in software, known as DCM44, greatly
simplifies the programmer's software design task.
BITBUS networks can be configured in two ways, either as distributed 1/0 systems with
centralized control, or as distributed control systems.

intel"---------C

Intel Corporation 1989

17-32

September; 1989
Order Number 280622·001

MASTER (HOST) SYSTEM

MASTER
NODE

+TOOLBOX

SOFTWARE

TERMINAL

DIGITAL
110

ANALOG
110

DIGITAL
I/O

\~----------------------------------------~I
REMOTE NODES

Figure 1: BITBUS'M Network

BUILT-IN RAC PROCEDURES SIMPLIFY
DISTRIBUTED 110 APPLICATIONS

DISTRIBUTED CONTROL BOOSTS
PERFORMANCE AND RELIABILITY

Distributed 1/0 systems are easy to design Node
code (code that runs on the remote BITBUS
board) is not required because the network IS
controlled by the master (host) system. To simplify
host code, each BITBUS board comes with a bUiltin set of procedures known as Remote Access and
Control (RAC). The master sends out commands
to the nodes and uses these RAC procedures to
collect data or to turn on and off motors, valves,
indicator lights, and other output devices.

BeSides using BITBUS for distributed 1/0, BITBUS
can also be used to implement powerful
distributed control systems. With distributed
control, the system can more easily control rapidly
changing, complex processes (e.g. robotics) and
gain the added benefit of higher network reliability
that is inherent in distributed control systems.
With distributed control, each board functions as a
controller performing a set of dedicated tasks. On
a periodic baSIS, the master can send a command
to a remote board to collect process control data
or request that a new task start running on a
remote board. The bUilt-in DCX 51 multitasking
executive on the 8044 BITBUS mlcrocontroller
allows up to 7 user tasks to run on the node at the
same time. The 12 MHz 8044 8-blt microcontroller,
together with the multitasking executive, allows
each BITBUS remote board to easily control
multiple, complex processes.

17-33

HOST SOFTWARE TOOLS
Intel's host software development tools include the
BITBUS Toolbox, a wide range of compilers and
assemblers for all of Intel's microprocessors,
software debug monitors, and in-circuit emulators.
BITBUS'" Toolbox - The Software Tool for All
Applications
The BITBUS Toolbox is a set of six software utilities
that greatly simplify development of host
applications software for BITBUS systems. The
utilities include: the BITBUS Monitor, two
procedure libraries known as the Universal
BITBUS Interface and the BITBUS Interface
Handlers; PC Bridge communications software;
and the OBJHEX and UOl200S c~de converters.
BITBUS'" Monitor.
The BITBUS Monitor provides the designer an online "window" into the BITBUS network. Over 35
commands are available allowing an operator to
check on the operation of various nodes turn I/O
either on or off, connect or disconnect n~des from
the network, start or stop tasks running on a node,
and download/upload code to/from remote
boards. The Monitor is invaluable when first
installing the BITBUS system, and is useful later to
troubleshoot a node or the equipment connected
to it.
Universal BITBUS'" Interface and BITBUS
Interface Handlers.
The Universal BITBUS Interface (UBI) is similar in
function to the BITBUS Monitor, except that UBI
calls can be made directly from the user's host
appl~cation program rather than from an operator's
terminal. Procedures are included that duplicate
most of the BITBUS Monitor commands. The UBI
is most useful for downloading code to a node,
uploading data to the host, starting and stopping
tasks running on the node, and writing/reading
data to/from the BITBUS boards' I/O ports.
If a programmer wants to develop custom, UBI-like
procedures, the Toolbox includes the BITBUS
Interface Handlers, which are a set of 4 basic
procedures that support communication with a
BITBUS node.
PC Bridge, OBJHEX, and UDI2DOS - The
Personal Computer Gateway to BITBUS"'.

Some designers may choose to use their PC as
the host system for the BITBUS network. To
support these networks, the Toolbox includes the
'U01200S utility, which is used to convert object
code, developed using Intel tools, to a ".exe"
format so that it will run on a PC.
The BITBUS Toolbox can be used on ~OS, iRMX®
86/286, XENIX#, and iPosm based systems.
Host Code Compilers, Assemblers. and Other
Tools
Intel's languages include PL/M, Fortran, PASCAL,
C, and a~se~bler for most of Intel's family of 8, 16,
and 32-blt.mlcroprocessors. For debug support,
PSCOPE, ISOMTM, and Soft-Scope#, which are
available in several versions, provide the
.
programmer powerful software tools to rapidly
isolate and correct faulty host code. These tools
are supported on a variety of host systems,
including ~OS, iRMX 86/286, and XENIX.
For programmers who need an even fuller featured
debug environment, Intel's 12ICE'M system
combines the capabilities of an in-circuit emulator
together with the PSCOPE 86 debug monitor and
a 16-channellogic analyzer. The 121CE system
supports 8086,8088,80186,80188, and 80286
code development. For programmers who are
designing 80386 code, Intel provides the ICE"'.
386 in-circuit emulator. The 121CE and ICE 386
emulators are supported on DOS and Intel Series
III/IV development systems.

SOFTWARE TOOLS FOR BITBUS'M
CONTROLLER BOARDS
By adding node programs to BITBUS boards the
designer can take full advantage of the BITBUS
boards' 8044 microcontroller's processing abilities.
Programmed remote boards enable the designer
to configure powerful, distributed control systems
with a minimum investment in hardware.
Developing node code for remote BITBUS boards
is just as easy as developing host code. Instead of
using iAPX-based software, BITBUS boards run
programs developed using "8051" tools. These
tools include PLIM 51 and ASM 51 languages,
RL51/LlB51 Linker/Locator/Librarian, and the ICE
51001044 in-circuit emulator. BITBUS-specific
software tools include OCS110 BITWARE and the
OCS120 Programmer's Support Package.

The BIT~US. Toolbox also includes the PC Bridge
communications software and the OBJHEX
PUM 51 and ASM 51 Languages
conversion utility. Many BITBUS networks will use
The programmer can write node code using either
an Intel 310 system as the host in order to take
PLIM 51 or the ASM 51 assembler Many programs
advantage of the systems performance or
a~e written using PLIM 51 because the language's
multitasking capabilities. The PC Bridge and
higher level statements reduce programming time
OBJHEX utilities enable the designer to use a PC
and produce reliable, easy-to-maintain code. If
.
to generate BITBUS node code, and then
necessary, speed-critical code is written using
download the code through the 310 system to any
ASM 51.
node on the BITBUS network. The software also
allows an operator to use a PC as a virtual terminal
to the 310 system.
.
17-34
• XENIX IS a trademark of MICrosoft Inc Soft-Scope IS a registered trademark of Concurrent SCiences, Inc
I

Multitasking Executive and DCS120 Maximize
System Performance

ICE 5100/044 and DCS110The Bug Chasers

Included In the 8044BEM mlcrocontroller on every
BITBUS board IS the DCX 51 multitasking
executive, which allows up to 7 user tasks plus the
RAC task to run on the board concurrently. If the
programmer is writing code for a remote board
that controls several Interrelated tasks, he can
segment the code into separate tasks and Increase
overall performance by uSing the multitasking
management provided by the executive. Twelve
DCX 51 calls are available providing tasks with
timing services, communications to other tasks on
the board, memory management services, and the
ability to dynamically create and delete running
tasks.

To provide debug support for node code
development, Intel provides the ICE 5100/044
In-circuit emulator and the DCS110 BITWARE
product. ICE 5100/044 includes an 8044 probe
that plugs into the BITBUS board in place of the
BITBUS 8044 microcontroller. BITWARE, which is
DCM44 firmware, provides the necessary software
so the ICE 5100/044 can emulate a BITBUS
environment. DCS110 also includes the DCX 51
Interface library and declaration files that are
provided in the DCS120 product.

INTEL SOFTWARE DEVELOPMENT
TOOLS - COMPLETE IN EVERY WAY
Intel provides a complete set of tools for the
software designer ranging from compilers and
debug monitors for the host system and BITBUS
nodes to specialized BITBUS software, like the
BITBUS Toolbox and BITWARE. These tools are
available for a Wide variety of development
environments, including Intel's system 310 and the
PC as shown in Table 1.

To access DCX 51 services, Intel provides the
DCS120 Programmer's Support Package, which
Includes an interface library to DCX 51 plus DCX
51 Procedure declaration files. To use DCS120, the
programmer adds the declaration files to the
source code. Then, after the source modules are
compiled, the interface library is linked with the
object modules and any other user libraries.

BITBUS'" TOOLS

NODE
CODE

ICE
(NOTE E)

OlX
:QUJ
~

OJ
OJ

::> 1D

Il..O

~
Il..

UJ
0:

ci.
en

::>

Il..

0
I
OJ...., C\J
OOJ 15
~

III

8"
XENIX 51ft!"

8"
DOS

X
A
X
X
X
X
X

A A
X X X X
)( A X X
X
B X
X
B X
X X X X X

X
X
X
X
X

Il.. 0:

X
X
X
X
X

C
X
X
C
D
D

Series II
IV
iPDS
iRMX5W'

10
::J
10 10
~ ~ 10
en ::J -.J

X X

C
X
X
C
D
D

X X X

Notes:
A IPDS uses Release 1 Toolbox
B Supports operation with XENIX. XENIX disks not required
C Down-reVision version
D Available for IRMX® 86
E ICE 44 and EMV 44 have been replaced by the ICET. 5100/044

Table 1
Product
BITBUS Toolbox
BITWARE
Programmer's Support Package

~
en

«en

-TOOLBOXQ)

EPROMPROG.

Order Code
iDCS100
iDCS110
iDCS120

17-35

«"""8::
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iSBXTM 344A
BITBUSTM INTELLIGENT MULTIMODULETM BOARD
• High Performance 12 MHz 8044
Controller

• 2 28-Pin JEDEC Memory Sites for
User's Control Functions

• Integral Firmware Including the iDCX 51 .
Executive Optimized for Real-Time
Control Applications

• Low Cost, Double-Wide iSBXTM BITBUS
Expansion MULTIMODULETM Board
• Power Up Diagnostics

• Full BITBUSTM Support
The iSBX 344A BITBUS Intelligent MULTIMODULE board is the BITBUS gateway to all Intel products that
support the iSBX I/O Expansion Interface. Based on the highly integrated 8044 component (an 8-bit 8051
microcontroller and an SDLC-based controller on one chip) the iSBX 344A MULTIMODULE board extends the
capability of other microprocessors via the BITBUS interconnect. With the other members of. Intel's Distributed
Control Modules (iDCM) family, the iSBX 344A MULTIMODULE board expands Intel's OEM microcomputer
system capabilities to include distributed real-time control. Like all members of the iDCM family, the iSBX 344A
MULTIMODULE board includes many features that make it well suited for industrial control applications such
as: data acquisition and monitoring, process control, robotics, and machine control.

280247-1

17-36

March 1988
Order Number: 280247-1102

inter

iSBXTM 344A BOARD

OPERATING ENVIRONMENT

MULTIBUS® Expansion

Typically, MULTIBUS iSBC boards have a maximum
of two iSBX I/O expansion connectors. These connectors facilitate addition of one or two iSBX I/O
MULTIMODULE boards with varying numbers of I/O
lines. The iSBX 344A MULTIMODULE board increases the number of I/O lines that can be accommodated by a MULTIBUS system by at least an order of magnitude.

As a member of the iDCM product line the iSBX
344A MULTIMODULE board fully supports the BITBUS microcontroller interconnect. Typically, the
iSBX 344A MULTIMODULE board would be part of a
node (master or slave) on the BITBUS interconnect
in an iDCM system. As shown in Figure 2 the iSBX
344A MULTIMODULE board plugs into any iSBC®
board with an iSBX connector.
The iSBX 344A MULTIMODULE board is the hardware interface between Intel's MULTIBUS® and the
BITBUS environment. With this interface the user
can harness the capabilities of other Intel microprocessors e.g. 80386, 80286, 80186, 8086, 80188,
8088 in a iDCM system or extend an existing MULTIBUS system with the iDCM family.

Extending BITBUSTM fiDeM System
Processing Capability
The iSBX 344A MULTIMODULE board allows utilization of other processors in a iDCM system to accommodate particular application requirements. The
MULTIMODULE board is compatible with any iSBX
connector so that any board having a compatible
connector can potentially enhance system performance. Intel's DCS100 BITBUS Toolbox Software
provides easy to use high performance software interfaces for iSBC boards. The iSBC 86/35, 286/12,
and 188/48 boards are a few examples. Custom
configurations are also possible with user customized software.

BITBUSTU
INTERCONNECT #2

280247-2

Figure 1. iDeM Operating Environment

17-37

intJ

ISBXTM 344A BOARD

face Unit (SIU). This 'dual processor architecture allows complex control and high speed communication to be realized cost effectively.

ARCHITECTURE
Figure 3 illustrates the major functional blocks of the
iSBX 344A board: 8044 BITBUS Enhanced Microcontroller (BEM), memory, BITBUS microcontroller
interconnect, Byte FIFO interface, initialization and
diagnostic logic.

The 8044 BEM microcontroller also includes built-in
firmware known as DCM44. This firmware includes a
set of functions called Remote Access and Control
(RAC), a preconfigured version of the DCX51 Executive, communications software, and a power-up test
procedure.

Memory

110 EXPANSION BUS

The iSBX 344A MULTIMODULE board memory consists of two internal and external memory. Internal
memory is located in the on-chip memory of the
iDCM controller. The iDCX 51 Executive and the remaining 8044 BEM firmware ration this resource.
However, eight bytes of bit addressable internal
memory are reserved for the user. Ample space is
reserved for user programs and data in the iSBX
344A MULTIMODULE board external memory.

OFF CHIP
INmAUZATION
& DIAGNOSTIC
LOGIC

MEMORY

......~-~~E
28PIN
CODE SITE

Two 28-pin JEDEC sites comprise the iSBX 344A
MULTIMODULE board external memory. One site
has been dedicated for data; the other for code. Table 1 lists the supported memory devices for each
site. Intel's 2764 and 27128 are examples. The user
may choose one of two memory configurations and
specify different memory sizes by placing the proper
jumpers at system initialization. The most flexible
configuration option provides the user with access to
the code site for program download or upload. This
feature ensures expansion of an existing system is
easily accommodated. For example, the addition of
another conveyor to a material handling system
would require adding another controller or controllers and changes to existing applications code and
addition of new code.

280247-4

Table 1. Supported Memory Devices

Figure 3. iSBXTM 344A Block Diagram

iDCM Controller
The heart of the iSBX 344A MULTIMODULE board's
controlling and communication capability is the highly integrated 12 MHz 8044 microcontroller. The 8044
consists of the advanced 8-bit, 8051 microcontroller
and a SDLC-based controller called the Serial Inter-

17-38

Device

Data Site

Code Site

4Kx8-64Kx8
EPROM/ROM
2Kx8-32Kx8
SRAM
2Kx8-16Kx8
NVRAM and E2PROM

Yes

inter

iSBXTM 344A BOARD

matically accepts messages for the FIFO. No user
code is required, increasing the time available for
application system development.

BITBUSTM Microcontroller
Interconnect
The iSBX 344A MULTIMODULE board fully supports
the BITBUS microcontroller interconnect. The
BITBUS interconnect is a serial bus optimized for
control applications. The interconnect supports both
synchronous and self-clocked modes of operation.
These modes of operation are selectable dependent
on application requirements as are the transmission
rates. Table 2 shows different combinations of
modes of operations, transmission rates, and distances. The SDLC-based protocol, BITBUS message format, and compatibility with Intel's other software and hardware products comprise the remainder of this established architecture. These features
contribute to BITBUS reliability and usefulness as a
microcontroller interconnect.
The BITBUS connection consists of one or two differential pair(s) of wires. The BITBUS interface of
the iSBX 344A MULTIMODULE board consists of a
half-duplex RS 485 transceiver and an optional
clock source for the synchronous mode of operation.

Byte FIFO Interface
The Byte FIFO Interface on the iSBX 344A
MULTIMODULE board implements the required
hardware buffering between the 8044 BEM and an
extension. An extension is defined as a device attached to the iSBX 1/0 expansion interface on the
iSBX 344A MULTIMODULE board. In an iDCM system, an example of an extension is an iSBC 286/12
board which may be considered the host board in a
MULTIBUS system. When used with the software
handlers in the BITBUS Toolbox, implementation'of
this interface is complete.
For particular applications, the user may wish to develop a custom software interface to the extension
or host board. On the iSBX 344A MULTIMODULE
board side of the interface the iDCM firmware auto-

The Byte FIFO supports both byte and message
transfer protocol in hardware via three register ports:
data, command, and status. The extension side supports polled, interrupt, and limited DMA modes of
operation (e.g. 80186 type DMA controllers).

Initialization and Diagnostic Logic
Like the other members of Intel's Distributed Control
Modules (iDCM) product line, the iSBX 344A
MULTIMODULE board includes many features
which make it well suited for industrial control applications. Power up diagnostics is just one of these
features. Diagnostics simplify system startup considerably, by immediately indicating an 8044 BEM or
external bus failure. The LEDs used for power up
diagnostics are available for user diagnostics after
power up as well as to further contribute to reliable
operation of the system.
Initial iSBX 344A MULTIMODULE board parameters
are set by positioning jumpers. The jumpers determine the BITBUS mode of operation: synchronous,
self-clocked, transmission rate, and address of the
iSBX module in the BITBUS system. This minimizes
the number of spare boards to be stocked for multiple nodes, decreasing stocking inventory and cost.

INTEGRAL FIRMWARE
Resident firmware located in the 8044 BEM includes: a pre-configured iDCX 51 Executive for user
program development; a Remote Access and Control (RAC) function that enables user communication
and control of different microcontrollers and 1/0
points; a communications gateway to connect the
BITBUS interconnect, iSBX bus, and iDCX 51 Executive tasks; and power up diagnostics.

Table 2. BITBUSTM Mlcrocontroller Interconnect Modes of Operation
Speed
Kb/s

Maximum Distance
Between Repeaters
Mlft

Maximum # Nodes
Per Segment

Maximum # Repeaters
Between a Master
and Any Slave

Synchronous

500-2400

30/100

Self Clocked

375
62.5

300/1000
1200/4000

28
28

2
10

Segment. Distance between master and repeater or a repeater and a repeater.
Synchronous mode requires user supplied crystal.

17-39

inter

ISBXTM 344A BOARD

The services provided by the iSBX 344A MULTIMODULE board integral firmware simplify the development and implementation of complex real-time
control application systems. All iDCM hardware
products contain integral firmware thus supplying
the user with a total ~ystem solution.

The Remote Access and Control Function is a special purpose task that allows the user to 'transfer
commands and program variables to remote BITBUS controllers, obtain the status of a remote 1/0
line(s), or reverse the state of a remote 1/0 line.
Table 4 provides a complete listing of the RAC services. No user code need be written to use this function.

Intel provides a complete development environment
for the iSBX 344A MULTIMODULE board. Software
development support consists of: the 8051 Software
Development Package, the DCS100 BITBUS Toolbox Host Software Utilities, the DSC11 0 Bitware for
ICETM Support, and the DCS120 Programmer's Support Package. The 8051 Software Development
Package provides the RL 51 Linker and Relocator
Program, and ASM 51. PL/M 51 is also available.
Hardware tools consist of the In-Circuit Emulator
(ICE 5100/044).

DEVELOPMENT ENVIRONMENT

Table 3. IDCX 51 Calls

Call Name

Description

TASK MANAGEMENT CALLS

RO$CREATE$TASK

Create and schedule a new task.

RO$DELETE$TASK

Delete speCified task from system.

RO$GET$FUNCTION$IDS

Obtain the function IDs of tasks currently in the system.

INTERTASK COMMUNICATION CALLS

RO$ALLOCATE

Obtain a message buffer from the system buffer pool.

RO$DEALLOCATE

Return a message buffer to the system buffer pool.

RO$SEND$MESSAGE

Send a message to specified task.

RO$WAIT

Wait for a message event.

MEMORY MANAGEMENT CALLS

RO$GET$MEM

Get available SMP memory.

RO$RELEASE$MEM

Release SMP memory.

INTERRU~T

MANAGEMENT CALLS

RO$DISABLE$INTERRUPT

Temporarily disable an interrupt.

RO$ENABLE$INTERRUPT

Re-enable an interrupt.

RO$WAIT

Wait for an interrupt event.

TIMER MANAGEMENT CALLS

RO$SET$INTERVAL

Establish a time interval.

RO$WAIT

Wait for an interval event.

17-40

iSBXTM 344A BOARD
Table 4. RAC Services
Action Taken by Task 0

RACService

RESET:""STATION

Perform a software reset.

CREATLTASK

Perform an RQ$CREATE$TASK system call.

DELETE_TASK

Perform an RQ$DELETE$TASK system call.

GET_FUNCTION_ID

Perform an RQ$GET$FUNCTION$IDS call.

RAC

Suspend or resume RAC services.

PROJECT

READ_I/O

Return values from specified I/O ports.

1/0
UPDATE_I/O
UPLOAD_MEMORY
DOWNLOAD_MEMORY
OR_I 10
AND 1/0
XOR_I/O

Write to the specified 1/0 ports.

WRITE

READ

INTERNAL

Update the specified 1/0 ports.
Return the values in specified memory area.
Write values to specified memory area.
OR values into specified 1/0 ports.
AND values into specified 1/0 ports.
XOR values into specified 1/0 ports.
Read values at specified internal RAM areas.

WRITLINTERNAL
NODE_INFO

Write values to specified internal RAM areas.

OFFLINE

Set node offline.

Return device related information.

UPLOAD_CODE

Read values from code memory space.

DOWNLOAD

Write values to specified EEPROM memory.

CODE

NOTE:
Internal memory locations are included in the 192 bytes of data RAM provided in the microcontroller. External memory refers
to memory outside the microcontroller - the 2S·pin sockets of the iSSX 344A module and the iRGS 44/10A board. Each
RAG Access Function may refer to multiple liD or memory locations in a Single command.

SPECIFICATIONS

Address Range

CPU
8044 BITBUS Enhanced Microcontroller (BEM)

Word Size
Instruction: 8 bits
Data: 8 bits

Processor Clock 12 MHz
Instruction Execution Times

,...S 60% instructions
,...S 40% instructions
4 ,...S Multiply & Divide
1

Memory CapacityI Addressing
iDCM Controller: Up to 64 Kbytes code

Option A

Option B

External
Data
Memory

0000H-7FFFH

External
Code
Memory

1000H-OFFFFH

8000H-OFEFFH

Internal
Code
Memory

OOOOH-OFFFH

OptIon A: Supports maxImum amount of external EPROM code memory.
OptIon B: Supports downloadIng code into external RAM or EEPROM
memory.

Terminations
Sockets provided on board for % Watt 5% Carbon
type resistors. Resistor value to match characteristic
impedance of cable as closely as possible-120n or
greater.

Message Size
54 bytes max

17-41

intJ

iSBXTM 344A BOARD

8044 BITBUSTM Enhanced Microcontroller
(8044
Function

+ Firmware) 1/0 Addressing as Viewed from the 8044
Address

Read

Write

Data

FFOOH

Command

FF01H

Status
-RFNP
-TFNE*
-TCMO*

B3H
B2H
92H

LED #1

90H

LED #2

91H

ROYINE*

B4H

Node Address

FFFFH

Configuration

FFFEH

Bit

Comments

Write sets command to
extension - Read clears
command from extension
Also INT1 Input
Also INTO Input

iSBXTM 344A MULTIMODULETM Board 1/0 Addressing as Viewed from the
iSBXTM 344A MULTIMODULETM Board
Register Function

Address

Comments

Base'

Read/Write

Data
Command

Base'

Write sets command from
extension
Read clears command to
extension

Status

Base'

Read Only

Interrupt/DMA Lines
Signal
RINT
TINT
RCMI
RORQTORQ

Location
- MORQ/MINTO
MINT1
OPTO
MORQ/MINTO
MINT1

Status Register Interface
Interface
Option

Status Register Interface

INT
INT
INTor OMA
OMA
OMA

7654321

III f I I I I iJ
~ TFNF*
~____________

RFNE*
RCMD*

280247-5

17-42

inter

iSBXTM 344A BOARD

The iSBX 344A MULTIMODULE board presents one
standard load to the BITBUS bus

Connector Options
10 Pin Plug
Flat Cable: 3M 3473-6010, TB Ansley 609-1001M,
or equal
Discrete Wire: BERG 65846-007, ITT Cannon 1217326-105, or equal

Power Requirements
0.9A at + 5V ± 5% (does not include power to the
memory devices)

Physical Characteristics
Pinout
Pin

Signal

1
2
3
4
5

+12V
+12V
GND
GND
DATA'
DATA
DCLK*/RTS'
DCLK/RTS
RGND
RGND

6
7
8
9
10

Double-wide iSBXTM MULTIMODULETM Form Factor
Dimensions
Height: 10.16 mm (0.4 in) maximum component
height
Width: 63.5 mm (2.50 in)
Length: 190.5 mm (7.50 in)
Weight: 113 gm (4 ounces)

Environmental CharacteristiCS
Operating Temperature: O·C to 55·C at 200 Linear
Feet/Minute Air Velocity
Humidity:
90% non-condensing

Electrical Characteristics
Interfaces
iSBXTM I/O Expansion Bus: supports the standard
I/O Expansion Bus Specification with compliance
level IEEE 959.

Reference Manual (NOT Supplied)
148099- iSBX 344A Intelligent BITBUS Interface
Board User's Guide

Memory Sites: Both code and data sites support the
standard 28-pin JEDEC site.

Ordering Information

BITBUSTM Interconnect: Fully supported synchronous mode at 2.4 Mbits/sec and self clocked mode
for 375 kbits/sec and 62.5 kbits/sec

Part Number Description
iSBX 344A
BITBUS Intelligent MULTIMODULE
board

17-43

iPCX 344A
BITBUSTM IBM* PC INTERFACE BOARD
•

High Performance 12 MHz 8044 SingleChip Microcontroller

•

Compatible with Intel's DOS-Based
Development Tools

•

Integral Firmware Optimized for RealTime Control Applications Using the
BITBUSTM Interconnect

•

External Memory Sites for User's
Control Programs

•

IBM PC System Form Factor Board

•

Fully Supports Intel's Complete Remote
Control Board Product Line (iRCB)

•

Power Up Diagnostics

The iPCX 344A BITBUS IBM PC INTERFACE board provides the BITBUS gateway to IBM's family of Personal
and Industrial Computers. Based on Intel's highly integrated 8044 (an 8051 microcontroller and an SDLC
controller on one chip) the iPCX 344A IBM PC INTERFACE board extends the real-time control capability of
the IBM PC via the BITBUS interconnect. The PC system performs the human interface functions for the
BITBUS interconnect. Like all members of Intel's Distributed Control Modules (iDCM) family, the iPCX 344A
IBM PC INTERFACE board includes features that make it well suited for Industrial Control applications such
as: data acquisition and monitoring, process control, machine control, and statistical process control (SPC).

,,'

,":
280414-1

·IBM is a trademark of International Business Machines.

17-44

March 1988
Order Number: 280414-002

inter

iPCX344A

IRCB 44/1 OA
DIGITAL BOARD

280414-2

Figure 1. iDeM Operating Environment

OPERATING ENVIRONMENT

ARCHITECTURE

Intel's Distributed Control Modules (iDCM) product
family provides the building blocks to implement
real-time distributed I/O control applications. All of
the iDCM family utilizes the BITBUS interconnect to
provide standard high speed serial communication
between microcontrollers. The iDCM hardware products: including the iPCX 344A board, iSBXTM 344A
MULTIMODULETM board and all iRCB BITBUS Remote Controller Boards communicate in an iDCM
system via the BITBUS interconnect as shown in
Figure 1.

Figure 2 illustrates the major functional blocks of
the iPCX 344A IBM PC INTERFACE board: 8044
BITBUS ENHANCED MICROCONTROLLER, memory, BITBUS interconnect, PC System Interface, and
initialization/diagnostic logic.

As a member of the iDCM Product line, the iPCX
344A IBM PC INTERFACE board fully supports the
BITBUS microcontroller interconnect. Typically, the
iPCX 344A IBM PC System INTERFACE board will
be part of a node (master or slave) on the BITBUS
interconnect. The iPCX 344A board plugs into the
PC add-in slot.
The iPCX 344A IBM PC INTERFACE board is the
hardware interface between the PC system and the
BITBUS environment. With this interface the user
can utilize the human interface and application software of the PC and extend the I/O range of the PC
to include real-time distributed control.

Memory, mode of operation, and bus transmission
rate options are easily selected by the user, thereby
decreasing inventory levels and associated costs.

8044 BITBUSTM Enhanced
Microcontroller (BEM)
The source of the iPCX 344A IBM PC INTERFACE
board's controlling and communication capability is
Intel's highly integrated 12 MHz 8044 microcontroller. The 8044 consists of the advanced 8-bit, 8051
microcontroller and a SDLC controller called the Serial Interface Unit (SIU). This dual processor architecture provides complex control and high speed
communications in a cost-effective, single chip implementation.

17-45

intJ

iPCX344A

Two 28-pin JEOEC sites comprise the iPCX 344A
board's external memory. One site is dedicated to
data; the other to code. Table 1 lists the supported
memory devices for each site. Intel's 2764 and
27128 are examples. The user can choose one of
two memory configurations and specify different
memory sizes by configuring the correct jumpers.
This configurability provides the user with access to
the code site for program download or upload and
ensures that an existing system is easily expanded.

PC BUS

, Table 1. Supported Memory Devices
OFF CHIP
MEMORY
28 PIN
DATA SITE
28 PIN
CODE SITE

INITIALIZATION
• DIAGNOSTIC
LOGIC

8044
BITBUS·· ENCHANCED
MICROCONTROLLER

Device

Data Site

Code Site

4Kx8-64Kx8
EPROM/ROM

Yes

2Kx 8-32K x 8
SRAM

Yes

2K x 8-16K x 8
NVRAM and E2PROM

Yes

BITBUSTM Microcontroller
Interconnect
The iPCX 344A IBM PC INTERFACE board fully supports the BITBUS microcontroller interconnect. The
BITBUS interconnect is a serial bus optimized for
control applications and supports both synchronous
and self-clocked modes of operation. Each mode of
operation and the different transmission rates are
jumper selectable dependent on application requirements.

BITBUS·· INTERCONNECT

280414-3

Figure 2. iPCX 344A Block Diagram
Another essential part of the 8044 controller is the
integral firmware residing on-chip to implement the
BITBUS interface. In the operating environment of
the iPCX 344A board, the 8044's'SIU acts as an
SOLC controller offloading the on-chip 8051 microcontroller of communication tasks; freeing the 8051
to concentrate on 'real-time control.
The 8044 BEM (8044 microcontroller and on-chip
firmware) provides in one package a simple user interface, and high performance communications and
control capabilities to efficiently and economically
build a complex control system ..

Table 2 shows different combinations of mode of
operation, transmission rate, and distance. The
SOLC protocol, BITBUS message format, and compatibility with Intel's other software and hardware
products comprise the remainder of this established
architecture. These features contribute to BITBUS
reliability and usefulness as a microcontroller interconnect.
The BITBUS connection consists of one or two differential user selected pair(s) of wires. The BITBUS
interface on the iPCX 344A board consists of a halfduplex RS485 transceiver and an optional clock
source for the synchronous mode of operation.

Memory
The iPCX 344A IBM PC System INTERFACE board
contains both internal and external memory. Internal
memory is located in the on-chip memory of the
8044 BEM. The BITBUS firmware includes Intel's
powerful iOCX 51, real-time, multitasking, executive.
Eight bytes of bit-addressable internal memory are
reserved for the user. Additional space is reserved
for user programs and data in the board's external
memory.

PC System Interface
The iPCX 344A board will operate in any IBM PC XT,
PC AT, or compatible system that meets the following requirements:
' - An IBM PC, PC XT with, an oscillator running at
4.77 MHz (processor running at 4.77 MHz also)

17-46

intJ
-

iPCX344A

An IBM PC AT with an oscillator running at 12 or
16 MHz (processor running at 6 or 8. MHz)
An available 1/0 channel with addresses that are
not used by any other boards in the system in the
range of 200H to 3FFH on even addresses
At least one available system interrupt (required
ONLY if running the iPCX 344A board in interrupt
mode; user selectable from PC Interrupts 2, 3, 4,
5,6, or 7)

All IBM guidelines have been followed to ensure
complete IBM PC system compatibility.

Initialization and Diagnostic Logic
Like the other members of Intel's Distributed Control
Modules (iDCM) product line, the iPCX 344A
BITBUS IBM PC INTERFACE board includes many
features making it well suited for industrial control
applications. Power on diagnostics simplify system
startup considerably by immediately indicating an
8044 BEM or external bus failure.

The iDCX 51 Executive is an event-driven software
manager that can respond to the needs of multiple
tasks. This real-time multitasking executive provides:
task management, timing, interrupt handling, and
message passing services. Table 3 shows the
iDCX 51 operating system calls. The executive supports up to seven user tasks at each node while
making BITBUS operations transparent.
Remote Access and Control (RAG) is a special purpose task that allows the user to transfer commands
and program variables to and from BITBUS controllers to obtain the status of 1/0 or data line(s), or
reverse the state of an 1/0 line or read and write
memory, etc. No user code need be written to use
this function. See Table 4 for a complete listing of
RAC services.
The services provided by the iPCX 344A board's integral firmware simplify the development and implementation of complex real-time control systems.

DEVELOPMENT ENVIRONMENT
Intel provides a variety of development environments for BITBUS applications. Intel's DevE1lopment
Systems and OEM Systems Handbooks provide details on the following development tools.
- BITBUS TOOLBOX-BITBUS Monitor and Interface Handlers
- ASM/PLM 51-Low and High level languages
for application code generation on 8044

INTEGRAL FIRMWARE

The iPCX 344A BITBUS PC-BUS INTERFACE board
contains resident firmware located in the 8044
BITBUS ENHANCED MICROCONTROLLER. This
on-chip firmware consists of: a pre-configured
iDCX 51 Executive for real-time, multitasking control;
DCM 44, a Remote Access and Control (RAG) program that enables BITBUS communication and control of 1/0 points on the BITBUS interconnect; and
power up diagnostics.
Table 2. BITBUSTM Microcontroller Interconnect Modes of Operation
Speed
Kb/s

Maximum Distance
Between Repeaters
M/ft

Maximum # Nodes
Per Segment'

Maximum # Repeaters
Between a Master and
Any Slave

Synchronous

500-2400

30/100

Self Clocked

375
62.5

300/1000
1200/4000

28
28

2
10

'Segment: DIstance between master and repeater or repeater and repeater.
Synchronous mode requires user supplied crystal.

Table 3. iDCX 51 Systems Calls
Description

Call Name
TASK MANAGEMENT CALLS
RO$CREATE$TASK

Create and schedule a new task.

RO$DELETE$TASK

Delete specified task from system.

RO$GET$FUNCTION IDS

Obtain the function IDs of tasks currently in the system.

INTERTASK COMMUNICATION CALLS
RO$ALLOCATE

Obtain a message buffer from the system buffer pool.

RO$DEALLOCATE

Return a message buffer to the system buffer pool.

RO$SEND$MESSAGE

Send a message to specified task.

RO$WAIT

Wait for a message event.
17-47

iPCX344A
Table 3. iDCX 51 Systems Calls (Continued)

Call Name

Des~ription

MEMORY MANAGEMENT CALLS
RQ$GET$MEM

Get available SMP memory.

RQ$RELEASE$MEM

Release SMP memory.

INTERRUPT MANAGEMENT CALLS
RQ$DISABLE$INTERRUPT

Temporarily disable an interrupt.

RE$ENABLE$INTERRUPT

Re-enable an interrupt.

RQ$WAIT

Wait for an interrupt event.

TIMER MANAGEMENT CALLS
RQ$SET$INTERVAL

Establish a time interval.

RQ$WAIT

Wait for an interval event.

Table 4. RAC Services
RACService

Action Taken by Task 0

RESET_STATION

Perform a software reset.

CREATLTASK

Perform an RQ$CREATE$TASK system call.

DELETLTASK

Perform an RQ$DELETE$TASK system call.

GET_FUNCTION_ID

Perform an RQ$GET$FUNCTION$IDS call.

RAC_PROJECT

Suspend or resume RAC services.

READ_I/O

Return values from specified 1/0 ports.

WRITE_1I0

Write to the specified 1/0 ports.

UPDATLI/O

Update the specified 1/0 ports.

UPLOAD_MEMORY

Return the values in specified memory area.

DOWNLOAD_MEMORY

Write values to specified memory area.

OR_1I0

OR values into specified 1/0 ports.

AND_I/O

AND values into spe~ified 1/0 ports.

XOR_1I0

XOR values into specified 1/0 ports.

READ_INTERNAL

Read values at specified internal RAM areas.

WRITE_INTERNAL

Write values to specified internal RAM areas.

NODE_INFO

Return device related information.

OFFLINE

Set node offline.

UPLOAD_CODE

Read values from code memory space.

DOWNLOAD_CODE

Write values to specified EEPROM memory.

SPECIFICATIONS
CPU

Processor Clock
12.0 MHz

8044 BITBUS Enhanced Microcontroller (BEM)

Instruction Execution Time

Word Size

1 ,..,s 60% instructions
2 ,..,s 40% instructions
4 ,..,s Multiply and Divide

Instruction-8 bits
Data-8 bits

17-48

inter

iPCX344A

Memory Capacity Addressing

Physical Characteristics

iDCM Controller: Up to 64 Kbytes code.
Device
EPROM/ROM
4Kx8-64KxB
SRAM
2Kx8-32KxB
NVRAM and E2PROM
2Kx8-16Kx8

IBM PC ADD-ON FORMAT
Height: 3.98 in.
Depth: 6 in.

Data

Code

Yes

Interfaces

Yes

BITBUS Interconnect: Fully supports synchronous
mode at 500 Kbps to 2.4 Mbs
and self-clocked modes at
375 Kbs or 62.5 Kbs
Note: On-board ALE clock
supports 1 Mbps synchronous operation. All other synchronous mode speeds require user-supplied 2.0 MHz9.6 MHz crystal.
PC System:
Two unidirectional, one-bytedeep, nine-bit FIFO buffers
(ninth bit distinguishes between data and command)

External 110 Space
OFFOOH-OFFFFH
space)

(mapped

into

data

memory

Termination
Minimum 120.0 each end of BITBUS interconnect
with user supplied resistors

Address Ranges
Power Requirements

Option'B
Option A
External Data 0000H-7FFFH
0000H-7FFFH
Memory Site
External Code 1000H-OFFFFH 8000H-OFEFFH
Memory Site (OOOOH -OFFFFH
If EA Active)
Internal Code OOOOH-OFFFH
OOOOH-OFFFH
Memory

0.9A at

up to 54 bytes

(memory not included)

Environmental Requirements

Opllon A: Supports maxImum amount of external EPROM code memo
ory.
OptIon B: Supports downloading code into external RAM or EEPROM
memory.

Message Size:

+ 5V ± 5%

Operating Temperature: 16·C to 32·C at no air flow
O·C to 55·C at 200 Linear
Feet/Minute air velocity
Operating Humidity:
90% Noncondensing
Storage Temperature: -40·C to + 70·C
Storage Humidity:

95% Noncondensing

REFERENCE MANUAL
149235-001- iPCX 344A BITBUS IBM PC System
Interface Board User's Guide

Connectors
Standard 9-pin-D Subminiature socket

ORDERING INFORMATION
Part Number
iPCX344A

17-49

Description
BITBUS IBM PC System
INTERFACE Board

iRCB 44/10A
BITBUSTM DIGITAL 1/0 REMOTE CONTROLLER BOARD

•
•
•
•
•

High Performance 12 MHz 8044
Controller
Integral Firmware: iDCX Executive,
Optimized for Real·Time Control
Full BITBUSTM Support
Standard Industrial Packaging:
Eurocard, DIN Connector

•
•
•
•

.110 Expansion with 8·Bit iSBXTM
Connector
Programmable Control/Monitoring
Using 24 Digital I/O Lines
Power Up Diagnostics
Compatible with IRCX 910 Digital Signal
Isolation and Termination Module

2 28·Pin JEDEC Memory Sites for
User's Control Functions

The iRCB 44/10A BITBUSTM Digital 110 Remote Controller Board is an intelligent real-time controller and a
remote 110 expansion device. Based on the highly integrated 8044 component (an 8 bit 8051 microcontroller
and an intelligent SOLC-based controller on one chip) the iRCB 44/10A board provides high performance
control capability at low cost. The iRCB 44/10A board can expand Intel's OEM microcomputer system capabilities to include distributed real-time control. Like all members of the iOCM family, the iRCB 44/10A board is
well suited for industrial control applications such as data acquisition and monitoring, process control, robotics,
and machine control.

280213-1

17-50

March 1988
Order Number: 280213-003

inter

iReB 44/10A

OPERATING ENVIRONMENT

ARCHITECTURE

Figure 2 illustrates the major functional blocks of the
iRCB 44/10A board: 8044 BITBUS Enhanced Microcontroller, memory, BITBUS microcontroller interconnect, parallel 1/0, iSBX expansion, initialization
and diagnostic logic.

The iRCB 44/10A board can be used as an intelligent remote controller or an 110 expansion device.
When performing as an intelligent controller the
iRCB 44/10A board not only monitors the status of
multiple process points, but it can execute varied
user supplied control algorithms. When functioning
as an 110 expansion device, the iRCB 44/1 OA board
simply collects data from multiple 110 ports and
transmits this information via the BITBUS or iSBX
bus interface to the system controller for analysis or
updating purposes.
As a member of the iDCM product line, the iRCB
44/10A board fully supports the BITBUS microcontroller interconnect. Typically, the iRCB 44/10A
board would be a node in a BITBUS system. The
iRCB 44/10A board could be a master or slave
node. (The BITBUS system supports a multidrop
configuration: one master, many slaves.)

8044 BITBUSTM Enhanced
Microcontroller
The heart of the iRCB 44/10A board's controlling
and communication capability is the highly integrated 12 MHz 8044 microcontroller. The 8044 consists
of the advanced 8-bit 8051 microcontroller and a
SDLC controller called the Serial Interface Unit
(SIU). This dual processor architecture allows complex control and high speed communication functions to be realized cost effectively. The 8044's SIU
acts as a SDLC-based controller which offloads the
on-chip 8051 microcontroller of communication
tasks; freeing the 8051 to concentrate on real-time
control.
The 8044 BEM microcontroller also includes, in firmware, a set of procedures known as Remote Access
and Control (RAG), a preconfigured version of the
DCX 51 Executive, communications software, and
power-up diagnostics.
The BEM (8044 microcontroller and on-chip firmware) provides, in one package, a simple user interface, and high performance communications and
control capabilities to efficiently and economically
build a complex control system.

280213-2

Figure 1. iDeM Operating Environment

17-51

inter

IRCB44/10A

ensures expansion of an existing system is easily
accommodated.

Memory
The iRGB 44/10A board memory consists of two
sections: internal and external. Internal memory is
located in the on-chip memory of the BEM. The
iDGX51 Executive and the remaining BEM firmware
ration this resource. However, eight bytes of bit addressable internal memory are reserved for the user.
Ample space is reserved for user programs and data
in the iRGB 44/10A board external memory.
Two 28 pin JEDEG sites comprise the iRGB 44/10A
board external memory. One site has been dedicated for data, the other for code .. Table 1 lists the supported memory devices for each site. Intel's 2764,
and 27128 are examples. The user may choose one
of two memory configurations and specify different
memory sizes by plaCing the proper jumpers at system initialization. The most flexible configuration option provides the user with access to the code site
for program download or upload. This feature

INITlALIZATION
AND
DIAGNOSTIC

Table 1. Supported Memory Devices
Device

Data Site

Code Site

4K x 8-64K x 8
EPROM/ROM

YES

8-32K
SRAM.

2K x 8-16K x 8
NVRAM and E2PROM

BITBUSTM Microcontroller
Interconnect
The iRGB 44/10A board serial interface fully supports the BITBUS microcontroller interconnect. The
BITBUS interconnect is a serial bus optimized for

28 PIN DATA SITE

LOGIC
28 PIN CODE SITE

24UNES
PARALLEL

I/O

BITBUsm
REPEATERS
(OPTIONAL)

•.......--,..,c::===.
REPEATED BITBUSg
INTERCONNECT

280213-3

Figure 2. iRCBTM 44/10A Block Diagram
17-52

iReB 44/10A

control applications. The bus supports both synchronous and self-clocked modes of operation. These
modes of operation are selectable dependent on application requirements as are the transmission
speeds. Table 2 shows the different combinations of
modes of operation, transmission speeds, and distances. The SOLC-based protocol, BITBUS message format, and compatibility with Intel's other software and hardware products comprise the remainder of the BITBUS architecture. These features contribute to BITBUS system reliability and usefulness
as a microcontroller interconnect.
The BITBUS connection consists of one or two differential pair(s) of wires. The serial (BITBUS) interface of the iRCB 44/10A board consists of: a halfduplex RS 485 transceiver, an optional BITBUS repeater and an optional clock source for the synchronous mode of operation.

Digital Parallel 110
In order to provide an optimal parallel liD interface
for control applications, the iRCB 44/1 OA board supports 24 software programmable parallel liD lines.
This feature supplies the flexibility and Simplicity required for control and data acquisition systems. Sixteen of these lines are fully programmable as inputs
or outputs, with loopback, on a bit by bit basis so
that bit set, reset, and toggle operations are streamlined. The remaining eight lines are dedicated as inputs. Figure 3 depicts the general 110 port structure.
The parallel liD lines can be manipulated by using
the Remote Access and Control (RAG) function (in
BEM firmware) from a supervisory node or locally by
a user program. The user program can also access

the RAC function or directly operate the liD lines.
Input, output, mixed- input and output, and bit operations are possible simply by reading or writing a
particular port.

iSBXTM Expansion
One iSBX liD expansion connector is provided on
the iRCB 44/10A board. This connector can be used
to extend the liD capability of the board. In addition
to specialized and custom designed iSBX boards, a
full line of compatible high speed, B-bit expansion
MULTIMODULE boards, both single and double
wide, are available from Intel. The only incompatible
modules are those that require the MWAIT' signal or
DMA operation. A few of Intel's iRCB 44/10A board
compatible iSBX MULTIMODULE boards include:
parallel liD, serial liD, BITBUS expansion, IEEE
488 GPIB, analog input and analog output.
With the iSBX 344A BITBUS Controller MULTIMODULE board and user supplied software, the iRCB
44/10A board can act as an intelligent BITBUS repeater facilitating the transition between two BITBUS segments operating at different speeds.

Initialization and Diagnostic Logic
Like the other members of Intel's Distributed Control
Modules (iDCM) product line, the iRCB 44/10A
board includes many features which make it well
suited for industrial control applications. Power up
diagnostics is just one of these features. Diagnostics
simplify system startup considerably, by immediately
indicating an iDCM controller or external bus failure.
The LEDs used for power up diagnostics are

Table 2. BITBUSTM MicrocontroJler Interconnect Modes of Operation
Speed
Kb/s

Maximum Distance
Between Repeaters
M/ft

Maximum # Nodes
Per Segment'

Maximum # Repeaters
Between A Master And
Any Slave

Synchronous

500-2400

30/100

Self Clocked

375
62.5

300/1000
1200/4000

28
28

2
10

'Segment: Distance between master and repeater or repeater and repeater. Synchronous mode reqUIres user supplied crystal.

17-53

inter

iReB 44/10A

available for user diagnostics after power up as well
to further contribute to reliable operation of the system.

INTEGRAL FIRMWARE

Initial iRCS 44/10A board parameters are set by poSitioning jumpers. The jumpers determine the
BITSUS mode of operation: synchronous, self
clocked, transmission speed, and address of the
iRCS 44/10A board in the BITBUS system. This
minimizes the number of spare boards to be stocked
for multiple nodes, decreasing stocking inventory
and cost.

The iRCB 44/10A board contains resident firmware
located in the 8044 BEM. The on-chip firmware consists of: a pre-configured iDCX 51 Executive for user
program development; a Remote Access and Controller (RAG) function that enables user communication and control of different microcontrollers and I/O
points; a communications gateway to connect the
BITSUS interconnect, iSBX bus, iPCX bus and iDCX
51 tasks; and power up diagnostics.

Table 3. iDCX 51 Executive Calls
Call Name

Description

TASK MANAGEMENT CALLS
RQ$CREATE$TASK

Create and schedule a new task.

RQ$DELETE$TASK

. Delete specified task from system.

RQ$GET$FUNCTION$IDS

Obtain the function IDs of tasks currently in the system.

INTERTASK COMMUNICATION CALLS
RQ$ALLOCATE

Obtain a message buffer from the system buffer pool.

RQ$DEALLOCATE

Return a message buffer to the system buffer pool.

RQ$SEND$MESSAGE

Send a message to specified task.

RQ$WAIT

Wait for a message event.

MEMORY MANAGEMENT CALLS
RQ$GET$MEM

Get available SMP memory.

RQ$RELEASE$MEM

Release SMP memory.

INTERRUPT MANAGEMENT CALLS
RQ$DISABLE$INTERRUPT

Temporarily disable an interrupt.

RQ$ENABLE$INTERRUPT

Re-enable an interrupt.

RQ$WAIT

Wait for an interrupt event.

TIMER MANAGEMENT CALLS
RQ$SET$INTERVAL

Establish a time interval.

RQ$WAIT

Wait for an interval event.

+5V

RESET"

OPEN
COLLECTOR

DATA
BUS - -.....--ID
BIT

;><:>--....- ....- - 1 1 0 PORT PIN

WR"---t-----'

RD"---+--.,
280213-4

Figure 3. 110 Port Structure

17-54

intJ

iReB 44/10A

BUS controllers, obtain the status of a remote 1/0
line(s), or reverse the state of a remote 1/0 line.
Table 4 provides a complete listing of the RAC services. No user code need be written to use this function. Power up tests provide a quick diagnostic service.
The services provided by the iRCB 44/10A board
integral firmware simplify the development and implementation of complex real-time control application systems. All iDCM hardware products contain
integral firmware thus supplying the user with a total
system solution.

Table 4_ RAC Services
RACService

Action Taken by Task 0

RESET_STATION
CREATE

Perform a software reset.

TASK

Perform an RO$CREATE$TASK system call.

DELETE_TASK

Perform an RO$DELETE$TASK system call.

GET FUNCTION
RAC_PROTECT

Perform an RO$GET$FUNCTION$IDS call.
Suspend or resume RAC services.

READ_IO

Return values from specified 1/0 ports:

WRITLIO

Write to the specified 110 ports.

UPDATE_IO

Update the specified 1/0 ports.

UPLOAD_MEMORY

Return the values in specified memory area.

DOWNLOAD_MEMORY
OR

Write values to specified memory area.
OR values into specified 1/0 ports.

1/0

AND_IIO

AND values into specified 1/0 ports.

XOR

XOR values into specified 1/0 ports.

1/0

READ_INTERNAL

Read values at specified internal RAM areas.

WRITE_INTERNAL

Write values at specified internal RAM areas.

NODLINFO

Return device related information.

OFFLINE

Set node offline.

UPLOAD

CODE

DOWNLOAD_CODE

Read values from code memory space.
Write values to specified EEPROM memory.

17-55

iRCB44/10A

mounting for one RCB 44/10A, with connectors for
power, the BITBUS interconnect signals, and 24 Industry Standard I/O isolation and signal conditioning
modules. These modules, available from a number
of vendors worldwide, typically provide greater than
1500V isolation and support signal conditioning in a
number of voltages including 5-60 VDC, 120 and
240 VAC.

INDUSTRIAL PACKAGING
The iRCB 44/10A form factor is a single high, 220
mm deep Eurocard and supports most standard industrial packaging schemes as well as Intel's RCX
910 Digital Signal Conditioning, Isolation and Termination Module (see below). The Eurocard form factor specifies reliable DIN connectors. A standard 64
pin connector is included on the iRCB 44/10A
board.

SPECIFICATIONS

Physical Characteristics

Word Size

Single high, 220 mm deep Eurocard Form Factor

Instruction: 8 bits
Data:

Dimensions
Width:

13.77 mm (0.542 in) maximum component
height

8 bits

Processor Clock 12 MHz

Height: 100 mm (3.93 in.)
Depth: 220 mm (8.65 in.)

Instruction Execution Times

Weight: 169 gm (6 ounces)

1 JLsec 60% instructions
2 JLsec 40% instructions
4 JLsec Multiply & Divide

DIGITAL SIGNAL CONDITIONING,
ISOLATION, AND TERMINATION
The RCB 44/10A is fully compatible with the RCX
910 Digital Signal Conditioning, Isolation and Termination Panel. The RCX 910 panel provides integral

Memory Capacityl Addressing
iDCM Controller: Up to 64 Kbytes code

DEVELOPMENT ENVIRONMENT
Intel provides a complete development environment for the iRCB 44/10A board.
BITBUSTM Development Environments
BITBUSTM TOOLS
DCS 100
TOOLBOX
(I)

ID
ID

1i'i

Series II

ID
()

8"
XENIX5%"

8"
DOS

CIl

0
0

C\I

15
:J

,...
,...

,...
~

X
X
X
X

B
B
X

X
X

::::;

~
......
...J

X
X

C
0
0

CIl

()

X
X
X
X

X
X
X

iO
~
CIl
«

III
IV
iPDS
iRMX5%"

iO
x
w
J:
....,

"0
.1:

ICETM

NODE
CODE

X
X
X

NOTES:
A. iPDS uses Release 1 Toolbox.
B. Supports operation with XENIX. XENIX disks not required.
C. Down-revision version.
D. Available for iRMX 86.

17-56

...J

v
v
0

......
0

....0

It)

EPROMPROG.

~
«CIl
«va.
..-~Q:

0 .... "0

~ffi

~~~
~.-:::I

a..<:"O

!:2

2j~

X
X

X
X
X

(I)

:;
"0

:e:::!:ff
~1X;a.

CIlU.·ca."O
9:2 a

iRCB44/10A

Address Ranges
Memory

Interrupt Sources

Option A

Option B

Two external: iSBX 1/0 Expansion bus sources or
other sources.
BITBUS Microcontroller Interconnect.

External -Data 0000H-7FFFH 0000H-7FFFH
-Code 1000H-OFFFFH SOOOH-OFEFFH
Internal

OOOOH-OFFFH

NOTES:
Option A: Supports maximum amount of external EPROM
code memory.
Option B: Supports downloading code Into RAM or
EEPROM memory.

8044 BITBUSTM Enhanced Microcontroller 1/0 Addressing
Function

Address

Read

Write

PORTA

FFCOH

PORTB

FFC1H

PORTC

FFC2H

MCSO

FFSOH-FFS7H
FFOO,FF01

MSC1

FFSSH-FF8F

LED #1

90H

LED #2

91H

RDY/NE*

B4H

NODE ADDRESS

FFFFH

CONFIGURATION

FFFEH

OPTO

92H

OPT1

93H

INTO

B2H

INT1

B3H

Bit

PARALLEL 1/0
Number: 2 S-Bit Bi-directional Ports
1 S-Bit Input Port
Table 5. Parallel 110 Electrical Specification
Parameter

Condition

VOL
VOH
VIH
VIL
IlL
IIH
II

IOL =16 rnA
IOH= -2 rnA

Min
2.4
2.0
-1.0

VIL =0.5V
VIH = logic high
VIH=7V

17-57

Max

Units

0.5

V
V
V
V
mA
rnA
mA

7.0
O.S
6.0
0.0
-2.2

inter

iRCB 44/10A

Memory Sites: Both code and data sites support the
electrical Universal 'Memory Site specification

Terminations
Sockets provided on board for Y4 Watt 5% Carbon
type resistors. Resistor value to match characteristic
impedance of cable as closely as possible-1-20n or
greater.

BITBUSTM Interconnect: The iRCB 44/10A Remote
Controller Board supports the BITBUS Specification ,
as follows:
Fully supported synchronous mode at 2.4
Mbits/second and self clocked mode for 375 kbits/
second and 62.5 kbits/second

Repeaters
Sockets provided on board: Devices 75174 and
75175

The iRCB 44/10A Remote Controller Board presents one standard load to the BITBUS without repeaters, with repeaters two standard loads

Connector Options
Message length up to 54 bytes supported
10 PIN PLUG

RAC Function support as shown in Table 4

Flat Cable: 3M 3473-6010, TB Ansley 609-1001M,
~~~

Parallel I/O: See the Table 5 for Electrical Specifications of the interface.

Discrete Wire: BERG 65846-007, ITT Cannon 1217326-105, or equal
-

Power Requirements
0.9A at +5V ±5% iRCB 44/10 board only (power
to memory, repeater, or iSBX board NOT included)

DIN CONNECTOR PLUG
Flat Cable: GW Elco 00-8259-096-84-124, Robinson
Nugent RNE-IDC64C-TG30, or equal

Environmental Characteristics

Discrete Wire: ITT Cannon G06 M96 P3 BDBL-004
GW Elco 60 8257 3017, or equal

Operating Temperature: O°C to 55°C at 200 Linear
Feet/Minute Air Velocity
Humidity:
90% non-condensing

10 Pin Repeater Connector Pin Out
Pin
1
2
3
4
5

6
7

8
9
10

Signal
+12V
+12V
GND
GND
DATA·
DATA
DCLK·/RTS·
DCLK/RTS
RGND
RGND

Reference Manual (NOT Supplied) ,
iRCB 44/10 Digital I/O Remote 148100-001 Controller Board User's Guide

Ordering Information
Part Number

Description

iRCB 44/10A

BITBUS Digital I/O Remote
Controller Board

Electrical Characteristics
Interfaces
iSBX I/O expansion bus: supports the standard
I/O Expansion Bus 'Specification with compliance
level D8/8F

17-58

iReB 44/20A
ANALOG I/O CONTROLLER
Distributed Intelligence via BITUSTM
• Serial
Bus
8044 8-bit Microcontroller at 12 MHz
• 12-bit Analog Resolution
• Up To 20 KHz Aquisition Rate (50 ms)
• Software Programmable Gain: 1, 10,
• 100,500
Ii Two 28-pin JEDEC Memory Sites

16 Single-ended or 8 Differential Input
• Channels
Channels
• 2±Outputs
Range or 4-20 mA Current Loop
• 1/010'1Expandable
via iSBXTM Connector
• Compact Single-Eurocard
• Low Power Consumption Packaging
• Compatible with iRCX 920 Analog
• Signal Conditioning, Isolation and
Termination Panel

The iRCS 44/20A is a fully programmable analog 110 subsystem on a single-Eurocard form-factor board. The
resident 8044 microcontroller operating at 12 MHz provides a means of executing data aquisition and control
routines remote from the host computer. Real-time capability is made possible by the iDGX 51 Distributed
Control Executive, resident in the 8044 microcontroller. Distribution of real-time control is implemented by the
SITSUS Serial Sus protocol, which is also managed integrally by the 8044.
Offering high performance, low-cost, and improved system bandwidth via distributed intelligence, the iRGS
44/20A Analog 110 Controller is ideal for data acquisition and control in both laboratory and industrial environments.

280721-1

MULTIMODULETM is a trademark of Intel Corporation.
IBM® PC is a registered trademark of International Business Machines Corporation.

17-59

November 1988
Order Number: 2e0121-002

inter

iRCB44/20A

. APPLICATION ENVIRONMENT

FUNCTIONAL DESCRIPTION

Intel's Distributed Control Modules (iDCM) product
family contains the building blocks to implement
real-time distributed control applications. The iDCM
family incorporates the BITBUS interconnect to provide standard high-speed serial communication between microcontrollers. The iRCB 44/20A may communicate with other nodes in a distributed system
via the BITBUS interconnect as shown in Figure 1.
Other nodes in the system may be the iSBX 344A
BITBUS Controller MULTIMODULETM, the iPCX
344A BITBUS IBM® PC Interface, the iRCB 44/10A
BITBUS Digital 1/0 Controller Board, or other BITBUS compatible products.
The iRCB 44/20A board, can be used as an intelligent remote controller or an 110 expansion device.
When performing as an intelligent controller the
iRCB 44/20A board not only monitors the status of
multiple sensors, it can also locally execute user developed control algorithms. When functioning as an
110 expansion device the iRCB 44/20A board manages tpe multiple 110 ports, transmitting this information via the BITBUS bus or iSBX interface to the
system controller for analysis or data logging purposes.
Typically, the iRCB 44/20A board will operate as a
node in a BITBUS system. BITBUS communication
supports a multidrop configuration with one master,
and multiple subordinate nodes. The iRCB 44/20A
board may be either a master or slave node to manage a wide variety of analog input or output tasks.

The major functional blocks of the iRCB 44/20A
board, shown in Figure 2, include the 8044 microcontroller and BITBUS interconnect, local memory,
Analog 1/0, and iSBX expansion.

Distributed Intelligence
The heart of the iRCB 44/20A board's controlling
and communication capability is the highly integrated 8044 microcontroller which operates at 12 MHz.
The 8044 contains the advanced 8-bit, 8051 microcontroller and a complimentary SDLC controller,
called the Serial Interface Unit (SIU). This dual processor architecture provides complex control and
high speed communication functions at a low cost.
Another essential part of the 8044 controller is the
on-chip firmware that exercises the BITBUS interface. The 8044's SIU acts as an SDLC controller, off
loading the on-chip microcontroller of communication tasks so it may concentrate on real-time control.
The 8044 microcontroller simplifies the user interface, and offers high performance communications
and control capabilities,in a single component package. Many interconnected Distributed Control Modules can form a powerful platform to efficiently and
economically administer a complete control system.

INPUT :t!iV,:l10V.
0-5V,D-IOV
• THERMOCOUPLE
• STRAIN GAUGE
• PRESURE SENSOR
eFLOWlolmR
• LEVEL IroIONITOR
OUTPUT_ 04-20mA,:l:5V,:I: lOV,

o-5V.o-1OV~ IRC84--

-=MCLK

r--D

CLR

0.0--

)--

DATA

S DATA

1/0.

RTS·

1
">

DATA-

J~
'I

1['-1

+5V

0-2-

DCLK/RTS

DCLK'I
RTS'

(]

J>--

L-J

-=-

SCLK

280129-7

NOTES:
1.
2.
3.
4.
5.

Connect to ground for self-clocked mode and SCLK for synchronous mode.
Remove for self-clocked operation with repeater(s).
Connect to RTS' for synchronous mode or 1/0' for self-clocked mode.
Selects MCLK as serial clock source.
Selects ALE or oscillator as serial clock source.

Figure 7. BITBUSTM Interface Hardware Requirements

IFLAG IADDRESS ICONTROL IINFORMATION IFCS IFLAG I
N

(BYTES)

Figure 8. BITBUSTM Frame Format
MSB

LSB
LENGTH

MT I SE I DE

J I
TR

NODE ADDRESS
SOURCE TASK

~::':~S~rTTED

RESERVED

IDESTINATION TASK

COMMAND/RESPONSE

MT - MESSAGE TYPE
SE - SOURCE EXTENSION
DE - DESTINATION EXTENSION
TR - TRACK FIELD

DATA

280129-8

Figure 9. BITBUSTM Message Format
17-80

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8044 BITBUSTM Enhanced Microcontroller

BITBUSTM Interface Configuration
The BEM's firmware also simplifies designation of
the bus mode of operation (Speed/distance option)
as well as the node address, memory configuration
and parallel interface parameters by reading two external locations for this information as shown in Fig-

ure 10. The designer no longer needs to directly manipulate the 8044's serial mode register (SMD),
status/command register (STS) , and send/receive
counter register (NSNR). These two 8-bit locations
are derived by multiplexing the 8044's port 0 address lines ADO-AD7.

Node Address Register

o
o
o
o

BITO
BIT1
BIT2
BIT3

BIT4

o
o
o

BITS
BIT6
BIT7

ALL JUMPERS REMOVED SELECTS
NODE ADDRESS OOH.
ALL JUMPERS INSTALLED SELECTS
NODE ADDRESS FFH.

280129-9

Mode Register
ESTABLISH THE BIT BUS'· MODE IN THE
BEM FIRMWARE. THEY ARE USED ONLY
DURING POWER·UP. BIT BUS'· MODE AND
BIT RATE ARE AS FOLLOWS:
00· SYNCHRONOUS
01 - SELF-CLOCKED 375Kb/SEC
10- RESERVED
11 - SELF· CLOCKED 62.5Kb/SEC.
RESERVED FOR FUTURE USE.
CONNECTED TO THE EA PIN OF THE
8044, ALLOWING INTERNAL ROM TO BE
DISABLED. JUMPER REMOVED ENABLES
INTERNAL ROM.

BITO
BIT1
BIT2

BIT3

BIT4
BITS

_______

_____

o
oO ~

CONNECTED TO THE MEMORY DECODE PAL
TO PROVIDE THE TWO MEMORY
ADDRESSING OPTIONS. IN BOTH CASES,

~~"o~O::DA~~~~T:;I~:: I~F SEPARATE
MAINTAINED. JUMPER REMOVED ROR
OPTION A; JUMI'ER INSTALLED FOR OPTION B.

BIT6
BIT7

~N~i:.riST~~g1~E~I:':~1~~I~~J~

THIS INFORMATION ON
INITIALIZATION. JUMPER REMOVED
INDICATES NO BYTE FIFO.
SELECTS EXTENSION MODE IF
BYTE FIFO IS PRESENT:
0= INTERRUPT
1 =DMA
RESERVED FOR FUTURE USE.
280129-10

NOTE:
Jumper Installed = 1
Jumper Removed = 0

Figure 10. BITBUSTM Firmware Configuration
17-81

intJ

8044 BITBUSTM Enhanced Microcontroller

Extended Firmware Services
PARALLEL COMMUNICATION INTERFACE
EXTENDS DISTRIBUTED CONTROL
CAPABILITY
The BEM's firmware also includes a parallel interface for expanding the capabilities of distributed systems. For example, this interface allows other processors to be employed in BITBUS systems if more
processing power is required as shown in Figure 11.
This interface provides the means for connection to
other buses: iSBX bus, STD bus, IBM's PC bus.
The interface consists of a byte-FIFO queue through
which BITBUS messages can be passd via embedded communications firmware. From the BEM's perspective the user simply designates the correct routing information in the BITBUS message header and
the message is directed to the communications firmware and passed through the parallel interface. One
example of an implementation that uses this interface is the iSBX BITBUS Controller MULTIMODULE
Board via the iSBX bus.
Parallel Interface Hardware
To implement the Parallel Interface, the user must
provide hardware for two FIFOs (one byte minimum)
in external data memory, and control Signals to/from
the 8044's Pins: INTO (P3.2), INT1 (P3.3), and P1.2.
Key hardware elements required are: decoder for
the registers' external addresses, temporary storage
for bytes passing through the interface, a way to
designate bytes as command or data, and a means
to generate the control signals. FIFO's must be used
to move the data through the interface although the
depth of the FIFO need not exceed one byte.

Interface hardware must also be provided for the
"extension" side of the interface. Implementation of
this hardware is left to the user with the restriction
that the operation of the BEM side remains independent.
Parallel Byte Stream and Message Protocol
The two byte registers (FIFOs) provide the path for
bytes to move through the parallel interface. Bytes
are read or written from the registers designated:
FIFO Data Byte (FFOOH) and FIFO Command Byte
(FF01 H). INTO, INT1 and P1.2 provide control signals to the firmware for moving the bytes through
the registers. These signals are referred to as the
Parallel Interface Control Bits:
Pin
INTO
INT1
P1.2

Function
RFNF
TFNE
TCMD

Internal Bit Address
B3H
B2H
92H

The hardware uses RFNF to control the output of
bytes from the BEM. RFNF is set when the FIFO
Data or FIFO Command Byte Registers can receive
information. RFNF remains clear when the FIFO
Data or Command Bytes are not available. Transmission of a BITBUS message across the parallel
interface consists of successively outputing message bytes to the FIFO Data Byte Register until all
bytes are sent. The firmware then writes a value of 0
to the Command Byte register indicating all the message bytes have been sent. The first data byte in the
message indicates the number of bytes in the message.

280129-11

Figure 11. Extending the Capability of BITBUSTM System with the Parallel Communications Interface
17-82

8044 BITBUSTM Enhanced Microcontroller

TFNE controls the input of data bytes to the BEM.
This bit is set when bytes are available for reading.
When no bytes are available this bit is clear. TCMD
indicates whether the next byte read is a Data Byte
or Command Byte. BITBUS messages are received
by inputing data bytes until a command byte is received. Data bytes are read from the FIFO Data Byte
Register. Command Bytes are read from the FIFO
Command Byte Register.
Figure 12 provides one example of a Byte FIFO Interface. This specific example illustrates the interface provided on the iSBX 344A BITBUS Controller
MULTIMODULE Board. Figure 13 shows transmission of bytes from the BEM across the parallel interface. Figure 14 shows transmission of bytes to the
BEM.

I
SEND MjSAGE

t~-----,

TO BITBUS'''INTERCONNECT

WRITE
NEXT
DATA

r~~~~~-----------~

BYTE

HEM

B044 LOCAL BUS

TCMD·

RFNF·

TFNE·

I
I
I

TRANSMIT
FIFO

RECEIVE
FIFO

YES

I
I
I
I
I
IL ________________
TFNF·
:~=~..
I
--1
EXTENSION DEVICE CPU

WRITE
END OF
MESSAGE
COMMAND

LOCAL BUS

EXTENSION
DEVICE CPU

260129-12

Figure 12. Byte FIFO Interface Example

RETURN

260129-13

Figure 13. Transmitting a Message from BEM
17-83

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8044 BITBUSTM Enhanced Microcontroller

RECEIVE MESSAGE

1990_Intel_Microcomputer_Boards_and_Systems 1990 Intel Microcomputer Boards And Systems

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