1990_MHS_8 Bit_Microcontrollers 1990 MHS 8 Bit Microcontrollers
User Manual: 1990_MHS_8-Bit_Microcontrollers
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I:1
8 BIT
MlCROCONTROLLERS
.•...
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o
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•
1990
--
- ~-------iiiiWliii
______
September 1989
GENERAL INFORMATION
MHS BACKGROUND
MATRA MHS was formed in 1979 as a joint venture
company beetween MATRA of France and HARRIS
Corporation of the United States. Its charter was to
develop a leading CMOS design and manufacturing
operation in Europe.
In the early 80's, MHS reached its objectives and became a pioneer with several novative products, especially CMOS static memories.
Then, several other agreements contributed to MHS
development.
In 1981, MHS signed an agreement with Intel Corp.
covering the manufacture of NMOS circuits in Nantes,
France and the establishment of a joint design facility
for telecom chips and video controllers (82716).
Resultingly, MHS manufactured Intel's 8086, 8088,
8051 and 8052, as well as Harris' 80C86/88.
MHS was also entitled to desing CMOS versions of the
8051 MCU family. The 80C51 and its derivates have
become one of MHS major successes, while fabrication
of 16 bit MPU and NMOS devices was stopped, to concentrate on CMOS MCU.
In 1985, a joint venture was created between MHS and
SGS Microelettronica to develop a fully automated assembly and test line for integrated circuits.
In a deal with Cypress, MHS received licensing rights
to manufacture Cypress fast 16 K, 64 K and 256 K
CMOS SRAMs and utilize Cypress fast 1.2 and 0.8
micron processes for MHS designs as well.
With France's national Telecom research labs (CNET),
MHS developed an advanced sub-micron process,
named Super-CMOS, to combine speed and low power
consumption (see page 4). This process is in production
at MHS since 1988, while most new devices are
designed to run on it.
Recently, MHS and NEC also signed a second-source
agreement covering mutual manufacture and design
rights of NEC's 78312A 16 bit microcontroller family.
MHS INDUSTRIAL CAPABILITY
MHS plant in Nantes (western France) includes a
2,000 m 2, class 10 wafer fab which is capable to
produce 100,000 125 mm wafers per year.
Around 15 million integrated circuits are shipped every
year by MHS.
The Nantes operation also has its own assembly and
test lines, as well as R&D and Quality departments.
This factory has been fully qualified by most major
military and space agencies according to their highest
standards; its quality has also been praised by some
of the world's most demanding I.C. users.
MHS SALES NETWORK
MHS has its own worldwide sales and distribution network, with direct subsidiaries in Paris, Munich, London,
Milan, Stockolm, Santa-Clara, and Hong-Kong.
These locations also have a technical center to ensure
local support for MHS' expertise inintegration and ASIC
design.
MATRA MHS
MHS PRODUCT OFFERING
devices for military, aeronautics and space applications : its factory has been certified AQAP-1 and a
variety of products have been listed by the corresponding agencies.
MHS offering includes four main product lines, all in
CMOS ; most circuits are available in commercial, indusrtrial, and military temperature ranges,
MHS is also a leading European manufacturerof Hi-Rei
MICROCONTROLLERS
The 8051 family in CMOS, with a complete palette of
options:
Quick ROM service: three weeks for ROM code customization.
ROM capacity from 4 K to 32 Kbytes : 80C51 , 80C52,
83C154, 83C154D.
and a specific single-chip keyboard controller :
80C752.
low-voltage (2.7 V), fuse-protected "secret ROM",
high-speed (20 MHz) versions.
STATIC RAMs
fast 16 K & 64 K devices: HM65728/767/768 (down
to 15 ns) & HM65764/787-790 and a fast 8 K x 9 :
HM65779, and 256 K devices 65756/65797/65798
"ultimate" 64 K SRAM, such as HM65664/656871
65688 : 35 ns, 1 i!A
very low-power 16 K and 64 K memories (6 transistors per cell) : HM65162/262 and HM65641
(8K x 8, 55 ns, 1 MA)
ECl SRAM 256 x 4 and 1 K x 4 in SICMOS process
technology. Access time: 3 ns.
application-specific memories.
DATACOM PRODUCTS
a family of combo devices (HC3054/57) compatible
with a market standard
ECMA102 multiplexed controllers, video codecs ...
These products can be used in Terminal Equipments or
at the Network Termination end.
specific chips for modem applications, the 29C42
error correction circuit for V42/LAP M Modems, the
HC55421 X21 interface, etc.
They are targeted for the upcoming generation of
equipment requiring powerful, flexible and low-cost
components.
MHS is introducing a range of circuits dedicated to
ISDN applications: rate adaptators (29C93), HDlC and
CMOS ASIC
Five gate-array families, with gate-counts from 250
up to 55,000 gates, ultra-fast CMOS arrays,
proprietary and standard software tools running on
VAX, SUN, or tumkey systems such as DAISY,
MENTOR, VALID, HP.
Specific smart software for system analysis and
logical synthetisis.
Digital and/or analog custom designs capabilities
using standard software from Silicon Compilers Systems Corp. : GOT and genesil.
Two families of Composite arrays mixing optimized
blocks (RAM, ROM, & others) with regular arrays of
gates.
iiii'MIiii
Field technical centers in most of its subsidiaries.
2
MHS DIFFERENTIATION
After having successfully proved its ability to provide the
electronic market with quality CMOS standard products
as well as ASICs, MHS has decided to offer additional
and newer solutions for system integration.
The above concept has been working so well that we
have developped priviledged relations with our customers. As a result, we are able to move with them
through the frontier between standard and user specific
I.C. We are diluting this frontier; our customer's experience has fertilized our tool box, and MHS's constantly richer tool box allows us to propose more and
smarter solutions every day.
We named it: "THE TOOLBOX".
It combines our best strengthes :
A unique sUb-micron process: the Super-CMOS.
With our customers, we became:
A proven experience in making microcontrollers,
SRAM, ASIC and Telecom chips which results in our
mastering several of the
most frequent
functionalities needed in modern electronic systems.
ACONSULTANT IN INTEGRATION
and
AN EXPERT IN INTEGRATION
A design methodology based the availability of the
above functions in a building block form, and a set
of advanced design tools - including silicon compilation - which allows to mix them on a single I.C. as required.
ALTERNATIVES FOR SYSTEM INTEGRATION
Each of the below criteria come from one or several different departments of our customers : marketing,
design, manufacturing, and purchasing or finance. Program managers will evaluate the appropriate trade-offs,
depending on the context of each program, including
technical, market, and other specific factors.
_ The total flexibility of these tools, which offers the
possibility to develop most specific product in gatearray, composite array, or optimized silicon, according to our customer needs, expressed in terms of
time-to-market, prototype cost, and production price.
This will help in choosing with MHS the best suitable
solution and planning, taking into account possibilities
offered by MHS to shift or evolve from one solution to
another one at a further program stage.
A team of very capable system and device architects, fully dedicated to analyze and discuss our
customers' needs, in order to choose with them the
best suited architecture and mean of integration to
completely satisfy their specific requirements.
STANDARD CIRCUITS
& PLD, GATE-ARRAYS
FULL CUSTOM
CIRClIlTS
COMPOSITE
ARRAYS
OPTIMIZED>
PARTITION
Breadboarding
++
+
++
-
-
Fast redesign
++
+
++
++
SAMPLE OF
CRITERIA
-
++
+
+
+/-
++
-
+
+
-
+
+
Test & emulation
++
+
++
Development cost
++
-
+
+
-
-/+
+
+
++
+
+
++
-/+
-
+
+
++
+
+
Level of integration
Complex systems
Flexibility
Technical risks
First production cost
Mature production cost
Second source
Confidentiality
+
(+ = satisfactory ; - = poor)
• Note : the optimizec partition is a multi·chip solution based on standard circuits and composite arrays, for which the balance of criteria is often more
favorable than solutions using custom circuits.
3
MHS SCMOS PROCESS
1. MHS COMMITMENT TO CMOS
THE DEVICES
For development and fabrication of the most advanced
integrated circuits in both the ASIC and standard
product fields MHS has made and stick to the choice of
CMOS technology. A lot of developments and progress
have been made from the initial 4 11m CMOS process,
back in 1980, to the most recent processes bearing on
materials, device physics or lithography which allow
now the new technology to provide speed and high integration density on top of the traditionnal virtues of
CMOS : low power consumption, wide voltage and
temperature operating range or high noise immunity.
To guarantee high operation frequency of products, it
is necessary to move toward submicronic transistor
size in new processes. SCMOS emphasizes this trend
as 0.8 micron drawn devices reach electrical channel
length as low as 0.65 micron forthe N channel transistor
thus conferring high speed potential to the circuits.
Short channels - however - have several drawbacks
that needed to be considered in SCMOS to guarantee
reliable operation and keep high performance:
To prevent punchthrough effects, such as voltage
limitations and subthreshold currents degrading the
circuit standby power consumption, in-depth study
and optimization of transistor ion implant have been
carried out.
When going to short channel length, very high
electrical fields are applied to electrons in the
devices and the chance for those carriers to get
enough energy to be injected in gate oxide becomes
significant.
This "hot electron" effect creates voltage and
transconductance shifts that degrade device and circuit reliability. To counter this threat on SCMOS,
both P and N channel transistors are built with LDD
structures. This "Lightly Doped Drain" structure
reduces the electrical fields in the devices drain
vicinity thus lowering the probability of hot electron
emission.
These continuous efforts made by the company in a
very focused way around CMOS led MHS to the introduction in 1988 of the Super CMOS (SCMOS) technology on which most of the new MHS integrated circuits
are now built or developed.
One single process however cannot fulfill all product requirements, and for this purpose complementary
developments have been performed to derivate from a
generic technology process varieties more suited to
particular needs as presented below.
2. THE SCM OS PROCESS
Co-developed with the France's National Telecom Research Laboratory (CNET) the SCMOS goal has been
to offer a generic process as described here before with
submicronic minimum features to provide a very high
speed potential as well as maximum integration
capability. Such advantages however should not be
gained against reliability characteristics which are of
prime importance in highly integrated system especially
for avionics or space application. For all these reasons
special options have been taken in building up the
process as can be viewed on the cross section of the
double metal version of SCMOS. Let's review the key
points of that construction:
These two examples illustrate, among other actions,
the particular care that was taken in designing the
SCMOS devices to get the best performances without
giving up any in reliability.
THE GATE MATERIAL
Used to build the transistor gates and being the first interconnection layer, this level has to have as low resistivity as possible. The SCMOS technology achieves
that goal by replacing the poly silicon material by a bilayer of polysilicon which keeps the transistor threshold
voltage characteristics, and Titanium Silicide which
provides the low resistance. A tenfold improvement has
been obtained through this solution, lowering typical
value of this layer from 30 ohm/square down to
3 ohm/square. A great benefit results for all product performances and especially for memory, for which long
word lines use to be realized with the gate level.
THE SUBSTRATE
The latch-up phenomenon has always been a major
concern of CMOS technology, that triggers parasitic
thyristor which can generate very high current flows
resulting in circuit non functionnality of destruction. By
using special electrical structure on circuits I/O's and
adopting careful layout rules inside the chips, accuity of
the problem has been greatly reduced on MHS
products. However, shrinking down the dimensions requires new solutions. Building the devices in a shallow
high resistive layer epitaxially grown on very low
resitivity substrate has proven its efficiency in killing the
latch-up phenomenon. By using such P+ epitaxial
wafers in SCMOS, voltage drops, induced by current injection in the substrate, are greatly reduced, while
chance of triggering the parasitic SCR is close to zero,
resulting in potential latch-up free circuits.
THE DOUBLE METAL SYSTEM
More and more circuits now require an enhanced routing capability, either to achieve higher integration density (memories), or to allow automation in placement
and routing tasks (ASIC). If multilayer interconnection
is a necessity, several limitations however have to be
overcome to implement it efficiently in very dense technology. Among the concerns of double metal systems
4
let us mention the silicon metal interface, the metal step
coverage, the risk of hillock formation generating shorts
between metal layers, contact filling, intermetal
dielectric planarization, via-contact stacking constrain,
and electromigration.
the next 5 years. Thanks to innovative options that were
made, it also bears the basics for future enhancements : it is already prepared for an analog version of
200 A
Gate oxide thickness
Here again, with SCMOS, an innovative solution has
been chosen to address most of these problems : it
stands in the utilization of Tungsten as the first metal
material, followed by a planarized intermetal dielectric
before deposition of the 2nd metal layer using
aluminium material.
Electrical channel length
• NMOS transistor
• PMOS transistor
0.65
Minimum drawn features
0.8
~m
Metal 1 pitch
2.9
~m
Among other properties, Tungsten can be deposited by
chemical vapor deposition technique which leads to
better topology coverage, and offers the possibility of
contact filling by an autoplanarization mechanism. Advantage is taken of this characteristic in allowing the
stacking of vias and contact to interconnect the 2 metal
layers. Such a possibility autorizes tighter metal pitches
thus saving area in repetitive structures and interconnections.
Metal 2 pitch
3.4
~m
~m
0.9~m
Propagation delay
120 ps/gate
Integration density
25000 transistor/mm 2
(RAM)
Table 1.
PRODUCT REQUIREMENTS
Other advantages come with tungsten utilization, including better reliability resulting from the very good
electromigration endurance of this material.
Through these specific developments, adding to the
basic works in new techniques around lithography
(direct stepping on wafers) or material deposition and
etching as well as manufacturing engineering works,
MHS as been able to master this advanced CMOS
process.
PRODUCTS
NEEDS
PROCESS
MICROCONTROLLER
OR COMPLEX LOGIC
Digital
high density
CMOS
DATACOM
Mixed analog
digital
CMOS
analog
MEMORIES
High density
CMOS
High speed High speed
ASIC
With its characteristics, of which an abstract is given in
table 1, the SCMOS appears as a key technology for
Flexibility
routeability
PROCESS VARIANCES
BASICSCMOS
LDWPOWER
1 POLY-1 METAL
SCMOS ANALOG
DIGITAL 2 POLY +
CAPACITORS
1<4-
~
SCMOS
2 METAL
-
5
CMOS
RADIATION
TOLERANCE
CMOS HIGH SPEED
2 POLY
BACK-BIAS GENERATION
CMOS
multilayer
2nd MEW..(AWMINIUM)
A'\SSIVAllON
LAYER
PlANARIZED
INTERMETAL
DIEI..ECTRIC
TUNGSTEN
POIYSIUCIOE
~re
~i6~~~;:~::~---1Z03-~~
~~~~~~===J~~~~+--LIJD
Pa-lANNB..
WJTHLIJD
lRANSISlOR
lCJW RESISTMTY P+ SUBSTMrE
HIGH RE5ISJMTY
P- EPITAXIALLAYER
MHS LlTTERATURE
the same process and for even smaller lithographies
(0.7 and 0.5 ~m).
Each volume includes all data pertinent to its topic :
data-sheets, application and technical notes,
software/progamming manuals, as well as a cross-reference guide to common industry equivalents, if any.
In order to provide our customers with a more exhaustive and regularly updated information, MHS has now
split its data book into several handbooks.
Last chapters deal with general information: quality and
reliability, dicelwafer form products, dice geometry
index, package selection & dimensions guides, and
sales network.
Following volumes are available:
MICROS - MEMORIES - DATACOM - ASIC GRAPHIC - HI-REL.
DATA SHEET CLASSIFICATION
CLASSIFICATION
DISCLAIMERS
PRODUCT STAGE
Preview
Formative or design
This document contains the design specifications for
product under development. Specifications may be
changed in any manner without notice.
Advance Information
Sampling or
pre-production
This is advanced information, and specifications are
subject to change without notice.
Preliminary
First production
Additional data may be published at a later date. MHS
reserves the right to make changes at any time without
notice, to improve design and supply the best possible
product.
PRODUCT INDEX
HANDBOOK
TOPIC
8 BIT MICROCONTROLLERS
80C51/C31 ; 80C51-UC31-L; 80C51F; 80C51S/C31S ; 80C52/32;
83C154 ; 83C154D ; 80C732/752.
16 BIT MICROCONTROLLER
78312/310 78312A1310A.
MEMORIES
HM 65687/688/664/767/768/770/772/728/7871788/789/790/791/764/7791
797/798/799/795/796/756/162/262/641/161 16116U6207165231.
DATACOM
29C93/94/95, 29C42/43, 29C80/82/84.
HC 55421 15570Al305213053/3054/3057.
ASIC
MA, MB, MAF, MC/MCR, MBM, MCM, CMOS Foundry, Macrocell
6402/12C, Macrocells in Development, MA & MB Summary, Daisy, Mentor,
Valid, Hewlett Packard, Gateaid II Vax, Superdesigner, Gasp.
6
MHS : A WORLD LEADER
IN 80C51 FAMILY OF MICROCONTROLLERS
In 1985, MHS became a pioneer in CMOS
microcontroller by introducing the CMOS version of the
popular 8051.
tomized ROM parts in less than 3 weeks
(80C51 and 80C52),
Beyond the well-known advantages of CMOS such as
low-power consumption, MHS design offered a fully
static core, allowing chip operation dONn to zero MHz
clock without data loss.
- a complete keyboard controller, integrated in
one single I.C. : 80C752.
- the long awaited 20 MHz version: 80C51 S,
All above devices have been successful around the
world in a wide variety of applications: over 8 million
parts have been shipped.
MHS kept on leading the way by continuoulsy introducing innovative versions:
MHS has more versions, more packages, more
temperature ranges and screening levels than any
other vendor on this family of microcontroller, for which
MHS is by far the first european source.
1986: - a low-voltage version (80C51-L) operating
with Vcc down to 2.7 V,
1987: - a "secret ROM" version (80C51 F) with which
simply blowing a fuse allows to protect ROM
content from being read or dumped by any
mean,
1989: - for software-greedy applications : at last a
32 K ROM device: 83C154D,
- piggy-back circuits 80C51 PX
- the first CMOS version of 8052 : 8 K ROM and
three timers.
- and a very clever solution for integrated
systems ...
1988: - 16 K bytes of ROM and additional features
with the 83C154,
If your already know most of all this, we will still surprize
you. If you did not so far, trying MHS might help you to
catch-up with those who know !
- the "Quick ROM" service : a precious advantage providing our customers with cus-
7
------1II1M1111111S - - - - - -
8 BIT MICROS
Product Index
Cross Reference
Architectural Overview of the MHS C51
Family of Microcontrollers
Hardware Description of the 80C51 , 80C52 and
83C154/C154D
MHS C51 Progammer's Guide
and Instruction Set
Data Sheets
Application Notes
Packaging
Quality
MHS Locations
IEII
I
9
MATRA MHS
PRODUCT
INDEX
~----------~~IIIS
1·1
PRODUCT INDEX
PART NUMBER
DESCRIPTION
PAGE
SOC51 131
4 KBYTES ROM, 12 MHz VERSION
SOC51 131-1
4 KBYTES ROM, 16 MHz VERSION
P 6-3
SOC51/31S
4 KBYTES ROM, 20 MHz VERSION
P 6-23
SOC51/31-L
4 KBYTES ROM, LOW POWER VERSION
P 6-41
SOC51 F
4 KBYTES ROM, ROM PROTECTED VERSION
P 6-59
SOC52/32
SOC52/32-1
SOC52/32S
SOC52/32-L
SOC52F
S KBYTES ROM, 12 MHz VERSION
P 6-77
S KBYTES ROM, 16 MHz VERSION
P 6-77
S KBYTES ROM, 20 MHz VERSION
P 6-77
S KBYTES ROM, LOW POWER VERSION
P 6-77
-----
P 6-3
S KBYTES ROM, ROM PROTECTED VERSION
P 6-77
SOC154/S3C154
16 KBYTES ROM, 12 MHz VERSION
P 6-101
SOC154/S3C154-1
16 KBYTES ROM, 16 MHz VERSION
P 6-101
SOC154/S3C154-L
16 KBYTES ROM, LOW POWER VERSION
P 6-101
S3C154F
16 KBYTES ROM, ROM PROTECTED VERSION
P 6-101
S3C154D
S3C 154 WITH 32 KBYTES OF ROM
P 6-101
SOC7521732
4 KBYTES ROM, KEYBOARD CONTROLLER
P 6-139
1-3
CROSS
REFERENCE
L - - - -_ _ _ _ _
2-1
~'{ji IllS
------ij l1li-----CROSS REFERENCE
8 BIT MICROCONTROLLERS with 4K BYTES OF ON·CHIP ROM
Reference
8OC31/80C51
80C31-U80C51-L
8OC51F
80C31S/80C51S
80C752!732
80C31 BHl80C51 BH
80C451/83C451
8OC31 BH/80C51 BH
MSM80C31/8OC51
8OC31/80C51
8OC451/83C451
8OC550/83C550
8OC851/83C851
SABSOC31/8OC51
Package
OIL PLCC FLAT
MHS
40
44
44
44
44
MHS
40
MHS
40
44
...
MHS
40
44
44
MHS
40
44
...
INTEL
40
44
...
INTEL
68
...
..
AMD
40
44
...
OKI
40
44
44
PHILIPS
40
44
44
PHILIPS
...
64
68
PHILIPS
40
44
...
PHILIPS
40
44
44
SIEMENS 40
44
...
Supplier
'
Freq.
MHz
0-16
0-6
0-16
0-20
0-12
16
16
16
16
16
16
16
12
12
Temp. Range
I
A M
X X
X X
X X
X X
X X
X X
X
X X
X X
X X
X X
X X
X X
X X
X
X
X
X
X
X
X
X
16 Bil
Timer
RAM
byles
110
ICC
max
2
2
2
2
3
2
2
2
2
2
2
2
2
2
128
128
128
128
256
128
128
128
128
128
128
128
128
128
32
32
32
32
32
32
56
32
32
32
56
32
32
32
26
10
26
32
26
26
28
26
26
26
29
???
24
???
16 Bit
Timer
RAM
bytes
110
ICC
max
Others
3
3
3
3
2
2
2
3
2
2
2
3
3
3
3
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
32
32
32
32
32
32
48
32
48
32
48
32
32
48
52
27
12
27
32
???
32
???
???
34
24
45
39
???
45
???
QUICK ROM
QUICK ROMI2.7 to 6 V
QUICK AND SECRET ROM
QUICK ROM120 MHz
NO
WATCHDOG + DDP
MORE 1/0, SLAVE INT.
12C
8 CAD, 2 PWM, 12C
12C
CAD,2 PWM
NO
NO
CAD, MORE VO
CAD, MORE 1/0, 2 USART
Olhers
QUICK ROM
QUICK ROM/2.7 to 6 V
QUICK ANO SECRET ROM
QUICK ROM120 MHz
QUICK ROMIKEYB. CONT.
80C51BHP PROTEC. ROM
MORE 1/0
NO
NO
NO
MORE VO
CAD+2 PWM
256 bytes EEPROM
8 BIT MICROCONTROLLERS with 8K BYTES OF ON·CHIP ROM
Package
OIL PlCC FLAT
44
8OC3218OC52
MHS
40
44
80C32-U80C52-l
MHS
40
44
44
8OC52F
MHS
40
44
...
8OC32S/80C52S
MHS
40
44
44
80C32T2I80C52T2 AMD
44
40
.. 80C321/80C521
AMD
40
44
...
8OC325180C525
AMD
68
...
68
8OC52180C32
PHILIPS
40
44
...
8OC552183C552
PHILIPS
...
68
80
8OC652183C652
PHILIPS
40
44
44
PHILIPS
...
8OC562183C562
68
80
8OC31 FAl8OC51 FA INTEL
40
44
...
SAB80C32180C52
SIEMENS 40
44
...
SABSOC515/80C535 SIEMENS ...
68
...
SAB80C517/80C537 SIEMENS ...
84
...
Reference
Supplier
Freq.
MHz
0-16
0-6
0-16
0-20
16
16
16
16
12
12
16
16
12
12
12
Temp. Range
I A M
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2·3
X
X
X
X
MATRAMHS
8 BIT MICROCONTROLLERS with 16K BYTES OF ON-CHIP ROM
Reference
Supplier
8OC154/83C154
80C154-L!83C 154-L
83C154F
80C154/83C154
80C31 FB/80C5.1 FB
80C654/83C654
80C541
MHS
MHS
MHS
OKI
INTEL
PHILIPS
AMD
H ·
Package
OIL PLCC FLAT
40
44
44
40
44
44
40
44
...
44
40
44
44
...
40
44
44
40
40
44
...
Freq.
MHz
0-16
0-6
0-16
16
16
16
12
Temp.
I
X X
X X
X X
X X
X
X X
X
Range
A M
X X
X X
X X
X
X
16 Bil
Timer
RAM
byles
I/O
ICC
max
Olhers
3
3
3
3
3
2
2
256
256
256
256
256
256
256
32
32
32
32
32
32
32
36
16
36
26
???
38
???
WATCHDOG
WATCHDOG/2.7 to 6 V
WATCHDOG/SECRET ROM
WATCHDOG
NO
12C
NO
Others
BIT MleROeONTROLLERS wllh 32K BYTES OF ON-CHIP ROM
Reference
83C154D
Supplier
MHS
Package
Freq.
OIL 1PLCC 1FLAT MHz
40144144 0-16
Temp. Range
1 I 1 AIM
X 1 1 1
16 Bil
Timer
RAM
byles
110
ICC
max
3
256
32
36
83C154 with 32 KROM
OIL: Dual In line; PLCC : Plastic Lead Chip Carrier; FLAT: Flat pack.
DDP : Dual Data Pointer.
MICROCONTROLLERS
M
•
D
80C51
IB
T
_T
TEMPERATURE RANGE
- BLANK : Commercial
(only one character
before device type)
: Industrial
-I
-40°C + 85°C
-A
: Automotive
- 40°C + 125°C
-M
: Military
-55°C + 125°C
-D
: Dice probed
at 25°C only
-Q
: Commercial
with Burn-in
•
MISCELLANEOUS
IB mil STD 883C
-116 MHz
- S 20 MHz
- L2.7Vto 6 V
•
•
ROM CODE: XXX
SECRET ROM: Fxxx
•
DEVICE TYPE
(48 H/125°C)
-L
•
: Industrial
with Burn-in
(48 HI125°C)
PACKAGE TYPE - - - - - - - '
• C: Side brazed
EXAMPLES
• D: Cerdip
P-80C31
• P: Plastic
• R: Leadless chip carrier
ID-t·OC32
• X: Dice form
XX-80C31
• S: PLCC
D-80C32-1
• F: Flat Pack
MD-80C51/B
• J: J leaded LCC
: Standart plastic 8 bit microcontroller ROM less.
Commercial temperature range.
: Industrial temperature range (- 40°C + 85°C)
Cerdip package
: Dice probed at 25°C - packaged in Chip-tray
: 80C32 in Cerdip - 16 MHz
: 80C51 after mil std. 883 - condo B
Military temperature range (- 55°C + 125°C)
Burn-in 168 H.
2-4
ARCHITECTURAL
D
OVERVIEW
OF THE MHS C51
FAMILY
MICROCONTROLLERS
3-1
------i-iIllS-----ARCHITECTURAL OVERVIEW
OF THE MHS C51 FAMILY
MICROCONTROLLERS
MEMBERS OF THE FAMILY
The MHS C51 family of microcontrollers consists of the devices listed in Table 1. The basic architectural structure of
these devices is shown in figure 1.
32K
ROM
83C154D
INTO INT1
TP1
TF2
TFO
RllTI
TXD
RXD
Figure 1 : Block Diagram of the 80C51/80C52/83C154/83C154D.
3·3
MATRA MHS
- - - - - - - -_ _ _ _ _ _ _ MHS C51
DEVICE
NAME
ROM LESS
VERSION
80C51
80C31
80C52
80C32
83C154/C154D
80C154
16K132K
ROM
BYTES
RAM
BYTES
16-BIT
TIMERS
TECHNO
4K
128
2
CMOS
8K
256
3
CMOS
256
3
CMOS
Table 1 : MHS C51 Family of Microcontrollers.
•
•
•
•
•
8-bit CPU optimized for control applications
Extensive boolean processing (single-bit logic) capabilities
32 bidirectionnal and individually address abies 110 lines
On chip clock oscillator.
Full duplex UART
•
•
•
•
•
•
•
On Chip Program ROM
On Chip Data RAM
External Data RAM
External Program Code
Timer/Counter
Source Interrupt
Priority Level
80C51
8OC52
83C154/C154D
4 K bytes
128 bytes
64 K bytes
64 K bytes
2
5
2
8 K bytes
256 bytes
64 K bytes
64 K bytes
3
6
2
16 Kl32 K bytes
256 bytes
64 K bytes
64 K bytes
3
6
2
• The 80C51 , 80C52, 83C154 and 83C154D differs from 80C31 , 80C32 and 80C154 in having the on-chip program
ROM. Instead, the 80C31 , 80C32 and 80C154 fetches all instructions from external memory.
80C51
The 80C51 is the CMOS version of the 8051. Functionally, it is fully compatible with the 8051, but being CMOS it
draws less current than its HMOS counterpart. To further exploit the power savings available in CMOS circuitry, two
reduced power modes are added ;
• Software-invoked Idle Mode, during which the CPU is turned off while the RAM and other onchip peripherals continue operating. In this mode, current draw is reduced to about 15 % of the current drawn when the device is fully
active.
• Software-invoked Power Down Mode, during which all on-chip activities are suspensed. The on-Chip RAM continues
to hold its data. In this mode the device typically draws less than 10 IJA.
Although the 80C51 is functionally compatible with its HMOS counterpart, specific differences between the two types
of devices must be considered in the design of an application circuit if one wishes to ensure complete interchangeability between the HMOS and CMOS devices.
The ROMless version of the 80C51 is the 80C31.
80C52
The 80C52 is an enhanced 80C51. It is fabricated with CMOS technology, and is backwards compatible with the
80C51. Its enhancements over the 80C51 are as follows:
• 256 bytes of on-chip RAM
• Three timer/counters
• 6-source interrupt structure
• 8 K bytes of on-chip Program ROM
The ROMless version of the 80C52 is the 80C32.
A separate product, the 80C52-BASIC, is an 80C52 with a full BASIC interpreter on-chip ROM.
------------------------------ MHSC51
83C154/C154D
The 83C154 is an enhanced 80C52. It is fabricated with CMOS technology, and is backwards compatible with the
80C52. Its enhancements over the 80C51 are as follows:
• 256 bytes of on-chip data RAM
• Three timer/counters (included watchdog and 32 bits timer/counters)
• 6 source interrupt structure
• Serial reception error detection
• New modes of power reduction consumption
• Programmable impedance port
• 16 K bytes of on-chip ROM for 83C154 and 32 K bytes for 83C154D
• Asynchronous Counter/Serial port mode during power-down
The ROMless version of the 83C154/C154D is the 80C154.
MEMORY ORGANIZATION IN MHS C51 DEVICES
LOGICAL SEPARATION OF PROGRAM AND DATA MEMORY
All MHS C51 devices have separate address spaces for program and Data Memory, as shown in figure 2. The logical
separation of Program and Data Memory allows the Data Memory to be accessed by 8-bit addresses, which can be
more quickly stored and manipulated by an 8-bit CPU. Nevertheless, 16-bit Data Memory addresses can also be
generated through the DPTR register.
Dl\D\P.EMORY
(READIWmE)
------------------FFFFH:
I
fFH:~i--~
I
I
I
I
I
INTEII'IAI.. I
I
I
I
U~l
I
I
I
I
.
IL____________
00
0000 _
L-~~~OO'~---J:
-------------,
Figure 2 : MHS C51 Memory Structure.
Program Memory can only be read, not written to. There can be up to 64 K bytes of program Memory. In the 80C51
the lowest 4 K bytes of Program Memory are on-chip. The 80C52 provides 8 K bytes of on-chip Program Memory
storage. The 83C154 provides 16 K bytes of on-chip Program Memory storage, and the 83C154D 32 K bytes. In the
ROM less versions (80C31 , 80C32, 80C154) all Program Memory is external. The read strobe for external Program
Memory is the signal PSEN (Program Store Enable).
Data Memory occupies a separate address space from Program Memory. Up to 64 K bytesQLexternal RAM can be
addressed in the external Data Memory space. The CPU generates read and write signals, RD and WR, as needed
during external Data Memory accesses. External Program Memory and external Data Memory may be combined if
desired by applying the RD and PSEN signals to the inputs of an AND gate and using the output of the gate as the
read strobe to the external Program/Data memory.
3-5
n
.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ MHS C51
PROGRAM MEMORY
Figure 3 shows a map of the lower part of the Program Memory. After reset, the CPU begins execution from location
OOOOH.
As shown in Figure 3, each interrupt is assigned a fixed location in Program Memory. The interrupt causes the CPU
to jump to that location, where it commences execution of the seNice routine. External Interrupt 0, for example, is
assigned to location 0003H. If External Interrupt 0 is going to be used, its seNice routine must begin at location 0003H.
If the interrupt is not going to be used, its seNice location is available as general purpose Program Memory.
002BH
0023H
INTEfIRUPT
LOCATIONS
001BH-
001~8BYTES
D
OOOBH
0003H
....... OOOOH
'--_
Figure 3 : MHS C51 Prograrn Memory.
The interrupt seNice locations are spaced at 8-byte inteNals : 0003H for External Interrupt 0, OOOBH for Timer 0,
0013H for External Interrupt 1, 001 BH for Timer 1, etc. If an interrupt seNice routine is short enough (as is often the
case in control applications), it can reside entirely within that 8-byte inteNal. longer seNice routines can use a jump
instruction to skip over subsequent interrupt locations, if other interrupts are in use.
The lowest 4 K (or 8 K in the 80C52 or 16 K in the 83C154 or 32 K in the 83C154D) bytes of Program Memory can
be either in the on-chip ROM or in an external ROM. This selection is made by strapping the EA (External Access)
pin to either Vcc or Vss. In the 80C51 and its derivatives, if the EA pin is strapped to Vcc, then program fetches to
addresses OOOOH through OFFFH are directed to the internal ROM. Program fetches to addresses 1OOOH through
FFFFH are directed to external ROM.
In the 80C52, EA = Vcc selects addresses OOOOH through 1FFFH to be internal, and addresses2000H through FFFFH
to be external.
In the 83C154, EA = Vcc selects addresses OOOOH through 3FFFH to be internal, and addresses 4000H to FFFFH
to be external.
In the 83C154D, EA = VCC selects addresses OOOOH through 7FFFH to be internal and addresses 8000H to FFFFH
to be external.
If the EA pin is strapped to Vss, then all program fetches are directed to external ROM. The ROMless parts must
have this pin externally strapped to Vss to enable them to execute from external Program Memory.
The read strobe to external ROM, PSEN, is used for all external program fetches. PSEN is not activated for internal
program fetches.
The harware configuration for external program execution is shown in figure 4. Note that 16 I/O lines (Ports 0 and 2)
are dedicated to bus functions during external Program Memory fetches. Port 0 (PO in Figure 4) seNes as a multiplixed
address/data bus. It emits the low byte of the Program Counter (PCl) as an address, and then goes into a float state
awaiting the arrival of the code byte from the Program Memory. During the time that the low byte of the Program
Counter is valid on PO, the signal ALE (Address latch Enable) clocks this byte into an address latch. Meanwhile,
Port 2 (P2 in Figure 4) emits the high byte of Program Counter (PCH). Then PSEN strobes the EPROM and the code
byte is read into the microcontroller.
Program Memory addresses are always 16 bits wide, even though the actual amount of Program Memory used may
be less than 64 K bytes. External program execution sacrifices two of the 8-bit ports, PO and P2, to the function of
addressing the Program Memory.
iiii'MIiii
3-6
MHSC51
Figure 4: Executing from External Program Memory.
DATA MEMORY
The right half of Figure 2 shows the internal and external Data Memory spaces available to the MHS C51 user.
Figure 5 shows a hardware configuration for accessing up to 2 K bytes of external RAM. The CPU in this case is
executing from internal ROM. Port 0 serves as mulliQ!exed address/data bus to the RAM, and 3 lines of Port 2 are
being used to page the RAM. The CPU generates RD and WR signals as needed during external RAM accesses.
There can be up to 64 K bytes of external Data Memory. External Data Memory addresses can be either 1 or 2 bytes
wide. One-byte address is often used in conjunction with one or more other I/O lines to page the RAM, as shown in
Figure 5. Two-byte addresses can also be used, in which case the address byte is emitted at Port 2.
Internal Data Memory is mapped in figure 6. The memory space is shown divided into three blocks, which are generally
referred to as the lower 128, the Upper 128, and SFR space.
Internal Data Memory addresses are always one byte wide, which implies an address space of only 256 bytes. However, the addressing modes for internal RAM can in fact accomodate 384 bytes, using a simple trick. Direct addresses
higher than 7FH access one memory space, and indirect addresses higher than 7FH access a different memory
space. Thus figure 6 shows the Upper 128 and SFR space occupying the same block of addresses, 80H through
FFH, although they are physically separate entities.
Figure 5 : Accessing External Data Memory. If the Program Memory is external, the other bits of P2 are available
as I/O.
The Lower 128 bytes of RAM are present in all MHS C51 devices as mapped in Figure 7. The lowest 32 bytes are
grouped into 4 banks of 8 registers. Program instructions call out these registers as RO through R7. Two bits in the
Program Status Word (PSW) select which register bank is in use. This allows more efficient use of code space, since
register instructions are shorter than instructions that use direct addressing.
The next 16 bytes above the register banks form a block of bit-addressable memory space. The MHS-C51 instruction
set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these
instructions. The bit addresses in this area are OOH through 7FH.
All of the bytes in the Lower 128 can be accessed by either direct or indirect addressing. The Upper 128 (Figure 8)
can only be accessed by indirect addressing. The Upper 128 bytes of RAM are not implemented in the 80C51 but
are in the 80C52, 83C154 and 83C154D.
3-7
n
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ MHS C51
7FH
~~-------r-----~~
I
BANK
IADDRESSING
SELECr
ACCESSIBLE
UPPER I BY INCIRECI"
128
801-1 1
7fH
lOWER
128
ONlY
ACCESSIILE
BYDlR:CT
AND INDIRECT
AIDlESSING
_ _--'
01...-_
FUNCTlQ\I
REGISI'ERS
BIT ADDRESSES Q..1F)
PSW~
}=AND
20H
11{
18H
I£GISI'ERS
1O{
lOH
ACCIJMU.A1OR
01{
00NTR0l.. BITS
TIMER
Sma< POINTER
(EIC)
lFH \
17H
OFH
OBH
OOf o
In
Figure 6 : Internal Data Memory.
I(
Brr-AOORESSA8LE SAI\CE
BI1S IN
BOH
lSPEaAL
2FI-I
4 BANKS OF
8 IEGISTERS
RO-R7
O1H t- IBlETIlAWE OF
srAO< POINTER
Figure 7: The Lower 128 Bytes of Internal RAM.
FFH
FFH
EOH
NO BIT-ADDRESSABLE
SPACES
BOH
AVAILABLE AS STACK
SPACE IN 8OC52/
83Cl 54 AND 83C154O
N:,C
··
··
REGISTER-MAPPED PORlS
PORT 3
·
PORT 2
ADRESSES THAT END IN
0,BOR9
ARE BIT-ADDRESSABLE
-PORTPlNS
- ACOJMUlAIOR
-PSW
NOT IMPLEMENTED
IN 8OC51
80H
Figure 8: The Upper 128 Bytes of Internal RAM.
90H
PORT 1
BOH
··
(ETC)
PORTO
Figure 9 : SFR Space.
Figure 9 gives a brief look at the Special Function Register (SFR) space. SFRs include the Port latches, timers,
peripheral controls, etc. These registers can only be accessed by direct addressing. In general, all MHS C51
microcontrollers have the same SFRs as the 80C51, and at the same addresses in SFR space. However, enhancements to the 80C51 have additional SFRs that are not present in the 80C51 , nor perhaps in other proliferation of the
family.
Sixteen addresses in SFR space are both byte-and bit-addressable. The bit-addressable SFRs are those whose ad-
THE MHS C51 INSTRUCTION SET
dress ends in 0, 8 or 9. The bit addresses in this area are 80H through FFH.
All members of the MHS C51 family execute the same instruction set. (except code A5H, skip opcode in MHS
C51/C52). The MHS C51 instruction set is optimized for 8-bit control applications. It provides a variety of fast addressing modes for accessing the internal RAM to facilitate byte operations on small data structures. The instruction
set provides extensive support for one-bit variables as a separate data type, allowing direct bit manipulation in control
and logic systems that require Boolean processing.
3-8
MHSC51
PSWO
PSW7
CARRY FLAG RECEIVES CARRY OUT
FROM BIT 1 OF ALU OPERANDS
~ITYOFMXUMU~RSIT
BY HARD'VIARE TO 1 IF IT CONlAINS
AN ODD NUMBER OF 1S. OfHERWISE
IT IS RESITTO 0
PSW6
AUXILIARY CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERANDS
PSW1
USER DEFINABLE FLAG
PSW5
GENERAL PURPOSE STATUS FLAG _ _ _--'
L -_ _ _
PSW4
REGISTER BANK SELECT BIT 1 _ _ _ _ _-'
PSW2
OVERFLOW FLAG SIT BY
ARITHMETIC OPERATIONS
PSW3
'--_ _ _ _ _ REGISTER BANK SELECfBITO
Figure 10 : PSW (Program Status Word) Register in MHS C51 Devices.
An overview of the MHS C51 instruction set is presented below, with a brief description of how certain instructions
might be used.
PROGRAM STATUS WORD
The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. The PSW,
shown in Figure 10, resides in SFR space. It contains the Carry bit, the Auxiliary Carry (for BCD operations), the two
register bank select bits, the Overflow flag, a parity bit, and two user-definable status flags.
The Carry bit, other than serving the functions of a Carry bit in arithmetic operations, also serves as the "Accumulator"
for a number of Boolean operations.
The bits RSO and RS1 are used to select one of the four register banks shown in Figure 7. A number of instructions
refer to these RAM locations as RO through R7. The selection of which of the four banks is being referred to is made
on the basis of the bits RSO and RS1 at execution time.
The parity bit reflects the number of 1 s in the Accumulator: P = 1 if the Accumulator contains an odd number of 1 s,
and P = 0 if the Accumulator contains an even number of 1 s. Thus the number of 1 s in the Accumulator plus P is
always even.
Two bits in the PSW are uncommitted and may be used as general purpose status flags.
ADDRESSING MODES
The addressing modes in the MHS C51 instruction set are as follows:
Direct addressing
In direct addressing the operand is specified by an 8-bit address field in the instruction. Only 128 Lowest bytes of
internal Data RAM and SFRs can be directly addressed.
Indirect addressing
In indirect addressing the instruction specifies a register which contains the address of the operand. Both internal
and external RAM can be indirectly addressed.
The address register for 8-bit addresses can be RO or R1 of the selected register bank, or the Stack Pointer.
The address register for 16-bit addresses can only be the 16-bit "data pointer" register, DPTR.
Register instructions
The register banks, containing registers RO through R7, can be accessed by certain instructions which carry a 3-bit
register specification within the opcode of the instruction. Instructions that access the registers this way are code efficient, since this mode eliminates an address byte. When the instruction is executed, one of the eight registers in
3-9
n
II)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ MHS C51
the selected bank is accessed. One of four banks is selected at execution time by the two bank select bits in the
PSW.
Register-specific instructions
Some instructions are specific to a certain register. For example, some instructions always operate on the Accumulator, or Data Pointer, etc., so no address byte is needed to point to it. The opcode itself does that. Instructions
that refer to the Accumulator as A assemble as accumulator-specific opcodes.
Immediate constants
The value of a constant can follow the opcode in Program Memory. For example,
MOV A, # 100
loads the Accumulator with the decimal number 100. The same number could be specified in hex digits as 64H.
Indexed addressing
Only Program Memory can be accessed with indexed addressing, and it can only be read. This addressing mode is
intended for reading look-up tables in Program Memory. A 16-bit base register (either DPTR or the Program Counter)
points to the base of the table, and the Accumulator is set up with the table entry number. The address of the table
entry in Program Memory is formed by adding the Accumulator data to the base pointer.
Another type of indexed addressing is used in the "case jump" instruction. In this case the destination address of a
jump instruction is computed as the sum of the base pointer and the Accumulator data.
ARITHMETIC INSTRUCTIONS
The menu of arithmetic instructions is listed in Table 2. The table indicates the addressing modes that can be used
with each instruction to access the operand. For example, the ADD A, instruction can be written as :
ADD A, 7FH
ADD A, @ RO
ADD A, R7
(direct addressing)
(indirect addressing)
(register addressing)
MNEMONIC
ADDRESSING
MODES
Dir Ind Reg Imm
X
X
X
X
OPERATION
A = A +
ADD A,
SUBB A,
A = A - - C
INCA
A=A+1
Accumulator only
INC
= + 1
X
INC DPTR
DPTR = DPTR + 1
Data Pointer only
DECA
A=A-l
Accumulator only
1
DEC
= - 1
X
1
A = A + + C
X
X
X
X
X
X
1
X
X
AD DC A,
X
X
EXECUTION TIME (Jls)
X
X
1
1
1
1
2
MULAB
B:A = B x A
ACC and B only
4
DIVAB
A = Int [AlB]
B = Mod [AlB]
ACC and B only
4
DAA
Decimal Adjust
Accumulator only
1
Table 2 : A list of the MHS C51 Arithmetic Instructions.
ADD A, # 127
(immediate constant)
The execution times listed in Table 2 assume a 12 MHz clock frequency. All of the arithmetic instructions execute in
1 Jls except the INC DPTR instruction, which takes 2 JlS, and the Multiply and Divide instructions, which take 4 Jls.
3-10
MHSC51
Note that any byte in the internal Data Memory space can be incremented or decremented without going through
the Accumulator.
One of the INC instructions operates on the 16-bit Data Pointer. The Data Pointer is used to generate 16-bit addresses
for external memory, so being able to increment it in one 16-bit operation is a useful feature.
The MUL AB instruction multiplies the Accumulator by the data in the B register and puts the 16-bit product into the
concatenated B and Accumulator registers.
The DIV AB instruction divides the Accumulator by the data in the B register and leaves the 8-bit quotient in the Accumulator, and the 8-bit remainder in the B register.
Oddly enough, DIV AB finds less use in arithmetic "divide" routines than in radix conversions and programmable shift
operations. An example of the use of DIV AB in a radix conversion will be given later. In shift operations, dividing a
number by 2n shifts its n bits to the right. Using DIV AB to periorm the division completes the shift in 4 Ils leaves the
B register holding the bits that were shifted out.
The DA A instruction is for BCD arithmetic operations. In BCD arithmetic ADD and ADDC instructions should always
be followed by a DA A operation, to ensure that the result is also in BDC. Note that DAA will not convert a binary
number to BCD. The DA A operation produces a meaningful result only as the second step in the addition of two
BCD bytes.
LOGICAL INSTRUCTIONS
Table 3 shows the list of MHS C51 logical instructions. The instructions that periorm Boolean operations (AND, OR,
Exclusive OR, NOT) on bytes periorm the operation on a bit-by-bit basis. That is, if the Accumulator contains
00110101 B and contains 01010011 B, then
ANL A,
will leave the Accumulator holding 00010001 B.
The addressing modes that can be used to access the operand are listed in Table 3. Thus, the ANL A,
instruction may take any of the forms.
MNEMONIC
ADDRESSING
MODES
OPERATION
Dir
Ind Reg Imm
EXECUTION
TIME (IlS)
CPL A
= A AND
= AND A
= AND # data
A = A OR
= OR A
= OR # data
A = A XOR
= XOR A
= XOR # data
A = OOH
A = NOT A
RL A
Rotate ACC Left 1 bit
Accumulator only
1
RLC A
Rotate Left through Carry
Accumulator only
1
ANL A,
ANL ,A
ANL , # data
ORL A,
ORL , A
ORL , # data
XRL A,
XRL ,A
XRL ,# data
CLR A
A
X
X
X
X
X
2
X
X
X
X
X
X
1
1
2
X
X
1
1
X
X
X
1
X
1
X
2
Accumulator only
1
Accumulator only
1
RRA
Rotate ACC Right 1 bit
Accumulator only
1
RRCA
Rotate Right through Carry
Accumulator only
1
SWAP A
Swap Nibbles in A
Accumulator only
1
Table 3 : A list of the MHS C51 Logical Instructions.
3-11
MHSC51
ANL A,7FH
ANL A,@R1
ANL A, R6
ANL A, #53H
(direct addressing)
(indirect addressing)
(register addressing)
(immediate constant)
All of the logical instructions that are Accumulator specific in 1 fls (using a 12 MHz clock). The others take 2 fls.
Note that Boolean operations can be performed on any byte in the internal Data Memory space without going through
the Accumulator. The XRL , # data instruction, for example, offers a quick and easy way to invert port bits, as
in
XRL P1, #OFFH
If the operation is in response to an interrupt, not using the Accumulator saves the time and effort to stack it in the
seNice routine.
The Rotate instructions (RLA, RLCA, etc.) shift the Accumulator 1 bit to the left or right. For a left rotation, the MSB
rolls into the LSB position. For a right rotation, the LSB rolls into the MSB position.
The SWAP A instruction interchanges the high and low nibbles within the Accumulator. this is a useful operation in
BCD manipulations. For example, if the Accumulator contains a binary number which is known to be less than 100,
it can be quickly converted to BCD by the following code:
MOV
DIV
SWAP
ADD
B, #10
AB
A
A,B
Dividing the number by 10 leaves the tens digit in the low nibble of the Accumulator, and the ones digit in the B register.
The SWAP and ADD instructions move the tens digit to the high nibble of the Accumulator, and the ones digit to the
low nibble.
DATA TRANSFERS
Internal RAM
Table 4 shows the menu of instructions that are available for moving data around within the internal memory spaces,
and the addressing modes that can be used with each one. With a 12 MHz clock, all of these instructions execute in
either 1 or 2 fls.
The MOV , instruction allows data to be transfered between any two internal RAM or SFR locations
without going through the Accumulator. Remember the Upper 128 bytes of data RAM can be accessed only by indirect, and SFR space only by direct addressing.
Note that in all MHS C51 devices, the stack resides in on-chip RAM, and grows upwards. The PUSH instruction first
increments the Stack Pointer (SP), then copies the byte into the stack. PUSH and POP use only direct addressing
to identify the byte being saved or restored, but the stack itself is accessed by indirect addressing using the SP register.
This means the stack can go into the Upper 128, if they are implemented, but not into SFR space.
The Upper 128 are not implemented in the 80C51, nor in their ROMless. With these devices, if the SP points to the
MNEMONIC
OPERATION
ADDRESSING
EXECUTION
MODES
TIME (flS)
Dir Ind Reg Imm
X
X
X
X
X
X
X
X
X
MOV DPTR,# data 16
=
= A
=
DPTR = 16-bit immediate constant
PUSH
INC SP : MOV"@SP",
X
MOV A,
MOV , A
MOV ,
A
X
1
X
2
1
X
POP
MOV , "@SP" : DEC SP
X
XCH A,
ACC and Exchange Data
X
XCHD A,@Ri
ACC and @ Ri exchange low nibbles
2
X
X
X
Table 4 : A list of the MHS C51 Data Transfer Instructions that Access Internal Data Memory Space.
3-12
2
2
1
1
MHSC51
Upper 128 PUSHed bytes are lost, and POPped bytes are indeterminate.
The Data Transfer instructions include a 16-bit MOV that can be used to initialize the Data Pointer (DPTR) for look-up
tables in Program Memory, or for 16-bit external Data Memory accesses.
The XCH A, instruction causes the Accumulator and addressed byte to exchange data.
The XCHD A, @ Ri instruction is similar, but only the low nibbles are involved in the exchange.
The see how XCH and XCHD can be used to facilitate data manipulations, consider first the problem of shifting an
8-digit BCD number two digits to the right. Figure 11 shows how this can be done using direct MOVs, and for com-
2A
MOV
MOV
MOV
MOV
MOV
A,2EH
2EH, 2DH
2DH, 2CH
2CH, 2BH
2BH, #0
00
00
00
00
00
2B
12
12
12
12
00
2C
34
34
34
12
12
20
56
56
34
34
34
2A 2B 2C 20 2E ACC
2E ACC
78
56
56
56
56
MOV R1,# 2EH
00 12
MOV RO,# 2DH
00 12
loop for R1 = 2EH :
LOOP: MOV A, @R1
00[12
XCHD A, @RO
00 12
SWAP A
00 12
MOV @R1, A
00 12
DEC R1
00 12
DEC RO
00 12
CJNE R1, #2AH, LOO
78
78
78
78
78
(a) Using direct MOVs : 14 bytes, 9 J.IS
CLR
XCH
XCH
XCH
XCH
A
A,2BH
A,2CH
A,2DH
A,2EH
2A
2B
2C
20
2E ACC
00
00
00
00
00
12
00
00
00
00
34
34
12
12
12
56
56
56
34
34
78
78
78
78
56
00
12
34
56
78
34 56 78 XX
34 56 78 XX
34 56
34 58
34 58
34 58
34 58
34 58
78
78
78
67
67
67
78
76
67
67
67
67
100pforR1 =2DH :100112138145167145
loop for R1 = 2CH : 00 18 23 45 67 23
loop for R1 = 2BH : 08 01 23 45 67 01
CLRA
XCH A,2AH
(b) Using XCHs : 9 bytes, 5 J.IS
108101123145167100
00 01 23 45 67 08
Figure 12 : Shifting a BCD Number One Digit to the
Right.
Figure 11 : Shifting a BCD Number Two Digits to the
Right.
parison how it can be done using XCH instructions. To aid in understanding how the code works, the contents of the
registers that are holding the BCD number and the content of the Accumulator are shown alongside each instruction
to indicate their status after the instruction has been executed.
After the routine has been executed, the Accumulator contains the two digits that were shifted out on the right. Doing
the routine with direct MOVs uses 14 code bytes and 9 !is of execution time (assuming a 12 MHz clock). The same
operation with XCHs uses less code and executes almost twice as fast.
To right-shift by an odd number of digits, a one-digit shift must be executed. Figure 12 shows a sample of code that
will right-shift a BCD number one digit, using the XCHD instruction. Again, the contents of the registers holding the
number and of the Accumulator are shown alongside each instruction.
First, pointers R1 and RO are set up to point to the two bytes containing the last four BCD digits. Then a loop is executed
which leaves the last byte, location 2EH, holding the last two digits of the shifted number. The pointers are decremented, and the loop is repeated for location 2DH. The CJNE instruction (Compare and Jump if Not Equal) is a loop
control that will be described later.
The loop is executed from LOOP to CJNE for R1 = 2EH, 2DH, 2CH and 2BH. At that point the digit that was originally
shifted out on the right has propagated to location 2AH. Since that location should be left with Os, the lost digit is moved
to the Accumulator.
External RAM
3-13
MHSC51
ADDRESS WIDTH
a bits
a bits
16 bits
16 bits
MNEMONIC
OPERATION
EXECUTION TIME (Ils)
MOVXA,@Ri
Read external
RAM@Ri
2
MOVX@Ri,A
Write external
RAM@Ri
2
MOVX A, @ DPTR
Read external
RAM@ DPTR
2
MOVX @ DPTR,A
Write external
RAM@ DPTR
2
Table 5: A list of the MHS C51 Data Transfer Instructions that Access Extemal Data Memory Space.
Table 5 shows a list of the Data Transfer instructions that access extemal Data Memory. Only indirect addressing
can be used. The choice is whether to use a one-byte address, @Ri, where Ri can be either RD or R1 of the selected
register bank, or a two-byte address, @DPTR. The disadvantage to using 16-bit addresses if only a few K bytes of
external RAM are involved is that 16-bit addresses use all a bits of Port 2 as address bus. On the other hand, a-bit
addresses allow one to address a few K bytes of RAM, as shown in Figure 5, without having to sacrifice all of Port 2.
In
All of these instructions execute in 2 !!S, with a 12 MHz clock.
Note that in all external Data RAM accesses, the Accumulator is always either the destination or source of the data.
The read and write strobes to extemal RAM are activated only during the execution of a MOVX instruction. Normally
these signals are inactive, and in fact if they're not going to be used at all, their pins are available as extra I/O lines.
More about that later.
MNEMONIC
OPERATION
EXECUTION
TIME (Ils)
MOVC A, @A + DPTR
Read pgm Memory at (A + DPTR)
2
MOVC A, @A + PC
Read Pgm Memory at (A + PC)
2
Table 6: The MHS C51 Lookup Table Read Instructions.
Lookup Tables
Table 6 shows the two instructions that are available for reading lookup tables in Program Memory. Since these instructions access only Program Memory, the lookup tables can be read, not updated. The mnemonic is MOVC for
"move constant".
If the table access is to external Program Memory, then the read strobe is PSEN.
The first MOVC instruction in Table 6 can accomodate a table of up to 256 entries, numbered D through 255. The
number of the desired entry is loaded into the Accumulator, and the Data Pointer is set up to point to beginning of
the table. Then
MOVC A, @A + DPTR
copies the desired table entry into the Accumulator.
The other MOVC instruction works the same way, except the Program Counter (PC) is used as the table base, and
the table is accesses through a subroutine. First the number of the desired entry is loaded into the Accumulator, and
the subroutine is called:
MOV
CALL
A, ENTRY NUMBER
TABLE -
The subroutine "TABLE" would look like this :
TABLE: MOVC A, @A + PC
RET
The table itself immediately follows the RET (return) instruction in Program Memory. This type of table can have up
to 255 entries, numbered 1 through 255. Number D can not be used, because at the time the MOVC instruction is
executed, the PC contains the address of the RET instruction. An entry numbered Dwould be the RET opcode itself.
BOOLEAN INSTRUCTIONS
3-14
MHSC51
MHS C51 devices contain a complete Boolean (single-bit) processor. The internal RAM contains 128 addressable
bits, and the SFR space can support up to 128 other addressable bits. All of the port lines are bit-addressable, and
each one can be treated as a separate single-bit port. The instructions that access these bits are not just conditional
branches, but a complete menu of move, set, clear, complement, OR and AND instructions. These kinds of bit operations are not easily obtained in other architectures with any amount of byte-oriented software.
The instruction set for the Boolean processor is shown in Table 7. All bit accesses are by direct addressing. Bit addresses OOH through 7FH are in the Lower 128, and bit addresses 80H through FFH are in SFR space.
OPERATION
MNEMONIC
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit
MOV C,bit
MOV bit,C
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
JC rei
JNC rei
JB bit,rel
JNB bit,rel
JBC bit,rel
C = C AND bit
C = C AND (NOT bit)
C = C OR bit
C = C OR (NOT bit)
C = bit
bit = C
C=O
bit = 0
C= 1
bit = 1
C = NOTC
bit = NOT bit
Jump if C = 1
Jump if C = 0
Jump if bit = 1
Jump if bit = 0
Jump if bit = 1 ; CLR bit
EXECUTION TIME
(J.ls)
2
2
2
2
1
2
1
1
1
1
1
1
2
2
2
2
2
Table 7 : A list of the MHS C51 Boolean Instructions.
Note how easily an internal flag can be moved to a port pin:
MOV
MOV
C, FLAG
P1.0, C
In this example, FLAG is the name of any addressable bit in the lower 128 or SFR space. An I/O line (the LSB of
Port 1, in the case) is set or cleared depending on whether the flag bit is 1 or O.
The Carry bit in the PSW is used as the single-bit Accumulator of the Boolean processor. Bit instructions that refer
to the Carry bit as C assemble as Carry-specific instructions (CLR C, etc). The Carry bit also has a direct address,
since it resides in the PSW register, which is bit-addressable.
Note that the Boolean instruction set includes ANL and ORL operations, but not the XRL (Exclusive OR) operation.
An XRL operation is simple to implement in software. Suppose, for example, it is required to form the Exclusive OR
of two bits:
C bit1 XRL bit2
The software to do that could be as follows:
MOV
JNB
CPL
C, bit1
bit2, OVER
C
OVER: (continue)
First, bit 1 is moved to the Carry. If bit 2 = 0, then C now contains the correct result. That is, bit 1 XRL bit2 = bit1 if
bit2 = O. On the other hand, if bit2 = 1 C now contains the complement of the correct result. It need only be inverted
(CPL C) to complete the operation.
This code uses the JNB instruction, one of a series of bit-test instructions which execute a jump if the addressed bit
3-15
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ MHS C51
is set (JC, JB, JBC) or if the addressed bit is not set (JNC, JNB). In the above case, bit2 is being tested, and if bit2 = 0
the CPL C instruction is jumped over.
JBC executes the jump if the addresed bit is set, and also clears the bit. Thus a flag can be tested and cleared in
one operation.
All the PSW bits are directly addressable, so the Parity bit, or the general purpose flags, for example, are also available
to the bit-test instructions.
Relative offset
The destination address for these jumps is specified to the assembler by a label or by an actual address in Program
MNEMONIC
JMP addr
JMP@A+ DPTR
CALL addr
RET
RETI
NOP
OPERATION
Jump to addr
Jump to A + DPTR
Call subroutine at addr
Return from subroutine
Return from interrupt
No operation
EXECUTION
TIME (I1S)
2
2
2
2
2
1
Table 8 : Unconditional Jumps in MHS C51.
Memory. However, the destination address assembles to a relative offset byte. This is a signed (two's complement)
offset byte which is added to the PC in two's complement arithmetic if the jump is executed.
The range of the jump is therefore - 128 to + 127 Program Memory bytes relative to the first byte following the instruction.
JUMP INSTRUCTIONS
Table 8 shows the list of unconditional jumps.
The table lists a single "JMP addr" instruction, but in fact there are three - SJMP, LJMP, AJMP - which differ in the
format of the destination address. JMP is a generic mnemonic which can be used if the programmer does not care
which way the jump is encoded.
The SJMP instruction encodes the destination address as relative offset, as described above. The instruction is 2
bytes long, consisting of the opcode and the relative offset byte. The jump distance is limited to range of - 128 to
In all cases the programmer specifies the destination address to the assembler in the same way: as a label or as a
16-bit constant. the assembler will put the destination address into the correct format for the given instruction. If the
format required by the instruction will not support the distance to the specified destination address, a "Destination
out of range" message is written, into the list file.
The JMP @ A + DPTR instruction supports case jumps. The destination address is computed at execution time as
the sum of the 16-bit DPTR register and the Accumulator. Typically, DPTR is set up with the address of a jump table,
and the Accumulator is given an index to the table. In a 5-way branch, for example, an integer 0 through 4 is loaded
into the Accumulator.
The code to be executed might be as follows:
MOV
MOV
RL
JMP
DPTR, # JUMP_TABLE
A, INDEX_NUMBER
A
@A+DPTR
The RLA instruction converts the index number (0 through 4) to an even number on the range 0 through 8, because
each entry in the jump table is 2 bytes long:
JUMP TABLE:
AJMP CASE_O
AJMP CASE_1
AJMPCASE_2
AJMPCASE_3
AJMPCASE_4
3-16
-
_ _ _ _ _ _ _ _ _ _ _ _ _ _ MHS C51
Table 8 shows a single "CALLaddr" instruction, but there are two of them - LCALL and ACALL - which differ in the
format in which the subroutine address is given to the CPU. CALL is a generic mnemonic which can be used if the
programmer does not care which way the address is encoded.
The LCALL instruction uses the 16-bit address format, and the subroutine can be anywhere in the 64K Program
Memory space. The ACALL instruction uses the 11-bit format, and the subroutine must be in the same 2K block as
the instructon following the ACALL.
In any case the programmer specifies the subroutine address to the assembler in the same way: as a label or as a
16-bit constant. The assembler will put the address into the correct format for the given instructions.
Subroutines should end a RET instruction, which returns execution following the CALL.
RETI is used to return from an interrupt service routine. The only difference between RET and RET I is that RETI tells
the interrupt control system that the interrupt in progress is done. If there is no interrupt in progress at the time RETI
is executed, then the RETI is functionnally identical to RET.
Table 9 shows the list of conditional jumps available to the MHS C51 user. All of these jumps specify the destination
address by the relative offset method, and so are limited to a jump distance of - 128 to + 127 bytes from the instruction
following the conditional jump instruction. Important to note, however, the user specifies to the assembler the actual
destination address the same way as the other jumps: as a label or a 16-bit constant.
MNEMONIC
ADDRESSING
MODES
OPERATION
EXECUTION TIME (J.Ls)
DIR IND REG IMM
JZ rei
Jump if A
=0
Accumulator only
2
JNZ rei
Jump if A *0
Accumulator only
2
DJNZ ,rel
Decrement and jump if not
zero
X
2
CJNE A,,rel
Jump if A
CJNE ,#data, rei
Jump
=
if = #data
X
X
X
X
X
2
2
Table 9: Conditional Jumps in MHS C51 Devices.
There is no Zero bit in the PSW. The JZ and JNZ instructions test the Accumulator data for that condition.
The DJNZ instruction (Decrement and Jump if Not Zero) is for loop control. To execute a loop N times, load a counter
byte with N and terminate the loop with DJNZ to the beginning of the loop, as shown below for N = 10 :
LOOP:
MOV
(begin loop)
COUNTER, # 10
*
(end loop)
DJNZ
(continue)
COUNTER, LOOP
The CJNE instruction (Compare and Jump if Not Equal) can also be used for loop control as in Figure 12. Two bytes
are specified in the operand field of the instruction. The jump is executed only if the two bytes are not equal. In the
example of Figure 12, the two bytes were the data in R1 and the constant 2AH. The initial data in R1 was 2EH. Every
time the loop was executed, R1 was decremented, and the looping was to continue until the R1 data reached 2AH.
Another application of this instruction is in "greater than, less than" comparisons. The two bytes in the operand field
are taken as unsigned integers. If the first is less than the second, then the Carry bit is set (1). If the first is greater
than or equal to the second, then the Carry bit is cleared.
CPU TIMING
All MHS C51 microcontrollers have an on-chip oscillator which can be used if desired as the clock source for the CPU.
To use the on-chip oscillator, connect a crystal or ceramic resonator between the XTAL 1 and XTAL2 pins of the
microcontroller, and capacitors to ground as shown in Figure 13.
3-17
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ MHS C51
XTAL.2
QUARTZCRVSW..1 C1
ORCERAMIC
RESONAlOR
0
T
MHSC51
-
FAMILY
C2
XTALl
~
\ISS
-=
Figure 13 : Using the On-Chip Oscillator.
Examples of how to drive the clock with an external oscillator are shown in Figure 14. In the MHS C51 devices the
signal at the XTAL 1 pin drives the internal clock generator. If only one pin is going to be driven with the external oscillator signal, make sure it is the right pin.
The internal clock generator defines the sequence of states that make up the MHS C51 machine cycle.
XTA1..2
(NC)
EXTERNAL
EXTERNAL
SIGNAL
SIGNAL
a.oa<-~~XTAL1
ClOCK
VSS
MHSC51
XTA1..2
XTALl
VSS
MHSC51
Figure 14: Using an External Clock.
MACHINE CYCLES
A machine cycle consists of a sequence of 6 states, numbered Sl through S6. Each state time lasts for two oscillator
periods. Thus a machine cycle takes 12 oscillator periods or 1 I1S if the oscillator frequency is 12 MHz.
Each state is divided into a Phase 1 half and a Phase 2 half. Figure 15 shows the fetch/execute sequences in states
and phases for various kinds of instructions. Normally two program fetches are generated during each machine cycle,
even if the instruction being executed doesn't require it. If the instruction being executed doesn't need more code
bytes, the CPU simply ignores the extra fetch, and the Program Counter is not incremented.
3-18
MHSC51
Execution of a one-cycle instruction (Figure 15A and B) begins during State 1 of the machine cycle, when the opcode
is latched into the Instruction Register. A second fetch occurs during S4 of the same machine cycle. Execution is
completed at the end of State 6 of this machine cycle.
The MOVX instructions take two machine cycles to execute. No program fetch is generated during the second cycle
of a MOVX instruction. This is the only time program fetches are skipped. The fetch/execute sequence for MOVX
instructions is shown in Figure 15 (0).
The fetch/execute sequences are the same whether the Program Memory is internal or external to the chip. Execution
times do not depend on whether the Program Memory is internal or external.
osc
I
~I~I~I~I~I$I~I~I~IMI~I$I~I
PI P2 PI P2 P1 P2 PI P2 PI P2 PI P2 PI P2 PI P2 PI P2 PI P2 PI P2 PI P2 PI P2
(XTAL2)
fEtID OPCOOE.
------------.,..-1-,.---r---.--1--.--""T--.. __[_'::' NEXT QPC()[E AGAIN.
----_______ ......._ . . L - _.....---I'---...L_-A.._~,
,
I
I
(A) 1-byte,1-cycIe instruction. e.g., INC A-
,I
I
I
I
I
,
I
:
:
FEAD OPCOOE.
I
I
[_~
--,--r---r-...L-r---,.--; __
_ _ _ _ _ _ _ _ _ _ _ _ j-i.......
NEXT
~
-------------t:-~--L--....&..--~-.;...&....~
(8) 2-byte, l-cyde insIrucIion, e.g., ADD A. fdata
FEAD OPCODE.
FEADNEXT
OPCOOE (D1SCARD).
------------f---:l':-r-,...--,--1.-,--r---+--,...--,--,-..1.-r--r-,
(C) l-byte, 2~ 11sIruction, e.g.. INC DPTR
FEADOPCOOE
(MOVX).
AEAONEXT
OPCOOE (DISCAfI)
-----------..L,_....._ ........_ ......._~-.&.....,.--I~--'-~--L-_......--'----',
(D) MOVX (1 :lIYte, 2-qde)
DATA
ACCESS EXTERNAl... MEMOR'f
Figure 15: State Sequences in MHS C51.
3-19
)
MHSC51
Figure 16 shows the signals and timing involved in program fetches when the Program Memory is external. If Program
Memory is external, then, the Program Memory read strobe PSEN is normally activated twice per machine cycle, as
shown in Figure 16 (A).
If an access to external Data Memory occurs, as shown in Figure 16 (B), two PSENs are skipped, because the address
and data bus are being used for the Data Memory access.
r--
ONE MAa-lI/IE CYa.E - - , - ONE MACHINE CYa.E - - - - ,
I 51 I 52 I 53 I 54 I 55 I 56 I 51 I 52 I 53 I 54 I 55 I 56 I
ALE
PSEN
(A)
RD------~--------~----------~--------~-------------- WITHOUT A
MOVX.
FO
I
I
t
f
f
PQ.our
PQ.our
PCLOUT
VALID
VAUD
VAUO
~CYaEl
51
f
PQ.our
VALl)
CYQE2~
I 53 154 155 I 56'!' 51 152 153 1 54 155156
152
ALE
L-J
I
PCHOUT
(8)
WITH A
MOVX.
PCHOUT
DPH OUT OR P2 OUT
PO
t
t
t
PCLOUT
AODROUT
VAlID
PQ.OUT
VALID
VAUD
Figure 16: Bus Cycles in MHS C51 Devices Executing from External Program Memory.
Note that a Data Memory bus cycle takes twice as much time as a Program Memory bus cycle. Figure 16 shows the
relative timing of the addresses being emitted at ports 0 and 2, and of ALE and PSEN. ALE is used to latch the low
address byte from PO into the address latch.
When the CPU is executing from internal Program Memory, PSEN is not activated, and program addresses are not
emitted. However, ALE continues to be activated twice per machine cycle and so is available as a clock output signal.
Note, however, that one ALE is skipped during the execution of the MOVX instruction.
3-20
MHSC51
INTERRUPT STRUCTURE
The 80C51 and his ROMless version provide 5 interrupt sources: 2 external interrupts, 2 timer interrupts, and the
serial port interrupt. the 80C52, 83C 154 and 83C154D and their ROM less v!3rsion provide these 5 plus a sixth interrupt
that is associated with the third timer/counter which is present in those devices.
What follows is an overview of the interrupt structure for these devices. More detailed information for specific members
of the MHS C51 family is provided in the chapters of this handbook that describe the specific devices.
Interrupt Enables
Each of the interrupt source can be individually enabled or disabled by setting or clearing a bit in the SFR named IE
(Interrupt Enable). This register also contains a global disable bit, which can be cleared to disable all interrupts at
once. Figure 1? shows the IE register for the 80C52 and 83C154 or the 83C154D.
(MSB)
I
EA
Symbol
EA
Position
IE.?
ET2
IE.6
IE.5
ES
IE.4
ET1
IE.3
EX1
ETO
IE.2
IE.1
EXO
IE.O
(LSB)
x
ET2
ES
ET1
EX1
ETO
EXO
I
Function
disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1 ,each interrupt source is individually enabled or disabled by setting or clearing its enable bit.
reserved
enables or disables the Timer 2 overflow or capture interrupt. If ET2 = 0, the Timer 2
interrupt is disabled.
enables or disables the Serial Port interrupt. If ES = 0, the Serial Port interrupt is disabled.
enables or disables the Timer 1 Overflow interrupt. If ET1 = 0, the Timer 1 interrupt is
disabled.
enables or disables External Interrupt 1. If EX1 = 0, External Interrupt 1 is disabled.
enables or disables the Timer 0 Overflow interrupt. If ETO = 0, the Timer 0 interrupt is
disabled.
enables or disables External Interrupt O. If EXO = 0, External Interrupt 0 is disabled.
Figure 17 : IE (Interrupt Enable) Register in the 80C52, 83C154 and 83C154D.
(MSB)
I
PCT
Symbol
PCT
Position
IP.?
PT2
IP.6
IP.5
PS
IP.4
PT1
IP.3
PX1
IP.2
PTO
IP.1
PXO
IP.O
(LSB)
x
PT2
PS
PT1
PX1
PTO
PXO
I
Function
83C154/C154D only.
Priority interrupt circuit control bit.
The priority register contents are valid and priority assigned interrupts can be
processed when this bit is "0". When the bit is "1 ", the priority interrupt circuit is stopped,
and interrupts can only be controlled by the interrupt enable register (IE).
reserved
defines the Timer 2 interrupt priority level. PT2 = 1 programs it to the higher priority
level.
defines the Serial Port interrupt priority level. PS = 1 programs it to the higher priority
level.
defines the Timer 1 interrupt priority level. PT1 = 1 programs it to the higher priority
level.
defines the External Interrupt 1 priority level. PX1 = 1 programs it to the higher priority
level.
defines the Timer 0 interrupt priority level. PTO = 1 programs it to the higher priority
level.
defines the External Interrupt 0 priority level. PXO = 1 programs it to the higher priority
level.
Figure 18 : IP (Interrupt Priority) Register in the 80C52, 83C154 and 83C154D.
3-21
MHSC51
Interrupt priorities
Each interrupt source can also be individually programmed to one of two priority level by setting or clearing a bit in
the SFR named IP (Interrupt Priority). Figure 18 shows the IP register in the 80C52, 83C154 and 83C154D.
A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another low-priority interrupt.
A high-priority interrupt can't be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is
serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Figure 19 shows, for the 80C52, 83C154 and 83C154D, how the IE and IP registers and the polling sequence work
to determine which interrupt will be serviced.
, -_ _ _-+
PREGISI'ER
no----______
~~~
HIGH PRIORITY
INTEIRJPT
INTERRUPT
POWNG
SEQUENCE
TA------------~~y
~c>_+-_+__o._
I
:
G-+---~~~
I
I
I
I
FI
11
>-----------4-~ ~o-.---~~~
:
~_r----~~
I
I
I
I
1F2
EXF2
I
>----~_cY' ~o-t---+-~
:
~~----~~
I
I
NlIVDJAl
ENAEILES
LGlDBAL
DISABlE
LOWPRIORJTY
INT13R.IPT
Figure 19: 80C52, 83C154 and 83C154D Interrupt Control System.
In operation, all the interrupt flags are latched into the interrupts control system during State 5 of every machine cycle.
The samples are polled during the following machine cycle. If the flag for an enabled interrupt is found to be set (1),
the interrupt system generates an LCALL to the appropriate location in Program Memory, unless some other condition
blocks the interrupt. Several conditions can block an interrupt, among them that an interrupt of equal or higher priority
level is already in progress.
The hardware-generated LCALL causes the contents of the Program Counter to be pushed onto the stack, and
reloads the PC with the beginning address of the service routine. As previously noted (Figure 3), the service routine
for each interrupt begins at a fixed location.
Only the Program Counter is automatically pushed onto that stack, not the PSW or any other register. Having only
the PC be automatically saved allows the programmer to decide how much time to spend saving which otherregisters.
This enhances the interrupt response time, albeit at the expense of increasing the programmer's burden of responsability. As a result, many interrupt functions that are typical in control applications-toggling a port pin, for example,
3-22
MHSC51
or reloading a timer, or unloading a serial buffer can often be completed in less time than it takes other architectures
to commence them.
Simulating a third priority level in software
Some applications require more than the two priority levels that are provided by on-chip hardware in MHS C51 devices.
In these cases, relatively simple software can be written to produce the same effect as a third priority level. First,
interrupts that are to have higher priority than 1 are assigned to priority 1 in the IP (Interrupt Priority) register. The
service routines for priority 1 interrupts that are supposed to be interruptible by "priority 2" interrupts are written to
include the following code :
PUSH
IE
MOV
IE, # MASK
CALL
LABEL
(execute service routine)
********
POP
IE
RET
RETI
LABEL:
As soon as any priority 1 interrupt is acknowledged, the IE (Interrupt Enable) register is redefined so as to disable all
but "priority 2" interrupts. Then, a CALL to LABEL executes the RETI instruction, which clears the priority 1 interruptin-progress flip-flop. At this point any priority 1 interrupt that is enabled can be serviced, but only "priority 2" interrupts
are enabled.
POPping IE restores the original enable byte. Then a normal RET (rather than another RETI) is used to terminate
the service routine. The additional software adds 10 j.lS (at 12 MHz) to priority 1 interrupts.
3-23
HARDWARE
DESCRIPTION OF THE II
80C51 , 80C52
and 83C154/C154D
L - - -_ _ _ _
4-1
~'1iiMlS
HARDWARE DESCRIPTION
OF THE 80C51 80C52, 83C154/C154D
INTRODUCTION
This chapter presents a comprehensive description of the on-chip hardware features of the MHS C51 microcontrollers.
Included in this description are
• The port drivers and how they function both as ports and, for Ports 0 and 2, in bus operations
• The Timer/Counters
• The serial Interface
• The Interrupt System
• Reset
• The Reduced Power Modes
POO-P07
,
~--------------~~H~l~-r±r
vee'
---1
VSS ,
....c;
SCON
TMOO
TCON
PSEN
AlE
Ell
RSt
,,L-__-'--'
,,
,,
~S
XTAL 1
XTAl2
~
t~r-----I·P;;'0·_;;P17-T+
P30-P37
• 80C52. 83C154 and 83C1540 only.
Figure 1 : MHS C51 Architectural Block Diagram.
4-3
MATRA MHS
- -____________________________ MHSC51
DEVICE
NAME
ROMLESS
VERSION
ROM
BYTES
80C51
80C31
4K
80C52
80C32
8K
83C154
80C154
16K
83C1540
80C154
32K
RAM
BYTES
16-BIT
TIMERS
PROCESS
TYPE
128
2
CMOS
256
3
CMOS
256
3'
CMOS
256
3*
CMOS
• included watch dog and Timer 32 bits.
Table 1 : The MHS C51 Family of Microcontrollers.
The devices under consideration are listed in Table 1. As it becomes unwieldy to be constantly referring to each of
these devices by their individual names, we will adopt a convention of refering to them generically as 80C51 s, 80C52s
and 83C154s, unless a specific member of the group is being refered to, in which case it will be specifically named.
The 80C51s include the 80C51 and 80C31. The 80C52s are the 80C52 and 80C32. The 83C154s are the 83C154,
the 80C154 and the 83C1540.
Figure 1 shows a functional block diagram of the 80C51 s, 80C52s and 83C154s.
Special Function Registers
A map of the on-chip memory area called SFR (Special Function Register) space is shown in Figure 2. SFRs marked
by parentheses are resident in the 80C52s and 83C154s but not in the 80C51 s. IOCON marked by a star is only
resident in the 83C154s.
D
Note that not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have no effect.
8 Bytes
F8
*IOCON
FO
B
FF
F7
E8
EO
EF
E7
ACC
08
OF
DO
PSW
C8
(T2CON)
07
(RCAP2L) (RCAP2H)
(TL2)
(TH2)
CF
C7
CO
B8
IP
BO
P3
B7
A8
IE
AF
BF
AO
P2
98
90
SCON
88
TCON
TMOO
TLO
TL1
80
PO
SP
OPL
OPH
A7
SBUF
9F
97
P1
THO
TH1
8F
PCON
87
• 83C154s only.
Figure 2: SFR Map. ( ... ) Indicates Resident in 80C52s and 83C154s, not in 80C51s.
User software should not write 1 s to these unimplemented locations, since they may be used in future MHS C51
products to invoke new features. In that case the reset or inactive values of the new bits will always be 0, and their
active values will be 1.
The functions of the SFRs are outlined below.
----------------------------__ MHSC51
Accumulator
ACC is the Accumulator register. The mnemonics for Accumalator-Specific instructions, however, refer to the Accumulator simply as A.
B Register
The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch
pad register.
Program Status Word
The PSW register contains program status information as detailed in Figure 3.
(MSB)
I
CY
Symbol
Position
CY
PSW.7
AC
PSW.6
(LSB)
AC
FO
RS1
ov
RSO
Function
F1
P
I
Symbol
Position
Carry flag
OV
PSW.2
Overflow flag.
Auxiliary Carry flag. (For
BCD operations).
F1
PSW.1
User definable flag.
P
PSW.O
Parity flag.
Set/Cleared by hardware
each instruction cycle to indicate an odd/even number
of "one" bits in the Accumulator, i.e., even parity.
FO
PSW.5
Flag 0 (Available to the user
for general purposes).
RS1
PSW.4
Register bank select
RSO
PSW.3
Control bits 1 & o. Set/
cleared by software to
determine working register
bank (see Note).
Function
Note:
The contents of (RS1, RSO) enable the working
register banks as follows:
(O.O)-Bank 0
(0.1 )-Bank 1
(1.0)-Bank 2
(1.1)-Bank3
(OOH-07H)
(08H-OFH)
(10H-17H)
(18H-1FH)
Figure 3 : Program Status Word Register.
Stack Pointer
The Stack Pointer Register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions.
While the stack may reside anywhere in on-chip RAM, the Stack Pointer is initialized to 07H after a reset. This causes
the stack to begin at location 08H.
Data Pointer
The Data Pointer (DPTR) consists of a high byte (DPH) and low byte (DPL). Its intented function is to hold a 16-bit
address. It may be manipulated as a 16-bit register or as two independent 8-bit registers.
Ports 0 to 3
PO, P1, P2 and P3 are the SFR latches of Ports 0, 1, 2 and 3, respectively.
Serial Data Buffer
The Serial Data Buffer is actually two separate registers, a transmit buffer and a receive buffer register. When data
is moved to SBUF, it goes to the transmit buffer where it is held for serial transmission. (Moving a byte to SBUF is
what initiates the transmission). When data is moved from SBUF, it comes from the receive buffer.
Timer Registers
Register pairs (THO, TLO), (TH1, TL 1), and (TH2, TL2) are the 16-bit counting registers for Timer/Counters 0, 1, and
2, respectively.
4-5
MHSC51
Capture Registers
The register pair (RCAP2H, RCAP2L) are the Capture registers for the Timer 2 "Capture Mode". In this mode, in response to a transition at the 8052s' and 83C154s' T2EX pin, TH2 and TL2 are copied into RCAP2H and RCAP2L.
Timer 2 also has a 16-bit auto-reload mode, and RCAP2H and RCAP2L hold the reload value for this mode. More
details about Timer 2's features are in a later section.
Control Registers
Special Function registers IP, IE, TMOD, TCON, T2CON, SCON, 10CON and PCON contain control and status bits
for the interrupt system, the Timer/Counters, and the serial port. they are described in later sections.
PORT STRUCTURES AND OPERATION
All four ports in the MHS C51 family are bidirectional. Each consists of a latch (Special Function Registers PO through
P3), an output driver and an input buffer.
The output drivers of Ports 0 and 2, and the input buffers of Port 0, are used in accesses to external memory. In this
application, Port 0 outputs the low byte of the external memory address, time-multiplexed with the byte being written
or read. Port 2 outputs the high byte of the external memory address when the address is 16-bits wide. Otherwise
the Port 2 pins continue to emit the P2 SFR content.
All the Port 3 pins, and (in the 80C52, 83C154 and 83C154D) two Port 1 pins are multifunctional. They are not only
port pins, but also serve the functions of various special features as listed below.
Port Pin
Alternate Function
*P1.0
*P1.1
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
T2 (Timer/Counter 2 external input)
T2EX (Timer/Counter 2 capture/Reload trigger)
RDX (serial input port)
TDX (serial output port)
INTO (external interrupt)
INT1 (external interrupt)
TO (Timer/Counter 0 external input)
T1 (Timer/Counter 1 external input)
WR (external Data Memory write strobe)
RD (external Data Memory read strobe)
*P1 .0 and P1.1 serve the alternate functions only on the 80C52s and 83C154s.
The alternate functions can only be activated if the corresponding bit latch in the port SFR contains a 1 . Otherwise
the port pin is stuck at O.
I/O Configurations
Figure 4 shows a functional diagram of a typical bit latch and I/O buffer in each of the four ports. The bit latch (one
bit in the port's SFR) is represented as a type D flip-flop, which will clock in a value from the internal bus in response
to a "write to latch" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a
"read latch" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a "read
pin" signal from the CPU. Some instructions that read a port activate the "read latch" signal, and others activate the
"read pin" signal. More about that later.
As shown in Figure 4, the output drivers of Ports 0 and 2 are switchable to an internal ADDR and AD DR/DATA bus
by an internal CONTROL signal for use in external memory accesses. During external memory accesses, the P2
SFR remains unchanged, but the PO SFR gets 1 s written to it.
Also shown in Figure 4, is that if a P3 bit latch contains a 1, then the output level is controlled by the signal labeled
"alternate output function". The actual P3.X pin level is always available to the pin's alternate input function, if any.
Ports 1, 2, and 3 have internal pullups. Port 0 has open drain outputs. Each I/O line can be independently used as
an input or an output. (Ports 0 and 2 may not be used as general purpose I/O when being used as the ADDR/DATA
BUS). To be used as an input, the port bit latch must contain a 1, which turns off the output driver FET. Then, for
Ports 1, 2, and 3, the pin is pulled high by the internal pullup, but can be pulled low by an external source.
Port 0 differs in not having internal pullups. The pullup FET in the PO output driver (see Figure 4) is used only when
the Port is emitting 1 s during external memory accesses. Otherwise the pullup FET is off. Consequently PO lines
that are being uses as output port lines are open drain. Writting a 1 to be bit latch leaves both output FETs off, so
the pin floats. In that condition it can be used a high-impedance input.
4·6
______________________________ MHSC51
READ _ _--,
tATai
R9D _ _..I
PIN
READ
PIN - - - '
A Part 0 lit
READ _ _--.
A\15lIIWE
OUTPUT
FUNCT10N
Vee
LAlt:H
INtBUS
WRITE
10
1IIlIUS _ _.....
WfITE
LAlt:H
10 .I-e:.~
I.ROt
All'ERNIQ'E
INPUT
fU\ICOON
D.Part 3 BIt
Figure 4 : MHS C51 FAMILY Port Bit Latches and 1/0 Buffers .
• See Figure 5 for details of the intemal pullup.
Because Ports 1, 2 and 3 have fixed intemal pullups they are sometimes called "quasi-bidirectional" ports. When configured as inputs they pull high and will source current (ilL, in the data sheets) when extemally pulled low. Port 0, on
the other hand, is considered "true" bidirectional, because when configurated as an input it floats.
All the port latches in the MHS C51 FAMILY have 1 s written to them by the reset function. If a 0 is subsequently
written to a port latch, it can be reconfigured as an input by writting a 1 to it.
Writing to a Port
In the execution of an instruction that changes the value in a port latch, the new value arrives at the latch during S6P2
olthe final cycle olthe instruction. However, port latches are in fact sampled by their output buffers only during Phase 1
of any clock period. (During Phase 2 the output buffer holds the value it saw during the previous Phase 1.) Consequently, the new value in the port latch won't actually appear at the output pin until the next Phase 1, which will be
at S1 P1 of the next machine cycle.
If the change requires a O-to-1 transition in Port 1,2, or 3, an additional pullup is tumed on during S1 P1 and S1 P2
of the cycle in which the transition occurs. This is done to increase the transition speed. The extra pull up can source
about 100 times the current that the normal pullup can. It should be noted that the intemal pullups are field-effect
transistors, not linear resistors. The pullup arrangements are shown in Figure 5.
In the MHS C51 family, the pullup consists of three pFETs. It should be noted that an n-channel FET (nFET) is tumed
on when a logical 1 is applied to its gate, and is tumed off when a logical 0 is applied to its gate. A p-channel FET
(pFET) is the opposite: it is on when its gate sees a 0, and off when its gate sees a 1.
4-7
MHSC51
Vee
Vee
Vee
2 OSC. PERIODS
(}
FROM PORT
LATCH
INPUT <=1--0< I - -......C !-_ _oJ
DAlA
READ
PORT PIN
pFET 1 is turned on for 2 osc. periods after Q makes a 1-to-0 transition. During this time, pFET 1 also turns on
pFET 3 through the inverter to form a latch which holds the 1.pFET 2 is also on.
Figure 5 : Port 1 and Internal Pullup Configurations. Port 2 is Similar Except That It Holds The Strong Pullup On
While Emitting 1 s That Are Address Bits. (See Text, "Accessing External Memory".)
111
pFET 1 in Figure 5 is the transistor that is turned on for 2 oscillator periods after a 0-to-1 transition in the port latch.
While it's on, it turns on pFET3 (a weak pullup), through the inverter. This inverter and pFET from a latch which hold
the 1.
Note that if the pin is emitting a 1, a negative glitch on the pin from some external source can turn off pFET3, causing
the pin to go into a float state. pFET2 is a very weak pullup which is on whenever the nFET is off, in traditional CMOS
style. It's only about 1/10 the strength of pFET3. Its function is to restore a 1 to the pin in the event the pin had a 1
and lost it to a glitch.
Port Loading and Interfacing
The output buffer of Ports 1, 2, and 3 can each drive 3LS TTL inputs. The pins can be driven by open-collector and
open-drain outputs, but note that 0-to-1 transitions will not be fast. In the CMOS device, an input 0 turns off pullup
pFET3, leaving only the very weak pullup pFET2 to drive the transition.
Port 0 output buffers can each drive 8 LS TTL inputs. They do, however, require external pullups to drive NMOS inputs,
except when being used as the ADDRESS/DATA bus.
83C154 and 83C154D I/O Configurations
The structure and behaviour ofthe 83C154s' ports P1, P2 and P3 are indentical to those of the 80C52. Only the control
block for the different pullups and pulldowns has been changed. The pullup resistance value can be programmed by
means of the 10CON register.
There are three possible values:
- three states (P1, P2, P3 and N are OFF).
- high impedance (100 kQ, P2 = ON),
-low impedance (10 kQ, P3 = ON).
Figure 6 is a functional diagram of the PORT.
4-8
----------------------------__ MHSC51
vee
a.--+---------1------~
POAlF---.. .
PnHZ _---.'--'
~~--~~~----------~--------------------~
vss
Figure 6 : PORTS 1 and 3 internal pullup configurations. PORT 2 is similar except that it holds the strong pullup on
while emitting 1 s that are address bits.
Read-Modify-Write Feature
Somes instructions that read a port read the latch and others read the pin. Which ones do what? The instructions
that read the latch rather than the pin are the ones that read value, possibly change it, and then rewrite it to the latch.
These are called "read-modify-write" instructions. The instructions listed below are read-modify-write instructions.
When the destination operand is a port, or a port bit, these instructions read the latch rather than the pin:
ANL
ORL
XRL
JBC
CPL
INC
DEC
DJNZ
MOV PX.Y,C
CLR PX.Y
SET PX.Y
(logical AND, e.g., ANL P1, A)
(logical OR, e.g., ORL P2, A)
(logical EX-OR, e.g., XRL P3, A)
(jump if bit = 1 and clear bit, e.g., JBC P1.1 , LABEL)
(complement bit, e.g., CPL P3.0)
(increment, e.g., INC P2)
(decrement, e.g., DEC P2)
(Decrement, and jump if not Zero, e.g., DJNZ P3, LABEL)
(move carry bit to bit Y of Port X)
(clear bit Y of Port X)
(set bit Y of Port X)
It is obvious that the last three instructions in this list are read-modify-write instructions, but they are. They read the
port byte, all 8 bits, modify the addressed bit, then write the new byte back to the latch.
The reason that read-modify-write instructions are directed to the latch rather than the pin is to avoid a possible
misinterpretation of the voltage level at the pin. For example, a port bit might be used to drive the base of a transistor.
When a 1 is written to the bit, the transistor is turned on. If the CPU then reads the same port bit at the pin rather
than the latch, it will read the base voltage of the transistor and interpret it as a O. Reading the latch rather than the
pin return the correct value of 1.
The first four bits of register IOCON (OF8H) must be used for programming the output pullup values. Figure 7 shows
how IOCON must be programmed in order to obtain the required value.
4-9
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ MHS C51
(LSB)
(MSB)
I
WDT
T32
SERR
IZC
P2HZ
P3HZ
P1HZ
ALF
I
Symbol
Position
Function
ALF
10CON.O
- Set to 1 and in Power Down mode PORTS 1 , 2, and 3 are floating.
P1HZ
IOCON.1
- If P1 HZ = and IZC = 0, PORT P1 is at low impedance.
- If P1 HZ = and IZC = 0, PORT P1 is at high impedance.
- If P1 HZ = 1, PORT P1 is floating.
P2HZ
IOCON.2
- If P2HZ
and IZC = 0, PORT P2 is at low impedance.
- If P2HZ = and IZC = 0, PORT P2 is at high impedance.
- If P2HZ = 1, PORT P2 is floating.
P3HZ
IOCON.3
- If P3HZ = and IZC = 0, PORT P3 is at low impedance.
- If P3HZ = and IZC = 0, PORT P3 is at high impedance.
- If P3HZ = 1, PORT P3 is floating.
IZC
10CON.4
- In conjunction with PnHZ selects the output pullup value.
°°
=°
°
°°
Figure 7 : laCON register content.
Loading and Interfacing
• When PnHZ = and IZC = 0, ports P1 , P2 and P3 are identical to the 80C52's ports and each of them can load 3
LS TTL gates. Each InpuVOutput can be loaded by a collector or an open drain. However, it is important to note
that transistors going from to 1 are slower. The circuit in figure 8 shows an I/O of a port loaded by a 100 pf capacitor
and a transistor T (open drain).
°
°
Figure 8 : A port loaded by an open drain transistor and a 100 pf capacitor.
~
5
I
I
I
I
I
4
3
-'
2
1
0
A
01
3
---
J-- - -
B
I
I
I
I
I
I
I
7
9
t"'8)
11
13
Figure 9: Shows the behaviour of Vs when transistor T is blocked.
Influence of transistor P3 in area B.
4-10
15
- - - - - - - - - - - - - - - MHS C51
In area A, Vs is less than = 2 V. Transistor P3 is blocked and only transistor P2 is active during the transition (therefore,
the time constant is 10 times greater than normal). In area B, Vs becomes greater than 2 V and transistors P2 and
P3 are active in order to terminate the transition.
• When PnHZ = 0 and IZC = 1, only transistor P2 loads the ports Input/Output and one LS TIL load can be accepted
by the port. Each I/O can be loaded by a collector or an open drain. However, as stated above, it is important to
note that transistors going from 0 to 1 are slower. During the transition, only transistor P2 conducts (whatever the
value of Vs) and the time taken for going from 0 to 2.4 V is ten times greater than normal.
ACCESSING EXTERNAL MEMORY
Accesses to external memory are of two types: accesses to external Program Memory and accesses to external
Data Memory. Accesses to external Pro9.@.m Memory use signal PSEN (program store enable) as the read strobe.
Accesses to external Data Memory use RD or WR (alternate functions of P3.7 and P3.6) to strobe the memory.
Fetches from external Program Memory always use a 16-bit address. Accesses to external Data Memory can use
eithE1r a 16-bit address (MOVX@ DPTR) or an S-bit address (MOVX@ RI).
Whenever a 16-bit address is used, the high byte of the address comes out on Port2, where it is held for the duration
of the read or write cycle. Note that the Port2 drivers use the strong pullups during the entire time that they are emitting
address bits that are 1 s. This is during the execution of a MOVX @ DPTR instruction. During this time the Port2
latch (the Special Function Register) does not have to contain 1 s, and the contents of the Port2 SFR are not modified.
If the external memory cycle is not immediately followed by another extemal memory cycle, the undisturbed contents
of the Port2 SFR will reappear in the next cycle.
If an S-bit address is being used (MOVX @ RI), the contents of the Port2 SFR remain at the Port2 pins throughout
the external memory cycle. This will facilitate paging.
In any case, the low byte of the address is time-multiplexed with data byte on PortO. The ADDRIDATA signal drives
both FETs in the PortO output buffers. Thus, in this application the PortO pins are not open-drain outputs, and do to
not require external pullups. Signal ALE (Address Latch Enable) should be used to capture the address byte into an
external latch. The address byte is valid at the negative transition of ALE. Then, in a write cycle, the data byte to be
written appears on PortO just before WR is activated, and remains there until after WR is desactivated. In a read cycle,
the incoming byte is accepted at PortO just before the read strobe is desactivated.
During any access to external memory, the CPU writes OFFH to the PortO latch (the Special Function Register), thus
obliterating whatever information the Port 0 SFR may have been holding.
External Program Memory is accessed under two conditions:
1) Whenever signal EA is active ; or
2) Whenever the program counter (PC), contains a number that is larger than OFFFH (1 FFFH for the SOC52, 3FFFH
for the S3C154 or 7FFFh for the the S3C154D).
This requires that the ROMless versions have EA wired low to enable the lower 4k (Sk for the SOC32, 16K for the
SOC154 or 32 K for the S3C154D) program bytes to be fetched from external memory.
When the CPU is executing out of external Program Memory, all S bits of Port 2 are dedicated to an output function
and may not be used for general purpose I/O. During external program fetches they output the high byte of the PC.
During this time the Port 2 drivers use the strong pullups to emit PC bits that are 1 s.
TIMERS/COUNTERS
The SOC51 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1. The SOC52, S3C154 and S3C154D have
these two plus one more: Timer 2. All three can be configured to operate either as timers or event counters.
In the 'Timer" function, the register is incremented every machine cycle. Thus, one can think of it as counting machine
cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.
In the "Counter" function, the register is incremented in response to a 1-to-0 transition at its corresponding extemal
input pin, TO, T1 or (in the SOC52/C154/C154D) T2. In this function, the external input is sampled during S5P2 of
every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented.
The new count value appears in the register during S3P1 of the cycle following the one in which the transition was
detected. Since it takes 2 machine cycles (24 oscillator periods) to recognize a 1-to-0 transition, the maximum count
rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to
ensure that a given level is sampled at least once before it changes, it should be help for at least one full machine
cycle.
In addition to the 'Timer" or "Counter" selection, Timer 0 and Timer 1 have four operating modes from which to select.
Timer 2, in the SOC52/C154/C154D, has three modes of operation: "Capture", "Auto-Reload" and "baud rate generator".
4-11
_ _'
~
MHSC51
Timer 0 and Timer 1
These Timer/Counters are present in the 80C51 , the 80C52, the 83C154 and 83C154D. The "Timer" or "Counter"
function is selected by control bits CIT in the Special Function Register TMOD (figure 10). These two Timer/Counters
have four operating modes, which are selected by bit-pairs (M1, MO) in TMOD and three more for the 83C154/C154D
which are selected by bit-pairs (WDT, T32) in IOCON. Modes 0, 1, and 2 are the same for both Timer/Counters. Mode
3 is different and mode 4, and 6 are reserved for 83C154/C154D only. The seven modes, 80C51 , 80C52 and
83C154/C154D operating modes are described in the following text.
(MSB)
I GATE
(LSB)
CIT
M1
MO
GATE
CIT
Timer 1
GATE
ciT
M1
MO
I
Timer 0
Gating control when set. Timer/Counter "x" is
enabled only while "INTx" pin is high and
"TRx" control pin is set. When cleared Timer
"x" is enabled whenever "TRx" control bit is
set.
M1
MO
o
o
o
Timer or Counter Selector cleared for Timer
operation (input from internal system clock).
Set for Counter operation (input from "Tx"
input pin).
16-bit Timer/Counter "THx" and
"TLx" are cascaded ; there is no
prescaler
o
II
Operating Mode
13 bit Timer/Counter. Timer "TLx
serves as a 5 bit prescaler
8-bit auto-reload Timer/Counter
"THx" holds a value which is to be
reloaded into "TLx" each time it
overflows.
(Timer 0) TLO is an 8-bit
Timer/Counter controlled by the
standard Timer 0 control bits. THO is
an 8-bit timer only controlled by
Timer 1 control bits.
(Timer 1) Timer/Counter 1 stopped.
Figure 10 : TMOD : Timer/Counter Mode Control Register.
Figure 11 : Timer/Counter 1 Mode 0: 13 Bit Counter.
4-12
MHSC51
(LSB)
(MSB)
I
TF1
TR1
TFO
TRO
Symbol
Position
TF1
TCON.?
Timer 1 overflow Flag. Set
by hardware on Timer/
Counter overflow. Cleared
by hardware when processor vectors to interrupt
routine.
TR1
TCON.6
Timer 1 Run control bit.
Set/cleared by software to
turn Time/Counter on/off.
TFO
TCON.S
Timer 0 overflow Flag. Set
by
hardware
on
overflow.
Timer/Counter
Cleared by hardware when
processor vectors to interrupt routine.
TRO
TCON.4
IE1
Function
Timer 0 Run control bit.
Set/cleared by software to
turn Timer/Counter on/off.
IT1
lEO
ITO
I
Symbol
Position
IE1
TCON.3
Interrupt 1 Edge flag. Set by
hardware when external interrupt edge detected.
Cleared when interrupt
processed.
Function
IT1
TCON.2
Interrupt 1 Type control bit.
Set/cleared by software to
specify falling edge/low
level triggered external interrupts.
lEO
TCON.1
Interrupt 0 Edge flag. Set by
hardware when external interrupt edge detected.
Cleared when interrupt
processed.
ITO
TCON.O
Interrupt 0 Type control bit.
Set/cleared by software to
specify falling edge/low
level triggered external interrupts.
Figure 12: TCON : Timer/Counter Control Register.
ModeD
Putting either Timer into Mode 0 makes it look like an a-bit Counter with a divide-by-32 prescaler. Figure 11 shows
the Mode 0 operation as it applies to Timer 1.
In this mode, the Timer register is configured as a 13-Bit register. As the count rolls over from all 1 s to all Os, it sets
the TimerinterruptflagTF1. The counted input is enabled to the Timerwhen TR1 = 1 and either GATE = Oor INT1 = 1.
(Setting GATE = 1 allows the Timer to be controlled by external input INT1, to facilitate pulse width measurements).
TR1 is a control bit in the Special Function Register TCON (figure 12). GATE is in TMOD.
The 13-bit register consists of alia bits of TH1 and the lower S bits of TL1. The upper 3 bits of TL1 are indeterminate
and should be ignored. Setting the run flag (TR 1) does not clear the registers.
Mode 0 operation is the same for Timer 0 as for Timer 1. Substitute TRO, TFO and INTO for the corresponding Timer 1
signals in figure 11. There are two different GATE bits, one for Timer 1 (TMOD.?) and one for Timer 0 (TMOD.3).
Mode 1
Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits.
Mode 2
Mode 2 configures the Timer register as an a-bit Counter (TL 1) with automatic reload, as shown in figure 13. Overflow
from TL1 not only sets TF1 , but also reloads TL1 with the contents of TH1, which is preset by software.
The reload leaves TH1 unchanged.
4-13
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ MHS C51
~-
CIT=O
T1PIN
INTEIRJPT
____-'1 CIi=l
-
ml---------------i~
IN10 PIN - - - - - - - '
Figure 13 : Timer/Counter 1 Mode 2 : 8-Bit Auto-Reload.
Mode 3
Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = O.
,
II
Timer 0 in Mode 3 establishes TLO and THO as t'il!.O separate counters. The logic for Mode 3 on Timer 0 is shown in
Figure 14. TLO uses the Timer 0 control bits: CIT, GATE, TRO, INTO, and TFO, THO is locked into a timer function
(counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, THO now controls the "Timer
1" interrupt.
Mode 3 is provided for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, an 80C51 can
look like it has three Timer/Counters, and an 80C52, like it has four. When Timer 0 is in Mode 3, Timer 1 can be
turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate
generator, or in fact, in any application not requiring an interrupt.
I
'osc
~
1/12fOSC
1/12fOSC-----------.
INTERRUPT
10 PIN------.....I
GATE
INIO PIN - - - '
J:I. .
-_"_1::1. 1.
1f12fOSC -----TR-1---------------_-_-_-_
HL_1F_l_. ~
. I~
_<:_:ls_·_)...
Figure 14 : Timer/Counter 0 Mode 3: Two 8-Bit Counters.
4-14
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ MHS C51
83C154 and 83C154D
• The 83C154 has two supplementary modes. They are accessed by bits WOT and T32 of register IOCON. Figure 15
shows how IOCON must be programmed in order to have access to these functions.
(MSB)
I
(LSB)
T32
WOT
I
SERR
IZC
P3HZ
P2HZ
P1HZ
ALF
I
Symbol
Position
Function
T32
IOCON.6
- If T32
- If T32
WOT
IOCON.7
- If WOT = 1 and according to the mode selected by TMOO, an 8-bit or
32-bit WATCHOOG is configured from TIMERS 0 and 1.
= 1 and if CITO = 0, T1
= 1 and if CITO = 1, T1
and TO are programmed as a 32 bit TIMER.
and TO are programmed as a 32 bit COUNTER.
Figure 15: Timer/Counter/Watch-dog Mode Control Register.
32-Bit Mode
• T32 = 1 enables access to this mode. As show in figure 16, this 32-bit mode consists in cascading TIMER 0 for
the LSBs and TIMER 1 for the MSBs.
TlMERO
16 bits
Figure 16 : 32-bit Timer/Counter.
T32 = 1 starts the timer/counter and T32 = 0 stops it.
It should be noted that as soon as T32 = 0, TIMERs 0 and 1 assume the configuration specified by register TMOO.
Moreover, if TRO = 1 or if TR1 = 1, the content of the TIMERs evolves. Consequently, in 32-bit mode, if the
TIMER/COUNTER must be stopped (T32 = 0), TRO and TR1 must be set to O.
32-Bit Timer
• Figure 17 illustrates the 32-Bit TIMER mode.
OSC
~~T_IM_E_R_I--4._T_IM_E_R_II_~
Figure 17 : 32-Bit Timer Configuration.
4-15
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ MHS C51
• In this mode, T32 = 1 and CITO = 0, the 32-bit timer is incremented on each S3P1 state of each machine cycle.
An overflow of TIMER 0 (TFO has not been set to 1) increments TIMER 1 and the overflow of the 32-bit TIMER is
signalled by setting TF1 (S5P1) to 1.
• The following formula should be used to calculate the required frequency:
f=
OSC
12 x (65536 - (TO, T1))
32-Bit Counter
• Figure 18 illustrates the 32-BIT COUNTER mode.
fEXT
~------------~L-T_IM_E_R_O~___T_IM_E_R_I_~
Figure 18: 32-Bit Counter Configuration.
• In this mode, T32 = 0 and CITO = 1. Before it can make an increment, the 83C154 must detect two transitions on
its TO input. As shown in figure 19, input TO is sampled on each S5P2 state of every machine cycle or, in other
words, every OSC + 12.
-TO PIN
READING OF INPUTTO
t
Ci-1'
Ci
Ci+n,
IS5P2 _____ S5P2
IS5P2
COUNTER INCREMENTATION
Figure 19 : Counter Incrementation Condition.
• The counter will only evolve if a level 1 is detected during state S5P2 of cycle Ci and if a level 0 is detected during
state S5P2 of cycle Ci + n.
• Consequently, the minimal period of signal fEXT admissible by the counter must be greater than or equal to two
machine cycles. The following formula should be used to calculate the operating frequency.
f=
fEXT
65536 - (TO, T1))
O-=-S-:-C_ __
f EXT:;:; _ _ _
24
4-16
------------------------------ MHSC51
Watch-Dog Mode
• WDT = 1 enables access to this mode. As shown in figure 20, all the modes of TIMERSs 0 and 1, of which the
overflows act on TF1 (TF1 = 1), activate the WATCH-DOG Mode.
TIM ERO
Mode3
8 bits
TIMERl
MODEO,1,2
13-16bits
TIMER 0,1 MODE32bits 32 bits
Figure 20: The Different WATCH-DOG Configurations.
• If cif = 0, the WATCH-DOG is a TIMER that is incremented every machine cycle. If cif = 1, the WATCH-DOG
is a counter that is incremented by an external signal of which the frequency cannot exceed OSC + 24.
• The overflow of the TIMER/COUNTER is signalled by raising flag TF1 to 1. The reset of the 83C154/83C154(D)
is executed during the next machine cycle and lasts for the next 5 machine cycles. The results of this reset are
identical to those of a hardware reset. The internal RAM is not affected and the special register assume the values
shown in Table 2.
REGISTER
PC
ACC
B
PSW
SP
DPTR
PO-P3
IP
IE
TMOD
TCON
T2CON
THO
TlO
TH1
Tl1
TH2
Tl2
RCAP2H
RCAP2l
SCON
SBUF
IOCON
CONTENT
OOOOH
OOH
OOH
OOH
OOH
OOOOH
OFFH
OOH
OXOOOOOOB
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
Indeterminate
OOH
Table 2: Content of the SFRs after a reset
triggered by the WATCHDOG.
4-17
------------------------_____ MHSC51
• As there are no precautions for protecting bit WDT from spurious writing in the IOCON register, special care must
be taken when writing the program. In particular, the user should use the IOCON register bit handling instructions:
- SETS and CLR x
in preference to the byte handling instructions:
- MOV IOCON, # XXH, ORL IOCON, # XXH,
- ANL IOCON, # XXH, ...............................................................................................................................................
External Counting in Power-down Mode (PO = peON. 1 = 1)
• In the power-down mode, the oscillator is turned off and the 83C154s' activity is frozen. However, if an external
clock is connected to one of the two inputs, T1ITO, TIMER/COUNTERS 0 and 1 can continue to operate.
In this case, counting becomes asynchronous and the maximum, admissible frequency of the signal is OSC : 24.
• The overflow of either counter TFO or TF1 causes an interrupt to be serviced or forces a reset if the counter is in
the WATCH-DOG MODE (T32 = ICON. 7 = 1).
Timer 2
Timer 2 is a 16-bit Timer/Counter which is present only in the 80C52, 83C154 and 83C154D. Like Timers 0 and 1,
it can operate either as a timer or as an event counter. This is selected by bit CIT2 in the Special Function Register
T2CON (figure 21). It has three operating modes: "capture", "auto-load" and "baud rate generator", which are selected
by bits in T2CON as shown in Table 3.
(MSS)
III
I
(LSS)
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
CIT2
CP/RL2
I
Symbol
Position
Function
TF2
T2CON.7
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software.
TF2 will not be set when either RCLK = 1 OR TCLK = 1.
EXF2
T2CON.6
Timer 2 external flag set when either a capture or reload is caused by a negative
transition on T2 EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2
= 1 will cause the CPU to vector to the timer 2 interrupt routine. EXF2 must be
cleared by software.
RCLK
T2CON.5
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflow
to be used for the receive clock.
TCLK
T2CON.4
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows
to be used for the transmit clock.
EXEN2
T2CON.3
Timer 2 external enable flag. When set, allows a capture or reload to occur as
a result of a negative transition on T2EX if Timer 2 is not being used to clock the
serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2
T2CON.2
Start/stop control for Timer 2. A logic 1 starts the Timer.
CIT2
T2CON.1
Timer or counter select. (Timer 2)
= internal timer (OSC/12)
1 = external event counter (falling edge triggered).
CP/RL2
T2CON.O
Capture/reload flag. When set, captures will occur on negative transitions at
T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2
overflows or negative transitions at T2EX when EXEN2 = 1. When either
RCLK = 1 or TCLK = 1 , this bit is ignored and the timer is forced to auto-reload
on Timer 2 overflow.
o
Figure 21 : T2CON : Timer/Counter 2 Control Register.
4-18
MHSC51
RCLK +
TCLK
CP/RL2
TR2
MODE
0
0
1
X
0
1
X
X
1
1
1
0
16-bit Auto-reload
16-bit Capture
Baud Rate Generator
(off)
Table 3 : Timer 2 Operating Modes.
In the capture Mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, then Timer 2
is a 16-bit timer or counter which upon overflowing sets bitTF2, the Timer 2 overflow bit, which can be used to generate
an interrupt. If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a 1-to-0 transition at
external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers,
RCAP2L and RCAP2H, respectively. (RCAP2L and RCAP2H are new Special Function Registers in the 80C52,
83C154 and 83C154D). In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2, like TF2,
can generate an interrupt.
The Capture Mode is illustrated in figure 22.
~
CJ - L:.:.J
,~=o
1
T2 PIN _ _ _- - I cif2=1
TIMER 2
INlEIRJPT
r
TRANSITION
DE1ECIOR
12EXPIN
Figure 22 : Timer 2 in Capture Mode.
In the auto-reload mode there are again two options, which are selected by EXEN2 in T2CON. If EXEN2 = 0, then
Timer 2 rolls over it not only sets TF2 but also causes the Timer 2 registers to be reloaded with the 16-bit value in
registers RCAP2L and RCAP2H, which are preset by software. If EXEN2 = 1, then Timer 2 still does the above, but
with the added feature preset by software. If EXEN2 = 1, then Timer 2 still does the above, but with the added feature
that a 1-to-0 transition at external input T2EX will also trigger the 16-bit reload and set EXF2.
Figure 23 : Timer 2 in Auto-Reload Mode.
The auto-reload mode is illustrated in figure 23.
The baud rate generator mode is selected by RCLK
serial port.
= 1 and/or TCLK = 1. It will be described in conjunction with the
4-19
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ MHS C51
SERIAL INTERFACE
The serial ports is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning
it can start reception of a second byte before a previously received byte has been read from the receive register.
(However, if the first byte still hasn't been read by the time reception of the second byte is completed, one of the
bytes will be lost). The serial port receive and transmit registers are both accessed at Special Function Register SBUF.
Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register.
The serial port can operate in modes:
Mode 0 : Serial data enters and exits through RDX, TDX outputs the shift clock. 8 bits are transmitted/received: 8 data
bits (LSD first). The baud rate is fixed at 1/12 the oscillator frequency.
Mode 1 : 10 bits are transmitted (through TXD) or received (through RXD) : a start bit (0), 8 data bits (LSB first), and
a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SCaN. The baud rate is variable.
Mode 2 : 11 bits are transmitted (through TXD) or received (through RXD) : a start bit (0), 8 data bits (LSB first), a
programmable 9 th data bit and a stop bit (1). On Transmit, the 9th data bit (TB8 in SCaN) can be assigned the value
of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes
into RB8 in Special Function Register SCaN, while the stop bit is ignored. The baud rate is programmable to either
1/32 or 1/64 the oscillator frequency.
Mode 3 : 11 bits are transmitted (through TXD) or received (through RXD) : a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except the baud
rate. The baud rate in Mode 3 is variable.
In all four modes, transmission, is initiated by any instruction that uses SBUF as a destination register. Reception is
initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming
start bit if REN = 1.
III
Multiprocessor Communications
Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received.
The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is
received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCaN.
A way to use this feature in multiprocessor systems is as follows.
When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address
byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address
byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will
interrupt all slaves, so that each slave can examine the received bytes that will be coming. The slaves that weren't
being addressed leave their SM2s set and go on about their business, ignoring the coming data bytes.
SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1 reception,
if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.
Serial Port Control Register
The serial port control and status register is the Special Function Register SCaN, shown in figure 24. This register
contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the
serial port interrupt bits (TI and RI).
Baud rates
The baud rate in Mode 0 is fixed:
Mode 0 Baud Rate =
Oscillator Frequency
12
4-20
- -_ _ _ _ _ _ _ _ _ _ _ _ _ _ MHS C51
°
The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Register PCON. If SMOD = (which
is the value on reset), the baud rate 1/64 the oscillator frequency. If Smod = 1, the baud rate is 1/32 the oscillator
frequency.
(MSB)
I
SMO
(LSB)
SM1
SM2
TBS
REN
RBS
TI
RI
I
Where SMO, SM1 specify the serial port mode, as follows:
SMO SM1
Mode Description
°° ° °
°
1
2
Shift register
S-bit UART
9-bit UART
1
3
9-bit UART
1
1
-SM2
- REN
Baud Rate
fose /12
variable
fose /64
or
fose /32
variable
enables the multiprocessor communication
feature in Modes 2 and 3. In mode 2 or 3,
if SM2 is setto 1 then RI will not be activated
if the received 9th data bit (RBS) is 0. In
Mode 1 , if SM2 = 1 then RI will not be activated if a valid stop bit was not received.
In mode 0, SM2 should be 0.
enables serial reception. Set by software to
enable reception. Clear by software to disable reception.
- TBS
is the 9th data bit that will be transmitted in
Modes 2 and 3. Set or clear by software as
desired.
- RBS
in Modes 2 and 3, isthe 9th data bit that was
received. In Mode 1, if SM2 = 0, RBS is the
stop bit that was received. In Mode 0, RB8
is not used.
-TI
is transmit interrupt flag. Set by hardware at
the end of the 8th bit time in Mode 0, or at
the beginning of the stop bit in the other
modes, in any serial transmission. Must be
cleared by software.
- RI
is receive interrupt flag. Set by hardware at
the end of the Sth bit time in Mode 0, or
halfway through the stop bit time in the
other modes, in any serial reception (except
see SM2). Must be cleared by software.
Figure 24 : SCON : Serial Port Control Register.
2 SMOD
Mode 2 Baud Rate = - - x (Oscillator Frequency)
64
In the SOC51 , the baud rates in Modes 1 and 3 is determined by the Timer 1 overflow rate. In the 80C52, 83C154
and S3C154D, these baud rates can be determined by Timer 1, or by Timer 2, or by both (one for transmit and the
other for receive).
Using Timer 1 to Generate Baud Rates
When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1
overflow rate and the value of SMOD as follows:
Modes 1, 3
Baud Rate =
2SMOD
32
x (Timer 1 Overflow Rate)
The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either "timer" or
"counter" operation, and in any of its 3 running modes. In the most typical applications, it is configured for "timer"
operation, in the auto-reload mode (high nibble of TMOD = 001 OB). In that case, the baud rate is given by the formula.
Modes 1, 3
Baud Rate =
2SMOD
-- x
32
Oscillator Frequency
12 x [256 - (TH1)J
One can achieve very low baud rates with Timer 1 by leaving the Timer 1 interrupt enabled, and configuring the Timer
to run a 16-bit timer (high nibble of TMOD = 0001 B), and using the Timer 1 interrupt to do a 16-bit software reload.
4-21
MHSC51
Figure 25 lists various commonly used baud rates and how they can be obtained from Timer 1.
TIMER 1
BAUD RATE
fose
SMOD
Mode 0 Max : 1 M
Mode 2 Max: 375 K
Mode 1,3 : 62.5 K
19.2 K
9.6 K
4.8 K
2.4 K
1.2 K
137.5 K
110 K
110 K
12 MHZ
12 MHZ
12 MHZ
11.059 MHZ
11.059 MHZ
11.059 MHZ
11.059 MHZ
11.059 MHZ
11.986 MHZ
6 MHZ
12 MHZ
X
1
1
1
0
0
0
0
0
0
0
CIT
MODE
RELOAD
VALUE
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
1
FFH
FDH
FDH
FAH
F4H
E8H
1DH
72 H
FEEBH
Figure 25 : Timer 1 Generated Commonly Used Baud Rates.
Using Timer 2 to Generate Baud Rates
In the 80C52 and 83C154/83C154D, Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK
in T2CON (figure 12). Note then the baud rates for transmit and receive can be simultaneously different. Setting RCLK
and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 26.
TIMER 1
r
~
NarE : osc. fREQ.1S IlIIIIDED BY 2. NOr 12.
~d
r;;w:;L
-----SMCXl
~
CrL.::.r ,~~o
'I·
"0"
--
--RCLJ(
+18
'I"
RXClDCK
"0"
1- .I~:j.
TXClDCK
12EXPIN
Figure 26 : Timer 2 in Baud Rate Generator Mode.
The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers
to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software.
Now, the baud rates in Modes 1 and 3 are determinated by Timer 2's overflow rate as follows:
Modes 1, 3 Baud Rate =
Timer 2 Overflow Rate
16
4,22
MHSC51
The Timer can be confiQ!:!!:ed for either "timer" or "counter" operation. In the most typical applications, it is configured
for "timer" operation (C1T2 = 0). "Timer" operation is a little different for Timer 2 when it's being used as a baud rate
generator. Normally, as a timer it would increment every machine cycle (thus at 1/12 the oscillator frequency). In that
case the baud rate is given by the fonmula
Modes 1,3 Baud Rate =
Oscillator Frequency
32 x [65536 - (RCAP2H, RCAP2L)]
where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.
Timer 2 as a baud rate generator is shown in Figure 25. This Figure is valid only if RCLK + TCLK = 1 in T2CON. Note
that a rollover in TH2 does not set TF2, and will not generate an interrupt. Therefore, the Timer 2 interrupt does not
have to be disabled when Timer 2 is in the baud rate generator mode. Note too, that if EXEN2 is set, a 1-to-0 transition
in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in
use as a baud rate generator, T2EX can be used as an extra external interrupt, if desired.
It should be noted that when Timer 2 is running (TR2 = 1) in "timer" function in the baud rate generator mode, one
should not try to read or write TH2 or TL2. Under these conditions the Timer is being incremented every state time,
and the results of a read or write may not be accurate. The RCAP registers may be read, but shouldn't be written to,
because a write might overlap a reload and cause write and/or reload errors. Turn the Timer off (clear TR2) before
accessing the timer 2 or RCAP registers, in this case.
More about Mode 0
Serial data enters and exits through RXD.TXD outputs the shift clock. 8 bits are transmitted/received: 8 data bits
(LSB first). The baud rate is fixed at 1/12 the oscillator frequency.
Figure 27 shows a simplified functional diagram of the serial port in Mode 0, and associated timing.
Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF" signal at
S6P2 also loads a 1 into the 9th position of the transmit shift register and tells the TX Control block to commence a
transmission. The internal timing is such that one full machine cycle will elapse between "write to SBUF", and activation
of SEND.
SEND enables the output of the shift register to the alternate output function of P3.0, and also enables SHIFT CLOCK
to the alternate output function line of P3.1. SHIFT CLOCK is low during S3, S4, and S5 of every machine cycle, and
high during S6, S1 and S2. At S6P2 of every machine cycle in which SEND is active, the contents of the transmit
shift register are shifted to the right one position.
As data bits shift out the right, zeroes come in from the left. When the MSB of the data byte is at the output position
of the shift register, then the 1 that was initially loaoed into the 9th position, is just to the left of the MSB, and all positions
to the left of contain zeroes. This condition flags the TX Control block to do one last shift and then deactivate SEND
and set TI. Both of these actions occur at S1 P1 of the 10th machine cycle after "write to SBUF".
Reception is initiated by the condition REN = 1 and R1 = O. At S6P2 of the next machine cycle, the RX Control unit
writes the bits 11111110 to the receive shift register, and in the next clock phase activates RECEIVE.
RECEIVE enables SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK makes transitions at
S3P1. and S6P1. of every machine cycle. At S6P2 of every machine cycle In which RECEIVE is active, the contents
of the receive shift register are shifted to the left one position. The value that comes in from the right is the value that
was sampled at the P3.0 pin at S5P2 of the same machine cycle.
As data bits come in from the right, 1s shift out to the left. When the 0 that was initially loaded into the rightmost position
arrives at the leftmost position in the shift register, it flags the RX Control block to do one last shift and load SBUF.
At S1 P1 of the 10th machine cycle after the write to SCaN that cleared RI, RECEIVE is cleared and RI is set.
4·23
MHSC51
RXO
P3.oAlI
OUTPUT
RJNCTION
TXO
pal AlI
0U1l'lJT
RJNCTION
REN
Ai
RXD
paOAlI
INPllT
RJNCT10N
LBUS
ALE
----" WRffElO SBUF
SEND
LseP2
SHFT
I
AXD (Ilf\TA OUT) \
lXD (SHFT a.ocK)
n~
___________
__l____________________________________________
~~l~~
L--jTRANSMIT
~r-----
----" WFlTElO SCON (CllAR RI)
iii
RECEIVE
=SH~FT~
__________~nL____~nL_____~~____~
RXD(Ilf\TAIN)
:==
I'L--
----~~-a~--~--~~~~--~~_U~~~---
lXD (SHFT CLOCKl
Figure 27 : Serial Port Mode O.
4-24
j
RECEIVE
MHSC51
More about Mode 1
Ten bits are transmitted (through TDX), or received (through RXD) : a start bit (0), B data bits (LSB first), and a stop
bit (1). On receive, the stop bit goes into RBB in SCON. In the BOC51 the baud rate is determinated by the Timer 1
overflow rate. In the BOC52, B3C154 and B3C154D it is determinated either by the Timer 1 overflow rate, or the Timer
2 overflow rate, or both (one for transmit and the other for receive).
Figure 2B shows a simplified functional diagram of the serial port in Mode 1, and associated timings for transmit
receive.
Transmission is initiated by any Instruction that uses SBUF as a destination register. The "write to SBUF" signal also
loads a 1 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually commences at S1 P1 of the machine cycle following the next rollover in the divideby-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the "write to SBUF" signal).
The transmission begins with activation of SEND, which puts the start bit at TXD. One bit time later, DATA is activated,
which enables the output bit of the transmit shift register to TXD. The first shift pulse occurs one bit time after that.
As data bits shift out to the right, zeroes clocked in from the left. When the MSB of data byte is at the output position
of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the MSB, and all positions
to the left that contain zeroes. This condition flags TX Control unit to do one last shift and then desactivate SEND
and set TI. This occurs at the 10th divide-by-16 rollover after "write to SBUF".
Reception is initiated by a detected 1-to-0 transition at RXD. For this purpose RXD is sampled at a rate of 16 times
whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset,
and 1FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times.
The 16 states of the counter divide each bit time into 16ths. At the 7th, Bth, and 9th counter states of each bit time,
the bit detector samples the value of RXD. The value accepted is the value that was seen in at least 2 of 3 samples.
This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset
and the unit goes back to looking for another 1-to-0 transition. This is to provide rejection of false start bits. If the start
bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed.
As data bits come in from the right, 1s shift out of the left. When the start bit arrives at the leftmost position in the shift
register, (which in mode 1 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RBB,
and to set RI, the signal to load SBUF and RBB, and to set RI, will be generated if, and only if, the following conditions
are met at the time the final shift pulse is generated.
1) RI = 0, and
2) Either SM2
= 0, or the received stop bit = 1
In either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop
bit goes into RBB, the B data bits go into SBUF, and RI is activated. At this time, whether the above conditions are
met or not, the unit goes back to looking for a 1-to-0 transition in RXD.
4-25
- - - - - - - - -_ _ _ _ _ _ MHS C51
TIMER 2
OIIERR.OW
SEiiit------'
!DAD
AI
SBUF
SHlFTI-----..
RXCONTROL
RXD
I
SIOPBlTGEN
RK
R:CEIVE
{;.,",:~
~
I
SAWLEDKS
+16 RESET
n
I SMl'8Jf ,
1M
n
...
!!O
6,
1M
n
..
D2
!!3
•
i!i
1M
A
'"
II
I
•
X
Ii
•
m
1M
"
•
1M
'SlOP
!II
I
r---
Figure 28 : Serial Port Mode 1. TCLK, RCLK and Timer 2 are Present in the 80C52, 83C154 and 83C154D only.
4-26
MHSC51
More about Modes 2 and 3
Eleven bits are transmitted (through TXD), or received (through RXD) : a start bit (0),8 data bits (LSB first), a programmable 9th data bit and a stop bit (1). On transmit the 9th data bit (TB8) can be assigned the value of 0 or 1. On receive,
the 9th data bit goes into RB8 in SCaN. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency
in Mode 2.
Mode 3 may have a variable baud rate generated from either Timer 1 or 2 depending on the state of TCLK and RCLK.
Figures 29 and 30 show a functional diagram of the serial port in Modes 2 and 3. The receive portion is exactly the
same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register.
Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF" signal also
loads TB8 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is
requested. Transmission commences at S1 P1 of the machine cycle following the next rollover in the divide-by-16
counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the "write to SBUF" signal).
The transmission begins with activation of SEND, which puts the start bit at TXD. One bit time later, DATA is activated,
which enables the output bit of the transmit shift register to TXD. The first shift pulse occurs one bit time after that.
The first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeroes are clocked
in. Thus as data bits shift out to the right, zeroes are clocked in from the left. When TB8 is at the output position of
the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that contain zeroes. This
condition flags the TX Control unit to do one last shift and then desactivate SEND and set TI. This occurs at the 11th
divide-by-16 rollover after "write to SBUF".
Reception is initiated by a detected 1-to-0 transition at RXD. For this purpose RXD is sampled at a rate of 16 times
whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset,
and 1FFH is written to the input shift register.
At the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RXD. The value accepted
is the value that was been in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the
receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. If the start bit proves valid, it
is shifted into the input shift register, and reception of the rest of the frame will proceed.
As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift
register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and
RB8, and set RI. The Signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated:
1) RI = 0, and
2) Either SM2 = 0 or the received 9th data bit = 1
If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are
met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later, whether the
above conditions were met or not, the unit goes back to looking for 1-to-0 transition at the RXD input.
Note that the value of the received stop bit is irrelevant to SBUF, RB8 or RI.
4-27
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ MHS C51
1)(
.
w
•
-
O1=:L::oaA
•
Figure 29 : Serial Port Mode 2.
4-28
D3
•
"
-•
DO
..
\7'
•
01
•
0'
•
A
MHSC51
llMER 2
OVERFLOW
RXD
WlSCSl
~~L-.JD3~I~Il....--D==ITRANSMIT
~
00
M
_
[)4
I~I~
ml~'~~
I
I
~oo~
RX
CWO<
IlECENE
{;~
I
STARfiIT
I
po
~
w
~~
~~
__
~
__~.~~~I.~
____ ____
~A
~
__
~.~L-
____A-__
__•.•
~AL-
4~
L-~mr~
__
~
_____
Figure 30 : Serial Port Mode 3. TCLK, RCLK, and Timer 2 are Present in the 80C52/80C32 and 83C154/83C154D.
4-29
- -_ _ _ _ _ _ _ _ _ _ _ _ _ MHS C51
Error Detection in Reception (83C154 and 83C154D only)
• A supplementary IOCON register bit, SERR = IOCON.5, enables detection of a RECEPTION error. Two types of
error are possible: OVERRUN error and FRAME error.
Frame Error
• SERR = 1 indicates that a data format error has been detected. All the bits of a same character are sampled on
the 7th, 8th and 9th RECEPTION clock cycles. A majority vote determines the logical state of the bit received.
A character terminates with one or more stop bits (level 1). In figure 31, the stop bit is missing (level) and bit SERR
is set to 1 at the same time as bit RI.
RXD
l
00
01
02
03
04
05
06
07
STOP;
=0
~----~~~--~~~--~~~--~---
RI
SERR
Figure 31 : SERR = 1 signals an error in the format of the received bit.
• SERR is cleared by the software.
Overrun Error
SERR = 1, indicates that the previously received character has not been read and has been replaced by the next
character. In figure 32, a first character has been received and flag RI is set at 1. A second character is received
before the first character has been read (RI is still at 1). The first character is lost and the SERR flag is raised to
1 to signal this error.
RXD
l
CHARACrER 1
CHARACTER 2
~~------~--~--~----~----
RI
SERR
Figure 32 : SERR = 1 signals an error in the received character (OVERRUN).
• SERR is cleared by the software.
Serial Link in Power-down and Idle Mode
• In POWER-DOWN (PO = 1) or IDLE (IDL = 1) mode the serial link can continue to transmit and receive in Modes 1
and 3. The transmission/reception clock is generated by counter 1 (CIT1 = 1 , GATE = 0) and the external clock
must not exceed OSC .;- 24. An interrupt generated by the serial link (RI = 1 or TI = 1) enables exit from these two
modes.
• All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been
set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled in software.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function
Register IE (figure 34). IE contains also a global disable bit, EA, which disables all interrupts at once.
Note in figure 34 that bit position 1E.6 is unimplemented. In the 80C51 bit position IE.5 is also unimplemented. User
software should not write 1s in these bit positions, since they may be used in future MHS C51 products.
4-30
MHSC51
INTERRUPTS
The 80C51 provides 5 interrupt sources. The 80C52, 83C154 and 83C154D provides 6. They are shown in figure 33.
The External Interrupts INTO and INT1 can each be either level-activated or transition-activated, depending on bits
ITO and IT1 in Register TCON. The flags that actually generate these interrupts are bits lEO and IE1 in TCON. When
an extemal interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is
vectored to only if the interrupt was transition-activated. If the interrupt was level-activated, then the external requesting
source is what controls the request flag, rather than the on-chip hardware.
The Timer 0 and Timer 1 Interrupts are generated by TFO and TF1, which are set by a rollover in their respective
Timer/Counter registers (except see Timer 0 in Mode 3). When a timer interrupt is generated, the flag that generated
it is cleared by the on-chip hardware when the service routine is vectored to.
The Serial Port Interrupt is generated by the logical OR of RI and TI. Neither of these flags is cleared by hardware
when the service routine is vectored to. In fact, the service routine will normally have to determine whether it was RI
or TI that generated the interrupt, and the bit will have to be cleared in software.
In the 80C52, 83C154 and 83C154D, the Timer 2 Interrupt is generated by the logical OR of TF2 and EXF2. Neither
of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have
to determine whether it was TF2 or EXF2 that generated the interrupt, and the bit will have to be cleared in software.
....
~----------------~
•.
~-----------------4
~==D)----·
EX"::
D (80C52,':54 AND 83C154D ONlY)
Figure 33 : MHS C51 Interrupt Sources.
==
H
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ MHS C51
(MSB)
I
II
(LSB)
EA
X
Symbol
Position
EA
IE.?
X
ET2
1E.6
1E.5
ES
IE.4
ET1
IE.3
EX1
ETO
IE.2
IE.1
EXO
lE.O
ET2
En
ES
EX1
ETO
EXO
I
Function
disables all interrupts. If EA = 0, no interrupt will be acknowledge. If EA = 1 each
interrupt source is individually enabled or disabled by setting or clearing its
enable bit.
reserved
enables or disables the Timer 2 Overflow or capture interrupt. If ET2 = 0, the
Timer 2 interrupt is disabled.
enables or disables the Serial Port interrupt. If ES = 0, the Serial Port interrupt
is disabled.
enables or disables the Timer 1 Overflow interrupt. If ET1 = 0, the Timer 1 interrupt is disabled.
enables or disables External Interrupt 1.lf EX1 = 0, External Interrupt is disabled.
enables or disables the Timer 0 Overflow interrupt. If ETO = 0, the Timer 0 interrupt is disabled.
enables or disables External Interrupt O. If EXO = 0, External Interrupt 0 is disabled.
Figure 34 : IE : Interrupt Enable Register.
Priority Level Structure
• Register IP (B8H) makes it possible for all interrupts to have 2 levels of priority. Figure 35 shows the content of this
register.
(MSB)
I
PCT
(LSB)
X
PT2
Symbol
Position
PCT
PT2
IP.?
IP.6
IP.5
PS
IP.4
PT1
IP.3
PX1
IP.2
PTO
IP.1
PXO
IP.O
PS
PT1
H
PTO
PXO
I
Function
PCT = 1, only one level (83C154 and 83C154D only)
reserved
defines the Timer 2 interrupt priority level. PT2 = 1 programs
it to the higher priority level.
defines the Serial Port interrupt priority level. PS = 1 programs
it to the higher priority level.
defines the Timer 1 interrupt priority level. PT1 = 1 programs
it to the higher priority level.
defines the external interrupt 1 priority level. PX1 =1 programs
it to the higher priority level.
defines the Timer 0 interrupt priority level. PTO = 1 programs
it to the higher priority level.
defines the Extemal interrupt 0 priority level. PXO =1 programs
it to the higher priority level.
Figure 35 : IP : Interrupt Priority Register.
==
PX1
4-32
- - -_ _ _ _ _ _ _ _ _ _ _ _ MHS C51
IP = 0, selection of first priority level. Therefore, all interrupts have this priority level. Figure 36 shows the order in
which the interrupts are accepted within a same level.
1
2
3
4
5
6
SOURCE
lEO
TFO
IE1
TF1
RI + TI
TF2 + EX2
PRIORITY WITHIN LEVEL
(Highest)
(Lowest)
Figure 36 : Order of priority within a priority level.
Interrupt requests are read during states S2 to S5 of each machine cycle. During state S6, a polling is executed
to determine which interrupt will be served. The order in which the requests are read conforms to the figure above,
lEO ----> TF2 + EX2. The first request read is executed and instruction RETI terminates the interrupt sub-routine.
The flag corresponding to the interrupt is cleared (by software or hardware). If two interrupt requests occur at the
same time, the first read is executed.
To enable an interrupt with a lower read priority to be serviced in priority, it is possible to program the interrupt bit
of register IP to 1. Thus, if 2 interrupt requests occur simultaneously, the first to be serviced will not be the first
request read but that with the highest priority. Therefore, if PT1 = 1 a simultaneous request from lEO and IE1 will
result in IE1 being serviced first.
Bit PCT IP.7, only present in the 83C154 and 83C154D, enables inhibiting of the 2nd priority level. Therefore, all
interrupts will have the same level and operation is identical to that of IP = O.
How Interrupts are Handled
The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled during the following
machine cycle. If one of the flags was set in a condition at S5P2 of the preceding cycle, the polling cycle will find
it and interrupt system will generate a LCALL to the appropriate service routine, provided this hardware-generated
LCALL is not blocked by any of the following conditions :
1. An interrupt of equal or higher priority is already in progress.
2. The current (polling) cycle is not the final cycle in the execution of the instruction in progress.
3. The instruction in progress is not RET or any write to the IE or IP registers.
Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2
ensures that the instruction in progress will be completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is RETI or any access to IE or IP, then at least one more instruction will be
executed before any interrupt is vectored to.
• The polling cycle is repeated with each machine cycle, and the values that were present at S5P2 of the previous
machine cycle. Note then that if an interruptflag is active but not being responded to for one of the above conditions,
if the flag is not still active when the blocking condition is removed, the denied interrupt will not be serviced. In other
words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle is
new.
The polling cycie/LCALL sequence is illustrated in figure 37.
• Note that if an interrupt of higher level goes active priority to S5P2 of the machine cycle labelled C3 in figure 37
then in accordance with the above rules it will be vectored to during C5 and C6, without an instruction of the lower
priority routine having been executed.
------Cl
S5P2
56
- ,-
.---cs-___•.
C2-...__
,
-cs-----
- - C 4 -_____
:
----~l~----BN,...-.-----lll~'------
n
IN1EFRJPT
oa;s
LONGCALLlO
INTERRUPT
VECIOR ADDRESS
INTERU'T
LAraiED
ACJIVE
This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP.
Figure 37 : Interrupt Response Timing Diagram.
4·33
- -_ _ _ _ _ _ _ _ _ _ _ _ _ MHS C51
Thus the processor acknowledges an interrupt request by executing a hardware-generated LCALL to the appropriate
servicing routine. In some cases it also clears the flag that generated the interrupt, and in other cases it doesn't. It
never clears the Serial Port or Timer 2 flags. This has be done in the user's software. It clears an external interrupt
flag (lEO or IE1) only if it was transition-activated. The hardware-generated LCALL pushes the contents ofthe Program
Counter onto the stack (but it does not save the PSW) and reloads the PC with an address that depends on the source
of the interrupt being vectored to, as shown below.
Source
Vector Address
CLEARED BY HARDWARE
lEO
0003H
Only on trigger edge (ITO = 0)
TFO
OOOBH
At the end of the interrupt routine
IE1
0013H
Only on trigger edge (IT1 = 0)
TF1
001BH
At the end of the interrupt routine
RI+TI
0023H
} Cleared by software
TF2+ EXF2
002BH
Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs the
processor that this interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads
the Program Counter. Execution of the Interrupted program continues from where it left off.
Note that a simple RET instruction would also have returned execution to the interrupted program, but it would have
left the interrupt control system thinking an interrupt was still in progress.
..
External Interrupts
The extemal sources can be programmed to be level-activated or transition-activated by setting or clearing bit IT1
or ITO in Register TCON. If ITx =0, external interrupt x is triggered by a detected lowatthe INTx pin. If ITx = 1, external
interrupt x is edge-triggered. In this mode if successive samples of the INTx pin show a high in one cycle and a low
in the next cycle, interrupt requests flag lEx in TCON is set. Flag bit lEx then requests the interrupt.
Since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least
12 oscillator periods to ensure sampling. If the external interrupt is transition-activated, the external source has to
hold the request pin high for at least one cycle, and then hold it low for at least one cycle to ensure that the transition
is seen so that interrupt request flag lEx will be automatically cleared by the CPU when the service routine is called.
If the external interrupt is level-activated, the external source has to hold the request active until the requested interrupt
is actually generated. Then it has to desactivate the request before the interrupt service routine is completed, or else
another interrupt will be generated.
Response Time
The INTO and INT1 levels are inverted and latched into lEO and IE1 at S5P2 of every machine cycle. The values are
not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to
be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The call itselftakes two cycles. Thus, a minimum of three complete machine cycles elapse between activation
of an external interrupt request and the beginning of execution of the first instruction of the service routine. Figure 37
shows interrupt response timings.
A longer response time would result if the request is blocked by one of the 3 previously listed conditions. If an interrupt
of equal or higher priority level is already in progress, the additional wait time obviously depends on the nature of the
other interrupt's service routine. If the instruction in progress is not in its final cycle, the additional wait time cannot
be more than 3 cycles, since the longest instructions (MUL and DIV) are only 4 cycles long, and if the instruction in
progress is RETI or an access to IE or IP, the additional wait time cannot be more than 5 cycles (a maximum of one
more cycle to complete the instruction in progress, plus 4 cycles to complete the next instruction if the instruction is
MUL or DIV).
Thus, in a single-interrupt system, the response time is always more than 3 cycles and less than 9 cycles.
SINGLE-STEP OPERATION
The MHS C51 interrupt structure allows single-step execution with very little software overhead. As previously noted,
an interrupt request will not be responded to while an interrupt of equal priority level is still in progress, nor will it be
responded to after RETI until at least one other instruction has been executed. Thus, once an interrupt routine has
been entered, it cannot be re-entered until at least one instruction of the interrupted program is executed. One way
to use this feature for single-stop operation is to program one of the external interrupts (INTO) to be level-activated.
The service routine for the interrupt will terminate with the following code :
______________________________ MHSC51
JNB P3.2,S : Wait Here Till INTO Goes High
JB P3.2,S: Now Wait Here Till it Goes Low
RETI :
Go Back and Execute One Instruction
Now if the INTO pin, which is also the P3.2 pin, is held normally low, the CPU will go right into the External Interrupt
o routine and stay there until INTO is pulsed (from low to high to low). Then it will execute RETI, go back to the task
program, execute one instruction, and immediately reenter the External Interrupt 0 routine to await the next pulsing
of P3.2. One step of the task program is executed each time P3.2 is pulsed.
RESET
The reset input is the RST pin, which is input to a Schmitt Trigger.
A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the
oscillator is running. The CPU responds by generating an internal reset, with the timing shown in figure 38.
The external reset signal is asynchronous to the internal clock. The RST pin is sampled during State 5 Phase 2 of
every machine cycle. The port pins will maintain their current activities for 19 oscillator periods after a logic 1 has
been sampled at the RST pin; that is, for 19 to 31 oscillator periods after the external reset signal has been applied
to the RST pin.
While the RST pin is high, ALE and PSEN are weakly pulled high. After RST is pulled low, it will take 1 to 2 machine
cycles for ALE and PSEN to start clocking. For this reason, other devices can not be synchronized to the internal
timings of the 8051.
Driving the ALE and PSEN pins to 0 while reset is active could cause the device to go into an indeterminate state.
The internal reset algorithm writes Os to all the SFRs except the port latches, the Stack Pointer, and SBUF. The port
latches are initialized to FFH, the Stack Pointer to 07H, and SBUF is indeterminate. Table 2 lists the SFRs and their
reset values.
The internal RAM is not affected by reset. On power up the RAM content is indeterminate.
I---
12OSCPERlOOS - - . /
I~I~I~I~I~I~I~I~I~I~I~I~I~I~I~I~I~I~I
RST:
LIIIIIIIIIIL
ALE:
r- INTERNAL. RESET SIGNAl
SAMPlERST
SAMPLERSr
1L-:-----InL-----In!--:
, ----In'------'n'--_
,,,
,
PO:
INSf
,,
,,
x+x "" X--X ~ X~X .... X~
,
,,------19 OSCPEHOOS
--<...
Figure 38 : Reset Timing.
4-35
,
----~.,
MHSC51
REGISTER
PC
ACC
B
PSW
SP
DPTR
PO-P3
IP
IE
TMOD
TCON
T2CON
THO
TLO
TH1
TL1
TH2
TL2
RCAP2H
RCAP2L
SCON
SBUF
10CON
CONTENT
OOOOH
OOH
OOH
OOH
07H
OOOOH
OFFH
OOH
OXOOOOOOB
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
Indeterminate
OOH
lpF
+
'oICC
r-
8OC5118OC52
83C154
83C154D
RST
-4:-
Table 4 : Reset Values of the SFRs.
VSS
Figure 39 : Power on Reset Circuit.
POWER·ON RESET
• An automatic reset on powering-up can be obtained by connecting a 0.1 /IF capacitance between input RST and
the Vcc. The power supply's rise time must not exceed 1 ms and the oscillator start-up time must not exceed 10 ms.
• Note that the port II0s will be in a determinate state (OFFH) as soon as the input RST is active (high).
• With this circuit (figure 39), if Vcc is reduced rapidly, input RST will momentarily go below O. However, input RST
is protected internally.
POWER·SAVING MODES OF OPERATION
• For applications in which power consumption is a critical parameter, the MHS C51 family offers two power-saving
modes: IDLE and POWER-DOWN. Figure 40 illustrates the principle used for implementing these two modes.
CPU
Figure 40 : Principle of the IDLE and POWER-DOWN Modes.
4·36
MHSC51
• In IDLE mode, the oscillator continues to operate and the interrupts the serial port and timers 0 and 1 remain under
the internal oscillator's control. Only the CPU is no longer driven by the clock.
In POWER-DOWN mode, the oscillator is turned off and none of the functions operate.
These two modes are called by two bits, IDL = PCON.O and PD = PCON.1, which are contained in the special PCON
register (address 87H). This register is not bit-addressable. Figure 41 shows the detail of the PCON register's content.
(LSB)
(MSB)
I
SMOD
HPD
Symbol
Position
SMOD
PCON.7
HPD
PCON.6
(83C154 and
83C154D only)
RPO
PCON.5
(83C154 and
83C1540 only)
X
GF1
GFO
PO
IOL
PCON.4
PCON.3
PCON.2
PCON.1
PCON.O
RPD
x
GF1
GFO
PD
IDL
I
Function
Double Baud rate bit. When set to a 1, the baud rate is doubled when the
serial port is being used in either modes 1, 2 or 3.
Hard Power Down bit. Setting this bit allows CPU to enter in Power Down
state on an external event (1 to 0 transition) on bit T1 (P3.5) the CPU quit the
Hard Power Down mode when bit T1 (P3.5) go high or when reset is
activated.
Recover from idle or Power Down bit. When 0 RPD has no effect. When 1,
RPD permits to exit from idle or Power Down with any non enabled interrupt
source (except timer 2). In this case the program start at the next address.
When interrupt is enabled the appropriate interrupt routine is serviced.
(Reserved)
General-purpose flag bit.
General-purpose flag bit.
Power Down bit. Setting this bit activates power down operation.
Idle mode bit. Setting this bit activates idle mode operation
Figure 41 : PC ON Power Control Register.
Idle Mode
Entry into this mode is effective when an instruction sets bit IDL = PCON.O of register PCON (87H) to 1. In this
mode only the CPU is no longer driven by the clock. However, its state before execution of the IDLE activation
instruction is fully stored: the stack pointer, Program Counter, Program Status Word, Accumulator and all the other
registers conserve their data during the IDLE mode. The ports maintain their data and the ALE and PSEN are at
level 1.
• Exit from IDLE mode is controlled by register IE for the 80C51/C52 and register IE and bit RPD of register PCON
for the 83C154 and the 83C154D.
Exit from Idle Mode on the 80C51 and 80C52
There are two possibilities for exiting this mode: by interrupt or by clearing the circuit (reset).
• When an interrupt is activated, bit IDL is set to zero and the interrupt is serviced. Return to the main program is
effective as soon as instruction RETI has been executed. The next instruction to be executed is that immediately
following the IDLE activation instruction.
The flag bits GFO and GF1 can be used to give an indication if an interrupt occured during normal operation or
during an IDLE. For example, an instruction that activates IDLE can also set one or both flag bits. When IDLE is
terminated by an interrupt, the interrupt service routine can examine the flag bits.
• The other way of quitting IDLE mode is by resetting via the RST input. The oscillator operates freely, the reset execution time is only 24 clock periods. The reset redefines all the SFRs but not the internal RAM.
Exit from Idle Mode on the 83C154 and 83C154D
• Exit from IDLE mode on the 80C154 series is controlled by register IE and bit RPD (PCON.5) of register PCON.
For RPD = 0, exit conditions are identical to those of the 80C51/C52. For RPD = 1, whether or not the interrupts
are enabled, an interrupt request terminates IDLE mode execution. If IE = 0 and RPD = 1, the program counter
with the instruction following the IDLE activation instruction. If IE = 1 and RPD = 1, the program executes the interrupt. If no interrupt request is made while the mode is activated, only a reset via the RST input can terminate
this mode.
4-37
II
MHSC51
ENTRY CONDITIONS
IDLE
SOFTWARE
EXIT CONDITIONS
IDL
RPD
INTERRUPTS
1
0
If authorized
RST
yes
1
1
Authorized or not
yes
Figure 42 : IDLE Mode Operation.
Power-down Mode
• In this mode, the oscillator is turned off and all the functions that were driven by the oscillator are frozen. However,
the internal RAM, the special SFR registers and the ports maintain their data throughout operation in POWERDOWN mode and during this time, signals ALE and PSEN are configured in the low state.
80C511C52
Entry into this mode is effective when an instruction writes a 1 in bit PO = PCON.1 of register PCON (87H).
• The only way to exit from this mode is to activate a reset via the RST input. This reset reconfigures the special
SFR registers and the ports but not the internal RAM.
83C154183C1540
• Unlike the 80C51 or the 80C52, TIMERs 0 and 1 and the UART can operate if an external clock is connected to
one of the inputs TO or T1.
Control of this mode can be done by :
- software by bits RPD, PO and register IE,
or by
- hardware by bit HPD.
Hardware Control
HPD = 1 , enables this mode to be controlled by means of an external Signal connected to T1. The trailing edge of
this signal activates the POWER-DOWN mode as soon as the current instruction has been terminated. The leading
edge of this same signal or a reset enable exit from this mode. Interrupt requests, even if enabled, do not permit exit
from the mode.
Software Control
• Entry into the mode is effective when an instruction writes a 1 in bit PO = PCON.1 of register PCON (87H). Exit
from the mode is controlled by bit RDP of register PCON and register IE.
If RPD = 0 and if the interrupts are enabled or RPD
terminates the mode.
= 1 and the interrupts are not enabled, an interrupt request
If this mode is terminated by an enabled interrupt, the next instruction to be executed an LCALL to the relevant
interrupt routine. If the mode is terminated by an interrupt that is not enabled and RPD = 1, the next instruction to
be executed is that immediatly following the power-down activation instruction. The exit-time from the mode
depends on the oscillator's start-up time and the frequency. Exit from the mode does not modify the data of the
internal RAM, the special SFR registers and the ports.
• If no interrupt request is made, or if RPD = IE = 0 (interrupts not enabled), the POWER-DOWN mode can only be
terminated by a reset. This operation reconfigures the special SFR registers and the ports, but not the internal RAM.
Software and Hardware Control
• This mode can be controlled by mixing software and hardware commands.
Entry to the mode can made either by setting bit PO to 1 or by setting bit HPD to 1 and presenting a trailing edge
on T1.
• Exit from this mode is effective if the software and hardware end-of-mode conditions are met: a leading edge on
T1 and an interrupt request. If these conditions are not satisfied, only a reset can terminate the mode.
Figure 43 summarizes the different types of operation of this mode.
4-38
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ MHS C51
ENTRY CONDITIONS
POWER-DOWN
HPD
PO
1
SOFTWARE
0
1
0
HARDWARE
1
0
1
1
SOFTWARE and
HARDWARE
1
1
T1
X
X
T1
X
X
X
OUTPUT CONDITIONS
RPD
INTERRUPTS
0
If authorized
1
Authorized or not
X
If authorized
0
1
Authorized or not
RST
Yes
Yes
Yes
Yes
Yes
x = without action.
Figure 43 : Software and Hardware Operation.
Voltage Reduction in Power-down Mode
• In the POWER-DOWN mode of operation, Vee can be reduced as low as 2 V. Care must be taken, however, to
ensure that Vcc is not reduced before the POWER-DOWN mode is invoked, and that Vee is restored to its normal
operating level, before the POWER-DOWN mode is terminated. The reset that terminates POWER-DOWN also
frees the oscillator. The reset should not be activated before Vee is restored to its normal operating level, and must
be held active long enough to allow the oscillator to restart and stabilize (normally less than 10 msec).
• The utilization of the interrupts, the TIMERs and UART in POWER-DOWN mode is only guaranteed within the limit
of the Vee specifications.
Table 5 shows the state of the signals during POWER-DOWN and IDLE mode.
PROGRAM
MEMORY
Idle
Internal
Idle
External
Power Down
Internal
External
Power Down
MODE
ALE
PSEN
PORTO
1
1
0
0
1
1
0
0
Port Data
Floating
Port Data
Floating
PORT1
PORT2
Port
Port
Port
Port
Port Data
Address
Port Data
Port Data
Data
Data
Data
Data
PORT3
Port
Port
Port
Port
Data
Data
Data
Data
Table 5 : Status of the External Pins during Idle and Power Down Modes.
OSCILLATOR CHARACTERISTICS
The oscillator is integrated in the microcontroller and consists of an inverting amplifier of which the input is XTAL1
and the output is XTAL2 (figure 44). A quartz crystal or a ceramic resonator (parallel resonance) must be used.
Vee
4002
XTAL2------QUARTZaMrW..
OOCSWIC
RESOI'UIIOR
Figure 44 : Oscillator Utilization Configuration.
The MHS C51 family is able to turn off its oscillator under software control (by writing a 1 to the PO bit in PCON). In
the MHS C51 family the internal clocking circuitry is driven by the signal at XTAL1.
4-39
n
- - - - - - - - - - - - - - - MHS C51
The feedback resistor R in figure 45 consists of parallele n- and p-channel FETs controlled by the PD bit, such that
R is opened when PD = 1. The diodes D1 and D2 which act as clamps to Vee and Vss, are parasitic to the R FETs.
Vee
10 INTEFINAI..
l1MING 0<15
R1
XW-1
40011
pfi-----I
Vss
Figure 45 : Oscillator Circuit Diagram.
4-40
MHSC51
MHS C51 microcontrollers have a wide operating range as, depending on the version, they operate from 0 to 16 MHz.
Consequently, the value of capacitors C1 and C2 is determined by the nomograph below.
C1 == C2(PF)
400
350
300
250
200
150
100
50
...
0
I
u
"' ..... "'~
g
f
0
~
Nomograph giving the value of C1 and C2 according to the frequency.
If an external circuit is to be driven by the MHS C51 microcontroller's clock, it must be connected to input XTAL 1, in
which case XTAL2 is floating (Figure 46).
BOC51
NC- XTAL2
~-----1 Xl1Il.l
t
vss
CMOSGRE
Figure 46 : Driving the MHS C51 Parts with an External Clock Source.
INTERNAL TIMING
Figures 47 through 50 show when the various strobe and port signals are clocked internally. The figures do not show
rise and fall times of the signals, nor do they show propagation delays between the XTAL2 signal and the events at
other pins.
Rise and fall times are dependent on the extemalloading that each pin must drive. They are often taken to be something in the neighbourhood of 10 nsec, measured between 0.8 V and 2.0 V.
Propagation delays are different for different pins. For a given pin they vary with pin loading, temperature, VCC and
manufacturing lot. If the XTAL2 waveform is taken as the timing reference, propagation delays may vary from 25 to
125 nsec.
4-41
-
_ _ _ _ _ _ _ _ _ _ _ _ _ _ MHS C51
The CA Timings section of the data sheets do not reference any timing to the XTAL2 waveform. Rather, they relate
the critical edges of control and input signals to each other. The timings published in the data sheet include the effects
of propagation delays under the specified test conditions.
I~A~2Ism~31~4Ism~51~61~~1 I~A~21
I ~A~1
P11P2 P11P2 P11P2 P11P2 P11P2 P11P2 P11P2 P11P2
XTAL2:
----..II
I
I
L
I L
I
-I
-I
po:~.1--f~1 ~ I . ~I ~ I
PSEN:
OOA
!=SAMPLED
III
I
P2:
DATA
DATA
=! ~SAMPLED
-1 ~I ~ ~
!=SAMPLED
PCH
PCH
OUT
OUT
PCH
OUT
Figure 47 : External Program Memory Fetches.
I
STATE51~~61 STATE 1 smTE2 1~ATE31 ~ATE41 5rATE51
I ~A~41
~I~ ~I~ ~I~ ~1P2 ~I~ ~I~ ~I~ ~1P2
XTAL2 :
L
ALE :
I
~------------~
PO: -------I DPlORRI
OUT
~:
POfOR
P2SFR
-"::j
I
DPH OR P2 sm OUT
Figure 48 : External Data Memory Read Cycle.
4-42
PCLOUTIF
q~~
tFUlAT~
L
!
POfOR
P2SFR
--___________________________ MHSC51 _____________________________
41
6 1 STATE' I ST.AJE 21 STATE 3 1STAlE 41 STATE 51
51 STATE
~I~ ~I~ ~I~ ~I~ ~I~ ~I~
STATE
STATE
I ~I~ ~I~
XTAL2:
L
1'0:-----1 DPLORRI
DATA OUT
OUT
P2
PCHOR
P2SFR
DPH OR P2 SFR OUT
II
Figure 49 : Extemal Data Memory Write Cycle.
I~I~41 ~I~51 ~I~ 1~I~ I~I~21 ~I~ 1~I~41 ~I~51
srATE
srATE
STATE 6 srATE 1 srATE
srATE 3 STATE
srATE
XTAL2:
INPUlS SAMPLED :
PO,P1-1
-----Iy=[,P1
-
MOl PORT. SAC :
SERIAL PORT
SHIFT ClOCK
(MODE 0)
P2. P3. RST
P2.P3.RST
OLD DATA
--I
~
==r1-
NEW DATA
I-- AXD PIN SAMPLED
Figure 50 : Port Operation.
4-43
~-----,I
RXD SAMPLED -I
I---
MHSC51
II
MHS C51 PIN DESCRIPTIONS
VCC : Supply voltage.
VSS : Circuit ground potential.
Port 0 : Port 0 is an 8-bit open drain bidirectional I/O port. As an open drain output port it can sink 8 LS TTL loads.
Port 0 pins that have 1s written to them float, and in that state will function as high-impedance inputs. Port 0 is also
the multiplexed low-order address and data bus during accesses to external memory. In this application it uses strong
internal pullups when emitting 1's. Port 0 also emits code bytes during program verification. In that application, external
pullups are required.
Port 1 : Port 1 is an 8-bit bidirectional I/O port with internal pullups. The port 1 output buffers can sink/source 3 LSTTL
loads. Port 1 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used
as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (ilL, on the data sheet) because
of the internal pullups.
In the 80C52, 83C154 and 83C154D, pins P1.0 and P1.1 also serve the alternate functions of T2 and T2EX. T2 is
the Timer 2 external input. T2EX is the input through which a Timer 2 "capture" is triggered.
Port 2 : Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source 3 LSTTL
loads. Port 2 emits the high-
Function :
Description:
Add
ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumulator.
The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or bit
3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow
occured.
OV is set there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6 ;
otherwise OV is cleared. When adding signed integers, OV indicates a negative number
produced as the sum of two positive operands, or a positive sum from two negative operands.
Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.
Example:
The Accumulator holds OC3H (11000011 B) and register 0 holds OAAH (1010101 OB). The instruction,
ADDA, RO
will leave 6DH (01101101 B) in the Accumulator with the AC flag cleared and both the carry flag
and OV set to 1.
ADDA,Rn
Byte:
Cycle:
1
1
Encoding:
1001011 r r r
Operation:
ADD
(A) f-- (A) + (Rn)
I
ADD A, direct
Bytes:
R
2
Cycle:
Encoding:
10 0 1 0 10 1 0 11
Operation:
ADD
(A) f-- (A) + (direct)
direct address
ADDA,@RI
Byte:
Cycle:
Encoding:
1001011 1 1 i
I
Operation:
ADD
(A) f-- (A) + (RI)
ADDA, # data
ADD A, # data
Bytes:
2
Cycle:
o1
o 01
Encoding:
10
Operation:
ADD
(A) f-- (A) + # data
01 0
Immediate data
5-22
MHSC51
ADDC A,
Function:
Description:
Add with Carry
AD DC simultaneously adds the byte variable indicated, the carry flag and the Accumulator contents, leaving the result in the Accumulator. The carry and auxiliary-carry or bit flags are set,
respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occured.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of
bit 6 ; otherwise OV is cleared. When adding signed intergers, OV indicates a negative number
produced as the sum of two positive operands or a positive sum from two negative operands.
Four source operand addressing mode are allowed; register, direct, register-indirect, or immediate.
Example:
The Accumulator holds OC3H (11000011 B) and register 0 holds OAAH (1010101 OB) with the
carry flag set. The instruction,
ADDCA, RO
will leave 6EH (0110111 OB) in the Accumulator with AC cleared and both the Carry flag and
OV set to 1.
ADDCA, RN
Byte:
Cycle:
I
Encoding:
10 0 1 1 11 r r r
Operation:
AD DC
(A) ~ (A) + (C) + (Rn)
ADDC A, direct
Bytes:
Cycle:
2
Encoding:
10 0 1 11 0 1 0 11
Operation:
AD DC
(A) ~ (A) + (C) + (direct)
ADDCA,@RI
Byte:
Cycle:
1
Encoding:
10 0 1 110 1 1 il
Operation:
ADDC
(A) ~ (A) + (C) + ((Ri})
ADDC A, #data
Bytes:
Cycle:
Encoding:
Operation:
direct address
2
10
o1
110 1
o 01
immediate data
AD DC
(A) ~ (A) + (C) + # data
5-23
MHSC51
AJMP addr11
Function:
Description:
Example:
Absolute Jump
AJMP transfers program execution to the indicated address, which is formed at run-time by concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits 7-5,
and the second byte of the instruction. The destination must therefore be within the same 2 K
block of program memory as the first byte of the instruction following AJMP.
The label" JMPADR" is at program memory location 0123H. The instruction,
AJMPJMPADR
is a location 0345H and will load the PC with 0123H.
ADD A, direct
Bytes:
Cycles :
2
2
I0
Encoding:
F10 a9 a8
Operation:
AJMP
(PC) ~ (PC) + 2
(PC1O-0) ~ page address
0
0
0
la7 a6 a5 a41 a3 a2 a1 aO
1
I
ANL ,
Function:
Logical-AND for byte variables
Description:
ANL performs the bitwise logical-AND operation between the variables indicated and stores the
results in the destination variable. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can be the Accumulator or immediate data. Note:
When this instruction is used to modify an output port, the value used as the original port data
will be read from the output data latch, not the input pins.
Example:
If the Accumulator holds OC3H (11000011 B) and register 0 holds 55H (01010101 B) then the
instruction,
.
ANLA, RO
will leave 41H (01000001 B) in the Accumulator.
When the destination is a directly addressed byte, this instruction will clear combinations of bits
in any RAM location or hardware register. The mask byte determining the pattern of bits to be
cleared would either be a constant contained in the instruction or a value computed in the Accumulator at run-time. The instruction,
ANL P1, #011100118
will clear bits 7, 3, and 2 of output port 1.
ANLA,RN
Bytes:
Cycles:
Encoding:
Operation:
1 0 1 11 r r rl
10
ANL
(A) ~ (A) 1\ (Rn)
ANL A, direct
Bytes :
2
Cycles:
Encoding:
Operation:
1 0 11 0 1 0 11
10
ANL
(A) ~ (A) 1\ (direct)
direct address
5-24
MHSC51
ANLA,@RI
Byte:
Cycle:
1
1
Encoding:
10 1 0 11 0 1 1 il
Operation:
ANL
(A) <- (A) /\ ((Ri))
ANLA, #DATA
Bytes:
Cycle:
2
Encoding:
10 1 0 11 0 1 0 01
Operation:
ANL
(A) <- (A) /\ # data
ANL direct, A
Bytes:
Cycle:
immediate data
2
1
o1
Encoding:
1 0 11 0
10
Operation:
ANL
(direct) <- (direct) /\ (A)
01
direct address
ANL direct, # data
Bytes:
3
Cycles:
2
Encoding:
1 0 11 0011 1
10
Operation:
ANL
(direct) <- (direct) /\ # data
direct address
5-25
immediate data
1
Uih'1lrn
MIS
MHSC51
ANL C,
Function:
Description:
Logical-AND for bit variables
If the Boolean value of the source bit is logical 0 then clear the carry flag; otherwise leave the
carry flag in its current state. A slash (" / ") preceding the operand in the assembly language
indicates that the logical complement of the addressed bit is used as the source value, but the
source bit itself is not affected. No other flags are affected.
Only direct addressing is allowed for the source operand.
Example:
Set the carry flag if, P1.0
= 1, ACC.7 = 1, and OV = 0 :
MOV C, P1.0
; LOAD CARRY WITH INPUT PIN STATE
ANLC,ACC.7
; AND CARRY WITH ACCUM. BIT 7
ANLC,/OV
; AND WITH INVERSE OF OVERFLOW FLAG
ANL C, bit
Bytes:
2
Cycles:
2
Encoding:
11
Operation:
ANL
(C) f- (C)
o0
bit address
010 0 1 01
1\
(bit)
ANL C,/bit
Bytes:
2
Cycles:
2
Encoding:
11
Operation:
ANL
(C) f- (C)
o1
bit address
110 0 0 01
1\
(bit)
CJNE , , rei
Function:
Description:
Compare and Jump if Not Equal
CJNE compares the magnitudes of the first two operands, and branches if their values are not
equal. The branch destination is computed by adding the signed relative-displacement in the
last instruction byte to the PC, after incrementing the PC to the start of the next instruction. The
carry flag is set if the unsigned integer value of is less than the unsigned integer
value of ; otherwise, the carry is cleared. Neither operand is affected.
The first two operands allow four addressing mode combinations: the Accumulator may be
compared with any directly addressed byte or immediate data, and any indirect RAM location
or working register can be compared with an immediate constant.
Example:
The Accumulator contains 34H, register 7 contains 56H. The first instruction in the sequence,
CJNE
R7, #60H, NOT_EO
; R7 = 60H
; IF R7 < 60H
; R7 > 60H
JC
sets the carry flag and branches to the instruction at label NOT-EO. By testing the carry flag,
this instruction determines whether R7 is greater or less than 60H.
If the data being presented to Port 1 is also 34H, then the instruction,
WAIT: CJNE A, P1, WAIT
clears the carry flag and continues with the next instruction in sequence, since the Accumulator
does equal the data read from P1. (If some other value was being input on P1, the program will
loop at this point until the P1 data changes to 34H).
5-26
MHSC51
CJNE A, direct, rei
Bytes:
3
Cycles:
2
Encoding:
'11-0-1-1'1-0-1-0---'11
Operation:
(PC) i- (PC) + 3
IF (A) <> (direct)
direct address
reI. address
THEN
(PC) i- (PC) + relative offset1
IF (A) < (direct)
THEN
(C)
i-
(C)
i-
ELSE
0
CJNE A, # data, rei
Bytes:
3
Cycles:
2
Encoding:
'11-0-1-1'1-0-1-0----,01
Operation:
(PC) i- (PC) + 3
IF (A) <> (data)
immediate data
reI. address
THEN
(PC)
IF (A) < data
(PC) + relative offset
i-
THEN
(C)
i-
1
ELSE
(C) i- 0
CJNE Rn, # data, rei
Bytes:
3
Cycles:
2
Encoding:
'11- -0 1- 1 '11-r-r---'r1
Operation:
immediate data
II
reI. address
(PC) i - (PC) + 3
IF (Rn) <> data
THEN
(PC) i- (PC) + relative offset
IF (Rn) < data
THEN
(C)
i-
(C)
i-
ELSE
0
CJNE @Ri, # data, rei
Bytes:
3
Cycles:
2
Encoding:
'-11-0-1-1'"1-0-1-1---'i1
Operation:
(PC) i- (PC) + 3
IF (Ri) <> data
immediate data
reI. address
THEN
(PC) i - (PC) + relative offset
IF ((Ri)) < data
THEN
(C)
i-
(C)
i-
ELSE
0
5·27
fffi.~MIS
MHSC51
CLR A
Function:
Description :
Example:
Bytes:
Cycles:
Clear Accumulator
The Accumulator is cleared (all bits set on zero). No flags are affected.
The Accumulator contains 5CH (010111 OOB). The instruction,
CLRA
Will leave the Accumulator set to OOH (OOOOOOOOB).
1
1
Encoding:
11 1 1 110
Operation:
CLR
0 01
(A)~O
CLR bit
Function :
Description:
Example:
Clear bit
The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on
the carry flag or any directly addressable bit.
Port 1 has previously been written with 50H (01011101 B). The instruction,
CLR P1.2
will leave the port set to 59H (01011001 B).
CLRC
Bytes:
Cycles:
II
Encoding:
11 1 0 01 0
Operation:
CLR
o1
11
o1
01
(C)~O
CLR bit
Bytes:
2
Cycles:
Encoding:
Operation:
11 1 0 01 0
bit address
CLR
(bit)~O
CPLA
Function:
Descritpion :
Example:
Bytes:
Cycles :
Complement Accumulator
Each bit of the Accumulator is logically complemented (one's complement). Bits which
previously contained a one are changed to a zero and vice-versa. No flags are affected.
The accumulator contains 5CH (010111 OOB). The instruction,
CPLA
will leave the Accumulator set to OA3H (10100011 B).
1
Encoding :
11 1 1 1 10
Operation:
CPL
0 01
(A)~(A)
5-28
MHSC51
CPL bit
Function:
Description:
Example:
Complement bit
The bit variable specified is complemented. A bit which had been a one is changed to zero
and vice-versa. No other flags are affected. CLR can operate on the carry or any directly
addressable bit.
Note: When this instruction is used to modify an output pin, the value used as the original
data will be read from the output data latch, not the input pin.
Port 1 has previously been written with 5BH (01011101 B). The instruction sequence.
CPL P1.1
CPL P1.2
will leave the port set to 5BH (01011011 B).
CPLC
Bytes:
Cycles:
o1
Encoding:
11
Operation:
CPL
11 0
o1
11
o1
01
(C)~(C)
CPL bit
Bytes:
Cycles:
Encoding:
Operation:
2
1
11
o1
11 0
bit address
CPL
(bit) ~ (bit)
5-29
MHSC51
DA A
Function:
Description:
Decimal-adjust Accumulator for Addition
DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two
variables (each in packed-BCD format), producing two four-bit digits, Any ADD or ADDC instruction may have been used to perform the addition.
If Accumulator bits 3-0 are greater than nine (xxxx1 01 0-xxxx1111), or if the AC flag is one, six
is added to the Accumulator producing the proper BCD digit in the low-order nibble. This internal
addition would set the carry flag if a carry-out of the low-order four-bit field propagated through
all high-order bits, but it would not clear the carry flag otherwise.
If the carry flag is now set, or if the four high-order bits now exceed nine (101 Ox xxx - 111 xxxx),
these high-order bits are incremented by six, producing the proper BCD digit in the high-order
nibble. Again, this would set the carry flag if there was a carry-out of the high-order bits, but
wouldn't clear the carry. The carry flag thus indicates if the sum of the original two BCD variables
is greater than 100, allowing multiple precision decimal. OV is not affected.
All of this occurs during the one instruction cycle. Essentially, this instruction performs the
decimal conversion by adding OOH, 06H, 60H, or 66H to the Accumulator, depending on initial
Accumulator and PSW conditions.
Note: DA A cannot simply convert a hexadecimal number in the Accumulator to BCD notation,
nor does DA A apply to decimal substraction.
Example:
The Accumulator holds the value 56H (0101011 OB) representing the packed BCD digits of the
decimal number 56. Register 3 contains the value 67H (01100111 B) representing the packed
BCD digits of the decimal number 67. The carry flag is set. The instruction sequence.
ADDC A, R3
DA
A
will first perform a standard twos-complement binary addition, resulting in the value OBEH
(10111110), in the Accumulator. The carry and auxiliary carry flags will be cleared.
The decimal Adjust instruction will then after the Accumulator to the value 24H (001001 OOB)
indicating the packed BCD digits of the decimal number 24, the low-order two digits of the
decimal sum of 56,67, and the carry-in. The carry flag will set by the Decimal Adjust instruction,
indicating that a decimal overflow occured. The true sum 56,67, and 1 is 124.
BCD variables can be incremented or decremented by adding 01 H or 99H. If the Accumulator
initially holds 30H (representing the digits of 30 decimal), then the instruction sequence,
ADD A, #99H
DA
A
will leave the carry set and 29H in the Accumulator, since 30 + 99 = 129. The low-order byte of
the sum can be interpreted to mean 30 - 1 = 29.
Bytes:
Cycles:
Encoding:
Operation :
1
11 1 0 110
a
01
DA
- contents of Accumulator are BCD
IF [[(A3 - 0) > 9] V [(AC) = 1]]
THEN (AJ - 0) (--- (A3 - 0) + 6
AND
IF [[(A7 - 4) > 9] V [(C) = 1]]
THEN (A7 - 4) (--- (A7 - 4) + 6
ffii.-j1l1S
5-30
MHSC51
DEC byte
Function :
Description:
Decrement
The variable indicated is decremented by 1. An original value of OOH will underflow to OFFH.
No flags are affected. Four operand addressing modes are allowed: accumulator, register,
direct, or register-indirect.
Note: When this instruction is used to modify an output port, the value used as the original port
data will be read from the output data latch, notthe input pins.
Example:
Register 0 contains 7FH (011111118). Internal RAM locations 7 EH and 7FH contain OOH and
40H, respectively. The instruction sequence.
DEC@RO
DEC RO
DEC@RO
will leave register 0 set to 7EH internal RAM locations 7EH and 7FH to OFFH and 3FH.
DEC A
Bytes:
Cycles:
1
Encoding : 1'-O-0-0-1-r10 --0-'01
Operation :
DEC
(A) ~ (A)-1
DECRn
Bytes:
Cycles:
Encoding:
10 0 0 1 [1
Operation :
DEC
(Rn) ~ (Rn) - 1
r r rl
DEC direct
Bytes:
Cycles:
2
Encoding:
10 0 0 11 0 1 0 11
Operation:
DEC
(direct)
DEC@RI
Bytes:
Cycles:
Encoding:
Operation :
~
direct address
(direct) - 1
1
'-10-0-0-1-r[-0-1-1-'il
DEC
((Ri))
~
((Ri)) - 1
5-31
MHSC51
DIVAB
Function :
Description:
Example:
Bytes:
Cycles:
Encoding:
Operation:
Divide
DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit integer in register B. The Accumulator receives the integer part of the quotient; register 8 receives
the integer remainder. The carry and OV flags will be cleared.
Exception: If B had originally contained OOH ; the values returned in the Accumulator and Bregister will be undefined and the overflow flag will be set. The carry flag is cleared in any case.
The Accumulator contains 251 (OFBH or 11111011 B) and B contains 18 (12H or 0001 0010B).
The instruction,
DIVAB
will leave 13 in the Accumulator (ODH or 000011 01 B) and the value 17 (11 H or 0001 0001 B) in
B, since 251 = (13 x 18) + 17. Carry and OV will both be cleared.
1
4
'11-0-0-0'1-0-0--'01
DIV
(A)15 -8
~
(A)/(B)
(8)7-0
DJNZ ,
Function:
Description :
Example:
Decrement and Jump if Not Zero
DJNZ decrements the location indicated by 1, and branches to the address indicated by the
second operand if the resulting value is not zero. An original value of OOH will underflow to OFFH.
No flags are affected. The branch destination would be computed by adding the signed relative-displacement value in the last instruction byte to the PC, after incrementing the PC to the
first byte of the following instruction.
The location decremented may be a register or directly addressed byte.
Note: When this instruction is used to modify an output port, the value used as the original port
data will be read from the output data latch, not the input pins.
Internal RAM locations 40H, 50H, and SOH contain the values 01 H, 70H, and 15H, respectively.
the instruction sequence,
DJNZ 40H, LABEL_1
DJNZ 50H, LABEL_2
DJNZ SOH, LABEL_3
will cause a jump to the instruction at label LABEL2 with the values OOH, SFH, and 15H in the
three RAM locations. The first jump was not taken because the result was zero.
This instruction provides a simple way of executing a program loop a given number of times,
or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction.
The instruction sequence,
MOV R2,#8
TOGGLE:
CPL
P1.7
DJNZ R2, TOGGLE
will toggle P1. 7 eight times, causing four output pulses to appear at bit 7 of output Port 1. Each
pulse will last three machine cycles; two for DJNZ and one to after the pin.
5-32
MHSC51
DJNZ Rn, rei
Bytes:
Cycles:
2
2
Encoding:
1'1-1-0-1'1-1-r-r---'rl
Operation:
OJNZ
(PC) ~ (PC) + 2
(Rn) ~ (Rn) - 1
IF (RN) > 0 or (Rn) < 0
THEN
(PC) ~ (PC) + rei
reI. address
DJNZ direct, rei
Bytes:
Cycles:
3
2
Encoding:
r-11-1-0-1"'-10-1-0--'11
Operation :
OJ NZ
(PC) ~ (PC) + 2
(direct) ~ (direct) - 1
IF (direct) > 0 or (direct) < 0
THEN
(PC) ~ (PC) + rei
direct address
reI. address
INC
Function:
Description :
Example:
Increment
INC increments the indicated variable by 1. An original value of OFFH will overflow to OOH. No
flags are affected. There addressing modes are allowed: register, direct, or register-indirect.
Note: When this instruction is used to modify an output port, the value used as the original port
data will be read from the output data latch, notthe input pins.
Register 0 contains 7EH (01111111 OB). Internal locations 7EH and 7FH contain OFFH
and 40H, respectively. The instruction sequence,
INC@RO
INCRO
INC@RO
will leave register 0 set to 7FH and internal RAM locations 7EH and 7FH holding (respectively)
OOH and 41H.
INCA
Bytes:
Cycles:
Encoding:
Operation:
1
r-Io-o-o-o"'-I0--0--'01
INC
(A) ~ (A) + 1
INCRn
Bytes:
Cycles:
Encoding:
Operation :
1
""10-0-0-0""T1-1-r-r---'rl
INC
(Rn)
~
(Rn) + 1
5-33
~
~
MHSC51
INC direct
Bytes:
Cycles:
Encoding:
Operation:
2
1
'10-0-0-0-'-10-1-0--'11
INC
(direct)
f--
direct address
(direct) + 1
INC@RI
Bytes:
Cycles:
Encoding:
Operation:
1
'10-0-0-0'1-0-1-1-'i1
INC
((Ri))
f--
((Ri)) + 1
INC DPTR
Function:
Description:
Increment Data Pointer
Incrementthe 16-bit data pointer by 1.A 16-bit increment (modulo 2 16) is performed; an overflow
of the low-order byte of the data pointer (DPL) from OFFH to OOH will increment the high-order
byte (DPH). No flags are affected.
This is the only 16-bit register which can be incremented.
Example:
Registers DPH and DPL contain 12H and OFEH, respectively. The instruction sequence,
INC DPTR
INC DPTR
INC DPTR
will change DPH and DPL to 13H and 01 H.
Bytes:
Cycles:
Encoding:
Operation:
1
2
'11-0-1-0'1-0-0-1-'11
INC
(DPTR)
f--
(DPTR) + 1
JB bit,rel
Function:
Descritpion :
Jump if Bit set
If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the Signed relative-displacement in the
third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction.
The bit tested is not modified. No flags are affected.
Note: When this instruction is used to test an output pin, the value used as the original data
will be read from the output data latch, not the input pin.
Example:
The data present at input port 1 is 1100101 OB. The Accumulator holds 56 (0101011 OB). The
instruction sequence.
JB P1.2, LABEL 1
JB ACC.2, LABEL 2
will cause program execution to branch to the instruction at label LABEL 2.
MHSC51
Bytes:
Cycles:
3
2
Encoding : 1'0-0-1-0'1-0- -0 0----,01
Operation:
bit address
reI. address
JB
(PC) f- (PC) + 3
IF (bit); 1
THEN
(PC) f- (PC) + rei
JBC bit, rei
Function:
Description:
Jump if Bit is set and Clear bit
If the indicated bit is a one, branch to the address indicated; otherwise proceed with the next
instruction. The bit will not be cleared if it is already a zero. The branch destination is computed
by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. No flags are affected.
Note: When this instruction is used to test an output pin, the value used as the original data
will be read from the output data latch, not the input pin.
Example:
The Accumulator holds 56H (0101011 OB). The instruction sequence,
JBC ACC.3, LABEL 1
JBC ACC.2, LABEL 2
will cause program execution to continue at the instruction identified by the label LABEL2, with
the Accumulator modified to 52H (0101001 OB).
Bytes:
Cycles:
3
2
Encoding:
10 0 0 110 0 0 01
Operation:
JBC
(PC) f- (PC) + 3
IF (bit) = 1
THEN
(bit) f-O
(PC) f- (PC) + rei
bit address
reI. address
JC rei
Function:
Description :
Example:
Jump if Carry is set
If the carry flag is set, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. No flags are affected.
The carry flag is cleared. The instruction sequence,
JC
CPL
JC
LABEL 1
C
LABEL 2
will set the carry and cause program execution to continue at the instruction identified by the
label LABEL2.
Bytes:
Cycles:
2
2
Encoding:
1'-0-1-0-0'1-0-0-0---'01
Operation :
JC
(PC) f- (PC) + 2
IF (C) = 1
THEN
(PC) f- (PC) + rei
reI. address
5-35
MHSC51
JMP @A + DPTR
Function:
Jump indirect
Description:
Add the eight-bit unsigned contents of the Accumulator with the sixteen-bit data pointer, and
load the resulting sum to the program counter. This will be the address for subsequent instruction
fetches. Sixteen-bit addition is performed (modulo 2 16 ) : a carry-out from the low-order eight bits
propagates through the higher-order bits. Neither the Accumulator nor the Data Pointer is altered. No flags are affected.
Example:
An even number from 0 to 6 is in the Accumulator. The following sequence of instructions will
branch to one of four AJMP instructions in a jump table starting at JMP-TBL :
JMP_TBL:
MOV
DPTR, #JMP_TBL
JMP
AJMP
AJMP
AJMP
AJMP
@A+DPTR
LABELO
LABEL1
LABEL2
LABEL3
If the Accumulator equals 04H when starting this sequence, execution will jump to label LABEL2.
Remembers that AJMP is a two-byte instruction, so the jump instructions start at every other
address.
Bytes:
Cycles:
1
2
Encoding:
10 1 1 110 0 1 11
Operation:
JMP
(PC)
f-
(A) + (DPTR)
JNB bit, rei
Function:
Jump if Bit not set
Description:
If the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in
the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected.
Example:
The data present at input port 1 is 1100101 OB. The Accumulator holds 56H (0101011 OB). The
instruction sequence,
JNB P1.3, LABEL 1
JNB ACC3, LABEL2
will cause program execution to continue at the instruction at label LABEL2.
Bytes:
Cycles:
3
2
Encoding:
"0-0-1-1'[-0-0-0-0',
Operation:
JNB
(PC) f- (PC) + 3
IF (bit) = 0
THEN (PC)
f-
bit address
(PC) + rei
5-36
reI. address
MHSC51
JNC rei
Function:
Description:
Example:
Jump if Carry not set
If the carry flag is a zero, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the
second instruction byte to the PC, after incrementing the PC twice to point to the next instruction.
The carry flag is not modified.
The carry flag is set. The instruction sequence,
JNC LABEL1
CPLC
JNC LABEL2
will clear the carry and cause program execution to continue at the instruction identified by the
label LABEL2.
Bytes:
Cycles:
2
2
Encoding:
rl0-1-0-1'I0-0-0---'01
Operation:
JNC
(PC) ~ (PC) + 2
IF (C) = 0
THEN (PC)
~
reI. address
(PC) + rei
JNZ rei
Function
Description :
Example:
Jump if Accumulator Not Zero
If any bit of the Accumulator is a one, branch to the indicated address; otherwise proceed with
the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The Accumulator
is not modified. No flags are affected.
The Accumulator originally holds OOH. The instruction sequence,
JNZ LABEL1
INCA
JNZ LABEL2
will set the Accumulator to 01 H and continue at label LABEL2.
Bytes:
Cycles:
Encoding:
Operation :
2
2
0- 1 - 1- 1'1-0-0-0---'01
rI
JNZ
(PC) ~ (PC) + 2
IF (A);t 0
THEN (PC)
~
reI. address
(PC) + rei
5-37
5
MHSC51
JZ rei
Function:
Description :
Example:
Bytes:
Cycles:
Jump if Accumulator Zero
If all bits of the Accumulator are zero, branch to the address indicated; otherwise proceed with
the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are affected.
The Accumulator originally contains 01 H. The instruction sequence.
JZ
LABEL 1
DEC
A
JZ
LABEL2
will change the Accumulator to OOH and cause program execution at the instruction identified
by the label LABEL2.
2
2
Encoding:
10 1 1 010 0 0 01
Operation:
JZ
(PC) ~ (PC) + 2
IF (A) =0
THEN (PC)
~
reI. address
(PC) + rei
LeALL addr16
Function:
Description :
Example:
Bytes:
Cycles:
Encoding:
Operation:
~--i
Long call
LCALL calls a subroutine located at the indicated address. The instruction adds three to the
program counter to generate the address of the next instruction and then pushes the 16-bit result
onto the stack (low byte first), incrementing the Stack Pointer by two. The high-order and loworder bytes of the PC are then loaded, respectively, with the second and third bytes of the LCALL
instruction. Program execution continues with the instruction at this address. The subroutine
may therefore begin anywhere in the full 64K-byte program memory address space. No flags
are affected.
Initially the Stack Pointer equals 07H. The label" SUBRTN " is assigned to program memory
location 1234H. After executing the instruction,
LCALL SUBRTN
at location 0123H, the Stack Pointer will contain 09H, intemal RAM locations 08H and 09H will
contain 26H and 01 H, and the PC will contain 1235H.
3
2
1'0-0-0-1'1-0-0-1-'01
addr15-addr8
addr7-addrO
LCALL
(PC) ~ (PC) + 3
(SP) ~ (SP) + 1
{(SP)) ~ (PC7-0)
(SP) ~ (SP) + 1
({SP)) ~ (SP15 - 8)
(PC) ~ addr15 - a
5-38
MHSC51
LJMP addr16
Function:
Long Jump
Description:
LJMP causes an unconditional branch to the indicated address, by loading the high-order and
low-order bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore be anywhere in the full 64K program memory address space. No flags
are affected.
Example:
The label" JMPADR ,. is assigned to the instruction at program memory location 1234H. The
instruction,
LJMPJMPADR
at location 0123H will load the program counter with 1234H.
Bytes:
Cycles:
3
2
Encoding:
"10-0-0-0"1-0-0-1""01
Operation:
LJMP
(PC) f- addr15·Q
addr15-addrB
addr7-addrO
MOV ,
Function:
Description:
Move byte variable
The byte variable indicated the second operand is copied into the location specified by the first
operand. The source byte is not affected. No other register or flag is affected.
This is by far the most flexible operation. Fifteen combinaisons of source and destination addressing modes are allowed.
Example:
Internal RAM location 30H holds 40H. The value of RAM location 40H is 10H.
The data present at input port 1 is 110010108 (OCAH).
MOV
MOV
MOV
MOV
MOV
MOV
RO, #30H
A, @ RO
R1, A
R,@R1
@ R1, P1
P2, P1
; RO <= 30h
; A <= 40H
; R1 <= 40h
;B<=10h
; RAM (40H) <= OCAH
; P2 # OCAH
leaves the value 30H in register 0,40H in both the Accumulator and register 1,1 OH in register
B, and OCAH (1100101 OB) both in RAM location 40H and output on port 2.
MOVA, Rn
Bytes:
Cycles:
Encoding:
Operation:
1
11 1 1 01 1 r r r
MOV
(A) f- (Rn)
I
'MOV A,direct
Bytes:
2
Cycles:
Encoding:
Operation:
11 1 1 01 0
MOV
(A) f- (direct)
0 11
direct address
-MOV A, ACC is not valid instruction.
5-39
ffit'1l1fl
II IS
MHSC51
MOVA,@RI
Bytes:
Cycles:
Encoding:
11 1 1 01 0 1 1 il
Operation:
MOV
1
(A)~(Ri)
MOVA,#data
Bytes:
Cycles:
Encoding:
1 1 110 1 0 01
10
Operation:
MOV
(A) ~#data
MOVRn,A
Bytes:
Cycles:
11 1 1 1 11 r r rl
Operation:
MOV
(Rn) ~(A)
2
2
Encoding:
1101011 r r rl
Operation:
MOV
(Rn) ~ (direct)
MOV Rn, # data
Bytes:
Cycles:
direct addr.
2
1
Encoding:
1 1 1 11 r r rl
10
Operation:
MOV
(Rn) ~#data
MOV direct, A
Bytes:
Cycles:
immediate data
1
Encoding:
MOV Rn, direct
Bytes:
Cycles:
R
2
1
immediate data
2
1
Encoding:
11 1 1 11 0
Operation:
MOV
(direct)
0 11
direct address
Encoding:
11 0 0 01 1 r r rl
direct address
Operation:
MOV
(direct)
MOV direct, Rn
Bytes:
Cycles:
~
(A)
2
2
~
(Rn)
5-40
MHSC51
MOV direct, direct
Bytes :
3
Cycles:
2
Encoding:
11
Operation:
o0
o 11
dir. addr. (src)
dir. addr. (dest)
MOV
(direct)
MOV direct, @ Ri
Bytes:
01 0
Cycles:
2
2
Encoding:
11
Operation:
MOV
~
o0
(direct)
01 0
il
direct addr.
(direct) ~ (Ri)
MOV direct, # data
Bytes:
3
Cycles:
2
Encoding:
Operation:
1 1 11 0
10
o 11
direct address
MOV
(direct)
~
# data
MOV@Ri,A
Bytes:
Cycles:
1
Encoding:
11 1 1 11 0 1 1
Operation:
MOV
q
((Ri))~(A)
MOV @ Ri, direct
Bytes:
Cycles:
2
2
o1
Encoding:
11
Operation:
MOV
((Ri))
MOV @ Ri, data
Bytes:
Cycles:
Encoding:
Operation:
~
01 0 1 1 il
direct addr.
(direct)
2
1
1 1 11 0
10
il
immediate data
MOV
((Ri)) ~ # data
5-41
immediate data
MHSC51
MOV ,
Function:
Description:
Example:
More bit data
The Boolean variable indicated by the second operand is copied into the location specified by
the first operand. One of the operands must be the carry flag; the other may be any directly
addressable bit. No other register or flag is affected.
The carry flag is originally set. The data present at input Port 3 is 11000101 B.
The data previously written to output Port 1 is 35H (00110101 B).
MOV
MOV
MOV
P1.3, C
C, P3.3
P1.2, C
will leave the carry cleared and change Port 1 to 39H (00111001 B).
MOVC, bit
Bytes:
Cycles:
2
Encoding:
11
Operation:
MOV
(C) f- (bit)
1
o
1 01 0
o
1 01
bit address
o
1 01
bit address
MOV bit, C
Bytes:
Cycles:
2
2
Encoding:
1100110
Operation:
MOV
(bit) f- (C)
MOV DPTR, # data 16
Function:
Description:
Load Data Pointer with a 16-bit constant
The Data Pointer is loaded with the 16-bit constant indicated. the 16-bit constant is loaded into
the second and third bytes of the instruction. The second byte (DPH) is the high-order byte,while
the third byte (DPL) holds the low-order byte. No flags are affected.
This is the only instruction which moves 16-bits of data at once.
Example:
The instruction,
MOV DPTR, 1234H
will load the value 1234H into the Data Pointer: DPH will hold 12H and DPL will hold 34H.
Bytes:
Cycles:
Encoding:
Operation:
H
3
2
'11-0-0-1'1-0-0-0-'01
immed. data 15-8
MOV
(DPTR) f- # data15·Q
DPH DPL f- # data15·8 # data7·Q
5-42
immed. data 7-0
MHSC51
MOVC A, @ A +
Function:
Move Code byte
Description:
The MOVC instructions load the Accumulator with a code byte, or constant from program memory. The address of the byte fetched is the sum of the original unsigned eight-bit. Accumulator
contents and the contents of a sixteen-bit base register, which may be either the Data Pointer
or the PC. In the latter case, PC is incremented to the address of the following instruction before
being added with the Accumulator; otherwise the base register is not altered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may propagate through higherorder bits. No flags are affected.
Example:
A value between 0 and 3 is in the Accumu lator. The following instructions will translate the value
in the Accumulator to one of four values defined by the DB (define byte) directive.
REL PC:
INC
MOVC
RET
DB
CB
CB
DB
A
A, @ A + PC
66H
77H
BBH
99H
If the subroutine is called with the Accumulator equal to 01 H, it will return with 77H in the Accumulator. The INC A before the MOVC instruction is needed to" get around" the RET instruction above the table. If several bytes of code separated the MOVC from the table, the
corresponding number would be added to the Accumulator instead.
MOVC A, @ A + DPTR
Bytes:
Cycles:
Encoding:
Operation:
2
'11- 0- 0 -1T"10-0-'11
MOVC
(A) ~ ((A) + (DPTR))
MOVCA,@A+PC
Bytes:
Cycles:
Encoding:
Operation :
2
1- 0 - 0- 0'1-0-0-1--'11
rI
MOVC
(PC) ~ (PC) + 1
(A) ~ ((A) + (PC))
5-43
MHSC51
MOVX ,
Function:
Description:
Example:
Move External
The MOVX instructions transfer data between the Accumulator and a byte of external data memory, hence the" X " appended to MOV. There are two types of instructions, differing in whether
they provide an eight-bit or sixteen-bit indirect address to the external data RAM.
In the first type, the contents of RO or R1 in the current register bank provide an eight-bit address
multiplexed with data on PO. Eight bits are sufficient for external I/O expansion decoding or for
a relatively small RAM array. For somewhat larger arrays, any output port pins can be used to
output higher-order address bits. These pins would be controlled by an output instruction
preceding the MOVX.
In the second type of MOVX instruction, the Data Pointer generates a sixteen-bit address. P2
outputs the high-order eight address bits (the contents of DPH) while PO multiplexes the loworder eight bits (DPL) with data. The P2 Special Function Register retains its previous contents
while the P2 output buffers are emitting the contents of DPH. This form is faster and more efficient when accessing very large data arrays (up to 64K bytes), since no additional instructions
are needed to set up the output ports.
It is possible in some situation to mix the two MOVX types. A large RAM array with its high-order
address lines driven by P2 can be addressed via the Data Pointer, or with code to output highorder address bits to P2 followed by a MOVX instruction using RO or R1 .
An external 256 byte RAM using multiplexed address/data lines is connected to the 80C51
Port O. Port 3 provides control lines for the external RAM. Ports 0 and 2 are used for normal
I/O. Registers 0 and 1 contain 12H and 34H. Location 34H of the external RAM holds the value
56H. The instruction sequence
MOVX
MOVX
A,@R1
@RO,A
copies the value 56H into both the Accumulator and external RAM location 12H.
II
MOVXA,@Ri
Bytes:
Cycles:
Encoding:
Operation:
MOVX@Ri,A
Bytes:
Cycles:
Encoding:
Operation:
2
11 1 1 01 0
o1
il
o1
il
MOVX
(A)...-((Ri))
2
11 1 1 11 0
MOVX
((Ri))...-(A)
MOVX A, @ DPTR
Bytes:
Cycles:
2
Encoding:
1'1-1-1-0-1'0-0-0--'01
Operation:
MOVX
(A) ...- ((DPTR))
MOVX @ DPTR, A
Bytes:
Cycles:
Encoding:
Operation:
1
2
'11-1-1-1'1-0-0-0--'01
MOVX
(DPTR)...- (A)
MHSC51
NOP
Function :
Description:
Example :
No Operation
Execution continue at the following instruction. Other than the PC. no registers or flags are effected.
It is desired to produce a low-going output pulse on bit 7 of Port 2 lasting exactly 5 cycles. A
simple SETB/CLR sequence would generate a one-cycle pulse. so four additional cycles must
be inserted. This may be done (assuming no interrupts are enable) with the instruction sequence.
CLR
P2.7
NOP
NOP
NOP
NOP
SETP
P2.7
Bytes:
Cycles :
Encoding:
10000100001
Operation:
NOP
(PC) ~ (PC) + 1
MULAB
Function:
Description :
Example:
Multiply
MUL AB multiplies the unsigned eight-bit integers in the Accumulator and register B. The loworder byte of the sixteen-bit product is left in the Accumulator. and the high-order byte in B. If
the product is greater than 255 (OFFH) the overflow flag is set; otherwise it is cleared. The carry
flag is always cleared.
Originally the Accumulator holds the value 80 (SOH). Register B holds the value 160 (OAOH).
The instruction.
MULAB
will give the product 12.800 (3200H). so B is changed to 32H (0011001 OB) and the Accumulator
is cleared. The overflow flag is set. carry is cleared.
1
Bytes :
Cycles:
Encoding:
r-11-0-1-0"""1-0--0-'01
Operation:
MUL
4
(A)7 - 0 ~ (A) X (B)
(B)15 - 8
5-45
MHSC51
ORL
Function:
Description:
Example:
ORLA, Rn
Bytes:
Cycles:
Encoding:
Operation
ORL A, direct
Bytes:
Cycles:
Encoding:
Operation:
Logical-OR for byte variables
ORL performs the bitwise logical-OR operation between the indicated variables, storing the
results in the destination byte, No flags are affected.
The two operands allow six addressing mode combinaisons. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can be the Accumulator or immediate data.
Note :When this instruction is used to modify an output port, the value used as the original port
data will be read from the output data latch, not the input pins.
If the Accumulator holds OC3H (11000011 B) and RO holds 55H (01010101 B) then the instruction,
ORLA, RO
will leave the Accumulator holding the value OD7H (11010111 B).
When the destination is a directly addressed byte, the instruction can set combinations of bits
in any RAM location or hardware register. The pattern of bits to be set is determined by a mask
byte, which may be either a constant data value in the instruction or a variable computed in the
Accumulator at run-time. The instruction.,
ORL P1 , # 0011001 Ob
will set bits 5, 4, and 1 of output Port 1.
1
',0-1-0-0"'1-1-r-r---'r'
ORL
(A) f- (A) V (Rn)
2
1
',0-1-0-0"'1-0-1-0---'1,
direct address
ORL
(A) f- (A) V (direct)
ORLA,@Ri
Bytes:
Cycles:
Encoding :
10 1 0 01 0 1 1 i 1
Operation:
ORL
(A) f- (A) V ((Ri))
ORL A, # data
Bytes:
Cycles:
2
1
Encoding:
,--,
0 -1-0-0"1-0-0""01
Operation
ORL
(A) f- (A) V # data
ORL direct, A
Bytes:
Cycles:
Encoding:
Operation:
immediate data
2
1
'10-1-0-0"'1-0-0-1"""'01
ORL
(direct)
f-
direct address
(direct) V (A)
5-46
MHSC51
ORL direct, # data
Bytes:
3
Cycles:
2
Encoding:
'I
Operation :
0-1-0-0'T1-0-0-1-'11
ORL
(direct)
~
direct address
immediate data
(direct) V # data
ORL C,
Function:
Description :
Example:
Logical-OR for bit variable
Set the carry flag ifthe Boolean value is a logical 1 ; leave the carry in its current state otherwise.
A slash (U { U) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit it self is not affected.
No other flags are affected.
Set the carry flag if and only if P1.0
MOV
ORL
ORL
C, P1.0
C, ACC.?
C,/OV
= 1, ACC. ? = 1, or OV = 0 :
; LOAD CARRY WITH INPUT PIN P10
; OR CARRY WITH THE ACC. BIT?
; OR CARRY WITH THE INVERSE OF OV
ORLC, bit
Bytes:
2
Cycles :
2
Encoding:
Operation:
1 1 11 0 o 1 01
10
ORL
(C) ~ (C) V (bit)
bit address
ORL C, {bit
Bytes:
Cycles:
2
2
Encoding:
11 0 1 010 0 0 01
Operation:
ORL
(C) ~ (C) V (bit)
bit address
POP direct
Function :
Pop from stack.
Description :
The contents of internal RAM location addressed by the Stack Pointer is read, and the Stack
Pointer is decremented by one. The value read is then transferred to the directly addressed byte
indicated. No flags are affected.
Example:
The Stack Pointer originally contains the value 32H, and internal RAM locations 30H through
32H contain the values 20H, 23H, and 01 H, respectively. The instruction sequence,
POPDPH
POPDPL
will leave the Stack Pointer equal to the value 30H and the Data Pointer set to 0123H. At this
point the instruction,
POPSP
will leave the Stack Pointer setto 20H. Note that in this special case the Stack Pointer was decremented to 2FH before being loaded with the value popped (20H)
Bytes:
2
Cycles:
Encoding:
2
'"11-1-0-1"T"10-0-0---'01
Operation:
POP
(direct) ~ ((SP))
(SP) ~ (SP) - 1
direct address
5-47
MHSC51
PUSH direct
Function :
Description:
Example:
push onto stack.
The Stack Pointer is incremented by one. The contents fo the indicated variable is then copied
into the intemal RAM location addressed by the Stack Pointer. Otherwise no flags are affected.
On entering interrupt routine the Stack Pointer contains 09H. The Data Pointer holds the value
0123H. The instruction sequence,
PUSH DPL
PUSH DPH
will leave the Stack Pointer set to OSH and store 23H and 01 H in internal RAM location OAH
and OSH, respectively.
Bytes:
Cycles:
Encoding:
Operation:
2
2
r-11-1-0-0-'-1-0-0-0---'01
direct address
PUSH
(SP) ~ (SP) + 1
((SP)) ~ (direct)
RET
Function:
Description :
Example:
Return from subroutine
RET pops the high-and low-order bytes of the PC successively from the stack, decrementing
the Stack Pointer by two. Program execution continues at the resulting address, generally the
instruction immediately following en ACALL or LCALL. No flags are affected.
The Stack Pointer originally contains the value OSH. Internal RAM locations OAH and OSH contain the values 23H, and 01 H, respectively. The instruction,
RET
will leave the Stack Pointer equal to the value 09H. Program execution will continue at location
0123H.
Bytes:
Cycles:
Encoding:
Operation:
2
r-I
0-0-1-0-'-10 -0---'01
RT
(PC15 . 8) ~ ((SP))
(SP) ~.(SP) - 1
(PC7-0) ~ ((SP))
(SP) ~ (SP) - 1
RETI
Function:
Description :
Example:
Return from interrupt
RETI pops the high-and low-order bytes of the PC successively from the stack, and restores
the interrupt logic to accept additional interrupts at the same priority level as the one just
processed. The Stack Pointer is left decremented by two. No other registers are affected ;the
PSW is not automatically restored to its pre-interrupt status. Program execution continues at
the resulting address, which is generally the instruction immediately after the point at which the
interrupt request was detected. If a lower-or-same-Ievel interrupt had been pending when the
RETI instruction is executed, that one instruction will be executed before the pending interrupt
is processed.
The Stack Pointer originally contains the value OSH. An interrupt was detected during the instruction ending at location 0122H. Internal RAM locations OAH and OSH contain the values 23H
and 01 H, respectively. The instruction,
RETI
will leave the Stack Pointer equal to 09H and return program execution to location 0123H.
5-48
MHSC51
Bytes:
Cycles:
Encoding:
Operation :
2
r-\0-0-1-1--r\-0-0-1-'0\
RETI
(PC15 - 8) ~ ((SP))
(SP) ~ (SP) - 1
(PC? - 0) ~ ((SP))
(SP) ~ (SP) - 1
RL A
Function:
Description:
Example:
Rotate Accumulator Left
The eight bits in the Accumulator are rotated one bit to the left. Bit 7 rotated into the bit 0 position.
No flags are affected.
The Accumulator holds the value OC5H (11000101 B). The instruction,
RLA
leaves the Accumulator holding the value BBH (100001011 B) with the carry unaffected.
Bytes:
Cycles:
1
1
Encoding:
r-\0-0-1-0"""\0-0-1--'1\
Operation :
RL
(An + 1) ~ (An) n = 0 - 6
(AO) ~ (A7)
RLC A
Function:
Description :
Example:
Rotate Accumulator Left through the Carry flag
The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. Bit
7 moves into the carry flag; the original state of the carry flag moves into the bit 0 pOSition. No
other flags are affected.
The Accumulator holds the value OC5H (11000101 B), and the carry is zero. The instruction,
RCLA
leaves the Accumulator holding the value BBH (1000101 OB) with the carry set.
Bytes:
1
Cycles:
1
Encoding:
\0 0 1 110 0 1 1\
Operation:
RLC
(An + 1) ~ (An) n = 0 - 6
(AO) ~ (C)
(C) ~ (A7)
5-49
MHSC51
RR A
Function:
Description :
Example:
Rotate Accumulator Right
The eight bits in the Accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7
position. No flags are affected.
The Accumulator holds the value OC5H (11000101 B). The instruction,
RRA
leaves the Accumulator holding the value OE2H (1110001 OB) with the carry unaffected.
Bytes:
Cycles:
1
Encoding:
10 0 0 010 0
Operation:
RR
(An)
(A7)
ff-
11
(An + 1) n = 0 - 6
(AO)
RRCA
Function:
Description :
Example:
Rotate Accumulator Right through Carry flag
The eight bits in the Accumulator and the carry flag are together rotated one bit to the right. Bit
moves into the carry flag; the original value of the carry flag moves into the bit 7 position. No
other flags are affected.
o
The Accumulator holds the value OC5H (11000101 B), and the carry is zero. The instruction,
RRCA
leaves the Accumulator holding the value 62 (0110001 OB) with the carry set.
Bytes:
Cycles:
1
Encoding :
10 0 0 1 10 0 1 11
Operation:
RRC
(An) f- (An + 1 )n = 0 - 6
(A7) f- (C)
(C) f- (AO)
iii
5-50
MHSC51
SETS
Function:
Description :
Example:
SUBBA, Rn
Bytes :
Cycles :
Encoding:
II
Operation:
SUBB A, direct
Bytes :
Cycles:
Encoding:
Operation:
SUBBA,@Ri
Bytes:
Cycles :
Encoding:
Operation:
SUBB A, # data
Bytes :
Cycles:
Encoding:
Operation:
Subtract with borrow
SUBB subtracts the indicated variable and the carry flag together from the Accumulator, leaving
the result in the Accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit7,
and clears C otherwise. (If C was set before executing a SUBB instruction, this indicates that
a borrow was needed for the previous step in a multiple precision substraction so the carry is
subtracted from the Accumulator along with the source operand). AC is set if a borrow is needed
for bit 3, and cleared otherwise. OV is set if a borrow is needed into bit 6, but not into bit 7, or
into bit 7, but not bit 6.
When subtracting signed integers OV indicates a negative number produced when a negative
value is subtracted from a positive value, or a positive result when a positive number is subtracted from a negative number.
The source operand allows four addressing modes: register, direct, register-indirect, or immediate.
The Accumulator holds OC9H (11001001 B), register 2 holds 54H (01010100B), and the carry
flag is set. the instruction,
SUBBA, R2
will leave the value 74H (01110100B) in the accumulator, with the carry flag and AC cleared
but OV set.
Notice that OC9H minus 54H is 75H. The difference between this and the above result is due
to the carry (borrow) flag being set before the operation. If the state of the carry is not known
before starting a single or multiple-precision substraction, it should not be explicity cleared by
a CLRC instruction.
1
11 o 0 111 r r rl
SUBB
(A) ~ (A) - (C) - (Rn)
2
1
11
o0
11 0 1 0 11
direct address
SUBB
(A) ~ (A) - (C) - (direct)
1
11
o0
11 0 1 1 il
SUBB
(A) ~ (A) - (C) - (Ri)
2
1
11
o0
11 0
o 01
immediate data
SUBB
(A) ~ (A) - (C) - # data
5-52
MHSC51
SWAP A
Function:
Description :
Example:
Swap nibbles within the Accumulator
SWAP A interchanges the low-and high-order nibbles (four-bit fields) of the Accumulator (bits
3 - 0 and bits 7 - 4). The operation can also be thought of a four-bit rotate instruction. No flag
are affected.
The Accumulator holds the value OC5H (11000101 B). The instruction,
SWAP A
leave the Accumulator holding the value 5CH (010111 OOB).
Bytes:
1
Cycles:
1
Encoding:
11 1 0 010
Operation:
SWAP
0 01
(Aa . 0) ~ (A7 . 4)
XCH A,
Function:
Exchange Accumulator with byte variable
Description :
XCH loads the Accumulator with the contents of the indicated variable, at the same time writing
the original Accumulator contents to the indicated variable. The source/destination operand can
use register, direct, or register-indirect addressing.
Example:
RO contains the addres 20H. The Accumulator holds the value 3FH (00111111 B). Intemal RAM
location 20H holds the value 75H (01110101B). The instruction,
XCHA,@RO
will leave RAM location 20H holding the values 3FH (00111111 B) and 75H (01110101 B) in the
Accumulator.
XCHA, Rn
Bytes:
Cycles:
1
Encoding:
'11-1-0-o'I-1-r-r-'rl
Operation:
XCH
(A);:! (Rn)
XCH A, direct
Bytes:
Cycles:
2
1
Encoding:
1110010011
Operation:
XCH
(A) ;:! (direct)
direct address
XCHA,@Ri
Bytes:
Cycles:
1
1
Encoding:
1"-1-1-0-01"-0-1-1-'i1
Operation:
XCH
(A) ;:! ((Ri»
5-53
MHSC51
XCHD A, @ Ri
Function:
Description :
Example:
Exchange Digit
XCHD exchanges the low-order nibble of the Accumulator (bits 3 - 0), generally representing
a hexadecimal or BCD digit, with that of the internal RAM location indirectly addressed by the
specified register. The high-order nibbles (7 - 4) of each register are not affected. No flags are
affected.
RO contains the address 20H. The Accumulator holds the value 36H (0011011 OB). Internal RAM
location 20H holds the value 75H (01110101 B). The instruction,
XCHDA,@RO
will leave RAM location 20H holding the value 76H (0111011 OB) and 35H (00110101 B) in the
Accumulator.
Bytes:
1
Cycles:
Encoding:
1
Operation:
11 101101 1 il
XCHD
(A3· 0) ~ ((Ri3 . 0))
XRL ,
Function:
Description:
Logical Exclusive-OR for byte variable
XRL performs the bitwise logical Exclusive- OR operation between the indicated variables, storing the results in the destination. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can be the accumulator or immediate data.
(Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins).
Example:
If the Accumulator holds OC3H (11000011 B) and register 0 holds OAAH (1010101 OB) then the
instruction,
XRLA, RO
will leave the Accumulator holding the value 69H (01101001 B).
When the destination is a directly addressed byte, this instruction can complement combinations
of bits in any RAM location or hardware register. The pattern of bits to be complemented is then
determined by a mask byte, either a constant contained in the instruction or a variable computed
in the Accumulator at run-time. The instruction,
XRL P1, # 00110001 B
will complement bits 5, 4, and 0 of output Port 1 .
XRLA, Rn
Bytes:
Cycles:
Encoding:
Operation:
XRL A, direct
Bytes:
Cycles:
Encoding:
Operation:
~i
1
- '-11-r-r--'rl
0- 1- 1- 0
rI
XRL
(A) ~ (A) V (Rn)
2
1
'10-1-1-0'1-0-1-0-'11
direct address
XRL
(A) ~ (A) V (direct)
5-54
MHSC51
XRLA,@Ri
Bytes:
Cycles:
Encoding:
1 1 01 0 1 1 il
10
Operation:
XRL
(A) f- (A) 'r/ ((Ri))
XRL A, #data
Bytes:
Cycles:
2
Encoding:
1 1 01 0 1 0 01
10
Operation:
XRL
(A) f- (A) 'r/ # data
XRL direct, A
Bytes:
Cycles:
immediate data
2
Encoding:
1 1 010 0
10
Operation:
XRL
(direct)
f-
01
direct address
(direct) 'r/ (A)
XRL direct, # data
Bytes :
3
Cycles:
2
Encoding:
1 1 010 0 1 11
10
Operation:
XRL
(direct)
f-
direct address
(direct) '<:/ # data
5-55
immediate data
DATA SHEETS
~__________ i~1IIS
6-1
-------i."dl M4S
---Se-p-tem-b-er-1-g8-9
80C51/S0C31
DATA SHEET
CMOS SINGLE-CHIP
8 BIT MICROCONTROLLER
• 8OC51-CMOS
SINGLE-CHIP
MICROCONTROLLER with
factory maskprogrammable ROM.
• 8OC31-ROM LESS VERSION OF THE 8OC51
• 8OC51/C31
0 TO 12 MHz
8OC51/C31-1
0 TO 16 MHz
8OC51/C31 s
0 TO 20 MHz
• OTHER DEVICES WITH A SPECIFIC DATA
SHEET:
8OC51/C31-L : Vee = 2.7 VTO 6 V (OT06 MHz)
THE INTERNAL ROM CODE
8OC51F
CANNOT BE READ OR DUMPED
AFTER ACTIVATION OF A
SPECIAL PROTECTION
8OC51/C31s
OT020MHz
FEATURES
•
•
•
•
•
•
•
POWER CONTROL MODES
128x8 BIT RAM
32 PROGRAMMABLE I/O LINES
TWO 16-Em TIMER/COUNTERS
64 K PROGRAM MEMORY SPACE
FULLY STATIC DESIGN
HIGH PERFORMANCE SAJI VI CMOS PROCESS
•
•
•
•
•
BOOLEAN PROCESSOR
5 INTERRUPT SOURCES
PROGRAMMABLE SERIAL PORT
64 K DATA MEMORY SPACE
TEMPERATURE RANGE:
Commercial, Industrial, Automotive and Military
DESCRIPTION
,~--------------.-i-HH-l-l~
"""
......
D:
,
,,;
,
,,
:,,
,,,
":"
-.....
II
:'----L....
,,,
IS
!~,~-------
~l-.»-1Tl-l---------------------------i
,
,
::
,
,,1
,,,
'
MHS's 80C51 and 80C31 are high performance CMOS versions of the
8051/8031 NMOS single chip 8 bit ~C
and is manufactured using a selfaligned silicon gate CMOS process
(SAJIVI).
The fully static desing of the MHS
80C51/80C31 allows to reduce system
power consumption by bringing the
clock frequency down to any value,
even DC, without loss of data.
The 80C51 retains all the features of the
8051 : 4 K bytes of ROM; 128 bytes of
RAM ; 32 110 lines ; two 16 bit timers ;
a 5-source 2-level interrupt structure; a
full duplex serial port ; and on-chip oscillator and clock circuits.
In addition, the 80C51 has two
software-selectable modes of reduced
activity for further reduction in power
consumption. In the Idle Mode the CPU
is frozen while the RAM, the timers, the
serial port and the interrupt system continue to function. In the Power Down
Mode the RAM is saved and all other
functions are inoperative.
The 80C31 is identical to the 80C51 except that it has no on-chip ROM.
Figure 1 : Block Diagram.
MATRA MHS
8OC51J8OC31
Pl.0
Pl.l
P1.2
Pl.3
Pl.4
Pl.5
Pl.6
Pl.7
RST
P3.0IRXO
P3.11TXD
P3.2/iNi'O
P3.3/INTl
P3.41T0
P3.51T1
P3.61WR
P3.7/RD
XTAL2
XTAll
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
fi
~
~
OIL
vee
PO.O
PO.l
P02
PO.3
PO.4
PO.5
PO.a
PO.7
EA
ALE
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
INDEX
CORNER
.
-.:
ii:
"I
ii:
.,
ii:
[
q
1i
ii:
»i
i 2 2
:.:
:5: :4: :3: :2: ::1:: ...............
~:.a::a: :41::.to:
...............
.....
PI.5
PI.7
FO.8
RST
1'0.7
El
P30
8OC31180C61
NC
NC
P3.1
AU!
P32
PiIA
P3.3
P2.7
RIA
P2.8
PaS
.................................
:18: :19: :m: :21: :a: :a: :24: :a: :28: :u: :s:
..
S! f
i ~ I 1i r ~ r ~ i
PLCC
Pe4
Pes
Pa
Pws
Pw.
Pw7
RST
PJe
"-7
~
8OC31\8OC51
Nt
~
ALE
P:Ir
PD
P:M
PSEN
Pa7
Pa6
Pas
I;s
Flat Pack
Diagrams are for pin reference only. Package sizes are not to scale.
Figure 2 : Configurations.
PO.4
P05
PI.8
Pw.. Pw3 Pwa Pw. Pwo Nt Vee Pta PaJ Pte Pa
Nt
•..
.••..
P2.5
8OC5118OC31
IDLE AND POWER DOWN OPERATION
Figure 3 shows the internal Idle and Power Down clock
configuration. As illustrated, Power Down operation
stops the oscillator. Idle mode operation allows the interrupt, serial port, and timer blocks to continue to function while the clock to the CPU is gated off.
These special modes are activated by software via the
Special Function Registers, its hardware address is
87H. PCON is not bit addressable.
PeON: Power Control Register
(MSB)
I SMODI -
I -
I -
(LSB)
I GF1 I GFO I PO IIDL
I
Symbol Position Name and Function
SMOD
PCON.7 Double Baud rate bit. When set
to a 1, the baud rate is doubled
when the serial port is being
used in either modes 1, 2 or 3.
PCON.6 (Reserved)
PCON.S (Reserved)
PCON.4 (Reserved)
GF1
PCON.3 General-purpose flag bit.
GFO
PCON.2 General-purpose flag bit.
PCON.1 Power Down bit. Setting this bit
PO
activates power down operation.
IDL
PCON.O Idle mode bit. Setting this bit activates idle mode operation.
If 1's are written to PO and IDL at the same time. PO
takes precedence. The reset value of PCON is
(OXXXOOOO).
Figure 3 : Idle and Power Down Hardware.
MODE
PROGRAM MEMORY
ALE
PSEN
Idle
Idle
Power
Down
Power
Down
Internal
External
1
1
1
1
PORTO
Port Data
Floating
PORn
Port Data
Port Data
PORT2
Port Data
Address
PORT3
Port Data
Port Data
Internal
0
0
Port Data
Port Data
Port Data
Port Data
External
0
0
Floating
Port Data
Port Data
Port Data
Table 1 : Status of the external pins during Idle and Power Down modes.
IDLE MODE
The instruction that sets PCON.O is the last instruction
executed before the mode is activated. Once in the idle
mode the CPU status is preserved in its entirety: the
Stack Pointer, Program Counter, Program Status
Word, Accumulator, RAM, and all other registers maintain their data during Idle. Table 1 describes the status
of the external pins during Idle mode.
There are two ways to terminate the Idle mode. Activation of any enabled interrupt will cause PCON.O to be
cleared by hardware, terminating Idle mode. The interrupt is serviced, and following RETI, the next instruction
to be executed will be the one following the instruction
that wrote a 1 to PCON.O.
The flag bits GFO and GF1 may be used to determine
whether the interrupt was received during normal execution or during the Idle mode. For example, the instruction that writes to PCON.O can also set or clear one
or both flag bits. When Idle mode is terminated by an
enabled interrupt, the service routine can examine the
status of the flag bits.
The second way of terminating the Idle mode is with a
hardware reset. Since the oscillator is still running, the
hardware reset needs to be active for only 2 machine
cycles (24 oscillator periods) to complete the reset
operation.
POWER DOWN MODE
The instruction that sets PCON.1 is the last executed
priorto entering power down. Once is power down, the
oscillator is stopped. The contents of the onchip RAM
and the Special Function Register is saved during
power down mode. A hardware reset is the only way of
exiting the power down mode. The hardware reset initiate the Special Function Register (see Table 1).
In the Power Down mode, Vcc may be lowered to minimize circuit power consumption. Care must be taken
to ensure the voltage is not reduced until the power
-=
iih'i
8OC5118OC31
down mode is entered, and that the voltage is restored
before the hardware reset is applied which frees the oscillator. Reset should not be released until the oscillator
has restarted and stabilized.
Table 1 describes the status of the external pins while
in the power down mode. It should be noted that if the
power down mode is activated while in external program memory, the port data that is held in the Special
Function Register P2 is restored to Port 2. If the data is
a 1, the port pin is held high during the power down
mode by the strong pullup, T1, shown in Figure 4.
proximately 2 V, T3 turns off to save ICC current. Note,
when returning to a logical 1, T2 is the only internal pullup that is on. This will result in a slow rise time if the
user's circuit does not force the input line high.
80C31/80C51 PINS DESCRIPTION
Vss
Circuit ground potential
vee
Supply voltage during normal, Idle, and Power Down
operation.
STOP CLOCK MODE
Due to static desing, the MHS 80C31/C51 clock speed
can be reduced until 0 MHZ without any data loss in
memory or registers. This mode allows step by step
utilization, and permits to reduce system power consumption by bringing the clock frequency down to any
value. At 0 MHz, the power consumption is the same
as in the Power Down Mode.
Port 0
Port 0 is an 8-bit open drain bi-directional 1/0 port. Port
o pins that have1's written to them float, and in that
state can be used as high-impendance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and Data
Memory. In this application it uses strong internal pullups when emitting 1'So Port 0 also outputs the code
bytes during program verification in the 80C51. External
pullups are required during program verification. Port 0
can sink eight LS TIL inputs.
80C51 I/O PORTS
The 1/0 port drive of the 80C51 is similar to the 8051.
The 1/0 buffers for Ports 1, 2 and 3 are implemented as
shown in figure 4.
When the port latch contains a 0, all pFETS in figure 4
are off while the nFET is turned on. When the port latch
makes a 0-to-1 transition, the nFET turns off. The strong
pullup pFET, T1, turns on for two oscillator periods, pulling the output high very rapidly. As the output line is
drawn high, pFET T3 turns on through the inverter to
supply the IOH source current. This inverter and T3 form
a latch which holds the 1 and supported by T2.
When Port 2 is used as an address port, for access to
external program of data memory, any address bit that
contains a 1 will have his strong pullup turned on for the
entire duration of the external memory access.
When an 1/0 pin on Ports 1, 2, or 3 is used as an input,
the user should be aware that the external circuit must
sink current during the logical 1-10-0 transition. The
maximum sink current is specified as ITL under the D.C.
Specifications. When the input goes below ap-
Port 1
Port 1 is an 8-bit bi-directionall/O port with internal pullups. Port 1 pins that have 1's written to them are pulled
high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 1 pins that are externally
being pulled low will source current (ilL, on the data
sheet) because of the internal pullups.
Port 1 also receives the low-order address bytes during
program verification. In the 80C51 , Port 1 can
sink/source three LS TIL inputs. It can drive CMOS inputs without external pullups.
Port 2
Port 2 is an 8-bit bi-directionall/O port with internal pullups. Port 2 pins that have 1's written to them are pulled
high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 2 pins that are externally
being pulled low will source current (ilL, on the data
sheet) because of the internal pullups. Port 2 emits the
high-order address byte during fetches from external
Program Memory and during accesses to external Data
Memory that uses 16-bit addresses (MOVX @ DPTR).
In this application, it uses strong internal pullups when
emitting 1'So During accesses to external Data Memory
that uses 8-bit addresses (MOVX @ Ri), Port 2 emits
the contents of the P2 Special Function Register.
It also receives the high-order address bits and control
signals during program verification in the 80C51. Port 2
can sink/source three LS TIL inputs. It can drive CMOS
inputs without external pullups.
a
~C:>-~------~--~~
.....,.
Figure 4 : 1/0 Buffers in the 80C51 (Ports 1,2, 3).
6-6
80C51/8OC31
Port 3
only out of external Program Memory. EA must not be
floated.
Port 3 is an 8-bit bi-directionallJO port with internal pullups. Port 3 pins that have 1's written to them are pulled
high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 3 pins that are externally
being pulled low will source current (IlL, on the data
sheet) because of the pullups. It also serves the functions of various special features of the MHS-51 Family,
as listed below.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
XTAL1
Input to the inverting amplifier that forms the oscillator.
Receives the external oscillator signal when an external
oscillator is used.
XTAL2
Output of the inverting amplifier that forms the oscillator,
and input to the internal clock generator. This pin should
be floated when an external oscillator is used.
Alternate Function
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
lliTimer 1 external input)
WR (external Data Memory write strobe)
RD (external Data Memory read strobe)
OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output respectively, of an inverting amplifier which is configured for use
as an on-chip oscillator, as shown in figure 5. Either a
quartz crystal or ceramic resonator may be used. To
drive the device from an external clock source, XTAL 1
should be driven while XTAL2 is left unconnected as
shown in figure 6. There is no requirement on the duty
cycle of the external clock signal, since the input to the
internal clocking circuitry is through a divide-by-two flipflop, but minimum and maximum high and low times
specified on the Data Sheet must be observed.
Port 3 can sink/source three LS TTL inputs. It can drive
CMOS inputs without external pullups.
RST
A high level on this for two machine cycles while the oscillator is running resets the device. An internal pulldown resistor permits Power-On reset using only a
capacitor connected to Vce.
ALE
XTAL2:18
Address Latch Enable output for latching the low byte
of the address during accesses to external memory.
ALE is activated as though for this purpose at a constant
rate of 1/6 the oscillator frequency except during an external data memory access at which time one ALE
pulse is skipped. ALE can sink/source 8 LS TTL inputs.
It can drive CMOS inputs without an external pullup.
XTALl:19
t----------iws: 20
PSEN
Figure 5: Crystal Oscillator.
Program Store Enable output is the read strobe to external Program Memory. PSEN is activated twice each
machine cycle during fetches from external Program
Memory. (However, when executing out of external
Program Memory, two activations of PSEN are skipped
during each access to external Data Memory). PSEN
is not activated during fetches from internal Program
Memory. PSEN can sink/source 8 LS TTL inputs. It can
drive CMOS inputs without an external pullup.
EXTERNAL
~------------;
SIGNAL
EA
When EA is held high, the CPU executes out of internal
Program Memory (unless the Program Counter exceeds OFFFH). When EA is held low, the CPU executes
Figure 6 : External Drive Configuration.
6-7
8OC51J8OC31
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias:
C = Commerical... ................................ O'C to 70'C
I = Industrial.................................... - 40'C to 85'C
Storage Temperature..................... - 65'C to + 150'C
Voltage on Vee to Vss........................ - 0.5 V to + 7 V
Voltage on Any Pin to Vss ........ - 0.5 V to Vee + 0.5 V
Power Dissipation .............................................. 1 W"
• NOTICE:
Stresses at or above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability .
• , This value is based on the maximum allowable die tempera·
ture and the thermal resistance of the package.
DC CHARACTERISTICS
TA =-40'C to 85'C; VCC = 5 V±20%; VSS = 0 V; F = 0 to 12 MHz
TA =-40'Cto 85'C; VCC = 5 V± 10%; VSS = 0 V; F = Oto 16 MHz
SYMBOL
PARAMETER
VIL
Input Low Voltage
VIH
VIH1
VOL
VOL1
VOH
VOH1
Input High Voltage
(Except XTAL and RST)
Input High Voltage
(RST and XTAL1)
Output Low Voltage (Ports1, 2, 3)
MIN
MAX
-0.5
0.2VCC
-0.1
0.2 VCC VCC + 0.5
+ 0.9
0.7VCC VCC +0.5
Output High Voltage
(Port 0, ALE, PSEN)
Logical 0 Input Current Ports 1, 2, 3
III
Input Leakage Current (Port 0, EA)
Logical 1 to 0 Transition Current
(Ports 1, 2, 3)
ITL
IPD
RRST
CIO
ICC
RST Pulldown Resistor
V
10L = 1.6 rnA (note3)
V
V
10L = 3.2 rnA (note 3)
0.9VCC
V
10H = -10
0.75 VCC
V
10H =-251JA
2.4
V
10H =-60 IJA
VCC = 5 V± 10 %
V
10H =-80
V
V
10H = - 300
0.9 VCC
0.75 VCC
50
IJA
IJA
IJA
800 IJA
IJA
10H = VCC = 5 V± 10 %
Vin = 0.45 V
-650
IJA
IJA
0.45 < Vin < VCC
Vin = 2.0 V
50
IJA
VCC = 2.0 V to 6 V
(note 2)
150
10
kn
pF
tc = 1 MHz, TA = 25°C
20
rnA
rnA
(notes 1, 2)
C I-50
I 1-60
± 10
Power Supply Current
(Power Down Mode)
Capacitance of I/O Buffer
Power supply current
Active mode 12 MHz
Idle mode 12 MHz
V
0.45
2.4
ilL
TEST CONDITIONS
0.45
Output Low Voltage Port 0, ALE, PSEN
Output High Voltage Ports 1, 2, 3
UNIT
V
5
Note 1 : ICC max is given by :
Active Mode: ICC MAX = 1.47 x FREQ + 2.35
Idle Mode: ICCMAX = 0.33 x FREQ + 1.05
where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mA. See Figure 1.
See figures 1 through 5for ICC test conditions.
8OC5118OC31
30
/
25
20
«E
/
15
-
/
( .)
~
10
5
0
/
v
~V
ACTIVE
MODE
/
Figure 2 : ICC Test Condition, Idle Mode. All other
pins are disconnected.
-
~
~
MAX
MAX
IDLE
MODE
4 MHz 8 MHz 12 MHz 16 MHz 20 MHz
FIEORlCIM..1
Figure 3: ICC Test Condition, Active Mode. All other
pins are disconnected.
Figure 1 : ICC vs. Frequency. Valid only within
frequency specifications of the device
under test.
Figure 4 : Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH = TCHCL = S ns.
Note 2 : ICC is measured with all output pins disconnected ; XTAL 1 driven with TCLCH, TCHCL = Sns,
VIL = VSS + .S V, VIH = VCC - .SV ; XTAL2 N.C ; EA
= RST = Port 0 = VCC .ICC would be slightly higher if
a crystal oscillator used. Idle ICC is measured with all
output pins disconnected; XTAL 1 driven with TCLCH =
TCHCL = Sns, VIL = VSS + .SV,
VIH = VCC - .SV ; XTAL2 N.C ; Port 0 = VCC ; EA =
RST=VSS.
Power Down ICC is measured with all output pins disconnected; EA = PORTO = VCC ; XTAL2 N.C. ; RST =
VSS.
Note 3 : Capacitance loading on Ports 0 and 2 may
cause spurious noise pulses to be superimposed on the
VOLS of ALE and Ports 1 and 3. The noise is due to
external bus capacitance discharging into the Port 0
and Port 2 pins when these pins make 1 to 0 transitions
during bus operations. In the worst case (capacitive
loading 100 pF), the noise pulse on the ALE line may
exceed O.4S V with maxi VOL peak 0.6 V. A Schmitt
Trigger use is not necessary.
X1l\L2
Xll\I.1
\ISS
Figure 5: ICC Test Condition, Power Down Mode.
All other pins are disconnected.
6-9
8OC51/8OC31
EXTERNAL CLOCK DRIVE CHARACTERISTICS (XT AL 1)
SYMBOL
1ITCLCL
VARIABLE CLOCK
FREQ = 0 to 16 MHz
MIN
MAX
PARAMETER
Oscillator Frequency
UNIT
62.5
ns
TCHCX
High Time
20
ns
TCLCX
Low Time
20
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
ns
A.C. PARAMETERS:
40°C + 85°C; VSS = 0 V ; VCC = 5 V ± 20 % ; F = 0 to 12 MHz
40°C + 85°C; VSS = 0 V; VCC = 5 V ± 10 % ; F = 0 to 16 MHz
(Load Capacitance for Port 0, ALE, and PSEN = 100 pf ; Load Capacitance for All Other Outputs
TA
TA
==-
= 80 pf).
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
SYMBOL
PARAMETER
MIN
MAX
UNIT
TLHLL
ALE Pulse Width
2TCLCL-40
ns
TAVLL
Address Valid to ALE
TCLCL-55
ns
TLLAX
Address Hold After ALE
TCLCL-35
TLLlV
ALE to Valid Instr in
TLLPL
ALE to PSEN
TCLCL-40
TPLPH
PSEN Pulse Width
3TCLCL-45
TPLIV
PSEN to Valid Instr in
TPXIX
Input Instr Hold After PSEN
TPXIZ
Input Instr Float After PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid Instr in
TPLAZ
PSEN Low to Address Float
ns
4TCLCL-100
ns
ns
ns
3TCLCL-105
ns
ns
0
TCLCL-25
TCLCL-8
ns
ns
5TCLCL-10S
ns
10
ns
MAX
UNIT
EXTERNAL DATA MEMORY CHARACTERISTICS
SYMBOL
PARAMETER
MIN
TRLRH
RD Pulse Width
6TCLCL-100
TWLWH
WR Pulse Width
6TCLCL-100
ns
TCLCL-SO
ns
TLLAX
Data Address Hold After ALE
ns
TRLDV
RD to Valid Data in
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
2TCLCL-70
ns
TLLDV
ALE to Valid Data in
8TCLCL-1S0
ns
TAVDV
Address to Valid Data in
9TCLCL-165
ns
TLLWL
ALE to WR or RD
3TCLCL+SO
ns
TAVWL
Address to WR or RD
TQVWX
Data Valid to WR Transition
TQVWH
Data Setup to WR High
TWHQX
Data Hold After WR
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
i'111111S
STCLCL-16S
0
3TCLCL-SO
ns
4TCLCL-130
ns
TCLCL-60
ns
7TCLCL-150
ns
TCLCL-50
TCLCL-40
6-10
ns
ns
0
ns
TCLCL+40
ns
80C51/8OC31
ABSOLUTE MAXIMUM RATINGS'
• NOTICE:
Ambiant Temperature Under Bias:
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at these orany other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
M = Military ............................... - 55'C to + 125'C
A = Automotive ......................... - 40·C to + 125'C
Storage Temperature .................... - 65'C to + 150'C
Voltage on Any Pin to Vss ........ - 0.5 V to Vee + 0.5 V
Voltage on Vee to Vss ....................... -- 0.5 V to 6.5 V
Power Dissipation .......................................... 200 mW
DC CHARACTERISTICS
TA = - 55'C to + 125'C ; VSS = 0 V; VCC = 5 V ± 10 %
SYMBOL
PARAMETER
VIL
Input Low Voltage
VIH
MIN
MAX
UNIT
-0.5
0.2 VCC
-0.1
V
Input High Voltage (Except XTAL1, RST) 0.2 vcc VCC + 0.5
+ 0.9
V
0.7 vcc VCC + 0.5
V
TEST CONDITIONS
VIH1
Input High Voltage (XTAL 1, RST)
VOL
Output Low Voltage (Ports 1, 2, 3)
0.45
V
IOL = 1.6 mA (note 3)
VOL1
Output Low Voltage (Port 0, ALE, PSEN)
0.45
V
IOL = 3.2 mA (note 3)
VOH
Output High Voltage (Ports 1, 2, 3)
2.4
V
IOH = - 60!1A
VCC = 5 V ± 10 %
0.75 VCC
V
IOH = - 25!1A
0.9 VCC
V
IOH = -10!1A
2.4
V
IOH = - 800 !1A
VCC = 5 V ± 10 %
0.75 VCC
V
IOH = - 300 !1A
0.9 VCC
V
IOH = 80!1A
-75
!1A
Vin = 0.45 V
-750
!1A
Vin = 2 V
± 10
k.Q
VOH1
Output High Voltage
(Port 0 in External Bus Mode, ALE, PEN)
ilL
Logical 0 Input Current Ports 1, 2, 3
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2, 3)
III
Input Leakage Current (Port 0, EA)
0.45 < Vin < VCC
Reset Pulldown Resistor
50
!1A
150
CIO
Pin Capacitance
10
pF
Test Freq = 1 MHz,
TA=25°e
IPD
Power Down Current
75
!1A
vec = 2 V to 5.5 V
ICC
Power supply current
Active mode 12 MHz
Idle mode 12 MHz
21
7
mA
mA
vce = 5.5 V
VCC = 5.5 V
RRST
6-11
8OC5118OC31
AC PARAMETERS:
TA=-55"C + 125"C; VSS = 0 V; VCC = 5 V± 10 %
(Load Capacitance for Port 0, ALE, and PSEN = 100 pf ; Load Capacitance for All Other Outputs = 80 pf).
FREQ = 12 MHz (MAX)
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
SYMBOL
TLHLL
TAVLL
TLLAX
TLLlV
TLLPL
TPLPH
TPLIV
TPXIX
TPXIZ
TPXAV
TAVIV
TPLAZ
PARAMETER
MIN
ALE Pulse Width
MAX
2TCLCL-55
Address Valid to ALE
TCLCL-70
Address Hold After ALE
TCLCL-50
4TCLCL-115
ALE to Valid Instr in
ALE to PSEN
TCLCL-55
PSEN Pulse Width
3TCLCL-60
PSEN to Valid Instr in
3TCLCL-120
Input Instr Hold After PSEN
0
TCLCL-40
Input Instr Float After PSEN
PSEN to Address Valid
TCLCL-8
5TCLCL-120
Address to Valid Instr in
25
PSEN Low to Address Float
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
EXTERNAL DATA MEMORY CHARACTERISTICS
SYMBOL
TRLRH
TWLWH
TLLAX
TRLDV
TRHDX
TRHDZ
TLLDV
TAVDV
TLLWL
TAVWL
TQVWX
TQVWH
TWHQX
TRLAZ
TWHLH
PARAMETER
MIN
RD Pulse Width
6TCLCL-100
WR Pulse Width
6TCLCL-100
MAX
TCLCL-50
Data Address Hold After ALE
5TCLCL-185
RD to Valid Data in
Data Hold After RD
0
2TCLCL-85
Data Float After RD
8TCLCL-170
ALE to Valid in
9TCLCL-185
Address to Valid Data in
ALE to WR or RD
3TCLCL-65
Address to WR or RD
3TCLCL+65
4TCLCL-145
TCLCL-75
Data Valid to WR Transition
Data Setup to WR High
7TCLCL-150
Data Hold After WR
TCLCL-65
RD Low to Address Float
0
RD or WR High to ALE High
TCLCL-65
6-12
TCLCL+65
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8OC5118OC31
AC TIMING DIAGRAMS
EXTERNAL PROGRAM MEMORY READ CYCLE
~---------------------~nu1----------------------~
ALE
INSTRIN
ADDREIIS
ADDREIIS A8-A15
PORr2 OR SFR-P2
EXTERNAL DATA MEMORY READ CYCLE
PIER
lID
PCRI'O
PCRI'2
AIlOI&S A8-A15 OR SFR-P2
EXTERNAL DATA MEMORY WRITE CYCLE
1WHLH
PIER
WI!
---------------+--------~~-------~--------~~----
PCRI'O _ _ _ _ _ _
PCRI'2
~
Dlill\0Uf
AIlOI&S
ORSFR-P2
AIlOI&S A8-A15 OR SFR-P2
AC TESTING INPUT/OUTPUT, FLOAT WAVEFORMS
AC inputs during testing are driven at Vcc - 0.5 for a Icgic "1" and 0.45 V for a logic "0". Timing measurements are
made at VIH min for a logic "1" and VIL max for a logic "0". For timing purposes a port pin is no longer floating when
a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOHNOL
level occurs. 101l10H <': ± 20 mAo
6-13
8OC51/BOC31
SERIAL PORT TIMING· SHIFT REGISTER MODE
MIN
PARAMETER
SYMBOL
MAX
UNIT
12TCLCL
f.lS
Output Data Setup to Clock Rising
Edge
1OTCLCL -133
ns
TXHQX
Output Data Hold after Clock Rising
Edge
2TCLCL-117
ns
TXHDX
Input Data Hold after Clock Rising
Edge
0
ns
TXHDV
Clock Rising Edge to Input Data
Valid
TXLXL
Serial Port Clock Time
TQVXH
ns
1OTCLCL -133
SHIFT REGISTER TIMING WAVEFORMS
INSIRUCI10N
I
a.oac:
OUTPUTDAlII
,
L...-.-...J
WM'£lOSIIJF
I\
10m<
-t ITXHOX
0
X
X
8
6
3
0
X
3
X
X
X •
~~j~~
X
,I
SET1I
,
IFUT~
SET"
EXPLANATION OF THE AC SYMBOL
Example:
Each timing symbol has 5 characters. The first character is always a "T" (stands for time). The other characters, depending on their positions, stand for the name
of a signal or the logical status of that signal. The following is a list of all the characters and what they stand
for.
TAVLL = Time for Address Valid to ALE low.
TLLPL = Time for ALE low to PSEN low.
A: Address.
C: Clock
D : Input data.
H : Logic level HIGH.
I : Instruction (program memory contents).
L : Logic level LOW, or ALE.
P: PSEN.
Q : Output data.
R : READ signal.
T:Time
V: Valid.
W : WRITE signal.
X : No longer a valid logic level.
Z: Float.
6-14
80C51/8OC31
CLOCK WAVEFORMS
STAJE6
STAlE 4
PlIP'l
PlIP'l
I
S'DI.lE5
I
PlIP'l
XTAL2
~
I
ALE
EXTERNAL PROGRAM MEMORY FEJQ!
I
L.---..;.._ _
I
THESE SIGNALS HE NOT
ACIlIIIQ"EI) DlRNG THE
EXEa./11ON OF A MO\IX INSTRUCIlON
I
t
I
L
PO
P'l (EX11
REAPC'fClE
m
----------------------,
PO
NlICAlES IlPH OR P'l SFR 10 POITRANSIllONS
P'l
W!!!TE CYa.E
WR
~
__________________
~I
~arr(~F~
-
• MEMORVIS INIERNALI
I•
PO PINS SAMPLm
PO
P'l
PORfOPE!!1illON
OlD f:lAm NEW f:lAm
IKNPORt SAC
IKN~PO _ _ _ _ _ _~~~~~~----------------------~
A
MOV oesr PORT (PI. P2- 1'3)
(1Na.UOESINTo.INTUo.TI)
___
~W:m9ffl
'T'
PO PINS SAMPlED
.
Cl.OCK
_______-.:.l;i_Pt-l
......P2.P3P1NSSAMPlED
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependant on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (TA = 25°C fully loaded) RD
and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are
incorporated in the AC specifications.
6·15
80C5118OC31
ARITHMETIC OPERATIONS
MNEMONIC
ADD
A,Rn
ADD
A,direct
ADD
A,@Ri
ADD
A,#data
AD DC
A,Rn
AD DC
A,direct
AD DC
A,@Ri
AD DC
A,#data
SUBB
A,Rn
SUBB
A,direct
SUBB
A,@Ri
SUBB
A,#data
INC
A
INC
Rn
INC
direct
@Ri
INC
INC
DPTR
DEC
A
DEC
Rn
DEC
direct
DEC
@Ri
MUL
AB
DIV
AB
DA
A
LOGICAL OPERATIONS
MNEMONIC
ANL
A,Rn
ANL
A,direct
ANL
A,@Ri
ANL
A,#data
ANL
direct,A
ANL
direct,#data
ORL
A,Rn
ORL
A,direct
A,@Ri
ORL
ORL
A,#data
ORL
direct,A
ORL
direct,#data
XRL
A,Rn
XRL
A,direct
A,@Ri
XRL
XRL
A,#data
XRL
direct,A
XRL
direct,#data
CLR
A
CPL
A
RL
A
RLC
A
RR
A
RRC
A
SWAP
A
DESCRIPTION
Add register to Accumulator
Add direct byte to Accumulator
Add indirect RAM to Accumulator
Add immediate data to Accumulator
Add register to Accumulator with Carry
Add direct byte to A with Carry flag
Add indirect RAM to A with Carry flag
Add immediate data to A with Carry flag
Subtract register from A with Borrow
Subtract direct byte from A with Borrow
Subtract indirect RAM from A with Borrow
Subtract immed. data from A with Borrow
Increment Accumulator
Increment register
Increment direct byte
Incriment indirect RAM
Incriment Data Pointer
Decrement Accumulator
Decrement register
Decrement direct byte
Decrement indirect RAM
Multiply A & B
Divide A by B
Decimal Adjust Accumulator
DESTINATION
AND register to Accumulator
AND direct byte to Accumulator
AND indirect RAM to Accumulator
AND immediate data to Accumulator
AND Accumulator to direct byte
AND immediate data to direct byte
OR register to Accumulator
OR direct byte to Accumulator
OR indirect RAM to Accumulator
OR immediate data to Accumulator
OR Accumulator to direct byte
OR immediate data to direct byte
Exclusive-OR register to Accumulator
Exclusive-OR direct byte to Accumulator
Exclusive-OR indirect RAM to A
Exclusive-OR immediate data to A
Exclusive-OR Accumulator to direct byte
Exclusive-OR immediate data to direct
Clear Accumulator
Complement Accumulator
Rotate Accumulator Left
Rotate A Left through the Carry flag
Rotate Accumulator Right
Rotate A Right through Carry flag
Swap nibbles within the Accumulator
Table 1 : MHS C51 Instruction Set Description.
6-16
BYTE
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
1
2
1
1
1
1
CYC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
BYTE
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
CYC
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
4
4
1
8OC51/8OC31
DATA TRANSFER
MNEMONIC
DESCRIPTION
MOV
A,Rn
Move register to Accumulator
MOV
A,direct
Move direct byte to Accumulator
MOV
A,@Ri
Move indirect RAM to Accumulator
MOV
A,#data
Move immediate data to Accumulator
MOV
Rn,A
Move Accumulator to register
MOV
Rn,direct
Move direct byte to register
MOV
Rn,#data
Move immediate data to register
MOV
direct,A
Move Accumulator to direct byte
MOV
direct,Rn
Move register to direct byte
MOV
direct,direct
Move direct byte to direct byte
MOV
direct,@Ri
Move indirect RAM to direct byte
MOV
direct,#data
Move immediate data to direct byte
MOV
@Ri,A
Move Accumulator to indirect RAM
MOV
@Ri,direct
Move direct byte to indirect RAM
MOV
@Ri,#data
Move immediate data to indirect RAM
MOV
DPTR,#data 16
Load Data Pointer with a 16-bit constant
MOVC
A,@A+DPTR
Move Code byte relative to DPTR to A
MOVC
A,@A+PC
Move Code byte relative to PC to A
A,@Ri
MOVX
Move External RAM (8-bit addr) to A
A,@DPTR
MOVX
Move External RAM (16-bit addr) to A
@Ri,A
MOVX
Move A to External RAM (8-bit addr)
MOVX
@DPTR,A
Move A to External RAM (16-bit addr)
PUSH
direct
Push direct byte onto stack
POP
direct
Pop direct byte from stack
Exchange register with Accumulator
XCH
A,Rn
XCH
A,direct
Exchange direct byte with Accumulator
XCH
A,@Ri
Exchange indirect RAM with A
A,@Ri
XCHD
Exchange low-order nibble ind RAM with A
BOOLEAN VARIABLE MANIPULATION
MNEMONIC
DESCRIPTION
Clear Carry flag
CLR
C
CLR
bit
Clear direct bit
SETB
C
Set Carry flag
SETB
bit
Set direct Bit
CPL
Complement Carry flag
C
CPL
Complement direct bit
bit
ANL
C,bit
AND direct bit to Carry flag
ANL
C, fbit
AND complement of direct bit to Carry
ORL
C, bit
OR direct bit to Carry flag
ORL
C, fbit
OR complement of direct bit to Carry
Move direct bit to Carry flag
MOV
C, bit
Move Carry flag to direct bit
MOV
bit,C
PROGRAM AND MACHINE CONTROL
MNEMONIC
DESCRIPTION
ACALL
addr 11
Absolute Subroutine Call
LCALL
addr 16
Long Subroutine Call
Return from subroutine
RET
RETI
Return from interrupt
Absolute Jump
addr 11
AJMP
Long Jump
addr 16
LJMP
rei
Short Jump (relative addr)
SJMP
@A+DPTR
Jump indirect relative to the DPTR
JMP
rei
Jump if Accumulator is Zero
JZ
rei
Jump if Accumulator is Not Zero
JNZ
rei
Jump if Carry flag is set
JC
rei
Jump if No Carry flag
JNC
Table 1. (Cont.)
6-17
BYTE
1
2
1
2
1
2
2
2
2
3
2
3
CYC
1
1
1
1
1
2
1
1
2
2
2
2
1
1
2
2
3
2
1
1
1
1
1
1
2
2
1
2
1
1
BYTE
1
2
1
2
1
2
2
2
2
2
2
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
CYC
1
1
1
1
1
1
2
2
2
2
1
2
BYTE
CYC
2
3
2
2
2
2
2
2
2
2
2
2
2
2
1
1
2
3
2
1
2
2
2
2
8OC51!80C31
PROGRAM AND MACHINE CONTROL (cont.)
MNEMONIC
DESCRIPTION
JB
bit, rei
Jump if direct Bit set
Jump if direct Bit Not set
JNB
bit, rei
JBC
bit, rei
Jump if direct Bit is set & Clear bit
CJNE
A,direct,rel
Compare direct to A & Jump if Not Equal
CJNE
A,#data,rel
Compo immed. to A & Jump if Not Equal
CJNE
Rn,#data,rel
Compo immed. to reg & Jump if Not Equal
CJNE
@Ri,#data.rel
Compo immed. to indo & Jump if Not Equal
DJNZ
Rn,rel
Decrement register & Jump if Not Zero
Decrement direct & Jump if Not Zero
DJNZ
direct. rei
NOP
No operation
BYTE
CYC
3
3
3
3
3
3
3
2
3
2
2
2
2
2
2
2
2
2
1
1
Table 1. (Cont.)
Notes on data addressing modes:
Rn
- Working register RO-R7
direct
- 128 internal RAM locations, any 110 port, control or status register
@Ri
-Indirect internal RAM location addressed by register RO or R1
- 8-bit constant included in instruction
#data
- 16-bit constant included as bytes 2 & 3 of instruction
#data 16
- 128 software flags, any I/O pin, control or status bit
bit
Notes on program addressing modes:
- Destination address for LCALL & LJMP may be anywhere within the 64-k program memory
address space
- Destination address for ACALL & AJMP will be within the same 2-k page of program
Addr 11
memory as the first byte of the following instruction
rei
- SJMP and all conditional jumps include an 8-bit offset byte. Range is + 127 - 128 bytes
relative to the first byte of the following instruction.
All mnemonics copyrighted© Intel Corporation 1979
addr 16
6-18
8OC51/8OC31
HEX NUMB.
CODE OF
MNEM.
BYTES
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
18
1C
10
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
1
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
1
1
2
2
1
1
1
1
1
1
1
1
1
1
3
2
1
NOP
AJMP
LJMP
RR
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
JBC
ACALL
LCALL
RRC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
JB
AJMP
RET
RL
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
JNB
ACALL
RETI
HEX NUMB.
CODE OF
MNEM.
BYTES
OPERANDS
33
34
code addr
code addr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr,code addr
code addr
code addr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr,code addr
code addr
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
A
A,data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
bit addr,code addr
code addr
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
1
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
RLC
AD DC
ADDC
AD DC
ADDC
ADDC
AD DC
AD DC
ADDC
ADDC
ADDC
AD DC
AD DC
JC
AJMP
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
JNC
ACALL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
JZ
AJMP
XRL
XRL
XRL
XRL
Table 2: Instruction Opcodes in Hexadecimal Order.
6-19
OPERANDS
A
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
data addr,A
data addr,#data
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
data addr,A
data addr,#data
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
data addr A
data addr,#data
A,#data
A,data addr
8OC51/8OC31
HEX NUMB.
CODE OF
MNEM.
BYTES
66
67
68
69
6A
6B
6C
60
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
70
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
1
1
1
1
1
1
1
1
1
1
2
2
2
1
2
3
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
3
2
2
2
2
2
2
2
2
2
2
3
2
2
1
2
2
1
1
1
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
JNZ
ACALL
ORL
JMP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
SJMP
AJMP
ANL
MOVC
OIV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ACALL
MOV
MOVC
SUBB
SUBB
SUBB
SUBB
SUBB
HEX NUMB.
CODE OF
MNEM.
BYTES
OPERANDS
99
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
C,bit addr
@A+OPTR
A,#data
data addr,#data
@RO,#data
@R1,#data
RO,#data
R1,#data
R2,#data
R3,#data
R4,#data
R5,#data
R6,#data
R7,#data
code addr
code addr
C,bit addr
A,@A+PC
AB
data addr,data addr
data addr,@RO
data addr,@R1
data addr,RO
data addr,R1
data addr,R2
data addr,R3
data addr,R4
data addr,R5
data addr,R6
data addr,R7
OPTR,#data
code addr
bit addr,C
A,@A+OPTR
A,#data
A,data addr
A,@RO
A,@R1
A,RO
9A
9B
9C
90
9E
9F
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BO
BE
BF
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
Table 2. (Cont.)
6-20
1
1
1
1
1
1
1
2
2
2
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
1
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
1
1
2
1
1
1
1
1
1
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
ORL
AJMP
MOV
INC
MUL
reserved
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ANL
ACALL
CPL
CPL
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
PUSH
AJMP
CLR
CLR
SWAP
XCH
XCH
XCH
XCH
XCH
XCH
XCH
OPERANDS
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
C,bi! addr
code addr
C,bit addr
OPTR
AB
@RO,data addr
@R1 ,data addr
RO,data addr
R1,data addr
R2,data addr
R3,data addr
R4,data addr
R5,data addr
R6,data addr
R7,data addr
C,bit addr
code addr
Bit addr
C
A,#data,code addr
A,data addr,code addr
@RO,#data,code addr
@R1 ,#data,code addr
RO,#data,code addr
R1,#da!a,code addr
R2,#data,code addr
R3,#data,code addr
R4,#data,code addr
R5,#data,code addr
R6,#data,code addr
R7,#data,code addr
data addr
code addr
bit addr
C
A
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
8OC51/8OC31
HEX NUMB.
CODE OF
MNEM.
BYTES
1
1
1
1
2
2
2
1
1
3
1
1
2
2
2
2
2
2
2
2
1
2
1
1
1
2
CC
CO
CE
CF
DO
01
02
03
04
05
06
O?
08
09
OA
DB
DC
DO
DE
OF
EO
E1
E2
E3
E4
E5
XCH
XCH
XCH
XCH
POP
ACALL
SETB
SETB
OA
OJNZ
XCHO
XCHO
OJNZ
OJNZ
OJNZ
OJNZ
OJNZ
OJNZ
OJNZ
OJNZ
MOVX
AJMP
MOVX
MOVX
CLR
MOV
HEX NUMB.
CODE OF
MNEM.
BYTES
OPERANDS
A,R4
A,RS
A,R6
A,R?
data addr
code addr
bit addr
C
A
data addr,code addr
A,@RO
A,@R1
RO,code addr
R1,code addr
R2,code addr
R3,code addr
R4,code addr
R5,code addr
R6,code addr
R?,code addr
A,@OPTR
code addr
A,@RO
A,@R1
A
A,data addr
E6
E?
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FO
FE
FF
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVX
ACALL
MOVX
MOVX
CPL
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
OPERANDS
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,RS
A,R6
A,R?
@OPTR,A
code addr
@RO,A
@R1,A
A
data addr,A
@RO,A
@R1,A
RO,A
R1,A
R2,A
R3,A
R4,A
R5,A
R6,A
R?,A
Table 2. (Cont.)
F
A
R
Q
P
S
L
I
M
D
T
T
J
80C31
80C51
T
xxx
T
-1
IB
T
:R
T
-1 : 16 MHz Version
Temperature Range
Package Type
Part Number
IB : Miliary Program
blank: Commercial
P: Plastic
80C51 Rom 4 K x 8
I : Industrial
S: PLCC
80C31 External Rom
M: Military
0: Cerdip
Customer Rom Code
Tape and Reel
L: Ind + BI*
R :LCC
(80C51 only)
Q: Com + BI*
J : J leaded LCC
A : Automotive
F : Quad Flat Pack
(only commercial)
* BI : Burn-In
6-21
------- ~)1rn IItS
---Se-pt-em-b-er-1-g8-9
SOC51 S/SOC31 S
DATA SHEET
CMOS SINGLE-CHIP
8 BIT MICROCONTROLLER
• 80C31S-ROM LESS VERSION OF THE 80C51
• 80C51S/80C31S : 0 To 20 MHz
• 80C51S-CMOS SINGLE-CHIP 8 BIT MICROCONTROLLER with factory mask-programmabie ROM
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
POWER CONTROL MODES
128 X 8 BIT RAM
32 PROGRAMMABLE 1/0 LINES
TWO 16-BIT TIMERICOUNTERS
64 K PROGRAM MEMORY SPACE
FULLY STATIC DESIGN
HIGH PERFORMANCE SAJI VI CMOS PROCESS
BOOLEAN PROCESSOR
5 INTERRUPT SOURCES
PROGRAMMABLE SERIAL PORT
64 K DATA MEMORY SPACE
TEMPERATURE RANGE: Commercial
DESCRIPTION
P20-P27
~~ tf~--------------------------:
,,
,,
MHS's 80C51S and 80C31S are high
performance CMOS versions of the
8051/8031 NMOS single chip 8 bit IlC
and is manufactured using a selfaligned silicon gate CMOS process
(SAJIVI).
The fully static design of the MHS
80C51 S/80C31 S allows to reduce system power consumption by bringing the
clock frequency down to any value,
even DC, without loss of data.
The 80C51S retains all the features of
the 8051 : 4 K bytes of ROM; 128 bytes
of RAM; 32 1/0 lines; two 16 bit timers;
a 5-source, 2-level interrupt structure; a
full duplex serial port; and on-chip oscillator and clock circuits.
.......
In addition, the 80C51S has two
software-selectable modes of reduced
activity for further reduction in power
consumption. In the Idle Mode the CPU
is frozen while the RAM, the timers, the
serial port, and the interrupt system
continue to function. In the Power Down
Mode the RAM is saved and all other
functions are inoperative.
rA
lIlT,
,'---'--'
,
,,,
l~
t~r----
The 80C31 S is identical to the 80C51 S
except that it has no on-chip ROM.
Figure 1 : Block Diagram.
6·23
MATRA MHS
___________________________ 80C51SmoC31S ___________________________
vee
Pl.0
Pl.l
P1.2
Pl.3
Pl.4
Pl.5
Pl.6
Pl.7
:6: :5: :.: :3: :2:
&.. 1:•
PO.O
PO.l
PO.2
PO.3
PO.4
PO.5
PO.6
PO.7
EA
ALE
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.l
P2.0
RST
P3.0/RXD
P3.lffXO
P3.2I1NTO
P3.3I1NTl
P3.4ffO
P3.5ff1
P3.61WR
P3.7/RD
XTAL2
XTALl
VSS
....
••• &• • • • • • • •
P1.5
~:a: :u: :41::.
•.•
&• • • • • • • • • • •
P1.6
P1.7
RST
P30
8OC51S/8OC31S
NC
P3.l
P3.2
P33
P3.4
P3.6
.- •••••••• -.
:18: :19: :m: :21:
I ~
OIL
i
p ••• - •• - ••••• - ••••
:~
:23:
~ I
~:
:m: :as: :2P.
~ ~ ~
i ~ ~
PLCC
PJ,
PI.
PJ7
RST
4
Pa
5
NC
6
~
7
Pa
8
Po4
Pa
P-.
3
P07
£i'
NC
ALE
PSEN
P,7
8OC51S/80C31S
9
P,.
24
23
10
P:.. P,~ ~
Vss NC PIG Pz. PH Pn P,.
~~
Flat Pack
Diagrams are for reference only. Package sizes are not to scale.
Figure 2 : Configurations.
6-24
Pz6
Pas
p ••
:~
____________________________
8OC51S~OC31S
____________________________
PCON : Power Control Register
(MSB)
IDLE AND POWER DOWN OPERATION
Figure 3 shows the internal Idle and Power Down clock
configuration. As illustrated, Power Down operation
stops the oscillator. Idle mode operation allows the interrupt, serial port, and timer blocks to continue to function while the clock to the CPU is gated off.
These special modes are activated by software via the
Special Function Register, PCON. Its hardware address is 87 H. PCON is not bit addressable.
I SMODI
-
I -
I -
(LSB)
I GF1 I GFO I PD IIDL
I
Symbol Position Name and Function
SMOD
PCON.7 Double Baud rate bit. When set
to a 1, the baud rate is doubled
when the serial port is being
used in either modes 1, 2 or 3.
PCON.6 (Reserved)
PCON.5 (Reserved)
PCON.4 (Reserved)
GF1
PCON.3 General-purpose flag bit.
GFO
PCON.2 General-purpose flag bit.
PD
PCON.1 Power Down bit. Setting this bit
activates power down operation.
IDL
PCON.O Idle mode bit. Setting this bit activates idle mode operation.
If 1's are written to PO and IDL at the same time. PD
takes precedence. The reset value of PCON is
(OXXXOOOO).
Figure 3 : Idle and Power Down Hardware.
1
PORTO
Port Data
Floating
PORT1
Port Data
Port Data
PORT2
Port Data
Address
PORT3
Port Data
Port Data
0
0
Port Data
Port Data
Port Data
Port Data
0
0
Floating
Port Data
Port Data
Port Data
MODE
Idle
PROGRAM MEMORY
Internal
ALE
1
PSEN
1
Idle
Power
Down
Power
Down
External
1
Internal
External
Table 1 : Status of the external pins during Idle and Power Down modes.
IDLE MODE
The instruction that sets PCON.O is the last instruction
executed before the Idle mode is activated. Once in the
Idle mode the CPU status is preserved in its entirety:
the Stock Pointer, Program Counter, Program Status
Word, Accumulator, RAM, and all other registers maintain their data during Idle. Table 1 describes the status
of the external pins during Idle mode.
There are two ways to terminate the Idle mode. Activation of any enabled interrupt will cause PCON.O to be
cleared by hardware, terminating Idle mode. The interrupt is serviced, and following RETI, the next instruction
to be executed will be the one following the instruction
that wrote a 1 to PCON.O.
The flag bits GFO and GF1 may be used to determine
whether the interrupt was received during normal execution or during the Idle mode. For example, the instruction that writes to PCON.O can also set or clear one
or both flag bits. When Idle mode is terminated by an
enabled interrupt, the service routine can examine the
status of the flag bits.
The second way of terminating the Idle mode is with a
hardware reset. Since the oscillator is still running, the
hardware reset needs to be active for only 2 machine
cycles (24 oscillator periods) to complete the reset
operation.
POWER DOWN MODE
The instruction that sets PCON.1 is the last executed
prior to entering power down. Once in power down, the
oscillator is stopped. The contents of the onchip RAM
and the Special Function Register is saved during
power down mode. A hardware reset is the only way of
exiting the power down mode. The hardware reset initiate the Special Function Register (see Table 1).
In the Power Down mode, Vce may be lowered to minimize circuit power consumption. Care must be taken
to ensure the voltage is not reduced until the power
down mode is entered, and that the voltage is restored
before the hardware reset is applied which frees the oscillator. Reset should not be released until the oscillator
has restarted and stabilized.
6-25
____________________________
80C51S~C31S
80C31S/80C51S PIN DESCRIPTIONS
Table 1 describes the status of the external pins while
in the power down mode. It should be noted that if the
power down mode is activated while in external program memory, the port data that is held in the Special
Function Register P2 is restored to Port 2. If the data is
a 1, the port pin is held high during the power down
mode by the strong pullup, T1, shown in Figure 4.
Vss
Circuit ground potential
Vee
Supply voltage during normal, Idle, and Power Down
operation.
Due to static design, the MHS 80C31S/C51S clock
speed can be reduced until 0 MHz without any data loss
in memory or registers. This mode allows step by step
utilization, and permits to reduce system power consumption by bringing the clock frequency down to any
value. At 0 MHz, the power consumption is the same
as in the Power Down Mode.
Port 0
Port 0 is an 8-bit open drain bi-directionall/O port. Port 0
pins that have 1's written to them float, and in that state
can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and Data
Memory. In this application it uses strong internal pullups when emitting 1'so Port 0 also outputs the code
bytes during program verification in the 80C51 S. External pullups are required during program verification.
Port 0 can sink eight LS TTL inputs.
BOC51 1/0 PORTS
The 1/0 port drive of the 80C51 S is similar to 8051. The
1/0 buffers for Ports 1, 2, and 3 are implemented as
shown in figure 4.
When the port latch contains a 0, all pFETS in figure 4
are off while the nFET is turned on. When the port latch
makes a 0-to-1 transition, the nFETturns off. The strong
pullup pFET, T1, turns on for two oscillator periods, pulling the output high very rapidly. As the output line is
drawn high, pFET T3 turns on through the inverter to
supply the IOH source current. This inverter and T3 form
a latch which holds the 1 and is supported by T2.
Port 1
Port 1 is an 8-bit bi-directional 1/0 port with internal pullups. Port 1 pins that have 1's written to them are pulled
high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 1 pins that are externally
being pulled low will source current (IlL, on the data
sheet) because of the internal pullups.
When Port 2 is used as an address port, for access to
external program of data memory, any address bit that
contains a 1 will have his strong pullup turned on for the
entire duration of the external memory access.
Port 1 also receives the low-order address bytes during
program verification. In the 80C51S, Port 1 can
sink/source three LS TTL inputs. It can drive CMOS inputs without external pullups.
When an 1/0 pin on Ports 1, 2, or 3 is used as an input,
the user should be aware that the external circuit must
sink current during the logical Ho-O transition. The
maximum sink current is specified as ITL under the D.C.
Specifications. When the input goes below approximately 2 V, T3 turns off to save IC current. Note,
when returning to a logical 1, T2 is the only internal pullup that is on. This will result in a slow rise time if the
user's circuit does not force the input line high.
Port 2
Port 2 is an 8-bit bi-directionall/O port with internal pullups. Port 2 pins that have 1's written to them are pulled
high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 2 pins that are externally
being pulled low will source current (ilL, on the data
sheet) because of the internal pullups. Port 2 emits the
high order address byte during fetches from external
Program Memory and during accesses to external Data
Memory that use 16-bit addresses (MOVX@DPTR). In
this application, it uses strong internal pullups when
emitting 1'so During accesses to external Data Memory
that use 8-bit addresses (MOVX@Ri), Port 2 emits the
contents of the P2 Special Function Register.
It also receives the high-order address bits and control
signals during program verification in the 80C51 S.
Port 2 can sink/source three LS TTL inputs. It can drive
CMOS inputs without external pullups.
=
II
IRCH
____________________________
c>-........----'----ft::-'
Port 3
Port 3 is an 8-bit bi-directionall/O port with internal pullups. Port 3 pins that have 1's written to them are pulled
high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 3 pins that are externally
being pulled low will source current (ilL, on the data
sheet) because of the pullups. It also serves the func-
Figure 4 : 1/0 Buffers in the 80C51 S (Ports 1,2, 3).
6-26
----------_________________
8OC51S~31S
XTAL2
Output of the inverting amplifier that forms the oscillator,
and input to the internal clock generator. This pin should
be floated when an external oscillator is used.
tions of various special features of the MHS-51 Family,
as listed below.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
___________________________
Alternate Function
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 Timer 1 external input)
WR (external Data Memory write strobe)
RD (external Data Memory read strobe)
OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output respectively, of an inverting amplifier which is configured for use
as an on-chip oscillator, as shown in figure 5. Either a
quartz crystal or ceramic resonator may be used.
To drive the device from an external clock source,
XTAL 1 should be driven while XTAL2 is left unconnected as shown in figure 6. There are no requirements
on the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a divideby-two flip-flop, but minimum and maximum high and
low times specified on the Data Sheet must be observed.
Port 3 can sink/source three LS TTL inputs. It can drive
CMOS inputs without extemal pullups.
RST
A high level on this for two machine cycles while the oscillator is running resets the device. An internal
pulldown resistor permits Power-On reset using only a
capacitor connected to VCC.
ALE
Address Latch Enable output for latching the low byte
of the address during accesses to external memory.
ALE is activated as though forthis purpose at a constant
rate of 1/6 the oscillator frequency except during an external data memory access at which time one ALE
pulse is skipped. ALE can sink/source 8 LS TTL inputs.
It can drive CMOS inputs without an external pullup.
PSEN
Program Store Enable output is the read strobe to external Program Memory. PSEN is activated twice each
machine cycle during fetches from extemal Program
Memory (However, when execution out of external Program Memory, two activations of PSEN are skipped
during each access to external Data Memory). PSEN
is not activated during fetches from internal Program
Memory. PSEN can sink/source 8 LS TTL inputs. It can
drive CMOS inputs without an external pullup.
+---------------~~:m
Figure 5 : Crystal Oscillator.
EA
When EA is held high, the CPU executes out of internal
Program Memory (unless the Program Counter exceeds OFFFH). When EA is held low, the CPU executes only out of external Program Memory. EA must
not be floated.
NC
EX11BW...
0SCII..LA10R--------IXl1.l..1 : '19
SIGNAL
VSS:20
XTAL1
Input to the inverting amplifier that forms the oscillator.
Receives the external oscillator signal when an external
oscillator is used.
Figure 6 : External Drive Configuration.
6-27
--------------------_______ 8OC51Smoc31S ___________________________
ABSOLUTE MAXIMUM RATINGS*
* NOTICE:
Ambient Temperature Under Bias:
- commercial ............................................ O·C to 70·C
Stresses at or above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.
Storage Temperature ..................... - 65·C to + 150·C
Voltage on Vcc to Vss ........................ - 0,5 V to + 7 V
Voltage on Any Pin to Vss ........ - 0.5 V to Vcc + 0.5 V
Power Dissipation .............................................. 1 W"
•• This value is based on the maximum allwable die temperature
and the thermal resistance of the package.
DC CHARACTERISTICS (see Note 2)
TA = O°C to 70·C ; VCC = 5 V ± 10 % ; VSS = 0 V; F = 0 to 20 MHz
SYMBOL
PARAMETER
MIN
MAX
UNIT
-0.5
0.2 VCC
-0.1
V
VCC + 0.5
V
0.7 VCC VCC + 0.5
V
VIL
Input Low Voltage
VIH
Input High Voltage
(Except XTAL and RST)
0.2
Input High Voltage
(RST and XTAL 1)
VIH1
vcc
TEST CONDITIONS
+ 0.9
VOL
Output Low Voltage (Ports 1, 2, 3)
0.45
V
10L = 1.6 rnA (note3)
VOL1
Output Low Voltage Port 0, ALE, PSEN
0.45
V
10L = 3.2 mA (note 3)
VOH
Output High Voltage Ports 1, 2, 3
0.9 VCC
V
10H = -10 !1A
0.75 VCC
V
10H =-25!1A
2.4
V
10H = -60!1A
VCC = 5 V± 10 %
0.9 VCC
V
10H = -80!1A
0.75 VCC
V
10H = - 350 !1A
2.4
V
10H = - 800 !1A
VCC = 5 V± 10 %
VOH1
Output High Voltage
(Port 0, ALE, PSEN)
ilL
Logical 0 Input Current Ports 1, 2, 3
-50
!1A
Yin = 0.45 V
III
Logical Leakage Current (Port 0, EA)
±10
!1A
0.45 < Yin < VCC
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2, 3)
-650
!1A
Yin = 2.0 V
IPD
Power Supply Current
(Power Down Mode)
50
!1A
VCC = 2.0 Vto 5.5 V
(note 2)
RRST
RST Pulldown Resistor
150
k.Q
10
pF
CIO
Capacitance of 110 Buffer
ICC
Power supply current
Active mode 20 MHz
Idle mode 20 MHz
50
32
8
rnA
fc = 1 MHz, TA = 25°C
(notes 1, 2)
mA
Note1: ICC max is given by :
Active Mode: ICCMAX = 1.47 x FREQ + 2.35
Idle Mode: ICCMAX = 0.33 x FREQ + 1.05
where FREQ is the extemal oscillator frequency in MHz. ICCMAX is given in mA. See Figure 1.
See figure 1 through 5 for ICC test conditions.
6-28
8OC51S~OC31S
____________________________
MAX
ACTIVE
MODE
:;(
E
Figure 2: ICC Test Condition, Idle Mode. All other
pins are disconnected.
-
MAX
IDLE
MODE
RSr
o~--~--~--~--~--~
41Rt: 8MHz 121Rt: 18 MHz 201Rt:
FREQRX1M.1
)CW.2
XlM.1
\ISS
Figure 1 : ICC vs. Frequency. Valid only within
frequency specifications of the device
under test.
Figure 3: ICC Test Condition, Active Mode. All other
pins are disconnected.
Figure 4: Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.
Note 2 : ICC is measured with all output pins disconnected ; XTAL1 driven with TCLCH, TCHCL = 5 ns,
VIL = VSS +.5 V, VIH = VCC-.5 V; XTAL2 N.C. ; EA =
RST = Port 0 = VCC ICC would be slightly higher if a
crystal oscillator used. Idle ICC is measured with all output pins disconnected; XTAL 1 driven with TCLCH,
TCHCL = 5 ns, VIL = VSS + .5 V, VIH = VCC -.5 V ;
XTAL2 N.C. ; Port 0= vec ; EA = RST = VSS.
Power Down ICC is measured with all output pins disconnected; EA= PORTO = VCC ;XTAL2 N.C.; RST =
VSS.
Note 3 : Capacitance loading on Ports 0 and 2 may
cause spurious noise pulses to be superimposed on the
VOLS of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and
Port 2 pins when these pins make 1 to 0 transitions
during bus operations. In the worst cases (capacitive
loading 100 pF), the noise pulse on the ALE line may
exceed 0,45 V with maxi VOL peak 0.6 V. A Schmitt
Trigger use is not necessary.
Figure 5: ICC Test Condition, Power Down Mode.
All other pins are disconnected.
6-29
----________________________ 80C51S/SOC31S ____________________________
EXTERNAL CLOCK DRIVE CHARACTERISTICS (XTAL 1)
SYMBOL
VARIABLE CLOCK
FREQ = 0 to 20 MHz
MIN
MAX
50
20
PARAMETER
UNIT
1/TCLCL
Oscillator Frequency
TCHCX
High Time
TCLCX
Low Time
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
20
ns
ns
ns
A.C. PARAMETERS:
TA = O·C + 70·C ; VSS = 0 V; VCC = 5 V ± 10 % (commercial)
(Load Capacitance for Port 0, ALE, and PSEN = 100 pf ; Load Capacitance for All Other Outputs = 80 pf).
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
SYMBOL
II
PARAMETER
MIN
MAX
UNIT
TLHLL
ALE Pulse Width
2TCLCL-40
TAVLL
Address Valid to ALE
TCLCL-35
ns
TLLAX
Address Hold After ALE
TCLCL-30
ns
TLLlV
ALE to Valid Instr in
TLLPL
ALE to PSEN
TCLCL-40
TPLPH
PSEN Pulse Width
3TCLCL-45
TPLIV
PSEN to Valid Instr in
TPXIX
Input Instr Hold After PSEN
TPXIZ
Input Instr Float After PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid Instr in
TPLAZ
PSEN Low to Address Float
ns
4TCLCL-100
ns
ns
ns
3TCLCL-50
0
ns
ns
TCLCL-20
TCLCL-8
ns
ns
5TCLCL-105
ns
10
ns
MAX
UNIT
EXTERAL DATA MEMORY CHARACTERISTICS
SYMBOL
TRLRH
RD Pulse Width
6TCLCL-100
ns
TWLWH
WR Pulse Width
6TCLCL-100
ns
PARAMETER
MIN
TLLAX
Data Address Hold After ALE
TRLDV
RD to Valid Data in
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
2TCLCL-50
ns
TLLDV
ALE to Valid Data in
8TCLCL-150
ns
TAVDV
Address to Valid Data in
9TCLCL-100
ns
TLLWL
ALE to WR or RD
3TCLCL+50
ns
TAVWL
Address to WR or RD
TQVWX
Data Valid to WR Transition
TQVWH
Data Setup to WR High
TWHQX
Data Hold After WR
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
i1I~MIS
TCLCL-30
ns
5TCLCL-100
0
3TCLCL-50
ns
4TCLCL-130
ns
TCLCL-60
ns
7TCLCL-150
ns
TCLCL-20
TCLCL-40
6-30
ns
ns
0
ns
TCLCL+40
ns
___________________________ 8OC51SmOC31S ---------------------------
AC TIMING DIAGRAMS
EXTERNAL PROGRAM MEMORY CYCLE
~--------------------~~--------------------~
IISTRIN
ADDfESS AB-A16
EXTERNAL DATA MEMORY READ CYCLE
1WHLH
------------~--------~~-------+~I--------~~----
PClRI'2
EXTERNAL DATA MEMORY WRITE CYCLE
1WHLH_+---.....,..
PClRI"O _ _ _ _
PClRI"2
~
ADDIIBS
OR8FR-P2
ADDIIEISS _111 OR 8FR-P2
AC TESTING INPUT/OUTPUT, FLOAT WAVEFORMS
N'UTlOU1PUT
~-------RQq'--------~
IICH-O,1V
__
.Ir
\ICL+O,1V
AC inputs during testing are driven at Vee - 0.5 for a logic "1" and 0.45 V for a logic "0". Timing measurements are
made at VIH min for a logic "1" and VIL max for a logic "0". For timing purposes a port pin is no longer floating when
a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOHNOL
level occurs. IOUIOH ~ ± 20 mAo
6-31
_ _ _ _ _ _ _ _ _ _ _ _ _ 80C51S/8OC31S _ _ _ _ _ _ _ _ _ _ _ __
SERIAL PORT TIMING - SHIFT REGISTER MODE
SYMBOL
MIN
PARAMETER
UNIT
MAX
TXLXL
Serial Port Clock Cycle Time
12TCLCL
TQVXH
Output Data Setup to Clock Rising Edge
1OTCLCL -133
liS
ns
TXHQX
Output Data Hold After Clock Rising Edge
2TCLCL-117
ns
TXHDX
Input Data Hold After Clock Rising Edge
TXHDV
Clock Rising Edge to Input Data Valid
ns
0
10TLCL-133
ns
SHIFT REGISTER TIMING WAVEFORMS
INSTRUCIICN
I
0
3
5
8
•
,
SETII
EXPLANATION OF THE AC SYMBOLS
Example:
Each timing symbol has 5 characters. The first character is always a "T" (stands for time). The other characters, depending on their positions, stand for the name
of a signal or the logical status of that signal. The following is a list of all the characters and what they stand
for.
TAVLL = Time for Address Valid to ALE low.
TLLPL = Time for ALE low to PSEN low.
A: Address.
C: Clock.
D : Input data.
H : Logic level HIGH.
I : Instruction (program memory contents).
L : Logic level LOW, or ALE.
P: PSEN.
Q : Output data.
R : READ signal.
T:Time.
V: Valid.
W : WRITE signal.
X : No longer a valid logic level.
Z : Float.
6-32
------------------------____ 8OC515/8OC315 ____________________________
CLOCK WAVEFORMS
~
I ~I~ I ~I~ I ~I~ I ~I~ I ~I~ I ~I~ I ~I~ I ~I~ I
S1l\TE4
S1l\TE 5
S1l\TE 6
S1l\TE 1
STATE 3
SWE 2
STATE 4
STATE 5
lCW.2
'
~
........--.;._....11
THESE SIGNALS N£ NOT
I
DUlING THE
EXECUIlON a: A MCNX INSl1IJCJION
ACrNI\1B)
Pa..out
I
~
t
__
I
L
~.
I~(EXT)
READ C't!l.E
lID
-----------,
~
WAlEcyg.E
WR
I Pa.. out (EVEN
F PROGRAM
IS IN1B'IIAIJ
•
MOVPORI'SAC
MOV~N
OlD DATA
INEW DATA
~
MBMJII'(
PO PINS SMIPlED
~
MOV~PORI'~(~~~~-~~-~ ,p~O~~~~~~~----------------------------~
(1NCUJIlESINfo.lNft.To.T1)
~---
JTI---------------------------------!~
I.
Pt.P2.P3~SAMP\.B)
•
~
~q __----------~
SEBALPORISIflrux:K
~PlNS1.P!-!.~~
,
RXD SAMPLED
r-.
RXD SAMP\.B)
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (TA = 25"C fully loaded) RD
and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are
incorparated in the AC specifications.
6-33
HillS
--__________________________ 80C515/80C315 --------------------________
ARITHMETIC OPERATIONS
MNEMONIC
DESCRIPTION
ADD
ADD
ADD
ADD
ADDC
AD DC
AD DC
ADDC
SUBB
SUBB
SUBB
SUBB
INC
INC
INC
INC
INC
DEC
DEC
DEC
DEC
MUL
DIV
DA
Add register to Accumulator
Add direct byte to Accumulator
Add indirect RAM to Accumulator
Add immediate data to Accumulator
Add register to Accumulator with Carry
Add direct byte to A with Carry flag
Add indirect RAM to A with Carry flag
Add immediate data to A with Carry flag
Subtract register from A with Borrow
Subtract direct byte from A with Borrow
Subtract indirect RAM from A with Borrow
Subtract immed. data from A with Borrow
Increment Accumulator
Increment register
Increment direct byte
Increment indirect RAM
Increment Data Pointer
Decrement Accumulator
Decrement register
Decrement direct byte
Decrement indirect RAM
Multiply A & B
Divide A by B
Decimal Adjust Accumulator
A,Rn
A,direct
A,@Ri
A,#data
A,Rn
A,direct
A,@Ri
A,#data
A,Rn
A,direct
A,@Ri
A,#data
A
Rn
direct
@Ri
DPTR
A
Rn
direct
@Ri
AB
AB
A
LOGICAL OPERATIONS
MNEMONIC
DESTINATION
ANL
ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
CLR
CPL
RL
RLC
RR
RRC
SWAP
AND register to Accumulator
AND direct byte to Accumulator
AND indirect RAM to Accumulator
AND immediate data to Accumulator
AND Accumulator to direct byte
AND immediate data to direct byte
OR register to Accumulator
OR direct byte to Accumulator
OR indirect RAM to Accumulator
OR immediate data to Accumulator
OR Accumulator to direct byte
OR immediate data to direct byte
Exclusive-OR register to Accumulator
Exclusive-OR direct byte to Accumulator
Exclusive-OR indirect RAM to A
Exclusive-OR immediate data to A
Exclusive-OR Accumulator to direct byte
Exclusive-OR immediate data to direct
Clear Accumulator
Complement Accumulator
Rotate Accumulator Left
Rotate A Left through the Carry flag
Rotate Accumulator Right
Rotate A Right through Carry flag
Swap nibbles within the Accumulator
A,Rn
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A,Rn
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A,Rn
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A
A
A
A
A
A
A
Table 1 : MHS - 51 Instruction Set Description.
i"l11f1111S
6-34
BYTE
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
1
2
1
1
1
1
CYC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
4
4
1
BYTE
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
CYC
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
- -__________________________
8OC51S~31S
____________________________
DATA TRANSFER
MNEMONIC
DESCRIPTION
MOV
A,Rn
Move register to Accumulator
MOV
A,direct
Move direct byte to Accumulator
MOV
A,@Ri
Move indirect RAM to Accumulator
MOV
A,#data
Move immediate data to Accumulator
MOV
Rn,A
Move Accumulator to register
MOV
Rn,direct
Move direct byte to register
MOV
Rn,#data
Move immediate data to register
MOV
direct,A
Move Accumulator to direct byte
MOV
direct,Rn
Move register to direct byte
MOV
direct,direct
Move direct byte to direct
MOV
direct,@Ri
Move indirect RAM to direct byte
MOV
direct,#data
Move immediate data to direct byte
MOV
@Ri,A
Move Accumulator to indirect RAM
MOV
@Ri,direct
Move direct byte to indirect RAM
MOV
@Ri,#data
Move immediate data to indirect RAM
MOV
DPTR,#data 16
Load Data Pointer with a 16-bit constant
MOVC
A,@A+DPTR
Move Code byte relative to DPTR to A
MOVC
A,@A+PC
Move Code byte relative to PC to A
A,@Ri
Move External RAM (a-bit addr) to A
MOVX
A,@DPTR
Move External RAM (16-bit addr) to A
MOVX
@Ri,A
MOVX
Move A to External RAM (a-bit addr)
@DPTR,A
Move A to External RAM (16-bit addr)
MOVX
PUSH
direct
Push direct byte onto stack
direct
Pop direct byte from stack
POP
XCH
A,Rn
Exchange register with Accumulator
XCH
A,direct
Exchange direct byte with Accumulator
XCH
A,@Ri
Exchange indirect RAM with A
A,@Ri
XCHD
Exchange low-order nibble ind RAM with A
BOOLEAN VARIABLE MANIPULATION
MNEMONIC
DESCRIPTION
Clear Carry flag
CLR
C
Clear direct bit
bit
CLR
SETB
C
Set Carry flag
SETB
bit
Set direct Bit
CPL
Complement Carry flag
C
Complement direct bit
CPL
bit
ANL
C,bit
AND direct bit to Carry flag
C,/bit
ANL
AND complement of direct bit to Carry
C, bit
ORL
OR direct bit to Carry flag
ORL
C, /bit
OR complement of direct bit to Carry
C, bit
Move direct bit to Carry flag
MOV
bit,C
Move Carry flag to direct bit
MOV
PROGRAM AND MACHINE CONTROL
DESCRIPTION
MNEMONIC
addr11
ACALL
Absolute Subroutine Call
addr16
Long Subroutine Call
LCALL
Return from subroutine
RET
RETI
Return from interrupt
addr11
AJMP
Absolute Jump
addr16
Long Jump
LJMP
rei
Short Jump (relative addr)
SJMP
@A+DPTR
Jump indirect relative to the DPTR
JMP
rei
Jump if Accumulator is Zero
JZ
rei
Jump if Accumulator is Not Zero
JNZ
rei
Jump if Carry flag is set
JC
Jump if No Carry flag
rei
JNC
Table 1. (Cont.)
6-35
BYTE
1
2
1
2
1
2
2
2
2
3
2
3
CYC
1
1
1
1
1
2
1
1
2
2
2
2
1
1
2
2
3
2
1
1
1
1
1
1
2
2
1
2
1
1
BYTE
1
2
1
2
1
2
2
2
2
2
2
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
CYC
1
1
1
1
1
1
2
2
2
2
1
2
BYTE
CYC
2
3
2
2
1
1
2
3
2
1
2
2
2
2
2
2
2
2
2
2
2
2
2
____________________________
80C51S~31S
____________________________
PROGRAM AND MACHINE CONTROL (cont.)
MNEMONIC
DESCRIPTION
JB
bit, rei
Jump if direct Bit set
Jump if direct Bit Not set
JNB
bit, rei
JBC
bit, rei
Jump if direct Bit is set & Clear bit
CJNE
A,direct, rei
Compare direct to A & Jump if Not Equal
CJNE
A,#data, rei
Compo immed. to A & Jump if Not Equal
CJNE
Rn,#data, rei
Compo immed. to reg & Jump if Not Equal
Compo immed. to indo & Jump if Not Equal
CJNE
@Ri,#data. rei
DJNZ
Rn,rel
Decrement register & Jump if Not Zero
DJNZ
direct. rei
Decrement direct & Jump if Not Zero
NOP
No operation
BYTE
3
3
3
3
3
3
3
2
3
1
CYC
2
2
2
2
2
2
2
2
2
1
Table 1. (Cont.)
Notes on data addressing modes:
Rn
- Working register RO-R7
direct
-128 internal RAM locations, any 110 port, control or status register
@Ri
-Indirect internal RAM location addressed by register RO or R1
#data
- 8-bit constant included in instruction
-16-bit constant included as bytes 2 & 3 of instruction
#data 16
bit
- 128 software flags, any 110 pin, control or status bit
Notes on program addressing modes:
addr 16
- Destination address for LCALL & LJMP may be anywhere within the 64-k program memory
address space
Addr 11
- Destination address for ACALL & AJMP will be within the same 2-k page of program
memory as the first byte of the fol/owing instruction
rei
- SJMP and aI/ conditional jumps include an 8-bit offset byte. Range is + 127 -128 bytes
relative to the first byte of the fol/owing instruction.
AI/ mnemonics copyrighted© Intel Corporation 1979
6-36
----------------------_____
HEX NUMB.
MNEM.
CODE OF
BYTES
1
NOP
00
01
AJMP
2
WMP
02
3
1
RR
03
1
INC
04
INC
05
2
1
06
INC
1
07
INC
1
INC
08
1
INC
09
1
INC
OA
1
INC
OB
1
INC
OC
OD
1
INC
1
INC
OE
1
INC
OF
10
3
J8C
11
2
ACALL
12
LCALL
3
13
1
RRC
14
1
DEC
15
2
DEC
16
1
DEC
1
17
DEC
1
18
DEC
19
1
DEC
1A
1
DEC
18
1
DEC
1
1C
DEC
1
10
DEC
1
1E
DEC
1F
1
DEC
JB
20
3
21
2
AJMP
RET
1
22
1
RL
23
2
24
ADD
2
ADD
25
1
ADD
26
27
1
ADD
1
ADD
28
1
ADD
29
1
ADD
2A
1
28
ADD
1
2C
ADD
1
20
ADD
1
2E
ADD
2F
1
ADD
JN8
30
3
ACALL
31
2
1
RETI
32
8OC51~31S
___________________________
HEX NUMB.
OF
CODE BYTES
OPERANDS
33
34
35
36
37
38
39
3A
38
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
48
4C
40
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
50
5E
5F
60
61
62
63
64
65
code addr
code addr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr,code addr
code addr
code addr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr,code addr
code addr
A
A,data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
bit addr,code addr
code addr
1
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
MNEM.
RLC
ADDC
ADDC
AD DC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
JC
AJMP
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
JNC
ACALL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
JZ
AJMP
XRL
XRL
XRL
XRL
Table 2 : Instruction Opcodes in Hexadecimal Order.
6-37
OPERANDS
A
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
data addr,A
data addr,#data
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
data addr,A
data addr,#data
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
data addr A
data addr,#data
A,#data
A,data addr
- - - - - - - - - - - - - 80C51S/8OC31S _ _ _ _ _ _ _ _ _ _ _ __
HEX NUMB.
OF
CODE BYTES
66
67
68
69
6A
6B
6C
60
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
70
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
1
1
1
1
1
1
1
1
1
1
2
2
2
1
2
3
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
3
2
2
2
2
2
2
2
2
2
2
3
2
2
1
2
2
1
1
1
MNEM.
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
JNZ
ACALL
ORL
JMP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
SJMP
AJMP
ANL
MOVC
OIV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ACALL
MOV
MOVC
SUBB
SUBB
SUBB
SUBB
SUBB
HEX NUMB.
OF
CODE BYTES
OPERANDS
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
C,bit addr
@A+OPTR
A,#data
data addr,#data
@RO,#data
@R1,#data
RO,#data
R1,#data
R2,#data
R3,#data
R4,#data
R5,#data
R6,#data
R7,#data
code addr
code addr
C,bit addr
A,@A+PC
AB
data addr,data addr
data addr,@RO
data addr,@R1
data addr,RO
data addr,R1
data addr,R2
data addr,R3
data addr,R4
data addr,R5
data addr,R6
data addr,R7
OPTR,#data
code addr
bit addr,C
A,@A+OPTR
A,#data
A,data addr
A,@RO
A,@R1
A,RO
99
9A
9B
9C
90
9E
9F
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BO
BE
BF
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
Table 2. (Cont.)
6·38
1
1
1
1
1
1
1
2
2
2
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
1
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
1
1
2
1
1
1
1
1
1
MNEM.
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
ORL
AJMP
MOV
INC
MUL
reserved
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ANL
ACALL
CPL
CPL
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
PUSH
AJMP
CLR
CLR
SWAP
XCH
XCH
XCH
XCH
XCH
XCH
XCH
OPERANDS
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
C,bi! addr
code addr
C,bit addr
OPTR
AB
@RO,data addr
@R1,data addr
RO,data addr
R1 ,data addr
R2,data addr
R3,data addr
R4,data addr
R5,data addr
R6,data addr
R7,data addr
C,bit addr
code addr
Bit addr
C
A, #data, code addr
A, data addr, code addr
@RO,#data, code addr
@R1 ,#data, code addr
RO,#data, code addr
R1 ,#data, code addr
R2,#data, code addr
R3,#data, code addr
R4,#data, code addr
R5,#data, code addr
R6,#data, code addr
R7,#data, code addr
data addr
code addr
bit addr
C
A
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
____________________________ aoC51S/8OC31S ____________________________
NUMB.
HEX
OF
CODE BYTES
CC
CD
CE
CF
DO
D1
D2
D3
D4
DS
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
EO
E1
E2
E3
E4
ES
1
1
1
1
2
2
2
1
1
3
1
1
2
2
2
2
2
2
2
2
1
2
1
1
1
2
MNEM.
XCH
XCH
XCH
XCH
POP
ACALL
SETB
SETB
DA
DJNZ
XCHD
XCHD
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
MOVX
AJMP
MOVX
MOVX
CLR
MOV
HEX NUMB.
OF
CODE BYTES
OPERANDS
A,R4
A,RS
A,R6
A,R7
data addr
code addr
bit addr
C
A
data addr,code addr
A,@RO
A,@R1
RO,code addr
R1,code addr
R2,code addr
R3,code addr
R4,code addr
RS,code addr
R6,code addr
R7,code addr
A,@DPTR
code addr
A,@RO
A,@R1
A
A,data addr
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
FS
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
OPERANDS
MNEM.
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVX
ACALL
MOVX
MOVX
CPL
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,RS
A,R6
A,R7
@DPTR,A
code addr
@RO,A
@R1,A
A
data addr,A
@RO,A
@R1,A
RO,A
R1,A
R2,A
R3,A
R4,A
RS,A·
R6,A
R7,A
Table 2. (Cont.)
F
R
P
5
D
J
T
Temperature Range
blank: Commercial
T
Package Type
P: Plastic
S: PLCC
D: Cerdip
R :LCC
J : J leaded LCC
80C31S
80C51S
xxx
T
Part Number
Customer Rom Code
(80CS1S only)
80CS1S Rom 4 K x 8
80C31 S External Rom
F: Flat Pack
6·39
:R
T
Tape and Reel
-------i.'1i IllS
---S-ep-te-m-b-er-1g-a-g
80C51-L/80C31-L
DATA SHEET
CMOS SINGLE-CHIP
8 BIT MICROCONTROLLER-LOW POWER
• 8OC51-L-CMOS SINGLE-SHIP 8-BIT MICROCONTROLLER with factory mask-programmable ROM
• 8OC31-L-CMOS SINGLE-CHIP 8-BIT CONTROL-ORIENTED CPU with RAM and 1/0
• 8OC51-UC31-L: 0 TO 6 MHz, VCC = 2.7 V TO 6 V
FEATURES
•
•
•
•
•
•
•
POWER CONTROL MODES
128x8BITRAM
32 PROGRAMMABLE 1/0 LINES
TWO 16-BIT TIMER/COUNTERS
64 K PROGRAM MEMORY SPACE
FULLY STATIC DESIGN
HIGH PERFORMANCE SAJI VI CMOS PROCESS
•
•
•
•
•
BOOLEAN PROCESSOR
5 INTERRUPT SOURCES
PROGRAMMABLE SERIAL PORT
64 K DATA MEMORY SPACE
TEMPERATURE RANGE:
Commercial, Industrial
DESCRIPTION
.
r--------------------------,
POO-f07
P20 P27
r--------------'~~ ~~---------------------------
.s..:
-,
p
MHS's 80C51 and 80C31 are high
performance CMOS versions of the
8051/8031 NMOSsingiechip8bitJ.l.C
and is manufactured using a selfaligned silicon gate CMOS process
(SAJI VI).
The fully static design of the MHS
80C51/80C31 allows to reduce system power consumption by bringing
the clock frequency down to any
value, even DC, without loss of data.
--
The 80C51 retains all the features of
the 8051 : 4 K bytes of ROM; 128
bytes of RAM ; 32 I/O lines ; two 16 bit
timers; a 5-source 2-level interrupt
structure; a full duplex serial port;
and on-<:hip oscillator and clock circuits.
D
fA
:
1
'~
':.
CIIC
-t!t!;;-~L_____
", •. ""
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----'
In addition, the 80C51 has two
software-selectable
modes
of
reduced activity for further reduction
in power consumption. In the idle
Mode the CPU is frozen while the
~b~b~~~
the interrupt system continue to function. In the Power Down Mode the
RAM is saved and all other functions
are inoperative.
The 80C31 is identical to the 80C51
except that it has no on-Chip ROM.
Figure 1 : Block Diagram.
MATRA MHS
_,"
----------------------------SOC51·USOC31·L ____________________________
vee
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.01RXD
P3.11TXD
P3.2I1NTO
P3.3I1NT1
P3.4ITO
P3.51T1
P3.6JWR
P3.7/RD
XTAL2
XTAL1
VSS
PO.O
PO.1
PO.2
PO.3
PO.4
PO.5
PO.6
PO.7
EA
ALE
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
INDEX
CORNER
-----..
:6:
:5: :4: :3: :2: 1:
..................
:
,
P1.5
:44! :43!
:.u: :41: :...:
................
Io • •
P1.8
P1.7
RST
80C31 -l/80C51 -L
P3D
He
1'3.1
P3.2
P3.3
PM
P3.6
P-.
p • • • • • • - • • oo • • oo.
:18: :19: :20: :21:
OIL
P_.
:23: :24:
:22;
poo.
:~
roo •
PLCC
PI4 PI3 Pu! Pu PIO NC Vee P oo POI POi! P03
PI'
44 43 42 41 40 39 38 37 36 35 34
Ie
PI6
PI7
RST
4
30
P07
P30
5
29
rA
NC
6
28
NC
n
P04
2
32
Po,
3
31
P06
80C31-L/80C51-L
P31
7
27
P32
8
26
ALE
PSEN
P33
9
25
P27
P34
10
24
P26
P35
11
23
Pi!:!
Flat Pack
Diagrams are for pin reference only. Package sizes are not to scale.
Figure 2 : Configurations.
6-42
• _ • • oo.
:z: :27: :m:
--------------______________ BOCS1-UBOC31-L ____________________________
IDLE AND POWER DOWN OPERATION
PCON : Power Control Register
Figure 3 shows the internal Idle and Power Down clock
configuration. As illustrated, Power Down operation
stops the oscillator. Idle mode operation allows the interrupt, serial port, and timer blocks to continue to function while the clock to the CPU is gated off.
These special modes are activated by software via the
Special Function Register, its hardware address is 8?H.
PCON is not bit addressable.
(MSB)
I SMODI
Symbol
SMOD
(LSB)
-
I -
I -
I GF1 I GFO I PO IIDL I
Position Name and Function
PCON.? Double Baud rate bit. When set
to a 1, the baud rate is doubled
when the serial port is being
used in either modes 1, 2 or 3.
PCON.6 (Reserved)
PCON.5 (Reserved)
PCON.4 (Reserved)
GF1
PCON.3 General-purpose flag bit.
GFO
PCON.2 General-purpose flag bit.
PO
PCON.1
Power Down bit. Setting this bit
activates power down operation.
IDL
PCON.O Idle mode bit. Setting this bit activates idle mode operation.
If 1's are written to PO and IDL at the same time. PO
takes precedence. The reset value of PCON is
(OXXXOOOO).
Figure 3 : Idle and Power Down Hardware.
MODE
PROGRAM MEMORY
ALE
PSEN
PORTO
PORT1
PORT2
PORT3
Idle
Internal
1
1
Port Data
Port Data
Port Data
Port Data
Idle
External
1
1
Floating
Port Data
Address
Port Data
Power
Down
Internal
0
0
Port Data
Port Data
Port Data
Port Data
Power
Down
External
0
0
Floating
Port Data
Port Data
Port Data
Table 1 : Status of the external pins during Idle and Power Down modes.
IDLE MODE
enabled interrupt, the service routine can examine the
status of the flag bits.
The instruction that sets PCON.O is the last instruction
executed before the Idle mode is activated. Once in the
Idle mode the CPU status is preserved in its entirety:
the Stack Pointer, Program Counter, Program Status
Word, Accumulator, RAM, and all other registers maintain their data during Idle. Table 1 describes the status
of the external pins during Idle mode.
The second way of terminating the Idle mode is with a
hardware reset. Since the oscillator is still running, the
hardware reset needs to be active for only 2 machine
cycles (24 oscillator periods) to complete the reset
operation.
POWER DOWN MODE
There are two ways to terminate the Idle mode. Activation of any enabled interrupt will cause PCON.O to be
cleared by hardware, terminating Idle mode. The interrupt is serviced, and following RETI, the next instruction
to be executed will be the one following the instruction
that wrote a 1 to PCON.O.
The instruction that sets PCON.1 is the last executed
prior to entering power down. Once in power down, the
oscillator is stopped. The contents of the on chip RAM
and the Special Function Register is saved during
power down mode. A hardware reset is the only way of
exiting the power down mode. The hardware reset initiates the Special Function Register (see Table 1).
The flag bits GFO and GF1 may be used to determine
whether the interrupt was received during normal execution or during the Idle mode. For example, the instruction that writes to PCON.O can also set or clear one or
both flag bits. When Idle mode is terminated by an
In the Power Down mode, Vee may be lowered to minimize circuit power consumption. Care must be taken
to ensure the voltage is not reduced until the power
6-43
- - - - - - - - - - - - - S O C 5 1 . L / 8 O C 3 1 . L -_ _ _ _ _ _ _ _ _ _ __
down mode is entered, and that the voltage is restored
before the hardware reset is applied which frees the oscillator. Reset should not be released until the oscillator
has restarted and stabilized.
SpeCifications. When the input goes below approximately 2 V, T3 tums off to save ICC current. Note,
when returning to a logical 1, T2 is the only internal pullup that is on. This will result in a slow rise time if the
user's circuit does not force the input line high.
Table 1 describes the status of the external pins while
in the power down mode. It should be noted that if the
power down mode is activated while in external program memory, the port data that is held in the Special
Function Register P2 is restored to Port 2. If the data is
a I, the port pin is held high during the power down
mode by the strong pullup, Tl, shown in figure 4.
SOC31/S0C51 PIN DESCRIPTIONS
Vss
Circuit ground potential
Vee
STOP CLOCK MODE
Supply voltage during normal, Idle, and Power Down
operation.
Due to static deSign, the MHS 80C31/C51 clock speed
can be reduced until 0 MHz without any data loss in
memory or registers. This mode allows step by step
utilization, and permits to reduce system power consumption by bringing the clock frequency down to any
value. At 0 MHz, the power consumption is the same
as in the Power Down Mode.
Port 0
Port 0 is an 8-bit open drain bi-directionall/O port. Port 0
pins that have l's written to them float, and in that state
can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and Data
Memory. In this application it uses strong internal pullups when emitting l's. Port 0 also outputs the code
bytes during program verification in the BOC51. External
pullups are required during program verification. Port 0
can sink eight LSTIL inputs.
SOC51 I/O PORTS
The I/O port drive of the 80C51 is similar to the 8051.
The I/O buffers for Ports I, 2 and 3 are implemented as
shown in figure 4.
Where the port latch contains a 0, all pFETS in figure 4
are off while the nFET is turned on. When the port latch
makes a O-to-l transition, the nFETturns off. The strong
pulluppFET, Tl, turns on for two oscillator periods, pulling the output high very rapidly. As the output line is
drawn high, pFET T3 turns on through the inverter to
supply the IOH source current. This inverter and T3 form
a latch which holds the 1 and is supported by T2. When
Port 2 is used as an address port, for access to external
program of data memory, any address bit that contains
a 1 will have his strong pullup turned on for the entire
duration of the external memory access.
Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pu 1lups. Port 1 pins that have l's written to them are pulled
high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 1 pins that are externally
being pulled low will source current (ilL, on the data
sheet) because of the internal pullups.
Port 1 also receives the low-order address bytes during
program verification. In the 80C51, Port 1 can
sink/source three LS TIL inputs. It can drive CMOS inputs without external pullups.
When an I/O pin on Ports I, 2, or 3 is used as an input,
the user should be aware that the external circuit must
sink current during the logical 1-10-0 transition. The
maximum sinkcurrentis specified as ITL under the D.C.
1I
~
Port 2
Port 2 is an B-bit bi-directionall/O port with internal pullups. Port 2 pins that have l's written to them are pulled
high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 2 pins that are externally
being pulled low will source current (IlL, on the data
sheet) because of the internal pullups. Port 2 emits the
high-order address byte during fetches from external
Program Memory and during accesses to external Data
Memory that use 16-bit addresses (MOVX @ DPTR).
In this application, it uses strong intemal pullups when
emitting l's. During accesses to external Data Memory
that uses B-bit addresses (MOVX @ Ri), Port 2 emits
the contents of the P2 Special Function Register.
C>-...L._--.......I . - - * . . 1
IJIIt:H
It also receives the high-order address bits and control
signals during program verification in the BOC51. Port 2
can sink/source three LS TTL inputs. It can drive CMOS
inputs without external pullups.
Figure 4 : I/O Buffers in the 80C51 (Ports I, 2, 3).
6-44
- - - -_ _ _ _ _ _ _ _ _ 8OC51.U8OC31·L _ _ _ _ _ _ _ _ _ _ _ __
Port 3
Port 3 is an 8-bit bi-directional I/O port with intemal pullups. Port 3 pins that have 1's written to them are pulled
high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 3 pins that are externally
being pulled low will source current (ilL, on the data
sheet) because of the pullups. It also serves the functions of various special features of the MHS-51 Family,
as listed below.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Function
RXD (serial input port)
TXD (serial output port)
INTO (extemal interrupt 0)
INT1 (extemal interrupt 1)
TO (Timer 0 extemal input)
I1jTimer 1 extemal input)
WR (external Data Memory write strobe)
RD (external Data Memory read strobe)
Port 3 can sink/source three LS TTL inputs. It can drive
CMOS inputs without extemal pullups.
RST
A high level on this for two machine cycles while the oscillator is running resets the device. An internal pulldown resistor permits Power-On reset using only a
capacitor connected to Vee.
XTAL1
Input to the inverting amplifier that forms the oscillator.
Receives the extemal OSCillator signal when an extemal
oscillator is used.
XTAL2
Output of the inverting amplifier that forms the oscillator,
and input to the intemal clock generator. This pin should
be floated when an extemal oscillator is used.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output respectiveIy, of an inverting amplifier which is configured for use
as an on-chip oscillator, as shown in figure 5. Either a
quartz crystal or ceramic resonator may be used.
To drive the device from an extemal clock source,
XTAL1 should be driven while XTAL2 is left unconnected as shown in figure 6. There are no requirements
on the duty cycle of the extemal clock signal, since the
inputto the intemal clocking circuitry is through a divideby-two flip-flop, but minimum and maximum high and
low times specified on the Data Sheet must be observed.
ALE
Address Latch Enable output for latching the low byte
of the address during accesses to extemal memory.
ALE is activated as though for this purpose at a constant
rate of 1/6 the oscillator frequency except during an extemal data memory access at which time one ALE
pulse is skipped. ALE can sink/source 8 LS TTL inputs.
It can drive CMOS inputs without an extemal pullup.
PSEN
Program Store Enable output is the read strobe to extemal Program Memory. PSEN is activated twice each
machine cycle during fetches from extemal Program
Memory. (However, when executing out of extemal
Program Memory, two activations of PSEN are skipped
during each access to extemal Data Memory). PSEN
is not activated during fetches from internal Program
Memory. PSEN can sink/source 8 LS TTL inputs. It can
drive CMOS inputs without an extemal pullup.
When EA is held high, the CPU executes out of intemal
Program Memory (unless the Program Counter exceeds OFFFH). When EA is held low, the CPU executes
only out of extemal Program Memory. EA must not be
floated.
.-----------------------------~vss
Figure 5 : Crystal Oscillator.
N C - XTAL2
EXTERNAL
OSCII..LAIOR
SIGNAl..
XTAL1
r-_ VSS
1.----
Figure 6 : Extemal Drive Configuration.
- - - - - -_ _ _ _ _ _ _ _ 8OC51.L/80C31·L _ _ _ _ _ _ _ _ _ _ _ _ __
ABSOLUTE MAXIMUM RATINGS·
• NOTICE:
Ambient Temperature Under Bias:
C = CommerciaL .................................. O·C to 70·C
1= Industrial .................................... - 40·C to 85·C
Storage Temperature ..................... - 65·C to + 150·C
Voltage on VCC to VSS ...................... - 0.5 V to + 7 V
Voltage on Any Pin to VSS .... - 0.5 V to VCC + 0.5 V
Power Dissipation .............................................. 1 W"
Stresses at or above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.
•• This value is based on the maximum allowable die tempera·
ture and the thermal resistance of the package.
DC CHARACTERISTICS
TA =-40·C to 85·C ; Vcc =2.7 Vt06 V; VSS= 0 V; F = 0 to 6 MHz
SYMBOL
PARAMETER
MIN
MAX
UNIT
-0.5
0.2 Vce
-0.1
V
Vee
V
VIL
Input Low Voltage
VIH
Input High Voltage
(Except XTALs and RST)
0.2 Vec
+ 0.9
Input High Voltage to RST for Reset
0.7 Vec
VIH1
TEST CONDITIONS
+ 0.5
Vcc
V
+ 0.5
VIH2
Input High Voltage to XTAL1
0.7 Vee
Vec
V
+ 0.5
VPD
Power Down Voltage to Vec in PD Mode
VOL
Output Low Voltage (Ports 1, 2, 3)
VOL1
Output Low Voltage Port 0, ALE, PSEN
VOH
Output High Voltage Ports 1, 2, 3
VOH1
ilL
Output High Voltag~J!:9rt 0 in External
Bus Mode), ALE, PSEN
2.0
6.0
V
0.45
V
10L = 1.6 mA (note 1)
V
10L = 3.2 mA (note 1)
V
10H = -10
V
10H =-60 IlA
V cc =5V±10%
10H =-80J.lA
0.45
0.9 Vee
2.4
V
0.9 Vee
2.4
Logical 0 Input Current Ports 1, 2, 3
V
C I-50
IlA
IlA
10H = - 800 IlA
V ee =5V±10%
Yin = 0.45 V
11-60
III
Input Leakage Current
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2, 3)
ICCPD
RRST
CIO
IlA
IlA
0.45 < Yin < Vec
-500
Vee = 2.0 V to 5.5 V
(note 2)
± 10
Power Supply Current
(Power Down Mode)
10
50
IlA
RST Pulldown Resistor
50
150
kQ
10
pF
Capacitance of I/O Buffer
Note 1 :
Capacitive loading on Ports 0 and 2 may cause
spurious noise pulses to be superimposed on the VOLS
of ALE and Ports 1 and 3. The noise is due to external
bus capacitance discharging into the Port 0 and Port 2
pins when these pins make 1-to-0 transitions during bus
Yin = 2.0 V
fc = 1 MHz, TA = 25°C
operations. In the worst cases (capacitive loading
100 pF), the noise pulse on the ALE line may exceed
0.45 V with maxi VOL peak 0.6 V. A Schmitt Trigger use
is not necessary.
6-46
- - - - - - -_ _ _ _ _ _ _ aOC51-U8OC31-L _ _ _ _ _ _ _ _ _ _ _ _ __
EXTERNAL CLOCK DRIVE CHARACTERISTICS (XT AL 1 )
SYMBOL
VARIABLE CLOCK
FREQ = 0 to 6 MHz
MIN
MAX
PARAMETER
UNIT
TCLCL
Oscillator Period
166
ns
TCHCX
High Time
TCLCX
Low Time
20
20
ns
ns
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
10iCX
VCC-O.5VL- ______~~====~
OA5V
~
-~
AC CHARACTERISTICS
(TA = - 40°C to 85°C, VCC = 2.7 V to 6 V, VSS = 0 V)
(Load Capacitance for Port 0, ALE, and PSEN = 100 pf ; Load Capacitance for All Other Outputs = 80 pf).
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
SYMBOL
PARAMETER
MIN
TLHLL
ALE Pulse Width
2TCLCL-40
TAVLL
Address Valid to ALE
TCLCL-55
TLLAX
Address Hold After ALE
TLLlV
ALE to Valid Instr In
TLLPL
ALE to PSEN
TCLCL-25
TPLPH
PSEN Pulse Width
3TCLCL-35
TPLIV
PSEN to Valid Instr In
TPXIX
Input Instr Hold After PSEN
TPXIZ
Input Instr Float After PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid Instr In
TPLAZ
PSEN Low to Address Float
MAX
UNIT
4TCLCL-170
ns
ns
ns
ns
ns
ns
ns
. TCLCL-35
3TCLCL-220
0
ns
TCLCL-20
TCLCL-8
5TCLCL-220
0
See next page for Extemal Data Memory Characteristics.
6-47
ns
ns
ns
ns
- - - - - - - - - - - - - aoC51·L/80C31·L -
_ _ _ _ _ _ _ _ _ _ __
EXTERNAL DATA MEMORY CHARACTERISTICS
SYMBOL
PARAMETER
MIN
MAX
UNIT
TRLRH
RD Pulse Width
6TCLCL-100
ns
TWLWH
WR Pulse Width
6TCLCL-100
ns
TLLAX
Data Address Hold After ALE
TRLDV
RD to Valid Data In
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
2TCLCL-70
ns
TLLDV
ALE to Valid Data In
STCLCL-150
ns
TAVDV
Address to Valid Data In
9TCLCL-165
ns
TLLWL
ALE to WR or RD
3TCLCL+50
ns
TAVWL
Address to WR or RD
TQVWX
Data Valid to WR Transition
TQVWH
Data Setup to WR High
TWHQX
Data Hold After WR
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
TCLCL-50
ns
5TCLCL-165
ns
ns
0
3TCLCL-50
4TCLCL-130
ns
TCLCL-60
ns
7TCLCL-150
ns
TCLCL-50
TCLCL-40
ns
0
ns
TCLCL+40
ns
MAXIMUM Icc (mA)
OPERATING (NOTE 3)
IDLE (NOTE 4)
FREQ.VCC
2.7 V
5V
6V
2.7 V
5V
6V
1 MHz
6 MHz
O.S mA
4mA
1.5 mA
SmA
1.S mA
10 mA
400 J.IA
1.2 mA
SOO J.IA
3.5mA
1 mA
3.S mA
Note 2 : Power Down lee is measured with all output
pins disconnected; EA = Port 0 = Vee; XTAL2 N.C. ;
RST = Vss
Note 3 : lee is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns,
VIL= Vss+0.5V ;VIH=Vee-0.5 V ;XTAL2 N.C. ; EA=
RST = Port 0 = Vee. lee would be slightly higher if a crystal oscillator is used.
Note 4 : Idle lee is measured with all output pins disconnected ;XTAL1 driven TCLCH, TCHCL=5ns,VIL =
Vss + 0.5 V ; VIH = Vee - 0.5 V; XTAL2 N.C. ; Port 0 =
Vee; EA = RST = Vss.
EXPLANATION OF THE AC SYMBOLS
EXAMPLE:
Each timing symbol has 5 characters. The first character is always a ' T' (stands for time). The other characters, depending on their positions, stand for the name
of a signal or the logical status of that signal. The following is a list all the characters and what they stand for.
TAVLL = Time for Address Valid to ALE low.
TLLPL = Time for ALE low to PSEN low.
A: Address.
C: Clock.
D : Input data.
H : Logic level HIGH.
I : Instruction (program memory contents).
L : Logic level LOW, or ALE.
P: PSEN.
Q : Output data.
R : READ signal.
T:Time.
V: Valid.
W : WRITE signal
X : No longer a valid logic level.
Z: Float.
- - - - - - - - - - -_ _ _ BOCS1-UBOC31-L _ _ _ _ _ _ _ _ _ _ _ _ __
AC TIMING DIAGRAMS
EXTERNAL PROGRAM MEMORY READ CYCLE
~----------------------12~------------------------_.~
ALE
INSIRIN
AOCIlESS
ADDRESS AB-A15
PORT 2 OR SFR-P2
ADDRESS AB-A15
EXTERNAL DATA MEMORY READ CYCLE
TWHLH
~--------~~~.--------nuw--------~·~I
PORrO
PORr2
AIlIJII;SS A&A15 OR 5fR-P2
EXTERNAL DATA MEMORY WRITE CYCLE
lWHLH-'-\--,...."'"
PORrO __________
~
ADIlRESS AB-A16 OR 5fR-P2
PORr2
AC TESTING INPUT/OUTPUT, FLOAT WAVEFORMS
INPUT/OUTPUT
~-------ROM------~
VOL+D.1V
AC inputs during testing are driven at Vee - 0.5 for a logic" 1 "and 0.45 V for a logic" 0 ". Timing measurements are
made at VIH min for a logic" 1 " and VIL max for a logic" 0 ". For timing purposes a port pin is no longer floating
when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOHNOL
level occurs. IOUIOH 2: ± 20 mAo
6-49
--------------------_______ 80C51·U8OC31·L ___________________________
SERIAL PORT TIMING - SHIFT REGISTER MODE
A.C. CHARACTERISTICS:
TA
=-
40'C to + 85'C ; VSS
SYMBOL
TXLXL
= 0 V; VCC = 2.7 V to 6 V ; Load Capacitance = 80 pF)
PARAMETER
MIN
Serial Port Clock Cycle Time
UNIT
MAX
12TCLCL
ns
TOVXH
Output Data Setup to Clock Rising Edge
10TCLCL-133
ns
TXHOX
Output Data Hold After Clock Rising Edge
2TCLCL-117
ns
TXHDX
Input Data Hold After Clock Rising Edge
TXHDV
Clock Rising Edge to Input Data Valid
ns
0
10TLCL-133
ns
SHIFT REGISTER TIMING WAVEFORMS
INSIlIUCflON
I
2
0
I- lCYXH-I1
OIIIPUT DATA
\
0
8
4
TXHQX
Xr-~X
X'-_--..JX
UHW~ j~~~
4
X__ X
--.l
6
x__--.l1
SET11
I
SETRI
6-50
-
_ _ _ _ _ _ _ _ _ _ _ _ _ 8OC51·U8OC31·L _ _ _ _ _ _ _ _ _ _ _ _ __
CLOCK WAVEFORMS
X1I\I..2
'
~
ALE
_____.....1
THESE SIGNALS ARE NOr
ACTIVRED DURING THE
I
EXEOJTlON OF A MOVX INSTRUCTION
I
t
I
L
PO
P2(EXT)
REAP CYClE
m
---------------------,
DOH IS EMI1T8)
PO
Po.otrrUF PROGRAM
________~~~~~~~~D~--~!~~+~.~~;~;::;;:~ROM~~~§~~DI'lA~~~::::::~~~~1~
INDICIIlES IlPH OR P2 SFRlO PCH TRANSITIONS
I
Pa.otrr(EVEN FPROGRAM
..__________....1
- Me.1ORV IS INTERNAL)
PO
P2
PORf 0PERIiT!0N
I
OlD DI'lA NEW DI'lA
MOVPORrSRC
MCNIlESfPO
1:::::1
-....I. -rp~ PINS SAMPlED
MCNteltPORT-(P1-.P2.P3--)
(1NCUJIlESINTO-INUTO-T1)
71....------------________r=I
~:~--Q.DCK-----.:.~-p.1. . m_-..
6f~
IRICO SAMPI.S)
This diagram indicates when signals are clocked intemally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (TA = 25'C fully loaded) RD
and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are
incorporated in the AC specifications.
6-51
- - - - - - - -_ _ _ _ _ _ 8OC51·L/80C31·L _ _ _ _ _ _ _ _ _ _ _ _ __
ARITHMETIC OPERATIONS
MNEMONIC
DESCRIPTION
ADD
ADD
ADD
ADD
AD DC
ADDC
AD DC
AD DC
SUBB
SUBB
SUBB
SUBB
INC
INC
INC
INC
INC
DEC
DEC
DEC
DEC
MUL
DIV
DA
Add register to Accumulator
Add direct byte to Accumulator
Add indirect RAM to Accumulator
Add immediate data to Accumulator
Add register to Accumulator with Carry
Add direct byte to A with Carry flag
Add indirect RAM to A with Carry flag
Add immediate data to A with Carry flag
Subtract register from A with Borrow
Subtract direct byte from A with Borrow
Subtract indirect RAM from A with Borrow
Subtract immed. data from A with Borrow
Increment Accumulator
Increment register
Increment direct byte
Increment indirect RAM
Increment Data Pointer
Decrement Accumulator
Decrement register
Decrement direct byte
Decrement indirect RAM
Multiply A & B
Divide A by B
Decimal Adjust Accumulator
A,Rn
A,direct
A,@Ri
A,#data
A,Rn
A,direct
A,@Ri
A,#data
A,Rn
A,direct
A,@Ri
A,#data
A
Rn
direct
@Ri
DPTR
A
Rn
direct
@Ri
AB
AB
A
LOGICAL OPERATIONS
MNEMONIC
DESTINATION
ANL
ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
CLR
CPL
RL
RLC
RR
RRC
SWAP
AND register to Accumulator
AND direct byte to Accumulator
AND indirect RAM to Accumulator
AND immediate data to Accumulator
AND Accumulator to direct byte
AND immediate data to direct byte
OR register to Accumulator
OR direct byte to Accumulator
OR indirect RAM to Accumulator
OR immediate data to Accumulator
OR Accumulator to direct byte
OR immediate data to direct byte
Exclusive-OR register to Accumulator
Exclusive-OR direct byte to Accumulator
Exclusive-OR indirect RAM to A
Exclusive-OR immediate data to A
Exclusive-OR Accumulator to direct byte
Exclusive-OR immediate data to direct
Clear Accumulator
Complement Accumulator
Rotate Accumulator Left
Rotate A Left through the Carry flag
Rotate Accumulator Right
Rotate A Right through Carry flag
Swap nibbles within the Accumulator
A,Rn
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A,Rn
A,direct
A,@Ri
A,#data
direct,A
direct,@data
A,Rn
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A
A
A
A
A
A
A
Table 1 : MHS 51 Instruction Set Description.
6-52
BYTE
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
1
2
1
1
1
1
CYC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
4
4
1
BYTE
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
CYC
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
- - -_ _ _ _ _ _ _ _ _ _ _ _ BOC51·UBOC31·L _ _ _ _ _ _ _ _ _ _ _ _ _ __
DATA TRANSFER
MNEMONIC
DESCRIPTION
MOV
Move register to Accumulator
A,Rn
MOV
A,direct
Move direct byte to Accumulator
MOV
A,@Ri
Move indirect RAM to Accumulator
MOV
Move immediate data to Accumulator
A,#data
MOV
Rn,A
Move Accumulator to register
MOV
Rn,direct
Move direct byte to register
MOV
Rn,#data
Move immediate data to register
MOV
direct,A
Move Accumulator to direct byte
MOV
direct,Rn
Move register to direct byte
MOV
direct,direct
Move direct byte to direct
MOV
direct,@Ri
Move indirect RAM to direct byte
MOV
Move immediate data to direct byte
direct,#data
MOV
@Ri,A
Move Accumulator to indirect RAM
MOV
@Ri,direct
Move direct byte to indirect RAM
MOV
@Ri,#data
Move immediate data to indirect RAM
Load Data Pointer with a 16-bit constant
MOV
DPTR,#data 16
MOVC
A,@A+DPTR
Move Code byte relative to DPTR to A
MOVC
A,@A+PC
Move Code byte relative to PC to A
A,@Ri
Move External RAM (a-bit addr) to A
MOVX
A,@DPTR
Move External RAM (16-bit addr) to A
MOVX
MOVX
@Ri,A
Move A to External RAM (a-bit addr)
MOVX
@DPTR,A
Move A to External RAM (16-bit addr)
Push direct byte onto stack
PUSH
direct
Pop direct byte from stack
POP
direct
Exchange register with Accumulator
XCH
A,Rn
Exchange direct byte with Accumulator
XCH
A,direct
A,@Ri
Exchange indirect RAM with A
XCH
A,@Ri
XCHD
Exchange low-order nibble in RAM with A
BOOLEAN VARIABLE MANIPULATION
MNEMONIC
DESCRIPTION
CLR
Clear Carry flag
C
CLR
bit
Clear direct bit
Set Carry flag
SETB
C
Set direct Bit
SETB
bit
Complement Carry flag
CPL
C
Complement direct bit
CPL
bit
AND direct bit to Carry flag
ANL
C,bit
C,/bit
AND complement of direct bit to Carry
ANL
OR direct bit to Carry flag
ORL
C,bit
ORL
C,/bit
OR complement of direct bit to Carry
C,bit
Move direct bit to Carry flag
MOV
bit,C
Move Carry flag to direct bit
MOV
PROGRAM AND MACHINE CONTROL
MNEMONIC
DESCRIPTION
Absolute Subroutine Call
addr11
ACALL
addr16
Long Subroutine Call
LCALL
Return from subroutine
RET
Return from interrupt
RETI
Absolute Jump
addr11
AJMP
addr16
Long Jump
LJMP
rei
Short Jump (relative addr)
SJMP
Jump indirect relative to the DPTR
@A+DPTR
JMP
rei
Jump if Accumulator is Zero
JZ
rei
Jump if Accumulator is Not Zero
JNZ
rei
Jump if Carry flag is set
JC
rei
Jump if No Carry flag
JNC
Table 1. (Cont.)
6-53
BYTE
1
2
1
2
1
2
2
2
2
3
2
3
CYC
1
1
1
1
1
2
1
1
2
2
2
2
1
1
2
2
3
2
1
1
1
1
1
1
2
2
1
2
1
1
BYTE
1
2
1
2
1
2
2
2
2
2
2
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
CYC
1
1
1
1
1
1
2
2
2
2
1
2
BYTE
CYC
2
3
2
2
2
2
2
2
2
2
2
2
2
2
1
1
2
3
2
1
2
2
2
2
____________________________ 8OC51·UBOC31·L ____________________________
PROGRAM AND MACHINE CONTROL (cont.)
MNEMONIC
DESCRIPTION
JB
bit, rei
Jump if direct Bit set
JNB
JBC
CJNE
CJNE
CJNE
CJNE
DJNZ
DJNZ
NOP
bit, rei
bit, rei
A,direct,rel
A,#data,rel
Rn,#data,rel
@Ri,#data. rei
Rn,rel
direct. rei
Jump if direct Bit Not set
Jump if direct Bit is set & Clear bit
Compare direct to A & Jump if Not Equal
Compo immed. to A & Jump if Not Equal
Compo immed. to reg & Jump if Not Equal
Compo immed. to indo & Jump if Not Equal
Decrement register & Jump if Not Zero
Decrement direct & Jump if Not Zero
No operation
BYTE
3
3
3
3
3
3
3
2
3
1
CYC
2
2
2
2
2
2
2
2
2
1
Table 1. (Cont.)
Notes on data addressing modes:
Rn
direct
@Ri
#data
#data 16
bit
- Working register RO-R7
- 128 internal RAM locations, any I/O port, control or status register
-Indirect internal RAM location addressed by register RO or R1
- 8-bit constant included in instruction
- 16-bit constant included as bytes 2 & 3 of instruction
- 128 software flags, any I/O pin, control or status bit
Notes on program addressing modes:
addr 16
Addr 11
rei
- Destination address for LCALL & LJMP may be anywhere within the 64-k program memory
address space
- Destination address for ACALL & AJMP will be within the same 2-k page of program
memory as the first byte of the following instruction
- SJMP and all conditional jumps include an 8-bit offset byte. Range is + 127 -128 bytes
relative to the first byte of the following instruction.
All mnemonics copyrighted@ Intel Corporation 1979
6-54
- - - - - - - - - - - - - - 8OC51·U8OC31·L _ _ _ _ _ _ _ _ _ _ _ _ __
HEX NUMB.
CODE OF
MNEM.
BYTES
00
01
02
03
04
05
06
07
08
09
OA
08
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
18
1C
10
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
28
2C
20
2E
2F
30
31
32
1
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
1
1
2
2
1
1
1
1
1
1
1
1
1
1
3
2
1
NOP
AJMP
LJMP
RR
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
J8C
ACALL
LCALL
RRC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
J8
AJMP
RET
RL
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
JN8
ACALL
RETI
HEX NUMB.
CODE OF
MNEM.
BYTES
OPERANDS
33
34
35
36
37
38
39
3A
38
3C
3D
3E
3F
40
41
42
code addr
code addr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr,code addr
code addr
code addr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr,code addr
code addr
43
44
45
46
47
48
49
4A
48
4C
40
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
58
5C
50
5E
5F
60
61
62
A
A, data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
bit addr,code addr
code addr
63
64
65
1
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
RLC
AD DC
ADDC
ADDC
ADDC
AD DC
ADDC
ADDC
ADDC
AD DC
AD DC
AD DC
AD DC
JC
AJMP
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
JNC
ACALL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
JZ
AJMP
XRL
XRL
XRL
XRL
Table 2 : Instruction Opcodes in Hexadecimal Order.
6-55
OPERANDS
A
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
data addr,A
data addr,#data
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
data addr,A
data addr,#data
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
data addr A
data addr,#data
A,#data
A,data addr
_ _ _ _ _ _ _ _ _ _ _ _ _ _ BOC51·L/BOC31·L _ _ _ _ _ _ _ _ _ _ _ _ __
HEX NUMB.
CODE OF
MNEM.
BYTES
66
67
68
69
6A
6S
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7S
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8S
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
1
1
1
1
1
1
1
1
1
1
2
2
2
1
2
3
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
3
2
2
2
2
2
2
2
2
2
2
3
2
2
1
2
2
1
1
1
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
JNZ
ACALL
ORL
JMP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
SJMP
AJMP
ANL
MOVC
DIV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ACALL
MOV
MOVC
SUSS
SUSS
SUSS
SUSS
SUSS
HEX NUMB.
CODE OF
MNEM.
BYTES
OPERANDS
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
C,bit addr
@A+DPTR
A,#data
data addr,#data
@RO,#data
@R1,#data
RO,#data
R1,#data
R2,#data
R3,#data
R4,#data
R5,#data
R6,#data
R7,#data
code addr
code addr
C.bit addr
A,@A+PC
AS
data addr,data addr
data addr,@RO
data addr,@R1
data addr,RO
data addr,R1
data addr,R2
data addr,R3
data addr,R4
data addr,R5
data addr,R6
data addr,R7
DPTR,#data
code addr
bit addr,C
A,@A+DPTR
A,#data
A,data addr
A,@RO
A,@R1
A,RO
99
9A
9S
9C
9D
9E
9F
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AS
AC
AD
AE
AF
BO
B1
B2
S3
B4
B5
S6
B7
S8
B9
SA
BS
SC
BD
BE
SF
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CS
Table 2. (Cont.)
6-56
1
1
1
1
1
1
1
2
2
2
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
1
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
1
1
2
1
1
1
1
1
1
OPERANDS
SUSS
A,R1
SUSS
A,R2
SUSS
A,R3
SUBB
A,R4
SUSS
A,R5
SUSB
A,R6
SUSS
A,R7
ORL
C,bit addr
AJMP
code addr
MOV
C,bit addr
INC
DPTR
MUL
AS
reserved
MOV
@RO,data addr
MOV
@R1 ,data addr
MOV
RO,data addr
MOV
R 1,data addr
MOV
R2,data addr
MOV
R3,data addr
MOV
R4,data addr
MOV
R5,data addr
MOV
R6,data addr
MOV
R7,data addr
ANL
C,bit addr
ACALL
code addr
CPL
Sit addr
CPL
C
CJNE
A,#data,code addr
CJNE
A,data addr,code addr
CJNE
@RO,#data,code addr
CJNE
@R1 ,#data,code addr
CJNE
RO,#data,code addr
CJNE
R1,#data,code addr
CJNE
R2,#data,code addr
CJNE
R3,#data,code addr
CJNE
R4,#data,code addr
CJNE
R5,#data,code addr
CJNE
R6,#data,code addr
CJNE
R7,#data,code addr
PUSH
data addr
AJMP
code addr
CLR
bit addr
CLR
C
SWAP
A
XCH
A,data addr
XCH
A,@RO
A,@R1
XCH
XCH
A,RO
A,R1
XCH
XCH
A,R2
XCH
A,R3
- - - - - - - - -_ _ _ _ _ 8OC51·U8OC31·L - - - - - - - - - - - - - -
HEX NUMB.
CODE OF
MNEM.
BYTES
1
1
1
1
2
2
2
1
1
3
1
1
2
2
2
2
2
2
2
2
1
2
1
1
1
2
CC
CO
CE
CF
DO
01
02
03
04
05
06
07
08
09
OA
DB
DC
DO
DE
OF
EO
E1
E2
E3
E4
E5
XCH
XCH
XCH
XCH
POP
ACALL
SETB
SETB
OA
OJNZ
XCHO
XCHO
OJNZ
OJNZ
OJNZ
OJNZ
OJNZ
OJNZ
OJNZ
OJNZ
MOVX
AJMP
MOVX
MOVX
CLR
MOV
HEX NUMB.
CODE OF
MNEM.
BYTES
OPERANDS
A,R4
A,R5
A,R6
A,R7
data addr
code addr
bit addr
C
A
data addr,code addr
A,@RO
A,@R1
RO,code addr
R1 ,code addr
R2,code addr
R3,code addr
R4,code addr
R5,code addr
R6,code addr
R7,code addr
A,@OPTR
code addr
A,@RO
A,@R1
A
A,data addr
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FO
FE
FF
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVX
ACALL
MOVX
MOVX
CPL
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
OPERANDS
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
@OPTR,A
code addr
@RO,A
@R1,A
A
data addr,A
@RO,A
@R1,A
RO,A
R1,A
R2,A
R3,A
R4,A
R5,A
R6,A
R7,A
Table 2. (Cont.)
F
R
P
S
D
J
I
T
Temperature Range
blank: Commercial
I : Industrial
T
80C31
80C51
xxx
T
Part Number
80C51 Rom 4 K x 8
80C31 External Rom
Package Type
P: Plastic
S: PLCC
0: Cerdip
R :LCC
J : J leaded LCC
F : Quad Flat Pack
(commercial only)
T
Customer Rom Code
(BOC51 only)
6·57
L
T
Low Power
Supply Version
:R
T
Tape and Reel
-------H IllS
---Se-p-tem-b-er-1-g8-9
80C51F
DATA SHEET
CMOS SINGLE-CHIP 8 BIT
MICROCONTROLLER WITH ROM PROTECTION
• 80C51 F - CMOS SINGLE-CHIP 8-BIT
MICROCONTROLLER with factory maskprogrammable ROM
• 8OC51F: OTO 12 MHz
• 8OC51F-1: 0 TO 16 MHz
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
SECRET ROM
POWER CONTROL MODES
128x8BITRAM
32 PROGRAMMABLE 1/0 LINES
TWO 16-BIT TIMER/COUNTERS
64 K PROGRAM MEMORY SPACE
FULLY STATIC DESIGN
HIGH PERFORMANCE SAJI VI CMOS PROCESS
BOOLEAN PROCESSOR
5 INTERRUPT SOURCES
PROGRAMMABLE SERIAL PORT
64 K DATA MEMORY SPACE
TEMPERATURE RANGE:
Commercial, Industrial
DESCRIPTION
POO·P07
:---------------~ttl; -,tlj~--------------------------:
.a: ,
--.
,,
P
!
I
........
I
I
iI
,,
,,
,
,
,
_____________ J,
I
:'----'---'
I
I
I
I
!~
t~r-----
I
I
I
MHS provides a new member in the
80C51 Family named " 80C51F "which
permits full protection of the internal
ROM contents.
With a non protected 80C51 , it is very
easy to read out the contents of the internal 4 K bytes of ROM.
Three methods exist, two of them are
special test modes and the last one is by
means of MOVC instructions.
• Test mode "VER" : Using this special test mode, the internal ROM contents are output on port PO ; the address being applied on ports P2
(AD15 .. AD8) and P1 (AD7 .. ADO).
• Test mode "TMB" : With this second
test mode, the contents ofthe 80C51
internal bus is presented on port P1
during the PH2 clock phases .
• Using MOVC instructions : If EA =
0, and following a reset, the 80C51
fetches its instructions from external
program memory. It is then possible
to write a small program whose purpose is to dump the internal ROM
contents by means of MOVC A, @A
+ DPTR and MOVC A, @A + PC instructions.
Figure 1 : Block Diagram.
6-59
MATRA MHS
8OC51F
80C51 F WITH PROGRAM PROTECTION
FEATURES
This new version adds ROM protection features in
some strategic points of the 80C51 F in order to
eliminate the possibility of reading the ROM contents
(once the protection has been programmed) by one if
the three forementioned methods (VER and TMB test
modes, or MOVC instructions).
Nevertheless the customer must note the following :
• After protection is activated: It is then no longer
possible to dump the internal ROM contents.
HOW TO PROGRAM THE PROTECTION
MECHANISM
• To burn correctly the fuse a specific configuration of
inputs must be settled as below:
RST = ALE
o
=1
P2.7 = 1
• Futhermore PSEN signal must be tied at + 9 V ± 5 %
level voltage and a pulse must be applied on P2.6
input Port. The timing on P2.6 is shown below:
o
o
o
Once the protection has been programmed, the
80C51 F program always starts at address 0 in
the internal ROM.
The application program must be self contained
in the internal 4 K of ROM, otherwise it would be
possible to trap the program counter address in
the external PROM/EPROM (beyond 4 K) and
then to dump the internal ROM contents by
means of a patch using MOVC instructions.
P2.6
SV
Thus, if an extra EPROM is necessary, it is advised to
ensure that it will contain only constants or tables.
O-+------~--~r'------------~~
:"'SOms
TEST OF THE ON·CHIP PROGRAM
MEMORY
• Before protection is activated: The 80C51 F can
be tested as any normal 80C51 (using test equipment or any other methods).
II
Pl.0
Pl.1
Pl.2
Pl.3
P1.4
P1.5
P1.6
Pl.7
RST
P3.01RXD
P3.11TXD
P3.2nNTO
P3.3nNTl
P3.4ffO
P3.51T1
P3.61WR
P3.71RD
XTAL2
XTALl
VSS
1
40
39
38
2
3
4
5
6
7
8
9
10
11
12
'.IT
36
35
34
IL
B
i
13
14
15
16
17
18
19
20
33
32
31
30
29
28
27
26
25
24
23
22
21
Time Rise and Fall Rise ~ 100 ~.
• The electrical schematic shows a typical application
to deliver P2.6 signal.
vee
PO.O
PO. 1
PO.2
PO.3
PO.4
PO.5
PO.6
PO.7
EA
ALE
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
:6: :5: :4: :3: :2: :1:
....
....
....
......
....
PI.6
...
....
•
,
!44:
:~ :u: :41:
...................
:.w:
10 ... .
PIS
PI.7
lIST
P3lI
NC
8OC51F
PS.l
PS2
Pal!
P3.4
P3.6
........... "' .... , ........... - ... -. r-, ...... ..
:18: :19: :m: :21:
DIL
:~
:23: !24: :z: :-. :27:
PLCC
Diagrams are for pin reference only. Package sizes are not to scale.
Figure 2 : Configurations.
6-60
:~
80C51F
IDLE POWER DOWN OPERATION
Figure 3 shows the internal Idle and Power Down clock
configuration. As illustrated, Power Down operation
stops the oscillator. Idle mode operation allows the interrupt, serial port, and timer blocks to continue to function while the clock to the CPU is gated off.
These special modes are activated by software via the
Special Function Register, Its Hardware address is
87H. PCON is not bit addressable.
PCON : Power Control Register
(LSB)
(MSB)
ISMODI
-
I -
I -
I GF1 I GFO I PD IIDL I
Symbol Position Name and Function
SMOD
PCON.7 Double Baud rate bit. When set
to a 1, the baud rate is doubled
when the serial port is being
used in either modes 1, 2 or 3.
PCON.6 (Reserved)
PCON.S (Reserved)
PCON.4 (Reserved)
GF1
PCON.3 General-purpose flag bit.
GFO
PCON.2 General-purpose flag bit.
PD
PCON.1
Power Down bit. Setting this bit
activates power down operation.
IDL
PCON.O Idle mode bit. Setting this bit activates idle mode operation.
If 1's are written t 0 PD and IDL at the same time. PD
takes precedence. The reset value of PCON is
(OXXXOOOO).
Figure 3 : Idle and Power Down Hardware.
MODE
Idle
PROGRAM MEMORY
Internal
External
ALE
Power
Down
Power
Down
Idle
PSEN
PORT1
PORT2
PORT3
Port Data
Port Data
Port Data
Port Data
Address
Port Data
1
1
1
1
PORTO
Port Data
Floating
Internal
0
0
Port Data
Port Data
Port Data
Port Data
External
0
0
Floating
Port Data
Port Data
Port Data
Table 1 : Status of the external pins during Idle and Power Down modes.
IDLE MODE
The instruction that sets PCON.O is the last instruction
executed before the Idle mode is activated. Once in the
Idle mode the CPU status is preserved in its entirety :
the Stack Pointer, Program Counter, Program Status
Word, Accumulator, RAM, and all other registers maintain their data during Idle. Table 1 describes the status
of the external pins during Idle mode.
There are two ways to terminate the Idle mode. Activation of any enabled interrupt will cause PCON.O to be
cleared by hardware, terminating Idle mode. The interrupt is serviced, and following RETI, the next instruction
to be executed will be the one following the instruction
that wrote a 1 to PCON.O.
The flag bits GFO and GF1 may be used to determine
whether the interrupt was received during normal execution or during the Idle mode. For example the instruction that writes to PCON.O can also set or clear one
or both f~ag bits. When Idle mode is terminated by an
enabled Interrupt, the service routine can examine the
status of the flag bits.
The second way of terminating the Idle mode is with a
hardware reset. Since the oscillator is still running, the
hardware reset needs to be active for only 2 machine
cycles (24 oscillator periods) to complete the reset
operation.
POWER DOWN MODE
The instruction that sets PCON.1 is the last executed
prior to entering power down. Once in power down, the
oscillator is stopped. The contents of the onchip RAM
and the Special Function Register is saved during
po~er down mode. A hardware reset is the only way of
eXiting the power down mode. The hardware reset initiates the Special Function Register (see table 1).
In the Power Down mode, Vee may be lowered to minimize circuit power consumption. Care must be taken to
ensure the voltage is not reduced until the power down
mode is entered, and thatthe voltage is restored before
the hardware reset is applied which frees the oscillator.
Reset should not be released until the oscillator has restarted and stabilized.
8OC51F
80C51 F PIN DESCRIPTIONS
Table 1 describes the status of the external pins while
in the power down mode. It should be noted that if the
power down mode is activated while in external program memory, the port data that is held in the Special
Function Register P2 is restored to Port 2. If the data is
a 1, the port pin is held high during the power down
mode by the strong pullup, T1, shown in figure 4.
Vss
Circuit ground potential
Vcc
Supply voltage during normal, Idle, and Power Down
operation.
STOP CLOCK MODE
Due to static design, the MHS 80C51 F clock speed can
be reduced until 0 MHz without any data loss in memory
or registers. This mode allows step by step utilization,
and permits to reduce system power consumption by
bringing the clock frequency down to any value. At 0
MHz, the power consumption is the same as in the
Power Down Mode.
Port 0
Port 0 is an 8-bit open drain bi-directionall/O port. Port
that have 1's written to them float, and in that
state can be used as high-impedance inputs.
o pins
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and Data
Memory. In this application it uses strong internal pullups when emitting 1'So Port 0 also outputs the code
bytes during program verification in the 80C51 F. External pullups are required during program verification.
Port 0 can sink eight LSTIL inputs.
80C51 F 1/0 PORTS
The 1/0 port drive of the 80C51 F is similar to the 8051.
The 1/0 buffers for Ports 1, 2 and 3 are implemented as
shown in figure 4.
When the port latch contains a 0, all pFETS in figure 4
are off while the nFET is turned on. When the port latch
makes a 0-to-1 transition, the nFETturns off. The strong
pullup pFET, T1 , turns on for two oscillator periods, pulling the output high very rapidly. As the output line is
drawn high, PFET T3 turns on through the inverter to
supply the IOH source current. This inverter and T3 form
a latch which holds the 1 and is supported by T2. When
Port 2 is used as an address port, for access to external
program of data memory, any address bit that contains
a 1 will have his strong pullup turned on for the entire
duration of the extemal memory access.
Port 1
Port 1 is an 8-bit bi-directionalliO port with internal pullups. Port 1 pins that have 1 's written to them are pulled
high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 1 pins that are externally
being pulled low will source current (ilL, on the data
sheet) because of the internal pullups.
Port 1 also receives the low-order address bytes during
program verification. In the 80C51 F, Port 1 can
sink/source three LSTTL inputs. It can drive CMOS inputs without external pullups.
When an I/O pin on Ports 1, 2 or 3 is used as an input,
the user should be aware that the external circuit must
sink current during the logical 1-10-0 transition. The
maximum sink current is specified as ITL under the D.C.
Specifications. When the input goes below approximately 2 V, T3 tums off to save ICC current. Note,
when returning to a logical 1, T2 is the only internal pullup that is on. This will result in a slow rise time if the
user's circuit does not force the input line high.
Port 2
Port 2 is an 8-bit bi-directionall/O port with internal pullups. Port 2 pins that have 1 's written to them are pulled
high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 2 pins that are externally
being pulled low will source current (ilL, on the data
sheet) because of the internal pullups. Port 2 emits the
high-order address byte during fetches from external
Program Memory and during accesses to external Data
Memory that use 16-bit addresses (MOVX @ DPTR).
In this application, it uses strong internal pullups when
emitting 1 'So During accesses to external Data Memory
that use 8-bit addresses (MOVX@ Ri), Port 2 emits the
contents of the P2 Special Function Register.
=
G
''''''''
It also receives the high-order address bits and control
signals during program verification in the 80C51. Port
2 can sink/source three LSTIL inputs. It can drive
CMOS inputs without external pullups.
c_. . . . .-----JI---*~
Port 3
Port 3 is an 8-bit bi-directionall/O port with internal pul-
Figure 4 : 1/0 Buffers in the 80C51 F (Ports 1, 2, 3).
6·62
80C51F
XTAL1
lups. Port 3 pins that have 1's written to them are pulled
high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 3 pins that are externally
being pulled low will source current (IlL, on the data
sheet) because of the pullups. It also serves the functions of various special features of the MHS-51 Family,
as listed below.
Port Pin
Alternate Function
P3.0
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
IUTimer 1 external input)
WR (external Data Memory write strobe)
RD (external Data Memory read strobe)
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Input to the inverting amplifier that forms the oscillator.
Receives the external oscillator signal when an external
oscillator is used.
XTAL2
Output of the inverting amplifier that forms the oscillator,
and input to the internal clock generator. This pin should
be floated when an external oscillator is used.
OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output respectively, of an inverting amplifier which is configured for use
as an on-chip oscillator, as shown in figure 5. Either a
quartz crystal or ceramic resonator may be used.
Port 3 can sink/source three LS TIL inputs. It can drive
CMOS inputs without external pullups.
RST
A high level on this for two machine cycles while the oscillator is running resets the device. An internal pulldown resistor permits Power-On reset using only a
capacitor connected to Vcc.
.....---------Ivss: 20
ALE
Address Latch Enable output for latching the low byte
of the address during accesses to external memory.
ALE is activated as though for this purpose at a constant
rate of 1/6 the oscillator frequency except during an external data memory access at which time one ALE pulse
is skipped. ALE can sink/source 8 LS TIL inputs. It can
drive CMOS inputs without an external pullup.
Figure 5 : Crystal Oscillator.
To drive the device from an external clock source,
XTAL 1 should be driven while XTAL2 is left unconnected as shown in figure 6. There are no requirements
on the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a divideby-two flip-flop, but minimum and maximum high and
low times specified on the Data Sheet must be observed.
PSEN
Program Store Enable output is the read strobe to external Program Memory. PSEN is activated twice each
machine cycle during fetches from external Program
Memory. (However, when executing out of external
Program Memory, two activations of PSEN are skipped
during each access to external Data Memory). PSEN is
not activated during fetches from internal Program
Memory. PSEN can sink/source 8 LS TTL inputs. It can
drive CMOS inputs without an external pullup.
N C - X"W..2: 18
EXTERNAL
osaUAlOR----------~~1:m
SIGNAL
EA
.,c-- VSS: 2D
When EA is held high, the CPU executes out of internal
Program Memory (unless the Program Counter exceeds OFFFH). When EA is held low, the CPU executes
only out of external Program Memory. EA must not be
floated.
Figure 6 : External Drive Configuration.
6-63
8OC51F
ABSOLUTE MAXIMUM RATINGS·
• NOTICE:
Ambient Temperature Under Bias:
C = commerciaL ................................... O'C to 70'C
1= industrial ................................. - 4O'C to + 85'C
Storage Temperature ..................... - 65'C to + 150'C
Voltage on Vcc to Vss ........................ - 0.5 V to + 7 V
Voltage on Any Pin to Vss ...... - 0.5 V to VCC + 0.5 V
Power Dissipation .............................................. 1 W"
Stresses at or above those listed under" Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.
•• This value is based on the maximum allowable die tempera·
ture and the thermal resistance of the package.
DC CHARACTERISTICS (see Note 2)
TA = - 40'C to 85'C ; vee = 5 V ± 20 %; VSS = 0 V ; F = 0 to 12 MHz
TA = - 40'C to 85'C ; VCC = 5 V ± 10 % ; VSS = 0 V ; F = 0 to 16 MHz
SYMBOL
PARAMETER
MIN
MAX
UNIT
-0.5
0.2 VCC
-0.1
V
VIL
Input Low Voltage
VIH
Input High Voltage
(Except XTAL and RST)
0.2 VCC VCC + 0.5
+ 0.9
V
VIH1
Input High Voltage
(RST and XTAL1)
0.7 VCC VCC +0.5
V
VOL
Output Low Voltage (Ports 1, 2, 3)
VOL1
Output Low Voltage Port
VOH
Output High Voltage Ports 1, 2, 3
VOH1
q, ALE,
PSEN
Output High Voltage
(Port 0, ALE, PSEN)
0.45
V
10L = 1.6 mA (note 3)
0.45
V
10L = 3.2 mA (note 3)
J.IA
J.IA
60 J.IA
0.9 VCC
V
10H = -10
0.75 VCC
V
10H = - 25
2.4
V
0.9 VCC
V
10H = - 80
vcc
V
10H = -
0.75
2.4
ilL
TEST CONDITIONS
Logical 0 Input Current Ports 1, 2, 3
V
I-so
1-60
10H = -
vcc = 5 V±10 %
10H = -
J.IA
300 J.IA
800 J.IA
vcc = 5V±10 %
J.IA
Vin = 0.45 V
J.IA
J.IA
0.45 < Vin < VCC
-650
50
J.IA
vcc = 2.0 V to 6 V
150
kn
C
I
± 10
III
Logical Leakage Current (Port 0, EA)
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2, 3)
IPD
Power Supply Current
(Power Down Mode)
RRST
RST Pulldown Resistor
CIO
Capacitance of 1/0 Buffer
10
pF
fc = 1 MHz, TA = 25°C
ICC
Power supply current
Active mode 12 MHz
Idle mode 12 MHz
20
mA
mA
(notes 1, 2)
Note1:
SO
5
Vin = 2.0 V
(note 2)
ICC max is given by :
Active Mode: ICC MAX = 1.47 x FREQ + 2.35
Idle Mode: ICC MAX = 0.33 x FREQ + 1.05
where FREQ is the external oscillator frequency in MHz. ICC MAX is given in mAo See figure 1.
See figures 1 through 5 for ICC test conditions.
80C51F
\ICC
MAX
r---,------.---,---;-, ACTIVE
MODE
(NC)
a..ocK
SIGNAL
Figure 2 : ICC Test Condition, Idle Mode. All other
pins are disconnected.
o
......o
\ICC
MAX
IDLE
~~~--+-~~~~MODE
RST
oL---L---~--J---~
4 MHz 8 MHz 12 MHz 16 MHz
FREQ MX1'AL1
INC)
a..ocK
SIGNAL
Figure 1 : ICC vs. Frequency. Valid only within
frequency specifications of the device
under test.
XTAL2
XTALl
\ISS
Figure 3: ICC Test Condition, Active Mode. All other
pins are disconnected.
VCC-~O'7VCC
,
o,2VCC- O,1
O.45V
Figure 4: Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.
Note 2 : ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns,
VIL= VSS+5 V, VIH = VCC-.5 V ;XTAL2 N.C. ; EA=
RST = Port 0 = VCC. ICC would be slightly higher if a
crystal oscillator used. Idle ICC is measured with all output pins disconnected; XTAL 1 driven with TCLCH,
TCHCL = 5 ns, VIL = VSS + 5 V,
VIH = VCC -5 V; XTAL2 N.C.; Port 0 = VCC; EA =
RST=VSS.
Power Down ICC is measured with all output pins disconnected; EA = PORT 0 = VCC ; XTAL2 N.C. ; RST =
VSS.
loading 100 pF), the noise pulse on the ALE line may
exceed 0.45 V may exceed 0.45 V with maxi VOL peak
0.6 V A Schmitt Trigger use is not necessary.
Vee
Note 3 : Capacitance loading on Ports 0 and 2 may
cause spurious noise pulses to be superimposed on the
VOLS of ALE and Ports 1 and 3. The noise is due to extemal bus capacitance discharging into the Port 0 and
Port 2 pins when these pins make 1 to 0 transitions
during bus operations. In the worst cases (capacitive
Figure 5 : ICC Test Condition, Power Down Mode.
All other pins are disconnected.
6-65
i'11iMIS
80C51F
EXTERNAL CLOCK DRIVE CHARACTERISTICS (XTAL 1)
SYMBOL
VARIABLE CLOCK
FREQ = 0 to 16 MHz
MIN
MAX
62.5
20
PARAMETER
UNIT
1ITCLCL
Oscillator Frequency
TCHCX
High Time
TCLCX
Low Time
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
ns
ns
ns
20
A.C. PARAMETERS:
TA=-40'C + 85'C ; VSS=O V; VCC =5 V±20% F=Oto 12 MHz
TA=-40'C + 85'C; VSS= 0 V; VCC = 5 V± 10 % F = 0 to 16 MHz
(Load Capacitance for Port 0, ALE, and PSEN = 100 pf ; Load Capacitance for All Other Outputs = 80 pf).
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
SYMBOL
n
PARAMETER
MIN
MAX
UNIT
TLHLL
ALE Pulse Width
2TCLCL-40
TAVLL
Address Valid to ALE
TCLCL-55
ns
TLLAX
Address Hold After ALE
TCLCL-35
ns
ns
TLLlV
ALE to Valid Instr in
TLLPL
ALE to PSEN
TCLCL-40
ns
TPLPH
PSEN Pulse Width
3TCLCL-45
ns
TPLIV
PSEN to Valid Instr in
TPXIX
Input Instr Hold After PSEN
TPXIZ
Input Instr Float After PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid Instr in
TPLAZ
PSEN Low to Address Float
4TCLCL-100
ns
3TCLCL-105
ns
TCLCL-25
ns
5TCLCL-105
ns
10
ns
MAX
0
ns
TCLCL-8
ns
EXTERNAL DATA MEMORY CHARACTERISTICS
SYMBOL
TRLRH
RD Pulse Width
6TCLCL-100
UNIT
ns
TWLWH
WR Pulse Width
6TCLCL-100
ns
PARAMETER
MIN
TLLAX
Data Address Hold After ALE
TRLDV
RD to Valid Data in
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
2TCLCL-70
ns
TLLDV
ALE to Valid Data in
8TCLCL-150
ns
TAVDV
Address to Valid Data in
9TCLCL-165
ns
TLLWL
ALE to WR or RD
3TCLCL-50
3TCLCL+50
ns
4TCLCL-130
ns
TCLCL-60
ns
7TCLCL-150
ns
TAVWL
Address to WR or RD
TOVWX
Data Valid to WR Transition
TOVWH
Data Setup to WR High
TWHOX
Data Hold After WR
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
TCLCL-50
ns
5TCLCL-165
0
ns
TCLCL-50
TCLCL-40
6-66
ns
ns
0
ns
TCLCL+40
ns
80C51F
AC TIMING DIAGRAMS
EXTERNAL PROGRAM MEMORY CYCLE
~---------------------12~----------------------~
1Ut..l..
ALE
INSlRIN
ADDRESS
PORT 2 OR SFR-P2
ADDRESS A&-A15
ADDRESS AlM15
EXTERNAL DATA MEMORY READ CYCLE
1WHI.H
-------------t----------~~.-------+~--------~~----PORrO
Dlm\1II
PORr2
EXTERNAL DATA MEMORY WRITE CYCLE
PORrO ______~
PORr2
AC TESTING INPUT/OUTPUT, FLOAT WAVEFORMS
INPU1' 10UIPIJT
jt--\Qi_--Q;_~_=_:___-_-_~~w
1Ia.+o.w
~w
AC inputs during testing are driven at Vee - 0.5 for a logic "1" and 0.45 V for a logic "0". Timing measurements are
made at VIH min for a logic "1" and VIL max for a logic "0". For timing purposes a port pin is no longer floating when
a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOHNOL
level occurs. IOUIOH ;:: ± 20 mAo
6-67
80C51F
SERIAL PORT TIMING· SHIFT REGISTER MODE
SYMBOL
PARAMETER
MAX
MIN
UNIT
12TCLCL
ns
Output Data Setup to Clock Rising Edge
1OTCLCL -133
ns
TXHQX
Output Data Hold After Clock Rising Edge
2TCLCL-117
ns
TXHDX
Input Data Hold After Clock Rising Edge
TXHDV
Clock Rising Edge to Input Data Valid
TXLXL
Serial Port Clock Cycle Time
TQVXH
0
ns
1OTCLCL -133
ns
SHIFT REGISTER TIMING WAVEFORMS
INSIIIJC1lON
I
0
2
3
4
6
8
SErIl
EXPLANATION OF THE AC SYMBOLS
Example:
Each timing symbol has 5 characters. The first character is always a" T" (stands for time). The othercharacters, depending on their positions, stand for the name
of a signal or the logical status of that signal. The following is a list of all the characters and what they stand
for.
TAVLL = Time for Address Valid to ALE low.
TLLPL = Time for ALE low to PSEN low.
A: Address.
C: Clock.
D : Input data.
H : Logic level HIGH.
I : Instruction (program memory contents).
L : Logic level LOW, or ALE
P: PSEN.
Q : Output data.
R : READ signal.
T:Time.
V:Valid.
W : WRITE signal.
X : No longer a valid logic level.
Z : Float.
6·68
8OC51F
CLOCK WAVEFORMS
S1JII'E8
S1JII'E3
PlII".l
PlII".l
XTAL2
'
~
_____....1
I
1H3SE SIGNAlSNE NOr
ACIMIED IUlINGllE
EXEaIllON OF A MO\IX INSmUCl10N
I
t
I
L
P2(EXl)
!!EADCVQE
m
------------------~
PO
OUT (EVEN FPIIlGIWtI
..__________...1- PCL
MEMOlI'( IS MSINAL)'
P2
PORI'tHRIinON
I
OlD DIII"A lEW DIOl\
MOiPORrSRC
I=:t
MOVOOSTPO
tIK:N DESrPORr-(-Pl-.1'2--P3-)-_"
(1NCllJIlESINTo.INT1.To.Tl)
,"PO PHI SMtPlED
Fj=I..___________________
~~0)S1FI--g.oc:K-----.:.~P~P3I'1NSSAMPUD
-!~
I;r~
....
Pl.....
Rl(I) SAMR.al
Rl(I) SAMPlED
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (TA = 25°C fully loaded) RD
and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are
incorporated in the AC specifications.
6·69
8OC51F
II
ARITHMETIC OPERATIONS
MNEMONIC
ADD
A,Rn
ADD
A,direct
A,@Ri
ADD
ADD
A,#data
ADDC
A,Rn
ADDC
A,direct
A,@Ri
AD DC
ADDC
A,#data
SUBB
A,Rn
SUBS
A,direct
SUBB
A,@Ri
SUBB
A,#data
INC
A
INC
Rn
INC
direct
@Ri
INC
INC
DPTR
DEC
A
DEC
Rn
DEC
direct
DEC
@Ri
MUL
AB
DIV
AB
DA
A
LOGICAL OPERATIONS
MNEMONIC
ANL
A,Rn
A,direct
ANL
ANL
A,@Ri
ANL
A,#data
ANL
direct,A
ANL
direct,#data
ORL
A,Rn
A,direct
ORL
A,@Ri
ORL
ORL
A,#data
ORL
direct,A
ORL
direct,#data
XRL
A,Rn
A,direct
XRL
A,@Ri
XRL
XRL
A,#data
XRL
direct,A
XRL
direct,#data
CLR
A
CPL
A
RL
A
RLC
A
RR
A
RRC
A
SWAP
A
DESCRIPTION
Add register to Accumulator
Add direct byte to Accumulator
Add indirect RAM to Accumulator
Add immediate data to Accumulator
Add register to Accumulator with Carry
Add direct byte to A with Carry flag
Add indirect RAM to A with Carry flag
Add immediate data to A with Carry flag
Subtract register from A with Borrow
Subtract direct byte from A with Borrow
Subtract indirect RAM from A with Borrow
Subtract immed. data from A with Borrow
Increment Accumulator
Increment register
Increment direct byte
Increment indirect RAM
Increment Data Pointer
Decrement Accumulator
Decrement register
Decrement direct byte
Decrement indirect RAM
Multiply A & B
Divide A by B
Decimal Adjust Accumulator
BYTE
1
DESTINATION
AND register to Accumulator
AND direct byte to Accumulator
AND indirect RAM to Accumulator
AND immediate data to Accumulator
AND Accumulator to direct byte
AND immediate data to direct byte
OR register to Accumulator
OR direct byte to Accumulator
OR indirect RAM to Accumulator
OR immediate data to Accumulator
OR Accumulator to direct byte
OR immediate data to direct byte
Exclusive-OR register to Accumulator
Exclusive-OR direct byte to Accumulator
Exclusive-OR indirect RAM to A
Exclusive-OR immediate data to A
Exclusive-OR Accumulator to direct byte
Exclusive-OR immediate data to direct
Clear Accumulator
Complement Accumulator
Rotate Accumulator Left
Rotate A Left through the Carry flag
Rotate Accumulator Right
Rotate A Right through Carry flag
Swap nibbles within the Accumulator
BYTE
1
Table 1 : MHS - 51 Instruction Set Description.
6-70
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
1
2
1
1
1
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
CYC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
4
4
1
CYC
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
80CS1F
DATA TRANSFER
MNEMONIC
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVC
MOVC
MOVX
MOVX
MOVX
MOVX
PUSH
POP
XCH
XCH
XCH
XCHD
A,Rn
A,direct
A,@Ri
A,#data
Rn,A
Rn,direct
Rn,#data
direct,A
direct,Rn
direct,direct
direct,@Ri
direct,#data
@Ri,A
@Ri,direct
@Ri,#data
DPTR,#data 16
A,@A+DPTR
A,@A+PC
A,@Ri
A,@DPTR
@Ri,A
@DPTR,A
direct
direct
A,Rn
A,direct
A,@Ri
A,@Ri
DESCRIPTION
Move register to Accumulator
Move direct byte to Accumulator
Move indirect RAM to Accumulator
Move immediate data to Accumulator
Move Accumulator to register
Move direct byte to register
Move immediate data to register
Move Accumulator to direct byte
Move register to direct byte
Move direct byte to direct
Move indirect RAM to direct byte
Move immediate data to direct byte
Move Accumulator to indirect RAM
Move direct byte to indirect RAM
Move immediate data to indirect RAM
Load Data Pointer with a 16-bit constant
Move Code byte relative to DPTR to A
Move Code byte relative to PC to A
Move External RAM (a-bit addr) to A
Move External RAM (16-bit addr) to A
Move A to External RAM (a-bit addr)
Move A to External RAM (16-bit addr)
Push direct byte onto stack
Pop direct byte form stack
Exchange register with Accumulator
Exchange direct byte with Accumulator
Exchange indirect RAM with A
Exchange low-order nibble ind RAM with A
BOOLEAN VARIABLE MANIPULATION
MNEMONIC
CLR
CLR
SETB
SETB
CPL
CPL
ANL
ANL
ORL
ORL
MOV
MOV
C
bit
C
bit
C
bit
C,bit
C, !bit
C, bit
C, !bit
C, bit
bit,C
DESCRIPTION
Clear Carry flag
Clear direct bit
Set Carry flag
Set direct Bit
Complement Carry flag
Complement direct bit
AND direct bit to Carry flag
AND complement of direct bit to Carry
OR direct bit to Carry flag
OR complement of direct bit to Carry
Move direct bit to Carry flag
Move Carry flag to direct bit
PROGRAM AND MACHINE CONTROL
MNEMONIC
ACALL
LCALL
RET
RETI
AJMP
LJMP
SJMP
JMP
JZ
JNZ
JC
JNC
addr11
addr16
addr11
addr16
rei
@A+DPTR
rei
rei
rei
rei
DESCRIPTION
Absolute Subroutine Call
Long Subroutine Call
Return from subroutine
Return from interrupt
Absolute Jump
Long Jump
Short Jump (relative addr)
Jump indirect relative to the DPTR
Jump if Accumulator is Zero
Jump if Accumulator is Not Zero
Jump if cara flag is set
Jump if No arry flag
Table 1. (Cant)
6-71
BYTE
CYC
1
1
1
1
1
1
2
1
2
1
2
2
2
2
3
2
3
2
1
1
2
2
2
2
1
1
2
2
3
2
1
1
1
1
1
1
2
2
1
1
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
BYTE
CYC
1
1
1
1
1
1
1
2
2
1
2
1
2
2
2
2
2
2
2
BYTE
2
3
1
1
2
3
2
1
2
2
2
2
2
2
2
2
1
2
CYC
2
2
2
2
2
2
2
2
2
2
2
2
80C51F
PROGRAM AND MACHINE CONTROL (cont.)
MNEMONIC
JB
JNB
JBC
CJNE
CJNE
CJNE
CJNE
DJNZ
DJNZ
NOP
bit,rel
bit,rel
bit,rel
A,direct, rei
A,#data, rei
Rn,#data, rei
@Ri,#data. rei
Rn,rel
direct,rel
DESCRIPTION
Jump if direct Bit set
Jump if direct Bit Not set
Jump if direct Bit is set & Clear bit
Compare direct to A & Jump if Not Equal
Compo immed. to A & Jump if Not Equal
Compo immed. to reg & Jump if Not Equal
Compo immed. to indo & Jump if Not Equal
Decrement register & Jump if Not Zero
Decrement direct & Jump if Not Zero
No operation
BYTE
3
3
3
3
3
3
3
2
3
1
CYC
2
2
2
2
2
2
2
2
2
1
Table 1. (Cont.)
Notes on data addressing modes:
Rn
direct
@Ri
#data
#data 16
bit
- Working register RD-R7
- 128 internal RAM locations, any I/O port, control or status register
-Indirect internal RAM location addressed by register RD or R1
- 8-bit constant included in instruction
- 16-bit constant included as bytes 2 & 3 of instruction
- 128 software flags, any I/O pin, control or status bit
Notes on program addressing modes:
addr 16
Addr 11
rei
- Destination address for LCALL & LJMP may be anywhere within the 64-k program memory
address space
- Destination address for ACALL & AJMP will be within the same 2-k page of program
memory as the first byte of the following instruction
- SJMP and all conditional jumps include an 8-bit offset byte. Range is + 127 - 128 bytes
relative to the first byte of the following instruction.
All mnemonics copyrighted© Intel Corporation 1979
6-72
8OC51F
HEX NUMB.
OF
CODE BYTES
00
01
02
03
04
05
06
07
08
09
OA
08
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
18
1C
10
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
28
2C
20
2E
2F
30
31
32
1
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
1
1
2
2
1
1
1
1
1
1
1
1
1
1
3
2
1
MNEM.
NOP
AJMP
LJMP
RR
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
J8C
ACALL
LCALL
RRC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
J8
AJMP
RET
RL
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
JN8
ACALL
RETI
NUMB.
HEX
OF
CODE BYTES
OPERANDS
33
34
35
36
37
38
39
3A
38
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
48
4C
40
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
58
5C
50
5E
5F
60
61
62
63
64
65
code addr
code addr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr,code addr
code addr
code addr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr,code addr
code addr
A
A,data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
bit addr,code addr
code addr
1
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
MNEM.
RLC
ADDC
ADDC
ADDC
ADDC
AD DC
AD DC
ADDC
AD DC
AD DC
ADDC
ADDC
ADDC
JC
AJMP
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
JNC
ACALL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
JZ
AJMP
XRL
XRL
XRL
XRL
Table 2 : Instruction Opcodes in Hexadecimal Order.
6-73
OPERANDS
A
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
data addr,A
data addr,#data
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
data addr,A
data addr,#data
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
data addr A
data addr,#data
A,#data
A,data addr
80C51F
HEX NUMB.
OF
CODE BYTES
66
67
68
69
6A
6B
6C
60
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
70
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
1
1
1
1
1
1
1
1
1
1
2
2
2
1
2
3
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
3
2
2
2
2
2
2
2
2
2
2
3
2
2
1
2
2
1
1
1
MNEM.
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
JNZ
ACALL
ORL
JMP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
SJMP
AJMP
ANL
MOVC
OIV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ACALL
MOV
MOVC
SUBB
SUBB
SUBB
SUBB
SUBB
NUMB.
HEX
OF
CODE BYTES
OPERANDS
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
C,bit addr
@A+OPTR
A,#data
data addr,#data
@RO,#data
@R1,#data
RO,#data
R1,#data
R2,#data
R3,#data
R4,#data
R5,#data
R6,#data
R7,#data
code addr
code addr
C,bit addr
A, @A+PC
AB
data addr,data addr
data addr,@RO
data addr,@R1
data addr,RO
data addr,R1
data addr,R2
data addr,R3
data addr,R4
data addr,R5
data addr,R6
data addr,R7
OPTR,#data
code addr
bit addr,C
A,@A+OPTR
A,#data
A,data addr
A,@RO
A,@R1
A,RO
99
9A
9B
9C
90
9E
9F
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AO
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BO
BE
BF
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
Table 2. (Cont.)
6-74
1
1
1
1
1
1
1
2
2
2
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
1
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
1
1
2
1
1
1
1
1
1
MNEM.
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
ORL
AJMP
MOV
INC
MUL
reserved
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ANL
ACALL
CPL
CPL
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
PUSH
AJMP
CLR
CLR
SWAP
XCH
XCH
XCH
XCH
XCH
XCH
XCH
OPERANDS
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
C,bit addr
code addr
C,bit addr
OPTR
AB
@RO,data addr
@R1,data addr
RO,data addr
R1 ,data addr
R2,data addr
R3,data addr
R4,data addr
R5,data addr
R6,data addr
R7,data addr
C,bit addr
code addr
Bit addr
C
A, #data, code addr
A, data addr, code addr
@RO,#data, code addr
@R1 ,#data, code addr
RO,#data, code addr
R1 ,#data, code addr
R2,#data, code addr
R3,#data, code addr
R4,#data, code addr
R5,#data, code addr
R6,#data, code addr
R7,#data, code addr
data addr
code addr
bit addr
C
A
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
8OC51F
HEX NUMB.
CODE OF
MNEM.
BYTES
CC
CD
CE
CF
DO
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
EO
E1
E2
E3
E4
E5
1
1
1
1
2
2
2
1
1
3
1 .
1
2
2
2
2
2
2
2
2
1
2
1
1
1
2
XCH
XCH
XCH
XCH
POP
ACALL
SETB
SETB
DA
DJNZ
XCHD
XCHD
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
MOVX
AJMP
MOVX
MOVX
CLR
MOV
HEX NUMB.
CODE OF
MNEM.
BYTES
OPERANDS
A,R4
A,R5
A,R6
A,R7
data addr
code addr
bit addr
C
A
data addr, code addr
A,@RO
A,@R1
RO,code addr
R1 ,code addr
R2,code addr
R3,code addr
R4,code addr
R5,code addr
R6,code addr
R7,code addr
A,@DPTR
code addr
A,@RO
A,@R1
A
A,data addr
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVX
ACALL
MOVX
MOVX
CPL
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
OPERANDS
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
@DPTR,A
code addr
@RO,A
@R1,A
A
data addr,A
@RO,A
@R1,A
RO,A
R1,A
R2,A
R3,A
R4,A
R5,A
R6,A
R7,A
Table 2. (Cont.)
R
P
S
D
J
T
Temperature Range
blank: Commercial
I : Industrial
Package Type
P: Plastic
S: PLCC
D: Cerdip
J : J leaded LCC
R:LCC
T
xxx
80C51F
Part Number
80C51F Rom 4 Kx 8
-1
T
- 1 : 16 MHz Version
Customer Rom Code
6-75
:R
Tape and Reel
~~~----IIIiM11ii
IllS -~~Se-pt-em-b-er-1-98-9
80C52/80C32
DATA SHEET
CMOS SINGLE-CHIP
8 BIT MICROCONTROLLER
80C52/C32 : 0 to 12 MHz
80C52-1/C32-1 : 0 to 16 MHz
80C52S/C32S : 0 to 20 MHz
80C52-L/C32-L : Vcc = 2.7 V to 5.5 V (0 to 6 MHz)
80C52F : SECRET ROM
• 80C52 - CMOS SINGLE -CHIP 8 BIT MICROCONTROLLER with factory mask-programmabie ROM
• 80C32 - CMOS SINGLE - CHIP 8-BIT CONTROL
ORIENTED CPU with RAM and 1/0
FEATURES
•
•
•
•
•
•
•
POWER CONTROL MODES
256 x 8 BIT RAM
32 PROGRAMMABLE 1/0 LINES
THREE 16-BIT TIMERICOUNTER
64 K PROGRAM MEMORY SPACE
FULLY STATIC DESIGN
HIGH PERFORMANCE SAJI VI CMOS PROCESS
•
•
•
•
•
BOOLEAN PROCESSOR
6 INTERRUPT SOURCES
PROGRAMMABLE SERIAL PORT
64 K DATA MEMORY SPACE
TEMPERATURE RANGE: Commercial,
Industrial, Automotive and Military
DESCRIPTION
"to-PU
~~
-;tfwtH;--------------------------:
I
I
,,,
:,
,,
,
:
,
I
MHS's 80C52 and 80C32 are high
performance CMOS versions of the
8052/8032 NMOS single chip 8 bit IlC
and is manufactured using a selfaligned silicon gate CMOS process
(SAJIVI).
The fully static design of the MHS
80C52/80C32 allows to reduce system power consumption by bringing
the clock frequency down to any
value, even DC, without loss of data.
The 80C52 retains all the features of
the 8052 : 8 K bytes of ROM ; 256
bytes of RAM; 32 1/0 lines; three 16
bit timers; a 6-source, 2-level interrupt
structure; a full duplex serial port; and
on-chip oscillator and clock circuits.
In addition, the 80C52 has two
software-selectable
modes
of
reduced activity for further reduction
in power consumption. In the Idle
Mode the CPU is frozen while the
RAM, the timers, the serial port, and
the interrupt system continue to function. In the Power Down Mode the
RAM is saved and all other functions
are inoperative.
: ....._.L.-J
,,
l~
f;r----
The 80C32 is identical to the 80C52
except that it has no on-chip ROM.
Figure 1 : Block Diagram.
6-77
MATRA MHS
_
80C52/80C32
MHS provides a new member in the 80CS2 Family
named "80CS2F" which permits full protection of the internal ROM contents.
temal PROM/EPROM (beyond 8 K) and then to
dump the internal ROM contents by means of a patch
using MOVC instructions.
With a non protected 80CS2, it is very easy to read out
the contents of the internal 8 K bytes of ROM.
Thus, if an extra EPROM is necessary, it is advised to
ensure that it will contain only constants or tables.
Three methods exist, two of them are special test
modes and the last one is by means of MOVC instructions.
• Test mode "VER" : Using this special test mode, the
internal ROM contents are output on port PO ; the address being applied on ports P2 (AD1S ... AD8) and
P1 (AD7... ADO).
Test mode "TMB" : With this second test mode, the
contents of the 80CS2 internal bus is presented on
port P1 during the PH2 clock phases.
• Using MOVC instructions: If EA = 0, and following
a reset, the 80CS2 fetches its instructions from external program memory. It is then possible to write a
small program whose purpose is to dump the internal
ROM contents by means of MOVC A, @A + DPTR
and MOVC A, @A + PC instructions.
TEST OF THE ON-CHIP PROGRAM
MEMORY
• Before protection is activated : The 80CS2F can
be tested as any normal 80CS2 (using test equipment or any other methods).
• After protection is activated : It is then no longer
possible to dump the internal ROM contents.
HOW TO PROGRAM THE PROTECTION
MECHANISM
To burn correctly the fuse a specific configuration of
inputs must be settled as below:
- RST =ALE = 1
- P2.7 = 1
Furthermore PSEN signal must be tied at + 9 V ± S %
level voltage and a pulse must be applied on P2.6 input
Port. The timing on P2.6 is shown below:
80C52F WITH PROGRAM PROTECTION FEATURES
This new version adds ROM protection features in
some strategic points of the 80CS2F in order to
eliminate the possibility of reading the ROM contents
(once the protection has been programmed) by one if
the three forementioned methods (VER and TMB test
modes, or MOVC instructions).
P2.6
SV
Nevertheless the customer must note the following:
- Once the protection has been programmed, the
80CS2F program always starts at address 0 in the internal ROM.
- The application program must be self contained in
the internal 8 K of ROM, otherwise it would be possible to trap the program counter address in the ex-
°-t-------+~--7'-=~----------..
:'SOms
Time Rise and Fall Rise::; 100 115.
• The electrical schematic shows a typical application
to deliver P2.6 signal.
6-78
80C5218OC32
T21P1.0
T2EX11.1
P1.2
Pl.3
P1.4
Pl.5
Pl.6
Pl.7
("oj
RST
P3.0/RXD
P3.1ITXD
P3.2I1NTO
P3.3I1NTl
P3.41T0
P3.51T1
P3.61WR
P3.7IRD
XTAL2
XTALl
VSS
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
It>
u
~
("oj
f3
&l
14
15
16
17
24
18
19
20
23
22
21
vee
PO.O
PO. 1
PO.2
PO.3
PO.4
PO.5
PO.6
PO.7
EA
ALE
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
:6: :5: :4: :3: :2: 1::.u::.ta:
:42! :41: :«t.
• ••• ••• •.• • •••••
............... a.... ....
PI.5
PI.6
PH
RST
P3.O
8OC32180C52
NC
P3.1
P3.2
P33
P3.4
P3.5
r·, •.••••• - ••.• P- ..... P-' .-. r- • •• ,
:18: :19: :20: :21:
OIL
:~
:23: :24:
:~
:26: :27:
:~
LCC
PI' PI3 PIC! Pn PIO NC Vee Poo POI POi! P03
44 43 42 41 40 39 38 37 36 35 34
PI5
1•
33
Po.
PI6
2
32
P05
PI7
3
31
P06
RST
4
30
P07
PJO
5
29
tA
28
NC
NC
6
P31
7
27
ALE
P32
8
26
PSEN
P33
9
25
PC!7
P3'
10
24
PC!6
P35
11
23
P25
80C32/80C52
Flat Pack
Diagrams are for reference only. Package sizes are not to scale.
Figure 4 : Configurations.
6-79
HillS
aOC52180C32
If 1's are written to PD and IDL at the same time. PD
takes precedence. The reset value of PCON is
(OXXXOOOO).
IDLE AND POWER DOWN OPERATION
Figure 5 shows the internal Idle and Power Down clock
configuration. As illustrated, Power Down operation
stops the oscillator. Idle mode operation allows the interrupt, serial port, and timer blocks to continue to function while the clock to the CPU is gated off.
These special modes are activated by software via the
Special Function Register, PCON. Its hardware address is 8?H. PCON is not bit addressable.
IDLE MODE
The instruction that sets PCON.O is the last instruction
executed before the Idle mode is activated. Once in the
Idle mode the CPU status is preserved in its entirety:
the Stack Pointer, Program Counter, Program Status
Word, Accumulator, RAM, and all other register maintain their data during Idle. Table 2 describes the status
of the external pins during Idle mode.
There are two ways to terminate the Idle mode. Activation of any enabled interrupt will cause PCON.O to be
cleared by hardware, terminating Idle mode. The interrupt is serviced, and following RETI, the next instruction
to be executed will be the one following the instruction
that wrote 1 to peON.O.
The flag bits GFO and GFl may be used to determine
whether the interrupt was received during normal execution or during the Idle mode. For example, the instruction that writes to PCON.O can also set or clear one
or both flag bits. When Idle mode is terminated by an
enabled interrupt, the service routine can examine the
status of the flag bits.
Figure 5 : Idle and Power Down Hardware.
The second way of terminating the Idle is with a
hardware reset. Since the oscillator is still running, the
hardware reset needs to be active for only 2 machine
cycles (24 oscillator periods) to complete the reset
operation.
PCON : Power Control Register
(MSB)
ISMODI
(LSB)
-
I -
I -
IGFl IGFOI PD IIDL I
Power Down Mode
Symbol Position Name and Function
SMOD
GFl
GFO
PD
IDL
PCON.? Double Baud rate bit. When set
to a 1, the baud rate is doubled
when the serial port is being
used in either modes 1, 2 or 3.
PCON.6 (Reserved)
PCON.5 (Reserved)
PCON.4 (Reserved)
PCON.3 General-purpose flag bit.
PCON.2 General-purpose flag bit.
PCON.1 Power Down bit. Setting this bit
activates power down operation.
PCON.O Idle mode bit. Setting this bit activates idle mode operation.
The instruction that sets PCON.1 is the last executed
prior to entering power down. Once in power down, the
oscillator is stopped. The contents of the onchip RAM
and the Special Function Register is saved during
power down mode. A hardware reset is the only way of
exiting the power down mode. the hardware reset initiates the Special Function Register (see Table 2). In
the Power Down mode, Vee may be lowered to minimize circuit power consumption. Care must be taken to
ensure the voltage is not reduced until the power down
mode is entered, and that the voltage is restored before
the hardware reset is applied which frees the oscillator.
Reset should not be released until the oscillator has re-
MODE
PROGRAM MEMORY
ALE
PSEN
PORTO
PORT1
PORT2
PORT3
Idle
Internal
1
1
Port Data
Port Data
Port Data
Port Data
Floating
Port Data
Address
Port Data
Idle
External
1
1
Power
Down
Internal
0
0
Port Data
Port Data
Port Data
Port Data
Power
Down
External
0
0
Floating
Port Data
Port Data
Port Data
Table 2 : Status of the external pins during Idle and Power Down modes.
6-80
8oo52l8OC32
started and stabilized.
Specifications. When the input goes below approximately 2 V, T3 turns off to save ICC current. Note,
when returning to a logical 1, T2 is the only internal pullup that is on. This will result in a slow rise time if the
user's circuit does not force the input line high.
Table 2 describes the status of the external pins while
in the power down mode. It should be noted that if the
power down mode is activated while in extemal program memory, the port data that is held in the Special
Function Register P2 is restored to Port 2. If the data is
a 1, the port pin is held high during the power down
mode by the strong pullup, T1, shown in Figure 6.
PIN DESCRIPTIONS
STOP CLOCK MODE
Vee
Due to static design, the MHS 80C32/C52 clock speed
can be reduced until 0 MHz without any data loss in
memory or registers. This mode allows step by step
utilization, and permits to reduce system power
consumption by bringing the clock frequency down to
any value. At 0 MHz, the power consumption is the
same as in the Power Down Mode.
Supply voltage during normal, Idle, and Power Down
operation.
Port 0
Port 0 is an 8-bit open drain bi-directionall/O port. Port 0
pins that have 1's written to them float, and in that state
can be used as high-impedance inputs.
80C52 1/0 PORTS
The 1/0 port drive of the 80C52 is similar to the 8052.
The 1/0 buffers for Ports 1, 2 and 3 are implemented as
shown in figure 6.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and Data
Memory. In this appllcation it uses strong internal pullups when emitting 1'so Port 0 also outputs the code
bytes during program verification in the 80C52. External
pullups are required during program verification. Port 0
can sink eight LS TIL inputs.
When the port latch contains a 0, all pFETS in figure 6
are off while the nFET is turned on. When the port latch
makes a O-to-1 transition, the nFETturns off. The strong
pFET, T1, turns on for two oscillator periods, pulling the
output high very rapidly. As the output line is drawn
high, pFET T3 turns on through the inverter to supply
the IOH source current. This inverter and T form a latch
which holds the 1 and is supported by T2.
Port 1
Port is an 8-bit bi-directional 1/0 port with internal pullups. Port 1 pins that have 1's written to them are pulled
high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 1 pins that are externally
being pulled low will source current (ilL, on the data
sheet) because of the intemal pullups.
When Port 2 is used as an address port, for access to
external program of data memory, any address bit that
contains a 1 will have his strong pullup turned on for the
entire duration of the external memory access.
Port 1 also receives the low-order address byte during
program verification. In the 80C52 , Port 1 can sink/
source three LS TIL inputs. It can drive CMOS inputs
without external pullups.
When an 110 pin on Ports 1, 2 or 3 is used as an input,
the user should be aware that the external circuit must
sink current during the logical 1-to-0 transition. The
maximum sink current is specified as ITL under the D.C.
Port 2
Port 2 is an 8-bit bi-directionall/O port with internal pullups. Port 2 pins that have 1's written to them are pulled
high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 2 pins that are externally
being pulled low will source current (ilL, on the data
sheet) because of the internal pullups. Port 2 emits the
high-order address byte during fetches from external
Program Memory and during accesses to external Data
Memory that use 16-bit addresses (MOVX@DPTR). In
this application, it uses strong internal pullups when
emitting 1'so During accesses to external Data Memory
that use 8-bit addresses (MOVX @Ri), Port 2 emits the
contents of the P2 Special Function Register.
It also receives the high-order address bits and control
signals during program verification in the 80C52. Port
2 can sink/source three LS TIL inputs. It can drive
CMOS inputs without extemal pullups.
Figure 6 : 110 Buffers in the 80C52 (Ports 1, 2, 3).
6-81
80C52/BOC32
Port 3
XTAL1
Port 3 is an 8-bit bi-directionall/O port with internal pullups. Port 3 pins that have 1's written to them are pulled
high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 3 pins that are externally
being pulled low will source current (ilL, on the data
sheet) because of the pullups. It also serves the function of various special features of the MHS 51 Family,
as listed below.
Input to the inverting amplifier that forms the oscillator.
Receives the external oscillator signal when an external
oscillator is used.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Function
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
lliTimer 1 external input)
WR (external Data Memory write strobe)
RD (external Data Memory read strobe)
Port 3 can sink/source three LS TTL inputs. It can drive
CMOS inputs without external pullups.
RST
XTAL2
Output of the inverting amplifier that forms the oscillator,
and input to the intemal clock generator. This pin should
be floated when an external oscillator is used.
OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output respectively, of an inverting amplifier which is configured for use
as an on-chip oscillator, as shown in figure 7. Either a
quartz crystal or ceramic resonator may be used.
To drive the device from an external clock source;
XTAL 1 should be driven while XTAL2 is left unconnected as shown in figure 8. There are no requirements
on the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a divideby-two flip-flop, but minimum and maximum high and
low times specified on the Data Sheet must be observed.
A high level on this for two machine cycles while the oscillator is running resets the device. An internal pulldown resistor permits Power-On reset using only a
capacitor connected to Vcc.
ALE
Address Latch Enable output for latching the low byte
of the address during accesses to external memory.
ALE is activated as though for this purpose at a constant
rate of 1/6 the oscillator frequency except during an external data memory access at which time on ALE pulse
is skipped. ALE can sink/source 8 LS TTL inputs. It can
drive CMOS inputs without an external pullup.
PSEN
Program Store Enable output is the read strobe to external Program Memory. PSEN is activated twice each
machine cycle during fetches from external Program
Memory. (However, when executing out of external
Program Memory, two activations of PSEN are skipped
during each access to external Data Memory). PSEN
is not activated during fetches from internal Program
Memory. PSEN can sink/source 8 LS TTL inputs. It can
drive CMOS inputs without an external pullup.
EA
When EA is held high, the CPU executed out of internal
Program Memory (unless the Program Counter exceeds 1 FFFH). When EA is held low, the CPU executes
only out of external Program Memory. EA must not be
floated.
Figure 7 : Crystal Oscillator.
N C - XTAl.2: 18
EXTERNAL
0S0Ll.Al0R--------IXTAL1: 19
SIGNAL
*VSS:20
Figure 8 : External Drive Configuration.
80C5218OC32
TIMER/EVENT COUNTER 2
ing sets bit TF2, the Timer 2 overflow bit, which can be
used to generate an interrupt. If EXEN2 = 1 , then Timer
2 still does the above, but with the added feature that a
1-to-0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be
captured into registers RCAP2L and RCAP2H, respectively, (RCAP2L and RCAP2H are new Special Function Register in the 80C52 ). In addition, the transition
at T2EX causes bit EXF2 in T2CON to be set, and
EXF2, like TF2, can generate an interrupt.
Timer 2 is a 16-bit timer/counter like Timers 0 and 1, it
can operate either as a timer or as an event counter.
This is selected by bit C!T2 in the Special Function
Register T2CON (Figure 1). It has three operating
modes: "capture", "autoload" and "baud rate generator", which are selected by bits in T2CON as shown in
RCLK + CP/RL2
TCLK
0
0
1
X
0
1
X
X
TR2
1
1
1
0
MODE
The capture mode is illustrated in Figure 2.
16-bit auto-reload
16-bit captu re
baud rate generator
(off)
In the auto-reload mode there are again two options,
which are selected by bit EXEN2 in T2CON.lf
EXEN2 = 0, then when Timer 2 rolls over it does not
only set TF2 but also causes the Timer 2 register to be
reloaded with the 16-bit value in registers RCAP2L and
RCAP2H, which are preset by software. If EXEN2 = 1,
then Timer 2 still does the above, but with the added
feature that a 1-to-0 transition at external input T2EX
will also trigger the 16-bit reload and set EXF2.
Table 1 : Timer 2 Operating Modes.
Table 1.
In the capture mode there are two options which are
selected by bit EXEN2 in T2CON; If EXEN2 = 0, then
Timer 2 is a 16-bit timer or counter which upon overflow-
The auto-reload mode is illustrated in Figure 3.
ICONllIOL
ICONIRCL
ElCfN2
ElCEN2
Figure 2 : Timer 2 in Capture Mode.
Figure 3 : Timer in Auto-Reload Mode.
6-83
80C5218OC32
(MSB)
I
TF2
(LSB)
EXF2
RCLK
TCLK
EXEN2
TR2
C!T2
I CP/RL2 I
The baud rate generator mode is selected by :
RCLK = 1 and/or TCLK = 1.
Symbol
TF2
T2CON.7
Position
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software.
TF2 will not be set when either RCLK = 1 OR TCLK = 1.
Name and Significance
EXF2
T2CON.6
Timer 2 external flag set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2
= 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software.
RCLK
T2CON.5
Receive clock flag. When set, causes the serial port to use Timer 2 overflow
pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow
to be used for the receive clock.
TCLK
T2CON.4
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow
pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2
T2CON.3
Timer 2 external enable flag. When set, allows capture or reload to occur as a
result of a negative transition on T2EX if Timer 2 is not being used to clock the
serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2
T2CON.2
Start/stop control for Timer 2. A logic 1 starts the timer.
C!T2
T2CON.1
Timer or counter select. (Timer 2) 0 = Internal timer (OSC/12)
1 = External event counter (falling edge triggered).
CP/RL2
T2CON.O
Capture/Reload flag. When set, captures will occur on negative transitions at
T2EX if EXEN 2 = 1. When cleared, auto reloads will occur either with Timer 2
T2CON : Timer/Counter 2 Control Register.
8OC5218OC32
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias:
e = commercial ................................... ooe to 70°C
I = industrial .................................. - 40°C to +85°e
Storage Temperature ..................... - 65°C to + 150°C
Voltage on Vcc to Vss ........................ - 0.5 V to + 7 V
Voltage on Any Pin to Vss ........ - 0.5 V to Vcc + 0.5 V
Power Dissipation .............................................. 1 W"
• NOTICE
Stresses at or above those listed under" Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.
•• This value is based on the maximum allowable die temperature and the thermal resistance of the package.
DC CHARACTERISTICS
TA = - 40°C to 85°C; VSS = 0 V ; vee = 5 V ± 10 % ; F = 0 to 16 MHz
SYMBOL
PARAMETER
VIL
Input Low Voltage
MIN
MAX
-0.5
0.2 vee
-0.1
UNIT
V
TEST CONDITIONS
VIH
Input High Voltage
(Except XTAL and RST)
0.2 vee vee + 0.5
+ 0.9
V
VIH1
Input High Voltage
(RST and XTAL1)
0.7 vee vee + 0.5
V
VOL
Output Low Voltage (Port 1, 2, 3)
0.45
V
10L = 1.6 rnA (note 3)
VOL1
Output Low Voltage Port 0, ALE, PSEN
0.45
V
VOH
Output High Voltage Ports 1, 2, 3
= 3.2 rnA (note 3)
= -10 J.lA
10H = - 25 J.lA
10H = - 60 J.lA
vee = 5V± 10 %
10H = - 80 J.lA
10H = - 300 J.lA
10H = - 800 J.lA
VCC = 5V±10 %
VOH1
ilL
Output High Voltage
(Port 0 in External Bus Mode, ALE,
PSEN)
0.9 vee
V
0.75 vee
V
2.4
V
0.9 VCC
V
0.75 VCC
V
2.4
V
Logical 0 Input Current Ports 1, 2, 3
III
Input Leakage Current (Port 0, EA)
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2, 3)
IPD
Power Supply Current
(Power Down Mode)
RRST
RST Pulldown Resistor
CIO
Capacitance of I/O Buffer
ICC
Power Supply Current
Active Mode 12 MHz
16 MHz
20 MHz
Idle Mode
12 MHz
16 MHz
20 MHz
Note1:
See figures 9 through 12 for ICC test conditions.
Yin = 0.45 V
J.lA
J.lA
0.45 < Yin < VCC
-650
50
J.lA
VCC = 2.0 V to 6 V
(note 2)
150
kQ
10
pF
22
rnA
rnA
rnA
rnA
rnA
rnA
1-60
±10
50
10H
J.lA
C I-50
I
10L
27
32
7
9
11
Yin
= 2.0 V
fc = 1 MHz, TA
(notes 1,2)
= 25°C
8OC52/8OC32
RST
30
(NC)
CLOCK
25
-«
E
XTAL2
XTALI
yss
SIGNAL
Figure 10: ICC Test Condition, Idle Mode. All other
pins are disconnected.
vee
20
vee
15
RST
()
()
1-1
=-
10
(NC)
MAX IDLE
MODE
5
XTAL2
XTALI
yss
Figure 11 : ICC Test Condition, Active Mode. All
other pins are disconnected.
oL---~--~--~--~--~
4 MHz 8 MHz 12 MHz 16 MHz 20 MHz
FREQRxmL1
Figure 9 : ICC vs. Frequency. Valid only within
frequency specifications of the device
under test.
Figure 12: ICC Test Condition, Power Down Mode.
All other pins are disconnected.
Figure 13 : Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.
6-86
aoC5218OC32
Note 2 : ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns,
VIL=VSS+.5V, VIH=VCC-.5V ;XTAL2N.C. ;EA=
RST = Port 0 = VCC. ICC would be slightly higher if a
crystal oscillator used.
Note 3 : Capacitance loading on Ports 0 and 2 may
cause spurious noise pulses to be superimposed on the
VOLS of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and
Port 2 pins when these pins make 1 to 0 transitions
during bus operations. In the worst cases (capacitive
loading 100 pF), the noise pulse on the ALE line may
exceed 0.45 V may exceed 0,45 V with maxi VOL peak
0.6 V. A Schmitt Trigger use is not necessary.
Idle ICC is measured with all output pins disconnected;
XTAL1 driven with TCLCH, TCHCL= 5 ns, VIL= VSS+
.5 V, VIH = VCC -.5 V; XTAL2 N.C; Port 0 = VCC;
EA = RST = VSS.
Power Down ICC is measured with all output pins disconnected; EA = PORT 0 = VCC ; XTAL2 N.C. ; RST
=VSS.
EXTERNAL CLOCK DRIVE CHARACTERISTICS (XTAL 1)
SYMBOL
VARIABLE CLOCK
FREQ = 0 to 16 MHz
PARAMETER
MIN
UNIT
MAX
1fTCLCL
Oscillator Frequency
50
ns
TCHCX
High Time
20
ns
TCLCX
Low Time
20
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
MAX
UNIT
ns
A.C. CHARACTERISTICS
TA=-40"Cto 85"C ;VSS = 0 V; VCC = 5 V± 10 %
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
SYMBOL
PARAMETER
MIN
TLHLL
ALE Pulse Width
2TCLCL-40
TAVLL
Address Valid to ALE
TCLCL-55
ns
TLLAX
Address Hold After ALE
TCLCL-35
ns
TLLlV
ALE to Valid Instr in
TLLPL
ALE to PSEN
TCLCL-40
TPLPH
PSEN Pulse Width
3TCLCL-45
TPLIV
PSEN to Valid Instr in
TPXIX
Input Instr Hold After PSEN
TPXIZ
Input Instr Float After PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid Instr in
TPLAZ
PSEN Low to Address Float
ns
4TCLCL-100
3TCLCL-105
ns
TCLCL-25
ns
ns
ns
5TCLCL-105
ns
10
ns
0
TCLCL-8
6-87
ns
ns
ns
8OC5218OC32
EXTERNAL DATA MEMORY CHARACTERISTICS
SYMBOL
PARAMETER
MIN
MAX
UNIT
TRLRH
RD Pulse Width
6TCLCL-100
ns
TWLWH
WR Pulse Width
6TCLCL-100
ns
TLLAX
Data Address Hold After ALE
TRLDV
RD to Valid Data in
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
2TCLCL-70
ns
TLLDV
ALE to Valid Data in
8TCLCL-150
ns
TAVDV
Address to Valid Data in
9TCLCL-165
ns
TLLWL
ALE to WR or RD
3TCLCL+50
ns
TAVWL
Address to WR or RD
TQVWX
Data Valid to WR Transition
TQVWH
Data Setup to WR High
TWHQX
Data Hold After WR
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
TCLCL-50
ns
5TCLCL-165
0
3TCLCL-50
ns
4TCLCL-130
ns
TCLCL-60
ns
7TCLCL-150
ns
TCLCL-50
TCLCL-40
6-88
ns
ns
0
ns
TCLCL+40
ns
8OC5218OC32
ABSOLUTE MAXIMUM RATINGS'
• NOTICE:
Ambient Temperature Under Bias:
A = Automotive ........................... - 40"C to +125"C
M = Military ................................ - 55"C to + 125"C
Storage Temperature ..................... - 65"C to + 150"C
Voltage on Any Pin to Vss ........ - 0.5 V to Vee + 0.5 V
Voltage on Vee to Vss ........................ - 0.5 V to 6.5 V
Power Dissipation ................................................. 1 W
Stresses above those listed under" Absolute Maximum
Ratings .. may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC CHARACTERISTICS
TA = - 55"C to + 125"C ; VSS = 0 V; VCC = 5 V ± 10% ; F = 0 to 12 MHz
SYMBOL
PARAMETER
MIN
MAX
UNIT
-0.5
0.2 VCC
-0.1
V
TEST CONDITIONS
VIL
Input Low Voltage
VIH
Input High Voltage (Except XTAL 1, RST)
0.2 VCC VCC + 0.5
+ 0.9
V
VIH1
Input High Voltage (XTAL 1, RST)
0.7 VCC VCC + 0.5
V
VOL
Output Low Voltage (Ports 1, 2, 3)
0.45
V
IOL = 1.6 mA (note 2)
VOL1
Output Low Voltage (Port 0, ALE, PSEN)
0.45
V
IOL = 3.2 mA (note 2)
VOH
Output High Voltage (Ports 1, 2, 3)
2.4
V
IOH =-60!JA
VCC = 5 V± 10 %
0.75 VCC
V
IOH = -25!JA
0.9 VCC
V
IOH = -10!JA
2.4
V
IOH = - 800 !JA
VCC = 5V±10 %
0.75 VCC
V
IOH = - 300 !JA
0.9 VCC
V
VOH1
Output High Voltage
(Port 0 in External Bus Mode, ALE,
PSEN)
IOH = - 80!JA
-75
!JA
-750
!JA
Vin = 2 V
150
!JA
kQ
0.45 < Vin < VCC
Pin Capacitance
10
pF
Test Freq = 1 MHz,
TA = 25°C
IPD
Power Down Current
75
!JA
VCC = 2 to 5.5 V
(note 1)
ICC
Power supply current
Active mode 12 MHz
Idle mode 12 MHz
25
10
rnA
rnA
VCC = 5.5 V
VCC = 5.5 V
ilL
Logical 0 Input Current Ports 1, 2, 3
ITL
Logical 1 to 0 Transition Current
III
Input Leakage Current (Port 0, EA)
RRST
Reset Pulldown Resistor
CIO
±10
50
Note1: ICC is measured with all output pins discon-
Vin = 0.45 V
Note 2 : Capacitance loading on Ports 0 and 2 may
cause spurious noise pulses to be superimposed on the
VOLS of ALE and Ports 1 and 3. The noise is due to extemal bus capacitance discharging into the Port 0 and
Port 2 pins when these pins make 1 to 0 transitions
during bus operations. In the worst cases (capacitive
loading 100 pF), the noise pulse on the ALE line may
exceed 0.45 V may exceed 0,45 V with maxi VOL peak
0.6 V. A Schmitt Trigger use is not necessary.
nected ; XTAL 1 driven with TCLCH, TCHCL = 5 ns,
VIL=VSS+.5 V, VIH =VCC-.5 V ;XTAL2 N.C. ; EA=
RST = Port 0 = VCC. ICC would be slightly higher if a
crystal oscillator used.
Idle ICC is measured with all output pins disconnected;
XTAL 1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS +
.5 V, VIH = VCC - .5 V ; XTAL2 N.C ; Port 0 = VCC ;
EA = RST = VSS.
Power Down ICC is measured with all output pins disconnected; EA = PORT 0 = VCC; XTAL2 N.C. ; RST
=VSS.
6-89
8OC521SOC32
AC PARAMETERS:
TA = - 55'C to + 125'C ; VSS = a v ; VCC = 5 V ± 10 %
(Load Capacitance for Port 0, ALE, and PSEN = 100 pf ; Load Capacitance for All Other Outputs = 80 pf).
FREO = 12 MHz (MAX)
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
SYMBOL
PARAMETER
MIN
MAX
UNIT
TLHLL
ALE Pulse Width
2TCLCL-55
ns
TAVLL
Address Valid to ALE
TCLCL-70
ns
TLLAX
Address Hold After ALE
TCLCL-35
TLLlV
ALE to Valid Instr in
ns
4TCLCL-115
TLLPL
ALE to PSEN
TCLCL-55
TPLPH
PSEN Pulse Width
3TCLCL-60
TPLIV
PSEN to Valid Instr in
TPXIX
Input Instr Hold After PSEN
TPXIZ
Input Instr Float After PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid Instr in
TPLAZ
PSEN Low to Address Float
ns
ns
ns
3TCLCL-120
a
ns
ns
TCLCL-40
TCLCL-8
ns
ns
5TCLCL-120
ns
25
ns
MAX
UNIT
EXTERNAL DATA MEMORY CHARACTERISTICS
SYMBOL
PARAMETER
MIN
TRLRH
RD Pulse Width
6TCLCL-100
TWLWH
WR Pulse Width
6TCLCL-100
ns
TCLCL-50
ns
TLLAX
Data Address Hold After ALE
TRLDV
RD to Valid Data in
TRHDX
Data Hold After RD
ns
5TCLCL-185
a
ns
ns
TRHDZ
Data Float After RD
2TCLCL-85
ns
TLLDV
ALE to Valid in
8TCLCL-170
ns
TAVDV
Address to Valid Data in
9TCLCL-185
ns
TLLWL
ALE to WR or RD
3TCLCL+65
ns
TAVWL
Address to WR or RD
TOVWX
Data Valid to WR Transition
TOVWH
Data Setup to WR High
TWHOX
Data Hold After WR
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
3TCLCL-65
4TCLCL-145
ns
TCLCL-75
ns
7TCLCL-150
ns
TCLCL-65
ns
TCLCL-65
6-90
0
ns
TCLCL+65
ns
80C5218OC32
AC TIMING DIAGRAMS
EXTERNAL PROGRAM MEMORY READ CYCLE
r----------------------12~----------------------~
INSTR IN
ADDRESS
ADDRESS A8-A15
PORI" 2 OR SFR-P2
ADDRESS A8-A15
EXTERNAL DATA MEMORY READ CYCLE
TWHLH
PSEIiI
REI
FORTO
PORf2
EXTERNAL DATA MEMORY WRITE CYCLE
r
TWHLH
"
_lUWl-:1
PSEIiI
WI!
__TAVWl
1U.AX
>-<
FORTO
AIJIlRESS
FORT2
ORSFR-P2
TWI.WH
N.
/
-;;:::r-,::;,=-TDYWX
Nr/fJ
~OUT
)
AIJIlRESS All-A15 OR SFR-P2
I
J
;
AC TESTING INPUT/OUTPUT, FLOAT WAVEFORMS
=X
flOAT
INPIJf10UlPUT
V
VCC-Il.5
~v
02'kc-0.9
\r-
~02
__
'kc~-~~~I_________~
~-------flOAT------~
VOH-o,W
\IOI..+o,w
VIDAD+o,lV
AC inputs during testing are driven at Vcc - 0.5 for a logic n 1 nand 0.45 V for a logic non. Timing measurements are
made at VIH min for a logic n 1 nand VIL max for a logic non. For timing purposes a port pin is no longer floating
when a 100 mV change from load voltage occurs and begins to float when a 100 mV change
6-91
8OC5218OC32
SERIAL PORT TIMING· SHIFT REGISTER MODE
A.C. CHARACTERISTICS
TA = - 40·C to 85·C ; VSS = 0 V ; VCC
SYMBOL
= 5 V ± 10 %
PARAMETER
TXLXL
TQVXH
TXHQX
TXHDX
TXHDV
MIN
Serial Port Clock lime
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
MAX
UNIT
12TCLCL
10TCLCL-133
2TCLCL-117
0
!IS
ns
ns
ns
ns
10TLCL-133
SHIFT REGISTER TIMING WAVEFORMS
I
2
0
a
4
1----11-
ClUIPUT_
\0
X~--""'x
2
•
I
X 3
x.
7
X...__,.,X.
-h~~ma
•
X 71
,
5ET1I
,
IETIi
Example:
TAVLL =Time for Address Valid to ALE low.
TLLPL =lime for ALE low to PSEN low.
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a" T " (stands for time) The other characters, depending on their positions, stand for the name
of a signal or the logical status of that signal. The following is a list of all the characters and what they stand
for.
A: Address.
C: Clock.
D : Input data.
H : Logic level HIGH.
I : Instruction (program memory contents).
L : Logic level LOW, or ALE.
P :PSEN.
Q : Output data.
R : READ signal.
T: lime.
V:Valid.
W : WRITE signal.
X : No longer a valid logic level.
Z: Float.
6·92
aOC5218OC32
CLOCK WAVEFORMS
INIERtW.
~
I ~I~ I ~I~ I ~I~ I ~I~ I ~I~ I ~I~ I ~I~ I ~I~ I
SDVE
4
STATE 6
SDVE 5
SDVE 1
SDVE 2
SW'E 3
SDVE 4
SDVE 5
X1l\L2
'
~
____I
I
11ESE SIGNAlS N£ HOI'
ACI'MIJB) DURING TtE
EXECUTION OF" MOYX INSmucrJON
I
t
I
~(EXTl
REAPcyg.E
~
--------------------~
OOH IS EMIT1ED
t
DURING THIS PEAOD
----..:--DPL-a:-Rl-""I,.
I•
INDICA1ES DPH OR ~ SFRlO PCH11WIIITIONS
"'-_________....1 PD..OUT(EVEN FPROGRAM
-
I
JIIDI PORI' SAC
JllDlDESTN
- MEMORY IS MERW.)
OlD DIIIA lEW DIIIA
J=.:I
•'POPINS~"-~
..........-
JTI. . . ----_____________---:c=1
Pl.P2 P3 PlNSSAMRm
CA~PlNSP11~.P!-!.!.. ....
~
~~--------~~
, r-
- -P2.P3)
---'"
IlDiDESTPORI'~.
(lCUJDES1NTG.1NT1.To.T1)
SS!W..PORTSHFTa.ooc
_
"""'"""'"
RlCD SNtFLB)
RlCD SAMPLED
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins.
however. ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (TA = 25°C fully loaded) RD
and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are
incorporated in the AC specifications.
6-93
80C5218OC32
ARITHMETIC OPERATIONS
MNEMONIC
ADD
A,Rn
ADD
A, direct
ADD
A,@Ri
ADD
A, #data
ADDC
A,Rn
ADDC
A, direct
ADDC
A,@Ri
ADDC
A, #data
A,Rn
SUBB
A, direct
SUBB
A,@Ri
SUBB
SUBB
A, #data
INC
A
INC
Rn
INC
direct
INC
@Ri
INC
DPTR
DEC
A
DEC
Rn
DEC
direct
DEC
@Ri
MUL
AB
DIV
AB
DA
A
LOGICAL OPERATIONS
MNEMONIC
A, Rn
ANL
ANL
A, direct
A,@Ri
ANL
ANL
A, #data
ANL
direct, A
ANL
direct, #data
ORL
A,Rn
ORL
A, direct
A,@Ri
ORL
ORL
A, #data
ORL
direct, A
ORL
direct, #data
XRL
A,Rn
XRL
A, direct
A,@Ri
XRL
XRL
A, #data
XRL
direct, A
XRL
direct, #data
CLR
A
CPL
A
RL
A
RLC
A
RR
A
RRC
A
SWAP
A
DESCRIPTION
Add register to Accumulator
Add direct byte to Accumulator
Add indirect RAM to Accumulator
Add immediate data to Accumulator
Add register to Accumulator with Carry
Add direct byte to A with Carry flag
Add indirect RAM to A with Carry flag
Add immediate data to A with Carry flag
Subtract register from A with Borrow
Subtract direct byte from A with Borrow
Subtract indirect RAM from A with Borrow
Subtract immed. data from A with Borrow
Increment Accumulator
Increment register
Increment direct byte
Incriment indirect RAM
Incriment Data Pointer
Decrement Accumulator
Decrement register
Decrement direct byte
Decrement indirect RAM
Multiply A & B
Divide A by B
Decimal Adjust Accumulator
BYTE
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
1
2
1
1
1
1
CYC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
4
4
1
DESTINATION
AND register to Accumulator
AND direct byte to Accumulator
AND indirect RAM to Accumulator
AND immediate data to Accumulator
AND Accumulator to direct byte
AND immediate data to direct byte
OR register to Accumulator
OR direct byte to Accumulator
OR indirect RAM to Accumulator
OR immediate data to Accumulator
OR Accumulator to direct byte
OR immediate data to direct byte
Exclusive-OR register to Accumulator
Exclusive-OR direct byte to Accumulator
Exclusive-OR indirect RAM to A
Exclusive-OR immediate data to A
Exclusive-OR Accumulator to direct byte
Exclusive-OR immediate data to direct
Clear Accumulator
Complement Accumulator
Rotate Accumulator Left
Rotate A Left through the Carry flag
Rotate Accumulator Right
Rotate A Right through Carry flag
Swap nibbles within the Accumulator
BYTE
1
2
1
2
2
CYC
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
Table 1 : MHS - 51 Instruction Set Description.
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
80C5218OC32
DATA TRANSFER
MNEMONIC
DESCRIPTION
MOV
A, Rn
Move register to Accumulator
MOV
A, direct
Move direct byte to Accumulator
MOV
A,@Ri
Move indirect RAM to Accumulator
MOV
A, #data
Move immediate data to Accumulator
MOV
Rn, A
Move Accumulator to register
MOV
Rn, direct
Move direct byte to register
MOV
Rn, #data
Move immediate data to register
MOV
direct, A
Move Accumulator to direct byte
MOV
direct, Rn
Move register to direct byte
MOV
direct, direct
Move direct byte to direct
MOV
direct, @Ri
Move indirect RAM to direct byte
MOV
direct, #data
Move immediate data to direct byte
MOV
@Ri,A
Move Accumulator to indirect RAM
MOV
@Ri, direct
Move direct byte to indirect RAM
MOV
@Ri, #data
Move immediate data to indirect RAM
MOV
DPTR, #data 16
Load Data Pointer with a 16-bit constant
MOVC
A,@A+DPTR
Move Code byte relative to DPTR to A
MOVC
A,@A+PC
Move Code byte relative to PC to A
A,@Ri
MOVX
Move External RAM (a-bit addr) to A
MOVX
A,@DPTR
Move External RAM (16-bit addr) to A
@Ri,A
MOVX
Move A to External RAM (a-bit addr)
@DPTR,A
MOVX
Move A to External RAM (16-bit addr)
PUSH
direct
Push direct byte onto stack
POP
direct
Pop direct byte from stack
XCH
A, Rn
Exchange register with Accumulator
XCH
A, direct
Exchange direct byte with Accumulator
A,@Ri
XCH
Exchange indirect RAM with A
XCHD
A,@Ri
Exchange low-order nibble ind RAM with A
BOOLEAN VARIABLE MANIPULATION
MNEMONIC
DESCRIPTION
CLR
C
Clear Carry flag
CLR
bit
Clear direct bit
SETS
Set Carry flag
C
SETS
bit
Set di rect Bit
CPL
C
Complement Carry flag
CPL
bit
Complement direct bit
ANL
C,bit
AND direct bit to Carry flag
ANL
C,/bit
AND complement of direct bit to Carry
ORL
C,bit
OR direct bit to Carry flag
ORL
C,/bit
OR complement of direct bit to Carry
MOV
C,bit
Move direct bit to Carry flag
MOV
bit, C
Move Carry flag to direct bit
PROGRAM AND MACHINE CONTROL
MNEMONIC
DESCRIPTION
ACALL
addr 11
Absolute Subroutine Call
LCALL
addr 16
Long Subroutine Call
RET
Return from subroutine
RETI
Return from interrupt
AJMP
addr 11
Absolute Jump
LJMP
addr 16
Long Jump
SJMP
rei
Short Jump (relative addr)
JMP
@A+DPTR
Jump indirect relative to the DPTR
rei
JZ
Jump if Accumulator is Zero
rei
JNZ
Jump if Accumulator is Not Zero
rei
Jump if Carry flag is set
JC
rei
Jump if No Carry flag
JNC
Table 1. (Cont.)
6-95
BYTE
1
2
1
2
1
2
2
2
2
3
2
3
CYC
1
1
1
1
1
2
1
1
2
2
2
2
1
1
2
2
3
2
1
1
1
1
1
1
2
2
1
2
1
1
BYTE
1
2
1
2
1
2
2
2
2
2
2
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
CYC
1
1
1
1
1
1
2
2
2
2
1
2
BYTE
CYC
2
3
2
2
2
2
2
2
2
2
2
2
2
2
1
1
2
3
2
1
2
2
2
2
8OC52J8OC32
PROGRAM AND MACHINE CONTROL (cont.)
MNEMONIC
DESCRIPTION
JB
bit, rei
Jump if direct Bit set
Jump if direct Bit Not set
JNB
bit, rei
JBC
CJNE
CJNE
CJNE
CJNE
DJNZ
DJNZ
NOP
bit, rei
A, direct, rei
A, #data, rei
Rn, #data, rei
@Ri, #data. rei
Rn, rei
direct. rei
Jump if direct Bit is set & Clear bit
Compare direct to A & Jump if Not Equal
Compo immed. to A & Jump if Not Equal
Compo immed. to reg & Jump if Not Equal
Compo immed. to indo & Jump if Not Equal
Decrement register & Jump if Not Zero
Decrement direct & Jump if Not Zero
No operation
BYTE
3
3
3
3
3
3
3
2
3
CYC
2
2
2
2
2
2
2
2
2
1
1
Table 1. (Cont.)
Notes on data addressing modes:
Rn
direct
@Ri
#data
#data 16
bit
- Working register RD-R7
- 128 internal RAM locations, any I/O port, control or status register
-Indirect internal RAM location addressed by register RD or R1
- 8-bit constant included in instruction
- 16-bit constant included as bytes 2 & 3 of instruction
-128 software flags, any 1/0 pin, control or status bit
Notes on program addressing modes:
- Destination address for LCALL & LJMP may be anywhere within the 64-k program memory
address space
Addr 11
- Destination address for ACALL & AJMP will be within the same 2-k page of program
memory as the first byte of the following instruction
rei
- SJMP and all conditional jumps include an 8-bit offset byte. Range is + 127 - 128 bytes
relative to the first byte of the following instruction.
All mnemonics copyrighted@ Intel Corporation 1979
addr 16
6-96
8OC5218OC32
HEX NUMB.
CODE OF
MNEM.
BYTES
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
20
2E
2F
30
31
32
1
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
1
1
2
2
1
1
1
1
1
1
1
1
1
1
3
2
1
NOP
AJMP
LJMP
RR
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
JBC
ACALL
LCALL
RRC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
JB
AJMP
RET
RL
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
JNB
ACALL
RETI
HEX NUMB.
CODE OF
MNEM.
BYTES
OPERANDS
33
34
code addr
code addr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr, code addr
code addr
code addr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr, code addr
code addr
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
50
51
52
53
54
55
56
A
A, data
A, data addr
A,@RO
A,@R1
A,RO
A, R1
A, R2
A,R3
A,R4
A, R5
A, R6
A, R7
bit addr, code addr
code addr
57
58
59
5A
5B
5C
50
5E
5F
60
61
62
63
64
65
1
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
RLC
AD DC
AD DC
AD DC
ADDC
ADDC
AD DC
AD DC
AD DC
AD DC
AD DC
AD DC
AD DC
JC
AJMP
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
JNC
ACALL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
JZ
AJMP
XRL
XRL
XRL
XRL
Table 2 : Instruction Opcodes in Hexadecimal Order.
6-97
OPERANDS
A
A, #data
A, data addr
A,@RO
A,@R1
A,RO
A, R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
data addr, A
data addr, #data
A, #data
A, data addr
A,@RO
A,@R1
A,RO
A, R1
A, R2
A, R3
A, R4
A, R5
A,R6
A,R7
code addr
code addr
data addr, A
data addr, #data
A, #data
A, data addr
A,@RO
A,@R1
A,RO
A, R1
A,R2
A,R3
A,R4
A,R5
A,R6
A, R7
code addr
code addr
data addr A
data addr, #data
A, #data
A, data addr
8OC52/8OC32
HEX NUMB.
CODE OF
MNEM.
BYTES
66
67
68
69
6A
6B
6C
60
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
70
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
1
1
1
1
1
1
1
1
1
1
2
2
2
1
2
3
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
3
2
2
2
2
2
2
2
2
2
2
3
2
2
1
2
2
1
1
1
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
JNZ
ACALL
ORL
JMP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
SJMP
AJMP
ANL
MOVC
OIV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ACALL
MOV
MOVC
SUBB
SUBB
SUBB
SUBB
SUBB
HEX NUMB.
MNEM.
CODE OF
BYTES
OPERANDS
A,@RO
A,@R1
A, RO
A, R1
A, R2
A, R3
A, R4
A, R5
A, R6
A, R7
code addr
code addr
C, bit addr
@A+OPTR
A, #data
data addr, #data
@RO, #data
@R1, #data
RO, #data
R1, #data
R2, #data
R3, #data
R4, #data
R5, #data
R6, #data
R7, #data
code addr
code addr
C, bit addr
A,@A+PC
AB
data addr, data addr
data addr, @RO
data addr, @R1
data addr, RO
data addr, R1
data addr, R2
data addr, R3
data addr, R4
data addr, R5
data addr, R6
data addr, R7
OPTR, #data
code addr
bit addr, C
A,@A+OPTR
A, #data
A, data addr
A,@RO
A,@R1
A,RO
A4
1
1
1
1
1
1
1
2
2
2
1
1
A5
A6
A7
A8
A9
AA
AB
AC
AO
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BO
BE
BF
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
2
2
2
2
2
2
2
2
2
2
2
2
2
1
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
1
1
2
1
1
1
1
1
1
99
9A
9B
9C
90
9E
9F
AD
A1
A2
A3
Table 2. (Cont.)
6-98
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
ORL
AJMP
MOV
INC
MUL
reserved
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ANL
ACALL
CPL
CPL
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
PUSH
AJMP
CLR
CLR
SWAP
XCH
XCH
XCH
XCH
XCH
XCH
XCH
OPERANDS
A,
A,
A,
A,
R1
R2
R3
R4
A, R5
A, R6
A, R7
C, bit addr
code addr
C, bit addr
OPTR
AB
@RO, data addr
@R1, data addr
RO, data addr
R1, data addr
R2, data addr
R3, data addr
R4, data addr
R5, data addr
R6, data addr
R7, data addr
C, bit addr
code addr
Bit addr
C
A, #data, code addr
A, data addr, code addr
@RO, #data, code addr
@R1, #data, code addr
RO, #data, code addr
R1, #data, code addr
R2, #data, code addr
R3, #data, code addr
R4, #data, code addr
R5, #data, code addr
R6, #data, code addr
R7, #data, code addr
data addr
code addr
bit addr
C
A
A, data addr
A,@RO
A,@R1
A,RO
A, R1
A,R2
A,R3
80C52/8OC32
HEX NUMB.
CODE OF
MNEM.
BYTES
CC
CO
CE
CF
DO
01
02
03
04
05
06
07
08
09
DA
DB
DC
DO
DE
OF
EO
E1
E2
E3
E4
E5
1
1
1
1
2
2
2
1
1
3
1
1
2
2
2
2
2
2
2
2
1
2
1
1
1
2
XCH
XCH
XCH
XCH
POP
ACALL
SETB
SETB
DA
OJNZ
XCHO
XCHO
OJNZ
DJNZ
OJNZ
OJNZ
OJNZ
OJNZ
OJNZ
OJNZ
MOVX
AJMP
MOVX
MOVX
CLR
MOV
HEX NUMB.
CODE OF
MNEM.
BYTES
OPERANDS
A, R4
A, R5
A, R6
A, R7
data addr
code addr
bit addr
C
A
data addr, code addr
A,@RO
A,@R1
RO, code addr
R1, code addr
R2, code addr
R3, code addr
R4, code addr
R5, code addr
R6, code addr
R7, code addr
A,@OPTR
code addr
A,@RO
A,@R1
A
A, data addr
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FO
FE
FF
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVX
ACALL
MOVX
MOVX
CPL
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
OPERANDS
A,@RO
A,@R1
A, RO
A, R1
A,R2
A,R3
A,R4
A, R5
A, R6
A,R7
@OPTR,A
code addr
@RO,A
@R1,A
A
data addr, A
@RO,A
@R1,A
RO,A
R1, A
R2,A
R3,A
R4,A
R5, A
R6,A
R7,A
Table 2. (Cont.)
F
R
P
S
A
M
I
D
J
T
Temperature Range
blank: Commercial
I : Industrial
M: Military
A : Automotive
Package Type
P: Plastic
S: PLCC
0: Cerdip
R: LCC
J : J leaded LCC
F: Flat Pack
S
-L
80C32
80C52
80C52F
-1
/B
xxx
T
:R
T
Part Number
80C52 Rom 8 K x 8
80C32 External Rom
80C52F : Secret Rom
Version
/B : Miltary Program
- 1 : 16 MHz Version
- L : Low Power Supply
S : 20 MHz Version
Customer Rom Code
(80C52 only)
6-99
Tape and Reel
-PR-E-U-M-'N-A-RY----
~'1i
rAtS
---S-ep-te-m-be-r-1g-a-g
83C154/83C154D
DATA SHEET
CMOS SINGLE-CHIP
8 BIT MICROCONTROLLER
• 83C154 - CMOS SINGLE CHIP 8 BIT MICROCONTROLLER with factory mask programmable
ROM
• 83Cl54D - 83C154 with DOUBLE ROM (under
development)
• 80Cl54: ROMLESS version of 83C154
• 8OC154/83Cl54: 0 to 12 MHz
• 8OC154-1/83Cl54-1: 0 to 16 MHz
• 80C154-U83C154-L: Vee = 2.7 V to 5.5 V
(0 to 6 MHz)
• 83C154F: SECRET ROM VERSION
FEATURES
• 16 K x 8 BIT INTERNAL ROM (32 K x 8 for
83Cl54D)
• 256 x BIT RAM
• 32 PROGRAMMABLE I/O LINES (PROGRAMMABLE IMPEDANCE)
• THREE 16-BIT TIMER/COUNTERS (INCLUDING
WATCH DOG AND 32 BIT TIMER)
• 64 K PROGRAM MEMORY SPACE
• FULLYSTATICDESIGN
•
•
•
•
•
•
•
•
POWER CONTROL MODES
INTERRUPT PRIORITY CONTROL
OT016MHz
BOOLEAN PROCESSOR
6 INTERRUPT SOURCES
PROGRAMMABLE SERIAL PORT
64 K DATA MEMORY SPACE
TEMPERATURE RANGE: Commercial,
Industrial, Automotive and Military
DESCRIPTION
r---------------!-1-tW-l:t
s.:
~tH;I:tH·--------------------------j
.
.r.
,
,,
,
:
!~;1
IOU
t~~
-------
:,
,,
,
:
:
-------------.1
The 83C154/83C154D retains all the
features of the MHS 80C52 with extended ROM capacity (16 K bytes or
32 K bytes), 256 bytes of RAM, 32 I/O
lines, a 6-source 2-level interrupts, a full
duplex serial port, an on-chip oscillator
and clock circuits, three 16 bit timers
with extra features : 32 bit timer and
watch dog functions. Timer 0 and 1 can
be configured by program to implement
a 32 bit timer. The watch dog function
can be activated either with timer 0, or
timer 1 or both together (32 bit timer).
In addition, the 83C154/83C154D has
two software selectable modes of
reduced activity for further reduction of
power consumption. In the Idle Mode,
the CPU is frozen while the RAM is
saved, and the timers, the serial port,
and the interrupt system continue to
function. In the Power Down Mode, the
RAM is saved and the timers, serial port
and interrupts continue to function when
driven by external clocks. In addition as
for the MHS 80C51 IC52, the stop clock
mode is also available.
Figure 1 : Block Diagram.
6-101
MATRA MHS
--__________________________
83C154~3C154D
____________________________
nal ROM contents by means of a patch using MOVC
instructions.
MHS provides a new member in the 83C154/154D
Family named "83C154F/C154DF" which permits full
protection of the internal ROM contents.
Thus, if an extra EPROM is necessary, it is advised to
ensure that it will contain only constants or tables.
With a non protected 83C154/C154D, it is very easy to
read out the contents of the internal 16 K/32 K bytes of
ROM.
TEST OF THE ONE CHIP PROGRAM
MEMORY
• Before protection is activated: The 83C154FI
C154DF can be tested as any normal
83C154/C154D (using test equipment or any other
methods).
• After protection is activated : It is then no longer
possible to dump the internal ROM contents.
Three methods exist, two of them are special test
modes and the last one is by means of MOVC instructions.
• Test mode "VER" : Using this special test mode, the
intemal ROM contents are output on port PO ; the address being applied on ports P2 (AD15 ... AD8) and
P1 (AD7 ... ADO).
• Test mode "TMB" : With this second test mode, the
contents of the 83C154/C154D internal bus is
presented on port P1 during the PH2 clock phases.
• Using MOVC instructions: If EA = 0, and following
a reset, the 83C154/C154D fetches its instructions
from external program memory. It is then possible to
write a small program whose purpose is to dump the
intemal ROM contents by means of MOVC A, @A +
DPTR and MOVC A, @A + PC instructions.
HOW TO PROGRAM THE PROTECTION
MECHANISM
• To burn correctly the fuse a specific configuration of
inputs must be settled as below:
- RST = ALE = 1
- P2.7 = 1
Furthermore PSEN signal must be tied at + 9 V ± 5 %
level voltage and a pulse must be applied on P2.6 input
Port. The timing on P2.6 is shown below:
83C154F/C154DF WITH PROGRAM PROTECTION FEATURES
This new version adds ROM protection features in
some strategic points olthe 83C154F/C154DF in order
to eliminate the possibility of reading the ROM contents
(once the protection has been programmed) by one if
the three forementioned methods (VER and TMB test
modes, or MOVC instructions).
P2.6
5V
Nevertheless the customer must note the following:
- Once the protection has been programmed, the
83C154F/C154DF program always starts at address
o in the intemal ROM.
- The application program must be self contained in
the internal 16 K/32 K of ROM, otherwise it would be
possible to trap the program counter address in the
external PROM/EPROM and then to dump the inter-
O-+______~--~~I------------~~
~50ms
Time Rise and Fall Rise $ 100 Ils.
The electrical schematic shows a typical application
to deliver P2.6 signal.
6-102
------------------------____ 83C154~3C154D ____________________________
vee
T21P1.0
T2EXIP1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.1
RST
P3.0/RXD
P3.1ITXD
P3.2IiR"i'O
P3.3/1NTi
P3.4ITO
P3.51T1
P3.61WR
P3.711m
XTAL2
XTAL1
PO.O
PO.1
.PO.2
PO.3
PO.4
PO.5
PO.6
PO.7
EA
ALE
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
VSS
:6: : 5: :4: :3: :2: 1: :44: :43: :42: :41:
"'..
.......
•••
....
.....
I
..........
", .. 01
:40;
•••
Pl.5
Pl.6
PH
RST
83C154
/83C154D
1'30
NC
1'31
1'32
P3.3
1'34
1'35
p- .....................
p-. r- •
:18: :19: :20: :21: :22! :23: :24: :25: :28: :27:
P- . . . . .
0
til
g!
OIL
Z
LCC
PI. PI3 PI2 Pu PIO NC Vee Poo POI PO! P03
PI'
PI6
1•
PI7
RST
3
4
P30
5
NC
P31
6
7
27
ALE
P32
8
26
PSEN
P33
9
P27
P3.
10
25
24
P3!I
11
23
P2!I
po.
2
Po,
83C154/83C154D
Flat Pack
Diagrams are for pin reference only. Package sizes are not to scale.
Figure 2 : Configurations.
6-103
31
PQ6
30
P07
29
rA
28
NC
P26
•••
:~
____________________________ 83C154~3C154D---------------------------Symbol Position Name and Function
IDLE AND POWER DOWN OPERATION
Figure 3 shows the internal Idle and Power Down clock
configuration. As illustrated, Power Down operation
stops the oscillator. The interrupt, serial port, and timer
blocks continue to function only with external clock
(INTO, INT1, TO, T1).
GF1
PCON.3 General-purpose flag bit.
GFO
PCON.2 General-purpose flag bit.
PD
PCON.1
Power Down bit. Setting this bit
activates power down operation.
IDL
PCON.O Idle mode bit. Setting this bit activates idle mode operation.
If 1's are written to PD and IDL at the same time. PD
takes, precedence. The reset value of PCON is
(OOOXOOOO).
IDLE MODE
The instruction that sets PCON.O is the last instruction
executed before the Idle mode is activated. Once in the
Idle mode the CPU status is preserved in its entirety:
the Stack Pointer, Program Counter, Program Status
Word, Accumulator, RAM and all other registers maintain their data during idle. In the idle mode, the internal
clock signal is gated off to the CPU, but interrupt, timer
and serial port functions are maintained. Table 1
describes the status of the external pins during Idle
mode.
There are three ways to terminate the Idle mode. Activation of any enabled interrupt will cause PCON.O to
be cleared by hardware, terminating Idle mode. The interrupt is serviced, and following RETI, the next instruction to be executed will be the one following the
instruction that wrote 1 to PCON.O.
The flag bits GFO and GF1 may be used to determine
whether the interrupt was received during normal execution or during the Idle mode. For example, the instruction that writes to PCON.O can also set or clear one
or both flag bits. When Idle mode is terminated by an
enabled interrupt, the service routine can examine the
status of the flag bits.
The second way of terminating the Idle mode is with a
hardware reset. Since the oscillator is still running, the
hardware reset needs to be active for only 2 machine
cycles (24 oscillator periods) to complete the reset
operation.
The third way to terminate the Idle mode is the activation of any disabled interrupt when recover is
programmed (RPD = 1). This will cause PCON.O to be
cleared. No interrupt is serviced. The next instruction is
executed. If interrupt are disabled and RPD = 0, only a
Figure 3 : Idle and Power Down Hardware.
Idle Mode operation allows the interrupt, serial port, and
timer blocks to continue to function with internal or external clocks, while the clock to CPU is gated off. The
special modes are activated by software via the Special
Function Register, PCON.lts hardware address is 87H.
PC ON is not bit addressable.
PCON : Power Control Register
(MSB)
(LSB)
@MOD HPD RPD
GF1
GFO
PD
IDL
I
Symbol Position Name and Function
SMOD
PCON.7 Double Baud rate bit. When set
to a 1, the baud rate is doubled
when the serial port is being
used in either modes 1, 2 or 3.
HPD
PCON.
RPD
PCON.5 Recover from Idle or Power
Down bit. When 0 RPD has no
effect. When 1, RPD permits to
exit from idle or Power Down with
any non enabled interrupt source
(except timex 2). In this case the
program start at the next address.
When
interrupt
is
enabled, the appropriate interrupt routine is serviced.
Hard power Down bit. Setting
this bit allows CPU to enter in
Power Down state on an external
event (1 to 0 transition) on bit T1
(p. 3-5) the CPU quit the Hard
Power Down mode when bit T1
(p. 3-5) go high or when reset is
activated
POWER DOWN MODE
The instruction that sets PCON.1 is the last executed
prior to entering power down. Once in power down, the
oscillator is stopped. The contents of the onchip RAM
and the Special Function Register is saved during
power down mode. The three ways to terminate the
Power Down mode are the same than the Idle mode.
But since the onchip oscillator is stopped, the external
interrupts, timers and serial port must be sourced by external clocks only, via INTO, INT1, TO, T1.
In the Power Down mode, Vee may be lowered to minimize circuit power consumption. Care must be taken
PCON.4 (Reserved)
6-104
____________________________
83C154~3C154D
to ensure the voltage is not reduced until the power
down mode is entered, and that the voltage is restored
before the hardware reset is applied which frees the oscillator. Reset should not be released until the oscillator
has restarted and stabilized.
____________________________
When the port latch contains 0, all pFETS in figure 4 are
off while the nFET is turned on. When the port latch
makes a 0-to-1 transition, the nFET turns off. The strong
pullup pFET, T1 , turns on for two oscillator periods, pulling the output high very rapidly. As the output line is
drawn high, pFET T3 turns on through the inverter to
supply the IOH source current. This inverter and T3 form
a latch which holds the 1 and is supported by T2. When
Port 2 is used as an address port, for access to external
program of data memory, any address bit that contains
a 1 will have his strong pullup turned on for the entire
duration of the external memory access.
When using voltage reduction : interrupt, timers and
serial port functions are guaranteed in the Vcc
specification limits.
Table 1 describes the status of the external pins while
in the power down mode. It should be noted that if the
power down mode is activated while in external program memory, the port data that is held in the Special
Function Register P2 is restored to Port 2. If the port
switches from 0 to 1, the port pin is held high during the
power down mode by the strong pullup, T1, shown in
figure 4.
When an I/O pin on Ports 1, 2, or 3 is used as an input,
the user should be aware that the external circuit must
sink current during the logical 1-to-0 transition. The
maximum sink current is specified as ITL under the D.C.
Specifications. When the input goes below approximately 2 V, T3 turns off to save ICC current. Note,
when returning to a logical 1, T2 is the only internal pullup that is on. This will result in a slow rise time if the
user's circuit does not force the input line high.
The input impedance of Port 1, 2, 3 are programmable
through the register 10CON. The ALF bit (IOCONO) set
all of the Port 1, 2, 3 floating when a Power Down mode
occurs. The P1 HZ, P2HZ, P3HZ bits (IOCON1,
IOCON2, IOCON3) set respectively the Ports P1, P2,
P3 in floating state. The IZC (IOCON4) allows to choose
input impedance of all ports (P1, P2, P3). When IZC =
0, T2 and T3 pullup of I/O ports are active; the internal
input impedance is approximately 10 K. When IZC = 1
only T2 pull-up is active. The T3 pull-up is turned off by
IZC. The internal impedance is approximately 100 K.
F:;r--1====~
FROM
. : C>+--t).__,
1IlIIIr __+_....
Figure 4: I/O Buffers in the 83C154/83C154D
(Ports 1, 2, 3).
STOP CLOCK MODE
PIN DESCRIPTIONS
Due to static design, the MHS 83C154/83C154D clock
speed can be reduced until 0 MHz without any data loss
in memory or registers. This mode allows step by step
utilization, and permits to reduce system power consumption by bringing the clock frequency down to any
value. At 0 MHz, the power consumption is the same
as in the Power Down Mode.
Vss
Circuit ground potential.
Vcc
Supply voltage during normal, Idle, and Power Down
operation.
83C154/83C154D I/O PORTS
PORTO
The I/O drives for P1, P2, P3 of the 83C154/83C154D
are impedance programmable. The I/O buffers for Ports
1, 2 and 3 are implemented as shown in figure 4.
Port 0 is an 8-bit open drain bi-directionall/O port. Port
1's written to them float, and in that
state can be used as high-impedance inputs.
o pins that have
MODE
PROGRAM MEMORY
ALE
PSEN
PORTO
PORT1
PORT2
PORT3
Idle
Internal
1
1
Port Data
Port Data
Port Data
Port Data
Idle
External
1
1
Floating
Port Data
Address
Port Data
Power
Down
Internal
0
0
Port Data
Port Data
Port Data
Port Data
Power
Down
External
0
0
Floating
Port Data
Port Data
Port Data
Table 1 : Status of the external pins during Idle and Power Down Modes.
6-105
---------------------------83C154/83C154D--_________________________
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and Data
Memory. In this application it uses strong internal pullups when emitting 1'so Port 0 also outputs the code
bytes during program verification in the 83C154/83C154D. External pullups are required during program verification. Port 0 can sink eight LS TTL inputs.
Port 3 can sink/source three LS TTL inputs. It can drive
CMOS inputs without external pullups.
RST
A high level on this for two machine cycles while the oscillator is running resets the device. An internal pulldown resistor permits Power-On reset using only a
capacitor connected to Vce.
PORT 1
ALE
Port 1 is an 8-bit bi-directionall/O port with internal pullups. Port 1 pins that have 1's written to them are pulled
high by the internal pullups, an in that state can be used
as inputs. As inputs, Port 1 pins that are externally being
pulled low will source current (ilL, on the data sheet) because of the internal pullups.
Port 1 also receives the low-order address byte during
program verification. In the 83C154, Port 1 can
sink/source three LS TTL inputs. It can drive CMOS inputs without external pullups.
Address Latch Enable output for latching the low byte
of the address during accesses to external memory.
ALE is activated as though for this purpose at a constant
rate of 1/6 the oscillator frequency except during an external data memory access at which time one ALE
pulse is skipped. ALE can sink/source 8 LS TTL inputs.
It can drive CMOS inputs without an extemal pullup.
PSEN
Program Store Enable output is the read strobe to external Program Memory. PSEN is activated twice each
machine cycle during fetches from external Program
Memory. (However, when executing out of external
Program Memory, two activations of PSEN are skipped
during each access to external Data Memory). PSEN
is not activated during fetches from intemal Program
Memory. PSEN can sink/source 8 LS TTL inputs. It can
drive CMOS inputs without an external pullup.
PORT 2
Port 2 is an 8-bit bi-directionalllO port with internal pullups. Port 2 pins that have 1's written to them are pulled
high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 2 pins that are externally
being pulled low will source current (ILL, on the data
sheet) because of the internal pullups. Port 2 emits the
high-order address byte during fetches from external
Program Memory and during accesses to external Data
Memory that use 16-bit addresses (MOVX @ DPTR).
In this application, it uses strong internal pullups when
emitting 1'so During accesses to external Data Memory
that use 8-bit addresses (MOVX@Ri), Port 2 emits the
contents of the P2 Special Function Register.
It also receives the high-order address bits and control
signals during program verification in the 83C154. Port
2 can sink/source three LS TTL inputs. It can drive
CMOS inputs without external pullups.
EA
When EA is held high, the CPU executes out of internal
Program Memory (unless the Program Counter exceeds 3 FFFH). When EA is held low, the CPU executes
only out of external Program Memory. EA must not be
floated.
XTAL1
Input to the inverting amplifier that forms the oscillator.
Receives the external oscillator signal when an external
oscillator is used.
PORT 3
Port 3 is an 8-bit bi-directionall/O port with internal pullups. Port 3 pins that have 1's written to them are pulled
high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 3 pins that are externally
being pulled low will source current (ILL, on the data
sheet) because of the pullups. It also serves the functions of various special features of the MHS-51 Family,
as listed below.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
XTAL2
Output of the inverting amplifier that forms the oscillator.
This pin should be floated when an external oscillator
is used.
OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output respectively, of an inverting amplifier which is configured for use
as an on-chip oscillator, as shown in figure 5. Either a
quartz crystal or ceramic resonator may be used.
Alternate Function
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
!.:!JTimer 1 external input)
WR (external Data Memory write strobe)
RD (external Data Memory read strobe)
To drive the device from an external clock source,
XTAL 1 should be driven while XTAL2 is left unconnected as shown in figure 6. There are no requirements
on the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a divide-
6-106
----------------------------83C154~3C154D
by-two flip-flop, but minimum and maximum high and
low times specified on the Data Sheet must be observed.
--
~
ElT
'--
____________________________
TIMER FUNCTIONS
In fact, timer 0 & 1 can be connected by a software instruction to implement a 32-bit timer function. Timer 0
(mode 3) or timer 1 (mode 0, 1,2) or a 32-bit timer consisting of timer 0 + timer 1 can be employed in the
watchdog mode, in which case a CPU reset is
generated upon a TF1 flag.
The internal pull-up resistances at ports 1 - 3 can be set
to a ten times increased value simply by software.
XTAL2:18
r- XTAL1: 19
Watchdog timer
VSS:20
--=
Figure 5 : Crystal Oscillator.
N C - X1N..2: 18
EXTB-1NAL
0SCII.LAJ0R-------04X1M.1: 19
SIGNAL
-r
ElT7.WDT
32-bit timer [IOCON bit 6 (T32)
= 11
VSS : 20
Figure 6 : External Drive Configuration.
PORT 1 SECONDARY FUNCTIONS
This is a quasi-bidirectional I/O port, internally pulled up
when used as input ports. Two of the ports have been
allocated a second function which are:
P1.0 [T2] : External clock input for timer/counter 2.
P1.1 [T2EX] : A trigger input for timer/counter 2, to be
reloaded or captured causing the timer/counter 2 interrupt.
Figure 7.
TIMER/EVENT COUNTER 2
INTERRUPT MODES
Timer 2 is a 16-bit timer/counter like Timers 0 and 1, it
can operate either as a timer or as an event counter.
This is selected by bit CIT2 in the Special Function
Register T2CON (Figure 7). It has three operating
modes: "capture", "autoload", and "baud rate generator", which are selected by bits in T2CON as shown in
The MHS 80C154/83C154/83C154D is capable of handling two external interrupts, three interrupts from the
timers, and one interrupt from the serial port, through its
incorporated six source, two-level interrupt structure.
SERIAL PORT TIMING
RCLK + TCLK CP/RL2 TR2
The interrupt is executed after the Stop Bit.
..
1 FRAME
0
0
0
1
X
X
1
X
•
1
1
1
0
MODE
16 bit auto-reload
16-bit capture
baud rate generator
(off)
Table 2 : Timer 2 Operating Modes.
Table 2.
t
S\MTBIT
Sa-98fT
IlIIW\
In the capture mode there are two options which are
selected by bit EXEN2 in T2CON. If EXEN2 = 0, then
Timer 2 is a 16-bittimer or counter which upon overflowing sets bit TF2, the Timer 2 overflow bit, which can be
used to generate an interrupt If EXEN2 = 1 , then Timer
2 still does the above, but with the added feature that a
1-to-0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 ans TH2, to be
t
SltJparr
INTERRUPT
6-107
--_________________________
83C154~3C154D
captured into registers RCAP2L and RCAP2H, respectively. (RCAP2L and RCAP2H are new Special Function Registers in the 80CS2). In addition, the transition
at T2EX causes bit EXF2 in T2CON to be set, and
EXF2, like TF2, can generate an interrupt.
The capture mode is illustrated in Figure B.
In the auto-reload mode there are again two options,
which are selected by bit EXEN2 in T2CON. If EXEN2
= 0, then when Timer 2 rolls over it not only sets TF2
but also causes the Timer 2 registers to be reloaded
with the 16-bitvalue in registers RCAP2L and RCAP2H,
which are preset by software. If EXEN2 = 1, then Timer
2 still does the above, but with the added feature that a
1-to-0 transition at extemal input T2EX will also trigger
the 16-bit reload and set EXF2.
The auto-reload mode is illustrated in Figure 9.
___________________________
(MSB)
I
TF2
(LSB)
EXF2
Symbol
TF2
EXF2
RCLK
TCLK
EXEN2
Figure 8: Timer 2 in Capture Mode.
TR2
CIT2
CP/RL2
Figure 9 : Timer 2 in Auto-Reload Mode.
RCLK
TCLK
EXEN2
TR2
CIT2 CP;RUj
Position Name and Significance
T2CON.7 Timer 2 overflow flag set by a
Timer 2 overflow and must be
cleared by software. TF2 will not
be set when either RCLK = 1 or
TCLK = 1
T2CON.6 Timer 2 external flag set when
either a capture or reload is
caused by a negative transition on
T2EX and EXEN2 = 1. When
Timer 2 interrupt is enabled, EXF2
= 1 will cause the CPU to vector to
the Timer 2 interrupt routine.
EXF2 must be cleared by
software.
T2CON.5 Receive clock flag. When set,
causes the serial port to use Timer
2 overflow pulses for its receive
clock in modes 1 and 3. RCLK =
o causes Timer 1 overflow to be
used for the receive clock.
T2CONA Transmit clock flag. When set,
causes the serial port to use Timer
2 overflow pulses for its transmit
clock in modes 1 and 3. TCLK = 0
causes Timer 1 overflows to be
used for the transmit clock.
T2CON.3 Timer 2 external enable flag.
When set, allows capture or
reload to occur as a result of a
negative transition on T2EX if
Timer 2 is not being used to clock
the serial port. EXEN2 = 0 causes
Timer 2 to ignore events as T2EX.
T2CON.2 Start/stop control for Timer 2. A
logic 1 starts the timer.
T2CON.l Timer or counter select. (Timer 2)
o = Internal timer (OSCI12) 1 =
External event counter (falling
edge triggered).
T2CON.O Capture/Reload flag. When set,
captures will occur on negative
transitions at T2EX if EXEN 2 = 1.
When cleared, auto reloads will
occur either with Timer 2 overflows or negative transitions at
T2EX when EXEN2 = 1. When
either RCLK = 1 or TCLK = 1, this
bit is ignored and the timer is
forced to auto-reload on Timer 2
overflow.
Figure 7 : T2CON :
Timer/Counter 2 Control Register.
6-108
- - - - - - - - - -_ _ _ 83C154/83C154D _ _ _ _ _ _ _ _ _ _ _ __
DATA MEMORY AND SPECIAL FUNCTION REGISTER LAYOUT DIAGRAM
OF8H
OFOH
OEOH
ODOH
OmH
OCCH
OCBH
OCAH
OCBH
OBBH
OBOH
OASH
OAOH
99H
98H
90H
80H
8CH
8BH
8AH
89H
88H
87H
83H
82H
81H
80H
OFFH
BaH
IOCON
B
N:;C
PSW
TH2
TL2
RCAP2H
RCAP2L
T2CON
IP
P3
IE
P2
SBUF
SCON
P1
TH1
THO
TL1
TLO
TMOD
TCON
PCON
DPH
DPL
SP
PO
7FH
30H
2FH
20H
1FH
1BH
17H
10H
OFH
7F BIT
78
ADDRESSABLE
7 RAM
0
R7
BANK 3
RO
R7
BANK 2
RO
R7
BANK 1
~
-
r------ DIRECT BIT ADDRESSING
REGISTER ADDRESSING
08H RO
07H R7
BANKO
OOH RO
-DiRECTBVTE ADDRESSING
INDIRECT ADDRESSiNG
6-109
- - - - - - - - - - - - 8 3 C 1 5 4 / 8 3 C 1 5 4 D _ _ _ _ _ _ _ _ _ _ __
DETAILED DIAGRAM OF DATA MEMORY (RAM)
(I
OFFH
255
7FH
127
2FH 7F
7E
70
7C
78
7A
79
78
47
2EH 77
76
75
74
73
72
71
70
46
2DH 6F
6E
60
6C
68
6A
69
68
45
2a-1 67
66
65
64
63
62
61
60
44
281-1 5F
5E
50
5C
58
5A
59
58
43
2AH
57
56
55
54
53
52
51
50
42
zC!J
29H 4F
4E
40
4C
48
4A
49
48
41
28H 47
46
45
44
43
42
41
40
CiS
m
m
c
~
c
c
27H
3F
3E
30
3C
38
3A
39
38
26H
37
36
35
34
33
32
31
30
40 c
c(
39 t::
m
38 t
25H 2F
2E
20
2C
28
2A
29
28
w
24H
27
26
25
24
23
22
21
20
37 ex:
0
36
23H
1F
1E
10
1C
18
1A
19
18
35
22H
17
16
15
14
13
12
11
10
34
21H OF
OE
00
OC
08
OA
09
08
33
20H
1FH
06
05
04
03
02
01
00
32
31
07
Bank 3
18H
17H
24
23
Bank 2
10H
OFH
C!J
i
~c
16 c
15 c(
Bank 1
08H
07H
8
7
BankO
OOH
0
6-110
m
C!J
i
C!J
z
~
C!J
z
w
~
~
~
0
~ t
C
~
----------------------------83C154~3C154D
____________________________
DETAILED DIAGRAM OF SPECIAL FUNCTION REGISTERS
Direct
Byte
Address
Special
Function
Register
Symbol
Bit Address
(MSB)
WOT
OF8H
OFOH
OEOH
OOOH
OCOH
OCCH
OCBH
OCAH
(LSB)
T32
ALF
CY
AC
FO
RS1
RSO
OV
F1
P
07
06
05
04
03
02
01
DO
~======================~
Not Bit Addressable
Not Bit Addressable
Not Bit Addressable
Not Bit Addressable
TF2
EXF2
RCLK
CF
CE
CO
CC
CB
CA
C9
C8
PT2
PS
PT1
PX1
PTO
PXO
TCLK EXEN2
TR2
B7
B6
OAOH
A7
A6
B5
B4
B3
B2
B1
BO
ET2
ES
ET1
EX1
ETO
EXO
AD
AC
AB
AA
A9
A8
A5
A4
A3
A2
A1
AO
99H
B
ACC
PSW
TH2
TL2
RCAP2H
RCAP2L
I
I
I
I
T2CON
IP
P3
IE
P2
SBUF
Not Bit Addressable
I
I
laCON
CIT2 CP/RL2
BO
BC
BB
BA
B9
B8 I
~B=F================================~
AF
SMO
SM1
SM2
REN
TB8
RB8
TI
RI
9F
9E
90
9C
9B
9A
99
98
SCaN
97
96
95
94
93
92
91
90
P1
Not Bit
Not Bit
Not Bit
Not Bit
Not Bit
80H
~H
8BH
MH
89H
Addressable
Addressable
Addressable
Addressable
Addressable
T~
TMOO
TFO
IT1
lEO
ITO
8F
8E
80
8C
8B
8A
Not Bit Addressable
89
88
86
Not Bit Addressable
Not Bit Addressable
Not Bit Addressable
84
85
83
82
6-111
IE1
T~
TL1
TR1
87
TRO
TH1
TF1
83H
82H
81H
80H
P1HZ
LI
OA8H
88H
87H
P2HZ
I
I
I
~======================~
E6
E4 __~
E3__-=~~~~~
E2
E5 __~
E1
EO I
~E~7__-=~~=-
EA
90H
P3HZ
~I
PCT
98H
IZC
FD
FC
FB
FA
F9
FE
=F:::::F==================;,
F6
F5
F4
F2
F1
F3
FO
F7
OC8H
OB8H
OBOH
SERR
TCON
PCON
OPH
OPL
SP
81
80
PO
___________________________
83C1~3C154D
___________________________
SPECIAL FUNCTION REGISTERS
TIME MODE REGISTER (TMOD)
NAME
ADDRESS
TMOD
a9H
BIT LOCATION
TMOD.O
FLAG
MO
LSB
MSB
7
I
GATE
I
I
6
CIT
J
5
I
4
3
Ml
L
MO
GATE
I
J
2
CIT
I
l
1
Ml
I
J
0
MO
FUNCTION
Ml
MO
0
0
0
1
16-bit timer/counter.
0
1
a-bit timer/counter with a-bit auto reloading.
1
Timer/counter 0 mode setting.
a-bit timer/counter with 5-bit prescalar.
TMOD.l
Ml
TMOD.2
CIT
Timer/counter 0 count clock designation control bit. XTAL 1.~ divided
by 12 clocks is the input applied to timer/counter 0 when CIT = "0".
The external clock appli~d to the TO pin is the input applied to
timer/counter 0 when CIT = "1 ".
TMOD.3
GATE
When this bit is "0", the TRO bit of TCON (timer control register) is
used to control the start and stop of timer/counter 0 counting.
If this bit is "1", timer/counter 0 starts counting when both the TRO bit
of TeON and INTO pin input signal are "1", and stops counting when
either is changed to "0".
TMOD.4
MO
TMOD.5
Ml
TMOD.6
CIT
TMOD.7
GATE
1
Ml
MO
0
0
Timer/counter 0 separated into TLO (a-bit) timer/counter
and THO (a-bit) timer/counter. TFO is set by TLO carry, and
TFl is set by THO carry.
Timer/counter 1 mode setting.
a-bit timer/counter with 5-bit prescalar.
0
1
16-bit timer/counter.
1
0
a-bit timer/counter with a-bit auto reloading.
1
1
Timer/counter 1 operation stopped.
Timer/counter 1 count clock designation control bit.
XTAL.2 givided by 12 clocks is the input applied to timer/counter 1
when CIT = "0".
The external clock appli~d to the Tl pin is the input applied to
timer/counter 1 when CIT = "1".
When this bit is "0", the TRl bit of TCON is used to control the start
and stop of timer/counter 1 countig.
If this bit is "1 ", timer/counter 1 starts counting when both the TRl bit
of TeON and INTl pin input signal are "1", and stops counting when
either is changed to "0".
6-112
----------------___________
83C1~3C154D
___________________________
POWER CONTROL REGISTER (PCON)
LSB
MSB
NAME
ADDRESS
PCON
87H
BIT LOCATION
FLAG
FUNCTION
PCON.O
IDL
PCON.1
PO
PCON.2
GFO
PCON.3
GF1
PCON.4
PCON.5
RPD
IDLE mode set when this bit is set to "1 ". CPU operations are stopped
when IDLE mode is set, but XTAL1-2, timer/counters 0, 1 and 2, the
interrupt circuits, and serial port remain active. IDLE mode is cancelled
when the CPU is reset or when an interrupt is generated.
PO mode set when this bit is set to "1". CPU operations and XTAL 1-2
are stopped when PO mode is set. PO mode is cancelled when the
CPU is reset or when an interrupt is generated.
General purpose bit. Testing this flag when IDLE mode is cancelled by
an interrupt shows whether the interrupt is a normal interrupt or an IDLE
mode release interrupt.
General purpose bit.
Testing this flag when PO mode is cancelled by an interrupt shows
whether the interrupt is a normal interrupt or a PO mode release
interrupt.
Reserved bit. The output data is "1" if the bit is read.
Bit used to specify cancellation of CPU power down mode (IDLE or PO)
by interrupt signal. Power down mode cannot be cancelled by interrupt
signal if interrupt is not enabled by IE (interrupt enable register) when
this bit is "0". If the interrupt flag is set to "1" by an interrupt request signal
when this bit is "1" (even if interrupt is disabled), the program is executed
from the next address of the power down mode setting instruction. The
flag is reset to "0" by software.
-
PCON.6
HPD
PCON.7
SMOD
7
SMOD
I
I
I
6
HPD
I
5
RPD
I
I
4
3
-
GF1
I
I
2
GFO
I
I
1
PO
I
I
0
IDL
ENABLE RECOVER
PWD not cancelled
0
0
Execute interrupt routine
1
0
1
Execute next address
0
1
Execute interrupt routine
1
The hard power down setting mode is enabled when this bit is set to "1".
If the level of the power failure detect signal applied to the HPD1 pin (pin
3.5) is changed from "1" to "0" when this bit is "1", XTAL1-2 oscillation is
stopped and the system is put into hard power down mode. HPD mode
is cancelled when the CPU is reset, or HPD1 pin go high.
When the timer/counter 1 carry signal is used as a clock in mode 1, 2 or
3 of the serial port, this bit has the following functions.
The serial port operation clock is reduced by 1/2 when the bit is "0" for
delayed processing. And when the bit is "1 ", the serial port operation
clock is normal for faster processing.
6-113
____________________________
83C15~83C154D
____________________________
TIMER CONTROL REGISTER (TCON)
LSB
MSB
NAME
ADDRESS
TCON
aaH
BIT LOCATION
TCON.O
FLAG
FUNCTION
ITO
External interrupt 0 signal used in level detect mode when this bit is
"0", and in trigger detect mode when "1 ".
TCON.1
lEO
Interrupt request flag for external interrupt O.
Bit is reset automatically when interrupt is serviced.
Bit can be set an reset by software when ITO = "1 ".
TCON.2
IT1
External interrupt 1 signal used in level detect mode when this bit is
"0", and in trigger detect mode when "1 ".
TCON.3
IE1
Interrupt request flag for external interrupt 1.
Bit is reset automatically when interrupt is serviced.
Bit can be set and reset by software when IT1 = "1 ".
TCON.4
TRO
Counting start and stop control bit for timer/counter O.
Timer/counter 0 starts counting when this bit is "1 ", and stops
counting when "0".
TCON.5
TFO
Interrupt request flag for timer interrupt O.
Bit is reset automatically when interrupt is serviced.
Bit is set to "1" when carry signal is generated from timer/counter O.
TCON.6
TR1
Counting start and stop control bit for timer/counter 1.
Timer/counter 1 starts counting when this bit is "1 ", and stops
counting when "0".
TCON.7
TF1
Interrupt request flag for timer interrupt 1.
Bit is reset automatically when interrupt is serviced.
Bit is set to "1" when carry signal is generated from timer/counter 1.
iiii'M1iii
7
TF1
I
l
I
6
TR1
J
6-114
5
TFO
I
I
4
3
TRO
IE1
I
I
2
IT1
I
I
1
lEO
I
I
0
ITO
--------------------________ 83C154~3C154D ____________________________
SERIAL PORT CONTROL REGISTER (SCON)
MSB
7
LSB
NAME
ADDRESS
SCON
98H
BIT LOCATION
FLAG
FUNCTION
SCON.O
RI
"End of serial port reception" interrupt request flag.
This flag must be reset by software during interrupt service routine.
This flag is set after the eighth bit of data has been received when in
mode 0, or by the STOP bit when in any other mode. In mode 2 or 3,
however RI is not set if the R88 data is "0" with SM2 = "1 ".
RI is set in mode 1 if STOP is received when SM2 = "1 ".
SCON.1
TI
"End of serial port transmission" interrupt request flag. This flag must
be reset by software during interrupt service routine.
This flag is set after the eighth bit of data has been sent when in
mode 0, or after the last bit of data has been when in any other
mode.
SCON.2
R88
The ninth bit of data received in mode 2 or 3 is passed to R88.
The STOP bit is applied to R88 if SM2 = "0" when in mode 1.
R88 can not be used in mode O.
SCON.3
T88
The T88 data is sent as the ninth data bit when in mode 2 or 3.
Any desired data can be set in T88 by software.
SCON.4
REN
Reception enable control bit.
No reception when REN = "0".
Reception enabled when REN = "1".
SCON.5
SM2
if the ninth bit of received data is "0" with SM2 = "1" in mode 2 or 3,
the "end of reception" signal is not set in the RI flag.
Nor is the "end of reception" signal set in the RI flag if the STOP bit is
not "1" when SM2 = "1" in mode 1.
SCON.6
SM1
SMO
SM1
MODE
0
0
0
8-bit shift register 110.
0
1
1
8-bit UART variable baud rate.
1
0
2
9-bit UART 1/32 XTAL 1, 1/64 XTAL 1 baud rate.
1
1
3
9-bit UART variable baud rate.
SCON.?
SMO
SMO
I
I
6
J
SM1
J
6-115
5
I
4
3
I
SM2
I
REN
T88
I
2
R88
I
1
I
0
I
TI
I
RI
____________________________
83C154~3C154D
____________________________
INTERRUPT ENABLE REGISTER (IE)
NAME
ADDRESS
IE
OA8H
BIT LOCATION
lE.O
FLAG
EXQ
IE.1
ETO
1E.2
EX1
1E.3
ET1
IE.4
ES
1E.5
ET2
1E.6
-
IE.?
EA
MSB
7
EA
LSB
I
I
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
6
-
I
I
5
ET2
I
I
4
3
ES
ET1
I
I
2
EX1
I
I
1
ETO
I
I
0
EXO
FUNCTION
control bit for external interrupt o.
disabled when bit is "0".
enabled when bit is "1".
control bit for timer interrupt O.
disabled when bit is "0".
enabled when bit is "1".
control bit for external interrupt 1.
disabled when bit is "0".
enabled when bit is "1".
control bit for timer interrupt 1.
disabled when bit is "0".
enabled when bit is "1".
Interrupt control for serial port.
Interrupt disabled when bit is "0".
Interrupt enabled when bit is "1 ".
Interrupt control bit for timer interrupt 2.
Interrupt disabled when bit is "0".
Interrupt enabled when bit is "1 ".
Reserved bit. The output data is "1" if the bit is read.
Overall interrupt control bit.
All interrupts are disabled when bit is "0".
All interrupts are controlled by IE.O through IE.5 when bit is "1 ".
INTERRUPT PRIORITY REGISTER (IP)
NAME
ADDRESS
IP
OB8H
BIT LOCATION
IP.O
FLAG
PXO
IP.1
PTO
IP.2
PX1
IP.3
PT1
IP.4
PS
IP.5
PT2
IP.6
IP.?
PCT
-
MSB
7
PCT
I
I
6
-
I
I
5
PT2
I
I
4
PS
3
PT1
I
I
2
PX1
I
I
1
PTO
I
I
LSB
0
PXO
FUNCTION
Interrupt priority bit for external interrupt o.
Priority is assigned when bit is "1 ".
Interrupt priority bit for timer interrupt o.
Priority is assigned when bit is "1".
Interrupt priority bit for external interrupt 1.
Priority is assigned when bit is "1".
Interrupt priority bit for timer interrupt 1.
Priority is assigned when bit is "1".
Interrupt priority bit for serial port.
Priority is assigned when bit is "1 ".
Interrupt priority bit for timer interrupt 2.
Priority is assigned when bit is "1".
Reserved bit. The output data is "1" if the bit is read.
Priority interrupt circuit control bit.
The priority register contents are valid and priority assigned interrupts
can be processed when this bit is "0". When the bit is "1", the priority
interrupt circuit is stopped, and interrupts can only be controlled by
the interrupt enable register (IE).
6-116
--__________________________
83C154~3C154D
____________________________
PROGRAM STATUS WORD REGISTER (PSW)
NAME
ADDRESS
PSW
ODOH
BIT LOCATION
FLAG
P
PSW.O
MSB
7
CY
LSB
I
I
6
I
AC
I
5
FO
I
I
4
3
RS1
RSO
I
I
2
OV
I
I
1
F1
I
0
L
P
FUNCTION
Accumulator (ACC) parity indicator.
"1" when the "1" bit number in the accumulator is an odd number,
and "0" when an even number.
PSW.1
F1
User flag which may be set to "0" or "1" as desired by the user.
PSW.2
OV
Overflow flag which is set if the carry C6 from bit 6 of the ALU or CY
is "1" as a result of an arithmetic operation. The flag is also set to "1"
if the resultant product of executing a multiplication instruction
(MULAB) is greater than OFFH, but is reset to "0" if the product is
less than or equal to OFFH.
PSW.3
RSO
PSW.4
RS1
RAM register bank switch.
BANK RAM ADDRESS
RS1
RSO
0
0
0
OOH - 07H
0
1
1
1
0
2
08H - OFH
10H - 17H
1
1
3
18H - 1FH
PSW.5
FO
User flag which may be set to "0" or "1" as desired by the user.
PSW.6
AC
Auxiliary carry flag.
This flag is set to "1" if a carry C3 is generated from bit 3 of the ALU
as a result of executing an arithmetic operation instruction.
In all other cases, the flag is reset to "0".
PSW.7
CY
Main carry flag.
This flag is set to "1" if a carry C7 is generated from bit 7 of the ALU
as result of executing an arithmetic operation instruction.
If a carry C7 is not generated, the flag is reset to "0".
6-117
____________________________
83C15~83C154D
____________________________
I/O CONTROL REGISTER (IOCON)
MSB
7
LSB
0
ALF
NAME
ADDRESS
laCON
OFBH
BIT LOCATION
IOCON.O
FLAG
ALF
IOCON.1
P1HZ
Port 1 becomes a floating state input port when this bit is "1".
IOCON.2
P2HZ
Port 2 becomes a floating state input port when this bit is "1 ".
IOCON.3
P3HZ
IaCONA
IZC
IOCON.5
SERR
Serial port reception error flag.
This flag is set to "1" if an overrun or framing error is generated when
data is received at a serial port.
The flag is reset by software.
IOCON.6
T32
Timer/counters 0 and 1 are connected serially to from a 32-bit timer/
counter when this bit is set to "1 ".
TF1 of TCON is set if a carry is generated in the 32-bit timer/counter.
IOCON.7
WDT
Watchdog timer mode is set when this bit is set to "1 ". And if TF1 is
set to "1" after watchdog timer mode has been set, the CPU is reset
and the program is executed from address O.
WDT
I
I
I
6
T32
5
I
I SERR I
4
IZC
3
P3HZ
I
2
I
1
I
I P2HZ I P1 HZ I
FUNCTION
If CPU power down mode (PD, HPD) is activated with this bit set to
"1 ", the outputs from ports 0, 1, 2 and 3 are switched to floating
status.
When this bit is "0", ports 0, 1, 2 and 3 are in output mode.
Port 3 becomes a floating state input port when this bit is "1 ".
The 10 kohm pull-up resistance for ports 1, 2 and 3 is switched off
when this bit is "1", leaving only the 100 kohm pull-up resistance.
6·118
------_______________________ 83C154/83C154D _____________________________
TIMER 2 CONTROL REGISTER (T2CON)
MSB
7
TF2
LSB
NAME
ADDRESS
T2CON
OCBH
BIT LOCATION
T2CON.0
CP/RL2
T2CON.1
CIT2
Timer/counter 2 count clock designation control bit.
The internal clocks (XTAL 1-2 .,. 12, XT AL 1-2 .,. 2) are used when this
bit is "0", and the external clock applied to the T2 is passed to
timer/counter 2 when the bit is "1".
T2CON.2
TR2
Timer/counter 2 counting start and stop control bit.
Timer/counter 2 commences counting when this bit is "1" and stops
counting when "0".
T2CON.3
EXEN2
T2EX timer/counter 2 external control signal control bit.
Input of the T2EX signal is disabled when this bit is "0", and enabled
when "1".
T2CONA
TCLK
Serial port transmit circuit drive clock control bit.
Timer/counter 2 is switched to baud rate generator mode when this
bit is "1 ", and the timer/counter 2 carry signal becomes the serial port
transmit clock.
Note, however, that the serial ports can only use the timer/counter 2
carry signal in serial port modes 1 and 3.
T2CON.5
RCLK
Serial port receive circuit drive clock control bit.
Timer/counter 2 is switched to baud rate generator mode when this
bit is "1", and the timer/counter 2 carry signal becomes the serial port
receive clock.
Note, however, that the serial ports can only use the timer/counter 2
carry signal in serial port modes 1 and 3.
T2CON.6
EXF2
Timer/counter 2 external flag.
This bit is set to "1" when the T2EX timer/counter 2 external control
signal level is changed from "1" to "0" while EXEN2 = "1 ".
This flag serves as the timer interrupt 2 request signal. If an interrupt
is generated, EXF2 must be reset to "0" by software.
T2CON.7
TF2
Timer/counter 2 carry flag.
This bit is set to "1" by a carry signal when timer/counter 2 is in 16-bit
auto reload mode or in capture mode.
This flag serves as the timer interrupt 2 request signal. if an interrupt
is generated, TF2 must be reset to "0" by software.
I
6
I
5
I
4
I EXF2 I RCLK I TCLK
FLAG
3
I
EXEN21
2
TR2
I
I
1
C/T2
I
0
ICP/RL2
FUNCTION
Capture mode is set when TCLK + RCLK = "0" and CP/RL2 = "1 ".
16-bit auto reload mode is set when TCLK + RCLK = "0" and
CP/RL2 = "0".
CP/RL2 is ignored when TCLK + RCLK = "1".
6-119
----------------------~
___ 83c154m3C154D----__________~___________
LIST OF INSTRUCTIONS
LIST OF INSTRUCTION SYMBOLS
A
: Accumulator
AB
: Register pair
AC
: Auxiliary carry flag
B
: Arithmetic operation register
: Carry flag
C
DPTR
: Data pointer
PC
: Program counter
: Register indicator (r = 0 - 7)
Rr
SP
: Stack pOinter
AND
: Logical product
OR
: Logical sum
: Exclusive OR
XOR
: Addition
+
: Substraction
x
: Multiplication
/
: Division
: Denotes the contents of x
(x)
((x))
: Denotes the contents of address
determined by the contents of x
iiii'Miiii
Denotes the immediate data
Denotes the indirect address
Equality
: Non equality
: Substitution
: Substitution
: Negation
: Smaller than
<
: Larger than
>
bit address
: RAM and the special function register
bit specifier address (bo - b7)
code address : Absolute address (Ao - A1)
: immediate data (10 - 17)
data
relative offset : Relative jump address offset value
(Ro- R7)
direct address : RAM and the special function register
byte specifier address (ao - a7)
#
@
6-120
_________________________ 83C154m3C154D _________________________
INSTRUCTION TABLE
~
0
0000
0
0000
NOP
1
0001
JBCbit,
rei
2
JBbit.
0010 ... rei
3
0011
JNBbIt,
4
JCbIt,
rei
rei
0100
1
2
0001
OQ10
AJMP
WMP ....
address 11 address 16
{Page 0)
,. ACAll
I.CALL ....
address 11 address 16
(Page 0)
AJMP
address 11
RET
(Page 1)
ACALL
adress 11
(PagEt 1)
AJMP
:11
(
2)
ACALL
5
JNCrei
0101
6
JZreI
0110
7
JNZreI
0111
address 11
(Page 2)
AJMP
address 11
(Page 3)
...
...
ACAll
address 11
C
1100
PUSH
direct
(PageS)
AJMP
address 11
(Page 6)
0
1101
POP
ACALL
E
1110
ORL
" dired,A
ANL
direct. A
XRL
direct, A
,. ACALL ,. ORLC,
address 11
bit
(Page 3)
AJMP
8
11
1000 SJMPrei address
(Page 4)
r./OI
ACALL
9
OPTR
address 11
1001
...# data 16 (Page 4)
AJMP
A
11
1010 ORALC,bit address
(Page 5)
B
1011 ANLCbIt,
RETI
direct
=
( 11
6)
,. AJMP
MOVXA,
@DPTR address 11
(Page 7)
,. ACALL
F
MOVX
1111 @DPTR.A :( 1 1
7)
ANLC,
bit
r./OIbIt,
C
tIOIc,
bit
3
5
7
0011
4
0100
0101
6
0110
0111
RRA
INCA
INC
direct
INCGRO
INC@R1
RRCA
DEC A
DEC
direct
DEC@RO
DEC@Rl
RLCA
QRl
,. AIDA,
, data
direct
AIDA,
@RO
AIDA,
@Rl
ADOCA,
AIXX:;A,
direct
AIXX:;A,
@RO
ADDCA,
@Rl
" ORLA, .... ,. 0RlA,
.fdata
direct
ORLA,
@RO
ORLA,
ORl
AIDA,
ALA
,.
, data
....
diJect,
, data
ANL
direct
, data
XRL
ANLA,
# data
ANLA,
direct
ANLA,
@RO
ANLA,
ORl
XRLA,
,. XRlA,
direct
XRLA,
XRLA,
• data
# data
JMP
@A+DPTR
r./OIA,
# data
MQ\£A,
@A+PC
DIVAS
MOV
direct 1.
direct 2
MOl
diJect,
@RO
direct,
@R1
SUBBA,
SUBBA,
# data
direct
SUBBA,
@RO
SUBS A.
.@R1
MQ\£A,
~A+DPTR
INC
... DPTR
MULAS
@Rl
@RO
direct
MOl ....
"MOV@Ro. MOVOR1,
direct,
# data
# data
I data
MOl
.... ,.MOV@RO, ,.r./OI@ R1,
direct
direct
....
...
CPLbit
CPLC
CJNEA, ....
# data,
rei
CJNEA,
direct,
rei
QRbit
CLRC
SWAP A
>OiA,
direct
>OiA,
@RO
>OiA.
@R1
SETBC
DJNZ
SETBbit
DAA
direct,
rei
>OiDA,
@RO
>OiA.
@Rl
MOVXA,
@RO
MOVXA,
@R1
ClRA
"MOVA,
direct
MOVA,
@RO
MOVA.
@Rl
MOVX
@RO,A
MOVX
@R1,A
CPLA
"
MOV
MOV
@Rl,A
6-121
r./OI
direct, A
CJNE@R(J. CJNE@Ri:
I data.
# data.
rei
rei
@RO.A
- - - - - -_ _ _ _ _ _ 83C154/83C154D _ _ _ _ _ _ _ _ _ _ __
~
1000
8
9
1001
A
1010
B
1011
C
1100
0
1101
E
1110
F
1111
0
0000
INCRO
INCRl
INCR2
INCR3
INCR4
INCR5
INCR6
INCR7
1
0001
DECRO
DECRl
DECR2
DECR3
DECR4
DECR5
DECR6
DECR7
2
0010
ADD A,
RO
ADD A,
Rl
ADD A,
R2
ADD A,
R3
ADD A,
R4
ADD A,
R5
ADD A,
R6
ADD A,
R7
3
0011·
ADDCA,
RO
ADDCA,
Rl
ADDCA,
R2
ADOCA,
R3
ADDCA,
R4
ADDCA,
R5
ADOCA,
R6
ADOCA,
R7
4
0100
ORLA,
RO
ORLA,
Rl
ORLA,
R2
ORLA,
R3
ORLA,
R4
ORLA,
R5
ORLA,
R6
ORLA,
R7
5
0101
ANLA,
RO
ANLA,
Rl
ANLA,
R2
ANLA,
R3
ANLA,
R4
ANLA,
R5
ANLA,
R6
ANLA,
R7
6
0110
XRLA,
RO
XRLA,
Rl
XRLA,
R2
XRLA,
R3
XRLA,
R4
XRLA,
R5
XRLA,
R6
XRLA,
R7
MCNRO,
data
"'MQV
8
direct,
1000
RO
MOVR1,
4tdata
MOVR2,
4tdata
MOVR3,
4tdata
MOVR4,
4tdata
MOVR5,
4tdata
MCNR6,
4tdata
MOVR7,
4tdata
MCN
direct,
Rl
MCN
direct,
R2
MOV
direct,
R3
MOV
direct,
R4
MOV
direct,
R5
9
1001
SUBBA,
RO
SUBBA,
Rl
SUBBA,
R2
SUBBA,
R3
SUBBA,
R4
SUBBA,
R5
SUBBA,
R6
SUBBA,
R7
A
1010
MOVRO,
direct
MOVR1, ,... MOVR2,
direct
direct
MOVR3,
direct
MCNR4,
direct
MOVR5,
direct
MOVR6,
direct
MCNR7,
direct
B
1011
CJNERO,
4tdata
rei
CJNER1,
4tdata
rei
CJNER2,
4tdata
rei
CJNER3,
4tdata
rei
CJNER4,
4tdata
rei
CJNER5,
4tdata
rei
CJNER6,
4tdata
rei
CJNER7,
4tdata
rei
C
1100
)CHA,
RO
)CHA,
Rl
)CHA,
R2
XCHA,
R3
XCHA,
R4
)CHA,
R5
XCHA,
R6
XCHA,
R7
DJNZR2,
rei
DJNZR3,
rei
DJNZR4,
rei
7
0111
'*
0 ,.. DJNZRO, ,.. DJNZR1,
1101
rei
rei
...
...
...
...
,.. MOV
direct,
R6
DJNZR5, ,.. DJNZR6,
rei
rei
....
MOV
direct,
R7
...
DJNZR7,
rei
E
1110
MOVA,
RO
MOVA,
Rl
MOVA,
R2
MOVA,
R3
MOVA,
R4
MOVA,
R5
MOVA,
R6
MOVA,
R7
F
1111
MOVRO,
A
MOVR1,
A
MOVR2,
A
tN:)VR3,
A
MOVR4,
A
MOVR5,
A
MOVR6,
A
MOVR7,
A
6-122
--------____________________ 83C154~3C154D---------------------------INSTRUCTION SET DETAILS
INSTRUCTION CODE
MNEMONIC
D7 ~(i D5 D4 D3 D2 D1 Do
ARITHMETIC OPERATION INSTRUCTIONS
ADD
A,Rr
1 0 1 r2 r1 ro
0 0
ADD
A, direct
1 0 0 1 0 1
0 0
BYTES
CYCLES
1
2
1
1
DESCRIPTION
(AC), (OV), (C), (A) ~
(AC), (OV), (C), (A) ~
+ (direct address)
(AG), (OV), (G), (A) ~
+ ((Rr))
(AG), (OV), (G), (A) ~
+ #data
(AG), (OV), (G), (A) ~
+(Rr)
(AG), (OV), (G), (A) ~
+ (direct address)
(AG), (OV), (G), (A) ~
((Rr})
(AG), (OV), (G), (A) ~
+ #data
(AG), (OV), (G), (A) ~
- (Rr)
(AG), (OV), (G), (A) ~
- (direct address)
(AG), (OV), (G), (A) ~
- ((Rri)
(AG), (OV), (G), (A) ~
- #data)
(AG)
~
(A) + (Rr)
(A)
ADD
A, @Rr
0
0
1
0
0
1
1
ro
1
1
ADD
A, #data
0
17
0
0
IR
0
1
Is
1
0
14
1
0
1
I?
r2
0
11
r1
0
10
ra
2
1
1
1
0
a7
0
0
aR
0
1
as
1
1
a4
1
1
a2
1
0
a1
1
1
ao
ra
2
1
1
1
0
1
14
1
1
1
12
r2
0
11
r1
0
10
ra
1
0
1
Is
0
2
k
SUBB A, Rr
0
17
1
1
1
SUBB A, direct
1
0
0
1
0
1
0
1
2
1
SUBB A, @Rr
1
0
0
1
0
1
1
ra
1
1
SUBB A, #data
0
16
1
14
0
0
11
0
2
1
1
0
0
IQ
0
0
1
4
4
0
0
1
1
When the contents of
accumulator bits 0 thru 3 are
greater than 3, or when auxiliary
carry (AC) is 1, 6 added to bits 0
thru 3. Bits 4 thru 7 are then
examined and when bits 4 thru
7 following compensation of
lower bits 0 thru 3 is greater
than 9, or when carry (C) is 1, 6
added to bits 4 thru 7. As a
result, the carry flag can be set,
but cannot be cleared.
0
0
1
1
1
1
1
1
1
(A) ~ 0
(A) ~ (A)
ADDG A, Rr
ADDG A, direct
ADDC A, @Rr
ADDG A, #data
I~
1
0
a~
0
0
"
MUL
DIV
AB
1
17
1
0
0
15
1
0
0
AB
1
0
0
0
0
1
12
1
1
DA
A
1
1
0
1
0
1
b
(A) quotient
(B) remainder
~
(A)
(A)
(A) + (G)
(A) + (G)
(A) + (G) +
(A) + (G)
(A) - (G)
(A) - (G)
(A) - (G)
(A) - (G)
(A) x (B)
(A)/B
ACCUMULATOR OPERATION INSTRUCTIONS
CLR
GPL
RL
A
A
A
1
1
0
1
1
0
1
1
1
0
1
0
0
0
0
1
1
0
0
0
1
Accumulator
~;I~H~I~I~I~I~J
RLG
A
0
0
1
1
0
0
1
1
1
1
Accumulator
r;H-H-I.+-I~J
6-123
___________________________
83C154~154D
___________________________
INSTRUCTION SET DETAILS (CONT.)
MNEMONIC
RR
A
INSTRUCTION CODE
D7 D6 Ds D4 Ds D2 D, Do
0 0 0 0 0 0 1 1
BYTES CYCLES
1
1
DESCRIPTION
Accumulator
@]C;H-I-+++I-I;j
RRC
A
0
0
0
1
0
0
1
1
1
1
Accumulator
~;H-I-H-H;j
SWAP A
1 1 0 0 0 1
INCREMENT/DECREMENT
INC
A
0 0 0 0 0 1
INC
Rr
0 0 0 0 1 r2
INC
direct
0 0 0 0 0 1
a7 as as a4 a3 a2
INC
@Rr
0 0 0 0 0 1
INC
DPTR
1 0 1 0 0 0
DEC A
0 0 0 1 0 1
DEC
Rr
0 0 0 1 1 r2
DEC direct
0 0 0 1 0 1
a7 as as a. as a2
DEC @Rr
0 0 0 1 0 1
LOGICAL OPERATION INSTRUCTIONS
ANL
A, Rr
0 1 0 1 1 r?
ANL
A, direct
0 1 0 1 0 1
a7 aR a~ a a~ a?
A,@Rr
ANL
0 1 0 1 0 1
0 1 0 1 0 1
ANL
A,#data
17 16 Is 14 13 b
direct, A
ANL
0 1 0 1 0 0
a7 as as ~ a3 a2
ANL
direct, #data 0 1 0 1 0 0
a7 as
~ a3 a2
b IR I~ I.. I~ I?
ORL
A, Rr
0 1 0 0 1 r2
A, direct
ORL
0 1 0 0 0 1
a7 as as a4 a3 a2
A,@Rr
ORL
0 1 0 0 0 1
ORL
A, #data
0 1 0 0 0 1
b 11'1 I~ I.. b I?
as
0
0
1
1
(A3 - 0) t- (A7 - 4)
0
0
r,
ro
1
ao
rn
1
1
1
1
1
1
2
1
1
1
1
1
(A) t- (Al + 1
(Rr) t- (Rr) + 1
(direct address) t- (direct
address) + 1
«Rr)) t- «Rr)) + 1
(DPTR) t- (DPTR) + 1
(Al t- (Al-1
(Rr) t- (Rr) -1
(direct address) t- (direct
address) -1
((Rr)) t- ((Rrll -1
1
1
1
(Al t- (Al AND (Rrl
(A) t- (A) AND (direct address)
2
1
1
(Al t- (A) AND (Rr)
(A) t- (A) AND #data
0
2
1
3
2
1
0
1
ao
In
ro
1
(direct address) t- (direct
address) AND (A)
(direct address) t- (direct
address) AND #data
(A) f.!.. (A) OR (Rr)
(A) t- (A) OR (direct address)
a,
1
an
1
1
rn
1
0
0
2
1
1
(Al t- (Al OR ((Rr))
(A) t- (A) OR #data
I,
In
0
a,
1
1
0
0
r,
ro
1
ao
rn
0
a,
1
r
a,
1
rn
1
an
ro
0
0
I,
1
a,
1
a,
I,
r
10
0
an
6-124
2
1
1
1
1
2
1
2
1
2
----_______________________
83C154~3C154D
___________________________
INSTRUCTION SET DETAILS (CONT.)
MNEMONIC
ORL
direct, A
ORL
direct,
#data
INSTRUCTION CODE
DESCRIPTION
BYTES CYCLES
0 7 0 6 Os 0 4 D~ O2 0, Do
1
(direct address) f- (direct
2
0 1 0 0 0 0 1 0
a7 as
XAL
XAL
A, Ar
A, direct
XAL
XAL
A,@Ar
A, #data
XAL
direct, A
0
0
a7 ae
17 Ie
as
15
1
1
as
1
1
Is
1
as
a4 a3 a2 a,
14 13 12 I,
0 1 r2 r,
0 0 1 0
~ a3 a2 a
0 0 1 1
0 0 1 0
14 13 12 I,
0
0
1
1
a7
as
0
0
1
17
0
1
Ie
1
a7_~
XAL
direct,
#data
a5~a3a2a
1
0
0
a7
17
0
~
1
1
as
0
as
Is
~
Is
14
0
0
0
0
1
1
a3 a2
a,
0 0 1
a3 a2 a,
13 b I
an
1
ao
MOV
MOV
Ar, #data
IlL
0
1
17
16
1
I~
Ik
1
14
1
1
Is
direct,
1
0
+-data
a7
as ~
b Is Is 14
@Ar, #data 0 1 1 1
a7 as as ~
DPTA,
1 0 0 1 0 0
#data 16
I,s 1'4 1,3 1'2 I" 110
Iz Is l!i 104 hl2
as
MOV
MOV
1112 I,
1 r2 r,
13 12 I,
0 1 0
a3 a2 a,
b b I
0 1 1
a3 a2 a,
ANL
OAL
OAL
MOV
MOV
C,Ibit
C, bit
C,/bit
C, bit
bit, C
b, b6
1 0
b7 bs
0 1
b7 bs
1 0
b7 bs
1 0
b7 bs
1 0
b7 be
bs b4
1 1
b~ b
1 1
bs b4
1 0
bs b
1 0
bs b 4
0 1
bs b 4
0
0
b~
b?
1
1
2
1
0
2
1
1
3
2
2
1
(A) +- #data
2
1
(Ar) +- #data
3
2
(direct address) +- #data
2
1
(Ar) +- #data
3
2
(DPTA) +- #data 16
1
1
1
1
1
1
1
1
1
0
2
2
(C) +-1
(C) f-(C)
(C) +- (C) AND (bit address)
2
2
(C) +- (C) AND (bit address)
2
2
(C) +- (C) OA (bit address)
2
2
(C) +- (C) OA (6ff address)
2
1
(C) +- (bit address)
2
2
(bit address) f- (C)
ao
ao
10
ro
10
1
ao
10
ro
ao
0
0
0
0
0
0
0
b?
b,
1
b,
1
b,
bn
0
0
b3
b2
fCl +- 0
bn
b~
0
I
bo
bn
b2
(direct address) +- (direct
address) XOA (A)
(direct address) +- (direct
address) XOA #data
10
0
0
jA) +- (A) XOA ((Ar»
(A) f- XOA #data
10
b,
0 0 1
b~ b? b,
b3
(A) +- (A) XOA (Ar)
(A) f- (A) XOR (direct address)
0
Is
In
b3 b2 b t
1
1
1
0
h
address) OR (A)
(direct address) f- (direct
address OA #data
2
19
CARRY FLAG OPERATION INSTRUCTIONS
CLA
1 1 0 0 0 0 1
C
SETB C
1 1 0 1 0 0 1
CPL
1 0 1 1 0 0 1
C
C, bit
1 0 0 0 0 0 1
ANL
2
10
ro
1
ao
ro
IMMEDIATE DATA SETTING INSTRUCTIONS
MOV A, #data
0 1 1 1 0 1 0 0
Iz
3
0
bn
0
bn
6-125
--iilu
------------________________
83C154~3C154D
____________________________
INSTRUCTION SET DETAILS (CONT.)
INSTRUCTION
D7 D6 D5 D4 D3
BIT OPERATION INSTRUCTIONS
SETB bit
1 1 0 1 0
b 7 b6 b s b 4 b3
CLR
bit
1 1 0 0 0
b 7 b6 b s b4 b3
CPL
bit
1 0 1 1 0
b 7 b s b s b4 b3
DATA TRANSFER INSTRUCTIONS
MOV A, Rr
1 1 1 0 1
MOV A, direct
1 1 1 0 0
a7 a6 as a4 a3
MOV A, @Rr
1 1 1 0 0
1 1 1 1 1
MOV Rr, A
MOV Rr, direct
1 0 1 0 1
a7 a6 as a4 a3
MOV direct, A
1 1 1 1 0
a7 a6 as a4 a3
MOV direct, Rr
1 0 0 0 1
a7 a6 as a4 a3
MOV direct 1,
1 0 0 0 0
direct 2
a~ a~ a~ a~ a~
MNEMONIC
CODE
D2 D1 Do
CYCLES
2
1
(bit address) <- 1
2
1
(bit address) <- 0
2
1
(bit address) <- (bit address)
1
2
1
1
(A) <- (Rr)
(A) <- (direct address)
1
1
1
1
0 1 0
b2 b 1 ba
0 1 0
b2 b 1 ba
0 1 0
b2 b ba
r2
1
a2
1
r2
r2
a2
1
a2
r2
a2
1
rl
0
al
1
rl
rl
al
0
al
rl
al
0
ra
1
aa
ro
ra
ra
2
2
(A) <- «Rr))
(Rr) <- (A)
(Rr) <- (direct address)
aa
1
aa
2
1
(direct address) <- (A)
ra
2
2
(direct address) <- (Rr)
3
2
(direct address 1) <- (direct
address 2)
2
2
(direct address) <- «Rr»
1
2
1
2
«Rr)l <- (A)
«Rr» <- (direct address»
1
2
(A) <- «A) + (DPTR»
1
2
(PC) <- (PC) + 1
(A) <- «A) + (PC))
1
2
1
1
(A)
(A)
1
1
1
1
(Al
«Rr»
(Ao - 3)
«Rro - 3))
aa
1
2
a~ a~ a a
a~ a~ a~ a1 a1 ai a~ a6
MOV direct, @Rr 1 0 0 0 0 1 1 ra
a7 a6 as a4 a3 a2 al aa
1 1 1 1 0 1 1 ra
MOV @Rr,A
MOV @Rr,direct 1 0 1 0 0 1 1 ra
a7 as as a4 a3 a2 al aa
CONSTANT CODE INSTRUCTIONS
MOVC A, @A
1 0 0 1 0 0 1 1
+ DPTR
MOVC A, @A + PC 1 0 0 0 0 0
1 1
DATA EXCHANGE INSTRUCTIONS
XCH
A, Rr
1 1 0 0 1
XCH
A, direct
1 1 0 0 0
az as as a4 a3
A, @Rr
XCH
1 1 0 0 0
XCHD A, @Rr
1 1 0 1 0
r2
1
a2
1
1
r1
0
al
1
1
DESCRIPTION
BYTES
ra
1
aa
ra
ra
6-126
(Rr)
(direct address)
---------------------------83C154~3C154D
___________________________
INSTRUCTION SET DETAILS (CONT.)
INSTRUCTION CODE
0 6 0 5 0 4 D~ O2 0 , Do
SUBROUTINE INSTRUCTIONS
MNEMONIC
PUSH direct
BYTES
CYCLES
2
2
0
2
2
ao
1
Ao
2
2
3
2
~
1
a7
1
a7
A10
A7
1
a6
1
a6
Ag
A6
0
0
a4 a3 a2 a1
0 1 0 0 0
as a4 a3 a2 a1
As 1 0 0 0
As A4 A3 A2 A1
ao
0
0
0
RET
0
0
1
0
0
0
1
0
1
2
RETI
0
0
1
1
0
0
1
0
1
2
2
2
POP
direct
ACALL addr 11
0
0
0
0
as
DESCRIPTION
(SP) ~ (SP) + 1
«SP» ~ (direct address)
(direct address) ~ «SP))
(SP) ~ (SP) - 1
(PC) ~ (PC) + 2
(SP) ~ (SP) + 1
«SP» ~ (PCo - 7)
(SP) ~ (SP) + 1
«SP)) ~ (PCs - 1S)
JPGrL -~~~-...1JL
LCALL addr 16
1 0 0
1 0
A 1S A14 A13 A12 A11 A10 Ag As
A7 A6 As A4 A3 A2 A1 Ao
(PC) ~ (PC) + 3
(SP) ~ (SP) + 1
«SP» ~ (PCo - 7)
(SP) ~ (SP) + 1
«SP» ~ (PCs - 1S)
(PCo - 15)~ ~--1.5.
(PCs - 1S) ~ «SP»
(SP) ~ (SP) - 1
(PCo - 7) ~ «SP»
• (spi ~·iSP)-1
(PCs - 15) ~ «SP»
(SP) ~ (SP) - 1
(PCo - 7) ~ «SP))
. (SPi ~(SP)-1
JUMP INSTRUCTIONS
A10 Ag As 0 0 0 0 1
A7 A6 As A4 A~ A, A f!..o
LJMP addr16
0 0 0 0 0 0 1 0
A1s A14 A13 A12 A11 A 10 Ag As
A7 As As A4 A3 A2 A Ao
SJMP rei
1 0 0 0 0 0 0 0
R7 Rs Rs ~ R3 R2 R1 Ro
JMP
@A+DPTR 0 1 1 1 0 0
1 1
AJMP addr11
(PC) ~ (PC) + 2
JPGrL - 10l ~ f!..u - .1!L
3
2
2
2
1
2
(PCo - 15) ~ Ao - 15
(PC) ~ (PC) + 2
I- 0 or (Rr) < 0
THEN
(PC) ~ (PC) + relative offset
(PC) ~ (PC) + 3
(direct address) ~ (direct
address) - 1
IF
(direct address) '" 0
THEN
(PC) ~ (PC) + relative offset
(PC) ~
+2
IF
A) ",0
THEN
(PC) ~ (PC) + relative offset
(PC) ~ ~PC) + 2
IF
A) ",0
THEN
(PC) ~ (PC) + relative offset
(PC) ~ ~PC) + 2
IF
C) = 1
THEN
(PC) ~ (PC) + relative offset
(PC) ~ ~PC) + 2
IF
C) = 0
THEN
(PC) ~ (PC) + relative offset
(PC) ~
+3
IF
bit address) = 1
THEN
(PC) ~ (PC) + relative offset
(PC) ~ ~PC) + 3
IF
bit address) = 0
THEN
(PC) ~ (PC) + relative offset
(PC) ~ rC) + 3
IF
bit address = 1
THEN bit addressl
0
(pcl ~ (PC) + relative offset
ELSE
DJNZ
Rr, rei
1 1 0 1 1 r2 r, ro
R7 Rs Rs R4 R3 R2 R, Ro
2
2
DJNZ
direct, rei
1 1 0 1 0 1 0 1
a7 as as a4 a3 a2 a, ao
R7 Rs Rs R4 R3 R2 R, Ro
3
2
JZ
rei
0 1 1 0 0 0 0 0
R7 Rs Rs R4 R3 R2 R, Ro
2
2
JNZ
rei
0 1 1 1 0 0 0 0
R7 Rs Rs R4 R3 R2 R, Ro
2
2
JC
rei
0 1 0 0 0 0 0 0
R7 Rs Rs R4 R3 R2 R, Ro
2
2
JNC
rei
0 1 0 1 0 0 0 0
R7 Rs Rs R4 R3 R2 R, Ro
2
2
JB
bit, rei
0 0 1 0 0 0 0 0
b7 bs bs b4 b3 b2 b, bo
R7 Rs Rs R4 R3 R2 R, Ro
3
2
JNB
bit, rei
0 0 1 1 0 0 0 0
b7 bs b s b 4 b3 b2 b, b o
R7 Rs Rs R4 R3 R2 R, Ro
3
2
JBC
bit, rei
0 0 0 1 0 0 0 0
b7 bs bs b4 b 3 b2 b, b o
R7 Rs Rs R4 R3 R2 R, Ro
3
2
6-128
tC)
tC)
~
___________________________ 83C154/83C154D ___________________________
INSTRUCTION SET DETAILS (CONT.)
INSTRUCTION
MNEMONIC
D7 D6 Ds D4 D3
EXTERNAL MEMORY INSTRUCTIONS
MOVX A, @Rr
1 1 1 0 0
MOVX A, @DPTR 1 1 1 0 0
CODE
D2 D1 Do
BYTES
CYCLES
0
0
1
0
ro
1
1
2
2
(A)...- ((Rr)) EXTERNAL RAM
(A)...- ((DPTR)) EXTERNAL
0
0
1
ro
0
0
1
1
2
2
(Rr) ...- (A) EXTERNAL RAM
((DPTR)) ...- (A) EXTERNAL
0
DESCRIPTION
RAM
MOVX @Rr, A
MOVX @DPTR, A
1
1
1
1
1
1
1
1
0
0
RAM
OTHER INSTRUCTIONS
NOP
0 0
0
0
0
0
0
0
6-129
1
1
(PC) ...- (PC) + 1
----________________________
83C15~83C154D
____________________________
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS·
*NOTlCE: Stresses at or above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and
functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device
reliability.
Ambient Temperature Under Bias:
C = commerciaL ................................... O'C to 70°C
I = industrial ............................... - 40°C to + 85'C
Storage Temperature .................... :- 65°C to + 150°C
Voltage on Vee to Vss ........................ - 0.5 V to + 7 V
Voltage on Any Pin to Vss ........ - 0.5 V to Vee + 0.5 V
Power Dissipation .......................................... 200 mW
DC CHARACTERISTICS
(TA = - 40"C to 85"C ; VCC
SYMBOL
= 5 V ± 10% ; VSS = 0 V ; F = 0 to 16 MHz)
PARAMETER
MIN
MAX
UNIT
-0.5
0.2 VCC
- 0.1
V
VIL
Input Low Voltage
VIH
Input High Voltage
(Except XTAL and RST)
0.2 VCC VCC + 0.5
+ 0.9
V
VIH1
Input High Voltage (RST and XTAL 1)
0.7 VCC VCC + 0.5
V
VOL
Output Low Voltage
(Ports 1, 2, 3)
VOL1
Output Low Voltage Port 0, ALE, PSEN
VOH
Output High Voltage Ports 1, 2, 3
VOH2
Output High Voltage Port 1, 2, 3 IZC
VOH1
Output High Voltage (Port 0
(port 0, ALE, PSEN)
=1
V
10L
0.45
V
!lA
= 3.2 mA (note 3)
= -10!lA
10H = 25!lA
10H = - 60!lA
vcc = 5 V ± 10 %
10H = - 2.5 !lA
10H = - 80!lA
10H = - 300 !lA
10H = - 800 !lA
vcc = 5 V ± 10 %
Vin = 0.45 V
±10
!lA
0.45 < Vin < VCC
-650
!lA
Vin
50
!lA
V
vcc
V
2.4
V
0.75 VCC
V
0.9 VCC
V
0.75
vcc
V
2.4
ilL
Logical 0 Input Current Ports 1, 2, 3
= 1.6 mA (note 3)
0.45
0.9 VCC
0.75
TEST CONDITIONS
V
C I-50
10L
10H
I 1-60
III
Input Leakage Current (Port 0, EA)
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2, 3)
IPD
Power Supply Current
(Power Down Mode)
RRST
= 2.0 V
vcc = 2.0
V to 5.5 V
(note 2)
150
kQ
CIO
Capacitance of I/O Buffer
10
pF
fc
ICC
Power supply current
Active mode 16 MHz
Idle mode 16 MHz
32
9
mA
mA
(notes 1,2)
RST Pulldown Resistor
50
= 1 MHz,
TA
= 25°C
Note 1 :
ICC max is given by :
Active mode: ICCMAX = 2 x FREQ + 4
Idle Mode: ICCMAX = 0.5 x FREQ + 2
i1I1iM IS
where FREQ is the external oscillator frequency in
MHz. ICCMAX is given in mAo See figure 1.
See figures 2 through 5 for ICC test conditions.
6·130
---------------------------83C154~3C154D
___________________________
DC CHARACTERISTICS (AUTOMOTIVE)
(TA = - 40'C to + 125'C ; VCC
SYMBOL
= 5 V ± 10 % ; VSS = 0 V)
PARAMETER
MIN
MAX
UNIT
-0.5
0.2 VCC
-0.1
V
Vil
Input low Voltage
VIH
Input High Voltage
(Except XTAl and RST)
0.2 VCC VCC + 0.5
+ 0.9
V
VIH1
Input High Voltage (RST and XTAl1)
0.7 VCC VCC + 0.5
V
VOL
Output low Voltage
(Ports 1, 2, 3)
VOL1
Output low Voltage Port 0, ALE, PSEN
VOH
Output High Voltage Ports 1, 2, 3
VOH1
0.45
Output High Voltage (Port 0
(Port 0, ALE, PSEN)
0.45
=1
2.4
V
0.9 VCC
V
vcc
V
V
Output High Voltage Port 1, 2, 3 IZC
logical 0 Input Current Ports 1, 2, 3
-75
Input leakage Current (Port 0, EA)
logical 1 to 0 Transition Current
(Ports 1, 2, 3)
IPD
Power Supply Current
(Power Down Mode)
= 3.2 mA (note 3)
= -10 IlA
10H = 251lA
10H = -60 IlA
VCC = 5V± 10 %
10H = -80 IlA
10H = - 300 IlA
10H = - 800 IlA
vcc = 5V± 10 %
10H = - 2.5 IlA
Vin = 0.45 V
V
III
III
V
0.75 VCC
VOH2
ITl
10l
V
2.4
0.75 VCC
= 1.6 mA (note 3)
V
0.9 VCC
0.75
TEST CONDITIONS
V
10l
10H
±10
IlA
IlA
0.45 < Vin < VCC
-750
IlA
Vin
75
IlA
VCC = 2.0 V to 5.5 V
(note 2)
= 2.0 V
150
kQ
CIO
Capacitance of I/O Buffer
10
pF
fc
ICC
Power supply current
Active mode 12 MHz
Idle mode 12 MHz
28
8
mA
mA
(notes 1, 2)
RRST
RST Pulldown Resistor
50
= 1 MHz, TA = 25°C
Note 2 :
Note 3 :
ICC is measured with all output pins disconnected;
XTAl1 driven with TClCH, TCHCl = 5 ns, Vil =VSS +
.5 V, VIH = VCC - .5 V ; XTAl2 N.C. ; EA = RST =
Port 0 = VCC. ICC would be slightly higher if a crystal
oscillator is used. Idle ICC is measured with all output
pins disconnected; XTAl 1 driven with TClCH, TCHCl
= 5 ns, Vil = VSS + .5 V, VIH = VCC - .5 V ; XTAL2
N.C. ; Port 0 = VCC ; EA = RST = VSS.
Power Down ICC is measured with all output pins disconnected; EA = PORT 0 =VCC; XTAl2 N.C. ; RST =
VSS.
Capacitance loading on Ports
and 2 may cause
spurious noise pulses to be superimposed on the VOlS
of ALE and Ports 1 and 3. The noise is due to external
bus capacitance discharging into the Port 0 and Port 2
pins when these pins make 1 to 0 transitions during bus
operations. In the worst cases (capacitive loading
100 pF), the noise pulse on the ALE line may exceed
0.45 V with maxi VOL peak 0.6 V.A Schmitt Trigger use
is not necessary.
a
6-131
------______________________
83C154~3C154D
____________________________
vee
5O.---"T-"--.----.-----.
401----1---1---+---1
t 30 I---+--+---t-~'-i
1
==
MAX
Figure 2: ICC Test Condition, Idle Mode.
~m~-+--~~r-~
All other pins are disconnected.
YCC
10 I------.,¥--+---f---I MAX
YCC
IDLE
MODE
0'----"-----''----'----'
4MHz 8 MHz 121M& 16 MHz
(NC)
~
X1l\l.2
XTN..1
\ISS
Figure 1 : ICC vs. Frequency. Valid only within fre-
quency specifications of the device under
test.
Figure 3 : ICC Test Condition, Active Mode.
All other pins are disconnected.
Figure 4 : Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.
lIST
X1l\l.2
XTN..1
\ISS
Figure 5 : ICC Test Condition, Power Down Mode. All other pins are disconnected.
6-132
--------------------________ 83C154m3c154D ____________________________
EXTERNAL CLOCK DRIVE CHARACTERISTICS (XTAL1)
SYMBOL
VARIABLE CLOCK
FREQ = 0 to 16 MHz
PARAMETER
UNIT
1/TCLCL
Oscillator Frequency
TCHCX
High Time
MIN
62.5
20
MAX
TCLCX
Low Time
20
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
ns
ns
ns
'S3C154-1fSOC154-1 versions only.
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
A.C. PARAMETERS:
TA = O'C + 70'C ; Vss = 0 V; Vcc = 5 V ± 10% (commercial).
TA = -40'C + 85'C; Vss = 0 V; Vcc = 5 V ± 10 % (industrial).
(Load Capacitance for port 0, ALE, and PSEN = 100 pf ; Load Capacitance for All Other Outputs = 80 pf).
SYMBOL
TLHLL
TAVLL
PARAMETER
MIN
ALE Pulse Width
Address Valid to ALE
TCLCL-40
TLLAX
Address Hold After ALE
TCLCL-35
TLLlV
ALE to Valid Instr in
TLLPL
ALE to PSEN
TPLPH
PSEN Pulse Width
TPLIV
PSEN to Valid Instr in
TPXIX
Input Instr Hold After PSEN
TPXIZ
Input Instr Float After PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid Instr in
TPAZ
PSEN Low to Address Float
MAX
UNIT
ns
ns
4TCLCL-100
ns
2TCLCL-40
ns
TCLCL-40
ns
3TCLCL-45
ns
3TCLCL-105
ns
ns
0
TCLCL-15
ns
5TCLCL-105
ns
10
ns
TCLCL-8
ns
ns
TRLRH
RD Pulse Width
6TCLCL-100
TWLWH
TLLAX
WR Pulse Width
6TCLCL-100
ns
TCLCL-35
ns
TRLDV
RD to Valid Data in
TRHDX
Data Hold After RD
Data Address Hold After ALE
5TCLCL-165
ns
ns
0
TRHDZ
Data Float After RD
2TCLCL-70
ns
TLLDV
ALE to Valid Data in
8TCLCL-150
TAVDV
Address to Valid Data in
9TCLCL-165
ns
ns
ns
TLLWL
ALE to WR or RD
3TCLCL-50
TAVWL
Address to WR or RD
4TCLCL-130
ns
TCLCL-60
ns
TOVWX
Data Valid to WR Transition
TOVWH
Data Setup to WR High
TWHOX
Data Hold After WR
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
7TCLCL-150
ns
TCLCL-50
ns
TCLCL-40
6-133
3TCLCL+50
0
ns
TCLCL+40
ns
____________________________
83C15~83C154D
____________________________
AC PARAMETERS:
TA = - 40'C to + 125'C ; Vss = 0 V ; Vee = 5 V ± 10 % (Automotive)
SYMBOL
PARAMETER
MIN
MAX
UNIT
2TCLCL-55
ns
Address Valid to ALE
TCLCL-70
ns
TLLAX
Address Hold After ALE
TCLCL-35
TLLlV
ALE to Valid Instr in
TLHLL
ALE Pulse Width
TAVLL
TLLPL
ALE to PSEN
TPLPH
PSEN Pulse Width
TPLIV
PSEN to Valid Instr in
TPXIX
Input Instr Hold After PSEN
TPXIZ
Input Instr Float After PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid Instr in
TPAZ
PSEN Low to Address Float
ns
4TCLCL-115
TCLCL-55
ns
ns
ns
3TCLCL-60
3TCLCL-120
ns
ns
0
TCLCL-40
ns
ns
TCLCL-8
5TCLCL-120
25
ns
ns
TRLRH
RD Pulse Width
6TCLCL-100
TWLWH
WR Pulse Width
6TCLCL-100
ns
TCLCL-50
ns
TLLAX
Data Address Hold After ALE
TRLDV
RD to Valid Data in
TRHDX
Data Hold After RD
TRHDZ
ns
5TCLCL-185
ns
Data Float After RD
2TCLCL-85
ns
ns
0
TLLDV
ALE to Valid Data in
8TCLCL-170
ns
TAVDV
Address to Valid Data in
9TCLCL-185
ns
TLLWL
ALE to WR or RD
3TCLCL-65
TAVWL
Address to WR or RD
4TCLCL-145
TQVWX
Data Valid to WR Transition
TQVWH
Data Setup to WR High
TWHQX
Data Hold After WR
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
3TCLCL+65
TCLCL-75
ns
7TCLCL-150
ns
ns
TCLCL-65
TCLCL-65
6-134
ns
ns
0
ns
TCLCL+65
ns
----------__________________
83C154~3C154D
____________________________
AC TIMING DIAGRAMS
EXTERNAL PROGRAM MEMORY READ CYCLE
~-----------------------12~----------------------~~
TlHLL_......._ _·
ALE---I
INSlR IN
NJ.R
POm"O INSTR IN
ADDR6SS
AOORESS AB-A15
ACORESS AB-A15
FIQFII' 2 OR SFR-P2 .
EXTERNAL DATA MEMORY READ CYCLE
1WHLH •
"
ALE
PORrO
PCRT2
lU.DV
_ _ TUlM.._
--
llQ/WL
---TU.AX~
1l\\/D\I
TRUIH
"
TJHll(
DO<
I
>
AIlIBS
ORSfR-P2
TAHDZ
j
___ llUlY_
....
...
OIID\ IN
.L.. TRLAZ
I
ADDI&S A&-A15 OR SFR-P2
I
r
lWHUI
"'-
ALE
~
I'
~TUlM.._
'TWIWH
/
llWWL---;:r-.l'
'-1ll.AX
. '::;'::::;-TDVWlC
PORrO
>--<
NJ-R
rMiQX-!
OOAOUT
I
I
AIlIHSS
ORSFR-P2
PCRT2
)
AIlOIeS A&-A15 OR !I'R-P2
6-135
;
___________________________
83C15~83C154D
___________________________
AC TESTING INPUT/OUTPUT, FLOAT WAVEFORMS
=X
INPUT 10Ull'UT
Y
YCC-Cl,5
~Y
)C
o.2lb:-Q.9
~O~2~1b:~-O~)
~-------~'-------.~
_-o,w
__________
AC inputs during testing are driven at Vee - 0.5 for a logic "1" and 0.45 V for a logic "0". Timing measurements are
made at VIH min for a logic "1" and VIL max for a logic "0". For timing purposes a port pin is no longer floating when
a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOHIVOL
level occurs. 101/10H 2: ± 20 mAo
SERIAL PORT TIMING· SHIFT REGISTER MODE
SYMBOL
MIN
PARAMETER
MAX
UNIT
12TCLCL
j.IS
Output Data Setup to Clock Rising Edge
10TCLCL-133
Output Data Hold after Clock Rising Edge
2TCLCL-117
ns
ns
TXLXL
Serial Port Clock Cycle Time
TQVXH
TXHQX
TXHDX
Input Data Hold after Clock Rising Edge
TXHDV
Clock Rising Edge to Input Data Valid
ns
0
10TLCL-133
ns
SHIFT REGISTER TIMING WAVEFORMS
INSJRUCTION
I
2
0
8
6
"
3
QflCK
I--~ITXHOX
D
OUIFUI' ......
...,.......
wmElOSIlF
\
0
X
X
2
X
3
X
4
~~J~ma
X
:x
G
X
,I
IlET1I
N'UTDATA
A
SETAl
a.EAAII
EXPLANATION OF THE AC SYMBOLS
Example:
Each timing symbol has 5 characters. The first character is always a "T" (stands for time). The other characters, depending on their positions, stand for the name
of a signal or the logical status of that signal. The following is a list of all the characters and what they stand
for.
TAVLL =Time for Address Valid to ALE low.
TLLPL = Time for ALE low to PSEN low.
A
C
D
H
I
L
P
Q:
R:
T:
V:
W:
X :
Z:
:
:
:
:
:
:
:
Address.
Clock.
Input data.
Logic level HIGH.
Instruction (program memory contents).
Logic level LOW, or ALE.
PSEN.
6·136
Output data.
READ signal.
Time.
Valid.
WRITE signal.
No longer a valid logic level.
Float.
----________________________
83C154~3C154D
____________________________
CLOCK WAVEFORMS
INIBINAL
rua
I ~I~ I ~I~ I ~I~ I ~I~ I ~I~ I ~I~ I ~I~ I ~I~ I
SIlITE
4
SIlITE 5
SIlITE 6
SIlITE 1
SOOE 2
SllIIE3
SWE 4
SIl\TE 5
XlAL2
~'
ALE
"--......;.._...1
PCLOOT
PCLOOT
I..
I
THESE SIGNALS ~ NOT
ACTMIIIED CURING THE
EXEaII10N OF A MO\IX INS1RJCIION
I
t
I
I-
~(EXTl
~
m
-------------------,
OOH IS EIMTTED
P2
WBl!ECVQE
PCLOUT(IF PRClGRi\M
---~1lPL0UT~OR=-RlOURINGJ!::!:T:E~===~FI..ClAr~8~=~.TTL
OR
I
INIlICAI'ES DPH
P2 SFRlO POI 11WG1IONS
WR
I MEMOIII'IS
Pi.:LOUT(EVBI FPRClGRi\M
INTBWAI..I
PO
P2
PQR[0PBlIIIJ0N
'-'-5I\C
-.~.
MOVDESrPalr(~.P2.P3)
(INaUlESlITo.IIT1.To.Tl)
SB!W.POI!TSHFTaDCK
I-
OlD DA1l\ NEW DA1l\
1=.:I
MO¥DESrPl _ _ _...
PI PlNSSANPLa>
~
ApO!:-PlNS=:-:::-.m=:;;;~--------------...
'T'
. --------------------!~
Pl.
f. P~!.~ ~
~
P2.
_ P 3 PINS SAt.II'LED
.PlNSPI. .,..,...~
~O)--_ _ _ _ _ _......
,
RltD SIM'I£D
r
RltD SIIMPl.ID
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (TA = 25'C, fully loaded) RD
and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are
incorporated in the AC speCifications.
6-137
----------__________________ 83C15~83C154D---------------------------F
R
83C154DF
83C154D
83C154F
83C154
80C154
P
S
D
A
I
T
J
Temperature Range
blank: Commercial
I : Industrial
A : Automotive
-L
xxx
T
T
Part Number
83C 154 Rom 16 K x 8
83C154D Rom 32 K x 8
80C154 External Rom
83C154F/83C154DF:
Secret Rom Version
Package Type
P: Plastic
S: PLCC
D: Cerdip
R: LCC
J : J leaded LCC
F: Flat Pack
:R
-1
-1 : 16 MHz Version
- L : Low Power Supply
Customer Rom Code
(83C154/83C154D
only)
(commercial only)
6-138
Tape and Reel
-P-re-lim-i-na-ry-----
~'1i
MtS
----Se-p-te-m-be-r-1-g8-9
SOC752/S0C732
DATA SHEET
CMOS SINGLE-CHIP 8 BIT
KEYBOARD CONTROLLER
FEATURES
•
•
•
4 K BYTES "QUICK-ROM" (80C752 only)
256 BYTES RAM
7 HIGH CURRENT 1/0 FULLY CUSTOMIZABLE
(80C752 only)
• THREE 16-BIT TIMERS/COUNTERS
• INTERFACE FOR MECHANICAL AND RESISTIVE KEYBOARDS (82C752-M)
• INTERFACE FOR CAPACITIVE AND SWITCH
CAP KEYBOARDS (80C752-C)
•
•
•
•
•
•
•
•
•
•
•
•
COMPATIBLE WITH 80C52
N-KEY ROLLOVER COMPATIBLE
32 1/0 LINES
PROGRAMMABLE SERIAL PORT
6 INTERRUPT SOURCES
KEY PRESSED DETECTION
FULLYSTATICDESIGN
SAJI VI CMOS PROCESS
32 K DATA MEMORY SPACE
64 K PROGRAM MEMORY SPACE
POWER CONTROL MODES
IBMPC SOFTWARE ROUTINE (PCS52, PCK52)
DESCRIPTION
MHS's 80C752180C732 is a high performance 8-bit
single-chip microcontroller designed for keyboard applications. It is derived from the 80C52/80C32 and bear
all its internal features, (except the ROM size, the I/O
structure and addressing : refer to MHS's 80C521
80C32 data-sheet).
- the keypressed detection circuit,
- the 7 high current and fully customizable I/O of port 3
which allow the user to configure the circuit to fit a wide
range of keyboards arrays and to directly interface
with accesories like mouse, card reader, bar code
reader, LCD display, etc.
The 80C752/80C732 allows the user to build powerful,
cost effective, and flexible keyboard controllers for
mechanical or capacitive keyboards using only this
"single chip solution". This is achieved by :
The MHS 80C752/80C732 are manufactured using the
SAJI VI CMOS PROCESS and supplied in DIL 40 pins
(80C752 only) or PLCC44 pins packages.
- the on-chip analog interface for capacitive or
mechanical matrix,
6-139
MATRA MHS
80C752180C732
FUNCTIONAL BLOCK DIAGRAM
PGO-P07
PCO-PC!7
,.u.~~.u.,-
PeON
Ti!CON
SCON
THO
TLI
THe!
RCAP
PSEN
Al.E
EA
RST
TIMING
AND
CONTROL
saur
- -- - - - - -- - -- - - - - - - -,
TIIDD
TCON
TLD
TLC!
RCAPC!H
IE
IP
TMI
~~
..iE'"
~~
'"rT'T'TT"I"TT _________ ...J
PJO-PI7
P30-P37
6·140
8OC75218OC732
PIN CONFIGURATIONS 80C752-M/80C732-M
Vss
P1.0
P1.1
P1.2
P1.3
Vref
P1.4
P1.5
P1.6
P1.7
Reset
P3.0
P3.1
P3.3
P3.4
P3.5
P3.6
P3.7
XTAL2
XTAL1
vee
39
38
37
36
35
34
33
32
31
30
29
28
27
21
EA
PO.O
PO.1
PO.2
PO.3
PO.4
PO.5
PO.6
PO.7
ALE
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.D
..
w
rr:
>
..,
N
:I
;;: ;;: ;;: ;;: ;:
~ I:li
0
0
0
"!
~
f
1[
NC
P03
P1.4
PO.4
P1.S
PO.
Pl.6
PO.6
Pl.7
PO.!
Vssb
AL~
Rsr
t'SIoN
Pl.O
P2.7
Pl.l
PZ.6
P2.s
P3.3
P2.4
...
~
on
~
::l
Q.
....;
o.
~
<
l-
x
:t '"'">
I-
x
<>
N
..,
g
[[
~
fl! fl! fl!
I:li
[[
PIN CONFIGURATIONS 80C752-C/80C732-C
Vss
P1.0
P1.1
P1.2
P1.3
Iref
P1.4
P1.5
P1.6
P1.7
Reset
P3.0
P3.1
P3.3
P3.4
P3.5
P3.6
P3.7
XTAL2
XTAL1
vee
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
E.A.
PO.O
PO.1
PO.2
PO.3
PO.4
PO.5
PO.6
PO.7
ALE
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
INDEX
CORNER
~
...!!:
IL
<"!
;;:
N
Ii:
0
Ii:
Ii:
..
!:
0
0
>
q
"!
NC
PO.3
P1.4
PO.4
PO.s
Pl.6
PO.6
Pl.7
PO.l
Vssb
ALl
RST
I'5IoN
PaO
P2.7
Pal
P2.6
P3.2
P2.s
Pl.3
P2.4
"l
r"" '"
Q.
6-141
..... ...
Q.
~
~ I-~
l-
x
x
(/)
'">
q
N
0-
..,
fl!
oi
0-
oi
0-
80C752!8OC732
PIN DEFINITIONS AND FUNCTIONS
SYMBOL
P3.0-P3.1
P3.2*
P3.3-P3.7
P3.6
INPUT (I)
OUTPUT (0)
I/O
0
I/O
I/O
FUNCTION
Port3 is an 7 bit quasi-bidirectional port plus a 1-bit output port. For the
masked version (80C752), the input level (TTUCMOS) and the output
structure (totempole/open-drain) of all the I/O can be individualy selected by
mask during the processing. Port3 also contains the interrupt, timer, serial
port, key detection and memory strobe pins:
- P3.0 : RxO (serial input port)
- P3.1 : TxO (serial output port)
- P3.2 : INTO (key detection), output only
- P3.3 : INT1 (external interrupt)
- P3.4 : TO (timer 0 external input)
- P3.5 : T1 (timer 1 external input)
- P3.6 : WR (external data memory write strobe)
- P3.7 : RO (external data memory read strobe)
Xtal1
I
Input to the inverting amplifier that forms the oscillator. Receives the external
oscillator signal when an external oscillator is used.
Xtal2
0
Output of the inverting amplifier that forms the oscillator, and input to the
internal clock generator. This pin should be floated when an external oscillator
is used.
Vss
Ground (Ov).
P2.0 P2.7
I/O
Port2 is an 8 bit port. For the 80C732. Port2 emits the high-order address
during code fetches and external memory accesses. For the 80C752, Port2 is
an 8 bit port that can be used as a scanning output port. Port2 is also used for
the high order address and the control signals during program verification.
PSEN
0
The Program Store Enable output is a control signal that enables the external
program memory fetch operations. It is activated every six oscillator periods
except during to the bus during external data memory accesses. Remains high
during internal program execution.
ALE
0
Provides address latch enable output used for latching the adress into external
memory during normal operation. It is activated every six oscillator periods
except during an external data memory access at which time one ALE pulse is
omitted.
EA
I
When EA is held high, the CPU executes out of internal program memory
(unless the program counter exceeds 4096). When EA is held low, the CPU
executes only out of external program memory. EA must not be left floating.
EA is internally connected to Vcc in the 40 pins OIL package.
I/O
PortO is an 8 bit port. In the 80C732, PortO is only the multiplexed low-order
adress and data bus during accesses to external program or data memory.
For the 80C752, PortO is either an 8 bit output port, which can be used for
scanning output, or the multiplexed address and data bus, depending on the
state of GFO flag bit (see 80C752' structure). It is also used during code
program verification.
PO.0-PO.7
Vcc
Power supply (+ 5 V power supply).
Vss, Vssa,
Vssb
Reference Ground.
RST
I
A high level on this pin for two machine cycles while the oscillator is running
resets the device. An internal pull-down resistor permits Power-On reset using
only a capacitor connected to Vcc.
6-142
80C75218OC732
PIN DEFINITIONS AND FUNCTIONS (continued)
SYMBOL
INPUT (I)
OUTPUT (0)
P1.0-P1.3
P1.4-P1.7
I/O
I
Port1 is an 8 bit port. All bits can be programmed as analog inputs or
quasi bidirectional I/O, depending on the organization of the matrix. This
programmability is possible only for the masked version (80C752). Default
configuration is 8 bit analog input (80C732). P1-0 and P1.0, as
quasibidirectional I/O can also serve Timer2 as follow:
- P1.0 : T2 (external input to timer2)
- P1.1 : T2EX (timer2 external trigger input)
Vref
I
Reference voltage for the mechanical interface or reference current for the
capacitive interface: Vref set-up the value of the threshold of the resistive
switch of the key for P1.0 to P1.7 of the 80C752-M or 80C732-M.
Iref
I
Reference current for the capacitive interface: Iref sets up the value of the
threshold for the capacitive. Version: 80C752-C or 80C732-C.
FUNCTION
DEVICE DESCRIPTION
INTRODUCTOIN
PortO, and Port2 pins are the scanning outputs,
Port 1 'pins are the return lines of the matrix, Port 3' pins
are the high current 110.
The 80C752 is a microcontroller designed to be used
mainly in keyboards applications. The two different versions are:
Standard configuration:
- 80C752-M for mechanical keyboards
· direct contact
· resistive contact
The 80C732 do not offers any options on the I/O configuration.
The standard configuration is shown in the table 2
page 8.
- 80C752-C for capacitive keyboards
· switch capacitive
· capacitive
Custom configuration:
The 80C752 is also the masked version of the 80C732
which means that the ROM code is implemented on the
80C752 using a special mask. On this mask, MHS offers several options which allow the customer to personalize some I/O of Port1 and Port3 to eliminate the
" glue logic" around the 80C752.
They can be provided in :
ROMless version: 80C732 with standard Input/Output
port structure (see table 2 page 8),
MASKED ROM versions : 80C752 with customizable
Input levels and Output port structure (see table 1
page 7).
The first four 110 of Port1 (P1.0 to P1.3) can be individually selected as a quasi bi-directional port or as an
input line from the matrix.
80C752 OVERVIEW
Each of the 7 high current I/O of Port3 can be entirely
configured; this means that the input level can be
selected between CMOS or TTL and that the structure
of the output stage can be selected between open-drain
or quasi bi-directional.
This keyboard controller is derived from the MHS80C32
microcontroller and has the same instruction set than
the 80C51 processor family. It has been designed for
single-chip keyboard or control applications which use
a keyboard. The structure of the I/O ports, the interrupt
system and the I/O port addressing have been modified
for those types of applications.
The table 1 shows the characteristics of the I/O port of
the 80C752.
STRUCTURE
INPUT/OUTPUT PORTS
The structure of each port of the 80C752/80C732 is
quite different of the 80C52/80C32's. Let us consider
first the I/O structure of the 80C752 (80C752-C and
80C752-M).
ORGANIZATION
The Input/Output ports have been modified and specialized to do different functions related to the keyboard
control:
6-143
iiii'l1iiii
80C752180C732
The 80C752 can operate in two modes: the Keyboard
Purpose
controller Mode
and the General
Microcontroller Mode. The selection between these two
modes in done with GFO, general purpose flag 0 in
PC ON (*), power control register.
must be mapped at Address : FFFFh and FFFEh
respectively.
- in ROM version PORT 0 and PORT 2 are dedicated for the keyboard scanning output lines.
- When the Controller executes a MOVX instruction:
- no control signal si sent to PORT3 (this allows
the use of P3.6 and P3.7 as an 1/0 PORT)
- no Address Data are sent on PORT 0 and
PORT 2.
1) The Keyboard Controller Mode: in this mode, GFO
is set
- in ROMLESS version PORTO is a standard 80C52
AddresslData PORT, and PORT 2 is and Address/SFR Standard PORT.
When using external ROM, some dedicated glue is
necessary to recreat 1/0 PORT 0 and 2 (see figure 1). To have a complete software compatibility
between ROMESS version and ROM version configuration, these 2 new external PORT 0 and 2,
8
8OC732
Serial {
link
------1
2) The General Purpose Microcontroller Mode:
In this Mode GFO is reset, and all functions are working as a standard 80C52.
* Note : For more information, see MHS 80C51
user's manual.
PO
AoI7
AD
P2
A15
NJ A15
ALE.!5Si:R
110
A15
PSEN
VIm
EA
Note: The two scanning ports are mapped in the external memory spaced of address OFFFEh and OFFFFh
so that the software will be the same when switching to the ROMed controller.
Figure 1 : Keyboard Controller Mode in ROMLESS Version.
6·144
8OC75218OC732
1/0
FUNCTION
PO.0-PO.7
ADbus
or
scanning Out
P1.0-P1.3
1/0 port
P1.4-P1.7
or
scanning In
scanning In
P2.0-P2.7
Scanning Out
P3.0/RxD
High current
1/0
P3.11TxD
High current
1/0
P3.2/INTO
P3.3/1NT1
P3.41T0
Key-pressed
output Signal
High current
110
High current
1/0
P3.51T1
High current
1/0
P3.6/WR
High current
1/0
P3.7/RD
High current
1/0
STRUCTURE
# GFO
=
0 bidirectional ADbus
# GFO
=
1 scanning output: output Port
OPTION
Soft
Soft
Quasi bi-directional 1/0 with TTL input level
Mask
Input from resistive or capacitive matrix
Input from resistive or capacitive matrix
Mask
Scanning output: output port only
CMOS or TTL input level
Open-drain or quasi bi-directional
1/0 port - 10L = 10 mA @ 0.45 Volt
CMOS or TTL input level
Open-drain or quasi bi-directional
1/0 port - 10L = 12 mA @ 0.45 Volt
Output activated (at 0) when a key is pressed in the
scanned line.
CMOS or TTL input level
Open-drain or quasi bi-directional
1/0 port - 10L = 10 mA @ 0.45 Volt
CMOS or TTL input level
Open-drain or quasi bi-directional
1/0 port - 10L = 3.2 mA @ 0.45 Volt
can be used as an 17th scanning Out.
CMOS or TTL input level
Open-drain or quasi bi-directional
1/0 port - 10L = 10 mA @ 0.45 Volt
CMOS or TTL input level
Open-drain or quasi bi-directional
1/0 port - 10L = 10 mA @ 0.45 Volt
No WR pulse in single-chip mode
CMOS or TTL input level
Open-drain or quasi bi-directional
1/0 port - 10L = 10 mA @ 0.45 Volt
No RD pulse in single-chip mode
Table 1 : 80C752 (-M or -C version).
6-145
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Mask
80C752180C732
Port1 operation is the same as SOC752's. Port3' 110
lines operate as Port3 of SOC32.
SOC732's STRUCTURE
The SOC732 has no on-chip ROM; as the SOC32, it
uses PortO and Port2 to fetch opcodes and to access
external data memory (RAM or I/O port mapped in the
external memory space). But, as the chip has no
masked-ROM, no options are possible on Port1 and
Port2.
I/O
FUNCTION
PO.0-PO.7
ADbus
P1.0-P1.3
P1.4-P1.7
scanning In
P2.0-P2.7
Add bus
P3.0/RxD
High current
I/O
P3.1/TxD
High current
110
P3.2/INTO
P3.3/INT1
The table 2 shows the characteristics of the I/O port of
the SOC732.
Key-pressed
output signal
High current
I/O
P3.4/T0
High current
I/O
P3.5/T1
High current
I/O
P3.6/WR
High current
I/O
P3.7/RD
High current
I/O
STRUCTURE
Bidirectional ADbus
Input from resistive or capacitive matrix
AS-A 15 adress bus
TTL input level
quasi bi-directional
I/O port - 10L = 10 mA @ 0.45 Volt
TTL input level
quasi bi-directional
I/O port - 10L = 12 mA @ 0.45 Volt
Output activated (at 0) when a key is pressed in the
scanned line.
TTL input level
quasi bi-directional
I/O port - 10L = 10 mA @ 0.45 Volt
TTL input level
quasi bi-directional
I/O port - 10L = 3.2 mA @ 0.45 Volt
TTL input level
quasi bi-directional
I/O port - 10L = 10 mA @ 0.45 Volt
TTL input level
quasi bi-directional
I/O port - 10L = 10 mA @ 0.45 Volt
WR pulse during each WRITE instruction
TTL input level
quasi bi-directional
I/O port - 10L = 10 mA @ 0.45 Volt
RD pulse during each READ instruction
Table 2: SOC752 (-M or -C version).
iiii'Miiii
6-146
OPTION
8OC752/8OC732
MECHANICAL KEYBOARDS
80C7S2-M/80C732-M
THE ON-CHIP ANALOG INTERFACE
The operation of the mechanical keyboards is based on
the use of contacting switches. These switches can be
elastomer-dome, mechanical, membrane and snapdome; they rely on basically the same hardware and
software techniques.
The measurement is based on a voltage comparison
between the selected threshold voltage and the voltage
coming from the matrix:
The 80C752-M and the 80C732-M are designed to
directly interface these types of mechanical keyboards,
whatever the types of the contacting switches.
The output voltage from the matrix may depend on the
state of the non-scanned keys. The user must take this
into account when selecting the threshold voltage.
PRINCIPLE
-------------,
r-----------------I
I
Ronl
Roll
IOC752-t.4
Ronl
Roff
ROft/Rotf
Port 0
Port 2 scanni1g ouIput
Keyboard matrix
I
Vee
I
I
lf11( (MINI
I
I
I
I
I
I
I
I
IOC7SZ-M
1 it
RI~Ron
OifRI=RoIl
I
______ _
L~O~~~c~~_~_~J~
I
SWITCH ROLLOVER TECHNIQUES
diode is mandatory for keyboards with mechanical
switches.
Depending on the keyboard's technology and its application, designers can use several rollover or validation schemes (defined as the number of keys that the
keyboard circuit can process as closed in the correct sequence at the same time). The most common types of
roll-over in use today are N-key lockout, two-key rollover, three-key rollover, and N-key rollover.
SCANNING TECHNIQUE
The scanning consists of resetting one of the drive lignes high and reading the state of the voltage comparators. Only one output at a given time can be active
(low level) ; this means that between two different active
states.
The 80C752-M and the 80C732-M allow all these different schemes. The number of roll-over is determined
by the value of the ON-resistor and the presence of a
blocking diode.
- without blocking diode.
THRESHOLD SETTING
To accomodate different types of contacting switches,
the user can adjust the threshold voltage of the
80C752-M/80C732-M by adjusting the input voltage on
Vref pin.
If the ON-resistor is less than 2 kQ, 16 keys can be
pressed at the same time on a same column (16 Key
Rollover). To avoid risk of phantom key only one column
must be activated at the same time.
- with blocking diode.
KEY PRESSED DETECTION
The 80C752-M and the 80C732-M provide hardware
detection of a pressed key. This information (state of the
P3.2 pin) can be used as a flag (state read by software)
or as an interrupt source, if INTO is enabled. The state
of P3.2 is updated after the start of every new scanning;
this is the reason why INTO must be edge triggerred (bit
ITO in TCON must be set).
Adding a blocking diode at each switch location
eliminates phantom key closures and provides current
protection with low ON-resistor switches. This technique also enables the use of the N-key rollover scheme,
whatever the characteristics of the switch. The blocking
6-147
iiii'Mliii
80C752J80C732
DEVELOPMENT
EMULATION
The 80C752-M has been designed so that any program
developed forthe 80C732-M, with the two output scanning ports mapped at external memory addresses
OFFFEh and OFFFFh, can be exactly the same for the
80C752-M. This is the reason why PortO and Port2 of
the 80C752 are mapped in the SFR space and in the
external memory space.
For the software and/or hardware debugging, any
80C52 emulator can be used to emulate the 80C752-M,
but the user has to add some external "glue logic"
around the emulator probe to build the mechanical interface of the 80C752-M and the drivers integrated in
Port3 pins. Hereafter is the schematic of the mechanical
interface which must be added between the 8 outputs
from the matrix and the 8 pins of Port1 of the emulator:
r---
_~~!!l~~t~
rn~--~I---t~~----~I--r>
I
1/41C1
1
/---- ---------/
Cl
from
Mechanical
matrix
1
:
r----
1
1
1
1/41C1
I
--------""1
1
1---------
1------1
1
1
1----
P'l.l
to Por11
of
the80C52
1
------~
emulator
--------1
1
1
1
---------1
~~--~:~-J:1~----~I--C>
1
Pl.0
1/41C2
i
Pl.7
L___ ------J:.-...l
\b:
v ret 2 -= VSSa
1C1, IC2 : LM 339
oraJ4584
Figure 2 : Mechanical Interface Schematic.
6-148
8OC75218OC732
80C732-M EMULATION
mended to map these ports at the addressed OFFFEh
and OFFFFh because when going from ROM less to
ROMed version, the software will remain the same.
This is the complete emulation schematic:
For 80C732-M emulation, the user has to provide one
or two external ports, to be mapped in the external
memory space forthe scanning output port. It is recom-
8
16.8Kays
8
ror-----+-~~~+--L------~--~
MechanIcal
Interface
....- - - 1 p~.o
(See fig')
Pl.7
P32
~r-----------------~
ALE
1-___ ALE
P3.3
!-----Io_ WIt
!----PSm
A15 _ _ _-...J
f'SBil ____-...J
!
SeriaJ
link
Figure 3 : 80C732-M Emulation Schematic.
6-149
00...07
8OC752180C732
80C752-M EMULATION
memory addressing and also because this allows the
use of P3.6 as an 1/0.
For 80C752-M emulation, it is not useful to build the external output ports (and it is not recommended) because the SFR and bit addressing of the scanning ports
(PO and P2) is preferable when using the external
The below figure shows the complete emulation
schematic:
8
16x8Keys
8
8OC52/C32
Enwlator
Probe
Mechanical
po.O
Pl.0
Interface
P1.7
P32
P2.0
P2.7
LED's
'b::
Serial
link
PO.7
P3.3
P3.4
Pa5
P3.1
P3.6
P3.o
Figure 4 : 80C752-M Emulation Schematic.
IDLE AND POWER-DOWN OPERATION
r~
As shown in the below figure, the idle and power-down
modes are the same than with 80C51 (see MHS 80C51
user's manual). As illustrated, Power-down operation
stops the oscillator and idle mode operation allows the
interrupt, serial port, and timer blocks to continue to
function while the clock to the CPU is gated off.
XTAL.2
During power-down, the analog interface is poweredoff to minimize circuit power consumption. The only way
to escape from power-down mode is to reset the CPU.
During idle, if any key is pressed, P3.2 will fall down and,
if INTO is enabled, the CPU will escape from idle mode.
6-150
XTAL 1
8OC75218OC732
CAPACITIVE KEYBOARDS
80C7S2-C/80C732-C
THE ON-CHIP ANALOG INTERFACE
There are 2 types of capacitive keys: the full c?pacitive
type and the switch~capacitor type.
PRINCIPLE
The 80C752~C and the 80C732~C allow the N~Key rol~
lever technique; this means that they can detect a key
independently of the state of the other keys and of the
technology of the matrix (flexprint...).
The measurement is based on a constant current
charge of the capacitor of the key:
The 80C752~C and the 80C732~C are designed to
directly interface these two types of capacitive key~
boards, independently of the state of each capacitive
key.
-~-~
r---~--------------
-------~I
':Fe
I
I
I
I
I
I
"L:
B
A
I
I
I
8OC75Z·C
Porto
Z
!CP
Port 2 scamitg
~
I
I
I
______ J
I
CPl
-=-
I
I
I
I
L~~~ ~!'!~
Keyboard malril
At the falling edge of the scanning output, the voltage
at node B goes down below the regulation voltage of the
"zener ".
______ _
THRESHOLD SETTING
The formula which determines the operation of the
capacitive interface is :
The voltage decreasing virtually disconnect the
regulator and all the current from the current generator
goes to the capacitors.
Ct
So, the capacitors are charged with a constant current.
At the end of the process, the voltage value is the same
as before the falling edge; this means that Cp1 has no
influence on the time to charge Ct the capacitor of the
key:
t Va x Ct/lref => Ct (t x Iref)/Va
=
I
I
=
=(t x Iref)/Va
~
Ct, is the capacitor threshold value,
~
Va, which is the value of the voltage variation on the
scanning output, Vee ~ 0.5 V,
~
t, determines the moment when the output of the com~
parator is strobed (0 if the capacitor is recharged, 1 if
not recharged).
Iref, which is the value of the constant current driving Ct.
It can be adjusted by an extemal resistor. This allows
the 80C752~C and the 80C732~C to operate with dif~
ferent types of capacitive matrixes. Iref can be fixed with
only one resistor; the formula to select Iref is Iref =
(Vcc - 1.5 V}/R, where R is the value of the extemal
resistor.
The voltage driven technique on the node A eliminates
the influence of Cp2.
Cp1 and Cp2 have no influence on Ct measurement;
this allows the 80C752~C and the 80C732~C to be used
in design with N~key rollover technique. They can fit with
a wide range of capacitive matrices because the on~
chip hardware allows the selection of the capacitor
threshold value.
KEY PRESSED DETECTION
The 80C752~C and the 80C732~C provide an internal
hardware detection of pressed key. This signal is output
on P3.2 and internally connected to INTO. This informa~
tion (state of P3.2) can be used as a flag (state read by
software) or as an interrupt source, if INTO is enabled.
This is the reason why INTO must be edge triggered (bit
ITO in TCON must be set).
SCANNING TECHNIQUE
The scanning must be done with a rolling zero on the
scanning outputs (the other outputs remain high). Only
one output at agiven time can be active (low level) ; this
means that between two different active states all scan~
ning outputs must be desactivated.
6-151
iiii'Miiii
aOC75218Oc732
DEVELOPMENT
EMULATION
The 80C752-C has been designed so that any program
developed for the ROMless, with the two output scanning ports mapped at external memory address
OFFFEH and OFFFFh, can be exactly the same for the
80C752-C. This is the reason why PortO and Port2 of
the 80C752 are mapped in the SFR space and in the
external memory space.
For software and/or hardware debugging, any 80C52
emulator can be used to emulate the 80C752-C, but the
user has to add some external" glue logic" around the
emulator probe to build the capacitive interface of the
80C752-C and the drivers integrated in port3 pins.
Hereafter is the schematic diagram of the capacitive interface which mut be added between the 8 inputs from
the matrix and the 8 pins of Port1 of the emulator:
R
""·rL-~_~~~_r-_-_-,------------~
I
I
co~n
--DP1.o
.:P2
;-1
: r-----------------,~
: r-~~~~~~~~~~~~~~II
1
1
11
from
the
1
mabix
1
1
1
1
1
I
I
L ______________
IL ________________-'I
I
I
I
I
II
to Port 1
ofthe80C52
(emulator)
II
L ________________-'
I
I
l::>i
C6
I.
I
I
!-+-il-D P1.6
f~--~---~:~~
eT
L45
I
---I
I -I1-f--DP1.7
0 Qt-t---r-
Figure 5 : Capacitive Interface Schematic.
6-152
IC2 P7Q7
1C1,1C2:
lea
74 HCT688
LM741
IC4
74HCT74
IC5
LM741
IC6
74 Her 374
leT
LM319
8OC75218OC732
80C732-C EMULATION
mended to map these ports at the addresses OFFFEh
and OFFFFh because when going from ROM less to
ROMed version, the software will remain the same.
Here is the complete emulation schematic:
For 80C732-C emulation, the user has to provide one
or two external ports, to be mapped in the external
memory space for the scanning output port. It is recom-
8
16 x 8 Keys
8
1'0
~
P1.0
Interface
P1.7
P32
OO.D7
P2
P3.3
ALE
I
Serial
link
Figure 6 : 80C732-C Emulation Schematic.
6·153
80C752J80C732
80C752-C EMULATION
(PO and P2) is better than the external memory addressing and also because this allows the use of P3.6
(WR) as an 1/0. The below figure shows the complete
emulation schematic:
For 80C752-C emulation, there is no need to build the
external output ports. However it is not recommended
since the SFR and bit addressing of the scanning ports
8
8
8OC52/C32
Emulator
Probe
CapacHive
1'0.0
Pl.0
Interface
P1.7
P3.2
PO.7
P2.0
P2.7
lJ3)'s
\tc
Serial
P3.3
P3.4
P3.5
P3.1
P3.6
P3.0
P3.7
link
Figure 7 : 80C752-C Emulation Schematic.
IDLE AND POWER-DOWN OPERATION
r~
As shown in the figure below, the idle and power-down
modes are the same as for 80C51 (see MHS 80C51
user's manual). As illustrated, Power-down operation
stops the oscillator and Idle mode operation allows the
interrupt, serial port, and timer blocks to continue to
function while the clock to the CPU is gated off.
XTA1.2
During power-down the capacitive interface is powered-off to minimize circuit power consumption. P3.2
remains in the same state until a new scanning value
is sent; if any key is pressed during Idle or Power-down,
it will not change the state of P3.2 and the circuit will stay
in the same mode.
6-154
Xll\l1
8OC752J8OC732
SOFTWARE CONSIDERATIONS
retriggered at each new scan generation (i.e. after
the falling edge of a scan line) and for some microsecond only.
The 80C752 has been built to simplify the design of keyboards and thus allowing the user to concentrate on the
real problems such as keys organisation, type of matrix,
design of the keys and the box of the keyboard ...
So, the state of P3.2 and the data read in SFR Port1 do
not indicate at every moment the state of the scannedkeys.
As a result, only one software has to be written by the
user. The same software can be used for:
-
Design considerations:
ROM less devices,
ROMed devices,
mechanical or resistive matrixes,
capacitive matrixes.
The data in Port1, which should be normally strobed
3 I-ls after a new scan generation, are not strobed on
this design.
The consequences are:
Moreover MHS can also provide a masked version for
IBM-PC (*) compatible keyboards, the PCK52, and the
assembly source program of the PCK52, named
PCS52.
- P3.2 must not be used for software tests and for interrupt generation.
- The 31-ls delay must be done by software,
- During the active time of the scanning, all interrupts
must be masked to ensure that the 3 I-ls software
delay will be always the same.
- The data in SFR Port1 must be read immediatly after
the 3 Jls delay.
1. MECHANICAL OR RESISTIVE MATRIXES. The
scanning is based on the static level of each input:
at any moment, the state of P3.2 and the data read
in SFR Port1 indicate the real state of the scannedkeys.
3. EXAMPLE: Hereafter is an example of a scanning
routine which can be used for capacitive or resistive
matrixes and for ROMed or ROMless devices.
2. CAPACITIVE MATRIXES. The scanning is based on
the dynaic level of each input of the matrix : the
capacitor measurement until (integrated in Port1) is
(') IBM is a trademark of International Business Machine Corporation.
6·155
8OC752J8OC732
SCANNING_ROUTINE:
; ASSUME (R?, RS) CONTAINS THE
; SCANNING VALUE
SETB
MOV
RLC
MOV
MOV
CJNE
MOV
MOV
RLC
MOV
CJNE
MOV
C
A, RS
A
RS,A
PSW.S, C
A, #OFFH, SCAN_LOW
C, PSW.S
A, R?
A
R?,A
A, #OFFH, SCAN HIGH
RS, #OFEH
-
MOV
MOV
CLR
MOVX
NOP
NOP
MOV
JMP
A,RS
DPTR,#OFFFFH
IE.?
@DPTR,A
MOV
MOV
CLR
MOVX
NOP
NOP
MOV
TEST_DETECT:
SETB
CPL
JZ
KEY-DETECTED:
NO_KEY:
RET
A,R?
DPTR,#OFFFEH
IE.?
@DPTR,A
; DISABLE ALL IT
; SCAN: FALLING EDGE ON P2.X
A, P1
; 311S DELAY BETWEEN SCAN AND SENSE
IE.?
A
NO_KEY
; RE-ENABLES ALL IT
; ROLLING 0 THROUGH (R?, RS)
; STORE CARRY FLAG IN GF1
; DISABLE ALL IT
; SCAN: FALLING EDGE ON PO.X
A, P1
TEST_DETECT
; 311S DELAY BETWEEN SCAN AND SENSE
; TEST FOR PUSHED KEYS
; TEST FOR RELEASED KEYS
6-156
8OC75218OC732
PCK52
The PCK52 has been specially designed for IBM-PC
keyboards. It is supplied in 2 versions :
It can be used in PC-XT or PC-AT applications, depending of the state of switch 1 (SW1).
The Key-mapping is shown in table 3. The number
given in this table designates the keybutton position,
conforming to the IBM nomenclature for keyboards.
- PCK52-M for mechanical or resistive matrix,
- PCK52-C for capacitive matrix.
P1.7
Pl.0
Pl.1
P1.2
P1.3
P1.4
P1.5
P1.6
PO.O
0
0
0
0
0
0
0
0
PO.1
53
52
61
62
56
54
PO.2
47
60
46
45
58
44
51
50
49
PO.3
33
32
31
30
37
36
35
48
34
PO.4
19
18
17
16
23
22
21
20
PO.S
4
3
2
1
8
7
6
5
PO.6
0
0
0
SWl
0
0
0
0
115
PO.7
114
113
112
110
118
117
116
P2.0
0
0
0
0
0
0
0
0
P2.1
91
96
101
103
0
42
64
93
98
57
0
79
89
99
P2.2
41
40
39
38
P2.3
108
106
105
104
83
84
P2.4
90
95
100
102
86
85
27
26
25
24
81
76
92
43
97
P2.S
P2.6
12
11
10
9
80
75
15
13
P2.7
122
121
120
119
126
125
124
123
28
SWI : ON : PC-Xl, OFF: PC-AT3.
Table 3 : Key Mapping of PCK52.
PCK52 MASK OPTIONS:
Hereunder are described the Mask options of the actual version of PCK52 for Mechanical Keyboard: 80C752M.290.
80C752-M 290 MASK OPTIONS
KEYBOARD MATRIX
-or
MECHANICAL
PORT 1
SELECTIONS
Pl.0
Pl.l
110 port with
TTL input
YES
YES
CAPACITIVE
Pl.2
P1.3
Pl.4
Pl.5
Pl.6
P1.7
YES
YES
YES
YES
YES
YES
OUTPUT SELECTION
INPUT SELECTION
PORT 3
OPTIONS
TTL
(51 type)
C51 TYPE
(*)
CMOS
OPEN DRAIN
P3.0/RXD
YES
YES
10 mA (max)
P3.1/TXD
YES
YES
12 rnA (max)
P3.3/1NTl
YES
P3.4/T0
YES
10 rnA (max)
YES
YES
3.2 rnA (max)
P3.5/T1
YES
YES
10 rnA (max)
P3.6/WR
YES
YES
10 mA (max)
P3.7/RD
YES
YES
10 mA (max)
(0) : Quasi bi-dlrectlonnal high current @ 0.45 V.
6-157
8OC752180C732
The Hardware environment must be following:
~
PCK52
CI. ,,.
OV
U
..
x,
,L
•
aU""
X2
•
1:3
lIST
HUm
f5V
,y2IQ
T
IV
'VVV1kQ
IV
5V
r-----'
>
Ri
'~,
I~IDATA
.;;
~
-r==
....,---
, !--';-<
,GIll
I 10:
~~.J
EA
I ...
VREFO
VREF,
1'0.1
1'02
VSSA
VSS8
1'1"
SCANOIIfo
SCANOIIf ,
.,
r-
SCANOIIf'
SCANOIIf 3
SCAN OUT 4
'05
SCANOIIf'
SCANOIIf'
..
".t/RXIl
PU
1'3.111lD
1'2.1
1'22
1'2.3
1'2.4
1'25
1'2.6
1'2.7
f5V
PC_
a.,01m
SCAN INO
SCAN IN ,
SCANIN 2
SCANIH3
5CAN1N4
SCAN IN'
SCANII.
SCAN IN 7
I'U
1'0.6
1'0.7
116
..
SCAH0UT7
.(
: +>t--'a.""OCK=---*-+-------'
,~
flU
Pl.'
Pl2
Pl.'
Pl.4
Pl.5
Pl ••
Pl.7
'2IOIIz?"
.sV
.sV
<'~
P3.3
1'3.'
f5Vr-- 1'3.7
r - 1'3.4
.---
SCNfOllfa
SCAN0IIf9
SCNfOllf 11
SCM OUT 11
SCNfOllflZ
SCNf OUT 13
SCNfOUf14
SCANOUf15
SOC7S2MZ90
112 KEYS KE'tIJOARD
.sV
lIZ
01 ...
'v
113
f/~
CoVSlOQ(
lIZ ...
_UJC1(
fI~
R4
03 .....
flf'fI(
SCROllLOO<
Keyboard using scanning 1 method.
PCS52
The PSC52 is the assembly source of the PCK52 program.
- the default type of the keys:
• make/break,
• typematic.
- the type of the scanning:
• positive or negative.
This software, fully documented, allows to change the
main characteristics of a keyboard by modifing some
parameters in the assembly is the source program:
This source file, in 8051 assembly code is provided in
1 floppy (5 or 3 inches) for MS-DOS compatible PC.
- the key-mapping
- the 3 internal timings:
• the debounce time,
• the scanning rate,
• the auto-repeat rate.
6-158
8OC752/8OC732
APPLICATION EXAMPLES
1 . Keyboard controller for Personal Computer:
136 Keys Keyboard
17xS
L-_,,"s--1 P1
PO
'---'_-II ref
Pad Nit.m ScIaII Caps
lock lock lock Lock
1'3.4
8OC752lED's
't:........._ _- I P3.7
'-----<_-11'3.6
L - - - -__>---1P3.5
P3.t 1----4-+-_
110
PC
P3.0"'---~-
2. Keyboard controller with extemal EPROM:
In this configuration, the BOC752-C can control keyboards with up to 136 keys.
The following options must be selected in order to drive
the capacitive matrix and to comply with the DC
specifications of the serial link with the PC :
Input levels:
P3.0 and P3.1 : TTL (O.B V; 2.4 V), selected by mask
option.
Output structures:
P3.0, P3.1 : open drain, selected by mask option,
P3.4 : quasi bi-directional port, selected by mask option,
P3.3, P3.5, P3.7 : open drain, selected by mask option.
n
8
8OC732
Serial {
link
_-----(
P2
I/O
Note: The two scanning ports are mapped in the external memory space of address OFFFEh and OFFFFh so that the software
will be the same when switching to the ROMed controller.
6-159
aOC75218OC732
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS·
• NOTICE: Stresses at or above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and
functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device
reliability.
Ambient Temperature Under Bias:
Commercial ........................................... - O·C to 70·C
Storage Temperature ..................... - 65·C to + 150·C
Voltage on Vee to Vss .................... - 0.5 to Vee + 7 V
Voltage on any pin to Vss ......... - 0.5 V to Vee + 0.5 V
Power Dissipation .......................................... 200 mW
DC CHARACTERISTICS
TA = O·C to + 70·C; Vss
= 0 V; Vcc = 5 V ± 10 %
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
-0.5
0.2 Vcc
-0.1
V
Input High Voltage
(Except XTAL1 and RST)
0.2 Vcc
+0.9
Vee + 0.5
V
0.7 Vec
Vee + 0.5
0.45
V
VIL
Input Low Voltage
VIH
TEST CONDITIONS
VIHl
Input High Voltage (RST and XTAL 1)
VOL
Output Low Voltage (Ports 1, 2, 3)
V
10L
VOLl
Output Low Voltage Port 0, ALE, PSEN,
P3.4, Port 2
0.45
V
10L
= 1.6 mA (note 2)
= 3.2 mA (note 2)
VOL2
Output Low Voltage
P3.3, P3.5, P3.6, P3.7
0.45
V
10L
= 10 rnA (note 2)
VOL3
Output Low Voltage P3.0, P3.1
0.45
V
= 12 rnA (note 2)
10H = - 10 f.IA
10H = - 25 f.IA
10H = - 60 f.IA
Vee = 5 V± 10 %
10H = - 40 f.IA
10H = 150 f.IA
10H = - 400 f.IA
Vcc = 5 V ± 10 %
Vin = 0.45 V
VOH
VOHl
Output High Voltage Ports 1, 2, 3
Output High Voltage
(Port 0 in External Bus Mode, ALE,
PSEN)
V
0.9 Vee
0.75 Vee
V
2.4
V
0.9 Vee
V
0.75 Vee
2.4
V
V
ilL
Logical 0 Input Current Ports 1, 2, 3
-SO
III
Input Leakage Current (Port 0, EA)
± 10
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2, 3)
IPD
Power Supply Current
(Power Down Mode)
RRST
RST Pulldown Resistor
CIO
Capacitance of I/O Buffer
SO
VREF
Reference Voltage
1.0
RVREF
Source Impedance of VREF
1.0
IRef
Current reference for current minors
10
6·160
-650
f.IA
f.IA
f.IA
100
f.IA
150
kQ
10
pF
Vec -1.0
500
10L
0.45 < Vin < Vee
Vin
= 2.0 V
Vee = 2.0 Vto 5.5 V
(note 1)
fc = 1 MHz
TA = 25°C
V
SOC752-M/SOC732-M
MQ
SOC752-M/SOC732-M
f.IA
SOC752-C/SOC732-C
8OC752J8QC732
Vcc-G,6V-
o,7VCC
G,45V-
I
\
D,2 VCC-o.1
100._.
~
I
1t:HCX
foe TaDt
Ta.CX
TQ.Il..
Figure: Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.
Idle ICC is measured with all output pins disconnected;
XTAL 1 driven with TCLCH, TCHCL =5 ns, VIL =VSS +
.5 V, VIH = VCC -.5 V; XTAL2 N.C. ; Port 0 = VCC;
EA = RST = VSS.
Power down ICC is measured with all output pins disconnected; EA =PORT 0 =VCC ; XTAL2 N.C. ; RST =
VSS.
vee
Note: 2.
Capacitance loading on Ports 0 and 2 may cause
spurious noise, pulses to be superimposed on the
VOLS of ALE and Ports 1 and 3. The noise is due
to external bus capacitance discharging into the
Port 0 and Port 2 pins when these pins make 1 to 0
transistions during bus operations. In the worst
cases (capacitive loading 100 pF), the noise pulse
on the ALE line may exceed 0.45 V with maxi VOL
peak 0.6 V. A Schmitt Trigger use is not necessary.
Figure: ICC Test Condition, Power Down Mode.
All other pins are Disconnected.
Note: 1.
ICC is measured with all output pins disconnected;
XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VS
+ 5 V, VIH = VCC -.5 V; XTAL2 N.C. ; EA = RST =
Port 0 = VCC. ICC would be slightly higher if a crys·
tal oscillator used.
EXTERNAL CLOCK DRIVE CHARACTERISTICS (XTAL 1)
SYMBOL
1JTCLCL
TCHCX
TCLCX
TCLCH
TCHCL
VARIABLE CLOCK
FREQ = 0 to 12 MHz
MIN.
MAX.
83
PARAMETER
Oscillator Frequency
High Time
Low Time
Rise Time
Fall Time
20
20
20
20
6-161
UNIT
ns
ns
ns
ns
ns
aOC752/8OC732
AC PARAMETERS
TA + O·C to 70·C; VSS = 0 V; VCC = 5 V± 10 % (commercial)
(load capacitance for Port 0, ALE; and PSEN = 100 pf ; load capacitance for all other outputs = 80 pt).
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
TLHLL
ALE Pulse Width
2TCLCL-40
ns
TAVLL
Address Valid to ALE
TCLCL-55
ns
TLLAX
Address Hold After ALE
TCLCL-35
TLLlV
ALE to Valid Instr in
TLLPL
ALE to PSEN
TCLCL-40
ns
TPLPH
PSEN Pulse Width
3TCLCL-45
ns
TPLIV
PSEN to Valid Instr in
TPXIX
Input Instr Hold After PSEN
TPXIZ
Input Instr Float After PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid Instr in
TPLAZ
ns
4TCLCL-110
3TCLCL-105
ns
ns
0
TCLCL-25
ns
ns
TCLCL-8
PSEN Low to Address Float
ns
5TCLCL-105
ns
10
ns
MAX.
UNIT
ns
ns
ns
ns
ns
ns
EXTERNAL DATA MEMORY CHARACTERISTICS
SYMBOL
PARAMETER
MIN.
TRLRH
RD Pulse Width
6TCLCL-100
6TCLCL-100
TWLWH
WR Pulse Width
TLLAX
Data Address Hold After ALE
TRLDV
RD to Valid Data in
TRHDX
Data Hold After RD
TCLCL-35
5TCLCL-165
0
TRHDZ
Data Float After RD
2TCLCL-70
TLLDV
ALE to Valid Data in
8TCLCL-150
ns
TAVDV
Address to Valid Data in
9TCLCL-165
ns
TLLWL
ALE to WR or RD
3TCLCL+50
ns
TAVWL
Address to WR or RD
TQVWX
Data Valid to WR Transition
TQVWH
Data Setup to WR High
TWHQX
Data Hold After WR
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
3TCLCL-50
TCLCL-60
ns
ns
7TCLCL-150
ns
4TCLCL-130
ns
TCLCL-50
TCLCL-40
6·162
0
ns
TCLCL+40
ns
8OC752/8OC732
AC TIMING DIAGRAMS
EXTERNAL PROGRAM MEMORY READ CYCLE
.--------~---12Ta.n------------_t
TlHlL_-+-_AlE
NJ-N
PORT 0 INSTR IN
ADDRESS
P0Rr2 OR SFR-P2
AIJORESS A8-A15
1NS1R IN
ADIJRESS AB-A15
EXTERNAL DATA MEMORY READ CYCLE
TWHUl _
,-----~~-----TWN----~·~I
ALE
---------------+----------~~-------+TIUHI--------~~------
PORf2
AIlORESS A8-A15 OR SFR-P2
ADRESS
ORSFR-P2
EXTERNAL DATA MEMORY WRITE CYCLE
I
r
TWHlH
"
AlE
_ 1 U . W L_ _ _
.I
..
PORrO
:>---VA NEW !>VA
MCNPORrSRC
MCNoe;rPII
I:::;:J
II!;N OESI"PORr:""CP1.=P2.--P3)----S
CINCWJESINTO. 1NT'.To.T1)
li!BlLPO!!!"SlFTgpac;
APO PItS MNI'lBl
'T'. .-----------------------------~
~
P1.P2.P3P1NSSAIFl.Bl
_
~O)---------....:..._i_I
L;~~!:!..~
~~_
,
r
RXDSAMPUD
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the
pins however ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from
output to output and component to component. Typically though (TA = 25°C, fully loaded) RD and WR
propagation delays are approximately 50 ns. The other
signal are typically 85 ns. Propagation delays are incorporated in the AC specifications.
6-165
80C752/80C732
ORDERING INFORMATION
P
80C732
-M
S
80C752
-C
I
T
temperature range:
blank: commercial
I : industrial
I
80C732 : Romless
version
80C752 : Rom 4k x 8
xxx
T
Customer ROM
Code (80C752 only)
M : Mechanical
C : Capacitive
Package type
P : Plastic OIL
S/Plastic LCC
PCK52
* Commercial version in POIL(P) or PLCC(S) package of PCK52 (Personal Computer Keyboard Controller
containing Software PCS52).
PCS52 : (assembly source code only)
* Personal Computer Software dedicated for: IBM PC keyboard.
iiiil1iiii
6-166
APPLICATION
NOTES
II
L - -_ _ _ _ _
7-1
ffii.~1IIS
-------lIliMi~
IllS
---S-ep-te-m-b-er-1-g8-9
AN1022
APPLICATION NOTE
DESIGN OF A PROCESSOR CARD USING
THE 8051/31 AH OR THE 80C51/C31
NOTA: IN THE TEXT HEREAFTER, 8051 REFERS TO THE 8051AH (HMOS) OR 80C51 (CMOS).
I - 8051/31 OVERVIEW
The 8051 is a stand-alone high performance single-chip
microcontroller. It provides hardware features, architectural enhancements and new instructions that make it
a powerful and cost-effective controller for applications
that require up to 64 K bytes of program memory and/or
64 K bytes of data memory.
The 8031 is a control-oriented CPU without on-chip program memory (ROM). It can address up to 64 K bytes
of program memory in addition to 64 K bytes of external
data memory.
4096BYTES
PROGRAM
1W)11H!1T
TNER/EVENT
128BYTES
tlAJAMEMORY
MEMORY
8051
OCIUNTEAS
PROGRAMMAIllE
SERlALPORT
-FUI..LOUPI..EX
UARI"
64K-BYTEBUS
EXRI\NSION
CONTROL
-SYNCHRONOUS
SHFTER
I
I
I
I
I
I
I
I
I
J
SERIAL
IMAllElPORTS
IN
SERIAl.
our
ADORESSIDATABUS
AND 110 PINS
Figure 1 : Block Diagram.
7-3
MATRA MHS
II
8051/31AH or 8OC51/31
RST/VPO
..
o(~ ~
~\~ I.
i
~
PIO
\ICC
PI I
PO.O ADO
PI.2
PIli ADI
PI3
PIl2 m2
P1."
PO.3 AD3
PIS
PO.4 AD4
PI6
1'0.5 ADS
OJ
g
~
il
I
-l
~\
.
J~
~\=
.-
RlCO_
TXD_
1NtD_
iifi
___
10_
Tt_
Wi!_
ii>_
..
::>
m
~
PI7
1'0.6 ADS
RST/VPO
1'0.7 N11
100)
1'3.0
~
TXD
1'31
ALE
iffii
P32
iNTi
P33
P§3ii
1'2.7 A15
10
1'34
1'2.6 AI4
TI
1'35
Wi!
ii>
1'3.6
P2.5 AI3
1'2.4 A12
P37
P2.3 A1t
X1l\L2
P2.2 AIO
XTALI
1'2.\ /oS
vss
P2.O A8
Most instructions are of one or two bytes and are executed in one or two cycles. With a 12 MHz crystal the
cycle time is 1 Ils. Only multiplication and division require 4 cycles to execute (4 IlS at 12 MHz).
Internally the 8051/31 comprises:
- 4 K bytes of program memory (8051 only)
- 128 bytes of data memory
- Four 8-bit ports giving up to 32 input/output lines
- Two 16-bit timers/event counters
- Full-duplex serial communications port
- An enhanced 8048 architecture
- Boolean processor within the CPU
- Externally an 8051/31 system may be expanded to
comprise:
- Up to 64 K bytes of program memory
- Up to 64 K bytes of data memory
- Input/output expansion using memory-mapped
peripherals
Because the architecture is based on the 8048 processors, programs written for the 8048 can be transferred
to the 8051 with some modification. These progams will
run at 2 1/2-10 times the speed of equivalent programs
on the 8048, due to the 8051 processor's higher
throughput.
8051 FAMILY PIN DESCRIPTION
vss
PORT 2
Port 2 is an 8-bit quasi-bidirectional I/O port. It also
emits the high-order address byte when accessing external memory. It is used for the high-order address and
the control signals during program verification. Port 2
can sink/source three LS TTL loads.
Circuit ground potential.
vee
+ 5 V power supply during operation and program
verification.
PORT 0
PORT 3
Port 3 is an 8-bit quasi bidirectional I/O porL!!.also contains the interrupt, timer, serial port and RD and WR
pins that are used by various options. The output latch
corresponding to a secondary function must be
programmed to a one (1) for that function to operate.
Port 3 can sink/source three LS TIL loads. The secondary functions are assigned to the pins of Port 3, as follows:
- RXD/data (P3.0). Serial port's receiver data input
Port 0 is an 8-bit open drain bidirectional I/O port. It is
also the multiplexed low-order address and data bus
when using external memory. It is used for data output
during program verification. Port 0 can sink/source
eight LS TIL loads.
PORT 1
Port 1 is an 8-bit quasi-bidirectional I/O port. It is used
for the low-order address byte during program verification. Port 1 can sink/source three LS TTL loads.
7·4
8051/31AH or 8OC51/31
(asynchronous) or data input/output (synchronous).
tion. It is activated every six oscillator periods except
during an external data memory access.
- TXD/clock (P3.1). Serial port's transmitter data output
(asynchronous) or clock output (synchronous).
- INTO (P3.2). Interrupt 0 input or gate control input for
counter o.
- INT1 (P3.3). Interrupt 1 input or gate control input for
counter 1.
- TO (P3.4). Input to counter O.
- IlJP3.5). Input to counter 1.
- WR (P3.6). The write control signals latches the data
b~from Port 0 into the External Data Memory.
- RD (P3.7). The read control signal enables External
Data Memory to Port o.
PSEN
The Program Store Enable output is a control signal that
enables the external Program Memory to the bus during
extemal fetch operations. It is activated every six oscillator periods, except during external data memory
accesses. Remains high during internal program
execution.
EA
When held at a TTL high level, the 8051 executes instructions from the internal ROM when the PC is less
than 4096. When held at a TTL low level, the 8051
fetches all instructions from external Program Memory.
RSTIVPD
A high level on this pin resets the 8051. A small internal
pulldown resistor permits power-on reset using only a
capacitor connected to VCC. If VPD is held within its
spec while VCC drops below spec, VPD will provide
standby power to the RAM. When VPD is low, the
RAM's current is drawn from VCC.
XTAL1
Input to the oscillator's high gain amplifier. Required
when a crystal is used. Connect to VSS when external
source is used on XTAL2.
ALE
XTAL2
Provides Address Latch Enable output used for latching
the address into external memory during normal opera-
Output from the oscillator's amplifier. Input to the internal timing circuitry. A crystal or external source can be
used.
1.1.8051 CPU ARCHITECTURE
The CPU operates in four memory spaces. These are:
- 64 K byte program memory
- 64 K byte external data memory
- 384 byte internal data memory
- 16 bit program counter
The 384 byte internal data memory is divided into
256 bytes of RAM and 128 bytes forthe special function
registers (SFR). The top 128 bytes of RAM and the SER
are overlapped. Of the 384 bytes theoretically available,
only 128 bytes of RAM are provided together with
20 bytes in the SFR.
The SFR contains all the 8051 registers except the pro-
.,t
gram counter, allowing operations to be carried out on
all registers. Within the internal RAM and SFR there are
also bit variables. The 16 bytes from 20H to 2FH contain
128 directly addressable bits. There are another
128 bits allocated to the SFR although not all of them
are assigned. Contained within the 8051 CPU is a
boolean processing unit.
This unit uses the carry as an accumulator in conjunction with bit instructions allowing fast and simple bitmanipulation without the need for masking.
II
!14K
64K
O\IER.APPED SIN:E
-----
4095
INTI: JW.
L-~----A
I
I 128
--- -" - I
2551
I
I
1~1
0
~
7-5
1
256
0
.
_ _ _ _ _ _ _ _ _ _ _ S05i/3iAM or 8OC5i/3i _ _ _ _ _ _ _ _ _ __
a) RAM Bit Addresses.
RAIl
BYtE (IISB)
7FH1
~
II
'iI
2FH
7F
7E
7D
7C
7B
7A
78
78
2&1
77
78
75
74
73
72
71
70
2DH
8F
6E
eo
6C
88
SA
88
88
201
ffI
88
66
84
83
82
81
80
2...
5F
5E
50
5C
58
SA
89
88
2AH
S1
5&
55
54
53
52
51
50
28M
4F
4E
4D
4C
4B
4A
49
48
28H
1ft
45
45
44
43
42
41
40
27M
3F
3E
3D
3C
3B
SA
39
38
26H
:fI
38
35
34
33
32
31
30
25H
2F
2E
2D
2e
28
2A
29
28
24H
%I
28
25
24
23
22
21
20
23H
1F
1E
10
1C
18
1A
19
18
22H
11
18
15
14
13
12
11
10
21H
OF
OE
OD
OC
OS
OA
09
08
20t1
at
08
05
04
03
02
01
00
1FH
881*3
18H
f1H
Bank 2
10H
OFH
BaM1·
08H
01H
881*0
OOH
7-6
- - - - - - - - - - - - - 8051/31AH or 80C51/31
b) Hardware Register Bit Addresses.
=DhcI:
.AdeII •••••
OFFH
OFOH
F71 F81 FSI F41 F31F21 Pli
FO
OEOH
E7leeIESJE4IE3IE2IE11
EO
ODOH
mloeIDSID4ID3ID2ID11
DO
088H
-1-1-l ac l-IBAI
OBOH
B71B8laslB4IB3IB2IB1lao
P3
OASH
AFI - 1 -IACJABIAAI
E
OAOH
A7
I AS 1 AS 1 A4
I A3
1 A2
B9
A9
l aa
I AS
1A1 1AO
8
PSW
p
P2
98H
9FI 9E I 9D J 9C 198 I 9A 199 I 9S
SCON
90H
91J98\95194193\92191190
P1
88H
SFISE\SDISCIS8I sA I 89 l aa
TCON
SOH
S1
J 88
1 85 1
84.1 83 1S2 I 81 180
As in the 8048 there are also eight general purpose
registers RO·R? asssigned to RAM addresses. In the
8051 there are four banks of eight registers that are
available, the bank in use being selected by two bits in
the processor status word (PSW). This is useful for task
changing, such as interrupt processing. The stack has
also changed from that of the 8048. There is an 8-bit
stack pointer that directly addresses internal RAM allowing all of the internal memory to be used (up to 128
bytes).
PO
In the 8051 the lower 4 K of the 64 K program memory
address space is filled by internal ROM. By tying the EA
pin high, the processor can be forced to fetch from the
internal ROM for program memory addresses between
o and 4 K. If the EA pin is tied low, then all program
memory fetches are from external memory. The execution speed is the same regardless of whether fetches
are from internal or external memory.
7-7
8051/31AH or 8OC51/31
1.2 8051 INSTRUCTION SET
The following table summarises the 8051 instruction set.
ARITHMETIC OPERATIONS
MNEMONIC
ADD
A.Rn
ADD
A.direct
ADD
A.@Ri
ADD
A.#data
ADDC
A.Rn
ADDC
A.direct
ADDC
A.@Ri
ADDC
A.#data
SUBB
A.Rn
SUBB
A.direct
A.@Ri
SUBB
SUBB
A.#data
INC
A
INC
Rn
INC
direct
@Ri
INC
DEC
A
DEC
Rn
DEC
direct
@Ri
DEC
INC
DPTR
MUI
AB
DIV
AB
DA
A
LOGICAL OPERATIONS
MNEMONIC
ANL
A.Rn
ANL
A.direct
ANL
A.@Ri
ANL
A.#data
ANL
direct.A
direct.#data
ANL
ORL
A.Rn
ORL
A.direct
A.@Ri
ORL
ORL
A.#data
ORL
direct.A
ORL
direct.#data
XRL
A.Rn
XRL
A.direct
A.@Ri
XRL
XRL
A.#data
XRL
direct.A
XRL
direct.#data
CLR
A
CPL
A
RL
A
RLC
A
RR
A
RRC
A
SWAP
A
DATA TRANSFER
MNEMONIC
MOV
A.Rn
MOV
A.direct
DESCRIPTION
Add register to Accumulator
Add direct byte to Accumulator
Add indirect RAM to Accumulator
Add immediate data to Accumulator
Add register to Accumulator with Carry
Add direct byte to A with Carry flag
Add indirect RAM to A with Carry flag
Add immediate data to A with Carry flag
Subtract register from A with Borrow
Subtract direct byte from A with Borrow
Subtract indirect RAM from A with Borrow
Subtract immed. data from A with Borrow
Increment Accumulator
Increment register
Increment direct byte
Increment indirect RAM
Decrement Accumulator
Decrement register
Decrement direct byte
Decrement indirect RAM
Increment Data Pointer
Multiply A & B
Divide A by B
Decimal Adjust Accumulator
DESTINATION
AND register to Accumulator
AND direct byte to Accumulator
AND indirect RAM to Accumulator
AND immediate data to Accumulator
AND Accumulator to direct byte
AND immediate data to direct byte
OR register to Accumulator
OR direct byte to Accumulator
OR indirect RAM to Accumulator
OR immediate data to Accumulator
OR Accumulator to direct byte
OR immediate data to direct byte
Exclusive-OR register to Accumulator
Exclusive-OR direct byte to Accumulator
Exclusive-OR indirect RAM to A
Exclusive-OR immediate data to A
Exclusive-OR Accumulator to direct byte
Exclusive-OR immediate data to direct
Clear Accumulator
Complement Accumulator
Rotate Accumulator left
Rotate A left through the Carry flag
Rotate Accumulator Right
Rotate A Right through Carry flag
Swap nibbles within the Accumulator
DESCRIPTION
Move register to Accumulator
Move direct byte to Accumulator
7-8
BYTE
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
CYC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
BYTE
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
CYC
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
BYTE
1
2
CYC
1
1
4
4
1
8051/31AH or 80C51/31
A.@Ri
MOV
Move indirect RAM to Accumulator
MOV
A.#data
Move immediate data to Accumulator
MOV
Rn.A
Move Accumulator to register
MOV
Rn.direct
Move direct byte to register
MOV
Rn.#data
Move immediate data to register
MOV
direct.A
Move Accumulator to direct byte
MOV
direct.Rn
Move register to direct byte
MOV
direct.direct
Move direct byte to direct
MOV
direct.@Ri
Move indirect RAM to direct byte
MOV
direct.#data
Move immediate data to direct byte
MOV
@Ri.A
Move Accumulator to indirect RAM
MOV
@Ri.direct
Move direct byte to indirect RAM
MOV
@Ri.#data
Move immediate data to indirect RAM
MOV
DPTR.#data16
Load Data Pointer with a 16-bit constant
MOVC
A.@A+ DPTR
Move Code byte relative to DPTR to A
MOVC
A.@A+ PC
Move Code byte relative to PC to A
MOVX
A.@Ri
Move External RAM (8-bit addr) to A
A.@DPTR
MOVX
Move External RAM (16-bit addr) to A
@Ri.A
Move A to External RAM (8-bit addr)
MOVX
@DPTR.A
Move A to External RAM (16-bit addr)
MOVX
PUSH
direct
Push direct byte onto stack
POP
direct
Pop direct byte from stack
XCH
A.Rn
Exchange register with Accumulator
XCH
A.direct
Exchange direct byte with Accumulator
A.@Ri
XCH
Exchange indirect RAM with A
A.@Ri
XCHD
Exchange low-order Digit indo RAM w/A
BOOLEAN VARIABLE MANIPULATION
MNEMONIC
DESCRIPTION
CLR
C
Clear Carry flag
CLR
bit
Clear direct bit
SETB
Set Carry flag
C
SETB
bit
Set direct Bit
CPL
C
Complement Carry flag
Complement direct bit
CPL
bit
ANL
C.bit
AND direct bit to Carry flag
ANL
C.bit
AND complement of direct bit to Carry
ORL
C.bit
OR direct bit to Carry flag
ORL
C.bit
OR complement of direct bit to Carry
MOV
C.bit
Move direct bit to Carry flag
MOV
bit.C
Move Carry flag to direct bit
PROGRAM AND MACHINE CONTROL
MNEMONIC
DESCRIPTION
ACALL
addr11
Absolute Subroutine Call
LCALL
addr16
Long Subroutine Call
RET
Return from subroutine
RETI
Return from interrupt
AJMP
addr11
Absolute Jump
addr16
LJMP
Long Jump
rei
SJMP
Short Jump (relative addr)
JMP
@A+DPTR
Jump indirect relative to the DPTR
JZ
rei
Jump if Accumulator is Zero
rei
JNZ
Jump if Accumulator is Not Zero
rei
Jump if Carry flag is set
JC
JNC
rei
Jump if No Carry flag
bitrel
Jump if direct Bit set
JB
bitrel
Jump if direct Bit Not set
JNB
bitrel
Jump if direct Bit is set & Clear bit
JBC
A.directrel
Compare direct to A & Jump if Not Equal
CJNE
A.#data.rel
Camp. immed. to A & Jump if Not Equal
CJNE
7·9
1
2
1
2
2
2
2
3
2
3
1
1
1
2
1
1
2
2
2
2
1
1
2
2
3
2
1
1
1
1
1
1
2
2
1
1
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
BYTE
1
2
1
2
1
2
2
2
2
2
2
2
CYC
1
1
1
1
1
1
2
2
2
2
1
2
BYTE
2
CYC
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
1
1
2
3
2
1
2
2
2
2
3
3
3
3
3
8051/31AH or 8OC51/31
CJNE
Rn.#data.rel
Compo immed. to reg & Jump if Not Equal
3
2
3
2
CJNE
@Ri.#data.rel
Camp. immed. to indo & Jump if Not Equal
DJNZ
Rn.rel
Decrement register & Jump if Not Zero
2
2
DJNZ
direct. rei
Decrement direct & Jump if Not Zero
3
2
NOP
No operation
1
1
NOTES ON DATA ADDRESSING MODES:
Rn
Working register RO-R?
direct
128 internal RAM locations, any I 0 port, control or status register
@Ri
Indirect internal RAM location addressed by register RO or R1
#data
8-bit constant included in instruction
#data16
16-bit constant included as bytes 2 & 3 of instruction
bit
128 software flags, any I 0 pin, control or status bit
NOTES ON PROGRAM ADDRESSING MODES:
addr16
Destination address for LCALL & LJMP may be anywhere within the 64-Kilobyte program
memory address space.
addr11
Destination address for ACALL & AJMP will be within the same 2-Kilobyte page of
program memory as the first byte of the following instruction
rei
SJMP and all conditional jumps include an 8-bit offset byte. Range is + 127 - 128 bytes
relative to first byte of the following instruction.
1.3. INPUT/OUTPUT PORTS
The 8051 contains four 8-bit ports known as PO-P3. Any
line on any port may be individually configured as an
input or an output. Ports 0, 2 and 3 can also carry out
other functions, depending upon how the 8051 has
been programmed.
Port 2 :
Quasi-bidirectional port capable of driving a single TTL
load. High-order address bus for 8051 expansion.
Port 3 :
Quasi-bidirectional port capable of driving a single TTL
load. Contains interrupt and timer inputs, serial input!
output and external memory control signals.
The differences between the types of port are at the
chip level. At functional and programming levels there
are no differences (except for Port 0 drive capability).
After power-up all ports are configured as inputs, they
may be reconfigured by writing a zero (0) to the pin.
Port 0 :
Bidirectional port with open-drain pins capable of driving 2 TTL loads. Multiplexed low-order address and
data bus for 8051 expansion.
Port 1 :
Quasi-bidirectional port capable of driving a single TTL
load.
READ PULSE (READ.
MOOIFY.WRITE)
+5V
INTERNAl
BUS
Q
a
o
RJP
FLOP
110
PIN
PORI"
o
WRItE PULSE
WRItE PULSE
~~ -+--------~
READ PULSE
(NON READ.
MODIfY.WRTE)
Figure 7: Port Pin Structure.
7-10
8051/31AH or 80C51/31
When writing a new value to port output pins, a one (1)
must be written to all those pins that are to remain as
inputs. All port pins may also be addressed individually
by bit instructions. The secondaryfunctions of Port 3 are
generated if the pin is configured as an input.
Example: Configure bits Pl.0-Pl.2 as outputs leaving
Pl.3-Pl.7 as inputs.
ANL Pl , # 11111 OOOB
If later on, we wish Pl.l to be an input and Pl. 7 to be
an output, then the following is performed.
In the 8051 instruction set there are three classes of instructions.
ORL Pl, # 0000001 OB ; set Pl.l to an input
ANL Pl, # 01111111 B ; set Pl.7 to an output
Read: Read current value from source
Write: Write value to destination
Read-modify-write : Read from source, perform operation, write to destination.
Reading and writing of ports is accomplished by
"MOVE" instructions.
MOV A, Pl ; read port 1
MOV PO, # OFFH ; write to port 0
Each class of instruction operates differently on the 110
parts.
1.4. TIMER/COUNTERS
The flip-flop contains the value that was written to the
port. If it was one (1) the port pulls up the output line.
This gives an output of one (1) for an output or allows
reading of the port pin for an input. Read-modify-write
instructions use the value in the flip-flop as the source.
This means that pins configured as inputs will not be
changed (unless done so by the instructions) '!Yhen the
write back is performed. Consequently, read-modifywrite instructions are used to configure ports. After
power-on all bits are inputs (at the one (1) level). Performing an AND of one (1) with bits to remain as inputs
and zero (0) with bits to become outputs will change this
configu ration.
Crystal
OSCIllator
External
source
0
~ I0 1
S
234
5-bit prescaler
The 8051 contains two 16-bit progammable timers/
event counters. They can be used to measure time inteNals, extemal pulse widths or generate periodic interrupt request. Each timer may be configured into one of
four modes. Modes 0-2 are identical for each timer, only
Mode 3 is different.
A-Mode 0 :
An 8-bit counter/timer with a 5-bit pres caler. Reading the
high order half (THO or TH1) accesses bits 12-5 of the
counter. The lower half (TLO or TL 1) contains the prescaler in bits 4-0. Bits 5-7 are not used and should be set
to zero.
B
70
XXX
I
5 6 7 8 9 10 11
8-bit counter
Figure 8 : Timer Mode O.
7-11
7
I
~T
~--
Overflow
interrupt
request
Pulse to serial
port-timer 1
only
8051/31AH or 8OC51/31
~:or"~12
8demm
source
B
B
0r-________~ror_----~----~7
1
1
1
0verfIc7N
.. - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 5 T interrupt
------~/
- _ - - - -.....y'
".....
1&bit counter
request
to serial
~
n -- Pulse
port-timer 1
only
Figure 9 : Timer Mode 1.
C - Mode 2 :
An 8-bit auto-reload timer. The lower half is incremented until it overflows. The auto-reload value in the
top half is then loaded into the lower half and counting
resumes.
=O:1+j. '1__1'-1------;1
B
0
7
=~
o
111
Overflow
- . - - interrupt request
7
t
'-Ir------B:~-=--==~I ~~~
Figure 10: Timer Mode 2.
O-Mode 3 :
Timer is configured as two independent 8-bit timers.
The upper half, THO, is an 8-bit timer using the clock as
a source. It is controlled by the bits of Timer 1. The 'Run'
and 'Overflow' bits fo Timer 1 are, therefore, not available to Timer 1. The lower half of Timer TLO, is configured as an 8-bit counter/timer in the usual manner.
°
°
Timer 1 has no overflow or run bits when Timer is in
mode 3. To overcome this, mode 3 of Timer 1 is used
to halt counting, changing to another mode will start it
again. Although Timer 1 can be used in Modes 0-2, note
that it cannot generate an interrupt.
°,
Crystal
°Source=·B
.+12_~r-1_J§l_~_-:,7 I 0 J§l
7
~t~ ~___________~~~.__________~I~~~
=..-EJ
§t' J![
· ~"'=
J_I----__
..
Program~~~~
=-..
---JI-._ _ _ _ _ _..J
Mode 3 halts timer
Figure 11 : Timer Mode 3.
called TMOD and TCON-timer mode and timer control.
The bit explanations are given in the tables.
E· Timer control
Associated with the timers are two control registers
iiih'i
7-12
8051/31AH or 80C51/31
(MSB)
I
GATE
(LSB)
CIT
M1
I
MO
CIT
GATE
TIMER 1
M1
MO
I
TIMER 0
GATE
Gating control. When set, Timer/counter "x" is enabled
only while "INTx" pin is high and "TRx" control bit is set.
When cleared, timer/counter is enabled whenever
"TRx" control bit is set.
M1
MO
o
o
o
8048 Timer. "TLx" serves as five-bit
prescaler.
16-bit timer/counter. "THx" and "TLx"
are cascaded; there is no prescaler.
o
CIT
Timer or Counter Selector. Cleared for Timer operation
(input from internal system clock). Set for Counter
operation (input from "Tx" input pin).
Operating Mode
8-bit auto-reload timer/counter. "THx"
holds a value which is to be reloaded
into "TLx" each time it overflows.
(Timer 0)
TLO is an eight-bit timer/counter
controlled by the standard Timer 0
control bits.
THO is an eight-bit timer only controlled
by Timer 1 control bits.
(Timer 1)
Timer/counter 1 stopped.
(MSB)
I
TF1
(LSB)
TR1
TFO
TRO
IE1
IT1
lEO
ITO
I
Symbol Position Name and Significance
TF1
TCON.7 Timer 1 overflow Flag. Set by
hardware on timer counter
overflow. Cleared when interrupt
processed.
IE1
TCON.3 Interrupt 1 Edge flag. Set by
hardware when external interrupt
edge detected. Cleared when
interrupt processed.
TR1
TCON.6 Timer 1 Run control bit. Set!
cleared by software to turn timer/
counter on/off.
IT1
TFO
TCON.5 Timer 0 overflow Flag. Set by
hardware on timer/counter
overflow. Cleared when interrupt
processed.
TCON.2 Interrupt 1 Type control bit. Set!
cleared by software to specify
falling edge/low level triggered
external interrupts.
lEO
TCON.1
ITO
TCON.O Interrupt 0 Type control bit. Set!
cleared by software to specify
falling edge/low level triggered
external interrupts.
TRO
TCON.4 Timer 0 Run control bit. Set!
cleared by software to turn timer/
counter on/off.
7-13
Interrupt 0 Edge flag. Set by
hardware when external interrupt
edge detected. Cleared when
interrupt processed.
ffif.'11i1111S
8051/31AH or 8OC51/31
1.5. SERIAL PORT
Mode 3 : UART interface with an 11-bit frame and variable transmission rate.
The 8051 contains a serial port that can link with UART
devices or expand input/output. The serial port is
programmable into one of four modes.
Mode 1 : UART interface with a 1O-bit frame and variable transmission rate.
The port is full duplex, meaning that it can transmit and
receive at the same time. The serial port buffer register
(SBUF) holds the received data and the data to be
transmitted, a write loading the transmit register and a
read reading from the receive register.
Mode 2 : UART interface with an 11-bit frame and fixed
transmission rate.
The control register, SCON, contains the information to
configure the port.
Mode 0 : Synchronous input/output using TTL or
CMOS shiff registers.
(LSB)
(MSB)
I
SMO
I
SM1
I
SM2
I
TB8
REN
RB8
TI
RI
I
Symbol Position Name and Significance
SMO
SCON.? Serial port Mode control bit o.
Set/cleared by software
(see note).
RB8
SM1
SCON.6 Serial port Mode control bit 1.
Set/cleared by software
(see note).
TI
SM2
SCON.5 Serial port Mode control bit 2.
Set by software to disable
reception of frames for which bit
8 is zero.
SCON.1 Transmit interrupt flag. Set by
hardware when byte transmitted.
Cleared by software after
servicing.
RI
SCON.O Received Interrupt flag. Set by
hardware when byte received.
Cleared by software after
servicing.
REN
TB8
SCON.4 Receiver Enable control bit. Set/
cleared by software to enablel
disable serial data reception.
SCON.3 Transmit Bit 8. Set/cleared by
hardware to determine state of
ninth data bit transmitted in
9-bit UART mode.
SCON.2 Receive Bit 8. Set/cleared by
hardware to indicate state of
ninth data bit received.
Note - the state of (SMO.SM1) selects:
(0, 0) - Shift register 1/0 expansion.
(0, 1) - 8 bit UART, variable data rate.
(1, 0) - 9 bit UART, fixed data rate.
(1, 1) - 9 bit UART, variable data rate.
A-Mode 0 : synchronous input/output
Two lines are used, P3.0 and P3.1. The first is the serial
data, either input or output, and the second is a bit clock.
Every time a byte is written to SBUF it is shifted out on
P3.0. Every time the receive flag (R1) is cleared, 8-bits
are read in from P3.0 to SBUF. Once completed, R1 is
set again. Data can be clocked into a shift register on
the rising edge of the clock (P3.1).
With the addition of more hardware and port lines a fully
interlocked full or half-duplex system can be built. For
parallel intercommunications it is probably more expedient to use one of the ports. The advantage of this
serial system is that it is faster than a UART, transfer is
at 1M bit/second with a 12 MHz clock, and may be
cheaper than a parallel system since only two lines are
needed (P3.0 and P3.1).
8051
INHNS
DA.TA 1 - - - - 4
PORrPIN
A. 110 INPUT
EXPANSION
8051
DAJ.6.
PORrPIN
These are the UART modes of the Serial Port. Each bit
is divided into 16 "ticks", the bit being sampled during
the seventh, eighth and ninth ticks. Format is the usual
UART/RS 232C format of one start bit, eight or nine
data bits and one or two stops bits. Typical frame formats are shown below.
=..
I----~
a..oo<
B-Modes 1-3
B. VO OUTPUT
EXFY>.NSION
Figure 14: 1/0 Expansion Technique.
~
iiih'i1rn
SIN
a.oa<
7-14
as
EN
8051/31AH or 80C51/31
__. -__________. -__. -__.---,MODE
TTY
[
1
7-BITDIOA
PAII1Y
3
2 SlOP
1
TYPICAL
CRT
7-BlTDIOA
MARK SlOP
3
PARfTYSlOP
L -__L -______________
MUlll-
~
__- L_ _
~I 2&3
PROCESSOR
COMMUNICATIONS
1 2 &3
~~--~-------~-BlT--DIOA----------~sro--OP~
110
EXPANSION
o
8DITS
Figure 15 : Typical Frame Formats.
Mode 1 consists of start and stop bits around 8 data bits.
This is a format used by many VDUs. The code is 7-bit
ASCII and parity, or is an 8-bit code (normally ASCII
with bit 7 at zero plus 128 special codes). For teletypes
two stop bits are usually required to reset the mechanical apparatus of the next character. Mode 3 can used
with the eighth bit set to a one (1) so that two stop bits
are always generated. The same mode can be used of
a CRT device having special codes as well as character
codes plus parity.
For multiprocessor communication between 8051 systems modes 2 and 3 are used. There are special features of the 8051 which make it advantageous to use
these modes. Mode 2 is exactly the same as mode 3
except that its transmission rate is fixed.
As in mode 0 the transmit interrut (TI) bits is set when
the byte has been transmitted. This indicates that the
buffer is free for another character. On reception of a
byte the receive interrupt (RI) bit is set. If the interrupt
enable bits are set then an interrupt will occur whenever
another character can be transmitted or when a character has been received.
1. Slaves - Configure serial port to interrupt CPU if
the received ninth data bit is a one (1).
C-Transmission rate
The serial port is clocked by the overflow of timer 1. The
input to timer 1 is either the crystal frequency divided by
12, or an external clock via the T1 input of Port 3. In
modes 0 and 2 the input frequency is feied at the oscillator frequency divided by 12 or 64 respectively. For
mode 0 this gives 1 M bit per second with a 12 MHz crystal, and 187,500 bits per second for mode 2 (again with
a 12 MHz crystal). Modes 1 and 3 have the transmission
rate determined by timer 1. The timer is configured in
autoreload to generate a fixed frequency. Either onetwelfth of the oscillator frequency or the T1 input is
divided by "256-Minus-The-Value-in-TH1" (auto-reload
value) which is then divided by 32 and used to clock the
UART shift register. At 12 MHz this allows transmission
rates from 122 to 31,250 bits per second.
2. Master - Transmit frame containing address in
first 8 data bits and set ninth data bit (i.e. ninth data
bit designates address frame).
3. Slaves - Serial port interrupts CPU when address
frame is received. Interrupt service program compares received address to its address. The slave
which has been addressed reconfigures its serial
port to interrupt the CPU on all subsequent transmissions.
4. Master - Transmit control frames and data frames
(these will be accepted only by the previously addressed slave).
7·15
III
8051/31AH or 8OC51/31
~I+rl
g
~en:' • _f',-------i
0
7
._. .------II Overflow
.. r:;L-UARTCock
_
D-
TL1
For a UART operating at 300 bps using an S051 clock
at 12 MHz, the auto reload value is given by :
Auto-reload =
INIT : MOV TMOD,# 001 OXXXXB ; timer 1 = mode 2
MOV TH1 ,# 9SH
; auto-reload
value
MOV SCON,# 01010000B ; set up UART
SETB TR1
; start timer
Clock Rate
12 x 32 x Bit Rate
If an external clock is used, via T1
Auto-reload =
Bit T1 is set in SCON to enable the routine to load the
first character. Afterwards it waits until T1 is set before
sending any new characters.
Clock Rate
32 x Bit Rate
READ : JNB RI, READ
So with an S051 clock of 12 MHz and a transmission
rate of 300 bps.
Auto-reload =
MOVA, SBUF
CLRRI
CLRACC?
RET
WRITE: MOV A, CHAR
MOVC, P
12 X 106
--:-c:-----~
12x32x300
Auto-reload value = 104.16
The nearest integer is 104, so the actual value for the
timer is 256 - 104 = 152 (9SH in hexadecimal). Loading
TH1 with a value of 9SH gives the correct speed.
MOVACC?C
WAIT : JNB TI, WAIT
For a simple polling operation of the UART (no interrupts) the following routines can be used.
MOV SBUF, A
RETI
; wait for
character
; load character
; reset flag
; clear parity
; end routine
; load character
; load parity into
carry
; transfer to
accumulator
; wait for buffer
to be free
; load character
; end routine
II - EXTERNAL MEMORY
2.1. Accessing external memory
II
outputs. Data access is via MOVX instructions using the
DPTR or RO or R1.
All memory, either program or data, is addressed using
16 address lines. Normally the first 4 K of program
memory is contained in the CPU. The rest is accessed
by using the secondary functions of the I/O ports. Port
2 emits the upper address byte (AS-A 15) and Port 0
emits the lower address byte and data byte (ADO-AD?).
The two signals ALE and PSEN are used together with
two pins from Port 3 (RD and WElL The PSEN line
selects external PrQ9@m Memory, RD selects external
Data Memory and WR latches data into external Data
Memory. If PSEN and RD are OR-ed together, then the
processor has a continuous 64 K program and data
space, as found on many computers (cf. SOS5). The Address Latch Enable (ALE) is used to latch the address
into external latches or synchronous memories.
The S051 can address 64 K bytes of external program
memory (as the S031 does) when the EA pin is tied to
a low level. This disables the internal 4 K of program
memory Ports 0 and 2 are automatically configured as
2.2 Timing diagrams
The basic cycle of the S051 is six oscillator periods.
When accessing Program Memory the instruction
fetches overlap with the start of the next cycle. This
means that the S051 always fetches an even number
of bytes, even if the second is ignored. External Data
Memory accesses last for two cycles allowing slower
peripherals or data memory than program memory.
The address is valid on the falling edge of ALE. This is
used to latch the address into the memory or for demultiplexing circuitry. For a read, of either data or program
memory, the PSEN or RD signal enables the bus
drivers. Data or an instruction is clocked into tlliu;lroces:,or. on the rising edge of PSEN or RD. The WR signal
indicates that the data on the bus is valid. During a write
cycle, it can also be used to enable external buffers or
latches in the system.
7-16
8051/31AH or 80C51/31
r---
A15
~
G2B
U1
NJ
ALE
A
Decoder
GOE
~
G
AUT
Chip select 0-7
for2KbIocks
~U4
latch
Address liles
to memory
U2
OE
~
bidirectional buffer
1.-.,-
"----
Data lines
to programIdata
U3
.~
J
memory
=1
U1,2: 8282174 LS :rT3n4 LS 734
U3 :8286n4 LS245
UA : 3205n4 LS 136
Figure 18 : Address/Data Latching.
2.3. External program memory
below divides the memory space between 0 and 16 K
into 2 K blocks.
To add external memory we must examine the timing
diagrams and choose a component with a suitable access time. The access time is the time from the validation of the chip select (CS) signal to the latching of the
data into the processor, less and delays and set-up
times. Most memory components require a latched
demultiplexed bus with some decoding. The diagram
For the 8051, addresses are stable by the falling edge
of ALE. This is used to clock the address into the buffers. The data is clocked into the processor on the rising
edge of PSEN. The time between the two is the maximum time available to access program memory.
~-----------------------TCY'--------------------------~."'I
ALE
/IiI-AO
PORrO INSTR IN
1:-lSTR IN
ADDRESS A15-AB
PORr2
Figure 19: Read Cycle.
7-17
8051/31AH or 8OC51/31
Time to chip select being valid after ALE = delay through
buffer and decoder. Time for data to be valid at processor = access time and delay through buffer.
Also associated with memories is the Output Enable
(OE). This signal enables the external drivers to pass
information onto the bus. For demultiplexed signals the
PSEN line can be used directly for program memory
output enable.
We have to calculate the time allowed by the processor
for a memory access, including any set-up times, according to the waveforms above. This is as follows:
Address hold time after ALE (TLLAX)
+ Address float to PSEN (TAZPL)
+ PSEN pulse width (TPLPH)
- Set-up time for 8051
From _ _ _ _ _--,
decoder
This gives up :
48 + 0 + 215 + 0 = 263 nS (minimum) at 12 MHz
Address
We now have to calculate the worst case delays across
all the system components (buffers, decoders, etc.).
For a typical system using all MOS components and a
system with all TIL LS components, we have:
Buffer delay (max) from ALEMOS : 45 nS LSTIL :
30 nS from ALE
Decoder delay (max) MOS : 40 nS LS TIL : 39 nS
Data buffer delay (max) MOS : 30 nS LS TIL: 12 nS
Total MOS: 115 nS LS TIL: 81 nS
Address Data
t--.,.....
ALE _ _ _ _ _-,
Times can be reduced by using inverting buffers and/or
Schottky TTL logic. These times are subtracted from
the time calculated above to give us the maximum access time on the memory.
MOS components: 263 - 115 = 148 nS
TIL components : 263 - 81 = 182 nS
AddressIdata
It is possible to lengthen the access times if the address
latches are replaced by transparent latches, i.e., the
outputs follow the inputs until latched. The address from
the 8051 is valid 53 nS before the falling edge of ALE
so it is possible to use this time to perform selection, effectively gaining all of the 53 nS. This technique does
not work for flip-flop latches (i8282, 74 LS 374).
Address Data
t--.,.....
From ._ _ _ _ _---'
decoder
Figure 20 : ROM Selection.
This effectively increases the access time to :
In synchronous systems ALE is used to load the address register and OE (or G in this case) is selected by
the decoder. This gains a little extra time as address
decoding can start immediately after ALE, with all
memories reading a particular byte. The decoder then
selects the correct memory and enables its output
drivers. Power consumption doesn't increase too
much, as it is the output drivers that consume the most
current. Note also, thata latched decoder (or equivalent
system) mut also be used if AO-A7 are used for address
decoding (A8-A15 are available throughout the cycle).
MOS components: 148 + 53 = 201 nS
TIL components : 182 + 53 = 235 nS
If a demultiplexed system is not required and large
loads are not being driven, then it may be possible to
do without latching and buffers altogether. There are
certain memories that incorporate on chip address
latches and are, therefore, ideally suited for multiplexed
buses. These are known as synchronous memories,
while those without internal latches are synchronous
memories.
7·18
8051/31AH or 80C51/31
2.4. External data memory
without much system degradation. In the 8051 RAM accesses are twice as long as ROM accesses allowing the
use of slower and chea~ RAMs. As-.1b.e timing
diagrams show, the read (RD) and write (WR) signals
are active for much longer, in fact a minimum of 400 nS.
External data memory will usually be RAM since the
ability to read and write data will be required. Generally
in a system of this sort most accesses will be to the program memory, interspersed with RAM accesses. Because RAM accesses are not as common as ROM
accesses, the time allowed for them can be longer
ALE
Dl'JAIN
PORTO
TRI.AZ
ADDRESS AI5-AS OR SFR-P2
PORT 2
TWHl.H
ALE
TDVWX
PORTO
ADmESS
PORT 2
_lWHClX
1lATA0lIT
ORSFR-P2
ADDRESS AI5-AS OR SFR-P2
Figure 21 : RAM Read and Write Timing.
If using an asynchronous system with latches this allows an access time of at least 485 nS (for MOS components) which is ample for most memories. The circuit
configurations are very similar. The RAM and ROM can
be placed in parallel and the output enable lines (OE)
selected by PSEN or RD. Synchronous RAMs are more
difficult to deal with. We cannot use the same techni-
ques as for PROMs. Loading the address into.,g!!
memories and selecting a particular output with the RD
signal and decodLQgJogic is fine, but we will also have
to do this with the WR signal whenever we update data.
It becomes apparentthatl!J.§..much easier to decode the
address first and use the WR and RD signals for writing
and output enable.
from ._ _ _ _~---,
decoder
from ._ _ _ _--.--.
decoder
RAM
RAM
. -_ _ RD
IN OEI---RD
Asynclvonous system
(Demultiplexed)
Synchronous system
(Multiplexed bus)
Figure 22 : RAM/ROM Selection.
7-19
8051/31AH or 8OC51/31
To generate the control signals for the synchronous
RIHWR
scheme, the following circuit can be used.
~~F
EN
This scheme iE..Qossible because the addresses are
stable before RD + WR and remain valid throughout
the cycle (A!L::.A1~Jt may be possible to use ALE
in place of RD + WR. but this depends upon the
memory characteristics.
EO-E1
Figure 23 : Generation of Selection Signals.
2.5. Single memory space configuration
and RD signals to form a new read signal for memory.
Note that the RAM access time must be the same as
that for the ROM - in the region of 200 nS.
Often it is useful to be able to treat program information
as data. This is especially true of development systems
where you wish to enter instructions as data, and then
execute them. To accomplish this on the 8051 it is
necessary to combine the program and data memory
spaces. Both 64 K byte areas can be map.Qruj to a single
memory space that is selected by RD, WR or PSEN.
The only modification necessary is to "OR" the PSEN
----10)---
READ
to RAM and ROM
Figure 24 : Generation of Read.
12 111Hz
-
18
9:
.... "
"3
pu ..
....."
0'"
••
•••
--............
--.
.
""'*-
III
70
-.
•••
30 •
.. 0
":"
8051
c.p.u.
AlE
.S~~
ASrIVPD
PO' 32
PO.
PO.
PO'
P03
...
11
G
80
OD
'"
7D
eD
80
':U3!g
"0'
lD
lQ
.0
20
'0
to
PO'
PO.
OE
··••
..'"
AS
A3
At
••
AD
1
":"
."
D7
DO
DO
D4
D3
DO
0'
00
U2
U3
U4
U5
U6
LS 373 (8282)
74 LS 373 (8282)
8286 (74 LS 245)
74 LS 138
74 LS 08
iiiiD
..
OE
or CMOS equivalents
for 80C31
Figure 26 : Example 8051 System.
i'(r~MIS
7·20
8051/31AH or 80C51/31
A circuit diagram of a CPU card using this system is
given below. All signals are buffered to provide drive to
external systems via a connector as well as all the
memory components. Only the first 16 K from 0 - 16 K
has been decoded into 2 K blocks that are selectable
between ROM and RAM (apart from the first block).
This is accomplished by a switch on the write (WR) line.
The ROM and RAM chips used are the HM 6616 and
HM 6116 which are directly..m.o-compatibie. Pin 21 is
either the program or write (WR) line.
ROM
+vcc
~ ROM RAM PWl21
WR _ _ _ _.~
RAM
Figure 25 : Selection of RAM/ROM.
III - INTERFACING PERIPHERAL DEVICES
This section contains details of how various devices can
be connected to the 8051, both via input/output ports
and by memory-mapping techniques. The applications
presented were used to build a small, completely selfcontained 8051 system that could be used to form the
basis of an industrial controller.
This gives rise to two sets of drivers, since MOS or TTL
cannot drive LEOs directly. These are digit drivers and
segment drivers, which are connected to the common
connections of the cathodes and anodes. These are
made from discrete transistors because large currents
are required. An active high TTL signal switches the
transistors on, using PNP transistors will allow an active
low TTL signal to turn them on.
3.1. Hexadecimal Keyboard and LED
display
+5V
A small keyboard consisting of 20 keys in a 4 x 5 matrix
was interfaced to the 8051 together with a 7 digit 7segment LED display. Because the system uses external memory it means that only Port 1 was free for
input/output. The final scheme consists of using Port 1
together with a memory-mapped latch to drive both the
keyboard and the LED display.
34Q
IIIIQI1IIII1t
selection
510Q
dVI
4-7KQ
2N2222
2N2222
selection
.,....... far .... diIpIay
~
OIlIer segments
dOlherdiljls
Other segments 01
.... _digit
(common ca_l
A-LED display
To keep hardware costs to a minimum the LED display
was multiplexed. Each of the digits is lit up in turn to give
the appearance of a continuous display. To select a
digit the segment code must be set up and then the digit
tumed on. The same code is presented to all digits but
only one of them is ever turned on, this process is
repeated for each of the digits in turn so that the whole
display is refreshed about 40-50 times each second.
The LED segments are connected in parallel as follows:
- all segments of the same LED display are connected
to the same point. This is normally done within the package, in this case common cathode devices were used,
but common anode devices also exist and can be used
in much the same manner.
- the same segments of each LED digit are connected
in parallel. All the anodes are connected together.
ThIo.-tor_ ....
Figure 28 : LED Display Drivers.
Digit selection is accomplished by using a 3 : 8 decoder
connected to Port 1 bits P1.5-P1.7. This leaves 5 bits
left for the keyboard. Of the eight signals available only
seven are actually used. The decoder signals are active
low, whereas the drivers use active high signals; in this
prototype inverters were added but the same effect
could be obtained by using a PNP transistors as the
digit driver.
Segment selection requires an external latch since only
5 bits of Port 1 remain and we require 7-bits (8 if the
decimal point is included). The latch used was a 74 LS
374 8-bit latch which is loaded on the rising edge of the
clock input. Only very simple decoding was used. Writing to any byte for which A15 is a one (1), i.e., address
8000H upwards, will write to the latch. More sophisticated
decoding can be used if the application demands it.
Data • doCked on ItIe
riaIng edge 01 a.K, whk;h
~..l!!.lhenaing
to the serne
aegmentol
.... OIIthaWRSVlBI
_LB)
1Ua.
10 _ _
Figure 27 : LED Digit Connections.
Figure 29 : Latch Configuration.
7-21
~"1ii
Q
8051/31AH or 80051/31
B-Hexadecimal keyboard
3.2. Parallel input/output
This is a small keyboard organised as a 4 x 5 matrix. It
too is connected using the 3 : 8 decoder of the LED display and the rest of Port 1. This allows an expansion of
up to 8 x 5 (40 keys) with very little hardware modification.
By adding more sophisticated decoding it is possible to
have as many latches as required. Bidirectional ports
can be constructed by using two latches in the same
manner as before.
Both latches are 8282 or 74 LS 374 or similar. The external device buses may also be connected together if
they are three-state and bidirectional. Obviously there
is no interlock or handshaking between devices so its
area of applications is somewhat limited. Adding control
via interrupt or status lines can be carried out but this
soon becomes expensive and much easier to use LSI
peripheral controller such as the 8255.
Pins P1.5-P1.7 are programmed as outputs, controlling
the decoder, while P1.0-P1.4 are inputs from the keyboard matrix. Software test to see if any of P1.0-P1.4
are zero (0) and then checks if the combination is valid.
If so the value is translated to the key value and
presented to the calling program.
3.3. Serial input/output
....
...
Pt.7
--"
74LS 3 8
3: 8
dacodar
The 8051 provides an UART giving a single full-duplex
channel. By itself the UART control cannot provide an
RS 232C compatible interface since the voltage levels
are incorrect. It is necessary to add line drivers and
receivers, suitable circuits being the 75188 and 75189.
If more serial channels are desired it is normally
necessary to add a UART such as the HD 6402 plus associated decoding and status logic. However if only one
channel is in operation at anyone time it is possible to
multiplex the 8051 serial channel between several actual channels. A two channel system, using a single
extra port pin was constructed using this method.
......-
_.
C
YO
~
.
y,
YO
v.
..
..
..
Y4
YS
VB
Y7
"--
;;"
~
l'.
~
!'-
P1.o p .1 Pt.2 Pt.3 PU
Figure 30 : Keyboard Configuration.
The diagram above shows the actual keyboard and the
expansion possibilities.
C-Software
II
The keyboard scanning and LED display refresh are
controlled by the same program. This is called periodically by interruption from one of the 8051 internal
timers. To achieve a refresh rate of 40-50 times a
second the timer interrupts the main program every 3
ms, since the program only updates a single digit at a
time. This 3 ms time delay is also used to provide
debouncing of the keyboard which is read by the same
routine. The values to be displayed are kept in a table
in RAM, changing the value in the table automatically
causes the digit of the display to be changed.
The interrupt program used is given in the appendix.
Figure 31 : Parallel Input/Output.
Figure 32 : Multiplexing Circuit for UART.
--7-22
8051/31AH or 80C51/31
another, which will more than likely cause framing errors.
But apart from this point the system works well in practice. By keeping a record of the channel and its speed
it is possible to reload the timer every channel change
and have multiple channels all operating at different
speeds.
By using more port pins and decoding logic it is possible
to expand this system. The only problem to be aware
of is when changing channels. If a character is being
transmitted it is essential that the routine waits until
transmission is finished [indicated by TI being one (1)]
before changing the channel. Otherwise some of the
character will appear on one line and the rest on
IV - CONCLUSION
able. Other applications include:
This application note has attempted to describe and
show what can be done using the 8051 and a modest
amount of hardware. All of the applications describe
have been implemented and debugged. The actual
CPU card was built on a single eurocard with another
eurocard being used forthe keyboard and LED display.
At the moment the CPU card is running a Tiny BASIC
system that controls an RS 232C terminal and
hardcopy device, such as a line printer or cassette recorder. This gives some idea of the applications avail-
• consumer products
• medical instruments
• portable instruments
• aero-space applications
• telecommunications
• automotive products
• test equipment
• etc.
In all the 8051 can be used where a small high-performance processor and associated peripherals are
necessary up to large applications requiring up to 64 K
of RAM and 64 K of ROM.
APPENDIX I
Listing of the interrupt program used to control the keyboard and display.
MCS-51 MACRO ASSEMBLER KEYBOARD/DISPLAY REFRESH PROGRAM
ISIS-II MCS-51 MACRO ASSEMBLER V2.0
OBJECT MODULE PLACED IN : FO : APPLlC.OBJ
ASSEMBLER INVOKED BY : : F1 : ASM51 APPLlC.A51 XREF
LOC OBJ LINE
1
SOURCE
$TITLE (KEYBOARD/DISPLAY REFRESH PROGRAM)
2
3
4
5
6
KEYBOARD/DISPLAY SCAN INTERRUPT ROUTINE
7
THIS ROUTINE UPDATES THE SEVEN SEGMENT DISPLAY
AND CHECKS THE KEYPAD TO SEE IF A KEY IS BEING
PRESSED. IF SO, THE FLAG "DBNCE" IS SET. THIS
CAUSES THE ROUTINE TO CHECK THE REST OF THE
KEYBOARD TO DETECT MULTIPLE CLOSURES, IT ALSO
SERVES TO DEBOUNCE THE CURRENT KEY. WHEN A KEY
HAS BEEN SEEN THE FLAG "CHARFND" IS SET TO
INDICATE THAT A VALID KEY CODE IS IN THE BYTE
"LAST KY". NO MORE KEYS WILL BE READ UNTIL THE
KEY IS RELEASED - INDICATED BY CLEARING
"CHARFND".
8
9
10
11
12
13
14
15
16
17
18
19
20
21
P1.5-P1.7 = NUMBER OF COLUMN OUTPUT
P1.0-P1.4 = NUMBER OF ROW INPUT
22
23
7·23
II
8051/31AH or 8OC51/31
LOC OBJ
0030
0031
0032
0033
FFFF
ooF4
0000
0000
0001
LINE SOURCE
24 ; DEFINITION OF CONSTANTS AND WORKING VARIABLES
25;
AT30H
26
DSEG
27 ;
28 LAST_KY: DS
; LAST KEY READ FROM KEYBOARD IN MATRIX
; NOTATION.
29
30 ROW NO: OS
1
; NUMBER OF LINE STROBED ON KEYBOARD.
; NUMBER OF DISPLAY DIGIT CURRENTLY LIT.
31 DIGIT:
DS
1
32 DATADDR: DS
1
; DIGITS OF DISPLAY
33 DISPLAY
EQU
OFFFFH
; ADDRESS FOR 7-8EGMENT DISPLAY LATCH
; TIME BETWEEN INTERRUPTS
34 INTVALH
EQU
OF4H
35 INTVALL
EQU
OOH
36
37
BSEG
ATO
38;
39 CHARFND: DBIT
; CHARACTER VALID FLAG
40 DBNCE:
DBIT
; DELAY FLAG
41
42 ; END OF VARIABLE DEFINITIONS
43
44
CSEG ATO
45
0000
00000195
oooB
000B0130
0030
oo30COEO
0032C083
0034C082
II
0036 E590
003844EO
003AF4
00386015
oo3D2532
003F2oo109
0042F530
0404D201
0046853231
00498010
0048853009
004ED2OQ
ii
46
47
48
49
50
51
52
53
54
ORG
RESET
AJMP
START
ORG
TlMERO
AJMP
KEYSCAN
; RESET VECTOR
; JUMP TO INTERRUPT ROUTINE
ORG
30H
; START AFTER OTHER INTERRUPT VECTORS
55;
56 KEYSCAN: PUSH ACC
; SAVE REGISTERS
57
PUSH DPH
58
PUSH DPL
59 ,
60 ; READ THE VALUE FROM THE PORT. IF NO KEYS HAVE BEEN DEPRESSED BITS P1.0-P1.4
61 ; WILL BE ONE (1). THIS IS TESTED BY INVERTING AND LOOKING FOR ZERO. IF A KEY HAS
62 ; BEEN PRESSED THEN THE DIGIT NUMBER IS ADDED BACK TO CREATE THE FULL CODE.
63
64
MOV
P,P1
; READ PORT-NEW DATA IN P1.4-P1.0
A, OEOH
; MASK-IF NO KEY, ACC IS FFH
65
ORL
66
CPL
A
; INPUT IS THE INVERSE
67
RNISH
; TEST FOR A KEY
JZ
ADD
A,DIGIT
; FORM FULL ADDRESS-ADD DIGIT NUMBER
68
69
JB
DBNCE,CHECK ; TEST DEBOUNCE FLAG
70
71 ; FIRST DEPRESSION-sAVE THE KEY CODE AND THE DIGIT NUMBER. SET THE DBNCE
72 ; FLAG TO INDICATE THIS HAS BEEN DONE.
73
74
MOV
LAST_KY,A
; FIRST TlME-8TORE ACC
75
SETB DBNCE
; SET DBNCE FLAG
76
MOV
ROW_NO,DIGIT ; SAVE DIGIT NUMBER
77
SJMP NO_KEY
; KEY NOT VALID YET
78 ,
79 ; IF THE DBNCE FLAG IS SET THEN THIS CODE CHECKS ALL OTHER KEYS IN TURN. WHEN IT
80 ; SEES A KEY PRESS IT TESTS FOR THE SAME KEY AS BEFORE, THIS DELAY ALSO PROVIDES
81 ; TIME TO ELIMINATE CONTACT BOUNCE. IF IT IS THE SAME KEY THEN A VALID KEY HAS
82 ; BEEN SEEN, IF NOT THE DBNCE FLAG IS RESET AND THE PROGRAM RESTARTS.
83;
84 CHECK:
CJNE A,LAST_KY,DIFF ; SAME KEY AFTER DEBOUNCE?
SETB CHARFND
; YE&CHARACTER VALID
85
7·24
8051/31AH or 8OC51/31
LOC OB.)
00508009
LINE
86
87
88
89
90
91
92
0052 E532
93
0054853104 94
0057C201
95
0059C200
96
97
98
99
100
101
102
103
005B90FFFF 104
005EE4
105
106
005FFO
0060 E532
107
00622420
108
0064F532
109
0066441F
110
0068F590
111
112
113
114
115
116
117
006AE532
118
006CC4
119
120
006D03
121
006E2433
0070es
122
123
0071 COED
124
0073E6
125
0074FO.
126
0075DOEO
127
0077es
128
129
130
131
132
0078118E
007AD082
133
134
007CD083
135
007EDOEO
136
008032
137
138
139
140
141
142
0081 C201
143
0083C200
0085753200 144
00885389FO 145
OO8B438901 146
OO8E758AOO 147
0091758CF4 148
SOURCE
SJMP
NO_KEY
; CONTINUE
,
; HERE THERE ARE NO KEYS PRESSED AT ALL. THE CURRENT DIGIT NUMBER IS
; COMPARED WITH THAT OF THE LAST VALID KEY. IF THEY ARE THE SAME THEN THE KEY
; HAS BEEN RELEASED AD THE CHARFND FLAG CAN BE CLEARED, OTHERWISE
; CONTROL PASSES DIRECTLY TO THE REFRESH ROUTINE
;
FINISH:
MOV
A,DIGIT
; NO KEYS PRESSED-LOAD PRESENT LINE
CJNE A,ROW_NO,NO_KEY ; SAME AS LAST TIME ?
DIFF:
CLR
DBNCE
; YES-RESET FLAGS FOR NEXT KEY
CLR
CHARFND
; REFRESH DISPLAY ROUTINE. LIGHTS EACH DIGIT OF THE DISPLAY IN TURN
,
; THE PRESENT DIGIT IS BLANKED BY CLEARING THE SEGMENTS. AFTERWARDS THE NEXT
; DIGIT IS SELECTED BY INCREMENTING THE DIGIT NUMBER OF P1.5-P1.7, DONE BY
; ADDING 20H TO THE PRESENT PORT VALUE.
;
NO_KEY:
MOV
DPTR,
DISPLAY ; ADDRESS OF OLITPLIT LATCH FOR DISPLAY
CLR
A
; BLANK CHARACTER
MOVX @DPTR,A
; OUTPLIT TO DISPLAY
MOV
A,DIGIT
; CURRENTLY LIT DIGIT
ADD
A, 20H
; NEXT DIGIT
MOV
; STORE FOR NEXTl1ME
DIGITA
ORL
; SET P1
A, 1FH
; OLITPLIT ACC TO SELECT NEXT DIGIT
MOV
P1A
;
; LOAD THE LATCH WITH THE CORRECT CODE FROM THE TABLE. THIS IS DONE BY
; SHIFllNG THE DIGIT NUMBER AND USING IT TO INDEX THE RAM TABLE CONTAINING
; THE 7-SEGMENT CHARACTER CODES. REGISTER RO IS SED TO INDEX THE TABLE
; AFTER HAVING BEEN SAVED FIRST. IT IS RESTORED AFTERWARDS
MOV
SWAP
RR
ADD
XCH
PUSH
MOV
MOVX
POP
XCH
A,DIGIT
A
A
A, DATADDR
A,RO
ACC
A,@RO
@DPTR,A
ACC
A,RO
; GET DIGIT NUMBER AGAIN
; DIGIT =P1.3-P1.1
; DIGIT =P1.2-P1.0
; ADD RAM TABLE ADDRESS
;SAVERO
; SEVEN SEGMENT CODE OF DIGIT
; OLITPUT TO DISPLAY
; RESTORE OLD VALUE OF RO
; RELOAD THE TIMER FOR THE NEXT INTERRUPT IN 3 MS. RESTORE ALL THE REGISTERS
; AND RETURN FROM THE INTERRUPT.
ACALL
POP
POP
POP
REl1
RELOAD
DPL
DPH
ACC
; LOAD TIMER AGAIN
; RESTORE VARIABLES FROM
; STACK AND EXIT INTERRUPT
,
; END OF INTERRUPT SERVICE ROUTlNE
;
LOAD:
RELOAD:
CLR
CLR
MOV
ANL
ORL
MOV
MOV
DBNCE
CHARFND
DIGIT, 0
TMOD, OFOH
TMOD, 01H
TLO, INTVALL
THO, INTVALH
7-25
; INITIALISE VARIABLES
; SET UP KEYBOARD TIMER
; LOAD DELAY
ii
II
- -_ _ _ _ _ _ _ _ _ _ 8051/31AH or 8OC51/31
LOC OBJ
009422
0095 1181
LINE
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
SOURCE
RET
; JUMP TO MONITOR
;ENDOFINITIALISATION
.
START:
ACALL
LOAD
; START OF PROG-SET UP TIMER
..
REST OF PROGRAM
CONTINUES FROM HERE
,
END
MCS-51 MACRO ASSEMBLER KEY BOARD/DISPLAY REFRESH PROGRAM
XREF SYMBOL TABLE LISTING
NAME
TYPE
ACC ................. DADDR
CHARFND ........ B ADDR
CHECK ............ C ADDR
DATADDR ........ DADDR
DBNCE ............ B ADDR
DIFF ................. CADDR
DIGIT ............... D ADDR
DiSPLAy .......... NUMB
DPH ................. DADDR
DPL. ................. DADDR
FINISH ............. C ADDR
INlVALH .......... NUMB
INlVALL ........... NUMB
KEYSCAN ........ C ADDR
LAST-KY............ D ADDR
LOAD ............... CADDR
NO-KEy............. C ADDR
P1 .................... DADDR
RELAOD .......... C ADDR
RESET ............. C ADDR
ROW-NO .......... D ADDR
START ............. C ADDR
THO .................. DADDR
TIMERO .. ,. '" ..... C ADDR
TLO .................. DADDR
TMOD .............. DADDR
VALUE
OOEOH
0020H.0
004BH
0033H
0020H.1
0057H
0032H
FFFFH
0083H
0082H
0052H
00F4H
OOOOH
0030H
0030H
0081H
005BH
0090H
008EH
OOOOH
0031H
0095H
008CH
OOOBH
008AH
0089H
ATTRIBUTES AND REFERENCES
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
56123126135
39 8596143
6984
32 121
40 69 75 95 142
8495
31 687693107109118144
33 104
57134
58133
6793
34 148
35 147
5256
28 7484
142 154
778694104
64111
132147
46
30 7694
48154
148
50
147
145146
REGISTER BANK (S) USED: 0, TARGET MACHINE(S) : 8051
ASSEMBLY COMPLETE, NO ERRORS FOUND
= ....
lHh'11m
7-26
8051/31AH or 80C51/31
APPENDIX 2
Circuit diagram
The circuit diagram for the CPU card is given overleaf.
All connections, except to RAM/ROM are shown. The
decoding has been carried out in 2 K blocks allowing the
use of HM6516, HM65161 or HM6116 RAMs and the
HM6616 PROM. All of these components are directly
pin compatible allowing easy system changes or
upgrades. Although this 8051 card uses an 8031, it is
possible to plug in a preprogrammed 8051. Changing
the EA switch setting will cause the internal ROM to be
enabled.
Because the program memory time access is about
200 ns the only EPROMs that can be used are the
2732A or 2764. The 2716 EPROMs are not guaranteed
to this speed. In practice the prototype system
described here works well with 2716 EPROMs from
four different manufacturers. It must be stressed that
this is under laboratory conditions, working well within
the manufacturers specifications. If speed is not a problem, slowing the processor clock will increase the available access time, guaranteeing operation under worst
case conditions.
8051 CPU CARD
=
{--------------'1~3,-14 iii'I1PJJ
30
8051
::111
"'11
~
~"
U214 LS 313 (8282)
U314 LS 313 {8282,
U4 8286 (74LS 245)
U51415138
U674 LS08
U774LSOO
UB74LS 32
0915189
UlO15188
r--+~-----------~~
}-L-_ _ _+-_ _ _ _ _ _ _ _ _ _
",CMOS_
bllOC31
7-27
~
..
------- ~~ IllS
---Se-pt-em-b-er-1-g8-9
AN1040
APPLICATION NOTE
DIFFERENCES BETWEEN THE 8051 AH
AND THE 80C51
This article discusses the few differences which exist
between the HMOS 8051AH and the CMOS 80C51
microcontrollers. From the CMOS family's point of view,
these differences consist of the addition to the software
of two instructions for power saving and, hardwarewise,
the inversion of the input from an external clock on inputs XTAL 1 and XTAL2, and the increased value of the
resitance of input RST.
SOFTWARE DIFFERENCES BETWEEN THE TWO FAMILIES
The 80C51 microcontroller has two additional power
saving modes: POWER-DOWN and IDLE.
These additional modes are accessed by the PCON
(87H) register. To activate these modes, it is simply
necessary to put a "1" in bit PO = PCON. 1 or bit IDL =
PCON.O
registers and the internal RAM is fixed. Only a reset via
the RST input enables exit from this status. The time
taken by the 80C51 to exit from this mode is equivalent
to the duration of the RESET and depends on the
oscillator's start-up time, the operating frequency and
the quartz used. If tosc is the oscillator's start-up time,
the duration of RESET should be equal to tosc + 2
machine cycles.
When the 80C51 returns to the normal mode, only the
content of the internal RAM remains unchanged, all the
special registers are reconfigured as a result of the
RESET.
POWER DOWN
This mode is entered by setting PO = PCON.1JQ "1".
As shown in figure 1, the oscillator is stopped (PO = 0)
and the 80C51 's activity is suspended.
While this mode is active, the status of the special
a..oa<
GENERAlOR
OSOUAlOR
01
02
PO - - t - - - - - - - - - - '
Figure 1.
7-29
MATRA MHS
8051AH AND 8OC51 _ _ _ _ _ _ _ _ _ _ _ __
etc. operations are suspended. Only the TIMERs, the
UART and the INTERRUPTS remain under the clock's
control.
Power dissipation which was 1SmA at VCC = SV and
at 12MHz, drops to 3mA. Once this mode has been
entered, the status of the special registers and the internal RAM is frozen.
There are two ways of exiting from this mode, either by
a reset or by means of any of the interrupts.
A reset, maintained during 2 machine cycles has the
same effects as a normal reset: the internal RAM's content is conserved and the special registers assume the
values given in table 1.
The interrupt sub-routine, which enables exit from this
mode, will be executed and instruction RETI will result
in the continuation in sequence of the instruction placed
immediately after the IDLE mode instruction.
Table 1 shows the content of the special registers after
execution of a reset.
REGISTERS
PC
ACC
B
PSW
SP
DPTR
PO-P3
IP
IE
TMOD
TCON
THO
TLO
TH1
TL1
SCON
SBUF
PCON
CONTENT
OOOOH
OOH
OOH
OOH
07H
OOOOH
OFFH
XXXOOOOOB
OXXOOOOOB
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OXXXOOOOB
DISSIPATION
Table 2 shows the different dissipation according to the
operating mode and the technology used.
OPERATING
MODE AT 12 MHZ 80131/51AH
VCC = 5 V
Normal
125 mA
Power-down
Idle
IDLE MODE
This mode is activated by setting bit IDL = PCON.O to
"1". In this mode (as shown in figure 2), the CPU is no
longer driven by the clock and its arithmetical, logical,
a...oCK
GENERAlOR
OSaLLATOR
III
80C31/
80C51
15 mA
SOJ.IA
3mA
TIMER 0 AND 1
~~--------
IPO
UART
INTERRUPTS
AND
IIOL _________
~
~---CPu
Figure 2.
Table 3 shows the status of the different Inputs/Outputs during the two power saving modes.
PROGRAM
MEMORY
IDLE
Internal
IDLE
External
Power-down
Internal
Power-down
External
MODE
ALE
PSEN
PORTO
PORT1
PORT2
PORT3
1
1
1
1
0
0
0
0
Port Data
Floating
Port Data
Floating
Port
Port
Port
Port
Port Data
Address
Port Data
Port Data
Port
Port
Port
Port
7-30
Data
Data
Data
Data
Data
Data
Data
Data
- - - - - - -_ _ _ _ _ _ _ 8051AH AND 80C51
HARDWARE DIFFERENCES BETWEEN THE TWO FAMILIES
EXTERNAL CLOCK
The impedance of input RST and the input on XTAL 1,
when an external clock is used, are the differences between the two families.
A fundamental difference is the case of the driving of the
microcontroller by an external clock.
Where as driving is on input 18 (XTAL2) for the 8051 AH,
it is on input 19 (XTAL1) on the 80C51 (see figure 3).
8051AH
80C51
18
18
-
External clock- XTAL2
19
-
19
External clock-
XTAL1
Figure 3.
RSTINPUT
The value of the RST input resistor is changed from 8.2
k to 125k in the CMOS version. As a result, the value
of the reset capacitance can be lower while conserving
the same time constant.
7-31
-------i"dl MtS
---Se-pt-em-b-er-1-gS-9
AN1041
APPLICATION NOTE
STATIC WORKING OF MHS C51
MICROCONTROLLERS USED FOR THE
SYNCHRONIZATION OF SLOW PERIPHERALS
The MHS C51 family of microcontrollers are built in
CMOS technology and are 100 % static. Their feature
is that they can operate at very low frequency and can
even stop the clock whilst operating without altering execution of the program.
LIMIT OF INTERFACING WITH A SLOW PERIPHERAL
In certain applications, for example that given in figure 1, it often happens that the peripheral's access time
is longer than the microcontroller's read/write cycle.
Therefore, it is necessary that the peripheral can subject the microcontroller's activity to its own speed to ensure correct operation of the cycle.
nbits
P2
NJ-An
WRJ
RDI
IWR
lAD
ALE
,1
8OC511~~
83C154
'0V'I0
• .....,
8 bits
Memory
L
A 8 bits
AD-A7
T
C
H
00-07
'--
8 bits
II
J
Figure 1 : Interfacing with a peripheral.
The timing diagram in figure 2 shows the different parameters that must be taken into account in order to solve
the problems of peripheral access time.
Thus, one of the parameters, tplatch, (latch address
propagation time) introduces a delay which varies according to the latch technology used (ct. TAB1).
A4fi1! 01-8nS
TAB 1. tpd = tplatch according to technology used.
7-33
MATRA MHS
STATIC WORKING OF MHS C51 MICROCONTROLLERS
READ CYCLE
o
0+1
aJ(
ALE
AD-A7
~t------'X,,------,'[
l
~
~-y
f-------'>-DOC
l~J-TRlW
j~/
ADI
Figure 2 : Peripheral read access.
operating frequency is 12 MHz and the latch is a
74HCT193, the peripheral must respond in at least:
The peripheral's maximum response time is given by
other parameters relating to the microcontroller :
TRDLV and TAVDV. Therefore, if the microcontroller's
II
- trep < TADV = (9 x TCLCL - 165) - tplatch = 585 - 49 = 563 ns
in relation to the appearance of the address
and
- trep < TRLDV = (5 x TCLCL -165) = 251 ns
in relation to the appearance of the command
tion to the command is 600 ns, the command cycle must
be prolonged by: 600 - 251 =349 ns or349/83.34 clock
periods at 12 MHz.
If the peripheral's response time is greater that 251 ns
or 536 ns, it is necessary to prolong the cycle until the
peripheral has completed the command.
For example, if the peripheral's response time in rela-
7-34
STATIC WORKING OF MHS C51 MICROCONTROLLERS
SOLUTION FOR INTERFACING WITH A SLOW PERIPHERAL
Figure 3 is a schematic of a typical application in which the peripheral controls the microcontroller's by means of the
Ready signal.
80C51/C52/C154
XTAL1
AO-A15
RR
DD-D7 DW
RST
rD1
IVCC
I
b
i
t
A
N
b
i
R
»
s s
N
0
R
Ready
DD-D7 RW
AO-A15
0
D
t
I
lEW
f----r).
8 8
74LS124
D R
PERIPHERIQUE
Figure 3 : Interfacing with a slow peripheral.
Figure 4 gives the timing diagrams for operating with a
peripheral that is not adapted to the microcontroller's
read cycle. The data arrives too late on the data bus 0007. Therefore, the access time, TROLV and TAVOV,
must be prolonged by a value equivalent to twait.
The schematic in figure 3 enables prolongation of the
read/write cycle for as long as the peripheral requires
in order to execute the command generated by the
microcontroller.
The microcontroller is equipped with an external oscillator, built with a 74LS124, driven by a quartz and connected to XTAL 1. The 74LS124 oscillator's operation
can be blocked by means of its /EW input. A "1" applied
to this input forces the 74LS124 to terminate the current
clock cycle and to stop on a low level. A "0" level on
inpuVEW reinitiates the clock which effectively restarts
on a level "1 ". Replacement of this circuit by a 748124
is not possible, once enabled this circuit requires several cycles before it becomes stable.
7-35
STATIC WORKING OF MHS C51 MICROCONTROLLERS
Therefore, the particularity of this circuit is to provide a stop and restart specific to the microcontroller.
XTAL1
~ll
ALE
~ll
II
IWR+/RD
t:~
Ready
~
l-twaitJ
ADO-AD7
11
Figure 4 : Timing diagrams for Figure 3.
At the beginning of the read/write cycle, the peripheral's
Ready output is at "1" and inpuVEW is at "0". When a
command is generated, IWR or /RD = 0, inputlEW goes
to "1" and the oscillator stops effectively on completion
of its current clock cycle, setting its Ready output to "0".
At the same time, the command synchronizes the
Ready signal's transition to level "0". After prolonging
the read cycle by twait, the Ready signal's transition to
"1" indicates to the microcontroller that the peripheral
has terminated execution of the command and that it
can complete the current cycle.
Another solution, if no 74LS124 is available, is to use
the schematic shown in figure 5.
Ready
EXTERNAL CLOO< --4-_-~U
Figure 5.
7-36
XTAL1
STATIC WORKING OF MHS C51 MICROCONTROLLERS
microcontrolier. The timing diagrams in figure 6 show
the electrical operation of this circuit.
This circuit performs the same functions as the
74LS124 circuit, that is to effectively stop and restart the
EXTERNAl a..oa<
IWR+/RD
/0
XTAL1
Figure 6.
voltage VIH (2 V) at the end of a time equivalent to twait,
X1 = 1 and X2 = a and the Ready output returns to "1".
The microcontrolier terminates the current command
by raising the write/read signal.
The peripheral controls the Ready signal and several
circuit can be used. Figures 7 and 8 show two of the
many possible solutions.
MONOSTABLE Timer
vee
R
X1
IWR
JRD
Ready
vee
CextlRext
74LS121
Rint
/0
L---.-_ _ _ _ _ _..J
Ready
twait = 7*R*C
2KQ result
=A
remainder =B
MHS B = FF
OKI B = 00
I
II
CONDITIONAL JUMP
Conditional jumps JC, JNC, JZ and JNZ are single byte
instructions that execute in 2 machine cycles. Before
branching to the new address :
- MHS increments the PC twice.
- OKI increments the PC once.
These differences are discussed in the following paragraphs.
LONG JUMP
The long jumps, LCALL and LJMP are three-byte instructions that execute in 2 machine cycles. Before
branching to the new address:
DIVISION BY ZERO
Division by zero is performed by putting the numerator
in register B and the denominator in register A. The
result in the division is stored in register A and the
A460 / 01-8775
- MHS increments the PC 3 times,
- OKI increments the PC twice.
7-49
MATRA MHS
83C154
SERIAL PORT
Transmission clock start-up in modes 1 , 2 and 3.
TIMER 1
fbaud
- MOV TCON, #XX
- MOV SCON, #XX
- MOV SBUF, #XX
The divider by 16 which, ultimately, generates the clock,
is controlled differently according to the manufacturer:
- MHS : the divider starts on completion of RESET,
- OKI : the divider starts after the following instructions:
The following timing diagrams illustrate the differences:
MHS
fbaud
WRITING IN
SBUFF
TXD
START8JT
OKI
fbaud
WRITING IN
SBUFF
STARfBlT
DO
TXD
7-50
83C154
INPUT/OUTPUT PORTS
The port write instructions execute in 2 cycles. The data
arrives at the gate outputs on the second instruction
cycle. The rapidity with which the data arrives at the
gates varies with the manufacturer:
MHS : the data arrives in phase with the 1st clock cycle
of the instruction cycle following the write cycle.
OKI : the data arrive in phase with the 6th clock cycle
of the 2nd write cycle.
C1
C2
MHSPORT
OKIPORT
INTERRUPTS
When a TIMER (0, 1 or 2) times out, the interrupt request
is generated in the same instruction cycle in the case of
the MHS microcontroller and in the next cycle in the case
of the OK!.
Ci
Ci+ 1
TIMER 2 OVERFLOW
SIGNAL TF2 SETTO 1
MHS
OKI
7-51
fiilijM IS
83C154
INTERQ SIGNAL INTERRUPT REQUEST
Ci+1
Ci
CONCLUSION
In pratice, all these differences are transparent from the
User's point of view. Only the differences in the division
by zero and the interrupt requests form the TIMERS are
i'1il
likely to prevent full compatibility between the two circuits.
7-52
PACKAGING
~
__________ ~mllll
8-1
------IIIil1i1ll
MIS------
PACKAGING
PACKAGE SELECTION GUIDE
PART NUMBER
PGA
PLASTIC PACKAGE
QUAD
OIL
PLCC
FLAT
-
5H
L09
J44
-
X22
K04
F03
80C32/52
C4
EA
J44
-
X29
K03
F04
80C 154/83C 154
-
C4
EA
J44
-
X29
K16
F04
80C732/752
-
C4
EA
J44
-
X29
K16
-
80C31/51
*
CERAMIC PACKAGE
SIDE
CERDIP LCC
JLCC
BRAZE
Contact your nearest sales office for other requirements.
STANDARD NOTES FOR PLASTIC D.I.L.
7 - Leads within 0.127 radius of true position at gauge
plane with MMC (maximum material condition) and
unit installed.
1 - Controlling dimensions: inches
In case of conflict or interpretation between the
english and metric tabulation, the inch dimensions
are controlling.
STANDARD NOTES FOR PLCC
1 - Controlling dimensions: inches.
In case of conflict or interpretation between the
english and metric tabulation, the inch dimensions
are controlling.
2 - Dimensioning and tolerancing per ansi y
14.5M-1982.
3 - Dimensions A.A 1. and L are measured with the
package seated in jedec seatind plane gauge GS-3.
2 - Dimensioning and tolerancing per ansi y
14.5 M-1982.
4 - D and E1 dimensions do not include mold flash or
protusions. Mold flash or protusions shall not exceed. 010 inch (0.25 mm).
3 - D and E1 dimensions do not include mold flash or
protusions. Mold flash or protusions shall not exceed 0.25 mm (.010 inch).
5 - E and eA measured at the leads contrained to be
perpendicular to the base plane.
6 - eB is measured at the lead tips with the leads uncontrained.
STANDARD NOTES FOR PLASTIC QFP
1 - Controlling dimensions: mm.
7 - Corner leads may be configured as shown in figure2.
2 - Dimensioning and tolerancing per ansi y 14.5 M1982.
3 - D1 and E1 dimensions do not include mold flash or
protusions. Mold flash or protusions shall not exceed 0.25 mm (.010 inch).
STANDARD NOTES FOR CERAMIC D.I.L.
1 - Controlling dimensions: inches.
In case of conflict or interpretation between the
english and metric tabulation, the inch dimensions
are controlling.
4 - Datum plane -H- located at top of mold parting line
and coincident with top of lead, where lead exit plastic body.
2 - Dimensioning and tolerancing per ansi y
14.5M-1982.
5 - Datums -A- and -D- to be determined where center
of leads exit plastic body.
3 - Dimensions A.A 1. and L are measured with the
package seated in jedec seatind plane gauge GS-3.
6 - When NBR of lead per side is even. Datums -A- and
-D- are determined by adding the half pitch basic
dim to the centerline of the adjacent lead.
When NBR of lead per side is odd. Datums -A- and
-0- are determined by the centerline of the lead.
4 - E and eA measured at the leads contrained to be
perpendicular to the base plane.
5 - eB is measured at the lead tips with the leads uncontrained.
6 - Corner leads may be configured as shown in
figure 2.
8-3
MATRA MHS
PLCC PACKAGE
CODES: K03 - K04 - K16
MM dimens.
min
A
A1
D
D1
D2
E
E1
E2
e
G
H
J
K
REV: C
44 PINS PLCC
max
4.57
4.20
2.29
3.04
17.40
17.65
16.66
16.51
14.99
16.00
17.40
17.65
16.51
16.66
14.99
16.00
1.27 B.S.C
1.07
1.22
1.07
1.42
0.51
0.33
0.53
PKG STD:
IN dimens.
min
max
.165
.180
.120
.090
.685
.695
.656
.650
.590
.630
.695
.685
.656
.650
.590
.630
.050 B.S.C
.042
.048
.042
.056
.020
.013
.021
00
H
8-4
CERDIP DUAL IN LINE
CODES: 5H - C4
REV: D
CERDIP 40 PINS.600
MM dimens.
IN dimens.
min
max
min
max
A
4.07
5.58
.160
.220
A1
0.51
1.78
.020
.070
A2
-
5.08
-
.200
B
0.38
0.51
.014
.020
B1
1.15
1.39
.045
.055
C
0.20
0.38
.006
.015
2.070
INDU
D
52.00
53.87
2.047
D1
0.25
-
.010
-
E
15.41
15.62
.607
.615
E1
12.95
14.73
.510
.580
e
2.54 B.S.C
.100 B.S.C
eA
15.24 B.S.C
.600 B.S.C
eB
-
17.78
-
.700
L
3.17
5.06
.125
.200
A.U
-CD ._,
m,
"
.
~ ~~
(EJ ~
r
I
-1
I
'181~
81 MAX •
-- JPAjJUII .. '/;' · '~
JL 'UH1
.UlIMa
01
PKG SrD : 01
8-5
.
-1"
',1)::1,1.1--1. p,.
.
1-81
8
I!I
k-01
'}
f
\
~•• c--l
~U
.1
e•
LEADLESS CHIP CARRIER
CODES: L09 - EA
44 LOS .050 CENTER LEAD LESS SQUARE CHIP CARRIER
MM dimens.
min
max
IN dimens.
min
max
A
1.47
1.83
.058
.072
A1
1.73
2.26
.068
.089
B
0.635TYP
.025TYP
D
16.33
16.82
.643
.662
E
16.33
16.82
.643
.662
e
h
1.27 B.S.C.
.050 B.S.C.
1.016
.040
j
0.51
.020
ND
11
11
NE
11
11
PKG STD: 01
8-6
REV:C
J LEADED CHIP CARRIER
CODE: J44
44 LEADS JLCC. LEADED J TYPE
REV: C
A
o
MM dimens.
IN dimens.
min
max
min
max
A-B
17.40
17.65
.685
.695
A1-B1
16.26
16.76
.640
.660
0
1.27 B.S.C
E
0.51 TYP
.020 TYP
F
2.03 REF
.080 REF
.050 B.S.C
J
0.89
1.14
.035
.045
K
1.50
1.80
.059
0.71
L
2.64
3.25
.104
.128
Q
14.99
16.00
.590
.630
N1
11
N2
11
B 81 ...:..'+-+-+
11
11
PKG STD : 01
8-7
PLASTIC DUAL IN LINE
IN dimens.
MM dimens.
min
max
min
max
A
-
5.08
-
.200
A1
0.38
-
.015
A2
3.18
4.95
B
0.36
0.56
.014
.022
B1
0.76
1.78
.030
.070
.125
.195
C
0.20
0.38
.008
.015
D
50.29
53.21
1.980
2.095
E
15.24
15.87
.600
.625
E1
12.32
14.73
.485
.580
e
eA
eB
L
D1
2.54 B.S.C.
.100 B.S.C.
15.24 B.S.C.
.600 B.S.C.
-
REV: D
40 PINS PLASTIC .600
CODES: X22 - X29
-
17.78
2.93
3.81
.115
0.13
-
.005
II
A1
-' 1-01
.700
.150
-
PKG STD: 02
8-8
L
PLASTIC QUAD FLAT PACK
CODE: F03 - F04
40 PINS PLASTIC QUAD FLAT PACK. SQUARE GULLWING
MM dimens.
min
A
c
D1-E1
D-E
e
f
J
L
N1-N2
max
o
IN dimens.
max
min
2.08
2.43
0.13
0.20
9.63
10.13
13.90
14.50
.80 B.S.C.
0.36
0.46
0.15
0.30
0.51
1.11
.081
.095
.005
.008
.379
.399
.547
.559
.03158.S.C .
.014
.018
.006
.012
.020
.044
11
11
8-9
REV: C
QUALITY
~___________ ~IIIS
9-1
-----~i_jMtS-----QUALITY
1 - INTRODUCTION
1.1 - STATEMENT OF SCOPE
To achieve these requirements, MATRA MHS has
started in early 1988 a Quality Improvement Program.
The objective of this program is to call for continuous
Progress and committment of every employee to total
Quality.
This section establishes the detail requirements for
MATRA MHS' circuits screened and tested under the
Quality Assurance Program.
Included in this section are the Quality standards and
screening methods for commercial parts which must
perform reliable in the field.
The reliability approach at MATRA MHS is based on
designing in reliability rather than testing for reliability
only. The latter is applied to check and confirm that
sound design with quality and reliability ground rules
are observed and correctly executed in a new product
design.
1.2 - APPLICABLE DOCUMENTS
The following documents form a part of this section to
the extent referenced herein and provide the foundation of Matra MHS Quality Program:
MIL-M-38510G
"General Specification of
Microcircuits"
MIL-STD-883C
"Test Methods and Procedures for
Microelectronics"
ESAlSCC9000
"European Space Agency Specification for Microelectronics"
Reliability engineering becomes involved as early as
concept review of a new product and continues to
remain involved through design and layout reviews. At
these critical development points of a new design,
basic reliability layout guidelines are invoked to insure
an all around reliable design. This concept is reflected
by the MATRA MHS reliability procedures which encompass mandatory first run product evaluation. This
is done at not only the circuit level, but also at the
process and package level. Reliability engineering approval is required before new product designs are
released to manufacturing.
The MHS Quality Assurance Manual, which is available upon request, describes the total function and
policies of the organization to assure product reliability
and quality. All customers are encouraged to visit the
MATRA MHS facilities and survey the deployment of
the Quality function.
Both maximum rated and accelerated stress conditions are performed. Acceleration is important to determine how and at what stress level a new design would
fail. From this information, necessary design changes
can be implemented to insure a wider and safer margin
between the maximum rated stress condition and the
device's stress limitation.
MATRA MHS maintains a Quality Assurance Program
(QAP) using the above defined documents as a guide.
This program assures compliance with the requirements and quality standard of control drawings and the
requirements of this specification.
PPM PROGRAM
• For standard and volume products, MHS proposes
to his customers a PPM program. Cooperation
agreement could be established with customer willing to engage such an improvement program.
• PPM programs are already existing and we expect
an optimum of 2 or 3 customers agreements by
product. It is obvious that the upgrade of the quality
level achieved is effective for all customers.
The special military and space programs will also be
found useful by those MATRA MHS customers who
must generate their own procurement specifications
(see hi-reI databook).
Use of the enclosed MATRA MHS standard test tables,
test parameters and burn-in circuits will aid in reducing
specification negociation time.
1.3 - QUALITY AND RELIABILITY AT MATRA
MHS
1.4 - AGENCIES QUALIFICATIONS
As part of specific qualification on military or space
programs, MATRA MHS received several agreements
from french agencies.
Our Quality Division strives to assure that the quality
and reliability of products shipped to customers are
high quality level and consistent with customer's requirements.
9-3
MATRA MHS
D
•
delivery of MOS products and on customer support on
custom design.
In 1986, MHS received the RAQ 1 certification (RAQ 1/
AQAP 1 Regulation quality assurance level 1) from the
SIAR (service de surveillance industrielle de
I'armement).
The major MHS technologies and products are agreed
by french telecommunication agency (CNET). These
products are in qualified list (LNZ).
The RAQ1 means that MATRA MHS quality assurance procedures satisfy design, manufacturing and
2 - QUALITY CONTROL
FLOW
[
PROCESS
TYPICAL ITEM
• Resistivity
• Bow-particles
• Flatness
Silicon wafers
• Taper
Incoming Inspection
• Oxygen content
• Dimensions
• Appearance
• Defects
• Dimensions
Masks
Incoming Inspection • Registration
• Conformity
FREQUENCY
Every
manufactured lot
REQUIREMENTS
25 Wafers/LOT
Every mask
Oxidize
Thickness
Every run
3 Wafers/run
5 points/wafer
Implant
Resistivity
Thersal wave
Every run
2 Wafers/run
5 points/wafer
Diffuse
Resistivity
Thickness
Every run
3 Wafers/lot
5 points/wafer
Silicon nitride
Thickness
Critical dimensions (*)
Every run
3 Wafers/run
5 points/wafer
Gate oxide
Thickness
Defect rates
VFBDVFB
Every run
3 Wafers/lot
5 points/wafer
Polysilicon
• Resistivity
• Thickness
• Critical dimensions (*)
• Sem Inspection
Metallization
• Resistivity
• Thickness
• Critical dimensions (*)
• Sem Inspection
Periodical
Passivation
• Doping
• CVD Thickness
• Sem Inspection
Every run
Periodical
3 points/wafer
Test site
Electrical charact.
Every Wafer
5 PCM/wafer
Blacklap
Thickness
Every lot
1 wafer/lot
QC visual gate
Visual
Sampling
5 wafer/lot
Electrical charact.
100 % chips
Wafer sort
• All Critical Dimensions (After etching) : Every lot
·3 wafers/lot
- 5 pOintslwafer.
Table 1 : Quality flow chart of wafer processing.
9-4
Every run
3 Wafers/lot
5 points/wafer
Periodical
Every run
1 Wafer/run
2.1 - PROCESS CONTROLS
company of MATRA MHS's designated representative, that suitable documentation exists and is
being applied. Information designated as proprietary
by MATRA MHS is made available to the customer or
its representative only with the written permission of
MATRA MHS.
As shown by table 1 each integrated circuit is constructed by manufacturing processes which are under
the surveillance of MATRA MHS Quality Control
Department. The processes are monitored and controlled by use of statistical techniques and computerization
in
accordance
with
published
specifications and procedures. MATRA MHS prepares
and maintains suitable documentation (such as quality
control manuals, inspection instructions, control
charts, etc.) covering all phases of incoming part and
material inspection and in-process specification. The
customer may verify, with the permission of and in the
FLOW
PROCESS
MATERIALS
Process control is recognized as being vital to the concept of "built-in" quality. The process control program
includes a scanning electron microscope (SEM)
monitor program for evaluating the metal integrity over
oxide step and oxide step contour. The SEM analysis
is defined in a Quality & Reliability Assurance document.
INSPECTION
METHOD
FREQUENCY
Scribing
Visual
2 Nd Optical
Visual
2010 Cond B
100%
Scribing
Visual
2010 Cond B
100 %
QC Inspection
Visual
2010 Cond B
Every lot
2010 Cond B
Monitor
Lead Frame, base
(incoming inspection)
Die Bonding
QC Inspection
Appearance
Every lot
Wire
(incoming inspection)
Wire Bonding
Bond sirength
Praseal inspection
Visual
100 %
QC Inspection
Visual
Every lot
2011
Every lot
Prestabilization sealing
Temperature Cycling
1010
Condition C
100 %
Centrifuge
2001
Condition E
100 %
Lead cut
Plating
Plating inspection
Marking
Appearance
'thickness
Permanency
Every lot
2015
Every lot
Fine leak
1014
Condition A or B
100 %
Gross leak
1014
Condition C
100 %
QA monitoring
All QC inspection
Table 2: QC Ceramic flow charts of assembly process (1).
9·5
B • Receiving inspection
2.1 • CONTROL OF PROCUREMENT SOUR·
CES
Purchased supplies are subjected to inspection after
receipt as necessary to ensure conformance to contract requirements. In selecting sampling plans, consideration is given to the controls exercised by the
procurement source and evidence of substained
quality conformance.
MATRA MHS is responsible for assuring that all supplies and services conform to this specification, the
detail specification and MHS's procurement requirements.
A· MATRA MHS/supplier convention
C· MATRA MHS initiates corrective action with the
procurement source depending upon the nature and
frequency of receipt of nonconforming supplies.
Prior to use in production, MATRA MHS verifies the
capability of the supplier QA, manufacturing engineering and services to deliver material conform to
specification and kept under control. Formal agreement is established between the two partners.
MILITARY TEMP. RANGE
AUTOMOTIVE
COMMERCIAL TEMP. RANGE INDUSTRIAL TEMP. RANGE
- 55°C to + 125°C
O°C to 70°C
- 40°C to + 85°C
- 40°C to 110°C
Family
Family STD STD + B.1.
Family
STD STD + B.1. Family
STD STD + B.1.
Memory
Memory
-9
Memory -2
-8
-5
-9+
-5+
suffix
suffix
Micro's prefix
Micro's
Micro's
M---/B
Micro's
L
Q
I
prefix
A
prefix
Gate
Gate
Gate
array
-5
array
-9
-2
-8
-5+
-9+
array
suffix
suffix
Table 1 : PROCESS FLOWS INFORMATION
QA Wafer visual inspection
Electrical test and probe 25°C
Assembly (see table 2 and 3)
Pre Burn-in test
Burn-in
Post Burn-in test
INDUSTRIAL
MILITARY
COMMERCIAL
AUTOMOTIVE
STD STD + B.I.
STD
STD + B.I. STD STD + B.I.
Monitor Manito(
Monitor
Monitor
Monitor Monitor Monitor
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100% (1)
100% (1)
100% (1)
100% (1)
100%
100%
100%
100%
P.D.A
(percentage defective allowable)
Final electrical test
(per MHS specification)
Marking (lot number + branding week
code, per MATRA MHS specification)
Lead Straigthen
MATRA MHSQuality final acceptance
electrical
mechanical (visual)
Notes:
5% (2)
5% (2)
5% (2)
5% (2)
100% high
temp.
Low temp.
optional
idem
idem
idem
idem
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
(3)
(3)
(3)
(3)
(3)
100%
(3)
100%
(3)
100%
100%
100%
100%
100%
idem
idem
100%
100%
100%
1) Burn-in is performed as 24 h, 12S'C (or equivalent) minimum.
2) ff a lot fails the S % PDA, but is < 10 %, the lot may be submitted to burn-in on time only to the same time and temperature condition.
3) MHS quality final acceptance is performed following quality dispositions to assure 200 ppm. Average Outgoing Quality.
9-6
3 - RELIABILITY RESULTS
The objective failure rate at 55"C, 60 % UCL is in any
case lower than 100 fits. Details about data base are
available upon request in Reliability Reports, written
for each product or product family.
4 - MILITARY HI-REL PRODUCTS
A broad choice of quality grades is available.
SC : space program according to level C or SCC9000
(LAT 1, 2, 3).
CB : CECC program according to level B of CECC
90000.
DB: dice military program with qualification flow.
MB : military program according to class B of MIL-STD
SS3C.
(refer to MATRA MHS high reliability Data-book)
SB : space program according to level B of SCC 9000
(LAT 1,2,3).
5 - DICE/WAFER FORM
MATRA
MHS
Memory,
Gate
Arrays
and
Microcontrolier products are available in chip form and
wafer form to the hybrid microcircuit designer. Table 1
gives the different flows used for Military and Standard
levels with the production operations and QC gates.
So as to respond to specific requirements of the hybrid
industry, MATRA MHS has several additionnal options
to table 1 as electrical qualification lots for military dice,
available upon request at extra cost.
PROCESS FLOWS INFORMATION (Table 1)
STANDARD FLOW
FAMILY
DICE FORM WAFER FORM
HMO-65162-6 HMW-65162-6
MEMORY
MICRO'S
XW-80C31
XX-80C31
GATE ARRAY MAD-250A69-6 MAW-250A69-6
DICE FORM
MILITARY FLOW
FAMILY
DICE FORM WAFER FORM
MEMORY
HMO-65162-2 HMW-65162-2
MICRO'S
-80C31
XW-80C31
GATE ARRAY MAO-250A69-2 MAW-250A69-2
WAFER FORM
DICE FORM
"'-
"'-
IPQC
IPQC
-
_100..,
_100..,
_100"
Scribing
IPQC
WAFER FORM
IPQC
--
QCGIITE
2OIOIB
10 DlC!;jWAFER
6 WAFERS
Scribing
DICE INI!PEC11ON
_:lO1O
QCGIIlE
10 DlCfIW'AFER
6 WAFERS
~
OOnd.B
IJ1CE IN8PEClION
_:!010
Ccn1B
QCGIIIE
_2010
OOnd.B
LTPD 10 A-il
QCGAl£
--
_:!01OB
-
LTPD 10 A=O
""'**111
9-7
~
D
MHS
LOCATIONS
'-----_____ ~'1i IllS
10-1
1m
------iiMtS-----M.H.S.
LOCATIONS
MHS ELECTRONIC CENTER
La ChantrerielRoute de Gachet
CP 3008
44087 Nantes Cedex 03/France
Tel. : (33) 40303030 - Twx : 711930 - Fax: (33) 40300216
SALES OFFICES
FRANCE
"Les Quadrants"
3, avenue du Centre
BP309
78054 St-Quentin-Yvelines Cedex
Tel.: (33) 1-30607000
Twx :697317
Fax: (33) 1-30640693
SCANDINAVIA
USA
MD Semiconductor AB
Dragon Plan 1 , Rissne
Box 2042 - 17202 Sundbyberg
Sweden
Tel. : (46) 87.33.00.90
Fax: (46) 87.33.05.58
MATRA DESIGN SEMICONDUCTOR
2895 Northwestern Parkway
Santa Clara, CA 95051
Tel. : (1) 4081986-9000
Twx :299656
Fax: (1) 408/748-1038
UNITED KINGDOM
GERMANY
Erfu rterstrasse 29
D-8057 Eching
Tel. : (49) 89-31900550
Twx: 524126
Fax: (49) 89-31900555
ITALY
Via Vigliani 13
1-20148 Milano
Tel. : (39) 2-4984586
(39) 2-462602
Twx :334595
Fax: (39) 2-4818660
Easthampstead Road
Bracknell
Berkshire RG12 1LX
Tel. : (0344) 485757
Inti: (44) 344-485757
Twx: 849392
Fax: (44) 344-427371
FAR EAST
MATRA DESIGN SEMICONDUCTOR
ASIA
Room 1601, 16/FL, Shui on Centre
6-8 Harbour Road
Wanchai
Hong Kong
Tel. : (852)-5-8650861
Fax: (852)-5-8651273
Tlx: 85351 HX
EUROPEAN DISTRIBUTORS
AUSTRIA
TRANSISTOR
VERTRIEBSGESELLSCHAFT
mbHCO-KG
Auhofstrasse 41 A
A-1130Wien
Tel. : (43) 222-829401
Twx: 133738
Fax: (43) 222-826440
BELGIUM
MICROTRON NV S.A.
Generaal Dewittelaan 7
2800 Mechelen
Tel.: (32) 15-212223
Twx :22606
Fax: (32) 15-210069
DENMARK
FRANCE
DITZ SCHWEITZER A.S.
Vallensbakvej 41
Post Box 5
DK-2600 Glostrup
Tel. : (45) 2-453044
Twx :33257
Fax: (45) 2-459206
FINLAND
YLEISELEKTRONIKKA OY
P.O. Box 73
SF-02201 Espoo
Tel. : (358) 0-4521255
Twx: 123212
Fax: (358) 0-428932
1()..3
A2M
6, avo Charles-de-Gaulle
78150 Le Chesnay
Tel.: (33) 1-39549113
Twx :698376
Fax: (33) 1-39543061
ALMEX
48, rue de l'Aubepine
92160 Antony
Tel. : (33) 1-46662112
Twx :250067
Fax: (33) 1-46666028
ELTEK (Wafer dice only)
BP 1077
Z.A. La Tuilerie
78204 Mantes-Ia-Jotie Cedex
Tel. : (33) 1-34771616
Twx :699717
MATRA MHS
_____________________________ LOCATIONS _____________________________
EUROPEAN DISTRIBUTORS (continued)
FRANCE (continued)
UNITED KINGDOM AND IRELAND
ITALY
FEUTRIER
5, rue Jean-Zay
42271 St-Priest-en-Jarez
Tel. : (33) 77934040
Twx: 300021
Fax: (33) 77932631
CAMEL ELETTRONICA
Via Tiziano 18
1-20145 Milano
Tel. : (39) 2-4981481
Twx: 325237
Fax: (39) 2-4818637
RTF
81, rue Pierre Semard
92320 Chatillon
Tel. : (33) 1-49652700
Twx: 632247
Fax: (33) 1-49652738
KONTRON SPA
Via Fantoli 16/15
1-20138 Milano
Tel. : (39) 2-50721
Twx: 312288
Fax: (39) 2-5060918
ERICSSON COMPOSANTS
1 , Parc Club Ariane
Rue Helene Boucher
78284 Guyancourt
Tel. : (33) 1-30640900
Twx: 697347
Fax: (33) 1-30641146
LASI ELETTRONICA SPA
Viale Fulvio Testi 126
1-20092 Cinisello Balsamo
Tel. : (39) 2-2440012
Twx: 352040
Fax: (39) 2-2487717
NETHERLANDS
GERMANY
ALFRED NEYE ENATECHNIK GMBH
Schillerstrasse 14
D-2085 Quickborn
Tel. : (49) 4106-6121
Twx: 213590
Fax: (49) 4106-612268
JERMYN GMBH
1m DachsstOck 9
D-6250 Limburg
Tel. : (49) 6431-5080
Twx: 4152570
Fax: (49) 6431-508289
RUTRONIK-RSC-Halbleiter und
Elektronische Bauelemente GMBH
Industriestrasse 2
D-7536 Ispringen
Tel. : (49) 7231-8010
Twx: 783650
Fax: (49) 7231-82282
SPOERLE ELECTRONICS GMBH
Max-Plank-Strasse 1-3
Postfach 102140
D-6072 Dreleich 1
Tel. : (49) 6103-3040
Twx: 417972
Fax: (49) 6103-304201
NIJKERK
Drentestraat 7
1083 HK AMSTERDAM
Postbus 7920
1008 AC AMSTERDAM
Tel. : (31) 20-5495-969
Twx: 11625 NESCO
Fax: (31) 20-423-948
NORWAY
TAHONICAIS
P.O. Box 140/KALBAKKEN
N-0902 OSLO 9
Tel. : (47) 2-161610
Twx: 77397
Fax: (47) 2-257317
SPAIN
SELCOSA
Paseo de la Habana 190
28036 Madrid
Tel. : (34) 1-4054213
Twx: 45458
Fax: (34) 1-2592284
SWITZERLAND
ELECTRONITEL
Chemin du Grand Clos 1
B.P.93
CH-1752 VILLARS-SUR-GLANE
Tel. :(37)41.00.60
Fax: (37) 41.00.70
MACRO MARKETING LTO
Burnham Lane - SLOUGH
Berkshire SL1 6LN.
Tel. : (06286) 4422
IntI. : (44) 62864422
Twx:847945
Fax: (06286) 66873
MTL MICROTECHNOLOGY LIMITED
(Die Distributor)
Test House - Mill Lane - ALTON
Hampshire. GU34 2QG.
Tel. : (0420) 88022
IntI. : 44 420 88022
Tlx: 858456
Fax: (0420) 87259
POLAR ELECTRONICS LIMITED
Cherry court Way
Leighton Buzzard
Bedfordshire. LU7 8YY.
Tel. : (0525) 377093
IntI. : 44 525 377093
Tlx: 825238
Fax: (0525) 378367
R R ELECTRONICS LIMITED
SI. Martin's Way Industrial Estate
Cambridge Road - BEDFORD
Bedfordshire. MK42 OLF
Tel. : (0234) 47188
IntI. : 4423447188
Tlx: 826251
Fax: (0234) 210674
THAME COMPONENTS LIMITED
Thame Park Road - THAME
Oxfordshire OX9 3XD.
Tel. : (084426) 1188
IntI. : 44 84426 1188
Twx :837917
Fax: (084426) 1681
SWEDEN
TH:S ELEKTRONIK
P.O. Box 3027
16303 Spanga - Sweden
Tel. : (46) 8.362970
Fax: (46) 8.761.30.65
FAR EAST REPRESENTATIVES AND DISTRIBUTORS
INDIA
SPARTEX SYSTEMS & SERVICES
Pvt Ltd.,
N" 68, Michael Palyarn,
Near Deccan Studio,
C.V. RAMAN NAGAR POST,
BANGALORE - 560 093,
INDIA
Tel. : 564211, 568772
Tlx : 0845 - 2190 MLHR IN
JAPAN
KOREA
CHRONIX INCORPORATED
Maruyama Bid 4F
7-9-7, Nishishinjuku
Shinjuku-ku, Tokyo, 160
Tel. : (81) 3-371-5711
Twx: 26244
Fax: (81) 3-371-5738
10·4
BUK SUNG INDUSTRIAL CO LTO
3/FL, Samyuna Bida, 159-22
Docksan-4 Dong, Guro-Ku
Seoul
Tel. : (82) 2.854.1362
Twx: BUSUCOK26925
Fax: (82) 2.8621273
------------__________________ LOCATIONS ______________________________
FAR EAST REPRESENTATIVES AND DISTRIBUTORS (continued)
SINGAPORE
WESTECH ELECTRONICS PTE
LTD.
3, Lorong Bakar Balu # 05-02
Brightway Building
Singapore 1334
Tel. : (65)-7436355
Twx: 55070
Fax: (65)-7461396
SCAN TECHNOLOGY(s) PTE LTO
So Kallana Bahru # 04-01/03
Kallana Basin Ind
Singapore 1233
Tel. : (65)-2942112
Twx: RS74983 STECH
Fax: (65) 2961685
TAIWAN
HONG KONG
UNION TECHNOLOGY
CORPORATION
3/FL, 585 Ming Sheng East Road
Taipei, Taiwan
Tel. : (886) 2-505.8616
Twx: 202 61 MECTAL
Fax: (886) 2-5056609
WORLD PEACE INDUSTRIAL
CO LTD
5/1L, 309 Sung Chiang Road
Taipei, Taiwan
Tel. : (886) 2-5056621/5056345
Fax: (886) 2-5058760
PROTECH COMPONENTS LTD
Flat 3, 10/F, Wing Shing Ind. Bldg
26 Ng Fong Street
San Po Kong, Kowloon
Tel. : (852) 3-3522181
Fax: (852) 3-3523759
WILLAS COMPANY LTD
8/F, Wing Tai Centre
12 Hing Yip Street
Kwun Tong, Kowloon
Tel. : (852) 3-414281, 3-890343
Twx: 39315 WILAS HX
Fax: (852) 3-431229
AUSTRALIA
CONSULAUST INTERNATIONAL
PTY, LTD.
1, Norfolk Road - Surrey Hills,
PO Box 357, Camberwell
Victoria, 3124
Tel. : (61) 3-8362566
Twx: CONAUS AA37455
Fax:61-3-8301764
US REPRESENTATIVES
ANCHOR ENGR.
11 WALKUP DR,
WESTBORO
MASSACHUSSEnS 01581-1018
Tel. : 508-898-2724
Fax: 508-870-0573
CAHILL, SCHMITZ & HOWE
4905 Lakeside Drive
N.E. SUITE 100
CEDAR RAPIDS
IOWA 52402
Tel. : 319-377-8219
Fax: 319-377-0958
ARBOTEK
10404 W. JOPPA RD.
TOWSON
MARYLAND 21204
Tel. : 301-825-0775
Fax: 301-337-2781
2201 ANGUS RD., SUITE 14
CHARLOnESVILLE
VIRGINIA 22901
Tel. : 804-971-5736
C.C. ELECTRO
5335 N. TACOMA AVE., SUITE #1
INDIANAPOLIS
INDIANA 48220
Tel. : 317-255-1508
Fax: 317-266-6875
5635 FORDHAM CIRCLE #203
CANTON
MICHIGAN 48187
Tel. : 313-981-9298
9735 RAVENNA RD.
TWINSBURG
OHIO 44087
Tel. : 216-425-8338
Fax: 216-425-2147
E.M.A.
6695 PEACHTREE IND. BLVD.,
SUITE 101
ATLANTA
GEORGIA 30360
Tel. :404-448-1215
Fax: 404-446-9363
210 W. STONE AVE.
GREENVILLE
S. CAROLINA 29609
Tel. : 803-233-4637
Fax: 803-242-3089
7501 South Memorial Parkway, #202
HUNTSVILLE
ALABAMA 35802
Tel. : 205-880-8050
Fax: 205-880-8054
8512 SIX FORKS RD., SUITE 601 A
RALEIGH
N. CAROLINA 27615
Tel. : 919-847-8800
Fax: 919-848-1787
ELECTEC
3211 scon BLVD., SU ITE 101
SANTA CLARA
CALIFORNIA 95054
Tel. : 408-496-0706
Fax: 408-727-9817
8465 ROYAL OAKS DRIVE
GRANITE BAY
CALIFORNIA 95661
Tel. :916-797-0414
Fax: 916-456-6001
GEORGE RUSSEL & ASSOC.
8030 CEDAR AVE. SOUTH,
SUITE 114
MINNEAPOLIS
MINNESOTA 55420
Tel. :612-854-1168
LANDA & ASSOC.
1518 COTNER AVE.
LOS ANGELES
CALIFORNIA 90025
Tel. : 213-879-0770
Fax. : 213-478-0190
1616 E. 4TH ST.
SANTA ANA
CALIFORNIA 92701
Tel. : 714-543-7805
Tax: 714-543-1380
662 NARDO AVE.
SOLANA BEACH
CALIFORNIA 92075
10-5
;'~MIS
_____________________________ LOCATIONS _____________________________
US REPRESENTATIVES (continued)
M.E.C.
SW MARKETING ASSOC.
700 W. HILLSBORO BLVD., BLDG. 4,
10940 ALDER CIRCLE
#204
DALLAS
TEXAS 75238
DEERFIELD BEACH
FLORIDA 33441
Tel. :214-341-8631
Tel. : 305-426-8944
Fax: 214-340-5870
Fax: 305-426-8799
830 N. ATLANTIC BLVD., SUITE B401
COCOA BEACH
FLORIDA 32931
Tel. : 407-799-0520
Fax: 407-799-0923
511 CARRIAGE ROAD
INDIAN HARBOUR BEACH
FLORIDA 32937
Tel. : 407-332-7158
Fax: 407-830-5436
13006 KELLIES FARMLANE
AUSTIN
TEXAS 78727
Tel. :512-255-8010
400 FM 1960 WEST, SUITE 100-15
HOUSTON
TEXAS 77090
Tel. :713-537-8166
Fax: 713-537-9738
6713 E. 54TH ST.
TULSA
OKLAHOMA 74145
Tel. : 918-663-7536
100145THAVE., NE
ST. PETERSBURG
FLORIDA 33703
Tel. : 813-522-3433
Fax: 813-522-3933
SYNERGISTIC SALES
501 MITCHELL ROAD
GLENDALE HEIGHTS
ILLINOIS 60139
Tel. : 312-858-8686
Fax: 312-790-9799
N.E. COMPONENTS
155 GRANDVIEW LANE
MAHWAH
NEW JERSEY 07430
Tel. : 201-825-0233
Fax: 201-934-1310
8700 S.w. 105TH AVE.
BEAVERTON
OREGON 97005
Tel. : 503-644-5900
fax: 503-644-5919
TRUE NORTH TECH. LTD.
100 WESTMORE DR., SUITE 12E
REXDALE, ONTARIO
CANADA MOV 5C3
Tel. :416-744-2233
Fax: 416-744-3376
1883 LONGMAN CRESCENT
GLOUCESTER, ONTARIO
CANADA K1 C 5G7
Tel. : 613 824-8957
Fax: 614-745-0315
WEST. INC.
1740 PLATTE SR. #200
DENVER
COLORADO 80202
Tel. :303-477-1134
TECH SALES ASSOC.
EXEC. MEWS, RJ-52, 2300
COMPUTER AVE.
WILLOW GROVE
PENNSYLVANIA 19090
Tel. :215-784-0170
Fax: 215-784-9201
22 LAWRENCE AVE,
SMITHTOWN
NEW YORK 11787
Tel. : 516-724-3485
PHOENIX SALES
257 MAIN ST.
TORRINGTON
CONNECTICUT 06790
Tel. : 203-496-7709
Fax: 203-496-0912
460 EAST 100 SOUTH
CENTERVILLE
UTAH 84014-5087
Tel. : 801-292-8787
Fax: 801-298-0788
THORSON CO. n.w.
12340 N.E. 8TH ST., SUITE 201
BELLEVUE
WASHINGTON 98005
Tel. : 206-455-9180
Fax: 206-455-9185
US DISTRIBUTORS
ADDED VALUE ELECTRONIC DISTRIBUTION, INC.
1512 PARKWAY LOOP, UNIT G
TUSTIN, CA 92680
Tel.: (714) 259-8258
Fax: (714) 259-0828
7741 E. GRAY ROAD, SUITE 9
SCOTTSDALE, AZ 85260
Tel.: (602) 951-9788
Fax: (602) 951-4182
31194 LA BAYA DRIVE, SUITE 100
WESTLAKE VILLAGE, CA 91362
Tel: (805) 643-2101
(818) 889-2861
Fax: (818) 889-2472
A.V.E.D. - ROCKY MOUNTAIN, INC.
1836 PARKWAY BLVD.
WEST VALLEY CITY, UT 84119
Tel.: (801) 975-9500
Fax: (801) 977-0245
A.V.E.D. - ROCKY MOUNTAIN, INC.
4090 YOUNGFIELD ST.
WHEAT RIDGE, CO 80033
Tel.: (303) 422-1701
Fax: (303) 422-2529
A.V.E.D. - SOUTHWEST INC.
4470 SPRING VALLEY ROAD
DALLAS, TX 75244
Tel.: (214) 404-1144
Fax: (214) 233-2614
ALL AMERICAN SEMICONDUCTOR CORP.
2360 QUME DRIVE, SUITE C
SAN JOSE, CA 95131
Tel.: (408) 943-1200
Fax: (408) 943-1393
16251 N.w. 54TH. AVENUE
MIAMI, FL33014
Tel.: (305) 621-8282
(800) 228-7459
Fax: (305) 620-7831
10-6
369 VAN NESS WAY, SUITE 701
TORRANCE, CA 90501
Tel.: (213) 320-0240
(800) 669-8300
Fax: (213) 320-7207
_______________________________ LOCATIONS _______________________________
US DISTRIBUTORS (continued)
ALL AMERICAN SEMICONDUCTOR CORP. (continued)
5009 HIATUS ROAD
SUNRISE, FL
107 AUDUBON ROAD, SUITE 104
WAFEFIELD, MA 01880
Tel.: (617) 246-2300
1819 FIRMAN DRIVE, #127
RICHARDSON, TX 75081
Tel.: (214) 231-5300
Fax: (214) 437-0353
14636 ROTHGEB DRIVE
ROCHVILLE, MD 20850
Tel.: (301) 251-1205
Fax: (301) 251-8574
11409 VALLEY VIEW ROAD
EDEN PRAIRIE, MN 55344
Tel.: (800) 342-7364
Fax: (612) 944-9803
711-2 KOEHLER AVENUE
RONKONKOMA, NY 11779
Tel.: (516) 981·3935
(800) 874·2830
Fax: (516) 931·3947
BELL INDUSTRIES
1031 PUTNAM DRIVE, SUITE A
HUNTSVILLE, AL 35816
Tel.: (205) 837-1074
Fax: (205) 830-5598
5230 WEST 79TH ST.
INDIANAPOLIS, IN 46268
Tel.: (317) 875-8200
Fax: (317) 875·8219
6024 SOUTHWEST JEAN ROAD
LAKE OSWEGO, OR 97034
Tel.: (503) 241-4115
Fax: (503) 635-6500
306 E. ALONDRA BLVD.
GARDENA, CA 90247
Tel.: (213) 515-1800
Fax: (213)777-3111 X306
1161 NO. FAIROAKS AVE.
SUNNYVALE, CA 94089
Tel.: (408) 734-8570
Fax: (408) 734-8875
6912 SOUTH 185 WEST, SUITE B
MIDVALE, UT 84044
Tel.: (801) 255-9611
Fax: (801) 255-2477
11812 SAN VINCENTE BLVD., #300
LOS ANGELES, CA 90049
Tel.: (213) 826-6778
Fax: (213) 258-6932
12421 W. 49TH AVENUE
WHEATH RIDGE, CO 80033
Tel.: (303) 424-1985
fax: (303) 424-0932
W. 227N, 913 WESTMOUND DRIVE
WAUKESHA, WI 53186
Tel.: (414) 547-8879
Fax: (414) 547-6547
1705 W. 4TH ST.
TEMPE, AZ 85281
Tel.: (602) 966-7800
Fax: (602) 967-6584
10810 72ND ST. NORTH, SUITE 201
LARGO, FL 33541
Tel.: (813) 541-4434
Fax: (813) 546-6418
11095 KNOTT AVE., SUITE E
CYPRESS, CA 90630
Tel.: (714) 891-4570
515 BUSSE AVENUE, UNIT D-I
ELK GROVE VILLAGE, IL 60007
Tel.: (312) 640-1910
Fax: (312) 640-0474
6979 WASHINGTON AVE. SO.,
SUITE 200
EDINA, MN 55435
Tel.: (612) 941-1493
Fax: (612) 941-2964
4311 ANTHONYCOURT,#100
ROCKLIN, CA 96677
Tel.: (916) 652-0414
Fax: (916) 652-0403
7450 RONSON ROAD
SAN DIEGO, CA 92111
Tel.: (619) 268-1277
Fax: (619) 268-3733
638 SO, MILITARY TRAIL
DEERFIELD BEACH, FL 33442
Tel.: (305) 421-1997
Fax: (305) 421-5705
3020 A BUSINESS PARK DRIVE
NORCROSS, GA 30071
Tel.: (404) 662-0923
Fax: (404) 449-6901
130 KILLARNEY
URBANA,IL61801
Tel.: (217) 328-1077
Fax: (217) 328-1148
3433 E. WASHINGTON BLVD.
FT. WAYNE, IN 46803
Tel.: (21C;) 423-3422
Fax: (219) 424-2433
1221 PARK PLACE, N.E.
CEDAR RAPIDS, IA 52402
Tel.: (319) 395-0730
Fax: (319) 395-9761
100 BURTT ROAD? #106
ANDOVER, MA01810
Tel.: (508) 474-8880
Fax: (508) 474-8902
814 PHOENIX DRIVE
ANN ARBOR, MI 48404
Tel.: (313) 971-9093
Fax: (313) 971-9178
444 WINDSOR PARK DRIVE
DAYTON, OH 45459
Tel.: (513) 435-8660
Fax: (513) 435-6765
10-7
11728 LINN, N.E.
ALBUQUERQUE, NM 87123
Tel.: (505) 292-2700
Fax: (505) 275-2819
118 WESTPARK ROAD
DAYTON, OH 45459
Tel.: (513) 434-8231
Fax: (513) 434-8103
1701 GREENVILLE, #306
RICHARDSON, TX 75081
Tel.: (214) 690-0466
Fax: (214) 690-0822
8553 154TH AVE. N.E.
REDMOND, WA 98052
Tel.: (206) 885-9963
Fax: (206) 867-5159
30101 AGOURA COURT, SUITE 118
AGOURA HILLS, CA 91301
Tel.: (818) 706-2608
Fax: (818) 891-7695
--------------------------____ LOCATIONS ______________________________
US DISTRIBUTORS (continued)
CAM RPC ELECTRONICS
2975 BRIGHTON HENRIETIA
TOWN LINE RD.
ROCHESTER, NY 14623
Tel.: (716) 427-9999
Fax: (716) 427-7559
749 MINER ROAD
CLEVELAND, OH 44143
Tel.: (216)461-4700
Fax: (216) 461-4329
620 ALPHA DRIVE
PITISBURGH, PA 15238
Tel.: (412) 963-6202
Fax: (412) 963-6210
7973-B WASHINGTON WOOD DRIVE
DAYTON, OH 45459
Tel.: (513) 433-5551
Fax: (513) 461-4329
FALCON ELECTRONICS INC.
5 HIGGINS DRIVE
MILFORD, CT 06460
Tel.: (203) 878-5272
Fax: (203) 877-2010
CATON RESEARCH CENTER,
SUITE 0
1520 CATON CENTER DRIVE
BALTIMORE, MD 21227
Tel.: (301) 247-5800
Fax: (301) 247-5893
1383 VETERAN'S MEMORIAL HWY.
HAUPPAGE, NY 11788
Tel.: (516) 724)-0980
(800) 528-0016
Fax: (516) 724-0993
HAMMOND ELECTRONICS, INC.
4411-B EVANGEL CIRCLE NW.
HUNTSVILLE, AL 35816
Tel.: (205) 830-4764
Fax: (205) 830-4287
6600 NW. 21ST AVE., 8AY D
FT. LAUDERDALE, FL 33309
Tel.: (305) 973-7103
(FT LAUDERDALE)
Fax: (305) 973-7601
2923 PACIFIC AVE.
GREENBORO, NC 27420
Tel.: (919) 275-6391
1230 WEST CENTRAL BLVD.
ORLANDO, FL 32802
Tel.: (407) 841-1 010 (ORLANDO)
Fax: (407) 648-8584
5680 OAKBROOK PKWY., SU ITE 160
NORCROSS, GA 30093
Tel.: (404) 449-1996
(800) 241-5437
Fax: (404) 424-9834
NU HORIZONS ELECTRONICS CORP.
151 ANDOVER ST.
DANVERS, MA 01923
Tel.: (617) 777-8800
Fax: (617) 777-8806
39 U.S. ROUTE 46
PINE BROCK, NJ 07058
Tel.: (201) 882-8300
Fax: (201) 882-8398
6000 NEW HORIZONS BLVD.
AMITYVILLE, NY 11701
Tel.: (516) 226-6000
Fax: (516) 226-6262
2002C GREENTREE EXECUTIVE
CAMPUS
MARLTON, NJ 08053
Tel.: (609) 596-1833
Fax: (609) 596-0612
100 BLUFF DRIVE
EACH ROCHESTER, NY 1445
Tel.: (716) 248-5980
(203) 265-0162
Fax: (716) 248-9132
SEMAD/DGW ELECTRONICS CORP.
85 Spy COURT
MARKHAM, ONTARIO
CANADA L3R 424
Tel.: (416) 475-3922
Fax: (416) 475-4158
8563 GOVERNMENT ST.
BURNABY, B.C.
CANADA V3N 4S9
Tel.: (604420-9889
Fax: (604) 420-0124
1827 WOODWARD DRIVE,
SUITE 303
OTIAWA, ONTARIO
CANADA K2C OR3
Tel.: (613) 727-8325
Fax: (613) 727-9489
243 PLACE FRONTENAC
POINTE CLAIRE, PO
CANADA H9R 4Z7
Tel.: (514) 694-0860
Fax: (514) 694-0965
MATRA MHS products are sold by description only. MHS reserves the right to make changes in circuit design, specifications
and other information at any time without prior notice. Accordingly, the reader is cautioned to verify that data sheets and other
information in this publication are current before placing orders.
6120 THIRD ST., SE UNIT #G
CALGARY, ALBERTA
CANADA T2H 1K4
Tel.: (403) 252-5664
Fax: (403) 255-0966
Information contained in application notes is intended solely for
general guidance; use of the information for user's specific application is at user's risk. Reference to products of other
manufacturers are solely for convenience of comparison and do
not imply total equivalency of design, performance, or otherwise.
Copyright © MHS 1989 - (All rights reserved) - Printed in France
JOUVE - PARIS
Typesetting and lay-out using Desktop-Publishing means - AZIMUT - France - 21.75.01.75
10-8
MATRA MHS
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