1990_Memory_Databook 1990 Memory Databook
User Manual: 1990_Memory_Databook
Open the PDF directly: View PDF 
.
Page Count: 610
| Download | |
| Open PDF In Browser | View PDF |
~
co
co
o
~ National
~
Semiconductor
400067
MEMORY
DATABOOK
1990 Edition
CMOS EPROMs
EEPROMs
PROMs
ECl I/O Static RAMs
TTL 1/0 Static RAMs
Appendices/Physical Dimensions
iii
TRADEMARKS
Following is the most current list of National Semiconductor Corporation's trademarks and registered trademarks.
Abuseable™
AnadigTM
ANS-R-TRANTM
APPSTM
ASPECTTM
Auto-Chern Deflasher™
BCPTM
BI-FETTM
BI-FET IITM
BI-LiNETM
BIPLANTM
BLCTM
BLXTM
Brite-Lite™
BTLTM
CheckTrack™
CIMTM
CIMBUSTM
CLASICTM
Cloc~ChekTM
COMBOTM
COMBO ITM
COMBO IITM
COPSTM microcontrollers
DatacheckerDENSPAKTM
DIBTM
Digitalker@
DISCERNTM
DISTILLTM
DNR®
DPVMTM
ELSTARTM
Embedded System
Processor™
E-Z-LlNKTM
FACTTM
FAIRCADTM
FairtechTM
FAST@
5-Star ServiceTM
GENIXTM
GNXTM
HAMRTM
HandiScan™
HEX3000TM
HPCTM
13L@
ICMTM
INFOCHEXTM
IntegrallSETM
IntelisplayTM
ISETM
ISE/06TM
ISEI08™
ISE/16TM
ISE32TM
ISOPLANARTM
ISOPLANAR-ZTM
KeyScan™
LMCMOSTM
M2CMOSTM
Macrobus™
Macrocomponent™
MAXI-ROMMea~ChekTM
MenuMaster™
Microbus™ data bus
MICRO-DACTM
,...talker™
Microtalker™
MICROWIRETM
MICROWIRE/PLUSTM
MOLETM
MSTTM
Naked-8TM
NationalNational SemiconductorNational Semiconductor
Corp.@
NAX800™
Nitride Plus™
Nitride Plus Oxide™
NMLTM
NOBUSTM
NScaOOTM
NSCISETM
NSX-16TM
...
NS-XC-16TM
NTERCOMTM
NURAMTM
OXISSTM
p2CMOSTM
PC Master™
Perfect WatchTM
PharmvChekTM
PLANTM
PLANARTM
Plus-2TM
Polycraft™
POSilinkTM
POSitalker™
Power + Control™
POWERplanar™
QUAD3000™
QUIKLOOKTM
RATTM
RTX16TM
SABRTM
Scrip~ChekTM
SCXTM
SERIES/800TM
Series 900TM
Series 3000TM
Series 32000Shelf,.....Chek™
SofChekTM
SONICTM
SPIRETM
Staggered RefreshTM
STARTM
StarlinkTM
STARPLEXTM
Super-BlockTM
SuperChipTM
SuperScriptTM
SYS32TM
TapePakTDSTM
TeleGate™
The National Anthem@
Time,.....ChekTM
TINATM
TLCTM
Trapezoidal™
TRI-CODETM
TRI-POLYTM
TRI-SAFETM
TRI-STATETURBOTRANSCEIVERTM
VIPTM
VR32TM
WATCHDOGTM
XMOSTM
XPUTM
Z STARTM
883B/RETSTM
883S/RETSTM
ABEL-is a registered trademark of Data I/O Corporation.
CUPL® is a registered trademark of Assisted Technology, Inc.
PAL- is a registered trademark of and used under license from Monolithic Memories, Inc.
Z80® is a registered trademark of Zilog Corporation.
TouchTone™ is a trademark of Western Electric Co., Inc.
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions
for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
NationalSemlconductorCorporatlon 2900 Semiconductor Drive, P.O. Box 58090, Santa Clara, California 95052-8090 (408) 721-5000
TWX (910) 339-9240
National does not assume any responsibility for use of any clrcuHry described, no circuit patent licenses are Implied, and National reserves the right, at any time
without notice, to change said clrcuHry or specifications.
iv
3:
Memory Databook
Introduction
CD
3
o
...
'<
C
-
II)
I I)
C"'
National Semiconductor's Memory Databook is a comprehensive collection of information on advanced memory products intended to meet the needs of virtually every electronic
system being designed today. National Semiconductor is
committed to designing and supplying high performance
memory products ranging from state-of-the-art static RAMs
to programmable non-volatile EPROMs and EEPROMs.
National Semiconductor has an array of advanced technology processes to apply to memory design and development.
These range from our unparalleled SiCMOS process used for
the industry's most advanced line of high density ECl 1/0
SRAMs, to our small geometry, silicon gate, oxide isolated
CMOS technology which is now producing unsurpassed, high
performance EPROM and EEPROM non-volatile memory devices.
National Semiconductor is committed to excellence in design, manufacturing, reliability, and service to our customers
through the continuing development of new products and
technologies. As new information and devices become available, individual new data sheets will be issued. For the most
current information, please contact your local National Semiconductor sales office or Distributor.
v
o
o=-:S-
a
c..
c
-
n
o·
::l
o
i=;
r-----------------------------------------------------------------------------~
~National
~ Semiconductor
c
i
Product Status Definitions
1:)
:::lI
"e
Definition of Terms
D.
Data Sheet Identification
<
'.".i.dunc.1i'Ifo11llatioo
y
;,-
:~Irfttna"
Product Status
This data sheet contains the design specifications for product
development. Specifications may change in any manner without notice.
First
Production
This data sheet contains preliminary data, and supplementary data will
be published at a later date. National Semiconductor Corporation
reserves the right to make changes at any time without notice in order
to improve design and supply the best possible product.
Full
Production
This data sheet contains final specifications. National Semiconductor
Corporation reserves the right to make changes at any time without
notice in order to improve design and supply the best possible product.
"
No
·kIentIfIcatIon
' ..
"Noted
..
Definition
Formative or
In Design
National Semiconductor Corporation reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. National does not assume any liability arising out of the application or use of any product
or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.
vi
Table of Contents
Alphanumeric Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 1 CMOS EPROMS
CMOS EPROM Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ONE TIME PROGRAMMABLE EPROMS AND SURFACE MOUNT
PACKAGING-INTRODUCTION.............................................
NMC27C16 16,384-Bit (2048 x 8) UV Erasable CMOS PROM ......................
NMC27C32 32,768-Bit (4096 x 8) UV Erasable CMOS PROM......................
NMC27C32B 32,768-Bit (4k x8) High Speed Version UV Erasable CMOS PROM. ... .
NMC27C64 65,536-Bit (8k x 8) UV Erasable CMOS PROM. . . . . . . . . . . . . . . . . . . . . . . . .
NMC27C64N 65,536-Bit (8k x 8) One-Time Programmable CMOS PROM............
NMC27C128B High Speed Version 131,072 (16k x 8) CMOS PROM. . . . . . . . . . . . . . . . .
NMC27C128BN High Speed Version 131 ,072-Bit (16k x 8) One-Time Programmable
CMOS PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NMC27C256 262, 144-Bit (32k x 8) UV Erasable CMOS PROM .....................
NMC27C256B High Speed Version 262, 144-Bit (32k x 8) UV Erasable CMOS PROM. .
NMC27C256BN High Speed Version 262, 144-Bit (32k x 8) One-Time Programmable
CMOS PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NMC27C512A 524,288-Bit High Speed Version (64k x 8) UV Erasable CMOS PROM. .
NMC27C512AN 524,288-Bit (64k x 8) One-Time Programmable CMOS PROM. ... ...
NMC27C010 1,048,576-Bit (128k x 8) UV Erasable CMOS PROM. . . . . . . . . . . . . . . . . . .
NMC27C1024 1,048,576-Bit (64k x 16) UV Erasable CMOS PROM. . . . . . . . . . . . . . . . . .
Section 2 EEPROMS
Electrically Erasable Programmable Memory Selection Guide ......................
SERIAL ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY
NMC9306 256-Bit Serial Electrically Erasable Programmable Memory. . . . . . . . . . . . . . .
NMC93C06/C46 256-Bitl1024-Bit Serial Electrically Erasable Programmable Memory.
NMC93CS06/CS46 256-Bitl1024-Bit Serial Electrically Erasable Programmable
Memory...................................................................
NMC9307 256-Bit Serial Electrically Erasable Programmable Memory. . . . . . . . . . . . . . .
NMC9313B 256-Bit Serial Electrically Erasable Programmable Memory. . . . . . . . . . . . . .
NMC9346 1024-Bit Serial Electrically Erasable Programmable Memory. . . . . . . . . . . . . .
NMC9314B 1024-Bit Serial Electrically Erasable Programmable Memory... . .. ... ... .
NMC93C56/C66 2048-Bitl4096-Bit Serial Electrically Erasable Programmable
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NMC93CS56/CS66 2048-Bitl4096-Bit Serial Electrically Erasable Programmable
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NMC93CS06x3/CS46x3/CS56x3/CS66x3 Extended Voltage Serial EEPROM .......
NMC93C06x3/C46x3/C56x3/C66x3 Extended Voltage Serial EEPROM. . . . . . . . . . . . .
APPLICATION SPECIFIC EEPROM
NMC95C12 1024-Bit CMOS EEPROM with DIP Switches ........... , . . . . . . . . . . . . . .
APPLICATIONS NOTES
AB-15 Protecting Data in Serial Electrically Erasable Programmable Memory. . ... ... .
AB-18 Electronic Compass Calibration Made Easy with Electrically Erasable
Programmable Memory .....................................................
AB-22 Automatic Low Cost Thermostat. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-338 Designing with the NMC9306 .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-423 NMC9346-An Amazing Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-431 An Easy/Low Cost Serial Electrically Erasable Programmable Memory
Interface.. .. ...... ... .. .. .... . .... . . .. . . . .. .... . .. .. . ... . .. .. . . .. . ... . ... .
AN-433 Using the NMC9306 for Configuration and Production Information ...........
AN-481 Common 1/0 Applications for the NMC9306 and NMC9346 . . . . . . . . . . . . . . . . .
vii
x
1-3
1-4
1-5
1-12
1-19
1-28
1-37
1-46
1-56
1-67
1-76
1-86
1-97
1-107
1-116
1-127
2-3
2-4
2-11
2-19
2-30
2-36
2-41
2-48
2-53
2-61
2-72
2-83
2-91
2-100
2-102
2-103
2-105
2-111
2-114
2-117
2-120
Table of Contents (Continued)
Section 2 EEPROMS (Continued)
AN-482 Error betection and Correction Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-123
AN-507 Using the NMC93CSXX Family of Electrically Erasable Programmable
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-128
Reliability of National Semiconductor's Electrically Erasable Programmable Memory
Products .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-142
Section 3 PROMS
Bipolar PROM Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3
NON-REGISTERED BIPOLAR PROMS
Pl77 /87X288B (32 x 8) 256-Bit TTL logic PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6
DM54174S188 (32 x 8) 256-Bit TTL PROM. . ..... ... . ...... .. .... ... ..... .. . .... .
3-10
DM5417 4S288 (32 x 8) 256-Bit TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-14
DM5417 4S287 (256 x 4) 1024-Bit TTL PROM ....................................
3-18
DM54174S387 (256 x 4) 1024-Bit TTL PROM.... .. . . ... ... .... ... .. ... .. .. ..... .3-22
DM54174lS471 (256 x 8) 2048-Bit TTL PROM.. . .. . .. .. .. .. .. .. .. .. . .. . . .. . . .. . .
3-26
3-30
DM54174S472 (512 x 8) 4096-Bit TTL PROM.... ... ............ ... ..... . ... . ... .
DM54174S473 (512 x 8) 4096-Bit TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-34
3-38
DM54174S474 (512 x 8) 4096-Bit TTL PROM....... .... .... .. .......... . ... . ... .
DM54174S475 (512 x 8) 4096-Bit TTL PROM. ..... . ............ ... . .. .. . . . ..... .
3-42
DM54174S570 (512 x 4) 2048-Bit TTL PROM. .. . .. .. .. .. .. ...... .. ..... ... . .... .
3-46
3-50
DM54174S571 (512 x 4) 2048-Bit TTL PROM. .. .... ... .. ... .. .. . .. ... .. . . .... .. .
DM54174S572 (1024 x 4) 4096-Bit TTL PROM.. . .. .... .... ....... ... .. .... . .... .
3-54
3-58
DM5417 4S573 (1024 x 4) 4096-Bit TTL PROM ...............................•.. .
DM77/87S180, DM77/87S280 (1024 x 8) 8192-Bit TTL PROMs. .. . .. ..... . . .... .. .
3-62
3-66
DM77 /87S181, DM77 /87S281 (1024 x 8) 8192-Bit TTL PROMs. . . . . . . . . . . . . . . . . . . .
DM77/87S184 (2048 x 4) 8192-BitTTl PROM...................................
3-70
DM77/87S185 (2048 x4) 8192-BitTTl PROM...................................
3-74
REGISTERED BIPOLAR PROMS
DM77/87SR474 (512 x8) 4k-Bit Registered TTL PROM...........................
3-78
DM77 /87SR4 76 (512 x 8) 4k-Bit Registered TTL PROM . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-82
DM77 /87SR27 (512 x 8) 4k-Bit Registered TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-86
3-91
DM77 /87SR181 (1024 x 8) 8k-Bit Registered TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . .
APPLICATIONS INFORMATION
Bipolar PROM Devices in Plastic leaded Chip Carriers ........................... .
3-95
Non-Registered PROM Programming Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-99
Registered PROM Programming Procedure. .. .. . . ..... .... . .... ... .. .. . . . ... ... . 3-101
Standard Test load.. ... ... . .. ... ... . . .. . .. .. . . ..... . .. .. .... ... .. .... . .. . ... . 3-103
Switching Time Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103
Approved Programmers/Quality Enhancement.. .. ... ...... ........ .. .. . . . ... ... . 3-105
Section 4 ECl 1/0 STATIC RAMS
BiCMOS ECl I/O SRAM Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BICMOS SRAMS (ECl I/O)
NM51 00/NM1 00500 ECl I/O 256k BiCMOS SRAM 262,144 x 1-Bit . . . . . . . . . . . . . . . . .
NM100504INM5104 256k BiCMOS SRAM 64k x4 Bit.............................
NM10049464k BiCMOS SRAM 16kx4Bit ............. ........... ..............
NM10494 64k BiCMOS SRAM 16k x 4 Bit.. . .. .. . .. . .. .. .. .. .. .. . .. . .. . . .. .. .. .. .
NM100492/NM4492 2k x 9 Advanced Self-Timed SRAM ......................... .
NM10E149 256 x 4-Bit ECl EPROM.. . .. ..... . .... . .. .. ...... ... ... ..... . ..... .
NM1 00E149 256 x 4-Bit ECl EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
4-3
4-4
4-11
4-18
4-25
4-32
4-45
4-53
Table of Contents (Continued)
Section 4 ECl I/O STATIC RAMS (Continued)
APPLICATION NOTES
AN-565 Memory System Efficiency and How National Semiconductor's 256k x 1
BiCMOS SRAM Helps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-566 National Semiconductor's BiCMOS III Process Is latch-Up Immune..... .....
AN-567 Hot Carrier and Gate Oxide Reliability Characterization of National
Semiconductor's BiCMOS III Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-568 The Reliability of National Semiconductor's 256k x 1 BiCMOS SRAM
(NM5100/NM100500) ......................................................
AN-569 256k x 1 BiCMOS ECl SRAM Memory Cell Characterization and Alpha
Sensitivity Testing ..........................................................
AN-572 Understanding Advanced Self-Timed SRAMs . .. ... . . .... .. .. .. .. .. .. .... .
AN-573 Design Considerations for High Speed Architectures. . . . . . . . . . . . . . . . . . . . . . .
Section 5 TTL I/O STATIC RAMS
TTL I/O-MOS SRAM Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIPOLAR STATIC RAMS
DM54S189/DM74S189 64-Bit (16 x 4) TRI-STATE RAM. .. . .. .. .. .. .... .. .... .... .
DM54S189A1DM74S189A High Speed 64-Bit TRI-STATE RAM....................
DM74S289 64-Bit (16 x 4) Open Collector RAM ..................................
93l415A 1024 x 1-Bit Static Random Access Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93l422A 256 x 4-Bit Static Random Access Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . .. .
93l425A 1024 x 1-Bit Static Random Access Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93479256 x 9-Bit Static Random Access Memory ................ , .. .. ... ... .... .
MOS STATIC RAMS
MM54174C89 65-Bit TRI-STATE Random Access Read/Write Memory. . . . . . . . . . . . . .
MM54174C200 256-Bit TRI-STATE Random Access Read/Write Memory. . . . . . . . . . .
MM54174C910 256-Bit TRI-STATE Random Access Read/Write Memory. ..... .....
MM54174C989 64-Bit (16 x 4) TRI-STATE Random Access Memory. ..... .. ... .....
NMC2147H 4096 x 1-Bit Static RAM ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NMC2148H 1024 x 4-Bit Static RAM ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDGE TRIGGERED REGISTERS
DM75S68/68A/85S68/68A 16 x 4 Edge Triggered Registers .................•....
Section 6 Appendices/Physical Dimensions
STARTM Surface Mount Tape-and-Reel Specification ........................•....
Physical Dimensions. . .. . . ...... .. .. .. ... . ... . . .. . ... ... .. .. ...... .. . . ... .....
Bookshelf
Distributors
ix
4-62
4-64
4-67
4-69
4-72
4-73
4-80
5-3
5-4
5-4
5-11
5-15
5-20
5-26
5-32
5-39
5-44
5-48
5-53
5-57
5-62
5-67
6-3
6-31
Alpha-Numeric Index
93L415A 1024 x 1-Bit Static Random Access Memory ......................................... 5-15
93L422A 256 x 4-Bit Static Random Access Memory .......................................... 5-20
93L425A 1024 x 1-Bit Static Random Access Memory ......................................... 5-26
93479256 x 9-Bit Static Random Access Memory ............................................ 5-32
AN-388 Designing with the NMC9306 ...................................................... 2-105
AN-423 NMC9346-An Amazing Device ................................................... 2-111
AN-433 Using the NMC9306 for Configuration and Production Information ...................... 2-117
AN-481 Common 1/0 Applications for the NMC9306 ......................................... 2-120
AN-481 Common 1/0 Applications for the NMC9346 ......................................... 2-120
AN-507 Using the NMC93CSXX Family of Electrically Erasable Programmable Memory ........... 2-128
AN-565 Memory System Efficiency and How National Semiconductor's 256k x 1 BiCMOS SRAM
Helps ................................................................................. 4-62
AN-566 National Semiconductor's BiCMOS III Process Is Latch-Up Immune ...................... 4-64
AN-567 Hot Carrier and Gate Oxide Reliability Characterization of National Semiconductor's
BiCMOS III Technology ................................................................. 4-67
AN-568 The Reliability of National Semiconductor's 256k x 1 BiCMOS SRAM
(NM5100/NM100500) .................................................................. 4-69
AN-569 256k x 1 BiCMOS ECL SRAM Memory Cell Characterization and Alpha Sensitivity Testing .. 4-72
AN-572 Understanding Advanced Self-Timed SRAMs ......................................... 4-73
AN-573 Design Considerations for High Speed Architectures ................................... 4-80
DM54LS471 (256 x 8) 2048-Bit TTL PROM ............................•..................... 3-26
DM54S188 (32 x 8) 256-Bit TTL PROM ...................................................... 3-10
DM54S189 64-Bit (16 x 4) TRI-STATE RAM ................................................... 5-4
DM54S189A High Speed 64-Bit TRI-STATE RAM .............................................. 5-4
DM54S287 (256 x 4) 1024-Bit TTL PROM ................................................... 3-18
DM54S288 (32 x 8) 256-Bit TTL PROM ...................................................... 3-14
DM54S387 (256 x 4) 1024-Bit TTL PROM ................................................... 3-22
DM54S472 (512 x 8) 4096-Bit TTL PROM ................................................... 3-30
DM54S473 (512 x 8) 4096-Bit TTL PROM ............................... , ................... 3-34
DM54S474 (512 x 8) 4096-Bit TTL PROM ................................................... 3-38
DM54S475 (512 x 8) 4096-Bit TTL PROM ................................................... 3-42
DM54S570 (512 x 4) 2048-Bit TTL PROM ................................................... 3-46
DM54S571 (512 x 4) 2048-Bit TTL PROM ................................................... 3-50
DM54S572 (1024 x 4) 4096-BitTTL PROM ......................................... '......... 3-54
DM54S573 (1024 x 4) 4096-Bit TTL PROM ................. ; ................................ 3-58
DM74LS471 (256 x 8) 2048-Bit TTL PROM .................................................. 3-26
DM74S188 (32x8) 256-BitTTL PROM ...................................................... 3-10
DM74S189 64-Bit (16 x 4) TRI-STATE RAM ................................................... 5-4
DM74S189A High Speed 64-BitTRI-STATE RAM .............................................. 5-4
DM74S287 (256 x 4) 1024-Bit TTL PROM ................................................... 3-18
DM74S288 (32 x 8) 256-Bit TTL PROM .............. " ...................................... 3-14
DM74S289 64-Bit (16 x 4) Open Collector RAM .............................................. 5-11
DM74S387 (256 x 4) 1024-Bit TTL PROM ................................................... 3-22
DM74S472 (512 x 8) 4096-BitTTL PROM ......................., ............................ 3-30
DM74S473 (512 x 8) 4096-Bit TTL PROM ................................................... 3-34
DM74S474 (512 x 8) 4096-Bit TTL PROM ................................................... 3-38
DM74S475 (512 x 8) 4096-BitTTL PROM ................................................... 3-42
DM74S570 (512 x 4) 2048-BitTTL PROM ................................................... 3-46
DM74S571 (512 x 4) 2048-Bit TTL PROM ................................................... 3-50
DM74S572 (1024 x 4) 4096-Bit TTL PROM .................................................. 3-54
DM74S573 (1024 x 4) 4096-Bit TTL PROM .................................................. 3-58
x
Alpha-Numeric
Index(continUed)
DM75S68 16 x 4 Edge Triggered Registers .................................................. 5-67
DM75S68A 16 x 4 Edge Triggered Registers ................................................. 5-67
DM77S180 (1024 x 8) 8192-Bit TTL PROM .................................................. 3-62
DM77S 181 (1024 x 8) 8192-Bit TTL PROM .................................................. 3-66
DM77S184 (2048 x 4) 8192-Bit TTL PROM .................................................. 3-70
DM77S185 (2048 x 4) 8192-Bit TTL PROM .................................................. 3-74
DM77S280 (1024 x 8) 8192-Bit TTL PROM .................................................. 3-62
DM77S281 (1024 x 8) 8192-Bit TTL PROM .................................................. 3-66
DM77SR27 (512 x 8) 4k-Bit Registered TTL PROM ........................................... 3-86
DM77SR181 (1024 x 8) 8k-Bit Registered TTL PROM ......................................... 3-91
DM77SR474 (512 x 8) 4k-Bit Registered TTL PROM .......................................... 3-78
DM77SR476 (512 x 8) 4k-Bit Registered TTL PROM .......................................... 3-82
DM85S68 16 x 4 Edge Triggered Registers .................................................. 5-67
DM85S68A 16 x 4 Edge Triggered Registers ................................................. 5-67
DM87S180 (1024 x 8) 8192-Bit TTL PROM .................................................. 3-62
DM87S181 (1024 x 8) 8192-Bit TTL PROM .................................................. 3-66
DM87S184 (2048 x 4) 8192-Bit TTL PROM .................................................. 3-70
DM87S185 (2048 x 4) 8192-Bit TTL PROM .................................................. 3-74
DM87S280 (1024 x 8) 8192-Bit TTL PROM .................................................. 3-62
DM87S281 (1024 x 8) 8192-Bit TTL PROM ............................ , ..................... 3-66
DM87SR27 (512 x 8) 4k-Bit Registered TTL PROM ........................................... 3-86
DM87SR181 (1024 x 8) 8k-Bit Registered TTL PROM ................................ , ..... , .. 3-91
DM87SR474 (512 x 8) 4k-Bit Registered TTL PROM .......................................... 3-78
DM87SR476 (512 x 8) 4k-Bit Registered TTL PROM .......................................... 3-82
MM54C89 65-BitTRI-STATE Random Access Read/Write Memory ............................. 5-39
MM54C200 256-Bit TRI-STATE Random Access Read/Write Memory .......................... 5-44
MM54C910 256-Bit TRI-STATE Random Access Read/Write Memory .......................... 5-48
MM54C989 64-Bit (16 x 4) TRI-STATE Random Access Memory ............................... 5-53
MM74C89 65-Bit TRI-STATE Random Access Read/Write Memory ............................. 5-39
MM74C200 256-Bit TRI-STATE Random Access Read/Write Memory .......................... 5-44
MM74C910 256-Bit TRI-STATE Random Access Read/Write Memory .......................... 5-48
MM74C989 64-Bit (16 x 4) TRI-STATE Random Access Memory ............................... 5-53
NM10E149 256 x4-Bit ECl EPROM ........................................................ 4-45
NM1 00E149 256 x 4-Bit ECl EPROM ....................................................... 4-53
NM4492 2k x 9 Advanced Self-Timed SRAM ................................................. 4-32
NM5100 ECl I/O 256k BiCMOS SRAM 262,144 x 1-Bit. ........................................ 4-4
NM5104 256k BiCMOS SRAM 64k x 4 Bit. ................................................... 4-11
NM100492 2k x 9 Advanced Self-Timed SRAM ..........................•..................... 4-32
NM10494 64k BiCMOS SRAM 16k x 4 Bit. ................................................... 4-25
NM100494 64k BiCMOS SRAM 16k x 4 Bit .................................................. 4-18
NM100500 ECl I/O 256k BiCMOS SRAM 262,144 x 1-Bit ...................................... 4-4
NM100504 256k BiCMOS SRAM 64k x 4 Bit ................................................. 4-11
NMC27C010 1,048,576-Bit (128k x 8) UV Erasable CMOS PROM .............................. 1-116
NMC27C16 16,384-Bit (2048 x 8) UV Erasable CMOS PROM .................................... 1-5
NMC27C32 32,768-Bit (4096 x 8) UV Erasable CMOS PROM .................................. 1-12
NMC27C32B 32,768-Bit (4k x 8) High Speed Version UV Erasable CMOS PROM ................. 1-19
NMC27C64 65,536-Bit (8k x 8) UV Erasable CMOS PROM ..................................... 1-28
NMC27C64N 65,536-Bit (8k x 8) One-Time Programmable CMOS PROM ........................ 1-37
NMC27C128B High Speed Version 131,072 (16k x 8) CMOS PROM ............................. 1-46
NMC27C128BN High Speed Version 131 ,072-Bit (16k x 8) One-Time Programmable CMOS PROM. 1-56
NMC27C256 262, 144-Bit (32k x 8) UV Erasable CMOS PROM ................................. 1-67
xi
Alpha-Numeric
Index(continUed)
NMC27C256B High Speed Version 262, 144-Bit (32k x 8) UV Erasable CMOS PROM .............. 1-76
NMC27C256BN High Speed Version 262, 144-Bit (32k x 8) One-Time Programmable CMOS PROM • 1-86
NMC27C512A 524,288-Bit High Speed Version (64k x 8) UV Erasable CMOS PROM .............. 1-97
NMC27C512AN 524,288-Bit (64k x 8) One-Time Programmable CMOS PROM .................. 1-107
NMC27C1024 1,048,576-Bit (64k x 16) UV Erasable CMOS PROM ............................ 1-127
NMC93C06 256-Bit Serial Electrically Erasable Programmable Memory ....................•..... 2-11
NMC93C06x3 Extended Voltage Serial EEPROM ............................................. 2-83
NMC93C46 1024-Bit Serial Electrically Erasable Programmable Memory ......................... 2-11
NMC93C46x3 Extended Voltage Serial EEPROM ............................................. 2-83
NMC93C56 2048-Bit Serial Electrically Erasable Programmable Memory ...... ; , ................. 2-53
NMC93C56x3 Extended Voltage Serial EEPROM ............................................. 2-83
NMC93C66 4096-Bit Serial Electrically Erasable Programmable Memory ......................... 2-53
NMC93C66x3 Extended Voltage Serial EEPROM ............................................. 2-83
NMC93CS06 256-Bit Serial Electrically Erasable Programmable Memory ........................ 2-19
NMC93CS06x3 Extended Voltage Serial EEPROM ......................................•..... 2-72
NMC93CS46 1024-Bit Serial Electrically Erasable Programmable Memory •..............•....... 2-19
NMC93CS46x3 Extended Voltage Serial EEPROM ................................•........... 2-72
NMC93CS56 2048-Bit Serial Electrically Erasable Programmable Memory .........•......•...... 2-61
NMC93CS56x3 Extended Voltage Serial EEPROM ............................................ 2-72
NMC93CS66 4096-Bit Serial Electrically Erasable Programmable Memory ..•...•..•............. 2-61
NMC93CS66x3 Extended Voltage Serial EEPROM .•.......•...........................•...... 2-72
NMC95C12 1024-Bit CMOS EEPROM with DIP Switches ............•.........••...•.......... 2-91
NMC2147H 4096 x 1-Bit Static RAM .......•................................................ 5-57
NMC2148H 1024 x 4-Bit Static RAM ........................................................ 5-62
NMC9306 256-Bit Serial Electrically Erasable Programmable Memory ..................•.•....... 2-4
NMC9307 256-Bit Serial Electrically Erasable Programmable Memory .......•....•.......•...... 2-30
NMC9313B 256-Bit Serial Electrically Erasable Programmable Memory ...................•...... 2-36
NMC9314B 1024-Bit Serial Electrically Erasable Programmable Memory .............•.....•..... 2-48
NMC9346 1024-Bit Serial Electrically Erasable Programmable Memory .......................... 2-41
PL77X288B (32 x 8) 256-Bit TTL Logic PROM ...........................•.............•....... 3-6
PL87X288B (32 x 8) 256-Bit TTL Logic PROM .................................•.•.....•....... 3-6
,xii
Section 1
CMOS EPROMs
Section 1 Contents
CMOS EPROM Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . • . . . . . . . . . . . . .
ONE TIME PROGRAMMABLE EPROMS AND SURFACE MOUNT
PACKAGING-INTRODUCTION...................................................
NMC27C16 16,384-Bit (2048 x 8) UV Erasable CMOS PROM ............................
NMC27C32 32,768-Bit (4096 x 8) UV Erasable CMOS PROM.... .. .... .... .....•........
NMC27C32B 32,768-Bit (4k x 8) High Speed Version UV Erasable CMOS PROM ...........
NMC27C64 65,536-Bit (8k x 8) UV Erasable CMOS PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NMC27C64N 65,536-Bit (8k x 8) One-Time Programmable CMOS PROM.... ..•..... ......
NMC27C128B High Speed Version 131,072 (16k x 8) CMOS PROM ......................
NMC27C128BN High Speed Version 131,072-Bit (16kx 8) One-Time Programmable
CMOS PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NMC27C256 262, 144-Bit (32k x 8) UV Erasable CMOS PROM ...........................
NMC27C256B High Speed Version 262, 144-Bit (32k x 8) UV Erasable CMOS PROM. . . . . . . .
NMC27C256BN High Speed Version 262, 144-Bit (32k x 8) One-Time Programmable
CMOS PROM. . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NMC27C512A 524,288-Bit High Speed Version (64k x 8) UV Erasable CMOS PROM. . . . . . . .
NMC27C512AN 524,288-Bit (64k x 8) One-Time Programmable CMOS PROM .............
NMC27C010 1,048,576-Bit (128k x 8) UV Erasable CMOS PROM. . . . . . . . . . . . . . . . . . . . . . . . .
NMC27C1024 1,048,576-Bit (64k x 16) UV Erasable CMOS PROM .......................
1-2
1-3
1-4
1-5
1-12
1-19
1-28
1-37
1-46
1-56
1-67
1-76
1-86
1-97
1-107
1-116
1-127
_National
Semiconductor
CMOS EPROMs Non-Volatile
Memory Selection Guide
CMOS EPROMs and OTP PROMs
No. of
Prog.
Volt.
PS
Tol.
Temp.
Range
300,350,450,550
450
25
25
5%
5%
O'Cto +70'C
-40'C to + 85'C
24
24
300,350,450,550
450
25
25
5%
5%
O'Cto +70'C
-40'Cto +85'C
32k
32k
24
24
150,200,250
200,250
13
13
5%,10%
10%
O'Cto +70'C
-40'Cto +85'C
8kx8
8kx8
8kx8
8kx8
64k
64k
64k
64k
28
28
28
28
150
150,200,250
150,200
200,250
13
13
13
13
5%
10%
10%
10%
O'Cto +70'C
O'Cto +70'C
-40'Cto +85'C
-55'Cto + 125°C
NMC27C128BQ/BN
NMC27C128BQE
NMC27C128QM
16kx8
16kx8
16kx8
128k
128k
128k
28
28
28
150,200,250
150,200
150,200
13
13
13
5%,10%
10%
10%
O'Cto +70'C
-40'Cto + 85'C
-55'C to + 125°C
NMC27C256Q
NMC27C256Q
NMC27C256QE
NMC27C256QM
32kx8
32kx8
32kx8
32kx8
256k
256k
256k
256k
28
28
28
28
170,200,250
200,250,300
200,250
250,350
13
13
13
13
5%
10%
10%
10%
O'Cto +70'C
O'Cto +70'C
-40'Cto +85'C
-55'Cto + 125'C
NMC27C256BQ/BN
NMC27C256BQE
NMC27C256BQM
32kx8
32kx8
32kx8
256k
256k
256k
28
28
28
150,200,250
150,200
150,200
13
13
13
5%,10%
10%
10%
O'Cto +70'C
- 40'C to + 85'C
-55'Cto + 125°C
NMC27C512AQIAN
NMC27C512AQE
NMC27C512ANE
NMC27C512AQM
64kx8
64kx8
64kx8
64kx8
512k
512k
512k
512k
28
28
28
28
150,170,200,250
150,170,200,250
150,170,200,250
150,170,200,250
13
13
13
13
5%,10%
10%
10%
10%
O'Cto +70'C
-40'Cto +85'C
-40'Cto +85'C
-55'Cto + 125°C
NMC27C010Q
NMC27C010QE
NMC27C010QM
128kx 8
128kx8
128kx 8
1024k
1024k
1024k
32
32
32
150, 170, 200, 250
150,170,200,250
170,200,250
13
13
13
5%,10%
10%
10%
O'Cto +70'C
- 40'C to + 85'C
-55'C to + 125°C
NMC27C1024Q
NMC27C1024QE
NMC27C1024QM
64kx16
64kx16
64kx 16
1024k
1024k
1024k
40
40
40
120,150,170,200,250
150,170,200
170,200
13
13
13
5%,10%
10%
10%
O'Cto +70'C
- 40'C to + 85'C
-55'Cto +125'C
Part No.
Org.
Size
NMC27C16Q
NMC27C16QE
2kx8
2kx8
16k
16k
24
24
NMC27C32Q
NMC27C32QE
4kx8
4kx8
32k
32k
NMC27C32BQ
NMC27C32BQE
4kx8
4kx8
NMC27C64Q
NMC27C64Q/N
NMC27C64QE
NMC27C64QM
Access
Time
Pins
1·3
III
::i
oII:
a..
w
CD
:cCIS
E
E
f!
~National
~ Semiconductor
ONE TIME PROGRAMMABLE EPROMs
c:n
e
a..
CD
E
j::
CD
C
o
One Time Programmable is the term coined for EPROMs encapsulated in packages without a quartz window. The absence of
the quartz window prevents erasure as the EPROM die is no longer capable of being exposed to any source of UV light. Thus
the user can program the device only once, thereby giving rise to the term One Time Programmable or OTP.
One Time Programmable EPROMs are frequently packaged in Dual-In-Line Packages (DIP) or surface mount Plastic Leaded
Chip Carriers (PLCC).
Dual-In-Line Package
The plastic DIP has lead spacing of 0.100 inch and is particularly advantageous for users of EPROMs that are in high volume
production. Plastic being less brittle than ceramic, the PDIPs can be used with auto insertion equipment, thereby offering an
additional advantage to high volume users by reducing manufacturing throughput time.
Density
Product Nomenclature
64kbit
NMC27C64N
128 kbit
NMC27C128BN
256 kbit
NMC27C256BN
512 kbit
NMC27C512AN
Surface Mount Package
Plastic Leaded Chip Carriers (PLCC) allow for a three to one improvement in surface mounting density over the plastic DIP, due
to the tighter lead spacings of 0.050 inch. As the leads bond to the surface of the board (vs. through hole mounting for DIPs),
system deSign engineers can optimize their PC board density by placing components on both sides of the PC board.
These packages are advantageous for cost sensitive, high volume users that are board space constrained and want to increase
their manufacturing throughput with the aid of auto insertion equipment.
National Semiconductor's scheduled introduction of a broad range of high density EPROMs in PLCC through early 1990 include:
Density
128 kbit
Product Nomenclature
NMC27C128BV
256 kbit
NMC27C256BV
512 kbit
NMC27C512AV
1 Mbit(X8)
NMC27C010V
1 Mbit(XI6)
NMC27Cl024V
National Semiconductor has had many years of experience building surface mount packages. The company has an excellent
reputation in the industry for product reliability. EPROMs in both the Plastic Dual-In-Line Package and the Plastic Leaded Chip
Carrier will be built with the same stringent reliability standards as other National products.
1-4
z
o==
~National
~
N
......
Semiconductor
o
....
Q)
NMC27C16
16,384-Bit (2048 x 8) UV Erasable CMOS PROM
General Description
Features
The NMC27C16 is a high speed 16k UV erasable and electrically reprogrammable CMOS EPROM, ideally suited for
applications where fast turnaround, pattern experimentation
and low power consumption are important requirements.
• Access time down to 300 ns
• Low CMOS power consumption
- Active Power: 26.25 mW max
- Standby Power: 0.53 mW max (98% savings)
• Performance compatible to NSCBOOTM CMOS
microprocessor
• Single 5V power supply
• Extended temperature range available
(NMC27C16E-45), -40'C to +85'C, 450 ns ±5%
power supply
• Pin compatible to MM2716 and higher density EPROMs
• Static-no clocks required
• TTL compatible inputs/outputs
• TRI-STATE® output
The NMC27C16 is packaged in a 24-pin dual-in-line package with transparent lid. The transparent lid allows the user
to expose the chip to ultraviolet light to erase the bit pattern.
A new pattern can then be written into the device by following the programming procedure.
This EPROM is fabricated with the reliable, high volume,
time proven, p2CMOSTM silicon gate technology.
Block Diagram
.
DATA OUTPUTS 00-07
Vee 0---+
GND~
Vpp
Pin Names
0---+
OUTPUT ENABLE
CHIP ENABLE
AND PROG LOGIC
y
DECODER
AD-A1D
ADDRESS
INPUTS
X
DECODER
OUTPUT
BUFFERS
Y GATING
16.3B4-8IT
CELL MATRIX
TL/D/5275-1
1-5
AO-A1D
Addresses
CE
Chip Enable
OE
Output Enable
00-0 7
Outputs
PGM
Program
NC
No Connect
CD
.,...
ol"-
Connection Diagram
N
o
::!l
z
27C256
27C128
27C64
27C32
27C32
27256
27128
2764
2732
2732
Vpp
Vpp
Vpp
A12
A12
A12
A7
A7
A7
Dual-In-Llne Package
NMC27C;;16
27C64 27C128 27C256
2764
27128
27256
Vee
Vee
Vee
PGM
PGM
A14
A13
A8
A7
A7- 1
24 f- Vee
Vee
NC
A13
23 f- A8
A8
A8
A8
A9
A9
A9
A9
A11
A11
A11
A11
A6
A6
A6
A6
A6- 2
A5
A5
A5
A5
A5- 3
22 f-A9
A4
A4
A4
A4
A4- 4
21 f-
A3
A3
A3
A3
A3- 5
20 rlll"
OElVpp
OE
OE
OE
Vpp
A2
A2
A2
A2
A2- 6
19 f- Al0
A10
A10
A10
A10
A1
A1
A1
A1
Al- 7
18 f-"Cf
CE
CE
CE
CE
AO
AO
AO
AO
AO- 8
17 f- D,
07
07
07
07
00
00
00
00
Do- 9
16 rD,
06
06
06
06
0,
0,
0,
0,
D,-10
15 f-D,
OS
Os
Os
Os
02
02
02
02
D'-11
14 rD,
04
04
04
04
GND
GND
GND
GND
GND- 12
13 f-D,
03
03
03
03
TLiD/5275-2
Top View
Note: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMC27C16 pins.
Order Number NMC27C16
See NS Package Number J24AQ
Commercial Temp Range (O'C to
+ 70'C) Vee
=
5V ± 5%
Parameter/Order Number
Access Time (ns)
NMC27C16-30
300
NMC27C16-35
350
NMC27C16-45
450
NMC27C16-55
550
1-6
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Power Dissipation
Temperature Under Bias
Operating Conditions
All Output Voltages with
Respect to Ground (Note 11)
300°C
0)
-65°C to +125°C
All Input Voltages with
Respect to Ground
1.0W
Lead Temperature (Soldering, 10 seconds)
-10°C to + BO°C
Storage Temperature
(Note 9)
Temperature Range
NMC27CI6-30, ·35, -45, ·55
NMC27C16E·45
+6.5Vto -0.3V
O°Cto +70°C
-40°C to +B5°C
5V ±5%
Vee Power Supply (Notes 2 and 3)
Vee+0.3V to GND-0.3V
Vpp Supply Voltage with
Respect to Ground
During Programming
Vpp Power Supply (Note 3)
Vee
+ 26.5V to - 0.3V
READ OPERATION
DC Electrical Characteristics
Symbol
Parameter
Min
Conditions
Typ (Note 4)
Max
Units
10
/LA
10
/LA
2
10
mA
1
5
mA
0.1
1
mA
0.01
0.1
mA
= Vee or GND
III
Input Load Current
VIN
ILO
Output Leakage Current
leel
(Note 3)
Vee Current (Active)
TTL Inputs
= Vee or GND, CE = VIH
DE = CE = VIL, f = 1 MHz
Inputs = VIH or VIL, liD = 0 mA
lee2
(Note 3)
Vee Current (Active)
CMOS Inputs
DE = CE = VIL, f = 1 MHz
Inputs = Vee or GND, liD = 0 mA
leeSBl
Vee Current (Standby)
TTL Inputs
CE
= VIH
leeSB2
Vee Current (Standby)
CMOS Inputs
CE
= Vee
VOUT
VIL
Input Low Voltage
-0.1
O.B
V
VIH
Input High Voltage
2.0
Vee + 1
V
VOL1
Output Low Voltage
IOL
= 2.1 rnA
0.45
V
VOHl
Output High Voltage
IOH
= -400/LA
VOL2
Output Low Voltage
IOL
= 0/LA
0.1
V
VOH2
Output High Voltage
IOH
= 0/LA
V
2.4
V
Vee - 0.1
AC Electrical Characteristics
NMC27C16
Symbol
Parameter
-30
Conditions
Min
tAee
Address to Output Delay
CE
teE
CE to Output Delay
DE
toE
DE to Output Delay
tDF
DE High to Output Float
tOH
(Note 5)
Output Hold from Addresses,
CE or DE, Whichever
Occurred First
= OE = VIL
=
CE =
CE =
CE =
-35
Max
Min
E-45, -45
Max
Min
Max
-55
Min
Units
Max
300
350
450
550
ns
VIL
300
350
450
550
ns
VIL
120
120
120
160
ns
100
ns
0
VIL
DE
z
oN
......
o
.....
3:
(Note 1)
100
0
100
0
100
0
= VIL
0
1-7
0
0
0
ns
CI)
..-
~
Capacitance T A = + 25°C, f
=
1 MHz (Note 5)
N
o
Symbol
z
CIN
Input Capacitance
VIN = OV
4
6
pF
COUT
Output Capacitance
VOUT = OV
8
12
pF
:E
Parameter
Conditions
Typ
Max
Units
AC Test Conditions
Output Load
1 TTL Gate and
Timing Measurement Reference Level
Inputs
CL = 100pF
Input Rise and Fall Times
0.8Vand2V
Outputs
,,20n8
Input Pulse Levels
;.
1Vand2V
0.8Vto2.2V
AC Waveforms
(Notes 2, 8, 9,10)
ADDRESSES
VALID
ADDRESSES
CE
V~
VIL
DE
VIH
VIL
OUTPUT
HI-Z
VOH
VOL
TUD/5275-3
Nota 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanant damage to the device. This Is a stress rating only and functional
operation of the device at these or any other condHions above those indicated in the operaUonal sactions of this specification Is not implied. Exposura to absolute
maximum rating conditions for extended periods may affect device reliabliHy.
Note 2: Vee must be applied simultaneously or before Vpp and removed simul1aneously or after Vpp.
Note 3: Vpp may be connected to Vee except during programming. ICC1
Note 4: Typical values are for TA =
s:
the sum of the lee active and Ipp read currents.
+ 25·C and nominal supply voltages.
Note 5: This parameter is only sampled and is not 100% tested.
Nota 6: OE may be delayed up to tACC - toE after the falling edge of CE without Impact on tAf!C'
Nota 7: The tOF compare level is determined as follows:
High to TRI·STATE, the measured VOH1 (DC) - O.10V
Low to TRI·STATE, the measured VOLI (DC) + 0.10V
Nota e: TRI·STATE may be attained using
m: or CE.
Nota 9: The power swHching characteristics of EPROMs require careful device decoupling. It Is recommended that a 0.1 ,..F ceramic capaCItor be used on every
device between Vee and GND.
Note 10: The NMC27C16 requires one address transition after initial power-up to reset the outputs.
Nota 11: The outputs must be restricted to Vee
+
0.3V to avoid latch·up and device damage.
1-8
PROGRAMMING CHARACTERISTICS
z
3:
oN
......
o.....
(Note 1)
DC Programming Characteristics (Notes 2 & 3)
(TA
en
= +25°C ±5°C, Vee = 5V ±5%, Vpp = 25V ±1V)
Symbol
Parameter
III
Input Current (for Any Input)
Ipp
Vpp Supply Current During
Programming Pulse
Conditions
Typ
Min
= Vee or GND
CE/PGM = VIH
VIN
Max
Units
10
!,-A
30
mA
lee
Vee Supply Current
10
mA
VIL
Input Low Level
-0.1
O.B
V
VIH
Input High Level
2.0
Vee + 1
V
AC Programming Characteristics (Notes 2 & 3)
(TA
= +25°C ±5°C, Vee = 5V ±5%, Vpp = 25V ±1V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
tAS
Address Setup Time
2
!,-S
toES
OE Setup Time
2
!,-S
tos
Data Setup Time
2
!,-S
tAH
Address Hold Time
2
!,-S
tOEH
OE Hold Time
2
!,-S
tOH
Data Hold Time
2
tOF
Output Enable to Output Float Delay
CE/PGM
= VIL
tOE
Output Enable to Output Delay
CE/PGM
= VIL
tpw
Program Pulse Width
tpRT
Program Pulse Rise Time
5
ns
tPFT
Program Pulse Fall Time
5
ns
!,-S
160
0
45
50
ns
160
ns
55
ms
AC Test Conditions
Vee
Vpp
Input Rise and Fall Times
Input Pulse Levels
5V ±5%
Timing Measurement Reference Level
Inputs
Outputs
25V ±1V
,;;20 ns
O.BVto 2.2V
1-9
1Vand2V
0.BVand2V
....
U) r-----------------------------------------------------------------------------------------~
~
C\I
o
Programming Waveforms (Note 3) Vpp =
25V ± W, VCC = 5V ±5%
-----1------ P~~:~;,M-----;+_------
:::&
z
ADDRESS VIH
ADDRESS N
ADDRESS N+ m
~VI~L____J~____________~--------------~,~---------
_---...J
IAH) - - - + 1
1----(2
lI""'-f-.................,.-_
Hi.Z VOH
DATA IN STABLE
ADD N+m
toF
(D.16MAX)
_ VIH
DE VIL
TL/D/5275-4
Note: All times shown in parentheses are minimum and in
,...5 unless otherwise specified.
Note I: National's standard product warranty applies only to devices programmed to specifications described herein.
Note 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The NMC27CI6 must not be inserted into or removed from a
board with Vpp at 25V ± tV to prevent damage to the device.
Note 3: The maximum allowable voltage which may be applied to the Vpp pin during programming is 26V. Care must be taken when switching the Vpp supply to
prevent overshoot exceeding this 26V maximum specification. A 0.1 I'F capacitor is required across VPP. Vee 10 GND to suppress spurious voltage transients
which may damage the device.
Functional Description
b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended that CE (pin 18) be decoded and used as the primary device selecting function, while OE (pin 20) be made a
common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low
power standby modes and that the output pins are active
only when data is desired from a particular memory device.
DEVICE OPERATION
The six modes of operation of the NMC27C16 are listed in
Table I. It should be noted that all inputs for the six modes
are at TTL levels. The power supplies required are a 5V Vcc
and a Vpp. The Vpp power supply must be at 25V during the
three programming modes, and must be at 5V in the other
: three modes.
Read Mode
The NMC27C16 has two control functions. both of which
must be logically active in order to obtain data at the out·
puts. Chip Enable (CE) is the power control and should be
used for device selection. Output Enable (OE) is the output
control and should be used to gate data to the output pins,
independent of device selection. Assuming that addresses
are stable, address access time (tACe) is equal to the delay
from CE to output (teE)' Data is available at the outputs tOE
after the falling edge of OE, assuming that CE has been low
and addresses have been stable for at least tACC-tOE' The
NMC27C16 requires one address transition after initial pow·
er-up to reset the outputs.
Programming
CAUTION: Exceeding 26.5V on pin 21 (Vpp) will damage the
NMC27C16.
Initially, and after each erasure, all bits of the NMC27C16
are in the "1" state. Data is introduced by selectively programming "Os" into the desired bit locations. Although only
"Os" will be programmed, both "1 s" and "Os" can be pre·
sented in the data word. The only way to change a "0" to a
"1" is by ultraviolet light erasure.
The NMC27C16 is in the programming mode when the Vpp
power supply is at 25V and OE is at VIH. It is required that a
0.1 ",F capacitor be placed across Vpp, Vcc to ground to
suppress spurious voltage transients which may damage
the device. The data to be programmed is applied 8 bits in
parallel to the data output pins. The levels required for the
address and data inputs are TTL.
Standby Mode
The NMC27C16 has a standby mode which reduces the
active power dissipation by 98%, from 26.25 mW to
0.53 mW. The NMC27C16 is placed in the standby mode by
applying a TTL high signal to the CE input. When in standby
mode, the outputs are in a high impedance state, independent of the OE input.
When the address and data are stable, a 50 ms, active high,
TTL program pulse is applied to the CE/PGM input. A program pulse must be applied at each address location to be
programmed. You can program any location at any time--either individually, sequentially, or at random. The program
pulse has a maximum width of 55 ms. The NMC27C16 must
not be programmed with a DC Signal applied to the CEI
PGM input.
Output OR-Tying
Because NMC27C16s are usually used in larger memory
arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
a) the lowest possible memory power dissipation, and
1-10
z
s::
o
Functional Description
(Continued)
Programming multiple NMC27C16s in parallel with the same
data can be easily accomplished due to the simplicity of the
programming requirements. Like inputs of the paralleled
NMC27C16s may be connected together when they are
programmed with the same data. A high level TTL pulse
applied to the CE/PGM input programs the paralleled
NMC27CI6s.
12,000 ",W/cm 2 power rating. The NMC27C16 should be
placed within 1 inch of the lamp tubes during erasure. Some
lamps have a filter on their tubes which should be removed
before erasure.
Note: The NMC27C16·55 may take up to 60 minutes for complete erasure
to occur.
An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one inch.
The erasure time increases as the square of the distance. (If
distance is doubled the erasure time increases by a factor of
4.) Lamps lose intensity as they age. When a lamp is
changed, the distance has changed, or the lamp has aged,
the system should be checked to make certain full erasure
is occurring. Incomplete erasure will cause symptoms that
can be misleading. Programmers, components, and even
system designs have been erroneously suspected when incomplete erasure was the problem.
Program Inhibit
Programming multiple NMC27C16s in parallel with different
data is also easily accomplished. Except for CE/PGM, all
like inputs (including OE) of the parallel NMC27C16s may
be common. A TTL level program pulse applied to an
NMC27CI6's CE/PGM input with Vpp at 25V will program
that NMC27CI6. A low level CE/PGM input inhibits the other NMC27C16 from being programmed.
Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with Vpp at 25V. Vpp must be at
Vee, except during programming and program verify.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, lee,
has three segments that are of interest to the system designer-the standby current level, the active current level,
and the transient current peaks that are produced on the
falling and rising edges of chip enable. The magnitude of
these transient current peaks is dependent on the output
capacitance loading of the device. The associated transient
voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that a 0.1 ",F ceramic capacitor be used on every device between Vee and
GND. This should be a high frequency capacitor of low inherent inductance. In addition, a 4.7 ",F bulk electrolytic capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
ERASURE CHARACTERISTICS
The erasure characteristics of the NMC27C16 are such that
erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It
should be noted that sunlight and certain types of f1uorescent lamps have wavelengths in the 3000A-4000A range.
Opaque labels should be placed over the NMC27C16 window to prevent unintentional erasure. Covering the window
will also prevent temporary functional failure due to the generation of photo currents.
The recommended erasure procedure for the NMC27C16 is
exposure to short wave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV
intensity X exposure time) for erasure should be a minimum
of 15W-sec/cm2 • The erasure time with this dosage is approximately 21 minutes using an ultraviolet lamp with a
TABLE I. Mode Selection
Mode
CE/PGM
(18)
OE
(20)
Vp
(21)
Vee
(24)
Outputs
(9-11,13-17)
Read
VIL
VIL
Vee
5
DOUT
Standby
VIH
Don't Care
Vee
5
Hi-Z
Program
Pulsed VIL to VIH
VIH
25
5
DIN
Program Verify
VIL
VIL
25
5
DOUT
Program Inhibit
VIL
VIH
25
5
Hi-Z
Output Disable
X
VIH
Vee
5
Hi-Z
Pins
1-11
N
......
o
......
en
~
CO)
fi
:::&
Z
,----------------------------------------------------------------------------,
~NaHonal
~ Semiconductor·
NMC27C32
32,768-Bit (4096 x 8) UV Erasable CMOS PROM
Gen.eral Description
Features
The NMC27C32 is a high speed 32k UV erasable and electrically reprogram mabie CMOS EPROM, ideally suited for
applications where fast turnaround, pattern experimentation
and low power consumption are important requirements.
The NMC27C32 is packaged in a 24-pin dual-in-line package with transparent lid. The transparent lid allows the user
to expose the chip to ultraviolet light to erase the bit pattern.
A new pattern can then be written into the device by following the programming procedure.
This EPROM is fabricated with the reliable, high voluine,
time proven, p2CMOSTM silicon gate technology.
• Access time down to 300 ns
• Low CMOS power consumption
Active power: 26.25 mW max
Standby power: 0.53 mW max (98% savings)
• Extended temperature range available· (NMC27C32E-45
and NMC27C32HE-45), -40'C to + 85'C, 450 ns
±5% power supply
• 10 ms programming available (NMC27C32H), an 80%
time savings
• Pin compatible to NMC2732 and higher density
EPROMs
• Static-no clocks required
• TTL compatible inputs/ outputs
• Two-line control
• TRI-STATEIB> output
Block Diagram
DATA DUTPUTSDo-D7
Vee 0--+
GNDo--+
Vpp 0--+
OUTPUT ENABLE AND
CHIP ENABLE
LOGIC
y
DECODER
AD-All
ADDRESS
INPUTS
X
DECODER
OUTPUT
BUFFERS
Pin Names
Y GATING
32,768-BIT
CELL MATRIX
TL/D/5274-1
1-12
AO-A11
Addresses
CE
Chip Enable
OE
Output Enable
0 0- 0 7
Outputs
z
s:::
Connection Diagram
27C216 27C64 27C128 27C256
27C256 27C128 27C64 27C16
27256
27128
2764
Vpp
Vpp
Vpp
A12
A12
A12
A7
A7
A7
27216
2716
NMC27C32
Dual-In-Line Package
2764
27128
27256
Vcc
Vcc
Vcc
PGM
PGM
A14
A13
A13
A7
A7-1
24 -Vee
Vcc
NC
23 -A8
A8
AS
AS
AS
22 -A9
A9
A9
A9
A9
A6
A6
A6
A6
A6- 2
A5
A5
A5
A5
A5- 3
A4
A4
A4
A4
A4-4
21 -All
Vpp
All
All
All
A3
A3
A3
A3
A3-5
20 -
OE
OE
OE
OE
A2
A2
A2
A2
A2- 6
19 -AID
Al0
Al0
Al0
Al0
Al
Al
Al
Al
Al- 7
18
-CE
CE
CE
CE
CE
AO- 8
17 - 0 ,
07
07
07
07
Os
Os
Os
OE/Vpp
AO
AO
AO
AO
00
00
00
00
00- 9
16 -06
Os
01
01
01
01
0 , - 10
15 - 0 ,
Os
Os
Os
Os
02
02
02
02
02-11
14 -04
04
04
04
04
GND
GND
GND
GND
GNO- 12
13 -03
03
03
03
03
TL/D/5274-2
Top View
Order Number NMC27C32
See NS Package Number J24AQ
Note: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMC27C32 pins.
Commercial Temp Range (O'C to + 70·C) Vee
= 5V ± 5%
Parameter/Order Number
Access Time (ns)
NMC27C32-30, NMC27C32H-30
300
NMC27C32-35, NMC27C32H-35
350
NMC27C32-45, NMC27C32H-45
450
NMC27C32-55, NMC27C32H-55
550
Extended Temp Range (-40'C to +8SOC) Vee
= 5V ±5%
I Access Time (ns)
450
NMC27C32E-45, NMC27C32EH-45 I
Parameter/Order Number
1-13
o
N
......
o
(0)
N
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature. under Bias
-10"C to +80·C
- 65·C to + 125·C
Storage Tem~erature
Power Dissipation
Lead Temperature (Soldering, 10 seconds)
1.0W
300·C
Operating Conditions (Note 7)
Temperature Range
NMC27C32-30, NMC27C32-35,
NMC27C32-45, NMC27C32-55,
NMC27C32H-30, NMC27C32H-35,
NMC27C32H-45, NMC27C32H-55
NMC27C32HE-45, NMC27C32E-45
,All Input Voltages with
+6.5Vto -0.3V
Respect to Ground
All Output Voltages with
Respect to Ground
Vcc + 0.3VtoGND -0.3V
Vpp Supply Voltage with Respect
to Ground during Programming
+ 26.5Vto -0.3V
O·Cto +70·C
-40·Cto +85·C
5V±5%
Vee Power Supply
READ OPERATION
DC Electrical Characteristics
Symbol
Parameter
Conditions
Typ(Note 2)
Min
Max
Units
III
Input Load Current
VIH = Vec or GND
10
/LA
ILO
Output Leakage Current
VOUT = Vec or GND, CE = VIH
10
/LA
ICCl
Vcc Current (Active)
TTL Inputs
OE = CE = VIL
Inputs = VIH or VIL, f = 1 MHz
I/O = OmA
2
10
mA
Vce Current (Active)
CMOS Inputs
OE = CE = VIL
Inputs = Vee or GND, f = 1 MHz
1/0 = OmA
1
5
mA
leeSBl
Vee Current (Standby)
TTL Inputs
CE = VIH
0.1
1
mA
IceSB2
Vee Current (Standby)
CMOS Inputs
CE = Vee
0.Q1
0.1
mA
VIL
Input Low Voltage
-0.1
0.8
V
VIH
Input High Voltage
2.0
Vee + 1
V
VOL1
Output Low Voltage
0.45
V
VOHl
Output High Voltage
IOH = -400/LA
VOL2
Output Low Voltage
IOL = O/LA
0.1
V
VOH2
Output High Voltage
IOH = O/LA
ICC2
IOL = 2.1 mA
2.4
V
V
Vcc - 0.1
AC Electrical Characteristics
NMC27C32
Symbol
Parameter
Conditions
-30, H-30
Min
Max
-35, H-35
Min
Max
-45, H-45
E-45; HE-45
Min
Max
-55, H-55
Min
Units
Max
tACC
Address to Output Delay
CE = OE = VIL
300
350
450
550
ns
teE
CE to Output Delay
OE = VIL
300
350
450
550
,ns
tOE
OE to Output Delay
CE = VIL
150
150
150
150
ns
tOF
OE High to Output Float
CE = VIL
130
ns
toH
(Note 3)
Output Hold from Addresses,
CE or OE, Whichever
Occurred First
CE = OE = VIL
0
0
1-14
130
0
0
130
0
0
130
0
0
ns
Capacitance TA = + 25'C, f =
Symbol
Parameter
1 MHz (Note 3)
Conditions
CIN!
Input Capacitance
Except OElVpp
VIN = OV
CIN2
OElVpp Input
Capacitance
VIN = OV
COUT
Output Capacitance
VOUT = OV
Typ
Max
Units
4
6
pF
20
pF
12
pF
B
AC Test Conditions
Timing Measurement Reference Level
Inputs
Outputs
1 TTL Gate and
CL=100pF
s;20 ns
Output Load
Input Rise and Fall Times
Input Pulse Levels
1Vand2V
0.BVand2V
0.45V to 2.4V
AC Waveforms
(Notes 6 & 8)
ADDRESSES
Y;;""'
Vll
-
ADDRESSES VALID
VIH
VIL
\.
VOH
"
VOL
--
)
tOE
(NOTE 4)
HI-Z
IACC
).
I
I-- tcE _
VIH
VIL
OUTPUT
"
I-
-00
VALID OUTPUT
HI-Z
.,
_
-00
(NOTE 4)
lor
(NOTE 5)
IoHI.TL/D/5274-3
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: Typical values are for T A = + 25·C and nominal supply vollages.
Note 3: This parameter is only sampled and is nollOO% tested.
Note 4: DE may be delayed up to tACC - tOE aller the falling edge of CE withoUi impacting tACC.
Note 5: The tOF compare level is determined as follows:
High to TRI-STATE.the measured VOH' (DC) - O.lOV;
Low to TRI-STATE. the measured VOU (DC) + O.lOV.
Note 6: TRI-STATE may be attained using OE or CE.
Note 7: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that a 0.1 p.F ceramic capaCitor be used on every
device between Vec and GND.
Note 8: The outputs must be restricted to Vee
+
0.3V to avoid lalch-up and device damage.
1-15
PROGRAMMING
(Note 1)
DC Programming Characteristics
TA
=
+25°C ±5°C, Vee
=
Symbol
5V ± 5%, Vpp
=
25V ±1V (Notes 2 and 3)
Conditions
Parameter
III
Input Current (All Inputs)
VIN
VOL
Output Low Voltage During Verify
IOL
= Vee or GND
= 2.1 mA
VOH
Output High Voltage During Verify
IOH
= -
lee
Vee Supply Current
VIL
Input Low Level (All Inputs)
Max
Units
10
/LA
0.45
Input High Level (All Inputs except OElVpp)
Ipp
V pp Supply Current
CE
AC Programming Characteristics TA =
Parameter
=
VIL,OE
=
V
2.4
400 /LA
V
10
mA
-0.1
0.8
V
2.0
Vee + 1
V
30
mA
2
VIH
Symbol
Typ
Min
Vpp
=
+25°C ±5°C, Vee
5V ± 5%, Vpp
=
25V ±1V
NMC27C32
Conditions
Min
Typ
NMC27C32H
Max
Min
Typ
Units
Max
tAS
Address Setup Time
2
2
/Ls
tOES
OE Setup Time
2
2
/Ls
tos
Data Setup Time
2
2
/Ls
tAH
Address Hold Time
0
0
/Ls
tOEH
OEHoldTime
2
2
/Ls
tOH
Data Hold Time
2
2
tOF
Chip Enable to Output Float Delay
0
=
=
, 130
/Ls
0
130
tov
Data Valid from CE
tpw
CE Pulse Width during Programming
45
tpRT
OE Pulse Rise Time during Programming
50
50
ns
tVR
Vpp Recovery Time
2
2
/Ls
CE
VIL, OE
1·16
1
ns
VIL
50
55
9
10
1
/Ls
11
ms
AC Test Conditions
Vcc
Vpp
Input Rise and Fall Times
Input Pulse Levels
5V ± 5%
Timing Measurement Reference Level
Inputs
Outputs
25V ± 1V
,;;20 ns
lVand2V
0.8V and 2V
0.45V to 2.4V
Programming Waveforms (Note 3)
DATA~--oo(J
iiElVpp
TL/D/5274-4
Nota: All times shown in parentheses are minimum and in Ils unless otherwise specified••
The input timing reference level is 1V for a VIL and 2V lor a VIH.
Note 1: National's standard product warranty applies only to devices programmed to specifications described herein.
Note 2: Vcc must not be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The NMC27C32 must not be inserted into or removed
from a board with Vpp at 25V ± 1V to prevent damage to the device.
Note 3: The maximum allowable voltage which may be applied to the Vpp pin during programming is 26V. Care must be taken when switching the Vpp supply to
prevent overshoot exceeding this 26V maximum specification. A 0.1 IlF capaCitor is required across Vee to GND to suppress spurious voltage transients which
may damage the device.
Functional Description (Continued)
DEVICE OPERATION
Output OR-Tying
The 6 modes of operation of the NMC27C32 are listed in
Table I. A single 5V power supply is required in the read
mode. All inputs are TIL levels except for OElVpp during
programming. In the program mode the OE/vpp input is
pulsed from a TIL level to 25V.
Because EPROMS are usually used in larger memory arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connection.
The 2-line control function allows for:
a) the lowest possible memory power diSSipation, and
Read Mode
The NMC27C32 has two control functions, both of which
must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be
used for device selection. Output Enable (OE) is the output
control and should be used to gate data to the output pins,
independent of device selection. Assuming that addresses
are stable, address access time (tACel is equal to the delay
from CE to output (teE)' Data is available at the outputs after
the falling edge of OE, assuming that CE has been low and
addresses have been stable for at least tAcc-toE.
b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended that CE (pin 18) be decoded and used as the primary device selecting function, while OE (pin 20) be made a
common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low
power standby modes and that the output pins are active
only when data is desired from a particular memory device.
Programming
CAUTION: Exceeding 26.5V on pin 20 (Vpp) will damage the
NMC27C32.
Initially, and after each erasure, all bits of the NMC27C32
are in the "1" state. Data is introduced by selectively programming "Os" into the desired bit locations. Although only
"Os" will be programmed, both "ls" and "Os" can be presented in the data word. The only way to change a "0" to a
"1" is by ultraviolet light erasure.
Standby Mode
The NMC27C32 has a standby mode which reduces the
active power dissipation by 98%, from 26.25 mW to
0.53 mW. The NMC27C32 is placed in the standby mode by
applying a TIL high Signal to the CE input. When in standby
mode, the outputs are in a high impedance state, independent of the OE input.
1-17
•
,
Functional Description (Continued)
the NMC27C32 window to prevent unintentional erasure.
Covering the window will also prevent temporary functional
failure due to the generation of photo currents.
The recommended erasure procedure for the NMC27C32 is
exprosure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV
intensity x exposure time) for erasure should be a minimum
of 15W-sec/cm2• The erasure time with this dosage is approximately 21 minutes using an ultraviolet lamp with a
12,000 fLW/cm2 power rating. The NMC27C32 should be
placed within 1 inch of the lamp tubes during erasure. Some
lamps have a filter on their tubes which should be removed
before erasure.
The NMC27C32 is in the programming mode when the OEI
Vpp input is at 25V. It is required that a 0.1 fLF capacitor be
placed across OElVpp, Vee, and ground to suppress spurious voltage transients which may damage the device. The
data to be programmed is applied 8 bits in parallel to the
data output pins. The levels required for the address and
data inputs are TTL.
When the address and data are stable, a 50 ms (10 ms for
the NMC27C32H devices) active low TTL program pulse is
applied to the CE input. A program pulse must be applied at
each address location to be programmed. You can program
any location at any time-either individually, sequentially, or
at random. The program pulse has a maximum width of
55 ms (11 ms for the NMC27C32H devices). The
NMC27C32 must not be programmed with a DC signal applied to the CE input.
Note: The NMC27C32·55 and NMC27C32H·55 may take up
An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one inch.
The erasure time increases as the square of the distance. (If
distance is doubled the erasure time increases by a factor of
4.) Lamps lose intensity as they age. When a lamp is
changed, the distance has changed or the lamp has aged,
the system should be checked to make certain full erasure
is occuring. Incomplete erasure will cause symptoms that
can be misleading. Programmers, components, and even
system designs have been erroneously suspected when incomplete erasure was the problem.
Programming of multiple NMC27C32s in parallel with the
same data can easily be accomplished due to the simplicity
of the programming requirements. Like inputs of the paralleled NMC27C32s may be connected together when they
are programmed with the same data. A low level TTL pulse
applied to the CE input programs the paralleled
NMC27C32s.
Program Inhibit
Programming multiple NMC27C32s in parallel with different
data is also easily accomplished. Except for CE, all like inputs (including OE) of the parallel NMC27C32s may be
common. A TTL level program pulse applied to an
NMC27C32's CE input with OElVpp at 25V will program
that NMC27C32. A high level CE input inhibits the other
NMC27C32s from being programmed.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer-the standby current level, the active current level,
and the transient current peaks that are produced on the
falling and rising edges of chip enable. The magnitude of
these transient current peaks is dependent on the output
capacitance loading of the device. The associated transient
voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that a 0.1 fLF ceramic capacitor be used on every device between Vee and
GND. This should be a high frequency capacitor of low inherent inductance. In addition, a 4.7 fLF bulk electrolytic capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify is accomplished with OElVpp and CE at VIL. Data
should be verified tDV after the falling edge of CE.
ERASURE CHARACTERISTICS
The erasure characteristics of the NMC27C32 are such that
erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It
should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000A-4000A range.
After programming, opaque labels should be placed over
TABLE I. Mode Selection
CE
(18)
OE/Vpp
(20)
Vee
(24)
Outputs
(9-11,13-17)
Read
VIL
VIL
5
DOUT
Standby
VIH
Don't Care
5
Hi-Z
Don't Care
VIH
5
Hi-Z
VIL
Vpp
5
DIN
DOUT
Hi-Z
Pins
Mode
Output Disable
Program
to 60 minutes
for complete erasure to occur.
Program Verify
VIL
VIL
5
Program Inhibit
VIH
Vpp
5
1-18
~National
~
PRELIMINARY
Semiconductor
NMC27C32B 32,768-Bit (4k x 8)
High Speed Version UV Erasable CMOS PROM
General Description
Features
The NMC27C328 is a high-speed 32k UV erasable and
electrically reprogram mabie CMOS EPROM, ideally suited
for applications where fast turnaround, pattern experimentation and low power consumption are important requirements.
The NMC27C328 is designed to operate with a single +5V
power supply with ± 10% tolerance. The CMOS design allows the part to operate over the Extended Temperature
Range.
The NMC27C328 is packaged in a 24-pin dual-in-line package with transparent lid. The transparent lid allows the user
to expose the chip to ultraviolet light to erase the bit pattern.
A new pattern can then be written electrically into the device
by following the programming procedure.
• Clocked sense amps for fast access time down to
150 ns
• Low CMOS power consumption
- Active Power
55 mW Max
0.55 mW Max
- Standby Power
• Optimal EPROM for total CMOS systems
• Single 5V power supply
• Extended temperature range (NMC27C328QE), -40'C
to + 85'C, available
• Pin compatible with NMOS 32k EPROMs
• Fast and reliable prograrnming-100 ".S typical/byte
• Static operation-no clocks required
• TTL, CMOS compatible inputs/outputs
• TRI-STATE® output
• Manufacturer's identification code for automatic programming control
• High current CMOS level output drivers
This EPROM is fabricated with National's proprietary, time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low power consumption and excellent reliability.
Block Diagram
DATA OUTPUTS 00-01
Vee 0---+
GND 0---+
AO·A11
ADDRESS
INPUTS
Pin Names
AO-A11
Addresses
OUTPUT
BUFFERS
CE
Chip Enable
OElVpp
Output Enable/
Programming
Voltage
Y GATING
00-0 7
Outputs
32.78B BIT
CELL MATRIX
TL/O/BB27 -1
1-19
III
N
CO)
~
N
o
:E
z
Connection Diagram
27C256
27256
27C128
27128
27C64
2764
27C16
2716
27C16
2716
Vpp
Vpp
Vpp
A12
A12
A12
A7
A7
A7
A7
A7- 1
A6
A6
A6
A6
A5
A5
A5
A4
A4
A3
A3
A2
NMC27C32B
Dual·ln·Llne Package
\..J
27C64
2764
27C128
27128·
27C256
27256
Vee
Vee
Vee
PGM
PGM
A14
A13
24 -Vee
Vee
NC
A13
A6- 2
23 -A8
AS
AS
AS
AS
A5
A5- 3
22 -A9
A9
A9
A9
A9
A4
A4
A4- 4
21 -A11
Vpp
All
All
All
A3
A3
A3- 5
20 -OE/V pp
OE
OE
OE
OE
A2
A2
A2
A2-6
19 -Al0
Al0
Al0
Al0
Al0
Al
Al
Al
Al
A1- 7
18 -CE
CE
CE
CE
CE
AO
AO
AO
AO
AO- S
00
01
02
00
01
02
00
01
02
00
01
02
00 -
17 -0 7
16 -06
GND
GND
GND
GND
07
06
05
04
03
07
06
05
04
03
07
06
05
04
03
07
06
05
04
03
9
°1- 10
15 -05
O2 - 11
GND- 12
14 -04
13 .... 03
TUD/8827-2
Note: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMC27C32B pins.
Order Number NMC27C32BO
See NS Package Number J24AO
Commercial Temp Range (O°C to + 70'C) Vee = 5V ± 5%
Parameter/Order Number
Access Time (ns)
150
NMC27C32BQ15
Commercial Temp Range (O'C to +70'C) Vee = 5V ±10%
Parameter/Order Number
Access Time (ns)
NMC27C32BQ150
150
NMC27C32BQ200
200
NMC27C32BQ250
250
Extended Temp Range (-40'C to + 85°C) Vee = 5V ± 10%
Parameter/Order Number
Access Time (ns)
NMC27C32BQE200
200
NMC27C32BQE250
250
1·20
COMMERCIAL TEMPERATURE RANGE
i
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-10·Cto +80·C
Temperature Under Bias
Extended Temp Parts
Operating Temp
- 65·C to + 150·C
Storage Temperature
OE Vpp Supply and A9 Voltage with
Respect to Ground
+14.0Vto -0.6V
Power Dissipation
Lead Temperature (Soldering, 10 sec.)
1.0W
300·C
ESD Rating
(Mil Spec 883C, Method 3015.2)
2000V
Vcc Supply Voltage with
Respect to Ground
All Input Voltages except A9
and OElVpp with
Respect to Ground (Note 9)
+7.0Vto -0.6V
Operating Conditions (Note 6)
+6.5Vto -0.6V
Temperature Range
NMC27C32BQ150, 200, 250
NMC27C32BQE200, 250
All Output Voltages with
Respect to Ground (Note 9)
Vcc+1.0Vto GND-0.6V
O·Cto +70·C
-40·Cto +85·C
Vcc Power Supply
except NMC27C32BQ15
+5V ±10%
+5V ±5%
READ OPERATION
DC Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.01
1
/LA
10
/LA
0.01
1
/LA
CE = VIL, f = 1 MHz
Inputs = VIH or VIL, I/O = 0 mA
8
20
rnA
CE = GND,f = 1 MHz
Inputs = Vcc or GND, I/O = 0 mA
3
10
rnA
0.1
1
mA
0.5
100
/LA
-0.2
0.8
V
2.0
Vcc + 1
V
0.45
V
III
Input Load Current
VIN = VCC or GND
Ipp
OElVpp Load Current
OElVpp = VCC or GND
ILO
Output Leakage Current
VOUT = VCC or GND, CE = VIH
ICCl
VCC Current (Active)
TTL Inputs
ICC2
Vcc Current (Active)
CMOS Inputs
ICCSBl
Vcc Current (Standby)
TTL Inputs
ICCSB2
Vcc Current (Standby)
CMOS Inputs
VIL
Input Low Voltage
VIH
Input High Voltage
VOLl
Output Low Voltage
IOL = 2.1 rnA
VOHl
Output High Voltage
IOH = -400/LA
VOL2
Output Low Voltage
IOL = 10 /LA
VOH2
Output High Voltage
IOH = -10/LA
a: = VIH
CE = VCC
2.4
V
0.1
V
V
Vcc - 0.1
AC Electrical Characteristics
NMC27C32B
Symbol
Parameter
Conditions
Q15,Q150
Min
tACC
Address to Output Delay
tCE
CE to Output Delay
tOE
OE to Output Delay
tDF
OE High to Output Float
tCF
CE High to Output Float
toH
Output Hold from Addresses,
CE or OE, Whichever
Occurred First
CE = OE = VIL
Max
Q200,QE200
Min
Max
Q250,QE250
Min
Units
Max
CE = OE = VIL
150
200
250
ns
OE.= VIL
150
200
250
ns
CE = VIL
60
60
70
ns
CE = VIL
0
50
0
60
0
60
ns
OE = VIL
0
50
0
60
0
60
ns
0
1·21
0
0
ns
m
~
~
N
o
:IE
z
Capacitance TA = + 25°C. f =
Symbol
1 MHz (Note 2)
Parameter
Conditions
Typ
Max Units
CINl
Input Capacitance except OElVpp
VIN = OV
6
B
pF
CIN2
OElVpp Input Capacitance
VIN = OV
25
2B
pF
COUT
Output Capacitance
VOUT = OV
9
12
pF
AC Test Conditions
Output Load
1 TTL Gate and
CL = 100 pF (Note B)
Timing Measurement Reference Level
Inputs
Outputs
:5:5 ns
Input Rise and Fall Times
0.BVand2V
0.BVand2V
0.45V to 2.4V
Input Pulse Levels
AC Waveforms (Note 7)
ADDRESSES
-
~:~ )!
2.0V
O.BV
ADDRESSES VALID
\.
"
..
rr
}
j
I-Icr(N0T£S4,5)
I-IcE-
OE/Vpp
2.0V
O.BV
2.0V
OUTPUT
O.SV
"HI-Z
-
tOE
(NOTE 3)
-
J
VALID OUTPUT
tACC _
(NOTE 3)
-
tDr
(N01ES4,5)
IHi-Z
taHITL/O/8827 -3
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage Ie the device. This is a stress reting only and functional
operation of the device at these or any other condHlons above those Indicated In the operational sections of this specification Is not implied. Exposure Ie absolute
maximum rating conditions for extended periods may affect device reliabilHy.
Note 2: This parameter is only sampled and is nolIOO% tested.
Note 3: DE may be delayed up to tACC - toE ailer the falling edge of CE without impacting tACC.
Note 4: The IoF and IcF compare level is determined as follows:
High Ie TRI·STATE,the measured VOH1 (DC) - 0.10V;
Low Ie TRI·STATE,lhe measured VOLl (DC) + O.IOV.
Note 5: TRI-STATE may be attained using DE or CE.
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended thai atleasl a 0.1 "F ceramic capacitor be used on
every device between Vcc and GNO.
Note 7: The outputs musl be restricted Ie Vee + I.OV Ie avoid lalch·up and device damage.
Nota 8: I TTL Gate: 10L = 1.6 rnA, 10H = - 400 "A.
CL: 100 pF includes fixture capaCitance.
Note 9: Inputs and outputs can undershoot to -2.0V for 20 ns Max, except for DElVpp which cannot exceed -0.2V.
1-22
z
s:
o
Programming Characteristics (Notes 1,2, 3 & 4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tAS
Address Setup Time
1
/.l.s
toES
OE Setup Time
1
/.l.s
tos
Data Setup Time
1
/.l.s
tves
Vee Setup Time
1
/.l.s
tAH
Address Hold Time
0
/.l.s
tOH
Data Hold Time
1
teF
Chip Enable to Output Float Delay
tpw
Program Pulse Width
toEH
OEHoldTime
tov
Data Valid from CE
tpRT
OE Pulse Rise Time
During Programming
tVR
Vpp Recovery Time
Ipp
Vpp Supply Current During
Programming Pulse
/.l.s
0
OE = VIL
95
100
60
ns
105
/.l.s
1
ns
250
OE = VIL
ns
50
ns
1
",s
CE = VIL,
OE = Vpp
30
mA
Icc
Vee Supply Current
10
mA
TA
Temperature Ambient
20
25
30
'c
Vee
Power Supply Voltage
6.0
6.25
6.5
V
Vpp
Programming Supply Voltage
12.5
12.75
13.0
tFR
Input Rise, Fall Time
VIL
Input Low Voltage
VIH
Input High Voltage
2.4
4.0
tiN
Input Timing Reference Voltage
0.8
1.5
2.0
V
tOUT
Output Timing Reference Voltage
0.8
1.5
2.0
V
5
V
ns
0.0
0.45
V
V
Programming Waveforms
P~I~ht ______
PROGRAM
O.8Y
~
ADDRESSES
DATA
ADDRESS N
~
2Y
....
-" "~-:1
~
cr
Vee 6.DV
DV
~~8V
toy
~
~
D.\TAOUTY~~
~
~
\
OE PP O.8V
tpRT
2Y
HI-Z
DlTA II SJAElLE
O.SV
~o
~
tOEH
c:
ClvR1
1\
I
f t vcs TLlDI8827-4
Nole 1: NaHonal's standard product warranty applies only to devices programmed to specifications described herein.
Nole 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be Inserted into or removed from a
board with voltage applied to Vpp or Vee.
Nole 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 /LF capacitor is required across Vee to GND to suppress spurious
voltage transients which may damage the device.
Nole 4: Programming and program verify are tested with the fast Program Algorithm, at typical power supply voltages and timings.
1-23
~
Co)
N
UJ
mr-------------------------------------------------------------~--------,
~
Fast Programming Algorithm Flow Chart (Note 4)
(.)
~
z
INCREMENT ADDR
TlID/8827-5
FIGURE 1
1-24
Interactive Programming Algorithm Flow Chart (Note 4)
INCREMENT ADDR
•
TLID/BB27-6
FIGURE 2
1-25
,
Functional Description
DEVICE OPERATION
The six modes of operation of the NMC27C32B are listed in
Table I. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for OElVpp during
programming. In the program mode the OElVpp input is
pulsed from a TTL low level to 12.75V.
Read Mode
The NMC27C32B has two control functions, both of which
must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be
used for device selection. Output Enable (OE) is the output
control and should be used to gate data to the output pins,
independent of device selection. Assuming that addresses
are stable, address access time (tACC) is equal to the delay
from CE to output (tCE). Data is available at the outputs tOE
after the falling edge of OE, assuming that CE has been low
and addresses have been stable for at least tACC-tOE.
The sense amps are clocked for fast access time. Vcc
should therefore the maintained at operating voltage during
read and verify. If Vcc temporarily drops below the spec.
voltage (but not to ground) an address transition must be
performed after the drop to ensure proper output data.
Standby Mode
The NMC27C32B has a standby mode which reduces the
active power dissipation by 99%, from 55 mW to 0.55 mW.
The NMC27C32B is placed in the standby mode by applying
a CMOS high signal to the CE input. When in standby mode,
the outputs are in a high impedance state, independent of
the OE input.
Output OR-Tying
Because EPROMs are usually used in larger memory arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connection.
The 2-line control function allows for:
a. The lowest possible memory power dissipation, and
b. complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended that CE (pin 1B) be decoded and used as the primary device selecting function, while OE (pin 20) be made a
common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low
power standby modes and that the output pins are active
only when data is desired from a particular memory device.
Programming
CAUTION: Exceeding 14V on pin 20 OElVpp will damage
the NMC27C32B.
Initially, and after each erasure, all bits of the NMC27C32B
are in the "1" state. Data is introduced by selectively programming "Os" into the desired bit locations. Although only
"Os" will be programmed, both "1s" and "Os" can be presented in the data word. The only way to change a "0" to a
"1" is by ultraviolet light erasure.
The NMC27C32B is in the programming mode when OEI
Vpp is at 12.75V. It is required that at least a 0.1 ,...F capacitor be placed across VCC and ground to suppress spurious
voltage transients which may damage the device. The data
to be programmed is applied B bits in parallel to the data
output pins. The levels required for the address and data
inputs are TTL.
When the address and data are stable, an active low, TTL
program pulse is applied to the CE input. A program pulse
must be applied at each address location to be programmed. The NMC27C32B is programmed with the Fast
Programming Algorithm shown in Figure 1. Each Address is
programmed with a series of 100 ,...s pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
Program with a Single 100,...s pulse.
Note: Some programmer manufactures due to equipment limitation may offer interactive program AlgOrithm (Shown In Figure 2).
The NMC27C32B must not be programmed with a DC signal
applied to the CE input.
Programming multiple NMC27C32Bs in parallel with the
same data can be easily accomplished due to the Simplicity
of the programming requirements. Like inputs of the paralleled NMC27C32B may be connected together when they
are programmed with the same data. A low level TTL pulse
applied to the CE input programs the paralleled
NMC27C32B.
TABLE I. Mode Selection
Pins
Mode
CE
(18)
OE/Vpp
(20)
Vee
(24)
Outputs
(9-11,13-17)
Read
VIL
VIL
5V
DOUT
Standby
VIH
Don't Care
5V
Hi-Z
Program
VIL
12.75V
6.25V
DIN
DOUT
Program Verify
VIL
VIL
6.25V
. Program Inhibit
VIH
12.75V
6.25V
Hi-Z
Output Disable
Don't Care
VIH
5V
Hi-Z
1-26
Functional Description
(Continued)
Program Inhibit
Programming multiple NMC27C32B in parallel with different
data is also easily accomplished. Except for CE all like inputs (including OE) of the parallel NMC27C32B may be
common. A TTL low level program pulse applied to an
NMC27C32B's CE input with OElVpp at 12.75V will program that NMC27C32B. A TTL high level CE input inhibits
the other NMC27C32B from being programmed.
Program Verify
A verify should be performed on the programmed bit to determine whether they were correctly programmed. The verify is accomplished with OElVpp and CE at VIL. Data should
be verified tov after the falling edge of CE.
MANUFACTURER'S IDENTIFICATION CODE
The NMC27C32B has a manufacturer's identification code
to aide in programming. The code, shown in Table II, is two
bytes wide and is stored in a ROM configuration on the chip.
It identifies the manufacturer and the device type. The code
for the NMC27C32B is, "BF01", where "BF" designates that
it is made by National Semiconductor, and "01" designates
a 32k part.
The code is accessed by applying 12.0V ± 0.5V to address
pin A9. Addresses A1-AB, A10-A11 , CE, and OE are held
at VIL. Address AO is held at VIL for the manufacturer's
code, and at VIH for the device code. The code is read out
on the B data pins. Proper code access is only guaranteed
at 25'C ± 5'C.
The primary purpose of the manufacturer's identification
code is automatic programming control. When the device is
inserted in an EPROM programmer socket, the programmer
reads the code and then automatically calls up the specific
programming algorithm for the part. This automatic programming control is only possible with programmers which
have the capability of reading the code.
ERASURE CHARACTERISTICS
The erasure characteristics of the NMC27C32B are such
that erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000A-4000A
range. After programming, opaque labels should be placed
over the NMC27C32B's window to prevent unintentional
erasure. Covering the window will also prevent temporary
functional failure due to the generation of photo currents.
The recommended erasure procedure for the NMC27C32B
is exposure to short wave ultraviolet light which has a wavelength of 2537A. The integrated dose (i.e., UV intensity X
exposure time) for erasure should be a minimum of
15 W-sec/cm2.
The NMC27C32B should be placed within 1 inch of the
lamp tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. Table III
shows the minimum NMC27C32B erasure time for various
light intensities.
An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one inch.
The erasure time increases as the square of the distance. (If
distance is doubled the erasure time increases by a factor of
4.) Lamps lose intensity as they age. When a lamp is
changed, the distance has changed or the lamp has aged,
the system should be checked to make certain full erasure
is occurring. Incomplete erasure will cause symptoms that
can be misleading. Programmers, components, and even
system designs have been erroneously suspected when incomplete erasure was the problem.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer-the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 ",F ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 ",F bulk electrolytic
capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
TABLE II. Manufacturer's Identification Code
Pins
AO
(8)
Manufacturer Code
Device Code
o
06
05
03
00
(16)
(15)
(13)
(9)
o
o
o
o
o
o
BF
o
TABLE III. Minimum NMC27C32B Erasure Time
Light Intensity
(",W/cm 2)
Erasure Time
(Minutes)
15,000
20
10,000
25
5,000
50
1-27
Hex
Data
o
o
01
~ r---------------------------------------------------------------------------~
co
o......
C'I
o
::!il
z
~NaHonal
~
Semiconductor
NMC27C64 65,536-Bit (Sk x 8) UV Erasable CMOS PROM
General Description
Features
The NMC27C64 is a high-speed 64k UV erasable and electrically reprogram mabie CMOS EPROM, ideally suited for
applications where fast turnaround, pattern experimentation
and low power consumption are important requirements.
The NMC27C64 is designed to operate with a single + 5V
power supply with ± 5% or ± 10% tolerance. The CMOS
design allows the part to operate over extended and military
temperature ranges.
II
The NMC27C64 is packaged in a 28-pin dual-in-line package with transparent lid. The transparent lid allows the user
to expose the chip to ultraviolet light to erase the bit pattern.
A new pattern can then be written electrically into the device
by following the programming procedure.
This EPROM is fabricated with National's proprietary, time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low power consumption and excellent reliability.
II
II
II
II
II
II
II
II
II
II
III
Clocked sense amps for fast access time down to
150 ns
Low CMOS power consumption
- Active Power: 55 mW max
- Standby Power: 0.55 mW max
Performance compatible to NSC800™ CMOS microprocessor
Single 5V power supply
Extended temperature range (NMC27C640E), -40'C
to
+ 85'C, and military temperature range
(NMC27C640M), - 55'C to + 125'C, available
Pin compatible with NMOS 64k EPROMs
Fast and reliable programming
Static operation-no clocks required
TIL, CMOS compatible inputs/outputs
TRI-STATE® output
Optimum EPROM for total CMOS systems
Manufacturer's identification code for automatic programming control
Block Diagram
DATA DUTPUTS DD-D7
Vee 0---+GND 0---+-
Pin Names
OUTPUT
BUFFERS
Y GATING
AO-A12
ADDRESS
INPUTS
65.S36·BIT
CElL MATRIX
TLlD/8S34-1
1-28
AO-AI2
Addresses
CE
Chip Enable
OE
Output Enable
0 0- 0 7
Outputs
PGM
Program
NC
No Connect
Connection Diagram
~7C512 27C256 27C12E 27C32 27C1E
27C16
NMC27C64Q
Dual·ln·Llne Package
27512 27256 27128 2732 2716
2716
27C32 27C128 27C256 27C512
2732
27128
27256
27512
A15
Vpp
Vpp
Vpp- 1
281- Vee
Vee
Vee
Vee
A12
A12
A12
A12- 2
27
I- PGM
PGM
A14
A14
A7
A7
A7
A7
A7
A7- 3
261- NC
Vee
Vee
A1S
A1S
A1S
A6
A6
A6
A6
A6
A6- 4
25 I- A8
AS
AS
AS
AS
AS
A5
A5
A5
A5
A5
A5- 5
24
I- A9
A9
A9
A9
A9
A9
A4
A4
A4
A4
A4
A4- 6
23 I- All
Vpp
All
All
All
All
AS
AS
AS
AS
AS
A3- 7
22
OElVpp
OE
OE
OEIVPF
A2
A2
A2
A2
A2- 8
21
Al0
A10
Al0
Al0
Al0
Al
Al
Al
Al
Al
Al- 9
I- DE
I- Al0
20 I- CE
OE
A2
p-E/PGM
CE
CE
CE/PGM
CE
AO
AO
AO
AO
AO
AO- 10
19
~07
07
07
07
07
07
00
00
00
00
00
00- 11
181-0&
06
06
06
06
06
01
01
01
01
01
01- 12
171- 05
Os
Os
Os
Os
Os
02
02
02
02
02
02- 13
161-04
04
04
04
04
04
GNO- 14
15 I- 03
Os
Os
Os
Os
OS
GND
GND
GND
GND GND
TL/D/8634-2
Nate: Socket compatible EPROM pin configurations are shawn in the blacks adlacent to the NMC27C64 pins.
Order Number NMC27C64Q
See NS Package Number J28AQ
Commercial Temp Range (O'C to
Vee = 5V ±5%
+ 70'C)
Access Time (ns)
Parameter/Order Number
NMC27C64Q15
150
Vee = 5V ±10%
Parameter/Order Number
Access Time (ns)
NMC27C64Q150
NMC27C64Q200
NMC27C64Q250
NMC27C64QSOO
150
200
250
SOO
Extended Temp Range (- 40'C to
Vee = 5V ±10%
Parameter/Order Number
+ 85'C)
Access Time (ns)
150
200
NMC27C64QE150
NMC27C64QE200
Military Temp Range (-55'C to
Vee = 5V ±10%
Parameter/Order Number
+ l25'C)
Access Time (ns)
NMC27C64QM200
NMC27C64QM250
200
250
NOTE: For plastic DIP requirements please refer to NMC27C64N data sheet
1·29
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature Under Bias
-10·Cto +80·C
Commercial
Military and Extended
Operating Temp. Range
Storage Temperature
-65·Cto + 150·C
All Input Voltages except A9 with
Respect to Ground (Note 10)
+6.5Vto -0.6V
All Output Voltages with
Respect to Ground (Note 10) Vee+ 1.0V to GND-0.6V
Vpp Supply Voltage and A9
with Respect to Ground
During Programming
+ 14.0Vto -0.6V
Vcc Supply Voltage with
Respect to Ground
+7.0Vto -0.6V
Power Dissipation
Lead Temperature (Soldering, 10 sec.)
300"C
1.0W
ESD Rating
(Mil Spec 883C, Method 3015.2)
2000V
Operating Conditions (Note 7)
Temperature Range
NMC27C64015, 0150, 200, 250
NMC27C640E150, 200
NMC27C640M200, M250
O·Cto +70·C
-40"Cto +85·C
-55·Cto + 125·C.
+5V ±10%
+5V ±5%
Vce Power Supply
except NMC27C64015
READ OPERATION
DC Electrical Characteristics
Symbol
Parameter
Conditions
=
Min
Typ
Max
Units
10
p.A
10
p.A
III
Input Load Current
ILO
Output Leakage Current
VOUT = VCC or GND, CE
ICC1
(Note 9)
VCC Current (Active)
TTL Inputs
CE = VIL, f = 5 MHz
Inputs = VIH or VIL, 1/0 = 0 rnA
5
20
mA
ICC2
(Note 9)
Vcc Current (Active)
CMOS Inputs
CE = GND, f = 5 MHz
Inputs = Vee or GND, 1/0
3
10
rnA
ICCSB1
VCC Current (Standby)
TTL Inputs
CE = VIH
0.1
1
mA
leeSB2
VCC Current (Standby)
CMOS Inputs
CE
0.5
100
",A
Vpp = Vcc
VIN
=
VCC or GND
=
VIH
=
0 rnA
Vee
Ipp
Vpp Load Current
10
p.A
VIL
Input Low Voltage
-0.1
0.8
V
VIH
Input High Voltage
2.0
Vee + 1
V
VOL1
Output Low Voltage
IOL
0.45
V
VOH1
Output High Voltage
IOH = -400 ",A
VOL2
Output Low Voltage
IOL=O",A
VOH2
Output High Voltage
IOH =
=
2.1 rnA
2.4
V
V
0.1
o ",A
Vee - 0.1
V
AC Electrical Characteristics
NMC27C64Q
Symbol
Parameter
Conditions
15,150, E150
Min
tAee
Address to Output Delay
CE = OE = VIL
PGM = VIH
icE
CE to Output Delay
OE
tOE
OE to Output Delay
CE = VIL, PGM = VIH
tOF
OE High to Output Float
CE
tCF
CE High to Output Float
OE = VIL, PGM
toH
Output Hold from Addresses, CE = OE = VIL
CE or OE, Whichever
PGM = VIH
Occurred First
=
=
VIL, PGM = VIH
VIL, PGM = VIH
=
VIH
Max
200, E200, M200
Min
Max
250,M250
Min
Units
Max
150
200
250
ns
150
200
250
ns
60
60
70
ns
0
60
0
60
0
60
ns
0
60
0
60
0
60
ns
0
1·30
0
0
ns
Capacitance TA = + 25°C, f =
Symbol
Parameter
z
s:::
oN
1 MHz (Note 2)
Conditions
Typ
......
Max
Units
o
Q)
0l:Io
CIN
Input Capacitance
VIN = OV
6
8
pF
COUT
Output Capacitance
VOUT = OV
9
12
pF
AC Test Conditions
Output Load
Timing Measurement Reference Level
Inputs
Outputs
1 TTL Gate and
CL = 100 pF (Note 8)
";5 ns
Input Rise and Fall Times
Input Pulse Levels
0.8Vand2V
0.8Vand2V
0.45V to 2.4V
AC Waveforms (Notes 6 &9)
ADDRESSES VALID
ADDRESSES
cr
OE
2.0V
O.BV
2.0V
O.BV
Hi-Z
2 OV
OUTPUT *·*-+-----1:~~tftf<1
O.BV
~:..lo.l~~+-
Hi-Z
VALID OUTPUT "'" ...____
_______
+--+~"'_'I
1--_ _ _ tAcc - - - . - J
(NOTE 3)
TL/0/8634-3
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: DE may be delayed up to tACC - toE after the falling edge of CE without impacting tACC.
Note 4: The tDF and tcF compare level is determined as follows:
High to TRI-STATE, the measured VOH' (DC) - 0.10V;
Low to TRI-STATE, the measured VOll (DC) + 0.10V.
Note 5: TRI·STATE may be attained using DE or
CE.
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 ""F ceramic capacitor be used on
every device between Vee and GND.
Note 7: The outputs must be restricted to Vcc
+
1.0V to avoid latch-up and device damage.
Note 8: 1 TTL Gate: IOL ~ 1.6 mA, IOH ~ -400 I"A.
CL: 100 pF includes fixture capacitance.
•
Note 9: Vpp may be connected to Vce except during programming.
Note 10: Inputs and outputs can undershoot to - 2.0V for 20 ns Max.
1-31
Programming Characteristics (Notes 1,2,3 & 4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tAS
Address Setup Time
2
!,-S
toES
OE Setup Time
2
!,-S
teES
CE Setup Time
2
!,-S
tos
Data Setup Time
2
!,-S
tvps
Vpp Setup Time
2
!,-S
tvcs
Vee Setup Time
2
!,-S
tAH
Address Hold Time
0
!,-S
tOH
Data Hold Time
tOF
Output Enable to Output Float Delay
2
CE
=
VIL
tpw
Program Pulse Width
toE
Data Valid from OE
CE
0.45
Ipp
Vpp Supply Current During
Programming Pulse
VIL
CE
PGM = VIL
=
=
!,-S
0
0.5
VIL
130
ns
0.55
ms
150
ns
30
mA
lee
Vee Supply Current
10
mA
TA
Temperature Ambient
20
25
30
'C
Vee
Power Supply Voltage
5.75
6.0
6.25
V
Vpp
Programming Supply Voltage
12.2
13.0
13.3
tFR
Input Rise, Fall Time
VIL
Input Low Voltage
VIH
Input High Voltage
2.4
4.0
tiN
Input Timing Reference Voltage
0.8
1.5
2.0
V
toUT
Output Timing Reference Voltage
0.8
1.5
2.0
V
0.0
1·32
V
ns
5
0.45
V
V
.-----------------------------------------------------------------------,z
i:
Programming Waveforms (Note 3)
~
..
g
ADDRESSES
DATA
TL/D/8634-6
Not. I: National's standard product warranty applies to devices programmed to specifications described herein.
Note 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vcr;.
Note 3: The maximum absoluta allowable voltage which may be applied to the Vpp pin during programming is 14V. care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum spec~lcation. At least a 0.1 p.F capacitor Is required across Vpp, Vee to GND to suppress
spurious voltage transients which may damage the device.
Not. 4: Programming and program verify are tasted with the interactive Program Algorithm, at typical power supply voltages and timings.
1-33
~
Interactive Programming Algorithm Flow Chart
N
(,)
~
z
INCREMENT ADDR
TLlD/8634-5
1-34
Functional Description
DEVICE OPERATION
The six modes of operation of the NMC27C64 are listed in
Table I. It should be noted that all inputs for the six modes
are at TTL levels. The power supplies required are Vee and
Vpp. The Vpp power supply must be at 13.0V during the
three programming modes, and must be at 5V in the other
three modes. The Vee power supply must be at 6V during
the three programming modes, and at 5V in the other three
modes.
Read Mode
The NMC27C64 has two control functions, both of which
must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be
used for device selection. Output Enable (OE) is the output
control and should be used to gate data to the output pins,
independent of device selection. The programming pin
(PGM) should be at VIH except during programming. Assuming that addresses are stable, address access time (tAeel is
equal to the delay from CE to output (teE)' Data is available
at the outputs tOE after the falling edge of OE, assuming
that CE has been low and addresses have been stable for
at least tAce-toE'
The sense amps are clocked for fast access time. Vee
should therefore be maintained at operating voltage during
read and verify. If Vee temporarily drops below the spec.
voltage (but not to ground) an address transition must be
performed after the drop to insure proper output data.
Standby Mode
The NMC27C64 has a standby mode which reduces the
active power dissipation by 99%, from 55 mW to 0.55 mW.
The NMC27C64 is placed in the standby mode by applying
a CMOS high Signal to the CE input. When in standby mode,
the outputs are in a high impedance state, independent of
the OE input.
Output OR-Tying
Because NMC27C64s are usually used in larger memory
arrays, National has provided a 2-Iine control function that
accommodates this use of multiple memory connections.
The 2-Iine control function allows for:
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended that CE (pin 20) be decoded and used as the primary device selecting function, while OE (pin 22) be made a
common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low
power standby modes and that the output pins are active
only when data is desired from a particular memory device.
Programming
CAUTION: Exceeding 14V on pin 1 (Vpp) will damage the
NMC27C64.
Initially, all bits of the NMC27C64 are in the "1" state. Data
is introduced by selectively programming "Os" into the desired bit locations. Although only "Os" will be programmed,
both "1 s" and "Os" can be presented in the data word. A
"0" cannot be changed to a "1" once the bit has been
programmed.
The NMC27C64 is in the programming mode when the Vpp
power supply is at 13.0V and OE is at VIH. It is required that
at least a 0.1 p.F capaCitor be placed across Vpp, Vee to
ground to suppress spurious voltage transients which may
damage the device. The data to be programmed is applied 8
bits in parallel to the data output pins. The levels required
for the address and data inputs are TTL.
For programming, CE should be kept TTL low at all times
while Vpp is kept at 13.0V.
When the address and data are stable, an active low, TTL
program pulse is applied to the PGM input. A program pulse
must be applied at each address location to be programmed. The NMC27C64 is designed to be programmed
with interactive programming, where each address is programmed with a series of 0.5 ms pulses until it verifies (up to
a maximum of 20 pulses or 10 ms). The NMC27C64 must
not be programmed with a DC signal applied to the PGM
input.
Programming multiple NMC27C64s in parallel with the same
data can be easily accomplished due to the simplicity of the
programming requirements. Like inputs of the paralleled
NMC27C64s may be connected together when they are
programmed with the same data. A low level TTL pulse applied to the PGM input programs the paralleled
NMC27C64s.
TABLE I. Mode Selection
Pins
Outputs
Mode
CE
(20)
OE
(22)
PGM
(27)
Vpp
(1)
Vee
(28)
(11-13,15-19)
Read
VIL
VIL
VIH
5V
5V
DOUT
Standby
VIH
Don't Care
Don't Care
5V
5V
Hi-Z
VIH
Hi-Z
Output Disable
Don't Care
VIH
Program
VIL
VIH
Program Verify
VIL
VIL
Program Inhibit
VIH
Don't Care
5V
5V
13V
6V
DIN
VIH
13V
6V
DOUT
Don't Care
13V
6V
Hi-Z
1-35
~
CD
(J
"'"
N
(J
:::E
z
r----------------------------------------------------------------------------,
Functional Description (Continued)
The recommended erasure procedure for the NMC27C64 is
Ejlxposure to short wave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV
intensity x exposure time) for erasure should be a minimum
of 15W·sec/cm2.
Program Inhibit
Programming multiple NMC27C64s in parallel with different
data is also easily accomplished. Except for CE all like inputs (including OE and PGM) of the parallel NMC27C64
may be common. A TTL low level program pulse applied to
an NMC27C64's PGM Input with CE at VIL and Vpp at 13.0V
will program that NMC27C64. A TTL high level CE input
inhibits the other NMC27C64s from being programmed.
The NMC27C64 should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. Table III
shows the minimum NMC27C64 erasure time for various
light intensities.
An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one inch.
The erasure time increases as the square of the distance. (If
distance is doubled the erasure time increases by a factor of
4.) Lamps lose intensity as they age. When a lamp is
changed, the distance has changed or the lamp has aged,
the system should be checked to make certain full erasure
is occurring. Incorriplete erasure will cause symptoms that
can be misleading. Programmers, components, and even
system deSigns have been erroneously suspected when incomplete erasure was the problem.
Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with Vpp at 13.0V. Vpp must be at
Vee, except during programming and program verify. '
MANUFACTURER'S IDENTIFICATION CODE
The NMC27C64 has a manufacturer's identification code to
aid in programming. The code, shown in Table II, is two
bytes wide and is stored in a ROM configuration on the chip.
It identifies the manufacturer and the device type. The code
for the NMC27C64 is "8FC2", where "8F" designates that it
is made by National Semiconductor, and "C2" designates a
64k part.
SYSTEM CONSIDERATION
The code is accessed by applying 12V ± 0.5V to address
pin A9. Addresses A 1-A8, Al O-A 12, CE, and OE are held
at VIL. Address AO is held at VIL for the manufacturer's
code, and at VIH for the device code. The code is read out
on the 8 data pins. Proper code access is only guaranteed
at 25'C ± 5'C.
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer-the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 fLF ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 fLF bulk electrolytic
capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
The primary purpose of the manufacturer's identification
code is automatic programming control. When the device is
inserted in a EPROM programmer socket, the programmer
reads the code and then automatically calls up the specific
programming algorithm for the part. This automatic programming control is only possible with programmers which
have the capability of reading the code.
ERASURE CHARACTERISTICS
The erasure characteristics of the NMC27C64 are such that
erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It
should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000A-4000A range.
After programming, opaque labels should be placed over
the NMC27C64's window to prevent unintentional erasure.
Covering the window will also prevent temporary functional
failure due to the generation of photo currents.
TABLE II. Manufacturer's Identification Code
Pins
Ao
(10)
07
(19)
Os
(18)
Manufacturer Code
VIL
1
a
VIH
1
1
Device Code
04
03
02
01
(16)
(15)
(13)
(12)
a
a
a
a
1
1
1
1
8F
a
a
1
a
C2
TABLE III. Minimum NMC27C64 Erasure Time
Light Intensity
(Mlcro-Watts/cm 2)
Erasure Time
(Minutes)
15,000
20
10,000
25
5,000
50
1-36
00
(11)
Hex
Data
05
(17)
r-------------------------------------------------------------------,z
s::
o
~l
Natilonal
~ Semuconductor
~MC27C64M
~.co.
Z
65,536-Bit (8k x 8)
One..l'ime Programmable CMOS PROM
Gsnsral Description
Features
The NMC27C64N is a high-speed 64k one-time programmable CMOS PROM. It is ideally suited for high volume production applications where low cost, fast turnaround, and low
power consumption are important factors and reprogramming is not required.
The NMC27C64N Is designed to operate with a single + 5V
power supply with ± 10% tolerance. The NMC27C64N is
packaged in a 2B-pin dual-in-line plastic molded package
without a transparent lid. This part is ideally suited for high
volume production applications where cost is an important
factor and programming only needs to be done once. Also
the plastic molded package works well in auto insertion
equipment used in automated assembly lines.
• Clocked sense amps for fast access time down to
150 ns, CMOS technology
• Low CMOS power consumption
- Active Power: 55 mW max
- Standby Power: 0.55 mW max
• Pin compatible with all 64k EPROMs
• Fast and reliable programming
• Static operation-no clocks required
• TTL, CMOS compatible inputs/outputs
• TRI-STATE@ output
• Optimum PROM for total CMOS systems
• Manufacture's identification code for automatic programming control
This device is fabricated with National's proprietary, time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low power consumption and excellent reliability.
Block Diagram
,
Vee 0---+
GND 0---+
Vpp
PGM ---.
CE--I>
:::
---.
OUTPUT ENABLE
AND CHIP
ENABLE LOGIC
y
DECODER
-+
AD-A12
ADDRESS
INPUTS
:::
::::
:::
::::
\
tttttttt
0---+
ilE---.
DATA OUTPUTS 00-11]
x
DECODER
j--.
j--.
f-t
•
·
r--+
f-;-+
·•
·
f--!-+
OUTPUT
BUFFERS
Pin Names
Y GATING
65.536·BIT
CELL MATRIX
TL/O/96B6-1
1-37
AO-A12
Addresses
CE
Chip Enable
OE
Output Enable
0 0- 0 7
Outputs
PGM
Program
NC
No Connect
III
z
~
Connection Diagram
C'\I
o
:::E
z
~7C512 27C25E 27C128 27C32 27C1E
27C16
NMC27C64N
Dual·ln·Llne Package
27512 27256 27128 2732 2716
2716
27C32 27C12e 27C256 27C512
2732
27128
27256
27512
Vee
A15
Vpp
Vpp
Vpp -
1
28 -
Vee
Vee
Vee
A12
A12
A12
A12 -
2
27 -
PllM
PGM
A14
A14
A7
A7
A7
A7
A7
A7- 3
26 -Ne
A6
A6
A6
A6
A6
A6- 4
25 -
A5
A5
A5
A5
A5
A5-5
24 -
A4
A4
A4
A4
A4
A4-6
23 -
A3
A3
A3
A3
A3
A3- 7
22
A2
A2
A2
A2
A2
A2- 8
21 -AID
Al
Al
Al
Al
A1
Al- 9
20 -Ci!
CE/PGM
AO
AO
AO
AO
AO
AD- 10
19 - 0 ,
07
07
07
07
07
00
00
00
00
00
00- 11
18 -0&
Os
Os
Os
Os
Os
01
02
01
02
01
02
01
01
02
01- 12
17 - 0 ,
02- 13
16 - 0 ,
05
04
05
04
05
04
05
04
05
04
GND
GND
GND
GND- 14
15 -03
03
03
03
03
03
02
GND GND
Vee
Vee
A13
A13
A13
A8
A8
A8
A8
A8
A8
A9
A9
A9
A9
A9
A9
A11
Vpp
All
All
All
All
OE
OElVpp
DE
OE
DElVpp
A10
Al0
A10
A10
Al0
CE
CE
CE/PGM
CE
-DE
TL/D/9686-2
Note: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMC27C64N pins.
Order Number NMC27C64N
See NS Package Number N28B
Commercial Temp Range (O'C to
+ 70'C)
Vee = 5V ±10%
Parameter/Order Number
Access Time (ns)
NMC27C64N150
150
NMC27C64N200
200
NMC27C64N250
250
(For Non Commercial Temp. Range Part.. call Factory)
1-38
z
3:
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature Under Bias
-10'Cto +80'C
(")
Vec Supply Voltage with
Respect to Ground
Power Dissipation
Lead Temperature (Soldering, 10 sec.)
Storage Temperature
-65'Cto +150'C
All Input Voltages except A9 with
Respect to Ground (Note 10)
+6.5Vto -0.6V
All Output Voltages with
Respect to Ground (Note 10) Vee + 1.0V to GND-0.6V
Vpp Supply Voltage and A9
with Respect to Ground
During Programming
+14.0Vto -0.6V
+7.0Vto -0.6V
1.0W
300'C
ESD Rating
(Mil Spec 883C, Method 3015.2)
N
.....
(")
Q)
,j:oo
Z
2000V
Operating Conditions (Note 7)
Temperature Range
O'Cto +70'C
Vec Power Supply
NMC27C64N150, 200, 250
+5V ±10%
READ OPERATION
DC Electrical Characteristics
Symbol
Parameter
Conditions
=
Input Load Current
ILO
Output Leakage Current
VOUT
lec1
(Note 9)
Vce Current (Active)
TIL Inputs
CE = VIL, f = 5 MHz
Inputs = VIH or VIL, 1/0
lec2
(Note 9)
Vee Current (Active)
CMOS Inputs
CE = GND, f = 5 MHz
Inputs = Vee or GND, I/O
leCSB1
Vce Current (Standby)
TIL Inputs
CE
=
VIH
leeSB2
Vee Current (Standby)
CMOS Inputs
CE
=
Vcc
Vpp
VIN
=
Typ
Min
III
Max
Units
10
p.A
10
p.A
6
20
mA
3
10
mA
0.1
1
mA
0.5
100
p.A
10
p.A
Vcc or GND
=
Vee or GND, CE
=
=
VIH
0 mA
=
0 mA
Ipp
Vpp Load Current
VIL
Input Low Voltage
-0.1
0.8
V
VIH
Input High Voltage
2.0
Vce + 1
V
VOll
Output Low Voltage
IOL
VOH1
Output High Voltage
IOH
VOL2
Output Low Voltage
VOH2
Output High Voltage
Vee
= 2.1 mA
= -400mA
IOL = 0 p.A
IOH = 0 p.A
0.45
V
V
2.4
V
0.1
V
Vec - 0.1
AC Electrical Characteristics
NMC27C64N
Symbol
Parameter
Conditions
Min
tAee
Address to Output Delay
CE = OE = VIL
PGM = VIH
teE
CE to Output Delay
toE
OE to Output Delay
tDF
OE High to Output Float
teF
CE High to Output Float
toH
Output Hold from Addresses,
CE or DE, Whichever
Occurred First
200
150
Max
Min
Units
250
Max
Min
Max
150
200
250
ns
OE
150
200
250
ns
CE
60
60
70
ns
= VIL, PGM = VIH
= VIL, PGM = VIH
CE = VIL, PGM = VIH
OE = VIL, PGM = VIH
CE = OE = VIL
PGM = VIH
1-39
0
60
0
60
0
60
ns
0
60
0
60
0
60
ns
0
0
0
ns
•
I
z
~
Capacitance T A = + 25°C, f =
1
MHz (Note 2)
N
o
Symbol
Typ
Max
Units
:::E
z
CIN
Input Capacitance
VIN = OV
5
10
pF
COUT
Output Capacitance
VOUT = OV
8
10
pF
Parameter
Conditions
AC Test Conditions
Output Load
1 TTL Gate and
CL = 100 pF (Note 8)
Timing Measurement Reference Level
Inputs
Outputs
";5ns
Input Rise and Fall Times
Input Pulse Levels
0.8V and 2V
0.8Vand2V
0.45V to 2.4V
AC Waveforms
(Notes
ADDRESSES
6, 7 & 9)
--
~~8V)l
ADDRESSES VALID
2V
O.BV
\.
.
).
.
j
_tcr-
!.--tCE_
OUTPUT
2V
O.BV
N01ES4.5
'-
2V
O.BV
HI-Z
J
tOE
(NOTE 3)
IVALID OUTPUT
_ , t ACC , _
(NOTE 3)
-
tDf"
N01ES4.5
IHI-Z
-tOHITl/D/9686-3
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. this Is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposura to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3:
m: may be delayed up to tACC -
toE aiter the failing edge of CE without impacting tAce.
Note 4: The tOF and tcF compare level is determined as follows:
High to TRI-STATE, the measured VOHI (DC) - 0.10V;
Low to TRI-STATE, the measured VOll (DC) + 0.10V.
Note 5: TRI-STATE may be aHained using DE or GE.
Note 6: The power switching characteristics of EPROMs require careful device decoupllng. It Is recommended that at least a 0.1 ,..F ceramic capacitor be used on
every device between Vce and GND.
Note 7: The outputs must be restricted to Vce
+
1.0V 10 avoid latch-up and device damage.
Note 8: 1 TTL Gale: IOl ~ 1.6 mA. IOH ~ -400 p.A.
Cl: 100 pF includes fixture capacitance.
Nola 9: Vpp may be connected 10 Vcc except during programming.
Nole 10: Inpuls and outputs can undershool to -0.2V for 20 ns Max.
1-40
Programming Characteristics (Notes 1, 2, 3 & 4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tAS
Address Setup Time
2
/Ls
toES
OE Setup Time
2
/Ls
teES
CE Setup Time
2
/Ls
tos
Data Setup Time
2
/Ls
tvps
Vpp Setup Time
2
/Ls
tvcs
Vee Setup Time
2
/Ls
tAH
Address Hold Time
0
/Ls
tOH
Data Hold Time
2
tOF
Output Enable to Output Float Delay
tpw
Program Pulse Width
CE = VIL
/Ls
0
0.45
0.5
130
ns
0.55
ms
toE
Data Valid from OE
CE = VIL
150
ns
Ipp
Vpp Supply Current During
Programming Pulse
CE = VIL
PGM = VIL
30
mA
lee
Vee Supply Current
10
mA
TA
Temperature Ambient
20
25
30
·C
Vee
Power Supply Voltage
5.75
6.0
6.25
V
Vpp
Programming Supply Voltage
12.2
13.0
13.3
V
tFR
Input Rise, Fall Time
VIL
Input Low Voltage
VIH
Input High Voltage
2.4
4.0
tiN
Input Timing Reference Voltage
0.8
1.5
2.0
V
toUT
Output Timing Reference Voltage
0.8
1.5
2.0
V
5
ns
0.0
0.45
V
V
Note 1: National's standard product warranty applies to devices programmed to specifications described herein.
Note 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or VeeNote 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least 0.1 JLF capacitor is required across Vpp, Vee to GND to suppress
spurious voltage transients which may damage the device,
Note 4:
Programming and program verify are tested with the Interactive Program Algorithm, at typical power supply voltages and timings.
1-41
..
z
CD
~
Prog'ramming Waveforms (Note 3)
::E
z
OE
llv
TU0/96B6-4
1-42
r--------------------------------------------------------------------------,
Interactive Programming Algorithm Flow Chart
Z
3:
o
......
oen
N
01:>0
Z
INCREMENT ADDR
TL/D/9686-5
1-43
z
~
C'II
'0
:2
z
Functional Description
DEVICE OPERATION
The six modes of operation of the NMC27C64N are listed in
Table I. It should be noted that all iniputs for the six modes
are at TTL levels. The power supplies required are Vee and
Vpp. The Vpp power supply must be at 13.0V during the
three programming modes, and must be at 5V in the other
three modes. The Vee power supply must be at 6V during
the three programming modes, and at 5V In the other three
modes.
Read Mode
The NMC27C64N has two control functions, both of which
must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be
used for device selection. Output Enable (OE) is the output
control and should be used to gate data to the output pins,
independent of device selection. The programming pin
(PGM) should be at VIH except during programming. Assuming that addresses are stable, address access time (tAeel is
equal to the delay from CE to output (teE), Data is available
at the outputs tOE after the falling edge of OE, assuming
that CE has been low and addresses have been stable for
at least tAee-tOE'
The sense amps are clocked for fast access time. Vee
should therefore be maintained at operating voltage during
read and verify. If Vee temporarily drops below the spec.
voltage (but not to ground) an address transition must be
performed after the drop to insure proper output data.
Standby Mode
The NMC27C64N has a standby mode which reduces the
active power dissipation by 99%, from 55 mW to 0.55 mW.
The NMC27C64N is placed in the standby mode by applying
a CMOS high signal to the CE input. When in standby mode,
the outputs are in a high impedance state, independent of
the OE input.
Output OR-Tying
Because NMC27C64Ns are usually used in larger memory
arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
sures that all deselected memory devices are in their low
power standby modes and that the output pins are active
only when data is desired from a particular memory device.
Programming
.CAUTION: Exceeding 14V on pin 1 (Vpp) will damage the
NMC27C64N.
Initially, all bits of the NMC27C64N are in the "1" state.
Data is introduced by selectively programming "Os" Into the
desired bit locations. Although only "Os" will be programmed, both "1s" and "Os" can be presented In the data
word. A "0" cannot be changed to a "1" once the bit has
been programmed. Due to package constraints programmability of the device is only tested In wafer form.
The NMC27C64N is in the programming mode when the
Vpp power supply is at 13.0V and OE Is at VIH. It Is required
that at least a 0.1 ,...F capacitor be placed across Vpp, Vee
to ground to suppress spurious voltage transients which
may damage the device. The data to be programmed is
applied 6 bits in parallel to the data outputs pins. The levels
required for the address and data inputs are TTL.
For programming, CE should be kept TTL low at all times
while Vpp is kept at 13.0V.
When the address and data are stable, an active low, TTL
program pulse is applied to the PGM input. A program pulse
must be applied at each address location to be programmed. The NMC27C64N is designed to be programmed
with interactive programming, where each address is programmed with a series of 0.5 ms pulses until it verifies (up to
a maximum of 20 pulses or 10 ms). The NMC27C64N must
not be programmed with a DC signal applied to the PGM
input.
Programming multiple NMC27C64Ns in parallel with the
same data can be easily accomplished due to the Simplicity
of the programming requirements. Like inputs of the paralleled NMC27C64Ns may be connected together when they
are programmed with the same data. A low level TTL pulse
applied to the PGM input programs the paralleled
NMC27C64Ns.
The NMC27C64N is packaged in a plastic molded package
which does not have a transparent lid. Therefore the memory cannot be erased. This means that after a user has programmed a memory cell to a "0" it cannot be changed back
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended that CE (pin 20) be decoded and used as the primary device selecting function, while OE (pin 22) be made a
common connection to all devices in the array and connected to the READ line from the system control bus. This as-
to a 111"0
If an application requires erasing and reprogramming, the
NMC27C64Q UV erasable PROM in a windowed package
should be used.
TABLE I. Mode Select
Pins
Mode
CE
(20)
OE
(22)
Read
VIL
VIL
Don't
Care
Standby
VIH
PGM
(27)
Vpp
(1)
Vee
(28)
Outputs
(11-13,15-19)
VIH
Don't
Care
5V
5V
DOUT
5V
5V
Hi-Z
6V
DIN
Program
VIL
VIH
VIL
13.0V
Program Verify
VIL
VIH
Don't
Care
13.0V
6V
DOUT
VIH
VIL
Don't
Care
13.0V
6V
Hi-Z
Don't
Care
VIH
VIH
5V
5V
HI-Z
Program Inhibit
Output Disable
1-44
z
Functional Description
:s::
(Continued)
The primary purpose of the manufacturer's identification
code is automatic programming control. When the device is
inserted in an EPROM programmer socket, the programmer
reads the code and then automatically calls up the specific
programming algorithm for the part. This automatic programming control is only possible with programmers which
have the capability of reading the code.
Program Inhibit
Programming multiple NMC27C64Ns in parallel with different data is also easily accomplished. Except for CE all like
inputs (including OE and PGM) of the parallel NMC27C64N
may be common. A TTL low level program pulse applied to
an NMC27C64Ns PGM input with CE at VIL and Vpp at
13.0V will program that NMC27C64N. A TTL high level CE
input inhibits the other NMC27C64Ns from being programmed.
SYSTEM CONSIDERATION
The power switching characteristics of this device require
careful decoupling. The supply current, Icc, has three segments that are of interest to the system designer-the
standby current level, the active current level, and the transient current peaks that are produced by voltage transitions
on input pins. The magnitude of these transient current
peaks is dependent on the output capacitance loading of
the device. The associated Vee transient voltage peaks can
be suppressed by properly selected decoupling capaCitors.
It is recommended that at least a 0.1 ".F ceramic capacitor
be used on every device between Vee and GND. This
should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 ".F bulk electrolytic capacitor should be used between Vee and GND for each eight
devices. The bulk capacitor should be located near where
the power supply is connected to the array. The purpose of
the bulk capacitor is to overcome the voltage drop caused
by the inductive effects of the PC board traces.
Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with Vpp at 13.0V. Vpp must be at
Vee, except during programming and program verify.
MANUFACTURER'S INDENTIFICATION CODE
The NMC27C64N has a manufacturer's identification code
to aid in programming. The code, shown in Table II, is two
bytes wide and is stored in a ROM configuration on the chip.
It identifies the manufacturer and the device type. The code
for the NMC27C64N is "BFC2", where "BF" designates that
it is made by National Semiconductor, and "C2" designates
a 64k part.
The code is accessed by applying 12V ±0.5V to address
pin A9. Addresses A1-AB, A10-A12, CE and OE are held
at VIL. Address AO is held at VIL for the manufacturer's
code, and at VIH for the device code. The code is read out
on the B data pins. Proper code access is only guaranteed
at 25°C ± 5°C.
TABLE II. Manufacturer's Identification Code
Pins
Manufacturer Code
Device Code
AO
(10)
06
05
03
00
(18)
(17)
(15)
(11)
Hex
Data
o
o
o
o
C2
1-45
o
o
SF
o
o
o
o0)
N
.....
oIiIo
Z
~NaHonal
~
PRELIMINARY
Semiconductor
NMC27C128B High Speed Version
131,072-Bit (16k x 8) UV Erasable CMOS PROM
General Description
Features
The NMC27C128B is a high-speed 128k UV erasable and
electrically reprogram mabie CMOS EPROM, ideally suited
for applications where fast turnaround, pattern experimentation and low power consumption are important requirements.
The NMC27C128B is designed to operate with a single
+ 5V power supply with ± 5% or ± 10% tolerance. The
CMOS design allows the part to operate over extended and
niilitary temperature ranges.
The NMC27C128B is packaged in a 28-pin dual-in-line
package with transparent lid. The transparent lid allows the
user to expose the chip to ultraviolet light to erase the bit
pattern. A new pattern can then be written electrically into
the device by following the programming procedure.
• Clock sense amps for fast access time down to 150 ns
• Low CMOS power consumption
- Active Power: 110 mW max
- Standby Power: 0.55 mW max
• Extended
temperature range
(NMC27C128BQE),
-40"C to + 85°C, and military temperature range
(NMC27C128BQM), - 55°C to + 125°C available
• Pin compatible with NMOS 128k EPROMs
• Fast and reliable programming-100 ,...S typical/byte
• Static operation-no clocks required
• TTL, CMOS compatible inputs/outputs
• TRI-STATE® output
• Optimum EPROM for total CMOS systems
• Manufacturer's identification code for automatic programming control
• High current CMOS level output drivers
This EPROM is fabricated with National's proprietary, time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low power consumption and excellent reliability.
Block Diagram
NMC27C128B
DATA OUTPUTS 00-07
Vee 0---+
GNDo---+
Pin Names
OUTPUT
BUFFERS
Y GATING
M-A13
ADDRESS
INPUTS
85.538-BIT
CliLLMATRIX
TL/D/9689-1
1-46
AO-A13
Addresses
CE
Chip Enable
OE
Output Enable
00-0 7
Outputs
PGM
Program
NC
No Connect
Connection Diagrams
NMC27C128B
Dual-In-Llne Package
27C512 27C256 27C64 27C32 27C16
27512
27256
2764 2732
27C16
2716
27C32 27C64 27C256 27C512
2716
A15
Vpp
Vpp
Vpp- 1
A12
A12
A12
A12- 2
A7
A7
A7
A7
A7
A7- 3
A6
A6
A6
A6
A6
2764
27256
27512
28 ~Vcc
Vee
Vee
Vee
27 I-PGI.1
PGM
A14
26
~A13
A6- 4
25
~A8
24 I-A9
2732
A14
"
'A13
Vee
Vee
NC
A13
AS
AS
AS
AS
A9
A9
A9
A9
A9
Vpp
All
All
All
All
AS
A5
A5
A5
A5
A5
A5- 5
A4
A4
A4
A4
A4
A4-6
23
A3
A3
A3
A3
A3
A3- 7
22 ~OE
OE
OElVpp
OE
OE
OElVpp
21 I-AID
A1D
AID
Al0
Al0
Al0
~All
A2
A2
A2
A2
A2
A2- 8
Al
Al
Al
Al
Al
Al- 9
20 ~CE
CE/PGM
CE
CE
CE/PGM
CE
AO
AO
AO
AO
AO
AO- 10
19 ~07
07
07
07
07
07
00
00
00
00
00
00 -
11
18 1-06
Os
Os
Os
Os
Os
01
01
01
01
01
0 1-
12
17 1-05
Os
Os
Os
Os
Os
02
02
02
02
02
16 ~04
04
04
04
04
04
GND
GND
GND
GND
GND
O2 - 13
GND- 14
15 ~03
Os
Os
Os
Os
OS
TL/D/9689-2
Note: Socket compatible EPROM pin configurations are shown i~ the blocks adjacent to the NMC27CI2BB pins.
Order Number NMC27C128BQ
See NS Package Number J28AQ
Commercial Temp Range (D'C to
Vee = 5V ±10%
+ 70'C)
Commercial Temp Range (O'C to
Vee = 5V ±5%
+ 70'C)
Parameter/Order Number
Access Time (ns)
Parameter/Order Number
NMC27C12SBQ150
150
NMC27C12SBQ15
150
NMC27C12SBQ200
200
NMC27C12SBQ20
200
NMC27C12SBQ250
250
NMC27C12SBQ25
250
Extended Temp Range (-40'C to
Vee = 5V ±10%
+ 85'C)
Access Time (ns)
Military Temp Range (-55'C to
Vee = 5V ±10%
+ 125'C)
Parameter/Order Number
Access Time (ns)
Parameter/Order Number
Access Time (ns)
NMC27C12SBQE150
150
NMC27C12SBQM150
150
NMC27C12SBQE200
200
NMC27C12SBQM200
200
NOTE: For plastic DIP and surface mount PLCC package requirements please refer to NMC27C128BN datasheet.
1-47
III
CO
....N
~
N
o
::::i
z
COMMERCIAL TEMPERATURE RANGE
Absolute Maximum Ratings
Temperature Under Bias
Power Dissipation
-S5·Cto + 150·C
Storage Temperature
All Input Voltages except A9 with
Respect to Ground (Note 10)
All Output Voltages with
Respect to Ground (Note 10)
(Note 1)
-10"Cto +80·C
+S.5Vto -O.SV
Vee Supply Voltage with
Respect to Ground
300"C
ESD Rating
(Mil Spec 883C. Method 3015.2)
2000V
Operating Conditions (Note 7)
Vee+1.0Vto GND-O.SV
Vpp Supply Voltage and A9
with Respect to Ground
During Programming
1.0W
Lead Temperature (Soldering. 10 sec.)
O·C to + 70"C
Temperature Range
Vee Power Supply
NMC27C128BQ150. 200. 250
NMC27C128BQ15. 20. 25
+ 14.0V to - O.SV
+ 7.0V to
+5V ±100/0
±5V ±50/0
-o.sv
READ OPERATION
DC Electrical Characteristics
Symbol
Parameter
Conditions
=
Min
III
Input Load Current
VIN
ILO
Output Leakage Current
VOUT
lee1
(Note 9)
Vee Current (Active)
TTL Inputs
CE = VIL. f = 5 MHz
Inputs = VIH or VIL. 110
lee2
(Note 9)
Vee Current (Active)
CMOS Inputs
CE = GND. f = 5 MHz
Inpuls = Vee or GND. 110
leeSB1
Vee Current (Standby)
TTL Inputs
CE
=
VIH
leCSB2
Vee Current (Standby)
CMOS Inputs
CE
=
Vee
Ipp
Vpp Load Current
Vpp
Vee or GND
=
=
Vee or GND. CE
=
=
VIH
0 mA
=
Input Low Voltage
VIH
Input High Voltage
2.0
VOL1
Output Low Voltage
IOL
VOH1
Output High Voltage
IOH
Output Low Voltage
Output High Voltage
Units
1
poA
0.01
1
poA
10
30
mA
8
20
mA
0.1
1
mA
0.5
100
p.A
10
/Jo A
Vee
VIL
VOH2
Max
0 mA
-0.2
VOL2
Typ
0.Q1
= 2.1 mA
= -2.5mA
IOL = 10 poA
IOH = -10 poA
0.8
V
Vee + 1
V
0.40
V
3.5
V
0.1
V
V
Vee - 0.1
AC Electrical Characteristics
NMC27C128B
Symbol
Parameter
Conditions
015,0150
Min
tAee
Address to Output Delay
teE
CE to Output Delay
toE
OE to Output Delay
tOF
OE High to Output Float
teF
CE High to Output Float
toH
Output Hold from Addresses.
CE or OE. Whichever
Occurred First
CE = OE = VIL
PGM = VIH
Max
020,0200
Min
Max
025,0250
Min
Units
Max
150
200
250
ns
OE
150
200
250
ns
CE
SO
75
100
ns
= VIL. PGM = VIH
= VIL. PGM = VIH
CE = VIL. PGM = VIH
OE = VIL. PGM = VIH
CE = OE = VIL
PGM = VIH
1-48
0
50
0
55
0
60
ns
0
50
0
55
0
60
ns
0
0
0
ns
z
3:
MILITARY AND EXTENDED TEMPERATURE RANGE
Absolute Maximum Ratings
oN
......
o......
(Note 1)
N
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature Under Bias
Operating Temp. Range
Vee Supply Voltage with
Respect to Ground
Lead Temperature (Soldering, 10 sec.)
300'C
Storage Temperature
ESD Rating
(Mil Spec 883C, Method 3015.2)
2000V
Power Dissipation
-S5'Cto + 150'C
All Input Voltages except A9 with
Respect to Ground (Note 10)
All Output Voltages with
Respect to Ground (Note 10)
+7.0Vto -O.SV
co
til
1.0W
+S.5Vto -O.SV
Operating Conditions (Note 7)
Vee + 1.0Vto GND-O.SV
Vpp Supply Voltage and A9
with Respect to Ground
During Programming
Temperature Range
NMC27C128BOE150, 200
NMC27C128BOM 150. 200
+ 14.0Vto -O.SV
-40'Cto + 85'C
-55'Cto + 125'C
+5V ±10%
Vee Power Supply
READ OPERATION
DC Electrical Characteristics
Symbol
Parameter
Conditions
=
Min
III
Input Load Current
ILO
Output Leakage Current
VOUT
leel
(Note 9)
Vee Current (Active)
TTL Inputs
CE = VIL, f = 5 MHz
Inputs = VIH or VIL. 1/0
ICC2
(Note 9)
Vee Current (Active)
CMOS Inputs
CE = GND, f = 5 MHz
Inputs = Vee or GND, 1/0
leeSBl
Vee Current (Standby)
TTL Inputs
CE
=
VIH
ICCSB2
Vee Current (Standby)
CMOS Inputs
CE
=
Vee
Vpp
VIN
Typ
Max
Units
10
p.A
10
p.A
10
30
rnA
8
20
rnA
0.1
1
rnA
0.5
100
p.A
Vee or GND
=
=
Vee or GND, CE
=
=
VIH
0 rnA
=
0 rnA
Ipp
Vpp Load Current
10
p.A
VIL
Input Low Voltage
-0.2
0.8
V
VIH
Input High Voltage
2.0
Vee + 1
V
VOLl
Output Low Voltage
VOHl
Output High Voltage
VOL2
Output Low Voltage
VOH2
Output High Voltage
Vee
= 2.1 mA
IOH = -1.SmA
IOL = 10 p.A
IOH = -10 p.A
0.40
IOL
3.5
V
V
0.1
V
V
Vee - 0.1
AC Electrical Characteristics
NMC27C128BQ
Symbol
Parameter
Conditions
E150, M150
Min
tAee
Address to Output Delay
CE = OE = VIL
PGM = VIH
teE
CE to Output Delay
tOE
OE to Output Delay
= VIL, PGM = VIH
= VIL, PGM = VIH
CE = VIL. PGM = VIH
CE = VIL, PGM = VIH
CE = OE = VIL
PGM = VIH
tOF
CE High to Output Float
teF
CE High to Output Float
toH
Output Hold from Addresses,
CE or CE, Whichever
Occurred First
Max
E200,M200
Min
Units
Max
ns
150
200
OE
150
200
ns
CE
SO
75
ns
1·49
0
50
0
55
ns
0
50
0
55
ns
0
0
ns
•
,
lEI
CO
~
~
N
o
:E
z
CapaCitance T A = '+ 25°C. f =
Symbol
Parameter
1 MHz (Note 2)
Typ
Max
Units
CIN
Input CapaCitance
VIN = OV
Conditions
6
12
pF
COUT
Output CapaCitance
VOUT = OV
9
12
pF
AC Test Conditions
Output Load
1 TTL Gate and
CL = 100 pF (Note 8)
Timing Measurement Reference Level
:;;;5 ns
Input Rise and Fall Times
Input Pulse Levels
Inputs
0.8Vand2V
Outputs
0.8Vand2V
0.45Vto 2.4V
AC Waveforms (Notes 6. 7 & 9)
ADDRESSES
~:~~)
-
2.0V
O.SV
ADDRESSES VALID
\.
2.0V
C.SV
- tCF -
"
tOE
(NOTE 3)
OUTPUT
HI-Z
)
)
I---tCE -
2.0V
"
..
..
I-
O.BV
VALID OUTPUT ;;
j . - - , tACC , _
(NOTE 3)
NOTES 4.5
)
-
tOF
NOTES 4.5
IHI-Z
tOHITLID/9689-3
Nole 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the, device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Nole 3: OE may be delayed up to tAce - toE after the falling edge of CE without impacting tAce.
Nole 4: The tOF and tcF compare level is determined as follows:
High to TRI·STATE. the measured VOH' (DC) -0.10V;
Low to TRI-STATE. the measured VOL1 (DC) +O.tOV:
Note 5: TRI·STATE may be attained using OE or CE.
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 "F ceramic capac~or be used on
every device between Vce and GND.
'
Note 7: The outputs must be restricted to Vcc + 1.0V to avoid latch-up and device damage.
Note 8: 1 TTL Gate: IOL
~
1.6 mAo IOH
~
-400 "A.
CL: 100 pF includes fixture capaCitance.
Nole 9: Vpp may be connected to Vce except during programming.
Note 10: Inputs and outputs can undershoot to - 2.0V for 20 ns Max.
1-50
z
s::
(")
Programming Characteristics (Notes 1,2,3 & 4)
Symbol
Parameter
Conditions
....
N
Min
Typ
Max
Units
tAS
Address Setup Time
1
".s
(")
.....
N
tOES
OE Setup Time
1
".s
OJ
teEs
CE Setup Time
1
".s
tos
Data Setup Time
1
".s
tvps
Vpp Setup Time
1
".s
tves
Vee Setup Time
1
".s
tAH
Address Hold Time
0
".s
tOH
Data Hold Time
1
tOF
Output Enable to Output Float Delay
OE = VIH
".s
0
CE = VIL
60
ns
105
".s
tpw
Program Pulse Width
tOE
Data Valid from OE
CE = VIL
100
ns
Ipp
Vpp Supply Current During
Programming Pulse
CE = VIL
PGM = VIL
30
mA
Icc
Vee Supply Current
10
mA
TA
Temperature Ambient
20
25
30
·C
Vee
Power Supply Voltage
6.0
6.25
6.5
V
Vpp
Programming Supply Voltage
12.5
12.75
13.0
tFR
Input Rise, Fall Time
VIL
Input Low Voltage
VIH
Input High Voltage
2.4
4.0
tiN
Input Timing Reference Voltage
0.8
1.5
2.0
V
tOUT
Output Timing Reference Voltage
0.8
1.5
2.0
V
95
100
5
V
ns
0.0
Programming Waveforms
CD
0.45
V
V
(Note 3)
ADDRESSES
=iJJ.....)
DATA
fiv-,
PROGRAM_
-PROGRAM
VERIFY
~
1 -
....
HI-Z
DA.TAINSfABLE
~
._
!L
ADDRESS N
~
....
1..,
DATA OUT V,W)
,--
_ID'
vcc~_ ~
II
12.5V
vpp =.J~
CE
O.BY
!-'cEs_
PGii o~
-1o£s1 -10,OE
llv
.-TLIDI9689-4
National's standard product warranty applies to devices programmed to specifications described herein.
Nole 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vee.
Nole 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 "F capacitor is required across Vpp, Vee to GNO to suppress
spurious voltage transients which may damage the device.
Nole 4: Programming and program verify are tested with the fast Program Algorithm, at typical power supply voltages and timings.
Nole 1:
1-51
r:D
~
Fast Programming Algorithm Flow Chart (Note 4)
~
3
:::!
z
INCREMENT ADDR
TL/D/9669-5
FIGURE 1
1·52
Interactive Programming Algorithm Flow Chart (Note 4)
INCREMENT ADDR
•
TL/D/9689-8
FIGURE 2
1·53
Functional Description
DEVICE OPERATION
The six modes of operation of the NMC27C128B are listed
in Table I. It should be noted that all inputs for the six modes
are at TTL levels. The power supplies required are Vee and
Vpp. The Vpp power supply must be at 12.75V during the
three programming modes, and must be at Vcc in the other
three modes. The Vcc power supply must be at 6.25V during the three programming modes, and at 5V in the other
three modes.
mary device selecting function, while OE (pin 22) be made a
common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low
power standby modes and that the output pins are active
only when data is desired from a particular memory device.
Read Mode
The NMC27C128B has two control functions, both of which
must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be
used for device selection. Output Enable (OE) is the output
control and should be used to gate data to the output pins,
independent of device selection. The programming pin
(PGM) should be at VIH except during programming. Assuming that addresses are stable, address access time (tAccl is
equal to the delay from CE to output (tCE). Data is available
at the outputs toE after the falling edge of OE, assuming
that CE has been low and addresses have been stable for
at least tACC-tOE'
The sense amps are clocked for fast access time. Vee
should therefore be maintained at operating voltage during
read and verify. If Vcc temporarily drops below the spec.
voltage (but not to ground) an address transition must be
performed after the drop to insure proper output data.
Initially, and after each erasure, all bits of the NMC27C128B
are in the "1" state. Data is introduced by selectively programming "Os" into the desired bit locations. Although only
"Os" will be programmed, both "1s" and "Os" can be presented in the data word. The only way to change a "0" to a
"1" is by ultraviolet light erasure.
Programming
CAUTION: Exceeding 14V on pin 1 (Vpp) will damage the
NMC27C128B.
The NMC27C128B is in the programming mode when the
Vpp power supply is at 12.75V and OE is at VIH. It is required that at least a 0.1 /LF capacitor be placed across
Vpp, Vee to ground to suppress spurious voltage transients
which may damage the device. The data to be programmed
is applied 8 bits in parallel to the data output pins. The levels
required for the address and data inputs are TTL.
For programming, CE should be kept TTL low at all times
while Vpp is kept at 12.75V
When the address and data are stable, an active low, TTL
program pulse is applied to the PGM input. A program pulse
must be applied at each address location to be programmed. The NMC27C128B is programmed with the Fast
Programming Algorithm shown in Figure 1. Each Address is
programmed with a series of 100 /Ls pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
program with a Single 100 /Ls pulse.
Standby Mode
The NMC27C128B has a standby mode which reduces the
active power dissipation by over 99%, from 110 mW to
0.55 mW. The NMC27C128B is placed in the standby mode
by applying a CMOS high signal to the CE input. When in
standby mode, the outputs are in a high impedance state,
independent of the OE input.
Note: Some programmer manufacturers due to equipment limitation may
offer interactive program AlgOrithm (shown in Figure 2).
The NMC27C128B must not be programmed with a DC signal applied to the PGM input.
Programming multiple NMC27C128Bs in parallel with the
same data can be easily accomplished due to the simplicity
of the programming requirements. Like inputs of the paralleled NMC27C128Bs may be connected together when they
are programmed with the same data. A low level TTL pulse
applied to the PGM input programs the paralleled
NMC27C128Bs.
Output OR·Tying
Because NMC27C128Bs are usually used in larger memory
arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended that CE (pin 20) be decoded and used as the pri-
TABLE I. Mode Selection
Pins
Mode
CE
(20)
OE
(22)
PGM
(27)
Vpp
(1)
Vee
(28)
Outputs
(11-13,15-19)
Read
VIL
VIH
Don't
Care
5V
VIH
VIL
Don't
Care
Vcc
Standby
Vcc
5V
DOUT
Hi-Z
Don't
Care
VIH
VIH
Vee
5V
Hi-Z
Program
VIL
VIH
VIL
12.75V
6.25V
DIN
Program Verify
VIL
6.25V
VIH
VIH
Don't
Care
12.75V
Program Inhibit
VIL
Don't
Care
12.75V
6.25V
DOUT
Hi-Z
Output Disable
1-54
z
Functional Description
3:
(Continued)
Program Inhibit
After programming opaque labels should be placed over the
NMC27C128B's window to prevent unintentional erasure.
Covering the window will also prevent temporary functional
failure due to the generation of photo currents.
Programming multiple NMC27C128s in parallel with different data is also easily accomplished. Except for CE all like
inputs (including OE and PGM) of the parallel
NMC27C128Bs may be common. A TTL low level program
pulse applied to an NMC27C128B's PGM input with CE at
VIL and Vpp at 12.75V will program that NMC27C128B. A
TTL high level CE input inhibits the other NMC27C128Bs
from being programmed.
the
The
recommended
erasure
procedure
for
NMC27C128B is exposure to short wave ultraviolet light
which has a wavelength of 2537 Angstroms (A). The integrated dose (Le., UV intensity x exposure time) for erasure
should be a minimum of 15W-sec/cm2.
The NMC27C128B should be placed within 1 inch of the
lamp tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. Table III
shows the minimum NMC27C128B erasure time for various
light intensities.
Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with Vpp at 12.75V. Vpp must be at
Vee except during programming and program verify.
An erasure system should be cailbrated periodically. The
distance from lamp to unit should be maintained at one inch.
The erasure time increases as the square of the distance. (If
distance is doubled the erasure time increases by a factor of
4.) Lamps lose intensity as they age. When a lamp is
changed, the distance has changed or the lamp has aged,
the system should be checked to make certain full erasure
is occurring. Incomplete erasure will cause symptoms that
can be misleading. Programmers, components, and even
system designs have been erroneously suspected when incomplete erasure was the problem.
MANUFACTURER'S IDENTIFICATION CODE
The NMC27C128B has a manufacturer's identification code
to aid in programming. The code, shown in Table II, is two
bytes wide and is stored in a ROM configuration on the chip.
It identifies the manufacturer and the device type. The code
for the NMC27C128B is "8F83", where "8F" designates
that it is made by National Semiconductor, and "83" designates a 128k part.
The code is accessed by applying 12.0V ± 0.5V to address
pin A9. Addresses A1-AB, Al0-A13, CE, and OE are held
at VIL. Address AO is held at VIL for the manufacturer's
code, and at VIH for the device code. The code is read out
on the 8 data pins. Proper code access is only guaranteed
at 25°C ± 5°C.
SYSTEM CONSIDERATION
The power switching characteristics of this device require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer-the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 ,...F ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 ,...F bulk electrolytic
capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
The primary purpose of the manufacturer's identification
code is automatic programming control. When the device is
inserted in an EPROM programmer socket, the programmer
reads the code and then automatically calls up the specific
programming algorithm for the part. This automatic programming control is only possible with programmers which
have the capability of reading the code.
ERASURE CHARACTERISTICS
The erasure characteristics of the NMC27C128B are such
that erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000A-4000A
range.
TABLE II. Manufacturer's Identification Code
AO
(10)
Pins
07
06
05
04
03
02
01
(19) (18) (17) (16) (15) (13) (12)
(11)
Hex
Data
00
Manufacturer Code
VIL
1
0
0
0
1
1
1
1
8F
Device Code
VIH
1
0
0
0
0
0
1
1
83
TABLE III. Minimum NMC27C128B Erasure Time
Light Intensity
(,...W/cm 2)
Erasure Time
(Minutes)
15,000
20
10,000
25
5,000
50
1-55
(")
N
--...I
(")
......
co
N
OJ
z
m
~ ~National
~
~ Semiconductor
C"I
o
I NMC27C128BN
High Speed Version 131,072-Bit (16k x 8)
One Time Programmable CMOS PROM
PRELIMINARY
General Description
Features
The, NMC27C128BN is a high-speed 128k one time programmable CMOS PROM, ideally suited for applications
where fast turnaround and low power consumption are important requirements.
• Clocked sense amps for fast access time down
to 150'ns
• Low CMOS power consumption
- Active Power: 11.0 mW max
- Standby Power: 0.55 mW max
• Optimum EPROM for total CMOS systems
• Pin compatible with NMOS 12Bk EPROMs
• Fast and reliable programming-100,..s typicel/byte
• Static operation-no clocks required
• TIL, CMOS compatible inputs/outputs
• TRI-STATEIII> output
• Manufacturer's identification code for automatic
programming control
• High current CMOS level output drivers
The NMC27C128BN is designed to operate with a Single
+5V power supply with ±5% or ±10% tolerance.
The NMC27C12BBN is packaged in a 2B-pin dual-in-line
plastic molded package without a transparent lid. This part
is ideally suited for high volume production applications
where cost is an important factor and programming only
needs to be done once. Also the plastic molded package
works well in auto insertion equipment used in automated
assembly lines.
This EPROM is fabricated with National's proprietary, time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low pow~
er consumption and excellent reliability.
Block Diagram
DATA OUTPUTS Ilo-07
Vceo--.
GNDo--.
Pin Namea
OUTPUT
BUFFfRS
AO-A13
Y GATING
AO·A13.AR
ADDRESS
INPIITS
131.072·BIT
CEll MATRIX
TL/O/9690-1
1-56
Addresses
CE
Chip Enable
OE
Output'Enable
00-0 7
Outputs
PGM
Program
z
s:::
o
N
Connection Diagram
......
27C512 27C256 27C64 27C32 27C16
27512
27256
2764
2732
27C16
2716
27C32 27C64 27C256 27C512
2716
Dual-In-Llne Package
2732
2764
27256
27512
A15
Vpp
Vpp
Vpp _
Vet
Vee
Vee
Vee
A12
A12
A12
A12- 2
27 -
PGM
PGM
A14
A14
A7
A7
A7
A7
A7
A7- 3
26 -
A13
Vee
Vee
NC
A13
A13
A6
A6
A6
A6
A6
A6 -
4
25 -
AS
A8
A8
A8
A8
A8
A5
A5
A5
A5
A5
A5- 5
24 -
A9
A9
A9
A9
A9,
A9
A4
A4
A4
A4
A4
A4- 6
23 -All
Vpp
All
All
All
All
A3
A3
A3
A3
A3
A3-7
22 -DE
OE
OElVpp
OE
OE
OElVpp
A2
A2
A2
A2
A2
AZ-8
21 -AID
Al0
Al0
Al0
Al0
Al0
Al
Al
Al
Al
Al
Al- 9
20 -Ci!
CE/PGM
CE
CE
CE/PGM
CE
AO
AO
AO
AO
AO
AD- 10
19
00
00
00- 11
18 -De
06 ,
07
06
17 -05
Os
Os
Os
Os
Os
02
01
02
01- 12
02
01
02
00
01
07
06
01
00
01
07
06
07
00
07
06
02
02- 13
16 - 0 ,
04
04
GND
GND
GND
GND
GNO- 14
15 -03
03
04
03
04
GND
04
03
1
28
~
-117
03
o
-0.
N
CD
to
Z
03
TL/D/9690-2
Note: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMC27C128BN pins,
Order Number NMC27C128BN
See NS Package Number N28B
Commercial Temp Range (O"C to
Vee = 5V ±5%
+ 70"C)
Access Time (ns)
Parameter/Order Number
NMC27C128BN15
150
NMC27C128BN20
200
NMC27C126BN25
250
Commercial Temp Range (O'C to
Vee = 5V ± 100/0
Parameter/Order Number
+ 70'C)
Access Time (ns)
NMC27C128BN150
150
NMC27C128BN200
200
NMC27C128BN250
250
For non-commercial temperature range parts. call the factory.
1-57
•
Z
I:D
GO
....
'"
~
o'"
::E
z
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature Under Bias
-10"Cto +80'C
Storage Temperature
All Input Voltages except A9 with
Respect to Ground (Note 10)
'All Output Voltages with
Respect to Ground (Note 10)
Vee Supply Voltage with
Respect to Ground
-65'Cto + 150"C
+7.0Vto -6.0V
Power Dissipation
Lead Temperature (Soldering. 10 sec.)
1.0W
300"C
ESD Rating
(Mil Spec 883C. Method 3015.2)
2000V
+6.5Vto -0.6V
Operating Conditions (Note 7)
Vee+ 1.0V to GND-0.6V
Vpp Supply Voltage and A9
with Respect to Ground
During Programming
Temperature Range
O'Cto +70'C
Vee Power Supply
NMC27C128BN 150. 200. 250
NMC27C128BN15. 20. 25
+ 14.0Vto -0.6V
+5V ±10%
+5V ±5%
READ OPERATION
DC Electrical Characteristics
Symbol
Typ
Max
Units
III
Input Load Current
Parameter
VIN = VccorGND
Conditions
Min
0.01
1
/LA
ILO
Output Leakage Current
VOUT = Vee or GND. CE = VIH
0,01
1
/LA
ICCl
(Note 9)
Vee Current (Active)
TTL Inputs
CE = VIL. f = 5 MHz
Inputs = VIH or VIL. I/O = 0 mA
10
30
mA
ICC2
(Note 9)
Vee Current (Active)
CMOS Inputs
CE = GND. f = 5 MHz
Inputs = Vee or GND. I/O = 0 mA
8
20
mA
ICCSBl
Vee Current (Standby)
TTL Inputs
CE = VIH
0.1
1
mA
leeSB2
Vee Current (Standby)
CMOS Inputs
CE = Vee
0.5
100
/LA
Ipp
Vpp Load Current
Vpp = Vee
10
/LA
VIL
Input Low Voltage
-0.2
VIH
Input High Voltage
2.0
VOL1
Output Low Voltage
IOL = 2.1 mA
VOHl
Output High Voltage
IOH = -2.5mA
VOL2
Output Low Voltage
IOL = 10/LA
VOH2
Output High Voltage
IOH = -10/LA
0.8
V
Vee + 1
V
0.40
V
3.5
V
0.1
V
V
Vee - 0.1
AC Electrical Characteristics
NMC27C128B
Symbol
Parameter
Conditions
N15, N150
Min
tACC
Address to Output Delay
teE
tOE
Max
N20, N200
Min
Max
N25,N250
Min
Units
Max
CE = OE = VIL '
PGM = VIH
150
200
250
ns
CE to Output Delay
OE = VII:'. PGM = VIH
150
200
250
ns
OE to Output Delay
CE = VIL. PGM = VIH
60
75
100
ns
tOF
OE High to Output Float
CE = VIL. PGM = VIH
0
50
0
55
0
60
ns
tcF
CE High to Output Float
OE = VIL. PGM = VIH
0
50
0
55
0
60
ns
toH
Output Hold from Addresses.
CE or 01:. Whichever
Occurred First
CE = OE = VIL
PGM = VIH
0
1-58
0
0
ns
z
3:
oN
......
o
Capacitance TA = + 25°C, f = 1 MHz (Note 2)
Symbol
Parameter
Conditions
= OV
CIN
Input Capacitance
VIN
COUT
Output Capacitance
VOUT
= OV
Typ
Max
Units
5
10
pF
...
8
10
pF
m
N
CD
Z
AC Test Conditions
Timing Measurement Reference Level
Inputs
Outputs
1 TTL Gate and
CL = toO pF (Note 8)
Output Load
,;;5 ns
Input Rise and Fall Times
0.8V and 2V
0.8Vand 2V
0.45V to 2.4 V
Input Pulse Levels
AC Waveforms (Notes 6,7 & 9)
ADDRESSES VALID
ADDRESSES
cr
OE
OUTPUT
2.0V
O.BV
2.0V
O.BV
*,2.~OV:;--+_H_i-_Z_-+H-H-H-H-<
VALID OUTPUT
Hi-Z
~~~~T---------\'r----+-+t.LJ.:.II
O.BV
t -_ _-:-tAcc .,---~
(NOTE 3)
TLID/9690-3
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: DE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC.
Note 4: The tOF and tCF compare level is determined as follows:
High to TRI·STATE, the measured VOH' (DC) - O.10V;
Low to TRI-STATE, the measured VOL1 (DC) + 0.10V.
Note 5: TRI·STATE may be attained using DE or CE.
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 ,u,F ceramic capacitor be used on
every device between Vee and GND.
Note 7: The outputs must be restricted to Vee
Note 8: 1 TTL Gate: IOL
~
1.6 mA, IOH
~
+
1.0V to avoid latch·up and device damage.
- 400 I'A
CL: 100 pF includes fixture capacitance.
Note 9: Vpp may be connected to Vee except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns max.
1-59
z
m
co
....
o
o"'"
N
N
::::!!
z
Programming Characteristics (Notes 1,2,3 & 4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tAS
Address Setup Time
1
",s
tOES
OE Setup Time
1
",s
teEs
CE Setup Time
1
",s
tos
Data Setup Time
1
",s
tyPS
Vpp Setup Time
1
",s
tyes
Vee Setup Time
1
",s
tAH
Address Hold Time
0
",s
tOH
Data Hold Time
1
",s
tOF
Output Enable to Output Float Delay
tpw
Program Pulse Width
OE = VIH
CE = VIL
0
95
100
60
ns
105
",s
toE
Data Valid from OE
CE = VIL
100
ns
Ipp
Vpp Supply Current During
Programming Pulse
CE = VIL
PGM = VIL
30
rnA
lee
Vee Supply Current
10
rnA
TA
Temperature Ambient
20
25
30
'C
Vee
Power Supply Voltage
6.0
6.25
6.5
V
12.5
12.75
13.0
Vpp
Programming Supply Voltage
tFR
Input Rise, Fall Time
VIL
Input Low Voltage
VIH
Input High Voltage
2.4
4.0
tiN
Input Timing Reference Voltage
0.6
1.5
2.0
V
tOUT
Output Timing Reference Voltage
0.6
1.5
2.0
V
5
0.0
1-60
V
ns
0.45
V
V
z
iii:
Programming Waveforms (Note 3)
o
~
o....
I\)
CD
m
z
OE
2V
O.BV
TLlD/9690-4
Note 1: National's standard product warranty applies only to devices programmed to specifications described herein.
Note 2: Vee must be applied simultaneously or before Vpp and removed simullaneously or after Vpp. The EPROM must not be inserted into or removed from a
board wHh voltage applied to Vpp or Vee.
Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Cara must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 ,.F capacHer is required across Vpp, Vee to GND to suppress
spurious voltage transients which may damage the device.
Note 4: Programming and program verify are tested with the fast Program Algorithm, at typical power supply voltages and timings.
1·61
z
;
....
Fast Programming Algorithm Flow Chart (Note 4)
~
N
o
:::::E
Z
INCREMENT ADDR
TL/D/9690-5
FIGURE 1
1·62
Interactive Programming Algorithm Flow Chart (Note 4)
INCREMENT ADDR
TUD/9690-6
FIGURE 2
1·63
Z
a:I
co
C'I
.,...
o.....
C'I
o
:::E
z
Functional Description
To most efficiently use these two control lines, it is recommended that CE (pin 20) be decoded and used as the primary device selecting function, while OE (pin 22) be made a
common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low
power standby modes and that the output pins are active
only when data is desired from a particular memory device.
DEVICE OPERATION
The six modes of operation of the NMC27C128BN are listed
in Table I. It should be noted that all inputs for the six modes
are at TTL levels. The power supplies required are Vee and
Vpp. The Vpp power supply must be at 12.75V during the
three programming modes, and must be at Vee in the other
three modes. The Vee power supply must be at 6.25V during the three programming modes, and at 5V in the other
three modes.
Programming
CAUTION: Exceeding 14V on pin 1 (Vpp) will damage the
NMC27C128BN.
Read Mode
The NMC27C128BN has two control functions, both of
which must be logically active in order to obtain data at the
outputs. Chip Enable (CE) is the power control and should
be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output
pins, independent of device selection. The programming pin
(PGM) should be at VIH except during programming. Assuming that addresses are stable, address access time (tAee) is
equal to the delay from CE to output (teE). Data is available
at the outputs tOE after the falling edge of OE, assuming
that CE has been low and addresses have been stable for
at least tAee-tOE'
Initially, and after each erasure, all bits of the
NMC27C128BN are in the "1" state. Data is introduced by
selectively programming "Os" into the desired bit locations.
Although only "Os" will be programmed, both "1s" and "Os"
can be presented in the data word.
The NMC27C128BN is in the programming mode when the
Vpp power supply is at 12.75V and OE is at VIH. It is required that at least a 0.1 ,.,.F capacitor be placed across
Vpp, Vee to ground to suppress spurious voltage transients
which may damage the device. The data to be programmed
is applied 8 bits in parallel to the data output pins. The levels
required for the address and data inputs are TIL.
The sense amps are clocked for fast access time. Vee
should therefore be maintained at operating voltage during
read and verify. If Vee temporarily drops below the spec.
voltage (but not to ground) an address transition must be
performed after the drop to insure proper output data.
For programming, CE should be kept TIL low at all times
while Vpp is kept at 12.75V.
When the address and data are stable, an active low TIL
program pulse is applied to the PGM input. A program pulse
must be applied at each address location to be programmed. The NMC27C128BN is programmed with the
Fast Programming Algorithm shown in Figure 1. Each Address is programmed with a series of 100 ,.,.S pulses until it
verifies good, up to a maximum of 25 pulses. Most memory
cells will Program with a single 100 P.s pulse.
Standby Mode
The NMC27C128BN has a standby mode which reduces
the active power dissipation over 99%, from 110 mW to
0.55 mW. The NMC27C128BN is placed in the standby
mode by applying a CMOS high signal to the CE input.
When in standby mode, the outputs are in a high impedance
state, independent of the OE input.
Note: Some programmer manufacturers due to equipment limitation may
offer interactive program Algorithm (Shown in Figure 21.
Output OR-Tying
The NMC27C128BN must not be programmed with a DC
signal applied to the PGM input.
Because NMC27C128BNs are usually used in larger memory arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
Programming multiple NMC27C128BNs in parallel with the
same data can be easily accomplished due to the simplicity
of the programming requirements. Like inputs of the paralleled NMC27C128BNs may be connected together when
they are programmed with the same data. A low level TIL
pulse applied to the PGM input programs the paralleled
NMC27C128BNs.
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
TABLE I. Mode Selection
Pins
Mode
CE
(20)
OE
(22)
PGM
(27)
Vpp
(1)
Vee
(28)
Outputs
(11-13,15-19)
Vee
5V
DOUT
Vee
5V
Hi-Z
Hi-Z
Read
VIL
VIL
VIH
Standby
VIH
Don't Care
Don't Care
Output Disable
Don't Care
VIH
VIH
Vee
5V
Program
VIL
VIH
VIL
12.75V
6.25V
DIN
Program Verify
VIL
VIL
VIH
12.75V
6.25V
DOUT
Program Inhibit
VIH
Don't Care
Don't Care
12.75V
6.25V
Hi-Z
1-64
r--------------------------------------------------------------------------. Z
Functional Description (Continued)
The code is accessed by applying 12.0V ± 0.5V to address
pin A9. Addresses A 1-AS, A1O-A 13, CE, and OE are held
at VIL. Address AO is held at VIL for the manufacturer's
code, and at VIH for the device code. The code is read out
on the S data pins. Proper code access is only guaranteed
at 25·C ± 5·C.
The NMC27C12SBN is packaged in a plastic molded package which does not have a transparent lid. Therefore the
memory cannot be erased. This means that aiter a user has
programmed a memory cell to a "0" it cannot be changed
back to a "1".
If an application requires eraSing and reprogramming, the
NMC27C12SBQ UV Erasable PROM in a windowed package should be used.
The primary purpose of the manufacturer's identification
code is automatic programming control. When the device is
inserted in a EPROM programmer socket, the programmer
reads the code and then automatically calls up the specific
programming algorithm for the part. This automatic programming control is only possible with programmers which
have the capability of reading the code.
Program Inhibit
Programming multiple NMC27C12SBNs in parallel with different data is also easily accomplished. Except for CE all
like inputs (including OE and PGM) of the parallel
NMC27C12SBNs may be common. A TTL low level program
pulse applied to an NMC27C12SBNs PGM input with CE at
VIL and Vpp at 12.75V will program that NMC27C12SBN. A
TTL high level CE input inhibits the other NMC27C12SBNs
from being programmed.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer-the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capaCitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capaCitors. It is recommended that at least a 0.1 ",F ceramic
capaCitor be used on every device between Vee and GND.
This should be a high frequency capaCitor of low inherent
inductance. In addition, at least a 4.7 ",F bulk electrolytic
capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capaCitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with Vpp at 12.75V (Vpp must be at
Vee) except during programming and program verify.
MANUFACTURER'S IDENTIFICATION CODE
The NMC27C12SBN has a manufacturer's identification
code to aid in programming. The code, shown in Table II, is
two bytes wide and is stored in a ROM configuration on the
chip. It identifies the manufacturer and the device type. The
code for the NMC27C12SBN is "SFS3", where "SF" designates that it is made by National Semiconductor, and "S3"
designates a 12Sk part.
TABLE II. Manufacturer's Identification Code
Pins
AO
(10)
07
(19)
06
(18)
05
(17)
04
(16)
Manufacturer Code
VIL
1
0
0
0
VIH
1
0
0
0
Device Code
1-65
03
(15)
00
(11)
Hex
Data
1
1
SF
1
1
S3
02
(13)
01
(12)
1
1
0
0
s:
oN
.....
...co
o
N
m
z
z
m
~
....
~
C'II
o
:::E
Package Information
6 SPACES AT
0.050
(1.2rol
Z
t
0.551 ± 0.002
(14.00±0.0511
0.590 ±0.OO5
(14.99±0.1271
VIEWA·A
~:IJ!I
x45°
0.100-0.140
(2.540 3.5561
• t
0.026-0.032
(0.660-0.8131
TYP
t t
0.060 -0.095
(1.524-2.4131
TL/O/9690-7
32·Lead PLCC Package
Order Number NMC27C128BV
1-66
.------------------------------------------------------------------.z
i:
~National
~
~
~
Semiconductor
~
c.n
Q)
NMC27C256
262, 144-Bit (32k x 8) UV Erasable CMOS PROM
General Description
Features
The NMC27C256 is a high-speed 256k UV erasable and
electrically reprogrammable CMOS EPROM, ideally suited
for applications where fast turnaround, pattern experimentation and low power consumption are important requirements.
The NMC27C256 is designed to operate with a single + 5V
power supply with ± 5% or ± 10% tolerance. The CMOS
design allows the part to operate over extended and military
temperature ranges.
The NMC27C256 is packaged in a 28-pin dual in-line package with transparent lid. The transparent lid allows the user
to expose the chip to ultraviolet light to erase the bit pattern.
A new pattern can then be written electrically into the device
by following the programming procedure.
• Clocked sense amps for fast access time down to
170 ns
• Low CMOS power consumption
- Active power: 55 mW max
- Standby power: 0.55 mW max
• Performance compatible to NSC800TM CMOS microprocessor
• Single 5V power supply
• Extended temperature range (NMC27C256QE),
-40'C to + 85'C, and military temperature range
(NMC27C256QM), - 55'C to + 125'C, available
• Pin compatible with NMOS 256k EPROMs
• Fast and reliable programming (0.5 ms for most bytes)
• Static operation-no clocks required
• TTL, CMOS compatible inputs/outputs
• TRI-STATE output
• Optimum EPROM for total CMOS systems
This EPROM is fabricated with National's proprietary, time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low power consumption and excellent reliability.
Block Diagram
IIA1lI OUTPUTS OD-II-,
Vee C>--+
GND C>--+
Pin Names
OUTPUT
BUFFERS
Y GATING
AD-A14
ADDRESS
INPUTS
212,144-1IT
CELL MATRIX
TUD17512-1
1-67
AO-A14
Addresses
CE
Chip Enable
OE
Output Enable
0 0- 0 7
Outputs
PGM
Program
NC
No Connect
•
Connection Diagram
27C512 27C128 27C64 27C32 27C16
27512 27128 2764 2732 2716
27C16
2716
NMC27C256Q
Dual-In-Llne Package
A15
Vpp
Vpp
Vpp- 1
28 I- Vee
A12
A12
A12
A12- 2
27
A7
A7
A7
A7
A7
A7- 3
26 -
A13
Vee
AS
AS
AS
AS
AS
AB- 4
25 -
AI
A5
A5
A5
A5
A5
A5- 5
24 -
27C32 27C64 27C128 27C512
2732 2764 27128 27512
Vee
Vee
Vee
PGM
PGM
A14
Vee
NC
A13
A13
A8
A8
A8
A8
A8
A9
A9
A9
A9
A9
A9
A11
Vpp
A11
A11
A11
A11
-liE
OE
OE/vpp
OE
OE
OE/vpp
~
A14
A4
A4
A4
A4
A4
M-B
23 -
A3
A3
A3
A3
A3
A3-7
22
A2
A2
A2
A2
A2
A2- 8
21 -Al0
A10
A10
A10
A10
A10
A1
A1
A1
A1
A1
Al- 9
20 -ii/Pm
CE/PGM
CE
CE
CE
CE
AO
AO
AO
AO
AO
AO- 10
19
-Or
07
07
07
07
D7
00
00
00
00
00
00- 11
18 -06
06
06
06
06
06
Os
01
01
01
01
01
0,- 12
17 -06
Os
Os
Os
Os
02
02
02
02
02
112- 13
16 - 0 ,
04
04
04
04
04
GND
GND
GND
GND
GND
GND- 14
~D3
03
03
03
03
03
15
TL/017512-2
Nala: Socket compatible EPROM pin configurations are shown In the blocks adjacent to the NMC27C2S6 pins.
Order Number NMC27C256Q
See NS Package Number J28AQ
Commercial Temp Range (O"C to
Vee = 5V ±5%
Parameter/Order Number
+ 70"C)
Commercial Temp Range (O"C to
Vee = 5V ±10%
Parameter/Order Number
Access Time
+ 70"C)
Access Time
NMC27C25SQ17
170
NMC27C256Q200
200
NMC27C256C20
200
NMC27C25SQ250
250
NMC27C256C25
250
NMC27C25SQ300
300
Extended Temp Range (- 40"C to
Vee = 5V ±10%
Parameter/Order Number
+ 85'C)
Military Temp Range (-55'C to
Vee = 5V ±10%
Access Time
Parameter/Order Number
+ 125'C)
Access Time
NMC27C25SQE200
200
NMC27C25SQM250
250
NMC27C25SQE250
250
NMC27C25SQM350
350
NOTE: For plastic DIP and surface mount PLCC package requirements please refer to NMC27C256BN data sheet.
1-S8
COMMERCIAL TEMPERATURE RANGE
Absolute Maximum Ratings
Temperature Under Bias
(Note 1)
Power Dissipation
-10'Cto +80'C
Storage Temperature
-65'C to + 150'C
All Input Voltages with
Respect to Ground (Note 10)
+6.5Vto -0.6V
All Output Voltages with
Respect to Ground (Note 10)
Vee + 1.0V to GND-0.6V
Vpp Supply Voltage with Respect
to Ground During Programming
1.0W
Lead Temperature (Soldering, 10 sec.)
300'C
Vee Supply Voltage with
Respect to Ground
+ 7.0V to -0.6V
Operating Conditions (Note 7)
Temperature Range
+14.0Vto -0.6V
O'Cto +70'C
Vee Power Supply
NMC27C256Q17, 20, 25
NMC27C256Q200, 250, 300
5V ±5%
5V ±10%
READ OPERATION
DC Electrical Characteristics
Symbol
Parameter
Conditions
=
Min
III
Input Load Current
VIN
ILO
Output Leakage Current
VOUT
leel
(Note 9)
Vee Current (Active)
TTL Inputs
CE = VIL, f = 5 MHz
Inputs = VIH orVIL, I/O
lee2
(Note 9)
Vee Current (Active)
CMOS Inputs
CE = GND, f = 5 MHz
Inputs = Vee or GND, I/O
leeSSl
Vee Current (Standby)
TTL Inputs
CE
=
VIH
leeSS2
Vee Current (Standby)
CMOS Inputs
CE
=
Vee
Ipp
Vpp Load Current
Vpp
VIL
Input Low Voltage
-0.1
VIH
Input High Voltage
2.0
VOL1
Output Low Voltage
VOHI
Output High Voltage
VOL2
Output Low Voltage
VOH2
Output High Voltage
Typ
Max
Units
10
p.A
10
p.A
6
20
mA
3
10
mA
0.1
1
mA
0.5
100
p.A
10
p.A
Vee or GND
=
=
Vee or GND, CE
=
=
VIH
0 mA
=
0 mA
Vee
= 2.1 mA
IOH = -400 p.A
IOL = 0 p.A
IOH = 0 p.A
IOL
0.8
V
Vee + 1
V
0.45
V
2.4
V
0.1
V
V
Vee - 0.1
AC Electrical Characteristics
NMC27C256
Symbol
Parameter
Conditions
Q17
Min
tAee
Address to Output Delay
teE
CE to Output Delay
tOE
OE to Output Delay
tDF
OE High to Output Float
teF
CE High to Output Float
tOH
Output Hold from Addresses,
CE or OE, Whichever
Occurred First
= OE =
= VIL
CE = VIL
CE = VIL
OE = VIL
CE = OE =
CE
VIL
OE
Max
Q20,Q200
Q25,Q250
Min
Min
Max
Max
Q300
Min
Units
Max
170
200
250
300
ns
170
200
250
300
ns
75
75
100
120
ns
0
60
0
60
0
60
0
105
ns
0
60
0
60
0
60
0
105
ns
VIL
0
1-69
0
0
0
ns
MILITARY AND EXTENDED TEMPERATURE RANGE
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature Under Bias
Operating Temp Range
-S5·C to + 150"C
Storage Temperature
All Input Voltages with
Respect to Ground (Note 10)
+ S.5V to -0.6V
All Output Voltages with
Respect to Ground (Note 10)
Vee+ 1.0V to GND-O.SV
Vpp Supply Voltage with
Respect to Ground
During Programming
1.0W
Power Dissipation
Lead Temperature (Soldering, 10 sec.)
300·C
Vee Supply Voltage with
Respect to Ground
+7.0Vto -O.SV
Operating Conditions (Note 7)
Temperature Range
NMC27C25S0E200, 250
NMC27C25S0M250, M350
+ 14.0Vto -O.SV
-40·Cto +85·C
- 55·C to + 125·C
5V ±10%
Vee Power Supply
READ OPERATION
DC Electrical Characteristics
Symbol
Parameter
Conditions
Input Load Current
ILO
Output Leakage Current
leel
(Note 9)
Vee Current (Active)
TTL Inputs
lee2
(Note 9)
Vee Current (Active)
CMOS Inputs
leeSBl
Vee Current (Standby)
TTL Inputs
iCCSB2
Vee Current (Standby)
CMOS Inputs
CE
Ipp
Vpp Load Current
Vpp
VIL
Input Low Voltage
VIH
Input High Voltage
VOL1
Output Low Voltage
VOHl
Output High Voltage
VOL2
Output Low Voltage
VOH2
Output High Voltage
Typ
Min
= Vee or GND
VOUT = Vee or GND, CE = VIH
CE = VIL, f = 5 MHz
Inputs = VIH or VIL, 1/0 = 0 mA
CE = GND, f = 5 MHz
Inputs = Vee or GND, 1/0 = 0 mA
CE = VIH
III
Max
= Vee
/LA
10
/LA
S
20
mA
3
10
mA
0.1
1
mA
0.5
100
/LA
= Vee
= 2.1 mA
IOH = -400/LA
IOH = 0/LA
IOH = 0/LA
Units
10
VIN
10
/LA
-0.1
0.8
V
2.0
Vee + 1
V
0.45
IOL
V
V
2.4
0.1
V
V
Vee - 0.1
AC Electrical Characteristics
NMC27C256Q
Symbol
Parameter
Conditions
Min
tAee
Address to Output Delay
teE
CE to Output Delay
toE
DE to Output Delay
tOF
OE High to Output Float
toH
Output Hold from Addresses,
CE or DE Whichever
Occurred First
teF
CE High to Output Float
E250
M250
E200
= OE = VIL
DE= VIL
CE = VIL
eE = VIL
eE = DE = VIL
CE
0
Max
= VIL
0
1·70
Max
Min
Units
Max
200
250
350
ns
200
250
350
ns
75
100
120
ns
105
ns
SO
0
OE
Min
M350
0
SO
0
0
60
0
0
SO
0
ns
105
ns
z
Capacitance TA = + 25'C, f =
Symbol
Parameter
3:
o
.......
o
1 MHz (Note 2)
I\)
Conditions
Typ
Max
Units
6
12
pF
9
12
pF
I\)
Input Capacitance
COUT
Output Capacitance
VOUT = OV
U1
en
AC Test Conditions
1 TTL Gate and
CL = 100 pF (Note 8)
,;;5 ns
Output Load
Input Rise and Fall Times
Input Pulse Levels
Timing Measurement Reference level
Inputs
Outputs
0.8Vand2V
0.8Vand2V
0.45V to 2.4V
AC Waveforms (Notes 6,7 & 9)
ADDRESSES
CE
--~:g~.
\.
2.0V
O.BV
"
! - - tCE _
DE
OUTPUT
Hi-Z
rr
tOE
(NOTE3)
I
I--tCF -
NOTES 4,5)
'i
2.0V
O.BV
2.0V
).
ADDRESSES VALID
I-
I
...
tOF
NOTES4,5)
--
Hi-Z
VALID OUTPUT
O.BV
t ACC
-(NOTE 3 ) -
... tOHITL/D/7S12-3
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: DE may be delayed up to tACC - toE after the falling edge of CE without impacting tACC.
Note 4: The tDF and tcF compare level is determined as follows:
High to TAl-STATE, the measured VOH1 (DC) - 0.10V;
Low to TAl-STATE, the measured Vall (DC) + 0.10V.
Note 5: TAl-STATE may be attained using OE or CE.
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 ILF ceramic capacitor be used on
every device between Vee and GNO.
Note 7: The outputs must be restricted to VCC
+
1.0V to avoid latch-up and device damage.
Note 8: 1 TTL Gate: IOL ~ 1.6 mA, 10H ~ - 400 p.A.
CL: 100 pF includes fixture capacitance.
Note 9: Vpp may be connected to Vee except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
1-71
CD
Lt)
N
o.....
N
o
::!E
z
Programming Characteristics (Notes 1,2,3 & 4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tAS
Address Setup Time
2
I1s
tOES
OE Setup Time
2
I1s
tvps
Vpp Setup Time
2
I1s
tves
Vee Setup Time
2
I1s
tos
Data Setup Time
2
I1s
tAH
Address Hold Time
0
I1s
tOH
Data Hold Time
2
tOF
Output Enable to Output Float Delay
tpw
Program Pulse Width
tOE
Data Valid from OE
Ipp
Vpp Supply Current During
Programming Pulse
I1s
0
130
ns
10
ms
CE = VIL
150
ns
CE = VIL
PGM = VIL
30
mA
CE = VIL
0.5
0.5
10
rnA
25
30
'C
5.75
6.0
6.25
V
12.2
13.0
13.3
Ice
Vee Supply Current
TA
Temperature Ambient
20
Vee
Power Supply Voltage
Vpp
Programming Supply Voltage
tFR
Input Rise, Fall Time
VIL
Input Low Voltage
5
V
ns
0.0
0.45
V
VIH
Input High Voltage
2.4
4.0
tiN
Input Timing Reference Voltage
0.8
1.5
2.0
V
tOUT
Output Timing Reference Voltage
0.8
1.5
2.0
V
V
Note 1: National's standard product warranty applies only to devices programmed to specifications described herein.
Note 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vee.
Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is t4V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 ,...F capacitor is required across Vpp, Vee to GND to suppress
spurious voltage transients which may damage .the devi,ce.
Note 4: Programming and program verify are tested with the Interactive Program Algorithm, at typical power supply voltages and timings.
Programming Waveforms (Note 3)
ADDRESSES
D
DATA~
ypp
C
ADDRESS N
~
llAH
I-_lor
I-
H1-Z
DA.TA IN STABL£
DATA OUT VALID
ADON
ADO N
~
~
Yee
P~I'I¢W_
-PROGRAM
5.75Y
Iyes
':::..J
~
CE O~Xv
Iw
-IoESj
2V
BE O.8V
1-72
-10[-
---
TL/D17512-4
z
s:
o
Interactive Programming Algorithm Flow Chart
N
......
oN
U'I
Q)
INCREMENT ADDR
TL/D/7512-5
FIGURE 1
1-73
~r-------------------------------------------------------'
1.1)
~
Functional Description
~
DEVICE OPERATION
The six modes of operation of the NMC27C256 are listed in
Table I. It should be noted that all inputs for the six modes
are at TIL levels. The power supplies required are Vee and
Vpp. The Vpp power supply must be at 13.0V during the
three programming modes, and must be at 5V in the other
three modes. The Vee power supply must be at 6V during
the three programming modes, and at 5V in the other three
modes.
::::iii
Z
To most efficiently use these two control lines, it is recommended that CE (pin 20) be decoded and used as the primary device selecting function, while DE (pin 22) be made a
common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low
power standby modes and that the output pins are active
only when data is desired from a particular memory device.
Programming
CAUTION: Exceeding 14V on pin 1 (Vpp) will damage the
NMC27C256.
Initially, and after each erasure, all bits of the NMC27C256
are in the "1" state. Data is introduced by selectively programming "Os" into the desired bit locations. Although only
"Os" will be programmed, both "1s" and "Os" can be presented in the data word. The only way to change a "0" to a
"1" is by ultraviolet light erasure.
The NMC27C256 is in the programming mode when the Vpp
power supply is at 13.0V and DE is at VIH. It is required that
at least a 0.1 /-tF capacitor be placed across Vpp, Vee to
ground to suppress spurious voltage transients which may
damage the device. The data to be programmed is applied 8
bits in parallel to the data output pins. The levels required
for the address and data inputs are TIL.
When the address and data are stable, an active low TIL
program pulse is applied to the CE/PGM input. A program
pulse must be applied at each address location to be programmed. Any location may be programmed at any timeeither individually, sequentially, or at random. The
NMC27C256 is designed to be programmed with interactive
programming, where each address is programmed with a
series of 0.5 ms pulses until it verifies (up to a maximum of
20 pulses or 10 ms). The NMC27C256 must not be programmed with a DC signal applied to the CE/PGM input.
Programming multiple NMC27C256s in parallel with the
same data can be easily accomplished due to the simplicity
of the programming requirements. Like inputs of the paralleled NMC27C256s may be connected together when they
are programmed with the same data. A low level TIL pulse
applied to the CE/PGM input programs· the paralleled
NMC27C256s.
Read Mode
The NMC27C256 has two control functions, both of which
must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be
used for device selection. Output Enable (DE) is the output
control and should be used to gate data to the output pins,
independent of device selection. Assuming that addresses
are stable, address access time (tAee) is equal to the delay
from CE to output (teE). Data is available at the outputs toE
after the falling edge of DE, assuming that CE has been low
and addresses have been stable for at least tAee - tOE.
The sense amps are clocked for fast access time. Vee
should therefore be maintained at operating voltage during
read and verify. If Vee temporarily drops below the spec.
voltage (but not to ground) an address transition must be
performed after the drop to ensure proper output data.
Standby Mode
The NMC27C256 has a standby mode which reduces the
active power dissipation by 99%, from 55 mW to 0.55 mW.
The NMC27C256 is placed in the standby mode by applying
a CMOS high signal to the CE input. When in standby mode,
the outputs are in a high impedance state, independent of
the DE input.
Output OR-Tying
Because NMC27C256s are usually used in larger memory
arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
TABLE I Mode Selection
Pins
OE
(22)
Vpp
(1)
Vee
(28)
Outputs
(11-13,15-19)
VIL
VIL
5V
5V
DOUT
VIH
Don't Care
5V
5V
Hi-Z
Program
VIL
VIH
13.0V
6V
DIN
Program Verify
VIH
VIL
13.0V
6V
DOUT
Mode
CE/PGM
(20)
Read
Standby
Program Inhibit
VIH
VIH
13.0V
6V
Hi-Z
Output Disable
Don't Care
VIH
5V
5V
Hi-Z
1-74
Functional Description
z
o
N
.......
oN
3:
(Continued)
Program Inhibit
Programming multiple NMC27C256s in parallel with different data is also easily accomplished. Except for CE all like
inputs (including OE) of the parallel NMC27C256s may be
common. A TTL low level program pulse applied to an
NMC27C256's CE/PGM input with Vpp at 13.0V will program that NMC27C256. A TTL high level CE input inhibits
the other NMC27C256s from being programmed.
Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with Vpp at 13.0V. Vpp must be at
Vee, except during programming and program verify.
ERASURE CHARACTERISTICS
The erasure characteristics of the NMC27C256 are such
that erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000A-4000A
range.
After programming, opaque labels should be placed over
the NMC27C256's window to prevent unintentional erasure.
Covering the window will also prevent temporary functional
failure due to the generation of photo currents.
The recommended erasure procedure for the NMC27C256
is exposure to short wave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV
intensity x exposure time) for erasure should be a minimum
of 15W-sec/cm2.
The NMC27C256 should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. Table II
shows the minimum NMC27C256 erasure time for various
light intensities.
An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one inch.
The erasure time increases as the square of the distance. (If
distance is doubled the erasure time increases by a factor of
4.) Lamps lose intensity as they age. When a lamp is
changed, the distance has changed or the lamp has aged,
the system should be checked to make certain full erasure
is occurring. Incomplete erasure will cause symptoms that
can be misleading. Programmers, components, and even
system designs have been erroneously suspected when incomplete erasure was the problem.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer-the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 J.LF ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capaCitor of low inherent
inductance. In addition, at least a 4.7 J.LF bulk electrolytic
capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
TABLE II. Minimum NMC27C256 Erasure Time
Light Intensity
(Micro-Watts/cm2)
Erasure Time
(Minutes)
15,000
20
10,000
25
5,000
50
1-75
(Jt
0)
~National
~
PRELIMINARY
Semiconductor
NMC27C256B High Speed Version
262, 144-Bit (32k x 8) UV Erasable CMOS PROM
General Description
Features
The NMC27C256B is a high-speed 256k UV erasable and
electrically reprogrammable CMOS EPROM, ideally suited
for applications where fast turnaround, pattern experimentation and low power consumption are important requirements.
The NMC27C256B is designed to operate with a single
+5V power supply with ±5% or ±10% tolerance. The
CMOS design allows the part to operate over extended and
military temperature ranges.
The NMC27C256B is packaged in a 28-pin dual-in-line
package with transparent lid. The transparent lid allows the
user to expose the chip to ultraviolet light to erase the bit
pattern. A new pattern can then be written electrically into
the device by following the programming procedure.
This EPROM is fabricated with National's proprietary, time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low power consumption and excellent reliability.
• Clocked sense amps for fast access time down to
150 ns
• Low CMOS power consumption
- Active power: 110 mW max
- Standby power: 0.55 mW max
• Optimal EPROM for total CMOS systems
• Extended temperature range
(NMC27C256BOE),
-40·C to + 85·C, and military temperature range
(NMC27C256BOM), - 55·C to + 125·C available
• Pin compatible with NMOS 256k EPROMs
• Fast and reliable programming-l00 p.s typical/byte
• Static operation-no clocks required
• TTL, CMOS compatible inputs/outputs
• TRI-STATE@ output
• Manufacturer's identification code for automatic programming control
• High current CMOS level output drivers
Block Diagram
Vcco--+
IIIIDo--+
Pin Names
OUTPUT
BUFFERS
Y GATlla
A11-A1.
ADDRESS
.IPUTS
2t2.144·ln
CELL MATRIX
TLlD/9125-1
1·76
AO-AI4
Addresses
CE
Chip Enable
OE
Output Enable
00-0 7
Outputs
PGM
Program
NC
No Connect
z
s:
(')
Connection Diagram
I\)
......
NMC27C256BQ
Dual-In-Line Package
27C512 27C128 27C64 27C32 27C16
27512 2712B 2764 2732 2716
27C16
2716
A15
A12
A7
A6
AS
Vpp
Vpp
v,,-
1
211-V"
A12
A7
A6
AS
012- 2
0'- 3
2'1- 0"
26 -0"
06- •
25- ..
A4
A4
A3
A2
Al
AO
A3
A2
Al
AO
A12
A7
A6
A5
A4
AS
A2
Al
AO
00
00
A7
AS
A5
A7
AS
AS
A4
A4
A3
A2
Al
AO
A3
A2
Al
AO
00
00
27C32 27C64 27C12B 27C512
2732
2764 2712B 27512
Vee
PGM
Vee
PGM
A13
AS
A9
All
A14
A13
AS
A9
All
Vee
Vee
NC
AS
A9
All
Vee
.5- 5
2' -At
AB
A9
"-6
23-011
Vpp
AS
A9
All
A3- ,
22-111
OE
OElVpp
OE
OE
OElVpp
.\2-1
21~010
Al0
Al0
Al0
Al0
Al0
01- •
20 f-II
CE/PGM
"Of:
CE
"Of:
CE
AO- 10
,. f-o,
07
07
07
07
07
00
00- 11
" f-o,
Os
Os
06
Os
Os
"1-0,
Os
Os
05
Os
05
04
04
04
04
04
03
03
03
03
03
0,
0,
0,
0,
0,
0.- 12
02
02
02
02
02
0,- 13
GND
GND
GND
GND
GND
" 1-14
QOD- "
" 1-0,
TL/D/912S-2
Note: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMC27C2S68 pins.
Order Number NMC27C256BQ
See NS Package Number J28AQ
Commercial Temp Range (O"C to
VCC = 5V ±5%
Parameter/Order Number
+ 70"C)
Commercial Temp Range (O'C to
VCC = 5V ±10%
Access Time (ns)
Parameter/Order Number
+ 70"C)
Access Time (ns)
NMC27C256BQ15
150
NMC27C256BQ150
150
NMC27C256BQ20
200
NMC27C256BQ200
200
NMC27C256BQ25
250
NMC27C256BQ250
250
Extended Temp Range (- 40"C to
VCC = 5V ±10%
Parameter/Order Number
+ 85'C)
Military Temp Range (- 55'C to
VCC = 5V ±10%
Access Time (ns)
Parameter/Order Number
+ 125'C)
Access Time (ns)
NMC27C256BQE150
150
NMC27C256BQM150
150
NMC27C256BQE200
200
NMC27C256BQM200
200
NOTE: For plastiC DIP and surface mount PLCC package requirements please refer to NMC27C256BN data sheet.
1-77
(')
I\)
U1
en
IXI
COMMERCIAL TEMPERATURE RANGE
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature Under Bias
-10"C to +80·C
-65·C to + 150·C
Storage Temperature
Vee Supply Voltages with
Respect to Ground
All Input Voltages except A9 with
Respect to Ground (Note 10)
All Output Voltages with
Respect to Ground (Note 10)
Vpp Supply Voltage and A9
with Respect to Ground
+ 14.0V to - 0.6V
Power Dissipation
Lead Temperature (Soldering. 10 sec.)
ESD Rating
(Mil Spec 883C. Method 3015.2)
1.0W
300·C
2000V
+ 7.0V to -0.6V
Operating Conditions (Note 6)
+6.5Vto -0.6V
O·Cto +70·C
Temperature Range
Vcc Power Supply
NMC 27C256BQ15, 20, 25
NMC 27C256BQ150, 200, 250
Vcc+ 1.0V to GND-0.6V
+5V ±5%
+5V ±10%
READ OPERATION
DC Electrical Characteristics
Symboi
Parameter
Conditions
Typ
Min
Max
Units
III
Input Load Current
VIN = Vee or GND
1.0
/LA
IlO
Output Leakage Current
VOUT = Vee or GND, CE = VIH
1.0
/LA
ICC1
(Note 9)
Vee Current (Active)
TTL Inputs
CE = Vll, f = 5 MHz
All Inputs = VIH or Vil. I/O = 0 mA
15
30
rnA
ICC2
(Note 9)
Vcc Current (Active)
CMOS Inputs
CE = GND,f = 5MHz
All Inputs = Vcc or GND, I/O = 0 rnA
10
20
rnA
ICCSB1
Vee Current (Standby)
TTL Inputs
CE = VIH
0.1
1
rnA
ICCSB2
Vcc Current (Standby)
CMOS Inputs
CE = Vee
0.5
100
/LA
Ipp
Vpp Load Current
Vpp = Vee
10
/LA
VIL
Input Low Voltage
-0.2
0.8
V
VIH
Input High Voltage
2.0
Vcc + 1
V
VOL1
Output Low Voltage
IOl = 2.1 rnA
0.40
V
VOH1
Output High Voltage
IOH = -2.5mA
VOL2
Output Low Voltage
IOl = 10/LA
VOH2
Output High Voltage
IOH = -10/LA
3.5
V
0.1
V
Vee - 0.1
V
AC Electrical Characteristics
NMC27C256B
Symbol
Parameter
Conditions
Q15,Q150
Min
Max
Q20,Q200
Min
Max
Q25,Q250
Min
Units
Max
tACC
Address to Output Delay
CE = OE = VIL
150
200
250
ns
teE
toE
CE to Output Delay
OE = Vil
150
200
250
ns
OE to Output Delay
CE = VIL
60
75
100
ns
tDF
OE High to Output Float
CE = Vil
0
50
0
55
60
ns
tCF
CE High to Output Float
OE = Vil
0
50
0
55
60
ns
tOH
Output Hold from Addresses,
CE or OE, Whichever
Occurred First
CE = OE = VIL
0
1-78
0
0
0
ns
z
:s:
MILITARY AND EXTENDED TEMPERATURE RANGE
Absolute Maximum Ratings
o
N
.......
o
(Note 1)
N
U1
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Temp. Range
Temperature Under Bias
Vpp Supply Voltage and A9
with Respect to Ground
Power Dissipation
Lead Temperature (Soldering, 10 sec.)
1.0W
300'C
Storage Temperature
Vee Supply Voltages with
Respect to Ground
ESD Rating
(Mil Spec 883C, Method 3015.2)
2000V
-65'Cto + 150'C
+ 14.0V to - 0.6V
+7.0Vto -0.6V
Operating Conditions (Note 6)
All Input Voltages except A9 with
+6.5Vto -0.6V
Respect to Ground (Note 10)
All Output Voltages with
Respect to Ground (Note 10) Vee + 1.0V to GND-0.6V
5V ±10%
Vee Power Supply
Temperature Range
NMC27C256BQE150, 200
NMC27C256BQM 150, 200
-40'Cto +85'C
-55'C to + 125'C
READ OPERATION
DC Electrical Characteristics
Symbol
Max
Units
III
Input Load Current
Parameter
VIN = Vee or GND
Conditions
Min
Typ
10
/LA
ILO
Output Leakage Current
VOUT = Vcc or GND, CE = VIH
10
/LA
Ice1
(Note 9)
Vec Current (Active)
TTL Inputs
CE = VIL, f = 5 MHz
All Inputs = VIH or VIL, 1/0 = 0 mA
15
30
mA
ICC2
(Note 9)
Vce Current (Active)
CMOS Inputs
CE = GND, f = 5 MHz
All Inputs = Vec or GND, 110 = 0 mA
10
20
mA
ICCSB1
Vcc Current (Standby)
TTL Inputs
CE = VIH
0.1
1
mA
leeSB2
Vec Current (Standby)
CMOS Inputs
CE = Vcc
0.5
100
/LA
Vpp = Vec
Ipp
Vpp Load Current
10
/LA
VIL
Input Low Voltage
. -0.2
0.8
V
VIH
Input High Voltage
2.0
Vec + 1
V
VOL1
Output Low Voltage
0.40
V
VOH1
Output High Voltage
IOH = -1.6mA
VOL2
Output Low Voltage
IOL= 10/LA
VOH2
Output High Voltage
IOH = -10/LA
IOL = 2.1 mA
3.5
V
0.1
V
V
Vec - 0.1
AC Electrical Characteristics
NMC27C256B
Symbol
Parameter
QE150,
QM150
Conditions
Min
QE200,
QM200
Max
Min
Units
Max
tAce
Address to Output Delay
CE = OE = VIL
150
200
tCE
CE to Output Delay
OE = VIL
150
200
ns
toE
OE to Output Delay
CE = VIL
60
75
ns
tOF
OE High to Output Float
CE = VIL
0
50
0
55
ns
tCF
CE High to Output Float
OE = VIL
0
50
0
55
ns
toH
Output Hold from Addresses,
CE or OE, Whichever
Occurred First
CE = OE = VIL
0
1-79
0
ns
ns
Q)
m
III
CD
~
~
N
o
:i
z
Capacitance T A= + 25°C, f =
Symbol
Parameter
1 MHz (Note 2)
Typ
Max
Units
CIN
Input Capacitance
Conditions
VIN = OV
6
12
pF
COUT
Output Capacitance
VOUT = OV
9
12
pF
AC Test Conditions
Output Load
1 TTL Gate and
CL = 100 pF (Note 8)
Input Rise and Fall Times
TIming Measurement Reference Level
Inputs
Outputs
:5:5 ns
Input Pulse Levels
0.8Vand2V
0.8V and 2V
0.45V to 2.4V
AC Waveforms (Notes 6, 7 & 9)
ADDRESSES VALID
ADDRESSES
CE
2.0V
O.BV
DE
2.0V
O.BV
2.0V
OUTPUT O.BV
VALID OUTPUT
tACC
(NOTE 3)
TLlD/9125-3
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: DE may be delayed up to tAee - toE aiter the falling edge of CE without impacting tAOO
Note 4: The tOF and tcF compare level is determined as follows:
High to TRI·STATE, the measurad VOH' (DC) - O.IOV;
Low to TRI·STATE, the measured VOL1 (DC) + 0.10V.
Note 5: TRI-STATE may be aHained using OE or CE.
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 ,..F ceramic capacitor be used on
every device between Vee and GND.
Note 7: The outputs must be restricted to Vee
+
1.0V to avoid latch·up and device damage.
Note 8: 1 TTL Gate: IOL ~ 1.6 mA, IOH ~ - 400 ,..A.
CL: 100 pF includes fixture capacitance.
Note 9: Vpp may be connected to Vee except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
1-80
Programming Characteristics (Notes 1. 2. 3 & 4)
Symbol
Parameter
Conditions
Min
tAs
Address Setup Time
1
toES
OE Setup Time
1
tos
Data Setup Time
1
tvps
Vpp Setup Time
1
tves
Vee Setup Time
1
tAH
Address Hold Time
0
tOH
Data Hold Time
1
tOF
Output Enable to Output Float Delay
0
tpw
Program Pulse Width
95
toE
Data Valid from OE
Ipp
Vpp Supply Current During
Programming Pulse
Typ
Max
Units
fLs
fLs
fLs
fLs
fLs
fLs
fLs
60
100
ns
105
fLs
OE = VIL
100
ns
CE = VIL
OE = VIH
30
mA
Icc
Vee Supply Current
10
mA
TA
Temperature Ambient
20
25
30
'C
Vee
Power Supply Voltage
6.0
6.25
6.5
V
Vpp
Programming Supply Voltage
12.5
12.75
13.0
V
tFR
Input Rise. Fall Time
VIL
Input Low Voltage
0.0
0.45
VIH
Input High Voltage
2.4
4.0
tiN
Input Timing Reference Voltage
0.8
1.5
2.0
V
toUT
Output Timing Reference Voltage
0.8
1.5
2.0
V
5
ns
V
V
Programming Waveforms
P~~~I'I¢~-
PROGRAM
ADDRESSES
lr:)
zy
DATA~
ADDRESS N
1
~
I~
I---- tor
6.0'1
tvcs
Vpp~
-
tAli
DATA OUT VAUD
ADD N
~
~
Vee
HI-Z
DATA IN SlABLE
ADD N
K:
.n
•
~
ZV
CE O.8Y
t
OE
~loEsj -10[-
Zy
1\
O.BY
J
TL/D/BI25-5
Nole 1: National's standard product warranty applies only to devices programmed to specifications described herein.
Nole 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or aher Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vee.
Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 "F capacitor is required across Vpp, Vee to GND to suppress
spurious voltage transients which may damage the device.
Note 4: Programming and program verity are tested with the fast Program AlgOrithm, at typical power supply voltages and timings.
1·81
m
~
Fast Programming Algorithm Flow Chart (Note 4)
~
C"I
o
::E
z
INCREMENT ADDR
TL/0/9125-7
FIGURE 1
1·82
,--------------------------------------------------------------------------, z
i!l:
Interactive Programming Flow Chart (Note 4)
n
N
......
n
N
CI1
Q)
OJ
INCREMENT ADDR
TLlD/9125-6
FIGURE 2
1-83
Functional Description
DEVICE OPERATION
b) complete assurance that output bus contention will not
occur.
The six modes of operation of the NMC27C256B are listed
in Table I. It should be noted that all inputs for the six modes
are at TTL levels. The power supplies required are Vee and
Vpp. The Vpp power supply must be at 12.75V during the
three programming modes, and must be at 5V in the other
three modes. The Vee power supply must be at 6.25V duro
ing the three programming modes, and at 5V in the other
three modes.
To most efficiently use these two control lines, it is recom·
mended that CE (pin 20) be decoded and used as the pri·
mary device selecting function, while OE (pin 22) be made a
common connection to all devices in the array and connect·
ed to the READ line from the system control bus. This as·
sures that all deselected memory devices are in their low
power standby modes and that the output pins are active
only when data is desired from a particular memory device.
Read Mode
Programming
The NMC27C256B has two control functions, both of which
must be logically active in order to obtain data at the out·
puts. Chip Enable (CE) is the power control and should be
used for device selection. Output Enable (OE) is the output
control and should be used to gate data to the output pins,
independent of device selection. Assuming that addresses
are stable, address access time (tAee! is equal to the delay
from CE to output (teE). Data is available at the outputs toE
after the falling edge of OE, assuming that CE has been low
and addresses have been stable for at least tAee - toE.
CAUTION: Exceeding 14V on pin 1 (Vpp) will damage the
NMC27C256B.
Initially, and after each erasure, all bits of the NMC27C256B
are in the "1" state. Data is introduced by selectively pro·
gramming "Os" into the desired bit locations. Although only
"Os" will be programmed, both "1s" and "Os" can be pres·
ent in the data word. The only way to change a "0" to a "1"
is by ultraviolet light erasure.
The NMC27C256B is in the programming mode when the
Vpp power supply is at 12.75V and OE is at VIH. It is reo
quired that at least a 0.1 /LF capacitor be placed across
Vpp, Vee to ground to suppress spurious voltage transients
which may damage the device. The data to be programmed
is applied 8 bits in parallel to the data output pins. The levels
required for the address and data inputs are TTL.
The sense amps are clocked for fast access time. Vee
should therefore be maintained at operating voltage during
read and verify. If Vee temporarily drops below the spec.
voltage (but not to ground) an address transition must be
performed after the drop to insure proper output data.
Standby Mode
When the address and data are stable, an active low, TTL
program pulse is applied to the CE input. A program pulse
must be applied at each address location to be pro·
grammed. The NMC27C256B is programmed with the Fast
Programming Algorithm shown in Figure 1. Each Address is
programmed with a series of 100 /Ls pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
program with a single 100 /Ls pulse. The NMC27C256B
must not be programmed with a DC signal applied to the CE
input.
Note: Some programmer manufactures due to equipment limitation may 01fer interactive program AlgOrithm (shown In Figure 2).
The NMC27C256B has a standby mode which reduces the
active power dissipation by over 99%, from 110 mW to
0.55 mW. The NMC27C256B is placed in the standby mode
by applying a CMOS high signal to the CE input. When in
standby mode, the outputs are in a high impedance state,
independent of the OE input.
Output OR-Tying
Because NMC27C256Bs are usually used in larger memory
arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
a) the lowest possible memory power dissipation, and
TABLE I. Mode Selection
Mode
Pins
CE
(20)
Read
Standby
Output Disable
OE
(22)
Vp
(1)
Vee
(28)
Outputs
(11-13,15-19)
VIL
VIL
5V
5V
DOUT
VIH
Don't Care
5V
5V
Hi·Z
Hi·Z
Don't Care
VIH
5V
5V
Program
VIL
VIH
12.75V
6.25V
DIN
Program Verify
VIH
VIL
12.75V
6.25V
DOUT
Program Inhibit
VIH
VIH
12.75V
6.25V
Hi·Z
1-84
z
==
Functional Description (Continued)
Programming multiple NMC27C2568s in parallel with the
same data can be easily accomplished due to the simplicity
of the programming requirements. Like inputs of the paralleled NMC27C2568 may be connected together when they
are programmed with the same data. A low level TTL pulse
applied to the CE input programs the paralleled
NMC27C2568.
(A). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000A-4000A
range. After programming, opaque labels should be placed
over the NMC27C2568 window to prevent unintentional
erasure. Covering the window will also prevent temporary
functional failure due to the generation of photo currents.
The
recommended
erasure
procedure
for
the
NMC27C2568 is exposure to short wave ultraviolet light
which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure
should be a minimum of 15W-sec/cm2.
Program Inhibit
Programming multiple NMC27C2568s in parallel with different data is also easily accomplished. Except CE, all like
inputs (including OE) of the parallel NMC27C2568s may be
common. A TTL low level program pulse applied to an
NMC27C2568 CE input with Vpp at 12.75V will program that
NMC27C2568. A TTL high level CE input inhibits the other
NMC27C2568s from being programmed.
The NMC27C2568 should be placed within 1 inch of the
lamp tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. Table III
shows the minimum NMC27C2568 erasure time for various
light intensities.
An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one inch.
The erasure time increases as the square of the distance. (If
distance is doubled the erasure time increases by a factor of
4.) Lamps lose intensity as they age. When a lamp is
changed, the distance has changed, or the lamp has aged,
the system should be checked to make certain full erasure
is occurring. Incomplete erasure will cause symptoms that
can be misleading. Programmers, components, and even
system designs have been erroneously suspected when incomplete erasure was the problem.
Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with Vpp at 12.75V. Vpp must be at
Vee except during programming and program verify.
Manufacturer's Identification Code
The NMC27C2568 has a manufacturer's identification code
to aid in programming. When the device is inserted in an
EPROM programmer socket, the programmer reads the
code and then automatically calls up the specific programming algorithm for the part. This automatic programming
control is only possible with programmers which have the
capability of reading the code.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, ICC,
has three segments that are of interest to the system designer-the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 j.LF ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 j.LF bulk electrolytic
capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
The Manufacturer's Identification code, shown in Table II,
specifically identifies the manufacturer and the device type.
The code for NMC27C2568 is "8F04", where "SF" designates that it is made by National Semiconductor, and "04"
designates a 256k part.
The code is accessed by applying 12.0V ± 0.5V to address
pin A9. Addresses A 1-AS, A 1O-A 14, and all control pins
are held at VIL. Address pin AO is held at VIL for the manufacturer's code, and held at VIH for the device code. The
code is read on the eight data pins, 00-07. Proper code
access is only guaranteed at 25°C ± 5°C.
ERASURE CHARACTERISTICS
The erasure characteristics of the NMC27C2568 are such
that erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms
TABLE II. Manufacturer's Identification Code
Pins
AO
(10)
07
(19)
0&
(18)
Os
(17)
04
(16)
03
(15)
02
(13)
01
(12)
00
(11)
Hex
Data
Manufacturer Code
VIL
1
0
0
0
1
1
1
1
SF
Device Code
VIH
0
0
0
0
0
1
0
0
04
TABLE III. Minimum NMC27C256B Erasure Time
Light Intensity
(Mlcro-Watts/cm2)
Erasure Time
(Minutes)
15,000
20
10,000
25
5,000
50
1-S5
fJ
~
en
m
z ,-------------------------------------------------------------------,
lEI
iQ
o
B
I
~
~
National
Semiconductor
PRELIMINARY
NMC27C256BN
High Speed Version 262, 144-Bit (32k x 8)
One-Time Programmable CMOS PROM
General Description
Features
The NMC27C256BN is a high-speed 256k one-time programmable CMOS PROM, ideally suited for applications
where fast turnaround and low power consumption are important requirements.
• Clocked sense amps for fast access time down to
150 ns
• Low CMOS power consumption
- Active power: 110 mW max
- Standby power: 0.55 mW max
• Pin compatible with NMOS 256k EPROMs
• Fast and reliable programming-100 p.s typical/byte
• Static operation-no clocks required
• TTL, CMOS compatible inputs/outputs
• TRI-STATE@ output
• Optimum EPROM for total CMOS systems
• Manufacturer's identification code for automatic programming control
• High current CMOS level output drivers
The NMC27C256BN is designed to operate with a single
+ 5V power supply with ± 5% or ± 10% tolerance.
The NMC27C256BN is packaged in a 28-pin dual-in-line
plastic molded package without a transparent lid. This part
is ideally suited for high volume production applications
where cost is an important factor and programming only
needs to be done once. Also the plastic molded package
works well in auto insertion equipment used in automated
assembly lines.
This EPROM is fabricated with National's proprietary, time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low power consumption and excellent reliability.
Block Diagram
IIATA OUTPUTB IIt-07
Vcco--+
8NDo--+
Pin Names
OUTPUT
BUFFERS
Y OATlNG
A11-A1.
ADDRESS
INPUTS
HZ.144-IIT
CELL MATRIX
TL/O/9691-1
1-86
AO-A14
Addresses
CE
Chip Enable
OE
Output Enable
0 0- 0 7
Outputs
PGM
Program
NC
No Connect
z
iii:
n
I\)
Connection Diagram
27C512 27C128 27C64 27C32 27C16
27512 27128 2764 2732 2716
A15
A12
A7
A6
A5
Vpp
A12
A7
A6
A5
Vpp
A12
A7
A6
A5
A7
A6
A5
A7
A6
A5
......
NMC27C256BN
Dual-In-Llne Package
V,,-1
" -AI<
A7- 3
" -A13
AS-.
"
-AI
"-AI
AS-5
AI-'
A4
A4
A4
A4
A4
A3
A2
Al
AO
A3
A2
Al
AO
A3
A2
Al
AO
A3
A2
Al
AO
A3
A2
Al
AO
A3-7
AO- ,.
19 .... 0,
00
01
02
00
01
02
00
01
02
00
01
02
00
01
02
Oa- 11
11-0,
GND
GND
GND
GND
GND
" -A11
"-01
A2-'
" -AI.
,. _l!
Al- •
. , _ 12
17
r-o,
" 1-..
• , - 13
I<
15
27C32 27C64 27C128 27C512
2732 2764 27128 27512
Vee
PGM
NC
Vee
Vee
A8
A8
A8
A9
A9
A9
Vpp
All
All
OE
OElVpp OE
Al0
Al0
Al0
CE/PGM CE
CE
" -Vee
A12- ,
••• -
27C16
2716
f-o,
07
06
07
06
07
06
07
06
Os
Os
Os
Os
Os
04
03
04
03
04
03
04
03
04
03
Nole: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMC27C256BN pins.
Order Number NMC27C256BN
See NS Package Number N28B
Parameter/Order Number
+ 70'C)
Access Time (ns)
NMC27C256BN15
150
NMC27C256BN20
200
NMC27C256BN25
250
Commercial Temp Range (O'C to
Vee = 5V ± 10%
Parameter/Order Number
+ 70'C)
Access Time (ns)
NMC27C256BN150
150
NMC27C256BN200
200
NMC27C256BN250
250
Nole: For non-commercial temperature range parts, call factory.
Extended Temp. Range (- 40'C to
Vee = 5V ±5%
Parameter/Order Number
+ 85'C)
Access Time (ns)
NMC27C256BNE15
150
NMC27C256BNE20
200
NMC27C256BNE25
250
Extended Temp Range (-40'C to
Vee = 5V ± 10%
Parameter/Order Number
+ 85'C)
Access Time (ns)
NMC27C256BNE150
150
NMC27C256BNE200
200
NMC27C256BNE250
250
1-87
Vee
A14
A13
A8
A9
All
OElVpp
Al0
CE
07
06
TUD/9691-2
Commercial Temp Range (O'C to
Vee = 5V ± 5%
Vee
PGM
A13
A8
A9
All
OE
Al0
CE
n
I\)
U1
en
m
z
Z
ID
!
z
Absolute Maximum Ratings (Note 1)
Temperature Under Bias
-10·Cto +80·C
-65·C to + 150"C
Storage Temperature
All Input Voltages except A9 with
Respect to Ground (Note 10)
All Output Voltages with
Respect to Ground (Note 10)
Vcc Supply Voltage
with Respect to Ground
Lead Temperature (Soldering, 10 sec.)
+6.5Vto -0.6V
ESD Rating
(Mil Spec 88SC, Method S015.2)
Vcc+ 1.0V to GND-0.6V
Vpp Supply Voltage and A9 with
Respect to Ground
2000V
Operating Conditions (Note 6)
O·Cto +70·C
Temperature Range
Vee Power Supply
NMC27C256BN15, 20, 25
NMC27C256BN150, 200, 250
+ 14.0V to -0.6V
Power Dissipation
+7.0Vto -0.6V
SOO·C
1..0W
+5V ±5%
+5V ±10%
READ OPERATION
DC Electrical Characteristics
Symbol
Parameter
Conditions
Typ
Min
Max
Units
III
Input Load Current
VIN = Vcc or GND
1
p.A
ILO
Output Leakage Current
VOUT = Vcc or GND, CE = VIH
1
p.A
ICCl
(Note 9)
Vee Current (Active)
TIL Inputs
CE = VIL, f = 5 MHz
Inputs = VIH or VIL, I/O = 0 mA
15
SO
mA
ICC2
(Note 9)
Vee Current (Active)
CMOS Inputs
CE = GND, f = 5 MHz
Inputs = Vee or GND, I/O = 0 mA
10
20
mA
IccSBl
Vcc Current (Standby)
TIL Inputs
CE = VIH
0.1
1
mA
IccSB2
Vcc Current (Standby)
CMOS Inputs
CE = Vee
0.5
100
/LA
Vpp = Vee
Ipp
Vpp Load Current
10
/LA
VIL
Input Low Voltage
-0.2
0.8
V
VIH
Input High Voltage
2.0
Vcc + 1
V
0.40
V
VOLl
Output Low Voltage
VOHl
Output High Voltage
IOH = -2.5mA
VOL2
Output Low Voltage
IOL = 10 p.A
VOH2
Output High Voltage
IOH= -10p.A
IOL = 2.1 mA
S.5
V
0.1
V
V
Vee- 0.1
AC Electrical Characteristics
NMC27C256B
Symbol
Parameter
N15, N150
Conditions
Min
Max
N20,N200
Min
Max
N25,N250
Min
Units
Max
tACC
Address to Output Delay
CE = OE = VIL
150
200
250
ns
tee
CE to Output Delay
OE = VIL
150
200
250
ns
toe
OE to Output Delay
CE =
60
75
100
ns
tOF
OE High to Output Float
CE = VIL
0
50
0
55
0
60
ns
teF
CE High to Output Float
OE= VIL
0
50
0
55
0
60
ns
toH
Output Hold from Addresses,
CE or OE, Whichever
Occurred First
CE = OE = VIL
VIL
0
1-88
0
0
ns
EXTENDED TEMPERATURE RANGE
Absolute Maximum Ratings (Note 1)
Temperature Under Bias
Storage Temperature
Operating Temp. Range
-65'Cto +150'C
Vee Supply Voltages
with Respect to Ground
All Input Voltages except A9 with
Respect to Ground (Note 10)
All Output Voltages with
Respect to Ground (Note 10)
+7.0Vto -0.6V
300'C
2000V
Operating Conditions (Note 6)
Temperature Range
+6.5Vto -0.6V
-40'C to + 85'C
Vee Power Supply
NMC27C256BNE15, 20, 25
NMC27C256BNE150, 200, 250
Vee + 1.0V to GND-0.6V
Vpp Supply Voltage and A9 with
Respect to Ground
Power Dissipation
Lead Temperature (Soldering, 10 sec.)
ESD Rating
(Mil Spec 883C, Method 3015.2)
+5V ±5%
+5V ±10%
+ 14.0V to - 0.6V
1.0W
READ OPERATION
DC Electrical Characteristics
Symbol
Parameter
Conditions
Typ
Min
Max
Units
III
Input Load Current
VIN = Vee or GND
10
/loA
ILO
Output Leakage Current
VOUT = Vee or GND, CE = VIH
10
/loA
leel
(Note 9)
Vee Current (Active)
TTL Inputs
CE = VIL, f = 5 MHz
All Inputs = VIH or VIL, 1/0 = 0 mA
15
30
mA
lee2
(Nots9)
Vee Current (Active)
CMOS Inputs
CE = GND, f = 5 MHz
All Inputs = Vee or GND, 1/0 = 0 mA
10
20
mA
leeSBl
Vee Current (Standby)
TTL Inputs
CE = VIH
0.1
1
mA
leeSB2
Vee Current (Standby)
CMOS Inputs
CE = Vee
0.5
100
/loA
Vpp = Vee
Ipp
Vpp Load Current
10
/loA
VIL
Input Low Voltage
-0.2
0.8
V
VIH
Input High Voltage
2.0
Vee + 1
V
VOL1
Output Low Voltage
0.40
V
VOHl
Output High Voltage
IOH = -1.6mA
VOL2
Output Low Voltage
IOL=10/loA
VOH2
Output High Voltage
IOH = -10/loA
IOL = 2.1 mA
3.5
V
0.1
Vee - 0.1
V
V
AC Electrical Characteristics
NMC27C256B
Symbol
Parameter
NE20,
NE200
NE15,
NE150
Conditions
Min
Max
Min
Max
NE25,
NE250
Min
Units
Max
tAee
Address to Output Delay
CE = OE = VIL
150
200
250
ns
teE
toE
CE to Output Delay
OE = VIL
150
200
250
ns
OE to Output Delay
CE = VIL
60
75
100
ns
tOF
OE High to Output Float
CE = VIL
0
50
0
55
0
60
ns
teF
CE High to Output Float
OE = VIL
0
50
0
55
0
60
ns
tOH
Output Hold from Addresses,
CE or OE, Whichever
Occurred First
CE = OE = VIL
0
1-89
0
0
ns
Z
ID
~
5
::E
Z
Capacitance TA = + 25'C, f = 1 MHz (Note 2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Typ
Max
Units
= OV
VOUT = OV
5
10
pF
8
10
pF
VIN
AC Test Conditions
1 TTL Gate and
CL = 100 pF (Note 8)
Output Load
Timing Measurement Reference Level
Inputs
Outputs
,5;5 ns
Input Rise and Fall Times
Input Pulse Levels
0.8V and 2V
0.8V and 2V
0.45V to 2.4V
AC Waveforms
(Notes 6,7 & 9)
ADDRESSES
OUTPUT
TUD/9691-3
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification Is not implied. Exposure to absolute
maximum rating condnions for extended periods may affect device reliabilny.
Nota 2: This parameter is only sampled and is not 100% tested.
Nofe 3: OE may be delayed up to tAce -
toe after the falling edge of CE without impacting tAce.
Nota 4: The tOF and IcF compare level Is determined as follows:
High to TRI·STATE, the measured VOHI (DC) - 0.10V;
Low to TRI-SrATE, the measured VOlt (DC) + 0.10V.
Nota 5: TRI-STATE may be attained using OE or GE.
Nole 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 ,.F ceramic capacitor be used on
every device between Vce and GND.
Nota 7: The outputs must be restricted to Vce + 1.0V to avoid latch·up and device damage.
Nole 6: 1 TTL Gate: IOL ~ 1.6 mA, IOH ~ -400,.A.
CL: 100 pF includes fixture capaeftance.
Nota 9: Vpp may be connected to Vce except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
1·90
z
Programming Characteristics (Notes 1, 2, 3 & 4)
Symbol
Parameter
oN==
Conditions
Min
Typ
Max
Units
tAS
Address Setup Time
1
J.Ls
tOES
OE Setup Time
1
J.Ls
tos
Data Setup Time
1
J.Ls
tvps
Vpp Setup Time
1
J.Ls
tves
Vee Setup Time
1
J.Ls
tAH
Address Hold Time
0
J.Ls
tOH
Data Hold Time
1
tOF
Output Enable to Output Float Delay
0
tpw
Program Pulse Width
95
J.Ls
100
60
ns
105
J.Ls
toE
Data Valid from OE
DE = VIL
100
ns
Ipp
Vpp Supply Current During
Programming Pulse
CE = VIL
OE = VIH
30
mA
10
mA
lee
Vee Supply Current
TA
Temperature Ambient
20
25
30
·C
Vee
Power Supply Voltage
6.0
6.25
6.5
V
Vpp
Programming Supply Voltage
12.5
12.75
13.0
tFR
Input Rise, Fall Time
VIL
Input Low Voltage
VIH
Input High Voltage
2.4
4.0
tiN
Input Timing Reference Voltage
0.8
tOUT
Output Timing Reference Voltage
O.B
5
V
ns
0.45
V
1.5
2.0
ns
1.5
2.0
ns
0.0
V
Programming Waveforms
DATA
&-
~
ADDRESS N
1
~
HI-Z
DATA IN STABLE
tAH
DATA OUT VAUD
ADD N
ADD N
~
Vee
pe~~,~M_
PROGRAM
Dl
ADDRESSES O.BY
~
I-
r-
-tor
6.0V
tvcs
12.5V
Vpp:::::........J~
C£
2V
O.8V
t
DE
l-'oES1 -'oE-
,
2V
D.BV
j
TU019691-4
Nole 1: National's standard product warranty applies only 10 devices programmed 10 specificalions described herein.
Nole 2: Vee musl be applied simullaneously or before Vpp and removed simultaneously or after Vpp. The EPROM musl nol be inserted inlo or removed from a
board wilh voltage applied to Vpp or Vee.
Nole 3: The maximum absolule allowable voltage which may be applied 10 Ihe Vpp pin during programming is 14V. Care musl be laken when swilching Ihe Vpp
supply 10 prevenl any overshool from exceeding Ihis 14V maximum specificalion. Alleasl a 0.1 I'F capacilor is required across Vpp, Vee 10 GND 10 suppress
spurious voltage Iransients which may damage Ihe device.
Nole 4: Programming and program verify are lesled wilh Ihe fasl Program Algorilhm, al typical power supply vollages and limings.
1-91
~
N
en
en
m
z
Z
I
r-----------------------------------------------------------------------.
Fast Programming Algorithm Flow Chart (Note 4)
~o
::::&
Z
INCREMENT ADDR
TLl0/9691-5
FIGURE 1
1·92
z
iii:
Interactive Programming Algorithm Flow Chart (Note4)
oN
~
N
en
en
aJ
Z
INCREMENT ADDR
TLlD/9691-6
FIGURE 2
1-93
Functional Description
To most efficiently use these two control lines, it is recommended that CE (pin 20) be decoded and used as the primary device selecting function, while OE (pin 22) be made a
common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low
power standby modes and that the output pins are active
only when data is desired from a particular memory device.
DEVICE OPERATION
The six modes of operation of the NMC27C256BN are listed
in Table I. It should be noted that all inputs for the six modes
are at TTL levels. The power supplies required are Vcc and
Vpp. The Vpp power supply must be at 12.75V during the
three programming modes, and must be at 5V in the other
three modes. The VCC power supply must be at 6.25V during the three programming modes, and at 5V in the other
three modes.
Programming
CAUTION: Exceeding 14V on pin 1 (Vpp) will damage the
NMC27C256BN.
Initially, and after each erasure, all bits of the
NMC27C256BN are in the "1" state. Data is introduced by
selectively programming "Os" into the desired bit locations.
Although only "Os" will be programmed, both "1s" and "Os"
can be presented in the data word. The only way to change
a "0" to a "1" is by ultraviolet light erasure.
Read Mode
The NMC27C256BN has two control functions, both of
which must be logically active in order to obtain data at the
outputs. Chip Enable (CE) is the power control and should
be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output
pins, independent of device selection. Assuming that addresses are stable, address access time (tACe) is equal to
the delay from CE to output (teE). Data is available at the
outputs tOE after the falling edge of OE, assuming that CE
has been low and addresses have been stable for at least
tACC - tOE'
The sense amps are clocked for fast access time. Vcc
should therefore be maintained at operating voltage during
read and verify. If Vee temporarily drops below the spec.
. voltage (but not to ground) an address transition must be
perlormed after the drop to insure proper output data.
The NMC27C256BN is in the programming mode when the
Vpp power supply is at 12.75V and OE is at VIH. It is required that at least a 0.1 ",F capacitor be placed across
Vpp, VCC to ground to suppress spurious voltage transients
which may damage the device. The data to be programmed
is applied 8 bits in parallel to the data output pins. The levels
required for the address and data inputs are TTL.
When the address and data are stable, an active low TTL
program pulse is applied to the CE input. A program pulse
must be applied at each address location to be programmed. The NMC27C256BN is programmed with the
Fast Programming Algorithm shown in Figure 1. Each Address is programmed with a series of 100
pulses until it
verifies good, up to a maximum of 25 pulses. Most memory
cells will program with a single 100
pulse. The
NMC27C256BN must not be programmed with a DC signal
applied to the CE input.
Standby Mode
The NMC27C256BN has a standby mode which reduces
the active power dissipation by over 99%, from 110 mW to
0.55 mW. The NMC27C256BN is placed in the standby
mode by applying a CMOS high signal to the CE input.
When in standby mode, the outputs are in a high impedance
state, independent of the OE input.
"'S
"'S
Note: Some program manufacturers due to equipment limitation may offer
interactive program Algorithm (shown in Figuf6 2).
Output OR-Tying
Because NMC27C256BN are usually used in larger memory
arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
Programming multiple NMC27C256BNs in parallel with the
same data can be easily accomplished due to the simplicity
of the programming requirements. Like inputs of the paralleled NMC27C256BNs may be connected together when
they are programmed with the same data. A low level
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
TABLE I. Mode Selection
Mode
Pins
CE
(20)
Read
Standby
OE
(22)
Vp
(1)
Vee
(28)
Outputs
(11-13,15-19)
VIL
VIL
5V
5V
DOUT
VIH
Don't Care
5V
5V
Hi-Z
Hi-Z
5V
5V
Program
VIL
VIH
12.75V
6.25V
DIN
Program Verify
VIH
VIL
12.75V
6.25V
DOUT
Program Inhibit
VIH
VIH
12.75V
6.25V
Hi-Z
Output Disable
Don't Care
VIH
1-94
z
Functional Description
(Continued)
TTL pulse applied to the CE input programs the paralleled
NMC27C256BNs.
The Manufacturer's Identification code, shown in Table II,
specifically identifies the manufacturer and the device type.
The code for NMC27C256BN is "SF04", where "SF" designates that it is made by National Semiconductor, and "04"
designates a 256k part.
The code is accessed by applying 12.0V ±0.5V to address
pin A9. Addresses At-AS, Al0-AI4, and all control pins
are held at VIL. Address pin AO is held at VIL for the manufacturer's code, and held at VIH for the device code. The
code is read on the eight data pins, 00-07. Proper code
access is only guaranteed at 25'C ± 5'C.
The NMC27C256BN is packaged in a plastic molded package which does not have a transparent lid. Therefore the
memory cannot be erased. This means that after a user has
programmed a memory cell to a "0" it cannot be changed
back to a "I".
If an application requires erasing and reprogramming, the
NMC27C256BQ UV erasable PROM in a windowed package should be used.
Program Inhibit
Programming multiple NMC27C256BNs in parallel with different data is also easily accomplished. Except CE, all like
inputs (including OE) of the parallel NMC27C256BNs may
be common. A TTL low level program pulse applied to an
NMC27C256BNs CE input with Vpp at 12.75V will program
that NMC27C256BN. A TTL high level CE input inhibits the
other NMC27C256BNs from being programmed.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer-the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 p.F ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 ,..F bulk electrolytic
capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with Vpp at 12.75V. Vpp must be at
Vee except during programming and program verify.
Manufacturer's Identification Code
The NMC27C256BN has a manufacturer's identification
code to aid in programming. When the device is inserted in
an EPROM programmer socket, the programmer reads the
code and then automatically calls up the specific programming algOrithm for the part. This automatic programming
control is only possible with programmers which have the
capability of reading the code.
TABLE II. Manufacturer's Identification Code
Pins
AO
(10)
Manufacturer Code
Device Code
o
0&
(18)
05
03
02
(17)
(15)
(13)
o
o
o
o
o
o
1-95
00
(11)
Hex
Data
SF
o
o
o
04
o==
~
~
~
UI
en
m
z
Z
III
U)
in
Packaging Information
N
....o
N
o
==
z
6 SPACES AT
0.050
(1.270)
i
0.551 ±0.002
(14.00±0.051)
0.590±0.005
(14.99±0.127)
VIEW A·A
~:::'--I~
x45°
0.100-0.140
(2.540 -3.556)
t
t
t f
0.060-0.095
(1.524-2.413)
TL/D/9691-7
32-Lead PLCC Package
Order Number NMC27C256
1-96
~National
~
PRELIMINARY
Semiconductor
NMC27C512A
524,288-Bit (64k x 8) UV Erasable CMOS PROM
General Description
Features
The NMC27CS12A is a high-speed S12k UV erasable and
electrically reprogrammable CMOS EPROM, ideally suited
for applications where fast turnaround, pattern experimentation and low power consumption are important requirements.
The NMC27CS12A is designed to operate with a single
+SV power supply with ±S% or ±10% tolerance. The
CMOS design allows the part to operate over extended and
military temperature ranges.
The NMC27CS12A is packaged in a 28-pin dual in-line package with transparent lid. The transparent lid allows the user
to expose the chip to ultraviolet light to erase the bit pattern.
A new pattern can then be written electrically into the device
by following the programming procedure.
This EPROM is fabricated with National's proprietary, time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low power consumption and excellent reliability.
• Clocked sense amps for fast access time down to
1S0 ns
• Low CMOS power consumption
- Active Power: 110 mW max
- Standby Power: O.SS mW max
• Optimum EPROM for total CMOS system
• Extended temperature range
(NMC27CS12AOE),
-40·C to 8S·C, and military temperature range
(NMC27CS12AOM), -SS·C to 12S·C, available
• Pin compatible with NMOS S12k EPROM
• Fast and reliable programming-100 ,""S typical/byte
• Static operation-no clocks required
• TTL, CMOS compatible inputs/outputs
• TRI-STATE® output
• Manufacturer's identification code for automatic programming control.
• High current CMOS level output drivers
Block Diagram
Vcc~
DAta DUTPUTI CIt-07
8/lD~
OUTPUT
IUFFERS
Pin Names
AO-A1S
YIIATIIIII
AD-All
ADDRESS
INPUTS
Addresses
CE
Chip Enable
OElVpp
Output Enable/Programming Voltage
Outputs
Program
I2UIHIT
cnLMATRIX
TL/D/9181-1
1-97
·Connection Diagram
27C256 27C128 27C64 27C32 27C16
27256 27128 2764 2732 2716
Vpp
A12
A7
A6
A5
A4
A3
A2
A1
AO
Vpp
A12
A7
A6
A5
A4
A3
A2
A1
AO
Vpp
A12
A7
A6
A5
A4
A3
A2
A1
AO
A7
A6
A5
A4
A3
A2
A1
AO
A7
A6
A5
A4
A3
A2
A1
AO
00
00
00
00
00
27C16 27C32 27C64 27C128 27C256
2732 2764 27128 27256
2716
NMC27C512AQ
Dual-In-Llne Package
-v..
Al&- 1
2,
A12- 2
2l-A14
.,-,
-,
20 -A13
..
01-'
21_01
A4-.
23 -Al1
03-7
u -RJv"
2. -AI
a-I
" -All
Al- •
.. -1:1
AD- 1.
0,- 11
Vee
PGM
A13
A8
A9
A11
OE
A10
CE
Vcc
PGM
NC
Vee
Vcc
A8
A8
A8
A9
A9
A9
A11
A11
Vpp
OE OElVpp OE
A10
A10
A10
CElVpp CE
CE
Vee
A14
A13
A8
A9
A11
OE
A10
CE
" -0,
11-0,
07
07
07
07
07
Os
Os
Os
Os
Os
01
01
01
01
01
0,-12
17-0,
05
05
05
05
05
02
02
02
02
02
0,- 13
04
04
04
04
04
GND
GND
GND
GND
GND
G'.- "
"-0.
"-Do
03
03
03
03
03
TL/D/9181-2
Order Part Number NMC27C512AQ
See NS Package Number J28AQ
Note: Socket compatible EPROM pin configurations are shown In the blocks adjacent to the NMC27C512A pins.
Commercial Temp Range (O"C to
Vee = 5V ±5%
Parameter/Order Number
+ 70'C)
Commercial Temp Range (O'C to
Vee = 5V ±10%
Access Time (ns)
Parameter/Order Number
+ 70"C)
Access Time (ns)
NMC27C512A015
150
NMC27C512A0150
NMC27C512A017
170
NMC27C512A0170
170
NMC27C512A020
200
NMC27C512A0200
200
NMC27C512A025
250
NMC27C512A0250
250
Extended Temp Range ( - 40"C to
Vee = 5V ±10%
Parameter/Order Number
+ 85'C)
150
Military Temp Range (-55'C to
Vee = 5V ±10%
Access Time (ns)
Parameter/Order Number
+ 125'C)
Access Time (ns)
NMC27C512AOE150
150
NMC27C512AOM150
NMC27C512AOE170
170
NMC27C512AOM170
170
NMC27C512AOE200
200
NMC27C512AOM200
200
NMC27C512AOE250
250
NMC27C512AOM250
250
150
NOTE: For plastic DIP and surface mount PLCC package requirements please refer to NMC27C512AN data sheet.
1·98
z
o==
N
.....
COMMERCIAL TEMPERATURE RANGE
oen
Absolute Maximum Ratings (Note 1)
Temperature Under Bias
Storage Temperature
All Input Voltages except A9 & OElVpp
with Respect to Ground (Note 9)
-10'Cto + BO'C
-65'C to + 150'C
OElVpp Supply Voltage & A9
with Respect to Ground
Power Dissipation
Lead Temperature (Soldering, 10 sec.)
+6.5Vto -0.6V
Vcc Supply Voltage with
Respect to Ground
......
+14.0Vto -0.6V
1.0W
300'C
Operating Conditions (Note 6)
+7.0Vto -0.6V
ESD Rating
(Mil. Std. BB3C, Method 3015.2)
2000V
All Output Voltages with
Respect to Ground (Note 9)
VCC+ 1.0V to GND-0.6V
Temperature Range
O'Cto +70'C
Vcc Power Supply
NMC27C512AQ15, 17, 20, 25
NMC27C512AQ150, 170, 200, 250
5V ±5%
5V ±10%
READ OPERATION
DC Electrical Characteristics
Symbol
Typ
Max
Units
III
Input Load Current
Parameter
VIN = Vcc or GND
Conditions
0,01
1
p.A
ILO
Output Leakage Current
VOUT = Vcc or GND, CE = VIH
0,01
1
p.A
Ipp
Vpp Load Current
OElVpp = Vcc or GND
10
p.A
ICCl
Vcc Current (Active)
TTL Inputs
CE = VIL, f = 5 MHz
Inputs = VIH or VIL, 1/0 = 0 mA
15
30
mA
ICC2
Vcc Current (Active)
CMOS Inputs
CE = GND, f = 5 MHz
Inputs = Vcc or GND, 1/0 = 0 mA
10
20
mA
ICCSBl
Vcc Current (Standby)
TTL Inputs
CE = VIH
0.1
1
mA
ICCSB2
Vcc Current (Standby)
CMOS Inputs
CE = Vcc
0.5
100
p.A
VIL
Input Low Voltage
-0.2
O.B
V
VIH
Input High Voltage
2.0
Vcc + 1
V
VOL1
Output Low Voltage
IOL = 2.1 mA
0.40
V
VOHl
Output High Voltage
IOH = -2.5mA
VOL2
Output Low Voltage
IOL=10p.A
VOH2
Output High Voltage
IOH = -10 p.A
Min
V
3.5
0.1
V
V
Vcc - 0.1
AC Electrical Characteristics
NMC27C512A
Symbol
Parameter
Conditions
Q15,Q150
Q17,Q170
Q20,Q200
Min
Min
Min
Max
Max
Max
Q25,Q250
Min
Units
Max
tACC
Address to Output Delay
CE = OE = VIL
150
170
200
250
ns
tCE
CE to Output Delay
OE = VIL
150
170
200
250
ns
tOE
OE to Output Delay
CE = VIL
60
75
75
100
ns
0
55
0
60
ns
0
55
0
60
ns
tDF
OE High to Output Float
CE = VIL
tCF
CE High to Output Float
OE = VIL
tOH
Output Hold from Addresses,
CE or OE, Whichever
Occurred First
CE = OE = VIL
0
0
0
1-99
50
50
0
0
0
55
55
0
0
ns
~
MILITARY AND EXTENDED TEMPERATURE RANGE
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature Under Bias
Operating Temp. Range
Storage Temperature
+7.0Vto -0.6V
Operating Conditions
+6.5Vto -0.6V
2000V
(Note 6)
Temperature Range
NMC27C256BQE150, 170,200,250
NMC27C256BQM150, 170,200,250
Vee + 1.0V to GND-0.6V
-40'Cto +85'C
- 55'C to + 125'C
Vee Power Supply
+ 14.0Vto -0.6V
Power Dissipation
300'C
ESD Rating
(Mil. Std. 883C, Method 3015.2)
- 65'C to + 150'C
All Input Voltages except A9 & OElVpp
with Respect to Ground (Note 9)
All Output Voltages with
Respect to Ground (Note 9)
OElVpp Supply Voltage & A9
with Respect to Ground
Lead Temperature (Soldering, 10 sec.)
Vee Supply Voltage with
Respect to Ground
+5V ±10%
1.0W
READ OPERATION
DC Electrical Characteristics
Symbol
Parameter
Conditions
Typ
Min
= Vee or GND
Your = Vee or GND, CE = VIH
CE = VIL, f = 5 MHz
Inputs = VIH or VIL, 1/0 = 0 mA
CE = GND, f = 5 MHz
Inputs = Vee or GND, 1/0 = 0 mA
III
Input Load Current
ILO
Output Leakage Current
lee1
Vee Current (Active)
TTL Inputs
lee2
Vee Current (Active)
CMOS Inputs
leeSB1
Vee Current (Standby)
TTL Inputs
CE
= VIH
leeSB2
Vee Current (Standby)
CMOS Inputs
CE
= Vee
OElVpp
Max
Units
10
JJ-A
10
JJ-A
15
30
mA
10
20
mA
0.1
1
mA
0.5
100
JJ-A
VIN
= Vee or GND
Ipp
Vpp Load Current
10
JJ-A
VIL
Input Low Voltage
-0.2
0.8
V
VIH
Input High Voltage
2.0
Vee + 1
V
VOL1
Output Low Voltage
VOH1
Output High Voltage
VOL2
Output Low Voltage
VOH2
Output High Voltage
= 2.1 mA
IOH = -1.6mA
IOL = 10JJ-A
IOH = -10 JJ-A
IOL
0.4
V
3.5
V
0.1
V
Vee - 0.1
V
AC Electrical Characteristics
NMC27C512A
Symbol
Parameter
Conditions
QE150, QM150
Min
tAee
teE
toE
tDF
teF
toH
= OE = VIL
CE to Output Delay
OE = VIL
OE to Output Delay
CE = VIL
OE High to Output Float
CE = VIL
CE High to Output Float
OE = VIL
Output Hold from Addresses, CE = OE = VIL
Address to Output Delay
CE or OE, Whichever
Occurred First
CE
Max
QE170, QM170
Min
Max
QE200, QM200
Min
Max
QE250, QM250 Units
Min
Max
150
170
200
250
ns
150
170
200
250
ns
60
75
75
100
ns
0
50
0
55
0
55
0
60
ns
0
50
0
55
0
55
0
60
ns
0
0
1·100
0
0
ns
z
Capacitance TA = + 25'C, f =
Symbol
s::
n
1 MHz (Note 2)
N
Parameter
Conditions
=
CINI
Input Capacitance
except OElVpp
VIN
Cour
Output Capacitance
Your
CIN2
OElVpp Input
Capacitance
VIN
=
OV
=
OV
OV
......
Typ
Max
Units
n
U'I
6
12
pF
»
9
12
pF
20
25
pF
......
N
AC Test Conditions
Output Load
1 TTL Gate and
CL = 100 pF (Note 8)
Timing Measurement Reference Level
Inputs
Outputs
';;5 ns
Input Rise and Fall Times
Input Pulse Levels
0.8Vand2V
0.8Vand2V
0.45V to 2.4V
AC Waveforms
(Notes 6, 7)
ADDRESSES
2.0'"
ADDRESSES VALID
O.BV)
2.0V
O.8V
OE/Vpp
OUTPUT
\.
I--
2.0V
O.BV
2.0V
HI-Z
"
t CE ____
..
)!
".
j
"
-t CF (HOTE4,5)
I
tOE
(NOTE 3)
VALID OUTPUT
O.BV
t ACC
I - - (NOTE
3)
I+-
----
..
-
tOF
(HOTE4,5)
I+HI-Z
-
tOHI-
TL/D/9'8'-3
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to tAee -
toE aiter the falling edge of CE without impacting tACC.
Note 4: The tDF and tcF compare level is determined as follows:
High to TRI·STATE, the measured VOH' (DC) - 0.10V;
Low to TRI·STATE, the measured VOL1 (DC) + 0.10V.
Note 5: TRI-STATE may be attained using OE or CE.
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 I'F ceramic capacitor be used on
every device between Vee and GND.
Note 7: The outputs must be restricted to Vee
+
1.0V to avoid latch-up and device damage.
Note 8: 1 TIL Gate: 10L ~ 1.6 mA,lOH ~ -400 pA
CL: 100 pF includes fixture capacitance.
Note 9: Inputs and outputs can undershoot to - 2.0V for 20 ns Max.
1-101
Programming Characteristics (Notes 1, 2, 3 and 4)
Symbol
Parameter
Conditions
Min
Max
Typ
Units
tAS
Address Setup Time
1
J.ts
toES
OE Setup Time
1
J.ts
tos
Data Setup Time
1
J.ts
tvcs
Vee Setup Time
1
J.ts
tAH
Address Hold Time
0
J.ts
tOH
Data Hold Time
1
J.ts
tcf
Chip Enable to Output Float Delay
0
OE = VIL
tpw
Program Pulse Width
95
toEH
OE Hold Time
1
tov
Data Valid from CE
tpRT
OE Pulse Rise Time
During Programming
100
Vpp Recovery Time
Ipp
V pp Supply Current During
Programming Pulse
ns
105
J.ts
J.ts
250
OE = VIL
tVR
60
ns
50
ns
1
J.ts
CE = VIL
OE = Vpp
30
mA
Icc
Vcc Supply Current
10
mA
TR
Temperature Ambient
20
25
30
·C
Vee
Power Supply Voltage
6
6.25
6.5
V
Vpp
Programming Supply Voltage
12.5
12.75
13
V
TFR
Input Rise, Fall Time
VIL
Input Low Voltage
0
0.45
VIH
Input High Voltage
2.4
4
tiN
Input Timing Reference Voltage
0.8
1.5
2
V
tOUT
Output Timing Reference Voltage
0.8
1.5
2
V
ns
5
V
V
Nale 1: National's standard product warranty applies 10 devices programmed to specifications described herein.
Nale 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted inlo or removed from a
board wilh voltage applied to Vpp or Vee.
Nale 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least 0.1 /'oF capacitor is required across Vee to GND to suppress spurious
voltage transients which may damage the device.
Nate 4: Programming and program verify are tested with the fast Program Algorithm, at typical power supply voltages and timings.
Programming Waveforms
pe~~I~Iot_
PROGRAM
ADDRESSES
O.8V
~
~
DATA
2V
o:w--
~
OE/Vpp
'~
CE
Va:
....
2V
~o
l-
~
DATA 0U1' VALID ADD N
~
~
~
1\
IoEH
C
VR1
~
F'vCSO.8V
2V
0.8V
HI-Z
DIlTAINSTAa.E
0.8V
tpRT
K=
ADDRESS N
j
6.25V
TLlD/9181-5
1·102
Fast Programming Algorithm Flow Chart (Note 4)
INCREIAENT ADDR
•
TL/D/91Bl-7
FIGURE 1
1-103
I
~
~
Interactive Programming Algorithm Flow Chart (Note 4)
~
o
:::!!
z
'"
INCREMENT ADDR
TLlD/9181-6
FIGURE 2
1·104
z
s::
Functional Description
This assures that all deselected memory devices are in their
low power standby modes and that the output pins are active only when data is desired from a particular memory device.
DEVICE OPERATION
The six modes of operation of the NMC27C512A are listed
in Table I. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for OElVpp during
programming. In the program mode the OElVpp input is
pulsed from a TTL low level to 12.75V.
Programming
CAUTION: Exceeding 14V on pin 22 (OElVpp) will damage
the NMC27C512A.
Initially, and after each erasure, all bits of the NMC27C512A
are in the "1" state. Data is introduced by selectively programming "Os" into the desired bit locations. Although only
"Os" will be programmed, both "ls" and "Os" can be presented in the data word. The only way to change a "0" to a
"1" is by ultraviolet light erasure.
The NMC27C512A is in the programming mode when the
OElVpp is at 12.75V. It is required that at least a 0.1 /LF
capacitor be placed across Vcc and ground to suppress
spurious voltage transients which may damage the device.
The data to be programmed is applied 8 bits in parallel to
the data output pins. The levels required for the address
and data inputs are TTL.
When the address and data are stable, an active low, TTL
program pulse is applied to the CE input. A program pulse
must be applied at each address location to be programmed.
The NMC27C512A is programmed with the Fast Programming Algorithm shown in Figure 1. Each Address is programmed with a series of 100 /Ls pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
Program with a single 100 /Ls pulse.
The NMC27C512A must not be programmed with a DC signal applied to the CE input.
Programming multiple NMC27C512AS in parallel with the
same data can be easily acccomplished due to the simplicity of the programming requirements. Like inputs of the paralleled NMC27C512A may be connected together when
they are programmed with the same data. A low level TTL
pulse applied to the CE input programs the paralleled
NMC27C512A.
Read Mode
The NMC27C512A has two control functions, both of which
must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be
used for device selection. Output Enable (OE) is the output
control and should be used to gate data to the output pins,
independent of device selection. Assuming that addresses
are stable, address access time (tACel is equal to the delay
from CE to output (tCE). Data is available at the outputs after
the falling edge of OE, assuming that CE has been low and
addresses have been stable for at least tACC-toE'
The sense amps are clocked for fast access time. Vcc
should therefore be maintained at operating voltage during
read and verify. If Vcc temporarily drops below the spec.
voltage (but not to ground) an address transition must be
performed after the drop to insure proper output data.
Standby Mode
The NMC27C512A has a standby mode which reduces the
active power dissipation by over 99%, from 110 mW to
0.55 mW. The NMC27C512A is placed in the standby mode
by applying a CMOS high signal to the CE input. When in
standby mode, the outputs are in a high impedance state,
independent of the OE input.
Output OR-Tying
Because NMC27C512A are usually used in larger memory
arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
a) the lowest possible memory power diSSipation, and
b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended that CE (pin 20) be decoded and used as the primary device selecting function, while OElVpp (pin 22) be
made a common connection to all devices in the array and
connected to the READ line from the system control bus.
Note: Some programmer manufacturers due to equipment limitation may
offer interactive program Algorithm (Shown in Figure 2).
TABLE I. Mode Selection
Pins
Mode
CE
(20)
OE/Vpp
(22)
Vee
(28)
(11-13,15-19)
Read
VIL
VIL
5.0V
DOUT
Standby
VIH
Don't Care
5.0V
Hi-Z
Program
VIL
12.75V
6.25V
DIN
Program Verify
VIL
VIL
6.25V
DOUT
Program Inhibit
VIH
12.75V
6.25V
Hi-Z
Output Disable
Don't Care
VIH
5.0V
Hi-Z
1-105
Outputs
oN
~
CJ1
......
~
Functional Description (Continued)
After programming opaque labels should be placed over the
NMC27C512A's window to prevent unintentional erasure.
Covering the window will also prevent temporary functional
failure due to the generation of photo currents.
Program Inhibit
Programming multiple NMC27C512A in parallel with differ·
ent data is also easily accomplished. Except CE all like inputs (including OE) of the parallel NMC27C512A may be
common. A TIL low level program pulse applied to an
NMC27C512A's CE input with OElVpp at 12.75V will program that NMC27C512A. A TIL high level CE input inhibits
the other NMC27C512A from being programmed.
for
the
The
recommended
erasure
procedure
NMC27C512A is exposure to short wave ultraviolet light
which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure
should be a minimum of 15W-sec/cm2.
Program Verify
The NMC27C512A should be placed within 1 inch of the
lamp tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. Table III
shows the minimum NMC27C512A erasure time for various
light intensities.
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify is accomplished with OElVpp and CE at VIL. data
should be verified tDV ailer the falling edge of CEo
An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one inch.
The erasure time increases as the square of the distance. (If
distance is doubled the erasure time increases by a factor of
4.) Lamps lose intensity as they age. When a lamp is
changed, the distance has changed, or the lamp has aged,
the system should be checked to make certain full erasure
is occurring. Incomplete erasure will cause symptoms that
can be misleading. Programmers, components, and even
system designs have been erroneously suspected when incomplete erasure was the problem.
'
Manufacturer's Identification Code
The NMC27C512A has a manufacturer's identification code
to aid in programming. The code, shown in Table II, is two
bytes wide and is stored in a ROM configuration on the chip.
It identifies the manufacturer and the device type. The code
for the NMC27C512A is, "8F 85", where "8F" designates
that it is made by National Semiconductor, and "85" designates a 512k part.
The code is accessed by applying 12V ± 0.5V to address
pin A9. Addresses Al-A8, Al0-A15, CE, and OE are held
at VIL. Address AO is held at VIL for the manufacturer's
code, and at VIH for the device code. The code is read on
the 8 data pins. Proper code access is only guaranteed at
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer-the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 ",F ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at ieast a 4.7 ",F bulk electrolytiC
capacitor should be used between Vee and GND for each
eight devices. The bulk, capacitor should be locat,ed near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.,
25 C ±5 C.
D
D
The primary purpose of the manufacturer's identification
code is automatic programming control. When the device is
inserted in an EPROM programmer socket, the programmer
reads the code and then automatically calls up the specific
programming algorithm for the part. This automatic programming control is only possible with programmers which
have the capability of reading the code.
ERASURE CHARACTERISTICS
The erasure characteristics of the NMC27C512A are such
that erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000A-4000A
range.
TABLE II. Manufacturer's Identification Code
Os
AD
(10)
07
(19)
06
(18)
Manufacturer Code
VIL
1
0
0
Device Code
VIH
1
0
0
Pins
(17)
00
(11)
Hex
Data
1
1
1
8F
1
0
1
85
02
(13)
0
1
0
0
TABLE III. Minimum NMC27C512A Erasure Time
Light Intensity
(Micro-Watts/cm2)
Erasure Time
(Minutes)
15,000
20
10,000
25
5,000
50
1-106
01
(12)
03
(15)
04
(16)
~NaHonal
~
PRELIMINARY
z
3:
n
N
~
en
......
Semiconductor
N
:J>
NMC27C512AN 524,288-Bit (64k x 8)
One Time Programmable CMOS PROM
z
General Description
Features
The NMC27C512AN is a high-speed 512k UVone time programmable CMOS EPROM, ideally suited for applications
where fast turnaround and low power consumption are important requirements.
• Clocked sense amps for fast access time down to
150 ns
• Low CMOS power consumption
- Active Power: 110 mW max
- Standby Power: 0.55 mW max
• Optimum EPROM for teital CMOS systems
• Pin compatible with NMOS 512k EPROMs
• Fast and reliable programming -100 fJos typical/byte
• Static operation-no clocks required
• TTL, CMOS compatible inputs/outputs
• TRI-STATE® output
• Manufacturer's identification code for automatic programming control
• High current CMOS level output drivers
The NMC27C512AN is designed to operate with a single
+5V power supply with ±5% or ±10% tolerance. The
CMOS design allows the part to operate over extended and
military temperature ranges.
The NMC27C512AN is packaged in a 28-pin dual-in-line
plastic molded package without a transparent lid. This part
is ideally suited for high volume production applications
where cost is an important factor and programming only
needs to be done once. Also the plastic molded package
works well in auto insertion equipment used in automated
assembly lines.
This EPROM is fabricated with National's proprietary, time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low power consumption and excellent reliability.
Block Diagram
,
Vee C>--+
GNDC>--+
Vpp C>--+
iiE ........
ce ........
::!
:::
AO-A15
ADDRESS
INPUTS
OUTPUT ENABLE
AND CHIP
ENABLE LOGIC
y
DECODER
::!
:::
:::
:::
-.
X
DECODER
-
'"""-
r-;-+
•
DATA OUTPUTS 110-0-,
\
lllll!!!
OUTPUT
BUFFERS
Pin Names
Y GATING
r--+
r-;-.
•
•
•
..!..t
524.2BB·BIT
CELL MATRIX
TL/D/8754-1
1-107
AO-A15
Addresses
CE
Chip Enable
OElVpp
Output Enable/ Programming Voltage
00-0 7
Outputs
PGM
Program
NC
No Connect
•
z
....~
Connection Diagram
f::?
IN
27C256 27C128 27C64 27C32 27C16
27256 27128 2764 2732 2716
II)
o
::IE
z
Vpp
A12
A7
A6
A5
Vpp
A12
A7
AS
A5
A1
AO
Vpp
A12
A7
A6
A5
A4
A3
A2
A1
AO
00
00
01
01
01
02
02
02
GND
GND
GND
GND
GND
A4
A3
A2
28 r- v"
'''-1
.7- 3
A3
A2
A1
AO
A7
AS
A5
A4
A3
A2
A1
AO
00
00
Vee
PGM
NC
Vcc
Vcc
AB
AB
AB
A9
A9
A9
Vpp
A11
A11
OE OElVpp OE
A10
A10
A10
CE
CElVpp CE
"r- ....
2& r-.13
A12- •
A7
A6
A5
A4
A3
A2
A1
AO
A4
27C16 27C32 27C64 27C128 27C256
2716
2732 2764 27128 27256
NMC27C512AN
Dual-In-Line Package
Vee
PGM
A13
AB
A9
A11
OE
A10
CE
Vee
A14
A13
AB
A9
A11
OE
A10
CE
AI-'
AI-'
Hr-AI
"r-.a
.. - 6
..AI-a- .
23
"-7
22 -III!/V"
' 0 - 10
19-Dr
07
07
07
07
07
00
0,- 11
18 -0,
Oe
Oe
Oe
06
Oe
01
01
0,- "
17-0"
05
05
05
05
05
02
02
0,- 13
16-0,
04
04
04
04
04
15 - 0 , .
03
03
03
03
03
r-.ll
.. -"a
2G-l!
GND- "
TLlD/8754-2
Order Number NMC27C512AN
See NS Package Number N28B
Note: Socket compatible EPROM pin configurations are shown in the block. adjacent to the NMC27C512AN pin•.
Commercial Temp Range (O'C to
+ 70'C)
Vee = 5V ±5%
Parameter/Order Number
Vee = 5V ±10%
Access Time (ns)
Parameter/Order Number
Access Time (ns)
NMC27C512AN15
150
NMC27C512AN150
NMC27C512AN17
170
NMC27C512AN170
170
NMC27C512AN20
200
NMC27C512AN200
200
NMC27C512AN25
250
NMC27C512AN250
250
Extended Temp Range ( - 40'C to
Vee = 5V ±5%
Parameter/Order Number
150
+ 85'C)
Vee = 5V ±10%
Access Time (ns)
Parameter/Order Number
Access Time (ns)
NMC27C512ANE15
150
NMC27C512ANE150
NMC27C512ANE17
170
NMC27C512ANE170
170
NMC27C512ANE20
200
NMC27C512ANE200
200
NMC27C512ANE25
250
NMC27C512ANE250
250
H08
150
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-10·Cto +80·C
Temperature Under Bias
1.0W
Lead Temperature (Soldering, 10 sec.)
300·C
ESO Rating
(Mil Std. 883C, Method 3015.2)
2000V
-65·Cto + 150·C
Storage Temperature
Operating Conditions (Note 6)
All Input Voltages except A9 and
OElVpp with Respect
to Ground (Note 9)
+6.5Vto -0.6V
Vcc Supply Voltage with
with Respect to Ground
+ 7.0V to -0.6V
All Output Voltages with
Respect to Ground (Note 9)
Power Dissipation
O·Cto +70·C
Temperature Range
Vcc Power Supply
NMC27C512AN15, 17, 20, 25
NMC27C512AN150, 170,200, 250
-40·Cto +85·C
Temperature Range
Vcc + 1 to GNO -0.6V
OElVpp Supply Voltage and A9
with Respect to Ground
+5V ±5%
+5V ±10%
Vcc Power Supply
NMC27C512ANE15, 17, 20, 25
NMC27C512ANE150, 170. 200, 250
+ 14.0V to - 0.6V
+5V ±5%
+5V ±10%
READ OPERATION
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Units
0.01
1
/LA
0.Q1
1
/LA
CE = VIL, f = 5 MHz
Inputs = VIH or VIL,
I/O = OmA
10
30
mA
Vec Current (Active)
CMOS Inputs
CE = GNO,f = 5MHz
Inputs = Vce or GND,
I/O = OmA
8
20
mA
ICCSB1
Vee Current (Standby)
TTL Inputs
CE
=
VIH
0.1
1
mA
leCSB2
Vce Current (Standby)
CMOS Inputs
CE
=
Vce
0.5
100
/LA
Vpp
Conditions
=
III
Input Load Current
VIN
ILO
Output Leakage Current
Your = Vcc or GND CE = VIH
ICC1
Vcc Current (Active)
TTL Inputs
lec2
=
Vcc or GND
Ipp
Vpp Load Current
10
/LA
VIL
Input Low Voltage
-0.2
0.8
V
VIH
Input High Voltage
2.0
Vee +1
V
VOL1
Output Low Voltage
0.4
V
VOH1
Output High Voltage
VOL2
Output Low Voltage
VOH2
Output High Voltage
Vee
= 2.1 mA
IOH = -2.5mA
IOL = 10 /LA
IOH = -10 /LA
IOL
3.5
V
0.1
V
V
Vec -0.1
AC Electrical Characteristics
NMC27C512AN/ANE
Symbol
Parameter
Conditions
15,150
Min
tAee
Address to Output Delay
tCE
CE to Output Delay
toE
OE to Output Delay
tOF
OE High to Output Float
tCF
CE High to Output Float
tOH
Output Hold from Addresses,
CE or OE, Whichever
Occurred First
= OE =
OE = VIL
CE = VIL
CE = VIL
OE = VIL
CE = OE =
CE
VIL
VIL
Max
17,170
Min
Max
20,200
Min
Max
25,250
Min
Units
Max
ns
150
170
200
250
150
170
200
250
ns
60
75
75
100
ns
0
50
a
55
0
55
0
60
ns
a
50
0
55
0
55
0
60
ns
a
1-109
0
0
a
ns
•
z
~
Capacitance T A = + 25°C, f = 1 MHz (Note 2)
II)
~
N
o
z
Symbol
Parameter
Conditions
:&
Typ
Max
Units
5
10
pF
8
10
pF
16
20
pF
VIN = OV
Input Capacitance
CIN
Except OElVpp
COUT
Output Capacitance
VOUT = OV
CIN2
OElVpp Input
VIN = OV
Capacitance
AC Test Conditions
Output Load
1 TTL Gate and
CL = 100 pF (Note 8)
Timing Measurement Reference Level
Inputs
Outputs
S:5 ns
Input Rise and Fall Times
Input Pulse Levels
0.8Vand2V
0.8Vand2V
0.45V to 2.4V
AC Waveforms (Notes 6, 7)
ADDRESSES
-
~:gn
)!
ADDRESSES VALID
2.DV
D.BV
\.
J~IcF_
(N01IS 4, 5)
!--IcE2.0V
D.8V
OUTPUT
't
2.0V
O.BV
tOE
(NOTE 3)
Hi-Z
-
-
I
.VALID OUTPUT
tACC _
(NOTE 3)
-
t Dr
(N01IS 4. 5)
-
fHi-Z
toHITL1018754-3
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 1DD% tested.
Note 3: OE may be delayed up to tAce-toE after the falling edge of
rn: without impacting tAce.
Nota 4: The tOF and tcF compare level is determined as follows:
High to TAI·STATE. the measured VOH'
(~C)
-O.IOV.
Low to TRI·STATE. the measured VOLI (DC) +0.10V.
Note 5: TRI·STATE may be attained using OE or GE.
Nole 6: The power switching characteristics of EPROMs require careful device decoupling. It Is recommended Ihat at least a 0.1 "F ceramic capacitor be used on
every devies between Vce and GND.
Note 7: The outputs must be restricted to Vce + 1.0V to avoid latch·up and device damage.
Nole 8: 1 TTL Gate: IOl
=
1.6 mAo IOH
= -
400 ,.A.
CL: 100 pF includes fixture capacitance.
Note 9: Inputs and outputs can undershoot to - 2.0V for 20 ns Max.
1-110
Programming Characteristics (Notes 1,2,3 and 4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tAS
Address Setup Time
1
,...s
tOES
OE Setup Time
1
,...s
tos
Data Setup Time
1
,...s
tAH
Address Hold Time
0
,...s
1
tOH
Data Hold Time
tCF
Chip Enable to Output Float Delay
tpw
Program Pulse Width
tOEH
OEHoldTime
tov
Data Valid from CE
tpRT
OE Pulse Rise Time
During Programming
tVR
Vpp Recovery Time
Ipp
Vpp Supply Current During
Programming Pulse
,...s
0
OE = VIL
100
95
60
ns
105
,...s
1
,...s
250
OE = VIL
ns
50
ns
1
,...s
CE = VIL
OE = Vpp
30
mA
Icc
Vcc Supply Current
10
mA
TA
Temperature Ambient
20
25
30
'C
Vcc
Power Supply Voltage
6.0
6.25
6.5
V
Vpp
Programming Supply Voltage
12.5
12.75
13.0
tFR
Input Rise, Fall Time
5
V
ns
0.0
0.45
VIL
Input Low Voltage
VIH
Input High Voltage
2.4
4.0
tiN
Input Timing Reference Voltage
0.8
1.5
2.0
toUT
Output Timing Reference Voltage
0.8
1.5
2.0
tvcs
Vcc Setup Time
V
V
1
V
V
,...s
Programming Waveforms
PROGRAM _ _
VERIFY"
PROGRAM
ADDRESSES
O.BV
~
ADDRESS N
~
DATA
OE/Vpp
2V
O.BV
~ ~(J
~
ipRT
CE
ADD.
~
-
2V
O.BV
HI-Z
DATA IN STABlE
tOEH
DATA OUT VAUD ADO N
~
~
~
~
1\
ClvR1
2V
O.BV
"
Ftves-.
Vee 6.DV
c::
,,)
TL/D/B754-4
Nole I: National's standard product warranty applies only to devices programmed to specifications described herein.
Note 2: Va; must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vee.
Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 "F capaCitor is required across Vec to GND to suppress spurious
voltage transients which may damage the device.
Note 4: Programming and program verify are tested with the fast Program AlgOrithm at typical power supply voltages and timings.
1·111
z
~
....
Fast Programming Algorithm Flow Chart (Note 4)
an
~
N
o
:e
z
INCREMENT ADDR
TLlD/8754-5
FIGURE 1
1-112
z
n
N
!!:
Interactive Programming Algorithm Flow Chart (Note4)
......
n
U\
....
N
l>
Z
INCREMENT ADDR
TLiD/B754-6
FIGURE 2
1-113
z
:i
.,...
\I)
(.)
.....
C'I
(.)
:::::e
z
Functional Description
DEVICE OPERATION
The six modes of operation of the NMC27C512AN are listed
in Table I. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for OElVpp during
programming. In the program mode the OElVpp input is
pulsed from a TTL low level to 12.75V.
Programming
CAUTION: Exceeding 14V on pin 22 (OElVpp) will damage
the NMC27C512AN.
Initially, and after each erasure, all bits of the
NMC27C512AN are in the "1" state. Data is introduced by
selectively programming "Os" into the desired bit locations.
Although only "Os" will be programmed, both "1s" and "Os"
can be presented in the data word. The only way to change
a "0" to a "1" is by ultraviolet light erasure.
The NMC27C512AN is in the programming mode when OEI
Vpp is at 12.75V. It is required that at least a 0.1 ",F capacitor be placed across Vee and ground to suppress spurious
voltage transients which may damage the device. The data
to be programmed is applied 8 bits in parallel to the data
output pins. The levels required for the address and data
inputs are TTL.
When the address and data are stable, an active low, TTL
program pulse is applied to the CE input. A program pulse
must be applied at each address location to be programmed. The NMC is programmed with the Fast Programming Algorithm shown in Figure 1. Each Address is programmed with a series of 100 ",s pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
program with a single 100 '" pulse.
Read Mode
The NMC27C512AN has two control functions, both of
which must be logically active in order to obtain data at the
outputs. Chip Enable (CE) is the power control and should
be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output
pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to
the delay from CE to output (teE). Data is available at the
outputs after the falling edge of OE, assuming that CE has
been low and addresses have been stable for at least tAeetoE·
The sense amps are clocked for fast access time. Vee
should therefore be maintained at operating voltage during
read and verify. If Vee temporarily drops below the spec.
voltage (but not to ground) an address transition must be
performed after the drop to ensure proper output data.
Standby Mode
The NMC27C512AN has a standby mode which reduces
the active power dissipation by over 99%, from 110 mW to
0.55 mW. The NMC27C512AN is placed in the standby
mode by applying a CMOS high signal to the CE input.
When in standby mode, the outputs are in a high impedance
state, independent of the OE input.
Note: Some programmer manufacturers due to equipment limitation may
offer interactive program Algorithm (shown In Ftgure 2).
The NMC27C512AN must not be programmed with a DC
signal applied to the CE input.
Output OR-Tying
Because EPROMs are usually used in larger memory arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connection.
The 2-line control function allows for:
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended that CE (pin 20) be decoded and used as the primary device selecting function, while OElVpp (pin 22) be
made a common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in their
low power standby modes and that the output pins are active only when data is desired from a particular memory device.
Programming multiple NMC27C512As in parallel with the
same data can be easily accomplished due to the simplicity
of the programming requirements. Like inputs of the paralleled NMC27C512AN may be connected together when
they are programmed with the same data. A low level TTL
pulse applied to the CE input programs the paralleled
NMC27C512AN.
The NMC27C512AN is packaged in a plastic molded package which does not have a transparent lid. Therefore the
memory cannot be erased. This means that after a user has
programmed a memory cell to a "0" it cannot be changed
back to a "1".
If an application requires erasing and reprogramming, the
NMC27C512AQ UV Erasable PROM in a windowed package should be used.
PROGRAM INHIBIT
Programming multiple NMC27C512ANs in parallel with different data is also easily accomplished. Except for CE all
like inputs (including OE) of the parallel NMC27C512AN
may be common. A TTL low level program pulse applied to
TABLE I. Mode Selection
Pins
Mode
CE
(20)
Read
Standby
Output Disable
OE/Vpp
(22)
Vee
(28)
Outputs
(11-13,15-19)
VIL
VIL
5.0V
DOUT
VIH
Don't Care
5.0V
Hi-Z
Hi-Z
Don't Care
VIH
5.0V
Program
VIL
12.75V
6.25V
DIN
Program Verify
VIL
VIL
6.25V
DOUT
Program Inhibit
VIH
12.75V
6.25V
Hi-Z
1-114
,----------------------------------------------------------------------, z
iii:
Functional Description
(Continued)
an NMC27C512A's CE input with OElVpp at 12.75V will
program that NMC27C512AN. A TTL high level CE input
inhibits the other NMC27C512A from being programmed.
PROGRAM VERIFY
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify is accomplished with OElVpp and CE at VIL. Data
should be verified tov ~fter the falling edge of CEo
MANUFACTURER'S IDENTIFICATION CODE
The NMC27C512AN has a manufacturer's identification
code to aid in programming. The code, shown in Table II, is
two bytes wide and is stored in a ROM configuration on the
Chip. It identifies the manufacturer and the device type. The
code for NMC27C512AN is "SF S5", where "SF" designates that it is made by National Semiconductor, and "S5"
designates a 512k part.
The code is accessed by applying 12V ±0.5V to address
pin A9. Addresses A1-AS, A10-A15, CE and OE are held
at VIL. Address AO is held at VIL for the manufacturer's
code, and at VIH for the device code. The code is read out
on the eight data pins. Proper code access is only guaranteed at 25'C ± 5'C.
The primary purpose of the manufacturer's identification
code is automatic programming control. When the device is
inserted in an EPROM programmer socket, the programmer
reads the code and then automatically calls up the specific
programming algOrithm for the part. This automatic programming control is only possible with programmers which
have the capability of reading the code.
n
N
......
n
U'I
.....
~
Z
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer-the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 fLF ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 fLF bulk electrolytic
capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
TABLE II. Manufacturer's Identification Code
Pins
AO
(10)
06
Os
03
00
(18)
(17)
(15)
(11)
o
o
o
o
Manufacturer Code
Device Code
o
o
Hex
Data
SF
o
o
S5
Package Information
rr mnrumr
1
8 SPACES AT
Lf
(~:~~I
a.I.
;:
i:::!
9
A. .
;: 25
~
I" l.][.Jl
~--I
(1.1431
x45'
10.813-1.016)
0.050
(1.~:01
~~
t
0.032-0.040
BSPACES AT
t
0.'51 ±0.002
(14.00±0.0511
~
.
~
(12.45-13.'61
T
(14.99 ±0.1271
(CONTACT rENSIONI
uu~
j;..::.2132
r:
l
~=JJ
•
x45'
(CO~;;;'~::ONI
illI
U......,jt'5'liil,,;..1__
0.015
(0.3811
VIEWA-A
0.013-0021
(0.330-0.5331
0.100-0.140
(2_.5._0~'_3_.55_6)...i
TY1'
___
~~=·~~~-~c~U~J~-~==~tt
(::~=:::::I EA.'~'liJj -Jljlll (:::=::~:) t(~::::=:::::)
0.450
-(11.43)
TYP
0.485-0.'95
(12.32-12.57)
TLlD/8754-7
32-Lead PLCC Package
Order Number NMC27C512AV
1-115
.,...
Q
.---------------------------------------------------------------------------~
~ ~National
~ ~
z
PRELIMINARY
Semiconductor
NMC27C010 (Former NMC27C1023)*
1,048,576-Bit (128k x 8) UV Erasable CMOS PROM
General Description
Features
The NMC27C010 is a high-speed 1024k UV erasable and
electrically reprogrammable CMOS EPROM, ideally suited
for applications where fast turnaround, pattern experimentation and low power consumption are important requirements.
The NMC27C010 is designed to operate with a single + 5V
power supply with ± 5% or ± 10% tolerance. The CMOS
design allows the part to operate over extended and military
temperature ranges.
The NMC27C010 is packaged in a 32-pin dual-in-line package with transparent lid. The transparent lid allows the user
to expose the chip to ultraviolet light to erase the bit pattern.
A new pattern can then be written electrically into the device
by following the programming procedure.
• Clocked sense amps for fast access time down to
150 ns
• Low CMOS power consumption
-Active power: 110 mW max
- Standby power: 0.55 mW max
• Extended temperature range (NMC27C0100E), -40·C
to
+ 85·C and military temperature range
(NMC27C0100M), -55·C to + 125·C, available
• Pin compatible with NMOS bytewide 1024k EPROMs
• Fast and reliable programming-100 p's typical/byte
• Static operation-no clocks required
• TTL, CMOS compatible inputs/outputs
• TRI-STATE® output
• Optimum EPROM for total CMOS systems
• Manufacturer's identification code for automatic programming control
• High current CMOS level output drivers
This EPROM is fabricated with National's proprietary, time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low power consumption and excellent reliability.
Block Diagram
DATA OUTPUTS 00-0,
Vcc~
OND~
Pin Names
OUTPUT
BUFFERS
Y GATING
AD·Ale
ADDRESS
INPUTS
U''.578011T
CRlMAIRIX
'Some programmer manufacturers will call this device NMC27Ct 023.
TL/D/9182-1
1-116
AO-A16
Addresses
CE
Chip Enable
OE
Output Enable
0 0- 0 7
Outputs
PGM
Program
NC
No Connect
Connection Diagram
NMC27C010Q
Dual·ln·Line Package
4 Mbit
2 Mbft
Vpp
Vpp
Vpp- I
A16
A16
A16- 2
32 -Vee
31 -PGM
A15
A15
A15- 3
30
A12
A12
A12- 4
A7
A7
A6
A6
A5
2 Mbit
4 Mbft
Vee
Vee
PGM
AlB
-Ne
A17
A17
29 -A14
A14
A14
A7- 5
28 -A13
A13
A13
A6- 6
27 -A8
AB
AB
A5
A5- 7
26 -A9
A9
A9
A4
A4
A4- 8
25 -All
All
All
A3
A3
A3- 9
24
,-1iE
OE
OE
A2
A2
A2- 10
23
~AIO
Al0
Al0
AI
AI
A,- II
22
,-cr
CE
CE
AO
AO
Ao- 12
21
~07
07
07
00
0,
02
00
0,
02
00- 13
°1- 14
20 ,-06
19 ~O5
Os
Os
Os
Os
GND
GND
°2- 15
GND- 16
18 ~O4
17 '-03
04
03
04
03
TL/D/9182-2
Note: Socket compatible EPROM pin configurations are shown In the blocks adjacent to the NMC27COI 0 pins.
Order Number NMC27C010Q
See NS Package Number J32AQ
Commercial Temperature Range (O"C to
Vee = 5V ±5%
Parameter/Order Number
+ 70'C)
Commercial Temperature Range (O"C to
Vee = 5V ±10%
Access Time (ns)
Parameter/Order Number
+ 70'C)
Access Time (ns)
NMC27C010015
150
NMC27C0100150
NMC27C010017
170
NMC27C0100170
170
NMC27C010020
200
NMC27C0100200
200
NMC27C010025
250
NMC27C0100250
250
Extended Temperature Range (- 40'C to
Vee = 5V ±10%
Parameter/Order Number
+ 85'C)
150
Military Temperature Range (-55'C to
Vee = 5V ±10%
Access Time (ns)
Parameter/Order Number
+ 125'C)
Access Time (ns)
NMC27C0100E170
170
NMC27C0100M170
170
NMC27C0100E200
200
NMC27C0100M200
200
NMC27C0100E250
250
NMC27C0100M250
250
NOTE: Surface mount PLCC package available for commercial and extended temperature ranges only.
1·117
•
o,...
o
~
N
o
:!i
Z
COMMERCIAL TEMPERATURE RANGE
Absolute Maximum Ratings (Note 1)
-10·C to +800C
Temperature Under Bias
Storage Temperature
- 65·C to + 1500C
All Input Voltages except A9 with
Respect to Ground (Note 10)
All Output Voltages with
Respect to Ground (Note 10)
+6.5Vto -0.6V
1.0W
300·C
ESD Rating
(Mil Spec 883C, Method 3015.2)
2000V
Operating Conditions (Note 7)
Vee+1.0VtoGND-0.6V
Vpp Supply Voltage and A9
with Respect to Ground
During Programming
Vee Supply Voltage with
Respect to Ground
Power Dissipation
lead Temperature (Soldering, 10 sec.)
O·Cto +700C
Temperature Range
Vee Power Supply
NMC27C010015, 17,20,25
NMC27C0100150, 170, 200, 250
+ 14.0Vto -0.6V
+5V ±5%
+5V ±10%
+ 7.0V to -0.6V
READ OPERATION
DC Electrical Characteristics
Symbol
Parameter
Conditions
=
Min
III
Input load Current
VIN
ILO
Output leakage Current
VOUT
lee1
(Note 9)
Vee Current (Active)
TTL Inputs
CE = VIL, f = 5 MHz
Inputs = VIH or VIL, I/O
1CC2
Vee Current (Active)
CMOS Inputs
CE = GND,f = 5MHz
Inputs = Vee or GND, I/O
leeSB1
Vee Current (Standby)
TTL Inputs
CE
=
VIH
leeSB2
Vee Current (Standby)
CMOS Inputs
CE
=
Vee
Vpp
(Note 9)
Typ
Max
Units
1
IJ-A
1
IJ-A
15
30
mA
10
20
mA
0.1
1
mA
0.5
100
p,A
Vee or GND
=
=
Vee or GND, CE
=
=
VIH
0 mA
=
0 mA
Ipp
Vpp load Current
10
IJ-A
VIL
Input low Voltage
-0.2
0.8
V
VIH
Input High Voltage
2.0
Vee + 1
V
VOL1
Output low Voltage
0.40
V
VOH1
Output High Voltage
VOL2
Output low Voltage
VOH2
Output High Voltage
Vee
= 2.1 mA
IOH = -2.5mA
IOL = 10 IJ-A
IOH = -10 IJ-A
IOL
3.5
V
0.1
V
V
Vee - 0.1
AC Electrical Characteristics
NMC27C010
Symbol
tAee
Parameter
Address to Output Delay
Conditions
CE =
PGM
teE
CE to Output Delay
toE
OE to Output Delay
tOF
OE High to Output Float
teF
CE High to Output Float
tOH
Output Hold from Addresses,
CE or OE, Whichever
Occurred First
015,0150
017,0170
020,0200
025,0250
Min
Min
Min
Min
OE = VIL
VIH
=
= VIL, PGM = VIH
CE = VIL, PGM = VIH
CE = VIL, PGM = VIH
OE = VIL. PGM = VIH
CE = OE = VIL
PGM = VIH
OE
Max
Max
Max
Units
Max
150
170
200
250
ns
150
170
200
,250
ns
60
75
75
100
ns
0
50
0
55
0
55
0
60
ns
0
50
0
55
0
55
0
60
ns
0
1·118
0
0
0
ns
z
a::
MILITARY AND EXTENDED TEMPERATURE RANGE
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature Under Bias
Operating Temp. Range
Storage Temperature
-65·C to + 150·C
All Input Voltages except A9 with
Respect to Ground (Note 10)
All Output Voltages with
Respect to Ground (Note 10)
Vpp Supply Voltage and A9
with Respect to Ground
During Programming
fJ
...oo~
(Note 1)
Vee Supply Voltage with
Respect to Ground
Power Dissipation
Lead Temperature (Soldering, 10 sec.)
ESD Rating
(Mil Spec 883C, Method 3015.2)
+6.5Vto -0.6V
+7.0Vto -0.6V
1.0W
300·C
2000V
Operating Conditions (Note 7)
Vee + 1.0V to GND-0.6V
Temperature Range
NMC27C0100E150, 170,200,250
NMC27C0100M170, 200, 250
+ 14.0V to -0.6V
-40·Cto +85·C
- 55·C to + 125·C
+5V ±100/0
Vee Power Supply
READ OPERATION
DC Electrical Characteristics
Symbol
Parameter
Max
Units
III
Input Load Current
VIN = Vee or GND
10
".A
ILO
Output Leakage Current
VOUT = Vee or GND, CE = VIH
10
".A
ICCl
(Note 9)
Vee Current (Active)
TTL Inputs
CE = VIL, f = 5 MHz
Inputs = VIH or VIL, 1/0 = 0 mA
15
30
mA
ICC2
(Note 9)
Vcc Current (Active)
CMOS Inputs
CE = GND,f = 5MHz
Inputs = Vee or GND, 1/0 = 0 mA
10
20
mA
leCSBl
Vcc Current (Standby)
TTL Inputs
CE = VIH
0.1
1
mA
leeSB2
Vcc Current (Standby)
CMOS Inputs
CE = Vee
0.5
100
".A
Ipp
Vpp Load Current
Vpp = Vee
VIL
Input Low Voltage
VIH
Input High Voltage
VOll
Output Low Voltage
Conditions
Min
Typ
10
".A
-0.2
0.8
V
2.0
Vee + 1
V
0.40
V
IOL = 2.1 mA
VOHl
Output High Voltage
IOH = -1.6 mA
VOL2
Output Low Voltage
IOL=10".A
VOH2
Output High Voltage
IOH = -10".A
V
3.5
0.1
V
Vcc - 0.1
V
AC Electrical Characteristics
NMC27C010Q
Symbol
Parameter
Conditions
E150
Min Max
E170,M170
E200,M200
E250,M250
Min
Min
Min
Max
Max
Units
Max
tAee
Address to Output Delay
CE = OE = VIL
PGM = VIH
150
170
200
250
ns
teE
CE to Output Delay
OE = VIL, PGM = VIH
150
170
200
250
ns
tOE
OE to Output Delay
CE = VIL, PGM = VIH
60
75
75
100
ns
tDF
OE High to Output Float
CE = VIL, PGM = VIH
0
50
0
55
0
55
0
60
ns
teF
CE High to Output Float
OE = VIL, PGM = VIH
0
50
0
55
0
55
0
60
ns
toH
Output Hold from Addresses, CE = OE = VIL
CE or OE, Whichever
PGM = VIH
Occurred First
0
1-119
0
0
0
ns
CI
.,...
~
'"
Capacitance TA = + 25"C, f =
(,)
Symbol
:&
CIN
Input Capacitance
COUT
Output Capacitance
z
Parameter
1 MHz (Note 2)
Conditions
VIN = OV
VOUT = OV
Typ
Max
Units
9
15
pF
12
15
pF
AC Test Conditions
Output Load
Timing Measurement Reference Level
Inputs
Outputs
1 TTL Gate and
CL = 100 pF (Note 8)
::;;;5n8
Input Rise and Fall Times
Input Pulse Levels
0.8Vand2V
0.8V and 2V
0.45V to 2.4V
AC Waveforms (Notes 6, 7, & 9)
rr
::>
2.0V
O.sv
.~
rr
J
.-
~
I--tcE-
II
~:OE
(NOrEl)
II
rr
HI-Z
IIIIIIIII
"\'\'\'\'\'\'\'\'\
IcF
~TES4:si
2.0V
O.sv
2.0V
OUTPUT O.SV
cc
II
ADDRESSES VALID
ADDRESSES O.sv
J
f4:- tDr.~
(NOTES 4,5)
rr
II
VALID OUTPUT
"
II
tAct
(NOTE 3)
-
~'\ '\'\ '\'
flllll
HI-Z
toH ITLlD/9t 82-3
Nota 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device relisbility.
Nota 2: This parameter is only sempled and is not 100% tested.
Note 3: OE may be delayed up to tAce - toE after the falling edge of CE wIthoutimpecting tAce.
Note 4: The toF and 1cF compare level is determined as follows:
High 10 TRI..sTATE.the measured VOH! (DC) - 0.10V;
Low to TAI-STATE. the measured VOLt (DC) + 0.10V.
Note 5: TAI·STATE may be attained using OE or CE.
Note 8: The power switching characteristics of EPROMs require careful device decoupllng. It is recommended that at least a 0.1 ,.F ceramic capacitor be used on
every device between Vce and GND.
Nota 7: The outputs must be restricted to Vce + 1.0V to avoid latch-up and device damage.
Note 8: 1 TIL Gate: 10L = 1.6 rnA, IOH = -400 pA
CL: 100 pF includes fIXtUre capacitance.
Note 9: Vpp may be connected to Vce except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
1·120
z
5:
Programming Characteristics (Notes 1. 2. 3 & 4)
Symbol
Parameter
tAS
Address Setup TIme
Conditions
Min
Typ
Max
Units
1
".s
1
".s
1
".s
toES
OE Setup Time
teEs
CE Setup Time
tos
Data Setup Time
1
".s
tvps
Vpp Setup TIme
1
".s
tves
Vee Setup TIme
1
".s
tAH
Address Hold Time
0
".s
tOH
Data Hold Time
1
tOF
Output Enable to Output Float Delay
tpw
Program Pulse Width
OE
CE
= VIH
= VIL
100
= VIL
toE
Data Valid from OE
CE
Ipp
Vpp Supply Current During
Programming Pulse
CE = VIL
PGM = VIL
o
.....
o
".s
0
95
~
......
(")
60
ns
105
".s
100
ns
30
rnA
Icc
Vee Supply Current
10
rnA
TA
Temperature Ambient
20
25
30
'C
Vee
Power Supply Voltage
6.0
6.25
6.5
V
12.5
12.75
13.0
V
Vpp
Programming Supply Voltage
tFR
Input Rise. Fall TIme
VIL
Input Low Voltage
VIH
Input High Voltage
2.4
4.0
tiN
Input Timing Reference Voltage
0.8
1.5
2.0
V
toUT
Output Timing Reference Voltage
0.8
1.5
2.0
V
ns
5
0.0
0.45
V
V
•
1·121
I
«:»
....
«:»
B
z
Programming Waveforms (Note 3)
::E
TL/D/9182-5
Note 1: National's standard product warranty applies only to devices programmed to specifications described herein.
Note 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vr;c.
Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 ,..F cepscHor is required acro.s Vpp, Vee to GND to suppress
spu10us voll8ge transients which may damage the device.
Note 4: Programming and program verily are tested wHh the fast Program Algorithm, at typical power supply voltages and timings.
1-122
z
3:
Fast Programming Algorithm Flow Chart
(")
N
.....
(")
o
....
o
INCREMENT ADDR
TL/D/9182-6
FIGURE 1
1-123
o
.,...
o
~
N
o
::!!
z
Functional Description
DEVICE OPERATION
The six modes of operation of the NMC27C010 are listed in
Table I. It should be noted that all inputs for the six modes
are at TTL levels. The power supplies required are Vee and
Vpp. The Vpp power supply must be at 12.75V during the
three programming modes, and must be at 5V in the other
three modes. The Vee power supply must be at 6.25V during the three programming modes, and at 5V in the other
three modes.
gramming "O's" into the desired bit locations. Although only
"O's" will be programmed, both "1's" and "O's" can be presented in the data word. The only way to change a "0" to a
"1" is by ultraviolet light erasure.
The NMC27C010 is in the programming mode when the Vpp
power supply is at 12.75V and OE is at VIH. It is required
that at least a 0.1 ,...F capacitor be placed across Vpp, Vee
to ground to suppress spurious voltage transients which
may damage the device. The data to be programmed is
applied S bits in parallel to the data output pins. The levels
required for the address and data inputs are
n:L.
Read Mode
The NMC27C010 has two control functions, both of which
must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be
used for device selection. Output Enable (OE) is the output
control and should be used to gate data to the output pins,
independent of device selection. Assuming that addresses
are stable, address access time (tAeel is equal to the delay
from CE to output (teE). Data is available at the outputs toE
after the falling edge of OE, assuming that CE has been low
and addresses have been stable for at least tAee-tOE.
The sense amps are clocked for fast access time. Vee
should therefore be maintained at operating voltage during
read and verify. If Vee temporarily drops below the specified
voltage (but not to ground) an address transition must be
performed after the drop to insure proper output data.
When the address and data are stable, an active low, TIL
program pulse is applied to the PGM input. A program pulse
must be applied at each address location to be programmed. The NMC27C010 is programmed with the Fast
Programming Algorithm shown in Figure 1. Each Address is
programmed with a series of 100 ,...S pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
program with a Single 100 ,...S pulse. The NMC27C010 must
not be programmed with a DC signal applied to the PGM
input.
Programming multiple NMC27C010 in parallel with the same
data can be easily accomplished due to the simplicity of the
programming requirements. Like inputs of the parallel
NMC27C010 may be connected together when they are
programmed with the same data. A low level TIL pulse applied to the PGM input programs the paralleled
NMC27C010.
Standby Mode
The NMC27C010 has a standby mode which reduces the
active power dissipation by over 99%, from 110 mW to
0.55 mW. The NMC27C010 Is placed in the standby mode
by applying a CMOS high signal to the CE input. When in
standby mode, the outputs are in a high impedance state,
independent of the OE input.
Program Inhibit
Programming multiple NMC27C010's in parallel with different data is also easily accomplished. Except for CE all like
inputs (including OE and PGM) of the parallel NMC27C010
may be common. A TIL low level program pulse applied to
an NMC27C010's PGM input with CE at VIL and Vpp at
12.75V will program that NMC27C010. A TTL high level CE
input inhibits the other NMC27C010's from being programmed.
Output OR-Tying
Because the NMC27C010 is usually used in larger memory
arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with Vpp at 12.75V. Vpp must be at
Vee, except during programming and program verify.
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended that CE be decoded and used as the primary device selecting function, while OE be made a common connection to all devices in the array and connected to the
READ line from the system control bus. This assures that all
deselected memory devices are in their low power standby
modes and that the output pins are active only when data is
desired from a particular memory device.
Manufacturer's Identification Code
The NMC27C010 has a manufacturer's identification code
to aid in programming. When the device is inserted in an
EPROM programmer socket, the programmer reads the
code and then automatically calls up the specific programming algorithm for the part. This automatic ·programming
control is only possible with programmers which have the
capability of reading the code.
Programming
CAUTION: Exceeding 14V on the Vpp or A9 pin will damage
the NMC27C010.
Initially, and after each erasure, all bits of the NMC27C010
are in the "1" state. Data is introduced by selectively pro-
The Manufacturer's Identification code, shown in Table II,
specifically identifies the manufacturer and the device type.
The code for the NMC27C01 0 is "SFS6", where "SF" deSignates that it is made by National Semiconductor, and "S6"
designates a 1Megabit byte-wide part.
1-124
z
Functional Description
5!:
(Continued)
TABLE I. Mode Selection
Pins
Mode
CE
(22)
OE
(24)
PGM
(31)
Vpp
(1)
Vee
(32)
Outputs
(13-15,17-21)
Read
VIL
VIL
VIH
Vee
5V
DOUT
Standby
VIH
Don't Care
Don't Care
Vee
5V
Hi·Z
VIH
Vee
5V
Hi·Z
Don't Care
VIH
Program
VIL
VIH
VIL
12.75V
6.25V
DIN
Program Verify
VIL
VIL
VIH
12.75V
6.25V
DOUT
Program Inhibit
VIH
Don't Care
Don't Care
12.75V
6.25V
Hi·Z
Output Disable
oN
-...I
oo
....o
TABLE II. Manufacturer's Identificatiion Code
AD
(12)
07
06
05
04
03
02
0,
00
(21)
(20)
(19)
(18)
(17)
(15)
(14)
(13)
Hex
Data
Manufacturer Code
VIL
1
0
0
0
1
1
1
1
8F
Device Code
VIH
1
0
0
0
0
1
1
0
86
Pins
The code is accessed by applying 12V ± 0.5V to address
pin A9. Addresses A1-A8, A10-A16, and all control pins
are held at VIL. Address pin AO is held at VIL for the manufacturer's code, and held at VIH for the device code. The
code is read on the eight data pins, 00-07. Proper code
access is only guaranteed at 25'C ± 5'C.
changed, the distance has changed, or the lamp has aged,
the system should be checked to make certain full erasure
is occurring. Incomplete erasure will cause symptoms that
can be misleading. Programmers, components, and even
system designs have been erroneously suspected when incomplete erasure was the problem.
ERASURE CHARACTERISTICS
The erasure characteristics of the NMC27C010 are such
that erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000A-4000A
range.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system design)-the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance
loading the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 /A-F ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 /A-F bulk electrolytic
capacitor should be used between Vee·and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
AFTER PROGRAMMING
Opaque labels should be placed over the NMC27C010 window to prevent unintentional erasure. Covering the window
will also prevent temporary functional failure due to the generation of photo currents.
The recommended erasure procedure for the NMC27C010
is exposure to short wave ultraviolet light which has a wave·
length of 2537 Angstroms (A). The integrated dose (I.e., UV
intensity x exposure time) for erasure should be a minimum
of 15 W-sec/cm2.
The NMC27C01 0 should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. Table III
shows the minimum NMC27C010 erasure time for various
light intensities.
TABLE III. NMC27C010
Minimum Erasure Time
An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one inch.
The erasure time increases as the square of the distance. (If
distance is doubled the erasure time increases by a factor of
4.) Lamps lose intensity as they age. When a lamp is
1-125
Light Intensity
(/A-Watts/cm 2)
Erasure Time
(Minutes)
15,000
20
10,000
25
5,000
50
•
....
~C'II
C)
(.)
:::IE
z
r-------------------------------------------------------------------------------------~
Package Information
6 SPACES AT
0.050
(1.270)
17
f
0.551 ±0.OO2
(14.00 ±0.051)
0.590±0.005
(14.99±0.127)
VIEWA-A
~.:--IlU
x45"
0.100-0.140
(2.540-3.556)
+ t
0.026 -0.032
(0.660 - 0.813)
TYP
t f
0.060-0.095
(1.524 -2.413)
TUD/9182-10
32-Lead PLCC Package
Order Number NMC27C010V
1-126
~National
~
PRELIMINARY
Semiconductor
NMC27C1024
1,048,576-Bit (64k x 16) UV Erasable CMOS PROM
General Description
Features
The NMC27C1024 is a high-speed 1024k UV erasable and
electrically reprogram mabie CMOS EPROM, ideally suited
for applications where fast turnaround, pattern experimentation and low power consumption are important requirements.
The NMC27C1024 is designed to operate with a single + 5V
power supply with ±5% or ±10% tolerance. The CMOS
design allows the part to operate over extended and military
temperature ranges.
• Clocked sense amps for fast access time down
to 120 ns
• Low CMOS power consumption
- Active Power: 110 mW max
- Standby Power: 550 ,..W max
• Performance compatible to 16-bit and 32-bit
microprocessors
• Extended temperature range (NMC27C10240E), -40·C
to
+ 85·C, and military temperature range
(NMC27C10240M), - 55·C to + 125·C, available
• Pin compatible with NMOS wordwide 1024k EPROMs
• Fast and reliable programming-100 ,..s typical/byte
• Static operation-no clocks required
• TTL, CMOS compatible inputs/outputs
• TRI-STATE® output
• Optimum EPROM for total CMOS systems
• Manufacturer's Identification Code for automatic programming control
• High current CMOS level output drivers
The NMC27C1 024 is packaged in a 40-pin dual in-line package with transparent lid. The transparent lid allows the user
to expose the chip to ultraviolet light to erase the bit pattern.
A new pattern can then be written electrically into the device
by following the programming procedure.
This EPROM is fabricated with National's proprietary, time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low power consumption and excellent reliability.
Block Diagram
Vee 0---+
,
GNDo---+
DATA OUTPUTS 00.016
VPPo--+
.
Pin Names
1111111111111111
OE-+
~:::
AO·AI5
ADDRESS
INPUTS
:::;
:::;
--+
:::;
::::
:::;
::::
OUTPUT ENABLE.
CHIP ENABLE AND
PROGRAM LOGIC
y
DECODER
--..
--..
--:--.-
OUTPUT
BUFFERS
Y BATING
--+
X
DECODER
--+
•
•
•
1.048.578·BIT
CELL MATRIX
~
TL/D/8806-1
1-127
AO-A15
Addresses
CE
Chip Enable
OE
Output Enable
00-0 15
Outputs
PGM
Program
NC
No Connect
•
..,.
N
CI
....
~
N
o
::&
z
Connection Diagram
27C2048
Vpp
CE
Vpp- 1.
015
015 - 3
01, - 4
014
013
012
011
010
Oe
Os
GND
07
06
05
04
03
02
01
00
OE
NMC27C1024V
Plastic Chip Carrier
NMC27C1024Q
Dual-In-Une Package
'-./
CE-2
013 - 5
012 - 6
011 - 7
010 - 8
09 - 9
08 - 10
GND- 11
D]-
12
06 - 13
05- 14
.., . . '" ... 81~ "' . .
'I 'I 'I 'I i i' 'i 'I ii' i'
--_
.....
5 4
3
a..CJ
(.)
__
Vee
PGM
38 -NC
A16
012- 7
39 -A13
37 I"'"A15
36 I-Al'
A15
A14
011- 8
38 -A12
010- 9
37 -All
35 I-A13
,34 I-A12
33 I-Al1
A13
A12
All
32 I-A10 .
31 I-Ag
30 I-GND
29 I- A8
28 I- A7
6
1 44 43 42 41 40
2
09- 10
36 -AID
OB- 11
35 I"'"A9
44 pin
PlCC
GND- 12
34 I-GND
AID
Ae
GND
NC- 13
33 I-NC
07- 14
32 I-AB
06- 15
311-A7
As
05- 16
30 I-A6
A7
04- 17
29 1-A5
27 I- A6
26 I- A5
A6
As
lB 19 20 21 22 23 24 25 26 27 28
25 I-A,
24 I- A3
A4
o
19
23 I-A2
22 I-Al
A2
20
21 1-40
Ao
0,- 15
03- 16
O20100 l!£-
27C2048
40 -Vee
39 -Pmi
17
18
!!
0
.!.0
! I!
0
0
~
Z
!
oC
.!.C ~ ~ ~
TUD/8806-11
Aa
Order Number NMC27C1024V
See NS Package Number V44A
Al
TUD/8806-2
Order Number NMC27C1024Q
See NS Package Number J40AQ
Note: National's socket compatible EPROM pin configurations are shown In
the block. adjacent to the NMC27Cl024 pin•.
Commercial Temperature Range (O"C to
Vee = SV ±S%
Parameter/Order Number
+ 70"C)
Commercial Temperature Range '(O"C to
Vee = SV ± 10%
Access Time (ns)
Parameter/Order Number
+ 70"C)
Access Time (ns)
NMC27Cl024012
120
NMC27Cl0240120
120
NMC27Cl024015
150
NMC27Cl0240150
150
NMC27Cl024017
170
NMC27Cl0240170
170
NMC27Cl024020
200
NMC27Cl0240200
200
NMC27Cl024025
250
NMC27Cl0240250
250
Extended Temperature (- 40"C to
Vee = SV ± 10%
Parameter/Order Number
NMC27Cl0240E150
+ 85"C)
Military Temperature Range (- SS'C to
Vee = SV ± 10%
Access Time (ns)
Parameter/Order Number
+ 125"C)
Access Time (ns)
150
NMC27Cl0240M170
170
NMC27Cl0240E170
170
NMC27Cl0240M200
200
NMC27Cl0240E200
200
Note: Surface mount PLCC package available lor commercial and extended temperelure renges only.
1-128
COMMERCIAL TEMPERATURE RANGE
Absolute Maximum Ratings (Note 1)
Temperature Under Bias
-10·Cto +80·C
Storage Temperature
Power Dissipation
-65·C to + 150·C
All Input Voltages except A9 with
Respect to Ground (Note 10)
All Output Voltages with
Respect to Ground (Note 10)
+6.5Vto -O.SV
300·C
ESD rating
(Mil Spec 883C Method 3015.2)
2000V
Operating Conditions (Note 7)
Vee + 1.0 to GND-0.6V
Vpp Supply Voltage and A9 with
Respect to Ground
During Programming
1.0W
lead Temperature (Soldering, 10 sec.)
O·Cto +70·C
Temperature Range
Vee Power Supply
NMC27C1 024012, IS, 17,20,25
NMC27C10240120, 150, 170,200,250
+ 14.0V to - O.SV
Vee Supply Voltage with
Respect to Ground
+5V ±5%
+5V ±10%
+7.0Vto -0.6V
READ OPERATION
DC Electrical Characteristics
Symbol
Parameter
Max
Units
III
Input load Curre!)t
VIN = Vee or GND
Conditions
Min
1
",A
ILO
Output leakage Current
VOUT = Vee or GND, CE = VIH
1
",A
leel
(Note 9)
Vee Current (Active)
TTL Inputs
CE = VIL, f = 5 MHz
Inputs = VIH or VIL
I/O = OmA
15
30
rnA
lee2
(Note 9)
Vee Current (Active)
CMOS Inputs
CE = GND, f = 5 MHz
Inputs = Vee or GND,
I/O = OmA
13
20
rnA
leeSBl
Vee Current (Standby)
TTL Inputs
CE = VIH
0.1
1
rnA
leesB2
Vee Current (Standby)
CMOS Inputs
CE = Vee
0.5
100
",A
Vpp = Vee
Typ
Ipp
Vpp load Current
10
",A
VIL
Input low Voltage
-0.2
0.8
V
VIH
Input High Voltage
2.0
Vee + 1
V
VOLl
Output low Voltage
IOL = 2.1 rnA
VOHl
Output High Voltage
IOH = -2.5 rnA
VOL2
Output low Voltage
IOL = 10 ",A
VOH2
Output High Voltage
IOH = -10 ",A
0.40
V
3.5
V
0.1
V
Vee -0.1
V
AC Electrical Characteristics
Symbol
Parameter
Conditions
012,0120
Max
Min
015,0150
Max
Min
017,0170
Max
Min
020,0200
Max
Min
025,0250 Units
Max
Min
tAee
Address to
Output Delay
CE = OE = VIL
PGM = VIH
120
150
170
200
250
ns
teE
CEtoOutput
Delay
OE = VIL
PGM = VIH
120
150
170
200
250
ns
toE
OE to Output
Delay
CE = VIL
PGM = VIH
50
60
75
75
100
ns
tOF
OE High to Output CE = VIL
Float
PGM = VIH
0
40
0
50
0
55
0
55
0
SO
ns
teF
CE High to
Output Float
0
40
0
50
0
55
0
55
0
60
ns
toH
Output Hold from CE = OE = VIL
Addresses, CE or PGM = VIH
OE, Whichever
Occurred First
OE = VIL
PGM = VIH
0
0
1-129
0
0
0
ns
MILITARY AND EXTENDED TEMPERATURE RANGE
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature Under Bias
Operating Temp. Range
Storage Temperature
-65°C to + 150°C
Vcc Supply Voltage with
Respect to Ground
Power Dissipation
Lead Temperature (Soldering, 10 sec.)
ESD Rating
(Mil Spec 883C, Method 3015.2)
All Input Voltages except A9 with
Respect to Ground (Note 10)
+6.5Vto -0.6V
All Output Voltages with
Respect to Ground (Note 10) Vee+l.0Vto GND-0.6V
Vpp Supply Voltage and A9
with Respect to Ground
During Programming
+ 14.0V to -0.6V
+ 7.0V to -0.6V
1.0W
300°C
2000V
Operating Conditions (Note 7)
Temperature Range
NMC27Cl0240E150, 170, 200
NMC27Cl0240M170, 200
Vcc Power Supply
- 40"C to + 85°C
- 55°C to + 125°C
+5V ±10%
READ OPERATION
DC Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
III
Input Load Current
VIN = Vee or GND
10
p.A
ILO
Output Leakage Current
Your
10
p.A
leel
(Note 9)
Vee Current (Active)
TIL Inputs
CE = VIL, f = 5 MHz
Inputs = VIH or VIL, I/O = 0 mA
15
30
mA
ICC2
(Note 9)
Vcc Current (Active)
CMOS Inputs
CE = GND, f = 5 MHz
Inputs = Vee or GND, I/O = 0 mA
13
20
mA
leCSBl
Vee Current (Standby)
TIL Inputs
CE = VIH
0.1
1
mA
IccSB2
Vee Current (Standby)
CMOS Inputs
CE = Vee
0.5
100
p.A
Vpp = Vcc
10
p.A
= Vee or GND, CE = VIH
Ipp
Vpp Load Current
VIL
Input Low ,Voltage
-0.2
0.8
V
VIH
Input High Voltage
2.0
Vee + 1
V
VOL1
Output Low Voltage
IOL = 2.1 mA
0.40
V
VOHl
Output High Voltage
IOH = -1.6mA
VOL2
Output Low Voltage
IOL = 10 p.A
VOH2
Output High Voltage
IOH
=
3.5
V
0.1
V
V
Vcc - 0.1
-10p.A
AC Electrical Characteristics
NMC27Cl024Q
Symbol
Parameter
Conditions
E1S0
Min
tACC
Address to Output Delay
CE = OE = VIL
PGM = VIH
teE
CE to Output Delay
toE
OE to Output Delay
tOF
OE High to Output Float
tcF
CE High to Output Float
tOH
Output Hold from Addresses,
CE or OE, Whichever
Occurred First
DE = VIL, PGM = VIH
CE = VIL, PGM = VIH
CE = VIL, PGM = VIH
OE = VIL, PGM = VIH
CE = DE = VIL
PGM = VIH
1·130
Max
E170,M170
E200,M200
Min
Min
Max
Units
Max
150
170
200
ns
150
170
200
ns
60
75
75
ns
0
50
0
55
0
55
ns
0
50
0
55
0
55
ns
0
0
0
ns
Capacitance TA = + 2S0C, f =
Symbol
1 MHz (Note 2)
Typ
Max
Units
CIN
Input Capacitance
Parameter
Conditions
VIN = OV
12
20
pF
COUT
Output Capacitance
VOUT = OV
13
20
pF
AC Test Conditions
Timing Measurement Reference Level
Inputs
Outputs
Output Load
1 TTL Gate and CL = 100 pF (Note 8)
Input Rise and Fall Times
5: S ns
Input Pulse Levels
0.4SV to 2.4V
0.8V and 2V
0.8Vand2V
AC Waveforms (Notes 6, 7, & 9)
ADDRESSES
-- )
~.g~
)I
ADDRESSES VALID
- -'2.0Y
O.BY
J
- tcr -(NoTEH,5)
!--IcE--
~
2.DY
O.BY
OUTPUT
2.0Y
O.8Y
Hi-Z
J
tOE
(NOTE 3)
-
- t Dr
VALID OUTPUT
"u
rr
u
(NOTES 4. 5)
Hi-Z
-
IoHi-
I - - (NOTE
tAcc - 3)
TLID18806-3
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to tAce-toE aHer the falling edge of CE without impacting tACe;.
Note 4: The tDF and tcF compare level is determined as follows:
High to TRI-STATE. the measured VOH1 (DC) - O.10V
Low to TRI-STATE. the measured VOL1 (DC) + 0.10V
Note 5: TRI-STATE may be attained using OE or CE.
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 p.F ceramic capacnor be used on
every device between Vee and GND.
Note 7: The outputs must be restricted to Vce + 1.0V to avoid latch-up and device damage.
Note 8: 1 TTL Gate: 10L = 1.6 rnA. 10H = - 400 p.A.
CL: 100 pF includes fixture capacitance.
II
Note 9: Vpp may be connected to Vce except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns max.
1-131
Programming Characteristics (Notes 1. 2. 3 & 4)
Symbol
Conditions
Parameter
Typ
Min
Max
Units
tAS
Address Set-Up Time
1
".s
toES
OE Set-Up Time
1
".s
tCES
CE Set-Up Time
1
".s
tos
Data Set-Up Time
1
".s
tyPS
Vpp Set-Up Time
1
".s
tvcs
Vcc Set-Up Time
1
".s
tAH
Address Hold Time
0
".s
tOH
Data Hold Time
1
".s
tOF
Output Enable to Output Float Delay
tpw
Program Pulse Width
CE
=
0
VIL
95
=
tOE
Data Valid From DE
CE
Ipp
Vpp Supply Current during
Programming Pulse
CE = VIL
PGM = VIL
100
VIL
60
ns
105
".s
100
ns
60
mA
Icc
Vcc Supply Current
10
mA
tR
Temp Ambient
20
25
30
'C
Vcc
Power Supply Voltage
6.0
6.25
6.5
V
Vpp
Programming Supply Voltage
12.5
12.75
13.0
V
TCR
Input Rise. Fall Time
VIL
Input Low Voltage
0.0
0.45
VIH
Input High Voltage
2.4
4.0
tiN
Input Timing Reference Voltage
0.8
1.5
2.0
V
tOUT
Output Timing Reference Voltage
0.8
1.5
2.0
V
Programming Waveforms
DATA
V
V
(Note 3)
P~I~M_
!--PROGRAW
ADDRESSES
ns
5
~
~
ifv-,
K:
AODRESS N
~
1
HI-Z
DATA-IN STABLE
ADD.
DATA OUT VAUO
ADD •
If--
-10,
~
~
lAM
vcc~ ~
vPP
BE
:=.....t
~
O.8V
j...tCES_
PQi;j
o2Jv
I
i-toES1
OE o~lv
-IoE-
rTLlO/8808-10
Nole 1: National's standard product warranty applies only to devices programmed to specmcatlons described herein.
Nole 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be Inserted into or removed from a
board with voltage applied to Vpp or Vee.
Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming Is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 p.F capaCitor Is required across VPP. Vee to GND to suppress
spurious voltage transients which may damage the device.
Note 4: Programming and program verify are tested with the Fast Program AlgOrithm. at typical power supply voltages and timings.
1-132
z
Fast Programming Algorithm Flow Chart
o==
I\)
......
o
.....
Q
I\)
0l:Io
INCREMENT ADDR
TLID/BB06-5
FIGURE 1
1-133
Functional Description
DEVICE OPERATION
The six modes of operation of the NMC27C1024 are listed
in Table I. It should be noted that all inputs for the six modes
are at TTL levels. The power supplies required are Vee and
Vpp. The Vpp power supply must be at 12.75V during the
three programming modes, and must be at 5V in the other
three modes. The Vee power supply must be at 6.25V during the three programming modes, and at 5V in the other
three modes.
Read Mode
The NMC27C1024 has two control functions, both of which
must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be
used for device selection. Output Enable (OE) is the output
control and should be used to gate data to the output pins,
independent of device selection. Assuming that addresses
are stable, address access time (tAee) is equal to the delay
from CE to output (teE). Data is available at the outputs toE
after the falling edge of OE, assuming that CE has been low
and addresses have been stable for at least tAee-tOE.
The sense amps are clocked for fast access time. Vee
should therefore be maintained at operating voltage during
read and verify. If Vee temporarily drops below the spec.
voltage (but not to ground) an address transition must be
performed after the drop to ensure proper output data.
Standby Mode
The NMC27C1024 has a standby mode which reduces the
active power dissipation by over 99%, from 110 mW to
0.55 mW. The NMC27C1024 is placed in the standby mode
by applying a CMOS high signal to the CE input. When in
standby mode, the outputs are in a high impedance state,
independent of the OE input.
Output OR-Tying
Because NMC27C1024s are usually used in larger memory
arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended that CE (pin 2) be decoded and used as the primary
device selecting function, while OE (pin 20) be made a common connection to all devices in the array and connected to
the READ line from the system control bus. This assures
that all deselected memory devices are in their low power
standby modes and that the output pins are active only
when data is desired from a particular memory device.
Programming
CAUTION: Exceeding 14V on the Vpp or A9 pin will damage
the NMC27C1024.
Initially, and after each erasure, all bits of the NMC27C1 024
are in the "1" state. Data is introduced by selectively programming "O's" into the desired bit locations. Although only
"O's" will be programmed, both "1 's" and "O's" can be presented in the data word. The only way to change a "0" to a
"1" is by ultraviolet light erasure.
The NMC27C1024 is in the programming mode when the
Vpp power supply is at 12.75V and OE is at VIH. It is required that at least a 0.1 I-'F capacitor be placed across
Vpp, Vee to ground to suppress spurious voltage transients
which may damage the device. The data to be programmed
is applied 16 bits in parallel to the data output pins. The
levels required for the address and data inputs are TTL.
When the address and data are stable, an active low, TTL
program pulse is applied to the PGM input. A program pulse
must be applied at each address location to be programmed. The NMC27C1024 is programmed with the Fast
Programming AlgOrithm shown in Figure 1. Each Address is
programmed with a series of 100 I-'s pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
program with a single 100 I-'s pulse. The NMC27C1024
must not be programmed with a DC Signal applied to the
PGM input.
Programming multiple NMC27C1024s in parallel with the
same data can be easily accomplished due to the simplicity
of the programming requirements. Like inputs of the parallel
NMC27C1024s may be connected together when they are
programmed with the same data. A low level TTL pulse applied to the PGM input programs the paralleled
NMC27C1024s.
TABLE I. Mode Selection
Pins
Mode
CE
(2)
OE
(20)
PGM
(39)
Vpp
(1)
Vee
(40)
Outputs
(3-10,12-19)
Read
VIL
VIL
VIH
Vee
5V
DOUT
Standby
VIH
Don't Care
Don't Care
Vee
5V
Hi-Z
Don't Care
VIH
VIH
Vee
5V
Hi-Z
VIL
VIH
VIL
12.75V
6.25V
DIN
6.25V
DOUT
6.25V
Hi-Z
Output Disable
Program
Program Verify
VIL
VIL
VIH
12.75V
Program Inhibit
VIH
Don't Care
Don't Care
12.75V
1-134
Functional Description
(Continued)
over the NMC27Cl 024 window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents.
Program Inhibit
Programming multiple NMC27Cl024s in parallel with different data is also easily accomplished. Except for CE, all like
inputs (including OE and PGM) of the parallel NMC27Cl024
may be common. A TTL low level program pulse applied to
an NMC27Cl024 PGM input with CE at VIL and Vpp at
12.5V will program that NMC27Cl024. A TTL high level CE
input inhibits the other NMC27Cl024s from being programmed.
The recommended erasure procedure for the NMC27Cl 024
is exposure to short wave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV
intensity x exposure time) for erasure should be a minimum
of 15W-sec/cm2 .
The NMC27Cl024 should be placed within 1 inch of the
lamp tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. Table III
shows the minimum NMC27Cl024 erasure time for various
light intensities.
An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one inch.
The erasure time increases as the square of the distance. (If
distance is doubled the erasure time increases by a factor of
4.) Lamps lose intensity as they age. When a lamp is
changed, the distance has changed, or the lamp has aged,
the system should be checked to make certain full erasure
is occurring. Incomplete erasure will cause symptoms that
can be misleading. Programmers, components, and even
system designs have been erroneously suspected when incomplete erasure was the problem.
Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with Vpp at 12.5V. Vpp must be at
Vee except during programming and program verify.
Manufacturer's Identification Code
The NMC27Cl024 has a manufacturer's identification code
to aid in programming. When the device is inserted in an
EPROM programmer socket, the programmer reads the
code and then automatically calls up the specific programming algorithm for the part. This automatic programming
control is only possible with programmers which have the
capability of reading the code.
The Manufacturer's Identification code, shown in Table II,
specifically identifies the manufacturer and the device type.
The code for the NMC27Cl024 is "SFD6", where "SF" designates that it is made by National Semiconductor, and
"D6" designates a 1 Meg part.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer-the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 p.F ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 p.F bulk electrolytic
capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
The code is accessed by applying 12 ±0.5V to address pin
A9. Addresses A1-AS, A10-A15, and all control pins are
held at VIL. Address pin AO is held at VIL for the manufacturer's code, and held at VIH for the device code. The code is
read on the lower eight data pins, 00-07. Proper code access is only guaranteed at 25'C ±5'C.
ERASURE CHARACTERISTICS
The erasure characteristics of the NMC27Cl024 are such
that erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000A-4000A
range. After programming opaque labels should be placed
TABLE II, Manufacturer's Identification Code
Pins
Ao
(21)
07
(12)
0&
(13)
05
(14)
04
(15)
Manufacturer Code
VIL
1
0
0
VIH
1
1
0
Device Code
02
(17)
01
(18)
0
1
1
1
1
SF
1
0
1
1
0
D6
TABLE III, Minimum NMC27C1024 Erasure Time
Light Intensity
(Mlcro-Watts/cm 2)
Erasure Time
(Minutes)
15,000
20
10,000
25
5,000
50
1-135
00
(19)
Hex
Data
03
(16)
Section 2
EEPROMs
•
Section 2 Contents
Electrically Erasable Programmable Memory Selection Guide ............................
2-3
SERIAL ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY
NMC9306 256-Bit Serial Electrically Erasable Programmable Memory. . . . . . . . . . . . . . . . . . . . .
NMC93C06/C46 256-Bitl1 024-Bit Serial Electrically Erasable Programmable Memory ......
NMC93CS06/CS46 256-Bitl1 024-Bit Serial Electrically Erasable Programmable Memory. . . .
NMC9307 256-Bit Serial Electrically Erasable Programmable Memory. . . . . . . . . . . . . . . . . . . . .
NMC9313B 256-Bit Serial Electrically Erasable Programmable Memory.............. ......
NMC9346 1024-Bit Serial Electrically Erasable Programmable Memory. . . . . . . . . . . . . . . . . . . .
NMC9314B 1024-Bit Serial Electrically Erasable Programmable Memory... .. ... .... ..... .
NMC93C56/C66 2048-Bitl4096-Bit Serial Electrically Erasable Programmable Memory .....
NMC93CS56/CS66 2048-Bitl4096-Bit Serial Electrically Erasable Programmable Memory. . .
NMC93CS06x3/CS46x3/CS56x3/CS66x3 Extended Voltage Serial EEPROM.. ...........
NMC93C06x3/C46x3/C56x3/C66x3 Extended Voltage Serial EEPROM. . . . . . . . . . . . . . . . . . .
2-4
2-11
2-19
2-30
2-36
2-41
2-48
2-53
2-61
2-72
2-83
APPLICATION SPECIFIC EEPROM
NMC95C121024-Bit CMOS EEPROM with DIP Switches... ..... ......... .... ..... ......
2-91
APPLICATIONS NOTES
AB-15 Protecting Data in Serial Electrically Erasable Programmable Memory. . . . . . . . . . . . . ..
AB-18 Electronic Compass Calibration Made Easy with Electrically Erasable
Programmable Memory. .. .... . .. .. .. .. ..... ....... . .. .. .... . .. . ... ... .. ..... .....
AB-22 Automatic Low CostThermostat. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-388 Designing with the NMC9306 .. .. ...... . ..... .. ... .. . ... . .. .... ... .. ..... .....
AN-423 NMC9346-An Amazing Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-431 An Easy/Low Cost Serial Electrically Erasable Programmable Memory Interface....
AN-433 Using the NMC9306 for Configuration and Production Information .. . . . . . . . . . . . . . . .
AN-481 Common I/O Applications for the NMC9306 and NMC9346... ... .. .... ...... ... ..
AN-482 Error Detection and Correction Techniques .................... -.. ..... . .... ... ..
AN-507 Using the NMC93CSXX Family of Electrically Erasable Programmable Memory. . . . ..
Reliability of National Semiconductor's Electrically Erasable Programmable Memory
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2
2-100
2-102
2-103
2-105
2-111
2-114
2-117
2-120
2-123
2-128
2-142
Capacity
Organization
Part
Number
Access
Time
(ns)
Cycle
Time
(ns)
Power
Supply
(V)
Active
(mA)
Standby
(fLA)
DIP
SO
Power Dissipation
Packaging
~
Operating
Temperature
fC~
CMOS EEPROM
256-Bit
16x 16
Serial
NMC93C06
NMC93CS06*
500
500
+5
2
50
8
14
1024-Bit
64x 16
Serial
NMC93C46
NMC93CS46*
500
500
+5
2
50
8
14
2048-Bit
128 x 16
Serial
NMC93C56
NMC93CS56*
500
500
+5
2
50
8
14
256 x 16
Serial
NMC93C66
NMC93CS66*
500
+5
2
4096-Bit
500
50
8
3!::r.
-·0
8:::J
:::Js!'
Q.
m
m
14
."
NMOS EEPROM
:tI
256-Bit
16x 16
I\)
lJ
1024-Bit
64x 16
NMC9306
2
4
NMC9307
2
4
NMC9313B
2
5
NMC9346
2
4
NMC9314B
2
5
"On chip write protection circuitry
Temperature Ranges
C ~ O"C to +70°C
E ~ -40"C to +B5°C
M ~ -55°C to + 125°C
+5
+5
10
3
8
10
3
8
15
5
8
12
3
8
17
5
8
14,8
14,8
C,E,M
0
C
(J)
C,E,M
C
c:
(')
8"
..,
s:
(I)
(I)
(')
_.
0
::s
Q
_.
c:
c..
(I)
9P!"9 UO!J0919S WOl::ld33
iii
~
§
I
~NaHonal
~ Semiconductor
NMC9306 256-Bit Serial Electrically Erasable
Programmable Memory
General Description
Features
The NMC9306 is a 256-bit non-volatile sequential access
memory fabricated using advanced floating gate N-channel
E2PROM technology. It is accessed via the simple
MICROWIRETM serial interface and is designed for data
storage and/or timing applications. The device contains 256
bits of read/write memory divided into 16 registers of 16 bits
each. Each register can be serially read or written by a
COP400 series controller. Written information is stored in a
floating gate cell with at least 10 years data retention and
can be updated by an erase-write cycle. The NMC9306 has
been designed to meet applications requiring up to 4 x 104
erase/write cycles per register. A power down mode reduces power consumption by 70 percent.
Ii
•
•
•
•
•
•
•
•
•
Low cost
Single supply operation (5V ± 10%)
TTL compatible
16X16 serial read/write memory
MICROWIRE compatible serial I/O
Compatible with COP400 processors
Low standby power
Non-volatile erase and write
Reliable floating gate technology
Designed for 40,000 erase/write cycles
Block Diagram
-..
VPI'
GENERATOR
~VCC
1 VPP
_I
~
~
DECODER
1/16
fa
~
ADDRESS
LATCHES
E'PROM
256 BITS
(16xI6)
l6
t-
R/WAMPS
Pin Names
I
~6
4
DI
rl
DATA
REGISTER
(17 BITS)
......
. . . >-
I
ClKI.,L..
DO
(I~
INSTRUCTION
REGISTER ClK
(9 BITS)
--CS
SK
J:
INSTRUCTION
DECODE.
CONTROL
AND
CLOCK
GENERATORS
-
-
~
TL/O/5029-1.
2-4
CS
Chip Select
SK
Serial Data Clock
01
Serial Data Input
DO
Serial Data Output
Vee
Power Supply
GND
Ground
z
:s:
o
Connection Diagram
CD
C.:I
O-Pin
SO Package (MO)
Dual-In-Line Package (N)
cs-
1
v
o
en
CSOB VCC
B r-VCC
SK- 2
SK
2
7
NC
01
3
6
NC
00
4
5
~o
01- 3
TL/D/5029-11
00- 4
Top View
See NS Package Number MOOA
TL/D/5029-10
Top View
See NS Package Number NOOE
Ordering Information
Commercial Temperature Range (O·C to
Vee = 5V ± 100/0
+ 700C)
Order Number
Device Marking
NMC9306N
NMC9306MB
NMC9306N
9306
Extended Temperature Range (- 40·C to
Vee = 5V ± 10%
+ 05·C)
Order Number
Device Marking
NMC9306EN
NMC9306EM8
NMC9306EN
9306E
EJI
2-5
Absolute Maximum Ratings
Operating Conditions
Voltage Relative to GND
Ambient Storage Temperature
Lead Temperature
(Soldering, 10 seconds)
ESD rating
Ambient Operating Temperature
O·Cto +70·C
NMC930S/COP494
- 40·C to + 85·C
NMC930SE
Positive Supply Voltage
4.5Vt05.5V
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
+SVto -0.3V
- S5·C to + 125·C
300"C
2000V
Electrical Characteristics Vee = 5V ±10% unless otherwise specified
Parameter
NMC930S, NMC930SE
Operating Current (Ieel)
NMC930S
NMC930SE
Standby Current (lee2)
NMC930S
NMC930SE
Input Voltage Levels
VIL
VIH
VIL
VIH
Conditions
Part Number
Operating Voltage (Vee>
Min
4.5
=
Vee =
Vee =
Vee =
Vee
=
5.5V, CS =
5.5V, CS =
5.5V, CS =
5.5V, CS
Typ
Max
Units
5.5
V
1
10
mA
1
12
mA
0
3
mA
0
4
mA
NMC930S
-0.1
2.0
0.8
Vee + 1
V
V
NMC930SE
-0.1
2.0
0.8
Vee + 1
V
V
0.4
V
V
10
/LA
Output Voltage Levels
VOL
VOH
NMC930S, NMC930SE
IOL = 2.1 mA
IOH = - 400 /LA
2.4
= 5.5V
= 5.5V, CS = 0
Input Leakage Current
NMC930S, NMC930SE
VIN
Output Leakage Current
NMC930S, NMC930SE
VOUT
SK Frequency
SK HIGH TIME tsKH (Note 2)
SK LOW TIME tSKL (Note 2)
NMC930S
0
1
1
SK Frequency
SK HIGH TIME tSKH (Note 2)
SK LOW TIME tSKL (Note 2)
NMC930SE
0
1
1
Input Set-up and Hold Times
CS
tess
tesH
DI
tOiS
tOIH
NMC930S, NMC930SE
Output Delay
DO
tpOI
tpoo
NMC930S, NMC930SE
Erase/Write Pulse Width
(tE/W) (Note 1)
NMC930S, NMC930SE
10
/LA
250
kHz
/Ls
/Ls
250
0.2
0
0.4
0.4
CL = 100pF
VOL = 0.8V, VOH = 2.0V
VIL = 0.45V, VIH = 2.4V
10
kHz
/Ls
/Ls
/Ls
/Ls
/Ls
/Ls
2
2
/Ls
/Ls
30
ms
CSLowTime
NMC930S, NMC930SE
1
/Ls
(tes) (Note 3)
Note 1: IE/W measured 10 rising edge of SK or CS, whichever occurs last.
Note 2: The SK frequency spec. specifies a minimum SK clock period of 4 "s, therefore in an SK clock cycle, tsKH + tsKL must be grealer than or equal to 4 "s.
e.g. If tsKL = 1 "s then the minimum tsKH = 3 "S in order to meet the SK frequency specification.
Note 3: CS must be brcughtlow for a minimum of 1 fIos (lesl between consecutive instruction cycles.
2-S
z
3:
Functional Description
(")
The NMC930S is a small peripheral memory intended for
use with COPSTM controllers and other non-volatile memory
applications. Its organization is sixteen registers and each
register is sixteen bits wide. The input and output pins are
controlled by separate serial formats'. Seven 10-bit instructions can be executed. The instruction format has a logical 0
as a start bit, followed by a logical 1, four bits as an op code,
and four bits of address. An SK clock cycle is necessary
after CS equals logical 0 followed by a logical 1 before the
instruction can be loaded. The on-chip programming-voltage generator allows the user to use a single power supply
(Vee). Only during the read mode is the serial output (DO)
pin valid. During all other modes the DO pin is in
TRI-STATE®, eliminating bus contention.
set to O's). After an ERASE instruction is input, CS is
dropped low. This falling edge of CS determines the start of
programming. The register at the address specified in the
instruction is then set entirely to 1'so When the erase/write
programming time (tE/W) constraint has been satisfied, CS
is brought up for at least one SK period. A new instruction
may then be input, or a low-power standby state may be
achieved by dropping CS low.
CD
Co)
o
en
WRITE (Note 4)
The WRITE instruction is followed by 16 bits of data which
are written into the specified address. This register must
have been previously erased. Like any programming mode,
erase/write time is determined by the low state of CS following the instruction. The on-chip high voltage section only
generates high voltage during these programming modes,
which prevents spurious programming during other modes.
When CS rises to VIH the programming cycle ends. All programming modes sho'uld be ended with CS high for one SK
period, or followed by another instruction.
READ
The read instruction is the only instruction which outputs
serial data on the DO pin. After a READ instruction is received, the instruction and address are decoded, followed
by data transfer from the memory register into a lS-bit serial-out shift register. A dummy bit (logical '0') precedes the
16-bit data output string. Output data changes are initiated
by a low to high transition of the SK clock.
CHIP ERASE (Note 4)
Entire chip erasing is provided for ease of programming.
Erasing the chip means that all registers in the memory array have each bit set to a 1. Each register is then ready for a
WRITE instruction.
ERASE/WRITE ENABLE AND DISABLE
Programming must be preceded once by a programming
enable (EWEN) instruction. Programming remains enabled
until a programming disable (EWDS) instruction is executed.
The programming enable instruction (EWEN) is needed to
keep the part in the enable state if the power supply (Vecl
noise falls below operating range. The programming disable
instruction is provided to protect against accidental data disturb. Execution of a READ instruction is independent of both
EWEN and EWDS instructions.
CHIP WRITE (Note 4)
All registers must be erased before a chip write operation.
The chip write cycle is identical to the write cycle, except for
the different op code. All registers are simultaneously written with the data pattern specified in the instruction.
Note 4: During a programming mode (write. erase. chip erase. chip write).
SK clock is only needed while the actual instruction, i.e., start bit, op
code, address and data, is being input. It can remain deactivated
ERASE (Note 4)
during the Erase/Write pulse width (!eIW).
Like most E2PROMS, the register must first be erased (all
bits set to 1's) before the register can be written (certain bits
Instruction Set
Instruction
SB
OpCode
Address
READ
01
10xx
A3A2A1AO
WRITE
01
01xx
A3A2A1AO
ERASE
01
llxx
A3A2A1AO
EWEN
01
0011
EWDS
01
0000
ERAL
01
0010
WRAL
01
0001
XXXX
XXXX
XXXX
XXXX
Data
Comments
Read Register A3A2A1AO
D15-DO
Write Register A3A2A 1AO
Erase Register A3A2A 1AO
Erase/Write Enable
Erase/Write Disable
Erase All Registers
D15-DO
Write All Registers
NMC9306 has 7 instructions as shown. Nots that MSB of any given instruction is a "1" and is viewed as a start bit in
the interface sequence. The next 6 bits carry the op code and the 4·bit address for 1 of 16. 16·bit registers.
X is a don't care state.
2-7
•
NMC9306
-I
3"
5"
Ul
c
Synchronous Data Timing
iii"
"
SK
4 j.LS*
_ _---JI·
ISKH
l
Ul
-,
3
tn
·11
ISKL
0.4 j.LS
t Dis
iil
!'--_ _
I'
_I'
-I
I-
-I
0.4 j.LS
tOIH
DI
'"Co
cs
2 j.LS
I.
,I
tpoo
DO
2 j.LS
t
P01
VOH
\
VOL
/
TL/D/5029-13
-This is the minimum SK period and is 5,u. for NMC9306M
-I
3'
Instruction Timing
lJL.rL..r'LI1
SK
S'
ce
READ
01
c
iii'
-\_---
CS /
~,
"
0
~::x?\
ce
...
SI)
3
1101_ _ _ _ _ _ _ _ _ _ _ _ __
UI
~
~
DO
3-
5·
TLID/5029-14
ffi
.s
U1..n.I---t:
SK
I\)
cO
WRITE
CS
tE/w ,
j
01~'~~X!"\
_;..,....._ _ _
--1
II
/,C::X::X:
TL/D/5029-15
SK
ERASE ( CS
01-1'
TLlD/5029-16
*tE/W measured to rising edge of SK or CS, whichever occurs last.
90E6~WN
II
NMC9306
-I
3"
Instruction Timing (Continued)
5"
ca
SK
EWEN
EWIIS
CS
(ERASE/WRITE
ENABLE/DISABLE)
r
DI~O
- --- ---------- ,,'-___________
I
~
c
i"
ca
DJ
3
en
g
ENABLE=ll
DISABLE=OO
Tl/0/5029-17
go
c:
(1)
.e,
SK
~
WHAL
(WRllE ALL) ~
CS /
-
-~
o
O/l~:xn
m--.f7\D
II
/1\
x:
TU0/5029-18
SK
BlAt
(ERABEALL)
DI~O
00\D~
TUO/5029-19
". E/W measured to rising edge of SK or es, whichever occurs last
z
3:
~NaHonal
oCD
oo
Co)
~ Semiconductor
CJ)
.......
z
NMC93C06/C46 256-Bit/1024-Bit Serial
Electrically Erasable Programmable Memory
3:
oCD
Co)
o
General Description
Compatibility with Other Devices
The NMC93C06/NMC93C46 are 256/1024 bits of CMOS
electrically erasable memory divided into 16-bit registers.
They are fabricated using National Semiconductor's floating-gate CMOS process for high speed and low power. They
operate from a single 5V supply since Vpp is generated onboard. The serial organization allows the NMC93G06/
NMC93C46 to be packaged in an 8-pin DIP or 8-pin SO
package to save board space.
The memories feature a serial interface with the instruction,
address, and write data, input on the Data-In (01) pin. All
read data and device status is output on the Data-Out (DO)
pin. A low-to-high transition of shift clock (SK) shifts all data
in and out. This serial interface is MICROWIRETM compatible for simple interface to standard microcontrollers and microprocessors. There are 7 instructions: Read, Erase/Write
Enable, Erase, Erase All, Write, Write All, Erase/Write Disable. The NMC93C06/NMC93C46 do not require an erase
cycle prior to the Write and Write All instructions. The Erase
and Erase All instructions are available to maintain complete read and programming compatibility with the NMOS
NMC9346. All programming cycles are completely selftimed for simplified operation. The busy status is available
on the DO pin to indicate the completion of a programming
cycle. EEPROMs are shipped in the erased state where all
bits are logical 1's.
These memories are pin compatible to National Semiconductor's NMOS EEPROMs, NMC9306 and NMC9346. The
NMC93C06/NMC93C46 are both pin and function compatible with the NMC93C56 2048-bit EEPROM and the
NMC93C66 4096-bit EEPROM with the one exception that
both of these larger devices require two additional address
bits.
Features
• Typical active current 400 J.LA; Typical standby current
25 J.LA
• Reliable CMOS floating gate technology
• 5V only operation in all modes
• MICROWIRE compatible serial I/O
• Self-timed programming cycle
• Device status signal during programming mode
• Over 40 years data retention
• Designed for 100,000 write cycles
Block Diagram
CS---------------------+r-~IN~sm;;U~~ON~
SK---;:::===i------1 CO~~~~~~GlC,
01
_Vee
AND CLOCK
GENERATORS.
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
00_---------1
TLlD/B790-3
2-11
"'"
CJ)
~
o
C")
Connection Diagrams
C»
o
:::E
z
.....
CD
Q
o
C»
o
C")
:::E
z
csOa
Dual-In-Llne Package (N)
SK
2
7
Vee
HC
01
3
6
HC
00
4
5
GNO
csOa
Pin Names
CS
SK
01
DO
GND
Vee
SO Package (M8)
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
SK
2
7
Vee
HC
01
3
6
NC
5GNO
004
TL/D/8790-1
TL/0/8790-2
Top View
Top View
See NS Package Number N08E
See NS Package Number M08A
Ordering Information
Commercial Temp. Range (O"C to
Vee = SV ± 10%
+ 70"C)
Order Number
NMC93C06N/NMC93C46N
NMC93C06MS/NMC93C46MS
Extended Temp. Range (- 40·C to
Vee = SV ± 10%
+ 8S·C)
Order Number
NMC93C06EN/NMC93C46EN
NMC93C06EMS/NMC93C46EMS
Military Temp. Range (- SS·C to
+ 12S·C)
Order Number
NMC93C06MN/NMC93C46MN
NMC93C06MMS/NMC93C46MMS
2-12
z
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
All Input or Output Voltages
with Respect to Ground
Ambient Storage Temperature
Lead Temperature
(Soldering. 10 seconds)
ESDrating
s:
o
Operating Conditions
(Note 1)
Ambient Operating Temperature
NMC93C06/46
NMC93C06/46E
NMC93C06/46M
+6.5Vto -0.3V
CD
Co)
O'Cto +70'C
-40'Cto +85'C
-55'C to + 125'C
Positive Supply Voltage
4.5Vt05.5V
ICCl
ICC2
ICC3
III
IOl
+300'C
o0l:Io
Co)
01
Parameter
Part Number
Conditions
Max
Units
Operating Current
CMOS Input Levels
NMC93C06/46
NMC93C06/46E
NMC93C06/46M*
CS = VIH. SK = 1 MHz
SK = 0.5 MHz
SK = 0.5 MHz
2
2
2
mA
Operating Current
TIL Input Levels
NMC93C06/46
NMC93C06/46E
NMC93C06/46M
CS = VIH. SK = 1 MHz
SK = 0.5 MHz
SK = 0.5 MHz
3
3
4
mA
Standby Current
NMC93C06/46
NMC93C06/46E
NMC93C06/46M
CS
50
100
100
p.A
NMC93C06/46
NMC93C06/46E
NMC93C06/46M
VIN = OV to Vcc
-2.5
-10
-10
2.5
10
10
p.A
NMC93C06/46
NMC93C06/46E
NMC93C06/46M
VOUT = OVto Vcc
-2.5
-10
-10
2.5
10
10
p.A
-0.1
2
VCC + 1
Output Leakage
Vil
VIH
Input Low Voltage
Input High Voltage
VOL1
Output Low Voltage
NMC93C06/46
NMC93C06/46E
NMC93C06/46M
=
=
IOH
VOl2
VOH2
Output Low Voltage
Output High Voltage
IOl = 10 p.A
IOH = -10 p.A
ISK
SK Clock Frequency
tcs
tcss
-400 p.A
NMC93C06/46
NMC93C06/46E
NMC93C06/46M
0.8
0.4
0.4
0.4
IOl = 2.1 mA
IOl = 2.1 mA
IOl = 1.8 mA
Output High Voltage
tSKl
Min
OV
VOHl
tSKH
V
V
2.4
0.2
Vcc - 0.2
0
0
0
1
0.5
0.5
V
MHz
NMC93C06/46
NMC93C06/46E
NMC93C06/46M
(Note 2)
(Note 3)
(Note 3)
250
500
500
ns
NMC93C06/46
NMC93C06/4SE
NMC93COS/46M
(Note 2)
(Note 3)
(Note 3)
250
500
500
ns
MinimumCS
Low Time
NMC93C06/46
NMC93COS/46E
NMC93C06/46M
(Note 4)
(NoteS)
(NoteS)
250
500
500
ns
CS Setup Time
NMC93COS/46
NMC93COS/4SE
NMC93C06/46M
Relative to SK
50
100
100
ns
SK High Time
SKLowTime
Z
s:
-65'Cto + 150'C
2000V
Input Leakage
01
......
o
CD
DC and AC Electrical Characteristics Vcc = 5V ± 10% unless otherwise specified
Symbol
o
o
• Note: Thruout this table "M" reiers to temperature range (- SS'C to + 12S'C). not package.
2-13
DC and AC Electrical Characteristics Vee = 5V ±10% (Continued)
Symbol
Parameter
Part Number
Dr Setup Time
tDIS
tcsH
CSHoldTime
tDIH
DIHoldTime
Output Delay to "1"
tpDl
Output Delay to "0"
tpDO
CS to Status Valid
tsv
CStoDOin
TRI-STATE@
tDF
Conditions
Min
Relative to SK
100
200
200
ns
Relative to SK
0
ns
NMC93C06/46
NMC93C06/46E
NMC93C06/46M
Relative to SK
100
200
200
ns
NMC93C06/46
NMC93C06/46E
NMC93C06/46M
ACTest
NMC93C06/46
NMC93C06/46E
NMC93C06/46M
ACTest
NMC93C06/46
NMC93C06/46E
NMC93C06/46M
ACTest
NMC93C06/46
NMC93C06/46E
NMC93C06/46M
CS = VIL
ACTest
NMC93C06/46
NMC93C06/46E
NMC93C06/46M
Max
Units
500
1000
1000
ns
500
1000
1000
ns
500
1000
1000
ns
100
200
200
ns
10
ms
Write Cycle Time
twp
Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause pennanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in operational sections of the specification is not implied. Exposure to absolute
maximum rating condHions for extended periods may affect device reliabilHy.
Note 2: The SK frequency specification for Commercial parts specifies a minimum SK clock period of II's, therefora in an SK clock cycle tSKH + tsKL must be
greater than or equal to II'S. For example if tsKL = 250 ns then the minimum tSKH = 750 ns in order to meet the SK frequency specHication.
Note 3: The SK frequency specification for Extended Temperature and Military parts specifies a minimum SK clock period of 21's, therefore in an SK clock cycle
tSKH + tsKL must be greater than or equal to 21's. For example, if tsKL = 500 ns then the minimum tsKH = 1.5 I's in order to meet the SK frequency specHication.
Note 4: For Commercial parts CS must be brought low for a minimum of 250 ns (tcsl between consecutive Instruction cycles.
Note 5: For Extended Temperature and Military parts CS must be brought low for a minimum of 500 ns (tcsl between consecutive instruction cycles.
Note 6: This parameter is periodically sampled and not 100% tested.
CapaCitance (Note 6)
TA
=
25°C, f
Symbol
=
AC Test Conditions
1 MHz
Test
Output Load
Max
Units
COUT
Output CapaCitance
Typ
5
pF
CIN
Input CapaCitance
5
pF
2-14
1 TTL Gate and CL
=
100pF
Input Pulse Levels
0.4Vt02.4V
Timing Measurement Reference Level
Input
Output
Wand2V
0.8Vand2V
Functional Description
The NMC93C06/NMC93C46 has 7 instructions as described below. Note that the MSB of any instruction is a "1"
and is viewed as a start bit in the interface sequence. The
next 8 bits carry the op code and the 6-bit address for selection of 1 of 16 or 64 16-bit registers.
Write (WRITE)
The Write (WRITE) instruction is followed by 16 bits of data
to be written into the specified address. After the last bit of
data is clocked in on the data-in (01) pin, CS must be
brought low before the next rising edge of the SK clock.
This falling edge of the CS initiates the self-timed programming cycle. The DO pin indicates the READY/BUSY status
of the chip if CS is brought high after a minimum of 250 ns
(tes). DO = logical "0" indicates that programming is still in
progress. DO = logical "1" indicates that the register at the
address specified in the instruction has been written with
the data pattern specified in the instruction and the part is
ready for another instruction.
Read (READ):
The Read (READ) instruction outputs serial data on the DO
pin. After a READ instruction is received, the instruction and
address are decoded, followed by data transfer from the
selected memory register into a 16-bit serial-out shift register. A dummy bit (logical "0") precedes the 16-bit data output string. Output data changes are initiated by a low-to-high
transition of the SK clock.
Erase All (ERAL)
The ERAL instruction will simultaneously program all registers in the memory array and set each bit to the logical "1"
state. The Erase All cycle is identical to the ERASE cycle
except for the different op-code.
As in the ERASE mode, the DO pin indicates the READY /
BUSY status of the chip if CS is brought high after a minimum of 250 ns (tes).
Erase/Write Enable (EWEN):
When Vee is applied to the part, it "powers up" in the
Erase/Write Disable (EWDS) state. Therefore, all programming modes must be preceded by an Erase/Write Enable
(EWEN) instruction. Once an Erase/Write Enable instruction is executed, programming remains enabled until an
Erase/Write Disable (EWDS) instruction is executed or Vee
is removed from the part.
Erase (ERASE):
Write All (WRAL):
The ERASE instruction will program all bits in the specified
register to the logical "1" state. CS is brought low following
the loading of the last address bit. This falling edge of the
CS pin initiates the self-timed programming cycle.
The WRAL instruction will simultaneously program all registers with the data pattern specified in the instruction. As in
the WRITE mode, the DO pin indicates the READY/BUSY
status of the chip if CS is brought high after a minimum of 50
ns (les).
The DO pin indicates the READY/BUSY status of the chip if
CS is brought high after a minimum of 250 ns (les).
DO = logical "0" indicates that programming is still in progress. DO = logical "1" indicates that the register, at the
address specified in the instruction, has been erased, and
the part is ready for another instruction.
Erase/Write Disable (EWDS):
To protect against accidental data disturb, the Erase/Write
Disable (EWDS) instruction disables all programming modes
and should follow all programming operations. Execution of
a READ instruction is independent of both the EWEN and
EWDS instructions.
Instruction Set for the NMC93C06/46
Instruction
S8
OpCode
Address
READ
1
10
A5-AO
Reads data stored in memory.
Write enable must precede all programming modes.
EWEN
1
00
11XXXX
ERASE
1
11
A5-AO
WRITE
1
01
A5-AO
ERAL
1
00
10XXXX
WRAL
1
00
01XXXX
EWDS
1
00
OOXXXX
Data
Comments
Erase register A5A4A3A2A 1AO.
015-00
Writes register.
015-00
Writes all registers.
Erase all registers.
Disables all programming instructions.
2-15
•
CD
(S
(W)
en
Timing Diagrams
o
::E
z
.....
Synchronous Data Timing
I
CD
CI
1 ~s·
less
~
tSKH
f;
-I'
i-"
tsKL-
tcsH
I
::E
--
Z
tOIS
.l tolH
I
X
X
~tpOl
::::1 tPDD
DO (PROGRAM) V
VOH
:jtor
.~
lk
tsv~.
::ltOF
STATUS VAUO
OL
TLlD/8790-4
'This Is the minimum SK period (Note 2).
Note 2: The SK frequency specification for Commercial parts specifies a minimum SK clock period of t ,",S, therefore In an SK clock cycle isKH
greater than or equal to t ,",s. For example ~ tSKL
= 250 ns then the minimum isKH =
+
isKL must be
750 ns in order to meet the SK frequency specification.
READ:
21
11
21
m~~~____~111~__________________~2~
DO----------~~)[XJ()[XJ0)_
TLlD/8790-5
'Address bits A5 and A4 become "don't care" for NMC93C06.
WEN:
DO = TRI-STATE
SK
01
--A. .
O____O,,!l
1
~____~~'--_____________
TLlD/8790-6
2-16
z
s:
Timing Diagrams (Continued)
DO
cs
=
oCD
oo
Co)
EWDS:
TRI·STATE
0)
J
.......
Z
s:
o
CD
Co)
o
"'"
0)
SK
OI~O
o
o
TLlD/B790-7
WRITE:
cs
J
L
SK
01
OO--~b~t
==!
READY
\...
t wp
TL/D/B790-B
'Address bits A5 and A4 become "don't care" for NMC93C06.
WRAL:
CSJ
SK
01
a
o
o
oo----------+L----.\,
BUSY~
~tw~
TL/D/B790-9
2·17
Timing Diagrams (Continued)
ERASE:
SK
csJ
DI
Do~m~I~-~~A~TE------------------~I~!----~~II--~~s~ri~)J~~
TLiD/8790-10
ERAL:
nntu-t..Jl..JL
SK
CS/r--------------------------~I!~I
tcs-
I~~~----~
CHECK STATUS
STANDBY
1lIlllIlll7tA,
DI ~.....O_0...Jf1\ 0
OO ___
m_I-_ST_Arr
________________________________
~~~--_L
J-~l--I
TL/D/8790-11
2-18
z
:s:
(')
~National
~
co
(0)
Semiconductor
(')
en
oQ)
......
(')
en
NMC93CS06/CS46 256-Bit/1024-Bit Serial
Electrically Erasable Programmable Memories
""
Q)
General Description
The NMC93CS06INMC93CS46 are 256/1024 bits of
read/write memory divided into 16/64 registers of 16 bits
each. N registers (N ~ 16 or N ~ 64) can be protected
against data modification by programming into a special onchip register called the memory protect register the address
of the first register to be protected. This address can be
locked into the device, so that these registers can be permanently protected. Thereafter, all attempts to alter data in
a register whose address is equal to or greater than the
address stored in the protect register will be aborted.
The read instruction loads the address of the first register to
be read into a 6-bit address pointer. Then the data is
clocked out serially on the DO pin and automatically cycles
to the next register to produce a serial data stream. In this
way the entire memory can be read in one continuous data
stream or as registers of varying length from 16 to
256/1024 bits. Thus, the NMC93CS06/NMC93CS46 can be
viewed as a non-volatile shift register.
in the protect register then the data is written 16 bits at a
time into one of the 16/64 data registers. If CS is brought
high following the initiation of a write cycle the DO pin indicates the ready/busy status of the chip.
National Semiconductor's EEPROMs are designed and
tested for applications requiring extended endurance. Refer
to device operation for further endurance information. Data
retention is specified to be greater than 40 years.
Features
• Write protection in user defined section of memory
• Typical active current 400 p.A; Typical standby current
25 p.A
II Reliable CMOS floating gate technology
1.'1 5 volt only operation in all modes
• Microwire compatible serial I/O
• Self-timed programming cycle
• Device status Signal during programming mode
1/ Sequential register read
III Over 40 years data retention
II Designed for 100,000 write cycles
The write cycle is completely self-timed. No separate erase
cycle is required before write. The write cycle is only enabled when pin 6 (program enable) is held high. If the address of the register to be written is less than the address
Block Diagram
CS----------------------~~_;IN~;m;u~cr;IO~N~l
SK---r===::::;i-----+j
DI
DECODER,
CONTROL LOGIC,
AND CLOCK
GENERATORS.
+-Vcc
1+-----------1+-------......--
ADDRESS COMPARE
AND
WRITE ENABLE
L..._ _ _--'EN
PRE
PE
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
oo.--------------~
TLl0/920B-3
2-19
CD
"'It
(I)
(,)
.......
CD
o
(I)
(,)
CO)
0)
(,)
:::i
z
Connection Diagrams
PIN OUT:
Dual-In-Line Package (N)
~o'~
SK2
7
PRE
01
3
6
PE
00
4
5
~O
TLlO/9208-1
PIN OUT:
Pin Names
CS Chip Select
SK Serial Data Clock
01
Serial Data Input
DO Serial Data Output
GNO Ground
PE Program Enable
PRE Protect Register Enable
Vee Power Supply
SO Package (M)
NC- 1
\,J
14 :-NC
CS- 2
13 ~Vcc
12 i-PRE
SK- 3
Top View
NC- 4
11 i-NC
01- 5
10 i-PE
00- 6
9 i-GNO
NC- 7
8 i-NC
See NS Package Number NOSE
TL/0/9208-2
Top View
See NS Package Number M14A
Ordering Information
Commercial Temp. Range (O'C to
Vee = 5V ± 10%
+ 70'C)
Order Number
NMC93CS06N/NMC93CS46N
NMC93CS06M/NMC93CS46M
Extended Temp. Range (- 40'C to
Vee = 5V ± 10%
+ 85'C)
Order Number
NMC93CS06EN/NMC93CS46EN
NMC93CS06EM/NMC93CS46EM
Military Temp. Range (-55'C to
+ 125'C)
Order Number
NMC93CS06MN/NMC93CS46MN
NMC93CS06MM/NMC93CS46MM
2-20
Absolute Maximum Ratings
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Ambient Operating Temperature
NMC93CS06/NMC93CS46
NMC93CS06E/NMC93CS46E
NMC93CS06M/NMC93CS46M
(Mil. Temp.)
Ambient Storage Temperature
-65'C to + 150'C
All Input or Output Voltages
with Respect to Ground
+6.5V to -0.3V
Lead Temperature (Soldering, 10 sec.)
ESDrating
Positive Power Supply
ICC1
ICC2
ICC3
IlL
IOL
2000V
5V ±10% unless otherwise specilied
Parameter
Part Number
Conditions
Max
Units
Operating Current
CMOS Input Levels
NMC93CS06/NMC93CS46
NMC93CS06E/NMC93CS46E
NMC93CS06M/NMC93CS46M*
CS = VIH, SK = 1 MHz
SK = 0.5 MHz
SK = 0.5 MHz
2
2
2
rnA
Operating Current
TIL Input Levels
NMC93CS06INMC93CS46
NMC93CS06E/NMC93CS46E
NMC93CS06M/NMC93CS46M
CS = VIH, SK = 1 MHz
SK = 0.5 MHz
SK = 0.5 MHz
3
3
4
rnA
Standby Current
NMC93CS06/NMC93CS46
NMC93CS06E/NMC93CS46E
NMC93CS06M/NMC93CS46M
CS= OV
50
100
100
p.A
NMC93CS06/NMC93CS46
NMC93CS06E/NMC93CS46E
NMC93CS06M/NMC93CS46M
VIN = OV to Vcc
-2.5
-10
-10
2.5
10
10
p.A
NMC93CS06INMC93CS46
NMC93CS06E/NMC93CS46E
NMC93CS06M/NMC93CS46M
VOUT = OV to Vcc
-2.5
-10
-10
2.5
10
10
p.A
-0.1
0.8
VCC + 1
V
0.4
0.4
0.4
V
Input Leakage
Output Leakage
VIL
VIH
Input Low Voltage
Input High Voltage
VOL1
Output Low Voltage
NMC93CS06/NMC93CS46
NMC93CS06E/NMC93CS46E
NMC93CS06M/NMC93CS46M
IOL = 2.1 rnA
IOL = 2.1 mA
IOL = 1.8 rnA
Output High Voltage
IOH = -400 p.A
VOL2
VOH2
Output Low Voltage
Output High Voltage
IOL = 10 p.A
IOH = -10 p.A
ISK
SK Clock Frequency
tSKL
les
tcss
SK High Time
NMC93CS06INMC93CS46
NMC93CS06E/NMC93CS46E
NMC93CS06M/NMC93CS46M
2.4
0.2
Vcc - 0.2
0
0
0
1
0.5
0.5
V
MHz
NMC93CS06/NMC93CS46
NMC93CS06E/NMC93CS46E
NMC93CS06M/NMC93CS46M
(Note 2)
(Note 3)
(Note 3)
250
500
500
ns
NMC93CS06/NMC93CS46
NMC93CS06E/NMC93CS46E
NMC93CS06M/NMC93CS46M
(Note 2)
(Note 3)
(Note 3)
250
500
500
ns
MinimumCS
Low Time
NMC93CS06/NMC93CS46
NMC93CS06E/NMC93CS46E
NMC93CS06M/NMC93CS46M
(Note 4)
(Note 5)
(Note 5)
250
500
500
ns
CS Setup Time
NMC93CS06INMC93CS46
NMC93CS06E/NMC93CS46E
NMC93CS06M/NMC93CS46M
Relative to SK
50
100
100
ns
50
100
100
ns
SKLowTime
NMC93CS06/NMC93CS46
Relative to SK
NMC93CS06E/NMC93CS46E
NMC93CS06M/NMC93CS46M
'Throughout this table "M" refers to temperature range (- 55'C to + 125'C), not package.
tpRES
Min
2
VOH1
tSKH
4.5Vt05.5V
+300'C
DC and AC Electrical Characteristics Vcc =
Symbol
O'Cto +70'C
- 40'C to + 85'C
-55'Cto + 125'C
PRE Setup Time
2·21
•
DC and AC Electrical Characteristics Vee =
Symbol
tPES
tOIS
DI Setup Time
tcSH
CSHoldTime
- tpEH
PEHoldTime
tpREH
PRE Hold Time
tOIH
DIHoldTime
tpOI
tpoo
tsv
tOF
Part Number
Conditions
Min
NMC93CS06INMC93CS46
NMC93CS06E/NMC93CS46E
NMC93CS06M/NMC93CS46M
Relative to SK
50
100
100
ns
NMC93CS06/NMC93CS46
NMC93CS06E/NMC93CS46E
NMC93CS06M/NMC93CS46M
Relative to SK
100
200
200
ns
Relative to SK
0
ns
Relative to CS
Relative to CS
Relative to CS
250
500
500
ns
Relative to SK
0
ns
Relative to SK
100
200
200
ns
Parameter
PE Setup Time
Output Delay to "1"
Output Delay to "0"
CS to Status Valid
CSto DO in
TRI-STATE®
5V ± 10% unless otherwise specified (Continued)
NMC93CS06/NMC93CS46
NMC93CS06E/NMC93CS46E
NMC93CS06M/NMC93CS46M
NMC93CS06INMC93CS46
NMC93CS06E/NMC93CS46E
NMC93CS06M/NMC93CS4SM
Max
Units
NMC93CS06INMC93CS46
NMC93CS06E/NMC93CS4SE
NMC93CSOSM/NMC93CS46M
ACTest
500
1000
1000
ns
NMC93CS06/NMC93CS46
NMC93CS06E/NMC93CS46E
NMC93CSOSM/NMC93CS4SM
ACTest
500
1000
1000
ns
NMC93CS06/NMC93CS4S
NMC93CS06E/NMC93CS46E
NMC93CSOSM/NMC93CS46M
ACTest
500
1000
1000
ns
100
200
200
ns
NMC93CSOS/NMC93CS46
NMC93CSOSE/NMC93CS4SE
NMC93CS06M/NMC93CS4SM
CS = VIL
ACTest
10
ms
Write Cycle Time
twp
Nole 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specHication is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: The SK frequency specification for Commercial parts specifies a minimum SK clock period of 1 microsecond, therefore in an SK clock cycle tSKH + tsKL
must be greater than or equal to 1 microsecond. For example If tSKL ~ 250 ns then the minimum tsKH ~ 750 ns in order to meet the SK frequency specification.
Note 3: The SK frequency specHicatlon for Extended Temperature and Military parts specifies a minimum SK clock period of 2 microseconds, therefore in an SK
clock cycle tsKH + tsKL must be greater than or equal to 2 microseconds. For example, if tsKL ~ 500 ns then the minimum tsKH ~ 1.5 microseconds In order to
meet the SK frequency specHication.
Nole 4: For Commercial parts CS must be brought low for a minimum of 250 ns (tcs) between consecutive instruction cycles.
Note 5: For Extended Temperature and Military parts CS must be brought low for a minimum of 500 ns (tcsl between consecutive instruction cycles.
Nole 6: This parameter is periodically sampled and not 100% tested.
Capacitance (Note 6)
TA = 25°C. f = 1MHz
Symbol
Test
AC Test Conditions
Output Load
Typ
Max
Units
GoUT
Output CapaCitance
5
pF
CIN
Input CapaCitance
5
pF
1 TIL Gate and CL = 100 pF
0.4Vto 2.4V
Input Pulse Levels
Timing Measurement Reference Level
Input
Output
2-22
1Vand2V
0.8Vand2V
Functional Description
The NMC93CS06 and NMC93CS46 have 10 instructions as
described below. Note that the MSB of any instruction is a
"1" and is viewed as a start bit in the interface sequence.
The next a-bits carry the op code and the 6-bit address for
selection of 1 of 16 or 64 16-bit registers.
that the register at the address specified in the instruction
has been written with the data pattern specified in the instruction and the part is ready for another instruction.
Write All (WRALL):
The Write All (WRALL) instruction is valid only when the
Protect Register has been cleared by executing a
PRCLEAR instruction. The WRALL instruction will simultaneously program all registers with the data pattern specified
in the instruction. Uke the WRITE instruction, the PE pin
MUST be held high while loading the WRALL instruction,
however, after loading the WRITE instruction the PE pin becomes a "don't care". As in the WRITE mode, the DO pin
indicates the READY/BUSY status of the chip if CS is
brought high after a minimum of 250 ns (tes).
Read (READ):
The Read (READ) instruction outputs serial data on the DO
pin. After a READ instruction is received, the instruction and
address are decoded, followed by data transfer from the
selected memory register into a 16-bit serial-out shift register. A dummy bit (logical 0) precedes the 16-bit data output
string. Output data changes are initiated by a low to high
transition of the SK clock. In the NONVOLATILE SHIFTREGISTER mode of operation, the memory automatically
cycles to the next register after each 16 data bits are
clocked out. The dummy-bit is suppressed in this mode and
a continuous string of data is obtained.
Write Disable (WDS):
To protect against accidental data disturb, the Write Disable
(WDS) instruction disables all programming modes and
should follow all programming operations. Execution of a
READ instruction is independent of both the WEN and WDS
instructions.
Write Enable (WEN):
When Vee is applied to the part, it "powers up" in the Write
Disable (WDS) state. Therefore, all programming modes
must be preceded by a Write Enable (WEN) instruction.
Once a Write Enable instruction is executed programming
remains enabled until a Write Disable (WDS) instruction is
executed or Vee is removed from the part.
Protect Register Read (PRREAD):
The Protect Register Read (PRREAD) instruction outputs
the address stored in the Protect Register on the DO pin.
The PRE pin MUST be held high while loading the instruction. Following the PRREAD instruction the 6-bit address
stored in the memory protect register is transferred to the
serial out shift register. As in the READ mode, a dummy bit
(logical 0) precedes the 6-bit address string.
Write (WRITE):
The Write (WRITE) instruction is followed by 16 bits of data
to be written into the specified address. After the last bit of
data (DO) is put on the data-in (DI) pin, CS must be brought
low before the next rising edge of the SK clock. This falling
edge of the CS initiates the self-timed programming cycle.
The PE pin MUST be held high while loading the WRITE
instruction, however, after loading the WRITE instruction the
PE pin becomes a "don't care". The DO pin indicates the
READY/BUSY status of the chip if CS is brought high after
a minimum of 250 ns (les). DO = logical 0 indicates that
programming is still in progress. DO = logical 1 indicates
Protect Register Enable (PREN):
The Protect Register Enable (PREN) instruction is used to
enable the PRCLEAR, PRWRITE, and PRDS modes. Before
the PREN mode can be entered, the part must be in the
Write Enable (WEN) mode. Both the PRE and PE pins
MUST be held high while loading the instruction.
Note that a PREN instruction must immediately precede a
PRCLEAR, PRWRITE, or PRDS instruction.
Instruction Set for the NMC93CS06 and NMC93CS46
S8
OpCode
Address
PRE
PE
Comments
READ
Instruction
1
10
A5-AO
Data
0
X
Reads data stored in memory, starting at specified address.
WEN
1
00
llXXXX
0
1
Write enable must precede all programming modes.
WRITE
1
01
A5-AO
DI5-DO
0
1
Writes register if address is unprotected.
WRALL
1
00
01XXXX
DI5-DO
0
1
Writes all registers. Valid only when Protect Register is
cleared.
WDS
1
00
OOXXXX
0
X
Disables all programming instructions.
PRREAD
1
10
XXXXXX
1
X
Reads address stored in Protect Register.
PREN
1
00
llXXXX
1
1
Must immediately precede PRCLEAR, PRWRITE, and
PROS instructions.
PRCLEAR
1
11
lllHl
1
1
Clears the Protect Register so that no registers are
protected from WRITE.
PRWRITE
1
01
A5-AO
1
1
Programs address into Protect Register. Thereafter,
memory addresses ~ the address in Protect Register are
protected from WRITE.
PROS
1
00
000000
1
1
One time only instruction after which the address in the
Protect Register cannot be altered.
2-23
•
Functional Description
(Continued)
Protect Register Clear (PRCLEAR):
The Protect Register Clear (PRCLEAR) instruction clears
the address stored in the Protect Register and, therefore,
enables all registers for the WRITE and WRALL instruction.
The PRE and PE pins must be held high while loading the
instruction, however, after loading the PRCLEAR instruction
the PRE and PE pins become "don't care". Note that a
PREN instruction must immediately precede a PRCLEAR
instruction.
ter must first be cleared by executing a PRCLEAR operation
and that the PRE and PE p,ins must be held high while
loading the instruction, however, after loading the PRWRITE
instruction the PRE and PE pins become 'don't care'. Note
that a PREN instruction must Immediately precede a
PRWRITE instruction.
Protect Register Disable (PROS):
The Protect Register Disable (PROS) instruction is a one
time only instruction which renders the Protect Register unalterable in the future. Therefore, the specified registers become PERMANENTLY protected against data changes. As
in the PRWRITE instruction the PRE and PE pins must be
held high while loading the instruction, and after loading the
PROS instruction the PRE and PE pins become "don't
Protect Register Write (PRWRITE):
The Protect Register Write (PRWRITE) instruction is used to
write into the Protect Register the address of the first register to be protected. After the PRWRITE instruction is executed, all memory registers whose addresses are greater
than or equal to the address specified in the Protect Register are protected from the WRITE operation. Note that before executing a PRWRITE instruction the Protect Regis-
care".
Note that a PREN instruction must Immediately precede a
PROS instruction.
Timing Diagrams
Synchronous Data Timing
-
-
I -
\PRES I-----~
tpES
t---- tpREH
r
p;;;
f---
~
1 p.s·
less
-
IsKH
tOIS
'j'
I
...-.. tcsH
tSKL -----
.11oIH
-
X\\\\\\ ,\\\\
I\\\\\\\\X
!::::::\.'PDl
!=::ltPDO
•
Ii
Isv
VOH
DO (PROGRAM) V
.
OL
STATUS VALID
~
1::1
::1
tor
tor
TLIO/9208-4
'This is the minimum SK period (See Note 2).
2-24
Timing Diagrams (Continued)
READ:
PRE=O,PE=X
csJ
21
21
DI~~~
____
21
~21~____________________~2~
\J8(~J0®()--
DO
• Address bits AS and A4 become "don't cares" for NMG93GS06
tThe memory automatically cycles to the next register.
PRE
CS
=
TLlD/9208-5
WEN:
0, DO = TRI-STATE
J
SK
DI
____0.l/
~_O
1
1
~______~~~______________
TL/D/9208-6
2-25
Timing Diagrams (Continued)
WDS:
PRE = D, PE = X, DO = TRI-STATE
SK
TL/D/9208-7
WRITE:
PRE = 0
t\\\\\\\\\\\
csJ
L
SK
READY
\.
TUD/920B-B
• Address b"s AS and A4 become "don't cares" for NMC93CS06
2-26
Timing Diagrams (Continued)
WRALL':
PRE = 0
f\\\\\\\
csJ
L
SK
o
OJ
o
o
Do-----------------+-L~\
BUSyJi
[tw~
READY \.
'Protect Register MUST be cleared.
PRE
TL/D/920B-9
PRREAD:
PE = X
J
csJ
SK
OJ~l
1
~______________________________...
DO--------------------------'"\.
TLlD/920B-l0
-Address bits AS and A4 beccme "don't cares" for NMC93CS06
2-27
CD
'1:1'
en
0
......
Timing Diagrams
(Continued)
CD
0
en
DO
0
('I)
."
0
:E
PRE
Z
PE
CS
=
PREN*:
TRI-STATE
J
J
J
~
SK
DI~O
0/1 1'0( ... )0\
TLlD19208-11
'A WEN cycle must precede a PREN cycle.
PRCLEAR*:
PRE
J
K\\\\\\\\\\
K\\\\\\\\'
CS
J
L
SK
1\"---___
DI~1
DO----------------IL_\
BUSY.Jl READY
~
'A PREN cycle must Immediately precede a PRCLEAR cycle.
2-28
TLID1920B-12
z
:s::
o<0
(0)
o(J)
Timing Diagrams (Continued)
PRWRITEt:
PRE
J
K\\\\\\\\\\\\\\\:
oQ)
......
o(J)
01>00
Q)
K\\\\\\\\\\\\\\\
CS
J
SK
DI
DO-----+---l8
READY
\'----TL/D/9208-13
'Address bits AS and A4 become "don't cares" for NMC93CS06
tProtect Register MUST be cleared before a PRWRITE cycle. A PREN cycle must Immediately precede a PRWRITE cycle.
PROS·:
PRE
J
K\\\\\\\\\\
K\\\\\\\\'
csJ
L
SK
____O
_____O
________O
____ O
____
DI~~O
O____
O________________________
DO----------------------+b--~ .~
TL/D/9208-14
'ONE TIME ONLY instruction. A PREN cycle must Immediately precede a PROS cycle.
2-29
~ r---------------------------------------------------------------------------~
~
~ ~National
[I ~
Semiconductor
NMC9307 2S6-Bit Serial Electrically Erasable
Programmable Memory
General Description
Features
The NMC9307 is a 256-bit non-volatile sequential access
memory fabricated using advanced floating gate N-channel
E2PROM technology. It is a peripheral memory designed for
data storage and/or timing and is accessed via the simple
MICROWIRETM serial interface. The device contains 256
bits of read/write memory divided into 16 registers of 16 bits
each. Each register can be serially read or written by a
COP400 series controller. Bulk programming instructions
(chip erase, chip write) can be enabled or disabled by the
user for enhanced data protection. Written information is
stored in a floating gate cell with at least 10 years data
retention and can be updated by an erase-write cycle. The
NMC9307 has been designed to meet applications requiring
up to 40,000 erase/write cycles per register. A power down
mode reduces power consumption by 70 percent.
• 40,000 erase/write cycles
• 10 year data retention
•
•
•
•
•
•
•
•
•
Low cost
Single supply operation (5V ± 10%)
TTL compatible
16x16 serial read/write memory
MICROWIRE compatible serial I/O
Compatible with COP400 processors
Low standby power
Non-volatile erase and write
Reliable floating gate technology
Block and Connection Diagrams
vpp
GENERATOR
Dual-In-Llne Package (N)
VCC
es
vee
SK
.e
III
aPE
DO
ON.
1+-_ _ _ _ _ _ _ _ _-,
TL/D/9204-2
Top View
See NS Package Number N08E
SO Package (M)
.0
.e
I
..
•
•
•
•
cs
OI-+++-ll--+--+
Ne
II
DO
Ne
3
T
"
"
"
.e
13
v"
11
.e
Ne
'PE
•
•
ON.
.e
TL/0/9204-3
Top View
See NS Package Number M14B
INSTRUCTION
cs,-+-------~
DECODE.
CONTROL
AND
CLOCK
Note: Contact factory for 508 availability.
GENERATORS
SK--------~
TL/D/9204-1
CS
SK
DI
DO
Vee
GND
2-30
Pin Names
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Power Supply
Ground
z
3:
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage Relative to GND
+6Vto -0.3V
Ambient Operating Temperature
NMC9307
NMC9307E
Ambient Storage Temperature
300·C
Lead Temperature (Soldering, 10 sec.)
ESDRating
2000V
(')
CD
W
CI
......
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
O·Cto +70·C
-40·Cto +85·C
- 65·C to + 125·C
Electrical Characteristics
Parameter
Conditions
Part No
Operating Voltage (Vecl
Operating Current (lee1)
Standby Current (lee2)
Min
Max
Units
4.5
5.5
V
9307
10
9307E
12
9307
3
9307E
4
Vee = 5.5V, CS= 1
Vee=5.5V, CS=O
mA
mA
Input Voltage Levels
-0.1
2.0
VIL
VIH
0.8
Vee + 1
V
V
Output Voltage Levels
IOL =2.1 mA
IOH=-400,..A
VOL
VOH
Input Leakage Current
VIN=5.5V
Input Leakage Current
PINS 1, 2, 3
PIN6
VIN=O to 5.5V
Output Leakage Current
VOUT=5.5V, CS=O
SK Frequency
SK HIGH TIME tSKH (Note 2)
SK LOW TIME tSKL (Note 2)
0
1
1
Input Set-Up and Hold Times
CS
tess
tesH
01
tOIS
tOIH
0.2
0
0.4
0.4
Output Delay
DO
V
V
10
,..A
±10
±50
,..A
,..A
10
,..A
250
kHz
,..S
,..S
,..s
,..s
,..S
,..s
CL=100pF
tp01
tpoo
VOL =0.8V, VOH= 2.0V
VIL =0.45V, VIH=2.40V
Erase/Write Pulse Width (tE/W) (Note 1)
10
CS Low Time (tes) (Note 3)
Endurance
0.4
2.4
2
2
,..s
,..s
30
ms
1
Number of Data
Changes per Bit
,..s
40, 000 Typical
Note 1: tE/W measured to rising edge of SK or es, whichever occurs last.
Note 2: The SK frequency spec. specifies a minimum SK clock period of 4 pos. therefore in an SK clock cycle. tSKH
e.g. if isKL = 1p.s then the minimum isKH = 3 pos in order to meet the SK frequency specification.
Note 3: GS must be brought low for a minimum of 1 po. (tcsl between consecutive instruction cycles.
2-31
+ isKL must be greater than or equal to 4 pos.
•
~
C
r---------------------------------------------------------------------------------~
~
Instruction Set
::e
z
Instruction
SB
OpCode
Address
READ
0,1
10xx
A3A2A1AO
WRITE
0,1
01xx
A3A2A1AO
ERASE
0,1
11xx
A3A2A1AO
EWEN
0,1
0011
xxxx
Erase/write enable
EWDS
0,1
0000
xxxx
Erase/write disable
ERAL
0, 1
0010
xxxx
WRAL
0, 1
0001
xxxx
o
Data
Comments
Read register A3A2A1AO
015-00
Write register A3A2A 1AO
Erase register A3A2A 1AO
Erase all registers
015-00
Write all registers
The NMC9307 has 7 instructions as shown. Note that MSB of any given instruction Is a '"I'" and is viewed as a start bH
in the interface sequence. The next 8 bits carry the op code and the 4·bit address for 1 of 16, 16-bH registers.
X is a don't care state.
Functional Description
The NMC9307 is a small peripheral memory intended for
use with COPSTM controllers and other non-volatile memory
applications. The NMC9307 is organized as sixteen registers and each register is sixteen bits wide. The input and
output pins are controlled by separate serial formats. Seven
9-bit instructions can be executed. The instruction format
has a logical '1' as a start bit, four bits as an op code, and
four bits of address. SK clock cycle is necessary after CS
equals logical "1" before the instruction can be loaded. The
on-chip programming-voltage generator allows the user to
use a single power supply (Vee>. Only during the read mode
is the serial output (DO) pin valid. During all other modes the
DO pin is in TRI-STATE®, eliminating bus contention.
instruction is then set entirely to 1s. When the erase/write
programming time (tE/W) constraint has been satisfied, CS
is brought up for at least one SK period. A new instruction
may then be input, or a low-power standby state may be
achieved by dropping CS low.
WRITE (Note 4)
The WRITE instruction is followed by 16 bits of data which
are written into the specified address. This register must
have been previously erased. Like any programming mode,
erase/write time is determined by the low state of CS following the instruction. The on-chip high voltage section only
generates high voltage during these programming modes,
which prevents spurious programming during other modes.
When CS rises to VIH, the programming cycle ends. All programming modes should be ended with CS high for one SK
period, or followed by another instruction.
READ
The read instruction is the only instruction which outputs
serial data on the DO pin. After a READ instruction is received, the instruction and address are decoded, followed
by data transfer from the memory register into a 16-bit serial-out shift register. A dummy bit (logical '0') precedes the
16-bit data output string. Output data changes are initiated
by a low to high transition of the SK clock.
CHIP ERASE (Note 4)
Entire chip erasing is provided for ease of programming.
Erasing the chip means that all registers in the memory array have each bit set to a 1. Each register is then ready for a
WRITE instruction. The chip erase (ERAL) instruction is ignored if the BPE pin is at VIL, i.e., data is not changed.
ERASE/WRITE ENABLE AND DISABLE
Programming must be preceded once by a programming
enable (EWEN) instruction. Programming remains enabled
until a programming disable (EWDS) instruction is executed.
The programming disable instruction is provided to protect
against accidental data disturb. Execution of a READ instruction is independent of both EWEN and EWDS instructions.
CHIP WRITE (Note 4)
All registers must be erased before a chip write operation.
The chip write cycle is identical to the write cycle, except for
the different op code. All registers are simultaneously written with the data pattern specified in the instruction.
The chip write (WRAL) instruction is ignored if the BPE pin is
at VIL, i.e., the array data is not changed.
ERASE (Note 4)
Like most E2PROMS, the register must first be erased (all
bits set to 1s) before the register can be written (certain bits
set to Os). After an ERASE instruction is input, CS is
dropped low. This falling edge of CS determines the start of
programming. The register at the address specified in the
Note 4: During a programming mode (write, erase, chip erase, chip write),
SK clock Is only needed while the actual instruction, i.e., start bit, op code,
address and data, is being input. It can remain deactivated during the Erase/
Write pulse width (tE/W)'
2-32
Timing Diagrams
Synchronous Data Timing
~---4
.s·
Ft... '"
-------l
. . . ---.....,1:-____
SK _ _ _ _......
01
cs
DO
TL/D/9204-4
'This is the minimum SK period
•
2-33
NMC9307
-f
Instruction Timing
~:
UL.rLrlI1
SK
:::::I
CC
-,~---
cs /
READ
01 ~
1
\
0~JC!r\
110'--------------
..,
CC
I»
3
(I)
'§
I~
DO
C
ii)'
:J
g.
TL/D/9204-S
C
CD
So
UU-VlJlJL
SK
I\)
'"
-I'-
WRITE
csJ
---C':J
DI~l~~X!!\
II
/1C::X::X:
TLlD/9204-6
1..JLf1
SK
ERASE
cs
r-
-,--C":Jr---------
DI~l
TLlD/9204-7
·tE/W measured to rising edge of SK or CS, whichever occurs last.
.of
~:
Instruction Timing (Continued)
::::J
CCI
c
SK
iir
EWEN
(ERASE/:
ENABLE/DISABlE)
l
I
CS
..,.
SI)
3
tn
oo
CCI
\_-------
,--
J
DI--fT\O
~
I
ENABLE=ll
DlSABLE=OO
3s·
TUD/9204-8
c:
<1l
B
~[hfUU1--1
SK
""c.,
01
WRAl
(WRITE All)
aJ
DI---./7\
0
0
I 1~:::x-F\"
I
1
\
x:
TLlD/9204-9
SK
ERAl
(ERASE All)
J cs
1
./r----------------==-.:C'J,.'-------------
DI~O
oF7\o~
TLlD/9204-10
*t E/W measured to rising edge of SK or CS, whichever occurs last.
LO£60WN
II
~National
~
Semiconductor
NMC9313B 2S6-Bit Serial Electrically Erasable
Programmable Memory
General Description
Features
The NMC9313B is a 256-bit non-volatile sequential access
memory fabricated using advanced floating gate N-channel
E2PROM technology. It is a peripheral memory designed for
data storage and/or timing and is accessed via the simple
MICROWIRETM serial interface. The device contains 256
bits of read/write memory divided into 16 registers of 16 bits
each. Each register can be serially read or written by a
COP400 series controller. Written information is stored in a
floating gate cell with at least 10 years data retention and
can be updated by an erase-write cycle. The NMC9313B
has been designed to meet applications requiring up to
1 x 104 erase/write cycles per register. A power down
mode reduces power consumption by 67 percent.
•
•
•
•
•
•
•
•
•
Low cost
Single supply operation (5V ± 10%)
TTL compatible
16 x 16 serial read/write memory
MICROWIRE compatible serial I/O
Compatible with COP400 processors
Low standby power
Non-volatile erase and write
Reliable floating gate technology
Block and Connection Diagrams
Dual-In-Llne Package (N)
8
CS
----+
VPP
GENERATOR
VCC
+-VCC
SK
NC
01
NC
DO
GND
VPP
,....
r+
I
DECODER
1/16
~
E'PROM
256 BITS
116x16)
TL/D/9145-2
fa
l6
ADDRESS
LATCHES
R/WAMPS
Top View
Order Number NMC9313B
See NS Package Number N08E
t1
01
Pin Names
CS
Chip Select
~6
4
rl
.""
DO
[1.1.
INSTRUCTION
REGISTER ClK
19 BITS)
J:
'--
CS
I-INSTRUCTION
DECODE.
CONTROL
AND
CLOCK
GENERATORS
DO
Serial Data Clock
Serial Data Input
Serial Data Output
Vee
GND
Ground
SK
I.
DATA
REGISTER
117 BITS) ClKI.,l....-
f----
SK
TL/D/9145-1
2-36
01
Power Supply
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage Relative to GND
+6Vto -0.3V
Ambient Operating Temperature
NMC9313B/COP494
Ambient Storage Temperature
with Data Retention
Lead Temperature (Soldering, 10 seconds)
300·C
ESORating
2000V
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other condHions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
O·Cto +70·C
-65·C to + 125·C
Electrical Characteristics o·c ,,;TA,,; 70·C, VCc=5V± 10% unless otherwise specified
Parameter
Conditions
Operating Voltage (Vccl
Min
Typ
Max
4.5
Units
5.5
V
Operating Current (lCC1)
Vcc=5.5V, CS= 1
15
mA
Standby Current (ICC2)
VCC=5.5V, CS=O
5
mA
0.8
VCC + 0.5
V
V
0.4
V
V
Input Voltage Levels
VIL
VIH
-0.1
2.0
Output Voltage Levels
VOL
VOH
IOL=2.1 mA
IOH=-400 ",A
Input Leakage Current
VIN=5.5V
10
",A
Output Leakage Current
VOUT=5.5V, CS=O
10
",A
200
kHz
",s
",s
2.4
SK Frequency
SK HIGH TIME tSKH (Note 2)
SK LOW TIME tSKL (Note 2)
0
3
2
Input Set-Up and Hold Times
CS
tcss
tCSH
01
tOIS
tOIH
0.2
0
0.4
0.4
Output Delay
DO
",s
",s
",s
}JoS
CL=100pF
VOL =0.8V, VOH=2.0V
VIL =0.45V, VIH=2.40V
tpOl
tpoo
Erase/Write Pulse Width (tE/W) (Note 1)
10
2
2
"'S
"'S
30
ms
CS Low Time (tcs) (Note 3)
1
"'S
Note 1: tE/W measured to rising edge of SK or CS, whichever occurs last.
Note 2: The SK frequency spec. specifies a minimum SK clock period of 5 p.s, therefore in an SK clock cycle, tSKH + tSKL must be greater than or equal to 5 p.••
e.g. if tsKL = 2 p.. then the minimum tsKH = 3 p.s In order to meet the SK frequency specificaUon.
Note 3: CS must be brought low for a minimum of 1 J.los (tcS) between consecutive instruction cycles.
Instruction Set
Data
Comments
Instruction
SB
OpCode
Address
READ
01
10xx
A3A2A1AO
WRITE
01
01xx
A3A2A1AO
ERASE
01
11xx
A3A2A1AO
Erase register A3A2A 1AO
EWEN
01
0011
xxxx
Erase/write enable
EWDS
01
0000
xxxx
Eraselwrite disable
ERAL
01
0010
xxxx
WRAL
01
0001
xxxx
Read register A3A2A 1AO
015-00
Write register A3A2A 1AO
Erase all registers
D15-00
Write all registers
NMC9313B has 7 instrucUons as shown. Note that MSB of any given instruction is a "I" and is viewed as a start bit in
the interface sequence. The next 8 bits carry the op code and the 4·bit address for 1 of 16, l6·bit registers.
X is a don't care state.
2-37
•
Functional Description
The NMC93138 is a small peripheral memory intended for
use with COPSTM controllers and other non-volatile memory
applications. Its organization is sixteen registers and each
register is sixteen bits wide. The input and output pins are
controlled by separate serial formats. Seven 1O-bit instructions can be executed. The instruction format has a logical
0, 1 as start bits, four bits as an op code, and four bits of
address. The on-chip programming-voltage generator allows the user to use a single power supply (Ved. Only during the read mode is the serial output (DO) pin valid. During
all other modes the DO pin is in TRI-STATEIII>, eliminating
bus contention.
set to Os). After an ERASE instruction is input, CS is
dropped low. This falling edge of CS determines the start of
programming. The register at the address specified in the
instruction is then set entirely to 1s. When the erase/write
programming time (tE/W) constraint has been satisfied, CS
is brought up for at least one SK period. A new instruction
may then be input, or a low-power standby state may be
achieved by dropping CS low.
WRITE (Note 4)
The WRITE instruction is followed by 16 bits of data which
are written into the specified address. This register must
have been previously erased. Like any programming mode,
erase/write time is determined by the low state of CS following the instruction. The on-Chip high voltage section only
generates high voltage during these programming modes,
which prevents spurious programming during other modes.
When CS rises to VIH, the programming cycle ends. All programming modes should be ended with CS high for one SK
period, or followed by another instruction.
READ
The read instruction is the only instruction which outputs
serial data on the DO pin. After a READ instruction is received, the instruction and address are decoded, followed
by data transfer from the memory register into a 16-bit serial-out shift register. A dummy bit (logical '0') precedes the
16-bit data output string. Output data changes are initiated
by a low to high transition of the SK clock.
CHIP ERASE (Note 4)
ERASE/WRITE ENABLE AND DISABLE
Entire chip erasing is provided for ease of programming.
EraSing the chip means that all registers in the memory array have each bit set to a 1. Each register is then ready for a
WRITE instruction.
Programming must be preceded once by a programming
enable (EWEN) instruction. Programming remains enabled
until a programming disable (EWDS) instruction is executed.
The programming disable instruction is provided to protect
against accidental data disturb. Execution of a READ instruction is independent of both EWEN and EWDS instructions.
CHIP WRITE (Note 4)
All registers must be erased before a chip write operation.
The chip write cycle is identical to the write cycle, except for
the different op code. All registers are simultaneously written with the data pattern speCified in the instruction.
ERASE (Note 4)
Like most E2PROMS, the register must first be erased (all
bits set to 1s) before the register can be written (certain bits
Note 4: During a programming mode (write, erase, chip erase, chip write),
SK clock is only needed while the actual instruction, I.e., start bit, op code,
address and data, is being Input. It csn remain deactivated during the Erasel
Write pulse width (te/W)'
Timing Diagrams
.1
F,S. =t...""!"'!""_;F-ts-IL=I---,~--5 "s'
,.
SK _ _ _ _
01
cs
DO
TLlD/9145-3
'This Is the minimum SK period
Synchronous Data Timing
2-38
lJ1.ILrLI1
SK
CS
=!
3
j
J
5'
CQ
II
c
iii'
\ , ,_ _ _ _ _ _ _ _
CQ
REAO
01
----1
1
1
\
~::x-!"\
0
DJ
3tn
1101_ _ _ _ _ _ _ _ _ _ _ _ __
i
I~
DO
TUD/914S-4
~.
~
t.rLrlJ UL.f1
---c
SK
'l'
Co)
co
WRITE~ cs
01
/W '
--------1
.I
~
1
~JG:)GOCxoo"\
I
1
c:x::x:
TUD/914S-S
l..rUL
SK
ERASE
CS
---t::Jr.-'- - - - - - -
/
0'---1'
TL/D/914S-6
9tEIW measured to rising edge of SK or
es, whichever occurs last.
Instruction Timing
S&~&6~WN
II
NMC9313B
-t
3"
:s"
ec
SK
EWEN
EWDS
cs /
(ERASE/WRITE
ENABLE/DISABLE)
--
-
--
,'-_ _ _ _ _ _ _ _ _ __
C
Dr
ec
""I
DI~O
01
D)
~
3
(I)
ENABLE=ll
DISABLE=OO
TLlD/9145-7
'§
a5·
c:
CD
S
~~
--1
SK
I\)
.J,..
o
aJ
WRAL
(WRITE ALL)
DI~O
D/l~JG'\"
11\
x:
TLiD/9145-8
SK
(ERASE~L~~ ~
.......
i.-I
~
i.-I
~
~
~
~
i.-I
~
~
C
CS . / , . - - - - - - - - - - - - - - - - - - - - - - - - - - -
DI~O
",,.a
.........
---1,.-----------------
/WL--.../
Df7\D~
TLiD/9145-9
*t E/W measured to rising edge of SK or es, whichever occurs last.
Instruction Timing (Continued)
~National
~
Semiconductor
NMC9346 1024-Bit Serial Electrically Erasable
Programmable Memory
General Description
Features
The NMC9346 is a 1024-bit non-volatile, sequential
E2PROM, fabricated using advanced N-channel E2PROM
technology. It is an external memory with the 1024 bits of
read/write memory divided into 64 registers of 16 bits each.
Each register can be serially read or written by a COP400
controller, or a standard microprocessor. Written information is stored in a floating gate cell until updated by an erase
and write cycle. The NMC9346 has been designed for applications requiring up to 4 x 104 erase/write cycles per register. A power-down mode is provided by CS to reduce power
consumption by 75 percent.
• DeSigned for 40,000 erase/write cycles
• 10 year data retention
• Low cost
II Single supply read/write/erase operations (5V±10%)
• TTL compatible
• 64 x 16 serial read/write memory
• MICROWIRETM compatible serial I/O
• Simple interfacing
• Low standby power
• Non-volatile erase and write
• Reliable floating gate technology
• Self-timed programming cycle
• Device status signal during programming
Block Diagram
Pin Names
DO
DI
cs-4----------+I
INSTRUCTION
DfCODE.
CONTRDL.
AND ClOCK
GENERATDR
.....
SK----------t>i
---'
TLiD/9205-1
2-41
CS
SK
DI
DO
Vee
GND
NC
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Power Supply
Ground
No Connection
Connection Diagrams
S-Pln
SO Package (MS)
Dual-In-Une Package (N)
CS-l
u
cs-
8!--YCC
SK- 2
7!--NC
01- 3
6 -NC
00- 4
5 -GND
1
'--'
8
~VCC
SK- 2
7 ~NC
DI-3
6~NC
DO- 4,
5
~GND
1-,;".---'
'
TU0/9205-7
Top View
See NS Package Number MOSA
Device Marking: 9346, 9346E
TL/0/9205-2
Top View
See NS Package Number NOSE
Ordering Information
Commercial Temp. Range
(O'C to + 70'C)
Extended Temp. Range
(- 40"C to + S5'C)
Order Number
Order Number
NMC9346N
NMC9346MB
NMC9346EN
NMC9346EM8
Absolute Maximum Ratings
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage Relative to GND
+6V to -O.3V
Ambient Storage Temperature
-6S'Cto + 12S'C
Lead Temperature
(Soldering. 10 seconds)
300'C
ESDrating.
2000V
Ambient Storage Temperatures
NMC9346
NMC9346E
Positive Supply Voltage
O'Cto +70'C
-40'Cto +BS'C
4.SVtoS.SV
DC and AC Electrical Characteristics Vee = sv ± 10% unless otherwise specified
Symbol
Parameter
Part Number
Vee
Operating Voltage
NMC9346. NMC9346E
leel
Operating Current
Erase/Write Operating Current
NMC9346
Operating Current
Erase/Write Operating Current
NMC9346E
2-42
Conditions
Min
Max
4.S
S.S
Units
V
Vee=5.SV. CS= 1. SK= 1
Vee=5.SV
12
12
mA
'IllA
Vcc=S.SV. CS=I. SK=1
Vcc=5.SV
14
14
mA
mA
DC and AC Electrical Characteristics Vee = sv ±10% unless otherwise specified (Continued)
Symbol
lee2
Parameter
Part Number
Conditions
MIn
Max
Units
Standby Current
NMC9346
Vee=S.SV, CS=O
3
mA
Standby Current
NMC9346E
Vee=S.SV, CS=O
4
mA
Input Voltage Levels
NMC9346, NMC9346E
0.8
Vee+ 1
V
V
0.4
V
V
/Jo A
-0.1
2.0
VIL
VIH
Output Voltage Levels
NMC9346, NMC9346E
IOL =2.1 mA
IOH = - 400 /JoA
VOL
VOH
2.4
III
Input Leakage Current
NMC9346, NMC9346E
VIN=S.SV
10
ILO
Output Leakage Current
NMC9346, NMC9346E
VOUT=S.SV, CS=O
10
/Jo A
MMC9346
2S0
tSKH
tSKL
SK Frequency
SK High Time (Note 2)
SK Low Time (Note 2)
kHz
/JoS
/Jos
SK Frequency
SK High Time (Note 2)
SK Low Time (Note 2)
MMC9346E
Inputs
CS
NMC9346, NMC9346E
tess
tcsH
tOIS
tOIH
tpd1
IpdO
0
1
1
0
1
1
2S0
0.2
0
0.4
0.4
01
Output
DO
NMC9346, NMC9346E
CL =100pF
VOL=0.8V, VOH=2.0V
kHz
/Jos
/Jos
/Jos
/Jos
/Jos
/Jos
2
/Jos
Self-Timed Program Cycle
NMC9346
10
ms
Self-Timed Program Cycle
NMC9346E
10
ms
les
Min CS Low Time (Note 3)
NMC9346, NMC9346E
tsv
Rising Edge of CS to Status Valid
NMC9346, NMC9346E
tE/W
1
CL =100 pF
/Jos
1
/Jos
Falling Edge of CS to DO TRI-STATE®
NMC9346, NMC9346E
0.4
toH, tlH
/JoS
Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: The SK frequency spec. specifies a minimum SK clock period of 4 ,",S, therefore in an SK clock cycle tSKH + tSKL must be greater than or equal to 4 ,",s.
e.g., if lsKL = 1 ,",S then the minimum lsKH = 3 ,",S in order to meet the SK frequency specification.
Note 3: CS must be brought low for a minimum of 1 ,",S (tcs) between consecutive instruction cycles.
'Thruout this table "M" refers to temperature range (-55"C to + 125"C), nol package.
2-43
U)
"'it'
C")
Q)
(.)
:::!iii
z
r---------------------------------------------------------------------------------,
Functional Description
The NMC9346 is a small peripheral memory intended for
use with COPSTM controllers and other nonvolatile memory
applications. The NMC9346 is organized as sixty·four registers and each register is sixteen bits wide. The input and
output pins are controlled by separate serial formats, Seven
9-bit instructions can be executed. The instruction format
has a logical '1' as a start bit, two bits as an op code, and six
bits of address. The programming cycle is self-timed, with
the data out (~O) pin indicating the ready/busy status of the
chip. The on-chip programming voltage generator allows the
user to use a single power supply (Vee>. It only generates
high voltage during the programming modes (write, erase,
chip erase, chip write) to prevent spurious programming duro
ing other modes. The DO pin is valid as data out during the
read mode, and if initiated, as a ready/busy status indicator
during a programming cycle. During all other modes the DO
pin is in TRI-STATE, eliminating bus contention.
tain bits set to logical '0'). After an erase instruction is input,
CS is dropped low. This falling edge of CS determines the
start of the self-timed programming cycle. If CS is brought
high subsequently (after observing the tes specification),
the DO pin will indicate the ready/busy status of the Chip.
The DO pin will go low if the chip is still programming. The
DO pin will go high when all bits of the register at the address specified in the instruction have been set to a logical
'1'. The part is now ready for the next instruction sequence.
WRITE (Note 4)
The write instruction is followed by 16 bits of data to be
written into the specified address. After the last bit of data
(DO) is put on the data in (01) pin CS must be brought low
before the next riSing edge of the SK clock. This falling edge
of CS initiates the self-timed programming cycle. Like all
programming modes, DO indicates the ready/busy status of
the chip if CS is brought high after a minimum of 1 JLS (lcs).
OO=logical '0' indicates that programming is still in progress. DO = logical '1' indicates that the register at the address specified in the instruction has been written with the
data pattern specified in the instruction and the part is ready
for another instruction. The register to be written into must
have been previously erased.
READ
The read instruction is the only instruction which outputs
serial data on the DO pin. After a read instruction is received, the instruction and address are decoded, followed
by data transfer from the memory register into a 16-bit serial-out shift register. A dummy bit (logical '0') precedes the
16·bit data output string. Output data changes are initiated
by a low to high transition of the SK clock.
CHIP ERASE (Note 4)
Entire chip erasing is provided for ease of programming.
EraSing the chip means that all registers in the memory array have each bit set to a logical '1'. Each register is then
ready for a write instruction. The chip erase cycle is identical
to the erase cycle except for the different op code.
ERASE/WRITE ENABLE AND DISABLE
When Vee is applied to the part it powers up in the programming disable (EWOS) state, programming must be preceded
by a programming enable (EWEN) instruction. Programming
remains enabled until a programming disable (EWOS) instruction is executed or Vee is removed from the part. The
programming enable instruction (EWEN) is needed to keep
the part in the enable state if the power supply (Vee> noise
falls below operating range. The programming disable instruction is provided to protect against accidental data disturb. Execution of a read instruction is independent of both
EWEN and EWDS instructions.
CHIP WRITE (Note 4)
All registers must be erased before a chip write operation.
The chip write cycle is identical to the write cycle except for
the different op code. All registers are simultaneously written with the data pattern specified in the instruction.
Note 4: During a programming mode (wlite, erase, chip erase, chip write),
SK clock is only.needed while the actual Instruction. I.e., start bit, op
code, address and data, is being Input. It can remain deactivated
during the self·timed programming cycle and status check.
ERASE (Note 4)
Like most E2PROMs, the register must first be erased (all
bits set to logical '1 ') before the register can be Written (cer-
Instruction Set for NMC9346
Instruction
Data
Comments
SB
OpCode
Address
READ
1
10
A5A4A3A2A1AO
WRITE
1
01
A5A4A3A2A1AO
ERASE
1
11
A5A4A3A2A1AO
EWEN
1
00
11xxxx
Erase/Write Enable
EWDS
1
00
OOxxxx
Erase/Write Disable
ERAL
1
00
10xxxx
WRAL
1
00
01xxxx
Read Register A5A4A3A2A1AO
015-00
Write Register A5A4A3A2A1AO
Erase Register A5A4A3A2A1AO
Erase All Registers
015-00
Write All Registers
NMC9346 has 7 instructions as shown. Note that the MSa of any given Instruction is a "1" and Is viewed as a start bit In the
interface sequence. The next B bits carry the op code and the 6·bit address for 1 of 64, lS·bit registers.
2-44
Timing Diagrams
Synchronous Data Timing
4 j.LS*
I'
V1H
~tSK" I·
SK
V1L
t OIS
"I
tDiH
0.4 j.LS
I
tSKLd
tOIH
0.4 j.LS
0.4 j.LS
V1H
DI
V1L
t OIS
0.4 j.LS
CS
V1L
I
tpoo
2 j.LS
VOH
DO
VOL
~
V
'This is the minimum SK period (51's for NMC9306M)
2-45
tp01
2 j.LS
TL/0/9205-4
NMC9346
-I
3'
Instruction Timing
::::s
u-uLn.IlIl..fUL..flSLJl.r
SK
CO
C
iii'
CO
~
CS /
A)
READ
~~_____________ • _______________
DI
.-+_________________
10M, !,.
DO
~
TRI-STATE'
'11J_T_RI..
-S_l..
AT.E_ _ _ _ _ __
3U)
-0
o
3.
:;'
t:
CD
.e,
1...f1..fLILrLfl.Jl
~
C1c: -=r
SK
S
CS /
I\J
.j,.
O'l
WRITE
.
~~
OO~
I,
=[: /
DI~O
CHECK STATUS
ru-
~
STAND8l
~
~
IE,.
',-_S_TAND_BY_ _ _ _ _ __
I
~
ENABLE=11
DISABLE=OO
TLID/9205-5
::!
3
5'
cc
Instruction Timing
1.IUUl ___
SK
CS
ERASE
I
n.n
CHECK STATUS
i'
cc
iiJ
01
3
X!'\
1~
UJ
I1H
Q
TRI-5TATE
TRI-STATE
DO
c
STANDBY
::J
g.
I:
CD
So
ru
SK
fWRNA
l1l.
CS /
~
ERAL
DI~O
DO
0f7\0~
TRI-5TATE
I.
"
I.
'u:...;f
U-UUWMMUl
SK
cs /
WRAL
01
-f'7'\
0
0
m~ATE
DO
/1
~.""""
n
'I
I.
I
•
I.
'~SY ~
tE/W
TU0/9205-6
9te6~WN
II
...
m ,-------------------------------------------------------------------,
i
~National
~ ~ Semiconductor
z
NMC9314B 1024-Bit Serial Electrically Erasable
Programmable Memory
General Description
Features
The NMC9314B is a 1024-bit non-volatile, sequential
E2PROM, fabricated using advanced N-channel E2PROM
technology. It is an external memory with the 1024 bits of
read/write memory divided into 64 registers of 16 bits each.
Each register can be serially read or written by a COP400
controller, or a standard microprocessor. Written information is stored in a floating gate cell until updated by an erase
and write cycle. The NMC9314B has been designed for applications requiring up to 104 erase/write cycles per register. A power-down mode is provided by CS to reduce power
consumption by 75 percent.
• 10,000 erase/write cycles
• 10 year data retention
•
•
•
•
•
•
•
•
•
•
•
Low cost
Single supply read/write/erase operations (5V±10%)
TTL compatible
64 x 16 serial read/write memory
MICROWIRETM compatible serial I/O
Simple interfacing
Low standby power
Non-volatile erase and write
Reliable floating gate technology
Self-timed programming cycle
Device status signal during programming
Dual-in-Line Package (N)
Block and Connection Diagrams
cs
vec
SK
NC
01
NC
DO
aND
TUD/9144-2
Top View
Order Number NMC9314N
See NS Package N08E
Pin Names
Chip Select
SK
Serial Data Clock
01
Serial Data Input
DO
Serial Data Output
Vee
Power Supply
GND
Ground
NC
Not Connected
CS
Mv-+H.... >-oo
m-+~~-----T----1
INSTRUCTION
DECODE,
CONTROL,
AND CLOCK
C S - t - - - - - - - - -. .
GENERATOR
sK------.,;---1L__j-------I
TUD/9144-1
2-48
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage Relative to GNO
Ambient Storage Temp.
-65'Cto + 125'C
Lead Temperature (Soldering, 10 seconds)
ESO Rating
300'C
>2000V
+6Vto -0.3V
Ambient Operating Temperature
O'Cto +70'C
DC and AC Electrical Characteristics O'CS:TAQO'C, Vee=5V±10% unless specified
Symbol
Parameter
Conditions
Min
Max
Units
4.5
5.5
V
Vee
Operating Voltage
lee1
Operating Current
Erase/Write Operating Current
Vee=5.5V, CS=1, SK=1
Vee=5.5V
17
17
mA
mA
lee2
Standby Current
Vee=5.5V, CS=O
5
mA
0.8
Vee + 0.5
V
V
0.4
V
V
J.LA
Input Voltage Levels
-0.1
2.0
VIL
VIH
Output Voltage Levels
IOL =2.1 mA
IOH= -400 J.LA
VOL
VOH
2.4
III
Input Leakage Current
VIN=5.5V
10
ILO
Output Leakage Current
VOUT=5.5V, CS=O
10
J.LA
200
IsKH
IsKL
SK Frequency
SK High Time (Note 2)
SK Low Time (Note 2)
kHz
J.Ls
J.Ls
less
leSH
tDiS
tOIH
Ipd 1
tpdO
0
3
2
Inputs
CS
0.2
0
0.4
0.4
01
Output
00
CL=100pF
VOL =0.8V, VOH= 2.0V
V,L = 0.45V, V,H = 2.40V
tE/W
Self-Timed Program Cycle
les
Min CS Low Time (Note 3)
tsv
Rising Edge of CS to Status Valid
tOH, t'H
Falling Edge of CS to 00 TRI-STATE®
J.Ls
J.Ls
J.Ls
J.Ls
2
2
J.Ls
J.Ls
15
ms
1
CL=100pF
J.Ls
1
J.Ls
0.4
J.Ls
Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated In the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: The SK frequency spec. specnies a minimum SK clock period of 5 p.s. therefore in an SK clock cycle tsKH
e.g., If tsKL ~ 2 p.s then the minimum tsKH ~ 3 p.s in order to meet the SK frequency specification.
Note 3: CS must be brought low for a minimum of 1 p.s (les) between consecutive instruction cycles.
+ tSKL must be greater than or equal to 5 ",".
Instruction Set for NMC9314B
SB
OpCode
Address
1
10
A5A4A3A2A1AO
WRITE
1
01
A5A4A3A2A1AO
ERASE
1
11
A5A4A3A2A1AO
EWEN
1
00
11xxxx
Erase/write enable
EWOS
1
00
OOxxxx
Erase/write disable
ERAL
1
00
10xxxx
WRAL
1
00
01xxxx
Instruction
REAO
Data
Comments
Read register A5A4A3A2A1AO
015-00
Write register A5A4A3A2A 1AO
Erase register A5A4A3A2A1AO
Erase all registers
015-00
Write all registers
NMC93148 has 7 instructions as shown. Note that the MSB of any given instruction is a "1" and is viewed as a start bit in
the interface sequence. The next B bits carry the op code and the 6-bit address for 1 of 64, 16·bit registers.
2-49
Functional Description
The NMC9314B is a small peripheral memory intended for
use with COPSTM controllers and other nonvolatile memory
applications. Its organization is sixty-four registers and each
register is sixteen bits wide. The input and output pins are
controlled by separate serial formats. Seven 9-bit instructions can be executed. The instruction format has a logical
'1' as a start bit, two bits as an op code, and six bits of
address. The programming cycle is self-timed, with the data
out (DO) pin indicating the ready/busy status of the chip.
The on-chip programming voltage generator allows the user
to use a single power supply {Vee}. It only generates high
voltage during the programming modes (write, erase, chip
erase, chip write). The DO pin is valid as data out during the
read mode, and if initiated, as a ready/busy status indicator
during a programming cycle. During all other modes the DO
pin is in TRI-STATE, eliminating bus contention.
the start of the self-timed programming cycle. If CS is
brought high subsequently (after observing the les specification), the DO pin will indicate the ready/busy status of the
chip. The DO pin will go low if the chip is still programming.
The DO pin will go high when all bits of the register at the
address specified in the instruction have been set to a logical '1'. The part is now ready for the next instruction sequence.
WRITE (Note 4)
The write instruction is followed by 16 bits of data to be
written into the specified address. After the last bit of data
(DO) is put on the data in (01) pin CSmust be brought low
before the next rising edge of the SK clock. This falling edge
of CS initiates the self-timed programming cycle. Like all
programming modes, DO indicates the ready/busy status of
the chip if CS is brought high after a minimum of 1 p.S (tes).
DO = logical '0' indicates that programming is still in progress. DO = logical '1' indicates that the register at the address specified in the instruction has been written with the
data pattern specified in the instruction and the part is ready
for another instruction. The register to be written into must
have been previously erased.
READ
The read instruction is the only instruction which outputs
serial data on the DO pin. After a read instruction is received, the instruction and address are decoded, followed
by data transfer from the memory register into a 16-bit serial-out shift register. A dummy bit (logical '0') precedes the
16-bit data output string. Output data changes are initiated
by a low to high transition of the SK clock.
CHIP ERASE (Note 4)
Entire chip erasing is provided for ease of programming.
Erasing the chip means that all registers in the memory array have each bit set to a logical '1'. Each register is then
ready for a write instruction. The chip erase cycle is identical
to the erase cycle except for the different op code.
ERASE/WRITE ENABLE AND DISABLE
When Vee is applied to the part it powers up in the programming disable (EWOS) state, programming must be preceded
by a programming enable (EWEN) instruction. Programming
remains enabled until a programming disable (EWOS) instruction is executed or Vee is removed from the part. The
programming disable instruction is provided to protect
against accidental data disturb. Execution of a read instruction is independent of both EWEN and EWOS instructions.
CHIP WRITE (Note 4)
All registers must be erased before a chip write operation.
The chip write cycle is identical to the write cycle except for
the different op code. All registers are simultaneously written with the data pattern specified in the instruction.
ERASE (Note 4)
Note 4: During a programming mode (wrHe, erase, chip erase, chip write),
SK clock is only needed while the actual instruction, i.e., start bit, op code,
address and data, is being input It can remain deactivated during the selftimed programming cycle and status check.
Like most E2PROMs, the register must first be erased (all
bits set to logical '1') before the register can be written (certain bits set to logical '0'). After an erase instruction is input,
CS is dropped low. This falling edge of CS determines
Timing Diagrams
Synchronous Data Timing
SK
01
cs
DO
~L ---------~----__- - '
TL/D/9144-3
'This is the minimum SK period.
2-50
-I
3-
Instruction Timing
1..fl...fl.S1JLJ"l...fLIl...rL.rLf1.J
SK
~
CQ
C
iii"
CQ
CS /
READ
~~______________...______________.~-+
01
__________________
toK.I'K
DO
~
TRI·STATE'"
iiJ
3In
'0
o
;a
TRI·STATE
5'
I:
OJ
S
UUUULJULI~
SK
~
CHECK STATUS
CS /
I\)
STANDBY
WRITE
00
TRI·STATE
.
\------IE/w
\~
I'K
READY'"
TRI·STATE
-I
SK
EWEN
EWDS
CS /
01
'""""\,.,.,._
_ _ _ _ _ _ _ _ _ __
STANDBY
--.f7\
0
XW1MMIMA.
I
ENABLE=l1
DISABLE=OO
TL/D/9144-4
8l'~&60WN
iii
NMC9314B
-I
3'
s'
cc
Instruction Timing
lIUlJl.I1..n..rLflJL
SK
CHECK STATUS
CS /
ERASE
o
iii'
cc
D;
STANDBY
3U)
g>
~
~~--+---~I--.--~I·~'--------~~-------t,.
DI
DO
TRI·STATE
• ~!...lI
TRI-STATE
~
g.
c:
CD
&
n...rLfLf1.1l....rl
SK
I--tcsI}'
U1
CS
J
DI
----.J7\
ERAL
I\)
~
D~~
f7\
0
0
-
TRI-STATE
DO
CHECK STATUS
J-tsv
BUSY
'(-
STANDBY
- J--hH
-TRI-STATE
READY
I---tE/W-
I
SK
CS
I
I
r
I
I
I
I
I
I
I
I
I
I
I
lrLrUULf1.1l....rl
+
-I-
CHECK STATUS
WRAL
DO
':.L!W
TRI-STATE
I'
tE/W-I
TLlD/9144-S
~
z
oco
==
c,,)
oU1
National
~ Semiconductor
NMC93C56/C66 2048-Bit/4096-Bit Serial
Electrically Erasable Programmable Memories
Q)
......
Z
General Description
Compatibility with Other Devices
The NMC93C56/NMC93C66 are 2048/4096 bits of CMOS
electrically erasable memory divided into 128/256 16-bit
registers. They are fabricated using National Semiconductor's floating-gate CMOS process for high speed and low
power. They operate from a single 5V supply since Vpp is
generated on-board. The serial organization allow the
NMC93C56/66 to be packaged in an 8-pin DIP or 14-pin SO
package to save board space.
The memories feature a serial interface with the instruction,
address, and write data, input on the Data-In (01) pin. All
read data and device status come out on the Data-Out (DO)
pin. A low-to-high transition of shift clock (SK) shifts all data
in and out. This serial interface is MICROWIRETM compatible for simple interface to standard microcontrollers and microprocessors. There are 7 instructions: Read, Erase/Write
Enable, Erase, Erase All, Write, Write All, and Erase/Write
Disable. The NMC93C56/66 do not require an erase cycle
prior to the Write and Write All instructions. The Erase and
Erase All instructions are available to maintain complete
read and programming capability with the NMOS NMC9346.
All programming cycles are completely self-timed for simplified operation. The busy status is available on the DO pin to
indicate the completion of a programming cycle. EEPROMs
are shipped in the erased state where all bits are logical 1's.
These memories are pin compatible to National Semiconductor's NMOS EEPROMs, NMC9306 and NMC9346 and
CMOS EEPROMs NMC93C06/46. The NMC93C56/66 are
both pin and function compatible with the NMC93C06/46,
256/1024-bit EEPROM with the one exception that the
NMC93C56/66 require 2 additional address bits.
Features
• Typical active current 400 p.A; Typical standby current
25 p.A
• Reliable CMOS floating gate technology
• 5V only operation in all modes
• MICROWIRE compatible serial I/O
• Self-timed programming cycle
• Device status signal during programming mode
• Sequential register read
• Over 40 years data retention
• Designed for 100,000 write cycles
Block Diagram
cS----------------------.r~IN~~;R~U~;I~ON~l
SK
----r===:::;I--------+j CO~~~O~~~'GlC.
DI
+-Vcc
AND CLOCK
GENERATORS.
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
+-VSS
oo.-----------------~
TL/D/9617-1
2-53
oco
==
c,,)
oQ)
Q)
Connection Diagrams
Dual-In-Llne Package (N)
CS-l
8 -Vee
SK- 2
01- 3
7 -NC
00-4
5 -GNO
6 -NC
Chip Select
SK
Serial Data Clock
01
DO
GND
TLlD/9617 -2
Top View
SO Package (M)
Pin Names
CS
NC- 1
14 -NC
Serial Data Input
CS- 2
SK- 3
13 :-Vee
Serial Data Output
NC- 4
11 !,-NC
Ground
01- 5
00- 6
10 !'-NC
NC- 7
8 !'-NC
Power Supply
12 -NC
9 !'-GNO
See NS Package Number N08E
TLlD/9617-3
Top View
See NS Package Number M14A
Ordering Information
Commercial Temp. Range (O·C to
+ 70·C)
Order Number
NMC93C56NINMC93C66N
NMC93C56MINMC93C66M
Extended Temp. Range (- 400C to
+ 85"C)
Order Number
NMC93C56EN/NMC93C66EN
NMC93C56EM/NMC93C66EM
Military Temp. Range (-S5"Cto
+ 12S·C)
Order Number
NMC93C56MN/NMC93C66MN
NMC93C56MM/NMC93C66MM
2·54
z
Absolute Maximum Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Ambient Operating Temperature
NMC93CS6INMC93C66
NMC93CS6E/NMC93C66E
NMC93CS6MINMC93C66M
(Mil. Temp.)
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temp. (Soldering, 10 sec.)
ESD Rating
- 6S'C to + lS0'C
+6.SVto -0.3V
iii:
g
Co)
Positive Power Supply
O'Cto +10'C
-40'Cto +8S'C
o
en
.....
-5S'C to + 12S'C
iii:
4.SVtoS.SV
leel
ICC2
ICC3
en
Max
Units
Operating Current
CMOS Input Levels
NMC93CS6INMC93C66
NMC93CS6E/NMC93C66E
NMC93CS6M/NMC93C66M*
CS
SK
SK
=
=
=
VIH,SK = 1 MHz
O.S MHz
O.S MHz
2
2
2
mA
Operating Current
TTL Input Levels
NMC93CS6/NMC93C66
NMC93CS6E/NMC93C66E
NMC93CS6M/NMC93C66M
CS
SK
SK
VIH,SK = 1 MHz
O.S MHz
O.S MHz
3
3
4
mA
Standby Current
NMC93CS6/NMC93C66
NMC93CS6E/NMC93C66E
NMC93CS6MINMC93C66M
CS
=
=
=
=
50
100
100
p.A
Conditions
Part Number
Min
OV
IlL
Input Leakage
NMC93CS6/NMC93C66
NMC93CS6E/NMC93C66E
NMC93CS6MINMC93C66M
VIN
=
OV to Vee
-2.S
-10
-10
2.S
10
10
p.A
p.A
IOL
Output Leakage
NMC93CS6/NMC93C66
NMC93CS6E/NMC93C66E
NMC93CS6M/NMC93C66M
VIN
=
OV to Vee
-2.S
-10
-10
2.S
10
10
p.A
p.A
VIL
VIH
Input Low Voltage
Input High Voltage
-0.1
2
Vee + 1
VOL1
Output Low
Voltage
VOH1
Output High
Voltage
VOL2
VOH2
Output Low Voltage
Output High Voltage
ISK
SK Clock Frequency
tSKH
tSKL
tes
tess
NMC93CSS6/NMC93CS66
NMC93CSS6E/NMC93CS66E
NMC93CSS6M/NMC93CS66M
= 2.1 mA
= 2.1 mA
= 1.8mA
IOH = 400 p.A
0.4
0.4
0.4
IOL
IOL
IOL
IOL = 10 p.A
IOH = -10 p.A
2.4
V
V
V
V
0.2
Vee - 0.2
0
0
0
NMC93CS6/NMC93C66
NMC93CS6E/NMC93C66E
NMC93CS6M/NMC93C66M
0.8
1
O.S
O.S
V
V
MHz
NMC93CS6INMC93C66
NMC93CS6E/NMC93C66E
NMC93CS6M/NMC93C66M
(Note 2)
(Note 3)
(Note 3)
2S0
SOO
SOO
ns
NMC93CS6/NMC93C66
NMC93CS6E/NMC93C66E
NMC93CS6M/NMC93C66M
(Note 2)
(Note 3)
(Note 3)
2S0
SOO
SOO
ns
MinimumCS
Low Time
NMC93CS6/NMC93C66
NMC93CS6E/NMC93C66E
NMC93CS6M/NMC93C66M
(Note 4)
(Note S)
(NoteS)
2S0
500
SOO
ns
CS Setup Time
NMC93CS6/NMC93C66
NMC93CS6E/NMC93C66E
NMC93CS6MINMC93C66M
Relative to SK
SO
100
100
ns
SKHighTime
SKLowTime
n
CO
Co)
2000V
Parameter
Z
n
en
+300'C
DC and AC Electrical Characteristics Vee = 5V ± 10% (unless otherwise specified)
Symbol
U1
'Note: Throughout this table "M" refers to temperature range (- SS'C to + 12S'CI, not package type.
2·SS
DC and AC Electrical Characteristics Vcc =
Symbol.
tOIS
Parameter
01 Setup Time
tcsH
CSHoldTime
tOIH
01 Hold Time
tp01
tpDO
tsv
tOF
twp
Output Delay to "1"
Output Delay to "0"
CS to Status Valid
CSto DOin
TRI-STATEIII>
5V ± 10% (unless otherwise specified) (Continued)
Part Number
Conditions
Min
NMC93C56/NMC93C66
NMC93C56E/NMC93C66E
NMC93C56M/NMC93C66M
Relative to SK
100
200
200
Units
ns
N!ax
Relative to SK
0
ns
NMC93C56/NMC93C66
NMC93C56E/NMC93C66E
NMC93C56M/NMC93C66M
Relative to SK
100
200
200
ns
NMC93C56/NMC93C66
NMC93C56E/NMC93C66E
NMC93C56M/NMC93C66M
ACTest
NMC93C56/NMC93C66
NMC93C56E/NMC93C66E
NMC93C56MINMC93C66M
ACTest
NMC93C56/NMC93C66
NMC93C56E/NMC93C66E
NMC93C56MINMC93C66M
ACTest
NMC93C56/NMC93C66
NMC93C56EINMC93C66E
NMC93C56M/NMC93C66M
ACTest
CS = VIL
Write Cycle Time
500
1000
1000
ns
500
1000
1000
ns
500
1000
1000
ns
100
200
200
ns
10
ms
Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: The SK frequency specification for Commercial parts specifies a minimum SK clock period of 1 ,.S, therefore in' an SK clock cycle IsKH + IsKL must be
greater than or equal to t p.o. For example H IsKL = 250 ns then the minimum IsKH = 750 ns in order to meet the SK frequency specHication.
Nole 3: The SK frequency specHication for Extended Temperature and Military parts speCifies a minimum SK clock period of 2 ,.s, therefore in an SK clock cycle
IsKH + IsKL must be greater than or equal to 2 ,.s. For example, if the IsKL = 500 ns then the minimum IsKH = 1.5,.s in order to meet the SK frequency
specHication.
Note 4: For Commercial perts CS must be brought low for a minimum of 250 ns (tcsl between consecutive instruction cycles.
Note 5: For Extended Temperature and Military parts CS must be brought low for a minimum of 500 ns (tcsl between consecutive instruction cycles.
Note 6: This parameter is periodically sampled and not 100% tested.
CapaCitance (Note 6)
TA = 25°Cf = 1 MHz
Symbol
Test
AC Test Conditions
TyP
Max
Units
COUT
Output CapaCitance
5
pF
CIN
Input Capacitance
5
pF
Output Load
Input Pulse Levels
1 TIL Gate and CL = 100pF
0.4Vt02.4V
Timing Measurement Reference Level
Input
Output
2-56
1V and 2V
0.8V and 2V
z
o<0
Co)
oU1
Q)
......
z
3:
o<0
Co)
oQ)
3:
Functional Description
The NMC93C56 and NMC93C66 have 7 instructions as described below. Note that the MSB of any instruction is a "1"
and is viewed as a start bit in the interface sequence. The
next 1O-bits carry the op code and the 8-bit address for
register selection.
Read (READ):
The Read (READ) instruction outputs serial data on the DO
pin. After a READ instruction is received, the instruction and
address are decoded, followed by data transfer from the
selected memory register into a 16-bit serial-out shift register. A dummy bit (logical 0) precedes the 16-bit data output
string. Output data changes are initiated by a low to high
transition of the SK clock.
Write (WRITE):
The Write (WRITE) instruction is followed by 16 bits of data
to be written into the specified address. After the last bit of
data is put on the data-in (01) pin, CS must be brought low
before the next riSing edge of the SK clock. This falling edge
of CS iniliates the self-limed programming cycle. The DO
pin indicates the READY/BUSY status of the chip if CS is
brought high after a minimum of 250 ns (tes). DO = logical
o indicates that programming is still in progress. DO = logical 1 indicates that the register at the address specified in
the instruction has been written with the data pattern specified in the instruction and the part is ready for another instruction.
Erase All (ERAL):
The ERAL instruction will simultaneously program all registers in the memory array and set each bit to the logical '1'
state. The Erase All cycle is identical to the ERASE cycle
except for the different op-code. As in the ERASE mode,
the DO pin indicates the READY/BUSY status of the chip if
CS is brought high after a minimum of 250 ns (tes).
Write All (WRAL):
Erase/Write Enable (EWEN):
When Vee is applied to the part, it powers up in the Erase/
Write Disable (EWDS) state. Therefore, all programming
modes must be preceded by an Erase/Write Enable
(EWEN) instruction. Once an Erase/Write Enable instruclion is executed, programming remains enabled until an
Erase/Write Disable (EWDS) instruction is executed or Vee
is removed from the part.
Erase (ERASE):
Q)
The (WRAL) instruction will simultaneously program all registers with the data pattern specified in the instruction. As in
the WRITE mode, the DO pin indicates the READY/BUSY
status of the chip if CS is brought high after a minimum of
250 ns (tes).
Erase/Write Disable (EWDS):
To protect against accidental data disturb, the Erase/Write
Disable (EWDS) instruction disables all programming modes
and should follow all programming operations. Execution of
a READ instruction is independent of both the EWEN and
EWDS instructions.
The ERASE instruction will program all bits in the specified
register to the logical '1' state. CS is brought low following
the loading of the last address bit. This falling edge of the
CS pin initiates the self-timed programming cycle.
The DO pin indicates the READY/BUSY status of the chip if
CS is brought high after a minimum of 250 ns (tes).
DO = logical '0' indicates that programming is still in progress. DO = logical '1' indicates that the register, at the
address specified in the instruction, has been erased, and
the part is ready for another instruction.
Instruction Set for the NMC93C56 and NMC93C66
S8
OpCode
Address
READ
1
10
A7-AO
EWEN
1
00
11XXXXXX
ERASE
1
11
A7-AO
ERAL
1
00
10XXXXXX
WRITE
1
01
A7-AO
015-00
Writes register if address is unprotected.
WRAL
1
00
01XXXXXX
015-00
Writes all registers. Valid only when Protect Register
is cleared.
EWDS
1
00
OOXXXXXX
Instruction
Comments
Data
Reads data stored in memory.
Write enable must precede all programming modes.
Erase register A7A6A5A4A3A2A1AO.
Erases all registers.
Disables all programming instructions.
•
2-57
Timing Diagrams
Synchronous Data Timing
SK
01
V1H
V1L-----I
V1H_'""I_--+--"'II----_._--+--""----+--V1L _-'II_ _--1_ _-'I_ _ _ _ _J _ _-+__J , ,_ _ _--1_ __
voH _--1I-____"'1
DO (REAO)VOL
~H
DO (PROGRAt.1) v _ _ _ _
OL
~c:::::::::::::::~~~~~::::::::::::::::~
TLl0/9617-4
"'This is the minimum SK period (Note 2).
READ:
csJ
11
11
11
-crr
l~t••
SK~UU1JLJlJlf1MfUl.
DI~~----~111-----~111~---~I~
OO--------------------_~~~~
TLl0/9617-5
• Address bit A7 becomes a "don't care" for NMC93C56.
EWEN:
csJ
SK
01
TL/O/9617-6
2-58
z
:s::
(")
Timing Diagrams (Continued)
CD
Co)
EWDS:
(")
~
z
11
CSJ
:s::
o
CD
Co)
(")
G)
G)
SK
o
DI
o
o
o
TL/O/9617 -7
WRITE:
csJ
JUUlJlfLIUlJLf
11
SK
TUD/9617-B
• Address bH A7 becomes a "don't care" for NMC93C56.
WRAL:
II
UlJLflJU1J1JL
SK
DI
o
o
o
..~~~----------
OO--------------------------------~I!~l----------~l~--_+--~
TL/D/9617-9
2-59
•
Timing Diagrams (Continued)
ERASE:
SK
csJ
01
TL/D/9617 -10
ERAL:
SK
csJ
DI
-.11\_0__0..,/1\ °IllIIWIlll>",
OO __
~TR~I-~~~AIT~
______________________________
~~_+--~
TL/D/9617 -11
2·60
,----------------------------------------------------------------------, z
s:
oCD
~National
oen
~ Semiconductor
c,.)
U1
Q)
......
NMC93CS56/CS66 2048-Bit/4096-Bit Serial
Electrically Erasable Programmable Memories
Z
s:
General Description
The NMC93CS56/NMC93CS66 are 2048/4096 bits of
read/write memory divided into 128/256 registers of 16 bits
each. N registers (N s: 128 or N s: 256) can be protected
against data modification by programming into a special onchip register, called the memory "protect register", the address of the first register to be protected. This address can
be "locked" into the device, so that these registers can be
permanently protected. Thereafter, all attempts to alter data
in a register whose address is equal to or greater than the
address stored in the "protect register" will be aborted.
The "read" instruction loads the address of the first register
to be read into an 8-bit address pointer. Then the data is
clocked out serially on the "DO" pin and automatically cycles to the next register to produce a serial data stream. In
this way the entire memory can be read in one continuous
data stream or as registers of varying length from 16 to
2048/4096 bits. Thus, the NMC93CS56/NMC93CS66 can
be viewed as a non-volatile shift register.
dress in the "protect register" then the data is written 16
bits at a time into one of the 128/256 data registers. If "CS"
is brought "high" following the initiation of a "write" cycle,
the "DO" pin indicates the ready/busy status of the chip.
National Semiconductor's EEPROMs are designed and
tested for applications requiring extended endurance. Refer
to device operation for further endurance information. Data
retention is specified to be greater than 40 years.
Features
II Write protection in user defined section of memory
II Typical active current 400 }LA; Typical standby current
II
II
II
..
..
..
..
a
The "write" cycle is completely self-timed. No separate
erase cycle is required before write. The "write" cycle is
only enabled when pin 6 (program enable) is held "high". If
the address of the register to be written is less than the ad-
25 }LA
Reliable CMOS floating gate technology
5 volt only operation in all modes
MICROWIRE compatible serial I/O
Self-timed programming cycle
Device status signal during programming mode
Sequential register read
Over 40 years data retention
Designed for 100,000 write cycles
Block Diagram
CS------------------------~--;IN~~~R~U~~IO;N__,
SK---r===:;-------+j
DI
DECODER,
CONTROL LOGIC,
AND CLOCK
GENERATORS.
Part Number
Conditions
Min
NMC93CS56/NMC93CS66
NMC93CS56E/NMC93CS66E
NMC93CS56M/NMC93CS66M
Relative to SK
50
100
100
ns
NMC93CS56/NMC93CS66
NMC93CS56E/NMC93CS66E
NMC93CS56M/NMC93CS66M
Relative to SK
100
200
200
ns
Relative to SK
0
ns
Relative to CS
Relative to CS
Relative to CS
250
500
500
ns
NMC93CS56/NMC93CS66
NMC93CS56E/NMC93CS66E
NMC93CS56M/NMC93CS66M
Max
Units
Relative to SK
0
ns
NMC93CS56/NMC93CS66
NMC93CS56E/NMC93CS66E
NMC93CS56M/NMC93CS66M
Relative to SK
100
200
200
ns
NMC93CS56/NMC93CS66
NMC93CS56E/NMC93CS66E
NMC93CS56M/NMC93CS66M
ACTest
NMC93CS56INMC93CS66
NMC93CS56E/NMC93CS66E
NMC93CS56M/NMC93CS66M
ACTest
NMC93CS56/NMC93CS66
NMC93CS56E/NMC93CS66E
NMC93CS56M/NMC93CS66M
ACTest
NMC93CS56/NMC93CS66
NMC93CS56E/NMC93CS66E
NMC93CS56M/NMC93CS66M
ACTest
CS = VIL
500
1000
1000
ns
500
1000
1000
ns
500
1000
1000
ns
100
200
200
ns
10
Write Cycle Time
ms
twp
Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational seelions of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: The SK frequency specification for Commercial parts specifies a minimum SK clock period of 1 microsecond, therefore In an SK clock cycle tsKH + IsKl
must be greater than or equal to 1 microsecond. For example if IsKl = 250 ns then the minimum IsKH = 750 ns in order to meet the SK frequency specification.
Note 3: The SK frequency specification for Extended Temperature and Military parts specifies a minimum SK clock period of 2 microseconds, lherefore in an SK
clock cycle tSKH + IsKl must be greater than or equal to 2 microseconds. For example, if IsKl = 500 ns then the minimum IsKH = 1.5 microseconds in order to
meet the SK frequency specification.
Note 4: For Commercial paris CS must be brought low for a minimum of 250 ns (Ies) between consecutive instruellon cycles.
Note 5: For Extended Temperature and MilHary parts CS must be brought low for a minimum of 500 ns (Ies) between consecutive instruelion cycles.
Note 6: This parameter Is periodically sampled and not 100% tested.
CapaCitance (Note 6)
AC Test Conditions
TA = 25°C, f = lMHz
Symbol
Test
Typ
Max
Units
COUT
Output Capacitance
5
pF
CIN
Input CapaCitance
5
pF
Output Load
1 TTL Gate and CL = 100 pF
Input Pulse Levels
0.4Vto 2.4V
Timing Measurement Reference Level
Input
tV and 2V
Output
0.8V and 2V
2·64
z
s:
Functional Description
The NMC93CS56 and NMC93CS66 have 10 instructions as
described below. Note that the MSB of any instruction is a
"1" and is viewed as a start bit in the interface sequence.
The next 1O-bits carry the op code and the 8-bit address for
register selection.
mum of 250 ns (te5). DO = logical 0 indicates that programming is still in progress. DO = logical 1 indicates that the
register at the address specified in the instruction has been
written with the data pattern specified in the instruction and
the part is ready for another instruction.
Read (READ):
Write All (WRALL):
The Write All (WRALL) instruction is valid only when the
"protect register" has been cleared by executing a
PRCLEAR instruction. The WRALL instruction will simultaneously program all registers with the data pattern specified
in the instruction. Like the WRITE instruction, the PE pin
MUST be held "high" while loading the WRALL instruction,
however, after loading the WRITE instruction the PE pin becomes a "don't care". As in the WRITE mode, the DO pin
indicates the READY IBUSY status of the chip if CS is
brought high after a minimum of 250 ns (te5).
The Read (READ) instruction outputs serial data on the DO
pin. After a READ instruction is received, the instruction and
address are decoded, followed by data transfer from the
selected memory register into a 16-bit serial-out shift register. A dummy bit (logical 0) precedes the 16-bit data output
string. Output data changes are initiated by a low to high
transition of the SK clock. In the NONVOLATILE SHIFTREGISTER mode of operation, the memory automatically
cycles to the next register after each 16 data bits are
clocked out. The dummy-bit is suppressed in this mode and
a continuous string of data is obtained.
Write Disable (WDS):
Write Enable (WEN):
To protect against accidental data disturb, the Write Disable
(WDS) instruction disables all programming modes and
should follow all programming operations. Execution of a
READ instruction is independent of both the WEN and WDS
instructions.
When Vee is applied to the part, it powers up in the Write
Disable (WDS) state. Therefore, all programming modes
must be preceded by a Write Enable (WEN) instruction.
Once a Write Enable instruction is executed programming
remains enabled until a Write Disable (WDS) instruction is
executed or Vee is removed from the part.
Protect Register Read (PRREAD):
The Protect Register Read (PRREAD) instruction outputs
the address stored in the "protect register" on the DO pin.
The PRE pin MUST be held "high" while loading the instruction. Following the PRREAD instruction the 8-bit address
stored in the memory Protect Register is transferred to the
serial out shift register. As in the READ mode, a dummy bit
(logical 0) precedes the 8-bit address string.
Write (WRITE):
The Write (WRITE) instruction is followed by 16 bits of data
to be written into the specified address. After the last bit of
data is put on the data-in (DI) pin, CS must be brought low
before the next rising edge of the SK clock. This falling edge
of CS initiates the self-timed programming cycle. The PE pin
MUST be held "high" while loading the WRITE instruction,
however, after loading the WRITE instruction the PE pin becomes a "don't care". The DO pin indicates the READY I
BUSY status of the chip if CS is brought high after a mini-
Protect Register Enable (PREN):
The Protect Register Enable (PREN) instruction is used to
enable the PRCLEAR, PRWRITE, and PRDS modes. Before
Instruction Set for the NMC93CS56 and NMC93CS66
S8
OpCode
Address
READ
Instruction
1
10
A7-AO
Data
PRE
PE
Comments
0
X
Reads data stored in memory, starting at specified address.
WEN
1
00
11XXXXXX
WRITE
1
01
A7-AO
D15-DO
0
1
Write enable must precede all programming modes.
0
1
Writes register if address is unprotected.
WRALL
1
00
01XXXXXX
D15-DO
0
1
Writes all registers. Valid only when Protect Register is
cleared.
WDS
1
00
OOXXXXXX
0
X
Disables all programming instructions.
PRREAD
1
10
XXXXXXXX
1
X
Reads address stored in Protect Register.
PREN
1
00
11XXXXXX
1
1
Must immediately precede PRCLEAR, PRWRITE, and
PRDS instructions.
PRCLEAR
1
11
11111111
1
1
Clears the "protect register" so that no registers are
protected from WRITE.
PRWRITE
1
01
A7-AO
1
1
Programs address into Protect Register. Thereafter,
memory addresses ;0: the address in Protect Register are
protected from WRITE.
PROS
1
00
00000000
1
1
One time only instruction after which the address in the
Protect Register cannot be altered.
2-65
o<0
(0)
o
en
U1
al
.......
Z
s:
o<0
(0)
o
en
al
al
Functional Description (Continued)
the PREN mode can be entered, the part must be in the
Write Enable (WEN) mode. Both the PRE and PE pins
MUST be held "high" while loading the instruction.
than or equal to the address specified in the Protect Register are protected from the WRITE operation. Note that before executing a PRWRITE instruction the Protect Register
must first be cleared by executing a PRCLEAR operation
and that the PRE and PE pins must be held "high" while
loading the instruction, however, after loading the PRWRITE
instruction the PRE and PE pins become 'don't care'. Note
that a PREN instruction must immediately precede a
PRWRITE instruction.
Note that a PREN instruction must Immediately precede a
PRCLEAR, PRWRITE, or PROS instruction.
Protect Register Clear (PRCLEAR):
The Protect Register Clear (PRCLEAR) instruction clears
the address stored in the Protect Register and, therefore,
enables all registers for the WRITE and WRALL instruction.
The PRE and PE pins must be held "high" while loading the
instruction, however, after loading the PRCLEAR instruction
the PRE and PE pins become "don't care". Note that a
PREN instruction must Immediately precede a PRCLEAR
instruction.
Protect Register Disable (PROS):
The Protect Register Disable (PROS) instruction is a one
time only instruction which renders the Protect Register unalterable in the future. Therefore, the specified registers become PERMANENTLY protected against data changes. As
in the PRWRITE instruction the PRE and PE pins must be
held "high" while loading the instruction, and after loading
the PROS instruction the PRE and PE pins become "don't
care".
Note that a PREN instruction must immediately precede a
PROS instruction.
Protect Register Write (PRWRITE):
The Protect Register Write (PRWRITE) instruction is used to
write into the Protect Register the address of the first register to be protected. After the PRWRITE instruction is executed, all memory registers whose addresses are greater
Timing Diagrams
Synchronous Data Timing
-
-
tpRES i"--
~ tpREH
I-
X
tpES i"--
~
::.ItPEH
-
II's'
tSKH
'I'
t SKL -
I
t DiS
I'-lcsH
.IIoIH
I
:::::=:J
X
~tpDl
tpDO
T
\:
Isvi
STATUS VALID
I::j
::1
tor
lor
TL/D/9209-4
'This is the minimum SK period (See Note 2).
2-66
Timing Diagrams (Continued)
READ:'
PRE=O,PE=X
csJ
II
II
__
01~Y2A""' ~1!1
r
II
I~t ••
~1 1
~1~
_____ ____
"Y:J
TL/D/9209-5
'Address bit A7 becomes a "don't care" for NMC93CS56.
'The memory automalically cycles to the next register.
WEN:
PRE = 0, DO = TRI·STATE
II
csJ
SK
01
.~-------------
2-67
TUD/9209-6
Timing Diagrams (Continued)
.WDS:
PRE = 0, PE = X, DO = TRI-STATE
csJ
21
SK
01
o
o
o
o
TUD/9209-7
WRITE:'
PRE = 0
II
csJ
SK
21
t\\\\\\\\\\\
21
5LJlJlJUlJUUU
Ol~~~______________________
00
" .
b~:1
READY
TUD/9209-8
• Address bit A7 becomes a "don't care" for NMC93CS56.
2-68
z
iii:
oCD
Co)
o
en
U1
Timing Diagrams (Continued)
-
WRALL:*
PRE = 0
en
K\\\\\\
Z
iii:
oCD
oen
Co)
csJ
11
en
en
UUUUUUUL
SK
o
01
o
..~~-------------
o
OO--------------------------------~I·~I----------~~----_+--~
TLlD/9209-9
'Protect Register MUST be cleared.
PRREAD:*
PE = X
PRE
J
csJ
11
1/
TL/D/9209-10
'Address bit A7 becomes a "don't care" for NMC93CS56.
2-69
Timing Diagrams (Continued)
PREN:O
DO = TRI-5TATE
11
PREJ
11
11
SK
..~--------------
01
TLID/S20S-11
• A WEN cycle must precede a PREN cycle.
PRCLEAR:'
PRE
J
11
f\\\\\\\\\\\\
11
t\\\\\\\\\\
csJ
JlJlJUlJlJ
II
SK
11
1\'--_____
01--1 1
OO----------~111 -------+b--~
.....
- '-
TLID/S20S-12
• A PREN cycle must Immediately precede a PRCLEAR cycle.
2·70
z
n
CD
3:
Timing Diagrams (Continued)
PRWRITE:t
PRE
J
11
Co)
n
en
U1
K\\\\\\\\\\\\\\\'
II
en
......
Z
3:
n
CD
K\\\\\\\\\\\\\\'
CSJ
Co)
n
en
en
en
\'-----
SKJUUl11IU
Ol~~_________________________________
lsJ .~ \\-----
00
TLlD19209-13
'Address bit A7 becomes a "don't care" for NMC93CS56.
tprotect Register MUST be cleared before a PRWRITE cycle. A PREN cycle mustlmmedlalely precede a PRWRITE cycle.
PROS:'
PRE
J
II
t\\\\\\\\w
II
K\\\\\\\\'
csJ
SKJUUl11IU
11
01
r0.0
~
0
II
o
0"'0
o
o
, ~~I-------------------------------------
OO-------------------~!il~------------~~--~~...
'TLlD19209-14
'ONE TIME ONLY instruction. A PREN cycle must Immediately precede a PROS cycle.
2-71
~NaHonal
~ Semiconductor
NMC93CS06x3/CS46x3/CS56x3/CS66x3
Extended Voltage 256-/1024-/2048-/4096-Bit
Serial EEPROM with Protect Register
General Description
The NMC93CS family of extended operating voltage serial
EEPROM are 256/1024/2048/4096 bits of readlwrite
memory divided into 16/64/128/256 registers of 16 bits
each. N registers (N';;16, N';;64, N';;128, N,;;256) can be
protected against data modification by programming a special on-chip register called the Protect Register with the address of the first register to be protected against data modification. Additionally, this address can be "locked" into the
device, making all future attempts to change data impossible.
These memories feature a serial interface with the instruction, address, and write data input on the Data-In pin. All
data-out, and device status are available on the Data-Out
pin. A low to high transition of Serial Data Clock (SK) shifts
all data in or out of the memory. This serial interface is
MICROWIRETM compatible providing simple interfacing to
standard microcontrollers and microprocessors. There are a
total of 10 instructions, 5 which operate on the EEPROM
memory, and 5 which operate on the Protect Register. The
memory instructions are READ, WRITE, WRITE ALL,*
WRITE ENABLE, and WRITE DISABLE. To perform any of
the memory instructions, the input PRE must be low. The
instructions to the Protect Register are similar, except the
'The WRITE ALL instruction is only functional from 4.5V to 5.5V Vee. Its
primary purpose is as a test mode.
input PRE must be high. The Protect register instructions
are PRREAD, PRWRITE, PREN, PRCLEAR, and PROS.
These memories feature a unique EEPROM memory cell
which does not require eraSing prior to writing, therefore
reduces the total number of programming cycles, thus increasing the endurance of the device in actual application.
These EEPROM memories are designed for applications requiring 40 years data retention and 100,000 data changes
per bit. They are ideal for battery operated applications due
to the wide operating voltage range. They are fully functional in all modes of operation across a guaranteed range of
3.0V,..5.5V.
Features
III 3.0V to 5.5V guaranteed operating range
II Typical active current 400 ,",A; typical standby current
25 ,",A
II Write protection in a user defined section of memory
.. Reliable CMOS floating gate technology
.. MICROWIRE compatible serial 1/0
II Self timed write cycle
II Device status during write mode
II 40 year data retention
I!I 100,000 data changes per bit
Block Diagram
~----------------------+f~IN~s~ffi~u~~oN;-l
SK
DI
DECODER,
~V~
1+-----------
PRE
CO:~O~L~~~IC, ~------......- - PE
GENERATORS.
ADDRESS COMPARE
AND
WRITE ENABLE
....________... EN
oo.-----------------~
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
TUO/10044-1
2-72
z
5:
Connection Diagrams
CsOs
n
CD
PIN OUT:
Dual-In-Line Package (N)
SK2
Vee
7
PRE
01
3
6
PE
00
4
5
~O
TL/D/l0044-2
Pin Names
CS Chip Select
SK Serial Data Clock
DI
Serial Data Input
DO Serial Data Output
GND Ground
Program Enable
PE
PRE Protect Register Enable
Vee Power Supply
Co)
n
(/)
PIN OUT:
SO Package (M)
NC-1
Top View
'-'
CI
en
>C
141-NC
CS-2
131-Vce
SK- 3
12 rPRE
NC- 4
11rNC
01- 5
10l-PE
00- 6
91-GNO
NC- 7
Sl-NC
See NS Package Number NOSE
TL/D/l0044-3
Top View
See NS Package Number M14A
Co)
......
n
(/)
~
en
>C
Co)
......
(')
(/)
(II
en
>C
Co)
......
n
(/)
en
en
>C
Co)
Ordering Information
Commercial Temp. Range (O"C to
+ 70'C)
Order Number
NMC93CS06N3/
NMC93CS46N3/NMC93CS56N3/NMC93CS66N3
NMC93CS06M3/
NMC93CS46M3/NMC93CS56M3/NMC93CS66M3
Extended Temp. Range ( - 40'C to
+ 85'C)
Order Number
NMC93CS06EN3/
NMC93CS46EN3/NMC93CS56EN3/NMC93CS66EN3
NMC93CS06EM3/
NMC93CS46EM3/NMC93CS56EM3/NMC93CS66EM3
2-73
Absolute Maximum Ratings
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Ambient Operating Temperature
NMC93CSxx
NMC93CSxxE
Ambient Storage Temperature
Positive Power Supply
- 65'C to + 150'C
All Input or Output Voltages
with Respect to Ground
3.0Vt05.5V
+ 6.5V to -0.3V
Lead Temperature (Soldering. 10 sec.)
ESD rating
O"Cto +70'C
-40"Cto +85'C
+300'C
2000V
DC and AC Electrical Characteristics Vcc = 3.0V to 5.5V unless otherwise specified
Symbol
Parameter
Part Number
Conditions
Min
Peak·to-Peak
(Note 7)
Max
Units
0.1 Vee
V
VRPP
Power Supply Ripple
ICC1
Operating Current
CMOS Input Levels
NMC93CS06-NMC93CS66
NMC93CS06E- NMC93CS66E
CS
1.0 MHz
2
2
mA
ICC2
Operating Current
TTL Input Levels
NMC93CS06-NMC93CS66
NMC93CS06E-NMC93CSS66E
CS = VIH. SK = 1.0 MHz
4.5V 05: Vcc 05: 5.5V
3
3
mA
Icca
Standby Current
NMC93CS06-NMC93CS66
NMC93CS06E- NMC93CS66E
CS
= OV
50
100
/LA
IlL
Input Leakage
NMC93CS06-NMC93CS66
NMC93CS06E-NMC93CS66E
VIN
= OV to Vcc
-2.5
-10
2.5
10
/LA
IOL
Output Leakage
NMC93CS06-NMC93CS66
NMC93CS06E-NMC93CSS66E
VOUT
-2.5
-10
2.5
10
/LA
VIL1
VIH1
Input Low Voltage
Input High Voltage
4.5V05:Vcc05:5.5V
VIL2
VIH2
Input Low Voltage
"Input High Voltage
3V05:Vee05:4.5V
VOL1
VOH1
Output Low Voltage
Output High Voltage
4.5V05:Vcc05:5.5V
IOL = 2.1 mA
IOH = -400/LA
VOL2
VOH2
Output Low Voltage
Output High Voltage
3V05:Vcc05:4.5V
IOL = 10 /LA
IOH = -10/LA
fSK
SK Clock Frequency
NMC93CS06-NMC93CS66
NMC93CS06E-NMC93CS66E
tSKH
SK High Time
NMC93CS06-NMC93CS66
NMC93CS06E-NMC93CS66E
(Note 2)
(Note 3)
500
500
ns
tSKL
SKLowTime
NMC93CS06-NMC93CS66
NMC93CS06E-NMC93CS66E
(Note 2)
(Note 3)
250
500
ns
tcs
MinimumCS
Low Time
NMC93CS06-NMC93CS66
NMC93CS06E-NMC93CS66E
(Note 4)
(Note 5)
250
500
ns
tcss
CS Setup Time
NMC93CS06-NMC93CS66
NMC93CS06E-NMC93CS66E
Relative to SK
50
100
ns
tpRES
PRE Setup Time
NMC93CS06-NMC93CS66
NMC93CS06E-NMC93CS66E
Relative to SK
50
100
ns
tPES
PE Setup Time
NMC93CS06-NMC93CS66
NMC93CS06E-NMC93CS66E
Relative to SK
50
100
ns
to IS
DI Setup Time
NMC93CS06-NMC93CS66
NMC93CS06E-NMC93CS66E
Relative to SK
100
200
ns
=
VIH. SK
=
= OV to Vcc
0.8
2
2-74
-0.1
2
V
0.6
Vee + 1
V
0.4
V
0.2
V
1
0.5
MHz
2.4
Vcc - 0.2
0
0
DC and AC Electrical Characteristics Vcc = 3.0V to 5.5V unless otherwise specified (Continued)
Symbol
Part Number
Parameter
tCSH
CSHoldTime
tpEH
PE Hold Time
NMC93CS06-NMC93CS66
NMC93CS06E-NMC93CS66E
Conditions
Min
Relative to SK
0
Max
Units
ns
Relative to CS
Relative to CS
250
500
ns
Relative to SK
0
ns
Relative to SK
100
200
ns
tpREH
PRE Hold Time
tOIH
DIHoldTime
NMC93CS06-NMC93CS66
NMC93CS06E-NMC93CS66E
tp01
Output Delay to "1"
NMC93CS06-NMC93CS66
NMC93CS06E- NMC93CS66E
ACTest
500
1000
ns
NMC93CS06-NMC93CS66
NMC93CS06E-NMC93CS66E
ACTest
500
1000
ns
NMC93CS06-NMC93CS66
NMC93CS06E-NMC93CS66E
ACTest
500
1000
ns
NMC93CS06-NMC93CS66
NMC93CS06E-NMC93CS66E
CS = VIL
ACTest
100
200
ns
15
ms
Output Delay to "0"
tpoo
tsv
CS to Status Valid
tOF
CSto DOin
TRI-STATE®
twp
Write Cycle nme
Endurance
Number of
Data Changes
per Bit
Typical
100,000
Cycles
Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: The SK frequency specification for Commercial parts specifies a minimum SK clock period of 1 microsecond, therefore in an SK clock cycle IsKH + IsKL
must be greater than or equal to 1 microsecond. For example if IsKL = 250 ns then the minimum tSKH = 750 ns in order to meet the SK frequency specification.
Note 3: The SK frequency specification for Extended Temperature parts specifies a minimum SK clock period of 2 microseconds,therefore in an SK clock cycle
IsKH + IsKL must be greater than or equal to 2 microseconds. For example, if IsKL = 500 ns then the minimum tSKH = t.5 microseconds in order to meet the SK
frequency specification.
Note 4: For Commercial parts CS must be brought low for a minimum of 250 ns (Ies) between consecutive Instruction cycles.
Note 5: For Extended Temperature parts CS must be brought low for a minimum of 500 ns (Ies) between consecutive instruction cycles.
Note 6: This parameter is periodically sampled and not 100% tested.
Note 7: Rate of voltage change must be less than 0.5 Vlms.
CapaCitance (Note 6)
TA
=
25'C, f
Symbol
=
AC Test Conditions
1MHz
Test
Output Load
Typ
Max
Units
COUT
Output Capacitance
5
pF
CIN
Input Capacitance
5
pF
2-75
1 TTL Gate and CL
=
100 pF
Input Pulse Levels
0.4Vt02.4V
Timing Measurement Reference Level
Input
Output
W and 2V
O.BV and 2V
~.-------------------------------------------------~
~
~
.....
~
~
Lt)
tJ)
o
.....
~
~
oo:r
tJ)
o.....
~
~
o
til
o
~
0)
o
z
:::iE
Functional Description
The NMC93CSxx family of extended voltage EEPROM have
10 instructions as described below. Note that there is a difference in the length of the instruction for the NMC93CS06
and NMC93CS46 vs. the NMC93CS56 and NMC93CS66.
This is due to the fact that the two larger devices require 2
additional address bits which are not required for the smaller devices. Within the two groups of devices the number of
address bits remain constant even though in some cases
the most significant bites) are not used. In every instruction,
the first bit is always a "I" and is viewed as a start bit. The
next B or 10 bits (depending on device size) carry the op
code and address. The address is either 6 or B bits depending on the device size.
Write Disable (WDS):
To protect against accidental data distUrb, the Write Disable
(WDS) instruction disables all programming modes and
should follow all programming operations. Execution of a
READ instruction is independent of both the WEN and WDS
instructions.
Protect Register Read (PRREAD):
The Protect Register Read (PRREAD) instruction outputs
the address stored in the Protect Register on the DO pin.
The PRE pin MUST be held high while loading the instruction. Following the PRREAD instruction the 6- or B-bit address stored in the memory protect register is transferred to
the serial out shift register. As in the READ mode, a dummy
bit (logical 0) precedes the 6- or B-bit address string.
Read (READ):
The Read (READ) instruction outputs serial data on the DO
pin. After a READ instruction is received, the instruction and
address are decoded, followed by data transfer from the
selected memory register into a 16-bit serial-out shift register. A dummy bit (logical 0) precedes the 16-bit data output
string. Output data changes are initiated by a low to high
transition of the SK' clock. In the NONVOLATILE SHIFTREGISTER mode of operation, the memory automatically
cycles to the next register after each 16 data bits are
clocked out. The dummy-bit is suppressed in this mode and
a continuous string of data is obtained.
Protect Register Enable (PREN):
The Protect Register Enable (PREN) instruction is used to
enable the PRCLEAR, PRWRITE, and PRDS modes. Before
the PREN mode can be entered, the part must be in the
Write Enable (WEN) mode. Both the PRE and PE pins
MUST be held high while loading the instruction.
Note that a PREN instruction must Immediately precede a
PRCLEAR, PRWRITE, or PRDS instruction.
Protect Register Clear (PRCLEAR):
The Protect Register Clear (PRCLEAR) instruction clears
the address stored in the Protect Register and, therefore,
enables all registers for the WRITE and WRALL instruction.
The PRE and PE pins must be held high while loading the
instruction, however, after loading the PRCLEAR instruction
the PRE and PE pins become "don't care". Note that a
PREN instruction must immediately precede a PRCLEAR
instruction.
Write Enable (WEN):
When Vee is applied to the part, it "powers up" in the Write
Disable (WDS) state. Therefore, all programming modes
must be preceded by a Write Enable (WEN) instruction.
Once a Write Enable instruction is executed programming
remains enabled until a Write Disable (WDS) instruction is
executed or Vee is removed from the part.
Write (WRITE):
Protect Register Write (PRWRITE):
The Protect Register Write (PRWRITE) instruction is used to
write into the Protect Register the address of the first register to be protected. After the PRWRITE instruction is executed, all memory registers whose addresses are grea~er
than or equal to the address specified in the Protect Register are protected from the WRITE operation. Note that before executing a PRWRITE instruction the Protect Register
must first be cleared by executing a PRCLEAR operation
and that the PRE and PE pins must be held high while
loading the instruction, however, after loading the PRWRITE
instruction the PRE and PE pins become 'don't care'. Note
that a PREN instruction must immediately precede a
PRWRITE instruction.
The Write (WRITE) instruction is followed by 16 bits of data
to be written into the specified address. After the last bit of
data is put on the data-in (DI) pin, CS must be brought low
before the next rising edge of the SK clock. This falling edge
of the CS initiates the self-timed programming cycle. The PE
pin MUST be held high while loading the WRITE instruction,
however, after loading the WRITE instruction the PE pin becomes a "don't care". The DO pin indicates the READY I
BUSY status of the chip if CS is brought high after a minimum of 250 ns (teg). DO = logical 0 indicates that programming is still in progress. DO = logical 1 indicates that the
register at the address specified in the instruction has been
written with the data pattern specified in the instruction and
the part is ready for another instruction.
Protect Register Disable (PRDS):
Write All (WRALL):
The Protect Register Disable (PRDS) instruction is a one
time only instruction which renders the Protect Register unalterable in the future. Therefore, the specified registers become PERMANENTLY protected against data changes. As
in the PRWRITE instruction the PRE and PE pins must be
held high while loading the instruction, and after loading the
PRDS instruction the PRE and PE pins become "don't
The Write All (WRALL) instruction is valid only when the
Protect Register has been cleared by executing a
PRCLEAR instruction. Additionally, it is only guaranteed at
Vee = 5.0V ± 10%. The WRALL instruction will sim~~ta
neously program all registers with the data pattern specified
in the instruction. Like the WRITE instruction, the PE pin
MUST be held high while loading the WRALL instruction,
however, after loading the WRITE instruction the PE pin b~
comes a "don't care". As in the WRITE mode, the DO pm
indicates the READY IBUSY status of the chip if CS is
brought high after a minimum of 250 ns (teg).
care".
Note that a PREN instruction must Immediately precede a
PRDS instruction.
2-76
Instruction Set for the NMC93CS06x3 and NMC93CS46x3
z
o
CD
is:
Co)
READ
1
10
A5-AO
0
PE
X
WEN
1
00
11XXXX
0
1
Write enable must precede all programming modes.
en
><
Co)
WRITE
1
01
A5-AO
015-00
0
1
Writes register if address is unprotected.
?;
WRALL
1
00
01XXXX
015-00
0
1
Writes all registers. Valid only when Protect Register is
cleared. Valid only at Vee = 4.5V to 5.5V.
en
><
Co)
WOS
1
00
OOXXXX
0
Disables all programming instructions.
PRREAO
1
10
XXXXXX
1
X
X
PREN
1
00
11XXXX
1
1
Must immediately precede PRCLEAR, PRWRITE, and
PROS instructions.
PRCLEAR
1
11
111111
1
1
Clears the Protect Register so that no registers are
protected from WRITE.
PRWRITE
1
01
A5-AO
1
1
Programs address into Protect Register. Thereafter,
memory addresses ~ the address in Protect Register are
protected from WRITE.
PROS
1
00
000000
1
1
One time only instruction after which the address in the
Protect Register cannot be altered.
Instruction
S8
OpCode
Address
Data
PRE
Comments
Reads data stored in memory, starting at specified address.
f6
CI
tJ)
Reads address stored in Protect Register.
0l:Io
.......
o
en
U1
en
~
"'
~
en
en
~
Instruction Set for the NMC93CS56x3 and NMC93CS66x3
S8
OpCode
Address
READ
1
10
A7-AO
0
PE
X
WEN
1
00
11XXXXXX
0
1
Instruction
Data
PRE
Comments
Reads data stored in memory, starting at specified address.
Write enable must precede all programming modes.
WRITE
1
01
A7-AO
015-00
0
1
Writes register if address is unprotected.
WRALL
1
00
01XXXXXX
015-00
0
1
Writes all registers. Valid only when Protect Register is
cleared. Valid only at Vee = 4.5V to 5.5V.
WOS
1
00
OOXXXXXX
0
1
10
XXXXXXXX
1
X
X
Disables all programming instructions.
PRREAO
PREN
1
00
11XXXXXX
1
1
Must immediately precede PRCLEAR, PRWRITE, and
PROS instructions.
PRCLEAR
1
11
11111111
1
1
Clears the "protect register" so that no registers are
protected from WRITE.
PRWRITE
1
01
A7-AO
1
1
Programs address into Protect Register. Thereafter,
memory addresses ~ the address in Protect Register are
protected from WRITE.
PROS
1
00
00000000
1
1
One time only instruction after which the address in the
Protect Register cannot be altered.
Reads address stored in Protect Register.
•
2-77
~
~
~
.....
,---------------------------------------------------------------------------------,
Timing Diagrams
Synchronous Data Timing
---
~
~
.....
~
~
.....
~
t pRES
I-----
tpES
I-----
-
tess
'I'
IsKH
~
-
1 ps·
IsKL-
I
t DiS
--
o
z
:::i
,I
I
!csH
tOIH
X
::::1lpoo
X
~tpOl
lk
VOH
I
::.itpEH
---J
~
G)
tpREH
f
Isv~
DO (PROGRAM) V
:jtDF
=1
tor
STATUS VALID
OL
TUD/10044-4
'This is the minimum SK period (See Note 2).
READ:
PRE=O,PE=X
11
11
SK
11
.JlJ1nJWUlJ1JlJ1MJUlJUl
DI~~~----~III----------~lil----------~I.~
DO
\JE)()G@()G@(r
'Address bit A7 becomes "don't care" for NMC93CS56
'Address bits A5 and A4 become "don't cares" for NMC93CS06
TlID/10044-5
tThe memory automatically cycles to the next register.
2·78
z
3:
Timing Diagrams (Continued)
~
WEN:
PRE = 0, DO = TRI-STATE
11
Co)
~
K\\\\\\\\\\
o
en
~
.......
o(J)
11
csJ
.j:>.
en
><
Co)
.......
o(J)
U1
en
><
Co)
.......
o
.X\""-----
01
en
en
en
><
Co)
TL/D/l0044-6
'The NMC93GS56 and NMC93GS66 require a minimum of 11 clocks. The NMC93CS06 and NMC93CS46 require a minimum of 9 clock cycles.
PRE =
cs
J
0, PE
=
WDS:
X, DO
=
TRI-STATE
11
SK'
01
o
o
o
o
TUD/l0044-7
'The NMC93CS56 and NMC93CS66 require a minimum of 11 clocks. The NMC93GS06 and NMC93CS46 require a minimum of 9 clock cycles.
WRITE:
PRE = 0
t\\\\\\\\\\\ '
L
•
SK
01
DO--~b~t
twp=-i
READY
\...
TL/D/l0044-8
• Address bH A7 becomes a "don't care" for NMC93GS56
• Address bHs A5 and A4 become "don't cares" for NMC93CS06
2-79
Timing Diagrams (Continued)
WRALLt:
PRE = 0
f\\\\\\\
csJ
L
SK
o
DI
o
o
DO---------------+-L~\
BUsyj
~tw~
·Don't care
READY
~
TLlD/10044-9
tProtect Register MUST be cleared.
tVaiid only at Vee = 4.5V to 5.5V.
PRREAD:
PE= X
PREJ
SK
DI---.! 1
1 ~~____________________________
DO------------------------~
TLlD/10D44-10
-Address bRs A5 and A4 become "don't cares" for NMC93CS06
-Address bR A7 becomes "don't care" for NMC93CS56
2-80
Timing Diagrams (Continued)
PREN*:
DO = TRI-STATE
PRE
cs
J
J
SK
DI
__0.l/1
~_O
TLlD11oo44-11
°A WEN cycle must precede a PREN cycle.
PRCLEAR*:
PRE
J
CSJ
L
SK
01-.1
1\'--____
DO-------------+L~\ ~
1
BUSY
~
°A PREN cycle must Immediately precede a PRCLEAR cycle.
2-81
READY
\.
TLlDI10044-12
•
Timing Diagrams (Continued)
PRWRITEt:
PRE
J
csJ
SK
DI
DO-----+--lsJ
READY
,'-----TLiO/l00M-1S
'Address bit A7 becomes a "don't care" for NMC93CSS6
'Address bits AS and A4 become "don't cares" for NMC93CS06
tProtect Register MUST be cleared before a PRWRITE cycle. A PREN cycle must Immediately precede a PRWRITE cycle.
PROS':
PRE
J
L
SK
rn
____O
_____O
________O
____O
____O
____O
_________________________
~~O
DO----------------IL-s -
'TLiD/l0044-14
'ONE TIME ONLY Instruction. A PREN cycle must Immediately precede a PROS cycle.
2-82
z
is:
PRELIMINARY o
CD
~National
Co)
~ Semiconductor
o
o
NMC93C06x3/C46x3/C56x3/C66x3
Extended Voltage 256-/1024/2048/4096-Bit
Serial EEPROM
.......
0')
General Description
The NMC93C06x3/C46x3/C56x3/C66x3 are 256/1024/
2048/4096 bits of CMOS electrically erasable memory divided into 16/64/1281256 16-bit registers. They are fabricated using National Semiconductor's floating-gate CMOS
process for high speed and low power. They operate from a
single 3.0V to 5.5V supply since Vpp is generated on-board.
The serial organization allow the NMC93C06x3/C46x3/
C56x3/C66x3 to be packaged in an 8-pin DIP or 14-pin SO
package to save board space.
The memories feature a serial interface with the instruction,
address, and write data, input on the Data-In (01) pin. All
read data and device status come out on the Data-Out (DO)
pin. A low-to-high transition of shift clock (SK) shifts all data
in and out. This serial interface is MICROWIRETM compatible for simple interface to standard microcontrollers and microprocessors. There are 7 instructions: Read, Erase/Write
Enable, Erase, Erase All', Write, Write All', and Erase/
Write Disable. The NMC93C06x3/C46x3/C56x3/C66x3 do
not require an erase cycle prior to the Write and Write All
instructions. The Erase and Erase All instructions are available to maintain complete read and programming capability
with the NMOS NMC9346. All programming cycles are completely self-timed for simplified operation. The busy status Is
><
Co)
z
is:
oCD
o0l:Io
Co)
available on the DO pin to indicate the completion of a programming cycle. EEPROMs are shipped in the erased state
where all bits are logical 1'So
0')
><
Co)
.......
z
is:
Compatibility with Other Devices
These memories are pin compatible to National Semiconductor's NMOS EEPROMs, NMC9306 and NMC9346 and
CMOS EEPROMs NMC93C06x3/C46x3/C56x3/C66x3.
oen
0')
~
.......
z
is:
Features
~
0')
• Typical active current 400 /LA; Typical standby current
25/LA
• Reliable CMOS floating gate technology
• 3.0V to 5.5V operation in all modes
• MICROWIRE compatible serial I/O
• Self-timed programming cycle
• Device status Signal during programming mode
• Sequential register read
• 40 years data retention
• 100,000 write cycles
·The Instructions Erase All and Write All are functional only from Vee
~
=
4.5V to 5.5V. Their primary purpose is as test modes.
Block Diagram
~----------------------~r-~IN~s;m~ucr~lo;N--'
SK----i====;---------~
01
DECODER,
CONTROL LOGIC,
AND CLOCK
GENERATORS.
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
•
00+----------1
TL/D/l0045-1
2-83
Connection Diagrams
csOs
Dual-In-Llne Package (N)
and B-Pln SO (MB)
SK
2
01
3
004
7
Vee
NC
6
NC
14-Pln SO Package (M)
Pin Names
5GNO
TL/O/10045-2
Top View
CS
Chip Select
SK
Serial Data Clock
CS- 2
13 """Vee
01
Serial Data Input
SK- 3
12 """Ne
DO
Serial Data Output
NC- 4
11 """NC
01- 5
10 t-NC
GND
Ground
Vee
Power Supply
NC- 1
14 """NC
00- 6
9 rGNO
NC- 7
8rNC
See NS Package Number NOBE
TL/0/10045-3
Top View
See NS Package Number M14A
Ordering Information
Commercial Temp. Range (O"C to
+ 70"C)
Order Number
NMC9SC06NS
NMC9SC46NS/NMC9SC56NS/NMC9SC66NS
NMC9SC46MS/NMC9SC56MS/NMC9SC66MS
NMC9SC06M8S/NMC9SC46M8S
Extended Temp. Range (- 40"C to
+ BS·C)
Order Number
NMC9SC06ENS
NMC9SC46ENS/NMC9SC56ENS/NMC9SC66ENS
NMC9SC46EMS/NMC9SC56EMS/NMC9SC66EMS
NMC9SC06EM8S/NMC9SC46EM8S
2-84
Absolute Maximum Ratings
Ambient Operating Temperature
NMC93C56-NMC93C66
NMC93C56E-NMC93C66E
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temp. (Soldering, 10 sec.)
ESD Rating
-65·C to + 150·C
Co)
O·C to + 10·C
-40·Cto +85·C
Positive Power Supply
3.0Vt05.5V
+6.5Vto -0.3V
Part Number
""~
3.0V to 5.5V (unless otherwise specified)
Conditions
Min
~
Max
Units
lee1
Operating Current
CMOS Input Levels
NMC93C06·NMC93C66
NMC93C06E·NMC93C66E
CS = VIH, SK = 0.5 MHz
2
2
mA
lee2
Operating Current
TTL Input Levels
NMC93C06·NMC93C66
NMC93C06E·NMC93C66E
CS = VIH. SK = 0.5 MHz
3
3
mA
lee3
Standby Current
NMC93C06·NMC93C66
NMC93C06E·NMC93C66E
CS = OV
50
100
",A
IlL
Input Leakage
NMC93C06·NMC93C66
NMC93C06E·NMC93C66E
VIN = OV to Vee
-2.5
-10
2.5
10
",A
IOL
Output Leakage
NMC93C06·NMC93C66
NMC93C06E·NMC93C66E
VIN = OV to Vee
-2.5
-10
2.5
10
",A
VIL1
VIH1
Input Low Voltage
Input High Voltage
4.5V ,;; Vee';; 5.5V
VIL2
VIH2
Input Low Voltage
Input High Voltage
3V ,;; Vee';; 4.5V
VOL1
VOH1
Output Low Voltage
Output High Voltage
4.5V ,;; Vee';; 5.5V
IOL = 2.1 mA
IOH = -400 ",A
VOL2
VOH2
en
~
.....
Z
s:
Co)
2000V
Parameter
oo
oCD
o
+300·C
DC and AC Electrical Characteristics Vee =
Symbol
z
o
CD
s:
Operating Conditions
(Note 1)
0.8
2
Output Low Voltage
Output High Voltage
3V ,;; Vee';; 4.5V
IOL=10",A
IOH = -10 ",A
-0.1
2
0.6
Vee + 1
0.2
V
V
SK Clock Frequency
NMC93C06·NMC93C66
NMC93C06E·NMC93C66E
tSKH
SKHighTime
NMC93C06·NMC93C66
NMC93C06E·NMC93C66E
(Note 2)
(Note 3)
500
500
ns
tsKL
SKLowTime
NMC93C06·NMC93C66
NMC93C06E·NMC93C66E
(Note 2)
(Note 3)
250
500
ns
tes
MinimumCS
Low Time
NMC93C06·NMC93C66
NMC93C06E·NMC93C66E
(Note 4)
(Note 5)
250
500
ns
tess
CS Setup Time
NMC93C06·NMC93C66
NMC93C06E·NMC93C66E
Relative to SK
50
100
ns
tpRES
PRE Setup Time
NMC93CS06·NMC93CS66
NMC93CS06E·NMC93CS66E
Relative to SK
50
100
ns
tpES
PE Setup Time
NMC93CS06·NMC93CS66
NMC93CS06E·NMC93CS66E
Relative to SK
50
100
ns
2·85
1
0.5
~
Z
o
en
~
V
fSK
0
0
en
V
V
V
Vee - 0.2
o
en
s:
0.4
2.4
Z
s:
MHz
•
DC and AC Electrical Characteristics Vcc = 3.0V to 5.5V (unless otherwise specified) (Continued)
Conditions
Min
Relative to SK
100
200
ns
Relative to SK
0
ns
NMC93C06-NMC93C66
NMC93C06E-NMC93C66E
Relative to SK
100
200
ns
Output Delay to "1"
NMC93C06-NMC93C66
NMC93C06E-NMC93C66E
ACTest
500
1000
ns
tpDO
Output Delay to "0"
NMC93C06-NMC93C66
NMC93C06E-NMC93C66E
ACTest
500
1000
ns
tsv
CS to Status Valid
NMC93C06-NMC93C66
NMC93C06E-NMC93C66E
ACTest
500
1000
ns
tDF
CSto DO in
TRI-STATE®
NMC93C06-NMC93C66
NMC93C06E-NMC93C66E
ACTest
CS = VIL
100
200
ns
twp
Write Cycle Time
15
ms
Symbol
Parameter
tOIS
01 Setup Time
tcSH
CSHoldTime
tOIH
01 Hold Time
tp01
Part Number
NMC93C06-NMC93C66
NMC93C06E-NMC93C66E
Endurance
Number of Data
Changes per Bit
Typical
100,000
Max
Units
Cycles
Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Nota 2: The SK frequency specification for Commercial parts specifies a minimum SK clock period of 2 p.s. therefore in an SK clock cycle isKH + isKL must be
greater than or equal to 2 p.s. For example if isKL = 250 ns then the minimum tSKH = 1750 ns in order to meet the SK frequency specification.
Note 3: The SK frequency specification for Extended Temperature parts specHies a minimum SK clock period of 2 fIos, therefore in an SK clock cycle isKH + tSKL
must be greater than or equal to 2 fIos. For example. if the isKL = 500 ns then the minimum isKH = 1.5 fIos in order to meet the SK frequency specification.
Note 4: For Commercial parts CS must be broughllow for a minimum of 250 ns (lcsl between consecutive instruction cycles.
Nota 5: For Extended Temperature parts CS must be brought low for a minimum of 500 ns (Ics) between consecutive instruction cycles.
Note 6: This parameter is periodically sampled and not 100% tested.
Capacitance (Note 6)
TA
AC Test Conditions
= 25°C f = 1 MHz
Symbol
Max
Units
COUT
Output Capacitance
Test
Typ
5
pF
CIN
Input Capacitance
5
pF
1 TTL Gate and CL = 100 pF
Output Load
0.4Vto 2.4V
Input Pulse Levels
Timing Measurement Reference Level
Wand2V
Input
0.8Vand2V
Output
2-86
z
3:
Functional Description
The NMC93C06/C46/C56/C66 have 7 instructions as described below. Note that the MSB of any instruction is a "1"
and is viewed as a start bit in the interface sequence. The
next 10-bits carry the op code and the 8-bit address for
register selection.
Read (READ):
o
CD
Write (WRITE):
CAl
The Write (WRITE) instruction is followed by 16 bits of data
to be written into the specified address. After the last bit of
data is put on the data-in (DI) pin, CS must be brought low
before the next rising edge of the SK clock. This falling edge
of CS initiates the self-timed programming cycle. The DO
pin indicates the READY/BUSY status of the chip if CS is
brought high after a minimum of 250 ns (tes). DO = logical
o indicates that programming is still in progress. DO = logical 1 indicates that the register at the address specified in
the instruction has been written with the data pattern specified in the instruction and the part is ready for another instruction.
Erase All (ERAL):
The Read (READ) instruction outputs serial data on the DO
pin. After a READ instruction is received, the instruction and
address are decoded, followed by data transfer from the
selected memory register into a 16-bit serial-out shift register. A dummy bit (logical 0) precedes the 16-bit data output
string. Output data changes are initiated by a low to high
transition of the SK clock.
Erase/Write Enable (EWEN):
The ERAL instruction will simultaneously program all registers in the memory array and set each bit to the logical '1'
state. The Erase All cycle is identical to the ERASE cycle
except for the different op-code. As in the ERASE mode,
the DO pin indicates the READY/BUSY status of the chip if
CS is brought high after a minimum of 250 ns (tes). The
ERAL instruction is valid only at Vee = 5.0V ± 10%.
Write All (WRAL):
When Vee is applied to the part, it powers up in the Erase/
Write Disable (EWDS) state. Therefore, all programming
modes must be preceded by an Erase/Write Enable
(EWEN) instruction. Once an Erase/Write Enable instruction is executed, programming remains enabled until an
Erase/Write Disable (EWDS) instruction is executed or Vee
is removed from the part.
Erase (ERASE):
The ERASE instruction will program all bits in the specified
register to the logical '1' state. CS is brought low following
the loading of the last address bit. This falling edge of the
CS pin initiates the self-timed programming cycle.
The (WRAL) instruction will simultaneously program all registers with the data pattern specified in the instruction. As in
the WRITE mode, the DO pin indicates the READY/BUSY
status of the chip if CS is brought high after a minimum of
250 ns (tes). The WRAL instruction is valid only at
Vee = 5.0V ±10%.
Erase/Write Disable (EWDS):
To protect against accidental data disturb, the Erase/Write
Disable (EWDS) instruction disables all programming modes
and should follow all programming operations. Execution of
a READ instruction is independent of both the EWEN and
EWDS instructions.
The DO pin indicates the READY/BUSY status of the chip if
CS is brought high after a minimum of 250 ns (tes).
DO = logical '0' indicates that programming is still in progress. DO = logical '1' indicates that the register, at the
address specified in the instruction, has been erased, and
the part is ready for another instruction.
Instruction Set for the NMC93C06 and NMC93C46
Instruction
READ
S8
OpCode
Address
1
10
A5-AO
Reads data stored in memory, at specified address.
Write enable must precede all programming modes.
EWEN
1
00
11XXXX
ERASE
1
11
A5-AO
WRITE
1
01
A5-AO
ERAL
1
00
10XXXX
WRAL
1
00
01XXXX
EWDS
1
00
OOXXXX
Data
Comments
Erase register A5A4A3A2A1AO.
D15-DO
Writes register.
D15-DO
Writes all registers. Valid only at Vee
Erases all registers. Valid only at Vee
= 4.5V to 5.5V.
= 4.5V to 5.5V.
Disables all programming instructions.
Instruction Set for the NMC93C56 and NMC93C66
Instruction
S8
OpCode
Address
1
10
A7-AO
Reads data stored in memory, at specified address.
EWEN
1
00
11XXXXXX
Write enable must precede all programming modes.
ERASE
1
11
A7-AO
READ
Data
Comments
Erase register A 7A6A5A4A3A2A tAO.
Erases all registers. Valid only at Vee
=
4.5V to 5.5V.
ERAL
1
00
10XXXXXX
WRITE
1
01
A7-AO
D15-DO
Writes register if address is unprotected.
WRAL
1
00
01XXXXXX
D15-DO
Writes all registers. Valid only when Protect Register
is cleared. Valid only at Vee = 4.5V to 5.5V.
EWDS
1
00
OOXXXXXX
Disables all programming instructions.
2-87
oo
~
CAl
........
z
3:
o
CD
CAl
o
.j:>,
~
CAl
......
z
3:
o
en
~
CAl
......
z
3:
o
C')
C')
><
CAl
C')
><
CD
CD
Timing Diagrams
0
Synchronous Data Timing
:::liE
Z
......
C')
VIH
CS Vil
><
CD
It)
tess
0
VIH
SK Vil
:::liE
Z
......
C')
tOIS
><
VIH
CD
"01'
01
0C')
Vil
CD
0
VOH
DO (REAO)VOl
:::liE
Z
......
C')
><
CD
CI
VOH
DO (PROGRAt.l) VOL
tsv
0C')
CD
0
Tl/D/l0045-4
'This is the minimum SK period (Note 2).
:::liE
Z
READ:
CsJ
11
11
DI~~~
____
'v:Y
~l'I~__________________________
00--------------------------TLlDIt 0045-5
'Address bits As and A4 become "don't care" for NMC93C06.
'Address bit A7 becomes a "don't care" for NMC93C56.
EWEN:
CSJ
DI
TL/D/l0045-6
'The NMC93C56 and NMC93C66 require a minimum of 11 clocks. The NMC93C06 and NMC93C46 require a minimum of 9 clock cycles.
2-88
Timing Diagrams (Continued)
EWDS:
csJ
II
o
01
o
o
o
TL/D/l0045-7
'The NMC93C56 and NMC93C66 require a minimum of 11 clocks. The NMC93C06 and NMC93C46 require a minimum of 9 clock cycles.
WRITE:
___________
DI~~XDD\
lZ
00
II
b ~t
READY
twp=:j
'TL/D/l0045-B
• Address bit As and
A.. become "don't care" for NMC93C06.
'Address bit A7 becomes a "don't care" for NMC93C56.
WRAL:t
csJ
II
lJ1JU1J1JUUL
01
o
o
o
OO--------------------------------~l'~l----------~~----_+--~
TLlD/l0045-9
'The NMC93C56 and NMC93C66 require a minimum of 11 clocks. The NMC93C06 and NMC93C46 require a minimum of 9 clock cycles.
tValid only at Vee = 4.5V to 5.5V.
2-89
~ r-------~------------------------------------------------------------------_,
~
Timing Diagrams (Continued)
:i
z
.....
~
~
:iii
z
.....
~
o"="
m
o
:iii
z
.....
ERASE:
SK
cs/r--------------------~S§~--~
CHECK STATUS
STANDBY
..~~.....~~~~..........~.....~.....--
DI
~
~
TLlD/IOO45-10
CD
CI
o
~
ERAL:t
m
o
:iii
z
SK
CSJ
DI
~....O_0.J/1\
olmmmM.,
TRI-STATE
DO----------------------------~~--~~e~
TL/D/l0045-11
tVaiid only at Vee
= 4.5V to 5.5V.
2-90
z
i!i:
PRELIMINARY o
CD
~National
~
U1
Semiconductor
o
.....
N
NMC95C12 1024-Bit CMOS EEPROM with DIP Switches
General Description
Features
The NMC95C12 is a 1024-bit, CMOS EEPROM with B programmable outputs that can be used as DIP switches. The
1024 bits of memory are divided into 64 registers of 16 bits
each and each register can be individually accessed. Registers 61-63 are dedicated to storing the switch settings.
In addition to the 1024 bits of EEPROM memory, the
NMC95C12 contains eight individually programmable outputs which can be used as DIP switches. Each output may
be programmed to provide either a High or Low level. These
outputs may also be programmed to form four individual
pairs of SPST switches.
The switch configuration information is obtained from a non
volatile register whenever power is first applied to the device. This ensures the switches will always have a user determined state upon power-up.
The NMC95C12 is designed to meet applications requiring
40,000 write cycles per register and at least 10 year data
retention.
• 1024 bits of CMOS EEPROM memory
• B DIP switch positions or 4 SPST switch positions
• 4 mA (max) operating current, 50 p.A (max) standby
current
• Software write protection
• Serial I/O interface fully MICROWIRE compatible
• Single +5V ±10% operation
• 14-pin DIP or SO package availability
• 40,000 write operations
• 10 year data retention
• Reliable floating gate technology
• Sequential register read
• Self-timed write cycle
• Erase cycles not necessary
• Compatible with COPSTM microcontrollers
Block Diagram
Address •
PROGRAMMING
It
POWER UP
CIRCUITS
.....------., 9
E2 PROM
61WORDSx16BITS
60
Al
Bl
INITIAL SWITCH
SETTINGS
A2
B2
A3
B3
01
DO
S K - - -.....
A4
cs----.....I
B4
TLlD/9632-1
FIGURE 1. Block Diagram
2-91
Absolute Maximum Ratings
Operating Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
6.5V
Supply Voltage Vcc
-0.3 to +6.5V
Voltage at Any Pin
Storage Temperature Range
-65'C to + 150'C
Maximum Power Dissipation @25'C
500mW
Lead Temperature
·(Soldering, 10 seconds)
300'C
ESD Rating
2000V
DC Electrical Characteristics Vcc =
Symbol
Ambient Operating Temperature
NMC95C12
NMC95C12E
NMC95C12M·
Power Supply Voltage
5V ±10%
Parameter
VIH,SK
Cs
Standby Current
TIL Input Levels on Switches
Cs
=
OV
IlL
Input Leakage
VIN
=
loL
Output Leakage
VOUT
VIL
Input Low Voltage
ICC1
ICC2
Operating Current TIL Input Levels
Cs
ICC3
Standby Current
CMOS Input Levels on Switches
ICC4
Input High Voltage
Output Low Voltage
VOH
Output High Voltage
RON
Switch On Resistance
ROFF
Switch Off Resistance
Vs
Maximum Voltage Allowed
on any Switch Terminal
fSK
tSKH
tsKL
tcs
tess
Units
4
mA
Min
1 MHz
6
mA
50
p.A
800
p.A
OV
OV to VCC
-2.5
+2.5
p.A
=
-2.5
2.5
p.A
-0.1
0.8
V
2.0
Vcc + 1
V
0.4
V
200
0
OV to Vcc
= 2.1 mA
IOH = -400p.A
2.4
V
10
MO
Vcc + 1
V
5V ± 10% unless otherwise specified
Parameter
Part Number
SK Clock Frequency
NMC95C12
NMC95C12E
NMC95C12M
SKHighTime
VIH,SK
=
=
IOL
AC Electrical Characteristics Vee =
Symbol
Max
1 MHz
Conditions
=
=
=
Cs
VOL
4.5Vto 5.5V
'Contact factory for availability
Operating Current CMOS Input Levels
VIH
O'Cto +70'C
-40'Cto + 85'C
- 55'C to + 125'C
Conditions
Min
Max
Units
0
0
0
1
0.5
0.5
MHz
NMC95C12
NMC95C12E
NMC95C12M
(Note 2)
(Note 3)
(Note 3)
250
500
500
ns
NMC95C12
NMC95C12E
NMC95C12M
(Note 2)
(Note 3)
(Note 3)
250
500
500
ns
MinimumCS
Low Time
NMC95C12
NMC95C12E
NMC95C12M
(Note 4)
(Note 5)
(Note 5)
250
500
500
ns
CS Setup Time
NMC95C12
NMC95C12E
NMC95C12M
Relative to SK
50
100
100
ns
SKLowTime
2·92
z
AC Electrical Characteristics VCC = sv ± 10% unless otherwise specified (Continued)
Symbol
Parameter
01 Setup Time
tOIS
tCSH
CSHoldTime
tOIH
DI Hold Time
Output Delay to "0"
tpoo
CS to Status Valid
tsv
tOF
tlSWO
tswpoo
tswPO,
tsws
tSWH
Conditions
Min
Relative to SK
100
200
200
ns
Relative to SK
a
ns
Relative to SK
100
200
200
ns
NMC9SC12
NMC9SC12E
NMC9SC12M
Output Delay to "1 "
tpo,
Part Number
NMC9SC12
NMC9SC12E
NMC9SC12M
Max
sao
NMC9SC12
NMC9SC12E
NMC9SC12M
ACTest
1000
1000
NMC9SC12
NMC9SC12E
NMC9SC12M
ACTest
1000
1000
NMC9SC12
NMC9SC12E
NMC9SC12M
ACTest
ns
sao
ns
SOO
1000
1000
ns
ns
CSto DOin
TRI-STATE®
NMC9SC12
NMC9SC12E
NMC9SC12M
CS = VIL
ACTest
100
200
200
Switch Delay
from Switch Input
NMC9SC12
NMC9SC12E
NMC9SC12M
ACTest
2S0
SOO
Switch Delay
to 0 from
Config. Change
NMC9SC12
NMC9SC12E
NMC9SC12M
ACTest
Switch Delay
to 1 from
Config. Change
NMC9SC12
NMC9SC12E
NMC9SC12M
ACTest
A l-A4, Bl-B4
Setup Time
NMC9SC12
NMC9SC12E
NMC9SC12M
100
200
200
ns
Al-A4, Bl-B4
Hold Time
NMC9SC12
NMC9SC12E
NMC9SC12M
100
200
200
ns
ns
sao
SOO
1000
1000
ns
sao
1000
1000
10
ns
ms
Endurance
Number of Data
Typical
Cycles
Changes per Bit
40,000
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature
Range". the device should not be oparated at these limits. The table of "Electrical Characteristics" provides actual operating limits.
Note 2: The SK frequency specification for Commercial parts specifies a minimum SK clock period of 1 ,",s, therefore in an SK clock cycle tsKH + tsKL must
be greater than or equal to 1 ,",S. For exemple if tsKL = 2S0 ns then the minimum tsKH = 7S0 ns in order to meet the SK frequency specification.
Note 3: The SK frequency specification for Extended Temperature and Military parts specifies a minimum SK clock period of 2 ,",S, therefore in an SK clock
cycle tsKH + tsKL must be greater than or equal to 2 ,",S. For example, if tsKL = SOO ns then the minimum tsKH = 1.S ,",S in order to meet the SK frequency
specification.
Note 4: For Commercial paris CS must be brought low for a minimum of 2S0 ns (les) between consecutive instruction cycles.
Note 5: For Extended Temperature and Military paris CS must be brought low for a minimum of 500 ns (leS) between consecutive instruction cycles.
Note 6: This parameter is periodically sampled and not 100% tested.
Note 7: Power dissipation temperature derating-plastic "N" package: -12 mW/'C from +6S'C to +BS'C.
Capacitance
TA
=
2SOC,f
Symbol
=
AC Test Conditions
(Note 6)
1 MHz
Test
Typ
Max
Units
COUT
Output Capacitance
S
pF
CIN
Input Capacitance
S
pF
Output Load
Input Pulse Levels
1 TTL Gate and CL = 100 pF
O.4Vto 2.4V
Timing Measurement Reference Level
Input
Output
2-93
....
(')
I\)
Write Cycle Time
twp
Units
3:
(')
co
(It
1Vand2V
0.8V and 2V
....
o
N
It)
Connection Diagrams
aI
o
:::&!
SO Package
z
CS- 1
'-../
Dual-In-Line Package
SK- 2
14 '-Vee
13 -A4
01- 3
12 !-B4
00- 4
11 r-A3
00- 4
11 -A3
B1- 5
10 r-B3
B1- 5
10 r-B3
SK- 2
01- 3
CS- 1
'-../
14 r-Vce
13 r-A4
12 r-B4
A1- 6
9r-A2
A1- 6
GNO- 7
8 r-B2
GNO- 7
01
DO
A1-A4
81-84
Chip Select
Serial Clock
Serial Data In
Serial Data Out
Switch Terminals
Switch Terminals
9-A2
8
~B2
TL/D/9632-2
TL/D/9632-3
Top View
Order Number NMC95C12M,
NMC95C12EM and NMC95C12MM
See NS Package M14A
Pin Names
CS
SK
Top View
Order Number NMC95C12N,
NMC95C12EN and NMC95C12MN
See NS Package N14A
Pin Descriptions
Pin
Name
Description
CS
Chip Select, Input-This input must be high while communicating with the NMC95C12. When this
input is LOW, the chip is powered down into the standby mode. It should be noted that the CS
does not control the A1 through A4 and 81 through 84 outputs and hence has no effect on them.
The CS input must be made LOW after completing an instruction to prepare the control logic to
accept the next instruction. If the CS input becomes LOW prematurely, the operation in progress
is aborted. If programming the E2 memory is in progress and the CS goes LOW, the programming
is not aborted but will proceed to its normal completion.
SK
Serial Clock, Input-This input is used for clocking the serial 110. The CS input must be high for
clocking to have any effect. Information presented on the 01 input will be shifted into the device
on the LOW to HIGH transition of the clock. Information from the device will be available on the
DO output serially, in response to the LOW to HIGH transition of the clock.
01
Serial Data In, Input-All information needed for the operation of the device is entered serially
from this input. HIGH represents logic '1' and LOW represents logic '0'. The entry order is most
significant bit first and least significant bit last.
DO
Serial Data Out, Output, 3-state--When data is read, data from the addressed location will be
available on this output serially, in sync with the LOW to HIGH transitions on the SK input.
Normally the DO pin is in high impedance state. During a read instruction, when the last bit of the
address is shifted in, the DO will go LOW indicating that data will follow. The data will follow in
response to the clock transitions. The data will come out most significant bit first and least
significant bit last. During E2 programming operations, this output is also used as the status
indicator. During programming operations, LOW indicates 8usy (programming in progress) and
HIGH indicates Ready. The DO output will be in the high impedance state if the CS input is LOW
unconditionally.
A1-A4
81-84
Switch Terminals--These pins provide the simulated DIP switch features and hence are called
terminals. The behavior of these pins is determined by the settings in the Switch Configuration
Register and are independent of the CS input.
Vee
+ 5V Power Supply.
GND
Ground.
2-94
z
o<0
U'I
o......
:!:
Functional Description
Figure 1 is a block diagram of the NMC95C12. It consists of
a 62-word X 16-bit E2PROM array, a lS-bit Switch Configuration Register (SCR), a lS-bit Switch Readback Register
(SRR), four identical blocks of switch logic, programming
and power-up circuits and the necessary control logic. It
may be noted that only eight bit positions of the SRR are
used in the NMC95C12.
ADDRESS SPACE
Registers a-so of the E2PROM are available to the user as
general purpose non-volatile memory. Data may be read or
programmed into this memory using the appropriate instructions. Address location 61 is an E2 location which also can
be read or programmed like any other E2 location. However,
address 61 is used in the NMC95C12 to provide the initial
switch configuration information automatically on power-up.
The SCR is located at address 62. The SCR is not an E2
location and hence is volatile. It does not have endurance
limits or programming time requirements associated with it,
allowing the switches to be reconfigured an unlimited number of times.
The SCR is automatically loaded from address 61 on powerup. The SCR controls the switch logic and hence the behavior of the terminals A1 through A4 and B1 through B4.
Located at address 63 is the Switch Readback Register
(SRR). This is a read only register.
TABLE I. Switch Configurations
MODE·
Z
Y
X
W
SWITCH CONfiGURATION
COMMENTS
0
0
0
0
0
~A~B
A=O,B=O
1
0
0
0
1
~A
Ec>-oB
A=O, B=l
2
0
0
1
0
Ec>-oA
~B
A=l ,B=O
3
0
0
1
1
Ec>-oA
Ec>-oB
A=l , B= 1
4
0
1
0
0
~A
A=O , B=Tris!a!e
OB
0
5
0
1
0
1
I I> ~:
A=B
6
0
1
1
0
I
t>o-::
A=B
7
0
1
1
1
8
1
0
0
0
9
1
0
D
1
10
1
0
1
0
Ec>-oA
0
OB
0
OA
A=l ,B=Tris!ate
~B
A=Tristate , B=O
~:
B=A
I ~:
B=A
I I>
OA
0
11
1
0
1
1
12
1
1
D
X
13
1
1
1
X
~B
A = Tristate , B=l
'+r'
+-+
A
B
-
-
·Modes 0 thru 11 are logic level functions. Modes 12 and 13 are Analog switch functions.
2-95
Analog Switch
Open
Analog Switch
Closed
TL/D/9632-6
N
C'I
.,...
o
\I)
Q)
Functional Description
(Continued)
o
SWITCH CONFIGURATIONS
z
The 16-bit SCR format is shown in Figure 2. It consists of
four 4-bit fields. Each field controls its corresponding switch
control logic. The individual bits in each field are labelled W,
X, Y, and Z. Table I shows the relationship between these
bit values and the resulting behavior of the terminals. It
should be remembered that the CS input has no effect on
the behavior of the terminals.
:5
The bit assignments and conceptual function of the SRR is
shown in Figure 3. As shown, only bits lS thru 8 are used,
and bits 7 thru 0 are always read as logical O. The SRR is a
Read-Only register and if it is written, the device will not
perform a write or generate a Ready/Busy status. The SRR
is not implemented in EEPROM, allowing an infinite number
of cycles in the register.
INSTRUCTION SET
SWITCH READBACK REGISTER
The NMC9SC12 instruction set contains five instructions,
and each instruction is nine bits long. One SK clock cycle is
necessary, after CS equals logical "1 ", before an instruction
can be loaded. The first bit of the instruction is the start bit
(SB) and is always a logical "1", followed by the op code (2
bits) and the address field (6 bits). The WRITE and WRALL
instructions are followed by sixteen bits of data (D1S-DO)
which is written into the memory. Table II is a list of the
instructions and their format.
The SRR allows the current logic level present at the switch
terminals to be read back via the Microwire bus. The SRR is
loaded by the rising edge of SK immediately after the last
instruction bit is clocked in (The same clock edge that loads
AO). The SRR is loaded on this clock edge only when register 63 (Switch Readback Register) is being read. In the case
of switch mode 13 (Analog switch mode), the SRR will not
report the actual levels present at the terminals due to this
mode being analog levels. In mode 13, bits lS-8 of the
SRR will be all O's to indicate a closed analog switch. This is
done to avoid ambiguous logic levels which could exist
when the device is used in the analog switch mode.
15 14 13 12 11 10
9
7
8
6
5
4
3
2
0
1
IZIYIXIWIZIYIXIWIZIYIXIWIZIYIXIWI
.
,
SWITCH 4
,
.
,
,
SWITCH 3
.
,
SWITCH 2
SWITCH 1
TLlD/9632-4
FIGURE 2. Switch Configuration Register (SCR)
15 14 13 12 11 10
9
8
I I I I I
7
5
6
4
3
2
1
0
I 0 I 0 1010 I 0101
. .lffiMl~IM
11
A
1010
R
ENABLE 3
~.
ENABLE 2 A4 B4 A3 B3
ENABLE 1
TL/D/9632-5
FIGURE 3. Switch Readback Register (SRR)
TABLE II. NMC95C12 Instructions
SB
OpCode
Address
READ
1
10
AS-AO
WEN
1
00
llXXXX
WRITE
1
01
AS-AO
D1S-DO
Writes register.
WRALL
1
00
01XXXX
D1S-DO
Writes all registers.
WDS
1
00
OOXXXX
Instruction
Data
Comments
Reads data stored in memory, starting at specified address.
Write enable must precede all programming modes.
Disables all programming instructions.
2-96
Functional Description (Continued)
WDS (Write Disable): When this instruction is issued, all
subsequent writing into the NMC95C12 is locked out. Any
attempt to write into a locked device is ignored. The
NMC95C12 powers up in the locked state. The WEN is the
only instruction that unlocks the device. The write disable
operation has no effect on read operations. Thus reading
will occur normally even from a locked device.
WRALL (Write All): When this instruction is executed, the
NMC95C12 bulk-programs the same 16-bit data pattern into
all of its E2 memory locations (address 0 through 61). The
SCR is unaffected since it is not an E2 location. The data
pattern must follow immediately after the last bit of this instruction. The chip enters into the self-timed program mode
after CS is brought low, before the next rising edge of SK.
WEN (Write Enable): This instruction is used to unlock the
write circuits. The circuits will remain unlocked until the
WDS instruction locks them. The NMC95C12 powers up in
the locked state and hence WEN must be executed prior to
any programming instructions.
WRITE (Write/Program): This instruction writes a 16-bit
data word into the address location specified by the Ao-A5
bits of the instruction. The 16 data bits must follow the last
bit of the instruction. After loading the WRITE instruction
and the 16-bit data, the chip enters into the self-timed program mode when CS is brought low before the next rising
edge of the SK clock. If the addressed location is the SCR,
then the chip does not enter into the self-timed E2 programming mode (the SCR is not an E2 location) but loads the
switch configuration data into the SCR. The WRITE instruction can only be aborted by deselecting the chip (CS LOW)
before entering all the instruction bits. The NMC95C12 does
not require erasing prior to writing.
READ (Read): This instruction reads the data from the addressed location. As before, the instruction also contains
the address. The data will come out serially on the DO output on the rising edge of the clock. A logical '0' precedes
the 16-bit data (dummy bit).
The NMC95C12 has a convenient feature called sequential
register read. Normally, the CS input is made LOW after the
last data bit is shifted out. However, if the CS input is left
HIGH and clocking continues, data from the next address
location will be delivered on the DO pin. This sequential read
can continue indefinitely whereby the address is automatically incremented after delivering 16 bits of data. It should
be noted that in the sequential register read mode, address
wrap-around will occur.
During a sequential register read there will be a dummy bit
preceding the first word read, after which, the bit stream will
be continuous without any dummy bits separating the data
words.
Ready IBusy Indication
Programming an E2 memory takes several milliseconds. Unlike some devices which require the user to keep track of
the elapsed time to ensure completion of the programming
cycle, the NMC95C12 contains an on-chip timer. The timer
starts when the CS input goes LOW after the last data bit is
entered. After entering a programming cycle (CS forced
LOW), the timer status may be observed by forcing the CS
input back HIGH. The timer status is available on the DO pin
if the CS input is forced HIGH within one ms of starting the
programming cycle. LOW on the DO pin indicates that the
programming is still in progress while HIGH indicates the
device is READY for the next instruction. It should be noted
that if the CS input is made HIGH for status observation, it
must be made LOW when READY is indicated before loading the next instruction.
Timing Diagrams
Synchronous Data Timing
CS
.... tessI-
-l tCSH I-
r--isKH
SK
....
I
tSKL-
tOIS I-tOI~
DI
J(
AO
....
-l tOP1 t:
...... tor I-
_tsvl:
DO (PROGRAM)
I
AI,BI _ _ _ _ _ _
... tor l-
\.
I
DO (READ)
tpoo
STATUS VALID
~X,.__ttswsJ tSWHt_ _ _ _~----_
t""l
BI,AI
1::~____
TL/D/9632-7
2-97
z
oco
==
U1
o
......
N
WEN:
csJ
\~------------------------
SK
DI~..::D_....::.o..J/l
1
~~~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
TLlD/9632-9
csJ
WDS:
\~-------------------------
SK
m~~o__~~~~o~~~~~~~Xh~___________________________
TLlD/9632-10
'The memory automatically cycles 10 the next register.
2-98
z
5:
Timing Diagrams (Continued)
oco
U'I
o....
InstructIon Sequence (Continued)
WRITE:
I\)
cs
SK
0
_ _- - 1
DO ~HI~-Z~------------------------------------_t------~~~B~U~~~__Ay-~R~~WYY--~------TL/D/9632-11
CSJ
WRITE SCR:
\
SK
DI~l
1 \
0
~~
______________________
DO HI-Z
TUD/9632-12
WRALL:
cs
SK
DO
01 _ _- - 1
DO ~H~~Z~----------------------------_____________________r------~~B~US~Y~
TUD/9632-13
2-99
....
II)
m
cr: Protecting Data in Serial
National Semiconductor
Application Brief 15
Paul Lubeck
EEPROMs
National offers a broad line of serial interface EEPROMs
which share a common set of features:
• Low cost
• Single supply in all modes (+5V ± 10%)
• TIL compatible interface
• MICROWIRETM compatible interface
• Read-Only mode or read-write mode
This Application Brief will address protecting data in any of
National's Serial Interface EEPROMs by using read-only
mode.
Whereas EEPROM is non-volatile and does not require Vee
to retain data, the problem exists that stored data can be
destroyed during power transitions. This is due to either uncontrolled interface signals during power transitions or noise
on the power supply lines. There are various hardware design considerations which can help eliminate the problem
although the simplest most effective method may be the
following programming method.
All National Serial EEPROMs, when initially powered up are
in the Program Disable Mode*. In this mode it will abort any
requested Erase or Write cycles. Prior to Erasing or Writing
it is necessary to place the device in the Program Enable
Modet. Following plaCing the device in the Program Enable
Mode, Erase and Write will remain enabled until either executing the Disable instruction or removing Vee. Having Vee
unexpectedly removed often results in uncontrolled interface signals which could result in the EEPROM interpreting
a programming instruction causing data to be destroyed.
Upon power up the EEPROM will automatically enter the
Program Disable Mode. Subsequently the deSign should incorporate the following to achieve protection of stored data.
1) The device powers up in the read-only mode. However,
as a backup, the EWDS instruction should be executed
as soon as possible after Vee to the EEPROM Is powered up to ensure that it is in the read-only mode.
2) Immediately preceding a programming instruction
(ERASE, WRITE, ERAL or WRAL), the EWEN instruction
should be executed to enable the device for programming; the EWDS instruction should be executed immediately following the programming instruction to return
'Ewes or wes, depending on exact device.
tEWEN or WEN, depending on exact device.
SK
EWEN
EWDS
II
csJ
I~",--~
L STANDBY
TLlD/7085-1
FIGURE 1. EWEN, EWDS Instruction Timing
MAIN POWER SUPPLY
4.5V.5.5V
vee
r
r
lL-_____
L
5.5V " Vee" 4.5V
MAINTAINED ON CAPACITOR
-IL
INSTRUcnDN.JEWiiiL~~
(ERASE, WRITE,
ERAL DR WRAL}
TL/D17085-2
'EweS must be executed before Vee drops below 4.5V to prevent accidental data loss during subsequent power down andlor power up transients.
FIGURE 2. Typical Instruction Flow for Maximum Data Protection
2-100
the device to the read-only mode and protect the stored
data from accidental disturb during subsequent power
transients or noise.
3) Special care must be taken in designs in which programming instructions are initiated to store data in the EEPROM after the main power supply has gone down. This is
usually accomplished by maintaining Vee for the EEPROM and its controller on a capacitor for a sufficient
amount of time (approximately 50 ms, depending on the
clock rate) to complete these operations. This capacitor
must be large enough to maintain Vee between 4.5 and
5.5 volts for the total duration of the store operation, INCLUDING the execution of the EWDS instruction immediately following the last programming instruction. FAilURE TO EXECUTE THE LAST EWDS INSTRUCTION
BEFORE Vee DROPS BELOW 4.5 VOLTS MAY CAUSE
INADVERTENT DATA DISTURB DURING SUBSEQUENT POWER DOWN AND/OR POWER UP TRANSIENTS.
•
2-101
.... r--------------------------------------------------------------------------------,
National Semiconductor
co
~ Electronic Compass
Application Brief 18
Doug Zrebski
Calibration Made Easy With
E2 Memory, NMC9306
When a compass is first installed in a vehicle, or when new
equipment, such as car speakers, are added to a vehicle
with a compass, the compass must be compensated for
stray magnetic fields. With a magnetic compass, it must be
pOinted towards magnetic north and then adjusted. This
procedure is repeated at all four main points of the compass
until the compass is calibrated. This procedure is lengthy
and also requires another calibrated compass to point the
vehicle in the correct direction.
The block diagram illustrates an electronic compass that,
with the aide of an E2 memory, makes adjusting a compass
as easy as pushing a button, and also eliminates the need
for another compass. In addition it gives you the ability to
adjust for variation between magnetic and true north. This is
a major advantage because it is something that even the
most expensive magnetic compass cannot do.
The brain of the electronic compass is the COP421 microcontroller. There are two sense coils, one for north/south
and one for east/west. The output of each of the sense
amplifiers is an analog voltage which is fed into the A to D
converter. These voltages are read by the COP421 over the
microwire interface. From these voltages, the microcontroller determines the direction and displays the results
once again over the microwire interface. To compensate the
compass in a new environment the procedure is very simple. Start by pOinting the car in any direction and push the
switch. The CPU at this time will measure the voltage at the
sense amplifiers and store this information in the E2 memory over the microwire interface. Now the vehicle is turned
180', and the button is pushed again. The same procedure
will be followed internally. The compensation procedures
are now complete. During operation the CPU will compensate for stray fields by adding an analog voltage back into
the sense amplifiers. This value is stored in E2 memory and
not lost when the power is turned off, but is readjustable if
its environment is modified.
Compass variation is the difference between true and magnetic north. This variation differs all over the world and is
something that must be taken into consideration when navigating by compass. With the E2 memory device, a variance
can be programmed in for any given location. In California
this is approximately 17', in Michigan approximately I'.
Once again, this cannot be accomplished by a magnetiC
compass, and would have been impossible to accomplish
without an E2 memory device.
Electronic Compass Block Diagram
r+
NORTH/SOUTH
SENSE
COIL
NORTH/SOUTH
SENSE AMPLIFIER
LM324
l.......+
EAST/WEST
SENSE
COIL
EAST/WEST
SENSE AMPLIFIER
LM324
-
FLUX GATE
TOROID
DRIVER
rl
D/A
CONVERTER
~
I
I
I
A/D
CONVERTER
COP434
-
+--
II
MICROWIRE'· INTERFACE
IL
I I I
p.P
B---
E2 MEMORY
NMC9306
DISPLAY AND
DRIVERS
COP421
TL/D/B613-1
2-102
Automatic Low Cost
Thermostat
National Semiconductor
Application Brief 22
Kent Brooten
Ths application brief describes the use of the NMC9346
(64 x 16) serial EEPROM. With the advent of the inexpensive COPSTM family from National Semiconductor, heretofore "expensive" applications can now be realized inexpensively. Such an application is a low cost thermostat. Typical
features of such a device are:
1) Ability to interface to local and remote temperature sensors,
2) Ability to hold changeable settings,
The EEPROM (NMC9346) holds the presettable temperature ranges (high and low settings) by day of the week.
Since data is in EEPROM rather than in mask ROM, it can
be changed.
The LED display is multiplexed by the microcomputer. Depending on the type of display selected, external drivers
may be necessary.
3) Digital display of present temperature,
4) Inexpensive in high volume.
CIRCUIT DESCRIPTION
The basis of the thermostat is the COP410 microcontroller.
This, with the addition of 2 ADC0854 AID converters, an
NMC9346 EEPROM and some logic for LED display, comprise an extremely versatile, yet low cost, system. The
ADC0854 allows 4 channels of temperature sensors, 1 local
and 3 remote. Temperature sensors used are LM34 (for
readings in 'F) or LM35 (for readings in 'C).
While there are several possible choices for AID converters
that are MICROWIRETM compatible, the ADC0854 was chosen because of its "settability". By presetting the "cold"
temperature (i.e., when the cooling unit should come
on-say 80'F) all the microcomputer has to do is to multiplex the inputs and read the data in line. Similarly, the "hot"
AID can be preset to the temperature where the furnace
should come on (e.g., 60'F) and scanned in a like manner.
Since the microcomputer is also keeping time of day, selecting an AID with more "smarts" (as in the ADC0854) the
software can be kept manageable and an external real time
clock chip is not needed.
Input power is typically 24 VAC. USing a linear regulator
would cause too much heat to be dissipated, which would
upset the local temperature sensors. Thus, a switch mode
regulator must be used. Fortunately, National Semiconductor has provided a solution to the problem with the LM3578,
a switching regulator in an 8-pin mini-DIP, providing more
than enough current for the application, using only a minimum of external components.
SOFTWARE DESCRIPTION
Since a real time clock is implemented in software, all routines must execute the same number of cycles independent
of the input. Because of the flexibility of the COPS family
instruction set, this is not as difficult a problem as it first
appears. Since the EEPROM contains the settings that are
periodically sent to the AID converters, the COPS program
merely fetches data from one source and dumps it to another while monitoring the output. Even the SET and MODE
keys can be acted upon in a predictable manner IF the software designer carefully plans the program flow BEFORE
writing code.
Note: Also see App Brief 15.
2-103
»
OJ
.
I\)
I\)
24VAC
D
.1:::1:: I
SWITCHER
V
+5
HMC9346 GHD
CS ClK SO SI
Irnnl-l~;:J---4A~ lO
L...+WH_~B;
L1
~=:::t:~~=C~D=1 ~
L--_+WH_~E-;l4
L~===~~~:jF~l5
G
l6
.~D~IG~IT~SE~l~Ecr~O
_ _ _ _ _ _-t~
U.D~loo~sn~E:cr~I_ _~-:===l~
G3
62
A/C
.
{::::::::::!
+5
10mV/or
(IYP 1 or 4)
REMOTE r.7.~,
SENSOR
4991).
II
TL/O/8647-1
FIGURE 1
2-104
Designing with the
NMC9306/COP494 a
Versatile Simple to Use
E2PROM
National Semiconductor
Application Note 338
Masood Alavi
This application note outlines various methods of interfacing
an NMC9306/COP494 with the COPSTM family of microcontrollers and other microprocessors. Figures 1-6 show
pin connections involved in such interfaces. Figure 7 shows
how parallel data can be converted into aserial formatto beinputted to the NMC9306; as well as how serial data outputted
from an NMC9306 can be converted to a parallel-formal.
4.
The second part of the application note summarizes the key
points covering the critical electrical specifications to be
kept in mind when using the NMC9306/COP494.
The third part of the application note shows a list of various
applications that can use a NMC9306/COP494.
GENERIC CONSIDERATIONS
A typical application should meet the following generic
criteria:
1. Allow for no more than 10,000 E/W cycles for optimum
and reliable performance.
2. Allow for any number of read cycles.
3. Allow for an erase or write cycle that operates in the
10-30 ms range, and not in the tens or hundreds of ns
range as used in writing RAMs. (Read vs write speeds
are distinctly different by orders of magnitude in
E2PROM, not so in RAMs.)
No battery back-up required for data-retention, which is
fully non-volatile for at least 10 years at room-ambient.
SYSTEM CONSIDERATIONS
When the control processor is turned on and off, power
supply transitions between ground and operating voltage
may cause undesired pulses to occur on data, address and
control lines. By using WEEN and WEDS instructions in conjunction with a LO-HI transition on CS, accidental erasing or
writing into the memory is prevented.
The duty cycle in conjunction with the maximum frequency
translates into having a minimum Hi-time on the SK clock. If
the minimum SK clock high time is greater than 1 P.s, the
duty cycle is not a critical factor as long as the frequency
does not exceed the 250 kHz max. On the low side no limit
exists on the minimum frequency. This makes it superior to
the COP499 CMOS-RAM. The rise and fall times on the SK
clock can also be slow enough not to require termination up
to reasonable cable-lengths.
Since the device operates off of a simple 5V supply, the
signal levels on the inputs are non-critical and may be operated anywhere within the specified input range.
Yee
Yee
12k
Yee
0.05 ~F
NMC93061 00
COP494
01
COP420
100 pF
Yss
LO-L7. GO-G3. 01-03
TL/D/5286-1
FIGURE 1_ NMC9306/COP494 -
2-105
COP420 Interface
co
C')
C')
Vee
z•
c(
STANDARD
,.P
iiii
IN1
CE
IH2
SK
SI
CDP
IN3 PRDCESSOR DD
Wi!
INT
GO
IiESEf
D2
RESET
. D3
':'
TD DTHER
pPs
TUD/52B6-2
FIGURE 2. NMC9306 - Standard ",p Interface Via COP Processor
ADO ...l1lI
AD7 ....
AD13
NSCBOO'·
CPU
...
r
ADO
AD7
ifii
CE
RO
Wi!
Wii
ALE
10TIM
RESET OUT
PAD ...l1lI
PA7
NSCB10
RAM
110
TIMER
PDO
PB7
PCO
PC5
~
~
ALE
IDT/M
....
--'0.
PORTA
BDITS
~
~
PORT B
BBITS
I'"
6DITS
NMC9306
BANK
PORT C
TlMER·IN
TlMER.oUT
ilmf
TUD/52B6-3
PAD PA1 PA2-7 -
SK
)
DilDO
Common to all 9306's
6CS for 6- 9306's
• SK Is generated on port pins by bit-set and bit-clear operations In software. A symmetrical duty cycle Is not critical•
• CS Is set In software. To generate 10-30 ms wrltelerase the tlmerlcounter Is used. During wrlte/erase. SK may be turned off.
FIGURE 3. NSCBOOTM to NMC9306 Interface (also Valid for BOBS/BOBSA and B1S6)
2·106
»
z
I
Co)
Co)
,.....
CD
ADD
DECODE
'11
.... DO CE CID BIA
DO ....
AD ....
07 .... DATA BUS ,. D7
Mi .... B BITS
Mi
A7 .... PORT A 110 ,.
lORD
lORD
iiii .... PliO CTRL ,. RD
MK3BBD
MK3BB1
ZBO
ZBOI
TNT
CPU
PIO
lEI....
BO ....
B7 .... PDRT B 110 ,.
lEDINTERRUPT
CONTRDL LINES
AO-A15
...
....
NMC9306
BANK 1
(6)
NMC9306
BANK 2
(6)
(3)
TL/D/S286-4
Z80-P10
9306
AO
SK
A1
DilDO
A2-A7
CS1-CS6
)
Common to all 9306's (Bank 1)
• Only used If priority Interrupt daisy chain Is desired
" Identical connection for Port B
FIGURE 4. Z80 -
NMC9306 Interface Using Z80-PIO Chip
P17
P16
DATA
01
NMC9306
DD #1
CLOCK
SK CS1
P15
INSB04B
P14
P13
CS2
7413B
B DECODER
P12
P11
G1
CS9
EN
!--....,....-'CS2
"---'--CS9
TL/D/S286-S
• SK and 01 are generated by software. It should be noted that at 2.72I's/lnstructlon. The minimum SK period achievable will be 10.881's or 92 kHz, well
within the NMC9306 frequency range •
• DO may be brought out on a separate port pin If desired.
FIGURE 5. 48 Series ",p -
2-107
NMC93061nterface
co
C")
r-----------------------------------------------------------------------------------------~
C")
z•
ct
P20~,....---t
P20
P21HI-t--I P2l
P22HI-+-'" P22
P23HI-+......... P23
...
~:~
SK
LDI
DO
CSl
CS2
"(
INS8243
1/0
CS3-CS6 ...
EXPANDER P5
INS8048
,.
P6
CS7-CS10 ...
r
PROG HI-+-+-... PROG
00
iiii P24I-HHHE_ _ _'!!J+---1~
P7
cs
Wi
...
---
- ..
,.
CS
CO
GO
00
Cl
Gl
01
C2
G2
02
Al
AO
DO
07
IN58253
iOii
lOW
TIMER 1/0
TUD/52B6-6
Expander outputs
01 }
SK
Port 4
(COMMON)
CS1
CS2
Port 5-6
Port 7
CS3-CS10
00 (COMMON)
FIGURE 6. 8048 I/O Expansion
~f
000
NMC9308/COP494
vcc-
--+
r-
PIN a
DO
CS
SK
PIN 9
01
-+I
t
LS184
t
+-i
I
LSl65
t t
I
PARALLEL OUT
SERIAL IN
CLOCK
I
PARAUELIN
SERIAL OUT
TL/D/52B6-7
FIGURE 7. Converting Parallel Data into Serial Input for NMC9306/COP494
2-108
.
:J>
z
Co)
Co)
Q)
SK
01
cs
'--_ _ _1,_,,)-.,
00
Min
Max
tCYCLE 0
tDIS400
tD1H 400
tcss200
tCSHO
tpDO
tpD1
250kHz
ns
ns
ns
ns
21"s
21"s
TLl0/528S-8
FIGURE 8. NMC9306/COP494 Timing
THE NMC9306/COP494
5.
Extremely simple to interface with any p.P or hardware logic.
The device has six pins for the following functions:
Pin 1
CS'
HI enabled
Pin 2
SK
Serial Clock input
Pin3
01
Pin 4
00"
For instruction or data
input
For data read, TRI-STATE@
otherwise
Pin 5
GNO
Pin 8
Pins 6-7
VCC
No Connect
6.
7.
Oata shows a fairly constant E/W Programming behavior over temperature. In this sense E2PROMs supersede EPROMs which are restricted to room temperature programming.
8.
As shown in the timing diagrams, the start bit on 01
must be set by a ZERO - ONE transition following a CS
enable (ZERO - ONE), when executing any instruction.
ONE CS enable transition can only execute ONE instruction.
For5Vpower
No termination required
'Following an E/W instruction feed, CS is also toggled
low for 10 ms (typical) for an E/W operation. This internally turns the VPP generator on (HI-LO on CS) and off
(LO-HI on CS).
9.
In the read mode, following an instruction and data
train, the 01 can be a don't care, while the data is being
outputted i.e., for next 17 bits or clocks. The same is
true for other instructions after the instruction and data
has been fed in.
10. The data-out train starts with a dummy bit 0 and is
terminated by chip deselect. Any extra SK cycle after
16 bits is not essential. If CS is held on after all 16 of
the data bits have been outputted, the 00 will output
the state of 01 till another CS LO-HI transition starts a
new instruction cycle.
11. When a common line is used for 01 and 00, a probable
overlap occurs between the last bit on 01 and start bit
on DO.
12. After a read cycle, the CS must be brought low for
1 SK clock cycle before another instruction cycle can
start.
All commands, data in, and data out are shifted in/out on
rising edge of SK clock.
Write/erase is then done by pulSing CS low for 10 ms.
All instructions are initiated by a LO-HI transition on CS followed by a LO-HI transition on 01.
REAO - After read command is shifted in
01 becomes don't care and data can
be read out on data out, starting
with dummy bit zero.
"01 and 00 can be on a common line since 00 is TRISTATEO when unselected 00 is only on in the read
mode.
USING THE NMC9306/COP494
The following pOints are worth noting:
1. SK clock frequency should be in the 0-250 kHz range.
With most p.Ps this is easily achieved when implemented in software by bit-set and bit-clear instructions,
which take 4 instructions to execute a clock or a frequency in the 100 kHz range for standard p.P speeds.
Symmetrical duty cycle is irrelevant if SK HI time is ~
2 p.s.
2.
CS low period following an E/W instruction must not
exceed the 30 ms max. It should best be set at typical
or minimum spec of 10 ms. This is easily done by timer
or a software connect. The reason is that it minimizes
the 'on time' for the high Vpp internal voltage, and so
maximizes endurance. SK-clock during this period may
be turned off if desired.
3.
All E/W instructions must be preceded by EWEN and
should be followed by an EWOS. This is to secure the
stored data and avoid inadvertent erase or write.
A continuously 'on' SK clock does not hurt the stored
data. Proper sequencing of instructions and data on 01
is essential to proper operation.
4.
Stored data is fully non-volatile for a minimum of ten
years independent of VCC, which may be on or off.
Read cycles have no adverse effects on data retention.
Up to 10,000 E/W cycles/register are possible. Under
typical conditions, this number may actually approach
1 million. For applications requiring a large number of
cycles, redundant use of internal registers beyond
10,000 cycles is recommended.
WRITE - Write command shifted in followed by
data in (16 bits) then CS pulsed low
for 10 ms minimum.
2-109
co
~
Z•
CC
INSTRUCTION SET
Instruction
S8
Opcode
Address
READ
01
10xx
A3A2A1AO
WRITE
01
01xx
A3A2A1AO
Data
Comments
Read Register A3A2A1AO
D15-DO
Write Register A3A2A1AO
ERASE
01
11xx
A3A2A1AO
EWEN
01
0011
XXXX
Erase/Write Enable
Erase Register A3A2A1AO
EWDS
01
0000
XXXX
Erase/Write Disable
ERAL
01
0010
XXXX
Erase All Registers
WRAL
01
0001
XXXX
D15-DO
Write All Registers
NMC9306 has 7 instructions as shown. Note that MSB of any gIVen Instruction IS a " 1,I and 18 viewed as a start bit
in the interface sequence. The next B bits carry the op code and the 4-bit address for I of 16, 16-b" registers.
X is a don't care state.
The following is a list of various systems that could use a
NMC930S/COP494
A. Airline terminal
Alarm system
Analog switch network
Auto calibration system
Automobile odometer
Auto engine control
Avionics fire control
B. Bathroom scale
Blood analyzer
Bus interface
C. Cable T.V. tuner
CAD graphics
Calibration device
Calculator-user programmable
Camera system
Code identifier
Communications controller
Computer terminal
Control panel
Crystal oscillator
D. Data acquisition system
Data terminal
E. Electronic circuit breaker
Electronic DIP switch
Electronic potentiometer
Emissions analyzer
Encryption system
Energy management system
F. Flow computer
Frequency synthesizer
Fuel computer
G. Gas analyzer
Gasoline pump
H. Home energy management
Hotel lock
J. Industrial control
Instrumentation
J. Joulemeter
K. Keyboard -softkey
L. Laser machine tool
M. Machine control
Machine process control
Medical imaging
Memory bank selection
Message center control
Mobile telephone
N.
O.
P.
Q.
R.
S.
T.
U.
V.
W.
X.
Y.
Z.
2-110
Modem
Motion picture projector
Navigation receiver
Network system
Number comparison
Oilfield equipment
PABX
Patient monitoring
Plasma display driver
Postal scale
Process control
Programmable communications
Protocol converter
Quiescent current meter
Radio tuner
Radar dectector
Refinery controller
Repeater
Repertory dialer
Secure communications system
Self diagnostic test equipment
Sona-Bouy
Spectral scanner
Spectrum analyzer
Telecommunications switching system
Teleconferencing system
Telephone dialing system
T.V. tuner
Terminal
Test equipment
Test system
TouchTone dialers
Traffic signal controller
Ultrasound diagnostics
Utility telemetering
Video games
Video tape system
Voice/data phone switch
Winchester disk controller
X-ray machine
Xenon lamp system
YAG-Iaser controller
Zone/perimeter alarm
system
The NMC9346-An Amazing
Device
National Semiconductor
Application Note 423
Stacy Deming
Question: What has 8 pins, runs on 5V and can store any
one of more than 10300 unique bit patterns?
The 5-contact key is nice, but a 4-contact key is at least
20% better. Figure 2 shows how the addition of a retriggerable one-shot can achieve this reduction. This Circuit puts
some timing constraints on the serial clock Signal, but these
are easily met. The output pulse of the one-shot should remain high for a period that is slightly longer than one serial
clock cycle to prevent the NMC9346 from being reset. (The
falling edge of CS must occur before the rising edge of the
serial clock after the last bit of a write command is transmitted.)
Answer: The NMC9346-a 1024-bit serial EEPROM.
Surprised? It is easy to check:
2 1024 = number of possible combinations
2 10 = 103
21024"" (210)102 = (103)102 = 10306
10306 combinations are more than enough for any conceivable security application, serial number, or station 1.0. many
times over. Although the NMC9346 is a small part both
physically and in memory size, its capacity to store unique
codes is boundless.
Figure 1 shows the pin aSSignments and pin names for the
NMC9346. Pins 6 and 7 are not connected, leaving only 6
active pins on the device. The DO pin is not active while
data is being loaded through the DI pin. 01 and DO can be
tied together, creating a device that requires a 5-wire interface. This interface may be useful in security applications.
The EEPROM could be built into a module that could be
used as a "smart key" in electronic security systems. The
key would be read whenever it was inserted into a 5-contact
keyhole and access would be granted or denied as determined by the stored code. If only 256 bits of the EEPROM
were to be used to store the code, this would still provide
1077 possible combinations. The remainder of the memory
in the key could be used for data collection or to keep a
record of where the key had been. It should be noted that
ability to write data into the key allows the key to be immediately erased if it is misused.
Dual-In-Line Package
+5V
~
SHOT
SK/es
DI/OO
L
CS
SK
01
DO
GNO~
GNO
TL/0/8611-2
One·shot is retriggerable MM74HC123
FIGURE 2
A circuit for a 3-contact key is shown in Figure 3. A filter
capacitor, diode and one-shot have been added. Both oneshots are triggered whenever a pulse to ground occurs on
the power supply contact. The capacitor and diode provide
power to the NMC9346 and the one-shots during this brief
power interruption. An operational amplifier can be used as
the power source and can easily generate the required
waveform. Both the serial clock and chip select signals are
recovered from this waveform.
C S 0 8 Vee
SK
2
7
NC
01
3
6
NC
0045GNO
TlI0/8611-1
Pin Names
CS
SK
Chip Select
Serial Clock
Data Input
Data Output
+5V
Ground
No Connection
01
DO
Vee
GND
NC
•
FIGURE 1
2-111
C")
N
.....
Vee
Z•
CC
at the DI pin as a pulse-width-modulated signal. Command
and data signals may now be entered. Data is read from the
key by monitoring the power supply current. When the DO
pin is in TRI-STATE® or outputs a one, transistor T2 is
turned off. When DO outputs a zero, T2 is turned on and
current flows through R5. The value of R5 may be chosen to
create whatever current change is needed to detect the
state of DO. The current should be tested when the voltage
at pOint 1 is 16V. The resistor in this example will produce a
10 mA change.
.
SK
CS
CS
SK
DI
DI/DO
GND
00
GNO--------------------~~
Figure 5 shows a typical read sequence for the circuit
shown in Figure 4.
TL/D/8611-3
One·Shot A-Yz MM74HC123
Conclusion
One·Shot B-Yz MM74HC123
FIGURE 3
This application note describes a number of circuits that are
useful in security and data collection systems. These circuits should be considered only the beginning. It no longer
makes sense to install DIP switches to select access codes
in garage door openers, cordless and mobile phones, or any
other microcontroller-based system. "Smart keys" can be
used to gain access to databases and can be invalidated
over normal communication lines if they are abused. It boggles the mind to consider what can be done with so many
unique codes.
By adding more circuitry to the key, it is possible to achieve
a 2-contact interface. A circuit for this interface is shown in
Figure 4.
Commands and data are transmitted to the key by superimpOSing a pulse-width-modulated code on the power supply
contact. The voltage swings between BV and 16V at point 1.
A regulated 5V is supplied to the circuits in the key by a
local regulator. Resistors R1 and R2 form a divider to create
a 3V reference for the operational amplifier. R3 and R4 are
used as a divider that converts the BV to 16V signal at point
1 to a signal at pOint 2 that swings between 2V and 4V. The
output of the operational amplifier now follows the signal at
point 1 but swings from OV to 5V. This signal is used to
trigger the one-shots as in the 3-contact circuit, and appears
Note: The circuHs in this application note feature the NMC9346. The
NMC9306 is a pin-compalible part Ihal stores 256 bils. The NMC9346
was used because il has a self·liming write cycle and the NMC9306
does not. Additional circuitry is not required to use the NMC9306, but
an additional chip select signal must occur at the CS pin to tenninate
a wrilecycle.
Vee
01
DO
Ir----------------------------------~srS------~L
OV--'
t.ruu1.
trlrlJL
5V
5V
SK @
OV
DATA
-
12
9
13
7
15
~
17
INPUT BIT 7
TO ROM A7
16
OE
12
11
INPUT BIT 4
06
19
OUTPUT BIT 6
8
INPUT BIT 3
07
15
1
INPUT BIT 1
07
16
ClK
31
ClK
L....!!c
~
OE
TLID18644-2
FIGURE 2
2-119
•
.,......
CD
Z
c(
Common 1/0 Applications
of NMC9306/COP494 an~
NMC9346/COP495
Non-Volatile Serial
Access Memories
National Semiconductor
Application Note 481
NMC9306/COP494 and NMC9346/COP495 are serial
access non-volatile memories designed for a 4-wire
(MICROWIAETM) interface; Chip Select (CS) input, clock
(SK) input, serial data input (DI), and serial data output (DO).
Since DO is in TRI-STATE® while instructions, address and
data are being shifted into the chip on the DI signal line, DI
and DO can be tied together as a common I/O to further
simplify the interface. However, the following potentially
troublesome situations should be kept in mind and dealt
with according to these recommendations:
address is clocked into the chip by the rising edge of SK,
DO comes out of TAl-STATE and goes low (logical '0') as a
dummy bit to signal the start of the data output string (Figure
1). In a common 1/0 application, if AO is a logical '1' and is
still driving DI when the dummy bit becomes valid, a low
impedance path between the power supply and ground is
created through the DI driver and the on-Chip DO buffer
(Figure 2). If measures are taken· to minimize the short circuit current, e.g., by inserting a current limiting resistor between the DI driver and the chip (Figure 2), the part will
continue to work normally since AO is clocked onto the chip
before this potential disturb condition occurs.
NMC9306/COP494
While clocking in a READ instruction, approximately 500 ns
(typical) after the least significant bit (AO) of the register
SK
CS
s~s----------~ss~----~\~
.J
_______
READ
DI
DO
--F1\
0
1J///////JJ;YA3)Q~
~ ~~ ~
DURING THIS nME CONFLICT BETWEEN DI DEVICE AND
CHIP DO BUFFER CAN CAUSE A LOW IMPEDANCE PATH
BETWEEN SYSTEM vee AND GROUND WHEN AO=LOGlCAL 1
0
DIS
D14
~
TLlD/9213-1
FIGURE 1. Read Instruction in Common I/O Configuration
2-120
.""
~------------------------------------------------~~
CS
SK
Vee
:i(~ ~.~\......-t---1
DI
DRIVER
that programming is still in progress. DO = logical '1' signals the end of the programming cycle. This 'status check'
function of DO is cancelled (i.e., DO returns to TRI-STATE)
when a logical '1' on 01 is clocked into the chip by SK with
CS high. With separate input and output this is automatically
accomplished by the start bit of the next instruction (Figure
3).
NMC9306/COP494
OR
NMC9346/COP495
R. '>
Vee
z
....
c»
In a common I/O application, the following clocking sequence is recommended to avoid premature cancellation of
the 'ready' status and/or interference of the 'ready' status
with the serial input sequence for the next instruction (Figure 4):
.-.-DO
BUFFER
1) Inhibit the SK clock after clocking in the programming
instruction.
2) After acknowledging the 'ready' status, clock SK once
while the common I/O is still high to cancel the ready/
busy status function of DO.
3) Bring CS low for a minimum of 1 p.s (tcs) to clear the
instruction register before initiating the next instruction.
DO is now reset back to TRI-STATE, and the chip is ready
to accept the next instruction.
The chip may enter the 'ready' status mode under certain
conditions of Vee power-up. This occurs due to the Vee
power-up conditions setting the status mode logic on the
chip, and is not an indication of a spurious programming
cycle on Vee power-up. The following clocking sequence is
recommended to ensure cancellation of this status signal
after Vee power-up (Figure 5):
1) Bring CS high.
• POSSIBLE LOCATIONS FOR
CURRENT LIMITING RESISTOR.
TL/O/9213-2
FIGURE 2. Current Path during 01 Driver and
DO Buffer Conflict during Read Instruction
NMC9346/COP495
The NMC9346/COP495 has a self-timed programming cycle which uses DO to indicate the ready/busy status of the
chip. Therefore, in addition to the potential problem in the
READ mode similar to NMC9306/COP494 described
above, another pitfall may be encountered at the end of a
programming cycle in common I/O applications.
The self-timed programming cycle is initiated by the falling
edge of CS after a programming instruction (ERASE,
WRITE, ERAL, WRAL) is shifted in. If CS is brought high
subsequently, after a minimum of 1 p's (tcs), DO indicates
the ready/busy status of the chip. DO = logical '0' indicates
2) Clock SK once to ensure cancellation of the 'ready'
status.
3) Bring CS low for a minimum of 1 ,.s (tcs) to clear the
instruction register before initiating the first instruction.
NMC9346 Timing Diagrams
CSJ
01
~J---+--"",~-----------i
BIT
DO _T:.;.;RI;..:-ST;.;.;A.;;.:TE:;..®_ _ _
--i~ ~S----~
TL/O/9213-3
"The Ready/Busy Status Indicator for a program Instruction
(ERASE. WRITE. ERAL, WRAL) is resel when the Start bil
for the following Instruction is clocked in.
FIGURE 3. Programming Cycle with 4-Wire Interface
2-121
•
..,....coz
NMCS)346 Timing Diagrams (Continued)
8051 INTERFACE-SERIAL PORT
The 8051 serial port operates in one of four modes: 8-bit
shift register, 8-bit UART and two different 9 bit UART
modes. The 8-bit shift register mode (Mode 0) is preferred
because it operates with no protocol, as opposed to the
UART modes which send and receive packeted data. When
in Mode 0, the 8051 RxD pin is used as a serial in/out pin
and the shift clock is provided on the TxD pin. The TxD pin
would be connected to SK and RxD would be connected to
DI and DO on the NMC93CSxx device. CS, PE and PRE
would be connected the same way as in the port pin interface.
When using the serial port in Mode 0, the serial port control
register (SCaN) must be programmed by setting the SMO
and SM1 bits (bits 7 and 6) to O. The serial clock runs at a
fixed rate of '112 of the oscillator frequency. The maximum
frequency for the serial clock on NMC93CSxx devices is
1 MHz. This means the 8051 can run with an oscillator frequency up to 12 MHz. After every eighth bit is received or
transmitted the 8051 hardware will set either the receive
interrupt (RI) or transmit interrupt (TI) bit in SCaN. These
bits may be polled, or used to generate interrupts.
The software routines for the serial port interface are virtually the same as those for the previous example. The only
differences are that the 8051 serial port performs the same
functions as the SNDBYT and RCVBYT routines. Instead of
calling these routines, the REN bit is enabled to initiate reception and the data is read from the serial buffer (SBUF).
For writing, the data is written into SBUF to perform the
transfer. The routines poll the RI or TI bits. Because data
transactions are synchronous, interrupts are not applicable
(see Figure 1(Jj.
8096 INTERFACE
The 8096 is a 16-bit microcontroller. Like other microcontrollers, it interfaces easily to the NMC93CSxx devices. The
use of parallel port pins or the on-chip serial port provide
two interface options.
When implementing the parallel port pin interface, the
choice of the port pins used is more critical because more of
these pins have alternate functions. If the 8096 must perform external memory accesses, the use of Ports 3 and 4
becomes a problem because these two 8-bit ports make up
the address/data bus. Port 0 pins are used for the analog
input channels. Port 2 pins have alternate functions such as
the serial port. Port 1 pins do not have alternate functions
and may be preferred for use.
The 8096 provides an on-chip serial port which may be used
for interfacing the NMC93CSxx devices. The serial port has
4 modes of operation. The mode of interest for this application is the shift register mode (Mode 0). The 8096 shift register mode serial clock rate is not a fixed rate. It is therefore
the responsibility of the support software to program the
baud rate appropriately.
INTERFACING NMC93CSxx WITH HIGH PERFORMANCE
MICROPROCESSORS
High performance microprocessors like the NS32000,
iAPX386 and the MC680xO are usually implemented as central processor in computers and aren't directly involved with
peripheral devices. Rather, these machines communicate
over a backplane bus. These processors are designed for
high speed, parallel data transfers. The NMC93CSxx devices could be used with these processors if a serial bus is
implemented as part of the backplane bus. Typically, a serial bus would be used for system configuration or diagnostic
purposes. Both the VME bus and Multibus II supply serial
communication Signals that may be used' to interface
NMC93CSxx devices to a high performance processor.
SUMMARY
The NMC93CSxx family can be used in a wide variety of
applications. The devices provide a non-volatile, writeable
memory that requires the least amount of board space, support logic and power. The protect register allows for a flexible mix of RAM and ROM. The previous examples illustrate
that the NMC93CSxx family easily interfaces to microcontrollers and systems with a serial bus.
2-139
z
•
U\
C)
.....
;RCYByr - READ UrILIry ROUrINE
;rHIS ROUrINE WILL READ 8 BIrs OF DArA FROM rHE SERIAL PORr
. ;rHE DArA IS srORED IN rHE LOCArION POINrED Ar BY rHE DX REGIsrER.
RCVBYr:
BOP_SK:
BIr_l:
R_SHIFr:
LDB
ANDB
ORB
JBS
ANDB
SJMP
ORB
SHLB
DECB
JNE
LDB
REr
AH.#8
P2.#FBH
P2.#04H
P2.3.BIr_l
AL.#FEH
R_SHIFr
AL.#OlH
AL.l
;LOAD SHIFr COUNr
;srROBE SK
AH
;DONE?
BOP_SK
(DX) .AL
;SAVE DArA
;READ BIr
;RDEEPROM - READ DArA FROM EEPROM
;SI. SK. CS. SO = P2[3 ••• 0)
;rHIS RourINE WILL READ A SPECIFIED NUMBER OF ByrES FROM rHE
;EEPROM AND srORE rHE DArA. ARGUMENrs SUPPLIED ro rHIS RourINE
;ARE A ByrE COUNr. OPCODE/REGISrER ADDRESS. AND ADDRESS FOR
;srORING rHE DArA.
RDEEPROM:
RD_LOOP:
PUSH
LDB
ANDB
ORB
ORB
LCALL
ANDB
ORB
LCALL
INC
DECB
JNE
ANDB
POP
REr
DX
BL. (DX)+
P2.#FOH
P2.#03
P2.#04
SNDBYr
P2.#FBH
P2. #04H
RCVBYr
DX
BL
RD_LOOP
P2.#FDH
DX
;SAVE POINrER
;COPY BYrE COUNr
;CHIP SELEcr.srARr Blr
;SEND INsrRucrION
;GEr DUMMY BIr
;GEr DArA BYrES
;DONE?
;DESELEcr
;REsrORE POINrER
FIGURE 11. 8096 Port Pin Interface Read Routines
2-140
.
~
;SNDBYT - WRITE 8 BITS OF DATA TO PORT PIN
Z
CI1
;THIS ROUTINE WILL WRITE 8 BITS OF DATA TO THE PORT PIN. THE
;DATA BYTE IS POINTED AT BY THE DX REGISTER.
SNDBY:r:
SLOOP:
BITl:
TOG_SK:
LDB
LDB
JBS
ANDB
SJMP
ORB
ANDB
ORB
SHLB
DECB
JNE
RET
AH.#8
AL. (DX)
AL.7.BIT_l
P2.#FEH
TOG_SK
P2.#01H
P2.#FBH
P2.#04H
AL
AH
SLOOP
<:)
~
;LOAD SHIFT COUNT
;GET DATA BYTE
;SEND BIT
;DONE?
;WREEPROM - WRITE DATA TO EEPROM
;SI. SK. CS. SO = P2[3 •• 0]
;THIS ROUTINE WILL WRITE A SPECIFIED AMOUNT OF BYTES TO THE
:EEPROM. THE DATA TO BE WRITTEN IS POINTED AT BY THE DX REGISTER.
:THE ARGUMENTS INCLUDE THE BYTE COUNT. OPCODE/REGISTER ADDRESS.
:AND 1 OR MORE DATA BYTES.
WREEPROM:
LDB
ANDB
ORB
ORB
LCALL
INC
DECB
JNE
ANDB
RET
BL. (DX)+
P2.#FOH
P2.#03H
P2.#04H
SNDBYT
DX
BL
WR_LOOP
P2#FDH
;COPY BYTE COUNT
;CHIP SELECT. START BIT
:SEND DATA BYTES
:DONE?
;DESELECT/PROGRAM
FIGURE 12.8096 Parallel Port Pin Interface Write Routines
•
2·141
The Reliabilit~ of National Semiconductor's
EEPROM ProClucts
This applications note provides the non-volatile memory
system designer with the necessary information to design
reliable non-volatile memory subsystems. The first section is
an introduction to EEPROM technology. Next, is a description of the intrinsic failure mechanisms common to all
EEPROM devices. The third section is a description of the
reliability aspects of National Semiconductor's manufacturing process.
stroms thick is used in the region between the floating polysilicon gate and the N + drain region. National's E2 Cell allows Individual bit erasing and writing.
EEPROM technology relies upon stored charge on the floating gate to retain information. Floating and control gate voltages are referenced to the source which is grounded. A
mode of the equivalent capacitances and voltages for an
EEPROM is shown in Figure 2. VGS is the voltage on the
floating gate, and delta Q is the charge stored on the floating gate. The charge remains on the floating gate even
when power is not applied because the surrounding silicon
dioxide serves as an excellent insulating material. Electrons
are transferred to and from the floating gate and the underlying MOS device through a process known as FowlerNordheim tunneling.
INTRODUCTION TO EEPROM TECHNOLOGY
EEPROM Background
The Electrically Erasable Programmable Read Only Memory
(EEPROM) is a non-volatile, fully static data storage device
which is also electrically erasable. It can be erased and written rapidly without removing the chip from the end application system or using a PROM programmer. The technology
allows for both byte- and chip-clear operations. These advantages are in contrast to UVPROMs which require removal from the system and total erasure of all the bits on the
chip.
.
eONlROL GATE - - . - Vb
I
"J .Lero
flOATING GATE
1,.__ Ie Ie
v:tGS
'~
X""" T GB T GD
SOURCE AT GND
Technology Description
Ves
VDS
TUX/0006-2
National Semiconductor's NMOS EEPROM devices utilize a
vGS
2.5 micron process. This technology was developed from
the basic NMOS double poly process, which National Semiconductor's Memory Division has been using for about 10
years.
The new family of CMOS devices is based on National's 2
micron M2CMOS process, which is the process National
Semiconductor uses most widely for such diverse products
as: Gate Arrays, Telecom, Microprocessing and many others. It is presently fabricated in one of the most modern,
state-of-the-art, 6 inch wafer fab facilities in the world.
= Ves Coo + Vos eGO + VBS CGB +
eGS + eGB + eGO + Coo
"Q
FIGURE 2. Equivalent Capacitances and Voltages
Tunneling Physic,S
The non-volatile memory storage in EEPROMs takes advantage of a quantum mechanical phenomenon known as
Fowler-Nordheim tunneling. This tunneling process is a
function of the energy levels of the materials involved. A
schematic of the energy configuration for an EEPROM is
illustrated in Figure 3. The energy difference between the
valence and conduction bands in silicon dioxide (Si02l is
about 9.05 eV. The energy difference between the same
two bands for silicon (Si) is approximately 1.1 eV. When the
Si02 and the Si are joined together the conduction band of
the Si02 is 3.25 eV above the conduction band of the Si,
while the valence band of the Si02 lies about 4.7 eV below
the valence band of the Si. Since the thermal energy of an
electron at room temperature (23'C) is only 0.025 eV the
likelihood of an electron jumping from the valence band of
the Si02 to the conduction band of the Si02 is very slight.
Device Description
National Semiconductor EEPROM devices utilize a double
poly silicon gate process. Figure 1 depicts the basic memory element in cross section. It is comprised of an N-channel
transistor with an additional floating polysilicon gate sandwiched between the control gate and the transistor channel
region. The gate structures are separated from each other
and from the transistor channel and drain regions by silicon
dioxide (Si02). A tunnel oxide which is less than 120 Ang-
CONDUCTION BAND 5102
CONDUCTION BAND SI
VALENCE BAND 51
j
1
'It ,~un, I
TLiX/0006-3
FIGURE 3. Energy Band Diagram of the Si
and SI02 System In its Neutral State
TL/X/0006-1
FIGURE 1. Cross Section of MOS
Floating Gate EEPROM
2-142
::xJ
gion. The electric field intensity across the tunneling 5i02
region is determined by the capacitive coupling ratio of the
cell.
Fowler-Nordheim tunneling predicts that these energy
bands can be distorted in the presence of an electric field.
This process is depicted in Figure 4. In EEPROMs, tunneling
of electrons occurs between the drain and floating gate
through the 5i02 tunneling region. The direction of FowlerNordheim tunneling of electrons through the tunneling region depends on the polarity of the voltages between the
control gate and the drain. Tunneling physics predicts that
when the electric fields across a thin insulator, such as
5i02, are high enough, electrons from the negative electrode can acquire enough energy to pass or tunnel through
the forbidden gap and enter the conduction band. The resulting current flux (J) is approximately proportional to an
exponential function of the applied voltage M as illustrated
in Figure 5. In order to obtain fields strengths large enough
to initiate tunneling (V > 7 X 106 eV/cm), at reasonable
voltages (20V), the 5i02 layer must be limited to a thickness
less than 120 Angstroms.
.19V
:::I
UNE
!!!..
OV
WORD
en
CD
LINE
3
o·
o
ELEC1RON
flOW
Tl/X/0006-6
n
0"
OV
CONIROl GA1£
(WORD LINE)
UI~
m
m
-a
C SECOND POLY ~
::xJ
o
==
-a
ac.
N+
c
TLiX/0006-7
FIGURE 6. Write Operation
SilICON
SUBSTRA1£
~
During the erase operation the drain is set to ground potential while the control gate is pulled up to 21V, as shown in
Figure 7. This charging of the control gate causes the floating gate to become capacitively coupled with a positive bias
and electrons then tunnel from the drain into the floating
gate. The transfer of electrons shifts the cell threshold positive forcing the transistor to pinch-off current flow, which is
then interpreted as a logic "1" state at its output.
(+)
GA1£
:::I
C.
C
..
E2PROM Transistor Write
I
POlYSllCON
~
o
z
o·
+21 V
SELECT
(-)
ji'
g;
-a
SELECTED
COLUMN
SELECTED
BIT
!!.
TLiX/0006-4
FIGURE 4_ Distortion of Energy Bands In the
Presence of a Strong Electric Field
SELECTED
COLUMN
DV
10-'
'0- 2
'0- 3
'0- 4
~
10"5
-,
10.. 6
C
+21V
SELECT
UNE
+21V
WORD
10-7
UNE
'0- 8
SELECT£1l
BIT
'0-<1 I---A_-'-_-'-_-'-_.1-_
10
11
12
6
ELEC1RON
flOW
TLiX/0006-B
E2PROM Transistor
TLiX/0006-5
FIGURE 5. Fowler-Nordheim
Tunneling I-V Characteristic
(Vpp)
21 V
CONIROL GA1£
(WORD LINE)
Device Operation
To write the cell to logic "0" the control gate is set to ground
potential, and a high voltage (19V) is applied to the drain,
while the source is left floating. The write operation is shown
in Figure 6. This causes electrons on the floating gate to
tunnel through the 5i02 into the drain. In this configuration
the transistor will allow current to flow. The electric field
strength is highest in the region between the floating gate
and the drain. Hence tunneling occurs in this thin 5i02 re-
N+
TLIX/0006-9
FIGURE 7. Erase Operation
2-143
,.
tI
E2PROM Transistor
:=I
"a
e
and failure mechanisms associated with EEPROMs, the designer can construct systems which successfully account
for these limitations. The three primary failure mechanisms
which affect all EEPROMs are charge trapping and tunnel
oxide breakdown which are endurance related, and charge
leakage which is data retention related.
SELECltD
COLUMN
2.0 V
a..
:::E
oa::
a..
5.0V
SElEer
LINE
i..
en
3.5V
WORD
LINE
"a
SElECltD
BIT
w
w
~:=I
C
g
TUX/DD06-1 D
'E
3.5 V
~
CONTROL GATE
(WDRD LINE)
1i
c
~
2.0V
-
DRAIN
__- - -...... (COLUMN)
(
RRST PDLY
J I
Z
o
~
N+)
:s
C
N+
.!!!
a;
a::
Endurance
An EEPROM's endurance-that is, the number of write and
erase operations through which each bit c' 2000V input protection for electrostatic discharge
• TRI-STATE outputs
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.
Block Diagram
A4
A3
A2
256 BIT OR ARRAY
PROVIDING
AI
ALL 32 PRODUCT TERt.lS
AD
07
06
05
04
03
02
01
00
TLl0/6747-1
Pin Names
AO-M
Addresses
G
Output Enable
GND
Ground
QO-Q7
Outputs
Vee
Power Supply
3-6
,--------------------------------------------------------------------------,
~
!;
Connection Diagrams
......
><
N
Dual-In-Llne Package
Plastic Leaded Chip Carrier (PLCC)
'-/
a g ~ ~I(!)
00- 1
16
-Vee
15
-G
I
I
I
3
2
1 20 19
I
CD
CD
m
I
01- 2
02- 3
14 -A4
02- 4
18 -A4
03- 4
13 -A3
03- 5
17 -A3
04- 5
A5- 6
12 -A2
NC- 6
16 -NC
II-AI
04- 7
15 -A2
06- 7
10 -AO
05- 8
GND- 8
9 -07
14 -AI
9 10 11 12 13
TUD/6747-2
Top View
Tl/D/6747-9
Top View
Order Number PL87X288BJ or PL87X288BN
See NS Package Number J16A or N16A
Order Number PL87X288BV
See NS Package Number V20A
Ordering Information
Commercial Temperature Range
O'Cto +70'C
Max Access Time (ns)
Parameter/Order Number
PL87X288BN
15
PL87X288BJ
15
PL87X288BV
15
3·7
ID
co
~
><
.....
~
a..
Absolute Maximum Ratings
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Note 2)
-0.5to +7.0V
Input Voltage (Note 2)
-1.2to +5.5V
Output Voltage (Note 2)
-0.5to +5.5V
Storage Temperature
-65 to + 150'C
Lead Temperature (Soldering, 10 seconds)
300'C
ESDRating
>2000V
Supply Voltage (Veel
PL87X288B
Ambient Temperature (TA)
PL87X288B
Logical "0" Input Voltage
Logical "1" Input Voltage
Min
Max
Units
4.75
5.25
V
0
0
2.0
+70
0.8
5.5
'C
V
V
DC Electrical Characteristics (Note 3)
Symbol
PL87X288B
Conditions
Parameter
Min
Units
Typ
Max
-80
-250
IlL
Input Load Current
Vee = Max, VIN = 0.4V
IIH
Input Leakage Current
Vee = Max, VIN = 2.7V
25
IJoA
Vee = Max, VIN = 5.5V
1.0
mA
0.50
V
0.80
V
VOL
Low Level Output Voltage
0.35
Vee = Min, IOL = 24 mA
IJoA
VIL
Low Level Input Voltage
(Note 7)
VIH
High Level Input Voltage
(Note 7)
Ve
Input Clamp Voltage
Vee = Min,IIN = -18 mA
CI
Input Capacitance
Vee = 5.0V, VIN = 2.0V
TA = 25'C, 1 MHz
4.0
pF
Co
Output Capacitance
Vee = 5.0V, Vo = 2.0V
TA = 25'C, 1 MHz, Outputs Off
6.0
pF
Ice
Power Supply Current
Vee = Max, Input Grounded
All Outputs Open
110
los
Short Circuit
Output Current
Vo = OV, Vee = Max
(Note 4)
10Z
Output Leakage
(TRI.STATE)
Vee = Max, Vo = O.4V to 2.4V
Chip Disabled
2.0
V
-0.8
-1.5
-30
V
140
mA
-130
mA
100
-100
IJoA
2.4
3.2
V
Output Voltage High
IOH = -3.2mA
VOH
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated at
these values.
Note 2: These limits do not apply during programming. For the programming ratings, refer to the programming instructions.
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee ~ S.OV and TA
~
2S'C.
Note 4: During los measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
Note 5: CL ~ 50 pF.
Note 6: CL ~ 5 pF.
Note 7: These are absolute voltages with respect to the ground pin on the device and includes all overshoots due to system and/or tester noise. Do not attempt to
test these values without suitable equipment.
3·8
"'\::J
r-
AC Electrical Characteristics with standard load and operating conditions
Symbol
Parameter
JEDEC
Symbol
CD
.......
><
~
PL87X288B
Min
Units
Typ
Max
TAVQV
10
15
ns
OJ
tAA
Address Access Time (Note 5)
tEA
Enable Access Time (Note 5)
TEVQV
8
12
ns
tER
Enable Recovery Time (Note 6)
TEXQX
8
12
ns
tzx
Output Enable Time (Note 5)
TEVQX
8
12
ns
txz
Output Disable Time (Note 6)
TEXQZ
8
12
ns
Functional Description
(J-package). Device performance in all package configurations is excellent.
TESTABILITY
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
TITANIUM·TUNGSTEN FUSES
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metalization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
3-9
CD
CD
~National
~ Semiconductor
DM54/74S188
(32 x 8) 256-Bit TTL PROM
General Description
Features
This Schottky memory is organized in the popular 32 words
by 8 bits configuration. A memory enable input is provided
to control the output states. When the device is enabled, the
outputs represent the contents of the selected word. When
disabled, the 8 outputs go to the "OFF" or high impedance
state.
• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access down to-25 ns max
Enable access-20 ns max
Enable recovery-20 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over
temperature
• Low voltage TRI-SAFETM programming
• Open-collector outputs
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.
Block Diagram
Pin Names
A4
A3
A2
256-81T ARRAY
32 x8
MEMORY MATRIX
Al
AD
07
06
05
04
03
02
Q1
00
TU0/9187-1
3-10
AO-A4
Addresses
G
Output Enable
GND
Ground
00-07
Outputs
Vee
Power Supply
r--------------------------------------------------------------------------,
Connection Diagrams
Dual-In-Line Package
C
:s:
U1
""...
(J)
Plastic Leaded Chip Carrier (PLCC)
CI)
00- 1
'-/
01- 2
-
16
o
I-Vcc
0
0
(,)
z
CI)
......
.....
8 I'"
I I
>
I
I
I
3
2
1 20 19
...""
(J)
02- 3
15 r-G
14 r-A4
03- 4
13 r-A3
03- 5
17 -A3
04- 5
12 r-A2
NC- 6
16 -NC
05- 6
11 r-Al
04- 7
15 -A2
06- 7
10 r-AO
05-8
14-Al
GND- 8
91-07
CI)
CI)
18 -A4
02- 4
9 10 11 12 13
TLlD/9187-2
Top View
TL/D/91 87-3
Top View
Order Number DM54/74S188J, 188AJ,
DM74S188N or 188AN
See NS Package Number J16A or N16A
Order Number DM74S188Vor 188AV
See NS Package Number V20A
Ordering Information
Commercial Temp Range (O"C to
Parameter/Order Number
+ 70'C)
Max Access Time (ns)
DM74S1BBN
35
DM74S1BBJ
35
DM74S1BBV
35
DM74S1BBAN
25
DM74S1BBAJ
25
DM74S1BBAV
25
Military Temp Range ( - 55'C to
Parameter/Order Number
+ 125'C)
Max Access Time (ns)
DM54S1BBJ
45
DM54S1BBAJ
35
•
3-11
Absolute Maximun Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Note 2)
-0.5Vto +7.0V
Input Voltage (Note 2)
-1.2Vto +5.5V
Output Voltage (Note 2)
-0.5Vto +5.5V
- 65·C to + 150"C
Storage Temperature
300·C
Lead Temp. (Soldering, 10 seconds)
ESD to be determined
Supply Voltage (Vecl
Military
Commercial
Ambient Temperature (TA)
Military
Commercial
Logical "0" Input Voltage
Logical "1" Input Voltage
Min
Max
Units
4.50
4.75
5.50
5.25
V
V
-55
0
0
2.0
+125
+70
0.8
5.5
·C
·C
V
V
DC Electrical Characteristics (Note 3)
Symbol
Parameter
DM54S188
Conditions
IlL
Input Load Current
IIH
Input Leakage Current
=
Vee =
Vee =
Vee =
Vee
VOL
Low Level Output Voltage
VIL(Note4)
Low Level Input Voltage
VIH(Note4)
High Level Input Voltage
loz
Output Leakage Current
(Open-Collector Only)
Ve
Input Clamp Voltage
CI
Input Capacitance
Co
Output Capacitance
= 0.45V
Max, VIN = 2.7V
Max, VIN = 5.5V
Min, IOL = 16 mA
Max, VIN
DM74S188
Typ
Max
-80
-250
Min
0.35
Min
Units
Typ
Max
-80
-250
25
IJ-A
1.0
1.0
mA
0.45
V
0.80
V
0.50
0.35
0.80
V
2.0
2.0
= Max, VeEX = 2.4V
= Max, VeEx = 5.5V
Vee = Min, liN = -18 mA
Vee = 5.0V, VIN = 2.0V
TA = 25·C, 1 MHz
Vee = 5.0V, Vo = 2.0V
TA = 25·C, 1 MHz, Outputs Off
IJ-A
25
Vee
50
50
IJ-A
Vee
100
100
p.A
-1.2
V
-0.8
-0.8
-1.2
4.0
4.0
pF
6.0
6.0
pF
Vee = Max, Input Grounded
110
70
70
110
mA
All Outputs Open
Nole 1: Absolute Maximum Ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated
Icc
Power Supply Current
at these values.
Nole 2: These limits do
not apply during programming. For the programming ratings, refer to the programming instructions.
Nole 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee ~ 5.0V and TA ~ 25"C.
Note 4: These are absolute voltages with respect to pin 8 on the device and Include all overshoots due to system andlor tester noise. Do not attempt to test these
vaJues without suitable equipment
AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMP RANGE (O·C to + 70"C)
JEDEC
Symbol
Parameter
TAA
TAVQV
TEA
TEVQV
TER
Symbol
DM74S188
DM74S188A
Typ
Max
Address Access Time
22
Enable Access Time
15
TEXQX
Enable Recovery Time
TZX
TEVQX
TXZ
TEXQZ
Min
Units
Typ
Max
35
17
25
ns
20
15
20
ns
15
25
15
20
ns
Output Enable Time
15
20
15
20
ns
Output Disable Time
15
25
15
20
ns
3-12
Min
c
15:
AC Electrical Characteristics with Standard Load and Operating Conditions (Continued)
MILITARY TEMP RANGE ( - 55'C to
""
en
.....
+ 125'C)
JEDEC
Symbol
Parameter
TAA
TAVQV
TEA
TEVQV
TER
TZX
TXZ
Symbol
UI
DM54S188
DM54S188A
Units
Typ
Max
45
17
35
ns
30
15
30
ns
15
35
15
30
ns
15
30
15
30
ns
15
35
15
30
ns
Typ
Max
Address Access Time
22
Enable Access Time
15
TEXQX
Enable Recovery Time
TEVQX
Output Enable Time
TEXQZ
Output Disable Time
Min
CO
CO
Min
Functional Description
TESTABILITY
TITANIUM-TUNGSTEN FUSES
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links deSigned to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-Chip programming circuit.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is deSigned to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.
3-13
.....
.....
""
en
.....
CO
CO
co
co
~ ~National
~ ~ Semiconductor
.....
co
~ DM54/74S288 (32
In
:::E
x 8)
256-Bit TTL PROM
Q
General Description
Features
This Schottky memory is organized in the popular 32 words
by 8 bits configuration. A memory enable input is provided
to control the output states. When the device is enabled, the
outputs represent the contents of the selected word. When
disabled, the 8 outputs go to the "OFF" or high impedance
state.
• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access down to--25 ns max
Enable access-20 ns max
Enable recovery-20 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over
temperature
• Low voltage TRI-SAFETM programming
• TRI-STATE® Outputs
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.
Block Diagram
A4
A3
A2
25lj.BlT ARRAY
AI
MEMORY MATRIX
32 xB
AD
07
06
05
04
03
02
01
00
TL/0/8360-1
Pin Names
AO-A4
Addresses
G
Enable
GND
Ground
QO-Q?
Outputs
Vee
Power Supply
3-14
Connection Diagrams
Dual·ln·Llne Package
00- 1
01- 2
'-.../
16
15
Plastic Leaded Chip Carrier (PLCC)
a
I-Vcc
I
Hi
g ~ .}Ic)
I I I I
3 2
1 20 19
02- 3
03- 4
14 I-M
13 r-A3
02- 4
03- 5
18 -A4
04- 5
NC- 6
05- 6
06- 7
12 r-A2
11 r-Al
10 r-AO
16 -NC
15 -A2
14-Al
GND- 8
9 r-07
17 -A3
04- 7
05- 8
9 10 11 12 13
TL/D/8360-2
Top View
TL/D/B360-7
Top View
Order Number DM54174S288J, 288AJ or
DM74S288N,288AN
See NS Package Number J16A or N16A
Order Number DM74S288V or 288AV
See NS Package Number V20A
Ordering Information
Commercial Temp Range (O"C to
Parameter/Order Number
+ 70"C)
Max Access Time (ns)
DM74S2BBN
35
DM74S2BBJ
35
DM74S2BBV
35
DM74S2BBAN
25
DM74S2BBAJ
25
DM74S2BBAV
25
Military Temp Range (-55"C to
Parameter/Order Number
+ 125'C)
Max Access Time (ns)
DM54S2BBJ
45
DM54S2BBAJ
35
3·15
Absolute Maximum Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Note 2)
-0.5V to + 7.0V
Input Voltage (Note 2)
-1.2Vto +5.5V
-0.5Vto +5.5V
Output Voltage (Note 2)
Storage Temperature
-65'C to + 150'C
Lead Temperature (Soldering, 10 sec.)
300'C
ESD rating to be determined
DC Electrical Characteristics
Symbol
Parameter
Min
Max
Units
Supply Voltage (Vee>
Military
Commercial
4.50
4.75
5.50
5.25
V
V
Ambient Temperature (TA)
Military
Commercial
-55
0
+125
+70
'C
'C
Logical "0" Input Voltage
0
0.8
V
Logical "1" Input Voltage
2.0
5.5
V
(Note 3)
DM54S288
Conditions
Min
DM74S288
Typ
Max
-80
-250
Min
Units
Typ
Max
-80
-250
III
Input Load Current
Vee = Max, VIN = 0.45V
IIH
Input Leakage Current
Vee = Max, VIN = 2.7V
25
25
)LA
Vee = Max, VIN = 5.5V
1.0
1.0
mA
0.45
V
0.80
V
.iVOl
Vil (Note 4)
Low Level Output Voltage
Vee = Min, IOl = 16 mA
0.35
Low Level Input Voltage
0.50
0.35
0.80
2.0
VIH (Note 4)
High Level Input Voltage
Ve
Input Clamp Voltage
Vee = Min, liN = -18 mA
CI
Input Capacitance
Vee = 5.0, VIN = 2.0V
TA = 25'C, 1 MHz
4.0
4.0
pF
Co
Output Capacitance
Vee = 5.0V, Va = 2.0V
T A = 25'C, 1 MHz, Outputs Off
6.0
6.0
pF
Icc
Power Supply Current
Vee = Max, Input Grounded
All Outputs Open
70
los
Short Circuit
Output Current
Va = OV, Vee = Max
(Note 5)
loz
Output Leakage
(TRI-STATE)
Vee = Max, Va = 0.45V to 2.4V
Chip Disabled
Output Voltage High
10H = -2.0mA
VOH
2.0
)LA
-0.8
-20
2.4
-1.2
V
-0.8
110
V
110
mA
-70
mA
+50
+50
)LA
-50
-50
)LA
-70
70
-1.2
-20
3.2
10H = -6.5mA
V
2.4
3.2
V
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated at
these values.
Note 2: These limits do not apply during programming. For the programming ratings, refer to the programming instructions.
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = 5.0V and TA = 25°C.
Note 4: These are absolute voltages with respect to pin 8 on the device and include all overshoots due to system and/or tester noise. Do not attempt to test these
values without suitable equipment.
Note 5: During los measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
3-16
c
3:
AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMPERATURE RANGE (O°C to
Symbol
"'coen"
+ 70°C)
JEDEC
Symbol
Parameter
U1
N
DM74S288
Min
DM74S288A
Typ
Max
Min
Units
Typ
Max
3:
TAA
Address Access Time
TAVQV
22
35
17
25
ns
TEA
Enable Access Time
TEVQV
15
20
15
20
ns
TER
Enable Recovery Time
TEXQX
15
25
15
20
ns
TZX
Output Enable Time
TEVQX
15
25
15
20
ns
TXZ
Output Disable Time
TEXQZ
15
25
15
20
ns
MILITARY TEMPERATURE RANGE (-55°C to
+ 125°C)
JEDEC
Symbol
Parameter
TAA
TAVQV
Address Access Time
22
TEA
TEVQV
Enable Access Time
15
TER
TEXQX
Enable Recovery Time
15
35
TZX
TEVQZ
Output Enable Time
15
30
TXZ
TEXQZ
Output Disable Time
15
35
15
Symbol
DM54S288
Min
Typ
DM54S288A
Max
Min
Units
Typ
Max
45
17
35
ns
30
15
30
ns
15
30
ns
15
30
ns
30
ns
Functional Description
TESTABILITY
TITANIUM-TUNGSTEN FUSES
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metalization is an integral part, and the use of an
on-chip programming circuit.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.
3-17
co
......
c
.......
en
"'"
N
co
co
~
co
~
~
:::iii
C
....
r----------------------------------------------------------------------------,
'?A National
~ Semiconductor
~
co
DM54/74S287
~ (256 x 4) 1024-Bit TTL PROM
:::iii
II)
C
General Description
Features
This Schottky memory is organized in the popular 256
words by 4 bits configuration. Memory enable inputs are
provided to control the output states. When the device is
enabled, the outputs represent the contents of the selected
word. When disabled, the 4 outputs go to the "OFF" or high
impedance state.
• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access-down to 30 ns max
Enable access-20 ns max
Enable recovery-20 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over
temperature
• Low voltage TRI-SAFETM programming
• > 2000V input protection for electrostatic discharge
• TRI-STATE® outputs
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.
Block Diagram
A7
A6
11124-8IT ARRAY
Pin Names
32 x 32
AS
AO-A7
MEMORY MATRIX
A4
A3
Addresses
G1,G2
Output Enables
GND
Ground
A2 - - - - I
00-03
Outputs
AI----I
AD - - - - f
Vee
Power Supply
DECODER
03
02
Q1
00
TU0/8359-1
3-18
Connection Diagrams
Dual-In-Line-Package
Plastic Leaded Chip Carrier (PLCC)
A6.!.~~VCC
7~ ¥ f ~
~A7
AS1
A3
3
~G2
~ iIT
~oo
A41
.!
AOJ.
.!
All
GND 1.
Al
2
1 20 19
M-4
lSI- G2
A3- 5
171- G1
t!!. 01
AO- 6
161-00
02
03
Al- 7
15i-NC
A2-S
141-01
~
t!-
9 10 11 12 13
TL/D/8359-2
Top View
Order Number DM54174S287J, 287AJ,
DM74S287N or 287AN
See NS Package Number J16A or N16A
TL/D/B359-7
Top View
Order Number DM74S287V or 287AV
See NS Package Number V20A
Ordering Information
Commercial Temp Range (O·C to
Parameter/Order Number
+ 70·C)
Max Access Time (ns)
DM74S287AJ
30
DM74S287J
50
DM74S287AN
30
DM74S287N
50
DM74S287AV
30
DM74S287V
50
Military Temp Range (-55"C to
Parameter/Order Number
+ 125·C)
Max Access Time (ns)
DM54S287AJ
40
DM54S287J
60
•
3-19
Absolute Maximum Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5 to +7.0V
Supply Voltage (Note 2)
Input Voltage (Note 2)
-1.2Vto +5.5V
-0.5Vto +5.5V
Output Voltage (Note 2)
Storage Temperature
-65'Cto + 150'C
Lead Temp. (Soldering, 10 seconds)
300'e
ESD
>2000V
Supply Voltage (Vecl
Military
Commercial
Ambient Temperature (TA)
Military
Commercial
Logical "0" Input Voltage
Logical "1 " Input Voltage
Min
Max
Units
4.50
4.75
5.50
5.25
V
V
-55
0
0
2.0
+125
70
0.8
5.5
'e
'e
V
V
DC Electrical Characteristics (Note 3)
Symbol
Parameter
DM54S287
Conditions
Min
IlL
Input Load Current
Vee = Max, VIN=0.45V
IIH
Input Leakage Current
Vee = Max, VIN=2.7V
VOL
Low Level Output Voltage
Max
-80
-250
Low Level Input Voltage
VIH (Note 4)
High Level Input Voltage
Min
Max
-80
-250
p.A
25
p.A
1.0
mA
0.45
V
1.0
0.35
Vee = Min, 10L =16mA
0.50
0.35
0.80
2.0
Units
Typ
25
Vee = Max, VIN=5.5V
VIL (Note 4)
DM74S287
Typ
0.80
2.0
-0.8
-1.2
V
V
-0.8
Ve
Input Clamp Voltage
Vee = Min, IIN= -18 mA
CI
Input CapaCitance
Vee=5.0V, VIN=2.0V
TA=25'C,1 MHz
4.0
4.0
pF
Co
Output Capacitance
Vee=5.0V, Vo=2.0V
TA=25'C,1 MHz, Outputs Off
6.0
6.0
pF
Icc
Power Supply Current
Vee = Max, Inputs Grounded
All Outputs Open
80
los
Short Circuit
Output Current
Vo=OV, Vee = Max
(Note 5)
loz
Output Leakage
(TRI-STATE)
Vee=Max, Vo=0.45Vto 2.4V
Chip Disabled
Output Voltage High
IOH=-2.0mA
VOH
-70
-20
2.4
130
80
-20
-1.2
V
130
mA
-70
mA
+50
+50
p.A
-50
-50
p.A
3.2
V
IOH=-6.5mA
2.4
3.2
V
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated at
these values.
Note 2: These limits do not apply during programming. For the programming ratings. refer to the programming instructions.
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = S.OV and TA = + 25"e.
Note 4: These are absolute voltages with respect to pin 8 on the devios and include all overshoots due to system and/or tester noise. Do not attempt to test these
values without suitable equipment.
Note 5: During los measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
3-20
AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMP RANGE (O·C to
+ 70·C)
DM74S287
Symbol
JEDEC Symbol
Parameter
Min
Typ
DM74S287A
Max
Min
Typ
Max
Units
TAA
TAVQV
Address Access Time
35
50
20
30
ns
TEA
TEVQV
Enable Access Time
15
25
15
20
ns
TER
TEXQX
Enable Recovery Time
15
25
15
20
ns
TZX
TEVQX
Output Enable Time
15
25
15
20
ns
TXZ
TEXQZ
Output Disable Time
15
25
15
20
ns
MILITARY TEMP RANGE ( - 55·C to
+ 125·C)
DM54S287
Symbol
DM54S287A
JEDEC Symbol
Parameter
TAA
TAVQV
Address Access Time
35
60
20
40
ns
TEA
TEVQV
Enable Access Time
15
30
15
30
ns
TER
TEXQX
Enable Recovery Time
15
30
15
30
ns
TZX
TEVQX
Output Enable Time
15
30
15
30
ns
TXZ
TEXQZ
Output Disable Time
15
30
15
30
ns
Min
Typ
Max
Min
Typ
Max
Units
Functional Description
TESTABILITY
TITANIUM·TUNGSTEN FUSES
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy 8
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.
3-21
•
r-. ,----------------------------------------------------------------------------,
CD
~National
~
r-.
::::E
C
......
r-.
CD
C")
~
It)
::::E
~
Semiconductor
DM54/745387
(256 x 4) 1024-Bit TTL PROM
C
General Description
Features
This Schottky memory is organized in the popular 256
words by 4 bits configuration. Memory enable inputs are
provided to control the output states. When the device is
enabled, the outputs represent the contents of the selected
word. When disabled, the 4 outputs go to the "OFF" or high
impedance state.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.
• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access-down to 30 ns max
Enable access-20 ns max
Enable recovery-20 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over temperature
• Low voltage TRI-SAFETM programming
• Open-collector outputs
Block Diagram
AI
AS
II124-BIT ARRAY
32,32
AS
A4
A3
A2
AI
MEMORY MATIIIX
------I
------I
AO-------,t..=or-"'-"""-I.....,""'-'"'"--'=>....I
03
02
01
ao
Pin Names
AO-A7
Addresses
G1-G2
Output Enables
GND
Ground
00-03
Outputs
Vee
Power Supply
3-22
TUO/9188-1
Connection Diagrams
Dual-In-Llne Package
Plastic Leaded Chip Carrier (PLCC)
'--"
~ f ¥f r
A6- 1
A5- 2
16 -Vee
15 -A7
A4- 3
14
3
2
1 20 19
A4- 4
18 ~G2
A3- 4
13
-G2
-iii
A3- 5
17 ~iii
AO- 5
12 -QO
AO- 6
16
I- QO
A1- 6
A1- 7
15
~NC
A2- 7
11-Q1
10 -Q2
A2- 8
14~Q1
GND- 8
9 -Q3
9 10 11 12 13
TL/D/9188-2
TUD/9188-3
Top View
Top View
Order Number DM54174S387J, 387AJ,
DM74S387N,387AN
See NS Package Number J16A or N 16A
Order Number DM74S387V, 387AV
See NS Package Number V20A
Ordering Information
Commercial Temp Range (O"C to
Parameter/Order Number
+ 70'C)
Max Access Time (ns)
DM74S387AJ
30
DM74S387J
50
DM74S387AN
30
DM74S387N
50
DM74S387AV
30
DM74S387V
50
Military Temp Range (-55'C to
Parameter/Order Number
+ 125'C)
.Max Access Time (ns)
DM54S387AJ
40
DM54S387J
60
•
3·23
Absolute Maximum Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Note 2)
-0.5Vto + 7.0V
Input Voltage (Note 2)
-1.2Vto +5.5V
Output Voltage (Note 2)
-0.5Vto +5.5V
Storage Temperature
300'C
ESO
Max
Units
4.50
4.75
5.50
5.25
V
V
-55
0
+125
70
'C
'C
Logical "0" Input Voltage
0
0.8
V
Logical "1" Input Voltage
2.0
5.5
V
Ambient Temperature
Military
Commercial
- 65'C to + 150'C
Lead Temp. (Soldering, 10 seconds)
Min
Supply Voltage (Vecl
Military
Commercial
>2000V
(TAl
DC Electrical Characteristics (Note 3)
Symbol
Parameter
DM54S387
Conditions
Min
DM74S387
Typ
Max
-80
-250
Min
Units
Typ
Max
-80
-250
IlL
Input Load Current
Vee
=
Max, VIN
=
0.45V
IIH
Input Leakage Current
Vee
Max, VIN
=
=
2.7V
25
25
p.A
Vee
=
=
5.5V
1.0
1.0
mA
Vee
=
Min, 10L
VOL
Low Level Output Voltage
VIL(Note 4)
Low Level Input Voltage
VIH(Note4)
High Level Input Voltage
loz
Output Leakage Current
(Open-Collector Only)
Max, VIN
=
0.35
16 mA
0.35
0.50
0.80
0.45
V
0.80
V
2.0
2.0
p.A
V
Vee
=
Max, VeEx
=
2.4V
50
50
p.A
Vee
=
=
Max, VeEX
=
5.5V
100
100
p.A
-1.2
V
=
Ve
Input Clamp Voltage
Vee
CI
Input Capacitance
Vee = 5.OV, VIN = 2.0V
TA = 25'C, 1 MHz
4.0
4.0
pF
Co
Output Capacitance
Vee = 5.OV, Va = 2.0V
TA = 25'C, 1 MHz, Outputs Off
6.0
6.0
pF
Icc
Power Supply Current
Vee = Max, Inputs Grounded
All Outputs Open
80
Note 1: Absolute maximum
these values.
Min, liN
-18 mA
-0.8
-1.2
-0.8
130
80
130
mA
ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated at
Note 2: These limits do not apply during programming. For the programming ratings, refer to the programming instructions.
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee
~
5.0V and TA
~
+ 25'C.
Note 4: These are absolute voltages with respect to pin 8 on the device and include all overshoots due to system and/or tester noise. Do not attempt to test these
values without suitable equipment.
3-24
AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMP RANGE (O'C to
Symbol
Parameter
+ 70'C)
DM74S387
JEDEC Symbol
Min
DM74S387A
Typ
Max
Min
Units
Typ
Max
TAA
Address Access Time
TAVaV
35
50
20
30
ns
TEA
Enable Access Time
TEVaV
15
25
15
20
ns
TER
Enable Recovery Time
TEXaX
15
25
15
20
ns
TZX
Output Enable Time
TEVaX
15
25
15
20
ns
TXZ
Output Disable Time
TEXaZ
15
25
15
20
ns
MILITARY TEMP RANGE (-55'Cto
Symbol
+ 125'C)
Parameter
DM54S387
JEDEC Symbol
Min
DM54S387A
Typ
Max
Min
Units
Typ
Max
TAA
Address Access Time
TAVaV
35
60
20
40
ns
TEA
Enable Access Time
TEVaV
15
30
15
30
ns
TER
Enable Recovery Time
TEXaX
15
30
15
30
ns
TZX
Output Enable Time
TEVaX
15
30
15
30
ns
TXZ
Output Disable Time
TEXaZ
15
30
15
30
ns
Functional Description
TESTABILITY
TITANIUM-TUNGSTEN FUSES
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide ~igh performance over the entire operating ranges of Vee and temperature.
3-25
•
~National
~
Semiconductor
DM54/74LS471
(256 x 8) 2048-Bit TTL PROM
General Description
Features
These Schottky memories are organized in the popular 256
words by 8 bits configuration. Memory enable inputs are
provided to control the output states. When the device is
enabled, the outputs represent the contents of the selected
word. When disabled, the 8 outputs go to the "OFF" or high
impedance state.
• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access down t0-60 ns max
Enable access-3~ ns max
Enable recovery-30 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over temperature
• Low voltage TRI-SAFETM programming
• TRI-STATE® outputs
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.
Block Diagram
A7
A6
AS
AO
1
2048-BIT ARRAY
32 x 64
MEMORY MATRIX
32
Al
DECODER
A2----I
A3----I
A4 - - - - I
ENABLE
GATE
07
OB
05
04
03
Pin Names
AO-A7
Addresses
G1-G2
Output Enables
GND
Ground
QO-Q7
Outputs
Vee
Power Supply
3-26
02
01
00
TL/O/9190-1
.----------------------------------------------------------------------.0
a::
Connection Diagrams
U'I
Dual·ln·Llne Package
AO- 1
Al- 2
A2- 3
'-./
'"
_
0
"".....
....
.....
o
~ ....
iii I i
20 ~VCC
19 ~A7
18 ~A6
A3- 4
18~A6
A3- 4
A4- 5
17 ~A5
16 ~
Military
Commercial
Ambient Temperature (TAl
Military
Commercial
Logical "0" Input Voltage
Logical "1" Input Voltage
- 65'C to + 150'C
Lead Temp. (Soldering, 10 seconds)
300'C
Min
Max
Units
4.50
4.75
5.50
5.25
V
V
-55
0
0
2.0
+125
+70
0.8
5.5
'C
'C
V
V
ESD to be determined
Note 1: Absolute maximum ratings are those values beyond which the da-
vice may be pennanently damaged. They do not mean that the device may
be operated at these values.
Note 2: These lim"s do not apply during programming ratings. refer to the
programming instructions.
DC Electrical Characteristics (Note 1)
Symbol
Parameter
Min
IlL
Input Load Current
Vee
IIH
Input Leakage Current
Vee
Vee
VOL
Low Level Output Voltage
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
Vee
=
=
=
=
DM74LS471
DM54LS471
Conditions
= 0.45V
= 2.7V
Max, VIN = 5.5V
Min, 10L = 16 mA
Max. VIN
Typ
Max
-80
-250
Max, VIN
0.35
Min
Max
-80
-250
25
}LA
1.0
1.0
mA
0.45
V
0.50
2.0
=
0.35
0.80
2.0
-0.8
}LA
25
0.80
=
Units
Typ
V
V
-1.2
-0.8
-1.2
Ve
Input Clamp Voltage
Vee
CI
Input Capacitance
Vee = 5.0V, VIN = 2.0V
TA = 25'C,1 MHz
4.0
4.0
pF
Co
Output Capacitance
Vce = 5.0V. Va = 2.0V
T A = 25'C, 1 MHz, Outputs Off
6.0
6.0
pF
lee
Power Supply Current
Vee = Max, Inputs Grounded
All Outputs Open
75
los
Short Circuit
Output Current
Va = OV, Vee
(Note 2)
loz
Output Leakage
(TRI-STATE)
Vee = Max, Va
Chip Disabled
Output Voltage High
10H
VOH
Min, liN
=
-18 mA
Max
=
-20
2.4
100
mA
-70
mA
+50
+50
}LA
-50
-50
}LA
-70
0.45V to 2.4V
= -2.0mA
= - 6.5mA
100
75
-20
3.2
10H
Note 1: These limits apply over the entire operating range unless slated otherwise. All typical values are for Vee
V
V
~
2.4
3.2
S.Ov and TA ~ 2S'C.
V
Note 2: During los measurement. only one output at a time should be grounded. Permanent damage may otherwise result.
AC Electrical Characteristics with Standard Load and Operating Conditions
Symbol
JEDEC Symbol
DM54LS471
Parameter
Min
DM74LS471
Typ
Max
Min
Units
Typ
Max
TAA
TAVQV
Address Access Time
45
70
40
60
ns
TEA
TEVQV
Enable Access Time
15
35
15
30
ns
ns
TER
TEXQX
Enable Recovery Time
15
35
15
30
TZX
TEVQX
Output Enable Time
15
35
15
30
ns
TXZ
TEXQZ
Output Disable Time
15
35
15
30
ns
3-28
.------------------------------------------------------------------.0
3:
Functional Description
U1
TESTABILITY
TITANIUM-TUNGSTEN FUSES
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.
""
Ii)
""................
o
3:
~
Ii)
"".....
....
•
3-29
~National
~ Semiconductor
DM54/74S472
(512 x 8) 4096·Bit TTL PROM
General Description
Features
This Schottky memory is organized in the popular 512
words by 8 bits configuration. A memory enable input is provided to control the output states. When the device is enabled, the outputs represent the contents of the selected
word. When disabled, the 8 outputs go to the "OFF" or high
impedance state.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.
• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access down to--35 ns max
Enable access-25 ns max
Enable recovery-25 ns max
• PNP inpuls for reduced input loading
• All DC and AC parameters guaranteed over
temperature
• Low voltage TRI-SAFETM programming
• TRI-STATE® outputs
Block Diagram
AB
A7
A6
A5
AD
Al
4IJ96.BlT ARRAY
64x64
MEMORY MATRIX
Pin Names
AO-A8
Output Enable
A2----f
A3----t
A4----_tU~r_t~lr_tU~r_t~lr~~r_t~ur~~~~u
ii
ENABLE
BUFFER
Addresses
07
OB
05
Q4
03
02
01
00
TUD/9191-1
3-30
GND
Ground
00-07
Outputs
Vee
Power Supply
Connection Diagrams
Dual-In-Llne Package
Plastic Leaded Chip Carrier (PLCC)
'-"
11_1;1
AO- 1
Al- 2
A2- 3
~_o
20 ~Vcc
19 ~A8
3 2
!:loo
1 20 19
A3- 4
18 -A7
A3- 4
18 -A7
17 -A6
M-S
17 -A6
A4- 5
16 -AS
00- 6
16 -AS
00- 6
15
-G
01- 7
15
01- 7
14
~07
02- 8
14 -07
02- 8
03- 9
13 -06
9 10 11 12 13
12 -05
GND- 10
11-04
~ ~
o z:
'"
!
0
~0
-G
!
0
TL/D/9191-3
Top View
TL/D/9191-2
Top View
Order Number DM74S472V, 472AV, 472BV
See NS Package Number V20A
Order Number DM54174S472J, 472AJ, 472BJ
DM74S472N, 472AN, 472BN
See NS Package Number J20A or N20A
Ordering Information
Commercial Temp Range (O·C to
Parameter/Order Number
+ 70·C)
Max Access Time (ns)
DM74S472AN
45
DM74S472BN
35
DM74S472N
60
DM74S472AJ
45
DM74S472BJ
35
DM74S472J
60
DM74S472AV
45
DM74S472BV
35
DM74S472V
60
Military Temp Range (-'-55·C to
Parameter/Order Number
+ 125·C)
Max Access Time (ns)
DM54S472AJ
60
DM54S472BJ
50
DM54S472J
75
•
3-31
Absolute Maximum Ratings
Operating Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Note 2)
-0.5Vto +7.0V
Input Voltage (Note 2)
-1.2Vto +5.5V
Output Voltage (Note 2)
-0.5Vto +5.5V
Storage Temperature
- 65'C to + 150'C
Lead Temp. (Soldering, 10 seconds)
300'C
ESD to be determined
Min
Max
Units
Supply Voltage (Vecl
Military
Commercial
4.50
4.75
5.50
5.25
V
V
Ambient Temperature (TA)
Military
Commercial
-55
0
+125
+70
'c
Logical "0" Input Voltage
0
0.8
V
Logical "1" Input Voltage
2.0
5.5
V
'C
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may
be operated at these values.
Note 2: These limits do not apply during programming. For the programming
ratings, refer to the programming instructions.
DC Electrical Characteristics
Symbol
Parameter
(Note 1)
DM54S472
Conditions
Min
DM74S472
Typ
Max
-80
-250
Min
Units
Typ
Max
-80
-250
IlL
Input Load Current
Vee
= Max, VIN = 0.45V
IIH
Input Leakage Current
Vee
= Max, VIN = 2.7V
25
25
/LA
Vee
= Max, VIN = 5.5V
1.0
1.0
mA
Vee
= Min, 10L = 16 mA
0.45
V
0.80
V
-1.2
V
VOL
Low Level Output Voltage
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
Ve
Input Clamp Voltage
Vee
CI
Input Capacitance
Vee = 5.0V, VIN = 2.0V
TA = 25'C, 1 MHz
4.0
4.0
pF
Co
Output Capacitance
Vee = 5.0V, Va = 2.0V
T A = 25'C, 1 MHz, Outputs Off
6.0
6.0
pF
lee
Power Supply Current
Vee = Max, Input Grounded
All Outputs Open
110
los
Short Circuit
Output Current
Va = OV, Vee
(Note 2)
loz
Output Leakage
(TRI-STATE)
Vee = Max, Va
Chip Disabled
Output Voltage High
10H
= -2.0mA
10H
= - 6.5mA
VOH
0.35
0.50
0.35
/LA
0.80
2.0
= Min, liN = -18 mA
= Max
2.0
-0.8
-20
V
-0.8
155
110
155
mA
-70
mA
+50
+50
/LA
-50
-50
/LA
-70
= 0.45V to 2.4V
2.4
-1.2
-20
3.2
V
2.4
3.2
Note 1: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = 5.0V and TA = 25°C.
Note 2: During los measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
3-32
V
AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMP RANGE (O'C to
Symbol
TAA
JEDEC
Symbol
Parameter
TAVaV
+ 70'C)
DM74S472
Min
DM74S472A
Typ
Max
Address Access Time
40
Min
DM74S472B
Typ
Max
60
25
Min
Units
Typ
Max
45
25
35
ns
ns
TEA
TEVaV
Enable Access Time
15
30
15
30
15
25
TER
TEXaX
Enable Recovery Time
15
30
15
30
15
25
ns
TZX
TEVQX
Output Enable Time
15
30
15
30
15
25
ns
TXZ
TEXQZ
Output Disable Time
15
30
15
30
15
25
ns
MILITARY TEMP RANGE (-55'Cto
+ 125'C)
JEDEC
Symbol
Parameter
TAA
TAVQV
Address Access Time
TEA
TEVQV
Enable Access Time
15
TER
TEXQX
Enable Recovery Time
15
TZX
TEVQX
Output Enable Time
15
TXZ
TEXQZ
Output Disable Time
15
Symbol
DM54S472A
DM54S472
Min
DM54S472B
Max
25
60
35
15
35
15
35
ns
35
15
35
15
35
ns
35
15
35
15
35
ns
35
15
35
15
35
ns
Max
40
75
Min
Min
Typ
Max
25
50
Units
Typ
Typ
ns
Functional Description
TESTABILITY
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) andCERDIP
(J-package). Device performance in all package configurations is excellent.
TITANIUM-TUNGSTEN FUSES
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-Chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.
\
3-33
~National
~ Semiconductor
DM54S473/DM74S473
(512 x 8) 4096-Bit TTL PROM
General Description
Features
This Schottky memory is organized in the popular 512
words by S bits configuration. A memory enable input is provided to control the output states. When the device is enabled, the outputs represent the contents of the selected
word. When disabled, the S outputs go to the "OFF" or high
impedance state.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.
• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access-45 ns max
Enable access-30 ns max
Enable recovery--30 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over
temperature
• Low voltage TRI-SAFETM programming
• Open-collector outputs
Block Diagram
AS
A7
AU
A5
AD
At
4(J96.BtT ARRAY
64x64
MEMORY MATRIX
DECODER
A2
A3
A4
ENABLE
BUFFER
07
06
05
04
03
02
ot
00
TL/D/9715-1
Pin Names
AD-AS
Addresses
G
Output Enable
GND
Ground
00-07
Outputs
Vee
Power Supply
3-34
Connection Diagrams
Plastic Leaded Chip Carrier (PLCC)
Dual·ln·Une Package
AO- 1
20 >-Vcc
Al- 2
19 >-AB
A2- 3
lB >-A7
A3- 4
17 >-A6
A3- 4
lB I-A7
A4- 5
16 -AS
A4- 5
17 I- A6
QO- 6
IS
QO- 6
161-As
3
-G
Ql- 7
14 -Q7
Ql- 7
Q2- B
13 -Q6
Q2- B
Q3- 9
121-Qs
GND- 10
l11-Q4
2
1 20 19
IS I- G
14 f-Q7
9 10 11 12 13
!o
~z o
! o.!,
C>
.!.
0
TL/D/9715-3
TUD/9715-2
Top View
Top View
Order Number DM54174S473J, 473AJ,
DM74S473N or 473AN
See NS Package Number J20A or N20A
Order Number DM74S473V or 473AV
See NS Package Number V20A
Ordering Information
Commercial Temp. Range (O"C to
Parameter/Order Number
+ 70'C)
Max Access Time (ns)
DM74S473AN
45
DM74S473N
60
DM74S473AJ
45
DM74S473J
60
DM74S473AV
45
DM74S473V
60
Military Temp. Range (-SS'C to
Parameter/Order Number
+ 12S'C)
Max Access Time (ns)
DM54S473AJ
60
DM54S473J
75
•
3-35
Operating Conditions
Absolute Maximum Ratings (Note 1)
Supply Voltage (Note 2)
-0.5V to + 7.0V
Input Voltage (Note 2)
-1.2Vto +5.5V
Output Voltage (Note 2)
-0.5Vto +5.5V
Storage Temperature
-65'C to + 150'C
Lead Temp. (Soldering, 10 seconds)
300'C
ESD to be determined
Note 1: Absolute maximum ratings are those values beyond which the device may be permanenHy damaged. They do not mean that the device may
be operated at these values.
Note 2: These limits do not apply during programm!ng. For the programming
Min
Max
Units
Supply Voltage (Vecl
Military
Commercial
4.50
4.75
5.50
5.25
V
V
Ambient Temperature (TA)
Military
Commercial
-55
0
+125
+70
'C
'C
Logical "0" Input Voltage
Logical "1" Input Voltage
0
2.0
0.8
5.5
V
V
ratings, refer to the programming instructions.
DC Electrical Characteristics (Note 1)
Symbol
Parameter
Min
IlL
Input Load Current
IIH
Input Leakage Current
VOL
Low Level Output Voltage
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
loz
Output Leakage Current
(Open-Collector Only)
Ve
Input Clamp Voltage
C,
Input Capacitance
Co
Output Capacitance
=
=
Vee =
Vee =
= 0.45V
= 2.7V
Max, VIN = 5.5V
Min, 10L = 16 mA
Vee
Max, VIN
Vee
Max, VIN
DM74S473
DM54S473
Conditions
Typ
Max
-80
-250
Min
-80
-250
",A
25
",A
1.0
mA
0.45
V
1.0
0.50
0.35
0.80
2.0
2.0
= Max, VeEX = 2.4V
Vee = Max, VeEx = 5.5V
Vee = Min, liN = -18 mA
Vee = 5.0V, VIN = 2.0V
TA = 25'C, 1 MHz
Vee
Vee = 5.0V, Vo = 2.0V
TA = 25'C, 1 MHz, Outputs Off
0.80
-0.8
Power Supply Current
3-36
V
V
50
50
",A
100
100
",A
-1.2
V
-1.2
-0.8
4.0
4.0
pF
6.0
6.0
pF
Vee = Max, Input Grounded
110
155
All Outputs Open
Note 1: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = 5.0V and TA
lee
Max
25
0.35
Units
Typ
110
= 25'C.
155
mA
AC Electrical Characteristics
COMMERCIAL TEMP. RANGE (O'C to
with Standard Load and Operating Conditions
+ 70'C)
JEDEC
Symbol
Parameter
TAA
TAVQV
Address Access Time
40
60
25
45
ns
TEA
TEVQV
Enable Access Time
15
30
15
30
ns
Symbol
DM74S473
Min
Typ
DM74S473A
Max
Min
Typ
Units
Max
TER
TEXQX
Enable Recovery Time
15
30
15
30
ns
TZX
TEVQX
Output Enable Time
15
30
15
30
ns
TXZ
TEXQZ
Output Disable Time
15
30
15
30
ns
MILITARY TEMP. RANGE (-55'C to
+ 125'C)
JEDEC
Symbol
Parameter
TAA
TAVQV
TEA
TEVQV
TER
Symbol
DM54S473
DM54S473A
Typ
Max
Address Access Time
40
Enable Access Time
15
TEXQX
Enable Recovery Time
TZX
TEVQX
TXZ
TEXQZ
Units
Typ
Max
75
25
60
ns
35
15
35
ns
15
35
15
35
ns
Output Enable Time
15
35
15
35
ns
Output Disable Time
15
35
15
35
ns
Min
Min
Functional Description
TESTABILITY
TITANIUM-TUNGSTEN FUSES
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
National's Programmable Read-Only Memories (PROMs)
feature titanuim·tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERIP (Jpackage). Device performance in all package configurations
is excellent.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.
3-37
~National
~ Semiconductor
DM54/74S474
(512 x 8) 4096-Bit TTL PROM
General Description
Features
This Schottky memory is organized in the popular 512
words by 8 bits configuration. Memory enable inputs are
provided to control the output states. When the device is
enabled, the outputs represent the contents of the selected
word. When disabled, the 8 outputs go to the "OFF" or high
impedance state.
• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access-35 ns max
Enable access-25 ns max
Enable recovery-25 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over
temperature
• low voltage TRI-SAFETM programming
• TRI-STATE® outputs
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.
Block Diagram
AD
Al
A6
AS
A4
A3
«IIfl.BlTARRAY
I
64.64
Il4
MEMORY MATRIX
Pin Names
AO-A8
Addresses
G1, G2, G3, G4
Output Enables
GND
Ground
DECODER
A2
AI
AD
ill
in
63
64
ENABLE
GATE
07
06
05
Q4
03
01
02
00
TL/D/9714-1
3-38
NC
No Connection
00-07
Outputs
Vee
Power Supply
Connection Diagrams
Dual-In-Llne Package
'-"
Plastic Leaded Chip Carrier (PLCC)
U')co ..... u
t:iooo
A6- 2
24 t- vcc
23 t-A8
A5- 3
22 I-NC
A4- 5
25
A4- 4
21
Hi!
A3- 6
A3- 5
A2- 7
A2- 6
20 -G2
19 -G3
24 1-G2
23 I-G3
Al- 8
22 I-G4
Al- 7
18 -G4
AO- 9
211-NC
AO- 8
17 -07
NC- 10
20 t-07
00- 11
A7- 1
iii iii i
4
3
2
1 28 27 26
00- 9
16 -06
01- 10
15 -05
12 13 14 15 16 17 18
02- 11
14 -04
GND- 12
13 -03
!.a !.0 J,Z
'"
Hi!
19 t-06
~
! !
zoo
~
0
TL/D/9714-3
Top View
TUD/9714-2
Top View
Order Number DM74S474V, 474AV, 474BV
See NS Package Number V28A
Order Number DM54174S474J, 474AJ, 474BJ,
DM74S474N, 474AN, 474BN
See NS Package Number J24A or N24A
Ordering Information
Commercial Temp Range (O'C to
Parameter/Order Number
+ 70'C)
Military Temp Range (-55'C to
Max Access Time (ns)
DM745474AJ
45
Parameter/Order Number
DM545474AJ
+ 125'C)
Max Access Time (ns)
60
DM745474BJ
35
DM545474BJ
50
DM745474J
65
DM545474J
75
DM745474AN
45
DM745474BN
35
DM745474N
65
DM745474AV
45
DM745474BV
35
DM745474V
65
•
3-39
Absolute Maximum Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Note 2)
-0.5Vto +7.0V
Input Voltage (Note 2)
-1.2Vto +5.5V
Output Voltage (Note 2)
-0.5Vto +5.5V
- 65·C to + 150·C
Storage Temperature
Lead Temp. (Soldering, 10 seconds)
300·C
ESD to be determined
Note 1: Absolute maximum ratings are those values beyond which the de·
vice may be permanently damaged. They do not mean that the device may
be operated at these values.
Note 2: These limits do not apply during programming. For the programming
Min
Max
Units
Supply Voltage {Veel
Military
Commercial
4.50
4.75
5.50
5.25
V
V
Ambient Temperature (TA)
Military
Commercial
-55
0
+125
+70
·C
·C
Logical "0" Input Voltage
0
0.8
V
Logical "1" Input Voltage
2.0
5.5
V
ratings, refer to the programming instructions.
DC Electrical Characteristics
Symbol
Parameter
(Note 1)
DM54S474
Conditions
Min
IlL
Input Load Current
IIH
Input Leakage Current
VOL
Low Level Output Voltage
V,L
Low Level Input Voltage
V,H
High Level Input Voltage
Ve
Input Clamp Voltage
C,
Input Capacitance
Co
Output Capacitance
Icc
Power Supply Current
=
=
Vee =
Vee =
= 0.45V
= 2.7V
Max, V,N = 5.5V
Min,loL = 16 rnA
Vee
Max, VIN
Vee
Max, V,N
Max
-80
-250
0.35
Min
Max
-80
-250
= Min, liN = -18mA
Vee = 5.0V, V,N = 2.0V
TA = 25·C, 1 MHz
Vee = 5.0V, Vo = 2.0V
TA = 25·C, 1 MHz, Outputs off
Vee = Max, Inputs Grounded
/LA
1.0
1.0
rnA
0.45
V
0.80
V
0.50
0.35
2.0
-0.8
los
Short Circuit
Output Current
Vo = OV, Vee
(Note 2)
= Max
loz
Output Leakage
(TRI-STATE)
Vee = Max, Vo
Chip Disabled
Output Voltage High
IOH
V
6.0
6.0
pF
170
170
rnA
-70
rnA
+50
+50
/LA
-50
-50
/LA
-70
115
-20
3.2
2.4
Note 1: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee ~ 5.0V and TA ~
Nole 2: During los measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
3-40
-1.2
pF
= 0.45V to 2.4V
,
V
-0.8
4.0
115
2.4
-1.2
4.0
-20
= -2.0mA
IOH = -6.5mA
/LA
25
0.80
Vee
Units
Typ
25
2.0
All Outputs Open
VOH
DM74S474
Typ
V
3.2
25'C.
V
AC Electrical Characteristics
COMMERCIAL TEMP RANGE (O'C to
with Standard Load and Operating Conditions
+ 70'C)
JEDEC
Symbol
Parameter
TAA
TAVQV
Address Access Time
40
65
25
TEA
TEVQV
Enable Access Time
20
35
15
Symbol
DM74S474
Min
Typ
DM74S474A
Max
Min
Typ
DM74S474B
Units
Typ
Max
45
25
35
ns
25
15
25
ns
Max
Min
TER
TEXQX
Enable Recovery Time
20
35
15
25
15
25
ns
TZX
TEVQX
Output Enable Time
20
35
15
25
15
25
ns
TXZ
TEXQZ
Output Disable Time
20
35
15
25
15
25
ns
MILITARY TEMP RANGE (- 55'C to
+ 125'C)
JEDEC
Symbol
Parameter
TAA
TAVQV
Address Access Time
40
70
25
TEA
TEVQV
Enable Access Time
20
40
15
TER
TEXQX
Enable Recovery Time
20
40
15
35
TZX
TEVQX
Output Enable Time
20
40
15
TXZ
TEXQZ
Output Disable Time
20
40
15
Symbol
DM54S474
Min
Typ
DM54S474A
Max
Min
Typ
Max
DM54S474B
Min
Units
Typ
Max
60
25
50
35
15
35
ns
15
35
ns
35
15
35
ns
35
15
35
ns
ns
Functional Description
TESTABILITY
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.
TITANIUM-TUNGSTEN FUSES
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.
•
3-41
U) r-------------------------------------------------------------------------------~
.....
;.....
~NaHonal
:i
~
;
DM54/74S475 (512 x 8) 4096-Bit TTL PROM
C
......
U)
.....
Semiconductor
U)
:i
c
General Description
Features
This Schottky memory is organized in the popular 512
words by S bits configuration. Memory enable inputs are
provided to control the output states. When the device is
enabled, the outputs represent the contents of the selected
word. When disabled, the S outputs go to the "OFF" or high
impedance state.
• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access--down to 45 ns max
Enable access-25 ns max
Enable recovery-25 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over
temperature
• Low voltage TRI-SAFETM programming
• Open-collector outputs
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.
Block'Diagram
A8
A7
A6
A5
A4
A3
Pin Names
41116-BIT ARRAY
84x84
MEMORY MATRIX
AO-AS
Addresses
G1, G2, G3, G4
Output Enables
GND
Ground
AZ-----1
A l - - -....
NC
No Connection
AO----1
0 0- 0 7
Outputs
G1
Vee
Power Supply
ii2
G3
G4
ENABLE
GATE
07
06
05
04
03
02
01
00
TL/D/9192-1
3-42
Connection Diagrams
Plastic Leaded Chip Carrier (PLCC)
Dual·ln·Line·Package
A7- 1
'-./
A6- 2
IOU),....,U
24
8000
iii I I i I
-Vee
A5- 3
23 -A8
22 -NC
M-5
25 -G4
M-4
21 -G4
A3- 6
24
A3-5
20
-Gl
A2- 7
23 -G3
22 -Gl
4321282726
-Gl
A2- 6
19 -G3
Al- 8
Al- 7
18 -Gl
AO- 9
21 -NC
AO- 8
17 -Q7
NC- 10
20 -07
QO- 9
16 -Q6
QO- 11
Ql- 10
Q2- 11
15 -Q5
14 -Q4
GND- 12
13 -Q3
19 -Q6
12 13 14 15 16 17 18
TLlD/9192-3
Top View
TL/D/9192-2
Top View
Order Number DM74S475V or 475AV
See NS Package Number V28A
Order Number DM54174S475J, 475AJ,
DM74S475N or 475AN
See NS Package Number J24A or N24A
Ordering Information
Commercial Temp Range (O"C to
Parameter/Order Number
+ 70"C)
Max Access Time (ns)
DM74S475AJ
45
DM74S475J
65
DM74S475AN
45
DM74S475N
65
DM74S475AV
45
DM74S475V
65
Military Temp Range (- 55"C to
Parameter/Order Number
+ 125"C)
Max Access Time (ns)
DM54S475AJ
60
DM54S475J
75
3-43
Absolute Maximum Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Note 2)
-0.5Vto +7.0V
Input Voltage (Note 2)
-1.2Vto +5.5V
Output Voltage (Note 2)
-0.5Vto +5.5V
Storage Temperature
Lead Temperature (Soldering, 10 sec.)
(
-65·C to + 150·C
300·C
ESO rating to be determined.
Nole I: Absolute maximum ratings are those values beyond which the de·
vice may be permanently damaged, They do not mean that the device may
Supply Voltage (Vee>'
Military
Commercial
Ambient Temperature (TAl
Military
Commercial
Logical "0" Input Voltage
Logic "1" Input Voltage
Min
Max
Units
4.50
4.75
5.50
5.25
V
V
-55
0
0
2.0
+125
+70
0.8
5.5
·C
·C
V
V
be operated at these values.
Nole 2: These limits do not apply during programming. For the programming
ratings, refer to the programming instructions.
DC Electrical Characteristics (Note 1)
Symbol
Parameter
DM54S475
Conditions
Min
DM74S475
Typ
Max
-80
-250
Min
Units
Typ
Max
-80
-250
IlL
Input Load Current
Vee = Max, VIN = 0.45V
IIH
Input Leakage Current
Vee = Max, VIN = 2.7V
25
25
p.A
Vee = Max, VIN = 5.5V
1.0
1.0
mA
0.45
V
0.80
V
50
p.A
100
p.A
-1.2
V
VOL
Low Level Output Voltage
Vee = Min, IOL = 16mA
0.35
0.35
0.50
0.80
p.A
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
loz
Output Leakage Current
(Open-COllector Only)
Ve
Input Clamp Voltage
Vee = Min, liN = -18 mA
CI
Input Capacitance
Vee = 5.0V, VIN = 2.0V
TA = 25·C, 1 MHz
4.0
4.0
pF
Co
Output Capacitance
Vee = 5.0V, Vo = 2.0V
T A = 25·C, 1 MHz, Outputs Off
6.0
6.0
pF
lee
Power Supply Current
Vee = Max, Inputs Grounded
All Outputs Open
115
2.0
2.0
100
Vee = Max, VeEX = 5.5V
-0.8
-1.2
Nole 1: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee
3-44
V
50
Vee = Max, VeEX = 2.4V
-0.8
170
~
5.0V and
115
TA
~
25'C,
170
mA
AC Electrical Characteristics (With Standard Load and Operating Conditions)
COMMERCIAL TEMP RANGE (O'C to
+ 70'C)
DM74S475
Symbol
JEDEC
Symbol
Parameter
TAA
TAVQV
Address Access Time
40
65
25
45
ns
TEA
TEVQV
Enable Access Time
20
35
15
25
ns
TER
TEXQX
Enable Recovery Time
20
35
15
25
ns
Tzx
TEVQX
Output Enable Time
20
35
15
25
ns
Txz
TEXQZ
Output Disable Time
20
35
15
25
ns
MILITARY TEMP RANGE (-WC to
Min
Typ
DM74S475A
Max
Min
Typ
Max
Units
+ 125'C)
Symbol
JEDEC
Symbol
Parameter
TAA
TAVQV
TEA
TEVQV
TER
DM54S475
DM54S475A
Max
Address Access Time
40
75
25
60
ns
Enable Access Time
20
40
15
35
ns
TEXQX
Enable Recovery Time
20
40
15
35
ns
Tzx
TEVQX
Output Enable Time
20
40
15
35
ns
Txz
TEXQZ
Output Disable Time
20
40
15
35
ns
Min
Typ
Units
Typ
Min
Max
Functional Description
TESTABILITY
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
RELIABILITY
As with all National products, the Ti:W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti:W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.
TITANIUM-TUNGSTEN FUSES
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti:W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.
3-45
o
r-.
~ ~NaHonal
i!i ~ Semiconductor
.....
o
rn DM54/748570
~ (512 x 4) 2048-Bit TTL PROM
Q
General Description
Features
This Schottky memory is organized in the popular 512
words by 4 bits configuration. A memory enable input is provided to control the output states. When the device is enabled, the outputs represent the contents of the selected
word. When disabled, the 4 outputs go to the "OFF" or high
impedance state.
• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access down to-45 ns max
Enable access-25 ns max
Enable recovery-25 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over temperature
• Low voltage TRI-SAFETM programming
• Open-collector outputs
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.
Block Diagram
M
~--------------,
A7
204SIIIT ARRAY
64x32
MEMORY MATRIX
A6
A5
A4
Pin Names
AO-AB
A3
Addresses
G
Enable
A2------1
At------1
GND
Ground
AO------1l.!!!!U-i.!'.!'!..J--i.!!!!!!..J--l!~
00-03
Outputs
Vee
Power Supply
Q3
02
at
QO
TL/0/9189-1
3-46
C
3:
Connection Diagrams
UI
en
""
UI
Dual-In-Llne Package
......
Plastic Leaded Chip Carrier (PLCC)
C
......
\
A6- 1
\..../
C
3:
A5- 2
16 rVcc
15 rA7
A4- 3
14 rA8
M- 4
18 rA8
UI
A3- 4
13 rG
12 rQO
A3- 5
17rG
C
AO- 6
16
r
I- NC
AO- 5
3
2
......
""......en
1 20 19
QO
Al- 6
11 rQl
Al- 7
15
A2- 7
10 rQ2
A2- 8
14 rQl
GND- 8
9 rQ3
9 10 11 12 13
TL/D/9189-2
Top View
TL/D/9189-3
Top View
Order Number DM54174S570J, 570AJ
DM74S570N,570AN
See NS Package Number J16A or N 16A
Order Number DM74S570V, 570AV
See NS Package Number V20A
Ordering Information
Commercial Temp Range (O'C to
Parameter/Order Number
+ 70'C)
Max Access Time (ns)
DM74S570AN
45
DM74S570N
55
DM74S570AJ
45
DM74S570J
55
DM74S570AV
45
DM74S570V
55
Military Temp Range (-55'C to
Parameter/Order Number
+ 125'C)
Max Access Time (ns)
DM54S570AJ
60
DM54S570J
65
3-47
Absolute Maximum Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Note 2)
-0.5Vto +7.0V
Input Voltage (Note 2)
-1.2Vto +5.5V
Output Voltage (Note 2)
-0.5Vto +5.5V
Storage Temperature
- 65'C to + 150'C
Lead Temp. (Soldering, 10 seconds)
300'C
Min
Max
Units
Supply Voltage (Vee>
Military
Commercial
4.50
4.75
5.50
5.25
V
V
Ambient Temperature (TA)
Military
Commercial
-55
0
+125
+70
'C
'C
Logical "0" Input Voltage
0
0.8
V
Logical "1" Input Voltage
2.0
5.5
V
ESD to be determined
Note 1: Absolute Maximum Ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may
be operated at these values.
Note 2: These limits do not apply during programming. For the programming
ratings, refer to the programming instructions.
DC Electrical Characteristics (Note 1)
Symbol
Parameter
DM54S570
Conditions
Min
IlL
Input Load Current
Vee
IIH
Input Leakage Current
Vee
Vee
VOL
Low Level Output Voltage
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
loz
Output Leakage Current
(Open-Collector Only)
Ve
Input Clamp Voltage
CI
Input Capacitance
Co
Output Capacitance
Icc
Power Supply Current
Vee
=
=
=
=
= 0.45V
= 2.7V
Max, VIN = 5.5V
Min, IOL = 16 mA
Max, VIN
DM74S570
Typ
Max
-80
-250
Max, VIN
0.35
Min
Max
-80
-250
25
/LA
1.0
1.0
mA
0.45
V
0.80
V
50
/LA
100
/LA
-1.2
V
0.50
0.35
2.0
2.0
V
50
Vee
100
-0.8
/LA
25
0.80
= Max, VeEX = 2.4V
Vee = Max, VeEX = 5.5V
Vee = Min, liN = -18 mA
Vee = 5.0V, VIN = 2.0V
TA = 25'C,1 MHz
Vee = 5.0V, Vo = 2.0V
T A = 25'C, 1 MHz, Outputs Off
Vee = Max, Input Grounded
Units
Typ
-1.2
-0.8
4.0
4.0
pF
6.0
6.0
pF
90
130
All Outputs Open
Note 1: These limits apply over the entire operating range unless otherwise noted. All typical values are for Vee ~ 5.0V and TA
90
~
130
mA
25"C.
AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMP RANGE (O'C to + 70'C)
Symbol
JEDEC Symbol
DM74S570A
DM74S570
Parameter
Min
Typ
Max
Min
Typ
Units
Max
TAA
TAVaV
Address Access Time
40
55
30
45
TEA
TEVaV
Enable Access Time
20
30
15
25
ns
ns
TER
TEXaX
Enable Recovery Time
20
30
15
25
ns
TZX
TEVaX
Output Enable Time
20
30
15
25
ns
TXZ
TEXaZ
Output Disable Time
20
30
15
25
ns
MILITARY TEMP RANGE ( - 55'C to + 125'C)
Symbol
JEDEC Symbol
DM54S570
Parameter
Min
Typ
DM54S570A
Max
Min
Typ
Units
Max
TAA
TAVaV
Address Access Time
40
65
30
60
ns
TEA
TEVaV
Enable Access Time
20
35
15
35
ns
TER
TEXaX
Enable Recovery Time
20
35
15
35
ns
TZX
TEVaX
Output Enable Time
20
35
15
35
ns
TXZ
TEXaZ
Output Disable Time
20
35
15
35
ns
3-48
c
3:
Functional Description
U1
TESTABILITY
TITANIUM·TUNGSTEN FUSES
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.
3-49
.;..
en
.....
o
......
c
3:
.....
.;..
en
U1
.....
o
U1
.... r--------------------------------------------------------------------------------,
~
.... ~National
.....
.... ~ Semiconductor
~
It)
~
It)
~ DM54/74S571
~ '(512 x 4) 2048-Bit TTL PROM
General Description
Features
This Schottky memory is organized in the popular 512
words by 4 bits configuration. A memory enable input is provided to control the output states. When the device is enabled, the outputs represent the contents of the selected
word. When disabled, the 4 outputs go to the "OFF" or high
impedance state.
• Advanced titanium-tungsten (fi-W) fuses
• Schottky-clamped for high speed
Address access down to-35 ns max
Enable access-25 ns max
Enable recovery-25 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over temperature
• Low voltage TRI-SAFETM programming
• TRI-STATE® outputs
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.
Block Diagram
Pin Names
AB
A7
A6
A5
A4
A3
2!J48.BIT ARRAY
AD-AS
MEMORY MATRIX
G
Output Enable
GND
Ground
00-03
Outputs
Vee
Power Supply
64,32
A2----i
AI----i
AO------i
ENABLE
BUFFER
03
02
01
00
TUD/9713-1
3-50
Address
c
i:
Connection Diagrams
UI
~
rn
Dual-In-Llne Package
A6- 1
'-/
A5- 2
16
UI
.....
....
Plastic Leaded Chip Carrier (PLCC)
15 -A7
14 -A8
.....
~"'U 8"
"" z > ""
-Vee
A4- 3
......
I
3
I
2
~
UI
I I I
1 20 19
A4- 4
"3- 4
13
A3- 5
18 r-A8
17 r- G
"0- 5
12 -QO
"0- 6
16 rQO
"1- 6
ll-Ql
"1- 7
"2- 7
GND- 8
10 ~Q2
9 -Q3
"2- 8
15 r NC
14 r-Ql
-G
.....
....
9 10 11 12 13
~ z~ z
~o
~o
.!.
z
TUD/9713-2
C>
Top View
TL/D/9713-3
Top View
Order Number
DM54174S571J, 571AJ, 571BJ
DM74S571N, 571AN, 571BN
See NS Package Number J16A or N16A
Order Number
DM74S571V, 571AV, 571BV
See NS Package Number V20A
Ordering Information
Commercial Temperature Range (O'C to
Parameter/Order Number
+ 70'C)
Max Access Time (ns)
DM74S571AN
45
DM74S571BN
35
DM74S571N
55
DM74S571AJ
45
DM74S571BJ
35
DM74S571J
55
DM74S571AV
45
DM74S571BV
35
DM74S571V
55
MIlitary Temp. Range (- 55"C to
Parameter/Order Number
+ 125°C)
Max Access Time (ns)
DM54S571AJ
60
DM54S571BJ
50
DM54S571J
65
•
3·51
.........
II)
en
'<:I'
.....
"....
.....
II)
en
'<:I'
II)
::::i
Q
Absolute Maximum Ratings
Operating Conditions·
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Note 2)
Input Voltage (Note 2)
-1.2Vto +5.5V
Output Voltage (Note 2)
-0.5Vto +5.5V
Storage Temperature
Lead Temp. (Soldering 10 sec.)
Supply Voltage (Vee>
Military
Commercial
Ambient Temperature (TAl
Military
Commercial
- 65'C to + 150"C
Logical "0" Input Voltage
Logical "1" Input Voltage
300'C
ESD to be determined
Min
Max
Units
4.50
4.75
5.50
5.25
V
V
-55
0
+125
+70
0.8
5.5
'C
'C
V
0
2.0
V
Note 1: Absolute maximum ratings are those values beyond which the de·
vice may be permanently damaged. They do not mean that the device may
be operated at these values.
Note 2: These limits do not apply during programming. For the programming
ratings, refer to the programming instructions.
DC Electrical Characteristics (Note 1)
Symbol
Parameter
DM54S571
Conditions
Min
I,L
Input Load Current
I'H
Input Leakage Current
Vee
Vee
Vee
=
=
=
=
= 0.45V
Max, Y,N = 2.7V
Max, Y,N = 5.5V
Min,lOL = 16 rnA
Max, Y,N
DM74S571
Typ
Max
-80
-250
0.35
Min
Units
Typ
Max
-80
-250
",A
25
25
",A
1.0
1.0
rnA
0.45
V
0.80
V
0.50
0.35
VOL
Low Level Output Voltage
V,L
Low Level Input Voltage
V,H
High Level Input Voltage
Ve
Input Clamp Voltage
Vee
C,
Input Capacitance
Vee = 5.0V, Y,N = 2.0V
TA = 25'C, 1 MHz
4.0
4.0
pF
Co
Output Capacitance
Vee = 5.0V, Va = 2.0V
TA = 25'C, 1 MHz, Outputs Off
6.0
6.0
pF
lee
Power Supply Current
Vee = Max, Input Grounded
All Outputs Open
90
los
Short Circuit
Output Current
Va = OV, Vee = Max
(Note 2)
loz
Output Leakage
(TRI-STATE)
Vee = Max, Va
Chip Disabled
Output Voltage High
10H =-2.0mA
VOH
Vee
0.80
2.0
=
Min, liN
=
=
2.0
-0.8
-18 rnA
-20
2.4
-0.8
-1.2
-70
rnA
+50
+50
",A
-50
-50
",A
-20
V
10H = -6.5 rnA
2.4
= S.OV and TA
Note 2: Durtng los measurement, only one output at a time should be grounded. Permanent damage may otherwise resun.
3-52
V
rnA
90
3.2
Note 1: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee
-1.2
130
130
-70
0.45V to 2.4V
V
3.2
= 2S'e.
V
c
AC Electrical Characteristics
COMMERCIAL TEMP RANGE (O'C to
JEDEC
Symbol
Parameter
TAA
TAVQV
TEA
TEVQV
Symbol
U1
==
01:00
en
U1
+ 70'C)
Unit
....
......
......
en
U1
......
DM74S571
DM74S571A
Typ
Max
Address Access Time
40
55
30
Enable Access Time
20
30
15
Min
Min
Typ
DM74S571B
Typ
Max
45
30
35
ns
25
15
25
ns
Max
Min
01:00
TER
TEXQX
Enable Recovery Time
20
30
15
25
15
25
ns
TZX
TEVQX
Output Enable Time
20
30
15
25
15
25
ns
TXZ
TEXQZ
Output Disable Time
20
30
15
25
15
25
ns
MILITARY TEMP RANGE (- 55'C to
Symbol
..........
+ 125'C)
JEDEC
Symbol
Parameter
DM54S571
Min
Typ
DM54S571A
Max
Min
Typ
Max
DM54S571B
Min
Typ
Max
Unit
TAA
TAVQV
Address Access Time
40
65
30
60
30
50
ns
TEA
TEVQV
Enable Access Time
20
35
15
35
15
35
ns
TER
TEXQX
Enable Recovery Time
20
35
15
35
15
35
ns
TZX
TEVQX
Output Enable Time
20
35
15
35
15
35
ns
TXZ
TEXQZ
Output Disable Time
20
35
15
35
15
35
ns
Functional Description
TESTABILITY
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.
TITANIUM-TUNGSTEN FUSES
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit deSign is
optimized to provide high performance over the entire operating ranges of Vee and temperature.
3-53
•
....
~ r---------------------------------------------------------------------------~
~
r:! ~National
;;: ~
Lt)
Semiconductor
:!!
C
DM54/74S572
(1024 x 4) 4096-Bit TTL PROM
General Description
Features
This Schottky memory is organized in the popular 1024
words by 4 bits configuration. Memory enable inputs are
provided to control the output states. When the device is
enabled, the outputs represent the contents of the selected
word. When disabled, the 4 outputs go to the "OFF" or high
impedance state.
• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address acces~5 ns max
Enable access-25 ns max
Enable recovery-25 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over
temperature
• Low voltage TRI-SAFETM programming
• Open collector outputs
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.
Block Diagram
A9
AB
A7
A6
A5
A4
I
4O!J6.BIT ARRAY
64
MEMORY MATRIX
64164
Pin Names
A3-------r~~~_.~--~~~
A2------;
Al------;
M----~~~~~~~-U~
AO-A9
Addresses
Gl,G2
Output Enables
GND
Ground
00-03
Outputs
Vee
03
02
01
00
TL/0/9712-1
3-54
Power Supply
Connection Diagrams
Plastic Leaded Chip Carrier (PLCC)
Dual-In-Llne-Package
A6- 1
'-../
II')lDU
B"
"I "I I' 'I "I
A5- 2
18 ~Vcc
17 ~A7
A4- 3
16
~A8
A4-4
A3- 4
15
~A9
A3- 5
17 -A9
AO- 5
14
~OO
AO- 6
16 -00
Al- 6
13
~01
Al- 7
15 -NC
A2- 7
12
~02
A2- 8
Gi- 8
11
~03
GND- 9
10
I-GZ
3
2
1 20 19
18 -A8
14 -01
9 10 11 12 13
TL/D/9712-2
TL/D/9712-3
Top View
Top View
Order Number DM54174S572J, 572AJ,
DM74S572N, 572AN
See NS Package Number J18A or N18A
Order Number DM74S572V, 572AV
See NS Package Number V20A
Ordering Information
Commercial Temp Range (O'C to
Parameter/Order Number
+ 70'C)
Military Temp Range (-55'C to
Max Access Time (ns)
Parameter/Order Number
+ 125'C)
Max Access Time (ns)
DM74S572AJ
45
DM54S572AJ
60
DM74S572J
60
DM54S572J
75
DM74S572AN
45
DM74S572N
60
DM74S572AV
45
DM74S572V
60
•
3-55
Operating Conditions
(Note 1)
If Military/Aerospace specified devices are required,
Min
Max
Units
please contact the National Semiconductor Sales
Supply Voltage (Vee>
Office/Distributors for availability and specifications.
Military
4.50
5.50
V
-0.5 to +7.0V
Supply Voltage (Note 2)
4.75
5.25
V
Commercial
Input Voltage (Note 2)
-1.2Vto +5.5V
Ambient Temperature (TA)
-55
Output Voltage (Note 2)
-0.5V to + 5.5V
Military
+125
'C
Commercial
0
+70
'C
Storage Temperature
-65'Cto + 150'C
Logical "0" Input Voltage
0
0.8
V
Lead Temp. (Soldering, 10 sec.)
300'C
"1"
Input
Voltage
2.0
5.5
V
Logic
ESD to be determined
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated at
Absolute Maximum Ratings
these values.
Note 2: These limits do not apply during programming. For the programming ralings, refer to the programming instructions.
DC Electrical Characteristics (Note 1)
Symbol
Parameter
DM54S572
Conditions
Min
IlL
Input Load Current
Vee = Max, VIN = 0.45V
IIH
Input Leakage Current
Vee = Max, VIN = 2.7V
VOL
Low Level Output Voltage
Vee = Min,lOL = 16 mA
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
loz
Output Leakage Current
Vee = Max, VCEX = 2.4V
DM74S572
Typ
Max
-80
-250
Min
Max
-80
-250
p.A
25
p.A
1.0
mA
0.45
V
25
Vee = Max, VIN = 5.5V
1.0
0.35
0.50
0.35
0.80
2.0
Units
Typ
0.80
2.0
V
V
50
50
p.A
100
p.A
-1.2
V
(Open-Collector Only)
Vee = Max, VeEx = 5.5V
Ve
Input Clamp Voltage
Vee = Min,IIN = -18 mA
CI
Input Capacitance
Vee = 5.0V, VIN = 2.0V
TA = 25'C, 1 MHz
4.0
4.0
pF
Co
Output Capacitance
Vce = 5.0V, Vo = 2.0V
TA = 25'C, 1 MHz, Outputs Off
6.0
6.0
pF
100
-0.8
-1.2
Vee = Max, Input Grounded
100
140
All Outputs Open
Note 1: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = S.OV and TA
Icc
-0.8
Power Supply Current
3-56
100
=
+ 2S'e.
140
mA
AC Electrical Characteristics
COMMERCIAL TEMP RANGE (O'C to
(With Standard Load and Operating Conditions)
+ 70'C)
DM74S572
Symbol
DM74S572A
JEDEC Symbol
Parameter
TAA
TAVQV
Address Access Time
40
TEA
TEVQV
Enable Access Time
20
TER
TEXQX
Enable Recovery Time
20
35
MILITARY TEMP RANGE (-55'C to
Min
Typ
Max
60
25
45
ns
35
15
25
ns
15
25
ns
Min
+ 125'C)
DM54S572
Symbol
Units
Typ
Max
JEDEC Symbol
Parameter
TAA
TAVQV
TEA
TEVQV
TER
TEXQX
Min
DM54S572A
Min
Typ
Max
Units
Typ
Max
Address Access Time
40
75
25
60
Enable Access Time
20
45
15
35
ns
Enable Recovery Time
20
45
15
35
ns
ns
Functional Description
TESTABILITY
TITANIUM-TUNGSTEN FUSES
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for .guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.
3-57
~National
~
Semiconductor
DM54/74S573
(1024 x 4) 4096-Bit TTL PROM
General Description
Features
This Schottky memory is organized in the popular 1024
words by 4 bits configuration. Memory enable inputs are
provided to control the output states. When the device is
enabled, the outputs represent the contents of the selected
word. When disabled, the 4 outputs go to the "OFF" or high
impedance state.
• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access-down to 35 ns max
Enable access-25 ns max
Enable recovery-25 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over
temperature
• Low voltage TRI-SAFETM programming
• TRI-STATE® Outputs
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.
Block Diagram
A9
A8
A7
A6
A5
A4
4096-81T ARRAY
64x64
MEMORY MATRIX
I
64
Pin Names
A3------~7_~~~~~~~~
A2-----I
AI-----I
AO----~~~~~~~~~~
03
02
01
00
TLlD/9193-1
3-58
AO-A9
Addresses
G1-G2
Output Enables
GND
Ground
00-03
Outputs
Vee
Power Supply
Connection Diagrams
Dual-In-Line Package
Plastic Leaded Chip Carrier (PLCC)
\,J
~ :;: ~ ~ ~
AO- 1
Al- 2
A2- 3
20 ~Vcc
19 ~A8
18 ~A7
A3- 4
18
~A7
M- 5
~A6
~A5
00- 6
17
16
151-G
14 ~07
01- 7
02- 8
17
16
00- 6
03- 9
GND- 10
I I I
1 20 19
~A6
A3- 4
M- 5
01- 7
02- 8
I I
3 2
13
~06
12
11
~05
~A5
15 ~G
14
~07
9 10 11 12 13
~ ::z:
~
C1
~04
<.:>
!
C1
~
C1
!
CJ
TL/D/9193-3
Top View
TUD/9193-2
Top View
Order Number
DM74S573V, 573AV, 573BV
See NS Package Number V20A
Order Number
DM54/74S573J, 573AJ, 573BJ
DM74S573N, 573AN, 573BN
See NS Package Number J18A or N18A
Ordering Information
Commercial Temp Range (O·C to
Parameter/Order Number
+ 70·C)
Max Access Time (ns)
DM74S573AJ
45
DM74S573BJ
35
DM74S573J
60
DM74S573AN
45
DM74S573BN
35
DM74S573N
60
DM74S573AV
45
DM74S573BV
35
DM74S573V
60
Military Temp Range (-55·C to
Parameter/Order Number
+ 125·C)
Max Access Time (ns)
DM54S573AJ
60
DM54S573BJ
50
DM54S573J
75
•
3-59
Operating Conditions
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Note 2)
-0.5Vto +7.0V
-1.2Vto +5.5V
Input Voltage (Note 2)
Output Voltage (Note 2)
-0.5Vto +5.5V
Storage Temperature
-65'Cto +150'C
Lead Temp. (Soldering, 10 seconds)
3000C
Nota 1: Absolute maximum ratings are those values beyond which the de·
vice may be permanently damaged. They do not mean that the device may
be operated at these value•.
Note 2: The.. limit. do not apply during programming. For the programming
ratings, refer to the programming instructions.
Supply Voltage (Vee)
Military
Commercial
Ambient Temperature (TA)
Military
Commercial
Logical "0" Input Voltage
Logical "1" Input Voltage
Min
Max
Units
4.50
4.75
5.50
5.25
V
V
-55
0
0
2.0
+125
+70
0.8
5.5
'c
'C
V
V
DC Electrical Characteristics (Note 1)
Symbol
Parameter
DM54S573
Conditions
Min
DM74S573
Typ
Max
-80
-250
Min
Units
Typ
Max
-80
-250
IlL
Input Load Current
Vee = Max, VIN = 0.45V
)J.A
IIH
Input Leakage Current
Vee = Max, VIN = 2.7V
25
25
)J.A
Vee = Max, VIN = 5.5V
1.0
1.0
rnA
0.45
V
0.80
V
VOL
Low Level Output Voltage
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
Ve
Input Clamp Voltage
Vee = Min, liN = -18 rnA
CI
Input CapaCitance
Vee = 5.0V, VIN = 2.0V
TA = 25'C, 1 MHz
4.0
4.0
pF
Co
Output CapaCitance
Vee = 5.0V, Vo = 2.0V
TA = 25'C, 1 MHz, Outputs Off
6.0
6.0
pF
lee
Power Supply Current
Vee = Max, Input Grounded
All Outputs Open
100
los
Short Circuit
Output Current
Vo = OV, Vee = Max
(Note 2)
loz
Output Leakage
(TRI·STATE)
Vee = Max, Vo = 0.45V to 2.4V
Chip Disabled
Output Voltage High
10H = -2.0 rnA
VOH
0.35
Vee = Min, 10L = 16 rnA
0.50
0.35
0.80
2.0
2.0
-0.8
-20
2.4
-1.2
V
-0.8
140
mA
-70
mA
+50
+50
)J.A
-50
-50
)J.A
-20
3.2
3.2
10H = - 6.5 rnA
2.4
Note 1: These limits apply over the entire operating range unless stated otherwise. All typical value. are for Vee = 5.0V and TA = 25·C.
Nota 2: During los measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
3·60
V
140
-70
100
-1.2
V
V
AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMP RANGE (O'C to
Symbol
+ 70'C)
JEDEC
Symbol
Parameter
DM74S573A
DM74S573
Min
Typ
Max
Min
Typ
Max
DM74S573B
Min
Typ
Max
Units
TAA
TAVaV
Address Access Time
40
60
25
45
25
35
TEA
TEVaV
Enable Access Time
20
35
15
25
15
25
ns
TER
TEXaX
Enable Recovery Time
20
35
15
25
15
25
ns
TZX
TEVQX
Output Enable Time
20
35
15
25
15
25
ns
TXZ
TEXQZ
Output Disable Time
20
35
15
25
15
25
ns
MILITARY TEMP RANGE (-55'C to
Symbol
ns
+ 125'C)
JEDEC
Symbol
Parameter
DM54S573
Min
Typ
DM54S573A
Max
Min
Typ
Max
DM54S573B
Min
Typ
Max
Units
TAA
TAVQV
Address Access Time
40
75
25
60
25
50
TEA
TEVQV
Enable Access Time
20
45
15
35
15
35
ns
ns
TER
TEXQX
Enable Recovery Time
20
45
15
35
15
35
ns
TZX
TEVQX
Output Enable Time
20
45
15
35
15
35
ns
TXZ
TEXQZ
Output Disable Time
20
45
15
35
15
35
ns
Functional Description
TESTABILITY
TITANIUM-TUNGSTEN FUSES
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.
3-61
~National
~ Semiconductor
DM77/87S 180, DM77/87S280
(1024 x 8) 8192-Bit TTL PROMs
General Description
Features
These Schottky memories are organized in the popular
1024 words by 8 bits configuration. Memory enable inputs
are provided to control the output states. When the device
is enabled, the outputs represent the contents of the selected word. When disabled, the 8 outputs go to the "OFF" or
high impedance state.
• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address acces~5 ns max
Enable access-30 ns max
Enable recovery-30 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over
temperature
• Low voltage TRI-SAFETM programming
• Open-collector outputs
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.
Block Diagram
A5
A4
A3
A2
Al
AD
Pin Names
8192·BIT ARRAY
64 x 12B
MEMORY MATRIX
AD-AS
A6-------r~~~~~~~~~~~~_r~r_~~~~,
A7-------j
AB-----;
A8------~~~~~~~~~~~~~~w-~~~~~
ii1
G2
63
64
ENABLE
GATE
07
.06
05
04
03
02
01
00
TL/D/9716-1
3-62
Addresses
GT, <32, G3, G4
Output Enables
GND
Ground
00-07
Outputs
Vee
Power Supply
c
5:
Connection Diagrams
......
......
en
Dual·ln·Llne·Package
A7- 1
'-"
....
Plastic Leaded Chip Carrier (PLCC)
~U)r-.u
OC)
o
.....
H:i!:CJ)
c
iiiiiii
A5- 3
24 I-Vcc
23 r-A8
22 r-A9
A4- 4
21 r-G4
A2- 7
A3- 5
20 r-G1
Al- 8
A2- 6
19 I-G3
MJ-9
22 - G2
21-NC
NC- 10
20 -07
Al- 7
181-(;2
00- 11
AO- 8
171-Q7
12 13 14 15 16 17 18
~
....
QO- 9
16 I-Q6
.!.o O
.!. a:,
zooo
o
.....
Ql- 10
Q2- 11
15 r-Q5
14 r-Q4
Top View
GND- 12
13 I-Q3
Order Number DM87S180V
See NS Package Number V28A
A6- 2
4
3
2
5:
......
......
1 28 27 26
A4- 5
25 -G4
A3-6
24 - iii
23 -G3
en
N
OC)
o
.....
c
5:
OC)
19 -06
~
OC)
.!, !. .!,
TL/D/9716-3
TLlD/9716-2
c
5:
OC)
~
N
OC)
o
Top View
Order Number DM77/87S180J, 280J
DM87S180N,280N
See NS Package Number J24A, J24F, N24A or N24C
Ordering Information
Commercial Temp Range (O'C to
Parameter/Order Number
24·Pin
Standard DIP
24·Pin
Narrow DIP
X
X
X
DM87S180J
DM87S180N
DM87S180V
DM87S280N
Military Temp Range (-55'C to
Parameter/Order Number
24·Pin
Standard DIP
55
55
55
55
+ 125'C)
24·Pin
Narrow DIP
X
Max Access
Time (ns)
75
X
DM77S280J
Max Access
Time (ns)
55
X
X
DM87S280J
DM77S180J
+ 70'C)
75
•
3-63
Absolute Maximum Ratings
Operating Conditions
(Note 1)
If MIlitary/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Note 2)
-0.5Vto +7.0V
Input Voltage (Note 2)
-1.2Vto +5.5V
Output Voltage (Note 2)
-0.5Vto +5.5V
Storage Temperature
- 65'C to + 150'C
Lead Temp. (Soldering, 10 seconds)
300'C
ESD to be determined
Note 1: Absolute maximum ratings are those values beypnd which the de·
vice may be permanently damaged. They do not mean that the device may
be operated at these values.
Note 2: These limits do not apply during programming. For the programming
ratings, refer to the programming instructions.
Min
Max
Units
Supply Voltage (Vee>
Military
Commercial
4.50
4.75
5.50
5.25
V
V
Ambient Temperature (TA)
Military
Commercial
-55
0
+125
+70
'C
'C
Logical "0" Input Voltage
0
0.8
V
Logical "1" Input Voltage
2.0
5.5
V
DC Electrical Characteristics (Note 1)
Symbol
Parameter
DM77S180
DM77S280
Conditions
Min
DM87S180
DM87S280
Typ
Max
-80
-250
Min
Units
Typ
Max
-80
-250
IlL
Input Load Current
Vee = Max, VIN = 0.45V
IIH
Input Leakage Current
Vee = Max, VIN = 2.7V
25
25
/LA
Vee = Max, VIN = 5.5V
1.0
1.0
mA
0.45
V
0.80
V
VOL
Low Level Output Voltage
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
loz
Output Leakage Current
(Open·Coliector Only)
0.35
Vee = Min,lOL = 16 mA
0.50
0.35
0.80
2.0
2.0
/LA
V
Vee = Max, VeEX = 2.4V
50
50
/LA
Vee = Max, VeEX = 5.5V
100
100
/LA
-1.2
V
-0.8
-1.2
-0.8
Ve
Input Clamp Voltage
Vee = Min,IIN = -18 mA
CI
Input Capacitance
Vee = 5.0V, VIN = 2.0V
TA = 25'C, 1 MHz
4.0
4.0
pF
Co
Output Capacitance
Vee = 5.0V, Vo = 2.0V
TA = 25'C, 1 MHz, Outputs Off
6.0
6.0
pF
Power Supply Current
Vee = Max, Input Grounded
115
170
All Outputs Open
Note 1: These lim"s apply over the entire operating range unless stated otherwise. All typical values are for Vee = 5.0V and TA
lee
3·64
115
= 25'C.
170
mA
AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMP RANGE (O'C to
Symbol
+ 70'C)
JEDEC Symbol
DM87S180
DM87S280
Parameter
Min
Units
Typ
Max
TAA
TAVaV
Address Access Time
40
55
ns
TEA
TEVaV
Enable Access Time
15
30
ns
TER
TEXaX
Enable Recovery Time
15
30
ns
MILITARY TEMP RANGE (-55'C to
+ 125'C)
DM77S180
DM77S280
Symbol
JEDEC Symbol
Parameter
Typ
Max
TAA
TAVaV
Address Access Time
40
75
ns
TEA
TEVaV
Enable Access Time
15
35
ns
TER
TEXaX
Enable Recovery Time
15
35
ns
Min
Units
Functional Description
TESTABILITY
TITANIUM-TUNGSTEN FUSES
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is deSigned to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamiC high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.
3-65
.r--------------------------------------------------------------------------------,
CD
~
::E
Q
.....
.-
~National
~ Semiconductor
CD
.DM77/87S181,DM77/87S281
~ (1024 x 8) 8192-Bit TTL PROMs
::E
Q
.....
.-
~....
:IE
....
.CD
.-
Q
re....
::E
General Description
Features
These Schottky memories are organized in the popular
1024 words by 8 bits configuration. Memory enable inputs
are provided to control the output states. When the device
is enabled, the outputs represent the contents of the selected word. When disabled, the 8 outputs go to the "OFF" or
high impedance state.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.
• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access---45 ns max
Enable acces~O ns max
Enable recovery-30 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over
temperature
• Low voltage TRI-SAFETM programming
• TRI-STATE® outputs
Q
Block Diagram
A5
A4
A3
1
8192-81T ARRAY
A2
Al
AD
64
MEMORY MAmlX
64 x 128
Pin Names
AO-A9
Addresses
G1, G2, G3, G4
Output Enables
A7-------I
GND
Ground
AB-----1
00-07
Outputs
Gf
Vee
Power Supply
A5------~~_r~~~_r;_~r;~~~_r_r~~~,
~------~~~~~~~~~~~~~~~~~~~~
iii"
G3
G4
07
06
05
Q4
03
02
01
DO
TL/D/9194-1
3-66
C
:!:
.....
~
.....
Q)
.....
......
Connection Diagrams
Dual-In-Line Package
A7- 1
\.J
Plastic Leaded Chip Carrier (PLCC)
A5- 3
M- 5
M- 4
211-G4
A3- 6
A3- 5
20 I-Gi
A2- 7
A6- 2
It)
co
.....
4
3
2
0
t!
00
'"
i i i I L_ii
24 f-Vcc
23 rA8
22 rA9
C
l5:
1 28 27 26
25 rG4
24 rGi
23 I-G3
.....
.....
en
N
Q)
.....
......
A2- 6
191-G3
Al- 8
22 I-Gi
C
Al- 7
18 f-Gi
AO- 9
21 I- NC
Q)
AO- 8
17 f-07
NC- 10
20 f-07
00- 9
16 f-06
00- 11
19 f- 06
Ol- IO
15 r05
12 13 14 15 16 17 18
02- 11
GND- 12
14 1-04
13 1-03
o
~ 0~
!
Z
'"
~
Z
0
Order Number DM87S181V
See NS Package Number V28A
Ordering Information
Commercial Temp Range (DOC to
Parameter/Order Number
DM87S181AJ
24-Pin
Standard DIP
+ 7DOC)
24-Pin
Narrow DIP
Max Access
Time (ns)
DM87S181J
X
X
55
DM87S181AN
X
45
DM87S181N
X
X
55
DM87S181V
45
55
DM87S281AJ
X
45
DM87S281J
X
X
55
DM87S281AN
DM87S281N
X
55
Military Temp Range (- 55°C to
Parameter/Order Number
24-Pin
Standard DIP
45
+ 125°C)
24-Pin
Narrow DIP
Max Access
Time (ns)
DM77S181AJ
X
65
DM77S181J
X
75
X
X
DM77S281AJ
DM77S281J
3-67
Q)
.....
TL/D/9194-3
Top View
Order Number DM77/87S181J, 281J, 181AJ, 281AJ,
DM87S181N, 281N, 181AN, 281AN
See NS Package Number J24A, J24F, N24A or N24C
l5:
0
Top View
TL/D/9194-2
65
75
~
.....
Q)
.....
......
C
! ! !
C1
l5:
en
N
Q)
.....
Absolute Maximum Ratings
Operating Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Note 2)
-0.5Vto +7.0V
Input Voltage (Note 2)
-1.2Vto +5.5V
Output Voltage (Note 2)
-0.5V to + 5.5V
-65·C to + 150"C
Storage Temperature
300·C
Lead Temp. (Soldering, 10 seconds)
Supply Voltage (Vee>
Military
Commercial
Ambient Temperature (TA)
Military
Commercial
Logical "0" Input Voltage
Logical "1" Input Voltage
ESD to be determined.
Note 1: Absolute maximum ratings are those values beyond which the davice may be permanently damaged. They do not mean that the device may
Min
Max
Units
4.50
4.75
5.50
5.25
V
V
-55
0
0
2.0
+125
+70
0.8
5.5
·C
·C
V
V
be operated at these values.
Note 2: These limits do not apply during programming. For the programming
ratings. refer to the programming Instructions.
DC Electrical Characteristics (Note 1)
Symbol
Parameter
DM77S181
DM77S281
Conditions
Min
DM87S181
DM87S281
Typ
Max
-80
-250
Min
Units
Typ
Max
-80
-250
IlL
Input Load Current
Vee = Max, VIN = 0.45V
IIH
Input Leakage Current
Vee = Max, VIN = 2.7V
25
25
/LA
Vee = Max, VIN = 5.5V
1.0
1.0
rnA
0.45
V
0.80
V
VOL
Low Level Output Voltage
Vee = Min, 10L = 16 rnA
0.35
0.50
0.35
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
Ve
Input Clamp Voltage
Vee = Min, liN = -18 mA
CI
Input Capacitance
Vee = 5.0V, VIN = 2.0V
TA = 25·C,1 MHz
4.0
4.0
pF
Co
Output Capacitance
Vee = 5.0V, Vo = 2.0V
TA = 25·C, 1 MHz, Outputs Off
6.0
6.0
pF
Icc
Power Supply Current
Vee = Max, Input Grounded
All Outputs Open
115
los
Short Circuit
Output Current
Vo = OV, Vee = Max
(Note 2)
loz
Output Leakage
(TRI-STATE)
Vee = Max, Vo = 0.45V to 2.4V
Chip Disabled
Output Voltage High
10H = -2.0mA
VOH
0.80
/LA
2.0
2.0
-0.8
-20
2.4
-1.2
170
-1.2
V
170
mA
-70
mA
+50
+50
/LA
-50
-50
/LA
-70
115
-20
3.2
2.4
10H = - 6.5mA
Note 1: These limits apply over the entire operating range unless slated otherwise. All typical values are for Vee = S.OV and TA =
Note 2: During los measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
3-68
V
-0.8
V
3.2
2S'C.
V
C
3:
.....
AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMP RANGE (O'C to
Symbol
JEDEC Symbol
DM87S181
DM87S281
Parameter
Min
TAA
~
....
+ 70'C)
....
......
co
DM87S181A
DM87S281A
Typ
Max
Min
Units
Typ
Max
TAVQV
Address Access Time
40
55
35
45
ns
TEA
TEVQV
Enable Access Time
15
30
15
30
ns
TER
TEXQX
Enable Recovery Time
15
30
15
30
ns
TZX
TEVQX
Output Enable Time
15
30
15
30
ns
TXZ
TEXQZ
Output Disable Time
15
30
15
30
ns
MILITARY TEMP RANGE (- 55'C to
Symbol
+ 125'C)
JEDEC Symbol
C
3:
.....
~
PI)
co
....
......
C
3:
co
~
....
....
......
co
c
DM77S181
DM77S281
Parameter
Min
3:
co
DM77S181A
DM77S281A
Typ
Max
Min
Units
Typ
Max
~
PI)
....co
TAA
TAVQV
Address Access Time
40
75
35
65
ns
TEA
TEVQV
Enable Access Time
15
35
15
35
ns
TER
TEXQX
Enable Recovery Time
15
35
15
35
ns
TZX
TEVQX
Output Enable Time
15
35
15
35
ns
TXZ
TEXQZ
Output Disable Time
15
35
15
35
ns
Functional Description
TESTABILITY
TITANIUM-TUNGSTEN FUSES
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanenlly fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.
•
3-69
~
....co
r-------------------------------------------------------------------------------------,
~National
Ie
co
::::IE
c
~
Semiconductor
~
co
.... DM77/87S184
Ie (2048 x 4) 8192-Bit TTL PROM
I'
::::IE
c
General Description
Features
This Schottky memory is organized in the popular 2048
words by 4 bits configuration. A memory enable input is provided to control the output states. When the device is enabled, the outputs represent the contents of the selected
word. When disabled, the 4 outputs go to the "OFF" or high
impedance state.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.
• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access-55 ns max
Enable access-25 ns max
Enable recovery-25 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over
temperature
• Low voltage TRI-SAFETM programming
• Open·collector outputs
Block Diagram
A9
A8
A7
A6
8192·81T ARRAY
64x128
MEMORY MATRIX
A5
A4
Pin Names
Al0:=====~
Al-------1
A3
A2
Ao-------1
03
02
00
01
TUD/9717-1
3-70
AO-A10
Addresses
G
Output Enable
GND
Ground
QO-Q3
Outputs
Vee
Power Supply
Connection Diagrams
Plastic Leaded Chip Carrier (PLCC)
Dual·ln·Llne Package
"'100
A6- 1
18 .... Yee
g"
iii i i
A5- 2
17 .... A7
A4-3
16 -A8
A4- 4
18 -A8
A3- 4
15 -A9
A3- 5
17 .... A9
AO- 5
14 -00
AO- 6
16 -00
Al- 6
13 -01
AI-7
15-NC
A2- 8
A2-7
12 -02
Al0- 8
11 -03
GND- 9
10 -G
3
2
1 20 19
14 -01
9 10 11 12 13
TUD/9717-2
TL/D/9717 -3
Top View
Top View
Order Number DM77/87S184J,
184AJ or DM87S184N, 184AN
See NS Package Number J18A or N18A
Order Number DM87S184V, 184AV
See NS Package Number V20A
Ordering Information
Commercial Temp Range (O'C to
Parameter/Order Number
+ 70'C)
Max Acces Time (ns)
DM87S184AN
45
DM87S184N
55
DM87S184AJ
45
DM87S184J
55
DM87S184AV
45
DM87S184V
55
Military Temp Range (-55'C to
Parameter/Order Number
+ 125'C)
Max Acces Time (ns)
DM77S184J
70
DM77S184AJ
60
3-71
Absolute Maximum Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices sre required,
please contact the National Semiconductor Sales
OHlce/Dlstrlbutors for availability and specifications.
Supply Voltage (Note 2)
-0.5Vto +7.0V
-1.2Vto +5.5V
Input Voltage (Note 2)
Output Voltage (Note 2)
-0.5Vto +5.5V
Storage Temperature
- 65'C to + 150'C
Lead Temp. (Soldering, 10 seconds)
300'C
ESD to be dete'rmined.
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may
Supply Voltage (Vee)
Military
Commercial
Ambient Temperature (TA)
Military
Commercial
Logical "0" Input Voltage
Logical "1" Input Voltage
Min
Max
Units
4.50
4.75
5.50
5.25
V
V
-55
0
0
2.0
+125
+70
0.8
5.5
'C
'C
V
V
be operated at these values.
Note 2: The.e limits do not apply during programming. For the programming
ratings, refer to the programming instructions.
DC Electrical Characteristics (Note 1)
Symbol
Parameter
Min
IlL
Input Load Current
IIH
Input Leakage Current
VOL
Low Level Output Voltage
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
loz
Output Leakage CUrrent
(Open-Collector Only)
Ve
Input Clamp Voltage
CI
Input Capacitance
Co
Output Capacitance
lee
Power Supply Current
=
Vee =
Vee =
Vee =
Vee
DM87S184
DM77S184
Conditions
= 0.45V
Max, VIN = 2.7V
Max, VIN = 5.5V
Min, IOL = 16 mA
Max, VIN
Typ
Max
-80
-250
0.35
Min
Max
-80 '
-250
25
p.A
1.0
1.0
mA
0.50
0.35
V
V
50
p.A
100
p.A
-1.2
V
V
50
100
-0.8
-1.2
-0.8
4.0
4.0
pF
6.0
6.0
pF
100
140
100
All Outputs Open
Nole 1: These limits apply over the entire operetlng range unle.. otherwise noted. All typical values are for Vee = 5.0V and TA = 25°C.
3-72
0.45
0.80
2.0
2.0
Vee
p.A
26
0.80
= Max, VeEX = 2.4V
Vee = Max, VeEx = 5.5V
Vee = Min, liN = -18 mA
Vee = 5.0V, VIN = 2.0V
TA = 25'C,1 MHz
Vee = 5.0V, Vo = 2.0V
TA = 25'C, 1 MHz, Outputs Off
Vee = Max, Input Grounded
Units
Typ
140
mA
AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMP RANGE (O'C to
+ 70'C)
JEDEC
Symbol
Parameter
TAA
TAVQV
TEA
TER
Symbol
DM87S184A
Typ
Max
Address Access Time
40
TEVQV
Enable Access Time
TEXQX
Enable Recovery Time
MILITARY TEMP RANGE (-55'Cto
Units
Typ
Max
55
30
45
ns
15
25
15
25
ns
15
25
15
25
ns
Min
+ 125'C)
JEDEC
Symbol
Parameter
TAA
TAVQV
Address Access Time
TEA
TEVQV
TER
TEXQX
Symbol
DM87S184
Min
DM77S184
DM77S184A
Typ
Max
40
Enable Access Time
Enable Recovery Time
Min
Units
Typ
Max
70
30
60
ns
15
30
15
30
ns
15
30
15
30
ns
Min
Functional Description
TESTABILITY
TITANIUM-TUNGSTEN FUSES
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional cirCUitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-Chip programming circuit.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.
3-73
U)
co
r--------------------------------------------------------------------------------,
~ ~National
i!i ~ Semiconductor
u;
~
~
c
DM77/87S 185
(2048 x 4) 8192-Bit TTL PROM
General Description
Features
This Schottky memory is organized in the popular 2048
words by 4 bits configuration. A memory enable input is provided to control the output states. When the device is enabled, the outputs represent the contents of the selected
word. When disabled, the 4 outputs go to the "OFF" or high
impedance state.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.
• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access-35 ns max
Enable access-25 ns max
Enable recovery-25 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over
temperature
• Low voltage TRI-SAFETM programming
• TRI-STATEIIi> outputs
Block Diagram
A9
A8
A7
8192·8IT ARRAY
64 x 128
MEMORY MATRIX
A6
A5
A4
Pin Names
A3
A1D~§
A2
AD -----------1
Al
03
02
00
01
TLlD/9197-1
3-74
AO-A10
Addresses
G
Output Enable
GND
Ground
00-03
Outputs
Vee
Power Supply
c
Connection Diagrams
.......
==
Dual-In-Line-Package
A6 A5 A4 -
1
U
3
171- A7
3
co
1r ¥ f r
lSI- Vee
2
....~
Plastic Leaded Chip Carrier (PLCC)
16 I- AS
2
UI
......
C
==
co
1 20 19
A4- 4
18 -A8
~
....
A3- 5
17 -A9
UI
A3 -
4
15 I- A9
AO- 6
16 -QO
AD -
5
14 I- 00
Al- 7
15 -NC
Al -
6
13 I-
Q1
A2- 8
A2 -
7
12 -
02
Al0 -
S
11 -
03
GNU -
9
10
co
14 -Ql
9 10 11 12 13
-6
TLID19197 -3
Top View
Order Number DM87S185V, 185AV, 185BV
See NS Package Number V20A
TL/D/9197-2
Top View
Order Number DM77/87S185J, 185AJ, 185BJ
DM87S185N, 185AN, 185BN
See NS Package Number J18A or N18A
Ordering Information
Commercial Temp Range (O"C to
Parameter/Order Number
+ 70'C)
Military Temp Range (-55'C to
Max Access Time (ns)
Parameter/Order Number
+ 125'C)
Max Access Time (ns)
60
DM87S185AJ
45
DM77S185AJ
DM87S185BJ
35
DM77S185BJ
50
DM87S185J
55
DM77S185J
70
DM87S185AN
45
DM87S185BN
35
DM87S185N
55
DM87S185AV
45
DM87S185BV
35
DM87S185V
55
•
3-75
Absolute Maximum Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Note 2)
-0.5Vto +7.0V
-1.2Vto +5.5V
Input Voltage (Note 2)
Output Voltage (Note 2)
- 0.5V to + 5.5V
Storage Temperature
-65'Cto +150'C
Lead Temp. (Soldering, 10 seconds)
300'C
ESD to be determined
Note 1: Absolute maximum ratings are those values beyond which the de·
vice may be permanently damaged. They do not mean that the device may
be operated at these values.
Supply Voltage (Vecl
Military
Commercial
Ambient Temperature (TAl
Military
Commercial
Logical "0" Input Voltage
Logical "1" Input Voltage
Min
Max
Units
4.50
4.75
5.50
5.25
V
V
-55
0
0
2.0
+125
+70
0.8
5.5
'C
'C
V
V
Note 2: These limits do not apply during programming. For the programming
ratings, refer to the programming instructions.
DC Electrical Characteristics (Note 1)
Symbol
Parameter
DM77S185
Conditions
Min
IlL
Input Load Current
IIH
Input Leakage Current
VOL
Low Level Output Voltage
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
Ve
Input Clamp Voltage
CI
Input Capacitance
Co
Output Capacitance
lee
Power Supply Current
=
=
Vee =
Vee =
= 0.45V
= 2.7V
Max, VIN = 5.5V
Min, 10L = 16 mA
Vee
Max, VIN
Vee
Max, VIN
DM87S185
Typ
Max
-80
-250
0.35
Min
Max
-80
-250
25
/LA
1.0
1.0
mA
0.45
V
0.80
V
0.50
0.35
2.0
2.0
= Min, liN = -18 mA
Vee = 5.0V, VIN = 2.0V
TA = 25'C, 1 MHz
Vee = 5.0V, Vo = 2.0V
TA = 25'C, 1 MHz, Outputs Off
Vee = Max, Input Grounded
-0.8
los
Short Circuit
Output Current
Vo = OV, Vee
(Note 2)
= Max
loz
Output Leakage
(TAl-STATE)
Vee = Max, Vo
Chip Disabled
VOH
Output Voltage High
10H
= 0.45Vt02.4V
= -2.0mA
-1.2
-1.2
V
4.0
pF
6.0
6.0
pF
140
100
140
mA
-20
-70
-20
-70
mA
-50
+50
-50
+50
/LA
2.4
3.2
2.4
10H = - 6.5mA
Note 1: These limits apply over the entire operating range unless otherwise noted. All typical values are for Vee = S.OV and TA =
Note 2: During los measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
3-76
V
-0.8
4.0
100
All Outputs Open
/LA
25
0.80
Vee
Units
Typ
V
3.2
2S'C.
V
AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMP RANGE (O'C to
+ 70'C)
DM87S185
DM87S185A
Symbol
JEDEC
Symbol
Parameter
TAA
TAVQV
Address Access Time
40
55
30
TEA
TEVQV
Enable Access Time
15
25
15
TER
TEXQX
Enable Recovery Time
15
25
15
25
TZX
TEVQX
Output Enable Time
15
25
15
TXZ
TEXQZ
Output Disable Time
15
25
15
MILITARY TEMP RANGE (-55'C to
Min
Typ
Max
Min
Typ
DM87S185B
Units
Typ
Max
45
25
35
25
15
25
ns
15
25
ns
25
15
25
ns
25
15
25
ns
Max
Min
ns
+ 125'C)
DM77S185
Symbol
JEDEC
Symbol
Parameter
TAA
TAVQV
TEA
TEVQV
TER
TZX
TXZ
Min
DM77S185A
Min
Typ
Typ
Max
Address Access Time
40
70
30
Enable Access Time
15
30
15
TEXQX
Enable Recovery Time
15
30
15
TEVQX
Output Enable Time
15
30
15
TEXQZ
Output Disable Time
15
30
15
DM77S185B
Units
Typ
Max
60
25
50
ns
30
15
30
ns
30
15
30
ns
30
15
30
ns
30
15
30
ns
Max
Min
Functional Description
TESTABILITY
TITANIUM·TUNGSTEN FUSES
The Schottky PROM-die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.
3-77
•
~National
~
Semiconductor
DM77/87SR474
(512 x 8) 4k-Bit Registered TTL PROM
General Description
The DM77/87SR474 is an electrically programmable
Schottky TTL read-only memory with D-type, master-slave
registers on-chip. This device is organized as 512 words by
8-bits and is available in the TRI-STATE® output version.
Designed to optimize system performance, this device also
substantially reduces the cost and size of pipelined microprogrammed systems and other designs wherein accessed
PROM data is temporarily stored in a register. The
DM77/87SR474 also offers maximal flexibility for memory
expansion and data bus control by providing both synchronous and asynchronous output enables. All outputs will go
into the "OFF" state if the synchronous chip enable (GS) is
high before the rising edge of the clock, or if the asynchronous chip enable (G) is held high. The outputs are enabled
when GS is brought low before the rising edge of the clock
and G is held low. The GS flip-flop is designed to power up
to the "OFF" state with the application of Vee.
The DM77/87SR474 also features an initialize function,
INIT. The initialize function provides the user with an extra
word of programmable memory which is accessed with single pin control by applying a low on INIT. The initialize function is synchronous and is loaded into the output register on
the next rising edge of the clock. The unprogrammed state
of the INIT is all lows, providing a CLEAR function when not
programmed.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions. Once programmed, it is impossible to go back to a low.
Features
• On-Chip, edge-triggered registers
• Synchronous and asynchronous enables for word
expansion
• Programmable synchronous register INITIALIZE
• 24-pin, 300 mil thin-DIP package
• 35 ns address setup and 20 ns clock to output for maximum system speed
• Highly reliable, titanium tungsten fuses
• TRI-STATE outputs
• Low voltage TRI-SAFETM programming
• All parameters guaranteed over temperature
• Pinout compatible with DM77SR181 (lk x 8) Registered
PROM for future expansion
Data is read from the PROM by first applying an address to
inputs AO-A8. During the setup time the output of the array
is loaded into the master flip-flop of the data register. During
the rising edge (low to high transition) of the clock, the data
is then transferred to the slave of the flip-flop and will appear on the output if the output is enabled. Following the
rising edge clock transition the addresses and synchronous
chip enable can be removed and the output data will remain
stable.
Block Diagram
"
"
"
"
"...
Pin Names
64 WORD ,,64·BIT
PROGRAMM.lBLE FUSE ARRAY
"
"
AO-A8
Addresses
C
Clock
G
Output Enable
GND
Ground
GS
Synchronous
Output Enable
IN IT
Initialize
'0
lIiIT--D.......-D..,.,J
iii
01
..
.5
..
.
,
.3
.
TLl0/9201-1
3-78
NC
No Connection
QO-Q7
Outputs
Vee
Power Supply
Connection Diagrams
Dual-In-line-Package
A7- 1A6- 2
'-.../
Plastic Chip Carrier (PlCC)
It)CD
......
U
~DOU
iii iii i
24 f-Vcc
23 f-A8
4321282726
A5- 3
22 I-NC
A4-5
251-G
M-4
A3- 5
21Hl
20 I-INITS
A3 - 6
A2-7
24 f- INITS
231-GS
22f-C
21 .... NC
A2- 6
19H1s
Al-8
Al- 7
18 f-C
AO- 9
AO- 8
17 f-07
NC- 10
00- 9
16 f-06
00- 11
01- 10
15 f-05
02- 11
14 1-04
13 1-03
GND- 12
20 f-07
19 .... 06
12 13 14 15 16 17 18
TL/D/9201-3
Top View
TL/D/9201-2
Top View
Order Number DM87SR474V, 474BV
See NS Package Number V28A
Order Number DM77/87SR474J, 474BJ
DM87SR474N,474BN
See NS Package Number J24A or N24A
Ordering Information
Commercial Temp Range (D'C to
Parameter/Order Number
+ 70'C)
Military Temp Range (- 55'C to
Min Address to ClK
Setup Time (ns)
Parameter/Order Number
+ 125'C)
Min Address to ClK
Setup Time (ns)
DM87SR474BJ
35
DM77SR474BJ
40
DM87SR474J
50
DM77SR474J
55
DM87SR474BN
35
DM87SR474N
50
DM87SR474BV
35
DM87SR474V
50
•
3-79
Absolute Maximum Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Note 2)
-0.5Vto +7.0V
Input Voltage (Note 2)
-1.2Vto +5.5V
Output Voltage (Note 2)
-0.5Vto +5.5V
Storage Temperature
-65·C to + 150·C
300·C
Lead Temp. (Soldering, 10 seconds)
Supply Voltage (Veal
Military
Commercial
Ambient Temperature (TA)
Military
Commercial
Logical "0" Input Voltage
Logical "1" Input Voltage
ESD to be determined.
Min
Max
Units
4.50
4.75
5.50
5.25
V
V
-55
0
0
2.0
+125
+70
0.8
5.5
·C
·C
V
V
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may
be operated at these values.
Note 2: These limits do not apply during programming. For the programming
ratings, refer to the programming Instructions.
DC Electrical Characteristics (Note 1)
Symbol
Parameter
DM77SR474
Conditions
Min
DM87SR474
Typ
Max
-80
-250
Min
Units
Typ
Max
-80
-250
IlL
Input Load Current
Vee = Max, VIN = 0.45V
IIH
Input Leakage Current
Vee = Max, VIN = 2.7V
25
25
p.A
Vee = Max, VIN = 5.5V
1.0
1.0
mA
0.45
V
0.80
V
0.35
VOL
Low Level Output Voltage
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
Ve
Input Clamp Voltage
Vee = Min, liN = -18 mA
CI
Input Capacitance
Vee = 5.0V, VIN = 2.0V
TA = 25·C, 1 MHz
4.0
4.0
pF
Co
Output Capacitance
Vee = 5.0V, Va = 2.0V
T A = 25·C, 1 MHz, Outputs Off
6.0
6.0
pF
Icc
Power Supply Current
Vee = Max, Inputs Grounded
All Outputs Open
135
los
Short Circuit
Output Current
Va = OV, Vee = Max
(Note 2)
-20
-70
loz
Output Leakage
(TRI-STATE)
Vee = Max, Vo = 0.45V to 2.4V
Chip Disabled
-50
+50
VOH
Output Voltage High
10H = -2.0mA
2.4
Vee = Min, 10L = 16 mA
0.50
0.35
p.A
0.80
2.0
2.0
-0.8
V
-1.2
-0.8
185
135
mA
-20
-70
mA
-50
+50
p.A
V
2.4
~
5.0V and TA
Note 2: During los measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
3-80
V
185
3.2
10H = - 6.5mA
Note 1: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee
-1.2
3.2
~
25'C.
V
Switching Characteristics
tS(A)
Address to C (High)
Setup Time
DM87SR474
DM77SR474
Parameter
Symbol
I SR474
I SR4748
Min
Typ
55
Max
Min
Typ
20
50
20
40
20
35
20
Units
Max
ns
tH(A)
Address to C (High) Hold Time
0
-5
0
-5
ns
tS(lNITS)
INITS to C (High) Setup Time
30
20
25
20
ns
tH(INITS)
INITS to C (High) Hold Time
0
-5
0
-5
tpHL(C)
tpLH(C)
Delay from C (High)
to Output (High or Low)
tWH(C)
tWL(C)
C Width (High or Low)
tS(GS)
I SR474
I
SR4748
ns
15
30
15
27
15
25
15
20
ns
25
13
20
13
ns
GS to C (High) Setup Time
10
0
10
0
ns
tH(GS)
GS to C (High) Hold Time
5
0
5
0
ns
tpZL(C)
tpZH(C)
Delay from C (High)
to Output Active (High or Low)
20
35
20
30
ns
tpZL(G)
tpZH(G"j
Delay from G (Low)
to Output Active (High or Low)
15
30
15
25
ns
tpLZ(C)
tpHZ(C)
Delay from C (High)
to Output Inactive (TRI-STATE)
20
35
20
30
ns
tpLZ(G)
tpHZ(G)
Delay from G (Low)
to Output Inactive (TRI-STATE)
15
30
15
25
ns
Functional Description
TESTABILITY
TITANIUM-TUNGSTEN FUSES
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each Chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy 8
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vcc and temperature.
3-81
•
~National
~
Semiconductor
DM77/87SR476
(512 x 8) 4k-Bit Registered TTL PROM
General Description
The DM77/87SR476 is an electrically programmable
Schottky TTL read-only memory with D-type, master-slave
registers on-chip. This device is organized as 512 words by
8-bits and is available in the TRI-STATE@ output version.
Designed to optimize system performance, this device also
substantially reduces the cost and size of pipelined microprogrammed systems and other designs wherein accessed
PROM data is temporarily stored in a register. The
DM77/87SR476 also offers maximal flexibility for memory
expansion and data bus control by providing both synchronous and asynchronous output enables. All outputs will go
into the "OFF" state if the synchronous chip enable (GS) is
high before the rising edge of the clock, or if the asynchronous chip enable (G) is held high. The outputs are enabled
when GS is brought low before the rising edge of the clock
and G is held low. The GS flip-flop is designed to power up
to the "OFF" state with the application of Vee.
Data is read from the PROM by first applying an address to
inputs AO-A8. During the setup time the output of the array
is loaded into the master flip-flop of the data register. During
the rising edge (low to high transition) of the clock, the data
is then transferred to the slave of the flip-flop and will appear on the output if the output is enabled. Following the
rising edge clock transition the addresses and synchronous
chip enable can be removed and the output data will remain
stable.
The DM77SR476 also features an initialize function, INIT.
The initialize function provides the user with an extra word
of programmable memory which is accessed with single pin
control by applying a low on INIT. The initialize function is
asynchronous and is loaded into the output register when
INIT is brought low. The unprogrammed state of the INIT is
all lows PS loads ones into the output registers when
brought low.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions. Once programmed, it is impossible to go back to a low.
Features
• Functionally compatible with AM27S25
• On-Chip, edge-triggered registers
• Synchronous and asynchronous enables for word expansion
• Programmable asynchronous INITIALIZE
• 24-pin, 300 mil thin-dip package
• 35 ns address setup and 20 ns clock to output for
maximum system speed
• Highly reliable, titanium tungsten fuses
• TRI-STATE outputs
• Low voltage TRI-SAFETM programming
• All parameter's guaranteed over temperature
• Preset input
Block Diagram
64 WORD
Pin Names
x 64 BIT
PROGRAMMABLE FUSE ARRAY
AO-A8
INii' _.£><_-----1
PS
-1>0-------1
m
~
~
~
00
m
m
~
TL/0/9202-1
3-82
Addresses
C
Clock
G
Output Enable
GND
Ground
GS
Synchronous
Output Enable
INIT
Initialize
PS
Preset
00-07
Outputs
Vee
Power Supply
Connection Diagrams
Dual·ln·line Package
Plastic Chip Carrier (PlCC)
'-.../
~ ~ ~ ~ ~ !:ll~
A7- 1
24
-Vee
A6- 2
23 -A8
-iiS
A5- 3
22
A4- 4
21-G
I
I
I
I
4
3
2
1 28 27 26
I
I
I
G
M- 5
25 r-
A3- 6
24 r-INIT
A2- 7
23 r-
Al- 8
22 r-C
Gs
A3- 5
20 -INIT
A2-6
19
-cs
Al- 7
18
-c
AO- 9
21 f- NC
AO- 8
17 -Q7
NC- 10
20l-Q7
QO- 9
16 -Q6
15 -Q5
QO- 11
Ql- 10
Q2- 11
19
I- Q6
12 13 14 15 16 17 18
14 -Q4
13 -Q3
GND- 12
TL/D/9202-3
Top View
TLlD/9202-2
Top View
Order Number DM87SR476V or 476BV
See NS Package Number V28A
Order Number DM77/87SR476J, 476BJ,
DM87SR476N or 476BN
See NS Package Number J24A or N24A
Ordering Information
Commercial Temp Range (O'C to
Parameter/Order Number
+ 70'C)
Min Address to
ClK Setup Time
DM87SR476BJ
35
DM87SR476J
50
DM87SR476BN
35
DM87SR476N
50
DM87SR476BV
35
DM87SR476V
50
Military Temp Range (- 55'C to
Parameter/Order Number
+ 125'C)
Min Address to
ClK Setup Time
DM77SR476BJ
40
DM77SR476J
55
•
3-83
Absolute Maximum Ratings
Operating Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Note 2)
-0.5Vto +7.0V
Input Voltage (Note 2)
-1.2Vto +5.5V
Output Voltage (Note 2)
-0.5Vto +5.5V
Storage Temperature
-65'Cto + 150'C
Lead Temperature (Soldering, 10 sec.)
300'C
ESD to be determined
Note 1: Absolute Maximum Ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may
be operated at these values
Note 2: These limits do not apply during programming. For the programming
Min
Max
Units
Supply Voltage (Vee)
Military
Commercial
4.50
4.75
5.50
5.25
V
V
Ambient Temperature (TA)
Military
Commercial
-55
0
+125
+70
'C
'C
Logical "0" Input Voltage
0
0.8
V
Logical "1 " Input Voltage
2.0
5.5
V
ratings, refer to the programming instructions.
DC Electrical Characteristics (Note 1)
Symbol
Parameter
DM77SR476,476B
Conditions
Min
Typ
Max
-80
-250
DM87SR476, 476B
Min
Typ
Max
-80
-250
Units
IlL
Input Load Current
Vee = Max, VIN = 0.45V
IIH
Input Leakage Current
Vee = Max, VIN = 2.7V
25
25
/LA
Vee = Max, VIN = 5.5V
1.0
1.0
mA
0.45
V
VOL
Low Level Output Voltage
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
0.35
Vee = Min, 10L = 16 mA
0.50
0.35
0.80
2.0
0.80
2.0
-0.8
-1.2
/LA
V
V
Ve
Input Clamp Voltage
Vee = Min, liN = -18 mA
CI
Input Capacitance
Vee = 5.0, VIN = 2.0V
TA = 25'C, 1 MHz
-0.8
4.0
4.0
pF
Co
Output Capacitance
Vee = 5.0V, Va = 2.0V
TA = 25'C, 1 MHz, Outputs Off
6.0
6.0
pF
lee
Power Supply Current
Vee = Max, Input Grounded
All Outputs Open
135
los
Short Circuit
Output Current
Va = OV, Vee = Max
(Note 2)
-20
-70
loz
Output Leakage
(TRI-STATE)
Vee = Max, Va = 0.45V to 2.4V
Chip Disabled
-50
+50
VOH
Output Voltage High
10H = -2.0mA
2.4
mA
-20
-70
mA
-50
+50
/LA
135
3.2
10H = - 6.5mA
2.4
3.2
Note 1: These limits apply over the entire operating range unless stated othelWise. Aillypical values are for Vee = 5.0V and TA = 25'C.
3-84
V
185
185
Note 2: During los measurements, only one output at a time should be grounded. Permanent damage may otherwise result.
-1.2
V
V
Switching Characteristics
Symbol
tS(A)
DM77SR476,476B
Parameter
Address to C (High) Setup Time
I SR476
I SR476B
tH(A)
Address to C (High) Hold Time
tpHL(C)
tpLH(C)
Delay from C (High) to Output
(High or Low)
tWH(C)
tWL(C)
C Width (High or Low)
!gIGS)
tH(GS)
tpLH(PS)
Delay from PS (Low) to Output (High)
tpLH(lNIT)
tpHL(iNm
Delay from INIT (Low) to Output (Low or High)
tWL(PS)
PS Pulse Width (Low)
Min
Typ
Max
DM87SR476,476B
Min
Typ
55
20
50
20
40
20
35
20
0
-5
0
-5
I SR476
I SR476B
Units
Max
ns
ns
15
30
15
27
15
25
15
20
ns
25
13
20
13
ns
GS to C (High) Setup Time
10
0
10
0
ns
GS to C (High) Hold Time
5
0
5
0
ns
20
40
20
30
ns
20
40
20
30
ns
15
10
15
10
ns
tWL(iNi'i')
INIT Pulse Width (Low)
15
10
15
10
tS(PS)
PS Recovery (High) to C (High)
25
10
20
10
ns
tSCiNl'i'l
INIT Recovery (High) to C (High)
25
10
20
10
ns
tpZL(C)
tpZH(C)
Delay from C (High) to Active Output
(High or Low)
20
35
20
30
ns
tpZL(G)
tPZi-I(G) .
Delay from G (Low) to Active Output
(High or Low)
15
30
15
25
ns
tpZL(C)
tpHZ(C)
Delay from C (High) to Inactive Output
(TRI-STATE)
20
35
20
30
ns
tpZL(G)
tpHZ(G)
Delay from G (High) to Inactive Output
(TRI-STATE)
15
30
15
25
ns
Functional Description
TESTABILITY
TITANIUM-TUNGSTEN FUSES
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of VCC and temperature.
3-85
r-.
N
a:
~
co
:!!
C
r----------------------------------------------------------------------------,
~National
~
Semiconductor
;::
a: DM77/87SR27
N
~
r-.
(512 x 8) 4k-Bit Registered TTL PROM
:!!
C
General Description
rising edge clock transition the addresses and synchronous
chip enable can be removed and the output data will remain
stable.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions. Once programmed, it is impossible to go back to a low.
The DM77 /87SR27 is an electrically programmable
Schottky TTL read-only memory with D-type, master-slave
registers on-chip. This device is organized as 512 words by
8 bits and is available in the TRI-STATE® output version.
Designed to optimize system performance, this device also
substantially reduces the cost and size of pipelined microprogrammed systems and other designs wherein accessed
PROM data is temporarily stored in a register. The
DM77 /87SR27 also offers maximal flexibility for memory
expansion and data bus control by providing both synchronous and asynchronous output enables. All outputs will go
into the "OFF" state if the synchronous chip enable (GS) is
high before the rising edge of the clock, or if the asynchronous chip enable (G) is held high. The outputs are enabled
when GS is brought low before the rising edge of the clock
and G is held low. The GS flip-flop is designed to power up
to the "OFF" state with the application of Vee.
Features
• Functionally compatible with Am27S27
• On-chip, edge-triggered registers
• Synchronous and asynchronous enables for word expansion
• 22-pin 400-mil thin-DIP package
• 35 ns address setup and 20 ns clock to output for maximum system speed
• Highly reliable, titanium tungsten fuses
• TRI-STATE outputs
• Low voltage TRI-SAFETM programming
• All parameters guaranteed over temperature
Data is read from the PROM by first applying an address to
inputs AO-A8. During the setup time the output of the array
is loaded into the master flip-flop of the data register. During
the rising edge (low to high transition) of the clock, the data
is then transferred to the slave of the flip-flop and will appear on the output if the output is enabled. Following the
Block Diagram
AD
A1
A2
A3
A4
1 OF 64
WORD
DECODER
64 WOROx64 BIT
PROGRAMMABLE FUSE ARRAY
Pin Names
A~
1 OF 8
BIT
DECODER
07
Q6
Q5
04
03
02
01
DO
TL/D/6688-1
3-86
AO-AS
Addresses
C
Clock
G
Output Enable
GND
Ground
GS
Synchronous
Output Enable
00-07
Outputs
Vee
Power Supply
.----------------------------------------------------------------------.0
3:
.......
Connection Diagram
.......
(J)
Dual-In-Llne Package
::II
N
~vcc
:::::!
A4.l
~A2
3:
Q)
A5..!
~A'
A6....!
~AD
A7.1
~ii
AS..!
rlLiiS
DD...l
lie
D'...!
~D7
DZ...!
.!!.Q6
Q3.l!!
.E.Q5
GNDJl
E.Q4
'-/
A3...l
o
~
::II
N
.......
TL/D/66B6-2
Top View
Order Number DM77/87SR27J, DM77/87SR27BJ,
DM87SR27N or DM87SR27BN
See NS Package Number J22A or N22A
Ordering Information
Commercial Temp Range (O'C to
+ 70'C)
Min Address to C
Setup Time (ns)
Parameter/Order Number
DM87SR27BJ
35
DM87SR27J
50
DM87SR27BN
35
DM87SR27N
50
Military Temp Range (-55'C to
+ 125'C)
Min Address to C
Setup Time (ns)
Parameter/Order Number
DM77SR27BJ
40
DM77SR27J
55
•
3-87
Absolute Maximum Ratings
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage {Vecl
Military
Commercial
Supply Voltage (Note 1)
-0.5Vto +7.0V
Input Voltage (Note 1)
-1.2Vto +5.5V
Output Voltage (Note 1)
-0.5Vto +5.5V
Ambient Temperature (TAl
Military
Commercial
Storage Temperature
Lead Temp. (Soldering, 10 sec.)
-65·Cto +150·C
300·C
4.5Vto 5.5V
4.75V to 5.25V
- 55·C to + 125·C
O·Cto +70·C
Logical "0" Input Voltage
OVto O.BV
Logical "1" Input Voltage
2.0Vto 5.5V
ESD rating to be determined.
Note: Absolute maximum ratings indicate limits beyond which permanent
damage may occur. Continuous operation at these limits is not intended;
operations should be limited to those conditions specified under DC Electri-
cal Characteristics.
DC Electrical Characteristics TA =
Symbol
Parameter
25·C, Vee = 5.0V unless otherwise specified
DM77SR27
Test Conditions
Min
DM87SR27
Typ
Max
-80
-250
Min
Units
Typ
Max
-80
-250
IlL
Input Load Current
Vee = Max, VIN = 0.45V
IIH
Input Leakage Current
Vee = Max, VIN = 2.7V
25
25
/LA
Vee = Max, VIN = 5.5V
1.0
1.0
mA
VOL
Low Level Output Voltage
VIL
Low Level Input Voltage
0.35
Vee = Min, 10L = 16 mA
0.50
0.35
O.BO
0.45
V
0.80
V
VIH
High Level Input Voltage
Ve
Input Clamp Voltage
Vee = Min, liN = -1B mA
CI
Input Capacitance
Vee = 5.0V, VIN = 2.0V
TA = 25·C,1 MHz
4.0
4.0
pF
Co
Output Capacitance
Vee = 5.0V, Va = 2.0V
T A = 25·C, 1 MHz, Outputs Off
6.0
6.0
pF
Icc
Power Supply Current
Vee = Max, Inputs Grounded
All Outputs Open
135
los
Short Circuit
Output Current
Va = OV, Vee = Max
(Note 2)
loz
Output Leakage
(TRI-STATE)
Vee = Max, Va = 0.45Vt02.4V
Chip Disabled
Output Voltage High
IOH = -2.0mA
VOH
2.0
/LA
2.0
-O.B
-20
2.4
-1.2
-1.2
V
185
mA
-70
mA
+50
+50
/LA
-50
-50
/LA
185
-70
135
-20
V
3.2
IOH = -6.5mA
2.4
Note 1: These limits do not apply during programming. For the programming ratings, refer to the programming instructions.
Note 2: During los measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
3-BB
V
-O.B
3.2
V
o
......
......
:!i:
Switching Characteristics
Symbol
DM77SR27
Parameter
Min
tS(A)
Address to C
(High) Setup Time
Typ
en
DMB7SR27
Max
Min
Typ
SR27
55
20
50
20
SR27B
40
20
35
20
0
-5
0
-5
Units
Max
N
......
......
o
ns
:!i:
co
ns
::xl
......
tH(A)
Address to C (High) Hold Time
tpHL(C)
tPLH(C)
Delay from C (High)
to Output (High or Low)
tWH(C)
tWL(C)
C Width (High or Low)
tS(GS)
tH(GS)
tpZL(C)
tpZH(C)
Delay from C (High)
to Active Output (High or Low)
20
35
20
30
ns
tpZL(G)
tpZH(G)
Delay from G (Low)
to Active Output (Low or High)
15
30
15
25
ns
tpLZ(C)
tPHZ(C)
Delay from C (High)
to Inactive Output (TRI-STATE)
20
35
20
30
ns
tPLZ(G)
tpHZ(G)
Delay from G (High)
to Inactive Output (TRI-STATE)
15
30
15
25
ns
en
N
SR27
15
30
15
27
SR27B
15
25
15
20
ns
25
13
25
13
ns
GS to C (High) Setup Time
10
0
10
0
ns
GS to C (High) Hold Time
5
0
5
0
ns
Programming Parameters
Symbol
::xl
......
Do not test or you may program the device
Parameter
Vcep
Required Vee for Programming
leep
Icc During Programming
Vop
Required Output Voltage for Programming
lop
Output Current While Programming
IRR
Rate of Voltage Change of Vee or Output
Test
Conditions
Min
Recommended
Value
Max
Units
10
10.5
11
V
750
mA
10
10.5
Vee = l1V
VOUT = llV
1
11
V
20
mA
10
V/)J.s
PWE
Programming Pulse Width (Enabled)
9
10
11
)J.s
VeevL
Required Low Vee for Verification
3.8
4
4.2
V
VeeVH
Required High Vee for Verification
5.8
6
6.2
V
MDe
Maximum Duty Cycle for Vee at Veep
25
25
%
Functional Description
TITANIUM·TUNGSTEN FUSES
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high perform·
ance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-Chip programming circuit.
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges,of Vee and temperature.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
3-89
•
~ r---------------------------------------------------------------------------------~
N
a:
Ie
CD
::iii
C
j:::
N
a:
Ie
~
::iii
c
Functional Description
c) Select the output where a logical high is desired by
raising that output voltage to 10.5V (± 0.5V). Limit the
slew rate from 1.0 VI p.s to 10 VI""s. This voltage may
occur simultaneously with the increase in Vee, but
must not precede it. It is critical that only one output at
a time be programmed since the internal circuits can
only supply programming current to one bit at a time.
Outputs not being programmed must be left open or
connected to a high impedance source of 20 kO minimum. (Remember that the outputs of the device are
disabled at this time.)
(Continued)
TESTABILITY
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.
d) Enable the device by taking the chip Enable G to a low
level. This is done with a pulse of 10 p.s. The 10 p.s
duration refers to the time that the circuit (device) is
enabled. Normal input levels are used and rise and fall
times are not critical.
RELIABILITY
e) Verify that the bit has been programmed by first removing the programming voltage from the output and then
reducing Vee to 4.0V (±0.2V) for one verification and
to 6.0V (± 0.2V) for a second verification. Verification
at Vee levels of 4.0V and 6.0V will guarantee proper
output states over the Vee and temperature range of
the programmed part. Each data verification must be
preceded by a positive going (low to high) clock edge
to load the data from the array into the output register.
The device must be Enabled to sense the state of the
outputs. During verification, the loading of the output
must be within specified IOl and IOH limits. Steps b, c,
and d must be repeated up to 10 times or until verification that the bit has been programmed.
f) Following verification, apply five additional programming pulses to the bit being programmed. The programming procedure is now complete for the selected bit.
g) Repeat steps a through e for each bit to be programmed to a high level. If the procedure is performed
on an automatic programmer, the duty cycle of Vee at
the programming voltage must be limited to a maximum of 25%. This is necessary to minimize device
junction temperatures. After all selected bits are programmed, the entire contents of the memory should be
verified.
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.
DM77/87SR27 Programming
Procedure
National Schottky PROMs are shipped from the factory with
all fuses intact. As a result, the outputs will be low (logical
"0") for all addresses. To generate high (logical "1") levels
at the outputs, the device must be programmed. Information
regarding commercially available programming equipment
may be obtained from National. If it is desired to build your
own programmer, the following conditions must be observed.
1. Programming should be attempted only at ambient temperatures between 15 and 30 degrees Celsius.
2. Address and Enable inputs must be driven with TTL logic
levels during programming and verification.
3. Programming will occur at the selected address when
Vee is at 10.5V, and at the selected bit location when the
output pin, representing that bit, is at 10.5V, and the device is subsequently enabled. To achieve these conditions in the appropriate sequence, the following procedures must be followed:
a) Select the desired word by applying high or low levels
to the appropriate address inputs. Disable the device
by applying a high level to asynchronous chip Enable
input G. Synchronous chip Enable GS should be held
low throughout the entire programming procedure.
b) Increase Vee from nominal10.5V (±0.5V) with a slew
rate between 1.0 V/p.s and 10 V/p.s. Since Vee is the
source of the current required to program the fuse as
well as the Icc for the device at the programming voltage, it must be capable of supplying 750 mA at 11V.
Note: Since only an enable device is programmed, it is possible to program
these parts at the board level if all programming parameters are complied with.
ACTest Load
B.DY
RL1
=3000
....
TL/D/66B6-S
3-90
~National
~
Semiconductor
DM77/87SR181
(1024 x 8) 8k-Bit Registered TTL PROM
General Description
The DM77/B7SR1B1 is an electrically programmable
Schottky TTL read-only memory with D-type, master-slave
registers on chip. This device is organized as 1024-words by
B-bits and is available in the TRI-STATE® output version.
Designed to optimize system performance, this device also
substantially reduces the cost and size of pipelined microprogrammed systems and other designs wherein accessed
PROM data is temporarily stored in a register. The
DM77/B7SR1B1 also offers maximal flexibility for memory
expansion and data bus control by providing both synchronous and asynchronous output enables. All outputs will go
into the "OFF" state if the synchronous chip enable (GS) is
high before the rising edge of the clock, or if the asynchronous chip enable (G) is held high. The outputs are enabled
when GS is brought low before the rising edge of the clock
and G is held low. The GS flip-flop is designed to power up
to the "OFF" state with the application of Vee.
The DM77/B7SR1B1 also features an initialize function
INIT. The initialize function provides the user with an extra
word of programmable memory which is accessed with single pin control by applying a low on INIT. The initialize function is synchronous and is loaded into the output register on
the next rising edge of the clock. The unprogrammed state
of the INIT is all lows.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions. Once programmed, it is impossible to go back to a low.
Features
On-chip, edge-triggered registers
Synchronous and asynchronous enables for word expansion
III Programmable register initialize
I!l 24-pin, 300 mil package
III 40 ns address setup and 20 ns clock to output for maximum system speed
IJ Highly reliable, titanium tungsten fuses
IJ TRI-STATE outputs
IJ Low voltage TRI-SAFETM programming
IJ All parameters guaranteed over temperature
IJ
IJ
Data is read from the PROM by first applying an address to
inputs AO-A9. During the setup time the output of the array
is loaded into the master flip-flop of the data register. During
the rising edge (low to high transition) of the clock, the data
is then transferred to the slave of the flip-flop and will appear on the output if the output is enabled. Following the
rising edge clock transition the addresses and synchronous
chip enable can be removed and the output data will remain
stable.
Block Diagram
AO
AI
A2
604 WORDx12B-BIT
PROGIWUoIABL[ ruSE ARRAY
A'
M
AS
Pin Names
AS
AS
M
.7
.S
.5
.,
.2
.,
QO
TLiO/9195-1
3-91
AO-A9
Addresses
C
Clock
G
Output Enable
GND
Ground
GS
Synchronous
Output Enable
INITS
Initialize
00-07
Outputs
Vee
Power Supply
...co r---------------------------------------------------------------------------------,
...
a::
fe
co
....j:::
::!
C
Connection Diagrams
Dual-In-Llne Package
A7- I
.
Plastic Leaded Chip Carrier (PLCC)
It)
24
A6- 2
AS- 3
23 -AS
22 -A9
A4- S
A4- 4
21 -G
A3- 6
A3- S
20 -INITS
A2- 7
A2- 6
19
-CiS
AI- 8
AI- 7
18 -C
17 -Q7
AO- 8
QO- 9
0
Sooen
AO- 9
NC- 10
QO- 11
16 -Q6
IS -QS
QI- 10
Q2- 11
co ......
iii iii i
-Vee
12 13 14 IS 16 17 18
14 ~Q4
13 -Q3
GND- 12
TL/0/9195-3
Top View
TU0/9195-2
Top View
Order Number DM87SR181V
See NS Package Number V28A
Order Number DM77/87SR181J or DM87SR181N
See NS Package Number J24A or N24A
Ordering Information
Commercial Temp Range (O'C to
+ 70'C)
Military Temp Range ( - 55'C to
I
I
Parameter/Order Number
DM87SR181J
DM87SR181N
DM87SR181V
3-92
+ 125'C)
Parameter/Order Number
DM77SR181J
I
I
Absolute Maximum Ratings
Operating Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Note 2)
-0.5Vto +7.0V
Input Voltage (Note 2)
-1.2Vto +5.5V
Output Voltage (Note 2)
-0.5Vto +5.5V
Storage Temperature
- 65·C to + 150·C
Lead Temp. (Soldering, 10 seconds)
300·C
ESD rating to be determined.
Min
Max
Units
Supply Voltage (Vecl
Military
Commercial
4.50
4.75
5.50
5.25
V
V
Ambient Temperature (TA)
Military
Commercial
-55
0
+125
+70
·C
·C
Logical "0" Input Voltage
0
0.8
V
Logical "1" Input Voltage
2.0
5.5
V
Note 1: Absolute maximum ratings are those values beyond which the de·
vice may be permanently damaged. They do not mean that the device may
be operated at those values.
Note 2: These limits do not apply during programming. For the programming
settings, refer to the programming instructions.
DC Electrical Characteristics
Symbol
Parameter
(Note 1)
DM77SR181
Conditions
Min
DM87SR181
Typ
Max
-80
-250
Min
Units
Typ
Max
-80
-250
III
Input Load Current
Vee = Max, VIN = 0.45V
IIH
Input Leakage Current
Vee = Max, VIN = 2.7V
25
25
/LA
Vee = Max, VIN = 5.5V
1.0
1.0
mA
0.35
VOL
Low Level Output Voltage
Vil
Low Level Input Voltage
VIH
High Level Input Voltage
Ve
Input Clamp Voltage
Vee = Min, liN = -18 mA
CI
Input Capacitance
Vee = 5.0V, VIN = 2.0V
TA = 25·C, 1 MHz
4.0
4.0
pF
Co
Output Capacitance
Vee = 5.0V, Vo = 2.0V
T A = 25·C, 1 MHz, Outputs Off
6.0
6.0
pF
Icc
Power Supply Current
Vee = Max, Inputs Grounded
All Outputs Open
115
los
Short Circuit
Output Current
Vo = OV, Vee = Max
(Note 2)
-20
-70
loz
Output Leakage
(TRI-STATE)
Vee = Max, Vo = 0.45V to 2.4V
Chip Disabled
-50
+50
VOH
Output Voltage High
10H = -2.0mA
2.4
Vee = Min, 10l = 16 mA
0.50
0.35
/LA
0.80
2.0
0.45
V
0.80
'V
2.0
-0.8
V
-1.2
-0.8
V
175
mA
-20
-70
mA
-50
+50
/LA
175
115
3.2
V
10H = - 6.5mA
2.4
Note 1: These limits apply over the entire operating range unless otherwise noted. All typical values are for Vee
-1.2
S.OV and TA
Note 2: During los measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
~
3.2
~
V
2S'e.
•
3-93
.,...
CI)
.,...
Switching Characteristics
a:
U)
,...
.......
,...
,...
Symbol
:5
tS(A)
Address to C (High) Setup Time
tH(A)
Address to C (High) Hold Time
tS(INITS)
INITS to C (High) Setup Time
tH(lNITS)
INITS to C (High) Hold Time
tpHL(C)
tpLH(C)
Delay from C (High)
to Output (High or Low)
tWH(C)
tWL(C)
C Width (High or Low)
tS(GS)
CI)
c
Parameter
DM77SR181
Conditions
Min
CL = 30pF
Typ
DM87SR181
Max
Min
Typ
Units
Max
50
20
40
20
ns
0
-5
0
-5
ns
35
20
30
20
ns
0
-5
0
-5
ns
15
30
15
20
ns
25
13
20
13
ns
GS to C (High) Setup Time
15
0
15
0
ns
tH(GS)
GS to C (High) Hold Time
5
0
5
0
ns
tpZL(C)
tpZH(C)
Delay from C (High)
to Active Output (High or Low)
tpZL(G)
tpZH(G)
Delay from G (Low)
to Active Output (Low or High)
tpLZ(C)
tpHZ(C)
Delay from C (High)
to Inactive Output (TRI-STATE)
CL = 30 pF
CL = 5 pF (Note 1)
Delay from G (High)
tpLZ(G)
to Inactive Output (TRI-STATE)
tpHZ(G)
Note: All typical values are for Vee = 5V, TA = 25"C.
20
30
20
25
ns
15
30
15
25
ns
20
30
20
25
ns
15
30
15
25
ns
Functional Description
TESTABILITY
TITANIUM-TUNGSTEN FUSES
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levelsto allow 100% functional and parametric testing at every stage of the test flow.
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.
3-94
.---------------------------------------------------------------------'m
-6'
~National
~
o
iii'
..,.
Semiconductor
"'tJ
::xJ
o
Bipolar PROM Devices in Plastic
Leaded Chip Carriers (PLCC)
3:
C
CD
<
n'
CD
(II
Introduction of Surface Mount
Technology
Recent years have seen rapid advances in microcircuit
technology. The integrated circuits of the 19BO's are more
complex than the circuit boards of the 1960's. It is evident
that the next decade will bring demands for packages with
higher lead counts and closer lead spacing, both to support
the greater system density sought by designers.
Products in PLCC
5'
National Semiconductor has a broad Family of high performance PROMs. All the PAL and PROM products presently offered in DIP packages will now be available in the PLCC
(plastic leaded chip carrier) package including the 15 ns industries fastest PAL.
"'tJ
iii'
(II
n'
~
a.
CD
a.
D)
Advantages of PLCC
National Semiconductor Corporation is committed to surface mount devices, for they provide the most practical solution to these needs. Geared to development of high-complexity semiconductor chips National has placed great emphasis on package development and introducing plastic
leaded chip carriers with various number of leads as surface
mounted components.
1. Permits automated assembly.
2. Lower manufacturing costs.
Features of Surface Mount Devices
Additional Information
3. Smaller PLCC size, reduces board density and weight.
4. Lower noise and improved frequency response resulting
from shorter circuit paths. Automated assembly ensures
accurate component placement which improves reliability and provides more consistent product quality.
(")
:J'
-6'
~
..,.
..,.
CD'
-h
Cil
"'tJ
Surface mount devices have additional features compared
to molded Dual-In-Line Packages (DIP):
1. Compact design that saves space during assembly.
2. Mounting on both sides of the substrate.
3. Easier handling and excellent reliability.
4. Automation of the assembly process.
5. Lower board manufacturing costs.
6. Improved operating speed.
7. Increased board density and reduced weight.
Applications
Surface mount devices can be used where substrate size,
as well as weight and thickness are limited. The surface
mount device can also be used in areas where conventional
packages cannot be used. Areas of application include; portable video cassette recorders, video cameras, hand-held
computers, personal computers, electronic toys, car electronics, cameras, telephones, and various telecommunication equipment.
National Semiconductor offers a variety of technical briefs
covering surface mount topiCS. These include:
STARTM Tape-and-Reel Shipping System
Order Number 113635
Getting Started in Surface Mount (Equipment Suppliers)
Order Number 570435
A Basic Guide to Surface Mounting of Electronic
Components
Order Number 113615
Reliability Report: Small Outline Packages
Order Number 570430
Reliability Report: Plastic Chip Carrier
Order Number 980040
Surface Mount Technology Notebook
Order Number 980020
Plastic Chip Carrier Technology
Order Number 113295
(")
•
3-95
§a.
-
PROM
Series-20 Selection Chart
~
II)
...
'0:
~
Size
(Bits)
Device
TAA (max) In ns
Configuration
Q.
:c
o
"C
II)
"C
~
<>
::
ii:
,5
II)
II)
25
PL87X288TS
256
32 X 8
DM74S287TS
DM74S3870C
1K
256 X 4
50
30
DM74S5700C
DM74S571 TS
2K
512 X 4
55
55
45
45
DM74LS471 TS
2K
256 X 8
60
:::!E
DM74S472TS
DM74S4730C
4K
a.
DM87S1840C
DM87S185TS
8K
...
35
256
<>
oa:
A-Series
DM74S1880C
DM74S288TS
DM74S5720C
DM74S573TS
'~
C
STD
32 X 8
1,024
4K
15
x4
512 X 8
2048
B-Serles
x4
60
60
45
45
60
55
45
45
55
55
45
45
ICC
max
inmA
DIP
pins
110
16
140
16
130
16
130
16
100
20
140
140
18
18
155
155
20
20
140
140
18
18
PLCC
pins
35
35
35
35
20
CIS
'0
Q.
iii
/
//
512XB 745472,745473
74L5471
256XB
210(4
875184,875165
/
As ..
Ne Vee '7
~
110(4
745572,745573
/
/
'5
"
Ne Vee '7
~
512)(4
745570,745571 /
/
/
'5
"
Ne Vee '7
2S'X4
745287,7'5387
'5
"
Ne Vee '7
V/ /
/ / / /
A,A4
03 5
17
'3
AS
6
16
Ne
G2
AS
0,
0,
04
7
15
A2
Gl
Gl
02
02
05'
8
14
'1
07
07
~
"\.
9
03 GND 0,
05
06
03 GND 04
05
0,
A,
{)
"
A,
"
"
5]
AI
1
~
8
AI
AI
sJ
7J
A,
~....J-'\~-:->t-:-'l---:->l
=,-19••
~8
02
As
~7
ill
01
~6
O.
O.
's
At At
o. O.
15
Ne
Ne
Ne
20 PIN PKO
AS
Ne
'2~A%~"
~< 'iO''ii''i2''i3'1~~4
~
AOV /
07
A,
As As As As
'iO'11i1 'i2' 'i3' .J~
/
' \' \ 0, GND Ne
A,
A6
OoOoNe
20 PIN PKG
.=... d..
"
~
c\.'\
"
,
9
0
0,
0,
0,
' " Ne GND Ne 03 Qz / ' /
Ne GND Ne 0 3 O2
ill
ONO 02
0, 0%
AID OND Gl
0, 0%
TL/D/9261-4
TUD/9261-5
Top View
Series-24 Selection Chart
Device
Size
(Bits)
STD
A-Series
B-Series
ICC
max
inmA
TAA (max) In ns
Configuration
DIP
pins
DM74S474 TS
DM74S4750C
4K
512
x8
65
45
35
170
24
DM87SR474 REG
DM87SR476 REG
4K
512
x8
50'
-
35'
170
24
DM87S1800C
DM87S181 TS
DM87SR181 REG
8K
1024
55
55
40'
-
-
170
24
PLCC
pins
28
x8
45
-
'setup time
3·96
m
-6'
o
iii"
....
Plastic Leaded Chip Carrier
/
lKX8
875180,875181
512X8
745474,745475
/jj
1/ / / /
~
Ag
As
As
A7
NC Vee As
'"tI
:rJ
o
s:
~' "
NC
L L L L / tIl 0 :LIlli ~ IE.I ~_"J-~-'I--'l--'l-"""
IT!
U
1m
1--1--1----1 A4
C/I
s·
Gl
Gl
G2
G2
GI
Gl
[ill
G3
G3
G2
All
22C
G4
G4
G3
E2
Ilil
NC
NC,~
~
07
ffiI
m:i
o
Os
-6'
A3
~
A2
IT!
~
W
ill
AI
Ao
00
28 PIN PKG
AIO AIO
c
~
n'
CD
02 GND NC
03
-
n'
rCD
I»
c..
CD
c..
:::r
~Ii]@Ir:3@1@1Ii]@I~
01
'"tI
~
oI»
....
:l.
04 Os
CD
Ul
'"tI
r-
o
TL/D/9261-6
.g
FIGURE 5. Bipolar PROM Pinout
Plastic Leaded Chip Carrier
2KX8
77SR193
2KX8
77SR191
/
512X8
Vee As
Ag
Vee As
Ag
/jjj
lKX8
512X8
/
/
875RI81,:::::::
77SR474 /
/
/
/
/
::: :: :: ~
As
As
A7
/ / / / / / tIl o ill
1-+--1---1--1
A4
rn
NC Vee As
1
1--1---1---+---1 A2
AI
Ao
IT!
8
rn
~' \
~ IE.I ~_'.J---l
"'~---+----T-~
1-1
1--1---1---+---1 A3 1:.-2
1-+--+--+---1
1-+--+--+---1
Ne
28 PIN PKG
25
~ li
G
G
AIO AIO
~ INIT
INITS INIT
[ill' GS
GS GIGS GIGS GS
m! C
=1---1--1--1-+--1
21
NC
I---+--+--t-l
1--1---1---+---1 NC
~
m:!
07 1---1--1---+-1
1--1---1---+---1 00
ffi]
m:!
Os 1---1--1---+-1
~~rJJB~~~@r@U~
~" ',"""', '0 "~
NC
= NO CONNECTION
TL/D/9261-7
FIGURE 6. Bipolar Registered PROM Pinout
3·97
•
§e:.
e
G>
°E
lJ
Q.
:c
(,)
"CI
Programming Support
Programming Equipment
PROM devices may be programmed with hardware and
software readily available in the market. Most programmer
manufacturers will offer a PLCC adapter which will fit in existing equipment. For the availability of PLCC adapter
please check with your programmer manufacturer.
1. Data I/O
2. Structured Design
3. Stag
4. Dig Elec
5. Kontron
6. Prolog
7. Citel
G>
"CI
~
()
j
D-
oE
8
o~
Q
oa::
==
Do..
CIS
'0
Q.
iD
3-98
z
Non-Registered PROM Programming Procedure
o:;:,
::iJ
CD
CC
![
...CDCD
Co
d) Enable the device by taking the chip enable(s) to a low
level. This is done with a pulse of 10 !,-S. The 10 !'-S
duration refers to the time that the circuit (device) is
enabled. Normal input levels are used and rise and fall
times are not critical.
National Schottky PROMs are shipped from the factory with
all fuses intact. As a result, the outputs will be low (logical
"0") for all addresses. To generate high (logical "1 ") levels
at the outputs, the device must be programmed. Information
regarding commercially available programming equipment
may be obtained from National. If it is desired to build your
own programmer, the following conditions must be observed:
e) Verify that the bit has been programmed by first removing the programming voltage from the output and then
reducing Vee to 4.0V (±0.2V) for one verification and
to 6.0V (±0.2V) for a second verification. Verification
at Vee levels of 4.0V and 6.0V will guarantee proper
output states over the Vee and temperature range of
the programmed part. The device must be Enabled to
sense the state of the outputs. During verification, the
loading of the output must be within specified IOL and
IOH limits. Steps b, c, and d must be repeated up to 10
times or until verification that the bit has been programmed.
1. Programming should be attempted only at ambient temperatures between 15°C and 30°C.
2. Address and Enable inputs must be driven with TTL logic
levels during programming and verification.
3. Programming will occur at the selected address when
Vee is at 10.5V, and at the selected bit location when the
output pin, representing that bit, is at 10.5V, and the device is subsequently enabled. To achieve these conditions in the appropriate sequence, the following procedure must be followed:
"Q
:::0
o
3:
...o
"Q
CC
@
3
3
:i"
CC
...o
"Q
o
CD
Co
r:::::
CD
...
f) Following verification, apply five additional programming pulses to the bit being programmed. The programming procedure is now complete for the selected bit.
a) Select the desired word by applying high or low levels
to the appropriate address inputs. Disable the device
by applying a high level to one or more "active low"
chip enable inputs.
g) Repeat steps a through f for each bit to be programmed to a high level. If the procedure is performed
on an automatic programmer, the duty cycle of Vee at
the programming voltage must be limited to a maximum of 25%. This is necessary to minimize device
junction temperatures. After all selected bits are programmed, the entire contents of the memory should be
verified.
b) Increase Vee from nominal to 10.5V (±0.5V) with a
slew rate between 1.0 and 10.0 V/!,-s. Since Vee is the
source of the current required to program the fuse as
well as the lee for the device at the programming voltage, it must be capable of supplying 750 mA at 11.0V.
c) Select the output where a logical high is desired by
raising that output voltage to 10.5V (±0.5V). Limit the
slew rate from 1.0 to 10.0 V/!,-s. This voltage change
may occur simultaneously with the increase in Vee, but
must not precede it. It is critical that only one output at
a time be programmed since the internal circuits can
only supply programming current to one bit at a time.
Outputs not being programmed must be left open or
connected to a high impedance source of 20 k!1 minimum. (Remember that the outputs of the device are
disabled at this time).
Note: Since only an enabled device is programmed, it is possible to program
these parts at the board level if all programming parameters are complied with.
•
3-99
e:::s
I
a.
0)
c
'sE
Programming Parameters Do not test or you may program the device
Symbol
Parameters
Veep
Required Vcc for Programming
Conditions
Min
Recommended
Value
Max
10.0
10.5
11.0
V
750
mA
11.0
V
20
mA
10.0
V/",s
Units
Iccp
Icc during Programming
Vop
Required Output Voltage
for Programming
lOp
Output Current while
Programming
IRR
Rate of Voltage Change of
Vee or Output
1.0
!'61
PWE
Programming Pulse Width
(Enabled)
9
10
11
",s
Vccv
Required Vee for Verification
5.8
6.0
6.2
V
a:
Vccv
Required Vee for Verification
3.8
4.0
4.2
V
Moc
Maximum Duty Cycle for
25
25
%
I!
C)
2
a.
:::i
o
a:
a.
"C
e
.
CD
c
o
z
Vcc = 11V
10.0
10.5
VO UT = 11V
Vee at Vccp
Programming Waveforms Non·Registered PROM
T, = 100 ns Min.
T2 = 5 I's Min. T2 may be > 0 if,
Vccp rises at the same rate or
faster than
ADDRESS
INPUTS
VIH~
VIL
(Yop)
T3 = 100 ns Min.
T4,= 100 ns Min.
TS = 100 ns Min.
!'we is repested for 5 additional
pulses aiter verHication of VOH indio
cates a bit has been programmed.
SELECTED ADDRESS STABLE
T1~
I
CCP
Vcc S.OV V - Vccv
PROGRAMMED
OUTPUT
ENABLE
zzzzm:j I::
Vop - - -
~~~ ?2?22222??j
V
IH
VIL
x:::
-J I- TS
T2
~ ~U~~
~~
~~~
liI/
I-
PWE-i
NOTE: ENABLE WAVEfORM FOR AN ACTIVE LOW ENABLE.
SOME PROMS HAVE MORE THAN ONE CHIP ENABLE.
HOLD ALL OTHER ENABLE(S) TO ACTIVE STATE(S).
3·100
TLIOO/2S06-1
:::D
CD
Registered PROM Programming Procedure
CC
National Schottky PROMs are shipped from the factory with
all fuses intact. As a result, the outputs will be low (logical
"0") for all addresses. To generate high (logical "1") levels
at the outputs, the device must be programmed. Information
regarding commercially available programming equipment
may be obtained from National. If it is desired to build your
own programmer, the following conditions must be observed:
1. Programming should be attempted only at ambient temperatures between 15·C and 30·C.
e;n;
d) Enable the device by taking the chip enable (G) to a
low level. This is done with a pulse of 10 JLs. The 10 JLs
duration refers to the time that the circuit (device) is
enabled. Normal input levels are used and rise and fall
times are not critical.
e) Verify that the bit has been programmed by first removing the programming voltage from the output and then
reducing Vee to 4.0V (±0.2V) for one verification and
to 6.0V (±0.2V) for a second verification. Verification
at Vee levels of 4.0V and 6.0V will guarantee proper
output states over the Vee and temperature range of
the programmed part. Each data verification must be
preceded by a positive going (low to high) clock edge
to load the data from the array into the output register.
The device must be Enabled to sense the state of the
outputs. During verification, the loading of the output
must be within specified IOL and IOH limits. Steps b, c,
and d must be repeated up to 10 times or until verification that the bit has been programmed.
f) The initialize word is programmed by setting INIT input
to a logic low and programming the initialize word output by output in the same manner as any other address.
This can be accomplished by inverting the highest order address input from the PROM programmer and applying it to the INIT input.
g) Following verification, apply five additional programming pulses to the bit being programmed. The programming procedure is now complete for the selected
bit.
h) Repeat steps a through f for each bit to be programmed to a high level. If the procedure is performed
on an automatic programmer, the duty cycle of Vee at
the programming voltage must be limited to a maximum of 25%. This is necessary to minimize device
junction temperatures. After all selected bits are programmed, the entire contents of the memory should be
verified.
2. Address and Enable inputs must be driven with TTL logic
levels during programming and verification.
3. Programming will occur at the selected address when
Vee is at 10.5V, and at the selected bit location when the
output pin, representing that bit, is at 10.5V, and the device is subsequently enabled. To achieve these conditions in the appropriate sequence, the following procedure must be followed:
a) Select the desired word by applying high or low levels
to the appropriate address inputs. Disable the device
by applying a high level to asynchronous chip Enable
input G. GS is held low during the entire programming
time.
b) Increase Vee from nominal to 10.5V (±0.5V) with a
slew rate between 1.0 and 10.0 V / JLs. Since Vee is the
source of the current required to program the fuse as
well as the lee for the device at the programming voltage, it must be capable of supplying 750 mA at 11V.
c) Select the output where a logical high is desired by
raising that output voltage to 10.5V (± 0.5V). Limit the
slew rate from 1.0 to 10.0 V / JLs. This voltage change
may occur simultaneously with the increase in Vee, but
must not precede it. It is critical that only one output at
a time be programmed since the internal circuits can
only supply programming current to one bit at a time.
Outputs not being programmed must be left open or
connected to a high impedance source of 20 k.o. minimum. (Remember that the outputs of the device are
disabled at this time).
ui"
a.
"'CI
:::D
o
s:::
"'CI
c;
;
CC
3
3
s·
ca
"'CI
c;
~
a.
c
n;
•
3-101
Programming Parameters Do not test or you may program the device
Symbol
Parameters
Conditions
Min
Recommended
Value
Max
10.0
10.5
11.0
V
750
mA
11.0
V
20
mA
10.0
V/p.s
11
,..5
Units
Vccp
Required VCC for Programming
Iccp
Icc during Programming
VOP
Required Output Voltage
for Programming
lop
Output Current while
Programming
IRR
Rate of Voltage Change of
Vcc or Output
1.0
PWE
Programming Pulse Width
(Enabled)
9
VCCVH
Required High Vcc for Verification
5.S
6.0
6.2
V
VCCVl
Required Low Vcc for Verification·
3.S
4.0
4.2
V
Moc
Maximum Duty Cycle for
VccatVccp
25
25
%
Vcc
=
l1V
10.0
=
VOUT
10.5
l1V
10
'See DM87SR191/193 and DM77SR191/193 for correct voltage.
Programming Waveforms
Registered PROM
ADDRESS
INPUTS
VIH
VIL
==j
Tl ~
Vee 50V VCCP- -
V~ I//I//Z~
PROGRAMMED
OUTPUT
,
G IH l!I/
ENABLE
-1 I- T5
;:.1
T3
VIL
PWE
~U;;~I//I//Ic
I-
-I I-
ClK
CLOCK
T, =
T2 =
Ts =
T, =
Ts =
T6 =
I
I; T2
~~~ :/il//I//zj
v
x:::
SELECTED ADDRESS STABLE
VERIFY
-j T6
r-
n
100 ns Min.
5 p.s Min. (T2 may be > 0 if Vccp rises at the same rate or faster than VoP.)
100 ns Min.
100 ns Min.
100 ns Min.
50 ns Min.
3-102
TUOO/2S06-2
Standard Test Loads
Non-Registered PROMs
Registered PROMs
Vee
~
1
OUlPUT
TEST POINT
R2
C=30pF
=GRD
TL/00/2506-3
Switching Time Waveforms
Non-Registered PROM
ADDRESS
TL/00/2506-8
3.0V 77'77V
OV £££U'
VALID
*Device input waveform characteristics are;
Repetition rate = 1 MHz
Source impedance = 50n
Rise and Fall times = 2.5 ns max.
t=TAA=1
-----~~--~~
OUlPUT
i.5~_~
30V
lZX
ENABLE ·ov ______ )(,
(1.0 10 2.0 volt levels)
___ .X.t:~~::j
_______ _
·TAA is measured with stable enable inputs.
*TEA and TER are measured from the 1.5 volt level on inputs and outputs
wilh all address and enable inpuls slable al applicable levels.
°For 10L ~ 16 rnA. RI ~ 300n and R2 ~ 600n
°for 10L ~ 12 rnA, RI ~ 400n and R2 ~ 800n.
O"C" includes scope and jig capacitance.
TL/00/2S06-4
Switching Waveforms Registered PROM
-J tH(A)
t
tts(A)-J tH(A)
t
3V
-----------_-~....;'-tH-(GS)'if:i:El...E
-I _~ItH(GS)XXE~X~X~X~X~X~X~X~X~X~====~~V
Ao-Ag
1"'7"'T"---T"'C:~ Is(GS)
GS _ _ _...I./~/~/' _
!s 0 if Vccp rises at the same rate or faster than VoP')
100 ns Min.
100 ns Min.
~
x:::
SELECTED ADDRESS STABLE
T6
TUOO/2506-9
Approved Programmers for NSC PROMs
System #
Manufacturer
DATA 1/0
PRO-LOG
KONTRON
STAG
AIM
DIGELEC
STARPLEXTM
5/17/19/29A
M910,M980
MPP80S
PPX
RP400
UP803
Quality Enhancement Programs For Bipolar Memory
A+ PROGRAM'
Test
D.C Parametric
and Functionality
A.C. Parametric
B+ PROGRAM
Condition
Guaranteed
LOTAQL5
25°C
0.05
Each
Temperature
Extreme
Test
D.C Parametric
and Functionality
0.05
Condition
Guaranteed
LOTAQL5
25°C
0.05
Each
Temperature
Extreme
0.05
25°C
0.4
A.C Parametric
25°C
0.4
Mechanical
Critical
0.01
Mechanical
Critical
0.01
Major
0.28
Major
0.28
Seal Tests
Hermetic
Fine Leak
(5 x 10-8)
0.4
Seal Tests
Hermetic
Fine Leak
(5 x 10-8)
0.4
Gross
0.4
Gross
0.4
'Includes 160 hours of burn·in at 125'C.
3-105
Section 4
Eel 1/0 Static RAMs
Section 4 Contents
SiCMOS ECl 1/0 SRAM Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BICMOS SRAMS (ECl I/O)
NM5100INM100500 ECl I/O 256k SiCMOS SRAM 262,144 x 1-Sit.......................
NM100504/NM5104 256k SiCMOS SRAM 64k x 4 Sit.... ......... ... ......... ..... . .. ..
NM100494 64k SiCMOS SRAM 16k x 4 Sit.. ... . ....... ......... ... ...... ... .. .... .. ..
NM 10494 64k SiCMOS SRAM 16k x 4 Sit .............................................
NM1 00492INM4492 2k x 9 Advanced Self-Timed SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
NM1 OE149 256 x 4-Sit ECl EPROM .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NM100E149 256 x 4-Sit ECl EPROM ............................. , ...... ..... ... ... ..
APPLICATION NOTES
AN-565 Memory System Efficiency and How National Semiconductor's 256k x 1 SiCMOS
SRAM Helps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-566 National Semiconductor's SiCMOS III Process Is latch-Up Immune........... .. ...
AN-567 Hot Carrier and Gate Oxide Reliability Characterization of National Semiconductor's
SiCMOS III Technology...........................................................
AN-568 The Reliability of National Semiconductor's 256k x 1 SiCMOS SRAM
(NM51 00/NM1 00500) ............................................................
AN-569 256k x 1 SiCMOS ECl SRAM Memory Cell Characterization and Alpha Sensitivity
Testing. . ... . .. .... ..... .... . ......... ... ........ .. ...... ........ . .. ... .. ... ....
AN-572 Understanding Advanced Self-Timed SRAMs ........... .. ................. .. ...
AN-573 Design Considerations for High Speed Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4·2
4-3
4-4
4-11
4-18
4-25
4-32
4-45
4-53
4-62
4-64
4-67
4-69
4-72
4-73
4-80
m
o
r
~NatiOnal
::::
o
Semiconductor
en
-
S'
BiCMOS Eel UO SRAM
Ss~sctDon
C:;"
Guide
::D
~
s:
en
CD
iii
Part
Number
Organization
NM5100
NM100500
NM5104
NM100504
NM100494
NM10494
NM100492
NM4492
256kx 1
256kx 1
64kx4
64kx4
16kx4
16kx4
2kx 9
2kx9
I/O Level
100K
100K
100K
100K
10K
100K
100K
100K
VEE
Access (ns)
-5.2V ±5%
-4.2V to -4.8V
-5.2V ±5%
-4.2Vto -4.8V
-4.2V to -4.8V
-5.2V ±5%
-4.2V to -4.8V
-5.2V ±5%
15
15
12,15
15
15,18
10,12,15
7,10
5,7, 10
BiCMOS Eel UO IUlV
IE~ROM Se~ecUoD1l
Pins
24
24
28
28
28
28
64
64
Temperature
Range
O'Gto
O'Gto
O'Gto
O'Gto
O'Gto
O'Gto
O'Gto
O'Gto
+ 85'G
+ 85'G
+ 85'G
+85'G
+ 85'G
+75'G
+ 75'G
+ 75'G
Guide
Part
Number
Organization
1/0 Level
VEE
Access (ns)
Pins
Temperature
Range
NM10E149
NM100E149
256x4
256x4
10K
100K
-5.2V ±5%
-4.2Vto -4.8V
5,7, 10
5,7,10
16
16
O'Gto + 75'G
O'Gto + 75'G
4·3
n
0"
::::J
C)
C
a:
CD
o ,----------------------------------------------------------------------------,
o
in
o
o
.....
::i!!
z
g.....
in
::i!!
z
~NaHonal
~ Semiconductor
NM5100/NM100500 ECl 1/0 256k BiCMOS SRAM
262,144 x 1 Bit
General Description
The NM5100 and NM100500 are a 262,144-bit fully static,
asynchronous, random access memories organized as
262,144 words by 1 bit. The devices are based on National's advanced one micron BiCMOS III process. This process
utilizes advanced lithography and processing techniques
with double polysilicon and double metal bringing high density CMOS to performance driven ECl designs. National's
combination of high performance technology and speed optimized circuit designs results in a very high speed memory
device.
The NM5100 operates with a supply voltage of -5.2V
±5%, yet the input and output voltage levels are temperature compensated 100k ECl compatible. The NM100500
operates with a - 4.2V to - 4.8V supply voltage.
Reading the memory is accomplished by pulling the chip
select (S) pin lOW while the write enable CNl pin remains
HIGH allowing the memory contents to be displayed on the
output pin (0). The output pin will remain inactive (lOW) if
either the chip select (S) pin is HIGH or the write enable CN)
pin is lOW.
input pin will then be written into the memory address specified on the address pins (AO-A17).
Features
• 15 ns/18 ns speed grades over the commercial
temperature range
• Balanced read and write cycle times
• Write cycle timing allows 33% of cycle time for system
skews
• Temperature compensated F100k ECl 1/0
• Power supply -5.2V ±5% (NM5100)
• Power supply -4.2V to -4.8V (NM100500)
• low power dissipation < 1.1 W
• Soft error rate less than 100 FIT
• Over 2000V ESD protection
• One micron BiCMOS III process technology
• Over 200 mA latch-up immunity
• low inductance, high density 24-pin flatpack
Writing to the device is accomplished by having the chip
select (S) and the write enable (W) pins lOW. Data on the
Connection Diagrams
365 x 535 Ceramic Flatpack
(30 Mil Lead Pitch)
400 Mil Ceramic DIP
Q-
1
A16- 1
A17- 2
W- 3
4
0- 5
24 -Vee
23 -0
AO- 2
s-
-s
Al- 3
A2- 4
22
21-W
A3- 5
20 -A17
A4- 6
19 -A16
AS- 7
18 -A15
A6- 8
17 -A14
A7- 9
16 -A13
AS- 10
15 -A12
A9- 11
14 -All
VEE - 12
24 r-A15
23 I-A14
221-A13
211_A12
20 i-A11
Vee - 6
Q- 7
AO- 8
Al-9
A2- 10
A3- 11
A4-~1_2
19 i-Al0
181-VEr
17 i-A9
lSi-AS
151-A7
14i-AS
_______________________________
1~3I-A5
TLfOf9451-2
13 i-Al0
Top View
TLfDf9451-1
Pin Names
Top View
4-4
AO-A17
Address Inputs
S
Chip Select
W
Write Enable
0
Data Out
D
Data In
Vee
Ground
VEE
Power
Absolute Maximum Ratings
AC Test Conditions
Above which useful life may be impaired
Input Pulse Levels
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Input Rise and Fall Times
Storage Temperature
VEE Pin Potential to Ground Pin
........
50% of Input
3:
.....
o
o
Figure 2
Static Discharge Voltage
(Per MIL-STD 883)
>200tV
Maximum Junction Temperature (TJ)
+150°C
Output Current (DC Output HIGH)
-50mA
Latch-Up Current
Parameter
z
U1
Capacitance Tested by Sample Basis
o
o
VEE to +0.5V
Symbol
o
o
0.7 ns
AC Test Circuit
-7.0V to + 0.5V
Input Voltage (DC)
Figure 1
Output Timing Referrence Levels
- 65'C to + 150'C
z
U1
.....
3:
Max
Units
CIN
Input Pin Capacitance
5.0
pF
COUT
Output Pin Capacitance
8.0
pF
>200 mA
Operating Voltage
These devices contain circuitry to protect the inputs against
damage due to high static voltages or electric fields however, it is advised that normal precautions be taken to avoid
applications of any voltage higher than maximum rated voltages to this high-impedance circuit.
DC Electrical Characteristics Vcc =
Symbol
Device
Voltage
NM5100
VEE = -5.2V ±5%
NM100500
VEE = -4.2Vto -4.8V
Ground, Tc = O'Cto +85'C
Parameter
Conditions
Min
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIN = VIH(Max) or VIL(Min),
Loading with 50n to -2.0V
VOHC
Output HIGH Voltage
-1025
VOLC
Output LOW Voltage
VIN = VIH(Min) or VIL(Max),
Loading with 50n to - 2.0V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIH
Input HIGH Current
VIN = VIH(Min)
IlL
Input LOW Current
VIN = VIL(Max)
-50
lEE
Power Supply Current
fa = 50 MHz
-200
All voltages are referenced to Vee pin =
Max
Units
-1025
-880
mV
-1810
-1620
mV
mV
-1620
mV
-1165
-880
mV
-1810
-1475
mV
220
/LA
170
/LA
mA
av.
Vcc
i
~-'"
-it!
50%
20%
20%
t,l--
~
i
-ot f
tA = Rise Time
IF
NM5100
-1.7V
.n
TLlD/9451-3
Fall Time
50% = Timing Reference Levels
FIGURE I. Input Levels
0.1 p.F.I.
-=
-
CL
~
Q
CL fRL
-2.0V
3 pF (Including Scope and Jig)
RL ~ son
VEE
TLlD/9451-4
FIGURE 2. AC Test Circuit
4-5
•
§
....8
Truth Table
:::&
z
......
8....
It)
:::&
z
s
W
D
Q
Mode
H
X
X
L
Not Selected
L
L
L
L
Write "0"
L
L
H
L
Write "1"
L
H
X
Q
Read
Logic Diagram
w-.....--t
5-......-01_.1
D--------,
Q
A4 A5 K1. AI NJ Ams N3 A16 A7
Note: A5 = MSB
A4 = MSB
4-6
TL/D/9451-5
z
3:
Read Cycles
AC Timing Characteristics Vee =
No.
....o
(II
Symbol
Ground, Te = O'Cto
o
.....
+ 85'C
z
18 ns Device
15 ns Device
Parameter
Units
Std.
Alt.
1
TAVAX
TRC
Address Valid to Address Invalid
2
TAVQV
TAA
Address Valid to Output Valid
3
TAXQX
TOH
Address Invalid to Output Invalid
3
3
4
TSLSH
TRC
Chip Select LOW to Chip Select HIGH
7
7
5
TSLQV
TACS
Chip Select LOW to Output Valid
5
5
ns
6
TSHQL
TRCS
Chip Select HIGH to Output LOW
4
4
ns
Min
Max
Min
Max
....3:o
o
o
o
(II
15
18
ns
15
18
ns
ns
ns
Read Cycle 1
Where S is active prior to or within TAVQV-TSLQV after address valid.
TAVAX (1)
A (ADDRESS)
XXXXX
XXXXXXXXXX
ADDRESS VALID
TAXQX (3)
TAVQV (2)
,I
Q (DATA OUT) XXXXXXXXXXXX(PREVIOUS DATAiXXXXXXXXXXXXX
.1
DATA VALID
XX-XXX
·1
'1
TL/D/9451-6
Read Cycle 2
Where address is valid a minimum of TAVQV-TSLQV prior to
5 (CHIP SELECT)
Q (DATA OUT)
i
S becoming active.
TSLSH (4)
TSLQV (5)
4-7
~
t~,(,)~
DATA VALID
TL/D/9451-7
~
g
.,...
Write Cycle 1
z
This write cycle is W controlled, where S is active (LOW) prior to W becoming active (LOW). In this write cycle the data out (a)
may become active and requires observance of TWLOL to avoid data bus contention in common I/O applications. At the end of
the write cycle the data out may become active if W becomes inactive (HIGH) prior to S becoming inactive (HIGH).
.,...
AC Timing Characteristics Vee =
::E
Ci
o
II)
::E
z
No.
Symbol
Ground, Te = O·Cto +85·C
15 ns Device
Parameter
Std.
Alt.
TWC
Min
1
TAVAX
7
TWLSH
8
TWHAX
TWHA
9
TWLWH
TW
10
TAVWL
18 ns Device
Max
Min
Units
Max
Address Valid to Address Invalid
15
18
ns
Write Enable LOW to Chip Select HIGH
10
12
ns
Write HIGH to Address Don't Care
0
3
ns
Write LOW to Write HIGH
10
12
ns
TWSA
Address Valid to Write LOW
0
2
ns
Data Valid to Write HIGH
10
14
ns
Write HIGH to Data Don't Care
0
3
11
TDVWH
12
TWHDX
TWHD
13
TWLOL
TWS
Write LOW to Output LOW
5
5
ns
14
TWHOV
TWR
Write HIGH to Output Valid
15
18
ns
A (ADDRESS)
TAVAX (1)
-....
xxx:
-
xxxxXX
ADDRESS VALID
TWLSH (7)
I.
5 (CHIP SELECT) \ \ \ \\\\
I//' '//////
TWHAX (8)
TWLWH (9)
Vi (WRITE ENABLE) \ \ '
ns
r// / / / / / / / / /
.\\\\\\\\:
i-TAVWL (10)-
.t=TDVWH (11)--::::
o (DATA IN) XXXXXXXXXX X XXXXXXXXU
'I
I-TWLOL(I~
o (DATA OUT) XXXXX)()(p!~N~~ €A~:XXXX='
DATA VALID
. r:.TWHDX (12)
IXXXXXXXXX
1
I-TWHOV
(14)1///
TLlD/9451-B
4·8
z
3:
Write Cycle 2
.....
U"I
This write cycle is S controlled, where Vii is active prior to, or coincident with, S becoming active (LOW). Write cycle 2 has
identical specifications to write cycle 1 with the exceptions of Vii and S being interchanged. This write cycle may be more
convenient for common 1/0 applications because data bus restrictions are alleviated.
AC Timing Characteristics Vee =
Ground, Te = O'Cto +85'C
o
o
......
z
3:
.....
o
o
U"I
No.
Symbol
15 ns Device
Parameter
Std.
Alt.
Min
15
TAVSL
TWSA
16
TSLSH
17
TSHAX
18
18 ns Device
Max
Min
Units
Max
Address Valid to Chip Select LOW
0
2
ns
Chip Select LOW to Chip Select HIGH
10
12
ns
Chip Select HIGH to Address Don't Care
0
3
ns
TSLWH
Chip Select LOW to Write Enable HIGH
10
12
ns
19
TDVSH
Data Valid to Chip Select HIGH
10
14
ns
20
TSHDX
Chip Select HIGH to Data Don't Care
0
3
ns
TWHA
TWHD
A (ADDRESS)
.1.
XXXX
TAVSL (Isi
l•
TAVAX (1)
~Xxxxx
ADDRESS VALID
TSLSH (16)
r//J '///////
I---- TSHAX (17)
5 (CHIP SELECT)
TSLWH (18)
Vi (WRITE ENABLE) ~
D (DATA IN)
Q (DATA OUT)
~////////
xxxxxxxxxxxxxxxxxxxxxxf=
LOW
TDVSH (19)-=
~TSHDX (20)
DATA VALlDXXXXXXXX
LOW
TL/D/9451-9
4-9
o
o
o
o
r.n
o
Consecutive Write Cycles
:::E
AC Timing Characteristics Vee =
o
.,...
z......
o
o
.,...
No.
:::E
Symbol
15 ns Device
Parameter
Min
Max
18 ns Device
Min
Units
Std.
Alt.
21
TWHWL
ITWP
Write Enable HIGH to Write Enable LOW
4
4
ns
22
TSHSL
ITSP
Chip Select HIGH to Chip Select LOW
4
4
ns
r.n
z
Ground, Te = O'Cto +85'C
Max
Minimum Write Pulse Disable
M
M
A (ADDRESS)
Vi (WRITE
ENABLE)
TL/D/9451-10
Minimum Select Pulse Disable
A (ADDRESS)
5 (CHIP
SELECT)
Standard Timing Parameter Abbreviations
TIMING EXPLANATIONS
The AC Operating Conditions and Characteristics tables
typically show either a minimum or maximum limit for a device parameter. Those timing parameters which show a minimum value do so because the system must supply at least
that much time, even though most devices do not need the
full amount. Thus, input requirements are specified from the
external point of view. In contrast, responses from the memory devices (i.e., access times) are specified as a maximum
time because the device will never provide the data later
than this stated value, and usually, much sooner.
TXXXX
Signal name from which Interval is defined-.l
.
Transition direction for first signal
Signal name to which Interval Is defined
Transition direction for second signal
TL/D/9451-11
J JJ
TL/D/9451-12
The transition definitions used In this data sheet are.
= Transition to HIGH State
= Transition to LOW State
v = Transition to Valid State
x = Transijion to Invalid or Don't Care Condition
H
L
XXXXXXXXX
invalid or don't care condition
~~
Transition from high to low
can occur during this period
LZll.2227
Transition from low to high
can occur during this period
TLlD/9451-13
Ordering Information
Part Number
Temperature Range
Package Type
Ordering Code
NM5100
O'Cto + 85'C
24 Pin Ceramic DIP
NM5100D15/18
NM5100
O'Cto +'85'C
24 Pin Flatpack
NM100500
O'Cto + 85'C
24 Pin Ceramic DIP
NM100500D15/18
NM100500
O'Cto + 85'C
24 Pin Flatpack
NM100500F15/18
4-10
NM5100F15/18
,----------------------------------------------------------------.z
:s::
.....
~National
~
o
o
CJ'I
o
~
Semiconductor
z
:s::
CJ'I
NM100504/NM5104 256k BiCMOS SRAM 64k x 4
.....
o
oIloo
General Description
The NM5104 and NM100504 are 262,144-bit fully static,
asynchronous, random access memories organized as
65,536 words by 4 bits. The devices are based on National's
advanced one micron BiCMOS III process. This process utilizes advanced lithography and processing techniques with
double polysilicon and double metal bringing high density
CMOS to performance driven ECL designs. National's combination of high performance technology and speed optimized circuit designs results in a very high speed memory
device.
The NM5104 operates with a supply voltage of -5.2V
± 5%, yet the input and output voltage levels are temperature compensated 100K ECL compatible. The NM100504
operates with a -4.2V to -4.8V supply voltage.
Reading the memory is accomplished by pulling the chip
select (S) pin LOW while the write enable (W) pin remains
HIGH allowing the memory contents to be displayed on the
output pins (00-03). The output pins will remain inactive
(LOW) if either the chip select (S) pin is HIGH or the write
enable (W) pin is LOW.
input pins will then be written into the memory address
specified on the address pins (AO-A 15).
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Speed Grades: 12 ns/15 ns (NM5104)
Speed Grades: 15 ns/18 ns (NM100504)
Balanced read and write cycle times
Write cycle timing allows 33% of cycle time for system
skews
Temperature compensated F100K ECL I/O
Power supply -S.2V to ±S% (NM5104)
Power supply -4.2V to -4.8V (NM100504)
Low power dissipation <1.4W @ 50 MHz
Soft error rate less than 100 FIT
Over 2000V ESO protection
One micron BiCMOS III process technology
Over 200 mA latch-up immunity
Low inductance, high density 28-pin flatpak and 28-pin
ceramic DIP
Writing to the device is accomplished by having the chip
select (S) and the write enable (W) pins LOW. Data on the
Connection Diagrams
28-Pin Ceramic Flatpak
(30 Mil Lead Pitch)
28-Pln Ceramic DIP
02- I
\...../
Ol- 2
AO- l
AI- 4
25 I-Ol
A2- 5
Al- 6
24 1-02
2ll-01
A4- 7
221-00
AS- 8
211-5
20l-W
A6- 9
DO
01
02
Ol
00
01
28 I-Vee
27 1-01
26 1-00
A7- 10
191-AI5
AB- II
181-AI4
A9- 12
AIO- Il
17 I-All
VEE - 14
151-All
Vee
02
Ol
AO
AI
A2
Al
A4
161-AI2
I
2
3
4
5
6
7
8
9
10
II
12
13
~
14
281- 5
27rW
26rA15
25rAI4
24rA13
231_A12
221_A11
21rVEE
20rAl0
191_A9
18rA8
17rA7
16rA6
_______________________1-"5I-AS
TL/D/l0390-2
TUD/l0390-1
Top View
Top View
Pin Names
AO-A15
Address Inputs
S
Chip Select
W
Write Enable
00-03
Data Out
00-03
Data In
Vee
Ground
Power
4-11
oo:r
Ct
.....
Ln
Absolute Maximum Ratings
::::!
AC Test Conditions
above which useful life may be impaired
Input Pulse Levels
~
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Input Rise and Fall times
.....
Storage Temperature
z
Ct
Ln
Ct
Ct
:i
z
50% of Input
AC Test Circuit
-7.0Vto +0.5V
Input Voltage (DC)
0.7 ns
Output Timing Reference Levels
-65'Cto + 150'C
VEE Pin Potential to Ground Pin
Figure 1
Figure 2
Capacitance Tested by Sample Basis
VEE to +0.5V
Symbol
Static Discharge Voltage
(Per MIL-STD 883)
>2001V
Maximum Junction Temperature (TJ)
Output Current (DC Output HIGH)
+ 150'C
-50 rnA
Latch-Up Current
>200 rnA
Units
Input Pin Capacitance
Parameter
5.0
pF
COUT.
Output Pin Capacitance
8.0
pF
Operating Voltage
These devices contain circuitry to protect the inputs against
damage to due to high static voltages or electric fields however, it is advised that normal precautions be taken to avoid
applications of any voltage higher than maximum rated voltages to this high-impedance circuil.
DC Electrical Characteristics Vee =
Max
CIN
Voltage
Device
NM5104
VEE = -5.2V ±5%
NM100504
VEE = -4.2V to -4.8V
Ground, Te = O'Cto +85'C
Parameter
Conditions
Min
Max
Units
VOH
Output HIGH Voltage
Loading with 50n to - 2.0V
VOL
Output LOW Voltage
-1025
-880
mV
-1810
-1620
VIH
mV
Input HIGH Voltage
-1165
-880
mV
Input LOW Voltage
-1810
-1475
VIL
mV
50
/LA
Symbol
IIH
Input HIGH Current
VIN = VIH(Min)
IlL
Input LOW Current
VIN = VIL(Max)
-50
fo = 50 MHz
-250
Power Supply Current
lEE
All voltages are referenced to Vee pin ~ ov.
50
/LA
rnA
Vee
r
~
50%
20%
I r ....
tA
tF
~
Rise Time
~
Fall Time
50%
~
.
f.RlyCl
~-.
-
20%
Ql
Q2
-2.0V
-1.7V
Q3
-It
lRl
Tl/D/l0390-3
-2.0V
Timing Reference Levels
FIGURE 1. Input Levels
-
±Cl
YCl tRl
NN5104/
NN100504
-
-2.0V
±~ ~Rl
-
-
Rll=
QO
-2.0V
c = 3 pF (Including Scope and Jig)
O.I PF D
-=-
500.
VEE
TLlD/l0390-4
FIGURE 2. AC Test Circuit
4-12
z
...s::oo
Truth Table
5
W
D
Q
H
X
X
L
Not Selected
L
L
L
L
Write "0"
L
L
H
L
Write "1"
L
H
X
Q
Read
Logic Diagram
MSB A5
A6
A12
All
AID
A13
A14
LSB A15
MSB A4
A3
A2
Al
A9
AS
AD
LSB A7 -
..._ _...
00
01
02
03-..._ _...
5-....-<1
w-............
4-13
Mode
UI
o
.a:o.
.....
Z
s::
...o
UI
.a:o.
0lIl'
C)
.....
Read Cycles
It)
:::&
Z
AC Timing Characteristics Vee = Ground, Te = O'Cto +85'C
;;r
C)
It)
C)
C)
No.
.....
:::&
z
Symbol
Std.
Alt•
Parameter
12 ns Device
15nsDevice
18 ns Device
Min
Min
Min
Max
Max
Units
Max
1
TAVAX
TRC
Address Valid to Address Invalid
2
TAVQV
TAA
Address Valid to Output Valid
3
TAXQX
TOH
Address Invalid to Output Invalid
3
4
TSLSH
TRC
Chip Select LOW to Chip Select HIGH
7
5
TSLQV
TACS
Chip Select LOW to Output Valid
5
5
5
ns
6
TSHQL
TRCS
Chip Select HIGH to Output LOW
4
4
4
ns
15
12
12
18
15
3
ns
18
7
ns
ns
3
7
ns
Read Cycle 1
Where S is active prior to within TAVQV·TSLQV after address valid.
--
TAVAX (1)
A (ADDRESS) XX .XX
XXXXXXXXXX
ADDRESS VALID
TAXQX (3)
TAVQV (2)
.I
Q (DATA OUT) XXXXXXXXXXXX(PREVIOUS DATA1XXXXXXXXXXXJU\
.1
DATA VALID
'I
XXXXX
'I
TLlD/l0390-6
Read Cycle 2
Where address is valid a minimum of TAVQV-TSLQV prior to S becoming active.
5 (CHIP SELECT)
Q (DATA OUT)
.
1
TSLSH (4)
~
TSLQV (5)
{ t",q~1
DATA VALID
TLlD/l0390-7
4-14
z
....s:::
Write Cycle 1
This write cycle is IN controlled, where S is active (LOW) prior to IN becoming active (LOW). In this write cycle the data out (0)
may become active and requires observance of TWLOL to avoid data bus contention in common 1/0 applications. At the end of
the wrile cycle Ihe dala oul may become active if IN becomes inaclive (HIGH) prior 10 S becoming inactive (HIGH).
C)
C)
~
~
Z
AC Timing Characteristics Vee =
No.
1
Symbol
Parameter
Std.
Alt.
TAVAX
TWC
7 TWLSH
8
TWHAX
Ground, Te = O'C 10
TWHA
s:::
+ 85'C
12 ns Device
15 ns Device
18 ns Device
Min
Min
Min
Max
Max
c.n
....
Units
Address Valid 10 Address Invalid
12
15
18
ns
Wrile Enable LOW 10 Chip Selecl HIGH
9
10
12
ns
Wrile HIGH 10 Address Don'l Care
0
0
3
ns
9
TWLWH
TW
Wrile LOW 10 Wrile HIGH
9
10
12
ns
10
TAVWL
TWSA
Address Valid 10 Wrile LOW
0
0
2
ns
Dala Valid to Write HIGH
9
10
14
ns
TWHD
Write HIGH to Data Don't Care
0
0
3
ns
11
TDVWH
12
TWHDX
13
TWLOL
TWS
Write LOW to Output LOW
5
5
5
ns
14
TWHOV
TWR
Write HIGH to Output Valid
12
15
18
ns
A (ADDRESS)
is (CHIP
--xxx:
SELECT) \.\:
TAVAX (1)
ADDRESS VALID
xxx
TWLSH (7)
I
TWHAX (8)
r///////IIII
,\.\ \.\.\.\ \.\'
-TAVWL (10)-
o (DATA IN)
. ' -TDVWH (11)--::::
XXXXXXXXXXX XXXXXXXXXI
'I
I--TWLQL(~
Q (DATA OUT)
X
I//' '111111
.\\\\.
TWLWH (9)
Vi (WRITE ENABLE) \.\'
g
Max
XXXXXXX:p:~I€uE €AtA:xxg~
DATA VAliD
. t::.TWHDX (12)
IXXXXXXXXX
~~HQV (14)}//iJ
TL/0/10390-8
•
4·15
Write Cycle 2
This write cycle is S controlled, where Vii is active prior to, or coincident with, S becoming active (LOW). Write cycle 2 has
indentical specifications to write cycle 1 with the exceptions of Vii and S being interchanged. This write cycle may be more
convenient for common 1/0 applications because data bus restrictions are alleviated.
AC Timing Characteristics Vee = Ground, Tc = O·Cto +85·C
No.
Symbol
Std.
Alt.
15
TAVSL
TWSA
16
TSLSH
17
TSHAX
18
Parameter
12nsDevice
15nsDevice
18 ns Device
Min
Min
Min
Max
Max
Units
Max
Address Valid to Chip Select LOW
0
0
2
ns
Chip Select LOW to Chip Select HIGH
9
10
12
ns
Chip Select HIGH to Address Don't Care
0
0
3
ns
TSLWH
Chip Select LOW to Write Enable HIGH
9
10
12
ns
19
TDVSH
Data Valid to Chip Select HIGH
9
10
14
ns
20
TSHDX
Chip Select HIGH to Data Don't Care
0
0
3
ns
TWHA
TWHD
A (ADDRESS)
--XXX
TAVSL (15)
TAVA'/. (1)
XXXXXXX
ADDRESS VALID
TSLSH (16)
,/1/ /1111111
S (CHIP SELECT)
- - TSHAX (17)
TSLWH (18)
Vi (WRITE ENABLE) ~
"'"' (")---=:
JIIIIIIII
~"'''' (20)
D (DATA IN) xxxxxxxxxXXXXXXXXXXXXxf= DATA VALlOXXXXXXXX
Q (DATA OUT)
LOW
LOW
TLlD/10390-9
4-16
z
3:
....
o
Consecutive Write Cycles
AC Timing Characteristics Vee =
o
U1
o
Ground, Te = DOC to + 85°C
~
Symbol
No.
Parameter
12 ns Device
15 ns Device
18 ns Device
Min
Min
Min
Units
Std.
Alt.
21
TWHWL
TWP
Write Enable HIGH to Write Enable LOW
3
4
4
ns
22
TSHSL
TSP
Chip Select HIGH to Chip Select LOW
3
4
4
ns
Max
Max
Max
......
z
3:
....o
U1
~
Minimum Write Pulse Disable
M
A (ADDRESS)
Vi (WRITE ENABLE)
Tl/D/l0390-10
Minimum Select Pulse Disable
~
A (ADDRESS)
S (CHIP SELECT)
Standard Timing Parameter Abbreviations
TIMING EXPLANATIONS
The AC Operating Conditions and Characteristics tables
typically show either a minimum or maximum limit for a de·
vice parameter. Those timing parameters which show a minimum value do so because the system must supply at least
that much time, even though most devices do not need the
full amount. Thus, input requirements are specified from the
external point of view. In contrast, responses from the memory devices (i.e., access times) are specified as a maximum
time because the device will never provide the data later
than this stated value, and usually, much sooner.
TXXXX
Signal name from which Interval is defined ----.l
Transition direction for first signal
Signal name to which interval is defined
Transillon direcllon for second signal
JJJ
TlID/l0390-12
The transition definitions used in this data sheet are:
H ~ Transition to HIGH State
L
=
v~
x=
TlID/l0390-11
Transition to LOW State
Transition to Valid State
Transition to Invalid or Don't Care Condition
XXXXXXXXX
Invalid or don't care condition
\..~SS%
Transition from high to low
can occur during this period
1/lTfl//
Transition from low to high
can occur during this period
R/D/l0390-13
Ordering Information
Part Number
NM51D4
NM51D4
NM1DD5D4
NM1DD5D4
Temperature Range
DOC to
DOC to
DOC to
DOC to
+85°C
+85°C
+85°C
+85°C
4-17
Package Type
Ordering Code
28-Pin Ceramic DIP
28-Pin Flatpak
28-Pin Ceramic DIP
28-Pin Flatpak
NM51D4D12/15
NM51D4F12/15
NM1DD5D4D15/18
NM1DD5D4F15/18
•
,
~National
~
Semiconductor
NM100494 64k BiCMOS SRAM 16k X 4 Bit
General Description
Features
The NM100494 is a 65,536-bit fully static, asynchronous,
random access memory organized as 16,384 words by 4
bits. The device is based on National's advanced one micron BiCMOS III process. This process utilizes advanced
lithography and processing techniques with double polysilicon and double metal bringing high density CMOS to perfonnance driven ECl designs. National's combination of
high performance technology and speed optimized circuit
designs results in a very high speed memory device.
The NM100494 operates with a -4.2V to -4.8V supply
voltage. Reading the memory is accomplished by pulling the
chip select (S) pin lOW while the write enable (W) pin remains HIGH allowing the memory contents to be displayed
on the output pins (00-03). The output pins will remain
inactive (lOW) if either the chip select (S) pin is HIGH or the
write enable (W) pin is lOW.
• 15 ns/18 ns speed grades over the commercial temperature range
• Balanced read and write cycle times
• Write cycle timing allows 33% of cycle time for system
skews
• Temperature compensated FlOOK ECl I/O
• Power supply -4.2V to -4.8V
• low power dissipation < 1.3W @ 50 MHz
• Soft error rate less than 100 FIT
• Over 2000V ESD protection
• One micron BiCMOS III process technology
• Over 200 mA latch-up immunity
• low inductance, high density 28-pin flatpak and 28-pin
ceramic DIP
Writing to the device is accomplished by having the chip
select (S) and the write enable (W) pins lOW. Data on the
input pins will then be written into the memory address
specified on the address pins (AO-A 13).
Connection Diagrams
28-Pin CeramiC DIP
DO-I
'-'
01- 2
28 roS
27
HOi
02- 3
26 roNC
03- 4
251-A13
QO- 5
241-A12
Ql- 6
231-Al1
Vcc - 7
221-Al0
VCCO - 8
Q2- 9
20 rA9
21 rVE[
Q3- 10
AO- 11
18rA7
191-AB
Al- 12
171-A6
A2- 13
161-AS
Al- 14
151-A4
28-Pin Ceramic Flatpak
(30 Mil Lead Pitch)
DO-I
010203OD01Va;0203NCAOAl-
281-5
271-W
261-NC
251-A13
24 rA12
23 I-Al1
22 rA10
2
3
4
5
6
7
8
9
21 roVE!:
20 rA9
19 roM
181-A7
171-A6
161-A5
151-A4
10
11
12
A2- 13
A3- 14
TL/D/10391-3
Top View
TL/D/lD391-2
Top View
Pin Names
4-18
AO-A13
Address Inputs
S
Chip Select
W
Write Enable
00-03
Data Out
00-03
Data In
Vee
Ground
VEE
Power
Absolute Maximum Ratings
AC Test Conditions
above which useful life may be impaired
Input Pulse Levels
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
- 65·C to + 150·C
VEE Pin Potential to Ground Pin
-7.OVto +0.5V
Input Voltage (DC)
VEE to +0.5V
Input Rise and Fall Times
>2001V
Maximum Junction Temperature (TJ)
+150·C
Output Current (DC Output HIGH)
-50mA
50% of Input
Figure 2
AC Test Circuit
Capacitance Tested by Sample Basis
Latch-Up Current
>200 rnA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields however, it is advised that normal precautions be taken to avoid
applications of any voltage higher than maximum rated voltages to this high-impedance circuit.
DC Electrical Characteristics Vee =
0.7 ns
Output Timing Reference Levels
Symbol
Static Discharge Voltage
(Per MIL-STD 883)
Figure 1
Max
Units
CIN
Input Pin Capacitance
Parameter
5.0
pF
COUT
Output Pin Capacitance
8.0
pF
Operating Voltage
Device
NM100494
I
J
Voltage
VEE = -4.2Vto -4.8V
Ground, Te = O·Cto +85·C
Parameter
Conditions
Min
Max
Units
VOH
Output HIGH Voltage
Loading with 50n to - 2.0V
-1025
-880
mV
VOL
Output LOW Voltage
-1810
-1620
mV
VIH
Input HIGH Voltage
-1165
-880
mV
VIL
Input LOW Voltage
-1810
-1475
mV
IIH
Input HIGH Current
VIN = VIH(Min)
50
",A
IlL
Input LOW Current
VIN = VIL(Max)
-50
Power Supply Current
fo = 50 MHz
-240
Symbol
lEE
All voltages are referenced to Vee pin
~
50
",A
rnA
OV.
Vee
i
QO
~
50%
20%
1,1-
.... ~
20%
-2.0V
~
50%
-
-
01
TLlD/10391-4
JRL :EeL
Fall Time
~ Timing Reference Levels
FIGURE 1. Input Levels
-2.0V
-
CL iRL
-2.0V
NM100494
-1.7V
tR = Rise Time
tF
i
CL
JRL : E
~-'.~
Q2
,.fi
0.1 J.lr.I.
-=
i
-
03
CL iRL
-2.0V
CL= 3 pr (Including Scope and Jig)
RL =50.11.
VEE
TL/D/10391-5
FIGURE 2_ AC Test Circuit
4-19
·
m
gCI
....
,--------------------------------------------------------------------------,
Truth Table
::E
z
s
W
D
Q
Mode
H
X
X
L
Not Selected
L
L
L
L
Write "0"
L
L
H
L
Write "1"
L
H
X
Q
Read
Logic Diagram
MSB
LSB
MSB
LSB
A9
Al0
A7
fIB
All
A12
A13
ROW
ADDRESS
BurrERS
A3
A2
Al
A6
AS
AO
M
COLUMN
ADDRESS
BurrERS
DO
01
02
D3
STATIC MEMORY
ARRAY
128 ROWS X 512 COLUMNS
7
128
7
128
128
128
COLUMN DECODER
and DATA I/O
4
DATA
INPUT
BUrrERS
DATA
OUTPUT
BurFERS
4
S
QO Ql Q2Q3
Vi
TL/D/l0391-6
4-20
Read Cycles
AC Timing Characteristics Vee =
Symbol
No.
Ground, Te = Q'Cto +85'C
Parameter
Std.
Alt.
15 ns Device
18 ns Device
Min
Min
Max
Units
Max
1
TAVAX
TRC
Address Valid to Address Invalid
2
TAVOV
TAA
Address Valid to Output Valid
3
TAXOX
TOH
Address Invalid to Output Invalid
3
3
4
TSLSH
TRC
Chip Select LOW to Chip Select HIGH
7
7
5
TSLOV
TACS
Chip Select LOW to Output Valid
5
5
ns
6
TSHOL
TRCS
Chip Select HIGH to Output LOW
4
4
ns
15
ns
18
15
18
ns
ns
ns
Reac.! Cycle 1
Where S is active prior to or within TAVOV·TSLOV after address valid.
TAVAX (1)
A (ADDRESS) XXXXX
ADDRESS VALID
.xxxxxxXXXX
TAXQX (3t
TAVQV (2)
.1
Q (DATA OUT) XXXXXXXXXXXX(PREVIOUS DATA)XXXXXXXXXXXXX
'I
.1
DATA VALID
XXXXX
'I
TL/D/l0391-7
Read Cycle 2
Where address is valid a minimum of TAVOV·TSLOV prior to
S (CHIP
SELECT)
Q (DATA OUT)
i
S becoming active.
TSLSH (4)
TSLQV (5)
t
.
,,(~~
~
DATA VALID
4·21
TL/D/l0391-8
I...
::::E
z
Write Cycle 1
This write cycle is W controlled, where S is active (LOW) prior to W becoming active (LOW). In this write cycle the data out (0)
may become active and requires observance of TWLOL to avoid data bus contention in common 1/0 applications. At the end of
the write cycle the data out may become active if W becomes inactive (HIGH) prior to S becoming inactive (HIGH).
AC Timing Characteristics Vee = Ground, Te = O·Cto +85·C
Symbol
No.
Parameter
Std.
Alt.
TWC
1
TAVAX
7
TWLSH
8
TWHAX
TWHA
15nsDevice
lBnsDevlce
Min
Min
Max
Units
Max
Address Valid to Address Invalid
15
18
ns
Write Enable LOW to Chip Select HIGH
10
12
ns
Write HIGH to Address Don't Care
0
3
ns
Write LOW to Write HIGH
10
12
ns
Address Valid to Write LOW
0
2
ns
Data Valid to Write HIGH
10
14
ns
Write HIGH to Data Don't Care
0
3
ns
9
TWLWH
TW
10
TAVWL
TWSA
11
TDVWH
12
TWHDX
TWHD
13
TWLOL
TWS
Write LOW to Output LOW
5
5
ns
14
TWHOV
TWR
Write HIGH to Output Valid
15
18
ns
A (ADDRESS)
5 (CHIP SELECT)
TAVAX (1)
xxx:
-
\ \'
XXXXXX
ADDRESS VALID
TWLSH (7)
I
I/h '//////
,\\\\
TWHAX (8)
TWLWH (9)
Vi (WRITE ENABLE) \.\.\
r///////////
l\.\ \ \ \ \.\.\:
~TAVWL (10)-
I=.TDVWH (11)----::
DATA VALID
D (DATA IN) XXXXXXXXXXX .XXXXXXXXXX
x
I-~HQV (14)}J//
'I
~TWLQL (13)iX.
Q (DATA
t:,TWHDX (12)
xxxx
ouT) XXXXXXX:~j~l€uE €At:xx~
TI.ID/1 0391-9
,
4-22
Z
This write cycle is 5 controlled, where W is active prior to, or coincident with, 5 becoming active (LOW). Write cycle 2 has
indentical specifications to write cycle 1 with the exceptions of Wand 5 being interchanged. This write cycle may be more
convenient for common 1/0 applications because data bus restrictions are alleviated.
AC Timing Characteristics Vee =
Symbol
No.
Parameter
15 ns Device
18ns Device
Min
Min
15
TAVSL
TWSA
Address Valid to Chip Select LOW
0
2
ns
16
TSLSH
Chip Select LOW to Chip Select HIGH
10
12
ns
17
TSHAX
Chip Select HIGH to Address Don't Care
0
3
ns
18
TSLWH
Chip Select LOW to Write Enable HIGH
10
12
ns
19
TDVSH
Data Valid to Chip Select HIGH
10
14
ns
20
TSHDX
Chip Select HIGH to Data Don't Care
0
3
ns
TWHD
A (ADDRESS)
--XXX
TAVSL (15)
Max
~XXXXXXX
TSLSH (16)
rill VIIIIIII
SELECT)
(WRITE ENABLE)
~ TSHAX (17)
I
~
""" ("1--'=
o (DATA IN)
Q (DATA OUT)
Max
TAVAX (1)
ADDRESS VALID
TSLWH (18)
Vi
i
Units
All.
TWHA
CI
CI
Ground, Te = O·Cto +85·C
Std.
S (CHIP
...
!!:
Write Cycle 2
XXXXXXXXXXXXXXXXXXXXXxf=
DATA VALID
~///L/L/l
~"""" ("1
XXXXXXXXX
LOW
LOW
TL/D/10391-10
•
4-23
Consecutive Write Cycles
AC Timing Characteristics Vee = Ground, Te = O'Cto +85'C
No,
Symbol
Parameter
15 ns Device
18nsDevice
Min
Min
Max
Units
Std.
Alt.
Max
21
TWHWL
TWP
Write Enable HIGH to Write Enable LOW
4
4
ns
22
TSHSL
TSP
Chip Select HIGH to Chip Select LOW
4
4
ns
Minimum Write Pulse Disable
M
M
A (ADDRESS)
Vi (WRITE
ENABLE)
TLlD110391-11
Minimum Select Pulse Disable
A (ADDRESS)
S (CHIP
SELECT)
I
TXXXX
Signal name from which Interval Is deflned---.l
Transition direction for first signal
Signal name to which Interval Is defined
TransHlon direction for second signal
TLID110391-12
TIMING EXPLANATIONS
The AC Operating Conditions and Characteristics tables
typically show either a minimum or maximum limit for a device parameter. Those timing parameters which show a minimum value do so because the system must supply at least
that much time, even though most devices do not need the
full amount. Thus, input requirements are specified from the
external point of view. In contrast, responses from the memory devices (i.e., access times) are specified as a maximum
time because the device will never provide the data later
than this stated value, and usually, much sooner.
Standard Timing Parameter Abbreviations
JJ
TLID110391-13
The transition definitions used in this data sheet are:
H = Trans"ion to HIGH State
L = Transition to LOW State
v = Transition to Valid State
x = Transition to Invalid or Don't Care Cond"ion
XXXXXXXXX
Invalid or don't care condition
\S~""SS..~
Transition from high to low
can occur during this period
L2Z2ZZZ7
Transition from low to high
can occur during this period
TLlD110391-14
Ordering Information
Part Number
NM100494
NM100494
Temperature Range
Package Type
Ordering Code
O'Cto +85'C
O'Cto +85'C
28-Pin Ceramic DIP
28-Pin Flatpak
NM100494D15/18
NM100494F15/18
4-24
~National
~
Semiconductor
NM10494 64k BiCMOS SRAM 16k x 4 Bit
General Description
The NM10494 is a 65,536-bit fully static, asynchronous, random access memory organized as 16,384 words by 4 bits.
The device is based on National's advanced one micron
BiGMOS III process. This process utilizes advanced lithography and processing techniques with double polysilicon
and double metal bringing high density GMOS to performance driven EGL designs. National's combination of high
performance technology and speed optimized circuit designs results in a very high speed memory device.
The NM10494 operates with a supply voltage of -5.2V
±5%, and the input and output voltage levels are 10k EGL
1/0 compatible.
Reading the memory is accomplished by pulling the chip
select (S) pin LOW while the write enable (W) pin remains
HIGH allowing the memory contents to be displayed on the
output pins (00-03). The output pins will remain inactive
(LOW) if either the chip select (S) pin is HIGH or the write
enable (W) pin is LOW.
the input pins will then be written into the memory address
specified on the address pins (AO-A 13).
Features
• 10 ns/12 ns/15 ns speed grades over the commercial
temperature range
• Balanced read and write cycle times
• Write cycle timing allows 33% of cycle time for system
skews
•
•
•
•
•
•
•
•
Writing to the device is accomplished by having the chip
select (S) and the write enable (iN) pins LOW. Data on
10k EGL 1/0
Power supply -5.2V ±5%
Low power dissipation < 1.3W @ 50 MHz
Soft error rate less than 100 FIT
Over 2000V ESD protection
One micron BiGMOS III process technology
Over 200 mA latCh-Up immunity
Low inductance, high density 28-pin flatpak and 28-pin
ceramic DIP
Connection Diagrams
28-Pin Ceramic DIP
'-'
DO-I
28-Pln Ceramic Flatpak
(30 Mil Lead Pitch)
281-5
01- 2
271-w
DO-I
2B -5
02- 3
26 I-HC
01- 2
27 -w
26 -HC
03- 4
251-A13
02- 3
00- 5
241-A12
03- 4
25 -A13
01- 6
23 I-A11
00- 5
24 -A12
Vex;- 7
221-Al0
01- 6
23,..All
Vrx:o- 8
211-VEE
20 I-A9
Vex;- 7
22 -AID
02- 8
21 -VEE
03- 10
AO- 11
19 I-AB
03- 9
20 r-A9
lB I-A7
NC- 10
19 --AS
Al- 12
171-A6
AO- 11
18,..A7
A2- 13
A3- 14
161-A5
Al- 12
17 r-A6
15 i-A4
A2- 13
16 i-AS
A3- 14
15 I-A4
02- 9
TLlQ/l0393-2
Top View
TL/0/10393-3
Top View
Pin Names
AO-A13
Address Inputs
S
GhipSelect
W
Write Enable
00-03
Data Out
00-03
Data In
Vee
Ground
VEE
Power
4-25
..
~
o
,..
::::E
z
Absolute Maximum Ratings
AC Test Conditions
Above which useful life may be impaired
Input Pulse Levels
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Input Rise and Fall Times
Storage Temperature
Input Voltage (DC)
Output Current (DC Output HIGH)
Latch-Up Current
Capacitance Tested by Sample Basis
Max
Units
>2001V
CIN
Input Pin Capacitance
5.0
pF
+150'C
-50mA
COUT
Output Pin Capacitance
8.0
pF
>200mA
These devices contain circuitry to protect the inputs against
damage due to high static voltages or electric fields however, it is advised that normal precautions be taken to avoid
applications of any voltage higher than maximum rated voltages to this high-impedance circuit.
DC Electrical Characteristics VEE =
VOL
VIH
VIL
Figure 2
AC Test Circuit
Symbol
Maximum Junction Temperature (TJ)
VOH
50% of Input
VEE to +0.5V
Static Discharge Voltage
(Per MIL-STD 883)
Symbol
0.7 ns
Output Timing Reference Levels
-65'C to + 150'C
-7.0Vto +0.5V
VEE Pin Potential to Ground Pin
Figure 1
Parameter
Operating Voltage
Device
NM10494
-5.2V, VCC
=
VCCQ
=
GND, Tc
I
I
=
Voltage
VEE
=
-5.2V ±5%
O'C to + 75'C (Note)
Parameter
Conditions
Min
Max
Units
Tc
Output HIGH Voltage
Loading is 500. to -2.0V
-1000
-960
-900
-840
-810
-720
mV
O'C
+ 25'C
+ 75'C
-1870
-1850
-1830
-1665
-1650
-1625
mV
O'C
+ 25'C
+ 75'C
Guaranteed Input Voltage
HIGH for All Inputs
-1145
-1105
-1045
-840
-810
-720
mV
O'C
+ 25'C
+75'C
Guaranteed Input Voltage
LOW for All Inputs
-1870
-1850
-1830
-1490
-1475
-1450
mV
O'C
+ 25'C
+ 75'C
-50
50
/LA
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
IlL
Input LOW Current
IIH
Input HIGH Current
lEE
Power Supply Current
= VIL(max)
VIN = VIH(min)
fo = 50 MHz
VIN
50
-240
/LA
mA
Note: The specified limits represent the "worst case" value for the parameter. Since these "worst case" values normally occur at the temperature extremes,
additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
~:~~
~
50~
50~
20~
20~
... t,
tr~
tR
tF
TL/D/l0393-4
Rise Time
Fall TIme
50% ~ 'Timing Reference Levels
~
~
VIH(NOM) ~ (VIH(MIN)
VIL(NOM) ~ (VIL(MIN)
V
IL(NOM)
+ VIH(MAl()/2
+ VIL(MAl()/2
FIGURE 1. Input Levels
4-26
DC Electrical Characteristics (Continued)
Truth Table
Vcc
00
02
RL
RL
-2.0V
-2.0V
NM10494
01
03
RL
5
W
0
Q
Mode
H
X
X
L
Not Selected
L
L
L
L
Write "0"
L
L
H
L
Write "1"
L
H
X
Q
Read
RL
-2.0V
-2.0V
CL =3 pF (Including Scope Bnd Jig)
RL = 5011
O.'J.'F
I
VEE
TLl0/10393-5
FIGURE 2. AC Test Circuit
Logic Diagram
~
MSB A9Al0A7A8A"A12A13-
ROW
ADDRESS
BUFFERS
STATIC MEMORY
ARRAY
!ll
§
7
Q
~
128
128 ROWS X 512 COLUMNS
'"
LSB
'--MSB
_1'28
A3-
111
'28
'28
'28
A2AIA6A5AOA4-
COLUMN DECODER
COLUMN
ADDRESS
BUFFERS
7
Bnd DATA I/O
LSB
14
,---+
DQDID2-
03-
DATA
INPUT
BUFFERS
/4
DATA
OUTPUT
BUFFERS
++++
ao al a2 a3
~
~
~
Vi
-
"I
J
TL/0110393-6
4-27
Read Cycles
AC Timing Characteristics Vee =
Symbol
No.
Ground, Tc = O"Cto +75°C
Parameter
Alt.
Std.
10 ns Device
12 ns Device
15 ns Device
Min
Min
Min
Max
Max
Units
Max
1
TAVAX
TRC
Address Valid to Address Invalid
2
TAVQV
TAA
Address Valid to Output Valid
3
TAXQX
TOH
Address Invalid to Output Invalid
3
3
3
ns
4
TSLSH
TRC
Chip Select LOW to Chip Select HIGH
7
7
7
ns
5
TSLQV
TACS
Chip Select LOW to Output Valid
5
5
5
ns
6
TSHQL
TRCS
Chip Select HIGH to Output LOW
4
4
4
ns
10
12
10
15
ns
15
12
ns
Read Cycle 1
Where
5 is active prior to or within TAVQV-TSLQV after address valid.
TAVAX (1)
A (ADDRESS)
-
XXXXX
XXXXXXXXXX
ADDRESS VALID
TAXQX (3)
TAVQV (2)
.1..____
.1.
Q (DATA OUT) XXXXXXXXXXXX(PREVIDUS DATA1XXXXXXXXXXXXX
DATA VALID
XXXXX
'1-
'1
TLlD/10393-7
Read Cycle 2
Where address is valid a minimum of TAVQV-TSLQV prior to
S (CHIP
SELECT)
Q (DATA OUT)
i
5
becoming active.
TSLSH (4)
TSLQV (5)
4-28
l
t",,(,}~
DATA VALID
TLlD/10393-6
Write Cycle 1
This write cycle is Iii controlled, where S is active (LOW) prior to Iii becoming active (LOW). In this write cycle the data out (0)
may become active and requires observance of TWLOL to avoid data bus contention in common I/O applications. At the end of
the write cycle the data may become active if Iii becomes inactive (HIGH) prior to S becoming inactive (HIGH).
AC Timing Characteristics Vee =
No.
Symbol
Std.
1
TAVAX
Ground, Te = O°Cto
Parameter
Alt.
TWC
+ 75°C
10nsDevice
12 ns Device
15 ns Device
Min
Min
Min
Max
Max
Units
Max
Address Valid to Address Invalid
10
12
15
ns
7
TWLSH
Write Enable LOW to Chip Select HIGH
7
8
10
ns
8
TWHAX
TWHA
Write HIGH to Address Don't Care
0
0
0
ns
9
TWLWH
TW
Write LOW to Write HIGH
7
8
10
ns
10
TAVWL
TWSA
Address Valid to Write LOW
0
0
0
ns
11
TDVWH
Data Valid to Write HIGH
7
B
10
ns
12
TWHDX
TWHD
Write HIGH to Data Don't Care
0
13
TWLOL
TWS
Write LOW to Output LOW
5
5
5
ns
14
TWHOV
TWA
Write HIGH to Output Valid
10
12
15
ns
A (ADDRESS)
0
TAVAX (1)
-xxx:
-
ADDRESS VALID
.XXXXXX
TWLSH (7)
jZ/~ '111111
5 (CHIP SELECT) \ \ \ l\\\\.
TWHAX (8)
TWLWH (9)
Vi (WRITE ENABLE) \ \ '
'III/I'lL/ILL
.\\\\\\\\'
-TAVWL (10)-
D (DATA IN)
.I=TDVWH (11)---::::
XXXX'VVVVCXX XXXXXXXXXX
===-
'1
Q {DATA OUT}
ns
0
~~
XXXXX)O(P:~I~U~ ~i
DATA VALID
.I::JWHDX {12}
J:xxxx XXX
I--~HQV {14}}///J
TUD/l0393-9
III
4·29
~
,..
::Ii
z
Write Cycle 2
This write cycle is 5 controlled, where W Is active prior to, or coincident with, 5 becoming active (LOW). Write cycle 2 has
identical specifications to write cycle 1 with the exceptions of Wand S being interchanged. This write cycle may be more
convenient for common I/O applications because data bus restrictions are alleviated.
AC Timing Characteristics Vee = Ground, Te = O·Cto +75·C
No.
Symbol
Parameter
Std.
Alt.
15
TAVSL
TWSA
16
TSLSH
17
TSHAX
18
TSLWH
19
TDVSH
20
TSHDX
TWHA
TWHD
10nsDevice
12 nsDevlce
15nsDevice
Min
Min
Min
Max
Max
Units
Max
Address Valid to Chip Select LOW
0
0
0
ns
Chip Select LOW to Chip Select HIGH
7
8
10
ns
Chip Select HIGH to Address Don't Care
0
0
0
ns
Chip Select LOW to Write Enable HIGH
7
8
10
ns
Data Valid to Chip Select HIGH
7
8
10
ns
Chip Select HIGH to Data Don't Care
0
0
0
ns
f4---------TAVAX ( 1 ) - - - - - - - - - 1
A (ADDRESS)
XXX
-
xxxxxxx
ADDRESS VALID
TAVSL (15)f4--ro--------TSLSH ( 1 6 ) - - - - - - + 1
5 (CHIP
I~"""".,..,.~~
rlI IVI I I I I I I
SELECT)
I-----:--- TSHAX (17)
i - - - - - - - - T S L W H (18)------it..,..,'"J""l,...,...,.,..,
W(WRITEENABLE)
~
II I I I I I I I
~TDVSH (19)-
D (DATA IN)
XXXXXXXXXXXXXXXXXXXXX"'r=
DATA VALID
~HDX(20)
~
Q (DATA OUT) ...:;;LO::..:.W:......._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~LO::..:.W;...
TL/0/10393-10
4-30
Consecutive Write Cycles
AC Timing Characteristics Vee = Ground, Te = O'C to
Symbol
No.
Parameter
Std.
All.
21
TWHWL
TWP
Write Enable HIGH to Write Enable LOW
22
TSHSL
TSP
Chip Select HIGH to Chip Select LOW
+ 75'C
10 ns Device
12 ns Device
15 ns Device
Min
Min
Max
Min
2
3
4
2
3
Max
Units
Max
ns
4
ns
Minimum Write Pulse Disable
M
M
A (ADDRESS)
Vi
(WRITE ENABLE)
TL/D/l0393-11
Minimum Select Pulse Disable
A (ADDRESS)
S (CHIP
SELECT)
TIMING EXPLANATIONS
Standard Timing Parameter Abbreviations
The AC Operating Conditions and Characteristics tables
typically show either a minimum or maximum limit for a de·
vice parameter. Those timing parameters which show a min·
imum value do so because the system must supply at least
that much time, even though most devices do not need the
full amount. Thus, input requirements are specified from the
external point of view. In contrast, responses from the memo
ory devices (i.e., access times) are specified as a maximum
time because the device will never provide the data later
than this stated value, and usually, much sooner.
TXXXX
JJJ
Signal name from which Interval Is deflned--.J
Transition direction for first signal
Signal name to which Interval Is defined
Transition direction for second signal
TL/D/l0393-13
The transition definitions used in this data sheet are.
H = Transition to HIGH State
L
~
Transition to LOW State
v = Transition to Valid State
x=
TL/D/l0393-12
Transition to Invalid or Don't Care Condition
XXXXXXXXX
Invalid or don't care condition
\S\\~~
Transition from high to low
can occur during this period
LZtl.l..l77
Transition from low to high
can occur during this period
TL/D/l0393-14
Ordering Information
Part Number
Temperature Range
Package Type
Ordering Code
NM10494
O'Cto + 75'C
28·Pin Ceramic OIP
NM1 049401 0/012/015
NM10494
O'Cto +75'C
28·Pin Flatpak
NM10494F10/F12/F15
4·31
N
~----------------------------------------------------------.
Q)
"'="
"'="
:E
z
......
N
~National
~
PRELIMINARY
Semiconductor
Q)
o"'="
o NM 100492/NM4492 2k x 9 Advanced Self-Timed SRAM
.....
:E
z Features
PARITY CHECKING
The device also offers several convenient features which
may be useful in specific applications. One such feature is
the on-chip parity checking function. For systems where
parity checking is desirable this device will check for odd
parity on the 9-bit data input field, and will check for either
even or odd parity (depending on the polarity of the parity
mode pin - PM) on the ll-bit address field combined with
the address parity input. Odd parity is met when the number
of highs in the field is odd. Address parity checking can be
conveniently disabled if desired, allowing data field only parity checking. If either the data or address demonstrates a
parity error, then the parity error output flag is set. The polarity of the error output flag facilitates emitter dot ORing several error outputs for minimal delay. The parity checking feature is benign in the sense that if parity checking is not
desired, the output can simply be ignored without detrimental effects to normal operation.
• Extremely fast access time
- 5 ns Max (NM4492)
- 7 ns Max (NM100492)
• Power supply: -5.2V ± 5% (NM4492)
• Power supply: -4.2V to -4.BV (NM100492)
• Completely self-timed read and write cycle
• On-chip input and output registers
• Modest power consumption-2W at 7 ns, < 1.5W at
100 MHz
• On-chip parity checking-with odd address parity mode
pin
• Clock enable input simplifies pipeline control
• Scan diagnostics supported by on-chip scan registers
• High speed ceramic flatpak
• High speed TapePak™ package under development
• I/O compatible with FlOOk standard
SERIAL SCAN DIAGNOSTICS REGISTERS
General Description
Another convenient feature provided on-chip is the scan diagnostics register. For system designs where scan diagnostics are included, this device allows observing the state of
the input registers (scan out) and forcing the state of the
input and output registers (scan in). For writable control
store applications the control store can be loaded via the
serial channel (scan in), simplifying circuit board layout by
eliminating the wide parallel data input bus structure. For
systems where scan diagnostics are not desired, the scan
enable input can simply be left open allowing the on-chip
pulldown device to disable scan functions and provide normal SRAM functionality.
The NM100492/NM4492 is an extremely high performance
2k x 9 SRAM. It is the first of a family of similar 9-bit wide
SRAMs designed specifically for very high speed ECl computer applications such as register files, writable control
stores, cache RAMs, cache tag RAMs, and address translation lookaside buffers. The NM100492/NM4492 offers several features which are very desirable in such applications.
ADVANCED SELF-TIMED ARCHITECTURE
This advanced self-timed RAM simplifies the system design
of ex1remely fast memory arrays by minimizing the impact of
timing skews on the cycle time of the memory array. All
input signals (address, data and control signals) are registered on-chip by a transition of the clock. By registering all
inputs with minimal setup and hold times (setup + hold =
2 ns) the troublesome skews inherent with traditional static
RAM timing requirements are significantly reduced. With
skew problems minimized, very short cycle times become
practical. Output registers (self-timed on-chip) hold output
data valid for an extended portion of the cycle easing system read timing requirements.
PIPELINE CONTROL
Yet a third convenient feature is the clock enable input. This
control simplifies starting and stopping pipeline operations
in pipe lined systems. It reduces, and may eliminate, the
need to gate the clock signal external to the RAM. This
feature is also benign since the on-chip pulldown device will
ensure normal operation if the clock enable is not used.
HIDDEN WRITE CYCLE MODE
The hidden write cycle timing allows relaxed data bus timing. This will often ease system setup and hold requirements for the data output bus. Hidden write timing is essentially a technique for interleaving reads and writes. This advanced self-timed SRAM supports hidden write timing more
conveniently in the system than first generation self-timed
SRAM's, due to the unique control signal functions defined
for write enable (Vii) and chip select (8). By keeping the
output register active (with the last read data) during a write
cycle, this device greatly simplifies the timing of interleaved
memory architectures. This mode may be very useful in
cache and register file applications, where multiple sources
and/or destinations may be interleaved within each machine cycle.
MODEST POWER CONSUMPTION
Modest power consumption is achieved without compromising device speed through very unique and innovative circuit
design techniques (patents applied for). Power consumption
is predominately dependent on clock frequency (l/cycle
time) allowing a reduction in power at lower operating frequency.
FlOOK COMPATIBLE I/O
The device is I/O compatible with standard temperature
compensated FlOOK ECl logic, allowing trouble free interfacing in high performance ECl systems.
4-32
CIl"11
2 c
c:J :::l
_
"TIC')
:J
_,
g·o
o :::l
~ I»
m -
c _
1im
0.0
~C')
CLOCKED
1 OF 128
ROW
DECODER
Pf'
AO-A
L
7
r
AI
INPUT
A7-A1
4
DO-D
!
128
-I>
CLOCKED
9 BIT
PARITY
CHECKER
S
--..
Vi
SE
CK
CK
--..~l
~V
TIMING
AND
CONTROL
LOGIC
T
I--
iii'
(Q
I»
3
I144
CLOCKED 9 OF 144
COLUMN DECODER
AND SENSE AMPS
REGISTER
CKE
c
""I
CLOCKED
12 BIT
PARITY
CHECKER
9
W
(,)
~
128 x 144
STATIC
MEMORY
ARRAY
t
~
1
r
9
OUTPUT REGISTER
AND BUFFERS
~9
,
OEP
00-08
TL/D/9748-1
l6PPWN/l6POO~WN
II
NM 1004921NM4492
00"11
£
r::::
c
_j
::J
_,
::J
"n
g,O
g
en
00-08 - - - - i
".....
~~
on
9
CKE
;111\
~
S-
Vi
AO-Al0
AP
.j>.
c:,
j
II)
0-
-
-
f-t
C
iii'
INPUT
REGISTER
INPUT
MULTIPLEXER
- Ir---t
~
....
f-t
~
~
~
rfg-t
r-----t'
24 EACH
2:1 MUX
25 BITS
....
'11
f-t
CC
""'I
II)
OUTPUT
MULTIPLEXER
10 EACH
2:1 MUX
I-----t
I-----t
OUTPUT
REGISTER
10 BITS
1---+ 00-08 3
~
()
o
a
1---+ OEP
::J
15
.9,
~
.j>.
fSIGNATUR9
10 BITS
I-
SE
,..
OS
1o91
11
9
OEPAP A W S CKED
os
SERIAL SCAN SHIFT REGISTER
34 BITS
o OEPAP
t91
Vi S
A
11
CKED
9
l l
CK
---+
CK
---(l
'"
V
~
----.
TIMING
AND
CONTROL
LOGIC
-
TLlD/9748-2
0."
.go c::::J
-roC')
<1l
_,
"0
§ ::J
g. ~
iil CJ
gO'
C')
OJ
~
~
- f-t
-
A7·
-
00-
-
.,.
W
irl
I--t
irl
~
I-t
~
CLI
CiT
-
~
INPUT
REGISTER
I-t
f---+
~
f---+
~
f---+
ft>
OS
i
'-
CLOCKED
12 BIT
PARITY
CHECKER
CLOCKEO
1 Of 128
ROW
DECODER
~
9
r-
25 BITS
t
I
4
L....I...........t
C
Di'
ce
Cl
1
CLOCKED
9 BIT
PARITY
CHECKER
3
STATIC
MEMORY ARRAY
128 x 14.
3
1144
I
4
~
24 EACH
2:1 MUX
- I-t
01
L I-t
7
f----t
INPUT
MULTIPLEXER
~ ="
Pt
CLOCKED 9 Of 1«
COLUMN DECODER
AND SENSE AMPS
9
~
OUTPUT
MULTIPLEXER
10 EACH
2:1 MUX
~
~
f-t
I--t
'0
o
:::J
g.
OUTPUT
REGISTER
AND
BUffER
-fg-+ 00-08
---+
C
CD
.e,
OEP
rTIMING
AND
CONTROL
LOGIC
~ ",~ ,~~~ 1'I
34 BITS
91
l l
J
111
J
1
OS
19
TLiO/9748-3
(;6PPWN/(;6POO ~WN
II
;..,.
:Ii
z
~o
o
.....
:E
Z
Advanced Self-Timed RAM Pin Descriptions
INPUTS
All input signals are registered by the rising edge of the
clock, and the falling edge of the clock bar. Address, data
in, and control lines are all registered in exactly the same
manner, and are all specified for exactly the same input
setup and hold requirements.
Pin
Pin
CK
Description
Differential Clock Input: The "true" side of the
differential clock input.
CK
Differential Clock Input: The "complement"
side of the differential clock input.
Note: Halting the clock does substantially reduce power consumption.
Description
SE
AO-A 10 Address Inputs: Used to select the memory location for storing or retrieving data.
AP
Address Parity Input: Should be set/reset to ensure parity when combined with AO-1 o. May also
be tied to VEE to disable parity checking of the
address field. An internal pulldown is included to
disable address parity checking when this input is
not connected.
DO-OS
Data Inputs: During a write operation the data
inputs are stored in the specified address location.
Clock Enable Input: When active (low), this input
allows the device to function normally with each
rising edge of the clock. When inactive, this input
will force the device to do nothing on each rising
clock edge, thereby providing a convenient
means for controlling the clock input to the device. Although this input functions as if it gates
the clock on an off, this input actually is registered by the clock exactly as all other inputs and
as such has the same input setup and hold requirements as all other inputs. A natural assumption is that gating off the clock with the clock enable control will reduce the device power consumption substantially; but this assumption is in
fact false. The state of the clock enable pin has
very little effect on power consumption. An internal pulldown device is included to permit normal
operation even when not connected.
Chip Select Input: Can be used to inhibit a write
operation or to force the device outputs to a deselected (low) state when not writing. When active (low), each rising clock edge allows a write or
read operation to occur. When inactive, a write
operation is precluded. When inactive, and when
Write Enable is also inactive, a deselect read operation will force the outputs to the inactive (low)
state. An internal pulldown device is included to
permit normal operation even when not connected.
Write Enable Input: When active (low), each rising clock edge allows a write operation to occur,
but when active the write function has no effect
on the state of the data output pins. When inactive, each rising clock edge allows either a read
operation or a deselect read operation to occur.
CKE
5
w
PM
OS
Scan Enable Input: Enables the serial scan diagnostics mode. With Scan Enable active (high), the
contents of the scan shift register is shifted one
position on each rising clock edge. The bit shifted
out will appear on the as pin and the bit shifted in
will come from the OS pin. Information serially
scanned into the device can be loaded into either
the input register or the output register. An internal pulldown device is included to permit normal
operation even when not connected.
Serial Data Input: When in scan diagnostics
mode this input allows serial shifting external data
into the scan shift register.
OUTPUTS
QS
Serial Data Output: When in scan diagnostics
mode this output allows reading internal data directly from the scan shift register. In normal
mode, as will output the same logic level as the
last registered value of 08.
QO-QS
Data Outputs: These represent the contents of
the addressed memory location during a read cycle. The outputs will not change unless another
read cycle occurs, or unless the outputs are
forced inactive (low) by a deselect read operation.
QEP
Parity Error Output: Normally low, it goes high
when the registered inputs have a parity error.
For a read cycle it indicates the address input has
a parity error, since data input parity is only
checked during write cycles. The parity error output delay approximates access time, appearing
close to the time the data word appears in a read
cycle. The parity error output signal will remain
active (high) for a duration of the one cycle time,
after which it may change back to inactive (low) if
the next set of inputs contains no parity errors.
POWER SUPPLIES
VEE
Negative Supply
Vee
Positive Supply (Ground)
Veea Positive Supply (Ground) for
output buffers only
SHIELD
Used to shield the input pins that are adjacent to Vee and
VEE power pins from mutually coupled inductive noise.
These pins should be connected to a DC power level or left
floating dependent on board layout convenience. Note that
the pin marked PM is actually a shield pin but must be connected to the appropiate level to facilitate parity.
Parity Mode Input: When tied to VEE device will
check for Odd parity on the address field. When
tied to Vee device will check for Even parity on
the address field.
VeeREF Vee Reference: Positive supply reference for input buffers.
4-36
z
Truth Tables
=::
.....
0
Recall that all inputs are registered by a rising clock edge. The following truth tables illustrate device operation if the inputs
shown are registered; the outputs shown will appear at access time.
....
NORMAL OPERATIONS
.......
Z
=::
....
Normal operations are defined by SE = low for prior and current cycle.
Inputs
....
Outputs
Type of Operation
CKE
5
W
A
AP
PM
D
Data
Parity
Q
QEP
H
X
X
X
X
X
X
(X)
NC
NC
L
L
L
L
L
L
L
H
L
L
H
H
H
H
H
V
V
0
X
X
E
X
X
X
X
X
(X)
(X)
(X)
(X)
(X)
V
V
V
L
H
X
L
H
V
V
L
L
L
H
H
Read
Read
Deselect
Read, A Parity Error
Read, A Parity Error
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
V
V
0
L
H
X
L
H
L
H
V
V
(0)
(0)
(X)
(0)
(0)
NC
NC
NC
NC
NC
NC
NC
L
L
L
H
H
H
H
Write
Write
Write Inhibit
Write, A Parity Error
Write, A Parity Error
Write, D Parity Error
Write, D Parity Error
Special Characters: 0
~
Odd, E
~
E
0
E
X
X
V
E
V
V
V
0
0
E
Even, NC
~
X
V
V
V
V
(E)
(E)
0
<0
N
V
L
<0
N
No Operation
No Change
SCAN MODE OPERATION
Scan operation depends on current and prior states of SE (as registered by the rising edge of the clock), and on the state of the
CKE bit after scan is completed (as scanned in serially):
Inputs
Outputs
Prior
SE
Current
SE
Scanned
CKE
DS
QS
Q
QEP
Type of Operation
L
L
X
X
D8
X
X
L
H
X
X
D7
NC
NC
Enter scan mode and do first
shift
H
H
X
V
V
NC
NC
Serial shift on each clock
H
L
L
X
V
V/NC
VINC
Exit scan mode; do last shift
and then execute instruction
scanned into input register; if
read or deselect Q and QEP will
update, else no change
H
L
H
X
V
V
V
Exit scan mode; do last shift
and then copy scan register into
Q and QEP; do not execute
input instruction
Normal Operation
•
4-37
Connection Diagram
PinOut
08
1
07
2
47
DO
07
3
46
QO
Vw.
06
4
5
45
44
Ql
06
43
Dl
SHIELD
42
SHIELD
SE
Vw.
Vee
Vee
VEE
SHIELD
VEE
SHIELD
D2
05
02
05
Vw.
04
13
14
OEP
15
Vw.
03
04
34
D3
33
CLKBAR
TLIDI974B-4
Top View
Note: Pin 26 is reserved for (All).
Pin 57 is reserved for (AI2).
4-38
~aximum Ratings Above which the useful life may be impaired
If Military/Aerospace specified devices are required,
Input Voltage (DC)
VEE - 0.5Vto +0.5V
please contact the National Semiconductor Sales
Output Current (DC, High)
-50mAMax
Office/Distributors for availability and specifications.
Power consumption of the device is primarily a function of
Storage Temperature
-65'Cto + 150'C
the clock frequency. Linear derating of the operating current
Absolute
Junction Temperature
Case Temperature under Bias
VEE Potential (to Ground)
specified less the quiescent current specified by 1.25 mAl
MHz will result in a reasonable approximation at the frequency of interest (lower frequency results in lower power).
+ 150'CMax
O'Cto + 75'C
-7.0Vto +0.5V
Operating Voltage
Device
Voltage
NM4492
=
VEE
NM100492
VEE
=
-5.2V ±5%
-4.2V to -4.8V
DC Characteristics TC = O'C to + 75'C
Symbol
"
Parameter
Conditions
Min
= 5ns
= 7ns
TCHCH = 10ns
Clock = VILIVIH
Max
Units
IEEO
Operating Current (-5)
TCHCH
-500
rnA
IEEO
Operating Current (- 7)
TCHCH
-400
rnA
IEEO
Operating Current ( -1 0)
-330
rnA
IEEQ
Quiescent Current
IlL
Input Low Current
IIH
Input High Current
VOH
Output HIGH Voltage
VOL
-120
-50
rnA
+170
p.A
+220
p.A
500 to -2V
-1025
-880
mV
Output LOW Voltage
500 to -2V
-1810
-1620
mV
VOHC
Output HIGH Corner V
500 to -2V
-1025
VOLC
Output LOW Corner V
500 to -2V
-1620
mV
VIH
Input HIGH Voltage
-1165
-880
mV
VIL
Input LOW Voltage
-1810
-1475
mV
I
4-39
mV
Read Cycle
DESCRIPTION
read cycle time realized in an application is largely a function of the system skews between inputs, and of setup and
hold requirements of the device to which the RAM provides
data. If the address field and address parity bit combine to
parity then the parity error output will not assert, remaining
low. The parity error output timing closely approximates access time and meets the same specifications.
A read cycle is performed when the following conditions are
present at the time the clock rising edge registers the inputs: CKE = Low, S = Low, VIi = High, SE = Low and was
low for the previous cycle also. At access time the outputs
become valid, making a single glitch free transition from the
previous state to the new state. A deselect read cycle is
very similar to a read cycle except that S = High, and the
outputs all go inactive (low) at access time. The minimum
AC Characteristics
Tc
=
O°C to
+ 75°C. Input levels are
Symbol
-0.9V and -1.7V. Timing References are -1.3V (Note 1).
5ns(Prellm)
Parameter
Min
7nsDevice
Max
Min
10 ns Device
Max
Min
Units
Max
tcHCH
Cycle Time
tCHQV
Access Time (Note 2)
2.5
5
2.5
7
2.5
10
ns
tCHQL
Disable Time
2.5
5
2.5
7
2.5
10
ns
tlVCH
Input Setup Time
0
0
0
ns
tCHIX
Input Hold Time
2
2.5
3
ns
tCHCL
Clock High Pulse Width
1.5
1.5
2
ns
tCLCH
Clock Low Pulse Width
1.5
1.5
2
ns
tCHQEPV
Parity Access (Note 2)
2.5
Output Load: 3.0 pF and
son to
5
7
10
2.5
5
7
2.5
ns
10
ns
- 2.0V
Note 1: All maximum timing specs are referenced to the latter of elK and CLK, whichever occurs later. All minimum timing specs are referenced to the earlier of
ClK and CLK. ClK and ClK must cross each other between 10% and 90% of AC input levels.
Note 2: Maximum access time is guaranteed to be the worst case bit In the memory using a pseudorandom testing pattern.
I
I
DESELECT
I
READ1
I
NO OP
I
READ 2
READ 3
CK---,~~~c:
\
CKE
s ---'
f..XXXXXX
.(xxxxxx
\
Vi - - - '
A
0
t lVCH
XXX KXXXXXX
I - tCHOl -
--
t CHOV
--
I-
..:I.
l
Y)()(')()()O()(X
t CHOV
-
--tCHIX
\.'iX'/.XXX
)~XXXXXX
IREAD 2
READ 1
PREVIOUS DATA
I-tcHOl-
I
READ 3
I- t CHQV ""
\
OEP
Tl/D/9748-5
4-40
Write Cycle
DESCRIPTION
not cause a change in any output except the parity error
output; data outputs remain unchanged in any case. During
writes parity is checked on both the address field (combined
with the address parity input) and the data field. The parity
error output will not assert if both fields show parity. The
parity error output timing closely approximates access time
and meets the same access time specifications.
A write cycle is performed when the following conditions are
present at the time the clock rising edge registers the inputs: CKE = Low, S = Low, IN = Low, SE = Low and was
low for the previous cycle also. The minimum write cycle
time realized in an application is largely a function of the
system skews on the inputs. Notice that a write cycle will
AC Characteristics
o·c to + 75·C. Input levels are
Tc =
Symbol
-0.9V and -1.7V. Timing References are -1.3V (Note 1).
5ns(Prelim)
Parameter
Min
7 nsDevice
Max
Min
10 ns Device
Max
Min
Units
Max
tCHCH
Cycle Time
5
7
10
tlVCH
Input Setup Time
0
0
0
ns
tCHIX
Input Hold Time
2
2.5
3
ns
tCHCL
Clock High Pulse Width
1.5
1.5
2
ns
tCLCH
Clock Low Pulse Width
1.5
tCHQV
Parity Access Time
2.5
1.5
5
ns
ns
2
2.5
7
2.5
10
ns
Disable Time
10
ns
2.5
5
2.5
7
2.5
tCHQL
Output load: 3.0 pF and 50n to - 2.0V
Nate 1: All maximum timing specs are referenced to the latter of ClK and ClK, whichever occurs later. All minimum timing specs are referenced to the earlier of
ClK and ClK. ClK and ClK must cross each other between 10% and 90% of AC input levels.
Note 2: Maximum access time is guaranteed to be the worst case bit in the memory using a pseudorandom testing pattern.
I
NO OP
I
I
WRITE
WRITE INHIBIT
I
I
NO OP
I
DESEl.ECT
I
WRITE
WRITE
.~r--L.~~
1\
CKE
tlVCH-
I
~
:X :X
:X
l-
I
S
Vi
/
\
~X
/
\
L)()()()()()(
-1cH1XA
XXxxxxXXX
XXXXXXXXXXXXX IXXXXXXX
X
XXXX :X
D
XXxxxxXXX
XXXXXXXXXXXXX ,XXXXXXX
X
XXXXX
~
I--
IoHQV -
I--
tCHQL
\
PREVIOUS DATA
Q
IoHQL -
QEP
TL/D/974B-6
4-41
Hidden Write Cycle
The hidden write cycle allows the SRAM to be operated at
twice the bandwidth of the data output bus. With relaxed
data bus timing (relative to the SRAM address & control
input timing) system constraints of setup and hold times
may be much more easily met. Hidden write is a technique
for interleaving read and write cyles in such a way that the
write cycle timing has no effect on the data output bus (read
timing). To allow hidden write operation the definition of the
functions performed by select (8) and write (Vii) are subtly
but importantly different than implemented on common
SRAMs.
Hidden write can provide throughput enhancement in certain cases. If, for example, the RAM is utilized as a register
file, and provides data to a pipelined ALU implemented in a
gate array. If the ALU data input register requires 3 ns setup
and 3 ns hold, the total data input window required is 4 ns
wide. The SRAM maximum access is 7 ns, and the minimum
access time is 2.5 ns; the difference is the guaranteed data
output valid window. In this example the SRAM must be
operated at greater than 9 ns cycle time to allow room for
data and clock skews. Depending on system details maybe
to or tins cycle could be practical. In contrast, using hidden write timing the memory could be run at 7 ns cycles with
the data output bus cycle times of 14 ns, eaSing the ALU
setup and hold times while allowing a store and a fetch
every 14 ns.
With hidden write timing there are no unusual restrictions.
Consecutive read and write cycles may be at different or at
the same address location. If a read is not desired at any
given moment a read deselect or a no op may be executed
instead. Similarly, if a write is unnecessary a write inhibit or
no op may be substituted.
READ 1
WRITE 1
READ 2
WRITE 2
READ 3
I
WRITE INHIBIT
I
READ~
CK
CKE
Q
~~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
~:.....--------.
~________REA_D_l______~X:=======R=EAD==2=======X~_______REA_D_3____~X~___REA_D_4__
TL/D/974B-7
4-42
z
s::
.....
Scan Mode
DESCRIPTION
The scan mode allows serial input and output for diagnostics or for loading RAM (e.g., in a writable control store application). In overview:
1. The first clock cycle with scan active (SE = High) causes
the device to enter scan mode and serially shift.
2. Succeeding clock cycles with scan active cause serial
shifting, and
3. The first clock cycle with scan inactive (SE = Low) causes the device to shift and then execute (conditionally)
either the scanned in instruction or to force the outputs to
a scanned in test vector (see truth table).
Several devices can be linked serially in a scan chain. A
detailed description follows:
1. Scan bits are transferred from the input register to the
scan serial register at the end of every regular read or
write cycle. The device also transfers a fixed scan signature into the remaining bits of the serial scan register in
preparation to also shift this data out (the remaining bits
are those bits of the serial shift register which correspond
with the output register).
2. On the first and each succeeding clock rising edge with
scan active (SE = High) the device will shift the serial
shift register one bit.
A. The state of DS is shifted into the chain.
B. The last bit of the chain is shifted out on as.
C. The other outputs remain unchanged. The rest of the
RAM executes a no operation. It will not write regardless of the state of the bit in the WE location of the
input register.
D. Any number of shifts can occur in scan mode; two to
infinite shifts are possible.
3. The first rising clock edge with scan inactive (SE = LOw)
causes the device to shift the scan chain and exit scan
mode and to conditionally either:
A. Execute the scanned in instruction (e.g., read, write,
deselect) with normal timing response (access, cycle)
only if the scanned in bit in the CKE location of the
input register is active (CKE = Low). The output may
be affected, according to the instruction executed. The
contents of the scan register bits corresponding to the
output register are ignored.
o
o
01:00
co
N
........
Z
s::
01:00
01:00
CO
N
Or:
B. Transfer the contents of the scan register into the output buffer, and ignore the contents of the input register, only if the scanned in bit in the CKE location of the
input register is inactive (CKE = High).
4. The second and succeeding clock cycles after scan is
inactive (SE = Low) are defined as normal mode operations and do not cause any scan functions.
The scan sequence is:
Input DS
to ao, a1, a2, a3, a4, a5, a6, a7, as, aEP,
to AP, A2, A1, AO, A6, A5, A4, A3, A1D, A9, AS, A7,
to WE, CS, CKE,
to DO, D1, D2, D3, D4, D5, D6, D7, DB,
to as Output
The scan logic is deSigned to output a sequence of bits
recognizable as a scan signature, intended as an aid in fault
detection in those cases where the fault causes a malfunction in the serial scan chain. This bit sequence can be easily
recognized by the scan diagnostics processor as it is shifted
out, providing a reasonably sure method of determining
where and/or if the serial scan chain is defective. The scan
signature bit sequence corresponds to the outputs:
QO
H
Ql
L
Q2 Q3
LH
Q4 Q5
LH
Q6 Q7 Q8
LHH
QEP
L
•
4-43
AC Characteristics
Tc = O'C to +75'C. Input levels are -0.9Vand -1.7V. Timing References are -1.3V (Note 1).
Symbol
5 ns (Prelim)
Parameter
Min
7nsDevice
Max
Min
10ns Device
Max
Min
Units
Max
tCHCH
Serial Scan Mode Cycle Time
5
7
10
ns
tDSVCH
Serial Data Setup Time
0
0
0
ns
tcHDSX
Serial Data Hold Time
2.0
2.5
3
tcHQSV
Serial Output Delay Time (Note 2)
2.5
5
2.5
7
2.5
ns
10
ns
Output Load: 3.0 pF and 50n to - 2.0V
Note 1: All maximum timing specs are referenced to the lattef of elK and elK, whichever occurs later. All minimum timing specs are referenced to the earlier
of elK and elK. elK and elK must cross each other between 10% and 90% of AC input levels.
Note 2: Maximum ~ccess time is guaranteed to be the worst case bit in the memory using a pseudorandom testing pattern.
I
I
I
I
I
CK~~~~
ENTER SCAN
SCAN MODE
EXIT SCAN
IcHCH-
'D5VC!I-
S[
os
QS
00-8
CD
DS
-
I--
XXXX ®XXXX
-I
D7
-
,I:;,IcH",
DO
@
'\.
r-IcHOSV
..
D5
PREVIOUS DATA OUT
~)(D
Z
-7.000
-6.800
-6.600
-6.400
-6.200
-6.000
-5.800
-5.600
-5.400
-5.200
~ -5.000
w -4.800
~ -4.600
-4.400
-4.200
-4.000
-3.800
-3.600
-3.400
-3.200
-3.000
•••••••••••• ppppppppppppppppppppppppppppppppppppppp
••••••••••••• pppppppppppppppppppppppppppppppppppppp
••••••••••••• pppppppppppppppppppppppppppppppppppppp
••••••••••••• pppppppppppppppppppppppppppppppppppppp
••••••• •••••• pppppppppppppppppppppppppppppppppppppp
••••••• ••••••• ppppppppppppppppppppppppppppppppppppp
•••••••••••••• ppppppppppppppppppppppppppppppppppppp
V ••••••••• ••••• ppppppppppppppppppppppppppppppppppppp
V ••••••••• •••••• pppppppppppppppppppppppppppppppppppp
V ••••••••••••••• pppppppppppppppppppppppppppppppppppp
V •••••••••••••••• ppppppppppppppppppppppppppppppppppp
V •••••••••••••••• ppppppppppppppppppppppppppppppppppp
V I ................. pppppppppppppppppppppppppppppppppp
V I •••••••.•••••••••• ppppppppppppppppppppppppppppppppp
vi ••••••••••••••••••• pppppppppppppppppppppppppppppppp
V I ••••••••••••••••••••• pppppppppppppppppppppppppppppp
V
V
V
V
V
V
V
V I •••.•••••••••.••••••..••.••.•.•••.•••••••••••••••••
vi ••••••••••••••••.••••••.•••••••••••••••••••••••••••
vi ••••••••••••••••••••••••••••••.••••••••••••••••••••
vi ••••••••••••••••••••••••••.••••••••••••••••••••••••
V I ....•.....•........•.•..................••........•
I I I I I II I I I I I I I I I I I I I I I I I I I I I I I I I I I II I I I I I I II I I I I I I I I
-5.0ns
-3.0ns
-l.Ons
(TWHAX1)
1.Ons
3.0n5
5.0n5
FIGURE 1. Address Hold Time vs Operating Supply Voltage
-7.000
-6.800
-6.600
-8.400
-6.200
-6.000
-5.800
-5.600
-5.400
-5.200
~
-5.000
w -4.800
~ -4.600
-4.400
-4.200
-4.000
-3.800
-3.800
-3.400
-3.200
-3.000
vi ••••••••••••• pppppppppppppppppppppppppppppppppppppp
vi ••••••••••••• pppppppppppppppppppppppppppppppppppppp
vi •••••••••••••• ppppppppppppppppppppppppppppppppppppp
V I .............. ppppppppppppppppppppppppppppppppppppp
vi ....•.•...•... ppppppppppppppppppppppppppppppppppppp
vi •••••••••••••• ppppppppppppppppppppppppppppppppppppp
vi •••••••••••••• ppppppppppppppppppppppppppppppppppppp
V I .•...•....•.•. ppppppppppppppppppppppppppppppppppppp
V ••••••••• ••••• ppppppppppppppppppppppppppppppppppppp
V ••••••••• ••••• ppppppppppppppppppppppppppppppppppppp
V •••••••••••••• ppppppppppppppppppppppppppppppppppppp
V •••••••••••••• ppppppppppppppppppppppppppppppppppppp
V . • • • . • . • • . . . . . . pppppppppppppppppppppppppppppppppppp
V ••••••••• ••••••• ppppppppppppppppppppppppppppppppppp
V •••••••••••••••••• ppppppppppppppppppppppppppppppppp
V • • • • • • • • • • • • • • • • • • • • • • ppppppppppppppppppppppppppppp
V
•••••••••••••••••••••••••••• PPPPPPP ••••••••••••••••
V
V
V
V
iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
5.00.
-3.0n5
-l.Ons
1.Ons
3.0ns
-5.0n5
(TAVWL1)
FIGURE 2. Address Setup Time vs Operating Supply Voltage
4·63
UI
en
UI
U)
r----------------------------------------------------------------------------,
:g
z• National Semiconductor's
cc BiCMOS III Process
Is Latch-Up Immune
National Semiconductor
Application Note 566
Dave DiMarco
LATCH-UP AND CMOS
Latch-up is a well known and documented phenomena in
CMOS technology.1 It occurs when parasitic pnpn (or SCR)
devices inherent in CMOS processes are turned on, and
results in a high current, low impedance path between Voo
and Vss. This can lead to permanent device damage or
temporary nonfunctionality until the device is powered
down.
In N-well CMOS the pnpn path is the result of a parasitic
lateral npn and a parasitic pnp transistor as shown in Figures 1 and 2. This structure has two stable states. In the first
or the "blocking state" the emitter/base junctions are reverse biased and a high impedance path is maintained be-
tween Voo and Vss. In the second state, both emitter base
junctions are forward biased, and a high current path between Voo and Vss is turned on.
In normal CMOS operation, this pnpn path is in its "blocking" state. It can, however, be switched into its "on" state if
the lateral current IpS and INW become large enough to forward bias the parasitic emitter base junctions. This can occur from: radiation currents, c dv/dt current resulting from
voltage spikes across the n-well/substrate junction, avalanche multiplication currents at the n-well/substrate junction, or input over voltage conditions. 2
N-WELL
Ips
P-SUBSTRATE
+-TL/D/10091-1
FIGURE 1_ Standard CMOS Process
Vss
TL/D/10091-2
FIGURE 2. ParasitiC Bipolar SchematiC
4-64
In order for latch-up to occur, three conditions must be
mel. 1 First, there must be high enough lateral substrate current to forward bias both emitter/base junctions. Second,
the current gain product of the parasitic pnp and npn must
be > 1. And third, the power supply must be capable of
supplying the "holding current" required to sustain latch-up.
In order to minimize the effects of latch-up, these conditions
must be controlled through intelligent process and design.
ed without forward biasing the parasitic npn and pnp transistors. Additionally, inclusion of a buried layer results in a significantly lower current gain for the parasitic devices. The
use of buried layers for latch-up control has previously been
described by Estreich et al. 2
Unique to SiCMOS processes is a latch-up condition created by the standard npn transistors in combination with the
parasitic npn and parasitic pnp as shown in Figure 4. If the
standard npn is allowed to saturate, forward biasing the
base-collector junction, majority carrier holes are injected
into the substrate. These carriers then form the base current
for the parasitic npn transistors, and potentially, could trip
the pnpn latch from its blocking state, to its on state. 3 Again,
the N+ and P+ buried layers used in the SiCMOS III process reduce the lateral resistances to the point where this
will not forward bias the parasitic transistors and latch-up is
avoided.
LATCH-UP AND BICMOS
National's SiCMOS III process has inherent advantages
over standard CMOS processes. These advantages eliminate latch-up problems and design/layout dependence. As
part of SiCMOS III, N+ and P buried layers are present
under all n-well and p-well areas respectively. A representative cross section is shown in Figure 3. As a result, the
lateral n-well and p-well resistance are reduced to ohms
from k-ohms. Hence, higher lateral currents can be tolerat-
P-SIUCON
TUD/l0091-3
FIGURE 3. BiCMOS III Process Cross Section
P SUBSTRATE
TL/D/l0091-4
FIGURE 4. BiCMOS Latch-Up Circuit
4-65
U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
U)
Ln
Z•
0(
TEST RESULTS
CONCLUSION
latch-up testing has been performed at temperature extremes for National's 256k x 1 ECl BiCMOS SRAM
(NM5100) and no latch-up was observed. In all cases, latchup could not be induced. Testing was performed under the
following conditions:
Temp. = -60°C and 130°C
National's BiCMOS III process has proven to be immune to
latch-up in extensive characterization and testing. It has inherent process advantages over standard CMOS processes
with respect to latch-up. Today, these advantages insure
latch-up immunity in the NM5100.ln the future, they will also
insure latch-up immunity in all of National's BiCMOS static
RAMs.
= -5.0V; Vee = OV
Each device pin ramped from 0 rnA to 500 rnA.
(Only one pin tested at a time.)
The following cases were tested:
VEE
REFERENCES
1. D.B. Estreich, "The Physics and Modeling of Latch-Up
and CMOS Integrated Circuits," Stanford Univ., Stanford,
CA, Tech. Rep. G-201-9, 1980.
2. D.B. Estreich, "An Analysis of Latch-Up Prevention in
CMOS IC's Using an Epitaxial-Buried Layer Process"
IEDM Digest, pp. 230-234, 1978.
1. Float all pins except supply pins and pin under test.
2. Pins adjacent to pin under test = Vee, all other pins floating except supply and pin under test.
3. Same as #2 except adjacent pins = -1.9V (V,Ll.
3. A.R. Alvarez, "BiCMOS Technology,"
Course, Dec. 1987.
4-66
IEDM Short
.
l>
Hot Carrier and Gate Oxide
Reliability Characterization
of National
Semiconductor's
BiCMOS III Technology
National Semiconductor
Application Note 567
Eric Hall
Marshall Davis
INTRODUCTION
5.0V and 5.5V to give the life under normal operating conditions as seen in Figure 1 below.
From CMOS ring oscillator simulations on SiCMOS III, the
time required for the gate to pass through the region which
creates the highest impact ionization current was found to
be about 1% of the total switching period. Taking into account that the CMOS circuitry constitutes approximately
50% of the total access time for the 256k SRAM, a 4E + 6
second time to 10% Gm degradation, obtained from Figure
1, would equate to BE+B seconds [4E+6/(0.01 x 0.5)1. or
about 25 years at worst case operating conditions. AC
stress data for inverter operation also shows much longer
lifetimes than DC stress data. For pass gate circuits, Gm
degradation is not important, but rather the drain current in
the saturation region. This has been studied using AC stresing and has also shown very satisfactory lifetimes. Actual
circuit degradation will be additionally determined by the
switching frequency in the application of the MOSFET. System level failure will be determined by the application of the
SRAM in terms of timing tolerances or power levels.
An additional processing concern is that the introduction of
hydrogen during the Silicon Nitride plasma deposition for
the second passivation, plasma bond pad etching, and the
final forming gas anneal, also contribute to hot carrier injection. Introduced hydrogen ions form weak Si-H bonds at the
oxide interface, and can be easily broken by hot carrier injection. Plasma radiation may enhance this process. Research is ongoing to optimize a final passivation process
with minimal degradation effect. A final phosphorous doped
silicon glass (PSG) passivation for devices in hermetic packages is also being considered.
To better understand total circuit effects, access time degradation is being characterized on 256k devices through
both static and dynamic burn-in at -55'C and VEE = -6V.
In a static burn-in, no parametric shifts were seen through
1000 hours. Dynamic burn-in is currently underway. To date,
the DC stressing results and the static burn-in results show
that SiCMOS III has good tolerance against hot carrier degradation.
Gate oxide quality and the susceptibility of MOSFETs to hot
carrier degradation are two concerns which are of prime
importance in the reliability of a MOS process. Detection of
weak devices that can lead to field reliability failures is critical. Thus, major emphasis has been placed on end of line
monitors and identifying processing steps which have improved the reliability of the SiCMOS III process.
HOT CARRIER DEGRADATION
With decreasing MOSFET channel lengths, such as with
National's SiCMOS III one micron technology and 256k
SRAM, localized fields at the drain region continue to increase. This results in highly accelerated electrons which
may collide with the silicon lattice and create electron hole
pairs (impact ionization). Some of the "hot" carriers may be
trapped in the gate oxide or at the oxide interface. Trapped
carriers, or charge generation as a result of carrier injection,
result in parametric shifts, which can lead to decreased performance and system non-functionality.
Device degradation is often measured in terms of percent
shift in transconductance, Gm, which is the change in drain
current with respect to the change in gate voltage at a constant drain voltage. In the SiCMOS III technology, Gm degradation has been characterized by accelerated DC and AC
testing of N-channel MOSFETs. In DC stressing, the drain is
held above 5.5V with the gate voltage set to achieve maximum impact ionization current, which is measured using
substrate hole current. The time for 10% Gm degradation is
used as a standard benchmark to show process stability
and to study process effects on degradation. For AC stressing, several test modes are used to simulate different circuit
conditions. Inverter and SRAM pass gate circuits are the
two most used stress conditions. AC frequencies have been
used up to 10 MHz, with rise and fall times from 100 ns
down to 4.5 ns. AC testing shows degradation mechanisms
not seen in DC stressing, and is, therefore, a better indicator
of circuit Iifetime(l). For both AC and DC stressing, the lifetime data is extrapolated back to a drain voltage of
z
CJ1
0)
.....
,0-2,-----------,
S
10-3
§
"'"
I
iil
'0-4
B.OV STRESS
7.5V STRESS
7.0V STRESS
6.7V STRESS
III
EXTRAPOLATED 5.5 V LIFE
EXTRAPOLATED
5.0V LIFE
,0-5
'0-6
,02 ,03 ,04 ,05
106 '07 loB
,09
10'0 '0" '0. 2
TIME TO , 0% GM DEGRADATIONS (SEC)
TUD/l0092-1
FIGURE 1. Accelerated AC and DC Stressing of Drain Voltage to Determine
10% GM Degradation under Normal Operating Conditions
4-67
.....
;z
cc
GATE OXIDE INTEGRITY
Wafer Level Reliability (WLR) monitors in the BiCMaS III
process are used to identify possibly unreliable lots. Two
such measurements that are used for monitoring gate oxide
integrity and possible hot carrier degradation are the
Charge-to-Breakdown (Qbd) and Fowler-Nordheim tunneling calculations to determine minimum oxide thickness.
These measurements are taken on test structures that lie in
the scribe line in between the 256k die. The test structures
used are poly edge intensive capacitors, with N + junction
regions, which best simulate actual transistor gates. The
WLR gate oxide monitors have been very successful in detecting processing problems which result in both yield failures and decreased reliability.
The Fowler-Nordheim minimum oxide thickness. is determined from current measurements taken during V-ramp
testing. This test shows the oxide thickness at the thinnest,
or weakest, point in the structure, unlike capacitance measurements which give an average thickness of the gate oxide. This measurement is particularly useful in detecting
point defects or oxide thinning at the field edges, which create localized high field regions.
In the Charge-to-Breakdown measurement, a constant current density is forced (J = 0.1 Alcm2) while the gate voltage is monitored. This is done until avalanche breakdown
occurs, which is defined as a 50% reduction in the gate
voltage in a one second interval. Qbd is calculated as being
J x time to fail, in units of Coulombs/cm2. Qbd, and not just
substrate current alone, has also been found to correlate
well with hot electron degradation in the BiCMaS III process
(Figures 2 and 3) (2).
6.0
QBD = COULOMBS/CM 2
ISUB=AMPS
~
::>
III
•
104 105 106 107 108 109 10'0 10"
TIME TO 10% GM DEGRADATION (SEC)
TUD/l0092-3
FIGURE 3. Relationship between Qbd/lsub
and the Time to 10-Percent Gm Degradation
during Hot-Electron StreSSing
SUMMARY
With reliability monitors and continued development, the effects of hot carrier and gate oxide degradation can be minimized and controlled. BiCMaS III also has incorporated inline and end-of-line WLR monitors to ensure high reliability.
Fowler-Nordheim thickness and Qbd measurements are
good indicators of weak or thin gate oxides with susceptibility to hot carrier degradation. All of these enhancements and
WLR monitors help to provide for excellent process stability.
REFERENCES
1. H. Wang, M. Davis, R. Lahri, "Transient Substate Cuffent
on N-Chai7nel MOSFET Device Lifetime'; (to be presented at IEDM 1988).
2. M. Davis and R. Lahri, "Gate Oxide Charge-ta-Breakdown Coffelation to MOSFET Hot-Electron Degradation';
IEEE Elect Dev. Let, vol. EDL-9, No.4, pp. 183-185,
April 1988.
! :; ~ -,-;;7" ~
10-1
B
SlRESS V
To (ANG)
QB'b (c/cw2)
A
7.5
200
0.3
• •
•• •
4.0
3~~~~~~~~~~~
102 " . - - - - - - - - - - ,
Co.
*
~
II>
e
'"0
....
••
••
5.0
B
7.5
200
6.3
ISUB05.5V 5olE-5A S.IE-SA
10-3 ..............~........~""-~""-"..............""'"
100 10' 102 103 104 105 106
STRESS TIME (SEC)
TUD/l0092-2
FIGURE 2. Gm Degradation over Time
for Devices with the Same Substate Current
and Stress Voltage, but Different Qbd
4·68
The Reliability of National
Semiconductor's 256k x 1
BiCMOSSRAM
(NM51 OO/NM 100500)
National Semiconductor
Application Note 568
Eric Hall
INTRODUCTION
NM5100 DIE RELIABILITY TESTING AND RESULTS
Since the beginning of the development of National Semiconductor's one micron BiCMOS III process one third of the
BiCMOS process development team has been dedicated to
reliability assurance. Long before first silicon of the 256k
SRAM arrived, many test structures which contained devices similar to those on the 256k were available for characterization and enhancement of the reliability of the process.
Once 256k die were available, extensive dynamic high temperature operational life (HTOL) testing began in a real-time
monitored burn-in system.
HTOL testing is used to accelerate failure mechanisms that
may occur during the lifetime of the device. This is achieved
by stressing the devices at elevated temperatures and voltage. Some of the typical failure modes stressed by HTOL
are ionic contamination, electromigration and oxide time dependent dielectric breakdown (TDDS). The first two failure
modes are accelerated by temperature when a bias voltage
is applied. The temperature increase will allow contaminating ions enough energy to become mobile and getter at the
device surface causing threshold shifts. Electromigration
occurs in high current density areas of metal. Aluminum atoms are transported along the grain boundaries of the metal
in the direction of the electron flow. This creates voids in the
metal at one end and a build up of aluminum atoms (hillocks) at the other. Often the failure mode results in an open
circuit.
TDDS is also accelerated by voltage stressing. Over time
when a constant voltage is applied across the gate of a
MOS transistor, trapped charge will accumulate in the gate
oxide. This will continue until the effective potential across
the gate oxide equals the breakdown voltage of the dielectric (hence the name TDDS), at which time failure occurs.
PROCESS RELIABILITY TESTING AND RESULTS
Before the 256k die arrived in silicon, test vehicles allowed
BiCMOS process engineers to characterize the process for
such reliability concerns as gate oxide quality, electromigration in metals and the integrity of passivation layers.
With the thin gate oxide (200A) in the BiCMOS III process,
the high quality of the oxide is critical. Such tests as breakdown voltage measurements, thickness measurements and
current stressing were performed. Normal breakdown voltages of the dielectric in excess of 24V were measured,
where target values are 20V-22V for this thickness. Thickness measurements were developed to give a thickness at
the thinnest point in the oxide and not just an overall average. Constant current stressing allowed for a method of
monitoring hot carrier degradation. These three tests allowed for detecting weak pOints in the oxide and correcting
them with process enhancements.
As well, electromigration was tested in the SiCMOS TiW I AICuSi/Ti metal sandwich, contacts and vias. From the results, all structures have expected lifetimes in excess of 100
years with small variance. This is independent of whether
the failure mode was an open circuit, intralayer short or interlayer short.
Another reliability monitor which was performed on un lidded, packaged test structures was a high temperature
(85'C) and high humidity (85% RH) stress test. Two groups
of units were tested; one group having just a single layer of
phosphorous doped silicon glass (PSG) passivation and the
other with an additional layer of silicon nitride passivation
(normal SiCMOS process). After 2000 hours, only two parts
from sixteen with PSG alone showed any signs of corrosion.
Later SiCMOS SRAMs were subjected to HAST (highly accelerated stress testing; 145'C, 85% RH). Through 48
hours, equivalent to over 2500 hours of 85'C/85% RH, five
of 26 parts had corroded bond wires. However, no sign of
metal corrosion of the die was observed, even under SEM
analysis. Again these parts were tested in un lidded packages with full passivation.
These monitors and testing of the BiCMOS III process are
just a sample of the total number that have been performed.
Furthermore, the areas of reliability concern, such as breakdown energy of metal and gate oxide quality are continually
monitored on each 256k fab lot with wafer level end of line
testing.
The activation energies for these three failure mechanisms
are given in Table I below where a higher energy corresponds to a larger acceleration factor from operating temperature to stress temperature. The temperature acceleration factor is given by equation 1 where Ea is the activation
energy.
Eq. 1
AF (Temp) = exp[Ea/k(1/Tst - 1/Top)]
The voltage acceleration factor for TDDS is
AF (Vtg) = exp[S(1/Eop - 1lEst)]
Eq. 2
where Eop is the operating voltage divided by the gate oxide
thickness (200A), Est is the stress energy and S is an empirical constant of the process. S has been measured to be
112 MV/cm for BiCMOS III.
SiCMOS 256k and 16k SRAMs (the 16k is identical in its
periphery cirCUitry to the 256k but has a smaller memory)
have been stressed in a monitored dynamic burn-in system
at a voltage supply of - 6.25V and a temperature of 150'C.
The acceleration factors and stressed hour to operational
year equivalents for the 256k are summarized in Table I.
The monitored burn-in system allows for functionally exercising each part to test patterns such as march and checkerboard. The burn-in tester will log the time and board location of any failure. In addition all devices were individually
serialized and tested for parametric shifts at 0, 24, 48, 72,
144, 288, 576, and 1152 hour readpoints. In all, 24 parameters were monitored across the commercial temperature
range of O'C to 85'C. Excellent results were attained; none
of the parameters shifted significantly from 0 to 1152 hours.
A sample of these parameters is summarized in Table II
below.
4-69
•
CD
CD
TABLE I
NM5100 BICMOS 256k x 1 SRAM Acceleration Factors
~
Z
cc
Fall Mechanism
Ea
TempAF
VTGAF
TOTAF
10YR
Electromigration
0.7eV
160
N/A
160
547HR
21 YR
OxideTDDB
0.3eV
8.8
133
1174
74HR
156YR
Ionic Contamination
1.0eV
1412
N/A
1412
62HR
186YR
1152 HR
vOP = -5.5V. VST = -S.25V, Top = 75'C. TST = 172'C
TABLE II
NM5100 BiCMOS 256k x 1 SRAM HTOL Parametric Data
Parameter
O"C
OHR
O·C
1152 HR
85·C
OHR
85·C
1152 HR
Units
lEE
-143.58
-144.36
-137.31
-138.49
rnA
VOH
-0.97
-0.97
-0.98
-0.98
V
VOL
-1.70
-1.71
-1.72
-1.73
V
TAA(TAVQV)
11.50
11.36
13.24
13.10
ns
Tw(TWLWH)
8.22
7.99
10.01
10.01
ns
TWSA (TAVWL)
-5.96
-5.96
-6.64
-6.87
ns
TWHA (TWHAX)
-4.51
-4.41
-5.62
-5.82
ns
Parametric Shifts in AC values
< 200 ps are not significant due to tester resolution.
TABLE III
BICMOS SRAM Burn-in Results
Lot #
Device
#IN
# HRS
# Fails
Shift
1
16k
StaticHTOL
30
3456
0
No
2
16k
StaticHTOL
28
1728
0
No
Test
Comment
3
16k
Dynamic HTOL
33
1152
0
No
4
16k
Dynamic HTOL
58
1152
0
No
5
256k
Dynamic HTOL
40
1728
1 @96Hrs
No
6
256k
Dynamic HTOL
114
1152
0
No
7
256k
Dynamic HTOL
125
1152
0
No
8
256k
Dynamic HTOL
75
1152
1 @24Hrs
No
Minirow
9
256k
Dynamic HTOL
12
1152
0
No
PtSilAs+ EVAL
10
16k
StaticLTOL
29
1000
0
No
HOTe- EVAL
Oven Temp = 150'C for HTOL, -55'C for LTOL.
Supply VEE = -S.25V for dynamic, -S.OV for static burn·in.
4-70
Single Bit
.
r--------------------------------------------------------------------;~
Out of all the 16k and 256k devices, only two units failed
functionally during the burn-in stress testing (Table III). One
unit failed at the 96 hour readpoint with a "stuck" single bit.
The second failed at the 24 hour read pOint with a minirow
fail. These failures are currently being analyzed. For 256k
devices alone, this would equate to 32 FIT (1 Failure In
Time equals 1E + 9 device hours). Since a production burnin equal to 48 hours is performed on all devices, this implies
that the 24 hour failure would have been screened out as a
failing unit. This brings the FIT rate down to 16 FIT. For
example, with 1000 units, it would be over 7 years of operation at constant worst case operating conditions before 1
device fails. One other remarkable point to note is that all of
the 16k SRAMs used for HTOL and also Lot 5 of the 256k
devices were from only the second SiGMOS SRAM lot ever
produced in the fab.
study no fails or parametric shifts were observed. A dynamic
test under the same conditions is under way.
Upcoming process changes involve conversion from phosphorus to arsenic doped emitters for speed enhancement
and adding a platinum silicide layer under first metal to reduce P + contact resistance. Twelve units have been
burned in to 1152 hours, once again with no fails or parametric shifts.
Z
CI1
en
OC)
SUMMARY
As indicated by the "upfront" commitment from the SiGMOS process development group to their wafer level testing and end of line monitors, followed by the burn-in studies
with actual 256k SRAMs, the reliability of the SiGMOS III
process has been fully characterized and enhanced. To further insure the reliability, each fab wafer lot will continue to
be monitored and samples will be periodically placed on
HTOL. Additionally, each device receives, and will continue
to receive, a 48 hour burn-in and gate oxide stress test in
order to eliminate infant mortality failures before they are
shipped to the customer. Reliability was designed into the
process and will continue to be a major factor in manufacturing of SiGMOS III products.
As part of the functional testing that each device receives, a
gate oxide stress is applied with a -6.5V supply. This stress
will screen devices with very weak oxides for TDDS failures.
Further evaluations include a low temperature op life study
for hot carrier degradation and a HTOL look ahead for possible process enchancements. At low temperatures the silicon lattice is more stable and an electron has a greater
probability of colliding with it and creating an electron hole
pair (impact ionization). The "hot" carriers may then become trapped in the gate oxide causing threshold shifts. A
static burn-in at a supply of -6.0V and stress temperature
of - 55'G was performed on 29 units for 1000 hours. In this
REFERENCES
1. D.L. Grook, "Method of Determining Reliability Screens
for Time Dependent Dielectric Breakdown, "ibid., 17,1,
1979.
2. Technology Associates, Accelerated Testing Handbook,
1987.
III
I
4-71
256k x 1 BiCMOS ECl
SRAM Memory Cell
Characterization and Alpha
Sensitivity Testing
National Semiconductor
Application Note 569
Paul Berndt
Dave DiMarco
INTRODUCTION
These high flux alpha sources make it possible to assess
the alpha sensitivity of the device in a short period of time.
Alpha performance is measured in FITs. One FIT equals
one fail in 10E9 device hours. The FIT Rate is calculated by
taking the flux of the alpha source and the flux of the device
package and calculating an acceleration factor.
For the NM5100, alpha sensitivity testing was done with Radium-226 sources. These sources match the energy distribution found in packaging materials. A Takeda 3331 Memory Tester was used to test devices and log errors. A checkerboard pattern was written into the memory and read in 5
minute intervals to check for errors for a total of 30 minutes.
Alpha testing was conducted over the following supply voltages: -4.00V, -4.20V, -4.50V, -4.80Vand -5.50V. Figure 1 shows the NM5100's FIT rate vs supply voltage. FIT
rates below 100 have been achieved for VEE less than
-4.50V!
National Semiconductor's 256k x 1 SiCMOS ECl SRAM
(NM5100) has undergone extensive characterization to ensure its reliable performance in a system. Part of the characterization entailed an extensive analysis of the stability and
alpha sensitivity of the memory cell. The stability and alpha
sensitivity are major attributes of the memory cell. These
attributes will affect the reliability and performance of the
memory in a system environment from a "soft error" stand
point. A "soft error" is a fail which occurs when the memory
cell looses data and flips state but can then successfully be
rewritten with data.
CELL STABILITY
The stability of the memory cell will determine the memory's
immunity to system level disturbances. One such disturbance of special interest is address skew. Address skew is
a common phenomena in systems which can cause "soft
error" problems. An unstable memory cell will be highly sensitive to this condition. When addresses are skewed on a
static RAM, memory cells can be partially selected. This can
degrade the internal voltage margin in the memory cell to
the point where it may flip states, resulting in a "soft error".
The NM5100 has been extenSively characterized from both
a DC and an AC point of view to verify immunity to this
phenomena. Additionally, all die are tested to a simulated
address skew condition at wafer level to insure device integrity.
Alpha
105
ASSUMPTIONS:
PKG FLUX = 0.1 CTS/CM 2 *HR
STD PROCESS
104
103
~
'"t::
"-
102
'0 '
10°
ALPHA SENSITIVITY
10-1
The alpha sensitivity of the memory cell is a major factor in
determining a memory's Soft Error Rate (SER). Alpha particle hits are a well documented cause of "soft errors" in
semiconductor memories.(I) The package material used in
semiconductor devices emits alpha particles due to contaminates which are present in the package material. These
contaminates are present in plastiC and ceramic packages.
When an alpha particle strikes the internal node of a memory cell, it can cause the cell to change states. This results in
a soft error. Even though low alpha flux package material is
used, alpha induced soft errors can still cause system problems if proper memory design techniques are not followed.
~~
CONDITIONS:
TEST TIME = 30 MIN
1.12 uCi RADIUM-226 SOURCE
ROOM TEMPERATURE
10-2 '-'-'~""""'~""""'~""""'~......J..~'-'-'
-3.5
-4
-4.5
-5
-5.5
-6
VEE (VOlts)
TUO/l0094-1
FIGURE 1
In order to determine what the alpha SER of a memory will
be, accelerated alpha testing must be conducted. Accelerated alpha testing is done with sources which have alpha
fluxes that are orders of magnitude higher than that of packages.
CONCLUSION
Cell stability and alpha immunity are two major components
required for system reliability. These components have
been thoroughly characterized to insure the NM5100's reliable performance in a system. Cell stability is tested on all
devices and alpha induced soft error rates of less than 100
FIT have been demonstrated (without die coat)!
REFERENCES
1. Tim May, Murry Woods, "A New Failure Mechanism for
Soft Errors in Dynamic Memories", Proceedings 1978,
Reliability Physics Symposium, April 1978, pp. 33-40.
4-72
National Semiconductor
Application Note 572
Charlie Hochstedler
Understanding Advanced
Self-Timed SRAMs
INTRODUCTION
The Advanced Self-Timed SRAM devices are designed to
relieve several system design difficulties usually encountered when designing memory arrays associated with high
speed ECl data processors. These unique and innovative
devices are intended for applications demanding high memory bandwidth. The design of arrays for cycle times of 5 ns
to 10 ns is much easier with these AST SRAMs than with
generic ECl SRAMs. Speed critical applications such as
caches, address translation buffers, writable control stores,
and large register files all may greatly benefit from the use
of these new memory devices.
This brief explains the differences between conventional
SRAMs, self-timed SRAMs, and these new Advanced SelfTimed SRAMs. Particular emphasis is given to the timing
differences, which profoundly influence the system design.
This brief does not include a complete discussion of all the
features and functions of an AST SRAM. Device data
sheets contain additional and very important information,
and should be reviewed along with this brief.
LIMITATIONS OF GENERIC SRAMs
High speed ECl SRAMs are certainly available. They offer
fast read access. Careful system design can result in good
access performance, but high bandwidth is very often a significant challenge or even an elusive goal. Memory bandwidth is commonly defined as the reciprocal of the cycle
time. Access time is the delay you encounter while waiting
for a memory response, and cycle time is the rate at which
you can repetitively access memory. Generic SRAM data
sheets would lead you to believe that cycle time is equal to
access time. A more realistic view might be to consider access time the lower limit of cycle time; seldom achieved in
practice. The reason for this difference between access
time and cycle time will become clear through a quick review of the timing of a generic ECl high speed SRAM.
Read cycle timing is shown in Figure 1, first as it is found in
the typical data sheet, and then again with a few practical
system level constraints included. Notice that there is only a
very short window of time where data outputs are valid if the
cycle time is set equal to the access time. This time is usually specified as output hold or data hold from address
change; and is often only a few nanoseconds for fast ECl
SRAMs. One system design problem is how to use a very
brief data output valid interval. The normal solution is to
latch or register the data into the next logic element. The
deSign must allow enough time for the data register or latch
setup and hold time. Also added to the setup and hold times
is some allowance for the variations expected in the signal
which clocks the data register or latch. These factors will
invariably sum to a value greater than the SRAM specification for output hold from address change; resulting in the
necessity of increasing the cycle time beyond the data
sheet minimum.
Address bus skew is another speed robbing effect which
must be accounted for. In a practical system, addresses can
not be guaranteed to change from the previous state to the
Data Sheet Read Cycle
ADDRESS
DATA OUT
TLlD/l0097-1
System Read Cycle
ADDRESS OF "0"
ADDRESS
"C"
DATA OUT
DATA PATH LATCH OR REGISTER
SETUP + HOLD TIME
TLlD/l0097-2
FIGURE 1. Generic SRAM Read Timing
4-73
•
new state all at exactly the same time. There is, in reality, a
window of time during which the addresses may be changing. Address bus skew, defined for the purposes of this
brief, is from the instant that the quickest address may begin
its transition until the slowest address can be guaranteed to
have completed its transition. Address bus skew and data
path setup and hold times are normally the most significant
factors which cause read cycle time to be slower than read
access time.
trates the differences between a data sheet write cycle and
the timing a system designer contends with. For most ECl
high speed SRAMs the sum of write pulse width, data setup,
and data hold times equals the data sheet write cycle time
specification. The write pulse skew (the soonest it may fall,
until the time is guaranteed to have risen) adds directly to
the write cycle time. Also the effects of address and data
bus skew need to be considered to determine which is actually the ,design limitation. These skews often sum to large
values relative to the data sheet speed. It is common for
system design constraints to result in practical cycle times
of 15 ns to 20 ns for 7 ns SRAMs. If fast access is all that is
required, then these effects are not deleterious. In many
applications cycle time is as critical as access time, creating
a strong desire for relief from these speed degrading effects.
The write cycle is almost always the bandwidth limiting factor in systems designed with generic ECl SRAMs. It is uncommon for a designer to design for different read and write
cycle times because most systems must accommodate
reads and writes at random. Writable control stores are a
notable exception; caches are a good example of memories
usually requiring random reads and writes. Figure 2 iIIus-
Data Sheet Write Cycle
1 - - - - - CYCLE - - - ' - - I
ADDRESS
DATA IN
"N"
WRITE
TLIDI1 0097-3
System Write Cycle
1 + - - - - - - - - - - cYCLE - - - - - - - - - - - 1
ADDRESS
ADDRESS OF "K"
ADDRESS OF "L"
DATA IN
"K"
ilL"
~Ba~
~~
PULSE WIDTH
WRITE
TUD110097-4
FIGURE 2_ Generic SRAM Write Timing
4-74
To maximize throughput system designers have often used
latches or registers to hold all the inputs going into, and the
outputs coming from the memory array. Most ECl processors designed today utilize ECl gate array or standard cell
ASICs for the logic elements in the design. This approach
makes the inclusion of memory support registers or latches
relatively easy and practical. A write pulse generator is generally implemented locally, very near the SRAMs to minimize the write pulse skews. The write pulse generator can
be a straightforward monostable utilizing gate delays to set
the pulse width; triggered by a write command generated
elsewhere in the system logic. As timing demands tighten,
the need to time the write pulse from a system clock increases, so more exacting design alternatives are used. Figure 3 illustrates these functions usually found supporting
common ECl fast SRAMs.
Self-Timed SRAMs include on chip registers and/or latches
for inputs and outputs, and also include an on chip write
pulse timing generator. A basic self-timed SRAM block diagram is given in Figure 4. Several variations are appearing
today, offering a choice of latches or registers, and a few
different types of clock and control functions. These differences are relatively minor and not significant in the understanding of the operation of this new class of memory.
ADDRESS
GENERIC ECL fAST SHAM ARRAY
(AN ARBITRARY ARRAY N WORDS X M BITS)
DATA IN
WRIIE ENABLE
-+---.....
DATA OUTPUT REGISTER OR LATCH
LATCH OR REGISTER _ ......_ _ _ _ _ _ _ _ _...
TIMING CLOCK
L.._ _ _ _ _...._ _ _ _ _..
DATA OUT
TLlD/l0097-5
FIGURE 3. A Typical Eel SRAM Implementation
ADDRESSES
==t
ADDRESS
REGISTER
..
ROW DECODER
r
..
.
~
T
DATA INPUTS
SELECT
WRITE
CLOCK
-
~
- --.
- --.
SRAM MATRIX
~
.
~
DATA REGISTER
r
T
CONTROL REGISTER
,.
COLUMN DECODER
AND DATA I/O
l
CONTROL LOGIC AND
WRITE TIMING
OUTPUT REGISTER
OR LATCH
l
T
DATA OUTPUTS
TL/D/l0097-6
FIGURE 4. Basic Self-Timed SRAM Block Diagram
4-75
The key to understanding the self-timed SRAM is the timing
waveforms of Rgure 5. Notice that all inputs are registered
(or latched in some devices) by the clock edge, in both the
read cycle and in the write cycle. Also notice that in a read
cycle the data output is registered (or latched in some devices) by the same clock edge. The device now contains the
functions which were often included in the 'memory support
logic ASICs. But something more than just different partitioning is happening. Now the registered data output is held
for much of a cycle, alleviating the data path setup and hold
constraints even with cycle times similar to access time.
Also, the data input and address busses are registered,
trading off bus skew problems for setup and hold times on
the inputs. The control line registers result in the most important difference. With write and select registered, the
write timing is all completed internally. This eliminates the
need for the system designer to be concerned with the
tricky write pulse width, setup and hold time constraints.
Control signals are often specified with the same characteristics as the address and data input signals. The ability to
easily design for cycle time about the same as access time,
especially for write cycles, is the fundamental benefit of selftimed devices.
Self-Timed SRAM Read Cycle
ADDRESS
SELECT
1---------
CYCLE
---------1
CLOCK
DATA OUT
"A"
"8"
"C"
TL/D/l0097-7
Self-Timed SRAM Write Cycle
CLOCK _ _ _ _J'
~---------------- CYCLE ----------------~
TUD/l0097-B
FIGURES
4-76
Different styles of self-timed SRAMs bring slightly different
issues to light. The devices with registered inputs and registered outputs are usually defined in such a way as to force
the system designer to treat them as a "1 deep" pipeline
stage. The data output is always clocked out at the same
time as the next set of inputs are clocked in, giving rise to
the notion of 1 clock period latency. For many system architectures this may not be a detriment, and the advantages of
a shorter cycle time usually outweigh the negatives.
For complete timing flexibility, separate clocks (i.e., an input
clock separate from an output clock) are possible. Generally, the flexibility and performance advantages this can provide are overshadowed by the additional complexity of generating and distributing two carefully controlled clocks instead of one.
ADVANCED SELF-TIMED SRAMs
Advanced Self-Timed SRAMs (AST SRAMs) expand on the
concepts of the basic self-timed devices (ST SRAMs) already reviewed. The most important difference is that the
AST devices are register based and include an on chip timing generator for the output register. A simplified block diagram for the AST SRAM is given in Figure 6.
In devices with latched inputs and outputs the data output is
available a little sooner (at least theoretically) but the clock
usually requires much more critical timing. Now one level of
the clock is used to latch the outputs. This places demands
on the clock generation and distribution which complicate it
more than edge triggered registered style devices .
ADDRESSES
......
......
ADDRESS
REGISTER
,..to.
to.
,..
ROW DECODER
SRAM MATRIX
.oil ~
T
"'I ,.
to.
DATA INPUTS
,..to.
::,..
DATA REGISTER
------
i
SELECT
WRITE
CONTROL LOGIC AND
TIMING GENERATORS
CONTROL REGISTER
I--
COLUMN DECODER
AND DATA I/O
1
OUTPUT REGISTER
CLOCK ENABLE
INPUT CLOCK
T
T
l
DATA OUTPUTS
TL/0/10097-9
FIGURE 6. Advanced Self-Timed SRAM Simplified Block Diagram
4-77
"".
z
N
Ln
Z
•
UI
.......
Co)
~
z
C-"
U
~
~
U
Zo = son
son
TL/D/1009B-6
FIGURE 4b. Transmission line Match
FIGURE 4a. Databook load
~
Zo
=SOA
~
OUT®
INP®
SOn.
-2V
CJ
FIGURE 4c. "Typical" Application
4-82
TUD/1009B-7
l>
z
Data Transmission on ECl Systems
•
en
(j
TERMINATION
lOAD LINE
\::~'
a
2T
4T
AT ECl OUTPUT (0)
ECl HIGH
~
3T
__ ---------+-..,-'-r------=~
LAST Eel INPUT
,,
-2V
®
Tl/O/1009B-B
FIGURE Sa. ECl Transition to High State
FIGURE 5b. Reflection Diagram
for Transition to High State
ECl System Design Considerations
Due to the terminated impedance environment required by
Eel devices, there are a few basic routing rules which must
be followed. Before designing an Eel system, an understanding of these basic routing conditions should be understood. Some of the basic considerations are discussed
here; a more comprehensive discussion can be found in the
National F100K Eel User's Handbook.
The most straight forward connection method was shown in
Figure 4c. This method simply places a son resistor at the
input to the next device to provide a series terminated load.
In some cases, it is desirable to connect several outputs to
a common bus. This is particularly desirable for Eel devices
since they have open emitter outputs and are specifically
designed to be used in wired-or bus configurations. Figure
6a shows a typical "party line" connection. In this case,
care must be taken to minimize the physical distance between the two outputs. If the distance is large enough, the
signal line between the two outputs will act as a transmission line (Figure 6b). For the output in device 1 this doesn't
cause a problem, because it is at one end of the transmission line. However, device 2 is in the middle of the transmission line. The output in device 2 sees two transmission lines
in parallel. The result is that the output sees the equivalent
of a 25.0. transmission line for some length of time. This
causes impedance mismatches at the terminated load and
results in signal reflections.
Party lines
Zo
OUT
=50D.
Zo
J-...,.-a=====)--""~IN
=50D.
IN
OUT
son
50a
@
Zo
-2V
=50D.
®
-2V
OUT
OUT
CD
TL/D/1009B-10
TLlD/1009B-9
FIGURE6b
FIGURE6a
•
4-83
tions and disturbed signal integrity can result. A correct termination method for bus configurations is shown in Figure
7b. This configuration has only one terminated load and
maintains a 500 environment throughout.
Figure 78 shows an incorrect signal termination method.
The parallel terminations cause the impedance that the device output sees to drop to 16.70. An impedance mismatch
occurs at node A where the transmission lines split. Reflee-
Zo
=50.0.
ra:==:::::J~T-IINP
SOD.
-2V
Zo
=50.0.
+---a===:>--,-IINP
50.0.
-2V
Zo
=5.0.
L...a:==::J-1-l 'NP
50.0.
-2V
TUD/10D9B-11
FIGURE 7a. Incorrect (For High Speed Applications)
Zo
=50.0.
Zo
=50.0.
)"-"\1
Zo
J-'
~
--- INP
=50.0.
Zo =50.0.
Zo
= 50.0.
--~
-
~
INP
~
- INP
~
'--
INP
50.0.
-2V[]
TL/D/10D9B-12
FIGURE 7b. Eel Bussing Terminations
4-84
.
~
ECl PCB Design Considerations
inherent capacitive and inductive characteristics which can
load a PCB transmission line. What is desired from the system point of view is that the final or "loaded" impedance of
the board is equal to 50n. The capacitance of the device
affects the final impedance of the PCB. Figure 9 shows a
discrete RlCM model of the transmission line network
shown in Figure 8 and Figure 10 shows the effect of adding
a device to this network. Capacitors COl, C02 are the capacitances of two device inputs. These capacitors are parallel to the capacitors of the transmission line and thus increase the overall capacitance of the transmission line. The
inductors (lD1, lD2) are the inductances of two device inputs. Though these inductors are parallel to the transmission line, they do not affect the overall characteristics of the
transmission line because they lead into an open circuit
(they device itself). Consequently, the dominant effect of
adding devices to a PCB is the increased capacitance of the
PCB.
In order to design a printed circuit board for an ECl system,
many factors have to be considered. The ultimate goal is to
develop a PCB with transmission line impedances as close
to 50n as possible. In order to accomplish this, the geometry of the board itself and the properties of the ECl device
must be considered.
Figure 8 shows a PCB cross-section of several ,",strip transmission lines. The factors affecting the overall impedance of
the board are the metal thicknesses, widths, heights, and
spacings; and the dielectric constants and thicknesses of
the dielectric materials. For example, the impedance of a
microstrip line can be found from:
Zo = [87/v(er + 1.41)1* In [4.98h/(0.8w + t))
where h = dielectric thickness, w = trace width, t = trace
thickness, e r = dielectric constant of board material relative
to air.
Z
en
.......
Co)
This formula can be used to calculate the undisturbed or
"unloaded" impedance of the PCB. Packaged devices have
METAL
GND
TUD/10098-13
FIGURE 8. Geometric Model of PCB
RII
LI2
RI2
CGI Z I
LIX
CGl
RIX
son
xI
-2V
Ct.tlZx
RZ 2
LZX
CG2x I
RZx
50n
III
-ZV
TUD/10098-14
FIGURE 9. RlCM Network Model for PCB (Unloaded)
4-85
~
.....
r--------------------------------------------------------------------------,
i
LDI
+
.1.:
RI2
LIX
CGI
XI
CMI2
50.11
-2V
X
R22
L2X
CG2
RIX
XI
LD2
R2X
5011
-2V
+
.1:
TL/D/1009B-15
FIGURE 10. RLCM Network Model for PCB (Unloaded)
For example, an unloaded PCB transmission line could have
the following properties:
Co (characteristic capacitance) :::: 1.44 pF/cm
Lo (characteristic inductance) :::: 3.61 nH/cm
Since the impedance of a transmission line is equal to the
square root of inductance divided by the capacitance,
Modeling of Loaded Transmission Lines
Using the RlCM model shown in Figure 10, a SPICE model
can be constructed to evaluate the effects of increased de·
vice capacitance on the PCB.
Figures 11-13 show the output from such a SPICE model;
the transition modeled Is a low to high transition at nominal
ECl levels. The transmission line model was tuned to a
specific capacitance value for the device. As expected, the
SPICE output predicts an underdamped condition for the
unpopulated board (Figure 11). The transition first over·
shoots and then undershoots the nominal V,H level. As ca·
pacitance is added, the transition gets closer and closer to
the ideal matched condition. Figure 12 shows the effects of
an "overloaded" line. In this case, the capacitance of the
device is not totally compensated by the PCB. Consequent·
Iy, the signal undershoots and then overshoots the nominal
VIH level.
Figure 13 shows the resulting signal of a tuned "loaded"
transmission line. Due to the design of the transmission line,
the added capacitance of the device is compensated by the
intentional addition of increased line inductance.
Zo (characteristic impedance) :::: 50.10 [unloaded].
If we want to place 5 devices along this line (10 cm in
length) and each device has an input capacitance Cdut =
2 pF, the resulting impedance of the transmission line would
be:
Zo'(loaded) = v'(Lo)/v'(Co + Cdutl
= v' (3.61 nH/cm)/v'[1.44 pF/cm +
(2 pF/device • 5 devices/10 cm)]
:::: 36.50
This impedance is significantly lower than the 500 imped·
ance which is needed. Consequently, the designer must de·
sign his' unloaded board to a sufficiently high impedance so
that aiter the board is populated it will measure 500.
toUT = I pF , • r-~
-0.9V
L,..--Ti/l ,
Cour=DpF
-1.3V
'"
\
-I.IV (UNLOADED),
'
\
\
'
' .. '
I-f-==~~~=: ~~~S'-M-,SS-IO-NI------i
LINE
-1.5V I--ff--if--i--\---I
-1.7V I--f---t----t----t---I
Ons
Ins
2ns
FIGURE 11
4·66
3ns
TLlD/10098-16
...,;!
-O.9V
I'rt-- ~-""
~'\,-
-I.W
~
I
-1.3V
-1.5V
\
----
-O.9V
-I.IV
=4pF
=3pF
COUT
COUT
-1.3V
j
I
I
-1.5V
1 "\
\
1
COUT =2pF
1
1
I
/..... IDEAL I
II
TRANi MISSION _
LINE
-1.7V
-1.7V
ons
1 ns
2 ns
ons
3 ns
1 ns
2 ns
I
3 n.
TLIDll0098-18
TLlDll0098-17
FIGURE 12
FIGURE 13
For maximum performance, layout and construction requirements on printed circuit boards for next generation systems
must become more demanding. While at first glance, designing with Eel devices poses more difficulties for a system designer than TIL devices, if the goal is to obtain high
system performance then Eel devices offer significant ad-
vantages. Because of the fact that they are designed specifically for high speed environments, the Eel device is easier
to integrate into a high speed system. With the geometries
and characteristics of the printed circuit board and the device considered as a unit, a network can be designed to
produce a clean controlled impedance environment for an
Eel device much easier than for a comparable TIL device.
Summary
4-87
Section 5
TTL 1/0 Static RAMs
Section 5 Contents
TTL I/O-MOS SRAM Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIPOLAR STATIC RAMS
DM54S189/DM74S189 64-Sit (16 x 4) TRI-STATE RAM... . . . .. . . .. . . . . . . . . . .. . .. .. .. . . .
DM54S189A/DM74S189A High Speed 64-SitTRI-STATE RAM..........................
DM74S289 64-Bit (16 x 4) Open Collector RAM.. . .. . .... .. ... . . .. . . . . . . . .. . . . . . . . . .. . .
93L415A 1024 x 1-Bit Static Random Access Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93L422A 256 x 4-Bit Static Random Access Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93L425A 1024 x 1-Bit Static Random Access Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93479256 x 9-Bit Static Random Access Memory. .. . . .. . . . .. . .... . .. . . . . ... . .. .. . . .. ..
MOS STATIC RAMS
MM54174C89 65-Bit TRI-STATE Random Access Read/Write Memory. . . . . . . . . . . . .. .. . . .
MM54174C200 256-Bit TRI-STATE Random Access Read/Write Memory.. . .. . . .. ... . . . . .
MM54174C910 256-BitTRI-STATE Random Access Read/Write Memory.................
MM54174C989 64-Bit (16 x 4) TRI-STATE Random Access Memory. . .. . .. . . . . . .. . . .. . . . .
NMC2147H 4096 x 1-Bit Static RAM. . . . . .... . .. . ... .. . . . . .. . .. .. . .. . .. . . . .. .. . . . .. . . .
NMC2148H 1024 x 4-Bit Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDGE TRIGGERED REGISTERS
DM75S68/68A185S68/68A 16 x 4 Edge Triggered Registers ............................
5-2
5-3
5-4
5-4
5-11
5-15
5-20
5-26
5-32
5-39
5-44
5-48
5-53
5-57
5-62
5-67
~Nationai
Semiconductor
TTL I/O-MOS Static RAM Selection Guide
Access
Time
Temperature Range
16
50
-55·Cto +125·C
16
30
-55·C to + 125·C
TS
16
35
O·Cto +70·C
16x4
TS
16
25
O·Cto +70·C
DM74S289
16x4
OC
16
35
O·Cto +70·C
93L415A
1kx 1
OC
16
25ns
O·Cto +70·C
93L422A
256x4
TS
22
25 ns
O·Cto +70·C
93L425A
1kx 1
TS
16
25 ns
O·Cto +70·C
256x9
TS
22
25 ns
O·Cto +70·C
NMC2147H
4kx 1
TS
18
70
O·Cto +70·C
NMC2147H-3
4kx 1
TS
18
55
O·Cto +70·C
NMC2147H-2
4kx 1
TS
18
45
O·Cto +70·C
NMC2147H-1
4kx 1
TS
18
35
O·Cto +70·C
NMC2147H-3L
4kx 1
TS
18
55
O·Cto +70·C
NMC2148H
1kx4
TS
18
70
O"Cto +70·C
NMC2148H-3
1kx4
TS
18
55
O·Cto +70·C
O·Cto +70·C
Organization
Outputs
Pins
DM54S189
16x4
TS
DM54S189A
16x4
TS
DM74S189
16x4
DM74S189A
Part Number
TTL I/O STATIC RAMS
93479
MOS STATIC RAMS
NMC2148H-2
1kx4
TS
18
45
NMC2148H-1
1kx4
TS
18
70
O·Cto +70·C
NMC2148H-3L
1kx4
TS
18
55
O·Cto +70·C
DM75S68
16kx4
TS
16
55
- 55°C to + 125·C
DM75S68A
16kx4
TS
16
45
-55·Cto +125·C
DM85S68
16kx4
TS
16
40
O"Cto +70"C
DM85S68A
16kx4
TS
16
24
O"Cto +70·C
EDGE-TRIGGERED REGISTERS
•
5-3
~National
~ Semiconductor
DM54S189/DM74S189 64-Bit (16 x 4) TRI-STATE® RAM
DM54S189A/DM74S189A High Speed 64-Bit
TRI-STATE RAM
General Description
These 64-bit active-element memories are monolithic
Schottky-clamped transistor-transistor logic (TTL) arrays organized as 16 words of 4 bits each. They are fully decoded
and feature a chip-enable input to simplify decoding required to achieve the desired system organization. The
memories feature PNP input transistors that reduce the low
level input current requirement to a maximum of -0.25 mA,
only one-eighth that of a DM74S standard load factor. The
chip-enable circuitry is implemented with minimal delay
times to compensate for added system decoding.
The TRI-STATE output combines the convenience of an
open-collector with the speed of a totem-pole output; it can
be bus-connected to other similar outputs; yet it retains the
fast rise time characteristics of the TTL totem-pole output.
Systems utilizing data bus lines with a defined pull-up impedance can employ the open-collector DM74S289.
Write Cycle: The complement of the information at the data
input is written into the selected location when both the
chip-enable input and the read/write input are low. While
the read/write input is low, the outputs are in the high-impedance state. When a number of the DM74S189 outputs
are bus connected, this high-impedance state will neither
load nor drive the bus line, but it will allow the bus line to be
driven by another active output or a passive pull-up if desired.
Read Cycle: The stored information (complement of information applied at the data inputs during the write cycle) is
available at the outputs when the read/write input is high
and the chip-enable is low. When the chip-enable is high,
the outputs will be in the high-impedance state.
The fast access time of the DM74S189A makes it particularly attractive for implementing high-performance memory
functions requiring access times less than 25 ns. The high
capacitive drive capability of the outputs permits expansion
without additional output buffering. The unique functional
capability of the DM74S189A outputs being at a high-impedance during writing, combined with the data inputs being
inhibited during reading, means that both data inputs and
outputs can be connected to the data lines of a bus-organized system without the need for interface circuits.
Features
• Schottky-clamped for high speed applications (SI89A)
Access from chip-enable input
17 ns max
Access from address inputs
25 ns max
• TRI-STATE outputs drive bus-organized systems and/or
high capacitive loads (SI89, S189A)
• DM74S289 are functionally equivalent and have opencollector outputs
• DM54SXXX is guaranteed for operation over the full
military temperature range of - 55'C to + 125'C
• Compatible with most TTL circuits
• Chip-enable input simplifies system decoding
Connection Diagram
T
v
CC
1&
.
Truth Table
Dual-In-Llne Package
SELECT INPUTS
D'
B
15
14
13
Inputs
Function
DATA
INPUT
OUTPUT
DATA
INPUT
OUTPUT
4
V4
3
V3
12
11
10
Write (Store
Complement of Data)
Chip- Readl
Enable Write
L
Output
L
High-Impedance
Read
L
H
Stored Data
Inhibit
H
x
High-Impedance
H
= High Level, L = Low Level. X = Don'\ Care
Order Number DM54S189J, DM54S189AJ,
DM74S189J, DM74S189AJ,
DM74S189N or DM74S189AN
See NS Package Number J16A or N16E
SELECT CHIP
INPUT A ENABLE
REAOI
WRITE
DATA
INPUT
I
OUTPUT
VI
DATA
INPUT
2
OUTPUT
V2
01;
TLlD/9232-1
Top View
5-4
Absolute Maximum Ratings
Operating Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, Vee
7.0V
Input Voltage
5.5V
Output Voltage
5.5V
Storage Temperature Range
- 65·C to + 150·C
Lead Temperature (Soldering, 10 sec.)
Min
Max
Units
Supply Voltage (Vecl
DM54S189
DM74S189
4.5
4.75
5.5
5.25
V
V
Temperature (TA)
DM54S189
DM74S189
-55
0
+125
+70
·C
·C
+300·C
DM54S189, DM74S189 Electrical Characteristics
over recommended operating free-air temperature range unless otherwise noted (Notes 2 and 3)
Symbol
Parameter
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
VOH
High Level Output
Voltage
Conditions
Vee = Min
Max
Units
0.8
V
V
IOH = -2.0 mA,
DM54S189
2.4
3.4
V
IOH = -6.5 mA,
DM74S189
2.4
3.2
V
Vee = Min
Low Level Output
Voltage
Vee = Min,
10l = 16mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
II
High Level Input Current
at Maximum Voltage
Vee = Max, VI = 5.5V
III
Low Level Input Current
Vee = Max, VI = 0.45V
los
Short Circuit Output
Current (Note 4)
Vee = Max,
Vo = OV
VOL
Typ
2
High Level Output Current
Open Collector Only
leEX
Min
VOH = 2.4V
40
VOH = 5.5V
100
p.A
DM54S189
0.5
V
DM74S189
0.45
V
25
p.A
1.0
mA
-250
p.A
-100
mA
DM54S189,
DM74S189
-30
75
lee
Supply Current (Note 5)
Vee = Max
Vie
Input Clamp Voltage
Vee = Min, 11= -18 mA
10ZH
TRI-STATE Output Current,
High Level Voltage Applied
Vee = Max.
Vo = 2.4V
DM54S189,
DM74S189
10Zl
TRI-STATE Output Current.
Low Level Voltage Applied
Vee = Max,
Vo = 0.45V
DM54S189,
DM74S189
CIN
Input Capacitance
Vee = 5V, VIN = 2V.
TA = 25·C.1 MHz
4.0
pF
Co
Output Capacitance
Vee = 5V, Vo = 2V.
TA = 25·C. 1 MHz,
Output "Off"
6.0
pF
-50
110
mA
-1.2
V
50
p.A
p.A
•
5-5
DM74S 189 Switching Characteristics
over recommended operating ranges of TA and Vcc unless otherwise noted
DM74S189
DM54S189
Symbol
Parameter
Conditions
Min
tAA
Access Times from Address
tCZH
Output Enable Time to
High Level
tCZL
Output Enable Time to
Low Level
tWZH
Output Enable Time to
High Level
tWZL
Output Enable Time to
Low Level
teHZ
Output Disable Time
from High Level
teLZ
Output Disable Time
from Low Level
tWHZ
Output Disable Time
from High Level
Access Times from
Chip-Enable
Units
Max
CL = 30pF,
RL = 2800
25
50
25
35
ns
(Rgure4)
12
25
12
17
ns
12
25
12
17
ns
13
35
13
25
ns
13
35
13
25
ns
12
25
12
17
ns
12
25
12
17
ns
15
35
15
25
ns
15
35
15
25
ns
Sense Recovery Times
from Read/Write
Disable Times from
Chip-Enable
Typ
Typ
Max Min
(Note2)
(Note 2)
CL = 5pF,
RL = 2800
(Figure 4)
Disable Times from
Read/Write
twLZ
Output Disable Time
from Low Level
twp
Width of Write Enable Pulse (Read/Write Low)
25
25
tASW
Set-Up Time (Figure 1) Address to Read/Write
0
0
ns
tDSW
Data to Read/Write
25
25
ns
tcsw
Chip-Enable to
Read/Write
0
0
ns
Address from Read/Write
0
0
ns
tDHw
Data from Read/Write
0
0
ns
teHw
Chip-Enable from
Read/Write
0
0
ns
tAHW
Hold Time (Figure 1)
5-6
ns
Absolute Maximum Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, Vee
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
7.0V
5.5V
5.5V
-65'C to + 150'C
Min
Mall
Units
Supply Voltage (Veal
DM54S189(A)
DM74S189(A)
4.5
4.75
5.5
5.25
V
V
Temperature (TAl
DM54S189(A)
DM74S189(A)
-55
0
+125
+70
'C
'C
+300'C
DM54S189A, DM74S189A Electrical Characteristics
over recommended operating free-air temperature range unless otherwise noted (Notes 2 and 3)
Symbol
VIH
Parameter
Conditions
Vil
Low Level Input Voltage
VOH
High Level Output
Voltage
Typ
Max
2
Vee = Min
IIH
High Level Input Current
Vee = Max, VI = 2.4V
II
High Level Input Current
at Maximum Voltage
Vee = Max, VI = 5.5V
III
Low Level Input Current
Vee = Max, VI = 0.40V
los
Short Circuit Output
Current (Note 4)
Vee = Max, Vo = OV
Units
V
0.8
Vee = Min
Low Level Output
Voltage
VOL
Min
High Level Input Voltage
V
IOH = -2.0 mA,
DM54S189A
2.4
3.4
V
10H = -6.5 mA,
DM74S189A
2.4
3.2
V
10l = 16mA
0.45
10l = 20mA
0.5
-20
V
10
",A
1.0
mA
-250
",A
-90
mA
lee
Supply Current (Note 5)
Vee = Max
Vie
Input Clamp Voltage
Vee = Min, 11= -18 mA
10ZH
TRI-STATE Output Current,
High Level Voltage Applied
Vee = Max, Vo = 2.4V
10Zl
TRI-STATE Output Current,
Low Level Voltage Applied
Vee = Max, Vo = 0.4V
CIN
Input Capacitance
Vee = 5V, VIN = 2V,
TA = 25'C, 1 MHz
4.0
pF
Co
Output Capacitance
Vee = 5V, Vo = 2V,
TA = 25'C, 1 MHz,
Output "Off"
6.0
pF
75
5-7
-40
100
mA
-1.2
V
40
",A
",A
c(
en
co
~
.....
:E
C
.......
c(
en
co
,..
(/)
oo:r
II)
DM54S 189A, DM7 4S 189A Switching Characteristics
over recommended operating ranges of TA and Vcc unless otherwise noted
DM54S189A
Symbol
tAA
Access Time from Address
tCZH
Output Enable Time to
High Level
C
.......
en
(/)
oo:r
.....
tCZl
Output Enable Time to
Low Level
tWZH
Output Enable Time to
High Level
:E
C
.......
en
co
,..
tWZl
Output Enable Time to
Low Level
(/)
tCHZ
Output Disable Time
from High Level
oo:r
II)
:E
C
Conditions
Min
:E
co
,..
Parameter
tClZ
Output Disable Time
from Low Level
tWHZ
Output Disable Time
from High Level
Access Times from
Chip-Enable
Cl = 30pF.
Rl = 280n
(Figure 4)
Sense Recovery Times
from Read/Write
Disable Times from
Chip-Enable
Cl = 5pF.
Rl = 280n
(Figure 4)
Disable Times from
Read/Write
DM74S189A
Typ
(Note 2)
Max
20
Units
Typ
(Note 2)
Max
30
20
25
ns
11
25
11
17
ns
11
25
11
17
ns
13
35
13
25
ns
13
35
13
25
ns
12
25
12
17
ns
12
25
12
17
ns
15
35
15
25
ns
15
35
15
25
ns
Min
tWlz
Output Disable Time
from Low Level
twp
Width of Write Enable Pulse (Read/Write Low)
25
20
ns
tASW
Set-Up Time (Figure 1)
Address to Read/Write
0
0
ns
tosw
Data to Read/Write
25
20
ns
tcsw
Chip-Enable to
Read/Write
0
0
ns
Address from Read/Write
0
0
ns
tOHW
Data from Read/Write
0
0
ns
tCHW
Chip-Enable from
Read/Write
0
0
ns
tAHW
Hold Time (Figure 1)
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified min/max limits apply across the -SS'C to + 12S'C temperature range for the
range for the DM74S189(A). All typicals are given for Vee ~ S.OV and TA ~ 2S'C.
OMS4S189(A)
and across the
O'C to + 70'C
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: ICC is measured with all inputs grounded; and the outputs open.
5-8
DM54S189(A), DM74S189(A) Switching Time Waveforms
Enable and Disable Time from Chip-Enable
CHIP ENABLE
INPUT (NOTE 31
3V
Ov------~-,----~------------'
~.5V
WAVEFORM 1
INOTE 11
VOL
WAVEFORM 2
(NOTE 11
VOl<
"<=1,5V
TL/D/9232-2
Access Time from Address Inputs
ADDRESS
INPUTS
INOTE 21
3V~""_ _ -----",,~
I.
ov __
LW
J '
IAA
::::::l
~5V
'------_.
IAA
I ___
OH
OUTPUT V
------y.5V
VOL ____________________,._ _ _ _ _ _ _ _ _
J
TL/D/9232-3
Write Cycle
3V
ADDRESS
INPUTS
DATA
INPUTS
3V
CHIP ENABLE
INPUT
DV
3V
REAO,wRITE
INPUT
DV
~1.5V
WAVEFORM I
(NOTE 11
VOL
------------r------r-"..--t----..ri---:-:-.
-------+---'-
WAVEFORM 2 VOH - - - - - - - - - (SIOPEN.
S2 CLOSEOI
(NOTE 11 >I.5V ----------------------~,-......- - - -.......~.....::l_
TLlD/9232-4
FIGURE 1
Note 1: Waveform 1 is for the output with internal conditions such that the output is low except when disabled. Waveform 2 is for the output with internal conditions
such that the output is high except when disabled.
Note 2: When measuring delay times from address inputs, the chip·enable input is low and the read/write input is high.
Note 3: When measuring delay times from chip-enable input, the address inputs are steady-state and the read/write input is high.
Note 4: Input waveforms are supplied by pulse generators having the following characteristics: tr ,; 2.5 ns, tl ,; 2.5 ns, PRR ,; 1 MHz and ZOUT ~ '"
5-9
son.
Block Diagram
A
B
ADDRESS
INPUTS
15
14
64-BIT MEMORY
MATRIX
ORGANIZED
16.4
ADDRESS
BUFFERS
C
o
13
4
~:O~__+-_+-....
DATA INPUTS { : :
12
D4~-----i---+---+-J
11
Yl
\
Y2
Y3
Y4,
OUTPUTS
TLlD/9232-5
FIGURE 3
AC Test Circuits
DM54S189(A}/DM74S 189(A}
Vee
TEST
POINT
FROM
OUTPUT _ ...._ _....
UNDER
TEST
-+.._.
CL includes probe and jig capacitance.
All diodes are 1N3064.
TL/D/9232-6
FIGURE 4
5·10
~National
~
Semiconductor
DM74S289
64-Bit (16 x 4) Open-Collector RAM TRI-STATE® RAM
General Description
These 64-bit active-element memories are monolithic
Schottky-clamped transistor-transistor logic (TTL) arrays organized as 16 words of 4 bits each. They are fully decoded
and feature a chip-enable input to simplify decoding required to achieve the desired system organization. The
memories feature PNP input transistors that reduce the low
level input current requirement to a maximum of - 25 mA,
only one-eighth that of a DM74S standard load factor. The
chip-enable circuitry is implemented with minimal delay
times to compensate for added system decoding.
Write Cycle: The complement of the information at the data
input is written into the selected location when both the
chip-enable input and the read/write input are low. While
the read/write input is low, the outputs are in the highimpedance state. When a number of the DM74S289
Connection Diagram
outputs are bus connected, this high-impedance state will
neither load nor drive the bus line, but it will allow the bus
line to be driven by another active output or a passive pullup if desired.
Read Cycle: The stored information (complement of information applied at the data inputs during the write cycle) is
available at the outputs when the read/write input is high
and the chip-enable is low. When the chip-enable is high,
the outputs will be in the high-impedance state.
Features
•
•
•
•
Commercial address access time 25 ns
Features open-collector output
Compatible with most TTL circuits
Chip-enable input simplifies system decoding
Truth Table
inputs
Dual-in-Line Package
.
SELECT INPUTS
Vr16
,
D
15
14
13
DATA
INPUT
4
DUTPUT
V4
12
"
DATA
INPUT
3
Function
DUTPUT
V3
Write (Store
Complement of Data)
10
READI
WRITE
DATA
INPUT
DUTPUT
VI
I
DATA
INPUT
DUTPUT
VZ
2
TL/D/9693-1
Top View
Order Number DM74S289J or DM74S289N
See NS Package Number J16A or N16E
5-11
Output
L
L
High-Impedance
Read
L
H
Stored Data
Inhibit
H
X
High-Impedance
H
SELECT
CHIP
INPUT A ENABLE
Chip- Readl
Enable Write
= High Level, L = Low Level, X = Don'l Care
Absolute Maximum Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, Vcc
7.0V
Input Voltage
5.5V
Output Voltage
5.5V
Storage Temperature Range
- 65'C to + 150'C
Lead Temperature (Soldering 10 Sec.)
+300'C
Supply Voltage (Vccl
DM74S289
Temperature (TAl
DM74S289
Min
Max
Units
4.75
5.25
V
0
+70
'C
DM74S289 Electrical Characteristics
Over recommended operating free·air temperature range unless otherwise noted (Notes 2 and 3)
VIH
Symbol
Parameter
High Level Input Voltage
VIL
Low Level Input Voltage
VOH
ICEX
High Level Output Voltage
Conditions
Min
Typ
Max
O.B
High Level Output Current
VOL
Low Level Output Voltage
IIH
II
IlL
High Level Input Current
High Level Input Current
at Maximum Voltage
Low Level Input Current
Icc
Supply Current (Note 4)
VIC
Input Clamp Voltage
CIN
Co
Input Capacitance
Vcc
Vcc
= -6.5mA
VOH = 2.4V
VOH = 5.5V
= Min
= Min
IOH
2.4
Output Capacitance
3.2
= Min,loL = 16 mA
= Max, VI = 2.7V
Vee = Max, VI = 5.5V
Vcc
Vec
= Max, VI = 0.45V
= Max
= Min,ll = -1B mA
Vee = 5V, VIN = 2V, T A = 25'C, 1 MHz
Vee = 5V, Vo = 2V,
TA = 25'C, 1 MHz, Output "Off"
Vcc
75
V
V
40
100
Vcc
Vcc
Units
V
2
p.A
0.45
V
25
p.A
1.0
mA
-250
p.A
110
-1.2
mA
4.0
V
pF
6.0
pF
DM74S289 Switching Characteristics
Over recommended operating ranges of TA and Vee unless otherwise noted
Symbol
Parameter
Conditions
Min
tAA
Access Time from Address
tcHL
Enable Time from
Chip·Enable
Enable Time from
Read/Write
twHL
tcLH
tWLH
twp
tASW
tDSW
tcsw
tAHW
tDHw
Sense Recovery Time
from Read/Write
CL = 30pF,
RL1 = 3000,
RL2 = 6000
(Figure 4)
Disable Time from Chip-Enable
Disable Time from Read/Write
Width of Enable Pulse (Read/Write Low)
Setup Time (Figure 2)
Address to Read/Write
Hold Time (Fl{Jure 2)
DM74S289
Typ
(Note 2)
Units
Max
25
35
ns
12
17
ns
12
25
ns
12
13
20
ns
ns
25
25
ns
0
ns
Data to Read/Write
Chip-Enable to Read/Write
25
0
ns
ns
Address from Read/Write
0
0
ns
Data from Read/Write
ns
Chip-Enable from Read/Write
0
ns
tCHW
Note 1: "Absolute Maximum Ra~ngs" are those values beyond which the safety of the device cannot be guaranteed Except for "Operating Temperature Range
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteris~cs provides conditions lor actual device
operation.
Note 2: Unless othelWise specified minImax limits apply across the -55'C to + 125'C temperature range for the DM54S189 and across the O"C to -70"C range
for the DM74S189/289. All typicals are given for Vee = 5.0V and TA = 25·C.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unle.s othelWise noted. All values shown
as max or min on absolute value basis.
Note 4: lee is measured with all Inputs grounded, and the outputs open.
5-12
DM74S289 Switching Time Waveforms
Enable and Disable Time from Chip-Enable
CHIP ENABLE
INPUT
(NOTE 3)
3V
1=
OV
:i}-
~,t
VOH
WAVEFORM I
(NOTE 11
1.5V
1.5V
VOL
TLiD/9693-2
Access Time from Address Inputs
3V~_-------'{
ADDRESS
INPUTS
,
(NOTE Z) OV _ _ J
~
ID
' - - ____ .
1AA::::I
~5V
OH
OUTPUT V - - - - - - - VOL ___________________
~.~
-IAA
I
r--
J1.5V
______________
J
TLiD/9693-3
Write Cycle
3V
ADDRESS
INPUTS
3V
DATA
INPUTS
3V
CHIP ENABLE
INPUT
OV
3V
READ/WRITE
INPUT
OV
/--IwLH--'
VOH
WAVEFDRM I
(NOTE I)
VOL
-"'~
---I).'
1.5V
TLiO/9693-4
FIGURE 2
Note 1: Waveform I Is for the output with internal condijions such that the output is low except when disabled.
Note 2: When measuring delay times from address inputs, the chip-enable is low and the read/write Input is high.
Note 3: When measuring delay times from chip-enable input, the address inputs are steady·state and the read/write input Is high.
Note 4: Input waveforms are supplied by pulse generators having the following characteristics Ir
5-13
,;;
2.5 ns, tf ,;; 2.5 ns. PRR ,;; 1 MHz and ZOUT
~
son.
I
Block Diagram
21
ADDRESS
INPUTS
64·BIT MEMDRV
MATRIX
ORGANIZED
1604
ADDRESS
BUFFERS
4
DATA INPUTS
{~: _~~O:-
_ _f-_+-..1
12
D4-----__
~__~--~
11
\
VI
V2
V3
V4/
OUTPUTS
TL/D/9693-5
FIGURE 3
AC Test Circuit
Vee
FROM
O~:~~~
___..._____
TEST
TL/D/9693-6
5-14
, - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - , U)
Co)
...
!;
~National
~
~ Semiconductor
93L415A 1024 X 1-Bit
Static Random Access Memory
General Description
Features
The 93L415A is a 1024-bit read write Random Access
Memory (RAM), organized 1024 words by one bit. It is designed for high speed cache, control and buffer storage applications. The device includes full on-Chip decoding, separate Data input and non-inverting Data output, as well as an
active LOW Chip Select line.
•
•
•
•
New design to replace old 93415/93L415
Improved ESD thresholds
Alpha hard without die coat
Commercial address access time
93L415A
25 ns max
• Features open collector output
• Power disSipation decreases with increasing
temperature
Connection Diagram
16-Pin DIP
CS-l
AO- 2
Al- 3
A2A3A40GND-
'-../
16 -Vee
15 -D
14 -WE
13 -A9
12 -AS
ll-A7
10 -A6
4
5
6
7
S
9 -AS
TLlD/l0D03-1
Top View
Order Number 93L415ADC or 93L415APC
See NS Pacl(age Number J16A· and N16E*
Optional Processing QR
= Bum-In
'For most current package Information, contact product marketing.
logic Symbol
Pin Names
2 - AO CS
3 - AI
4 - A2
5 - A3
6 - A4
9 - AS
10- A6
11- A7
12- AS
13- A9
D
WE
93L41SA
CS
Chip Select Input
Active LOW
AO-A9
Address Inputs
WE
Write Enable Input
Active LOW
D
Data Input
o
Data Output
o
TLlD/l0003-3
vee = Pin 16
GND = Pin 8
5-15
III
Absolute Maximum Ratings
Guaranteed Operating Ranges
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Above which the useful life may be impaired
Storage Temperature
- 65'C to + 150'C
Supply Voltage Range
-0.5Vto +7.0V
Input Voltage (DC) (Note 1)
-0.5VtoVee
Input Current (DC)
-12 mA to +5.0 mA
Voltage Applied to Outputs
(Note 2)
-0.5V to 5.5V
Lead Temperature (Soldering, 10 sec.)
300'C
Maximum Junction Temperature (TJ)
+ 175'C
Output Current
+20mA
Supply Voltage (Vee)
Commercial
5.0V ±5%
Case Temperature (Tel
Commercial
O'Cto +75'C
DC Characteristics over operating temperature ranges (Note 3)
Symbol
Parameter
Conditions
=
=
VOL
Output LOW Voltage
Vee
VIH
Input HIGH Volt~ge
Guaranteed Input HIGH Voltage
for All Inputs (Notes 4, 5, & 6)
VIL
Input LOW Voltage
Guaranteed Input LOW Voltage
for All Inputs (Notes 4, 5, & 6)
IlL
Input LOW Current
Vee
IIH
Input HIGH Current
Vee
Min,loL
=
=
Max, VIN
=
=
Vee =
Vee =
Max, VIN
=
=
Input Breakdown Current
Vee
Max, VIN
Input Diode Clamp Voltage
Vee
Max,llN
leEX
Output Leakage Current
lee
Power Supply Current
Output is Open
5-16
Typ
16mA
Max
Units
0.45
V
0.8
V
2.1
0.4V
-180
-300
p.A
4.5V
1.0
40
p.A
1.0
mA
-1.0
-1.5
V
1.0
100
p.A
65
mA
= Vee
= -10 mA
Max, VOUT = 4.5V
Max, All Inputs = GND
IIHB
Vie
Min
AC Electrical Characteristics (Note 6) Vcc =
Symbol
5.0 ± 5%, GND = OV, Tc = O'C to
Parameter
Conditions
Min
+ 75'C
Max
Units
15
ns
15
ns
25
ns
READ TIMING
tACS
Chip Select Access Time
tRCS
Chip Select Recovery Time
tAA
Address Access Time (Note 7)
Figures
3a,3b
WRITE TIMING
Write Pulse Width to Guarantee
Writing (Note 8)
20
ns
tWSD
Data Setup Time Prior to Write
5
ns
tWHD
Data Hold Time after Write
5
ns
tWSA
Address Setup Time Prior
to Write (Note 8)
5
ns
ns
tw
Figure 4
tWHA
Address Hold Time after Write
5
tWSCS
Chip Select Setup Time Prior to Write
5
ns
5
ns
tWHCS
Chip Select Hold Time after Write
tws
Write Enable to Output Disable
15
ns
tWR
Write Recovery Time
15
ns
Note 1: Either input voltage limit or input current limit sufficient to protect the inputs.
Note 2: Output current limit required.
Note
3: Typical values are at Vce = S.OV, Te = + 2S'C and maximum loading.
Note 4: Tested under static condition only.
Note
5: Functional testing done at input levels VIL = O.4SV (VOL Max) and VIH = 2.4V (VOH Min).
= 3V, VIL = OV.
Note 6: AC testing done at input levels VIH
Note 7: The maximum address access time is guaranteed to be the worst case bit in the memory using a pseudorandom testing pattern.
Note 8: tw measured at tWSA = Min. twSA measured at tw
= Min.
5-17
~r-------------------------------------------------------'
~
Logic Diagram
C")
G)
ADDRESS
DECODER
WDRD
DRIVER
32x32 ARRAY
0
cs
SENSE AMPS
&:
WRITE DRIVERS
WE
D
ADDRESS
DECODER
AS A6 A7 A8 A9
TL/D/10003-2
(AO through A9). To assure a valid write, data setup (tW50),
address setup (twsAl, data hold (tWHO), and address hold
(tWHA) times must be met. When WE is held HIGH and the
chip selected, data is read from the addressed location and
presented at the output O.
Truth Table
Outputs
Inputs
CS
WE
D
0
H
L
L
L
X
X
L
L
H
L
H
H
H
H
X
OOUT
Mode
An open collector output is provided to allow maximum flexibility in output connection. In many applications such as
memory expansion, the outputs of many 93L415As can be
tied together. In other applications the wired-OR is not used.
In either case an external pull-up resistor of RL value must
be used to provide a HIGH at the output when the chip is
deselected. Any RL value within the range specified below
may be used.
Not Selected
Write "0"
Write "1"
Read
H = HIGH Voltage Level: 2.4V
L = LOW Voltage Level: O.45V
X = Oon't Care (HIGH or LOW)
Functional Description
Vee (Max)
IOL - FO (1.6)
The 93L415Pi is a fully decoded 1024-bit read/write Random Access Memory organized 1024 words by one bit. Bit
selection is achieved by means of a 10-bit address AO
through A9.
S;
R
S;
L
Vee (Min) - VOH
n (leEXl + FO (0.04)
RL is in kG
n = number of wired-OR outputs tied together
FO = number of TTL Unit Loads (UL) driven
leEX = Memory Output Leakage Current
VOH = Required Output HIGH Level at Output Node
IOL = Output LOW Current
One Chip Select input is provided for easy memory array
expansion of up to 2048 bits without the need for external
decoding. For larger memories, the fast chip select access
time permits direct address decoding without an increase in
overall memory access time.
The read and write functions of the 93L415A are controlled
by the state of the active low chip select (CS) input. The
write function is controlled by the active low write enable
(WE) input. With CS held low and WE held low, the data (D)
is written into the memory location specified by addresses
The minimum RL value is limited by the output current sinking ability. The maximum RL value is determined by the output and input leakage current which must be supplied to
hold the output at VOH.
One Unit Load = 40 fI-A HIGH/1.6 mA LOW.
FOMAX = 5 UL.
5-18
r-------------------------------------------------------------------------------------,
U)
Co)
...
Functional Description (Continued)
!;
~
Vee
30OD.
93L415A
30'pF
TlID/l0003-4
Tl/D/l0003-5
'Includes jig and probe capacitance
FIGURE 2. AC Test Input Levels
FIGURE 1. AC Test CIrcuit
...w~"I
DATA OUTPUT
1.5V
TlID/l0003-7
TlID/l0003-6
b. Read Mode Propagation Delay
from Address Valid
FIGURE 3. Read Mode Timing
a. Read Mode Propagation Delay from Chip Select
CHIP SELECT
1.5V
1.5V
ADDRESS
DATA INPUT
._---. -----
1.5V
-_ . ,-------------------------,
. _- ----- ------tw
1.5V
WRITE ENABLE
tWHD
,..::.:..:::0.
~
- tWHA - tWHcs -------tWR
-1wsA-twscs
.'.
tws
DATA OUTPUT - - - - - - -_ _ _ _ _
1~O...5-V----------~
_ _ __
TlID/l0003-B
FIGURE 4. Write Mode TimIng
Note 1: Timing Diagram represents one solution which results in an optimium cycle time. Timing may be changed to
fit various applications as long as the worst case limits are not violated.
Note 2: Input voltage levels for worst case AC test are 3.0V/OV.
•
5·19
~ ~NaHonal
~ ~
Semiconductor
93L422A
256 x 4-Bit Static Random Access Memory
General Description
Features
The 93L422A is a 1024-bit read/write Random Access
Memory (RAM) organized 256 words by four bits. It is designed for high speed cache, control and buffer storage applications. The device includes full on-chip decoding, separate Data input and non-inverting Data output, as well as
two Chip Select lines.
•
•
•
•
New design to replace old 93422/93L422
Improved ESD thresholds
Alpha hard without die coat
Commercial address access time
93L422A
25 ns
• Fully TTL compatible
• Features TRI-STATECIl outputs
• Power dissipation decreases with increasing temperature
Connection Diagram
Pin Names
22-PinDIP
AS-I
'-"
A2- 2
22 -Vee
21 -A4
Al- 3
20
AO-A7
Address Inputs
00-03
Data Inputs
CS1
Chip Select Input (Active LOW)
AS- 5
-ViE
19 -CSl
18 -Of
CS2
Chip Select Input (Active HIGH)
A6- 6
17 -CS2
WE
Write Enable Input (Active LOW)
AO- 4
A7- 7
16 -03
GND- 8
15 -03
00- 9
14 -02
00- 10
Dl- 11
13 -D2
Output Enable Input (Active LOW)
00-03
Data Outputs
12 -01
TL/O/9996-1
Top View
Order Number 93L422ADC or 93L422APC
See NS Package Number J22A' or N22A'
Optional Processing OR = Bum·ln
'For most current package Information, contact product marketing
Logic Symbol
CS
(4)
(3)
(2)
(t)
(23)
(5)
(6)
(7)
432121567-
WE 00 Dl D2 D3
AO
AI
A2
AS
A4
AS
A6
A7
93L422A
OE 00 01 02 03
! l1LLt
(20)(10)(14)(16)(18)
5-20
TUO/9996-3
Absolute Maximum Ratings
Guaranteed Operating Ranges
Above which the useful life may be impaired
Supply Voltage (Vee)
Case Temperature (Tcl
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
-65'C to + 150'C
-0.5Vto +7.0V
Supply Voltage Range
Input Voltage (DC) (Note 1)
-0.5V to Vee
Input Current (DC)
-12 mA to +5.0 mA
Voltage Applied to Outputs (Note 2)
-0.5Vto +5.5V
Lead Temperature (Soldering, 10 sec.)
Maximum Junction Temperature (TJ)
Output Current
5.0V ±5%
O'Cto +75'C
300'C
+ 175'C
+20mA
DC Characteristics over operating temperature ranges (Note 3)
Symbol
Parameter
Conditions
=
=
VOL
Output LOW Voltage
Vee
VIH
Input HIGH Voltage
Guaranteed Input HIGH Voltage
for All Inputs (Notes 4, 5 & 6)
VIL
Input LOW Voltage
Guaranteed Input LOW Voltage
for Allinpuis (Notes 4, 5 & 6)
VOH
Output HIGH Voltage
=
Vee =
Vee =
Vee =
Vee =
Vee =
Vee =
Vee =
IlL
Input LOW Current
IIH
Input HIGH Current
IIHB
Input Breakdown Current
VIC
Input Diode Clamp Voltage
10ZH
Output Current (HIGH Z)
10ZL
los
Output Current Short
Circuit to Ground
Icc
Power Supply Current
Vee
Min, 10L
= -5.2V
Max, VIN = 0.4V
Max, VIN = 4.5V
Max, VIN = Vee
Max, liN = -10 mA
Max, VOUT = 2.4V
Max, VOUT = 0.5V
Min, 10H
Max (Note 7)
Vee = Max, All Outputs Open,
All Inputs = GND
5-21
Min
8 mA
Typ
Max
Units
0.3
0.45
V
2.1
0.8
V
2.4
-150
-300
1.0
40
/LA
1.0
mA
-1.5
V
50
/LA
-50
/LA
-70
mA
80
mA
-1.0
-10
/LA
AC Electrical Characteristics (Note 6) Vee = 5.0V ± 5%, GND = OV, Tc = O"C to + 75·C
Symbol
I
Parameter
I
Conditions
I
Min
I
Max
I
Units
READ TIMING
tACS
Chip Select Access TIme
20
ns
tZACS
Chip Select to High Z
20
ns
tAOS
Output Enable Access Time
20
ns
tZAOS
Output Enable to HIGH Z
20
ns
tAA
Address Access Time (Note 8)
25
ns
Figures
3a,3b,3c
WRITE TIMING
tw
Write Pulse Width to Guarantee Writing
(Note 9)
tWSD
tWHD
tWSA
Address Setup Time prior to Write
(Note 9)
tWHA
Address Hold Time aiter Write
5
ns
twscs
Chip Select Setup Time prior to Write
5
ns
tWHCS
Chip Select Hold Time aiter Write
5
tzws
Write Enable to Output Disable
20
ns
Data Setup Time prior to Write
5
ns
Data Hold Time aiter Write
5
ns
5
ns
Figure 4
ns
20
ns
20
Write Recovery Time
twA
Note 1: Either Input voltage limit or Input current limit sufficient to protecting Inputs.
Note 2: Output current IImR required.
Note 3: Typical values are at Vee = S.OV, Ie = + 2S'O and maximum loading.
Note 4: Static condition only.
Note 5: Functional testing done at Input levels VIL = O.4SV t:~IAA-==\1---r--~
DATA OUTPUTS
TL/D/9996-7
3a. Read Mode Propagation Delay from Address
OUTPUT ENABLE
lAOS
DATA OUTPUTS
(~~~:-
.
TUD/9996-8
-- - - --
LOAD B
HIGHZ------TL/D/9998-9
3b. Read Mode P~pagatlon Delay from Chip Select
3c. Read Mode Propagation Delay from Output Enable
FIGURE 3. Read Mode Testing
5·24
r------------------------------------------------------------------------------------------,
Functional Description
U)
w
!;:
(Continued)
N
N
CHIP SELECTS
CSi,CS2
ADDRESS
AO-A7
»
tI\
'\
~V
~ 1.5V
J
~ 'tJ r\
~V
~ 1.5V
J
~ ~ 1.5V
I
DATA IN
00- 03
7 '\t'\
-tw-
~
WRITE ENABLE
t\
L
1.5V
7 tWHO
twso
~
~
I---tWSAtwscs
- tWHA -tzws
1-
DATA OUTPUTS
00-03
[
tWHCS
-tWR-
LOADB~
1.5V
z·---
----HIGH
---·HIGH Z----
LOADA~
1.5V
O.SV
TL/D/9996-10
FIGURE 4. Write Mode Timing
Note 1: Timing Diagram represents one solution which results in an optimium cycle time. Timing may be changed to fit various applications as long as the worst
case limits are not violated.
Note 2: Input voltage levels for worst case AC test are 3.0V-OV.
5-25
§ ~NaHonal
~ ~ Semiconductor
93L425A
1024 x 1·Bit Static Random Access Memory
General Description
Features
The 93L425A is a 1024-bit read write Random Access
Memory (RAM). organized 1024 words by one bit. It is designed for high speed cache control and buffer storage applications. The device includes full on-chip decoding. separate Data input and non-inverting Data output. as well as an
active LOW Chip Select line.
•
•
•
•
New design to replace old 93425/93L425
Improved ESD thresholds
Alpha hard without die coat
Commercial address access time
93L425A
25 ns max
• Features TRI-STATE@ output
• Power dissipation decreases with increasing temperature
Connection Diagram
16·Pln DIP
'-../
16
:-Vcc
AO- 2
15
:-0
:-WE
CS-l
Al- 3
14
A2- 4
13 I-A9
A3- 5
12 I-A8
A4- 6
111-;"7
0- 7
10 I-A6
GNO- 8
91-A5
TL/0/10004-1
Top View
Order Number 93L425ADC or 93L425APC
See NS Package Number J16A' or N16E'
Optional Processing QR = Burn-In
·For most current package information, contact product marketing.
Logic Symbol
Pin Names
2 - AO CS
o
Chip Select (Active LOW)
WE
AO-A9
3 - AI
4 - A2
Vee = Pin 16
GND = Pin 8
5 - A3
6 - A4
9 - AS
10- A6
11- A7
12- AS
13- A9
Address Inputs
Write Enable Input (Active LOW)
93L425A
o
TL/0/10004-3
5-26
o
Data Input
a
Data Output
Absolute Maximum Ratings
Guaranteed Operating Ranges
Above which the useful life may be impaired
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
- 65·C to + 150·C
Storage Temperature
Supply Voltage Range
-0.5Vto +7.0V
Input Voltage (DC) (Note 1)
-0.5V to Vee
Supply Voltage (Vee)
Commercial
Input Current (DC)
Voltage Applied to Outputs
(Note 2)
5.0V ±5%
Case Temperature (Te)
Commercial
O·Cto +75·C
-12 mA to +5.0 mA
Lead Temperature (Soldering, 10 sec.)
Maximum Junction Temperature (TJ)
Output Current
-0.5V to 5.5V
300·C
+ 175·C
+20mA
DC Characteristics over operating temperature ranges (Note 3)
Symbol
Parameter
Conditions
Min
Vee
= Min, 10H = -5.2 mA
VOL
Output LOW Voltage
Vee
= Min, 10l = 16 mA
VIH
Input HIGH Voltage
Guaranteed Input HIGH Voltage
for All Inputs (Notes 4, 5, & 6)
Vil
Input LOW Voltage
Guaranteed Input LOW Voltage
for All Inputs (Notes 4, 5, & 6)
III
Input LOW Current
Vee
= Max, VIN = 0.4V
IIH
Input HIGH Current
Vee
= Max, VIN = 4.5V
Vee
VOH
Output HIGH Voltage
Typ
Max
Units
0.45
V
V
2.4
2.1
V
0.8
V
-180
-300
/LA
1.0
40
/LA
1.0
mA
-1.5
V
IIHB
Input Breakdown Current
Vie
Input Diode Clamp Voltage
= Max, VIN = Vee
Vee = Max,llN = -10 mA
10ZH
Output Current (HIGH Z)
Vee
50
/LA
Vee
-50
/LA
-100
mA
65
mA
10Zl
los
Output Current Short Circuit
to Ground (Note 7)
lee
Power Supply Current
= Max, VOUT = 2.4V
= Max, VOUT = 0.5V
Vee = Max (Note 7)
Vee = Max, All Inputs
Output Open
5·27
= GND,
-1.0
AC Electrical Characteristics (Note 6) VCC =
Symbol
5.0 ± 5%, GND = OV, TC = O°C to
Parameter
Conditions
Min
+ 75°C
Max
Units
READ TIMING
tACS
Chip Select Access Time
tZACS
Chip Select to HIGH Z
tAA
Address Access Time (Note 8)
Figures
3a,3b
15
ns
15
ns
25
ns
WRITE TIMING
tw
Write Pulse Width to Guarantee
Writing (Note 9)
20
ns
tWSD
Data Setup Time Prior to Write
5
ns
tWHD
Data Hold Time after Write
5
ns
tWSA
Address Setup Time Prior
to Write (Note 9)
5
ns
tWHA
Address Hold Time after Write
5
ns
tWSCS
Chip Select Setup Time Prior to Write
5
ns
tWHCS
Chip Select Hold Time after Write
5
ns
tzws
Write Enable to Output Disable
15
ns
tWA
Write Recovery Time
15
ns
Figure 4
Note 1: Either input voltage limit or input current limit is sufficient to protect the inputs.
Note 2: Output current limit required.
Note 3: Typical values are at
Vee
~
S.OV. Te ~ + 2S'C and maximum loading.
Note 4: Static condition only.
Note 5: Functional testing done at input levels VIH
Note 6: AC testing done at input levels
VIH
~
~
3V, VIL
0.45V (VOL Max) and VIH
~ OV.
~
2.4V (VOH Min).
Note 7: Short circuit to ground not to exceed one second.
Note 8: The maximum address access time is guaranteed to be the worst case bit in the memory using a pseudorandom testing pattern.
Note 9: tw measured at tWSA = Min. tWSA measured at tw = Min.
5-28
r---------------------------------------------------------------------------------,
U)
Co)
r-
Logic Diagram
~
N
CJI
:I>
o
WORD
DRIVER
32x32
ARRAY
ADDRESS
DECODER
TL/D/10004-2
Functional Description
The 93L425A is a fully decoded t 024-bit read write Random
Access Memory organized t 024 words by one bit. Bit selection is achieved by means of a to-bit address AO-A9.
The 93L425A has a three-state output which provides an
active pull-up or pull-down when enabled and a high impedance (HIGH Z) state when disabled. The active pull-up provides drive capability for high capacitive loads while the high
impedance state allows optimization of word expansion in
bus organized systems.
One Chip Select (CS) input is provided for easy memory
array expansion of up to 2048 bits without the need for external decoding. For larger memories the fast chip select
access time permits direct address decoding without an increase in overall memory access time.
Truth Table
The read and write functions of the 93L425A are controlled
by the state of the active LOW Write Enable WE input.
When WE is held LOW and the chip is selected, the data at
D is written into the location specified by the binary address
present at AO through A9. Since the write function is level
triggered, data must be held stable at the data input for at
least tWSD(m.i!!l..Plus tW(min) plus tWHD(min) to insure a valid
write. When WE is held HIGH and the chip selected, data is
read from the addressed location and presented at the output O.
Inputs
Outputs
CS
WE
0
0
H
L
L
L
H
L
L
H
X
L
H
HIGHZ
HIGHZ
HIGHZ
X
DOUT
H = HIGH Voltage Level: 2.4V
L = LOW Voltage Level: O.4SV
X = Don't Care HIGH or LOW
HIGH Z = High·lmpedance
5-29
Mode
Not Selected
Write 0
Writet
Read
CHIP SELECT
o
93L425A
30*pF
LOAD A
DATA OUWUT
LOAD A
TLlD/10004-4
LOAD B
TL/D/10004-6
GND
38. Read Mode Propagation Delay from Chip Select
~ 3004
0
93L<42SA
60GA :
LOAD B
::: 300pF
-TL/D/10004-6
Note: Load A Is used for all production testing.
'Includes jig and probe capacHanca.
FIGURE 1. AC Test Output Load
ADDRESS~~tAA_~r__
___
DATA OUTPUTS
TL/D/10004-7
3b. Read Mode Propagation Delay from Address
FIGURE 3. Read Mode Timing
! ' - - - - . J I 90l!
1..-3nl
,
~
TLlD/10004-8
FIGURE 2. AC Test Input Levels
5-30
CHIP SELECT
ADDRESS
DATA INPUT
~ I~1.5V
I
~ lIJ~
~ ~1.5V
I
,
7 't\
~L
\: 1.5V
I
~
I~
I---tw-
~
WRITE ENABLE
r\
1.5V
7
twso
~
tWHO
~
_ tWSAtwscs
1-
~
I-tzws
I--tWHAtWHCS
I - tWR 1.5V
···-HIGH Z····
····HIGH Z••••
1.5V
TL/D/10004-9
Note 1: Timing Diagram represents one solution which results In an optimum cycle time Timing may be changed to fit various applications as long as the worst
case limits are not violated.
Note 2: Input voltage levels for worst case AC test are 3.0V-OV.
FIGURE 4. Write Mode Timing
III
5·31
~NaHonal
~ Semiconductor
93479
256 x 9-Bit Static Random Access Memory
General Description
Features
The 93479 is a 2304-bit read/write Random Access Memory (RAM). organized as 256 words by nine bits per word. It is
ideally suited for scratchpad. small buffer and other applications where the number of required words is small and
where the number of required bits per word is relatively
large. The ninth bit can be used to provide parity for a-bit
word systems.
• Commercial address time
93479-45 ns max
93479A-35 ns max
• Military address access time
· 93479-60 ns max
93479A-45 ns max
• Common data input/output
• Features TRI-STATE® output
Connection Diagrams
22-Pin Ceramic DIP
008- 1
'-./
28-Pln LCC
0"'
i
....
8
2
1282726
~
.....
o
11'1 i i i
007- 2
22 -VCl;
21-A7
006- 3
20 -A6
005- 5
251-A6
005- 4
19 -AS
004- 6
241-AS
004- 5
18 -A4
003- 7
003- 6
002- 7
17 -A3
002- 8
DQ1- 9
001- 8
16 -A2
15,...Al
000- 9
14 -AO
0[- 10
4
3
231-A4
TOP
221-A3
211-A2
20l-Al
000- 10
NC- 11
131-CS
GNO- 11
12
I-WE
TLlD/9675-1
TUD/9675-3
Top View
Top View
Order Number 93479DC, 93479ADC,
93479DMQB or 93479ADMQB
See NS Package Number J22A *
Order Number 93479LMQB or 93479ALMQB
See NS Package Number E28A*
'For most current package information. contact product marketing.
'For most current package information. contact product marketing.
Optional Processing QR = Burn In
Optional Processing QR = Burn In
Pin Names
AO-A7
Logic Symbol
Address Inputs
DQO-DQa
Data Input Outputs
OE
Output Enable Input (Active LOW)
WE
Write Enable Input (Active LOW)
OE CS WE
Chip Select Input (Active LOW)
NC
No Connect
vee = Pin 22
GND
= Pin 11
1415161718192021-
AO
AI
A2
A3
A4
93479
AS
A6
A7
ggggggggg
lUUlUI
5-32
TL/D/9675-2
Absolute Maximum Ratings
Guaranteed Operating Ranges
Above which the useful life may be impaired
Supply Voltage (Vee)
Commercial
Military
Case Temperature (Tcl
Commercial
Military
Storage Temperature
- 6S·C to + 1S0·C
Supply Voltage Range
-O.SV to + 7.0V
Input Voltage (DC) (Notes 1,2)
Voltage Applied to Outputs
(Notes 2, 3)
(Output HIGH)
-O.SV to Vee (RAMs)
-1.SV to Vee (PROMs)
- O.SV to + S.SV (RAMs)
-1.SV to + S.SV (PROMs)
Lead Temperature
(Soldering, 10 seconds)
300·C
Maximum Junction
Temperature (TJ)
+ 17S·C
Output Current
+20mA
Input Current (DC)
-12 mA to +S.O mA
Nole 1: Either Input Voltage lim" or Input Current limit is sufficient to protect the inputs.
Nole 2: Output current limit required.
Note 3: Typical values are at Vee
= 5.0V. Tc = + 25°C and maximum loading.
Nole 4: Stalic condition only.
Note 5: Functional testing done at input levels VIL
= VOL (Maxi (0.45V), VIH = VOH (Min) (2.4V).
Note 6: AC testing done at input levels VIH = av, VIL = OV.
Note 7: Short circuit to ground not to exceed one second.
Note 8: The maximum address access time is guaranteed to be the worst case bit in the memory using a pseudorandom testing pattern.
Nole 9:
tw measured at tWSA = Min. tWSA measured at tw = Min.
S-33
S.OV ±S%
S.OV ±10%
O·Cto +7S·C
- SS·C to + 12S·C
.....
oo:t
G)
C")
G)
Logic Diagram
AO
AI
A2
A3
A4
ADDRESS
BUFFER
A5
A6
A7
WE
cs
Q[
AI.
.-+72
X
DECODE
I OF 32
32 MEMORY CELL MATRIX
32 x 8x9 - 2304
Y
DECODE
I OF 8
CONTROL
LOGIC
WE·cs
READ/WRITE CIRCUITS
DIN' Dour BUFFERS
Q[. cs· WE
O ...... Ntt)~lOCD ...... CXJ
000000000
cccocococ
TL/D/9675-4
Functional Description
The 93479 has TRI-STATE outputs which provide an active
pull-up or pUll-down when enabled and a high impedance
(HIGH Z) state when disabled. The active pull-ups provide
drive capability for high capacitive loads while the high impedance state allows optimization of word expansion in bus
organized systems.
The 93479 is a fully decoded 2304-bit random access memory organized 256 words by nine bits. Word selection is
achieved by means of an 8-bit address AO-A7.
The Chip Select input provides for memory array expansion.
For larger memories the fast chip select access time permits decoding without an increase in overall memory access
time.
The read and write operations are controlled by the state of
the active LOW Write Enable (WE) input. With WE held
LOW, the chip selected and the output disabled, the data at
DOO-D08 is written into the addressed location. Since the
write function is level triggered, data must be held stable for
at least tWSD(min) plus tWHD(min) to insure a valid write. To
read, WE is held HIGH, the chip selected and the output
enabled. Non-inverted data is then presented at the outputs
DOO-D08.
Truth Table
Data In lOut
Inputs
CS
OE
WE
X
H
H
L
L
X
X
X
L
H
H
L
DQD-DQS
Mode
HIGHZ
HIGHZ
Data Out
Data In
Output Disabled
RWDisabled
Read
Write
H ~ HIGH Voltage Level 2.4V
L ~ LOW Voltage Level O.5V
X ~ Don't Care HIGH or LOW
HIGH Z ~ High Impedance State
5-34
DC Electrical Characteristics Over operating temperature ranges (Note 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VOL
Output LOW Voltage
Vee = Min, 10l = B.O mA
VOH
Output HIGH Voltage
Vee = Min,loH = -5.2 mA
2.4
V
VIH
Input HIGH Voltage
Guaranteed Input HIGH Voltage
for All Inputs (Notes 4, 5 & 6)
2.1
V
Vil
Input LOW Voltage
Guaranteed Input LOW Voltage
for All Inputs (Notes 4, 5 & 6)
0.5
V
O.B
V
/LA
III
Input LOW Current
Vee = Max, VIN = O.4V
-250
-400
hH
Input HIGH Current
Vee = Max, VIN = 4.5V
1.0
40
/LA
IIHB
Input Breakdown Current
Vee = Max, VIN = Vee
1.0
mA
10ZH
10Zl
Output Current (HIGH Z)
Vee = Max, VOUT = 2.4V
Vee = Max, VOUT = 0.5V
-50
50
-400
/LA
/LA
-1.0
-1.5
V
-70
mA
185
200
mA
Ve
Input Diode Clamp Voltage
Vee = Max, VIN = -10 mA
los
Output Current
Short Circuit to Ground
Vee = Max, (Note 7)
lee
Power Supply Current
Commercial
Military
I
Vee = Max
All Inputs GND
5-35
Commercial
AC Electrical Characteristics (Note 6) VCC =
Symbol
Parameter
=
5.0V ± 5%, GND
OV, Tc .;, O·C to
+ 75·C
A
Conditions
Min
Std
Max
Min
Units
Max
READ TIMING
tAcs
tZRCS
tAOS
tZROS
tM
Chip Select Access Time
Chip Select to HIGH Z
Output Enable Access Time
Output Enable to HIGH Z
Address Access Time (Note 8)
25
25
25
25
45
25
25
25
25
35
(Figures 3a, 3b, 3d)
ns
ns
ns
ns
ns
WRITE TIMING
tw
tso
tHO
tWSD
tWHD
twSA
tWHA
tWSCS
twHCS
Write Pulse Width to Guarantee Writing
(Note 9)
Output Enable Setup Time
Data Enable Hold Time
Data Setup Time Prior to Write
Data Hold Time after Write
Address Setup Time Prior to Write
(Note 9)
Address Hold Time after Write
Chip Select Setup Time Prior to Write
Chip Select Hold Time after Write
(Figure 4)
25
25
ns
5
5
25
5
5
5
25
5
ns
ns
ns
ns
5
5
ns
5
5
5
5
5
5
ns
ns
ns
Military
AC Electrical Characteristics (Note6)Vcc =
Symbol
Parameter
5.0V ±10%. GND
=
ov. Tc =
-55·Cto
Std
A
Conditions
Min
+ 125·C
Max
Min
Units
Max
READ TIMING
tACS
tZRCS
tAOS
tZROS
tM
Chip Select Access Time
Chip Select to HIGH Z
Output Enable Access Time
Output Enable to HIGH Z
Address Access Time (Note 8)
30
30
30
30
45
(Figures 3a, 3b, 3d)
40
40
40
40
60
ns
ns
ns
ns
ns
WRITE TIMING
tw
tso
tHO
twSD
tWHD
tWSA
tWHA
twscs
tWHCS
Write Pulse Width to Guarantee Writing
(Note 9)
Output Enable Setup Time
Data Enable Hold TIme
Data Setup TIme Prior to Write
Data Hold Time after Write
Address Setup Time Prior to Write
,
(Note 9)
Address Hold Time after Write
Chip Select Setup Time Prior to Write
Chip Select Hold Time after Write
(Figure 4)
5·36
40
40
ns
5
5
50
10
5
5
50
10
ns
ns
ns
ns
10
10
ns
10
10
10
10
10
10
ns
ns
ns
r---------------------------------------------------------------------------------,
(Q
Co)
0l:Io
~
=
LOAD A
TL/D/9675-5
I"'" I~f.: i'~P'
-=
LOADB
'Includes jig and probe capacitance
Note: Load A is used for all production testing.
TUD/9675-6
TLlD/9675-7
FIGURE 2. AC Test Input Levels
FIGURE 1. AC Test Load Output Load
CHIP SELECT
LOAD A
LOAD B
-··-HIGH Z- • • • • • • • • • • •
TUD/9675-8
a. Read Mode Propagation Delay from Chip Select to Output
..~~":"tAA-,---~--
~
DATA OUTPUTS
TUD/9675-9
b. Read Mode Propagation Delay from Address to Output
FIGURE 3. Read Mode Timing
5·37
··HIGHZ·
LOAD A
DATA OUTPUTS
LOAD B
•• HIGH Z • • • • •
TUD/9675-10
c. Read Mode Propagation Delay from Output Enable
FIGURE 3. Read Mode Timing (Continued)
OUTPUT ENABLE
CHIP SELECT
ADDRESS INPUTS
DATA INPUTS
WRITE ENABLE
TL/D/9675-11
'These timing parameters are only necessary to guarantee High Z state during the entire write cycle.
FIGURE 4. Write Mode Timing
Note 1: Timing Diagram represents one solution which results In an optimum cycle time. TIming may be changed to fit various applications as long as the worst
case limits are not vlclated.
Note 2: Input voltage levels for worst case AC test are 3.0/0.0V.
5·38
MM54C89/MM74C89
Random Access
64m[Su~ TR~gSTAl'[E®
lReadl/WU"o~e
Mem)(O)U"w
General Description
The MM54CB9/MM74CB9 is a 16-word by 4-bit random access read/write memory. Inputs to the memory consist of
four address lines, four data input lines, a write enable line
and a memory enable line. The four binary address inputs
are decoded internally to select each of the 16 possible
word locations. An internal address register latches the address information on the positive to negative transition of
the memory enable input. The four TRI-STATE data output
lines working in conjunction with the memory enable input
provide for easy memory expansion.
Address Operation: Address inputs must be stable tSA prior to the positive to negative transition of memory enable. It
is thus not necessary to hold address information stable for
more than tHA after the memory is enabled (positive to negative transition of memory enable).
Nole: The Uming is different than the DM7489 in that a posiUve to negative
transition of the memory enable must occur for the memory to be
selected.
Read Operation: The complement of the information which
was written into the memory is non-destructively read out at
the four outputs. This is accomplished by selecting the desired address and bringing memory enable low and write
enable high.
When the device is writing or disabled the output assumes a
TRI-STATE (Hi-z) condition.
features
Wide supply voltage range
3.0V to 15V
Guaranteed noise margin.
1.0V
[] High noise immunity
0.45 Vee (typ.)
[J Low power
fan out of 2
TTL compatibility
driving 74L
o Low power consumption
100 nW/package (typ.)
[J Fast access time
130 ns (typ.) at Vee = 10V
D TRI-STATE output
El
[J
Write Operation: Information present at the data inputs is
written into the memory at the selected address by bringing
write enable and memory enable low.
logic and Connection Diagrams
DATA
IiAfi
DATA
DATi
DATA
DAD
DATA
om
INPUT I DUTPUT 1 INPUT 2 OUTPUTZ INPUT 3 OUTPUT 3 INPUT. our,uli
Dual·ln·Line Pacl(age
ADDRESS INPUT A
I
1& Vee
rmll!IIVEllJII[E 2
15 ADDR£SSINPUTB
WRlTEEllJII[E ,
DATA INPUT I
m'il1!IlTl'1IT1
14 ADDRESS IN'UT C
•
"
5
ADDRESS INPUT D
IZ DATA IU'DU
11 IfifitrnmJf4
DATA INPun 6
10 DATA INPUT 3
DATA:DlJTPDTz '
•••
B DmtrnmJT3
Top View
TL/F/5BBB-2
Order Number MM54C89
orMM74C89
TLlF/5BBB-1
5-39
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at any Pin
-0.3VtoVee +0.3V
Operating Temperature Range
MM54C89
- 55·C to + 125·C
MM74C89
- 40·C to + 85·C
-65·Cto + 150·C
Storage Temperature Range (TS)
Power Dissipation (Po)
Dual-In-Line
Small Outline
Operating Vee Range
Absolute Maximum Vee
Lead Temperature (Tt.l
(Soldering, 10 seconds)
700mW
500mW
3.0Vto 15V
18V
260·C
DC Electrical Characteristics MinIMax limits apply across temperature range, unless otherwise noted
I
Symbol
Parameter
CMOS TO CMOS
Logical "1 " Input Voltage
VIN(l)
VIN(O)
Logical "0" Input Voltage
VOUT(l)
Logical "1 " Output Voltage
VOUT(O)
Logical "0" Output Voltage
I
Logical "1" Input Current
Logical "0" Input Current
Output Current in High
Impedance State
Supply Current
Icc
CMOS/LPTTL INTERFACE
Logical "1" Input Voltage
VIN(l)
IINll1
IINIOI
loz
Conditions
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
=
=
=
=
=
=
=
=
=
=
=
=
=
I
I
Min
I Max I Units
Typ
3.5
8.0
5.0V
10V
5.0V
10V
5.0V, 10 = -10 p.A
10V, 10 = -10 p.A
5.0V, 10 = +10 p.A
10V, 10 = + 10 p.A
15V, VIN = 15V
15V, VIN = OV
15V, V = 15V
15V, Vo = OV
15V
1.5
2.0
4.5
9.0
-0.005
-0.005
-1.0
0.005
-0.005
0.05
-1.0
0.5
1.0
1.0
1.0
300
V
V
V
V
V
V
V
V
p.A
p.A
p.A
p.A
p.A
V
54C, Vee = 4.5V
Vee - 1.5
V
74C, Vee = 4.75V
Vee -1.5
Logical "0" Input Voltage
0.8
V
54C, Vee = 4.5V
VIN(O)
0.8
V
74C, Vee = 4.75V
Logical "1 "Output Voltage
2.4
V
54C, Vee = 4.5V, 10 = -360 p.A
VOUT(l)
2.4
V
74C, Vee = 4.75V, 10 = -360 p.A
Logical "0" Output Voltage
0.4
V
54C, Vee = 4.5V, 10 = +360 p.A
VOUT(O)
0.4
V
74C, Vee = 4.75V, 10 = +360 p.A
OUTPUT DRIVE (See 54C174C Family Characteristics Data Sheet) (Short Circuit Current)
Output Source Current
Vee = 5.0V, VOUT = OV
IsoUReE
-3.3
-1.75
mA
(P-Channel)
TA = 25·C
Output Source Current
Vee = 10V, VOUT = OV
ISOUReE
-15
-8.0
mA
(P-Channel)
TA = 25·C
Output Sink Current
Vee = 5.0V, VOUT = Vee
ISINK
1.75
3.6
mA
(N-Channel)
TA = 25·C
Output
Sink
Current
Vee
=
10V,
VOUT
=
Vee
ISINK
8.0
16
mA
(N-Channel)
TA = 25·C
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Range" they are not
meant to Imply that the devices should be operated at these limHs. The table of "Electrical Characteristics" provides condHions for actual device operation.
AC Electrical Characteristics * TA = 25·C, CL = 50 pF, unless otherwise noted
Symbol
IsA
Parameter
Propagation Delay from
Memory Enable
Access Time from
Address Input
Address Setup Time
tHA
Address Hold Time
tME
Memory Enable Pulse Width
Ipd
tAee
Conditions
Min
=
=
=
=
=
=
=
=
=
=
150
60
60
40
400
150
Vec
Vce
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5-40
Typ
270
100
350
130
250
90
Max
500
220
650
280
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC Electrical Characteristics*
Symbol
TA
= 25'C, CL = 50 pF, unless otherwise noted (Continued)
Parameter
Min
Conditions
tSR
Write Enable Setup
Time for a Read
Vee
Vee
tws
Write Enable Setup
Time for a Write
Vee
Vee
tWE
Write Enable Pulse Width
Vee
Vee
tHD
Data Input Hold Time
Vee
Vee
tSD
Data Input Setup
Vee
Vee
t1H, tOH
Propagation Delay from a Logical
"1" or Logical "0" to the High
Impedance State from
Memory Enable
Vee
Vee
= 5V
= 10V
= 5V
= 10V
= 5V, tws = 0
= 10V, tws = 0
= 5V
= 10V
= 5V
= 10V
= 5V, CL = 5 pF, RL = 10k
= 10V,CL = 5pF, RL = 10k
t1H, tOH
Propagation Delay from a Logical
"1" or Logical "0" to the High
Impedance State from
Write Enable
Vee
Vee
=
=
50V, CL
10V, CL
= 5 pF, RL =
= 5 pF, RL =
Typ
Max
0
0
ns
ns
tME
tME
300
100
10k
10k
Units
160
60
ns
ns
ns
ns
50
25
ns
ns
50
25
ns
ns
180
-85
300
120
ns
ns
180
85
300
120
ns
ns
CIN
Input Capacity
Any Input (Note 2)
5
pF
CaUT
Output Capacity
Any Output (Note 2)
6.5
pF
(Note 3)
230
pF
Power Dissipation Capacity
CPD
*AC Parameters are guaranteed by DC correlated testing.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load AC power consumption of any CMOS device, For complete explanation see 54C/74C Family Characteristics application note,
AN-SO.
AC Electrical Characteristics*
Parameter
Conditions
TA
=
Min
tpD
Vee
Vee
Vee
tAee
Vee
Vee
Vee
tSA
Vee
Vee
Vee
tHA
tME
= 5V
= 10V
= 15V
= 5V
= 10V
= 15V
= 5V
= 10V
= 15V
Vee = 5V
Vee = 10V
Vee = 15V
Vee = 5V
Vee
Vee
= 10V
tWE
Vee
Vee
Vee
= 5V
= 10V
tHD
Vee
Vee
Vee
=
15V
= 15V
= 5V
= 10V
= 15V
Guaranteed across the specified temperature range, CL
MM54C89
-55'Cto + 125'C
Max
TA
=
Min
= 50 pF
MM74C89
-40'Cto +85'C
Units
Max
700
310
250
600
265
210
ns
ns
ns
910
400
320
780
345
270
ns
ns
ns
210
90
70
180
80
60
ns
ns
ns
80
55
45
70
50
40
ns
ns
ns
560
210
170
480
180
150
ns
ns
ns
420
140
110
360
120
100
ns
ns
ns
70
35
30
60
30
25
ns
ns
ns
• AC Parameters are guaranteed by DC correlated testing.
•
5-41
..
·~
B
I"
::iii
::iii
.....
~
,-------------------------------------------------------------------------,
AC Electrical Characteristics*
Guaranteed across the specified temperature range, CL = 50 pF (Continued)
Parameter
MMS4C89
TA = -SSOCto + 12SoC
Conditions
CD
~
LI)
Max
Min
60
30
30
ns
ns
ns
25
Vee = 5V
Vee = 10V,CL = 5pF
Vee = 15V, RL = 10 kO
Units
Max
Min
70
35
Vee = 5V
Vee = 10V
Vee = 15V
tSD
::iii
::iii
MM74C89
TA = -40"Cto +8SOC
420
360
170
135
145
115
ns
ns
ns
• Ae Parameters are guaranteed by DC correlated testing.
Truth Table
ME
WE
Operation
Condition of Outputs
L
L
L
H
H
H
H
Write
Read
Inhibit, Storage
Inhibit, Storage
TRI-STATE
Complement of Selected Word
TRI-STATE
TRI-STATE
L
AC Test Circuits
tOH
~i--..........-
TL/F/5BB8-3
TLlF/5BBB-4
Switching Time Waveforms
tOH
Vee
MEMORY
INmE
OV
VOH
t1H
-f··
:i-'.
Vee
!mIliII'I
ENABLE
ov
t,"
V••
IJm(
IJm(
I!UTPUT
iiiI'fPiii'
OV
TLlF/5BBB-6
Read Cycle
Write Cycle
ammwv~----~r----,
ENiiil
v"' _ _ _ _ _,
ADDRESS
INPUT
iMnV~------~
mm
v"' _ _ _ _ _ _ _
~
DATA
.NPUT
TL/F/5BBB-7
5-42
TLlF/5BBB-B
Switching Time Waveforms
(Continued)
Read Modify Write Cycle
Vee
r-.. .-
=oJ
'\
ADDRESS
INPUT
)K
0
Vee
liATA1i1lf
"
I--ts.- - t H A
Vee
__
0
-J"~U'~""'''
lR~T~E~~:;N._
- - - --~
yf~t
Vee
WiiiTE
ENAill
0
Vee
DATA
IN
0
TUF/5888-9
Note: I, - 60 ns
11- 10 ns
•
5·43
~National
~ Semiconductor
MM54C200/MM74C200 256-Bit TRI-STATE®
Random Access Read/Write Memory
General Description
The MM54C200/MM74C200 is a 256-bit random access
read/write memory. Inputs consist of eight address lines
and three chip enables. The eight binary address inputs are
decoded internally to select each of the 256 locations. The
internal address register, latches, and address information
are on the positive to negative edge of CEs. The TRISTATE data output line, working in conjunction with CEl or
CE2 inputs, provides for easy memory expansion.
Address Operation: Address inputs must be stable tSA prior to the positive to negative transition of CEs. It is therefore
unnecessary to hold address information stable for more
than tHA aiter the memory is enabled (positive to negative
transition).
Note: The timing is different from the DM74200 in that a positive to negative
transition of the CEs must occur for the memory to be selected.
Read Operation: The data is read out by selecting the
proper address and bringing CEs low and WE high.
Holding either CE I , CE2, or CEs at a high level forces the
output into TRI-STATE. When used in bus-organized systems, CE1, or CE2, a TRI-STATE control provides for fast
access times by not totally disabling the chip.
Write Operation: Data is written into the memory with CEs
low and WE low. The state of CEl or CE2 has no effect on
the write cycle. The output assumes TRI-STATE with WE
low.
.
Features
•
•
•
•
3V to 15V
1V
0.45 Vee (typ.)
Fan out of 1
driving standard TTL
500 nW (typ.)
Wide supply voltage range
Guaranteed noise margin
High noise immunity
TTL compatibility
• Low power
• Internal address register
Logic and Connection Diagrams
ADDRESS
INPUT C
nITE_~~::::::::::::~
EIIABLE
__4-__
ADDRESS
INPUT B
ADDRESS
INPUT A
-+r-~~L-%-~~L-~-%--%-~l
"~:--+--------------l----l----+I
X·DECODER
Dual-in-Line Package
ADDRESS 1
INPUT A
ADDRESS Z
INPUTB
_
3
CE,
_
16 Vee
15 ADDRESS
I.PUTC
14 ADDRESS
INPUTH
4
13 DATAIN
CE,
_
a •.--------....--II>Oo-1r-~
5
12 WRITE
6
11 ADDRESS
ADDRESS 1
INPUTG
.1 ADDRESS
CE,
om
ENAiii
OUT
2Ss.BIT
MEMORY ARRAY
INPUTF
INPUYD
9 ADDRESS
INPUTE
GND
TUF/5903-2
Top View
Order Number MM54C200 or
MM74C200
TUF/5903-1
5-44
s:
s:
Absolute Maximum Ratings (Note 1)
U1
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
- 0.3V to Vee + 0.3V
Power Dissipation (PD)
Dual-In-Line
Smail Outiine
Operating Vee Range
Operating Temperature Range (TA)
MM54C200
MM74C200
Absolute Maximum Vee
Lead Temperature (TLl
(Soldering, 10 seconds)
Storage Temperature Range (TS)
-55°C to + 125°C
- 40°C to + 85°C
- 65°C to + 150°C
DC Electrical Characteristics
18V
260°C
o"'"
I\)
o
o
......
s:
s:
......
"'o"
I\)
o
o
MiniMax limits apply across temperature range unless otherwise noted
Parameter
Symbol
700mW
500mW
3V to 15V
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
3.5
8
VIN(l)
Logical "1" Input Voltage
Vee = 5V
Vee = 10V
VIN(O)
Logical "0" Input Voltage
Vee = 5V
Vee = 10V
VOUT(l)
Logical "1" Output Voltage
Vee=5V, 10= -10 p.A
Vee = 10V, 10= -10 p.A
VOUT(O)
Logical "0" Output Voltage
Vee= 5V, 10= + 10 p.A
Vee = 10V, 10= + 10 p.A
IIN(l)
Logical "1" Input Current
Vee = 15V, VIN=15V
IIN(O)
Logical "0" Input Current
Vee = 15V, VIN=OV
Icc
Supply Current
V
V
1.5
2
4.5
9
V
V
0.005
-1
0.5
1
V
V
1
p.A
-0.005
0.1
Vee = 15V
V
V
p.A
600
p.A
CMOS/TTL INTERFACE
VIN(l)
Logical "1" Input Voltage
54C Vee = 4.5V
74C Vee = 4.75V
VIN(O)
Logical "0" Input Voltage
54C
74C
VOUT(l)
Logical "1" Output Voltage
54C Vee=4.5V, 10= -1.6 rnA
74C Vee=4.75V, 10= -1.6 mA
VOUT(O)
Logical "0" Output Voltage
54C Vee = 4.5V, 10=1.6mA
74C Vee = 4.75V, 10=1.6mA
V
V
Vee- 1.5
Vee- 1.5
0.8
0.8
Vee = 4.5V
Vee = 4.75V
2.4
2.4
V
V
V
V
0.4
V
OUTPUT DRIVE (See 54C174C Family Characteristics Data Sheet) (Short Circuit Current)
ISOUReE
Output Source Current
(P-Channel)
Vee=5V, VOUT=OV
TA=25°C
-4
-1.8
-6
mA
mA
ISOUReE
Output Source Current
(P-Channel)
Vee=10V, VOUT=OV
TA=25°C
-16
-1.5
-25
mA
mA
ISINK
Output Sink Current
(N-Channel)
Vee=5V, VOUT=Vee
TA=25°C
5
8
mA
ISINK
Output Sink Current
(N-Channel)
Vee=10V, VOUT=Vee
TA=25°C
20
30
mA
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
5-45
AC Electrical Characteristics * TA =
Symbol
25'C, CL
= 50 pF, unless otherwise specified
Typ
Max
Units
tAee
Access Time from Address
Vee
Vee
Conditions
= 5V
= 10V
450
200
900
400
ns
ns
tpd
Propagation Delay from CE3
Vee
Vee
= 5V
= 10V
360
120
700
300
ns
ns
tpeEI
Propagation Delay from CE I or CE2
Vee
Vee
= 5V
= 10V
250
85
700
200
ns
ns
tSA
Address Setup Time
Vee
Vee
= 5V
= 10V
200
100
80
30
ns
ns
tHA
Address Hold Time
Vee
Vee
= 5V
= 10V
50
25
15
5.0
ns
ns
twE
Write Enable Pulse Width
Vee = 5V
Vee = 10V
300
150
160
70
ns
ns
teE
CE3 Pulse Widths
Vee = 5V
Vee = 10V
400
160
200
80
ns
ns
CIN
Input Capacity
Any Input (Note 2)
5.0
pF
COUT
Output Capacity in TRI-STATE
(Note 2)
9.0
pF
CPD
Power Dissipation Capacity
(Note 3)
400
pF
Parameter
AC Electrical Characteristics*
Symbol
Parameter
Min
CL = 50pF
Conditions
MM54C200
TA = -55'C to + 125'C
Min
Max
MM74C200
TA= -40'Cto +85'C
Min
Units
Max
tAee
Access Time from Address
Vee = 5V
Vee = 10V
1200
520
1100
480
ns
ns
tpd
Propagation Delay from CE3
Vee = 5V
Vee = 10V
950
400
850
360
ns
ns
tpdeEI
Propagation Delay from
CEIorCE2
Vee = 5V
Vee = 10V
650
300
600
275
ns
ns
tSA
Address Setup Time
Vee = 5V
Vee = 10V
250
120
250
120
ns
ns
tHA
Address Hold Time
Vee = 5V
Vee = 10V
100
·50
100
50
ns
ns
twE
Write Enable Pulse Width
Vee = 5V
Vee = 10V
450
225
400
200
ns
ns
teE
Disable Pulse Width
Vee = 5V
Vee = 10V
500
250
460
230
ns
ns
tHD
Data Hold Time
Vee = 5V
Vee = 10V
50
25
50
25
ns
ns
• AC Parameters are guaranteed by DC correlated testing.
Note I: "'Absolute Maximum Ratings"' are those values beyond which the safety of the device cannot be guaranteed. Except for "'Operating Temperature Range"'
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: CapaCitance is guaranteed by periodic testing.
Note 3: CpD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note,
AN-90.
5-46
s:
s:
U1
Switching Time Waveforms
01:1-
o
~
o
o
......
Read and Write Cycles Using CE3 (CEl = CE2 = logic 0)
R3
------~,,~________
s:
s:
......
Vee
_J
01:1-
o
~
OV
o
o
v~
ADDRESS
INPUT
OV
vee
OV
V~
DATA
IN
::~ -------------\
TRI-5TATE
- TRI:sTAiE -
OV
Vee
•
"----- OV
TL/F/5903-3
Read and Write Cycles Using CE3 and CEl (or CE2)
\
/r'------------vce
I ~-".-- - - - - o V
,---------,---------------------V~
------------OV
-----------V~
ADDRESS
INPUT
~------------OV
cc
",,---V
w
I
I"~
I
DATA
IN
" ------~-------::
~
"I "',
__ __ __ ___
TRI·STATE
TRI·STATE
_________________________________ OV
TL/F/5903-4
Note: Used for fast access time in bused systems.
5·47
.... r----------------------------------------------------------------------------,
C)
~ ~NaHonal
'0:1'
.....
:!i ~ Semiconductor
:!i
(:)
.... MM54C910/MM74C910 256 Bit TRI-STATE®
G)
~
II)
:!i
:!i
Random Access Read/Write Memory
General Description
Outputs are in the TRI-STATE (Hi-Z) condition when the
device is writing or disabled.
The MM54C910/MM74C910 is a 64 word by 4-bit random
access memory. Inputs consist of six address lines, four
data input lines, a WE, and a ME line. The six address lines
are internally decoded to select one of the 64 word locations. An internal address register latches the address information on the positive to negative transition of ME. The
TRI-STATE outputs allow for easy memory expansion.
Features
•
•
•
•
•
Address Operation: Address inputs must be stable (tsAl
prior to the positive to negative transition of ME, and (tHA)
after the positive to negative transition of ME. The address
register holds the information and stable address inputs are
not needed at any other time.
Write Operation: Data is written into memory at the selected address if WE goes low while ME is low. WE must be
held low for twE and data must remain stable tHO after WE
returns high.
Read Operation: Data is nondestructively read from a
memory location by an address operation with WE held
high.
Supply voltage range
High noise immunity
TTL compatible fan out
Input address register
Low power consumption
• Fast access time
• TRI-STATE outputs
• High voltage inputs
3.0V to 5.5V
0.45VCC (typ.)
1 TTL load
250 nW/package (typ.)
(chip enabled or disabled)
250 ns (typ.) at 5.0V
Logic Diagrams
Dill
0 Dun DIN!
0 Dun D INl
DDUll D IN4
0 OUT4
Input Protection
Vee
TLlF/5914-2
TL/F/5914-1
5-48
Absolute Maximum Ratings
Operating Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Output Pin
- 0.3V to Vee + 0.3V
-0.3Vto +15V
Voltage at Any Input Pin
Power Dissipation
Dual·ln·Line
Small Outline
700mW
500mW
Operating Vee Range
3.0Vt05.5V
Standby Vee Range
1.5Vt05.5V
Min
Max
Units
Supply Voltage (Vecl
MM54C910
MM74C910
4.5
4.75
5.5
5.25
V
V
Temperature (TA)
MM54C910
MM74C910
-55
-40
+125
+85
"C
"C
6.0V
Absolute Maximum (Vecl
Lead Temperature (T Ll
(Soldering, 10 sec.)
260"C
DC Electrical Characteristics
Min/Max limits apply accross the temperature and power supply range indicated
Symbol
Parameter
Conditions
VIN(l)
Logical "1" Input Voltage
Full Range
VIN(O)
Logical "0" Input Voltage
Full Range
IIN(l)
Logical "1" Input Current
VIN
VIN
IIN(O)
Logical "0" Input Current
VOUT(l)
Logical "1" Output Voltage
= 15V
= 5V
VIN = OV
10 = -150 p.A
10 = -400 p.A
VOUT(O)
Logical "0" Output Voltage
10 = 1.6mA
loz
Output Current in High
Impedance State
Vo
Vo
Supply Current
Vee
lee
AC Electrical Characteristics*
Min
TA
Typ
Max
Units
0.8
V
2.0
1.0
p.A
p.A
V
Vee - 1.5
0.005
0.005
-1.0
-0.005
p.A
V
V
Vee - 0.5
2.4
= 5V
= OV
-1.0
= 5V
0.4
V
0.005
-0.005
1.0
p.A
p.A
5.0
300
p.A
= 25"C, Vee = 5.0V,CL = 50pF
Typ
Mal(
Units
tAee
Access Time from Address
250
500
ns
tpd
Propagation Delay from ME
180
360
ns
tSA
Address Input Set-Up Time
140
70
ns
tHA
Address Input Hold Time
20
10
ns
tME
Memory Enable Pulse Width
200
100
ns
tME
Memory Enable Pulse Width
400
200
tso
Data Input Set-Up Time
Symbol
Min
Parameter
ns
0
ns
ns
tHO
Data Input Hold Time
30
15
!WE
Write Enable Pulse Width
140
70
tlH, tOH
Delay to TRI-STATE (Note 4)
100
CIN
Input Capacity
Any Input (Note 2)
5.0
pF
COUT
Output Capacity
Any Output (Note 2)
9.0
pF
CPO
Power Dissipation Capacity
(Note 3)
350
pF
ns
200
ns
CAPACITANCE
5·49
AC Electrical Characteristics * (Continued)TA =
Symbol
25·C. Vcc = 5.0V. CL = 50 pF
MM54C910
TA = -55"Cto + 125'C
Vee = 4.5V to 5.5V
Parameter
MM74C910
TA = -40'Cto +85'C
Vee = 4.75V to 5.25V
Max
Min
Min
Units
Max
tACC
Access Time from Address
860
700
ns
tpd1. tpdO
Propagation Delay from ME
660
540
ns
tSA
Address Input Set-Up Time
200
,160
ns
tHA
Address Input, Hold Time
20
20
ns
!ME
!ME
Memory Enable Pulse Width
280
260
ns
Memory Enable Pulse Width
750
600
ns
tso
Data Input Set-Up Time
0
0
ns
tHO
Data Input Hold Time
50
50
ns
!WE
Write Enable Pulse Width
200
180
ns
Delay to TRI-STATE (Note 4)
200
200
ns
t1H. tOH
•AC Parameters ara guaranteed by DC correlated tesflng.
Note 1: '"Absolute Maximum Ratings'" are those values beyond which the safety of the device cannot be guaranteed. Except for '"Operating Temperature Range'"
they are not meant to Imply that the devices should be operated at these limits. The table of '"Electncal Characteristics'" provides condHions for actual device
operation.
Note 2: CapaCitance is guaranteed by periodiC testing.
Note 3: Cpo determines the no load AC power consumption for any CMOS device. For complete explanation see 54CI74C Family Charactenstics application note
AN·9O.
Note 4: See AC test circuits for t, H. IoH.
Typical Performance Characteristics
Truth Table
Typical Access Time vs
Ambient Temperature
450
4DO
350
4,5V ....
~ 3ao
!
I
5V
250
ME
WE
Operation
Outputs
L
L
L
H
H
H
H
Write
Read
Inhibit. Store
Inhibit. Store
TRI·STATE
Data
TRI-STATE
TRI-STATE
L
5.5V
200
150
100
50
0
-55 -25
5
35
85
95
125
FREE AIR TEMPERATURE ('C)
TL/F/5914-4
AC Test Circuits
tOH
t1H
Vc:c
Vc:c
002
ooz
TCC
RL
RL
001
' . L CL
T
004
T
'::"
...L.'CL
Vc:c
. . L cL
'T
~
003
· . L CL V
0D3
RL ..LCL
RL
RL
"*
'::"
001
RL i C L
':d:'
.LCL
T
TL/F/5914-5
5-50
'::"
RL
"::-
004
T"
RL
'::"
TLlF/5914-6
AC Test Circuits (Continued)
All Other AC Tests
002
"I
003
T
Cl
001
Cl
004
TL/F/5914-7
Switching Time Waveforms
Read Cycle
(See Note 1)
VCC--------+.r---------~
MEMDRV
ENABLE
VCC -------------.....
ADDRESS
INPUT
VCC--------J7.~~7;7.~~7;7.~~----_1--------------
WiiifE
ENABLE
~ VCC-------------------------------4-~-------------
OUT
--------------TRI·STATE® CONDITION
TL/F/5914-B
Write Cycle
(See Note 1)
VCC-------+-,----------~
MEMlIl!Y
ENABLE
ADDRESS
INPUT
VCC --------------'"
VCC--------------------~
IiA'fA
iiUT
TLlF/5914-9
5-51
.... r-----------------------------------------------------------------------------,
~..... Switching Time Waveforms (Continued)
o
::::E
::::E
Read Modify Write Cycle
(See Note 1)
C;
....
G)
~
II)
yee-----j-/----""'
MEMORY
ffim
::::E
::::E
yee------'"
ADDRESS
INPUT
_
LATCHED ADDRESS
yee-------I-----
DATA
0iIi'
I'iiii'fE
q'WE
Vee
ENABLE
DATA
IN
X
----
- -
Vee
'*D
' -_ __
TUF/5914-10
toH
E ':
DATA Vee
OUT
0
,,:1e:
0.1 Vee
- - - TRloSTATE@
TL/F/5914-12
TUF/5914-11
.
Note 1: MEMORY ENABLE must be brought high for tME nanoseconds between every address change.
Note 2:
t, = If = 20 ns for all inpuls.
Connection Diagram
Dual-In-Line Package
WIIITr fmIiIiW
Vee
1,8
D Dun
17
OlN3
16
OlN4 0 OUTC"ERAm ENJiI[(
15
14
13
12
AD
AC
10
11
Order Number MM54C910 or MM74C910
I--
~
1
o Dun
2
3
01NZ
01Nl
4
0 Dun
5
AB
6
AA
7
AF
8
1
9
aND
TLlF/5914-3
AE
Top View
5-52
~National
~
Semiconductor
MM54C989/MM74C989
64-Bit (16 x 4) TRI-STATE® RAM
General Description
The MM54C9B9/MM74C9B9 is a 16-word by 4-bit random
access read/write memory. Inputs to the memory consist of
4 address lines, 4 data input lines. a write enable line and a
memory enable line. The 4 binary address inputs are decoded internally to select each of the 16 possible word locations. An internal address register latches the address information on the positive to negative transition of the memory
enable input. The 4 TRI-STATE data output lines working in
conjunction with the memory enable input provides for easy
memory expansion.
Read Operation: The complement of the information which
was written into the memory is non-destructively read out at
the 4 outputs. This is accomplished by selecting the desired
address and bringing memory enable low and write enable
high.
When the device is writing or disabled the output assumes a
TRI-STATE (Hi-Z) condition.
Features
3.0V to 5.5V
1.0V
0.45 Vee (typ.)
Fan out of 2
driving 74L
•
•
•
•
Wide supply voltage range
Guaranteed noise margin
High noise immunity
Low power TTL
compatibility
• Input address register
• Low power consumption
Address Operation: Address inputs must be stable tSA prior to the positive to negative transition of memory enable. It
is thus not necessary to hold address information stable for
more than tHA after the memory is enabled (positive to negative transition of memory enable).
Nate: The timing is different than the DM7489 in that a positive to negative
transition of the memory enable must occur for the memory to be
selected.
Write Operation: Information present at the data inputs is
written into the memory at the selected address by bringing
write enable and memory enable low.
250 nW/package (typ.)
@Vee= 5V
140 ns (typ.) at Vee = 5V
• Fast access time
• TRI-STATE output
Logic and Connection Diagrams
DATA
6i'i'i
DATA
am
DATA
6lTi
DATA
INPUT 1 amUT I II.UT Z OUTPUT Z INPUT:I OUTPUT:I INPUT.
6iTi
iiUiPIiii
Dual·ln·Llne Package
ADDRESS 1
INPUTA
MDmRV 2
mm
liIIITE
mm
iililff
ENABLE
18 Vee
16 ADDRESS
INPUTB
14 ADDRESS
INPUTe
13 ADDRESS
INPUTD
II DATA
INPUT4
11
tI1ITP1IT4
10 DATA
INPun
3
DATA 4
INPUT I
5
tI1ITP1ITl
DATA 8
INPun
IiATA 1
MEMORY
EIlABLE
am
INPUT"
am
tI1ITP1ITz
8
DND •
am
lI1ITPDT3
INPUT.
TL/F/5925-2
Top View
INPUTe
Order Number
MM54C989 or MM74C989
.•,orl
TUF/5925-1
5-53
Absolute Maximum Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
-0.3VtoVee + 0.3V
Power Dissipation
Dual-In-Line
700mW
Small Outline
500mW
Absolute Maximum Vee
7.0V
Lead Temperature (TO
(Soldering, 10 seconds)
260·C
Supply Voltage (Vee)
MM54C989
MM74C989
Temperature (TA)
MM54C989
MM74C989
Operating Vee Range
Standby Vee Range
Min
Max
Units
4.7
4.75
5.5
5.25
V
V
-55
-40
+125
+85
·C
·C
3.0Vto5.5V
1.5Vto5.5V
DC Electrical Characteristics MM54C989/MM74C989
MinIMax limits apply across the temperature and power supply range indicated
Symbol
Parameter
Conditions
VIN(l)
Logical "1" Input Voltage
VIN(O)
Logical "0" Input Voltage
IIN(l)
Logical "1" Input Current
VIN = 5V
IIN(O)
Logical "0" Input Current
VIN = OV
VOUT(l)
Logical "1" Output Voltage
10 = -360p.A
10 = -150p.A
VOUT(O)
Logical "0" Output Voltage
10 = 360 ",A
loz
Output Current in High Impedance State
Vo = 5V
Vo = OV
lee
Min
Typ
Max
Vee - 1.5
Supply Current Active (Note 1)·
V
0.005
-1
0.8
V
1
p.A
-0.005 .
p.A
2.4
Vee - 0.5
V
V
-1 .
ME = OV,
Vee = 5V
0.4
V
0.005
-0.005
1
p.A
p.A
0.05
150
p.A
3
",A
ME = 5V
Supply Current (Stand-By)
lee
Note 1': MEMORY ENABLE must be brought high for tME ns between every address change.
AC Electrical Characteristics*
Units
MM54C989/MM74C989
TA = 25·C, Vee = 5V, CL = 50 pF
Symbol
Typ
Max
Units
tAee
Access Time from Address
Parameter
Min
140
500
ns
tpo
Propagation Delay from ME
110
360
ns
!sA
Address Input Set-Up Time
140
30
ns
tHA
Address Input Hold Time
20
15
ns
tME
Memory Enable Pulse Width
200
80
ns
!ME
Memory Enable Pulse Width
400
100
ns
tso
Data Input Set-Up Time
tHO
Data Input Hold Time
30
20
!WE
Write Enable Pulse Width
140
70
t1H, tOH
DelaytoTRI-STATE,CL = 5pF,RL = 10k,(Note4)
0
ns
100
ns
ns
200
ns
CAPACITANCE
CIN
Input Capacity, Any Input, (Note 2)
5
pF
COUT
Output Capacity, Any Output, (Note 2)
8
pF
Power Dissipation Capacity, (Note 3)
Cpo
350
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the deviea cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devieas should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual davlea
operation.
Note 2: CapaCitance Is guaranteed by periodic testing.
Note 3: Cpo determines the no load AC power consumption for any CMOS device. For complete explanation see 54C174C Family Characteristics Application
Note. AN·9O.
5-54
AC Electrical Characteristics*
(Continued)
MMS4C989: TA = -SS·C to + 12S·C. Vee = 4.SV to S.SV. CL = SO pF
MM74C989: TA = -40·C to +8S·C. Vec = 4.7SV to S.SV. CL = SO pF
Symbol
MM54C989
Parameter
Min
Access Time from Address
tAec
MM74C989
Max
Min
Units
Max
SOO
620
ns
430
ns
tpOl. tpoo
Propagation Delay from ME
tSA
Address Input Set-Up Time
lS0
140
ns
tHA
Address Input Hold Time
SO
60
ns
tME
Memory Enable Pulse Width
2S0
310
ns
!ME
Memory Enable Pulse Width
S20
400
ns
tso
Data Input Set-Up Time
0
0
ns
tHO
Data Input Hold Time
60
SO
ns
\WE
Write Enable Pulse Width
220
180
t1H. toH
Delay to TRI-STATE. (Note 4)
350
ns
200
200
ns
• AC Parameters are guaranteed by DC correlated testing.
Note 1: "Absotute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides condHions for actual device
operation.
Note 2: CapaCitance is guaranteed by periodic testing.
Not. 3: CPO determines the no load AC power consumption for any CMOS device. For complete explanation see 54CI74C Family Characteristics Application
Note. AN-gO.
Not. 4: See AC test circuit for tlH. toH.
Truth Table
Operation
Condition of Outputs
ME
WE
L
L
Write
TRI-STATE
L
H
Read
Complement of Selected Word
H
L
Inhibit, Storage
TRI-STATE
H
H
Inhibit, Storage
TRI-STATE
AC Test Circuits
tOH
All Other AC Tests
tlH
vee
)
~
·IDk
IIl'flI
•
iiiiffijf
-~5.DpF
T
mm
OUTPUT
10k f5.OPF
~
-=
TL/F/5925-4
TL/F/5925-3
S-SS
G-r.J
iill'fPli'f
50PF
TL/F/5925-5
Switching Time Waveforms
Read Cycle (Note 1)*
-
Write Cycle (Note 1)*
Vcc----h.._---""
E ilii[f
ADDRESS
INPUT
ADDRESS
INPUT
TL/F/5925-6
TL/F/5925-7
Read-Modlfy-Wrlte Cycle (Note 1)*
mliRV
tOH
MI!
Vee---I"7----""
ENABLE
Ye:
Juyec
YCC~TRI.srATE"
Vee-----_
ADDRESS
LATCHED ADDRESS
INPUT
D
-.-
D.IYee
IIlIn
TL/F/5925-9
Vee
m
IiliifEvee
IliAm
QIIiI!
'ODr_
yee-------------
DA~:
X,,_____..~
TL/F/5925-B
Note I': MEMORY ENABLE musl be broughl high for IME ns between every address change.
Note 2: I, = II = 20 ns for all inputs.
5-56
TLlF/5925-10
.---------------------------------------------------------------------'z
3:
~National
~
o
N
....
Semiconductor
oIl>o
.......
~
NMC2147H 4096 x 1-Bit Static RAM
General Description
Features
The NMC2147H is a 4096-word by 1-bit static random access memory fabricated using N-channel silicon-gate technology. All internal circuits are fully static and therefore require no clocks or refreshing for operation. The data is read
out nondestructively and has the same polarity as the input
data.
The separate chip select input automatically switches the
part to its low power standby mode when it goes high.
The output is held in a high impedance state during write to
simplify common I/O applications.
•
•
•
•
•
•
•
•
•
All inputs and outputs directly TTL compatible
Static operation-no clocks or refreshing required
Automatic power-down
High-speed-down to 35 ns access time
TRI-STATE® output for bus interface
Separate Data In and Data Out pins
Single + 5V supply
Standard 18-pin dual-in-line package
Available in MIL-STD-883 class 8 screening
Logic Symbol *
Block Diagram*
,..!!.o vee
Aa
.!ovss
A'
A2
A3
A4
MEMORY ARRAY
B4ROWS
A.
D,.,D)
AI
84 COLUMNS
DDUy,D)
A7
A.
A'
A,a
A11
DUll (D)
Ai
C!
,!)
WE
iWI
Y Y
TLI015257-2
COLUMN I/O CIRCUITS
°OUl(O)
C! 1Il1-,a't1'-a..-
Connection Diagram*
miWI,~·~r-~______~~~+-++_+~~~~--~
Dual-In-Line Package
Alt
Ala
A9
A.
A7
A.
1B
Aa
TLI015257-1
A'
A'
Pin Names·
AO-A11
Address Inputs
Write Enable
WErN)
CS(S)
Chip Select
Data In
DIN (D)
Data Out
DOUT(Q)
Power (5V)
Vee
Ground
Vss
1& A7
,.
A2
Order Number NMC2147HJ-1,
NMC2147HJ-2, NMC2147HJ-3,
or NMC2147HJ-3L
See NS Package Number J18A
vee
17
,.
A3
A4
"
A.
A'
A9
A,a
12 All
Dauy,n) 7
WEiWI'
11 0,.(0)
,a . . ,S)
vss
TLI015257-3
Top View
·The symbols in parentheses are proposed industry standard.
5-57
•
Absolute Maximum Ratings
Truth Table*
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage on Any Pin Relative to VSS
-3.5Vto +7V
Storage Temperature Range
Power Dissipation
- 65'C to + 150'C
1.2W
DC Output Current
20mA
-65'Cto +135'C
Bias Temperature Range
Lead Temperature (Soldering, 10 sec.)
DIN
(D)
DOUT
(Q)
Mode
Power
X
X
L
L
H
H
L
Hi-Z
Hi-Z
Hi-Z
DOUT
Not Selected
Write 1
Write 0
Read
Standby
Active
Active
Active
CS
(S)
WE
(W)
H
L
L
L
X
300'C
DC Electrical Characteristics TA = O'C to +70'C, VCC = 5V ± 10% (Notes 1 and 2)
Symbol
Parameter
NMC2147H-l
NMC2147H-2
NMC2147H-3
NMC2147H-3L
Conditions
Min
= OV to 5.5V, VCC = Max
Max
Min
Max
IILlI
Input Load Current
(All Input Pins)
VIN
IiLOI
Output Leakage
Current
CS = VIH, VOUT
VCC = Max
VIL
Input Low Voltage
-3.0
0.8
-3.0
0.8
VIH
Input High Voltage
2.0
6.0
2.0
6.0
VOL
Output Low Voltage
VOH
ICC
= GND to 4.5V,
= 8.0mA
Output High Voltage IOH = -4.0mA
Power Supply
VIN = 5.5V, TA = O'C,
IOL
NMC2147H
Min
Units
Max
10
10
10
/LA
50
50
50
/LA
-3.0
0.8
V
2.0
6.0
V
0.4
V
0.4
0.4
2.4
2.4
2.4
V
125
180
160
mA
20
30
20
mA
30
40
30
mA
Output Open
Current
= Min to Max, CS = VIH
ISB
Standby Current
VCC
IPO
Peak Power-On
Current
VCC = VSS to VCC Min,
CS = Lower of VCC or VIH Min
Capacitance TA = 25'C, f = 1 MHz (Note 3)
Symbol
Parameter
Conditions
Min
Max
Units
5
pF
6
pF
= OV
CIN
Address/Control Capacitance
VIN
COUT
Output Capacitance
VOUT
= OV
Note 1: The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute.
Note 2: These circuits require 500 /los time delay after vee reaches the specified minimum limit to ensure proper orientation aiter power-on. This allows the
Internally generated substrate bias to reach its functional level.
Note 3: This parameter Is guaranteed by periodic testing.
AC Test Conditions
Input Test Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level (H-l)
Output Timing Reference Level
(H-2, H-3, H-3L)
GNDt03:0V
DDUT
5V
(
C
5ns
1.5V
~
.~51on
1.5V
0.8V and 2.0V
Output Load
•
:~ 300n
See Figure 1
•
-:=
-
30pF
(INCLUDING
SCDPEAND
FIXTURE)
~
FIGURE 1. Output Load
'Symbols in parentheses are proposed Industry standard.
5-58
TL/D/5257-4
z
Read Cycle AC Electrical Characteristics TA =
:s::
0
0'Ct070'C, vcc = 5V ±10% (Note 1)
N
Symbol
NMC2147H-1
NMC2147H-2
Parameter
Alternate Standard
Min
Max
35
Min
NMC2147H-3
NMC2147H-3L
Max
Min
45
-0.
NMC2147H
Max
55
Min
Max
ns
tRC
TAVAV
Read Cycle Time
tM
TAVOV
Address Access Time
35
45
55
70
ns
tACS
TSLOV
Chip Select Access Time
(Notes 4)
35
45
55
70
ns
tLZ
TSLOX
Chip Select to Output Active
(Note 5)
5
tHZ
TSHOZ
Chip Deselect to Output
TRI-STATE (Note 5)
0
tOH
TAXOX
Output Hold from Address
Change
5
tpu
TSLIH
Chip Select to Power-Up
0
tpo
TSHIL
Chip Deselect to Power-Down
0
30
0
5
30
5
0
0
30
5
20
20
ns
ns
ns
0
0
20
ns
10
10
5
30
70
30
ns
NMC2147H-1
NMC2147H·2
NMC2147H·3
NMC2147H-3L
NMC2147H
Access (TAVOV-ns)
35
45
55
55
70
Active Current (lCC-mA)
180
180
180
125
160
Standby Current (lSB-mA)
30
30
30
20
20
Max Access/Current
Read Cycle Waveforms*
_______
Read Cycle 1 (Continuous Selection CS = VIL, WE = VI H)
ADDRESS
~
~======~_~llicM.======~,
}E
'AA
",VUV/
DATA DUT
PREVIOUS DATA VALID
DATA VALlO
---4---~--~~
r---(T~~~XI----l
TL/D/5257-5
Read Cycle 2 (Chip Select Switched, WE = VI H) (Note 4)
I---------ITA'::VI---------r
CHIPSELE~ ~
1,-------tACS
I--~Mx) (TSL~
DATA OUT
VCC ICC _ _ _
SUPPLY
CURRENT
'HZ
(TSHDZ)
I
DATA VALID
HIGH IMPEDANCE
J____~ ~LlH)
HIOH IMPEDANCE
tpo
-
~I
(TSHIL~",,-\_ _ __
SOH
ISS - - - - - -
TL/D/5257-6
Nota 4: Addresses must be valid coincident with or prior to the chip select transition from high to low.
Nota 5: Measured ±50 mV from steady state voltage. This parameter is sampled and not 100% tested.
'The symbols in parentheses are proposed industry standard.
5-59
"":::J:
'-..I
Units
Write Cycle AC Electrical Characteristics TA = 0·Ct070·C, vcc =
Symbol
NMC2147H-1
NMC2147H-2
Parameter
Alternate Standard
TAVAV
twe
Min
Write Cycle Time
Max
Min
35
Max
5V ±10% (Note 1)
NMC2147H-3
NMC2147H-3L
Min
NMC2147H
Max
Min
Units
Max
45
55
70
ns
55
ns
tew
TSLWH
Chip Select to End of Write
35
45
45
tAW
TAVWH
Address Valid to End of Write
35
45
45
55
ns
tAS
TAVSL
TAVWL
Address Set-Up Time
0
0
0
0
ns
twp
TWLWH
Write Pulse Width
20
25
25
40
ns
tWR
TWHAX
Write Recovery Time
0
0
10
15
ns
tow
TDVWH
Data Set-Up Time
20
25
25
30
ns
tOH
TWHDX
Data Hold Time
10
10
10
10
ns
twz
TWLQZ
Write Enable to Output
TRI-STATE (Note 5)
0
tOw
TWHQX
Output Active from End
of Write (Note 5)
0
Write Cycle Waveforms*
20
0
25
0
0
25
0
0
0
35
ns
ns
(Note 6)
Write Cycle 1 (Write Enable Limited)
twc
(TAVAV)
ADDRESS
~
-
.-l
tcw
\TSLWHI
-,~ ~
1iImm'f~ ~
tAW
1',Avonl
If~e~LI
twR
l,onAIII
'WI'
(TWLWH)
-'~
TITNAm
tow
ITOVWHI
,
DATA IN
)
DATA IN VALID
(~~Z)
DATA OUT
tDH
(TWHDX)
-
1HIGH IMPEDANCE
, UNDEFINED
"
tow
(TWHDX).
~~
TLIDI5257 -7
5-60
Write Cycle Waveforms*
z
:s:::
o
N
(Note 6)
....
.a:..
Write Cycle 2 (Chip Select Limited)
.....
:::J:
DATA IN
------------------~~--------------~~----------
DATA
TL/D/5257-8
Nole 6: The output remains TRI-STATE if the CS and WE go high simultaneously. WE or CS or both must be high during the address transitions to prevent an
erroneous write.
'The symbols in parentheses are proposed industry standard.
5·61
:c
! ~National
~ ~ Semiconductor
z
NMC2148H 1024 x 4-Bit Static RAM
General Description
Features
The NMC2148H is a 1024-word by-4-bit static random access memory fabricated using N-channel silicon-gate technology. All internal circuits are fully static and therefore require no clocks or refreshing for operation. The data is read
out nondestructively and has the same polarity as the input
data.
The separate chip select input automatically switches the
part to its low power standby mode when it goes high. Common input/output pins are provided.
•
•
•
•
•
•
•
•
All inputs and outputs directly TTL compatible
Static operation-no clocks or refreshing required
Automatic power-down
High-speed-down to 45 ns access time
TRI-STATE output for bus interface
Common data 1/0 pins
Single + 5V supply
Standard 18-pin dual·in-line package
Block Diagram*
AI
Logic Symbol*
000----1
AD
A. 000----1
.. 0 - - - - - 1
II
AI
.....-!.ova
A3
AZ
A4
MEMORY ARRAY
ROW
•• 0------1
+..ll.ovcc
84 ROWS
SELECT
"COLUMNS
,oF84
A.o""ll_ _ _-I
11
•• 00"----1
'1114
COO4I
11
TL/D17404-3
Connection Diagram*
co':' o",,'3....1+-i--I
Dual-In-Llne Package
'ill' ,.
COOl)
'8
AI
yee
17 A1
A5
AI
A3
CleJ)
AD
1.
m~I~~==~:)
________________
A'
~
TL/D17404-1
Pin Names'
Address Inputs
WE(W)
Write Enable
es(S)
Chip Select
1/01-1/04 Data Input/Output
(001-0Q4)
vee
Power (5V)
VSS
Ground
AO-A9
AZ
CI(!I
vss
Order Number NMC2148HJ-L,
NMC2148HJ-3L, NMC2148HJ,
NMC2148HJ-2 or NMC2148HJ-3
See NS Package Number J18A
'Symbolsln parentheses are proposed Industry standard.
5-62
TL/DI7404-2
Top View
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin with Respect to VSS
-3.5Vto +7V
Storate Temperature
Temperature with Bias
DC Output Current
z
s:::
oN
..
Truth Table
-65'C to + 150'C
-10'Cto +85'C
CS
WE
I/O
Mode
Power
H
L
L
L
X
Hi·Z
H
L
DOUT
Standby
Write 1
Write 0
Read
Standby
Active
Active
Active
L
L
H
~
co
::t:
20 rnA
1.2W
Power Dissipation
Lead Temperature (Soldering, 10 sec.)
300'C
DC Electrical Characteristics TA = O'C to + 70'C, vcc = 5V ± 10% (Notes 1 and 2)
Symbol
Parameter
Conditions
NMC2148H-L
NMC2148H-3L
NMC2148H
NMC2148H-2
NMC2148H-3
Min
Min
Max
Units
Max
jill I
Input Load Current
(All Input Pins)
VIN = OV to 5.5V,
VCC = Max
IILol
Output Leakage Current
CS = VIH, VOUT
VCC = Max
VIL
Input Low Voltage
-2.5
0.8
-2.5
0.8
V
VIH
Input High Voltage
2.1
6.0
2.1
6.0
V
VOL
Output Low Voltage
10L
0.4
V
VOH
Output High Voltage
IOH
ICC
Power Supply Current
VIN = 5.5V, TA
Output Open
125
180
rnA
ISB
Standby Current
VCC
IPO
Peak Power-On Current
VCC = VSS to VCC Min,
CS = Lower of VCC or VIH Min
Iiosl
Output Short Circuit Current
VOUT
= GND to 4.5V,
= 8.0 rnA
= -4.0mA
10
10
/LA
50
50
/LA
0.4
2.4
2.4
= O'C,
= Min to Max, CS = VIH
= GND to VCC
V
20
30
rnA
30
40
rnA
250
250
rnA
Capacitance TA = 25'C, f = 1.0 MHz (Note 3)
Symbol
Parameter
Conditions
CIN
Address/Control Capacitance
CliO
Input/Output Capacitance
Min
= OV
VIIO = OV
VIN
Max
Units
5
pF
7
pF
Note 1: The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute.
Note 2: These circuits require 500 I"s time delay after vee reaches the specified minimum limit to ensure proper operation after power·on. This allows the
Internally generated substrate bias to reach its functional level.
Note 3: This parameter is guaranteed by periodic testing.
AC Test Conditions
Input Test Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Levels
Output Load
Dour
GNDto 3.0V
5 ns
5V
4800
1.5V
0.8V and 2.0V
See Figure 1
~
q''''''"'''3D pF
2550
AND FIXTURE)
TL/D17404-4
FIGURE 1. Output Load
5-63
::c
co
:!:
Read Cycle AC Electrical Characteristics TA =
~
z
Symbol
:IE
O'C to
+ 70'C. vcc =
Alternate Standard
Min
NMC2148H
NMC2148H·L
NMC2148H·3
NMC2148H·3L
NMC2148H·2
Parameter
5V ± 10% (Note 1)
Min
Max
Min
tRC
TAVAV
Read Cycle Time
TAVQV
Address Access Time
45
55
70
ns
tACSl
TSLQV1
Chip Select Access Time (Notes 4 and 5)
45
55
70
ns
tACS2
TLSQV2
Chip Select Access Time (Notes 4 and 6)
55
65
80
ns
tLZ
TSLQX
Chip Select to Output Active (Note 7)
20
tHZ
TSHQZ
Chip Deselect to Output TRI-STATE (Note 7)
0
tOH
TAXQX
Output Hold from Address Change
5
tpu
TSLIH
Chip Select to Power-Up
0
tpo
TSHIL
Chip Deselect to Power-Down
NMC2148H·2
55
Units
Max
tAA
Max Access/Current
45
Max
70
20
20
20
0
20
ns
0
5
20
5
0
ns
30
NMC2148H
30
NMC2148H·3L
ns
ns
0
30
NMC2148H·3
ns
ns
NMC2148H·L
Access (TAVQV-ns)
45
55
70
55
70
Active Current (ICC-mA)
180
180
180
125
125
Standby Current (ISB-mA)
30
30
30
20
20
Read Cycle Waveforms*
ADDRESS
DATA OUT
-
Read Cycle 1 (Continuous Selection CS = VIL, WE = VIH)
'RC
......
'REVIDUS DATA VALID
DATA VALID
--~----~~--~
~,,,,,,!,!.~~~v,,---I
TL/DI7404-5
Read Cycle 2 (Chip Select Switched, WE = VIH) (Note 4)
CHIP SELECT 1
~
I------------------'~A~hl------------------I
1,-------1 - - - - - - (T~~~~, --------11
~1T;t~,----I
DATA OUT
VCC ICC
SUPPlY
CURRENT
'HZ
~HIIZI
DATA VALID
HIDH IMPEDANCE
----I----t~LlHI
. . . __
HIGH IMPEDANCE
~~~L~1
.""
ISS - - - - - -
TL/DI7404-6
Note 4: Addresses must be valid coincident with or prior to the chip select transition from high to low.
Nota 5: Chip deselected longer than 55 ns.
Not. 6: Chip deselected less than 55 ns.
Not. 7: Measured ± 50 mV from steady state voltage. This parameter is sampled and not 100% tested.
'The symbols In parentheses are proposed industty standard.
5-64
z
Write Cycle AC Electrical Characteristics TA =
Symbol
O'Cto +70'C, vcc = 5V ±10% (Note 1)
N
NMC2148H·2
Parameter
Alternate Standard
s:
o
Min
Max
NMC2148H·3
NMC2148H·3L
Min
Max
NMC2148H
NMC2148H·L Units
Min
TAVAV
Write Cycle Time
45
55
70
ns
tew
TSLWH
Chip Select to End of Write
40
50
65
ns
tAW
TAVWH
Address Valid to End of Write
40
50
65
ns
tAS
TAVSL
TAVWL
Address Set-Up Time
0
0
0
ns
twp
TWLWH
Write Pulse Width
35
40
50
ns
tWR
TWHAX
Write Recovery Time
5
5
5
ns
tDW
TDVWH
Data Set-Up Time
20
20
25
ns
TWHDX
Data Hold Time
0
twz
TWLQZ
Write Enable to Output TRI-STATE (Note 7)
0
tow
TWHQX
Output Active from End of Write (Note 7)
0
Write Cycle Waveforms*
0
15
0
0
20
0
0
0
co
:c
Max
twe
tDH
......
.c:.
ns
25
ns
ns
(Note B)
Write Cycle 1 (Write Enable Limited)
'Wc
(TAVAV)
ADDRESS
:=Jf-
-Htcw
(TSLWHI
CHIP SELECT
,~ ~~
~ ~b
\r~e~LI
WRITE ENABLE
'-!~~"
,'.... n'
-~~.
IIwHAXI
I-(TW~~H)
~b
,I-
tow
(TOVWH)
DATA IN
-l {.
tOH
(TWHDX)
-c (-
,IN VALID
1-(~tZI-
1HIGH IMPEDANCE
r-
DATA OUT
tow
(TWHQX)
~
XXXXXXXXX
TL/D17404-7
III
5-65
::c
!
Write Cycle Waveforms*
(Note 8) (Continued)
N
o
Write Cycle 2 (Chip Select Limited)
:::E
(T~iVI------~-----1
Z
J1-1____________________-t'-_______________
DATAIN __________________________
DATA DUT
-----------------------~
TL/DI7404-8
Note 8: The oulput remains TRI·STATE If the CS and WE go high simulataneously. WE or CS or both must be high during the address transitions to prevent an
erroneous write.
'Symbols in parentheses are proposed industry standard.
5·66
~National
~
Semiconductor
DM75S68/DM85S68/DM75S68A/DM85S68A
16 x 4 Edge Triggered Registers
General Description
Features
These Schottky memories are addressable "0" register
files. Any of its 16 four-bit words may be asynchronously
read or may be written into on the next clock transition. An
input terminal is provided to enable or disable the synchronous writing of the input data into the location specified by
the address terminals. An output disable terminal operates
only as a TRI-STATE® output control terminal. The addressable register data may be latched at the outputs and retained as long as the output store terminal is held in a low
state. This memory storage condition is independent of the
state of the output disable terminal.
All input terminals are high impedance at all times, and all
outputs have low impedance active drive logic states and
the high impedance TRI-STATE condition.
•
•
•
•
•
•
•
•
•
On-chip output register
PNP inputs reduce input loading
Edge triggered write
High speed-20 ns typ
All parameters guaranteed over temperature
TRI-STATE output
Schottky-clamped for high speed
Optimized for register stack applications
Typical power dissipation-350 mW
Logic and Block Diagram
(DATA INPUTS)
02
(WRITE CLOCK INPUT)
03
I
Pin Names
CLK
14
11
AO-A3
Address Inputs
01- 0 4
Data Inputs
01-04
Data Outputs
WE
Write Enable
m~lS~tx~______________~~~~~~~~~--~
ClK
Write Clock Input
A' ~~
~ ~ ~
OS
Output Store
00
Output Disable
(WRITE ENABlEI
AI~~
16 a 4MEMORY CELL ARRAY
OD
~~
Al~
WE ClK
Os
MODE
0
X
X
X
0
...r
0
X
X
1
1
1
X
X
0 Output Store
X
X
1
OUTPUTS
0 Output Store
Data From Last
Addressed Location
X WrtteData
Dependent on State
of 00 and OS
13
M~----~----4r-+~----~~----~-4~--~
,OUTPUT
STOREl
Read Data
Data Stored in
Addressed location
High Impedance State
Output Disable High Inpedance State
0= Low level
1 = High Level
X = Don't Care
1212.~f:;:=~t,:=~~~
"0-;:
(OUT'UT
DISABLE)
(OUTPUTSI
TL/F/9233-1
5-67
•
Absolute Maximum Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7.0V
Input Voltage
5.5V
Output Voltage
5.5V
Storage Temperature Range
-65'Cto + 150'C
Temperature (Soldering, 10 sec.)
300'C
Supply Voltage, Vee
DM85S68/DM85S68A
DM75S68/DM75S68A
Temperature, TA
DM85S68/DM85S68A
DM75S68/DM75S68A
Min
Max
Units
4.75
4.5
5.25
5.5
V
V
0
-55
70
+125
'C
'C
Electrical Characteristics
over recommended operating free-air temperature range unless otherwise noted (Notes 2 and 3)
Symbol
Parameter
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VOH
High Level Output Voltage
Conditions
Min
Max
Typ
0.8
10H = -2.0 rnA,
DM75S68/DM75S68A
Vee = Min
10H = -5.2 rnA,
DM85S68/DM85S68A
,
Units
V
2
V
2.4
V
2.4
V
VOL
Low Level Output Voltage
Vee = Min,
10L = 16mA
IIH
High Level Input Current
Vee = Max, VIH = 2.4V
II
High Level Input Current
at Maximum Voltage
Vee = Max, VIH
IlL
Low Level Input Current
Vee = Max,
VIL = 0.5V
Clock Input
-500
p.A
All Others
-250
",A
= OV
-55
rnA
100
mA
los
Short Circuit Output Current
(Note 4)
Vee = Max, VOL
DM75S68/DM75S68A
0.5
DM85S68/DM85S68A
0.45
V
25
",A
50
",A
= 5.5V
-20
Icc
Supply Current
Vee = Max
VIC
Input Clamp Voltage
Vee = Min, liN = -18 rnA
loz
TRI-STATE Output Current
Vee= Max.
70
Va = 2.4V
V
-1.2
V
+40
/LA
-40
Va = 0.5V
",A
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2. Unless otherwise specified minImax limits apply across the -55·C to + 125·C temperature range for the DM75S68/DM75S68A and across the O"C to
+ 70"C range for the DM85S68/DM85S68A. All typicals are given for Vee ~ 5.0V and TA ~ 25·C.
Note 3: All currents into device pins shown as posit~e. out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Switching Characteristics
Symbol
over recommended operating range of TA and Vee unless otherwise noted
Parameter
DM75S68
Min
Max
DM85S68
Min
Max
DM75S68A
DM85S68A
Min
Min
Max
Units
Max
tZH
Output Enable to High Level
40
35
40
35
ns
tZL
Output Enable to Low Level
30
24
30
24
ns
tHZ
Output Disable Time from High Level
35
15
35
15
ns
tLZ
Output Disable Time from Low Level
35
18
35
18
ns
tAA
Access Time
55
40
45
24
ns
20
ns
35
ns
Address to Output
tOSA
Output Store to Output
35
30
35
teA
Clock to Output
50
40
50
5-68
Switching Characteristics
over recommended operating range of T A and Vcc unless otherwise noted (Continued)
Symbol
DM75S68
Parameter
Min
Max
DM85S68
Min
Max
DM75S68A
DM85S68A
Min
Min
Max
Units
Max
Address to Clock
25
15
25
15
ns
tosc
Data to Clock
15
5
15
5
ns
tASOS
Address to Output Store
40
30
40
10
ns
tWESC
Write Enable Set-Up Time
10
5
10
5
ns
tossc
Store before Write
15
10
15
10
ns
ns
tASC
Set-UpTime
Address from Clock
15
10
15
10
tOHC
Data from Clock
20
15
20
15
ns
tAHOS
Address from Output Store
10
5
10
2
ns
tWEHC
Write Enable Hold Time
20
15
20
10
ns
tAHC
Hold Time
Connection Diagram
Dual-In-Llne Package
1~18
--Vee
OZ---
Z
01---
-- 03
A02
..!! 04
4
AZ---
.!!WE
5
A3--
-elK
6
Al--
..!! OS
01.2.
.!!oo
oz..!
.!.!. 04
GNO.!
10
I""" 03
17
14
TL/F/9233-2
Top View
Order Number DM75S68J, DM85S68J,
DM85S68N, DM75S68AJ,
DM85S68AJ or DM85S68AN
See NS Package
Number J18A or N18A
•
5-69
i
AC Test Circuit and Switching Time Waveforms
5.0V
GO
::&
Q
~
CL = 5.0 pF for 1HZ, ILZ
CL = 30 pF for all others
CL includes probe and jig capacitance
All diodes are 1N3064
OUTPUT
::&
DM16S881
DM85SB81
DM76SBBAI
DM86S88A
Q
I
::&
Q
.....
GO'
m
::&
TUL/9233-3
Q
ADDRESS
INPUT
Write Cycle
Read Cycle
Clock Set·Up and Hold Time
Address to Output Access Time
r---"'
15V\.r----------
ADDRESS
INPUT ~ _ _ ~J"7If\1
\..___________
1.5V
-.AA-I r------·
DATA
INPUT
OUTPUTS _ _ _ _ _ _
~~'i(,,_______
TL/L/9233-6
Output Store Access, Set·Up and Hold Time
OUTPUT
STORE
A~~~~~ ~---X1.5V
__ J .
WRITE
ENABLE
WRITE
CLOCK
O~:~~~
------.W-EH.JC~--
l-tAHos~I'--1.5V
-----
1.5V
OUTPUTS
TUU9233-4
TL/L/9233-7
Clock to Output Access
Output Disable and Enable Time
I~~~~
----I.-5V"')I(------ - --,
____ J .
WRITE
CLOCK
1.5V
•
OUTPUT
DISABLE
i
+
1.5V--t-'-+:oI""-__r--....:+-:-::
O.SV
VaL--~r.l
_ _ _ _L_IcA""""'\-I, __
OUTPUTS _ _ _ _ _ _ _ _ _ _
\1.5V
"T
OUTPUT
VOH--~"""
~.~L
TL/U9233-5
D.SV
1.5V--+--+-..30----+--~f-_,_
TL/L/9233-8
Note: Input waveforms supplied by pulse generator having Ihe following characteristics: V=3.0V, 1R,,2.5 ns, PRR"I.0 MHz and loUT
5·70
= 5OM.
Section 6
Appendicesl
Physical Dimensions
Section 6 Contents
STARTM Surface Mount Tape-and-Reel Specification ........... . . . . . . . . . . . . . . . . . . . . . . . .
Physical Dimensions............... ............ ............. ............... ........ .
Bookshelf
Distributors
6·2
6-3
6-31
~National
~
PRELIMINARY
Semiconductor
SEMICONDUCTOR TAPE·AND·REEl SYSTEM
STARTM Surface Mount
Tape-and-Reel Specification
General Description
• Fully compatible with National's surface mount package
types
• Variable code density code 39 bar code label for Automated Inventory Management availability
• Mechanical samples of surface mount packages available in Tape-and-Reel for automated assembly process
development
• Single Tape-and-Reel holds hundreds-to-thousands of
surface mount semiconductors for additional labor savings
• Conductive cover Tape-and-Reel availability
• Reels individually packed
Tape-and-Reel is a new method for shipment of surface
mount devices. This approach simplifies the handling of
semiconductors for automated circuit board assembly systems. A Tape-and-Reel holds hundreds-to-thousands of
surface mount devices (as compared with less than 100
devices in a rail), so that pick-and-place machines have to
be reloaded less frequently. This savings in labor will further
reduce manufacturing costs for automated circuit board assembly.
Features
• Conductive PVC material redeuces static charge buildup
• Fully meets proposed EIA standard RS-481A (taping of
surface-mounted components for automatic placing)
Tape-and-Reel Diagram
COVER TAPE
(SECURES DEVICE
IN CAVITY)
ARBOR HOLE
(FOR MOUNTING REEL
ON PICK-ANO·PLACE
MACHINE)
LABEL
(IDENTIFIES
DEVICE CONTENTS)
\ SPROCKET HOLES
(GUIDE TAPE IN
PICK·AND·PLACE
MACHINE)
REEL
(CARRIES
TAPE OURING
SHIPPING AND
COMPONENT
FEEDING)
"MADE OF CONDUCTIVE PVC MATERIAL
TL/HH/8352-1
6-3
Tape-and-Reel Overview
TAPE FORMAT AND DEVICE ORIENTATION
DIRECTION
OF FEED
+
r--TRAILER
SECTION
•
00000000000000000000000000 0
~
-
i
I
I
I
I
I
I
I
END
I
I
I
CAVITIES
• UNSEALED
COVEll TAPE
I
- - -
'------0-" '-----r--"
• EMPTY
CAVITIES
• SEAlED COVER TAPE
CAVITIES
'EMI'TY
• SEALED
COVEll TAPE
[iJ
I
r~ 110:
i~ 0
i
I _________ I
L!
~
I
0
I
I
I
I
I
I
I _________ I
L!
~
OPTION 2
I
PIN1
oRIENTATIDN
I
I
I
I
L!_
j
0
0
0
0
COVERTAPE
1
1~1
II~
II
1
=1
t.=
I
SO-IC
DEVICES
!
I
SOT-23
• UNSEALED
COVERTAPE
r;- -------;,
r.-------'-:1
iI 11;U111I iI 11";111I
.oPTIDN'
'----r--"'------o-"
CAVITIES
~.'EMI'TY
• FILLED CAVITIES . (
• SEALED
I
-I
0 0 0 10 0 00000 000000000
I
I
HUB
• EMPTY
+
CARRIER SECTII*
pce-IC
~
DEVICES
DEVICES
TLlHH/B352-2
Page
Small Outline Transistor
Small Outline IC (SO-IC)
Page
PLCC-20
11
PLCC-28
12
4
PLCC-44
13
5
PLCC-68
14
SO-14 (Wide)
6
PLCC-84
15
SO-16 (Narrow)
7
SO-16 (Wide)
8
SOT-23 (High Profile)
3
SOT-23 (Low Profile)
3
SO-8 (Narrow)
50-14 (Narrow)
SO-20 (Wide)
9
SO-24 (Wide)
10
Plastic Chip Carrier IC (PLCC-IC)
MATERIALS
• Cavity Tape:
Conductive PVC (less than 105 O/Sq)
• Cover Tape:
Polyester
1. Conductive Cover available
• Reel: 1. Solid 80 pt. Fibreboard (standard)
2. Conductive Fibreboard available
3. Conductive Plastic (PVC) available
LABEL
Human and machine readable label is provided on reel. A variable (C.P.I.) density code 39 is available. NSC STO Label (7.6
C.P.I.).
Field
Lot Number
Date Code
Revision Level
National Part No. 1.0.
Quantity
Example:
LOT
(NUMBER
LOT,
EPb3'3b3KD2?
DATE
(CODE
Ole,
Mllb44
(REVISION
NUMBER
R,
IIIIIIIIIII••UIIIII IIIIIIRI.
INiNliiIMlillfl.llllilil~II.lgIBQTYlliilll
Fields are separated by at least one blank space.
Future Tape-and-Reel packs will also include a smaller-size
bar code label (high-density code 39) at the beginning of the
tape. (This tape label is not available on current production.)
NATIONAL SEMICONDUCTOR PART NUMBER
TL/HH/D352-3
National Semiconductor will also offer additional labels containing information per your specific specification.
6-4
.-----------------------------------------------------------------------,~
~
SOT-23 (High Profile), SOT-23 (Low Profile)
::tI
TAPE FORMAT
Tape Section
Leader
(Start End)
Direction
of
Carrier
t
Feed
Trailer
(Hub End)
# Cavities
Cavity Status
Cover Tape Status
5 (min)
Empty
Unsealed
5 (min)
Empty
Sealed
t'2500 (High)
Filled
Sealed
t'3000 (Low)
Filled
Sealed
2 (min)
Empty
Sealed
2 (min)
Empty
Unsealed
'These quantities represent 7' Reel Quantity availability.
tlO,OOO For 13" Reel.
TAPE DIMENSIONS
O.041±O.OO2 TVP
1.O5±O.05
h'3Ll
MAXIMUM AWlWAllLE
BEND RADIUS
TL/HH/8352-4
REEL DIMENSIONS
I--I I
0.567 MAx--l
14.4
0.512 ±0.OO2
13±0.05
L
I"
TL/HH/8352-5
6·5
a:
~
50-8 (Narrow)
TAPE FORMAT
Tape Section
# Cavities
Cavity Status
Cover Tape Status
5 (min)
Empty
Unsealed
5 (min)
Empty
Sealed
2500
Filled
Sealed
2 (min)
Empty
SeaJed
2 (min)
Empty
Unsealed
Leader
(Start End)
Direction
of
t
Feed
Carrier
Trailer
(Hub End)
TAPE DIMENSIONS
0.157±0.OM TVPbO.l
w-jr-
J.~ .~.-rt=~
@TANGi;;:O~N~~)
(-----i,.- 12r
~0-.~-B5-±±-001-00-4~4~~------~~-~----------~.
..
___
~_-L__
O.~±O.OM
2.1±0.1
0.25B±0.DM
6.55±0.1
@TANGEIITPOINTS
HI-"
II
-+I
B· MAX
~=t=ffibJtj b~
(2.1)
(0.3)
MAXIMUM ALLOWABLe
BEllO RADIUS
TUHH/8352-6
REEL DIMENSIONS
O.724 MAX
18.4
-i II I
O.512±O.OO2
13±0.05
~
(330)
L
((OJ'\)====:::t=il'1.1.'969
'._/
50
I
FUURAOIUS
0.488·::::
II
12.4": ----..,
6-6
r-
TL/HH/8352-7
SO-14 (Narrow)
TAPE FORMAT
Tape Section
# Cavities
Cavity Status
Cover Tape Status
5 (min)
Empty
Unsealed
5 (min)
Empty
Sealed
2500
Filled
Sealed
2 (min)
Empty
Sealed
2 (min)
Empty
Unsealed
Leader
(Start End)
Direction
of
i
Feed
Carrier
Trailer
(Hub End)
TAPE DIMENSIONS
0.157:!: 0.004
~TYP
tllO.61±O.002
o
0
O. ~9:t±O~O~02 TYP
_
l.S5±O.05
O'~~795 ~~~04
~_L
TYP
o o o
0
o
B'MAX
O~--.----
/
0.29S±0.002
7.S±0.OS
0,630± 0.012
c------tt- 16±0.3
t \
I
10,266 ± 0,002)
(6,7S±0,OS)
0.3BO±0,004
9.6S±0,1
@TANGENT POINTS
1
I
I
'---_ _ _ _ O,061±0,002
1.55±O.05
0,OB3 ± 0,004
2hO,1
0,262 ± 0,0041
6.65±O,1 @TANGENTPOINTS
1-
0,3
r-
II
~
~----So MAX
-.--L °O~2
-=r=~J
.~+M~~
(2.1±O.1)
MAXIMUM AlLDWABLE
BEND RADIUS
TLlHH/8352-B
REEL DIMENSIONS
0,059
0,BB2 MAX
22,4
1.5
_1
I-I
0,S12±0.002
13±D.05
L
I
.!l!W
(330)
Tl/HH18352-9
6-7
a:
~
50-14 (Wide)
TAPE FORMAT
Tape Section
Direction
of
II Cavities
Cavity Status
Cover Tape Status
5 (min)
Empty
Unsealed
5 (min)
Empty
Sealed
Sealed
leader
(Start End)
t
1000
Filled
2 (min)
Empty
Sealed
2 (min)
Empty
Unsealed
Carrier
Feed
Trailer
(Hub End)
TAPE DIMENSIONS
\ -_ _ _ 0.15: :
0.79 ± 0.002 TVP
2 ± 0.05
4> 0.61 ± 0.002 TYP
1.55 ± 0.05
o
0
0
:'iD1J4 TYP
0
~(03)-::1i
"
(I'
0.069±0.004
11.75±0.1
MAX
o
0
0.3agt.lIO~
9.65±0.1
o
@TANGENT POINTS
l
0.061:0.002 TYP _ _ _- '
1.55,.0.05
0.472:± 0.004
12,.0.1
0.43hO.D1J4
n.05=O.1
@TANGENTPOIIITS
-rr:J
J!!!J.-:;=r
ir .
•
I MAX
0
L~REF
(0.3)
(3)
MAXIMUM ALlDWAilLE
BENORAOIUS
TL/HH/8352-10
REEL DIMENSIONS
0.059
0.IB2 MAX
22.4
1.5
_1
II
0.512±0.002
13,.0.05
L
I
~
(330)
TL/HH/8352-1 I
6-8
SO-16 (Narrow)
TAPE FORMAT
Tape Section
Leader
(Start End)
Direction
of
t
Feed
# Cavities
Cavity Status
Cover Tape Status
5 (min)
Empty
Unsealed
5 (min)
Empty
Sealed
2500
Filled
Sealed
2 (min)
Empty
Sealed
2 (min)
Empty
Unsealed
Carrier
Trailer
(Hub End)
TAPE DIMENSIONS
_
<1>0.61 + 0.002
1.55:0.05
o
o
0
0
0
~_L
0.79±0.002 TYP
2±0.05
0
,
8' MAX
0+-------.0.295: 0.002
7.5±if.ii5
o
I
c-----+t -
O.Jl±O.~04
I
0.630 ± 0.012
16±0.3
(0.266+0.002!
16.75 ± 0.05!
10.45±0.1
@TANGENT POINTS
~
I
'--_ _ _ _ 0.061 ± 0.002
1.55 ± 0.05
~
0.262% 0.0041
~---"'8'MAX
@ TANGENT POINTS
.
r-
1-
0.3
0.083%0.004
2.1±D.1
I
~
..!!J!B.
0.3
-=c=~-
(0.083+0.004)
12.1±0.1)
I
~
MAXIMUM ALLOWABLE
8END RADIUS
TUHH/B352-12
REEL DIMENSIONS
0.059
0.882
22.4
1.5
MAX-I
II
0.512 ± 0.002
13±0.05
L
I
(13.00)
(330)
TL/HH/B352-13
6·9
SO-16 (Wide)
TAPE FORMAT
Tape Section
# Cavities
Cavity Status
Cover Tape Status
5 (min)
Empty
Unsealed
5 (min)
Empty
Sealed
1000
Filled
Sealed
2 (min)
Empty
Sealed
2 (min)
Empty
Unsealed
Leader
(Start End)
Direction
of
t
Feed
Carrier
Trailer
(Hub End)
TAPE DIMENSIONS
_
/
~ 0.S1 ± 0.002 TYP
1.55 ± 0.05
~6[::J I
/
1.S5±O.05
_
1-
0.79 ± 0.002
2 ± 0.05
10.3)
O.OShO.Oo.
1.75±O.'
(aOMAX
1
0
~ 0.061 ± 0.002 TYP
-ji
0.157 ± 0.004 TYP
4 ± D.l
0
0
0
0
o~
0.295 L.0021
7.S±D.DS
1 D.61~O:O~3012
0
~REF'l
-----:>
•
I
Isr
----f~
O.472±~
.m3±D.1
..
12±O.l
JI ~'"-I~
n.05±O.1
@TANGENT POINTS
~D
~REF
(3)
0
~REF
B MAX
I
0
D'43uL.~\
10.91±D.1
@ TANGENT POINTS
II'
L~REF
(0.3)
MAXIMUM ALLDWABLE
BEND RADIUS
ISEE NOTE 3)
TL/HH/8352-14
REEL DIMENSIONS
---
,--
_.0.059
1.5
0.882 MAX
22.4
0.795
2 .2
l!!Ml
/ ,\
:1
r-
0.512 ±0.002
13 ±0.05
1
( (0"
_!
1 969
~:.."'
L
I
0.646'::::
16.4';
---IITL/HH/8352-15
6-10
50-20 (Wide)
TAPE FORMAT
Tape Section
Leader
(Start End)
Direction
of
i
Feed
# Cavities
Cavity Status
Cover Tape Status
5 (min)
Empty
Unsealed
5 (min)
Empty
Sealed
1000
Filled
Sealed
Carrier
Trailer
(Hub End)
2 (min)
Empty
Sealed
2 (min)
Empty
Unsealed
TAPE DIMENSIONS
~TYPP~
1.55:t 0.05
G
>0 0
>
1--1--
0
0
0
0 79 0 002
-
o
0
0
- ' '2:0.05
boo
0
0
o
1.75 ± 0.1
O+-~--Jr-
0
~
a"MAX
I
!
(--+1-
1--+--1
S{
~
I\
J!!!!l~~
(0.31
II
0.069:t 0.004
C
TYP
".5±0.05
0.453±0.002
0.945 ± 0.012
24:0.3
:::;I~~='~
\
~
13.45,00.1
~~1~':
.-_E.i_PO_IN_TS
. . ___.-=O'l!l
'-------------------+---------+---~~~~----.0-.~--±-0.0-02--~---L-_~
0.412 ± 0.004
12±0.1
2.05±0.05
~ ~
O.nB ± 0.004
3:0.1
J1!lli
(SOl
MAXIMUM ALlOWABL£
BENORADIIIS
REEL DIMENSIONS
0.059
1.197 MAX
30.4
1.5
TLlHH/8352-16
_i
0.512 %0.002
13~0.05
T\
113.001
L
I
.-
(:0' "\,=====1~:tT1.1.969
\~:/
~
FULL RADIUS
0.960'::::
24.4':
II
---"1 r
TL/HH/8352-17
6-11
~
~
r-----------------------------------------------------------------------,
80-24 (Wide)
TAPE FORMAT
Tape Section
Leader
(Start End)
Direction
of
Feed
t
Carrier
Trailer
(Hub End)
II Cavities
Cavity Status
Cover Tape Status
5 (min)
Empty
Unsealed
5 (min)
Empty
Sealed
1000
Filled
Sealed
2 (min)
Empty
Sealed
2 (min)
Empty
Unsealed
TAPE DIMENSIONS
L.lH!nw
(0.3)
MAXIMUM ALLDWAliLE
lEND RADIUS
TLlHH/8352-18
REEL DIMENSIONS
0.059
1.197 MAx-i
30.4
1.5
I-
I
O.512±0.002
1i±D.ii5
L
I
~
. (330)
TLlHH/8352-19
6-12
PLCC-20
TAPE FORMAT
Tape Section
Direction
t
of
# Cavities
Cavity Status
Cover Tape Status
5 (min)
Empty
Unsealed
5 (min)
Empty
Sealed
1000
Filled
Sealed
2 (min)
Empty
Sealed
2 (min)
Empty
Unsealed
Leader
(Start End)
Carrier
Feed
Trailer
(Hub End)
TAPE DIMENSIONS
~-~
~TYP-
.,
4:tD.1
oi~:~::2
TYP
_o.o:~~.~:uz
TYP
I
(BOMAX
o
0
0
G
0
0
0
0
000
a
0.061,.0.002 _ _ _---J
1.55"0.05
---II
0.472 :s:O.OO4
10.193±0.0041 .
14.ho.ll
12±O,1
0'413%0'004@TAHGENTPUINTSH/_
COY
"Bo MAX
1Q.5"i1f.1
=r=LJ 0
~~
4.1%0.1
0\
0.012
\====:t=
MAXIMUM ALLOWABLE
BEND RADIUS
TL/HH/8352-20
REEL DIMENSIONS
0.059
0.882
22.4
1.5
MAX-I
II-
0.512±0.002
13±0.05
(13.001
(3301
/
,
1.969
(,.(0).... ~,()~====t=PL50
L
I
FULL RADIUS
TLlHH/8352-21
6-13
~
PLCC-28
TAPE FORMAT
Tape Section
Leader
(Start End)
Direction
of
Feed
t
"" Cavities
Cavity Status
Cover Tape Status
5 (min)
Empty
Unsealed
5 (min)
Empty
Sealed
750
Filled
Sealed
2 (min)
Empty
Sealed
2 (min)
Empty
Unsealed
Carrier
Trailer
(Hub End)
TAPE DIMENSIONS
L~
4.0±0.1
0.078:1.1102 TYP
2:tO.15
o
0.812
O.0&9:tO.1ID4
1.7I±0.1
T3
o
/-
f\
o
0.&24 :to.OM
~
@ TANGENT POINTS
I
I~"'",O.'
0.113000.004
0.830 :d.DD4
":to,'
~
13.3±0.1
@TAMGENTPOIIfIS
MAXIMUM ALLOWABLE
8ENORADIUS
TUHH/8352-22
REEL DIMENSIONS
0.059
1.197
1.5
38.4
MAX-I
I
I -
~
(330)
FULL RADIUS
TUHH/8352-23
6-14
PLCC-44
Tape Section
Direction
of
t
Feed
Leader
(Start End)
Carrier
Trailer
(Hub End)
# Cavities
Cavity Status
Cover Tape Status
5 (min)
Empty
Unsealed
5 (min)
Empty
Sealed
500
Filled
Sealed
2 (min)
Empty
Sealed
2 (min)
Empty
Unsealed
TAPE DIMENSIONS
0.157:0.1104 TYP
4:0.1
_ 1 , 0 . 0 10.3
2
-L
0.728}0.~
•.5",0.1
@TANGENTPOINTS
l
O.72bO·IIII4H~ ~
lB.5:0.1
@TANGENTPOINTS
(0.203:0.1104)
(5:0.1)
=r= 0
~
n
B' MAX
I'
U-----r
LO.012 REF
0.3
Ref
MAXIMUM ALUlWABLE
BEND RADIUS
TLlHH/8352-24
REEL DIMENSIONS
0.059
1.512
38.4
1.5
MAX-I
I
I -
0.512:0:0.l1li2
lhO.05
L
I
(13.00)
(330)
TL/HH/8352-25
6·15
a:
=:
en
PLCC-68
TAPE FORMAT
Tape Section
Direction
of
Feed
Leader
(Start End)
t
Carrier
Trailer
(Hub End)
# Cavltle.
Cavity Statu.
Cover Tape Statu.
5 (min)
Empty
Unsealed
5 (min)
Empty
Sealed
250
Filled
Sealed
2 (min)
Empty
Sealed
2 (min)
Empty
Unsealed
TAPE DIMENSIONS
/
I" _.D'o:!~.':811111 TYP
;-.0.1111,.11.II1II TYP
1.I1Z0.111
O.lIIbl.1III4
1.75(,.1
ooooooooooooooooooooooooooooooo~.
'r-
.
)
I
~
to
0 0 0
oj
0
~
f
'1.514:t0. •
4O.5:tO.05
SYIIMUOUT
T::.:~
0
CEIITEIIUIIE
I
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0--;;-;-)
L.D...,. .11111
2.1... 0...
r
=r=.cs
'.117 ...... 111FT ......
1:t1.1
MAIOMUM MUIWAIIL£
IENOMDIIS
TUHH/8352-26
REEL DIMENSIONS
__ 1--,0,059
1.5
0.512,00.002
1""0.05
.L.
~I
(330)
"
TLlHH/8352-27
6-16
PLCC-84
TAPE FORMAT
Tape Section
# Cavities
Cavity Status
Cover Tape Status
5 (min)
Empty
Unsealed
5 (min)
Empty
Sealed
250
Filled
Sealed
2 (min)
Empty
Sealed
2 (min)
Empty
Unsealed
Leader
(Start End)
Direction
of
i
Feed
Carrier
Trailer
(Hub End)
TAPE DIMENSIONS
0.15;::';004 TYP
_
D.061±O.002 TYP
1.55±O.05
O.079±O.002 TYP
r
2::tD.05
O.06!J±D.0CI4
----u5±ii:1
t
1.594±O.002
40.S±O.05
SYMM ABOUT
o
o
~
CENTERlI::32±D 012
o
44±03
SYMM ABOUT
CENTERLINE
00000000000000000000000000
1
1.411±O.DIM
O.081±O.DD2 TYP
2.0S±O.05
-~-
1.22&.0.004
-...l/
I--;~TS I---" ~
=r=L511
ULJ-L
MAX
O.197±O.004~
5.0±O.1
~
(0.3)
MAXIMUM ALLOWABLE
BEND RADIUS
TL/HH/8352-28
REEL DIMENSIONS
1.984
MAX-I
50.4
0.059
1.5
0.512 ±0.OO2
13±D.05
T\
~
/ '\======\=±T1.1.969
i,COl)
-.
~
L
I
FULL RADIUS
TL/HH/8352-29
6-17
~
Application-Total System Saving
TAPE·AND·Rm IMPROVES THE COST
SAVINGS OF AUTOMATED ASSEMBLY
BY REDUCING THE LABDilINVOIllED
WRH DEVICE HANDLING.
SEMICDNDUClOR
SUPPlIER
ELECTIIDNIC EDUIPMENT MANUFACTURER
PICK·ANII-PLACE
MACHINE
ASSEMBLED
PC
BOARDS
SIMPLIFIED DEVICE HANDLING DURING AUTOMATED ASSEMBLY
•
TL/HH/8352-32
Cost pressures today are forcing many electronics manufacturers to automate their production lines. Surface mount
technology plays a key role in this cost-savings trend because:
Automated manufacturers can improve their cost savings by
using Tape-and-Reel for surface mount devices. Simplified
handling results because hundreds-to-thousands of semiconductors are carried on a single Tape-and-Reel pack (see
the "Ordering Information" section for the exact quantities).
With this higher device count per reel (when compared with
less than 100 devices per rail), pick-and-place machines
have to be re-Ioaded less frequently and lower labor costs
result.
With Tape-and-Reel, manufacturers save twice-once from
using surface mount technology for automated PC board
assembly and again from less device handling during shipment and machine set-up.
1. The mounting of devices on the PC board surface eliminates the expense of drilling holes;
2. The use of pick-and-place machines to assemble the PC
boards greatly reduces labor costs;
3. The lighter and more compact assembled products resulting from the smaller dimensions of surface mount
packages mean lower material costs.
Production processes now permit both surface mount and
insertion mount components to be assembled on the same
PC board.
6-18
Ordering Information
When you order a surface mount semiconductor, it will be in
one of the 15 available surface mount package types (see
Appendix II for the physical dimensions of the surface
mount packages). Specifying the Tape-and-Reel method of
shipment (Note 1) means that you will receive your devices
in the following quantities per Tape-and-Reel pack:
Device Quantity
Small Outline Transistor
Small Outline IC
Plastic Chip Carrier IC
SOT-23 (High Profile) (Note 2)
10000
SOT-23 (Low Profile) (Note 2)
10000
I
I
SO-8 (Narrow)
2500
SO-14 (Narrow)
2500
SO-14 (Wide)
1000
SO-16 (Narrow)
2500
SO-16 (Wide)
1000
SO-20 (Wide)
1000
SO-24 (Wide)
1000
PLCC-20
1000
PLCC-28
750
PLCC-44
500
PLCC-68
250
PLCC-84
250
2500'
3000'
'This denotes 7" reel quantity availability.
Note 1: For small outline transistors. your order will automatically be shipped in Tape-and·Aeel unless you indieste otherwise. For surface mount integrated Circuits,
your order will automatieslly be shipped in conductive rails unless you indieste "Tape-and·Aeel" after the device description on your purchase order.
Note 2: Your SOT-23 devices will automatically have Option 1 orientation unless you indieste "Option 2 Orientation" after the device deSCription on your purchase
order (see "Tape-and·Aeel Overview" for definition of SOT-23 orientations). In addition, your SOT-23 devices will automatically have the high-profile outline unless
you indieste "Low·Profile Oudine" after the device deSCription on your purchase order (see "Appendix II-Physical Dimensions of Surface Mount Package" for
definition of SOT-23 outlines).
Example: You order 5,000 LM324M ICs shipped in Tapeand-Reel.
• All 5,000 devices have the same date code
• You receive 2 SO-14 (Narrow) Tape-and-Reel packs,
each having 2500 LM324M ICs
6-19
Appendix I-Short-Form Procurement Specification
TAPE FORMAT
~
Direction of Feed
Trailer (Hub End)
Empty Cavities,
min
(Unsealed
Cover Tape)
Carrier
Empty Cavities,
min
(Sealed
Cover Tape)
Filled Cavities
(Sealed
Cover Tape)
Leader (Start End)
Empty Cavities,
min
Sealed
Cover Tape)
Empty Cavities,
min
(Unsealed
Cover Tape)
SMALL OUTLINE TRANSISTOR
80T-23
(High Profile)
2
2
10000
2500'
5
5
80T-23
(Low Profile)
2
2
10000
3000'
5
5
SMALL OUTLINE IC
80-8 (Narrow)
2
2
2500
5
5
80-14 (Narrow)
2
2
2500
5
5
80-14 (Wide)
2
2
1000
5
5
80-16 (Narrow)
2
2
2500
5
5
80-16 (Wide)
2
2
1000
5
5
80-20 (Wide)
2
2
1000
5
5
80-24 (Wide)
2
2
1000
5
5
PLASTIC CHIP CARRIER IC
PLCC-20
2
2
1000
5
5
PLCC-28
2
2
750
5
5
PLCC-44
2
2
500
5
5
PLCC-68
2
2
250
5
5
PLCC-84
2
2
250
5
5
·This denotes 7" reel quantity availability.
6-20
Appendix I-Short-Form Procurement Specification
TAPE DIMENSIONS (24 Millimeter Tape or Less)
~~T
-4-.
-lor-
~oflT
~ ~
0
["
-I
TAPETOLERANCE :0.2mm
E
0
@:
Bo
---L
___ Po 10 PITCH CUMULATIVE
~
P2-
8
0
~
-
(Continued)
+j>\~.~~
B;NDING RADIUS·(NDTE 2)
1
;--~Dl
AD
P
DEVICE ORIENTATION
A
r
~
~
OPTION 1
SOT·23
D
OPTION 2
SOl·23
PIN
1
SO·IC
'"
U
PCC·IC
TL/HH/8352-33
P
I W I
I
SMALL OUTLINE TRANSISTOR
F
I
E
I
P2
I
Po
I
D
I
T
I
AO
I
BO
I
KO
I
D1
IR
80T-23
8±.30 4.0±.10 3.S±.OS 1.7S±.10 2.0±.OS 4.0±.10 1.SS±.OS .30±.10 3.1S±.OS 2.SS±.OS 1.20±.OS 1.0S±.OS 2S
(High Profile)
80T-23
8±.30 4.0±.10 3.S±.OS 1.7S±.10 2.0±.OS 4.0±.10 1.SS±.OS .30±.10 3.1S±.OS 2.SS±.OS 1.20±.OS 1.0S±.OS 2S
(Low Profile)
SMALL OUTLINE IC
80-8
(Narrow)
12±.30 8.0±.10 S.S±.OS 1.7S±.10 2.0±.OS 4.0±.10 1.SS±.OS .SO±.10 6.4±.10 S.2±.10 2.1 ±.10 1.SS±.OS SO
80-14
(Narrow)
16±.30 8.0±.10 7.S±.10 1.7S±.10 2.0±.OS 4.0±.10 1.SS±.OS .30±.10 6.S±.10 9.0±.10 2.1 ±.10 1.SS±.OS 40
80-14 (Wide) 16±.30 12.0±.10 7.S±.10 1.7S±.10 2.0±.OS 4.0±.10 1.SS±.OS .SO±.10 10.9±.10 9.S±.10 3.0±.10 1.SS±.OS 40
SO-16
(Narrow)
16±.SO B.0±.10 7.S±.10 1.7S±.10 2.0±.OS 4.0±.10 1.SS±.OS .30±.10 6.S±.10 10.S±.10 2.1 ±.10 1.SS±.OS 40
SO-16 (Wide) 16±.30 12.0±.10 S.S±.10 1.7S±.10 2.0±.OS 4.0±.10 1.SS±.OS .SO±.10 10.9±.10 10.76±.10 3.0±.10 1.SS±.OS 40
80-20 (Wide) 24±.SO 12.0±.10 11.S±.10 1.7S±.10 2.0±.OS 4.0±.10 1.SS±.OS .30±.10 10.9±.10 1S.S±.10 3.0±.10 2.0S±.OS so
80-24 (Wide) 24±.SO 12.0±.10 11.S±.10 1.7S±.10 2.0±.OS 4.0±.10 1.SS±.OS .SO±.10 10.9±.10 1S.BS±.10 3.0±.10 2.0S±.OS so
PLASTIC CHIP CARRIER IC
PLCC-20
16±.SO 12.0±.10 7.S±.10 1.7S±.10 2.0±.OS 4.0±.10 1.SS±.OS .SO±.10 9.S±.10 9.3±.10 4.9±.10 1.SS±.OS 40
PLCC-2B
24±.SO 16.0±.10 11.S±.10 1.7S±.10 2.0±.OS 4.0±.10 1.SS±.OS .SO±.10 1S.0±.10 1S.0±.10 4.9±.10 2.0S±.OS SO
Bo and Ko dimensions are measured 0.3 mm above the inside wall of the cavity bottom.
Note 1: Ao.
Note 2: Tape with components shall pass around a mandril radius R without damage.
Note 3: Cavity tape material shall be PVC conductive (less than 105 Il/Sq).
Note 4: Cover tape material shall be polyester (30-65 grams peel·back force).
Note 5: 01 Dimension is centered within cavity.
Note 6: All dimensions are in millimeters.
6-21
~
~
,----------------------------------------------------------------------,
Appendix I-Short-Form Procurement Specification (Continued)
TAPE DIMENSIONS (32 Millimeter Tape or Greater)
-
;0
cJ 0
!
=;
roooot
E
~l
I
~~
/0
(I
.
1--1'2
0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0
°
BO
PolO PITCH CUMULATIVE
TAPE TOLERANCE ± 0.2 mm
-
1(- o~AO~
10
-
°
<
W
~~l
-.-
000001,0000000000 0
·~~ i·~
F2
oo)~
,
~
~~~LlEST POSSIBLE
v-
PlN/
v\·_~·m'
1
PCC-IC
TL/HH/8352-34
I
I
w
P
PLASTIC CHIP CARRIER IC
I
F2
I
E' I
P2
I
Po
I
D
IT
I
AD
I
80
I
Ko
I
D1
IR
PLCC-44 32±.3 24.0±.1 14.25±.1 1.75±.1 2.0±.05 4.0±.1 1.55±.05 .30±.1 18.0±.1 18.0±_1 5.0±.1 2.05±.05 50
PLCC·68 44.3±.3 32.0±.1 20.25±.1 1.75±.1 2.0±.05 4.0±.1 1.55±.05 .30±.1 25.6±.1 25.6±.1 5.0±.1 2.05±.05 50
PLCC-84 44.3±.3 36.0±.1 20.25±.1 1.75±.1 2.0±.05 4.0±.1 1.55±.05 .30±.1 30.7±.1 30.7±.1 5.0±.1 2.05±.05 50
Note 1: Ao. Bo and Ko dimensions are measured 0.3 mm above 1he Inside wall of the cavity bottom.
Note 2: Tape with componenls shell pass around a mandril radius R without damage.
Note 3: cavity tape material shall be PVC conductive (less than lOS O/Sq).
Note 4: Cover tape material shall be polyester (30-65 grams peel-back force).
Note 5: D1 Dimension Is centered within cevity.
Note 6: All dimensions are In millimeters.
6·22
Appendix .-Short-Form Procurement Specification
(Continued)
REEL DIMENSIONS
TMAX
-
/
"-
'-_/
"12 mm Tape
16mmTape
24mmTape
DI 'j~
(CO) \
A
8mmTape
H
.--8
c:::c:
~.~-.
M
TUHH/B352-35
A (Max)
B{Min)
C
o (Min)
N{Mln)
G
T{Max)
(13.00)
(330)
0.059
1.5
0.512 ± 0.002
13±0.05
0.795
20.2
1.969
50
0331+ 0.059
_'_-0.000
8.4~J·5
0.567
14.4
(13.00)
(330)
0.059
1.5
0.512±0.002
13±0.05
0.795
20.2
1.969
50
0.488~g·gbg
0.724
18.4
50-14 (Narrow)
50-14 (Wide)
50-16 (Narrow)
50-16 (Wide)
PlCC-20
(13.00)
(330)
0.059
1.5
0.512±0.002
13±0.05
0.795
20.2
1.969
50
0.646~g·gbg
50-20 (Wide)
50-24 (Wide)
PlCC-28
(13.00)
(330)
0.059
1.5
0.512±0.002
13±0.05
0.795
-20.2
1.969
50
0960+ 0.078
_'_-0.000
50T-23
(High Profile)
50T-23
(low Profile)
50-8 (Narrow)
12.4~g
16.4~g
24.4~g
0.882
22.4
1.197
30.4
32mmTape
PlCC-44
(13.00)
(330)
0.059
-1.5
0.512±0.002
13±0.05
0.795
-20.2
1.969
-50
1276+ 0.078
_'_-0.000
32.4~g
1.512
38.4
44 mm Tape
PlCC-68
PlCC-84
(13.00)
(330)
0.059
1.5
0.512±0.002
13±0.05
0.795
20.2
1.969
50
1.748~g·gbg
1.984
50.4
UnIts:
Inches
MillImeters
Material: Paperboard (Non-FlakIng)
6-23
44.4~g
~
t;
Appendix II-Physical Dimensions of Surface Mount Packages
SOT·23 (High Profile)
(Generally used lor Top-ol-Board Mounting)
1
H
0.110-0.120
(2.794-3.0481
';(~'=:~=8'; ;=;: : :=1 ~,
!-I
=-~
0.047 -0.055
(1.194 -1.3971
f
0.083-0.098
(2.108-2.4891
0.031-0.047
0.003-0.005
(0.07&-0.1271
10'
NOM
+
t
t
10'
NOM
(0.767 1.1941 10' ~t-!
NOM
If
-I~
1
f
0.018-0.022
(0.457 -0.5591
II
10'
NOM
0.004-0.010
(0.102-0.2541
.:b:Jlk. I
t
NOM
NOM
0.015-0.017
(0.381-0.4321
0.018-0.024
(0.457 -0.6101
N01E: NOT TO SCALE
M03A(REVC)
SOT·23 (Low Profile)
(Generally used lor Underside-ol-Board Mounting)
1
!--
0.110-0.120
(2.794-3.0481
I
n-
~(~:~~=~::111
~t________~
___ rn2rj1=~:~~~9-~~~:~=61
0.047 -0.055
(1.194-1.3971
t
f
3
0.083-0.098
(2.108 -2.489)
O.DOII5-O.DD4D
0.035-0.041
10' NOM
t
10' NOM
0.0034-11.0050
(0.0116-0.1271
T··
.
-,-rt .----_~U
t
j L)
!
10'NOM 0.01&.l1.D24
(0.457-0.6101
0.018-0.024
(0.457 -0.6101
10' NOM
W
I
(0.013-0.102)
w
-
j;: 10' NOM
f
0.015-0.017
(0.381-0.4321
NOTE: NOT TO SCALE
M03B (REV 0)
6-24
Appendix II-Physical Dimensions of Surface Mount Packages (Continued)
50-8 (Narrow)
0.189-0.191
(UDD-5.004) "'
8
7
6
5.1
O"2I~D""
i5.7ii'=iTaii
~ 0.010 MAX
/",,1 0.'54)
•
LEAD NO. 1
1
,
3'
IDENT
~x45,1Ir~:!:=:::1
10.'''-0.508)
l
r
0.Q53-0.0&9
11.346;1.753)
S' MAX TVP
~-t-T
3DD
TVP
~
-
f t-:;;:J-~L~-~II~-;'·
J:~~, I. T' :J:
10.203-0.2541
ALl lEAD TIPS _____
(~::~:I ~
0.016-0.0511
D.D14-0.D2D
('.270)
~':.L ~J
TVP ALL LEADS
TVP
(0.35'-0.508)
~TYP
TYP
.-
10.203)
t.IOM(FlEYH)
50-14 (Narrow)
0,335-0,344
--I~ 3 (350i7~ A ~I
1
0.2'S-0.2"1
(5.79',6.198)
0
30'
TVP
LEAO'~~N:n ~ ~ ~ ~ ~ ~~\
1
-
~X45'~
(0.254-0.508)
t
I~:~:~=~~~)
!--
'~I
r
Ir-___I
-r--I] I
0.008 -0.010
~
TIP ALL lEADS
0.D04
(0.102)
ALL lfADTIPS
2
3
4
5
6
7---,
.!!!!!MAX
10.'54)
0.053-0.069
('.346-'.753)
S' MAX TVP
ALL lfADS
+
0.004-0.010
SEATING
PLANE
**
f O.t
(0.356)
=:I0.050
1-(0.406-1.270)
TVP ALL LEADS
k~
s£hikl] ~
-----i
0.050
11.270)
TYP
J I JL II
-
-
-
0.014-0.020 TVP
(0.356-0.508)
(~:~:) TYP
MlolAjREV
6-25
.,~
~
~
,--------------------------------------------------------------------------,
Appendix II-Physical Dimensions of Surface Mount Packages (Continued)
If
SO-14 (Wide)
0.346-0.362
ii.7ii=9.ffii
~
14 13 12 11 10 9
8
0.394-0.419
'''Mr:~J'1_ ,.,.,
mr.
(0.&86)
(~:=::~::1)t_.!!:!!!!.
rr---,==--
*===~~~==~~~~9
I
0.093-0.104
x45'
(0.432)
8' MAX
t
T'/P
A~l~DS
t
~
0.037-0.044
t
0.030-0.050
~~
r-
~J
(0.940-1.118)1
-+- (0.762-1.270)
~
(0.102-0.305)
JL~T'/P
1
(1.270)
lYPALL~DS
SEATING
-----.-PLANE
(0.356-0.493)
lYP
M14B (REV Dj
S0-16 (Narrow)
30'
L~ONO.l
10ENT
~;:::::;;:::;:r=~~
.----,
~MAX
(0.254)
1
r
L
(::~:::::~)
~
~45'
(0.254 -0.508) x
1)-----/
0.OD8C
T'/P
(0.203-0.254)
lli Lms
-r-j
I
-+
0.004
(0.102)
0.004-0.010
(0.102 0.254)
(1.346-1.753)
8' MAX lYP
A~lEADS
L-J-
+
-
o.050J
(1.270)
(0.4118-1.270)
lYP A~ lEADS
lYP
ALLL~OTIPS
6-26
-
-
-
~
SEAlING
j Lo.mL.:;;p
(0.356-0.608)
008
(~:203) lYP
""'"••, ..
Appendix II-Physical Dimensions of Surface Mount Packages (Continued)
SO-16 (Wide)
~~-I
{lD.11-l0.50)
1&
15
14
13
12
11
10
9
1
0,394-0.419
~
!!r\
LEAD NO.1
IDENT---;j\...)~FFF~~FfF~~~ft~
&-,
~MAX
(0.254)
0.093-0.104
~
t
SEA11NG
PlANE
f
0.004-0.012
~.~
. -- - - ~
(~:!: )
-
II ~
..... (1.2TO)
TYP
JLJ L
0.014-0.020 TVP
('.356-0.508)
..!Q2!TYP
(0.203)
M16B(FIE'IEI
50-20 (Wide)
~~;::;:;::::;:;::~
1D---r
.!!1!MAX
10.254)
,
D.083 -0.104
(2.362-2.642)
L
8" MAX TYP
~ ~=O.=IJIM==:::;;~~~s
0.0II!I-0.013
ii.iH-i.iiii
1YP ALL
was
-
ALLI~:~IPS
I-+-(~::=~:~j~)
f I~':~)f
.
TVP ALL LEADS
~~
~ t
0.004-0.012
ILL JL
--....!!:!!.
11.2711)
TVP
-.
6-27
~TYP
10.203)
SEATING
t PlANE
~TYP
ID.35& -0.508)
M2CB(REvF)
~
Appendix II-Physical Dimensions of Surface Mount Packages (Continued)
SO-24 (Wide)
OO------1~55::=~56~)-------IO~
n 21 ~ 19 18 17 16 15 14 13
10
11
12
.!!!.!..=.Y!!..---.
17.3111-7.594)
0.037 - 0.044
10.940-1.116)
0.017
0.009-0.013
(0.229-0.330)
TYP ALL LEADS
(0.432)1
x45·
O.093-0.11M
(2.362-2.6421
fli5.Diiciriri:
fj L~
J1.!
+
L
-t·r::J..!:::::~r=~~
0.03D-0.D5D
10.7(;2-1.2711)
TVP ALL LEADS
0.DD4
iQ.iDzi
0.004-0.012
10.102 O.3D5)
11.270)
ALL LEAD TIPS
ir
PLCC-20
4 SPACES I(!
0.050
(1.270)
I
11.143)
D45
x45"
0.
0.D8D
16
i2.032i
:.:="'...........--1r--'- :E:~:L
tu~
150
4 SMCES AT
0.050
iI.Foi
0.310-0.330
1Wi=i.3iii
(CONTACT OIMENSIDII)
0.020
(0.508)
•.a-O.D11
(O.127~D.311)
~
Jl-:~;~~~!~~~~~
6·28
0.032-0.040
(0.613-1.016)
MIN
VIEW irA
i
0.01L.019
(0.356 -0.463)
TYP
Appendix II-Physical Dimensions of Surface Mount Packages (Continued)
.c"·'r
l .rn-
PLCC·28
0.0511
ll .21O )
15
0.130
I (::1
PEDESTAl
VlOW'"
~:;JJ
....
=r
lc~:~i,i~ON) Irl
I '1 M-_m_O_."_7)__I:_: ~_'~*~_.~_~_)L+
r=~
i=:, jl I:::~;::) fI:::=::~:)t
0.020
0.013-0.018
0.1115-0.01'
10.127-0.311)
....
0
(1f.43j
REFSII
8.485-0.485
112.32-12.57)
SQUARE
PLCC·44
I"
1.-0.050
11.210)
Rlf
~D.DZO
(0.813-1.018)
(O.5DS)
VoMA(IIEYHI
6-29
IX
~ Appendix II-Physical Dimensions of Surface Mount Packages (Continued)
PLCC-68
--
1. • - ... .
121·..-·...'1
..
...
'I
'"I·I----:O~I---. .·-t-l
PLCC-84
.!:l!!..;!JJ!.
(2.1142-2.1117)
Jj
"'. . . ':
...
'!1
J
..!J!!.
(29.21)
!J!i!!=.L!!!!.
...
(O.'7&2-1.1oU)
1YP
6-30
...
~''''I
L~':::::
.!:!!!.:!:!!!.
(4.111-4.171)
t...-.!J!!::!J!!!..!!!!.
f
(UI1-4.ml(U.ll1Z)
......
D.IM2-D.D4I-J
(1.CIIJT-1.11I)
""'
...
"'C
::T
~
~National
C:;'
~ Semiconductor
All dimensions are in inches (millimeters)
!!!.
C
3'
CD
::s
0'
::s
til
16 Lead Hermetic Dual-In-Line Package (D)
NS Package Number D16EQ
til
1 - - - - D.BDD±D.D1D - - - - l 9..~1
(2D.32±D.254)
\•
16
f
D.295±0.D1D
(1.493±D.254)
PIN NO.1
IDENT
JL
1
j
O.I35±D.D2D
(3.429±D.508) DIA
+
8
(::::) MAX TYP
I
•
0.185
(4.&99)
D.150~~:~~
(3.810 ~~:~:)
MAX
JL
II
0.300 ~~:~~~
D.D1B±D.DD3 TYP
-'11+- (D.457±D.D16)
+0.508)
( 1620
.
-0.254
(~::!::~:) TYP
"
I
0.215
(6.9B5) MAX
a~ +
I.
'"""-m
(D.254±D.D51)
"I
DI6EOLflEVAI
24 Lead Hermetic Sidebraze Dual-In-Line Package (D)
NS Package Number 0241<
I
1.195
I
:4
23
22
21
2D
1
2
3
4
6
::~~
11
16
15
14 13"
8
9
10
11
M·,,,1:: I~ ~ ~ ~ I~ ~ ]3~
6
1
12
_£1 I---+~~_1'524)L
'
0.020-0.1160
(0.229-0.305)
TYP
~~j '(3'115_5'OBD~
0.125-0.200
19.908-10.41)
~
(1.270±0.127)
0.016 -0.02D
10.405 -0.508)
TYP
TYP
D24KIAEVA)
6·31
II)
s:::
o
"w
s:::
Q)
28 Lead Ceramic Sidebraze Dual-In-Line Package (D)
NS Package Number D28F
E
is
1.415
(35.94)-------~
..
I
~
~
Il.
28
T ~~{
I
0.420
(10.67)
1
II- (9M~)
0.
0.008-0.015
(0.203-0.381)
385
1
~~
~-
I
I
0.4110 ±0.020
-4- (10.16±0.508)"
27
26
25
24
23
MA
22 :l
20
19
18
17
16
15
2
3
4
5
6
7
9
10
11
12
13
14
;;r~ ~ ~ ~ I ~ ~ ]],
8
0.040 ± 0.020
J#~
-,-
1_
0.125
(3.175)
MIN
0.019±0.004
(0.483±0.102)- TYP
0.050
(1.270) TYP
0.100±0.010
(2.5411±0.254)
028F(REVA)
28L Leadless Chip Carrier Type C (E)
NS Package Number E28A
0.404
r-
~(10.26)--J
sa ~I
~
0.065-0.076
(1.651-1.930)
D
BOTTOM
VIEW
TOP
VIEW
SlOE
VIEW
E2BA(AEVC)
6-32
r-----------------------------------------------------------------------------,~
::r
16 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J16A
~
~
c
3·
0.785--\
~(19.939)1
15
0.025
(0.635)
RAo
M
13 AX,2
14
1m Ii01 191
11
10
9
I
CD
:J
til
~
o·
:J
0.220-0.310
(5.588-7.874)
til
'-r.rT::T'"T":T-r:T"T~-r::T"T::T'I.~
.-=!.
GLASS
SEALANT
I"
0.290-0.320
O.IBO
95'±5'
I
~ ~~~~~~~~~~~~~.-~T--1,-~_+--~
0.008-0.012
(0.203-0.3:5:
I---
0.310 - 0.410
(7.874 -10.41)
0.200
(~~~)
0.005---j
~~J(7.366_8.128)
(~~x~2)
0.005 - 0.020
(0.127-0.508)
RAO TYP
80
J
(2.~~
80TH
ENOS
J16A(AEVKI
18 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J18A
~RAOMAX
0.915
1-------- (23.24) MAX
(0.508)
15
14
;;
131 [ffi
mJ
I
t
0.310
(7.874) MAX
~-::-r-r::-1r-r-:T'T~--,-;-r"T-::-r-r.:r"U
0.290-0.320
1(7.366-8.128)
r-
0.200
(5.0BO) MAX
0.020-0.060
(0.508-1.524)
0.125-0.200
(3.175 - 5.080)
0.055:0.005
(1.397:0.127)
r:~GLASSSEALANT
..!!:!!!Ltll
(~572)
AX
_
I
95' ±S:-0.310 - 0.410
(7.874-10.41)
L
0.008-0.012
(0.203-0.305)
86'94'
TYP
L
0.loo±0.010
(2.540±O.254)
0.OI8±0.003 TYP
(O.457±0.076)
JP
Lj
0.098
(2.489)
MAX
80TH ENDS
J18A(REVL.1
6-33
o ,-----------------------------------------------------------------------------,
C
o
";;
c
CD
E
20 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J20A
i5
0.985
1+"-----(25.019) -----~
i
MAX
ia.
0.005-0.020
10.127 -0.508)
nAOTVP
D.188
(4.572)
GLASS SEALANT
MAX
0.200
15.080)
MAX
0.150
(3.810)
MIN
0.008-0.012
10.203-0.305)
I.-17.874-10.41)
0.310-0.410
t
1L
0.125-0.200
(3.175-5.088)
t
0.018±0.003 __
(0.457±0.076)11
J20AtAEYM)
22 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J22A
I
1.110
1+------128
. 1 9 ) - - - - - - - l..~
MAX
0.025
(0.635)
0.400
110.16)
nAD
0.030-0.055
iiffiz::;:m)
~r.r~~rr.~r.r~rr.~7r~~rrr~~
MOTYP
0.390-0.420
rI9.906
95' ±5'
0.037 ±0.005
10.940 ±0.127)
0.225
(5.715)
GLASS
10.668)"~NT
Ie
:II
0.4B5±0.06D
~L
=t_/,i=O
.!!:!!!!.MAX
14.572)
\T
I
I
II
(12.319±1.270)--l
86' 94'
0.420 MAX
12 ;ill0'668) GLASS
r.l1- ~ ~
MAX BOTH 0.100
. ENDS (2.540)
0.loo±0.010
12.540 ±0.254)
TVP
0.020-0.070
II
rll- 13~~5)
0.125
O.OIB±O.OO3
10.457±0.076)
J22AIREVG)
6-34
24 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J24A
1.290
1-·0--------(32.766) - - - - - - - "
MAX
1
0.025
(0.635)
RAD
I
0.600
(15.240)
fMAX
iGLASS
0.514-0.526
: T"1I" :T. ,. ,. r-T:,. . .-=r., . ,. ,. ,. ,. . ., ". ,. ., . ,. ,. ~ ' ' or''
1"-T':"T..,.".......
0.030-ll.055
(0.762-1.397)
RADlVP
~
0.590-0.620 ~
0.005
~"ir ~ .~J
... :. "'''~~, J
95" l5"
f---
,
0.008-0.012
~::~:).--j
(2~~~~~
(0,685
17.40 -1.524
1-- 0.100'0.010 I
MAX
0,125-l1.200
(3.175-5.080)
MIN
(2.540 '0.254)-l
0.150
(3.Bl01
MIN
J24A1AEVHJ
24 Lead EPROM Ceramic Dual-In-Line Package (JQ) (Small Window)
NS Package Number J24AQ
1.290
·~I·o--------(~~'------------~~
0.025
(0.635)
BAD
0.180
(4.572)
Mi
0,030-0.055
(0.762-1.397)
BAD TYP
I-
0.590-0.620
-I
n -=
I_
95'±5'
r-----
0.514-0.526
(13.06-13.36)
~~~_l
0.005
L--t~~(14'i-r74B):::::L~1
(OM~~7)
I
0.OOB-D.015J
~:::
0.681
1740+0.635)
• -1.524
(0.203-0.381)
_
I
~
0.060-0.100
(1.524-2.540)
TYP
0,56Q
(14.22)
MAX GLASS
I--
I
0,100±0.010
(2,54D±0.254) - l
6-35
24 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J24F
1.210
lIZ5
(0.135' HAD
1-------(21."1 M A X - - - - - - - - I
0.030-0.056
r
I
~-~~~~~~I~(:~:)t:\
10.7&2-1.397'
0.060 1G.005
iI.52i±iii7i TYP
(~:~::~~~:)
0.021-0.070 RAD TYP
(0.608-1.771)
't.
I
MAX
l1----I-f-
~I
8.125
(3.175)
MIN
(2.54 fII.254,-l
TYP
95'''-'
I
I
I--~-l
~
(0.203-0.305)
TYP
(7.874-10A1I
JZ4FiREYGI
28 Lead EPROM Ceramic Dual-In-Line Package (JQ) (Small Window)
NS Package Number J28AQ
GLASS
SEALANT\
-
0590 0620
(14.99-15.75)-
II
IL
!.-!- 95' ± 5"
0.180
14.572)
JI
~I
Jt- 'h
+0.025
0.685 -0060
('7.40
0.009-0.012
(0.203-0.305)
+
0.635)
-1.524
.
I·
\~
~
D.225j
t·
11
15M~) ~
(3.175)
MIN
0.060-0.100 _
(1.524-2.540)
TVP
_
_
11- -
0.100+0.010 _
-(2.54D±0.254,
TVP
6·36
0.020-0.070
(0.508 -1.778)
0.055±0.0='94'TYP
(1.397±0.127)
TVP
+- 0.D18±0.0D3
(0.457±0.076)
J2BA.Q (REV B)
32 Lead EPROM Ceramic Dual-In-Line Package (JQ)
NS Package Number J32AQ
(!26::)---------~
MAX
~~~~~~~~~~~~~~~~~~~~1~7~
0.025
ri
W -
(0.889)
I
(0.635)~
RAD
~
0.585
(14.86)
MAX
~~1
(O.762-1.397J
.!:.!!!
(~F)
RAD TY.
I-
~-
~ .....
0.010
(1.397±0.127)
(0.254) 0.225
MAX (5.715)
MAX 0.015-0.060
0.590-0.620
(14.99 -15.75)
td',ar'
86'
--94'
II
1.-./
0.018±0.003
(0.457±0.076)-I1-
0.125
(3.175)
r
MIN
J32AQ(REve.
40 Lead EPROM Ceramic Dual-In-Line Package (JQ)
NS Package Number J40AQ
_ _ _ _ _ _ _ _ _ _ _ _ 1:;0:: _ _ _ _ _ _ _ _ _ _ _--1
1
MAX
0.025
--RAD
(0.635)
0.030-0.055
(0.162-1.391)
RAD TYP
0.018±0.003
II
(O.457±O.D76)II
TV.
I I
0.100± 0.010
12.540 ± O,2541----j
TV'
6-37
r-
I
--j
0.08a
12.489)
MAX (80TH ENOS)
•
o
C
o
"in
c
CP
E
r---------------------------------------------------------------------------------,
8 Lead (0.150" Wide) Molded Small Outline Package (M)
NS Package Number M08A
is
0.IB9-0.197
(4.Boo-5.004)
~
~
a.
B
r
1 1~:~~~=~:!:!)
0.010-0.0ZO x45'_
(0.254-0.50B).
.
r.
(0.102)
ALL LEAD TIPS
_
6
0.053-0.069
(1.346-1.753)
B' MAX TYP
t = .~I I. T
0.008-0.010
(0.203-0.254)
TYPALL LEADS
7
0.1104-0.010
(0.102 0.254)
+
f o.t
10.356}
0.016-0.050
(0.406-1.2TD)
..!!:!!!!!!..
J j
(1.270)
TYP
TYPAULEADS
~
.!!:!!!!!TYP
t
_
10.203)
SEATING
PLANE
0.014-0.020 TYP
(0.356-0.5Il8)
.",",REY H)
14 Lead (0.150" Wide) Molded Small Outline Package (M)
NS Package Number M14A
30'
:;::::;:;:::;:;;:::;:;:::;:;::~
3
4
7-,
.!.!!!!MAX
10.254}
0.053 -0.069
(1.346 1.753)
0.010-0.020 x45'
(0.264 -0.5118)
t
B'MAXTYP
I-±~
I.-
SEATING
PLANE
0.1104-0.010
+
t f
0.014
iD.35ei
(0.406-1.270)
TYP ALL LEADS
ttL~
~J
(1.2TD)
TYP
(0.102 0.254)
~-=i
I-JL _I L
0.014-0.0;0 TYP
(0.356 0.50B)
O.OOB TYP
(0.203)
M14A(fIEVI11
6-38
r-----------------------------------------------------------------------------,
14 Lead (0.300" Wide) Molded Small Outline Package (M)
NS Package Number M 148
~
~
~
c
3"
CD
~
rn
0"
~
rn
4
·
r (~:~::-~:::):t
1
r---.==-I
~
LJ,
3:,---===4=
0.017 x4S o
(0.432)
0.009-0.013
(0.229-0.330)
BO MAXlYP
lYP Alll£ADS
All lEADS
r
~J
(0.102)
All lEAD
6
7
0.093-0.104
(2.362-2.642)
t
t
t
'F????
j
0.004-0.012
(0.102 0.305)
1 L JLO--.tt
ilJjJjJjJjJOjJJ
0.037-0.044
(0.940-1.11B)
I
S
T
~
0.030-0.050
- - (0.762 1.270)
TYP All lEADS
SEATING
PLANE
~lYP
(1.270)
TYP
(0.356-0.483)
TIPS
M14,BtREVD)
8 Lead Molded Dual-In-Line Package (N)
NS Package Number N08E
~DIA
0.032±0.00S
(0.B13 ±0.127)
RAO
(2.337)
PIN NO. llDENT
~7
PlNNO.lI0ENT~
1
OPTION 2
O.OlB ±0.OO3
(D.457±D.D76)
(~::!::~~:)
0.D45±0.015
(1.143±0.3Bl)
~I--
D.D6D
iiTzi)
NOBE(REVFI
6-39
o
C
.~
5i
r---------------------------------------------------------------------------------,
14 Lead Molded Dual-In-Line Package (N)
NS Package Number N 14A
E
is
B
i
a..
0.092
0.030 MAX
(2.337) DlA 10.762) OEP'TH
OP'TION 1
OPTION 02
0.135±0.005
13.429 to.127)
0.300-0.320
40 TYP
OPTIONAL
+
0.020
10~~S) 0.125~0.150
13.175-3.810)
f
~
--'1 --
90o ±4° TYP
-II
I
0.014-0.023 TYP- . . 10.356 -0.584)
--
~
~::!so ~~I
otS-0.016 TYP
10.203-0.406)
I
0.075tO.015
11.905±0.381)
I
__ 0.100±0.010 TYP
12.540 t 0.254)
0.05D±0.010 TYP
11.270 -0.254)
...
_
_
h~~)
1
0.2S0
_17.112)_
MIN
.
0.325 ~~:~~
(8255 +1.016)
.
-0.381
Nl~"
16 Lead Molded Dual-In-Line Package (N)
NS Package Number N16A
0.092
(2.337)
DIANDM
12X)
(~:~~:) ~
MIN
0.300-0.320
0.030
10.762)
MAX
(7 .620-8.128)
~
0.065
. . r~"-~". IJ J
-'l--(O.229-0.3811
I·
0.325
(
~~:~~~
·1
+1016)
8.255 -0:381
0.075 ±0.015
(1.905 ±0.3811
I
r-
0.100 ±0.010
(2.540 ±0.254)
N16A(REVEI
6·40
[REV Fl
"a
~
16 Lead Molded Dual-In-Line Package (N)
NS Package Number N16E
1:
5
AREA
INDEX
,
PIN NO. 1 ".,.t~i'!!'i'''i'!'~i'i'''f,",,'i'!l''i'''i'!''i''i'l'fIJ
IDENT
0.145 - 0.200
(3.683 - 5.080)
0.010 MIJ
r=
0"25-0'15~L
(0.508)
~
c
PIN NO.1
IDENT
3'
CD
:s
CII
0'
:s
",
';
CII
-'- "-'- '
1 2
OPTION 02
I-- (0.762:1:0.381)
0.030:1:0.015
,
I- 0.100:1:0.010
(3.175-3.810)
0.014 - 0.023
(0.356 - 0.584)
TYP
(2.540:1: 0.254)
TYP
18 Lead Molded Dual-In-Line Package (N)
NS Package Number N 18A
0.843-0.870
121A1-22.10)
~
X 0.030
(2.336)
10.762)
NOM
MAX
DEEP (2 PLCS)
1&
"
13
Ht6E (REV F)
-:j
12
"
0
f
0.260 ±0.D06
16.350 ±0.127)
~
iffi::T.r;:::;:::;"T.T'~~"T.T';;;rI-1
0'280~
17.112)
MIN
Ir: I
0.300-0.320
o
-::.:
j£J\
I•
+0.040
0.325 -0.015
·1
'U55 +1.016)
~
-8.381
1I-- J
0.025.0.015
10.635 '0.381)
0.100 '0.Gl0
12,540 >0.254)
TVP
-9o;:lf
~
(0.508)
0.126-0.140 I MIN
13.175-3.556)
N18A(REVE)
6-41
20 Lead Molded Dual-In-Line Package (N)
NS Package Number N20A
1.013-1.040
(25.73-26.42)
0.092 X0.030
(2.337 X 0.762)
=:1
0.032±O.o05
(0'813±0'127)~D
1.
HAD
'F====~~='=7==16~1=6~14~=13~1~2~11~---r
MAXDP
0.260 to.005
(6.604 .0.127)
PIN NO. IIDENT
PIN NO.IIDENT~
~rrrrmm~~~rnm~~
1
DPTION2
0.065
(1.651)
~~~++~~~~~~rl
0.325
~:~~~
0.009-0.0IJJ
(0.229-0.381)
TVP
0.06UtO.005
(1.524.0.127)
-90°> 0.004°'
I 0.100>0.010 I
I- (2.540<0.254)-j
I
I--
0.018>0.003
(0.457 >0.076)
~ I_
0.125-0.140
(3.175-3.556)
(0.508)
MIN
(8.255 +1.D16
~
-UBI
N20ACREVGl
22 Lead Molded Dual-In-Line Package (N)
NS Package Number N22A
1.093-1.120
(27.76-28.45)
19
1
0.062
HAD (1.575)
PIN NO.1
IOENT
18
17
:-:-:j
16
15
14
13
12
f
0.350 to.005
(8.890 to.127)
I::;:;:;=;::;;;;:::;::;;;::=;::;::::;;:;::;:=::r=;::::;=;;::::;::::;::;;:;:;:;;;:::;:;:~
OAOO-OA20
(10.160-10.668)
_
0.380
(9.652)
MIN
(1.270 to.381)
(2.540 to.254)
(OA57 to.076)
N22A{REYO)
6-42
r-----------------------------------------------------------------------------,
24 Lead Molded Dual-In-Line Package (N)
NS Package Number N24A
~
(i'
e!.
I
c
3'
1.Z43-1.270
1-------(31.57_32.26)------o·~
13
0.062
11.575)
RAD
CB
CB
PIN NO. I IDENT
CD
:J
til
il
0'
:J
til
I 0.540 ±0.005
J.."
,AO=F.i=r.:;=;::;;;=;:;:;:=;:;:;:=;;:T"ffl=;=::;==;;:T"iffi'''i'ffii''T.!;r=!I!
1
2
DOTTED OUTLINES
REFLECT ALTERNATE
~:l
MOLDED BODY CONFIGURATION
114.73)
0.030
MIN
-(0.-76-2)
0.075
0.600-0.620
MAX
11.905)
~
0.160 '0.005
Lc:r---+f-----....:..:.:......+t---n--j-------1
1);=115.24-15.748)
~
TYP
95 D ±5 D
1_
~:~~~.
_I
r--(15875 +O.635)~
. -11.381
0.625
~
f t
0.015
0.018.0.003
(0.381)
;-l f-- -(0.457
- .- - 0.125-0.140
_0.078) ~ MIN
0.100 '0.010
(2.540 ±0254)
.
N24AIREVE)
24 Lead Skinny Dual-In-Line Package (0.300" Centers Molded) (N)
NS Package Number N24C
1.243-1.270
(31.57-32.26)
0.092
(2.337)
(2 PLS)
MAX
t
PIN NO.1
10ENT
0.260±0.OO5
(6.604±0.127)
I
OPTION 2
0.300-0.320
C:'"'I
0.009-0.016
(0.229-0.381)
+0040
0.325 -0:015
95"±5"
0.280
(7.112)
MIN
-+----"=---/
(8255 +1.016)
~
.
"'J
0.062
(1.575)
RAD
0.065
(1.651)
0.075±0.015
(1.905±0.381)
I
I--
-0.381
N24CIREV F)
6-43
~
~
o ,-----------------------------------------------------------------------------,
a
"iE
28 Lead Molded Dual-In-Line Package (N)
NS Package Number N28B
is
If.
PIN NO. IIDENT
1.393-1.420
~------(35.38-36.07)-------.j
0.125 -0.145
(3.175-3.683)
N28B(REVE)
20 Lead Plastic Chip Carrier (V)
NS Package Number V20A
(1.143)
0.04if5
x45'
I
18
0.D6D
(2.032)
~_+-r'-_+----'L ~~E~~:L
~~
4 SPACES AT
0.050
(1.270)
4---+1,-
~
15'
VIEW A·A
0.226
i5.74oi
NOM
SOUARE
0.310 -0.330
(7.874-8.382)
(CONTACT DIMENSION)
t
0.005-0.011
(0.127-0.311)
T
0.026-0.032
(0.660-0.813)
TYP
,
0.104 I 0.118
(2.642 - 2.997)
PIN NO.l/
10ENT
_.0.013-0. 018
----45-7)
(0.330-0.
TYP
0.020
rT .t
trI-
:..-- 0.3~•• _
i8.ii0')
(0.508)
MIN
0.032-0.040
(0.813 1.016)
,-,0.165-0.180
(4.19
~
REFSQ
0.385-0.395
(9.779 10.03)
-
SQUARE
V2DA (REV J)
6·44
."
:::r
28 Lead Plastic Chip Carrier (V)
NS Package Number V28A
r
l rrr
8SFACESAT
0.050
l1.2111)
15
~
~
ii.5aii
MIN
~,
1
!!!.
C
3'
0.130
CD
::s
iffij
PED":s~AL
!e.
OIA
o
::s
UJ
l ICO:::~~:ON)"' r-
0.020
0.032-0.040
10.BI3-1.018)
1.
n
r-Fr=
T 0.ODS-0.015 T
iD.iiH.iiii
I
0.013-0.01.
110.330-U57)
TYP
0.185-0.180
14.191-4.672)
* t
I ~=~c::=ti~i======;:--f
"
f
--" "'>:-:--I::::::::::~)
TYP
t~
12.542 - 2.997)
V28AIRIiYO)
24 Lead Cerpac, Fine Pitch Package (W)
NS Package Number W24D
I~:=~=:::)
0.037_0.041
(0.9.. -1.194,--'
1
r(::::~=:::~~
10.737-0.7871
~TYPt1
r-
_1-'·005
-
10.1271 MINTYP
ln31 __~.-_ _. .
"
O.191i!O.215
l'
"r
0.532 -0.544
SEEOETAlLA-"!'rirTTTTTTTTTmrrTTT1rm'
I
l'
I
0.004-0.00'
II
(0.'0'-0.'52,---11---
J"
0...15-0.01D5.L (0.1905-0.26871 1- II
~O,328-D.332
18.331-8.4331
6·45
(:4~~:) MAX
(:::, MAX
L·
~J~
DElAlLA
LW110ENT
rn
c
o
c
'iii
CP
28 Lead Cerpac, Fine Pitch Package (W)
NS Package Number W28B
E
is
1j
~
I::::) MAX
. M2<···1II
(1.116"'.127)
O.03D±O.DOl
IO.762±D.D25)
NOTES: UNLESS OllIERWISE SPf:ClRED
NOTE 1. LEAD FltlSH: SOLDER IIIPfIBI WITH SnBO OR Sn13 SOLDER CONRJRM1H8 TO r.lL·M-3151D TO A M!MIMUM THICKNESS OF 200
MlCaCHES (5.G1 MICBOMETERI. SOLDER MAY BE APPUED
a..
OVER LEAD IASIS Ell OR 8n PLATE.
NDTE 2. LEAD THICKNESS MAY IE INCREASED BY D.G03INCHES (D.oamml·
MAXIMUM AFJE1IlEAD RIIISH IS APPlIEO,
NOTE 3. LEAD lI1JENT1F1CA11DN SHALL BE:
I) ANOTCH IHIi OTHER IDmIFICA11DN MARK
Wl11tIN 11115 AREA. tlB
bl "TU ON lEAD 1, EmlER SIIIE.
~l
SEEllElNl.~~.........
(NOlE')
...">o.,,,jlI--
(1.121>0.025)
:::::.Jl-
0.0075-0.0105
(D.19D5-D.2&Sn
(NOTE!)
OETAILA
(""£3)
WKBtREYA!
64 Lead Cerquad Flatpak (W)
NS Package Number W64A
D.0II±o.al0 DIA
tl.I24±O.2S4)
sa
6-46
NOTES
~National
D Semiconductor
Bookshelf of Technical Support Information
National Semiconductor Corporation recognizes the need to keep you informed about the availability of current technical
literature.
This bookshelf is a compilation of books that are currently available. The listing that follows shows the publication year and
section contents for each book.
Please contact your local National sales office for possible complimentary copies. A listing of sales offices follows this
bookshelf.
We are interested in your comments on our technical literature and your suggestions for improvement.
Please send them to:
Technical Communications Dept. M/S 16-300
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090
ALS/AS LOGIC DATABOOK-1987
Introduction to Bipolar Logic. Advanced Low Power Schottky • Advanced Schottky
ASIC DESIGN MANUAL/GATE ARRAYS & STANDARD CELLS-1987
SSI/MSI Functions. Peripheral Functions. LSIIVLSI Functions. Design Guidelines • Packaging
CMOS LOGIC DATABOOK-1988
CMOS AC Switching Test Circuits and Timing Waveforms. CMOS Application Notes. MM54HC/MM74HC
MM54HCT/MM74HCT. CD4XXX. MM54CXXX/MM74CXXX. Surface Mount
DATA ACQUISITION LINEAR DEVICES-1989
Active Filters. Analog Switches/Multiplexers. Analog-to-Digital Converters. Digital-to-Analog Converters
Sample and Hold • Temperature Sensors. Voltage Regulators. Surface Mount
DATA COMMUNICATION/LAN/UART DATABOOK-1990
LAN IEEE 802.3 • High Speed Serial/IBM Data Communications. ISDN Components • UARTs
Modems. Transmission Line Drivers/Receivers
DISCRETE SEMICONDUCTOR PRODUCTS DATABOOK-1989
Selection Guide and Cross Reference Guides. Diodes • Bipolar NPN Transistors
Bipolar PNP Transistors. JFET Transistors. Surface Mount Products. Pro-Electron Series
Consumer Series. Power Components. Transistor Datasheets • Process Characteristics
DRAM MANAGEMENT HANDBOOK-1989
Dynamic Memory Control. Error Detection and Correction. Microprocessor Applications for the
DP8408A109A117 /18/19/28/29. Microprocessor Applications for the DP8420Al21A122A
Microprocessor Applications for the NS32CG821
EMBEDDED SYSTEM PROCESSOR DATABOOK-1989
Embedded System Processor Overview. Central Processing Units • Slave Processors • Peripherals
Development Systems and Software Tools
F100K DATABOOK-1989
Family Overview. FlOOK Datasheets • 11 C Datasheets • 10K and lOOK Memory Datasheets
Design Guide. Circuit Basics. Logic Design. Transmission Line Concepts. System Considerations
Power Distribution and Thermal Considerations. Testing Techniques. Quality Assurance and Reliability
FACTTM ADVANCED CMOS LOGIC DATABOOK-1989
Description and Family Characteristics. Ratings, Specifications and Waveforms
Design Considerations. 54ACI74ACXXX. 54ACT174ACTXXX
FAST® ADVANCED SCHOTTKY TTL LOGIC DATABOOK-Rev. 1-1988
Circuit Characteristics. Ratings, Specifications and Waveforms. Design Considerations. 54F /7 4FXXX
FAST® APPLICATIONS HANDBOOK-REPRINT
Reprint of 1987 Fairchild FAST Applications Handbook
Contains application information on the FAST family: Introduction. Multiplexers. Decoders. Encoders
Operators. FIFOs. Counters. TTL Small Scale Integration. Line Driving and System Design
FAST Characteristics and Testing • Packaging Characteristics. Index
GENERAL PURPOSE LINEAR DEVICES DATABOOK-1989
Continuous Voltage Regulators. Switching Voltage Regulators. Operational Amplifiers. Buffers. Voltage Comparators
Instrumentation Amplifiers • Surface Mount
GRAPHICS HANDBOOK-1989
Advanced Graphics Chipset. DP8500 Development Tools. Application Notes
INTERFACE DATABOOK-1988
Transmission Line Drivers/Receivers. Bus Transceivers. Peripheral Power Drivers • Display Drivers
Memory Support. Microprocessor Support. Level Translators and Buffers. Frequency Synthesis • Hi-Rei Interface
LINEAR APPLICATIONS HANDBOOK-1986
The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear integrated circuit
applications using both monolithic and hybrid circuits from National Semiconductor.
Individual application notes are normally written to explain the operation and use of one particular device or to detail various
methods of accomplishing a given function. The organization of this handbook takes advantage of this innate coherence by
keeping each application note intact, arranging them in numerical order, and providing a detailed Subject Index.
LS/S/TTL DATABOOK-1989
Contains former Fairchild Products
Introduction to Bipolar Logic. Low Power Schottky. Schottky. TTL. TTL-Low Power
MASS STORAGE HANDBOOK-1989
Rigid Disk Pulse Detectors. Rigid Disk Data Separators/Synchronizers and ENDECs
Rigid Disk Data Controller. SCSI Bus Interface Circuits. Floppy Disk Controllers. Disk Drive Interface Circuits
Rigid Disk Preamplifiers and Servo Control Circuits. Rigid Disk Microcontroller Circuits. Disk Interface Design Guide
MEMORY DATABOOK-1990
PROMs, EPROMs, EEPROMs • TTL I/O SRAMs • ECL I/O SRAMs
MICROCONTROLLER DATABOOK-1989
COP400 Family. COP800 Family. COPS Applications. HPC Family. HPC Applications
MICROWIRE and MICROWIRE/PLUS Peripherals. Microcontroller Development Tools
MICROPROCESSOR DATABOOK-1989
Series 32000 Overview. Central Processing Units. Slave Processors. Peripherals
Development Systems and Software Tools • Application Notes • NSC800 Family
PROGRAMMABLE LOGIC DATABOOK & DESIGN MANUAL-1989
Product Line Overview. Datasheets. Designing with PLDs • PLD Design Methodology. PLD Design Development Tools
Fabrication of Programmable Logic. Application Examples
REAL TIME CLOCK HANDBOOK-1989
Real Time Clocks and Timer Clock Peripherals • Application Notes
RELIABILITY HANDBOOK-1986
Reliability and the Die • Internal Construction. Finished Package. MIL-STD-883. MIL-M-38510
The Specification Development Process. Reliability and the Hybrid Device • VLSIIVHSIC Devices
Radiation Environment. Electrostatic Discharge. Discrete Device. Standardization
Quality Assurance and Reliability Engineering. Reliability and Documentation. Commercial Grade Device
European Reliability Programs. Reliability and the Cost of Semiconductor Ownership
Reliability Testing at National Semiconductor. The Total Militaryl Aerospace Standardization Program
883B/RETSTM Products. MILS/RETSTM Products. 883/RETSTM Hybrids. MIL-M-38510 Class B Products
Radiation Hardened Technology. Wafer Fabrication. Semiconductor Assembly and Packaging
Semiconductor Packages. Glossary of Terms • Key Government Agencies • ANI Numbers and Acronyms
Bibliography. MIL-M-3851 0 and DESC Drawing Cross Listing
SPECIAL PURPOSE LINEAR DEVICES DATABOOK-1989
Audio Circuits. Radio Circuits. Video Circuits. Motion Control Circuits. Special Function Circuits
Surface Mount
TELECOMMUNICATIONS-1987
Line Card Components. Integrated Services Digital Network Components. Modems
Analog Telephone Components. Application Notes
~ National
D
Semiconductor
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2017:06:23 09:00:04-08:00 Modify Date : 2017:06:23 09:22:13-07:00 Metadata Date : 2017:06:23 09:22:13-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:0a9dee8b-7059-4444-9092-88ea5f2db812 Instance ID : uuid:e6b1009b-8c6d-5343-9a58-334a328b0e90 Page Layout : SinglePage Page Mode : UseNone Page Count : 610EXIF Metadata provided by EXIF.tools