1990_Microchip_Data_Book 1990 Microchip Data Book

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MICROCHIP
DATA\ BOOK

Microchip

Microchip Data Book
Second Edition

For Military devices, please refer to the "MILITARY DATA BOOK"
© 1990 Microchip Technology Inc.

DS00018C

Microchip

"Information contained in this publication regarding device applications
and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no
liability is assumed by Microchip Technology Inc. with respect to the
accuracy or use of such information, or infringement of patents arising
from such use or otherwise. Use of Microchip's products as critical
components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any int{lilectual property rights."

DS00018C

DEC, VAX, VMS, and ULTRIX are trademarks of Digital Equipment
Corp.
MACINTOSH is a trademark of Apple Computer, Inc.
IBM and IBM PC are trademarks of IBM Corp.
SMC is a trademark of Standard Microsystems Corp.
PICPAK, PIC-ICE, PICPRO, PICALC, and PICSIM are trademarks of
Microchip Technology Inc.
PIC is· a registered trademark of Microchip Technology Inc.
The Microchip logo and name is a registered trademark of Microchip
Technology Incorporated.
All rights reserved. Copyright © 1990, Microchip Technology Inc.

Table of Contents

Microchip

SECTION 1

SERIAL EEPROM PRODUCT SPECIFICATIONS
24C01A
24C01 A Dice
24C02A
24C02A Dice
24C04A
24C04A Dice
59C11
59C11 Dice
85C72
85C72 Dice
85C82
85C82 Dice
85C92
85C92 Dice
93C06
93C06 Dice
93C46
93C46 Dice
24CXX/85CXX
ER59256/93C06
24C01A

SECTION 2

EEPROM PRODUCT SPECIFICATIONS
28C04A
28C16A
28C17A
28C17A Dice
28C64A
28C64A Dice

SECTION 3

1K (128 x 8) CMOS Serial Electrically Erasable PROM ........................................... 1- 1
1K (128 x 8) CMOS Serial Electrically Erasable PROM Die Form ........................... 1- 9
2K (256 X 8) CMOS Serial Electrically Erasable PROM ........................................... 1- 17
2K (256 X 8) CMOS Serial Electrically Erasable PROM Die Form ........................... 1- 25
4K (512 x 8) CMOS Serial Electrically Erasable PROM ........................................... 1- 33
4K (512 x 8) CMOS Serial Electrically Erasable PROM Die Form ........................... 1- 41
1K (128 x 8 or 64 x 16) CMOS Serial Electrically Erasable PROM .......................... 1- 49
1K (128 x 8 or 64 x 16) CMOS Serial Electrically Erasable PROM Die Form .......... 1- 57
1K (128 x 8) CMOS Serial Electrically Erasable PROM ........................................... 1- 65
1K (128 x 8) CMOS Serial Electrically Erasable PROM Die Form ........................... 1- 73
2K (256 x 8) CMOS Serial Electrically Erasable PROM ........................................... 1- 81
2K (256 x 8) CMOS Serial Electrically Erasable PROM Die Form ........................... 1- 89
4K (512 x 8) CMOS Serial Electrically Erasable PROM ........................................... 1- 97
4K (512 x 8) CMOS Serial Electrically Erasable PROM Die Form ........................... 1-105
256 Bits (16 x 16) CMOS Serial Electrically Erasable PROM ................................... 1-113
256 Bits (16 x 16) CMOS Serial Electrically Erasable PROM Die Form ................... 1-121
1K (64 x 16) CMOS Serial Electrically Erasable PROM ........................................... 1-129
1K (64 x 16) CMOS Serial Electrically Erasable PROM Die Form ........................... 1-137
24CXX/85CXX To Microcontroller Communication .................................................. 1-145
ER59256/93C06 And NMC9306/NMC93C06 Compatibility Issue ............................ 1-155
24C01A Compatibility Issue And Its Mobility For Memory Upgrade ......................... 1-159

4K (512 x 8) CMOS Electrically Erasable PROM
16K (2K x 8) CMOS Electrically Erasable PROM
16K (2K x 8) CMOS Electrically Erasable PROM
16K (2K x 8) CMOS Electrically Erasable PROM
64K (8K x 8) CMOS Electrically Erasable PROM
64K (8K x 8) CMOS Electrically Erasable PROM

..................................................... 2..................................................... 2..................................................... 2Die Form ..................................... 2..................................................... 2Die Form ..................................... 2-

1
9
17
25
33
41

64K (8K x 8) CMOS UV Erasable PROM ................................................................. 3128K (16K x 8) CMOS UV Erasable PROM ............................................................. 3256K (32K x 8) CMOS UV Erasable PROM ............................................................. 3512K (64K x 8) CMOS UV Erasable PROM ............................................................. 364K (8K x 8) High Speed CMOS UV Erasable PROM ............................................. 3256K (32K x 8) High Speed CMOS UV Erasable PROM ... ,..................................... 3256K (16K x 16) High Speed CMOS UV Erasable PROM ....................................... 364K (8K x 8) High Speed CMOS UV Erasable PROM ............................................. 327Cxxx EPROM Family Programming Algorithm ..................................................... 3-

9
17
25
33
41
49
57
65

EPROM PRODUCT SPECIFICATIONS
27C64
27C128
27C256
27C512
27HC64
27HC256
27HC1616
27HC641
27Cxxx

DS00018C

iii

Microchip

DS00018C

Table of Contents

Microchip

SECTION 4

MICROCONTROLLER PRODUCT SPECIFICATIONS
PIC
PIC16C5X
PIC1654S
PIC1655
PIC1670

SECTION 5

LOGIC PRODUCT SPECIFICATIONS
AY2661
AY3-1015D
AY58116/36
AY58126/46
AY38910Al12A
AY8930
AY0438-1

SECTION 6

Product Portfolio ....................................................................................................... 6- 1
CMOS Digital Signal Processor (B Version) ............................................................. 6- 5
Development Tools ................................................................................................... 6- 23

Quality Without Compromise .................................................................................... 7EPROM Plastic Package Reliability Bulletin ............................................................. 7- 11

PACKAGING
Packaging

APPENDIX

17
29
37
45
61
81

QUALITY AND RELIABILITY
QA
27Cxxx

SECTIONS

Enhanced Programmable Communication Interface ................................................ 5UARIT: Universal Asynchronous ReceiverITransmitter ........................................... 5Dual Baud Rate Generator ....................................................................................... 5Single Baud Rate Generator ..................................................................................... 5Programmable Sound Generator .............................................................................. 5Enhanced Programmable Sound Generator ............................................................. 532-Segment CMOS LCD Driver ................................................................................ 5-

DIGITAL SIGNAL PROCESSING PRODUCT SPECIFICATIONS
DSP
DSP320C10
DSP320C10

SECTION 7

PIC 16xxx Series Microcontroller Family .................................................................. 4- 1
EPROM-Based 8-Bit CMOS Microcontroller Series ................................................ .4- 5
8-Bit Microcontroller .................................................................................................. 4- 35
8-Bit Microcontroller .................................................................................................. 4- 51
8 Bit Microcontroller .................................................................................................. 4- 67

Outlines and Dimensions .......................................................................................... 8-

OFFICE LOCATIONS
Factory Representatives ........................................................................................................................A- 1
Distributors
.................................................................................................................................. A- 5
Field Offices
..................................................................................................................................A- 12

DS00018C

Microchip

DS00018C

MICROCHIP
TECHNOLOGY
INCORPORATED

Microchip

Company Profile

FEATURES

BUSINESS SCOPE

Fully integrated manufacturing
A global network of plants and facilities
A history of innovation
Strategic marketing focus
• A prOduct family of shared strengths
Quality without compromise
Research and development of high performance
products
Performance alliance with customers
• A solid executive team with an eye towards
innovation

Microchip Technology manufactures and markets very
large scale integrated circuits (VLSI). The Company's
strong experience in CMOS nonvolatile memories,
programmable microcontrollers and peripheral devices
has positioned the firm as a leading supplier to manufacturers of computer peripheral, automotive, consumer,
military and telecommunication products.

Company headquarters in Chandler, Arizona; executive offices, R&D, and two wafer fabrication units occupy this 142,000
square-foot facility.

DS00027D-1

vii

Microchip Technology Incorporated

DS00027D-2

viii

Microchip Technology Incorporated

MICROCHIP:
A FULLY INTEGRATED COMPANY
SERVING A GLOBAL MARKET

Propelled by customer
requirements ....

"Microchip Technology draws its impetus from the technology
expectations of a large base of longstanding customers. Microchip is small enough to respond quickly with technology to equate
the customer's need. Moreover, as a fully integrated IC Manufacturer, Microchip deploys its panoply of resources to act timely and
efficiently, and on a worldwide scale: Design, Technology Development, Mask Shop, Wafer Fabrication, Assembly and Test,
Customer Support.

... and powered by continuous
improvement. ..

"World-wide competition leaves no room for divergence or mediocrity. Therefore, Microchip Technology is committed to focus
and to continuously improve all the vital aspects of its business.
To improve performance, our employees are encouraged to
analyze their methods continually.
Personal empowerment
trespasses the limits of personal responsibility to act in anticipation .

... upfront the wave of
technological change.

"Our industry's life-line is innovation. The fast pace of technological change is inherent in our industry. Microchip Technology has
accelerated the rate of change of its technology and products to
the forefront of the eConomical feasibility.
"Change is our ally. Driving and managing change is our winning
strategy."

President

DS00027D-3

Microchip Technology Incorporated
A PRODUCT FAMIL V OF
SHARED STRENGTHS

Microchip's product focus is CMOS nonvolatile memories and
programmable microcontrollers. These product lines include
EEPROMs, High Speed EPROMs, Flash EPROMs, and PIC®
microcontrollers in a broad range of product densities, speeds
and packages.

Microchip is quick to capitalize on advances in one product line by
incorporating those breakthroughs into other product families.
The possibility of enhancing the performance levels of each
Microchip product family is explored with every innovation.

MICROCONTROLLERS

Microcontrollers from Microchip combine high performance, low
cost, and small package size. They offer the best price/performance
ratio in the industry. Large numbers of these devices are used in
computer peripherals, data entry, office automation, automotive
control systems, security, and cost-sensitive consumer products,
such as remote controls and appliances.

The widely accepted PIC16XX (over 75 million shipped) and
PIC16CXX series are the industry's only 8-bit based microcontrollers using a high speed RISC architecture. Microchip pioneered
the use of RISC architecture to obtain high speed and instruction
efficiency. The CMOS PIC16CXX is in volume production, and
has achieved over one thousand design wins.

The PIC family is supported by a range of user-friendly development
systems, including simulators and in-circuit emulators.

Future CMOS PIC generations will include advanced features,
such as higher speed, additional I/O, sophisticated timers, embedded AID, extended instruction/data memory and inter-processor communication,

SERIAL EEPROMs

Serial EEPROM devices are available in 256 bit, 1K, 2K, 4K, and
16K bit densities. Endurance is greater than 100,000 erase/write
cycles. These EEPROMs are ESD protected for greater than 4
to +85
kV and operate over a temperature range from -40
They are available in SOIC packages conforming to JEDEC and
Japanese standards. The main markets are automotive and
consumer products, such as entertainment and telecommunication electronics and appliances.

EEPROMs

ac.

The 1.2* micron CMOS EEPROM devices from Microchip are
available in 4K, 16K, and 64K densities. The manufacturing
process used for these EEPROMs ensures 10,000 to 100,000
write and erase cycles. Data retention is over 10 years. Short
write times are less than 200 I1sec. These EEPROMs work
reliably under demanding conditions and have been proven to
to + 125
operate efficiently at temperatures from -55

ac.

* All EEPROMs 4K and greater utilize a 1.2 micron CMOS process.
D800027D-4

Microchip Technology Incorporated
Common applications include computer peripherals, engine control, pattern recognition and telecommunications.

EPROMs

Microchip's CMOS EPROM devices are produced in densities
from 64K to 512K. High Speed EPROMs have access times
range as low as 45 nano-seconds. Microchip's process flow
uniqueness lies in its simplicity. A minimum number of steps allow
to offer a reliable family of commodity EPROMs, single metal
EPROMs, and double metal EPROMs. Typical applications include computer peripheral, military, instrumentation, and automotive devices.

Microchip's expertise in Plastic Packaging, combined with its
previous leadership in the ROM market, led to the development
of the Plastic OTP EPROM market where Microchip the #1
supplier today.

MILITARY PRODUCTS

Microchip delivers military devices that conscientious engineers
can use with confidence. Our 883C compliant parts cover all
quality fronts: DESC standard military drawing approval, high
speed performance and quick turn availability.

Microchip's military products include CMOS memories, CMOS/
NMOS digital signal processors and microcontrollers - all with
high reliability, fast access times and proven retention. Endurance
is guaranteed in both dual in-line cerdip packages and leadless
chip carriers.

OTHER MICROCHIP
PRODUCTS

Other Microchip products, such as DSPs, ICs for serial data
communications and sound generation, are mature products with
proven track record, and a large, repeat customer base.

Microchip provides a wide package selection of single-chip DSPs
that can be programmed for a wide variety of applications. Several
variants of the industry standard 32010 and 320Cl 0 are offered
at speeds up to 25 MHz. The 320 DSP family is often found in
commercial and military applications were medium and high
performance parts are required.

The Company's reputation as a quality supplier of DSPs is
evidenced by a license agreement with Texas Instruments to
second-source the TMS 32010 and TMS 320Cl0.

DS00027D-5

Microchip Technology Incorporated
FULLY INTEGRATED
MANUFACTURING

Microchip delivers fast turnaround through total control over all
phases of production. Design, product development, mask making, wafer fabrication, assembly and quality assurance testing are
conducted at facilities owned and operated by Microchip. Our
integrated approach to manufacturing along with rigorous use of
statistical process control, continuous improvement and implementation of root cause fixes, has brought forth tight product
consistency levels and high yields which enable Microchip to
compete successfully in world markets.

A GLOBAL NETWORK OF
PLANTS AND FACILITIES

Microchip is a global competitor providing local service to the
world's technology centers. The Company's focal point is the
design and technology advancementfacility in Chandler, Arizona.
Most military and high performance parts emanate from here, as
well as front end wafer fabrication and electrical probing.
Microchip's assembly and test facility in Kaohsiung, Taiwan
houses the technology and modern assembly methods necessary for plastic and ceramic packaging. Select quality conscious
firms who fabricate wafers in the Pacific Rim use our Kaohsiung
plant for assembly.
Sales and application offices are located in key cities throughout
the Western Hemisphere, Pacific Rim and Europe. Offices are
staffed to meet the high quality expectations of our customers,
and can be accessed for technical support, purchasing information and failure analysis.

A HISTORY OF INNOVATION

Microchip's history of innovation in the semiconductor industry is
as old as the industry itself. For over a quarter century Microchip
and its former parent company General Instruments have been
developers of cost-effective logic and memory technology and
products.
Microchip is credited with a number of firsts: The Metal-OxideSilcon (MOS) Integrated Circuit, DRAM, serial EEPROM, Reduced Instruction Set Computer (RISC) microcontroller product
family, UART, CMOS 64K EEPROM, and CMOS single chip DSP
are all innovations that were originally developed and introduced
by our engineers.

STRATEGIC
MARKETING FOCUS

Microchip targets selected markets where our advanced designs,
progressive process technology and industry leading operating
speeds enable us to deliver decidedly superior performance. The
firm has recently positioned itself to playa dominant role as a
supplier of high performance reprogrammable microcontrollers,
and CMOS nonvolatile memories.

FUTURE PRODUCTS

New process technology is constantly being developed for
EEPROM, High Speed EPROM, and microcontroller products.
Many advanced process technology modules are being developed that will be integrated into our present product lines to
achieve a range of compatible processes. Current production
technology is attaining 1.2 micron densities. Substantial progress

DS00027D-6

xli

Microchip Technology Incorporated
toward 1 micron and submicron technologies are under development, as well as new CMOS EEPROM, High Speed CMOS
EPROM and advanced CMOS RISC-based microcontroller products.

QUALITY WITHOUT
COMPROMISE

Product reliability is designed into Microchip products at the
outset. Design margins are established to guarantee that every
product can be produced easily, error-free and within the tolerances
of the manufacturing process.
All our quality assurance tests are run tighter than customer
specifications. Products are tested at least two machine tolerances higher than those specified by the customer.
Every new product is measured under accelerated stress testing.
Test samples encompass the full range of processed tolerances
at each step. Data sheets detailing these processes enable
customers to reach accurate decisions based on known quantitative values.
To determine whether a process is within normal manufacturing
variation, statistical techniques are put to work at each process
step. In-process controls are performed by operators in the wafer
fabrication division and immediate corrective action is taken if
they deem a process is out of control. Products are also sampled
weekly through a variety of carefully monitored stress and accelerated life tests.
Microchip's positive documentation control program assures the
correct document is always available at the point of use. Active
documents are serialized and stamped to eliminate the possibility
of performing a job from obsolete or incorrect instructions.
Individuals in all departments are required to analyze the methods
employed at their positions and formulate plans to improve
performance. The evaluation process is never exhausted.
Screening efforts alone are never considered enough. In all areas
of our business, everyone is expected to make continuous improvement.

RESEARCH AND
DEVELOPMENT OF

PERFORMANCE PRODUCTS

Microchip's research and development activities, include exploring new process technologies and products that have industry
leadership potential. Particular emphasis is placed on products
that can be put to work in high performance niche markets.
Equipment is continually updated to bring the most sophisticated
process, CAD and testing tools on line. Cycle times for new
technology development are continuously reduced by using a
pilot line within the manufacturing facility.

FORMING A
PERFORMANCE ALLIANCE
WITH CUSTOMERS

Microchip works in tangent with customers to establish mutual
programs to improve the performance of our products in their
systems. We go beyond the incoming inspection level and specification by extending our quality responsibility to the point where
the customer ships the system. Microchip's quality programs
ensure that our products can be used with such impunity, a
customer can implement improvement programs centered on us
as a supplier.

DS00027D-7

xiii

Microchip Technology Incorporated
NOTES:

D5000270-8

xlv

Microchip

SECTION 1
SERIAL EEPROM PRODUCT SPECIFICATIONS
24C01A
24C01A Dice
24C02A
24C02A Dice
24C04A
24C04A Dice
59C11
59C11 Dice
85C72
85C72 Dice
85C82
85C82 Dice
85C92
85C92 Dice
93C06
93C06 Dice
93C46
93C46 Dice
24CXXl85CXX
ER59256/93C06
24C01A

1K (128 x 8) CMOS Serial Electrically Erasable PROM ........................................... 1- 1
1 K (128 x 8) CMOS Serial Electrically Erasable PROM Die Form ........................... 1- 9
2K (256 X 8) CMOS Serial Electrically Erasable PROM ........................................... 1- 17
2K (256 X 8) CMOS Serial Electrically Erasable PROM Die Form ........................... 1- 25
4K (512 x 8) CMOS Serial Electrically Erasable PROM ........................................... 1- 33
4K (512 x 8) CMOS Serial Electrically Erasable PROM Die Form ........................... 1- 41
1K (128 x 8 or 64 x 16) CMOS Serial Electrically Erasable PROM .......................... 1- 49
1K (128 x 8 or 64 x 16) CMOS Serial Electrically Erasable PROM Die Form .......... 1- 57
1K (128 x 8) CMOS Serial Electrically Erasable PROM ........................................... 1- 65
1K (128 x 8) CMOS Serial Electrically Erasable PROM Die Form ........................... 1- 73
2K (256 x 8) CMOS Serial Electrically Erasable PROM ........................................... 1- 81
2K (256 x 8) CMOS Serial Electrically Erasable PROM Die Form ........................... 1- 89
4K (512 x 8) CMOS Serial Electrically Erasable PROM ........................................... 1- 97
4K (512 x 8) CMOS Serial Electrically Erasable PROM Die Form ........................... 1-105
256 Bits (16 x 16) CMOS Serial Electrically Erasable PROM ................................... 1-113
256 Bits (16 x 16) CMOS Serial Electrically Erasable PROM Die Form ................... 1-121
1K (64 x 16) CMOS Serial Electrically Erasable PROM ........................................... 1-129
1K (64 x 16) CMOS Serial Electrically Erasable PROM Die Form ........................... 1-137
24CXXl85CXX To Microcontroller Communication .................................................. 1-145
ER59256/93C06 And NMC9306/NMC93C06 Compatibility Issue ............................ 1-155
24C01A Compatibility Issue And Its Mobility For Memory Upgrade ......................... 1-159

1-i

DS00018C

Microchip

DS00018C

1-ii

24C01A

Microchip

lK (128 X 8) CMOS Serial Electrically Erasable PROM
FEATURES

DESCRIPTION

•
•
•
•
•
•
•
•
•
•
•

The Microchip Technology Inc 24C01A is a 1K bit Electrically Erasable PROM. The device is organized as 128
x 8 bit memory with a two wire serial interface. Advanced
CMOS technology allows a significant reduction in power
over NMOS serial devices. Up to eight 24COI As may be
connected to the two wire bus. The 24COI A is available
in the standard 8-pin DIP and a surface mount SOIC
package.

Low power CMOS technology
Organized as one block of 128 bytes (128 x 8)
Two wire serial interface bus
S volt only operation
Self-timed write cycle (including auto-erase)
Page-write butter for up to 2 bytes
1ms write cycle time for single byte
100,000 eraselwrite cycles
Data retention >10 years
8-pin DIP or SOIC package
Available for extended temperature ranges:
-Commercial: O'C to +70'C
-Industrial: -40'C to +8S'C
-Automotive: -40'C to +12S'C

PIN CONFIGURATION

BLOCK DIAGRAM

DIP Package
AO

Vee

SCL

Vss

SDA
SDA

SO Package
AO

Vee

SCL

Vss

SDA

SCL
AO A1 A2

1-1

24C01A
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE

Maximum Ratings·
All inputs and outputs w.r.t. Vss .................... -0.3 V to +7 V
Storage temperature ........................ -65'C to + 150'C
Ambient temp. with power applied ....... -65'C to + 125'C
Soldering temperature 01 leads (10 seconds) .... +300'C
ESD protection on all pins ..................................... .4 kV
*Notice: Stresses above those listed under "Maximum ratings" may cause
permanent damage to the device. This is astress rating only and functional

Name

Function

AO,A1,A2
Vss
SDA
SCl
NF
Vcc

Chip Address Inpu's
Ground
Serial Address/Data I/O
Serial Clock
No Function
+5 V Power Supply

operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied.

Exposure to maximum rating conditions for extended periods may affect
device reliability.

Vee = +5 V (±10%)
Commercial (C): Tamb = O'C to +70'C
Industrial
(I): Tamb = -40'C to +85'C
Automotive lEi: Tamb - -40'C to +125'C

DC CHARACTERISTICS

Parameter

Symbol

Min

Max

Units

Vee detector threshold

VTH

2.8

4.5

SCl and SDA pins:
High level input voltage
low level input voltage
low level output voltage

VIH
VIL
VOL

Vee x 0.7
-0.3

Vee + 1
Vee x 0.3
0.4

V
V
V

AO, A1 & A2 pins:
High level input voltage
low level input voltage

VIH
VIL

Vee - 0.5
-0.3

Vee + 0.5
0.5

V
V

Input leakage current

III

J,tA

VIN = 0 V to Vcc

Output leakage current

ILO

j.!A

VOUT = 0 V to Vcc

Internal capacitance
(all inputs/outputs)

CINT

7.0

VINNoUT = 0 V (Note 1)
Tamb = +25'C, 1 = 1 MHz

Operating current

leeo

3.5

4.25

mA
mA
j.!A

FeLK = 100 kHz. program cycle
time = 2 ms, Vee = 5 V,
Tamb = O'C to 70'C
FeLK = 100 kHz, program cycle
time = 2 ms, Vee = 5 V,
Tamb = (I) and (E)
Vee = 5 V, Tamb = O'C to +70'C
Vee = 5 V, Tamb= (I) and (E)
Vee=5 V, Tamb= (C), (I) and (E)

j.!A

program cycle

lecw

read cycle

leeR

7.0
8.5
750

Ices

100

Standby current

Conditions

IOL = 3.2 mA (SDA only)

SDA = SCl = Vee = 5 V
(no PROGRAM active)

Note 1: This parameter is periodically sampled and not 100% tested.
BUS TIMING START/STOP

seL--~

SDA

DS111338-2

-----r..1

1-2

24C01A
AC CHARACTERISTICS
Parameter

Symbol

Clock frequency

FCLK

Clock high time

THIGH

4000

Clock low time

TLOW

4700

SDA and SCl rise time

Typ

Min

Units

100

kHz

Remarks

ns
ns

SDA and SCl fall time

Max

1000

300

START condition hold time

THD:STA

4000

After this period the first
clock pulse is generated

START condition setup time

TSU:STA

4700

Only relevant for repeated
START condition

Data input hold time

THD:DAT

Data input setup time

TSU:DAT

250

Data output delay time
STOP condition setup time
Bus free time

300
4700

TBUF

4700

Input filter time constant
(SDA and SCl pins)
Program cycle time

3500

TPD
TSU:STO

TI
.7N

Twc

100

See Note 1

Time the bus must be free
before a new transmission
can start

Byte or Page mode N = # of
bytes to be written

Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min 300
ns) of the falling edge of SCl to avoid unintended generation of START or STOP conditions.

BUS TIMING DATA
SCL

SDA
_TBUF

FUNCTIONAL DESCRIPTION
The 24C01 A supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl), controls the bus access, and generates the
START and STOP conditions, while the 24C01 A works
as slave. Both, master and slave can operate as trans-

mitter or receiver but the master device determines
which mode is activated.
Up to eight 24C01 As can be connected to the bus,
selected by the AO, A1 and A2 chip address inputs.
Other devices can be connected to the bus but require
different device codes than the 24C01 A (refer to section Slave Address).

1-3

DS111338-3

24C01A
BUS CHARACTERISTICS
The following bus protocol has been defined:
- Data transfer may be initiated only when the bus is not
busy.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will. be interpreted as a
START or STOP condition.
Accordingly, the following bus conditions have been defined (see Figure 1):

The data on the line must be changed during the lOW
period olthe clock signal. There is one clock pulse ~r bit
of data.
Each data transfer is initiated with a START condition and
terminatedwithaSTOPcondition. Thenumberofthedata
bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited.

Bus not Bysy (A)
Both data and clock lines remain HIGH.

Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the clock
(SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.

Stop Data Transfer (C)
A lOW to HIGH transition of the SDA line while the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

Data Valid (D)
The state olthe data line represents valid data when, after
a START condition, the data line is stable for the duration
of the HIGH period of the clock signal.

Note: The 24C01A does not generate any acknowledge
bits if an internal programming cycle is in progress.
The device that acknowledges, has to pull down the SDA
lineduringtheacknowledgeclockpulse in such a way that
the SOA line is stable lOW during the HIGH period of the
acknowledge related clock pulse. Of course, setup and
hold times must be taken into account. A master must
signal an end of data to the slave by not generating an
acknowledge bit on the last byte that has been clocked out
olthe slave. In this case, the slave must leave the data line
HIGH to enable the master to generate the STOP condition.

FIGURE 1 - DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)

SCl

(8)

--+--t-"'"

SDA

START CONDITION

DS111338'4

ADDRESS
DATA AllOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID

1-4

STOP
CONDITION

24C01A
SLAVE ADDRESS
word address and will be written into the address pointer
ofthe24C01 A. The most significant bitofthewordaddress
is a "Do Not Care" value for the 24C01 A. After receiving
the 'acknowledge of the 24C01 A, the master device transmits the data word to be written into the addressed memory
location. The 24C01A acknowledges again and the
master generates a STOP condition. This initiates the
internal programming cycle of the 24C01 A. (See Figure
3).

The chip address inputs AO, A1 and A2. of each 24C01 A
must be externally connected to either Vee or ground
(Vss), assigning to each 24C01A a unique 3-bit address.
Up to eight 24C01 As may be connected to the bus. Chip
selection is then accomplished through software by setting
the bits AO, A1 and A2 of the slave address to the corresponding hardwired logic levels of the selected 24C01 A.
Aftergenerating a START condition, the bus master transmits the slave address consisting of a 4-bit device code
(1010) for the 24C01 A, followed by the chip address bits
AO, A1 and A2.

PAGE PROGRAM MODE

The eighth bit of slave address determines if the master
devicewantsto read or writeto the 24C01A. (See Figure2.)

To program the 24C01 A, the mastersends addresses and
data tothe 24C01 A which is the slave, (see Figure 3). This
is done by supplying a START condition followed by the 4bit device code, the 3-bit slave address, and the RiW bit
which is defined as a logic LOW for a write. This indicates
to the addressed slave that a word address will follow so
the slave outputs the acknowledge pulse to the master
during the ninth clock pulse. When the word address is
received by the 24C01 A, it places it in the lower a bits olthe
address pointer defining which memory location is to be
written. (One do not care bit and seven address bits.) The
24C01 A will generate an acknowledge after every a-bits
received and store them consecutively in a 2-byte RAM
until a STOP condition is detected which initiates the
internal programming cycle. If more than 2 bytes are
transmitted by the master, the 24C01 A will terminate the
write cycle. Th is does not affect erase/write cycles of the
EEPROM array.

The 24C01 A monitors the bus for its corresponding slave
address all the time. It generates an acknowledge bit ifthe
slave address was true and it is not in a programming
mode.

FIGURE 2 - SLAVE ADDRESS
ALLOCATION
START

/
I

(

READIWRITE

'-.....

I :

If the master generates a STOP condition after transmittingthefirstdataword (Point 'P' on Figure3), byte programming mode is entered.
The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by the
master and all received (up to two) databyteswill be written
in a serial manner.

BYTE PROGRAM MODE
In this mode the master sends addresses and one data
byte to the 24C01 A.

The PROGRAM cycle takes N milliseconds, whereby N is
the number of received data bytes (N max = 2).

Following the START condition, the device code (4-bit),
the slave address (3-bit), and the RiW bit, which is logic
LOW, are placed onto the busby the master. This indicates
to the addressed 24C01 A that a byte with a word address
will follow after it has generated an acknowledge bit.
Therefore, the next byte transmitted by the master is the

FIGURE 3 - PROGRAM MODE (ERASEIWRITE)

1-5

ACKNOWLEDGES FROM SLAVE

DSll1338-5

24C01A
READ MODE
This mode illustrates master device reading data from the
24C01A.
As can be seen from Figure 4, the master first sets up the
slave and word addresses by doing a write. (Note:
Although this is a read mode, the address pointer must be
written to.) During this period the 24C01 A generates the
necessary acknowledge bits as defined in the appropriate
section.
The master now generates another START condition and
transmits the slave address again, except this time the
read/write bit is set into the read mode. After the slave
generates the acknowledge bit, it then outputs the data

from the addressed location on tothe SDA pin, increments
the address pointer and, if it receives an acknowledge from
the master, will transmit the next consecutive byte. This
autoincrement sequence is only aborted when the master
sends a STOP condition instead of an acknowledge.
Note: If the master knows where the address pointer is, it
can begin the read sequence at point 'R' indicated on
Figure 4 and save time transmitting the slave and word
addresses.
In all modes, the address pointer will automatically increment from the end olthe memory block (128 byte) back to
the first location in that block.

FIGURE 4 " READ MODE

R/W

AUTO INCREMENT
WORD ADDRESS

PIN DESCRIPTION
AQ, A1 and A2 Chip Address Inputs

SCL Serial Clock

The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if
the compare is true.

This input is used to synchronize the data transfer from
and to the device.

Up to eight 24C01 As can be connected to the bus.

NF No Function
Must be connected to either Vss or Vcc.

These inputs must be connected to either vss or Vcc.

SDA Serial Address/Data Input/Output

Notes:

This is a bidirectional pin used to transfer addresses and
data into and data out of the device. It is an open drain
terminal.

1) A "page" is defined as the maximum number of bytes
that can be programmed in a single write cycle. The
24C01A page is 2 bytes long.

For normal data transfer, SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are reserved for indicating the START and STOP conditions.

2) A "block" is defined as a continuous area of memory
with distinct boundaries. The address pointer can not
cross the boundary from one block to another. It will
however, wrap around from the end of a block to the first
location in the same block. The 24C01A has only one
block (128 bytes).

05111338-6

1-6

24C01A
NOTES:

1-7

D5111338-7

24C01A
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.

PART NUMBERS

J
P

PACKAGE:

SN
SM

0511133B-8

TEMPERATURE
RANGE:

DEVICE:

Blank
I
E

24COtA
24C01AT

1-8

CERDIP
Plastic DIP
Plastic SOIC (0. t 50 mil Body)
Plastic SOIC (0.207 mil Body)
0' C to +70' C
-40' C to +85' C
-40' C to +125' C
1K CMOS Serial EEPROM
1K CMOS Serial EEPROM
(in Tape & Reel)

24C01A
DICE FORM

Microchip

lK (128 X 8) CMOS Serial Electrically Erasable PROM
FEATURES
•

•
•
•

DESCRIPTION

Low power CMOS technology
Organized as one block of 128 bytes (128 x 8)
Two wire serial interface bus
5 volt only operation
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 2 bytes
1ms write cycle time for single byte
Available in wafer or wafflepack
Temperature range:
-Commercial: O'C to +70'C

The Microchip Technology Inc. 24C01A is a 1K bit
Electrically Erasable PROM. The device is organized as
128 x 8 bit memory with a two wire serial interface.
Advanced CMOS technology allows a significant reduction in power over NMOS serial devices. Up to eight
24C01 As may be connected to the two wire bus. The
24C01 A dice are available in wafer or waffle pack
package.

DIE CONFIGURATION

BLOCK DIAGRAM

Die Size: 106 x 76 mils

Vcc --Vss ___

Data
Buffer

2xB

(FIFO)

AP
do
di
r n
e t
s e
s r

Slave

12.

3.
4.

AO
AI
A2
Vss

8.
7.

6.
5.

Increment

SCL

Vcc
NF
SCL
SDA

Memory
Array
128 x 8

AOto
A6

AO AI A2

1-9

DS11141C-l

24C01A

DICE FORM

ELECTRICAL CHARACTERISTICS

PAD FUNCTION TABLE
Function

Name

Maximum Ratinas*
All inputs and outputs w.r.t. vss ................... -0.3V to +7V
Storage temperature ....................... -65'C to +150'C
Ambient temp. with power applied ..... -65'C to + 125'C
Soldering temperature of leads (10 seconds) .. +300'C
ESD protection on all pins ................................... .4 kV

AO, A1, A2
Vss
SDA
SCL
NF
Vcc

"Notice: Stresses above those listed under "Maximum ratings" may

cause permanent damage to the device. This is a stress rating only and

Chip Address Inputs
Ground
Serial Address/Data I/O
Serial Clock
No Function
+5 V Power Supply

functional operation of the device at those or any other conditions above

those indicated in the operational listings of this specification is not
implied. Exposure to n;aximum rating conditions for extended periods
may affect device reliability.

DC CHARACTERISTICS

Parameter

Vee = +5V (±10%)
Commercial (C): Tamb

Symbol

Min

Max

Units

Vee detector threshold

VTH

2.8

4.5

SCL and SDA pins:
High level input voltage
Low level input voltage
Low level output voltage

VIH
VIL
VOL

Vcex 0.7
-0.3

Vce+ 1
Vee x 0.3
0.4

V
V
V

AO, A1 & A2 pins:
High level input voltage
Low level input voltage

VIH
VIL

Vee - 0.5
-0.3

Vee + 0.5
0.5

V
V

= O'C to +70'C

Conditions

IOL

=3.2 mA (SDA only)

= 0 V to Vcc

Input leakage current

III

IlA

VIN

Output leakage current

= 0 V to Vcc

ILO

IlA

VOUT

Internal capacitance
(all inputs/outputs)

CINT

7.0

VINlVoUT =0 V (Note 1)
T amb = +25'C, f = 1 MHz

Operating current

leeo

3.5

program cycle

leew

7.0

FeLK=o 100 kHz,program cycle
time = 2 ms, Vee = 5 V,
Vee=5 V

read cycle

leeR

750

IlA

Vee=5 V

Ices

100

IlA

SDA = SCL =Vee = 5 V
(no PROGRAM active)

Standby current

Note 1: This parameter is periodically sampled and not 100% tested.

BUS TIMING START/STOP

SCL _ _- - J

SDA

------;-,1

START

DS11141C-2

STOP

1-10

24C01 A DICE FORM
AC CHARACTERISTICS
Parameter

Symbol

Typ

Min

Clock Frequency

FCLK

Clock high time

THIGH

4000

Clock low time

TLOW

4700

Max

Units

100

kHz

Remarks

ns
ns

SDA and SCl rise time

1000

SDA and SCl fall time

300

START condition hold time

THD:STA

4000

After this period the first
clock pulse is generated

START condition setup time

TSU:STA

4700

Only relevant for repeated
START condition

Data input hold time

THD:DAT

Data input setup time

TSU:DAT

250

Data output delay time

TPD

300

Tsu:sTo

4700

TBUF

4700

STOP condition setup time
Bus free time

Noise suppression time constant
(SDA and SCl pins)
Program cycle time

3500

.7N

Twc

100

See Note 1

Time the bus must be free
before a new transmission
can start

Byte or Page mode N = #
of bytes to be written

BUS TIMING DATA
SCL
....-..-

THD:DAT (receiver)
(transmitter)

T PO

FUNCTIONAL DESCRIPTION
transmitter or receiver but the master device determines
which mode is activated.

The 24COI A supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl), controls the bus access, and generates the
START and STOP conditions, while the 24COI A works
as slave. Both, master and slave can operate as

Up to eight 24C01As can be connected to the bus,
selected by the AO, Al and A2 chip apdress inputs.
Other devices can be connected to the bus but require
different device codes than the 24COI A (refer to section
Slave Address).

1-11

DSll141C-3

24C01 A DICE FORM
BUS CHARACTERISTICS
The following bus protocol has been defined:
- Data transfer may be initiated only when the bus is not
busy.
During data transfer, the data line must remain stable
wheneverthe clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as
a START or STOP condition.
Accordingly, the following bus conditions have been
defined (see Figure 1):

Bus not Busy CAl
Both data and clock lines remain HIGH.

Start Data Transfer CBl
A HIGH to LOW transition olthe SDA line while the clock
(SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

Stop Data Transfer Cel
A LOW to HIGH transition of the SDA line while the clock
(SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

Data Valid COl
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clOCk pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.

Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note: The 24C01 A does not generate any acknowledge
bits if an internal programming cycle is in progress.
The device that acknowledges, has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out olthe slave. In this case the slave must
leave the data line HIGH to enable the master to generate the STOP condition.

FIGURE 1· DATA TRANSFER ON THE SERIAL BUS

(A)
(8)
SCl --+--t~

(A)

SDA

START CONDITION

DS11141C·4

ADDRESS
DA fA N lOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID

1-12

STOP
CONDITION

24C01 A DICE FORM
SLAVE ADDRESS
indicates to the addressed 24C01A that a byte with a
word address will follow after it has generated an acknowledge bit. Therefore the next byte transmitted by
the master is the word address and will be written into
the address pOinter of the 24C01 A. The most significant
bit of the word address is a "Do Not Care" value for the
24C01 A. After receiving the acknowledge of the 24C01 A,
the master device transmits the data word to be written
into the addressed memory location. The 24C01A
acknowledges again and the master generates a STOP
condition. This initiates the internal programming cycle
of the 24C01 A. (See Figure 3.)

The chip address inputs AO, A1 and A2 of each 24C01A
must be externally connected to either Vee or ground
(Vss) , assigning to each 24C01 A a unique 3-bit address.
Uptoeight24C01As may be connected to the bus. Chip
selection is then accomplished through software by
setting the bits AO, A1 and A2 of the slave address to the
corresponding hardwired logic levels of the selected
24C01A.
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24C01A, followed by the chip address bits AO, A1 and A2.
The eighth bit of slave address determines if the master
device wants to read orwrite to the 24C01 A. (See Figure
2.)

PAGE PROGRAM MODE
To program the 24C01A, the master sends addresses
and data to the 24C01 A which is the slave (see Figure
3). This is done by supplying a START condition
followed by the 1jlit device code, the 3-bit slave address, and the RIW bit which is defined as a logic LOW
for a write. This indicates to the addressed slave that a
word address will follow so the slave outputs the acknowledge pulse to the master during the ninth clock
pulse. When the word address is received by the
24C01A, it places it in the lower a bits of the address
pointer defining which memory location is to be written.
(One do not care bit and seven address bits.) The
24C01 A will generate an acknowledge after every a-bits
received and store them consecutively in a 2- byte RAM
until a STOP condition is detected which initiates the
internal programming cycle. If more than 2 bytes are
transmitted by the master, the 24C01A will terminate the
write cycle. This does not affect erase/Write cycles of the
EEPROM array.

The 24C01 A monitors the bus for its corresponding
slave address all the time. It generates an acknowledge
bit if the slave address was true and it is not in a programming mode.

FIGURE 2 - SLAVE ADDRESS
ALLOCATION
START

READIWRITE

1 : s:LAV~

AD9RES:S

:'"(Ami
\

Ifthe master generates a STOP condition after transmitting the first data word (Point 'P' on Figure 3), byte
programming mode is entered.
The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been' generated by
the master and all received (up to two) data bytes will be
written in a serial manner.

BYTE PROGRAM MODE
In this mode, the master sends addresses and one data
byte to the 24C01 A.

The PROGRAM cycle takes N milliseconds, whereby N
is the number of received data bytes (N max = 2).

Following the START condition, the device code (4-bit),
the slave address (3-bit), and the Rm bit, which is logic
LOW, are placed onto the bus by the master. This

FIGURE 3 - PROGRAM MODE (ERASEIWRITE)
ACKNOWLEDGES FROM SLAVE

1-13

DS11141C-5

24C01 A DICE FORM
READ MODE
This mode illustrates master device
the 24C01A.

n~ading

data from

As can be seen from Figure 4, the master first sets up the
slave and word addresses by doing a write. (Note:
Although this is a read mode, the address pOinter must
be written to.) During this period the 24C01 A generates
the necessary acknowledge bits as defined in the appropriate section.
The master now generates another START condition
and transmits the slave address again, except this time
the readlwrite bit is set into the read mode. After the

slave generates the acknowledge bit, it then outputs the
data from the addressed location on to the SDA pad,
increments the address pointer and, if it receives an
acknowledge from the master, will transmit the next
consecutive byte. This autoincrement sequence is only
aborted when the master sends a STOP condition
instead of an acknowledge.
Note: If the master knows where the address pointer is,
it can begin the read sequence at point 'R' indicated on
Figure 4 and save time transmitting the slave and word
addresses.

FIGURE 4 - READ MODE

AUTO INCREMENT
WORD ADDRESS

PAD DESCRIPTION
AQ, A1 and A2 ChiD Address Inputs
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the cOmpare is true.
Up to eight24C01 As can be connected to the bus.

For normal data transfer, SDA is allowed to change only
during SCl lOW. Changes during SCl HIGH are reserved for indicating the START and STOP conditions.

SCL Serial Clock

These inputs must be connected to either Vss or Vcc.

This input is used to synchronize the data transfer from
and to the device.

SDA Serial Address/Data Input/Output

NF No Function

This is a bidirectional pad used to transfer addresses
and data into and data out of the device. It is an open
drain terminal.

DS11141C-6

Must be (;onnected to either Vss or Vcc.

1-14

24C01 A DICE FORM
NOTES:

1-15

DSll141C-7

24C01 A DICE FORM
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.

PART NUMBERS

W
S

DS11141C·8

O' Cto 70' C

TEMPERATURE
RANGE:

DEVICE:

DICE in WAFER
DICE in WAFFLEPACK

24COIA

1-16

lK CMOS SERIAL EEPROM

24C02A

Microchip

2K (256 X 8) CMOS Serial Electrically Erasable PROM
FEATURES

DESCRIPTION

•
•
•
•
•
•
•
•
•
•
•
•

The Microchip Technology Inc. 24C02A is a 2K bit Electrically Erasable PROM. The device is organized as 256
x 8 bit memory with a two wire serial interface. Advanced
CMOS technology allowsasignificant reduction in power
over NMOS serial devices. A special feature allows a
write protection for the upper 1K (128 x 8). The 24C02A
also has a page-write capability for up to 2 bytes of data.
Up to eight 24C02As may be connected to the two wire
bus. The 24C02A is available in the standard 8-pin DIP
and a surface mount SOIC package.

Low power CMOS technology
Organized as one block of 256 bytes (256 x 8)
Hardware write protect for upper 1K (128 x 8)
Two wire serial interface bus
5 volt only operation
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 2 bytes
1ms write cycle time for single byte
100,000 erase/write cycles
Data retention >10 years
8-pin DIP or SOIC package
Available for extended temperature ranges:
- Commercial: O·C to +70·C
- Industrial: -40·C to +SS·C
- Automotive: -40·C to +125·C

BLOCK DIAGRAM

PIN CONFIGURATION
DIP Package

Vee

SCl

Vss

SOA

SO Package
AO

Vee

SCl

Vss

SOA

SCL
AOA1 A2WP

1-17

24C02A
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE

Maximum Ratings*

Name

All inputs and outputs w.r.t. Vss ................ -0.3 V to +7 V
Storage temperature ....................... -65"C to +150"C
Ambient temp. with power applied ..... -65"C to + 125"C
Soldering temperature 01 leads (10 seconds) .. +300"C
ESD protection on all pins ................................... .4 kV

Function

AO,Al,A2
Vss
SDA
SCL
WP
Vcc

"Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specification is not
implied. Exposure to maximum rating CQnditions for extended periods
may affect device reliability.

Chip Address Inputs
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+5 V Power Supply

Vee = +5 V (±10%)
Commercial (C): Tamb = O"C to +70"C
Industrial
(I): Tamb = -40"C to +85"C
Automotive (E): Tamb = -40"C to +12S"C

DC CHARACTERISTICS

Parameter

Symbol

Min

Max

Units

Conditions

Vee detector threshold

VTH

2.8

4.5

SCL and SDA pins:
High level input voltage
Low level input voltage
Low level output voltage

VIH
VIL
VOL

Vee x 0.7
-0.3

Vee + 1
Vee x 0.3
0.4

V
V
V

AO, Al & A2 pins:
High level input voltage
Low level input voltage

VIH
VIL

Vee - 0.5
-0.3

Vee + 0.5
0.5

V
V

Input leakage current

III

VIN = 0 V to Vcc

Output leakage current

IOL = 3.2 mA (SDA only)

ILO

VOUT = 0 V to Vee

Internal capacitance
(all inputS/outputs)

CINT

7.0

VINlVoUT = 0 V (Note 1)
TAMS = 25"C, 1 = 1 MHz

Operating current

leeo

3.5

4.25

mA
mA
mA
~

FeLK = 100 kHz, program cycle
time = 2 ms, Vee = 5 V,
Tamb = O"C to 70"C
FeLK = 100 kHz, program cycle
time = 2 ms, Vee = 5 V,
Tamb = (I) and (E)
Vce = 5 V, Tamb = O"C to +70"C
Vee = 5 V, Tamb = (I) and (E)
Vee = 5 V, Tamb = (C), (I) and (E)

program cycle

leew

read cycle

leeR

7.0
8.5
750

Ices

100

Standby current

SDA = SCL = Vee = 5 V
(no PROGRAM active)

Note 1: This parameter is periodically sampled and not 100% tested.

BUS TIMING START/STOP
I
I
I
I
I

SCL~
Tsu,sTA

--i--

SOA

I
I
I
I
I
I

I
I

THD:sTA

Tsu,sro ~

I
I

/1I

I
I
I

STOP

START

DSll1399-2

I
I
I
I
I
I
I
I

1-18

24C02A
AC CHARACTERISTICS
Parameter

Symbol

Min

Typ

Max

Units

100

kHz

Clock frequency

FCLK

Clock high time

THIGH

4000

Clock low time

TLOW

4700

SDA and SCl rise time

1000

SDA and SCl fall time

300

Remarks

START condition hold time

THD:STA

4000

After this period the first
clock pulse is generated

START condition setup time

Tsu:sTA

4700

Only relevant for repeated
START condition

Data input hold time

THD:DAT

Data input setup time

Tsu:DAT

250

TPD

300

Tsu:sTo

4700

TSUF

4700

Data output delay time
STOP condition setup time
Bus free time

Input filter time constant
(SDA and SCl pins)
Program cycle time

ns
3500

.7N

Twc

100

See Note 1

Time the bus must be free
before a new transmission
can start

Byte or Page mode N = #
of bytes to be written

Note 1: As transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min 300
ns) of the falling edge of SCl to avoid unintended generation of START or STOP conditions.

BUS TIMING DATA
SCL

SOA

FUNCTIONAL DESCRIPTION
The 24C02A supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl), controls the bus access, and generates the
START and STOP conditions, while the 24C02A works
as slave. Both, master and slave can operate as trans-

mitter or receiver but the master device determines
which mode is activated.
Up to eight 24C02As can be connected to the bus,
selected by the AO, AI and A2 chip address inputs.
Other devices can be connected to the bus, but require
different device codes than the 24C02A (refer to section
Slave Address).

1-19

OS111398-3

24C02A
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus is
not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (see Figure 1):

Bus not Busy (A)

The data on the line must be changed during the lOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a STARTcondition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.

Both data and clock lines remain HIGH.

Start Data Transfer (B)
A HIGH to lOW transition of the SDA line while the clock
(SCl) is HIGH determines a STARTcondition. All commands must be preceded by a START condition.

Stop Data Transfer (C)
A lOW to HIGH transition of the SDA line while.the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the. data line is stable for the
duration of the HIGH period of the clock signal.

Note: The 24C02A does not generate any acknowledge
bits if an internal programming cycle is in progress.
The device that acknowledges, has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable lOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line HIGH to enable the master to
generate the STOP condition.

FIGURE·1 - DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)

SCL

(8)

(A)

--t---j-,

SDA

START CONDITION

08111398-4

ADDRESS
DATA ALLOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID

1-20

STOP
CONDITION

24C02A
SLAVE ADDRESS
The chip address inputs AO, A 1 and A2 of each 24C02A
must be externally connected to either Vee or ground
(Vss), assigning to each 24C02A a unique 3-bit address.
Up to eight 24C02As may be connected to the bus. Chip
selection is then accomplished through software by
setting the bits AO, A 1 and A2 of the transmitted slave
address to the corresponding hardwired logic levels of
the selected 24C02A.

indicates to the addressed 24C02A that a byte with a
word address will follow after it has generated an acknowledge bit. Therefore, the next byte transmitted by
the master is the word address and will be written into the
address pointer of the 24C02A. After receiving the
acknowledge of the 24C02A, the master device transmits the data word to be written into the addressed
memory location. The 24C02A acknowledges again
and the master generates a STOP condition. This
initiates the internal programming cycle of the 24C02A.
(See Figure 3.)

After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24C02A, followed by the chip address bits AO, A 1 and A2.

PAGE PROGRAM

The eighth bit of slave address determines if the master
device wants to read or write to the 24C02A. (See Figure
2.)

To program the 24C02A, the master sends addresses
and data to the 24C02A which is the slave. (See Figure
3.) This is done by supplying a START condition
followed by the 4-bit device code, the 3-bit slave address, and the RiW bit which is defined as a logic LOW
for a write. This indicates to the addressed slave that a
word address will follow so the slave outputs the acknowledge pulse to the master during the ninth clock
pulse. When the word address is received by the
24C02A, it places it in the lower 8 bits of the address
pointer defining which memory location is to be written.
The 24C02A will generate an acknowledge after every
8 bits received and store them consecutively in a 2-byte
RAM until a STOP condition is detected which initiates
the internal programming cycle. If more than 2 bytes are
transmitted by the master, the 24C02A will terminate the
write cycle. This does not affect erase/write cycles olthe
EEPROM array.

The 24C02A monitors the bus for its corresponding
slave address all the time. It generates an acknowledge
bit if the slave address was true and it is not in a
programming mode.

FIGURE 2 - SLAVE ADDRESS
ALLOCATION

I 11 I I I IAO'l
0

MODE

lithe master generates a.STOP condition after transmitting the first data word (Point 'P' on Figure 3), byte programming mode is entered.

BYTE PROGRAM MODE

The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received (up to two) data bytes will be
written in a serial manner.

In this mode the master sends addresses and one data
byte to the 24C02A.
Following the START condition, the device code (4-bit),
the slave address (3-bit), and the RiW bit, which is logic
LOW, are placed onto the bus by the master. This

The PROGRAM cycle takes N milliseconds, whereby N
is the number of received data bytes (N max = 2).

FIGURE 3 - PROGRAM MODE (ERASEIWRITE)
ACKNOWLEOGES FROM SLAVE

1-21

D5111398-5

24C02A
WRITE PROTECTION
Programming of the upper half of the memory will not
take place if the WP pin of the 24C02A is connected to
Vee (+5 V). The 24C02A will accept slave and word addresses but ifthe memory accessed is write protected by
the WP pin, the 24C02A will not generate an acknowledge after the first byte of data has been received, and
thus the program cycle will not be started when th~ stop
condition is asserted.

READ MODE
This mode illustrates master device reading data from
the 24C02A.
As can be seen from Figure4, the master first sets up the
slave and word addresses by doing a write. (Note:
although this is a read mode the address pOinter must be
written to.) During this period the 24C02A generates the
necessary acknowledge bits as defined in the appropriate section.

The master now generates another START condition
and transmits the slave address again, except this time
the read/write bit is set into the read'mode. After the
slave generates the acknowledge bit, it then outputs the
data from the addressed location on to the SDA pin, increments the address pointer and, if it receives an acknowledge from the master, will transmit the next consecutive byte. This autoincrement sequence is only
aborted when the master sends a STOP condition
instead of an acknowledge.
Note: If the master knows where the address pointer is,
it can begin the read sequence at point 'R' indicated on
Figure 4 and save time transmitting the slave and word
addresses.
Note: In all modes, the address pointer will automatically
increment from the end of the memory block (256 byte)
back to the first location in that block.

FIGURE 4 • READ MODE

RIW

AUTO INCREMENT
WORD ADDRESS

PIN DESCRIPTION
AO. A1 and A2 Chip Address Inputs
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24C02As can be connected to the bus.
These inputs must be connected to either Vss or Vee,

SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses and
data into and data out of the device. It is an open drain
terminal.

of memory (addresses OaQ-OFF) will not be executed.
Read operations are possible.
Iflied to Vss, normal memory operation is enabled (read/
write the entire memory OOQ-OFF).
This feature allows the user to assign the upper half of
the memory as ROM which can be protected against
accidental programming. When write is disabled, slave
address and word address will be acknowledged but
data will not be acknowledged.

Notes:

For normal data transfer SDA is allowed to change only
during SCl lOW. Changes during SCl HIGH are reserved for indicating the START and STOP conditions.

1) A "page" is defined as the maximum number of bytes
that can be programmed in a single write cycle. The
24C02A page is 2 bytes long.

SCL Serial Clock

2) A "block" is defined as a continuous area of memory
with distinct bOundaries. The address pointer can not
cross the boundary from one block to another. It will
however, wrap around from the end of a block to the first
location in the same block. The 24C02A has only one
block (256 bytes).

This input is used to synchronize the data transfer from
and to the device.

WP Write Protection
This pin must be connected to either Vss or Vee.
Iflied to Vee, PROGRAM operations onto the upper half

D5111399-6

1-22

24C02A
NOTES:

1-23

08111398-7

24C02A
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.

PART NUMBERS

J
P

PACKAGE:

SN
SM

I
I

08111398-8

TEMPERATURE
RANGE:

DEVICE:

Blank
I

24C02A
24C02AT

1-24

CERDIP
PLASTIC DIP
PLASTIC SOIC (0.150 mil Body)
PLASTIC SOIC (0.207 mil Body)
0' C to +70' C
-40' C to +85' C
-40' C to +125' C
2K CMOS Serial EEPROM
2K CMOS Serial EEPROM
(in Tape & Reel)

24C02A
DICE FORM

Microchip

2K (256 X 8) CMOS Serial Electrically Erasable PROM
FEATURES

DESCRIPTION

• Low power CMOS technology
Organized as one block of 256 bytes (256 x 8)
Hardware write protect for upper 1k (128 x 8)
Two wire serial interface bus
• 5 volt only operation
Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 2 bytes
• 1ms write cycle time for single byte
• Available in wafer or wafflepack
• Temperature range:
-Commercial: O·C to +70·C

The Microchip Technology Inc 24C02A is a 2K bit
Electrically Erasable PROM. The device is organized as
256 x 8 bit memory with a two wire serial interface.
Advanced CMOS technology allows a significant reduction in power over NMOS serial devices. A special
feature allows a write protection for the upper 1k (128 x
8). The 24C02A also has a page-write capability for up
to 2 bytes of data. Up to eight 24C02As may be
connected to the two wire bus. The 24C02A dice are
available in wafer or wafflepack package.

BLOCK DIAGRAM

DIE CONFIGURATION
Die Size: 106 x 76 mils

Vee .....
Vss .....

Data
Buffer
2x8
(FIFO)

SDA

AOto
A7

1-25

Memory
Array
256 x8

DS11142C-1

24C02A

DICE FORM

ELECTRICAL CHARACTERISTICS

PAD FUNCTION TABLE

MAXIMUM RATINGS·
All inputs and outputs W.r.t. vss ................... -0.3V to +7V
Storage temperature ....................... -65·C to +150'C
Ambient temp. with power applied ..... -65'C to + 125'C
Soldering temperature 01 leads (10 seconds) .. +300'C
ESD protection on all pins ................................... .4 kV
"Notice: Stresses above those listed under "Maximum ratings" may

cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions above

Name

Function

AO, AI, A2
Vss
SDA
SCL
WP
Vee

Chip Address Inputs
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+5 V Power Supply

those indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.

Vee = +5 V (±10%)
Commercial (C): Tamb = O'C to +70'C

DC CHARACTERISTICS
Parameter

Symbol

Min

Max

Units

Vee detector threshold

VTH

2.8

4.5

SCL and SDA pins:
High level input voltage
Low level input voltage
Low level output voltage

VIH
VIL
VOL

Vee x 0.7
-0.3

Vee + 1
Vee x 0.3
0.4

V
V
V

AO, AI & A2 pins:
High level input voltage
Low level input voltage

VIH
VIL

Vee - 0.5
-0.3

Vee + 0.5
0.5

V
V

Conditions

IOL = 3.2 mA (SDA only)

Input leakage current

III

J.lA

VIN = 0 V to Vcc

Output leakage current

ILO

J.lA

VOUT = 0 V to Vcc

Internal capacitance
(all inputs/outputs)

CINT

7.0

VINNoUT = 0 V (Note 1)
T amb = +25'C, 1 = 1 MHz

Operating current

leeo

3.5

program cycle

leew

7.0

FeLK = 100 kHz, program cycle
time = 2 ms, Vee = 5 V,
Vee=5 V

read cycle

leeR

750

J.lA

Vee=5 V

Ices

100

J.LA

SDA = SCL = Vee = 5 V
(no PROGRAM active)

Standby current

Note 1: This parameter is periodically sampled and not 100% tested.

BUS TIMING START/STOP

SCL _ _ _J

SDA

-----n.1

START

DS11142C-2

STOP

1-26

24C02A

DICE FORM

AC CHARACTERISTICS
Parameter

Symbol

Min

Typ

Clock frequency

FCLK

Clock high time

THIGH

4000

TLOW

4700

Clock low time
SDA and SCl rise time

Units

100

kHz

Remarks

ns
ns

SDA and SCl fall time

Max

1000

300

START condition hold time

THD:STA

4000

After this period the first
clock pulse is generated

START condition setup time

TSU:STA

4700

Only relevant for repeated
START condition

Data input hold time

THD:DAT

Data input setup time

TSU:DAT

250

Data output delay time
STOP condition setup time
Bus free time

TPD

300

TSU:STO

4700

TBUF

4700

Noise suppression time constant
(SDA and SCl pins)
Program cycle time

3500

.7N

Twc

100

See Note 1

Time the bus must be free
before a new transmission
can start

Byte or Page mode N
of bytes to be written

BUS TIMING DATA
SCL
THD:DAT (receiver)

T PO

(transmitter)

SDA

transmitter or receiver but the master device determines
which mode is activated.
Up to eight 24C02As can be connected to the bus,
selected by the AO, A1 and A2 chip address inputs.
Other devices can be connected to the bus but require
different device codes than the 24C02A (refer to section
Slave Address).

1-27

DS11142C-3

24C02A

DICE FORM

BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus is not
busy.
During the data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes in
the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (see Figure 1):

Bus not busy CA)

The data on the line must be changed during the lOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOPp condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.

Both data and clock lines remain HIGH.

Start Data Transfer (B)
A HIGH to lOW transition of the SDA line while the clock
(SCl) is HIGH determines a START condition. All
commands must be preceded by a START condition.

Stop Data Transfer (C)
A lOW to HIGH transition of the SDA line while the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

Data Valid CD)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

FIGURE 1 • DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(8)
SCL --+---If--..

SDA

START CONDITION

ADDRESS
DATA ALLOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID

DSl1142C-4

1-28

STOP
CONDITION

24C02A

DICE FORM

SLAVE ADDRESS
The chip address inputs AO, A 1 and A2 of each 24C02A
must be externally connected to either Vee or ground
(VSS) , assigning to each 24C02A a unique 3-bit address.
Up to eight 24C02As may be connected to the bus. Chip
selection is then accomplished through software by
setting the bits AO, A1 and A2 of the transmitted slave
address to the corresponding hardwired logic levels of
the selected 24C02A.

word address will follow after it has generated an acknowledge bit. Therefore, the next byte transmitted by
the master is the word address and will be written into the
address pointer of the 24C02A. After receiving the
acknowledge of the 24C02A, the master device transmits the data word to be written into the addressed
memory location. The 24C02A acknowledges again
and the master generates a STOP condition. This
initiates the internal programming cycle of the 24C02A.
(See Figure 3.)

After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24C02A, followed by the chip address bits AO, A1 and A2.

PAGE PROGRAM MODE

The eighth bit of slave address determines if the master
device wants to read or write to the 24C02A. (See Figure

To program the 24C02A, the master sends addresses
and data to the 24C02A which is the slave (see Figure
3). This is done by supplying a START condition
followed by the 4-bit device code, the 3-bit slave address, and the RIW bit which is defined as a logic LOW
for a write. This indicates to the addressed slave that a
word address will follow so the slave outputs the acknowledge pulse to the master during the ninth clock
pulse. When the word address is received by the
24C02A, it places it in the lower 8 bits of the address
pointer defining which memory location is to be written.
The 24C02A will generate an acknowledge after every
8-bits received and store them consecutively in a 2-byte
RAM until a STOP condition is detected which initiates
the internal programming cycle. If more than 2 bytes are
transmitted by the master, the 24C02Awili terminate the
write cycle. This does not affect erase/write cycles ofthe
EEPROM array.

2.)
The 24C02A monitors the bus for its corresponding
slave address all the time. It generates an acknowledge
bit if the slave address was true and it is not in a programming mode.

FIGURE 2· SLAVE ADDRESS
ALLOCATION
READIWRITE

START

/'
I

:
0

~LAV~ AD9RES:S

: ,
,,
,

IRIWI A

If the master generates a STOP condition after transmitting the first data word (Point 'P' on Figure 3), byte
programming mode is entered.
The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received (up to 2) data bytes will be
written in a serial manner.

BYTE PROGRAM MODE
In this mode, the master sends addresses and one data
byte to the 24C02A.

The PROGRAM cycle takes N milliseconds, whereby N
is the number of received data bytes (N max = 2).

Following the START condition, the device code (4-bit),
the slave address (3-bit), and the Rm bit, which is logic
LOW, are placed onto the bus by the master. This
indicates to the addressed 24C02A that a byte with a

FIGURE 3 . PROGRAM MODE (ERASEIWRITE)

1-29

ACKNOWLEDGES FROM SLAVE

DS11142C-5

24C02A

DICE FORM

WRITE PROTECTION
Programming of the upper half of the memory will not
take place if the WP pad of the 24C02A is connected to
Vcc (+5 V). The 24C02A will accept slave and word
addresses but if the memory accessed is write protected
by the WP pad, the 24C02A will not generate an acknowledge after the first byte of data has been received,
and thus the program cycle will not be started when the
STOP condition is asserted.

READ MODE
This mode illustrates master device reading data from
the 24C02A.
As can be seen from Figure 4, the master first sets up the
slave and word addresses by doing a write. (Note:
Although this is a read mode, the address pointer must
be written to.) During this period the 24C02A generates
the necessary acknowledge bits as defined in the appropriate section.

The master now generates another START condition
and transmits the slave address again, except this time
the read/write bit is set into the read mode. After the
slave generates the acknowledge bit, it then outputs the
data from the addressed location on to the SDA pad,
increments the address pointer and, if it receives an
acknowledge from the master, will transmit the next
consecutive byte. This autoincrement sequence is only
aborted when the master sends a STOP condition
instead of an acknowledge.
Note: If the master knows where the address pointer is,
it can begin the read sequence at point 'R' indicated on
Figure 4 and save time transmitting the slave and word
addresses.
Note: In all modes, the address pointer will automatically
increment from the end of the memory block (256 bytes)
back to the first location in that block.

FIGURE 4 • READ MODE

R/W

AUTO INCREMENT
WORD ADDRESS

PAD DESCRIPTION
AD. A1 and A2 Chip Address Inputs

SCL Serial Clock

The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.

This input is used to synchronize the data transfer from
and to the device.

Up to eight 24C02As can be connected to the bus.
These inputs must be connected to either Vss or Vcc.

SDA Serial Address/Data Input/Output
This is a bidirectional pad used to transfer addresses
and data into and data out of the device. It is an open
drain terminal.
For normal data transfer, SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are reserved for indicating the START and STOP conditions.

DS11142C-6

WP Write Protection
This pad must be connected to either VCC or VSS.
If tied to Vcc, PROGRAM operations onto the upper
memory page (addresses 080-0FF) will not be executed. READ operations are possible.
If tied to Vss, normal memory operation is enabled (readl
write the entire memory OOO-OFF).
This feature allows the user to assign the upper half of
the memory as ROM which can be protected against
accidental programming. When write is disabled, slave
address and word address will be acknowledged but
data will not be acknowledged.

1-30

24C02A

DICE FORM

NOTES:

1-31

DSll142C-7

24C02A

DICE FORM

SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.

PART NUMBERS

W
S

DS11142C-8

O' C

TEMPERATURE
RANGE:

DEVICE:

DICE in WAFER
DICE in WAFFLEPACK

24C02A

1-32

to 70' C

2K CMOS SERIAL EEPROM

24C04A

Microchip

4K (512 X 8) CMOS Serial Electrically Erasable PROM
FEATURES

DESCRIPTION

• Low power CMOS technology
• Organized as two blocks of 256 bytes (2 x 256 x 8)
• Hardware write protect for upper block
Two wire serial interface bus
• 5 volt only operation
• Self-timed write cycle (including auto-erase)
Page-write buffer for up to 8 bytes
1ms write cycle time for single byte
100,000 erase/write cycles
Data retention> 10 years
8-pin DIP or SOIC package
Available for extended temperature ranges:
-Commercial: O·C to +70·C
-Industrial: -40·C to +85·C
-Automotive: -40·C to +85·C

The Microchip Technology Inc. 24C04A is a 4K bit Electrically Erasable PROM. The device is organized as two
blocks of 256 x 8 bit memory with a two wire serial
interface. Advanced CMOS technology allows a significant reduction in power over NMOS serial devices. A
special feature allows a write protection for the upper
256 byte block. The 24C04A also has a page-write capability for up to 8 bytes of data. Up to four 24C04As may
be connected to the two wire bus. The 24C04A is
available in the standard a-pin DIP and a surface mount
SOIC package.

PIN CONFIGURATION

BLOCK DIAGRAM

DIP Package
AO

Vee

SCL

Vss

SDA

SOA

SO Package
AO

Vee

SCL

Vss

SDA

SCL
AO A1 A2WP

1-33

OSll1408-1

24C04A
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE

Maximum Ratings*
All inputs and outputs w.r.t. Vss ................ -0.3 V to +7 V
Storage temperature ....................... -65'C to +150'C
Ambient temp. with power applied ..... -65'C to + 125'C
Soldering temperature 01 leads (10 seconds) .. +300'C
ESD protection on all pins ................................... .4 kV

Name

Function

No Function, Must he
connected to Vee or Vss
Chip Address Inputs
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+5 V Power Supply

Al,A2
Vss
SDA
SCL
WP
Vee

*Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.

Vee = +5 V (±10%)
Commercial (C): Tamb = O'C to +70'C
Industrial
(I): Tamb = -40'C to +85'C
Automotive: (E): Tamb = -40'C to +125'C

DC CHARACTERISTICS

Parameter

Symbol

Min

Max

Units

Vee detector threshold

VTH

2.8

4.5

SCL and SDA pins:
High level input voltage
Low level input voltage
Low level output voltage

VIH
Vil
VOL

Vee x 0.7
-0.3

Vee + 1
Vee x 0.3
0.4

V
V
V

Al & A2 pins:
High level input voltage
Low level input voltage

VIH
Vil

Vee - 0.5
-0.3

Vee + 0.5
0.5

V
V

Conditions

IOl = 3.2 mA (SDA only)

Input leakage current

III

I!A

VIN = 0 V to Vcc

Output leakage current

IlO

I!A

VOUT = 0 V to Vcc

Internal capacitance
(all inputs/outputs)

CINT

7.0

VINlVoUT = 0 V (Note 1)
Tamb = +25'C, 1 = 1 MHz

Operating current

leeo

3.5

rnA

4.25

mA
mA

FelK = 100 kHz, program cycle
time = 2 ms, Vee = 5 V,
Tamb = O'C to +70'C
FelK = 100 kHz, program cycle
time = 2 ms, Vee = 5 V,
Tamb = (I) and (E)
Vee = 5 V, Tamb = O'C to +70'C
Vee = 5 V, Tamb= (I) and (E)
Vee = 5 V, Tamb= (C), (I) and (E)

I!A

program cycle

Iccw

read cycle

leeR

7.0
8.5
750

Ices

100

Standby current

!!A

SDA = SCL = Vee = 5 V
(no PROGRAM active)

Note 1: This parameter is periodically sampled and not 100% tested.

BUS TIMING START/STOP

SCl

SDA

-----+,1
START,

D8111408-2

STOP

1-34

24C04A
AC CHARACTERISTICS
Parameter

Symbol

Min

Clock frequency

FeLK

Clock high time

THIGH

4000

Clock low time

TLOW

4700

SDA and SCl rise time

Typ

Units

100

kHz

Remarks

ns
ns

SDA and SCl fall time

Max

1000

300

ns
ns

START condition hold time

THD:STA

4000

After this period the first
clock pulse is generated

START condition setup time

TSU:STA

4700

Only relevant for repeated
START condition

Data input hold time

THD:DAT

Data input setup time

TSU:DAT

250

Data output delay time
STOP condition setup time
Bus free time

TPD

300

TSU:STO

4700

TBUF

4700

Input filter time constant
(SDA and SCl pins)
Program cycle time

3500

.7N

Twe

100

See Note 1

Time the bus must be free
before a new transmission
can start

Byte or Page mode N = #
of bytes to be written

BUS TIMING DATA
SCL

SDA
_TBUF

FUNCTIONAL DESCRIPTION
The 24C04A supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl), controls the bus access, and generates the
START and STOP conditions, while the 24C04A works
as slave. Both, master and slave can operate as trans-

mitter or receiver but the master device determines
which mode is activated.
Up to four 24C04As can be connected to the bus, selected by the A 1 and A2 chip address inputs. AO must
be tied to Vee or Vss. Other devices can be connected
to the bus but require different device codes than the
24C04A (refer to section Slave Address).

1-35

DS11140B-3

24C04A
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiat'3d only when the bus is not
busy.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as
a START or STOP condition.
Accordingly, the following bus conditions have been defined (see Figure 1):

Bus not Busy (A)

The data on the line must be changed during the lOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.

Both data and clock lines remain HIGH.

Start Data Transfer (B)
A H IG H to lOW transition olthe SDA line while the clock
(SCl) is HIGH determines a START condition. All commands must be preceded by a START condition.

Stop Data Transfer eC)
A lOW to HIGH transition olthe SDA line while the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

Note: The 24C04A does not generate any acknowledge
bits if an internal programming cycle is in progress.
The device that acknowledges, has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable lOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave. by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line HIGH to enable the master to
generate the STOP condition.

FIGURE 1 - DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

SCL

(8)

---+----1h

SDA

START CONDITION

DS111408-4

ADDRESS
DATA ALLOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID

1- 36

STOP
CONDITION

24C04A
SLAVE ADDRESS
word address will follow after it has generate' an acknowledge bit. Therefore the next byte tran"mltted by
the master is the word address and will be writt ..m into the
address pointer of the 24C04A. After rece 'Jing the
acknowledge of the 24C04A, the master devil.e transmits the data word to be written into the addressed
memory location. The 24C04A acknowledges again
and the master generates a STOP condition. This
initiates the internal programming cycle of the 24C04A.
(See Figure 3.)

The chip address inputs Aland A2 of each 24C04A
must be externally connected to either Vee or ground
(Vss), assigning to each 24C04A a unique2-bit address.
Up to four 24C04As may be connected to the bus. Chip
selection is then accomplished through software by
setting the bits A 1 and A2 of the slave address to the
corresponding hardwired logic levels of the selected
24C04A. AO is not used and must be connected to either
Vee or Vss.
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24C04A, followed by the chip address bits A 1 and A2. The seventh bit of that byte (BA)
is used to select the upper block (addresses 100-1 FF)
or lower page (addresses OOO-OFF) of the 24C04A.

PAGE PROGRAM MODE
To program the 24C04A, the master sends addresses
and data to the 24C04A which is the slave (see Figure
3). This is done by supplying a START condition followed by the 4-bit device code, the 3-bit slave address,
and the RiW bit which is defined as a logic LOW for a
write. This indicates to the addressed slave that a word
address will follow so the slave outputs the acknowledge
pulse to the master during the ninth clock pulse. When
the word address is received by the 24C04A, it places it
in the lower 8 bits of the address pointer defining which
memory location is to be written. (The BA bit transmitted
with the slave address is the ninth bit of the address
pOinter.) The 24C04A will generate an acknowledge
after every 8-bits received and store them consecutively
in an 8-byte RAM until a STOP condition is detected
which initiates the internal programming cycle. If more
than 8 by1es are transmitted by the master, the 24C04A
will roll over and overwrite the data beginning with the
first received byte. This does not affect erase/write
cycles of the EEPROM array and is accomplished as a
result of only allowing the address registers bottom 3
bits to increment while the upper 5 bits remain unchanged.

The eighth bit of slave address determines if the master
device wants to read or write tothe 24C04A. (See Figure
2.)
The 24C04A monitors the bus for its corresponding
slave address all the time. It generates an acknowledge
bit if the slave address was true and it is not in a
programming mode.

FIGURE 2 • SLAVE ADDRESS
ALLOCATION
START

READIWRITE

S:LAV~ AD~RES:S

: ,

IRiWl A
\

,
\

If the master generates a STOP condition after transmitting the first data word (Point 'P' on Figure 3), by1e programming mode is entered.

BYTE PROGRAM MODE

The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received (up to eight) data bytes will
be written in a serial manner.

In this mode, the master sends addresses and one data
byte to the 24C04A.
Following the START condition, the device code (4-bit),
the slave address (3-bit), and the Rm bit, which is logic
LOW, are placed onto the bus by the master. This
indicates to the addressed 24C04A that a by1e with a

The PROGRAM cycle takes N milliseconds, whereby N
is the number of received data by1es (N max = 8).

FIGURE 3 • PROGRAM MODE (ERASEIWRITE)

RiW

ACKNOWLEDGES FROM SLAVE

1-37

DS11140B-5

24C04A
WRITE PROTECTION
Programming of the upper half of the memory will not
take place if the WP pin of the 24C04A is connected to
Vce (+5 V). The 24C04A will accept slave and word addresses but if the memory accessed is write protected by
the WP pin, the 24C04A will not generate an acknowledge after the first byte of data has been received, and
thus the program cycle will not be started when the
STOP condition is asserted.

READ MODE
This mode illustrates master device reading data from
the 24C04A.
As can be seen from Figure 4, the master first sets up the
slave and word addresses by doing a write. (Note:
Although this is a read mode, the address pOinter must
be written to.) During this period the 24C04A generates
the necessary acknowledge bits as defined in the appropriate section.

The master now generates another START condition
and transmits the slave address again, except this time
the read/write bit is set into the read mode. After the
slave generates the acknowledge bit, it then outputs the
data from the addressed location on to the SDA pin, increments the address pointer and, if it receives an acknowledge from the master, will transmit the next consecutive byte. This autoincrement sequence is only
aborted when the master sends a STOP condition
instead of an acknowledge.
Note: If the master knows where the address pointer is,
it can begin the read sequence at point 'R' indicated on
Figure 4 and save time transmitting the slave and word
addresses.
Note: In all modes, the address pointer will not increment through a block (256 byte) boundary, but will rotate
back to the first location in that block.

FIGURE 4 - READ MODE

R/W

AUTO INCREMENT
WORD ADDRESS

PIN DESCRIPTION
WP Write Protection
This pin must be connected to either Vee or Vss.

This pin must be connected to either Vcc or Vss.

A1. A2 Chip Address Inputs

If tied to Vcc, PROGRAM operations onto the upper
memory block (addresses 100-1 FF) will not be executed. Read operations are possible.

The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to four 24C04As can be connected to the bus.
These inputs must be connected to either Vss or Vcc.

SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses and
data into and data out of the device. It is an open drain
terminal.

If tied to Vss, normal memory operation is enabled (read/
write the entire memory 000-1 FF).
This feature allows the user to assign the upper half of
the memory as ROM which can be protected against accidental programming. When write is disabled, slave
address and word address will be acknowledged but
data will not be acknowledged.

Notes:

For normal data transfer, SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are reserved for indicating the START and STOP conditions.

1) A "page" is defined as the maximum number of bytes
that can be programmed in a single write cycle. The
24C04A page is 8 bytes long.

SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

D8111408-6

1-38

24C04A
NOTES:

1-39

08111408-7

24C04A
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.

PART NUMBERS

PACKAGE:

J
P
SN
SM

O' C to 70' C
_40' C to 85' C

I ~~~~~~ATURE

DS111408-8

DEVICE:

CERDIP
Plastic DIP
Plastic SOIC (0.150 mil Body)
Plastic SOIC (0.207 mil Body)

24C04A
24C04AT

1-40

4K CMOS Serial EEPROM
4K CMOS Serial EEPROM
(in Tape & Reel)

24C04A
DICE FORM

Microchip

4K (512 X 8) CMOS Serial Electrically Erasable PROM
FEATURES

DESCRIPTION

• Low power CMOS technology
Organized as two blocks of 256 bytes (2 x 256 x 8)
• Hardware write protect for upper block
• Two wire serial interface bus
• 5 volt only operation
Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 1ms write cycle time for single byte
Available in wafer or wafflepack
Temperature range:
-Commercial: O·C to +70·C

The Microchip Technology Inc. 24C04A is a 4K bit
Electrically Erasable PROM. The device is organized as
two blocks of 256 x 8 bit memory with a two wire serial
interface. Advanced CMOS technology allows a significant reduction in power over NMOS serial devices. A
special feature allows a write protection for the upper
256 byte block. The 24C04A also has a page-write
capability for up to 8 bytes of data. Up to four 24C04As
may be connected to the two wire bus. The 24C04A dice
are available in wafer or wafflepack package.

DIE CONFIGURATION

BLOCK DIAGRAM

Die Size: 113 x 76 mils
Data
Buffer

Vcc
Vss __

8x8

f--

AO
A1
A2
Vss

8.
7.
6.
5.

SCL-q

Vcc
WP
SCL
SDA

1-41

do
d i
r n
e t ACto
s e A7
s~

!
t

Control
Logic

Memory
Array
512 x 8

r--

Slave
Address

1.
2.
3.
4.

~RIWAmpl

(FIFO)
Data Reg .

SDA--

....

Increment

12!p

DS11143C-1

24C04A

DICE FORM

ELECTRICAL CHARACTERISTICS

PAD FUNCTION TABLE

Maximum Ratings*
All inputs and outputs W.r.t. Vss
.......... -0.3 V to +7 V
Storage temperature ....................... -65'C to + 150'C
Ambient temp. with power applied ..... -65'C to + 125'C
Soldering temperature 01 leads (10 seconds) .. +300'C
ESD protection on all pins ................................... .4 kV
*Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress rating only and

Name

Function

AO, A1, A2
Vss
SDA
SCL
WP
Vee

Chip Address Inputs
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+5 V Power Supply

may affect device reliability.

Vee = +5 V (±10%)
Commercial (C): Tamb = O'C to +70'C

DC CHARACTERISTICS
Parameter

Symbol

Min

Max

Units

Vee detector threshold

VTH

2.8

4.5

SCL and SDA pins:
High level input voltage
Low level input voltage
Low level output voltage

VIH
VIL
VOL

Vee x 0.7
-0.3

Vee + 1
Vee x 0.3
0.4

V
V
V

AO, A1 & A2 pins:
High level input voltage
Low level input voltage

VIH
VIL

Vee - 0.5
-0.3

Vee + 0.5
0.5

V
V

Conditions

IOL = 3.2 mA (SDA only)

Input leakage current

III

IlA

VIN = 0 V to Vcc

Output leakage current

ILO

IlA

VOUT = 0 V to Vee

Internal capacitance
(all inputs/outputs)

CINT

7.0

VINlVoUT = 0 V (Note 1)
Tamb = +25'C, 1 = 1 MHz

Operating current

leeo

3.5

program cycle

leew

7.0

FeLK = 100 kHz, program cycle
time = 2 ms, Vee = 5 V,
Vee=5 V

read cycle

leeR

750

IlA

Vee=5 V

Ices

100

IlA

SDA = SCL = Vee = 5 V
(no PROGRAM active)

Standby current

Note 1: This parameter is periodically sampled and not 100% tested.

BUS TIMING START/STOP

SCL _ _-..J

soA - - - - - ; , . 1

STOP

START

OS11143C-2

1-42

24C04A

DICE FORM

AC CHARACTERISTICS
Parameter

Symbol

Min

Typ

Max

Units

100

kHz

Clock frequency

FCLK

Clock high time

THIGH

4000

Clock low time

TLOW

4700

SDA and SCl rise time

SDA and SCl fall time

1000

300

Remarks

ns
ns

START condition hold time

THD:STA

4000

After this period the first
clock pulse is generated

START condition setup time

TSU:STA

4700

Only relevant for repeated
START condition

Data input hold time

THD:DAT

Data input setup time

TSU:DAT

250

Data output delay time
STOP condition setup time
Bus free time

TPD

300

TSU:STO

4700

TSUF

4700

Noise suppression time constant
(SDA and SCl pins)
Program cycle time

3500

TI
Twc

.7N

100

See Note 1

Time the bus must be free
before a new transmission
can start

Byte or Page mode N
of bytes to be written

BUS TIMING DATA

SCL

SDA

_TBUF

FUNCTIONAL DESCRIPTION
The 24C04A supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl). controls the bus access, and generates the
START and STOP conditions, while the 24C04A works
as slave. Both, master and slave can operate as
©1990 Microchip Technology Inc.

transmitter or receiver but the master device determines
which mode is activated.
Up to four 24C04A can be connected to the bus, selected by the A1 and A2 chip address inputs. AO must
be tied to Vcc or Vss. Other devices can be connected
to the bus but require different device codes than the
24C04A (refer to section Slave Address).

1-43

DS11143C-3

24C04A

DICE FORM

BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus is not
busy.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as
a START or STOP condition.
Accordingly, the following bus conditions have been
defined (see Figure 1):

Bus not Busy CAl
Both data and clock lines remain HIGH.

Start Data Tansfer CBl
A HIGH to lOW transition of the SDA line while the clock
(SCl) is HIGH determines a START condition. All
commands must be preceded by a START condition.

Stop Data Transfer (C)
A lOW to HIGH transition olthe SDA line while the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

Data Valid (D)
The state of the data line represents valid data when,
after a start condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the lOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.

Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note: The 24C04A does not generate any acknowledge
bits if an internal programming cycle is in progress.
The device that acknowledges, has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable lOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line HIGH to enable the master to
generate the STOP condition.

FIGURE 1· DATA TRANSFER SEQUENCE ON THE

(A)
(8)
SCL - - j . -__h

SDA

START CONDITION

DS11143C-4

ADDRESS
DATA ALLOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID

1-44

STOP
CONDITION

24C04A

DICE FORM

SLAVE ADDRESS
The chip address inputs A 1 and A2 of each 24C04A
must be externally connected to either Vee or ground
(Vss), assigning to each 24C04A a unique 2-bit address.
Up to four 24C04As may be connected to the bus. Chip
selection is then accomplished through software by
setting the bits A 1 and A2 of the slave address to the
corresponding hardwired logic levels of the selected
24C04A. AO is not used and must be connected to Vee
or Vss.

indicates to the addressed 24C04A that a by1e with a
word address will follow after it has generated an acknowledge bit. Therefore, the next byte transmitted by
the master is the word address and will be written into the
address pOinter of the 24C04A. After receiving the
acknowledge of the 24C04A, the master device transmits the data word to be written into the addressed
memory location. The 24C04A acknowledges again
and the master generates a STOP condition. This
initiates the internal programming cycle of the 24C04A.
(See Figure 3.)

After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24C04A, followed by the chip address bits A1 and A2. The seventh bit of that by1e (PA)
is used to select the upper page (addresses 100-1 FF)
or lower page (addresses OOO-OFF) of the 24C04A.

PAGE PROGRAM MODE
To program the 24C04A, the master sends addresses
and data to the 24C04A which is the slave (see Figure
3). This is done by supplying a START condition
followed by the 4-iJit device code, the 3-bit slave address, and the RiW bit which is defined as a logic LOW
for a write. This indicates to the addressed slave that a
word address will follow so the slave outputs the acknowledge pulse to the master during the ninth clock
pulse. When the word address is received by the
24C04A, it places it in the lower 8 bits of the address
pointer defining which memory location is to be written.
(The PA bit transmitted with the slave address is the
ninth bit of the address pointer.) The 24C04A will
generate an acknowledge after every 8-bits received
and store them consecutively in an 8-byte RAM until a
STOP condition is detected which initiates the internal
programming cycle. If more than 8 bytes are transmitted
by the master, the 24C04A will roll over and overwrite the
data beginning with the first received byte. This does not
affect erase/write cycles of the EEPROM array and is
accomplished as a result of only allowing the address
registers bottom 3 bits to increment while the upper 5 bits
remain unchanged.

The eighth bit of slave address determines if the master
device wants to read or write to the 24C04A. (See Figure
2.)
The 24C04A monitors the bus for its corresponding
slave address all the time. It generates an acknowledge
bit if the slave address was true and it is not in a
programming mode.

FIGURE 2 • SLAVE ADDRESS
ALLOCATION
START

READIWRITE

S~AV~ AD~RES:S :

lR1W1

If the master generates a STOP condition aftertransmitting the first data word (Point 'P' on Figure 3), byte
programming mode is entered.

BYTE PROGRAM MODE

The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received (up to eight) data bytes will
be written in a serial manner.

In this mode the master sends addresses and one data
byte to the 24C04A.
Following the START condition, the ~vice code (4-bit),
the slave address (3-bit), and the RIW bit, which is logic
LOW, are placed onto the bus by the master. This

The PROGRAM cycle takes N milliseconds, whereby N
is the number of received data by1es (N max; 8).

FIGURE 3 . PROGRAM MODE (ERASEIWRITE)

R/W

ACKNOWLEDGES FROM SLAVE

1-45

DS11143C-5

24C04A

DICE FORM

WRITE PROTECTION
Programming of the upper half of the memory will not
take place if the WP pad of the 24C04A is connected to
Vcc (+5 V). The 24C04A will accept slave and word
addresses but if the memory accessed is write protected
by the WP pad, the 24C04A will not generate an acknowledge after the first byte of data has been received,
and thus the program cycle will not be started when the
STOP condition is asserted.

READ MODE
This mode illustrates master device reading data from
the 24C04A.
As can be seen from Figure 4, the master first sets up the
slave and word addresses by doing a write. (Note:
Although this is a read mode, the address pointer must
be written to.) During this period the 24C04A generates
the necessary acknowledge bits as defined in the appropriate section.

The master now generates another START condition
and transmits the slave address again, except this time
the read/write bit is set into the read mode. After the
slave generates the acknowledge bit, it then outputs the
data from the addressed location on to the SDA pad,
increments the address pointer and, if it receives an
acknowledge from the master, will transmit the next
consecutive byte. This autoincrement sequence is only
aborted when the master sends a STOP condition
instead of an acknowledge.
Note: .If the master knows where the address pointer is,
it can begin the read sequence at pOint 'R' indicated on
Figure 4 and save time transmitting the slave and word
addresses.
Note: In all modes, the address pointer will never
automatically increment through a block (256 byte)
boundary but will rotate back to the first location in that
block.

FIGURE 4 - READ MODE

RIW

AUTO INCREMENT
WORD ADDRESS

PAD DESCRIPTION
SCl Serial Clock
This pad must be connected to either Vcc or Vss.

A1. A2 Chip Address Inputs
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to four 24C04As can be connected to the bus.
These inputs must be connected to either vss or Vcc.

SDA Serial Address/Data Input/Output
This is a bidirectional pad used to transfer addresses
and data into and data out of the device. It is an open
drain terminal.
For normal data transfer SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are reserved for indicating the START and STOP conditions.

DS11143C-6

This input is used to synchronize the data transfer from
and to the device.

WP Write Protection
This pad must be connected to either Vcc or Vss.
If tied to Vcc, PROGRAM operations onto the upper
memory block (addresses 100-1FF) will not be executed. Read operations are possible.
If tied to Vss, normal memory operation is enabled (read/
write the entire memory 000-1 FF).
This feature allows the user to assign the upper half of
the memory as ROM which can be protected against
accidental programming. When write is disabled,slave
address and word address will be acknowledged but
data will not be acknowledged.

1-46

24C04A

DICE FORM

NOTES:

1-47

DS11143C-7

24C04A

DICE FORM

SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.

PART NUMBERS

W
S

TEMPERATURE
RANGE:

DEVICE:

DICE in WAFER
DICE in WAFFLEPACK

O' C

24C04

to 70' C

4K CMOS SERIAL EEPROM

DS11143C-8

1-48

59C11

Microchip

lK (128 x 8 or 64 x 16) CMOS Serial Electrically Erasable PROM

FEATURES

DESCRIPTION

Low power CMOS technology
• Pin selectable memory organization
- 128 x 8 or 64 x 16 bit organization
• Single 5 volt only operation
• Self timed WRITE, ERAL and WRAL cycles
Automatic erase before WRITE
• RDY/BSY status information during WRITE
• Power on/off data protection circuitry
• 100,000 ERASEIWRITE cycles
• Data Retention> 10 Years
8-pin DIP or SOIC package
Available for extended temperature ranges:
- Commercial: O·C to +70·C
-Industrial: -40·C to +85·C
- Automotive: -40·C to + 125·C

The Microchip Technology Inc. 59Cll is a 1K bit Electrically Erasable PROM. The device is configured as
128 x 8 or 64 x 16, selectable externally by means of the
control pin ORG. Advanced CMOS technology makes
this device ideal for low power non-volatile memory applications. The 59C 11 is available in the standard 8-pin
DIP and a surface mount SOIC package.

BLOCK DIAGRAM

PIN CONFIGURATION

esOs
DIP Package

elK

013
DO

Vee

Vas

Vee
RDYfBSY

eRG

SORG
5

Vss

esOs

SO Package

Vee

elK

ADY/BSY

SORG

elK

Vss

1-49

DS20040C-1

59C11
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE

Maximum Ratings*

Name

All inputs and outputs w.r.t. Vss ............. -0.3 V to +7.0 V
Storage temperature ............................ -65"C to. + 150"C
Ambient temperature with
power applied ........................................ 65·C to +125·C
Soldering temperature 01 leads (10 seconds) .... +300·C
ESD protection on all pins ..................................... .4 kV

Function

CS
ClK
DI
DO
Vss
ORG
RDY/BSY
Vee

*Notice: Stresses above those listed under "Maximum ratings" may

cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.

Chip Select
Serial Clock
Data In
Data Out
Ground
Memory Array Organization
Ready/Busy Status
+5 V Power Supply

Vee; +5 V (±10%)
Commercial: Tamb; O°C to +70°C
Industrial:
Tamb ; -40°C to +85°C
Automotive: Tamb; -40°C to +125°C

DC CHARACTERISTICS

Parameter

Symbol

Min

Max

Units

Vee detector threshold

VTH

2.8

4.5

High level input voltage

VIH

2.0

Vee + 1

low level input voltage

Vil

-0.3

0.8

High level output voltage

VOH

2.4

low level output voltage

Conditions

IOH ; -400 IlA
IOl; 3.2 mA

VOL

0.4

Input leakage current

III

IlA

VIN ; 0 V to Vee (Note 1)

Output leakage current

ILO

IlA

VOUT ; 0 V to Vee (Note 1)

Internal capacitance
(all inputs/outputs)

CINT

VINlVoUT ; OV (Note 2)
Tamb ; 25"C, 1 ; 1 MHz

Operating current
(all modes)

leeo

FelK ; 1 MHz, Vec ;5.5 V

Standby current

Ices

100

f.lA

CS; 0 V, Vee; 5.5 V

Note 1: Internal resister pull-up at Pin 6. Active output at Pin 7.
Note 2: This parameter is periodically sampled and not 100% tested.

SYNCHRONOUS DATA TIMING

elK

DS20040C-2

1-50

59C11
AC CHARACTERISTICS
Parameter

Symbol

Min

Max

Units

MHz

Clock frequency

FCLK

Clock high time

TCKH

500

Clock low time

TCKL

500

Chip select setup time

Tcss

Chip select hold time

TCSH

Chip select low time

Tcs

100

Data input setup time

To IS

100

Data input hold time

TOIH

100

Data output delay time

Tpo

Data output disable time (from CS = low)

Tcz

Conditions

ns
400

Cl = 100pF

100

Cl=100pF

Cl = 100 pF

Data output disable time (from last clock)

Tooz

400

RDY/BSY delay time

TRBO

400

Program cycle time (Auto Erase & Write)

Twc

1
15

ms
ms

for 8-bit mode
for ERAl and WRAl
in 8/16-bit modes

PIN DESCRIPTION
Chip Select (CS)
ClK cycles are not required during the self-timed WRITE
(I.e., auto erase/write) cycle.

A HIGH level selects the device. A lOW level deselects
the device and forces it into standby mode. However, a
WRITE cycle which is already initiated and/or in progress will be completed, regardless of the CS input signal.
If CS is brought lOW during a WRITE cycle, the device
will go into standby mode as soon as the WRITE cycle
is completed.

Alter detection of a START condition the specified number of clock cycles (respectively lOW to HIGH transitions of ClK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (see instruction set truth table). When that limit has been reached,
ClK and 01 become "Don't Care" inputs until CS is
brought lOW for at least chip select low time (TCSL) and
brought HIGH again and a WRITE cycle (if any) is completed.

CS must be lOW for 100 ns (TCSL) minimum between
consecutive instructions. If CS is lOW, the internal
control logic is held in a RESET status.

Serial Clock (ClK)
The Serial Clock is used to synchronize the communication between a master device and the 59C11. Opcode, address, and data bits are clocked in on the
positive edge of ClK. Data bits are also clocked out on
the positive edge of ClK.

Data In (01)
Data In is used to clock in START bit, opcode, address
and data synchronously with the ClK input.

Data Out (~O)

ClK can be stopped anywhere in the transmission
sequence (at HIGH or lOW level) and can be continued
anytime (with respectto clock high time (TCKH) and clock
low time (TCKL)). This gives freedom in preparing
opcode, address and data for the controlling master.

Data Out is used in the READ mode to output data
synchronously with the ClK input (Tpo alter the positive
edge of ClK). This output is in HIGH-Z mode except if
data is clocked out as a result of a READ instruction.
01 and DO can be connected together to perform a 3wire interface (CS, ClK, 01/00).

ClK is a "Don't Care" if CS is lOW (device deselected).
If CS is HIGH, but a START condition has not been
detected, any number of clock cycles can be received by
the device without changing its status (I.e., waiting for
START condition).

Care must be taken with the leading dummy zero which
is output alter a READ command has been detected.
Also, the controlling device must not drive the DI/DObus
during WRITE cycles.
DS20040C-3

1-51

59C11
Organization (ORG>

DATA PROTECTION

This input selects the memory array organization. When
the ORG pin is connected to +5 V the 64 x 16 organization is selected. When it is connected to ground, the 128
x 8 organization is selected. If the ORG pin is left unconnected, then an internal pullup device will select the 64
x 16 organization.

During power-up, all modes of operation are inhibited
until Vee has reached a level of between 2.8 V and 4.5
V. During power-down, the source data protection circuitry acts to inhibit all modes when VCC has fallen
below the voltage range of 2.8 V to 4.5 V.
The EWEN and EWDS commands give additional protection against accidentally programming during normal
operation.

Ready/Busy (ROY/BSY)
Pin 7 provides RDY/BSY status information. RDY/BSY
is low if the device is performing a WRITE, ERAl, or
WRAl operation. When it is HIGH the internal, selftimed WRITE, ERAl or WRAl operation has been completed and the device is ready to receive a new instruction.

INSTRUCTION SET

Instruction

Start
Bit

READ
WRITE
EWEN
EWDS
ERAL
WRAL

1
1
1
1
1
1

After power-up, the device is automatically in the EWDS
mode. Therefore, EWEN instruction must be performed
before any WRITE, ERAl or WRAl instruction can be
executed.

64 X 16 MODE, ORG=1

Address

Opcode
1
X
0
0
0
0

0
1
0
0
0
0

AS A4 A3 A2
AS A4 A3 A2
X X X X
X X X X
X X X X
X X X X

X
X
1
0
0
1

X
X
1
0
1
0

A1
A1
X
X
X
X

AO
AD
X
X
X
X

Data In

Data Out

Number of
Req. ClK Cycles

D1S- DO
High-Z
High-Z
High-Z
High-Z
High·Z

27
27
11
11
11
27

D1S-DO

D1S- DO

128 X 8 MODE, ORG=O
Instruction
READ
WRITE
EWEN
EWDS
ERAL
WRAL

Start
Bit
1
1
1
1
1
1

Opcode
1
X
0
0
0
0

0
1
0
0
0
0

X
X
1
0
1
0

Address
X
X
1
0
0
1

A6
A6
X
X
X
X

AS
AS
X
X
X
X

A4 A3 A2 A1
A4 A3 A2 AI
X X X X
X X X X
X X X X
X X X X

AO
AO
X
X
X
X

Data In

Data Out

07-00
High-Z
High-Z
High-Z
High-Z
High-Z

07 -DO

D1S - DO

Number of
Req. ClK Cycles
20
20
12
12
12
20

FUNCTIONAL DESCRIPTION
START Condition
The START bit is detected by the device if CS and 01 are
both High with respect to the positive edge of ClK for the
first time.
Before a START condition is detected, CS, ClK, and 01
may change in any combination (except to that of a
START condition) without resulting in any device operation (READ, WRITE, EWEN, EWDS, ERAl, and WRAl).
As soon as CS is HIGH, the device is no longer in the
standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address and
data bits for any particular instruction is clocked in.
After execution of an instruction (i.e. clock in or out of the

DS20040C-4

last required address or data bit) ClK and 01 become
don't care bits until a new start condition is detected.
Note: CS must go lOW between consecutive instructions.

01/00 Pins
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a "bus conflict" to occur during the "dummy zero" that
precedes the READ operation, if AO is a logic high level.
Under such a condition the voltage level seen at Data
Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
AO. The higher the current sourcing capability of AO, the
higher the voltage at the Data Out pin.

1-52

59C11
READ Mode
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy bit
(logical 0) precedes the 8- or 1S-bit output string. The
output data changes during the high state of the system
clock (ClK). The dummy bit is output TPD after the
positive edge of ClK, which was used to clock in the last
address bit (AO). Therefore, care must be taken if 01 and
DO are connected together as a bus contention will
occur for one clock cycle if AO is a one.

READ MODE

DO will go into HIGH-Z mode with the positive edge of
the next ClK cycle. This follows the output of the last
data bit DO orthe negative edge of CS, whichever occurs
first. DO remains stable between ClK cycles for an unlimited time as long as CS stays HIGH.
The most significant data bit (015 or 07) is always output
first, followed by the lower significant bits (014 - DO or OS
- DO).

CLK
~

01_

IIJ
ISB\ J \

Sf
OPCODE

! &IlK
x

sr-LT

I
I AO

wr mj'('Ix ~_~
/
~I

DO - - - - - - - - - - HIGH·Z

TPD~

r--

I I

NOTE:

~TDDZ~

ro;=x:J"~

r-~~--+~~~-I

NEW INSTRUCTION
OR STANDBY (CS 0 0)

WRITE
The WRITE instruction is followed by 8 or 1S bits of data
which are written into the specified address. The most
significant data bit (015 or 07) has to be clocked in first
followed by the lower significant data bits (014 - DO or
OS - DO). If a WRITE instruction is recognized by the
device and all data bits have been clocked in, the device

WRITE MODE

CLK

performs an automatic erase cycle on the specified
address before the data are written. The WRITE cycle
is completely self timed and commences automatically
after the rising edge oflhe ClK signal for the last data bit
(~O).

The WRITE cycle takes 1 ms max for S-bit mode and 2
ms max for 1S-bit mode.

"""""",ow......J

Tcs,~

~ -~--7n----------------~~~.----~~~:~~~~
OPCODE

I DO

1XlI1x

4==

~£>m---'{
I

Twc

r-~~-_+~4_~

NEW INSTRUCTION
OR STANDBY (CS. 0)

1-53

DS2004OC-5

59C11
ERASEIWRITE Enable/Disable (EWEN, EWDS)
instruction has to be performed before any WRITE,
ERAL, or WRAL instruction is executed by the device.

The device is automatically in the ERASEIWRITE Disable mode (EWDS) after power-up. Therefore, EWEN

ERASEIWRITEENABLE
AND DISABLE

ClK

=-zz;

~
~ TCSL

---l
--~~------------------------~~------~

Y=---=---=~~""""---~
Ewes

x
EWEN
DO - - - - - - - - - - - - - - - - HIGH· Z - - - - - - - ' ; - - - - - - - - - - - - - - - - - , - - - - NOTE:

f-'-c-::::---::---+-:-:-l
NEW INSTRUCTION
OR STANDBY ICS" 0)

ERASE All (ERAl)
mode. The ERAL cycle is completely self-timed and
commences after the rising edge of the eLK signal for
the last dummy address bit. ERAL takes 15 ms max.

The entire chip will be erased to logical "1 s" if this instruction is received by the device and it is in the EWEN

ERASE ALL
(CHIP ERASE)

ClK

~,m1j~in&0~01

.L.tl<=lL..J
TCSH

=--zz;

l.--.-

----..I

~:~~
Ao I,

OPCOoE

S8
01

o
DO - - - - - - - - - - - - - - - - - HIGH· Z

I...- TCSL

-.J

x mx~~/
I

-----is

~TR8D

-¥

RDY/BSY ---------------------------ff~

0-----i}---/1

I
I..

.,
Twc

64 x 16

NEW INSTRUCTION

OR STANDBY ICS " 0)

WRITE All (WRAL)
The entire chip will be written with the data specified in
that command. The WRAL cycle is completely selftimed and commences after the last data bit (DO) has
been clocked in. WRAL takes 15 ms max.

WRITE ALL

ClK

Note: The WRAL does not include an automatic ERASE
cycle for the chip. Therefore, the WRAL instruction must
be preceded by an ERAL instruction and the chip must
be in the EWEN status in both cases. The WRAL instruction is used for testing and/or device initialization.

~Lr1JLrlSL~IUl~'"
TCSH

~
AN

OPCOOE

~ ____I

.;.-

TCSl

f@;§_t-

:
100

~;mm;@;

DO - - - - - - - - - - - - - - - HIGH· Z

fi
S8

--------------)(~5---L1----_;\_~- - - - - , 'TRBO~ ~

,..,
..I - -____- - I.~:
.

RDYiBSY--------,~~
NOTE:

ORGANIZATION
128 x 8
64 x 16

Twc

A6
A5

07
015

NEW INSTRUCTION
OR STANDBY (CS = 0)

~~---------------

DS20040C-6

1-54

59C11
NOTES:

1-55

DS20040C-7

59C11
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.

PART NUMBERS

Package:

'1 Temperature
Range:

J
P
SN
SM

Blank
I

DS20040C·8

Device:

59CII
59CI1T

1·56

CERDIP
Plastic DIP
Plastic SOIC (0.150 mil Body)
Plastic SOIC (0.207 mil Body)

O°Cto +70° C
-40° C to +85° C
-40° C to +125° C

I K CMOS Serial EEPROM
I K CMOS Serial EEPROM
(In Tape &.Reel)

59C11
DICE FORM

Microchip

1K (128 x 8 or 64 x 16) CMOS Serial Electrically Erasable PROM

FEATURES

DESCRIPTION

• Low power CMOS technology
• Pad selectable memory organization
- 128 x 8 or 64 x 16 bit organization
• Single 5 volt only operation
• Self-timed write, ERAL and WRAL cycles
• Automatic erase before write
RDY/BSY status information during write
• Power on/off data protection circuitry
• Available in wafer or wafflepack
• Temperature range:
- Commercial: O'C to +70'C

The Microchip Technology Inc. 59Cll is a 1K bit Electrically Erasable PROM. The device is configured as
128 x 8 or 64 x 16, selectable externally by means of the
control pad ORG. Advanced CMOS technology makes
this device ideal for low power non-volatile memory applications. The 59Cll dice are available in wafer or
wafflepack.

DIE CONFIGURATION

BLOCK DIAGRAM

Die Size: 88 x 78 mils.
Vee

1. CS

6. Vee

2. ClK

7. ROY/BSY
6.0RG

3.01
4.00

Vss

5. Vss

1-57

OS20043C-1

59C11

DICE FORM

ELECTRICAL CHARACTERISTICS

PAD FUNCTION TABLE

Maximum Ratlngs*

Name

All inputs and outputs w.r.t. Vss .............. -0.3 V to +7.0 V
Storage temperature ............................ -6S'C to +1S0'C
Ambient temperature with
power applied ...................................... -6S'C to +12S'C
Soldering temperature of leads (10 seconds) .... +300·C
ESD protection on all pins ..................................... .4 kV

CS
ClK
DI
DO
vss
ORG
RDY/BSY
Vee

'Notice: Stresses above those listed under "Maximum ratings' may
cause permanent damage to the device. This is a stress rating only and
lunctional operation 01 the device at those or any other conditions above
those indicated in the operational listings 01 this specification is not
implied. Exposure to maximum rating conditions lor extended periods
may affect device reliability.

Chip Select
Serial Clock
Data In
Data Out
Ground
Memory Array Organization
Ready/Busy Status
+S V Power Supply

Vee = +S V (±10%)
Commercial: Tamb = O°C to +70°C

DC CHARACTERISTICS
Parameter

Function

Symbol

Min

Vee detector threshold

VTH

2.8

4.S

High level input voltage

VIH

2.0

Vee + 1

low level input voltage

VIL

-0.3

0.8

High level output voltage

VOH

2.4

IOH = -400

low level output voltage

VOL

0.4

IOL= 3.2 mA

III

VIN = 0 V to Vee (Note 1)

ILO

i!A
i!A

CINT

VINIVOUT = 0 V (Note 2)
Tamb = 2S'C, f = 1 MHz

Input leakage current
Output leakage current
Internal capacitance
(all inputS/outputs)

Max

Units

Conditions

i!A

VOUT = 0 V to Vee (Note 1)

Operating current (all modes)

leeo

FeLK = 1 MHz, Vee = S.S V

Standby current

Ices

100

CS = 0 V, Vee = S.S V

Note 1: Internal resistor pull-up at Pin 6. Active output at Pin 7.
Note 2: This parameter is periodically sampled and not 100% tested.

SYNCHRONOUS DATA TIMING

CLK

OS20043C-2

1-58

59C11

DICE FORM

AC CHARACTERISTICS
Parameter

Symbol

Min

Max

Units

MHz

Clock frequency

FClK

Clock high time

TCKH

500

Clock low time

TCKl

500

Conditions

Chip select setup time

Tcss

Chip select hold time

TCSH

Chip select low time

Tcs

100

Data input setup time

TOls

100

Data input hold time

TOIH

100

Data output delay time

Tpo

400

Cl = 100 pF

Data output disable time (from CS = low)

Tcz

100

Cl = 100 pF

Data output disable time (from last clock)

Tooz

400

Cl = 100 pF

400

1
15

ms
ms

RDY/BSY delay time

TRBO

Program cycle time (Auto Erase & Write)

Twc

for 8-bit mode
for ERAl and WRAl in
8/16-bit modes

PAD DESCRIPTION

the device without changing its status (i.e., waiting for
START condition).

Chip Select (CS)

ClK cycles are not required during the self-timed WRITE
(i.e. auto erase/write) cycle.

A HIGH level selects the device. A lOW level deselects
the device and forces it into standby mode. However, a
WRITE cycle which is already initiated and/or in progress will be completed, regardless olthe CS input signal.
If CS is brought lOW during a WRITE cycle, the device
will go into standby mode as soon as the WRITE cycle
is completed.
CS must be lOW for 100 ns (TCSl) minimum between
consecutive instructions. If CS is lOW, the internal
control logic is held in a RESET status.

After detection of a START condition the specified number of clock cycles (respectively lOW to HIGH transitions of ClK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (see instruction set truth table). When that limit has been reached,
ClK and 01 become don't care inputs until CS is brought
lOW for at least chip select low time (Tcsl) and brought
HIGH again and a WRITE cycle (if any) is completed.

Serial Clock (ClK>

Data In (Oil

The Serial Clock is used to synchronize the communication between a master device and the 59Cll. Opcode, address, and data bits are clocked in on the
positive edge of ClK. Data bits are also clocked out on
the positive edge of ClK.

Data In is used to clock in START bit, opcode, address
and data synchronously with the ClK input.
Data Out (DO)
Data Out is used in the READ mode to output data
synchronously with the ClK input (Tpo after the positive
edge of ClK). This output is in HIGH-Z mode except if
data is clocked out as result of a READ instruction.

ClK can be stopped anywhere in the transmission
sequence (at HIGH or lOW level) and can be continued
anytime (with respect to clock HIGH time (TCKH) and
clock lOW time (TCKl)). This gives freedom in preparing opcode, address and data for the controlling master.

DI and DO can be connected together to perform a 3wire interface (CS, ClK, DilDO).
Care must be taken with the leading dummy zero which
is output after a READ command has been detected.
Also, the controlling device must not drive the DilDO bus
during WRIT.E cycles.

ClK is a "Don't Care" if CS is lOW (device deselected).
If CS is HIGH, but a start condition has not been
detected, any number of clock cycles can be received by

DS20043C-3

1-59

59C11

DICE FORM

Organization (ORG>

DATA PROTECTION

This input selects the memory array organization. When
the ORG pad is connected to +5 V the 64 x 16 organization is selected. When it is connected to ground, the 128
x 8 organization is selected. If the ORG pad is left unconnected, then an internal pullup device will select the 64
x 16 organization.

During power-up all modes of operation are inhibited
until Vee has reached a level of between 2.8 Vand 4.5 V.
During power-down the source data protection circuitry
acts to inhibit all modes when Vee has fallen below the
voltage range of 2.8 V to 4.5 V.
The EWEN and EWDS commands give additional protection against accidentally programming during normal
operation.

Ready/Busy (ROY/BSY)
Pad 7 provides RDY/BSY status information. RDY/BSY
is low if the device is performing a WRITE, ERAL, or
WRAL operation. When it is HIGH, the internal selftimed WRITE, ERAL orWRAL operation has been completed and the device is ready to receive a new instruction.

INSTRUCTION SET

After power-up the device is automatically in the EWDS
mode. Therefore, EWEN instruction must be performed
before any WRITE, ERAL or WRAL instruction can be
executed.

64 X 16 MODE, ORG=1

Instruction
READ
WRITE
EWEN
EWDS
ERAL
WRAL

1
1
1
1
1
1

Opcode
1 0 X X
X 1 X X

0
0
0
0

0 1 1
0 0 0
0 1 0
0 0 1

Data In

Address
AS A4 A3 A2
AS A4 A3 A2

AI
AI

AO
AO

X
X
X
X

D1S- DO

DIS-DO

Data Out
DIS-DO
High-Z
High·Z
High-Z
High-Z
High-Z

Rei!. ClK Cycles
27
27
11
11
11
27

128 X 8 MODE, ORG=O

r-Instruction

Number of

Start
Bit

READ
WRITE
EWDS
~N
ERAL
WRAL

Start
Bit
1
1
1
1
1
1

Number of
Opcode
1 0 X X
X 1 X X
0 0 1 1
0 0 0 0
0 0 1 0
0 0 0 1

Address
AS AS A4 A3 A2 AI
AS AS A4 A3 A2 AI
X X X X X X
X X X X X X
X X X X X X
X X X X X X

FUNCTIONAL DESCRIPTION
START Condition
The START bit is detected by the device if CS and DI are
both HIGH with respect to the positive edge of CLK for
the first time.
Before a START condition is detected, CS, ClK and DI
may change in any combination (except to that of a
START condition) without resulting in any device operation (READ, WRITE, EWEN, EWDS, ERAL, and WRAL).
As soon as CS is HIGH, the device is no longer in the
standby mode.
An instruction following a START condition will only be
executed if the required amount of opcQde, address and
data bits for any particular instruction is clocked in.

DS20043C-4

Data In
AD
AO
X
X
X
X

D7 -DO

D7-DO

Data Out
D7-DO
High-Z
High-Z
High-Z
High-Z
High-Z

Req. ClK Cycles
20
20
12
12
12
20

After execution of an instruction (i.e. clock in or out of the
last required address or data bit) CLK and DI become
"don't care" bits until a new start condition is detected.
Note:
CS must go LOW between consecutive instructions.

01/00 Pads
It is possible to connect the Data In and Data Out pads
together. However, with this configuration it is possible
for a "bus conflict" to occur during the "dummy zero" that
precedes the READ operation, if AO is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
AO. The higher the current sourcing capability of AO, the
higher the voltage at the Data Out pad.

1-60

59C11

DICE FORM

READ Mode
The READ instruction outputs the serial data of the
addressed memory location on the DO pad. A dummy
bit (logical 0) precedes the 8/16-bit output string. The
output data changes during the HIGH state olthe system
clock (ClK). The dummy bit is output TPD after the
positive edge of ClK, which was used to clock in the last
address bit (AO). Therefore, care must betaken if 01 and
DO are connected together as a bus contention will
occur for one clock cycle if AO is a one.

READ MODE

DO will go into HIGH-Z mode with the positive edge of
the next ClK cycle. This follows tile output of the last
data bit DO or the low going edge of CS, whichever occurs first. DO remains stable between ClK cycles for an
unlimited time as long as CS stays HIGH.
The most significant data bit (015 or 07) is always output
first, followed by the lower significant bits (014 - DO or 06
-~O).

ClK

01_

!II

Sfl

SB
I\.r\

OPCODE

m:m:
x

I AO

I '

~~ ]i§l8888888888!§Wll~

TPD _ _

DO----------HGH·Z

t--

~TDDZ~

~~IO~~
I I

NEW INSTRUCTION
OR STANDBY (CS - 0)

WRITE Mode
performs an automatic erase cycle on the specified
address before the data are written. The WRITE cycle is
completely self timed and commences automatically
after the last data bit (~O) has been clocked in.

The WRITE instruction is followed by 8 or 16 bits of data
which are written into the specified address. The most
significant data bit (015 or 07) has to be clocked in first
followed by the lower significant data bits (014 - DO or
06 - ~O). If a WRITE instruction is recognized by the
device and all data bits have been clocked in, the device

WRITE MODE'

The WRITE cycle takes 1 ms for 8-bit mode and 2 ms for
16-bit mode max.

ClK
1>AOl!I.16IlOO"---J

TcsL.....-l
CS

-~-'TTT------------:\ss>---~ss--1----o<>W~-~
I

Ola

OPCOOE

L
I

r\D/\I\/\a$~m~ _~
,

I
DO - - - - - - - - - HIGH· Z - - - - , l l f f - - ' - - - - - ! S S I l - - . I - - : - - - - - - -

__I TRso t.-

11 I \'-----lIS~-.{

ROY/BSY

"I
NEW INSTRUCTION
OR STANDBY (CS = 0)

1-61

0520043C-5

59C11

DICE FORM

ERASEIWRITE Enable/Disable (EWEN,EWDSl
The device is automatically in the ERASE/WRITE Disable mode (EWOS) after power-up. Therefore, EWEN

instruction has to be performed before any WRITE,
ERAL, or WRAL instruction is executed by the device.

ERASEIWRITE ENABLE
AND DISABLE

f.4-

TCSL

cs -==zJ-'~----------------~--~~
SB

OPCODE

t;:m07W"",A0Vcm""""",

01~tC0CU_~
10000

EWDS

EWEN

DO - - - - - - - - HIGH-Z -~i---------.--NOTE:

ORGANIZATION

128 x8

64x 16

ERASE All (ERALl

The ERAL cycle is completely self-timed and commences after the last dummy address bit has been
clocked in. ERAL takes 15 ms max in both 8-bit and 16bit modes.

The entire chip will be erased to logical "1 s" ifthis instruction is received by the device and it is in the EWEN mode_

ERASE ALL
(CHIP ERASE)

NEW INSTRUCTION
OR STANDBY (CS. 0)

TeSH

~~II

1.-

r--4--

--.-I

TeSL

--~------------~M~~I~~~~~
AO

x mx~~/
I

~I
1-0- TR!
---------------------~~~~~
HIGH-Z

I..

Twe

NEW INSTRUCTION
OR STANDBY (CS "" 0)

WRITE All (WRALl

Note: The WRAL does not include an automatic erase
cycle forthe chip. Therefore, the WRAL instruction must
be preceded by an ERAL instruction and the chip must
be in the EWEN status in both cases.

The entire chip will be written with the data specified in
that command. The WRAL cycle is completely selftimed and commences after the last data bit (~O) has
been clocked in. WRAL takes 15 ms max in both a-bit
and 16-bit modes.

WRITE ALL

ClK

The WRAL instruction is used for testing and/or device
initialization.

:~.ILfLILnIU4rUl_1f_J___~
I

TCSH

=--zz;
SB

OPCODE

DO - - - - - - - - HIGH-Z

'-="""----'

f4'-

••

100

@:~;mm:

---I

TCSL

-------,f,5--'-1---~\l_--,_,

!c-L-

ROY/BSY _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _T_RB-1D~-

II~:
NOTE:

f--;-;;;;-::-;;--+-=-If-;;;:;-i
64x 16

DS20043C-6

015

1-62

I'"

Twc

NEW INSTRUCTION
OR STANDBY (CS = 0)

59C11

DICE FORM

NOTES:

1-63

DS20043C-7

59C11

DICE FORM

SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.

PART NUMBERS

Package:

Temperature
Range:

' - - - - - - - - 11 Device:

DS20043C-8

Blank

59C11

1-64

Dice in Wafer
Dice in Wafflepack

0° Cto+70° C

1K CMOS Serial EEPROM

85C72

Microchip

lK (128 X 8) CMOS Serial Electrically Erasable PROM
FEATURES

DESCRIPTION

•
•
•
•
•
•
•
•
•
•
•

The Microchip Technology Inc. 8SC72 is a 1K bit Electrically Erasable PROM. The device is organized as 128
x 8 bit memory with a two wire serial interface. Advanced
CMOS technology allows a significant reduction in power
over NMOS serial devices. Up to eight 8SC72s may be
connected to the two wire bus. The 8SC72 is available
in the standard 8-pin DIP and a surface mount SOIC
package.

Low power CMOS technology
Organized as one block of 128 bytes (128 x 8)
Two wire serial interface bus
S volt only operation
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 2 bytes
1ms write cycle time for single byte
100,000 eraselwrite cycles
Data retention >10 years
8-pin DIP or SOIC package
Available for extended temperature ranges:
-Commercial: O·C to +70·C
-Industrial: -40·C to +8S·C
-Automotive: -40·C to +12S·C

PIN CONFIGURATION

MOe

BLOCK DIAGRAM

DIP Package

A23
Vss

Vee
NC

6SCL
5

SOA

SO Package

M ....-I~--"""!'h-Vcc
A1

AO A1 A2

SCL
Vss

SOA

1-65

85C72
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE

Maximum Ratings"

Name

All inputs and outputs w.r.t. Vss ................ -0.3 V to +7 V
Storage temperature ....................... -65'C to +150'C
Ambient temp. with power applied ..... -65'C.to +125'C
Soldering temperature of leads (10 seconds) .. +300'C
ESD protection on all pins ................................ .4.0 kV

Function

AO, A1, A2
VSS
SDA
SCl
NC
VCC

'Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress rating onty and
functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.

Chip Address Inputs
Ground
Serial Address/Data I/O
Serial Clock
No Connect
+5 V Power Supply

Vee = +5 V (±10%)
Commercial (C): Tamb = O'C to +70'C
Industrial
(I): Tamb = -40'C to +85'C
Automotive (E): Tamb = -40'C to +125'C

DC CHARACTERISTICS

Symbol

Min

Max

Units

Vee detector threshold

VTH

2.8

4.5

SCl and SDA pins:
High level input voltage
low level input voltage
low level output voltage

VIH
VIL
VOL

Vee x 0.7
-0.3

Vee + 1
Vee x 0.3
0.4

V
V
V

AO, A1 & A2 pins:
High level input voltage
low level input voltage

VIH
VIL

Vee - 0.5
-0.3

Vee + 0.5
0.5

V
V

Input leakage current

III

IlA

VIN = 0 V to Vee

Output leakage current

ILO

IlA

VOUT = 0 V to Vee

Internal capacitance
(all inputs/outputs)

CINT

7.0

VINNoUT = 0 V (Note 1)
Tamb = +25'C, f = 1 MHz

Operating current

leeo

3.5

4.25

mA
mA
mA

FeLK = 100 kHz, program cycle
time=2ms, Vee=5V,
Tamb = O'C to +70'C
FeLK = 100 kHz, program cycle
time = 2 ms, Vee = 5 V,
Tamb = (I) and (E)
Vec = 5 V, Tamb = O'C to +70'C
Vee = 5 V, Tamb= (I) and (E)
Vec=5 V, Tamb= (C), (I) and (E)

IlA

Parameter

Program cycle

leew

Read cycle

leeR

7.0
8.5
750

Ices

100

Standby current

IlA

Conditions

IOL = 3.2 mA (SDA only)

SDA = SCl = Vee = 5 V
(no PROGRAM active)

Note 1: This parameter is periodically sampled and not 100% tested.

BUS TIMING START/STOP

sel _ _- J

SOA

-----""1
STOP

START

05111378-2

1-66

85C72
AC CHARACTERISTICS
Parameter

Symbol

Min

Typ

Max

Units

100

kHz

Clock frequency

FCLK

Clock high time

THIGH

4000

Clock low time

TLOW

4700

SDA and SCl rise time

1000

SDA and SCl fall time

300

Remarks

START condition hold time

THD:STA

4000

After this period the first
clock pulse is generated

START condition setup time

Tsu:sTA

4700

Only relevant for repeated
START condition

Data input hold time

THD:DAT

Data input setup time

Tsu:DAT

250

Data output delay time

TpD

300

Tsu:sTo

4700

TSUF

4700

STOP condition setup time
Bus free time

Input filter time constant
(SDA and SCl pins)
Program cycle time

ns
3500

TI
Twc

.7N

100

See Note 1

Time the bus must be free
before a new transmission
can start

Byte or Page mode N = #
of bytes to be written

SUS TIMING DATA

FUNCTIONAL DESCRIPTION

Both, master and slave can operate as transmitter or
receiver but the master device determines which mode
is activated.

The 85C72 supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl), controls the bus access, and generates the start
and STOP conditions, while the 85C72 works as slave.

Up to eight 85C72s can be connected to the bus,
selected by the AO, A 1 and A2 chip address inputs.
Other devices can be connected to the bus, but require
different device codes than the 85C72 (refer to section
Slave Address).

1-67

DS111378-3

85C72
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initilited only when the bus is
not busy.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the
data line while the clock line is HIGH will be interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (see Figure 1):

Bus not Busy (A)
Both data and clock lines remain HIGH.

Start Data Transfer (B)
A HIGH to lOW transition of the SOA line while the clock
(SCl) is HIGH determines a START condition. All commands must be preceded by a START condition.

Stop Data Transfer (C)
A lOWto HIGH transition olthe SOA line while the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed dloring the lOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.

Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note: The 85C72 does not generate any acknowledge
bits if an internal programming cycle is in progress.
The device that acknowledges, has to pull down the SOA
line during the acknowledge clock pulse in such a way
that the SOA line is stable lOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must Signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line HIGH to enable the master to
generate the STOP condition.

FIGURE 1 • DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(A)
(9)
SCl ~--I-"":"";'--I-.....

SDA

START CO~mITlON

ADDRESS
DATA AllOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID

DS111379-4

1-68

STOP
CONDITION

85C72
SLAVE ADDRESS
indicates to the addressed 85C72 that a byte with a word
address will follow after it has generated an acknowledge bit. Therefore the next byte transmitted by the
master is the word address and will be written into the
address pointer of the 85C72. The most significant bit of
the word address is a "Do Not Care" value for the 85C72.
After receiving the acknowledge of the 85C72, the
master device transmits the data word to be written into
the addressed memory location. The 85C72 acknowledges again and the master generates a STOP condition. This initiates the internal programming cycle of the
85C72. (See Figure 3.)

The chip address inputs AO, A1 and A2 of each 85C72
must be externally connected to either Vcc or ground
(Vss), assigning to each 85C72 a unique 3-bit address.
Up to eight 85C72s may be connected to the bus. Chip
selection is then accomplished through software by
setting the bits AO, A1 and A2 ofthe slave address to the
corresponding hardwired logic levels of the selected
85C72.
After generating a START condition, the bus master
transmits the slave address conSisting of a 4-bit device
code (1 01 0) for the 85C72, followed by the chip address
bits AO, A1 and A2.
The eighth bit of slave address determines if the master
device wants to read or write to the 85C72. (See Figure

PAGE PROGRAM

2.)

To program the 85C72, the master sends addresses
and data to the 85C72 which is the slave. (See Figure
3.) This is done by supplying a START condition followed by the 4-bit device code, the 3-bit slave address,
and the R!W bit which is defined as a logic LOW for a
write. This indicates to the addressed slave that a word
address will follow so the slave outputs the acknowledge
pulse to the master during the ninth clock pulse. When
the word address is received by the 85C72, it places it in
the lower 8 bits of the address pointer defining which
memory location is to be written. (One" Do Not Care" bit
and seven address bits.) The 85C72 will generate an acknowledge after every 8 bits received and store them
consecutively in a 2-byte RAM until a STOP condition is
detected which initiates the internal programming cycle.
If more than 2 bytes are transmitted by the master, the
85C72 will terminate the write cycle. This does not affect
eraselwrite cycles of the EEPROM array.

The 85C72 monitors the bus for its corresponding slave
address all the time. It generates an acknowledge bit if
the slave address was true and it is not in a programming
mode.

FIGURE 2 • SLAVE ADDRESS
ALLOCATION

READIWRITE

I :

(

,,
lAO')

MODE

Ifthe master generates a STOP condition after transmitting the first data word (Point 'P' on Figure 3), byte programming mode is entered.

BYTE PROGRAM MODE

The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received (up to two) data bytes will be
written in a serial manner.

In this mode, the master sends addresses and one data
byte to the 85C72.
Following the START condition, the device code (4-bit),
the slave address (3-bit), and the Rfii bit, which is logic
LOW, are placed onto the bus by the master. This

The PROGRAM cycle takes N milliseconds, whereby N
is the number of received data bytes (N max = 2).

FIGURE 3 • PROGRAM MODE (ERASElWRITE)

ACKNOWLEDGES FROM SLAVE

1-69

DS11137B-5

85C72
READ MODE
This mode illustrates master device reading data from
theB5C72.
As can be seen from Figure 4, the master first sets up the
slave and word addresses by doing a write. (Note:
Although this is a read mode the address pointer must be
written to.) During this period the 85C72 generates the
necessary acknowledge bits as defined in the appropriate section.
'
The master now generates another START condition
and transmits the slave address again, except this time
the read/write bit is set into the read mode. After the

slave generates the acknowledge bit, it then outputs the
data from the addressed location on to the SDA pin, increments the address pointe .. and, if it receives an acknowledge from the master, will transmit the next consecutive byte. This autoincrement sequence is only
aborted .when the master sends a STOP condition instead of an acknowledge.
Note: If the master knows where the address pOinter is,
it can begin the read sequence atpoint 'R' indicated on
Figure 4 and save time transmitting the slave and word
addresses.
In all modes, the address pointer will automatically
increment from the end olthe memory block (128 bytes)
back to the first location in that block.

FIGURE 4 - READ MODE

R!W

RIW

AUTO INCREMENT
WORD ADDRESS

PIN DESCRIPTION
AD. A1 and A2 Chip Address Inputs

NC No Connect

The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.

This pin can be left open or used as a tie point.

Up to eight 85C72s can be connected to the bus.

Notes:

These inputs must be connected to either Vss or VCC.

1) A "page" is defined as the maximum number of bytes
that can be programmed in a single write cycle. The
85C72 page is 2 bytes long.

SDA Serial Address/Data InputlOutput
This is a bidirectional pin used to transfer addresses and
data into and data out of the device. It is an open drain
terminal.
For normal data transfer SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are reserved for indicating the START and STOP conditions.

SCl Serial Clock
This input is used to synchronize the data transfer from
and to the device.

DS11137B,6

1-70

85C72
NOTES:

1-71

D8111379-7

85C72
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.

PART NUMBERS

PACKAGE:

P
SM

D8111379-8

TEMPERATURE
RANGE:

DEVICE:

Blank
I
E

85C72
85C72T

1-72

CER:':,P
Plastic DIP
Plastic SOIC (0.207 mil Body)
O' C to +70' C
-40' C to +85' C
·40' C to +125' C

1K CMOS SERIAL EEPROM
1K CMOS SERIAL EEPROM
(in Tape & Reel)

85C72
DICE FORM

Microchip

lK (128 X 8) CMOS Serial Electrically Erasable PROM
FEATURES

DESCRIPTION

• Low power CMOS technology
• Organized as one block of 128 bytes (128 x 8)
Two wire serial interface bus
5 volt only operation
Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 2 bytes
1 ms write cycle time for single byte
• Available in wafer or waffle pack
Temperature range:
-Commercial: O·C to +70·C

The Microchip Technology Inc. 85C72 is a 1 K bit Electrically Erasable PROM. The device is organized as 128
x 8 bit memory with a two wire serial interface. Advanced
CMOS technology allows a significant reduction in power
over NMOS serial devices. Up to eight 85C72s may be
connected to the two wire bus. The 85C72 dice are
available in wafer or wafflepack.

DIE CONFIGURATION

BLOCK DIAGRAM

Die Size: 106 x 76 mils

Vcc -_
Vss

SDA-

1.
2.
3.
4.

AD
Al
A2
Vss

8.
7.
6.
5.

.....

SCL-~

Vcc
NF
SCL
SDA

Data
Buffer
"""
2x8
(FIFO)
Data Reg.

ASlave
Address

Control
Logic
10

1-73

~R/wAmp

do
di
r n
e t
s e

Memory
Array
128 x 8

I AD:'
A6

.!~

Increment

DS11147C-l

85C72

DICE FORM

ELECTRICAL CHARACTERISTICS
Maximym Ratings·

PAD FUNCTION TABLE

All inputs and outputs w.r.t. Vss ................ -0.3 V to +7 V
Storage temperature ....................... -6S'C to +150'C
Ambient temp. with power applied ..... -65'C to + 125'C
Soldering temperature 01 leads (10 seconds) .. +300·C
ESD protection on all pins ................................... .4 kV

Name
AO, A1, A2
Vss
SDA
SCl
NF
Vee

'Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is astress rating only and
functional operation of the device at those or any other conditions above
thOSe indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.

Chip Address Inputs
Ground
Serial Address/Data I/O
Serial Clock
No Function
+5 V Power Supply

Vee = +5 V (±10%)
Commercial (C): Tamb = O'C to +70'C

DC CHARACTERISTICS

Parameter

Function

Symbol

Min

Max

Units

Vee detector threshold

VTH

2.8

4.5

SCl and SDA pins:
High level input voltage
low level input voltage
low level output voltage

VIH
Vil
VOL

Vee x 0.7
-0.3

Vee + 1
Vee x 0.3
0.4

V
V
V

AO, A1 & A2 pins:
High level input voltage
low level input voltage

VIH
Vil

Vee - 0.5
-0.3

Vee + 0.5
0.5

V
V

Input leakage current

III

ItA

VIN = 0 V to Vcc

Output leakage current

IlO

J.1A

VOUT = 0 V to Vee

Internal capacitance
(all inputs/outputs)

CINT

7.0

VINIVoUT = 0 V (Note 1)
Tamb = +25'C, 1= 1 MHz

Operating current

leeo

3.5

program cycle

leew

7.0

FelK = 100 kHz, program cycle
time = 2 ms, Vee = 5 V,
Vee=5V

read cycle

leeR

750

ItA

Vee=5V

Ices

100

ItA

SDA = SCl = Vee,. 5 V
(no PROGRAM active)

Standby current

Conditions

IOl = 3.2 mA (SDA only)

Note 1: This parameter is periodically sampled and not 100% tested.

BUS TIMING START/STOP

sel _ _- . J

SOA ...,....----;-"'1

START

STOP

1-74

85C72

DICE FORM

AC CHARACTERISTICS
Parameter

Symbol

Min

Typ

Clock frequency

FCLK

Clock high time

THIGH

4000

Clock low time

TLOW

4700

Max

Units

100

kHz

Remarks

ns
ns

SDA and SCl rise time

1000

SDA and SCl fall time

300

START condition hold time

THD:STA

4000

After this period the first
clock pulse is generated

START condition setup time

TSU:STA

4700

Only relevant for repeated
START condition

Data input hold time

THD:DAT

Data input setup time

TSU:DAT

250

Data output delay time

TPD

300

TSU:STO

4700

TBUF

4700

STOP condition.setup time
Bus free time

Noise suppression time constant
(SDA and SCl pins)
Program cycle time

3500

.7N

Twc

100

See Note 1

Time the bus must be free
before a new transmission
can start

Byte or Page mode N
of bytes to be written

Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min
300 ns) of the falling edge of SCl to avoid unintended generation of START or STOP conditions.

BUS TIMING DATA

THD:DAT (receiver)

T PO

(transmitter)

FUNCTIONAL DESCRIPTION
The 85C72 supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl), controls the bus access, and generates the
START and STOP conditions, while the 85C72 works as
slave. Both, master and slave can operate as transmit-

ter or receiver but the master device determines which
mode is activated.
Up to eight 85C72s can be connected to the bus,
selected by the AO, A1 and A2 chip address inputs.
Other devices can be connected to the bus but require
different device codes than the 85C72 (refer to section
Slave Address).

DS11147C-3

1-75

85C72

DICE FORM

Bus not Busy (A)
Both data and clock lines remain HIGH.

Start Data Transfer (B)
A HIGH to lOW transition of the SDA line while the clock
(SCl) is HIGH determines a START condition. All
commands must be preceded by a START condition.

Note: The 85C72 does not generate any acknowledge
bits if an internal programming cycle is in progress.

Stop Data Transfer (Cl

The device that acknowledges, has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line HIGH to enable the master to
generate the STOP condition.

A lOW to HIGH transition of the SDA line while the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

Data Valid (D)
The state of the data line represents valid data when,
after a start condition, the data line is stable for the
duration of the HIGH period of the clock signal.

FIGURE 1 - DATA TRANSFER SEQUENCE ON THE SERIAL

SCL

(A)
(8)
--+-__
____

(D)

(C)

(A)

SDA

START CONDITION

DS11147C-4

ADDRESS
DATA ALLOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID

1-76

STOP
CONDITION

85C72

DICE FORM

SLAVE ADDRESS
The chip address inputs AO, A1 and A2 of each 85C72
must be externally connected to either Vee or ground
(Vss), assigning to each 85C72 a unique 3-bit address.
Up to eight 85C72s may be connected to the bus. Chip
selection is then accomplished through software by
setting the bits AO, A1 and A2 of the slave address to the
corresponding hardwired logic levels of the selected
85C72.

the slave address (3-bit), and the RIW bit, which is logic
LOW, are placed onto the bus by the master. This
indicates to the addressed 85C72 that a byte with a word
address will follow after it has generated an acknowledge bit. Therefore, the next byte transmitted by the
master is the word address and will be written into the'
address pointer of the 85C72. The most significant bit of
the word address is a "Do Not Care" value forthe 85C72.
After receiving the acknowledge of the 85C72, the
master device transmits the data word to be written into
the addressed memory location. The 85C72 acknowledges again and the master generates a STOP condition. This initiates the internal programming cycle olthe
85C72. (See Figure 3.)

After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1 01 0) for the 85C72, followed by the chip address
bits AO, A1 and A2.
The eighth bit of slave address determines if the master
device wants to read or write to the 85C72. (See Figure
2.)

PAGE PROGRAM

The 85C72 monitors the bus for its corresponding slave
address all the time. It generates an acknowledge bit if
the slave address was true and it is not in a programming
mode.

To program the 85C72, the master sends addresses
and data to the 85C72 which is the slave (see Figure 3).
This is done by supplying a start condition followed by
the 4-bit device code, the 3-bit slave address, and the
RIW bit which is defined as a logic LOW for a write. This
indicates to the addressed slave that a word address will
follow so the slave outputs the acknowledge pulse to the
master during the ninth clock pulse. When the word
address is received by the 85C72, it places it in the lower
8 bits of the address pointer defining which memory
location is to be written. (One do not care bit and seven
address bits) The 85C72 will generate an acknowledge
after every 8 bits received and store them consecutively
in a 2-byte RAM until a stop condition is detected which
initiates the internal programming cycle. If more than 2
bytes are transmitted by the master, the 85C72 will
terminate the write cycle. This does not affect erasel
write cycles of the EEPROM array.

FIGURE 2 - SLAVE ADDRESS
ALLOCATION
READ,E

(

I :
o

If the master generates a STOP condition after transmitting the first data word (Point 'po on Figure 3), byte
programming mode is entered.

BYTE PROGRAM MODE

The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received (up to 2) data bytes will be
written in a serial manner.

In this mode, the master sends addresses and one data
byte to the 85C72.
Following the START condition, the device code (4-bit),

I FIGURE 3 - PROGRAM MODE (ERASElWRITE)

MODE

1-77

ACKNOWLEDGES FROM SLAVE

DS11147C-5

85C72

DICE FORM

READ MODE
This mode illustrates master device reading data from
the 85C72.
As can be seen from Figure 4, the master first sets up the
slave and word addresses by doing a write. (Note:
Although this is a read mode the address pointer must be
written to.) During this period the 85C72 generates the
necessary acknowledge bits as defined in the appropriate section.
'
The master now generates another start condition and
transmits the slave address again, except this time the
read/write bit is set into the read mode. After the slave

generates the acknowledge bit, it then outputs the data
from the addressed location on to the SDA pad, increments the address pointer and, if it receives an acknowledge from the master, will transmit the next consecutive
byte. This autoincrement sequence is only aborted
whim the master sends a stop condition instead of an
acknowledge.
Note: If the master knows where the address pointer is,
it can begin the read sequence at point 'R' indicated on
Figure 4 and save time transmitting the slave and word
addresses.

FIGURE 4 - READ MODE

AUTO INCREMENT
WORD ADDRESS

PAD DESCRIPTION
AQ, A 1 and A2 Chip Address Inputs
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 85C72s can be connected to the bus.
These inputs must be connected to either Vss or VCC.

For normal data transfer SDA is allowed to change only
during SCl lOW. Changes during SCl HIGH are reserved for indicating the START and STOP conditions.

SCLSerial Clock
This input is used to synchronize the data transfer from
and to the device.

SDA Serial Address/Data InputlOutput

NF No Function

This is a bidirectional pad used to transfer addresses
and data into and data out of the device. It is,an open
drain terminal.

Thi,s pad must be connected to Vss for normal operation.

DSll147C~6

1-78

85C72

DICE FORM

NOTES:

1-79

DS11147C-7

85C72

DICE FORM

SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.

PART NUMBERS

PACKAGE:

TEMPERATURE
RANGE:

DEVICE:

DS11147C·8

DICE in WAFER
DICE in WAFFLE PACK

O' C

85C72

1-80

to 70' C

1K CMOS SERIAL EEPROM

85C82

Microchip

2K (256 X 8) CMOS Serial Electrically Erasable PROM
FEATURES

DESCRIPTION

•
•
•
•
•
•
•
•
•
•
•

The Microchip Technology Inc. 85C82 is a 2K bit Electrically Erasable PROM. The device is organized as 256
x 8 bit memory with a two wire serial interface. Advanced
CMOS technology allows asignificant reduction in power
over NMOS serial devices. The 85C82 also has a pagewrite capability for up to 2 bytes of data. Up to eight
85C82s may be connected to the two wire bus. The
85C82 is available in standard 8-pin DIP and surface
mount SOIC package.

Low power CMOS technology
Organized as one block of 256 bytes (256 x 8)
Two wire serial interface bus
5 volt only operation
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 2 bytes
1ms write cycle time for single byte
100,000 eraselwrite cycles
Data retention >10 years
8-pin DIP or SOIC package
Available for extended temperature ranges:
-Commercial: O'C to +70'C
-Industrial: -40'C to +85'C
-Automotive: -40'C to +125'C

BLOCK DIAGRAM

PIN CONFIGURATION
DIP Package

Vee

SCL

Vss

SDA

SO Package

Vee

SCL

Vss

SOA

AOA1 A2

1-81

OS11136C-1

85C82
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE

Maximum Ratings*
All inputs and outputs w.r.t. Vss ................ -0.3 V to +7 V
Storage temperature ....................... -65"C to + 150"C
Ambient temp. with power applied ..•.. -65"C to + 125"C
Soldering temperature 01 leads (10 seconds) .. +300"C
ESD protection on all pins ................................... .4 kV
"Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress rating only and

Name

Function

AO"Al, A2
Vss
SDA
SCl
NC
Vee

Chip Address Inputs
Ground
Serial Address/Data Input/Output
Serial Clock
No Connect
+5 V Power Supply

functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
Vee = +5 V (±10%)
Commercial (C): Tamb = O"C to+70"C
Industrial
(I): Tamb = -40"C to +85"C
Automotive lEi: Tamb=-40"Cto+125"C

DC CHARACTERISTICS

Symbol

Min

Max

Units

Vee detector threshold

VTH

2.8

4.5

SCl and SDA pins:
High level input voltage
low level input voltage
low level output voltage

VIH
VIL
VOL

Vee x 0.7 Vee + 1
-0.3
Vee x 0.3
0.4

V
V
V

AO, Al & A2 pins:
High level input voltage
low level input voltage

VIH
VIL

Vee - 0.5
-0.3

Vee + 0.5
0.5

V
V

Parameter

Conditions

IOL = 3.2 mA (SDA only)

Input leakage current

III

IlA

VIN = 0 V to Vcc

Output leakage current

ILO

IlA

VOUT = 0 V to Vee

Internal capacitance
(all inputs/outputs)

CINT

7.0

VINIVoUT = 0 V (Note 1)
Tamb = +25"C, 1 = 1 MHz

Operating current

leeo

3.5

4.25

mA
mA
mA
I1A

FeLK = 100 kHz, program cycle time = 2 ms,
Vee = 5 V, Tamb = O"C to +70"C
FeLK = 100 kHz, program cycle time = 2 ms,
Vee = 5 V, Tamb = (I) and (E)
Vee = 5 V, Tamb = O"C to +70"C
Vee=5 V, Tamb= (I) and (E)
Vee = 5 V, Tamb= (C), (I) and (E)

I1A

SDA = SCl = Vee = 5 V(no PROGRAM active)

program cycle

leew

read cycle

leeR

7.0
8.5
750

Standby current

Ices

100

Note 1: This parameter is periodically sampled and not 100% tested.

BUS TIMING START/STOP
seL _ _- J
SOA - - - - - ; , . 1

STOP

START

D811136C-2

1-82

85C82
AC CHARACTERISTICS
Parameter

Symbol

Min

Typ

Clock frequency

FCLK

Clock high time

THIGH

4000

Clock low time

TLow

4700

Max

Units

100

kHz

Remarks

ns
ns

SDA and SCl rise time

1000

SDA and SCl fall time

300

START condition hold time

THD:STA

4000

After this period the first
clock pulse is generated

START condition setup time

Tsu:sTA

4700

Only relevant for repeated
START condition

Data input hold time

THD:DAT

Data input setup time

TSU:DAT

250

Data output delay time

TPD

300

Tsu:sTo

4700

TBuF

4700

STOP condition setup time
Bus free time

Input filter time constant
(SDA and SCl pins)
Program cycle time

3500

TI
Twc

.7N

100

See Note 1

Time the bus must be free
before a new transmission
can start

Byte or Page mode N ; #
of bytes to be written

BUS TIMING DATA

FUNCTIONAL DESCRIPTION

slave. Both, master and slave can operate as transmitter or receiver, but the master device determines which
mode is activated.

The 85C82 supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl), controls the bus access, and generates the
START and STOP conditions, while the 85C82 works as

Up to eight 85C82s can be connected to the bus,
selected by the AO, Aland A2 chip address inputs.
Other devices can be connected to the bus, but require
different device codes than the 85C82 (refer to section
Slave Address).

1-83

DSll136C-3

85C82
BUS CHARACTERISTICS

Data Valid (Ql

The following bus protocol has been defined:

The state of the data line represents valid data when,
after a start condition, the data line is stable for the
duration of the HIGH period of the clock signal.

- Data transfer may be initiated only when the bus is not
busy.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as
a START or STOP condition.

The data on the line must be changed during the lOW
period of the clock signal. There is one clock pulse per
bit of data.

Bus not Busy (Al

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.

Both data and clock lines remain HIGH.

Acknowledge

Start Data Transfer (Bl·

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.

Accordingly, the following bus conditions have been
defined (see Figure 1):

A HIGH to lOW transition of the SDA line while the clock
(SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.

Stop Data Transfer (Cl
A lOW to HIGH transition of the SDA line while the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

Note: The 85C82 does not generate any acknowledge
bits if an internal programming cycle is in progress.
The device that acknowledges, has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable lOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out ofthe slave. In this case the slave must
leave the data line HIGH to enable the master to generate the STOP condition.

FIGURE 1 - DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)

SCL

(8)

(C)

-+-+. . .

(A)

SDA

START CONDITION

DSll136C-4

ADDRESS
DATA ALLOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID

1-84

STOP
CONDITION

85C82
SLAVE ADDRESS
The chip address inputs AO, A 1 and A2 of each 85C82
must be externally connected to either Vee or ground
(Vss), assigning to each 85C82 a unique 3-bit address.
Up to eight 85C82s may be connected to the bus. Chip
selection is then accomplished through software by
setting the bits AO, A 1 and A2 of the transmitted slave
address to the corresponding hardwired logic levels of
the selected 85C82.

LOW, are placed onto the bus by the master. This
indicates to the addressed 85C82 that a byte with a word
address will follow after it has generated an acknowledge bit. Therefore, the next by1e transmitted by the
master is the word address and will be written into the
address pointer of the 85C82. After receiving the acknowledge of the 85C82, the master device transmits
the data word to be written into the addressed memory
location. The 85C82 acknowledges again and the
master generates a STOP condition. This initiates the
internal programming cycle of the 85C82. (See Figure
3.)

After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) forthe 85C82, followed by the chip address
bits AO, A1 and A2.
The eighth bit of slave address determines if the master
device wants to read or write to the 85C82. (See Figure

PAGE PROGRAM MODE

2.)

To program the 85C82, the master sends addresses
and data to the 85C82 which is the slave (see Figure 3).
This is done by supplying a START condition followed by
thl:!..4-bit device code, the 3-bit slave address, and the
RIW bit which is defined as a logic LOW for a write. This
indicates to the addressed slave that a word address will
follow so the slave outputs the acknowledge pulse to the
master during the ninth clock pulse. When the word
address is received by the 85C82, it places it in the lower
8 bits of the address pointer defining which memory
location is to be written. The 85C82 will generate an
acknowledge after every 8 bits received and store them
consecutively in a 2-by1e RAM until a stop condition is
detected which initiates the internal programming cycle.
If more than 2 by1es are transmitted by the master, the
85C82 will terminate the write cycle. This does not affect
erase/write cycles of the EEPROM array.

The 85C82 monitors the bus for its corresponding slave
address all the time. It generates an acknowledge bit if
the slave address was true and it is not in a programming
mode.

FIGURE 2· SLAVE ADDRESS
ALLOCATION
START

/""
/

: ~LAV~

READIWRITE

AD9RES:S

"'"

(RIWI

If the master generates a STOP condition after transmitting the first data word (Point 'po on Figure 3). byte programming mode is entered.

BYTE PROGRAM MODE

The internal. completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received (up to two) data by1es will be
written in a serial manner.

In this mode the master sends addresses and one data
by1e to the 85C82.
Following the START condition, the device code (4-bit),
the slave address (3-bit), and the RNii bit, which is logic

The PROGRAM cycle takes N milliseconds. whereby N
is the number of received data bytes (N max = 2).

FIGURE 3 • PROGRAM MODE (ERASEIWRITE)

ACKNOWLEDGES FROM SLAVE

DS11136C-5

1-85

85C82
READ MODE
This mode illustrates master device reading data from
.
the 85C82.
As can be seen from Figure 4, the master first sets upthe
slave and word addresses by doing a write. (Note:
Although this is a read mode, the address pointer must
be written to.) During this period the 85C82 generates
the necessary acknowledge bits as defined in the appropriate section.
The master now generates another START condition
and transmits the slave address again, except this time
the read/write bit is set into the read mode. After the
slave generates the acknowledge bit, it then outputs the

data from the addressed location on to the SDA pin, increments the address pointer and, if it receives an acknowledge from the master, will transmit the next consecutive byte. This autoincrement sequence is only
aborted \' :,en the master sends a STOP condition
instead of an acknowledge.
Note: If the master knows where the address pointer is,
it can begin the read sequence at point 'R' indicated on
Figure 4 and save time transmitting the slave and word
addresses.
Note: In all modes, the address pointer will automatically
increment from the end of the memory block (256 byte)
back to the first location in that block.

FIGURE 4 • READ MODE

AUTO INCREMENT
WORD ADDRESS

PIN DESCRIPTION
AO. A1 and A2 Chip Address Inputs

SCl Serial Clock

The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.

This input is used to synchronize the data transfer from
and to the device.

NC No Connect

Up to eight 85C82s can be connected to the bus.
These inputs must be connected to either Vss or Vcc.

SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses and
data into and data out of the device. It is an open drain
terminal. For normal data transfer SDA is allowed to
change only during SCL LOW. Changes during SCL
HIGH are reserved for indicating the START and STOP
conditions.

DSll136C-6

This pin can be left open or used as a tie point.

Notes:
1) A "page" is defined as the maximum number of bytes
that can be programmed in a single write cycle. The
85C82 page is 2 bytes long.
2) A "block" is defined as a continuous area of memory
with distinct boundaries. The address pointer can not
cross the boundary from one block to another. It will
however, wrap around from the end of a block to the first
location in the same block. The 85C82 has only one
block (256 bytes).

1-86

85C82
NOTES:

1-87

DS11136C-7

85C82
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.

PART NUMBERS

J
P

PACKAGE:

I
I

DS11136C-8

TEMPERATURE
RANGE:

DEVICE:

Blank
I
E

85C82
85C82T

1-88

CERDIP
Plastic DIP
Plastic SOIC (0.207 mil Body)

0' C to +70' C
-40' C to +85' C
-40' C to +125' C

2K CMOS Serial EEPROM
2K CMOS Serial EEPROM
(in Tape & Reel)

85C82
DICE FORM

Microchip

2K (256 X 8) CMOS Serial Electrically Erasable PROM
FEATURES

DESCRIPTION

• Low power CMOS technology
• Organized as one block of 256 bytes (256 x 8)
Two wire serial interface bus
• 5 volt only operation
Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 2 bytes
• 1ms write cycle time for single byte
• Available in wafer or wafflepack
• Temperature range:
-Commercial: O'C to +70'C

DIE CONFIGURATION

BLOCK DIAGRAM

Die Size: 106 x 76 mils

AOto
A7

1-89

Memory
Array
256 x 8

DS11148C-1

85C82

DICE FORM

ELECTRICAL CHARACTERISTICS
Maximum Ratings*
All inputs and outputs w.r.t. vss ................ -0.3 V to +7 V
Storage temperature ....................... -65·C to + 150·C
Ambient temp. with power applied ..... -65·C to + 125·C
Soldering temperature of leads (10 seconds) .. +300·C
ESD protection on all pins ................................... .4 kV
"'Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specification is not

implied, Exposure to maximum rating conditions for extended periods

PAD FUNCTION TABLE
Name

Function

AQ,A1,A2
Vss
SDA
SCL
NF
Vee

Chip Address Inputs
Ground
Serial Address/Data I/O
Serial Clock
No Function
+5 V Power Supply

may affect device reliability.

Vee = +5 V (±10%)
Commercial (C): Tamb = O·C to +70·C

DC CHARACTERISTICS

Parameter

Symbol

Min

Max

Units

Vee detector threshold

VTH

2.8

4.5

SCL and SDA pins:
High level input voltage
Low level input voltage
Low level output voltage

VIH
VIL
VOL

Vee x 0.7
-0.3

Vee + 1
Vee x 0.3
0.4

V
V
V

AO, A1 & A2 pins:
High level input voltage
Low level input voltage

VIH
VIL

Vee - 0.5
-0.3

Vee + 0.5
0.5

V
V

Conditions

IOL = 3.2 mA (SDA only)

Input leakage current

III

/lA

VIN = 0 V to Vcc

Output leakage current

ILO

/lA

VOUT = 0 V to Vcc

Internal capacitance
(all inputs/outputs)

CINT

7.0

VINNoUT = 0 V (Note 1)
Tamb = +25"C, f = 1 MHz

Operating current

leeo

3.5

program cycle

leew

7.0

FeLK = 100 kHz, program cycle
time = 2 ms, Vee = 5 V,
Vec=5 V

read cycle

leeR

750

flA

Vee=5V

lees

100

/lA

SDA = SCL = Vee = 5 V
(no PROGRAM active)

Standby current

Note 1: This parameter is periodically sampled and not 100% tested.

BUS TIMING START/STOP

SCL---J

SOA ------;-,1

START

STOP

DSl1148C-2

1-90

85C82

DICE FORM

AC CHARACTERISTICS
Parameter

Symbol

Min

Typ

Max

Units

100

kHz

Clock frequency

FCLK

Clock high time

THIGH

4000

Clock low time

TLow

4700

SDA and SCl rise time

1000

SDA and SCl fall time

300

Remarks

START condition hold time

THD:STA

4000

After this period the first
clock pulse is generated

START condition setup time

Tsu:sTA

4700

Only relevant for repeated
START condition

Data input hold time

THD:DAT

Data input setup time

TSU:DAT

250

Data output delay time

TPD

300

Tsu:sTo

4700

TBuF

4700

STOP condition setup time
Bus free time

Noise suppression time constant
(SDA and SCl pins)
Program cycle time

ns
3500

.7N

Twc

100

See Note 1

Time the bus must be free
before a new transmission
can start

Byte or Page mode N
of bytes to be written

Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min
300 ns) of the falling edge of SCl to avoid unintended generation of START or STOP conditions.

BUS TIMING DATA
SCL

SDA

FUNCTIONAL DESCRIPTION
ter or receiver but the master device determines which
mode is activated.

The 85C82 supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is, defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl), controls the bus access, and generates the
START and STOP conditions, while the 85C82 works as
slave. Both, master and slave can operate as transmit-

Up to eight 85C82S can be connected to the bus,
selected by the AO, A1 and A2 chip address inputs.
Other devices can be connected to the bus but require
different device codes than the 85C82 (refer to section
Slave Address).

1-91

DS11148C-3

85C82

DICE FORM

BUS CHARACTERISTICS
The following bus protocol has been defined:
-

Data transfer may be initiated only when the bus is not
busy.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as
a START or STOP condition.

Accordingly, the following bus conditions have been
defined (see Figure 1):

Bus not Busy (Al
Both data and clock lines remain HIGH.

Start Data Transfer (B)
A HIGH to lOW transition of the SDA line while the clock
(SCl) is HIGH determines a START condition. All
commands must be preceded by a START condition.

Stop Data Transfer (C)
A lOW to HIGH transition of the SDA line while the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note: The 85C82 does not generate any acknowledge
bits if an internal programming cycle is in progress.
The device that acknowledges, has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable lOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out ofthe slave. In this case the slave must
leave the data line HIGH to enable the master to generate the STOP condition.

Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the lOW
period of the clock Signal. There is one clock pulse per
bit of data.

FIGURE 1· DATA TRANSFER SEQUENCE ON THE SERIAL BUS BUS

(A)

SCL

(8)

--I--h

SDA

START CONDITION

DS11148C-4

ADDRESS
DATA ALLOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID

1-92

STOP
CONDITION

85C82

DICE FORM

SLAVE ADDRESS
Following the START condition, thesLevice code (4-bit),
the slave address (3-bit), and the R, W bit, which is logic
LOW, are placed onto the bus by the master. This
indicates to the addressed 85C82 that a byte with a word
address will follow after it has generated an acknowledge bit. Therefore, the next byte transmitted by the
master is the word address and will be written into the
address pointer of the 85C82. After receiving the
acknowledge of the 85C82, the master device transmits
the data word to be written into the addressed memory
location. The 85C82 acknowledges again and the
master generates a STOP condition. This initiates the
internal programming cycle of the 85C82. (See Figure
3.)

The chip address inputs AO, A 1 and A2 of each 85C82
must be externally connected to either Vee or ground
(Vss), assigning to each 85C82 a unique 3-bit address.
Up to eight 85C82s may be connected to the bus. Chip
selection is then accomplished through software by
setting the bits AO, A 1 and A2 of the transmitted slave
address to the corresponding hardwired logic levels of
the selected 85C82.
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1 01 0) for the 85C82, followed by the chip address
bits AO, A1 and A2.
The eighth bit of slave address determines if the master
device wants to read or write to the 85C82. (See Figure

2.)

PAGE PROGRAM MODE

The 85C82 monitors the bus for its corresponding slave
address all the time. It generates an acknowledge bit if
the slave address was true and it is not in a programming
mode.

To-program the 85C82, the master sends addresses
and data to the 85C82 which is the slave (see Figure 3).
This is done by supplying a start condition followed by
the 4-bit device code, the 3-bit slave address, and the
RIW bit which is defined as a logic LOW for a write. This
indicates to the addressed slave that a word address will
follow so the slave outputs the acknowledge pulse to the
master during the ninth clock pulse. When the word
address is received by the 85C82, it places it in the lower
8 bits of the address pointer defining which memory
location is to be written. The 85C82 will generate an
acknowledge after every 8 bits received and store them
consecutively in a 2-byte RAM until a STOP condition is
detected which initiates the internal programming cycle.
If more than 2 bytes are transmitted by the master, the
85C82 will terminate the write cycle. This does not affect
erase/write cycles of the EEPROM array.

FIGURE 2· SLAVE ADDRESS
ALLOCATION
START

READ/WRITE

"""

If the master generates a STOP condition after transmitting the first data word (Point 'P' on Figure 3), byte
programming mode is entered.

BYTE PROGRAM MODE

The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received (up to 2) data bytes will be

In this mode the master sends addresses and one data
byte to the 85C82.

FIGURE 3 • PROGRAM MODE (ERASEIWRITE)

1-93

ACKNOWLEDGES FROM SLAVE

DS11148C-5

85C82

DICE FORM

READ MODE
This mode illustrates master device reading data from
the 85C82.
As can be seen from Figure 4, the master first sets up the
slave and word addresses by doing a write. (Note:
although this is a read mode the address pOinter must be
written to.) During this period the 85C82 generates the
necessary acknowledge bits as defined in the appropriate section.
The master now generates another START condition
and transmits the slave address again, except this time
the read/write bit is set into the read mode. After the
slave generates the acknowledge bit, it then outputs the
data from the addressed location on to the SDA pad,

increments the address pointer and, if it receives an
acknowledge from the master, will transmit the next
consecutive byte. This autoincrement sequence is only
aborted when the master sends a STOP condition
instead of an acknowledge.
Note: If the master knows where the address pointer is,
it can begin the read sequence at point 'R' indicated on
Figure 4 and save time transmitting the slave and word
addresses.
Note: In all modes, the address pointer will automatically increment from the end of the memory block (256
bytes) back to the first location in that block.

FIGURE 4 • READ MODE

RIW

AUTO INCREMENT
WORD ADDRESS

PAD DESCRIPTION
AO. A1 and A2 Chip Address Inputs
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.

For normal data transfer SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are reserved for indicating the START and STOP conditions.

Up to eight 85C82s can be connected to the bus.

SCL Serial Clock

These inputs must be connected to either Vss or Vcc.

SDA Serial Address/Data Input/Output
This is a bidirectional pad used to transfer addresses
and data into and data out of the device. It is an open
drain terminal.

DSll148C-6

This input is used to synchronize the data transfer from
and to the device.

NF No Function
This pad must be connected to Vss for normal operation.

1-94

85C82

DICE FORM

NOTES:

DSll148C-7

1-95

~-~-

~~-~~-------

85C82

DICE FORM

SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.

PART NUMBERS

W
S

TEMPERATURE
RANGE:

DEVICE:

DS11148C-8

DICE in WAFER
DICE In WAFFLEPACK

O' C1070' C

85C82

1-96

2K CMOS SERIAL EEPROM

85C92

Microchip

4K (512 X 8) CMOS Serial Electrically Erasable PROM
FEATURES

DESCRIPTION

•
•
•
•
•
•
•

The Microchip Technology Inc. 85C92 is a 4K bit Electrically Erasable PROM. The device is organized as two
blocks of 256 x 8 bit memory with a two wire serial
interface. Advanced CMOS technology allows a significant reduction in power over NMOS serial devices. The
85C92 also has a page-write capability for up to 8 bytes
of data. Up to four 85C92s may be connected to the two
wire bus. The 85C92 is available in the standard 8-pin
DIP and a surface mount SOIC package.

Low power CMOS technology
Organized as two blocks of 256 bytes (2 x 256 x 8)
Two wire serial interface bus
5 volt only operation
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 8 bytes
1ms write cycle time for single byte
100,000 erase/write cycles
Data retention> 10 years
8-pin DIP or SOIC package
• Available for extended temperature ranges:
-Commercial: O"C to +70"C
-Industrial: -40"C to +85"C
-Automotive: -40"C to + 125"C

PIN CONFIGURATION

BLOCK DIAGRAM

DIP Package
AD

Vee

SCL

Vss

SOA

SDA

SO Package
AD

Vee

SCL

Vss

SOA

SCL
AO A1 A2

1-97

DS11146B-1

85C92
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE

Maximum Ratings·

Name

All inputs and outputs w:r.t. Vss ................ -0.3 V to +7 V
Storage temperature ....................... -65·C to +150·C
Ambient temp. with power applied ..... -65·C to +125·C
Soldering temperature of leads (10 seconds) .. +300·C
ESD protection on all pins ................................... .4 kV

No function. Must be conner.ted to
Vee orVss
Chip address Inputs
Ground
Serial Address/Data 1/0
Serial Clock
No Connect
+5 V Power Supply

AO
Al, A2
Vss
SDA
SCL
NC
Vee

"Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is II stress rating only and
functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specijication is not
implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
r

DC CHARACTERISTICS
Parameter

Function

Vee = + 5 V (±10%)
Commercial (C): Tamb = O"Cto +70"C
Industrial
(I): Tamb = -40"C to +85"C
Automotive (Ei: Tamb = -40"C to +125"C
Conditions
Units

Symbol

Min

Max

Vee detector threshold

VTH

2.8

4.5

SCL and SDA pins:
High level input voltage
Low level input voltage
Low level output voltage

VIH
Vil
VOL

Vee x 0.7
-0.3

Vee + 1
Vee x 0.3
0.4

V
V
V

Al & A2 pins:
High level input voltage
Low level input voltage

VIH
Vil

Vee - 0.5
-0.3

Vee + 0.5
0.5

V
V

IOl = 3.2 mA (SDA only)

Input leakage current

III

j.1A

VIN = 0 V to Vcc

Output leakage current

IlO

j.1A

VOUT = 0 V to Vee

Internal capacitance
(all inputS/outputs)

CINT

7.0

VINNoUT = 0 V (Note 1)
TAMB = 25"C, f = 1 MHz

Operating current

leeo

3.5

4.25

mA
mA
mA
j.1A

FelK = 100 kHz, program cycle
time = 2 ms, Vee = 5 V,
Tamb = O"C to +70"C
FelK = 100 kHz, program cycle
time = 2 ms, Vee = 5 V,
Tamb = (I) and (E)
Vee=5 V, Tamb =O"C to +70"C
Vee = 5 V, Tamb= (I) and (E)
Vee = 5 V, Tamb= (C), (I) and (E)

j.1A

program cycle

leew

read cycle

leeR

7.0
8.5
750

Ices

100

Standby current

SDA = SCL = Vee = 5 V
(no PROGRAM active)

Note 1: ThiS parameter IS periodically sampled and not 100% tested.

BUS TIMING START/STOP

sel _ _-oJ

SDA-----.;....,.

START
OSll1468-2

STOP

1-98

85C92
AC CHARACTERISTICS
Parameter

Symbol

Min

Typ

Max

Units

100

kHz

Clock frequency

FCLK

Clock high time

THIGH

4000

Clock low time

TLOW

4700

SDA and SCl rise time

1000

SDA and SCl fall time

300

Remarks

START condition hold time

THD:STA

4000

After this period the first
clock pulse is generated

START condition setup time

Tsu:sTA

4700

Only relevant for repeated
START condition

Data input hold time

THD:DAT

Data input setup time

TSU:DAT

250

Data output delay time

TPD

300

TSU:STO

4700

TBUF

4700

STOP condition setup time
Bus free time

Input filter time constant
(SDA and SCl pins)
Program cycle time

3500

TI
Twe

.7N

100

See Note 1

Time the bus must be free
before a new transmission
can start

Byte or Page mode N = #
of bytes to be written

SUS TIMING DATA

FUNCTIONAL DESCRIPTION
ter or receiver but the master device determines which
mode is activated.

The 85C92 supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter. and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl). controls the bus access. and generates the
START and STOP conditions. while the 85C92 works as
slave. Both. master and slave can operate as transmit-

Up to four 85C92s can be connected to the bus. selected
by the Aland A2 chip address inputs. AO must be tied
to Vee or Vss. Other devices can be connected to the
bus but require different device codes than the 85C92
(refer to section Slave Address).

1-99

D8111468-3

85C92
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus is not
busy.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as
a START or STOP condition.

The data on the line must be changed during the lOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.

Accordingly, the following bus conditions have been defined (see Figure 1l:

Acknowledge

Bus not Busy CAl

Both data and clock lines remain HIGH.

Note: The 85C92 does not generate any acknowledge
bits if an internal programming cycle is in progress.

Start Data Transfer CBl
A HIGH to lOW transition of the SDA line while the clock
(SCll is HIGH determines a START condition. All commands must be preceded by a START condition.

Stop Data Transfer (Cl
A lOW to HIGH transition olthe SDA line while the clock
(SCll is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

Data Valid (D)

The device that acknowledges, has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable lOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line HIGH to enable the master to
generate the STOP condition.

the state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

FIGURE 1 - DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)

SCl

(A)

(8)

--+---+-'"'-

SOA

START CONDITION

08111468-4

ADDRESS
DATA AllOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID

1-100

STOP
CONDITION

85C92
SLAVE ADDRESS
LOW, are placed onto the bus by the master. This
indicates to the addressed 85C92 that a byte with a word
address will follow after it has generated an acknowledge bit. Therefore the next byte transmitted by the
master is the word address and will be written into the
address pOinter of the 85C92. After receiving the acknowledge of the 85C92, the master device transmits
the data word to be written into the addressed memory
location. The 85C92 acknowledges again and the
master generates a STOP condition. This initiates the
internal programming cycle of the 85C92. (See Figure

The chip address inputs A1 and A2 of each 85C92 must
be externally connected to either Vee or ground (Vss),
assigning to each 85C92 a unique 2-bit address. Up to
four 85C92s may be connected to the bus. Chip selection is then accomplished through software by setting
the bits A1 and A2 of the slave address to the corresponding hardwired logiC levels of the selected 85C92.
AO is not used and must be connected to either Vee or
Vss.
After generating a start condition, the bus master transmits the slave address consisting of a 4-bit device code
(1010) for the 85C92, followed by the chip address bits
A1 and A2. The seventh bit of that byte (BA) is used to
select the upper block (addresses 10D-1FF) or lower
page (addresses OOO-OFF) of the 85C92.

3.)

PAGE PROGRAM MODE
To program the 85C92, the master sends addresses
and data to the 85C92 which is the slave (see Figure 3).
This is done by supplying a START condition followed by
th~4-bit device code, the 3-bit slave address, and the
RIW bit which is defined as a logic LOW for a write. This
indicates to the addressed slave that a word address will
follow so the slave outputs the acknowledge pulse to the
master during the ninth clock pulse. When the word
address is received by the 85C92, it places it in the lower
8 bits of the address pointer defining which memory location is to be written. (The BA bit transmitted with the
slave address is the ninth bitofthe address pointer.) The
85C92 will generate an acknowledge after every 8 bits
received and store them consecutively in an 8-byte RAM
until a STOP condition is detected which initiates the
internal programming cycle. If more than 8 bytes are
transmitted by the master, the 85C92 will roll over and
overwrite the data beginning with the first received byte.
This does not affect eraselwrite cycles of the EEPROM
array and is accomplished as a result of only allowing
the address registers bottom 3 bits to increment while
the upper 5 bits remain unchanged.

The eighth bit of slave address determines if the master
device wants to read or write to the 85C92. (See Figure
2.)
The 85C92 monitors the bus for its corresponding slave
address all the time. It generates an acknowledge bit if
the slave address was true and it is not in a programming
mode.

FIGURE 2· SLAVE ADDRESS
ALLOCATION
START

/'
)
I

: S~V~

READIWRITE

AD9RES:S

:'"(Ami
\

If the master generates a STOP condition after transmitting the first data word (Point 'P' on Figure 3), byte programming mode is entered.

BYTE PROGRAM MODE

The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received (up to 8) data bytes will be
written in a serial manner.

In this mode the master sends addresses and one data
byte to the 85C92.
Following the START condition, theQ.evice code (4-bit),
the slave address (3-bit), and the RIW bit, which is logic

The PROGRAM cycle takes N milliseconds, whereby N
is the number of received data bytes (N max = 8).

FIGURE 3 • PROGRAM MODE (ERASE/WRITE)
ACKNOWLEDGES FROM SLAVE

1-101

OS111469-5

85C92
READ MODE
This mode illustrates master device reading data from
the 85C92.
As can be seen from Figure 4, the master first sets up the
slave and word addresses by doing a write. (Note:
Although this is a read mode, the address pOinter must
be written to.) During this period the 85C92 generates
the necessary acknowledge bits as defined in the appropriate section.
The master now generates another START condition
and transmits the slave address again, except this time
the read/write bit is set into the read mode. After the
slave generates the acknowledge bit, it then outputs the

data from the addressed location on to the SDA pin, increments the address pointer and, if it receives an acknowledge from the master, will transmit the next consecutive byte. This autoincrement sequence is only
aborted when the master sends a STOP condition
instead of an acknowledge.
Note: If the master knows where the address pointer is,
it can begin the read sequence at point 'R' indicated on
Figure 4 and save time transmitting the slave and word
addresses.
In all modes, the address pointer will not increment
through a block (256 byte) boundary but will wraparound
to the first location in that block.

FIGURE 4 - READ MODE

R/W

AUTO INCREMENT
WORD ADDRESS

PIN DESCRIPTION

SCL Serial Clock

This pin must be connected to either vcc or Vss.

This input is used to synchronize the data transfer from
and to the device.

A1. A2 Chip AddresS Inputs
NC No Connect

The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.

This pin can be left open or used as a tie point.

Up to four 85C92s can be connected to the bus.

Notes:

These inputs must be connected to either Vssor Vcc.

1) A "page" is defined as the maximum number of
bytes that can be programmed in a single write cycle.
The 85C92 page is 8 bytes long.

SDA Serial Address/Data Input[Qutput
This isa bidirectional pin used to transfer addresses and
data into and data out of the device. It is an open drain
terminal.
For normal data transfer SDA is allowed to change only
during SCl lOW. Changes during SCl HIGH are reserved for indicating the START and STOP conditions.

0811146B-6

2) A "block" is defined as a continuous area of
memory with distinct boundaries. The address pointer
can not cross the boundary from one block to another.
It will however, wrap around from the end of a block to
the first location in the same block. The 85C92 has
two blocks, 256 bytes each.

H02

85C92
NOTES:

1-103

OSll146B-7

85C92
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.

PART NUMBERS

PACKAGE:

J
P
SM

I
I

TEMPERATURE
RANGE:

DEVICE:

Blank
I
E
85C92
85C92T

DS11146B-8

1-104

eERDIP
Plastic DIP
Plastic sOle (0.207 mil Body)

0' C to +70' C
-40' C to +85' e
-40' C to +125' e
4K CMOS Serial EEPROM
4K CMOS Serial EEPROM
(in Tape & Reel)

85C92
DICE FORM

Microchip

4K (512 X 8) CMOS Serial Electrically Erasable PROM
FEATURES

DESCRIPTION

•
•
•
•
•
•
•
•
•

Low power CMOS technology
Organized as two blocks of 256 bytes (2 x 256 x 8)
Two wire serial interface bus
5 volt only operation
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 8 bytes
1ms write cycle time for single byte
Available in wafer or wafflepack
Temperature range:
-Commercial: O·C to +70·C

DIE CONFIGURATION

BLOCK DIAGRAM

Die Size: 113 x 76 mils
VccVss _

AP
do
di
r n
e t

Slave
Address

se
s r

~~~F=-

1.
2.
3.
4.

AO
A1
A2
Vss

Vcc

6.
5.

SCL

Increment
_
_ _...... A8

AO A1 A2

SDA

1-105

DSll149C-1

85C92

DICE FORM

ELECTRICAL CHARACTERISTICS

PAD FUNCTION TABLE

Maximum Ratings'

Name

All inputs and outputs w.r.t. Vss ................ -0.3 V to +7 V
Storage temperature ....................... -65'C to + 150'C
Ambient temp. with power applied ..... -65'C to + 125'C
Soldering temperature 01 leads (10 seconds) .. +300'C
ESD protection on all pins ................................... .4 kV
*Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions
above those indicated in the operational Ilstings of this specification is
not implied. Exposure to maximum rating conditions for extended
periods

Function

AO,A1,A2

Chip Address Inputs

Vss

Ground

SDA

Serial Address/Data I/O

SCL

Serial Clock

No Function

Vee

+5 V Power Supply

may affect device reliability.

Vee = +5V (±10%)
Commercial: Tamb = O' C to +70' C

DC CHARACTERISTICS
Parameter

Symbol

Min

Max

Units

Vee detector threshold

VTH

2.8

4.5

SCL and SDA pins:
High level input voltage
Low level input voltage
Low level output voltage

VIH
VIL
VOL

Vee x 0.7
-0.3

Vee + 1
Vee x 0.3
0.4

V
V
V

AO, AI & A2 pins:
High level input voltage
Low level input voltage

VIH
VIL

Vee - 0.5
-0.3

Vee + 0.5
0.5

V
V

Conditions

IOL = 3.2 mA (SDA only)

Input leakage current

III

l!A

VIN = 0 V to Vcc

Output leakage current

ILo

l!A

VOUT = 0 V to Vee

Internal capacitance
(all inputs/outputs)

CINT

7.0

VINlVoUT = 0 V (Note 1)
Tamb = +25'C, 1 = 1 MHz

Operating current

leeo

3.5

program cycle

leew

7.0

FeLK = 100 kHz, program cycle
time = 2 ms, Vee = 5 V,
Vee=5 V

read cycle

leeR

750

itA

Vee=5 V

Ices

100

IlA

SDA = SCL = Vee = 5 V
(no PROGRAM active)

Standby current

Note 1: This parameter is periodically sampled and not 100% tested.

BUS TIMING START/STOP

SCL _ _- - f

S D A - - - - - i.....

START

DS11149C-2

STOP

1-106

85C92

DICE FORM

AC CHARACTERISTICS
Parameter

Symbol

Min

Typ

Max

Units

100

kHz

Clock frequency

FeLK

Clock high time

THIGH

4000

Clock low time

TLOW

4700

SDA and SCl rise time

1000

SDA and SCl fall time

300

Remarks

START condition hold time

THD:STA

4000

After this period the first
clock pulse is generated

START condition setup time

TSU:STA

4700

Only relevant for repeated
START condition

Data input hold time

THD:DAT

Data input setup time

TSU:DAT

250

Data output delay time

TPD

300

TSU:STO

4700

TSUF

4700

STOP condition setup time
Bus free ti me

Noise suppression time constant
(SDA and SCl pins)
Program cycle time

TI
Twe

3500

.7N

100

See Note 1

Time the bus must be free
before a new transmission
can start

Byte or Page mode N = #
of bytes to be written

BUS TIMING DATA
SCL
THD:DAT (receiver)

TPD

(transmitter)

SDA

FUNCTIONAL DESCRIPTION
ter or receiver but the master device determines which
mode is activated.

The 85C92 supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl), controls the bus access, and generates the
START and STOP conditions, while the 85C92 works as
slave. Both, master and slave can operate as transmit© 1990 Microchip Technology Inc.

Up to four 85C92s can be connected to the bus, selected
by the A 1 and A2 chip address inputs. AO must be tied
to Vee or Vss. Other devices can be connected to the
bus but require different device codes than the 85C92
(refer to section Slave Address).

1-107

DS11149C-3

85C92

DICE FORM

BUS CHARACTERISTICS
The following bus protocol has been defined:

The data on the line must be changed during the lOW
period of the clock signal. There is one clock pulse per
bit of data.

Data transfer may be initiated only when the bus is
not busy.

Each data transfer is initiated with a start condition and
terminated with a stop condition. The number olthe data
bytes transferred between the start and stop conditions
is determined by the master device and is theoretically
unlimited.

During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (see Figure 1):

Acknowledge

Bus not Busy CA)

Both data and clock lines remain HIGH.

Note: The 85C92 does not generate any acknowledge
bits if an internal programming cycle is in progress.

Start Data Transfer CB)
A HIGH to lOW transition ofthe SDA line while the clock
(SCl) is HIGH determines a START condition. All
commands must be preceded by a START condition.

The device that acknowledges, has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable lOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked outofthe slave. In this case the slave must
leave the data line HIGH to enable the master to generate the STOP condition.

Stop Data Transfer (C)
A lOW to HIGH transition of the SDA line while the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

FIGURE 1" DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

SCL

(C)

(8)

--+---+____

(A)

SDA

START CONDITION

ADDRESS
ACKNOWLEDGE
VALID

DS11149C-4

DATA ALLOWED
TO

CHANG~

H08

STOP
CONDITION

85C92

DICE FORM

SLAVE ADDRESS
indicates to the addressed 85C92 that a byte with a word
address will follow after it has generated an acknowledge bit. Therefore, the next byte transmitted by the
master is the word address and will be written into the
address pointer of the 85C92. After receiving the
acknowledge of the 85C92, the master device transmits
the data word to be written into the addressed memory
location. The 85C92 acknowledges again and the
master generates a STOP condition. This initiates the
internal programming cycle of the 85C92. (See Figure

The chip address inputs A 1 and A2 of each 85C92 must
be externally connected to either Vee or ground (Vss),
assigning to each 85C92 a unique 2-bit address. Up to
four 85C92s may be connected to the bus. Chip selection is then accomplished through software by setting
the bits A 1 and A2 of the slave address to the corresponding hardwired logic levels of the selected 85C92.
AO is not used and must be connected to Vee or Vss.
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1 01 0) for the 85C92, followed by the chip address
bits A 1 and A2. The seventh bit of that byte (PA) is used
to select the upper page (addresses 100-1 FF) or lower
page (addresses OOO-OFF) of the 85C92.

3.)

PAGE PROGRAM MODE
To program the 85C92, the master sends addresses
and data to the 85C92 which is the slave (see Figure 3).
This is done by supplying a start condition followed by
the 4-bit device code, the 3-bit slave address, and the
RIW bit which is defined as a logic LOW for a write. This
indicates to the addressed slave that a word address will
follow so the slave outputs the acknowledge pulse to the
master during the ninth clock pulse. When the word
address is received by the 85C92, it places it inthe lower
8 bits of the address pointer defining which memory
location is to be written. (The PA bit transmitted with the
slave address is the ninth bitofthe address pointer.) The
85C92 will generate an acknowledge after every 8 bits
received and store them consecutively in an 8-byte RAM
until a STOP condition is detected which initiates the
internal programming cycle. If more than 8 bytes are
transmitted by the master, the 85C92 will roll over and
overwrite the data beginning with the first received byte.
This does not affect erase/write cycles of the EEPROM
array and is accomplished as a result of only allowing
the address registers bottom 3 bits to increment while
the upper 5 bits remain unchanged.

The eighth bit of slave address determines if the master
device wants to read or write to the 85C92. (See Figure

2.)
The 85C92 monitors the bus for its corresponding slave
address all the time. It generates an acknowledge bit if
the slave address was true and it is not in a programming
mode.

FIGURE 2 - SLAVE ADDRESS
ALLOCATION
START

/""
/

READIWRITE

: S~V~ AD~RES:S

IRiWl A
'\

'\
'\

I I I
0

If the master generates a STOP condition after transmitting the first data word (Point 'P' on Figure 3), byte
programming mode is entered.

BYTE PROGRAM MODE

The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received (up to 8) data bytes will be
written in a serial manner.

In this mode the master sends addresses and one data
byte to the 85C92.
Following the START condition, the ~vice code (4-bit),
the slave address (3-bit), and the RIW bit, which is logic
LOW, are placed onto the bus by the master. This

The PROGRAM cycle takes N milliseconds, whereby N
is the number of received data bytes (N max = 8).

FIGURE 3 - PROGRAM MODE (ERASEIWRITE)

START

ACKNOWLEDGES FROM SLAVE

DATA BYTE 1

A STOP

1-109

DS11149C-5

85C92

DICE FORM

READ MODE
This mode illustrates master device reading data from
the 85C92.
As can beseen from Figure 4, the master first sets up the
slave and word addresses by doing a write. (Note:
although this is a read mode the address pointer must be
written to.) During this period the 85C92 generates the
necessary acknowledge bits as defined in the appropriate section.
The master now generates another START condition
and transmits the slave address again, except this time
the read/write bit is set into the read mode. After the
slave generates the acknowledge bit, it then outputs the

data from the addressed location on to the SDA pad,
increments the address pointer and, if it receives an
acknowledge from the master, will transmit the next
consecutive byte. This autoincrement sequence is only
aborted when the master sends a STOP condition
instead of an acknowledge.
Note: If the master knows where the address pointer is,
it can begin the read sequence at point 'R' indicated on
Figure 4 and save time transmitting the slave and word
addresses.
Note: In all modes, the address pOinter will never
automatically increment through a block (256 byte)
boundary but will rotate back to the first location in that
block.

FIGURE 4 - READ MODE

AUTO INCREMENT
WORD ADDRESS

PAD DESCRIPTION
SCL Serial Clock
This pad must be connected to either Vee or Vss.

A1. A2 Chip Address Inputs
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.

This input is used to synchronize the data transfer from
and to the device.

NF No Function
This pad must be connected to Vss for normal operation.

Up to four 85C92s can be connected to the bus.
These inputs must be connected to either Vee or Vss.

SDA Serial Address/Data Input/Output
This is a bidirectional pad used to transfer addresses
and data into and data out of the device. It is an open
drain terminal.
For normal data transfer SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are reserved for indicating the START and STOP conditions.

DSll149C-6

1-110

1990 Microchip Technology Inc.

85C92

DICE FORM

NOTES:

1-111

DS11149C-7

85C92

DICE FORM

SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.

PART NUMBERS

W
S

DS11149C-8

O' C to 70' C

TEMPERATURE
RANGE:

DEVICE:

DICE in WAFER
DICE in WAFFLEPACK

85C92

1-112

4K CMOS SERIAL EEPROM

93C06

Microchip

256 Bits (16 X 16) CMOS Serial Electrically Erasable PROM

FEATURES

DESCRIPTION

•
•
•
•
•
•
•
•
•
•

The Microchip Technology Inc. 93C06 is a 256 bit serial
Electrically Erasable PROM. The device memory is configured as 16 x 16 bits. Advanced CMOS technology
makes this device ideal for low power non-volatile memory
applications. The 93C06 is available in the standard 8pin DIP and a surface mount SOIC package.

Low power CMOS technology
16 x 16 bit memory organization
Single 5 volt only operation
Self-timed ERASE and WRITE cycles
Automatic ERASE before WRITE
Power on/off data protection circuitry
100,000 ERASElWRITE cycles
Data Retention> 10 Years
8-pin DIP or SOIC package
Available for extended temperature ranges:
- Commercial: O'C to +70'C
- Industrial: -40'C to +85'C
- Automotive: -4O'C to +125'C

PIN CONFIGURATION

BLOCK DIAGRAM

DIP Package
Vee

Vas

Vee
NU

NU
Vss
00
DI

SO Package
os

Vee

CLK

v••

ClJ(

1-113

DS11150C-1

93C06
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE

Maximum Ratings*
All inputs and outputs W.r.t. Vss .............. -0.3 V to +7.0 V
Storage temperature ............................ -65°C to + 150°C
Ambient temperature with
power applied ...................................... -65°C to + 125°C
Soldering term perature of leads (10 seconds) ... +300°C
ESD protection on all pins ..................................... .4 kV
"'Notice: Stresses above those listed under "Maximum ratings" may

Name

Function

CS
ClK
DI
DO
Vss
NU
Vee

Chip Select
Serial Clock
Data In
Data Out
Ground
Not Utilized. No Connection
+5 V Power Supply

may affect device reliability.

Vee = +5 V (±10%)
Commercial: Tamb=
O°C to +70°C
Tamb = -40°C to +85°C
Industrial:
Automotive:
Tamb = -40°C to +125°C

DC CHARACTERISTICS
Parameter
1--

Symbol

Min

Max

Units

Vce detector threshold

VTH

2.8

4.5

High level input voltage

VIH

2.0

Vee + 1

0.8

Conditions

low level input voltage

VIL

-0.3

Hlgh level output voltage

VOH

2.4

low level output voltage

VOL

0.4

Input leakage current

III

J.LA

VIN = 0 V to Vee (Note 1)

Output leakage current

ILO

/lA

VOUT = 0 V to Vee (Note 1)

Internal capacitance
(all inputs/outputs)

CINT

VINNoUT = 0 V~Note 2)
T amb = +25'C, = 1 MHz

Operating current
(all modes)

leeo

FeLK = 1 MHz, Vee = 5.5 V

Standby current

Ices

100

J.LA

CS = Vss, Vee = 5.5 V

10H = -400 /lA
10L = 3.2 mA

Note 1: Internal resistor pull-up at Pin 6.
Note 2: This parameter is periodically sampled and not 100% tested.

SYNCHRONOUS DATA TIMING

eLK

DS11150C-2

1-114

93C06
AC CHARACTERISTICS
Symbol

Parameter

Min

Max
1

Units
MHz

Clock frequency

FCLK

Clock high time

TCKH

500

Clock low time

TCKL

500

Chip select setup time

Tcss

Chip select hold time

TCSH

Chip select low time

TCSL

100

Data input setup time

To IS

100

Data input hold time

TOIH

100

Data output delay time

Tpo

Data output disable time (from CS

= low)

Conditions

= 100 pF
= 100 pF
= 100 pF

Tcz

100

400

100

Cl - 100 pF

ms
ms

for ERAl and WRAl

Data output disable time (from last clock)

Tooz

Status valid time

Tsv

Program cycle time (Auto Erase & Write)

Twc

Erase cycle time

TEC

400

PIN DESCRIPTION
Chip Select (CS)
A HIGH level selects the device. A lOW level deselects
the device and forces it into standby mode. However, a
programming cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought lOW during a program cycle, the
device will go into standby mode as soon as the pro·
gramming cycle is completed.
CS must be lOW for 100 ns minimum (TCSL) between
consecutive instructions. If CS is lOW, the internal
control logic is held in a RESET status.

Serial Clock (ClK)
The Serial Clock is used to synchronize the communi·
cation between a master device and the 93C06. Op·
code, address, and data bits are clocked in on the
positive edge of ClK. Data bits are also clocked out on
the positive edge of ClK.
ClK can be stopped anywhere in the transmission
sequence (at HIGH or lOW level) and can be continued
anytime (with respect to clock HIGH time (TCKH) and
clock lOW time (TCKL). This gives the controlling master
freedom in preparing opcode, address and data.
ClK is a "Don't Care" if CS is lOW (device deselected).
If CS is HIGH, but START condition has not been de·
tected, any number of clock cycles can be received by
the device without changing its status. (i.e., waiting for
START condition).

ClKcycles are not required during the self·timed WRITE
(i.e,. auto ERASEIWRITE) cycle.
After detection of a START condition, the specified
number of clock cycles (respectively lOW to HIGH tran·
sitions of ClK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (see instruc·
tion set truth table). ClK and 01 then become "Don't
Care" inputs waiting for a new start condition to be
detected.
Note: CS must go lOW between consecutive instruc·
tions.

Data In (On
Data In is used to clock in a Start bit, opcode, address,
and data synchronously with the ClK input.

Data Out (DO)
Data Out is used in the READ mode to output data
synchronously with the ClK input (Tpo after the positive
edge of ClK).
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY status
information is available on the DO pin if CS is brought
high after being low for minimum chip select lOW time
(TCSL) from the falling edge of the ClK which clocked in
the last 01 bit (DO for WRITE, AO for ERASE) and an
ERASE or WRITE operation has been initiated.

1·115

DSll150C·3

93C06
Care must be taken with the leading dummy zero which
is outputted after a READ command has been detected.
Also, the controlling device must not drive the 01/00 bus
during ERASE and WRITE cycles if the READY/BUSY
status information is output by the 93COS.

The status signal is not available on DO, if CS is held
LOW or HIGH during the entire WRITE or ERASE cycle.
In all other cases DO is in the HIGH-Z mode. If status is
checked after the WRITE/ERASE cycle, a pull-up resistor on DO is required to read the READY signal.
01 and DO can be connected together to perform a 3wire interface (CS, ClK, 01/00).

INSTRUCTION SET
Instruction
READ
WRITE
ERASE
EWEN
EWDS
ERAL
WRAl

Start
BIT

Opcode
OP10P2

1
1
1

1 0
0 1
1 1

1
1
1
1

0 0
0 0
0 0
0 0

Humber of
Data In

Address
0
0
0
1
0
1
0

0
0
0
1
0
0
1

A3 A2

A1
A3 A2 A1
A3 A2 A1

AO
AO

X
X
X
X

015-00
-

015-00

Data Out

Req. elK Cycles

015-00
(RDY/BSY)
(RDY/BSY)
High-Z

25
25

High·Z
(RDY/BSY)
(RDY/BSY)

9
9
9
9
25

FUNCTIONAL DESCRIPTION
START Condition
The start bit is detected by the device if CS and 01 are
both HIGH with respect to the positive edge of ClK for
the first time.
Before a START condition is detected, CS, ClK, and 01
may change in any combination (except to that of a
START condition), without resulting in any device opera·
tion (READ, WRITE, ERASE, EWEN, EWDS, ERAl,
and WRAl). As soon as CS is High, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address and
data bits for any particular instruction is clocked in.
After execution of an instruction (Le., clock in or out of
the last required address ordata bit) ClKand 01 become
don't care bits until a new START condition is detected.

It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a "bus conflict" to occur during the "dummy zero" that
precedes the READ operation, if AO is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
AO. The higher the current sourcing capability of AO, the
higher the voltage at the Data Out pin.

Data Protection and Noise Immunity

During power-down, the source data protection circuitry
acts to inhibit all modes when Vee has fallen below the
range of 2.8 V to 4.5 V.
The EWEN and EWDS commands give additional protection against accidentally programming during normal
operation.
After power-up, the device is automatically in the EWDS
mode. Therefore, an EWEN instruction must be per·
formed before any ERASE, or WRITE instruction can be
executed.

READ Mode
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy bit
(logical 0) precedes the 1S-bit output string. The output
data changes during the high state of the system clock
(ClK). The dummy bit is output TPD after the positive
edge of ClK, which was used to clock in the last address
bit (AO). Therefore, care must be taken if 01 and DO are
connected together as a bus contention will occur for
one clock cycle if AO has been a "1".
DO will go into HIGH-Z mode with the positive edge of
the next ClK cycle. This follows the output of the last
data bitDO orthe negative edge of CS, whichever occurs
first.
DO remains stable between ClK cycles for an unlimited
time as long as CS stays HIGH.
The most significant data bit (015) is always output first,
followed by the lower significant bits (014 . DO).

During power-up, all modes of operation are inhibited
until Vee has reached a level of between 2.8 Vand 4.5 V.
DS11150C·4

1-116

93C06
READ MODE

CLK

~"r-------------------~~~~------------~~
SB

DI_

ThSL

I~I

III

OP1

OP2

lAO

~'--_~----La_,m""""l-~__
II
__
TPo __ 1t4-

DO - - - - - - - - - - - - - - - - - - - - - HIGH-Z

''I;

Tooz

~~
NEW INSTRUCTION
OR STANDBY (CS = 0)

WRITE Mode
The WRITE instruction is followed by 16 bits of data
which are written into the specified address. The most
significant data bit (015) has to be clocked in first,
followed by the lower significant data bits (014 - ~O). If
a WRITE instruction is recognized by the device and all
data bits have been clocked in, the device performs an

WRITE MODE

automatic ERASE cycle on the specified address before
the data are written. The WRITE cycle is completely selftimed and commences automatically after the rising
edge of the elK signal for the last data bit (~O).
The WRITE cycle takes 2 ms max.

CLK
_ _ I TeSL

14- ~ TeSL

cs ~r'-~--------------------~~~-----------+:~~~~
SB

OP1

OP2

D15

CHECK

I
I

~----:---f-a~;;~~;m;~E9fol\U"l---L---l--1i--1i---L---_
1

...-J ~

~~Tsv

Tooz

HIGH -Z

-------------~~i--i----~JiRoY~
I _ Twe _ _ I
I

NEW INSTRUCTION
OR STANDBY (CS = 0)

ERASE Mode
The ERASE instruction forces all the data bits of the
specified address to logical "1s". The ERASE cycle is
completely self-timed and commences automatically

after the last address bit has been clocked in.
The ERASE cycle takes 1 ms max.

~I
_ _I TesL 1___

ERASE MODE
~I

TeSL

,-,r---------------------------~~I
-.ill
I '\
~.:r
: ~i
i'--.l'
I

CHECK

DI~

OP1

OP2

'1f::A~;nvn

I
DO

/'----,\'--_~~~~

HIGH - Z

I_Tooz

T8v __ 1 ~
'I - -

--------l-----1f---..,... BSY I ROY I

~......-

TEe

NEW INSTRUCTION
OR STANDBY (CS =0)

DS11150C-5

93C06
ERASEIWRITE Enable/Disable (EWEN. EWDS)
instruction has to be performed before any ERASE,
WRITE, ERAL, WRAL instruction is executed by the
device.

The device is automatically in the ERASEIWRITE Disable mode (EWOS) after power-up. Therefore, an EWEN

ERASEIWRITE
ClK ~~~J
ENABLE/DISABLE
I
'7",..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~Ics
DI

mo,

Tesl -.-1 _ _ __

,-----+--'

OP1

OP2

~~
o
0
(EWDS) Ji ;
1

(EWEN)

NEW INSTRUCTION
OR STANDBY (CS = 0)

ERASE All (ERAL)
The entire chip will be erased to logical "1 s" if this instruction is received by the device and it is in the EWEN mode.
The ERAL cycle is completely self-timed and com-

mences after the last dummy address bit has been
clocked in.
ERAL takes 15 ms max.

ERASE ALL

DO - - - - - - - - - - - - HIGH·Z - - - - - j - - - j ) - - - - i BSY I

~Twe~
NEW INSTRUCTION

OR STANDBY ICS - 0)

WRITE All (WRAL)
The entire chip will be written with the data specified in
that command. The WRAL cycle is completely selftimed and commences after the last data bit (~O) has
been clocked in. WRAL takes 15 ms max.
Note: The WRAL does not include an automatic erase

WRITE ALL

cycle forthe chip. Therefore, the WRAL instruction must
be preceded by an ERAL instruction and the chip must
be in the EWEN status in both cases.
The WRAL instruction is used for testing and/or device
initialization.

CLK~LflSLflSLJLJLrL~~
~

~------------------------~Ii

OP1

QP2

015

1_._

I DO

CHECK

TeSL

~
STATUS

~~-=------=-~/'1'~"""""'X=""x=""'x"""'WW 10 years
8-pin DIP or SOIC package
• Available for extended temperature ranges:
- Commercial: O·C to +70·C
- Industrial: -40·C to +8S·C
- Automotive: -40·C to + 12S·C

BLOCK DIAGRAM

PIN CONFIGURATION

DIP Package

esO'·

CLK2

Vee

7NU

013

6NU

004

SVss

eso.

S:ePaCka9:SO. NU

elK

Vee

Vss

013

6NU

eS3

600

004

5vss

CLK4

50t

93C46

Vss

es
01

elK

93C46X

1-129

DS20041C-1

93C46
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE

Maximum Ratings'
All inputs and outputs w.r.t. Vss .............. -0.3 V to +7.0 V
Storage temperature ............................ -65°C to +150°C
Ambient temperature with
power applied ........................................ -65°C to + 125C
Soldering termperature of leads (10 seconds) ... +300°C
ESO protection on all pins ..................................... .4 kV
*Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended periods

Name

Function

CS
ClK
01
DO
Vss
NU
Vee

Chip Select
Serial Clock
Data In
Data Out
Ground
Not Utilized. No Connection
+5 V Power Supply

L_.. _ _

may affect device reliability.

Vee = +5 V (±10%)
Commercial: Tamb= O°C to +70°C
Tamb = -40°C to +85°C
Industrial:
Automotive:
Tamb = -40°C to + 125°C

DC CHARACTERISTICS
Parameter

Symbol

Min

Vec detector threshold

VTH

High level input voltage

VIH

low level input voltage

Conditions

Max

Units

2.8

4.5

2.0

Vce + 1

VIL

-0.3

0.8

High level output voltage

VOH

2.4

low level output voltage

VOL

0.4

Input leakage current

III

IJA

VIN = 0 V to Vee (Note 1)

Output leakage current

ILO

j.lA

VOUT = 0 V to Vec (Note 1)

Internal capacitance
(all inputs/outputs)

CINT

VINlVoUT = 0 V INote 2~
Tamb = +25°C, = 1 M z

Operating current
(all modes)

Iceo

FeLK = 1 MHz, Vee = 5.5 V

Standby current

Ices

100

IJA

CS = 0 V, Vee = 5.5 V

V
V

IOH = -400 IJA
IOL =3.2 mA

Note 1: Internal resistor pull-up at Pin 6.
Note 2: This parameter is periodically sampled and not 100% tested.

SYNCHRONOUS DATA TIMING

ClK

DS20041C-2

1-130

93C46
AC CHARACTERISTICS
Parameter

Symbol

Min

Max

Units

Clock frequency

FCLK

Clock high time

TCKH

500

Clock low time

TCKL

500

Conditions

MHz

Chip select setup time

Tcss

Chip select hold time

TcsH

Chip select low time

TCSL

100

Data input setup time

TOls

100

Data input hold time

TOIH

100

Data output delay time

Tpo

Data output disable time (from CS = low)

Tcz

Data output disable time (from last clock)

Tooz

ns
400

100

Cl = 100 pF
Cl = 100pF

400

Cl = 100pF

-~~

Status valid time

Tsv

100

Cl = 100pF

Program cycle time (Auto Erase & Write)

Twc

ms
ms

for ERAl and WRAl

Erase cycle time

TEC

PIN DESCRIPTION
Chip Select (CS)
A HIGH level selects the device. A lOW level deselects
the device and forces it into standby mode. However, a
programming cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought lOW during a program cycle,
the device will go into standby mode as soon as the programming cycle is completed.
CS Irlust be lOW for 100 ns minimum (TCSL) between
consecutive instructions. If CS is lOW, the internal
control logic is held in a RESET status.

Serial Clock (ClK)
The Serial Clock is used to synchronize the communication between a master device and the 93C46. Opcode, address, and data bits are clocked in on thE"
positive edge of ClK. Data bits are also clocked out 0 I
the positive edge of ClK.
ClK can be stopped anywhere in the transmission
sequence (at HIGH or lOW level) and can be continued
anytime (with respect to clock HIGH time (TCKH) and
clock lOW time (TCKL). This gives the controlling master
freedom in preparing opcode, address and data.
ClK is a "Don't Care" if CS is lOW (device deselected).
If CS is HIGH, but STARTcondition has not been detected, any number of clock cycles can be received by
the device without changing its status. (i.e., waiting for
START condition).

ClKcycles are not required during the self-timed WRITE
(i.e., autoERASE/WRITE) cycle.
After detection of a start condition, the specified number
of clock cycles (respectively lOW to HIGH transitions of
ClK) must be provided. These clock cycles are required
to clock in all required opcode, address, and data bits
before an instruction is executed (see instruction set
truth table). ClK and 01 then become "Don't Care"
inputs waiting for a new start condition to be detected.
Note: CS must go lOW between consecutive instructions.

Data In (On
Data In is used to clock in a START bit, opcode, address,
and data synchronously with the ClK input.

Data Out (DO)
Data Out is used in the READ mode to output data
synchronously with the ClK input (TpDafter the positive
edge of ClK).
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY status
information is available on the DO pin if CS is brought
HIGH after being lOW for minimum chip select lOW
time (TcsL) from the falling edge of the ClK which
clocked in the last 01 bit (DO for WRITE, AO for ERASE)
and an ERASE or WRITE operation has been initiated.

1-131

DS20041C-3

93C46
The status signal is not available on DO, if CS is held
lOW or HIGH during the entire WRITE or ERASE cycle.
In all other cases DO IS in the HIGH-Z mode. If status is
checked after the WRITE/ERASE cycle, a pull-up resistor on DO is required to read the READY signal.

Care must be taken with the leading dummy zero which
is outputted after a READ command has been detected.
Also, the controlling device must not drive the 01/00 bus
during Erase and Write cycles if the. READY/BUSY
status information is outputted by the 93C46.

01 and DO can be connected together to perform a 3wire interface (CS, ClK, 01/00).

INSTRUCTION SET
Instruction
READ
WRITE
ERASE
EWEN
EWOS
ERAL
WRAL

Start
BIT
1
1,
1
1
1
1
1

Opcode
OP10P2
1
0
1
0
0
0
0

0
1
1
0
0
0
0

Number of
Data In

Address
A5 A4 A3A2 A1 AO
AS A4 A3 A2 A1 AO
A5 A4 A3 A2 A1 AO
1 1 X X X X
0 0 X X X X
1 0 X X X X
0 1 X X X X

015-00

Data Out

Req. elK Cycles

015-00
(ROYIBSY)
(ROY/BSY)
High-Z
High-Z
(ROY/BSY)
(ROY/BSy)

25
25
9
9
9
9
25

FUNCTIONAL DESCRIPTION
START Condition
The START bit is detected by the device if CS and 01 are
both HIGH with respect to the positive edge of ClK for
the first time.
Before a START condition is detected, CS, ClK, and 01
may change in any combination (except to that of a
START condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAl,
and WRAl). As soon as CS is HIGH, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address and
data bits for any particular instruction is clocked in.
After execution of an instruction (I.e., clock in or out of
the last required address or data bit) ClK and 01
become don't care bits until a new start condition is
detected.
~

It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a "bus conflict" to occur during the "dummy zero" that
precedes the READ operation, if AO is a logic HIGH
level. Under such a condition the voltage leyel seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
AO. The higher the current sourcing capability oIAO, the
higher the voltage at the Data Out pin.

Data protection
During power-up, all modes of operation are inhibited
until Vee has reached a level of between 2.8 Vand 4.5 V.
During power-down, the source data protection circuitry
DS20041C-4

acts to inhibit all modes when Vee has fallen below the
range of 2.8 V to 4.5 V.
The EWEN and EWDS commands give additional protection against accidentally programming during normal
operation.
After power-up, the device is automatically in the EWDS
mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be
executed.

READ Mode
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy bit
(logical 0) precedes the 16-bit output string. The output
data changes during the HIGH state of the system clock
(ClK). The dummy bit is output TPD after the positive
edge of ClK, which was used to clock in the last address
bit (AO). Therefore, care must be taken if 01 and DO are
connected together as a bus contention will occur for
one clock cycle if AO has been a one.
DO will go into HIGH-Z mode with the positive edge of
the next ClK cycle. This follows the output of the last
data bit DO or the low going edge of CS, which ever
occurs first.
DO remains stable between ClK cycles for an unlimited
time as long as CS stays HIGH.
The most significant data bit (015) isalways'output first,
followed by the lower significant bits (014 - DO).

1-132

93C46
READ MODE

ClK

~~'---------------------~~--T---------------~
SB

DID

ThSl

I~I

/77

OP1

OP2

;---\ Ii l&

lAO

m: 2&~ ~~
I
Tpo __ l~

DO - - - - - - - - - - - - - - - - - - - - HIGH - Z

----~1lT_--",

Tooz

rw=x:::J~

NEW INSTRUCTION
OR STANDBY (CS = 0)

automatic ERASE cycle on the specified address before
the data are written. The WRITE cycle is completely selftimed and commences automatically after the rising
edge of the elK for the last data bit (~O).
The WRITE cycle takes 2 ms max.

WRITE MODE
~I TeSl ~ -------' TeSl ~
r,-,---------------------~~~----------~I
~
$-I
I~ STATUS I~

cs ---.-LV

OP1

OP2

DI~

'<&:

:m:

»Z

015

I DO

m! zm< 2ijU

CHECK

~Tooz

• I

~_Tsv

00------------------- HIGH - Z

-------------~~T-:----~,ifoY':---

I_Twc
- - I,
1

NEW INSTRUCTION
OR STANDBY (CS 0)

ERASE Mode
The ERASE instruction forces all the data bits of the
specified address to logical "1s". The ERASE cycle is

completely self-timed and commences automatically
after the last address bit has been clocked in.
The ERASE cycle takes 1 ms max.

ERASE MODE

=X"U~<=""""""lll!I----,1

CLK

Ii!
-------'--LI

I
I

01!lQl&

TeSL

,.,.,----------------------------r----,I

OP1

OP2

lAO

~ ~

'\~; CHECK

;"---11

~m~~

Tsv __ l~
DO - - - - - - - - - - - - - - - - - - - HIGH - Z

Tesl

~-r-

------~~---%----I_e.1 BSY

I_Tooz

I
I ROY

NEW INSTRUCTION
OR STANDBY (CS • 0)

1-133

DS20041C-5

93C46
ERASE/WRITE Enable/Disable (EWEN. EWDS)
EWEN instruction has to be performed before any
ERASE, WRITE, ERAL, WRAL instruction is executed
by the device.

The device is automatically in the ERASEIWRITE Disable mode (EWDS) after power-up. Therefore, an

ERASEIWRITE
ClK ~~~J
ENABLE/DISABLE
cs
DI

~TCSl~

~--------------------~{.''-----If---/'~,--------.iZ/
S8

mo,

OP1

OP2

I\~----L~""----\'i--~;o

0
1

(EWDS)
(EWEN)

NEW INSTRUCTION
OR STAND8Y (CS = 0)

ERASE All (ERAL)
The entire chip will be erased to logical "1 s" if this instruction is received by the device and it is in the EWEN mode.
The ERAL cycle is completely self-timed and com-

ERASE ALL

ClK

ERAL takes 15 ms max.

~Ir

"""'''''''''''''''_...J

TcsL

-.-I

TcsL

/~/n-/------------------------------~1--4
~;r-----LLI
I
~!1 ';;';~~~ 1"-/1
S8

mences after the last dummy address bit has been
clocked in.

OP1

OP2

'fY'I''''''''--c>S----+I-----!''--"""~
I
I

ITDDz~

r---

Tsv.....,

D O - - - - - - - - - - - - - - - - - - - - - - - HIGH - z ----------jf----+-----i

NEW INSTRUCTION
OR STAND8Y (CS 0)

WRITE All (WRAL)
The entire chip will be written with the data specified in
that command. The WRAL cycle is completely selftimed and commences after the rising edge of the eLK
for the last data bit (DO). WRAL takes 15 ms max.
Note: The WRAL does not include an automatic ERASE

WRITE ALL
~

TCSL

OP1

OP2

r---;""""""",ww="""""",ow;;~D",15,,=-

STATUS
CHECK

I DO

~0~-,:---:----;:--I/ 1 ~ $~/!C't--'-~'---- f (0)

3,0
RXBUF,O
BITIN
EEPROM,DI
RXBUF,O
COUNT
RXLP
EEPROM,DO
BITOUT
0

Input bit =1
8 bits?
Set acknowledge bit =
to STOP further input

SUB

;---------------------------------------------------TRANSMIT

DATA

subroutine

i---------------------------------------------------Input
Output

TXBUF
Data X'mitted to EEPROM device

i---------------------------------------------------TX
0127 6010
0130 0066

MOVLW
MOVWF

.8
COUNT

TXLP
0131 2312
0132 3364

BCF
BTFSC

EEPROM, DO
TXBUF,7

0133
0134
0135
0136
0136
0137
0140
0140
0141
0142
0143
0144
0145
0146

BSF
CALL
RLF
SKPC
BTFSS
BCF
SKPNC
BTFSC
BSF
DECFSZ
GOTO
CALL
MOVLW
BTFSC

EEPROM,DO
BITOUT
TXBUF

CALL

ERR

2712
4454
1564
3403
2024

3003
2424
1366
5131
4434
6003
3352

0268 0147 4400

3,0
TXBUF, 0
3,0
TXBUF,O
COUNT
TXLP
BITIN
3
EEPROM,DI

Shift data bit out.
If shifted bit=O, data
bit = 0
Otherwise data bit = 1
Serial data out
Rotate TXBUF left
f(6) ---> f(7)
f (7) ---> carry
carry ---> f (0)

8 bits done?
No.
Read acknowledge bit
Check for
acknowledgement
No acknowledge from
device

0269 0150 4000
RETLW
o
0270
0271
;END SUB
0273
0274
i---------------------------------------------------0275
BYTE-WRITE, write one byte to EEPROM device
0276
;---------------------------------------------------0277
Input
DATAO = data to be written
0278
ADDR = destination address
0279
SLAVE = device address t1010xxxO)
Data written to EEPROM device
0280
Output
0281
i---------------------------------------------------0282

DS00515A·8

1-152

COMMUNICATING WITH TWO WIRE/12C BUS

0283 0200

ORG

200

The location for BYTEWRITE routine can be
assigned anywhere
between (377- 777)
octal.

SLAVE,W
TXBUF
BSTART
TX
ADDR,W
TXBUF
TX
DATAO,W
TXBUF
TX

Get SLAVE address
to TX buffer
Generate START bit
Output SLAVE address
Get WORD address
into buffer
Output WORD address
Move DATA
into buffer
Output DATA and detect

0284

0285
0286
0287
0288
0289
0290
0291
0292
0293
0294
0295

0200
0201
0202
0203
0204
0205
0206
0207
0210
0211

WRBYTE
1023
MOVF
0064
MOVWF
4404
CALL
4527
CALL
1020
MOVF
0064
MOVWF
4527
CALL
1022
MOVF
0064
MOVWF
4527
CALL

acknowledgement

0296 0212 4420
CALL
BSTOP
Generate STOP bit
0297
0298
0299
0300
;---------------------------------------------------0301
BYTE-READ, read one byte from serial EEPROM
device
0302
ADDR
0303
Input
source address
0304
SLAVE = device address (1010xxxO)
0305
Output
DATAl = data read from serial
EEPROM
0306
;--~-----------------------------------------------0307
0308 0300
ORG
300
The location for BYTEREAD routine can be
0

______ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

assigned

0309
0310
0311
0312
0313
0314

between
0300
0301
0302
0303

RDBYTE
1023
MOVF
0064
MOVWF
4404
CALL
4527
CALL

SLAVE,W
TXBUF
BSTART
TX

0315 0304 1020
0316 0305 0064
0317 0306 4527

MOVF
MOVWF
CALL

ADDR,W
TXBUF
TX

0318 0307 4404

CALL

BSTART

0319 0310 1023

MOVF

SLAVE,W

0320 0311 0064
0321.0312 2424

MOVWF
BSF

TXBUF
TXBUF,O

0322 0313 4527
0323 0314 4507

CALL
CALL

TX
RX

0324 0315 4420
0325 0316 1065
0326 0317 0061
0327
0328
0329
END
0330

CALL
MOVF
MOVWF

BSTOP
RXBUF
DATAl

%ASM-I,

No Warnings

No Errors,

1-153

anywhere

(377-777)

octal.

Move SLAVE address
into buffer (R/W = 0)
Generate START bit
Output SLAVE address.
Check ACK.
Get WORD address
Output WORD address.
Check ACK.
START READ (if only one
device
is connected to the 12C
bus)
Specify READ mode
(R/W = 1)
Output SLAVE address
READ in data and
acknowledge
Generate STOP bit
Save data from buffer
to DATAl file.

DS00515A-9

COMMUNICATING WITH TWO WIRE/12C BUS

NOTES:

DS00515A'-10

1-154

_Microchip

APPLICATION NOTES

ERS92S6/93C06 AND NMC9306/NMC93C06
COMPATIBILITY ISSUE

Introduction
The ER59256 and 93C06 are 256 bits (16 x 16) serial EEPROM currently offered by
Microchip. ER59256 is fabricated in N-channel SNOS technology and 93C06 in
advanced CMOS. There are some uncertainties in the field regarding the compatibility
between Microchip's 256 bits serial EEPROM and National. Namely NMC9306 and
NMC93C06. This report highlights the differences.

Software Differences
Microchip

Microchip

ER59256

I~SIBUQIIQ~

sa~

READ

1000

A3A2A1AO

sa~

1000

A3A2A1AO

WRITE

0100

A3A2A1AO

0100

A3A2A1AO

ERASE

1100

A3A2A1AO

1100

A3A2A1AO

ll8IA

D15 - DO

National

93C06
ll8IA
D15 - DO

sa
1

NMC9306/NMC93C06

QEQ.QQl;.

10XX

A3A2A1AO

a 1 xx

A3A2A1AO

11 XX

A3A2A1AO

EWEN

0011

00 0 0

0011

XXXX

0011

XXXX

EWDS

0000

XXXX

0000

XXXX

ERAL

0010

0 0

0010

XXXX

0010

XXXX

0001

XXXX

0001

XXXX

WRAL

Note:

NOT SPECIFIED

EWEN ..... EraseIWrite Enable
EWDS ..... EraseIWrite Disable

D15- 00

015- DO

015-00

ERAL ..... Erase All
WRAL .... Write All

From the instruction sets shown, the address bits on EWEN, EWOS, ERAL and WRAL
are "don't care" for 9306/93C06 and all logical O's for ER59256. The WRAL instruction is
not specified for ER59256. The two LSB of the opcode are "0 0" for Microchip's
ER59256/93C06 and "don't care" for National's NMC9306/NMC93C06. In order to make
software fully compatible to all parts, it is recommended to design program with all logical
O's in place of the "don't care" bits.
Polling is available on the 93C06 and NMC93C06. The soft polling can be done by
checking the status signal on the DO line (pin 4). A low busy signal (BSY) indicates the
device is still in the programming mode and a high level (ROY) represents the device is
ready to receive new instruction. ER59256 and NMC9306 however, do not provide this
feature.

DS00516A-1

1-155

ER59256/93C06

AND

NMC9306/NMC93C06

Hardware Differences
Microchip

National

PARAMETER

tlIMQaaQQIl

PIN6
PIN 7

TEST

NC
NC

ClOCKFREQ

250 KHZ

1 MHZ

250 KHZ

1 MHZ

ClK DUTY CYCLE
ClK HIGH TIME min.

25%-75%
not specified

not specified
500 ns

not specified
1 us

250 ns

ClK lOW TIME min.
CS lOW TIME min.

not specified
not specified
10K

500 ns
100 ns
100K

1 us
1 us
40K

250 ns
250 ns
40K

4.0KV

2.0KV
10-30ms

2.0KV

ENDURANCE
ESDRATING
ElWTIME
ACTIVE CURRENT
STANDBY CURRENT

1.0KV
10 - 30 ms
10mA

2ms
4mA

3mA

100 uA

not specified

10mA

10ms
3mA

3mA

50 uA

Pin 6 and 7 configuration Microchip uses the pin 6 and 7 of ER59256 for factory internal test purposes. Pin 6 is
used to monitor the on-Chip charge pump which generates the required internal high
programming voltage (>20 volts) during the ERASE and WRITE cycles. Any circuitry
connects to this pin will force to reduce the data retention of the device or even no
programming will take place. Signal on pin 7 can force the device into its internal test
modes resulting in overprogramming all memory locations. It is therefore recommended
that pin 6 should be left open and pin 7 tied to Vss for normal operation.
Microchip's 93C06 and National's NMC9306/NMC93C06 have their pin 6 and 7 physically
not utilized. To make ER59256 compatible, the TEST pin (pin 7) can be left floating but
must be kept "clean" (noise-free).

Clock high time, clock low time For a clock frequency of 250 kHz, both ER59256 and NMC9306 specify the same
electrical parameters:
250 kHz equals 4 us clock cycle time
25% of the clock period (4 us) = 1 us (clock high time)
75% of the clock period (4 us) = 3 us (clock low time = 4 - 3 us =1 us)
For slower clock frequencies, the ER59256 spec would restrict the user regarding clock
.
low and high times:
100 k Hz
A clock frequency of
would result in clock low = 75% of 10 us
and
clock high = 25% of 10 us

= 10 us cycle time
= 7.5 us
= 2.5 us.

In reality, Microchip'S ER59256 can fulfill National's NMC9306 spec regarding SK low and
SK high equal to 1 usec over all operating frequencies as 250 kHz is the maximium
allowable frequency and is therefore the worst case.

DS00516A-2

1-156

ER59256/93C06

AND

NMC9306/NMC93C06

Chip select low tlmeAll parts require a chip select (CS) input goes low between any two instructions.
Programming of the part (ER59256, NMC9306,NMC93C06) begins at the falling edge of
the CS. Microchip's 93C06 however, starts self-programming at the rising edge of the last
data clocked bit. CS goes low and high with a minimium of chip select low time (Tcsl)
during programming can be used for polling purpose as discribed in 2.

DS00516A-3

1-157

ER59256/93C06

AND

NMC9306/NMC93C06

NOTES:

DS00516A-4

1-158

Microchip

APPLICATION NOTES

24COIA COMPATIBILITY ISSUE
AND ITS MOBILITY FOR MEMORY UPGRADE

Introduction
The 24C01 is a 1K (128 x 8) serial EEPROM which is currently offered by Microchip and
Xicor. There are several important differences between the two devices which are
discussed in this report. This report refers to the Microchip part as the 24C01A and the
Xicor part as the X24C01. It is intended to assist in designing a board which is compatible
with either device.

Compatibility Issues
There are three major differences between Microchip 24C01A and Xicor X24C01 as
detailed in the following paragraphs.

2.1

PAGE MODE DIFFERENCES

The 24C01A was originally designed to work in the same socket as the PCD8572 which
has a two-byte page mode. Its page is therefore two bytes deep. The X24C01 has a
page mode of four bytes depth.
If more than two bytes are transmitted to the 24C01 A during a page programming cycle,
the 24C01A will terminate the write cycle.
In many applications where serial EEPROMs are used and speed is not a key issue, the
byte write mode can be used without any loss of system performance. If only the byte
write mode is used, there is no compatibility problem (other than the slave address
software differences discussed in 2.2).
If the page write feature must be used,two different page mode algorithms can be
transmitted by the master depending upon whose device is being used. The master will
have to first do a polling routine to determine if it is interfacing with a 24C01 A or X24C01.
This polling technique is discussed in 2.2.

DS00517A-1

1-159

24C01A COMPATIBILITY ISSUE

Interestingly, the 24C01A actually updates faster in the page mode even though it has
one-half the page depth of the X24C01. This is due to the faster write cycle time of the
24C01 A. The two devices are compared below:

Max byte program time
Max page program time
Max time to program 4 bytes
Max time to rewrite device

Microchip

Xicor

1 ms
2 ms (2 bytes)
4ms
128 ms

10 ms
10 ms (4 bytes)
10 ms
320 ms

2.2 SOFTWARE DIFFERENCES
Microchip's 24C01 A is designed to share a 2-wire bus on which it resides with other
devices. To support this, the first byte of each command sequence from the master to
the 24C01 A must be a slave address. The 24C01 A monitors the 2-wire bus for its slave
address and "wakes-up" from standby mode if the address tr2.;I~mitted matches its
address as defined by the voltage level (Vss or Vcc) on pins 1, 2 and 3. X24C01 does not
support a multiple device bus and will always "wake-up" if a start condition is detected.
A slave address must be transmitted to the 24C01A at certain points during reading and
writing. This slave address is not required by the X24C01. Transmitting a slave address to
X24C01 will result in erroneous operation. This problem can be solved by having the
master transmit the the proper serial bit pattern to the slave, but first the master has to be
ascertained which 24C01 it is communicating with.
The master can do a simple polling routine before beginning serial communication with
24C01 A or X24C01 to determine which device it is working with. The proper serial
protocol for both devices must be contained in the master controller's firmware. Once the
master knows which 24C01 is on the bus, it can execute the proper serial commands.
The polling consists of the pattern like the one shown below:

SDA LINE:

I START BIT

I 00000001

I ACKNOWLEDGE BIT I DATA 7 ... 0

IfaX24C01 is used on the 2-wire bus, an acknowledge bit and eight data bits will be
returned whereas 24C01 A will issue no response and will ignore the command.

2.3 HARDWARE DIFFERENCES
As described earlier, the 24C01 A is designed to share a 2-wire bus with other devices
while the X24C01 is not. Chip address bits are ·included in the slave address for the
24C01 A, and are incorporated into pins 1, 2 and 3 of the device. They must be
connected to Vcc or Vss for proper operation. Since pins 1, 2 and 3 of the Xicor part are
NC (no connect) pins and they are not internally connected, they can be tied high or low.

DS00517A-2

1-160

24C01A COMPATIBILITY ISSUE

Another hardware difference involves pin 7 which MUST be connected to Vss on
X24C01. The 24C01 A can have pin 7 connected to Vss or Vcc.
If only one device is planned for the 2-wire bus, the board can be made compatible for
either device by connecting pins 1, 2 and 3 to either Vss or Vcc and tieing pin 7 to Vss.

Mobility For Memory Upgrade And Expansion
In system applications where the master device needs to address more than one serial
EEPROM on a 2-wire bus, Microchip's 24C01 A offers the flexibility. Up to eight 24C01 As
can be connected to the 2-wire bus. More than one Xicor X24C01 connecting to the bus
may result in bus contention.
If memory upgrade is required, Microchip's 24C01 A can be upgraded to 24C02A (256 x
8) or 24C04A (512 x 8) on the same IC socket with NO change in hardware. Using Xicor
X24C01 will have to reconfigure both software and hardware to accomodate the changes.

DS00517A-3

1-161

24C01A COMPATIBILITY ISSUE

NOTES:

DSOOS17A-4

1-162

Microchip

SECTION 2
EEPROM PRODUCT SPECIFICATIONS
28C04A
28C16A
28C17A
28C17A Dice
28C64A
28C64A Dice

1
9
17
25
33
41

DS00018C

2-i

DS00018C

2-ii

28C04A

Microchip

4K (512 X 8) CMOS Electrically Erasable PROM
FEATURES

DESCRIPTION

• Fast Read Access Time-1S0ns Maximum
• CMOS Technology for Low Power Dissipation
-30mA Active
-100).lA Standby
• Fast Byte Write Time-200lls or 1ms
• Data Retention> 10 years
• High Endurance 104 Erase/Write Cycles
• Automatic Write Operation
-Internal Control Timer
-Auto-Clear Before Write Operation
-On-Chip Address and Data Latches
• Data Polling
• Chip Clear Operation
• Enhanced Data Protection
-Vce Detector
-Pulse Filter
-Write Inhibit
• S-Volt-Only Operation
• Organized S12x8 JEDEC standard pinout
-24 Pin Dual-In-Line Package
-32 Pin Chip Carrier (Leadless or Plastic)
• Available for Extended Temperature Ranges:
-Commercial: O· C to 70· C
-Industrial: -40· C to 8S· C

The Microchip Technology Inc 28C04A is a CMOS 4K
non-volatile electrically Erasable and Programmable
Read Only Memory. The 28C04A is accessed like a
static RAM for the read or write cycles without the need
of external components. During a "byte write", the
address and data are latched internally, freeing the
microprocessor address and data bus for other operations. Following the initiation of write cycle, the device
will go to a busy state and automatically clear and write
the latched data using an internal control timer. To
determine when a write cycle is complete, the 28C04A
uses nata polling. oata polling allows the user to read
the location last written to when the write operation is
complete. CMOS design and processing enables this
part to be used in systems where reduced power consumption and reliability are required. A complete family
of packages is offered to provide the utmost flexibility in
applications.

PIN CONFIGURATION

BLOCK DIAGRAM

000·······

Top View

~""-

CEDE_

Data Protectton
Circuitry
Chip Enable!
Output Enable
Control Logic

WE_

Auto EraseiWrite

Vcc_

Timing

Data
Poll

Program Voltage
Generation

:- -~jD~der D

Input/Output
Buffers

AO_

::: ::: •
a
t

:.a::

.Pln 1 indlca1ot' on PLCC on lop of package

2-1

I--

YGating

h
e

U07

4Kbit

Decoder

Cell Matrix

05111268-1

28C04A
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE
Name

FUnction

AO-A8
CE
OE
WE

Address Inputs
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
+5V Power Supply
Ground
No Connect; No Internal
ConneCtion
Not Used; No External
Connection is Allowed

1/00- 1107

Vcc
Vss
NC
NU

MAXIMUM RATINGS*
Vcc and input voltages w.r.t. Vss .;.; .... -0.6V to+ 6.25V
Voltage on OE w.r.t. Vss ........................... -0.6V to +13.5V
Output Voltage w.r.t. Vss .................... -0.6V to Vcc+0.6V
Storage temperature .................... ,..... -65· C to 125· C
Ambient temp. with power applied ........ -50· C to 95· C
"Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.

Vcc= +5V ±10%
Commercial (C): Tamb= O· Cto 70· C
Industrial
(I): Tamb= -40· Cto 85· C

READ I WRITE OPERATION
DC Characteristics

Status

Symbol

Min

Max

logic "1"
logic "0"

VIH
Vil

2.0
-0.1

Vcc+1
0.8

V
V

Input leakage

III

-10

ItA

Input Capacitance

CIN

Parameter
Input Voltages

Units Conditions

VIN= -0.1V to Vcc+1
VIN= OV; Tamb = 25· C;
f", 1 MHz

Output Voltages

logic "1"
logic "0"

Output leakage

VOH
VOL

2.4

IlO

-10

CoUT

Output CapaCitance

0.45

V
V

ItA

IOH", -4001tA
IOl= 2.1mA
. VOUT= -0.1Vto VcC+0.1V
VIN", OV; Tamb = 25· C;
f = 1 MHz'

Power Suppy Current, Active

TTL input

Icc

f = 5 MHz (Note 1)

Vcc= 5.5V;
Power Supply Current, Standby

IcC(S)TIl
.TTl input
ICC(S)TIl
TTL input
CMOS input IcC(S)CMOS

2
3
100

mA
mA

ItA

-CE = VIH (0· C to 70· C)
CE = VIH (-40· C to 85· C)
CE = Vcc-0.3.. to Vcc+ 1

Note: (1) AC power supply current above 5 MHz: 1 mA/MHz

2-2

28C04A
READ OPERATION
AC Characteristics

AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:

Parameter

Sym

VIH= 2.4V; VIL= 0.45V; VOH = 2.0V; VOL = 0.8V
1 TTL Load + 100 pF
20 nsec
Commercial (C): Tamb = O· C to 70· C
(I): Tamb = -40· C to 85· C
Industrial

28C04A·15

28C04A·20

28C04A·25

Min

Max

Units

Conditions

Max

Address to Output Delay

lAce

150

200

250

OE = CE = VIL

CE to Output Delay

teE

150

200

250

OE = VIL

OE to Output Delay

toE

100

CE = VIL

CE or OE High to Output Float

toFF

Output Hold from Address, CE
or OE, whichever occurs first.

toH

•

READ WAVEFORMS

VIH
Address
VIL
VIH

CE
VIL

Address Valid

_"7'

VIH

VIL
VOH

teE(2)

Data

tOE(2) --

IIIII

High Z

\\\\

VOL

-- toFF(1.3)
toH
I--

Valid Output

1\\\ ~

High Z

IVI/

lAce
Notes: (1) toFF is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to teE - toE after the falling edge of CE without impact on teE
(3) This parameter is sampled. and is not 100% tested

2-3

05111268-3

28C04A
AC Testing Waveform:
Output Load:
Input Rise/Fall Times:
Ambient Temperature:

BYTE WRITE
AC Characteristics

VIH = 2.4V; VIL = O.4SV; VOH = 2.0V; VOL
1 TTL Load + 100 pF
20 nsec
Commercial (C): Tamb = O· C to 70· C
Industrial
(I): Tamb = -40· C to 85" C

Symbol

Min

Address Set-Up Time

lAs

Address Hold Time

IAH

Data Set-Up Time

tos

Parameter

Max

= 0.8V

Units Remarks

toH

Write Pulse Width

twPL

100

Write Pulse High Time

twPH

OE Hold Time

toEH

OE Set-Up Time

toES

Data Valid Time

tov

1000

Note 2

Write Cycle Time (28C04A)

twe

0.5 ms typical

Write Cycle Time (28C04AF)

twe

200

/ls

1OO/lS typical

Data Hold Time

Note:

(1 )
(2)

Note 1

A write cycle can be initiated CE or WE going low, whichever occurs last. The data is latched on
the positive edge of CE or WE, whichever occurs first.
Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until
tOH after the positive edge of WE or CE, whichever occurs first.

PROGRAMMING
Waveforms

Address

V'"=t
VIL

VIH

CE,WE

tAS

",=1
tWPL

VIL
Data In

VIH
VIL
VIH

OE
VIL

OS111266-4

2-4

28C04A
DATA POLLING
Waveforms

Address

V1H=X

Address Valid

VIL

f'f-__ _ _

~"_ _ _ _-'"

Last Written
Address Valid

tACC - -

tWPH

VIH

WE
VIL
tOE

VIH

OE
VIL
VIH
Data

----+-...

True Data Out

VIL

CHIP CLEAR

Waveforms

VIH - - - - - - - - - - . .
CE

1,\

VIL
VH

I~
VIH

1.....
0----

-------------J

----l~

\
VIL

1\'----_ _-

tw = 10ms
ts =tH = 1~s
VH = 12.0V ±O.5V

DS111268-5

2-5

28C04A
DEVICE OPERATION

Write Mode

The Microchip Technology Inc 28C04A has four basic
modes of operation-read, standby, write inhibit, and
byte write-as outlined in the following table.

The 28C04A has a write cycle similar to that of a Static
RAM. The write cycle is completel~elf-timed and
initiated by a low going pulse on the WE pin. On the
falling edge of WE, the address information is latched.
On rising edge, the data and the control pins (CE and
OE) are latched.

Operation Mode
Read
Standby
Write Inhibit
Write Inhibit
Write Inhibit
Byte Write
Byte Clear
X

L
H
H

X
X

X
X
X

H
L

1/0
DouT
HighZ
HighZ
High Z
HighZ
DIN

Automatic Before Each "Write"

= Any TTL level.

Read Mode
The 28C04A has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and is used to gate data to the
output pins independent of device selection. Assuming
that addresses are stable, address access time (lAcC) is
equal to the delay from CE to output (tCE). Data is
available at the output tOE after the falling edge of OE,
assuming that CE has been low and addresses have
been stable for at least tAcc-tOE.

Data Polling
The 28C04A features Data polling to signal the completion of a byte write cycle. During a write cycle, an
attempted read of the last byte written results in the data
complement of 1/07 (IIOO to 1/06 are indeterminable).
After completion olthe write cycle, true data is available.
Data polling allows a simple readlcompare operation to
determine the status of the chip eliminating the need for
external hardware.

Optional Chip Clear
All data may be cleared to l's in a chi£.Elear c~le by
raising OE to 12 volts and bringing the WE and CE low.
This procedure clears all data.

Standby Mode
The 28C04A is placed in the standby mode by applying
ahigh signaltotheCE input. When in the standby mode,
the outputs are in a high impedance state, independent
of the OE input.

Data Protection
In orderto ensure data integrity, especially during critical
power-up and power-down transitions, the following
enhanced data protection circuits are incorporated:
First, an internal Vcc detect (3.3 volts typical) will inhibit
the initiation of non-volatile programming operation when
Vcc is less than the Vcc detect circuit trip.
Second, there is a WE filtering circuit that prevents WE
pulses of less than IOns duration from initiating a write
cycle.
Third, holding WE or CE high or OE low, inhibits a write
cycle during power-on and power-off (Vcc).

D811126B-6

2-6

28C04A
NOTES:

2-7

OS11126B-7

28C04A
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.

PART NUMBERS

J
K
L
P
Temperature
Range:

Access Time:

I Option:
~-------I

DS11126B·8

Device:

Blank
I
15
20
25

F
4K

Cerdip
Ceramic Leadless Chip Carrier (LCC)
Plastic Leaded Chip Carrier (PLCC))
Plastic DIP
O' C

to 70' C

·40' C to 85' C
150 nsec
200 nsec
250 nsec
= twc= lms
= twc = 200~s

(512 x 8) CMOS EEPROM

2-8

28C16A

Microchip

16K (2K X 8) CMOS Electrically Erasable PROM
FEATURES

DESCRIPTION

• Fast Read Access Time-150ns Maximum
• CMOS Technology for Low Power Dissipation
-30mA Active
-100JlA Standby
• Fast Byte Write Time-200!1s or 1ms
• Data Retention> 10 years
• High Endurance 104 Erase/Write Cycles
• Automatic Write Operation
-Internal Control Timer
-Auto-Clear Before Write Operation
-On-Chip Address and Data Latches
• Data polling
• Chip Clear Operation
• Enhanced Data Protection
-Vee Detector
-Pulse Filter
-Write Inhibit
• Electronic Signature for Device Identification
• 5-Volt-Only Operation
• Organized 2Kx8 JEDEC Standard Pinout
-24 Pin Dual-In-Line Package
-32-Pin Chip Carrier (Leadless or Plastic)
• Available for Extended Temperature Ranges:
-Commercial: 0' C to 70' C
-Industrial: -40' C to 85' C
-Military *: -55' C to 125' C

The Microchip Technology Inc 28C16A is a CMOS 16K
non-volatile electrically Erasable and Programmable
Read Only Memory. The 28C16A is accessed like a
static RAM for the read or write cycles without the need
of external components. During a "byte write", the
address and data are latched internally, freeing the
microprocessor address and data bus for other operations. Following tre initiation of write cycle, the device
will go to a busy state and automatically clear and write
the latched data using an internal control timer. To
determine when a write cycle is complete, the 28C 16A
uses Data polling. Data polling allows the user to read
the location last written to when the write operation is
complete. CMOS design and processing enables this
part to be used in systems where reduced power consumption and reliability are required. A complete family
of packages is offered to provide the utmost flexibility in
applications.
* See military data sheet DS60036.

PIN CONFIGURATION

BLOCK DIAGRAM

voo .......

V07

Top View

Vs,,Vcc_
Vee
AI!
A9

WE
i5E
Al0

BE
1/07
1/06
1/05
1/04
1103

DIP

A6 5-'

l~Jl~Jl~!"":l~Jl~Jl~J

'.._.

§~j

•

AS
A4
A3 j]
A2 j]
A1 3jlJ

r29 AS

fgj
fg§

A9
NC
NC

DE_

Chip Enablel
Output Enable
Control Logic

WE_

Auto EraselWrite

Generation

f?~ Ai0

:::
:::

AO_

f~ 1107

jg] 1100 jjj

fiS

IIOG

f~lr~f~f~:~:~r-:I

~~~2~~g

I-

PLCC/LCC

II-

.Pin 1 indicator on PLCC on top of package

Al0_

2-9

L
a
t

oDe~er D
Decoder

I
YGating

16K bit
Cell Matrix

Buffers

..--

h
e

InpuVOutput

Data
Poll

Program Voltage

fg§ OE

Circuitry

CE-

Timing

fij CE

AO j3]

Data Protection

..--

D511125B-1

28C16A
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE
Name

Function

AO -Al0
CE
OE
WE
1/00 -1/07
vcc
Vss
NC

Address Inputs
Chip Enable
Output Enable
Write Enable
Data InputslOutputs
+5V Power Supply
Ground
No Connect; No Internal
Connection
Not Used; No External
Connection is Allowed

MAXIMUM RATINGS·
Vcc and input voltages w.r.t. Vss ........ -0.6V to + 6;25V
Voltage on OE w.r.t. Vss ........................... -0.6V to +13.5V
Voltage on A9 w.r.t. Vss ............................ -0.6V to + 13.5V
Output Voltage w.r.t. Vss .................... -0.6V to Vcc+0.6V
Storage temperature .......................... -65" C to 125" C
Ambient temp. with power applied ........ -50" C to 95" C

'Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.

Vcc = +5V ±1 0%
Commercial (C): Tamb= 0' Cto 70' C
Industrial
(I): Tamb= -40" C to 85" C

READ / WRITE OPERATION
DC Characteristics

Status

Symbol

Min

Max

Logic "1"
Logic "0"

VIH
VIL

2.0
-0.1

Vcc+l
0.8

V
V

Input Leakage

III

-10

VIN= -O.lV to Vcc+l

Input Capacitance

CIN

VIN = OV; Tamb = 25" C;
f = 1 MHz

0.45

V
V

VOUT= -O.lV to Vcc+0.1V

GoUT

VIN= OV; Tamb = 25" C;
f = 1 MHz

TTL input

Icc

f = 5 MHz (Note 1)
VCC=5.5V;

TTL input
TTL input
CMOS input

ICC(S)TTL
ICC(S)TTL
ICC(S)CMOS

2
3
100

mA
mA
itA

Parameter
Input Voltages

Logic "1"
Logic "0"

Output Voltages

Output Leakage
Output Capacitance

Power Suppy Current, Active

Power Supply Current, Standby
"

VOH
VOL

2.4

ILO

-10

Units Conditions

IOH= -400~
IOL= 2.1mA

CE = VIH (0' C to 70' C)
CE = VIH (-40" C to 85' C)
CE = Vcc-0.3 to Vcc+ 1

Note: (1) AC power supply current above 5 MHz: 1 mA/MHz

DS111258-2

2-10

28C16A
READ OPERATION
AC Characteristics

AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:

Parameter

Sym

VIH= 2.4V; VIL= 0.45V; VOH = 2.0V; VOL = 0.8V
1 TTL Load + 100 pF
20 nsec
Commercial (C): Tamb = 0" C to 70' C
(I): Tamb = -40' C to 85' C
Industrial

28C16A·15

28C16A-20

28C16A-25

Min

Max

Units

Conditions

Max

Address to Output Delay

lAcc

150

200

250

OE = CE = VIL

CE to Output Delay

tCE

150

200

250

OE = VIL

OE to Output Delay

toE

100

CE = VIL

CE or OE High to Output Float

toFF

Output Hold from Address. CE
or OE. whichever occurs first.

toH

READ WAVEFORMS

VIH
Address
VIL
VIH

Address Valid
~

CE
VIL

X
l?"'"

tCE(2)
VIH

ZL.

- - tOE(2) - VOH
Data

////;
\\\\\

High Z

VOL

- -~

VIL

-- toFF(1.3) toH

Valid Output

High Z

; '/1

lAcc
Notes: (1) toFF is specified for OE or CEo whichever occurs first
(2) OE may be delayed up to tE - toE after the falling edge of CE without impact on tE
(3) This parameter is sampled and is not 100% tested

2-11

D811125B-3

28C16A
VIH = 2.4V; VIL = 0.45V; VOH =2.0V; VOL
1 TTL Load + 100 pF
20 nsec
Commercial (C): Tamb = O' C to 70' C
Industrial
(I): Tamb = -40' C to 85' C

AC Testing Waveform:
Output Load:
Input Rise/Fall Times:
Ambient Temperature:

BYTE WRITE
AC Characteristics

Symbol

Min

Address Set-Up Time

tAS

Address Hold Time

tAH

Data Set-Up Time

tos

Parameter

Max

Units Remarks

toH

Write Pulse Width

twPL

100

Write Pulse High Time

twPH

OE Hold Time

toEH

OE Set-Up Time

toES

Data Hold Time

= 0.8V

Note 1

Data Valid Time

tov

1000

Note 2

Write Cycle Time (28C16A)

twe

0.5 ms typical

Write Cycle Time (28C16AF)

twe

200

J.ls

100J.lS typical

Note:

(1 )
(2)

PROGRAMMING
Waveforms

Address

V'"=t----~:====-t-AH--------~:f<~
VIL

VIH

-----------------------

tAS

~1~-------twPL----~~

CE,WE
VIL
VIH
Data In
VIL
tOES
VIH
OE

VIL

OSll1256-4

2-12

28C16A

DATA POLLING

Waveforms

Address

VIH
VIL

=><

Address Valid

({

'-_ _ _ _~)L)_ _ _

Last Written
!lddress Valid

tACC - -

VIH~

VIL _
-"-'>-.:.
_ _ _ _ _ _ _-L-...&-L....~:..._<.~ "'-''-''--'-''''-----+----------tWPH

VIH
WE
VIL
tOE

VIH
OE
VIL
VIH ----1---..
True Data Out

Data
VIL ----1-..../

CHIP CLEAR

Waveforms

VIH - - - - - - - - - - - , .
CE
~~

VIL
VH

___________________J/

OE VIH _ _ _ _ _ _- J/

I~..
_--

----i~

VIH

WE
VIL

tw = 10ms
ts =tH = 11.ls
VH = l2.0V ±O.5V

SUPPLEMENTARY CONTROL
Mode

Chip Clear
Extra Row Read
Extra Row Write
Note: VH = l2.0V ±O.5V

VIL
VIL

VIL
X
VH
A9=VH
VIL
VIH
VIH
A9=VH
• Pulsed per programming waveforms.

2-13

Vee

1/01

Vee
Vee
Vee

Data Out
Data In

D511125B-5

28C16A
DEVICE OPERATION
The Microchip Technology Inc 28C16A has four basic
modes of operation-read, standby, write inhibit, and
byte write-as outlined in the following table.
Operation Mode
Read
Standby
Write Inhibit
Write Inhibit
Write Inhibit
Byte Write
Byte Clear

L
H
H

X
X

I/O

DoUT

X
X

X
X
X

HighZ
HighZ
HighZ
HighZ
DIN

H
L

Second, there is a WE filtering circuit that prevents WE
pulses of less than 10ns duration from initiating a write
cycle.
Third, holding WE or CE high or DE low, inhibits a write
cycle during power-on and power-off (Vce).

Write Mode
The 28C 16A has a write cycle similar to that of a Static
RAM. The write cycle is completely self-timed and
initiated by a low going pulse on the WE pin. On the
falling edge of WE, the address information is latched.
On rising edge, the data and the control pins (CE and
DE) are latched.

Automatic Before Each "Write"

X = Any TTL level.

Data POlling

Read Mode
The 28C16A has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip enable (CE) is the power control and
should be used for device selection. Output Enable
(DE) is the output control and is used to gate data to the
output pins independent of device selection. Assuming
that addresses are stable, address access time (tACC) is
equal to the delay from CE to output (teE). Data is
available at the output tOE after the falling edge of DE,
assuming that CE has been low and addresses have
been stable for at least tACC-tOE.
Standby Mode
The 28C16A is placed in the standby mode by applying
a high signal to the CE input. When in the standby mode,
the outputs are in a high impedance state, independent
of the DE input.

The 28C16A features Data polling to signal the completion of a byte write cycle. During a write cycle, an
attempted read of the last byte written results in the data
complement of 1/07 (1/00 to 1/06 are indeterminable).
After completion of the write cycle, true data is available.
Data polling allows a simple read/compare operation to
determine the status of the chip eliminating the need for
external hardware.

Electronic Signature for Device Identification
An extra row of 32 bytes of EEPROM memory is available to the user for device identification. By raising A9
to 12V ±0.5V and using address locations 7EO to 7FF,
the additional bytes can be written to or read from in the
same manner as the regular memory array.

Optional Chip Clear
Data Protection
In order to ensyre data integrity, especially during critical
power-up and power-down transitions, the following
enhanced data protection circuits are incorporated:

All data may be cleared to 1's in a chip clear cycle by
raising DE to 12 volts and bringing the WE and CE low.
This procedure clears all data, except for the extra row.

First, an internal Vcc detect (3.3 volts typical) will inhibit
the initiation of non-volatile programming operation when
Vce is less than the Vce detect circuit trip.

0811125B-6

2-14

28C16A
NOTES:

2-15

05111259-7

28C16A
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.

PART NUMBERS
~.1!AF

·15 II P

Package:

I Temperature
Range:

Access Time:

I Option:
Device:

O· C to 70· C
-40· C to 85· C

Blank
I

15
20
25

150 nsec
200 nsec
250 nsec

DS11125B-8

Cerdip
Ceramic Leadless Chip Carrier (LCC)
Plastic Leaded Chip Carrier (PLCC))
Plastic DIP

J
K
L
P

16K

=\Wc= 1ms
= \We = 200115
(2K x 8) CMOS EEPROM

2·16

28C17A

Microchip

16K (2K X 8) CMOS Electrically Erasable PROM
FEATURES

DESCRIPTION

• Fast Read Access Time--150ns Maximum
CMOS Technology for Low Power Dissipation
-30mA Active
-1001lA Standby
• Fast Byte Write Time--2001lS or 1ms
• Data Retention> 10 years
High Endurance 10' EraselWrite Cycles
• Automatic Write Operation
-Internal Control Timer
-Auto-Clear Before Write Operation
-On-Chip Address and Data Latches
• Data Polling
• Ready/Busy
• Chip Clear Operation
• Enhanced Data Protection
-Vee Detector
-Pulse Filter
-Write Inhibit
• Electronic Signature for Device Identification
• 5-Volt-Only Operation
Organized 2Kx8 JEDEC Standard Pinout
-28 Pin Dual-In-Line Package
-32-Pin Chip Carrier (Leadless or Plastic)
Available for Extended Temperature Ranges:
-Commercial: O' C to 70' C
-Industrial: -40' C to 85' C
-Military *: -55' C to 125' C

The Microchip Technology Inc 28C17A is a CMOS 16K
non-volatile electrically Erasable and Programmable
Read Only Memory. The 28C17A is accessed like a
static RAM for the read or write cycles without the need
of external components. During a "by1e write", the
address and data are latched internally, freeing the
microprocessor address and data bus for other operations. Following the initiation of write cycle, the device
will go to a busy state and automatically clear and write
the latched data using an internal control timer. To
determine when the write cycle is complete, the user has
a choice of monitoring the Ready/Busy output or using
Data polling. The Ready/Busy pin is an open drain
output, which allows easy configuration in wired-or
systems. Alternatively, Data polling allows the user to
read the location last written to when the write operation
is complete. CMOS design and processing enables this
part to be used in systems where reduced power consumption and reliability are required. A complete family
of packages is offered to provide the utmost flexibility in
applications.
* See military data sheet DS60036.

PIN CONFIGURATION

1/00·······1/07

BLOCK DIAGRAM

Top View

V",,Vee . . .

Data Protection
Circuitry
Chip Enablel
Output Enable
Control Logic

BE...

OE'"

WE_
Rdy!_

Auto EraselWrite
Timing

!lUSy

Generation

::::
::::

IDIP/SOle

PlCClLCC

I-

I
YGating

16K bit
Cell Matrix

Decoder

t---

e l-

A~O:::

oDe~der D

11-

.Pin 1 Indicator on PLCC on top of package

Buffers

Poll

Program Vohage

AO_

Input/Output

Data

2-17

DSl1127B-l

28C17A
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE
Name

Function

AO-Al0
CE
OE
WE
1/00 -1/07
-RDY/Busy
Vcc
Vss
NC

Address Inputs
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
Ready/Busy
+5V Power Supply
Ground
No Connect; No Internal
Connection
Not Used; No External
Connection is Allowed

MAXIMUM RATINGS'
VCC and input voltages w.r.t. Vss ........ -0.6V to + 6.25V
Voltage on OE w.r.t. Vss ........................... -0.6V to +13.5V
Voltage on A9 w.r.t. Vss ............................ -0.6V to +13.5V
Output Voltage W.r.t. Vss .................... -0.6V to Vcc+0.6V
Storage temperature .......................... -65' C to 125' C
Ambient temp. with power applied ........ -50' C to 95' C

Vcc = +5V ±1 0%
Commercial (C): Tamb= 0' C to 70' C
Industrial
(I): Tamb= -40' C to 85' C

READ / WRITE OPERATION
DC Characteristics

Parameter
Input Voltages

Status

Symbol

Min

Max

Units

Logic "1"
Logic "0"

VIH
VIL

2.0
-0.1

Vcc+l
0.8

V
V

III

-10

flA

Input Leakage

CIN

Input Capacitance

Conditions

VIN = -O.W to Vcc+ 1
VIN = OV; Tamb = 25' C;

f = 1 MHz
Output Voltages

Logic "1"
Logic "0"

Output Leakage

VOH
VOL

2.4

ILO

-10

GoUT

Output Capacitance

0.45

V
V

IOH= -400flA
IOL= 2.1mA

flA

VOUT= -O.W to Vcc+0.1V

VIN = OV; Tamb = 25' C;

f = 1 MHz
Power Suppy Current, Active

TIL input

Icc

f = 5 MHz (Note 1)
Vcc = 5.5V;

Power Supply Current, Standby

TIL input
TIL input
CMOS input

ICC(S)TTL
ICC(S)TTL
ICC(S)CMOS

2
3
100

mA
mA
flA

CE = VIH (0' C to 70' C)
CE = VIH (-40' C to 85' C)
CE = Vcc-0.3 to Vcc+ 1

Note: (1) AC power supply current above 5 MHz: 1 mA/MHz

DS11127B-2

2-18

28C17A
READ OPERATION
AC Characteristics

AC Testing Waveform:
VIH= 2.4V; VIL= 0.45V; VOH = 2.0V; VOL = 0.8V
Output Load:
1 TTL Load + 100 pF
Input Rise and Fall Times: 20 nsec
Ambient Temperature:
Commercial (C): Tamb = 0' C to 70' C
Industrial
(I): Tamb = -40' C to 85' C

Parameter

Sym

28C17A·15

28C17A·20

28C17A·25

Min

lAcc

Address to Output Delay

CE to Output Delay

OE to Output Delay

CE or OE High to Output Float

Output Hold from Address, CE
or OE, whichever occurs first.

Max
150

Max
200

Units

Max
250

teE

150

200

250

toE

100

toFF

toH

Conditions

OE = CE =VIL

OE = VIL
CE = VIL

READ WAVEFORMS

VIH
Address
VIL
VIH

Address Valid
~

CE
VIL

VIH

--,..

VIL

- - toE(2) - VOH
Data

"--

tCE(2)

IIIII
\\\\\

HighZ

VOL

c...

- - toFF(1,3) f.toH
I--

Valid Output

\1\\\1\

High

III IIV

lAcc
Notes: (1) toFF is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to teE - toE after the falling edge of CE without impact on teE
(3) This parameter is sampled and is !lot 100% tested

2-19

D5111278-3

28C17A
AC Testing Waveform:
Output Load:
Input Rise/Fall Times:
Ambient Temperature:

BYTE WRITE
AC Characteristics

Parameter

VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V
1 TTL Load + 100 pF
20 nsec
Commercial (C): Tamb = 0' C to 70' C
(I): Tamb = -40' C to 85' C
Industrial

Symbol

Min

Max

Units

Remarks

Address Set-Up Time

tAS

Address Hold Time

tAH

Data Set-Up Time

IDs

Data Hold Time

IDH

Write Pulse Width

twPL

100

Write Pulse High Time

twPH

OEHold Time

toEH

OE Set-Up Time

toES

Data Valid Time

IDv

1000

Time to Device Busy

IDB

Write Cycle Time (28C17A)

twc

0.5 ms typical

Write Cycle Time (28C17AF)

twc

200

IlS

1OOIlS typical

Note:

(1 )
(2)

Note 1

ns
ns

Note 2

PROGRAMMING
Waveforms

Add~

:::
VIH

=1---------:¥<-----------.
tAS..

tAH

tWPL

CE,WE
VIL

f..-tov_- t o s Data In

VIH
VIL
VIH

OE
VIL

--7

tOES

->K

':::,~

.."k(

1- tOEH

VOH
Rdy/Busy

DS11127B-4

Re
~adY

Busy
VOL

•

LIDB'i

twc

2-20

28C17A
DATA POLLING

Waveforms

Address

VIH

:=x

VIL

A
ddress Valid

'-_ _ _ _-1

Last Written
Address Vahd

4___

tACC . - -

CE VIH ~
VIL _~-"-"--"~ _ _ _ _ _...L......L....L..-L....L.L"-LJ."--'''--''--->''':''-_ _ _

+ __________

tWPH

VIH
VIL
tOE

.--

VIH
OE
VIL
VIH ----t--...
Data

VIL ----t---/

CHIP CLEAR
Waveforms

VIH - - - - - - - - - - . . .
CE

~~--------------------~/

VIL

~---

----I~

VIH - - - - - - - - - - - - - - J

1,\

VIL

tw = 10ms
ts =tH = 1~s
VH = 12.0V ±O.5V

SUPPLEMENTARY CONTROL
Mode
Chip Clear
Extra Row Read
Extra Row Write
Note: VH = 12.0V ±O.5V

WE
A9
OE
VH
VIL
X
VIL
VIH
A9=VH
VIH
A9 = VH
• Pulsed per programming waveforms.

CE
VIL
VIL

2-21

Vee

1/01

Vee
Vee
Vee

Data Out
Data In

DS11127B-5

28C17A
DEVICE OPERATION
The Microchip Technology Inc 28C17A has four basic
modes of operation-read, standby, write inhibit, and
byte write-as outlined in the following table.
Operation Mode CE OE WE I/O

Second, there is a WE filtering circuit that prevents WE
pulses of less than 10ns duration from initiating a write
cycle.
Third, holding WE or CE high or OE low, inhibits a write
cycle during power-on and power-off (Vcc).

Rdy/8usY(1 )
Write Mode

Read
Standby
Write Inhibit
Write Inhibit
Write Inhibit
By1e Write
8y1e Clear

L
H
H

X
X
L

L
X
X
L
X

DoUT

X
X
X

HighZ
HighZ
HighZ
HighZ
DIN
L

H
H
H
H
H

Automatic Before Each "Write"
Note: (1) Open drain output.
(2) X = Any TTL level.

Read Mode
The 28C17A has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip enable (CE) is the power control and
should be used for device selection. Output Enable (OE)
is the output control and is used to gate data to the output
pins independent of device selection. Assuming that
addresses are stable, address access time (tACC) equal
to the delay from CE to output (tCE). Data is available at
the output tOE after the falling edge of OE, assuming that
CE has been low and addresses have been stable for at
least lACC-tOE.

The 28C 17A has a write cycle similar to that of a Static
RAM. The write cycle is completely self-timed and
initiated by a low going pulse on the WE pin. On the
falling edge of WE, the address information is latched.
On rising edge, the data and the control pins (CE and
OE) are latched. The Ready/Busy pin goes to a logic low
level indicating that the 28C17A is in a write cycle which
signals the microprocessor host that the system bus is
free for other activity. When Ready/Busy goes back to
a high, the 28C17A has completed writing and is ready
to accept another cycle.

Data Polling
The 28C17A features Data polling to signal the completion of a by1e write cycle. During a write cycle, an
attempted read of the last by1e written results in the data
complement of 1/07 (1/00 to 1/06 are indeterminable).
After completion of the write cycle, true data is available.
Data polling allows a simple read/compare operation to
determine the status of the chip eliminating the need for
external hardware.

Standbv Mode
The 28C 17A is placed in the standby mode by applying
a high signal to the CE input. When in the standby mode,
the outputs are in a high impedance state, independent
of the OE input.

Data Protection

Electronic Signature for Device Identification
An extra row of 32 by1es of EEPROM memory is available to the user for device identification. By raising A9
to 12V ±O.5V and using address locations 7EO to 7FF,
the additional by1es can be written to or read from in the
same manner as the regular memory array.

In order to ensure data integrity, especially during critical
power-up and power-down transitions, the following
enhanced data protection circuits are incorporated:

Optional Chip Clear

First, an internal Vcc detect (3.3 volts typical) will inhibit
the initiation of non-volatile programming operation when
Vcc is less than the vcc detect circuit trip.

All data...!!!ay be cleared to 1's in a chip clear cycle by
raising OE to 12 volts and bringing the WE and CE low.
This procedure clears all data, except for the extra row.

DS111279-6

2-22

28C17A
NOTES:

2-23

D8111278-7

28C17A
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.
PART NUMBERS
~,.!!AF

-15 liP

Package:

J
K
L
P
SO

I 'Temperature
Range:
I

Access TIme:

Blank
I
15
20
25

jOPllon:
F

1-.-------1. Device:

D811127B-8

28C17A

Cerdip
Ceramic Leadless Chip Carrier (LCC)
Plastic Leaded Chip Carrier (PLCC))
Plastic DIP
Plastic Small Outline IC
0' C to 70' C
-40' C to 85' C
150 nsec
200 nsec
250 nsec

= twc= lms
= twc = 200~s
(2K x 8) CMOS EEPROM

2-24

28C17A
DICE FORM

Microchip

16K (2K X 8) CMOS Electrically Erasable PROM
FEATURES

DESCRIPTION

• 250ns Access Time
CMOS Technology for Low Power Dissipation
-30mA Active
-1001lA Standby
• Fast Byte Write Time-1 ms
• Automatic Write Operation
-Intemal Control Timer
-Auto-Clear Before Write Operation
-On-Chip Address and Data Latches
• Data Polling
Ready/Busy
• Chip Clear Operation
• Enhanced Data Protection
-Vee Detector
-Pulse Filter
-Write Inhibit
Electronic Signature for Device Identification
5-Volt-Only Operation
• Commercial Temperature Range:
-0' Ct070' C
• Available in Wafer Form or Waffle Pack

The Microchip Technology Inc 28C 17A is a CMOS 16K
non-volatile electrically Erasable and Programmable
Read Only Memory. The 28C17A is accessed like a
static RAM for the read or write cycles without the need
of external components. During a "byte write", the
address and data are latched internally, freeing the
microprocessor address and data bus for other operations. Following the initiation of write cycle, the device
will go to a busy state and automatically clear and write
the latched data using an internal control timer. To
determine when the write cycle is complete, the user has
a choice of monitoring the Ready/Busy output or using
Data polling. The Ready/Busy pin is an open drain
output, which allows easy configuration in wired-or
systems. Alternatively, Data polling allows the user to
read the location last written to when the write operation
is complete. CMOS design and processing enables this
part to be used in systems where reduced power consumption and reliability are required.

BLOCK DIAGRAM

DIE CONFIGURATION
Die Size: 137 x 117 sq. mils

1100 .... ···1/07

~~~~~~ ~~~~<

vss--r.=o;:a=ta::;p;=ro=te=c::tio=n:::::;----jffirHrHH-.

CE
A10
A2

Vee......

Circuitry

CE--

Chip Enable/

OE__

~~~~F~;~~

WE......

Auto EraselWrite

Data

Timing

Poll

Rdy!_

Program Voltage

IlUSy

AO __

:::
:::

1-1--

1--

Iw~

.---

Generation

=l oec~der D

InpuUOutput

Buffers

I
YGating

I--

Decoder

16K bit
Cell Matrix

A\O::~__
==~--=====~I__-!========~

>C/)

2-25

D8111348-1

28C17 A DICE FORM
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE
Name

Function

AD - Al0
CE
OE
WE
1100-1/07
ROY/Busy
Vce
Vss
NC

Address Inputs
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
Ready/Busy
+SV Power Supply
Ground
No Connect; No Internal
Connection

Maximum Ratings·
Vcc and input voltages w.r.t. Vss ........ -0.6V to + 6.2SV
Voltage on OE w.r.t. Vss ........................... -0.6V to +13.SV
Voltage on A9 W.r.t. Vss ............................ -0.6V to +13.SV
Output Voltage w.r.t. Vss .................... -0.6V to Vcc+0.6V
Storage temperature .......................... -6S" C to 12S" C
Ambient temp. with power applied ........ -SO" C to 9S" C
'Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.

READ / WRITE OPERATION
DC Characteristics

Parameter
Input Voltages

Vcc = +5V ±1 0%
Commercial: Tamb=

Symbol

Min

Max

Logic "1"
Logic "0"

VIH
VIL

2.0
-0.1

Vcc+l
0.8

V
V

III

-10

JJ.A

VIN =. -0.1V to Vcc+ 1

VIN= OV; Tamb = 25" C;
f = 1 MHz

0.45

V
V

IoH = -4OOIlA
IoL= 2.1mA

JJ.A

VOUT= -O.IV to Vcc+O.1V

CoUT

VIN= OV; Tamb = 25" C;
f = 1 MHz

Icc

f = 5 MHz (Note 1)
Vcc = 5.5V;

2
100

mA
IlA

CE =VIH
CE= Vcc-0.3 to Vcc+ 1

CIN

Input Capacitance

Logic "1"
Logic "0"

Output Leakage
Output Capacitance

Power Suppy Current. Active

Power Supply Current. Standby

Units Conditions

Status

Input Leakage

Output Voltages

0" C to 70" C

TTL input

VOH
VOL

2.4

ILO

-10

ICC(S)TTL
TTL input
CMOS input IcC(S)CMOS

Note: (1) AC power supply current above S MHz: 1 mA/MHz

OSl11349-2

2-26

©.1990 Microchip Technology Inc.

28C17 A DICE FORM
VIH= 2.4V; VIL= 0.45V; VOH = 2.0V; VOL = O.BV
1 TTL Load + 100 pF
20 nsec
Commercial: Tamb = O' C to 70' C

AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:

READ OPERATION
AC Characteristics

Parameter

28C17A·25

Sym

Min
Address to Output Delay

CE to Output Delay

OE to Output Delay

250

tCE

250

Output Hold from Address, CE
or OE, whichever occurs first.

tOFF

tOH

Conditions

Max

tAcC

tOE

CE or OE High to Output Float

Units

100

OE = CE = VIL

OE = VIL

CE = VIL

READ WAVEFORMS

VIH

Address
VIL
VIH

rk-

Address Valid
~

~ 1-=-

CE
VIL

VIH

VIL
- - tOE(2) - VOH

l2"
...

"'--

tCE(2)

Data

High Z

////1

\\\\\

VOL

toFF(1.3) I-~
tOH

Valid Output

\1\\ 1\

High Z

/1//11/

tACC

Notes: (1) toFF is specified for OE or CE, whichever occurs first
_
(2) OE may be delayed up to teE - toE after the falling edge of CE without impact on tE
(3) This parameter is sampled and is not 100% tested

2-27

08111346-3

28C17A DICE FORM
VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V
1 TTL Load + 100 pF
20 nsec
Commercial: Tamb = O·C to 70·C

AC Characteristics

AC Testing Waveform:
Output Load:
Input Rise/Fall Times:
Ambient Temperature:

Parameter

Symbol

Min

Address Set-up Time

tAS

Address Hold Time

tAH

100

Data Set-Up Time

tos

100

Data Hold Time

toH

Write Pulse Width

twPL

100

Write Pulse High Time

twPH

OE Hold Time

toEH

OE Set-Up Time

tOES

Data Valid Time

tov

1000

Time to Device Busy

tos

Write Cycle Time (28C17A)

twe

BYTE WRITE

Max

Units

Remarks

Note 1

Note 2

0.5 ms typical

(1 ) A write cycle can be initiated CE or WE going low, whichever occurs last. The data is latched on
the positive edge of CE or WE, whichever occurs first.
(2) Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least
until toH after the positive edge of WE or CE, whichever occurs first.

Note:

PROGRAMMING
Waveforms

Address

v'"=>{--",3---VIL

VIH
CE,WE

tAS

1-----:--- tWPL

----I~;f"

VIL
Data In

VIH
VIL
tOES
VIH

OE
VIL

VOH

Rdy/Busy
VOL

D811134B-4

I~"-----

twc

2-28

tOB

_~J'__B_'u:fieady
~

28C17A DICE FORM
DATA POLLING
Waveforms

Address

V1H=X
VIL

VIH~
VIL

tCE

+_---------

_
-"-'......".
_ _ _ _ _ _ _£.-,~__L..L..L....LJ"_".._"_._"_""__ _ _ _
tWPH

VIH

WE
VIL
VIH

"7'""':rr-r--+----"«"""""''"""'''_.,...____~,.......__._:7"/"<"""""'<_.,...'''"""''

tOE

...

OE
VIL
VIH

Data

----+-,

VIL

CHIP CLEAR

Waveforms

VIH - - - - - - - -.....
CE

VIL

I\.

/
VIH _ _ _ _ _ _- J

14---- tw

VIH - - - - - - - - - - - - . . \
WE VIL

--~

1"''---__tw = 10ms
ts =tH = 1IIs
VH = l2.0V ±O.SV

SUPPLEMENTARY CONTROL
Mode
ChioClear
Extra Row Read
Extra Row Write
Note: VH = 12.0V ±c.SV

A9
WE
VH
VIL
X
VIL
VIH
A9=VH
VIH
A9=VH
• Pulsed per programming waveforms.

VIL
VIL

2-29

Vee
Vee
Vee
Vee

1/01

Data Out
Data In

05111348-5

28C17A

DICE FORM

DEVICE OPERATION
The Microchip Technology Inc 28C17A has four basic
modes of operation-read, standby, write inhibit, and
byte write-as outlined in the following table.
Operation Mode CE DE WE 110

Rdy/BusY(1)
WrjteMode

L L
H DoUT H
H X X HighZ H
H X X HighZ H
X L
X HighZ H
X X H HighZ H
L
L H L DIN
Automatic Before Each "Write"
Note: (1) Open drain output.
(2) X = Any TTL level.
Read
Standby
Write Inhibit
Write Inhibit
Write Inhibit
Byte Write
Byte Clear

Read Mode

The 28C17A has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip enable (CE) is the power control and
should be used fordeviceselection. Output Enable (DE)
is the output control and is used to gate data to the output
pins independent of device selection. Assuming that
addresses are stable, address access time (lAcc) equal
to the delay from CE to output (tCE). Data is available at
the outputtOE after the falling edge of DE, assuming that
CE has been low and addresses have been stable for at
least IACC-tOE.

The 28C17A has a write cycle similar to that of a Static
RAM. The write cycle is completely self-timed and
initiated by a I~oing pulse on the WE pin. On the
falling edge of WE, the address information is latched.
On rising edge, the data and the control pins (CE and
DE) are latched. The Ready/Busy pin goes to a logic low
level indicating that the 28C17A is in a write cycle which
signals the microprocessor host that the system bus is
free for other activity. When Ready/Busy goes back to
a high, the 28C17A has completed writing and is ready
to accept another cycle.

ifatiPolling

The 28C17A features Data polling to signal the completion of a byte write cycle. During a write cycle, an
attempted read of the last byte written results in the data
complement of 1107 (1100 to 1106 are indeterminable).
After completion olthe write cycle, true data is available.
Data polling allows a simple read/compare operation to
determine the status of the chip eliminating the need for
external hardware.

Standby Mode

The 28C17A is placed in the standby mode by applying
a high signal to the CE input. When in the standby mode,
the ou!E!!,ts are in a high impedance state, independent
of the DE input.
Data Protection

Electronic SlgnatYre for Device Identlficatjon

An extra row of 32 bytes of EEPROM memory is available to the user for device identification. By raising A9
to 12V ±O.5V and using address locations 7EO to 7FF,
the additional bytes can be written to or read from in the
same manner as the regular memory array.

In order to ensure data integrity, especially during critical
power-up and power-down transitions, the following
enhanced data protection circuits are incorporated:

Optional Chip Clear

First, an internal Vcc detect (3.3 volts typical) will inhibit
the initiation of non-volatile programming operation when
Vcc is less than the Vcc detect circuit trip.

All data may be cleared to 1's in a chip clear ~Ie by
raising DE to 12 volts and bringing the WE and CE low.
This procedure clears all data, except for the extra row.

05111348-6

2-30

28C17A

DICE FORM

NOTES:

DS111348-7

2-31

28C17A

DICE FORM

SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refsr to the
factory or the listed sales offic"!s.

PART NUMBERS

28C17A -25 -/W

~
1-._ _-1

W
S

Pso"g.'
Temperature
Range:

Blank

' - - - - - - - i Access Time:

' - - - - - - - - - - t Device:

08111348-8

25
28C17A

2-32

Dice in Wafer Form
Dice in Waffle Pack
O· C to 70· C

250 nsec
(2K

x 8)

CMOS EEPROM

28C64A

Microchip

64K (8K X 8) CMOS Electrically Erasable PROM
FEATURES

DESCRIPTION

• Fast Read Access Time-150ns Maximum
• CMOS Technology for Low Power Dissipation
-30mA Active
-100IlA Standby
• Fast Byte Write Time-200lls or 1ms
• Data Retention> 10 years
• High Endurance 10" EraselWrite Cycles
Automatic Write Operation
-Internal Control Timer
-Auto-Clear Before Write Operation
-On-Chip Address and Data Latches
• Data Polling
• Ready/Busy
• Chip Clear Operation
• Enhanced Data Protection
-Vee Detector
-Pulse Filter
-Write Inhibit
• Electronic Signature for Device Identification
• 5-Volt-Only Operation
• Organized 8Kx8 JEDEC Standard Pinout
-28 Pin Dual-In-Line Package
-32-Pin Chip Carrier (Leadless or Plastic)
• Available for Extended Temperature Ranges:
-Commercial: O· C to 70· C
-Industrial: -40· C to 85· C
-Military": -55· C to 125· C

The Microchip Technology Inc 28C64A is a CMOS 64K
non-volatile electrically Erasable and Programmable
Read Only Memory. The 28C64A is accessed like a
static RAM for the read or write cycles without the need
of external components. During a "byte write", the
address and data are latched internally, freeing the
microprocessor address and data bus for other operations. Following the initiation of write cycle, the device
will go to a busy state and automatically clear and write
the latched data using an internal control timer. To
determine when the write cycle is complete, the user has
a choice of monitoring the Ready/Busy output or using
Data polling. The Ready/Busy pin is an open drain
output, which allows easy configuration in wired-or
systems. Alternatively, Data polling allows the user to
read the location last written to when the write operation
is complete. CMOS design and processing enables this
part to be used in systems where reduced power consumption and reliability are required. A complete family
of packages is offered to provide the utmost flexibility in
applications.
" See Military Data Sheet DS60003

PIN CONFIGURATION

BLOCK DIAGRAM

VOO ••••••• V07

Top View

DIP/SOIC

e
s

PLCCJLCC

X
Oecoder

64KbH
Cell Matrix

• Pin 1 Indlca10r on PLCC on top 01 package

2-33

DS11109C-1

28C64A
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE
Name

Function

AO-A12
CE
OE
WE

Address Inputs
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
Ready/Busy
+5V Power Supply
Ground
No Connect; No Internal
Connection
Not Used; No External
Connection is Allowed

1/00-1/07

ROY/Busy
Vcc
VSS
NC
NU

MAXIMUM RATINGS·
Vcc and input voltages w.r.t. VSS ........ -0.6V to + 6.2SV
Voltage on OE w.r.t. VSS ........................... -0.6V to +13.5V
Voltage on A9 w.r.t. Vss ............................ -0.6V to +13.5V
Output Voltage w.r.t. Vss .................... -0.6V to Vcc+0.6V
Storage temperature .......................... -65· C to 125' C
Ambient temp. with power applied ........ -50·C to 95' C
'Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation. of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.

Vcc = +5V ±1 0%
Commercial (C): Tamb= O' Cto 70' C
Industrial
(I): Tamb= -40' C to 85' C

READ I WRITE OPERATION
DC Characteristics

Parameter
Input Voltages

Status

Symbol

Min

Max

Logic "1"
LogiC "0"

VIH
VIL

2.0
-0.1

Vcc+l
0.8

V
V

III

-10

itA

VIN= -O.lV to Vcc+1

VIN = OV; Tamb = 25' C;
f= 1 MHz

0.45

V
V

IoH = -4001tA
IoL= 2.1mA

ItA

VOUT= -O.lV to Vcc+O.1V

CoUT

VIN= OV; Tamb = 25' C;
f = 1 MHz

TIL input

Icc

rnA

f= 5 MHz (Note 1)
Vcc=5.5V;

TTL input
TIL input
CMOS input

ICC(S)TIL
ICC(S)TIL
IcC(S)CMOS

2
3
100

rnA
rnA

CE = V1H (0' C to 70' C)
CE = V1H (-40' C to 85' C)
CE = Vcc-0.3 to Vcc+ 1

Input Leakage

CIN

Input Capacitance

Output Voltages

Logic "1"
Logic "0"

Output Leakage
Output Capacitance

Power Suppy Current, Active

Power Supply Current, Standby

VOH
VOL

2.4

-10

Units Conditions

ItA

Note: (1) AC power supply current above 5 MHz: 2 mNMHz

DS11109C-2

2-34

28C64A
READ OPERATION
AC Characteristics

AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:

Parameter

Sym

VIH= 2.4V; VIL= 0.45V; VOH= 2.0V; VOL = 0.8V
1 TTL Load + 100 pF
20 nsec
Commercial (C):Tamb = 0' C to 70' C
Industrial
(1):Tamb = -40' C to 85' C

28C64A-15

28C64A-20

28C64A-25

Min

Max

Units

Conditions

Max
-

fAcc

150

200

250

CE to Output Delay

teE

150

200

250

OE = VIL

OE to Output Delay

toE

100

CE = VIL

CE or OE High to Output Float

toFF

Output Hold from Address, CE
or OE, whichever occurs first.

toH

Address to Output Delay

OE = CE = VIL

READ WAVEFORMS

VIH

Address
VIL
VIH

CE
VIL

VIH

VIL
VOH

Address Valid

<=-

"'--

tCE(2)

Data

I"'-

- - tOE(2) --

IIIII

High Z

\\\\\

VOL

... tOFF(1.3) ~
tOH

Valid Output

\ \\\1\

High Z

II II1I

fACC

Notes: (1) toFF is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to teE - toE after the falling edge of CE without impact on tE
(3) This parameter is sampled and is not 100% tested

2-35

DS11109C-3

28C64A
AC Testing Waveform:
Output Load:
Input Rise/Fall Times:
Ambient Temperature:

BYTE WRITE
AC Characteristics

Parameter

VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL
1 TTL Load + 100 pF
20 nsec
Commercial (C): Tamb = O' Cto 70' C
Industrial
(I): Tamb = -40' C to 85' C

Symbol

Min

Max

Units

=0.8V

Remarks

Address Set-Up Time

tAs

Address Hold Time

tAH

Data Set-Up Time

IDS

Data Hold Time

IDH

Write Pulse Width

twPL

100

Write Pulse High Time

twPH

OE Hold Time

toEH

OE Set-Up Time

toES

Data Valid Time

tDV

1000

Time to Device Busy

IDB

Write Cycle Time (28C64A)

twe

0.5 ms typical

twe

200

Ils

1OOIlS typical

Write Cycle Time (28C64AF)
Note:

(1)
(2)

Note 1

ns
ns

Note 2

A write cycle can be initiated CE or WE going low, whichever occurs last. The data is latched on
the positive edge of CE or WE, whichever occurs first.
Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until
tDH after the positive edge of WE or CE, whichever occurs first.

PROGRAMMING
Waveforms

Address

~::-+_4v~_
VIH

-----.---I
____t_t_A_S..
,

1.....
---

..
VIL
VIH
Data In

tAH

-----I:f~\

tWPL

I--tDv_ _

==-1

tDS~

------~1----_---------

-VIH
VIL _ _ _J

tOES

tDH
.......

JI--

j'-

~K
~--------------

l-tOEH
VOH-------1------------+---'~

Rdy/Busy
VOL

DS11109C-4

BuS~Ready

tDB~~'---4

I~..
-----twc----~----~----~

2-36

28C64A
DATA POLLING
Waveforms

Address

VIH

=><

Address Valid

VIL

~._ _ _ _--' ' - _ _ _

Last Written
Address Valid

tACC - -

CE VIH

V I"-"--'
L":......::.
-,,_ _ _ _ _ _...L.......L.L-."--<'-L-LJ -'-'''--''--''-'"''----+---_-----tWPH

VIH
WE
VIL
tOE

VIH -r77-r-+-----.,-""""....-":-<""""""'"""'"'<""7·/':--c-~,,
OE
VIL
VIH - - - - - t____
True Data Out

Data
VIL

------t--'

CHIP CLEAR

Waveforms

VIH - - - - - - - - - - - - . .
CE
VIL

~~------------------~/

I~
VIH

I~.---

----I~

~~--

-----------~I

VIL

tw = 10ms
ts =tH = 1~s
VH = 12.0V ±O.5V

SUPPLEMENTARY CONTROL
Mode
Chip Clear
Extra Row Read
Extra Row Write
Note: VH = 12.0V ±O.5V

A9
OE
WE
VH
VIL
X
VIH
VIL
A9 = VH
VIH
A9=VH
• Pulsed per programming waveforms.

CE
VIL
VIL

2-37

Vee

1101

Vee
Vee
Vee

Data Out
Data In

DS11109C·5

28C64A
DEVICE OPERATION
The Microchip Technology Inc 28C64A has four basic
modes of operation-read, standby, write inhibit, and
byte write-as outlined in the following table.

Operation Mode CE OE WE I/O

Second, there is a WE filtering circuit that prevents WE
pulses of less than IOns duration from initiating a write
cycle.
Third, holding WE or CE high or OE low, inhibits a write
cycle during power-on and power-off (Vec).

Rdy/Busy(1)
Write Mode

Read
Standby
Write Inhibit
Write Inhibit
Write Inhibit
Byte Write
Byte Clear

L
H
H

X
X

X
X
X

H
L

DoUT
HighZ
HighZ
HighZ
HighZ
DIN

H
H
H
H
H
L

Automatic Before Each "Write"
Note: (1) Open drain output.
(2) X : Any TTL level.

Read Mode
The 28C64A has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip enable (CE) is the power control and
should be used for device selection. Output Enable (OE)
is the output control and is used to gate data to the output
pins independent of device selection. Assuming that
addresses are stable, address access time (lACC) is
equal to the delay from CE to output (tCE). Data is
available at the output tOE after the falling edge of OE,
assuming that CE has been low and addresses have
been stable for at least tACC-tOE.

The 28C64A has a write cycle similar to that of a Static
RAM. The write cycle is completel~elf-timed and
initiated by a low going pulse on the WE pin. On the
falling edge of WE, the address information is latched.
On rising edge, the data and the control pins (CE and
OE) are latched. The Ready/Busy pin goes toa logic low
level indicating that the 28C64A is in a write cycle which
signals the microprocessor host that the system bus is
free for other activity. When Ready/Busy goes back to
a high, the 28C64A has completed writing and is ready
to accept another cycle.

Data Polling
The 28C64A features Data polling to signal the completion of a byte write cycle, During a write cycle, an
attempted read of the last byte written results in the data
complement of 1/07 (1/00 to 1/06 are indeterminable).
After completion of the write cycle, true data is available.
Data polling allows a simple read/compare operation to
determine the status of the chip eliminating the need for
external hardware.

Standby Mode
The 28C64A is placed in the standby mode by applying
a high signal to the CE input. When in the standby mode,
the outputs are in a high impedance state, independent
of the OE input.

Data Protection

Electronic Signature for Device Identification
An extra row of 32 bytes o/EEPROM memory is available to the user for device identification. By raising A9
to 12V ±0.5V and using address locations 1FEO to
1FFF, the additional bytes can be written to or read from
in the same manner as the regular memory array.

In ordertoensure data integrity, especially during critical
power-up and power-down transitions, the following
enhanced data protection circuits are incorporated:

Optional Chip Clear

First, an internal Vce detect (3.3 volts typical) will inhibit
the initiation of non-volatile programming operation when
Vcc is less than the Vcc detect circuit trip.

All data may be cleared to l's in a chip clear cycle by
raising OE to 12 volts and bringing the WE and CE low.
This procedure clears all data, except for the extra row.

DSlll09C-6

2-38

28C64A
NOTES:

2-39

DS11109C-7

28C64A
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the

factory or the listed sales offices.

PART NUMBERS

~AF""'L

1'£_'
I Temperature
Range:

I
I

Access Time:

Option:

1 - - - - - - - - 1 Device:

DS11109C-8

J
K
L
P
SO
Blank
I

Cerdip
Ceramic Leadless Chip Carrier (LCC)
Plastic Leaded Chip Carrier (PLCC))
Plastic DIP
Plastic Small Outline IC
O' C to 70' C
-40' C to 85' C

15
20
25

150nsec
200 nsec
250 nsec

F
X

=twc= lms
= twc = 200IJS
Pin 1 NC (Pin 2 PLCC). twc = 1ms

64K

(8K x 8) CMOS EEPROM

2-40

28C64A
DICE FORM

Microchip

64K (8K X 8) CMOS Electrically Erasable PROM
DIE CONFIGURATION

FEATURES
•

•

•
•

•

Die Size: 134 x 206 sq. mils

~~~~~~ ~~~~<

250ns Access Time
CMOS Technology for Low Power Dissipation
-30mA Active
-1 OO~A Standby
Fast Byte Write Time-1 ms
Automatic Write Operation
-Internal Control Timer
-Auto-Clear Before Write Operation
-On-Chip Address and Data Latches
Data Polling
Ready/Busy
Chip Clear Operation
Enhanced Data Protection
-Vee Detector
-Pulse Filter
-Write Inhibit
Electronic Signature for Device Identification
5-Volt-Only Operation
Commercial Temperature Range:
-0' Cto 70' C
Available in Wafer Form or Waffle Pack

DESCRIPTION
The Microchip Technology Inc 28C64A is a CMOS 64K
non-volatile electrically Erasable and Programmable
Read Only Memory. The 28C64A is accessed like a
static RAM for the read or write cycles without the need
of external components. During a "byte write", the
address and data are latched internally, freeing the
microprocessor address and data bus for other operations. Following the initiation of write cycle, the device
will go to a busy state and automatically clear and write
the latched data using an internal control timer. To
determine when the write cycle is complete, the user has
a choice of monitoring the Ready/Busy output or using
Data polling. The Ready/Busy pin is an open drain
output, which allows easy configuration in wired-or
systems. Alternatively, Data polling allows the user to
read the location last written to when the write operation
is complete. CMOS design and processing enables this
part to be used in systems where reduced power consumption and reliability are required.

BLOCK DIAGRAM

1100 .... • .. 1/07

VSS-'~==D;a=~~p;ro=te=c=tio=n~-----lHHHHHHHr--'
Vcc-..

Circuitry

C'E-.

gu~~u~~~~~(e

~---

Control Logic
Auto EraseIWrite
Timing

WE-.
Rdy! _

BuSy

Da~
Poll

Program Voltage
Generation

]

Dec~derD

Input/Output
Buffers

I
YGating

at _ _

Decoder

2-41

64Kbit
Cell Matrix

DS111358-1

28C64A

DICE FORM
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE
Name

Function

AO -A12
CE
-OE
WE
1/00 -1/07
ROY/Busy
vcc
VSS
NU

Address Inputs
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
Ready/Busy
+5V Power Supply
Ground
Not Used; No External
Connection is Allowed

MAXIMUM RATINGS·
Vcc and input voltages w.r.t. VSS ........ -0.6V to + 6.2SV
Voltage on OE w.r.t. Vss ........................... -0.6V to + 13.SV
Voltage on A9 w.r.t. Vss ............................ -0.6V to +13.SV
Output Voltage w.r.t. Vss .................... -0.6V to Vcc+0.6V
Storage temperature .......................... -65· C to 125" C
Ambient temp. with power applied ........ -SO" C to 9S" C

READ / WRITE OPERATION
DC Characteristics

vcc = +5V ±10%
Commercial: lamb=

Status

Symbol

Min

Max

Logic "1"
Logic "0"

VIH
Vil

2.0
-0.1

Vcc+1
0.8

V
V

Input Leakage

III

-10

J.lA

Input Capacitance

CIN

Parameter
Input Voltages

0" C to 70" C

Units Conditions

VIN= -O.tV to Vcc+1
VIN= OV; lamb = 25" C;

f = 1 MHz
Output Voltages

Logic "1"
Logic "0"

Output Leakage

VOH
VOL

2.4

IlO

-10

CoUT

Output Capacitance

0.45

V
V

J.LA

IOH = -400J.LA
IOl= 2.1mA
VOUT= -0.1V to Vcc+0.1V
VIN= OV; lamb = 25· C;

f = 1 MHz
Power Suppy Current, Active

TTL input

Icc

f = S MHz (Note 1)
Vcc = 5.5V;

Power Supply Current, Standby

TTL input
CMOS input

ICC(S)TTl
ICC(S)CMOS

2
100

mA
J.lA

CE =VIH
CE = Vcc-0.3 to Vcc+ 1

Note: (1) AC power supply current above S MHz: 2 mA/MHz

DS11135B-2

2-42

28C64A
READ OPERATION
AC Characteristics

AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:

Parameter

Sym

VIH= 2.4V; VIL= 0.45V; VOH= 2.0V; VOL = 0.8V
1 TTL Load + 100 pF
20 nsec
Commercial: Tamb = O'C to 70'C

28C64A-25
Min

Units

tAee

250

CE to Output Delay

teE

250

toE

CE or OE High to Output Float

toFF

Output Hold from Address, CE
or OE, whichever occurs first.

toH

Conditions

Max

Address to Output Delay

OE to Output Delay

DICE FORM

100

OE =CE = VIL

OE =VIL

CE = \ilL

READ WAVEFORMS

VIH
Address
VIL
VIH

.,..

Address Valid
~

CE
VIL

VIH

~ I.- - toE(2) - -

1111
\\\\'

High Z

VOL

k?«-

- -~

VIL
VOH

teE(2)

Data

... toFF(1,3) toH

Valid Output

\0,\ \

High Z

'I /

tAce
Notes: (1) toFF is specified forOE or CE, whichever occurs first
(2) OE may be delayed up to tE - toE after the falling edge of CE without impact on tE
(3) This parameter is sampled and is not 100% tested

2-43

OS111358-3

28C64A

DICE FORM
VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL
1 TTL Load + 100 pF
20 nsec
Commercial: Tamb = O'C to 70'C

AC Characteristics

AC Testing Waveform:
Output Load:
Input Rise/Fall Times:
Ambient Temperature:

Parameter

Symbol

Min

Address Set-up Time

tAS

Address Hold Time

tAH

100

Data Set-Up Time

tos

100

Data Hold Time

toH

Write Pulse Width

twPL

100

Write Pulse High Time

twPH

OE Hold Time

toEH

OE Set-Up Time

toES

Data Valid Time

tDV

1000

Time to Device Busy

toB

Write Cycle Time (28C64A)

twe

BYTE WRITE

Note:

Max

Units

= 0.8V

Remarks

Note 1

Note 2

0.5 ms typical

(1 ) A write cycle can be initiated CE or WE going low, whichever occurs last. The data is latched on
the positive edge of CE or WE, whichever occurs first.
(2) Data must be valid within 1OOOns max. after a write cycle is initiated and must be stable at least
until toH after the positive edge of WE or CE, whichever occurs first.

PROGRAMMING
Waveforms

Address

~:~-tA-S--.--.------t-AH-~------------------------VIH - - - - - - "
•

VIL

tWPL
__

~tDV

Data In

VIH

-.,k

:---:1

tDS~

_ _ _ _ _+t-_-<.71'"

_tDH

-'K>-_ _ _ _ _ __

VIL
-.
VIH
OE
VIL

tOES

T,------

----'/~

--It~EH

VOH
Rdy/Busy
VOL

DS11135B-4

1~.
______

L "\l-

Bu~y ;f"ReadY
twc _ _ _ _~~~t~D~B~~~==~~~==~

2-44

28C64A

DICE FORM

DATA POLLING

Waveforms

Address

VIH
VIL

=><

Address Valid

Last Written
Address Valid

~._ _ _ _-', ,-'_ _ _

tACC - -

CE VIH ~
V I,..>....,;,~
L -'~
-

_____...L....L...L-L-...~~A.-''--''---''-'~

tCE

-+-__________

___

tWPH

VIH

WE
VIL
tOE

VIH
OE
VIL
VIH

----+---..

True Data Out

Data
VIL

CHIP CLEAR

Waveforms

VIH - - - - - - - - " " "
CE

VIL
VH
OE

/
VIH - - - - - - - - - '
1....
---

tw ----I~

VIH

WE
VIL

tw = 10ms
ts =tH = llJs
VH = 12.0V ±O.5V

SUPPLEMENTARY CONTROL
Mode

Chip Clear
Extra Row Read
Extra Row Write
Note: VH = 12.0V ±O.5V

VIL
VIL

VH
VIL
X
VIL
VIH
A9= VH
VIH
A9=VH
• Pulsed per programming waveforms.

2-45

Vee

1/01

Vee
Vee
Vee

Data Out
Data In

08111358-5

28C64A

DICE FORM

DEVICE OPERATION
The Microchip Technology Inc 28C64A has four basic
modes of operation-read, standby, write inhibit, and
byte write-as outlined in the following table.

Operation Mode CE OE WE I/O

Rdy/BusY(1)
Write Mode

Read
Standby
Write Inhibit
Write Inhibit
Write Inhibit
Byte Write
Byte Clear

L
H
H

DoUT

X
X

X
X
X

High Z
HighZ
High Z
HighZ
DIN

H
L

H
H
H
H
H
L

Automatic Before Each "Write"
Note: (1) Open drain output.
(2) X = Any TTL level.
Read Mode

The 28C64A has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip enable (CE) is the power control and
should be used for device selection. Output Enable (OE)
is the output control and is used to gate data to the output
pins independent of device selection. Assuming that
addresses are stable, address access time (tACC) is
equal to the delay from CE to output (tCE). Data is
available at the output tOE after the falling edge of OE,
assuming that CE has been low and addresses have
been stable for at least tACC-tOE.

The 28C64A has a write cycle similar to that of a Static
RAM. The write cycle is completel~elf-timed and
initiated by a low going pulse on the WE pin. On the
falling edge of WE, the address information is latched.
On rising edge, the data and the control pins (CE and
OE) are latched. The Ready/Busy pin goes to a logic low
level indicating that the 28C64A is in a write cycle which
signals the microprocessor host that the system bus is
free for other activity. When Ready/Busy goes back to
a high, the 28C64A has completed writing and is ready
to accept another cycle.

Data Polling
The 28C64A features Data polling to signal the completion of a byte write cycle. During a write cycle, an
attempted read of the last byte written results in the data
complement of 1107 (1/00 to 1/06 are indeterminable).
After completion of the write cycle, true data is available.
Data polling allows a simple read/compare operation to
determine the status of the chip eliminating the need for
external hardware.

Standby Mode

The 28C64A is placed in the standby mode by applying
a high signal to the CE input. When in the standby mode,
the outputs are in a high impedance state, independent
of the OE input.
Data Protection

Electronic Signature for Device Identification

An extra row of 32 bytes of EEPROM memory is available to the user for device identification. By raising A9
to 12V ±O.SV and using address locations 1FEO to
1FFF, the additional bytes can be written to or read from
in the same manner as the regular memory array.

In orderto ensure data integrity, especially during critical
power-up and power-down transitions, the following
enhanced data protection circuits are incorporated:

Optional Chip Clear

First, an intemal vcc detect (3.3 volts typical) will inhibit
the initiation of non-volatile programming operation when
Vec is less than the Vcc detect circuit trip.

All data may be cleared to l's in a chip clear cycle by
raising OE to 12 volts and bringing the WE and CE low.
This procedure clears all data, except for the extra row.

OS11135B-6

2-46

28C64A

DICE FORM

NOTES:

2-47

05111358-7

28C64A

DICE FORM

SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.

PART NUMBERS
28C64A • 25 • I W

~P"-'

W
S

L..----I Temperature
Range:
L..-_ _ _--I
L..-_ _ _ _ _ _-I

D8111358-8

Blank

Access Time:
Device:

25
2SC64A

2-48

Dice in Wafer Form
Dice in Waffle Pack
O' C to 70' C

250 nsec
(SK x S) CMOS EEPROM

Microchip

SECTION 3
EPROM PRODUCT SPECIFICATIONS
27C64
27C128
27C256
27C512
27HC64
27HC256
27HC1616
27HC641
27Cxxx

64K (8K x 8) CMOS UV Erasable PROM ................................................................. 3128K (16K x 8) CMOS UV Erasable PROM ............................................................. 3256K (32K x 8) CMOS UV Erasable PROM ............................................................. 3512K (64K x 8) CMOS UV Erasable PROM .................•........................................... 364K (8K x 8) High Speed CMOS UV Erasable PROM ............................................. 3256K (32K x 8) High Speed CMOS UV Erasable PROM ......................................... 3256K (16K x 16) High Speed CMOS UV Erasable PROM ....................................... 364K (8K x 8) High Speed CMOS UV Erasable PROM ............................................. 327Cxxx EPROM Family Programming Algorithm ..................................................... 3-

3-i

1
9
17
25
33
41
49
57
65

DS00018C

Microchip

DS00018C

3-ii

27C64

Microchip

64K (8K X 8) CMOS EPROM
FEATURES

DESCRIPTION

• High speed performance
-120ns maximum access time
• CMOS Technology for low power consumption
-20mA Active current
-100J.lA Standby current
• Factory programming available
• Auto-insertion-compatible plastic packages
• Auto IOTM aids automated programming
• Separate chip enable and output enable controls
• High speed "express· programming algorithm
Organized 8K x 8: JEOEC standard pinouts
-28-pin Oual-in-line package
-32-pin Chip carrier (Ieadless or plastic)
-28-pin SOIC package
-Tape and reel
• Available for extended temperature ranges:
-Commercial: O· C to 70· C
-Industrial: -40· C to 85· C
-Automotive: -40· C to 125· C
-Military"" (8): -55· C to 125· C

The Microchip Technology Inc 27C64 is a CMOS 64K bit
(electrically) Programmable Read Only Memory. The
device is organized as 8K words by 8 bits (8K bytes).
Accessing individual bytes from an address transition or
from power-up (chip enable pin going low) is accomplished in less than 120ns. This very high speed device
allows the most sophisticated microprocessors to run at
full speed without the need for WAIT states. CMOS
design and processing enables this part to be used in
systems where reduced power consumption and reliability are requirements.
A complete family of packages is offered to provide the
most flexibility in applications. For surface mount applications, PLCC or SOIC packaging is available. Tape
and reel packaging is also available for PLCC or SOIC
packages. U.V. erasable versions are also available.

PIN CONFIGURATIONS
Top View
Vpp

Vee

A12
A7

PGM

.... ~II:~!l~o
«>2>Il..Z

/lJJ
A9

A6
".,

A11

OE
A10

CE
AO

05
04
03

06
02
Vss

DIP

EJ t~'Jt:'Jt~j~!~~Jl~Jl~J f~
AS i]
fM
A4 J]
:i!
A6

li
r;j
rilr~if~l:t:lr;lf~l:il

5fj~~8a8

PLCC/LCC

/lJJ

".,

A9
A11

PGM
NC

OE
CE

01
02
Vss

f..2j A10

AD JiJ
NC 3iJ
00 j~J

r.!i~

i§]

Vee

A4
A3
A2

A11
:~ NC

A3 i]
A2 i]
A1

/lJJ
A9

Vpp
A12
A7

A10

04
03

SOIC

"" See 27C64 Military Oata sheet OS60011
© 1990 Microchip Technology Inc.

3-1

DS11107F-1

27C64
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE
Name
AO - A12
CE
OE
PGM
Vpp
00-07
Vee
Vss
NC
NU

Maximum Ratings*

Function

Vee and input voltages w.r.t. Vss .......... -0.6V to +7.25V
Vpp voltage w.r.t. Vss during
programming ........................................ -0.6V to + 14V
Voltage on A9 W.r.t. Vss ............................ -0.6V to +13.5V
Output voltage w.r.t. Vss .................... -0.6V to Vee + 1.0V
Storage temperature .......................... -65· C to 150' C
Ambient temp. with power applied ..... -65' C to 125' C

Address Inputs
Chip Enable
Output Enable
Program Enable
Programming Voltage
Data Output
+5V Power Supply
Ground
No Connection; No Internal
Connections
Not Used; No External
Connection Is Allowed

'Notice: Stresses above those listed under"Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at those or any
other conditions above those indicated in the operation listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

Vee = +5V ±10%
Commercial: Tamb= O' Cto 70' C
Tamb= -40' C to 85' C
Industrial:
Automotive: Tamb= -40' C to 125' C

READ OPERATION
DC Characteristics

Part*

Status

Symbol

Min

Max

Input Voltages

all

Logic "1"
Loaic "0"

Input Leakage

all

VIH
VIL
III

2.0
-0.5
-10

Vee+1
0.8
10

Output Voltages

all

2.4

Parameter

V
V
I1A

VIN= 0 to Vee
IOH=-400~

V
V

Output Leakage

all

VOH
VOL
ILO

Input Capacitance

all

CIN

Output Capacitance

all

GoUT

Power Suppy Current,
Active

TTL input
TTL input

lee1
lee2

20
25

mA
mA

S
X
all
all
all

TTL input
TTL input
CMOS input
Read Mode
Read Mode

lee(s)

2
3
100
100
Vee

mA
mA
I1A
I1A
V

Power Supply Current,
Standby
Ipp Read Current
Vpp Read Voltaae

Logic "1"
LogiC "0"

Units Conditions

Ipp
VPp

-10

Vee-0.7

0.45
10

IOL=2.1mA
VOUT = OV to Vee
VIN = OV; Tamb = 25' C;
f = 1MHz
VOUT= OV;Tamb= 25' C;
f= 1MHz
Vee = 5.5V; Vpp = Vee;
f= 1MHz;
OE = CE=VIl.;
10ut=OmA;
VIL= -0.1 to 0.8 V;
VIH= 2.0 to Vee;
Note 1

CE = Vee ±O.2V
VPP= 5.5V
Note 2

* Parts:
S = Standard Power; X = Extended Temp. Range;
Notes: (1) AC Power component above 1MHz: 8mA up to maximum frequency.
(2) Vee must be applied before VPP, and be removed simultaneously or after VPP.

DS11107F-2

3-2

27C64
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:

READ OPERATION
AC Characteristics

Parameter

Sym 27C64·12
Min

Address to Output Delay tAcc

VIH= 2.4V and VIL= 0.45V;
1 TIL Load + 100 pF
10nsec
Commercial: Tamb= O'
Tamb = -40'
Industrial:
Automotive: Tamb = -40'

27C64·15 27C64·17 27C64·20

VOH = 2.0V VOL =0.8V

C to 70' C
C to 85' C
C to 125' C

27C64·25 Units

Max Min

Max

120

150

170

200

250

CE to Output Delay

teE

120

150

170

200

250

OE to Output Delay

toE

100

CE or OE to OIP High
Impedance

tOFF

Output Hold from
Address CE or OE,
whichever occurs first

toH

Conditions

CE =OE =VIL

OE = VIL
CE = VIL

READ WAVEFORMS

VIH
Address Valid

Address
VIL
VIH
CE
VIL

VIH
OE
VIL

Outputs
00-07

VOH

HighZ

Valid Output

VOL
tACC

Notes: (1) toFF is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to tCE - toE after the falling edge of CE without impact on tCE
(3) This parameter is sampled and is not 100% tested.

3-3

DS11107F-3

27C64
PROGRAMMING
DC Characteristics
Parameter
Input Voltages

Ambient Temperature: Tamb = 2S· C ±S· C
Vee = 6.SV ± 0.2SV, Vpp = VH = 13.0V ± 0.2SV

Status

Symbol

Min

Max

Units

Logic "1"
Logic '0"

VIH
VIL

2.0
-0.1

Vee+l
0.8

V
V

III

-10

IlA

VIN = OV to Vee

VOH
VOL

2.4
O.4S

V
V

IOH = -4OOIlA
IOL=2.1mA

Input Leakage
Output Voltages

Logic "1"
Logic "0"

Conditions

Vee Current, program & verify

lee2

Note 1

Vpp Current, program

IpP2

Note 1

12.5

A9 Product Identification

11.S

Note: (1) Vee must be applied simultaneously or before VPP and removed simultaneously or after Vpp

PROGRAMMING
AC Characteristics
for Program, Program Verify
and Program Inhibit Modes

Parameter

AC Testing Waveform: VIH= 2.4 V and VIL= O.4S V; VOH= 2.0 V; VOL = 0.8 V
Output Load:
1 TTL Load + 100 pF
Ambient Temperature: Tamb = 2S· C ±S· C
Vee = 6.SV ± 0.2SV, Vpp = VH = 13.0V ± 0.2SV

Symbol

Min

Max

Address Set-Up Time

tAS

Ils

Data Set-Up Time

tos

Ils

Data Hold Time

toH

Ils

Address Hold Time

tAH

Ils

Float Delay (2)

toF

Vee Set-Up Time

tves

Program Pulse Width (1)

tpw

CE Set-Up Time

teES

!lS

OE Set-Up Time

tOES

Ils

Vpp Set-Up Time

tvps

Ils

Data Valid from OE

toE

130

Units

Remarks

ns
Ils

10S

100

Ils

1OOIlS typical

Notes: (1) For express algorithm, initial programming width tolerance is 1OO!lSec ±S%.
(2) This parameter is only sampled and not 100% tested. Output float is defined as the pOint where data
is no longer driven (see timing diagram).

DS11107F-4

3-4

27C64
PROGRAMMING

Waveforms
1 4 - - - - - - Program

-------4*_---- Verify ------l~

VIH
Address
VIL
VIH
Data
VIL

Vpp
5.0V

Vcc
5.0V
VIH
CE
VIL

toE

VIH

(1)

OE
VIL

(1) IDF and tOE are characteristics of the device but must be accommodated by the programmer
(2) Vcc = 6.5 V ±0.25 V, Vpp = VH = 13.0 V ±O.25 V for express algorithm

Notes:

Read Mode

MODES
Operation Mode CE
Read
Program
Program Verify
Program Inhibit
Standby
Output Disable
Identity
x

VIL
VIL
VIL
VIH
VIH
VIL
VIL

PGM

VPp

00-07

VIL
VIH
VIL

VIH
VIL
VIH

X
X

VIH
VIL

VIH
VIH

X
X
X
X
X
X

DoUT

X
X

Vee
VH
VH
VH
Vee
Vee
Vce

(See Timing Diagrams and AC Characteristics)
Read Mode is accessed when

DIN
DoUT

a) the CE pin is low to power up (enable) the chip

HighZ
HighZ
HighZ
Identity Code

b) the OE pin is low to gate the data to the output
pins.

Don't Care

For Read operations, if the addresses are stable, the
address access time (tACC) is equal to the delay from CE
to output (tCE). Data is transferred to the output after a
delay from the falling edge of OE (tOE).

3-5

DS11107F-5

27C64
Standby Mode

The standby mode is defined when the CE pin is high
(VIH) and a program mode is not defined.
When these condition are met, the supply current will
drop from 20mA to 100IlA.

After the array has been programmed it must be verified
to ensure all the bits have been correctly programmed.
This mode is entered when all the following conditions
are met:
a)
b)
c)
d)
e)

Output Enable

This feature eliminates bus contention in multiple bus
microprocessor systems and the outputs go to a high
impedance when the following condition is true:
The OE pin is high and a program is not defined.
Erase Mode (U.V. Windowed Versions)

Windowed products offer the ability to erase the memory
array. The memory matrix is erased to the all1's state
as a result of being exposed to ultraviolet light. To
ensure complete erasure, a dose of 15 watt-second/cm2
is required. This means that the device window must be
placed within one inch and directly underneath an ultraviolet lamp with a wavelength of 2537 Angstroms, intensity of 12,OOOIlW/cm2 for approximately 20 minutes.
Programming Mode

The express algorithm has been developed to improve
on the programming throughput times in a production
environment. Up to 10 100-microsecond pulses are
applied until the byte is verified. No overprogramming is
required. A flowchart of the express algorithm is shown
in Figure 1.

Vcc is at the proper level,
Vpp~ at the proper VH level,
the CE line is low,
the PGM line is high, and
the OE line is low.

When programming multiple devices in parallel with
different data, only CE or PGM need be under separate
control to each device. By pulsing the CE or PGM line
low on a particular device in conjunction with the PGM or
CE line low, that device will be programmed; all other
devices with CE or PGM held high will not be programmed with the data, although address and data will
be available on their input pins (Le., when a high level is
present on CE or PGM); and the device is inhibited from
programming.
Identity Mode

In this mode specific data is outputted which identifies
the manufacturer as Microchip Technology Inc and
device type. This mode is entered when Pin A9 is taken
to VH (11.5V to 12.5V). The CE and OE lines must be
at VIL. AO is used to access any of the two non-erasable
bytes whose data appears on 00 through 07.

Programming takes place when:
a)
b)
c)
d)
e)

Vcc is brought to proper voltage,
Vpp is brought to proper VH level,
the CE pin is low,
the OE pin is high, and
the PGM pin is low.

Since the erased state is "1" in the array, programming
of "0" is required. The address to be programmed is set
via pins AO-A 12 and the data to be programmed is
presented to pins 00-07. When data and address are
stable, OE is high, CE is low and a low-going puiseon the
PGM line programs that location.

DS11107F-6

Pin-

Identity

Input

0 00 0 0 0 0 0 H
7 6 5 4 3 2 1 0 e
x

VIL
VIH

0 0 1 0 1
0 0 0 0 0

!
Manufacturer
Device Type'

Output

0
0

0 1 29
1 0 02

• Code subject to change.

3-6

27C64
PROGRAMMING - FIGURE 1
EXPRESS ALGORITHM
Conditions:

Tamb= 25° C ±5° C
Vee = 6.5 ±O.25V
Vpp = 13.0 ±O.25V

ADDR = First Location

Vee = 6.5V
Vpp= 13.0V

Verify
Byte

Pass

>-'--==----,

All

3-7

DS11107F-7

27C64
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.

PART NUMBERS

~C~-25II~

I""""

J
K
L

P
SO

II Temperature
Range:

O' C to 70' C
I

E
' - - - - - - - 1 Access Time:

L..------------~·D
I
eVlce:

DS11107F-8

Cerdip
Ceramic Leadless Chip Carrier
Plastic Leaded Chip Carrier
Plastic DIP
Plastic SOIC

12
15
17
20
25
27C64

3-8

-40' C to 85' C
-40' C to 125' C

120 nsec
150 nsec
170 nsec
200 nsec
250 nsec
64K (8K x 8) CMOS EPROM

27C128

Microchip

128K (16K X 8) CMOS EPROM
FEATURES

DESCRIPTION

• High speed performance
-120ns Maximum access time
• CMOS Technology for low power consumption
-20mA Active current
-100IlA Standby current
• Factory programming available
• Auto-insertion-compatible plastic packages
• Auto 10TM aids automated programming
Separate chip enable and output enable controls
• High speed "express" programming algorithm
Organized 16K x 8: JEoEC standard pinouts
-28-pin oual-in-line package
-32-pin Chip carrier (Ieadless or plastic)
-28-pin SOIC package
-Tape and reel
Available for extended temperature ranges:
-Commercial: 0" C to 70" C
-Industrial: -40" C to 85" C
-Automotive: -40" C to 125" C
-Military**(8): -55" C to 125" C

The Microchip Technology Inc 27C128 is a CMOS 128K
bit (electrically) Programmable Read Only Memory. The
device is organized as 16K words by 8 bits (16K by1es).
Accessing individual bytes from an address transition or
from power-up (chip enable pin going low) is accomplished in less than 120ns. This very high speed device
allows the most sophisticated microprocessors to run at
full speed without the need for WAIT states. CMOS
design and processing enables this part to be used in
systems where reduced power consumption and reliability are requirements.
A complete family of packages is offered to provide the
most flexibility in applications. For surface mount applications, PLCC or SOIC packaging is available. Tape
and reel packaging is also available for PLCC or SOIC
packages. UV erasable versions are also available.

PIN CONFIGURATIONS
Top View
Vpp

Vee
PGM

A12
A7

A13
AS
A9
A11

<~~~~~~
AS

BE
CE

A2
A1

06
05
04
03

DIP

:j!j A9

t:JL~Jl~Ji ~ il~Jl!:,Jt!?J

AS ~~.J
A4 '?~J
A3 j~.J

07
00
01
02
Vss

Vpp
A12
A7
A6
A5

All

fjj NC
fjj OE

rj~ A10

3§j
AO ]5]
NC
00

L2J
L2!

33]
j§]
r~l :01 r~lf~lf~l:~l r~l

o~~~8oC3

PLCC/LCC

[jj CE
!2207
:~} 06

Vee
PGM
A13
AS
A9
A11

A3
A2
A1

AO
00
01
02

07
06
05
04

A10

Vss

SOIC

** See 27C128 Military Data sheet OS60012

3-9

DS11003F-1

27C128
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE

Maximum Ratings·

Name

Function

AO-A13
CE

Address Inputs
Chip Enable
Output Enable
Program Enable
Programming Voltage
Data Output
+5V Power Supply
Ground
No Connection; No
Internal Connections
Not Used; No External
Connection Is Allowed

PGM
Vpp
00-07
Vcc
Vss
NC
NU

Vcc and input voltages w.r.t. Vss .......... -0.6V to +7.25V
Vpp voltage w.r.t. Vss during
programming ........................................ -0.6V to +14 V
Voltage on A9 w.r.t. Vss ............................ -0.6V to +13.5V
Output voltage w.r.t. Vss ...................... -0.6V to Vee + 1V
Storage temperature .......................... -65" C to 150" C
Ambient temp. with power applied ..... -65" C to 125" C
'Notice: Stresses above those listed under "Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device atthose or any
other conditions above those indicated in the operation listings
of this specnication is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

Vee = +5V ±1 0%
Commercial: Tamb= 0" C to 70" C
Industrial:
Tamb= -40" C to 85" C
Automotive: Tamb= -40" C to 125" C

READ OPERATION
DC Characteristics

Part'

Status

Symbol

Min

Max

Input Voltages

ali

Logic "1"
Logic ·0"

Input Leakage

all

V,H
VIL
III

2.0
-0.5
-10

Vee+1
0.8
10

Output Voltages

all

2.4

Parameter

V
V

!!A

VIN= Oto Vee

V
V

Output Leakage

all

VOH
VOL
ILO

Input Capacitance

all

CIN

Output Capacitance

all

GoUT

Power Suppy Current,
Active

S
X

TTL input
TTL input

lee1
lce2

20
25

mA
mA

Power Supply Current,
Standby

TTL input
TTL input
CMOS input
Read Mode
Read Mode

lee(s)

2
3
100
100
Vee

mA
mA

Ipp Read Current
Vpp Read Voltage

all
all
all

Logic "1"
Loaic "0"

Units Conditions

Ipp
Vpp

-10

Vee-0.7

0.45
10

/lA

/lA
/lA

IOH = -400/lA
IOL= 2.1mA
VOUT= OV to Vee
VIN = OV; Tamb = 25" C;
f = 1MHz
VOUT= OV;Tamb= 25" C;
f = 1MHz
Vee = 5.5V; Vpp = Vee;
f = 1MHz;
OE =CE = VII.;
lout = OmA;
VIL= -0.1 to 0.8 V;
VIH= 2.0 to Vee;
Note 1

CE = Vee +0.2V
Vpp = 5.5V
Note 2

• Parts:
S = Standard Power; X = Extended Temp. Range;
Noles: (1) AC Power component above 1MHz: 8mA up to maximum frequency.
(2) Vee must be applied before VPP, and be removed simultaneously or after VPP.

DS11003F-2

3-10

27C128
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:

READ OPERATION
AC Characteristics

Parameter

VIH= 2.4V and VIL= 0.45V;
1 TTL Load + 100pF
10nsec
Commercial: Tamb= O·
Tamb = -40·
Industrial:
Automotive: Tamb = -40·

VOH = 2.0V VOL =0.8V

C to 70· C
C to 85· C
C to 125· C

Sym 27C128-12 27C128-15 27C128-17 27C128-20 27C128-25

Min Max

Min Max Min Max Min

Max

Min

Units Conditions

Max

Address to Output Delay IACc

120

150

170

200

250

CE = OE = VIL

CE to Output Delay

tCE

120

150

170

200

250

OE= VIL

OE to Output Delay

toE

100

CE = VIL

CE or OE to OIP High
Impedance

toFF

Output Hold from
Address CE or OE,
whichever occurs first

toH

READ WAVEFORMS

VIH
Address
VIL
VIH

Address Valid
~

~ =-

CE
VIL

t:K
~

-tCE(2) VIH
VIL

Outputs
00-07

VOH

- - ~

k"c-

toE(2)

HighZ

III
\\\'

VOL

toFF(1,3) I-toH
r-

Valid Output

\1\\\1\ High Z

II/DV

IACC

Notes: (1) toFF is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to teE - toE after the falling edge of CE without impact on tCE
(3) This parameter is sampled and is not 100% tested.

3-11

DS11003F-3

27C128
Ambient Temperature: Tamb = 25" C ±5" C
Vee = 6.5V ±0.25V, Vpp= 13.0V ± 0.25V

PROGRAMMING
DC Characteristics
Parameter
Input Voltages

Status

Symbol

Min

Max

Units

Logic "1"
Logic "0"

VIH
VIL

2.0
-0.1

VeC+l
0.8

V
V

III

-10

I1A

VIN = OV to Vee

VOH
VOL

2.4
0.45

V
V

IOH = -4001lA
IOL=2.1mA

Input Leakage
Output Voltages

Logic "1"
Logic "0"

Conditions

Vee Current, program & verify

lce2

Note 1

Vpp Current,program

IpP2

Note 1

12.5

A9 Product Identification

11.5

Note. (1) Vee must be applied simultaneously or before VPP and removed simultaneously or after VPP

PROGRAMMING
AC Characteristics
for Program, Program Verify
and Program Inhibit Modes

Parameter

AC Testing Waveform: VIH= 2.4 V and VIL= 0.45 V; VOH = 2.0 V; VOL = 0.8 V
Output Load:
1 TTL Load + 100 pF
Ambient Temperature: Tamb = 25" C ±S" C
Vee = 6.5V ± 0.25V, VPP = 13.0V ± 0.25V

Symbol

Min

Address Set-Up Time

lAS

I1S

Data Set-Up Time

IDS

I1s

Data Hold Time

IDH

I1S

Address Hold Time

IAH

I1s

Float Delay (2)

IDF

Vee Set-Up Time

IVes

Program Pulse Width (1)

IPw

CE Set-Up Time

teES

I1s

OE Set-Up Time

toES

I1S

VPP Set-Up Time

IVPS

I1s

Data Valid from OE

toE

Max

130

Units

Remarks

ns
I1s

105

100

1001lS typical

IlS

Notes: (1) For express algorithm, initial programming width tolerance is 1OOllSec ±5%.
(2) This parameter is only sampled and not 100% tested. Output float is defined as the point where data
is no longer driven (see timing diagram).

DS11003F-4

27C128
PROGRAMMING

Waveforms
1 4 - - - - - - Program------I4---- Verify

-----I~

VIH
Address

Address Stable
VIL
VIH

HighZ

Data
VIL
IDH

13.0V(2)
Vpp
5.0V

Vcc
5.0V
VIH
CE
VIL
toE
(1 )

VIH
OE
VIL

Notes:

(1) IDF and toE are characteristics of the device but must be accommodated by the programmer
(2) Vcc = 6.5 V ±O.25 V. VPp = VH = 13.0 V ±O.25 V for express algorithm

MODES

Read Mode

Operation Mode CE

PGM

Vpp

A9 00-07

Read
Program
Program Verify
Program Inhibit
Standby
Output Disable
Identity

VIL
VIH
VIL
X
X
VIH
VIL

VIH
VIL
VIH
X
X
VIH
VIH

Vee
VH
VH
VH
Vee
Vee
Vee

X
X
X
X
X
X
VH

VIL
VIL
VIL
VIH
VIH
VIL
VIL

(See Timing Diagrams and AC Characteristics)
Read Mode is accessed when

[)oUT

DIN
DoUT

a) the CE pin is low to power up (enable) the chip

HighZ
HighZ
HighZ
Identity Code

b) the OE pin is low to gate the data to the output
pins.

x= Don' Care
For Read operations. if the addresses are stable. the
address access time (lAcc) is equal to the delay from CE
to output (tCE). Data is transferred to the output after a
delay from the falling edge of OE (tOE).

3-13

DS11003F-5

27C128
Standby Mode
The standby mode is defined when the CE pin is high
(VIH) and a program mode is rot defined.
When these condition are met, the supply current will
drop from 20mA to 1001lA.

After the array has been programmed it mllst be verified
to ensure all the bits have been correctly programmed.
This mode is entered when all the follpwing conditions
are met:
a)
b)
c)
d)
e)

Output Enable
This feature eliminates bus contention in multiple bus
microprocessor systems and the outputs go to a high
impedance when the following condition is true:
The OE pin is high and a program is not defined.
Erase Mode (U.V. Windowed Versions)
Windowed products offerthe ability to erase the memory
array. The memory matrix is erased to the all 1's state
as a result of being exposed to ultraviolet light. To
ensure complete erasure, a dose of 15 watt-second/cm"
is required. This means that the device window must be
placed within one inch and directly underneath an ultraviolet lamp with a wavelength of 2537 Angstroms, intensityof 12,000j!W/cm" for approximately 20 minutes.
Proorammjng Mode
The express algorithm has been developed to improve
on the programming throughput times in a production
environment. Up to 10 100-microsecond pulses are
applied until the byte Is verified. No overprogramming is
required. A flowchart of the express algorithm is shown
in Figure1.

Vee is at the proper level,
VPp is at the proper VH level,
the CE line is low,
the PGM line is high, and
the OE line is low.

When programming multiple devices in paral/el with
different data, only CE or PGM need be under separate
control to each device. By pulsing the CE or PGM line
low on a particular device in conjunction with the PGM or
CE line low, that device will be programmed; all other
devices with CE or PGM held high will not be programmed with the data, although address and data will
be available on their input pins (i.e., when a high level is
present on CE or PGM); and the device is inhibited from
programming.
Identity Mode
In this mode specific data is outputted which identifies
the manufacturer as Microchip Technology Inc and
device type. This mode is entered when Pin A9 is taken
to VH (11.5V to 12.5V). The CE and OE lines must be
at VIL. AO is used to access any of the two non-erasable
bytes whose data appears on 00 through 07.

Programming takes place when:
Plna)
b)
c)
d)
e)

Vce is brought to proper voltages,
Vpp is brought to proper VH level,
the CE pin is low,
the OE pin is high, and
the PGM pin is low.

Since the erased state is "1" in the array, programming
of "0' is required. The address to be programmed is set
via pins AO-A 13 and the data to be programmed is
presented to pins 00-07. When data and address are
stable, CE is low and a low-going pulse on the PGM line
programs that location.

DS11003F-6

Identity

Input
AO

i
Manufacturer
Device Type'

VIL
VIH

Output
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0 1 0 1
1 0 0 0 0

0
0

e
x

0 1 29
1 1 83

• Code subject to change.

3-14

27C128
PROGRAMMING· FIGURE 1
EXPRESS ALGORITHM
Conditions:

Tamb = 2S· C ±S· C
Vee = 6.S ±O.2SV
VPp = 13.0 ±0.2SV
ADDR = First Location

Vee = 6.SV
VPp= 13.0V

3-15

DS11003F-7

27C128
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.

PART NUMBERS

~~-251/~
J

I"""'·

K
L
P
SO

'I Temperature
Range:

L - - - - - - I Access Time:

DS11003F-8

Device:

12
15
17
20
25

27C128

3-16

Cerdip
Ceramic Leadless Chip Carrier
Plastic Leaded Chip Carrier
Plastic DIP
Plastic SOIC

O· C to 70· C
-40· C to 85· C
-40· C to 125· C

120 nsec
150 nsec
170 nsec
200 nsec
250 nsec
128K (16K

x 8) CMOS EPROM

27C256

Microchip

256K (32K X 8) CMOS EPROM
FEATURES

DESCRIPTION

• High speed performance
-120ns maximum access time
• CMOS Technology for low power consumption
-20mA Active current
-1 OO~ Standby current
• Factory programming available
• Auto-insertion-compatible plastic packages
• Auto 10TM aids automated programming
• Separate chip enable and output enable controls
• High speed "express" programming algorithm
• Organized 32K x 8: JEOEC standard pinouts
-28-pin Oual-in-line package
-32-pin Chip carrier (Ieadless or plastic)
-28-pin SOIC package
-Tape and reel
Available for extended temperature ranges:
-Commercial: 0" C to 70" C
-Industrial: -40" C to 85" C
-Automotive: -40" C to 125" C
-Military" (8): -55" C to 125" C

The Microchip Technology Inc 27C256 is a CMOS 256K
bit (electrically) Programmable Read Only Memory. The
device is organized as 32K words by 8 bits (32K bytes).
Accessing individual bytes from an address transition or
from power-up (chip enable pin going low) is accomplished in less than 120ns. This very high speed device
allows the most sophisticated microprocessors to run at
full speed without the need for WAIT states. CMOS
design and processing enables this part to be used in
systems where reduced power consumption and reliability are requirements.
A complete family of packages is offered to provide the
most flexibility in applications. For surface mount applications, PLCC or SOIC packaging is available. Tape
and reel packaging is also available for PLCC or SOIC
packages. UV erasable versions are also available.

PIN CONFIGURATIONS
Top View
Vpp

Vee

Vpp

Vee

A12

A14
A13

A12
A7
A6
AS
A4
A3
A2
Al

A14
A13
AS
A9
All

<~~~~~~
L~Jl~Jl~J:~ It~Jl~Jl~J

AB
A9
All

DE
A2

Al0

CE
07
06
05
04
03

01
02
Vss

DIP

A6
AS EJ
A4
A3
A2 _9~j
Al _lpJ
AO jIJ

'.'

:y~ AS
f28
A9

C~7 All

~~j

:j~ NC

[3!..5 OE
L2_4 A10

[.:2"; CE
L2_2 07

_iii
00 jiJ

fjj 06
f~:f~lf~l :~l :~l:~~ f~l

oS~~8o(3

PLCC/LCC

DE
Al0

07
06
05
04
03

00
01
02
Vss

SOIC

•• See 27C256 Military Data sheet OS60013

3-17

D811001 F-1

27C256
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE

Maximum Ratings·

Name

Function

AO - A14
CE
OE
Vpp
00-07
Vee
vss
NC

Address Inputs
Chip Enable
Output Enable
Programming Voltage
Data Output
+5V Power Supply
Ground
No Connection;
No Internal Connection
Not Used; No External
Connection is Allowed

Vee and input volt~ges w.r.1. Vss .......... -0.6V to +7.25V
Vpp voltage w.r.1. Vssduring
programming ..................................... -Q.6V to +14.0V
Voltage on A9 w.r.1. Vss ............................ -0.6V to + 13.5V
Output voltage w.r.1. Vss .................. -0.6V to Vee + 1.0V
Storage temperature .......................... -65· C to 150' C
Ambient temp. with power applied ..... -65' C to 125' C
"Notice: Stresses above those listed under"Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at those or any
other conditions above those indicated in the operation listings
of this specification is not implied. Exposure to maximum rating
conditions for extended period!; may affect device reliability.

Vee = +5V ±1 0%
Commercial: Tamb= O' C to 70' C
Indu!;trial:
Tamb= -40' C to 85' C
Automotive: Tamb= -40' C to 125' C

READ OPERATION
DC Characteristics

Part·

Status

Symbol

Min

Max

Input Voltages

all

Logic "1"
Logic "0"

Input Leakage

all

VIH
Vil
III

2.0
-0.5
-10

Vee+1
0.8
10

Output Voltages

all

2.4

Parameter

V
V
I1A

VIN= 0 to Vee

V
V

Output Leakage

all

VOH
VOL
IlO

Input Capacitance

all

CIN

Output Capacitance

all

CoUT

Power Suppy Current,
Active

S
X

TTL input
TTL input

lee1
lee2

20
25

mA
mA

Power Supply Current,
Standby

S
X
all
all
all

TTL input
TTLinput •
CMOS input
Read Mode
Read Mode

lee(s)

2
3
100
100
Vee

mA
mA

Ipp Read Current
Vpp Read Voltage

Logic "1"
Logic "0·

Units Conditions

Ipp
Vpp

-10

Vee-0.7

0.45
10

ItA

IOH = -4001tA
IOl= 2.1mA
VOUT = OV to Vee

ItA
ItA
V

VIN = OV; Tamb = 25' C;
f= 1MHz
VOUT= OV;Tamb= 25' C;
f = 1MHz
Vee = 5.5V; Vpp = Vee;
f = 1MHz;
OE = CE = VII.;
lout = OmA;
Vll= -0.1 to 0.8 V;
VIH= 2.0 to Vee;
Note 1

CE = Vee ±O.2V
Vpp= 5.5V
Note 2

" Parts:
S = Standard Power; X = Extended Temp. Range;
Notes: (1) AC Power component above 1MHz: 5mA up to maximum frequency.
(2) Vee must be applied before VPP, and be removed simultaneously or after VPP.

, DS11001F-2

3-18

27C256
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:

READ OPERATION
AC Characteristics

Parameter

VIH= 2.4V and VIL= O.45V; VOH = 2.0V VoL =0.8V
1 TTL Load + 100pF
10nsec
Commercial: Tamb = O· Cto 70· C
Tamb = -40· C to 85· C
Industrial:
Automotive: Tamb = -40· C to 125· C

Sym 27C256-12 27C256-15 27C256-17 27C256-20 27C256-25 Units Conditions
Min Max

Address to Output Delay tAcc

Min

120

Max

Min

150

Max

Min

170

Max

Min

200

Max
250

CE = OE = VIL

CE to Output Delay

teE

120

150

170

200

250

OE =VIL

OE to Output Delay

toE

100

CE = V1L

CE or OE to OIP High
Impedance

toFF

Output Hold fro~
Address CE or OE,
whichever goes first

toH

READ WAVEFORMS

VIH

Address
VIL
VIH

~ ...,...

CE
VIL

Address Valid

....".

-teE(2)VIH
VIL
Outputs
00-07

VOH

HighZ

toE(2)

- -

j////

\\\\\

VOL

k?f-

.... toFF(1,3)
toH

Valid Output

f--

\\\1\
/I/IV

High Z

tAcc
Notes: (1) toFF is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to teE - toE after the falling edge of CE without impact on teE
(3) This parameter is sampled and is not 100% tested.

3-19

DS11001F-3

27C256
Ambient Temperature: Tamb = 25' C ±5' C
Vee = 6.5V ± 0.25V, Vpp = 13.0V ± 0.25V

PROGRAMMING
DC Characteristics
Parameter
Input Voltages

Status

Symbol

Min

Max

Units

Logic "1"
Logic "0"

VIH
VIL

2.0
-0.1

Vee+1
0.8

V
V

III

-10

I1A

VOH
VOL

2.4
0.45

V
V

Input Leakage
Output Voltages

Logic "1"
Logic "0"

Conditions

VIN = OV to Vee
IOH=-400~

IOL= 2.1mA

Vee Current, program & verify

lee2

Note 1

Vpp Current, program

IpP2

Note 1

12.5

A9 Product Identification

11.5

Note: (1) Vee must be applied simultaneously or before VPP and removed simultaneously or after VPP

PROGRAMMING
AC Characteristics
for Program, Program Verify
and Program Inhibit Modes

Parameter

AC Testing Waveform: VIH = 2.4 V and VIL = 0.45 V; VOH = 2.0 V; VOL = 0.8 V
Output Load:
1 TTL Load + 100 pF
Ambient Temperature: Tamb = 25' C ±5' C
Vee = 6.5V ± 0.25V, VPP = 13.0V ± 0.25V

Symbol

Min

Address Set-Up Time

lAs

I1 s

Data Set-Up Time

tos

I1 s

Data Hold Time

toH

I1 S

Address Hold Time

lAH

I1 s

Float Delay (2)

tOF

Vee Set-Up Time

tves

Program Pulse Width (1)

lPw

CE Set-Up Time

teES

I1 s

OE Set-Up Time

tOES

I1 s

VPP Set-Up Time

tvps

I1 s

Data Valid from OE
Notes:

tOE

Max

130

Units

Remarks

I1 s
105

100

I1 s

100l1s typical

(1) For express algorithm, initial programming width tolerance is 1OOl1sec ±5%.
(2) This parameter is only sampled and not 100% tested. Output float is defined as the point where data
is no longer driven (see timing diagram).

D811001 F-4

3-20

27C256
PROGRAMMING
Waveforms
1 4 - - - - - - Program - - - - - + - 0 > - - - - - Verify ----~

VIH
Address

Address Stable
VIL
VIH

HighZ

Data
VIL
toH
13.0V(2)
VPp
5.0V

Vcc
5.0V
VIH
CE
VIL
toE
(1 )

VIH
OE
VIL

Notes:

(1 ) toF and toE are characteristics of the device but must be accommodated by the programmer
(2) vcc = 6.5 V ±0.25 V, Vpp = VH = 13.0 V ±0.25 V for express algorithm

Read Mode

MODES
Operation Mode CE OE

VPp

00-07

Read
Program
Program Verify
Program Inhibit
Standby
Output Disable
Identity

Vcc
VH
VH
VH
Vcc
Vcc
Vcc

X
X
X
X
X
X
VH

DoUT

VIL
VIL
VIH
VIH
VIH
VIL
VIL

VIL
VIH
VIL
VIH
X
VIH
VIL

(See Timing Diagrams and AC Characteristics)
Read Mode is accessed when

DIN
DoUT

a) the CE pin is low to power up (enable) the chip

HighZ
HighZ
HighZ
Identity Code

b) the OE pin is low to gate the data to the output
pins.
For Read operations, if the addresses are stable, the
address access time (tACC) is equal to the delay from CE
to output (tCE). Data is transferred to the output aiter a
delay from the falling edge of OE (tOE).

x = Don't Care

DS11001F~5

3-21

27C256
Standby Mode

The standby mode is defined when the CE pin is high
(VIH) and a program mode is not defined.
When these condition are met, the supply current will
drop from 20mA to 1001lA.

After the array has been programmed it must be verified
to ensure all the bits have been correctly programmed.
This mode is entered when all the following conditions
are mel:
a)
b)
c)
d)

Output Enable

Vcc is at the proper level,
Vpp is at the proper VH level,
The CE pin is high and
the OE line is low.

Windowed products offer the ability to erase the memory
array. The memory matrix is erased to the all 1's state
as a result of being exposed to ultraviolet light. To
ensure complete erasure, a dose of 15 watt-second/cm2
is required. This means that the device window must be
placed within one inch and directly underneath an ultraviolet lamp with a wavelength of 2537 Angstroms, intensityof 12,000f,lW/cm2 for approximately 20 minutes.
Programming Mode

vcc is brought to proper voltage,
Vpp is brought to proper VH level,
The OE pin is high and
the CE pin is low.

When programming multiple devices in parallel with
different data, only CE need be under separate control
to each device. By pulsing the CE line low on a particular
device, that device will be programmed; all other devices
with CE held high will not be programmed with the data,
although address and data will be available on their input
pins.

Identity Mode

Pln-

Input

Output

Identity

0 0 0
7 6 5

Manufacturer
Device Type'

VIL
VIH

0 0 1 0 1 0 0
1 0 0 0 1 1 0

0 0 0 0
4 3 2 1 0

H
e
x

1 29
0 BC

• Code subject to change.

Since the erased state is "1" in the array, programming
of "0" is required. The address to be programmed is set
via pins AO-A14 and the data to be programmed is
presented to pins 00-07. When data and address are
stable, a low-going pulse on the CE line progrartls that
location.

DS11001F-6

3-22

27C256
PROGRAMMING - FIGURE 1
EXPRESS ALGORITHM
Conditions:

Tamb = 2So C ±So C
Vee = 6.S ±O.2SV
Vpp = 13.0 ±O.2SV
ADDR = First Location
Vee = 6.SV
Vpp= 13.0V

DS11001F·7

3-23
-----_.

--~~~-~------

27C256
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.

PART NUMBERS

J
K
L
P
SO

Temperature
Range:

l.....-----I Access Time:

' - - - - - - - - - - 1 Device:

DS11001F-8

12
15
17
20
25

27C256

3-24

CERDIP
Ceramic Leadless Chip Carrier
Plastic Leaded Chip Carrier
Plastic DIP
Plastic SOIC

0' C 1070' C
-40' C to 85' C
-40' C to 125' C

120 nsec
150 nsec
170 nsec
200 nsec
250 nsec

256K (32K

x 8) CMOS EPROM

27C512

Microchip

SI2K (64K X 8) CMOS EPROM
DESCRIPTION

FEATURES

The Microchip Technology Inc 27C512 is a CMOS 512K
bit (electrically) Programmable Read Only Memory. The
device is organized into 64K words by 8 bits (64K bytes) .
Accessing individual bytes from an address transition or
from power-up (chip enable pin going low) is accomplished in less than 120ns. This very high speed device
allows the most sophisticated microprocessors to run at
full speed without the need for WAIT states. CMOS
design and processing enables this part to be used in
systems where reduced power consumption and reliability are requirements.

High speed performance
-120ns access time available
• CMOS Technology for low power consumption
-35mA Active current
-1 OO~A Standby current
• Factory programming available
Auto-insertion-compatible plastic packages
Auto IDTM aids automated programming
High speed "express" programming algorithm
Organized 64K x 8: JEDEC standard pinouts
-28-pin Dual-in-line package
-32-pin Chip carrier (Ieadless or plastic)
-28-pin SOIC package
-Tape and reel
Available for extended temperature ranges:
-Commercial: 0' C to 70' C
-Industrial: -40' C to 85' C
-Automotive: -40' C to 125' C
-Military" (8): -55' C to 125' C

A complete family of packages is offered to provide the
most flexability in applications. For surface mount
applications, PLCC or SOIC packaging is available.
Tape or reel packaging is also available for PLCC or
SOIC packages. U.V. erasable versions are also
available.

PIN CONFIGURATIONS
Top View
A15

A15
A12
A7
A6
A5
A4
A3
A2
Al
AO
00
01
02

AS
A9
All

07
06
05
04
03

DIP

PLCC/LCC

Vee

A14
A13
AS
A9
All

OENpp
Al0

BE
07
06
05
04
03

SOIC

'-See 27C512 Military Data Sheet DS60014
© 1990 Microchip Technology Inc.

3-25

DS11006F-1

27C512
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE
Name

AO·A15
CE
OENpp
00-07
Vcc
Vss
NC
NU

Maximum Ratings'

Function

vcc and input voltages w.r.t. Vss .......... ·0.6V to +7.25V
Vpp voltage W.r.t. vSS during
programming ..................................... ·0.6V to +14.0V
Voltage on A9 w.r.t. Vss ............................ ·0.6V to +13.5V
Output voltage w.r.t. Vss .................. ·0.6V to Vcc + 1.0V
Storage temperature .......................... -65· C to 150· C
Ambienttemp. with power applied ..... -65· C to 125· C

Address Inputs
Chip Enable
Output Enable!
Programming Voltage
Data Output
+5V Power Supply
Ground
No Connection; No Internal
Connection
Not Used; No External
Connection Is Allowed

'Notice: Stresses above those listed under"Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at those or any
other conditions above those indicated in the operation listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

vcc = +5V ±1 0%
Commercial: Tamb= O· Cto 70· C
Tamb= -40· C to 85· C
Industrial:
Automotive: Tamb= -40· C to 125· C

READ OPERATION
DC Characteristics

Part'

Status

Symbol

Min

Max

Input Voltages

all

Logic "1"
Logic "0"

Input Leakage

all

VIH
VIL
III

2.0
-0.5
-10

Vcc+1
0.8
10

Output Voltages

all

2.4

Parameter

Logic "1"
Logic "0"

Units Conditions

V
V
I-lA

Output Leakage

all

VOH
VOL
ILO

Input Capacitance

all

CIN

Output Capacitance

all

GoUT

Power Suppy Current,
Active

S
X

Icc
Icc

35
45

mA
mA

Power Supply Current,
Standby

S
X
S

2
3
100

mA
mA
I-lA

TTL input
TTL input

-10

Icc(s)TTL
TTL input
ICC(S)TTL
TTL input
CMOS input ICC(S)CMOS

V
V

0.45
10

I-lA

VIN= 0 to Vcc
IOH = -4001-lA
IOL=2.1mA
VOUT = OV to Vcc
VIN = OV; Tamb = 25· C;
f = 1MHz
VOUT= OV;Tamb= 25· C;
f-1MHz
Vcc= 5.5V
f= lMHz;
OE/vpp= CE = VIL;
lout = OmA;
VIL= -0.1 to 0.8 V;
VIH= 2.0 to Vcc;

CE = Vce ±0.2V

• Parts:
S = Standard Power; X = Extended Temp. Range;
Notes: (1) AC Power component above 1Mhlz: 2mAlMHz.

DS11006F-2

3-26

27C512
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:

READ OPERATION
AC Characteristics

VIH= 2.4V and VIL= 0.45V; VOH= 2.0 V and VOL = 0.8V
1 TTL Load + 100pF
10nsec
Commercial: Tamb = O· Cto 70· C
Tamb = -40· C to 85· C
Industrial:
Automotive: Tamb = -40· C to 125· C

Sym 27C512·12* 27C512·15 27C512·17 27C512·20 27C512·25 Units Conditions

Parameter

Min

Max

Min Max

Min Max Min Max

Min Max

Address to Output
Delay

fAcc

120

150

170

200

250

CE = OE/Vpp = VIL

CEto Output Delay

ICE

120

150

170

200

250

OENpp= VIL

OE to Output Delay toE

100

CE = VIL

OE to Output High
Impedance

toFF

Output Hold from
Address, CE or
OENpp, whichever
occured first

toH

*27C512-12 is on Iv available in commercial temperature ranae

READ WAVEFORMS

VIH
VIL
VIH
VIL

-ICE(2)

VIH

OE/Vpp
VIL
VOH

Address Valid

~ .....

Outputs
00-07

Address

- - toE(2) ....

IIIIIIIIII
\\\\\\\\\\

HighZ

VOL

...,

F-

k?'

toFF(1.3) I-toH
'--

Valid Output

\\\\ 1\

High Z

III/II

fAcC

Notes: (1) toFF is specified for OE/Vpp or CE, whichever occurs first
(2) OE may be delayed up to tCE - toE after the falling edge of CE without impact on tCE
(3) This parameter is sampled and is not 100% tested.

3-27

DS11006F-3

27C512
Ambient Temperature: 25° C ±So C
Vee = 6.5V ± 0.25V, OENpp = VH = 13.0V ± 0;25V

PROGRAMMING
DC Characteristics
Parameter
Input Voltages

Status

Symbol

Min

Max

Units

Logic "1"
Logic "0"

VIH

2.0

Vee+1

VIL

-0.1

0.8

ilL

-10

IlA

Logic "1"

VOH

2.4

Logic "0"

VOL

Input Current (all inputs)
Output Voltages

VIN = OV to Vee

IoH = -4001lA

0.45

IoL = 2.1mA

Vee Current, program & verify

lce2

OE/Vpp Current, program

IpP2

A9 Product Identification

VID

12.5

11.5

Conditions (See Note 1)

CE = VIL

Note: (1) Vee must be applied simultaneously or before the Vpp voltage on OENpp and removed simultaneously
or after the Vpp voltage on OE/Vpp.

PROGRAMMING
AC Characteristics
for Program, Program Verify
and Program Inhibit Modes

AC Testing Waveform: VIH= 2.4V and VIL= 0.45V; VOH= 2.0V; VOL = 0.8V
Output Load:
1 TTL Load + 100pF
Ambient Temperatur~ 25° C ±5° C
Vee = 6.5V ± 0.25V, OE/vpp = VH = 13.0V ± 0.25V

Parameter

Symbol

Min

Address Set-Up Time

tAs

115

Data Set-Up Time

IDs

IlS

Data Hold Time

tDH

Ils

Address Hold Time

tAH

Ils

Float Delay (2)

IDF

Vee Set-Up Time

tves

Program Pulse Width (1)

IPw

CE Set-Up Time

teES

Ils

OE Set-Up Time

toES

IlS

OE Hold Time

toEH

115

toR

Ils

IPRT

OE Recovery Time

OE/Vpp Rise Time During Programming
Notes:

Max

130

Units Remarks

115
105

1OOIlS typical

Ils

(1) For express algorithm, initial programming width tolerance is 1OOll5ec ± 5%.
(2) This parameter is only sampled and not 100% tested. Output float is defined as the point where data
is no longer driven (see timing diagram).

DSlio06F-4

3-28

27C512
PROGRAMMING
Waveforms
1 0 4 - - - - - - Program------t4---- Verify ----~

Address

Data

Vpp
5.0V

Vcc
5.0V
VIH
CE
VIL
toE
(1)

VIH
OE
VIL

Notes:

(1) IDF and toE are characteristics of the device but must be accommodated by the programmer
(2) Vcc = 6.5 V ±O.25 V, Vpp = VH = 13.0 V ±O.25 V for express algorithm

Read Mode

MODES
Operation Mode

OENpp

00-07

Read
Program
Program Verify
Program Inhibit
Standby
Output Disable
Identity

VIL
VIL
VIL
VIH
VIH
VIL
VIL

VIL
VH
VIL
VH
X
VIH
VIL

X
X
X
X
X
X
VH

DoUT

(See Timing Diagrams and AC Characteristics)
Read Mode is accessed when

DIN
DoUT

a) the CE pin is low to power up (enable) the chip

HighZ
HighZ
HighZ
Identity Code

b) the OENpP pin is low to gate the data to the
output pins.

X.Don1Care
For Read operations, if the addresses are stable, the
address access time (tACC) is equal to the delay from CE
to output (tCE). Data is transferred to the output after a
delay (tOE) from the falling edge of OEIVpp.

DS11006F-5

3-29

27C512
Standby Mode
The standby mode is defined when the CE pin is high
and a program mode is not identified.
When this condition is met, the supply current will drop
from 35mA to 100IlA.

Output Enable OElVpp
This multifunction pin eliminates bus connection in multiple bus microprcessor systems and the outputs go to
high impedance when:

Since the erased state is "1" in the array, programming
of "0" is required. The address to be programmed is set
via pins AO - A 15 and the data to be programmed is
presented to pins 00 - 07. When data and address are
stable, a low going pulse on the CE line programs that
location.

After the array has been programmed it must be verified
to ensure all the bits have been correctly programmed.
This mode is entered when all the following conditions
are met:
a) Vee~atlhe proper level,
b) the OElVpp pin is low, and
c) the CE line is low.

• the OElVpp pin is high (VIH).
When a VH input is applied to this pin, it supplies the
programming voltage (Vpp) to the device.

Erase Mode IU.V. Windowed Versions)
Windowed products offer the ability to erase the memory
array. The memory matrix is erased to the all "1 "'s state
as a result of being exposed to ultraviolet light. To
ensure complete erasure, a dose of 15 watt-second/cm 2
is required. This means that the device window must be
placed within one inch and directly underneath an ultraviolet lamp with a wavelength of 2537 Angstroms, intensity of 12,000IlW/cm 2 for approximately 20 minutes.

Programming Mode
The express algorithm has been developed to improve
on the programming throughput times in a production
environment. Up to 10 100-microsecond pulses are
applied until the byte is verified. No overprogramming is
required. A flowchart of the express algorithm is shown
in Figure 1.

When programming multiple devices in parallel with
different data, only CE needs to be under separate
control to each device. By pulsing the CE line low on a
particular device, that device will be programmed; all
other devices with CE held high will not be programmed
with the data (although address and data will be available on their input pins).
Identity Mode
In this mode specific data is output which identifies the
manufacturer as Microchip Technology Inc and the
device type. This mode is entered when Pin A9 is taken
to VH (11.5V to 12.5V). The CE and OE/Vpp lines must
be at VIL. AO is used to access any of the two nonerasable bytes whose data appears on 00 through 07.

PinIdentity

Programming takes place when:
a) Vec is brought to the proper voltage,
b) OElVpp is brought to the proper VH level, and
c) CE line is low.

DS11006F-6

Manufacturer
Device Type'

Input
AO

VIL
VIH

Output
00 0
7 6 5

1
0

0
0

0 0
0 0

4 3

0
2

0 0
1 0

1
1

0
1

0
0

H
e
x

1 29
1 00

• Code subject to change.

3-30

27C512
PROGRAMMING - FIGURE 1
EXPRESS ALGORITHM
Conditions:
Tamb = 2S" C ±S" C
Vee = 6.S ±O.2SV
OENpp = 13.0 ±O.2SV
ADDR = First Location
Vee=6.SV
OENpp = 13.0V

Vee = 4.SV,S.SV

3-31

DS11006F-7

27C512
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.

PART NUMBERS
~~-251/P

~-~

J
K
L
P
SO

I Temperature
Range:

'------I

Access Time:

Device:

DS11006F-8

12
15
17
20
25

27C51.2

3-32

Cerdip
Ceramic Leadless Chip Carrier
Plastic Leaded Chip Carrier
Plastic DIP
Plastic SOIC

O' C to 70' C
·40' C to 85' C
-40' C to 125" C

120 nsec
150 nsec
170 nsec
200 nsec
250 nsec
512K (64K x 8) CMOS EPROM

27HC64

Microchip

64K (8K X 8) High Speed CMOS UV Erasable PROM
FEATURES

DESCRIPTION

• Bipolar Performance
- 40ns Maximum Access Time
• CMOS Technology For Low Power Consumption
- 80mA Active Current
-lOOl1A Standby Current (Low Power Option)
• OTP (One Time Programming) Available
• Auto·lnsertion-Compatible Plastic Packages
• Auto 10TM Aids Automated Programming
• Separate Chip Enable and Output Enable Controls
• Two Programming Algorithms Allow Improved
Programming Times
- Fast Programming
-Express
• Organized 8K x 8: JEOEC Standard Pinouts
- 28 Pin Dual in Line Package
- 32 Pin Chip Carrier (Leadless or Plastic)
• Available for Extended Temperature Ranges:
- Commercial: 0" C to 70" C
-Industrial: -40' C to 85" C
- Military": -55" C to 125" C

The Microchip Technology Inc 27HC64 is a CMOS 64K
bit ultraviolet light Erasable (electrically) Programmable
Read Only Memory. The device is organized as 8K
words by 8 bits (8K bytes). An advanced CMOS design
allows bipolar speed with a significant reduction in
power over bipolar PROMs. A low power option (L)
allows further standby power reduction to 100llA. The
27HC64 is configured in a standard 64K EPROM
pinout, which allows an easy upgrade for 27C64 sockets. This very high speed device allows digital signal
processors (DSP) or other sophisticated microprocessors to run atfull speed withoutthe need forWAITstates.
CMOS design and processing enables this part to be
used in systems where reduced power consumption and
reliability are requirements.
A complete family of packages is offered to provide the
most flexibility in applications. One Time Programming
(OTP) is available for low cost (plastic) applications.

BLOCK DIAGRAM

PIN CONFIGURATION

00······· 07

Top View
Vpp
A12

Vee
PGM

NC
A6
A5
M

A9
All

AS
A2
AI

i5E

07
06

01
02
Vss

Al0

04
03

CE
OE

~~~~~I~~
'..,.,lcn,'(\J,' .....

"~".,....,I~,

PGM

A6 fjL.!LJLJ~!LJl~JLJ:~ AS

A4
A3

A2 ~:j

jjiJ
AO 1jj
NC jjj
A1

ooJru

Vpp

[gj A9

0
f;:lf§1f§1fi-.:lf§lr~ [fii

:?I

Voo

All

[~ NC
~
:.?~ Al0

Vee

:i§

AO
I
I
I
I
I
I
I
I

fgj CE

fig
iii

Chip Enablel
Output Enable
Control Logic

oS~~BaCS

Decoder

64Kbit
Cell Matrix

.Pln 1 Indicator on PLCC on top of package

A12

.. See 27HC64 Military Data sheet OS60006

3-33

DS11105E-1
~,~~-~~~~-~ ~-~------~--~~~~~

27HC64
ELECTRICAL CHARACTERISTICS
Maximum Ratings·

PIN FUNCTION TABLE
Name

Function

AO-A12
CE
OE
PGM
Vpp
00-07
Vee
Vss
NC

Address Inputs
Chip Enable
Output Enable
Program Enable
Programming Voltage
Data Output
+5V Power Supply
Ground
No Connection; No
Internal Connection
Not Used; No External
Connection Is
Allowed

Vee and input voltages w.r.t. Vss ... -0.6V to + 7.2SV
Vpp voltage w.r.t. Vss during
programming ............................... -0.6V to + 14V
Voltage on A9 w.r.t. Vss ..................... -0.6V to +13.5V
Output voltage w.r.t. Vss .................... -0.6V to Vee +1.0V
Storage temperature ..................... -65' C to lS0' C
Ambient temp. with power applied -6S' C to 125' C
ESD protection on all pins ............. 2KV
'Notice: Stresses above those listed under"Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at those or any
other conditions above those indicated in the operation listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

Vee = +SV ±10%
Commercial: Tamb= 0' Ct070' C
Industrial:
Tamb= -40' C to 85' C

READ OPERATION
DC Characteristics

Parameter

Part"

Status

Symbol

Min

Max

Units Conditions

Input Voltages

all

Logic "1"
Logic "0"

Input Leakage

all

VIH
VIL
III

2.0
-0.1
-10

Vee+l
0.8
10

V
V
IlA

Output Voltages

all

2.4

Leakage

all

VOH
VOL
ILO

Input Capacitance

all

CIN

Output Capacitance

all

GoUT

Power Suppy Current,
Active

S,L
SX,LX

leel
lee2

80
90

rnA
rnA

Power Supply Current,
Standby
Power Supply Current,
Standby

S
SX
L
LX
L,LX
all
all

lee(S)l

40
SO
2
3
100
100
Vee

rnA
rnA
rnA
rnA

Ipp Read Current
Vpp Read Voltage

Logic "1"
Logic "0"

TTL input
TTL input

TTL input
TTL input
CMOS input
Read Mode
Read Mode

-10

lee(S)2

Ipp
Vpp

Vee0.7

V
V

0.45
10

I!A

I!A
I!A
V

VIN= 0 to Vee
IoH=-4mA
IOL= 16mA
VOUT= OV to Vee
VIN = OV; Tamb = 2S' C;
1= lMHz
VOUT= OV;Tamb= 2S' C;
1-1MHz
Vee = S.SV; Vpp = Vee
1=2MHz;
OE = CE = VIL;
lout = OmA;
VIL= -0.1 to 0.8 V;
VIH= 2,0 to Vee;
Note 1

CE = Vee ±0.2V
Vpp = S.SV
Note 2

• Parts:
S = Standard Power; L = Low Power; X = Industrial Temp Range;
Notes: (1) AC Power component above 2 MHz: 3rnAlMHz lor standard part; S mAIM Hz lor
industrial temperature range part.
(2) Vee must be applied belore (or simultaneously with Vpp), and be removed after (or
simultaneously with) VPP.

DSll105E-2

3-34

27HC64
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:

READ OPERATION
AC Characteristics

Part- Sym 27HC64·40

Parameter

Min

Max

VIH= 3.0V and Vll= O.OV; VOH = VOL = 1.5V
1 TTL Load + 30 pF
5 nsec
Commercial: Tamb = 0' Cto 70' C
Tamb = -40' C to 85' C
Industrial:

27HC64·45 27HC64-55 27HC64-70 Units Conditions
Min

Max

Min

Max

Min

Max

Address to Output Delay

all

tACC

CE to Output Delay

L
S

tCE1
tcE2

40
30

45
30

55
35

70
45

OE = Vil

OE to Output Delay

all

toE

CE = Vil

CE or OE to OIP High
Impedance

all

toFF

Output Hold from
Address CE or OE, whichever goes first

all

toH

CE =OE = Vil

• Parts: S = Standard Power; L = Low Power
•• 27HC64-40 is only available in commercial temperature range

READ WAVEFORMS

VIH

Address
Vil
VIH

CE
Vil

Outputs
00-07

"""""

~ ..,...

Vil
VOH

....,..

X
k?

-tCE(2)-

VIH
OE

Address valid

i<:=

HighZ

toE(2)

IIII

\\\\

VOL

I--

kZ"f-

-- toFF(1,3)
tOH

Valid Output

I--

\\\1\

High Z

IIJV

tAcc

3-35

DS11105E-3

27HC64
PROGRAMMING
DC Characteristics

Ambient Temperature: Tamb = 25' C ±5' C
For vPp and Vee Voltages refer to Programming Algorithms

Parameter

Status

Symbol

Min

Max

Units

Input Voltages

Logic "1"
Logic "0"

VIH
VIL

2.0
-0.1

Vee+1
0.8

V
V

III

-10

IlA

VIN = OV to Vee

VOH
VOL

2.4
0.45

V
V

IOH=-4mA
IOL= 16mA

Input Leakage
Output Voltages

Logic "1"
Logic "0"

Conditions

Vec Current, program & verify

Icc

Note 1

Vpp Current,program

Ipp

Note 1

A9 Product Identification

12.5

11.5

Note: (1) Vee must be applied simultaneously or before VPP and removed simultaneously or after Vpp

PROGRAMMING
AC Characteristics
for Program, Program Verify
and Program Inhibit Modes

AC Testing Waveform: VIH= 2.4 V and VIL= 0.45 V; VOH = 2.0 V; VOL = 0.8 V
Output Load:
1 TIL Load + 100 pF
Ambient Temperature: Tamb = 25' C ±5' C
For VPP and Vee Voltages, refer to Programming Algorithms

Parameter

Symbol

Min

Address Set-Up Time

lAs

Ils

Data Set-Up Time

tDS

Ils

Data Hold Time

tDH

Ils

Address Hold Time

IAH

Ils

Float Delay (3)

tDF

Vee Set-Up Time

tves

Program Pulse Width (1)

tpw

0.95

1.05

1 ms typical

Program Pulse Width (1)

IPw

105

Ils

100 Ils typical

CE Set-Up Time

teES

IlS

OE Set-Up Time

toES

Ils

Vpp Set-Up Time

tvps

Ils

Overprogram Pulse Width (2)

topw

2.85

Data Valid from OE

toE

Max

130

Units

Remarks

ns
IlS

78.75

100

Notes: (1) For Express algorithm, initial programming width tolerance is 100 Ilsec ±5%. For
fast programming algorithm, initial program pulse width tolerance is 1 msec ± 5%.
(2) For fast programming algorithm, the length of the overprogram pulse may vary
from 2.85 to 78.75 msec as a function of the iteration counter value.
(3) This parameter is only sampled and not 100% tested. Output float is defined as
the point where data is no longer driven (see timing diagram).

DS11105E·4

3-36

27HC64
PROGRAMMING
Waveforms
1 4 - - - - - Program

----_*"o-----Verify-------l~

VIH
Address Stable

Address
VIL
VIH

HighZ

Data
VIL

VPp
5.0V

VCC
5.0V
VIH
CE
VIL
VIH
PGM
VIL
tOE

VIH

(1)

OE
VIL

(1 ) tDF and toE are characteristics of the device but must be accommodated by the programmer
(2) Vcc = 6.0 V ±0.25 V, \pp = VI-i = 12.5 V ±O.25 V for fast programming algorithm
Vcc = 6.5 V ±0.25 V, \oPp = VI-i = 13.0V ±0.25 V for Express algorithm

Notes:

MODES

Read Mode

Operation Mode CE

PGM

VPp

A9 00-07

Read
Program
Program Verify
Program Inhibit
Standby
Output Disable
Identity

VIL
VIH
VIL
X
X
VIH
VIL

VIH
VIL
VIH
X
X
VIH
VIH

Vee
VH
VH
VH
Vee
Vee
Vee

X
X
X
X
X
X
VH

VIL
VIL
VIL
VIH
VIH
VIL
VIL

(See Timing Diagrams and AC Characteristics)
Read Mode is accessed when

DoUT

DIN
DoUT

a) the CE pin is low to power up (enable) the chip

HighZ
HighZ
HighZ
Identity Code

b) the OE pin is low to gate the data to the output
pins.

x = Don't Care
For Read operations on the low powered version, if the
addresses are stable, the address access time (tACC) is
equal to the delay from CE to output (tCE). A faster CE
access time (tCE) is available on the standard part to
provide the additional time for decoding olthe CE signal.
Data is transferred to the output after a delay from the
falling edge of OE (tOE).
© 1990 Microchip Technology Inc.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____ •
~

~'_.~'_M~_'_'~_

3-37

DS11105E-5

27HC64
Standby Mode
The standby mode is defined when the CE pin is high
(VIH).
When this condition is met, the supply current will drop
from BOmA to 1OOIlA on the low power part and to 40mA
on the standard part.

Output Enable
This feature eliminates bus contention in multiple bus
microprocessor systems and the outputs go to a high
impedance when

After the array has been programmed it must be verified
to ensure all the bits have been correctly programmed.
This mode is entered when all the following conditions
are met:

The OE pin is high and a program is not defined.

a)
b)
c)
d)
e)

Erase Mode
Windowed products offer the ability to erase the memory
array. The memory matrix is erased to the aliI's state
as a result of being exposed to ultraviolet light. To
ensure complete erasure, adose of 15 watt-second/cm 2
is required. This means that the device window must be
placed within one inch and directly underneath an ultraviolet lamp with a wavelength of 2537 Angstroms, intensity of 12,000f.!W/cm2 for 20 minutes.

Programming Mode
Two programming algorithms are available. The fast
programming algorithm is the industry-standard programming mode that requires both initial programming
pulses and overprogramming pulses. A flowchart of the
fast programming algorithm is shown in Figure 1.

Vcc is at the proper level,
Vpp is at the proper VH level,
the CE line is low,
the PGM line is high, and
the OE line is low.

When programming multiple devices in paralit:i with
different data, only CE need be under separate control
to each device. By pulsing the CE line low on a particular
device in conjunction with the PGM line low, that device
will be programmed; all other devices with CE held high
will not be programmed with the data, although address
and data will be available on their input pins (i.e., when
a high level is present on CE or PGM); and the device is
inhibited from programming.

Identity Mode
The Express algorithm has been developed to improve
on the programming throughput times in a production
environment. Up to 10 100-microsecond pulses are
applied until the byte is verified. No overprogramming is
required. A flowchart of the Express algorithm is shown
in Figure 2.

In this mode specific data is outputted which identifies
the manufacturer as Microchip Technology Inc., and
device type. This mode is entered when Pin A9 is taken
to VH (11.5V to 12.5V). The CE and OE lines must be
at VIL. AO is used to access any of the two non-erasable
bytes whose data appears on 00 through 07.

Programming takes place when:
a)
b)
c)
d)
e)

Vcc is brought to proper voltage,
Vpp is brought to proper VH level,
the CE pin is low,
the OE pin is high, and
the PGM pin is low.

PinIdentity

Manufacturer
Device Type"

Input
AO

Vil
VIH

Output

0 00 0 0
7 6 5 4 3

0
2

0
1

0
0

0
1

0
0

1 29
1 91

0 1
0 0

0
1

1
0

e
x

• Code subject to change.

DSll105E-6

3-38

27HC64
PROGRAMMING· FIGURE 1
EXPRESS ALGORITHM
Conditions:
Tamb = 25' C ±5" C
Vee = 6.5 ±O.25 V

Vpp = 13.0 ±0.25 V

ADDR = First Location
Vee = 6.5 V
Vpp = 13.0 V

Yes

All

3-39

DS11105E-7

SALES AND SUPPORT
To orderior to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.

PART NUMBERS
27HC64 ·45 11K

Package:

J
K
L
P

I Temperature
Range:

Access Time:

Device:

DS11105E-8

Blank
I

Cerdip DIP
Ceramic Leadless Chip Carrier
Plastic Leaded Chip Carrier (OTP Available)
Plastic DIP (OTP Available)
0' C to 70' C
-40' C to 85' C

40
45
55
70

27HC64
27HC64L

nsec
nsec
nsec
nsec

64K (8K x 8) High Speed CMOS EPROM
64K (8K x 8) High Speed Low Power CMOS
EPROM

3·40

27HC256

Microchip

256K (32K X 8) High Speed CMOS EPROM
FEATURES

DESCRIPTION

High speed performance
-55ns access time available
CMOS technology for low power consumption
-55mA active current
-100IlA standby current (low power option)
OTP (one time programming) available
Auto-insertion-compatible plastic packages
Auto IDTM aids automated programming
Organized in 32K x 8 - JEDEC Standard Pinouts
-28-pin Dual-in-line and SOIC package
-32-pin Chip carrier (lead less or plastic)
Extended temperature ranges available:
-Commercial: 0" C to +70" C
-Industrial: -40" C to +85" C
-Automotive: -40" C to +125" C
-Military": -55" C to +125" C

The Microchip Technology Inc 27HC256 is a CMOS
256K bit (electrically) Programmable Read Only Memory.
The device is organized into 32K words of 8 bit each.
Advanced CMOS technology allows bipolar speed with
a significant reduction in power. A low power option (L)
allows further reduction in the standby power requirement
to 100IlA. The 27HC256 is configured in a standard
256K EPROM pinout which allows an easy upgrade for
present 27C256 users. A complete family of packages
are offered to provide the utmost flexibility. The 27HC256
allows high performance microprocessors to run at full
speed without the need of wait states. CMOS design
and processing makes this part suitable for applications
where reliability and reduced power consumption are
essential.

PIN CONFIGURATIONS
TOP VIEW
Vpp

Vpp

Vee
A14
A13

A12
A6
A5

AS
A9
A11

A10

07
06
05
04
03

CE
01
02
Vss

DIP

<~!~~~~
l~Jl~Jl:'Ji ~il~Jl~Jl~J

~~j
A4 EJ

'.'

A6
A5 j~j

ry}

A3 ~J
A2 jJ
A1 ]§J

JiJ
NC 3iJ
00 3iJ

L2~ A9
:28

A10
CE
07

L2_4 A10

fjj CE
:~l

:01 :~: :~l :~lf~: :~l

oS~~8oC3

PLCC/LCC

A11

L2_6 NC

:;_5 OE

Vee
A14
A13
AS
A9
A11

A12
A7
A6
A5

fJJ
f]3

07
06

A1
AD
00
01

06
05
04

02
Vss

SOIC

"See 27HC256 Military Data Sheet DS60009A

3-41

DS11124C-1

27HC256
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE

Maximum Ratings*

Name

Function

AO -A14
CE
OE
Vpp
00-07
Vcc
Vss
NC
NU

Address Inputs
Chip Enable
Output Enable
Programming Voltage
Data Output
+5V
Ground
No Connection; No Internal Connection
Not Used; No External Connection Is
Allowed

Vcc and input voltages w.r.t. Vss .......... -0.6V to +7.25V
Vpp voltage w.r.t. Vss during
programming .......................................... -0.6V to + 14V
Voltage on A9 w.r.t. Vss ............................ -0.6V to + 13.5V
Output voltage w.r.t. Vss .................... -0.6V to Vcc + 1.0V
Temperature under bias ..................... -65· C to 125· C
Storage temperature .......................... -65· C to 150· C
Maximum exposure to UV .................... 7258Wsec/cm'
ESO protection on all pins .................................. 2.0kV
"Notice: Stresses above those listed under "Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device allhose or any
other conditions above those indicated in the operation listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

Part'

Status

Symbol

Min

Max

Input Voltages

all

Logic "1"
Logic "0"

Input Leakage

all

VIH
VIL
III

2.0
-0.1
-10

Vcc+1
0.8
10

Output Voltages

all

2.4

Parameter

Output Leakage

all

VOH
VOL
ILO

Input Capacitance

all

CIN

Output Capacitance

all

GoUT

Power Suppy Current,
Active

S,L
X

IcC1
Icc2

55
65

Power Supply Current,
Standby
Power Supply Current,
Standby

S
SX
L
LX
L,LX
all
all

IcC(S)1

35
40
2
3
100
100
Vee

Ipp Read Current
VPp Read Voltage

Logic "1"
Logic "0"

TTL input
TTL input

TTL input
TTL input
CMOS input
Read Mode
Read Mode

-10

ICC(S)2

Ipp
Vpp

Tamb= O· C to 70· C
Tamb= -40· C to 85· C
Tamb= -40· C to 125· C

Commercial:
Industrial:
Automotive:

Vcc = +5V ±10%

READ OPERATION
DC Characteristics

Vee
-0.7

0.45
10

Units Conditions
V
V
IlA

VIN= -0.1Vto Vcc+1.0V

V
V

IOH= -4mA
IOL= 16mA
J.lA VouT=-0.1Vto
Vcc+0.1V
pF VIN= OV; Tamb = 25· C;
f = 1MHz
VOUT= OV;Tamb = 25·C;
pF
If = 1MH7
rnA Vcc = 5.5V; Vpp = Vcc
rnA f =2MHz;
OE =CE = VIL;
lout = OmA;
VIL= -0.1 to 0.8 V;
VIH= 2.0 to Vcc;
Note 1
rnA
rnA
rnA
rnA CE = Vee ±O.2V
IlA
IlA Vpp= 5.5V
Note 2
V

• Parts:
S = Standard Power; L = Low Power; X = Industrial and Automotive Temp. Ranges;
Notes: (1) AC Power component above 2 MHz: 3mAlMHz for standard part; 5 mAIM Hz for
extended temperature range part.
(2) Vce must be applied simultaneously or before VPP, and removed simultaneously or atler VPP.

DS11124C-2

3-42

27HC256
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:

READ OPERATION
AC Characteristics

VIH= 3.0V and VIL= O.OV; VOH = VOL = 1.5V
1 TTL Load + 30 pF
5 nsec
Commercial: Tamb= 0' Cto 70' C
Industrial:
Tamb= -40' C to 85' C
Automotive: Tamb= -40' C to 125' C

Part* Sym 27HC256·SS** 27HC2S6-70 27HC2S6·90

Parameter

Min

Max

Min

Max

Min

Units

Conditions

Max

Address to Output Delay

all

IACC

-CE = -OE = VIL

CE to Output Delay

L
S

teE1
teE2

55
45

70
45

90
50

OE=VIL

OE to Output Delay

all

toE

CE=ViL

OE to OIP High
Impedance

all

toFF

all

toH

Output Hold from
Address CE or OE, whichever goes first

• Parts: S = Standard Power; L = Low Power
•• 27HC256-55 is only available in commercial temperature range

READ WAVEFORMS

VIH
Address valid

Address
VIL
VIH
CE
VIL
VIH
OE
VIL
Outputs
00- 07

VOH

HighZ

Valid Output

VOL
IACC

3-43

DSll124C-3

27HC256
PROGRAMMING
DC Characteristics
Parameter
Input Voltages

Ambient Temperature: Tamb = 25° C ±5° C
Vee = 6.5V ± 0.25V, Vpp = 13.0V ± 0.25V

Status

Symbol

Min

Max

Units

Logic "1"
Logic "0"

VIH
VIL

2.0
-0.1

Vee+1
0.8

V
V

III

-10

/lA

VIN = OV to Vee

VOH
VOL

2.4
0.45

V
V

IOH= -4mA
IOl= 16mA

Input Leakage
Output Voltages

Logic "1"
Logic "0"

Vee Current,
program & verify

Icc

Vpp Current, program

Ipp

A9 Product Identification

12.5

11.5

Conditions

Note 1

Note: (1) Vee must be applied simultaneously or before Vpp and removed simultaneously or after VPP.

PROGRAMMING
AC Characteristics
for Program, Program Verify
and Program Inhibit Modes

Parameter

AC Testing Waveform: VIH= 2.4V and VIL= 0.45V; VOH = 2.0V; VOL = 0.8V
Output Load:
1 TIL Load + 100 pF
Ambient Temperature: Tamb = 25° C ±5° C
Vee = 6.5V ± 0.25V, VPP = 13.0V ± 0.25V

Symbol

Min

Address Set-Up Time

lAs

/ls

Data Set-Up Time

tDS

/ls

Data Hold Time

lDH

/lS

Address Hold Time

IAH

/ls

Float Delay (2)

tDF

Vee Set-Up Time

tves

Program Pulse Width (1)

tpw

OE Set-Up Time

toES

/ls

VPP Set-Up Time

tvps

/ls

Data Valid from OE

tOE

Max

130

Units

Remarks

ns
/ls

105

100

/ls

100 /ls typical

Notes: (1) For express algorithm, initial programming width tolerance is 100 /lsec ±5%.
(2) This parameter is only sampled and not 100% tested. Output float is defined as the point where data
is no longer driven (see timing diagram).

DS11124C-4

3-44

27HC256
PROGRAMMING

Waveforms
1 - - - - - - Program

-----.,...>-----

Verify - - - - . . ,

VIH
Address
VIL
VIH
Data
VIL

Vpp
5.0V

Vee
5.0V
VIH
CE
VIL

toE

VIH

(1 )

OE
VIL

Notes:

(1 ) tDF and tOE are characteristics of the device but must be accommodated by the programmer
(2) Vee = 6.5V ±0.25V, Vpp = VH = 13.0V ±0.25V for express algorithm

FUNCTIONAL DESCRIPTION

Vpp A9

VIL
VIL
VIH
VIH
VIH
VIL
VIL

VIL
VIH
VIL
VIH

Vee
VH
VH
VH
Vee
Vee
Vee

Operation Mode CE

The 27HC256 has the following functional modes:
Read
Program
Program Verify
Program Inhibit
Standby
Output Disable
Identity

-Operation: The 27HC256 can be activated for data
read, be put in standby mode to lower its power
consumption, or have the outputs disabled.
-Programming: To receive its permanent data, the
27HC256 must be programmed. Both a program and
program/verify procedure is available. It can be
programmed with Fast or Rapid Pulse algorithm.

X
VIH
VIL

X
X

X
X
VH

00-07
DoUT
DIN
DoUT
High Z
High Z
High Z
Identity Code

X = Don't Care

Theprogrammingequipmentcanautomaticallyrecognize
thedevicetype and manufacturer using the identity mode.

Operation
• Read
• Standby
• Output Disable
Forthe general characteristics in these operation modes,
refer to the table above.

3-45

DS11124C-5

27HC256
Read Mode

Inhibit Mode

For timing and AC characteristics refer to the tables
Read Waveforms and Read Operation AC Characteristics.

When Programmin!L!!!ultiple devices in parallel with
different data only CE needs to be under seperate
control to each device. By pulsing the CE line low on a
particular device, that device will be programmed, and
all other devices with CE held high will not be programmed with the data although address and data are
available on their input pins.

The 27HC256's memory data is accessed when
- the chip is enabled by setting the CE pin low.
- the data is gated to the output pins by setting the
OEpin low.
For Read operations on the Low Power version, once
the addresses are stable, the address access time
(tAcc) is equal to the delay from CE to output (teE). A
faster CE access time (tCE) is available on the standard
part to provide the additional time for decoding the CE
signal. Data is transferred to the output after a delay
(tOE) from the falling edge of OE.
Standby Mode
The standby mode is entered when the CE pin is high,
and a program mode is not defined. When these
conditions are met, the supply current will drop from
55mA to 1001lA on the low power part, and to 35mA on
the standard part.

Identity Mode
In this mode specific data is read from the device that
identifies ths manufacturer as Microchip Technology,
and the device type. This mode is entered whlill.Pin A9
is taken to VH (11.5V to 12.5V). The CE and OE pins
must be at VIL. AO is used to access any of the two nonerasable bytes whose data appears on 00 - 07.

Pin-

00 0
765

Manufacturer
Device Type

VIL
VIH

0 0 1 0 1 0 0 1 29
1 0 0 1 0 1 0 0 94

0 0 0 0
4 3 2 1 0

H
e
x

Identity

Oytput plsable
This feature eliminates bus contention in multiple bus
microprocessor systems. The outputs go to a high
impedance when the OE pin is high, and the program
mode is not defined.

Output

Input

Programming Algorithms
The express algorithm has been developed to improve
programming through-put times in a production environment. Up to 10 pulses of 1OOj.1Sec each are applied
until the byte is verified. No overprogramming is required. A flowchart of this algorithm is shown in Figure1.
The programming mode is entered when:
a) Vec is brought to the proper level
b) VPP.l!.brought to the proper VH level
c) the OE pin is high
d) the CE pin is low
Since the erase state is "1" in the array, programming of
·0" is required. The address of the memory location to
be programmed is set via pins AO - A14, and the data is
presented to pins 00 - 07. When data and address are
stable, a low going pulse on the CE line programs that
memory location.

Windowed products offer the ability to erase the memory
array. The memory matrix is erased to the all "1"s state
as a result of being exposed to ultra-violet light at
wavelenghts s 4000 Angstroms (A). The recommended
procedure is to expose the erasure window of device to
a commercial UV source emitting at 2537 A with an
intensity of 12,00011W/cm2at 1". Theerasuretimeatthat
distance is about 15 to 20 min.
Note: Fluorescent lights and sunlight emit rays at the
specified wavelengths. The erasure time is about 3
years or 1 week resp. in these cases. To prevent loss of
data, an opaque label should be placed over the erasure
window.

After the array has been programmed, it must be verified
to make sure that all the bits have been correctly
programmed. This mode is entered when all of the
following conditions are met:
a) Vec is at the proper level
b) VPP is at the proper VH level
c) the CE pin is high
d) the DE line is low

DS11124C-6

3-46

27HC256
PROGRAMMING - Figure 1
Express Algorithm
Conditions:
Tamb = 25+/-5C
Vee = 6.5+/-0.25V
VPp = 13.0+/-0.25V
ADDR = First Location
Vee = 6.5V
VPp= 13.0V

3-47

DSll124C-7

27HC256
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing, or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.

PART NUMBERS
27HC256 L - 55 II SO

Package:

L
P
SO

Temperature
Range:

J
K

Access Time:

Blank
I
E

55
70
90

Power Type:

'----------11

DS11124C-8

Device:

27HC256

3-48

Cerdip DIP
Ceramic Leadless Chip Carrier
PLCC
Plastic DIP
Plastic SOIC

O' Cto +70' C
-40' C to +85' C
·40' C to + 125' C

55 nsec
70 nsec
90 nsec

Standard Power
Low Power

256K (32K x 8) High Speed EPROM

27HC1616

Microchip

256K (16K X 16) High Speed CMOS UV Erasable PROM
FEATURES

DESCRIPTION
The Microchip Technology Inc. 27HC1616 is a CMOS
256K bit (ultraviolet light) Erasable (electrically) Programmable Read Only Memory. The device is organized as 16K words of 16 bits each. Advanced CMOS
technology allows bipolar speed with a significant reduction in power. A low power option (L) allows further
standby power reduction to 1DOIlA. The 27HC 1616 is
configured in the JEDEC WordWide pinout which allows
a two for one package savings over Bytewide memories
along with a significant PC board savings. This very high
speed single chip solution is ideal for 16/32 bit digital
signal processors (DSP) or other sophisticated microprocessors. A complete family of packages is offered to
provide the utmost flexibility. One Time Programming
(OTP) is available for low cost (plastic) applications.

High speed performance
--45ns Maximum access time
CMOS Technology for low power consumption
-90mA Active current
-100IlA Standby current (low power option)
OTP (one time programming) available
WordWide architecture offers space saving over
By1ewide memories
Two programming algorithms allow improved
programming times
-Fast programming
-Express
Organized 16K x 16: JEDEC standard pinouts
--40-Pin dual in line package
--44-Pin chip carrier (lead less or plastic)
Extended temperature ranges available:
-Commercial: O' C to 70' C
-Industrial: _40' C to 85' C
-Military··: _55' C to 125' C

PIN CONFIGURATION

BLOCK DIAGRAM
00···············015

Top View

'-'

0"
0"
0"

3
4

40~~CC
PG"M
38~NC
37~NC

"0
AS

Vpp

BE
015

0"
09

os
V~

'032

"
0'
00 "
DEC "

T
27

03
02

23~~2
Al

OE
PGM

g6Bits g:g ~I~ g g g
6 5 4 3 2 14443424140
0127
3.
011 8
3B
0109
37
0910
36
0811
35
Vss 12
34
NC 13
33
07 14
32
0615
31
0516
30

0417
29
1819202122232425262728

Chip Enable!
Output Enable
Control Logic

vpp

Programming
Logic

vss

A13

Vee

An
A"
A,

AO
I
I
I
I
I
I
I
I

V"
NC

A8
A7
A'
A5

8So81~!i~< ~:2:=

21 ]AO

X
Decoder

256K bit
Cell Matrix

A13

•• See 27HC 1616 Military Data sheet DS60038
© 1990 Microchip Technology Inc.

3-49

08110108-1

27HC1616
ELECTRICAL CHARACTERISTICS

PIN FUNCTION TABLE

Maximum Ratings·

Name

Function

AO -A13
CE
OE
PGM
Vpp
00-01S
Vec
vss
NC

Address Inputs
Chip Enable
Output Enable
Program Enable
Programming Voltage
Data Output
+SV Power Supply
Ground
No Connection; No
Internal Connection

Vec and input voltages W.r.t. Vss ........ -0.6V to +7.2SV
Vpp voltage w.r.t. vss during
programming ..................................... -0.6V to +14.0V
Voltage on A9 w.r.t. Vss ............................ -0.6V to +13.SV
Output voltage w.r.t. Vss .................... -0.6V to Vcc + 1.0V
Temperature under bias ...................... -6S·C to 12S' C
Storage temperature ........................... -6S'C to 150' C
ESD protection on il.II pins ..................................... 2KV
"Notice: Stresses above those listed under "Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device atthose or any
other conditions above those indicated in the operation listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

Vee = +SV ±10%
Commercial: Tamb= O' C to 70' C
Tamb= -40' C to 85' C
Industrial:

READ OPERATION
DC Characteristics

Parameter

Part" .

Input Voltages

all

Input Leakage

all

Output Voltages

all

Status

Symbol

Min

Max

Logic "1"
Logic "0"

VIH
VIL
III

2.0
-0.1
-10

Vcc+l
0.8
10

2.4

V
V
IlA

Output Leakage

all

VOH
VOL
ILO

Input Capacitance

all

CIN

Output Capacitance

all

GoUT

Power Suppy Current,
Active

all

lee1

Power Supply Current,
Standby
Power Supply Current,
Standby
Ipp Read Current
Vpp Read Voltage

S,SX

lee(s)1

lee(S)2

3
100
100
Vee

L,LX
L,LX
all
all

Logic "1"
Logic "0"

Units Conditions

TTL input

TTL input
CMOS input
Read Moc!e
Read Mode

Ipp
Vpp

-10

Vee-0.7

V
V

0.45
10

IlA

IlA
IlA
V

VIN= -0.1 to Vcc + 1.0V
IOH= - 2mA
IOL=8mA
VOUT= -0.1 to Vcc+ 1.0V
VIN= OV; Tamb = 2S' C;
1= lMHz
VOUT= OV;Tamb= 25' C;
1= lMHz
Vee = S.SV; Vpp = Vee
1= 2MHz;
OE = CE =VIL;
lout = OmA;
VIL= -0.1 to 0.8 V;
VIH= 2.0 to Vee;
Note 1

CE = Vee ±0.2V
Vpp = S.SV
Note 2

" Parts:
S = Standard Power; L = Low Power; X = Industrial Temp Range;
Notes: (1) AC Power component above 2MHz: 2mAlMHz.
(2) Vee must be applied simultaneously or belore Vpp and be removed simultaneously
or after VPP.

DSll0l08-2

3-50

1990 Microchip Technology Inc.

27HC1616
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:

READ OPERATION
AC Characteristics

Parameter

Part' Sym

VIH= 3.0 V and VIL= 0.0 V; VOH = VOL = 1.5 V
1 TTL Load + 30 pF
5 nsec
O· C to 70· C
Commercial: Tamb=
Tamb= -40· C to 85· C
Industrial:

27HC1616-45

27HC1616-55

27HC1616-70

Min

Max

Units

Conditions

Max

Address to Output Delay

all

IACC

CE =OE = VIL

CE to Output Delay

L
S

tcE1
tcE2

45
30

55
35

70
45

OE = VIL

OE to Output Delay

all

tOE

CE = VIL

CE or OE to OIP High
Impedance

all

tOFF

Output Hold from
Address CE or OE. whichever occurs first

all

toH

a
a

* Parts: S = Standard Power; L = Low Power

READ WAVEFORMS

VIH
Address valid

Address
VIL
VIH
CE
VIL

VIH
OE
VIL

Outputs

00 - 015

VOH

High Z

Valid Output

VOL
IAcc

Notes: (1) tOFF is specified for OE or CEo whichever occurs first
(2) OE may be delayed up to tCE - toE after the falling edge of CE without impact on tCE
(3) This parameter is sampled and is not 100% tested.

DS11010B-3

3-51

27HCt616
PROGRAMMING
DC Characteristics
Parameter
Input Voltages

Ambient Temperature: 25° C ±5° C
For vpp and Vee Voltages refer to Programming Algorithms

Status

Symbol

Min

Max

Units

Logic "1"
Logic "0"

VIH
VIL

2.0
-0.1

Vee+l
0.8

V
V

III

-10

IlA

VIN= -.IV to Vee + 1.0V

VOH
VOL

2.4
0.45

V
V

IOH= - 2mA
IOL= 8mA

Input Leakage
Output Voltages

Logic "1"
Logic "0"

Conditions

Vee Current, program & verify

lee

Note 1

Vpp Current,program

Ipp

Note 1

A9 Product Identification

12.5

11.5

Note: (1) Vee must be applied simultaneously or before Vpp and removed simultaneously or after VPP

PROGRAMMING
AC Characteristics
for Program, Program Verify
and Program Inhibit Modes

AC Testing Waveform: VIH= 2.4V; VIL= 0.45V; VOH= 2.0V and VOL = 0.8V
Output Load:
1 TTL Load + 100 pF
Ambient Temperature: 25° C ±5° C
For Vpp and Vee Voltages, refer to Programming Algorithms

Symbol

Min

Address Set-Up Time

lAs

Ils

Data Set-Up Time

tDS

Ils

Data Hold Time

tDH

IlS

Address Hold Time

lAH

Ils

Float Delay (3)

tDF

Vee Set-Up Time

tves

Program Pulse Width (1)

tpw

0.95

1.05

1 ms typical

Program Pulse Width (1)

IPw

105

Ils

100 Ils typical

CE Set-Up Time

teEs

Ils

OE Set-Up Time

toES

Ils

Vpp Set-Up Time

tvps

Ils

Overprogram Pulse Width (2)

topw

2.85

Parameter

Data Valid from OE

toE

Max

130

Units

Remarks

ns
Ils

78.75

100

Notes: (1) For express algorithm, initial programming width tolerance is 100 Ilsec ±5%. For fast
programming algorithm, initial program pulse width tolerance is 1 msec ± 5%.
(2) For fast programming algorithm, the length of the overprogram pulse may vary from 2.85 to 78.75 msec
as a function of the iteration counter value.
(3) This parameter is only sampled and not 100% tested. Output float is defined as the point where data
is no longer driven (see timing diagram).

08110108-4

3-52

27HC1616
PROGRAMMING

Waveforms
~-----

Program - - - - - - ' * - - - - - Verify

------l~

Address

Data

Vpp
5.0V
6.0V/6.5V(2)
Vee
5.0V
VIH
CE
VIL
VIH
PGM
VIL
tOE
(1 )

VIH
OE
VIL
Notes:

(1) tDF and tOE are characteristics of the device but must be accomodated by the programmer
(2) Vee = 6.0V ±O.25V, Vpp = VH = 12.5V ±O.5V for fast programming algorithm
Vee = 6.5V ±O.25V, Vpp = VH = 13.0V ±O.25V for express algorithm

FUNCTIONAL DESCRIPTION
The 27HC1616 has the following functional modes:

Operation Mode eE

-Operation: The 27HC 1616 can be activated for data
read, be put in standby mode to lower its power
consumption, or have the outputs disabled.

Read
Program
Program Verify
Program Inhibit
Standby
Output Disable
Identity

-Programming: To receive its permanent data, the
27HC1616 must be programmed. Both a program
and program/verify procedure is available. It can be
programmed with Fast or Express algorithm.

PGM

VPp

Vce
VH
VH
VH
Vce
Vce
Vee

X
X
X
X
X
X

VIL
VIL
VIH
VIH
VIH

VIL
VIH
VIL

VIH
VIL
VIH

X
X

VIH
VIL

VIH
VIH

VIL

00-015
Dout
Din

Dout
High Z
High Z
High Z
Identity Code

X ~ Don't eare
VH ~ 12.0 ±O.5V

The programming equipment can automatically recognize the device type and manufacturer using the identity
mode.
For the general characteristics in these operation and
programming modes, refer to the table.

3-53

08110108-5

27HC1616
OPERATION
Read Mode
For timing and AC characteristics refer to the tables
Read Waveforms and Read Operation AC Characteristics.
The 27HC1616's memory data is accessed when
-the chip is enabled by setting the CE pin low.
_
-the data is gated to the output pins by setting the OE
pin low.
For Read operations on the Low Power version, once
the addresses are stable, the address access time
(tACC) is equal to the delay from
to output (tCE). A
faster CE access time (tCE) is available on the standard
part to provide the additional time for decoding the CE
signal. Data is transferred to the output after a delay
(tOE) from the falling edge of CE.

Standby Mode
The standby mode is entered when the GE pin is high,
and the program mode is not defined. When these
conditions are met, the supply current will drop from
90mA to 100llA on the low power part, and to 50mA on
the standard part.

Output Disable
This feature eliminates bus contention in multiple bus
microprocessor systems. The outputs go to a high
impedance when the OE pin is high, and the program
mode is not defined.

ProgramminglVerification
The 27HC1616 has to be programmed, and afterward
the programmed information verified. Before these
operations, the Identity Code can be read to properly set
up automated equipment. Multiple devices in parallel
can be programmed using the programming and inhibit
modes.

Since the erase state is "1" in the array, programming of
"0" is required. The address of the memory location to
be programmed is set via pins AO - A 13, and the data is
presented to pins 00 - 015. When data and address are
stable, a low going pulse on the CE line programs that
memory location.

Verify
After the array has been programmed, it must be verified
to make sure that all the bits have been correctly
programmed. This mode is entered when all of the
following conditions are met:
a) Vcc is at the proper level
b) Vpp ~at the proper VH level
c) the OE line is low
d) the CE pin is low, and
e) the PGM line is high.

Inhibit Mode
When ProgramminlLfl'llJltiple devices in parallel with
different data only PGM needs to be under separate
control to each device. By pulsing the PGM line low on
a particular device, that device will be Rrogrammed, and
all other devices with corresponding PGM or CE held
high will not be programmed with the data although
address and data are available on their input pins.

Identity Mode
In this mode specific data is read from the device that
identifies the manufacturer as Microchip Technology,
and the device type. This mode is entered whellPin A9
is taken to VH (11.5V to 12.5V). The CE and OE pins
must be at VIL. AO is used to access any of the two nonerasable bytes whose data appears on 00 - 07.

PinIdentity

Manufacturer
Device Type'

Output'

00 0
7 6 5

VIL
VIH

0 0
1 0

Programming Algorithms
Two programming algorithms are available: fast programming and express.

Input

1
0

00 0
4 3 2

0 0
1 0

0 1
1 0

0
1

1 29
1 97

The fast programming algorithm is the industry standard
programming mode that requires both initial programming
pulses and overprogramming pulses. A flowchart of the
algorithm is shown in Figure 1.

'Code subject to change.
Note: 015 - 08 are 00 for the manufacturer and
device type code.

The express algorithm has been developed to improve
programming through-put times in a production environment. Up to 10 pulses of 1OOllsec each are applied until
the by1e is verified. No overprogramming is required. A
flowchart of this algorithm is shown in Figure 2.

The programming mode is entered when:
a) Vcc is brought to the proper level
b) Vpp is brought to the proper VH level
c) the OE pin is high
d) the CE pin is low, and
e) the PGM pin is pulsed low.

D5110108-6

H
e
x

Windowed products offer the ability to erase the memory
array. The memory matrix is erased to the all "1 "s state
as a result of being exposed to ultra-violet light at
wavelengths ~ 4000 Angstroms (A). The recommended
procedure is to expose the erasure window of device to
a commercial UV source emitting at 2537A with an
intensity of 12,0001lW/cm 2 at 1". The erasure time althat
distance is about 15 to 20 min.
Note: Fluorescent lights and sunlight emit rays at the
specified wavelengths. The erasure time is about 3
years or 1 week resp. in these cases. To prevent loss of
data, an opaque label should be placed overthe erasure
window.

3-54

27HC1616
PROGRAMMING - FIGURE 1
EXPRESS ALGORITHM
Conditions:
Tamb = 25" C t5" C
Vee = 6.5 ±O.25 V
Vpp = 13.0 to.25 V

ADDR = First Location
Vee = 6.5 V
Vpp= 13.0 V

3-55

D811010B-7

27HCt616
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.

PART NUMBERS

J
K
L
P

Temperature
Range:

I Access Time:

I
'--_ _ _ _ _ _-11 Device

DS110108-8

Cerdip DIP
Ceramic Leadless Chip Carrier
Plastic Leaded Chip Carrier
Plastic DIP

O· C to 70· C
-40· C to 85· C

Blank
I

45
55
70

27HC1616
27HC1616L

45 nsec
55 nsec
70 nsec
256K (16K x 16) High Speed CMOS EPROM
256K (16K x 16) High Speed Low Power CMOS
EPROM

3-56

27HC641

Microchip

64K (8K X 8) High Speed CMOS UV Erasable PROM
FEATURES

DESCRIPTION

Bipolar Performance
- 40ns Maximum Access Time
CMOS Technology For Low Power Consumption
- 80mA Active Current
- 1OO~A Standby Current (Low Power Option)
OTP (One Time Programming) Available
Auto-Insertion-Compatible Plastic Packages
Auto IDTM Aids Automated Programming
Two Programming Algorithms Allow Improved
Programming Times
- Fast Programming
- Express
Organized 8K x 8: Bipolar PROM Pinouts
- 24 Pin Dual in Line Package
- 28 Pin Chip Carrier (Lead less or Plastic)
Available for Extended Temperature Ranges:
- Commercial: 0' C to 70' C
- Industrial: -40' C to 85' C
- Military": -55' C to 125' C

The Microchip Technology Inc27HC641 isaCMOS 64K
bit ultraviolet light Erasable (electrically) Programmable
Read Only Memory. The device is organized as 8K
words by 8 bits (8K bytes). An advanced CMOS design
allows bipolar speed with a significant reduction in
power over bipolar PROMs. A low power option (L)
allows further standby power reduction to 1OO~A. The
27HC641 is configured in a standard 64K bipolar PROM
pinout, which allows an easy upgrade for PROM sockets. This very high speed device allows digital signal
processors (DSP) or other sophisticated microprocessors to run atfull speed withoutthe need for WAIT states.
CMOS design and processing enables this part to be
used in systems where reduced power consumption and
reliability are requirements.
A complete family of packages is offered to provide the
utmost flexibility in applications. Skinny Cerdip (300 mil)
and Skinny Plastic are available. One Time Programming (OTP) is available for low cost (plastic) applications.

PIN CONFIGURATION

BLOCK DIAGRAM

00········07

Top View
A7
A6

Vee
AS

CENpp

Chip Enable

Control Logic

A9
A4

A3
A2
A1
AO

00
01
Vss

A10
CE/Vpp

Vss

Vee

A11
A12

07
06
05
04

Ao __1-r-~-I------L-~----------~
I
I
I

X
Decoder

• Pin 1 indicator on PLCC on top of package

64Kbit
Cell Matrix

A12

"See 27HC641 Military Data Sheet DS60007A

3-57

DS11115D-1

27HC641
ELECTRICAL CHARACTERISTICS
Maximum Ratings·

PIN FUNCTION TABLE
Name

Function

AO - A12
CElVpp
00-07
Vee
Vss
NC

Address Inputs
Chip EnablelVpp Pin
Data Output
+5V Power Supply
Ground
No Connection; No
Internal Connection
Not Used; No External
Connection Is Allowed

Vcc and input voltages
w.r.t. Vss ................................................-O.6V to + 7.25V
CElVpp voltage w.r.t. Vss during
programming.....
...... -0.6V to + 14V
Voltage on A9 w.r.t. Vss ........................... -0.6V to +13.5V
Output voltage w.r.t. Vss ....................... -0.6VtoVcc+1.0V
Storage temperature ..................................... -65' C to 150' C
Ambient temperature with
................. -65· Cto 125' C
power applied
.... 2KV
ESD protection on all pins ....
'Notice: Stresses above those listed under"Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation olthe device at those or any
other conditions above those indicated in the operation listings
of this specification is notimplied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

READ OPERATION
DC Characteristics

Vcc = +5V ±1 0%
Commercial: Tamb= O· Cto 70' C
Tamb= -40' C to 85' C
Industrial:

Parameter

Part"

Status

Symbol

Min

Max

Units Conditions

Input Voltages

all

Logic "1"
LOQic "0"

Input Leakage

all

VIH
Vil
III

2.0
-0.1
-10

Vee+1
0.8
10

V
V
flA

VIN= OV to Vec

Output Voltages

all

2.4
0.45
10

V
V
flA

IOH= - 4mA
IOl= 16mA
VOUT= OV to Vcc
VIN= OV; Tamb = 25°C;
I -1MHz
VOUT= OV;Tamb = 25°C;
1= 1MHz
Vce = 5.5V; CE/Vpp = Vil
f= 2MHz;
lout = OmA;
Vll= -0.1V to 0.8 V;
VIH= 2.0V to Vcc;
Note 1

Logic "1"
Logic "0"

Output Leakage

all

VOH
VOL
IlO

Input Capacitance

all

CIN

Output CapaCitance

all

CoUT

Power Suppy Current,
Active

S,L
TIL input
SX,LX TIL input

lecl
ICC2

80
90

Power Supply Current,
Standby
Power Supply Current,
Standby

S
SX
L
LX
L, LX

ICC(S)l

40
50
2
3
100

mA
mA

TIL input
TIL input
CMOS input

-10

Icc(s)2

mA
rnA
flA

CElVpp = Vce ±O.2V

• Parts:
S = Standard Power; L = Low Power; X = Industrial Temp Range;
Notes: (1) AC Power component above 2 MHz: 3mAlMHz for standard part; 5 mAlMHz lor
industrial temperature range part.

DSlll15D-2

3-58

27HC641
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:

READ OPERATION
AC Characteristics

Parameter

Part' Sym

VIH~ 3.0V and VIL~ O.OV; VOH ~ VOL ~ 1.5V
1 TIL Load + 30 pF
5 nsec
Commercial: Tamb~ O· C to 70· C
Tamb ~ -40· C to 85· C
Industrial:

27HC641·40' 27HC641·45 27HC641·55 27HC641·70
Min

Max

Min

Max

Min

Max

Min

Units Conditions

Max

Address to Output Delay

ali

IAcc

Ct/Vpp to Output Delay

tCEI
tCE2

40
30

45
35

55
35

70
45

S
Ct/Vpp to OIP High
Impedance

ali

tOFF

Output Hold from
Address or CE/Vpp, whichever goes first

ali

tOH

, Parts: S ~ Standard Power; L ~ Low Power
" 27HC641-40 is only available in commercial temperature range

READ WAVEFORMS

VIH-------.....
Address

CE/Vpp

Address Valid

VIL - - - - - - - "
VIH - - - - - - - - t - - . , .
VIL

Outputs
00 -07

VOH

High Z

Valid Output

VOL
~---

lAce

------I~

Note: (1) This parameter is sampled and is not 100% tested.

3-59

08111150-3

27HC641
PROGRAMMING
DC Characteristics

Ambient Temperature: Tamb ; 25' C ±5' C
For CE/Vpp and Vee Voltages refer to Programming Algorithms

Parameter

Status

Symbol

Min

Max

Units

Input Voltages

Logic "1"
Logic "0"

VIH
Vil

2.0
-0.1

Vee+1
0.8

V
V

III

-10

/lA

VIN; OV to Vee

VOH
VOL

2.4
0.45

V
V

IOH; - 4mA
IOl; 16mA

Input Leakage

Output Voltages
du ring verification

Logic "1"
Logic "0"

Vee Current,
program & verify

lee

Vpp Current,
program

Ipp

A9 Product Identification

12.5

PROGRAMMING
AC Characteristics
for Program, Program Verify
and Program Inhibit Modes

11.5

Conditions

AC Testing Waveform: VIH; 2.4 V and Vll; 0.45 V; VOH; 2.0 V; VOL; 0.8 V
Output Load:
1 TTL Load + 100 pF
Ambient Temperature: Tamb; 25' C ±5' C
For CE/Vpp and Vce Voltages, refer to Programming Algorithms

Max

Units

Remarks

Parameter

Symbol

Min

Address Set-Up Time

lAs

/ls

Data Set-Up Time

tos

/ls

Data Hold Time

tOH

/ls

Address Hold Time

IAH

/ls

Float Delay (3)

tOF

Vee Set-Up Time

tves

Program Pulse Width (1)

tpw

0.95

1.05

1 ms typical

Program Pulse Width (1)

tpw

105

/ls

100 /ls typical

Overprogram Pulse Width (2)

topw

2.85

78.75

CE to Output Delay

teE

100

130

/ls

Notes: (1) For Express algorithm, initial programming width tolerance is 100 /lsec ±5%. For fast
programming algorithm, initial program pulse width tolerance is 1 msec ± 5%.
(2) For fast programming algorithm, the length of the overprogram pulse may vary from 2.85 to 78.75 msec
as a function of the iteration counter value.
(3) This parameter is only sampled and not 100% tested. Output float is defined as the point where data
is no longer driven (see timing diagram).

08111150-4

3-60

27HC641
PROGRAMMING
Waveforms
~----- Program-----~----

Verify

---~

VIH
Address
VIL
VIH

High Z

Data
VIL

6.0V/6.5V(2)
Vcc
5.0V
VH 12.5V/13.0V(2)

CE/Vpp

tCE

VIH
tpw
VIL
topw

Notes:

(1) tDF is a characteristics of the device but must be accomodated by the programmer
(2) Vcc = 6.0V ±O.25V, CE/vpp = VH=12.5V ±O.5V for fast programming algorithm
Vcc = 6.5V ±O.25V, CE/vpp = VH=13.0V ±O.25V Express programming algorithm

MODES

Read Mode
A9

Read/Program Verify

IAl

Program

\A-I

X
X

Standby/Program Inhibit

IAH
IAl

High Z

\A-I

Identity Code

Identify

(See Timing Diagrams and AC Characteristics)

00-07

CE/Vpp

Operating Modes

DoUT

Read Mode is accessed when

DIN

the CE/Vpp pin is low to power up (enable) the
chip

X = Don't Care

For Read operations on the low powered version, if the
addresses are stable, the address access time (tACC) is
equal to the delay from CE/Vpp to output (tCE). A faster
CE/Vpp access time (tCE) is available on the standard
part to provide the additional time for decoding for the
CE/Vpp signal.

3-61

OS111150-5

27HC641
Standby Mode
The standby mode isdefinedwhenthe CENpppin ishigh
(VI H).
When this condition is met, the supply current will drop
from BOmA to 1OOIlA on the low power part and to 40mA
on the standard part.

Erase Mode
Windowed products offer the ability to erase the memory
array. The memory matrix is erased to the all "1 '''s state
as a result of being exposed to ultraviolet light. To
ensure complete erasure, a dose of 15 watt-second/cm 2
is required. This means that the device window must be
placed within one inch and directly underneath an ultraviolet lamp with a wavelength of 2537 Angstroms, intensity of 12,000IlW/cm 2 for 20 minutes.

Programming Mode
Two programming algorithms are available. The fast
programming algorithm is the industry-standard programrning mode that requires both initial programming
pulses and overprogramming pulses. A flowchart of the
fast programming algorithm is shown in Figure 1.
The Express algorithm has been developed to improve
on the programming throughput times in a production
environment. Up to 10 100-microsecond pulses are
applied until the byte is verified. No overprogramming is
required. A flowchart of the Express algorithm is shown
in Figure 2.
The CENpp is a multifunction pin that controls the
programming of the 27HC641 .
Programming takes place when:
a) Vcc is brought to proper voltage,
b) the CE Npp pin is pulsed at the proper VH level.

Since the erased state is "1" in the array, programming
of "0" is required. The address to be programmed is set
via pins AO - A 12 and the data to be programmed is
presented to pins 00 - 07. When data and address are
stable, a high voltage pulse (VH) on the CENpp line
programs that location.

After the array has been programmed it must be verified
to ensure all the bits have been correctly programmed.
This mode is entered when all the following conditions
are met:
a) Vcc~ at the proper level,
b) the CENpp line is low.

When programming multiple devices in parallel with
different data, only CENpp needs to be under separate
control to each device. By pulsing the CENpp line to a
VH on a particular device, th~device will be programmed; all other devices with CENpp held high (VIH)
will not be programmed with the data, although address
and data will be available orlJ!:eir input pins (i.e., when
a level (VIH) is present on CENpp) and the device is
inhibited from programming.

Identity Mode
In this mode specific data is output which identifies the
manufacturer as Microchip Technology Inc., and the
device type. This mode is entered when Pin A9 is taken
to VH (11.5V - 12.5V).
The CENpp line must be at VIL. AO is used to access any
of the two non-erasable bytes whose data appears on
00 through 07.

PinIderty

Manufacturer
Device Type

Input

Output
H
e
x

0 0
7 6

0 0 0
5 4 3

0
2

0
1

0
0

VIL
VIH

0 0
0 0

1
0

0
0

1 29
0 10

0
1

- Code subject to change.

D511115D-6

3-62

27HC641
PROGRAMMING - FIGURE 1
EXPRESS ALGORITHM
Conditions:

lamb = 25' C ±5' C
Vee = 6.5 ±0.25 V
Vpp = 13.0 ±0.25 V

ADDR

= First Location
Vee= 6.5 V
Vpp= 13.0V

3-63

DS11115D-7

27HC641
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.

PART NUMBERS
27HC641 - 45 II K

Package:

J
K
L
P
SJ
SP
Blank
I

'------II Temperature
I Range:
Access Time:

OS111150·8

Device:

40
45
55
70

27HC641
27HC641 L

Cerdip DIP
Ceramic Leadless Chip Carrier
Plastic Leaded Chip Carrier (OTP Available)
Plastic DIP (OTP Available)
SKINNY CEROIP
SKINNY PLASTIC (OTP Available)
0' C to 70' C
·40' C to 85' C

40
55
55
70

nsec
nsec
nsec
nsec

64K (8K x 8) High Speed CMOS EPROM
64K (8K x 8) High Speed Low Power CMOS
EPROM

3-64

_Microchip

Application Notes
EPROM PROGRAMMING ALGORITHM

27Cxxx EPROM FAMILY
PROGRAMMING ALGORITHM
Overview

Microchip Technology Inc supports three programming algorithms for its CMOS EPROM
Family. The selection of an algorithm is an important consideration and will impact the
programming time, programming yield and programming margins of the EPROM.

Fast Programming Algorithm

This is the old industry standard programming algorithm with up to 25 1-msec
programming pulses and a three times overprogramming pulse. It is a very stable algorithm
to use, with its major draw back being an increase in throughput time especially at the
larger densities.

Rapid Pulse Programming Algorithm

The Rapid Pulse algorithm provides an alternative· to the Fast algorithm. The slight
increase in Vee and Vpp during programming allows the use of a narrower 100 usec
programming pulse and the removal of the overprogramming pulse associated with the
Fast Programming. This translates into a decrease in programming times of nearly 40 to 1
and an increase in throughput of nearly 10 to 1. (Throughput is heavily influenced by the
machine cycle time of the programmer during the pre-programming blank check, and the
post-programming verification. It also varies from programmer to programmer.)

Express Programming Algorithm

The Express algorithm is an improvement on the Rapid Pulse algorithm. While it exhibits
the same excellent throughput as the Rapid Pulse algorithm, its advantage lies in the
additional increase in VPP and Vee applied during programming. The higher Vpp and Vee
voltages provide additional charge to the floating gate during programming. After each
programming pulse, the cell is verified against Vee (6.5 Volts for Express, 6.25 volts for
Rapid Pulse). This verification step with a higher Vee ensures improvement in
programming margins over the Rapid Pulse algorithm.

EPROM PROGRAMMING ALGORITHM

Algorithm Selection

The optimization of programmer throughput is a concern
to all EPROM users in a production environment. A major
contributor to increasing throughput is shorter
programming times. The Express algorithm has been
developed to minimize programming times. In addition,
sufficient programming margins must be developed to
insure EPROM functionality over the full range of voltage
and temperature variations. The higher Vcc and Vpp
voltages generate this increased margin and provide
additional guardband against the effects of aging
hardware.

PROGRAMMING ALGORITHM
Fast Algorithm
Conditions:
Tamb = 25' C±5' C
Vee = 6.0 ±0.25V
VPP = 12.5 ±0.5V

ADDR = First Location
Vcc = 6.0V
VPP = 12.5V

Programming Times (sec)
Memory Size

Fast

Rapid

Express

64K
128K
256K
512K

32.8
131.1
93/32
262.2

0.819
1.64
3.28
6.55

Note.

Actual throughput time depends on the machine cycle
time of the programmer during pre·programming blank
check, and the post·programming verification.

Microchip Programming Algorithm
Recommendations

Microchip recommends that the Express algorithm be
used on all commercial/industrial EPROMs (when
available).
The Fast Programming algorithm should be your second
choice for the 64K and the 128K EPROMs, with Rapid
Pulse being the second choice for the 256K and 512K
EPROMs, The remaining algorithm should be your third
choice. This recommendation is based on the
maximization of programmer throughput and cell
margins. At the smaller density (when Express is not
available) the increased margins supplied by the Fast
Programming far outweigh the small increase in
throughput of Rapid Pulse. As you increase density,
programming throughput becomes the dominant criteria.
Data 1/0 Family Code and Pin-Outs·
Device

Size

Fast

Rapid

Express

27C64

64K

93/33

5C/33

115/033

27C128

128K

93/51

5C/51

115/051

27C256

256K

93/321

5C/32

115/032

27C512

512K

4B/A4

5E/A4

116/0A4

• DIP Packages

DS11138A

EPROM PROGRAMMING ALGORITHM

PROGRAMMING ALGORITHM

Rapid Pulse

Express

Conditions:

Tamb = 25" C ±5" C

T amb = 25°C ±5°C

Vee = 6.25 ±0.25V
Vpp = 12.75 ±0.25V

Vee = 6.5 ±0.25V
Vpp = 13.0 ±0.25V

= First Location
Vce = 6.25V
Vpp= 12.75V

ADDR

ADDR = First Location
Vee = 6.5V
Vpp = 13.0V

DS11138A

3-67

EPROM PROGRAMMING ALGORITHM

NOTES:

3-68

Microchip

SECTION 4
MICROCONTROLLER
PRODUCT SPECIFICATIONS
PIC
PIC16C5X
PIC1654S
PIC1655
PIC1670

PIC 16xxx Series Microcontroller Family ..................................................................4- 1
EPROM-Based 8-Bit CMOS Microcontroller Series ................................................ .4- 5
8-Bit Microcontroller .................................................................................................. 4- 35
8-Bit Microcontroller .................................................................................................. 4- 51
8 Bit Microcontroller .................................................................................................. 4- 67

4-i

DS00018C

Microchip

DS00018C

4-ii

Microchip

PIC® 16xxx SERIES

PIC 16xxx Series Microcontroller Family
FEATURES
PIC EPROM Technology
PIC's OTP EPROM technology offers a low cost alternative to using competitive ROM based devices for high
volume production. EPROM technology also offers
several important cost saving advantages namely:

Time-To-Market:

Since the financial success of a
product is often determined by its time-to-market, through
user programmability PIC offers an immediate solution
to lengthy market entry delays. Our off-the shelf products eliminate the 10-18 week lead times experienced
with conventional ROM based MCU suppliers.

EPROM Flexibility: Means decisions to change codes
"on-the-fly" while in development or in mid-production
no longer carry a financial or time penalty in the event of
error. System performance enhancements which may
be critical to market success can now be achieved
quickly, effortlessly and cost effectively. Another demonstration of EPROM flexibility is the ability to perform incircuit-programming. This allows for product variants to
be developed cost effectively. Participation in high profit
custom business becomes economically feasible with
OTP PICs.
Off-The-Shelf: EPROM technology benefits the user by
eliminating the need for substantial inventories and
limits exposure to product obsolescence; typical of ROM
devices. OTP parts also ensure an immediate supply
from a variety of worldwide stocking locations. High
volume quick-turn-production (aTP) programming services are also available from Microchip for customers who
chose not to perform high volume programming themselves.

THE PIC FAMILY
A History of Innovation and Success
Microchip's history of innovation and its strong commitment to develop and market leading edge products, is
best exemplified by its popular 8-Bit Microcontroller
families. Microchip is the first semiconductor company
to introduce RISC-like features and offer the time saving
flexibility of one-time-programmable (OTP) EPROM 8Bit MCUs. These new design concepts and the integration of advanced CMOS EPROM technology overcomes
three major user barriers, namely: efficiency/perform"
ance; time to market; and affordability. The benefits of
PIC® microcontroller technology are being shared by
hundreds of customers worldwide with over 80 million
CMOS and NMOS PIC microcontrollers in use.

PIC's RISC Architecture
PIC's RISC Architecture sets a new standard in performance in the 8-Bit MCU marketplace. The highly efficient
and powerful instruction set which supports this architecture requires only 33 single cycle instructions to learn
versus 60 to 110 multi-byte instructions common to
competitive CISC MCU architectures. Benchmarks
have demonstrated that the efficiency of this instruction
set provides the user with up to a 2:1 code compaction
advantage over competitive products. It has also
been demonstrated that this level of efficiency can also

reduce code development time by up to 30 percent.

PIC® is a registered trademark of Microchip
Technology Inc.
© 1990 Microchip Technology Inc.

4-1

OS300318-1

PIC 16xxx SERIES
The PIC's single cycle instructions andRISC architecture facilitates up to five million instructions per second
execution throughput. This provides the designer with
up to a 5:1 speed advantage over competitive products.
This advanced rate of code execution rivals many 16-Bit
MCU designs and opens new real-time, high performance application opportunities. Also, memory inefficient, engineering intensive and inaccurate look-uptables
can now be replaced with PIC's high level algorithmic
processing speed. Applications such as efficient motor
control, high speed 1/0 and high speed data bit stream
manipulation now becomes a reality in the a-Bit domain.
A new design concept of user definable oscillators
allows the chip to execute instructions in four speed
ranges from DC to 200ns.

PIC's CMOS Design

time multiplexed between input and output or can be
programmed into a high impedance state thus supporting multi-chip common bus configurations.
The PIC's small die size and Microchip's advanced
CMOS technology support a wide performance range
but also allow low operating and standby current. These
low currents will make long-life battery dependent projects possible.

PIC's Small Packaging
Microchip has also engineered the world's smallest 8-bit
microcontroller package. For highly integrated deSigns,
300 mil. wide 18 pin PDIP,SOIC and PLCC surface
mount packages are available. Tape and reel packaging is also offered for automatic high speed surface
mount placement.

PIC TemperatUre Ranges

The PIC employs a fully static CMOS design allowing for
reliable low power operation. PIC incorporates on-chip
POR and Watchdog Timer circuitry thus eliminating
expensive off-chip support components.

The PIC16C5X family is currently available in commercial and industrial temperatures. There are plans to offer
this family inautomotive and military temperatures.

Bit manipulation is one of PIC's strongest suits. The
designer can now utilize very powerful bit manipulation
instructions capable of setting, clearing and testing any
bit in any register (including 1/0 registers) in one instruction cycle. This allows the PIC to efficiently interface to
external circuitry and be used as a powerful 1/0 controller. The 1/0 is software definable bi-directional. Under
software control, each pin of a port can be individually

Future CMOS PIC generations will provide a family of
products with embedded analog capabilities, additional
1/0, sophisticated timers, increased memory and industry leading CPU power. The capability to address offchip extended RAMIEPROM memory and inter-chip
communication is currently under development.

UPward Migration Path

PIC FAMILY PRODUCT GUIDE
High Performance CMOS Microcontrollers...

where performance and power efficiency is prime consideration.

PIC16C5X CMOS MICROCONTROLLER
Part Number
PIC16C54
PIC16C55
PIC16C56
PIC16C57

Pins

1/0

RAM

ROM

EPROM

18
28
18
28

12
20
12
20

32x8
32x8
32x8
80 x a

512 x 12
512 x 12
1024 x 12
2048 x 12

Low-Cost NMOS Microcontrollers...

Oscillator Range Min.lnstr.Cycie
25kHz-20M Hz
25kHz-20M Hz
25kHz-20M Hz
25kHz-20M Hz

200ns
200ns
200ns
200ns

Available
NOW
NOW
NOW·
NOW

for highly cost sensitive applications where the superior
performance of the PIC16C5X series is not required.

PIC16XXX NMOS MICROCONTROLLER
Part Number
PIC1654S
PIC1655
PIC1670

05300318-2

Pins

1/0

RAM

18
28
40

12
20
32

32 x 8 512 x 12
32 x 8 512 x 12
64x8 1024 x 13

ROM

EPROM

4-2

Oscillator Range Min.lnstr.Cycle

21.ls
41.lS
21.ls

Available
NOW
NOW
NOW

PIC 16xxx SERIES
PC-HOSTED SYSTEMS SIMPLIFY
SOFTWARE DEVELOPMENT

QUALITY FROM THE TOP DOWN
AND THE BOTTOM UP

Two advanced PC-hosted systems, the PIC-ICETM and
PIC PAKTM, are available to help users develop applications software and program PIC 16C5X devices quickly
and easily. Both operate with IBM PC, XT, AT, or
compatibles.

Microchip's sole ownership of its facilities ensures our
quality control standards remain consistent throughout
all manufacturing steps. Continuous improvement programs are active at every operations level. Equipment
for simulation, product testing and failure analysis is
constantly updated to the most current levels of sophistication. Our customer support reaches out to the point
when a customer ships his product.

PIC-ICE
The PIC-ICE system provides low-cost in-circuit emulation and debugging and inciudes an 18-pin and 28-pin
EPROM PIC programmer. This low profile module has
a handy carrying case and comes with an external power
supply, ribbon cabling, cross assembler, PIC16C5X
EPROM product samples and a users manual. Key
features inciude a DC to 20M Hz operating range, a builtin disassembler, breakpoints and a symbolic debugger.

To ensure product quality, Microchip conducts accelerated mechanical tests, temperature tests and memory
retention tests to explore the many ways failures might
occur. Stresses carefully applied over time, guarantee
the effective operation of Microchip products. Comprehensive 1,OOO-hour qualification tests such as high
temperature reverse bias, high temperature retention
bake, latchup tests and operating life provide precise
quality and reliability data. An electrostatic discharge
sensitivity test is also conducted in accordance with M ILSTD 883-C, method 5005.

PIC PAK
The PIC PAK (PIC Applications Kit) is a powerful yet lowcost software development tool that combines assembler and simulator software to compile, execute, debug
and analyze microcode in a non-real time environment.
An EPROM PIC programmer (PIC PRO) and PIC16C5X
EPROM product samples are inciuded for code verification.

Microchip PIC microcontrollers have demonstrated their
reliability in several demanding applications such as
high noise, high temperature under-hood automotive
applications, NASA space shuttle missions and missile
safe-arm fuse control.

PICALC Cross Assembler
The PIC Cross Assembler PICALC is available for
several host computer platforms, including IBM PC.
Macro assembly and conditional assembly are just a few
of the capabilities of PICALC. Besides the PIC16C5x
and PIC167x family members. PICALC can generate
various object code formats to support Microchip's proprietary development tools as well as third party systems.

CMOS PIC16C5X MICROCONTROLLER
RELIABILITY DATA
(Failures/Sample Size)
TEST: 125°C DYNAMIC LIFE

PICSIM Software Simulator
The software simulator PICSIM allows PIC16C5x code
development on IBM PCs without any additional hardware. It simulates the PIC16C5x series on instruction
level. Software trace, break-points, symbolic debugging, and stimulus file generation are just a few of the
features available. PICSIM is particularly useful in the
early development stages of an application, or when
real-time and/or in-circuit emulation are not necessary
for the code development.

WJa

J..6.a..t:!R

2Q.Q.Ha

.1QQQ.HB..

Fits

4/2344

5/2340

0/2331

1/2331

117 Fits

TEST: 150°C HIGH TEMPERATURE REVERSE BIAS
0/162

0/162

16 Fits

TEST: 150°C RETENTION EPROM BAKE

PICPRO EPROM Programmer

0/1710

PICPRO is a low volume EPROM programmer for the
PIC16C5x series. It allows downloading and programming of PIC object code generated with PICALC from
any host computer system providing a serial interface
(RS232).

1/1710

1/1709

3/1708

31 Fits

Failure analysis available upon request.

DS30031 B-3

4-3

PIC 16xxx SERIES
EXACTING SOLUTIONS FOR DEMANDING APPLICATIONS .....
Smallest Packaging
For highly integrated insertion or surface mount modules, Microchip produces the smallest microcontroller
devices in the world, An 18 pin DIP, SOIC or PLCC
package makes space limited applications a design
reality, such as:
Handheld devices
• Automotive modules
Small PC peripherals
Consumer products
For even further integration, PIC's in dice form will also
be available for Hybrid or COB packaging.

Lowest Power Consumption

Fastest Operating Speed

The PIC16C5X families possess one of the lowest
standby and operating currents in the industry, opening
new design opportunities for battery, solar and remotely
powered applications, such as
Cordless Telephones
Mobile Telephones
• Automobile Electronic Locks
• Secure Access Remote Control
• Consumer Remote Controls
Remote Smart Sensors
• Cordless Radar Detectors

For "High Performance" applications, the PIC's 5 million
instruction per second architecture offers a very unique
solution. With PIC, system designers are now able to
replace inaccurate predetermined look-up table values
with high precision, real time, algorithmic processing.

A GLOBAL COMMITMENT TO
CUSTOMER SUPPORT

PIC can solve several real-time problems often found in
designs of:
Disk Drives
Pointing Devices/Scanners
Motor/Compressor Controls
I/O Processors
"Glue" Logic Replacement

Microchip's commitmentto microcontroller breakthrough
technology is superseded only by our attention to customer support. Through a worldwide network of manufacturing facilities, sales offices and field apr!;,.,~t;~r.,:
support, Microchip delivers total customer service
worldwide.

Microchip Technology Inc.' 2355 W. Chandler Blvd.' Chandler, AZ 85224-6199' (602) 963-7373' Printed in USA © 9003
United States: Mid-West (312) 505-0022
North-East (508) 820-3334
Mid-Atlantic (516) 232-1930
South-East (404) 642-6933 - South-Central (214) 733-0391 - North-West (408) 436-7950 - South-West (213) 323-1888
• France (1) 43.99.12.63 • West Germany (089) 609 6072' United Kingdom (0628) 776433 • Hong Kong 3/3116103
• Japan 3/2348774' Singapore 2355326' Taiwan 2/9146234' Korea 2/7398543
"Information contained in this publication regarding device applications and the like is intended by way of suggestion only. No representation or warranty is given and no liability is assumed by Microchip Technology
Inc. with respect to the accuracy or use of such information. The Microchip logo and name is a registered trademark of Microchip Technology Incorporated. All rights reserved:

DS300318-4

4-4

PIC®16C5x Series

Microchip

EPROM-Based 8-Bit CMOS Microcontroller Series
FEATURES
•

•

Low power, high speed CMOS EPROM technology
Wide variety of EPROM and RAM sizes, oscillator
types, frequency ranges and I/O configurations
Fully static chip design
Operating Frequency Range:
- DC - 8 MHz (20 MHz future release)
Operating voltage range:
- Standard: 4.0V to 5.5V
Low power consumption:
- < 2 mA (4 MHz, 5V, XTAL oscillator)
- < 1O!lA standby
Available in temp ranges:
- Commercial = O'C to + 70'C
- Industrial
= -40'C to + 85'C
Wide selection of 18 and 28 lead packaging
options: PDIP, SOIC, PLCC, or CERDIP Window

•
•
•
..
•

•

•
•
•

512 to 2048 words of 12-bit program EPROM
32 to 80 words of 8-bit data RAM
Only 33 single 12-bit-word instructions to learn
8 bitALU
12 or 20 bidirectional tristate 1I0's
2 level stack for subroutine nesting
Direct, indirect, immediate, and relative addressing
modes for data and instructions
8 bit real time clock/counter (RTCC) with selectable
signal source and trigger edge
Free running on-chip watchdog timer
8 bit prescaler, assignable to RTCC or watchdog
timer
Oscillator start up timer
Security EPROM fuse for code protection
OTP (factory programming) available

FIGURE 1: PIN CONFIGURATIONS
PDIP,SOIC
CERDIP Window

PDIP,SOIC
CERDIP Window

---4 Vss
N/C
.... RAO
.... RA1
.... RA2
HRA3
HRBO
HRB1

.... RBO
.... RB1

.... RB2
HRB3

PLCC

MCLR
RC7 ....
RC6H
RCS ....
RC4 ....
RC3 .....
RC2 ....
RC1 ....
RCO ....

4VOD
N/C

.... RA2
HRA3
4RTCC
->MCLR
-+ Vss

HRB2

RB7~

HRB3
HRB4

RB6 ....
RBS ....

PLCC

RRRV RRR
CBBsBBB

RRRRRRR
CBBBBBB
0765432

6545321

18 17 16 15 14 13 12
RB7

RBO

N/C
N/C

N/C
21

VOD

RC1

N/C
PIC16C54
PIC16C56

d 23
N/C d 24
aSC2 d2S
2627281

RC5

N/C

Res
RC7

N/C
2

d20
RC3 d21
RC4 d22
RC2

PIC16C55
PIC16C57

d25 262728123
aOMRVN/CV

aRRRRRM
SAAAATC
C0123CL
1
C R

[PIl®J~~m~I1il~II~ ~l1ilff@lIm~~~@11il

N/C

PIC® is a registered trademark of Microchip Technology, Inc.

RB1

10J RBO

sse

T 0

eeL c
2

R C

4-5

DS30015F-1

PIC®16C5x Series
GENERAL DESCRIPTION

ARCHITECTURAL DESCRIPTION

The Microchip Technology PIC16C5xseries is based on
the proven architecture of the PIC165x NMOS 8-bit
microcontroller family. Using Microchip's low-power,
high-speed CMOS EPROM technology, the PIC16C5x
offers additional features like on-chip watchdog timer,
tristate I/O, power-down mode, and several prescaler
options.
The advantages of the user programmable CMOS
EPROM technology allow extremely flexible applications, as well as reduced development costs and turnaround time compared to mask programmable ROM
versions.

HARVARD ARCHITECTURE

APPLICATIONS
The PIC16C5x series fits perfectly for applications from
high speed automotive and appliance motor control to
low-power remote transmitters/receivers, pointing devices, and telecom processors. The EPROM technology
allows customizing of application programs (transmitter
codes, motor speeds, receiver frequencies, etc.) extremely last and convenient. The small footprint packages lor through hole or surface mounting make this
microcontroller series perfect for all applications with
space limitations. low cost, high performance, ease of
use, and I/O flexibility make the PIC16C5x series very
versatile even in areas where no microcontroller use has
been considered before (e.g. timer functions, replacement of "glue" logic in larger systems, co-processor
applications) .

PIN FUNCTION TABLE

Name

Function

RAO - RA3
RBO - RB7
RCO - RC7
RTCC
MClR
OSCl
OSC2/ClKOUT

I/O PORTA
I/O PORT B
I/O PORTC
Real Time Clock/Counter
Master Clear
Oscillator (input)
Oscillator (output)
Power supply
Ground
No (internal) Connection

Voo
Vss
N/C

DS30015F-2

The PIC16C5x single-chip microcomputers are lowpower, high-speed, full static CMOS devices containing
EPROM, RAM, 110, and a central processing unit on a
single chip.
The firmware architecture is based on a register file
concept with separate bus and memories for data and
instructions (Harvard architecture). The data bus and
memory (RAM) are 8 bits wide while the program bus
and program memory (EPROM) have a width of 12 bits.
This concept allows a simple yet powerful instruction set
designed to emphasize bit, byte and register operations
under high speed with overlapping instruction fetch and
execution cycles. That means that, while one instruction
is executed, the following instruction is already being
read from the program memory. A block diagram of the
PIC16C5x series is given in Figure 2.

DATA REGISTER FILE
The 8 bit data bus connects two basic functional elements together: the Register File composed of up to 80
addressable 8 bit registers including the I/O Ports, and
an 8 bit wide Arithmetic logic Unit. 32 bytes of RAM are
directly addressable while a "banking" scheme, with
banks of 16 bytes each, is employed to address larger
data memories (Figure 3). Data can be addressed
direct, or indirect using the file select register (14).
Immediate data addressing is supported by special
"literal" instructions which load data from program
memory into the Wregister.
The register file is divided into two functional groups:
operational registers and general purpose registers.
The operational registers include the Real Time Clock
Counter (RTCC) register, the Program Counter (PC),
the Status Register, the 1/0 registers (PORTs), and the
File Select Register. The general purpose registers are
used lor data and control information under command of
the instructions.
In addition, special purpose registers are used to control
the I/O port configuration, and the prescaler options.

4-6

PIC®16C5x Series
ARCHITECTURAL DESCRIPTION (CONT.)
ARITHMETIC/LOGIC UNIT (ALU)

PROGRAM MEMORY

The 8 bit wide ALU contains one temporary working
register (W Register) and gating to perform Boolean
functions between data held in the W Register and any
file register.

Up to 512 words of 12 bit wide on-chip program memory
(EPROM) can be directly addressed. Larger program
memories can be addressed by selecting one of up to
four available pages with 512 words each (Figure 4).
Sequencing of microinstructions is controlled via the
Program Counter (PC) which automatically increments
to execute in-line programs. Program control operations, supporting direct, indirect, relative addressing
modes, can be performed by Bit Test and Skip instructions, Call instructions, Jump instructions or by loading
computed addresses into the PC. In addition, an on-chip
two-level stack is employed to provide easy to use
subroutine nesting.

FIGURE 2: PIC16C5x SERIES BLOCK DIAGRAM
OSC1 OSC2 MCLR

WDTTIME
OUT

8
"SLEEP"

DIRECT RAM
ADDRESS
GENERAL
PURPOSE
REGISTER
FILE

DATA BUS

4
FROMW

FROMW

"TRIS5"

"TRIS6"

4-7

"TRIS?"

RBO·RB?

RAO·RA3

FROMW

RCO·RC?
(PIC16C55/C5?
ONLY)

DS30015F-3

PIC®16C5x Series
PIC16C5X SERIES OVERVIEW
A wide variety of EPROM and RAM sizes, number of
I/O pins, oscillator types, frequency ranges, and packaging options is available. Depending on application and
production requirements the proper device option can
be selected using the foHowing information and tables.
When placing orders, please use the "PIC16C5x Product Identification System" on page 32 of this data sheet
to specify the correct part number.

UV ERASABLE DEVICES
Four different device versions, as listed in Table 1, are
available to accommodate the different EPROM, RAM,
and I/O configurations. These devices are optimal for
prototype development and pilot series. The desired
oscillator configuration is EPROM programmable as
"RC", "XT", or "HS". An erased device is configured as
"RC" type by default. Depending on the selected oscillator type and frequency, the operating supply voltage
must bewithin the same range as a OTP/OTP part would
be specified for.
The PIC development programmer, "PICPRO", can
program aH members of the PIC16C5x family for
prototyping and small-volume production. See page 432 for high-volume programming support.

ONE-TIME-PROGRAMMABLE (OTP) DEVICES
The availability of OTP devices is especially useful for
customers expecting frequent code changes and updates. OTP devices have the oscillator type pre-configured by the factory, and they are tested only for this
special configuration (including voltage and frequency
ranges, current consumption). Table 2 below gives an
overview about devices available now and planned for
future release.
The program EPROM is erased, allowing the user to
write his application code into it. In addition, the watchdog timer can be disabled, and/or the code protection
logic can be activated by programming special EPROM
fuses. The sixteen special EPROM bits for ID code
storage are also user programmable.

QUICK-TURNAROUND-PRODUCTION (QTP)
DEVICES
Microchip offers a OTP Programming Service for factory
production orders. This service is made available for
users who chose not to program a medium to high
quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices (see
Table 2) but with all EPROM locations and fuse options
already programmed by the factory. Certain code and
prototype verification procedures do apply before production shipments are available. Please contact your
Microchip Technology sales office for more details.

TABLE 1: OVERVIEW UV-ERASABLE DEVICES

EPROM

RAM

1/0"

Supply Voltage

Osc.Freq.Range

Package Options

PIC16C54

512 x 12

32 x 8

4.0' - 5.5 V

DC - 8 MHz **'

181d. Windowed CERDIP

PIC16C55

512 x 12

32 x 8

4.0' - 5.5 V

DC - 8 MHz , ••

28 Id. Windowed CERDIP

PIC16C56

1K x 12

32 x 8

4.0' - 5.5 V

DC - 8 MHz'"

18 Id. Windowed CERDIP

PIC16C57

2K x 12

80x8

4.0' - 5.5 V

DC - 8 MHz **.

28 Id. Windowed CERDIP

Frequencies above 4 MHz and/or operation in the industrial temperature range (-40 to +85'C) require that

..
**

Part #

VDD is greater than 4.75 V.
Includes RTCC pin

, Device operation is currently guaranteed up to 8 MHz oscillator frequency .
Please contact Microchip Technology Inc. for expected release dates of 20 MHz devices.

DS30015F-4 .

4-8

PIC®16C5x Series

TABLE 2: OVERVIEW OTP AND QTP DEVICES
Supply'"

Osc.

Voltage

Type

Freq.
Range

Package
Options (Note)

DC -4 MHz

DIP-18, SOIC-18, PLCC-28

4.0 - 5.5 V

XTAL, Ext.

0.4 - 4 MHz

DIP-18, SOIC-18, PLCC-28

4.5 - 5.5 V

XTAL, Ext.

4 - 8 MHz"

DIP-18, SOIC-18, PLCC-28

32 x 8

4.0 - 5.5 V

DC -4 MHz

DIP-28, SOIC-28, PLCC-28

512x 12

32 x 8

4.0 - 5.5 V

XTAL, Ext.

0.4-4 MHz

DIP-28, SOIC-28, PLCC-28

PIC16C55HS

512x 12

32x8

4.5 - 5.5 V

XTAL, Ext.

4 - 8 MHz"

DIP-28, SOIC-28, PLCC-28

PIC16C56RC

1K x 12

32 x8

4.0 - 5.5 V

DC-4 MHz

DIP-18, SOIC-18, PLCC-28

PIC16C56XT

1K x 12

32 x 8

4.0 - 5.5 V

XTAL, Ext.

0.4 - 4 MHz

DIP-18, SOIC-18, PLCC-28

PIC16C56HS

1K x 12

32 x 8

4.5 - 5.5 V

XTAL, Ext.

4 - 8 MHz

DIP-18, SOIC-18, PLCC-28

PIC16C57RC

2K x 12

80 x 8

4.0 - 5.5 V

DC-4MHz

DIP-28, SOIC-28, PLCC-28

PIC16C57XT

2K x 12

80x8

4.0 - 5.5 V

XTAL, Ext.

0.4-4 MHz

DIP-28, SOIC-28, PLCC-28

PIC16C57HS

2K x 12

SOx8

4.5 - 5.5 V

XTAL, Ext.

4- 8 MHz

DIP-28, SOIC-28, PLCC-28

Part #

EPROM

RAM

I/O'

PIC16C54RC

512x 12

32x8

4.0 - 5.5 V

PIC16C54XT

512x 12

32x8

PIC16C54HS

512 x 12

32 x 8

PIC16C55RC

512x 12

PIC16C55XT

...
...

Including RTCC pin
Device operation is currently guaranteed up to 8 MHz oscillator frequency .
Please contact Microchip Technology for expected release dates of 20 MHz devices.
Minimum supply voltage for industrial temperature range is 4.SV for XT and RC, and 4.7SV for HS versions .
Devices operating at supply voltages below 4.0V or 4.SV respectively, are under development.

4-9

DS30015F-5

PIC®16C5x Series
REGISTER FILE ARRANGEMENT

FIGURE 3: PIC16C5x DATA MEMORY MAP
FILE
ADDRESS

7 6 5 4 3 2 1 0
INDIRECT ADDR.

00
01

RTCC

IA10 IA91A8

n
10 9 8 7 6 5 4 3 2 1 0
RETLW

FSR

PORTA

PORTB

IIII-

09
OA
OB
OC

[TRiSA
I

TRISB

TRISC

I--

OPTION

GENERAL

PURPOSE

FILE

TOANO FROM
REGISTER FILE
VIAALU
W

1__

I--

5 4 3 2 1 0

I-- REGISTER _

STACK 2

7 6 543210

PORTC (.. )

10 9 8 7 6 5 4 3 2 1 0

I-I

STACK 1

CALL

STATUS

BIT 6, 5 OF FSR: BANK SELECT
(PIC16C57 ONLY)

00
1
10

101
30

FROMPR OGRAM MEMORY

11
12
13
14
15
16

17
18

GENERAL
PURPOSE
REGISTER
FILE
(ALL TYPES)

GENERAL PURPOSE
REGISTER FILE
(PIC16C57 ONLY)

19
1A
1B
1C

(BANKO) (0")

(BANK 1) ("0)

(BANK 2)

r")

(BANK 3) (0")

1E
1F

n
(.. )

NOT A PHYSICALLY IMPLEMENTED REGISTER. SEE SECTION "OPERATIONAL REGISTER FILES" FOR DETAILS
FILE f7IS A GENERAL PURPOSE REGISTER ON THE PIC16C54/C56

(0") BANK 0 IS AVAILABLE ON ALL MICROCONTROLLERS WHILE BANK 1 TO BANK 3 ARE ONLY AVAILABLE ON THE
PIC16C57. (SEE SECTION "FILE SELECT REGISTER" FOR DETAILS)

DS30015F-6

4-10

PIC®16C5x Series
OPERATIONAL REGISTER FILES

f1 REAL TIME CLOCK/COUNTER REGISTER
(RTCC)

INDIRECT DATA ADDRESSING

Not a physically implemented register. fO calls for the
contents of the File Select Register to be used to select
a file register. fO is useful as indirect address pOinter. For
example, the instruction ADDWF fO, W will add the
contents of the register pointed to by the FSR (f4) to the
content of the W Register and place the result in W .

This register can be loaded and read by the program as
any other register. In addition, its contents can be
incremented by an external signal edge applied to the
RTCC pin, or by the internal instruction cycle clock
(CLKOUT;f05c/4).
An 8 bit prescaler can be assigned to the RTCC by
writing the proper values to the PSA bit and the PS bits
in the OPTION register. If the prescaler is assigned to
the RTCC, instructions writing to f1 (e.g. CLRF 1, or
BSF1,5, ... etc.) clear the prescaler.
The bit "RTS" (RTCC signal Source) in the OPTION
register determines, if f1 is incremented internally or
externally.
RTS=1: The clock source for the RTCC or the prescaler,
if assigned to it, is the signal on the RTCC pin.
Bit4 of the OPTION register (RTE) determines,
ifan increment occurs on the falling (RTE;1) or
rising (RTE;O) edge of the signal presented to
the RTCC pin.
RTS;O: The RTCC register or its prescaler, respectively, will be incremented with the internal
instruction clock (; F05C/4). The "RifE" bit in the
OPTION register and the RTCC pin are "don't
care" in this case. However, the RTCC pin
must be tied to VDD or Vss, whatever is convenient, to prevent unintended entering of test
modes and to reduce the current consumption
in low power applications.
As long as clocks are applied to the RTCC (from internal
or external source, with or without prescaler), f1 keeps
incrementing and just rolls over when the value "OFF16"
is reached. All increment pulses forf1 are delayed by two
instruction cycles. After writing to f1, for example, no
increment takes place for the following two instruction
cycles. This is independent if internal or external clock
source is selected. If a prescaler is assigned to the
RTCC, the output of the prescaler will be delayed by two
cycles beforef1 is incremented.

4-11

DS30015F-7

PIC®16C5x Series
OPERATIONAL REGISTER FILES (CONT.)

f2 PROGRAM COUNTER
The program counter generates the addresses for the
up to 2048 x 12 on-chip EPROM cells containing the
program instruction words (Figure 4).
Depending on the device type, the program counter and
its associated two-level hardware stack is 9 - 11 bits
wide.

TABLE 3: PROGRAM COUNTER/STACK WIDTH
Part #
PIC16C54/PIC16C55
PIC16C56
PIC16C57

PC width
9 bit
10 bit
11 bit

Stack width
9 bit
10 bit
11 bit

Incrementing the program counter when It is pointing to
the last address of a selected memory page is also
possible and will cause the program to continue in the
next higher page. However, the page pre-select bits in f3
will not be changed, and the next "GOTO", "CALL",
"ADDWF 2", "MOVWF 2" instruction will return to the,
previous page, unless the page pre-select bits have
been updated under program control. For example, a
"NaP" at location "1 FF"(page 0) increments the PC to
"200" (page 1). A "GOTO xxx" at "200" will return the
program to address "xxx" on page "0" (assuming that the
page preselect bits in f3 are '0".
Upon a RESET condition, page 0 is pre-selected while
the program counter addresses the last location in the
last page. Thus, a "GOTO" instruction at this location will
automatically cause the program to continue in page O.

StGk
The PIC16C5x series employs a two level hardware
push/pop stack (Figure 4).

The program counter is set to all "1 "s upon a RESET
condition. During program execution it is auto
incremented with each instruction unless the result of
that instruction changes the PC itself:
a)

"GOTO" instructions allow the direct loading of the
lower 9 program counter bits.
b) "CALL" instructions load the lower 8 bit of the PC
directly while the ninth bit is cleared to "0". The PC
value, incremented by one, will be pushed into the
stack.
c) "RETLW" instructions load the program counter
with the top of stack contents.
d) "MOvWF 2" allows the loading of computed addresses from the W register into the program counter.
e) "ADDWF 2" allows adding of relative addresses to
the current PC contents. In this case the PC will also
be incremented. That is, adding "000" to f2 results
in the PC value PC + 1.
In the cases d) and e), the ninth bit of the PC will always
be cleared to "0". Thus, indexed addressing is only
possible within the lower half of a program memory page
(addresses OOO-OFF, 200-2FF, 400-4FF, 600-6FF).
Program Memorv Page Select (PIC16C561
PIC16C57 Only):
The most significant program counter bit(s) will be
loaded with the contents of the page preselect bits in the
status register f3 upon execution of a "GOTO", "CALL",
"ADDWF 2", or "MOVWF 2" instruction.

DS30015F-8

CALL instructions push the current program counter
value, incremented by "1 ", into stack level 1. Stack level
1 is automatically pushed to level 2. If more than 2
subsequent "CALL"s are executed, only the most recent
two return addresses are stored.
For the PIC16C56 and PIC16C57, the page preselect
bits 0113 will be loaded into the most significant bits olthe
program counter. The ninth bit is always cleared to "0"
upon a CALL instruction. This means that subroutine
entry addresses have to be located always within the
lower half'of a memory page (addresses OOO-OFF, 2002FF, 400-4FF, 600-6FF). However, as the stack has
always the same width as the PC, subroutines can be
called from anywhere in the program.
RETLW instructions load the contents of stack level 1
into the program counter while stack level 2 gets copied
into level 1. If more than 2 subsequent "RETLW"s are
executed, the stack will be filled with the address previously stored in level 2. Forthe PIC16C56 and PIC16C57,
the return will be always to the page from where the
subroutine was called, regardless of the current setting
of the page pre-select bits in file register 13. Note that the
W register will be loaded with the literal value specified
in the RETLW instruction. This is in particular useful for
the implementation of "data" tables within the program
memory.

4-12

PIC®16C5x Series
OPERATIONAL REGISTER FILES (CONT.)

FIGURE 4: PROGRAM MEMORY ORGANIZATION

. - - - - - - - - GOTO, CALL, ADDWF 2, MOVWF 2 ............... FROM 13, BIT 6 (PIC16C57 ONLY)
. - - - - - - GOTO, CALL, ADDWF 2, MOVWF 2 ............... FROM 13, BIT 5 (PIC16C56/C57 ONLY)
, - - - -./GOTO ............................................. DIRECT FROM INSTRUCTION WORD
-\CALL, ADDWF 2, MOVWF 2 ......... ALWAYS "0"

r--

.--....l...--~,--.l--r-----I.--,

PC
(12)

l A10

A09

-./GOTO, CALL.. .... .... ...... DIRECT FROM INSTRUCTION WORD
\ADDWF 2, MOVWF 2 ........ FROM ALU
RETLW

CALL
STACK LEVEL 1

9-11 BIT
/

RETLW

Aoa IA07-AOO
1

I STACK LEVEL 2

CALL

000
MAX. EPROM ADDRESS FOR:
00

OFF

PAGE a

100

01
~

PAGE 1

I--

PAGE 2

PAGE 3

4-13

DS30015F-9

PIC®16C5x Series
OPERATIONAL REGISTER FILES (CONT.)

STATUS WORD REGISTER

This register contains the arithmetic status of the ALU,
the RESET status, and the page preselect bits for larger
program memories than 512 words (PIC16C56,
PIC16C57).
f3 can be altered under program control only via bit set,
bit clear, or MOVWF 3 instructions except for the "TO"
and "PD" bits.
For other instructions, affecting any status bits, see
section "Instruction Set Summary."

Time out and power down status bits (TO. POl
The "TO" and "PD" bits in the status register f3 can be
tested to determine if a RESET condition has been
caused by a watchdog timer time-out, a power-up condition, or a wake-up from SLEEP by the watchdog timer or
MCLR pin.
These status bits are only affected by events listed in
Table 4.

STATUS WORD REGISTER f3
(7)

PA2

(6)

PAl

(5)

(4)

PAol

TOI

(3)

(2)

(1)

(0)

I DC I C I

CARRY BIT:
For ADDWF and SUBWF instructions, this bit is set if there is
a carry out from the most significant bit of the resultant.
Note that a subtraction is executed by adding the two's
complement of the second operand. For rotate (RRF, RLF)
instructions, this bit is loaded with either the high or low
order bit of the source register.

- - - DIGIT CARRY BIT:
For ADDWF and SUBWF instructions, this bit is set if there is
a carry out from the 4th low order bit of the resultant.
' - - - - - - - - ZERO BIT:
Set if the result of an arithmetic or logic operation is zero.
' - - - - - - - - - POWER DOWN BIT:
Set to "I" during power up or by a CLRWDT command. This
bit is reset to "0" by a SLEEP instruction.
L -_ _ _ _ _ _ _ _ _

TIME-OUT BIT:
Set to "I" during power up and by the CLRWDT and SLEEP
command. This bit is reset to "0" by a watchdog timer time
out.

L _ _ _ _ _ _ _ _ _ _ _ _ _ PIC16C54/C55 : Two general purpose read/write bits

PIC16C56

: BIT 5 ." Page preselect bit
0= Page 0 (000 -IFF)
1 = Page 1 (200 - 3FF)
BIT 6 ... General purpose read/write bit

PIC16C57

: Two page preselect bits
00 = Page 0 (000
01 = Page 1 (200
10 = Page 2 (400
11 = Page 3 (600

- 1FF)
- 3FF)
- 5FF)
- 7FF)

L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ BIT 7: General purpose read/write bit

(reserved for future use)

DS30015F-l0

4-14

PIC®16C5x Series
OPERATIONAL REGISTER FILES (CONT.)
TABLE 4:
EVENTS AFFECTING PDITO STATUS BITS

f4 FILE SELECT REGISTER (FSR)

Event

Bits 0-4 select one of the 32 available file registers in the
indirect addressing mode (that is, calling for file to in any
of the file oriented instructions).
Bits 5-7 of the FSR are read-only and are always read as
"one"s.
If no indirect addressing is used, the FSR can be used
as a 5 bit wide general purpose register.

Power-up
WOTTimeoul
SLEEP instruction
CLRWOT instruction

X
0

1
1

PIC16C54/C55/C56

Remarks

No effect on PO

Note: A WOT timeout will occur regardless of the
status olthe TO bit. A SLEEP instruction will be
executed, regardless of the status of the PO bit.
Table 5 reflects the status of PO and TO after
the corresponding event.

PIC16C57 ONLY
Bit 5 and 6 of the FSR select the current data memory
bank (Figure 3).
The lower 16 bytes of each bank are physically identical
and are always selected when bit 4 of the FSR (in case
of indirect addressing) is "0", or bit 4 of the direct file
register address of the currently executing instruction is
"0" (e.g. MOVWF 08).
Only if bit 4 in the above mentioned cases is "1 ", bits 5
and 6 of the FSR select one of the four available register
banks with 16 bytes each.
Bit 7 is read-only and is always read as "one."

TABLE 5: PDITO STATUS AFTER RESET
TO

0
0

1
1

RESET was caused by
WOT wake-up from SLEEP
WOT time-out (not during SLEEP)
MCLR wake-up from SLEEP
Power-up
= Low pulse on MCLR input

Note: The PO and TO bit maintain their status (X)
until an event of Table 4 occurs. A low-pulse
on the MCLR input does not change the PO
and TO status bits.

Program Page Preselect (PIC16C56. PIC16C57
ONLY)
Bits 5-6 of the STATUS register are defined as PAGE
address bits PAO - PAl, and are used to preselect a
program memory page. When executing a GOTO,
CALL, MOVWF 2, or AOOWF 2 instruction, PAO - PAl
are loaded into bit A9-A 10 of the program counter,
selecting one of the available program memory pages.
The direct address specified in the instruction is only
valid within this particular memory page.
RETLW instructions do not change the page preselect
bits.
Upon a RESET condition, PAO-PA2 are cleared to "O"s.

4-15

DS30015F-ll

PIC®16C5x Series
I/O REGISTERS (PORTS)

I/O INTERFACING

The I/O registers can be written and read under program
control like any other register of the register file. However, "read" instructions (e.g. MOVF 6,W) read always
the I/O pins, regardless if a pin is defined as "input" or
"output." Upon a RESET condition, all I/O ports are
defined as "input" (= high impedance mode) as the I/O
control registers (TRISA, TRISB, TRISC) are all set to
"ones."
The execution of a "TRIS f" instruction with corresponding "zeros" in the W-register is necessary to define any
of the I/O pins as output.

The equivalent circuit for an I/O port bit is shown in
Figure 5. All ports may be used for both input and output
operations. For input operations these ports are nonlatching. Any input must be present until read by an input
instruction (e.g. MOVF 6, W). The outputs are latched
and remain unchanged until the output latch is rewritten.
For use as an output, the I/O control register
(TRISA,TRISB, TRISC) must be zero in order to enable
the output buffer. For use as an input the I/O control
register must be "one" in order to allow an external
device to drive the port high or low. This principle is the
same whether operating on individual pins or the entire
port. Any I/O pin can be programmed individually as
input, output or bidirectional pin.

f5 (PORT A)
4-bit I/O register. Low order 4 bits only are used (RAO RA3). Bit 4 - 7 are defined as "zeros."

f6 (PORT B)
8-bit I/O register.

f7 (PORT C)
PICt6C55/C57: 8-bit I/O register
PICt6C54/C56: General purpose register.

FIGURE 5: EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN
FROM - _
DATA
BUS

VDD

DATA
LATCH

_ _ CK

"Ci

"WRITE"

\----4

TO DATA BUS

110
PIN

"READ"

FROM - W-REGISTER

"TRIS f"

1--_-+_--'

I/O

CONTROL
LATCH
- - CK SET Q \ - - - - - - - - 1

---1

vs~

"RESET"

DS30015F-12

4-16

PIC®16C5x Series
I/O PROGRAMMING HINTS
BIDIRECTIONAL 1/0 PORTS

SUCCESSIVE OPERATIONS ON 1/0 PORTS

a) Some instructions operate internally as input followed by output operations. The BCF and BSF
instructions, for example, read the entire port into the
CPU, execute the bit operation, and re-output- the
result. Caution must be used when these instructions
are applied to a port where one or more pins are used
as input/outputs. As an example, a BSF operation on
bit 5 of f6 (Port B) will cause all eight bits of f6 to be
read into the CPU. Then the BSF operation takes
place on'bit 5 and f6 is re-output to the output latches.
If another bit of f6 is used as a bidirectional I/O pin
(say bit 0) and it is defined as an input at this time, the
input signal present on the pin itself would be read
into the CPU and re-written to the data latch of this
particular pin, overwriting the previous content. As
long as the pin stays in the input mode, no problem
occurs. However, if bit is switched into output mode
later on, the content of the data latch may now be
unknown.

Writing to an I/O port happens always at the end of an
instruction cycle, while for reading, the data have to be
valid as shown in Figure 20.
Therefore, care must be exercised if successive instructions operate on the same I/O port. The sequence of
instructions should be such to allow the pin voltage to
stabilize (load dependent) before the next instruction
which causes that file to be read into the CPU is
executed. Otherwise, the previous state of that pin may
be read into the CPU rather than the new state. When in
doubt, it is better to separate these instructions with a
NOP or an other instruction not accessing this I/O port.

OPERATION IN NOISY ENVIRONMENT
In noisy application environments, for example keyboards which are exposed to ESD (Electro Static Discharge), register contents can get corrupted due to
noise spikes.
The on-chip watchdog timer will take care of all situations involving program sequence "lock-ups." However, if a I/O control register gets corrupted, the program
sequence may still be executed properly although an
input pin may have switched unintentionally to an output.
In this case, the program would always read the same
value on this pin. This may result, for example, in a
keyboard "lock-up" situation without leading to a watchdog timer timeout. Thus, it is recommended to redefine
all I/O pins in regular time intervals (inputs as well as
outputs). The optimal strategy is to update the I/O control
register every time before reading or putting data out.

b) A pin actively outputting a "0" or "1" should not be
driven from external devices at the same time in
order to change the level on this pin ("wired-or",
"wired-and"). The resulting high output currents may
disturb an otherwise clean power supply, and proper
device functionality is not guaranteed.
For "wired-or" outputs (assuming negative logic), it is
recommended to use external pull-up resistors on
the corresponding pins. The pin should be left in
high-impedance mode, unless a "0" has to be output.
Thus, external devices can drive this pin "O"as well.
"Wired-abd" outputs can be realized in the same
way, but with external pull-down resistors and only
actively driving the "1" level from the PIC. The resistor values are user selectable, but should not force
output currents above the specified limits (see DC
Characteristics) .

4-17

DS30015F-13

PIC®16C5x Series
TRISA

GENERAL PURPOSE REGISTERS

PORT A (f5)

PIC16C54/C55/C56 :
f0816 - f1 F16:

Bit 0 - 3 only available. The corresponding I/O port (f5)
is only 4 bit wide.

are general purpose register files.

PIC16C57 ONLY:
f0816 - fOF16:

f1 016 - f1 F16:
f2016 - f2F16:
f3016 - f3F16:
f4016 - f4F16:
f5016 - f5F16:
f6016 - f6F16:
f7016 - f7F16:

TRISB

are general purpose register files which
are always selected, independent of bank
select.
general purpose register files in memory
bank 0
physically identical to fOO - fOF
general purpose register files in memory
bank 1
physically identical to fOO - fOF
general purpose register files in memory
bank 2
physically identical to 100 - 10
general purpose register files in memory
bank 3

1/0 CONTROL REGISTER FOR
PORT B (f6)

TRISC

1/0 CONTROL REGISTER FOR
PORTC (f7)

The I/O control registers will be loaded with the content
of the W register by executing of the TRIS f instruction.
A "1" in the I/O control register puts the corresponding
I/O pin into a high impedance mode. A "0" puts the
contents of file register f5, f6, or f7 , respectively, out on
the selected I/O pins.
These registers are "write-only" and are set to all "ones"
upon a RESET condition.

OPTION PRESCALER/RTCC OPTION

SPECIAL PURPOSE REGISTERS

1/0 CONTROL REGISTER FOR

WORKING REGISTER

Defines prescaler assignment (RTCC or WDT), prescaler value, signal source and signal edge for the RTCC.
The OPTION register is "write-only" and is 6 bit wide.
By executing the "OPTION" instruction, the contents of
the "W" register will be transferred to the option register.
Upon a RESET condition, the option register will be set
to all "ones."

Holds second operand in two operand instructions and/
or supports the internal data transfer.

OPTION REGISTER
5

I RTS I RTE I PSA I PS2 I PS1 Ipso
/

\
PRESCALER

VALUE

RTCC RATE WDT RATE
1 : 2
1 : 4
: 8

0
0
0
0

0
0

: 16

1
1
1

0
0

: 32
: 64

1
0

: 1
: 2
: 4
:8

: 128

: 16
: 32
: 64

: 256

: 128

' - - - - - - - - PRESCALER ASSIGNMENT BIT:
0 .... RTCC
1 .... WDT
' - - - - - - - - - - - RTCC SIGNAL EDGE:
0 .... INCREMENT ON LOW-TO-HIGH TRANSITION ON RTCC PIN
1 .... INCREMENT ON HIGH-TO-LOW TRANSITION ON RTCC PIN
' - - - - - - - - - - - - - - RTCC SIGNAL SOURCE:
o .... INTERNAL INSTRUCTION CYCLE CLOCK (CLKOUT)
1 .... TRANSITION ON RTCC PIN

DS30015F-14

4-18

PIC®16C5x Series
RESET CONDITION

dog timer. Thus, a prescaler assignment for the RTCC
means that there is no prescalerfor the watchdog timer,
and vice versa.
The PSA and PSO-PS2 bits in the OPTION register
determine the prescaler assignment and ratio.
The prescaler will be cleared whenever the circuit to
which it is assigned is being written to. That is, when
assigned to the RTCC, all instructions writing to the
RTCC (e.g. CLRF 1, MOVWF 1, BSF 1,x ....etc.) will
clear the prescaler.

A RESET condition can be caused by applying power to
the chip (power-up), pulling the MCLR input "low", or by
a Watchdog Timer Timeout. The device will stay in
RESET as long as the oscillator start-up timer (OST) is
active or the MCLR input is "low."
During a RESET condition the PIC function is defined
as:
The oscillator is running, or will be started (powerup or wake-up from SLEEP)
All 110 port pins (RAO - RA3, RBO - RB7, RCORC7) are put into the high-impedance state (tristated) by setting the "TRIS" registers to all "ones"
(= input mode).
The Program Counter is set to all "ones"
The OPTION register is set to all "ones"
The Watchdog Timer and prescaler are cleared
The upper three bits (page select bits) in the
Status Register (f3) are cleared to "zero."
"RC· devices only: The "CLKOUT" signal on the
OSC2 pin is held at a"low" level.

PRESCALER PROGRAMMING CAUTIONS
The prescaler assignment is fully under software control. Thus, it can be changed "on the fly" during program
execution. To avoid an unintended device RESET, the
following instruction sequence has to be executed when
changing the prescaler assignment from RTCC to WDT:
1.MOVLW B'xxxOOxxx'
2.0PTION
3.CLRF 1
4.MOVLW B'xxxx1 x1 0'
5.0PTION

PRESCALER

;Select internal RTCC.clock
;Clear RTCC and prescaler

;Select WDT prescaler with
ratio:<: 1:4
Step 1 and 2 are only required if an external RTCC
source is used with a clock period less than Tcy +20ns.
In all other cases, only steps 3-5 are necessary.
No precaution is required when changing the prescaler
assignment from WDT to RTCC.

An a-bit counter is available as prescaler for the RTCC,
or as post-scaler for the watchdog timer, respectively
(Figure 6). For simplicity, this counter is being referred to
as "prescaler" throughout this data sheet. Note that
there is only one prescaler available which is mutually
exclusively shared between the RTCC and the watch

FIGURE 6: BLOCK DIAGRAM RTCCIWDT PRESCALER
CLKOUT (=FoscI4)

0-?
PIN

OATA BUS

0
M

RTE

u
x
0

RTS
PSA

WATCH
DOG
TIMER

WDT ENABLE
EPROM FUSE
NOTE: RTE, RTS, PSA, PSO-PS2
ARE BITS IN THE OPTION REGISTER

WDT
TIMEOUT

4-19

DS30015F-15

PIC®16C5x Series
BASIC INSTRUCTION SET SUMMARY

NOTES TO TABLE 6

Each PIC instruction is a t 2-bit word divided into an OP
code which specifies the instruction type and one or
more operands which further specify the operation olthe
instruction. The PIC instruction set summary in Table 6
lists byte-oriented, bit-oriented, and literal and control
operations.

Notel: The 9th bit of the program counter will be forced
to a "zero" by CALL, MOVWF 2 , or ADDWF 2
instructions.
Note 2: When an 1/0 register is modified as a function of
itself ( e.g. MOVF 6,1 ), the value used will be
that value present on the pins themselves. For
example, a tristated pin which data latch is "1"
but is driven low by an external device, will be
relatched in the low state.
Note 3: The instruction "TRIS f" , where f = 5 or 6 or 7
causes the contents of the W register to be
written to the tristate latches of the specified file
(port). A "one" forces the pin to a high impedance state and disables the output buffers.
Note 4: If this instruction is executed on file register fl
(and, where applicable, d=I), the prescalerwill
be cleared if assigned to the RTCC.

For byte-oriented instructions, "f" represents a file register designator and "d" represents a destination designator. The file register designator specifies which one of
the 32 PIC file registers is to be utilized by the instruction.
Forthe PICI6C57, bit 5 and 6 in the FSR determine the
selected register bank.
The destination designator specifies where the result of
the operation is to be placed. If "d" is zero, the result is
placed in the W register. If "d" is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, "b" represents a bit field
designator which selects the number of the bit affected
by the operation, while "f" represents the number of the
file in which the bit is located.
For literal and control operations, "k" represents an eight
or nine bit constant or literal value.
All instructions are executed within one single instruction cycle, unless a conditional test is true or the program
counter is changed as a result of an instruction. In this
case, the execution takes two instruction cycles. One
instruction cycle consists of four oscillator periods. Thus,
for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 J..lsec. If a conditional test is true
or the program counter is changed as a result of an
instruction, the instruction execution time is 2 J..lsec.

DS30015F-16

4-20

PIC®16C5x Series
TABLE 6: INSTRUCTION SET SUMMARY
(11-6)

BYTE ·ORIENTED FILE REGISTER OPERATIONS
Instruction-Binary (Hex)
0000
0000
0000
0000
0000
0000
0001
0001
0001
0001
0010
0010
0010
0010
0011
0011
0011
0011

0000
0011
0100
0111
10dl
lldl
OOdl
01dl
10dl
lldl
OOdl
01dl
10dl
lldl
OOdl
01dl
10dl
lldl

0000
ffff
0000
Iffl
Iffl
ffff
ffff
ffff
Iffl
Iffl
ffff
Iffl
Iffl
Iffl
Iffl
Iffl
Iffl
ffff

000
021
040
061
081
OCI
101
141
181
lCI
201
241
281
2CI
301
341
381
3CI

Name

[

Mnemonic, Operands

No Operation
MoveWtol
ClearW
Clearf
Substract WIrom I
Decrement I
Inclusive OR Wand I
ANDWandl
Exclusive OR Wand I
Add W and I
Move I
Complement I
Increment I
Decrement I,Skip il Zero
Rotate right I
Rotate left I
Swap halves I
Increment I,Skip il zero

NOP
MOVWF
CLRW
CLRF
SUBWF
DECF
IORWF
ANDWF
XORWF
ADDWF
MOVF
COMF
INCF
DECFSZ
RRF
RLF
SWAPF
INCFSZ

I
I
I, d
I, d
I, d
I, d
I, d
I, d
I, d
I, d
I, d
I, d
I, d
I, d
I, d
I, d

0100
0101
0110
0111

bbbi
bbbl
bbbl
bbbl

Iffl
ffff
ffff
Iffl

(Hex)
4bl
5bl
6bl
7bl

Name

Mnemonic,Operands

Bit Clear I
Bit Set I
Bit Test I,Skip il Clear
Bit Test I, Skip il Set

BCF
BSF
BTFSC
BTFSS

I, b
I, b
I, b
I, b

Instruction-Binary (Hex)
0000
0000
0000
0000
1000
1001
101 k
1100
1101
1110
1111

0000
0000
0000
0000
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk

0010
0011
0100
Olff
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk

002
003
004
001
8kk
9kk
Akk
Ckk
Dkk
Ekk
Fkk

Name

Load OPTION register
Go into standby mode
Clear Watchdog timer
Tristate port I
Return,place Literal in W
Call subroutine
Go To address (k is 9 bit)
Move Literal to W
Incl. OR Literal and W
AND Literal and W
Excl. OR Literal and W

OPTION
SLEEP
CLRWDT
TRIS
RETLW
CALL
GOTO
MOVLW
IORLW
ANDLW
XORLW

4
1,2,4
2,4
2,4
2,4
2,4
1,2,4
2,4
2,4
2,4
2,4
2,4
2,4
2,4
2,4

(7-5)

(4 - 0)

I b(BIT#) I

I(FILE#)

Operation

2,4
2,4

None
None
None
None

1 ---71(b)
Test bit (b) in file (I): Skip il clear
Test bit (b) in lile (I): Skip il set

OPCODE

[

Status affected Notes

a---71(b)

Operation

[

1,4

(11-8)

[

Mnemonic,Operands

None
None
Z
Z
C, DC,Z
Z
Z
Z
Z
C,DC,Z
Z
Z
Z
None
C
C
None
None

OPCODE

(11-8)

LITERAL AND CONTROL OPERATIONS

f(FILE #)

Status Affected Notes

W---71
0---7W
0---71
I-W---7d[f+W+l---7d}
1-1 ---7d
Wvl---7d
W&I---7d
Wffi 1---7d
W+I---7d
1---7d
1---7d
1+ 1---7d
1- 1 ---7 d, skip il zero
I(n) ---7 d(n-l), C ---7 d(7), 1(0) ---7 C
I(n) ---7 d(n+ 1), C ---7 d(O), 1(7) ---7 C
1(0-3) B 1(4-7) ---7 d
1+1 ---7 d, skip il zero

[

(4 - 0)

(5)

Operation

BIT· ORIENTED FILE REGISTER OPERATIONS
Instruction-Binary

OPCODE

(7 - 0)

k (LITERAL)

[

Status affected Notes

None
TO,PD
0---7 WDT (and prescaler, il assigned) TO,PD
W---7 I/O control register I
None
None
k ---7 W, Stack ---7 PC
PC+l .... Stack,k---7PC
None
k ---7 PC (9 bits)
None
k---7W
None
kvW---7W
Z
k&W---7W
Z
kffiW---7W
Z
W---7 OPTION register

a---7 WDT, stop oscillator

I
k
k
k

k
k
k
k

3
1

Notes: See previous page

4-21

DS30015F-17

PIC®16C5x Series
WATCHDOG TIMER (WDT)
The watchdog timer is realized as a free running on-chip
RC oscillator which does not require any external components. That means that the WOT will run, even if the
clock on the OSC1/0SC2 pins of the device has been
stopped, lor example, by execution 01 a SLEEP instruction. A WOT timeout generates a device RESET condition. The WOT can be permanently disabled by programming a "zero" into a special EPROM fuse which is
not part 01 the normal program memory EPROM. The
PIC development tools "PIC-ICE" and "PICPRO" provide special commands to program this fuse.

WDTPERIOD
The WOT has a time-out period of approx. 18 ms. If
longer time-out periods are desired, a prescaler with a
division ratio of up to 1:128 can be assigned to the WOT
under software control by writing to the OPTION register. Thus, time-out periods up to 2.5 seconds can be
realized.
The "CLRWOT" and "SLEEP" instructions clear the
WOT and the prescaler, if assigned to the WOT, and
prevent it from timing out and generating a device
RESET condition.
The status bit "TO" in file register 13 will be cleared upon
a watchdog timer timeout.
The WOT period is a function of the supply voltage,
operating temperature, and may also vary from unit to
unit due to variations in the manufacturing process.
Please refer to the ELECTRICAL CHARACTERISTICS
section and Figures 21, 22 lor more details.

SPECIAL WDT PROGRAMMING CAUTIONS:
1. PIC16C54/C55:
If no prescaler is assigned to the WOT, its typical timeout period is 18 ms. However, a CLRWOT orSLEEP
instruction has to occur before 1/2 01 the time-out
period (Le. 9 ms) is over. Otherwise, the CLRWOT or
SLEEP instruction itself will cause a device RESET.
If the WOT has a prescaler assigned, the full WOT
period is available lor a CLRWOT instruction.
This precaution is not necessary for the PIC16C56
and PIC16C57.
2. In a noisy application environment the OPTION register can get corrupted. The OPTION register should
be updated at regular intervals.
It should also be taken in account that under worst
case conditions (VDD = Min., Temperature = Max.,
max. WOT prescaler) it may take several seconds
belore a WOT timeout occurs.

DS30015F-18

OSCILLATOR CIRCUITS
OSCILLATOR TYPES
The PIC16C5x series is available with 4 different oscillator circuits. On windowed devices, a particular oscillator circuit can be selected by programming the configuration EPROM accordingly. The PIC developmenttools
(e.g. PIC-ICE, PICPRO) provide special commands to
select the desired oscillator configuration.
On OTP and aTP devices, the oscillator configuration is
determined by the factory and the parts are tested only
to the according specifications.

CRYSTAL OSCILLATOR
The PIC16C5x-XT, -HS needs a crystal or ceramic
resonator connected to the OSC1 and OSC2 pins to
establish oscillation (Fig. 7). Note that the series resistor
Rs is only required for the "HS" oscillator.

RC OSCILLATOR
For timing uncritical applications the "RC" device option
offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor
(Rext) and capacitor (Cext) values, and the operation
temperature. In addition, there will be variation from unit
to unit due to normal process variation. Figure 9 shows
how the RIC combination is connected tothe PIC16C5x.
Some typical values for the oscillator frequency at given
Rand C values and supply voltages are listed in Table
7. For Rext values below 2.2 kOhm, the oscillator
operation will become unstable, or stop completely. For
very high Rext values (e.g. 1 MOhm), the oscillator
becomes sensitive to noise and humidity. Thus, we
recommend to keep Rext between 5 kOhm and 100
.
kOhm.

TABLE 7: RC OSCILLATOR FREQUENCIES
Rext

Cext

voo

Fosc

5kOhm
5kOhm
5kOhm
10 kOhm
10 kOhm
100 kOhm

o pF

5.0V
6.0 V
3.5 V
5.0V
5.0V
3.5V

4.0 MHz
2.2 MHz
2.5 MHz
480 kHz
245 kHz
30 kHz

Rext. min.

4-22

20pF
20 pF
130 pF
290pF
300 pF

=2.2 kOhm, Cext. min. = 0 pF

1= 25°

(see text)

PIC®16C5x Series
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons.
Figure 10 shows the typical dependency of the oscillator
frequency from VDO for given RexVCext values. Figure
11 shows the frequency as a typical function of the

operating temperature with given R, C, and VOD values.
Note that this graph is normalized to 25' C.
The oscillator frequency, divided by 4, is available on the
OSC2/CLKOUT pin, and can be used for test purposes
or to synchronize other logic (see Fig. 20 for timing).

FIGURE 7: CRYSTAL OPERATION (OR CERAMIC RESONATOR) (HS, XT TYPES ONLY)
OS~I

f-_------~.

CJ XTAL

....OSC2

PIC16C5x

r~~ ,_J:

~
("HS" TYPE ONLY)
C
no

- -.- - - - ,

LTJ

,~SLEEP

IRT

-_.---

4-47
----------_

.. -

-._._-- ..

DS33013A-13

PIC1654S
OSCILLATOR OPTIONS (TYPICAL CIRCUITS) (Cont.)
CRYSTAL INPUT OPERATION
20pF

r--[

1-10M

t
~
~

)

c::::J XTAL' PARALLEL
- [ - RESONANT)

1--l~-+-~'VVv----.c,

OSC1(PIN16)

OSC2 (PIN 15)

20pF

, Or ceramic resonator

EXTERNAL CLOCK INPUT OPERATION
VDO

,,~1

CLOCK FROM
""-_
EXTERNAL SYSTEM --V~-~o----~) OSC1 (PIN 16)
NC------~

OSC2 (PIN 15)

PRIMARY SUPPLY CURRENT AT SELECTED TEMPERATURES
PIC1654S
PIC1654S-1
Characteristic
Primary Supply Current

Sym

Typ

Max

Typ

Max

Units

IDD

40
35
24
22

54
50
45
42

48
44
39
36
30

58
54
49
46
40

rnA
rnA
rnA
rnA
rnA

DS33013A-14

PIC1654S-H

4-48

Conditions
-40'C, All I/O pins at VDD
O'C, All 1/0 pins at VDD
70'C, All I/O pins at VDD
85T, All 1/0 pins at VDD
11 O'C, All 1/0 pins at VDD

PIC1654S
MASTER CLEAR (TYPICAL CIRCUIT)
VDD
Rext

Cext

R::; lOOK

b
y

Typical Values
R = lOOK
C =O.l~f

MCLR (PIN 4)
O.l~F

The MCLR pin must be pulsed low for a minimum of one
complete instruction cycle (tCY) for the master clear function
to be guaranteed, assuming that power is applied and the
oscillator is running. For initial power application, a delay is
required for the external oscillator time base element to start
up before "M"eIR is brought high. To achieve this, an
external RC configuration, as shown, can be used. This
provides approximately a 10ms delay (assuming VDD is
applied as a step function), which may be insufficient for
some time base elements. Consult the manufacturer of the
time base element for the specific start-up times.

OUTPUT SINK CURRENT GRAPH (TYPICAL)
20

15
IOL
(mA)

~
5

.J>V
/'fI'

.-- ---

1.0

2.0

- -

VDD=5.0V

3.0

VOL (volts)
IOLVS VOL
TA = 25'C, VDD = 5.0V

4-49

DS33013A-15

PIC1654S
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.

PART NUMBERS
PIC1654S· H /P X

y
Y

Pattern

Package

Temperature
Range

Device

Notes:

DS33013A-16

3-Digil

P
'SO
'L

Pattern Code

Plaslic DIP
SOIC (Gull Wing Lead)
PLCC (J Lead)

Blank O°C 10 +70°C
J -40°C 10 +85°C
H -4Q°C to + 110°C
PIC1654S

'SOIC and PLCC available in Commercial Temperature (O°C to +70°C) only

4-50

PIC1655

Microchip

8-Bit Microcontroller
FEATURES
PIN CONFIGURATION

User programmable
Intelligent controller for stand-alone applications
32 8-bit RAM registers
512 x 12-bit program ROM
• Arithmetic Logic Unit
Real Time Clock/Counter
External or RC input oscillator mask option
Self-contained oscillator
Access to RAM registers inherent in instruction
Wide power supply operating range (4.5V to 7.0V)
Available in three temperature ranges: O' to 70'C,
_40' to 85T and _40' to 11 O'C
4 inputs, 8 outputs, 8 bi-directional 1/0 lines
• 2 level stack for subroutine nesting

28 LEAD DUAL INLINE
Top View
-> RTCC
Vdd
Vxx
Vss
TEST
<--->RAO
<--->RA1
<--->RA2
<--->RA3
<--->RBO
<--->RB1
<--->RB2
<-7 RB3
<-7 RB4

DESCRIPTION
The PIC®1655 microcontroller is an MOSILSI device
containing RAM, 1/0, and a central processing unit as
well as customer-defined ROM on a single chip. This
combination produces a low cost solution for applications which require sensing individual inputs and controlling individual outputs. Keyboard scanning, display
driving, and other system control functions can be done
at the same time due to the power of the 8-bit CPU.

Extensive hardware and software support is available to
aid the user in developing an application program and to
verify performance before committing to mask tooling.
Programs can be assembled into machine language
using PICALC, a powerful macroassembler. PICALC is
available in a MS-DOS version that can be run on an
IBM PC or compatible computer system. Once the application program is developed several options are
available to insure proper performance. The PIC's
operation can be verified in any hardware application by
using the PIC1664. The PIC1664 is a ROMless PIC
microcomputer with additional pins to connect external
PROM or RAM and to accept HALT commands. The
PFD1000 Field Demo System is available containing a
PIC1664 with sockets for erasable CMOS PROM's.
Finally, the PICES II (PIC In-Circuit Emulation System)
provides the user with emulation and debugging capability in either a stand-along mode or operation as a
peripheral to a larger computer system. Easy program
debugging and changing is facilitated because the user's
program is stored in RAM. With these development
tools, the user can quickly and confidently order the
masking of the PIC's ROM and bring his application into
the market.

The internal ROM contains a customer-defined program
using the PIC's powerful instruction set to specify the
overall functional characteristics of the device. The 8-bit
input/output registers provide latched lines for interfacing to a limitless variety of applications. The PIC can be
used to scan keyboards, drive displays, control electronic games and provide enhanced capabilities for
motor controls, telecommunication equipment, radios,
television, consumer appliances, industrial timing and
control applications. The 12-bit instruction word format
provides a powerful yet easy to use instruction repertoire
emphasizing single bit manipulation as well as logical
and arithmetic operations using bytes.
The PIC1655 is fabricated with N-Channel Silicon Gate
technology resulting in a high performance product with
proven reliability and production history. Only a single
wide range power supply is required for operation, and
an on-chip oscillator provides the operating clock with
only an external RC network (or buffered crystal oscillator signal, for greater accuracy) to establish the frequency. Inputs and outputs are TTL-compatible.

MCLR
RC7 <--->
RC6 <--->
RC5H
RC4 <--->
RC3H
RC2 <--->
RC1 <--->
RCOH
RB7H
RB6 <--->
RB5 <--->

4-51

DS30006B-1

PIC1655
ARCHITECTURAL DESCRIPTION
The firmware architecture of the PIC series microcontroller is based on a register file concept with simple yet
powerful commands designed to emphasize bit, byte,
and register transfer operations. The instruction set
also supports computing functions as well as these
control and interface functions.
Internally, the PIC is composed of three functional
elements connected together by a single bidirectional
bus: the Register File composed of 32 addressable 8bit registers, an Arithmetic Logic Unit, and a userdefined Program ROM composed of 512 words each 12
bits in width. The Register File is divided into two
functional groups: operational registers and general
registers. The operational registers include, among
others, the Real Time Clock Counter (PC), the Status
Register, and the 110 Registers. The general purpose
registers are used for data and control information
under command of the instructions.

The Arithmetic Logic Unit contains one temporary working register or accumulator (W Register) and gating to
perform Boolean functions between data held in the
working register and any file register.
The Program ROM contains the operational program for
the rest of the logic within the controller. Sequencing of
microinstructions is controlled via the Program Counter
(PC) which automatically increments to execute in-line
programs. Program control operations can be performed
by Bit Test and Skip instructions, Jump instructions, Call
instructions, or by loading computed addresses into the
PC. In addition, an on-Chip two-level stack is employed
to provide easy to use subroutine nesting. Activating the
MCLR input on power up initializes the ROM program to
address 7778.

PIC1655 BLOCK DIAGRAM

FILE SELECT
REGISTER
(F4)

GENERAL
REGISTER
FILES (F10·F37)

RAO-3

RBO-7

8
RCO-7

PROGRAM
ROM 512 x 12

0530006B-2

4-52

PIC1655
PIN FUNCTION TABLE
Name

Function

OSC1 (Input)

Oscillator input. This signal can be driven by an external oscillator if a precise frequency
of operation is required or an external RC network can be used to set the frequency of
operation of the internal clock generator. This is a Schmitt trigger input.

RTCC (Input)

Real Time Clock Counter. Used by the microprogram to keep track of elapsed time
between events. The RTCC register increments on falling edges applied to this pin.
This register can be loaded and read by the program. This is a Schmitt trigger input.

RAO-3 (input)

4 input lines.

RBO-7 (output)

8 output lines.

RCO-7 (input/output)

8 user programmable input/output lines.

MCLR (input)

Master Clear. Used to initialize the internal ROM program to address 7778 and latch
all 1/0 register high. Should be held low at least 1 ms past the time when the power
supply is valid. This is a Schmitt trigger input. RAM registers are not initialized by
Master Clear

CLKOUT (output)

A signal derived from the internal oscillator. Used by external devices to synchronize
themselves to PIC timing.

TEST

Used for testing purposes only. Must be grounded for normal operation.

Voo

Primary power supply.

Vxx

Output Buffer power supply. Used to enhance output current sinking capability.

Vss

Ground.

4-53

08300068-3

PIC1655
REGISTER FILE ARRANGEMENT
File
(Octal)

Function

Nol a physically implemented register. FO calls for the contents of the File Select Register (low order 5 bits) to be used to select a
file register. FO is thus useful as an indirect address pointer. For example, W+ FO ~ Wwill add the contents of the file register
pointed to by the FSR (F4) to Wand place the resuH in W.

Real Time Clock Counter Register. This register can be loaded and read by the microprogram. The RTCC register keeps counting
up after zero is reached. The counter increments on the falling edge of the input RTCC. However, if data is being stored in the
RTCC register simultaneously with a negative transition on the RTCC pin, the RTCC register will contain the new stored value and
the external transition will be ignored by the microcomputer.

Program Counter (PC). The PC is automatically incremented during each instruction cycle, and can be written into under program
control (MOVWF F2). The PC is nine bits wide, but only its low order 8 bits can be read under program control.

Status Word Register. F3 can be altered under program control only via b~ set, b~ clear, or
MOVWF F3 instruction.
(7)
(4)
(3)
(2)
(1)
(6)
(5)

I1
C (Carry):

DC(Dig~

Carry):
Z(Zero):
Bits: 3-7

I z I DC I

(0)

For ADD and SUB instructions, this bit is set if there is a carry out from the most significant bit
of the resuHant.
For ROTATE instructions, this bit is loaded with either the high or low order bk of the source.
For ADD and SUB instructions, this bit is set if there is a carry out from the 4th
low order bit of the resultant.
Set if the result of an Arithmetic operation is zero.
These bits are defined as logic ones.

File Select Register (FSR). Low order 5 bits only are used. The FSR is used in generating effective file register addresses under
program control. When accessed as a directly addressed file, the upper 3 bits are read as ones.

Input Register A (AO-A3) (M - A7 defined as zeros).

Output Registers B (BO·B7).

1/0 Register C (CO-C?).

Fl0sF37s

General Purpose Registers.

BASIC INSTRUCTION SET SUMMARY

Each PIC instruction is a 12-bit word divided into an OP
code that specifies the instruction type and one or more
operands specifying the operation of the instruction.
The following PIC instruction summary lists byte-oriented, bit-oriented, and literal and control operations.

For bit oriented instructions, "b" represents a bit field
designator that selects the number of the bit affected by
the operation, while "f" represents the number of the file
in which the bit is located.

For byte-oriented instructions, "f" represents a file register designator and "d" represents a destination designator. The file register designator specifies which one of
the 32 PIC file registers is to be utilized by the instruction.
The destination designator specifies where the result of
the operation performed by the instruction is to be
placed. If "d" is zero, the result is placed in the PIC W

08300068-4

For literal and control operations, "k" represents an
eight- or nine-bit constant or literal value.
For an oscillator frequency of 1 MHz the instruction
execution time is 4l1sec, unless a conditional test is true
or the program counter is changed as a result of an
instruction. In these cases, the instruction execution
time is 8 I1sec.

4-54

® 1990 Microchip Technology Inc.

PIC1655
BYTE-ORIENTED FILE REGISTER OPERATIONS

(11-6)

For d = 0, I ~ W (pICAL accepts d = 0 or d = W in the mnemonic)

(5)

OPCODEI

(4-0)

d I

I(FILE#) I

d =I, I ~ I (il d is omitted, assembler assigns d =1).
INSTRUCTION·

MNEMONIC,

NAME

BINARY (Octal)

STATUS

OPERATION

OPERANDS

AFFECTED

000

(0000)

No Operation

NOP

000

Iff

(0040)

Move W to I (Note 1)

MOVWF

000

001

000

ClearW

CLRW

001

Iff

000
Ifl

(0100)

000

(0140)

Clear I

CLRF

O~I

000

010

dff

(0200)

Subtract W Irom I

SUBWF

I,d

I-W~d [I + IN + 1~dl

C,DC,Z

000

011

dll

000

100

dff

000

101

dff

000

110

dff

Iff
Iff
Iff
Iff
Ilf

000

111

dff

None
W~I

None

O~W

(0300)

Decrement I

DECF

I,d

I-l~d

(0400)

Inclusive OR Wand I

10RWF

I,d

Wvf~d

(0500)

ANDbW and I

ANDWF

W·I~d

(0600)

Exclusive OR Wand I

XORWF

I,d
I,d

W(jll~d

Iff

(0700)

AddWandl

ADDWF

I,d

W+F~d

C,DC,Z

(1000)

Move I

MOVF

I,d

I~d

(1100)

Complement I

COMF

I,d

I~d

(1200)

Increment I

INCF

I,d

f+l~d

DECFSZ

I,d

I - 1~d, skip il Zero

None

RRF

I,d

I(n)~d(n-l), C~d(7), I(O)~C

RLF

I,d

I(n)~d(n

001

000

dff

001

dff

001

011

dff

Iff
Iff
Iff

001

011

dff

ffl

(1300)

001

100

dlf

Iff

(1400)

Decrement I, Skip to Zero
Rotate Right I

001

101

dff

ffl

(1500)

Rotate Left I

+ I), C~d(O),

1(7)~C

001

110

dff

001

111

dff

Iff
Iff

H 1(4-7)~d

(1600)

Swap halves I

SWAPF

I,d

1(0-3)

(1700)

Increment I, Skip il Zero

INCFSZ

I,d

I + l~d, skip il Zero
(11-8)

BIT-ORIENTED FILE REGISTER OPERATIONS

None
None
(7-5)

(4-0)

I OP CODE I b (BIT #) I I(FILE #) I
INSTRUCTION·

MNEMONIC,

NAME

BINARY (Octal)

OPERATION

OPERANDS

STATUS
AFFECTED

(2000)

Bit Clear I

BCF

I,b

O~I(b)

None

(2400)

Bit Set I

BSF

I,b

1~I(b)

None

bff

Iff
Iff
Iff

(3000)

Bit Test I, skip il Clear

BTFSC

I,b

Bit Test I(b): skip il clear

None

bff

Iff

(3400)

Bit Test I, skip il Set

BTFSS

I,b

Bit Test I(b): skip il set

None

010

Obb

bff

010

lbb

bff

011

Obb

011

lbb

(11-8)

(7-0)

OPCODE

k (LITERAL)

LITERAL AND CONTROL OPERATIONS

INSTRUCTION·

MNEMONIC,

NAME

BINARY (Octal)

OPERANDS

OPERATION

STATUS
AFFECTED

100
100

Okk

kkk

(4000)

Return and place Literal in W

RETLW

k~w, Stack~PC

None

lkk

kkk

(4400)

Call subroutine (Note 1)

CALL

PC + 1~Stack, k~PC

None

101

kkk

(5000)

Go to address (k is 9 bits)

GOTO

k~PC

None

110

Okk

kkk

(6000)

Move Literal to W

MOVLW k

k~W

None

110

ikk

kkk

(6400)

Inclusive OR Literal and W

10RLW

kvW~W

111

okk

kkk

(7000)

AND Literal and W

ANDLW k

k·W~W

111

lkk

kkk

(7400)

Exclusive OR Literal and W

XORLW k

kffiW~W

NOTES:
1. The 9th bit 01 the program counter in the PIC is zero or a CALL and a MOVWF F2. Therelore, subroutines must be located in program
memory locations 0-3778. However, subroutines can be called Irom anywhere in the program memory since the Stack is 9 bits wide.
2. When an 1/0 register is modilied as a lunction 01 itsell, the value used will be that value present on the pins. For example, an output
pin which has been latched high but is driven low by an external device, will be relatched in the low state. See example 2 on page 7.

4·55

DS30006B-5

PIC1655
the pin can be connected directly to a TTL gate input.
When inputting data through an 1/0 Port, the port latch
must first be set to a high level under program control.
This turns off 02, allowing the TTL open collector device
to drive the pad, pulled up by 01, which can source a
minimum of lOOIlA. Care, however, should be exercised when using open collector devices due to the
potentially high TTL leakage current which can exist in
the high logic state.

1/0 INTERFACING
The equivalent circuit for an 1/0 port bit is shown below
as it would interface with either the input of a TTL device
(PIC is outputting) or the output of an open collector TTL
device (PIC is inputting). Each 1/0 port bit can be
individually time multiplexed between input and output
functions under software control. When outputting
through a PIC 1/0 Port, the data is latched at the port and

TYPICAL INTERFACE-BIDIRECTIONAL 1/0 LINE
-

VDD
Vxx
DN
(INTERNAL
DATA BUS)

WRITE
(INTERNAL
SIGNAL)

c
-

~-?=

READ
(INTERNAL
SIGNAL)

PIC I/O BIT

--.J

I
I TTL DEVICE OUTPUT
(OPEN-COLLECTOR)
- - - -

Note: 01 can be disconnected via mask option to form an "open drain" pin.

Bidirectional 1/0 Ports
The bidirectional ports may be used for both inut and
output operations. For input operations these ports are
non-latching. Any input must be present until read by an
input instruction. The outputs are latched and remain
unchanged until the output latch is rewritten. For use as
an input port the output latch must be set in the high
state. Thus the external device inputs to the PIC circuit
by forcing the latched output line to the low state or
keeping the latched output high. This principle is the
same whether operating on individual bits or the entire
port.
Some instructions operate internally as input followed by
output operations. The BCF and BSF instructions, for

DS30006B-6

example, read the entire port into the CPU, execute the
bit operation, and re-output the result. Caution must be
used when using these instructions. As an example a
BSF operation on bit 5 of F7 (port RC) will cause all eight
bits of F7 to be read into the CPU. Then the BSF
operation takes place on bit 5 and F7 is re-output to the
output latches. If another bit of F7 is used as an inut (say
bit 0) then bit 0 must be latched high. If during the BSF
instruction on bit 5 an external device is forcing bit 0 to
the low state then the input/output nature of the BSF
instruction will leave bit 0 latched low after execution. In
this state bit 0 cannot be used as an input until it is again
latched high by the programmer. Refer to the examples
below.

4-56

PIC1655
Input Only Port: (Port RA)

Successive Operations on Sidirectionall/O
Ports

The input only port of the PIC1655 consists of the four
LSB's of F5 (port RA). An internal pull-up device is
provided so that external pull-ups on open collector logic
are unnecessary. The four MSB's of this port are always
read as zeros. Output operations to F5 are not defined.
Note that the BTFSC and BTFSS instructions are input
only operations and so can be used with F5. Also, file
register instructions which leave the results in W can be
used.

Care must be exercised if successive instructions
operate on the same 1/0 port. The sequence of instructions should be such to allow the pin voltage to stabilize
(load dependent) before the next instruction which causes
that file to be read into the CPU (MOVF, BIT SET, BIT
CLEAR, and BIT TEST) is executed. Otherwise, the
previous state of that pin may be read into the CPU
rather than the new state. This will happen iftpd(Seel.O
Timing Diagram) is greater than 1/4tcy (min). When in
doubt, it is better to separate these instructions with a
NOP or other instruction.

Output Only Port: (Port RS)
The output only port of the PIC1655 consists of F6 (port
RB). This port contains no input circuitry and is therefore
not capable of instructions requiring an input followed by
an output operation. The only instructions which can
validly use F6 are MOVWF and CLRF.

EXAMPLE 1:

EXAMPLE 2:

~~----'I----/~-----Ir---~/
OUTPUT

'~----rl--~/'~----'I--~/

INPUT

OUTPUT

What is thought to be happening:
BSF 7,5
Read into CPU:
Set bit5:
Write to F7:

What could happen if an input were low:
BSF 7,5

00001111
00101111
00101111

Read into CPU:
Set bit 5:
Write to F7:

If no inputs were low during the instruction
execution, there would be no problem.

INPUT

00001110
00101110
00101110

In this case bit 0 is now latched low and is
no longer useful as an input until set high
again.

4-57

OS300068-7

PIC1655
ELECTRICAL CHARACTERISTICS

-Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation olthe
device at those or any other conditions above those
indicated in the operation listings of this specification is
not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

Maximum Ratings*
Ambient temperature under bias ........................ 125·C
Storage Temperature ...................... - 55·C to + 150·C
Voltage on any pin with respect
to Vss .................................................... -0.3V to + 10.0V
Power Dissipation (Note 1) ........................... 1000mW

DC CHARACTERISTICS/PIC1655
Characteristic

Sym

Primary Supply Voltage
Output Buffer Supply Voltage
Primary Supply Current
Output Buffer Supply Current
Input Low Voltage
Input High Voltage (except
MClR, RTCC & OSC)
Input High Voltage
(MCLR, RTCC & OSC)
Output High Voltage

Vcc
Vxx
100
Ixx
VIL

Output Low Voltage
(1/0 only)

Output low Voltage
(CLKOUT)
Input Leakage Current
(MCLR, RTCC)
Leakage Current
(open drain 110 pins)
Input Low Current
(all 1/0 ports)
Input High Current
(all 1/0 ports)
t Typical data is at TA

Operating temperature TA
Min
4.5
4.5

30
1

-0.2

VIH

2.4

VILH
VOH

Voo - 1
2.4
3.5

VOL1

Max

Units

7.0
10.0
65
5
0.8

V
V
mA
mA
V

Voo

Voo
Voo
Voo
0.45
0.90
0.90
1.20
2.0

V
V
V
V
V
V
V
V

Conditions

(Note 2)
All 1/0 pins @ Voo (Note 6)
All 110 pins @ voo (Note 3)

VOL2

0.45

IOH = -100~A (Note 4)
IOH = 0
IOL = -1.6mA, Vxx = 4.5V
IOL = 5.0mA, Vxx = 4.5V
IOL = 5.0mA, Vxx = 8.0V
IOL = 10.0mA, Vxx = 8.0V
IOL = 20.0mA, Vxx = 8.0V
(Note 5)
IOL = -1.6mA, (Note 5)

ILC

-5

Vss ::; VIN ::; Voo

IOLC

Vss::; VPIN::; 10V

IlL

- 0.2

-0.6

-1.6

VIL

= O.4V internal pullup

IIH

- 0.1

-0.4

-1.4

VIH

= 2.4V

= 25·C, Voo = 5.0V.

NOTES:
1. Total power dissipation for the package is calculated as follows:
Po = (Voo) (100) + L(VOO - VIL) (IIOHI) + L(VOL)
(IOL).
The term 1/0 refers to all interface pins; input,
output or 1/0.
2. Vxx supply drives only the 1/0 ports.
3. The maximum Ixx current will be drawn when all
1/0 ports are outputting a High.

D8300068-8

Typt

= O·C to + 70·C

4. Positive current indicates current into pin.
Negative.current indicates current out of pin.
5. TotalloL for all output pins (1/0 ports plus ClK
OUT) must not exceed 225mA.
6. See Primary Supply current Chart for additional
information.

4-58

PIC1655
DC CHARACTERISTICS/PIC16551
Characteristic

Sym

Operating temperature TA = -40'C to + 85'C

Min

Typt

Max

Units

7.0
10.0
70
5
0.7

V
V
mA
mA
V

Primary Supply Voltage
Output Buffer Supply Voltage
Primary Supply Current
Output Buffer Supply Current
Input Low Voltage
Input High Voltage (except
MCLR, RTCC & OSC)
Input High Voltage
(MCLR, RTCC & OSC)
Output High Voltage

VDD
Vxx
IDD
Ixx
VIL

4.5
4.5

VIH

2,4

VDD

VILH
VOH

VDD -1
2,4

VDD
VDD

V
V

Output Low Voltage
(1/0 only)

VOL1

0,45
0.90
0.90
1.20
2.0

V
V
V
V
V

30
1
-0.2

(Note 2)
All 1/0 pins @ VDD (Note 6)
All 1/0 pins @ VDD (Note 3)

VOL2

0,45

IOH = -100IlA (Note 4)
IOH = 0
IOL = -1.6mA, Vxx = 4.5V
IOL = 5.0mA, Vxx = 4.5V
IOL = 5.0mA, Vxx = 8.0V
IOL = 10.0mA, Vxx = 8.0V
IOL = 20.0mA, Vxx = 8.0V
(Note 5)
IOL = -1.6mA, (Note 5)

ILC

-5

IlA

Vss ~ VIN ~ VDD

IOLC

IlA

Vss

IlL

- 0.2

-0.6

-1.8

VIL = O,4V internal pullup

IIH

- 0.1

-0,4

-1.8

VIH = 2,4V

Output Low Voltage
(CLKOUT)
Input Leakage Current
(MCLR, RTCC)
Leakage Current
(drain 1/0 pins)
Input Low Current
(all 1/0 ports)
Input High Current
(all 1/0 ports)

Conditions .

VPIN

10V

Typical data is at TA = 25'C, VDD = 5.0V.

NOTES:
1. Total power dissipation for the package is calculated as follows:
PD = (VDD) (IDD) + :L(VDD - VIL) (IIOHI) + :L(VOL)
(IOL).
The term 1/0 refers to all interface pins; input,
output or 1/0.
2. Vxx supply drives only the 1/0 ports.
3. The maximum Ixx current will be drawn when all
1/0 ports are outputting a High.

4. Positive current indicates current into pin.
Negative current indicates current out of pin.
5. TotalloL for all output pins (1/0 ports plus CLK
OUT) must not exceed 225mA.
6. See Primary Supply current Chart for additional
information.

4-59

DS30006B-9

PIC1655
DC CHARACTERISTICS/PIC1655H
Characteristic

Sym

Operating temperature TA = -40·C to + 11 O'"C

Min

Typt

Max

Units
V
V
rnA
rnA
V

Conditions

Primary Supply Voltage
Output Buffer Supply Voltage
Primary Supply Current
Output Buffer Supply Current
Input low Voltage
Input High Voltage (except
MClR, RTCC & OSC)
Input Low-lo-High Threshold
Voltage (MClR, RTCC & OSC)
Output High Voltage

Voo
Vxx
100
Ixx
VIL

4.5
4.5

30
1

-0.2

5.5
10.0
70
5
0.7

VIH

2.4

Voo

VILH
VOH

Voo -1
2.4

Voo
Voo

V
V

Output Low Voltage
(I/O only)

VOL1

0.45
0.90
0.90
1.20
2.0

V
V
V
V
V

VOL2

0.45

IOH = -100J.1A (Note 4)
IOH = 0
IOL = -1.6mA, Vxx = 4.5V
IOL = 5.0mA, Vxx = 4.5V
IOL = 5.0mA, Vxx = 8.0V
IOL = 10.0mA, Vxx = 8.0V
IOL = 20.0mA, Vxx = 8.0V
(Note 5)
IOL = -1.6mA, (Note 5)

ILC

-5

J.1A

Vss :; VIN :; Voo

IOLC

J.1A

Vss:; VPIN:; 10V

IlL

- 0.2

-0.6

-1.8

rnA

VIL = 0.4V internal pullup

IIH

- 0.1

-0.4

-1.8

rnA

VIH = 2.4V

Output Low Voltage
(ClKOUT)
Input leakage Current
(MClR, RTCC)
Leakage Current
(open drain I/O pins)
Input low Current
(all I/O ports)
Input High Current
(all I/O ports)

(Note 2)
All I/O pins @ Voo (Note 6)
All I/O pins @ Voo (Note 3)

Typical data is at TA = 25·C, Voo = 5.0V.

NOTES:
1. Total power dissipation for the package is calculated as follows:
Po = (Voo) (100) + L(VOO - VIL) (IIOHI) + L(VOL)
(IOL).
The term I/O refers to all interface pins; input,
output or I/O.
2. Vxx supply drives only the I/O ports.
3. The maximum Ixx current will be drawn when all
I/O ports are outputting a High.

D830006B-10

4. Positive current indicates current into pin.
Negative current indicates current out of pin.
5. TotalloL for all output pins (I/O ports plus ClK
OUT) must not exceed 225mA.
6. See Primary Supply current Chart for additional
information.

4-60

-- -

- - - - - _ ..- -

-~".-.~---~"

---~-----

PIC1655
Operating temperature TA = O'C to + 70'C

AC CHARACTERISTICS/PIC1655,
PIC16551 AND PIC1655H
Characteristic
Instruction Cycle Time

-40'C to +85'C and -40'C to + 11 O'C

Min

Sym
tCY

Max

Typt

Units

Conditions

I1s

0.2 MHz - 1.0MHz external
time base (Notes 1, 2 and 5)

RTCC Input

= 0.2I1S-

Period

tRT

tCY

High Pulse Width

tRTH

1/2 tRT

low Pulse Width

tRTl

1/2 tRT

Data Input Setup Time

1/4tcY - 125

Data Input Hold Time

Data Output Propagation
Delay
OSC Input

tpo

600

1000

Capacitive load

External Input Impedance
High

ROSCH

120

800

3500

Vosc

External Input Impedance
low

ROSCl

10·

VOSC = O.4V OSC drive only

(Notes 2 and 3)

1/0 Ports

= 50pF

=5V Applies to external

Typical data is at TA = 25'C, Voo = 5.OV.

NOTES:
1. Instruction cycle period (tCY) equals four times the inut oscillator time base period.
2. Due to the synchronous timing nature between ClK OUT and the sampling circuit used on the RTCC input,
ClK OUT may be directly tied to the RTCC input.
3. The maximum frequency which may be input to the RTCC pin is calculated as follows:
f(max) = _1_ = -:-:-__1---,;;-;;:_
tRT (min)
tCY (min) + 0.211S
For example: if tCY = 411S, f(max) = - 4
21
= 238KHz .
. I1s
4. Caution must be exercised to allow for unit to unit variation of oscillator frequency when using RC option.
(See RC Option Operation Graph).

PRIMARY SUPPLY CURRENT AT SELECTED TEMPERATURES:
PIC1655, PIC16551, PIC1655H
Characteristic
Primary Supply Current

Sym

Max

Units

100

70
65
48
45
42

mA
mA
mA
mA
mA

4-61

Conditions
-40'C, All 1/0 pins at Voo
O'C, All 1/0 pins at Voo
70'C, All 1/0 pins at Voo
85'C, All 1/0 pins at Voo
11 O'C, All 1/0 pins at voo

OS300068-11

PIC1655
1/0 TIMING
CLKOUT

f--\

;-\

/-\-5

GATE
ANSWER

I..INCREMENT
I
PC-

EXECUTE
4
~4
INSTRUCTION

ADDRESS ROM
FOR NEXT
INSTRUCTION

WRITE
TO _ _

I/O

INTERNAL
BUS

I-I
I VALID
I

Tpd

OUTPUT

- IV
TS

I--

I-- -

INPUT

--------~!~

NOTE:

Rise and fall times
are load dependant

STABLE 1 : -

I (~----

CLOCK OUT TIMING

I..

1/4t CY

1\
CLOCK OUT

4t
3/ CY

-·)\1

____________________

I..

RTCCTIMING

i-----

I..

DS30006B-12

tRTH

.1...

tRTH_1

1
.1

tRT

4-62

PIC1655
SCHMITT TRIGGER CHARACTERISTICS (RTCC, MCLR AND OSC PINS)
TA =2S'C (TYPICAL)
4.0

3.0
VTHRESHOLD
VOLTS

I2.0

NOTE...1.

I-

NOTES:
1. Low-1o-High Threshold Vol1age (VTLH).
2. High-to-Low Threshold Voltage (V THL).

NOTE 2
1.0

4.5

5.0

6.0

5.5

6.5

7.0

VDD VOLTS

RC OPTION OPERATION

Voo
Rext

Cext

~05C

PIC1655

TYPICAL RC OSCILLATOR FREQUENCY RANGE
Rext
(kn)
40 , - - - . - - - .

Voo= 5.0V
TA = 25'C

f---t---

1--+--+----'

Cext = 47pF

0'--_-'--_-'--_-'-_--'-_--'
0.2

0.4

0.6

0.8

1.0 (MHz) Oscillator Frequency

20.0

10.0

6.7

5.0

4.0 (f1s) Instruction Cycle Time

Rext
(kn)
40

Voo= 5.0V
TA = 25'C

Cext = 100pF

20 i---t----'

f--+--+---t--=

o L-_~_-" __~_ _-'--_~
0.2

0.4

0.6

0.8

1.0 (MHz) Oscillator Frequency

20.0

10.0

6.7

5.0

4.0 (f1s) Instruction Cycle Time

Unit to Unit Variation @ 5.0V, 25'C is ±25'7'0
Variation from VOO = 4.5V - 7.0V referenced to 5.0V is -3%, +9%
Variation from TA = O'C - 70'C referenced to 25'C is +3%, -5%

4-63

05300068-13

PIC1655
MASTER CLEAR (TYPICAL CIRCUIn

BUFFERED CRYSTAL
INPUT OPERATION
XTAL

Voo

R
Rext
74HC04

74HC04
0---- TO OSC PIN #27

Cext

30% $ OUTY CYCLE $ 70%

R $100K

TO PIC1655 MCLR PIN #28

O.I~F

Master Clear requires> 1.0ms delay before
pin,
activation after power is applied to the
for the oscillator to start up. To achieve this, an
external RC configuration as shown can be
used (assuming VOO is applied as a step
function).

"bo

The buffer must be capable of driving 120Q, min. (BOOQ,
typ.) to 2.0V. However, it is recommended that the
pull-down transistor on the OSC pin be removed (an
option) if OSC is to be driven externally.

EXTERNAL CLOCK INPUT OPERATION
CLOCK FROM
""-. - TO OSC PIN #27
EXTERNAL SYSTEM ~

OUTPUT SINK CURRENT GRAPH
100

VXX

= 10V

VXX

= 9V

Vxx = BV

70
VXX

= 7V

60
10L 50
(mA)
40

Vxx = 5V

30
20
10

1.0

1.5

2.0

2.5

3.0

VOL (VOLTS)
The Output Sink Current is dependent on the VXX
supply and the output load. This chart shows the typical
curves used to express the output drive capability.

OS300068-14

4-64

PIC1655
VOH VS IOH (I/O PORTS) (TYPICAL)
voo = vxx

POWER SUPPLY CURRENT VS
TEMPERATURE (TYPICAL LIMITS)

= 4.25V

41.o:::--f--f--f--f--f-""""';

40
"00

VOH 3
VOLTS

T = 7.0V !----

t-- r--

(mA)
~-f--~~~~~-f--4

20
10

200

400

600

800

1000

-40

10H(~s)

120

B. Make sure to only use two levels of stack within the
program.

PIC1655 EMULATION CAUTIONS
When emulating a PIC1655 using a PICES II development system certain precautions should be taken.

C. Make sure all 110 cautions contained in this spec
sheet are used.

A. Be sure that the PICES II Module being used is
programmed for the PIC1655 mode. (Refer to the
PICES Manual). The PIC1655 contained within the
module should have the MODE pin #22 set to a high
state.

D. Be sure to use the 28 pin socket for the module plug.
E. Make sure that during an actual application the
MCLR input swings from a low to high level a minimum of 1msec after the supply voltage is applied.

F. If an oscillator drive is used, be sure that it can drive
the 1200 input impedance of the OSC pin on the
PIC1664.

1. This causes the MCLR to force all 110 registers high.
2. The OSC 1 pin #59 becomes a single clock input pin.

3. The interrupt system becomes disabled and the RTCC
always counts on the trailing edges.

G. The cable length and internal variations may cause
some parameter values to differ between the PICES
II module and a production PIC1655.

4. Bits 3 through 7 on file register F3 are all ones.

0
40
Temp ee)

0830006B-15

4-65

---_.

~.--------

PIC1655
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the sales offices. For the currently available code-combinations, refer to previous page.

PART NUMBERS
IP X

Pattern

Package

"--_---II Temperature

Range

'---_ _ _ _-11 Device
I

DS3OO06B-16

3-Digit

Blank
I
H

Pattern Code

Plastic DIP

00 C to +70 0 C
-40 0 C to +85 0 C
-40 0 C to +110 0 C

PIC1655
PIC1657

4-66

PIC1670

Microchip

8 Bit Microcontroller
FEATURES

PIN CONFIGURATION
40 Lead Dual In Line

1024 x 13-bit Program ROM
64 x 8-bit RAM (16 special purpose registers)
Arithmetic Logic Unit
Sophisticated interrupt structure
6 level pushdown stack
• Versatile self contained oscillator
2.01lS instruction execution time
Wide power supply operating range (4.5-5.5 volts)
• 4 sets of 8 user defined TTL compatible 1/0 lines
• Available in two temperature ranges: O'C to 70'C
and -40'C to 85'C

Top View

DESCRIPTION
The PIC1670 microcontroller is an MOSILSI device containing RAM, 1/0, and a central processing unit as well
as customer-defined ROM on a Single chip. This combination produces a low cost solution for applications
which require sensing individual inputs and controlling
individual outputs. Keyboard scanning, display driving,
and system control functions can be done at the same
time due to the power of the 8-bit CPU.

VoofMCLRf-

HRAO
HRA1
HRA2
HRA3
f- CLKOUT
HRA4
HRA5
HRAS
HRA7
HRBO
HRB1
HRB2
HRB3
HRB4
HRB5
HRBS
HRB7

RDSH
RD5H
RD4H
RD3H
RD2H
RD1H
RDOH
RC7H
RCSH
RC5H
RC4H
RC3 f-'7
RC2 f-'7
RC1H
RcoH

TEST~

Vss

RT~

RD7~

Extensive hardware and software support is available to
aid the user in developing an application program and to
verify performance before committing to mask tooling.
Programs can be assembled into machine language
using PICALC, eliminating the burden of coding with
ones and zeros. Once the application program is developed, several options are available to insure proper performance. The PIC's operation can be verified in any
hardware application by using the PIC1665. The PIC 1665
is a ROM-less PIC1670 microcontroller with additional
pins to connect external EPROM or RAM and to accept
HALT comm W
Move lile to itseH

DAW
MOVWF
SUBBWF
SUBWF
DECF
IORWF
ANDWF
XORWF
ADDWF
ADCWF
COMPF
INCF
DECFSZ
RRCF
RLCF
SWAPF
INCFSZ
MOVFW
CLRF
RRNCF
RLNCF
CPFSLT
CPFSEO
CPF.SGT
TESTF

I
I,d
I,d
I,d
I,d
I,d
I,d
I,d
I,d
I,d
I,d
I,d
I,d
I,d
I,d
I,d
I
I
I
I
I
I
I
I

(6)

(5-0)

f(FILE #)

Operation

Status Affected

(Note 1)
C
W-,>I
I+W+c-,>d
OV,C,DC,Z
I+W+l-,>d
OV,C,DC,Z
1-1-,> d
OV,C,DC,Z
WVf -'> d
Z
W'l-,>d
Z
wEB I-,>d
Z
W+I-,>d
OV,C,DC,Z
W+I+c-,>d
OV,C,DC,Z
f-,>d
Z
I+l-,>d
OV,C,DC,Z
I • 1 -'> d, skip il zero
I(n)-,>d(n - 1), c-,>d(7), I(O)-'>C
C
I(n)-,>d(n + 1), c-,>d(O), 1(7)-,>c
C
1(0-3) ~ (4-7)-,>d
I + 1 -'> d, skip il zero
1-,> W
Z
o -'> I
Z
I(n) -'> d(n-l), 1(0) -'> 1(7)
I(n)-,>d(n + 1), 1(7)-,>1(0)
1- W, skip ilC = 0
I - W, skip il Z = 1
1- W, skip ilZ· C = 1
f-l
Z

Note 1: The DAW instruction adjusts the eight bit number in the W register to form two valid BCD (binary coded
decimal) digits, one in the lower and in the upper nibble. (The results will only be meaningful if the number
in W to be adjusted is the result of adding together two valid two digit BCD numbers). The adjustment obeys
the following two step algorithm.
1. If the lower nibble is greater than 9 or the digit carry flag (DC) Is set, 06 is added to the W register.
2. Then, if the upper nibble is greater than 9 or the carry from the original or step 1 addition is set, 60 is
added to the W register. The carry bit is set if there is a carry from the original step 1 or step 2 addition.

OS300038-4

4-70

PIC1670

BIT ORIENTED FILE REGISTER OPERATIONS
Instruction-Binary
100
101
110
111

a
a
a
a

bbb
bbb
bbb
bbb

Iff
ttf
Iff
Iff

Name

(Octal)
Iff
Iff
Iff
Iff

(04000)
(05000)
(06000)
(07000)

(12-9)

(8 - 6)

(5-0)

OPCODE

b(BIT#)

f(FILE#)

Mnemonic, Operands

Bit clear file
Bit set file
Bit test, skip if clear
B~ test,skip if set

BCF
BSF
BTFSC
BTFSS

f,b
f,b
f,b
f,b

Operation

Instruction-Binary
a
a
a
1
1
1
1
1
1
1
1

000
000
000
001
001
010
010
all
all
10k
11k

000
000
000
Okk
lkk
Okk
lkk
Okk
lkk
kkk
kkk

000
000
000
kkk
kkk
kkk
kkk
kkk
kkk
kkk
kkk

(Octal)
000
010
all
kkk
kkk
kkk
kkk
kkk
kkk
kkk
kkk

I
Mnemonic, Operands

Name
No Operation
Return from interrupt
Return from Subroutine
Move Literal tro W
Add Literal to W
Inclusive OR L~eral to W
And Literal and W
Exclusive OR Literal to W
Return and load I~eral in W
Go to address
Call Subroutine

(00000)
(00002)
(00003)
(11000)
(11400)
(12000)
(02400)
(13000)
(13400)
(14000)
(16000)

NOP
RETFI
RETFS
MOVLW
ADDLW
IORLW
ANDLW
XCRLW
RETLW
GOTO
CALL

k
k
k
k
k
k
k
k

Status Affected

a -? fIb)
1 -? fIb)
Bit Test f(b),skip if clear
B~ Test fIb), skip if set

(12-8)

LITERAL AND CONTROL OPERATIONS

OPCODE
Operation

(7-0)

Ik (LITERAL) I
Status Affected

Stack -? PC
Stack -? PC
k -? W
k+W-?W
kVW -?- W
k·W-?W
k W-?W
k !iIll W, Stack - PC
k -? PC
PC + 1 -? Stack, k -? PC

OV,C,DC,Z
Z

Z
Z

PIN FUNCTIONS
Signal
Name
OSC1,OSC2

Function

Signal
Type
Input
Output

Oscillator pins. The on-board oscillator can be driven by an external crystal
ceramic resonator or an external clock via these pins.

Input

Real Time Input. Negative transitions on this pin increment the RTCC (F6)
register. This pin can also be used for an interrupt input. This pin uses a
Schmitt trigger input. There is no internal active pull-up device.

RAO-7, RB-7,
RCO-7, RDO-7

Input
Output

User programmable inpuVoutput lines. These lines can be used as inputs andi
or outputs and are under direct control of the program.

MCLR

Input

Master Clear: Used to initialize the internal ROM program to address 17778
latch all I/O registers high, and disables the interrupts. This pin uses a Schmitt
trigger input. There is no internal active pull-up device.

TEST

Input

Test pin. This pin is used for testing purposes only. It must be grounded for
normal operation.

Voo

Power supply pin.

Vss

Ground pin.

CLKOUT

Output

Clock Output: A signal derived from the internal oscillator. May be used by
external circuitry to synchronize with PIC1670 timing.

4-71

OS300039-5

PIC1670
INTERRUPT SYSTEM
The interrupt system of the PIC1670 is comprised of an
external interrupt and a real-time clock counter interrupt.
These have different interrupt vectors, enable bits and
status bits. Both interrupts are controlled by the status
register (F5) shown below.

[!"JNTE
Notes:

I AlB ICNTS I RTCIR I

XIR

I RTCIE I XIE

1. Bit 7 is unused and is read as zero.
2. The Status Register F5 will power up to all
zeroes.

External Interrupt
On any high to low transition of the RT pin the external
interrupt request (XIR) bit will be set. This request will be
serviced if the external interrupt enable (XI E) bit is set or
if it is set at a later point in the program. The latter allows
the processor to store a request (without interrupting)
while a critical timing routine is being executed. Once
external interrupt service is initiated, the processor
willclear the XIR bit, delay one cycle (to execute the
current instruction), then push the current program
counter onto the stack and execute the instruction at
location 17608. It takes three to four instruction cycles
from the transition on the RT pin until the instruction at
17608 is executed. No new interrupts can be serviced
until a return from interrupt (RETFI) instruction has been
executed.

Real-Time Clock Interrupt
The real-time clock counter (RTCCA & RTCCB, file
registers F6 and F7) have a similar mechanism of interrupt service. The RTCCA register will increment if the
count enable (CNTE) bit is set: If this bit is not set the
RTCCA & RTCCB will maintain their present contents
and can therefore be used as general purpose RAM
registers. The count source (CNTS) bit selects the
clocking source for RTCCA. If CNTS is cleared to a '0',
then RTCCA will use the internal instruction clock and
increment at 1/8 the frequency present on the OSC pins.
If CNTS is set to a '1', then RTCCA will increment on
each high to low transition of the RT pin. RTCCB can
only be incremented when RTCCA makes a transition
from 3778 to 0 and the AlB status bit is set. This condition
links the two eight bit registers together to form one
sixteen bit counter. An interrupt request under these
conditions will occur when the combined (egisters make
a transition from 1777778 to O. If, however, the AlB bit
is not set, then RTCCA will be the only incrementing
register and an interrupt request will occur when RTCCA
makes a transition from 3778 to O. (In this setup the
RTCCB register will not increment and can be used as
a general purpose RAM register). Once a request has
come from the real-time clock counter, the real-time
clock interrupt request (RTCIR) bit will be set. At this
pOint, the request can either be serviced immediately if
the real-time clock interrupt enable (RTCIE) bit is set or
be stored if RTCIE is not set. The latter allows the

INTERRUPT SYSTEM BLOCK DIAGRAM

-",
INTERNAL
CLOCK
JL

CARRY OUT

·s·
1 - - - - - CNTE
(SIT6)

17408

DS300038-6

4-72

PIC1670
on its odd-numbered location will interrogate the chip
pins while an 1/0 port READ on its even-numbered
location will interrogate the internal latch in that 1/0 port.
This simplifies programming in cases where a portion of
a single port is used for inputting only while the remainder is used for outputting as illustrated in the following
example.

Interrupt System (Cont.)
processor to store a real-time clock interrupt while a
critical timing routine is being executed. Once interrupt
service is initiated, the processor will clear the RTCIR bit,
delay one cycle (to execute the current instruction), then
push the present program counter onto the stack and
execute the instruction at location 1740s. It takes three
instruction cycles from when the RTCC(A or B) overflows until the instruction 1740s is executed. No new
interrupts can be serviced until a RETFI instruction has
been executed.

Here, the low 3 bits of port RA are used as output-only,
while the high 5 bits are used as input-only. During
power on reset (MCLR low), the latches in the 1/0 ports
will be set high, turning off all pull down transistors as
represented by 0 2 in the figure below. During program
execution if we wish to interrogate an input pin, then, for
example,
BTFSS 11,6

The RETFI instruction (00002s) must be used to return
from any interrupt service routine if any pending interrupts are to be serviced. External interrupts have priority
over RTCC driven interrupt in the event both types occur
simultaneously. Interrupts cannot be nested but will be
serviced sequentially. The existance of any pending
interrupts can be tested via the state of the XIR (bit 2) and
RTCIR (bit 1) in the status word F5.

will test pin RA6 and skip the next instruction if that pin
is set. If we wish to modify a single output, then, for
example,
BCF 10,2
will force RA2 to zero because its internal latch will be
cleared to zero. This will turn on 02 and pull the pin to
zero.

INPUT/OUTPUT CAPABILITY

The way this instruction operates internally is the CPU
reads file 10 into the A.L.U., modifies the bit and reoutputs the data to file 10. If the pins were read instead,
any input which was grounded externally would cause a
zero to be read on that bit. When the CPU re-outputted
the data to the file, that bit would be cleared to zero, no
longer useful as an input until set high again.

The PIC1670 provides fourcompletequasi-bidirectional
input/output ports. A simplified schematic of an 1/0 pin
is shown below. The ports occupy address locations in
the register file space of the PIC1670. Thus, any
instruction that can operate on a general purpose register can operate on an 1/0 port. Two locations in the
register file space are allocated for each 1/0 port. Port
RAO-7 is addressable as either F1 Os or F11s. Port RBO7 is addressable as either F12s or F13s. Port RCO-7 is
addressable as either F14s or F15s. An 1/0 port READ

During program execution, the latches in bits 3-7 should
remain in the high state. This will keep 02 off, allowing
external circuitry full control of pins RA3-RA7, which are
being used here as input.

BIDIRECTIONAL INPUT-OUTPUT PORT
INTERNAL

1/0 PORT
VDD

VDD

BUS

MCLR
RAQ

S
D

RA1
Q

RA2
PIC
WRITE

RA3
RA4

C
Vss

Vss

RA5
RA6
RA7

READ EVEN

1/0 FILE #

READ ODD = 1/0 FILE #

4-73

D8300036-7

PIC1670
ELECTRICAL CHARACTERISTICS
Maximum Ratings·

* Exceeding these ratings could cause permanent
damage to the device. This is a stress rating only and
functional operation of this device at these conditions
is not implied. Operating ranges are specified in Standard Conditions. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
Data labeled "typical" is presented for design guidance
only and is not guaranteed.

Temperature Under Bias .................................. 125'C
Storage Temperature ...................... - 55'C to +150'C
Voltage on any pin with
respect to Vss ................................ -0.3V to +1 O.OV
Power Dissipation ........................................1000mW

Operating temperature:
TA
- Commercial:
- Industrial:
TA

DC CHARACTERISTICS

= 0 'C to + 70 'C
= -40'C to + 85'C

Characteristic

Sym

Min

Typ*

Max

Units

Power Supply Voltage
Primary Supply Current
Input Low Voltage
(except MCLR & RT)
Input High Voltage (except
MCLR. RT, OSC1)
Input High Voltage
(MCLR, RT, OSC1)
Output High Voltage

Voo
100
VIL

4.5

Vss

5.5
100
0.8

V
mA
V

VIHI

2.4

Voo

VIH2

Voo-1

Voo

VOH

2.4

Voo

VOL

0.45

ILC

-5

IlA

Vss

ilL

-0.2

-0.6

-2.0

VIL

= O.4V internal pullup

IIH

-0.1

-0.4

VIH

= 2.4V

Output Low Voltage
(I/O and CLK OUT)
Input Leakage Current
(MCLR, RT, OSC1)
Input Low Current
(All I/O ports)
Input High Current
(All I/O ports)

Conditions

All I/O pins high

IOH - 100 IlA provided
by internal pullups (Note 2)
IOl = 1.6mA

= VIN - Voo

* Typical data is at TA = 25'C, voo = OV.
Notes: 1. Total power dissipation for the package is calculated as follows:
Po = (Voo) (100) + ~ {(Voo - VIL)·IVILll + ~ {(Voo - VOH)·lloHll + ~ {(VOLj·IOL}.
2 Positive current indicates current into pin. Negative current indicates current out of pin.
3. TotalloL for all output pin (I/O ports plus CLK OUT) must not exceed 175mA.
(

08300038-8

4-74

PIC1670

AC CHARACTERISTICS

Characteristic
Instruction Cycle Time

Operating temperature:
TA
- Commercial:
- Industrial:
TA
Sym

Min

Typ

Max

Units

tCY

2.0

tRT
tRT
tRTH
tRTL

tCY+175ns
tcY+200ns
1/2tRT
1/2tRT

tR
tH
tRT

1/4tcy - 125

500

800

RT input
Period - Commercial
Period -Industrial
High Pulse Width
Low Pulse Width
1/0 Ports
Data Input Setup Time
Data Input Hold Time
Data Output Propagation Delay

ns
ns
ns

= 0 ·C to + 70 ·C
= -40 ·C to + 85 ·C

Conditions
4 MHz external time
base (Notes 1, 2, 4))
(Note 3)
Commercial: TA = 70·C
Industrial: TA = 85·C
Commercial: TA = 70·C
Commercial: TA = 70·C

Capacitance load

= 50pF

Notes:
1. Instruction cycle period (tCY) equals eight times the oscillator time base period.
2. The oscillator frequency may deviate to 4.08 MHz to allow for tolerance of the time base element (LC, crystal,
or ceramic resonator).
3. Due to the synchronous timing nature between CLK OUT and the sampling circuit used on the RT input, CLK
OUT may be directly tied to the RT input. The minimum times specified represent theoretical limits.
4. The maximum frequency which may be input to the RT pin is calculated as follows: fmax= _1_ =_1_
where: d=175 ns for Commercial
IRTm;n \cVm;n+O
d=200 ns for Industrial
Examples: Commercial:
if tCY = 2~s, f(max) = 1/2.175 ~s = 460 KHz
Industrial:
if tCY = 2~s, f(max) = 1/2.2~s = 455 KHz.

4-75

OS300038-9

PIC1670
1/0 TIMING
CLKOUT

bR~~E~

WRITE
TO 1/0

EXECUTE
INSTRUCTION

ADDRESS ROM
FOR NEXT
INSTRUCTION

-II

1-----1-- GATE
ANSWER
INTERNAL
BUS
tpd ; - -

OUTPUT

VALID
NOTE:
Rise and fall times
are load dependent

INPUT

ClK OUT TIMING

1/4lcy

CLKOUT

TL
I

"'~

~--------------------

Icy

RTec TIMING

RTCC

:......--

tRTH

____I

tAll

,'-------,
tRT

SCHMITT TRIGGER CHARACTERISTICS (TYPICAL)
(RT, MCLR) T A = 25'C

VTLH

VTHRESHOLD

(VOLTS)

VTHL

4.5

5.0

5.5

IobD (VOLTS)

DS30003B-10

4-76

PIC1670
TYPICAL OSCILLATOR CIRCUITS
CRYSTAL INPUT OPERATION

POWER DISSIPATION DERATING GRAPH

20pF

1000

rl~TOOSCPIN#l

t1-10M~ Q:

XTAL'

~TOOSCPIN#2

20pF

800

700

C;;

600

CIl

'OR CERAMIC RESONATOR,
PARALLEL RESONANT
(1.0 - 4.0 MHz)

:>
w

f'.

400

«
::;;

300
NOTE 1
200
100
NCTE2

" TO OSC PIN #1

~ TO OSC PIN #2

TA - AMBIENT TEMPERATURE ("C)

Notes: 1. 70'C is the maximum operating temperature for standard parts.
2. 85'C is the maximum operating temperature for "I" suffix parts.

R,;100K

~
C

500

::;;
:::>
::;;

MASTER CIRCUIT (TYPICAL)
R

r'\

EXT, INPUT OPERATION

NO CONNECTION

D-

--~

CLOCK FROM
EXT. SYSTEM

~ 900

E-

MCLR (PIN #39)

OUTPUT SINK CURRENT GRAPH

O.lI1F

Note: The MCLR pin must be pulsed low for a minimum
of one complete instruction cycle (tCY) for the
master clear function to be guaranteed, assuming that power is applied and the oscillator is
running. For inititial power application, a delay is
required for the external oscillator time base
element to start up before MCLR is brought high.
To achieve this, an external RC configuration as
shown can be used. This provides approximately
a 10 ms delay (assuming Voo is applied as a step
function), which may be insufficientfor some time
base elements. Consult the manufacturer of the
time base element for specific start-up times.

IOH
(rnA)

....

VOo- 5.0V

.,;'

/'
1.0

3.0

2.0
VOL(VOLTS)

VOH VS 10H (1/0 PORTS) (TYPICAL)

VOH

I---~~~-t---+--I

(VOLTS)
2

I"L--1---t---.:~~~==t=

TA - 8S'C
TA .2S'C

'----'_--'_-'."--~':t==.=.t--

TA - 40'C

200

400
10H

. 4-77

600

800

1000

(IJA)

OS300038-11

PIC1670
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.

PART NUMBERS

!:!!:.~ -

H I.

TLX_____--I
Pattern:

3-Digit Pattern Code

Package:

Plastic DIP

I
I

Temperature
Range:

O·Cto +70·C
-40·C to +85·C
-40·C to + 11 O·C

Device:

PIC1670

LIFE SUPPORT SYSTEM - Microchip's products are not authorized for use as critical components in tife support devices or systems without the express written approval of
Microchip Technology, Inc.

05300038-12

4-78

Microchip

SECTION 5
LOGIC PRODUCT SPECIFICATIONS
AY2661
AY3-1015D
AY58116/36
AY58126/46
AY38910Al12A
AY8930
AY0438-1

Enhanced Programmable Communication Interface ................................................ 5UARIT: Universal Asynchronous ReceiverITransmitter ........................................... 5Dual Baud Rate Generator ....................................................................................... 5Single Baud Rate Generator ................................................•.................................... 5Programmable Sound Generator .............................................................................. 5Enhanced Programmable Sound Generator ............................................................. 532-Segment CMOS LCD Driver ................................................................................ 5-

5-i

1
17
29
37
45
61
81

DS00018C

Microchip

DS00018C

5-ii

AY2661

Microchip

Enhanced Programmable Communication Interface
FEATURES

PIN CONFIGURATION

Synchronous and Asynchronous full or half duplex
operation
On-chip baud rate generator - 3 standards
• Double buffering of data
• TTL compatible
Single +5 volt power supply
• Compatible with SC2661, COM2661

28 LEAD DUAL INLINE
Top View

RxO
GNO

DESCRIPTION

The AY2661 is a universal synchronous /asynchronous
receiver/transmitter designed for microcomputer system data communications. It may be programmed by
the processor to communicate in commonly used asynchronous and synchronous serial data transmission
techniques including Bi-Sync. The AY2661 receives
serial data streams and converts them into parallel data
characters for the processor. While receiving serial
data, the device will also accept data characters from the
processor in parallel format, convert them to serial
format and transmit. The AY2661 will signal the processor when it has completely received or transmitted a

VCC
RiCC/BKOET
OTR
RTS
OSR
RESET
BRCLK
TxD
TxEMT/DSCHG

05
07
TxC/SYNC
A1

AO
RIW

CfS
DCD
TxROY

RxROY

character and requires service. Complete status information including data format errors and control signals
is available to the processor at any time.

A Y2661 BLOCK DIAGRAM
DATA au S
00-07

'-----'

DATA BUS

BUFFER

OPERATION CONTROL

RESET

MODE REGISTER 1

,->

SYN/DLE CONTROL

r-r--

SYN 2 REGISTER

r:==

STATUS REGISTER

---

r-- r-

ROM
RE-PROGRAMMABLE

BAUD RATE
GENERATOR AND
CLOCK CONTROL

r--

r- ~
r-

f-'--'---

OSR
OCD
CTS
RTS
OTR

MODEM
CONTROL

TxEMTI
DSCHG

5-1

SYN 1 REGISTER

OLE REGISTER

•

MODE REGISTER 2
COMMAND REGISTER

BRCLK

fv--

TRANSMITIER

TRANSMIT DATA
HOLDING REGISTER
TRANSMIT

TxO

SHIFT REGISTER

RECEIVER

RECEIVE DATA
HOLDING REGISTER

RECEIVE

RxD

SHIFT REGISTER

Vec
GND

DS70007C-1

AY2661
PIN FUNCTIONS
Function

Pin Name
BRCLK

Clock input to the internal baud rate generator. Not required if external receiver and
transmitter clocks are used.

R x C/BKDET

Receiver clock. If external receiver clock is programmed, this input controls the rate at
which 'the character is to be received. Its frequency is 1X, 16X or 64X the baud rate, as
programmed by mode register 1. Data are sampled on the rising edge of the clock.
If internal receiver clock is programmed, this pin can be a 1Xl16X clock or a break detect
output pin.

T x C/xSYNC

Transmitter clock. If external transmitter clock is programmed, this input controls the rate
at which the character is transmitted. Its frequency is lX, l6X or 64X the baud rate, as
programmed by mode register 1. The transmitted data changes on the falling edge of the
clock. If internal transmitter clock is programmed, this pin can be al Xl16X clock output
for an external jam synchronization input.

RxD

Serial data input to the receiver. "Mark" is hi,gh, "space" is low.

TxD

Serial data output from the transmitter. "Mark" is high, "space" is low. Held in mark
condition when the transmitter is disabled.

DSR

General purpose input which can be used for data set ready or ring indicator condition.
Its complement appears as status register bit SR? It causes a low output on TxEMTI
DSCHG when its state changes and CR2 or CRO = 1.

DCD

Data carrier detect input. Must be low in order for the receiver to operate. Its complement
appears as status register bit SR6. Causes a low output on TxEMT/DSCHG when its state
changes and CR2 or CRO =1.lfi5'CD goes high while receiving, the R x C is internally inhibited.

CTS

Clear to send input. Must be low in order for the transmitter to operate. If it goes high during
transmission, the character in the transmit shift register will be transmitted before termination.

DTR

General purpose output which is the complement of command register bit CR1. Normally
used to indicate data terminal ready.

RTS

General purpose output which is the complement of command register bit CRS. Normally
used to indicate request to send. If the transmit shift register is not empty when CRS is reset
(1 to 0), then RTS will go high one T x C time after the last serial bit is transmitted.

RESET

A high on this input performs a master reset on the AY266l. This signal asynchronously
terminates any device activity and clears the mode, command and status registers. The device
assumes the idle state and remains there until initialized with the appropriate control words.
Address lines used to select internal EPClregisters.

RIW

Read cOmmand when low, write command when high.

Chip enable command. When low, indicates that control and data lines to the EPCI are valid
and that the operation specified by the Rtw, Al and Ao inputs should be performed. When
high, places the Do - D7 lines in the three-state condition.

DS70007C-2

5-2

AY2661

PIN FUNCTIONS (CONTINUED)
Pin Name
D7 - Do

---

Function
a-bit, three-state data bus used to transfer commands, data and status between EPCI and the
CPU. Do is the least significant bit; D7 the most significant bit.

Tx RDY

This output is the complement of status register bit SRO. When low, it indicates that the
transmit data holding register (THR) is ready to accept a data character from the CPU. It goes
high when the data character is loaded. This output is valid only when the transmitter is enabled
It is an open drain output which can be used as an interrupt to the CPU.

RxRDY

This output is the complement of status register bit SRI. When low, it indicates that the
receive data holding register (RHR) has a character ready for input to the CPU. It goes
high when the RHR is read by the CPU, and also when the receiver is disabled. It is an open
drain output which can be used as an interrupt to the CPU.

---

TxEMTI
DSCHG

This output is the complement of status register bit SR2. When low, it indicates that the transmitter has completed serialization of the last character loaded by the CPU, or that a change of
state of the DSR or DCD inputs has occured. This output goes high when the status'register is
read by the CPU, if the TxEMT condition does not exist. Otherwise, the THR must be loaded
by the CPU for this line to go high. It is an open drain output which can be used as an interrupt
to the CPU.

AY2661 OPERATION
The functional operation of the AY2661 is programmed
by a set of control words supplied by the processor.
These control words specify items such as synchronous
or asynchronous mode, baud rate, number of bits per
character, etc.

detected (RxD is low for the entire character as well as
the stop bit), only one character consisting of all zeros
(with the Framing error status bit set) will be transferred
to the Holding Register. The RxD input must return to
a high condition before a search for the next start bit
begins.

Receiver

Pin 25 can be programmed to be a break detect output
by appropriate setting of MR27-MR24. If so, a detected
break will cause that pin to go high. When RxD returns
to mark for one RxC time, pin 25 will go low. Refer to
the break detection timing diagram.

The AY2661 is conditioned to receive data when the DCD
input is low and RxEN bit in the command register is true.
In the asynchronous mode, the receiver looks for a high
to low (mark to space) transition of the start bit on the RxD
input line. If a transition is detected, the state of the RxD
line is sampled again after a delay of one-half of a bit time.
If RxD is now high, the search for a valid start bit is begun
again. If RxD is still low, a valid start bit is assumed and
the receiver continues to sample the input line at one bit
time intervals until the proper number of data bits, the
parity bit, and one stop bit have been assembled. The
data is then transferred to the Receive Data Holding
Register, the RxRDY bit in the status register is set, and
the RxRDY output is asserted. If the character length is
less than a bits, the high order unused bits in the Holding
Register are set to zero. The Parity Error, Framing Error,
and Overrun Error status bits are strobed into the status
register on the positive going edge of RxC corresponding
.to the received character boundary. If the stop bit is
present, the receiver will immediately begin its search for
the next start bit. If the stop bit is absent (framing error),
the receiver will interpret a space as a start bit if it persists
into the next bit time interval. If a break condition is
© 1990 Microchip Technology Inc.

When the AY2661 is initialized into the synchronous
mode, the receiver first enters the hunt mode on a 0 to
1 transition of RxEN (CR2). In this mode, as data is
shifted into the Receiver Shift Register a bit at a time,
the contents of the register are compared to the contents of the SYN1 register. If the two are not equal, the
next bit is shifted in and the comparison is repeated.
When the two registers match, the hunt mode is terminated and character assembly begins. If the single
SYN operation is programmed, the SYN DETECT
status bit is set. If double SYN operation is programmed, the first character assembled after SYN1
must be SYN2 in order for the SYN DETECT bit to be
set.
Otherwise, the AY2661 returns to the hunt mode. (note
that the sequence SYN1-SYN1-SYN2 will not achieve
synchronization). When synchronization has been
acheived, the AY2661 continues to assemble charac-

5-3

DS70007C-3

ters and transfers them to the Holding Register. The
RxRDY status bit is set and the RxRDY output is
asserted each time a character is assembled and transferredto the Holding Register. The Overrun error (OE)
and Parity error (PE) status bits are set as appropriate.
Further receipt of the proper SYN sequence sets the
SYN DETECT status bit. If the SYN stripping mode is
commanded, SYN characters are not transferred to the
Holding Register. Note that the SYN characters used to
establish initial synchronization are not transferred to
.
the Holding Register in any case.

acter to the AY2661 by the time the transmitter has
completed sending the previous character. Since synchronous communication does not allow gaps between
characters, the AY2661 asserts TxEMT and automatically "fills" the gap by transmitting SYN1s, and SYN1SYN2 doublets, or DLE-SYN1 doublets, depending on
the state of MR16 and MR17. Normal transmission of
the message resumes when a new character is available in the Transmit Data Holding Register. If the SEND
DLE bit in the command register is true, the DLE
character is automatically transmitted prior to transmission of the message character in the transmit holding
register.

External jam synchronization can be achieved via pin 9
by appropriate setting of MR27-MR24. When pin 9 is an
XSYNC input, the internal SYN1-SYN2, and DLE-SYN1
detection is disabled. Each positive going signal on
XSYNC will cause the receiver to establish synchronization on the rising edge of the next RxC pulse. Character
assembly will start with the RxD input at this edge.
XSYNC may be lowered on the next rising edge of RxC.
This external synchronization will cause the SYN DETECT status bit to be set until the status register is read.
Refer to XSYNC timing diagram.

AY2661 Programming
Prior to initiating data communications, the AY2661 operational mode must be programmed by performing
write operations to the mode and command registers. In
addition, if synchronous operation is programmed, the
appropriate SYN/DLE registers must be loaded. The
AY2661 can be reconfigured at any time during program
execution. A flow chart of the initialization process
follows.

Transmitter

The internal registers of the AY2661 are accessed by
applying specific signals to the CE, RIW A1 and AO
inputs. The conditions necessary to address each
register are shown in Fig. 3.

The AY2661 is conditioned to transmit when the CTS
input is low and the TxEN command register bit is set.
The AY2661 indicates tothe processor that it can accept
acharacterfortransmission by setting the TxRDY status
bit and asserting the TxRDY output. When the processor writes a character into the Transmit Data Holding
Register, the TxRDY status bit is reset and the TxRDY
output is returned to a high (false) state. Data is
transferred from the Holding Register to the Transmit
Shift Register when it is idle or has completed transmission of the previous character. The TxRDY conditions
are then asserted again. Thus, one full character time of
(
buffering is provided.

The SYN1, SYN2, and DLE registers are accessed by
performing write operations with the conditions A1=O,
AO=1, andRIW=1. The first operation loads the SYN1
register. The next loads the SYN2 register, and the third
loads the DLE register. Reading or loading the mode
registers is done in a similar manner. The first write (or
read) operation addresses Mode Register 1 and subsequent operation addressed Mode Register 2. If more
than the required number of accesses are made, the
internal sequencer recycles to point at the first register.
The pointers are reset to SYN1 Register and Mode
Register 1 by a RESET input or by performing a "Read
Command Register" operation, but are unaffected by
any other read or write operation.

In the asynchronous mode, the transmitter automatically sends a start bit followed by the programmed
number of data bits, the least significant bit being sent
first. It then appends an optional odd or even parity bit
and the programmed number of stop bits. If, following
transmission of the data bits, a new character is not
available in the Transmit Holding Register, the TxD
output remains in the marking (high) condition and the
TxEMT/DSCHG output and its corresponding status bit
are asserted. Transmission resurries when the processor loads a new character into the Holding Register. The
transmitter can be forced to output a continuous low
(BREAK) condition by setting the Send Break command
bit high ..

The AY2661 register formats are summarized in Tables
6,7,8 and 9. Mode Registers 1 and 2 define the general
operational characteristics of the AY2661, while the
Command Register controls the operation within this
basic framework. The AY2661 indicates its status in the
Status Register. These registers are cleared when a
RESET input is applied.

In the synchronous mode, when the AY2661 is initially
conditioned to transmit, the TxD output remains high
and the TxRDY condition is asserted until the first
character to be transmitted (usually a SYN character) is
loaded by the processor. Subsequent to this, a continuous stream of characters is transmitted. No extra bits
(other ihan parity if cOmmanded) are generated by the
AY2661 unless the processor fails to send a new char-

DS70007C-4

5-4

AY2661
AY2661 INITIALIZATION FLOW CHART
INITIAL RESET

NOTE
Mode Register 1 must be written before 2
can be written. Mode Register 2 need not
be programmed if external clocks are used.

SYNCHRONOUS?
NOTE
SYN 1 Register must be written before
SYN2 can be written and SYN2 before DLE

can be written.

TRANSPARENT
MODE?

5-5

DS70007C-5

AY2661
AY2661 REGISTER ADDRESSING
CE

RfW

1
0
0
0
0
0
0
0
0

X
0
0
0
0
1
1
1
1

X
0
0
1
1
0
0
1
1

X
0
1
0
1
0
1
0
1

Function

Tri-state data bus
Read receive holding register
Write transmit holding register
Read status register
Write SYN1/SYN2/DLE registers
Read mode registers 1 and 2
Write mode registers 1 and 2
Read command register
Write command register

NOTE
See AC Characteristics section for timing requirements.

MODE REGISTER 1 (MR1)
MR17

MR1S

Sync/Async
Async: Stop Bit Length
00 = Invalid
01 = 1 stop bit
10 = 1 1/2 stop bits
11 = 2 stop bits
Sync:
Number of
SYN char
0= Double
Syn
1 = Single
Syn

MR15
Parity
Type

O=Odd
1 = Even

MR14
Parity
Control

0= Disabled
1 = Enabled

MR13 MR12

Character
Length

00 =
01 =
10 =
11 =

5 bits
6 bits
7 bits
8 bits

MRll

MR10

Mode and Baud
Rate Factor

00 = Synchronous 1X rate
01 = Asynchronous 1X rate
10 = Asynchronous 16X rate
11 = Asynchronous 64X rate

Sync:
Transparency
Control
0= Normal
1 = Transparent

NOTE
Baud rate factor in asynchronous applies only if external clock is selected. Factor is 16X if internal clock is selected.

DS70007C-6

5-6

AY2661
MODE REGISTER 2 (MR2)
MR27·MR24
TxC RxC Pin 9
0000
0001
0010
0011
0100
0101
0110
0111

E
E
I
I
E
E
I
I

I
E
I
E
I
E
I

TxC
TxC
lX
lX
TxC
TxC
16X
16X

Pin 25
RxC
lX
RxC
lX
RxC
16X
RxC
16X

MR23·MR2G

TxC RxC
1000
1001
1010
1011
1100
1101
1110
1110

E
E
I
I
E
E
I
I

I
E
I
E
I
E
I

Pin 25

Mode

Baud Rate Selection

RxCfTxC
BKDET
RxC
BKDET
RxCfTxC
BKDET
RxC
BKDET

Sync
Async
Sync
Async
Sync
Async
Sync
Async

See baud rates in
baud rate standards

Pin 9
XSYNC1
TxC
XSYNC1
lX
XSYNC1
TxC
XSYNC1
16X

NOTES
1. When pin 9 is programmed as XSYNC input, SYN1, SYNl-2, and DLE-SYNl detection is disabled.
E = External clock
I = Internal clock (BRG)
1X and 16X are clock outputs

COMMAND REGISTER (CR)
CR7

CR6

Operating Mode

CR5
Request
To Send

00 = Normal operation 0= Force RTS
01 = Async:
output high
Automatic
one clock
echo mode
time after
Sync: SYN andl
TxSR
or DLE stripping
serialization
mode
1 = Force RTS
10 = Local loop back
output low
11 = Remote loop back

CR4

CR3

Reset Error

Sync/Async

0= Normal
Async:
1 = Reset
Force break
error flags
0= Normal
in status
1 = Force
register (FE,
break
OE, PEIDLE
detect).

CR2

CR1

CRG

Receive
Control
(RxEN)

Data
Terminal
Ready

Transmit
Control
(TxEN)

0= Disable
1 = Enable

0= Force DIR 0= Disable
output high 1 = Enable
1 = Force DIR
output low

Sync:
Send DLE
0= Normal
1 = Send
DLE

5-7

DS70007C-7

AY2661
STATUS REGISTER (SR)
SR7

SR6
Data Carrier
Detect

DataSet
Ready

SR4

SR3

SR2

Overrun

PE/DLE
Detect

TxEMTI
DSCHG

SR5
FE/SYN
Detect

0= DSR input 0= DCD input Async:
is high
is high
0= Normal
1 = DSR input 1 = DCD input 1 = Framing
is low
Error
is low

0= Normal
1 = Overrun
Error

Sync:
0= Normal
1 = SYN CHAR
detected

Async:
0= Normal
1 = Parity
Error

SR1
RxRDY

0= Normal 0= Receive
1 = Change
holding
in DSR or
register
DCD, or
empty
transmit
1 = Receive
shift register
holding
register
is empty
has data

Sync:
0= Normal
1 = Parity
error or
DLE
received

SRO
TxRDY

0=
Transmit
holding
register
busy
1=
Transmit
holding
register
empty

TIMING DIAGRAMS
TxRDY, TxEMT (shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode]

TxD

0
::;
(/J

::>
0

~:t

(,)

>
(/J

TxEN

TXRoY
TxEMT
CEFOR
WRITE OF
THR

~s:~(,)

TxD
TxEN

DATAl

DATA 2

DATA 4

DATA 3

~D~AI1121314ISIBC AI11213141S1 BC AI1121314ISIBC~D~AL...!.ili.

I . DATAl
.
I . DATA 2
.
I. DATA3..
~
-----.Jr--+I-------+I-------+I----t-I- - - - - + 1 - - -

::::: --+-L---f-~-~+---1------1-0--+-1_ I .-----1b
~
uJ

CEFOR lY
WRITE OF DATA I
THR

DATA 2

DATA 3

:\=
~

DATA 4

NOTES
A = S1art bn

B=Stopbnl
C=SlopbH2
o ... TxD marking condition
TxEMT goes low at the beginning of the last data bit or if parity is enabled at the beginning of the parity bit

DS70007C-8

5-8

AY2661

TIMING DIAGRAMS (Cont.)

RxRDY (Shown for 5·blt characters, no parity, 2 stop bits [In asynchronous mode])
RxC
RxD

"::;0

RxEN

'"0

SYNDET
STATUS BIT

:I:

-.J

RxRDY
CEFOR ~
READ
READ
STATUS

~
RxD

READ
STATUS

A11 I 21 3 I 4 I 51

IGNORED

DATA 1

READ RHR
(DATA 2)

READ RHR
(DATAl)

All I 21 3 I 4 I 51 B I CI

I I.

DATA 2

- I DI -

READ RHR
(DATA 3)

All I 21 3 I 4 I 51 B I C All I 2 13 I

DATA 3

II.

DATA 4

RxEN....!

s~:~~:;;.:=====================t::}~~t:========================s:==~~1
~

CEFOR
READ

READ RHR
(DATAl)

READ RHR
(DATA 3)

NOTES
A",Slartbit

B. Slop bit 1
C.Stopbit2

o '" TxD marking condition

TIMING DIAGRAMS (Cont.)
RESET

RESET-1
IRES

}
CLOCK

+-- IBRH ---; +-- IBRl ---;
+-- IRITH ---i E-- IRITl ---i

/
BRClK,-.J
!xc; RXC"

1lfBRG
1lfRIT

5·9

DS70007C-9

AY2661

TIMING DIAGRAMS (Cont.)
TRANSMIT
\ f - - - - 1 BIT TIME
(1. 16. OR 64 CLOCK PERIODS)

TxC
(INPUT)
TxD

->I

r_-+-_f\_

TxC
(OUTPUT)

E-t TCS

~_ _ _- '

RECEIVE

~D -lL,_~Rx_~=--*-+-,~Jr L

RxC(lX)

READ AND WRITE

teE

RIW

3'-+-~---------~-+-'f~:-

DO - 07 - - - t - - - - " " " " \
(WRITE)

- f '------'f- "-tD-H -

tDS~

DO - 07
BUS
(READ) FLOATING

DATA
VALID

BUS FLOATING
tDF

DS70007C-10

5-10

AV2661

TIMING DIAGRAMS (Cont.)
EXTERNAL SYNCHRONIZATION WITH XSYNC

1XRxC

XSYNC

n~1L1L

~~II~'
, - - - - - - - - - - lI
I

t es = XSYNC SETUP TIME = 300ns

'-_________

tH = XSYNC HOLD TIME = ONE RxC

RxD

V
CHARACTER ASSEMBLY

BREAK DETECTION TIMING
Rx CHARACTER 5 BITS, NO PARITY

R~~~~ LJ1.SLflJLIL~
I
RxD

I
I

LOOK FQ>R START BIT LOW (IF RxD IS HIGH,
LOOK F9R HIGH TO LOW TRANSITION)

FALSE ;rART BIT CHECK MADE (RxD LOW)

I,-----;k------"'---"'---:I:-------i---

MISSING STOP BIT
DETECTED
SET FE BIT

MISSING STOP BIT DETECTED SET FE BIT.
0- RHR, ACTIVATE RXRlJ'r. SET BKDET PIN.
RxD INPUT - RxSR UNTIL A MARK TO SPACE
TRANSITION OCCURS.

NOTE
• If the stop bit is present, the start bit
search will commence immediately.

5-11

DS70007C-11

AY2661
ELECTRICAL CHARACTERISTICS
Maximum Guaranteed Ratings·

• Exceeding these ratings could cause permanent damage to the device. This is a stress rating only and
functional operation of this device at these conditions is
not implied. Operating ranges are specified in Standard
Conditions. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

Operating Temperature Range .............. O'C to +70'C
Storage Temperature Range ........... - SS'C to +1S0'C
Lead Temperature (soldering, 10 sec.) ........... +32S'C
Positive Voltage on any Pin,
with respect to ground ............................................... +18.0V
Negative Voltage on any Pin,
with respect to ground .................................................. -O.3V

Data labeled "typical" is presented for design guidance
only and is not guaranteed.

DC CHARACTERISTICS
Operating temperature TA = O'C to + 70'C, Vee = S.OV +S%
Characteristics
Input Voltage
Low
High
Output voltage
Low
High
Input leakage current
Output leakage current
Data bus high
Data bus low
Power supply current
Capacitance
Input
Output
Input/Output

DS70007C-12

Sym

Min

VIL
VIH

VOL
VOH
IlL
ILH
ILL
lee
CIN
COUT
Cia

Typ

Max

0.8

Unit

2.0

- -

0.4
10

2.4

10
10
1S0

20
20
20

5-12

Test Conditions

I1A

IOL = 2.2mA
10H = 4OOl1A
VIN = 0 to S.SV

I1A
I1A

Vo = 4.0V
Va = 0.4SV

pF
pF
pF

mA
fc= 1MHz
Unmeasured pins tied
to ground

AY2661

AC CHARACTERISTICS
Operating temperature TA = -O·C to +70·C, Vcc = 5.0V +5%
Characteristics
Pulse Width
Reset
Chip enable
Setup and hold time
Address setup
Address hold
RIW control setup
R/W control hold
Data setup for write
Data hold for write
Rx data setup
Rx data hold
Data delay time for read
Data bus floating time for read
CE to CE delay
Input clock frequency
Baud rate generator
(2661-1, -2)
Baud rate generator
(2661-3)
TxC or RxC
Clock width
Baud rate high
(2661-1, -2)
Baud rate high
(2661-3)
Baud rate low
(2661-1, -2)
Baud rate low
(2661-3)
TxC or RxC high
TxC or RxC low
TxD delay from falling
edge ofTxC
Skew between TxD
changing and falling
edge of TxC output

Sym

Min

Typ

t RES

1000
250

ns
ns

10
10
10
10
150
0
300
350

tCE
t AS
tAH
tcs
tCH
t DS
tDH
t RXS
t RXH
tDD
tDF
tCED

Max

200
100

600

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Test Conditions

Units

fBRG

1.0

4.9152

4.9202

MHz

fBRG

1.0

5.0688

5.0738

MHz

CL = 150pF
CL = 150pF

1.0

MHz

tBRH

tBRL

tRTH1
tRTL
'TXD

480
480

650

ns
ns
ns

CL = 150pF

t TCS

CL = 150pF

fRT

fBRG = 4.915MHz; meas
ured at V,H
fBRG = 5.0688MHz; meas
ured at V ,H
fBRG = 4.915MHz; meas
ured at V,L
fBRG = 5.0688MHz; meas
ured at V,L

NOTE:
1. fRT and tRTL shown for all modes except Local Loopback. For Local Loopback mode
fRT = 0.7MHz and tRTL = 700ns min.

5-13

DS70007C-13

AY2661
BAUD RATE STANDARDS
AY2661·A
(BRCLK = 4.9152MHz)

MR23·20

Baud Rate

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

50
75
110
134.5
150
200
300
600
1050
1200
1800
2000
2400
4800
9600
19200

Actual Frequency
16X Clock
0.8kHz
1.2
1.7598
2.152
2.4
3.2
4.8
9.6
16.8329
19.2
28.7438
31.9168
38.4
76.8
153.6
307.2

Percent
Error

-0.D1

0,196

-0.19
-0.26

Divisor
6144
4096
2793
2284
2048
1536
1024
512
292
256
171
154
128
64
32
16

AY2661~B
(BRCLK = 4.9152MHz)

MR23-20
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

DS70007C·14

Baud Rate
45.5
50
75
110
134.5
150
300
600
1200
1800
2000
2400
4800
9600
19200
38400

Actual Frequency
16XCIock
0.7279kHz
0.8
1.2
1.7598
2.152
2.4
4.8
9.6
19.2
28.7438
31.9168
38.4
76.8
153.6
307.2
614.4

Percent
Error
0.005

-0.01

-0.19
-0.26

Divisor
6752
6144
4096
2793
2284
2048
1024
512
256
171
154
128

64
32
16
8

AV2661
BAUD RATE STANDARDS (CO NT.)
AY2661-C
(BRCLK = 5.0688MHz)

MR23-20
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Baud Rate
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200

Actual Frequency
l6X Clock
0.8kHz
1.2
0.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8

Percent
Error

Divisor

6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66

3.125

33
16

0.016

-0.253

NOTE
16X clock is used in asynchronous mode. In synchronous mode, clock multiplier is1X and BRG can be
used only for TxC.

5-15

DS70007C-15

AY2661
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.

PART NUMBERS
~261

X/P

PACKAGE

Plastic Dip

A
B
C

(See Baud Rate Standards Tables)
(See Baud Rate Standards Tables)
(See Baud Rate Standards Tables)

'---------1: DEVICE

DS70007C-16

Programmable Communication Interface

5-16

AY31015D

Microchip

UAR/T: UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER
FEATURES

DESCRIPTION

• DTL and TTL compatible - no interfacing circuits
required - drives one TTL load
Fully Double Buffered - eliminates need for system
synchronization, facilitates high-speed operation
Full Duplex Operation - can handle multiple bauds
(receiving - transmitting) simultaneously
Start Bit Verification - decreases error rate with
center sampling
Receiver center sampling of serial input; 46%
distortion immunity
High Speed Operation
Three-State Outputs - bus structure capability
Low Power - minimum power requirements
Input Protected - eliminates handling problems
Single Supply Operation: +4.75V to +5.25V
1 1/2 stop bit mode
• External reset of all registers except control bits
register
N-channel Ion Implant Process
• 0 to 25K baud
Pull-up resistors to Vcc on all inputs

The Universal Asynchronous Receiver/Transmitter
(UARIT) is an LSI subsystem which accepts binary
characters from either a terminal device or a computer
and receives/transmits this character with appended
control and error detecting bits. All characters contain a
start bit, 5 to 8 data bits, 1,1-1/2, or 2 stop bit capability,
and either odd/even parity or no parity. In order to make
the UARIT universal, the baud, bits per word, parity
mode, and the number of stop bits are externally selectable. The device is constructed on a single monolithic chip. All inputs and outputs are directly compatible
with TTUDTUCMOS logic without the need for interfacing components. All strobed outputs are three-state
logic.

PIN CONFIGURATION

AY31015D BLOCK DIAGRAM

40 LEAD DUAL INLINE
Top View
TRAN$MITIER

Vcc(+SV)
No Connect
GND
ROE
RD8
RD7
RD6
RDS
RD4
RD3
RD2
RDl
PE
FE
OR
SWE
RCP
RDAV
DAV
SI

TCP
EPS
NBl
NB2
TSB
NP
CS
DB8
DB7
DB6
DBS
DB4
DB3
DB2
DBl
SO
EOC

DATA BITS

CONTROL

STROBE

16xT
CLOCK

[=[[===:::;~:;;;====::;:::==:t---f---<>
L--_-+---o

OUTPUT

END OF
CHARACTER

l6x R
CLOCK
SERIAL

INPUT

~+-C=:::'::====~=======:J-+--o
~

EXTERNAL
RESET

WQRlj

TBMT
XR

SERIAL

5-17

19l~

RECEIVER
DATA BITS

DS70005C-1

AY31015D
PIN FUNCTIONS
Inputl

Pin
Number

Signal
Name

Output

1
2

VCC
N.C.

VCC Power Supply: +5V Supply
(Not Connected)

Ground

ROE

Function

Received Data Enable: A logic "0" on this input places the received data onto the
output lines (ROB .. R01).
Received Data Bits: These are the B data output lines. Received characters are
right justified: the LSB always appears on R01. These lines have tri-state outputs;
i.e., they have the normal TTL output characteristics when ROE is "0" and a high
impedence state when ROE is "1 ". Thus, the data output lines can be bus structure oriented.

5-12

ROB .. R01

Parity Error: This line goes to a logic "1" if the received character parity does not
agree with the selected parity. Tri-state when SWE (pin 16) is "1 ".

Framing Error: This line goes to a logic "1" if the received character has no valid
stop bit. Tri-state when SWE (pin 16) is "1".

Over-Run: This line goes to a logic "1 "if the previously received character is not
read (OAV line not reset) before the present character is transferred to the receiver
holding register. Tri-state when SWE (pin 16) is "1".

SWE

Status Word Enable: A logic "0" on this line places the status word bits (PE, FE,
OR, OAV, TBMT) onto the output lines. A logic "1" puts the status word bit outputs
into a high impedance state.

RCP

Receiver Clock: This input line requires a clock whose frequency is 16 times (16X)
the desired receiver baud rate.

ROAV

Reset Data Available: A logic "0" will reset the OAV line. The OAV FIF is the only
thing that is reset.

OAV

Data Available: This line goes to a logic "1" when an entire character has been
received and transferred to the receiver holding register. Tri-state when SWE (pin
16) is "1 ". Fig. B.

Serial Input: This line accepts the serial bit input stream. A marking (logic "1 ") to
spacing (logic "0") transition is required for initiation of data reception. Fig. 7, B.

External Reset: Resets all registers. Sets SO, EOC, and TBMT to a logic "1".
Resets OAV, and error flags to "0". Clears input data buffer. Must be tied to logic
"0" when not in use.

DS70005C-2

5-18

AY31015D
PIN FUNCTIONS (CONT.)
Pin
Number

Signal
Name

TBMT

Input! Function
Output

Transmitter Buffer Empty: The transmitter buffer empty flag goes to a logic "1"
when the data bits holding register may be loaded with another character. Tri-state.
See Fig. 14, 16. Tristate when SWE (pin 16) is "1 ".

Data Strobe: A strobe on this line will enter the data bits into the data bits holding
register. Initial data transmission is initiated by the rising edge of OS. Data must be
stable during entire strobe.

EOC

End of Character: This line goes to a logic "1" each time a full character is transmitted. It remains at this level until the start of transmission of the next character. See
Fig. 13, 15.

Serial Output: This line will serially, by bit, provide the entire transmitted character. It
will remain at a logic "1" when no data is being transmitted.

26 .. 33 OB1 .. 0B8

Data Bit Inputs: There are up to 8 data bit input lines available.

Control Strobe: A logic "1" on this lead will enter the control bits (EPS, NB1, NB2,
TSB, NP) into the control bits holding register. This line can be strobed or hard
wired to a logic "1" level.

No Parity: A logic "1" on this lead will eliminate the parity bit from the transmitted and
received character (no PE indication). The stop bit(s) will immediately follow the last
data bit. If not used, this lead must be tied to a logic "0".

TSB

Number of Stop Bits: This lead will select the number of stop bits, 1 or 2 to be
appended immediately after the parity bit. A logic "0" will insert 1 stop bit and a logic
"1" will insert 2 stop bits. The combined selection of 2 stop bits and 5 bits/character
will produce 1 1/2 stop bits.

37-38

NB2, NB1

Number of Bits/Character: These two leads will be internally decoded to select either
5, 6, 7 or 8 data bits/character.
NB2
0
0
1
1

NB1
0
1
0
1

Bits/Character
5
6
7
8

EPS

Odd/Even Parity Select: The logic level on this pin selects the type of parity which
will be appended immediately after the data bits. It also determines the parity that
will be checked by the receiver. A logic "0" will insert odd parity and a logic "1" will
insert even partiy.

TCP

Transmitter Clock: This input line requires a clock whose frequency is 16 times (16X)
the desired transmitter baud rate.

5-19

DS70005C-3

AY31015D
ELECTRICAL CHARACTERISTICS
Maximum Ratings·
• Exceeding these ratings could cause permanent damage to the device.

Vee (with Respect to GND) ...................... -0.3 to + 16V
Storage Temperature ........................ -6SoC to + 1S0°C
Lead Temperature (Soldering, 10 sec) ............ +330°C

This is a stress rating only and functional operation ofthisdevice atthese
conditions is not implied. Operating ranges are specified in Standard
Conditions. Exposure to absolute maximum rating conditions for ex-

Standard Conditions

tended periods may affect device reliability.

(unless otherwise noted)
Vee ................................................................. +4.7SV to +S.2SV
Operating Temperature (TA) .................. O°C to +70°C

Data labeled "typical" is presented for design guidance only and is not
guaranteed.

DC CHARACTERISTICS
Characteristics

Min

Typ

Max

Units

Conditions

0
2.0

0.8
Vee +0.3

Volts
Volts

Has internal pull-up resistors to Vce

o volts bias, f :

O.S

Mohms

V ,N : SV

0.8

IOL : 1.6mA (sink)
IOL : 40 f.1A (source) - at Vec : +5V

Input Logic Levels (AY31 0150)
Logic 0
Logie 1

Input Capacitance
All inputs

1MHz

Output Impedance
Hi-Impedance Outputs

Data Output Levels
Logic.O
Logic 1

Output Capacitance
Power Supply Current

lee at Vee: +SV

2.4

Volts
Volts
pF

AC CHARACTERISTICS
Characteristics

Min

Typ

Max

Units

Conditions

Clock Frequency
Baud

DC
0

400
25

kHz
kbaud

at Vee: +4.75V
at Vee: +4.75V

Pulse Width
Clock Pulse
Control Strobe
Data Strobe
External Reset
Status Word Enable
Reset Data Available
Received Data Enable

1.0
200
200
SOO
500
200
SOO

f.1s
ns
ns
ns
ns
ns
ns

See
See
See
See
See
See
See

20
20

ns
ns

See Fig. 10
See Fig. 11

500
500

ns
ns

See Figs. 17 and 20
See Figs. 17 and 20

Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.

5
11
10
9
17
18
17

Remarks
All AC testing
waveforms at:
V ,H : 2.4V
V ,L : 0.8V
V OH : 2.0V
VOL: 0.8V

Set Up & Hold Time
Input Data Bits
Input Control Bits

Output Propagation Delay
TPDO
TPD1

DS70005C-4

5-20

AY31015D
TIMING DIAGRAMS
FIG. 1 UARIT - TRANSMITTER TIMING
~--'------------------'I-N-oT-E-3------------------------------------------'I

~------------------------~~-

TBMT~

---1

~ NOTE 2

~_____ ~A~~~i]~~:~0lE~~D~A~§-~l:£A~s.::~P~~STOP1
NOTE 1 I
~
BIT TIME

so Iii

DA~1~

STOP2!START

~--!
NOTES; SEE FIGURES 2, 3, 4 FOR DETAILS
TRANSMITTER INITIALLY ASSUMED INACTIVE AT START OF DIAGRAM.
SHOWN FOR 8 LEVEL CODE AND PARITY AND TWO STOPS.

DETAIL;

DATA~-

1; BIT TIME = 16 CLOCK CYCLES.

STROBE

ttl\-

CLOCK~

2; IF TRANSMITTER IS INACTIVE THE START PULSE WILL APPEAR ON LINE SO
1 TO 2 CLOCK CYCLES AFTER THE DATA STROBE OCCURS. SEE DETAIL.

3; SINCE TRANSMITTER IS DOUBLE BUFFERED ANOTHER DATA STROBE CAN
OCCUR ANYWHERE DURING TRANSMISSION OF CHARACTER 1 AFTER TBMT
GOES HIGH.

FIG.2 TRANSMITTER AT START BIT
NOT A TEST POINT

FIG. 3 TRANSMITTER AT START BIT

TRANSMITIER INACTIVE
TRANSMIT BUFFER LOADED WHEN EOC HIGH

TRANSMITIER ACTIVE
TRANSMIT BUFFER LOADED WHEN EOC LOW

~lLflJLJ
~

~ IIkh",,~
~_
~

I
L-,-______

TBMTI
EOC

()S
IIII
-=-=---_-LI--LI---'!. I
SO

I I

TBMT

I I
I I

_Eo_c__~II~

________

FIG.4 ALLOWABLE POINTS TO USE

~ STARTBIT ~

______~~______

FIG. 5 ALLOWABLE TCP, RCP

MAXIMUM~ ~~
DUTY CYCLE

~F REFER TO NOTE #1
DA
LEGAL
CS

I
I

1_ _ _

.
ILLEGAL TO USE CS

MINIMUM
DUTY CYCLE

I LEGAL

~U~

CYCLE
NOTE 1:
TIS AND CS MAY OCCUR SIMULTANEOUSLY
WHEN TRANSMITIER INACTIVE.

••

~Il...- ..

~~!~

50%DUTY~

'----------------------~CS

L':_:~MIN.
1 s MIN
u
.

ANY PULSE WIDTH WHICH MEETS ABOVE
CRITERIA IS ALLOWABLE.

NOTE:
IF CONTROL STROBE IS HARDWIRED TO "1 ".
THEN THE CONTROL DATA BITS MUST BE
STABLE DURING "ILLEGAL CS" TIME.

5-21

DS70005C-5

AV31015D
TIMING DIAGRAMS (CONT.)
FIG. 6 UARIT - RECEIVER TIMING
"I"
SI "0'

START

---I

DATAl

INTERNAL _ _ _ _

_ _L __

= = = =r= = ==- =

DATA2

;LSB -==-

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

~B.=r

PARITY STOPI STOP2

START

_ l_ _~_~_ __ L_ _~_~_ __ L_ _L __

DATAl

_L_ _ _ _ _L __ ___

SAMPLES
NOTE 1___1--

PARITY
ERROR
FRAMING

NOTE 1___1
-----------------------------==
--'

---7'1 t-

ERROR

1 CLOCK

D~A------------------------------------------______N_OT_E_2_~~1

_ __________________________________________________~N~OT~E~I____1~----------OVERRUN
-

NOTES:
1. THIS IS THE TIME WHEN THE ERROR CONDITIONS ARE INDICATED, IF

ERROR OCCURS.
2. DATA AVAILABLE IS SET ONLY WHEN THE RECEIVED DATA AND PE, FE, OR
HAVE BEEN TRANSFERRED TO THE HOLDING REGISTERS. (SEE
RECEIVER BLOCK DIAGRAM).
3. ALL INFORMATION IS GOOD IN HOLDING REGISTERS UNTIL DATA
AVAILABLE TRIES TO SET FOR NEXT CHARACTER.

FIG. 7 TRUE RECEIVER CENTER SAMPLING

4. ABOVE SHOWN FOR 8 BIT CODE WITH PARITY AND TWO STOP BITS.
FOR NO PARITY, STOP BITS FOLLOW DATA.
5. FOR ALL LEVEL CODE, THE DATA IN THE HOLDING REGISTER IS
RIGHT JUSTIFIED, THAT IS, LSB ALWAYS APPEARS IN RDI (PIN 12).

FIG.8 RECEIVER DURING 1ST STOP BIT
DAVANDSTOPBITONE

12345678

1il

RCPlJl-fl--JLn.JLJLJLflSLJ
I

----JI(

It-- SAMPLE
POINT

8 CLOCKS

I
I
I

7 CLOCKS

I
I

--+--.
SI
~ J
SI
SI

jf- ~; C;~6~~~~~~~~ '?:E~T;~;

I
I
I

SAMPLE POINT WILL BE HERE ~

RC'
INTERNAL
SAMPLE

""ST5W''''
u"LJLflSULJLJLllJ}liS1Fuu
I I I

I
I
I I

ROi-ROB
PE,FE,OR

o"o,~
DAVOFF _ _ _ _ _ _ _ _ _ _ _ _ _

INTERNAL SAMPLE PULSE - - - - - - - - '

FIG. 9 XR PULSE

FIG. 10 OS

·~-H~

VIH--

XR
500ns
MIN.

WHEN NOT IN USE, XR MUST BE HELD AT GND.
XR RESETS EVERY REGISTER EXCEPT THE
CONTROL REGISTER. SO, TBMT EOC ARE
RESET TO LOGIC "1" , ALL OTHER OUTPUTS
RESET TO LOGIC "0",

DS70005C-6

':::.]
MIN.

5-22

~ ro~, J L.
MIN.

MIN.

AY31015D
TIMING DIAGRAMS (CONT.)
FIG. 11A CS
VIH-

FIG.11B

VIH-

1\,------

r- -

"JL

200ns
MIN.

---7

.}-

CONTROL STROBE AND CONTROL BITS MUST BE
500ns MINIMUM.

CONTROL BITS MUST BE STABLE FOR LAST 200ns OF CS.

'20ns MIN.

FIG. 13 EOC TURN - ON

FIG,12
VIH-

I-

---'

V7 -jL- H

NPETC.

J-

200ns
MIN

f----I

VIH-

4\~I \.-

::: -1- - -Ii -

~s r--I,

----71

LEADING EDGE OF CONTROL DATA IS NOT CRITICAL AS LONG AS
TRAILING EDGE AND PULSE WIDTH SPECS ARE OBSERVED.

1.5
TYP.

*20ns MIN.

FIG. 15 EOC TURN - OFF

FIG. 14 TBMT TURN - OFF

VIH

)t-------------

TcP\

~iI
T::L~ ~,' ~l -_ ____

VIL- \ -

------------------

VIL

EOC

VOL-

1 ~s
TYP.

----7\ TYP.~s

IE--

5-23

DS70005C-7

AY31015D
TIMING DIAGRAMS
FIG. 17 ROE, SWE

FIG. 16 TBMT TURN· ON

RDE~WE
-Tep \

VIL-

TRI-STATE
OUTPUTS

~--------------

-II --~

VOH
TBMT

I-VIL

°t

VOH~

RD1-RD8 11.5V (
PE, FE, OR,
DA, TBMT

.1___1. \ __

~ 1.5~S ~

-~VIH

500nsMIN.
-

---7 500ns

MAX.

TYP.

---1

500ns
MAX.
VOL.

FIG. 19 SHORT CIRCUIT OUTPUT CURRENT

FIG.1s ROAV

(only 1 output may be shorted at a time)
21

f--

." y-

200ns

"
15

112

."\

I
/

NOMINAL

VOL-L
500ns
MAX.

<.)

.!£l

DAV

SHORT CIRCUIT
OUTPUT CURRENT

WIORSTrSE

4
VOUT

FIG. 20 R01 • ROB, PE, FE, OR, TBMT, OAV

2500

FIG. 21 +5 VOLT SUPPLY CURRENT
15

r-----,----r----~--~--_____,

+5 VOLT SUPPLY CURR~NT

.........

112 .. ..

1500

..........

<.)

r-....

, / WORST CASE

.........

.. .. ..

1000

t........

10 f-- NOMINAJ /

.. .

500

100

200

300

400

500

CASE TEMPERATURE ("C)

COUT pF

DS70005C-8

r-....

5-24

AY31015D
TRANSMITTER
FIG. 22 TRANSMITTER OPERATION
1. Turn Power On
2. Pulse External Reset
3. Select Baud -16 x eLK

Power is applied, external reset is enabled and clock pulse
is applied having a frequency of 16 times the desired baud.
The above conditions will set TBMT, EOC, and SO to logic
"1" (line is marking).
After initialization is complete, user may set control bits and
data bits. Control bits selection should occur before data
bit selection, however, one may set both OS and CS
simultaneously if minimum pulse width specifications are
followed. Once Data Strobe (OS) is pulsed the TBMT
signal will change from a logic "1" to a logic "0" indicating
that the data bits holding register is filled with a previous
character and is unable to receive new data bits and
transmitter shift register is transmitting previously loaded
data. TBMTwili return to a logic "1 ". When transmitter shift
register is empty, data bits in the holding register are
immediately loaded into the transmitter shift register for
transmission. The shifting of information from the holding
register to the transmitter shift register will be followed by
SO and EOC going to a logic "0" and TBMT will also go to
a logic "1" indicating that the shifting operation is completed and that the data bits holding register is ready to
accept new data. It should be remembered that one full
character time is now available for loading of the next
character without loss of transmission speed due to double
buffering (separate data bits holding register and transmitter shift register).

TBMT = 1

EOC= 1
SO = 1 (Stop Bit)

Data transmission is initiated with transmission of a start
bit, data bits, parity bit (if desired) and stop bit(s). When the
last stop bit has been on line for one bit time, EOC will go
to a logic "1" indicating that new character is ready for
transmission. This new character will be transmitted only
if TBMT is a logic "0" as was previously discussed.

TBMT = 0

Ves

5-25

DS70005C-9

AV31015D
RECEIVER
FIG. 23 RECEIVER OPERATION
1. Turn Power On

3. Select Baud - 16 x eLK
4. Set Control Bits

2. Pulse External Reset

DAV=O

Has

A Start Bit
Been Verified?
8-16xCLK
Yes

Power is applied, external reset is enabled and clock pulse
is applied having a frequency of 16 times the desired baud.
The previous conditions will set data available (DAV) to a
logic "0".
After initialization is complete, user should note that one
set of control bits will be used for both receiver and
transmitter making individual control bit setting unnecessary. Data reception starts when serial input signal changes
from marking (logic "1 ") to spacing (logic "0") which initiates start bit. The start bit is valid if, after transition from
logic "1" to logic "0", the Slline continues to be at logic "0",
when center sampled, 8 clock pulses later. If, however,
line is at a logic "1" when center sampling occurs, the start
bit verification process will be reset. If the Serial Input line
transitions from a logic "1" to a logic "0" (marking to
spacing) when the 16x clock is in a logic "1" state, the bit
time for center sampling will begin when the clock line
transitions from a logic "1" to a logic "O"state. After
verification of a genuine start bit, data bit reception, parity
bit reception and stop bit(s) reception proceeds in an
orderly manner.
While receiving parity and stop bit(s), the receiver will
compare transmitted parity and stop bit(s) with control
data bits (parity and number of stop bits) previously set and
indicate an error by changing the parity error flip flop and/
or the framing errorflip flop to a logic "1 ". It should be noted
that if the No Parity Mode is selected, the PE (parity error)
will be unconditionally set to a logic "0".
Once a full character is received, internal logic looks at the
data available (DAV) signal to determine if data has been
read out. If the DAV signal isata logic"1", the receiver will
assume data has not been read out and the over run flipflop of the status word holding register will be set to a logic
"1". If the DAV signal is at a logic "0", the receiver will
assume that data has been read out. After DAV goes to a
logic "1 ", the receiver shift register is now ready to accept
the next character and has one full character time to
remove the received character.

Yes

DS70005C-10

5-26

AY31015D
FIG. 24 TRANSMITTER BLOCK DIAGRAM

.....

l(j

..,.

(')

~~~~~~~~

TRANSMITTER
BUFFER EMPTY
TRANSMITTER
SHIFT REGISTER

SERIAL
OUTPUT

ENDOF
CHARACTER

FIG. 25 RECEIVER BLOCK DIAGRAM

TBMTF/F

5-27

DS70005C-11

AY31015D
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.

PART NUMBERS

AY31015D -

~
I
I

'------I

Temperature
Range:

Device:

DS70005C·12

Package:

Blank

AY31015D

5·28

Plastic DIP
PLCC

O· C to 70· Conly

UARfT

AY58116/8116T
AY58136/8136T

Microchip

Dual Baud Rate Generator
FEATURES

PIN CONFIGURATIONS
18 LEAD DUAL INLINE

• Single +5V power supply
• On-chip crystal oscillator 8116/8136 or external
frequency input 8116/8116T/8136/8136T
Direct compatibility with UART/USRT
Dual selectable 16x clock outputs
• High frequency reference output (Available only on
8136/8136T)
• Reprogrammable ROM allowing generation of nonstandard frequencies
• TTL, MaS compatibility
Pin for pin and functionally compatible with SMC's
COM 8116/8116T/8136/8136T
• Microchip Technology Advanced N-Channel Silicon
Gate Process

AY58116/8116T

Top View

GND
NC

NC
Top View

DESCRIPTION
XTAUEXTI
Vee
IR
RA
Rs
Re
Ro
STR

The Microchip Technology AY58116/8136 Series is a
very versatile family of Dual Baud Rate Generators. The
AY58116/8116T and AY58136/8136T are pin for pin
functionally equivalent to SMC's COM 8116/8116T and
COM 8136/8136T, respectively.
The AY58116/8136 is designed to generate the full
spectrum of 16 asynchronous Isynchronous data communication frequencies for use with 16x and 32x UARTI
USRT devices.

An on-chip crystal oscillator available on the 8116 and
8136 is capable of providing a master reference frequency. Alternatively, complimentary TTL level clock
signals can be input to pins 1 and 18. The 8116T and
8136T are only suitable for this external TTL reference.
When using TTL outputs to drive the XTAUEXT inputs,
they should not be used to drive other TTL inputs due to
excessive loading which may result in a reduction of
noise immunity.

XTAUEXT2
IT
TA
Ts
Te
To
SIT

GND
fxl4

frequency (f,) is used by the 8136/8136T to provide a
high frequency output (fj4).
The 8116/8136 family allows generation of other frequencies with the use of its two divisor ROMs which
contain 16 divisors, each 19 bits wide, allowing for up to
32 different divisors on custom parts.
Ex1ernally strobed data latches are used to hold the
divisor select bits, RA- RD and TA-T D' The strobe inputs,
STR or STT, allow data to pass directly through the data
latch when in the high state. A new frequency is initiated
within 3.5 Ilsec of a change in any of the four divisor
select bits read by the device. Pull-up resistors are
provided on the divisor select inputs which are not
present on the strobe inputs.

Dividers are used on the output of the oscillatorlbuffer
which generate the output frequencies f, and fRo These
dividers can divide any integer from 6 to 219 + 1, inclusive. When using an even divisor, the output will be
square; an odd divisor will cause the output to be high
longer than it is low by one clock period (lIf,). The clock

XTAUEXT2
IT
TA
Ts
Tc
To
SIT

XTAUEXTI
Vee
IR
RA
Rs
Re
Ro
STR

5-29

OS70004C-1

AY58116/8116T
AY58136/8136T
PIN FUNCTIONS
Signal

Pin Number

Function

XTAUEXT1

Input is either one pin of the crystal package or one polarity of
the external input.

Vcc

Positive power supply - normally +5V.

This output runs at a Irequency selected by the Receiver divisor
select data bits.

4-7

RA,RB,Rc,R o

These inputs, as shown in Table 1, select the receiver output
frequency, IR.

STR

A high level input strobe loads the receiver data (RA,RB,Rc,R o)
into the receiver divisor select register. This input may be
strobed or hard-wired to a high level.

NC orf/4

NC (8116/8116T), 1,14 (8136/8136T).

GND

Ground.

STT

A high level inut strobe loads the transmitter data
(TA,TB,Tc,To) into the transmitter divisor select register.
This input may be strobed or hard-wired to a high level.

13-16

To,Tc,TB,TA

These inputs, as shown in Table 1, select the transmitter output
frequency, IT'

This output runs at a frequency selected by the transmitter
divisor select data bits.

XTAUEXT2

This input is either the other pin 01 the crystal package or the
other polarity of the external input.

TIMING DIAGRAM
tpw

---~

V,H
STROBE

r----tos----~

V,H
DIVISOR
SELECT
DATA
VIL

DS70004C-2

5-30

AY58116/8116T
AY58136/8136T
* Exceeding these ratings could cause permanent
damage to the device. This is a stress rating only and
functional operation of this device at these conditions is
not implied. Operating ranges are specified in Standard
Conditions. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

ELECTRICAL CHARACTERISTICS
Maximum Ratings·
Operating Temperature Range ............... O°C to +70°C
Storage Temperature Range ............. -55°C to + 150°C
Positive Voltage on any Pin,
with respect to ground ................................... +8.0V
Negative Voltage on any Pin,
with respect to ground .................................... -0.3V

Data labeled "typical" is presented for design guidance
only and is not guaranteed.

Standard Conditions (unless otherwise noted):
TA = O°C to +70°C, Vee = +5V ±5%

DC CHARACTERISTICS
Characteristic

Input Voltage Levels
Low Level
High Level
Output Voltage Levels
Low Level
High Level
Input Current
Low Level
Input Capacitance All inputs
Power Supply Current

Sym

Min

Typ

Max

Unit

V
V

excluding XT AL inputs

V
V
V

10L = 1.6mA, for f/4,
10L = 3.2mA, for fR' fT
10H = -100llA

-0.1
10
50

rnA
pF
rnA

Y'N = GND, RA-Ro & TA-To only
Y'N = GND, excluding XTAL inputs

Unit

0.8

2.0

VOL

0.4
0.4

V OH

3.5

V ,L
V ,H

I'L
lee

Min

Typ

Max

5.1
DC

Conditions

AC CHARACTERISTICS
Characteristic

Sym

Clock Frequency
Strobe Pulse Width
Input Set-up Time
Input Hold Time
Strobe to new Frequency
Delay

fx
tpw
tos
tOH

0.01
150
200
50

Conditions

XTAUEXT, 50% Duty Cycle ±5%

MHz
ns
ns
ns

3.5

@fx=5.0MHz

CRYSTAL SPECIFICATIONS
Temperature range O°C to +70°C
Series resistance ::;500
Series resonant
Overall tolerance ± 0.01%

5-31

DS70004C-3

AY58116/8116T
AY58136/8136T

EXTERNAL INPUT OPERATION AY58116/
8116T/8136/8136T

CRYSTAL OPERATION
AY58116/8136

lSp-

74XX

74XX
TTL

TTL

,J{»:d'l-

<:"""T'
1S

74XX - TOTEM POLE OR OPEN COLLECTOR
OUTPUT (EXTERNAL PULL-UP
RESISTOR REQUIRED)

BLOCK DIAGRAM: AY58116/8116T/8136/8136T
STT
TA
T8
Te

9
.

D-LATCH

FREQUENCY
DECODE
AND
CONTROL

XTAU

EXTl
XTAL
OSCI

CLOCK
BUFFER
XTAU
EXT2

RA
R8
Re

RD
STR

DS70004C-4

5-32

AY58116/8116T
AY58136/8136T
Table 1 Output Frequency AY58116/8116T/8136/8136T
REFERENCE FREQUENCY = 5.068800 MHz
Divisor
Select
DCBA

Desired
Baud
Rate

Clock
Factor

Desired
Frequency
(KHz)

Divisor

Actual
Baud
Rate

Actual
Frequency
(KHz)

Deviation

0000

50.00

16X

0.80000

6336

50.00

0.800000

0.0000%

0001

75.00

16X

1.20000

4224

75.00

1.200000

0.0000%

0010

110.00

16X

1.76000

2880

110.00

1.760000

0.0000%

0011

134.50

16X

2.15200

2355

134.52

2.152357

0.0166%

0100

150.00

16X

2.40000

2112

150.00

2.400000

0.0000%

0101

300.00

16X

4.80000

1056

300.00

4.800000

0.0000%

0110

600.00

16X

9.60000

528

600.00

9.600000

0.0000%

0111

1200.00

16X

19.20000

264

1200.00

19.200000

0.0000%

1000

1800.00

16X

28.80000

176

1800.00

28.800000

0.0000%

1001

2000.00

16X

32.00000

158

2005.06

32.081013

0.2532%

1010

2400.00

16X

38.40000

132

2400.00

38.400000

0.0000%

1011

3600.00

16X

57.60000

3600.00

57.600000

0.0000%

1100

4800.00

16X

76.80000

4800.00

76.800000

0.0000%

1101

7200.00

16X

115.20000

7200.00

115.200000

0.0000%

1110

9600.00

16X

153.60000

9600.00

153.600000

0.0000%

1111

19200.00

16X

307.20000

19800.00

316.800000

3.1250%

5-33

DS70004C-5

AY58116/8116T
AY58136/8136T
Table 1 (Cont.) Output Frequency AY58116/8116T/8136/8136T-005
REFERENCE FREQUENCY = 4.915200 MHz
Divisor
Select
DCBA

Desired
Baud
Rate

Clock
Factor

Desired
Frequency
(KHz)

Divisor

Actual
Baud
Rate

Actual
Frequency
(KHz)

Deviation

0000

50.00

16X

0.80000

6144

50.00

0.800000

0.0000%

0001

75.00

16X

1.20000

4096

75.00

1.200000

0.0000%

0010

110.00

16X

1.76000

2793

109.93

1.758983

0.0100%

0011

134.50

16X

2.15200

2284

134.50

2.152000

0.0000%

0100

150.00

16X

2.40000

2048

150.00

2.400000

0.0000%

0101

300.00

16X

4.80000

1024

300.00

4.800000

0.0000%

0110

600.00

16X

9.60000

512

600.00

9.600000

0.0000%

0111

1200.00

16X

19.20000

256

1200.00

19.200000

0.0000%

1000

1800.00

16X

28.80000

171

1796.49

28.743859

0.1949%

1001

2000.00

16X

32.00000

154

1994.81

31.916883

0.2597%

1010

2400.00

16X

38.40000

128

2400.00

32.000000

0.0000%

1011

3600.00

16X

57.60000

3614.11

57.825882

0.3921%

1100

4800.00

16X

76.80000

4800.00

76.800000

0.0000%

1101

7200.00

16X

115.20000

7144.19

114.306976

0.7751%

1110

9600.00

16X

153.60000

9600.00

153.600000

0.0000%

1111

19200.00

16X

307.20000

19200.00

307.200000

0.0000%

DS70004C-6

5-34

AY58116/8116T
AY58136/8136T
Table 1 (Cont.) Output Frequency AY58116/8116T/8136/8136T-006
REFERENCE FREQUENCY
Divisor
Select
DCBA

Desired
Baud
Rate

Clock
Factor

Desired
Frequency
(KHz)

Divisor

=5.068800 MHz
Actual
Baud
Rate

Actual
Frequency
(KHz)

Deviation

0000

50.00

32X

1.60000

3168

50.00

1.60000

0.0000%

0001

75.00

32X

2.40000

2112

75.00

2.40000

0.0000%

0010

110.00

32X

3.52000

1440

110.00

3.52000

0.0000%

0011

134.50

32X

4.30400

1177

134.52

4.30600

0.0600%

0100

150.00

32X

4.80000

1056

150.00

4.80000

0.0000%

0101

200.00

32X

6.40000

792

200.00

6.40000

0.0000%

0110

300.00

32X

9.60000

528

300.00

9.60000

0.0000%

0111

600.00

32X

19.20000

264

600.00

19.20000

0.0000%

1000

1200.00

32X

38.40000

132

1200.00

38.40000

0.0000%

1001

1800.00

32X

57.60000

1800.00

57.60000

0.0000%

1010

2400.00

32X

76.80000

2400.00

76.80000

0.0000%

1011

3600.00

32X

115.20000

3600.00

115.20000

0.0000%

1100

4800.00

32X

153.60000

4800.00

153.60000

0.0000%

1101

7200.00

32X

230.40000

7200.00

230.40000

0.0000%

1110

9600.00

32X

307.20000

9900.00

316.80000

3.1250%

1111

19200.00

32X

614.40000

19800.00

633.60000

3.1250%

5-35

0570004C·7

AY58116/8t16T
AY58136/8136T
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.

PART NUMBERS

AY5 81X6 TIP XXX

T IT___~

005
006

MODEL
PACKAGE

Plastic DIP

On-Chip Oscillator
TTL Capability

1
3

Pin 8 = NC
Pin 8 = (fx/4)

VERSION

DEVICE

DS70004C-8

5-36

See Output
Frequency Tables

AY581X6

Dual Baud Rate Generator

AY58126/8126T
AY58146/8146T

Microchip

SINGLE BAUD RATE GENERATOR
FEATURES
PIN CONFIGURATIONS

• Single +5V power supply
• On-chip crystal oscillator 8126/8146 or external
frequency input 8126/8126T/8146/8146T
• Direct compatibility with UART/USRT
• Choice of 16x clock outputs
• High frequency reference output (Available only on

14 LEAD DUAL INLINE
AY58126/8126T

8146/8146T)

Top View

XTALJEXT1
XTALJEXT2

• Reprogrammable ROM allowing generation of nonstandard frequencies
• TTL, MaS compatibility
• Pin for pin and functionally compatible with SMC's
COM 8126/8126T/8146/8146T
• Microchip Technology Advanced N-Channel Silicon
Gate Process

+5V

lA
11

1::

GND

NC
NC
AY58146/8146T

STT

NC
Top View

DESCRIPTION
XTALJEXT1
XTALJEXT2

The Microchip Technology AY58126/8146 Series is a
very versatile family of Single Baud Rate Generators.
The AY58126/8126T and AY58146/8146T are pin for
pin functionally equivalent to SMC's COM 8126/8126T
and COM 814618146T, respectively.

+5V

NC
GND

NC
NC

The AY58126/8146 is designed to generate the full
spectrum of 16 asynchronous Isynchronous data communication frequencies for use with 16x and 32x UARTI
USRT devices.
low by one clock period (1/f,). The clock frequency (f,)
is used by the 8146/8146Tto provide a high frequency
output (f,/4).

An on-chip crystal oscillator available on the 8126 and
8146 is capable of providing a master reference frequency. AlternativelYi complimentary TTL level clock
signals can be input to pins 1 and 2. The 8126T and
8146T are only suitable for this external TTL reference.
When using TTL outputs to drive the XTAUEXT inputs,
they should not be used to drive other TTL inputs due to
excessive loading which may result in a reduction of
noise immunity.

The 8126/8146 family allows generation of other frequencies with the use of its two divisor ROMs which
contain 16 divisors, each 19 bits wide, allowing for up to
32 different divisors on custom parts.
Externally strobed data latches are used to hold the
divisor select bit TA-To' The strobe input STT allows
data to pass directly through the data latch when in the
high state. A new frequency is initiated within 3.5 usec
of a change in any of the four divisor select bits read by
the device. Pull-up resistors are provided on the divisor
select inputs which are not present on the strobe inputs.

Dividers are used on the output of the oscillatorlbuffer
which generate the output frequency fT" This divider can
divide any integer from 6 to 2'9 + I, inclusive. When
using an even divisor, the output will be square; an odd
divisor will cause the output to be high longer than it is

DS70008C-1

5-37

AV58126/8126T
AV58146/8146T
PIN FUNCTIONS
Function

Signal

Pin Number
1

XTAUEXT1

XTAUEXT2

Vee

GND

6-7

NC orf,!4

STT

10-13

To,Te,TB,TA

Input is either one pin of the crystal package or one polarity of
the external input.
This input is either the other pin of the crystal package or the
other polarity of the external input.
Positive power supply - normally +5V.

Ground.

NC (8126/8126T), f,/4 (8146/8146T).
A high level input strobe loads the transmitter data (TA' TB' Te'
To) into the transmitter divisor select register. This input may
be strobed or hard-wired to a high level.
These inputs, as shown in the Tables p.5 If, select the
transmitter output frequency, fT"
This output runs at a frequency selected by the transmitter
divisor select data bits.

TIMING DIAGRAM

V,H
STROBE

lOS
~

DIVISOR V,H
SELECT
DATA

V'L

~IOH

\.A,

~ 1/

/'1

r 1\

DS70008C-2

5-38

AY58126/8126T
AY58146/8146T
ELECTRICAL CHARACTERISTICS
Maximum Ratings·

• Exceeding these ratings could cause permanent
damage to the device. This is a stress rating only and
functional operation of this device at these conditions is
not implied. Operating ranges are specified in Standard
Conditions. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Operating Temperature Range ............... O°C to +70°C
Storage Temperature Range ............. -55°C to + 150°C
Positive Voltage on any Pin,
with respect to ground ................................... +8.0V
Negative Voltage on any Pin,
with respect to ground .................................... -0.3V

Data labeled "typical" is presented for design guidance
only and is not guaranteed.

Standard Conditions
(unless otherwise noted):
TA = O°C to +70°C, Vee = +5V ±5%

DC CHARACTERISTICS
Characteristic
Input Voltage Levels
Low Level
High Level
Output Voltage Levels
Low Level
High Level
Input Current
Low Level
Input Capacitance All inputs
Power Supply Current

Sym

V ,L
V ,H
VOL
V OH
I'L
Icc

Min

Typ

Max

Unit

0.8

2.0

V
V

excluding XTAL inputs

V
V
V

10L = 1.SmA, for f/4,
10L = 3.2mA, for fR' fT
10H = -100j.lA

-0.1
10
50

mA
pF
mA

Y'N = GND, TA-T D only
Y'N = GND, excluding XTAL inputs

Unit

3.5

0.4
0.4

Min

Typ

Max

0.01
150
200
50

5.1
DC

Conditions

AC CHARACTERISTICS
Characteristic

Sym

Clock Frequency
Strobe Pulse Width
Input Set-up Time
Input Hold Time
Strobe to new Frequency
Delay

fx
tpw
t DS
tDH

3.5

MHz
ns
ns
ns
j.lS

Conditions

XTAUEXT, 50% Duty Cycle ±5%

@fx=5.0MHz

CRYSTAL SPECIFICATIONS
Temperature range O°C to +70°C
Series resistance" 500
Series resonant
Overall tolerance ± 0.01 %

DS70008C-3

5-39

AY58126/8126T
AY58146/8146T

EXTERNAL INPUT OPERATION

CRYSTAL OPERATION

AV58126/8126T18146/8146T

AY58126/8146

74XX >
TIL

74XX
TIL

74XX - TOTEM POLE OR OPEN COLLECTOR
OUTPUT (EXTERNAL PULL-UP
RESISTOR REQUIRED)

BLOCK DIAGRAM: AY58126/8126T/8146/8146T

STI
TA
TB
TC
TD

D-LATCH

FREQUENCY
DECODE
AND
CONTROL

REPROGRAMMABLE
FREQUENCY SELECT
ROM

XTAU
EXT1
XTAL

1------7

ascI
CLOCK
BUFFER

fX/4AY581461
8146T OPTION

XTAU
EXT2

DS70008C-4

5-40

AY58126/8126T
AY58146/8146T

OUTPUT FREQUENCY

AY58126/8126T/8146/8146

Reference Frequency = 5.068800 MHz
--

Divisor
Select
DCBA

Desired
Baud
Rate

Clock
Factor

Desired
Frequency
(KHz)

Divisor

Actual
Baud
Rate

Actual
Frequency
(KHz)

Deviation

0000

50.00

16X

0.80000

6336

50.00

0.800000

0.0000%

0001

75.00

16X

1.20000

4224

75.00

,1.200000

0.0000%

0010

110.00

16X

1.76000

2880

110.00

1.760000

0.0000%

0011

134.50

16X

2.15200

2355

134.52

2.152357

0.0166%

0100

150.00

16X

2.40000

2112

150.00

2.400000

0.0000%

0101

300.00

16X

4.80000

1056

300.00

4.800000

0.0000%

0110

600.00

16X

9.60000

528

600.00

9.600000

0.0000%

0111

1200.00

16X

19.20000

264

1200.00

19.200000

0.0000%

1000

1800.00

16X

28.80000

176

1800.00

28.800000

0.0000%

1001

2000.00

16X

32.00000

158

2005.06

32.081013

0.2532%

1010

2400.00

16X

38.40000

132

2400.00

38.400000

0.0000%

1011

3600.00

16X

57.60000

3600.00

57.600000

0.0000%

1100

4800.00

16X

76.80000

4800.00

76.800000

0.0000%

1101

7200.00

16X

115.20000

7200.00

115.200000

0.0000%

1110

9600.00

16X

153.60000

9600.00

153.600000

0.0000%

1111

19200.00

16X

307.20000

19800.00

316.800000

3.1250%

DS70008C-5

5-41

AY58126/8126T
AY58146/8146T

OUTPUT FREQUENCY

AY58126/8126T/8146/8146T -005
Divisor
Select
DCBA

Desired
Baud
Rate

Clock
Factor

Reference Frequency

Desired
Frequency

(KHz)

Divisor

Actual
Baud
Rate

4.915200 MHz

Actual
Frequency
(KHz)

Deviation

0000

50.00

16X

0.80000

6144

50.00

0.800000

0.0000%

0001

75.00

16X

1.20000

4096

75.00

1.200000

0.0000%

0010

110.00

16X

1.76000

2793

109.93

1.758983

0.0636%

0011

134.50

16X

2.15200

2284

134.50

2.152000

0.0000%

0100

150.00

16X

2.40000

2048

150.00

2.400000

0.0000%

0101

300.00

16X

4.80000

1024

300.00

4.800000

0.0000%

0110

600.00

16X

9.60000

512

600.00

9.600000

0.0000%

0111

1200.00

16X

19.20000

256

1200.00

19.200000

0.0000%

1000

1800.00

16X

28.80000

171

1796.49

28.743859

0.1949%

1001

2000.00

16X

32.00000

154

1994.81

31.916883

0.2597%

1010

2400.00

16X

38.40000

128

2400.00

38.400000

0.0000%

1011

3600.00

16X

57.60000

3614.11

57.825882

0.3921%

1100

4800.00

16X

76.80000

4800.00

76.800000

0.0000%

1101

7200.00

16X

115.20000

7144.19

114.306976

0.7751%

1110

9600.00

16X

153.60000

9600.00

153.600000

0.0000%

1111

19200.00

16X

307.20000

19200.00

307.200000

0.0000%

DS70008C-6

5-42

AY58126/8126T
AY58146/8146T

OUTPUT FREQUENCY
AY58126/8126T/8146/8146T-006

Reference Frequency

5.068800 MHz

~~--

Divisor
Select
DCBA

Desired
Baud
Rate

Clock
Factor

Desired
Frequency
(KHz)

Divisor

Actual
Baud
Rate

Actual
Frequency
(KHz)

Deviation

0000

50.00

32X

1.60000

3168

50.00

1.60000

0.0000%

0001

75.00

32X

2.40000

2112

75.00

2.40000

0.0000%

0010

110.00

32X

3.52000

1440

110.00

3.52000

0.0000%

0011

134.50

32X

4.30400

1177

134.52

4.30600

0.0600%

0100

150.00

32X

4.80000

1056

150.00

4.80000

0.0000%

0101

200.00

32X

6.40000

792

200.00

6.40000

0.0000%

0110

300.00

32X

9.60000

528

300.00

9.60000

0.0000%

0111

600.00

32X

19.20000

264

600.00

19.20000

0.0000%

1000

1200.00

32X

38.40000

132

1200.00

38.40000

0.0000%

1001

1800.00

32X

57.60000

1800.00

57.60000

0.0000%

1010

2400.00

32X

76.80000

2400.00

76.80000

0.0000%

1011

3600.00

32X

115.20000

3600.00

115.20000

0.0000%

1100

4800.00

32X

153.60000

4800.00

153.60000

0.0000%

1101

7200.00

32X

230.40000

7200.00

230.40000

0.0000%

1110

9600.00

32X

307.20000

9900.00

316.80000

3.1250%

DS70008C-7

5-43

AY58126/8126T
AY58146/8146T
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.

PART NUMBERS

MODEL

--I

I
I

005
006

PACKAGE

Plastic DIP

On-Chip Oscillator
TIL Capability

2
4

Pin 8 = NC
Pin 8 = (fx/4)

VERSION

I DEVICE

See Output
Frequency Tables

AY581X6

Dual Baud Rate Generator

DS70008C-8

5-44

AY38910A
AY38912A

Microchip

PROGRAMMABLE SOUND GENERATOR
FEATURES

DESCRIPTION

•
•
•
•

The AY3891 OAl38912A Programmable Sound Generator (PSG) is an LSI circuit which can produce a wide
variety of complex sounds under software control. The
AY3891 OAl38912A is manufactured in Microchip Technologys N-Channel Ion Implant Process. Operation
requires a single +5V power supply, a compatible clock,
and a microprocessor controller, such as the PIC series
of 8-bit microcomputers.

•
•
•
•
•

Industry standard programmable sound generator
Register oriented architecture for ease of use
Full software control of sound generation
Easily interfaces to most 8-bit and 16-bit microprocessors
Three independently programmable analog outputs
One or two 8-bit 1/0 ports
Single 5 volt supply
0 0 to 70 0 C operation
40 pin or 28 pin package option

The PSG is easily interfaced to any bus oriented system.
Its flexibility makes it useful in applications such as
music synthesis, sound effects generation, audible
alarms, tone signaling, and personal computer usage.
In order to generate sound effects while allowing the
processor to perform other tasks, the PSG can continue
to produce sound after the inilial commands have been
given by the control processor. The fact that realistic
sound production often involves more than one component is satisfied by the three independently controllable
analog sound output channels can each provide 4 bits of
logarithmic digital to analog conversion, greatly enhancing the dynamic range of the sounds produced.

APPLICATIONS
•
•
•
•
•

Arcade games
Warning alarms
Special effects
Personal computers
Music synthesis

PIN CONFIGURATION

Top View
28 LEAD DUAL INLINE - AY38912A

40 LEAD DUAL INLINE - AY38910A
Vss (GND)
No Connect
Analog Channel B
Analog Channel A
No Connect
IOB7
IOB6
IOB5
IOB4
IOB3
IOB2
IOB1
lOBO
IOA7
IOA6
IOA5
IOA4
IOA3
IOA2
IOA1

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

]
]

Vee (+5V)
No Connect
] Analog Channel C
] DAO
] DA1
] DA2
] DA3
] DA4
] DA5
] DA6
] DA7
] BC1
] BC2
] BDIR
] No Connect
] A8
] A9
] RESET
] Clock
] lOAD

5-45

Analog Channel C
No Connect
Vcc(+5V)
Analog Channel B
Analog Channel A
Vss (GND)
IOA7
IOA6
IOA5

10M
IOA3
IOA2
IOA1
lOAD

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

]
]
]
]
]
]
]
]
]
]
]
]
]
]

DAD
DA1
DA2
DA3
DA4
DA5
DA6
DA7
BC1
BC2
BDIR
A8
RESET
Clock

DS5000BC-1

AY3891 OAI AY38912A
DESCRIPTION (CTD.)
All circuit control signals are digital in nature and may
be provided directly by a microprocessor/microcomputer. Therefore, one PSG can produce the full
range of required sounds with no change in external

circuitry. Since the frequency response of the PSG
ranges from sub-audible at its lowest frequency to
post-audible at its highest frequency, there are few
sounds which are beyond reproduction.

A Y389XXA BLOCK DIAGRAM
A9

BOIR BC2

DA7-DAO

BC1

RESET

CLOCK

RESET
REGISTERS

LATCHI
DECODER

(16 AEADIWRITE

CONTROL REGISTERS)

ANALOG
CHANNELS

PIN FUNCTIONS
DA7-DAO (Input /Output/High Impedence)

Address 9. Address 8

Data/Address Bits 7-0:

A8 (input):

Pins 30-37 (AY38910A)
Pins 21-28 (AY38912A)
These 81ines comprise the 8-bit bidirectional bus used by
the microprocessor to send both data and addresses to
the PSG and to receive data from the PSG. In the
address mode, DA3-DAO select the internal register
address (0-17.) and DA7-DA4 in conjunction with address inputs A9 and A8, form the chip select function.
When the high order address bits are "incorrect", the
bidirectional buffers are forced to a high impedence state.

DS50008C-2

Pin 25 (AY38910A)
Pin 17 (AY38912A)
A9 (input):
Pin 24 (AY38910A)
Not available (AY38912A)
High order address bits A9 and A8 are fixed to recognize
a "01 "code. They may be left unconnected as each is
provided with either an on chip pull-down (A9) or pull-up
(A8) resistor. In noisy environments, however, it is
recommended that A9 and A8 be tied to external ground
and +5V respectively if they are not to be used.

5-46

AV38910A/AV38912A
RESET (Input)

For example, if these bus control signals are generated
directly by a microprocessor to control all bus operations internal and external to the PSG, then the following Bus Control Function Table applies.
Interfacing to a processor simply requires simulating
the decoding shown in the Function Table. The redundancies in the PSG functions vs. bus control signals
can be used as an advantage in that only four of the
eight possible decoded bus lunctions are required by
the PSG. This could reduce the programming of the
bus control signals to the following Simplified Bus
Control Function Table which would only require that
the processor generate two bus control signals (BDIR
and BC1, with BC2 tied to +5V).

Pin 23 (AY38910A)
Pin 16 (AY38912A)
For initialization/power-on purposes, applying a low level
input to the RESET pin will reset all registers to Oe. The
RESET pin is provided with an on-chip pull-up resistor.

CLOCK (Input)
Pin 22 (AY38910A)
Pin 15 (AY38912A)
This TTL compatible input supplies the timing reference
for the Tone, Noise, and Envelope Generators.

BDIR. BC2. BC1 (Inputs)
Pins 27,28,29 (AY38910A)
Pins 18,19,20 (AY38912A)
The Bus DIRection, Bus Control 2 and Bus Control 1 are
used to control the PSG.

BUS CONTROL FUNCTION TABLE
BOIR

Inputs
BC2

BC1

Microprocessor
Function

0
0

0
1

NACT
ADAR

INACTIVE. See 010 (lAB) below.
LATCH ADDRESS. See 111 (INTAK) below.

lAB

DTB

1
1
1

0
0
1

0
1
0

BAR
DW
DWS

INTAK

INACTIVE. The PSG/CPU bus is inactive. DA7-DAO are
in a high impedance state.
READ FROM PSG. This signal causes the contents of
the register which is currently addressed to appear on the
PSG/CPU bus. DA7-DAO are in the output mode.
LATCH ADDRESS. See 111 (INTAK) below.
INACTIVE. See 010 (lAB) above.
WRITE TO PSG. This signal indicates that the bus
contains register data which should be latched into the
currently addressed register. DA7 -DAO are in the input
mode.
LATCH ADDRESS. This signal indicates that the bus
contains a register address which should be latched in the
PSG. DA7-DAO are in the input mode.

PSG
Function

SIMPLIFIED BUS CONTROL FUNCTION TABLE
BOIR

Inputs
BC2

0
0
1

1
1
1

PSG
Function

BC1

0
1
0
1

INACTIVE.
READ FROM PSG.
WRITE TO PSG.
LATCH ADDRESS.

PSG

FROM
PROCESSOR

r-~
+5 -

BC2

-BC'
'----

5-47

DS50008C-3

AY38910A/AY38912A
Analog Channel A, B, C (Outputs)
Pins 4,3,38 (AY38910A)
Pins 5,4,1 (AY38912A)
Each of these signals is the output of its corresponding
digital to analog converter and provides 1V peak-peak
(max) signal representing the complex sound waveshape generated by the PSG.

No Connect
Pins 2,5,26,39 (AY38910A)
Pins 2 (AY38912A)
These pins are for Microchip Technology test purposes
only and should be left open. Do not use as tie-points.

Pins 40 (AY38910A)
Pin 3 (AY38912A)
Nominal +5 Volt power supply to the PSG.

The four low order address bits select one of the 16
registers (ROs-R17s). The six high order address bits
function as chip selects to control the tri-state bidirectional buffers (when the high order address bits are
incorrect, the bidirectional buffers are forced to a high
impedance state). High order address bits A9, A8 are
fixed in the PSG design to recognize a "01" code; high
order address bits DA7-DA4 are programmed to recognize only a "0000" code. All addresses are latched
internally. This internally latched address is updated
and modified on every latch address signal presented to
the PSG via the BDIR, BC2 and BC1 inputs. A latched
address will remain valid until the receipt of a new
address, enabling multiple reads and writes of the same
register contents without the need for redundant readdressing.
Conditioning of the Register Address Latch/Decoder
and the Bidirectional Buffers to recognize the bus function
required (Inactive, Latch Address, Write Data) is accomplished by the Bus Control Decode block.

Pin 1 (AY38910A)
Pin 6 (AY38912A)
Ground reference for the PSG.

Sound Generating Blocks

ARCHITECTURE

The basic blocks in the PSG which produce the programmed sounds include:

The AY38910AlAY38912A is a register oriented Programmable Sound Generator (PSG). Communication
between the processor and the PSG is based on the
concept of memory-mapped I/O. Control commands
are issued to the PSG by writing to 16 memory-mapped
registers. Each of the 16 registers within the PSG is
also readable so that the microprocessor can determine, as necessary, present states or stored data values. All functions of the PSG are controlled through the
16 registers which, once programmed, generate and
sustain the sounds, thus freeing the system processor
for other tasks.

Tone Generators

Noise Generator

Mixers

Envelope Generator

Register Array
The principle element of the PSG is the array of 16 read/
write control registers. These 16 registers look to the
CPU as a block of memory and as such occupy a 16
word block out of 1,024 possible addresses. The 10
address bits (8 bits on the common data/address bus,
and 2 separate address bits) are decoded as follows:

Amplitude Control

0/A Converters

THROUGH

Produce the basic square wave
tone frequencies for each channel (A, B, C).
Produces a pulse width modulated pseudo-random square
wave output.
Combine the outputs of the Tone
Generators and the Noise Generator; per channel (A,B,C).
Produces an envelope pattern
which can be used to amplitude
modulate the output of each
Mixer.
Provides the 0/A Converters
with either a fixed or variable
amplitude pattern. Fixed amplitude is under direct CPU
control. Variable amplitude is
accomplished via the output of
the Envelope Generator.
The three 0/A Converters each
produce a 161evel (max) output
signal as determined by the
Amplitude Control.

'~------.-------~/\-------.------~I

HIGH ORDER

LOW ORDER

(Chip Select)

(Register No.)

DS5000BC-4

5-48

AV38910A/AV38912A
OPERATION

TUNE REGISTERS

Since all PSG functions are processor controlled by
writing to the internal registers (see table). A detailed
description of the PSG operation may best be accomplished by relating each PSG function to control of the
corresponding register. The function of creating or
programming a specific sound effect logically follows
the control sequence shown in the figure below.

Coarse Tune
Register

Channel

Rl
R3

Fine Tune
Register

A
B

RO
R2

Tone Generator Control CRO - RS)

Noise Generator Control C R6)

The frequency of each square wave generated by the
three Tone Generators (one each for Channels A, B,
and C) is obtained by first dividing the input clock by 16
then by further dividing the result by the programmed 12
bitTone Period value. Each 12-bit tone period value is
obtained by combining the contents of the respective
Coarse and Fine Tune registers, as illustrated.

The frequency olthe noise source is obtained by dividing
the input clock by 16, then by further dividing the result
by the programmed 5 bit Noise Period value. This 5 bit
value consists of the lower 5 bits (B4-BO) of register R6,
as illustrated:

NOISE PERIOD REGISTER (R6)

I~I~I~I~I~I~I~I~I

INTERNAL REGISTERS
Operation

Tone Generator RO-R5
Control
Noise Generato R6
Control
Mixer Control
R7

5-bit Noise Period(NP)
to Noise Generator

Not Used

Function
Program tone periods
Program noise period

Enable tone and/or
noise on selected
channels
Rl0s-Rl2s Select fixed or variable
Amplitude
Control
(envelope) amplitudes
Envelope Gene- R13s-R15s Program envelope pe
riod, select envelope
rator Control
pattern

CONTROL SEQUENCE
COARSE TUNE

FINE TUNE

12-bit Tone Period (TP) to Tone Generator

Notes:

1. The period of the output of the tone generator is therefore determined by: 16 x TP x P where P =
the period of the input clock.
2.lf the Coarse and Fine Tune registers are both set to OOOs, the resulting period will be minimum,
ie., the generated tone period will be as if the Coarse Tune register was set to OOOs and the Fine
Tune register set to 001s.

5-49

DS50008C-5

AY3891 OAfAY38912A
Mixer Control· I/O Enable (R7)

I/O PORT TRUTH TABLE

Register R7 is a multi-function ENABLE register which
controls the three Noiserrone Mixers.
The mixers, as previously described, combine the noise
and tone frequencies for each of the three channels.
Thedetermination of combining neither/either/both noise
and tone frequencies on each channel is made by the
state of bits B5-BO of register R7, as illustrated.
The direction (input or output) of the general purpose 1/
ports (I/OA and I/OB) is determined by the state of bits
B7 and B6 of R7, as illustrated.

R7blts
B7B6
0 0
0 1
1 0
1 1

I/O Port Status
I/OB
1I0A
Input
Input
Input
Output
Input
Output
Output
Output

NOTE: Disabling noise and tone does llQ1turn off a
channel. Turning a channel off can only be accomplished by writing all zeros into the corresponding Amplitude Control Register.

Amplitude Control (R1Qa,R11a,R12a}
MIXER CONTROL REGISTER (R7)

The amplitude of the signals generated by each of the
three D/A Converters (one each for Channels A,B, and
C) is determined by the content of the lower bits (B4-BO)
of registers R10a, R11a, and R12a as illustrated.
These five bits consist of a 1-bit mode select ("M" bit) and
a 4-bit "fixed" amplitude level (L3-LO). When the M bit is
low, the output level of the analog channel is defined by
the 4-bit "fixed" amplitude level of the Amplitude Control
Register. This amplitude level is fixed in the sense that
the amplitude
CHANNEL CONTROL

NOISE ENABLE TRUTH TABLE
R7 Bits
B5B4 B2
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Noise Enabled
on Channel
C B A
C B
C
A
C
B A
- B
- - A

Channel
A
B
C

AMPLITUDE CONTROL BITS

- - -

Not Used

TONE ENABLE TRUTH TABLE
R7 Bits
B2B1 BO
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

DS50008C-6

Tone Enabled
on Channel
C B A
C B
C
A
C - B A
- B
A

AMPLITUDE CONTROL REGISTER
Amplitude
4 bit fixed
Amplitude Level
Mode
0
o0 o0

- - -

0
1

5-50

··
·

.
.

Note
Amplitude Defined
By LO-L3

1 1 1 1

XX XX

Amplitude Defined
By EO-E3

AV38910A/AV38912A
Envelope Shape/Cycle Control (R15s)

is under direct control of the system processor. When
the M bit is high, the output level of the analog channel
is defined by the 4-bits of the Envelope Generator (bits
E3-EO). The amplitude mode bit can also be thought of
as an "envelope enable" bit.

The Envelope Generator further divides the envelope
period by 16, producing a 16-state per cycle envelope
pattern as defined by the 4-bit counter output, E3, E2, E1
and EO. The particular shape and cycle pattern of any
desired envelope is accomplished by controlling the
count pattern of the 4-bit counter. (See Figure 4 and 5).

Envelope Generator Control
To accomplish the generation of complex envelope
patterns, two independent methods of control are provided: first, it is possible to vary the frequency of the
envelope using registers R138 and R148; second, the
relative shape and cycle pattern of the envelope can be
varied using register R158. The following paragraphs
explain the details of the envelope control functions,
describing first the envelope period control and then the
envelope shape/cycle control. (See Figure 1 and 2).

This envelope shape/cycle control is contained in the
lower4 bits (83-80) of register R15. Each ofthese 4 bits
controls a function in the envelope generator, as illustrated:

ENVELOPE SHAPE/CYCLE CONTROL
Bit

Signal

The frequency of the envelope is obtained by first dividing the input clock by 256, then by further dividing the
result by the programmed 16 bit Envelope Period value.
This 16 bit value is obtained by combining the contents
of the Envelope Coarse and Fine Tune registers, as
illustrated:

HOLD

ENVELOPE SHAPE/CYCLE CONTROL
REGISTER (R15)

Envelope Period Cotrol (R138,R14a)

I"I:~~I",I@~~

\~
To

Envelope
Generator

Function

When this is set high (logic 1)
the envelope is limited to one
cycle, the value of the envelope at the end of the cycle
being held.
ALTERNATE When set high (logic 1) the
envelope counter reverses direction at end of each cycle
(i.e. performs as an up/down
counter).
ATTACK
When set high (logic 1) the
envelope counter will count up
(attack). When set low (logic 0)
the counter will count down
(decay).
CONTINUE When set high (logic 1) the
cycle pattern will be defined by
the HOLD bit. When set low
(logic 0) the envelope counter
will resetto 0000 after one cycle
and hold that value.

16-81T ENVELOPE PERIOD (EP) TO ENVELOPE GENERATOR
Envelope Coarse Tune Register (R14)

Envelope Fine Tune Register (R13)

EPa

Refer to Programmable Sound Generator Data Manual for calculation example.
NOTE:

If the Coarse and Fine Tune registers are both set to 0008, the resulting period will be minimum, i.e., the
generated tone period will be as if the Coarse Tune register was set to 0008 and the Fine Tune register set
to 001s.

5-51

DS50008C-7

AY3891 OAIAY38912A
DIA Converter
FIG. 1 ENVELOPE SHAPE /CYCLE

Since the primary use of the PSG is to produce sound for
the non-linear amplitude detection mechanism of the
human ear, the D/A conversion is performed in logarithmic steps with a normalized voltage range from 0 to 1
voll. The specific amplitude control of each of the three
D/A Converters is accomplished by the three sets of 4 bit
outputs of the Amplitude Control block while the Mixer
outputs provide the base signal frequency (Noise and/or
Tone). (See Fig. 3).

OPERATION

R1581TS
82 81 80

0
N
T
N
U
E

A
T
T
A
C

A
L
T
E
R
N
A
T
E

GRAPHIC REPRESENTATION
OF ENVELOPE GENERATOR
OUTPUT E3 E2 E1 EO.

X
X

EP IS THE ENVELOPE
PERIOD (DURATION OF
ONE CYCLE)

FIG.2 DETAIL OF TWO CYCLES (REF. WAVEFORM "1010"IN FIG. 1)

GRAPHIC REPRESENTATION
OF THE DECIMAL VALUES OF
ENVELOPE GENERATOR
OUTPUT E3 E2 E 1 EO

EP
(HIE)

DS50008C-8

------·14-----

5-52

(HIE)

- - - - - - <..
~

AY3891 OAIAY38912A
FIG.3 D/A CONVERTER OUTPUT
NORMALIZED
VOLTAGE
15

1V 15

NOTE:
ENVELOPE ONL YNOISE AND TONES ARE
DISABLE D.-

TYPICAL RATIO FROM ONE STEP
TO THE NEXT LOWER STEP IS

1.2/1.7
13

/ ' " DECIMAL VALUE
OF E3 E2 E1 EO

JI'

EP ENVELOPE PERIOD

FIG. 5 MIXTURE OF THREE TONES
WITH FIXED AMPLITUDES

FIG. 4 SINGLE TONE WITH ENVELOPE
SHAPE/CYCLE PATTERN 1010

5-53

DS5000BC-9

AY3891 OAIAY38912A
ELECTRICAL CHARACTERISTICS
Maximum Ratings·

Standard Conditions

Storage Temperature ......................... -55°C to + 150°C
Operating Temperature ........................... O°C to +70°C
Vee and all other Input/Output
Voltages with Respect to Vss ............... -0.3V to +8.0V

Vee = +5V±5%
Vss=GND
Operating Temperature = O°C to +70°C
(Unless otherwise noted)

'Exceeding these ratings could cause permanent damage to the device. This is a stress rating only and functional operation of this device
at these conditions is not implied. Operating ranges are specified in Standard Conditions. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Data labeled "typical"' is presented for design guidance only and is not
guaranteed.

DC CHARACTERISTICS

Sym

Min

Typ"

Max

Units

Conditions

VIL
VIH

-0.2
2.2

0.8
Vee

V
V

VOL
VOH

0
2.4

0.4
Vee

V
V

IIAL

-10

Vo
lee

70
2.0

SO
90

dB
mA
mA

Test Circuits: Fig. S

200

A
A

VIN = O.4V, Outputs
disabled
VIN = 3.5V

All Inputs
Low Level
High Level
Data Bus (DA7-DAO) Output
Levels
Low Level
High Level
Data Bus(DA7-DAO)
Input Leakage
Analog Channel Outputs
Output Volume
Power Supply Current
Max. Current (per channel)

0.4

I/O Ports
Pull Up Current Low

IlL

IiH

100

VOL
VOHh
VOH1

0
3.5
2.4

0.5
Vee
Vee

V
V
V

VIL
VIH

0
2.4

0.8
Vee

V
V

IILpU
IIHPU

-10
-10

-100
-50

A
A

VIN = O.4V
VIN =2.4V

IIHpd

100

VIN = 2.4V

-10

VIN = O.4V to Vee

Pull Up Current High
- as Outputs (A7-AO, B7-BO)
Low Level
High Level
- as Inputs (A7-AO,B7-BO)
Low Level
High Level
- A8 and Reset Input
Pull up Current
-A9
Pull down Current
- BC1,BDIR, Clock Inputs
Input Leakage

IleL

IOL = 1.SmA, 150pF
IOH = 100 A, 150pF
VIN = 0.4V to Vee

VOUT = 0.7V,
Amplitude Control Set
to F

IIL= 1.SmA
IOHh = 10A
IOH1 = 85A

See
Note 1

"Typical values are at +25°C and nominal voltages.
Note 1:

The active pull-up during an output operation will achieve a logic 1 of 2.4 volts in a time of typically 1
microsecond. However, from 2.4 volts to the high level of 3.5 volts the available pull up current will reduce
significantly and further edge transition will be highly dependent upon load capacitance.

DS50008C-10

5-54

AY38910A/AY38912A
AC CHARACTERISTICS

Sym

Min

fe
tr
tf

Typ**

Max

Conditions

Units

Clock Input
Frequency
Rise Time
Fall Time
Duty Cycle

tBD

2
50
50
60

MHz
ns
ns
%

tRW

500

Fig. 8

tAS
tAH

300
65

ns
ns

Fig. 9

tDW
tDS
tDH

500
300
65

10,000

Fig. 7

Bus Signals (BDIR, BC2, BC1)
Associate Delay Time

Reset
Reset Pulse Width

A9, AS, DA7-DAO
(Address Mode)
Address Setup Time
Address Hold Time

DA7-DAO (Write Mode)
Write Data Pulse Width
Write Data Setup Time
Write Data Hold Time

ns
ns
ns

Fig. 10

200

Fig. 11

DA7-DAO (Read Mode)
Data Access Time from DTB

tDA

DA7-DAO (Inactive Mode)
Tri-state Delay Time from DTB

ITs

100

tPN

Ilsec

I/O Ports (A7-AO, B7-BO)
Pull up Recovery Time

VOH = 3.5V
CLOAD = 100pF
See Note 2

""Typical values are at +25°C and nominal voltages
NOTE 2: Pull up recovery time is defined as the time required for any 110 pin A7-AO or B7-BO to change up to a 100pf
capacitor load from 0.0 volts to 3.5 volts. This recovery time is conditional on the output function of Port A
or Port B being deselected via Bits B7 and B6 of register R10.

Fig. 6

ANALOG CHANNEL
OUTPUT TEST CIRCUIT
R

Analog
Channel 0
Output

1J>:l
(OP AMP Must Not Saturate)

5-55

DS50008C-11

AY3891 OAIAY38912A
TIMING CONDITIONS FOR AC CHARACTERISTICS
FIG. 7 CLOCK AND BUS SIGNAL TIMING

BDIR/
BCl

BDIRI
BCl

FIG. 8 RESET TIMING

RESET

L______
FIG. 9 LATCH ADDRESS TIMING

BUS
CONTROL
DECODE

INACTIVE~

LATCH
ADDRESS

INACTIVE

~
P~~~~EUS X~ES0I'-------_

A9 A8
DA7-DAO

HtAH
, - - - - - - - - - VIH

~ BUS CONTROL

k:Z!

--1
DS50008C-12

'BDIR
1

SIGNALS CHANGING

VIL

BCl
1

50 ns Max., Including Skew.

5-56

AY3891 OAfAY38912A

FIG. 10 WRITE DATA TIMING
BUS
CONTROL
DECODE

INACTIVE

WRITE TO PSG'

1://1
lL2

•

VALID

DATA

IDH

INPUT

BUS CONTROL
SIGNALS CHANGING

r--

-I

INACTIVE

I DW
IDS

PREVIOUS
STATE

~ t:a

'BDIR

BC1

50 ns Max, Including Skew

FIG.11 READ DATA TIMING
BUS
CONTROL INACTIVE
INACTIVE
DECODE ______~~ _______________~LL!---------------

VOH
PREVIOUS
STATE

DA7-DAO

READ

VALID

DATA

TRISTATE

VOL
VOH
VOL

V7i
tL:6

-I

BUS CONTROL
SIGNALS CHANGING

r--

'BDIR

BC1

50 ns Max, Including Skew

5-57

DS50008C-13

AY3891 OAfAY38912A
TIMING DIAGRAMS
State Timing

PSG) consists of several operations (indicated below by
rectangular blocks) defined by the pattern of bus control
signals (BDIR, BC1).
The functional operation and relative timing of the
PSG control sequences are described in the following
sections.

While the state flow for many microprocessors can be
somewhat involved for certain operations, the sequence
of events necessary to control the PSG is simple and
straightforward. Each of the three major state sequences (Latch Address, Write to PSG, and Read from

; 4 - - - - - - - Address and Write Data

to PSG Sequence

;4-------

Address and Read Data
from PSG Sequence

Address PSG Register Sequence

upon the processor used, the program sequence will
normally require four principal microstates: (1) send
NACT (inactive); (2) send INTAK (latch address): (3) put
address on bus; (4) send NACT (inactive).

The Latch Address sequence is normally an integral part
of the write or read sequences but for simplicity is
illustrated here as in individual sequence. Depending

BC1
BUS
CONTROL
DA7-DAO

DS50008C-14

BDIR

NACT

DON'T
CARE

INTAK

NACT

OUTPUT
ADDRESS

DON'T
CARE

5-58

AY38910A/AY38912A

four principal microstates: (1) send NACT (inactive);(2)
put data on bus; (3) send DWS (write to PSG); (4) send
NACT (inactive).

Write Data to PSG Sequence
The Write to PSG sequence, which would normally
follow immediately after an address sequence, requires

BDIR

\1
1
1

BC1
BUS
CONTROL

DA7-DAO

NACT

DON'T
CARE

DWS

OUTPUT DATA
(FROM PSG)

NACT

DON'T
CARE

the read sequence are: (1) send NACT (inactive); (2)
send DTB (read from PSG); (3) read data on bus; (4)
send NACT (inactive).

Read Data From PSG Sequence
As with the Write to PSG sequence, the READ from PSG
sequence would also normally follow immediately after
an address sequence. The four principal microstates of

BDIR

BUS
CONTROL

\11
~

BC1
NACT

DA7-DAO

DTB

NACT

INPUT DATA
(FROM PSG)

5-59

DS50008C-15

AY3891 OAfAY38912A
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.

PART NUMBERS

AY38910A
AY38912A - II P

~-'"

II Temperature

Plastic DIP

O' C to 70' Conly

Range:

AY38910A Sound Generator
AY38912A Sound Generator

Device

DS5000BC-16

5-60

AY8930

Microchip

Enhanced Programmable Sound Generator
FEATURES
PIN CONFIGURATION
40 LEAD DUAL INLINE

• Two Modes Available On-Chip
- A Y8930 Expanded Mode
- AY38910A-Compatible Mode
• Improved Frequency Range
• Three Independently Programmable Analog Output
Channels with Separate Frequency, Duty Cycle and
Envelope Controls for Each Channel
• 5 Bits of Logarithmic Digital-to-Analog Conversion
Per Channel
• Bus Interface Independent of Clock Frequency
• Input Clock FrequenCy: 2 or 4MHz
• Two 8-Bit General Purpose 110 Ports

Vss (GND)
No Connect
Analog Channel B
Analog Channel A
No Connect
lOB?
IOB6
lOBS
IOB4
IOB3
IOB2
lOBI
lOBO
lOA?
IOA6
10AS
10A4
IOA3
10A2
10Al ""1-_ _ _--.J

DESCRIPTION
The AY8930 Enhanced Programmable Sound Generator (EPSG) is an LSI circuit that can produce a wide
variety of complex sounds under software control. The
AY8930 is manufactured in the Microchip Technology
Inc. n-channel silicon gate process. The AY8930 is an
enhanced version of the company's industry standard
AY38910A sound generator. Enhanced features include improved frequency range and noise synthesis
and independent control of each channel's envelope
and duty cycle.

Vcc(+SV)
No Connect
Analog Channel C
DAO
DAI
DA2
DA3
DA4
DAS
DA6
DA?
BCl
BC2 (Not Connected)
BDIR
Select
AS

As
RESET
Clock
10AO

All circuit control signals are digital in nature and can be
provided directly by a microprocessor/microcomputer.
Therefore, one PSG can produce the full range of
required sounds with no change in external circuitry.
Since the frequency response of the PSG ranges from
sub- audible at its lowest frequency to post-audible at its
highest frequency, there are few sounds which are
beyond reproduction with only the simplest electrical
connections.

The PSG is easily interfaced to any bus-oriented system. Its flexibility makes it useful in applications such as
music synthesis, sound effects generation, audible
alarms, tone signalling, and personal computer usage.
In order to generate sound effects while allowing the
processor to perform other tasks, the PSG can continue
to produce sound after the initial commands have been
given by the control processor. The fact that realistic
sound production often involves more than one effect is
satisfied by the three independently controllable analog
sound output channels available in the device. These
analog sound output channels can each provide five bits
of logarithmic digital-to-analog conversion, greatly enhancing the dynamic range of the sounds produced.

Top View

DEVICE ARCHITECTURE
The AY8930 is a register oriented PSG. Communication
between the microprocessor and the PSG is based on
the concept of memory mapped 110. Control commands
are issued to the PSG by writing to these memory
mapped registers. Each of the registers within the PSG
is readable so that the microprocessor can determine,
as necessary, present states or stored data values.

5-61

DS50010C-l

AY8930
PIN FUNCTIONS
DA7·DAO (Input /Output/High Impedance)
bata/Address Bits 7-0: Pins 30-37
These S lines comprise the S-bit bidirectional bus used
by the microprocessor to send both data and addresses
to the PSG, and to receive data from the PSG. In the
address mode, DA3-DAO select the internal register
address (O-Fn) and DA7-DA4 in conjunction with address inputs AS and AS, form the chip select function.
When the high order address bits are "incorrect," the
bidirectional buffers are forced to a high impedance
state.
Address 9, Address 8
AS (input):
Pin 25
AS (input):
Pin 24

High order address bits AS and AS are fixed to recognize a "01" code. They may be left unconnected, as
each is provided with either an on chip pull-down (AS)
or pull-up (AS) resistor. In noisy environments, however, it is recommended that AS and AS be tied to
external ground and +5V respectively, if they are not to
be used.
RESET (Input): Pin 23
For initialization/power-on purposes, applying a low
level input to the RESET pin will reset all registers to O.
(See following table). The RESET pin is provided with
an on-chip pull-up resistor.

DS50010C-2

87 86 85 84 83 82 81

RO/ROA
R1/R1A
R2IR2A
R3/R3A
R4/R4A
RS/RSA
R6/R6A
R7/R7A
RBiRSA
R9/R9A
RAiRAA
RB/RBA
RC/RCA
RD/RDAIRDB
RE/REA
RF/RFA
ROB
R1B
R2B
R3B
R4B
RSB
R6B
R7B
RSB
R9B
RAB
RFB

0
0
0
0
0
0
0
0
#
#
#
0
0
0
0
0
0
0
0
0
#
#
#
#
#
0
X
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
0
X
0

0
0
0
0
0
0
0
0
#
#
#
0
0
0
0
0
0
0
0
0
#
#
#
#
#
0
X
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
#
#
#
#
#
0
X
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
0
X
0

X indicates a don't care.
# indicates that there is no physical memory element
for a bit; if read, a 0 will be returned.
All counter work registers will be initialized to zeros.
- The noise generator 17-bit shift register will be initialized to ones.
- The noise value register will be initialized to zeros.

5-62

AY8930
CLOCK (Input): Pin 22

INPUT CONTROL SIGNALS

This TTL compatible input supplies the timing reference
for the Tone, Noise, and Envelope Generators.

Interfacing to the AY8930 requires the generation of
only two of the three AY38910A input control signals,
BDIR and BC 1. BC2 is shown on the pinout diagram for
reference only; the pin is not internally connected.

CLOCK DIVIDE· SELECT (Input): Pin 26
Select = 0

Input Clock = 4 MHz max.
(Divided internally by 2)
Select = 1
Input Clock = 2 MHz max.
The select pin is provided with an internal pull-up resistor
such that the pin default condition is Select = 1.

INPUT CONTROL SIGNALS
BDIR

BC1

INACTIVE: The PSG/CPU bus is
inactive. DA7-DAO are in a high
impedance state.

READ FROM PSG: This signal causes
the contents of the register which is
currently addressed to appear on the
PSG/CPU bus. DA7-DAO are in the
output mode.

WRITE TO PSG: This signal indicates
that the bus contains register data
which should be latched into the currently addressed register. DA7-DAO are
in the input mode.

LATCH ADDRESS: This signal indicates that the bus contains a register
address which should be latched by the
PSG. DA7- DAO are in the input mode.

BDIR, BC2, BC1 (Inputs): Pins 27, 28, 29
Bus Direction, Bus Control 2*, Bus Control 1
* Not connected
Analog Channel A, B, C (Outputs): Pins 4, 3, 38
Each of these signals is the output of its corresponding
digital-to-analog converter, and provides 1V peak-peak
(max) signal representing the complex sound waveshape generated by the PSG.
No Connect: Pins 2, 5, 39
These pins are for Microchip Technology test purposes
only and should be left open. Do not use as tie-points.
Vee:

Pin 40, Nominal +5 Volt power supply to the
PSG.

Vss:

Pin 1, Ground reference for the PSG.

5-63

Function

DS50010C-3

AY8930
REGISTER ARRAY

Address bits OA7-0AO are latched internally. This internally latched address is updated and modified on every
"latch address" signal presented to the PSG via the BOIR
and BC1 control lines.

The principal element of the A Y8930 is an array of 27
control registers arranged in one bank of 16 and one
bank of 11 registers. These registers occupy 16 address locations of the 1,024-word memory space in
which the PSG resides.

The AY8930 initializes in the AY38910A-compatibility
mode. To utilize the expanded features of the AY8930,
an access code must be input to register R15 upon
program initialization.

The configuration of this register array is shown on the
following pages. Note the two modes of operation:
8910A-compatibility mode and 8930 expanded mode.

Entering a "101" code in bits B7-B5 of register R15
selects the 8e:;o expanded mode. In the 8930 expanded
mode, bit B4=0 (R15) selects BANKAand B4= 1 selects
BANK B. All other bit selections are defined as 891 OAcompatibility mode. Registers R15A and R15B are
mapped into the same physical register.

The registers are addressed via the combination of the
bidirectional data bus (OAO-OA7) and address input
pins A8 and A9.

AS DA7 DA6 DA5 DA4 DA3 DA2 DA1 DAO

OAO-OA3

Switching modes causes loss of all register data from the
previous mode. All registers will be initialized except for
the Mode Select code of R15.

These four low-order address bits are used
to select one of the internal registers within a
bank.

Shown on the next page is the register configuration for
the AY8930. Note that Bank A of the expanded mode is
virtually identical to the single register array of the 891 OAcompatibility mode.

0A4-0A7,
A8, A9
These six high-order address bits function as
chip selects and are used to position the
register bank(s) within the 1,024-word
memory space. In the deselected state, the
data bus is in the high impedance state.
The address enable fode for bits 0A4-0A7
is all zeros.
Inputs A8 and A9 are enabled by a high on A8
and a low on A9; all other input level combinations result in a deselected condition. Pins
A8 and A9 have an on-chip pull-up and pulldown resistor, respectively, and will assume
the correct logic level if left unconnected.

DS50010C-4

5-64

AY8930
AY8930 REGISTER ARRAY: AY38910A-COMPATIBILITY MODE
Register
Function

BO
8-Bit Fine Tune

Channel A

Tone Period

Channel B

Tone Period

ChannelC

Tone Period

Noise Period

Enable

R10

Channel A Amplitude

R11

Channel B Amplitude

R12

Channel C Amplitude

R13

R14

Envelope Period

R15

Envelope Shape/Cycle

R16

I/O PortA

8-Bit Parallel I/O on Port A

R17

I/O Port B

8-Bit Parallel I/O on Port B

4-Bit Coarse Tune

4-Bit Coarse Tune
5-Bit Period Control

8-Bit Fine Tune

8-Bit Coarse Tune
MODE SELECT

5-65

HOLD

DS50010C-5

AY8930
AY8930 REGISTER ARRAY: EXPANDED CAPABILITY MODE - BANK A
Bit

Hex

Octal

ROA

Channel A

R1A

Tone Period

R2A

ChannelB

R3A

Tone Period

R4A

ChannelC

R5A

Tone Period

8-Bit Coarse Tune

R6A

Noise Period

8-Bit Noise Period

R7A

Enable

R8A

R10A

Channel A Amplitude

R9A

R11A

Channel B Amplitude

RAA

R12A

Channel C Amplitude

RBA

R13A

Channel A

RCA

R14A

Envelope Period

RDA

R15A

Bank AlB: Envelope A

ATT.

ALT.

HOLD

REA

R16A

1/0 PortA

8-Bit Parallel 1/0 on Port A

RFA

R17A

1/0 Port B

8-Bit Parallel 1/0 on Port B

8-Bit Fine Tune
8-Bit Coarse Tune
8-Bit Fine Tune
8-Bit Coarse Tune
8-Bit Fine Tune

INIOUT

DS50010C-6

TONE

NOISE

8-Bit Fine Tune
8-Bit Coarse Tune
1

5-66

CONT.

AY8930
AY8930 REGISTER ARRAY: EXPANDED CAPABILITY MODE - BANK B
Register
Function

8-Bit Fine Tune

ROB

ChannelB

R1B

Envelope Period

R2B

ChannelC

R3B

Envelope Period

R4B

Envelope Shape/Cycle B

ATT.

ALT.

HOLD

R5B

Envelope Shape/Cycle C

ATT.

ALT.

HOLD

R6B

Channel A Duty Cycle

R7B

Channel B Duty Cycle

R8B

Rl0B

Channel C Duty Cycle

R9B

RllB

Noise "And" Mask

RAB

R12B

RBB

R13B"

RBC

R14B"

RBD

R15B

RBC

R16B"

RBF

RHB"

8-Bit Coarse Tune
8-Bit Fine Tune
8-Bit Coarse Tune

" Not accessible in AY8930 mode.
NOTE: All unused bits will be read back as "0".

5-67

DS50010C-7

AV8930
SOUND GENERATING BLOCKS

Operation

Registers'

The basic blocks in the PSG that produce the programmed
sounds include:

Tone Generator
Control

ROA-R5A

Program tone
periods

Tone
Generators

Duty Cycle
Control

R6B-RBB

Select duty cycle

Noise Generator
Control

R6A,
R9B-RAB

Program noise
period

Mixer Control

R7A

Enable tone/noise
on selected
channels

Ainplftude
Control

RBA-RAA

Select "fixed" or
"variable"
amplitudes

Envelope
Generator
Control

RBA-RDA,
ROB-R5B

Program envelope
period and
envelope pattern

Noise
Generator

Mixers

Amplitude
Control

Envelope
Generators

D/A
Converters

- Produce the basic pulse tone frequencies
for each channel (A, B, C).

- Produces a frequency modulated pseudorandom noise output.
- Combine the outputs of the tone generators and the noise generator. One for each
channel (A, B, C).

- Provides the D/A converters with either a
fixed or, variable amplitude pattern. The
fixed amplitude is under direct CPU control; the variable amplitude is accomplished
by using the output of the envelope generators, one for each channel (A, B, C).

- Produce an envelope pattern that can be
used to amplitude modulate the output of
the mixer, one for each channel (A, B, C).

Produces a 32-bit
output signal

'All registers referenced are for the AY8930 Expanded Mode.

TONE GENERATOR CONTROL
- The three D/A converters each produce
up to a 32-level output signal as determined by the amplitude control.

OPERATION
Since all functions of the PSG are controlled by a host
processor via a series of register loads, a detailed description of the PSG operation can best be accomplished by
relating each PSG function to its corresponding register.
The function of creating or programming a specific sound
or sound effect logically follows the control sequence
listed:

DS50010C-8

D/A Converters

Function

Each analog output channel has associated with it
two registers which specify the tone period for that
channel, the coarse tune and the fine tune registers.
The tone period for each channel is obtained by
combining the coarse and fine tune registers as
shown.
Note that the value programmed in the combined
coarse and fine tune registers is a period value- the
higher the value in the registers, the lower the resultant frequency.
Coarse Tune
Registers

Channel

R1A
R3A
R5A

A
B
C

Fine Tune
Register
ROA
R2A
R4A

AV8930
12-BIT TONE PERIOD (TP) VALUE:
AY38910A-COMPATIBILITY MODE

NOTE:
The percent duty cycles refers to the high (logic high)
portion of the duty cycle. The low portion is then 100%
duty cycle. For example, a 10%duty cycle is then 10%
up and 90% down, as shown below.

COARSE TUNE

16-BIT TONE PERIOD (TP) VALUE:
A Y8930 EXPANDED MODE

In AY891 OA-compatibility mode, the duty cycle is fixed
at 50%. The capability for a variable duty cycle exists
only in the expanded AY8930 mode.
In order to change a duty cycle, the appropriate duty
cycle register must be updated. The new duty cycle will
then remain constant at this value until the duty cycle
register is modified. The new duty cycle value will take
effect immediately. This may result in one period with
a "random" duty cycle at the time the register is
updated.

PERIOD OF OUTPUT = 16 x TP x P
WHERE P = PERIOD OF INPUT CLOCK AND
TP = DECIMAL EQUIVALENT OF TONE PERIOD BITS
TP15-TPO

If the coarse and fine tune registers are both set to OOh, the
resulting period will be minimum, i.e. the generated tone
period will be as if the coarse tune register were set to OOh
and the fine tune register were set to 01 h. The counter will
count the period valuedown to zero. When zero is reached,
the period value will be reloaded into the counter.

DUTY CYCLE CONTROL
The duty cycle of each pulse generated by the three tone
generators is controlled by an associated 4-bit duty cycle
register (R6B, R7B, and R8B).

NOISE GENERATOR CONTROL
AY38910A-COMPATIBILITY MODE:
Noise is generated by a 17-bit polynominal shift register. The period of the clock to this shift register is
specified by the 8-bit binary value NP.
The noise period value is derived from the lower five
bits (B4-BO) of the noise period register (R6) as shown.
NOISE PERIOD REGISTER (R6)

The following duty cycles are selectable:
%
Duty Cycle
3.125%
6.25 %
12.50%
25.00%
50.00%
75.00%
87.50%
93.75%
96.875%

Duty Cycle

0
1
2
3
4
5
6
7
8'

0000
0001
0010
0011
0100
0101
0110
0111
1000

5 BIT NOISE PERIOD (NP) VALUE

NOTE:
As with the tone period, the lowest period value is 01 h
(divide by 1), an entry of OOh will have the same value
asOl h;the highest period value is 1Fh (divideby3110).

'NOTE: Any value greater than 810 decodes as an 810.

5-69

DS50010C-9

AY8930
AY38910A-COMPATIBILITY MODE NOISE BLOCK DIAGRAM

TO MIXER

R6/32

NOMINAL
VALUE

125 kHz

NOISE PERIOD
REGISTER
(B4-BO)

SHIFT ENABLE

[_B_16_-_-_-_-_--;~I------'i

RIGHT SHIFT

AY8930 EXPANDED MODE:

NOISE PERIOD REGISTER (R6A)

In the AY8930 expanded mode, noise is generated
using a 17-bit polynomial shift register, an "AND" mask,
an "OR" mask, and an 8-bit noise period value. The least
significant byte ofthe polynomial shift register is logically
AND'ed with the "AND" mask specified in Register 11 B,
then logically OR'ed with the "OR" mask specified in
Register 12B. The result is stored in a temporary register
which is clocked each time the counter associated with
the 8-bit noise period register (R6A) reaches zero.
When the noise value reaches zero, a new value is
fetched from the polynomial shift register and the process is repeated. The noise output is toggled each time
the noise value reaches zero.

7
8 BIT NOISE PERIOD (NP) VALUE

The lowest period value is 01 h (divide by 1), an entry OOh
will have the same value as 01 h; the highest period value
is FFh (divide by 25510.)

AY8930 EXPANDED MODE NOISE BLOCK DIAGRAM
R6A1256

iT]
1------1>---LT-

TOMIXER

250 kHz
NOISE PERlbD REGISTER
(B7-BO)

SHIFT ENABLE
B16 - - - B9 B8 B7 B6 B5 B4 B3 B2 B1 BO

ENABLE WHEN
NOISE VALUE = 0

RIGHT SHIFT

DS50010C-10

5-70

AY8930
MIXER CONTROL - I/O ENABLE

Disabling noise and tone does D.Q1 turn off a channel.
Turning off a channel can only be accomplished by
writing all zeros into corresponding amplitude control
register.

Register 7A is a multi-function Enable register which
controls the three NoiselTone Mixers and the two general purpose I/O Ports. The mixers, as previously
described, combine the noise and tone frequencies for
each of the three channels. The determination of
combining neither/either/both noise and tone frequencies on each channel is made by the state of bits B5-BO
of R7A.

I/O PORT DATA STORE
Registers REA and RFA function as intermediate data
storage registers between the PSG/CPU data bus (DAODA7) and the two I/O ports (IOAO-IOA7, IOBO-IOB7).
Both I/O ports are available on the AY8930.

The direction (input or output) olthe two general purpose
I/O Ports (lOA and lOB) is determined by the state of bits
B7 and B6 of R7 A.

Using registers REA and RFA for the transfer of I/O data
has no effect on sound generalion.

These functions are illustrated in the following:

To output data from the CPU Bus to a peripheral device
connected to I/O port A:

MIXER CONTROL - I/O ENABLE
REGISTER (R7A)

NOISE
ENABLE

INPUT ENABLE

TONE
ENABLE

Noise Enable Truth Table

R7A Bits
B5 B4 B3
0
0
0
0
1
1
1
1

1. Address the enable register (R7A).
2. Set the port A direction bit to output (write "1" to bit B6
ofR7A).
3. Address the I/O port A register (REA).
4. Write data to I/O port A register. The data will pass
through the PSG I/O port A register to the I/O port bus.

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Noise
Enabled
On Channel
C
C
C
C

B
B

To input data from I/O port A to the CPU bus:

Tone Enable Truth Table

R7ABits
B2 B1 BO
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Tone
Enabled
On Channel
B
B

C
C
C
C

B
B

1. Address the enable register (R7A).
2. Set the port A direction bit to input (write a "0" to bit B6
ofR7A).
3. Address the I/O port A register (REA). The contents
of the port register will follow the signals applied to the
I/O port.
4. Read data from I/O port A register. The data will be
transferred from the PSG I/O port A register to the
CPU bus as in a normal read operation.

If a logic 1 has been written to any bit position of register
REA or register RFA and the corresponding I/O pins of
port A or port B are externally pulled below the logic 0,.
(VIL) level, a subsequent CPU read instruction of registers REA or RFA will actually contain a logic 0 in the
pulled down bit positions. The output pins will return to
logic 1 if the pull down condition is removed.

The direction of the I/O Port(s) is determined as follows:
I/O Port Truth Table

1/0 Direction

R7ABits
B7

lOB

lOA

0
0
1
1

0
1
0
1

In
In
Out
Out

In
Out
In
Out

If a logic 0 has been written to any bit pOSition of the I/O
registers and the external world wishes to pull these pins
to a 1, the user should be aware that an impedence
conflict will exist between the pull down transistor and
the external driver.

Note: The Mixer - I/O Control function is identical in
both modes of operation.

5-71

DS5DDt DC-tt

AV8930
AMPLITUDE CONTROL

The following is a chart describing all combinations of
the 6-bit Amplitude Control.

The amplitudes of the signals generated by each of the
three D/A converters (one each for channels A, B, and
C) are determined by the contents of the amplitude
control registers as illustrated in the following:
Amplitude Control
Register #

M L4 L3L2L1 LO
o 0 0 0 0 O' The amplitude is fixed at 1 of 31
0 0 0 0 l' levels as determined by L4, L3,
L2, L1, LO.

Channel

o
The amplitude is variable at 31

R8A
R9A
RAA

A
B
C

X X X X X levels as determined by the output of the Envelope Generator.
(X = Don't care)

NOTE:

AY38910A-COMPATIBILITY MODE:

In the AY38910A-compatibility mode, the externally
driven "fixed" amplitude is limited to a total of 16 possible
levels determined by amplitude bits L4-L 1.

ENVELOPE GENERATOR CONTROL
AMPLITUDE
"MODE"

ENVELOPE PERIOD CONTROL

4-81T "FIXED"
AMPLITUDE LEVEL

The period of the sound envelope, in the AY38910Acompatibility mode, is controlled by two 8-bit registers,
RB and RC (the envelope fine and coarse tune, respectively). In the 8930 expanded mode, each analog output
channel has its own independent sound envelope.
Changes to the envelope period counter will occur at envelope period boundary or when envelope shape/cycle
register is loaded.

• FORCE TO "1"

AY8930 EXPANDED MODE:

AMPLITUDE
"MODE"

5-81T "FIXED"
AMPLITUDE LEVEL

The amplitude "mode" (bit M) selects either fixed level
amplitude (M = 0) or variable level amplitude (M = 1). It
follows that bits L4 - LO, defining the value of a "fixed"
level amplitude, are only active when M = O. The
amplitude is only "fixed" in the sense that the amplitude
level is under the direct control of the system processor
via an address latch/write data sequence.

Coarse Tune
Register

Channel

Fine Tune
Register

RCA
R1B
R3B

A
B
C

RBA
ROB
R2B

When "variable amplitude" is selected (M = 1), the
amplitude of each channel is determined by the envelope pattern as defined by the envelope generators 5-bit
output (E4 - EO). The amplitude "mode" bit (bit M) can
also be thought of as an envelope enable bit, i.e. when
M = 1, the envelope is enabled.

D850010C-12

5-72

AY8930
16-BIT ENVELOPE PERIOD TO
ENVELOPE GENERATOR

The definition of each function is as follows:

Hold - When set to logic "1" in AY3891 OA mode, limits
the envelope to one cycle, holding the last count of the
envelope counter (E3 - EO = 0000 or 1111, depending on
whether the envelope counter was in a count-down or
count-up mode, respectively).
Alternate - When set to logic "1 ", the envelope counter
reverses count direction (up-down) after each cycle.

Note thatthe value programmed in the combined coarse
and fine tune registers is a period value - the higher the
value in the registers, the lower the resultant frequency.

NOTE: When both the hold bit and the alternate bit are
ones, the envelope counter is reset to its initial
count before holding.

Note also, that as with the tone period, the lowest period
value is 0001 h (divided by 1); the highest period value is
FFFFh (divided by 65,53510).

Attack - When set to logic "1" in AY38910A mode, the
envelope counter will count up (attack) from E3, E2, El,
EO=OOOOto E3, E2, El, EO= 1111 ;when setto logic "0",
the envelope counter will count down (decay) from 1111
to 0000.

ENVELOPE SHAPE/CYCLE CONTROL
The AY8930 envelope generator further counts down
the envelope frequency by 32, producing a 32-state per
cycle envelope pattern defined by its 5-bit counter output, E4, E3, E2, El, and EO. The particular shape and
cycle pattern of any desired envelope is accomplished
by controlling the count pattern (count up/ count down)
of the 5-bit counter and by defining a single cycle repeatcycle pattern. The AY3891 OA mode envelope generator
further divides the envelope period by 16, producing a
16-state per cycle envelope pattern as defined by the 4bit counter output, E3, E2, El and EO.

Continue - When set to logic "1 ", the cycle pattern will
be as defined by the hold bit; when set to logic "0", the
envelope generator will be reset to 0000 after one cycle
and hold at that count.
Further description of the above functions could be
accomplished by numerous charts of the binary count
sequence of E3, E2, El, EO for each combination of
hold, alternate, attack and continue. However, since
these ouputs are used (when selected by the amplitude
control registers) to amplitude modulate the output of the
mixers, a better understanding of their effect can be
accomplished via a graphic representation of their value
for each condition selected, as illustrated in the Envelope Shape/Cycle Control figure to the right and the
Detail of Two Cycles figure below.

Loading of the envelope shape/cycle control register will
reset the associated counter to the appropriate initial
state and reset the envelope period counter for that
channel.
The envelope shape/cycle control is contained in the
lower 4 bits (83-80) of the respective envelope control
registers. Each of these 4 bits controls a function in the
envelope generator, as illustrated in the following:

For AY8930 mode, hold, alternate, attack and continue
is the same, however the pattern is defined by 5 bits (E4,
E3, E2, El, EO.)

ENVELOPE SHAPE/CYCLE
CONTROL REGISTER

Hold

I
NOT USED
(MODE SELECT BITS)

L - _....
L -_ _ _ _ _

Alternate
Attack

L.._ _ _ _ _ _

Continue

5-73

DS50010C-13

AV8930
ENVELOPE SHAPE/CYCLE CONTROL
RD BITS
B3

AY3891 OA MODE

A
C

0
N
T
I
N
U

A
T
A
C
K

T
E
R
N
A

0
L

GRAPHIC REPRESENTATION
OF ENVELOPE GENERATOR
OUTPUT E3 E2 E1 EO.

EP IS THE ENVELOPE
PERIOD (DURATION OF
ONE CYCLE)

DETAIL OF TWO CYCLES - AY38910A MODE

GRAPHIC REPRESENTATION
OF THE DECIMAL VALUES OF
ENVELOPE GENERATOR
OUTPUT E3 E2 E1 EO

I...

DS50010C-14

EP
(1!fE)

(lifE)

5-74

AY8930
DIGITAL TO ANALOG CONVERTER

control register' or the envelope generator. The signal
of the output is the NoiselTone specified for that channel.

The Digital to Analog conversion is performed in logarithmetic steps with a normalized voltage range of OV to
1.0V. The specified amplitude of each converter is
controlled by a 5-bit word from either the amplitude

• Except in the 8910A-compatibility mode, which only
allows for 4 bits of external amplitude control.

D/A CONVERTER OUTPUT - AV8930 EXPANDED MODE
NORMALIZED
VOLTAGE

1.0

.841

.707

.595

.500

.420
.354

.297
.250
.210
.177
.149
.125

ENVELOPE PERIOD (111 E)

THIS FIGURE ILLUSTRATES THE D/A CONVERTER OUTPUT WHICH WOULD RESULT IF
NOISE AND TONES WERE DISABLED AND AN ENVELOPE CONTROLLED VARIABLE
AMPLITUDE WERE SELECTED.
NOTE: THE RESET CONDITION IS ZERO CURRENT.

5-75

DS50010C-15

AY8930
ELECTRICAL CHARACTERISTICS
Maximum Ratings'
Storage temperature ......................... -55°C to + 150°C
Maximum temperature under bias ............... +125°C
Voo and all other input/output
voltages with respect to Vss ............... -0.3V to +7.0V

'Exceeding these ratings could cause permanent damage to the device. This is a stress rating only and
functional operation of this device at these conditions is
not implied. Operating ranges are specified in Standard
Conditions. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Data labeled "typical" is presented for design
guidance only and is not guaranteed.

Standard Conditions (Unless otherwise noted)
Free air ambient operating
temperature ......................................... O°C to +70°C
Voo ........................ ....... ............ ........ +4.5V to +5.5V
Vss .................................................... O.OV (Ground)

DC CHARACTERISTICS
Parameters

Sym

Min

Input Logic Levels
Logic 0
Logic 1

VIL
VIH

-0.3
+2.4

Input Leakage
Clock
BC1, BDIR

Typ

Max

Units

+0.4
Voo

Volts
Volts

10
10

Conditions

Inputs with Pullups
A8, RESET, Select

IlL

100

VIN

= +O.4V

Inputs with Pulldowns
A9

IIH

VIN

= +2.4V

IlL
VOH
VOL

20
+2.4
0.0

150
Voo
+0.4

Volts
Volts

VIN = +O.4V
IOH = 100 ~A w/1 OOpF
IOL = 1.6 mA w/1 OOpF

VOH
VOL

+2.4
0.0

Voo
+0.4

Volts
Volts

IOH = 100 ~A w/100pF
IOL = 1.6 mA w/1 OOpF

All inputs and outputs
tied to Vss or Voo.

I/O with Pullups
A7-AO, B7-BO

Data/Address
DA7-DAO

Power Supply

OS50010C-16

100

5-76

AV8930
AC CHARACTERISTICS *
Parameters

Sym

Min

Typ

Max

Units

Conditions

Clock Input
Frequency
Rise/Fall Time

tr,tf

Master Reset
RESET

tms

1
0

4
50

MHz
ns

40/60 asymmetry
allowed

'Two Clock Periods

ns
ns

Control Signals
BC1, BC2, BDIR
Skew
Valid

tes
tees

300

tas
tah

300
65

tab
ttd

200
100

ns
ns

tds
tdh

300
65

ns
ns

tpw

500

tprs
tprh

200
65

ns
ns

Data Address Bus
DA7-DAO, AB, A9
Address Setup Time
Address Hold Time

Read Mode
Data Setup Time
Data Hold Time

Write Mode
Data Setup Time
Data Hold Time

Input/Output Port
IOA7-IOAO, IOB7-IOBO

Output Mode
Data Setup Time

Input Mode
Data Setup Time
Data Hold Time

, The address/data read cycle is latch address followed by an inactive state then the read command.
The address/data write cycle would be the same with the substitution of the write command in place
of the read. An inactive state is required between each cycle (or active command).

5-77

DS50010C-17

AV8930
TIMING DIAGRAMS

READ MODE
BUS CONTROL
BC1, BDIR

NO ACTION

LATCH ADDRESS

READ FROM PSG

DATA/ADDRESS BUS
-----------------------

DATA OUTPUT

WRITE MODE

BUS CONTROL
BC1, BDIR

LATCH ADDRESS

NO ACTION

WRITE TO PSG

I- las -I ~~ 1

--~~!:":I~~?-~:~-~-~~~----------- '--___--'-----------------------1

DATA INPUT

~-----.

BUS CONTROL SIGNALS
BC1, BDIR

Iccs

DS50010C-18

5-78

AY8930
TIMING DIAGRAMS (Cont.)
MASTER RESET
RESET

lms

1/0 PORT OUTPUT MODE: WRITE DATA FROM CPU BUS TO 1/0 PORT"
BUS CONTROL
BC1, BDIR

LATCH ADDRESS

NO ACTION

WRITE TO PSG

I_ las _1°1
tah
DATA/ADDRESS BUS
-----------------------

DATA INPUT
TO PORT
REGISTER

tpw
110 PORT

VALID DATA
OUTPUT TO
PORT

1/0 PORT INPUT MODE: WRITE DATA FROM 1/0 PORT TO CPU BUS"
BUS CONTROL
BC1, BDIR

LATCH ADDRESS

DATA/ADDRESS BUS

NO ACTION

READ FROM PSG

_______________________

DATA OUTPUT
TO CPU BUS

I/O PORT

VALID DATA INPUT
FROM PORT

• Assume the direction of the I/O port has already been
determined via a write to the Enable register (R7A).

5-79

DS500l0C-19

AY8930
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.

PART NUMBERS

Package

I Temperature

Blank

L - - - - li Range

Device

DS50010C-20

AY8930

5-80

40-Pin Plastic DIP
0° C to 70° C

Enhanced Programmable Sound Generator

AY0438-1

Microchip

32-Segment CMOS LCD Driver
FEATURES
PIN CONFIGURATION

• Drives up to 32 LCD segments of arbitrary
configuration
CMOS process for: wide supply voltage range, low
power operation, high noise immunity, wide
temperature range
CMOS, NMOS and TTL-compatible inputs
Electrostatic discharge protection on all pins
Cascadable
• On-chip oscillator
Requires only three control lines
Can be used to drive relays, solenoids, print head
drives, etc.

40 LEAD DUAL INLINE
Top View

APPLICATIONS
•
•
•
•

Industrial displays
Consumer product displays
Telecom product displays
Automotive dashboard displays

DESCRIPTION

]

LCD~

] BP
]
]
]
]
]
]

SEG6
SEG7
SEGB
SEG9
SEG 10
SEG 11
SEG 12
SEG 13
SEG14

J
]

'" fi!~

SEG 26

BLOCK DIAGRAM

CJl

:!:

fi!CJl CJlfi!

~ gj gj ~

'"w 'w" 'w"
CJl

CJl

fi!

CJl

DATA OUT

WAD~L_ _~_~,T,C_HE_S_~

LCD~

CLOCK
SEG 1
SEG2
SEG3
GND
DATA OUT
DATA IN
SEG4
SEG5

•

The AY0438-1 can drive any standard or custom parallel
drive LCD display, whether it be field effect or dynamic
scattering; 7-, 9-,14-, or 16-segment characters; decimals; leading + or -; or special symbols. Several
AY0438-1 devices can be cascaded. The AC frequency
olthe LCD waveforms can either be supplied by the user
or generated by attaching a capacitor to the LCD input,
which controls the frequency of an internal oscillator.

O-O~_

]
]

44 PLCC

The AY0438-1 is a CMOS LSI circuit that drives a liquid
crystal display, usually under microprocessor control.
The part acts as a smart peripheral that drives up to 32
LCD segments. It needs only three control lines due to
its serial input construction. It latches the data to be
displayed and relieves the microprocessor from the task
of generating the required waveforms.

CLOCK
DATA IN

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

Voo
LOAD
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG 19
SEG 18
SEG 17
SEG 16
SEG 15

The device also acts as a versatile peripheral, able to
drive displays, motors, relays, and solenoids within its
output limitations.

~====::>

320UTPUTS

f-----------.-o

BAg;~~E

The AY0438-1 is available in 40 lead dual-in-line ceramic
and plastic packages. Unpackaged dice are also available.

5-81

AY0438-1
PIN DESCRIPTION
Pin #

Name

Direction

1
2
3-29,32,33,37-39
30
31
34
35
36
40

VDD
Load
Seg 1-32
BP
LCD
Data In
Data Out
Vss
Clock

Input
Output
Output
Input
Input
Output
Ground
Input

FIGURE 1 TIMING DIAGRAM
III
CLOCK
DATA IN

tdh

Ids:

DATA OUT

i
I

FIGURE 2 OSCILLATOR FREQUENCY
GRAPH (TYPICAL @ 2S·C)

--l

X
I

-;Ipd : LOAD

Supply voltage
Latch data from registers
Direct drive outputs
Backplane drive output
Backplane drive input
Data input to shift register
Data output from shift register
Ground
System clock input

--.J:;----\L.....I;----\:L

140
_

fiiII:
~

"' "'"

60
40

..... r--.,

60
Cl(pF)

I"80

100

120

condition and pass the LCD inputto the backplane
output. If the LCD pin is allowed to oscillate, its
frequency is inversely proportional to capacitance
and the LCD drivingwaveforms have a frequency 28
slower than the oscillator itself. The relationship is
shown graphically (see Figure 2). The frequency is
nearly independent of supply Voltage. If LCD is
oscillating, it is important to keep coupling capacitance to backplane and segments as low as possible. Similarly, it is recommended that the load
capacitance on LCD be as large as is practical.

2. A logic 1 on Data In causes a segment to be visible.
3. A logic 1 on Load causes a parallel load of the data in
the shift register into latches that control the segment
drivers.
4. If LCD is driven, it is in phase with the backplane
output.

DS70010G-2

100

1. The shift register loads, shifts, and outputs on the
falling edge of the clock.

7. The LCD pin can be used in two modes, driven or
oscillating. If LCD is driven, the circuit will sense this

OPERATING NOTES

6 The supply voltage olthe AY04381 is equalto halfthe
peak driving voltage of the LCD.

120

5. To cascade units, either connect backplane of one
circuit to LCD of all other circuits (thus one capacitor
provides frequency control for all circuits) or connect
LCD of all circuits to a common driving signal. If the
former is chosen, tie just one backplane to the LCD
and use a different backplane output to drive the
LCD inputs. The data can be loaded to all circuits in
parallel or else Data Out can be connected to Data In
to form a long serial shift register.
.

Description

8. There are two obvious signal races to be avoided in
this circuit, (1) changing Data In when the clock is
falling, and (2) changing Load when the clock is
falling.
9. The number of a segment corresponds to how
many pulses have occurred since its data was
present atthe input. For example, the data on SEG
17 was input 17 clock pulses earlier.
1O.lt is acceptable to tie the load line high. In this case
the latches are transparent. Also, remote control
would only require two signal lines, clock and Data
In.

5-82

AY0438-1
ELECTRICAL CHARACTERISTICS

-Exceeding these ratings could cause permanent damage to the device. This is a stress rating only and
functional operation of this device at these conditions is
not implied. Operating ranges are specified in Standard
Conditions. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Data labeled "typical" is presented for design guidance
only and is not guaranteed.

Maximum Ratings*
VDD ......................................................... -0.3V to +12V
Inputs (CLK, Data In, Load) ............. Vee to VDD +0.3V
LCD Input .................................... -0.3V to VDD +0.3V
Power Dissipation ............................................ 250mW
Storage Temperature ......................... -65·C to +125·C
Operating Temperature Industrial ........ -40·C to +85·C

VDD = +5V unless otherwise noted
TA = -40·C to +85·C

DC CHARACTERISTICS
Characteristics

Sym

Min

Supply Voltage

VDD

+3.0

+10.5

Supply Current

IDD

25
13

60
30

IlA
IlA

Input High Level
Input Low Level

VIH
VIL1
VIL2
IL
CI

0.5VDD
0
0

V
V
V

0.01

VDD
+0.6
+1.0
±10
5.0

IlA
pF

Segment Output Voltage

VOH
VOL

0.8VDD
0

VDD
O.IVDD

V
V

LCD Input High Level

VIN

0.9VDD

VDD

LCD Input Low Level

VIL

O.1VDD

IlA

Sym

Min

Typ

1.5

MHz

50% duty cycle

Data Set-up Time

tds

150

nsec

Data change to Clk
falling edge

Data Hold Time

tdh

Load Pulse Width

tpw

175

nsec

Data Out Prop. Delay

tpd

500

nsec

Clock,
Data,
Input Leakage Current Load
Input Capacitance

LCD Input Leakage
Current Level

Typ

Max

Units

Conditions

LCD OSC < 15 kHz
LCD OSC < 100Hz

VDD = +3.0V
VDD = +10.5V
VIN = OV and +5.0V
VDD = +5.0V
IOH = -IOOIlA
IOL = 1001lA

VIN = OV and +5.0V
VDD = +5.0V

AC CHARACTERISTICS
Characteristics
Clock Rate

5-83

Max

Units

Conditions

nsec

CL = 55pF

DS70010G-3

AY0438-1
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.

PART NUMBERS

AY0438- II P

Package:

Temperature
Range:

40· C to 85· Conly

32 Segment LCD Driver

Device:

DS70010G-4

Plastic DIP
PLCC

5-84

Microchip

SECTION 6
DIGITAL SIGNAL PROCESSING
PRODUCT SPECIFICATIONS
DSP
DSP320C10
DSP320C10

Product Portfolio ....................................................................................................... 6- 1
CMOS Digital Signal Processor (8 Version) ............................................................. 6- 5
Development Tools ................................................................................................... 6- 23

DS00018C

6-i

Microchip

O800018C

6-ii

DIGITAL SIGNAL
PROCESSORS

Microchip

DSP Product Portfolio
COMMERCIAL DSP (0' TO 70')
CMOS DSP - COMMERCIAL (0' TO 70')
Microchip
Part Number

Speed (MHz) 1
TI Part Number

Maximum Instruction
Cycle Time (ns)

Internal Mask ROM
Version Available

Package

DSP320C10-32/P

15.0 to 32.8

122

40L Plastic DIP

DSP320C10-32/L

15.0 to 32.8

122

44LPLCC

DSP320C10-25/P

15.0 to 25.61
TMS320C10NL-25

156

40L Plastic DIP

DSP320C10-25/L

15.0 to 25.61
TMS320C10FNL-25

156

44LPLCC

oJ to 'W.:>I
TMS320C10NL

HI:>

JK.

4UL I"'lastlc UII"'

6.7 to 20.51
TMS320C10FNL

195

JK.

44LI"'LGG

DSP320C10-14/P

6.7 to 14.41
TMS320C10NL-14

277

40L Plastic DIP

~v. ~'vv10-14/L

6.7 to 14.4

277

44LPLGG

.~Iu/I"'

~~,

~_v..,

lOlL

INDUSTRIAL DSP (_45' TO +85'C)
CMOS DSP -INDUSTRIAL (-45' TO +85'C)
Microchip
Part Number

Speed (MHz) 1
TI Part Number

Maximum Instruction Internal Mas ROM
Cycle Time (ns)
Version Available

Package

DSP320C10-321/P

15.0 to 32.8

122

40L Plastic DIP

DSP320C10-321/L

15.0 to 32.8

122

44L PLCC

DSP320C10-251/P

15.0 to 25.61
TMS320C10NA-25

156

40L Plastic DIP

DSP320C10-251/L

15.0 to 25.61
TMS320C10FNA-25

156

44LPLCC

DSP320C101/P

6.7 to 20.51
TMS320C10NA

195

40L Plastic DIP

DSP320C101/L

6.7 to 20.51
TMS320C10FNA

195

44LPLCC

6-1

08210258-1

DIGITAL SIGNAL PROCESSORS
MILITARY DSP (-55' TO +110'C)

Please refer to the "MILITARY DATA BOOK"

CMOS DSP - MILITARY (-55' TO +125'C)
Microchip

DESCSMD
Part Number

DSP320C10-B/OA

5962-87633010A

Speed (MHz)
Part Number
Number

Maximum
TIPart
Cycle Time (ns)

Package
Instruction

Lead
Finish

195

40L Ceramic

Solder

6.71020.5

Side-Braze

SMJ320C10JDM
DSP320C10-B/OC

5692-87633010C

Internal
Masked ROM
Version

6.7 to 20.5

195

40L Ceramic

Gold

Side-Braze
DSP320C 1O-B/UA

5962-8763301 XA

6.7 to 20.5

195

SMJ320C10FDM
DSP320C10-B/UC

5692-8763301 XC

44 Terminal

Solder

LCC

6.7 1020.5

195

44 Terminal

Gold

LCC
DSP320C10-25B/OA

5962-87633020A

15.01025.6

156

40L Ceramic

Solder

Side-Braze
DSP320C10-25B/OC

5962-87633020C

15.0 to 25.6

156

40L Ceramic

Gold

Side-Braze
DSP320C10-25B/UA

5692-8763302XA

15.0 to 25.6

156

44 Terminal

Solder

LCC
DSP320Cl0-25B/UC

5962-8763302XG

15.0 to 25.6

156

44 Terminal

Gold

LCC
DSP320CF10-25B/OA

5962-8763305QA

6.71025.6

156

40L Ceramic

Solder

Side-Braze
DSP320CF10-25B/OC

5962-8763305QC

6.71025.6

156

40L Ceramic

Gold

Side-Braze
DSP320CF10-25B/UA

5962-8763305XA

6.7 1025.6

156

44 Terminal

Solder

LCC
DSP320CF10-25B/UC

5962-8763305XC

6.7 to 25.6

156

44 Terminal

Gold

LCC
DSP320CM10-B/OA

5962-87633030A

6.7 to 20.5

195

X
DSP320CM10-B/OC

5962-87633030C

40L Ceramic

Solder

Side-Braze
6.7 to 20.5

195

40L Ceramic

Gold

Side-Braze
DSP320CM10-B/UA

5962-8763303XA

6.7 10 20.5

195

X
DSP320CM10-B/UC

5962-8763303XC

44 Terminal

Solder

LCC
6.7 to 20.5

195

44 Terminal

Gold

LCC
DSP320CM10-25B/OA

5962-8763304QA

15.01025.6

156

X
DSP320CM10-25B/OC

5962-87633040C

40L Ceramic

Solder

Side-Braze
15.0to 25.6

156

40L Ceramic

Gold

Side-Braze
DSP320CM10-25B/UA

5962-8763304XA

15.0 to 25.6

156

DSP320CM10-25B/UC

5962-8763304XC

44 Terminal

Solder

LCC

X
15.0 to 25.6

156

44 Terminal

Gold

LCC

DS21 0258-2

6-2

DIGITAL SIGNAL PROCESSORS
MILITARY DSP (_55' TO +110'C) (CONT.)
NMOS DSP - MILITARY (-55' TO +110'C)
Microchip
Part Number

DESCSMD
Part Number

DSP32010-B/OA

Speed (MHz)
TIPart
Number

5962-84053010A

Maximum
Instruction
Cycle Time (ns)

6.7 to 20.0

200

Package

40L Ceramic

Lead
Finish

Solder

Side-Braze
DSP32010-B/OC

5692-84053010C

6.7 to 20.0

200

40L Ceramic

Gold

Side-Braze
DSP32010-B/UA

5962-8405301 ZA

6.7 to 20.0

200

44 Terminal

Solder

LCC
DSP32010-B/UC

5692-8405301 ZX

6.7 to 20.0

200

44 Terminal

Gold

LCC
,--------------------------------------------------------------------------~

PART NUMBERS - MILITARY (see next page for Commercial and Industrial Parts)

T-!~!IT~ '-"'dRn"",
~
~____---II

Case Outline:

Solder Dip
Gold

44 Pin Side Braze OIL
40 Terminal LCC

Screening
Level':

Frequency:
25
Device:

'Note: 32010

A
C

DSP32010
DSP320Cl0
DSP320CF10
DSP320Cl0

MIL-STD-883C Compliant
(-55' C 10125' C)
20.5 MHz
25.6 MHz
NMOS
CMOS
CMOS
CMOS

DSP
DSP
DSP, 6.7 to 25.6 MHz
DSP, ROM Version

=TE (Thermally Enhanced LCC); 320Cl0 =NTE (Non-Thermally Enhanced LCC)

PART NUMBERS - DESC SMD

5U"~~T

Lead Finish:

~------II Case Outline':

A
C

Solder Dip
Gold

Ceramic Dual-in-line (28 lead)
Ceramic Side Braze DIL(40 lead)
Flal pack

~------------~--I.I
I

Version:

301
302
303
304
305

Device:

5962
5692

6.7 to 20.5 MHz
15.0 10 25.6 MHz
6.7 to 20.5 MHz, ROM Version
15.0 to 25.6 MHz, ROM Version
6.71025.6 MHz
CMOS DSP
NMOS DSP

'Note: The Case Outline Code is used for order entry only and will not be marked on device

6-3

DS21 0258-3

DIGITAL SIGNAL PROCESSORS
NOTES:

DS21025B-4

6-4

DSP320C10

Microchip

CMOS Digital Signal Processor
FEATURES

DESCRIPTION

•
•
•
•

The DSP320C1 0 is the first low power CMOS member
of the Microchip Technology DSP320 family of digital
signal processors, designed to support a wide range of
high-speed or numeric-intensive applications. This
device is a CMOS pin-for-pin compatible version of the
industry standard DSP32010 digital signal processor.

•
•
•
•

•

•
•

122ns instruction cycle
144 word on-chip data RAM
ROM-less version - DSP320C1 0
1.5K word on-chip program ROM-DSP320CM10
External memory expansion to a total of 4K words
at full speed
16-bit instruction/data word
32-bit ALU/Accumulator
16 x 16-bit multiply in 122ns
0 to 15-bit barrel shifter
Eight input and eight output channels
16-bit bidirectional data bus with a 65Mbps
transfer rate
Interrupt with a full context save
Signed two's complement fixed-point arithmetic
CMOS technology
Single 5 volt supply
Four versions available:
-DSP320C10-14
14.4MHz Clock
-DSP320C10
20.5MHz Clock
-DSP320C10-25
25.6MHz Clock
-DSP320C10-32
32.8MHz Clock

The processor has been enhanced to make the Data
RAM static with respect to the Reset. Also, the address
hold time has been improved to a non-negative value.
This 16/32 bit single-chip microcomputer combines the
flexibility of a high-speed controller with the numerical
capability of an array processor thereby offering an
inexpensive alternative to multichip bit-slice processors.
The DSP320 family contains MOS microcomputers
capable of executing eight million instructions per second. This high throughput is the result of the comprehensive, efficient, and easily programmed instruction
set and of the highly pipelined architecture. Special
instructions have been incorporated to speed the execution of digital signal processing (DSP) algorithms.
The DSP320 family's unique versatility and power give
the design engineer solutions to a variety of complicated
applications. In addition, these microcomputers are
capable of providing the multiple functions often required for asingle application. For example, the DSP320
family can enable an industrial robot to synthesize and
recognize speech, sense objects with radar or optical
intelligence, and perform mechanical operations through
digital servo loop computations.

PIN CONFIGURATION

40 LEAD DIP

Top View
A1/PA1
AD/PAD
MC_

A21PA2

:;:

~ ~ ~ ~ ~

::i :\'

1m'

A5
A6
A7

X2/CLKIN

D9
D10
D11
012
013
D14
015
07
D6

I~ I~ ~ ~

lIS

44 PIN PLCC

1"-~

C\I

....

;

MEN

"'""

DEN

Ilrn
WE
Vee

DSP320C10

A9
A10
A11
DO
01
02
D3
04

Vex;

AO
A10
31

A11
DO

012

!!? !il N 1:: t:l eli lQ

ro
~ 5 0 5 15 i'l i'l 1\ 8 8 ~
~

6-5

08210376-1

DSP320C10
DSP320C10 BLOCK DIAGRAM
~

- - - - - - - - -- - - - - - - - - - - - - -A11 AO,· - - - - - - - - - - - - - - - - - - - - - - - - -~

PA2.PAO

015 ·00
MICROPROCESSOR
OPTION

16 BITS

ADDRESS
(144 X 16)

,
~----------------------------------------------------- -------

ARITHMETIC
MODULE

RAM
MODULE

PIN DESCRIPTIONS
Name

I/O

Definition

Name

I/O

Definition

A11·AO/
PA2·PAO

OUT

External address bus, 1/0 port address
multiplexed over PA2·PAO,
External polling input for bit test and jump
operations,
System clock output, 1/4 crystal ClKIN
frequency,
16-bit data bus,
Data enable indicates the processor
accepting input data on D15-DO,
Interrupt

MC/MP

Memory mode select: High selects microcom·
puter, low selects microprocessor mode,
Memory enable indicates that
D15·DO will accept external memory instruction,
Reset used to initialize device,
Power.
Ground,
Write enable indicates valid data on D15-DO,
Crystal input.
Crystal input or external clock input.

810

ClKOUT

OUT

D15·DO
DEN

I/O
OUT

INT

D521 0378-2

MEN
-

RS
VCC
VSS
WE
X1
X2IClKIN

6-6

OUT
IN
IN
IN
OUT
IN
IN

DSP320C10
ARCHITECTURE
The DSP320 family utilizes a modified Harvard architecture for speed and flexibility. In a strict Harvard architecture, program and data memory lie in two separate
spaces, permitting a full overlap of the instruction fetch
and execution. The DSP320 family's modification of the
Harvard architecture allows transfers between program
and data spaces, thereby increasing the flexibility of the
device. This modification permits coefficients stored in
program memory to be read into the RAM, eliminating
the need for a separate coefficient ROM. It also makes
available immediate instructions and subroutines based
on computed values.

Program Memory Expansion
The DSP320C10 is equipped with a 1536-word ROM
which can be mask-programmed at the factory with a
customer's program. It can also execute from an additional 2560 words of off-chip program memory at full
speed. This memory expansion capability is especially
useful for those situations where a customer has a
number of different applications that share the same
subroutines. In this case, the common subroutines can
be stored on-chip while the application specific code is
stored off-chip.
The DSP 320C1 0 can operate in either of the following
memory modes via the MC/MP pin:

The DSP320C1 0 utilizes hardware to implement functions that other processors typically perform in software.
For example, this device contains a hardware multiplier
to perform a multiplication in a single 122ns cycle. There
is also a hardware barrel shifter for shifting data on its
way into the ALU. Finally, extra hardware has been
included so that auxiliary registers, which provide indirect data RAM addresses, can be configured in an auto
increment/decrement mode for single-cycle manipulation of data tables. This hardware-intensive approach
gives the design engineer the type of power previously
unavailable on a single chip.

Microcomputer Mode (MC)-Instruction addresses 01535 fetched from on-Chip ROM. Those with addresses
1536-4095 fetched from off-chip memory at full speed.
Microprocessor Mode (MP)-Full speed execution from
all 4096 off-chip instruction addresses.
The ability of the DSP320C1 0 to execute at full speed
from off-chip memory provides important benefits:
Easier prototyping and development work than is
possible with a device that can address only onchip ROM
Purchase of a standard off-the-shelf product rather
than a semi-custom mask-programmed device
Ease of updating code
Execution from external RAM
Downloading of code from another microprocessor
• Use of off-chip RAM to expand data storage
capability

32-bit ALU/Accumulator
The DSP320C1 0 contains a 32-bit ALU and accumulator that support double-precision arithmetic. The ALU
operates on 16-bit words taken from the data RAM or
derived from immediate instructions. Besides the usual
arithmetic instructions, the ALU can perform Boolean
operations, providing the bit manipulation ability required of a high-speed controller.

Input/Output

Shifters

The DSP320C10's 16-bit parallel data bus can be utilized to perform I/O functions at burst rates of 65 million
bits per second. Available for interfacing to peripheral
devices are 128 input and 128 output bits consisting of
eight 16-bit multiplexed input ports and eight 16-bit
multiplexed output ports. In addition, a polling input for
bit test and jump operations (BIO) and an interrupt pin
(INT) have been incorporated for multi-tasking.

A barrel shifter is available for left-shifting data 0 to 15
places before it is loaded into, subtracted from, or added
to the accumulator. This shifter extends the high-order
bit of the data word and zero-fills the low-order bits for
two's complement arithmetic A second shifter left-shifts
the upper half of the accumulator 0, 1, or 4 places while
it is being stored in the data RAM. Both shifters are very
useful for scaling and bit extraction.

Interrupts and Subroutines

16 x 16-bit Parallel Multiplier

The DSP320C10 contains a four-level hardware stack
for saving the contents of the program counter during
interrupts and subroutine calls. Instructions are available for saving the DSP320C1 O's complete context. The
instructions, PUSH stack from accumulator, and POP
stack to accumulator permit a level of nesting restricted
only by the amount of available RAM. The interrupts
used in the DSP320C10 are maskable.

The DSP320C10's multiplier performs a 16 x 16-bit,
two's complement multiplication in one 122ns instruction cycle. The 16-bit T Register temporarily stores the
multiplicand; the P Register stores the 32-bit result.
Multiplier values either come from the data memory or
are derived immediately from the MPYK (multiply immediate) instruction word. The fast on-chip multiplier allows
the DSP320C10 to perform such fundamental operations as convolution, correlation, and filtering at a very
high rate.

6..7

D821037B-3

DSP320C10
INSTRUCTION SET
The DSP320C10's comprehensive instruction set supports both numeric-intensive operations, such as signal
processing, and general purpose operations, such as
high-speed control. The instruction set, explained in
Tables 1 and 2, consists primarily of single-cycle singleword instructions, permitting execution rates of up to
eight million instructions per second. Only infrequently
used branch and 110 instructions are multicycle.
The DSP320C1 0 also contains a number of instructions
that shift data as part of an arithmetic operation. These
all execute in a single cycle and are very useful for
scaling data in parallel with other operations.
Three main addressing modes are available with the
DSP320C10 instruction set: direct, indirect, and immediate addressing.

Indirect Addressing
Indirect addressing forms the data memory from the
least significant eight bits of one of two auxiliary registers, ARO and AR1. The auxiliary register pointer (ARP)
selects the current auxiliary register. The auxiliary
registers can be automatically incremented or decremented in parallel with the execution of any indirect
instruction to permit single-cycle manipulation of data
tables. The instruction format for indirect addressing is
as follows:
1514131211109 8 7 6 5 4 3 2 1 0
I D N
A
1 0 N E A 0 0 R
C C R
P

OPCODE

Direct Addressing
In direct addressing, seven bits of the instruction word
concatenated with the data page pointer form the data
memory address. This implements a paging scheme in
which the first page contains 128 words and the second
page contains 16 words. In a typical application, infrequently accessed variables, such as those used for
servicing an interrupt, are stored on the second page.
The instruction format for direct addressing is shown
below.

15 14 13 12 11 10 9 8 7 6 543 2 1 0
OPCODE

DMA

Bit 7 = 0 defines direct addressing mode. The opcode is
contained in bits 15 through 8. Bits 6 through 0 contain
data memory address.
The seven bits of the data memory address (DMA) field
can directly address up to 128 words (1 page) of data
memory. Use of the data memory page pointer is
required to address the full 144 words of data memory.
Direct addressing can be used with all instructions
requiring data operands except for the immediate operand instructions.

Bit7 =1 defines indirect addressing mode. The opcode
is contained in bits 15 through 8. Bits 7 through 0 contain
indirect addressing control bits.
Bit 3 and bit 0 control the Auxiliary Register Pointer
(ARP). If bit 3 = 0, then the content of bit 0 is loaded into
the ARP. If bit 3 = 1, then content of ARP remain
unchanged. ARP =0 defines the contents of ARO as
memory address. ARP = 1 defines the contents of AR1
as memory address.
Bit 5 and bit 4 control the auxiliary registers. If bit 5 = 1,
then the ARP defines which auxiliary register is to be
incremented by 1. If bit4 = 1, then the ARP defines which
auxiliary register is to be decremented by 1. If bit 5 or
bit 4 are zero, then neither auxiliary register is incremented or decremented. Bits 6,2 and 1 are reserved
and should always be programmed to zero.
Indirect addressing can be used with all instructions
requiring data operands, except for the immediate operand instructions.

Immediate Addressing
The DSP320C1 0 instruction set contains special"immediate" instructions. These instructions derive data from
part of the instruction word rather than from the data
RAM. Some very useful immediate instructions are
multiply immediate (MPVK), load accumulator immediate (LACK), and load auxiliary register immediate (LARK).

05210378-4

6-8

DSP320C10
INSTRUCTION SET SUMMARY
TABLE 1 -INSTRUCTION SYMBOLS
Symbol

Meaning

ACC

Accumulator
Data memory address field
Addressing mode bit
Immediate operand field
3-bit port address field
1-bit operand field specifying auxiliary register
4-bit left-shift code
3-bit accumulator left-shift field

0
I
K
PA

R
S
X

TABLE 2 - ACCUMULATOR INSTRUCTIONS

Mne-

monic
ABS
ADD
ADDH
ADDS
AND
LAC
LACK
OR
SACH
SACL
SUB
SUBC
SUBH
SUBS
XOR
ZAC
ZALH
ZALS

Description

Number of
Cycles Words

Absolute value of accumulator
Add to accumulator with shift
Add to high-order accumulator bits
Add to accumulator with no sign
extension
AND with accumulator
Load accumulator with shift
Load accumulator immediate
OR with accumulator
Store high-order accumulator
bits with shift
Store low-order accumulator bits
Subtract from accumulator
with shift
Conditional subtract (for divide)
Subtract from high-order
Subtract from accumulator with
no sign extension
Exclusive OR with accumulator
Zero accumulator
Zero accumulator and load
high-order bits
Zero accumulator and load
low-order bits with no sign
extension

OpCode - Instruction Register
15 14 13 12 11 10 9

1
1
1

1
1
1
1

0
0
0
0

1
1

0
0
0

1
1
1
1
1

0
0
0
0
0

1
1
1
1

1
1

1
1
1

1 1 1 1
f----S-->

0
0

0
1

1
I
I
I

1 0 0
1
f---- S-->
1 1 1 0
1 0 1 0
1 <---X-->

I
I

E
E
E

E
E

3 2 1
1 0
D
D
D

0
0

1
1

f---- S-->

I
I

0
0
0

1
1
1

0
0
0

0
0

1
1

I
I
I

1
1
1

1
1
0

0
1
1

0
1
0

0
1
1

I
1
I

a a a

1
1
1

D
1 0
D

0
0
1

E
E

,
E

,
,
,

,
,
,
,
,
,
,
,
,

I
I

D
D
K
D
D

1
1
1

6-9

1
1
1

D
D
D
D
D

,
0

,
,

DS21037B-5

DSP320C10
INSTRUCTION SET SUMMARY (CONT.)
TABLE 2 (CONT.) - AUXILIARY REGISTER AND DATA PAGE POINTER INSTRUCTIONS

Mne·
monic
LAR
LARK
LARP
LDP
LDPK
MAR
SAR

Description

Number of
Cycles Words

Load auxiliary register
Load auxiliary register immediate
Load auxiliary register
pointer immediate
Load data memory page pointer
Load data memory page pointer
immediate
Modify auxiliary register and pointer
Store auxiliary register

OpCode • Instruction ,Register

15 14131211 10 9

1
1
1

0
0
0

1
1

1
1
1

1
1

0
0

1
1

0
0

1
1

0
0

1
0

1
1

0
0
0

R
R
0

1
1

0
0

3 2 1

D
K
0 0

D
0 0

3 2 1

o
o
o
o
o
o
o
o
o
o

I
0

0
R

I
I

D
D

E
E

---------------------

TABLE 2 (CONT.) - BRANCH INSTRUCTIONS

Mnemonic
B

Description

Number of
Cycles Words

Branch unconditionally

BGEZ

Branch on auxiliary register
not zero
Branch if accumulator", 0

BGZ

Branch if accumulator> 0

BIOZ

Branch on BIO = 0

BANZ

BLEZ
BLl
BNZ
BV
BZ

Branch if accumulator :s; 0
Branch if accumulator < 0
Branch if accumulator .. 0
Branch on overflow
Branch if accumulator = 0

2
2
2
2
2
2

2
2
2
2
2

15 14131211 10 9
1

(

0
0

0
1

(

0
1

1
0
0

1
0

1
0
1

CALA

Call subroutine from accumulator

CALL

Call subroutine immediately

RET

Return from subroutine or
interrupt routine

DS21037B-6

OpCode • Instruction Register

6-10

(

8
1

0
0 0 0
0 0
BRANCH ADDRESS _____
0 0 0
0
0 0
0
BRANCH ADDRESS~
1 0 0 0 0
0 0
BRANCH ADDRESS _____
0 0
0 0 0
0 0
BRANCH ADDRESS _____
0 0
0 0 0
0 0
BRANCH ADDRESS _____
1 0 0 0 0
0 0
BRANCH ADDRESS _____
0 0
0 0
0 0 0
BRANCH ADDRESS _____
0 0
0 0
0 0
0
BRANCH ADDRESS _____
1 0 0 0 0
0 0
BRANCH ADDRESS _____
1 0 0 0 0
0 0
BRANCH ADDRESS _____
1 1 0
1 1 0
0 0

0
0 0
0 0
0 0
BRANCH ADDRESS _____
1
1 0 0 0 1 1 0

0
0
0
0
0
0
0
0
0

0
0
1

DSP320C10
INSTRUCTION SET SUMMARY (CONT.)

TABLE 2 (CONT.) - T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS
Mnemonic

Description

APAC
LT
LTA

Number of
Cycles Words

Add P register to accumulator
Load T register
LTA combines LT and APAC
into one instruction
lTD combines LT, APAC, and
LTD
DMOV into one instnuction
MPY
Multiply with T register, store
product in P register
MPYK Multiply T register with immediate
operand; store product in P register
PAC
Load accumulator from P register
SPAC Subtract P register from
accumulator

OpCode -Instruction Register
15 14 13 12 11 10 9

3 2 1

1
1
1

0
0
0

1
1
1

1
0
0

1
1
1

1
0
1

1
1
0

1
0
0

1
I
I

0
E

1 1 1
1
D ---7
D ---7

---7

1
1

0
0

1
1

K
1
1

1
1

0
0

)

0
0

0
1

1 1
0 0

1
0

0
0

TABLE 2 (CONT.) - CONTROL INSTRUCTIONS
Mnemonic
DINT
EINT
lST
NOP
POP
PUSH
ROVM
SOVM
SST

Description
Disable interrupt
Enable interrupt
load status register
No operation
POP stack to accumulator
PUSH stack from accumulator
Reset overflow mode
Set overflow mode
Store status register

Number of
Cycles Words
1
1
1
1
2
2
1
1
1

1
1
1
1
1
1
1
1
1

OpCode - Instruction Register
15 14 13 12 11 10 9

3 2 1

0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
0

1
1
I
1
1
1
1
1
I

0
0

1
0

0
0
0
0
0

0
1
1
0
0

0
0
D
0
1
1
1
1
D

1
1
1
1
1
1
1
1
1

1
1
0
1
1
1
1
1
1

1
1
1
1
1
1
1
1
0

0
0
0
0
0
E

0
0

0
1

---7

0
1
1
0
0

0
0
0
1
1

0
1
0
1
1

---7

TABLE 2 (CONT.) -I/O AND DATA MEMORY OPERATIONS
Mnemonic

Description

DMOV
IN
OUT
TBlR

Copy contents of data memory
Input data from port
Output data to port
Table read from program
memory to data RAM
TBlW Table writ,e from data RAM
to program (external only)

Number of
Cycles Words

OpCode - Instruction Register
15 14 13 12 11 10 9

I
I
I
I

D
D
D
D

1
2
2
3

1
1
1
1

0
0
0
0

1
1
1
1

1
0
0
1

0
0
0
0

1
0
1
0

+- PA --+
+- PA --+
1

1! I

3 2 1

E
E

---7
---7
---7
---7
---7

DS21037B-7

6-11

DSP320C10
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings'

"Exceeding these ratings could cause permanent damage to the device. This is a stress rating only and
functional operation of this device at these conditions is
not implied - operating ranges are specified in Standard
Conditions. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

Over specified temperature range (unless otherwise
noted)"
Supply voltage, Vce ............................................. -0.3V to 7V
All input voltages ........................................ -0.3V to 7V
Output voltage ............................................ -0.3V to 7V
Continuous power dissipation:

Data labeled "typical" is presented for design guidance
only and is not guaranteed.

DSP320C10 (0° to +70°C) ................................... 0.3W
DSP320C101 (-40° to +85°C) ............................ 0.36W
DSP320C10-25 (0° to +70°C) ............................ 0.35W
DSP320C101-25 (-40° to +85°C) ......................... 0.4W
Air temperature range above operating device:
- Commercial ......................................... O' C to 70'
-Industrial ........................................... -40' C to 85'
Storage Temperature Range ............. -55· C to 150'
Junction Temperature (TJ) ................................ 165·

C
C
C
C

DC CHARACTERISTICS
Characteristics

'Vee = 5V, TA = 25' e
DSP320C10

DSP320C10-14 DSP320C10-25 DSP320C10-32

Unit

Conditions

Min Nom' Max Min Nom' Max Min Nom' Max Min Nom' Max
Supply voltage, Vec

4.5

5.0

5.5

4.5

5.0

5.5

4.5

5.0

5.5

4.5

5.0

5.5

Supply voltage, Vss

2.0 .65Va -

V
V

High-level input voltage, VIH
- All inputs except ClKIN
-ClKIN
low-level input voltage, VIL (all inputs)
High-level output voltage VOH

2.0 .65Vrx -

Voe-.4 2.4 -

2.0 .65Va -

0.8

Voe-.
2.4

Woe-.
2.4

V
V

IOH= 20l!A
IOH = 3001!A

0.4

IOL= 2rnA

20
-20

I!A

Vee = 5.5V
Vo= Vee-.4V

low-level output voltage, VOL

0.4

Off-state output current, loz

20
-20

Input current, Ii

±50

I!A

Supply current, Icc
(tested w/clocks running & part in reset)

rnA

25
15

pF
pF

Input capacitance, CI
- Data bus
- All others
Output capacitance, Co
I' - Data bus
- All others

D521 0378-8

25
10

6-12

25
10

Vce= 5.5V

f=1MHz,
all other pins OV
pF
pF

1990 Microchip Technology Inc.

DSP320C10
PARAMETER MEASUREMENT INFORMATION
FIGURE 2 " TEST LOAD CIRCUIT

v = 2.14V
From output{L= 870 ohms
under test
Test Point
~

CL= 100pF

TIL Load Condition

FIGURE 3 " AC TIMING VOLTAGE REFERENCE LEVELS

b. Outputs, TTL compatible

a. Inputs, TTL compatible
2.00V

0.80V -

r-- " -c=

VIH

(min.)

2.00V

VIL

(max.)

0.80V

r-- " -c=

VOH (min.)
VOL (max.)

0521037B-9

6-13

DSP320C10
CLOCK
The DSP320C 10 can use either its internal oscillator or
an external frequency source for a clock.

INTERNAL CLOCK OPTION
The internal oscillator is enabled by connecting a crystal
across Xl and X2/CLKIN (See Figure 1) . The frequency
of CLKOUT is one-fourth the crystal fundamental frequency.

FIGURE 1 -INTERNAL CLOCK
OPTION

C1 ~

The crystal should be fundamental mode, and parallel
resonant, with an effective series resistance of 30 ohms,
a power dissipation of 1mW, and be speCified at a load
capacitance of 20pF.

EXTERNAL CLOCK OPTION
An external frequency source can be used by injecting
the frequency directly into X2/CLKIN with Xl left unconnected.
The external frequency injected must conform to the
specifications listed in the table below.

CLOCK FREQUENCIES
Characteristics

DSP320Cl0 Crystal frequency
DSP320C 10-14 Crystal frequency
DSP320Cl0-25 Crystal frequency
DSP320Cl0-32 Crystal frequency
Cl,C2

D521 0378.10

Sym

Min

fx
fx
fx
fx

6.7
6.7
6.7
6.7

Nom

Max

Unit

Temperature
Range Conditions

20.5
14.4
25.6
32.8

MHz
MHz
MHz
MHz
pf

I,C
I,C
I,C
I,C
I,C

DSP320C10
CLOCK (CONT.)
TA (Commercial) = 0' to 70' C
TA (Industrial) = _40' to 85' C
Vee = 5V + 10%. Vss = OV

CLOCK AC CHARACTERISTICS
Timing requirements/Switching Characteristics over Recommended Operating Conditions

DSP320Cl0
Characteristics

DSP320Cl ()"25

DSP320Cl0·14

DSP320Cl0·32

Sym

Min

NOll

Max

Min

Nom

Max

Min

Nom

Max

Min

Nom

Max

Te(MC)

48.78

Unit Conditions

150

69.50

150

30.5

150

ns Note 1

Rise time mast. elk in. Tr(MC)

10'

TI(MC)

Tw(MCl)

14'

12'

high, Te(MC) = 70ns

Tw{MCH)

14'

12'

Pulse duro mast elk

Tw{MCP) OATele), -

Master elk cycle time

Fall time mast. elk in.
Pulse dur. mast. elk
low, Te(MC) = 70ns
Pulse dur. mast elk

0.6TeIG)' OATClC)' -

0.6TelG)' OA5TClG)' -

0.55TeIG), 0.45TClG)' -

ClKOUT eyele time

Te(C)

277.80

156

122

ClKOUT rise time

Tr(C)

TI(C)

Pis. dur., ClKOUT low Tw(Cl)

131

Pls.dur., ClKOUT high Tw(CH)

129

ClKOUT fall time

195.12

0.55Tc(G)' ns
ns

ns See Fig 2

ns
ns

Delay time to ClKIN!
to ClKOUTJ- (Note 2) Td(MCC)
Note:

(1) Te(e) is the cycle time of CLKOUT. i.e., 4'TC(MC) (4 times eLKIN cycle time if an external oscillator is used)
(2) 'These values were derived from characterization data and are not tested or guaranteed.

CLOCK TIMING
Q3

X2/CLKIN
(DSP internal
clock)
Tw(CH)
CLKOUT
TF(C)

TR(C)
Tw(CL)
Tc(C)

, TD(MCC) and TW(MCP) are referenced to an intermediate level of 1.5 volts on the ClKIN waveform.
Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage
of 2.0 volts, unless otherwise noted.

DS210378-11

6-15

DSP320C10
MEMORY AND PERIPHERAL INTERFACE TIMING
MEMORY AND PERIPHERAL INTERFACE - AC CHARACTERISTICS
Over recommended operating conditions
Characteristics

Sym

Min

Typ

Max

Unit

Conditions

Delay time CLKOUT! to address bus valid (see note)

Td1

10'

See Figure 2

Delay time CLKOUT! to MEN!

Td2

1/4Tc(C) -5'

1/4Tc(C) +12

Delay time CLKOUT! to MENi

Td3

-S'

Delay time CLKOUT! to DEN!

Td4

1/4Tc(C) -5'

1/4Tc(C) +12

Delay time CLKOUT! to DENi

TdS

-S'

Delay time CLKOUT! to WE!

Td6

1/2Tc(C) -5'

1/2Tc(C) +12

Delay time CLKOUT! to WEi

Td7

-S'

Delay time CLKOUT! to data bus OUT valid

TdS

1/4Tc(C) +40

Time after CLKOUT! that data bus starts to be driven

Td9

1/4Tc(C) - 5'

Time after CLKOUT! that data bus stops being driven

Td10

1/4Tc(C) +30'

1/4Tc(C) -10

Delay time DENi. MENi and WEi from RS!

Tdll

Tc(C) + 50'

Setup time data bus valid prior to CLKOUT!

Tsu(D)

Hold time data bus held valid after CLKOUT!

Th(D)

Address bus setup time prior to MEN! or DEN!

Tsu(A-MD)

1/4Tc(C) -35

Address bus hold after WEi. MENi or DENi

Th(A-WMD)

Address bus setup time prior to WE!

TsuIA-WE)

1/2Tc(C) -34

Data bus setup time prior to WE!

TsuID-WE)

1/4Tc(C) -32

Data bus hold after WEi

ThID·WE)

1/4Tc(C) -18

External memory access time

Tacc

Tc(C) - 69

External memory output enable time

Toe

3/4 Tc(C) - 40

Data bus OUT valid after CLKOUT!

'These values were derived from characterization data and are not tested.
Note:
1. Address bus will be valid upon WEi. DENi. or MENi.
2. Data may be removed from the data bus upon MENi or DENi preceding CLKOUT!

D821 0378-12

6-16

DSP320C10
MEMORY AND PERIPHERAL INTERFACE TIMING (CONT.)
MEMORY READ TIMING DIAGRAM
Tc(C)
CLKOUT

MEN
Tsu(A-MO)
ADDRESS BUS VALID

A11-AO

015-00

___..J>>---------------~

Tsu(O)

, '.

~NSTRUCTION IN VALID

TH(O)

p--------

Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts. unless otherwise noted.

6-17

08210378-13

DSP320C10
INSTRUCTION TIMING DIAGRAMS (CONT.)
TBLR INSTRUCTION TIMING DIAGRAM
CLKOUT

MEN

All-AO

015-00

Legend:
L
2.
3.
4.
5.
6.

TBLR INSTRUCTION PREFETCH
DUMMY PREFETCH
DATA FETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
ADDRESS BUS VALID

ADDRESS BUS VALID
ADDRESS BUS VALID
INSTRUCTION IN VALID
10. INSTRUCTION IN VALID
11. DATA IN VALID
12. INSTRUCTION IN VALID

8.
9.

Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

TBLW INSTRUCTION TIMING DIAGRAM
CLKOUT

MEN

A11-AO

015-00

Legend:
L
2.
3.
4.
5.
6.

TBLW INSTRUCTION PREFETCH
DUMMY PREFETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
ADDRESS BUS VALID
ADDRESS BUS VALID

7.
8.
9.
10.
1L

ADDRESS BUS VALID
INSTRUCTION IN VALID
INSTRUCTION IN VALID
DATA OUT VALID
INSTRUCTION IN VALID

Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

OS21 0378-14

6-18

DSP320C10
INSTRUCTION TIMING DIAGRAMS (CONT.)
IN INSTRUCTION TIMING DIAGRAM

Legend:
1. IN INSTRUCTION PREFETCH

2. NEXT INSTRUCTION PREFETCH
3. ADDRESS BUS VALID
4. PERIPHERAL ADDRESS VALID

5. ADDRESS BUS VALID
6. INSTRUCTION IN VALID
7. DATA IN VALID
8. INSTRUCTION IN VALID

Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

OUT INSTRUCTION TIMING DIAGRAM
CLKOUT

MEN

A11-AO

015-00

Th(D-WE}

Legend:

1.
2.
3.
4.

OUT INSTRUCTION PRE FETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
PERIPHERAL ADDRESS VALID

5. ADDRESS BUS VALID
6. INSTRUCTION IN VALID
7. DATA OUT VALID

Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts,
unless otherwise noted.

DS210378-15

6-19

DSP320C10
RESET (RS) TIMING
RESET TIMING AC CHARACTERISTICS
Timing requirements over recommended operating conditions

Characteristics

Sym

Min

Reset (RS) setup time prior to
CLKOUT. See notes 1-4.
DSP320C 10-32

Tsu(R)

RS pulse duration

Tw(R)

5Tc(C)

Delay time DENI, WEI, and
MENI from RSJ.,

Td11

Tc(C) + 50·

Tdis(R)

3/4Tc(C) + 120·

Data bus disable time after RS

Nom

Max

Unit

Conditions

See Figure 2

Note: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.
·These values were derived from characterization data and are not tested.

FIGURE 4 • RESET TIMING
CLKOUT

~TdiS(R)

015-00

----~--------

-----41\

Data In from
pc Addr (0)

'-------..r5ata In from

~Addr(PC+1)

Data shown relative to WE

Address
Bus

AB=PC XAB=PC+1
AB = Address Bus

X=~:

AB=PC=O ~+1
---------

Notes:
1. RS forces DEN, WE, and MEN high and tristates data bus DO through 015. AB outputs (and program counter) are
synchronously cleared to zero after the next complete elK cycle from RSJ,.
2.
RS must be maintained for a minimum of five clock cycles.
3. Resumption of normal program will commence after one complete elK cycle from RS1'.
4.
Due to the synchronizing action on AS, time to execute the function can vary dependent upon when RS1' or RSJ, occur in the
ClK cycle.
5.
Diagram shown is for definition purpose only. DEN, WE, and MEN are mutually exclusive.
6. Timing measurements are referenced to and from a low voltage of O.S volts and a high voltage of 2.0 volts, unless otherwise
noted.
7. During a write cycle, RS may produce an invalid write address.

DS21037B-16

6-20

DSP320C10
INTERRUPT (INT) TIMING
INTERRUPT TIMING AC CHARACTERISTICS
* These values are not tested

Timing requirements over recommended operating conditions
Characteristics

Min

Sym

Fall time INT

Tw(lNT)

Setup time INTJ, before CLKOUT J.-

T8u(INT)

Max

Unit

15*

Tc(C)

Tf(INT)

Pulse duration INT

Nom

Conditions

INTERRUPT TIMING DIAGRAM

CLKOUT

~Jl ~t--TSU-(INT-)-..J/

INT

(

~
i
______
Tw(INT)

TF(INT)

---__00_

Note: Timing measurements are referenced to and from a low voltage of O.B volts and a high voltage of
2.0 volts. unless otherwise noted.

I/O (810) TIMING
1/0 (810) AC CHARACTERISTICS
* These values are not tested

Timing requirements over recommended operating conditions
Characteristics

Sym

Min

Nom

Max

Unit

Tf(IO)

15*

Pulse duration 810

Tw(IO)

Tc(C)

Setup time 810J.- before CLKOUT J.-

T8u(10)

Fall time 810

Conditions

1/0 (810) TIMING DIAGRAM
CLKOUT

-fJ----L--T Tsu(IO)

BIO

"'(0)

~k:=====-TW-(I-O-)

\'-----J/

-'f(

- - - -..

Note: Timing measurements are referenced to and from a low voltage of O.B volts and a high voltage of
2.0 volts, unless otherwise noted.

D821037B-17

6-21

DSP320C10
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.

PART NUMBERS
DSP320C10 • 32 I / P

Package:

P
L

Temperature
Range:

Blank
to 70° C
I
-40 to 85° C

Frequency:

25
32

I
I

DS21 0376-18

Device

Plastic DIP
PLCC

DSP320C10

6-22

14.4 MHz
20.5 MHz
25.6 MHz
32.8 MHz

Digital Signal Processor

Microchip

APPLICATION NOTES

DSP320CIO DIGITAL
SIGNAL PROCESSOR
SUPPORT TOOLS
Introduction
The following information relates to the support tools available for Microchip's
DSP320C10 Digital Signal Processor. A brief description of each tool is provided
along with the availability and prices. A part number is assigned for each product
and this number should be used when ordering.
For more information, please contact your local Microchip sales office. Microchip
reserves the rights to change the specifications of each system without notice.

Systems & Tools
Hardware Tools:
Please contact your local sales office or factory for a list of third party support
products. These include in-circuit emulators, EVM boards and other plug in
modules.

Software Tools:
IProduct

Function

C10ASM

A cross assembler and linker with macro capabilities for
DSP320C1 O. Various computer systems are supported.

C10SIM

A software instruction level simulator of DSP320C10.
Available on various computer systems.

Please contact your local sales office or factory for a list of third party support
products. These include assemblers/linkers, filter design packages and other
DSP libraries.

DS21047B- 1

6-23

DSP320C10

SUPPORT TOOLS

CIOASM (ASSEMBLER/L1NKER)
Description
This is a cross assembler which converts the source code to object code for
Microchip's DSP320C10 series of 16-bit digital signal processors. A linker is also
provided for combining separately assembled modules into one or more object
modules. Multiple object code format is provided and supports formats required
by all other Microchip's development systems. One of the output format is 8 bit
Intel hex format. Under this format two separate files with high bytes in one and
low bytes in another file are produced. This eases programming 8 bit wide
EPROMs.

Functional Features
Absolute and Relocatable addressing.
Conditional assembly.
Macro capability.
External Symbol Reference.
Multiple Object code formats.
Combines separately assembled modules into one or more object modules.
External Symbol resolution.
ROM/RAM partitioning.
Object code libraries and Multiple Object code formats.

Minimum Host Requirements :
MS-DOS -- 512k RAM.
VAXNMS.

Part Number & Ordering Information
C10ASM-DS
C10ASM-VS

C10 Assembler/Linker for MS-DOS systems/IBM
compatibles
C 10 Assembler/Linker for DEC VAX/VMS

D821047B- 2

6-24

DSP320C10 SUPPORT TOOLS

CIOSIM (SIMULATOR)
Description
This is a software simulator simulating the DSP320C10 series. The simulator
accepts any object code format generated by Microchip's cross assembler, and
aids in debugging and testing microcode. Algorithms and software development
can be executed without waiting for silicon and other hardware. Since the
simulator is totally under software control, the user has a lot more control in
execution of his code through complex breakpoints, trace, single stepping,
viewing/modifying. Various signals, memory locations and registers can be
viewed very easily. Signals can be injected or captured from/to files by redirecting
the 110 port to files, and then be analyzed by other software.

Functional Features
Instruction Boundary Simulation
Three execution modes ( execute until break condition, trace and single
stepping).
Flexible breakpoints : On Instruction acquisition, error conditions, data
conditions and maskable memory read/wr,ite.
Watch/modify registers and memory locations.
128 instruction trace buffer (can be output to a file).
Continuous trace mode
Symbolic debug and symbolic disassembler.
File associated port I/O.
Programmable interrupts.
Friendly user interface that can constantly display registers and memory on
screen.
Input/Output Radix can be Hex, decimal or Octal.

Part Number & Ordering Information
C10SIM-DS
C10SIM-VS

C10 Simulator for MS-DOS systems/IBM compatibles
C10 Simulator for DEC VAX/VMS

DS21 0478- 3

6-25

DSP320C10

SUPPORT TOOLS

NOTES:

08210478- 4

6-26

Microchip

SECTION 7
QUALITY AND RELIABILITY
QA
27Cxxx

Quality Without Compromise .................................................................................... 7- 1
EPROM Plastic Package Reliability Bulletin ............................................................. 7- 11

DS00018C

7-i

Microchip

DS00018C

Microchip

Quality Without Compromise
A CORPORATE COMMITMENT
Raising the quality level of Microchip's products and
services is a performance alliance built with customers
and suppliers.
Total quality improvement and quality awareness is
powered by company-wide participation.
Meeting a customer's expectations is where quality
commitment begins. The resolve to continuously improve as a supplier never ends.

THE CHALLENGE OF COMPLEXITY
Integrating An Ideal
Microchip's quality programs and business plan are vertically integrated and touch all levels of the company.
From the top down the President and CEO actively leads
and audits programs to ensure continuous improvement
is a perpetual process. Quality teams work from the
bottom up to improve performance at every department
level. Incorporating quality improvement objectives into
the business plan creates a unity of purpose and mandates that the two merge as one measurement.

Determination To Be The Best
Through statistical management and the use of statistical tools, a framework is built for becoming a continuously improving supplier. The programs put in place are
to become the foundation for success.

7-1

OS000476-1

Quality & Reliability
PROCESS TECHNOLOGY

QUALITY

EEPROM Technology

Design For Quality And Reliability

Microchip's CMOS floating gate EEPROM technology
produces a non-volatile memory cell by storing or removing charge from the floating gate. Charge is transferred bidirectionally to the floating gate by FowlerNordheim tunneling through a sub-1 0 nm oxide over the
drain of the transistor. This technology produces a
memory cell with a guaranteed endurance of > 10" which
can be erased automatically and byte written in-situ in a
system, all in 1 ms.

Product reliability is designed into all Microchip processes and products. Design margins are established to
guarantee every product can be produced economically, error-free and within the tolerances of the manufacturing process. Design committee members representing manufacturing, engineering, quality and product
divisions ensure that exacting standards are met for
each specific product.

Documentation And Procurement
Specifications

EPROM Technology
The CMOS EPROM technology produces a non-volatile
memory cell by storing or removing charge from a selfaligned floating gate. Electrons are provided to the
floating gate via hot electron injection from the drain
depletion region, and are removed by radiation from a
high intensity UV source. This memory cell is guaranteed to have an endurance of > 100. Programming is
done off-line using an EPROM programmer and block
erasing accomplished with a high intensity UV source
through the package window.

Microchip's positive documentation control program
assures the correct and current document always is
available at the point of use. Active documents are
revision coded and serialized. Procurement specifications bear the same requirements. These positive
document control procedures, which are common in the
industry for military and high reliability products, are
employed by Microchip, system wide.

SNOS Technology

Product integrity is assured by samplings and inspection plans performed in line. This enables Microchip to
control and improve product quality levels as product
moves through the manufacturing operation. Microchip's acceptance sampling plans in assembly emphasize the attempt to eliminate defective product as it is
discovered. Acceptance and sampling plans follow MILSTD-SS3C procedures where applicable.

In Line Controls And Process Assessment

Microchip's SNOS EEPROM technology produces a
non-volatile memory cell which stores or removes charge
from the nitrite/oxide interface by electron tunneling
through a sub-5 nm oxide under the nitride. This cell is
guaranteed to have an endurance> 10'. Individual bytes
can be written in-situ in a system at 30 ms but due to
layout design constraints, a circuit can only be block
erased.

To determine whether a process is within normal manufacturing variation, statistical techniques are put to work
at selected process steps. In-process controls are
performed by operators in the wafer fabrication and
assembly operations. Operators take immediate corrective action if a process step is out of its control limit.
Through these in-line controls the true capability of a
process is assured and data to guide continuous improvement is generated. (See Appendix A - Controls)

Microcontroller and Logic
Logic Products use an N-well CMOS technology.
Depending on functionality and/or performance requirements, however, different variations of the CMOS process are used. These include ROM, EPROM or EEPROM
and use of single or double level metallization. Two
levels of polysilicon are used for EPROM, EEPROM or
capacitors (in analog circuits).

Material controls prevent defective piece parts from
getting into the line. Microchip's assembly material
control sample plan is typical of the emphasis placed on
safeguards. (See Appendix B - Material Controls)

Oxide spacers are used to obtain DDD (Double Diffused
Drains) and titanium is used for polycide formation for
low resistance poly lines. The process uses a 250 A
gate-oxide thickness and 550 A interpoly oxide thickness. Boron and Phosphorous plugs are used for Ncontacts and P-contacts to prevent junction spiking.

DS000478 - 2

Testing For Margin
Microchip conducts a product's initial test under stringent requirements. All quality assurance tests are run to
tighter limits than customer specifications. As part of an
out going quality assurance program, most products are
tested at least two machine tolerances tighter than those
specified by the customer. Margin testing accounts for
normal tolerances of any particular test system and
provides customers with the assurance that Microchip's
products meet a customer's specifications.

7-2

Quality & Reliability
RELIABILITY
Variation From Expectation

Process Qualification

Microchip works to make variation from target as small
as possible. The better process is the one that holds the
narrowest dispersion. Presently Microchip uses electrical screens to help eliminate short term failures. The
long term program of total quality improvement emphasizes continuous improvement.

No priority is more important than the one where processes under which Microchip products are built operate
without fail. Engineers labor under strict guidelines to
ensure tests of sample lots are precise and reliable.
Exacting internal specifications demand every product
used to qualify a process endure an accelerated life test.
EPROMs, EEPROMs, and Logic Products are stressed
beyond normal use limits when undergoing high temperature reverse bias, operating life, and retention bake
tests.

Individuals in all departments are encouraged to analyze the methods employed at their positions and formulate plans to improve performance. Because a customer
could receive part of every mistake, definitive programs
are continuously formulated at all working levels, designed to eliminate mistakes and contain error.

Package Qualification
Package qualification measures a component's ability to
withstand thermal and mechanical shock, temperature
cycles and moisture. Stresses applied to products
exceed normal parts use. All products are stressed to
high level military or industrial specifications to ensure
reliability.

Outgoing Qualitv
Quality Control samples all outgoing productfrom Microchip final testing.

Ongoing Sampling Of Key Reliability
Variables
Microchip conducts accelerated mechanical tests, operating life tests and memory retention tests to explore the
many ways failures might occur. Data gleaned from
continuous testing is used to identify potential reliability
problems and for defining action courses to improve
product. Microchip's reliability knowledge is shared with
customers. This data is available for use in customer's
own quality and reliability improvement programs.

7-3

D5000478 - 3

Quality & Reliability
RELIABILITY CONCEPTS
Definition

Temperature Dependency

Reliability is the probability of a system or circuit performing its predefined function adequately under specific conditions for a given period of time. Thus. the
reliability of a microcircuit is a function of both stress
conditions and the time of operation.

In order to establish failure rates in a reasonable time, it
is necessary to accelerate by higher environmental
stress levels, the incidence of the failure modes encountered under normal conditions. The accelerating parameter most employed is junction temperature, although voltage and humidity, for example, are also
used. Higher temperatures are capable of accelerating
many common failure modes dramatically.

The reliability (or probability of survival) range runs from
(no chance of survival) to 1 (no chance of failure).
Current microelectronic circuits are manufactured and
controlled to such tight specifications that reliability
figures for the total operation time approaching 1 (i.e.,
0.9999) are common. As a result, the complement of
reliability, orthe failure probability, is more often quoted
in current literature.

Arrhenius Equation
A number of mathematical models were developed to
quantify the relationship between accelerated failure
rates and increased junction temperatures. The one
model most commonly used is known as the Arrhenius
Equation. It is as follows:

The failure rate isthe rate atwhich failures occur on units
surviving to a specific number of hours of operation.
Failure rates per unit circuit-hour would generally be
very small. To avoid reporting such small numbers,
failure rates have been defined for longer periods of
circuit-hours. One thousand circuit-hours is defined as
one circuit operating for one thousand hours, or 1,000
circuits operating for 1 hour, etc. The number of circuithours is the number of circuits multiplied by the number
of operation hours for each circuit.

AF = e', Where:

AF = Acceleration Factor (non-dimensional)
e = 2.718281828 .... (non-dimensional constant)
EA

=Activation energy level (electron volts)

k = Boltzmann's constant
tron-volts/degree Kelvin)

Two methods of failure rate statements are commonly
used:
* Percent failures per thousand circuit-hours,
(represented as A), or

(elec-

TN = Normal junction temperature (degrees Kelvin)
TA = Accelerated junction temperature (degrees Kelvin)

* Absolute failures per 109 circuit-hours, or Fits.
Note that a failure rate of 0.0001 %/1 000 hours and 1 Fit
are equivalent numbers.

Thus, the time to achieve a certain probability of failure
at time T 1 under temperature TN can be compressed by
the amount T 1 divided by AF at the accelerated temperature T A. Note that for true acceleration, the acceleration
factor AF is independent of the probability olthe fail point
specified.

Bathtub Curve: Failure Rate Over Time
The generic representational graph of failure rate vs.
time takes the shape of a bathtub curve. (Figure 1).
The early failure rate (infant mortality) period starts from
initial operation (time To) and decreases as time goes
on.
Time Tl signifies the end of the infant mortality period.
The next phase of the curve occurs between time T 1 and
T2. This long period of time is distinguished by a nearly
constant and very low failure rate. AfterT2 is passed, the
failure rate starts to increase slowly. This last phase of
failure rate vs. time is known as the wear-out period.

FIGURE 1: BATHTUB CURVE
FAILURE RATE

\..• ... • ",
TO

03000476 - 4

= 8.6172754* 10-5

7-4

•
Tl

0001
TIME

•
T2

Quality & Reliability
RELIABILITY TESTS
Actiyation Energy Level

Operating Life Test

The dependent variable AF in the Arrhenius Equation is
a function of several variables. TN and TA are specified
for the situation under consideration. EA is a function of
the particular mode of failure, and can be viewed as the
minimum energy required for a particular failure to occur.

The Operating Life Test is run under dynamic bias conditions where inputs are clocked like a typical application
and outputs are loaded in the same way as a typical application. The test is conducted at high temperature to
accelerate the failure mechanisms. The normal temperature for the test is + 125·C for 1 ,000 hours. Readouts
occur at 24, 168, 500 and 1,000 hours. Early hour
failures are usually associated with test escapes, manufacturing defects or otherwise marginal material. Longer
term failures are typically caused by metal migration,
ionic contamination, and oxide breakdowns.

Activation energy levels in semiconductors generally
are in the 0.4 - 1.1 electron-volt range. Each failure
mode that is accelerated has its own activation energy
level. Some typical examples are:

FAILURE MECHANISM
Oxide/Dielectric Defects
Chemical, Galvanic, or Electrolytic
Corrosion Silicon Defect
Electromigration
Unknown
Broken Bonds
Lifted Die
Surface Related Contamination
Induced Shifts/ Lifted
Bonds (Au-A1 Interface)
Charge Injection
Floating Gate Charge Loss
Hot Electron Trapping
Tunnel Dielectric Breakdown

EA(eV)
0.3
0.3

High Temperature Reverse Bias (HTRBl
Microchip employs the High Temperature Reverse Bias
test on floating gate devices to accelerate any charge
gain onto the floating gate due to oxide defects and to
accelerate threshold shifts due to ionic contamination.
The test is conducted by putting the device into a special
test mode whereby 7.0 volts is applied to all poly 2 structures with all source, drain and substrate held at ground.
The test is conducted at +150·C and is normally conducted for 1,000 hours with readouts at 24, 168,500 and
1,000 hours.

0.5
0.5 to 0.7
0.7
0.7
0.7
1.0
1.0

1.3
0.6
-.06

Retention Bake

0.13

The Retention Bake Test is performed to accelerate
data loss on floating gate and SNOS devices. The test
consists of unbiased baking at elevated temperature.
Usually the test lasts for 1,000 hours at + 150·C. The
failure mechanism that is accelerated is charge leakage
from a stored element.

A compromise value of 0.7 electron-volts is often used
when there are no specific a prior facts relating to the
failure modes being accelerated.
There is however, a contino us reliability program at
Microchip structured to validate EA values in use and to
categorize new failure mechanisms.

Endurance Cycling
Endurance Cycling establishes the number of times a
programmable device can be programmed and erased.
Normally the test is conducted at worse ~ase programming conditions and is followed by a retention bake.

Temperature Cycle
The Temperature Cycle test simulates systems that are
subject to power up/power down sequences. The test is
intended to reveal any deficiencies resulting from thermal expansion mismatch of the die/package structure.
Normally the test is conducted by cycling between -65·C
and +150·C in an air ambient. Duration for the test is
normally 1,000 cycles for plastic and 100 cycles for
ceramic packages. Endpoint criteria is both electrical
and mechanical.

7-5

0500047B-5

Quality & Reliability
RELIABILITY TESTS (CONT.)

QUALIFICATION CATEGORIES

Thermal Shock

Qualification is required for new design, major changes
in old design, process or material when either wafer
fabrication or package assembly operations are affected. Qualification applies to the following changes:

The Thermal Shock test is similar to the Temperature
Cycle test except that the ambient during cycling is
liquid-to-liquid which simulates rapid environment
changes. The mechanisms accelerated are identical to
those in the Temperature Cycle test except that the
Thermal Shock test is a more accelerated test with temperatures normally + 125°C to -55°C and the number of
cycles are typically 15.

New technology

II.

Start-up of Fab or Assembly

III. Transfer of fab or assembly to another location
IV. Major process changes:

Autoclave·
The autoclave test determines the survivability of devices in molded plastic packages to a hot, humid environment. The test exposes unbiased, plastic packaged
devices to saturated steam at 121°C and 15 pounds per
square inch (one atmosphere) gauge pressure. The 168
or more hours of testing allows moisture to penetrate to
the die surface. Chemical corrosion olthe die metallization may occur if ionic contaminants are present and the
die surface protection is deficient or damaged. Charge
leaks from floating gate devices usually happen before
a corrosion mechanism develops.

Process scaling (shrink conversion)

Change in vendor or material source

New equipment that affects reliability

New die configurations:
A.

New structures

New packaging material

Design rule changes

Existing package revision (dimensional or
layout)

QUALIFICATION PROGRAMS

Temperature Humidity Test

Qualifications guarantee new processes and technologies are properly evaluated for reliability performance.

The Temperature Humidity test determines the survivability of devices in molded plastic packages functioning
in a humid environment. By convention, test conditions
are 85°C and 85% relative humidity. The parts are
biased to lend themselves to electrochemical corrosion.
The duration of the test is usually 1,000 hours or more.
The test checks the adequacy of the die surface protection and the plastic's lack of ionic impurities. The applied
bias may be 5 volts on alternating pins or set up for minimum power to reduce internal heating and consequent
moisture evaporation on the device. Similar to the
Autoclave test, charge loss on floating gate devices is a
principle failure mechanism.
.

D8000478 - 6

Reliability Monitoring
Microchip's reliability monitoring program is a comprehensive effort to measure the reliability of all process
families with strict regularity. The program strives to
improve performance through failure analysis and corrective action. Numerous screening procedures are
used and estimates of product life and expected failure
rates are provided.
Typical tests and frequency on each process family
include:

7-6

168 hour operating life - weekly

1,000 hour operating life - annually

Endurance test - weekly

Data retention test - weekly

Temperature cycle - weekly

Temperature humidity - annually

Long term retention - annually

Mechanical tests - annually

Quality & Reliability
APPENDIX A - IN-LINE CONTROLS

CONTROLS - PLASTIC PACKAGE ASSEMBLY
PROCESS
STEP

REJECT
PARAMETER
LIMITS

SAMPLE
PLAN

FUNCTION
PROD

Die Visual
Inspection

Reject For
Any Defect

100%

Wafer Saw

Report Failure
Modes

1 Slice
Per Lot
Visual

883C
Method
2010

Die Attach
Inspection

Machine
Shut Down

5/Shift
Each
Machine

SS3C
Method
2019

Wire Bond
Inspection

Report Failure
Mode
Machine Shut
Down

1%AQL
Each Half
Shift

883C
Method
2011 D
2010

Post Wire
Bond Visual
Inspect

Reject For
Any Defect

100%

Mould Press
Visual

Machine
Shut Down

LTPD
15%
A=O

X-Ray
Monitor

Package
Visual

Report Defects
100% Screen
For Major Defects

LTPD
2%
A=O

N/A

Trim & Form
Visual

Report Defects
100% Screen
For Major Defects

LTPD
2%
A=O

S83C
Method
2016

External Final
Visual
Inspection
- Run Ticket
Verification
- Marking
Legibility
- Package Outline
Check
- Solderability
Monitor
- Package Form

Major Defects
100% Screen

LTPD 2%
A=O

SS3C
Method
2009

7-7

MIL
STD
REP

883C
Method
2010 B

SS3C
Method
2010

05000478 - 7

Quality & Reliability

CONTROLS· CERAMIC PACKAGE ASSEMBLY
PROCESS
STEP

REJECT
PARAMETER

SAMPLE
PLAN
LIMITS

FUNCTION
fBQQ

QC.

MIL
STD
REP
883C
Method
2010 B

Die Visual
Inspection

Reject For
Any Defect

100%

Wafer Saw
Inspection

Machine
Shut Down

1 Slicel
Lot
Visual

883C
Method
2010

Die Attach
Inspection

Machine
Shut Down

Non-destruct
Each gjyJ;
Destruct Each Shift

883C
Method
2019

Wire Bond
Inspection

Report Failure
Mode
Machine Shut
Down

1%AQL
Each Half
Shift

883C
Method
2011 D
2010

Preseal
Visual
Inspection

Reject For
Any Defect

LTPD
15%
A=O

Package
Seal
Inspection

Machine
Shut Down

LTPD
15%
A=O

883C
Method
1014

Fine Leak
Test

Screen 100%

LTPD
5%
A=O

883C
Method
1014

Gross Leak
Test

Screen 100%

LTPD
5%
A=O

883C
Method
2014

Lead Trim
Visual

Screen 100%

LTPD
2%
A=O

883C
Method
2016

Package Mark
Inspection

Machine
Shut Down

LTPD
10%
A=1

883C
Method
2015

Environmental
Inspection

Machine
Shut Dow

LTPD
5%
A=O

883C
MEithods
1010C
2001E,
1014

External
Package
Visual

Screen 100%

LTPD
10%
A=1

883C
Method
2009

0500047B-8

7-8

883C
Method
2010 B

Quality & Reliability
APPENDIX B • MATERIAL CONTROLS

MATERIAL CONTROLS - PLASTIC PACKAGE ASSEMBLY

PROCESS
STEP
Lead Frame
Inspection

REJECT
PARAMETER
LIMITS

SAMPLE PLAN

Reject For
Any Failure

Visual
Functional

LTPD 2%
A=O
LTPD 10%
A=O

Die Mount
Epoxy Inspect

Functional
Test-Reject
Any Failure

3 Sample Runs

GoldWire
Inspection

Reject For
Any Defect

2 Spools
Per Lot
A=O

Mould Compound
Inspection

Storage Temp
SoC
Pellet Weight
±SGMS
Functional Test
Any Failure

3 Sample
Runs

7-9

08000478 -9

Quality & Reliability

MATERIAL CONTROLS - CERAMIC PACKAGE ASSEMBLY
PROCESS
STEP

REJECT
PARAMETER
LIMITS

Package Inspection
Mechanical Visual
- Hermeticity
- Plating Thickness
Bake Visual

Reject For
Any Defect

Preform Inspection

Reject For
Any Defect

SAMPLE PLAN

Bond Wire Inspection

Reject For
Any Defect

Lid Inspection

Reject For
Any Defect

DS000478 - 10

FUNCTION
PROD

Visual
Functional

7-10

. MIL
STD
REP

LTPD %
10A=O
15A=O
10A=O
15A=O

N/A

LTPD %
10A=O
15A=O

N/A

2 Spools
Per Lot
A=O

N/A

LTPD %
7 A=O
10A=O

N/A

27Cxxx EPROM Family

Microchip

Plastic Package Reliability Bulletin
AVERAGE OUTGOING QUALITY OF PLASTIC
EPROMS
Microchip Technology Inc.'s organized data on outgoing
quality of plastic EPROMs tracks parametric failures such

500

400

Il.
Il.

.
.;,

OVERVIEW
Microchip Technology Inc.'s Plastic EPROM products provide competitive leadership in quality and reliability, with
demonstrated performance of less than 170 FITs (Failures
in Time) operating life. The designed-in reliability of
Microchip Technology Inc.'s Plastic EPROMs is supported
by ongoing reliability data monitors. This document presents current data for your use - to provide you with results
you can count on.
The test descriptions included in this document explain
Microchip Technology Inc.'s quality and reliability system,
and the EPROM product data demonstrate its results .

300

200

100

2Q88

30S8

4088

1089

2089

3089

4Q89

Quarter/Year

The customer's quality requirements are Microchip Technology Inc.'s top priority: Ongoing customer feedback and
device performance monitoring drive Microchip Technology Inc.'s manufacturing and design process, leading to
continuing improvements in the long-term quality and
reliability of Microchip Technology Inc.'s products.

PRODUCT SCOPE
as speed, power and device leakage. Its present level has
reached 200 ppm after programming, with a goal of 100
ppm.

Subject of this Product Reliability Bulletin are the Plastic
Packages of Microchip Technology Inc.'s EPROM Product Family:

As plastic parts have extremely high impact resistance,
visual/mechanical failure rate is expected to run half the
expected failure rate of ceramic parts.

27C64-XXlYV
27C128-XXlYV
27C256-XXNY
27C512-XXNY

300 " , - - , - - - - , - - - - ; - - - - - , - - - , - - , - - - - , - - - - - - , - - - ,

Il.
Il.

These EPROMs are available in a range of access times
designated by the XX parameter: 120, 150, 170, 200 and
250 ns. Available plastic packages are identified by the VV
parameter: Plastic DIP, PLCC, and SOIC.

200

64K (8Kx8) CMOS EPROM
128K (16Kx8) CMOS EPROM
256K (32Kx8) CMOS EPROM
512K (64Kx8) CMOS EPROM

RELIABILITY DATA

100

1Q8B

2Q88

3088

4088

1089

2Q89

3089

40&9

QuarterNear

Microchip Technology Inc.'s EPROMs in plastic were produced to offer the customer the flexibility of using the
plastic device as a direct substitution for a Cerdip EPROM
in one-time-programming applications. Failure Rate Predictions/Operating Life data for plastic EPROMs at 125°C
proves to be equivalent to the data of ceramic EPROMs
(refer to page 8), opening the way for package substitution
for cost savings and inventory reduction.

DS110088-1

7-11

Plastic EPROM Reliability Bulletin
FAILURE RATE CALCULATION
DEFINITIONS
Extended field life is simulated by using high ambient
temperature. In the semiconductor technology: high temperatures dramatically accelerate the mechanisms leading to component failure. Using performance results at
differenttemperatures, an activation energy is determined
using the Arrhenius equation. For each type of failure
mechanism, the activation energy expresses the degree to
which temperature increases the failure rate.
The activation energy values determined by Microchip
Technology Inc. agree closely with those published in the
literature. For complex CMOS devices in production at
Microchip Technology Inc., an activation energy of 0.7 eV
has been shown to be most representative of typical
failures on operating life, while 0.6 eV is representative of
charge gain or loss failures. By definition, failure is
reached when a device no longer meets the data sheet
specifications as a direct result of the reliability test environment to which it was exposed. Common failure modes
for CMOS integrated circuits are identified for each test environment.

AOQ (Average OUtgoing Quality); The artl.oont of d?"
feetive product in a populatiOn, usually expressed In
terms of parts per million (PPM).

FIT (Failure In Time): Expresses the estimated field
failure rate in number of failures per billion power-on
device-hours. 100 FITS equals 0.01% fall per 1000
device-hours.
Operating Life Test: The device is dynamically exercised at a high ambient temperature (osually 125°C) to
quickly simulate field life; Derating from high temperature, an ambient use condition failure rate can be calculated,
Temperature cycle: The devices are exposed. to
severe extremes of temperator& in an alternaTing fashion (-65°C for 15 minutes, 150°C for 15 minutes per
CYCle),. Package strength, bondquafily and consistency
of assembly process are stressed using this environment

EPROM products have an early failure rate (infant mortality) of less than 0.05% and thus, a production burn-in
should not be necessary. For all products shown, the early
and the intermediate failure rates are combined and expressed as a single failure rate.

Biased-Humidity: Moisture and bias are used to acceI·
erate corrosion-type failures in plastic packaQes, The
conditions include $5·C ambient temperature .with 85%
relative humidity, Typl¢albias voltage is +5vOltsahd
ground on alternating pins.

To establish a field failure rate, the acceleration factor is
applied to the device operating hours observed at high
temperature stress and extrapolated to a failure rate at
55°C ambient temperature in still air.

Autoclave(pressurecoolRQM:
High"emR~ra"re Reverse Blalil (FlTAB): A SpeCial
test ll'iode.whichsubjeplS the. entire EPR.QM array.to a
high .voltage leVlili and is used tOm&asure charge gain
and/on~reshQldshifts..
. ,.
....

High Temp. Reverse Charge gain to EPROM cell
Bias
Parameter drift/shift

05110086-2

7-12

Plastic EPROM Reliability Bulletin
RELIABILITY CONTROL SYSTEM
A comprehensive qualification system
ensures that released products are
designed, processed, packaged and
tested to meet both design functionality and strict reliability objectives. Once
qualified, a reliability monitor system

ensures that wafer fabrication and made after successful demonstration
assembly process performance is of reliability performance. This system
stable over time. A set of baseline results in reliable field performance,
specifications is maintained that states while enabling the smooth phase-in of
which changes require requalification. improved designs and product capabilThese process changes can only be ity.

__-t"''''·RElJABIt.tTYC()NTAQL

·.~e~~~~~~!!:~=~"'~Q~.·.·.tJ~A~L~IF~tC~~l'!!IOIII~
• • . ~. t::-~
Pb~tnn~~~bI~es using

9~alif!~ti,,~;t~ts:.

,. OperlitingUte(12~~Carnbient
~ Temp,~~, .,e!i~f1$)·C
~ . . rherrnaishock,'-65~f150'O

··ESD.IlI~istan(';6,±2000 V
' . Latch-IJP.(OMOSdevices)

• Bia¥d'-hymidit¥;85°Cf85%
'Autoolave(pr~ssure cooker)

retention baklll
•..• ·HT~B

A88ureOl.itIOlngOuallty Level:
• De$igntejease dOClJment
' Baseline wafer fabriClitiol1
process
• Baseline assemblyproc:ess
• QualifICation release
• Enter device to Specification
System
• Wafer-level reliability controls
•.. Pfssembly teliability~ntrols
•.... Early failure. rallll. sampling
,. Reliability m~nitoring
•.. Statlslloalprop&SS coilfrplJel'ld-

back
•.•.• AuditspecifiClltibnS
~Analyze . telumedfailures
• ReqlJalify devi(';6~ a~ nee

(\J

!!!

.a
'm

200

o
Quarter/Year

HIGH TEMPERATURE REVERSE BIAS (150°C/7 Volts)
Microchip Technology Inc.'s EPROMs are designed for enhanced reliability by having a special test mode which
allows all gates on the array to be simultaneously placed
at a high voltage stress level in reference to the rest of the
circuitry. This test is used to create a high voltage stress
on the memory oxide. An additional acceleration of three

times is gained from the 7V level based on experimental
data. This is calculated into the failure rates below. Failures which will be detected with this type of stress are: pin
holes in the oxide, thin oxide layers, and charge gain
failures.

800

150°C HTRB
derated to 55°C
600

400

200

o
3087

4087

1088

2088

3088

4088

1H89

3089

Quarter/Year

7-15

D8110088-5

Plastic EPROM Reliability Bulletin
MOISTURE RESISTANCE TESTING
Moisture resistance evaluation of Microchip Technology
Inc. plastic EPROMs includes both autoclave testing (121°C,
15 PSI) and temperature humidity testing (85°CI 85% relative humidity with bias). Moisture resistance could not be
obtained by the industry standard so a layered passivation
utilizing an Oxy-Nitride film to provide a moisture block
while allowing unblocked UV transmission is used.
The autoclave accelerates any moisture penetration through
the plastic package material or around the metalleadframe

and plastic to leadframe interface. The objective of this
testing is to accelerate failure of the device as a result of
any moisture contamination on the surface of the die.
Failure mechanisms such as passivation defects (pinholes, cracking, lifting), corrosion of bondpads or surface
metal through passivation defects, leakage and surface
contamination as well as charge loss failures may be
identified. The predominantfailure mechanism for EPROMs
is data loss.

AUTOCLAVE (121°C/15 PSI)
Product

Failures/Sample Size

27C256/L
27C64/P
27C128/P
27C256/P
27C5121P
27Cxxx/X (discounted
for charge loss)

24Hrs

96 Hrs

168Hrs

0/723
1/767'
0/380
0/444
0/450
0/2764

0/766
0/380
1/444'
1/450'
31723'
0/2763

1/766'
11766'
21443'
3/449'
91720'
0/2758

, - Failures due to charge loss on EPROM cell

HUMIDITY BIAS· 85°C/850/0RH
Temperature humidity testing is utilized to accelerate
failures through electrolytic corrosion. This is accomplished by subjecting devices to a high temperature and
high humidity atmosphere with bias applied to the device.
The combination of moisture penetration through the plas-

tic package and interaction of the moisture with any contaminates on the surface of the device and the applied
voltage to the unit, will result in electrolytic corrosion and
failure of the device.

85°C/850/0 RH Bias Test

C\I

III

J:
~

::R
0

IX:

::I

=i
u..

o
1087

2087

3087

4087

1088

2088

3088

4088

1H89

3089

QuarterlYear

OS110089-6

7-16

Plastic EPROM Reliability Bulletin
DATA RETENTION BAKE
Data storage in EPROMs is done by developing a
charge on the floating gate structure in the memory cell.
Charge loss in this cell structure results in loss of data.
In order to detect this type of failure, devices are subjected to a 150°C bake. This bake accelerates charge
loss in the memory cell.

This added screen for detecting infant mortality charge
loss allows Microchip Technology Inc. 's plastic product to
duplicate the excellent data retention characteristics of the
ceramic EPROM packages.

800

-----=:---------rn

150°C Retention Bake
derated to 55°C

600

!:::
Ii..

I II

400

I!:!

'"'"

'iii

Ii..

200

o
1087

2087

3087

4087

1088

2088

3088

4088

1H89

3089

Quarter/Year
TEMPERATURE CYCLING (-65°C TO +1S0°C)

Product

This stress is used to evaluate the mechanical integrity of
the plastic package and the assembly process. Temperature cycling consists of cycling the devices between -65°C
and + 150°C atthe rate of 4 cycles per hour. This stress will
identify failure mechanisms such as plastic package cracking, die attach problems, and wire bonds lifting.

27C64/L
27C256/L
27C64/P
27C256/P

THERMAL SHOCK (-55°C TO + 125°C)

Product

This stress is used to evaluate the mechanical integrity of
the plastic package. It consists of rapid immersion of
devices into liquids of -55°C and + 125°C respectively.

Failures/ Sample Size
100 Cycles

500 Cycles

0/34
0/102
0/374
0/68

0/0
0/0
0/340
0/68

Failures/ Sample Size
15 cycles

27C64/P
27C256/L
27C256/P

7-17

0/170
0/34
0/68

05110088-7

Plastic EPROM Reliability Bulletin
PRODUCT RELIABILITY DATA
1988/89 FAILURE RATES AT 60% CONFIDENCE
Reliability Test

Product
24 Hrs

125°C Operating Life

Failures/Sample Size at
168 Hrs 500 Hrs 1000 Hrs

FITs

27C64
27C128
27C256
27C512

0/871
3/393
2/1243
4/954

2/871
1/390
2/1241
1/949

0/198
0/216
2/882
0/948

0/45
0/172
0/880
0/948

170
301
100
85

27C64
27C128
27C256
27C512

1/749
3/225
1/902
2/411

1/748
0/222
3/901
4/409

2/154
0/45
1/586
2/405

0/0
0/45
0/585
0/284

84
157
27
77

150°C Retention Bake

27C64
27C128
27C256
27C512

1/1074
0/1562
1/1670
2/477

0/1073
0/1562
2/1669
2/475

0/813
0/1562
1/1509
0/397

0/813
0/1562
0/1508
0/397

9
4
29
108

Failure Modes

Operating Life: (5) Metal Migration, (10) Oxide Breakdown, (2) Poly Shorts
HT Reverse Bias: (12) Oxide Breakdown, (8) Charge Gain
Retention Bake: (9) Charge Loss

05110088-8

7-18

Microchip

SECTION 8
PACKAGING
Packaging

Outlines and Dimensions .......................................................................................... 8-

DS00018C

8-i

Microchip

DS00018C

8-ii

Microchip

PACKAGING

Commercial/Industrial Outlines and Parameters
COMMERCIAL AND INDUSTRIAL PARTS
Part Number Suffix Designations:

xxxxxxxxxx -xx

X I XX

xxx

IL
L

ROM Code or Special Requirements

Case
P
J
D
L
W
S
K
SP
SJ
SN
SM
SO
CB
IC
JW

Outline
= Plastic Dual In-Line
= Cerdip (with window if EPROM) - all product except Microcontrollers
= Ceramic Side Brazed Dual In-Line
= PLCC (Plastic Leaded Chip Carrier)
= Die in Wafer Form
= Die in Waffle Pack
= LCC (Ceramic Leadless Chip Carrier, not thermally enhanced)
= Skinny Plastic Dual In-Line
= Skinny Cerdip
= Small Outline Narrow Plastic Gull Wing (150 mil Body)
= Small Outline Medium Plastic Gull Wing (207 mil Body)
= Small Outline Wide Plastic Gull Wing (300 mil Body)
= COB (Chip-On-Board)
= IC Card
= Cerdip, windowed - for Microcontrollers only

Process Temperature
Blank = O°C to +70°C
I
= -40'C to +85°C
H
= -40°C to + 110°C
E
= -40°C to + 125°C

1..---

Speed
Frequency
(EPROM / High
(DSP)
Density EEPROM)
Blank = 20.5 MHz
-35 = 35 ns
-40 = 40 ns
-14
= 14.4 MHz
-45 = 45 ns
-25
= 25.6 MHz
= 32.8 MHz
-55 = 55 ns
-32
-70 = 70 ns
-90 = 90 ns
-10 = 100 ns
-12 = 120 ns
-15 = 150 ns
-17 = 170 ns
-20 = 200 ns
-25 = 250 ns

Crystal Designation
(PIC)
LP = 41ls
RC = 1 I!S

XT = IllS
HS

200 ns

....- - - - - Device Type (Up To 10 Digits)

DS00049A

8-1

Microchip

DS00049A

8-2

PACKAGING

Microchip

TABLE OF CONTENTS
SECTION 1: HERMETIC
A. Ceramic Side Brazed Dual In-line Package ("0" Case Outlines)
Symbol List for Side Brazed Package Parameters ................................................................ 8-1-1
8-Lead, Side Brazed, 300 mil ................................................................................................8-1-2
14-Lead, Side Brazed, 300 mil .............................................................................................. 8-1-3
16-Lead, Side Brazed, 300 mil ..............................................................................................8-1-4
18.. Lead Side Brazed, 300 mil ...............................................................................................8-1-5
20-Lead Side Brazed, 300 mil ............................................................................................... 8-1-6
22-Lead, Side Brazed, 400 mil ..............................................................................................8-1-7
24-Lead, Side Brazed, 600 mil ..............................................................................................8-1-8
24-Lead, Side Brazed, 600 mil, Window ............................................................................... 8-1-9
28-Lead, Side Brazed, 600 mil ..............................................................................................8-1-10
28-Lead, Side Brazed, 600 mil, Window ............................................................................... 8-1-11
40-Lead, Side Brazed, 600 mil ..............................................................................................8-1-12
40-Lead, Side Brazed, 600 mil, Window ............................................................................... 8-1-13
48-Lead, Side Brazed, 600 mil .............................................................................................. 8-1-14

B. Ceramic Cerdip Dualln-iine Package ("J, JW, SJ" Case Outlines)
Symbol List for Cerdip Dual In-Line Package Parameters .................................................... 8-1-15
8-Lead, Cerdip, 300 mil .........................................................................................................8-1-16
16-Lead, Cerdip, 300 mil ....................................................................................................... 8-1-17
18-Lead, Cerdip, 300 mil ....................................................................................................... 8-1-18
18-Lead, Cerdip, 300 mil, Window ........................................................................................ 8-1-19
20-Lead, Cerdip, 300 mil ....................................................................................................... 8-1-20
22-Lead, Cerdip, 400 mil ....................................................................................................... 8-1-21
24-Lead, Cerdip, 300 mil ....................................................................................................... 8·1-22
24·Lead, Cerdip, 600 mil .......................................................................................................8-1-23
24-Lead, Cerdip, 300 mil, Window ........................................................................................ 8-1·24
24-Lead, Cerdip, 600 mil, Window ........................................................................................ 8-1-25
28.Lead, Cerdip, 600 mil ....................................................................................................... 8-1-26
28·Lead, Cerdip, 600 mil, Window ........................................................................................ 8-1-27
40-Lead, Cerdip, 600 mil ....................................................................................................... 8-1-28
40·Lead, Cerdip, 600 mil, Window ........................................................................................8-1-29

C. Ceramic Flatpack
Symbol List for Ceramic Flatpack Package Parameters ....................................................... 8-1·30
28·Lead .................................................................................................................................8-1-31

O. Ceramic Leadless Chip Carrier (Surface Mount Package, "K" Case Outlines)
Symbol List for Ceramic Leadless Chip Carrier Package Parameters .................................. 8-1-32
28·Lead (Square) .................................................................................................................. 8-1-33
28-Lead, Window (Square) ....................................................................................................8-1-34
32·Lead (Rectangle) ..............................................................................................................8-1-35
32·Lead, FRIT (Rectangle) .................................................................................................... 8-1-36
32·Lead, Window (Rectangle) ............................................................................................... 8-1-37
32·Lead, FRIT Window (Rectangle) ...................................................................................... 8-1-38
44-Lead (Square) .................... :............................................................................................. 8-1·39

8-3

DS00049A

PACKAGING

Microchip

TABLE OF CONTENTS (Cont'd)
SECTION 2: PLASTIC
A. Plastic Dual In-Line Package ("P, SP" Case Outlines)
Symbol List for Plastic Dual In-Line Package Parameters .................................................... 8-2-1
8-Lead, 300 mil ......................................................................................................................8-2-2
14-Lead, 300 mil ....................................................................................................................8-2-3
16-Lead, 300 mil ....................................................................................................................8-2-4
18-Lead, 300 mil ....................................................................................................................8-2-5
20-Lead, 300 mil ....................................................................................................................8-2-6
22-Lead, 400 mil ....................................................................................................................8-2-7
24-Lead, 300 mil ....................................................................................................................8-2-8
24-Lead, 600 mil ....................................................................................................................8-2-9
28-Lead, 600 mil ....................................................................................................................8-2-10
40-Lead, 600 mil ....................................................................................................................8-2-11
48-Lead, 600 mil ....................................................................................................................8-2-12

B. Plastic Leaded Chip Carrier (Surface Mount, "L" Case Outlines)
Symbol List for Plastic Leaded Chip Carrier Package Parameters ....................................... 8-2-13
20-Lead (Square) ..................................................................................................................8-2-14
28-Lead (Square) ..................................................................................................................8-2-15
32-Lead (Retangle) ................................................................................................................8-2-16
44-Lead (Square) ..................................................................................................................8-2-17

C. Plastic Small Outline (SOIC) (Surface Mount, "SN, SM, SO" Case Outlines)
Symbol List for Plastic Small Outline Package Parameters .................................................. 8-2-18
8-Lead, 150 mil (Body) ..........................................................................................................8-2-19
8-Lead, 200 mil (Body) .........................................................................................................:8-2-20
14-Lead, 150 mil (Body) ........................................................................................................8-2-21
14-Lead, 300 mil (Body) ........................................................................................................8-2-22
16-Lead, 150 mil (Body) ........................................................................................................8-2-23
16-Lead, 300 mil (Body) ........................................................................................................8-2-24
18-Lead, 300 mil (Body) ........................................................................................................8-2-25
20-Lead, 300 mil (Body) ........................................................................................................8-2-26
24-Lead, 300 mil (Body) ........................................................................................................8-2-27
28-Lead, 300 mil (Body) ........................................................................................................8-2-28

DS00049A

8-4

1990 Microchip Technoiogy Inc.

Microchip

Packaging Diagrams and Parameters
Ceramic Side Brazed Dual In-line Family
Symbol List for Ceramic Side Brazed Dual In-line Package Parameters
Symbol

Description of Parameters

Angular spacing between min and max lead positions measured at the guage plane

Distance between seating plane to highest point of body (lid)

Distance between seating plane and base plane

Distance from base plane to highest point of body (lid)

Base body thickness

Width of terminal leads

Width of terminal lead shoulder which locate seating plane (standoff geometry optional)

Thickness of terminal leads

Largest overall package parameter of length

Body length parameter - end lead center to end lead center

Largest overall package width parameter outside of lead

Body width parameters not including leads

Linear spacing of true minimum lead position center line to center line

Linear spacing between true lead position outside of lead to outside of lead

Linear spacing between center lines of body standoffs (terminal leads)

Distance from seating plane to end of lead

Total number of potentially useable lead positions

Distance from true position center line of No.1 lead to the extremity of the body

Distance from other end lead edge positions to the extremity of the body

Notes:
1. Controlling parameter: inches.

2. Parameter "e," ("e") is non-cumulative.

3. Seating plane (standoff) is defined by board hole size.
4. Parameter "B," is nominal.

8-1-1

DS00049A

~®

Microchip

Packaging Diagrams and Parameters
Package Type: 8-Lead Ceramic Side Brazed Dual In-line (.300 mil)

OIII
m

PinNo.1_
Indicator
Area

a_I
/I

eA
eB---~

s-t° Sl_·I+- . 1 J j

Base

Plane"-Seating -

Plane

_ I_

=!Tm~

II I I I I
·.I:j~~"
I'=-f A, k
01-1
L

Package Group: Ceramic Side Brazed Dual In·line (CER)
Millimeters

DS00049A

Symbol

Min

Max

3.302

A1
A2.

Inches
Notes

Min

Max

10°

3.937

0.130

0.155

0.635

1.143

0.025

0.045

2.032

2.794

0.080

0.110

1.778

2.413

0.070

0.095

0.4064

0.508

0.016

0.020

Notes

1.3716

Typical

0.054

Typical

0.2286

0.3048

Typical

0.009

0.012

Typical

13.0048

13.4112

0.512

0.528

7.4168

7.8232

0.292

0.308

7.5692

8.2296

0.298

0.324

7.112

7.620

0.280

0.300

2.540

Typical

0.100

Typical

6'\

7.620

Reference

0.300

Reference

7.620

9.652

0.300

0.380

3.302

3.810

0.130

.150

Reference

2.540

3.048

0.100

0.120

0.127

.005

8-1-2

Reference

Microchip

Packaging Diagrams and Parameters
Package Type: 14-Lead Ceramic Side Brazed Dual In-line (.300 mil)
N

11
E1

Pin No. 1 _
Indicator
Area

* I

"'!>r-Tr-"'--rr-"TT"*-rI~
I

I~"

eA
eB----tl~

::-::::=o-=-:::.~

I_~

Seating
Plane

I~I
11=r
A1

A3 A A2

Package Group: Ceramic Side Brazed Dual In-line (CER)
Inches

Millimeters

1-.

Symbol

Min

Max

0°

Notes

Min

Max

10°

0°

10°

3.302

4.064

0.130

0.160

0.635

1.143

0.025

0.045

2.032

2.794

0.080

0.110

1.778

2.413

0.070

0.095

0.Q16

0.020

Notes

0.4064

0.508

1.270

Typical

0.050

Typical

0.2032

0.3048

Typical

0.008

0.012

Typical

18.796

19.2278

0.740

0.757

15.0368

15.4432

0.592

0.608
0.330

Reference

7.620

8.382

0.300

7.0612

7.5692

0.278

0.298

2.3622

2.7432

Typical

0.093

0.108

Typical

7.366

7.874

Reference

0.290

0.310

Reference

7.620

9.652

0.300

0.380

3.175

4.191

0.125

0.165

2.4892

0.098

0.127

0.005

8-1-3

DS00049A

Microchip

Packaging Diagrams and Parameters
Package Type: 16-Lead Ceramic Side Brazed Dual In-line (.300 mil)
N

Seating
Plane

Package Group: Ceramic Side Brazed Dual In·line (CER)
Inches

Millimeters

DS00049A

Symbol

Min

Max

0°

A
A1
A2
A3
B

Notes

Min

Max

10°

0°

10°

3.302

4.064

0.130

0.160

0.635

1.143

0.025

0.045

2.032

2.794

0.080

0.110

1.778

2.413

0.070

0.095

0.4064

0.508

0.016

0.020

1.3716

Typical

0.054

Typical

0.2286

0.3048

Typical

0.009

0.012

Typical

D
D1
E
E1
e1
eA
es

19.812

20.574

0.780

0.810

17.653

17.907

0.695

0.705

7.620

8.382

0.300

0.330

7.1628

7.4676

0.282

0.294

2.413

2.667

Typical

0.095

0.105

Typical

7.366

7.874

Reference

0.290

0.310

Reference

7.620

9.652

0.300

0.380

3.175

4.191

0.125

0.165

S
S1

2.032

0.080

0.127

0.005

Reference

8-1-4

Notes

Reference

Microchip

Packaging Diagrams and Parameters
Package Type: 18-Lead Ceramic Side Brazed Dual In-line (.300 mil)
N

a_I:
/I

~::~

Pin No. 1 _
Indicator
"'I"''l't-TT"""TT""TT""TT"'"T"T"-rr''''''''''''
Area

::===D==::'~
Seating
Plane

-:-ffi
=r
e1

I...

A1 A3 A A2.

-I

Package Group: Ceramic Side Brazed Dual In-line (CER)
Inches

Millimeters
Symbol

Min

Max

0°

A
A1
A2

Min

Max

10°

0°

10°

3.302

4.064

0.130

0.160

0.635

1.143

0.025

0.045

2.032

2.794

0.080

0.110

Notes

1.778

2.413

0.070

0.095

0.4064

0.508

0.016

0.020

1.3716

Typical

0.054

Typical

0.2286

0.3048

Typical

0.009

0.012

Typical

22.352

23.114

0.880

0.910

20.193

20.447

0.795

0.805

0.300

0.330

Reference

7.620

8.382

7.0612

7.5692

0.278

0.298

2.413

2.667

Typical

0.095

0.105

Typical

7.366

7.874

Reference

0.290

0.310

Reference

7.620

9.652

0.300

0.380

3.175

4.191

0.125

0.165

2.4892

0.098

0.127

0.005

8-1-5

DS00049A

Microchip

Packaging Diagrams and Parameters
Package Type: 20-Lead Ceramic Side Brazed Dual In-line (.300 mil)
N

f'.. -

Area

eA - - J

_"I

eB~

Seating
Plane

1+-------D1------.. 1

Package Group: Ceramic Side Brazed Dual In-line (CER)
Inches

Millimeters

DS00049A

Symbol

Min

Max

Notes

Min

Max

Notes

0°

10°

0°

10°

0.508

0.200

0.381

1.778

0.015

0.070

3.81

4.445

0.150

0.175

0.355

0.584

0.014

0.023

1.27

Typical

0.050

Typical

0.008

0.015

Typical

0.940

0.980

0.900

0.300

0.330

0.220

0.310

0.100

Typical
Reference

0.203

0.381

23.876

24.892

22.86

7.62

8.382

5.588

7.874

2.54

Reference

Typical

7.62

0.300

7.62

10.16

0.300

00400

3.175

3.810

0.125

0.150

0.508

1.397

0.020

0.055

0.381

1.270

0.015

0.050

Reference

8-1-6

Reference

Microchip

Packaging Diagrams and Parameters
Package Type: 22-Lead Ceramic Side Brazed Dual In-line (.400 mil)

DO
N

Pin No.1
Indicator ----Area

8~:r--

TI
E1

a~1I

.1
~

I....
"

eB---~

D~~.~
I

=r-hru

e1 I ...

A1 A3 A A2

~------D1 -------~~~I

Package Group: Ceramic Side Brazed Dualln·line (CER)
Inches

Millimeters
Min

Max

10°

0°

10°

Symbol

Min

Max

0°

A
A1
A2
A3
B
B1

Notes

2.667

4.064

0.105

0.160

0.7112

1.2192

0.028

0.048

2.032

3.302

0.080

0.130

1.778

2.921

0.070

0.115

0.4318

0.5842

0.017

0.023

Notes

1.016

Typical

0.040

Typical

0.2286

0.3048

Typical

0.009

0.012

Typical

D
D1
E
E1
e1
eA
eB

27.1526

27.8638

1.069

1.091

25.2968

25.6032

Reference

0.992

1.008

0.400

0.430

Reference

10.160

10.922

9.7282

9.9822

0.383

0.393

2.3368

2.7432

Typical

0.092

0.108

Typical

9.906

10.414

Reference

0.390

0.410

Reference

10.160

12.192

0.400

0.480
0.165

3;175

4.191

0.125

8
81

2.032

0.080

0.127

0.005

8-1-7

DS00049A

Microchip

Packaging Diagrams and Parameters
Package Type: 24-Lead Ceramic Side Brazed Dual In-line (.600 mil)

DO..ll
N

TI
E1

Pin No. 1
Indicator ---Area

a--II

[~..

eA
e B - -____

D~~.9rW

S~:t=

trm

I"=f"
I

A3 A A2

~------D1 ------------.~~I

Symbol

DS00049A

Package Group: Ceramic Side Brazed Dual In-line (CER)
Inches
Millimeters
Max
Min
Max
Notes
Min

0°

10°

0°

10°

3.048

4.445

0.120

0.175

Notes

1.016

1.524

0.040

0.060

2.032

2.921

0.080

0.115

1.778

2.540

0.070

0.100

0.4064

0.508

0.016

0.020

1.270

Typical

0.050

Typical

0.2286

0.3048

Typical

0.009

0.012

Typical

30.1752

30.7848

1.188

1.212

27.7368

28.1432

14.986

16.002

14.7828

14.9352

2.3368

2.7432

Typical

14.986

15.748

Reference

14.986

3.302

S
S1

1.092

1.108

0.590

0.630

0.582

0.588

0.092

0.108

Typical

0.590

0.620

Reference

16.256

0.590

0.640

4.064

0.130

0.160

2.540

0.100

0.127

0.005

Reference

8-1-8

Reference

Microchip

Packaging Diagrams and Parameters
Package Type: 24-Lead Ceramic Side Brazed Dual In-line with Window (.600 mil)
N

Package Group: Ceramic Side Brazed Dual In-line (CER)
Millimeters
Min

Max

a
A

Symbol

Inches
Notes

Notes

Min

Max

0°

10°

0°

10°

3.048

4.445

0.120

0.175

1.016

1.524

0.040

0.060

2.032

2.921

0.080

0.115

1.778

2.540

0.070

0.100

0.4064

0.508

0.016

0.020

1.270

Typical

0.050

Typical

0.2286

0.3048

Typical

0.009

0.012

Typical

1.188

1.212

Reference

1.092

1.108

0.590

0.630

0.582

0.588

30.1752

30.7848

27.7368

28.1432

14.986

16.002

14.7828

14.9352

2.3368

2.7432

Typical

0.092

0.108

Typical

14.986

15.748

Reference

0.590

0.620

Reference

14.986

16.256

0.590

0.640
0.160

3.302

4.064

0.130

2.540

0.100

5'1

0.127

0.005

8-1-9

Reference

DS00049A

Microchip

Packaging Diagrams and Parameters
Package Type: 28-Lead Ceramic Side Brazed Dual In-line (.600 mil)

a--II
II

f~ ~
Area

eB----I--l

~=-=~D;::==:;.~
e1

=r±ffif

I
I ..

A3 A A2

------I~~I

Package Group: Ceramic Side Brazed Dualln·line (eER)
Millimeters

DS00049A

Symbol

Min

Max

0°

3.048

Inches
Notes

Min

Max

10°

0°

10°

4.064

0.120

0.160

1.016

1.524

0.040

0.060

2.032

2.921

0.080

0.115

1.778

2.540

0.070

0.100

0.4572

0.508

0.018

0.020

Notes

1.270

Typical

0.050

Typical

0.2286

0.3048

Typical

0.009

0.012

Typical

35.2044

35.9156

1.386

1.414

32.8168

33.2232

14.986

16.002

14.7828

15.1892

2.4892

2.5908

Typical

14.986

15.494

Reference

1.308
0.630

0.582

0.598

0.098

0.102

Typical

0.590

0.610

Reference

14.986

16.256

0.590

0.640

3.302

4.064

0.130

0.160

2.540

0.100

0.127

0.005

8-1-10

Reference

1.292
0.590

Microchip

Packaging Diagrams and Parameters
Package Type: 28-Lead Ceramic Side Brazed Dual In-line with Window (.600 mil)
N

Package Group: Ceramic Side Brazed Dual In-line (CER)
Inches

Millimeters

Max

10°

0°

10°

4.064

0.120

0.160
0.060

Min

Max

0°

A
A1
A2
A3
B
B1

3.048

D
D1
E
E1
e1
eA
eB

Min

Symbol

Notes

1.016

1.524

0.040

2.032

2.921

0.080

0.115

1.778

2.540

0.070

0.100

0.4572

0.508

0.018

0.020

1.270

Typical

0.050

Typical

0.2286

0.3048

Typical

0.009

0.012

Typical

35.2044

35.9156

1.386

1.414

32.8168

33.2232

1.292

1.308

Reference

14.986

16.002

0.590

0.630

14.7828

15.1892

0.582

0.598

2.4892

2.5908

Typical

0.098

0.102

Typical

14.986

15.494

Reference

0.590

0.610

Reference

14.986

16.256

0.590

0.640

4.064

0.130

0.160

3.302

8
81

2.540

0.100

0.127

0.005

1990 Microchip Technology Inc.

8-1-11

DS00049A

Microchip

Packaging Diagrams and Parameters
Package Type: 40-Lead Ceramic Side Brazed Dual In-line (.600 mil)

DO..llTI
N

Pin No. 1
Indicator - Area

a--II

s--i:r=

i~"

eA
eB----t

o~~~~
I

Hof------- 01

±Tm

=-r-

e1 I ..

A3 A A2

- - - - - - - l...~1

Package Group: Ceramic Side Brazed Dual In-line (CER)
Inches

Millimeters
Symbol

Min

Max

0°

Min

Max

10°

0°

10°

3.048

4.445

0.120

0.175

1.016

1.524

0.040

0.060

2.032

2.921

0.080

0.115

1.829

2.235

.072

.088

0.4064

0.508

0.016

0.020

Notes

1.270

Typical

0.050

Typical

0.2286

0.3048

Typical

0.009

0.012

Typical

50.546

51.308

1.990

2.020

48.056

48.463

15.240

16.256

DS00049A

Notes

Reference

1.892

1.908

0.600

0.640

Reference

14.478

15.748

0.570

0.620

2.3368

2.7432

Typical

0.092

0.108

Typical

15.240

Reference

0.600

Reference

14.986

16.256

0.590

0.640

3.302

4.064

0.130

0.160

2.4892

0.098

0.127

0.005

8-1-12

1990 Microchip Technology Inc.

Microchip

Packaging Diagrams and Parameters
Package Type: 40-Lead Ceramic Side Brazed Dual In-line with Window (.600 mil)
N

I
a~1

c--

~::~

Area

===~D;;:==::.~
e1

I
I..

trm

A1 A3 A A2

~----------D1------------~~~1

Package Group: Ceramic Side Brazed Dual In·line (CER)
Millimeters
Symbol

Min

Max

0°

Inches
Notes

Min

Max

10°

0°

10°

3.048

4.445

0.120

0.175

1.016

1.524

0.040

0.060

2.032

2.921

0.080

0.115

1.829

2.235

.072

.088

0.016

0.020

Notes

0.4064

0.508

1.270

Typical

0.050

Typical

0.2286

0.3048

Typical

0.009

0.012

Typical

50.546

51.308

1.990

2.020

48.056

48.463

1.892

1.908

15.240

16.256

0.600

0.640

0.570

0.620

0.092

0.108

Typical
Reference

Reference

14.478

15.748

2.3368

2.7432

Typical

15.240

Reference

0.600

14.986

16.256

0.590

0.640
0.160

3.302

4.064

0.130

2.4892

0.098

0.127

0.005

8-1-13

Reference

DS00049A

~®

Microchip

Packaging Diagrams and Parameters
Package Type: 48-Lead Ceramic Side Brazed Dual In-line (.600 mil)

a----II
/I

f~"

Area

eA
es--_~

o~~~~
I
e1 I
~-----

±Tm

--==r

Ai A3 A A2

- - - - - - - I...~I

Package Group: Ceramic Side Brazed Dual In-line (CER)
Inches

Millimeters

DS00049A

Symbol

Min

Max

0°

10°

Notes

Min

Max

0°

10°

3.048

4.445

0.120

0.175

1.016

1.524

0.040

0.060

2.032

2.921

0.080

0.115

1.829

2.235

0.072

0.088

0.Q16

0.020

Notes

0.4064

0.508

1.270

Typical

0.050

Typical

0.2286

0.3048

Typical

0.009

0.012

Typical

60.3504

61.5696

2.376

2.424

58.2168

58.6232

2.292

2.308

15.240

16.256

0.600

0.640

14.478

15.748

0.570

0.620

2.3368

2.7432

Typical

0.092

0.108

Typical

15.240

15.290

Reference

0.600

Reference

14.986

16.256

0.590

0.640
0.160

Reference

3.302

4.064

0.130

2.4892

0.100

0.127

0.005

8-1-14

Reference

Microchip

Packaging Diagrams and Parameters
Ceramic Cerdip Dual In-line Family
Symbol List for Ceramic Cerdip Dual In-line Package Parameters
Symbol

Description of Parameters

Angular spacing between min and max lead positions measured at the guage plane

Distance between seating plane to highest point of body (lid)

Distance between seating plane and base plane

Distance from base plane to highest point of body (lid)

Base body thickness

Width of terminal leads

Width of terminal lead shoulder which locate seating plane (standoff geometry optional)

Thickness of terminal leads

Largest overall package parameter of length

Body length parameter - end lead center to end lead center

Largest overall package width parameter outside of lead

Body width parameters not including leads

Linear spacing of true minimum lead position center line to center line

Linear spacing between true lead position outside of lead to outside of lead

Linear spacinQ between center lines of body standoffs (terminal leads)

Distance from seating plane to end of lead

Total number of potentially useable lead positions

Distance from true position center line of No.1 lead to the extremity of the body

Distance from other end lead edge positions to the extremity of the body

Notes:
1. Controlling parameter: inches.
2. Parameter "e," ("e") is non-cumulative.
3. Seating plane (standoff) is defined by board hole size.
4. Parameter "B," is nominal.

8-1-15

DS00049A

Microchip

Packaging Diagrams and Parameters
Package Type: 8-Lead Cerdip Dual In-line (.300 mil)

O
N

iTI
I

Pin No. 1__
Indicator

a~: !-,:-----..,,,...--,-I

J I

Area

Plane"-Seating _ _
Plane

Symbol

a
A
A1
A2

DS00049A

I _ _ _ 1_

/1111

iTn

S - r i = D Sl---:l_
Base

:I:~~"
I.=-f A,
D1-1

'" A

Package Group: Ceramic Cerdl~ Dual In-line (COP)
Millimeters
Inches
Max
Min
Notes
Min
Max

0°

10°

0°

10°

5.080

0.200

0.381

1.524

0.015

0.060

Notes

4.445

0.150

0.175

0.356

0.584

0.014

0.023

1.270

1.651

Typical

0.050

0.065

Typical

0.008

0.015

Typical

0.370

0.405

0.300

0.325

0.220

0.310

0.100

Typical
Reference

A3
B

3.810

Ref. A3

0.203

0.381

9.398

10.287

D1
E

7.620

8.255

E1
e1
eA

5.588

7.874

7.366

8.128

0.290

0.320

7.620

10.160

0.300

0.400

3.175

3.810

0.125

0.150

S
Sl

5.08

1.397

0.020

0.055

0.381

1.270

0.Q15

0.050

2.540

Reference

Typical
Referemce

8-1-16

Reference

Microchip

Packaging Diagrams and Parameters
Package Type: 16-Lead Ceramic Cerdip Dual In-line (.300 mil)
N

ITT
E1

Pin No. 1 _
Indicator
Area

11-------1

ex-"

~:~
JJ

"'~TT"TT""TT""TT"TT""TT"-r~

D--J~~
i-t-----------h
Seating
Plane

;

-:-±Trr
-- =r
e1

~-----

I...

A3 A

-----I~~I

Package Group: Ceramic Cerdip Dual In-line (COP)
Inches

Millimeters
Min

Max

10°

0°

10°

4.191

5.080

0.165

0.200

0.381

1.524

0.015

0.060

3.810

4.445

Symbol

Min

Max

0°

Notes

Ref. A3

0.150

0.175

Notes

Ref. A3

0.356

0.584

0.014

0.023

1.270

1.651

Typical

0.050

0.065

Typical

0.203

0.381

Typical

0.008

0.015

Typical

19.050

20.320

0.750

0.800

17.780

0.700

7.493

8.255

0.295

0.325

5.588

7.874

0.220

0.310

2.540

Typical

0.100

Typical

7.366

8.128

Reference

0.290

0.320

Reference

7.62

10.160

0.300

0.400

3.175

3.810

0.125

0.150

5.08

1.397

0.020

0.055

0.381

1.270

0.D15

0.050

Reference

8-1-17

Reference

DS00049A

Microchip

Packaging Diagrams and Parameters
Package Type: 18-Lead Ceramic Cerdip Dual In-line (.300 mil)
N

iTT
E1

ll------I

a~1

..,...,.~ J

Pin No. 1 _ ...Ih-,..,....,......TT""TT"..,............
Indicator
Area

D-_.~

i-+--------+;_I

-- e

=sTTT
=r

I
I..

A1 A3 A

~------D1------·~1

Package Group: Ceramic Cerdip Dual In-line (COP)
Min

0°

5.080

0.381

1.524

Notes

10°

3.180

4.445

Min

0°
0.015
Ref. A3

Inches
Max

Notes

10°
0.200
0.070

0.150

0.175

Ref. A3

0.356

0.584

0.014

0.023

1.270

1.651

Typical

0.050

0.065

Typical

0.203

0.381

Typical

0.008

0.015

Typical

0.880

0.930

0.800

0.300

0.330

22.352

23.622

20.320

7.620

8.382

5.588

7.874

0.220

0.310

2.540

Typical

0.100

Typical

7.366

8.128

Reference

0.290

0.320

Reference

7.62

10.160

0.300

0.400

3.175

3.810

0.125

0.150

DS00049A

Millimeters
Max

Symbol

Reference

5.08

1.397

0.020

0.055

0.381

1.270

0.015

0.050

8-1-18

Reference

Microchip

Packaging Diagrams and Parameters
Package Type: 18-Lead Cerdip Dual In-line with Window (.300 mil)
N

iTT
E1

PinNo.l~ .......
Indicator

ll---...,,---U'

a---."

IJ I

-I

...,.-JL:::h.L

TT""TT""TT""TT"""TT""TT".......

Area

Seating
Plane

A1 A3 A

~-----D1-----~

Package Group: Ceramic Cerdip Dual In-line (COP)
Inches

Millimeters
Symbol

Min

Max

0°

10°

Notes

Min

Max

0°

10°

5.080

0.200

0.381

1.524

0.015

0.070

3.810

4.699

0.150

0.185

3.180

4.445

0.150

0.175

Notes

0.356

0.584

0.014

0.023

1.270

1.651

Typical

0.050

0.065

Typical

0.203

0.381

Typical

0.008

0.Q15

Typical

22.352

23.622

0.880

0.930

20.320

0.800

7.620

8.382

0.300

0.330

5.588

7.874

0.220

0.310

2.540

Typical

0.100

Typical

7.366

8.128

Reference

0.290

0.320

Reference

7.62

10.160

0.300

0.400
0.150

Reference

3.175

3.810

0.125

5.08

1.397

0.020

0.055

0.381

1.270

0.015

0.050

8-1-19

Reference

DS00049A

Microchip

Packaging Diagrams and Parameters
Package Type: 20-Lead Ceramic Dual In-line (.300 mil)

Symbol

DS00049A

Package Group: Ceramic Cerdip Dual In-line (COP)
Millimeters
Inches
Max
Notes
Min
Max
Min

0°

10°

0°

10°

.508

0.381

0.200

1.778

0.015

0.070

3.81

4.445

Ref. A3

0.150

0.175

Notes

Ref. A3

0.355

0.584

0.014

0.023

1.27 typ

Typical

0.050 typ

0.050typ

Typical

0.203

0.381

Typical

0.008

0.015

Typical

0.940

0.980

0.900

0.300

0.330

23.876

24.892

22.86

7.62

8.382

5.588

7.874

0.220

0.310

2.54

Typical

0.100

Typical

7.62

Reference

0.300

Reference

7.62

10.16

0.300

0.400
0.150

Reference

3.175

3.81

0.125

0.508

1.397

0.020

0.055

0.381

1.27

0.015

0.050

8-1-20

Reference

Microchip

Packaging Diagrams and Parameters
Package Type: 22-Lead Ceramic Cerdip Dual In-line (.400 mil)
N

r\\lTI

a-."

ll----.,.....--U

~~i~a~~~---~~~

~::-----I~

Area

8 ~I-I"I-------- 0

i-f------"""'" .--------+-1 --t---J"----l~

Ht------ 01 - - - - -__~

Symbol

Package Group: Ceramic Cerdip Dualln·line (COP)
Millimeters
Inches
Max
Notes
Min
Max
Min
0°

10°

0°

10°

Notes

5.715

0.225

0.381

1.524

0.015

0.070

3.180

4.445

0.356

0.584

0.014

0.023

1.270

1.651

Typical

0.050

0.065

Typical

0.2032

0.381

Typical

0.008

0.015

Typical

26.670

27.940

1.050

1.100

25.400

1.000

10.160

10.922

0.400

0.430

8.890

10.414

0.350

0.410

2.540

Typical

0.100

Typical

9.906

10.668

Reference

0.390

0.420

Reference

10.160

12.700

0.400

0.500

3.175

3.810

0.125

0.150

1.270

0.050

0.127

1.270

0.005

0.050

Ref. A3

Reference

8-1-21

0.150

0.175

Ref. A3

Reference

DSO0049A

Microchip

Packaging Diagrams and Parameters
Package Type: 24-Lead Ceramic Cerdip Dual In-line (.300 mil)
N

:;~;-Dull

ll-------i

0;~1

Area

S ~I"""I-------- 0

...--1----------. .---------__r, __

+-"':""'...l--

!*------- 01 ------~

Symbol
0;

DS00049A

Package Group: Ceramic Cerdil Dual In-line (COP)
Inches
Millimeters
Notes
Min
Max
Max
Min
O·
O·
10·
10·

Notes

5.715

0.225

0.381

1.905

0.015

0.075

3.810

4.445

0.150

0.356

0.584

0.014

0.023

1.270

1.651

Typical

0.050

0.065

Typical

0.203

0.381

Typical

0.008

0.015

Typical

31.115

32.385

1.225

1.275

27.940

Ref. A3

Reference

Ref. A3

0.175

Reference

1.100

0.300

0.330

0.220

0.310

0.100

Typical

0.290

0.320

Reference

11.43

0.300

0.450

3.810

0.125

0.150

7.620

8.382

5.588

7.894

2.540

Typical

eA
es

7.366

8.128

Reference

7.62

3.175

24
0.090
0.070

1.016

2.286

0.040

0.381

1.778

0.015

8-1-22

Microchip

Packaging Diagrams and Parameters
Package Type: 24-Lead Ceramic Cerdip Dual In-line with Window (.300 mil)
N
ll---~-_i

IX-'"

11
Area

~------D1 -----~~

Package Group: Ceramic Cerdip Dual In-line (COP)
Millimeters
Symbol

Min

Max

0°

10°

Inches
Notes

Min

Max

0°

10°

Notes

5.715

0.381

1.905

0.015

0.075

3.810

4.699

0.150

0.185

3.810

4.445

0.150

0.175

0.356

0.584

0.014

0.023

1.270

1.651

Typical

0.050

0.065

Typical

0.203

0.381

Typical

0.008

0.015

Typical

D
D1
E
E1
e1
eA
eB

31.115

32.385

1.225

1.275

27.940

7.62

8.382

5.588

7.874

A
A1
A2
A3
8
81

Reference

0.225

1.100

0.300

0.330

0.220

0.310

0.100

Typical
Reference

2.540

Typical

7.366

8.128

Reference

0.290

0.320

7.62

11.43

0.300

0.450
0.150

3.175

3.810

0.125

S
S1

1.016

2.286

0.040

0.090

0.381

1.778

0.015

0.070

8-1-23

Reference

DS00049A

Microchip

Packaging Diagrams and Parameters
Package Type: 24-Lead Ceramic Cerdip Dual In-line (.600 mil)

OOTT
N

Pin No.1
Indicator Area

-=:!:::.l..

5 ~I-I~I-------- 0
ri------"""\ t"-------t-, --t-L--l-

\1It------- 01

------~

Package Group: Ceramic Cerdi Dual In-line (COP)
Millimeters
Symbol

Min

Max

0°

10°

0.381

A
A1
A2
A3
6
61

DSOOO49A

Inches
Min

Max

0°

10°

5.715

0.225

1.524

0.015

0.075

Notes

Ref. A3

0.150

Notes

Ref. A3

3.810

4.445

0.356

0.584

0.014

0.023

1.270

1.651

Typical

0.050

0.065

Typical

0.203

0.381

Typical

0.008

0.015

Typical

0
01
E
E1
e1

31.115

32.385

1.225

1.275

27.940

1.100

15.240

15.875

0.600

0.625

12.954

15.240

0.510

0.600

2.540

Typical

0.100

Typical

14.986

15.748

Reference

0.590

0.620

Reference

15.240

18.034

0.600

0.710
0.150

Reference

0.175

3.175

3.810

0.125

5
51

1.016

2.286

0.040

0.090

0.127

1.778

0.015

0.070

8-1-24

Reference

Microchip

Packaging Diagrams and Parameters
Package Type: 24-Lead Ceramic Cerdip Dual In-line with Window (.600 mil)
N
I

a-II

1----::---1

I·

Area

~-----------D1 ---------~~

Package Group: Ceramic Cerdi) Oualln-line (COP)
Inches

Millimeters
Symbol

Min

Max

0°

10°

A
A1
A2
A3
B
B1

Notes

Min

Max

0°

10°

0.225

5.715

0.381

1.524

0.015

0.075

3.810

4.699

0.150

0.185

3.810

4.445

0.150

0.175

0.356

0.584

0.014

0.023

Notes

1.270

1.651

Typical

0.050

0.065

Typical

0.203

0.381

Typical

0.008

0.015

Typical

D
D1
E
E1
e1
eA
es

31.115

32.385

1.225

1.275

27.940

1.100

15.240

15.875

0.600

0.625

12.954

15.240

0.510

0.600

2.540

Typical

0.100

Typical

14.986

15.748

Reference

0.590

0.620

Reference

15.240

18.034

0.600

0.710

3.175

3.810

0.125

0.150

S
S1

1.016

2.286

0.040

0.090

0.127

1.778

0.015

0.070

Reference

8-1-25

Reference

DS00049A

Microchip

Packaging Diagrams and Parameters
Package Type: 28-Lead Ceramic Cerdip Dual In-line (.600 mil)
N

DuITM

P;oN01
Indicator Area

II-----~

a-II
/I

8 ~......- - - - - - - - D

.--------h

r-t------""""\

~------

--t--L...-L-

------~

Package Group: Ceramic Cerdip Dual In-line (COP)
Millimeters

DS00049A

Symbol

Min

Max

a
A
A1

0°

10°

5.461

0.381

1.524

Inches
Notes

Min

Max

0°

10°

0.015
Ref. A3

Notes

0.215
0.060
Ref. A3

A3
8
81

3.810

4.445

0.356

0.584

0.014

0.023

1.270

1.651

Typical

0.050

0.065

Typical

0.203

0.381

Typical

0.008

0.015

Typical

D
D1

36.195

1.425

1.475

33.020

15.240

15875

12.954

15.240

e1
eA
eB

2.540

Typical

14.986

8.128

Reference

0.590

15.240

18.034

0.600

0.710

3.175

3.810

0.125

0.150

Reference

0.175

1.300
0.625

0.510

0.600

0.100

Typical

0.620

Reference

1.016

2.286

0.040

0.090

0.381

1.778

0.015

0.070

8-1-26

Reference

1.300
0.600

Microchip

Packaging Diagrams and Parameters
Package Type: 28-Lead Ceramic Cerdip Dual In-line with Window (.600 mil)
N
I

a-II

1----:::---1

II
/I

Area

~------

D1 -----~~

Package Group: Ceramic CerdiJ Oualln-line (COP)
Millimeters
Symbol

a
A
A1

Min

Max

Inches
Notes

Min

Max

0°

10°

Notes

0°

10°

5.461

0.381

1.524

0.015

0.060

A2
A3
B
B1

3.810

4.699

0.150

0.185

3.810

4.445

0.150

0.175

0.356

0.584

0.014

0.023

1.270

1.651

Typical

0.050

0.065

Typical

0.203

0.381

Typical

0.008

0.015

Typical

1.425

1.475

D
D1
E
E1
e1
eA
es

36.195

33.020

15.240

15875

12.954

15.240

2.540

Typical

14.986

8.128

Reference

15.240

0.215

1.300
0.625

0.510

0.600

0.100

Typical

0.590

0.620

Reference

18.034

0.600

0.710
0.150

3.175

3.810

0.125

8
81

1.016

2.286

0.040

0.090

0.381

1.778

0.015

0.070

Reference

1.300
0.600

Reference

I
8-1-27

DS00049A

Microchip

Packaging Diagrams and Parameters
Package Type: 40-Lead Ceramic Cerdip Dual In-line (.600 mil)
N

~TI
D
~~i~~~:~~ ld

ex~1

1----:::----1

~::----J

Area

~"'''I-------- 0
rl------~

r - - - - - - - i - " 1 --1-''--'-

~----------01------------~

Package Group: Ceramic Cerdip Dualln·line (COP)
Inches

Millimeters
Symbol

Min

Max

0°

A
A1
A2
A3
B
B1
C

0
01
E
E1
e1
eA
eB
L

DSOOO49A

Notes

Min

Max

10°

0°

10°

4.318

5.715

0.170

0.225

0.381

1.778

0.015

0.070

3.810

4.445

0.356

0.584

0.014

0.023

1.270

1.651

Typical

0.050

0.065

Typical

0.203

0.381

Typical

0.008

0.015

Typical

51.435

52.705

2.025

2.075

48.260

1.900

1.900
0.625

Ref. A3

Reference

0.150

0.175

Ref. A3

Reference

15.240

15875

0.600

12.954

15.240

0.510

0.600

2.540

Typical

0.100

Typical

14.986

16.002

Reference

0.590

0.630

Reference

15.240

18.034

0.600

0.710

3.175

3.810

0.125

0.150

S
S1

1.016

2.286

0.040

0.090

0.381

1.778

0.015

0.070

8+28

Microchip

Packaging Diagrams and Parameters
Package Type: 40-Lead Ceramic Cerdip Dual In-line with Window (.600 mil)
N

ll---....,,---I

0.-11
II

I_
Area

~------

----------~~

Package Group: Ceramic Cerdi

Dual In-line (COP)

Millimeters

Inches
Max

0°

10°

Min

Max

0°

10°

4.318

5.715

0.170

0.225

A1
A2
A3
B
B1

0.381

1.778

0.Q15

0.070

3.810

4.699

0.150

0.185

3.810

4.445

0.150

0.175

0.356

0.584

0.014

0.023

D
D1
E
E1
e1

Notes

Min

Symbol

Ref. A3

Notes

Ref. A3

1.270

1.651

Typical

0.050

0.065

Typical

0.203

0.381

Typical

0.008

0.015

Typical

2.025

2.075

51.435

52.705

48.260

1.900

15.240

15875

0.600

0.625

12.954

15.240

0.510

0.600

Reference

2.540

Typical

0.100

Typical

14.986

16.002

Reference

0.590

0.630

Reference

15.240

18.034

0.600

0.710

3.175

3.810

0.125

0.150

8
81

1.016

2.286

0.040

0.090

0.381

1.778

0.015

0.070

8-1-29

DS00049A

Microchip

Packaging Diagrams and Dimensions
Ceramic Flatpack Family
Symbol List for Ceramic Flatpack Package Parameters
Symbol

Description of Parameters
Distance between seating plane to highest pOint of body (lid)

Width of terminal leads

Thickness of terminal leads

Largest overall package parameter of length

Body length parameter - end lead center to end lead center

E
E2. E3

Largest overall package width parameter outside of lead
Body width parameters not including leads

Linear spacing between center lines of body standoffs (terminal leads)

Other package width parameter

Distance from package body to end of lead

Total number of potentially useable lead positions

Distance between seating plane and lead

Distance from true position center line of No.1 lead to the extremity of the body

Distance from other end lead edge positions to the extremity of the body

Notes:
1. Controlling parameter: inches.
2. Parameter "el" ("e") is non-cumulative.
3. Seating plane (standoff) is defined by board hole size.
4. Parameters "B" and "C" are nominal.

DS00049A

8-1-30

Microchip

Packaging Diagrams and Dimensions
Package Type: 28-Lead Ceramic Flatpack

Terminal N

PinNo.1~

Indicator

1
1

1 1

!+- 81
I--

1 1

-Ier- r-

---1 B

--I

Package Group: Ceramic Flatpack (CFPK)
Millimeters
Symbol

Min

Max

2.286

Inches
Min

Max

3.302

0.090

0.130

0.381

0.4826

0.015

0.019

Typical

0.0762

0.1524

0.003

0.006

Typical

17.780

18.796

0.700

0.740

16.307

16.713

0.642

0.658

E
E2
E3

9.652

10.668

0.380

0.420

9.756

0.180

0.762

0.030

0.050

Notes

1.270

0.050

22.352

29.464

0.880

1.160

6.350

9.398

0.250

0.370

0.660

1.143

0.026

0.045

0.889

1.016

0.035

0.040

0.254

0.381

0.010

0.015

8-1-31

Notes

Reference

Typical

DS00049A

Microchip

Packaging Diagrams and Parameters
Ceramic Leadless Chip Carrier Family
Symbol List for Ceramic Leadless Chip Carrier Package Parameters
Symbol

Description of Parameters

Thickness of base body

Total package height

Distance from base body to highest point of body (lid)

Width of terminal lead pin

Largest overall package dimension of length

D1, E1

80dy length dimension - end lead center to end lead center

Largest overall package dimension of width

Linear spacing

Linear spacing between edges of true lead positions (of corner terminal lead pads)
lead corner to lead corner

Depth of major index feature

Width of minor index feature

Distance from package edge to end of effective pad

Total number of potentially useable lead positions

Notes:
1.
2.
3.
4.
5.

DS00049A

Controlling dimension: inches.
Dimension "e;' ("e") is non-cumulative.
Seating plane (standoff) is defined by PC board hole size.
Dimension "8" is nominal.
Corner configuration optional.

8-1-32

Microchip

Packaging Diagrams and Parameters
Package Type: 28-Lead Ceramic Leadless Chip Carrier

N
'-------'-- Pin No.1 Indicator
(size and type of
indicator may vary)

----ll
.
.~ Ir

! l

j x 45°
Index Corner

J
1'1 I

Seating Plane

f f
A1

Package Group: Ceramic Leadless Chip Carrier (LCC)
Inches

Millimeters
Symbol

Min

Max

Notes

Min

Max
0.085

1.397

2.159

0.055

1.651

2.540

0.065

0.100

0.254

0.381

0.010

0.015

0.5588

0.7112

11.2268

11.684

7.620

Typical

Reference

0.022

0.028

0.442

0.460

0.300

Notes

Typical

Reference

11.2268

11.684

0.442

0.460

7.620

Reference

0.300

Reference

1.270

Typical

0.050

Typical

0.38

Typical

0.015

Typical

1.02

Reference

0.040

Reference

0.020

Reference

Typical

0.045

0.055

Typical

0.51

1.143

1.397

8-1-33

DS00049A

Microchip

Packaging Diagrams and Parameters
Package Type: 28-Lead Ceramic Leadless Chip Carrier with Window

Pin No.1 Indicator
(size and type of
indicator may vary)

--II.
. -I

Seating Plane

--'-t--.t-.. . . .

1.....
'1 .....1_ _--1...1.....1'.....1--11

j x45'
Index Corner

F
A2

Package Group: Ceramic Leadless Chip Carrier (LCC)
Millimeters

DS00049A

Symbol

Min

Max

A
A1
A2

1.397

Inches
Notes

Min

Max

2.159

0.055

0.085

2.286

3.302

0.090

0.100

0.889

1.143

0.035

0.045

0.022

0.028

0.442

0.460

0.300

0.442

0.460

Typical

Notes

Typical

0.5588

0.7112

0
01
E
E1
e
e1

11.2268

11.684

7.620

11.2268

11.684

7.620

Reference

0.300

Reference

1.270

Typical

0.050

Typical

0.38

Typical

0.015

Typical

Reference

1.02

Reference

0.040

Reference

0.51

Reference

0.020

Reference

1.143

1.397

Typical

0.045

0.055

Typical

8-1-34

Microchip

Packaging Diagrams and Parameters
Package Type: 32-Lead Ceramic Leadless Chip Carrier

N
Pin No.1 Indicator
(size and type of
indicator may vary)

j x 45°
Index Corner

i
Seating Plane

1'1 I

I 1'1

Package Group: Ceramic Leadless Chi!! Carrier (LCC)
Millimeters
Symbol

Min

Max

Inches
Notes

Min

Max
0.085

1.397

2.159

0.055

2.54

3.048

0.100

0.120

0.254

0.381

0.010

0.015

0.635

0.7112

13.716

14.224

Typical

Reference

0.025

0.026

0.540

0.560

0.393

0.407

0.442

0.458

Notes

Typical

Reference

9.98

10.34

11.2268

11.684

7.442

7.80

Reference

0.293

0.307

Reference
Typical

1.270

Typical

0.050

0.38

Typical

0.015

Typical

1.02

Reference

0.040

Reference

0.51

Reference

0.020

Reference

1.143

1.397

Typical

0.045

0.055

Typical

8-1-35

DS00049A

Microchip

Packaging Diagrams and Parameters
Package Type: 32-Lead Ceramic Leadless Chip Carrier - FRIT

h'~O~~
! i

Seating Plane

-t-r--""""tA1

Pin No. 1 Indicator
(size and type of
indicator may vary)

j x 45°
Index Corner

L......J....IL.. .OII_ _.l-IIL....OI-J1

F
~

Package Group: Ceramic Leadless Chip Carrier (LCC)
Millimeters
Symbol

Min

Max

A
A1
A2

1.397

Min

Max

2.159

0.055

0.085

2.286

3.302

0.090

0.130

0.635

1.143

0.025

0.045

0.5588

0.7112

0.022

0.028

0
01
E
E1
e
91

13.716

14.224

0.540

0.560

7.620

11.2268

11.6332

10.160

1.270

0.38
1.02

DS00049A

Inches
Notes

Typical

Notes

Typical

Reference

0.300

0.442

0.458

Reference

0.400

Typical

0.050

Typical

0.015

Typical

1.02

Reference

0.040

Reference

0.51

Reference

0.020

Reference

1.143

1.397

Typical

0.045

0.055

Typical

8-1-36

1990 Microchip Technology Inc.

~®

Microchip

Packaging Diagrams and Parameters
Package Type: 32·Lead Ceramic Leadless Chip Carrier with Window

t:D
I

ar.,

_......

=
I

Pin No.1 Indicator
(size and type of
indicator may vary)

..-'

•

mill /
j x 45°
Index Corner

Seating Plane

"""""'j.----jr-A1

Symbol

L...-.L......L-'-_ _ _..L-lC-.l--'

Package Group: Ceramic Leadless Chip Carrier (LCC)
Millimeters
Inches
Notes
Max
Max
Min
Min

A
A1
A2

0.889

1.143

0.5588

0.7112

D
D1
E
E1
e
81

13.716

14.224

1.397

2.159

0.055

0.085

2.286

3.302

0.090

0.130

0.035

0.045

0.022

0.028

0.540

0.560

0.300

0.442

0.458

Typical
Reference

Notes

Typical
Reference

7.620

11.2268

11.6332

10.160

Reference

0.400

Reference

1.270

Typical

0.050

Typical

0.38

Typical

0.015

Typical

1.02

Reference

0.040

Reference

1.02

Reference

0.020

Reference

1.143

1.397

Typical

0.045

0.055

Typical

8-1-37

DS00049A

~®

Microchip

Packaging Diagrams and Parameters
Package Type: 32-Lead Ceramic Leadless Chip Carrier with FRIT Window

.... -.
(

\
I

Pin No.1 Indicator
(size and type of
indicator may vary)

I~'--------'

j x 45°
Index Corner

Seating Plane

---;j.-----jr-A1

III

1111=l==
I

I-.L....J.-L.._ _ _...L...J'-'---'

Package Group: Ceramic Leadless Chip Carrier (LCC)
Millimeters

DS00049A

Symbol

Min

Max

A
A1
A2

1.397

2.159

2.286
0.889

0.5588

0.7112

D
D1
E
E1
e
e1

13.716

14.224

Inches
Notes

Min

Max

0.055

0.085

3.302

0.090

0.130

1.143

0.035

0.045

Typical

Reference

0.022

0.028

0.540

0.560

0.300

0.442

0.458

Notes

Typical

7.620

11.2268

11.6332

10.160

Reference

0.400

Reference

1.270

Typical

0.050

Typical

0.38

Typical

0.015

Typical

Reference

1.02

Reference

0.040

Reference

0.51

Reference

0.020

Reference

1.143

1.397

Typical

0.045

0.055

Typical

8-1-38

Microchip

Packaging Diagrams and Parameters

LD -

Package Type: 44-Lead Ceramic Leadless Chip Carrier

•

E
L

•

II
IIIIII!

IIIIII!

-----'
L
~ Ir
J

1 1

Symbol

j x 450
Index Corner

Package Group: Ceramic Leadless Chip Carrier (LCC)
Inches
Millimeters
Notes
Min
Max
Max
Min

1.37

2.082

0.054

0.082

1.778

3.048

0.070

0.120

0.254

1.143

0.010

0.045

0.023

0.028

0.640

0.662

0.500

0.640

0.662

Pin No.1 Indicator
(size and type of
indicator may vary)

rII

Seating Plane

~~~._J--

0.584

0.7112

Typical

Notes

Typical

16.256

16.8148

12.700

16.256

16.8148

12.700

Reference

0.500

Reference

1.270

Typical

0.050

Typical

0.38

Typical

0.Q15

Typical

Reference

1.02

Reference

0.040

Reference

0.51

Reference

0.020

Reference

1.143

1.397

Typical

0.045

0.055

Typical

8-1-39

DS00049A

Microchip

Packaging Diagrams and Parameters

DS00049A

8-1-40

Microchip

Packaging Diagrams and Dimensions
Plastic Dual In-line Family
Symbol List for Plastic Dual In-line Package Parameters
Symbol

Description of Parameters

Angular spacing between min and max lead positions measured at the guage plane

Distance between seating plane to highest point of body

Distance between seating plane and base plane

Base body thickness

Width of terminal leads

Width of terminal lead shoulder which locate seating plane (standoff geometry optional)

Thickness of terminal leads

Largest overall package parameter of length

Body length parameter - end lead center to end lead center

Largest overall package width parameter outside of lead

Body width parameters not including leads

Linear spacing of true minimum lead poSition center line to center line

Linear spacing between true lead position outside of lead to outside of lead

Linear spacing between center lines of body standoffs (terminal leads)

Distance from seating plane to end of lead

Total number of potentially useable lead positions

Distance from true position center line of No.1 lead to the extremity of the body

Distance from other end lead edge positions to the extremity of the body

Notes:
1. Controlling parameter: inches.
2. Parameter "e,· ("e") is non-cumulative.
3. Seating plane (standoff) is defined by board hole size.
4. Parameter "B, " is nominal.
5. Details of pin No. 1 identifier are optional.

8-2-1

DS00049A

Microchip

Packaging Diagrams and Dimensions
Package Type: a-Lead Plastic Dual In-line (.300 mil)

a~: ~----~~il
II

~::~

DS00049A

Package Group: Plastic Dualln·line (PLA)
Millimeters
Min
Max
Notes

Symbol

Min

100

0.381

B
B1

Inches
Max

Notes

100

4.064

0.160

0.015

3.048

3.810

0.120

0.150

0.356

0.559

0.014

0.022

1.524

Typical

0.060

Typical

0.2032

0.381

Typical

0.008

0.015

Typical

D
D1
E
E1
81
8A
8S

9.144

10.922

0.360

0.430

Reference

7.620

0.300

7.620

8.255

0.300

0.325

6.096

7.112

0.240

0.280

2.489

2.591

Typical

0.098

0.102

Typical

7.620

Reference

0.300

Reference

7.874

9.906

0.310

0.390
0.140

3.048

3.556

0.120

5
51

0.889

0.035

0.127

0.005

8-2-2

Microchip

Packaging Diagrams and Dimensions
Package Type: 14-Lead Plastic Dual In-line (.300 mil)
N

TI
Pin No. 1__
Indicator
.1h-TT""TT""TT""TT""TT...r
Area

II------l

a~1

j:~

es----..J

Packaae Group: Plastic Dual In-line (PLA)
Inches

Millimeters
Symbol

Min

Max

a
A
A1

0°

10°

0.381

Notes

Min

Max

0°

10°

4.064

0.160

0.Q15

3.048

3.810

0.120

0.150

0,356

0.559

0.014

0.022

1.524

Typical

0.060

Typical

0.2032

0.381

Typical

0.008

0.015

Typical

18.415

19.431

0.725

0.765

15.240

7.620

8.255

6.096

7.112

2.4892

2.591

Notes

Reference

Typical

0.600

0.300

0.325

0.240

0.280

0.098

0.102

Typical
Reference

7.620

0.300

7.874

9.906

0.310

0.390

3.048

3.556

0.120

0.140

0.889

0.035

0.127

0.005

Reference

8-2-3

Reference

0.600

DS00049A

Microchip

Packaging Diagrams and Dimensions
Package Type: 16-Lead Plastic Dual In-line (.300 mil)
N

iTT
E1

Pin No. 1__
Indicator
1I!IIh-,..,....,.,........,.......,.......,.......,.......J
Area

11---,.....---1

a-"
1/

~::~

J J

D-~.~

:-~
=r

I..

A1 A2. A

~----D1--------··1

DS00049A

Package Group: Plastic Dualln·line (PLA)
Millimeters
Max
Min
Notes

Inches
Max

Symbol

Min

0°

10°

0°

10°

4.064

0.160

0.381

0.015

A2.

3.048

3.810

0.120

0.150

Notes

0.356

0.559

0.014

0.022

1.524

Typical

0.060

Typical

0.2032

0.381

Typical

0.008

0.015

Typical

18.923

19.939

0.745

0.785

17.780

0.700

Reference

7.620

8.255

0.300

0.325

6.096

7.112

0.240

0.280

2.489

2.591

Typical

0.098

0.102

Typical

7.620

Reference

0.300

Reference

7.874

9.906

0.310

0.390

3.0480

3.556

0.120

0.140

0.889

0.127

0.035

0.005

Microchip

Packaging Diagrams and Dimensions
Package Type: 18-Lead Plastic Dual In-line (.300 mil)
N

fTI
E1

I 1--------1

u-"
1/

PinNo.1~ ....1-T-TT""TT""TT""TT"..,.,.....,..,.....,........,...!.::hL
IJ I
Indicator

I~ ~

- - - - - l..

Area

1+------ D1 - - - - - Package Group: Plastic Dualln·line (PLA)
Millimeters
Max
Notes
Min

Symbol

Min

0°

100

Inches
Max

100
0.160

Notes

4.064

0.381

0.Q15

3.048

3.810

0.120

0.150

0.356

0.559

0.014

0.022

1.524

Typical

0.060

Typical

0.008

0.015

Typical

0.885

0.925

0.800

0.300

0.325

0.240

0.280

81
C

0.203

0.381

22.479

23.495

20.320

20.32

7.620

8.255

6.096

7.112

2.489

2.591

Typical

0.098

0.102

Typical

7.620

Reference

0.300

Reference

7.874

9.906

0.310

0.390

3.048

3.556

0.120

0.140

0.889

0.035

0.127

0.005

8-2-5

Reference

DS00049A

Microchip

Packaging Diagrams and Dimensions
Package Type: 20-Lead Plastic Dual In-line (.300 mil)

Area

I4-----D-_~~

_I_+lr=r=sTTT
1

----+

I..

A2 A

1 4 - - - - - - - D 1 - - - - - -•• 1

Symbol

Min

0°

10°

Inches
Max

0°

10°
0.160

4.064

0.381

0.015

3.048

3.810

0.120

0.150

0.355

0.558

0.014

0.022

Notes

1.524

Typical

0.060

Typical

0.203

0.381

Typical

0.008

0.Q15

Typical

24.892

26.924

0.980

1.060

22.86

0.900

7.620

8.255

0.300

0.325

6.096

7.112

0.240

0.280

2.591

Typical

0.098

0.102

Typical

Reference

2.489

7.620

0.300

7.874

9.906

0.310

0.390

3.048

3.556

0.120

0.140

0.889

0.035

0.127

0.005

DS00049A

Package Group: Plastic Dualln·line (PLA)
Millimeters
Min
Max
Notes

8-2-6

Reference

Microchip

Packaging Diagrams and Dimensions
Package Type: 22-Lead Plastic Dual In-line (.400 mil)
N

P;ON01_uuF..l:.i

I
([--/I
/I

1--------1

eB------I~

Indicator
Area

~-----

------..-1

Package Group: Plastic Dualln·line (PLA)
Inches

Millimeters
Symbol

Min

Max

([

0°

10°

Notes

Min

Max

0°

10°
.180

Notes

.180

0.381

0.015

3.175

3.810

0.125

0.150

0.356

0.559

0.014

0.022

1.524

Typical

0.060

Typical

0.008

0.015

Typical

1.050

1.120

0.203

0.381

26.670

28.448

25.400

9.906

10.795

8.382

9.398

0.330

0.370

2.489

2.591

Typical

0.098

0.102

Typical

10.160

Reference

0.400

Reference

10.160

12.192

0.400

0.480

3.048

3.556

0.120

0.140

0.889

0.035

0.127

0.005

Reference

8-2-7

1.000

0.390

0.425

Reference

DS00049A

Microchip

Packaging Diagrams and Dimensions
Package Type: 24-Lead Plastic Dual In-line (.600 mil)
N

l\\lTI

11-------1

a~n

~~i~a~~:--~~M

c--~.~-

1'.. ::

~\\I

- - - - I..

Area

S ~"",,.I-------- D

r - i - - - - - - - - - . . .---------+_. --+--'--'-

~-----D1------~

Package Group: Plastic Dualln·line (PLA)
Millimeters

DS00049A

Inches

Symbol

Min

Max

Notes

0°

A
A1
A2
8
81

0.356

0.559

1.270

Typical

0.2032

0.381

Typical

D
D1
E
E1
e1
eA
eB

30.353

32.385

27.940

15.240
12.827
2.489

2.591

15.240

15.494

3.048

S
S1

Notes

Min

Max

10°

0°

10°

5.080

0.200

0.508

0.020

3.175

4.064

0.125

0.160

0.014

0.022

0.050

Typical

0.008

0.Q15

Typical

1.195

1.275

1.100

15.875

0.600

0.625

14.224

0.505

0.560

Typical

0.098

0.102

Typical

Reference

0.600

Reference

17.272

0.610

0.680

3.556

0.120

0.140

0.889

0.035

0.127

0.005

Reference

8-2-8

Reference

Microchip

Packaging Diagrams and Dimensions
Package Type: 24-Lead Plastic Dual In-line (.300 mil)
N

1-----:---1

.'""01_
Indicator
Area

a.----II
II

r
\\1F
~~11

~----------01-----------~

Package Group: Plastic Dual In-line Package (PLA)
Inches

Millimeters
Symbol

a.
A
A1
A2

Min

Max

0°

10°

0°

10°

4.064

0.160

0.381

0.015

3.048

3.810

0.120

0.150

Notes

Min

Max

Notes

0.356

0.559

0.014

0.022

1.524

Typical

0.060

Typical

0.2032

0.381

Typical

0.008

0.015

Typical

31.242

32.258

1.230

1.270

27.940

E
E1

7.620

8.255

6.096

7.112

2.489

2.591

Typical

7.620

Reference

7.874

L
N

Reference

1.100

0.300

0.325

0.240

0.280

0.098

0.102

Typical

0.300

Reference

9.906

0.310

0.390

3.048

3.556

0.120

0.140

0.889

0.035

0.381

Reference

0.015

8-2-9

DS00049A

Microchip

Packaging Diagrams and Dimensions
Package Type: 28-Lead Dual In-line Plastic (.600 mil)

~--~---I
C'-~I .......-

a--II
II

i~"

~\ I

- - - - - I..

~-----01------~

DS00049A

Symbol

Min

Package Group: Plastic Dual-In-Llne (PLA)
Millimeters
Inches
Notes
Min
Max
Max

Notes

A
A1

0.508

0.020

3.175

4.064

0.125

0.160

B
B1

0.356

0.559

0.014

0.022

1.270

1.778

Typical

0.050

0.070

Typical

0.2032

0.381

Typical

0.008

0.015

Typical

0
01
E
E1
e1
eA
es

35.560

37.084

1.400

1.460

33.020

Reference

1.300

15.240

15.875

0.600

0.625

12.827

13.970

0.505

0.550

2.489

2.591

Typical

0.098

0.102

Typical

15.240

Reference

0.600

Reference

15.240

17.272

0.600

0.680

2.921

3.683

0.115

0.145

0.889

0.035

0.508

0.020

5.080

8-2-10

0.200

Reference

Microchip

Packaging Diagrams and Dimensions
Package Type: 40-Lead Plastic Dual In-line (.600 mil)
N

~"~.1
l\\lr
Indicator--~~M

ll------l

a--II
II

I.... :: ----I..-.JI

Area

!*------ 01 - - - - - - - . 1

Package Group: Plastic Dualln·line (PLA)
Millimeters
Min
Max
Notes

Symbol

Min

a
A
A1

0°

10°

0.381

B
B1

Inches
Max

Notes

0°

10°

5.080

0.200

0.015

3.175

4.064

0.125

0.160

0.356

0.559

0.014

0.022

1.270

1.778

Typical

0.050

0.070

Typical

0.008

0.015

Typical

2.015

2.055

0.2032

0.381

0
01
E
E1
e1

51.181

52.197

48.260

15.240

15.875

13.462

13.970

2.489

2.591

Typical
Reference

Reference

1.900
0.625

0.530

0.550

0.098

0.102

Typical
Reference

15.240

0.600

15.240

17.272

0.600

0.680

2.921

3.683

0.115

0.145

1.270

0.050

0.508

0.020

8-2-11

Reference

1.900
0.600

DS00049A

Microchip

Packaging Diagrams and Dimensions
Package Type: 48-Lead Plastic Dual In-line (.600 mil)
N

A"~.1

Indicator - Area

QuIT

a~n

~
C---'.I~-

f~"

~""""I--------

1---,.------1

:: ---·~\\I

1-1-------,.

~-------+-i -~f___l--l-

1*----- D1 -------.1

Package Group: Plastic Dual In-line (PLA)
Millimeters

DS00049A

Inches

Symbol

Min

0°

10°

0°

10°

5.080

0.200

Max

Notes

Min

Max

0.381

0.015

A2.

3.175

4.064

0.125

0.160

Notes

0.356

0.559

0.014

0.022

1.270

Typical

0.050

Typical

0.2032

0.381

Typical

0.008

0.015

Typical

2.420

2.450

61.468

62.230

58.420

15.240

15.875

Reference

2.300

0.600

0.625

Reference

13.716

14.224

0.540

0.560

2.489

2.591

Typical

0.098

0.102

Typical

eA
es

15.240

Reference

0.600

Reference

15.240

17.272

0.600

0.680

2.921

3.683

0.115

0.145

1.270

0.050

0.508

0.020

8-2-12

Microchip

Packaging Diagrams and Parameters
Plastic Leaded Chip Carrier Family
Symbol List for Plastic Leaded Chip Carrier Package Parameters
Symbol
A

Description of Parameters
Distance from seating plane to highest point of body

Distance from lead shoulder to seating plane

Seating plane coplanarity

DIE

Outside dimension

D1/E1

Plastic body dimension

D2/E2

Footprint

D3/E3

Footprint

Lead th ickness

Total number of potentially useable lead positions

Total number of leads on short side (rectangular)

Total number of leads on long side (rectangular)

Notes:

ffi

All dimensions and tolerances conform to ANSI
Y14.5M-1982.

ffi
&

A
Lit

Datum planet8jlocated at top of mold parting
line and coincident with top of lead. Where lead
exits plastic body.
DatumslQ;E!andlF-Glto be determined where
center leads exit plastic body at datum plane[8j .
To be determined at seating planel::Qj.

All dimensions and tolerances include lead
trim offset and lead finish.
These two dimensions determine maximum angle of the lead for certain socket
applications. If unit is intended to be
socketed, it is advisable to review these
dimensions with the socket supplier.

&
& (.007)
&

Controlling dimension: inches.

Transition is optional.

Sum of dam bar protrusions to be 0.17
max per lead.

Plastic body details between leads are optional.
Dimensions Dl and El do not include mold
protrusion. Allowable mold protrusion is .254
mm/.Ol0 in. per side. Dimensions D and E
include mold mismatch and are dtermined at
parting line.

Location to datumsQgand IJ3Jto be
determined at plane Q±] .

Feature is not required, but is optional at
manufacturer's discretion.

Square: Details of pin 1 identifier are optional but
must be located within one of the two zones
indicated.
Rectangle: Details of pin 1 identifier are optional
but must be located within zone indicated. If the
number of terminals on a side is odd, terminal 1
is the center terminal.

8-2-13

DS00049A

Microchip

Packaging Diagrams and Parameters
Package Type: 20-Lead Plastic Leaded Chip Carrier (Square)

:::::::~

~
T

)

..... i

M.Qa
"'-'=-->L..:'-=-.,--+-,~i--L"'T'" .020

1.651
.065
R 1.14/0.64

0.254 Max
.010

~..
::

.0451.025

Symbol

DS00049A

-~
~.508

~ MOllil&

---c 1.651
.065
R 1.14/0.64
.045/.025

Package Group: Plastic Leaded Chip Carrier (PLCC)
Inches
Millimeters
Min
Max
Notes
Min
Max

A
A1
D
D1
D2
D3
E
E1
E2
E3

4.191

4.572

0.165

2.413

2.921

0.095

0.115

9.779

10.033

0.385

0.395

0.180

8.890

9.042

0.350

0.356

7.493

8.255

0.295

0.325

5.080

0.200

9.779

10.033

0.385

0.395

8.890

9.042

0.350

0.356

7.493

8.255

0.295

0.325

5.080

0.200

0.1016

0.004

0.203

0.381

0.008

0.015

Reference

8-2-14

Notes

.Reference

Reference

Microchip

Packaging Diagrams and Parameters
Package Type: 28-Lead Plastic Leaded Chip Carrier (Square)
D

rl.I~~~BI~~
m ..
D,

.... II .. ~
Innnn

: :

~:::::::~....:

~fo

tJ'

~
~
L..JL..JL..JL..JL..JL..JL..J

/3'.,.fT1-1

1-1 I· ~6b?,7 ®I AI ®
Ell

F-G

OOi~500
~...

1.651
.065
R 1.14/0.64

~~rm&

--r:. 1.651
.065
R 1.14/0.64

.0451.025

Package Group: Plastic Leaded Chip Carrier (PLCC)
Millimeters
Symbol

Min

Max

4.191

A1
D
D1
02
03
E
E1
E2
E3
N

. CP
LT

Inches
Notes

Min

Max

4.572

0.165

0.180
0.115

2.413

2.921

0.095

12.319

12.573

0.485

0.495

11.430

11.582

0.450

0.456

10.414

10.922

0.410

0.430

7.620

0.300

0.300
0.495

Reference

12.319

12.573

0.485

11.430

11.582

0.450

0.456

10.414

10.922

0.410

0.430

7.620

0.300

0.1016

0.004

0.203

0.381

0.008

0.015

Reference

8-2-15

Notes

Reference

DS00049A

~~~~=~~

-.--.~-

Microchip

Packaging· Diagrams and Parameters
Package Type: 32-Lead Plastic Leaded Chip Carrier (Rectangle)

*.i

0.12
.005

1.14
.045
R 1.0210.76
.0401.030

Symbol

A
A1
D
D1
D2
D3
E
E1
E2
E3
N

DSOOO49A

0.51

~MOOOA
--r.1.:!!..
.045
R 1.0210.76
.040/.030

Package Group: Plastic Leaded Chip Carrier (PLCC)
Millimeters
Inches
Notes
Min
Max
Min
Max

3.048

0.120

3.556

1.905

2.413

0.075

0.095

12.319

12.573

0.485

0.495

11.35

11.506

0.447

0.453

4.826

5.334

0.190

0.210

Reference

7.620

0.300

14.859

15.113

0.585

0.595

13.893

14.046

0.547

0.553

6.096

6.858

0.240

0.270

10.160

0.400

Ne
CP

0.1016

0.004

0.203

0.381

0.008

0.015

Reference

8-2-16

Notes

0.140

Reference

Microchip

Packaging Diagrams and Parameters
Package Type: 44-Lead Plastic Leaded Chip Carrier (Square)
0

r'.I~~BI~~
01

....11.. r:o:JA\.
,i-inMnnM

:::::::~.l

.1"3\.1-

E1 E

_~II- 1$1~6h~7®IAIF-G®

0.254 Max
.010

~...

1.651
.065
R 1.14/0.64

.0451.025

Symbol

A
A1
0
01
02
03
E
E1
E2
E3

~.508

~MOQD&

-r,1.651
.065
R 1.14/0.64
.045/.025

Package Group: Plastic Leaded Chip Carrier (PLCC)
Millimeters
Inches
Min
Max
Notes
Min
Max
4.191

4.572

0.165

0.180

2.413

2.921

0.095

0.115

17.399

17.653

0.685

0.695

16.510

16.662

0.650

0.656

15.494

16.002

0.610

0.630

12.700

0.500

17.399

17.653

0.685

0.695

16.510

16.662

0.650

0.656

15.494

16.002

0.610

0.630

12.700

0.500

0.1016

0.004

0.203

0.381

0.008

0.Q15

Reference

8-2-17

Notes

Reference

OS00049A

Microchip

Packaging Diagrams and Parameters
Plastic Small Outline Family
Symbol List for Small Outline Package Parameters
Symbol

Description of Parameters

Angular spaciing between min and max lead positions measured at the guage plane

Distance between seating plane to highest point of body

Distance between seating plane and base plane

Width of terminals

Thickness of terminals

Largest overall package parameter of length

Largest overall package width parameter not including leads

Linear spacing of true minimum lead position center line to center line

Largest overall package dimension of width

Length of terminal for soldering to a substrate

Total number of potentially useable lead postions

Seating plane coplanarity

Notes:
1. Controlling parameter: inches.
2. All packages are gull wing lead form.
3. "0" and "E" are reference datums and do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .15 mm (.0086 inches).
4. The chamfer on the body is optional. If it is not present, a visual index feature must be located
within the crosshatched area to indicate pin 1 position.
5. Terminal numbers are shown for reference.

DSOO049A

8-2-18

Microchip

Packaging Diagrams and Parameters
Package Type: 8-Lead Plastic Surface Mount (SOle - Narrow, 150 mil Body)

Index
Area
Chamfer

~~D-1

t II
- :i===r1=~i

CP
Seating
Plane

Base
Plane

Package Group: Plastic sOle (SN)
Millimeters
Symbol

Min

Max

0°

Inches
Min

Max

8°

0°

8°

Notes

1.3716

1.7272

0.054

0.068

0.1016

0.2489

0.004

0.0098

0.3556

0.4826

0.014

0.019

0.1905

0.2489

0.0075

0.0098

4.8006

4.9784

0.189

0.196

3.810

3.9878

0.150

0.157

1.270

0.050

5.8166

6.1976

0.229

0.244

0.381

0.762

0.015

0.030

0.508

1.016

0.020

0.040

Typical

0.1016

0.004

I
8-2-19

Notes

Typical

DS00049A

Microchip

Packaging Diagrams and Parameters
Package Type: 8-Lead Plastic Surface Mount (SOle - Medium, 200 mil Body)

Index
Area

Chamfer
h x 45°

-L~D-1

CP
Seating Plane

*t=t;==~-Base
t

Plane

DSOo049A

Symbol

Min

0°

Package Group: Plastic SOIC (SM)
Millimeters
Max
Notes
Min

8°

0°

Inches
Max

1.778

2.032

0.070

0.080

0.1016

0.2489

0.004

0.0098

0.3556

0.4826

0.014

0.019

0.1905

0.2489

0.0075

0.0098

5.08

5.334

0.200

0.210

5.156

5.410

0.203

0.213

1.270

7.62

h
L

Typical

0.050

8.382

0.300

0.330

0.381

0.762

0.015

0.030

0.508

1.016

0.020

0.040

0.1016

0.004

8-2-20

Notes

Typical

Microchip

Packaging Diagrams and Parameters
Package Type: 14-Lead Plastic Surface Mount (SOle - Narrow, 150 mil Body)

-+I e
I

Index
Area
Chamfer

h x 45°

-.LI~

CP
Sealing Plane

·1

=i=t==i1r===~
t
Al

Base
Plane

Symbol

Min

0°

Package Group: Plastic sOle (SN)
Millimeters
Min
Max
Notes

8°

0°

Inches
Max

1.3716

1.7272

0.054

0.068

0.1016

0.2489

0.004

0.0098

0.3556

0.4826

0.014

0.019
0.0098

0.1905

0.2489

0.0075

5.08

5.334

0.387

0.393

3.810

3.9878

0.150

0.157

1.270

0.050

5.8166

6.1976

0.229

0.244

0.381

0.762

0.015

0.030

0.4064

1.143

0.016

0.045

0.1016

0.004

Typical

8-2-21

Notes

8°

Typical

DS00049A

Microchip

Packaging Diagrams and Parameters
Package Type: 14-Lead Plastic Surface Mount (SOle - Wide. 300 mil Body)

-I e lI

Index
Area

Chamfer
h x 45°

--.LI~

CP
Seating Plane

t==;1r====~ -

=i=+

Base
Plane

Package Group: Plastic SOIC (SO)
Millimeters
Symbol

Max

Inches
Notes

Min

Max

0°

8°

0°

8°

2.3622

2.6416

0.093

0.104

0.1016

0.2997

0.004

0.0118

0.3556

0.4826

0.014

0.019

0.2413

0.3175

0.0095

0.0125

0.8763

9.271

0.345

0.365

7.4168

7.5946

0.292

0.299

DS00049A

Min

1.270

10.0076

10.6426

0.381

0.4064

0.050

0.394

0.419

0.762

0.015

0.030

1.143

0.016

0.045

0.1016

0.004

Typical

8-2-22

Notes

Typical

Microchip

Packaging Diagrams and Parameters
Package Type: 16-Lead Plastic Surface Mount (SOle - Narrow, 150 mil Body)

-I e lI I
Index
Area
Chamfer
h x 45°

t ==;:::=~q;;J
1

CP ;::t
Seating - Plane
Al

Base
Plane

PackaQe Group: Plastic sOle (SN)
Inches

Millimeters
Symbol

Min

Max

Notes

Min

Max

0°

8°

0°

8°

1.3716

1.7272

0.054

0.068

0.1016

0.2489

0.004

0.0098

0.3556

0.4826

0.014

0.019

0.1905

0.2489

0.0075

0.0098

5.08

5.334

0.387

0.393

3.810

3.9878

0.150

0.157

1.270

0.050

5.8166

6.1976

0.229

0.244

0.381

0.762

0.015

0.030

0.4064

1.143

0.016

0.045

0.1016

0.004

Typical

8-2-23

Notes

Typical

DS00049A

Microchip

Packaging Diagrams and Parameters
Package Type: 16-Lead Plastic Surface Mount (SOle - Wide, 300 mil Body)

--I

I
Index
Area

14I

h x 45°

-I ~

Chamfer

h x 45°

--.L~

CP
Seating - . .
Plane

'q;;gJ i :::::;::=~
1

:;::+

Base
Plane

Package Group: Plastic SOIC (SO)
Millimeters

DSO0049A

Symbol

Min

Max

0°

Inches
Notes

Min

Max

8°

0°

8°

2.3622

2.6416

0.093

0.104

0.1016

0.2997

0.004

0.0118

0.3556

0.4826

0.014

0.019

0.2413

0.3175

0.0095

0.0125

10.1092

10.4902

0.398

0.413

7.4168

7.5946

0.292

0.299

1.270

0.050

10.0076

10.6426

0.394

0.419

Typical

0.381

0.762

0.015

0.030

0.4064

1.143

0.Q16

0.045

0.1016

0.004

8-2-24

Notes

Typical

Microchip

Packaging Diagrams and Parameters
Package Type: 18-Lead Plastic Surface Mount (SOle - Wide, 300 mil Body)

--J e 14I I

Index
Area

h x 45°

-I ~

Chamfer

h x 45°

CP
Seating Plane

.1
t :::::r:=~'qRfJ
'
0

*=+

Base
Plane

Package Group: Plastic sOle (SO)
Millimeters
Symbol

Min

Max

0°

8°

Inches
Notes

Min

Max

0°

8°

2.3622

2.6416

0.093

0.104

0.1016

0.2997

0.004

0.0118

0.3556

0.4826

0.014

0.019

0.2413

0.3175

0.0095

0.0125

11.3538

11.7348

0.447

0.462

7.4168

7.5946

0.292

0.299

1.270

10.0076

0.050

10.6426

0.394

0.419

0.381

0.762

0.015

0.030
0.045

Typical

0.4064

1.143

0.016

0.1016

0.004

8-2-25

Notes

Typical

DS00049A

Microchip

Packaging Diagrams and Parameters
Package Type: 20-Lead Plastic Surface Mount (SOle - Wide, 300 mil Body)

Index
Area

Chamfer
h x 450

~~
CP
Seating Plane

1 ==r====rtHHH;\\iKtJ
1

i=*

Base
Plane

Package Group: Plastic sOle (SO)
Millimeters
Notes
Min
Max

Inches
Max

Symbol

Min

2.3622

2.6416

0.093

0.104
0.0118

DSOOO49A

0.1016

0.2997

0.004

0.3556

0.4826

0.014

0.019

0.2413

0.3175

0.0095

0.0125

12.5984

13.0048

0.496

0.512

7.4168

7.5946

0.292

0.299

1.27.0

1.270

0.050

10.0076

10.6426

0.394

0.419

0.381

0.762

0.G15

0.030

0.4064

1.143

0.016

0.045

0.1016

0.004

Typical

8-2-26

Notes

Typical

Microchip

Packaging Diagrams and Parameters
Package Type: 24·Lead Plastic Surface Mount (SOle· Wide, 300 mil Body)

Index
Area

Chamfer
h x 45°

~I~
CP
Seating - Plane

i ===r==~
'I

\iKFJ -

i=*

Base
Plane

Package Group: Plastic sOle (SO)
Millimeters
Symbol

Inches
Min

Max

8°

0°

8°

2.3622

2.6416

0.093

0.104

0.1016

0.2997

0.004

0.0118

Min

Max

0°

Notes

0.3556

0.4826

0.014

0.019

0.2413

0.3175

0.0095

0.0125

15.2146

15.5956

0.599

0.614

7.4168

7.5946

0.292

0.299

1.270

0.050

10.0076

10.6426

0.394

0.419

0.381

0.762

0.015

0.030

0.4064

1.143

0.016

0.045

0.1016

0.004

1990 Microchip Technology Inc.

Typical

8-2-27

Notes

Typical

DS00049A

Microchip

Packaging Diagrams and Parameters
Package Type: 28-Lead Plastic Surface Mount (SOle - Wide, 300 mil Body)
~

e I--

I
Index
Area

h x 45°

-I ~

Chamfer
h x 45°

.-L~
D
~I
t ==r===~'qf;J--Base
1
Plane

CP
Seating Plane

i=+

A
Package Group: Plastic sOle (SO)
Inches

Millimeters
Symbol

DS00049A

Min

Max

Notes

Min

Max

0°

8°

0°

8°

2.3622

2.6416

0.093

0.104

0.1016

0.2997

0.004

0.0118

0.3556

0.4826

0.014

0.019

0.2413

0.3175

0.0095

0.0125

17.7038

18.0848

0.697

0.712

7.4168

7.5946

0.292

0.299

1.270

0.050

10.0076

10.6426

0.394

0.419

Typical

0.381

0.762

0.015

0.030

0.4064

1.143

0.016

0.045

0.1016

0.004

8-2-28

Notes

Typical

Microchip

APPENDIX
OFFICE LOCATIONS
Factory Representatives ........................................................................................................................ A- 1
Distributors
.................................................................................................................................. A- 5
.................................................................................................................................. A- 12
Field Offices

A-i

DS00018C

Microchip

DSOOOl8C

A-ii

Field Offices

Factory Representatives

CANADA

SOUTH AMERICA

USA

British Columbja

~
Hitech Commercial & Industrial
Av. Eng. Luiz Carlos Berrini 801
Conj. 111/121 - CEP: 04571
Brooklin, Sao Paulo
Tel: 011 531 9355
Fax: 011 240 2650
Telex: 11 53288

Alabama

Enerlec Sales, Ltd.
3671 Viking Way #7
Richmond, B.C. V6V 1W1
Tel: 604 273 0882
Fax: 604273 0884
~

Electramark, Inc.
4950 Corporate Dr., Suite 130L
Huntsville, AL 35805
Tel: 205 830 4400
Fax: 205 830 4406

Admna
Western High Tech Marketing, Inc.
9414 E. San Salvador
Scottsdale, AZ 85258
Tel: 602 860 2702
Fax: 602 8602712

Dynasty Components, Inc.
6295 Northam Drive, Unit 1
Missisauga, Ont. L4V 1W8
Tel: 4166725977
Fax: 416 672 6252

Arkansas

Dynasty Components, Inc.
174 Colonnade Road - Unit 21
Nepean, Ontario K2E 7J5
Tel:613 723 0725
Fax: 613 723 8820

Comptech Sales, Inc.
9810 E. 42nd Street, Suite 219
Tulsa, OK 74146
Tel: 918 622 7744
Fax: 918 660 0340

California

Dynasty Components, Inc.
1870 Blvd. des Sources, # 304
Pointe Claire, P.Q. H9R 5N4
Tel: 514 694 0275
Fax: 5146946826

QuadRep Southern
28720 Roadside Dr. - Suite 227
Agoura, CA 91301
Tel: 818 597 0222
Fax: 818 5971116
QuadRep Southern
4 Jenner Street, Suite 120
Irvine, CA 92718
Tel: 7147274222
Fax: 714 727 4033
QuadRep Southern
7585 Ronson Road, Suite 100
San Diego, CA 92111
Tel: 619 560 8330
Fax: 619 560 9156
QuadRep, Inc.
2713 North First Street
San Jose, CA 95134
Tel: 408 432 3300
Fax: 408 432 3428

Colorado
Western Region Marketing
9176 Marshall Place
Westminster, CO 80030
Tel: 303 428 8088
Fax: 303 426 8585

DSOOO56C-1

A-1

Factory· Representatives

Field Offices

Connecticut

Illinois

Kentucky

VISTAssociates, Inc.
2505 Main Street
Stratford, CT 06497
Tel: 203 375 5456
Fax: 203 375 6907

Janus Incorporated
650 E. Devon Ave.
Itasca, IL 60143
Tel: 708 250 9650
Fax: 708 250 8761

Electro Reps, Inc.
7240 Shadeland Station #275
Indianapolis, IN 46256
Tel: 317 8427202
Fax: 317 8410230

Delaware

SPS Associates, Ltd.
3301 Rider Trail So.uth
Earth City, MO 63045
Tel: 314291 0520
Fax: 314 291 7138

JMK Electronics
7921 Euclid Rd., Suite B
Cincinnati, OH 45243
Tel: 513 271 3860
Fax: 513 271 6321

Louisiana

Electro Reps, Inc.
407 Airport North Office Park
Fort Wayne, IN 46825
Tel: 219 489 8205
Fax: 219484 2897

Comptech Sales, Inc.
15415 Katy Fwy., Suite 102
Houston, TX 77094
Tel: 7134920005
Fax: 7134926116

Electro Reps, Inc.
7240 Shadeland Station #275
Indianapolis, IN 46256
Tel: 317 842 7202
Fax: 317 8410230

Comptech Sales, Inc.
2401 Gateway Dr., Suite 114
Irving, TX 75063
Tel: 214 751 1181
Fax: 214 550 8113

Tritek Sales
21 E. Euclid Avenue
Haddonfield, NJ 08033
Tel: 609429 1551
Fax: 609 429 4915

District of Columbia
Parogem, Inc.
3201 Harness Creek Road
Annapolis, MD 21403
Tel: 301 2691898
Fax: 301 9748170

.E!m:i.d.a
Electramark, Inc.
401 Whooping Loop, Suite 1565
Altamonte Springs, FL 32701
Tel: 407 830 0844
Fax: 407 830 0847
Electramark, Inc.
1700 N Dixie Hwy - Suite 126
Boca Raton, FL 33432
Tel: 407 3921763
Fax: 407 392 7188
Electramark, Inc.
6105E Memorial Hwy
Tampa, FL 33615
Tel: 813 889 7775
Fax: 813 889 7772

.!mu

Maine

SPS Associates, Ltd.
119 - 19th Street, Suite 102
West Des Moines, IA 50265
Tel: 515 225 0607
Fax: 515 225 8713
Telex: TWX:910 380

VISTAssociates, Inc.
237 Cedar Hill Street
Marlborough, MA 01752
Tel: 508 481 9277
Fax: 508 4601869
Telex: 710-380-0466

Kansas

Maryland

SPS Associates, Ltd.
300 A. Clairborne
Olathe, KS 66062
Tel: 913 7644460
Fax: 913 764 6161

Parogem, Inc.
3201 Harness Creek Road
Annapolis, MD 21403
Tel: 301 2691898
Fax: 301 974 8170

Georgia
Electramark, Inc.
6030H Unity Drive
Norcross, GA 30071
Tel: 404 446 7915
Fax: 404 263 6389

SPS Associates, Ltd.
501 Lancaster Dr.
Wichita, KS 67230
Tel: 316 733 4415
Fax: 316 733 5218

~
QR/Crown, Inc.
1111 South Orchard, Suite 112
Boise, ID 83702
Tel: 208 3449588
Fax: 208 344 9550

Massachusetts
VISTAssociates, Inc.
237 Cedar Hill Street
Marlborough, MA 01752
Tel: 508481 9277
Fax: 508 460 1869
Telex: 710-380-0466

Michigan
J.L.MontgomeryAssociates, Inc.
34405 W. 12 Mile Rd., Suite 149
Farmington Hills, MI 48333-2726
Tel: 313 489 0099
Fax: 313 489 0189

DS00056C-2

A-2

Field Offices

Factory Representatives

Minnesota

New Jersey

QhiQ

Comprehensive Technical Sales,
Inc.
6525 City West Parkway
Eden Prairie, MN 55344
Tel: 612 9417181
Fax: 612 9414322

Technical Marketing Group
175-3C Fairfield Ave.
W. Caldwell. NJ 07006
Tel: 201 2263300
Fax: 2012269518

JMK Electronics
7921 Euclid Rd., Suite B
Cincinnati, OH 45243
Tel: 513 271 3860
Fax: 513 271 6321

Tritek Sales
21 E. Euclid Avenue
Haddonfield, NJ 08033
Tel: 609 4291551
Fax: 6094294915

JMK Electronics
124B Woolery Lane
Dayton, OH 45415
Tel: 513 898 8834
Fax: 513 898 8863

New Mexico

JMK Electronics
7050 Engle Road, Suite 100
Middleburg Heights, OH 44130
Tel: 216 2341202
Fax: 216 2341912

Mississippi
Electramark, Inc.
4950 Corporate Dr., Suite 130L
Huntsville, AL 35805
Tel: 205 830 4400
Fax: 205 830 4406

Missouri
SPS Associates, Ltd.
3301 Rider Trail South
Earth City, MO 63045
Tel: 314 291 0520
Fax: 314 291 7138

Montana
OR/Crown, Inc.
1111 South Orchard, Suite 112
Boise, 1083702
Tel: 208 344 9588
Fax: 208 344 9550

Nebraska
SPS Associates, Ltd.
21930 Locust Street
Panama, NE 68419
Tel: 402 788 2536
Fax: 402 788 2537

~
OuadRep, Inc.
2713 North First Street
San Jose, CA 95134
Tel: 408 432 3300
Fax: 408 432 3428
Western High Tech Marketing, Inc.
9414 E. San Salvador
Scottsdale, AZ 85258
Tel: 602 860 2702
Fax: 602 860 2712

New Hampshire
VISTAssociates, Inc.
237 Cedar Hill Street
Marlborough, MA 01752
Tel: 508 481 9277
Fax: 508 460 1869
Telex: 710-380-0466

Western High Tech Marketing
4205 Montgomery, NE
Albuquerque, NM 87109
Tel: 505 884 2256
Fax: 505 884 2258

New York
Apex Associates, Inc.,
121 0 Jefferson Rd.
Rochester, NY 14623
Tel: 716 272 7040
Fax: 716 272 7756
Technical Marketing Group
20 Broad Hollow Rd., #3001
Melville, NY 11747
Tel: 516 3518833
Fax: 516 351 8667
Technical Marketing Group
175-3C Fairfield Ave.
W. Caldwell, NJ 07006
Tel: 201 2263300
Fax: 201 2269518

North Carolina
Zucker Associates
4070 Barrett Drive
Raleigh, NC 27609
Tel: 919 782 8433
Fax: 919 782 8476

Oklahoma
Comptech Sales, Inc.
9810 E. 42nd Street, Suite 219
Tulsa, OK 74146
Tel: 918 622 7744
Fax: 918 660 0340

Qwum
OR/Crown, Inc.
17020 SW Upper Boones
Ferry Road, Suite 202
Portland, OR 97224
Tel: 503 620 8320
Fax: 503 639 4023

Pennsylyania
Tritek Sales
21 E. Euclid Avenue
Haddonfield, NJ 08033
Tel: 609 4291551
Fax: 609429 4915
JMK Electronics
7921 Euclid Rd., Suite B
Cincinnati, OH 45243
Tel: 513 271 3860
Fax: 513 271 6321

North Dakota
Compo Technical Sales, Inc.
6525 City West Parkway
Eden Prairie, MN 55344
Tel: 612 941 7181
Fax: 612 9414322

Rhode Island
VISTAssociates, Inc.
237 Cedar Hill Street
Marlborough, MA 01752
Tel: 508481 9277
Fax: 5084601869
Telex: 710-380-0466

DS00056C-3

A-3

Factory Representatives

Field Offices

South Carolina

Utah

Zucker Associates
4070 Barrett Drive
Raleigh, NC 27609
Tel: 919 782 8433
Fax: 919 782 8476

Western Region Marketing
3539 S Main - Suite 210
Salt Lake City, UT 84115
Tel: 801 2689768
Fax: 801 2689773

South Dakota

Vermont

Compo Technical Sales, Inc.
0525 City West Parkway
Eden Prairie, MN 55344
Tel: 612 941 7181
Fax: 612 9414322

VISTAssociates, Inc.
237 Cedar Hill Street
Marlborough, MA 01752
Tel: 508 481 9277
Fax: 508460 1869
Telex: 710-380-0466

Tennessee
Electramark, Inc.
4950 Corporate Dr., Suite 130L
Huntsville, AL 35805
Tel: 205 830 4400
Fax: 205 830 4406
Zucker Associates
4070 Barrett Drive
Raleigh, NC 27609
Tel: 919 782 8433
Fax: 919 782 8476

Texas
Comptech Sales, Inc.
11130 Jollyville Rd., Suite 200
Austin, TX 78759
Tel: 512 343 0300
Fax: 512 345 2530
Comptech Sales, Inc.
802 E Harrison - Suite 19
Harlingen, TX 78523
Tel: 5124287503
Fax: 512 428 0242
Comptech Sales, Inc.
15415 Katy Fwy., Suite 102
Houston, TX 77094
Tel: 713 492 0005
Fax: 7134926116
Comptech Sales, Inc.
2401 Gateway Dr., Suite 114
Irving, TX 75063
Tel:2147511181
Fax: 214 550 8113

Virginia
Parogem, Inc.
3201 Harness Creek Road
Annapolis, MD 21403
Tel: 301 269 1898
Fax: 301 974 8170

Washington
QR/Crown, Inc.
375 118th Ave., Suite 110
Bellevue, WA 98005
Tel: 206 4535100
Fax: 206 646 8775

West Virginia
JMK Electronics
124B Woolery Lane
Dayton, OH 45415
Tel: 513 898 8834
Fax: 5138988863

Wisconsin
Janus, Inc.
W239 N 1690 Busse Road
Waukesha, WI 53188
Tel: 414 542 7575
Fax: 414 542 7634

Wyoming
Western Region Marketing
9176 Marshall Place
Westminster, CO 80030
Tel: 303 428 8088
Fax: 303 426 8585

Western High Tech Marketing, Inc.
4205 Montgomery NE
Albuquerque, NM 87109
Tel: 505 884 2256
Fax: 505 884 2258

DS00056C·4

A-4

Distributors

Field Offices
QnIm:!g

AFRICA

CANADA

South Africa

AIbma

Pace Electronic Components (PTY)
LTD.
Cnr. Van Acht & Gewel Streets
P.O. Box 7014
Isando 1600ITransvaai
Tel: 11 9741211/6
Fax: 11 9741271
Telex: 4-29023

ITT Multicomponents
3015 - 5th Ave. N.E. - Suite 210
Calgary, Alberta, T2A 6T8
Tel: 403 273-2780
Fax: 403 273-7458

ASIA
~
Marubeni Hytech Corporation
Marubeni Hytech Bldg.
4-20-22, Koishikawa
Bunkyo-Ku, Tokyo 112,
Tel: 81 3817-4921
Fax: 81 3817-4880

KQru
Daeho Corporation
1004, Keo Yang Building
51-8 Soosong Dong
Chongro-Ku,Seoul,
Tel: 82 2 739-8543
Fax: 82 2 739-6040

Future Electronics
3833 - 29th Street N.E.
Calgary, Alta. T1Y 6B5
Tel: 403 250-5550
Fax: 403 291-7054
ITT Multicomponents
9840 - 47th Avenue - Suite 3
Edmonton, Alta. T6E 5P3
Tel: 403 436-9555
Fax: 403 438-4983
Future Electronics
5312 Calgary Trail
Edmonton, Alta. T6H 4J8
Tel: 403 438-2858
Fax: 403 434-0812

British Columbia
ITT Multicomponents
3455 Gardner Court
Burnaby, B.C., V5G 4J7
Tel: 604291-8866
Fax: 604 291-1227
Future Electronics
1695 Boundary Road
Vancouver, B.C., V5K 4X7
Tel: 604 294-1166
Fax: 604294-1206

Manitoba
Future Electronics
106 King Edward
Winnipeg, Man. R3H ON8
Tel: 204 786-7711
ITT Multicomponents
1313 Border Street - Suite 35
Winnipeg, Manitoba, R3H OM4
Tel: 204 697-2300
Fax: 204 697-2293

A-5
-.

-~~~~~

Future Electronics
82 St. Regis
Downs View, ant. M3J 1S6
Tel: 416638-4771
Fax: 416 638-2936
ITT Multicomponents
39 Robertson Rd.
#506, Bell Mews
Nepean, ant. K2H 8R2
Tel: 613 596-6980
Fax: 613 596-6987
Future Electronics
1050 Baxter Road
Ottawa, ant. K2C 3P2
Tel: 613 820-8313
Fax: 613 820-3271

~
Future Electronics
237 Hymus Boulevard
Pointe Claire, P.O. H9R 5C7
Tel: 514 694-7710
Fax: 514 695-3707
Future Electronics
1990 Charest Blvd. West - #190
St. Foy, P.O. G1N 4K8
Tel: 418 682-8092
Fax: 418 682-8303
ITT Multicomponents
5713 Chemin St. Francois
Ville St. Laurent, P.O. H4S 1W9
Tel: 514 335-7697
Fax: 514 335-9330

Saskatchewan
ITT Multicomponents
3521 - 8th St. East, #209
Saskatoon, Sask. S7H OW5
Tel: 306 373-7138
Fax: 306 373-7390

DS00056C-5

.~--.-~-.

ITT Multicomponents
300 N. RivermedFl Road
Concord, ant. L4K 2Z4
Tel: 416 736-1144
Fax: 416 736-4831

Distributors
EUROPE
Austria
Bacher EI. Geraete GmbH
Rotenmuehlgasse 26
A-1120Wien
Tel: 0222 813564
Fax: 0222 834276

Belgium
Velleman N.V.
Legen Heirweg
Industrieterrein 27
B-9751 Gavere
Tel: 091 843611
Fax: 091 844362 Telex: 11668

Denmark
Nordisk Elektronik AS
Transiormervej 17
DK-2730 Herlev
Tel: 02 842000

England
Polar Electronics PLC
Cherrycourt Way
Leighton Buzzard
Bedfordshire LU7 8YV
Tel: 0525 377093
V.S.1. Electronics Ltd.
Roydonbury Ind. Park
Horsecroit Road
Harlow, Essex CM19 5BY
Tel: 0279 29666
Campbell Collins Ltd.
162 High Street
Stevenage
Hertfordshire
Tel: 0438 369466
Future Electronics Ltd.
Petersfield Avenue
Slough, Berkshire, SL2 5EA

.Ei.!:l.I.and.
KomdelOy
Meteorinkatu 3
SF-02211 Espoo
Tel: 0 885011

f!:mg
Ericsson
1 parc Club Ariane
Rue Helene Boucher
78284 Guyancourt
Tel: 30640900
Fax: 30 64 11 46

Field Offices
France (cont.)

Italy (cont.)

P.E.P.
6 Rue Ambroise Croizat
ZI des Glaises
91122 Palaiseau Cedex
Tel: 64470031
Fax: 64 47 00 84

Kevin
Via del Gradenigo, 3
20148 Milano
Tel: 2 4870 6300
Fax: 2 4870 6500

Netherlands
Mecodis
Parc d'Activites
3 Allee des Erables
94042 Creteil Cedex
Tel: 43 99 44 00
Fax: 43 99 98 28

Semicon B.V.
P.O. Box 258, Gulberg 33
NL-5670 AG Nuenen
Tel: 040 837075
Fax: 040 832300

Germany
Metronik GmbH
Leonhardsweg 2
8025 Unterhaching
Tel: 089611080
Fax: 089 611468

Morgenstierne & Co. AlS
Konghellengaten 3/5
N-0569 Oslo 5
Tel: 02356110

Portugal

Semitron W. Roeck GmbH
1m Gut 1
D-7891 Kuessaberg 6
Tel: 07742 7011
Fax: 07742 6901

Digicontrole
Dpt. Comercial
Ave. Eng. Arantes E Oliveira 52d
1900 Lisboa
Tel: 11 805 730
Fax: 11 890 373

Electronic 2000 Vertriebs AG
Stahlgruberring 12
D-8000 Muenchen 82
Tel: 089 42001-0
Fax: 08942001210

sam

!m!aruI
Eltech Agencies, ltd.
Lehanaghmore
Farmers Cross, Cork

lmJ!
Elina Ltd.
3, Hametzuda Street
Azur 58001, Holon
Tel: 3 559 0275/6
Fax: 3 559 0270

!lilY
Deutsche ITT/lntesi
Viale Milanofiori, E/5
20090 Assago Milano
Tel: 2 8247 0215
Fax: 2 8247 0278
Eurelettronica Sri
Viale E. Fermi 8
20094 Assago Milano
Tel: 2 488 0022
Fax: 2 488 0275

DS00056C-6

Sagitron
Corazon de Maria 80/82
28402 Madrid
Tel: 1 4169261
Fax: 14158652

Sweden
Bexab Technology AS
Kemistvaegen 10
Box 523, KAJC
Tel: S-18325 Taeby
Fax: 08 732 8980

Switzerland
OmniRayAG
Industriestrasse 31
CH-8305 Dietlikon
01 8352111
Tel: 01 8335081

~
Electro
Sanayiva Ticaret Koli. StL
Ahmet Rasim Sok. No. 16
Hasanpasa, Kadikoy, Istanbul
Tel: 01 3372245
Fax: 01 3368814

A-6

Distributors

Field Offices
USA
Alabama
Future Electronics
4950 Corporate Dr. - Suite 145
Huntsville, AL 35081
Tel: 205830-2322
Fax: 205 830-6664
Hall-Mark Electronics
4900 Bradford Drive
Huntsville, AL 35805
Tel: 205 837-8700
Fax: 205 830-2565
Reptron Electronics
4950 Corporate Dr. - Suite 105C
Huntsville, AL 35805
Tel: 205 722-9500
Fax: 205 722-9565

A!:.imDi
Future Electronics
4636 E. University Dr. - Suite 245
Phoenix, AZ 85034
Tel: 602 968-7140
Fax: 602 968-0334
Hall-Mark Electronics
4637 South 36th Place
Phoenix, AZ 85040
Tel: 602437-1200
Fax: 602 437-2348

California

California (cont.)

Future Electronics
9301 Oakdale Ave. - Suite 210
Chatsworth, CA 91311
Tel: 818 772-6240
Fax: 818 772-6247

Hall-Mark Electronics
580 Menlo Drive - Suite 2
Rocklin, CA 95677
Tel: 916 624-9781
Fax: 916 961-0922

Hall-Mark Electronics
9420 Topanago Canyon Blvd.
Chatsworth, CA 91311
Tel: 818 773-4500
Fax: 818 773-4555

Future Electronics
3940 Ruffin Road #E
San Diego, CA 92123
Tel: 619 278-5020
Fax: 619 576-8564

Bell Microproducts, Inc.
18350 Mt. Langley - Suite 207
Fountain Valley, CA 92708
Tel: 714 963-0667
Fax: 714 968-3195

Hall-Mark Electronics
3878 Ruffin Road
San Diego, CA 92123
Tel: 619 268-1201
Fax: 619 268-0209

Future Electronics
1692 Browning Ave.
Irvine, CA 92714
Tel: 714 250-4141
Fax: 714250-4185

Hall-Mark Electronics
2105 Lundy Avenue
San Jose, CA 95131
Tel: 408 432-0900

Falcon Electronics
2301 Dupont Drive - Suite 160
Irvine, CA 92715
Tel: 714 757-1955
Fax: 714 757-1890

Future Electronics
575 River Oaks Parkway
San Jose, CA 95134
Tel: 408 434-1122

Hall-Mark Electronics
1 Maunchly
Irvine, CA 92718
Tel: 714 727-6000
Fax: 714 727-6066
Bell Microproducts, Inc.
550 Sycamore Drive
Milpitas, CA 95035
Tel: 408 434-1150
Fax: 408 434-0778

DS00056C-7

A-7

Distributors

Field Offices

Colorado

Florida (cont.>

Georgia (cont.)

Future Electronics
9030 Yukon Street - Suite 2700
Broomfield, CO 80021
Tel: 303 421-0123

Future Electronics
4900 M Creekside Drive
Clearwater, FL 34620
Tel: 813 578-2770
Fax: 813 576-7600

Reptron Electronics
3040 Business Park Dr. - Suite H
Norcross, GA 30071
Tel: 404 446-1300
Fax: 404 446-2991

Hall-Mark Electronics
12503 E. Euclid Drive - Suite 20
Englewood, CO 80111
Tel: 303 790-1662
Fax: 303 790-4991

Vantage Components, Inc.
1761 W. Hillsborough Ave. - #318
Deerfield Beach, FL 33441
Tel: 305 429-1001
Fax: 305481-3586

Connecticut

Illinois
Advent Electronics
7110 - 16 N. Lyndon Street
Rosemont, IL 60018
Tel: 708 297-6200
Fax: 708 297-6650

Future Electronics
24 Stoney Hill Road
Bethel, CT 06801
Tel: 203 743-9594
Fax: 203 798-9745

Reptron Electronics
3320 N.W. 53rd SI. - Suite 206
FI. Lauderdale, FL 33309
Tel: 305 735-1112
Fax: 305 735-1121

Hall-Mark Electronics
615 West Johnson Ave. - Bldg. 3
Cheshire, CT 06410
Tel: 203 271-2844

Hall-Mark Electronics
10491 - 72nd SI. North
Largo, FL 34647
Tel: 813 541-7440
Fax: 813 544-4394

Reptron Electronics
1000 East State Pkwy - Suite K
Schaumburg, IL 60195
Tel: 708 882-1700
Fax: 708 882-8904
Hall-Mark Electronics
210 Mittel Drive
Wood Dale, IL 60191
Tel: 708 860-3800

Florida

Hall-Mark Electronics
3161 SW. 15th Street
McNabb Road
Pompano Beach, FL33069
Tel: 305 971-9280
Fax: 305 971-9339

Future Electronics
380 S. Northlake Blvd. - Suite 1048
Altamonte Springs, FL 32701
Tel: 407 767-8414
Fax: 407 834-9318

Reptron Electronics
14401 McCormick Drive
Tampa, FL 33626
Tel: 813 855-4656
Fax: 813 855-7660

CAM/RPC
1329 W. 96th SI. - Suite 10
Indianapolis, IN 46260
Tel: 317 578-1111
Fax: 317 578-3338

Vantage Components, Inc.
1110 Douglas Ave. - Suite 2050
Altamonte Springs, FL 32714
Tel: 407 682-1199
Fax: 407 682-1286

Falcon Electronics
1265 S. Semoran Blvd. - Suite 1203
Winter Park, FL 32792
Tel: 407 671-3739
Fax: 407 679-3255

Advent Electronics
8446 Moller Road
Indianapolis, IN 46268
Tel: 317 872-4910
Fax: 317 872-9987

Hall-Mark Electronics
489 E. Semoran Blvd. - Suite 145
Casselberry, FL 32707
Tel: 407 830-5855
Fax: 407 767-5002

Georgia

Hall-Mark Electronics
4275 West 96th Street
Indianapolis, IN 46268
Tel: 317 872-8875
Fax: 317 876-7165

Falcon Electronics
5 Higgins Drive
Milford, CT 06460
Tel: 203 878-5272
Fax: 203 877-2010

Future Electronics
3000 Northwoods Pkwy. - #295
Norcross, GA 30071
Tel: 404 441-7676
Fax: 404441-7580

Future Electronics
1000 East State Parkway - Suite B
Schaumburg, IL 60195
Tel: 708 882-1255

!ruWmil

Hall-Mark Electronics
3425 Corporate Way - Suite A
Duluth, GA 30136
Tel: 404 623-4400
Fax: 404 476-8806

DS00056C-8

A-8

Distributors

Field Offices
!Qn

Massachussetts

Michigan (cont.)

Advent Electronics
682 - 58th Ave. Court S.W.
Cedar Rapids, IA 52404
Tel: 319 363-0221
Fax: 319 363-4514

Vantage Components, Inc.
200 Bullfinch Drive
Andover, MA 01810
Tel: 508 687-3900
Fax: 508 687-4116

Hall-Mark Electronics
38027 Schoolcraft Road
Livonia, MI48150
Tel: 313 462-1205
Fax: 313 462-1830

KmHi

Hall-Mark Electronics
6 Cook St. - Pinehurst Park
Billerica, MA 01821
Tel: 617 935-9777
Fax: 617 667-4129

Reptron Electronics
34403 Glendale Road
Livonia, MI 48150
Tel: 313 525-2700
Fax: 313 525-3209

Falcon Electronics
500 Franklin Village Dr. #302
Franklin, MA 02038
Tel: 508 520-0323
Fax: 508 528-2626

Minnesota

Hall-Mark Electronics
10809 Lakeview Drive
Lenexa, KS 66215
Tel: 913 888-4747'
Fax: 913 888-0523

Maryland
Falcon Electronics
1520 Caton Research Ctr. #0
Baltimore, MD 21227
Tel: 301 247-5800
Fax: 301 247-5893
Vantage Components, Inc.
6925 R. Oakland Mills Road
Columbia, MD 21045
Tel: 301720-5100
Fax: 301381-2172
Future Electronics
7165 Columbia Gateway Dr. #G
Columbia, MD 21046
Tel: 301 995-1222
Fax: 301 290-0328
Hall-Mark Electronics
10240 Old Columbia Road
Columbia, MD 21046
Tel: 301 988-9800
Fax: 301381-2036

Future Electronics
133 Flanders Road
Westborough, MA 01581
Tel: 508 366-2400
Fax: 508 366-1195
Bell Microproducts, Inc.
16 Upton Drive
Wilmington, MA 01887
Tel: 508 658-0222
Fax: 508 694-9987

Michigan
Advent Electronics
24713 Crestview Court
Farmington Hills, MI 48333
Tel: 313 477-1650
Fax: 313 477-2630
CAM/RPC
32468 Schoolcraft Road
Livonia, MI48150
Tel: 313 427-4800
Fax: 313 427-4820
Future Electronics
35200 Schoolcraft Road - #106
Livonia, MI48150
Tel: 313 261-5270
Fax: 313 261-8125

Future Electronics
10025 Valley View Road - #196
Eden Prairie, MN 55344
Tel: 612 944-2200
Fax: 612 944-2520
Hall-Mark Electronics
10300 Valley View Road - #101
Eden Prairie, MN 55344
Tel: 612 941-2600
Fax: 612 941-5778
Reptron Electronics
5959 Baker Road - Suite 405
Minnetonka, MN 55344
Tel: 612 938-0000
Fax: 612 938-3995

Missouri
Hall-Mark Electronics
3783 Rider Trail South
Earth City, MO 63045
Tel: 314 291-5350
Fax: 314 291-0362
Future Electronics
1067 N. Mason Road - Suite 15
St. Louis, MO 63141
Tel: 314 469-6805
Fax: 314 469-7226

DS00056C-9

A-9

Distributors

Field Offices

New Jersey

New York

North carolina

Vantage Components, Inc.
23 Sebago Street
Clifton, NJ 07013
Tel: 201 777-4100
Fax: 201 777-6194

Hall-Mark Electronics
6605 Pittsford Palmyra Rd. #E-8
Fairport, NY 14450
Tel: 716 425-3300
Fax: 716 425-7195

Future Electronics
1515 Mockingbird Lane
Charlotte, NC 28209
Tel: 704529-5500
Fax: 704 527-2222

Future Electronics
122 Fairfield Road
Fairfield, NJ 07006
Tel: 201 227-4346
Fax: 201 227-5305

Falcon Electronics
1383-18 Veterans Memorial Hwy.
Hauppauge, NY 11788
Tel: 516 724-0980
Fax: 516 724-0993

Hall-Mark Electronics
5234 Green's Dairy Road
Raleigh, NC 27604
Tel: 919 872-0712
Fax: 919 878-8729

Future Electronics
520 Fellowship Road
Mt. Laurel, NJ 08054
Tel: 609 778-7600
Fax: 609778-4621

Future Electronics
801 Motor Parkway
Hauppauge, NY 11788
Tel: 516 234-4000
Fax: 516 234-6183

Future Electronics
1304 Paddock Dr. - Suite F100
Raleigh, NC 27609
Tel: 919 790-7111
Fax: 919 790-9022

Hall-Mark Electronics
11000 Midlantic Drive - Suite 5
Mt. Laurel, NJ 08054
Tel: 609 235-1900
Fax: 609 235-3381

Future Electronics
7453 Morgan Road
Liverpool, NY 13090
Tel: 315 451-2371
Fax: 315 451-7258

Reptron Electronics
5954-A Six Forks Road
Raleigh, NC 27609
Tel: 919 870-5189
Fax: 919 870-5210

Future Electronics
1259 Route 46 East
Parsippany, NJ 07054
Tel: 201 299-0400
Fax: 201299-1377

CAM/RPC
2975 Brighton Henrietta
Town Line Road
Rochester, NY 14623
Tel: 716 427-9999
Fax: 716 427-7559

~
CAM/RPC
749 Miner Road
Cleveland, OH 44143
Tel: 800 283-5588
Fax: 216 461-4329

Future Electronics
333 Metro Park
Rochester, NY 14623
Tel: 716 272-1120
Fax: 716 272-7182

CAM/RPC
15 Bishop Drive - Suite 104
Columbus, OH 43081
Tel: 614 888-7777
Fax: 614 895-1550

Hall-Mark Electronics
3075 Veterans Memorial Hwy.
Ronkonkoma, NY 11779
Tel: 516 737-0600
Fax: 516 737-0838

CAM/RPC
7973-B Washington Woods Drive
Dayton, OH 45459
Tel: 513 898-1111
Fax: 513 433-6792

Vantage Components, Inc.
1056 West Jericho Turnpike
Smithtown, NY 11787
Tel: 516 543-2000
Fax: 516 543-2030

Hall-Mark Electronics
5821 Harper Road
Solon, OH 44139
Tel: 216 349-4632
Fax: 216 248-4803

Hall-Mark Electronics
200 Lanidex Plaza - 2nd Floor
Parsippany, NJ 07054
Tel: 201 575-4415
Fax: 201 525-4475

Reptron Electronics
30640 Bainbridge Road
Solon, OH 44139
Tel: 216 349-1415
Fax: 216 349-1634

DSOOO56C-10

A-10

Distributors

Field Offices
Ohio (cont.)

Pennsylvania

1.HIh

Hall-Mark Electronics
400 E. Wilson Bridge Rd. - #S
Worthington, OH 43085
Tel: 614 888-3313
Fax: 614 888-0767

CAM/RPC
620 Alpha Drive
Pittsburgh, PA 15238
Tel: 800 245-2519
Fax: 412 963-6210

Future Electronics
2250 S. Redwood Road
Salt Lake City, UT 84119
Tel: 801 972-8489
Fax: 801 972-3602

Reptron Electronics
404 E. Wilson Bridge Rd. #A
Worthington, OH 43085
Tel: 614 436-6675
Fax: 614 436-4285

lull

Washington

Hall-Mark Electronics
12211 Technology Blvd.
Austin, TX 78727
Tel: 512 258-8848
Fax: 512 258-3777

Falcon Electronics
19231 - 36th ave. West
Lynnwood, WA 98036
Tel: 206 774-3005

Oklahoma
Hall-Mark Electronics
5411 S. 125th E. Ave. - Suite 305
Tulsa, OK 74146
Tel: 918 251-1108
Fax: 918 254-6207

Future Electronics
15236 N.w. Greenbrier Pkwy.
Beaverton, OR 97006
Tel: 503 645-9454
Fax: 503 645-1559

Hall-Mark Electronics
11420 Pagemill Road
Dallas, TX 75243
Tel: 214 553-4300
Fax: 214 553-4395
Hall-Mark Electronics
8000 Westglen
Houston, TX 77063
Tel: 713 781-6100
Fax: 713 953-8420
Future Electronics
11271 Richmond Ave. - Suite 106
Houston, TX 77082
Tel: 713 556-8696
Fax: 713 589-7069

Future Electronics
4038 - 148th Ave. N.E.
Redmond, WA 98052
Tel: 206 881-8199
Fax: 206 881-5232
Hall-Mark Electronics
250 N.W. 39th - Suite 4
Seattle, WA 98107
Tel: 206 547-0415

Wisconsin
Hall-Mark Electronics
16255 W. Lincoln Ave.
New Berlin, WI 53151
Tel: 414 797-7844
Fax: 414 797-9259

Future Electronics
1850 N. Greenville Ave. - Suite 146
Richardson, TX 75081
Tel: 214 437-2437
Fax: 214 669-2347

DS00056C-11

A-11

Field Offices
ASIA

EUROPE

ASIAN HEADQUARTERS

EUROPEAN HEADQUARTERS

USA

Hong Kong

England

California

Arizona Microchip Technology Ltd.
75, Mody Road, Tsimshatsui East
Rm 1103, Tower 1, So. Seas Ctr.
Kowloon
Tel: 311 6103
Fax: 311 5125
Telex: 44611

Arizona Microchip Technology
Unit 3, Meadow Bank, Furlong
Road
Bourne End, Bucks SL8 5AJ
Tel: 0628 850303
Fax: 0628 850178

Microchip Technology Inc.
1411 W. 190th Street, Suite 230
Gardena, CA 90248
Tel: 213 3231888
Fax: 213 3231424

~
Microchip Technology Inc.
4F Madre Matsuda Bldg.
4-13, Kioi-Cho,
Chiyoda-Ku, Tokyo 102
Tel: 3 234 8774
Fax: 3 234 8549

KQru
Microchip Technology Inc.
c/o Daeho Corp.
1004 Keo Yang Bldg.
51-8 Soosong Dong
Chongro-Ku, Seoul
Tel: 2 7209800
Fax: 2 7396040
Telex: 26880

~
Arizona Microchip Technology
2, Rue du Buisson aux Fraises
F-91300 Massy
Tel: 1 69309090
Fax: 1 69 30 90 79

Germany
Arizona Microchip Technology
Alte Landstr. 12-14
D-8012 Ottobrunn
Tel: 089 609 6072
Fax: 089 6091997
Telex: 524518

Microchip Technology Inc.
2107 North First Street, #410
San Jose, CA 95131
Tel: 408 436 7950
Fax: 408 436 7955

Georgia
Microchip Technology Inc.
2860 Johnson Ferry Rd. N.E.,
#250B
Marietta, GA 30062
Tel: 404 642 6933
Fax: 404 642 6890

Illinois
Microchip Technology Inc.
800 East Diehl Road, Suite 175
Naperville, IL 60563
Tel: 708 505 0022
Fax: 708 505 0065

Singapore
Massachusetts

Arizona Microchip Technology Ltd.
Singapore Representative Office
10 Anson Road, #14-02
International Plaza
Singapore 0207
Tel: 2224962
Fax: 2224939

Microchip Technology Inc.
Five The Mountain Road, Suite 120
Framingham, MA 01701
Tel: 508 820 3334
Fax: 508 872 0923

New York
!§iY!am

Microchip Technology Inc.
300 Wheeler Road., Suite 206
Hauppage, NY 11788
Tel: 516 2321930
Fax: 516 232·1935

Microchip Technology Taiwan
Liaison Office
5F, 41 Ming Chuan Road
Hsin-Tien, Taipei
Tel: 2 911 3431
Fax: 2 914 6234

Iu.u

Microchip Technology Inc.
17480 N Dallas Pkwy., Suite 114
Dallas, TX 75287
Tel: 214 733 0391
Fax: 214 250 4631

Microchip
Microchip Technology Inc.· 2355 W. Chandler Blvd.· Chandler, AZ85224-6199· (602) 963-7373· Printed in USA ©9005

OS00056C-12

A-12

- - - - - - - - - - - - -- - - - - - - -..

Microchip

DS00018C

Microchip Technology Inc,
2355 W Chandler Blvd.
Chandler, AZ 85224-6199
Tel:602 963 7373 FAX:602 345 3390

Printed in USA

Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2013:10:26 16:05:55-08:00 Modify Date : 2013:10:26 21:55:19-07:00 Metadata Date : 2013:10:26 21:55:19-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:e1b807a2-8a3d-405b-a334-7ae6aca2cd91 Instance ID : uuid:a25e265c-c6b2-4619-bca5-28fd8e14d96d Page Layout : SinglePage Page Mode : UseNone Page Count : 608
EXIF Metadata provided by EXIF.tools

1990_Microchip_Data_Book 1990 Microchip Data Book

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