1990_Microprocessors_and_Peripheral_Circuits 1990 Microprocessors And Peripheral Circuits

User Manual: 1990_Microprocessors_and_Peripheral_Circuits

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___ CIRCUIT

All values shown in this catalogue are subject to change for product improvement.
The information, diagrams and all other data included herein
are believed to be correct and reliable. However, no responsibility is assumed by Mitsubishi Electric Corporation for their use, nor
for any infringements of patents or other rights belonging to third
parties which may result from their use.

MITSUBISHI LSls

CONTENTS

DGM'CRO M32 Family MICROPROCESSORS
M33210GS-20/FP-20
M33220GS-20

CMOS 32-bit Parallel Microprocessor (M32/100) ··························· .. ················ .. ··7-3
CMOS 32-bit Parallel Microprocessor (M32/200) ................................................. 7-5

M33230GS-20

CMOS 32-bit Parallel Microprocessor (M32/300) ·················································7-7

DGM'CRO M32 Family PERIPHERAL CIRCUITS
M33241GS

CMOS DMA Controller (M32/DMAC) ...................................................... ···········8-3

M33242SP/J

CMOS Interupt Controller (M32/IRC) ...................................................... ···········8-5

M33243GS-25, -30

CMOS TAG Memory (M32/TAGM) ...................................................... ··············8-7

M33244T-16, -20

Clock Pulse Generator for M32/200 (CPG/200) ................................................... 8-9

M33245GS

CMOS Cache Controller/Memory (M32/CCM) .................................................... 8-10

M33281 GS-20

CMOS Floating-Point Processing Unit (M32/FPU) ················································8-12

Contact Addresses for Further Information

•
MITSUBISHI
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MITSUBISHI LSls

INDEX BY FUNCTION

Electncal characteristics

Type

CircUit function and organization

Structure

Supply
voltage
(V)

Typ
Max
pwr access
diSSipation time
(mW) (ns)

Min
Max
cycle Ire- Package
time quency
(ns) (MHz)

Page

.CMOS PERIPHERAL CIRCUITS
M5M81C55P-2
M5M81C55FP-2
M5M81C55J-2
M5M81C56P-2
M5M81C56FP-2
M5M81C56J-2

CMOS 2048-blt Static RAM with 1/0
Ports and Timer (CE="L" active)
CMOS 2048-blt Static RAM with 1/0
Ports and Timer (CE="H" active)

M5M82C37AP-5
M5M82C37AFP-5
M5M82C37AJ-5

CMOS Programmable DMA
Controller

M5M82C51AP
M5M82C51AFP
M5M82C51AJ

CMOS Programmable
Communication Interlace

M5M82C54P
M5M82C54FP
M5M82C54J

CMOS Programmable
Interval Timer

M5M82C55AP-2
M5M82C55AFP-2
M5M82C55AJ-2

CMOS Programmable
Pertpheral Interface

M5M82C59AP-2
M5M82C59AFP-2
M5M82C59AJ-2
M5M82C255ASP

C,SI

5±1O%

35

120

200

5

40P4

4-3

C,SI

5±10%

35

120

200

5

40P2R

4-3

C,SI

5±1O%

35

120

200

44PO

4-3

e,SI

5±10%

35

120

200

5
5

40P4

4-13

C,SI

5±10%

35

120

200

5

40P2R

4-13

C,SI

5±10%

35

120

200

5

44PO

4-13

C,SI

5±10% 22,5

140

200

5

40P4

4-23

C,SI

5±10% 22.5

140

200

5

40P2R'
44PO

e,SI

5±10%

6

170

320

3

28P4

C,SI

5±10%

6

170

320

3

28P2W

C,SI

5±10%

6

170

320

3

28PO

C,SI

5±10%

35

120

125

8

24P4
24P2W

C,SI

5±10%

120

125

8

C,SI

5±10%

-

120

320

-

40P4

C,SI

5±10%

-

120

320

-

40P2R

C,SI

5±10%

-

120

310

-

28P4

35

28PO

44PO

4-23
4-43
4-43
4-61
4-61
4-72
4-72
4-88

CMOS Programmable
Interrupt Controller

C,SI

5±10%

-

120

310

-

28P2W

CMOS Programmable
Pertpheral Interface

C,SI

5±10%

-

120

320

-

64P4B

4-105

Max
frequency
(MHz)

Package

Page

20

135S81160PS

7-3

20

135S8X-A

7-5

20

179S8X-B

7-7

28PO

4-88

.32-BIT MICROPROCESSORS GMICRO'" • M32 FAMILY
Electrical characteristiCS

Type No

Structure

CIrCUit function

Supply
voltage

power

(V)

diSSipation

Typ.
(mW)

**
**
M33230GS-20 **
M33241GS
**
M33242SP/J
**
M33243GS-25,-3Q **
M33244T-16,-20 **
M33245GS
**
M33281 GS-20 **

-

M33210GSlFP-20

32-Blt Mlcroprocessor( M32/1 00)

C,SI

5+5%

M33220G8-20

32-Blt Mlcroprocessor( M32/200)

C,SI

5±5%

32-Blt Mlcroprocessor( M32/300)

C,SI

5±5%

DMA Controller(M32/DMAC)

C,SI

5±5%

1200

20

179S8X-A

8-3

Interrupt Request Controller(M32/IRC)

C,SI

5±5%

200

20

64P4X·AI
6BPOX·A

8-5

TAG Memory(M32/TAGM)

C,SI

5±10%

1250

-

64S8X-A

8-7

-

5±5%

16/20

14T4X·A

8-9

Cache Controller/Memory( M32/CCM)

C,SI

5±5%

-

-

135S8

8-10

Floating POint Processing Unit( M3,2/FPU)

C,SI

5+5%

-

20

135S8X-A

8-12

Clock Pulse Generator for M32/200(CPG/200)

The GMICROn, trade mark indicates a G-MICRO group thoron type micro processor

** :

Under development
C = CMOS.
SI = SIlicon gate

1-4

• MITSUBISHI
" " ELECTRIC

MITSUBISHI LSls

PACKAGE OUTLINES

TYPE 14P4 14-PIN MOLDED PLASTIC DIP

19+ 0 . 5
-0 2

762±0.3

I

,----,

i\

2 54±0 25

o 5±0
1 5

1

/'

7.6-10

:t:g:~

TYPE 16P4 16-PIN MOLDED PLASTIC DIP

Dimension

7 62± 0 3

2 54 ± 0 25

o 5± 0

1

15::g ;

1-6

\

• MITSUBISHI
" " ELECTRIC

7.6-10

In

mm

MITSUBISHI LSls

PACKAGE OUTLINES

Dimension in mm

TYPE 20P4 20-PIN MOLDED PLASTIC DIP

7 62± 0 3

r ' . \
i\
3MIN

li

O.27~g·g~

0.S±0.1
2. 54± 0 .25

7.6-10

Dimension in mm

TYPE 24P4 24-PIN MOLDED PLASTIC DIP
31.1~n

~I

o
15.24±0.3

I
i

I

J

\

0.27+ 0 . 1

~,~~5
0.5±0.1
2.54 ±O. 25

1-8

1.2~n

•
MITSUBISHI
"'ELECTRIC

15.2-17

i

MITSUBISHI LSls

PACKAGE OUTLINES

TYPE 28P2W

Dimension in mm

28-PIN MOLDED PLASTIC FLAT

o

o

8. 4±Q. 2

"CO
00

6

+1<'J

ciei

+1

"'

6

cJ~r==t!=--;;;~ ----,) ~

Q.5±Q.2

;:;;6

11. 93±Q. 3

TYPE 40P4

Dimension In mm

40-PIN MOLDED PLASTIC DIP

15.24 ±O.3

~~
~ .. '"" ,.'""
•

1.2:':t~

1-10

\

_.

,

~5.5MAX

.

• . MITSUBISHI
..... ELECTRIC

15.2-17

MITSUBISHI LSls

PACKAGE OUTLINES

TYPE 64S8X-A

'Dimension in mm

64-PIN METAL-SEALED CERAMIC PGA (GMICRO™)

1.27 TYP DIA

/

:@

' "~, \h~
~0
I

18.24

sa TYP

26.20

0

coo

0

0

0

0

@

0000000000

o

0

o

0

o

0

o

0

o

0

0

o

0

o

0

o
o
o

0

0

I

~U~ sa
5.33MAX

TYPE 68POX-A

68-PIN MOLDED PLASTIC LEADED CHIP CARRIER (GMICRO™)
4 30+ 0. 22
. -0.11

0.51

Dimension

20·~ _ _ REF

1. 27±0. 13

MIN

TYP

:7 ~-=--_-~ ____________________ _
"A·· I

I

Details of "A" part

I
I

I

I
I
:

O 20 +0.05
• -Q~

I
I
I

(RO.95

~

I
I
I

:
23. 65±0. 51
:
IL ______________________
RO.75
TYP
1
~

1-12

•
MITSUBISHI
..... ELECTRIC

No

LEAD No

In

mm

MITSUBISHI LSI.

PACKAGE OUTLINES

TYPE 14T4X-A

14-PIN HERMETIC· SEALED PACKAGE (GMICRO™)

Dimension in mm

15. 24±0. 3

III

d

+t
<>
d

N

I..

2O.0±0.5

~

m

~--------,

j;.,--------I

TYPE 64P4X-A

I

3g

<>

+i
~

Dimension in mm

64-PIN MOLDED PLASTIC DIP (LEAD PITCH 1.778mm)

58.00~~:~

~

d

+1

8

~

'- --L
O. 25±0.

MAX

MIN

I. 778
MAX

1. 778±0. 18

,II.

O. 45±0. 10

'"'-_ _ _ _----'5~5.c.!.1~18_ _ _ R E F - - - - - _ . . I

1-14

• MITSUBISHI
. . . .·ELECTRIC

0.51

MIN

05T

MITSUBISHI LSls

LETTER SYMBOLS FOR THE DYNAMIC PARAMETERS

1. INTRODUCTION
A system of letter symbols to be used to represent the
dynamic parameters of intergrated circuit memories and
other sequential circuits especially for single-chip microcomputers, microprocessors and LSls for peripheral
circuits has been discussed internationally in the TC47
of the International Electrotechnical Committee (IEC).
Finally the IEC has decided on the meeting of TC47 in
February 1980 that this system of letter symbols will be
a Central Office document and circulated to all countries
to vote which means this system of letter symbols wi II
be a international standard.
The system is applied in this LSI data book for the
new products only. Future editions of this data book
will be applied this system. The I EC document which
describes "Letter symbols for dynamic parameters of
sequential integrated circuits, including memories" is
introduced below. In this data book, the dynamic parameters in the I EC document are applied to timing
requirements and switching characteristics.

2. LETTER SYMBOLS

Note 1 SubSCripts A to F may each conSists of one or more1ietters

2 Subscripts 0 and E are not used for tranSition times
3 The "-"

In

the symbol (1) above IS used to Indicate "to", hence the sym·

bol represents the time Interval from Signal event B occurlng to slqnal
event

0 occunng, and

It IS Important to note that thiS convention IS used

for all dynamiC parameters Including hold times Where no rnl$understarldlng can occur the hyphen may be omitted

2.2. Abbreviated Form

The system of letter symbols outlined in this document
enables symbols to be generated for the dynamic parameters of complex sequential circuits, including memories, and also allows these symbols to be abbreviated to
simple mnemonic symbols when no ambiguity is likely
to arise.

2.1. General Form
The dynamic parameters are represented by a general
symbol of the form:
tA(BC-DC)F

Subscript D indicates the name of the signal or terminal
for which a change of state or level (or
establ ishment of a state or level) constitutes a signal event assumed to occur last,
that is, at the end of the time interval. If
this event actually occurs first, that is, at
the beginning of the time interval, the
value of the time interval is negative.
Subscript E indicates the direction of the transition
and/or the final state or level of the signal
represented by D. When two letters are
used, the initial state or level is also indicated.
Subscript F indicates additional informatioh such as
mode of operation, test conditions, etc.

The general symbol given above may be abbreviated
when no misunderstanding is likely to arise. For' example
to:

or

tA(B)

or

tA(D)

often used for hold times

or

tAF

no brackets are used in this case

or

tA

or

tBC-DE

..................................... (1)

often used for unclassified time
intervals

where:
Subscript A indicates the type of dynamic parameter
being represented, for example; cycle
time, setup time, enable time, etc.
Subscript B indicates the name of the signal or terminal
for which a change of state or level (or
establishment of a state or level) constitutes a signal event assumed to occur
first, that is, at the beginning of the time
interval. If this event actually occurs last,
that is, at the end of the time interval,
the value of the time interval is negative.
Subscript C indicates the direction of the transition
and/or the final state or level of the signal
represented by B. When two letters are
used, the initial state or level is also indicated.

1-16

2.3. Allocation of Subscripts
In allocating letter symbols for the subscripts, the most
commonly used subscripts are given single letters where
practicable and those less commonly used are designated
by up to three letters. As far as possible, some form of
mnemonic representation is used. Longer letter symbols
may be used for specialised signals or terminals if this
aids understanding.

3. SUBSCRIPT A
(For Type of Dynamic Parameter)
The subscript A represents the type of dynamic parameter to be designated by the symbol and, for memories, the parameters may be divided into tv~/O classes:
a) those that are timing requirements for the memory
and

•
MITSUBISHI
"-ELECTRIC

MITSUBISHI LSls

. LETTER SYMBOLS FOR THE DYNAMIC PARAMETERS

6. SUBSCRIPT F. (For Additional Information)
If necessary, subscript F is used to represent any additional qualification of the parameter such as mode of
operation, test conditions, etc. The letter symbols for
subscript F are given below.
Subscript F should be in upper-case.
Modes of operation
Power-down
Page-mode read
Page-mode write
Read
Refresh
Read-modify-write
Read-write
Write

1-18

Subscript
PD
PGR
PGW
R
RF
RMW
RW
W

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MITSUBISHI
. . . . ELECTRIC

MITSUBISHI LSls

SYMBOLOGY

New symbol

Parameter-definition

Former symbol

td

Delay time-the time between the specified reference pOints on two pulses

td(¢)

Delay time between clock p'ulses-e g. symbology. delay time, clock 1 to clock 2 or clock 2 to clock 1

Delay time, column address strobe to row address strobe

td (CAS-RAS)
td (CAS-W)

td (CAS WR)

Delay time, column address strobe to write

Delay time, row address strobe to column address strobe

td (RAS-CAS)
td (RAS-W)

td(RAS-WR)

Delay time, row address strobe to wnte

tdls (R-O)

tdls (R-DA)

Output disable time after read

tdIS(S)

tpXZ(CS)

tdIS(W)

tPXZ(WR)

, Output disable time after chip select

Output disable time after write

tDHL

High-level to lOW-level delay time} -the time Interval between speCified reference POints on the Input and on the output pulses. when the

tDLH

LOW-level to high-level delay time

output IS gOing to the low (high) level and when the deVice IS dnven and loaded by specified networks

Output enable time after address

ten(A-Q)

tPZV(A-DQ)

ten(R-Q)

tPZV(R-DQ)

Output enable time after read

ten(S-Q)

t PZX (CS-DQ)

Output enable time after chip select

tf

Fail time

th

Hold time-the Interval time dunng which a slgndl at a specified Input terminal after an actIVe tranSition occurs at another speCified Input terminal

theA)

th(AD)

Address hold time

theA-E)

th(AD-GE)

Chip enable hold time after address

theA-PRj

th(AD-PRO)

Program hold time after address
Column address hold time after column address strobe

th(CAS-CA)
th(CAS-D)

th(CAS-DA)

Data-In hold time after column address strobe

th(CAS-Q)

th (CAS-OUT)

Data-out hold time after column address strobe
Row address strobe hold time after column address strobe

th (CAS-RAS)
th(CAS-W)

t h (CAS-WR)

Write hold time after column address strobe

th(D)

th(DA)

Data-In hold time

th(D-PR)

theDA-PRO)

Program hold time after data-m

theE)

th(CE)

Chip enable hold time

theE-D)

th(CE-DA)

Data-In hold time after chip enable

theE-G)

th(CE-OE)

Output enable hold time after chip enable

th(R)

th(RD)

Read hold time

th(RAS-CA)

Column address hold time after row address strobe

t h(RAS-CAS)

Column address strobe hold time after row address strobe
Data-In hold time after row address strobe

th(RAS-D)

th(RAS-DA)

th(RAS-W)

th(RAS-WR)

Write hold time after row address strobe

th(S)

th(CS)

Chip select hold time

thew)

th(WR)

Wnte hold time

th(W-CAS)

th(WR-CAS)

Column address strobe hold time after write

theW-D)

th(WR-DA)

Data-In hold time after write

th (W-RAS)

th(WR-RAS)

Row address hold time after wflte

tPHL

High-level to low-level propagation time

tpLH

Low-level to high-level propagation time

}

the time Interval between specified reference pOints on the Input and on the output pulses when the
output IS gOing to the low (high) level and when the deVice IS dnven and loaded ,by tYPical deVices
of stated type

Rise time

tr
trec(w)

twr

Write recovery time-the time Interval between the termination of a write pulse and the Initiation of a new cycle

treC(PD)

tR(PD)

Power-down recovery time
Setup time-the time Interval between the application of a Signal which IS maintained at a speCilfed Input terminal and a consecutive active

tsu

tarnSltlon at another speCified Input terminal

tSU(A)

tSU(AD)

Address setup time

tsu (A-E)

tsu (AD-CE)

Chip enable setup time before address

tsu (A-W)

tsu (AD-WR)

tsu (CA-RAS)

1-20

Write setup time before address
Row address strobe setup time before column address

•
MITSUBISHI
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MITSUBISHI MICROPROCESSOR AND PERIPHERAL CIRCUITS ICs

QUALITY ASSURANCE AND RELIABILITY TESTING

1

INTRODUCTION

(3)

IC & LSI have made rapid technical progress in electrical
performances of high integration, high speed, and sophisticated functionality. And now they have got boundless wider
applications in electronic systems and electrical appliances.
To meet the above trend of expanding utilization of IC &
LSI, Mitsubishi considers that it, is extremely important to
supply stable quality and high reliable products to customers.
Mitsubishi Electric places great emphasis on quality as a
basic policy "Quality First", and has striven always to improve quality and reliability.
Mitsubishi has already developed the Quality Assurance
System covering design, manufacturing, inventory and delivery for IC & LSI, and has supplied highly reliable products to customers for many years. The following articles
describe the Quality Assurance System and examples of
reliability control for Mitsubishi Microprocessor and
Peripheral Circuits ICs.

2.

QUALITY ASSURANCE SYSTEM

The Quality Assurance System places emphasis on built-in
reliability in designing and built-in quality in manufacturing.
The System from development to delivery is summarized in
Figure 1.

2.1

Quality Assurance in Designing

The following steps are applied in the designing stage for a
new product.
(1). Setting of perfomance, quality and reliability target for
new product.
(2) Discussion of performance and quality for circuit design, device structure, process, material and package.
(3) Verification of design by CAD system to meet standardized design rule.
(4) Functional evaluation for bread-board device to confirm
electrical performance.
(5) Reliability evaluation for TEG (Test Element Group)
chip to detect basic failure mode and investigate failure machanism.
(6) Reliability test (In-house qualification) for new product
to confirm quality and reliability target.
(7) Decision of pre-production from the standpoint of performance, reliability,' production flow/conditions, production capability, delivery and etc.

2.2

2.3

Reliability Test

To verify the reliability of a product as described in the Mitsubishi Quality Assurance System, reliability tests are performed at three different stages : new product development, pre-production, and mass-production.
At the development of a new product the reliability test
plan is fixed corresponding to the quality and reliability
target of each product, respectively. The test plan includes
in-house qualification test, and TEG evaluation, if necessary. TEG chips are designed and prepared for new device
structure, new process and new material.
After the proto-type product has passed the. in-house qualIfication test, the product advances to the pre-production. In
the pre-production stage, the specific reliability tests are
programmed and performed again to verify the quality of
pre-production product.
In the mass production, the reliability tests are performed
periodically to confirm the quality of the mass production
product according to the quality assurance test program.

Table 1

TYPICAL RELIABILITY TEST PROGRAM
FOR PLASTIC ENCAPSULATED IC & LSI
Test

Group

1
2
3

4

Test condition

Solderability

230"C,5sec

Soldering heal

260"C, 10sec

Thermal shock

-55"C, 125"C , l5cycles

ROSin

flux

Temperature cycling

-65"C, 150"C, 100cycles

Lead fatigue

250gr, 90·, 2arcs

Shock

1500G, O. 5msec

Vibration

20G,100-2000Hz
X, Y, Z direction
4mln Icycle, 4cycles/dtrection

Constant acceleration

20000G, Y direction, 1min

5

Dynamic operation life

T a- Toprmax, Vccmax
1000hours

6

High temperature.
storage life

T a =150"C,1000hours

High temperature and
high humidity

85"C, 85%, 1000hours

Pressure cooker

121'C, 100%, 100hours

Quality Assurance in Manufacturing

Quality assurance in manufacturing is performed as follows
(1) Environment control such as temperature, humidity and
dust as well as deionized water and utility gases.
(2) Maintenance and calibration control for automatized
manufacturing eqUipment, automatic testing equipment,
and measuring instruments.

1-22

Material control such as silicon wafer, lead frame,
packaging material, mask and chemicals.
(4) In-process inspections" in wafer-fabrication, assembly
and testing.
(5) 100% final inspection of electrical characteristics,
visual inspection and burn-in, if necessary.
(6) Quality assurance test
-Electrical characteristics and visual inspection, lot by
lot sampling
-Environment and endurance test, periodical sampling.
(7) Inventory and shipping control, such as storage environment, date code identification, handling and ESD
(Electro Static Discharge) preventive procedure.

7

• MITSUBISHI
""ELECTRIC

MITSUBISHI MICROPROCESSOR AND PERIPHERAL CIRCUITS ICs

QUALITY ASSURANCE AND RELIABILITY TESTING

Table 1 shows an example of reliability test program for
plastic encapsulated Ie & LSI.

2.4 Returned Product Control
When
failed
sales
quest

failure analysis is requested by a customer, the
devices are returned to Mltsublshl Electric via the
office of Mitsubishi using the form of "Analysis Reof Returned Product"

Mitsubishi provides various failure analysis equipment to
analyze the returned product. A failure analysis report is
generated to the customer upon completion of the analysis.
The failure analysis result enforces taking corrective action
for the design, fabrication, assembly or testing of the product to improve reliability and realize lower failure rate.
Figure 2 shows the procedure of returned product control
from customer.

FAILURE ANALYSIS

r-------------------,

ELECTRICAL
CHARACTERISTICS TEST
CLASSIFICATION OF
FAILURE MODES

z
,---------~~~~~§
w

Ul

II:

INTERNAL VISUAL
INSPECTION

CHIP ANALYSIS

~CE!'~A.!:!.CE

REJECTION
________ _

I'
I
-,__-___- __- __...J______--fr

CON'FiRMATiONOF-~

L_~I~REC~U~ _ _ ..J

SURVEY OF
PROCESS RECORD

NO GO

,
Fig.2

1-24

PROCEDURE OF RETURNED PRODUCT CONTROL

• MITSUBISHI
"ELECTRIC

MITSUBISHI MICROPROCESSOR AND PERIPHERAL CIRCUITS ICs

QUALITY ASSURANCE AND RELIABILITY TESTING

Table 4

MECHANICAL TEST RESULTS

~-:,::::
Package Pin Count

4

Solderability

Lead Fatigue

See Table 1

See Table 1

Shock
Vibration
Constant Acceleration
See Table 1

Type Number'" Number of Samples Number of Failures Number of Samples Number of Failures Number of Samples Number of Failures

24P4

M5LB253P-5

2BP4

M5LB251AP-5
M5LB259AP

40P4

M5LBOB5AP
M5LB255AP-5

60
30
30
30
30

2BP2W

M5MB259AFP

15

40P2W

M5M82C55AFP-5

15

0
0
0
0
0
0
0

30
30

22

15

0
0
0
0
0
0

15

0

22

15

30
30

22
22
22
22
22

0
0
0
0
0
0
0

FAILURE ANALYSIS

Accelerated reliability tests are applied to observe failures
casued by temperature, voltage, humidity, current, mechanical stress and those combined stresses on chips and
packages
Examples of typical failure modes are shown below.
(1) Wire Bonding Failure by Thermal Stress
Figure 3, Figure 4 and Figure 5 are examples of a failure which occurs by high temperature storage test of
225"C, 1000hours.
Au-AI
Intermetallic formation, so-called "Purple
plague", by thermal overstress makes Au wire lift off
from aluminum metallization. The activation energy of
this failure mode is estimated at approximately 1.0eV
and no failure has been observed so far in practical
uses.

(2)

Aluminum Corrosion Failure by Temperature/Humidity
Stress.
Figure 6, Figure 7 and Figure 8 are examples of corroded failure of aluminum metallization of plastic encapsulated IC after accelerated temperature/humidity
storage test (pressure cooker test) of 121"C, 100% RH,
1000hours duration.
Aluminum bonding pad is dissolved by penetrated water from plastic package, and chlorine concentration is
observed on corroded aluminum bonding pad as shown
in Figure 8.

Fig.3
Micrograph of
lifted Au ball trace
on AI bonding pad

Fig.6
Micrograph of corroded
Aluminum metallization
(3)

Flg.4
Au-AI plague formation
on bonding pad

1-26

Fig.5
Lifted Au wire ball base

Destructive Failure by Electrical Overstress
Surge voltage marginal tests have been performed to
reproduce the electrical overstress failure in field uses.
Figure 9 and Figure 10 are examples of failure
observed by surge voltage test. The trace of destruction is verified as the aluminum bridge by X ray micro
analysis.

• MITSUBISHI
;"ELECTRIC

MITSUBISHI LSls

PRECAUTIONS IN HANDLING MOS ICs

A MOS transistor has a very thin oxide insulator under the

ing personnel should be grounded. Work tables should

gate electrode on the silicon substrate. It is operated by

be covered with copper or aluminum plates of good

altering the conductance (gm) between source and drain to

conductivity, and grounded. One method of grounding

control mobile charges in the channel formed by the
appl ied gate voltage.

difference with electrical equipment, is by the use of a

If a high voltage were applied to a gate terminal, the

wristwatch metallic ring, etc. attached around the wrist

insulator-film under the gate electrode could be destroyed,

and grounded in series with a 1M .\1 resistor. Be sure that

and all Mitsubishl MOS IC/lSls contain internal protection
circuits at each input terminal to prevent this. It is inherently necessary to apply reverse bias to The P-N junctions of a
MOS IC/lSI.

personnel, after making sure that there is no potential

the grounding meets national regulations on personnel
safety.
2. Current

leakage from

electriC equipment must be

prevented not only for personnel safety, but also to

Under certain conditions, however, it may be impossible

avert the destruction of MOS IC/lSls, as described

to completely avoid destruction of the thin insulator-film

above. Items such as testers, curve-tracers and synchro-

due to the application of unexpectedly high voltage or

scopes must be checked for current leakage before being

thermal

grounded.

destruction due to

excessive current from a

forward biased P-N junction. The following recommendations should be followed in handling MOS devices.

4. PRECAUTIONS FOR MOUNTING OF
MOS IC/LSls

1. KEEPING VOLTAGE AND CURRENT TO
EACH TERMINAL BELOW MAXIMUM
RATINGS

1. The printed wiring lines to input and output terminals

1. The

recommended

ranges

of

operating

conditions

of MOS IC/lSls should not be close to or parallel to
high-voltage or high-power signal lines. Turning power
on while the device IS short-circuited, either by a solder

proVide adequate safety margins. Operating within these

bridge made during assembly or by a probe during

limits will assure maximum equipment performance and

adjusting and testing, may cause maximum ratings to be

quality.

exceeded, which may result in the destruction of the

2. Forward bias should not be applied to any terminal since
excessive current may cause thermal destruction.

device.
2. When inputloutput, or input andlor output, term inals

3. Output terminals should not be connected directly to

of MOS le/lSls (now open-circuits) are connected,

the power supply. Short-circuiting of a terminal to a

we must consider the possibility of current leakage and

power supply having low impedance may cause burn-out

take precautions similar to §2 above. To reduce such

of the internal leads or thermal destruction due to

undesirable trouble, it is recommended that an interface

excessive current.

circuit be inserted at the input or output terminal, or a
resistor with a resistance that does not exceed the

2. KEEPING ALL TERMINALS AT THE
SAME POTENTIAL DURING TRANSPORT
AND STORAGE
When MOS IC/lSls are not in use, both input and output
terminals can be in a very high impedance state so that they
are easily subjected to electrostatic Induction from AC
fields of the surrounding space or from charged objects
in their vicinity. For this reason, MOS IC/lSls should be
protected from electrostatic charges while being transported
and stored by conductive rubber foam, aluminum foil,
shielded boxes or other protective precautions.

output driving capability of the MOS IC/lSI be inserted
between the power supply and the ground.
3. A filter circuit should be inserted in the AC power
supply line to absorb surges which can frequently be
strong enough to destroy aMOS IC/lSI.
4. Terminal connections should be made as described in the
catalog while being careful to meet specifications.
5. Ungrounded metal plates should not be placed near
input or output terminals of any MOS IC/lSls, since
destruction of the insulation may result if they become
electrostatically charged.
6. Equipment cases should provide shielding from electro-

3. KEEPING ELECTRICAL EQUIPMENT,
WORK TABLES AND OPERATING
PERSONNEL AT THE SAME POTENTIAL
1. All electric equipment, work table surfaces and operat-

1-28

static charges for more reliable operation. When a plastic
case is used, it is desirable to coat the inside of the case
with conductive paint and to ground it. This is considered
necessary even for battery-operated equipment.

•
MITSUBISHI
"'ELECTRIC

MITSUBISHI LSls

MSMSOCSSAP-2/FP-21 J-2
CMOS a·BIT PARALLEL MICROPROCESSOR

BLOCK DIAGRAM
AD,

x,

ClK

i--

x,

------«Y-:
Vee

Vss

I

I

8

I

I

I

I

I

I

I

I

H(8)

U8)

0(8)

E(a)

8(8)

C(8)

STACK POINTER (16)

I

I

PROGRAM COUNTER (16)

I

I

I
L_

I

I

I

-~
INTA

I
INTR

RST

5.5

I
RST

RST

7.5

I
TRAP

SOD

HlDA

I READY I

I

.

SID

HOLD

So

101M

6.5

2-4

• MITSUBISHI
...... ELECTRIC

MITSUBISHI LSls

MSM80C8SAP-2/FP-21 J-2
CMOS S-BIT PARALLEL MICROPROCESSOR

PIN DESCRIPTIONS
Pin

X,. X2
RESET OUT
SOD
SID
TRAP
RST5.5
RST6.5
RST7.5

Name

Input or

Functions

output

Clock input

In

Reset output

Out

Serial output data

Out

Serial input data

In

Trap interrupt

In

Restart interrupt
request

In

These pins are used to connect an external crystal to the internal clock generator
An external clock pulse can also be input through Xl
This signal indicates that the CPU is in the reset mode It can be used as a system RESET The signal is synchromsed to the processor clock
This is an output data line for selial data, The output SOD may be set or reset by means of the SIM
Instruction, It returns to high-level after the RESET.

This is an mput data line for senal data, and the data on this line

IS

moved to the 7th bit of the accu-

mulator whenever a RIM Instruction IS executed

A non-maskable restart which

IS

recognized at the same time as an INTR It IS not affected by any

mask or another interrupt It has the highest interrupt priority
Input timing is the same as for INTR for these three signals They all cause an automatic insertion of

an Internal RESTART RST 7.5 has the highest priority while RST 5.5 has the lowest All three slgnals have a higher PriOrity than INTR
This signal is for a general purpose Interrupt and IS sampled only dUring the last clock cycle of the

Interrupt
request signal

INTR

instruction When an interrupt IS acknowledged, the program counter (PC) IS, held and an INTA slg-

In

nal IS generated During this cycle, a RESTART or CALL can be inserted to Jump to an interrupt service routine. The interrupt request may be enable and disable by means of software But It IS disable by the RESET and immeadlately after an accepted Interrupt.

-INTA

Interrupt acknowledge
control signal

Out

ADo-AD 7

Bidirectional address
and data bus

Inlout

Address bus

Out

As-A,5

-

This signal IS used instead of RD dUring the instruction cycle after an INTR is accepted
The low-order (110 address) appears during the first clock cycle' DUring the second and thIrd clock
cycles, It becomes the data bus It remainS In the bus hold state during the HOLD and HALT
modes.

Output the high-order 8 bits of the memory address or the 8 bits of the 1/0 address
It remains in the bus hold state dUring the HOLD and HALT modes.
Indicates the status of the bus

Status

So. S,

Out

HALT
WRITE
READ. DAD
FETCH
The 8, signal can be

S,
0
0

So
0

1
1

0

1
1

-

used as an advanced R/W status

This signal IS generated dUring the first clock cycle, to enable the address to be latched into the latches of

ALE

Address latch enable

Out

WR

Write control

Out

RD

Read control

Out

lo/Kif

Data transfer
control output

Out

peripherals The fall 109 edge of ALE is guaranteed to latch the address information The ALE can also be
used to strobe the status Information, but it IS kept 10 the law-level state dUring bus Idle machine cycles
Indicates that the data on the data bus IS to be written Into the selected memory at the failing edge

of the signal WR It remains the bus hold state during the HOLD and HALT modes
Indicates that the selected memory or 1/0 address IS to be read and that the data bus IS active for
data transfer It remains In the bus hold state dUring the HOLD and HALT modes.
This signal Indicates whether the read/wrlte IS to memory or to I/0s
It remains In the bus hold state dUring the HOLD and HALT modes
When It IS at high-level during a read or wnte cycle, the READY indicates that the memory or

READY

Ready input

In

peripheral IS ready to send or receive date. When the signal IS at low-level, the CPU will walt for the
signal to turn high-level before completing the read or write cycle
This signal (at least three clock cycles are necessary) sets the program counter to zero and resets

RESET IN

Reset input

In

Clock output

Out

Hold
acknowledge signal

Out

the interrupt enable and HLDA flip-flops None of the other flags or registers (except the instruction
register) are affected The CPU IS held m the reset mode as long as the signal is applied

ClK

HlDA

Clock pulses are available from this pin when a cry;:;talls used as an mput to the CPU
By this signal the processor acknowledges the HOLD request signal and mdlcates that It will relinquish the buses In the next clock cycle The signal IS returned to the lOW-level state after the HOLD
request IS completed The processor resumes the use of the buses one half clock cycle after the

signal HLDA gose lOW-level
When the CPU receives a HOLD request It relinqUishes the use of the buses as soon as the current

HOLD

Hold
request signal

In

machme cycle IS completed The CPU can regam the use of buses only after the HOLD state is removed Upon acknowledging the HOLD signal. the address bus. the data bus. RD. WR and 101M
hnes are put

Note

2-6

In

the bus hold state

HOLD. READY and all interrupt signals are synchronous with clock signal

• MITSUBISHI
. . . . ELECTRIC

MITSUBISHI LSls

MSM80C8SAP-2/FP-21 J-2
CMOS 8-BIT PARALLEL MICROPROCESSOR

MACHINE INSTRUCTIONS
ro

~~
Inst

class

0706 050.03

....
•• n

01
01
01
00

DOD
1 1 0
DOD
DOD

MYI

". n

o

0

1 1 0

LXI

•• m

00

000

MOY
MOY
MOY

rl. r2
II ••

MYI

<."
<""

<."


M

M.

M

SP)+l

M.
M,

M,
M,
M.
M.



,
,

M.
M.

M.

1M)


,
,

M.
M.

M

M.

(M)
(82)

,,

M.
M.

M

M.

1M)
(82)

,
,

M.
M.

M

M.

M)

M

M.

(M)

,
,

M.

•
MITSUBISHI
. . . . ELECTRIC

I

M-,-

X

x x x x x
0

00000
X X X 1 X
X X X o X

*

2-8

M,
M,

(82)

••

O.
I
D

I
I

n

Where. M-=(H)(L)

S S •

!lex

M,
M,

o x

X X X o X
X X X 0 X
x
X X X
00000
00000
00000

,

E

I
I

<82)

00000

1 1 0
1 0
1 1 0

H

X X

I~~~~~

1 0
1 0
1 1

I
D

(82)

(82)

n

, NX
INX
I u"X
DCX

M,
M,

X X X X X

H L -(D)(E)
(H) (L) ...... «SP) f-1) (eSp»

000
000
000

:::

I

(L)
(H)

Where. M-=(H) (L)

~~
0:<0

(82)

<83)

M.
M,

(A)'" (A)V(r)
(A) -(A)V(M)
CAl ...... (Al ....... n

fii~

M,
M,

,

m
m+l

1
2

~
(jj:u

(83)

X X X X X

n --

I
1

..

M,

I
I

(m)-(L)
(H)

, ,

' NA

I

(82)

(m)

4
7
7

I~~:

(82)

M.

A E
E E

c

M.
M.
M.

m

2 A

0

X X X

1 1 0
1 1 0

,
M
,

,
,

X X X X X

o 1 0

1 ,

X X X
X X X
X X X
X X X
X X X

S 0 S

, NA

0

(M)

(A)-(m)

(m+

~ ~ ~

X
X
X
X
X
X

1 01
1 o 1
1 01

CM,
C ....
CPO

(d

~gl~~.

(82)

(83)

1 0
1 0
1.1

OA,

M,

x x x x

n

I ~::

M.
M.

Where. m=

1 1 0

M~(H)(L)

X
X
X
X

X

(0)-<82)
(8) ..... (83)

3

o 1 0

ADC
ADC
AC,

~

1 1 0
1 1 0

Mach

S Z P CYzCy, Contents cycle-

1
1
1
2

1 1 1

AD,

$



'0 '0 '0

LOA

LHLD

0>
51

'in

Instruction code
Mnemonic

State IS TI

**

State IS T2

MITSUBISHI LSls

MSM80C8SAP-2/FP-21 J-2
CMOS 8-BIT PARALLEL MICROPROCESSOR

MACHINE INSTRUCTIONS SYMBOL MEANING
Symbol

Meaning

Meanmg

Symbol

Bit pattern

Two"byte data
One·byte data

<62)

Second byte of Instruction

(83)

Third byte 01 Instruction

AAA

Binary representation for AST inStruction n

a-bit data from the most to the least Slgmflcant

555

designating
register or
memory

or

2-10

Program counler

5P

Stack pointer

8
C

D

H

Where

L,
M

M;(H)(L)

A

bit S, Z, X, CY1, 0, P, X, CY2 (X IS Indeflmle)

PC

Data IS transferred

Register
or
memory

E

DDD

Meanmg

Symbol

Register

direction shown
Contents of register or memoy location

555
or

DDD
0 0
o0
0 1
0 1
1 o
1 0
1 1
1 1

0
1
0
1
0
1
0
1

v

...

InclUSive OR

Exclusive OR
Logical AND
1 s complement
Content of flag

0

IS

not changed after execution

Content olflag IS set or reset aller execution
Input mode

0

•
MITSUBISHI
..... ELECTRIC

In

Output mode

MITSUBISHI LSls

MSM80C8SAP-2/FP-21 J-2
CMOS 8-BIT PARALLEL MICROPROCESSOR

ABSOLUTE MAXIMUM RATINGS
Symbol
Input voltage

Vo

Output voltage

IOHMAX

IOLMAX

Ratings

Unit

-0.3-7

V

-0. 3-V ee +0. 3

V

Conditions

Parameter

Supply voltage

Vee
V,

With respect to V55

MAX"H"

All output and I/O pins output

Output current

"H" level and force same current.

MAX"L"

All output and 1/0 pins output

Output current

"L" level and force same current.

Topr

Operating free-air temperature range

Tsto

8torge temperature range

RECOMMENDED OPERATING CONDITIONS

Vee

Supply voltage

Vss

Supply voltage (GND)

4.5

I
I

Nom

I

ELECTRICAL CHARACTERISTICS
Symbol

Min

V

-500

J-lA

2.5

mA

-20-75

"C

-65-150

"c

(Ta=-20-75"Cunless otherwise noted)
Limits

Parameter

Symbol

-0. 3-Vee+0. 3

5
0

I
I

Max
5.5

I

Unit

V
V

(Ta=-20-75t, Vee=5V±10%, Vss=ov. unless otherwise noted)

Parameter

Limits

Test conditions

Min

Typ

Max

V'H

H,gh·level input voltage

2.0

V'L

Low-level input voltage

-0.3

V 1HX

X" X, High·level voltage

4.0

VeC+O.3

V1H(RESIN)

High-level reset input voltage

2.4

Vce+O.3

VIL(RESIN)

Low-level reset input voltage

-0.3

VO H

High·level output voltage

VOL
lee

Low-level output voltage

IOH=-400;.A

2.4

IOH=-20;.A

4.4

VeetO,3
0.8

0.8

0.45
15

Supply current from Vee (HALT)
(Note 1 )

V
V
V
V

V
V

IOL=2mA

Supply current from (Operation)

Unit

V

20

mA

7

10

mA

20

30

J-lA

10

J-lA

Ices

Supply current from Vee (Stand by)

I,

Input leak current

V,=OV, Vee

loz

Off-state output current

Vo=OV-Vee

-10

10

J-lA

ISHH

Input current bus hold high

V,=3.0V

(Note 2 )

-50

-400

J-lA

ISHL

Input current bus hold low

V,=O.8V

(Note 3 )

50

400

J-lA

(Note 4 )

10

pF

(Note 4 )

15

pF

(Note4 )

20

pF

Vcc=,Vss, f= 1MHz

Ci
Co
CliO

Input terminal capacitance

Output terminal capacitance

Input/Output terminal capacitance

25mVrms, Ta=25'C
Vee=Vss, f= 1MHz
25mVrms, Ta=25'C
Vee=Vss, f= 1MHz
25mVrms, Ta=25'C

Note 1 :

-10

Ices should be measured after execution HALT instruction and then fixing clock on Vee or Vss
V,=Vee or Vss, Vee=5, 5V, outputs unloaded.
Note 2 . leHH should be measured after rasing V'N in bushold status to Vee and setting it for 3, OV.
Measurable pins; ADo-AD?, A.-A", RD, WR, 101M
Note 3 : leHL should be measured after lowering V'N in bushold status to Vss and setting it for O. 8V.
Measurable pins; ADo-AD?, A.-A,s, RD, WR, 101M
Note 4 : Unmeasured pins should be connected to Vss.

2-12

• MITSUBISHI
~ELECTRIC

MITSUBISHI LSls

MSMSOCSSAP-2/FP-21 J-2
CMOS 8-BIT PARALLEL MICROPROCESSOR

Parameters described in the timing requirements and
switching characteristics take relevant values in accord-

ance with the relational expression shown in the following
tables when the frequency is varied.

Relational expression with the frequency T (tC(CLK» in the M5M80C85AP-2
nMMING REQUIREMENTS (Ta=-20-75"C, Vcc =5V±10%, Vss=ov, unless. otherwise noted)
Symbol
DA Input setup time

tSU (OA-R'5)

DA Input setup time

tSU(RDY-AO)

READY Input setup time

tSU(OA-ALE)

DA mput setup time

CL = 150pF

SWITCHING CHARACTERISTICS
Symbol

ClK output low-level pulse width

tW(CLK)

ClK output high-level pulse width

Id(Ao-ALE)

Delay lime, address output to ALE signal

td(ALE-AO)

Delay time, ALE signal to address output

tW(ALE)

ALE pulse width

td(ALE-CLK)

Delay time, ALE to ClK

td(ALE-CONT)

Delay lime, ALE to conlrol signal

tOZX(RO-AO)

Address enable time from read

td(CONT-AD)

Address valid time after control signal

Id(oA-wR)

Delay time, data output to WR signal

td(WR-DA)

Delay time WR signal to data output

tW(CONT)

Control signal pulse width

td(CONT-ALE)

Delay time, CONT to ALE signal

Id(cLK-HLoA)

Delay time, ClK to HlDA signal

tOXZ(HLDA-BUS)

Bus disable lime from HlDA

tOZX(HLDA-BUS)

Bus enable time from HLDA

td{ CONT.CONT)

Control signal disable time

Note 6

2-14

Relational expression (Note 6 )

limit

170-(5/2+N)T
150-(3/2+N)T
200 (3/2)T

Min
Min

150-(2+N)T

Min

Min

(Ta=-20-7S'C, Vcc=5V±10%, Vss=ov, unless otherwise noted)

Palameter

tW(CLK)

td(AD-COiiJf)

Test conditions

Parameter

tSU(OA-AO)

Test conditions

I ADo-AD7

I

Ae-A'5

C L=150pF

Relational expression (Note 6 )

Min

(3/2+N)T-70

Min

(1/2)T-40
(3/2+N)T-70
(1/2)T-75
(1/2)T-60
(1/2)T+50
(1/2)T+50
(3/2)T-80

Min

Delay time, address output to control

I

ADo-AD7

T-85

signal

I

Ae-A'5

T-85

N Indicates Ihe total number of walt cycles
T=lc(CLKi

• MITSUBISHI
. . . . ELECTRIC

Limit

(1/2)T-60
(1/2)T-30
(1/2)T-50
(1/2)T-50
(1/2)T-50
(1/2)T-20
(1/2)T-50
(1/2)T-40
(1/2)T-10
(1/2)T-40

Min
Min
Min
Min
Min
Min
Min
Min

Min
Min
Min
Max
Max
Min
Min

MITSUBISHI LSls

MSM80C8SAP-2/FP-21 J-2
CMOS a·BIT PARALLEL MICROPROCESSOR
Hold Cycle

,

T2
CLK

""\

HOLD

Tl

\

I,~
td~

thIHLD-CLKi

HLDA

THOLD

\

/

1

tSUIHLD-CL3

T HOLO

T3

t

\
I

toxz( HLDA- BUS)

tOZX(HLDA-BUS)

. I

I

~~

(ADDRESS, CONTROLS)

BUS

II

I

Interrupt and Hold Cycle

Tl

T2

T3

T5

Ts

T HOLD

As-15

ADo-7

CALL INST
BUS HOLD

ALE

RD

INTR

INTA

tOZX(HLDA-BUS)

,".J:

HOLD

.::.::+_++...:t",hIHLD-CLKi

HLDA

--------------------------~t:tt-D-XZ-IH-L-DA---B-US-i----------~
td(ClK-HLOA)

Clock Output Timing Waveform
Xl INPUT

CLOCK OUTPUT

2-16

• MITSUBISHI
. . . . ELECTRIC

I

Tl

T2

MITSUBISHI LSls

MSM80C8SAP-21 FP-21 J-2
CMOS a-BIT PARALLEL MICROPROCESSOR

DRIVING CIRCUIT OF X1 AND X2 INPUTS
Input terminals, Xl and X2 of the M5M80C85AP-2 can be
driven by either a crystal or external clock. Since the driver
clock frequency is divided to 112 internally, the input frequency required is twice the actual execution frequency
(10MHz for the M5M80C85AP-2 which is operated at 5MHz)

RELATION OF RIM AND SIM INSTRUCTIONS
WITH THE ACCUMULATOR
(SUPPLEMENTARY DESCRIPTION).
The contents of the accumulator after the execution of a
RIM instruction is shown in Fig.7 .

, - - - - - - - - - - - - - S E R I A L INPUT DATA (SID)

1 x,
.---_ _.----'-1

~

±

,--_ _ _ _ _ _ _ STATE OF UNFULFILLED
INTERRUPT REQUEST

~--+----=-1T x,

17.5·STATE OF PENDING
FLIP-FLOP

r

16.5)·STATE OF TERMINALS
15.5 RST 6.5 AND RST 5.5
STATE OF INTERRUPT ENABLE

[

OSCILLATION FREQUENCY
BELOW 10MHz PARALLEL
RESONANT CRYSTAL
OSCILLATOR IS USED

Fig. 5

Connections when crystal is used for X 1 and
X 2 inputs

~

~FLAG

External Clock Driver Circuit
V ,H

;;:

,--------A----.

'CONTENTS OF
ACCUMULATOR

7

Fig.7

1

Relation of the 81M instruction RIM
with the accumulator

O. BVee

The contents of the accumulator after the execution of a
SIM instruction is shown in Fig. 8 .

HIGH TIME;;: 40ns
LOW TIME;;: 40ns

----i

STATE OF INTERRUPT MASK
1 WHEN THE MASK IS SET)

r--- (

, d, d, d IE I.IM7·1M6.5,M5.5,
d. d, d
ISID.•.,7.5.,6.5.,5.5.
2

Fig. 5 is a typical connection diagrams for a crystal respectively.

(1 WHEN ENABLE)

. - - - - - - - - - - - - S E R I A L OUTPUT DATA

~oO-----L-----tX,

, - - - - - - - - - - S O D SET ENABLE
VALUE IN BIT 7 IS TRANSFERRED TO SOD LATCH
WHEN SSE IS 1

MSM80C8SAP-2

. - - - - - - - - - - N O T USED
, - - - - - - - R S T 7.5 PENDING RESET
PENDING FLIP-FLOP OF
RST 7.5 IS RESET WHEN
R7.5 IS 1
.-------MASK SET ENABLE
ENABLES SET IRESET OF MASKS
FOIi BITS 0-2, WHEN MSE IS 1

X,

open

Tl[-[=j

r

WAIT STATE GENERATOR
Fig. 6 shows a typical 1-wait state generator for low speed
RAM and ROM applications.

MASK SET/RESET OF RST7.5
MASK SET IRESET OF RST 6. 5
-MASK SET/RESET OF RST 5. 5
SET=1 INTERRUPT DISABLE
RESET=O INTERRUPT ENABLE

~~~~~.r.r.-~
IlsoolSSEI x IR7.5IMSEIM7.5IM6.5IM5.51~g~~~~TL~-?6R

76543210
M5M80C85AP-2
CLK(OUT)

j
~

I 1

2D 2CK
2Q
M7 4LS7 4P
lRD lCK lQ

( -.lD

1

READY
M5M80C85AP-2

Fig. 8 Relation of the 81M instruction
with the accumulator

1'-

IALEJ
+5V M5MBOC85AP-2

Fig. 6

2-18

I-wait state generator

• MITSUBISHI
...... ELECTRIC

MITSUBISHI LSls

MSLSOSSAP
S·BIT PARALLEL MICROPROCESSOR

PIN DESCRIPTIONS
Pin

X" X2
RESET OUT
SOD
SID
TRAP
RST5.5
RST6,5
RST7.5

Name

Input or

Functions

output

Clock input

In

Reset output

Out

Serial output data

Out

Serial input data

In

Trap interrupt

In

Restart interrupt
request

In

These PinS are used to connect an external crystal or RC

ClfCUlt

to the internal clock generator

An external clock pulse can also be Input through-Xl
This signal Indicates that the CPU IS In the reset mode It can be used as a system RESET The

slg~

nal is synchronised to the processor clock
This IS an output data. Ime for senal data The output SOD may be set or reset by means of the 81M
Instruction It returns to high-level after the RESET

This

IS

an mput data Ime for serial data, and the data on this line

mUlator whenever a RIM instruction

A non-maskable restart which

IS

IS

IS

moved to the 7th bit of the accu-

executed.

recognized at the same time as an INTR It IS not affected by any

mask or another Interrupt It has the highest mterrupt Priority
Input timing IS the same as for INTR for these three signals They all cause an automatic insertion of

an '"ternal RESTART RST 7.5 has the highest Priority while RST 5.5 has the lowest All three slg·
nals have a higher prlonty than INTR
This signal IS for a general purpose Interrupt and IS sampled only dUring the last clock cycle of the
InstructIOn When an Interrupt IS acknowledged, the program counter (PC) IS held and an INTA slg-

Interrupt
request signal

In

-INTA

Interrupt acknowledge
control signal

Out

ADo-AD7

Bidirectional address
and data bus

Inlout

Address bus

Out

INTR

nal IS generated DUring this cycle, a RESTART or CALL can be Inserted to Jump to an Interrupt service routme The Interrupt request may be enable and disable by means of software But It IS disable by the RESET and Immeadlately after an accepted Interrupt

As-A'5

This signal IS used Instead of RD during the instruction cycle after an INTR IS accepted
The low-order (110 address) appears dUring the first clock cycle Dunng the second and third clock
cycles, it becomes the data bus It remains 10 the high-Impedance state dunng the HOLD and HALT
modes
Output the high-order 8 bits of the memory address or the 8 bits of the 1/0 address
It remains In the high-Impedance state dunng the HOLD and HALT modes
Indicates the status of the bus

So, S,

Status

Out

HALT
WRITE
READ, DAD
FETCH

S,
0
0

So
0

,
,, ,
0

-

The 81 signal can be used as an advanced R/W status
This signal IS generated durmg the first clock cycle, to enable the address to be latched mto the latches of

ALE

Address latch enable

Out

WR

Write control

Out

peripherals The failing edge of ALE IS guaranteed to latch the address Information The ALE can also be
used to strobe the status mformatlon, but It IS kept m the low-level state dUring bus Idle machine cycles.

RD
-

101M

Read control

Out

Data transfer
control output

Out

Indicates that the data on the data bus IS to be written IOta the selected memory at the fallmg edge
-

of the signal WR It remains the high-impedance state during the HOLD and HALT modes
Indicates that the selected memory or I/O address IS to be read and that the data bus IS active for
data transfer It remains In the high-Impedance state dUring the HOLD and HALT modes
This signal mdlcates whether the read/wnte IS to memory or to lIDs
It remains In the hlgh-Ipedance state dUring the HOLD and HALT modes
When It IS at hIgh-level dUTIng a read or write cycle, the READY indicates that the memory or

READY

---RESET IN

Ready input

In

penpheral IS ready to send or receive date When the signal IS at low-level, the CPU Will walt for the
signal to turn high-level before completing the read or wnte cycle
ThIs signal (at least three clock cycles are necessary) sets the program counter to zero and resets

Reset input

In

Clock output

Out

Hold
acknowledge Signal

Out

the Interrupt enable and HLOA flip-flops None of the other flags or registers (except the mstructlon
register) are affected The CPU IS held In the reset mode as long as the signal IS applied

ClK

HlDA

Clock pulses are available from this pin when a crystal or RC circuit is used as an Input to the CPU
By thiS signal the processor acknowledges the HOLD request signal and Indicates that It Will rehnqUlsh the buses In the next clock cycle The signal IS returned to the lOW-level state after the HOLD
request IS completed The processor resumes the use of the buses one half clock cycle after the
signal HLDA gose low-level
When the CPU receives a HOLD request It relinquishes the use of the buses as soon as the current

HOLD

Hold
request signal

In

machine cycle IS completed The CPU can regain the use of buses only after the HOLD state is removed Upon acknowledging the HOLD signal, the address bus, the data bus, RD, WR and loiiii!
lines are put In the high-Impedance state

Note

2-20

HOLD, READY and all Interrupt signals are synchronous with clock signal

• MITSUBISHI
"ELECTRIC

MITSUBISHI LSls

MSL808SAP
a-BIT PARALLEL MICROPROCESSOR

MACHINE INSTRUCTIONS
't 10
a a a
~

b>~.em

Instruction code
MnemoniC

In5t;s""class

0106
MOV
MOV
MOV
MYI

rl.n

o

050.03
ODD

'. M
, • n

1
01
01
o 0

MVI

M. n

o

0

LX'

a

.m

o

0

1 1 0

o 0 0

0


1 1 0

3 •

10

2

3

o

o

10

3

3

0 1

1

<82>
LX,

LX,

.

LX,

O.m

H .m

SP,m

o

1 1
0
0
o 0
o 0
o 0



M

M,

(82)

X

x X x

x x x x

(82)

(Llo----(82>
(H) .... 

(83)

m =<83>(82)

(83)

x x x x x

(SP)---m

LDAX 0
SfA
m

o
o

(82)



0

o

c

0

"."



1 1 1

o

1 0

3 A

13

3

4

(Al..-.-(m)

O'

1

<82>
<.. >
o 0

o

1 0

2 2

16

3

5

(m) ....... (L)
(m+1}--(H)

o

1 0

2 A

16

3

5

0 1 1
0 1 1

E a
E 3

4
16

1
1

1
5

4

1

7
7

A A
(Al -- (A) + (M)
(A) 0-- (A) t- n

Where M - (H) (L)

2

1
2
2

1
1
2

1
2
2

(Al -(Al + {rl /- (CY2)
(A} ...· (Al t (M) + (CY2)
(A) ..... (Al I• (CY2)

Where M

,

3
3
3
3

(H) (L) •.. (H) (Ll ' (8) (C)
(H) (L) ..... (H) (L) + (D) (E)

x x

:~: :~: =- :~: :~:: :~iJLl

x x

m

o

SHLD m

o

LHLD m

o

0

1 o 1

LOA

<82>

x x x

m

M.

(m)

,

+1

M.
M,

(Ll
(H)

m
m +1

M.
M,

1m)
(m+ 1)

(SP)
(SP) + 1

M,
M,

«SP) )
(SP +1)

m
m

0
0

<83>

<82)
(83)

XCMG
XTML

I;~~
AD.
AOC
AOC
AC,

,
M
n

,
M
n

1 1
1 1

1 0 1
1 o 0

1 0
1 0
1 1

o
o
o

1 0
1 0
1 1

0 0
0 0
0 0

S!
u

ANA
ANA
AN,

~

~
~

XAA
XAA
XA,

c

~

&~
~."

~~

"'.E

~

~~~
*~~
&8~

,

,
M
n

,
M
n

,

0
0
0
0
1 0
1 0

1 0
1 0
1 1
1 0
1 0
1 1
1 0
1 0
1

,

DAA
DAA
DA,

M
n

CM.
CM.
CPO

M
n

1 0
1 0
1 1

,

o

o NA
, NA
IOCA
~CA

,
,
,
,

NX
NX
NX
NX

IU"X
OCX
OCx
OCX
RLC

,
M

,

M
a,
0
H

S.
a

0
H

s.

1 0
1 0
1 1

0
o 0
0
0
0
0
0
0
o 0
o 0
o 0
o 0
o 0

o
o
o
o
o
o

00 1

o

1 1
1
1 1 1
o 1 0
o 1 0
o 1 0
<82>
o 1 1
o 1 1
o 1 1
<82>
1 o 0
1 o 0
1 o 0
<82>
1 o 1
1 o 1
1 o 1
<82>
1 1 0
1 0
1 1 0
<82>
1 1 1
1 1 1
1 1 1
<82>
ODD
1 1 0

1

o

,

o

0 0
1 1 0
o 0 0
o 1 0
1
.1
o
o
1
1

o

o

0
1 0
0 1

1
o
1
0

1
1
1
0

o
o
o
o

0
0
0
0

1
1
1
1

,

1 1 0
1 1 0

o •

7

2

I2

• E
o E

7
7

1
1
2

1
2
2

(Al ---(A) ~ I. )
(A)-IA) 1M)
(Al -- (Al-

1
2
2 '

(Al <- (A) A(r)
(Al -(A) A(M)
'(A)" (Al A

• ••
1 1 0
1 1 0

Where M

2

(A)<- (AlV(rl
IA) - (A)V(M)
(A) <- (Al...,.. n

Where M

(A) "-'(A) \ (r)
(A)"-'(A)\ (M)
{Al ---(Al \

Where, M

A •
E •

5 5 5
1 1 0
1 1 0

5 5 5
1 1 0
1 1 0

5 5 5
1 1 0
1 1 0
1 o 0
1 o 0
1 o 1
1 0 1
o 1 1
o 1 1
o 1 1
0 1 1
o 1 1
o 1 1
0 1 1
o 1 1
1 1 1

00--1--111

o

AAL

o 0

o

1 0

1 1 1

o

0

o

1 1

1 1 1

o
o
o
o

0
0
0
0

1 o 1
1 o 0
1 1 0
1 1 1

7

a E
F E

3

3

o
1
2
3
o
1
2
3

o

2

7'

1
1

7

2

4

a •
F •

2

j I;
4

A E
E E

,

,
I2

'!

7
7

1
1 I 2
2
2

4

, i 1

7
7

"
2

,

1
10 1
4 I
5
10 1
1
3
6
1
3
6
6
1
3
1
3
1
a
a
1
6
B
6
1
B i ,
1
1
7 i 4

,

4

,,

0.+, ,

2
2
1
3
1
3
1
1
1
1
1
1

,

1
1

1

o<:lc:J

~-

Accumu CMA
campen OAA
Carry se t STC
CMC

1
1
1
1

1
1
1
1

1
1
1
1

1 1

4

1

1

,
, ,
• ,
t-i-i- • 1
1 F

1

1

2 F
2 1

1

1
1

~4

1
1

IA)-(A)
(Al ..-. (Al
IA)-(A)

Ie)
1M)

(H) IL)

(CYz)
(CYzl
(eY2)

,

,

Where M

I Compare, Where

" I

(r) ..... ( r)+ 1
(M) ..... (M)+ 1
(r) ...... ( r) 1
(8) (C) t
(D) (El· (0) (El t
(H) (L). (H) (Ll t
(SPl - (sP) f 1
(8) (c) - (8) (C)
(D) (El <- (0) (E)
(H) (L) <-- (H) ( l l
(sp) <--, (SP)

,

Right shift
(A)-

M

(H) (L)

(H) (L)

(H) (L)

= (H) (L)

(H) (L)

x o

AlAs

A1AO~l

00000
00000
00000

M

000
000
000

0
0
0

1
1
1

M

000
000
000

0
0
0

0
0
0

M

000
000
000

0
0
0

0
0
0

M

00000
00000
00000

M

66-6 x 6
X X X X x

x

X

X

0 X

x

X

X

0 x

CYz~_ _ ~
W

x

x

x o

x

x

x

x

M.
M.

X

M.

,
,

M.
M.

,
,

M.
M.



~~

M

M.

M

M.

,

M.

State

IS T2

1M)

I
.1
I

00000

I

X

ey,

x

•
MITSUBISHI
"-ELECTRIC

,
,

(M)

<8z>

X
x
x
X
X
X
X

~6_.~_.~

M.

,82>

X X 1 X
x x 0 x

--

•

2-22

M.
M.

(82)

X

CYz~----== A1AO_~

x

,
,

(M)

M,
M,

~

M

000 x 0

1

M.

M.
M,

M.
M.

(M)

<8z>

X~x

(H) (Ll

1

M

M.
M,

,
,
,
,

<82>

000001
00000
00000 1

X X X X
x X x X
x x x x
x X x X
x X x x
x X x x
x X X X
x x x v

,
,

X
X
X

Where. M

1

e"G-

x o

x x o

000 x 0
000 x 0

Results 0 blnarv addition are adjusted to B D
CYz (CYz) <-

M.

M

00000
00000
00000

(H) ( l l

1
1
1

Right shift CY2Q _
Left shift

12525252525

M

Where

(M)-(M)~l

Left shift

(H) (L)

"

(8) (e)'

x x x X
x x x x

x X

Where, M

,

(A)
(e)
(Al - (M)
IA)

x
x

x

7

5 ••
1 1 0
1 1 0

1

1
1
1
1

• •• •• •
•

AAC

0

•

1
2 •
3 •

X

00000

(82)

DAD
DAD
DAD
DAD
sua
sua

x

M.

~~

State

IS TI

j--••

~-

MITSUBISHI LSls

MSL808SAP
I-BIT PARALLEL MICROPROCESSOR

MACHINE INSTRUCTIONS SYMBOL MEANING
Symbol

Meaning

Bit pattern

Two-byte data
(82)

60ns

7 are typical connection diagram for a crystal circuit respectively.

M5L8085AP
4700
L.....--4--j

X2

Pullup resistors are required to assure that
the high level voltage of the Input IS at least
4V

OSCILLATION FREQUENCY 1~6MHz PARALLEL
RESONANT CRYSTAL OSCILLATOR IS USED

Fig.

2-32

7 Connections when crystal is used for
Xl and X2 inputs

• MITSUBISHI
..... ELECTRIC

MITSUBISHI LSls

MSL8212P
8- BIT INPUT jOUTPUT PORT WITH 3- STATE OUTPUT

DESCRIPTION
The M5L8212p is an Input/output port consisting of an 8-bit
latch with 3-state output buffers along with control and device selection logic. Also a service request flip-flop for the
generation and control of interrupts to a microprocessor IS
included.

PIN CONFIGURATION (TOP VIEW)

DEVICE SELECT DS, -

•
•
•
•
•
•

vee (5V)

1

-INT ~J~~~grTSIGNAL
22-DI, DATA INPUT

MODE INPUT MD- 2

FEATURES
Parallel 8-blt data register and buffer
Service request flip-flop for interrupt generation
Three-state outputs
Low input load current: I'L =-250,uA( max.)
High output sink current: IOL =16mA(max,)
High-level output voltage for direct interface to a
M5L8085AP, CPU: VoH =3. 65V( min.)

2 -DO, DATA OUTPUT

2 +- DI, DATA INPUT
1 -DO, DATA OUTPUT
1 -DI, DATA INPUT
7-DO, DATA OUTPUT
DATA INPUT DI,- 9
DATA OUTPUT DO,-l
STROBE I NPUT STB -

APPLICATION

16-Dls DATA INPUT

(OV)GND

Input/output port for a M5L8085AP
Latches, gate buffers or multiplexers
Peripheral and input/output functions for microcomputer
systems

FUNCTION

-

11

DOs DATA OUTPUT

-CLR CLEAR

12 _ _ _ _.r - DS, DEVICE SELECT

~

Outline 24P4

Device select 1 (OS,), and device select 2 (OS2) are used
for chip selection when the mode input MO is low. When
OS, is low and OS2 is high, the data in the latches is transferred to the data outputs DO, - DOs, and the service request flip-flop SR is set. Also, the strobed input STS is active, the data inputs 01 , - Dis are latched in the data latches,
and the service request flip-flop SR is reset.

When MO is high, the data in the data latches is transferred to the data outputs. When OS, is low and OS2 is high,
the data inputs are latched in the data latches. The low-level
clear input CLR resets the data latches and sets the service
request flip-flop SR, but the state of the output buffers is not
changed.

BLOCK DIAGRAM

r--------------------.
STROBE INPUT STB
MODE INPUT

11

DEVICE SELECT DS,
DEVICE SELECT

I

INTERRUPT
CONTROL
SIGNAL

Dh

DATA INPUTS

CLEAR

2-34

Diz

5

Db

7

DI,

9

Dis

16

01,

18

DI,

20

01,

22

DATA
OUTPUTS

~------~--------------------_4==i[~F=~-=~~-------------{21

CLR 14

~

I

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _._J

• MITSUBISHI
...... ELECTRIC

DO,

MITSUBISHI LSls

MSL8212P
8-BIT INPUT/OUTPUT PORT WITH 3-STATE OUTPUT

SWITCHING CHARACTERISTICS

(T a=O-75'C, Vee=5V±5%, unless otherwise noted)
Limits

Symbol

Unit

Test conditions (Note 4)

Parameter

Min
tpHL(OI~OO)

High-to-Iow-Ievel and low-to-high-Ievel output propagation

tPLH (Ol-DO)

time, from Input 01 to output DO

Typ

Max

30

ns

40

ns

40

ns

45

ns

45

ns

55

ns

CL =30pF, R,,=300n, R,,=600n

tPHUOS2-DO)

High-to-Iow-Ievel and low-to-hlgh-Ievel output propagatIOn

tPLH (OS2-DO)

time. from input DS1, DS2 and STS to output DO

tPHUSTB-INT)

High-io-iow-ievel output propagation time, from Input STB to output INT

tPZL(MD-DO)

Z-to-Iow-Ievel and Z-to-high-Ievel output propagation

CL =30pF, R,,=300n, R,,=600n

tPZH(MD-DO)

time, from inputs MD, DSl and DS2 to output DO

CL =30pF, R,,=10kn, R,,=lkn

tPHZ(MD-OO)

High-to-Z-Ievel and low-to-Z-Ievel output propagation

C L =5pF, R,,=10kn, R,,=lkn

tPLZ(MD-OO)

time, from inputs MD, DSl and DS2 to output DO

CL =5pF, R,,=300n, R,,=600n

High-to-Iow-Ievel output propagation time, from Input
tPHL(CLR_DO)

C L =30pF. R,,=300n, R,,=600n
CLR to output DO

Note 4:

Test circuit

Vee

T
R"

IN

OUT

RL.2

2-36

• MITSUBISHI
;"ELECTRIC

MITSUBISHI LSls

MSL8216P / MSL8226P
4-BIT PARALLEL BIDIRECTIONAL BUS DRIVERS

DESCRIPTION
The M5LB216P and M5LB226P are 4-bit bidirectional bus
drivers and suitable for the B-bit parallel CPU M5LBOB5AP.

CHIP s~~~8t

FEATURES
•
•
•

•
•

PIN CONFIGURATION (TOP VIEW)

Parallel 8-bit data bus buffer driver
I'L =-500,uA(max.)
Low input current OlEN, CS:
01, DB:
I'L =-250,uA(max.)
High output current M5L8216P
IOL =55mA( max.)
DB:
IOH=-10mA(max.)
IOH=-lmA(max.)
DO:
M5LB226P
DB:
IOL=50mA(max.)
IOH=-10mA(max.)
DO:
IOH=-lmA(max.)
Outputs can be connected with
VoH =3.65V(min.)
the CPU M5LBOB5AP:
Three-state output

cs-

vee

(5V)

DATA OUTPUT 000-

DATA INPUT 010 -

4

12 - 01, DATA INPUT

DATA OUTPUT 00,-

BIDIR6~·no~Ct

DB, -

11 -

002 DATA OUTPUT

DATA INPUT 01, -

10 -

DB2

9 -

012 DATA INPUT

(OV) GND

g~i~E~J~ONAL

Outline 16P4

APPLICATION
Bidirectional bus driver/receiver for various types of microcomputer systems.

FUNCTION
The M5LB216P is a non-inverting and the M5LB226P is an inverting 4-bit bidirectional bus driver.
When the terminal CS is. high-level, all outputs are in
high-impedance state, and when low-level, the direction of
the bidirectional bus can be controlled by the terminal OlEN.

The terminal OlEN controls the data flow. The data flow
control is performed by placing one of a pair of buffers in
high-impedance state and allowing the other to transfer the
data.

BLOCK DIAGRAM

DATA INPUT 010

4}-----n>---+~

DATA INPUT 010

DATA OUTPUT 000 2 )----1--<1-+--'
DATA INPUT Db

7j---+--t::>---+-

DATA OUTPUT DO,

5l---f------+~

DATA OUTPUT 003 14}---+--<:'--+--'

12

DATA OUTPUT 003 14

1

cs

CHIP
SELECT INPUT
ENABLE

I~~~~ 'BiEN

15

M5L8226P

M5L8216P

2-3B

4

DATA OUTPUT 000 2

• MITSUBISHI
..... ELECTRIC

MITSUBISHI LSls

MSL8216P /MSL8226P
4-BIT PARALLEL BIDIRECTIONAL BUS DRIVERS

SWITCHING CHARACTERISTICS
Symbol
tPHL(OB-DO)

tpLH ( DB-DO)
tPHUOI-DB)
tPLH(OI_DB)

tPHZ(cs-oo)

(Vee=5V±5%, Ta=25'C, unless otherwise noted)

Parameter

Test conditions

Hlgh-to-Iow and low-to-hlgh output propagation time.
from input DB to output DO

CL=30pF, RLl=300n, RL2=600n

High-to-Iow and low-to-high, output
propagation time. from Input 01 to
output DB

CL=300pF, RLl=90n, RL2=180n

M5L8216P
M5L8226P

limits
(Note 3)

Min

Typ

25
30
25

CL=5pF, RLl=10kn, RL2=lkn

High-to-Z and low-to-Z output propagation time.
from inputs OlEN CS, to output DO

35

~--

tPLZ(CS-DO)

CL=5pF, RLl=300n, RL2=600n

M5L8216P
tPZHCCS-DO)

Output enable time.

M5L8226P

from inputs OlEN CS to output DO

M5L8216P

tPZL(Cs-DO)

tPHZCCS-OB)
tPLZ(Cs-DB)

54

54
CL=5pF, RLl=10kn, RL2=lkn

OlEN. CS. to output DB

M5L8216P

tPZL(Cs-DB)

65

CL=300pF, RLl=10kn, RL2=lkn

54
65

CL=300pF, RLl=90n, RL2=180n

M5L8226P

TIMING DIAGRAM

35

CL=5pF, RLl=90n, RL2=180n

M5L8216P
M5L8226P

65

CL=30pF, RLl=300n, RL2=600n

Output disable time, from inputs OlEN. CS to
output DB

Output enable time from Inputs

65

CL=30pF, RLl=10kn, RL2=lkn

M5L8226P

tPZHCCS-DB)

Max

54

(Reference level=1.5V)

Note

Unit

ns

ns

ns

ns

ns

ns

ns

ns

3: Test circuit

DBa-DB,
Dlo-DI, - - - - ' "

"--:t-PL-H~(D-B-_-DO-:)-''l"tp-LH-:(-:D-'_-D~B)-:--­

______,,1

Vee

tPHL(OB-DO), tPHUOI-DBJ

000- 00,
DBa-DB, _ _ _ _ _J' ' -_ _ _ _ _ _ _ __

RLl
OUT

tPHZ(CS-DO), tPHZ(Cs-DS)
tPLZ(Cs-DO), tPLZ(Cs-DB)

m-------j'"

DBIN
15

APPLICATION EXAMPLES

4DIDIEN
3
2
DB
7 DO
6
5
9 M5L8216P
OR
11~ M5L8226P

Fig. 1 shows a pair of M5L8216Ps or M5L8226Ps which are
directly connected with the 8080A CPU data bus, and their
control signal. Fig. 2 shows an example circuit in which the
M5L8216P or M5L8226P is used as an interface for memory
and 110 to a bidirectional bus.

13

14

DBa
OB,
DB,
DB,
SYSTEM DATA BUS

8080A

15
DB,
DBs
DB,
13
CS

DB,

BUsrn
Fig. 1

2-40

• MITSUBISHI
~ELECTRIC

Data bus buffer

MITSUBISHI LSls

MSL8282P/MSL8283P
OCTAL LATCH

ABSOLUTE MAXIMUM RATINGS

(T a =0-75'C, unless otherwise noted)

Parameter

Symbol
Vee

Supply voltage

V,

Input voltage

Va

Output voltage

Topr

Operating free-alf temperature range

Tstg_

Storage temperature range

Conditions

RECOMMENDED OPERATING CONDITIONS
Symbol

Unit
V

-0.5-+5.5

V

-0.5- V ee

V

0-+75

"C

-65-+150

"C

(Ta=0-7S"C, unless otherwise noted)
Limits

Parameter

Min

Unit

Nom

Max

5

Vee

Supply voltage

5.5

V

10H

High-level output current

I

VoH ;;,2.4V

0

-5

10L

Low-level output current

I Vo,;i;O.45V

0

32

rnA
rnA

4.5

ELECTRICAL CHARACTERISTICS
Symbol

Ratings
-0.5-+7

(T a=0-7S'C , unless otherwise noted)

Parameter

Limits

Test conditions

V ,H

High-level Input voltage

V IL

Low-level input voltage

Vie

Input clamp voltage

Vcc=4.5V, l,c=-5mA

V OH

High-level output voltage

Vcc=4.5V, IOH=-5mA

VOL

LOW-level output voltage

Vcc=4.5V, 10'=32mA

IOZH

Off-state output current, high-level applied to the output Vcc=5.5V, V,=2V, Vo=5. 25V

IOZL

Off-state output current, low-level applied to the output

Vcc=5.5V, V,=2V, Vo=O. 4V

Min

Typ

Max

2

Unit
V

0.8

V

-1

V

0.45

V

2.4

V

I'H

High-level Input current

Vcc =5. 5V, V,=5. 25V

50

III

LOW-level input current

Vcc=5. 5V, V,=O.45V

-0.2

lee

Supply current

Vcc =5.5V

80

J..) l-MEGABYTE
...
V ADDRESS BUS

~~

~OE

M5L8286P
TRANSCEIVER
' - -_ _,,',
(2)

A

K:=======J16-BIT DATA BUS

(2) Use in the minimum mode

r

Vcc

1

r

rD~

M5L8284AP
MN/MX I---Vcc
CLOCK......
GENERATOR
CLK
MIlO
RES
ro- READY INTA
~ RESET

RDY

T

)CC""'" '"

RD
WR

DT/R
DEN
MELPS 86
CPU

-----1

I
I I
I
I
I
I I

----l

ALE

I
I
A

ADo-AD"
A16 ...... A19

"

,",1\£

SHE I---

r-----'

I

:~

;"DATA "
I
I
I
I

,

STB

I
I
I
I

I

OE
M5L8282P
LATCH
20R3

r

I

:

'\ l-MEGABYTE
ADDRESS BUS

-'-'-"1","":"' - - (

.J

r-----'
----, I

: L_-,~

I I
I I
M5L8286P * I ~

~---tOE

"

•

TRANSCEIVER

(2)

I I

I I
IL _____ .JU

* : Option
Required when the number of devices
driving the bus increases

3-6

" • MITSUBISHI
~ELECTRIC

MITSUBISHI LSls

MSL8284AP
CLOCK GENERATOR AND DRIVER
PIN DESCRIPTIONS
Inpul

Name

Pin

or

Function

Inpul

When AENl and AEN2 are sel low. RDYl and RDY2 are enabled. respecllvely. By using Ihese two inpuls
separately, the CPU can be used to access two Multlbusses. When not used as a multimaster, AEN should

oulpul
AEN1.
AEN2

RDY1.
RDY2

Address enable
Inpul

be set to low. These mputs are active low.
These inputs are connected to the output signal indicating the completion of data reception from a system

Bus ready inpul

Inpul

bus deVice or. indicaling Ihal dala IS valid RDYl and RDY2 are.enabled when AENl and AEN2 are low. respectively. These inputs are active high.
This signal is used to select the synchronization mode of the READY signal generation Circuit. When the

ASYNC

Active low input

Inpul

ASYNC signal Is sel low. Ihe READY signal is generaled 10 two synchronlzalion sleps. When Ihe ASYNC
signal is set high, the READY signal IS generated in one step

READY

Ready oulpul

Oulpul

The state of ROY appears at this output In synchronization with the elK output This is done to synchronize
Ihe READY oulpul 10 Ihe M5L8284AP mlernal clock because Ihe RDY inpul generalion is unrelaled 10 Ihe

CLK signal. This pin IS normally connecled 10 Ihe CPU ready inpul and cleared after Ihe reqUired hold CPU
time has elapsed.
These pins are used to connect the crystal. The crystal frequency is 3 times of CPU clock frequency The

Cryslal elemenl
terminals

Inpul

FIC

Clock seleclion inpul

Inpul

EFI

Exlernal clock inpul

Inpul

ClK

Clock oulpul

X,. X2
-

crystal should be in the 12-25M Hz range with the serres resistance as possible as small. Care should be

laken Ihat Ihese pms are not shorled 10 ground
When FIC is sel low. CLK and PCLK oulpuls are driven from the cryslal oscLlIalor circuli When il is sel
high. Ihey are driven from Ihe EFI mput.
When FIC is sel high, CLK and PCLK oulput signals are driven from Ihls pin. A TTL level reclangular signal
and Ihree limes of Ihe CPU frequency should be used.
This output is connected to the clock in puis of the CPU and the peripheral deVices on the local bus. The

Oulpul

output waveform is 1/3 the frequency of the crystal oscillator connected at Xl and Xl or the signal applied

to Ihe FEI inpul. and has a duly cycle of 1/3. Since for Vcc=5V. VOH=4. 5V. Ihls oulpul can be dlreclly drive
the CPU clock input.

PClK

asc
-RES

RESET

CSYNC

3-8

Peripheral clock
oulpul
Oscilialor oulpul

Resel inpul

Reset output

Clock
input

synchronization

Oulpul

Oulpul

Inpul
Oulpul

This output provides a clock signal for use with peripheral devices. The output waveform is 50% duty cycle
TTL level rectangular waveform with a frequency 1/2 that of the clock output.
Thi~

output is a TTL level crystal oscillator output. The frequency

IS

the same as that of the crystal con-

nected at Xl and X2, but care should be taken as the frequency will be unstable if these pins are left open.
This active low mput is used to generate the reset output signal for the CPU The Input IS a schmitt tngger
input so that by connecting a capacitor and a resistor, the CPU reset signal can be generated at power on.
This pm IS connected to the CPU reset input. The signal at this pin is synchronized the RES input With the

CLK signal. This oulpul is aclive high.
When using multiple M5L8284AP devices. Ihis mpul is used as a clock synchronlZalLon inpul When CSYNC

Inpul

is high. Ihe inlernal counler of Ihe M5L8284AP is resel and when CSYNL LS low. II begins operation. CSYNC
must be synchronized with EFI. See application notes.

•

MITSUBISHI

" " ELECTRIC

MITSUBISHI LSls

MSL8284AP
CLOCK GENERATOR AND DRIVER

SWITCHING CHARACTERISTICS

(Vcc=SV±10%, Ta=O-7S"C, unless otherwise noted)
Alternate

Symbol

Limits

symbol
CLK repetition period

Te

Min

CLK high pulse width

TW0---........

(EFIi

3-14

•
MITSUBISHI
. . . . ELECTRIC

MITSUBISHI LSls

MSL8286P/MSL8287P
OCTAL BUS TRANSCEIVER

DESCRIPTION
The M5L8286P and M5L8287P are semiconductor integrated
circuits consisting of a set of eight 3-state output bus transceivers for use with a variety of microprocessor systems.

PIN CONFIGURATIONS (TOP VIEW)
vee

FEATURES
•

•

3-state, high-fanout outputs (l oL = 16mA, IOH = -1 mA for
the A 'outputs and 10L = 32mA, IOH = - 5mA for the B
outputs)
Low power dissipation

LOCAL BUS
DATA
SYSTEM BUS
DATA

APPLICATION
Two-way bus transceivers for microcomputer systems

OUTPUT
ENABLE INPUT

(ov) GND

FUNCTION
The M5L8286P and M5L8287P are two-way bus transceivers
with non-inverted and inverted outputs respectively.
When the output enable input OE is high, the local bus
data pins Ao - A7 and system data pins Bo - B7 are both
placed in the high-impedance state.
When the output enable input OE is low, the input and
output states are controlled by the transmit input T.
When T is high, Ao-A7 are input pins and Bo-B7 are output pins. When T is low, Bo- B7 are input pins and Ao- A7
are output pins.

11 -T TRANSMIT INPUT

Outline 20P4
vee

LOCAL BUS
DATA
SYSTEM BUS
DATA

OUTPUT
ENABLE INPUT
11 -

(OV) GND

T TRANSMIT INPUT

Outline 20P4

BLOCK DIAGRAM

LOCAL BUS
DATA

SYSTEM BUS
DATA

OUTPUTE~~:b~ OE 9)--~===::::'..l---(1I

LOCAL BUS
DATA

T TRANSMIT INPU,fUTPUT

E~~:M

SYSTEM BUS
DATA

OE

9)---~===:::1-{1I

10 GND (Ov)

M5L8286P

3-16

M5L8287P

• MITSUBISHI
. . . . ELECTRIC

T TRANSMIT INPUT

10 GND (Ov)

MITSUBISHI LSls

MSL8286P/MSL8287P
OCTAL BUS TRANSCEIVER

SWITCHING CHARACTERISTICS
Symbol

t pLH
t pHL
t PZH
t PZL
t pHZ
t pLZ

(Vee=5V±10%, Ta=0-75"C , unless otherwise noted)

Parameter

Alternate

Test

symbol

conditIons

Low-level to high-level and
high-level and low-level
transition time from input A
B to outputs B, A

TIVOV

Output enable time from OE
input to A or B output
mput to A or B output

Symbol

Typ

Min

Unit

Limits

Max

Min

Typ

Max

5

30

5

22

ns

TELOV

10

30

10

30

ns

TEHOZ

5

18

5

18

ns

(Vee=5V±10%, Ta =0-75'C, unless otherwise noted)
Alternate

Parameter

Test conditions

Symbol

tsu

T setup time with respect to DE

TTVFL

th

T hold time with respect to OE

T EHTV

Note 2:

M5L8287P

Limits

(Note 2)

Output disable time from OE

TIMING REQUIREMENTS

M5L8286P

limits

Min

Typ

Max

Unit

10

ns

5

ns

Test Circuit
INPUT

Vee

OUTPUT

1"'-----.,
PG
50n

I
:
DEVICE
: LOAD I
UNDER ~-~-i CIRCUIT:
TEST
: (Note 3):
I
IL

I

_____ .JI

Note 3
Test Item

tpLH , tPHL

tpLZ • tPZL

tpHZ • tPZH

1.5V

1.5V

2.28V

A OUTPUT LOAD CIRCUIT
A OUTPUT

~'''O

A OUTPUT

-to

Il00PF

2.14V

B OUTPUT LOAD CIRCUIT

B OUTPUT

~2m

B OUTPUT

r:300PF

3-18

• MITSUBISHI
..... EI,.ECTRIC

1900n
A OUTPUT--1

r:l00PF

rl00PF

1. 5V

1.5V

~~O
r300PF

B OUTPUT

~"'o
r300PF

MITSUBISHI LSls

MSL8288P
BUS CONTROLLER

DESCRIPTION
The M5L8288P is a semiconductor integrated circuit consisting of a bus controller and bus driver for the M ELPS 86, 88,
l6-bit microprocessors. By using the status signals from the
CPU a Multibus (Intel trademark) control signal is generated.

PIN CONFIGURATION (TOP VIEW)

I/O BUS

~~~~ 10B-

V e d5V)

CLOCK INPUT ClK-

FEATURES

STATUS INPUT

•

~:J~,J~A~JWJ~ DTlR~~~:cnM~~~ AlE-

•
•

High-fanout outputs
Command output 10L =32mA, IOH=-5mA
Control output IOL=16mA, IOH=-lmA
Advanced command outputs (AIOWC
outputs)

and

AMWC

ADDRESS E~~~M

S, -

AEN -

3

16 - DEN DATA ENABLE OUTPUT

15 -CEN ~~~~AND ENABLE
. INTERRUPT
14 -'NTA ACKNOWLEDGE
COMMAND OUTPUT

6

MEMOR6u~~~ MRDC- 7

Low power dissipation

APPLICATION

ADVANCED _ _
MEMORY WRITE AMWC"4COMMAND OUTPUT

13

-'ORcggMR~~2D

COMMJ~N~Rb~~JI

12

-+ AIOWC

Bus controller and bus driver for maximum mode operation
of the MELPS 86, 88

MWTC

~

(OV)GND

11 -IOWC
'--------'

Outline

OUTPUT

¢?R~:~~~MI~~ND
OUTPUT

ggM%~~~ OUTPUT

20P4

FUNCTION
The M5L8288P is a bus controller and driver for maximum
mode operation of theMELPS 86, 88 processors.
The command signals and control signals are decoded
by means of the So-S2 outputs from the CPU and the control signals for I/O devices and memory are output.
The device can be used in the Multimaster mode in
which several CPUs acting as masters are connected to one
data bus. An input pin for the control signal AEN. from an
8289 bus arbiter is provided.
By using the M5L8288P as a bus controller, a highperformanca 16-bit microcomputer system can be configured.

BLOCK DIAGRAM
vee (5V)

r----------------~
I

STATUS INPUTS

r

~

,

7 MRDC MEMORY READ COMMAND OUTPUT

STATUS
DECODER

1

S2

8
COMMAND
SIGNAL

f - - - - - - f GENERATOR

9

iiMWC ~gv,:~~~g ~~~p~~Y WRITE
MWfC MEMORY WRITE COMMAND OUTPUT

11 10WC

I/O WRITE COMMAND OUTPUT

12 AIOWC

~g¥::J;~g g~T~~+TE

13 10RC

I/O READ COMMAND OUTPUT
INTERRUPT ACKNOWLEDGE
COMMAND OUTPUT

1/0 BUS MODE INPUT lOB

I

CLOCK INPUT ClK

2

ADDRESS ENABLE INPUT AEN

6

COMMAND ENABLE INPUT CEN

15

DATA TRANSMIT/RECEIVE OUTPUT
CONTROL I-__~ Cg~~~~L
lOGIC
GENERATOR

DATA ENABLE OUTPUT
16 DEN

17 MCEIPDEN

L _________.___ -4

GND (OV)

3-20

ADDRESS LATCH ENABLE OUTPUT

•
MITSUBISHI
"ELECTRIC

~::'~~~~:LS~~~~ ~~:~t~ ~~i~~r

ge~p~~~D

I

ge~~~~i

MITSUBISHI LSls

MSL8288P
BUS CONTROLLER

FUNCTIONAL DESCRIPTION
The state of the command outputs and control outputs are
determined by the CPU status outputs So - &.1. The table
summarizes the states of the outputs S;; - S2 and their cor-

responding valid command output names.
Depending upon whether the M5L8288S is in the 1/0 bus
mode or system bus mode, the command output sequence
will vary.

STATUS INPUTS AND COMMAND OUTPUTS RELATIONSHIPS
So

8,

So

L

L

L

Interrupt acknowledge

L

L

H

Data read from an I/O port

IORC

L

H

L

Data write to an I/O port

IPWC,AIOWC

L

H

H

Halt

-

H

L

L

Instruction fetch

MRDC

H

L

H

Read data from memory

MRDC

H

H

L

Write data to memory

MWTC,AMWC

H

H

H

Passive state

-

INTA

1. 1/0 bus mode operation
When I~B is high, the M5L8288S function in the 1/0 bus
mode.
----'- - In the 1/0 Bus mode all 1/0 command lines (IORC, 10WC,
AIOWC, INTA) are always enabled (i.e., not dependent on
AEN). When an 1/0 command IS initiated by the processor,
the 8288 immediately activates the command lines using
PDEN and DTiR" to control the 1/0 bus transceiver. The 1/0
command lines should not be used to control the system bus
in this configuration because no arbitration is present. This
mode allows one 8288 Bus Controller to handle two external
busses. No waiting is involved when the CPU wants to gain
access to the 1/0 bus. Normal memory access requires a
"Bus Ready" signal (AEN LOW) before it will proceed. It is
advantageous to use the lOB mode if 1/0 or peripherals dedicated to one processor exist in a multi-processor system.

2.

Valid command output name

8086, 8088 status

3.

AMWC and AIOWC outputs

With respect to the normal write control signals MWTC and
10WC, the advanced-write command signals AMWC and
AIOWC transit low one clock cycle earlier and remain low
for two clock cycles.
These signals are used with peripheral devices or static
RAM devices which require a long write pulse, so that the
CPU does not go into an unnecessarily wait cycle.

System bus mode operation

When lOB is set to low, the M5L8288S enters the system bus
mode. In this mode no command is issued until 115 ns after
the AEN Line is activated (LOW). This mode assumes bus
arbitration logic will inform the bus controller (on the AEN
line) when the bus is free for use. Both memory and 110
commands wait for bus arbitration. This mode is used when
only one bus exists. Here, both 1/0 and memory are shared
by more than one processor.

• MITSUBISHI
l!i-.ELECTRIC

MITSUBISHI LSls

MSL8288P
BUS CONTROLLER

SWITCHING CHARACTERISTICS

Alternate

Symbol
t pLH

t pHL

(Vcc=SV±10%, Ta=0-7S"C, unless otherwise noted)

Parameter
Output

low~level

to

hlgh~level

Test conditions

symbol

Limits
Min

Typ

Max

Unit

propagation time

From elK mput to DEN output

Output hIgh-level to low-level propagation time

TCVNV

5

45

ns

TCVNX

10

45

ns

From elK rnput to PO EN output

t pLH

Output low-level to high-level propagation time
From elK Input to DEN output

t pHL

Output high-level to low-level propagatlOll time
From elK Input to PO EN output
Output low-level to high-level propagation time

TCLLH

20

ns

tpLH

Output low-level to high-level propagalon time
From elK Input to MCE output

TCLMCH

20

ns

t pLH

Output low-level to high-level propagation time
From
rnputs to ALE output

TSVLH

20

ns

t pLH

Output low· level to high-level propagation time
From
Inputs to MCE output

TSVMCH

20

ns

t pHL

Output high-level to low-level propagation time
From ClK Input to ALE output

TCHLL

4

15

ns

t pHL

Output high-level to low-level propagatioo time
From ClK Input to MRDC, IORC, INTA,
AMWC, MWTC, AIOWC, and lowe outputs

TCLML

10

35

ns

t pLH

Output low-level to high-level propagation time
From ClK Input to MRDC, IORC, INTA,
AMWC, MWTC, AIOWC, and IOWC outputs

TCLMH

10

35

ns

t pHL

Output high-level to low· level propagatton time
From ClK Input to DTiR output

TCHDTL

50

ns

t pLH

Output low-level to high-level propagation time
From elK inPut to DT IR output

TCHDTH

30

ns

t PZH

High-level output enable time
From AEN Input to MRDC, lORe, INTA,
AMWC, MWTC, AIOWC, and IOWC outputs

TAELCH

40

ns

t pHZ

High-level output disable time
From AEN Input to MRDC, IORC, INTA,
AMWC, MWTC, AIOWC, and IOWC outputs

TAEHCZ

40

ns

t pHL

Output high-level to low-level propagation time
From AEN Input to MRDC, IORC, INTA,
AMWC, MWTC, AIOWC, and IOWC outputs

TAELCV

200

ns

Output low-level to high-level and high-level to
low-level propagation time
From AEN Input to DEN output

TAEVNV

20

ns

Output low-level to high-level and high· level to
low-level propagation time From CEN Input to
DEN and POEN outputs

TCEVNV

25

ns

Output low-level to high-level and high-level to
low-level propagation time,
From CEN Input to MRDC, IORC, INTA,
AMWC, MWTC, AIOWC and IOWC outputs

TCELRH

35

ns

t pLH

t pLH
t pHL
t pLH

t pHL
t pLH

t pHL

From eLK Input to ALE output

So'-51

SO-s,

TIMING REQUIREMENTS
Symbol

(Note 1)

115

(Vcc=SV±10%, Ta=0-7S"C, unless otherwise noted)

Parameter

Alternate

symbol

Test conditions

Limits
Min

Typ

Max

Umt

te

Clock ClK cycle time

TCLCL

100

ns

tW(CLKU

Clock ClK low pulse width

TCLCH

50

ns

tW(CLKH)

Clock ClK high pulse width

TCHCL

30

ns

TSVCH

35

ns

TCHSV'

10

ns

TSHCL

35

ns

TCLSH

10

ns

80---32 setup time with respect to
tsuCso-Sz)
thCSO-S2)

T for the Tl state

So-&.> hold time with respect to
T for the T4 state
80---32 setup time with respect to

t SU (SO-S2)

T for the T3 state
80---32 hold time with respect to

thCsO-S2)

3-24

T for the T3 state

'MITSUBISHI
..... ELECTRIC

MITSUBISHI LSls

MSL8288P
BUS CONTROLLER

TIMING DIAGRAM
1. Command output timing
T4

STATE

T

r-\
CLK

I

--I

th(So-S,)
(TCHSV)

,

T

tplH .,..

.-

twl elK )

tW(CLKHJ

J!---

(TCHCL) ~WJt
tsu(S,-S,)
thCS,-S,)
1\ (TSVCH)
(TCLSH)

ADDRESS/DATA

(TCLLH)

T3

~::'''Lf' ~

'\

s"s"SQ

ALE

,

te
(TCLCL)

~

ft ~
I ....

~ef*

DATA
VALID

VALID



-AEN)

Propagation time from clock to AEN

200

ns

t pHL (



-AEN)

Propagation time from clock to AEN

130

ns

tpzv(

-A)

Propagation time from clock to address active

170

ns

tpHL(;' -A)

Propagation time from clock to address stable

170

ns

t pVZ (

Propagation time from clock to address floating

90

ns

;'-A)

t pzv( -00)

Propagation time from clock to data bus

200

ns

tpVZ (

Propagation time from clock to data bus

170

ns

tpLH ( (> -AOSTB)

Propagation time from clock to ADSTB

130

ns

tPHL.(;' -ADSTB)

Propagation time from clock to ADSTB

90

ns

tSU(OQ.ADSTB)

Data output setup time before ADSTB

100

th(ADSTB-OQ)

Data output hold time before ADSTB

30

t pzv ( '" -R)
tpzv( -w)

Propagation time from clock to read or write active

-co)



C~=150pF

ns
ns
150

ns

Propagation time from clock to read or write

190

ns

tpLH( I> -R)

Propagation time from clock to read

190

ns

t pLH (

Propagation time from clock to write

130

ns

Propagation time from clock to read or write floating

120

ns

t pHL ('; -R)
t pHL ( I>-W)

I>-w)

t pvz ( I>-R)
t pVZ ( ';-w)

thIA-A)

Address output hold time after read

el' )-100

ns

thIW-A)

Address output hold time after write

tel.,-50

ns

tsU(OQ-MEMW)

Data output setup time before MEMW

125

ns

th(MEMW-OQ)

Data output hold time after MEMW

10

ns

t pHL(

~ -DACK)

Propagallon time from clock to DACK

170

ns

t pHL ('; -EOP)

Propagation time from clock to EOP

170

ns

tpLH( I> -EOP)

Propagation time from clcok to EOP

170

ns

Propagation time from clock to H RQ

120

ns

tpLH ( (> -OACK)

t pLH ( ;. -HRQ)

t pHL (';

Note

4-36

-HRQ)

A.C Testing waveform
Input pulse level
Input pulse rise time
Input pulse fall time
Reference level input
output

O. 45-2. 4V
10ns
10ns
V'H=2V. V'L =0. 8V
VOH=2V. VOL =0. 8V

• MITSUBISHI
;"ELECTRIC

MITSUBISHI LSls

MSM82C37AP-S/FP-S/ J-S
CMOS PROGRAMMABLE DMA CONTROLLER
Slave mode timing (WRITE)

tsu(cs-W)

\

I

tr

tSU(A_W)

}

thlw-Ai

K

ADDRESS VALID

tw(w)

lOW

\
thlw-OQi
tSU(DO-W)

)

4-38

INPUT DATA VALID

•
MITSUBISHI
;"ELECTRIC

f----

K

MITSUBISHI LSls

MSM82C37AP-S/FP-SI J-S
CMOS PROGRAMMABLE DMA CONTROLLER

READY input timing

ClK

READY

( - - - signifies expansion write)

Compressed timing

ClK

READY

4-40

•
MITSUBISHI
. . . . ELECTRIC

MITSUBISHI LSls

MSM82CS1AP/FPI J
CMOS PROGRAMMABLE COMMUNICATION INTERFACE

DESCRIPTION
The M5M82C51 AP is a universal synchronous/asynchronous
receiver/transmitter (USART) IC chip designed for data
communications use. It is produced using the silicon-gate
CMOS process and is mainly used in combination with 8-bit
microprocessors. It is housed in a 28-pin plastic molded
DIP.
And preparatory for surface equipment M5M82C51 AFP
(SOP) and M5M82C51AJ(PLCC).

FEATURES
•
•
•

•
•
•

PIN CONFIGURATION (TOP VIEW)

BIDIRECTIONAL
DATA BUS
RECEIVER-DATA

INPUT

0,-

..... Dl

- 00

-- Rx e

04 05 0, ....
07
TRANSMITTERCLOCK INPUT

~~~';~~~~~PUT

-

s:
01
s:
ex>
N

READ-DATA
CONTROL INPUT

'"IJ

»'"IJ
18

cio-+

Modem control of data communications using microcomputers
Control of CRT, TTY and other terminal equipment

• MITSUBISHI
;"ELECTRIC

~~!~1~JpUT

RESET

RESET INPUT

CLOCK INPUT

-+

TxD 6~~~~M~~~~-

-+

TxEMPTY ET~~~';~~"7~~T

15 -

~i~~~iJ~UT

SO

IBREAK DETECT

TxAOY

OUTPUT
TRANSMITTERREADY OUTPUT

28P4 (M5M82C51AP)
28P2W (M5M82C51AFP)

M5M82C51AJ

FUNCTION

4-42

~~~~~J~~~~

16 ..... SYNDETI f~~tTT ~g~~~~T

o

APPLICATION

RTS

17 -- CTS

AO-

Outline

-+

....- eLK

WR-+

~Eg~~~~PUT

OTR ~:;~yT~~~~~~L

+-

R~~~~16~~-PUTRxRDY --

The M5M82C51 AP is used in the peripheral circuits of a
CPU. It permits assignments, by means of software, of operations in all the currently used serial-data transfer systems.
The M5M82C51 AP receives parallel-format data from the
CPU, converts it into a serial format, and then transmits via
the TxD pin. It also receives data sent in via the RxD pin
from the external circuit, and converts it into a parallel format for sending to the CPU. On receipt of parallel-format
data for transmission from the CPU or serial data for the
CPU from external devices, the M5M82C51 AP informs the
CPU using the TxRDY or RxRDY pin. In addition, the CPU
can read the M5M82C51 AP status at any time. The
M5M82C51 AP can detect the data received for errors and
inform the CPU of the presence of errors as status information. Errors include parity, overrun and frame errors.

BIDIRECTIONAL
DATA BUS

-+

-- DSR

N
0 Q 0
~
~

»"'T1

Tx C -

s:
01
s:
ex>

CHIP-SELECT
INPUT

gg~~=~t/l~~~AT

l

I

Vee (5V)

Ax O -

(OV) Vss

BIDIRECTIONAL
DATA BUS

Single 5V supply voltage
TTL compatible
Synchronous and asynchronous operation
Synchronous:
5~8-bit characters
Internal or external synchronization
Automatic SYNC character insertion
Asynchronous system:
5~8-bit characters
Clock rate~ 1 , 16 or 64 times the baud rate
1 , 1y" or 2 stop bits
False-start-bit detection
Automatic break-state detection
Baud rate: DC~64K-baud
Full duplex, double-buffered transmitter/receiver
Error detection: parity, overrun, and framing

1

103 -

t

t
>- >- 0
0
0
I~
m
0
a:: a:: f::
x
a:: ~ UJ

10

I~

0

Z

>CfJ

Outline

28PO

>f-

a.
::;;
UJ
x
f-

MITSUBISHI LSls

MSM82CS1AP/FPI J
CMOS PROGRAMMABLE COMMUNICATION INTERFACE

OPERATION

M5M82C51AP Access Methods

Table

The M5M82C51 AP interfaces with the system bus as shown
in Fig.l, positioned between the CPU and the modem or
terminal equipment, and offers all the functions required for
data communication.

16

ADDRESS BUS

C/D

RD

WR

cs

Funcllon

L

L

H

L

Data bus - Data in USART
USART - Data bus

L

H

L

L

H

L

H

L

H

H

L

L

Control - Data bus

X

H

H

L

3-State - Data bus

X

X

X

H

3-State - Data bus

Data bus -

Status

Ao

4

CONTROL BUS
CLK
IIOR I/OW RESET

8

DATA BUS

8

CID

CS 0 0 ......... 0 7 RD

WR RESET CLK

M5M82C51AP

Fig, 1

M5M82C51AP interface to CPU system bus

When using the M5M82C51 AP, it is necessary to program,
as the initial setting, assignments for synchronous/asynchronous mode selection, baud rate, character length, parity check, and even/odd parity selection in accordance with
the communication system used. Once programming is
completed, functions appropriate to the communication system can be carried out continuously.
When initial setting of the USART is completed, data communication becomes possible. Though the receiver is always in the enable state, the transmitter is placed in the
transmitter-enable state (TxEN) by a command instruction,
and the application of a low-level signal to the CTS pin
prompts data-transfer start-up. Until this condition is satisfied, transmission is not executed. On receiving data, the
receiver informs the CPU that reading for the receiver data
in the USART by the CPU has become possible (the
RxRDY terminal has turned to high-level) . Since data reception and the entry of the CPU into the data-readable
state are output as status information, the CPU can access
USART status without accessing the RxRDY terminal.
During receiving operation, the USART checks errors and
gives out status information. There are three types of errors:
parity, overrun, and frame. Even though an error occurs, the
USART continues its operations, and the error state is retained until error reset (ER) is effected by a command instruction. The M5M82C51 AP access methods are listed in
Table 1.

4-44

ReadlWrite Control Logic
This logic consists of a control word register and command
word register. It recei·ves signals from the CPU control bus
and generates internal-control signals for the elements.
Modem Control Circuit
This is a general-purpose control-signal circuit designed to
simplify the interface to the modem. Four types of control
signal are available: output signals DTR and RTS are controlled by command instructions, input signal DSR is given
to the CPU as status information and input signal CTS controls direct transmission.
Data-Bus Buffer
This is an 8-bit 3-state bidirectional bus through which control words, command words, status information, and transfer
data are transferred. Fig. 2 shows the structure of the databus buffer.

~D7
100
Do

·l

H
H
y

STATUS BUFFER

l

RECEIVE-DATA.
BUFFER

r

CONTROL BUFFER

Fig. 2

TO INT ERNAL
0 ATA BUS

r

TRANSMIT-DATA ~
BUFFER

r--

Data-bus buffer structure

Transmit Buffer
This buffer converts parallel-format data given to the databus buffer in to serial data with addition of a start bit, stop
bits and a parity bit, and sends out the converted data
through the TxD pin based on the control signal.
Transmit-Control Circuit
This circuit carries out all the controls required for serial
data transmission. It controls transmitter data and outputs
the signals required by external devices in accordance with
the instructions of the read/write control logic.

• MITSUBISHI
"'ELECTRIC

MITSUBISHI LSls

MSM82CS1AP/FP/J
CMOS PROGRAMMABLE COMMUNICATION INTERFACE
Clear-To-Send Input (CTS)
When the TxEN bit (Do) of the command instruction has
been set to 1 and the CTS input is low-level serial data is
sent out from the TxD pin. Usually this is used as a clearto-send signal for the modem
Note: CTS indicates the modem status as follows:
ON means data transmission is possible;
OFF means data transmission is impossible.
Transmitter-Empty Output (TxEMPTY)
When no transmisison characters are left in the transmit
buffer, this pin enters the high-level state. In the asynchronous mode, the following transmission character is shifted
to the transmit buffer when it is loaded from the CPU. Thus,
it is automatically reset. In the synchronous mode, a SYNC
character is loaded automatically on the transmit buffer
when no transfer-data characters are left. In this case,
however, the TxEMPTY does not enter the low-level state
when a SYNC character has been sent out, since TxEMPTY
=" H" denotes the state in which there is no transfer character and one or two SYNC characters are being transferred or the state in which a SYNC character is being transferred as a filler. TxEMPTY is unrelated to the TxEN bit of
the command instruction.
. Transmission-Data Output (TxD)
Parallel-format transmission characters loaded on the
M5M82C51 AP by the CPU are assembled into the format
designated by the mode instruction and sent in serial-data
form via the TxD pin. Data is output, however, only in cases
where the Do bit (T xEN) of the command instruction is 1
and the CTS terminal is in the low-level state. Once reset,
this pin is kept at the mark status (high-level) until the first
character is sent.
Clock Input (ClK)
This system-clock input is required for internal-timing generation and is usually connected to the clock-output (ClK)
pin of the M5l8085AP. Although there is no direct relation
with the data-transfer baud rate, the clock-input (ClK) frequency is more than 30 times the TxC or RxC Input frequency in the case of the synchronous system and more
than 4.5 times in the case of the asynchronous system.
Reset Input (RESET)
Once the USART is shifted to the idle mode by a high-level
input, this state continues until a new control word is set
Since this is a master reset, it is always necessary to load a
control word following the reset process. The reset input
requires a minimum 6-clock pulse width.
Data-Set Ready Input (DSR)
This is a general-purpose input signal, but is usually used
as a data-set ready signal to test modem status. Its status
can be known from the status reading process. The D7 bit
of the status information equals 1 when the DSR pin is in
the low-level state, and 0 when in the high-level state.
DSR="l"-+D7 bit of status information=l
DSR="H"-+D7 bit of status information=O
Note. DSR indicates modem status as follows:

4-46

ON means the modem can transmit and receive;
OFF means it cannot.
Request-To-Send Output (RTS)
This is a general-purpose output signal but is used as a request-to-send signal for the modem. The RTS terminal is
controlled by the D5 bit of the command instruction. When
D5 is equal to 1, RTS="l", and when D5 is 0, RTS="H".
Command register D5=1-+RTS="l"
Command register D5=0-+RTS="H"
Note: RTS controls the modem transmission carrier as follows:
ON means carrier dispatch;
OFF means carrier stop.
Data-Terminal Ready Output (DTR)
This is a general-purpose output signal, but is usually used
as a data-terminal ready or rate-select signal to the modem. The DTR pin is controlled by the DJ bit of the command instruction; if DJ=l, DTR="l", and if DJ=O, DTR=
"H".
DJ of the command register=l-+DTR="l"
DJ of the command register=O-+DTR="H"
Receiver-Clock Input (RxC)
This clock signal controls the baud rate for the sending in
of characters via the RxD pin. The data is shifted in by the
rising edge of the RxC signal. In the synchronous mode, the
RxC frequency is equal to the actual baud rate. In the asynchronous mode, the frequency is specified as 1, 16, or 64
times the baud rate by mode setting. This relationship is
parallel to that of TxC, and in usual communication-line systems the transmission and reception baud rates are equal.
The TxC and RxC terminals are, therefore, used connected
to the same baud-rate generator.

PROGRAMMING
It is necessary for the M5M82C51 AP to have the control
word loaded by the CPU prior to data transfer. This must always be done following any resetting operation (by external RESET pin or command instruction IR). There are two
types of control words: mode instructions specifying general operations required for communications and command
instructions to control the M5M82C51 AP actual operations.
Following the resetting operation, a mode instruction must
be set first. This instruction sets the synchronous or asynchronous system to be used. In the sysnchronous system, a
SYNC character is loaded from the CPU. In the case of the
bi-sync system, however, a second SYNC character must
be loaded in succession.
loading a command instruction makes data transfer possible. This operation after resetting must be carried out for
initializing the M5M82C51 AP. The USART command instruction contains an internal-reset IR instruction (D 6 bit) that
makes it possible to return the M5M82C51 AP to its reset
state. The initialization flowchart is shown in Fig. 3 and the
mode,instruction and command-instruction formats are
shown in Figs. 4 and 5.

•
MITSUBISHI
"-ELECTRIC

MITSUBISHI LSls

MSM82CS1AP/FP/J
CMOS PROGRAMMABLE COMMUNICATION INTERFACE

Asynchronous Transmission Mode
When data characters are loaded on the M5M82C51 AP after initial setting, the USART automatically adds a start bit
(0), an odd or even parity bit specified by the mode in~truction during initialization, and a specified number of
stop bits (1). After that, the assembled data characters are
transferred as serial data via the TxD pin, if transfer is enabled (TxEN=l·CTS="L"). In this case, the transfer data
(baud rate) is shifted by the mode instruction at a rate of
1X, 1f16X, or 1f64X the TxC period.
If the data characters are not loaded on the M5M82C51 AP,
the TxD pin enters a mark state ("H"). When SBRK is programmed by the command instruction, break characters (0)
are output continuously through the TxD pin

Asynchronous Reception Mode
The RxD line usually starts operations in a mark state
("H"), triggered by the falling edge of a low-level pulse
when it comes to this line. This Signal is again strobe at the
middle of the bit to confirm that it is a perfect start bit. The
detection of a second low-level indicates the validity of the
start bit (again strobe is carried out only in the case of 16X
and 64X)
After that, the bit counter inside the
M5M82C51 AP starts operating; each bit of the serial information on the RxD line is shifted in by the riSing edge of
RxC, and the data bit, parity bit (when necessary), and
stop bit are sampled at the middle position.
The occurrence of a parity error causes the setting of a
parity-error flag. If the stop bit is 0, a frame error flag is set.
Attention should be paid to the fact that the receiver requires only one stop bit even though the program has designated 1.5 or 2 stop bits.
Reception up to the stop bit means reception of a complete
character. This character is then transferred to the receiver-data buffer shown in Fig.2, and the RxRDY becomes active. In cases where this character is not read by the CPU
and where the next character is transferred to the receiver-

data buffer, the preceding character is destroyed and an
overrun-error flag is set.
These error flags can be read as the M5M82C51 AP status
information. The occurrence of an error does not stop
USART operations. The error flags are cleared by the ER
(D 4 bit) of the command instruction.
The asynchronous-system transfer formats are shown in
Figs. 6 and 7.

Synchronous Transmission Mode
In this mode the TxD pin remains in the high-level state until initial setting by the CPU is completed. After initialization,
the state of CTS = "L" and TxEN = 1 enables serial transmission of characters through the TxD pin. Then, data characters are sent out and shifted by the falling edge of the
TxC signal. The transmission rate equals the TxC rate.
Thus, once data-character transfer starts, it must continue
through the TxD pin at the same rate as that of TxC. Unless
data characters are provided from the CPU before the
transmitter buffer becomes empty, one or two SYNC characters are automatically output from the TxD pin. In this
case, it should be noted that the TxEMPTY pin enters the
high-level state when there are no data characters left in
the M5M82C51 AP to be transferred, and that the low-level
state is not entered until the USART is provided with the
next data character from the CPlJ. Care should also be
taken over the fact that merely setting a command instruction does not effect SYN C character insertion, because the
SYNC character insertion is enabled after sending out the
first data character.
In this mode, too, break characters are sent out in succession from the TxD pin when SBRK is deSignated (D3=1) by
a command instruction.

CPU-USART (5-S-BIT/CHARACTER)
DATA

CH~RACTER

I

TRANSMITTER DATA OUTPUT (TxD)

USART-CPU (5-S-BIT/CHARACTER)

I

DATA CHARACTER (5-S)

Note

I

When the data character IS 5, 6, or 7 bits/character
length, the unused bits (for USART - CPU) are set to

o
Fig, 6 Asynchronous transmission format I
(transmission)

4-48

Fig,7

•

Asynchronous transmission format II (reception)

MITSUBISHI

~ELECTRIC

MITSUBISHI LSls

MSM82CS1AP/FP/J
CMOS PROGRAMMABLE COMMUNICATION INTERFACE
Status Information

FE:

The CPU can always read USART status by setting the C/O
to high-level and RD to low-level.
The status information format is shown in Fig. 10. In this format RxROY, TxEMPTY and SYNDET have the same definitions as those of the pins. This means that these three
pieces of status information become high-level when each
pin is 1. The other status information is defined as follows:
DSR:
When the OSR pin is in the low-level state, status
information OSR becomes 1.

OE:
PE:
TxRDY:

11

FOR DSR

The occurrence of a frame error in the receiver
section makes the status information FE=l.
The occurrence of an overrun error in the receiver
section makes the status information OE=l.
The occurrence of a parity error in the receiver
section makes this status information PE= 1.
This information becomes 1 when the transmit
data buffer is empty. Be careful because this has
a different meaning from the TxRDY pin that enters the high-level state only when the transmitter
buffer is empty, when the CTS pin is in the lowlevel state, and when TxEN is 1.

"L",Q FOR DSR

"H"

I SAME DEFINITION AS SYNDET/BD PIN
1FE IS SET WHEN A VALID STOP BIT IS NOT DETECTED AT THE END OF EVERY CHAR
1ACTER (ASYNC ONLY) IT IS RESET BY THE ER BIT OF THE COMMAND INSTRUCTION

I

II

FE DOES NOT INHIBIT OPERATION OF THE M5M82C51AP

1g~6~~~1 ~~.J:I~,;~t"E 9m ~~~~P~J f~t~t~~'6Rl{J~IM~3NEi~NEs~~6b~~~
OE DOES NOT INHIBIT OPERATION OF THE M5M82C51AP

_I PE IS SET WHEN

A PARITY ERROR IS DETECTED IT IS RESET BY THE ER BIT OF THE
COMMAND INSTRUCTION PE DOES NOT INHIBIT OPERATION OF THE M5M82C51AP

SAME DEFINITION AS TxEMPTY PIN
SAME DEFINITION AS RxRDY PIN

I I 5~~ I
DSR
D,

Fig. 10

D,

FE
D5

I

OE
D4

I

PE
D3

I

TxE
D,

I

I
=OY
D,

1-----11
I ~OY I

I
I

I

Do

Status information C/D="H", RO="L")

APPLICATION EXAMPLES
Fig. 11 shows an application example for the M5M82C51 AP
in the asynchronous mode. When the port addresses of the
M5M82C51 AP are assumed to be 00 # and 01 # in this figure, initial setting in the asynchronous mode is carried out
in the following manner:
MVI
A,86#
Mode setting
OUT
01 #
Command instruction
MVI
A,27#
OUT
01 #
In this case, the following are set by mode setting:
Asynchronous mode
6-bitlcharacter
Parity enable (even)
1. 5 stop bits
Baud rate: 16X
Command instructions set the following
RTS=l-+RTS pin="L"
RxE=l
DTR=1-+0TR pin="L"
Tx EN =l
When the initial setting is complete, transfer operations are
allowed. The RTS pin is initially set to the low-level by setting RTS to 1, and this serves as a CTS input with TxEN

4-50

FOR TRANSMIT DATA BUFFER IS EMPTY

I
I

being equal to 1. For this reason the same definition applies to the status and pin of TxRDY, and 1 is assigned
when the transmit-data buffer is empty. Actual transfer of
data is carried out in the following way:
IN
01 #
Status read
The IN instruction prompts the CPU to read the USART's
status. The result is; if the TxRDY equals 1 transmitter data
is sent from the CPU and written on the M5M82C51 AP.
Transmitter data is written in the M5M82C51 AP in the following manner:
MVI
A,20#
20'6 is an example of transmitter data.
OUT
00#
USART-(A)
Receiver data is read in the following manner:
IN
00#
(A)+-USART
In the above example, the status information is read and as
a result, the transmitter data is written and read. Interruption processing by using the TxROY and RxRDY pins is also
possible.
Fig. 12 shows the status of the TxD pin when data written in
the USART is transferred from the CPU. When the data
shown in Fig.12 enters the RxD pin, data sent from the
M5M82C51 AP to the CPU becomes 2016 and bits 0 6 and 0 7
are treated as O.

• MITSUBISHI
"ELECTRIC

MITSUBISHI LSI.

MSM82CS1AP/FP/J
CMOS ,PROGRAMMABLE COMMUNICATION INTERFACE

ABSOLUTE MAXIMUM RATINGS
Power.supply

V,

Input voltage

Va

Output voltage

IOHMAX

MAX"H"
Output current

IOLMAX

MAX"L"
Output current

Topr

Operating free-air temperature range

Tstg

Storage temperature range

Ratings

Unit

-0.3-7

V

-0. 3-Vee+0. 3

V

Conditions

Parameter

Symbol
Vee

vo~age

With respect to Vss

-0. 3-Vee+0. 3

V

All output and 1/0 pins output
"H~ level and force same current

-500

p,A

All output and 1/0 pins output
"L" level and force same current

2.5

mA

-20-75

"C

65-150

·c

RECOMMENDED OPERATING CONDITIONS
Parameter

Symbol

Limits

M,n
4.5

Vee

Supply vollage

Vss

Power·supply voltage (GNO)

ELECTRICAL CHARACTERISTICS
Symbol

(Ta=-20-75'C unless otherwise noted)

I
I

Nom

I

0

5

I

Max

I
I

5.5

Unit
V
V

(Ta=-20-75'C, Vcc =5V±10%, Vss=ov unless otherwise noted)

Parameter

Test conditions

L,mns
Min

V'H

High·level input voltage

2.0

V'L

Low·level Input voltage

-0.3

VOH

High·level output voltage

IOH=-400!,A

2.4

IOH=-20!,A

4.4

VOL

Low·level output voltage

IOL-2.2mA

Icc

Supply current from Vce

All outputs are high·level

Typ

Max

Unit

Vcc +O.3

V

0.8

V
V

0.45

V

;'H

High-levellnput current

VI=VCC

-10

I'L
loz

Low-level Input current

V,=OV

-10

10

Off·state Input current

Vo=OV-Vcc

-10.

10

mA
p,A
p,A
p,A

C,

Input term,nal capacitance

Vce=Vss, f=l MHz, 25mV rms , Ta=25'C

10

pF

CliO

Input/output terminal capacitance

Vcc=Vss, f=lMHz, 25mV rms , Ta-25'C

20

pF

4-52

. , MITSUBISHI
"E'-EtTRIC

5
10

MITSUBISHI LSls

MSM82CSIAP/FP/J
CMOS PROGRAMMABLE COMMUNICATION INTERFACE

SWITCHING CHARACTERISTICS
Symbol

(Ta =-20-7S'C, Vcc =5V±10%, Vss=ov unless otherwise noted)
Llm~s

Parameter

tPZV(R-OQ)

Output data enable time after read (Note8)

tPVZ(R-OQ)

Output data disable time after read

tpZVCTxC-TxO)

T XD enable time after falling edge of TxC

tPLH(CLB-TxR)
tPHL.(W-TxR)

Test conditions

Min

CL=150pF

Typ

Max
200(170)

10

Unit
ns

100

ns

1

I-'S

Propagation time from center of last bit to TxROY (Noteg)

8

t C( ~)

Propagation time from write data to TxROY clear (Noteg)

400

ns

tpLH(CLS-RxR)

Propagation time from center of last bit to RxROY (Noteg)

26

t C( ~)

tPHL(R-RxA)

Propagation time from read data to RxROY clear (Noteg)

tPLH(RxC-SYO)

Propagalron time from rising edge of RxC to internal SYNDET (Note9)

26

tPLH(CLB-TxE)

Propagation time from center of last bit to TxEMPTY (Noteg)

20

t C( ~)

tpHL(W-C)

Propagation time from rising edge of WR to control (Noteg)

8

tcU)

400

Note B : Assumes that address is valid before falling edge of RD.
9 : Status-up data can have a maximum delay of 2B clock periods from the event affecting the status.
10: Input pulse level
O. 45-2. 4V
Reference level Input
V ,H =2V, VIL=O.BV
Output VOH=2V. VOL =0. BV
Input pulse rise time IOns
Input pulse fall time IOns
11: M5MB2CSI AP is also invested with the extended specification showed in the brackets.

4-54

• MITSUBISHI
;"ELECTRIC

ns
tC( ~)

MITSUBISHI LSls

MSM82CS1AP/FP/J
CMOS PROGRAMMABLE COMMUNICATION INTERFACE

,

Write Control Cycle (CPU-+USART)

t
C/O

t

ISUIA-W)

I

~

tSUCA-wl

IWlw)

~tSU(OQ_W)

)

0,-00
(DATA INPUT)

~

VAll)

K
tPHL(W_C)

}
Read Control Cycle (USART-+CPU)

Isule R)

}
ISUIA-R)

IhIR_A)

.j

C/O
ISUIA-R)

th(R_A)

IWIR)

.1

-j
tPVZ(R-OQ)

IpZVIR-OQ)

0,-0 0
(DATA OUTPUT)

4-56

iJJ
\\'

• .MITSUBISHI
"'ELECTRIC

~

VALID

\

MITSUBISHI LSls

M5M82C51AP/FP/J
CMOS PROGRAMMABLE COMMUNICATION INTERFACE

Transmitter Control & Flag Timing (Async Mode)
C/O

]

\~~\~[J~~
WR-TxEN

_____
\~/____~__
I ______~I

\

WR-DATA 1 WR-OATA2
WR-DATA3
WR-OATA4
WR-SB_RX
~------~ ~--------~ ~--------------~

r------

TxRDY
(PIN)

TxRDY
(STATUS)

TxEMPTY

TxD
BREAK STATE

Note 12: Example format= 7 bits/character with parity & 2 stop bits
13: TxROY(pin)="H"-(Transmit-data buffer is empty) • (TxEN= 1) • (CTS="L")
14: TxROY(status)= 1 -(Transmit-data buffer is empty)

Receiver Control & Flag Timing (Async Mode)
C/O

.-J ,\. . ____-1\'---11

LD ''-----L..\---L...I_----JJ V '"

__________________~R~D OATrA~I________________~R~D OATrA~3~______~RD~A~LLOrD~A~TA~_______________

WR-Rrx~E_______________+------------------------+----W~R-E~R--------4_-----------W__,R-RxE WR-Rx E

so
(PIN)
OATA2
LOST

rt______1

OE
(STATUS)
RxROY

~

T

Rx O

BREAK STATE

Note 15: Example format= 7 bits/character with parity & 2 stop bits

4-58

S
T

SO:23456PpS0123406Pp

• MITSUBISHI
;"ELECTRIC

MITSUBISHI LSls

MSM82CS4P/FPI J
CMOS PROGRAMMABLE INTERVAL TIMER

DESCRIPTION
The M5M82C54P is a programmable general-purpose timer
device developed by using the silicon-gate CMOS process.
It offers counter and timer functions in systems using an 8bit parallel-processing CPU. The use of the M5MS2C54P
frees the CPU from the execution of looped progra·ms,
count-operation programs and other simple processing involving many repetitive operations, thus contributing to improved system throughputs. It is housed in a 24-pin plastic
molded DIP.
And preparatory for surface equipment M5M82C54FP
(SOp) and M5M82C54J(PLCC).

PIN CONFIGURATION (TOP VIEW)
D7

Vee (5V)

-

23 -

WR WRITE INPUT
READ INPUT

BIDIRECTIONAL
DATA BUS

18 -

CLK2 CLOCK INPUT

17 - OUT2

FEATURES
•
•
•
•
•
•
•
•

CLOCK INPUT CLKO-

Single 5V supply voltage
TTL compatible
Pin connection compatible with M5LS253P-5 (except
M5M82C54J)

cg~~~5~ OUTO _ 10
GATE INPUT GATEO -

Clock period: DC-SMHz
3 independent bUilt,-in 16-bit down counters
6 counter modes freely assignable for each counter
Binary or decimal counts
Read-back command for monitoring the count and
status

11

g~¥~JiR

16 -

GATE2 GATE INPUT

15 -

ClK1 CLOCK INPUT

14 -

GATE1 GATE INPUT
COUNTER
OUTPUT

(OV) Vss

24P4 (M5M82C54P)
24P2W (M5M82C54FP)

Outline

()

Q Q 0- z

f

f

f

>"
"

I~ I~
~

~

APPLICATION
Delayed-time setting, pulse counting and rate generation in
microcomputers.

0

FUNCTION

M5M82C54J

Three independent 16-bit counters allow free programming
based on mode-control instructions from the CPU. When
roughly classified, there are 6 modes (0 - 5). Mode 0 is
mainly used as an interruption timer and event counter,
mode 1 as a digital one-shot, modes 2 and 3 as a rate
generator, mode 4 for a software triggered strobe, and
mode 5 for a hardware triggered strobe.
The count can be monitored and set at any time. Besides
the count, the status of the counter can be monitored by
Read-back command. The counter operates with either the
binary or BCD system.

4-60

NC

• MITSUBISHI
"ELECTRIC

NC

0

f-

:::>

0

0
W

f«
(!)

~

>

()

Z

Outline

t= u:;f-

:::>

0

~

...J

«
(!)

()

28PO
NC : NO CONNECTION

MITSUBISHI LSls

MSM82CS4P/FPI J
CMOS PROGRAMMABLE INTERVAL TIMER

DESCRIPTION OF FUNCTIONS

CONTROL-WORD AND INITIAL-VALUE LOADING

Data-Bus Buffer

The function of the M5M82C54P depends on the system
software. The operational mode of the counters can be
specified by writing control words (AD, A1 = 1, 1) into the
control-word registers.
The programmer must write out to the M5M82C54P the
programmed number of count register bytes (1 or 2) prior
to actually using the selected counter.
Fig. 1 shows control-word format, which consists of 4 fields.
Only the counter selected by the D7 and D6 bits of the control-word is set for operation. Bits D5 and D4 are used for
specifying operations to read values in the counter and to
initialize. Bits D3 ~ D1 are used for mode designation, and
Do for specifying binary or BCD cOl!nting. When Do=O, binary counting is employed, and any number from 000016 to
FFFF16 can be loaded into the count regist~r. The counter
is counted down for each clock. The counting of 0000 16
causes the transmission of a time-out signal from the countoutput pin.
The maximum number of counts is obtained when 0000 16 is
set as the Initial value. When Do = 1, BCD counting is employed, and any number from 000010 to 999910 can be loaded
on the counter.
Neither system resetting nor connecting to the power supply sets the control word to any specific value. Thus to bring
the counters into operation, the above-mentioned control
words for mode designation must be given to each counter,
and then 1 ~ 2 byte initial counter values must be set. The
following is an example of this programming step.
To designate mode 0 for counter 1 ,with initial value 8254 16
set by binary count, the following program is used:
MVI
A, 7016
Control word 70 16
OUT
n1
n1 is control-word-register address
MVI
A,54 16
Low-order 8 bits
OUT
n2 is counter 1 address
A,82 16
MVI
High-order 8 bits
OUT
n2 is counter 1 address
Thus, the program generally has the following sequence:
(1) Control-word output to counter i (i=O, 1,2).
(2) Initialization of low-order 8 counter bits
(3) Initialization of high-order 8 counter bits
The three counters can be executed in any sequence. It is
possible, for instance, to designate the mode of each counter and then load initial values in a different order. Initialization of the counters designated by RL 1 and RL 0 must be
executed in the order of the low-order 8 bits and then the
high-order 8 bits for the counter in question.

This 3-state, bidirectional, 8-bit buffer is used to interface
the M5M82C54P to the system-side data bus. Transmission
and reception of all the data including control words for
mode designation and values written in, and read from, the
counters are carried out through this buffer.

ReadIWrite Logic
The read/write logic accepts control signals (RD, WR)
from the system and generates control signals for each
counter. It is enabled or disabled by the chip-select signal
(CS); if CS is at the high-level the data-bus buffer enters a
floating (high-impedance) state.

Read Input (RD)
The count of the counter designated by address inputs Ao
and A1 on the low-level is output to the data bus.

Write Input (WR)
Data on the data bus is written in the counter or controlword register designated by address inputs AD and A1 on
the low-level.

Address Inputs

(An, A 1 )

These are used for selecting one of the 3 internal counters
and either of the control-word registers.

Chip-Select Input (CS)
A low-level on this input enables the M5M82C54P. Changes
in the level of the CS input have no effect on the operation
of the counters.

Control-Word Register
This register stores information required to give instructions
about operational modes and to select binary or BCD
counting. It allows reading,using Read back command.

Counters 0,1 and 2
These counters are identical in operation and independent
of each other. Each is a 16-bit, presettable, down counter,
and has clock-input, gate-input and output pins. The counter can operate in either binary or BCD using the falling
edge of each clock. The mode of counter operation and the
initial value from which to start counting can be designated
by software. The count can be read by input instruction at
any time, and there is a "read-on-the-fly" function which
enables stable reading by latching each instantaneous
count to the registers by a special counter-latch instruction.

4-62

•
MITSUBISHI
. . . . ELECTRIC

"2
"2

MITSUBISHI LSls

MSM82CS4P/FP/J
CMOS PROGRAMMABLE INTERVAL TIMER

MODE DEFINITIOf\i

Mode 4 (Software Triggered Strobe)

Mode 0 (Interrupt on Terminal Count)

After the mode is set, the output will be high-level. By loading a number on the counter, however, clock-input counts
can be started and on the terminal count, the output will go
lOW-level for one input-clock period and then will go highlevel again. Mode 4 differs from Mode 2 in that pulses are
not output repeatedly with the same set count. The pulse
output is delayed one clock period in Mode 2, as shown in
Fig. 6 . When a new value is loaded into the count register
during its count operation, it is reflected on the next pulse
output without affecting the current count. The count will be
inhibited while the gate input is low-level.

Mode set and initialization cause the counter output to go
low-level (see Fig. 2 ). When the counter is loaded with an
initial value, it will start counting the clock input. When the
terminal count is reached, the output will go high-level and
remain high-level until the selected count register is reloaded with the mode. This mode can be used when the
CPU is to be interrupted after a certain period or at the
time of counting up.
Fig. 2 shows a setting of 4 as the initial value. If gate input
goes low-level, counting is inhibited for the duration of the
low-level period.
Reloading of the initial value during count operation will
stop counting by the loading of the first byte and start the
new count by the loading of the second byte.

Mode 1 (Programmable One-Shot)
The gate input functions as a trigger input. A gate-input rising edge causes the generation of low-level one-shot output with a predetermined clock length starting from the
next clock. Fig. 3 shows an initial setting of 4. While the
counter output is at the lOW-level (during one-shot), loading
of a new value does not change the one-shot pulse width,
which has already been output. The current count can be
read at any time without affecting the width of the one-shot
pulse being output. This mode permits retriggering.

Mode 2 (Rate Generator)
Low-level pulses during one clock operation are generated
from the counter output at a rate of one per n clock inputs
(where n is the value initially set for the counter). When a
new value is loaded during the counter operation, it is reflected on the output after the pulses by the current count
have been output. In the example shown in Fig. 4 , n is
given as 4 at the outset and is then changed to 3.
In this mode, the gate input provides a reset function. While
it is on the loW-level, the output is maintained high-level;
the counter restarts from the initial value, triggered by a rising gate-input edge. This gate input, therefore, makes
possible external synchronization of the counter by hardware.
After the mode is set, the counter does not start counting
until the rate n is loaded into the count register, with the
counter output remaining at the high-level.

Mode 5 (Hardware Triggered Strobe)
This is a variation of Mode 1. The gate input provides a
trigger function, and the count is started by its rising edge.
On the terminal count, the counter output goes low for on
one clock period and then goes high-level. As in Mode 1,
retriggering by the gate input is possible. An example of
timing in Mode 5 is shown in Fig. 7 .
As mentioned above, the gate input plays different roles
according to the mode. The functions are summarized in
Table 3.

Table

~
Mode

a

Low-level
or
going lOW-level

2

Rismg

High-level

Enables
counting

Disables counting
(1) Initiates counting
(2) Resets output
after next clock

1

(1) Disables counting

(1) Reloads counter

Enables

(2) Sets output high

(2) Initiates counting

counting

(1) Reloads counter
(2) Initiates counting

Enables
counting

immediately

3

(1) Disables counting
(2) Sets output high
immediately

4

Disables counting

5

Mode 3 (Square Rate Generator)
This is similar to Mode 2 except that it outputs a square
wave with the half count of the set rate. When the set value
n is odd, the square-wave output will be high-level for (n+
1) 12 clock-input counts and low for (n-1 ) 12 counts. When
a new rate is reloaded into the count register during its operation, it is immediately reflected on the count directly following the output transition (high-to-Iow or low-to-high) of
the current count. Gate-input operations are exactly the
same as in Mode 2. Fig. 5 shows an example of Mode 3 operation.

4-64

2 Gate Operations

• MITSUBISHI
"'ELECTRIC

Enables
counting
Initiates counting

MITSUBISHI LSls

MSM82CS4P/FPI J
CMOS PROGRAMMABLE INTERVAL TIMER

READ BACK COMMAND
M5M82C54P has a function of reading not only the count but
also status (Read Back Command). The read back command enables the next four functions.
(1) read the current count "on the fly"
(2) monitor the current state of the OUT pin
(3) monitor the current state of the counter element
(whether the count is loaded into the counter element
or not)
(4) read the control-word
Read back operation can be specified by writing read back
command_ into the control word registers (Ao, A1 =1.1). Fig.
8 shows the format of read back command.
Bits D7 and D6 are used for specifying read back command
and fixed 1 (D 7 = 1. D6 = 1). Respectively bits D5 (count)
and D4 (status) are used for reading the count and the status of the counter selected by the D3- D1 bits. Bit Do must
be fixed O.
Only the count can be read "on the fly" by setting D5 = 0
and D4 = 1 as well as counter latch command above mentioned. If D3 - D1 are set 1 all, the counts of three counters
are simultaneously latched by one read back command.
(By counter-latch command, it must be latched for each
counter.) Next, by read operation, the latched count is read
out.
Only the status can be latched by setting D5 =1 and D4 =0.
By read operation, the status shown in Fig. 9 can be read .
.. lit D7 gives the current state of OUT pin. When D7 = 1,
OUT = "H", and when D7 =0, OUT = "l". Bit D6 indicates
the current state of counter element. When D6 = 1, the initial counter value has not been loaded to counter e.lement.
This state is following.
(1) The control word is written, but the initial counter value
is not loaded
(2) The initial counter value is written to count register, and
the ClK inputs are not.
When 0 6 = 0, the initial counter value has already been
loaded. It is the state when the ClK falls following the rising edge after the initial value is written. Bits D5- Do show
the current state of the control-word regsiter.
It is possible to read both the count and the status. By setting D5 =0 and D, =0, the status can be read first, and the
count next.
The count and/or the status are unlatched when read, so by
the next read operation the current counting value can be
read. And they are unlatched too when the control-word is
set, so the read back command must be set on all such
occasions.
If multiple read back commands are written before the read
operation, only the first one is valid.
Thus, the read of the status is effective when the state of
output and the timing of count reading can be monitored by
software.

4-66

• MITSUBISHI
"'-ELECTRIC

MITSUBISHI LSls

MSM82CS4P/FPI J
CMOS PROGRAMMABLE INTERVAL TIMER

ABSOLUTE MAXIMUM RATINGS
Power supply voltage

V,

Input voltage

Va

Output voltage

With respect to Vss

IOLMAX

Output current

"H" level and force same current

MAX "L"

All output and 1/0 pins output

Output current

"Lit level and force same current

Toor

Operating free-air temperature range

Tstg

Storage temperature range

RECOMMENDED OPERATING CONDITIONS

Vee

Power supply voltage

Vss

Supply voltage (GN D)

Min
4.5

ELECTRICAL CHARACTERISTICS
Symbol

V

-0. 3-Vee+0. 3

V

-0. 3-Vee+0. 3

V

-500

I-'A

2.5

mA

-20-75

"c

-65-150

"C

(Ta=-20-75'C, unless otherwise noted)
limits

Parameter

Symbol

Unit

All output and 1/0 pins output

MAX·'H"
IOHMAX

Ratings
-0.3-7

Conditions

Parameter

Symbol
Vee

I
I
I

Nom
5
0

I
I
I

Max
5.5

Un!t

V

V

(Ta=-20-75"C, Vee =5V±10%, Vss=ov, unless otherwise noted)

Parameter

Test conditions

Limits

Min

V ,H

High-level input voltage

2.0

V ,L

Low-level Input voltage

-0.3
IOH=-400"A

2.4

IOH=-20"A

4.4

Typ

Max
Vee +O.3
0.8

Unit

V
V

V OH

High-level output voltage

VOL

Low-level output voltage

10,=2,OmA

0.45

V

I'H

High-level input current

Vr=Vcc

I'L

Low-level input current

V,=OV

+10
+10

loz

Off -state output cu rrent

Vo=OV-Vee

±10

lee

Supply current from Vee (operallng)

f=8MHz

10

I-'A
I-'A
I-'A
mA

Ices

Supply current from Vee (stand by)

V,=OV, Vee

10

"A

Ci

Input termiral capacitance

V,,=Vss , f=lMHz, 25mVrms, Ta=25'C

10

Cilo

Input/output termiral capacitance

V,/OL =Vss , f=l MHz,25mVrms, Ta=25'C

20

pF
pF

4-68

• .MITSUBISHI
"ELECTRIC

V

MITSUBISHI LSls

MSM82CS4P/FPI J
CMOS PROGRAMMABLE INTERVAL TIMER

TIMING DIAGRAMS
Read Cycle

V

"\IL
tSU(S-R)
~

r\

tSU(A-R)

Ao. A,

tW(R)

.v
I

X
tPZV(A-OQ)

-

-

"'ZVeR-CO)

/~

00-0,

I----

~

th(R-A)

K
tpVZ(R-OQ)

'?l/"'

Write Cycle

J/
tsues-w)

tsueA-W)

~
I

tw(w)

I

Ao. A,

)(

V
I---

theW-A)

K

tSUCOQ-W)

thew-co)

X

~

(Recovery Time)

~~=t=rece=R).=trec=eW)~~_ _ _~~

,,
_____

RD.

WR

Clock and Gate Cycle

GATE

elK

OUT

tPXV(t\

4-70

~OUT)

• MITSUBISHI
..... ELECTRIC

MITSUBISHI LSI.

MSM82CSSAP-2/FP-21 J-2
CMOS PROGRAMMABLE PERIPHERAL INTERFACE

BLOCK DIAGRAM

PA,
PA,
READ INPUT RD

PA,
PA 4

WRITE INPUT WR

PA 3
CONTROL

A,

lOGIC

Ao

RESET INPUT RESET

CHIP SELECT

~

CS

INPUT

D,
0,

D,
DATA BUS

(SV)

(OV)

4-72

(8-BIT)

I-----U

PA,

DATA BUS

BUFFER

0,
0,
0,

"l------

PC,
PC,

8·81T

r--1

GROUP B

It------I.

PC.

110

PC 3

PORTS C

PC,

1--;~-1II-"'1
JI (LEAST
PORT C
l
SIGNIFI· t - - - - - - I .

PC,
1--+----:~~~~~~~~~~~~~~-_{=1=~:;::C:A:N:T:~:'T:9~~======::c5 PC,
DATA BUS

"l------

PA,

PC,

PORT C
(MOST SIGNIFICANT 4BITS)

4

I
INTERNAL

)-------0
)-------0
)-------0

vcct

I~----~I~~~~==~
L~GROUPA

I

)-----)-------0
)-------0

D.
D,

r-

a

CONTROL

PA,

ADDRESS {
INPUTS

110
PORTS A

I

a

Lt----

PB,

PB,
PB,

GROUP

c-

GROUP

B

B

PORTS

CONTROL

PB,
PB,
PB,

(8-BIT)

PS,
PB,

,

~

--------------------------------------------------~

• MITSUBISHI
.... ELECTRIC

110
PORTS B

MITSUBISHI LSls

MSM82CSSAP-2/FP-21 J-2
CMOS PROGRAMMABLE PERIPHERAL INTERFACE

BASIC OPERATING MODES
The PPI can operate in anyone of three selected basic
modes.
(group A, group B)
Mode 0: Basic input/output
(group A, group B)
Mode 1: Strobed input/output
(group A only)
Mode 2: Bidirectional bus
The mode of both group A and group B can be selected independently. The control word format for mode set is
shown in Fig. 2.

0, 06 05 0, 0, 0, 0, Do

0, 06 05 0, 0, 0, 0, Do

11101010101011101

1tl010101010ll1n

Mode sel flag

I

Active

=

1

I

Group A mode sel
Mode U 06. 0,
Mode 1 06, 05 =
Mode 2 06, 05 =
Port A input/oulpul
louIPut
0
onput = 1

I
0, 0
0, 1
1, X
set

0, 06 05 0, 0, 0, 0, Do

11 101010111010101

I

I

Port C (high-order 4 bits) inpuVoutput sel

I
I
I
,".""~." I
loutpul - 0
,npul = 1

. - - - - Group B mode sel
ModeO-O
Model = 1

PA,-PAo
0, 06 05 0, 0, 0, 0, Do

0, 06 05 0, 0, 0, 0, Do

11 101010111011101

111010101110111t!

I; '"' , ,.

loutpul
0
onput = 1
Port C (low-order 4 bits) inpuVoulput set
,.......--,
louIPut - 0
10,10610510,10,10,1011001. inpul = 1
•

I

Fig. 2

1.

PA,-PAo

I

0, 06 05 0, 0, 0, 0, Do

11 10 10111010101t!

Control word format for mode set.

Mode 0 (Basic Input/Output)

This functional configuration provides simple input and output operations for each of the 3 ports. No "handshaking" is
\
required; data is simply written in, or read from, the specified port. Output data from the CPU to the port can be held,
but input data from the port to the CPU cannot be held. Any
one of the a-bit ports and 4-bit ports can be used as an input port or an output port. The diagrams following show the
basic input/output operating modes.

PA,-PAo

4-74

0, 06 05 0, 0, 0, 0, Do

11 10 10111010101 0 1

0, 06 05 0, 0, 0, 0, Do

07 D6 Os 04 03 02 01 Do

11 1010111010111 0 1

111010111010111t!

0, 0 6 05 0, 0, 0, 0, Do

0, 06 05 0, 0, 0, 0, Do

11 101011111010101

1 1 1010111110101t!

PA,-PAo

0, 06 05 0, 0, 0, 0, Do

0, 06 05 0, 0, 0, 0, Do

11 1010101010101 01

11 10 1010101010ln

PA,-PAc

0, 06 05 0, 0, 0, 0, Do

11 10 10 111110 11 10

' . MITSUBISHI
. . . . ELECTRIC

I

0, 06 05 0, 0, 0, 0, Do

111010111110111t!

MITSUBISHI LSls

MSM82CSSAP-2/FP-21 J-2
CMOS PROGRAMMABLE PERIPHERAL INTERFACE

MODE

I (PORT A)

MODE

8

I (PORT B)
8

OBFA

OBFa

ACKA

ACK a

INTRa

INTRA
WR
I/O

WR

CONTROL WORD

WR
OBF
ACK
INTR

CONTROL WORD
D7 D6 D5 D, D3 D, D, Do

PORT
OUTPUT

l'IXIXIXlxIIIOlxl
Note 2'

o=OUTPUT

Fig. 5

Fig. 6

An example of mode 1 output state

When INTE is low-level. then the output of INTR is
aways low-level

Timing diagram

I/O

OBF B
PC,

IBF.

PCa

INTRa

PORT A (STROBED OUTPUT)
PORT B (STROBED INPUT)

ACK B
PORT A (STROBED INPUT)
PORT B (STROBED OUTPUT)

o =OUTPUT

4-76

INTRa

CONTROL WORD

CONTROL WORD

Fig. 7

PCa

Mode 1 port A and port B 1/0 example

O=OUTPUT

Fig. 8

•
MITSUBISHI
"ELECTRIC

Mode 1 port A and port B 1/0 example

MITSUBISHI LSls

MSM82CSSAP-2/FP-21 J-2
CMOS PROGRAMMABLE PERIPHERAL INTERFACE

4.

Control Signal Read

Table

2

Read-out control signals

In mode 1 or mode 2 when using port C as a control port,
by CPU execution of an IN instruction, each control signal
and bus status from port C can be read.

~
1.

5.

Mode I, output OBFA INTEA

Control Word Tables

Control word formats and operation details for mode 0,
mode 1, mode 2 and set/reset control of port C are given in
Tables 3, 4, 5 and 6, respectively.

Table

input

Mode 2

D.
I/O

D5

OBFA INTE,

D.

D3

D,

D2

Do

IBFA INTEA INTRA INTEB IBFB INTRB
1/0
1/0 INTRA INTEB OBFB INTRB
By group B mode
IBFA INTE2 INTRA

3

Mode 0 control words

D7

D,

D5

D,

D,

D2

D,

Do

HexadeCImal

Port A

Port e (high-order 4 bits)

Port e (low-order 4 bits)

Port B

1

0

0

0

0

0

0

0

80

OUT

OUT

OUT

OUT

1

0

a

1

81

OUT

OUT

IN

OUT

1

0

1

a

82

OUT

OUT

OUT

IN

1

0

1

1

83

OUT

OUT

IN

IN

1

0

OUT

IN

OUT

OUT

a

89

OUT

IN

IN

OUT

1

0

a a
a 1
1
a

88

1

8A

OUT

IN

OUT

IN

1

0

1

1

8B

OUT

IN

IN

IN

1

0

a a 0
a a 0 0
a a 0 a
a 0 1 0
a a 1 a
a 0 1 a
a a 1 0
a 1 a 0
a 1 0 a
a 1 0 a
a 1 a a
a 1 1 a
a 1 1 a
0
1
1
a
0
1
1
a

a a
a 1

90

IN

OUT

OUT

OUT

91

IN

OUT

IN

OUT

1

0

92

IN

OUT

OUT

IN

1

1

93

IN

OUT

IN

IN

a
a

0

98

IN

IN

OUT

OUT

1

99

IN

IN

IN

OUT

1

0

9A

IN

IN

OUT

IN

1

1

9B

IN

IN

IN

IN

Group A

Control words

1

0

1

a
a
a

1
1
1

0

1

a
a

1

0

Note 4

OUT indicates output port, and I N Indicates Input port

Table

4

Control words

Group A

Do

Hexadecimal

1

a

1

0

a

1

0

x

A4

1

a

1

0

a

1

1

x

A6

1

0

1

a

1

1

a

X

1

0

1

a

1

1

1

X

1

a

1

1

0

1

a

X

1

a

1

1

a

1

1

x

1

a

1

1

1

1

a

X

1
Note 5
6'

0

Group B

Mode 1 control words

D7 D, D5 D, D, D2 D,

4-78

D7
1/0

Mode

Mode

1

1

1

1

1

X

A5
A7
AC
AD
AE
AF
B4
85
B6
B7
BC
BD
BE
BF

Port A

Group B

porte

Port e
PC7

PC.

OUT

-OBFA

OUT

PC5

PC.

PC3

Port B

PC2

PC,

PCo
INTRB

OUT

ACKA

OUT

INTRA

ACKB

-OBF B

-OBFA

ACKA

OUT

INTRA

STBB

IBF.

INTRB

IN

OUT

-OBFA

-ACKA

IN

INTRA

ACK.

-OBF.

INTR.

OUT

OUT

-OBFA

-ACKA

IN

INTRA

STBB

IBF.

INTRB

IN

...

~-

IN

OUT

IBFA

STBA

INTRA

ACKB

OBFB

INTR.

OUT

IN

OUT

IBFA

-STBA

INTRA

STB.

IBF.

INTR.

IN

IN

IN

IBFA

-STBA

INTRA

ACKB

-OBF.

INTRB

OUT

IBFA

-STBA

INTRA

STB.

IBFB

INTR.

IN

IN

IN

Mode of group A and group B can be programmed independently.
It IS not necessary for both group A and group B to be in mode 1

• MITSUBISHI
"'ELECTRIC

MITSUBISHI LSls

MSMS2CSSAP-2/FP-21 J-2
CMOS PROGRAMMABLE PERIPHERAL INTERFACE

ABSOLUTE MAXIMUM RATINGS
Symbol

Parameter

Vee

Supply voltage

V,

Input voltage

Va

Output voltage

Conditions
With respect to Vss

IOLMAX

Unit
V

-0. 3-V ee +0. 3

V

All output and I/O p,ns output

-0. 3-V ee +0. 3
-4
Port

Output current

"H" level and force same current

Data bus

MAX"L"

All output and I/O pms output

Port

Output current

"L" level and force same current 2

Data bus

MAX "H"
IOHMAX

Ratmgs

-0.3-7

Topr

Operatmg free-alf temperature renge

Tstg

Storage temperature range

RECOMMENDED OPERATING CONDITIONS
Symbol
Vee

Supply voltage

Vss

Supply voltage (GND)

ELECTRICAL CHARACTERISTICS
Symbol

Min

J

Nom

I

Max

4.5

I

5

5.5

I

0

I
I

V

Test conditions

Limits
Min
2.0

V'L

Low-level input voltage

-0.3

VOL
lee

Supply current from Vee

"C

V

High-level input voltage

Output high voltage (NotelO)

"C

-65-150

Unit

V'H

Output low voltage (NotelO)

mA

-20-75

(Ta=-20-75'C, Vcc =5V±10%, Vss=ov, unless otherwise noted)

Parameter

V OH

4
2.5

(Ta=-20-75'C, unless otherwise noted)
Limits

Parameter

-500

V

mA
I'A

IOH=-400,uA

2.4

IOH=-20,uA

4.4

Typ

Max

Unit

Vcc+0.3

V

0.8

V
V

III

Input leak current

loz

Off-state output current

Vo=OV-Vce

Ci

Input terminal capacitance

f=lMHz

10

pF

GilD

Input/output terminal capacitance

Unmeasured plns=OV

20

pF

Note 9 : Current flowing into an

Ie IS positive, out is negative,

10: Output current must be less than ±4mA for each Port pin

4-80

•
MITSUBISHI
;"ELECTRIC

0.4

V

IOL=2.5mA
All ,nput mode
RESET=OV. Other pins=Vcc.
V,=OV, Vee

10

I'A

±10
±10

I'A
I'A

MITSUBISHI LSls

MSM82CSSAP·2/FP·21 J·2
CMOS PROGRAMMABLE PERIPHERAL INTERFACE

TIMING DIAGRAM
Data Bus Read Operation
tW(R)

~l~

~\
-'-.:

thIR_A)

l

2
IOL(DATA BUS) (rnA)

VoL-l oL CHARACTERISTICS (PORT)

0.3r------------r----------~------------+_----------~--~~~--~
Vcc=4.5V

Vcc=5V
Vcc =5.5V
Vcc=4.5V

~
-;::

0.2

Vcc=5V
Vcc =5.5V
Vcc=4.5V
Vcc=5V
Vcc =5.5V

0:

0

II.
~

oJ

0.1

3
IOL(PORT) (rnA)

4-86

• MITSUBISHI
..... ELECTRIC

4

MITSUBISHI LSI.

MSM82CS9AP-2/FP-21 J-2
CMOS PROGRAMMABLE INTERRUPT CONTROLLER

BLOCK DIAGRAM

INTERRUPT
ACKOWLEDGE INPUT

INTA

INTERRUPT
AEOUEST OUTPUT

INT

0,
CONTROL LOGIC

0,
DATA BUS

0,

BUFFER

0,

BIDIRECTIONAL DATA BUS

lA,
lA,
lA,
lA,

INTERRUPT
AEQUEST INPUTS

WR

READ/WRITE

lA,

CONTROL

IRs

3

LOGIC

lA,
lA,

'-----( 1

WRITE CONTROL INPUT

RD READ CONTROL INPUT
Ao ADDRESS INPUT
CS CHIP SELECT INPUT
CAS,

1

CASCADE LINES

INTEAAUPT MASK AEGISTEA (lMAI

J
SP/EN
I

SLAVE PROGRAM INPUT/ENABLE

1_ _ _ _ _ _- - - - - - - - - - - - - - -

4-88

,. MITSUBISHI

~ELECTRIC

BUFFER OUTPUT

MITSUBISHI LSls

MSM82CS9AP-2/FP-21 J-2
CMOS PROGRAMMABLE INTERRUPT CONTROLLER
Interrupt Sequence
1. When the CPU is a MELPS85

IRU"IRR SET

(1)

When one or more of the interrupt request inputs
are raised high, the corresponding IRR bites) for the
high-level inputs will be set.
(2) Mask state and priority levels are considered and, if
appropriate, the M5M82C59AP-2 sends an INT sig(3)

nal to the CPU.
The acknowledgement of the CPU to the INT signal,
the CPU issues an INTA pulse to the M5M82C59AP-

2.
(4)

Upon receiving the first INTA pulse from the CPU, a
CALL instruction is released onto the data bus.
(5) A CALL is a 3-byte instruction, so additional two
INTA pulses are issued to the M5M82C59AP-2 from
the CPU.
(6) These two INTA pulses allow the M5M82C59AP-2 to
release the program address onto the data bus. The
low-order 8 bits vectored address is released at the
second INTA pulse and the high-order 8 bits vectored address is released at the third INTA pulse.
The ISR bit corresponding to the interrupt request
input is set upon receiving the third INTA pulse from
the CPU, and the corresponding IRR bit is reset.
(7) This completes the 3-byte CALL instruction and the
interrupt routine will be serviced. The ISR bit is reset at the trailing edge of the third INTA pulse in the
AEOI mode. In the other modes the ISR bit is not
reset until an EOI command is issued.

r--

1
r----:J 2
L--J /L--J\!~~

INTA - - - - ,

RESET
ISR RESET (AEOI MODE)

ISR SET

The interrupt request input must be held at high-level until
the first INTA pulse is issued. If it is allowed to return to
low-level before the first INTA pulse is issued, an interrupt
request in IR7 is executed However, in this case the ISR
bit is not set.
This is a function for a noise countermeasure of interrupt
request inputs. In the interrupt routine of IR7, if ISR is
checked by software either the interrupt by noise or real interrupt can be acknowledged. In the state of edge -trigger
mode normally the interrupt request inputs hold high-level
and its input low-level pulse in the case of interrupt.

Interrupt sequence outputs
1. When the CPU is a MELPS85
A CALL instruction is released onto the data bus when
the first INTA pulse is issued. The low-order 8 bits of the
vectored address are released when the second INTA
pulse is issued, and the high-order 8 bits are released
when the third INTA pulse is issued. The format of these
three outputs is shown in Table 2.
Table 2 Formats of interrupt CALL instruction and vectored addre.ss
First INTA pulse (CALL instruction)

IRUt'IRR SET
06

0,

05

a

a

Do

o

Second INTA pulse (low-order 8 bits of vectored address)

2.

When the CPU is a MELPS86 or MELPS88
(1)

(2)

(3)
(4)

(5)
(6)

4-90

When one or more of the interrupt request inputs
are raised high, the corresponding IRR bit(s) for the
high-level inputs will be set.
Mask state and priority levels are considered and if
appropriated, the M5M82C59AP-2 sends an INT signal to the CPU.
As an acknowledgement to the INT signal, the CPU
issues an INTA pulse to the M5M82C59AP-2.
Upon receiving the first INTA pulse from the CPU,
the M5M82C59AP-2 does not drive the data bus,
and the data bus keeps high-impedance state.
When the second INTA pulse is issued from the
CPU, an 8-bit pOinter is released onto the data bus.
This completes the interrupt cycle and the interrupt
routine will be serviced. The ISR bit is reset at the
trailing edge of the second INTA pulse in the AEOI
mode. In the other modes the ISR bit is not reset
until an EOI command is issued from the CPU.

IR

Interval= 4

07

06

05

0_

03

02

0,

IRa

A7

A6

A5

0

0

0

0

0

IR,

A7

As

A5

0

0

1

0

0

Do

IR2

A7

A6

A5

0

1

0

0

0

IR3

A7

As

A5

0

1

1

a

0

IR_

A7

A6

A5

1

0

0

0

0

IR5

A7

As

A5

1

0

1

0

0

IR6

A7

A6

A5

1

1

0

0

0

IR7

A7

A6

A5

1

1

1

0

0

•
MITSUBISHI
' " ELECTRIC

MITSUBISHI LSls

MSM82CS9AP-2/FP-21 J-2
CMOS PROGRAMMABLE INTERRUPT CONTROLLER

Write Control Input (WR)
When WR goes to low-level the M5M82C59AP-2 can be
written.
Read Control Input (RD)
When RD goes low-level status information in the Internal
register of the M5M82C59AP-2 can be read through the
data bus.
Address Input (Ao)
The address input is normally connected with one of the
address lines and is used along with WR and RD to control
write commands and reading status information.
Cascade Buffer/Comparator
The cascade buffer/comparator stores or compares identification codes. The three cascade lines are output when
the M5M82C59AP-2 is a master or input when it is a slave.
The identification code on the cascade lines select it as
master or slave.

PROGRAMMING THE M5M82C59AP-2
The M5M82C59AP-2 is programmed through the Initialization Command Word (ICW) and the Operation Command
Word (OCW). The following explains the functions of these
two commands.
Initialization Command Words (ICWs)
The initialization command word is used for the initial setting of the M5M82C59AP-2. There are four commands in
this group and the following explains the details of these
four commands. The command flow of ICWs is shown Fig.

2.
ICW1
The meaning of the bits of ICW1 is explained in Fig.

Fig. 2

4-92

along with the functions. ICW1 contains vectored address
bits A7- A5, a flag indicating whether interrupt input is edge
triggered or level triggered, CALL address interval,
whether a single M5M82C59AP-2 or the cascade mode is
used, and whether ICW4 is required or not.
Whenever a command is issued with Ao=O and 04=1, this
is interpreted as ICW1 and the following will automatically
occur.
(a) The interrupt mask register (IMR) is cleared.
(b) The interrupt' request input IR7 is assigned the lowest
priority.
(c) The special mask mode is cleared and the status read
is set to the interrupt request register (IRR).
(d) When IC4=O all bits in ICW4 are set to O.
ICW2
ICW2 contains vectored address bits A15 - As or interrupt
type T7-T3, and the format is shown in Fig. 3.
ICW3
When SNGL = 1 it indicates that only a single
M5M82C59AP-2 is used in the system, in which case ICW3
is not valid. When SNGL=O, ICW3 is valid and indicates
cascade connections with other M5M82C59AP-2 devices. In
the master mode, a 1 is set for each slave.
When the CPU is a MELPS85 the CALL instruction is released from the master at the first I NTA pulse and the vectored address is released onto the data bus from the slave
at the second and third I NTA pulses.
When the CPU is a MELPS86 the master and slave are in
high-impedance at the first INTA pulse and the pointer is

3

Initialization sequence

• MITSUBISHI
~ELECTRIC

MITSUBISHI LSls

MSM82CS9AP-2/FP-21 J-2
CMOS PROGRAMMABLE INTERRUPT CONTROLLER

released onto the data bus from the slave at the second
INTA pulse.
The master mode is specified when SP/EN pin is highlevel or BUF = 1 and M/S = 1 in ICW4, and slave mode is
specified when SP/EN pin IS low-level or BUF=1 and M/S
=0 in ICW4. In the slave mode, 3-bit ID2~IDo identify the
slave. And then when the slave code released on the cascade lines from the master, matches the assigned ID code,
the vectored address is released by it onto the data bus at
the next INTA pulse
ICW4
Only when IC4= 1 in ICW1 is ICW4 valid. Otherwise all bits
are set to O. When ICW4 is valid it specifies special fully

nested mode, buffer mode master/slave, automatic EOI and
microprocessor mode. The format of ICW4 is shown in Fig.

3.
Operation Command Words (OCWs )
The operation command words are used to change the
contents of IMR, the priority of interrupt request inputs and
the special mask. After the ICW are programmed into the
M5M82C59AP-2, the device is ready to accept interrupt requests. There are three types of OCWs; explanation of
each follows, and the format of OCWs is shown in Fig 4
OCW1
The meaning of the bits of OCW1 are explained in Fig. 4
along with their functions. Each bit of IMR can be indepen-

, . - - - - , - - , - _ - - ,_ _. - - _ - ,_ _,--_---,_ _ _ _--11.

INTERRUPT MASK SET
INTERRUPT MASK RESET

OCW1

0 1
0 1 1
1 0 1
1 0 0
0 0 0
1 1 1·
0

1
0

NON-SPECIFIC EOI
} EOI

SPECIFIC EOI (RESETS ISR BITS L,-Lo)
ROTATE ON NON-SPECIFIC EOI
SETS AUTOMATIC ROTATION FLIP-FLOP

} AUTOMATIC ROTATION

RESET AUTOMATIC ROTATION FLIP-FLOP
ROTATE ON SPECIFIC EOI (RESETS ISR BIT L2-Lo)

:J
L Ao0 I

R

0,

I

} SPECIFIC ROTATION

1 0 SETS PRIORITY COMMAND (SET LOWEST PRIORITY BIT L,-Lo)
1 0 NO OPERATION

10 LEVEL TO BE ACTED UPON

SL

EOI

06

05

I

0

I

0

I

03

L,
0,

I

I

0 1
0 0
0 0
0 1

I

I

L,

0,

Lo

2 3 4 5
0 0 1 1
1 1 0 0
0 1 0 1

6

I

Do

OCW2

0
1

X

NO OPERATION

0

RESET SPECIAL MASK MODE

1

1

SETS SPECIAL MASK MODE

11
0

I

,

I

0
Ao

Fig, 4

4-94

I

0
0,

ESMM

I SMM I

06
05
OCW3

0

I

1
03

I

P

0,

I

X

NO OPERATION

1
1

0

SETS STATUS READ REGISTER IN IRR

1

SETS STATUS READ REGISTER IN ISR

I
0,

POLL COMMAND
NO POLL COMMAND

0

RR

I

I
RIS
Do

Operation command word format

•
MITSUBISHI
..... ELECTRIC

7

1 1
1 1
0 1

MITSUBISHI' LSls

MSM82CS9AP-2/FP-21 J-2
CMOS PROGRAMMABLE INTERRUPT CONTROLLER

of those that are set. Other ISR bits are reset by a specific
EOI and the bit to be reset is specified in the EOI by the
program. The SEOI is useful in modes other than fully
nested mode. When the M5M82C59AP-2 is in special mask
mode ISR bits masked in IMR are not reset by EOL EOI
and SEOI are selected when OCW2 is executed.

Automatic EOI (AEOI)
In the AEOI mode the M5M82C59AP-2 executes nonspecific EOI command automatically at the trailing edge of
the last INTA pulse. When AEOI = 1 in ICW4, the
M5M82C59AP-2 is put In AEOI mode continuously until reprogrammed in ICW4.

Automatic rotation
The automatic rotation mode is used in applications where
many interrupt requests of the same level are expected
such as multichannel communication systems In this mode
when an interrupt request is serviced, that request is
assigned the lowest priority so that if there are other interrupt requests they will have higher priorities. This means
that the next request on the interrupt request being serviced must wait until the other interrupt requests are serviced (worst case is waiting for all 7 of the other controllers
to be serviced). The priority and serving status are rotated
as shown in Fig. 5.

BEFORE ROTATION

(IR3 THE HIGHEST PRIORITY
REQUIRING SERVICE)

Specific rotation
Specific rotation gives the user versatile capabilities in interrupt controlled operations. It serves in those applications
in which a specific device's interrupt priority must be
altered. As opposed to automatic rotation which automatically sets priorities, specific rotation is completely user
controlled. That is, the user selects the interrupt level that
is to receive lowest or highest priority. Priority changes can
be executed during an EOI command.

Level triggered mode/Edge triggered mode
Selection of level or edge triggered' mode of the
M5M82C59AP-2 is made by ICW1, When using edge triggered mode not only is a transition from low-level to highlevel required, but the high-level must be held until the first
INTA.· If the high-level is not held until the first INTA, the interrupt request will be treated as if it were input on IR7, except that the ISR bit is not set. When level triggered mode
is used the functions are the same as edge triggered mode
except that the transition from low-level to high-level is not
required to trigger the interrupt request.
In the level triggered mode and using AEOI mode together,
if the high-level is held too long the interrupt will occur immediately. To avoid this situation interrupts should be kept
disabled until the end of the service routine or until the IR
input returns low-level. In the edge triggered mode this
type of mistake is not possible because the interrupt request is edge triggered.

Reading the M5M82C59AP-2 internal status
IS,

IS.

IS5

ISR STATUS

IS,

a

IS3

IS,

ISo

I
HIGHEST PRIORITY

LOWEST PRIORITY
PRIORITY
STATUS

IS,

i

!

AFTER ROTATION
(IR3 WAS SERVICED AND ALL OTHER
PRIORITIES ROTATED CORRESPONDINGLY)
IS,

Is"

IS5

IS,

IS3

IS,

IS,

ISo

ISR STATUS

HIGHEST P,110RITY
PRIORITY
STATUS

Fig. 5

i

,I

LOWEST PRIORITY

CASCADING

7

An example of priority rotation

In the non-specific EOI command automatic rotation mode
is selected when R=l, EOI=l, SL=O in OCW2. The internal priority status is changed by EOI or AEOI commands.
The rotation priority A flip-flop is set by R = 1, EOI = and
SL=O which is useful when the M5M82C59AP-2 is used in
the AEOI mode.

a

4-96

The contents of IRR and ISR can be read by the CPU with
status read. When an OCW3 is issued to the M5M82C59AP2 and an RD pulse issued the contents of IRR or ISR can
be released onto the data bus. A special command is not
required to read the contents of 1M R. The contents of 1M R
can be released onto the data bus by issuing an RD pulse
when Ao=l. There is no need to issue a read register command every time the IRR or ISR is to be read. Once a read
register command i~ received by the M5M82C59AP-2, it remains valid until it is changed. Remember that the programmer must issue a poll command every time to check
whether there is an interrupt request and read the priority
level. Polling overrides status read when P = 1, RR = 1 in
OCW3.

The M5M82C59AP-2 can be interconnected in a system of
one master with up to 8 slaves to handle up to 64 priority
levels. A system of 3 units that can be used with the
MELPS85 is shown in Fig. 6.
The master can select a slave by outputting its identification code through the 3 cascade lines. The INT output of
each slave is connected to the master interrupt request inputs. When an interrupt request of one of the slaves is to
be serviced the master outputs the identification code of
the slave through the cascade lines, so the slave will release the vectored address on the next INTA pulse.

• MITSUBISHI
. . . . ELECTRIC

MITSUBISHI LSI.

MSM82CS9AP-2/FP-21 J-2
CMOS PROGRAMMABLE INTERRUPT CONTROLLER

ADDRESS

aus

16

CONTROL BUS
DATA BUS

8

3

3

3

8

8

es

8

1 es

INT

Ao
M5M82C59AP-2
MASTER

CASo
CAS,

CASo
CAS,
CAS,

CAS,

SP/EN IR,IR IRs IR41R31R21R,IRo

I f
Vee

7

6

l ~S

I

Ao

INT

CASo
--00 CAS
,----'
CAS,

M5M82C59AP-2
SLAVE

SP/EN IR,IR.IR.IR.IR3IR2IR,IRo

! ! f3! !!

M5 M82C59AP-2
SLAVE

SP/EN IR,IR IR5 IR.IR3IR,IR,IR

ttl!!t!!

G!D

r=-

INT

Ao

' G!D

tI!!!!r!

y

INTERRUPT REQUEST INPUTS

Fig. 6 Cascading the M5M82C59AP-2

DEN
DATA BUS
ADDRESS BUS

Do -D,
(Note 3) ADo- AD,
RD OR-IORC
WROR~
WC
INTA
M/iO

8

Do-D,

~ Ao

I

....
Ao
A,
A,
A.

As
As

..........

......

..

RD

LS30

s:::
s:::

'"co
N

)0-

0

'"~""~[~--REQUEST
INPUTS

-

IRo
IR,
IR,
IR,
IR,
IR,
IR.
IR,

'"~
~

Note 3 : Do-D, of the M5M82C59AP-2 are direct connected with ADo-AD, of the MELPS86

Fig. 7 Example of interface with the MELPS86

4-98

OE
TO BUS BUFFER

jjj'f7(

I000o-

A,

INTR

•
5.

Wii sp/rn
~

. , J'"

.... ....

II

INT

• MITSUBISHI
. . . . ELECTRIC

R>-

MITSUBISHI LSls

MSM82CS9AP-21 FP-21 J-2
CMOS PROGRAMMABLE INTERRUPT CONTROLLER

ABSOLUTE MAXIMUM RATINGS
Symbol

Parameter

Vee

Supply voltage

V,

Input\voltage

Vo

Output voltage

IOHMAX

IOLMAX

Conditions

With respect to Vss

MAX"H"

All output and liD pins output

Output current

"H" level and force same current

MAX "L"

All output and liD pins output

Output current

"L" level and force same current

free~air

Topr

Operating

Tstg

Storage temperature range

Ratings

Unit

-0.3-7

V

-0. 3-Vee+0. 3

V

-0. 3-Vec+0. 3

V

-500

/-lA

temperature range

RECOMMENDED OPERATING CONDITIONS

2.5

mA

-20-75

·C

-65-150

·C

(Ta=-20-75'C, unless otherwise noted)
Limits

Symbol

Unit

Parameter

Min
Vee

Supply voltage

Vss

Supply voltage (GND)

Nom

4.5

Max
5

5.5

0

ELECTRICAL CHARACTERISTICS

V
V

(Ta=-20-75'C, Vcc =5V±10%, Vss=OV, unless otherwise noted)
Limits

Symbol

Parameter

Test conditions

Unit

Min

V'H

High·level input voltage

V'L

Low~level

2.0
-0.3

input voltage

VO H

High·level output voltage

VOH(INT)

High-level output voltage, interrupt request output

IOH=-400,uA

2.4

IOH=-20,uA

4.4

Typ

Max
Vcc+0.3
0.8

V
V
V

IOH=-400,uA

2.4

IOH=-100,uA

3.5

IOH=-20,uA

4.4

V

V

VOL

Low-level output voltage

10L =2.2mA

Icc

Standby supply current Irom Vee

V,=OV, Vee output open

I'H

High-level input current

VI=VCC

I'L

Low-level input current

v,=ov

loz

Off~state

vo=ov-Vcc

ILIR1

I R pin input current

V,=OV

ILIR2

IR pin input current

VI=VCC

10

/-lA

Ci

Input capacitance

Vcc=Vss, 1=1 MHz. 25mVrms. Ta=25'C

10

pF

Ci/o

Input/output capacitance

Vcc=Vss, 1=1 MHz. 25mVrms, Ta=25'C

20

pF

4-100

output current

• MITSUBISHI
"-ELECTRIC

0.45
10

/-lA

-10

10

/-lA

-10

10

/-lA

-10

10

/-lA
/-lA

-300

MITSUBISHI LSls

MSM82CS9AP-2/FP-21 J-2
CMOS PROGRAMMABLE INTERRUPT CONTROLLER

TIMING DIAGRAM
Write Mode

>-

K
Ih(w-A)

ISU(A-W)

-00-

\

Iw(w)

>--

-/

r
tSU{oc-w)

Ih(w-oo)

I~r-

'}F-

0,-00

~

r--

K

Read Mode
es, Ao

}:

~

tSU(A_R)

Ih(R-A)
IW(R)

\~

¥

tPYZ(R-OO)

tPZV(R-OQ)

IpZV(A-OO)

~
tpHL(R-ENl

~

W

tPlH(R-EN)

I

\-r

4-102

• MITSUBISHI
..... ELECTRIC

MITSUBISHI LSls

M5M82C255ASP
CMOS PROGRAMMABLE PERIPHERAL INTERFACE

DESCRIPTION
The M5M82C255ASP is a LSI equivalent to two
M5M82C55AP-2. It is housed in a single 64-pin shrink DIP.
The M5M82C255ASP is fabricated using silicon-gate
CMOS technology for a single supply voltage. This LSI is a
simple input and output interface for TTL circuits, having 48
input/output pins which correspond to six 8-bit input/output
ports.

PIN CONFIGURATION (TOP VIEW)
PA04

CHIP

S~L~~;
PORT

•
•
•
•
•
•
•
•
•

Single 5V supply voltage
Input: TTL compatible (l oL =2.5mA)
Output: CMOS/TTL compatible
Each I/O pin has ±4mA driving capability
Read access time: 120ns
Timing specification enable easy design of system bus
timing
Noise limiter is built-in to provide high noise margin
(RESET, ACK, STB)
48 programmable I/O pins
Direct bit set/reset capability
64-pin shrink DIL package (lead pitch 0.07 inch) is.
used for easy mounting

1
2

PAo,.... 3

1/0 PORTS Ao

A~~~5~~

FEATURES

++

PA03 -

1

64 .... PA051
63 ++ PAoe

PA o, - 4

62 .... PA07
61 - R/W

PAoo '" 5

60 -

eso -+
A,

-+

f I/O PORTS Ao
READIWRITE
Y,?pNJfOL

RESET RESET INPUT

6

7

Ao -+ 8
DATA BUS

1/0 PORTS Co

1/0 PORTS Bo

110 PORTS A1

APPLLlCATION
Input/output ports for microprocessor

If0 PORTS 8 t

FUNCTION
A Block diagram of the M5M82C255ASP is shown in the
following page. The M5M82C255ASP consists of block 0
and block 1 each of which is functionally equivalent to the
M5M82C55AP-2. Block 0 and block 1 have independent
chip select inputs CSo and CS" and independent ports PAo,
PBo, PCo, PA" PB, and PC,. The 8-bit data bus, address inputs Ao and A" and the RESET input are shared by block 0
and block 1. The CPU's RD signal and WR signal must be
multiplexed to generate the R/W signal.
The 48 I/O pins consist of two blocks each with two 12-bit
sub blocks A and B. All four blocks can be programmed independently by three mode control commands from the
CPU.
In mode 0, four 8-bit I/O ports and four 4-bit I/O ports are
available for use as output ports. In mode 1, the 24 I/O pins
of each bJock are divided into groups A and B. In each
group, 8 bits are used for input or output data ports. And 4
bits are used for control data ports. In mode 2, 8 bits of
group A are used as a bidirectional bus with a 5-bit control
signal.
Any of the 8 data bits at port C of each block can set or reset. When reset input (RESET) is high, all ports are set to
the input mode (high-impedance state).

4-104

1/0 PORTS C,

• MITSUBISHI
. . . . ELECTRIC

Outline

64P4B

MITSUBISHI LSls

MSM82C2SSASP
CMOS PROGRAMMA8LE PERIPHERAL INTERFACE

FUNCTIONAL DESCRIPTION

Table 1 Basic Operations

Block 0 has the same function as block 1. Therefore, block
o is explained in the following.

A,

Aa

eSa

es,

R/W

0

0

L

H

H

Data bus - Port

Read function operates when the R/W is high-level, and
data input at the port is transferred to the CPU. Write function operates when the R/W is low-level, and data or control from the CPU are written.

0

0

H

L

H

Data bus - Port A,

0

1

L

H

H

Data bus - Port Bo

0

1

H

L

H

Data bus - Port B,

1

0

L

H

H

Data bus - Port Co

Ao,

1

0

H

L

H

Data bus - Port C,

0

0

L

H

L

Port

0

0

H

L

L

Port AI - Data bus

RiW

(ReadlWrite) Input

Al (Port address) Input

These input signals are used to select one of the three
ports: port A, port B, and port C, or the control register.
They are normally connected to the least significant two
bits of the address bus.

RESET (Reset) Input
At high-level, the control register is cleared. Then all ports
are set to the input mode (high-impedance state).

CSo, CS1 (Chip-Select) Input
At low-level, the communication between M5M82C255ASP
and the CPU is enabled. When CSo is low-level block 0 is
selected, and when CS, is low-level, block 1 is selected.
When CSo and CS, are both high-level, the data bus maintains high impedance state and control from the CPU is
ignored. In modes 0 or 1, the previous data is stored.

Ao - Data bus

0

1

L

H

L

Port

0

1

H

L

L

Port B, - Data bus

So -

Data bus

1

0

L

H

L

Port Co - Data bus

1

0

H

L

L

Port Cl - Data bus

1

1

L

H

L

Control register 0 - Data bus

1

1

H

L

L

Control register 1 - Data bus

X

X

H

H

X

Data bus is high-impedance state

1

1

L

H

H

1

1

H

L

H

ReadlWrite Control Logic
The function of this block is to control transfers of both data
and control words. It accepts the address signals (Ao, A"
CSo, CS1 ), I/O control signals (R/W) and RESET signal,
and then issues commands to both of the control groups.

Data Bus Buffer
This three-state, bidirectional, 8-bit buffer is used to transfer
the data when an input or output instruction is executed by
the CPU. Control words and status information are also
transferred through the data bus buffer.

Group A and Group B Control
Accepting commands from the read/write control logic, the
control blocks (Group A, Group B) receive 8 bit control
words from the internal data bus and issue the proper commands for the associated ports. Control group A is associated with port A and the 4 high-order bits of port C. Control
group B is associated with port B and the 4 low-order bits
of port C. The control register, which stores control words,
can only be written into.

Port 'A, Port B and Port C
M5M82C255ASP contains six 8-bit ports whose modes and
input/output settings are programmed by the system software.
Port A has an output latch/buffer and an input latch/buffer. Port B has an input-output latch/buffer. Port C has an
output latch/buffer and an input buffer. Port C can be divided into two 4-bit ports which can be used as ports for
control signals for port A and port B.
The basic operations are shown in Table 1.

4-106

Operation

Ao

• MITSUBISHI
"ELECTRIC

Illegal condition

MITSUBISHI LSls

M5M82C255ASP
CMOS PROGRAMMABLE PERIPHERAL INTERFACE
chip select Signal, care must be taken when connecting the
M5M82C255ASP to a high-speed microprocessor.
The ad~~~ss setup time and hold time of the M5M82C55AP-2 read signal are defined as tSU(A-R) and th(R-A) but, in
the M5M82C255ASP, they are defined as tsu (A,-CS) and th
(CS-A,) due to above reason, where Ai means address inpus
of AD or A1 . The time is specified to be Ons minimum for
each.

CPU INTERFACE
Fig. 1 shows an application with the M5L8085AP as the
CPU. In this figure, the M5M82C255ASP is mapped in the
1/0 space, but it could also be mapped in the memory
space. The following description applies to the circuit in the
Fig. 1. Characteristics are shown in Figs. 2, 3 and 4.

Chip select signal

Note The term "address" used in describing the address setup time
and address hold time of M5M82C55AP-2 means the address Inputs Ao,
A, and CS

The M5M82C255ASP chip select signal (CS a, CS, ) is the
logical product of the 10· RD (10· WR) signal derived
from the read (write) Signal and 101M signal from the CPU,
and the address decoder output generated by decoding
the address. Therefore, the timing of chip select signal
(CS a, CS, ) is delayed from that of 10· RD (10· WR) signal. The chip select signals CS a and CS, must not be active simultaneously.

Read operation

Write operation
Fig. 4 shows the write timing. The phase relationship of the
R/W and chip select signals is marked by an
For the
M5M82C55AP-2, the phase relationship is defined as the
(Note)
•
)
address
setup time
tsu (A-W) (
or tAW
before WR ,an d .IS specified to be Ons minimum. In the M5M82C255ASP, however,
the phase relationship is reversed by the circuit which
generates the control signal (See Fig. 1), when the chip
select signal becomes active after the R/W Signal goes
low-level. Therefore, we have discarded the previous definition. The phase difference of write Signal and chip
select Signal is defined as tsu (CS-W) and specified as Ons
maximum and - 30ns minimum. The phase difference of
the write signal and address inputs of AD and A, is defined
as tSU(A'-W) and the minimum value is -30ns.
This means that the address inputs of AD and A, and the
chip select signal must become stable within 30ns after the
R/W signal goes low-level. The signals AD and A, can become stable before R/W goes low-level, but the chip
select signal must be activated after the R/W signal goes
low-level. This is required because, if the chip select signal
is active before R/W Signal, the R/W signal will be highlevel, causing the M5M82C255ASP to enter the read operation. The address inputs of AD and A, will write properly
as long as the minimum value is -30ns.

*.

_

The read operation of M5M82C255ASP starts when RD·
CS = 1, just as with the M5M82C55AP-2. When the
M5L8085AP CPU enters into 1/0 read operation, the M5M82C255ASP R/W signal, obtained by inverting the 10 • WR
signal, is kept at high-level. The actual read operation
starts when the chip select signal is activated by the 10 •
RD signal and address decoder output. The access time of
the M5M82C255ASP is specified by the falling edge of the
chip select signal, and is defined a,s t pzv (CS-DQ). Fig. 3
shows the read timing. The delay time (marked by *) extends from the time when the RD signal of CPU become's
active until the chip select signal becomes active. It is
obtained by adding the delay time of LS02 and LS51 in Fig.
1. Table 2 shows the gate delay time of LS02, LS51, LS04
and LSOO used in the circuit of Fig. 1. The sum of the gate
delay times of LS02 and LS51 is 35ns, after which the
actual read operation starts. The access time of the
M5M82C255ASP is 120ns maximum, so the total access
time is 155ns maximum. As the access time of the
M5M82C255ASP is specified by the falling edge of the
M5M82C255ASP
R/W

CPUWR

"H"------------

f

' ' -_ _....J

M5M82C255ASP _ _ _ _""'"
R/W

CPU RD

+""

M5M82C255ASP _ _ _ _ _
CSo or CS,

M5M82C255ASP
CSo or CS,

Ao, A,

Fig. 3

Read operation of the M5M82C255ASP

Fig. 4

Write operation of the M5M82C255ASP

Table 2 Gate delay time
Type

LS02
Typ

tpLH

6

tpHL

6

4-108

I
I
I

LS51
Max

Typ

15

6

15

8

I

1
1

LSOO

LS04
Max

Typ

20

6

20

6

I
I

L

Max

Typ

15

6

15

6

I
I
I

Max

Unit

15

nsee

15

nsee

•
MITSUBISHI
. . . . ELECTRIC

Refer to the Bipolar Digital ICs Section of,
)
( Mltsubishl
Semiconductor Handbook

MITSUBISHI LSls

MSM82C25SASP
CMOS PROGRAMMABLE PERIPHERAL INTERFACE

ABSOLUTE MAXIMUM RATINGS
Symbol

Parameter

Vee

Supply voltage

V,

Input voltage

Vo

Output voltage

Conditions
With respect to Vss

IOLMAX

Unit
V

-0. 3-Vee+0. 3

V

All output and liD pins output

Port

"H" level and force same current.

Data bus

MAX"L"

All output and I/O pins output

Port

Output current

"L" level and force same current.

Data bus

Topr

Operating temperature range

Tstg

Storage temperature

RECOMMENDED OPERATING CONDITIONS

Vee

Supply voltage

Vss

Supply voltage (GND)

4.5

ELECTRICAL CHARACTERISTICS
Symbol

Min

-500
4
2.5
-20-75

"C

-65-150

"C

(Ta = -20-75"C, unless otherwise noted)
limits

Parameter

mA
!LA
mA
mA

-4

Output current

Symbol

V

-0. 3-Vee+0. 3

MAX "H"
IOHMAX

Ratings

-0.3-7

I
I

Nom
5

I
I

I

0

I

Max
5.5

Unit
V
V

(Ta = -20-75"C, Vee = 5V±10%, Vss = OV, unless otherwise noted)
Test conditions

Parameter

Limits
Min

V ,H

High~level

input voltage

2.0

V ,L

Low-level Input voltage

-0.3

VOH

High-level output voltage

(Note2)

VOL

Low-level output voltage

(Note2)

lee

Supply current

I'L
loz

Input leak current
Off-state output current

IOH--400I'A

2.4

IOH=-2OI'A

4.4

IOL=2.5mA
All Input Mode

Typ

Max

Unit

Vee+O.3

V

0.8

V
V

0.4

V

10

f"A

V,=OV, Vee

±1O

Vo=OV-Vec

±10

!LA
f"A

RESET=OV, Other Pins=Vec

Ci

Input capacitance

f=l MHz, 25mVrms, Ta=25'C

10

pF

Clio

1/0 capacitance

OV except test pms

30

pF

Note1: Current flowing into an IC is positive (no sign).
2: The maximum value of the output current should be held within ±4mA at each port pin.

4-110

•
MITSUBISHI
..... ELECTRIC

MITSUBISHI LSls

M5M82C255ASP
CMOS PROGRAMMABLE PERIPHERAL INTERFACE

TIMING DIAGRAM
Data Bus Read Timing
R/W
tw(CS)

~

cSa or cs,

V
th(CS-AI)

tSU(AI-CS)

).

Ao, A,

K

tplIZ( CS-DQ)

tPZV(CS-DQl

///
\\\

~\

)

~//

Data Bus Write Timing
t W (R/W
-

'\

R/W

t!r-

1
W

th(W.AI)
)

)(

Ao, A,

K

tsU(cs-wl

th(w_cs)

i

cSo or cs,

th(w-OQ)

tSU(DQ-W)

K

)
Mode 0 Port Input

~

CSoorCS,="L"
and R/W="H"

PORT INPUT

---------------

~

• ._

~

--------------------

i

Mode 0, 1 Port Output
CSo or CS,="L" - - - - - - - - - - - - - - - - - - - . \
and.R/W="L"

'-------PORT OUTPUT

4-112

~ '-~.~~~~~~~~~~~~~~~~~

_.

• MITSUBISHI
. . . . ELECTRIC

..

tPHL(W-PE)

_

"~'w,,' x~-------

__

MITSUBISHI LSI.

MSM82C2SSASP
CMOS PROGRAMMABLE PERIPHERAL INTERFACE

Mode 2 Bidirectional

esc or eS, ="L"
and R/W="L"

J

OBF

tPLH(ACK-OSF)

~---1---"/

lNTR

tWCACKl

V

\ /1I!...--3-----\

STB

I

\

IBF

esc or eS, ="L"

----------------+---e--I------1~

and R/W="H"
tSU(PE-STB)

PORTA

R/W

thCSTB-PE)

t\\

------H1'/"'L)

Timer input low-level pulse width

80

Ic( ~)

Timer input cycle time

tr( ~)

Timer input rise time

30

ns

tf( ~)

Timer Input fall time

30

ns

ns

DC

320

SWITCHING CHARACTERISTICS

ns

(Ta=-20-75'(;, Vcc =5V±5%, Vss=ov, unless otherwise noted.)
Limtts

Symbol

Test conditions

Parameter

Unit
Min

Typ

Max

tpZV(R~DQ)

Propagation time from read to data output

170

ns

tPZV(A~DQ)

Propagation tIme from address to data output

400

ns

tPYZ(R-DQ)

Propagation time from read to data floating (Note 6)

100

ns

Propagation time from write to data output

400

ns

tPHL(W-P)

0

tPLH(W_P)
tPLH(STB-BF)

Propagation time from strobe to SF lIag

400

ns

tPHL(R-BF)

Propagation time from read to SF flag

400

ns

tpLH(STB4NTR)

PropagatIon time from strobe to Interrupt

400

ns

tPHL(R-INTR)

Propagation time from read to Interrupt

400

ns

tpHL(STB-BF)

Propagation tIme from strobe to SF flag

400

ns

tPLH(W_BF}

Propagation time from write to SF flag

400

ns

tPHL(W_INTR)

Propagation time from write to Interrupt

400

ns

Propagation time from timer input to timer output

400

ns

tpHL( I-OUT)

C L = 150pF

tpLH(; -OUT)

Note 6

7

5-8

Test conditions are not applied.
A.C Testing waveform
Input pulse level
O. 45-2. 4V
Input pulse rise tIme
20ns
20ns
Input pulse fall time
Reference level input
V,H =2V, V'c =0. 8V
VoH=2V, Vo L =0.8V
output

2.4-V2

2Y-

0.45 -A""O.",,8_...;;;O'..:;;8A-

• MITSUBI$HI
~ELECTRIC

MITSUBISHI LSls

M5LS155P
2048·BIT STATIC RAM WITH I/O PORTS AND TIMER
Strobed Output

Strobed Input

K

)

PORT

tSU(P-STB)

\

tplH(STB-BF)

th(STB-p)

II

_\

H~~

tpLHCSTS-tNTR)

\

BF

J

INTR

\
tPHll(~-BF~

\

Q /L

.t

Timer

(Note 8)

5
TIMER IN

TIMER OUT

\.. ___ ":'J

(Note9)

PULSE MODE

riMERMODE
OUT _________________ J ' (Note9)
SQUARE WAVE
Note 8 : The wave form IS shown for the case of counting down from 5 to 1
9 : As long as the Ml mode flag of the timer register is at
hi,gh-Ievel, pulses are continuously output.

5-10

• MITSUBISHI
..... ELECtRIC

MITSUBISHI LSls

MSL81S6P
2048-BIT STATIC RAM WITH I/O PORTS AND TIMER

OPERATION

Table

Data Bus Buffer
This 3-state bidirectional S-bit buffer is used to transfer the
data while input or output instructions are being executed by
the CPU. Command and address information IS also transferred through the data bus buffer.
ReadlWrlte Control Logic
The read/write control logic controls the transfer of data and
commands by interpreting the signals (CE, RD, WR, 10iM,
ALE and RESET) from CPU.
Bidirectional Address/Data Bus (ADo-AD 7)
The bidirectional address/data bus is a 3-state S-bit bus.
The S-bit address is latched in the internal latch by the failing edge of ALE. Then if 10iM input signal is at high-level,
the address of I/O port, counter/timer, or command register
Is selected. If it is at low-level, address of RAM is selected.
The S-bit data is transferred by read input (RD) or write input (WR).
Chip Enable Input (CE)
When CE is at high-level, the address information on
address/data bus is stored in the M5L8156P.
Read Input (RD)
When RD is at low-level, the data bus buffer is active. If 10/
M Input signal is at low-level, the contents of RAM are read
through the address/data bus. If 10iM input is at high-level,
the contents of selected I/O port or counter/timer are read
through the address/data bus.
Write Input (WR)
When WR is at low-level, the data on the address/data bus
are written into RAM if 10iM is at low-level, or they are written into I/O port, counter/timer or command register if 10iM
is at high-level.
Address Latch Enable Input (ALE)
An address on the address/data bus is latched in the
M5LS156P on the falling edge of ALE along with the levels of
CE and 10/M.
.
10lMemory Input (101M)
When 10/M is at low-level, the RAM is selected, while at
high-level the I/O port, counter/timer or command register
are selected.
110 Port A (PAo-PA7)
Port A is an S-bit general-purpose I/O port. Input/output setting is controlled by the system software.
110 Port B (PBo-pa7)
Port B is an S-bit general-purpose I/O port. Input/output setting is controlled by the system software.
1/0 Port C (PCo-PC s)
Port C is a 6-bit I/O port that can also be used to output
control signals of port A (PA) or port B (PB). The functions
of port C are controlled by the system software. When port C
is used to output control signals of ports A or B, the assignment of the signals to the pins is as shown in Table 1.

5-12

1

Pin assignment of control signals of port C

Pin

PCs
PC.
PC3
PC2
PC,
PCa

Function
BSTB
B BF

(port B strobe)

BINTR

(port B Interrupt)

ASTB

(port A strobe)

A BF

(port A buffer full)

AINTR

(port A Interrupt)

(port B buffer full)

Timer Input (TIMER IN)
The signal on this input terminal is used by the counter/timer
for counting events or time. (3MHz max.)
Timer Output (TIMER OUT)
A square wave signal or pulse from the counter/timer is output through this pin when in the operation mode.
Command Register (8 bits)
The command register is an B-bit latched register. The loworder 4 bits (bits 0-3) are used for controlling and determination of the mode of the ports. Bits 4 and 5 are used as
interrupt enable flags for ports A and B when port C is used
as a control port. Bits 6 and 7 are used for controlling the
counter/timer. The contents of the command register are rewritten by output instructions (110 address XXXXXOOO).
Details of the functions of the individual bits of the command
register are shown in Table 2.
Table
Bit

2 Bit functions of the command register
Symbol

0

PA

1

PB

2

PC,

3

PC2

4

lEA

5

IEB

Function
PORT A I/O SET

PORT B I/O SET

1: Output port A
0: Input port A
1. Output port B

O' Input port B
PORT C SET

00. ALTl
11. ALT2
01. ALT3
10' ALT4

PORT A INTERRUPT
ENABLE FLAG
PORT B INTERRUPT
ENABLE FLAG

1. Enable

Inte~rupt

0: Disable interrupt
l' Enable interrupt
0: Disable interrupt

COUNTER/TIMER CONTROL

6

TMl

00. No Influence on counter/timer operation
01. Counter/timer operation discontinued (If not already
stopped)
10: Counter/timer operation discontinued after the current

7

TM2

• MITSUBISHI
. . . . ELECTRIC

counter/timer operation IS completed
11: Counter/timer operation started

MITSUBISHI LSls

M5L8156P
2048·BIT STATIC RAM WITH I/O PORTS AND TIMER

CONFIGURATION OF PORTS
A block diagram of 1 bit of ports A and B is shown in Fig. 1.
While port A or B is programmed as an output port, if the
port is addressed by an input instruction, the contents of the
selected port can be read. When a port IS put In Input mode,
the output latch is cleared and writing into the output latch is

disabled. Therefore when a port is changed to output mode
from input mode, low-level signals are output through the
port. When a reset signal is applied, all 3 ports (PA, PB, and
PC) will be input ports and their output latches are cleared.
Port C has the same configuration as ports A and B in modes ALT1 and ALT2.

M5L8156P

EXTERNAL PIN
( PORT A OR)
PORT B

Note 1. WR PORT=IO/M·WR·CE
(PORT ADDRESS SELECTED)
2. RD PORT=IO/M·RD·CE
(PORT ADDRESS SELECTED)
3. MULTIPLEX CONTROL
1 STROBE INPUT MODE
*2 INPUT MODE
3 OUTPUT MODE
4. MD= 1 : OUTPUT MODE
o : INPUT MODE

*

MD

Configuration for 1 bit of port A or B

Fig. 1
Table

5

XXXXXOOO
XXXXXOO1
XXXXX010
XXXXX011

5-14

The basic functions of the 1/0 ports are shown in Table 5.
The control signal levels to ports A and B, when port C is
programmed as a control port, are shown in Table 6.

Basic functions of I/O ports

Address

Table

*

6

RD

WR

L

H

AD bus - Status register

H

L

Command register - AD bus

L

H

AD bus - Port A

Function

H

L

Port A - AD bus

L

H

AD bus - Port B

H

L

Port B -AD bus

L

H

AD bus - Port C '

H

L

Port C - AD bus

COUNTERITIMER
The counter/timer is composed of a 14-bit counting register
and 2 mode flags. The register has two sections: 1/0
address XXXXX100 is assigned to the low-order 8 bits and II
o address XXXXX101 is assigned to the high-order 6 bits
and timer mode flag 2 bits. The low-order bits 0 - 13 are
used for counting or timing. The counter is initialized by the
program and then counted down to 0." The initial value can
be ranged from 216 to 3FF16. Bits 14 and 15 are used as

Port control signal levels at ALT3 and AL T4

Control Signal

Output mode

Input mode

STB

Input

Input

SF

"L"

"L"

INTR

"H"

"L"

mode flags.
The mode flags select 1 of 4 modes with functions as follows:
Mode 0: Outputs high-level signal during the former
half of the counter operation
Outputs low-level signal during the latter half
of the counter operation

• MITSUBISHI
. . . . ELECTRIC

MITSUBISHI LSls

M5L8156P
2048-BIT STATIC RAM WITH I/O PORTS AND TIMER

TIMING REQUIREMENTS

(T a=-20~75°C, Vcc= 5 V± 5 %, Vss=OV, unless otherwise noted)
Limits

Symbol

Parameter

Test conditions

Min

Typ

Unit

Max

tSU(A-L)

Address setup time before latch

50

ns

theL-A)

Address hold time after latch

80

ns

td{L-RW)

Delay time, latch to read/write

lOa

ns

tweL)

Latch pulse width

lOa

ns

tdCRW-L)

Delay time, read/write to latch

20

ns

tWCRW)

Read/write pulse width

250

ns

tSU(OQ-W)

Data setup time before write

150

ns

theW-DQ)

Data hold time after wnte '

0

ns

tC(RW)

Read/write cycle time

300

ns

tSU(P-R)

Port setup time before read

70

ns

theA-p)

Port hold time after read

50

ns

tWCSTS)

Strobe pulse width

200

ns

tSU(P-STB)

Port setup time before strobe

50

ns

thCSTB-P)

Port hold time after strobe

120

ns

tW (

Timer input high-level pulse width

120

ns

Timer mput low-level pulse width

80

tW

H)

( 1>L)

ns

DC

320

ns

tce. )

Timer input cycle time

tre • )

Timer Input rise time

30

ns

tfe • )

Timer input fall ttme

30

ns

SWITCHING CHARACTERISTICS

(Ta=-20~75°C, Vcc= 5 V± 5 %, Vss=OV, unless otherwise noted.)
Limits

Symbol

Parameter

Test condlttons
Min

Typ

Unit

Max

tpZV(R~DQ)

Propagation time from read to data output

170

ns

tPZV(A-DQ)

Propagation time from address to data output

400

ns

tPVZ(R-DQ)

Propagation time from read to data floatmg (Note 6)

100

ns

Propagation time from write to data output

400

ns

tPLH(STB_BF)

Propagation time from strobe to BF flag

400

ns

tPHL(R-BF)

Propagation time from read to BF flag

400

ns

tPLH(STB-INTR)

Propagation time from strobe to interrupt

400

ns

tPHL(R_INTR)

Propagation time from read to mterrupt

400

ns

tPHL(STB-BF)

PropagatIon time from strobe to BF flag

400

ns

tPLH(W_BF)

Propagation time from write to BF flag

400

ns

tPHL(W-INTR)

Propagation time from write to mterrupt

400

ns

400

ns

0

tpHLCW_P)
tPLHCW-P)

tpHLC '" -OUT)

C L = 150pF

Propagation time from

~Imer

input to timer output

tpLHC '" -OUT)

Note

5-16

Test conditions are not applied.
A.C Testmg waveform
Input pulse level
0, 45~2. 4V
Input pulse rise time
20ns
Input pulse fall time
20ns
Reference level input
V,H =2V, V'L =0. 8V
output
VoH =2V, VoL=0.8V

2.4-V2

2V-

0,45-.-1\""0,,,,8_ _..:;0,c.::.~

• MITSUBISHI
;"ELECTRIC

MITSUBISHI LSla
)

MSL8156P
2048·BIT STATIC RAM WITH I/O PORTS AND TIMER
Strobed Output
PORT

)
I--

'i

INTR

"J;~V

tPLH(W-P)

tPHL(W-P)

/

tPLH(W~/

SF

~ ~"'~-,:~
~f(71 /

Basic Input
PORT

SF

INTR

Timer

(Note 1)

TIMER IN

TiMER OUT
PULSE MODE

'- ____ J

(Note9)

TIMER bUT
,
SQUARE WAVE MODE - - - - - - - - - - - - _____ J (Note 9)
Note 8 : The wave form IS shown for the case of counting down from 5 to 1
9 : As long as the Ml mode flag of the timer register IS at
high-level, pulses are continuously output

5-18

• MITSUBISHI
..... ELECTRIC

MITSUBISHI LSls

MSL82S1AP-S
PROGRAMMABLE COMMUNICATION INTERFACE

Table

OPERATION
The M5L8251 AP-5 interfaces with the system bus as shown
in Fig.l, positioned between the CPU and the modem or terminal equipment, and offers all the functions required for
data communication.

16

ADDRESS BUS

AD
4

IIOR IIOW RESET

C/D

RD

WR

CS

L

L

H

L

L

H

L

L

H

L

H

L

H

H

L

L

Control - Data bus

X

H

H

L

3-Stat. - Data bus

X

X

X

H

3-8tate -

Function
Data bus -

Data in USART

USART - Data bus
Data bus -

Status

Data bus

elK

DATA BUS

8
CID CS

00-07 RD WR RE'SET ClK

M5L8251AP-5

M5L8251AP-5 interface to CPU system bus

When using the M5L8251 AP-5, it is necessary to program, as
the initial setting, assignments for synchronous/asynchronous
mode selection, baud rate, character length, parity check,
and even/odd parity selection in accordance with the communication system used. Once programming IS completed,
functions appropriate to the communication system can be
carried out continuously.
When initial setting of the USART is completed, data communication becomes possible. Though the receiver is always
in the enable state, the transmitter is placed in the transmitter-enable state (T xEN) by a command instruction, and the
application of a low-level signal to the CTS pin prompts
data-transfer start-up. Until this condition is satisfied, transmission is not executed. On receiving data, the receiver informs the CPU that reading for the receiver data in the
USART by the CPU has become possible (the RxRDY terminal has turned to high-level) . Since data reception and
the entry of the CPU into the data-readable state are output
as status information, the CPU can access USART status
without accessing the RxROY terminal.
During receiving operation, the USART checks errors and
gives out status information. There are three types of errors:
parity, overrun, and frame. Even though an error occurs, the
USART continues its operations, and the error state is retained until error reset (ER) is effected by a command instruction. The M5L8251 AP-5 access methods are listed in
Table 1.

5-20

M5L8251AP-5 Access Methods

CONTROL BUS

8

Fig, 1

1

Read/Write Control Logic
This logic consists of a control word register and command
word register. It receives signals from the CPU control bus
and generates internal-control signals for the elements.
Modem Control Circuit
This is a general-purpose control-signal circuit designed to
simplify the interface to the modem. Four types of control
signal are available: output signals OTR and RTS are controlled by command instructions, input signal DSR is given to
the CPU as status information and input signal CTS controls
direct transmission.
Data-Bus Buffer
This is an 8-bit 3-state bidirectional bus through which control words, command words, status information, and transfer
data are transferred. Fig. 2 shows the structure of the databus buffer.

%210
,

7

TO INT ERNAL
ATA BUS

Do

I

Do

STATUS BUFFER

I

RECEIVE-DATA
BUFFER

I-

CONTROL BUFFER

~

~

~

Y

TRANSMIT-DATA
BUFFER

Fig.

2

~

0

f----

Data-bus-buffer structure

Transmit Buffer
This buffer converts parallel-format data given to the databus buffer in to serial data with addition of a start bit, stop
bits and a parity bit, and sends out the converted data
through the TxD pin based on the control signal.
Transmit-Control Circuit
This circuit carries out all the controls required for serial
data transmission. It controls transmitter data and outputs the
signals required by external devices in accordance with the
instructions of the read/write control logic.

• MITSUBISHI
' " ELECTRIC

MITSUBISHI LSls

MSL82S1AP-S
PROGRAMMABLE COMMUNICATION INTERFACE

Clear-To-Send Input (CTS)
When the TxEN bit (Do) of the command instruction has
been set to 1 and the CTS input is low-level serial data is
sent out from the TxD pin. Usually this is used as a clear-tosend signal for the modem
Note: CTS indicates the modem status as follows:
ON means data transmission is possible;
OFF means data transmission is impossible.
Transmitter-Empty Output (TxEMPTV)
When no transmisison characters are left in the transmit buffer, this pin enters the high-level state. In the asynchronous
mode, the following transmission character is shifted to the
transmit buffer when it is loaded from the CPU. Thus, it is
automatically reset. In the synchronous mode, a SYNC character is loaded automatically on the transmit buffer when no
transfer-data characters are left. In this case, howeyer, the
TxEMPTY does not enter the low-level state when.a SYNC
character has been sent out, since TxEMPTY= "H" denotes
the state in which there is no transfer character and one or
two SYNC characters are being transferred or the state in
which a SYNC character is being transferred as a filler.
TxEMPTY is unrelated to the TxEN bit of the command instruction.
Transmission-Data Output (TxD)
Parallel-format transmission characters loaded on the
M5L8251 AP-5 by the CPU are a~sembled into the format designated by the mode instruction and sent in serial-data form
via the TxD pin. Data is output, however, only in cases
where the Do bit (T xEN) of the command instruction is 1 and
the CTS terminal is in the low-level state. Once reset, this
pin is kept at the mark status (high level) until the first character is sent.
Clock Input (ClK)
This system-clock input is required for internal-timing generation and is usually connected to the clock-output (CLK)
pin of the M5L8085AP. Although there is no direct relation
with the data-transfer baud rate, the clock-input (CLK) frequency is more than 30 times the TxC or RxC input frequency in the case of the synchronous system and more than 4.5
times in the case of the asynchronous system.
Reset Input (RESET)
Once the USART is shifted to the idle mode by a high-level
input, this state continues until a new control word is set
Since this is a master reset, it is always necessary to load a
control word following the reset process. The reset input requires a minimum 6-clock pulse width.
Data-Set Ready Input (DSR)
This is a general-purpose input signal, but is usually used as
a data-set ready signal to test modem status. Its status can
be known from the status reading process. The 07 bit of the
status information equals 1 when the OSR pin is in the lowlevel state, and 0 when in the high-level state.
OSR="L"-+07 bit of status information=l
OSR="H"-+07 bit of status information=O
Note: OSR indicates modem status as follows:

5-22

ON means the modem can transmit and receive;
OFF means it cannot.
Request-To-Send Output (RTS)
This is a general-purpose output signal but is used as a request-to-send signal for the modem. The RTS terminal is
controlled by the 0 5 bit of the command instruction. When 0 5
is equal to 1, RTS="L", and when 0 5 is 0, RTS="H".
Command register D5=1-+RTS="L"
Command register D5=0-+RTS="H"
Note: RTS controls the modem transmission carrier as follows:
ON means carrier dispatch;
OFF means carrier stop.
Data-Terminal Ready Output (DTR)
This is a general-purpose output signal, but is usually used
as a data-terminal ready or rate-select signal to the modem.
The OTR pin is controlled by the 01 bit of the command instruction; if 01=1, OTR="L", and if 0 1=0, OTR="H".
01 of the command register=1-+0TR="L"
01 of the command register=O-+OTR="H"
Receiver-Clock Input (RxC)
This clock signal controls the baud rate for the sending in of
characters via the RxO pin. The data is shifted in by the rising edge of the RxC signal. In the synchronous mode, the
RxC frequency is equal to the actual baud rate. In the asynchronous mode, the frequency is specified as 1, 16, or 64
times the baud rate by mode setting. This relationship is parallel to that of TxC, and in usual communication-line systems the transmission and reception baud rates are equal.
The TxC and RxC terminals are, therefore, used connected
to the same baud-rate generator.

PROGRAMMING
It is necessary for the M5L8251 AP-5 to have the control word
loaded by the CPU prior to data transfer. This must always
be done following any resetting operation (by external RESET pin or command instruction IR). There are two types of
control words: mode instructions specifying general operations required for communications and command instructions
to control the M5L8251 AP-5 actual operations.
Following the resetting operation, a mode instruction must
be set first. This instruction sets the synchronous or asynchronous system to be used. In the sysnchronous system, a
SYNC character is loaded from the CPU. In the case of the
bi-sync system, however, a second SYNC character must be
loaded in succession.
Loading a command instruction makes data transfer possible. This operation after resetting must be carried out for initializing the M5L8251 AP-5. The USART command instruction
contains an internal-reset I R instruction (Dsbit) that makes it
possible to return the M5L8251 AP-5 to its reset state. The initialization flowchart is shown in Fig. 3 and the modeinstruction and command-instruction formats are shown in
Figs. 4 and 5.

•
MITSUBISHI
. . . . ELECTRIC

MITSUBISHI LSls

MSL82S1AP-S
PROGRAMMABLE COMMUNICATION INTERFACE

Asynchronous Transmission Mode
When data characters are loaded on the M5L8251 AP-5 after
initial selling, the USART automatically adds a start bit (0),
an odd or even parity bit specified by the mode instruction
during initialization, and a specified number of stop bits (1).
After that, the assembled data characters are transferred as
serial data via the TxD pin, if transfer is enabled (T xEN =
l·CTS="L"). In this case, the transfer data (baud rate) is
shifted by the mode instruction at a rate of 1X, 1/16X, or 1I
64X the TxC period.
If the data characters are not loaded on the M5L8251 AP-5,
the TxD pin enters a mark state ("H"). When SBRK is programmed by the command instruction, break characters (0)
are output continuously through the TxD pin.
Asynchronous Reception Mode
The RxD line usually starts operations in a mark state ("H"),
triggered by the falling edge of a low-level pulse when it
comes to this line. This signal is again strobe at the middle
of the bit to confirm that it is a perfect start bit. The detection of a second low-level indicates the validity of the start
bit (again strobe is carried out only in the case of 16X and
64X) . After that, the bit counter inside the M5L8251 AP-5
starts operating; each bit of the serial information on the RxD
line is shifted in by the rising edge of RxC, and the data bit,
parity bit (when necessary), and stop bit are sampled at the
middle position.
The occurrence of a parity error causes the setting of a parity-error flag. If the stop bit is 0, a frame error flag is sel.
Attention should be paid to the fact that the receiver requires only one stop bit even though the program has designated 1/1.5 or 2 stop bits.
Reception up to the stop bit means reception of a complete
character. This character is then transferred to the receiverdata buffer shown in Fig.2, and the RxRDY becomes active.
In cases where this character is not read by the CPU and

where the next character is transferred to the receiver-data
buffer, the preceding character is destroyed and an overrunerror flag is sel.
These error flags can be read as the M5L8251 AP-5 status information. The occurrence of an error does not stop USART
operations. The error flags are cleared by the ER (D 4 bit) of
the command instruction.
The asynchronous-system transfer formats are shown in
Figs. 6 and 7.
Synchronous Transmission Mode
In this mode the TxD pin remains in the high-level state until
initial selling by the CPU is completed. After initialization,
the state of CTS="L" and TxEN =1 enables serialtransmission of characters through the TxD pin. Then, data characters are sent out and shifted by the falling edge of the TxC
signal. The transmission rate equals the TxC rate.
Thus, once data-character transfer starts, it must continue
through the TxD pin at the same rate as that of TxC. Unless
data characters are provided from the CPU before the transmiller buffer becomes empty, one or two SYNC characters
are automatically output from the TxD pin In this case, it
should be noted that the TxEMPTY pin enters the high-level
state when there are no data characters left in the
M5L8251 AP-5 to be transferred, and that the low-level state
is not entered until the USART is provided with the next data
character from the CPU. Care should also be taken over the
fact that merely selling a command instruction does not
effect SYNC-character insertion, because the SYNC character insertion is enabled after sending out the first data char-.
acter.
In this mode, too, break characters are sent out in succession from the T"D pin when SBRK is designated (D 3 = 1) by
a command instruction.

CPU-USART (5-8-BIT/CHARACTER)
DATA

CH~RACTER

ASSEMBLED
GTARTIDATA
IT

DATA

CH~RACTER

I

FORMAT

(5-8) PARITY
IT

RECEIPTION FORMAT

STO~
BITSI
(1, 1.5. 2)

I

STBAITRTI

L.~_J.L..

ST0{?m
__~:";;~~__...L.2W....L:.:..,(l,
1.5, 2)

USART-CPU (5-8-BIT/CHARACTER)
I DATA
Note

:

CHARA~TER

(5-8)

I

When the data character is 5, 6, or 7 bits/character
length, the unused bits (for USART- CPU) are set to

O.

Fig.

5-24

6

Asynchronous transmission format I
(transmission)

Fig.

7

Asynchronous transmission format II (reception)

• MITSUBISHI
"ELECTRIC

MITSUBISHI LSls

MSL82S1AP-S
PROGRAMMABLE COMMUNICATION INTERFACE

OE:

STATUS INFORMATION
The CPU can always read USART status by setting the C/O
to high-level and RO to low-level.
The status information format is shown in Fig. 10. In this format RxROY, TxEMPTY and SYNOET have the same definitions as those of the pins. This means that these three
pieces of status information become high-level when each
pin is 1. The other status information is defined as follows:
OSR:
When the OSR pin is in the low-level state, status
information OSR becomes 1.
FE:
The occurrence of a frame error in the receiver
section makes the status information FE=1.

PE:
TxROY:

11
I

FOR DSR

The occurrence of an overrun error in the receiver
section makes the status information OE=1.
The occurrence of a parity error in the receiver
section makes this status information PE=l.
This information becomes 1 when the transmit data
buffer is empty. Be careful because this has a
different meaning from the TxROY pin that enters
the high-level state only when the transmitter buffer is empty, when the CTS pin is in the low-level
state, and when TxEN js 1.

"L" 0 FOR DSR

"H"

SAME DEFINITION AS SYNDET/SD PIN

I
I

FE IS SET WHEN A VALID STOP BIT IS NOT DETECTED AT THE END OF EVERY CHAR'l
ACTER (ASYNC ONLY) IT IS RESET BY THE ER BIT OF THE COMMAND INSTRUCTION
FE DOES NOT INHIBIT OPERATION OF THE M5L8251AP·5
OE IS SET WHEN THE CPU DOES NOT READ A CHARACTER BEFORE THE NEXT ONE
BECOMES AVAILABLE IT IS RESET BY THE ER BIT OF THE COMMAND INSTRUCTION
OE DOES NOT INHIBIT OPERATION OF THE M5L8251AP·5

1

PE IS SET WHEN A PARITY ERROR IS DETECTED IT IS RESET BY THE ER BIT OF THE
COMMAND INSTRUCTION PE DOES NOT INHIBIT OPERATION OF. THE M5L8251AP-5

I

I I 8~~ I
DSR

0,

Fig.

06

FE

Os

I

OE

0,

I

PE

I

Tx E

0,

10 Status information

02

I
I

FOR TRANSMIT DATA SUFFER IS EMPTY

I

Do

(c/D="H", WR="L")

APPLICATION EXAMPLES
Fig. " shows an application example for the M5L8251 AP-5
in the asynchronous mode. When the port addresses of the
M5L8251 AP-5 are assumed to be 00:1:1 and 01:1:1 in this figure,
initial setting in the asynchronous mode is carried out in the
following manner:
Mode setting
MVI
A,86:1:1
OUT
01:1:1
Command instruction
MVI
A,27:1:1
OUT
01:1:1
In this case, the following are set by mode setting:
Asynchronous mode
6 bits/character
Parity enable (even)
1. 5 stop bits
Baud rate: 16X
Command instructions set the following
RTS=1""RTS pin="L"
Rx E=1
OTR=1""OTR pin="L"
TxEN=1
When the initial setting is complete, transfer operations are
allowed. The RTS pin is initially set to the low-level by setting RTS to 1, and this serves as a CTS input with TxEN

5-26

SAME DEFINITION AS TxEMPTY PIN
SAME DEFINITION AS RxRDY PIN

1--------11
I
I =ty I ~DY I
0,

I
I

being equal to 1. For this reason the same definition applies
to the status and pin of TxROY, and 1 is assigned when the
transmit-data buffer is empty. Actual transfer of data is carried out in the following way:
IN
01 :1:1
Status read
The IN instruction prompts the CPU to read the USART's
status. The result is; if the TxROY equals 1 transmitter data is
sent from the CPU and written on the M5L8251 AP-5. Transmitter data is written in the M5L8251 AP-5 in the following
manner:
MVI
A,2D:I:I
20,6 is an example of transmitter data.
USART+-(A)
OUT
00:1:1
Receiver data is read in the following manner:
IN
00:1:1
(A)+-USART
In the above example, the status information is read and as
a result, the transmitter data is written and read. Interruption
processing by using the TxROY and RxROY pins is also
possible.
Fig. 12 shows the status of the TxO pin when data written in
the USART is transferred from the CPU. When the data
shown in Fig.1 2 enters the RxO pin, data sent from the
M5L8251 AP-5 to the CPU becomes 20 16 and bits 06 and 07
are treated as 0.,

•
MITSUBISHI
. . . . ELECTRIC

MITSUBISHI LSls

MSL82S1AP-S
PROGRAMMABLE COMMUNICATION INTERFACE
ABSOLUTE MAXIMUM RATINGS
Symbol

Parameter

Vee

Power-supply voltage

V,

Input voltage

Vo

Output voltage

Conditions

With respect to vss

Pd

Power dissipation

Topr

Operating free-air temperature range

Tstg

Storage temperature range

Ta=25'C

Ratings

Unit

-0.5-7

V

-0.5-7

V

-0.5-7

V

1000

mW

-20-75

'c
'c

-65-150

(Ta~-20-7S'C, unless otherwise noted)

RECOMMENDED OPERATING CONDITIONS

Limits

Symbol

Parameter

Unit
Min

Vee

Supply voltage

Vss

Power-supply voltage (GN D)

Max

5

5.25

4.75

ELECTRICAL CHARACTERISTICS
Symbol

Nom

0

V
V

(Ta=-20-7S'C, Vee=SV±S%, Vss=OV, unless otherwise noted)
Limits

Parameter

Test conditions
Min

Typ

Max

Unit

V'H

High-level input voltage

2.0

Vee

V

V'L

LOW-level input voltage

-0.5

0.8

V

V OH

High-level output voltage

IOH=-400!,A

VOL

LOW-level output voltage

IOL=2.2mA

Icc

Supply current from Vee

All outputs are high-level

I'H

High-level Input current

VI=VCC

IlL'

Low-level input current

V,=O.45V

loz

Off-state input current

Vo=O.45V- Vec

C,

Input terminal capaCitance

GIIO

Input/output terminal capaCitance

5-28

•

2.4

V
0.45

V

100

mA

-10

10

I-/A

-10

10

I-/A

-10

10

I-/A

Vec=Vss, f-1 MHz, 25mV rms , T.=25'C

10

pF

Vcc=Vss, f=lMHz, 25mV rms , Ta=25'C

20

pF

MITSUBISHI

. . . . ELECTRIC

I

MITSUBISHI LSls

M5L8251AP-5
PROGRAMMABLE COMMUNICATION INTERFACE

,SWITCHING CHARACTERISTICS

(Ta=-20-75'C, Vcc =5V±5%, Vss=OV, unless otherwise noted)
Limits

Symbol

Test conditions

Parameter

Min
tPZV(R-OQ)

Output data enable time after read (Note8)

tPVZ(R-OQ)

Output data disable time after read

CL=150pF

IpZV(TxC-TxD)

TxD enable time after falling edge of TxC

IpLH(CLS-TxR)
tPHL(W-TJlR)

IPL.H (ClB-RxR)

Propagation time from center of last bit to RxRDY (Note9)

Typ

Unit
Max
200

ns

100

ns

1

I-'S

Propagation time from center of last bit to TxRDY (Noteg)

8

tcc. )

Propagation time from write data to TxRDY clear (Noteg)

400

10

26

ns
tcc. )

tPHl(R-RxA)

Propagation time from read data to RxRDY clear (Noteg)

tPLH(AxC-SYD)

Propagation time from rising edge of RxC to internal SYNDET (Noteg)

26

tpL.HCCLB-TxE)

Propagation time from cenU,r of last bit to TxEMPTY (Noteg)

20

tcc. )

tPHLCW-Cl

Propagation time from rising edge of WR to control (Note9)

8

tcc. )

-

Note 8 : Assumes that address is vaild before falling edge of RD
9 : Status-up date can have a maximum delay of 28 clock periods from the event affecting the status.
10: Input pulse level
0.45-2. 4V Reference level
Input V,H =2V, VIL =0. 8V
Input pulse rise time
20ns
Output VoH =2V, VOL =0. 8V
Input pulse fall time
20ns

5-30

•
MITSUBISHI
..... ELECTRIC

400

ns
tcc. )

MITSUBISHI LSI.

MSL82S1AP·S
PROGRAMMABLE COMMUNICATION INTERFACE

,

Write Control Cycle (CPU-USART)

cio

J

~V

tSU(A_W)

~I\

tSU(A-W)

Iw(w)

~~

tSU(OQ-w)

)

D,-Do
(DATA INPUT)

(

VAll

tPHL(W_C)

}

DTR. RTS

Read Control Cycle (USART-CPU)
Isu(c

R)

}
\
C/O

/

tSU(A_R)

Ih(R-A)

ISU(A_R)

Ih(R_A)

IW(R)

j
IpVZ(R-DQ)

tPZV(R_DQ)

D,-Do
(DATA OUTPUT)

5-32

//)
\\'

•
MITSUBISHI
"'ELECTRIC

~

VALID

V
~

MITSUBISHI LSls

MSL82S1AP-S
PROGRAMMABLE COMMUNICATION INTERFACE

Transmitter Control & Flag Timing (Async Mode)

c/o

]

\~~'~Cl~~/
WR-TxEN

____~\~/_____\~~/______~1

\

WR-DATA 1 WR-DATA 2
WR-DATA 3
WR-DATA 4
WR-SBRK
~------~ ~--------~ ~---------------,

r------

TxRDY
(STATUS)

TxEMPTY

BREAK STATE
Note 11: Example format = 7 bits/character with parity & 2 stop bits
12: TxRDY(pin) = "H" ~(Transmit-data buffer is empty)· (TxEN = 1)· (CTS= "L")
13: TxRDY(status) = 1 ~(Transmit-data buffer is empty)

Receiver Control & Flag Timing (Async Mode)

c/o

OJ \'-____......1\---',

LD

\~

__~\'___'I___. . . . I. V \0

___________________~R=,D DATrA~1__________________~RD~DATrA~3--------~R~D~A~LLOrD-A-TA------------______

+-___________W..;...,R-RxE

WR-Rrx_E_______________t-______________________.....,____...,WR-Er_R________

BD
(PIN)

OE
(STATUS)

RxRDY

S

S0123456P~S0123456P~

RxD

BREAK STATE

Note 14: Example format = 7 bits/character with panty & 2 stop bits

5-34

• MITSUBISHI
..... ELECTRIC

WR-RxE

MITSUBISHI LSls

MSL8253P-S
PROGRAMMABLE INTERVAL TIMER

DESCRIPTION
The M5L8253P-5 is a programmable general-purpose timer
device developed by using the N-channel silicon-gate EDMOS process. It offers counter and timer functions in systems using an 8-bit parallel-processing CPU.
The use of the M5L8253P-5 frees the CPU from the execution of looped programs, count-operation programs and
other simple processing involving many repetitive operations, thus contributing to improved system throughputs.
The M5L8253P-5 works on a single power supply, and both
its input and output can be connected to a TTL circuit.

PIN CONFIGURATION (TOP VIEW)

vee (5V)
23 ~ WR WRITE INPUT
BIDIRECTIONAL
DATA BUS

•
•
•
•
•
•

~ CS ~~~;.SElECT

RD READ INPUT

I

20 ~ A,
19 ~ Ao

0,-

7

18 ~CLK2 CLOCK INPUT

00 -

8

17 ~OUT2 g~¥~JiR
16 ~ GATE2 GATE INPUT

C~~~;~~ OUTO~

Single 5V supply voltage
TTL compatible
Clock period: DC-2.6MHz
3 independent built-in 16-bit down counters
6 counter modes freely assignable for each counter
Binary or decimal counts

~

21

02- 6

CLOCK INPUT ClKO~ 9

FEATURES

22

ADDRESS
INPUTS

10

15 ~ ClK1 CLOCK INPUT

GATE INPUT GATEO~ 11

14 ~GATE1 GATE INPUT

(OV) Vss

"-1-_ _ _- - '13
-

Outline

~OUT1 g3¥~JfR

24P4

APPLICATION
Delayed-time setting, pulse counting and rate generation in
microcomputers.

FUNCTION
Three independent 16-bit counters allow free programming
based on mode-control instructions from the CPU. When
roughly classified, there are 6 modes (0-5). Mode 0 IS mainly used as an interruption timer and event counter, mode 1
as a digital one-shot. modes 2 and 3 as a rate generator,
mode 4 for a software triggered strobe, and mode 5 for a

hardware triggered strobe. The count can be monitored and
set at any time. The counter operates with either the binary
or BCD system.

BLOCK DIAGRAM

CLKO

CLOCK INPUT
GATE INPUT
COUNTER OUTPUT

BIDIRECTIONAL
DATA BUS

CLOCK INPUT
GATE INPUT
COUNTER OUTPUT

READ INPUT

CLOCK INPUT

WRITE INPUT

GATE INPUT

CHIP-SELECT INPUT
ADDRESS INPUTS {

5-36

COUNTER OUTPUT
A120
19

Ao

INTERNAL
DATA BUS
I
_____________ - - l

• MITSUBISHI
~ELECTRIC

MITSUBISHI LSls

MSL8253P-S
PROGRAMMABLE INTERVAL TIMER

Table

Basic Functions

CS

RD

WR

A,

Ao

L
L
L

H

a
a

a

Data bus-Counter 0

H

1

Data bus-Counter 1

H

L
L
L

1

a

Data bus-Counter 2

L

H

L

1

1

Data bus-Control-word register

L
L
L

L

H

a

a

Data bus-Counter 0

L
L

H

a

1

Data bus-Counter 1

H

1

a

Data bus-Counter 2

L

L

H

1

1

3-state

H

X

X

X

X

3-state

L

H

H

X

X

3-state

Function

eSC(Select Counter)
SCl
a

sca

a

Select counter 0

a

1

Select counter 1

1

a

Select counter 2

1

1

Prohibited combination

e RL(Read/Load)
RLl

a

RLa
a

a

1

Read/load low-order 8 bits only

1

a

Read/load high-order 8 bits only

1

1

Read/load low-order 8 bits and then high-order 8 bits

Counter Latch Command

eM(Mode)

D,
D7
D6
D5
D3
SCl
RLa
M2
sca
RLl
f--sc
RL
I
I

I

Fig. 1

5-38

I

I

I

I

I

b

Ma
a

a

a

1

Model

X

1

a

Mode2

ModeO

X

1

1

Mode3

1

a

a

Mode4

1

a

1

Mode5

Binary counter (l6-bit)
\

D2
Ml
M

Ml

a

ieBCaD

,

~~,

M2

I

D,
Ma

Do

1

I
I BCD
BCD-j
I

Control-Word Format

•
MITSUBISHI
"ELECTRIC

Binary-coded decimal counter (4 decades)

I
I

MITSUBISHI LSls

MSL82S3P-S
PROGRAMMABLE INTERVAL TIMER

ClK

CLK

WR

GATE

4

3

OUT(GATE="H")

GATE~
OUT

Fig. 4

OUT(n=4)

LJ

GATE

4
1 4 3
LJr-.......
..:.......;t...r-

4

1

Mode 2

3

OUT(n=4)

Fig. 7

Mode 5

COUNTER MONITORING

Read-on-the-Fly Operation

Sometimes the counter must be monitored by reading its
count or using it as an event counter. The M5L8253P-5 offers
the following two methods for count reading:

This method makes it possible to read the current count
without affecting the count operation at all. A special counter-latch command is first written in the control-word register. This causes latching of all the instantaneous counts to
the register, allowing retention of stable counts. An example
of a program to execute this operation for counter 2 is given
below.
MVI
A, 1000XXXX .... D5 = D4 = 0 designates counter
latching
OUT
n 1 .... n1 is the control-word-register address
IN
n3 .... n3 is the counter 2 address
MOV
D, A
IN
n3
MOV
E, A
In this example, the IN instruction is executed twice. Due to
the internal logic of the M5L8253P-5 it is absolutely essential
to complete the entire reading procedure. If 2 bytes are
programmed to be read, then two bytes must be read before
any OUT instruction can be executed to the same counter.

Read Operation
The count can be read by designating the address of the
counter to be monitored and executing a simple I/O read
operation. In order to ensure correct reading of the count, it
is necessary to cause the clock input to pause by external
logic or prevent a change in the count by gate input. An example of a program to read the counter 1 count is shown below. If RL1, RLO=l, 1 has been specified in the control word,
the first IN instruction enables the low-order 8 bits to be read
and the second IN instruction enables the high-order 8 bits.
IN
n 2 .... n2 is the counter 1 address
MOV
D,A
IN
n2
MOV
E, A
The IN instruction should be executed once or twice by the
RLl and RLO designations in the control-word register.

5-40

• MITSUBISHI
. . . . ELECTRIC

MITSUBISHI LSls

MSL82S3P-S
PROGRAMMABLE INTERVAL TIMER

TIMING REQUIREMENTS

(T a=-20-75'C, Vcc= 5 V±10%, Vss=

°

V, unless otherwise noted)

Read cycle
Symbol

Parameter

limits

Test conditions
Min

tW(R)

Read pulse width

tsU{A~R)

Address setup time before read

th(R-A)

Address hold time after read

treC(R)

Read recovery time

Unit
Typ

Max

300

ns

30

ns

5

ns

1000

ns

Write cycle
Symbol

T est conditions

Parameter

Limits
Min

Unit
Typ

-,---",.-

Max

tW(W)

Write pu Ise width

300

ns

tSU(A-W)

Address setup time before wnte

30

ns

theW-A)

Address hold time after write

30

ns

tsuCOQ-W) Data setup time before write

250

ns

30

ns

th(W-DQ)

Data hold time after wnte

trec(w)

Write recovery time

----

1000

ns

Clock and gate timing
Limits
Test conditions

Parameter

Symbol

Unit
Min

Typ

Max

tW (  H)

Clock high pulse width

230

tW (

Clock low pulse width

150

tc (' )

Clock cycle time

380

tW(GH)

Gate high pulse width

150

sn

tWCGL)

Gate low pulse width

100

ns

tsu(G-'" )

Gate setu p time before clock

100

ns

th<1-G)

Gate hold time after clock

50

ns

1>

L)

SWITCHING CHARACTERISTICS

(Ta=-20-75'C, Vcc= 5 V±10%, Vss=

ns
ns

DC

ns

°

V, unless otherwise noted)
Limits

Parameter

Symbol

Test conditions

Unit
Min

Max
200

ns

100

ns

Propagation time from gate to output

300

ns

Propagation time from clock to output

400

ns

tPZV(R-OQ)

Propagation time from read to output

tPVZ(R_OQ)

Propagation time from read to output floating (Note 2 )

tPXV(G-OUT)
tpXV( ¢ -OUT)

25

CL=150pF

Notel: A C Testing waveform
Input pulse level
Input pulse rise time
Input pulse fall time
Reference level mput
output
2 : Test conditIOn is not applied

0. 45~2.4V
20ns
20ns
V'H=2. 2V, VIL =0. BV
VoH=2.0V, VOL =0. BV

2.4 --v'2.2

2.2V-

0. 45 --""'...0.....
8 _..;0......
8"Input

5-42

Typ

• MITSUBISHI
..... ELECTRIC

°

2.0V~O;;,.'8~...:::.0•.::.8" -

2.4:X 2

0. 45

MITSUBISHI LSls

MSL82SSAP-S
PROGRAMMABLE PERIPHERAL INTERFACE

DESCRIPTION
The M5L8255AP-5 is a family of general-purpose programmable inputl output devices designed for use with an 8-bit/16bit parallel CPU as input/output ports. Device is fabricated
using N-channel silicon-gate ED-MOS technology for a single supply voltage. They are simple input and output interfaces for TTL circuits, having 24 input/output pins which correspond to three 8-bit input/output ports.

PIN CONFIGURATION (TOP VIEW)
INPUT/OUTPUT [ : : : :
PORTSA PA,-

INPUT/OUTPUT
PORTS A

PAoREAD INPUT
CHIP

RD~

S~~~Si CS~

35 -

RESET RESET INPUT

(Ov) Vss
PORT ADDRESS { A, ~
INPUTS Ao~

FEATURES
•
•
•
•
•

Single 5V supply voltage
TTL compatible
Darlington drive capability
24 programmable 1/0 pins
Direct bit set/reset capability

BI-DIRECTIONAL
DATA BUS

INPUT/OUTPUT
PORTS C

APPLICATION
Input/output ports for microprocessor
INPUT/OUTPUT
PORTS B

FUNCTION
These PPls have 24 input/output pins which may be individually programmed in two 12-bit groups A and B with
mode control commands from a CPU. They are used in three
major modes of operation, mode 0, mode 1 and mode 2.
Operating in mode 0, each group of 12 pins may be programmed in sets of 4 to be inputs or outputs. In mode 1, the 24
1/0 terminals may be programmed in two 12-bit groups,
group A and group B. Each group contains one 8-bit data
port, which may be programmed to serve as input or output,
and one 4-bit control port used for handshaking and interrupt
control signals. Mode 2 is used with group A only, as one 8-

~

_ _ _ _-r- -PB 3

Outline

40P4

bit bidirectional bus port and one 5-bit control port. Bit set/
reset is controlled by CPU. A high-level reset input (RESET)
clears the control register, and all ports are set to the input
mode (high-impedance state).

BLOCK DIAGRAM

1----------------

t=
t=~-'

READ INPUT RD
WRITE INPUT WR
ADDRESS
INPUTS

6

J AI 8

1Ao

9

3
->-

1

GROUP A
PORT C
J(MOST SIGNIFI
CANT 4 BITS)

8-BIT
INTERNAL
DATA BUS

4

29~

0, 3
0, 33>------Do 4~

5-44

~H

8

0, 30~ DATA BUS
3 ) - - - BUFFER

1

I
L;...

,..,.
f.-..;..

l

1

0"

;:~; ~::

8

I

~

0,
Os
DATA BUS

~

8
8

CONTROL
LOGIC
I--

RESET INPUT RESET 3
6

GROUP
A
CONTROL

GROUP
A
PORT A
(8-BIT)

GROUP
B
CONTROL

8
8

L

11

GROUP B
PORT C
WLEAST SIGNIFI
CANT 4 BITS)

PAs
4
1

2
3
4

:1
~

1~

i----'GROUP
B
PORT B
(8-BIT)

8

• MITSUBISHI
"-ELECTRIC

PA., INPUT/OUTPUT
PA3 PORTSA
PA,
PA,
PAo
PC,
PC,
PCs
PC, INPUT/OUTPUT
PC3 PORTS C
PC,
PC,
PCo

=~:1

PBs
PB, INPUT/OUTPUT
2 PB3i PORTS B
PB,
PB,
PBo

t _______________'_______________ ~
L.,..

26

PA,
PA,

MITSUBISHI LSls

MSL82SSAP-S
PROGRAMMABLE PERIPHERAL INTERFACE

BASIC OPERATING MODES
The PPI can operate in anyone of three selected basic
modes.
(group A, group B)
Mode 0: Basic input/output
(group A, group B)
Mode 1: Strobed input/output
(group A only)
Mode 2: Bidirectional bus
The mode of both group A and group B can be selected independently. The control word format for mode set is shown
in Fig. 2.

,-~~~~~~~

Mode set flag

I Active -

1

07 06 05 04 03 0, 0, Do
111 0 10 10101 0 111 0 1

07 06 05 04 03 0, 0, Do
11101010101011111

07 06 05 04 03 0,0, Do
111 0 10 10111 0 10 101

07 06 05 04 03 0, 0, Do
11101010111010111

I

, - - - - - - - - Group A mode set
Mode 0 06. 05 - 0, 0
Mode 1 06, 05 = 0, 1
Mode 2 06, 05 = 1, X
, - - - - - Port A Input/output set
output - 0
_ Input = 1
.

I

I

I

PA7-PAo

I

Port C (high-order 4 bits) Input/output set

I
~
I
I

output
0
Input = 1

I
,--'----,

output 0
Input =1

1.

07 06 05 04 03 02 0, Do
11101010111011101

07 06 05 04 03 0, 0, Do
11101010111011111

07 06 05 04 03 0, 0, Do
11101011101010101

07 06 05 04 03 02 0, Do
11101011101010111

I,-port C (high-order 4 bits) input/output set

10710610510410310,1 0,1001

Fig. 2

I
I

Group B mode set
Mode 0 - 0
Mode 1 = 1
Port B Input/output set

I

output
0
Input = 1

I

Control word format for mode set.

Mode 0 (Basic Input/Output)

This functional configuration provides simple input and output operations for each of the 3 ports. No "handshaking" is
required; data is simply written in, or read from, the specified port. Output data from the CPU to the port can be held,
but input data from the port to the CPU cannot be held. Any
one of the 8-bit ports and 4-bit ports can be used as an input
port or an output port. The diagrams following show the
basic input/ output operating modes.

5-46

07 06 Os 04 03 02 0, Do

111010111010111n

07 06 05 04 030, 0, Do
11101011111010101

07 06 05 04 03 0, 0, Do
11101011111010ln

PA7-PAo

PA7-PAo
07 06 05 04 03 0, 0, Do
11101010101010101

07 06 Os 0 4 03 02 0, Do

11101011101011101

0 7 06 05 04 03 0, 0, Do
11101010101010111

07 06 05 04 03 02 0, Do
11 0 0 1111 0 11 10 1

• MITSUBISHI
...... ELECTRIC

II

I

MITSU~ISHI

LSls

MSL82SSAP-S
PROGRAMMABLE PERIPHERAL INTERFACE

MODE 1 (PORT A)
8

MODE 1 (PORT B)

OBFA

OBFB

ACKA

ACKB

INTRA

INTRB

WR
1/0

WR

CONTROL WORD

WR
OBF
ACK
INTR

CONTROL WORD
0, D, 05 04 0, 0, 0, Do

PORT
OUTPUT

11IXlXlXlXlllOlXl

Note 2.

o=OUTPUT

Fig. 5

An example of mode 1 output state

Fig. 6

When INTE is low-level. then the output of INTR is
aways low-level

Timing diagram

PA,-PAo
OBF A

WR

ACK A

IBFA

INTRA

INTRA

1/0

1/0

STBB

RD
PC,
PCo

INTRB

ACKB
PORT A (STROBED INPUT)
PORT B (STROBED OUTPUT)

o=OUTPUT

5-48

PCo

INTRB

CONTROL WORD

CONTROL WORD

Fig. 7

OBF B

WR

IBFB

PORT A (STROBED OUTPUT)
PORT B (STROBED INPUT)

STBA

RD

Mode 1 port A and port B 1/0 example

O=OUTPUT

Fig. 8

• MITSUBISHI
. . . . ELECTRIC

Mode 1 port A and port B 1/0 example

MITSUBISHI LSls

MSL82SSAP-S
PROGRAMMABLE PERIPHERAL INTERFACE

4.

Control Signal Read

Tabl~

In mode 1 or mode 2 when using port C as a control port, by
CPU execution of an IN instruction, each control signal and
bus status from port C can be read.

5.

Read-out control signals

~
Mode

Control Word Tables

Mode 1, input

Control word formats and operation details for mode 0, moqe
1, mode 2 and set/reset control of port C are given in Tables
3, 4, 5 and 6, respectively.
Table

2

D?

06

I/O

1/0

05

OBFA INTE,

0,

02

03

Do

IBFA INTEA INTRA INTEe IBFe INTRe

Mode I, oolpul OBFA INTEA
Mode 2

0_

I/O

INTRA INTEe OBFe INTRe

I/O

IBFA INTE2 INTRA

By group B mode

3

Mode 0 control words

D7

D6

D5

D,

D,

D2

D,

Do

Hexadecimal

PortA

Port C (high-order 4 bits)

Port C (low-order 4 bits)

Port B

1

0

0

0

0

0

0

0

80

OUT

OUT

OUT

OUT

1

0

0

0

0

0

0

1

81

OUT

OUT

IN

OUT

1

0

0

0

0

0

1

0

82

OUT

OUT

OUT.

IN

1

0

0

0

0

0

1

1

83

OUT

OUT

IN

IN

1

0

0

0

1

0

0

0

88

OUT

IN

OUT

OUT

1

0

0

0

1

0

0

1

89

OUT

IN

IN

OUT

1

0

0

0

1

0

1

0

8A

OUT

IN

OUT

IN

1

0

0

0

1

0

1

1

8B

OUT

IN

IN

IN

1

0

0

1

0

0

0

0

90

IN

OUT

OUT

OUT

1

0

0

1

0

0

0

1

91

IN

OUT

IN

OUT

1

0

0

1

0

0

1

0

92

IN

OUT

OUT

IN

1

0

0

1

0

0

1

1

93

IN

OUT

IN

IN

1

0

0

1

1

0

0

0

98

IN

IN

OUT

OUT

1

0

0

1

1

0

0

1

99

IN

IN

IN

OUT

1

0

0

1

1

0

1

0

9A

IN

IN

OUT

IN

1

0

0

1

1

0

1

1

9B

IN

IN

IN

IN

Note 4'

OUT indicates output port, and IN indicates input port

Table

4

Mode 1 control words
Group A

Control words

D7 Do D5 D, D, D2 D, Do

I

Group B

Group A

Control words

0

1

0

0

1

0

I

0

1

0

0

1

1

X

I

0

1

0

1

1

0

X

I

0

1

0

1

1

1

X

1

0

1

1

0

1

0

X

1

0

1

1

0

1

1

X

X

Port A

A4
A5

Port C
PC_

PC2

PC,

PCo

OUT

INTRA

-ACK e

-OBFe

INTRe

OUT

ACKA

OUT

INTRA

-STBe

IBFe

INTRe

IN

OBFA

-ACKA

IN

INTRA

-ACK B

-OBF B

INTRe

OUT

-OBFA

-ACK A

IN

INTRA

-STB B

IBFe

INTRe

IN

PCe

OUT

-OBFA

-ACKA

OUT

OBFA

OUT

OUT

PC5

A6
A7
AC
AD
AE
AF

Port B

PC3

PC?

decimal

Group B

PortC

Hexa-

B4

1

0

1

1

1

1

0

X

1

0

1

1

1

1

1

X

Note 5:
6:

5-50

B5

IN

OUT

IBFA

STBA

INTRA

ACK B

OBFe

INTRe

OUT

IN

OUT

IBFA

STBA

INTRA

STB B

IBFe

INTRe

IN

IN

IN

IBFA

-STB A

INTRA

-ACK e

OBFe

INTRe

OUT

IN

IN

IBFA

STBA

INTRA

STB B

IBFe

INTRe

IN

B6
B7
BC
BD
BE
BF

Mode of group A and group B can be programmed independently
It is not necessary for both group A and group B to be in mode 1.

• MITSUBISHI
..... ELECTRIC

MITSUBISHI LSls

MSL825SAP-S
PROGRAMMABLE PERIPHERAL INTERFACE

ABSOLUTE MAXIMUM RATINGS
Symbol

Parameter

Conditions

Vee

Supply voltage

V,

Input voltage

Va

Output voltage

Pd

Power disSipation

Topr
Tstg

Operating free-air temperature range

With respect to vss
Ta=25'C

Storage temperature range

RECOMMENDED OPERATING CONDITIONS
Symbol
Vee

Supply voltage

Vss

Supply voltage (GND)

Min
4.75

ELECTRICAL CHARACTERISTICS
Symbol

Unit
V

-0.5-7

V

-0.5-7

V

1000

mW

-20-75
65 150

'c
'c

(Ta =-20-75'C, unless otherwise noted)
Limits

Parameter

Ratings
-0.5-7

I
I
I

Nom
5
0

I
I

Max
5.25

1

Unit
V
V

(T a=-20-75'C, Vcc =5V±5%, Vss=OV, unless otherwise noted)

Test conditions

Parameter

Limits
Min

Typ

Max

Unit

V ,H

High-level Input voltage

2.0

Vee

V

V ,L

Low-level input voltage

-0,5

0.8

V

VOH

High-level output voltage

VOL

low-level output voltage

IOH

High-level output current (NoteIO)

Icc

Supply current from Vee

120

mA

I,H

High-level input current

VI=VCC

±10

I-'A

I'L
loz

Low-level Input current

V,=OV

±10

I-'A

Off-state output current

Vo=OV-Vcc

+10

Ci

Input terminal capacitance

VIL =Vss, f=1 MHz, 25mVrms Ta=25'C

10

I-'A
pF

Input/output terminal capacitance

VIIOL=V SS, f-I MHz, 25mVrms Ta=25"C

20

pF

Gila
Note

g.

10

Data bus

IOH=-400"A

Port

IOH=-200"A

Data bus

10L =2. 5mA

Port

2,4

V
0.45

10L -1. 7mA
-1

VoH=I. 5V, R,xT=750n

-4

V
mA

Current flowing mto an Ie IS positive. out is negative
It IS valid only for any8,nput/output pins of PB and PC.

TIMING REQUIREMENTS

(T a=-20-75'C, Vcc =5V±5%, vss=ov, unless otherwise noted)

Symbol

Prameter

Test conditions

limits
Min

Typ

Max

Umt

tW(R)

Read pulse width

300

ns

tSU(PE-R)

Peripheral setup time before read

0

ns

th(R-PE)

Peripheral hold time after read

0

ns

tSUCA-R)

Address setup time before read

0

ns

th(R-A)

Address hold time after read

0

ns

twCW)

Write pulse Width

300

ns

tSU(DQ-W)

Data setup time before write

100

ns

th(w-oQ)

Data hold time after write

30

ns

tSU(A-W)

Address setup time before write

0

ns

th(W-A)

Address hold time after write

20

ns

tW(ACK)

Acknowledge pulse Width

300

ns

tW(STB)

Strobe pulse Width

500

ns

tsu( PE-STB)

Penpheral setup time before strobe

0

ns

th(STB-PE)

Penpheral hold time after strobe

180

ns

tC(RW)

Read/write cycle time

850

ns

5-52

• MITSUBISHI
..... ELECTRIC

MITSUBISHI LSls

MSL825SAP-S
PROGRAMMABLE PERIPHERAL INTERFACE

TIMING DIAGRAM
Data Bus Read Operation

twiRl
-'

..., v~

j\~

~
CS, Ao, A,

~

~K

~~
-'

.....

tPVZ(R_DQ)

tPZV(R_DQ)

X:

~

Do-D,

~

Data Bus Write Operation

~

~147

tW(W)

-'

J?

I\~

~
CS, Ao, A,

X

~

thlw_AI

X

~

Ir

th{w_oQ)

tSU(oQ_wl

:K

~:
ModeO Port Input

PORT INPUT

ModeO, 1 Port Output

w(w)

'\

Jl

jL

tPHL(W-PE)
tPLH(W-PE)

X'-

PORT OUTPUT

-'I.-

5-54

• MITSUBISHI
"ELECTRIC

MITSUBISHI LSls

MSL825SAP-S
PROGRAMMABLE PERIPHERAL INTERFACE

Mode2 Bidirectional

\

/
tPHUW.OBF)

\

\

/
tPLH(ACK-OBF)

INTR

tW(ACKJ

/

V

\ \-/~
tW(STB}

\~
tPLH(STB-IBF)

Vr

~I-

I<-

}~

IBF

-\tPHL{R-1BF)

fE---->
,I-

th(STB-PE)
tSU(PE-STB)

PORT A

Note 13

5-56

11"/-

k\\

\\~ ~

INTR=IBF' MASK' STB • RD

tPZV(ACK-PE)

~

~~II

II}
\ \~t-

+ OBF • MASK' ACK • WR

• .MITSUBISHI
"ELECTRIC

tPVZ{ACK-PE)

E------':o

k\\

-¥II

MITSUBISHI LSls

MSL82SSAP-S
PROGRAMMABLE PERIPHERAL INTERFACE

2. Mode 1

The actual program for the circuit of Fig. 12 is as follows:

An example of a circuit for an application using mode 1 is
shown in Fig. 12.

MVI

A,BO#

OUT

03#
A,09#
03#

MVI

OUT
EI
FROM
ROM
FROM
FROM

INPUT{
DATA

DATA STROBE
SIGNAL

ADDRESS A,
ADDRESS Ao
DECODER
CPU

0,
02

0,
0,
PC,

TO DATA
} BUS

Os

0,
PBo-PB,

0,

HLT

If the data has been set in a terminal unit, and the strobe
signal has been input, then the data will be latched in port A
and the CPU RST7.5 goes high-level. In the case of Fig. 11,
a jump to 003C16 is executed to continue the program as follows:

003C16 IN 00# CPU register A +- Port A
PC 3 interrupt Signal becomes lOW-level
EI
RET

CPU
' - - - - - - - - - TO RST7. 5
(INTERRUPT INPUT)

Fig. 12

A circuit for an application using mode 1

Transferring data from a'terminal unit to port A and sending
a strobe signal to PC4 will hold the data in the internal latch
of the PPI, and PCs (IBF input buffer full flag) is set to highlevel. If a bit-set of PC4 has been executed in advance, the
CPU can be interrupted by the INTR signal of PC s when the
input data is latched in the PPI. In this way, port A becomes
an interrupting port; and at the same time, port B can select
its mode independently.

5-58

Control word is 10110000, port A is
the mode 1 input and the others are
output
Outputting to the control address
PC4bit-set 00001001
Outputting to the control address
Interrupt enable
Halt

• MITSUBISHI
. . . . ELECTRIC

MITSUBISHI LSls

MSL825SAP-S
PROGRAMMABLE PERIPHERAL INTERFACE

1. Master CPU subroutine for transmitting data to the slave
CPU.

2. Subroutine for receiving data from the slave CPU.

Program example

Program example
MOUT
OBF

PUSH

PSW

MIN

IN

02#

IN

02#

ANI

20#

ANI

80#

JZ

MIN

JZ

OBF

IN

00#

POP

PSW

RET

OUT

00#

RET

RET

RET

3. Slave CPU subroutine for transmitting data to the master
CPU.

4. Subroutine for receiving data from the master CPU.

Program example

Program example

SOUT

PUSH

PSW

IBF

IN
ANI
JNZ

SIN

IN

01#

01#

ANI

01#

02#

JNZ

SIN

00#

IBF

IN

POP

PSW

RET

OUT

00#

RET

RET

5-60

• MITSUBISHI
.... ELECTRIC

MITSUBISHI LSls

MSL82S7P-S
PROGRAMMABLE DMA CONTROLLER

DESCRIPTION

PIN CONFIGURATION (TOP VIEW)'

The M5L8257P-5 is a programmable 4-channel direct memory access (DMA) controller. It is produced uSing the Nchannel silicon-gate ED-MOS process and is specifically
designed to simplify data transfer at high speeds for microcomputer systems
The LSI operates on a single 5V power supply.

INPu,Jf8u~~t9 IIOR ~

INPu¥?o~~~f I/OW~

MEMORdu~~t9 MEMR MEMORbtfr~~f MEMW MARK OUTPUT MARK -

1
2
3
4
5

READY INPUT READY -

6

FEATURES

HOLDE~~~~2~J-T HLDA -

?

•
•
•
•
•
•
•

STOROBEAgB~~crl ADSTB -

8

Single 5V supply voltage
TTL compatible interface
Priority DMA request logic
Channel-masking function
Terminal count and Modulo 128 outputs
4-channel DMA controller
Compatible with MELPS85 devices

ENABLEA8B~~~¥

AEN 9
HRQ-l0

R5~¥~~t
ST~~8t

HOLD

CHIP

CS -

11

CLOCK INPUT CLK-12

OATA
INPUTS!
OUTPUTS

RESET INPUT RESET-13
DMA ( DACK, -

AC'6Nu~~~¥E~.~\.

APPLICATION

DMA
REQUEST
'INPUTSO-3

DMA control of peripheral equipment such as floppy disks
and CRT terminals that require high-speed data transfer.

14

DACK" -15

r DRQ,-16
DRQ,-I?

l

DRQ, -18
DRQo-19
Vss

(ov)

FUNCTION
The M5L8257P-5 controller is used in combination with the
M5L8212P 8-bit input/output port in 8-bit microcomputer systems. It consists of a channel section to acknowledge DMA
requests, control logic to exchange commands and data with
the CPU, read/write logic, and registers to hold transfer
addresses and count the number of bytes to be transferred.
When a DMA request is made to an unmasked channel from
the peripherals after setting of the transfer mode, transferstart address and the number of transferred bytes for the
registers, the M5L8257P-5 issues a priority request for the
use of the bus to the CPU. On receiving an HLDA signal

BLOCK DIAGRAM

Outline 40P4
from the CPU, it sends a DMA acknowledge signal to the
channel with the highest priority, starting DMA operation.
During DMA operation, the contents of the high-order 8 bits
of the transfer memory address are transmitted to the
M5L8212P address-latch device through pins Do - 07. The
contents of the low-order 8 bits are transmitted through pins
Ao - A7. After address transmission, DMA transfer can be
started by dispatching read and write signals to the memories and peripherals.

.-------------------;
(~
CH 0
; ~'ilI

(5V) Vee
(OV) Vss ~~

DATA INPUTSIOUTPUTS

1~:
~

a

DATA BUS
BUFFER

a

~

"" 3

cs~l

~
ADDRESS OUTPUTS { A.A'

DATA

I
f--J

l

I

~

CONTROL

7

f

';II DACKo OUTPUT CH·O

,

DMA REQUEST
INPUT CH-2
DACK, DMA ACKNOWLEDGE
OUTPUT CH-2

CH·2
16·BIT ADDRESS
REGISTER

DRQ,

CH·3
16·BIT ADDRESS
REGISTER

ORO,

J

I

DMA REQUEST
INPUT CH·3
DMA ACKNOWLEDGE
DACK,
OUTPUT CH·3

~'TC

5 MARK
PRIORITY,
RESOLVER

READY INPUT READ~16~~
LOGIC
i---t;;-a
HOLD REQUEST OUTPUT
HRQ~
HOLD ACKNOWLEDGE INPUT HLD~"
1~3!k:

---l

DMA REQUEST
CH·I
;~)~ DRQ, INPUT CH-I
16·BIT ADDRESS'
DMA ACKNOWLEDGE
REGISTER
DACK, OUTPUT CH·I

H

a

BU~

I

I

1---+--------------'

ADDRESS ENABLE OUTPUT
AEN
ADDRESS STROBE OUTPUT ADSTB~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

5-62

• MITSUBISHI
. . . . ELECTRIC

DMA REQUEST
INPUT CH-O
DMA ACKNOWLEDGE

16.BIT ADDRESS
REGISTER

H

a

~DRQo

r-l

~ 1---++::-1,--+-1

1/0 READ INPUTIOUTPUT
IIOR 1;- __
1/0 WRITE INPUT/OUTPUT
I/OW 2"....
CLOCK INPUT
ClK ff"";r--_-'
L-.............
RESET INPUT RESET r
READ/WRITE I - ' a LOGIC
{
a·BIT
ADDRESS INPUTS/OUTPUTS ~
INTERN~~

CHIP SELECT INPUT

20

----,_ _ _ _ _.r-

,
I

--.-J

6t~~~TAL COUNT
MARK OUTPUT

MITSUBISHI LSls

MSL82S7P-S
PROGRAMMABLE DMA CONTROLLER

Register Initialization
Two 16-bit registers are provided for each of the 4 channels.
DMA Address register
15

MODESET:

MVI A, ADDL
OUT 00 #:

0

'~5~4~3~2~'~O~ ~ ~ ~ ~ ~ ~ ~ ~ ~I
DMA TRANSFER STARTING ADDRESS

Terminal count register
15

o

1413

'"i:>MAMoDE '

Channel 0 lower-order address
MVI A,ADDH
OUT 00 #:
Channel 0 upper-order address
MVI A, TCL
OUT 01 #:
Channel 0 terminal count lower-order
MVI A, TCH
OUT 01 #:
Channel 0 terminal count upper-order
MVI A, XX
OUT 08 #:
Mode set resister

NUMBER OF TRANSFERRED BYTES-l

The DMA transfer starting address, number of transferred
bytes, and DMA mode are written for each channel in 2
steps uSing the 8-blt data bus. The lower-order and upperorder bytes are automatically indicated by the first-last flipflop for the writing and reading in 2 continuous steps.
The DMA mode (read, write, or verify) is indicated by the
upper 2 bits of the terminal count register. The read mode
refers to the operation of peripheral devices reading data
out of memory. The write mode refers to data from peripheral devices being written into memory. The verify mode
sends neither the read nor the write Signals and performs a
date check at the peripheral device.
In addition to the above-mentioned registers, there is a
mode set register and a status register.
Mode set register (write only)
7

0

i---r--,---.,.---;--,---,--:-;______,

As can be seen from the above example, until the contents
of the address register and terminal count register become
valid, the enable bit of the mode set register must not be
set. This prevents memory contents from being destroyed by
improper DRO signals from peripheral devices.

DMA OPERATION DESCRIPTION
When a DMA request signal is received at the DRO pin from
a peripheral device after register initialization for a channel
that is not masked, the M5L8257P-5 outputs a hold request
signal to the CPU to begin DMA operation (S,).
The CPU, upon receipt of the HRO signal, outputs the HLDA
signal which reserves capture of the bus after it has executed the present instruction to place this system in the
hold state.
When the M5L8257P-5 receives the HLDA signal, an internal
priority determining circuit selects the channel with the highest priority for the beginning of data transfer (So) .

...:'=A::L==I=T::c::s::;I=E=W==1=R=p=I=E:N:3=:E:N:2=::E=N:l~=E:N:O=- Upon the next S,
ADDED FUNCTION SETTING BITS

CHANNEL ENABLE BITS

Status Register (read only)
7

o

'---o-"---o-r--o--rI-u-p--"I-TC-3--'-T-C-2-'--T-C-1- r -T-C-o'l
The upper-order 4 bits of the mode set register are used to
select the added function, as described in 5-66. The lowerorder 4 bits are mask bits for each channel. When set to I,
DMA requests are allowed. When the reset signal is input,
all bits of the mode set and status registers are reset and
DMA is inhibited for all channels. Therefore, to execute
DMA operations, registers must first be initialized. An example of such an initialization is shown below.

5-64

state, the address signal is sent. The lower-order 8 bits and upper-order 8 bits are sent by means of
the Ao - A7 and Do - D7 pins respectively, latched into the
M5L8212P and output at pins As-A,5. Simultaneous with this,
the AEN signal is output to prohibit the selection of a device
not capable of DMA.

In the S2 state, the read, extended write, and DACK signals
are output and data transferred from memory or a peripheral
device appea~s on the data bus.
In the S3 state, the write signal required to write data from
the bus is output. At this time if the rernaining number of
bytes to be transferred from the presently selected channel
has reached 0, the terminal count (TC) Signal is output.
Simultaneously with this, after each 128-byte data transfer a
mark signal is output as required. In addition, in this state
the READY pin is sampled and, if low-level, the wait state
(Sw) is entered. This is used to perform DMA with slow access memory devices. In the verify mode, READY input is
ignored.

•
MITSUBISHI
i1IL·ELECTRIC

MITSUBISHI LSls

MSL8257P·S
PROGRAMMABLE DMA CONTROLLER

INTERNAL REGISTERS OF THE M5L8257P-5
Lower

Upper

DMA address
channel-O
terminal count

DMA address
channel-l
terminal count

DMA address
channel-2
terminal count

DMA address
channel-3
terminal count

Mode setting (tor write only)

Status (for read only)

Rd. Wr

AL
EW
TCS

RP

: Address of the memories for which DMA WIll be carned out from now on In initialization, DMA start addresses must be written
: Terminal counts-in th,s IC (the number of remainIng transfer bytes mInus 1) The address IS decremented for each DMA transfer of one
byte, and when the transfer IS finished, becomes ( 3 FFF) H If addItIonal DRQ signals are input, the address continues to be decremented.
: Used for DMA-mode setting by the following convention'
Rd

Wr

Mode to be set

0
0
1
1

0
1
0
1

DMA verify
DMAwnte

DMA read
Prohibition

: Automatic load mode. When this bit has been set, contents of the channel 3 register are written, as are on the channel 2 register when
channel 2 DMA transfer comes to an end This mode allows qUick, automatic chaining operations without intervention of the software
: Extended write signal mode When this bit has been set, write signals can be transmitted in advance to memories and peripheral equipment requiring long access time
: Terminal count stop When a DMA transfer process is complete, with terminal-count output, the channel-enable mask of that channel is reset, prohibiting subsequent DMA cycles.
: Rotating priority mode The setting of this mode allows the priority order to be rotated by each byte transfer.
The setting priority is fixed with the channel 0 as highest, followed by channell, 2 and 3 In descending order
CH-O

CH-l

CH-2

1

CH-l

CH-2

CH-3

CH-O

2

CH-2

CH-3

CH-O

CH-l

3

CH-3

CH-O

CH-l

CH-2

4

CH-O

CH-l

CH-2

CH-3

Channel used for the present data transfer

Pnoflty list for the next cycle

ENO-EN3

UP
TCO-TC3

5-66

CH-3

Channel-enable bit. This mask prohibits or allows the DMA request When the reset signal IS applied, all channels are disabled.
Update flag. This is set when register contents are transferred in an automatic load mode from channel 3 to channel 2.
Terminal-count status flags. At the time of terminal-count output, the flag corresponding to the channel is set
The flag is, set by reading the status register, annd IS unaffected by the TCS bits

•
MITSUBISHI
. . . . ELECTRIC

MITSUBISHI LSls

MSL8257P-S
PROGRAMMABLE DMA CONTROLLER

ELECTRICAL CHARACTERISTICS
Symbol

V ,H
V,L
VOL
V OH 1
V OH2
V OH3

Test conditions

High-level Input voltage
laL=I.6mA

High-level output voltage far AB, DB and AEN

laH=-150"A

High-level output voltage for HRO
High-level output voltage far others

loz

C,

Input terminal capacitance

ClIO

InpuVoutput terminal capaCItance

TIMING REQUIREMENTS

Limits
Typ

Min

Max

2.0
-0.5

Low-level Input voltage
Low-level output voltage

Supply current from Vcc
Input current
Off-state output current

Icc
I,

(Ta=-20-75"C, Vee=5V±5%, unless otherwise noted)

Parameter

Vee
0.8
0.45

2.4
3.3

IOH=-80"A

2.4

V,=OV, Vee
Vo-OV-Vcc
Ta-25'C, Vcc=Vss
Pins other than that under measurement are set
to OV, fC=1 MHz

120
10
10

-10
-10

Unit

V
V
V
V
V
V
mA
J.lA
J.lA

10

pF

20

pF

(Ta=-20-75'C, Vcc= 5 V± 5 %, Vss= 0 V, unless otherwise noted)

Symbol

Parameter

Test conditions

Limits

Typ

Min

Max

Unit

tweRI

Read pulse Width

250

ns

tsu(A-R)
tau(eS-R)

Address or CS setup time before read

0

ns

0

ns

200

ns

20

ns
ns

:~l==~~1

Address or CS hold time after read

twewl

White pulse Width

tsueA-wl
theW-AI

Address setup time before write
Address hold time after write

0

tsueoo-wl Data setup time before write
thew-Dol Data hold time after write
Reset pulse width
tW(RST)

200

ns

0
300

ns
ns

tSU(vcc-RSTl

Supply voltage setup time before reset

tr

Input signal rise time

tf
tSU(RST-W)

Input signal fall time
Reset setup time before write

tce ~I
twe ~I

Clock cycle time
Clock pulse Width high-level

tsueDRQ-~ I

ORO setup time before clock

lh(HLDA-DRQ)

ORO hold time after HLDA

tSU{RDV-; )

HLDA setup time before clock
Ready setup time before clock

Ihc; -RDYI

Ready hold time after clock

tSU{HLDA-; )

500

tPZV(R_DQ)
tPVZ(R_DQ)

5-68

4
O. 8tce~)

80
70

I

ns
ns
tce~ I

2
0.32

J.lS

ns
ns

0

ns
ns

100
30
20

SLAVE MODE SWITCHING CHARACTERISTICS
Symbol

ns
20
20

ns
ns

(Ta=-20-75"C, Vec=5V±5%, Vss=ov, unless otherwise noted)

Parameter

Test conditions

Output data enable time after read
Output data disable time after read

C L =150pF

• MITSUBISHI
..... ELECTRIC

Limits
Min
0
20

I
I
I

Typ

I
I
I

Max
200
100

Unit
ns
ns

MITSUBISHI LSls

MSL8257P-S
PROGRAMMABLE DMA CONTROLLER

TIMING DIAGRAMS
DMA Mode

.1 • I·. 1 • 1 • 1 •

1 •

1 • 1 •

1 •

1 •

I • I • I.

ISUIO~~ ~:~~0:[V'-1U ru ~

ClK

,

I

OROo-ORO,

IPLHI .... HRQI ...

)(

II

\

H-

tpHL(~HRQ)

ISUIH~A-'I -+ I-

HRO

th(HLDA-ORQ)

:::1
X-

- \ ____ 1

r

HLDA

I

IPLHI ....AENI-~

AEN

~PHLI ....AEN)

1

....

Ipzvl ....AI ....

I-- IpLHI '-AI

~tPVZ(f-A)

Ao-A7

..

(lOWER ADORE SS)

~~~l-OQI

Ipzvl .... oQ) ...

00-07

t

~

tPLH(?-ASTB) ..

AOSTB
I

--=l--

IPHLTAST81

/./7

-----------------------

\

... '---!-IPLHI ....R)

,

...

I

tPHL(ASTB-WE)
tW(R)

1

~LI~lpLHI ....WI

,

'--t--- -i
~
Ihl .... Royl

tSU(RDY ~)

~ tPHL(ASTB-R)

1

\

IPHLI .... RI~

/U'

TC/MARK

1

IpZVI .... R)-~

MEMR/i7OR

n

~
tPHL(A-ASTB)

... ~LHI~~I

IPHLI .... ~ACKI

'\

OACKo-_ _
OACK,

READY

h

..!WI

(UPPER ADORE SS)

~
Ihl ....AI '"!thIAST8-AI

IPLHI ....Te/MARKI~PHLI ....Te/MARKI

------------

~--.
'~
/ \

~"

.......

tPVZ(~A)
~

\wIWEI

.~

Slave Mode
Read

Write

cs

00-07

CS

~-A7

________-'~~------~--~~'-~--~----_

00-07

-----------------'~~--~--~r'---------

----------------------~::==~--------RESET

Vee

5-70

• MITSUBISHI
"ELECTRIC

MITSUBISHI LSls

M5L8259AP
PROGRAMMABLE INTERRUPT CONTROLLER

DESCRIPTION
The M5L8259AP is a programmable LSI for interrupt control.
It is fabricated using N-channel silicon-gate ED-MaS technology and is designed to be used easily in connection with
an MELPS85, MELPS86 or MELPS88.

PIN CONFIGURATION (TOP VIEW)
CHIP

ST~~8t CS~

\%~~~ WR ~
CONTROL I~~t~ RD~

CONTROL

0, -

FEATURES
•
•
•
•
•
•

Single 5V supply voltage
TTL compatible
CALL instruction to the CPU is generated automatically
Priority, interrupt mask and vectored address for each interrupt request input are programmable
Up to 64 levels of interrupt requests can be controlled by
cascading with M5L8259AP

1

Vc d5V)

27
26

2

3
4

~ Aa ADDRESS INPUT

_ _ INTERRUPT

~INTAACKNOWLEDG

INPUT

Os -

05 BIDIRECTIONAL
DATA BUS

INTERRUPT
REQUEST
INPUTS

0, 03 0, -

19

~IR,

18 -IRo
-INT

17

Polling functions

16

INTERRUPT

~'G~~G~T

-SP/EN~~til~~

15 -CAS, CASCADE
-.._ _ _ _ _..rLINE

APPLICATION
The M5L8259AP can be used as an interrupt controller for
MELPS85, MELPS86 and MELPS88.

Outline 28P4

FUNCTION
The M5L8259AP is a device specifically designed for use in
real time, interrupt driven microcomputer systems. It manages eight level requests and has built-in features for expandability to other M5L8259APs. The priority and interrupt
mask can be changed or reconfigured at any time by the
main program
When an interrupt is generated because of an interrupt request at 1 of the pins, the M5L8259AP based on the mask

and priority will output an INT to the CPU. After that, when
an INTA signal is received from the CPU or the system controller, a CALL instruction and a programmed vector address
is released onto the data bus.

BLOCK DIAGRAM

INTERRUPT
ACKNOWLEDGE INPUT

INTA
CONTROL LOGIC

INTERRUPT
REQUEST OUTPUT

INTERRUPT
REQUEST INPUTS

DATA BUS
BUFFER

I Ro 18'>---r---""'"
IR,
IR,
IR3
IR,
IRs
IRs
IR, 25

READ/WRITE
CONTROL
LOGIC

BIDIRECTIONAL DATA BUS

2 WR WRITE CONTROL INPUT
3 RD READ CONTROL INPUT
27

....._-.:::=:;--1.1

Ao ADDRESS INPUT
CS CHIP SELECT INPUT

12 CAsa}
13 CAS,
CASCADE LINES

15

L
-

5-72

AS,

L-----{16 SP/EN

- --- - --- - --- - --- - --- -

•
MITSUBISHI
;"ELECTRIC

SLAVE PROGRAM INPUT/
ENABLE BUFFER OUTPUT

MITSUBISHI LSls

MSL82S9AP
PROGRAMMABLE INTERRUPT CONTROLLER

Interrupt Sequence
1. When the CPU is a MELPS85
(1)

(2)

(3)
(4)
(5)

(6)

(7)

'R~'RRSET

When one or more of the interrupt request inputs are
raised high-level, the corresponding IRR bit(s) for the
high-level inputs will be set
Mask state and priority levels are considered and, if
appropriate, the M5L8259AP sends an INT signal to
the CPU.
The acknowledgement of the CPU to the INT signal,
the CPU issues an INTA pulse to the M5L8259AP.
Upon receiving the first INTA pulse from the CPU, a
CALL instruction is released onto the data bus.
A CALL is a 3-byte instruction, so additional two
INTA pulses are issued to the M5L8259AP from the
CPU.
These two INTA pulses allow the M5L8259AP to release the program address onto the data bus. The
low-order 8 bits vectored address is released at the
second INTA pulse and the high-order 8 bits vectored address is released at the third INTA pulse.
The ISR bit corresponding to the interrupt request input is set upon receiving the third INTA pulse from
the CPU, and the corresponding IRR bit is reset.
This completes the 3-byte CALL instruction and the
interrupt routine will be serviced. The ISR bit is reset
at the trailing edge of the third INTA pulse in the
AEOI mode In the other modes the ISR bit is not reset until an EOI command is issued.

INTA ----"l

1

(5)
(6)

5-74

ISR RESET (AEOI MODE)

A CALL instruction is released onto the data bus when
the first INTA pulse is issued. The low-order 8 bits of the
vectored address are released when the second INTA
pulse is issued, and the high-order 8 bits are released
when the third INTA pulse is issued. The format of these
three outputs is shown in Table 2.

Table 2 Formats of interrupt CALL instruction and vectored address

06

0,

05

o

o

Do

o

Second INTA pulse (low-order 8 bits of vectored address)

2. When the CPU is a MELPS86 or MELPS88

(4)

ISR SET

Interrupt sequence outputs
1. When the CPU is a MELPS85

ISR SET

(3)

r-'

The interrupt request input must be held at high-level until
the first INTA pulse is issued. If it is allowed to return to lowlevel before the first INTA pulse is issued, an interrupt request in IR7 is executed. However, in this case the ISR bit is
not set.
This is a function for a noise countermeasure of interrupt request inputs. In the interrupt routine of IR7, if ISR is checked
by software either the interrupt by noise or real interrupt can
be acknowledged. In the state of edge trigger mode normally the interrupt request inputs hold high-level and its input
low-level pulse in the case of interrupt

iNTA

(2)

2

~~'\!~~ RESET

First INTA pulse (CALL instruction)

IRI...fi" IRR SET

(1)

r---J

~

When one or more of the interrupt request inputs are
raised high-level, the corresponding IRR bit(s) for the
, high-level inputs will be set.
Mask state and priority levels are considered and if
appropriated, the M5L8259AP sends an INT signal to
the CPU.
As an acknowledgement to the INT Signal, the CPU
issues an INTA pulse to the M5L8259AP.
Upon receiving the first INTA pulse from the CPU,
the M5L8259AP does not drive the data bus, and the
data bus keeps high-impedance state.
When the second INTA pulse is issued from the
CPU, an 8-bit pOinter is released onto the data bus.
This completes the interrupt cycle' and the interrupt
routine will be serviced. The ISR bit is reset at the
trailing edge of the second INTA pulse in the AEOI
mode. In the other modes the ISR bit is not reset until an EOI command is issued from the CPU.

IR

Interval= 4

07

Os

05

04

Dg

02

0,

Do

IRo

A7

As

0

0

0

0

0

IR,

A7

As

0

0

1

0

0

IR2

A7

As

0

1

0

0

0

IRg

A7

As

0

1

1

0

0

IR4

A7

As

1

0

0

0

0

IRs

A7

As

1

0

1 '

0

0

IRs

A7

As

1

1

0

0

0

IR7

A7

As
As
As
As
As
As
As
As

As

1

1

1

0

0

• MITSUBISHI
"'ELECTRIC

MITSUBISHI LSls

MSL82S9AP
PROGRAMMABLE INTERRUPT CONTROLLER

Read Control Input (RD)
When RO goes low-level status information in the internal
register of the M5L8259AP can be read through the data bus.
Address Input (Ao)
The address input is normally connected with one of the
address lines and is used along with WR and RO to control
write commands and reading status information.
Cascade Buffer/Comparator
The cascade buffer/comparator stores or compares identification codes. The three cascade lines are output when the
M5L8259AP is a master or input when it is a slave. The identification code on the cascade lines select it as master or
slave.

PROGRAMMING THE M5L8259AP
The M5L8259AP is programmed through the Initialization
Command Word (ICW) and the operation command word
(OCW) . The following explains the functions of these two
commands.
Initialization Command Words (ICWs)
The initialization command word is used for the initial setting
of the M5L8259AP. There are four commands in this group
and the following explains the details of these four commands. The command flow of ICWs is shown Fig. 2.
ICW1
The meaning of the bits of ICWl is explained in Fig. 3 along
with the functions. ICWl contains vectored address bits A7~
A5 , a flag indicating whether interrupt input is edge triggered or level triggered, CALL address interval, whether a

single M5L8259AP or the cascade mode is used, and
whether ICW4 is required or not.
Whenever a command is issued with Ao=O and 04=1, this is
interpreted as ICW1 and the following will automatically
occur.
(a) The interrupt mask register (IMR) is cleared.
(b) The interrupt request input IR7 is assigned the lowest
priority.
(e) The special mask mode is cleared and the status read
is set to the interrupt request register (IRR).
(d) When IC4=O all bits in ICW4 are set to O.
ICW2
ICW2 contains vectored address bits A15 ~ As or interrupt
type T7~T3, and the format is shown in Fig. 3.
ICW3
When SNGL= 1 it indicates that only a single M5L8259AP is
used in the system, in which case ICW3 is not valid. When
SNGL=O, ICW3 is valid and indicates cascade connections
with other M5L8259AP devices. In the master mode, a 1 is
set for each slave.
When the CPU is a MELPS85 the CALL instruction is released from the master at the first INTA pulse and the vectored address is released onto the data bus from the slave
at the second and third INTA pulses.
When the CPU is a MELPS86 the master and slave are in
high-impedance at the first INTA pulse and the pointer is released onto the data bus from the slave at the second INTA
pulse.

ICWl

ICW2

ICW3

ICW4

Fig. 2

5-76

Initialization sequence

• MITSUBISHI
;"ELECTRIC

MITSUBISHI LSls

MSL82S9AP
PROGRAMMABLE INTERRUPT CONTROLLER

The master mode is specified when SP/EN pin is high-level
or BUF=l and M/S=l in ICW4, and slave mode is specified
when SP/EN pin is low-level or BUF = 1 and M/S = 0 in
ICW4. In the slave mode, three bits ID2 ~ IDo identify the
slave. And then when the slave code released on the cascade lines from the master, matches the assigned ID code,
the vectored address is released by it onto the data bus at
the next INTA pulse.

ICW4
Only when IC4=1 in ICWl is ICW4 valid. Otherwise all bits
are set to O. When ICW4 is valid it specifies special fully
nested mode, buffer mode, master/slave, automatic EOI and
microprocessor mode The format of ICW4 is shown in Fig. 3.

Operation Command WOrds (OCW s)
The operation command words are used to change the contents of IMR, the priority of interrupt request inputs and the
special mask. After the ICW are programmed into the
M5L8259AP, the device is ready to accept interrupt requests.
There are three types of OCWs; explanation of each follows,
and the format of OCWs is shown in Fig. 4.
OCW1
The meaning of the bits of OCWl are explained in Fig. 4
along with their functions. Each bit of IMR can be independently changed (set or reset) by OCW1.
OCW2
The OCW2 is used for issuing· EOI commands to the
M5L8259AP and for changing the priority of the interrupt reINTERRUPT MASK SET
INTERRUPT MASK RESET

OCWl

0
0
1
1

1 NON-SPECIFIC EOI
1 SPECIFIC EOI (RESETS ISR BITS L2-Lo)
1 ROTATE ON NON-SPECIFIC EOI
0 SETS AUTOMATIC ROTATION FLIP-FLOP
0 RESET AUTOMATIC ROTATION FLIP-FLOP

0

1
0
0
0 0

}EOI

} AUTOMATIC ROTATION

,

1 1 1 ROTATE ON SPECIFIC EOI (RFRFT~ "'" ~'T !..'_·!..o)
1 1 0 SETS PRIORITY COMMAND (SET LOWEST PRIORITY BIT L2-Loi
0 1 0 NO OPERATION

~
I

o

1

Ao

R
07

,I

} SPECIFIC ROTATION

10 LEVEL TO BE ACTED UPON

I
SL

EOI 1

0,

05

0

1

0

1

03

L2

1

L,
0,

02

0 1 2
0 0 0
0 0 1
0 1 0

I

I

Lo
Do

3 4 5 6
0 1 1 1
1 0 0 1
1 0 1 0

I

OCW2

0
1
1

X

NO OPERATION

0
1

RESET SPECIAL MASK MODE
SETS SPECIAL MASK MODE

11
1 o.

I
Fig. 4

5-78

o
Ao

1

0
07

ESMM 1 SMM 1

0,
05
OCW3

o

1

1
03

1

P
02

1

0

X

NO OPERATION

1
1

0
1

SETS STATUS READ REGISTER IN IRR

I

I

RR

1 RIS

0,

POLL COMMAND
NO POLL COMMAND

SETS STATUS READ REGISTER IN ISR

I

Do

Operation command word format

• MITSUBISHI
..... ELECTRIC

7

1
1
1

MITSUBISHI LSls

MSL82S9AP
PROGRAMMABLE INTERRUPT CONTROLLER
mode. When the M5L8259AP is in special mask mode ISR
bits masked in IMR are not reset by EOI. EOI and SEOI are
selected when OCW2 is executed.

Automatic EOI (AEOI)
In the AEOI mode the M5L8259AP executes non-specific
EOI command automatically at the trailing edge of the last
INTA pulse. When AEOI=l in ICW4, the M5L8259AP is put in
AEOI mode continuously until reprogrammed in ICW4.
The AEOI mode can only be used in a master M5L8259AP
and not a slave.

Automatic rotation
The automatic rotation mode is used in applications where
many interrupt requests of the same level are expected
such as multichannel communication systems. In this mode
when an interrupt request is serviced, that request is
assigned the lowest priority so that if there are other interrupt requests they will have higher priorities. This means
that the next request on the interrupt request being serviced
must wait until the other interrupt requests are serviced
(worst case is waiting for all 7 of the other controllers to be
serviced) . The priority and serving status are rotated as
shown in Fig. 5.

BEFORE ROTATION

(IR3 THE HIGHEST PRIORITY
REQUIRING SERVICE)

IS,
ISR STATUS

ISs

ISs

Is.,

IS,

IS,

1

,

HIGHEST PRIORITY

i

AFTER ROTATION
(IR3 WAS SERVICED AND ALL OTHER
PRIORITIES ROTATED CORRESPONDINGLY)
IS,
ISR STATUS

ISs

ISs

Is.,

IS,

IS,

ISo

1010111010101010
HIGHEST PRIORITY

PRIORITY
STATUS

Fig. 5

IS,

LOWEST PRIORITY

i *

An example of priority rotation

In the non-specific EOI command automatic rotation mode is
selected when R=l, EOI=l, SL=O in OCW2. The internal
priority status is changed by EOI or AEOI commands. The
rotation priority A flip-flop is set by R=l, EOI=O and SL=O
which is useful when the M5L8259AP is used in the AEOI
mode.

Specific rotation
Specific rotation gives the user versatile capabilities in interrupt controlled operations. It serves in those applications in

5-80

Level triggered mode/Edge triggered mode
Selection of level or edge triggered mode of the M5L8259AP
is made by ICW1 , When using edge triggered mode not only
is a transition from low-level to high-level required, but the
high-level must be held until the first INTA. If the high-level
is not held until the first I NT A, the interrupt request will be
treated as if it were input on IR7, except that the ISR bit is
not set. When level triggered mode is used the functions are
the same as edge triggered mode except that the transition
from low-level to high-level is not required to trigger the in,
terrrupt request.
In the level triggered mode and using AEOI mode together,
if the high-level is held too long the interrupt will occur immediately. To avoid this situation interrupts should be kept
disabled until the end of the service routine or until the IR
input returns low-level. In the edge triggered mode this type
of mistake is not possible because the interrupt request is
edge triggered.

Reading the M5L8259AP internal status
ISo

01 00

01011101
LOWEST PRIORITY

PRIORITY
STATUS

IS,

which a specific device's interrupt priority must be altered.
As opposed to automatic rotation which automatically sets
priorities, specific rotation is completely user controlled.
That is, the user selects the interrupt level that is to receive
lowest or highest priority. Priority changes can be executed
during an EOI command.

The contents of IRR and ISR can be read by the CPU with
status read. When an OCW3 is Issued to the M5L8259AP and
an RD pulse issued the contents of IRR or ISR can be released onto the data bus. A special command is not required to read the contents of IMR. The contents of IMR can
be released onto the data bus by issuing an RD pulse when
Ao= 1. There is no need to issue a read register command
every time the IRR or ISR is to be read. Once a read register command is received by the M5L8259AP, it remains valid
until it is changed. Remember that the programmer must
issue a poll command every time to check whether there is
an interrupt request and read the priority level. Polling overrides status read when P=l, RR=l in OCW3.

CASCADING
The M5L8259AP can be interconnected in a system of one
master with up to 8 slaves to handle up to 64 priority levels.
A system of 3 units that can be used with the MELPS85 is
shown in Fig. 6.
The master can select a slave by outputting its identification
code through the 3 cascade lines. The INT output of each
slave is connected to the master interrupt request inputs.
When an interrupt request of one of the slaves is to be serviced the master outputs the identification code of the slave
through the cascade lines, so the slave will release the vectored address on the next INTA pulse.
The cascade lines of the master are nomally low-level, and
will contain the slave identification code from the leading
edge of the first INTA pulse to the trailing edge of the last

•
MITSUBISHI
..... ELECTRIC

MITSUBISHI LSls

M5L8259AP
PROGRAMMABLE INTERRUPT CONTROLLER

INSTRUCTION SET

~

Ao

D7

D6

Ds

D4

D3

D2

D,

A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7

A6
A6
A6
A6

A5
As
As
As
0
0
0

1
1
1
1
1
1
1
1

0
1
0
1
0
1

1
1
1
1
0
0
0
0
1
1
1
1
0
0
0

1
1
0
0
1
1
0
0
1
1

A'4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

ICW1
ICW1
ICW1
ICW1
ICW1
ICW1
ICW1
ICW1
ICW1
ICW1
ICW1
ICW1
ICW1
ICW'
ICW1
ICW1

A
B
C
D
E
F
G
H
I
J
K
L
M
N
0
P

0
0
0
0
0
0
0
0

17
18
19

ICW2
ICW3 M
ICW3 S

1
1
1

A'5
S7

20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51

ICW4 A
ICW4 B
ICW4 C
ICW4 D
ICW4 E
ICW4 F
ICW4 G
ICW4 H
ICW4 I
ICW4 J
ICW4 K
ICW4 L
ICW4 M
ICW4 N
ICW40
ICW4 P
ICW4 NA
ICW4 NB
ICW4 NC
ICW4 ND
ICW4 NE
ICW4 NF
ICW4 NG
ICW4 NH
ICW4 NI
ICW4 NJ
ICW4 NK
ICW4 NL
ICW4 NM
ICW4 NN
ICW4 NO
ICW4 NP

1
1
1
1
1
1
1
1
1
1
1

0

52
53
54
55
56
57
58
59
60
61
62
63
64

OCW1
OCW2 E
OCW2 SE
OCW2 RE
OCW2 RSE
OCW2 R
OCW2 CR
OCW2 RS
OCW3 P
OCW3 RIS
OCW3 RR
OCW3SM
OOW3 RSM

Note 4·

5-82

Function

Instruction code
Mnemonic

Number

a

0
0
0
0
0
0
0

,
1
1
1
1

,,
,
1

1
1
1
1
1
1
1
1
1
1
1
1
1
0

a

a
a
0
0

a

0
0
0
0
0
0
0
0

a
a
0
a
a
a
0
a

As
As
As
As
A6
A6
A6
A6
A6
A6

As
As
So
0

a
0
0
0

a
0
0
0

a
a
0
0

a
a
0
0
0

a
0
0

a
0
0
0
0
0
0

0
0
0
0
0
0

a

0
0

0
0
0
0

M7

M6

a
a

a
1
a

a

As
As
A5
As

,,

a
1

b

0
0
0

1
0
1
0
1
0
1

a

0
1
1
0
0

A13
Ss
0

A'2
S4
0

All
S3
0

A,o
S2,
1D2

A9
S,
ID,

0
0
0

0
0
0
0
0

a

0
0
0
0
1
1
1
1

0
1
0
1

a

0
0
1
1
0
0
1
1

a

a

0
0
0

0
1
1
0
0
1
1
0
0

1
0

a

a

0
0
0
0
0
0
0
0
0

a
0
0

a
a
a
0
0
0
0
0
0
0
0
0
0

a
0
0
Ms
1
1
1
1

a
0
0

a
a
0
0
0
0

a

0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
M4

, ,
,

1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1

M,

Mo

L2
0
L2
0

L,

L2
1

L,
0
1
1

Lo
0
Lo
0
0
La
0
1

a

0

a

0
0

0
0

1
1

0

0
0
0
0

1
1
1
1
1

1

0
1
0
1
0
1
0
1

M2

0
0
0
0

1
0

,
,

0

M3

0
0
0
0

0
0

1
0
1

a

a
0
0
0
0

,

1
0
0
1
1
0
0
1
1
0
0
1
1

a
a
L,
a
a

0
0

a

1
0
1
0

,
,

a
0
1

a

0
0
0

Y. yes, N no, E edge, L. level, M: master, S· slave

• MITSUBISHI
...... ELECTRIC

4
4
4
4
8
8
8
8
4
4
4
4
8
8
8
8

Single
y
y
N
N
y
y
N
N
y
y
N
N
y
y
N
N

Trigger

E
L
E
L
E
L
E
L
E
L
E
L
E
L
E
L

8~blt

vectored address
Slave connections (master mode)
Slave Identification code (slave mode)

IDa

a

Intervel

N
N
N
N
N
N
N
N
y
y
y
y
y
y
y
y

As
So

,,

a

a
a
a

1

a

1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

a
1
a

1
0

a
a
0
a

0
0
0
0
0
0
0
1
1
1

a
a
0
a
a
a
a

1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

1
1
1
1
1
1

a
a
a
0
a
a
a

a
a

Do ICW4 required?

SFNM

BUF

AEOI

MELPS86

N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y

N
N
N
N
N
N
N
N

N
N
Y
Y
N
N
y
Y
N
N
y
y
N
N
y
y
N
N
y
Y
N
N
Y
y
N
N
y
y
N
N
y
y

N
Y
N
Y
N
y
N
Y
N
y
N
y
N
Y
N
y
N
Y
N
Y
N
Y
N
y
N
Y
N
y
N
Y
N
y

y
y
y

S
S
S
S
M
M
M
M

Y
Y
Y

y
y
N
N
N
N
N
N
N
N

y
y
y
y
y
y
y
y

S
S
S
S
M
M
M
M

Interrupt mask

EOI
SEOI
Rotate on Non-Specific EOI command (Automatic rotation)
Rotate on Specific EOI command (Specific rotation)

Rotate in AEOI Mode (SET)
Rotate in AEOI Mode (C LEAR)
Set Priority without EO I
Poll mode
Sets Status Read Resister In ISR
Sets Status Read Resister In IRR
Sets Special Mask mode
Reset Special Mask mode

MITSUBISHI LSls

MSL82S9AP
PROGRAMMABLE INTERRUPT CONTROLLER

SWITCHING CHARACTERISTICS

(Ta=-20-75°C, Vcc =5V±10%, Vss=OV, unless otherwise noted)
Limits

Symbol

Test conditions

Parameter

Typ

Min
tpZV(R~DQ)

Data output enable time after read

tpvzeA-OQ)

Data output disable time after read

tpZV(A-DQ)

Data output enable time after address

tPHL(R-EN)

Propagation time from read to enable signal output

tPLH(R-EN)

Propagation time from read to disable signal output

tPL.H(IR_INT)

Propagation time from Interrupt request input to mterrupt request output

tPLV(INTA_CAS)

Propagation time from INTA to cascade output (master)

10
C L =100pF

Where $PiEN
pin is 15pF

Data output enable trme after cascade output (slave)
tpZV ( CAS-DO)
-Note 5 : INTA signal is considered read signal
CS signal is considered address signal
0.45-2. 4V
Input pulse level
Input pulse rise time
20ns
Input pulse fall time
20ns
Reference level input V'H=2V, V'L =0. BV
output VoH =2V, VOL =0. BV

TIMING DIAGRAM
Write Mode
CS. Ao

}
\

twlwl

K

---

thlw-AI

tSU(A-W)

J'---

~

thlw-DO)

-r- I-

tsu(oo-w)

~~

0,-00

:K

Read Mode

CS,Ao

J~

K
thiR-AI

tSU(A-R)

twiRl

\

j
tPVZeR-DQ)

tpZV(A-DQ)

tpzv(A-ool

i/7r-

0,-00

tPHL(R-EN}

\

~r

5-84

~\

\~l-

•
MITSUBISHI
...... ELECTRIC

~/
tPLH(R-EN)

I.

Unit
Max

200

ns

100

ns

200

ns

125

ns

150

ns

350

ns

565

ns

300

ns

MITSUBISHI LSls

MSL8279P-S
PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE

DESCRIPTION

PIN CONFIGURATION (TOP VIEW)

The M5L8279P-5 is a programmable keyboard and display
interface device that is designed to be used In combination
with an 8-bitl16-bit microprocessor. This device is fabricated
with N-channel silicon-gate ED-MOS process technology
and is packed in a 40-pin OIL package. It needs only single
5V power supply.

RETURN LINE J R2 ~ 1
INPUTS R3 ~ 2

Vee (5V)

1

CLOCK INPUT ClK ~ 3

REQUE~~T6~~~0t

~

4

R4~

5

INT

RETURN LINE
INPUTS

FEATURES

SCAN TIMING
OUTPUTS

8
RESET INPUT RESET ~ 9
READ S~~~Bf RD ~ 10
WRITE S~~~Bf WR ~ 11
00-12
R7~

•
•

Single 5V supply voltage
TTL compatible

•
•
•
•
•
•
•
•
•

Keyboard mode
Sensor matrix mode
Strobed mode
Internally provided key bounce protection circuit
Programmable debounce time
2-key 10ckoutlN-key rollover
8-character keyboard FIFO
Internally contained 16 X 8-bit display RAM
Programmable right and left entry

DISPLAY (B)
OUTPUTS

DISPLAY (A)
OUTPUTS

BIDIRECTIONAL
DATA BUS

24-0A3

23 ~

~rtpNl~~gUTPUT

BD

22 ~ CS fNH~0TSElECT
(OV) vss

2-1 ~ AD ~mtRplf,;~d:v

---,'--_ _ _ _- I

APPLICATION

Outline 40P4

Microcomputer 1/0 device
64 contact key input device for such items as electronic
cash registers
Dual 8- or single 16-alphanumeric display

debounce buffer and an 8 X 8-bit FIFOISENSOR RAM. It
operates In anyone of the scanned keyboard mode, scanned sensor matrix mode or strobed entry mode. The display
portion is provided with a 16 X 8-bit display RAM that can
be organized into a dual16X 4 configuration. Also, an 8-digit
display configuration is possible by means of programming.

FUNCTION
The total chip, consisting of a keyboard interface and a display interface, can be programmed by eight 8-bit commands. The keyboard portion is provided with a 64-bit key

BLOCK DIAGRAM
RESET CLOCK
INPUT INPUT

BIDIRECTIONAL
DATA BUS

~~~~~~~~~

CONTROL/DATA SELECT INPUT
CHIP SELECT INPUT
WRITE STROBE INPUT
READ STROBE INPUT

I,
RETURN LINE INPUTS

I,
OA, OA, OA, 01<, OB3 OB, OB, aBo

BD

~ DISPLAY (B)BLANKING
OUTPUTS
OUTPUTS
gl~~~~i

5-86

• MITSUBISHI
' " ELECTRIC

-~

MITSUBISHI LSls

MSL8279P-S
PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE

COMMAND DESCRIPTION

4.

There are eight commands provided for programming the
operating modes of the M5L8279P-5. These commands are
sent on the data bus with the signal CS in low-level and the
signal Ao in 1 and are stored in the M5L8279P-5 at the rising
edge of the signal WR. The order of the command execution
is arbitrary.
1.

Mode Set Command
MSB
Code:

LSB

1 0 1 0 1 OlD 1 D 1 K 1 K 1 K 1

QJ2... (Display mode set command)

oa

8-8-bit character display-left entry
16-8-bit character display-left entry (Notel)
1 a
8-8-bit character display-right entry
1 1 16-8-bit character display-right entry
KKK (Keyboard mode set command)
0
Encoded display keyboard mode - 2-key lockout (Notel)
o a 1 Decoded display keyboard mode - 2-key lockout
o 1 0 Encoded display keyboard mode - N-key rollover
1 1 Decoded display keyboard mode - N-key rollover
100 Encoded display, sensor mode
1 0 1 Decoded display, sensor mode
Encoded display, strobed entry mode
1
1 1 1 Decoded display, strobed entry mode

o1

a a
o

a

Note1: Default after reset.

2.

MSB
Code:

MSB
Code:

LSB

11 1 0 1 0 1AliA 1 A 1 A 1 A

I

With this command, following display RAM read/write
addressing is achieved without changing the data readout
source (FIFO or display RAM). Meaning of AI and AAAA are
identical with read display RAM command.
6. Display Write inhibit/Blanking Command
MSB

LSB

r-11-r"1-0TI--r"I-x'I-IW-'I-'W-r-1B-L"!"""IB-'LI X = Don't care

A

1 0 1 0 l i p 1 pip 1 pip 1

MSB

I0 i 1 I 0

1

B A B

LSB

The external clock is divided by the prescaler value PPPPP
designated by this command to obtain the basic internal frequency.
When the internal clock is set to 100kHz, it will give a 5. 1ms
keyboard scan time and alD. 3ms debounce time. The prescale value that can be specified by PPPPP is from 2 to 31.
In case PPPPP is 00000 or 00001, the prescale is set to 2.
Default after a reset pulse is 31, but the prescale value is
not cleared by the clear command.
3. Read FIFO Command

Code:

IA

This command is used to specify that the following data
readout (CS'Ao'RD) is from the display RAM. As long as
data is to be read from the display RAM, no additional commands are necessary.
The data AAAA is the value with which the display RAM
read/write counter is set, and it specifies the address of the
display RAM to be read or written next.
AI is the auto-increment flag. Turning AI to 1 makes the
address automatically incremented after the second read/
write operation. This auto-increment bit does not affect the
auto-increment of FIFO readout in the sensor mode.
5. Write Display RAM Command

Program Clock Command
Code :

LSB

1 0 11 11 1AliA 1 A 1 A

Code:

MSB

LSB
1AI

I X I A 1A 1A 1 X =

Don't care

This command is used to specify that the following data
readout (CS'Ao'RD) is from the FIFO. As long as data is to
be read from the FIFO, no additional commands are necessary.
AI and AAA are used only in the sensor mode. AAA designates the address of the FIFO to be read, and AI is the autoincrement flag. Turning AI to 1 makes the address automatically incremented after the second read operation. This
auto-increment bit does not affect the auto-increment of the
display RAM.

5-88

Read Display RAM Command

The IW is a write inhibit bit to the display RAM that corresponds with the output A or B. Inhibit is activated by turning
the IW 1.
The BL is used in blanking the out A or B. Blanking is activated by turning the BL 1. Setting both BL flags makes the
signal BD low-level so that it can be used in 8-bit display
mode.
Resetting the flags makes all IW and BL turn O.
7. Clear Command
MBS

LSB

11 11 1 0 IColColColcFlcAI

Code:

Co: Clears the display RAM.
Co CD CD
X X No specific performance
X Entire contents of the display RAM are
turned O.
The contents of the display RAM are
turned 20H (00100000 = OA30A20A I OAo
OB 30B20B I OBo) .
Entire contents of the display RAM are
turned 1.

o

•
MITSUBISHI
...... ELECTRIC

o

o

MITSUBISHI LSls

MSL8279P-S
PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE

CPU INTERFACE
1. Command Write
A command is written on the riSing edge of the signal WR
with CS low-level and AQ 1.
2. Data Write
Data is written to the display RAM on the rising edge of the
signal WR with CS low-level and Ao O.
The address of the display RAM is also incremented on the
riSing edge of the signal WR if AI is set for the display RAM.
3. Status Read
The status word is read when CS and RD are low-level and
AQ is 1. The status word appears on the data bus as long as
the signal RD is low-level.
4. Data Read
Data is read from either the FIFO or the display RAM with
CS and RD are low-level and Ao is O. The source of the data
(FIFO or display RAM) is decided by the latest command
(read display or read FIFO). The data read appears on the
data bus as long as the signal RD is low-level.
The trailing edge of the signal RD increments the address of
the FIFO or the display RAM when AI is set. After the reset,
data will be read from the FIFO, however.

H~ever, 'both the key scan cycle and the key debounce
cycle are the same as in the encoded mode.)
1. 2-Key Lockout (Scanned Keyboard Mode)
The detection of a new key closure resets the internal debounce counter and starts counting. At the end of a key debounce cycle, the key is checked and entered into the FIFO
if it is still down. An entry in the FIFO sets the INT output
high. If any other keys are depressed in a key debounce cycle, the internal key debounce counter is reset each time it
encounters a new key. Thus only a single-key depression
within a key debounce duration is accepted, but all keys are
ignored when more than two keys are depressed at the
same time.

Example 1 : Accepting two successive key depressions
KEY1

t~EY DEBOUNC~lCYCLE
KEY2

Note 2 :

: Debounce counter reset
: Key input

Ao
1

CS

RD

WR

Operation

L

H

L

Command wnte

0

L

H

L

Data write

1

L

L

H

Status read

0

L

L

H

Data read

X

H

X

X

No operation

Example 2 : Overlapped depression of three keys
KEY 1
KEY2

+.-----1

KEY DEBOUNCE CYCLE
KEY 3

KEYBOARD INTERFACE
Keyboard interface is done by the scan timing signals (80S3) , the return line inputs (Ro - R7) , the SHIFT and the
CNTRL inputs.
In the decoded mode, the low-order of 2 bits of the internal
scan counter are decoded and come out on the timing pins
(So-S3). In the encoded mode, the four binary bits of the
scan counter are directly output on the timing pins, thus a 3\ to-8 decoder must be employed to generate keyboard scan

Note 3 : Only key 2 Is acceptable

timing.
The return line inputs (Ro-R7), the SHIFT and the CNTL Inputs are pulled up high-level by internal pullup transistors
until a switch closure pulls one low.
The internal key debounce logic works for a 64-key matrix
that is obtained by combining the return line inputs with the
scan timing.
For the keyboard interface, M5L8279P-5 has four distinctive
modes that allow various kinds of applications. In the following explanation, a "key scan cycle" is the time needed to
scan a 64-key matrix, and a "key debounce cycle" needs a
duration of two "key scan" cycles. (In the decoded mode 32
keys, unlike 64 keys in the encoded mode, can be employed
for a maximum key matrix due to the limit of timing signals

5-90

u-u
+
t

• MITSUBISHI
..... ELECTRIC

MITSUBISHI LSls

MSL8279P-S
PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE

DISPLAY INTERFACE
The display interface is done by 8 display outputs (OAoOA3. OBo - OB3). a blanking signal (BD). and scan timing
outputs (SO-S3).
The relation between the data bus and the display outputs is
as shown below:

Timing relations of So. BD. and display outputsTbAo - OA3•
OBo-OB3) are shown below.

So ( E n c : : l L - - - . J
mode)

Do

!
OA3

OA2

OA,

OAo

OB3

OB2

OBI

OBo

Clearing the display RAM is not achieved by the reset signal
(9-pin) but requires the execution of the clear command.
The timing diagrams for both the encoded and decoded
modes are shown below.
For the encoded mode. a 3-to-8 or 4-to-16 decoder is required. according to whether eight or sixteen digit display
used.
(1) Encoded mode

II

8,

L

83

L

(2) Decoded mode
So
8,
8,
83

Note 4 : Here Pw is 640",s If the internal clock frequency is set to
100kHz.

5-92

"

"

Note 5 : Values of the output data shown in the slanted line areas are
decided upon the clear command executed last to become
the value of the display RAM after the reset. The values in the
slanted areas after reset will go low-level. In the same manner. the values OAo-OA3. 08 0 -083 are dependent on the
clear command executed last. When the both A and 8 are
blanked. the signal BD will be in low-level.

So

8,

"

•
MITSUBISHI
"'ELECTRIC

MITSUBISHI LSls

MSL8279P-S
PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE

ABSOLUTE MAXIMUM RATINGS
Symbol

Conditions

Parameter

Vee

Supply voltage

V,

Input voltage

Va

Output voltage

With respect to Vss

Pd

Maximum power dissipation

Topr

Operatmg free-arr temperature range

TstQ

Storage temperature range

Ta=25'C

RECOMMENDED OPERATING CONDITIONS

Ratings

Unit

-0.5-7

V

-0.5-7

V

-0.5-7

V

1000

mW

-20-75

"C

-60-150

'C

(Ta=-20-75'C. unless otherwIse noted.)
Limits

Symbol

Unit

Parameter

Vee

Supply voltage

Vss

Supply voltage (GNO)

Min

Nom

Max

5

5.5

4.5

.-

V

--

0

ELECTRICAL CHARACTERISTICS

V

(T a=-20-75'C , Vee =5V±10%, Vss=OV, unless otherwise noted.)
limits

Symbol

Parameter

Test conditions
Min

Typ

Max

Unrt

V1H(RL)

HIgh-level mput voltage, for return line Inputs

2.2

V,H

High-level mput voltage, all others

2.0

V'L(RU

Low-level mput voltage, for return line mputs

Vss-O.5

1.4

V

V,L

Low-Jevel Input voltage, all others

Vss-O.5

0.8

V

V OH

High-level output voltage

IOH=-400,uA

2.4

VOH(INT)

High-level output voltage, Interrupt request output

IOH=-400,uA

3.5

VOL

Low-level output voltage

10L =2.

Icc

Supply current from V cc

2mA

V
V

V
V

0.45
120

-

V

rnA

10

Input current, return line Inputs, shift Input and control

VI=VCC

Input

V,=OV

I,

Input current, all others

V,=OV, Vee

-10

10

/lA

loz

Off-state output current

Vo=OV-Vee

-10

10

,uA

C,

Input terminal capacitance

VI=VCC

5

10

pF

Co

Output terminal capacitance

Vo=Vcc

10

20

pF

II(RL)

5-94

•
MITSUBISHI
. . . . ELECTRIC

/lA

-100

MITSUBISHI LSls

MSL8279P-S
PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE

TIMING DIAGRAM
Read operati on

tOIRl
tWIRl

th(R-AJ

tSU{A-R)

CS, Ao

-

X:

K

'"

.-~

tPVZ(R

tPZV(R-OQ)
tPZV(A-DQ)

q

Do-D,
(DATA OUTP UTS)

00)

~~

~

~

J

Write operation
tOlwl
tW(W)

thlw-Al

tSU{A-W)

Do-D,
(DATA INPUTS)

Clock input
tOI
tWill

ClK

5-96

3'--

V~

~~

• MITSUBISHI
. , . , ELECTRIC

¢)

W

MITSUBISHI LSls

MSL8279P-S
PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE

APPLICATION EXAMPLE

CNTL

CONTROL

SHIFT

x

SHIFT
RETURN
a-ROW
LINES
KEY
CODE

a

a a KEY
KEYBOARD
MATRIX

~Vcc(5V)

a LINES

37
36
CNTL SHIFT Ro-R,
INTERRUPT REQUEST

DATA BUS

8-BIT
MICROPROCESSOR
SYSTEM
CONTROL!

ADDRESS BUS {

CLOCK

INT

4 INT

BIDIRECTIONAL
BUS
a

00-0,

Vee
Vss

~

8

20

r-;h

GND(OV)
3-8 DECODER

RD

10...

WR

u

RESET

9

CS

22..

Ao

21

ClK

3

3

RD
WR

4

So-S,

SCAN LINE
4

RESET
CS

4-16 DECODER
DRIVE

Ao
ClK

BD

~3

BD
16

OBo-OB, OAo-OA,

M5L8085AP
BLANKING
4

4

Note 8

5-98

(Note a)

M5L8279P-5

DISPLAY
DATA

ADDRESS

DISPLAY
16-DIGITS

When using an a-bit character display of more than 9 digits for the decoder display, it is necessary to provide
two decoders for example 4 -10 decoder, 4 -16 decoder and key scan 3 - a decoder.
Only So, S, and So may be used as inputs to the key scan 3 - 8 decoder.
(Don't drive the keyboard decoder with the MSB of the scan line)

• MITSUBISHI
..... ELECTRIC

(Note a)

MITSUBISHI LSls

NOTICE FOR CMOS PERIPHERALS

4. TRANSFER' CHARACTERISTICS AND
POWER DISSIPATION
For COMS devices, the circuit threshold voltage is approximately one-half of Vcc. Contrasted with NMOS logic,
where threshold voltage is a fixed level not related to supply voltage, ideal transfer characteristics can be achieved.
In order to maintain compatibility with the conventional
NMOS devices, transfer characteristics of CMOS peripherals 110 circuits have been established at TTL level.
Fig. 4 illustrates input voltage V'N versus supply current Icc
for M5M82C55AP-2. Here, when V'N reaches 1.3 to 1.5V,
the resulting switch in internal circuits causes a sharp increase in Ice flow.

creases power diSSipation.
The M5M82C55AP-2 illustrated in Fig. 4 has parallelconnected I/O ports, and is relatively limited in switching
operations. However, devices such as the programmable
timer M5M82C54P are subjected to constant clock operations, and the current flow for each CMOS circuit must be
added to get the total for the device. As shown in Fing. 5,
currnet dissipation increases along with increases in operating frequency.

I

Vee=SV
DUTY=SO%
Ta=25l:

(PORT-Ao MODE 0 INPUT)
2S0 1

Ta =2S·C

Vee=S.SV""",

"--tln put 0 utput 1---(').-'VV'v--1.

1'1,
O.Ol.uF

Condition (e) can be created by exceeding the absolute
maximum voltage ratings at the Vee pin. Also, even though
Vee is within the recommended operating conditions, device latchup can be caused by the surge voltage superimposing at power ON, or crosstalk between lines. The voltage at Vee should never exceed absolute maximum rating
values under any circumstances.
Provisions should be made to reduce power ON surge voltage to a minimum. and as described in section 6, a capacitor should be connected beteen Vec and Vss to reduce impedance in the power line.

InputJUL

Vee~---Vee

Vee

14

~---Vee

Nocapacitor

Capaeitorused

Preventing latchup when driving large current
circuits

Conditions (b) or (d)
Applying a constant voltage to an output pin is not one of
the normal usage configurations of a CMOS device, but a
capacitor connected between output and Vcc (or Vss)
would be a cause for latchup. This is due to the high Impedance created in the power supply line, combined with the
fact that switching the power supply on and off produces
fluctuations in the power supply line which causes the
capacitor to discharge a trigger current.

6-8

It:. _ _ ________ V ss

Preventing latchup when using differential circuits
Vee

Fig.

- , . - - - " - Vee

• MITSUBISHI
. . . . ELECTRIC

MITSUBISHI LSls

M33210GS-20/FP-20
CMOS 32-BIT PARALLEL MICROPROCESSOR (M32/100)

BLOCK DIAGRAM

INSTRUCTION

I

FETCH UNIT

BRANCH BUFFER

DATA INPUT/

I

,

OUTPUT CIRCUIT

DATA BUS

il

INSTRUCTION
DECODE UNIT
BRANCH
EI
PREDICTION TABLE

1'1

I .;

OPERAND ADDRESS
AND PC ADDRESS
GENERATION UNIT

r= ~

ADDRESS
OUTPUT CIRCUIT

11
MICRO-ROM AND
CONTROL UNIT

7-4

f----3o

EXECUTION UNIT

INTERNA\I
REGISTERS

• MITSUBISHI
. . . . ELECTRIC

G

ADDRESS BUS

MITSUBISHI LSls

M33220GS-20
CMOS 32·BIT PARALLEL MICROPROCESSOR (M32/200)

BLOCK DIAGRAM

,----..

INSTRUCTION
PREFETCH UNIT

INSTRUCTION
CACHE

BRANCH
WINDOW

I
I

CONTROL UNIT

~

INSTRUCTION
DECODE UNIT

~

I

MICROPROGRAMS

1
EXECUTION UNIT

MEMORY MANAGEMENT UNIT

I

ALU

I I

I

TLB

I

REGISTERS

I

1

I
I

~

INPUT/OUTPUT CONTROL UNIT

1

ADDRESS BUS

7-6

t

DATA BUS

• MITSUBISHI
;"ELECTRIC

STACK CACHE

I

STORE BUFFER

I

I

MITSUBISHI LSls

M33230GS-20
CMOS 32-BIT PARALLEL MICROPROCESSOR (M32/300)

PIN ASSIGNMENT
PIN CODE

NAME

PIN CODE

NAME

PIN CODE

NAME

PIN CODE

NAME

PIN CODE

NAME

A2

*2
OCCPRG

C3

G2

FLOAT

N2

T18

Vee

G3

*2

N3

A'3
A,s

Ul

*1
Vss

C5

Vss
GBR
WAY

G16

N16

Vss

U2

A"._
Vss

C6

Vee

G17

Vee
CPSTo

N17

Vee

C7

Gl,8

CPST,

N18

U4

D30

C8

*2
RNG,

A'9
A30

U3

*2
HACK

HI

A,

Pl

A,.

U5

D28

Vss
BATo
HALT

C9

BAT,

H2

Ao

P2

A"

U6

Vss

Cl0

Vss
CLK!

H3

P16

A"
A,.

U7

H16

Vee
CPST,

P3

Cl1

U8

D'3
D,o

A3
A4
A5
A6
A7
A8
A9
Al0
All

HREQ

C12

CLK!

H17

NCA

P17

A27

U9

Vee

A12

RESET

C13

Vss

H18

BLACKF

P18

A28

Ul0

Vee

A13

Vee
BCLK,

C14

Vee

Jl

A.

Rl

Ul1

C15

J2

D'8
D,s

BCLK,

C16

J3

A3
A,

R2

A15

Vss
L/C

A"
Vss

R3

A21

U13

A16

A19 Vss

C17

BLOCK

J16

BLACKS

R4

Vee

U14

A17

A" AS

C18

Vss

J17

Vss

R15

D8

*2

Dl

IRLo

J18

Vee

R16

Vss
D,

U15

Bl

U16

D,

B2

*2
jCCPRG

D2

IRL,

Kl

As

R17

A,s

U17

D3

B3

D3

*2

K2

Vs•

R18

A'6

U18

D,

B4

TCS

D15

A'9

V2

Vee

D16

K16

A6
BC,

Tl

*1

Vss
DS

K3

B5

T2

A"

V3

Vss

B6

D17

RETRY

K17

BC,

T3

D'9

D18

BERR

K18

BC3

T4

V5

B8

RNG o

El

*1

Ll

A7

T5

A'3
Vss
D3,

V4

B?

Vee
DAT

D'6
D,s

B9

BAT,

E2

L2

As

T6

E3

L3

E16

Vee

U6

A9
NCAO

T7

Bl1

Vee
Vee

D"
D,.

V7

Bl0

*1
IRL,

CPST, D"

V8
V9

B12

Vss

E17

ASDC

L17

Vss

T9

Vss

Vl0

Vss

B13

Vss

E18

SDC

U8

BCo

T10

Vee

Vl1

*2

Fl

*1

Ml

~~

D'9

B14

Ttl

V12

B15

Vee

F2

*1

M2

D"
D,.

V13

D"
Vss

B16

Vee
Vss BS

F3

B17

F16

*1
CPDC

B18

Vee R/W

F17

Cl

Vee

C2

Vss

A14

* 1 : Connect to Vee.
* 2 : No connect

7-8

C4

T8

T12

f-

U12

V6

D'3
D,o

D"
Vee

Vss

M3

A"
Vee

.-

M16

A31

T14

D"
Vss

V15

D"
D9

Vee

M17

MVIN

T15

Ds

V16

v,,,,,-----

F18

Vss

M18

LOC

T16

D.

V17

Gl

Vss

Nl

A"

T17

Do

• MITSUBISHI
..... ELECTRIC

T13

V14

D5

--

MITSUBISHI LSls

M33241GS
CMOS D~A CONTROLLER (M32/DMAC)

BLOCK DIAGRAM
INTERRUPT

aus ARBITRATION

DIITA CONTROL

EXCEPTION
SIGNAL

t----t ~~~~~~N
SECTION

ADDRESS __-~,...

CLOCK

_

TRANSFER
REQUEST
SIGNAL

PERIPHERAL
EQUIPMENT
CONTROL
SIGNAL

TRANSFER
REQUEST
CONTROL
SIGNAL

MICRO
CONTROL
SIGNAL

PLA

SECTION

TRANSFER
OPERATION
CONTROL
SECTION

MICROSEQUENCE CONTROL UNIT

8-4

• MITSUBISMI
"ELECTRIC

ERROR
TESTING
SECTION

MITSUBISHI LSls

M33242SP/J
CMOS INTERRUPT CONTROLLER (M32/IRC)

BLOCK DIAGRAM

LOCAL
INTERRUPT
INPUT

R, -;..

q

~J

"

BUS
BIRo-BIR ,

---;0

INTERRUPT

-

LEVEL

INTERRUPT

CONVERSION

OUTPUT

r'"

~BI

~I RLo-IRL,

r'"

l~
f-U
VECTOR
GENERATION

INPUT

ACKNOWLEDGMENT
CONTROL

FSE L - -

30---;0

Ni--

cs--

CKIN - - ; 0 .

f---- U
BUS
INTERFACE

r--- A

EL-

0
C
E
B

ETLK-

8-6

• MITSUBISHI
..... ELECTRIC

MITSUBISHI LSls

M33243GS-2S,-30
CMOS TAG MEMORY (M32/TAGM)

BLOCK DIAGRAM

Ao

A.

TO,

HITIREPLACE
INFO

MHENSL

OUTPUT CONTROUMULTIPLEX
BLOCK

EXTH

MHIT

~--+--------------oHIT

.---------------0 HITo/REPo
~--------0

HIT,/REP,

.----------0 HIT,/REP,
MPX

.----------
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