1990_NEC_Single Chip_Microcontroller_Data_Book 1990 NEC Single Chip Microcontroller Data Book
User Manual: 1990_NEC_Single-Chip_Microcontroller_Data_Book
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SINGLE-CHIP MICROCONTROLLER
DATA BOOK
i
I DISTRIBUTED
i
//I~..
/MERIT
'I"
NEe
BY:
MERIT ELECTRONICS INC
2070 RingwOod Ave
San Jose, CA 95131·
(408) 434-0800
•
•
I
I
NEe
NEe Electronics Inc.
1990
Single-Chip Microcontroller
Data Book
May 1990
Document No. 50053
©1990 NEe Electronics Inc.lPrinted in U.S.A.
No part ofthis document may be copied or reproduced in any form or by any means withoutthe prior written consent
of NEG Electronics Inc. The information in this document Is subject to change without notice. Devices sold by NEG
Electronics Inc. are covered by the warranty and patent indemnification provisions appearing in NEG Electronics Inc.
Terms and Gonditions of Sale only. NEG Electronics Inc. makes no warranty, express, statutory, implied, or by
description, regarding the information set forth herein or regarding the freedom of the described devices from patent
infringement. NEG Electronics Inc. makes no warranty of merchantability or fitness for any purpose. NEG Electronics
Inc. assumes no responsibility for any errors that may appear in this document. NEG Electronics Inc. makes no
commitment to update or to keep current the Information contained in this document.
/
t\'EC
ii
t-IEC
Selection Guides
a
Reliability and Quality Control
fJ
JlPD7500 Series:
4-Bit Microcomputers
JlPD75000 Series:
4-Bit Microcomputers
Jl PD7800 Series:
8-Bit Microcomputers
II
II
EI
JlPD78K2 Series: 8-Bit Microcomputers
II
JlPD78K3 Series:
i6-Bit Microcomputers
II
JlPD722x Series:
LCD Controller/Drivers
II
Development Tools
Package Drawings
iii
m
1m
ftlEC
iv
t-IEC
Contents
Section 1
Selection Guides
Single-Chip Microcomputers
1-3
Figure 6. NEC Quality and Reliability Targets
2-10
JlPD75XX Series Development Tools
1-7
Appendix 1. Typical QC Flow
2-12
JlPD75XXX Series Development Tools
1-9
Appendix 2. Typical Reliability Assurance
Tests
2-15
Appendix 3. New Product/Process Change
Tests
2-16
Appendix 4. Failure Analysis Flowchart
2-17
JlPD78XX Series Development Tools
1-11
JlPD782XX Series Development Tools
1-13
JlPD783XX Series Development Tools
1-15
PG-1500 Programming Adapters
1-17
V-Series Microprocessors and Peripherals
1-19
Intelligent Peripheral Devices (IPD)
1-23
DSP and Speech Products
1-25
V-Series Development Tools
1-27
DSP and Speech Development Tools
1-31
Section 2
Reliability and Quality Control
Introduction
2-3
Built-In Quality and Reliability
2-3
Technology Description
2-3
Approaches to Total Quality Control
2-3
Implementation of Quality Control
2-5
Reliability Testing
2-7
Life Distribution
2-7
Failure Distribution at NEC
2-7
Infant Mortality Failure Screening
2-8
Long-Term Failure Rate
2-8
Accelerated Reliability Testing
2-8
Failure Rate Calculation/Prediction
2-9
Product/Process Changes
2-10
Failure Analysis
2-10
NEC's Goals on Failure Rates
2-10
Summary and Conclusion
2-10
Figure 1. Quality Control System Flowchart
2-5
Figure 2. New Product Development Flow
2-6
Figure 3. Electrical Testing and Screening
2-6
Figure 4. Reliability Life (Bathtub) Curve
2-7
Figure 5. Typical Reliability Test Results
2-9
Section 3
I'PD7500 Series:
4-Bit, CMOS Microcomputers
I'P D75 02/03
4-Bit, Single-Chip CMOS Microcomputers
With LCD Controller/Driver
3-3
I'P D75 07/0 8
4-Bit, Single-Chip CMOS Microcomputers
3-19
I'PD7507H/08H/75CG08HE
4-Bit, Single-Chip CMOS Microcomputers
3-39
I'PD7527A/28A/75CG 28E
4-Bit, Single-Chip CMOS Microcomputers
With FIP Driver
3-53
I'PD7533/75CG33E
4-Bit, Single-Chip CMOS Microcomputers
With A/D Converter
3-65
I'PD7537A!38A/75CG38E
4-Bit, Single-Chip CMOS Microcomputers
With FIP Driver
3-85
I'PD7554/54A/64/64A
4-Bit, Single-Chip CMOS Microcomputers
With Serial I/O
3-99
I'PD75P54/P64
4-Bit, Single-Chip, One-Time Programmable
(OTP) CMOS Microcomputers With Serial I/O
3-121
I'PD7556/56A/66/66A
4-Bit, Single-Chip CMOS Microcomputers
With Comparator
3-141
I'PD75P56/P66
4-Bit, Single-Chip, One-Time Programmable
(OTP) CMOS Microcomputers With
Comparator
3-163
v
NEe
Contents
Section 4
p.PD75000 Series:
4-Bit, High-Integration Microcomputers
Section 6
p.PD78K2 Series:
8-Bit, Advanced Microcomputers
I'PD7500x/7SPOO8
General-Purpose 4-Bit Microcomputers
With Multiple II0s
4-3
"PD75028/75P036
General-Purpose4-Bit Microcomputers
With AID Converter
4-27
"PD7822X
Advanced, 8-Bit Real-Time Control
Microcomputers With Analog Comparators
"PD75048/75P056
General-Purpose 4-Bit Microcomputers
With EEPROM and AID Converter
4-35
"PD7823X
Advanced, 8-Bit Real-Time Control
Microcomputers With AID and DIA Converters
"PD751 xx/75P1 xx
High-End 4-Bit Microcomputers
4-43
I'PD7520x/7521 x/75CG 2xx/75P216A
4-Bit Microcomputers
With FIP (VF) ControllerlDriver
4-95
"PD7821x
Advanced, 8-Bit Real-Time Control
Microcomputers With A!DConverter
4-123
"PD7831 xA/78P31 xA
i6/8-Bit, Single-Chip CMOS Microcomputers,
Real-Time Control Oriented
"PD7530x/31 x/P308/P316
4-Bit Microcomputers
With LCD ControllerlDriver
4-135
"PD7832x
Advanced, 8/i6~Bit, Real-Time Control
Microcomputers With AID Converter
"PD75328/75P328
4-Bit Microcomputers
With LCD ControllerlDriver and AID Converter
4-191
"PD71P301
Memory Extender and Port Re-Creation Logic
(Turbo Access Manager)
6-119
7-3
7-61
7-113
Section 8
p.PD722x Series:
Intelligent LCD Controller/Drivers
Section 5
p.PD7800 Series:
8-Bit, General-Purpose Microcomputers
vi
6-63
Section 7
p.PD78K3 Series:
16-Bit, Advanced Microcomputers
"PD75268
4-Bit Microcomputer
With FIP (VF) ControllerlDriver
"PD78Cix/78C1xA/CG14/CP14
8-Bit CMOS Microcomputers
With AID Converter
6-3
5-3
"PD7225
CMOS, Intelligent, Alphanumeric
LCD Controller/Driver
8-3
"PD7227
CMOS, Intelligent, Dot-Matrix
LCD Controller/Driver
8-13
"PD7228/28A
CMOS, Intelligent, Dot-Matrix
LCD Controller/Driver
8-21
NEe
Contents
Section 9
Development Tools
4-Bit; pPD7500 Series
8-Bit; pPD78K2 Series (cont)
EVAKIT-7500B
For the IlPD7500 Series
9-3
IE-78210
In-Circuit Emulator
9-51
ASM75
Absolute Assembler for the IlPD7500 Series
9-7
IE-78220
In-Circuit Emulator
9-55
CC782XX
C Compiler Package for the IlPD782XX
Series
9-59
RA78K2
Relocatable Assembler Package for the
IlPD782XX Series
9-63
ST78K2
Structured Assembler Preprocessor for the
IlPD782XX Series
9-67
4-Bit; pPD75000 Series
RA75X
Relocatable Assembler Package for the
IlPD75000 Series
ST75X
Structured Assembler Preprocessor for the
IlPD75000 Series
9-9
9-15
8oBit; pPD7BOO Series
DDK-78C10
Evaluation Board for the IlPD78CXX Series
9-19
IE-78C11
In-Circuit Emulator
9-23
DDK-78310A
Evaluation Board for the IlPD78310A
9-71
CC87
Micro-Series T• C Compiler Package for the
IlPD7800 Series
9-27
EB-78320
Evaluation Board for the IlPD78320
9-75
9-79
RA87
Relocatable Assembler Package for the
IlPD7800 Series
9-29
IE-18310A
In-Circuit Emulator
IE-78320
In-Circuit Emulator
9-83
CC7831X
C Compiler Package for the IlPD7831X/
IlPD7831XA Series
9-89
CC7832X
C Compiler Package for the IlPD7832X
Series
9-93
RA78K3
Relocatable Assembler Package for the
IlPD7831X/7832X
9-97
8-Bit; pPD78K2 Series
DK-78K2
IlPD782XX Designer Kits
9-33
EK-78K2
IlPD782XX Evaluation Kits
9-35
IK-78K2
IlPD782XX In-Circuit Emulator Kits
9-37
DDB-78K2
Evaluation Boards for the IlPD782XX Series
9-39
EB-78210
Evaluation Board for the IlPD78213
9-43
EB-78220
Evaluation Board for the IlPD78220
9-47
8/16-Bit; pPD78K3 Series
ST78K3
Structured Assembler Preprocessor for the
pPD783XX Series
9-101
PG-1S00 Series
EPROM Programmer
9-105
vii
NEe
Contents
Section 10
Package Drawings
Package/Device Cross-Reference
10-3
64-Pin Ceramic LCC (w/Window)
10-20
20-Pin Plastic Shrink DIP
10-5
64-Pin Ceramic Piggyback Shrink DIP
10-21
20-Pin Plastic SOP
10-5
64-Pin Ceramic Piggyback QUIP
10-22
24-Pin Plastic Shrink DIP
10-6
64-Pin Ceramic Piggyback QFP
10-23
24-Pin Plastic SOP
10-6
64-Pin Plastic QFP (2.55 mm thick)
10-24
40-Pin Plastic DIP
10-7
64-Pin Plastic QFP (1.5 mm thick)
10-25
40-Pin Plastic Shrink DIP
10-8
64-Pin Plastic QFP (2.7 mm thick)
10-26
10-9
64-Pin Plastic QFP (2.05 mm thick)
10-27
64-Pin Ceramic QUIP (w/window)
10-28
40-Pin Ceramic Piggyback DIP
42-Pin Plastic DIP
10-10
42-Pin Plastic Shrink DIP
10-10
64-Pin Plastic QUIP
10-29
42-Pin Ceramic Piggyback DIP
10-11
68-Pin PLCC
10-30
44-Pin Ceramic LCC (w/window)
10-12
74-Pin Plastic QFP
10-31
44-Pin Plastic QFP
10-13
80-Pin Ceramic LCC (w/window)
10-32
44-Pin PLCC
10-14
80-Pin Plastic QFP (14 by 14 mm)
10-32
52-Pin Plastic QFP (1.8-mm leads)
10-15
80-Pin Plastic QFP (20 by 14 mm;
1.8-mm leads)
10-33
80-Pin Plastic QFP (20 by 14 mm;
2.35-mm leads)
10-34
84-Pin PLCC
10-35
94-Pin Ceramic LCC (w/window)
10-36
94-Pin Plastic QFP
10-37
52-Pin Plastic QFP (3$mm leads)
10-16
64-Pin Shrink CERDIP (w/350-mil
window)
10-17
64-Pin Shrink CERDIP (w/300-mil
window)
10-18
64-Pin Plastic Shrink DIP
10-19
viii
NEe
Contents
Numerical Index
Device, ~PD
Page
Device, ~PD
Page
71P301
7-113
7225
7227
7228
7228A
8-3
8-13
8-21
8-21
75028
75P036
75048
75P056
4-27
4-27
4-35
4-35
7502
7503
7507
7507H
3-3
3-3
3-19
3-39
75104
75104A
75106
4-43
4-43
4-43
7508
75CG08
7508H
75CG08HE
3-19
3-19
3-39
3-39
75108
75108A
75P108
75P108B
4-43
4-43
4-43
4-43
7527A
7528A
75CG28E
3-53
3-53
3-53
75112
75116
75P116
4-43
4-43
4-43
7533
75CG33E
7537A
7538A
75CG38E
3-65
3-65
3-85
3-85
3-85
75206
75208
75CG208
4-95
4-95
4-95
75212A
75216A
75CG216A
75P216
75P216A
4-95
4-95
4-95
4-95
4-95
7554
7554A
75P54
3-99
3-99
3-121
7556
7556A
75P56
75268
4-123
3-141
3-141
3-163
75304
75306
75308
75P308
4-135
4-135
4-135
4-135
7564
7564A
75P64
3-99
3-99
3-121
75312
75316
75P316
4-135
4-135
4-135
7566
7566A
75P66
3-141
3-141
3-163
75328
75P328
4-191
4-191
78C10
78C10A
78C11
78C11A
5-3
5-3
5-3
5-3
75004
75006
75008
75P008
4-3
4-3
4-3
4-3
ix
,-,'
NEe
Contents
Numerical Index (cont)
Device, ",0
78C12A
78C14
78C14A
78CG14
78CP14
78213
78214
781'214
78220
78224
78P224
x
Page
5-3
5-3
5-3
5-3
5-03
6-3
6-3
6-3
6-63
6-63
6-63
Device, "PO
78233
78234
78P238
78310A
78312A
78P312A
78320
78322
Page
6-119
6-119
6-119
7-3
7-3
7-3
7-61
7-61
t\'EC
Selection Guides
1-1
a
ttlEC
Selection Guides
Part Numbering System
Section 1
Selection Guides
Single-Chip Microcomputers
1-3
~PD75XX
1-7
Series Development Tools
~PD75XXX
~PD78XX
Series Development Tools
Series Development Tools
~PD782XX
Series Development Tools
~PD783XX
Series Development Tools
PG-1500 Programming Adapters
1-9
1-11
1-13
1-15
1-17
V-Series Microprocessors and Peripherals
1-19
Intelligent Peripheral Devices (IPD)
1-23
DSP and Speech Products
1-25
V-Series Development Tools
1-27
DSP and Speech Development Tools
1-31
1-2
~PD72001L
~P
D
72001
L
Typical microdevice part number
NEC monolithic silicon integrated circuit
Device type (D = digital MOS)
Device identifier (alphanumeric)
Package type (L = PLCC)
A part number may include an alphanumeric suffix that
identifies special device characteristics; for example,
~PD72001L-11 has an 11-MHz data clock rating.
NEe
Single-Chip
Microcomputers
4-Blt, Single-Chip CMOS Microcomputers
Device,
).lPD
Features
(MHz)
7502
7503
7507
LCD controller/driver
LCD controller/driver
General-purpose
0.41
0.41
0.41
7507H
General-purpose
7508
Clock
Supply
Voltage (V)
ROM
(X8)
RAM
(X4)
1/0
, ilackage
Pins
2.5 to 6.0
2.5 to 6.0
2.5 to 6.0
2K
4K
2K
128
224
128
23
23
32
4.19
2.7 to 6.0
2K
128
32
General-purpose
0.41
2.5 to 6.0
4K
224
32
7508H
General-purpose
4.19
2.7 to 6.0
4K
224
32
75CG08
75CG08H
7527A
Piggyback EPROM
Piggyback EPROM
FIP controller/driver
0.41
4.19
0.61
4.5 to 5.5
4.5 to 5.5
2.7 to 6.0
2K or 4K
2Kor 4K
2K
224
224
128
32
32
35
7528A
FIP controller/driver
0.61
2.7 to 6.0
4K
160
35
75CG28
Piggyback EPROM;
FIP controller/driver
AID converter
0.5
4.5 to 5.5
4K
160
35
QFP
QFP
DIP
SDIP
QFP
DIP
SDiP
QFP
DIP
SDiP
QFP
DIP
SDiP
QFP
Ceramic DIP
Ceramic DIP
DIP
SDiP
DIP
SDiP
Ceramic DIP
64
64
40
40
52
40
40
52
40
40
52
40
40
52
40
40
42
42
42
42
42
0.5
2.7 to 6.0
4K
160
30
0.5
4.5 to 5.5
4K
160
30
42
42
44
42
7537A
Piggyback EPROM;
AID converter
FIP controller/driver
DIP
SDiP
QFP
Ceramic DIP
0.61
2.7 to 6.0
2K
128
35
7538A
FIP controller/driver
0.61
2.7 to 6.0
4K
160
35
75CG38
0.61
4.5 to 5.5
4K
160
35
42
42
42
42
42
0.71
2.5 to 6.0
lK
64
16
0.71
2.0 to 6.0
lK
64
16
0.71
4.5 to 6.0
16
0.71
2.7 to 6.0
lK
OTPROM
lK
64
7564n564A
Piggyback EPROM;
FIP controller/driver
Serial 110; external clock
or RC oscillator
Serial 110; external clock
or RC oscillator
Serial I/O; external clock
or RC oscillator
Serial 110; ceramic oscillator
DIP
SDIP
DIP
SDiP
Ceramic DIP
64
15
75P64
Serial 110; ceramic oscillator
0.71
4.5 to 6.0
64
15
7556
0.71
2.5 to 6.0
64
20
0.71
2.0 to 6.0
lK
64
20
0.71
4.5 to 6.0
20
0.71
2.7 to 6.0
lK
OTPROM
lK
64
756617566A
Comparator; extemal
clock or RC oscillator
Comparator; external
clock or RC oscillator
Comparator; external
clock or RC oscillator
Comparator; ceramic oscillator
lK
OTPROM
lK
64
19
75P66
Comparator; ceramic oscillator
0.71
4.5 to 6.0
64
19
75004
General-purpose
4.19
2.7 to 6.0
lK
OTPROM
4K
512
34
SDIP
SOP
SDIP
SOP
SDIP
SOP
SDiP
SOP
SDIP
SOP
SDIP
SOP
SDIP
SOP
SDIP
SOP
SDIP
SOP
SDiP
SOP
SDIP
QFP
20
20
20
20
20
20
20
20
20
20
24
24
24
24
24
24
24
24
24
24
42
44
7533
75CG33
7554
7554A
75P54
7556A
75P56
a
# Plastic unless ceramic (or cerdip) is specified .
• Under development; consult Microcontroller Marketing for availability.
1-3
NEe
Single.Chip
4-Blt, Single-Chip CMOS Microcomputers (cant)
Device,
I1PD
75006
Features
Clock
(MHz)
Supply
Voltage (V)
General·purpose
4.19
75008
General·purpose
75POOS
ROM
RAM
(X8)
(X4)
UO
# Package
Pins
2.7 to 6.0
6K
512
34
4.19
2.7t06.0
8K
512
34
General·purpose
4.19
4.5 to 5.5
512
34
75028 •
AID converter
4.19
2.7 to 6.0
8K
OTPROM
8K
512
48
75P036 •
AID converter
4.19
2.7t06.0
16K
1024
48
75048 •
AID converter; 1Kx 4 EEPROM
4.19
2.7 to 6.0
8K
512
48
75P056 •
AID converter; 1Kx 4 EEPROM
4.19
2.7 to 6.0
16K
512
48
75104
High-ilnd with 8·bit instruction
4.19
2.7 to 6.0
4K
320
58
75104A
75106
High-ilnd with 8·bit instruction
High-end with 8·bit instruction
4.19
4.19
2.7 to 6.0
2.7 to 6.0
4K
6K
320
320
58
58
75108
High-engY!ith 8-bit instruction
4.19
2.7106.0
8K
512
58
7510SA
High-ilnd with 8·bit instruction
4.19
2.7 to 6.0
8K
512
58
75P1OS
Hlgh-ilnd with 8·bit instruction;
on-chip OTPROM or UVEPROM
4.19
4.5 to 5.5
8K
512
58
4.19
2.7 to 6.0
8K
512
58
75112
High-ilnd with 8·bit instruction;
on-chip OTPROM
. High-ilnd with 8·bit inslructicm
4.19
2.7 to 6.0
12K
512
58
75116
High-ilnd with 8·bit instruction
4.19
2.7 to 6.0
16K
512
58
75P116
4.19
4.5 to 5.5
58
4.19
2.7 to 6.0
16K
OTPROM
6K
512
75206
High-ilnd with 8·bit instruction
on-chipOTPROM
FIP controller/driver
369
33
75208
FIP controller/driver
4.19
2.7 to 6.0
8K
497
33
75CG208
4;19
4.5105.5
8K
512
33
75212A
FIP riontroller/driver;
piggyback EPROM
FIP controllerldriver
4.19
2.7 to 6.0
12K
512
33
75216A
FIP controller/driver
4.19
2.7 to 6.0
16K
512
33
75CG216A
4.19
4.5 to 5.5
16K
512
33
75P216A
FIP controller/driver;
piglllback EPROM
FIP cOntroller/driver
4.19
4.5 to 5.5
512
33
42
44
42
44
42
44
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
75268
F1P controller/driver
4.19
2.7 to 6.0
16K
OTPROM
8K
SDIP
OFP
SDIP
OFP
SDIP
OFP
SDIP
OFP
SDIP
OFP
SDIP
OFP
SDIP
OFP
SDIP
OFP
OFP
SDIP
OFP
SDIP
OFP
OFP
OFP
SDIP
OFP
Shrink cerdi~
SDIP
OFP
SDIP
OFP
SDIP
OFP
SDIP
OFP
SDIP
OFP
SDIP
OFP
Ceramic SDIP
Ceramic OFP
SDIP
OFP
SDIP
OFP
Ceramic SDIP
CeramicOFP
SDIP
512
32
75304
75306
75308
75P308
LCD controller/driver
LCD controller/driver
LCD controller/driver
LCD controller/driver;
on-chip OTPROM or UVEPROM
4.19
4.19
4.19
4.19
2.7 to 6.0
2.7 to 6.0
2.7to 6.0
4.75 to 5.25
4K
6K
8K
8K
512
512.
5j2
512
40
. 40
40
40
SDIP
OFP
OFP
OFP
OFP
OFP
Ceramic LCC
64
64
80
80
80
80
80
75P1OSB
1-4
NEe
Single-Chip
4-Blt, Single-Chip CMOS Microcomputers (cont)
Device,
J,lPD
ROM
RAM
(X4)
110
# Package
Pins
12K
16K
16K
OTPROM
16K
OTPROM
8K
512
512
512
40
40
40
QFP
QFP
QFP
80
80
80
512
40
512
44
QFP
Ceramic LCC
QFP
80
80
80
8K
OTPROM
2K
512
44
QFP
80
64
22
4.5 to 5.5
2K
OTPROM
64
22
2.7 to 6.0
2.7 to 6.0
4.75 to 5.5
12K
16K
16K
OTPROM
512
512
512
64
64
64
DIP
SDiP
QFP
DIP
SDIP
QFP
QFP
QFP
QFP
Ceramic LCC
28
28
44
28
28
44
80
80
80
80
(MHz)
Supply
Voltage (V)
4.19
4.19
4.19
2.7 to 6.0
2.7 to 6.0
4.75 to 5.25
4.19
2.7 to 6.0
4.19
2.7 to 6.0
4.19
4.5 to 5.5
75402A
LCD controller/driver
LCD controller/driver
LCD controller/driver;
on-chip OTPROM
LCD controller/driver;
on-chip OTPROM or UVEPROM
LCD controller/driver;
AID converter
LCD controller/driver;
AID converter
Low-end
4.19
2.7 to 6.0
75P402
Low-end
4.19
75512
75516
75P516
High-endj AID converter
High-endj AID converter
High-end; AID converter
4.19
4.19
4.19
75312
75316
75P316
75P316A *
75328
75P328
Clock
(X8)
Features
a
a-Bit, Single-Chip CMOS Microcomputers
ROM
RAM
(X8)
(X8)
110
# Package
Pins
4.5 to 5.5
Extemal
256
32
15
4.5 to 5.5
4K
256
44
CMOS; AID converter
15
4.5 to 5.5
8K
256
44
78C14nBC14A
CMOS; AID converter
15
4.5 to 5.5
16K
256
44
78CP14
CMOS; AID converter
15
4.75 to 5.25
16K
OTPROM
256
44
256
44
256
44
QUIP
SDiP
QFP
PLCC
QUIP
SDIP
QFP
PLCC
QUIP
SDIP
QFP
PLCC
QUIP
SDIP
OFP
PLCC
QUIP
SDIP
QFP
PLCC
Ceramic QUI P
Shrink cerdiE
Ceramic QUI P
64
64
64
68
64
64
64
68
64
64
64
68
64
64
64
68
64
64
64
68
64
64
64
512
54
512
54
SDiP
QUIP
QFP
PLCC
SDIP
QUIP
QFP
PLCC
64
64
74
68
64
64
74
68
Device,
J,lPD
Features
(MHz)
78C10n8C10A
CMOS; AID converter
15
78C11nBC11A
CMOS; AID converter
78Cl2A
78CG14
78213
78214
Clock
Supply
Voltage (V)
CMOS; AID converter;
piggyback EPROM
CMOS; AID converter;
advanced peripherals
15
4.5 to 5.5
12
4.5 to 5.5
16K
UVEPROM
4K,8Kor
16K
Extemal
CMOS; AID converter;
advanced peripherals
12
4.5 to 5.5
16K
1-5
NEC
Single-Chip
8-Bit, Single-Chip NMOS/CMOS Microcomputers (cont)
Device,
J.lPD
78P214
78220
78224
78P224
78233
78234
Clock
Fe"ture$
(MHz)
CMOS; AID converter;
advanced peripherals
12
Supply
Voltsge(V)
4,5 to 5.5
ROM
RAM
(X8)
(X8)
110
# Packsg",
Pins
16K
OTPROM
512
54
512
54
SOIP
OUIP
OFP
PLCC
Shrink cerdip
64
64
74
68
64
640
71
84
94
84
94
84
94
80
94
84
80
94
84
80
94
84
94
CMOS; analog comparator;
large I/O
CMOS; analog comparator;
large I/O
CMOS; analog comparator;
large I/O
CMO,S; real-time outputs;
AID and O/A converters
12
4.5 to 5.5
16K
UVEPROM
External
12
4.5 to 5.5
16K
640
71
12
4.5 to 5.5
640
71
12
4.5 to 5.5
16K
OTPROM
Extemal
640
64
CMOS; real-time outputs;
12
4.5 to 5.5
16K
640
64
12
4.5 to 5.5
32K
OTPROM
640
64
32K
UVEPROM
640
64
PLCC
OFP
PLCC
OFP
PLCC
OFP
OFP
OFP
PLCC
OFP
OFP
PLCC
OFP
OFP
PLCC
Ceramic LCC
AID and O/A converters
78P238
CMOS; real-time outputs;
AID and O/A converters
8/16-Blt, Single-Chip CMOS Microcomputers
ROM
RAM
(X8)
(X8)
I/O
# Package
Pins
4.5 to 5,5
External
256
48
12
4.5 to 5.5
8K
256
48
12
4.5 to 5.5
8K
UVEPROM
8K
OTPROM
256
48
256
48
SOIP
OUIP
OFP
PLCC
SOIP
OUIP
OFP
PLCC
Shrink cerdip
Ceramic OUIP
SOIP
OUIP
OFP
PLCC
OFP
PLCC
OFP
PLCC
PLCC
OFP
Ceramic LCC
Ceramic LCC
PLCC
OFP
OUIP
Ceramic LCC
Ceramic LCC
Ceramic OUI P
64
64
64
68
64
64
64
68
64
64
64
64
64
68
64
68
64
68
68
74
68
74
44
64
64
44
64
64
Device,
J.lPD
Featurea
(MHz)
78310A
Real-time motor control
12
78312A
Real-time motor control
78P312A
Real-time motor control
78320
78322
78P322
71P301
1-6
Clock
High-end; advanced analog
and digital peripherals
High-end; advanced analog
and digital ~eri~herals
High-end; advanced analog
and digital peripherals
Port and memory extender
used with 7832X microcomputer
family; UVEPROM or OTPROM
Supply
Voltage (V)
16
4.5 to 5.5
External
640
55
16
4,5 to 5.5
16K
640
55
16
4.5 to 5;5
16K
OTPROM
16K
UVEPROM
16K
OTPROM
640
55
640
55
1K
16
16K
UVEPROM
1K
16
4.5 to 5.5
NEe
jlPD75XX Series
Development Tools
/lPD75XX Series Development Tools Selection Guide
Part Number
(Note 1)
Emulator'
f1I'D7502G·12
f1I'D7503G-12
f1I'D7507C
f1I'D7507CU
f1I'D7507G-OO
f1I'D7507HC
f1I'D7507HCU
f1I'D7507HG-22
f1I'D7508C
f1I'D7508CU
f1I'D7508G-OO
f1I'D75CG08E
f1I'D7508HC
f1I'D7508HCU
f1I'D7508HG-22
f1I'D75CG08HE
f1I'D7527AC
f1I'D7527ACU
f1I'D7528AC
f1I'D7528ACU
f1I'D75CG28E
f1I'D7533C
f1I'D7533CU
f1I'D7533G-22
f1I'D75CG33E
f1I'D7537AC
f1I'D7537ACU
f1I'D7538AC
!1!'D7538ACU
f1I'D75CG38E
f1I'D7554CS
f1I'D7554G
f1I'D7554ACS
f1I'D7554AG
f1I'D75P54CS
f1I'D75P54G
f1I'D7556CS
f1I'D7556G
f1I'D7556ACS
f1I'D7556AG
f1I'D75P56CS
f1I'D75P56G
f1I'D7564CS
f1I'D7564G
f1I'D7564ACS
IlPD7564AG
f1I'D75P64CS
f1I'D75P64G
f1I'D7566CS
f1I'D7566G
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
Add·on
Board'
System
Evaluation
Board
EV7514
EV7514
SE-7514A
SE-7514A
EPROM/OTP
Device
PG·1500
Adapter
(Note 2)
f1I'D78CG08E
EV7508H
EV7508H
EV7508H
f1I'D75CG08HE
f1I'D78CG08E
EV7508H
EV7508H
EV7508H
EV7508H
EV7528
EV7528
EV7528
EV7528
EV7528
EV7533
EV7533
EV7533
EV7533
EV7528
EV7528
EV7528
EV7528
EV7528
EV7554A
EV7554A
EV7554A
EV7554A
EV7554A
EV7554A
EV7554A
EV7554A
EV7554A
EV7554A
EV7554A
EV7554A
EV7554A
EV7554A
EV7554A
EV7554A
EV7554A
EV7554A
EV7554A
EV7554A
f1I'D78CG08HE
f1I'D78CG28E
f1I'D78CG28E
f1I'D75CG33E
f1I'D75CG38E
f1I'D75CG38E
SE-7554A
SE-7554A
SE-7554A
SE-7554A
f1I'D75P54CS
f1I'D75P54G
f1I'D75P54CS
f1I'D75P54G
PA-75P54CS
PA-75P54CS
PA-75P54CS
PA-75P54CS
SE-7554A
SE-7554A
SE-7554A
SE-7554A
f1I'D75P56CS
f1I'D75P56G
f1I'D75P56CS
f1I'D75P56G
PA-75P56CS
PA-75P56CS
PA-75P56CS
PA-75P56CS
SE-7554A
SE-7554A
SE-7554A
SE-7554A
f1I'D75P64CS
f1I'D75P64G
f1I'D75P64CS
f1I'D75P64G
PA-75P54CS
PA-75P54CS
PA-75P54CS
PA-75P54CS
SE-7554A
SE-7554A
f1I'D75P66CS
f1I'D75P66G
PA-75P56CS
PA-75P56CS
Absolute
Assembler
(Note 3)
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
a
• Required Tools
1-7
NEe
J.1PD75XX Series
JlPD75XX Series Development Tools Selection Guide (cont)
Part Number
(Note 1)
~D7566ACS
¢lD7566AG
~D75P66CS
¢lD75P66G
Emulator*
Add-on
Board'
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EVAKIT-7500B
EV7554A
EV7554A
EV7554A
EV7554A
System.
Evaluation
Board
SE-7554A
SE-7554A
• Required Tools
Notes:
(1) Packages:
Package Description
C
CS
CU
E
G
G'-OO
G-12
G-22
40-pin plastic DIP (jLPD7507/07H108IOSH)
42-pin plastic DIP (IlPD7527A128A133137A138A)
20-pin plastic shrink DIP (IlPD7554154A1P54164164A1P64)
24-pin plastic shrink DIP (IlPD7556156A1P56/66166A/P66)
4O-pin plastic shrink DIP (IlPD7507/07HI08IOSH)
42-pin plastic shrink DIP (IlPD7527A12SAI33/37A138A)
40-pin ceramic piggy-back DIP (IlPD75CG08l0SH)
42-pin ceramic piggy-back DIP (!1PD75CG2813313S)
2O-pin plastic SO (IlPD7554154A1P54/64/64A1P64)
24-pin plastic SO (IlPD7556156A1P56166/66A/P66)
52-pin plastic OFP
64-pin plastic OFP (jLPD7502I03)
44-pin plastic OFP
(2) By using the specified adapter, the PG-1500 EPROM programmer
can be used to program the OTP device.
(3) The ASM75 Absolute Assembler is provided Ie run under the MS-DOS·
operating system. (ASM75-D52).
MS-DOS is a registered trademark of Microsoft Corporation.
1-8
EPROM/OTP
Device
~D75P66CS
~D75P66G
PG-1500
Adapter
(Note 2)
Absolute
A.sembler
(Note 3)
PA-75P56CS
PA-75P56CS
ASM75
ASM75
ASM75
ASM75
NEe
j.lPD75XXX Series
Development Tools
!!PD75XXX Series Development Tools Selection Guide
Part Number
(Note 5)
~D75004CU
~D75006GB-3B4
~D75006CU
~D75006GB-3B4
~D75008CU
~D75008GB-3B4
~D75POO8CU
jJl'D75POO8GB-384
~D7502SCW
jJl'D7502SGC-A8S
jJl'D75P036CW
~D75P036GC-A8S
jJl'D7504SCW
~D7504SGC-A8S
~D75P056CW
~D75P056GC-ABS
jJl'D75104CW
Emulator"
Emulation
Probe"
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
EP-75008CU-R
EP-75008GB-R
EP-75008CU-R
EP-75008GB-R
EP-75008CU-R
EP-75008GB-R
EP-75008CU-R
EP-75008G8-R
EP-7502SCW-R
EP-7502SGC-R
EP-7502SGW-R
EP-75028GC-R
EP-7502SCW-R
EP-7502SGC-R
EP-7502SCW-R
EP-7502SGC-R
EP-75108CW-R
Optional Socket
Adapter (Note 1)
EPROM/OTP
Device (Note 2)
~D75POO8CU
EV-9200G-44
~D75POO8GB
~D75POO8CU
EV-9200G-44
~D75POO8GB
~D75POO8CU
EV-9200G-44
jJl'D75POO8GB
EV-9200G-44
jJl'D75P036CW
EV-9200GC'64
~D75P036GC
EV-9200GC-64
~D75P056CW
EV-9200GC-64
~D75P056GC
EV-9200GC-64
jJl'D75P108CW/DW
Relocatable
Assembler
(Note 3)
Structured
Assembler
(Note 4)
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X .
ST75X
RA75X
ST75X
RA75X
ST75X
RA75X
RA75X
ST75X
ST75X
RA75X
ST75X
RA75X
ST75X
RA75X
RA75X
RA75X
ST75X
ST75X
ST75X
RA75X
ST75X
RA75X
ST75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
a
~D75P116CW
~D75104G-1B
IE-75000-R
EP-7510SGF-R
EV-9200G-64
jJl'D75P10SG/GF
~D75P116GF
jJl'D75104GF-3BE
IE-75000-R
EP-75108GF-R
EV-9200G'64
~D75P108G/GF
jJl'D75P116GF
jJl'D75104AGC-AB8
IE-75000-R
IE-75000-R
EP-7510SAGC-R
EP-75108CW-R
EV-9200GC-64
~D75106CW
~D75106G-1B
IE-75000-R
EP-7510SGF-R
EV-9200G-64
jJl'D75P108CW/DW
~D75P116CW
jJl'D75P108G/GF
~D75P116GF
jJl'D75106GF-38E
IE-75000-R
EP-75108GF-R
EV-9200G-64
~D75P108G/GF
jJl'D75P116GF
~D751 08AG-22
EP-75108AGC-R
EP-75108AGC-R
EP-75108CW-R
EV-9200GC'64
EV-9200GC-64
jJl'D75108CW
IE-75000-R
IE-75000-R
IE-75000-R
~D75108G-1B
IE-75000-R
EP-75108GF-R
EV-9200G-64
~D75108AGC-A88
jJl'D75P108CW/DW
jJl'D75P116CW
jJl'D75P108G/GF
~D75P116GF
jJl'D75108GF-3BE
IE-75000-R
EP-7510SGF-R
~D75P108BCW
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-7500thR
IE-75000-R
IE-75000-R
IE-75000-R .
IE-75000-R
IE-75000'R
IE-75000-R
IE-75000-R
EP-75108CW-R
EP-75108GF-R
EP-7510SCW-R
EP-75108CW-R
EP-75108GF-R
EP-75108CW-R
EP-75108GF-R
EP-75108CW-R
EP-75108GF-R
EP-75108CW-R
EP-75108GF-R
EP-75216ACW-R
EP-75216AGF-R
EP-75216AGF-R
EP-75216ACW-R
~D75P108BGF-3BE
~D75P108CW
~D75P108DW
~D75P108G-1B
~D75112CW
~D75112GF-38E
~D75116CW
~D75116GF-38E
~D75P116CW
~D75P116GF-38E
~D75206CW
~D75206G-18
~D75206BGF-3BE
jJl'D75208CW
EV-9200G-64
jJl'D75P108G/GF
jJl'D75P116GF
EV-9200G-64
EV-9200G-64
~D75P116CW
EV-9200G-64
~D75P116GF
~D75P116CW
EV-9200G-64
~D75P116GF
EV-9200G-64
~D75P216ACW
EV-9200G-64
EV-9200G-64
~D75P216ACW
* Required Tools
1-9
NEe
/lPD75XXX Series
llPD75XXX Series Development Tools Selection Guide (cont)
Part Number
(NoteS)
flPD75208G-IB
flPD75208GF-38E
flPD75CG208E
flPD75CG208EA
flPD75212ACW
flPD75212AGF-3BE
flPD75216ACW
flPD75216AGF
flPD75CG216AE
flPD75CG216AEA
flPD75P216ACW
flPD75268CW
flPD75268GF-38E
flPD75304GF-389
flPD75306GF-389
flPD75308GF-389
flPD75P308GF-389
flPD75P308K
flPD75312GF-3B9
flPD75316GF-389
flPD75P316GF-3B9
flPD75P316AGF-389
flPD75P316AK
flPD75328GC-389
flPD75P328GC-389
flPD75402AC
flPD75402ACT
flPD75402AG8-384
flPD75P402C
flPD75P402CT
flPD75P402GB-3B4
flPD75512GF-389
flPD75516GF-389
flPD75P516GF-3B9
flPD75P516K
Emulator'
Emulation
Probe'
Optional Socket
Adapter (Note 1)
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R
IE-75000-R .
IE-75000-R
IE-75000-R
IE-75000-R
EP-75216AGF-R
EP-75216AGF-R
EP-75216ACW-R
EP-75216AGF-R
EP-75216ACW-R
EP-75216AGF-R
EP-75216ACW-R
EP-75216AGF-R
EP-75216ACW-R
EP-75216AGF-R
EP-75216ACW-R
EP-75216ACW-R
EP-75216AGF-R
EP-75308GF-R
EP-75308GF-R
EP-75308GF-R
EP-75308GF-R
EP-75308GF-R
EP-75308GF-R
EP-75308GF-R
EP-75308GF-R
EP-75308GF-R
EP-75308GF-R
EP-75328GC-R
EP-75328GC-R
EP-75402C-R
EP-75402C-R
EP-75402G8-R
EP-75402C-R
EP-75402C-R
EP-75402G8-R
EP-75516GF-R
EP-75516GF-R
EP-75516GF-R
EP-75516GF-R
EV-9200G-64
EV-9200G-64
EV-9200G-64
flPD75P216ACW
EV-9200G-64
flPD75P216ACW
EV-9200G-64
EV-9200G-64
flPD75P216ACW
flPD75P216ACW
EV-9200G-64
EV-9200G-80
EV-9200G-80
EV-9200G-80
EV-9200G-80
EV-9200G-80
EV-9200G-80
EV-9200G-80
EV-9200G-80
EV-9200G-80
EV-9200G-80
EV-9200GC-80
EV-9200GC-80
flPD75P316GF
flPD75P316GF
flPD75P328GC
flPD75P402C
flPD75P402CT
flPD75P402GB
EV-9200G-44
EV-9200G-80
EV-9200G-80
EV-9200G-80
EV-9200G-80
(1) The EV-9200G-XX is an LCC socket with the footprint of the flat
package. One unit is supplied with the probe. Additional units are
available as replacement parts in sets of five.
(2) All EPROMlOTP devices can be programmed using the NEC PG1500. Refer to the PG-1500 Programming Socket Adapter
Selection Guide for the appropriate socket adapter.
(4) The ST75X structures assembler preprocessor is provided with
RA75X.
flPD75P308GF/K
flPD75P308GF/K
flPD75P308GF/K
EV-9200G-44
Notes:
(3) The RA75X relocatable assembler package is provided for the
following operating systems:
RA75X-D52 (MS-DOS·)
RA7SX-VVTl (VAXNMS·)
EPROM/OTP
Device (Note 2)
flPD75P516GF/K
flPD75P516GF/K
1-10
Structured
Assembler
(Note 4)
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
RA75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
ST75X
(5) Packages:
Package Description
C
CT
CU
CW
DW
E
EA
G-IB
G-22
GB-3B4
GC-ABB
GC-389
GF-3BE
GF-389
K
MS-DOS is a registered trademark of Microsoft Corporation.
Relocatable
Assembler
(Note 3)
2S-pin plastic DIP
2S-pin plastic shrink DIP
42-pin plastic shrink DIP
64-pin plastic shrink DIP
64-pin ceramic shrink DIP with window
64-pin ceramic piggy-back shrink DIP
64-pin ceramic piggy-back OFP
64-pin plastic OFP (2.05 mm thick)
64-pin plastic OFP (1.55 mm thick)
44-pin plastic OFP
64-pin plastic OFP (2.55 mm thick)
SO-pin plastic OFP
64-pin plastic OFP (2.77 mm thick)
SO-pin plastic OFP
SO-pin ceramic LCC
VAX and VMS are registered trademarks of Digital Equipment Corporation.
NEe
JlPD78XX Series
Development Tools
J.l.PD78XX Series Development Tools Selection Guide··
Part Number
(Note 1)
fll'D78Cl0CW
~D78Cl0G-36
~D78Cl0G-1B
~D78Cl0GF-3BE
~D78Cl0L
fll'D78Cl0ACW
!iPD78Cl0AGQ-36
!iPD78Cl0AGF-3BE
!iPD78Cl0AL
!iPD78CllCW
fll'D78Cll G-36
Emulator"
IE-78Cll-M
IE-78Cll-M
IE-78Cll-M
IE-78Cll-M
IE-78Cll-M
IE-78Cll-M
(Note 8)
IE-78Cll-M
(Note 8)
IE-78Cll-M
(Note 8)
IE-78Cll-M
(Note 8)
IE-78Cl1-M
IE,78Cl1-M
Relocatable
Assembler
(Note 9)
CCompller
(Note 9)
RA87
CC87
EV-9001-64
RA87
RA87
RA87
RA87
RA87
CC87
CC87
CC87
CC87
CC87
(Note 3)
(Note 4)
RA87
CC87
(Note 5)
RA87
CC87.
(Note 5)
RA87 .
CC87
Emulation
Probe"
EV-9001-64
(Note 3)
(Note 4)
EPROM/OTP
Device
PG-1500
Adapter
(Note 2)
(Note 5)
(Note 5)
(Note 5)
EV-9001-64
(Note 3)
(Note 4)
.. . !iPD78CP14CWIDW
PA-78CPI4CW
RA87
Ces7
fll'D78CPI4G-361R
PA-78CP14GQ
RA87
CC87
PA-78CPI4GF
PA-78CPI4GF
PA-78CPI4L
PA-78CPI4CW
RA87
RA87
RA87
RA87
CC87·
CC87
CC87
CC87
PA-78CPI4GQ
RA87
CC87
PA-78CPI4GF
RA'87
Cea7
PA-78CPI4L
RA87
CC87
PA-78CPI4CW
RA87
CC87
PA-78CP14GQ
RA87
CC87
PA-78CP14GF
RA87
CC87
PA-78CP14L
RA87
CC87
PA-78CPI4CW
RA87
CC87
PA-78CPI4GQ
RA87
CC87
PA-78CPI4GF
PA-78CPI4GF
PA-78CPI4L
RA87
RA87
RA87
RA87
CC87
CC87
CC87
CC87
RA87
CC87
PA-78CPI4CW
RA87
CC87
PA-78CP14CW
RA87
CC8t
II
~D78CPI4E
~D78CllG-1B
~D78Cl1 GF-3BE
~D78Cl1l
fll'D78Cl1ACW
fll'D78CllAGQ-36
fll'D78Cl1AGF-3BE
.IE-78Cl1-M
IE-78Cll-M
IE-78Cll-M
IE-78Cl1-M
(Note 7)
IE-78Cl1-M
(Note 7)
IE-78Cll-M
(Note 5)
(Note 5)
!Note 5)
~D78CPI4GF-3BE
EV-9001-64
(Note 3)
(Note 4)
fll'D78CI2ACW
fll'D78Cl2AGQ-36
IE-78Cl1-M
EV-9001-64
IE-78Cll-M
(Note 3)
(Note 4)
fll'D78CPI4G-361R
n
IE-78Cll-M
(Note n
(Note 5)
(Note 5)
IE-78Cl1-M
EV-9001-64
(Note 7)
(Note 3)
(Note 4)
IE-78Cll-M
(Note 7)
!iPD78CI2AGF-3BE
IE-78Cl1-M
(Note 5)
(Note 7)
fll'D78CI2AL
IE-78Cll-M
(Note 5)
(Note 7)
fll'D78C14CW
!iPD78C14G-36
~D78CPI4L
!iPD78CPI4CWIDW
(Note 6)
fll'D78CPI4G-361R
(Note 6)
!iPD78CPI4GF-3BE
(Note 6)
fll'D78CPI4L
(Note 6)
fll'D78CPI4CWIDW
(Note 6)
fll'D78CPI4G-361R
(Note 6)
fll'D78CPI4GF-3BE
(Note 6)
fll'D78CPI4L
(Note 6)
fll'D78CPI4CW/DW
(Note
fll'D78CllAL
~D78CPI4GF-3BE
~D78CG14E
~D78C14G-IB
~D78CI4GF-3BE
~D78C14L
fll'D78C14AG-ABS
fll'D78CGI4E
IE-78Cll-M
IE-78Cll-M
IE-78Cll-M
IE-78Cll-M
(Note 7)
IE-78Cl1-M
(Note 5)
(Note 5)
(Note 5)
(Note 5)
~D78CPI4GF
~D78CPI4GF
~D78CPI4L
(Note 4)
(Note 8)
fll'D78CPI4CW
IE-78Cl1-M
EV-9001-64
(Note 3)
fll'D78CP14DW
IE-78Cl1-M
EV-9001-64
(Note 3)
" Required Tools
"For all jlPD78C1X devices. you may use the DDK-78Cl0 for evaluation purposes.
..
;
1-11
NEe
IlPD78XX Series
j.tPD78XX Series Development Tools Selection Gulde** (cont)
Part Number
(Note 1)
Emulator'
Emulation
Probe'
J.lPD78GP14G-36
J.lPD78GPI4GF-3BE
J.lPD78GP14L
J.lPD78GP14R
IE-78Gll-M
IE-78Gl1-M
IE-78Gll-M
IE-78Gll-M
(Note 4)
(Note 5)
(Note 5)
(Note 4)
EPROM/OTP
Device
PG-1S00
Adapter
(Note 2)
Relocatable
Assembler
(Note 9)
CCompller
(Note 9)
PA-78GPI4GO
PA-78GPI4GF
PA-78GPI4L
PA-78GPI4GO
RA87
RA87
RA87
RA87
GG87
GG87
GG87
GG87
• Required Tools
"For all J,lPD78C1X devices, you may use the DDK-78Cl0 for evaluation purposes.
Notes:
(1) Packages:
Package
CW
DW
E
G-IB
G-36
G-AB8
GF-3BE
GQ-36
L
R
Description
64-pin plastic shrink DIP
64-pin ceramic shrink DIP with window
64-pin ceramic piggy-back QUIP
64-pin plastic QFP (Resin Thickness: 2.05 mm)
64-pin plastic QUIP
64-pin plastic QFP (Interpin Pitch: 0.8 mm)
64-pin plastic QFP (Resin Thickness: 2.7 mm)
64-pin plastic QUIP
68-pin PLCC
64-pin ceramic QUIP with window
(2) By using the specified adapter, the PG-1S00 EPROM programmer
can be used to program the EPROMlOTP device.
(3) 64-pin shrink DIP adapter which plugs into the EP-7811 HGQ
emulation probe supplied with each IE.
(4) The emulation probe for the 64-pin QUIP package (EP-7811 HGQ)
is supplied with the IE.
(S) No emulation probe available.
(6) The J,lPD78CPI4 EPROM/OTP devices do not have pull-up
resistors on ports A, B, and C.
(7) The IE-78Cll-M can be used by replacing the J,lPD78Cl0G-36
with a J,lPD78C 1OAGQ-36. However, it will not be able to emulate
the optional pull-up resistors on ports A, B, and C.
(8) The J,lPD78CGI4E is a piggy-back EPROM device in a ceramic
QUIP package. It accepts 27C256 and 27C2S6A EPROMS.
(9) The following relocatable assemblers and C compilers are
available:
RA87-DS2
RA87-VVTl
(MS-Dose)
(VAXNMS8)
Relocatable assemblers
for 78XX series
CCMSD-ISDD-87
CCVM5-0TI6-87
CCUNX-OTI6-87
(MS-DOS)
(VAXNMS)
(VAXlUNIX8j
4.2 BSD or Ultrixe)
C Compilers for
78XX Series
MS-DOS is a registered trademark of Microsoft Corporation.
VAX, VMS and Ultrix are registered trademarks of Digital Equipment Corporation.
UNIX is a trademark of AT&T Bell Laboratories.
1-12
NEe
IlPD782XX Series
Development Tool.s
IlPD782XX Series Development Tools Selection Guide (Note 1)
Part Number
(Note 2)
Evaluation
Kit (Note 3
Designer Kit
(Note 4)
Emulator Kit
(Note 5)
Low-End
Emulator
Emulation
System
Emulation
Probe
~D78213CW
EK-78K2-21X
EK-78K2-21X
EK-78K2-21X
EK-78K2-21X
EK-78K2-21X
EK-78K2-21X
EK-78K2-21X
EK-78K2-21X
EK-78K2-21X
EK-78K2-21X
EK-78K2-21X
EK-78K2-21X
EK-78K2-21X
EK-78K2-22X
EK-78K2-22X
EK-78K2-22X
EK-78K2-22X
EK-78K2-22X
EK-78K2-22X
EK-78K2-23X
EK-78K2-23X
EK-78K2-23X
EK-78K2-23X
EK-78K2-23X
EK-78K2-23X
EK-78K2-23X
EK-78K2-23X
EK-78K2-23X
EK-78K2-23X
DK-78K2-21XCW
DK-78K2-21XGJ
DK-78K2-21XGQ
DK-78K2-21XL
DK-78K2-21XCW
DK-78K2-21XGJ
DK-78K2-21XGQ
DK-78K2-21XL
DK-78K2-21XCW
DK-78K2-21XCW
DK-78K2-21XGJ
DK-78K2-21XGQ
DK-78K2-21 XL
DK-78K2-22XGJ
DK-78K2-22XL
DK-78K2-22XGJ
DK-78K2-22XL
DK-78K2-22XGJ
DK-78K2-22XL
DK-78K2-23XGC
DK-78K2-23XGJ
DK-78K2-23XL
DK-78K2-23XGC
DK-78K2-23XGJ
DK-78K2-23XL
DK-78K2-23XGC
DK-78K2-23XGJ
DK-78K2-23XGJ
DK-78K2-23XL
IK-78K2-21XCW
IK-78K2-21XGJ
IK-78K2-21XGQ
IK-78K2-21XL
IK-78K2-21XCW
IK-78K2-21XGJ
IK-78K2-21XGQ
IK-78K2-21 XL
IK-78K2-21XCW
IK-78K2-21 XCW
IK-78K2-21XGJ
IK-78K2-21XGQ
IK-78K2-21XL
IK-78K2-22XGJ
IK-78K2-22XL
IK-78K2-22XGJ
IK-78K2-22XL
IK-78K2-22XGJ
IK-78K2-22XL
IK-78K2-23XGC
IK-78K2-23XGJ
IK-78K2-23XL
IK-78K2-23XGC
IK-78K2-23XGJ
IK-78K2-23XL
IK-78K2-23XGC
IK-78K2-23XGJ
IK-78K2-23XGJ
IK-78K2-23XL
EB-78210-PC
EB-78210-PC
EB-78210-PC
EB-78210-PC
EB-78210-PC
EB-78210-PC
EB-78210-PC
EB-78210-PC
EB-78210-PC
EB-78210-PC
EB-78210-PC
EB-78210-PC
EB-78210-PC
EB-78220-PC
EB-78220-PC
EB-78220-PC
EB-78220-PC
EB-78220-PC
EB-78220-PC
EB-78230-PC
EB-78230-PC
EB-78230-PC
EB-78230-PC
EB-78230-PC
EB-78230-PC
EB-78230-PC
EB-78230-PC
EB-78230-PC
EB-78230-PC
IE-78210-R
IE-78210-R
IE-78210-R
IE-78210-R
IE-78210-R
IE-78210-R
IE-78210-R
IE-78210-R
IE-78210-R
IE-78210-R
IE-78210-R
IE-78210-R
IE-78210-R
IE-78220-R
IE-78220-R
IE-78220-R
IE-78220-R
IE-78220-R
IE-78220-R
IE-78230-R
IE-78230-R
IE-78230-R
IE-78230-R
IE-78230-R
IE-78230-R
IE-78230-R
IE-78230-R
IE-78230-R
IE-78230-R
EP-78210CW-R
EP-78210GJ-R (7)
EP-78210GQ-R
EP-78210L-R
EP-78210CW-R
EP-78210GJ-R (7)
EP-78210GQ-R
EP-78210L-R
EP-78210CW-R
EP-78210CW-R
EP-78210GJ-R (7)
EP-78210GQ-R
EP-78210L-R
EP-78220GJ-R (8)
EP-78220L-R
EP-78220GJ-R (8)
EP-78220L-R
EP-78220GJ-R (8)
EP-78220L-R
EP-78230GC-R
EP-78230GJ-R
EP-78230LQ-R
EP-78230GC-R
EP-78230GJ-R
EP-78230LQ-R
EP-78230GC-R
EP-78230GJ-R
EP-78230GJ-R
EP-78230LQ-R
~D78213GJ-SBJ
jlI'D78213GQ-36
jlPD78213L
~D78214CW
jlPD78214GJ-SBJ
jlI'D78214GQ-36
~D78214L
jlI'D78P214CW
jlPD78P214DW
~D78P214GJ-SBJ
~D78P214GQ-36
~D78P214L
jlPD78220GJ-SBG
jlPD78220L
jlI'D78224GJ-SBG
jlI'D78224L
jlI'D78P224GJ-SBG
jlI'D78P224L
~D78233GC-3B9
jlPD78233GJ-SBG
jlI'D78233LQ
jlPD78234GC-3B9
jlPD78234GJ-5BG
~D78234LQ
jlPD78P238GC-3B9
~D78P238GJ-5BG
~D78P238KF
jlPD78P238LQ
Device
(Note 6)
~D78P214CW/DW
~D78P214GJ
jlI'D78P214GQ
~D78P214L
~D78P224GJ
jlPD78P224L
~D78P238GC
jlPD78P238GJ/KF
jlI'D78P238LQ
Notes:
1. The following software packages are available for the J.1PD782XX
Series:
RA78K2 relocatable assembler package
RA78K2-DS2 (MS-DOS~)
RA78K2-VVTl (VAX~NMS~)
ST78K2 Structured assembler preprocessor
Provided with RA 78K2
CC782XX C Compiler package
CCMSD-ISDD-782XX (MS-DOS~)
(2) Packages:
Package
Description
CW
DW
GC-3B9
GJ-SBG
GJ-SBJ
GQ-36
KF
L
64-pin plastic shrink DIP
64-pin ceramic shrink DIP with window
80-pin plastic QFP
94-pin plastic QFP
74-pin plastic QFP
64-pin plastic QUIP
94-pin ceramic LCC with window
68-pin PLCC (J.1PD78213/214/P214L)
84-pin PLCC (J.1PD78220/224/P224L)
84-pin PLCC
LQ
MS-DOS is a registered trademark of Microsoft Corporation.
(3) The J.1PD782XX Evaluation Kit contains the appropriate DDB-78K22XX evaluation board for the part selected, the RA 78K2 Relocatable Assembler Package, and the ST78K2 Structured Assembler
Preprocessor.
(4) The J.1PD782XX Designer Kit contains the appropriate EB-782XXPC low-end emulator and emulation probe for the part selected, the
RA78K2 Relocatable Assembler Package, and the ST78K2
Structured Assembler Preprocessor.
(S) The J.1PD782XX Emulator Kit contains the appropriate IE-782XX
system and emulation probe for the part selected, the RA78K2
Relocatable Assembler Package, and the ST78K2 Structured
Assembler Preprocessor.
(6) All EPROMlOTP devices can be programmed using the NEC PGIS00. Refer to the PG-1500 Programming Socket Adapter
Selection Guide for the appropriate programming adapter.
(7) The EP-78210GJ-R emulation probe is shipped with one EV9200G-74, a 74-pin LCC socket with the footprint of the QFP
package. Additional sockets are available as replacement parts in
sets of five.
(8) The EP-78220GJ-R emulation probe is shipped with one EV9200G-94, a 94-pin Lee socket with the footprint of the QFP
package. Additional sockets are available as replacement parts in
sets of five.
VAX and VMS are registered trademarks of Digital Equipment Corporation.
1-13
II
JlPD782XX Series
1-14
NEe
NEe
~PD783XX Series
Development Tools
IlPD783XX Series Development Tools Selection Guide (Note 10)
Relocatable
Assembler
(Note11)
Structured
Assembler
(Note 12)
(Note 3)
RA78K3
ST78K3
RA78K3
ST78K3
IE-78310A-R
EP-78310GF
(Note 6)
(Note 4)
RA78K3
ST78K3
fll'D78310AL
IE-78310A-R
EP-78310L
RA78K3
ST78K3
fll'D78312ACW
IE-78310A-R
(Note 3)
fll'D78P312ACW/DW
PA-78P312CW
RA78K3
ST78K3
fll'D78312AGF-3BE
IE-78310A-R
fll'D78P312AGF-3BE
PA-78P312GF
RA78K3
ST78K3
fll'D78312AGO-36
IE-78310A-R
EP-78310GF
(Note 6)
(Note 4)
fll'D78P312AGQ/RO
PA-78P312GO
RA78K3
ST78K3
fll'D78312AL
IE-78310A-R
EP-78310L
fll'D78P312AL
PA-78P312L
RA78K3
ST78K3
fll'D78P312ACW
IE-78310A-R
(Note 3)
PA-78P312CW
RA78K3
ST78K3
fll'D78P312ADW
IE-78310A-R
(Note 3)
PA-78P312CW
RA78K3
ST78K3
fll'D78P312AGF-3BE
IE-78310A-R
PA-78P312GF
RA78K3
ST78K3
fll'D78P312AGO-36
IE-78310A-R
EP-78310GF
(Note 6)
(Note 4)
PA-78P312GO
RA78K3
ST78K3
fll'D78P312AL
IE-78310A-R
EP-78310L
PA-78P312L
RA78K3
ST78K3
fll'D78P312AR
IE-78310A-R
(Note 4)
PA-78P312GO
RA78K3
ST78K3
fll'D78320GJ-5BJ
IE-78320-R
RA78K3
ST78K3
fll'D78320L
IE-78320-R
EP-78320GJ-R
(Note 7)
EP-78320L-R
CC7831X
(Note 5)
CC7831X
(Note 5)
CC7831X
(Note 5)
CC7831X
(Note 5)
CC7831X
(Note 5)
CC7831X
(Note 5)
CC7831X
(Note 5)
CC7831X
(Note 5)
CC7831X
(Note 5)
CC7831X
(Note 5)
CC7831X
(Note 5)
CC7831X
(Note 5)
CC7831X
(Note 5)
CC7831X
(Note 5)
CC7832X
RA78K3
ST78K3
CC7832X
fll'D78322GJ-SBJ
IE-78320-R
RA78K3
ST78K3
CC7832X
fll'D78322L
IE-78320-R
RA78K3
ST78K3
CC7832X
fll'D78P322GJ
IE-78320-R
PA-78P322GJ
PA-78P322KD
PA-78P322L
PA-78P322KC
PA-78P322GJ
RA78K3
ST78K3
CC7832X
fll'D78P322KC
fll'D783P322KD
IE-78320-R
IE-78320-R
PA-78P322KC
PA-78P322KD
RA78K3
RA78K3
ST78K3
ST78K3
CC7832X
CC7832X
~D78P322L
IE-78320-R
IE-78320-R
IE-78320-R
IE-78320-R
PA-78P322L
PA-71 P301 GF
PA-71 P301 GO
PA-71 P301 KA
RA78K3
ST78K3
CC7832X
Part Number
(Note 1)
Emulator'
Emulation
Probe'
fll'D78310ACW
IE-78310A·R
fll'D78310AGF·3BE
IE-78310A-R
fll'D78310AGO-36
~D71P301GF-3BE
fll'D71P301GO-36
fll'D71P301KA
(Note 8)
fll'D71P301KB
(Note 9)
fll'D71P301L
fll'D71P301RO
EP-78320GJ-R
(Note 7)
EP-78320L-R
EP-78320GJ-R
(Note 7)
EP-78320L-R
EP-78320GJ-R
(Note 7)
EP-78320L-R
EPROM/alP
Device
fll'D78P322GJ
fll'D78P322KD
fll'D78P322L
fll'D78P322KC
PG·1500
Adapter
(Note 2)
IE-78320-R
PA-71 P301 KB
IE-78320-R
IE-78320-R
PA-71P301L
PA-71 P301 GO
CCompiler
(Note 13)
a
• Required Tools
1-15
NEe
I-lPD783l(X Series
Notes:
(1)
Packages:
(7)
Package
Description
CW
OW
GF-3BE
GJ-SBJ
G0-36
KA
KB
KC
KD
L
64-pin plastic shrink DIP
64-pin Ceramic shrink DIP with window
64-pin plastic QFP (Resin Thickness: 2.7 mm)
74-pin plastic QFP (20 mm x 20 mm)
64-pin plastic QUIP
44-pin ceramic LCC with window
64-pin ceramic LCC with window
68-pin ceramic LCC with window
74-pin ceramic LCC with window
44-pin PLCC (jI.PD71P301L)
68-pin PLCC (jI.PD78310Al312A1P312AL,
I1PD783201322L)
64-pin ceramic QUIP with window
64-pin ceramic QUIP with window
R
RQ
The EP-78320GJ-R emulation probe is shipped with one EV.. 9200G-74, a 74-pin LCC socket with the footprint of the QFP
. package, Additional sockets are available as replacement parts
in sets of five.
(8)
Sockets for the I1PD71 P301 KA (44-pin LCC package) are
available from Yamaichi, Inc. (IC61-o444-030).
(9)
Scckets for the I1PD71 P301 KB (64-pin LCC package) are
available from NEC Electronics (EV-9200G-64) in se.ts offive.
(10) The followin!;! evaluation boards are available for the I1PD783XX
series:
Part Number
DesIgn/Development Boards
I1PD7831XA
I1PD7832X
EB-78320-PC
Evaluation Boards
DDK-78310A
(11) The following relocatable packages are available:
(2)
By using the specified adapter, the PG-1S00 EPROM programmer can be used to program the EPROMlOTP device.
(3)
The emulation probe for the 64-pin shrink DIP package (EP78310CW) is supplied with the IE.
(4)
The emulation probe for the 64-pin QUIP package (EP78310GQ) is supplied with the IE.
(13) The following C Compiler packages are.available:
(S)
There are two C Compilers for the I1PD7831X devices: CC7831 X
from NEC Electronics and one from Lattice Corporation.
CCMSD-ISDD-7831X
CCMSD-ISDD-7832X
(6)
The EP-78310GF emulation probe is shipped with one EV9200G-64, a 64-pin LCC socket with the footprint of the QFP
package. Additional sockats are available as replacement parts
in sets of five.
MS-DOS is a registered trademark of Microsoft Corporation.
VAX and VMS are registered trademarks of Digital Equipment Corporation.
1-16
RA-78K3-DS2
RA-78K3-VVn
(MS-DOS-)
(VAXNMS'1
Relocatable assembler
for 783XX series
(12) The ST78K3 structured assembler preprocessor is provided with
RA78K3.
(MS-DOS-)
. (MS-DOS-)
Forl1PD7831X series
For I1PD7832X series
NEe
PG·1500
Programming Adapters
Socket Ada~ters and Ada~ter Modules
Target Chip
Socket Adapter
(Note 1)
Adapter Module
(Note 2)
Standard 27XXX EPROM Devices
!ll'D27256 (12.5 V)
flI'D27256 (21 V)
flI'D27C256
flI'D27C256A
flI'D27C512
flI'D27C1000
flI'D27C1001
!ll'D27C10124
PA-75P54CS
PA-75P54CS
PA-75P54CS
PA-75P54CS
PA-75P54CS
PA-75P54CS
PA-75P56CS
PA-75P56CS
04A Board
04A Board
04A Board
04A Board
04A Board
04A Board
04A Board
04A Board
IlPD75XXX Series Devices
flI'D75POO8CU
flI'D75POO8GB
flI'D75P036CW
flI'D75P036GC
flI'D75P108BCW
flI'D75P108CW
flI'D75P108DW
flI'D75P108BGF
flI'D75P108G
flI'D75Pl16CW
flI'D75Pl16GF
flI'D75P216GF
flI'D75P308GF
flI'D75P308K
flI'D75P316GF
flI'D75P316AGF
flI'D75P316AK
flI'D75P328GC
flI'D75P402C
flI'D75P402CT
flI'D75P402GB
flI'D75P516GF
I!fD75P516K
PA-75POOSCU
PA-75POOSCU
PA-75P036CW
PA-75P036GC
PA-75P1OSCW
PA-75P1OSCW
PA-75P108CW
PA-75P1OSG
PA-75Pl16GF
PA-75P1OSG
PA-75Pl16GF
PA-75P1OSCW
PA-75P108G
PA-75P116GF
PA-75P216ACW
PA-75P3OSGF
PA-75P3OSK
PA-75P308GF
PA-75P308GF
PA-75P308K
PA-75P328GC
(Note 3)
PA-75P402CT
PA-75P402GB
PA-75P516GF
PA-75P516K
Socket Adapter
Adapter Module
(Note 1)
(Note 2)
IlPD78XX Series Devices
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
IlPD75XX Series Devices
flI'D75P54CS
flI'D75P54G
flI'D75P56CS
flI'D75P56G
!ll'D75P64CS
flI'D75P64G
flI'D75P66CS
flI'D75P66G
Target Chip
04A Board
04A Board
04A Board
04A Board
04A Board
04A Board
04A Board
04A Board
04A Board
04A Board
04A Board
04A Board
04A Board
04A Board
04A Board
04A Board
04A Board
04A Board
04A Board
04A Board
04A Board
027A Board
027A Board
027A Board
04A Board
04A Board
flI'D78CP14CW
flI'D78CP14DW
flI'D78CP14G
flI'D78CP14GF
flI'D78CP14L
flI'D78CP14R
PA-78CP14CW
PA-78CP14CW
PA-78CP14GO
PA-78CP14GF
PA-78CP14L
PA-78CP14GO
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
II
IlPD78XXX Series Devices
flI'D71P301GF
flI'D71P301GO
flI'D71P301KA
flI'D71 P301 KB
flI'D71P301L
flI'D78P214CW
!ll'D78P214GJ
!ll'D78P214GO
!ll'D78P214L
flI'D78P224GJ
flI'D78P224L
flI'D78P238GC
flI'D78P238GJ
flI'D78P238KF
flI'D78P238LO
flI'D78P312ACW
!ll'D78P312ADW
flI'D78P312AGF
flI'D78P312AGO
!ll'D78P312AL
flI'D78P312AR
flI'D78P322GJ
!ll'D78P322KC
flI'D78P322KD
flI'D78P322L
PA-71 P301 GF
PA-71P301GO
PA-71 P301 KA
PA-71 P301 KB
PA-71P301L
PA-78P214CW
PA-78P214GJ
PA-78P214GO
PA-78P214L
PA-78P224GJ
PA-78P224L
PA-78P238GC
PA-78P238GJ
PA-78P238KF
PA-78P238LO
PA-78P312CW
PA-78P312CW
PA-78P312GF
PA-78P312GO
PA-78P312L
PA-78P312GO
PA-78P322GJ
PA-78P322KC
PA-78P322KD
PA-78P322L
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
027A Board
PA-70P322L
027A Board
V-Series Devices
flI'D70P322K
Digital Signal Processors
flI'D77P56CR
!ll'D77P56G
!ll'D77P25C
!ll'D77P25D
!ll'D77P230R
PA-77P56C
PA-77P56C
PA-77P25C
PA-77P25C
PA-77P230R
04A Board
04A Board
027A Board
027A Board
027A Board
Not.. :
(1) All socket adapters must be purchased separately.
(2) The 27A and 04A Adapter Modules are shipped with the PG-1500.
(3) The IlPD75P402C does not require a programming socket
adapter. It can be plugged direcdy into the 027A board.
1-17
PG·1500
1-18
NEe
NEe
V-Series
Microprocessors and Peripherals
CMOS Microprocessors
Device,
).lPD
Features
70008A
'Z80 microprocessor
70108
(V2O)
Data
BIts
(MHz)
8
8
8088 compatible; enhanced
8/16
80rl0
70116
(V30)
8086 compatible; enhanced
16
80rl0
70208
(V40)
MS-DOS, V20 compatible CPU with peripherals
8/16
80rl0
70216
(V50)
MS-DOS, V30 compatible CPU with peripherals
16116
80rl0
70616
(V60)
70632
(V70)
70832
(V80)
70136
(Vaa)
70236
(V53)
70320
(V25)
70330
(V35)
70325
(V25+)
70335
(V35+)
70327
(V25 Software Guard)
70337
(V35 Software Guard)
79011
(V25 RTOS)
79021
(V35 RTOS)
70322
(V25 ROM)
32-bit; high-speed
16132
16
32-bit; high-speed
32132
20/25
32-bit; high-speed
32132
Hardwired, enhanced V30
16
vaa core-based; high-integration; DMA, serial 1/0,
interrupt controller, etc.
MS-DOS compatible; high-integration; DMA, serial 1/0,
interrupt controller, etc.
MS-DOS compatible; high-integration; DMA, serial 1/0,
interrupt controller, etc.
MS-DOS compatible; high-integration; high-speed DMA
16
Clock
• Package
PIns
DIP
CFP
PLCC
DIP
Cenimic DIP
CFP
PLCC
DIP
Ceramic DIP
QFP
PLCC
CeramicPGA
PLCC
OFP
PGA
PLCC
QFP
PGA
40
44
44
40
40
52
44
40
40
52
44
68
68
80
68
68
80
68
PGA
132
25
CeramicPGA
208
12 or 16
PGA
PLCC
Ceramic PGA
OFP
PLCC
OFP
PLCC
QFP
PLCC
OFP
PLCC
QFP
PLCC
QFP
PLCC
OFP
PLCC
QFP
PLCC
OFP
PLCC
OFp
68
68
132
120
84
94
84
94
84
94
84
94
84
94
84
94
84
94
84
94
84
94
8/16
50r8
16
8
8116
80rl0
16
80rl0
MS-DOS compatible; high-integration; software protection
8/16
8
MS-DOS compatible; high-integration; software protection
16
8
MS-DOS compatible; high-integration; real-time operating system
8/16
8
MS-DOS compatible; high-integration; real-time operating system
16
8
8/16
8
MS-DOS compatible; high-integration; high-speed DMA
MS-DOS compatible; high-integration; 16K-byte ROM
# Plastic unless ceramic (or cerdip) is specified.
, For additional information, refer to 1987 Microcomputer Oata B9ok.
1-19
II
NEe
V-Series
CMOS Microprocessors (cont)
Device,
",PO
70P322
70332
(V35 ROM)
Features
MS-DOS compatible; high-integration; 16K-byte UVEPROM;
V25 or V35 mode
MS-DOS compatible; high-integration; 16K-byte ROM
Data
Bits
(MHz)
Clock
• Package
Pins
8/16
8
Ceramic LCC
84
16
8
PLCC
OFP
84
94
Data
Bits
Clock
NMOS and HMOS Microprocessors
Device,
",PO
Features
808SA
'8-bit microprocessor; NMOS or HMOS
8
5
DIP
40
8086
'16-bit microprocessor; HMOS
16
8
Cerdip
40
8088
'8-bit microprocessor; HMOS
8
8
Ceramic DIP
40
Data
Bits
(MHz)
# Package
Pins
(MHz)
• Package
Pins
CMOS System Support Products
Device,
",PO
Name
71011
Clock Pulse Generator/Driver
71037
Programmable DMA Controller
8
10
71051
Serial Control Unit
8
8/10
71054
Programmable Timer/Controller
8
8/10
71055
Parallel Interface Unit
8
8/10
71059
Interrupt Control Unit
8
8/10
71071
DMA Controlle r
8/16
8/10
71082
Transparent Latch
8
8
71083
Transparent Latch
8
71084
Clock Pulse GeneratorlDriver
71086
Bus BufferlDriver
8
8
71087
Bus Buffer/Driver
8
8
1-20
Clock
DIP
SOP
DIP
OFP
PLCC
DIP
OFP
PLCC
DIP
OFP
PLCC
DIP
OFP
PLCC
18
20
40
40
44
28
44
28
24
44
28
40
44
44
DIP
OFP
PLCC
DIP
Ceramic DIP
OFP
PLCC
DIP
SOP
28
44
28
48
48
52
52
20
20
8
DIP
SOP
20
20
25
DIP
SOP
DIP
SOP
DIP
SOP
18
20
18
20
20
20
20
NEe
V-Series
CMOS System Support Products (cont)
Device,
IlPD
71088
Name
Syslem Bus Controller
8110
82C43
·lnputlOutput Expander
5
Data
Blta
Clock
(MHz)
• Package
Plna
DIP
SOP
DIP
Skinny DIP
20
20
24
24
Plna
NMOS System Support Products
Device,
IlPD
Name
8l55H
8l56H
Data
Blta
Clock
(MHz)
# Peckage
·256 x 8 RAM; 110 ports and timer
8
30r5
DIP
40
·256 x 8 RAM; 110 ports and timer
8
30r5
DIP
40
8237A
·Programmable DMA Controller
8
5
DIP
40
8243
"InputlOutput Expander
5
DIP
24
8251A
·Programmable Communications Inlerface
8
3J5
DIP
28
8253
"Programmable Internal Timer
8
5
DIP
24
40
8255A
·Programmable Peripherallnleriace
8
5
DIP
8257
·Programmable DMA Controller
8
5
DIP
40
8259A
·Programmable Interrupt Controller
8
5
DIP
28
8279
·Programmable Keyboard/Display Inlerface
5
DIP
40
1-21
II
V-Series
1-22
tvEe
Intelligent
Peripheral Devices (lPD)
1tIEC
Communications Controllers
Device,
Il PD
Name
Description
7201A
Multiprotocol Serial
Communications Controller
72001
CMOS, Advanced Multiprotocol
Serial Communications
Controller
72002
CMOS, Advanced Multiprotocol
Serial Communications Controller
Dual full-duplex serial channels; four DMA channels;
programmable interrupt vectors; asychronous
COP and BOP support; NMOS
Functional superset of 8530; 8086N30 interface; two
full-duplex serial channels; two digital phase-locked
loops; two baud-rate generators per channel; loopback
test mode; short frame and mark idle detection
Low-cost, single-channel version of 72001; software
compatible; direct interface to 8237 DMA.
CMOS, HDLC Controller
Not included in 1989-1990 IPD Data Book; refer to 72002
data sheet.
Single full-duplex serial channel; on-ehip DMA Controller.
72103
Data Rate
# Package
Pins
1 Mb/s
DIP
Ceramic DIP
40
40
2.5 Mb/s
DIP
OFP
PLCC
40
52
52
2.5 Mb/s
DIP
OFP
PLCC
40
44
44
4 Mb/s
DIP
PLCC
64
68
Not included in 1989-1990 IPDData Book; refer to 72103
data sheet
Graphics Controllers
Device,
IlPD
7220A
72020
72120
72123
Name
Description
High-Performance
Graphics Display
Controller
Graphics Display
Controller
Advanced Graphics
Display Controller
General-purpose, high-integration controller; hardwired
supportfor lines, arC/circles, rectangles, and graphics
characters; 1024xl024 pixel display with four planes
CMOS 7220A with 2M video memory; dual-port RAM control;
write-masking on any bit; enhanced external synch
High-speed graphics operations including paint, area fill,
slant, arbitrary angle rotate, up to 16x enlargement and
reduction; dual-port RAM control; CMOS
Enhanced 72120; expanded command set; improved painting
performance; laser printer interface controls; CMOS
Advanced Graphics
Display Controller II
Drawing Rate
# Package
Pins
500 ns/dot
Ceramic DIP
40
500 ns/dot
DIP
OFP
PLCC
OFP
40
52
84
94
PLCC
OFP
84
94
500 ns/dot
400 ns/dot
Advanced Compression/Expansion Engine
Device,
IlPD
72185
Name
Description
# Package Pins
Advanced Compression/
Expansion Engine
High-speed ccm Group 3/4 bit-map image compression/expansion (A4test
chart, 400 PPI x 400 LPI in under 1 second); 32K-pixelline length; 32-megabyte
image memory; on-chip DMA and refresh timing generator; CMOS
SDiP
PLCC
64
68
# Plastic unless ceramic (or cerdip) is specified.
1-23
II
NEe
IPD
Floppy-Disk Controllers
Device,
ILPD
Name
Description
765A1B
Floppy-Disk Controller
71065166
Floppy-Disk Interface
72064'
Floppy-Disk Controller
72065165B
CMOS Roppy-Disk
Controller
72067
Transfer
Rate
'Package
Industry-standard controller supporting IBM 3740 and IBM
System 34 double-density format; enhanced 765B supports
multitasking applications
Compatible with 765-family controllers and others; supports
multiple data rates from 125 to SOO kb/s
CMOS; All features of 72068 with complete AT register set.
Pin compatible with WD 37C651AIB but with higher
performance DPLL and reliable multitasking operation
100% 765AIB microcode compatible; compatible with 808x
microprocessor families
500 kbls
DIP
40
SOO kb/s
SOP
SDiP
PLCC
aFP
28
30
44
52
Floppy-Disk Controller
CMOS; 765A1B microcode compatible; clock generationl
switching circuitry; selectable write precompensation;
digital phase-locked loop
500 kb/s
DIP
PLCC
QFP
DIP
aFP
PLCC
72068
Floppy-Disk Controller
500 kb/s
72069
Floppy-Disk Controller
All features of the 72067 plus IBM-PC, PCIXT, PC/AT, or
PS/2 style registers; 24-ma high-current drivers
All features of the 72067168 with substitution of highperformance analog phase-locked loop for digital PLL
aFP
PLCC
PLCC
aFP
40
44
52
48
52
52
80
84
84
100
ReadlWrlte
Clock
500 kb/s
500 kb/s
1 Mb/s
Pins
Hard-Disk Controllers
Device,
ILPD
Name
Description
'Package
Pins
7261AIB
Hard~ilisk Controller
23 MHz
Ceramic DIP
40
7262
Enhanced Small-pisk
Interface (ESDI) Controller
CMOS Hard-Disk
Controller
Supports eight drives in SMD mode, four drives in ST506
mode; error correction and detection
Serial;mode ESDI compatible; controls up to seven drives;
supports up to 80 heads; hard and soft-sector interfacing
Supports SMDISMD-E and ST5061412 type drives
18 MHz
Ceramic DIP
40
24 MHz
Selectable 8/16 data bus width; 16 high-level commands
for reduced CPU load; single-command automatic
execution; 5-Mb sync/async; CMOS
16 MHz
DIP
aFP
PLCC
SDiP
aFP
PLCC
40
52
52
64
74
68
72061
72111
Small Computer System
Interface (SCSI) Controller
• Not included in 1989-90 IPO Data Book; refer to 72064 Data Sheet.
1-24
NEe
DSP and
Speech Products
Digital Signal Processors
Device,
j.1PD
Description
7720A
16-bit, fixed-point DSP; NMOS
Instruction
Cycle (ns)
Instruction
ROM (Bits)
Data ROM
(Bits)
Data RAM
(Bits)
244
512 x 23
510 x 13
128x 16
77C20A
16-bit, fixed-point DSP; CMOS
244
512 x 23
510 x 13
128 x 16
77P20
16-bit, fixed-point DSP; CMOS
244
16-bit, fixed-point DSP; CMOS
122
510 x 13
UVEPROM
1024 x 16
128 x 16
77C25
512 x 23
UVEPROM
2048 x 24
77P25
16-bit, fixed-point DSP; CMOS
122
2048 x 24
OTPROM
2048 x 24
UVEPROM
2048 x 32
1024 x 16
OTPROM
1024 x 16
UVEPROM
1024 x 24
256 x 16
256 x 16
256 x 16
512 x 24
# Package
DIP
PLCC
DIP
PLCC
PLCC
Cerdip
Pins
2~
44
28
28
44
28
DIP
PLCC
SOP
DIP
PLCC
Cerdip
28
44
32
68
68
68
28
44
28
77220
24-bit, fixed-point DSP; CMOS
122
77P220R
24-bit, fixed-point DSP; CMOS
122
2048 x 32
UVEPROM
1024 x 24
UVEPROM
512 x 24
Ceramic PGA
PLCC
Ceramic PGA
77230AR
32-bit, floating-point DSP; CMOS
150
2048 x 32
1024 x 32
1024 x 32
Ceramic PGA
68
77230AR-003
150
n/a
n/a
n/a
Ceramic PGA
68
77P230R
32-bit, floating-point DSP; CMOS;
standard library software
32-bit, floating-point DSP; CMOS
150
Ceramic PGA
68
16-bit fixed-point modem DSP; CMOS
181
1024 x 32
UVEPROM
1024 x 16
1024 x 32
77810
2048 x 32
UVEPROM
2048 x 24
256 x 16
Ceramic PGA
PLCC
7281
Image pipelined processor; NMOS
5-MHzclock
n/a
n/a
512 x 18
Ceramic DIP
68
68
40
72181
Image pipelined processor; CMOS
10-MHz clock
n/a
n/a
512 x 18
9305
Support device for j.tI'D7281
processors; CMOS
10-MHz
clock
n/a
n/a
n/a
DIP
OFP
Ceramic PGA
40
68
132
• Package
Pins
Speech Processors
Device,
j.1PD
Clock
Name
Data ROM
(Bits)
Technology
(MHz)
NMOS
NMOS
8
77C30
ADPCM Speech Encoder/Decoder
ADPCM Speech Encoder/Decoder
7755
ADPCM Speech Synthesizer
CMOS
0.7
96K
7756
ADPCM Speech Synthesizer
CMOS
0.7
256K
77P56
ADPCM Speech Synthesizer
CMOS
0.7
7757
ADPCM Speech Synthesizer
CMOS
0.7
256K
OTPROM
512K
7759
ADPCM Speech Synthesizer
CMOS
0.7
7730
8
1024K
external
DIP
DIP
PLCC
DIP
SOP
DIP
SOP
DIP
SOP
DIP
SOP
DIP
OFP
28
28
44
18
24
18
24
20
24
18
24
40
52
# Plaslic unless ceramic (or cerdip) is specified.
1-25
a
DSP and Speech
1-26
NEe
NEe
V-Series
Development Tools
V-Series Development Tools
Part
Number
(Note 1)
Full
Emulator
).II'D70136GJ-12
IE-70136-A016
).II' D70136GJ-16
IE-70136-A016
).II'D70136L-16
).II'D70136L-12
).II'D70136R-12
IE-70136-A016
IE-70136-A016
IE-70136-A016
).II'D70136R-16
IE-70136-A016
).II'D70208GF-8
).II'D70208GF-l0
).II'D70208L-8
IE-70208-A010
IE-70208-A010
IE-70208-A010
EP-70136L-A
(Note 2)
EP-70136L-A
(Note 2)
EP-70136L-A
EP-70136L-A
EP-70136L-A
(Note 3)
EP-70136L-A
(Note 3)
(Note 12)
(Note 12)
IE-7OOOO-2958
).II'D70208L-10
IE-70208-A010
IE-7OOOO-2958 EB-V40MINHE
).II'D70208R-8
).II'D70208R-10
).II'D70216GF-8
).II'D70216GF-l0
).II'D70216L-8
IE-70208-A010
IE-70208-A010
IE-70216-A010
IE-70216-A010
IE-70216-A010
IE-7OOOO-2959
IE-7OOOO-2959
(Note 12)
(Note 12)
IE-7OOOO-2958
).II'D70216L-l0
IE-70216-A010
IE-70000-2958 EB-VSOMINI-IE
).II'D70216R-8
).II'D70216R-l0
fLPD70320GJ
IE-70216-A010
IE-70216-A010
IE-70320-A008
EB-V50MINI-IE
EB-V50MINI-IE
EB-V25MINI-IE-P
fLP D70320GJ-8
IE-70320-A008
fLPD70320L
fLPD70320L -8
fLPD70322GJ
IE-70320-AOO8
IE-70320-AOO8
IE-70320-A008
fLPD70322GJ-8
IE-70320-AOO8
fLPD70322L
IE-70320-AOO8
IE-7OOOO-2959
IE-70000-2959
EP-70320GJ
(Note 5)
EP-70320GJ
(Note 5)
EP-70320L
EP-70320L
EP-70320GJ
(Note 5)
EP-70320GJ
(Note 5)
EP-70320L
EB-V25MINI-IE-P
ADAPT68PGA
68PLCC (Note 4)
ADAPT68PGA
68PLCC (Note 4)
(Note 4)
(Note 4)
EP-70320GJ
(Note 6)
EP-70320GJ
(Note 6)
(Note 7)
(Note 7)
EP-70320GJ
(Note 6)
EP-70320GJ
(Note 6)
(Note 7)
fLPD70322L-8
IE-70320-A008
EP-70320L
EB-V25MINI-IE-P
(Note 7)
DDK-70320
fLPD70325GJ-8
IE-70325-AOOS
EP-70320GJ
(Note 5)
(Note 12)
(Note 12)
fLPD70325GJ-l0
IE-70325-A008
(Note 8)
IE-70325-A008
IE-70325-A008
(Note 8)
EP-70320GJ
(Note 5)
(Note 12)
EP-70320L
EP-70320L
(Note 12)
(Note 12)
fLPD70325L-8
fLPD70325L-10
Full
Emulator
Probe
Relocatable
EPROM/OTP Assembler CCompller
(Note 13)
(Note 14)
Device
Mini-IE
Emulator
Mini-IE
Probe
Evaluation
Boards
IE-70136-PC
EP-70136L-PC
(Note 2)
EP-70136L-PC
(Note 2)
EP-70136L-PC
EP-70136L-PC
EP-70136L-PC
(Note 3)
EP-70136L-PC
(Note 3)
DDK-70136
RA70136
CC70136
DDK-70136
RA70136
CC70136
DDK-70136
DDK-70136
DDK-70136
RA70136
RA70136
RA70136
CC70136
CC70136
CC70136
DDK-70136
RA70136
CC70136
EB-70208
EB-70208
EB-70208
RA70116
RA70116
RA70116
CC70116
CC70116
CC70116
EB-70208
RA70116
CC70116
EB-70208
EB-70208
EB70216
EB70216
EB70216
RA70116
RA70116
RA70116
RA70116
RA70116
CC70116
CC70116
CC70116
CC70116
CC70116
EB70216
RA70116
CC70116
EB70216
EB70216
DDK-70320
RA70116
RA70116
RA70320
CC70116
DDK-70320
RA70320
CC70116
DDK-70320
RA70320
RA70320
RA70320
CC70116
DDK-70320
DDK-70320
DDK-70320
RA70320
CC70116
RA70320
CC70116
RA70320
CC70116
DDK-70325
RA70320
CC70116
(Note 12)
DDK-70325
RA70320
CC70116
(Note 12)
(Note 12)
DDK-70325
RA70320
RA70320
CC70116
CC70116
IE-70136-PC
IE-70136-PC
IE-70136-PC
IE-70136-PC
IE-70136-PC
EB-V40MINI-IE
EB-V40MINHE
EB-V40MINHE
EB-V40MINI-IE
EB-V40MINHE
EB-V50MINI-IE
EB-V50MINHE
EB-V50MINI-IE
EB-V25MINI-IE-P
EB-V25MINHE-P
EB-V25MINI-IE-P
EB-V25MINHE-P
EB-V25MINI-IE-P
ADAPT68PGA
68PLCC (Note 4)
ADAPT68PGA
68PLCC (Note 4)
(Note 4)
(Note 4)
DDK-70320
DDK-70325
70P322K
(Note 10)
70P322K
(Note 10)
a
CC70116
CC70116
CC70116
CC70116
1-27
NEe
V-Series
V-Series Development Tools (cont)
Part
Number
(Note 1)
Full
Emulstor
ILPD70327GJ-8
(Note 9)
ILPD70327L-8
(NQte 9)
ILPD70330GJ-S
IE-70330-A008
ILPQ70330L-S
ILPD70332GJ-S
IE-70330-A008
IE-70330-A008
ILPD70332L-S
IE-70330-A008
ILPD70335GJ-S
I,E-70335-A008
ILPD70335GJ-l0
IE'70335-AOOS
(Note 8)
IE-70335-A008
IE-7033.5-A008
(Note 8)
IE-7033O-AOOS
ILPD70335L-8
ILPD70335L-l0
ILPD70337GJ-8
(Note 9)
ILPD70337L-8
(Note 9)
ILPD79011 GJ-8
(Note 11)
ILPD79011 L-S
(Note 11)
ILPD79021L-8
(Note 11)
Notes:
(1) Packages:
Package
·GF
GJ
K
L
R
IE-70320-AOOS
IE-70230-AOOS
IE-70330-A008
IE-70320-AOOS
+IE-70320-RTOS
IE-70330-AOOS
+IE-70330-RTOS
Full.
Emulator
Probe
EP-7032QGJ
(Note 5)
EP-70320L
EP-70320GJ
(Note 5)
EP-70320L
Ep·70320GJ
, (Note 5)
EP-70320L
Mini-IE
Emulator
Mini-IE
Probe
EB-V25MINI-IE-P
EP-70320GJ
(Note 6)
(Note 7)
EB-V25MINI-IE-P
Relocatilble
EPROM/OTP Assembler CComplier
(Note 10)
(Note 11)
Davlca
RA70320
CC70116
RA70320
CC70116
EP-70320GJ
(Note 6)
(Note 7)
EP-70320GJ
(Note 6)
(Note 7)
DDK-70330
RA70320
CC70116
DDK-70330
DDK-70330
RA70320
RA70320
CC70116
CC70116
RA70320
CC70116
EP-70320GJ . (Note 12)
(Note 5)
EP-70320GJ
(Not~ 12)
(Note 5)
EP-70320L
(Note 12)
EP-70320L
(Note 12)
(Note 12)
DDK-70330
RA70320
CC70116
(Note 12)
DDK-70330
RA70320
C070116
(Note 12)
(Note 12)
DDK-70330
DDK-70330
RA70320
RA70320
CC70116
CC70116
EP-70320GJ
(Note 5)
EP-70320L
EB-V35MINI-IE-P
RA70320
C070116
EB-V35MINI-IE-P
EP-70320GJ
(Note 6)
(Note 7)
RA70320
CC70116
EP-70320GJ
(Note 5)
EP-70320L
(Note 12)
(Note 12)
RA70320
CC70116
(Note 12)
(Note 12)
RA70320
CC70116
EP-70320L
(Note 12)
(Note 12)
RA70320
CC70116
EB'V35MINI·IE-P
EB-V35MINI·IE·P
EB-V35MINI-IE·P
EB-V35MINI·IE-P
~, Description
8o-pin plastic OFP
74-pin or 94-pin plastic OFP
84-pin ceramic LCC with window
S8-pin or 84-pin plastic LCC
S8-pin PGA
(3) 68-pin PGA parts are supported by using the EP-7013SL-A
PLC.c probe or EP-70136L-PC PLCC probe, plus a PLCC
socket with a PGA~pinout. A PLCC socket of this type is
supplied with the EP-7013SL-A.
(4) The EB~V40 MINI-IE and EB-V50 MINI-IE support PGA
packages direc~y; the ADAPTS8PGAS8PLCC adapter
converts the PGA-pinollt on the MINI-IE to a PLCC footprint.
This adapter is supplied with the MINI-IE.
DDK-70330
70P322K
(Note 10)
(5) The EP-70320GJ is an adapter to the EP-70320L, which converts
84-pin PLCC probes to a 94-pin OFP footprint. For GJ parts,
both the PLCC probe and the adapter are needed.
(S) The EP-70320GJ adapter can be used to convert the supplied
84-pin PLCC cable. of the EB-V25 MINI-IE-Por EB-V35 MINI-IE-P
to a 94-pin OFP.
(7)
(2) The EP-7013SGL-A and EP-7013SL-PC contain both a 58-pin
PLCC probe and an adapter Which converts the S8-pin PLCC
probes to a 74-pin OFP footprint
1-28
Evaluation
Bosrds
The EB-V25 MINI-IE-P and EB-V35 MINI-IE-P are supplied with an
84-pin PLCC cable.
(8) At the current time, the emulators for the ILPD70325 and ILPD70335
are specified to 8 MHz. Contact your local NEC Sales Office for the
latest information on 10 MHz emulation.
(9) Development for the fLPD70327 or ILPD70337 can be done using
the appropriate ILPD70320 or ILPD70330 tools; however,
debugging the programs in the Software Guard mode is
not supported at this time.
(10) The ILPD70P322K EPROM device can be used for both ILPD70322
and ILPD70332 emulation. The ILPD70P322K EPROM device can
be programmed by using the PA-70P322L Programming Adapter
and the PG-1500 EPROM Programmer.
NEe
V-Series
V-Series Development Tools (cont)
Notes (continued):
(11) For emulation of J.lPD79011 or J.lPD79021, the base emulator
(IE-70320 or IE-70330) plus Real-Time Operating System
software IE-70320-RTOS or IE-70330-RTOS) is required.
(12) This emulation option is not currently supported, but may be
available in the future. Contact your local NEC Sales Office for
further information.
(13) The following relocatable assemblers are available:
RA70116-D52
RA70116-VVT1
RA70116-VXT1
For V20*N30"/
V40"W50™
(MS-DOS")
(VAXNMSTM)
(VAx/UNIXTM 4.2 BSD or
UltrixTM)
RA70136-D52
RA70136-VVT1
RA70136-VXT1
ForV33™
(MS-DOS)
(VAXNMS)
(VAx/UNIX 4.2 BSD or
Ultrix)
RA70320-D52
RA70320-VVT1
RA70320-VXT1
ForV25™
and V351M
(MS-DOS)
(VAXNMS)
(VAx/UNIX 4.2 BSD or
Ultrix)
(14) The following C compilers are available:
CC70116-D52
CC70116-VVT1
CC70116-VXT1
For V20N30/
V40N50 and
V25N35
(MS-DOS)
(VAXNMS)
(VAx/UNIX 4.2 BSD or
Ultrix)
CC70136-D52
CC70136-VVT1
CC70136-VXT1
For V33
(MS-DOS)
(VAXNMS)
(VAx/UNIX 4.2 BSD or
Ultrix)
V20 and V30 are registered trademarks of NEC Corporation.
V25, V33, V35, V40 and V50 are trademarks of NEC Corporation.
MS-DOS is a registered trademark of Microsoft Corporation.
VAX, VMS and Ultrix are trademarks of Digital Equipment Corporation.
UNIX is a trademark of AT&T Bell Laboratories.
1-29
a
V-Series
1-30
NEe
NEe
DSP and Speech
Development Tools
DSP and Speech Development Tools
Part Number
(Note 7)
flI'D7720AC
flI'D7720AL
flI'D77P20D
flI'D77C20AC
flI'D77C20AL
flI'D77C20ALK
flI'D77220L
flI'D77220R
flI'D77P220R
flI'D77230AR
flI'D77P230R
flI'D77C25C
flI'D77C25L
flI'D77P25C
flI'D77P25D
flI'D77P25L
flI'D7755C
flI'D7755G
fLPD7756C
flI'D7756G
flI'D77P56CR
flI'D77P56G
flI'D7757C
flI'D7757G
flI'D7759C
flI'D7759GC
flI'D77810L
flI'D7781 OR
Emulator
Evaluation
Board
EVAKIT-7720B
EVAKIT-7720B (Note 4)
EVAKIH720B
EVAKIT-77208
EVAKIH720B (Note 4)
EVAKIT-7720B (Note 4)
EVAKIT-77220
EVAKIT-77220
EVAKIT-77220
EVAKIT-77230
EVAKIH7230
EVAKIH7C25
EVAKIH7C25 (Note 4)
EVAKIH7C25
EVAKIH7C25
EVAKIH7C25 (Note 4)
NV-300 System
NV-300 System
NV-300 System
NV -300 System
NV-300 System
NV-300 System
NV-300 System
NV-300 System
NV-300 System
NV-300 System
DDK-77230
DDK-77230
Simulator
(Note 2)
EPROM/OTP
Device
PG·1500
Adapter
(Note 3)
ASM77
ASM77
SIM77
SIM77
SIM77
SIM77
SIM77
SIM77
SM77230
SM77230
SM77230
SM77230
SM77230
~D77P20D
(Note 5)
flI'D77P20D
(Note 5)
flI'D77P220R
PA-77P230R
PA-77P230R
PA-77P230R
PA-77P230R
ASM77
ASM77
ASM77
ASM77
RA77230
RA77230
RA77230
RA77230
RA77230
RA77C25
The following simulators are available:
Part Number
Description
SIM77-D52
Simulator for 7720 (MS-DOS)
SM77230-VVTl
Simulator for 77230 (VAx/UNIX)
SM77230-VXTl
Simulator for 77230 (VAx/UNIXlM 4.2
BSD or Ultrix)
a
PA-77P25C
flI'D77P25L
PA-77P25C
PA-77P25C
EB-7759
EB-7759 (Note 6)
EB-7759
EB-7759 (Nole 6)
EB-7759
EB-7759 (Note 6)
EB-7759
EB-7750 (Note 6)
EB-7759
EB-7759
IE-77810
IE-77810
flI'D77P230R
flI'D77P25C/D
RA77C25
RA77C25
RA77C25
RA77C25
Notes:
(1)
The following assemblers are available:
Part Number
Description
ASM77-D52
Assembler for 7720 (MS-Dose)
RA77C25-D52
Assembler for 77C25 (MS-DOS)
RA77C25-VVTl
Assembler for 77C25 (VAXNMSlM)
RA77230-D52
Assembler for 77230 (MS-DOS)
RA77230-VVTl
Assembler for 77230 (VAXNMS)
RA77230-VXT1
Assembler for 77230 (VAX/UNIXlM 4.2
BSD or UltrixlM)
(2)
Assembler
(Note 1)
flI'D77P56CR
flI'D77P56G
flI'D77P56CR
flI'D77P56G
PA-77P56C
PA-77P56C
PA-77P56C
PA-77P56C
PA-77P56C
PA-77P56C
RA7781 0
RA7781 0
(3)
By using the specified adapter, the NEC PG-1500 EPROM
programmer can be used to program the EPROM/OTP device.
(4)
Please check with your NEC Sales Representative on the
availability of a PLCC emulation probe.
(5) The fLPD77P20D can be programmed using the EVAKIT-7720B.
(6) The EB-7759 comes with an emulation probe for only the 18-pin
DIP.
(7)
Packages:
Package
C
D
G
GC
L
LK
R
Description
18,28, or 40-pin plastic DIP
28-pin ceramic DIP
24-pin plastic SOP
52-pin plastic QFP
44-or 68-pin PLCC
28-pin PLCC
68-pin ceramic PGA
MS-DOS is a registered trademark of Microsoft Corporation.
VAX, VMS, and Ultrix are trademarks of Digital Equipment Corporation.
UNIX is a trademark of AT&T Bell Laboratories.
1-31
DSP and Speech
1-32
NEe
fttfEC
Reliability and Quality Control
EJ
I
1
p.
2-1
ttlEC
Reliability and Quality Control
Section 2
Reliability and Quality Control
Introduction
2-3
Built-In Quality and Reliability
2-3
Technology Description
2-3
Approaches to Total Quality Control
2-3
Implementation of Quality Control
2-5
Reliability Testing
2-7
Life Distribution
2-7
Failure Distribution at NEC
2-7
Infant Mortality Failure Screening
2-8
Long-Term Failure Rate
2-8
Accelerated Reliability Testing
2-8
Failure Rate Calculation/Prediction
2-9
Product/Process Changes
2-10
Failure Analysis
2-10
NECs Goals on Failure Rates
2-10
Summary and Conclusion
2-10
Figure 1. Quality Control System Flowchart
2-5
Figure 2. New Product Development Flow
2-6
Figure 3. Electrical Testing and Screening
2-6
Figure 4. Reliability Life (Bathtub) Curve
2-7
Figure 5. Typical Reliability Test Results
2-9
Figure 6. NEC Quality and Reliability Targets
2-10
Appendix 1. Typical QC Flow
2-12
Appendix 2. Typical Reliability Assurance Tests
2-15
Appendix 3. New Product/Process Change
Tests
2-16
Appendix 4. Failure Analysis Flowchart
2-17
ttlEC
Reliability and Quality Control
Introduction
Approaches to Total Quality Control
As large-scale integration reaches a higher level of density, the reliability of individual devices imposes a more
profound impact on system reliability. Great emphasis has
thus been placed on assuring device reliability.
TOC activities are geared towards total satisfaction of the
customer. The success of these activities is dependent
upon the total commitment of management to enhancing
employee development, maintaining a customer-first attitude, and fulfilling community responsibilities.
Conventionally, performing reliability tests and attaining
feedback from the field are the only methods by which
reliability has been monitored and measured. At these
higher levels of LSI density, however, it is increasingly
difficult to activate all of the internal circuit elements in a
device, moreover, to detect the degradation of those
elements by measuring characteristics across external
terminals. As a result, testing alone may not provide
enough information to insure today's demanding reliability
requirements. A different philosophy and methodology is
needed for reliability assurance.
In orderto guarantee and improve a high level of reliability
for large-scale integrated circuits, it is essential to build
quality and reliability into the product. Then, conventional
testing can be performed to confirm that the product
demonstrates acceptable reliability.
Built·ln Quality and Reliability
NEe has introduced the concept of total quality control
(TOe) across its entire semiconductor product line for
implementing this philosophy. Rather than performing
only a few simple quality inspections, quality control is
distributed into each process step and then summed to
form a consolidated system. TOC involves workers, engineers, quality control staffs, and all levels of management in company-wide activities. Please see Figure 1 for
the quality control system flowchart. Through TOC, NEe
builds quality into the product and thus can assure high
reliability. Additionally, NEC has introduced a pre-screening
method into the production line for eliminating potentially
defective units. This combination of building quality in and
screening projected early failures out has resulted in
superior quality and excellent reliability.
Technology Description
Most large-scale integrated circuits utilize high density
MaS technology. State-of-the-art high performance has
been achieved by improving fine-line generation techniques. By reducing physical parameters, circuit density
and performance increase while active circuit power dissipation decreases. The data presented here shows thatthis
advanced technology, combined with the practice of TOe,
yields products as reliable as those from previous technologies.
10002
First, the quality control function is embedded into each
process. This method enables early detection of possible
causes of failure and immediate feedback.
Second, the reliability and quality assurance policy reflects
the beliefs and practices of the entire organization. This
enables companywide quality control activities: at NEe,
everyone is involved with the concept and methodology of
total quality control.
Third, there is an ongoing research and development effort
to set even higher standards of device quality and reliability.
Fourth, extensive failure analysis is performed periodically
and appropriate corrective actions are taken as preventative measures. Process control is based on statistical data
gathered from this analysis.
The new standard is continuously upgraded, and the
iterative process continues. The goal is to maintain the
superior product quality and reliability that has become
synonymous with the NEe name.
Zero Defect Activities. One of the activities that involves
every level of the NEC staff in quality control is the Zero
Defects (ZD) Program. As the name implies, the purpose
of the ZD program is to minimize, if not eradicate, defects
due to controllable causes. Such activities must involve
each and every worker and can be most effective when
pursued by groups of workers. The groups of workers are
organized by consideration of the following:
• A group must have a target to pursue
• Several groups can be organized to pursue the common target
• Each group must have a responsible person
• Each group is well supported
The item of the group target is to be selected among items
relating to specifications, inspections, operation standards,
and so forth. When data made in the past is available, it is
used to make a Pareto diagram which is reviewed for
selection ofthe item most conducive to quality improvement.
Records are analyzed and compared with the target, in
order to compute the numerical equivalents of the defects.
Action is then taken to control these defects as required.
2-3
fI
t\'EC
Reliability and Quality Control
Figure 1. Quality Control System Flowchart
Dept
Customer
Market/Sales
Needs
Market
Research
'ECD
...
E
.!!
CD
>
2l
I
Circuit Design
DeVice Design
Production
Engineering
I
Development
of
Technology
I
R&QC
I
Manufacturing Facility
(Inspection) (Manufacturing)
Planning
~
rl
Sales
Plan
~
I
r-
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1j
Conference of New Device Development and Salas
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Devalopmantl
Device Design
Clrcult'Deslgn
Product/Process Design
~
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CD
c
Design Review
I
-
I
~
I
J
l
Spec/Eng Support
Trial Run
1
~
I
-
c
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Characterization/
Evaluation
Rei
Evaluation
t
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I
J J
Conference on Mass ProductlonlSales
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~
.
:I
I
L
::;;
I
Preparation 01 Spec for
ManufacturlnglTestlQA
Production
Plan
J-r--(
~ ~
I
Incoming
Inspection
_1
I.
Warehousing
-I
r-
!
~...
:::;
'--
Use
Complaint
(Field Data)
Archive
Order
I
t::C
J
Receipt
Collection
~
(
~
Manufacturing
Electrical Test
Reliability Test
QA Insp/Packlng
Of~
Ship
I
Procurement OfJ
Parts/Materials
I
~_
Investlgatlon/AnalyslslCountarnieasure
Direction of Lot Traveled
(
1
Data Collection
~-
In·Process Quality Monitoring;
In·Process Inspection;
Environment and Equipment
Control/Calibration;
Lot Control; Corrective
Actions; Data Analysis/
Feedback; Etc.
83vO·69348
2-4
NEe
Reliability and Quality Control
Statistical Approach. Another approach to quality control
is the use of statistical analysis. NEC has been utilizing
statistical analysis at each stage of LSI production development, trial runs, and mass production in order to build
and maintain product quality. Some of the methods for
implementing this statistical approach are:
• Design of experiments
• Control charts
• Data analysis:
• Cp, Cpk study:
Figure 2. New Product Development Flow
• Circuit Design
• Mask Pattarn Layout
• Package Daalgn
Variance, correlation, regression,
multivariance, etc.
Variables and attributes data
(Normally. study is done on a
monthly basis)
fI
Process control sheets and other QC tools are used to
monitor various important parameters such as Cp, Cpk, X,
X. X-R, electrical parameters, pattern dimensions; bond
strength, test percentage·defects, etc.
The results of these studies are watched by the producJion
staff, QC Engineers, and other responsible engineers. If
any out-of-control or out-of-specification limit is observed,
quick action is taken in accordance with corrective action
procedures.
Implementation of Quality Control
Building quality into a product requires early detection of
possible causes of failure at each process step, then
immediate feedback to remove these causes. A fixed
station quality inspection is often lacking in immediate
feedback; it is therefore necessary to distribute quality
control functions to each process step-including the
conceptual stage. Following is a breakdown of the significant steps at which NEC has implemented these functions:
• Product development
• Incoming material inspection
• Wafer processing
• Chip mounting and packaging
• Electrical testing and thermal aging
• Outgoing material inspection
• ReliabiliJy testing
• Process/product changes
New Product Development Phase. The product development phase includes conception of a product, review of
the device proposal, physical element design and organization, engineering evaluation, and finally, transfer of the
product to manufacturing. Quality and reliabiliJy are considere~ at every step. The new product development flow
is shown in Figure 2.
2-5
NEe
Reliability and Quality Control
Design. Design plays an extremely important role in
determining the product quality and reliability. NEC believes that the foundation of device quality is determined at
the design stage. The four steps involved in the design of
LSI devices are circuit deSign, mask pattern layout, process and product manufacturing, and package design.
Design standards and the standardization of deSign steps
have .been established to maximize quality and reliability.
Design Review. After completion of the deSign, a design
review is performed.lnthis review, the design is compared
with design standards and other factors which influence
the reliability and quality. If necessary, modification or
redesign is then performed. NEC believes that the design
review is very essential for not only newly designed products but also for product modifications.
Trial Production/Evaluation/Mass Production. When
the design passes the design review successfully, a trial
run is carried out. The trial run is evaluated forthe products'
characteristics and quality/reliability.
Thorough evaluation is carried out by generating samples
in which process conditions-ones that cause characteristic factors to change in mass production-are varied
deliberately. Inaddition, reliabjlity tests are conducted for
durability, stress resistance, etc., to insure sufficient quality and reliability.
modes. The. results of these inspections are used to rate
the vendorsforfutl.lre purchasing.
In-Process· Qua·nty Inspections. Typical in-process
quality. inspections done at the wafer fabrication, chip
mounting and packaging, and device testing stage are
listed in Appendix 1Electrical Testing and Screening. A flowchart of the
typical infant mortality screening (when required) and
electrical testing is depicted in Figure 3.
At the first electrical test, DC parameters are tested according to the electrical specifications on 100% of each lot.
This is a prescreening prior to any infant mortality test. At
the second electrical test, AC functional tests as wei! as DC
parameter tests are performed on 100% of each lot. If the
percentage of defective units exceeds the limit, the lot is
subjected to rescreen. During this time, the defective units
undergo failure analysis, the resu.Hs of which are fed back
into the process through corrective actions.
Figure 3. Electrical Testing and Screening
DC Parameters
(Full AC/DC Teetlng
r--~---,-"'::=:::::o;r----I If No 1QO% Bum·ln)
If no problems are found at this stage, the product is
approved,after which mass production is possible.
"Whenever RequlrllCl
Prior to the transfer, the production Design Department
prepares a production schedule, including the reliability
and quality control steps relating to the production. Even
after the mass-production has started, the standards for
those production and control steps are always reexamined
for improvements.
DC Parameters,
AC Functional
Incoming Material Inspection. NEC has various programs to control incoming materials. Some are:
• Vendor/material qualification system
No
• Purchasing specifications for materials
• Incoming materials inspection
• Inspection data feedback
• Quality meetings with vendor
• Vendor audits
If any parts or materials are rejected at incoming inspection, they are returned to the vendor with a rejection
notification form which specifies the failure items and
2-6
Electrical,
Appearance, and
L-_--,_.,..----I Dlmenslone
NEe
Reliability and Quality Control
Outgol~g Inspection. Prior to warehouse storage, lots
are subjected to an outgoing inspection according to the
following sampling plan.
• Electrical test:
De parameters LTPD
Functional test LTPD
3%
3%
• Appearance:
-Major LTPD
Minor LTPD
3%
7%
Reliability Assurance Tests. Samples are continually
prior to shipment and subjected to monitoring relia?Ihty tests. They are taken from similar process groups, so
It may be assumed that the samples' reliability is representative of the reliability of the group.
-
Figure 4. Reliability Lffe (Bathtub) Curve
t~~en
Wearout
fI
Period
Random Failure Pe.1od
Tlme_
Reliability Testing
Reliability is defined as the characteristics of an item
expresse(l by the probability that it will perform a required
function l!J1der stated conditions for a stated period of time.
This involves the concepts of probability, the definition of
required function(s), and the critical time used in defining
the reliability.
.. '
.
Definition of a required function, by Implication, treats the
definition of a failure. Failure is defined as the termination
of the ability of a device to perform its required function. A
device is said to have failed if it shows the inability to
perform within guaranteed parameters as given in an
electrical specification.
Discussion of reliability and failure can be approached in
two ways: with respect to systems or to individual devices.
ImPortant considerations are the constant failure period,
the early failure (infant mortality) period, and overall reliability level.
With regard to individual (levices, areas of prime interest
incll!de specific failure mechanisms, failures in acceler~ted tests, and failures in screening tests.
The accumulation of normal device failure rates constitutes
the expected failure rate of the system hardware: the
probability that no device failures will occur in a system is
the pro~uct of each devi.ce's Probability that it will not fail.
The failure rate of system hardware is then the sum of the
failure rates of the components used to construct the
system.
Life Distribution
The fundamental ptinciplesof reliability engineering predictthat tl1e failure rate of a group of devices will follow the
well-known bathtub curve in Figure 4. The curve is divided
into three regions: infant mortality, random failures, and
wearout failures.
Infantrnortality, as th.e name implies, represents the earlylife failures of devices. These failures are usually associatedwith one or more manufacturing defects.
After some period of time, the failure rate reaches a low
value. Th.is is the random failure portion of the curve,
representing the useful portion of the life of a device.
During this random failure period, there is a decline in the
failure rate due tothe depletion of potential random failures
from the general population.
The wearout failures occur atthe end ofthedevice's useful
life. They are characterized by a rapidly rising failure rate
over time as devices wear out both physically and electrically.
TI1us, for a device that has a very long life expectancy
compared to the system which contains it, the areas of
concern will be the .infant mortality anel the random failure
portions of the bathtub curve.
Failure Distribution at NEe
In an effort to eliminate infant rnortalityfailures, NEe
subjects its products to production bum-I" wh~never necessary. This burn-in is perforli1ed at an elevated temperature for 100 percent of the lots involved and is designed to
remove the potentially defective units" . ...
To study the random failure population, integrated circuits
returned to NEe from the field undergo extensive failure
analysis at respective NEe Manufacturing Div!sions. Failure mechanisms are identified and (lata.fed back to cognizant Production and Engineering groups.
ThiS data coupled with in-line data is then used to introduce
corrective actions and quality improvement measures.
2-7
NEe
Reliability and Quality Control
After elimination of early devicefailures,a system will be
left to the random failure rate of its components. Thus, in
order to make proper projections of the failure rate of the
system in the operating environment, failure rates must be
predicted for the system's components.
Infant Mortality Failure Screening
Establishing infant mortality screening requires knowledge of the likely failure mechanisms and their associated
activation energies. The most likely problems associated
with infant mortality failures are generally manufacturing
defects and process anomalies. These defects and anomalies generally consist of contamination, cracked chips,
wire bond shorts, or bad wire bonds. Since these describe
a number of possible mechanisms, anyone of which might
predominate at a given time, the activation energy for
infant mortality varies considerably.
Correspondingly, the effectiveness of a screening condition-preferably at some stress level in order to shorten
the screening time-varies greatly with the failure mechanism. For example, failures due to ionic contamination
have an activation energy of approximately 1.0 eV. Therefore, a 15-hourstressat 125°C junction temperature would
be the equivalent ofapproximately 314 days of operation
at a Junction temperafure of 55°C. On the other hand,
failures due to oxide defects have an activation energy of
approximately 0.3 eV, and a 15-hour stress at 125°C
junction temperature would be the equivalent of approximately four day's operation at 55°C junction temperature.
As indicated by this situation, the conditions and duration
of Infant mortality screening must be strongly dependent
on the allowable .colT1pQnent, hence system, failureS in the
field, as well as the economic factors involved.
Empirical data gathered at NEC indicates that early failures (if any) occur after less than 4 hours of stress at 125°C
ambienttemperature. This fact is supported by the bathtub
curve created from the life test results of the same lots,
where the failure rate shows a random distribution as opposed to a decreaSing failure rate that runs into the random
failure .region.
Long.Term Failure Rate
NEC's long-term failure rate goal, based on the mask and
process deSign, is confirmed by life testing using the
following conditions:
• A minimum of 1.2 million device hours (= sample size x
test period) at 125°C should be accumulated to obtain
the accuracy necessary for predicting a failure rate of
0.02% per 1000 hours at 55°C with a 60% confidence
level.
• A minimum of 3 million device hours at 125°C should be
accumulated to obtain the accuracy necessary for
predicting a failure rate of 0.01% per 1000 hours at 55°C
with a 60% confidence level.
Accelerated Reliability Testing
NEC performs extensive reliability testirig both at preproduction and post-production level.s to insure that its
products meet the minimum expectations set by NEC.
Accelerated reliability testing results are then used to
quantitatively monitor the reliability.
As an example, assume that an electronic system contains
1000 integrated circuits and can tolerate 1 percent system
failures per month. The failure rate per component is:
1% Failures
= .0014 % Failures
720 Hours x 1000 Pcs.
1000 Hrs
or 14 FITs
To demonstrate this failure rate, note that 14 FITs correspond to one failure in about 85 devices during an operating test of 10,000 hours. It is quickly apparent that a test
condition is required to accelerate the time-to-failure in a
predictable and understandable way. The implicit requirement forthe accelerated stress test is that the relationship
between the accelerated stress testing condition and the
condition of actual use be known.
Whenever necessary,NEC haS adopted this Initial infant
mortality bum-in at 125°C as a standard production screening procedure. As a result, .the field reliability of NEC
devices is an order of magnitude higher than the goal set
for NEC's integrated circuit products. ,
.
A most common time-to-failure relationship involves the
effect of temperature., which accelerates many physiochemical reactions which may lead to device failure. Other
environmental conditions are voltage, current,. humidity,
vibration, or some combination of these. Appendix 2 lists
typical reliability assurance tests performed at NEC for
molded integrated circuits. Figure 5 shows the results of
some of these tests for various process types.
NEC believesit is imperative that failure modes associated
with infant mortality screens be understood andflxed at the
manufacturing level. If, such failures can b~ minimized or
elimfnated, and countermeasur.es appropriately monitored,
then such screens can be eliminated.
High-Temperilture Operating Life Test. This test is used
to accelerate failure mechanisms by operating devices at
an elevated temperature of 125°C. The data obtained is
translated to a lower temperature by using the Arrhenius
relationship.
'
2-8
tt1EC
Reliability and Quality Control
Figure 5. Typical Reliability Test Results
HTB
TM
PCT
NMOS
7/19113
(15 FIT)
1519315
0/11752
CMOS
3111892
(5.4 FIT)
217293
819476
TIC
Micro: 1
Memory:
[HTOL]
DRAM2
10110052
(19 FIT)
0/9958
0/5880
SRAM"
1/10421
2/8142
018768
1 MEGDRAM4
38114300
(115 FIT)
0/3634
1/3060
213506
(33 FIT)
1/1111
1/2995
1/1780
In some cases, an average activation energy is assumed
in order to accomplish a quick first order approximation.
NEC assumes an average activation enefgy of 0.7 eVfor
such approximations. This average value has been assessed from extensive reliability test results and yields a
conservative failure rate.
Since most semiconductor failures are temperature dependent, the Arrhenius relationship is used to normalize
failure rate predictions at a system operation temperature
of 55°C. It assumes that temperature dependence is an
exponential function that defines the probability of occurrence, andthatthe degradation of aperformance parameter is linear with time. The Arrhenius model includes'the
effects of temperature and activation energies of the
failure mechanisms in the following Arrhenius equation:
A = exp -EA(TJl - TJ2 )
Asic: 5
CMOS
ECl
1/4764
0/1080
(8.4 FIT)
BiCMOS
11895
011073
0/935
(18 FIT)
Information has been extracted from NEC Report Numbers:
1 TRQ.89.05-0030
2TRQ-89.01-0021
"TRQ.Q8.Q9.Q008
4TRQ.89-01-0020
5 TRQ.89-04-0025
k(TJ1 ) (TJ2 )
412680
0/141
. 011781
High-Temperature and High-Humidity Test~ Semicon·
ductor integrated circuits are highly sensitive to the effect
of humidity causing electrolytic corrosion between biased
lines. The high-temperature and high-humidity test is performed to detect failure mechanisms that are accelerated
by these conditions, such as leakage-related problems
and drifts in device parameters due to process instability.
High-Temperature Storage Test. Another common test
is the high·temperature storage test, in which devices are
subjected to elevated temperatures with no applied bias.
This test is used to detect process instability and stress
migration problems.
Environmental Tests. Other environmental tests are performed to detect problems related to the package, material, susceptibility to extremes in environment, and problems related to usage of the devices.
Failure Rate CalculationJPrediction
When predicting the failure rate at a certain temperature
from accelerated life test data, the activation energies of
the failure mechanisms involved should be considered.
This isdone whenever the exact cause offailures is known
through failure analyses results.
Where:
A = Acceleration factor
EA = Activation energy
TJl .. Junction temperature (in K)
at TAl = 55°C
TJ2 = Junction temperature (in K)
at TA2 = 125°C
k = Boltzmann's constant
= 8.62 x 1Q-6 eVIK.
Because the thermal resistance and power dissipation of
a particular device type cannot be ignored, junction
temperatures (TJl and TJ2) are used instead of ambient
temperatures (TA1 and TA2). We calculate junction
temperatures using the following formula:
TJ = TA + (Thermal Resistance) (Power Diss. at TA)
In orderto estimate long term failure rate, the acceleration
factor must be used to determine the Simulated test time.
From the high temperature qperating life test results,
failure rates can then be predicted at a 60% confidence
level using the following equation:
)(210 5
L=
2T
Where:
L = Failure rate in %/1000 hours
*)(2 = The tabular value of chi-squared distribution at a
given confidence level and calculated degrees of
freedom (2f + 2, where f =number of failures)
T = # of equivalent device hours
= (# of devices) x (# of test hours)
x (acceleration factor)
2-9
fI
NEe
Reliability and Quality Control
*Since the failures of concern here are the random, notthe
infant mortality failures (that is, the end of the downward
slope and the middle-constant-section of the bathtub curve
in Figure 4), )(2 is determined assuming a one-sided, fixed
time test.
Another method of expressing failures is in FITs (failures
in time). One FITis equal to one failure in 109 hours. Since
L is already expressed as %/1000 hours (10-5 failure/hr) ,
an easy conversion from %/1000 hours to FIT would be to
muHiply the value of L by 104 •
EXAMPLE: A sample of 960 pieces was subjected to
1000 hours 125°C burn-in. One reject was observed.
Given that the acceleration factor was calculated to be
34.6 using the Arrhenius equation, what is the failure rate
normalized to 55°C using a confidence level of 60%?
Express the failure rate in FIT:
Solution:
For n = 2f + 2 =2(1) + 2 = 4, X2 =4.046.
Then L
X 10
=~
2
5
(%/1000 hour)
= 0.0061
.
Therefore, FIT = 0.0061 • (104)
As mentioned previously, a design review is performed for
product modifications or changes. Once the· deSign is
approved, and processes altered (if necessary) for maximum quality, the device goes through qualification testing
to check the reliability. If the test results are acceptable,
the product is released for mass production.
Testing is also performed when only a process modification or change is made.
The typical qualification/process change tests are listed in
Appendix 3.
Failure Analysis
At NEC, failure analysis is performed not only on field failures, but also routinely on products which exhibit defects
during the production process. This data is closely checked
for correlation with the production process quality information, inspection results, and reliability test data. Information derived from these failure analyses is used to improve
product quality.
As there are a lot of failure mechanisms of LSI devices,
highly advanced analytical technologies are required to
investigate such failures. in detail. The standard failure
analysis flowchart relating to the returned products from
customers is shown in Appendix 4.
105
(%/1000 hr)
2 (# of dev.) (# of test hrs.) (acel. factor)
)(2
(4.046)
105
2(960) (1000) (34.6)
Product/Pl'ocess Changes
(0/. /1 000 hr)
°
= 61
NEC's Goals on Failure Rates
The reject rate at customer's incoming inspection, the
infant mortality rate, and the long term reliability, are all
monitored and checked against NEC's quality and reliability
targets (listed in Figure 6).
Figure 6. NEe Quality and Reliability Targets
Roject Rato at Cusiomor's
Incoming Eloct~cal·lnspectlon (PPM)
Memory
EClRAM
MOS
1988
1S0
SO
1990
lOa
SO
2-10
Gat,Arrays
iJCOM
Vear
Long Torm Ronability (FIT)
Memory
Gate Arrays
iJCOM
BICMOS
ECl
CMOS
EClRAM
MOS
lOa
1000
300
300
lOa
SO
100
SOO
200
1S0
80
SO
Infant Mortality (AT)
Momory
iJCOM
EClRAM MOS
Gato Arrays
BICMOS
ECl CMOS
BICMOS
ECl
CMOS
lOa
1000
300
1S0
lOa
lOa
1S0
1000
300
400
80
SOO
2S0
lOa
80
lOa
1S0
SOO
250
300
ttlEC
Summary and Conclusion
As has been discussed, building quality and reliability into
products is the most efficient way to ensure product
success. NEC's approach of distributing quality control
functions to process steps, then forming a total quality
control system, has produced superior quality and excellent reliability.
Prescreening, whenever necessary, has been a major
factor in improving reliability. In addition, monthly reliability assurance tests have ensured high outgoing quality
levels.
Reliability and Quality Control
The combination of building quality into products, effective
prescreening of potential failures, and monitoring of reliability through extensive testing, has established a singularly high standard of quality and reliability for NEC's largescale integrated circuits.
Through acompanywide quality control program, continuous research and development activities, extensive failure
analysis, and process improvements, this higher standard
of quality and reliability will continuously be set and maintained.
2-11
NEe
Reliability and Quality Control
Appendlxt
Typical QC Flowfor CMOS Fabrication
WAFER FABRICATION PROCESS QC FLOW (CMOS)
FLOW
PROCESS MATERIAL
IN-PROCESS INSPECTION/QUALITY MONITOR
Silicon Wafer
Incoming
Inspection
Reslstlvlly (sampling by 101)
Dimension (sampling by 101)
Visual (sampling by 101)
Wall
Formation
Oxldallon
Photo Lithography
Oxide Thickness (sampling by 101)
Allgnmenl and Elchlng Accuracy (sampling by 101)
Layer Resistance (sampling by day)
Ion Implantation
Field
Formation
Deposition
Photo Lithography
Deposit Thickness (sampling by lot)
Allgnmenl and Etching Accuracy (sampling by 101)
Oxide Thickness (sampling by lot)
Oxidation
Channel Slopper
Formation
Photo Lithography
Ion Implantation
Oxidation
Allgnmenl and Etching Accuracy (sampling by 101)
Layer Resistance (sampling by lot
Oxide Thickness (sampling by 101)
Gate
Formation
Deposition
Doping
Photo Lithography
Deposit Thickness (sampling by lot)
Layer Resistance (sampling by lot)
Alignment and Etching Accuracy (sampling by lot)
Gate Electrode Width (sampling by lot)
pin SD Formation
Photo Lithography
Alignment and Etching Accuracy (sampling by lot)
Layer Resistance (sampling by lot)
Ion Implantation
Anneal
Contact
Hole
Deposition
Photo Lithography
Deposit Thickness (sampling by lot)
Allgnmenl and Etching Accuracy (sampling by 101)
Metallization
Metal Deposition
Photo Lithography
Metal Thickness (sampling by run)
Alignment and Elchlng Accuracy (sampling by lot)
Parametric Test (sampling by 101)
Alloy
Passivation
Deposition
Photo Lithography
Deposit Thickness (sampling by lot)
Allgnmenl and Etching Accuracy (sampling by lot)
Wafer Sort
Contact Hole and Metallization Steps are Repealed Twice
83vQ-69:)gB
2-12
NEe
Reliability and Quality Control
Appendix 1
Typical QC Flow for PLCC Assemblyffest
The Check of Manufacturing Qualities
The Check of Manufacturing Conditions
Process/Materials
1
Sorted Wafers
2
Wafer Visual
3
Dicing
4
Break and Expand
5
Ole Visual Inspection
6
Lead Frames
Check
Items
Table Speed
01 Water
Blade Height
Wafer Break
Conditions
Frequency
Instrument
Checked
By
Checked
By
Check
Item
Frequency
Instrument
Wafer Visual
100%
(Naked Eye)
Operator
Microscope
with Filter
Eyepiece
(Naked Eye)
Operator
Every
Shift
Indicators
Gauges
P.C.
Sawing
Dimensions
Before
Running
Every
Shift
Indicators
Gauges
P.C.
Wafer Visual
100%
Die
Visual
Every Lot
Sampling
(Or 100%)
Microscope
Operator
Die Visual
Epoxy
Every
Magazine
(Naked Eye)
Operator
Every Shift
Microscope
Operator
Wafer Expand
Conditions
Die Attached
Conditions
Every
Shift
Indicators
Thermocouple.
P.C.
Potentiometer
Coverage
7
Die Attached
Temperature
Epoxy Cure
(Not Done for Gold
Ole Attached product)
Heat
Temperature
N2 Flow
Every
Shift
Indicators
Gauges
P.C.
Shear
Strength
Every
Shift
Dynamometer
Operator
8
Bonding
Conditions
Every
Shift
Indicators
P.C.
Visual
Every
Magazine
Microscope
Operator
Temperature
Every
Week
Thermocouple
and
Potentiometer
P.C.
Wire Pull
Test
Every
Shift
Tension
Gauge
Operator
Die
Visual
Every Lot
Sampling
(or 100%)
Microscope
Inspector
Visual
100%
(Naked Eye)
Operator
Visual
Every Lot
(Naked Eye)
Operator
~
FlneWlre
10
Wire Bonding
11
Pre-Seal Visual
Inspection
~
13
Molding Compound
Molding
Temperature
ofPeliet.
Expiration Date
Temperature
Profile of
Die Set
Every
Shift
Thermocouple
P.C.
Every Shift Thermocouple.
Potentiometer
P.C.
Preheat
Temperatue
Pressure
Cure Time
14
Mold Aging
Temperature
Every Shift
Indicator
P.C.
15
Deflashlng
Deflashing
Conditions
Every Shift
Indicators
P.C.
Titration
Tech.
Concentration Every Week
Density
Water Jet
Pressure
0
Plating
Plating
Conditions
Every Week Density Meter
Tech.
Every Day
Gauge
Tech.
Every Day
Indicators
P.C.
Titration
Tech.
Concentration Every Week
83VQ..6914OB
2-13
fI
ttlEC
Reliability and Quality Control
Appendix 1
Typical QC Flow for PLCC AssemblyfTest (Cont.)
The Check of Manufacturing Qualities
The Check of Manufacturing Conditions
Process/Materials
~~
~
Check
Items
Marking Ink
Marking
20
Mark Cure
21
Lead Forming
22
Final Assembly Inspection
23
1st Electrical Sorting
24
Burn-In (Whenever Necessary)
25
1st Electrical Sorting
26
Reliability Assurance Test
In-Warehouse Inspection
Check
Item
Frequency
Instrument
Checked
By
Visual
Every Lot
(Naked Eye)
Technician
Plating
Thickness
Every Lot
X-ray
Technician
Composition
Every Lot
X-ray
Technician
Solderability
Once/Day
(Naked Eye)
Technician
Marking
Conditions
Every Shilt
Indicators
P.C.
Visual
Every Lot
(Naked Eye)
Operator
Temperature
Every
Shilt
Thermocouple
P.C.
Marking
Permanency
Twice/Shilt
Automatic
Tester
Operator
Dimensions
Every Shilt
(Before
Running)
Test Jig.
Caliper
Operator
Visual
Every Lot
(Naked Eye)
Operator
Visual
Every Lot
Magnifying
Lamp
Operator
P.M. Check
28
Instrument
Plating Inspection
19
27
Frequency
Checked
By
Every Day
P.M. Jig.
Operator
Sample
Check
Before
Testing
Test
Samples
Operator
Burn-In
Conditions
Every
Batch
Indicator
P.C.
Every Day
P.M. Jig.
Operator
Before
Testing
Test
Samples
Operator
.Electrical
Characteristics
100%
ICTester
Operator
Electrical
Characteristics
100%
IC Tester
Operator
Electrical
Characteristics
Every Lot
IC Tester
inspector
Visual (Major)
Every Lot
(Naked Eye)
and
Microscope
Inspector
Visual (Minor)
Every Lot
(Naked Eye)
inspector
Every
Month
Every Day
P.M. Jig.
Before
Testing
Test
Samples
Warehousing
83vQ-6941B
2-14
NEe
Reliability and Quality Control
Appendix 2
Typical Reliability Assurance Tests
The life tests performed by NEe consist of high temperature
bias life (HTB), high temperature storage life (HTSL), high
temperature/high humidity (T/H) , and high humidity storage
life (HHSL) tests. Additionally, various environmental and
mechanical tests are performed. The table below shows
the conditions of the various life tests, environmental tests,
and mechanical tests.
Symbol
MIL·STD·883C
Method
Condition
Remarks
High Temperature
Bias Life
HTB
1005
TA = 125~, Voo specified per device type.
(Note 1)
High Temperature
Storage Life
HTSL
1008
TA .150~.
(Note 1)
High Temperature!
High Humidity
TIH
TA =85~, RH = 85%, Voo = 5.5 V.
(Note 1)
HHSL
TA = 85~, RH = 85%.
(Note 1)
Pressure Cooker
PCT
. TA=125~, P .2.3 atm.
(Note 1)
Temperature Cycling
TIC
1010
-
Lead Fatigue
C3
2004
90· bends. 3 bends whhout breaking.
(Note 2)
Solderability
C4
2003
230~,
(Note 3)
Soldering Heat!
Temperature Cycle!
Thermal Shock
C6
(Note 4)
1010
1011
260~,
Test Item
High Humidity
Storage LHe
65~
to
150~,
1 hr/cycle.
5 sec, Rosin Base Flux.
10 sec, Rosin Base Flux!
10-1 hr cycles, -65~to 150~1
15-10 min cycles, O~ to 100~
(Note 1)
(Note 1)
Notes:
(1) Electrical test per data sheet is performed. Devices that exceed the data
sheet limits are considered to be rejects.
(3) Less than 95% coverage is considered to be a reject.
(4) MIL·STD-750A, method 2031.
(2) Broken lead is considered to be a reject.
·2-15
II
ttlEC
Reliability and Quality Control
Appendix 3
New Product / Process Change Tests
Newly
Developed
Product
Shrink
Ole
New
Package
Wafer
Assembly
Test Item
Test Conditions
Sample Size
High Temp.
Operaling Lffe
See Appendix 2, l000H
201050 pes
Xl 10 3 lois
0
0
0
0
0
High Temp.
Siorage Life
T = 150"C (Plaslic),
175"C (Ceramic), l000H
101020 pes
Xl 103 lois
0
0
0
0
0
High Temp. and
See Appendix 2, l000H
2010 SO pes
Xl 10 3 lois
0
0
0
0
0
Pressure cooker
(Plastic Device)
See Appendix 2, 288H
101020 pes
Xl 103 lois
0
0
0
0
0
Thermal
Environmenlal
See Appendix 2
101020 pes
Xl 103 lois
0
X
0
X
0
Mechanical
Environmenlal
(Ceramic Device)
20G, 10102000 Hz
l500G, 0.5 ms
20000G, 1 min
10 10 20 pes
Xl 103 lois
0
X
0
X
0
Lead Faligue
See Appendix 2
Spes
Xl 103 lois
X
X
X
Solderabilfty
See Appendix 2
Spes
Xl 10 3 lois
X
X
X
ESD
(1)C=200pF,R=On
(2) C= 100pF, R= 1.5 Kn
20 pes
Xl 1031015
0
0
X
0
X
Long Term TIC
See Appendix 2, 1000 cy
10 10 SO pes
Xl 1031015
0
0
0
0
0
Humid~y Bias Lffe
(Plastic Device)
O-Performed
2-16
X- Perform if Necessary
- - Nol Performed
NEe
Reliability and Quality Control
Appendix 4
Failure Analysis Flowchan
t-----INFORMATION
Failure mode:
SHuatlon, When Failure
Appeared:
,te.
DClFunctlon Testing
by Tester Curvet racer
Ves
Test correlation
May be Needed
'--"'----'
case:
Due to the
X-ray Fluoroacope,
Hermetical Test, Dew-polnt Test,
Curvet racer Check, etc.
Decapsulation, Internal Visual
Check, Electrical Measurement,
ClrcuH Analysis
Etching the Passivation, etc.
SEM, XMA, Cros.oS.ctlon, etc.
Estimation of Cauese
Countermeasures
Corrective Action
2-17
Reliability and Quality Control
2-18
NEC
NEe
4~BitMicrocomputers
J..lPD7500 Series:
'I
3-1
II
tYEe
4-Bit, CMOS Microcomputers
Seotion 3
p.PD7qOO Series:
4-Bit, CMOS Microcomputers
"PD7502/03
3-3
4-Bit, Single-Chip CMOS Microcomputers
With LCD Controller/Driver
"PD7507108
3-19
4-Bit, Single-Chip CMOS Microcomputers
"PD7507H/08Hn5CG08HE
3-39
4-Bit, Single-Chip CMOS Microcomputers
"PD7527A/28An5CG28E
3-53
4-Bit, Single-Chip CMOS Microcomputers
With FIP Driver
"P07533n5CG33E
3-65
4-Bit, Single-Chip CMOS Microcomputers
With A/D Converter
"PD7537A/38An5CG38E
3-85
4-Bit, Single-Chip CMOS Microcomputers
With FIP Driver
"PD7554/54A/64/64A
3-99
4-Bit, Single-Chip CMOS Microcomputers
With Serial 1/0
"PD75P54/P64
3-121
4-Bit, Single-Chip, One-Time Programmable
(OTP) CMOS Microcomputers With Serial 1/0
"PD7556/56A/66/66A
3-141
4-Bit, Single-Chip CMOS Microcomputers
With Comparator
"PD75P56/P66
4-Bit, Single-Chip, One-Time Programmable
(OTP) CMOS Microcomputers With
Comparator
3-2
3-163
pPD7002J'03
t-IEC
4-Bit, Single-Chip
CMOS Microcomputers
With LCD Controller/Driver
NEe Electronics Inc.
Description
The IlPD7502 and IlPD7503 4-bit, single-chip CMOS
microcomputers have advanced fourth-generation architecture with the functional blocks necessary for a
single-chip controller, including an 8-bit timer/event
counter, an 8-bit serial I/O, and an LCD controller/
driver.
The instruction set includes the following types of
instructions: addressing, table look-up, bit manipulation, vectored jump, auto increment or decrement
data pointer, and conditional skip. These instructions
maximize use offixed program memory space.
o RC oscillation clock
o Crystal oscillation clock
o 2.5 to 6.0 V operating voltage
o CMOS technology
Ordering Information
Package Type
pPD7502GF-12
64-pin plastiC CFP
410 kHz
pPD7503GF-12
64-pin plastiC CFP
410 kHz
Features
o 92 powerful instructions
o Program ROM
o
o
o
o
o
o
o
o
- IlPD7502: 2048 x 8-bit
- IlPD7503: 4096 x 8-bit
Data RAM
-IlPD7502: 128 x 4-bit
- IlPD5703: 224 x 4-bit
Interrupts
- External: INTO, INT1
- Internal: INTT (timer/event counter)
INTS (serial interface)
8-bit timer/event counter
- Based on crystal oscillation
- External event counter (prescale option by 64)
Serial interface
LCD controller/driver
- Programmable multiplexing mode: triplex,
quadruplex, or pseudo-static
- 4 common lines (COM o-COM3)
- 24 segment lines (SO-S23)
Standby modes: stop, halt
Data retention mode
I/O ports
- 3-bit input port
- 4-bit input port
- 4-bit output port
- Two 4-bit I/O ports with 8-bit capability
- 4-bit I/O port with each bit configurable as an
input or output
50270 (NECEL·538)
II
Pin Configuration
Both devices are manufactured with the CMOS process
and have a maximum power consumption of 900llA at
5 V and 300 IlA at 3 V. Halt and stop modes further
reduce power consumption.
These devices are ideal for a wide range of solar- and
battery-powered applications.
Max Frequency
of Operation
Part No.
64 63 62 61 60 59 58 57 56 55 54 53 52
Ne
1
P32
2
o
POaiSI
POo/SO
6
P63
510
P62
9
P61
10
S11
"P07502/03
S12
P60
11
P53
12
$13
514
P52
13
S15
P51
14
S16
PSo
15
$17
P43
16
518
P42
17
519
P41
18
520
P40
19
S21
20 21 22 23 24 25 26 27 28 29 30 31 32
83-003429A
3-3
ttlEC
pPD7502/03
Pin Identification
Status of Unused Pins
Symbol
No.
Function
Name
Pin Connection
1
NC
No connection
CL2
Open
2-4,64
P33-P30
4-bit output port 3
Xl
VSS
5-7
P03/S1
P02/§Q,.
POl/SCK
3-bit input port O,or
serial I/O interface
X2
Open
Vss or Voo
8-11
P63-P60
4-bit .1/0 port 6
P01/SCK
P02/S0
P03/S1
12-15
P53-P50
4-bit I/O port 5
P10/INTO
Vss
16-19
P43-P40
Hit I/O port 4
P11-P13
Vss or Voo
20,21
X2, Xl
Crystal clock/external event
input port X
P30-P33
Open
22
Vss
Ground
Input mode: Vss or Voo
Output mode: Open
23-25
P40-P43
P50-P53
P60-P63
VLCD3-VLCOl
LCD bias supply inputs
26,58
Voo
Positive power supply
27-30
COM3-COMo
LCD backplane driver outputs
31-54
S23-S0 .
LCD segment driver outputs
55
INTl
External interrupt
56
RESET
RESET input
57,59
CL1, CL2
System clock input
60-63
P13-P11,
P10llNTO
4-bit input port 1, or
external interrupt INTO
3-4
INn
Vss
SO-S23
COMO-COM3
VLC01- VLC03
Open
t-fEC
pPD7502/03
Pin Functions
P03/SI, P02/S0, P01/SCK [Port 0 or Serial
Interface]
This port can be configured as a 4-bit parallel input
port 0 or as the 8-bit serial I/O interface under control
of the serial mode select register. The serial interface
consists of the serial input (SI), the serial output (SO),
and the serial clock (SCK), which synchronizes data
transfer.
P13-P11, P10/iNTO [Port 1 or Interrupt]
4-bit input port 1. Line P10 is shared with external
interrupt INTO, which is a rising edge-triggered interrupt.
P33-P30 [Port 3]
4-bit, latched three-state output port 3.
P43-P40 [Port 4]
4-bit input or latched three-state output port 4. Can
perform 8-bit I/O in conjunction with port 5.
P53-P50 [Port 5]
4-bit input or latched three-state output port 5. Can
perform 8-bit I/O in conjunction with port 4.
INT1 [Interrupt]
This external interrupt is a riSing edge-triggered
interrupt latched by CL.
RESET
A high-level input to this pin initializes the pPD7502/
7503.
X2, X1 [Crystal Clock/External Event Input Port X]
For crystal clock operation, connect a crystal oscillator
circuit to input X1 and output X2. For external event
counting, input external event pulses to X1 and leave
X2 open.
CL 1, CL2 [System Clock Input]
Connect an 82-kO resistor across CL 1 and CL2, and a
33-pF capacitor from CL 1 to Vss. Or, connect an
external clock source to CL 1 and leave CL2 open.
VLC03-VLC01 [LCD Bias Voltage Inputs]
LCD bias voltage supply inputs to the LCD voltage
controller. Apply appropriate voltages from a voltage
ladder connected across VDD.
VOO
P63-P60 [Port 6]
4-bit input or latched three-state output port 6. The port
6 mode select register configures individual lines as
inputs or outputs.
COM3-COMO [LCD Backplane Driver Outputs]
Positive power supply. For proper operation, apply a
single voltage from 2.5 to 6.0 V.
Vss
Ground.
LCD backplane driver outputs.
S23-S0 [LCD Segment Driver Outputs]
LCD segment driver outputs.
3-5
II
fttIEC
pPD7502/03
Block Diagram
SCK/POl
INT1
X2
Xl
INTO/P1o
SI/P03
SO/P02
H [4)
Program Memory
2048 x 8 Bits [7502)
4046 x 8 Bits [7503)
Instruction
Decoder
Data Memory
128 x 4 Bits [7502]
224
x 4 Bits (7503]
LCDCL
System
Clock
Generator
CLl
CL2
LCD Controller/Driver
Standby
Control
t
VOO
t
VSS
t
RESET
COMO·COM3
VLCD1, VLCD2,
VLC03
83-0034308
See figures 1 through 8 for additional block diagram
details.
Figure
1
2
3
4
5
6
7
8
3-6
Title
Data Memory Map
Program Memory Map
Interface at Input/Output Ports
Clock Control
Timer/Event Counter
Interrupt Control
Serial Interface
LCD Controller/Driver
NEe
Figure 1.
pPD7502/03
Figure 2.
Data Memory Map
Address
[D'Clma~
='J
Addre..
,..-_ _ _ _ _ _ _ _,
Program Memory Map
Add ....
[Decimal]
MSa
LCD Segment Data
Storage Area
0
7
8
Addre..
[HexJ
LSB
5
4
3
2
1
0
DOOH
:: 1 - - - - - - - - - - 1 ~~=
RESET Pulse Vectors Program
Execution to Add ..... DOH
INTT [Internal Timer/Event
16
010H
32
020H
INTO/S [Extemallnterrupt or
Serial Interface Interrupt]
Vectors Execution to 020H
48
030H
INTI [Extomal InterruptI J
Vectors Execution to O3OH
~
~ ...
I:i... ....!!o
192
OCOH
~
207
208
OCFH
ODOH
255
OFFH
1023
1024
3FFH
4DOH
,-2047
2048
7FFH
800H
<--4085
FFFH
Counter Interrupt] Vectors
Execution to 010H
.
Q
.
1~ ~--------~:=
~
0
pPD7503
l..
~
0
LHL T InltruCUon
Reference Table
CALT Instruction
Reference Table
La.t Addre.s tor
CALL Instruction
Entry [pPD7503J
223 1...-_ _ _ _ _ _ _.....1 DFH
83-003432A
83-003431A
3-7
ttiEC
pPD7502/03
Figure 3.
Interface at Input/Output Ports
Type A
P11, P12, P13
Type E
P02/S0, P40-P43, P50-P53, P60-P63
Datall:
Voo
Voo
P·ch
Inputl
Output
Output
Disable
Vss
VDD
Vss
Type B
INT1, P03/SI, P10/INTO, RESET
~Input
Typ!!.L
P01/SCK
Type 0
P30·P33
Datall:
Vss
VOD
Output
Datall:
VDD
Inputl
Output
Output
Disable
Output
Disable
Vss
Vss
In -----<0<
83-003859C
3-8
t-IEC
Figure 4.
pPD7502/03
Clock Control
Internal Bus
·Command execution
Clock Mode Register
MPX
Presealer 1
CL
(1/4)
Presealer 2
~/64)
I---'-.,----~ ~~ ~~ntrolier/Drl.er)
X--~--------__---------------+--~--I_-'
Clock Mode Register
CM1 CMO
Count Pulse
CL x
2~
X x
-i4
LCD Clock
CLX·2~6
Xx
X
CL x
X
Xx
1
64
>-------------------------------- ~mer/E..nt counter)
1
256
1
64
83-oo3321B
Figure 5.
·TCNTAM
Timer/Ellent Counter
--------.-------o-t
INTT
I--~---- (To Interrupt Circuit)
CP-----.....
Count Hold
Circuit
I--+----~ ~u;.~.llnt.rI.c.)
·Command Execution
"TIMER
RESET
63-0033228
3-9
t\'EC
j.tPD7502/03
Figure 6,
Interrupt Control
C>--I-====-----I
INTI
INTS
PIO/INTO o--t--ILJ
SIO'--1'-~
INTT------L~J-j;;;;rj!"~l-+-+-+----L.....f
Standby
"Command Execution
Release
83-0034338
Figure 7,
Serial Interface
'IP
'IPL
PO:vSI ~-------I:>---4-++-+I
P02/S0o----_~-----+-<..._--------+----------...J
PO,/SCK O - - - - - i
'-'....Jo-+-- TOUT
F----¢
RS F/F
--+---. ~oT~nt.rruPt Circuit)
R ....
.. Command Execution
¢ System Clock
S ....- - - - - - 'SIO
83-0038056
3-10
ttlEC
Figure 8.
pPD7502/03
LCD Controller/Driver
OP, OPL (Command Execution)
Data
Memory
LCD CL
Timing Controller
"""-T--r-ir-'-~r--,--T-'-
Multiplexer
5,
Multiplexer
So
VLCD3
VLCD2
VLCD'
COM3 COM2 COM, COMO
COMo·COMa Outputs (Type G)
..l...
P.ch
.-L
P-ch
T
N·ch
OUT
LCD Voltage Ladder Connections
T
Voo
R
C
If--
VLCD1
R
Jf-
VLCD2
R
VLCD3
,....
R~
Jf-
N·ch
50-523 Outputs (Type H)
...L P-ch
~-----,
~OUT
ill
T
N-ch
VSS
;;
83-00332SC
3-11
t-iEC
pPD7502/03
Absolute Maximum Ratings
Capacitance
TA = 25°C
TA=2SoC;Voo=OV
-0.3 to H.O V
Power supply voltage, VOO
All input and output voltages
-0.3 V to VOO + 0.3 V
Output current high, 10H
Per pin
Total, output ports
-17 mA
-20mA
Output cUrrent low, IOl
Per pin
Tdtal, output ports
17 mA
55 mA
Limits
Parameter
Symbol
Min
Typ
Max
Unit
Input
capacitance
CI
15
pF
Output
capacitance
Co
15
pF
1/0
. capacitance
CIO
15
pF
Test
Conditions
Ie = 1 MHz
Unmeasured
pins returned to
Vss
-10 to HO°C
Operating temperature, TOPT
-65 to +150°C
storage temperature, TSTG
Comment: Exposing the device to stresses above those Iisted~in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operat!onal sections of this specification.
I;:xposure to absolute maximum rating conditions for extended
periods may affect device reliability.
DC Charactf"istics 1
For VDD
= 2.5 to 3.3 Volts
TA = -10 to +7QOC
Limits
Parameter
Symbol
Input voltage, high
VIHl
O.B VOO
VIH2
VOO - 0.3
VIHOR
Input voltage, low
VIL1
VIl2
Output voltage, high
VOH
Output voltage, low
VOL
Input leakage current, high
IUHl
Min
Typ
Test
Conditions
Max
Unit
VOO
V
VOO
V
CL1, Xl
0.9 VOOOR
VOOOR + 0.2
V
RESET, data retention mode
0
0.2 VOO
V
Except CL 1, Xl
0
0.3
V
CL1, Xl
Except CL1, Xl
V
10H = -BO/lA
0.5
V
10l
3
/lA
VDO - 0.5
=350/lA
Except CL 1, Xl; VIN = VOO
IUH2
10
/lA
CL1, Xl; VIN = VOO
Input leakage current, low
IUL1
-3
/lA
Except CL 1, Xl; VIN = 0 V
IUL2
-10
/lA
CL1, Xl; VIN = 0 V
Output leakage current, high
IlOH
3
/lA
Vo = Voo
-3
/lA
Vo=OV
Output leakage current, low
IlOl
Supply voltage
VOOOR
Supply current
1001
1002
1000R
3-12
V
2.0
Data retention mode
50
250
/lA
Normal operation, Voo = 3 V ± 10%;
R = 240 kn ±2%, C= 33 pF ±5%
35
230
/lA
Normal operation, VOO = 2.5 V;
R = 240 kn ±2%, C= 33 pF ±5%
0.3
10
/lA
Stop mode, Xl = 0 V; VOO = 3 V ±10%
0.2
10
/lA
Stop mode, Xl = 0 V; VOD = 2.5 V
0.2
10
/lA
Data retention mode, VonOR = 2.0 V
t\'EC
pPD7502/03
DC Characteristics 2
For Voo = 2.7 to 6.0 Volts
TA = -10 to +70°C
Limits
Symbol
Input voltage, high
VIH1
VIH2
VIHOR
0.9 VOOOR
VOOOR + 0.2
VIL1
0
0.3 Voo
V
Except CL 1, X1
VIL2
0
0.5
V
CL 1, X1
VOH
VOO -1.0
V
10H = -1.0 rnA, VOO = 4.5 to 6.0 V
VOO - 0.5
V
IOL = -100 JiA
V
10L = 1.6 rnA, VOO = 4.5 to 6.0 V
Input voltage, low
Output voltage, high
Output voltage, low
VOL
Input leakage current, high
ILlH1
Input leakage current, low
Min
Typ
Test
Conditions
Parameter
Max
Unit
0.7 VDO
VOO
V
VOO -0.5
VOO
V
0.4
Except CL 1, X1
CL1, X1
RESET, data retention mode
0.5
V
3
JiA
ILlH2
10
JiA
CL1, X1
ILlL1
-3
JiA
Except CL1, X1; VI = 0 V
CL 1, X1
IOL = 400JiA
Except CL1, X1; VI = VOO
ILlL2
-10
JiA
Output leakage current, high
ILOH
3
JiA
Va =Voo
Output leakage current, low
ILOL
-3
JiA
Vo=OV
Output impedance (1)
ReaM
3
5
kn
COMo-COM3; VOO = 4.5 to 6.0 V
5
15
kn
COMo-COM3
15
20
kn
SO-S23; VOO = 4.5 to 6.0 V
20
60
kn
SO-S23
6.0
V
Data retention mode
300
900
JiA
Normal operation, VOO = 5 V ± 10%;
R = 82 kn ± 2%, C = 33 pF ± 5%
70
300
JiA
Normal operation, VOO = 3 V ± 10%;
R = 160 kn ± 2%, C = 33 pF ± 5%
Rs
Supply voltage
VOOOR
Supply current
1001
1002
1000R
2.0
1.0
20
JiA
Stop mode, X1 = 0 V; VOO = 5 V ± 10%
0.3
10
JiA
Stop mode, X1
0.2
10
JiA
Data retention mode, VOOOR = 2.0 V
= 0 V; VOO = 3 V ± 10%
Note:
(1) VLCD = 2.7 V to VDD
VLCD1 = VDD - (1/3) VLCD
VLCD2 = VDD - (2/3) VLCD
VLCD3 = VDD - VLCD
3-13
ft(EC
pPD7502/03
AC Characteristics 1
For Voo = 2.7 to 6.0 Volts
TA=-10to+70°C
Limits
Test
Conditions
Parameter
Symbol
Min
Typ
Max
Unit
System clock frequency
fcc
150
200
240
,kHz
Voo = 5 V ±10%; R= 82 kn ±2% (Note 1)
75
100
120
kHz
Voo = 3 V ±10%; R= 160 kn ±2% (Note 1)
75
135
kHz
R= 160 kn ±2% (Note 1)
10
410
kHz
Cll. external clock. 50% duty; Voo = 4.5 to
6.0 V
10
125
kHz
Clf. external clock. 50% duty; Voo = 2.7 V
0.2
IlS
Clf. external clock
1.2
50
IlS
Cll. external clock; Voo = 4.5 to 6.0 V
4.0
50
IlS
Cll. external clock; Voo = 2.7 V
Ic
System clock rise and lall
time
tCR. tCF
System clock pulse width
tCH. tCl
Counter clock.lrequency
Ixx
25
50
kHz
XI. X2. crystal oscillator
Ix
0
410
kHz
XI. external pulse input. 500/0 duty;
Voo = 4.5 to 6.0 V
0
125
kHz
XI. external pulse input. 50% duty;
Voo = 2.7 V
0.2
IlS
XI. external pulse input
XI. external pulse input; Voo ;"4.5 to 6.0 V
Counter clock rise and lall
time
tXR. tXF
Counter clock pulse width
tXH. tXl
SCK cycle time
tKCY
SCK pulse width
SI setup time to SCK
tKH. tKl
t
SI hold time after SCK
t
SO delay time after SCK
l
32
1.2
IlS
4.0
115
XI. external pulse input; Voo = 2.7 V
3.0
Il S
SCK as input; Voo = 4.5 to 6.0 V
8.0
IlS
SCK as input
4.9
IlS
SCK as output; Voo = 4.5 to 6.0 V
16.0
IlS
SCK as output
1.3
Il S
SCK as input; Voo = 4.5 to 6.0 V
4.0
pS
SCK as input
2.2
IlS
SCK as output; Voo = 4.5 to 6.0 V
8.0
Il S
SCKas output
tSIK
30D
ns
tKSI
450
tKSO
ns
850
ns
1200
ns
INTO pulse width
tIOH. tlOl
10
INTI pulse width
t11H. tl1l
(Note 2)
IlS
RESET pulse width
tRSH. tRSl
10
pS
RESET setup time
tSRS
0
ns
RESET hold time
tHRS
0
ns
Notes:
(1) RC network at CL1 and CL2; C = 33 pF ±5%.I.Il.C/ocl;r;; 60 ppm.
(2) 2 x 103 .;- Icc or Ie in kHz.
3-14
IlS
Voo = 4.5 V to 6.0 V
t-IEC
pPD7502/03
AC Characteristics 2
For VDD = 2.5 to 3.3 Volts
TA = -10 to +70°C
Limits
Parameter
Symbol
Min
System clock frequency
fcc
50
Max
Unit
80
kHz
R= 240 kn ±2'10 (Note 1)
64
77
kHz
VDD = 2.5 V; R = 240 kn ±2'10 (Note 1)
80
kHz
CL1, external clock, 50% duty
0.2
ps
CL1, external clock
50
ps
CL1, external clock
50
kHz
Xl, X2, crystal oscillator
80
kHz
Xl, external pulse input, 50% duty
0.2
ps
Xl, external pulse input
50
fc
10
System clock rise and fall
time
tCR, tCF
System clock pulse width
tCH, tCl
Counter clock frequency
fxx
25
fx
0
Test
Conditions
Typ
6.25
32
Counter clock rise and fall
time
tXR, tXF
Counter clock pulse width
tXH, tXl
6.25
ps
Xl, external pulse input
tKCY
12.5
ps
SCiras input
25
ps
SCK as output
6.25
ps
SCKas input
11.5
ps
SCK as output
SCK cycle time
SCK pulse width
51 setup time to SCK
. tKH, tKl
t
tSIK .
51 hOld time after SCK t
SO delay time after SCK
p.S
tKSI
l
II
p.S
2
tKSO
p.S
INTO pulse width
tlOH, tlOl
30
p.S
INTI pulse width
t11H, tl1l
(Note 2)
ps
RESET pulse width
tRSH, tRSl
30
p.S
Notes:
(1) RC network at CL1 and CL2; C = 33 pF ±5%,lllC/oCI;;a; 60 ppm.
(2) 2 x 1()3 ·;-fcc or fc in kHz.
Recommended Rand C Values for System
Clock Oscillation Circuit
TA = -10 to +70°C
Supply Voltage Range
Recommended
Values (Note 11
Frequency Range
4.5 to 6.0 V
R=82kn±2%
150 to 250 kHz,
200 kHz typical
2.7 to 3.3 V
R=160kn±2%
75 to 120 kHz,
100 kHz typical
2.7 to 6.0 V
R=160kn±2%
75 to 135 kHz
2.5 to 3.3 V
R=240kn±2%
50 to 80 kHz
2.5 to 6.0 V
R=240 kn±2%
50 to 85 kHz
Note:
(1) C = 33 pF ±5%, IllC/oCI$ 60 ppm.
3-15
1tt{EC
PPD7502/03
Timing Waveforms
Timing Measurement Points
Voo
'==X0.7VDD
0.3 VDD
=
External Interrupts
2.7 to 6.0 V
'IlI.1 Polnls
0.7VDDX
0.3 VDD
' -_ __
INTO~IIOLJ=IIOH-=(
INn
---X
VDD = 2.5
0.8VDD
~111L=r=I"H~
to 3.3 V
'IlI.1 Polnls
O.8VDD~
83-003317A
~0=.2~V~D~D_ _ _ _ _ _ _~0=.2~V~D~D
83-003314A
Reset
Clock Timing
RESET
~IRSL=r=IRSH~
1-----ll1c-----I
83-003316A
CL
Input
Data RetentlDn Mode
Data Retention Mode
XL
Input
VDD
RESET
83.Q02917A
Serial Interface
SI--+----{
so
valid Oulpul Dala
V
'-------"-
83-003316A
3-16
VDDDR
IHDR
NEe
pPD7502/03
Operating Characteristics
TA
= 25°C
IC vs Voo [External Clock]
IccvsVOO
500
I
400
"
~
~,
I t = 25'C]-
~
-
250 ; - -
!
200
-
i
150
-
c
33 PFJ;
---
R
---.-
g 100
U
go
~
~
50
'1
--. -
R
Defined
Operating Voltage
< 12: Ie = _!_
21,
.!!
160 kCl
"
-,
E
!
240kCl-
~
~
1;
ij
10
II
,o
i1l
2
Supply Voltage Voo [V]
Supply Voltage Voo {V]
ICC
VS
R
Ix
SOD
.."
I
J,!
f; 200
c
0
f
IL
C
100
cl
SO
1
VD~=5~
-
I i
ITA L 5 ' c l -
~
.
~
R
f
i1l
500
~
_
,o
100 vsVOO
U
1-I
••
CL2
1000
50
~
Q
C=33pF
-----+=....:J;::;~~~~
100
182 kCl]
HALT 1160
kCl]
HALT 1240 kCl]
50
~
C
~
J C --1""----__ ______ -----r----r-'
I--________-+-__
. ________+
182 kCl]
+----+--:::::;;0011160 kCl]
1240 kCl]
500
Voo=3V,
~-----
Defined
Operating Voltage
10
TA
R=160kCl
1
/
Supply Voltage Voo [V]
!
-------- -----r-..!!..':..!~'.!...
~ 200~--------_+-----------r------~~~~~~~~
(
-------- -----r----£c
~Ll
~ 100 -
r'
212
1:
"
250r---------~-----------r----------r-7.V~D-D--~5~V~,--'
R
t1>t2:fx=~
ITA = 25'C]
21,
Resistance R [kel]
150
x'~
,..,
~
ij
200
VS
-11--1
g
I I
ICC
VOO [External Clock]
~
u
~
100
12
VS
I
t1t2:lc= ~.
100
IL
----- --- ----- --
~
0
~
R-82kCl
ITA = 25'C]
CL'~
N
~
1
'2
-11--1
400
J,! 300
go
1000
10
3
t,
-----~----
0
__________+r-_'VDD = 2.5 V,R=240kCl
en
~
p_pm~__________-L__________L-________~~
0.5
OL-A_C/_'_C_900
___
-25
25
Operating Temperature TA rOC]
50
75
0.1
0
Supply Voltage VDD IV]
3-17
NEe
IlPD7502/0~
Operating Characteristics (cont)
1001 vs fcc
IOH Vs VOH
-6
500
~
0
E
&
":E
0
go
i
0
C
"
!
~
J
400
300
33pF
J:
52
R
"'S
.
-4
-3
~
200
0
§
"i.
-5
.§.
100
~
~
-2
;:
-1
-§,
0
2
0
50
100
150
200
250
300
High~Level Output Voltage VOH
System Clock Oscillation Frequency fCC [kHz]
1001 vs TA
20
~
0 400
E
300
-
~
~
0 200
~
"...
.§.
&
0
-
-
.
c3
52
C
~
0
_ _- , - - - VDD
~
~
R
.
0.
Voo
II)
=jV' R= 160kO
~
l
0
...I
~
2
25
Operating Temperature T A [OC]
3-18
1 _ _ _- - . . . ,
50
VDD
"'S
Voo = 5 V, R = 82 kQ
C. 100
-25
~
-
~
J
33pF
o
[V]
IOL vs VOL
500
go
VDD~3V
~
II)
":E
_.-1-----...,
75
Low-Level Output Voltage VOL
IV]
2.5 V
~
3V
t\fEC
pPD7507/08
4-Bit, Single-Chip
CMOS Microcomputers
NEe Electronics Inc.
Description
Features
The pPD7507 and pPD7508 4-bit, single-chip CMOS
microcomputers have the pPD7500 series architecture.
The subroutine stack is implemented in RAM for
greater nesting depth and flexibility.
D Single chip microcomputer
D Program ROM
- pPD7507: 2048 x 8-bit
- pPD7508: 4096 x 8-bit
- pPD75CG08: piggyback EPROM
D Data RAM
- pPD7507: 128 x 4-bit
- pPD7508: 224 x 4-bit
- pPD75CG08: 224 x 4-bit
D 8-bit timer/event counter
D Four 4-bit general purpose registers
D Four vectored, prioritized interrupts
D Executes 92 instructions of pPD7500 series A
instruction set
D 5 ps instruction cycle/400 kH.z external clock
D Two standby modes
D 321/0 lines
D Low-power HALT and STOP modes
Thirty-two I/O lines are organized into eight 4-bit
ports: input port/serial interface port 0, output ports 2
and 3, and I/O ports 1, 4, 5, 6, and 7.
The pPD7507 and pPD7508 execute 92 instructions of
the pPD7500 series A instruction set with a 5-ps
instruction cycle time.
Maximum power consumption is 900 pA at 5 V, less in
the HALT and STOP low-power modes.
The pPD75CG08E is a piggyback EPROM prototyping
chip that is pin-compatible withpPD7507 andpPD7508.
A 2716 inserted into the top of the pPD75CG08E
emulates the pPD7507's ROM. A 2732 emulates the
pPD7508's ROM. When emulating the pPD7507, the
user must take care to use only the first128 RAM
locations. Although the pPD7507 and pPD7508 can
operate over a range of 2.5 to 6.0 V, pPD75CG08E
operation is limited to 5 V ±10%.
.
Table 1 summarizes the differences among pPD7507,
pPD7508 and pPD75CG08E.
TiJbl.1_
Featurea Comparison
IIPD75CGDBE
IIPD75D7fl508
Program memory
2K x 8 EPROM (2716)
4K x 8 EPROM (2732)
2K x 8 masked ROM (7507)
4K x 8 masked ROM (7508)
Data memory
224 x4
128 x 4 (7507)
224 x 4 (7508)
Data retention
mode
No
Yes
Power supply
5V±100/0
2.7 to 6.0 V
Package types
4O-pin ceramic
piggyback DIP
4O-pin plastic DIP
4Q.pin plastic shrink DIP
52-pin plastic QFP
50271 (NECEL-542)
Ordering Information
·Part Number
Packlge Type
MIX Frequency
01 Operation
IIPD7507C
4O-pin plastic DIP,
410 kHz
IIPD7507CU
4O-pin plastic shrink DIP
410 kHz
IIPD7507GC-OO
52~pin
plastic QFP
410 kHz
IIPD7508C
4O-pin plastic DIP
410 kHz
IIPD7508CU
4O-pin plastic shrink DIP
410 kHz
IIPD7508GC-OO
52-pin plastic QFP
410 kHz
IIPD75CG08E
4O-pin ceramic piggyback DIP
410 kHz
• A 3-digit mask identification code is added to the part number by
NEe at the time of code verification.
3-19
NEe
IlPD750:7/08
Pin Configurations
52-Pin Plastic QFP
40-Pin Plastic DIP and Plastic Shrink DIP
If If-
Xl
X.
P201PSTB
P2,/PTOUT
P2.
0
<.>
Z
P2,
P4.
RESET
P53
P52
NC
P12
Cl'
NC
P13
P5,
NC
X2
P3.
P3,
P5.
VDD
P63
NC
P32
P33
P7.
P7,
P6.
P6,
Cl2
Vss
INn
P43
P7.
P02/S0
PO,/SCK
P6.
P21/PTOUT
P20/PSTB
VDD
X,
POa/INTO
NC
P01/SCK
P4,
NC
NC
P03/S1
PO./INTO
INn
Cl2
VDD
<.>
z
83-003454A
X2
P2./PSTB
40
39
"PD75CG08E
P2,/PTOUT
P22
P23
A7
As
P'2
P13
A3
P3,
P32
Ao
10
I,
12
.~ ~ i
0
if i i
.. if i
JI
f i
;r
83-0034S5A
Pin Identification
40-Pin Ceramic Piggyback DIP
38
VDD 37
MSEl 36
VDD
35
A.
34
A9
33
Al1
32
VSS 31
A,o
30
BE
29
17
2'
Is
27
Is
26
14
25
40-Pin DIP, Shrink DIP and Piggyback DIP
x,
Vss
No.
P43
P42
Symbol
Function
1,40
X2, X1
Crystal clock/external event inputport
2-5
P2o/PSTB,
P2,/PTOUT,
P22, P23
Output port 2/output strobe pulse,
timer out F/F signal
6-9
P1o-P13
I/O port 1
10-13
P30-P33
Output port 3
14-17
P7o-P73
I/O port 7
18
RESET
RESET input
P03/S1
19,21
CL1,CL2
System clock inputs
20
VDD
Positive power supply
P4,
P40
P53
P52
P5,
P50
P63
P62
P6,
P60
24
P02/S0
PO,/SCK
RESET
23
POollNTO
22
INT1
External interrupt
Cl'
VDD
22
INT1
Cl2
23-26
2'
POo/INTO,
PO,/SCK,
P02/S0,
P03/S1
Input port O/external interrupt, serial
I/O interface
I/O port 6
Vss
13
83-003779A
3-20
.
~
;;: ;;: ;;:
P23
Cll
P72
P73
z
NC
P73
RESET
P33
P70
P7,
<.>
P73
Pl.
Pl,
P30
If f If i
P4.
P4,
P23
P10
Pl,
~
Vss
P43
27-30
P6o-P63
31-34
P50-P53
I/O port 5
35-38
P43-P40
I/O port 4
39
Vss
Ground
t-{EC
IlPD7507/08
Pin Identification (cont)
Pin Functions
28-Pln EPROM Socket on Piggyback DIP
POOIINTO, P01/SCK, P02/S0, P03/S1 [Port 01
External Interrupt, Serial Interface]
No.
Symbol
1,2
NC
Not connected
Function
3-10
A7-AO
Address bits 7-0
11-13
10-12
Data bits 0-2
14,22
Vss
Ground
15-19
13-17
Data bits 3-7
20
CE
Chip enable
21,23
A10-A11
Address bits 10, 11
24,25
Ag, As
Address bits 9, 8
26,28
Voo
Positive power supply
27
MSEL
Memory select
52-Pin QFP
No.
Symbol
1,4,6,8,13,
14,27,29,
35,40,45
NC
Not connected
2,50-52
P7o-P73
1/0 port 7
Function
3
RESET
RESET input
5,9
Cll, Cl2
System clock inputs
7
Voo
Positive power supply
10
INn
External interrupt
11,12,
15,16
POo/lliIQ,
P01/SCK,
P02/S0,
P03/S1
Input port O/external
interrupt, serial I/O
interface
17-20
P60-P63
I/O port 6
21-24
P50-P53
I/O port 5
25,26
28,30
P43-P40
1/0 port 4
31
VSS
Ground
32,34
Xl, X2
Crystal clock/external
event input
33
Voo
Positive power supply
36·39
P2o/PSTB,
P21/PTOUT,
P22, P23
4·bit output port 2/ output
strobe pulse, timer out
F/F signal
41-44
P10-P13
I/O port 1
46-49
P30-P33
Output port 3
4-bit input port/serial I/O interface. This port can be
configured as a 4-bit parallel input port or as the a-bit
serial I/O interface under control of the serial mode
select register. The serial input SI, serial output SO
(active low), and the serial clock SCK (active low), used
for synchronizing data transfer, make up the a-bit
serial I/O interface. Line POo is always shared with
external interrupt INTO, a rising edge-triggered interrupt. If POollNTO is unused, it should be connected to
Vss.lf P0 1/SCK, P02/S0, or PO:vSI are unused, connect
them to Vss or V DD .
P10-P13 [Port 1]
4-bit input/three-state output port. Data output to port 1
is strobed in synchronization with a P2o/PSTB pulse.
Connect unused pins to Vss or V DD .
P20/PSTB, P21/PTOUT, P22, P23 [Port 2]
4-bit latched three-state output port. Line P20 is shared
with PSTB, the port 1 output strobe pulse. Line P2 1 is
shared with PTOUT, the timer out F/F signal. Leave
unused pins open.
P30-P33 [Port 3]
4-bit latched three-state output port. Leave unused pins
open.
P40-P43 [Port 4]
4-bit latched three-state output port. Can also perform
a-bit parallel I/O with port 5. In input mode, connect
unused pins to VDD or GND. In output mode, leave
unused pins open.
P53-P50 [Port 5]
4-bit input/latched three-state output port. This port
also performs a-bit parallel I/O with port 4. In input
mode, connect unused pins to Vss or V DD . In output
mode, leave unused pins open.
P63-P60 [Port 6]
4-bit input/latched three-state output port. The port 6
mode select register configures individual lines as
inputs or outputs. In input mode, connect unused pins
to VSSorVDD.ln output mode, leave unused pins open.
3-21
EJ
NEe
IlPD7507/08
P70-P73 [Port 7)
RESET [Reset)
4-bit input/latched three state output port. In input
mode, connect unused pins to Vss or VDD. In output
mode, leave unused pins open.
A high level input to this pin initializes the pPD7507 /08
after power up.
INT1 [Interrupt 1)
X2, X1 [Crystal Clock/External Event Input)
External rising edge-triggered interrupt. Connect to
Vss if unused.
Connect a crystal oscillator circuit to input X1 and
output X2 for crystal clock operation. Alternatively,
connect external event pulses to input X1 and leave
output X2 open for external event counting. If X1 is not
used, connect it to ground. If X2 is not used, leave it
open.
Voo [Power Supply)
Positive power supply. Apply a single voltage in the
range 2.7 to 6.0 V for proper operation.
Vss
CL 1, CL2 [System Clock Input)
[Ground)
Ground.
Connect a 82 kO resistor across CL 1 and CL2, and
connect a 33 pF capacitor from CL 1 to Vss. Alternatively, connect an external clock source to CL 1 and
leave CL2 open.
Block Diagram
P03/S1
P02/S 0
General Registers
Program Memory
2048 x 8-Bit ROM [pPD7507j
4096
x 8-Bit ROM
Instruction
Decoder
[.uPD7508]
0[4]
E [4]
H [4]
l [4]
Stack Pointer [81
Data Memory
128 x 4·B;' ROM [pPD7507]
224 x 4-Bi. ROM [pP07508]
Cl
Cll
¢
Cl2
r r r
RESET
Voo
Vss
83-003470C
3-22
NEe
J..LPD7507/08
Memory Map
Clock Control Circuit
Figure 1 shows the ROM memory map of the
pPD7507/08.
The clock control circu it consists of a 4-bit clock mode
register (bits CM1 and CM2), prescalers 1,2, and 3, and
a multiplexer. It takes the output of the system clock
generator (Cl) and count clock generator circuit (X). It
also selects the clock source and divides the signal
according to the setting in the clock mode register. It
outputs the count pulse (CP) to the timer/event counter.
Figure 2 shows the clock control circuit.
Figure 1.
ROM Map
Addre..
[Hex[
Address
[Decimal]
MSB
0
7
6
LSB
5
4
3
2
16
1
0
OOOH
RESET Pulse Vectors Program
Execution to Address DOH
010H
INTT [Internal Timer/Event
Counter Interrupt] Vectors
Execution to 010H
INTO!S (External Interrupt 01
32
020H
Serial Interface Interrupt]
030H
INT1 [External Interrupt 1]
Vectors Execution to 030H
Vectors Execution to 020H
~
C
.
0.
.!!~
0
~
C
~
48
..
Table 2 lists the codes set in the clock mode register by
the OP or OPl instruction to specify the count pulse
frequency.
Table 2.
Selecting the Count Pulse Frequency
c
0.
a.
:E
~
0
192
OCOH} LHLT Instruction
OCFH Reference Table
207
208
OOOH} CALT Instruction
255
OFFH
1023
1024
3FFH
400H
,-2047
2048
8UGH
'---4095
FFFH
7FFH
Reterence Table
CMZ
CM1
CMu
Frequency Selected
o
o
o
o
0
0
CL/256
0
1
X/54
0
X
X
o
o
Last address for
CALL Instruction
entry for pPD7507
o
CL/32
XIS
o
Not used
Not used
Last address lor
CALL instruction
entry for pPD7508
83-003456A
CM3
TOUT Signal
o
Disabled
Enabled
Figure 2.
Clock Control Circuit
System Clock
Oscillator
r-----lCL1
t-----;CL2
>-------------+
CP
(Timer/Event Counter)
Crystal Clock Oscillator/
Event Counter Input
83-003457B
3-23
twEe
IlPD7507/08
Timer/Event Counter
The timer/event counter consists of an 8-bit counter,
an 8-bit modulo register, an8-bit comparator, and a
timer out flip-flop as shown in figure 3.
The 8-bit count register is a binary 8-bit up-counter
which is incremented each time a count pulse is input.
The TIMER instruction, a RESET signal, or an INTT
coincidence signal clears it to DOH.
The 8-bit modulo register determines the number of
counts the count register holds. The TAMMOD instruction loads the contents of the modulo register.
RESET sets the modulo register to FFH.
The 8-bit comparator compares the contents of the
count register and the modulo register and outputs an
INTT when they are equal.
Figure 3.
Timer/Event Counter
INIT
(Coincidence
Signal)
TOUT
(to Sertal
Interface
and Port 2)
TIMER'
RESET
Note:
1) CP is count pulse selected by the clock mode register.
2) *Execution of instruction.
83·003600A
3-24
~EC
~PD7507/08
Serial Interface
The 8-bit serial interface allows the pPD7507/08 to
communicate with peripheral devices such as the
pPD7001 A/D converter, the pPD7227 dot matrix LCD
controller/driver, and other microprocessors or microcomputers. Figure 4 shows the serial interface.
The serial interface consists of an 8-bit shift register, a
3-bit SCK pulse counter, the SI input port, the SO
output port, the SCK serial clock I/O port, and a 4-bit
serial mode select register (MSR). The MSR selects
serial I/O or port 0 operation.
Figure 4"
Serial Interface
II
"IP
"IPL
Pll3lSI o--------1I>--I~+--I
~~~---~----tr--<]_-------~-------~
'-.Jo--t-- TOUT
PDoIINTOo--------r.:~--
RS F/F
R I+--~-- :r::.terrupt Circuli)
* Command Execution
.,. Systom Clock
S I + - - - - - "SIO
83-0030148
3-25
ttlEC
J.lPD7507/08
Interrupts
The pPD7507/08 has four vectored, prioritized interrupts. Two of these interrupts, INTT and INTS, are
internally generated from the timer/event counter and
serial interface, respectively. INTO and INT1 are
externally generated. Table 3 is a summary of the four
interrupts. Figure 5 is the block diagram.
Table 3.
pPD7507108 Interrupts
Function
Source
Location
Priority
INTT
Coincidence in timer/event counter
Internal
INTS
Transfer complete signal from serial interface
Internal
INTO
INTO pin
External
2
INn
INT1 pin
External
3
Figure 5.
ROM Vector Address
10H
20H
20H
30H
2
Interrupt Block Diagram
INT1o---i--;u.;;;==----j
INTS _ - ' - _ r -.....
P10llNTO o---i--L..-J
SIO'
INTT---------jl!~~
*Command Execution
Standby
Release
83-0034338
3-26
NEe
IlPD7507/08
System Clock and Timing Circuitry
Figure 6.
Timing for the pPD7507/08 is internally generated
except for a frequency reference, which can be an RC
circuit or an external clock source. Connect the
frequency reference to the on-chip oscillator for the
feedback phase shift required for oscillation. Figure 6
shows the connection for an RC circuit. Figure 7 shows
the connection for an external clock source.
RC Circuit Connection
vsso-H-~- CLI
' - - CL2
83-002994A
The internal oscillator generates a frequency in the
range 60 kHz to 300 kHz depending on the frequency
reference. For example, at Voo = 5 V, an 82-kn resistor
and a 33-pF capacitor generate a frequency of 200 kHz.
The oscillation frequency is fed to the clock control
circuit. It is divided by two and the resulting signal is
fed to the CPU and serial interface as shown in figure 8.
Figure 7.
External Clock Source Connection
II
CL2
Table 4 shows the operating status of the various logic
blocks under the three power down-modes.
83-002995A
Figure 8.
System Clock Circuitry
Xl
X2
INTT
CLI
INTS
System Clock
Oscillator
CL2
'--____+ _________.......--<> STOP
~:~~~~:~~n
L _ _ _ _ _ _ _~-----_c~==~StandbYRelease
Reset
83-0034608
3-27
ftlEC
Il PD 7507/08
Table 4.
Power-Down Operating Status
Power-Down Mode
Logic Block
HALT
STOP
System clock
(Note 1)
Disabled
Disabled
X2
Normal
Norm!!1
Disabled
Data Retention Mode
CPU
Disabled
Disabled
Disabled
RAM
Data retained
Data retained
Data retained
Internal registers
Data retained
Data retained
Data retained
Timer/event counter
Normal
(Note 3)
Disabled
Serial interface
(Note 2)
(Note 2)
Disabled
INTO
Normal
Normal
Disabled
INT1
Normal
Disabled
Disabled
RESET
Normal
Normal
(Note 4)
Note:
(1) Supplied to timer/event counter but not to CPU or serial interface.
(2) Can function normally if the serial MSR is set to get the SCK signal externally or from the TOUT signal.
(3) Can function normally if the clock MSR is set to use X1 as the source for the count pulse.
(4) To enter the data retention mode, raise RESET while Voo is lowered. To end the data retention mode, raise RESET when Voo is raised, then
lower it. INTT, INTO, INTS or RESET releases the STOP mode. RESET or any interrupt releases the HALT mode.
3-28
t-IEC
J.lPD7507/08
1/0 Port Interfaces
Figure 9 shows the internal circuit configurations at the
I/O ports.
Figure 9.
Interface at Input/Output Ports
Type A
1YpeE
P02/S0, P40-P43, PSO-PS3, P60-P63, P10-P13, P70-P73
Voo
Voo
·P·ch
oataJJ:
Inputl
Output
II
Output
Disable
.
Vss
Voo
Vss
TypeB
POD/INTO, P03lSI, RESET, INT1
~Input
Vss
Typ!.L
P01/SCK
1Ype 0
P30-P33, P2oJPSTB, P21/PTOUT, 'P22-P23
Voo
Voo
P·ch
oataJJ:
oataJJ:
Inputl
Output
Output
Output
Disable
Output
Disable
N·ch
Vss
Vss
In_-----t2:fX=~
2'2
t112:fc=
100
!
50 j - - - - - + - - ' - - - + - - - - f - v o o = 2.5 V,- ~
C=33pF
R=240kCl
~
[TA=25°C]
'2
CL1SLfL
I
Voo = 3 V,
R = 160 kO
I
i,
-11.....+i
400
.!:!
-------- -----
-25
500
Ie vs Voo [External Clock]
ICC vs TA
100 - J
200
100
Resistance R [kO]
2s0r-----,------,-----~7.V-OO--~57.V~,-,
~
....,
2.sV~
Voo
50 -
Supply Voltage Voo [V]
N
voo~
I"'"
[82kO]
[160kO]
[240 kO]
HALT [82 ill]
~:~~ l~:~ :gl-
STOP + Xlal Oscillation
"....-
-Supply Voltage Voo IV]
STOP [X1
OV]
ftlEC
J,LPD7507/08
Operating Characteristics (cont)
TA
= 25°C
1001 vs Icc
1001 VSTA
500
500r------r------.------,-------r------r-----~
1
.Ij
0
2 300
33pF
g'
!
z.
0
1:
1
~
J
Q 400
E
Q 400
E
.Ij
0
2 300 f--
go
R
!
z.
0
200
1:
f--
~~
~
~
u
100
~
a.
..
~
~
Ii9
0
200
100
150
200
250
-
~
l
33pF
u
100
~
a.
VDD = 5 V. R = 82 kCl
R
~
VOD
II>
::l
0
-
o
-25
300
= iV' R = 160 kO
25
50
Operating Tempe....ure TA (OC]
System Clock OlOlllatlon Frequency fCC [kHz]
IOL VB YOL
IOHVS YOH
-6
20
ITA = 25°C]
C
C
~
~
....
l:
!}
E
1:
1:
U
U
~~
15
1__- - - . . , VDD =
~~
'5
'5
~
~
VDD=3V
0
0
1
~
Ii!
OUT
Cli
Cl2
1 1 1
RESET
Voo
Vss
83-0034358
3-42
t\'EC
Figure 1.
pPD7507H/08H/75CG08HE
System Clock Options
rro
*
nrro
A.
Clock Control Circuit
Ceramic Oscillator
Recommended
Max Freq
L1
30 pF
"~
c:::J
~
30 pF
CL2
B.
=
S; 20 pF
:~~o 6.0 V 0~;: :;".!~z
~NOO=~~
38 to 6.0 V
091025 MHz
20 MHz
27to6.0V
09to11MHz
OSCillator stabilization lime lOS
10MHz
20 ms (Note 2]
Crystal Oscillator
L1
10 pF
The clock control circuit consists of a 4-bit clock mode
register (bits CMo-CM3), prescalers 1, 2, and 3, and a
multiplexer. It takes the output of the system clock
generator (Cl) and external EVENT input. It also
selects the clock source and divides the signal
according to the setting in the clock mode register. It
outputs the count pulse (CP) to the timer/event
counter. Figure 3 shows the clock control circuit.
Table 2 lists the codes set in the clock mode register by
the OP or OPl instruction to specify the count pulse
frequency. Bit CM3 controls the timer out F/F; it is
disabled when the bit is 0 and output when the bit is 1.
ccVD-D-_-__-__
----=-~'-.q--CRC-a-ng-.-_-_~T~Yp~_!~-a,ccFc-,.-q-_
4.5 to 6.0 V 3.5 to 4.2 MHz
4.19 MHz
o,,;nalo, ,'abm,.uo. Um, 'OS - 25 m. [No', 2[
CL2
C.
Table 2.
CM2
External Clock
-I.pI>O_---I CL 1
2.7 to 6.0 V
74HCOO
CMo
Frequency Selected
0
0
0
fcc/1536 (or CLl256)
0
0
1
fcc/512
900 ns
0
0
EVENT input
0.1 to 1.8 MHz
Noles:
--t;><>--L.C_L_2_ _..a
CMl
teR and tCF
110 ns
CL1
~ _~~~q~a_n~~
4.5 to 6.0 V 0.1 to 4.2 MHz
[1] Due to ceramic oscillator tolerance, operation at
the maximum frequency is nol recommended.
[2] A crystal frequency 014.194304 MHz will yield a
II
Selecting the Count Pulse Frequency
0
very-accurate l-second time base using an Inlernal
divider.
1
Not used
0
fCC/192 (or CLl32)
0
83-003763A
= (feel B) (1/64)
fcC/64
0
Memory Map
= (fcc/B) (1/B)
Not used
Not used
Figure 2 shows the ROM program map of the
7507H/7508H.
Figure 2.
ROM Map
Address
[DeCimal]
MSB
0
I:
:;
I:
..~.
~ "
:c
..."
:c
c
7
6
Address
[Hex]
LSB
5
4
3
2
1
0
RESET Pulse Vectors Program
Execution to Address OOOH
OOOH
16
010H
32
020H
48
030H
INTT [Internal Timer/Event
Counter Interrupt] Vectors
Execution to 010H
INTO/S [External Interrupt 0/
Serial Interface Interrupt1
Vectors Execution 10 020H
INT1 [External Interrupt 1]
Vectors Execution to 030H
I
I
192
OCOH
207
208
OCFH
255
OFFH
1023
1024
3FFH
400H
,-~047
2048
7FFH
BOOH
Last Address for CALL Instruction Entry
,uP07507H
'-4095
FFFH
Last Address for CALL Instruction Entry
pPD7508H
~
~
0
0
ODOH
LHL T Instruction
Reference Table
CAL T Instruction
Reference Table
63-003436B
3-43
t\'EC
pPD7507H/08H/75CG08HE
Figure 3.
Clock Control Circuit
1/8 fCC---------t-+--t--11
CL----I
[1/6fccl
EVENT-----;
>----_cp
Count Pulse to
Timer/Event Counter
*Instruction execution
83-0034698
Timer/Event Counter
Serial Interface
The timer/event counter consists of an 8-bit counter,
an 8-bit modulo register, an 8-bit comparator, and a
timer out flip flop as shown in figure 4.
The 8-bit serial interface allows the pPD7507H/08H to
communicate with peripheral devices such as the
pPD7001 A/D converter, the pPD7227 dot matrix LCD
controller/driver, and other microprocessors or
microcomputers.
The 8-bit count register is a binary 8-bit up counter,
which is incremented each time a count pulse is input.
The TIMER instruction, a RESET signal, or an INTT
coincidence signal clears it to OOH.
The 8-bit modulo register determines the number of
counts the count register holds. The TAMMOD instruction loads the contents of the modulo register.
RESET sets the modulo register to FFH.
The 8-bit comparator compares the contents of the
count register and the modulo register and outputs an
INTT one clock pulse after they are equal.
Table 3.
The serial interface consists of an 8-bit shift register, a
3-bit SCK pulse counter, the SI input port, the SO
output port, the SCK serial clock I/O port, and a 4-bit
serial mode select register (MSR). The MSR selects
serial I/O or port 0 operation.
Interrupts
ThepPD7507H/08H has four vectored, prioritized interrupts. Two of these interrupts, INTT and INTS, are
internally generated from the timer/event counter and
serial interface, respectively. INTO and INT1 are
externally generated. Table 3 is a summary of the four
interrupts.
pPD7507H/08H Interrupts
Source
Function
Location
Priority
ROM Vector Address
2
20H
INTT
Coincidence in timer/event counter
Internal
INTS
Transfer complete signal from serial interface
Internal
INTO
INTO pin
External
2
20H
INn
INn pin
External
3
30H
3-44
10H
NEe
Figure 4.
pPD7507H/08H/75CG08HE
Timer/Event Counter
INn
(Coincidence
Signal)
II
TOUT
(to Serial
Interlace
and Port 2)
TIMER·
RESET
Note:
1) CP is count pulse selected by the clock mode register.
2) "Execution of instruction.
83·003600A
Figure 5.
System Clock Circuitry
I-t-----------~';:~~~l Timer/Event Counter
~
_________
~CL
[698 kHzJ
CL1
¢
[349 kHzJ
CL2
"....,L.....j..._ _ Halt Release
...........Jr--;---
Reset
['-.J
/"""'I!'----I--- Halt *
....----+-+-- Stop *
----+-- Reset
R ....
*Command Instruction
83·003438B
3-45
ttlEC
pPD7507H/08H/75CG08HE
System Clock and Timing Circuitry
Table 4.
There are four time bases available for the
pPD7507H/08H. Table 4 shows these bases and the
frequencies generated.
Base
The CPU clock is used by the CPU and serial interface.
The system clock is used by the timer/event counter
and the INT1 signal.
pPD7507HIOBH Time Bases
Symbol
Frequency
System clock
CL
698 kHz
fcc/6 (4.19 MHz/6)
CPU clock
~
349 kHz
fcc/12 (4.19 MHz/12)
~OUT
349 kHz
fcc/12 (4.19 MHz/12)
524 kHz
fcc/S (4.19 MHz/S)
External clock
Timer/event
counter clock
Derivation
I/O Port Interfaces
Figure 6 shows the internal circuit configurations at the
I/O ports.
Figure 6.
Interface at InpuVOutput Ports
TypeB
POo/INTO, INT1, P03/SI, RESET, EVENT
TypeE
P10-P13, P02/S0, P40-P43, P50-P53, P60-P63, P70-P73
VDD
- - o < c < € J I - - - - o o 'npul
Poch
Da1811:
'npull
Oulpul
TypeC
Output
~OUT
Disable
VDD
VDD
~
VSS
Output
In_---+
Vss
Vss
Type 0
P20/PSTB, P21/PTOUT, P22, P23, P30-P33
VDD
Type F
P01/SCK
VDD
Dala 1 1 :
Oulpul
D81a11:
·Output
Disable
.
'npull
N·ch
O~tput
Vss
Note: Upon RESET, both transistor. are turned off.
Oulpul
Disable
N·ch
'n_--O<
83-OO3439C
3-46
ftlEC
pPD7507H/08H/75CG08HE
Absolute Maximum Ratings
Capacitance
TA = 25°C
TA = 25°C, Voo = a v
limits
Operating temperature, TOPT
Storage temperature, TSTG
Power supply voltage, VDO
All input and output voltages
-65 to 150°C
-0.3 to +7.0 V
--0.3 to VOO + 0.3 V
Output current, high, IOH
One pin
All pins, total
-5mA
-20mA
Output current, low, IOl
One pin
Ports 6, 7
Total ports
20 mA
200 mA
Parameter
Symbol
Typ
Max
Input capacitance
CI
15
Output capacitance
Co
15
I/O capacitance
Cia
15
Unit
Test
Conditions
pF f = 1 MHz;
unmeasured pins
pF
retumed to Vss.
pF
17 mA
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
3-47
ftfEC
pPD7507H/08H/75CG08HE
DC Characteristics
TA
.-.'
.
=: -10 to +70·C; Voo =2.7 to 6.0 V (5 V ±10% for 75CG08HE)
Limits
Para~at.r
Symbol
Input voltage, high
VIHl
VIH2
VIHOR
Input voltage, low
Output voltage, high
Output voltage, low
Min
Typ
Teat
Conditions
Max
Unit
0.7 Voo
Voo
V
Except CL1, CL2
Voo -O.S
Voo
V
CL1, CL2
0.9VOOOR
VOOOR +0.2
V
RESET, data retention mode, pPD7507H/08H
only
VILl
0
0.3 VOO
V
Except CL1, CL2
VIL2
0
O.S
V
CL1, CL2
VOH
VOO -1.0
V
IOH = -1.0 rnA; VOO = 4.S to 6.0 V; except
AlliVPP, for pPD7SCGOBHE
VOO -0.5
V
IOL=-100pA
VOO -0.7S
V
AlliVpp; IOH = -S rnA (pPD7SCGOBHE only)
1.S
V
IOL = 12 rnA; VOO = 4.S to 6.0 V; Ports 2-S
0.4
V
IOL = 1.6 rnA; VOO = 4.S to 6.0 V; Ports 6-7
O.S
V
O.S
VOL
IOL =400pA
High level input current (MSEL) IIH
VIN =VOO
300
pA
pPD7SCGOBHE only
Low level input current (10-17)
IlL
VIN=OV
-200
pA
pPD7SCGOBHE only
Input leakage current, high
IUH1
3
pA
Except CL1, CL2; VI = Voo
IUH2
20
pA
CL1, CL2; VI = VOO
IUL1
-3
pA
Except CL 1, CL2; VI = 0 V
IUL2
-20
pA
CL1. CL2; VI = 0 V
Input leakage current, low
Output leakage current, high
ILOH
3
pA
Vo =VOO
Output leakage current, low
ILOL
-3
pA
Vo=OV
6.0
V
900 (1)
1000 (2)
3000 (1)
3000 (2)
pA
pA
Normal operation, VOO = 4.S to 6.0 V;
fCC = 4.19 MHz
150 (2)
700 (2)
pA
Normal operation, Voo = 2.7 to 3.3 V;
fcC = 1 MHz, pPD7S07H/08H only
350 (1)
SOO (2)
BOO (1)
1100 (2)
pA
pA
HALT mode, X1 = 0 V; VOO = 4.S to 6.0 V;
fcc = 4.19 MHz
70 (2)
180 (2)
pA
HALT mode, X1 = 0 V; VOO = 2.7 to 3.3 V;
fCC = 1 MHz, pPD7507H/OBH only
0.1
10
pA
STOP mode, pPD7507H/08H only
O.S
50
pA
STOP mode, pPD7SCGOBHE only
Supply voltage
Supply current
VOOOR
1001
1002
10D3
Not..:
(1) Crystal oscillation; Cl = C2 = 10 pF.
(2) Ceramic oscillation; Cl = C2 = 30 pF.
3-48
2.0
Data retention mode, pPD7S07H/OBH only
~EC
~PD7507H/08H/75CG08HE
AC Characteristics
TA = -10 to +70·C; Voo = 2.7 to 6.0 V (5 V ±10% for 75CG08HE)
limits
Parameter
Symbol
Min
System cycle time
tCY
EVENT input frequency
fE
Typ
Max
Unit
2.86
120
JiS
11
120
JiS
0
700
kHz
0
150
kHz
Test
Conditions
Voo = 4.5 to 6.0 V
Voo = 4.5 to 6.0 V
Voo = 4.5 to 6.0 V
EVENT input high
tEH
0.7
JiS
EVENT input low
tEL
3.3
JiS
SGK cycle time
tKCY
2.5
JiS
10
JiS
SGK as input
2.86
JiS
SGK as output; Voo = 4.5 to 6.0 V
11
JiS
SGK as output
SGK pulse width
tKH, tKl
1.1
JiS
SGK as input; Voo = 4.5 to 6.0 V
4.5
JiS
SGK as input
1.3
JiS
SGK as output; Voo = 4.5 to 6.0 V
5.0
JiS
SGK as output
ns
SI setup time to SCK t
tSIK
300
SI hold time after SGK t
tKSI
450
SO delay time after SGK !
tKSO
Port 1 output setup time to
PSTSt
tpST
Port 1 output hold time after
PSTB t
PSTS pulse width
ns
1200
ns
ns
(Note 2)
ns
tSTP
80
ns
tSWl
(Note 1)
ns
(Note 2)
ns
INTO pulse width
tIOH, tlOl
tI1WH, tl1Wl
RESET pulse width
RESET setup time
Glock stabilization time
IJ
ns
850
(Note 1)
INT1 pulse width
SGK as input; Voo = 4.5 to 6.0 V
10
JiS
1 (Note 3)
tCY
tRSH, tRSl
10
JiS
tSRS
0
ns
tos
25
ms
VOD = 4.5 to 6.0 V
Voo = 4.5 to 6.0 V
Voo = 4.5 to 6.0 V
Voo = 4.5 V
Notes:
(1) (3 + fcc or fe) - 350.
(2) (3 + fCC or fe)- 1000.
(3) tCY = 12 + fcc or fc·
3-49
NEe
pPD7507H/08H/75CG08HE
Timing Waveforms
ExJernallnterrupts
Clocks
INTO
-C=IIOL=rIIOH~
INTI
-C=IIIL=r=IIIH~
Timing Measurement Points
83-003317A
O.7VDD~
--V0.7VDD
-------I\~O~.3~V~D~D______________~O~.3~V~DD~
Reset
83-003411A
Ser/allnterface
83-003318A
STOP Mode
SCK
~"":----STOP Mode
::+-
SI
VOO
so
Valid Output Data
)(
83-003316A
EVENT Input
-~
3-50
;
1/fE
IEL
IEH
t
83-003441A
RESET
~
Oala Relenllon
YODOR
t-rEC
pPD7507H/08H/75CG08HE
Operating Characteristics (cont)
TA = 25°C
Oscillator Frequency vs Supply Voltage
Oscillator Frequency vs Supply Voltage
10
10
N
l:
i....
~
--ttc~tt~··
0
f---
N
::
l:
~
(J
s
Jl
f
c
~
~
~
~
...~
1
S
0.5
0.4
0.3
~
'il
o
~C1 10pF
Cl1
CL2 C2<~
!
t=
~
0
C1J;
J;C2
C1J;
J;C2
1
~
1.1 MHz_----1
,~
l!
0.2
o.1
4.2 MHZ,
2.SMHz
I II
0.2
0.1
o
o
Supply Voltage, Voo IV]
Supply Voltage, Voo IV]
Event Frequency vs Supply Voltage
Clock Frequency vs Supply Voltage
100
=1
=
~
CL21
CL1
N
~cJ
J.l.
==
-
l:
~
.)!!
~
"P074HCOO
.
-
~
...
~
0.1
'5
]"
c
~
0.01
w
0.01
0.001
o
0
Supply Voltage, Voo [V]
Supply Vollag'e, VOO [V]
Supply Current vs Supply Voltage
Oscillator Frequency vs Supply Voltage
10'
C
10'
3
~1Pt
~
0
E
~
0
E
i
~ 10'
...
;+;C1
;+;C2
C1~C2~30pF
<3
JI...
-
fCC
fCC
1
.J.. +-HALT Mode
~
a.
'"
!----fCC -
4.19 jHZ
1 MHz
4.19 MHz
fCc=1 MHz
~
~b;t
1000
f-
0
~
E
.:
~
..
U
>.
~
'"
101
1200
1400
Operating Mode
t-TA
-
Supply Voltage, Voo IV]
o
~
2S'C
VOperatin9 Mode
J;C'
400
o
o
0
J;C1
,. / '
600
25°C
I
TA
C,~C2~30pF
800
200
100
J VDD~SV-
f--
~
--
~ 'HALT Mode
2.
Oscillation Frequency, fCC [MHz]
3-51
t-{EC
pPD7507H/08H/75CG08HE
Operating Characteristics (cont)
TA
= 25°C
Clock Frequency vs Supply Voltage
VOL vs. IOL [Ports 2-7]
20
TA ~ 25°C
1400
TA-25°C
Voo
1200
~
Q
= 5V
1000
E
~
...
U
./
800
=
1/
400
200
o
o
c::..
./
/'
"
g
U
HALT Mode
--
1 VVD~
II VDD~4~
///
voo - a
U
~3
§
;;
a
.3
~2
/11/
~1
o
t'
--
Voo=3V
o
Output Voltage - V
3-52
Voo =3V
Output Voltage - V
TA
~4
-
o
~6
C
v
f-"
o
~7
"
$.D~4:--
'I
VOHvs.IOH
~5
II ~VDD~51v
1!L
~
o
Counter Clock 'Frequency, fe [MHz]
g
/
110
=
/
= 6 v;
15
/peraung Mode
600
0.
UI
/'
/'
Voo
= 25°C
pPD7527AJ28AJ75CG28E
fttIEC
4-Bit,Single-Chip
CMOS Microcomputers
With FIP® Driver
NEe Electronics Inc.
Description
The IlPD7527A, IlPD7528A, and IlPD75CG28E are 4-bit,
single-chip CMOS microcomputers with the IlPD7500
architecture and FIP direct-drive capability.
The pPD7527 A contains a 2048 x 8-bit ROM and a 128 x
4-bit RAM. ThepPD7528A contains a 4096 x 8-bit ROM
and 160 x 4-bit RAM.
The IlPD7527A/28A contains two 4-bit general purpose
registers located outside RAM. The subroutine stack is
implemented in RAM for greater depth and flexibility.
The IlPD7527A/28A typically executes 67 instructions
with a 5 Ils instruction cycle time.
The IlPD7527A/28A has one external and two internal
edge-triggered hardware-vectored interrupts. It also
contains an 8-bit timer/event counter and an 8-bit serial
interface to help reduce software requirements.
Thirty-one high-voltage lines are organized into the 3-bit
output port 2, the 4-bit output ports 3, 8, and 9, and the 4bit 1/0 ports 4, 5, 10, and 11.
The low power consumption CMOS process allows the
use of a power supply between 2.7 and 6.0V. Current
consumption is less than 3.0 mA maximum, and can be
further reduced in the halt and stop power-down modes.
The IlPD75CG28E is a piggyback EPROM version of the
IlPD7527A/28A.
Pin-compatible
and
functioncompatible with the final, masked versions of the
IlPD7527A/28A, the IlPD75CG28E is used for prototyping and for aiding in program development.
D
D
D
D
D
D
D
D
D
D
Vectored interrupts: one external, two internal
8-bit timer/event counter
8-bit serial interface
Standby function (HALT, STOP)
Data retention mode
Zero-cross detector on POOl INTO input (mask
optional)
System clock (j.iPD7527A/7528A/75CG28E): on-chip
RCosciliator
CMOS technology
Law power consumption
Single power supply
- IlPD7527A/7528A: 2.7 to 6.0 V
- IlPD75CG28E: 5.0 V
Ordering Information
Part
Number
Package Type
Mu Frequlncy
of Operation
I'PD7527AC/28AC
42-pin plastic DIP
I'PD7527ACU /28ACU
42-pin plastic shrink DIP
610kHz
610 kHz
I'PD75CG28E
42-pln ceramic piggyback DIP
500 kHz
Pin Configurations .
IlPD7527A128A, 42-Pin Plastic DIP or Shrink DIP
RESET
CLl
CL2
Features
D 67 instructions
D Instruction cycle:
-Internal clock: 3.31ls/600 kHz, 5 V
- External clock: 3.3 Ils/600 kHz, 5 V
D Upwardly compatible with the IlPD7500 series
product family
D 4,096 x 8-bit ROM (j.iPD7528A/75CG28E)
2,048 x 8-bit ROM (j.iPD7527A)
D 160 x 4-bit RAM (j.iPD7528A/75CG28E)
128 x 4-bit RAM (j.iPD7527 A)
D 351/0lines
D 31 high-voltage output lines that can directly drive a
vacuum fluorescent display (FIP)
D Can select either a pull-down resistor or open-drain
output per 31 high-voltage outputs (mask optional)
Pl00
49-001078A
FIP is the registered trademark for NEC's fluorescent Indicator panel (vacuum
fluorescent display).
50275 (NECEL-509)
3-53
II
,..,EC
~PD7527A/28A/75CG28E
MPD75CG28E EPROM
Pin Configurations (cont)
No.
MPD75CG28E, 42·Pin Ceramic Piggyback DIP
RESET
CL1
CL2
vooo, 280 Voo
NCO 2 270MSEL
P53
A7 61·[60 Voo
PS2
PS,
I
As 04 250 As
NC
No connection
EPROM address output
11-13,15-19
10-17
Data read input from the EPROM
P3.
14
Vss
Connection to EPROM GND pin
P3,
20
CE
Chip enable output
ps.
Supplies EPROM OE Signal
I
P32
I
I
P33
22
Vss
23
A11
Program counter MSB output
I
P40
P4,
P42
26
VOO
Supplies Vee to the EPROM
P43
27
MSEL
Mode select input
28
Voo
Supplies high-level signal to MSEL
6 230I A"
A40
I
A30 7 220V55
I
A2082l0 A"
P21/PTOUT
I
1-
Al0 920QCE
P103
I
I
Ao01O '90 17
P102
I
I
1.011 '80ls
1,6,2 1761,
P101
I
I
120'3 '601.
'7
P112
vssy
~S913
P8.
P8,
P82
Note:
P83
(1) Output drivers on ports 2-5 and 8-11 are mask·optional. Accordingly,
either an open·drain output or a pull-down resistor can be selected.
VLOAD is suitable for an output driver with a pull·down resistor.
P9.
P9,
P111
P110
P02/S0
P03/S1
I
AsO 5 240 A•
P23
P22
P'On
P113
I
Connection to pin 21 of I'PD75CG28E
Ao-A10
P01/SCK
NC
Function
Voo
3-10,21,
24,25
V55
POolINTO
VPRE
Symbol
EPROM: 2732
P92
(2) Ports 2-5 are suitable as FIP segment signal outputs, and ports 8-11
are suitable for FIP digit signal outputs.
P93
Voo
49-001079A
(3) Ports 8-11 have high-current drive capability and can drive an LED
directly.
Pin Identification
Pin Functions,JAPD7527A/28Aand
JAPD75CG28E
MPD7527A/28A and MPD75CG28E
No.
Symbol
Function
RESET
Reset input
2,3
CL1, CL2
Clock pins
RESET
System reset (input).
4
VPRE
High·voltage predriver supply
5
VLOAO
High·voltage option resistor supply
7527A/ 28A only
6-9
P50-P53
High·voltage I/O port 5
10,12
P23, P22
P21/PTOUT
High·voltage output port 2, and output
port from timer / event counter (PTOUT)
VPRE
Negative power supply for high-voltage output predrivers (for ports 2-5, 8-11).
13-16
Pl00-Pl03
High·current, high·voltage I/O port 10
17-20
Pll0-P113
High-voltage, high-current I/O port 11
21
VOO
Positive power supply
22-25
P90-P93
High-voltage, high-current output port 9
26-29
P80-P83
High-voltage, high-current output port 8
High-voltage I/O port 4
CL1,CL2
Connection to the RC oscillator. CL1 is the external
clock input.
VLOAD
Negative power supply for optional load resistors (pulldown resistors) of high-voltage output drivers (for ports
2-5,8-11). This pin is only on the MPD7527A/28A.
30-33
P40-P43
34-37
P30-P33
High-voltage output port 3
38
39
40
41
P03/S1
P02/§Q.
P01/SCK
POo/INTO
4-bit input of port 0; or serial data input
(SI), serial data output (SO), serial clock
I/O (SCK), and external interrupt input
(INTO) or zero-cross detect input (POo).
4-bit, high-voltage 1/0 port 5.
42
Vss
Ground
P21-P23
P53- P50
3-bit, high-voltage output port 2.
3-54
NEe
~PD7527A/28A/75CG28E
PTOUT
Pin Functions, J.lPD75CG28E EPROM
Output port from the timer/event counter.
MSEL
P103-P100
P113-P110
Changes the addressing area of the external EPROM
and the on-chip RAM (with a pull-down resistor). Connecting a jumper between socket pins 27 (MSEL) and 28
(Voo) selects f.4PD7527 A mode (2-Kbyte EPROM, 128 x 4bit RAM). Leaving MSEL open selects f.4PD7528A mode
(4-Kbyte EPROM, 160 x 4-bit RAM).
4-bit, high-voltage, high-current I/O port 11. Capable of
bit set/reset by SPBLI RPBL instructions.
Ao-A10
Vee
Output the low-order 11 bits of the program counter
(PCO-PC10). Used as EPROM address signals.
4-bit, high-voltage, high-current I/O port 10. Capable of
bit set/reset by SPBLI RPBL instructions.
Positive power supply.
A11
P93-P90
4-bit, high-voltage, high-current output port 9. Capable
of bit set/reset by SPBLlRPBL instructions.
When MSEL is high level, A11 outputs high-level signals.
When MSEL is open, A11 outputs the MSB of the PC,
which is used as the most significant address signal of
the 4-Kbyte EPROM 2732.
P83-P80
4-bit, high-voltage, high-current output port 8. Capable
of bit set/ reset by SPBLI RPBL instructions.
10-17
Input data read from the EPROM.
P43-P40
CE
4-bit, high,voltage I/O port 4.
Outputs the chip enable signal to the EPROM.
P33-P30
Vee
4-bit, high-voltage output port 3.
Pin 26 is electrically equivalent to the bottom Voo pin
and is used to supply Vee to the EPROM. Pin 28 is electrically equivalent to the bottom Voo pin and is used to
supply the high level signal to MSEL. Pin 1 connects to
pin 21 of f.4PD75CG28E.
POO-P03
4-bit input port O. POo is also used as the zero-cross detection input.
SI
Serial data input.
so
Vss
Pin 14 is electrically equivalent to the bottom Vss pin in
voltage, and is connected to the EPROM GND pin. Pin
22 is electrically equivalent to the bottom Vss pin and is
used to supply the OE signal to the EPROM.
Serial data output.
Instruction Set
SCK
I/O serial clock.
Refer to the User's Manual. The instruction set appears
also as subset A4 in the data sheet for the f.4PD7500 series of single-chip microcomputers.
INTO
External interrupt input.
Vss
Ground.
3-55
II
ttlEC
~PD7527A/28A/75CG28E
Block Diagram,f-IPD7527A/28A
Program Memory
2048 x 8 Bits ~PD7527A)
4096 x 8 Bits {flPD7528A)
Cl
Instruction
Decoder
,I,
Data Memory
~~g ~ : ~::: ~~g~~~~:~
Cll
3-56
Cl2
i t t
VDD
Vss
RESET
NEe
~PD7527A/28A/75CG28E
Block Diagram, fJPD75CG28E
POO"NTO
P21-P23
PTOUT/P21
II
' -_ _ _ _
---'~DP7C
Instruction
Buffer
Instruction
Decoder
Data Memory
160 x 4 Bits
P100-P103
ell
CL2
h h t
P110-P113
Voo Vee Vss Vss RESET
49-0010688
Absolute Maximum Ratings
TA=25°C
Power supply voltage, Voo
-0.3to +7V
Output current high, ports 3,4,8,9 total, IOH
-55mA
Power supply voltage, VLOAO (I'PD7527A / 28A)
VOO-40 V to Voo +0.3 V
Output current high, ports 2, 5, 10, 11 total, IOH
-55mA
Power supply voltage, VPRE
VOO-12 V to Voo +0.3 V
Output current low, per pin, IOL
15mA
Output current low, all ports total, IOL
15mA
Input voltage, except ports 4,5,10,11, VIN
Input voltage, ports 4,5,10,11, VIN
Output voltage, except ports 2-5, 8-11, Vo
Output voltage, ports 2-5, 8-11, Vo
-0.3VtoVoO +0.3V
VOO-40 V to Voo +0.3 V
-0.3VtoVoO +0.3V
VOO-40 V to Voo +0.3 V
Output current high, per pin: P01, P02; IOH
-15 mA
Output current high, per pin: ports 2-5, 8-11; IOH
- 30 mA
Operating temperature, TOPT
Storage temperature, TSTG
Comment: Exposing the device to stresses above those listed in Abso-
lute Maximum Ratings could cause permanent damage. The device is
not meant to be operated under conditions outside the limits described in the operational sections of the specification. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
3-57
NEe
~PD7527AJ28A/75CG28E
DC Characteristics
jAPD7527A128A
TA =. -10°C to + 70°C, Voo = +2.7VtoS.OV
Limits
Parameter
Input voltage,
low
Input voltage,
high
Symbol
Min
Output voltage,
high
Max
Unit
0
0.3 Voo
V
Port 0, RESET
VIL2
0
0.5
V
CL1
VIL3
Voo-35
0. 3Voo
V
Ports 4, 5, 10, 11
VIHt
0. 7Voo
Voo
V
Port 0, RESET
VIH2
Voo-0.5
Voo
V
CL1
VIH3
0. 7Voo
Voo
V
Ports 4, 5, 10, 11;
4.5V"Voo"
6.0V
VOL
VOH
Voo
V
Ports 4, 5, 10, 11;
2.7V" Voo"
4.5V
0.4
V
POt, P02; 4.5 V"
Voo" 6.0V;
IOL =t6mA
0.5
V
POt, P02;
IOL =400,..A
V
Ports 2-5,
IOH= -4 mA
(Note 1)
Voo-2.0
V
Voo-2.0
V
Voo-2.0
V
Voo-2.0
V
Voo-tO
V
VOO-O.5
Input leakage
current, low
Input leakage
current, high
3-58
Test
Conditions
VILt
Voo-0.5
Output voltage,
low
l'yP
Ports 8-11,
IOH= -10mA
(Note 1)
Ports 2-5,
IOH=-2mA
(Note 2)
Ports 8-11,
IOH=-5mA
(Note 2)
POt, P02;
IOH= -1mA
(Note 3)
POt, P02;
IOH= -100,..A
IULt
-3
,..A
VIN=OV; POO-P03
(Note 4)
IUL2
-40
,..A
VIN=OV; POo
(Note 5)
IUL3
-10
,..A
VIN=OV; CL1
IUL4
-10
,..A
VIN=Voo-35V;
ports 4, 5, 10, 11
IUHt
3
,..A
VIN=VOO;
POO-P03 (Note 4)
IUH2
40
,..A
VIN=VOO; POo
(Note 5)
IUH3
10
,..A
VIN = Voo; CL1
IUH4
80
,..A
VIN = Voo; ports 4,
5,10,11
Llmill
Parameter
Output leakage
current, low
Output leakage
current, high
Max
Unit
Test
Conditions
ILOL1
-3
,..A
Vo=OV; POt, P02
ILOL2
-10
,..A
Vo=Voo-35V;
ports 2-5, 8-11
ILOHt
3
,..A
Vo=Voo; except
ports 4, 5, 10, 11
ILOH2
80
,..A
Vo=Voo; ports 4,
5,10,11
to
3.0
mA
Voo=5V±10%,
R=39kQ
0.4
1.0
mA
Voo=3V,
R=82 kQ
200
600
,..A
Voo=5V±10%,
R=39kQ (Note 4)
60
200
,..A
Voo=3V,
R=82kQ (Note 4)
210
640
,..A
Voo=5V±1O%,
R=39kQ (Note 5)
67
230
,..A
Voo=3V,
R=82kQ (Note 5)
0.1
10
,..A
Voo=3 V (Note 4)
10
40
,..A
Voo=5V±10%
(Note 5)
7
30
,..A
Voo=3V (Note 5)
140
220
kQ
VOO-VLOAO=35V
Symbol
Min
Supply current, loOt
normal operation
Supply current, 1002
HALT mode
(Note 6)
Supply current, 1003
STOP mode
(Note 6)
On-chip pullRL
down resistance
80
l'yP
Note:
(1) VpRE = Voo-9V ±t V. The circuit in figure 5 is recommended.
(2) VpRE=OV. Voo=4.5Vto6.0V.
(3) Voo=4.5Vto6.0V.
(4) Without zero-cross detector.
(5) With zero-cross detector.
(6) Ports 4, 5, 10, 11 are low level output or low level input.
NEe
~PD7527A'28A/75CG28E
DC Characteristics (cont)
j.lPD75CG28E
Limits
TA= -10°C to +70°c, Voo= +5V±10%
Parameter
Limits
Symbol
Parameter
Input voltage,
low
Input voltage,
high
Output voltage,
low
Output voltage,
high
Min
Typ
Mall
Un"
Telt
Cond"lons
Symbol
Input leakage
current, low
Min
Typ
Test
Conditions
Mall
Unit
IUL1
-3
f'A VIN=OV; POO-P03
f'A VIN=OV; POo
f'A VIN=OV; CL1
f'A VIN = Voo- 35 y;
VILl
0
0. 3Voo
V
Port 0, RESET
IUL2
-40
VIL2
0
0.5
V
CL1
IUL3
-10
VIL3
Voo-35
0. 3Voo
V
Ports 4, 5, 10, 11
IUL4
-10
Port 0, RESET
IUHl
3
f'A VIN=VOO;
IUH2
40
IUH3
10
IUH4
80
f'A
f'A VIN=VOO; Cll
f'A VIN = Voo; ports 4,
VIHl
0. 7Voo
Voo
V
VIH2
Voo-0.5
Voo
V
CL1
VIH3
0. 7Voo
Voo
V
Ports 4, 5, 10, 11
0.4
V
POl, P02;
IOL=I.6mA
0.5
V
POl, P02;
10L = 400 f'A
V
Ports 2-5,
10H= -4 mA (1)
Ports 8-11,
10H = -10 mA(I)
VOL
VOH
Voo-2.0
V
Voo-2.0
V
Voo-2.0
V
Voo-2.0
V
Voo-1.0
Ports 2-5,
IOH= -2mA(2)
Ports 8-11,
IOH= -5mA(2)
POl, P02;
10H=-lmA
Input current,
low (10-17)
IlL
-200
f'A VIN=OV
Input current,
high (MSEL)
IIH
300
",A
ports 4, 5, 10, 11
Input leakage
current, high
VIN=VOO
POO-P03
VIN = Voo; POo
5,10,11
Output leakage
current, low
ILOL1
-3
ILOL2
-10
f'A Vo=OV; POl, P02
f'A Vo=Voo-35 V;
ILOHl
3
f'A Vo = Voo; except
ILOH2
80
f'A Vo=Voo; ports 4,
ports 2-5,8-11
Output leakage
current, high
ports 4, 5, 10, 11
5,10,11
Supply current, 1001
normal operation
1.0
3.0
mA
R=39kQ
Supply current, 1002
HALT mode(3)
210
630
f'A
R=39kQ
Supply current, 1003
STOP mode(3)
10
50
f'A
Nota:
(1) VpRE= Voo- 9V +1V. The circuit in figure 6 is recommended.
(2) VpRE=OV
(3) Ports 4, 5, 10, 11 are output off or low input.
Figure 1.
Recommended Circuit, j.lPD7527AI 7528A
Voo
j..lPD7527
17528
VpRE
+~
Figure 2.
Recommended Circuit, j.lPD75CG28E
+5V
Voo
~RD9.1EL
+5V
:'::
.PD75CG28
I
VpRE
6akU
68kH
~-30V
30V
VLOAD
Vss
~~RD9.1EL
3.3f.1F
1
Vss
49,OO1052A
1
49-001054A
3-59
IJ
ttlEC
",PD7527A/28A/75CG28E
Zero·Cross Detection Characteristics
AC Characteristics
"PD7527A/28A:TA= -10"010 +70"0, Voo=4.5VI06.0V
"PD75CG28E:TA= -'10"Olo+70"O,Voo= +5V±10%
IlPD7527AI28A
Limits
Parameter
Symbol
Min
iero·cross
detection input
voltage
Vzx(P-P) 1
Zero·cross
accuracy
VAZX
Zero-cross
detection input
frequency
Trp
'Mall
3
Test
UnH
Vp.p AC coupled,'
C=O,I"F
±100
45
fzx
mV
1000
50 Hz to 60 Hz sine
wave
Hz
Zero·Cross Detection Waveform
AClnput
I
I
I
Limits
Parameter
Cycletinie
(Note 1)
Symbol
tCY
POo event input fpo
frequency
Min
TrP
Mu
UnH
3.3
200
,,5
6.9
200
,..s
0
610
kHz
0
290
kHz
POo input rise
time
tpOR
0,1
POo input fall
time
tPOF
0,1
POo input pulse tpOl
width, low
1,63
POo input pulse tPOH
width, high
0.72
SCK cycle time
3,0
tKCY
I
,,5
,,5
I
Zeroc"""'~
Signal'
_ o n oIgnol delay from the Iow-to-hlgh and hlgh·to-!ow lransltionsollhe AC
Input slgnol, raopecIlwly.1fow8var, ft Is possible that the zero.cross detecllon
lead. iCJw..to.hlgh andlor high-to-lowlranslllon(s) Glthe AC input signal.
8,0
SCK pulse
width, low
tKl
Capacitance
SCK pulse
width, high
tKH
TA =25"0, Voo=Ov, 1=1.0 MHz, Unmeasured pins relurned 10 GND
Limits
Symbol
Input
capacitance
CI
Output
capacRance
Co
I/O
CIO
capacRance
3-60
Min
Trp
3,35
3,9
4&-OO1055A
Parameter
1.55
,,5
,,5
,,5
,,5
,,5
,,5
6.9
'
N_ In the above _ _ boIh o-to-l and l-to-O Iransltions 01 the zero-cross
1,4
Test
Condition.
Mill
Unit
300
ns
pF
POo, POa
SI set-up time
(to rising·edge
ofSCK)
tSIK
15
SI hold time
tKSI
450
lis
15
pF
Port 2
35
pF
Ports 3,8,9
15
pF
POl, P02
35
pF
Ports 4, 5, 10, 11
Voo=4.5Vto
6.0V
~oo=4,5Vto
,,5
,,5
,,5
,,5
3.3
I
!
!I
Teat
CondHlon.
6.0V
I
II
_on
TA= -10"010 +70°C, Voo = +2.7V10 6.0V
CondHlon.
VOO=4.5Vto
6,OV
Input; Voo= 4.5 V
t06,OV
Output;
VDO=4.5Vto
6.0V
Input
Output
Input
Output
Input; Voo=4.5 V
t06.0V
Output;
Voo=4.5Vto
6,OV
(afterri~
edge of SCK)
SO output delay tKSO
time (after
falling·edge of
SCK)
850
ns
1200
ns
INTO pulse
tIOH,
width, high, low tlOl
10
,,5
RESET pulse
tRSH,
width, high, low tRSl
10
,,5
Voo=4,5Vto
6.0V
NEe
~PD7527A128A175CG28E
Oscillation Characteristics
AC Characteristics (cont)
IlPD75CG28E
p.PD7527A/28A
TA= -10 0 Cto +70 0 C, voo= +5V±10%
TA = -10"0 to +7O"C, voo = 2.7 Vto 6.0 V
Limits
Symbol
Parameter
Min
Typ
Max
Unit
tCY
4.0
200
"'S
POD event input fpo
frequency
a
500
kHz
Cycle time
(Note 1)
POD input rise
time
tpOR
0.2
"'s
POa input fall
time
tPOF
0.2
"'S
POa input pulse tpOH,
width, high, low tpOl
SCK cycle time
0.8
tKCY
Test
Conditions
"'S
3.0
"'S
Input
4.0
"'s
Output
"'S
Output
Input
SCK pulse
width, low
tKl
1.8
SCK pulse
width, high
tKH
1.3
"'S
SI set-up time
(to rising-edge
ofSCK)
tSIK
300
ns
SI hold time
(after risingedge of SCK)
tKSI
Parameter
Symbol
System clock
oscillation
frequency
(Note 1)
fcc
System clock
CL 1 Input
frequency
(Note 2)
fc
CL 1 Input rise
time (Note 2)
Min Typ Max Unit Condltone
300
400
500
kHz
150
200
250
kHz
R=82kO±2%
10
610
kHz
Voo = 4.5 Vto
6.0 V
10
290
kHz
teR
0.1
p.S
CL 1 Input fall
time (Note 2)
teF
0.1
p.S
CL 1 Input
pulse width,
low (Note 2)
tel
0.7
50
pos
CL 1 Input
pulse width,
high (Note 2)
teH
1.63
50
p.S
Voo = 4.5 Vto
6.0 V
Unit
Conditions
IlPD75CG28E
TA= -10°Cto +70°C,V oo =5V±10%
450
ns
Limits
Parameter
SO output delay tKSO
time (after
falling-edge of
SCK)
850
ns
Symbol
System clock
oscillation
frequency
(Note 1)
fcc
fc
Test
Min
Typ
Max
300
400
500
kHz
R=39kQ±2%
110
150
190
kHz
R=110kQ:t2%
500
kHz
INTO pulse
tIOH,
width, high, low tlOL
10
"'S
RESET pulse
tRSH,
width, high, low tRSl
10
"'S
System clock
CL1 input
frequency
(Note 2)
ns
CL1 input rise
time (Note 2)
tCR
0.2
",s
CL1 input fall
time (Note 2)
tCF
0.2
",s
50
",s
Data input delay tACC
time from
address
700
Data input delay tCE
time from CE
700
Input hold time
after address
R=39kO:t2%
Voo = 4.5 Vto
6.0 V
a
tlH
ns
10
CL1 input pulse tCH,
width, high, low tCl
ns
0.8
Note:
(1) R, C (see figure 3).
Note:
(1) tcy = 2/fcc or 2lfc
Figure 3.
(2) External clock (see figure 4),
Recommended RC Oscillator Circuit
AC Waveform Measurement Points (Except CL 1)
~0.7VDO
Test
0.7VOOC
.0.3 voe> Points < 0 . 3 Voo.
49·Q01056A
C=33pF±S%
I~Cls60ppm/OC
49-001059A
3-61
fttIEC
f,.tPD7521A/28A/75CG28E
Figure 4.
p
.
Recommended External Clock Circuit
C.L1CL2
Data Retention Mode Timing
VOO --1------1
open
CMOS
RESET
Stop Mode Low Voltage Data Retention
Characteristics
CD VOOOR
",PD7527A/28A
0
V'HOR
0
V'l1
49-001077A
Limits
Paramstar
® V'H1
Note: In data retention mode, all inputs should be made lower level than VODDR'
TA= -10 0Cto +70°C
Symbol
Min
Data retention
supply voltage
VOOOR
2.0
Data retention
supply current
IOOOR
Test
Conditions
Mal
Unit
6.0
V
0.3
10
~
VOOOR=2V
(Note 1)
7
30
~
VOOOR=2V
(Note 2)
VOOOR
+0.2
V
TyP
Data retention
RESET input
voltage high
VIHOR 0. 9VOOOR
RESET set-up
time
tSRS
0
,..5
RESET hold time tHRS
0
,..5
J.lPD75CG28E EPROM Interface
A 4-Kbyte EPROM (2732) plugs into socket pins on top of
the ",PD75CG28E. A high input to MSEL selects
",PD7527A mode and fixes the A11 output high level in order to access the upper 2-Kbytes of the 4-Kbyte EPROM_
When MSEL is open, ",PD7528A mode is selected_ All
EPROM addresses can be accessed because A11 functions as the MSB of the address. Figure 5 shows the address control unit. Figures 6 and 7 show the
",PD75CG28E connected with the 2732.
Figure 8 shows the EPROM read timing. Data is read
into the instruction buffer at the end of the T4 state. The
chip enable (CE) signal is made active during 2 states
(T3, T4) in order to decrease the power consumption of
the EPROM.
",PD75CG28E
TA= -100Cto +70 0C
Figure 5.
Limits
Parametar
Symbol
Min
Data retention
supply voltage
VOOOR
2.0
Data retention
supply current
IOOOR
Data retention
RESET input
voltage high
VIHOR 0.9VOOOR
RESET set-up
time
tSRS
0
,..5
RESET hold time tHRS
0
,..5
7
Unit
5.5
V
30
~
VOOOR
+0.2
V
Address Control Unit
Tast
Conditions
VOOOR=2V
VOO(28)
MSEL
to Address Decoder
of Data Memory
sw
On-chip
pull-down
resistor
Vss
Note:
(1) Without zero-cross detector
(2) With zero-cross detector
3-62
TyP
Mal
SWan: !-,PD7527A Mode
SW off: !-,PD7528A Mode
49-001069A
ttlEC
~PD7527A128A175CQ28E
Figure 6. Connection with the 2732 (pPD7527A Mode)
Figure 7. Connection with the 2732 (pPD7528A Mode)
2732
VDD(26)
Vee
VDD(26)
VDD(28)
MSEl
~
Vee
VDD(28) t--(open)
-'1,
All (high)
MSEl t--(open)
Ao-A,.
Ao-A,.
Ao-A;,
Ao-An
CE
CE
CE
CE
VSs(22)
DE
VSS(22)
DE
00-0.
10-1-,
GND
VSs('4)
GND
VSS('4)
II
Oo-Or
10-17
49·00f070A
Figure 8.
49-Q01071A
EPROM Read Timing
1 Machine Cycle
T4
ell \
(Ex1ernal)
Ao-A11
CE
10-17
T1
I
X
I
I
\
12
I
I
13
I
T4
!
\
\
X
Add....
I
\
)-------------<
'I
ReadDa1a
)----4g·001072A
3-63
N'EC
~PD7527A/28A/75CG28E
Timing Waveforms
EPROM (/JPD75CG28E only)
10- 17
Serial Interface
51
-----------(1
---+---<1
49-00107SA
SO _ _ _J
Clock
~
>C
Output
___
_ Data
_ _ _- '
49-001074A
1 - - - - -1Ifc----+J
Interrupt Input
CL11nput
RESET
49-001169A
Reset Input
POo Input
49-0010?3A
INTO
49-001168A
Differences Among the
~PD7527A/28A/CG28E
~PD75C028E
~PD7527A
~PD7528A
Program memory
4 Kbyte EPRO M
(2732)
connectable
on top
On-chip 2 Kbyte
ROM
On-chip 4 Kbyte
ROM
Data memory
(RAM)
160x4
128x4
160x4
High-voltage
output lines
All open-drain
outputs
On-chip load capacitor or open drain
output (bit by bit, mask optional)
VLOAD pin
No
Zero-cross
detection
Yes
Package
42-pin ceramic
piggyback DIP
bottom pin
compatible with
I'PD7527A/ 28A
Power supply
5V
3-64
Mask optional
42-pin plastic DIP
42-pin plastic
shrink DIP
2.7Vto6.0V
pPD7533/75CG33E
4-Bit, Single-Chip
CMOS Microcomputers
With AID Converter
t¥EC
NEe Electronics Inc.
Description
The IIPD7533 is a 4-bit, single-chip CMOS microcomputer with a 4-channel, a-bit A/D converter, a-bit
timer/event counter, and an a-bit serial interface. The
IIPD7533 has 30 I/O lines, a of which can be used to
directly drive LEDs. The IIPD7533 executes 67 instructions of the IIPD7500 series "A" instruction set.
The A/D converter has various temperature monitoring
appl ications that can be used with household electrical
appliances, such as air conditioners and electric
ovens. Other applications include health monitoring
equipment and cameras.
The IIPD75CG33E consists of a 2a-pin socket "piggybacked" on the lower 42-pin ceramic DIP. This socket
is configured to hold either a 2732A or 2764 EPROM.
For engineering purposes, programs can be tried and
debugged before ROM code submission.
Ordering Information
Part
Number
pPD7533C
42-pin plastic DIP
510 kHz
pPD7533CU
42-pin plastic shrink DIP
510 kHz
pPD7533G-22
44-pin plastic QFP
510 kHz
pPD75CG33E
42-pin ceramic piggyback DIP
510 kHz
Pin Configurations
42-Pin Plastic DIP or Plastic Shrink DIP
P43
P42
P4,
Features
D
D
D
D
D
D
D
D
D
D
D
50276 (NECEL-460)
P50
P5,
Cl'
DIVSEl
D 4-bit single chip microcomputer
D 67 instructions (subset of IIPD7500 series set A)
D Instruction cycle
- 5 liS at 5 V, 400-kHz clock at ceramic oscillation,
DIVSEL = high
- 10 liS at 5 V, 400-kHz clock at ceramic
oscillation, DIVSEL = low
Program memory (ROM): 4096 words x a bits
- External in the IIPD75CG33E
Data memory (RAM): 160 words x 4 bits
a high current output lines for LED direct drive
Input/output ports
- Two 4-bit input ports
- One 2-bit output port
- One 4-bit output port
- Three 4-bit input/output ports (two of these
can function in a-bit units)
- One 4-bit input/output port usable at bit level
Interrupts: two internal and one external
a-bit serial interface
Standby operation
-STOP mode
- HALT mode
On-chip system clock oscillator
- Ceramic resonator
- Full or 1/2 oscillation frequency
CMOS technology
Low power consumption
Single power supply
Maximum
Frequency
o! Operallon
Package
Type
POo/INTO/EVENT
PO,/SCK
P02/S0
P03/SI
P10
P1,
AN2
AN1
P62
83-002631A
3-65
t-IEC
pPD7533/75CG33E
Pin Configurations (cont)
Pin Identification
42-Pin Ceramic Piggyback DIP
42-Pln DIP, Shrink DIP, and Piggyback DIP
P43
Vss
P42
P50
pP075CG33E
No.
Symbol
1·4
P43-P40
P4,
P5,
5.6
P22, P21/PTOUT
Port 2 output
P40
P52
7-10
P73·P70
1/0 port7
5
Voo
Voo
P53
P21/PTOUT
P22
Vss
Voo
Cl2
P73
A7
Voo
P72
As
As
Cl'
OIVSEl
P7,
As
Ag
RESET
'0
11
Ao
A11
POolINTO/EVENT
A3
Vss
po,/SCi<
P32
'2
A2
A,o
P02/S0
P3,
'3
A,
CE
P03/S1
P30
'4
Ao
17
P'o
AVss
'5
16
10
I,
I,
15
12
10
11-14
P33·P30
Port 3 output
15
AID converter ground
16-19
AvSS
AN3-ANO
Analog input
20
VAREF
AID reference voltage input
21
Voo
Positive power supply
22-25
P63-P60
1/0 port6
P"
26-29
P13-P10
Port 1 input
P'2
30
P03/S1
Port 0 input/Serial input
P'3
pSo
31
P02/SD
Port 0 input/Serial output
ANO
ps,
32
P01/SCK
Port 0 input/(I/O) Serial clock
VAREF
PS2
33
POoIINTO/EVENT
Port 0 input/Interrupt O/Event
input
34
RESET
RESET input
35
DIVSEL
System clock selection input
36,37
CL 1, CL2
External clock input/System
clock terminal
P70
P33
AN3
AN2
AN'
Vss
13
Voo
PS3
83-002633A
44-Pln Plastic QFP
NO
N
~
P2,/PTOUT
P73
~
~
....
o:t
~
C\lMU)O
011
~
'II'
~
(I)
>
IS'I
~
....
1ft
~
NC')N
It)
a
IS'I
..J
a" U
NC
Cl'
P72
OIVSEl
P7,
P33
RESET
POo/lNTOI
EVENT
PO,/SCK
P32
P02/S0
P3,
P03/S1
P30
P'o
P70
AVss
P"
AN3
P'2
83-002632A
3-66
Function
1/0 port 4
38-41
P53-P50
1/0 port5
42
Vss
Ground
NEe
pPD7533/75CG33E
Pin Functions
Pin Identification (cont)
POO-P03 [Port 0]
44-Pin QFP
No.
Symbol
1,44
P2l/PTOUT, P22
Port 2 output
PlJ-P70
I/O port 7
2-5
Function
6-9
P33-P30
Port 3 output
10
Avss
A/D converter ground
11-14
AN3-ANO
Analog input
15
VAREF
A/D reference voltage input
17
Voo
Positive power supply
18-21
P63-P60
I/O port 6
22-25
P13-P10
Port 1 input
26
P03/S1
Port 0 input/Serial input
PO O-P0 3 function as port O. POo also functions as a
count pulse input pin for the timer/event counter
(EVENT) or as interrupt 0 (INTO). POl also functions as
a serial clock input/output pin (SCK) for the serial
interface. P02 functions as a serial data output pin (SO)
and pins P03 as a serial data input pin (SI). The P0 1/SCK
and P02/S0 pins are three-state input/output.
The shift mode register (SMo-SM3) determines the
operation mode of the port 0 input/output pins; however, the data on POO-P03 can be loaded into the
accumulator at any time by executing a port input
instruction (IP/IPL). This is possible even when P01P03 are functioning as the serial interface.
After a RESET, POO-P03 become input ports (high
impedance).
27
P02/S0
Port 0 input/Serial output
28
P01/SCK
Port 0 input/ (I/O) Serial clock
29
POo/INTO/EVENT
Port 0 input/Interrupt O/Event
input
P10-P13 [Port 1]
30
RESET
RESET input
31
DIVSEL
System clock selection input
32,34
CL1,CL2
External clock input/System
clock
P1o-P13 function as port 1. Execution of an IP or IPL
instruction reads data present on P1o-P13 into the
accumulator. Tie any unused lines of P1o-P13 to VDD or
Vss·
35-38
P53-P50
I/O port 5
P21-P22 [Port 2]
39
Vss
Ground
40-43
P43-P40
I/O port 4
16,33
NC
No connect
P2l-P22 function as port 2 with an output latch. When
an output instruction (OP/OPL) to port 2 is executed,
the middle 2 bits (Al and A2) of the accumulator are
latched by the output latch and, at the same time,
output to P2l-P22.
28-Pin EPROM Socket on 42-pln Piggyback DIP
No.
Symbol
1,26-28
Voo
Positive power supply
2. 14.22
Vss
Ground
Function
20
CE
Chip enable output
3-10,21,
23-25
Ao-All
Address bus
11-13,
15-19
10-17
Data bus
After being written once, the output latch contents
remain until they are rewritten by an output instruction
or a reset. The status of the corresponding output
signal also remains. After a reset, the output latch
contents become undefined, all output signals are
disabled, and the output drivers are turned off.
P2 l is also used as an output pin (PTOUT) for the
timer-out F/F signal (PTOUT). Bit 3 (CM3) of the clock
mode register controls the PTOUT output. When CM3
is 1, TOUT is ORed with the P2l output latch contents
and sent to the output driver. Therefore, to output the
P2l output latch contents, reset CM3 to 0 to inhibit the
TOUT signal.
Note that soon after the RESET signal is asserted, CM3
is reset and TOUT is inhibited. However, since the
output latch contents are undefined after a reset, to
output the TOUT signal, first write 0 in the P2l output
latch and then set CM3 to 1 to output TOUT.
3-67
an
ttlEC
jlPD7533/75CG33E
P30-P33 [Port 3]
P60-P63 [Port 6]
P30-P33 function as port 3 with an output latch: When
an output instruction to port 3 is executed, the accumulator contents are latched and output.
P6o-P63 function as the 4-bit input latched, three-state
output port. The individual lines can be programmed
as either inputs or outputs.
Once data is written in the output latch, the data is held
until the next output instruction to port 3 is executed or
RESET is asserted. After a reset, the output latch
contents become undefined and the output driver is
turned off.
In input mode, data present at this port is read into the
accumulator by the execution of an IP or IPL instruction. Accumulator data written to this port by the
execution of an OP, OPL, ANP, or ORP instruction is
statically latched, and remains unchanged until rewritten. This data, however, is not output since the
output buffer is disabled and placed in the high
impedance state.
P40-P43 [Port 4]
P50-P53 [Port 5]
P4o-P43 function as port 4 and P50-P53 function as port
5. When an input instruction isexecuted, the data on
these pins is read into the accumulator. When an
output instruction is executed, the accumulator
contents are latched and output. After the data is
written into the latch, it is held until the next output
instruction to ports 4 or 5 is executed, or RESET is
asserted.
Ports 4 and 5 can work as a pair enabling data (input
with the IP54 instruction and output with the OP54
instruction) in 8-bit units. The high four bits of data are
from the accumulator and the low four bits are from
memory (addressed by HL).
Ports 4 and 5 automatically set in the input mode (high
impedance output) after a reset or when the input
instructions to these ports are executed. After a reset,
the output latch contents become undefined. Both
ports 4 and 5 can drive LEOs directly.
Note that after the port changes from output mode to
input mode, the data on the line is unstable when the
input instruction that changes the mode is first executed. It is strongly recommended that you re-execute
the input instruction considering the input/output
mode switching time. This will insure reading stable
data.
The bit manipulation instruction affects the specified
bit only. So when the output latch contents are undefined, (immediately after a reset), initialize the output
latch contents with an output instruction before the bit
manipulation instruction is executed.
3-68
In output mode, accumulator data written to the
specified port line by the execution of the OP, OPL,
ANP, or ORP instruction is statically latched and
output to the P6n pin. Data present at P6 n is read into
the accumulator by the execution of the IP or IPL
instruction, making it possible to read the contents of
the P6 n output latch.
All lines of port 6 are initialized to the high impedance
state at Reset. Leave any unused lines open (if outputs)
or tied to VDD or Vss (if inputs).
The port 6 mode select register (MSR) controls the
function of the individual port 6lines. The execution of
the OP or OPL instruction loads the port 6 MSR with
the accumulator contents. The 4-bit immediate data
operand or the contents of the L register must be set to
OEH. Figure 1 shows the format of the port 6 MSR.
Figure 1.
Port 6 MSR Format
I
PM3
I
PM2
I
I
PM,
[
I
PMo
I
I'---P60
P6,
' - - - - - - - - P62
' - - - - - - - - - - - P63
PM n
Pori 6 Selection
P6n input [output buffer high-impedance]
P6 n output [output buffer on 1
83-002634A
t-IEC
pPD7533n5CG33E
P70-P73 [Port 7]
Pin Functions, pPD75CG33 EPROM
Port 7 is a 4-bit input or latched three-state output port.
The execution of an IP or IPL instruction execution
reads data present at this port into the accumulator.
Accumulator data written to this port by the execution
of an OP, OPL, ANP, or ORP instruction is statically
latched and remains unchanged until rewritten.
Ao-A11 [EPROM Address]
Upon reset, all lines are initialized to the highimpedance state. Leave any unused lines open (if
outputs) or tied to Voo or Vss (if inputs).
Ao-A11 output the contents of the EPROM program
address counter. A reset leaves Ao-A11 undefined.
10-17 [Data Bus]
10-17 input the contents of the EPROM data bus.
CE [Chip Enable]
ANO-AN3 [AID Input Terminal]
CE outputs the EPROM chip enable signal. (Active
low.)
ANO-AN3 are the 4-channel ND converter input terminals. The AID converter uses a successive approximation method.
Voo [Power Supply], VSS [Ground]
VAREF [AID Converter Positive Reference]
The voltage on VAREF determines the full scale analog
voltage.
Voo is the positive power supply pin with the same
voltage as the lower portion pin 21. Vss is the ground
pin with the same voltage as the lower portion pin 42.
The following voltages are supplied to the 2764 or
2732A pins from Voo or Vss.
AVSS [AID Converter Ground]
Avss is the ground for the ND circuit.
CL 1, CL2 [Clock]
CL 1 and CL2 connect external oscillator elements to
the system clock. Connect a ceramic resonator to
these pins. ·If an external clock is used, place a buffer
between the clock source and the CL 1 and CL2 pins.
When connecting the oscillation parts to the CL 1 and
CL2 pins, use the shortest wiring possible. Ground the
capacitor as close to the Vss pin as possible.
DIVSEL [System Clock Divider Selection Input]
DIVSEL selects whether the system clock runs at
ceramic osci lIation freq uency, or at one-half the ceram ic
oscillation frequency. If a logic 0 (Vss) is connected to
DIVSEL, the system clock is one-fourth the ceramic
oscillation. If DIVSEL is high, then the system clock will
be one-half of the ceramic oscillation.
RESET [Reset]
A high on RESET activates this input.
Voo [Power Supply]
Voo is the positive power supply pin.
Vss [Ground]
Vss is the ground pin.
Pin Number
2764
2732A
20
Symbol
Vpp
28
24
Vee·
22
20
DE
12
Vss
2
14
A12
Voltage
Voo pin 21 = +5 V
Voo pin 21 = +5 V
Vss pin 42 = 0 V
. Voo pin 21 = +5 V
Vss pin 42 == 0 V
NEe
pPD7533/75CG33E
Block Diagram
INTO/EVENT/POO
SCK/PO,
so/po,
Sl/PO,
EVENT
Clock
Control
Cl
P10-P103
P30·P33
P40-P43
Program Memory
4096
Instruction
Decorder
x 8 Bits
P50·P53
Cl
¢
P60·P63
Cl' Cl2
111
voo
vss
P70·P73
RESET
83-0026358
Absolute Maximum Ratings
Capacitance
TA =25°C
TA = 25°C, Voo =0 v
Power supply voltage, VDD
limits
-0.3 to +7.0 V
Input voltage, VI
-0.3 V to VDD + 0.3 V
Parameter
Output voltage, Vo
-0.3 V to VDD + 0.3 V
Input
capacitance
High level output current, 10H
-17 rnA (1 pin)
-20 rnA (all output ports)
Low level output current, 10L
17 rnA (1 pin)
80 rnA ports 2,3,4,7 (total pins)
80 rnA ports 0,5,6
Operating temperature, TOPT
-10 to +70°C
Storage temperature, TSTG
-65 to +150°C
AID Vss, Avss
-0.3 to +0.3 V
AI D reference, VAREF
-0.3 V to VDD
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
3-70
Symbol
Min
Max
Unit
CIN
15
pF
Output
capacitance
COUT
15
pF
I/O
capacitance
CIO
15
pF
Test
Conditions
f=1 MHz
Unmeasured
pins are 0 V.
NEe
J.lPD7S33nSCG33E
DC Characteristics
DC Characteristics
TA = -10 to +70·C, Voo = 2.7 to 6.0 V, DIVSEL = 1
TA = -10 to +70·C, Voo = 2.7 to 6.0 V, DIVSEL = 1
Limits
Parameter
Symbol
Min
Max
Unit
0.7 Voo
Voo
V
High level
input voltage
(other than
CL 1, CL2)
VIH1
High level
input voltage
(CL1, CL2)
VIH2
Voo - 0.5
Voo
V
Low level
input voltage
(other than
CL1, CL2)
VIL1
0
0.3 Voo
V
Low level
input voltage
(CL1, CL2)
VIl2
0
0.5
Conditions
specified by
oscillation
characteristics
Limits
Parameter
Symbol
Test
Conditions
Min
Max
Unit
Supply current 1001
1.0 (typ)
3.0
mA Operating mode:
fcc = 500 kHz
1002
250 (typ)
750
/iA HALT mode:
fcc = 500 kHz
300 (typ)
900
/iA (75CG33:
Voo = 4.5 - 6.0 V;
fcc = 500 kHz)
0.1 (typ)
10
25 (typ)
200
/i A STOP mode
/i A (75CG33:
Voo = 4.5 - 6.0 V)
1003
V
AC Characteristics
TA = -10 to +70·C, Voo = 2.7 to 6.0 V
rligh level
VOH
output voltage
V
Voo -1.0
Voo - 0.5
V
Voo - 0.5 Voo - 0.2
Low level
VOL
output voltage
High level
IUH1
input leakage
current (other
than CL 1, CL2)
High level
input leakage
current (CL1,
CL2)
Test
Conditions
IUH2
Parameter
Symbol
Min
Max
Unit
10H = -100 /iA
Cycle time
tCY
3.92
200
/is
9.52
200
/is
Limits
Voo = 4.5-6.0 V
IOH=-2 mA
(P63 only)
EVENT input
frequency
fE
0
510
kHz
210
kHz
0.6 (typ)
2.0
V
Voo = 4.5-6.0 V
10l = 15 mA
EVENT input
high duration
tEH
0
0.8
0.7 (typ)
2.5
V
(75CG33:
Voo = 4.5 - 6.0 V)
EVENT input
low duration
tEL
2.2
/is
0.4
V
10l = 1.6 mA
SCK cycle
time
tKCY
4.0
/is
3.92
/is
0.5
V
3
/i A
20
Low level
IUL1
input leakage
current (other
than CL1, CL2)
-3
Low level
input leakage
current (CL1,
CL2)
-20
IUL2
V
Voo = 4.5-6.0 V
IOH=-1 mA
except P63
/iA
/i A
/i A
10l = 400/iA
/is
VIN = Voo
VIN =Voo
SCK high,
low level
duration
tKH,
tKL
VIN = 0 V
VIN =OV
High level
li.OH
output leakage
current
3
/i A
VOUT = Voo
Low level
IlOL
output leakage
current
-3
/i A
VOUT = 0 V
Test
Conditions
Voo = 4.5-6.0 V
Voo = 4.5-6.0 V
Voo = 4.5-6.0V
Input
Voo = 4.5-6.0 V
Output
Voo = 4.5-6.0 V
Input
10.0
/is
9.52
/is
Output
1.8
/is
1.76
/is
Input
Voo= 4.5-6.0 V
Output
Voo = 4.5-6.0 V
4.8
/is
Input
4.6
/is
Output
SI setup
time (SCK high)
tSIK
300
ns
SI hold
time (SCK high)
tKSI
450
ns
SCK low
to SO
output delay
time
tKSO
INTO high,
low level
duration
tIOH,
tlOl
10
/is
RESET high,
low level
duration
tRSH,
tRSl
10
/is
850
ns
Voo = 4.5-6.0 V
1200
3-71
II
tttrEC
pPD7533/75CG33E
Data Memory, STOP Mode Data Retention
Characteristics
TA=-10to+70·C
limits
Parameter
Symbol
Min
Typ
Max
Unit
Data
retention
supply voltage
VOOOR
2.0
6.0
V
Data retention
supply current
IOOOR
RESET setup
time
tSRS
0
ps
Oscillation
stabilizing
time
tos
20
ms
Test
Conditions
A/D Converter Characteristics
TA = -10 to +70·C, Voo = +5.0 V ±5%,
Vss = Avss = 0 v, VAREF = Voo - 0.5 V to Voo
limits
Parameter
Symbol
Min
Resolution
Typ
pA
10
VOOOR = 2.0 V
Ceramic
resonator:
when VOO
greater than
4.5 V
Unit
Test
Conditions
Bits
8
Absolute
accuracy
0.1
Max
±1.5 LSB
Conversion
time
tCONV
Sampling
time
tSAMP
Analog input
voltage
VI AN
Analog input
impedance
RAN
VAREF current
IAREF
9
tCyc· Voo - 0.5
::s VAREF::S VOO
tCyc·
Avss
VAREF
Mo
1000
0.4
V
2
mA
2
• tCYC = (DIVSEL = 1)
fcc
Data Retention Timing
I
J
Voo ---t--lJ\
STOP
I· '
Mode
Data
"-Iloperaling
Mode
HALT
• 'I
Rete::O:o:Ode_l'Ir --''----:---
STOP
'SRS=--!
~
Instruction
RESET
Mode
Execution
/
--~------------~
--to
r'I
~
'os
~
83-002636A
Oscillator Characteristics
TA = -10 to +70·C, VOO =2.7 to 6.0 V, DIVSEL = 1
limits
Test
Conditions
Oscillation
Configuration
Parameter
Min
Typ
Max
Unit
Ceramic
See figure 3
Oscillation frequency (fcel
390
500
510
kHz
VOO = 4.5 to 6.0 V
390
500
510
kHz
VOO = 4.0 to 6.0 V
390
500
510
kHz
Voo = 3.0 to 6.0 V
DlVSEL = 0
390
400
410
kHz
VOO = 2.7 to 6.0 V
DlVSEL = 0
External clock
See figure 3
Stabilization time
20
ms
Voo greater than 4.5 V
CL 1 input frequency
10
510
kHz
Voo = 4.5 to 6.0 V
10
210
kHz
1.0
50
ps
1.0
50
ps
CL 1 input high, low level duration (tcH.tcLl
3-72
Voo = 4.5 to 6.0 V
t-IEC
pPD7533/75CG33E
Timing Waveforms
AC Timing Measuring Points (Except CLf)
0.7 VOO
0.3 VOO
.>
Measuring Points
Serial Transfer Timing
~ 0.7 Voo
---.. 0.3 Voo
Clock Timing
SI---+---(I
1+------1IfC----.,----.J
so
Cl1
Output Data
>C
------'
83-002640A
Interrupt Input Timing
EVENT Timing
INTO
RESET Input Timing
83-002639A
RESET
3-73
II
ttiEC
pPD7533n5CG33E
Functional Description
Standby Control
System Clock Generator
The HALT F/F and the STOP F/F; comprise the control
circuitry for standby mode (figure 2). The STOP F/F is
set by the STOP instruction. When the STOP F/F is set
the ceramic oscillator stops. The rising edge of th~
RESET input resets the STOP F/F.
The ceramic 0s,cillator circuit generates the system
clock for th&pPD7533. Figure 2 shows that the oscillator
circuit for the pPD7533 includes a ceramic oscillator
two divide~by-two circuits, the DIVSEL input, and
con1rol circuitry for the standby modes, HALT and
STOP.
Figure 3 shows that the ceramic oscillator requires that
a ceramic resonator be connected to the CL 1 and CL2
pins. An external clock can also be input at CL 1. In this
case, th~osdl!ator operates as an inverted buffer.
Figure 2 shows that the output frequency from the
ceramic oscillator cOnnects either directly to the clock
sele~tor or via a divide-by-two circuit. The selector is
controlled QY the DIVSEL line. If DIVSEL is low the
divide-by-two frequency is selected. This opti~n is
used during a low power operating mode. If DIVSEL is
high, then the direct frequency is chosen. The output
of the selector is used as system clock (CL), and is also
divided by two to supply the CPU clock (If».
The HALT instruction sets the HALT F/F and inhibits
the input of the half-frequency divider which generates
the CPU clock. As a result, only the CPU clock is
stopped in HALT mode. The RELEA~E signal resets
~he HALT F/F. RELEASE becomes active when any
mterrupt request flag isset, or at the falling edge ofthe
.RESET input.
While RESET is active, the HALT F/F is set and the
chip goes into the HALT mode. At.a powei'-~n Reset,
the ceramic oscillation is driven when the RESET input
signal becomes high.
Figure 3.
Clock Driver Configuration
30pF
..-----i 11---...-....
CL 1
Table 1 shows how DIVSEL selects. the system and
CPU clocks, and machine cycle timing.
Table 1.
DIVSEL
Clock Selection
System Clock
·ICll
CMOS
Inverter
1--+-....
CL2
CL2
CPU Clock
low
200 kHz
11/11
100 kHz
High
400 kHz
200 kHz
Machine Cycle
lOpS
5ps
83-o02644A
Figure 2. System Clock Generator
: I - - - - - - l c - r - - - STOP Instruction
1---+-- ,HALT Instruction
4--RESET
rl----4---
Standby Release
........ r - - - RESET
L..f---------RESET
'--
J
CLI
Ceramic
Oscillator
CL2
1---4>CPU
'-----------+ CL To Timer/Event Counter
DIVSEL 0 - - - - - - - - - - - - - - 1
83-0026438
3-74
ttt{EC
pPD7533/75CG33E
It takes a short period of time for the osci Ilator output to
become stable. To prevent errors due to an unstable
clock, the HALT F/F is set to inhibit the CPU clock
while the RESET input is high. Therefore,. the highlevel pulse width for the RESET input should be wide
enough to cover the required time for the ceramic
resonator oscillation to stabilize.
Figure 5.
Format of Clock Mode Register
I CM. I CM, I CM, I CM.
I
I
CM,
CM,
CM.
• • •
• • ,
• ,
Clock Control
Figure 4 shows that the clock controller contains a
4-bit clock mode register (CMO-CM3), prescalers 1-3,
and multiplexers. The clock controller selects the
clock sources and prescalers, and supplies the count
pulses (CP) to the timer/event counter. The clock
sources are the system clock generator output (Cl) or
the EVENT pulse.
-
0
EVENT
,
1
EVENT
,
0
0
CLxli
0
1
EVENT
0
CL
1
CM.
Figure 5 shows the format of the clock mode register.
CL x 2!s
EVENT x
0
,
, ,
,
,
The OP 12 or OPl (l = 12) instruction sets codes in the
clock mode register. CM3 designates the output of the
timer-out signals. If CM3 = 1, the output of the timerout F/F (TOUT) is available at the PTOUT (P21) pin.
CP Count Pulse
i4
xi
xi
EVENT
Timer~out
F/F
0
PTOUT inhibited
1
PTOUT output enabled
83-002646A
Figure 4.
Clock Controller Block Diagram
Internal Bus
+----OP, OPL Instruction Execution
Timer/Event Counter _ _ _....J
CL
EVENT [POoJINTO]
O-------1~~--+1=$$$~[)
~~~~:>-
r
____
Timer/Event Counter
CP
83-0026456
3-75
t-IEC
pPD7533n5CG33E
Timer/Event Counter
Event Counter Operation
Figure 6 shows the timer/event counter has an 8-bit
count register, 8-bit modulo register, an 8-bit comparator, and a timer-out flip flop.
To use the timer/event counter as an !lvent counter,
input the external event pulse into the POa pin, and
select POa' as the count pulse (CP) for the clock
controiler. Th'e count register counts the external event
pulses input at the POa pin, either as they are, or
frequency divided.
Timer Operation
After the TAMMOD instruction sets a count value in the
modulo register and the TIMER instruction clears the
contents of the count register, the timer starts counting
count pulses (CP). If an external clock is used, the
count pulses are synchronized with the rising edge of
CL 1 or the POa input.
When the value of the modulo register equals the value
of the count register, the comparator generates a
coincidence signal (INTT) to set an interrupt request
flag. Then it clears the count register to repeat the
counting. In this manner, the timer functions as an
interval timer whose interval is set by the modulo
register.
As a result, the timer/event counter operates as an
event counter that generates interrupts after observing
the number of counts (events) specified by the modulo
register. The TCNTAM instruction can read the current
count at any time.
Set the modulo register with the number of count
pulses minus one. If set to 0, no counting will occur
because the counter register is held at 0 (both the
detection of coincidence and zero-clearing are simultaneously madej.
Regardless of. any instructions, the count pulses are
always input into the count register, updating the
count value. If the contents of the count register are
equal to those of the modulo register, the INTT request
flag is then set. For this reason, inhibit INTT interrupts
when not using the timer.
Figure 6.
Block Diagram of Timer/Event Counter
I
J
TAMMOD
8
Instruction Execution
TCNTAM
Instruction
Execution
I
I
8-Blt Modulo Reg.
8
8
I
8·Bi. Compara'or
J
INTT
i8
CP -
{
Count Hold
Circuit for
TCNTAM Execution
'I
I
-:
I
a·BUCoun' Reg.
CLR
I
_CLR
~
TlmoroutF/F
I
~ 1--+ Serial Interface
TOUT
and Port 2
T
TImer Reset
Instruction Execution
83-002647B
3-76
NEe
pPD7S33nSCG33E
The end of a 1-byte transfer can be confirmed by
testing the INTS RQF with the SKI instruction instead
of interrupt processing.
Serial Interface
As figure 7 shows, the serial interface includes an 8-bit
shift register, a 4-bit shift mode register, and a 3-bit
counter.
The following three types of serial clock sources are
available: system clock f/J, external clock (SCK input),
and timer-out F/F output signal (TOUT). Bits SM2-SMO
of the shift mode register select the clock source.
The serial clock controls serial data 1/0. At the falling
edge of the serial clock (SCK), the SO line outputs the
most significant bit (7) of the shift register. The
contents of the shift register are shifted by one bit atthe
rising edge of the next serial clock (n -0 n+1). At the
same time, the data on the SI line is loaded into the
least significant bit (0) of the shift register.
If the system clock f/J is chosen, execute the SIO
instruction to supply the clock to the serial interface,
controlling the input/output of serial data whilef/J is
output from the SCK pin.
After eight f/J pulses, the clock is automatically discontinued by holding the SCK output at a high level.
Therefore, the input/output of serial data automatically
stops after each byte has been transferred. Consequently, the software does not need to control the
serial clock and the transfer rate is determined by the
system clock frequency ..
The 3-bit counter (octal counter) counts up the serial
clocks and generates an internal interrupt signallNTS
at every count of 8 clocks (atthe end of a 1-byte serial
data transfer). It then sets the interrupt request flag
(INTO/S RQF). The TAMSIO instruction sets data in
the shift register during the transmission of serial data,
then starts transmission. At the end ofthe transmission
of each byte (8 bits) an internal interrupt (INTS) is
generated.
In this mode, after six machine cycles from the execution of the SIO, the TSIOAM instruction can read out
the received data from the shift register or can write in
the next transmit data.
The SIO instruction also starts the reception of serial
data. The. received data is taken from the shift register
by executing the TSIOAM instruction after an interrupt
(INTS) is generated by the reception of one. byte of
data.
.
Figure 7.
Figure 8 shows the shift mode register format.
Serial Interface Block Diagram
/
I
Internal Bus
A
IP,IPL~_
1
P03/S1
LSB I
I
I
I
I
I
-OP,OPL'
I MSB
I
I
l-- I
Shift Mode Register
!
1
~
-1>0-
-L
~
3·bllCNT
--
l
.,.".
PDoIINTO/EYENT
8-blt Shift Register
I
I
8 -TAMSIO·
SM3
.......
.......
0--
TSIOAM*_ 8
I
r-t>
P02/SI
4
TOUT
INTO/EVENT
r--R
.n*Instructlon Execulion
INTS
RS F/F
Q
S
•
SIO'
'--83~26748B
3-77
-=~
ftiEC
pPD7533/75CG33E
Figure 8.
Format of Shift Mode Register
SM z
SM 1
SMO
POs/SI
POz/SO
a
0
0
Port input
Port input
0
Serial Operation
Port input
Stops
Outputs ¢ continuously
0
Outputs TOUT continuously
0
0
SI input
SO output
0
Bit SM3 selects the interrupt source in the following
manner:
SM3
Interrupt Source
o
INTS
INTO
1
If the external clock (SCK input) is selected, the serial
clocks are input from SCK. When the eighth external
serial clock is input, an internal interrupt (INTS) is
generated, signalling the end of a 1-byte data transfer.
Since the serial clocks are not internally inhibited, the
external clock must hold the signal high after eight
clocks. The external serial clock determines the transfer
rate. The serial interface can be operated from DC to
the maximum rate in the electrical specifications.
If TOUT is selected, the half-frequency divided coincidence signal of the timer/event counter is the serial
clock. This serial clock controls the input/output of the
serial data and is output from the SCK pin.
3-78
SCK input
Operates with external clock
SCK output (¢ x 8)
Operates with
SCK output (TOUT)
Operates with TOUT
¢
The count pulse supplied to the timer/event counter
and the value set in the modulo register determine the
transfer rate. The end of a 1-byte data transfer is
signalled by INTS. TOUT is not inhibited automatically,
therefore the program should stop TOUT at intervals of
16.
To use the external clock or the TOUT signal, execute
the SIO, TAMSIO or TSIOAM instructions while the
serial clock (SCK) is held high. Operation cannot be
guaranteed if these intructions are executed over the
rising or falling edge of SCK, or at the low level.
In a system that does not require serial data transfer,
the 8-bit shift register can be ued as a register with the
serial operation stopped. The TSIOAM or TAMSIO
instruction can read or write data.
NEe
pPD7533/75CG33E
Analog to Digital Converter
Figure 10.
ThepPD7533 integrates a 4-channeI8-bit AID converter
with separate positive reference and ground from the
device power supply. Figure 9 shows that the AID
converter includes an AID converter mode register,
successive approximation (SA) register, and end of
conversion (EOC) control circuitry.
I
ADS
I
AID Conversion Mode Register Format
X
I ANI1 I ANlo
L
AID Converter Mode Register
The AID converter mode register is a 4-bit internal port
that controls the AID circuitry. The lower two bits,
ANIO and ANI1, select which analog signal (ANO-AN3)
is input to the AID converter. The most significant bit,
ADS, initiates the AID conversion. If ADS is set to a
logic1, the analog signal selected by ANI1 and ANIO is
converted to 8-bit digital data. Upon completion of the
data conversion, ADS is cleared to O.
Analog Input Selection
0
0
ANO
0
1
AN1
1
0
AN2
1
1
AN3
AID Conversion Start
1
Initiates AID Conversion
0
AID Conversion Completed
II
X = Do Not Care
83-002650A
Figure 10 shows the format for the AID conversion
mode register.
Figure 9.
AID Converter Siock Diagram
OPOAW
OPL"
ADM Register
[L~AH[
ADS
r-
r--
J
3
ANI1
ANIO
I
AID Start
:
Control
IPOtW
IPl*
[ EOC
Circuil
[L~AH[
I
I
ANO
High
~
Mux
AN,
SA
Register
~-~.
AN3
IPJ
IPL"
~
..
ID
E
~
[L~9H[
Low
IPJ
I
Analog Voltage Selector
VAREF
R/2
11 1
R
R
1 1 'I ""."~,
R
I
IPL·
[L
~8H[
R/2
~
AVss
"'Instruction Execution
83-002649A
3-79
NEe
pPD7S33nSCG33E
Successive Approximation [SA]
Reading Converted Data
The 8-bit data converted from the analog signal using
the successive approximation method is stored in the
SA register. When ADS is set to a logic 1, the contents
of the SA register are undetermined. The SA register is
set to 7FH after a reset.
Internal port 9 specifies the upper four bits of the SA
register. Therefore, execute an IP 9 or IPL (L = 9)
instruction to read the data in the accumulator.
End of Conversion [EOC] Flag
The EOG flag specifies the completion of an AID
conversion. When ADS is set to 1, the EOG flag is set to
a logic 0 and an AID conversion starts. When the 8-bit
AID conversion is complete, the EOG flag is set to a
logic 1. The EOG flag resides in bit 2 of internal Port A.
The IP OAH or IPL instruction can read the contents of
Port A when the L register is set to OAH. The contents of
Port A (other than bit 2) will be read as a logic O. The
EOG flag is set to 1 after a reset.
AID Converter Operation
An OP OAH or OPL instruction selects one of four
analog signals and starts a conversion when the L
register is set to OAH. The lower two bits of the
accumulator specify which analog signal will be converted. Bit 3 of the accumulator sets to 1 to initiate the
AID conversion. The AID conversion requires 9
machine cycles for completion. When the conversion
is complete, the EOG flag is set.
Internal port 8 specifies the lower four bits of the SA
register. Therefore, execute an IP 8 or IPL (L = 8)
instruction to read the data in the accumulator. Do not
read the SA register until EOG is set to 1.
Figure 12 shows the configuration forthe AID converter
reference voltage during standby mode.
Interrupt Function
The tJPD7533 provides one external interrupt and two
types of internal interrupts. The POo pin is used as the
input pin for external interrupt INTO. INTO shares
priority and vectored addresses with internal interrupt
INTS. Figure 13 shows the interrupt controller block
diagram.
Figure 12.
Configuration of VAREF for
Standby Mode Operation
pP07533
5V ____~VD~D+-~_____
P63
....
....
In order to assure an accurate data conversion, do not
execute an output instruction when EOG is a logic O.
VAREF
Figure 11 shows how the analog input voltage corresponds to the converted digital data.
I
Figure 11.
AID Conversion Graph
: Resistor
I String
I
FFH
~
c
!
AVSS
FEH
FDH
'm
Q
~
~
03H
o
U
02H
01H
VAREF
High Level
VAREF approximately = Voo
Low Level
or High Impedance
V AREF approximately = 0 V
83-0026S2A
Analog Input Voltage
3-80
P63 Output
t\fEC
Figure 13.
pPD7533/75CG33E
Interrupt Controller Block Diagram
SM3
INTS
INTO/PO. - ;_ _
·SIO
--.:JLr---------'
Generator
INTT
--------1
·TIMER - - - - - - - - - - - - '
*Instruction Execution
L~====:t:::==[>--------- Standby
Release
83-0026538
Standby Function
The tJPD7533 has two types of standby modes (STOP
and HALT) to minimize power consumption during a
prog ram standby state. STOP mode is set by the STOP
instruction and HALT mode by the HALT instruction.
When standby mode is set, program execution is
stopped, and the contents of all internal registers and
data memory are held. However, it is possible to
operate the shift register and the timer/event counter.
An interrupt or reset releases standby mode. Since an
interrupt releases standby mode, neither STOP nor
HALT modes can be set if an interrupt request flag is
set. Therefore, when setting standby mode when there
is a possibility of a request flag being set, first reset the
interrupt request flag by processing the interrupt in
advance or by executing the SKI instruction.
The major difference in the two modes is that crystal
oscillation (el) stops in STOP mode but does not stop
in HALT mode.
In STOP mode, it is possible to go into data retention
mode by lowering the power supply voltage. During
data retention mode, all operation stops and only the
data RAM stays intact.
Table 2 shows the differences between STOP and
HALT modes.
Table 2.
Differences Between STOP and HAL T Modes
Mode
Operation
STOP Mode
HALT Mode
Ceramic Oscillation
X (1)
0(2)
1/2 Ceramic Oscillation
X (1)
X (1)
CPU
X (1)
X (1)
Serial 110
Timer IEvent Counter
AID Converter
Release of Standby
Mode
(3)
(2)
X (1)
0(2)
X (1)
0(2)
RESET
INTOIS ROF
NTIROF
RESET Input
Note:
(1) Not possible
(2) Possible
(3) Possible depending on clock source selected
3-81
fttIEC
pPD7533nSCG33E
$TOP Mode
In STOP mode, ceramic oscillation and the halffrequency divider stop. The CPU stops and the operations requiring the system clock (CL, 0) stop.
Release from STOP mode is with the RESET input
only. All other functions cease to operate.
In order to minimize power consumption, the current
flowing through the resistor ladder oftheA/D converter
must be minimized. To minimize power consumption,
turn off the power to theVAREF pin.
Note that ceramic oscillation stops and disables the
system clock during STOP mode by bringing CL2 to
ground. Therefore, if the external Clock is connected to
CL 1 and a STOP instruction is executed, the CPU will
enter HALT mode instead.
HALT Mode
In HALT mode, only the half-frequency divider circuit
stops in the clock generator circuit (CL operates, ¢
stops). Therefore, the CPU and .the operation of the
serial interface (when using ¢ as a serial clock) stop.
However, since the clock control circuit is still in
operation, it can select the CL signal from the clock
generator or the EVENT input and supply the count
pulse (CP) to the timer/event counter.
Consequently, the timer/event counter can be operated
in HALT mode. The serial interface operates if a serial
clock other than ¢ (such as the external clock, TOUT
signal) is selected. The HALT mode is released by the
RESET input or an interrupt, even if the interrupt is
disabled.
Release from Standby Mode by Interrupt
If the interrupt master enabfeF/F is disabled, the·
instruction following the STOP/HALT instruction is
executed regardless of the state of the interrupt enable
register (interrupt routine is not initiated). In this case,
the interrupt request flag is left set. If necessary, it can
be reset by the SKI instruction.
After any release, operation resumes with the same
register contents as before standby mode.
Release From Standby Mode with RESET
Both STOP and HALT modes are released unconditionally by the RESET input. Figure 14 shows the
release timing.
If the device is reset during STOP mode, the low to high
transition of the RESET pin will take the processor
from STOP mode to HALT mode. When RESET goes
high to low, the HALT mode is abandoned, and after a
normal reset operation, the PC is initialized to O. Only
the data memory will stay intact during the HALT
mode, but all registers become undefined.
If the device is reset during HALT mode, the high to low
transition of RESET will release the device from standby
mode. After a normal reset operation, the PC is
initialized to O. Only the data memory will stay intact
during the HALT mode, but all registers become
undefined.
Figure 15 shows the release from HALT mode by
RESET.
Release from STOP mode by RESET
Figure 14.
R~:~ ~~TO~P ~~
___
The standby mode is released when the interrupt
request flag is set by an interrupt source, whether
interrupts are disabled orenabled. However, the operations after release differ in each case.
__
______
~~I_____
~ HALTMode.1
STOP
Mod.
.
~
Reset Operation
pc=o
Clock Oscillation
Begins' .
83-Q02654A
If the interrupt master enable F/F is enabled, and if the
interrupt is enabled, the corresponding interrupt routine
is initiated after execution of one instruction after the
STOP/HALT instruction. Then, the result flag is reset.
IHhe corresponding bit of the interrupt enable register
has been reset, execution of instructions starts after
the STOP/HALT instruction, and the interrupt routine
is not initiated. In this case, the request flag .for release
remains set. If necessary, reset the request flag with the
SKI instruction.
3-82
Figure 15.
Release from HAL T Mode by RESET
RESET~
- - - H A L T Mod'!
.1 .. •
Raset Operation'
PC=o
83-002655A
t\'EC
pPD7S33nSCG33E
Reset Function
Power-on Reset Circuit
The pPD7533 is reset and initialized by the input of the
RESET signal (active high).
Figure 16 shows an example of the simplest power-on
reset circuit using a resistor and a capacitor.
A RESET causes the CPU to initialize in the following
manner:
Figure 16.
• Program counter (PC) is cleared to 0
• Skip flags (SK1, SKO) and program status word
(PSW) are reset to 0
• Timer/event counter:
- Count register = OOH
- Modulo register = FFH
- Timer-out F/F = 0
• Clock control circuitry:
- Clock mode register (CM3-CMO) = 0
CL
- CP = 256
•
•
•
•
•
Power-on Reset Circuit
PPD7533
+-----+1 RESET
,,7
83-002656A
- Timer-out FF signal not output to PTOUT
- Prescalers 1-3 = 0
Shift Mode Register (SM3-SMO) is cleared to O.
- Shift operation stops
- Port 0 is in input mode (high impedance)
- INTS is selected interrupt source of INTO/S
A/D converter circuit:
- ADM register is set to 0
- ANO is selected
- SA register is set to 7FH
- EOC flag is set to logic 1
Interrupt control circuit:
- Interrupt request flags = 0
- Interrupt master enable F/F = 0
- Interrupt enable register = 0
- A" pending interrupts are cancelled
- A" interrupts are disabled
A" Port 2-7 output buffers are turned off
Contents of data memory and the following registers
are undefined:
- Stack pointer (SP)
- Accumulator (A)
- Carry flag (C)
- General purpose registers (H,L)
- A" port output latches
- Shift register
3-83
II
pPD7533/75CG33E
3-84
NEe
ftt{EC
pPD7537A/38Af75CG38E
4-Bit, Single-Chip
CMOS Microcomputers
With Flp® Driver
NEe Electronics Inc.
Description
o
The I/PD7537A, I/PD7538A, and I/PD75CG38E are 4-bit;
single-chip CMOS microcomputers with the I/PD7500
architecture and FIP direct-drive capability.
o
o
o
o
o
o
The I/PD7537A contains a 2048 x 8-bit ROM and a
128 x 4-bit RAM. The I/PD7538A contains a 4096 x 8-bit
ROM and a 160 x 4-bit RAM.
The I/PD7537A/38A contains two 4-bit general purpose
registers located outside RAM. The subroutine stack is
implemented in RAM for greater depth and flexibility.
The I/PD7537A/38A typically executes 67 instructions
with a 51/s instruction cycle time.
The I/PD7537A/38A has one external and two internal
edge-triggered hardware-vectored interrupts. An 8-bit
timer/event counter and an 8-bit serial interface help to
reduce software requirements.
Thirty-one high-voltage lines are organized into the 3-bit
output port 2, the 4-bit output ports 3, 8, and 9, and the 4bit I/O ports 4, 5, 10, and 11.
The low power consumption CMOS process allows the
use of a power supply between 2.7V and 6.0V. Current
consumption is less than 3.0 mA maximum, and can be
further reduced in the halt and stop power-down modes.
The I/PD75CG38E is a piggyback EPROM version of
the I/PD7537A/38A. Pin-compatible and functioncompatible with the final, masked versions of the
I/PD7537A/38A, the I/PD75CG38E is used for prototyping and for aiding in program development.
o
o
o
o
Can select either a pull-down resistor or open-drain
output per 31 high-voltage outputs (mask optional)
Vectored interrupts: one external, two internal
8-bit timer/event counter
8-bit serial interface
Standby function (HALT, STOP)
Data retention mode
Zero-cross detector on POolINTO input (mask
optional)
System clock (j.IPD7537 A/7538A/75CG38E): on-chip
ceramic oscillator
CMOS technology
Low power consumption
Single power supply
-!-,PD7537 A/7538A: 2.7 V to 6.0 V
-!-,PD75CG38E: 5.0 V ± 10%
Ordering Information
Part
Number
Package Type
Max Frequency
01 Operation
I'PD7537AC 138AC
42-pin plastic DIP
I'PD7537ACU/38ACU
42-pin plastic shrink DIP
610 kHz
610 kHz
I'PD75CG38E
42-pin ceramic piggyback DIP
500kHz
Pin Configurations
!-,PD7537A/38A 42-Pin Plastic DIP or Shrink DIP
RESET
CLI
CL2
VPRE
Features
o
o
o
o
o
o
o
VLOAD
P53
67 instructions
Instruction cycle:
-Internal clock: 3.3 I/s/600 kHz, 5 V
- External clock: 3.3!-,s/600 kHz, 5 V
Upwardly compatible with the !-,PD7500 series
product family
4,096 x 8-bit ROM (j.IPD7538A/75CG38E)
2,048 x 8-bit ROM (j.IPD7537A)
160 x 4-bit RAM (j.IPD7538A/75CG38E)
128 x 4-bit RAM (j.IPD7537 A)
351/0 lines
31 high-voltage output lines that can directly drive a
vacuum fluorescent diplay (FIP)
FIP is the registered trademark for NEC's fluorescent indicator panel (vacuum
fluorescent display).
50277 (NECEL·510)
P52
P5,
P50
49-0Q1170A
3-85
II
NEe
~PD7537A/38A/75CG38E
jAPD75CG38E EPROM
Pin Configurations (cont)
No.
jAPD75CG38E 42·Pin Ceramic Piggyback DIP
RESET
CLl
CL2
NC
PO,/SCK
PSD
10-17
Data read input from the EPROM
Connection to EPROM GND pin
P30
P3,
20
CE
Chip enable output
P3,
22
Vss
Supplies EPROM OE signal
P33
23
Program counter MSB output
A30 7 220VSS
P4D
P4,
All
26
VOO
Supplies Vee to the EPROM
A,O 8 2'OA'D
I
1A,o 9200CE
P4,
27
MSEL
Mode select input
28
Voo
Supplies high-level signal to MSEL
I
I
I
I
I
I
P21/PTOUT
P10a
I
I
AD010 '9017
P102
I
I
10011 '8016
P1O,
1,~)12
17(~15
I
I
Pl00
1,0'3 '601,
17
P112
P02/SO
P43
PBo
P8,
P8,
P9D
EPROM: 2732
P9,
P9,
Voo
Note:
(1) Output drivers on ports 2-5 and 8-11 are mask-optional. Accordingly,
either an open-drain output or a pull-down resistor can be selected.
VLOAD is suitable for an output driver with a pull·down resistor.
P83
vSSy:.s9 13
P111
P110
(2) Ports 2-5 are suitable as FIP segment signal outputs, and ports 8-11
are suitable for FIP digit signal outputs.
P93
49-001171A
Pin Identification
Symbol
(3) Ports 8-11 have high-current drive capability and can drive an LED
directly.
Pin Functions, J.lPD7 53 7 A 138A and
J.lPD75CG38E
jAPD7537A138A and jAPD75CG38E
No.
EPROM address output
Vss
AoO 6 230A"
P23
P2,
No connection
3-10,21,24, 25 Ao-Al0
14
A7(P-fs9 Voo
lis 0I 4 250I A•
A505 240A9
P5,
Connection to pin 21 of I'PD75CG38E
11-13,15-19
NC 02 270MSEL
P53
P5,
Function
P03/S1
Voo 0 1 280 voo
NC
P113
VOO
Vss
POD/INTO
VpRE
Symbol
Function
RESET
RESET
Reset input
2,3
CL1, CL2
Clock pins
4
VpRE
High-voltage output predriver supply
CL1,CL2
5
VLOAO
High-voltage output option resistor
supply 7537AI 38A only
Connection to the ceramic oscillator. CL1 is the external
clock input.
6-9
P50-P53
High-voltage I I a port 5
10,12
P23, P22
P21 I PTOUT
High-voltage output port 2, and output
port from timer I event counter (PTOUT)
13-16
Pl00-Pl03
High-current, high-voltage I 10 port 10
17-20
Pllo-Pl13
High-voltage, high-current I I 0 port 11
21
VOO
Positive power supply
22-25
P90-P93
High-voltage, high-current output port 9
26-29
P80-P83
High-voltage, high-current output port 8
30-33
P40-P43
High-voltage I I 0 port 4
34-37
P30-P33
High-voltage output port 3
38
39
40
41
P03/S1
P01/SCK
POol INTO
4-bit input of port 0; or serial data input
(SI), serial data output (SO), serial clock
I 10 (SCK), and external interrupt input
(INTO) or zero-cross detect input (POo).
42
Vss
Ground
3-86
P02/~
System reset (input).
VPRE
Negative power supply for high-voltage output pred rivers (for ports 2-5, 8-11).
Negative power supply for optional load resistors (pulldown resistors) of high-voltage output drivers (for ports
2-5,8-11). This pin is only on the jAPD7537A138A.
P53-P50
4-bit, high-voltage 1/0 port 5.
P21-P23
3-bit, high-voltage output port 2.
~EC
~PD7537A138A175CG38E
PTOUT
Pin Functions,,,,PD75CG38E EPROM
Output port for the timer/event counter.
P103-P1OO
4-bit, high-voltage, high-current I/O port 10. Capable of
bit set/reset by SPBL/RPBL instructions.
P113-P110
. 4-bit, high-voltage, high-current I/O port 11. Capable of
bit set/reset by SPBL/RPBL instructions.
Ao-A10
Output the low-order 11 bits of the program counter
(PCO-PC10). Used as EPROM address signals.
VDD
Positive power supply.
P93-P90
4-bit, high-voltage, high-current output port 9. Capable
of bit set/reset by SPBL/RPBL instructions.
P83-PSo
A11
When MSEL is high level, A11 outputs high-level signals.
When MSEL is open, A11 outputs the MSB of the PC,
which is used as the most signfficant address signal of
the 4-Kbyte EPROM 2732.
10-17
4-bit, high-voltage, high-current output port 8. Capable
of bit set/reset by SPBLlRPBL instructions.
Input data read from the EPROM.
CE
P43-P40
4-bit, high-voltage I/O port 4.
Outputs the chip enable signal to the EPROM.
VDD
P33-P30
4-bit, high-voltage output port 3.
POO-P03
4-bit input port O.
tection input.
MSEL
Changes the addressing area of the external EPROM
and the on-chip RAM (with a pull-down resistor). Connecting ajumper between socket pins 27 (MSEL) and 28
(Voo) selects ",PD7537 A mode (2-Kbyte EPROM, 128 x 4bit RAM). Leaving MSEL open selects ",PD7538A mode
(4-Kbyte EPROM, 160 x 4-bit RAM) .
POo is also used as the zero-cross de-
SI
Serial data input.
SO
Pin 26 is electrically equivalent to the bottom Voo pin
and is used to supply Vee to the EPROM. Pin 28 is electrically equivalent to the bottom Voo pin and is used to
supply the high level signal to MSEL. Pin 1 connects to
pin 21 of ",PD75CG38E.
Vss
Pin 14 is electrically equivalent to the bottom Vss pin in
voltage, and is connected to the EPROM GND pin. Pin
22 is electrically equivalent to the bottom Vss pin and is
used to supply the OE signal to the EPROM.
Serial data output.
Instruction Sat
SCK
Refer to the User's Manual. The instruction set appears
also as subset A4 in the data sheet for the ",PD7500 series of single-chip microcomputers.
Serial I/O clock.
INTO
External interrupt input.
Vss
Ground.
3-87
II
fttfEC
~PD7537A/38A/75CG38E
Block Diagram,j.tPD7537 AI38A
POOflNTO
P30-P33
Program'Memory
P50,-P53
2048 x 8 Bits (,uPD7537A)
4096 x 8 Bits (,uPD7538A)
Instruction
Decoder
PIIo- P83
Cl
P90- P93
Pl00-P103
Cll
CL2
i t
Vee
Vss
P110-P113
RESET
49-0010678
3-88
NEe
~PD7537A/38A/75CG38E
Block Diagram, J.tPD75CG38E
POa/INTO
P01/SCK
P03/SI
POe-P03
P2l~P23
.
PTOUT/P21
P30-P33
L-_ _ _ _
---'~DP7C
Instruction
Buffer
Instruction
Decoder
(I>
CL·
Data Memory
160x4Bits
P10e-P103
Cll
Cl2
h h t
Voo Vee Vss Vss RESET
49-0010688
Absolute Maximum Ratings
TA=25°C
Power supply voltage. Voo
-0.3Vto +7V
Power supply voltage. VLOAO (flPD7537A I 38A)
VOO-40VtoVoO +0.3V
Power supply voltage. VPRE
VOO-12 Vto Voo +0.3 V
Input voltage. except ports 4.5.10.11. VIN
Input voltage. ports 4.5.10.11. VIN
Output voltage. except ports 2-5. 8-11. Vo
Output voltage. ports 2-5. 8-11. Vo
Output current high. per pin: pat. P02; IOH
-0.3VtoVoO +0.3V
-0.3 Vto Voo +0.3 V
Voo-40VtoVoo +0.3V
Capacitance
TA=25°C. Voo=0V,f=1.0MHz, Unmeasured pins returned toGND
Limits
-15 rnA
-30 rnA
Output current high. ports 3. 4. 8. 9 total. IOH
- 55 rnA
Output current high. ports 2. 5. 10.11 total. IOH
- 55 rnA
Output current low. per pin. IOl
15 rnA
Output current low. all ports total. IOl
15 rnA
Storage temperature. TSTG
lute Maximum Ratings could cause permanent damage. The device is
not meant to be operated under conditions outside the limits described in the operational sections of the specification. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
VOO-40VtoVoO +0.3V
Output current high. per pin: ports 2-5.8-11; IOH
Operating temperature. TOPT
Comment: Exposing the device to stresses above those listed in Abso-
-10°C to +70°C
Parameter
Symbol
Input
capacitance
Output
.
capacitance
Co
1/0
capacitance
CIO
MIn
Typ
lu
Unit
15
pF
relt
CondItions
15
pF
Port 2
35
pF
Ports 3,8,9
15
pF
POt. P02
35
pF
Ports 4, 5,10. 11
- 65°C to +150°C
;3-89
ttlEC
~PD7537A138A175CG38E
DC Characteristics
",PD7537A13BA
TA= -10"Cto +70"C, voo,:" +2.7Vto6.0V
Umlts
Parameter
Input voHage,
low
Input wltage,
high
Output voltage,
low
Output voHage,
high
I,mbol
Min
Trp
Unit
Output leakage
current, low
3-90
ILOH1
3
i-iA
Vo = Voo; except
ports 4, 5, 10, 11
ILOH2
80
i-iA
Vo=Voo; ports 4,
5,10,11
0. 3Voo
V
Port 0, RESET
0
0.5
V
CL1
VIl3
Voo-35
0. 3Voo
V
Ports 4, 5, 10, 11
VIH1
0.7Voo
Voo
V
Port 0, RESET
VIH2
Voo-0.5
Voo
V
CL1
VIH3
0. 7Voo
Voo
V
Ports 4, 5, 10, 11;
4.5V~
Mo.k Option
r--t----o InfOut
Type E.
Type D Output with Type A
Input Buffer
PO:z/SO
(Mldcll.LeveI Voltage,
Mlddl.LeveI Current)
Data
Output
Disable---L':':":'J
InlOut
Mlddle·LeveI Voltago input Buffo,
83-003557C
3-103
NEe
pPD7554/54A/64/64A
Program Memory
Arithmetic Logic Unit
The I4PD7554/54A/64/64A has a mask-programmable
ROM with a capacity of 1024 words by 8 bits for program
storage. It is addressed by the program counter. The
reset start address is OOOH. Figure 2 shows the program
memory map.
The arithmetic logic unit (ALU) is a 4-bit arithmetic
circuit that performs operations such as binary addition,
logical operation, increment, decrement, comparison,
and bit processing.
Program Status Word
General.Purpose Registers
Two registers, H(2-bit) and L(4-bit), are provided as
general-purpose registers. Each register can be individually manipulated. The two registers also form pair
register HL; H being the. high register and L being the low
one. The HL register is a data pointer to address data
memory. Figure 3 shows the configuration of the general
purpose registers.
The L register also specifies an I/O port or mode register
when an I/O instruction (IPL or OPL) is executed. It also
specifies the bits of a port when the SPBL or RPBL
instruction is executed.
Data Memory
The data memory is static RAM with a capacity of 64
words by 4 bits. Part of this memory is used as the stack
area. The data memory is also used in 8-bit data processing when paired with the accumulator. Figure 4
shows the data memory map.
Data memory can be addressed directly, with the immediate data from an instruction; indirectly, with the contents of HL (incl uding auto-increment and autodecrement); and indirectly by the contents of the stack
pointer.
You may use any area of the data memory as the stack.
The boundary of the stack is determined by how the
TAMSP instruction initializes the stack pointer. Once the
boundary is set, a call or return instruction automatically
accesses the stack.
When a call instruction is executed, the contents of the
program counter and the program status word (PSW) are
stored to the stack in the sequence shown in figure 5.
When a return instruction is executed, the contents of
the program counter are automatically restored, but the
PSW is not. The contents of data memory can be retained
with a low supply voltage during STOP mode.
Accumulator
The accumulator is a 4-bit register used in arithmetic
operations. The accumulator can process 8-bit data with
paired data addressed by HL. Figure 6 shows the configuration of the accumulator.
3-104
The program status word (PSW) consists of two skip
flags (SKO and SK1), a carry flag (C), and bit 1, which is
always zero. Figure 7 shows the configuration of the
PSw.
The contents of the PSW are stored to the stack when a
call instruction is executed, but are not restored from
the stack by the return instruction.
The skip flags retain the following skip conditions: string
effect by LAlor LHLI instruction, and skip condition
satisfied by an instruction other than a string-effect
instruction. The skip flag is set or reset according to the
instruction executed.
The carry flag is set to 1 if an addition instruction (ACSC)
generates a carry from bit 3 of the ALU. If no carry is
generated, the flag is reset to zero. The SC instruction
sets the carry flag and the RC instruction resets it.
When a RESET is input, the SK1 and SKO flags are
cleared to zero and the contents of the carry flag are
undefined.
I
Figure 2. Program Memory Map
·~I ",m~'
~023)
3FFH
83-002592A
Figure 3. Configuration of General Purpose
Registers
1
0
~
3
0
r-I-""'::"1
~I
NEe
pPD7554/54A/64/64A
Figure 4. Datallemory lIap
This flip-flop also stops the RC oscillator. The STOP
flip-flop is reset by the standby release signal that
becomes active when one of the test requests flags is set
or at the falling edge of the RESET signal. When the
STOP flip-flop is reset, the RC oscillator resumes operation and supplies the system clock.
(0) OOH
84 words x 4 bltl
(83) 3FH L -_ _- - '
83-Q02594A
Figure 5. Call Instruction Storlllle to Stack
Stick Area
0
°10Ipc·l pC
psw·
pc.·pca
pCr-pc.
3
SP·4
SP·3
SP·2
SP·I
8
·BIII 01
Figure 9 shows the system clock generator circuit for the
",PD7564/64A.
psw
o.
10 IIwIY.
83-002595A
Figure tJ. Configuration of the Accumulator
I Ao I Ao I A, I AI IA
I
Figure 7. Configuration of theflrogram Status
lib,.,
3
2
The HALT and STOP instructions and RESET HIGH set
the HALT flip-flop which disables signals from going to
the 1/2 frequency divider that generates the CPU clock.
Only the CPU clock stops in HALT mode. The HALT
flip-flop is reset by the same conditions as the STOP
flip-flop.
0
ISK,lsKoI 0 I CIpsw
83-002597A
System Clock Generator
The system clock generator consists of a ceramic oscillator, a 1/2 frequency divider, standby modes (STOP/
HALT), and control circuit. Figure 8 is a circuit diagram of
the system clock generator.
In the "PD7554/54A, the RC oscillator operates with a
single external resistor connected across CL 1 and CL2
(the capacitor C is incorporated). When the RC oscillator
is not used, external clock pulses can be input by the
CL 1 pin. In this case, the RC oscillator functions as an
inverting buffer. The output from the RC oscillator serves
as the system clock (CL) which is then divided by two
and used as the CPU clock (I/l).
On the "PD7564/64A, the ceramic oscillator operates
with a ceramic resonator connected across CL 1 and
.CL2. The output from the ceramic oscillator is used as
the system clock (CL); iiis divided by two to produce the
CPU clock (I/l).
The standby mode control circuit is made up of a STOP
flip-flop and a HALT flip-flop. The STOP instruction sets
the STOP flip-flop and stops the ceramic oscillation,
thus stopping the supply for all clocks. The STOP flipflop is reset by the RESET signal (high level) and restarts
ceramic oscillation. The supply of each clock resumes
when RESET goes low.
The HALT instruction sets the HALT flip-flop which disables signals from going to the 1/2 frequency divider that
generates the CPU clock. Only the CPU clock stops in
HALT mode. The HALT flip-flop is reset by the HALT
RELEASE signal (activated by setting at least one test
request flag) or the falling edge of RESET, resuming
supply of the CPU clock.
The HALT flip-flop is also set when RESET is active (high
level). At power on reset operation, the rising edge of
RESET starts ceramic oscillation; however, some time is
required to achieve stable oscillation. To prevent the
unstable clock from operating the CPU, the HALT flipflop is set and the CPU clock is stopped while RESET is
high. Accordingly, the high-level width of RESET must be
more than the required stable time for the ceramic
resonator.
The standby mode control circuit is made up of a STOP
flip-flop and a HALT flip-flop. The STOP instruction sets
the STOP flip-flop and stops the system clock supply.
3-105
NEe
"PD7554/54A/64/64A
Figure B. System Clock Gener.tor for PPD7554/54A
STOP F/F
S I----------~ STOP"
'Q
R
HALT"
RESET (High)
Standby R.I••••
L-t----4-C j:=- RESET
CL2
("'-.)'
+(to CPU)
L-_ _ _ _ _ _ _ _ _ _ _ _ _ CL (Syst.m Clock)
·Executlon of Instruction
83-0D25988
Figure 9. System Clock Generator for pPD7564/64A
STOP F/F
Q
SJ.-------~-"t_r-R
STOP"
HALT F/F
Q
CLl
S
I==---~ HALT"
RESET (High)
Standby Ro.....
CL2
""'- \ - - - - RESET ' -
L - 4 - - - - - - - - - - ' " ' - - RElla '....r(To CPU)
' - - - - - - - - - - - - - - - - - CL (System Clock)
·Executlon of Instruction
3-106
NEe
pPD7554/54A/64/64A
Clock Control Circuit
Timer/Event Counter
The clock control circuit consists of a 2-blt clock mode
register (bits CM1 and CM2), prescalers 1, 2, and 3, and
a multiplexer. It takes the output of the system clock
generator (CL) and event pulses (POa). It also selects the
clock source and prescaler according to the setting in
the clock mode register and supplies the timer/event
counter with count pulses. Figure 10 shows the clock
control circuit.
The timer/event counter is a binary 8-bit up-counter
which is incremented each time a count pulse is input.
The TIMER instruction or a RESET signal clears it to
OOH. When an overflow occurs, the counter is reset from
FFH to OOH. Figure 11 shows the inputs and outputs of
the counter.
Table 2 lists the codes set in the clock mode register by
the OPL instruction to specify the count pulse frequency.
The serial interface consist of an 8-bit shift register, a
3-bit shift mode register, and a 3-bit counter. This interface inputs and outputs serial data. Figure 12 is a block
diagram of the interface.
When you set the clock mode register with the OPL
instruction, clear bit 0 of the accumulator (corresponding to bit CMO of the EVAKIT-7500 or "PD7500H during
emulation).
Figure 10.
Serial Interface
Test Control Circuit
The "PD7564/64A has three test sources, as shown in
table 3.
Clock Control Circuit
The test control circuit consists of two test request flags
(lNTT RQF andINTO/S RQF) set by the three test
sources, and a test request flag control circuit that
checks tlJe contents of each test request flag by executing an SKI instruction and resetting the flags.
Test sources INTO and INTS share the request flag
INTO/S RQF. Bit 3 of the shift mode register (SM3)
determines which source is selected. A zero in SM3
selects INTS and a one selects INTO.
CL
Figure 11. Timer/E"ent Counter
CP
".nstrucllon
Execution
83-002600A
Table 2. Selecting the Count Pulse Frequency
CM2
a
a
CM1
Frequency Selected
a
CL/256
a
CL/32
*Instructlon Execution
83·002601A
POo
CL/4
3-107
II
NEe
pPD7554/54A/64/64A
T.ble3. pPD7564/64A.7ilst Sources
Source
FuriCtlon
location
Request Flag
INTT
Overflow In timerl
event counter
Internal
INTTRQF
INTO
Test request signal
from POo pin
External
INTOIS RQF
INTS
Transfer complete
signal from serial
Interface
Internal
INTOIS RQF
The request flag INTT RQF is set when a timer overflow
occurs in the timer event counter. The SKI or TIMER
instructiO!1 resets it.
When SM3 is one, request flag INTOtS RQF is set at the
riSing edge of the Signal input to the POollNTO pin. The
SKI instruction resets the flag. .
The logical sum of the outputs from the test request flags
releases standby mode (STOP1 or HALT mode). The
mode is released when one or both flags are set. Both
flags and SM3 are reset when the RESET signal is input.
After reset, source INTS is selected and signal input to
the INTO pin is inhibited as the initial condition.
Figure 13 is a block diagram of the test control circuit.
Note:
(1) Only I'PD7554/54A.
When SM3 is zero, request flag INTOtS RQF is set when
the INTS signals is generated, indicating the end of an
8-bit serial data transfer. The SKI or SIO instruction
resets the flag.
Figure 12. Seri."nterf.ce Block Oi".,..",
SMa
~#.Wo-~-----+1--------~~
Note:
(1)
+18 the Intemal clock 81gnll (I .••• syst.m clock~
(2) • Instruction execution
(3) SMa and INTO are Input to the te.t control· circuit.
83-0028229
3-108
tt1EC
pPD7554/54A/64/64A
Figure 13. Test Control Circuit Block Diagram
INTT
--+------1
INTS--'-~-
II
Standby
Release
INTD--,.-.._
·Slo--=t_r---------...J
Note:
(1) SMa Is bit 3 of the shift mode register.
(2) * Instruction execution
83-0026238
Standby Modes
The "PD7554/54A/64/64A has two standby modes to
reduce power consumption while the program is in the
wait state. The STOP and HALT instructions set these
modes.
When the program enters a standby mode, program
execution stops and the contents of all registers and
data memory immediately before the program entered
standby mode are retained. The timer and serial interface can operate.
The RESET signal and STANDBY Release signaJ(1) release STOP mode. HALT mode is released when one or
both ofthe test request flags are set, or when the RESET
signal is input. The program cannot enter a standby
mode when a test request is being set, even if the STOP
or HALT command is executed.
If there is some uncertainty about the state of the test
request flags, execute the SKI instruction to reset them
so the program can enter standby mode.
Table 4 compares STOP and HALT modes. The main
difference is that STOP mode stops the system clock and
HALT does not Ceramic oscillation stops during STOP
mode. The power consumed by the ceramic oscillator is
the difference between the two modes. In STOP mode,
data memory can be retained with a lower supply
voltage.
Note:
(1) Standby release signal for I'PD7554/54A only.
Table 4. STOP and HALT Modes
Mode
CL
4»
POo
CPU
Timer
STOP
x
a
x
x
a
a
x
x
/).
RESET input
a
INTTRQF
INTOIS RQF
RESET Input
HALT
Released by
Notes:
(1) 0: operates. x: stops.
/).: operates depending on clock source. "PD7554/54A; If external
clock Is used, STOP instruction will not stop CL. In this case
STOP mode acts as HALT mode.
Power-on Reset Circuit
Figure 14 shows a circuit example of the power-on reset
circuit using a resistor and a capacitor. This is the
simplest reset control circuit. Figure 15 shows the circuit
with a pull-down resistor internally connected to RESET
as a mask option.
3-109
NEe
pPD7554/54A/64/64A
"PD7554/54A/64/64A Applications
Figures 16 and 17 show examples of application circuits
for the ~PD7554/54A/64/64A.
Figure 15. Power-on Reset Circuit with Pull-down
Resistor
VDD
~PD7554184
Table 5 compares the features of the low-end products of
the 7500 series devices.
RESET
Figure 14. Power-on Reset Circuit
VOD
Vss
63-002625A
f--
RESET
r;
83-002624A
T1Ible5. Product Comparison
Item
Instruction
cycle/system
clock (5 V)
"PD7554/54A
"PD7564/64A
"PD7556/56A
RC
4 p.e/
500 kHz
41'81
External
2.S6 p.e/
700 kHz
2.S6 p.S/
700 kHz
500 kHz
3 p.e/
660 kHz
Ceramic
"PD7566/66A
3p.S/
660 kHz
Instruction set
47
47
45
ROM
1024 x S
1024xS
1024 x S
1024xS
RAM
64x4
64x4
64x4
64x4
I/O port total
16 (max)
15
20 (max)
19
PortO
POo-P03
POo-P03
POo-POl
POe-POl
P1o-P13
POl-P03
P80-P&.!
PSalCL2
PSo-P&.!
PSo-P&.!
PSalCL2
PBo-P&.!
Port 1
PortS
Port 9
45
Peo-Pel
P90-P9l
P100-P103
'P10e-P1Oa
P100-P103
P100-P103
P11o-P1.13
P11o-P113
P11o-I>113
P110-Pl13
Timer/Event
counter
S-blt
S-blt
8-blt
S-blt
Serial Interface
S-blt
S-bit
4-channel
4-channel
Proceas
CMOS
CMOS
CMOS
CMOS
Package
2O-pln plastic SOP
2O-pin plastic SOP
24-pin plastiC SOP
24-pin plastiC SOP
2O-pin shrink DIP
2O-pin shrink DIP
24-pin shrink DIP
24-pln shrink DIP
Port 10
Port 11
Comparator
3-110
FIgure 16. Tape Counter Circuit
y
Microcomputer
lor Tape Counter
M••ter
Microcomputer
RESET
POoIINTO
CLI
+OUT
SCK
so
Count Pul••
Up/Down SIgnal
PII,
SCK
81
.PD7507H 81
.PD750SH
II
Fltlure 17. Remote-controlltid o.t. Reception, Key InpUt.nd LED DI.,.y
....ter
Microcomputer
rrSIr• PD7508H r.PD7S19H
SCK
SO
ate.
,
.PD7584
ImR
81
rS
SO
I
I
DrIver (,--
->--
>---<>--
I--
PI,
(3)
P80
Remote
Controlled
.Slg..1
Amplifier
~C1473
~
P80
POo
PlOo
PIG,
(4)
PlOo
PIO.
NoIe:
(I) CMOS output
(2) Chip Hie.. or Ironsfer requ...
(3) Openodnln oulpuf
(4) Input with Intemal pull-up nsl8lor
Kay Input (4 x 4)
1I3-0021I278
3~111
pPD75S4154A/64164A'
E~CTRICAL
SPECIFICATIONS
Capacitance
,>'"
Absolute Maximum Ratings
T" • 25"C
P.r~r
Operating temperature, TOPT
-10 to+7Q"C
~--------~~~----------~------~
Storage
temperatura, TSTG
~ to + 16O"C
--~--~----~~-------------------Foweraupply voltage, Voo
-0.3 to +7.0 V
----~----~~----~---------------Input voltage, VI
Except porta 10, 11
-0.3 to Voo +0.3 V
Power dleelpatlon, Po (T"
Shrink DIP
SOP
pF
POo, FDa
35
pF
Port 8
35
pF
Porta 10, 11
15
pF
P01,
I/O capacltance,CIIO
-0.3 to Voo +0,3 V
-0.3 to Voo +0.3 V
-o.3to +13V
-o.3Vto +11 V
"PD7554A/64A only (Note 2)
.
Output currant.. low IOL
P01, PO:!
. Porta 8·11
Port 8
All porte, total
15
Co
Output capacitance
-o.3to +11 V
(Note 2)
Outputcurrant,hlgh IOH
One port
All output porta, total
. InpuloapaeitanceC..
"'-o.3to +13V
Porta 8, 10. 11 (Note 1)
-SmA
",'"
",
.
.7!~.mA,
,;/) .
5mA
15mA
SOmA
100mA:
"! -
+70"0)
..eo;;,;w
250mW
Expoaure to Absolute Maximum Ratings for extended perlodamay
affect device reliability; exceedllig Ihe ratlnge could cause permanent
clamage. The device should, be operated. within' the.Jlmltl specified
under DC end AC Charactlrlatlca.
Notes:
(1) CMOS 110 or N-ohennel open drain + Intamal pull up reelator.
(2) N-chennel open drain VO.
\','\'
a-:112
'\ ~~,
Symbol Mifl 1)p Max Unit Conditions
-o.Uo Voo+O.3V
Porta 10, 11 (Note 1)
(Note 2)
"PD71554A164A only (Note 2)
Output voltage, Vo
. Except porta 8, 10, 11
•.. :,'i
. , '.,
T" .. 25"C, Voo = GND - OV; f - 1 MHz
Unmeasured plna returned to GND
-
PO:!
NEe
JlPD7554/54A/64/64A
DC Characteristics 1j Voo
TA
= -10 to
+70°C; GND
=0V
= 2.5 to 3.3 Vj "PD7554/54A
Parameter
Symbol
Input high voltage except CL 1
VIHI
0.8VOO
Input high voltage CL 1
VIH2
Input high voltage ports 10, 11
VIH3
Input high voltage RESET
VIHOR
Input low voltage except CL 1
VILI
Input low voltage CL 1
Input leakage current except CL 1
Max
Unit
VOO
V
Voo-0.3
VOO
V
0.8VOO
12 (Note 1);
9 (Note 2)
V
0.9VOOOR
VOOOR + 0.2
V
0
0.2VOO
V
VIL2
0
0.3
V
ILiI
-3
3
p.A
OV
S
VI
S
VOO
Input leakage current CL 1
ILl2
-10
10
p.A
OV
S
VI
S
VOO
Input leakage current ports 10, 11
ILl3
10 (Note 1)
p.A
10 (Note 2)
p.A
= 12V
VI = 9V
IOH = -80p.A
Output voltage high POI' P02,
. ports 8-11
Output voltage low POI,
ports 10,11
~,
Output voltage low port 8
VOH
Min
Typ
V
VOO -1.0
0.5
VOL
ILOI
Output leakage cu rrent ports 8-11
IL02
Data retention mode
POI, P02: IOL = 350 p.A;
Ports 10,11: IOL = 350 p.A
V
IOL = 500 p.A
3
p.A
OVsVosVoo
10 (Notes 1, 2)
p.A
Vo
6.0
V
55
180
p.A
Voo
40.
150
p.A
VOO
25
80
p.A
Voo
18
60
p.A
Voo
-3
Supply voltage, data retention mode
VOOOR
Supply current, normal operation;
R oscillation (Note 3)
IDOl
Supply current, HALT mode;
R oscillation (Note 3)
1002
Supply current, STOP mode (Note 3)
1003
0.1
5
p.A
Supply current, data retention
mode (Note 3)
1000R
0.1
5
p.A
Pull-up/down resistance, port Q, RESET
RPI
23.5
47
70.5
kO
Pull-up resistance, ports 8-11
RP2
7.5
15
22.5
kO
2.0
II
VI
0.5
VOL
Output leakage current
V
Conditions
= 12 V ",PD7554; Vo = 9 V p.PD7554A
= 3 V ::1:0.3 V; R = 150 kO ::1:2%
= 2.5 V; R = 150 kO ::1:2%
= 3 V ::1:0.3 V; R = 150 kO ::1:2%
= 2.5 V; R = 150 kO ::1:2%
VOOOR
= 2.0 V
Notes:
(1) N-channel, open drain I/O ports, p.PD7554.
(2) N-channel, open drain I/O ports, p.PD7554A
(3) Current in built-in pull-up/down resistors excluded.
3-113
NEe
pPD7554/54A/64/64A
DC Characteristics 2; Voo
= -10 to +70°C; GND = 0 V
= 2.7 to 6.0 V; "PD7554/54A164/64A
TA
Parameter
Symbol
Input high voltage except CL 1
VIHl
0.7Voo
Min
Input high voltage CL 1 (Note 2)
Typ
Max
Unit
Voo
V
VIH2
Voo-0.5
Voo
V
Input high voltage ports 10, 11
VIH3
0.7Voo
12 (Note 1);
9 (Note 2)
V
Input high voltage RESET
VIHOR
Input low voltage except CL 1 (Note 3)
Input low voltage CL 1
Input leakage current except CL 1 (Note 3)
ILil
Input leakage current CL 1
ILl2
Input leakage current ports 10, 11 (Note 4)
ILl3
Output voltage high POl, P02, ports 8-11
0. 9VOOOR
VOOOR
+
0.2
V
VILl
0
0.3 VOO
V
VIL2
0
0.5
V
-3
3
p.A
-10
10
",A
10
",A
IOH
VOO -2.0
VOH
VOO - 1.0
Output voltage low POl, P02
VOL
Output voltage low ports 10, 11
VOL
Output voltage low port 8
VOL
Output leakage current
ILOl
Output leakage current, port 8-11 (Note 4)
IL02
Supply voltage, data retention mode
VOOOR
Supply current, normal operation;
ceramic oscillation (Notes 3, 5)
1001
Supply current, normal operation;
R oscillation (Note 3)
1001
Supply current, HALT mode;
ceramic oscillation (Notes 3, 5)
1002
Supply current, HALT mode;
R oscillation (Note 3)
1002
Supply current, STOP mode (Note 3)
1003
Supply current, data retention mode (Note 3)
1000R
Pull-up/down resistance, port 0, RESET
RP1
Pull-up resistance, ports 8-11
RP2
V
V
-3
2.0
0.4
V
0.5
V
0.4
V
2.0
V
0.5
V
2.0
V
Conditions
Data retention mode
oV S
oV S
0.5
V
3
",A
OVsVosVOO
10
p.A
Vo = 12 V ",PD7554/64; Vo
",PD7554A/64A
6.0
V
650
2200
p.A
VOO
120
360
p.A
Voo
270
900
p.A
80
240
p.A
450
1500
",A
65
200
p.A
120
400
p.A
35
110
",A
0.1
10
p.A
0.1
5
p.A
0.1
5
p.A
23.5
47
70.5
kO
7.5
15
22.5
kO
=9V
= 5 V ±0.5 V; fcc = 700 kHz
= 3 V ±10%; fcc = 300 kHz
Voo = 5 V ±0.5 V; R = 56 kO ±2%
VOO = 3 V ±10%; R = 100 kll ±2%
VOO = 5 V ±0.5 V; fcc = 700 kHz
VOO = 3.0 V ±10%; fcc = 300 kHz
VOO = 5 V ±0.5 V; R = 56 kO ±2%
VOO = 3 V ±10%; R = 100 kll ±2%
Voo = 5V ±0.5V
VOO = 3V ±10%
VOOOR = 2.0 V
(1) ",PD7554/64.
(4) N-channel, open-drain 1/0 ports.
(2) ",PD7554A/64A.
(5) ",PD7564/64A.
3-114
VI S VOO
= 9 V (7554A); or 12 V
VOO = 4.5 to 6.0 V; IOH = -1 mA
VOO = 2.7 V; IOH = -100 p.A
VOO = 4.5 to 6.0 V; IOL = 1.6 mA
IOL = 400 ",A
VOO = 4.5 to 6.0 V; IOL =' 1.6 mA
VOO = 4.5 to 6.0 V; IOL = 10 rnA
IOL = 400 ",A
VOO = 4.5 to 6.0 V; IOL = 15 mA
IOL = 600 p.A
VI
Notes:
(3) Current in built-in pull-up/down resistors excluded.
VI S VOO
NEe
DC Characteristics 3; VDD
pPD7554/54A/64/64A
= 2.0 to 3.3 V; p.PD7554A only
TA = -10 to +70'C; GND = 0 V
Parameter
Symbol
Min
Typ
Max
Unit
0.8 Voo
VOO
V
Voo-0.2
VOO
V
Conditions
Input high voltage except CL 1
VIHl
Input high voltage CL 1
VIH2
Input high voltage ports 10, 11
VIH3
0.85Voo
9
V
Input high voltage RESET
VIHOR
0.9VOOOR
VOOOR + 0.2
V
Input low voltage except CL 1
VILl
0
0.15Voo
V
Input low voltage CL 1
V IL2
0
0.2
V
Input leakage current except CL 1
ILil
-3
3
pA
Input leakage current CL 1
ILI2
-10
10
pA
oV
oV
Input leakage current ports 10, 11 (Note 1)
ILI3
10
pA
VI = 9V
Output voltage high POl, ~, ports 8-11
VOH
V
IOH = -70pA
Output voltage low POl, P02, ports 10, 11
VOL
V
POl, P02: IOL = 270 pA
Ports 10, 11: IOL = 300 p.A
Output voltage low port 8
VOL
Output leakage current
IL0 1
Output leakage current ports 8-11 (Note 1)
IL02
Supply voltage, data retention mode
VOOOR
Supply current, normal operation;
R oscillation (Note 2)
1001
Voo-1.0
0.5
Data retention mode
:s VI :s VOO
:s VI :s VOO
II
0.5
V
-3
3
pA
OV:s Vo :s'VOO
10
pA
Vo=gV
2.0
6.0
V
38
130
pA
VOO = 3.0 V ::t10%; R = 240 kO ::t2%
20
70
pA
VOO = 2.0 V; R= 240 kIl ::t2%
17
60
".A
Voo = 3 V ::t10%; R = 240 kIl ::t2%
8
25
pA
VOO = 2V; R = 240 kG ::t2%
0.1
5
pA
Supply current, HALT mode;
R oscillation (Note 2)
1002
Supply current, STOP mode (Note 2)
1003
Supply current, data retention mode
1000R
0.1
5
pA
Pull-up/down resistance, port 0, RESET
RP1
23.5
47
70.5
kO
Pull-up resistance, ports 8-11
RP2
7.5
15
22.5
kG
IOL = 400pA
VOOOR = 2.0 V
Notes:
(1) N-channel, open-drain I/O ports.
(2) Current In built-In pull-up/down resistors excluded.
3-115
NEe
pPD7554/54A/64/64A
AC Characteristics 1; Voo
TA
= -10 to
+70°C; GND
=0 V
= 2.5 to 3.3 V; p,PD7554/54A
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
System clock oscillation frequency
fcC
140
180
220
kHz
R
System clock oscillation frequency, CL 1, CL2
fcC
140
175
210
kHz
Voo
External clock frequency. CL 1
fc
250
kHz
50% duty
200
ns
System clock rise time, CL 1
teR
System clock fall time, CL 1
teF
10
200
ns
50
I's
System clock pulse width, high
teH
2
System clock pulse width, low
tel
2
50
I's
fpoo
0
250
kHz
External clock frequency (POol
POo rise time
teRPoO
200
ns
POQ fall time
teFPO
200
ns
POa pulse width, high
tpooH
2
I's
POo pulse width, low
tpOOl
2
I's
INTO high time
tlOH
30
I's
INTO low time
tlOL
30
I'S
I's
= 150 kG ±2%
= 2.5 V; R = 150 kG ±2%
50% duty
RESET high time
tRSH
30
RESET low time
tRSl
30
i'S
RESET setup time
tsRS
0
I'S
RESET hold time
tHRS
0
I's
S'CR cycle time
tKCY
8.0
1'8
10.0
1'8
Output
tKH
4.0
I's
Input
tKl
5.0
I's
Output
tSIK
0.3
I's
tKSI
0.3
S'CR pulse width, high
S'CR pulse width, low
S I setup time to S'CR i
SI hold time after S'CR i
SO output delay time after S'CR i
3-116
tKSO
Input
I's
2.0
I's
COUT
= 100 pF max
NEe
pPD7554/54A/64/64A
AC Characteristics 2; Voo
TA
= -10 to
+70·C; GND
=0V
= 2.7 to 6.0 V; "PD7554/54A/64/64A
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
System clock oscillation
frequency (Note 1)
fcc
400
500
600
kHz
Vee
200
2SO
300
kHz
Vee
External clock frequency, CL 1
fc
10
710
kHz
Vee
10
350
kHz
Vee
System clock oscillation
frequency (Note 2)
Oscillation stabilization time
fcc
tos
System clock rise time, CL 1
teR
System clock fall time, CL 1
teF
System clock pulse width
290
700
710
kHz
Vee
290
SOO
510
kHz
Vee
290
400
410
kHz
Vee
290
300
310
kHz
Vee
ms
Vee
20
200
ns
200
ns
50
= 4.5 to 6.0 V; R = 56 kO :1:2%
= 3 V :1:10%; R = 100 kO :1:2%
= 4.5 to 6.0 V; SO% duty
= 2.7 V; 50% duty
= 4.5 to 6.0V
= 4.0 to 6.0 V
= 3.5 to 6.0 V
= 2.7 to 6.0 V
= 2.7 to 6.0 V
teH
0.7
lIS
Vee 4.5 to 6.0 V
Syste!" clock pulse width, CL 1
tel
1.45
50
lIS
Vee
External clock frequency (POol
fPOO
0
710
kHz
Vee
0
350
kHz
Vee
200
ns
200
ns
POo rise time
teRPOO
= 2.7 V
= 4.5 to 6.0 V; SO% duty
= 2.7 V; SO% duty
POo lall time
teFPO
POo pulse width, high
1POOH
0.7
lIS
Vee
POo pulse width, low
1POOl
1.45
liS
Vee
INTO high time
fK>H
10
lIS
INTO low time
fK>l
10
lIS
RESET high time
iRsH
10
lIS
RESET low time
~Sl
10
liS
RESET setup time
taRS
0
liS
RESET hold time
\iRS
0
liS
~cycletlme
tKCY
2.0
liS
Input; Vee
2.5
liS
Output; ; Vee
5.0
liS
5.7
liS
= 4.5 to 6.0 V
= 4.5 to 6.0 V
Input; Vee = 2.7 V
Output; ; Vee = 2.7 V
1.0
liS
Input; Vee = 4.5 to 6.0 V
1.25
liS
Output; Vee
2.5
lIS
Input; Vee
2.85
liS
liS
~ pulse width
~ pulse width
lKH
lKl
SI setup time to ~ r
talK
0.1
SI hold time after ~ r
iKsl
0.1
SO output delay time after ~ r
tKSO
= 4.5 to 6.0 V
= 2.7 V
= 4.5 to 6.0 V
= 2.7 V
Output; Vee = 2.7 V
lIS
0.85
lIS
Voo
1.2
lIS
Veo
= 4.5 to 6.0 V; COUT = 100 pF max
= 2.7 V; COUT = 100 pF max
Notes:
(1) IIPD7554/54A.
(2) IIPD7564/64A.
3-117
t-{EC
pPD7554/54A/64/64A
AC Characteristics 3; Voo
TA
= -10 to
+70°C; GND
= 0V
= 2.0 to 3.3 V; I'PD7554A
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
System clock oscillation frequency
fcc
65
120
145
kHz
R
System clock oscillation frequency, CL1, CL2
fcc
65
100
130
kHz
Voo
External clock frequency, CL 1
fc
10
150
kHz
System clock rise time, CL 1
teA
200
ns
teF
200
ns
50
p.s
System clock fall time, CL 1
= 240 kO ±2%
= 2.0 V; R = 240 kO
System clock pulse width, high
teH
3.3
System clock pulse width, low
tel
3.3
50
p.s
External clock frequency (POo)
fpoo
0
150
kHz
POo rise time
teAPOO
200
ns
POo fall time
teFPO
200
ns
POo pulse width, high
tpOOH
3.3
p.s
POo pulse width, low
tpOOl
3.3
p's
INTO high time
tlOH
50
p's
INTO low time
tlOl
50
p.s
RESET high time
tASH
50
p's
RESET low time
tASl
50
p.s
RESET setup time
tSAS
0
p.s
RESET hold time
tHAS
0
p's
SCK cycle time
tKCY
13.4
p.s
16.6
p's
Output
tKH
6.7
p.s
Input
tKl
8.3
p.s
Output
tSIK
0.5
p.s
tKSI
0.5
SCi< pulse width, high
SCi< pulse width, low
SI setup time to SCi< i
SI hold time after SCi< i
SO output delay time after SCi< i
3-118
tKSO
50% duty
Input
p.s
3.5
p.s
COUT
= 100 pF max
±2%
NEe
pPD7554/54A/64/64A
Datil Retention Mode, pPD7564/54A.
TIMING WAVEFORMS
Clocks
"PD7554If4. - - - - - S T O P Mode'-----+i
J--+-+-
VDD
1------lIlc----+I
Operating
Mode
(1) VIHI
(2) VDDD.
(3) VIHD.
tCL
CL1----,
(4)VILI
t
po, _ _ _ _
IC'
1/POO
1-
:POOL~FIPOOH
RESET
tSRS
83-002612A
=~:~
Dlltll Retention Mode, pPD7564/tUA
tpooRdLtPOOF
83-002609A
~PD756411-----sTOP MOde _ _ _ _~HI-A-LT-M-od~e _~~:r:ting
Externlllinterropt
VDD
83-002610A
Reset
RESET _ _ _ _ _ _ _ _ _ _ _ _J
83-002613A
1=I'SLTI'SH~=~:~
RESET _ _ _
83-002611 A
Serilllinterfllce
1----IKCy----.,
SCK---"""",
51----+--<\
SO
Output Data
V-
----"B3-002628A
3-119
II
JlPD7554/54A/64/64A
3-120
NEe
NEe
NEC Electronics Inc.
pPD75P54/P64
4-Bit, Single-Chip,
One-Time Programmable (OTP)
CMOS Microcomputers With Serial I/O
Description
Ordering Information
The J.lPD75P54 and J.lPD75P64 are 1024 x 8-bit on-chip,
one-time programmable (OTP) ROM versions of the
mask ROMs, J.lPD7554 and J.lPD7564. They have the
same functions as, and are pin-compatible with, their
mask ROMs. Because of their programming capabilities, the J.lPD75P54/P64 are suitable for evaluation and
small lot production for system development. Their
unique features will be described in this data sheet. For
information about the base part J.lPD7554/64, please
refer to its data sheet.
Part Number
Package Type
JlPD75P54CS
20 -pin plastic shrink DIP (OTP)
JlPD75P64CS
JlPD75P54G
20 -p in plastic SO P (OTP)
JlPD75P64G
Pin Configuration
o 47 instructions (subset of J.lPD7500 set B)
o Instruction cycle:
- External clock (J.lPD75P54): 2.86 J.ls/700 kHz, 5 V
- RC oscillator (J.lPD75P54): 4 J.lS/500 kHz, 5 V
- Ceramic oscillator (J.lPD75P64):
2.86 J.ls/700 kHz, 5 V
o
Program memory (ROM) of 1024 x 8 bits
o Data memory (RAM) of 64 x 4 bits
o 8-bit timer/event counter
o 8-bit serial interface
II
2O-Pin Plastic Shrink DIP or SOP (OTP)
Features
Vss
POO/INTONpp
P01/SCK
PO:!ISO
Pea/SI
P80/MOO
P113iD7
3
4
S
P112iDS
P111iDS
P110iD4
P81!t.101
6
P103iD3
P82!t.102
• CL2IM03 (P63/M03)
7
8
P102iD2
P101iD1
CL1 9
VOO _'-_ _ _1~1
P100iDO
RESET
• P63can be selected when using external clock on I1P07SP54 only.
CL2 can be selected when using RC oscillator.
49NR-GSOA
o I/O lines: 16-J.lPD75P54; 15-J.lPD75P64
o Data memory retention at low supply voltage
o CMOS technology
o Low-power consumption
o Single power supply:
- 4.5 to 6.0 V normal operation
-6.0 V OTP
o STOP, HALT standby functions
o 2O-pin plastic shrink DIP or SOP (OTP)
50287
3-121
1tt{EC
pPD75P54/P64
Pin Identification
CL 1 (Clock Input 1)
Symbol·
Function
POoIINTO/Vpp
4-blt Input port O/count clock Input/serial
Interface. Programming voltage supply
pin for program memory write/Verlfy.
~a
POalSl
P80-P82I'M00-M02
CL2JMD3 (P8afMD3)
VDD (Power Supply)
4-blt output port 8IOTP operation mode.
Connection for ceramic resonator or RC
(No P8a on "P075P64) (Note 1)
CL1
Connection for ceramic resonator or RC
Vee
4.5 to 6.0 V power supply, normal
operation. 6.0 V for OTP.
RESET
. Reset Input pin
4-blt va port 10 and 00-03 during
programming writetverify.
4:bit va port 1.1 and 04-07 during
programming wrlte/Verify.
Vss
. On the ",P075P54, CL 1 is one of the two pins to which a
resistor for RC oscillation is connected. On the
",P075P64, CL 1 is one of the two pins to which a ceramic
resonator is connected.
Ground
Note:
(1) MDO-M03 are us~ as mode select pins during programming.
Positive power supply. 4.5 to 6.0 V for normal operation.
6.0 V for program memory write/Verify.
RESET (Reset)
System reset input pin (active high). This pin is not
internally connected to a pull-down resistor.
P100-P103fDo-D3 (Port 10/Data I/O)
4-bit I/O port. This port can sink 10 mA and interface
12 V. If any of these pins are unused, connect them to
ground or Voo in the input state, or leave open in the
output state. The port is in the high impedance or
high-level output-state at reset. 00-03 are 4-bit I/O pins
for program memory write/Verify.
,n
PIN FUNCTIONS
POoIINTONpp, P011SCi<
POaISO, PO31'S I
. (Port O/Count Clock Input/Programming/
Serial Interface)
4-bit input port O/count clock input/serial I/O interface.
This port can be configured as a 4-bit parallel input port
or as the S-bit serial I/O interface, under control of the
serial mode select register. The serial input SI (active
high), serial output SO (active low), as the serial clock
SCK (active low-synchronizes data transfer) comprise
the S-bit serial I/O interface. If POollNTO is unused,
connect it to ground. If any of P01-P03 are unused,
connect them to ground. The port is in the input state at
reset.
P80-PSVMDO-MD2, P83/MD3 (CL2IMD3)
(Port 8/Clock Input/Mode Selection for OTP)
4-bit output port S. This port can sink 15 rnA and
interface 12 V. PS3 is a output port on the ",P075P64; On
the ",P075P54, CL2 is one of the pins to which a resistor
for RC oscillation is connected. On the ",P075P64, CL2
is one of the pins to which a ceramic resonator is
connected. If any of PSO-PS2 pins are unused, leave them
open. The port is in the high impedance state at reset.
MOO-M03 are used for OTP program memory write and
read mode selection. There is no PS3 on the ",P075P64.
3-122
P11o-P113fD4-Dr (Port 11/Data I/O)
4-bit I/O port. This port can sink 10 rnA and interface
12 V. If any of these pins are unused, connect them to
ground or Voo in the input state, or leave open in the
output state. The port is in the high impedance or
high-level output state at reset. 0 4 -07 are 4-bit I/O pins
for program memory write/Verify.
Vss (Ground)
Ground.
NEe
IIPD75P54/P64
Block Diagram
POO liNTON PP
POO·PO 3
P80·P82.1~1~
0-
P8 3 (CL2).] •
Program
Memory
1024 x 8 Bits
CL
PIOO .PI03/~~I~
III
System Clock
Generator
Stand By
Control
! ! ! !
Vpp Voo VSS Reset
@~~ For 75P54 and 75P84 (OTP)
\!II
For7564
For 77541P54/P64
83Yl-7180B
FUNCTIONAL DESCRIPTION
I/O Ports
Figure 1 shows the internal circuits at I/O ports 0, 8, 10,
and 11.
3-123
II
t-IEC
pPD75P54/P64
Figure 1. Interface at I/O Ports
Type P-A
Type A
(forTypeW)
VDD
~~
-Ch
Input
Data ---~-r""",
'
Mask option for
mask devices
N-ch
~--+----o In/Out
CMOS standard input buffer
Output Disable --+----,L~
TypeB-B
MDO·MD2
Input o--"t""-..,.j
-----0<:
TypeQ-A
I
RC
,
IL_o_s_ci_lIa_to_r...l~
To PROM unit
~pe
...<>--__-o0CLI
_
Mask
P83/MD3 (Cl2lMD3)
ift.ti~~sk
0
~devices
When a voltage of 21 V is applied'to this pin, Vpp Is supplied to the PROM
unit. When input of VSS to VDD i. applied, VDD is supplied to this pin.
TypeD
(for Types Wand X)
TypeR
VDD
DataE~_Ch
Input 0-_.--1
Output
N-ch
Output Disable
':"
Push·pull output where output can be placed in high impedance
when a RESET input is applied. P and N channels are tumed off.
TypeP
TypeS
VDD
Data ---~-r""",
h
l !
P-;h
Mask option for
mask devices
VOD
t. . .," " . . . . . .
Input 0---1---+----1
~--+---o In/Out
Output Disable ---+-'--L~
N-ch
49NR-677B
3-124
NEe
pPD75P54/P64
Figure 1. Interface at 110 Ports (cont)
Type X
TypeW
In/Out
Output
Disable
TypeY
r:-~""l-'----OCll
Data
Data
VoD
!
Mask option
for mask
devices
f
Output
Disable
In/Out
L.:=:::...t-T--<>CI.2IMD3.
VDD
!
i
MOS
~~!~ttion
devices
'(9NR-&78B
3-1.25
II
t\fEC
pPD75P54/P64
Table 1 compares the features of the p.PD7554/64 and
their aTP versions, p.PD75P54/P64.
Table 1. Product Differences and Comparisons. pPD7554/64 and pPD75P54iP64
Item
Instruction
cycle/system
clock (5 V)
,.PD7554
,.PD7564
,.PD75P54 (OTP)
RC
4,.s/
500 kHz
41£S/
500 kHz
4,.s/
500 kHz
'External
2.86 p.s/
700 kHz
Ceramic
,.PD75P64 (OTP)
2.86,.s/
700 kHz
2.86,.s/
700 kHz
3,.s/
660 kHz
Instruction set
47 (set B)
47 (set B)
47 (set B)
47 (set B)
ROM or PROM
1024 x 8 mask ROM
1024 x 8 mask ROM
1024 x 8 one·time
PROM
1024 x 8 one·time
PROM
RAM
64x4
64x4
64x4
64x4
I/O port total
16 (max)
15
16 (max)
15
PortO
POO·P03
POO·P03
POo·POsIMDO ·MD3
POo·POs/MDO·MD3
POo pin mask option
Available
Available
None
None
Port 8
P80·P82
P8s/CL2
P80·P82
P8o·P82/MDO·MD2
P8s1MD3
P8()"P82/MDO·MD2
CL2IMD3
P1Oo·P10s/Do·D3
Port 10
P10o•P103
P10o·P103
P10o·P10s/Do·D3
Port 11
P11o·Pl13
P11o·Pl13
P11o·P11s/D4·D7
P11o·P11s/D4·D7
Timer/event
counter
8·bit
8·bit
8·bit
8·bit
Serial interface
8·bit
8·bit
8·bit
8·bit
Sense input
INTO, INTS, INTT
INTO, INTS, INTT
INTO, INTS, INTT
INTO, INTS, INTT
Supply voltage
2.5 to 6.0 V
2.7 to 6.0 V
4.5 to 6.0 V
4.5 to 6.0 V
Process
CMOS
CMOS
CMOS
CMOS
Package
20'pin plastic SOP
20'pin plastic SOP
20·pin plastic SOP
20·pin plastic SOP
20·pin shrink DIP
20'pin shrink DIP
20'pin shrink DIP
2O·pin shrink DIP
Output and I/O pins
N-channel open drain
N·channel open drain
N·channel open drain
N-channel open drain
Input pins
Mask options
available
Mask options
available
No on·chip resistor
No on-chip resistor
RESET
Mask options
available
Mask options
available
No pull·down resistor
No pull·down resi stor
3-126
NEe
pPD75P54/P64
I£PD75P64 Application
Figure 2 shows an example of an application circuit for
remote-controlled data reception, key input, and LED
display for the ~PD75P64.
Figure 2. Remote-Controlled Data Reception, Key Input, and LED Display (pPD75P64)
-SCK
SO
51
-SCK
SO
J-
P113
RESET
Master
Microcomputer
I'PD750SHI
I'PD7519H
Chip Select
or Transfer
Request
SLEDS
!1PD75P64
r
r-
Output
Open Drain
Amplifier
Circuit
I'PC1473
Q~ G~
G~ G~
~
~
G~ G
~ Q~ G~
f--
~
PS1
PS 2
P112
Remo te
Cont
Is
Signaro:~
Driver
I'PASOC
outputt110
CMOS P111
51
...
.4~
A~
.4.
On.chip
Input P101
Pull-Up P102
Resistor P103
INTO
CL1
CL2
}1D~
r r
Key Input 4 x 4
49NR-676B
3-127
NEe
pPD75P54lP64
OTP PROM (Program Memory Write and Verify)
The p.PD75P54/P64 is a, one-time programmable (OTP)
PROM. version of the p.PD7554/64. The OTP is programmed by the pins and their functions listed in table 2.
During OTP programming, addresses are updated by
inputting clocks, instead of addresses, from the CL 1 pin,
Table 2. OW Access
Pin
Function
Vpp
OTP programming voltage pin (normally Voo)
Address update clock input during programming
CL1
Mode selection during OTP programming
MOO-M03
a-bit data I/O pins during OTP programming
Supply voltage pin: 4.5 to 6.0 V during normal
Voo .
operation; 6 V during OTP programming
Program Memory Write Procedure. The program memory write procedure follows (high speed write is enabled):
..
.
(1) Connect unused pins to Vss through a pull-down
resistor. RESET is pulled up to Voo through a resistor. Hold CL 1 low.
(2) Supply 5 V to Voo and Vpp.
(3) Select the program memory address clear mode.
(4) Change the voltage onVoo to 6 V, and on VPP to
21 V.
(5) Select the program inhibit mode.
(6) Write data in the 1 ms write mode.
(7) Select the program inhibit mode.
Notes:
The IIP075P54/P64 has no erasure window. The program memory
data cannot be erased with ultraviolet light
(8) Select the verify mode. If data is written correctly,
proceed to step 9; if data is not written correctly,
repeat steps 6-8.
OTP Operation Mode
(9) Perform an additional write of X (number of times a
write was performed in steps 6-8) x 1 ms.
The p.PD75P54/P64 operates in the program memory
write/verify mode when +6 V is applied to Voo and 21 V
to Vpp. Mode pins MDO-MD3 select the operation modes
shown in Table 3.
(11) Increment the program memory address by one, by
inputting four pulses to CL 1.
(10) Select the program inhibit mode.
(12) Repeat steps 6-11 until the end address occurs.
Table 3. OW Ope,ation Mode Selection
Vpp = +21 V; voo = +6V
MOO MD1
MD2
M03
H
L
H
L
L
H
H
H
L
L
H
H
H
X
H
H
Operating Mode
Program memory address clear (Note 2)
Program memory write (Note 3)
Program memory verify (Note 4)
Program Inhibit (Note 5)
Notes:
Lor H.
While HLHL is being applied, the program counter continues to
be cleared.
(3) While LHHH is being applied, data applied to 00-07 continue to
be written to the OTP.
(4) While LL HH is being applied, the OTP contents at the address
that the program counter indicates continue to be output to
PO-07.
(5) While HXHH Is being applied, the OTP continues to be nonaecessible, and 00-07 remain at a high Impedance level.
(1) X =
(2)
3-128
(13) Select the program memory address clear mode.
(14) Change the voltage on Voo and VPP to 5 V.
(15) Turn off power.
The timing for steps 2-11 is shown in figure 3.
IIPD75P54/P84
Figure 3. Tlml. DIag,.", tor OTI'",...",
~
1Iemor, Wrll.
. X RepetllIona.
.1.
I--Wrfte
Verify
:I.
Additional Wr!te-...• f41·---Add,...I-:----I.1
~p---r------------------------~J,~r----------------------------------VpP
Voo
V o o J ..
VOO.1
Voo
J
r(
sir
ell
,
•
00·07
-------<{
InputDa1a
.~.F--{
InputDa1a
)>----------------------
..I1
M01 _____
M02J
M03
•rr
--.:I
Program Memory Read Procedure. The program memory read procedure follows:
(1) Connect unused pins to Vss through a pull-down
resistot RESET Is pulled up to Voo through a resistor. Hold CL 1 low.
(6) Select the verify mode. Data is read from "OOOH.Upon entry of a clock pulse to CL 1, data is sequentially output by one address In a cycle of four pulses.
(2) Supply 5 V to Voo and Vpp.
(7) Pulse input to the CL 1. Program memory address is
updated at the rising edge of the third pulse. Address after updated one (+ 1) Is updated every four
pulses. Repeat update to last address.
.
(3) Select the program memory address clear mode.
(8) Select the program memory address clear mode.
(4) Change the voltage on Voo to 6 V, and on Vpp to
21 V.
(9) Change the voltage on Voo and Vpp to 5 V.
(10) Turn off power.
(5) Select the program inhibit mode.
The timing for steps 2-9 is shown in figure 4.
3-129
•
pPD75P54/P64
Figute 4.
NEe
Timing Dillgram for Program Memory Read
~pVPP--J'~--------------------------------------~--------------~L(
VOO--/
Vo:o+l--jrr--------------------------------------------------------~J.~c-------VOO--/
ell
~-07----------~(~______o_~_p_ut_o_am______~)(~______o_~_pu_t_oa_m____--J)(~------~~----~)MOO)
\~--~--------~~l~
MOl
------------------------------------------------------------~L~(--------
M02)
$ ...
M03--./
49NR.saoB
··3"'-1'30
NEe
pPD75P54/P64
Capacitance
ELECTRICAL SPECIFICATIONS
TA = 25°C, Voo = Vss = 0 V; f = 1 MHz. Unmeasured pins
returned to Vss.
Absolute Maximum Ratings
TA = 25°C
Operating temperature, TOPT
-10 to +70°C
Storage temperature, TSTG
-65 to +150°C
Power supply voltage, Voo
-0.3 to +7.0 V
Input voltage, VI
Except ports 10, 11
Ports 10, 11 (Note 1)
Ports 10, 11 (Note 2)
-0.3 to Voo +0.3 V
-0.3 to Voo +0.3 V
-0.3 to +13V
Output voltage, Vo
Except ports 10, 11
Ports 10, 11 (Note 1)
Ports 10, 11 (Note 2)
-0.3 to Voo +0.3 V
-0.3 to Voo +0.3 V
-0.3 to +13 V
Output current, high 10H
One pin
All output pi ns, total
-5mA
-15mA
Output current, low 10L
P01, P02
Ports 10,11
PortS
All ports, total
5mA
15mA
30mA
100mA
Power dissipation, Po (T A = + 70°C)
Shrink DIP
SOP
Parameter
Symbol Min Typ Max Unit Conditions
Input capacitance
CI
50
pF
POo
15
pF
P03
Output capacitance Co
35
pF
PortS
1/0 capacitance
35
pF
Ports 10, 11 and
P01, P02
II
4S0mW
250mW
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent
damage. The device should be operated within the limits specified
under DC and AC Characteristics.
Notes:
(1) CMOS I/O or N-channel open drain + internal pull up resistor.
(2) N-channel open drain 1/0.
3-131
ttlEC
pPD75P54/P64
DC Characteristics, Normal Operation; Voo = 4.5 to 6.0 V; Vss = 0 V
TA = -10 to +70"C
Parameter
Symbol
Max
Unit
Input high voltage except CL 1
VIH1
0.7VOO
VOO
V
Input high voltage CL 1
VIH2
Voo-0.5
VOO
V
Input high voltage ports 10, 11 (Note 1)
VIH3
0.7VOO
12
V
Input high voltage RESET
VIHOR
0.9 VOOOR
VOO OR + 0.2
V
Input low voltage except CL 1
VILl
0
0.3 VOO
V
Input low voltage CL 1
VIL2
0
0.5
V
3
p.A
10
p.A
oV :s VI :S VOO
oV :S VI :S VOO
10 (Note 1)
p.A
VI = 12 V
V
IOH = -1 mA
V
POj, ~: IOL = 1.6 mA;
Ports 10, 11: IOL = 1.6 rnA
Port 8: IOL = 15 rnA
Ports 10, 11: IOL = 10 rnA
Input leakage current except CL 1
Min
ILI1
-3
Input leakage current CL 1
ILI2
-10
Input leakage current ports 10, 11
ILl3
Output voltage high POl, P~, ports 8-11
VOH
Typ
Voo-2.0
Conditions
Data retention mode
Output voltage low POl, P~, ports 10, 11
VOL
0.4
Output voltage low ports 8, 10, 11
VOL
2.0
V
3
p.A
OV:sVo,.VOO
10 (Note 1)
p.A
Vo = 12V
Output leakage current
IL01
Output leakage current ports 8-11
IL02
Supply voltage, data retention mode
VOOOR
Supply current, normal operation
IDOl
Supply current, HALT mode
Supply current, STOP mode
Supply current, data retention mode
Notes:
(1) N-channel, open drain 1/0 ports.
3-132
-3
6.0
V
400
1400
p.A
p.PD75P54: VOO = 5 V ±10%;
R=56kD±2%
700
2300
p.A
p.PD75P64: VOO = 5 V ± 10%;
fcc = 700 kHz
120
400
p.A
p.PD75P54: VOO = 5 V ± 10%;
R = 56 kD ±2%
450
1500
p.A
p.PD 75P64: VOO = 5 V ±10%;
fcc = 700 kHz
1003
0.1
10
p.A
VOO = 5.0 V :tl0%
1000R
0.1
5
p.A
VOOOR = 2.0 V
1002
2.0
1tt{EC
pPD75P54/P64
DC Characteristics, Programming Mode; Voo = 6.0 ± 0.25 V; Vpp = 21 ± 0.5 V, Vss = 0 V
(Notes 1 and 2)
TA
= 25°C
Parameter
Symbol
Input high voltage except C L 1
VIHl
0.7VOO
Input high voltage CL 1
V IH2
Input low voltage except CL 1
VILl
Input low voltage CL 1
VIL2
Input leakage current
III
Min
Typ
Max
Unit
VOO
V
VOO -0.5
VOO
V
0
0.3VOO
V
0
0.5
V
10
p.A
Conditions
Output voltage high
IOH
V
IOH = -1 rnA
Output voltage low
VOL
0.4
V
IOL = 1.6 rnA
Voo supply voltage
100
30
rnA
Vpp supply current
Ipp
30
rnA
Voo-2.0
MOO
= VII.. M01 = VIH
Notes:
(1) Vpp, including an overshoot, should not exceed +22 V.
(2) Apply Voo before Vpp, and cut off aiter Vpp.
Figure 5. Recommended Circuit.
RC Oscillation
CL1
R
I'P075P54
CL2
Extemal Clock
CMOS
.....
.....
Cll
i1P075P54
Open- Cl2
Ceramic Resonatot
Cl
GJ.
~
C2
T
Cll
i1P075P64
R2
CL2
49NR·681A
3-133
II
NEe
pPD75P54/P64
AC Characteristics, Normal Operation; Voo = 4.5 to 6.0 V; Vss = 0 V
TA = -10 to +70·C
Parameter
System clock oscillation frequency
Symbol
Min
Typ
Max
Unit
Conditions
fcc
400
500
600
kHz
"PD75P54: R = 56 kQ ±2%
290
710
kHz
"PD75P64: R = 100 kll ±2%
710
kHz
"PD75P54: 50% duty
ms
"PD75P64 (Note 1)
External clock frequency, CL 1
fc
10
Oscillation stabilization time
tos
20
System clock rise time, CL 1
teR
0.2
System clock fall time, CL 1
teF
0.2
,,5
"s
"s
System clock pulse width
teH
0.7
50
System clock pulse width, CL 1
tel
0.7
50
"s
Event Input frequency (POol
fPO
0
710
kHz
POo rise time
tpOR
200
ns
POofall time
!POF
POo pulse width, high
ipaH
0.7
"s
Voo = 4.5 to 6.0 V
POo pulse width, low
tpOl
0.7
1'8
Voo = 2.7 V
INTO high time
tlOH
10
1'8
INTO low time
~Ol
10
RESET high time
tRSH
10
RESET low time
~Sl
10
"s
RESET setup time
!sRS
0
"s
RESET hold time
~RS
0
"s
Ij<;CY
2.0
"s
Input
2.5
"s
Output
S"CK cycle time
200
50% duty
ns
"s
,,5
S"CK pulse width, high
S"CK pulse width, low
tKH
1.0
"s
Input
tKL
1.25
"s
Output
SI setup time to ~ t
tSIK
0.1
SI hold time after ~ t
"s
tKSI
0.1
SO output delay time after ~ t
tKSO
Notes:
(1) Hold the RESET Signal at a high level until oscillation becomes
stable.
3-134
"s
0.85
"s
CL = 100 pF
NEe
pPD75P54/P64
AC Characteristics, Programming Mode; Voo
= 25°C
= 6.0 ± 0.25 V; Vpp = 21
±0.5 V, Vss
=0 V
TA
Parameter
Symbol
Note 1
Address setup time for MDO J, (Note 2)
tAS
tAS
2
",s
p,S
Min
Typ
Max
Unit
MDI setup time for MDO J,
tMIS
tOES
2
Data setup for MDO J,
tos
tos
2
p,S
Address hold time for MDO t (Note 2)
tAH
tAH
2
",s
Data hold time for MDOt
tOH
tOH
2
MDO t to data output float delay time
tOF
tOF
0
Vpp setup time for MD3 t
tvps
tvps
2
VOO setup time for MD3 t
tvos
tvcs
2
Initial program pulse width
lpw
tpw
0.95
Additional program pulse width
topw
topw
0.95
teES
2
MDO setup time for MDI t
iMos
Conditions
",s
200
ns
",s
",s
1.0
1.05
ms
21.0
ms
",s
MDO J, to data output delay time
toy
tov
p,S
MDO
= MDI =VIL
MDI hold time for MDO t
tM1H
tOEH
2
p,S
iM1H
+ tMIR
MDI recovery time for MDO J,
tM1R
tOR
2
p,S
",s
1 (Note 3)
Program counter reset time
tpCR
10
CL 1 input high- and low-level widths
tXH' tXL
0.7
CL 1 input frequency
fx
'" 50
"'S
"'s
710
kHz
Initial mode set time
lJ
2
"'s
MD3 setup time for MDI t
tM3S
2
",s
MD3 hold time for MC11 J,
tM3H
2
MD3 setup time for MDO J,
tM3SR
2
"'S
"'S
Address to data output delay time (Note 2)
tOAD
tACC
2
Address to data output hold time (Note 2)
tHAD
toH
0
MD3 hold time for MDO t
tM3HR
2
",s
MD3 J, to data output float delay time
tOFR
2
",s
During program memory read
p,S
300
ns
Notes:
(1) Symbol of the corresponding ",PD27C256.
(2) "1" is added to the internal address signal at the rising edge of
the third CL 1 input. The signal is not input to the pin.
(3) During CMOS output.
3-135
t\fEC
pPD75P54/P64
Timing Waveforms
Test
AC TeBt Points
.J
Clock
Cl1 Input
INTO
RESET
RESET
Serial Transfer
POD Input
3-136
ttlEC
pPD75P54/P64
Program Memory Write
tyPS
Vpp
Vpp
Jr-----------------------------{,:~--------------------------------------------~5~
VOO
IVOS
VOO-1
VOO
~----------------------------~}!~------------------------------------------_i/~
VOO
Cl1
II
MOO
.,
M01
M02
IM3~~-
--------------------~~--------------------------------~.,
~
49NR-686B
3-137
NEe
IIPD75P54/P64
Program Memory Read
tvps
VpP
VpP
VDD
IVDS
.r
VDD+1
VDD
VoD
CL1
-+-+...............41l\-...................._ _ _ _ _...J:"-_ _ _O_utpu_I_D_a_ta_ _ _...I
DO-D7 .....
~
O_U_IP~UI~
,,_ _ _
~
IM3HR
MDO
MD1
MD2
MD3
49NR-687B
3-138
NEe
pPD75P54/P64
Dlltll Retention Timing, pPD75P54
STOP Instruction
Execution
~------------------STOPMode-----------------1
Operation
Mode~
i+------Data Retention Mode *
VDD
VDDDR
RESET
VIHDR
• In the data retention mode. set all inputs to a value smaller than V DDDR.
49NR-6898
II
Dlltll Retention Timing, pPD75P64
STOP Instruction
Execution
HALT
Mode
I-~------------------STOPMode------------------~
00If- Operation
Mode-"'-
Ii+-----Data Retention M o d e ' VDD
I
' - - - _ -VDDDR
==_--J
tosl-• In the data retention mode, set all inputs to a value smaller than V DOOR.
49NR-&88B
3-139
pPD75P54/P64
3-140
ttlEC
NEe
IIPD7556/56A/66/66A
4-Bit, Single-Chip
CMOS Microcomputers
With Comparator
NEG Electronics Inc.
Description
Ordering Information
The J.lPD7556/66A and J.lPD7566/66A are low-end versions of J.lPD7500 series products. These microcomputers incorporate a 4-bit comparator input and are useful
as slave CPUs to high-end J.lPD7500 series or 8-bit
J.lCOM-87 series products.
Part Number
Package Type
IlPD7556CS
24-pin plastic shrink DIP
IlPD7556ACS
IlPD7566CS
IlPD7566ACS
The J.lPD7556/56A/66/66A has output ports that can
directly drive triacs and LEDs. Also, various maskoptional I/O circuits can be configured for a wide
selection of outputs allowing a reduction of external
circuitry in your design. There are two testable interrupts.
The J.lPD7556/56A and J.lPD7566/66A differ only in their
clock circuitry. The J.lPD7556/56A uses an external resistor with an internal capacitor for an RC oscillator clock,
where the J.lPD7566/66A uses a ceramic oscillator as a
clock. These microcomputers are ideally suited to control devices such as air conditioners, microwave ovens,
refrigerators, rice cookers, and audio equipment.
Features
24-pin plastic SOP
IlPD7556G
IlPD7556AG
IlPD7566G
11
IlPD7566AG
Pin Configurations
I
2O-Pin Plastic Shrink DIP
pP9o-P91
VDD -JNv-,
.
. .... 0 Mask Option
0
.-----(ll-
Data
~-o11 O-Pl13
VDD
Data
Mask Option
r-----+---O In/OUt
(Middle-Level Voltage.
Middle-Level CurrenQ
Mlddle·Level Voltage Input Buffer
Type 3 Input Cell: POl "'REF
vDD -JNv-,
. ,. . 0
Mask Option
Type 6 Schmitt-triggered Input: RESET
o
~r-----/1~Mas---ko-p~:n
Reference
Voltage
3-144
t
83SL-6852B
NEe
IIPD7556/56A/66/66A
Program Memory
Arithmetic Logic Unit
The ttPD7556/56A/66/66A has a mask-programmable
ROM with a capacity of 1024 words by 8 bits for program
storage. It is addressed by the program counter. The
reset start address is OOOH. Figure 2 shows the program
memory map.
The arithmetic logic unit (ALU) is a 4-bit arithmetic
circuit that performs operations such as binary addition,
logical operation, increment, decrement, comparison,
and bit processing.
Program Status Word
General-Purpose Registers
Two registers, H(2-bit) and L(4-bit) are provided as
general-purpose registers. Each register can be individually manipulated. The two registers also form pair
register HL; H being the high register and L being the low
one. The HL register is a data pointer to address data
memory. Figure 3 shows the configuration of the generalpurpose registers.
The L register also specifies an I/O port or mode register
when an I/O instruction (IPL or OPL) is executed. It also
specifies the bits of a port when the SPBL or RPBL
instruction is executed.
Data Memory
The data memory is static RAM with a capacity of 64
words by 4 bits. Part of this memory is used as the stack
area. The data memory is also used in 8-bit data processing when paired with the accumulator. Figure 4
shows the data memory map.
Data memory can be addressed directly, with the immediate data from an instruction; indirectly, with the contents of HL (including auto-increment and autodecrement); and indirectly by the contents of the stack
pointer.
You may use any area of the data memory as the stack.
The boundary of the stack is determined by how the
TAMSP instruction initializes the stack pointer. Once the
boundary is set, a call or return instruction automatically
accesses the stack.
When a call instruction is executed, the contents of the
program counter and the program status word (PSW) are
stored to the stack in the sequence shown in figure 5.
When a return instruction is executed, the contents of
the program counter are automatically restored, but the
PSW is not. The contents of data memory can be retained
with a low supply voltage during STOP mode.
The program status word (PSW) consists of two skip
flags (SKO and SK1), a carry flag (C), and bit 1, which is
always zero. Figure 7 shows the configuration of the
PSw.
The contents of the PSW are stored to the stack when a
call instruction is executed, but are not restored from
the stack by the return instruction.
The skip flags retain the following skip conditions: string
effect by LAlor LHLI instruction, and skip condition
satisfied by an instruction other than a string-effect
instruction. The skip flag is set or reset according to the
instruction executed.
The carry flag is set to 1 if an addition instruction (ACSC)
generates a carry from bit 3 of the ALU. If no carry is
generated, the flag is reset to zero. The SC instruction
sets the carry flag and the RC instruction resets it.
When a RESET is input, the SK1 and SKO flags are
cleared to zero and the contents of the carry flag are
undefined.
System Clock Generator
The system clock generator consists of a RC oscillator
(ttPD7556/56A), a ceramic resonator (ttPD7566/66A), a
1/2 frequency divider, standby modes (STOP/HALT), and
control circuit. Figure 8 is a circuit diagram of the system
clock generator for the ttPD7556/56A.
In the ttPD7556/56A, the RC oscillator operates with a
single external resistor connected across CL 1 and CL2
(the capacitor C is incorporated). When the RC oscillator
is not used, external clock pulses can be input by the
CL 1 pin. In this case, the RC oscillator functions as an
inverting buffer. The output from the R C oscillator serves
as the system clock (CL) which is then divided by two
and used as the CPU clock (cp).
Accumulator
The accumulator is a 4-bit register used in arithmetic
operations. The accumulator can process 8-bit data with
paired data addressed by HL. Figure 6 shows the configuration of the accumulator.
3-145
II
NEe
pPD7556/56A/66/66A
The standby mode control circuit is made up of a STOP
flip-flop and a HALT flip-flop. The STOP instruction sets
the STOP flip-flop and stops the system clock supply.
This flip-flop also stops the RC oscillator. The STOP
flipcflop is reset by the standby release signal that
becomes active when one of the test requests flags is set
or at the falling edge of the RESET signal. When the
STOP flip-flop is reset, the RC oscillator resumes operation and supplies the system clock.
The HALT and STOP instructions and RESET HIGH set
the HALT flip-flop which disables signals from going to
the 1/2 frequency divider that generates the CPU clock.
Only the CPU clock stops in HALT mode. The HALT
flip-flop is reset by the same conditions as the STOP
flip-flop.
Figure 9 shows the system clock generator circuit forthe
I'PD7566/66A.
(O)OOOH
(1023)3FFHU
83-002592A
Figure 3. Configuration of General Purpose
Registers
1
The HALT instruction sets the HALT flip-flop which disables signals from going to the 1/2 frequency divider that
generates the CPU clock. Only the CPU clock stops in
HALT mode. The HALT flip-flop is reset by the HALT
RELEASE signal (activated by setting at least one test
request flag) or the falling edge of RESET, resuming
supply of the CPU clock.
The HALT flip-flop is also set when RESET is active (high
level). At power on reset operation, the rising edge of
RESET starts ceramic oscillation; however, some time is
required to achieve stable oscillation. To prevent the
unstable clock from operating the CPU, the HALT flipflop is set and the CPU clock is stopped while RESET is
high. Accordingly, the high-level width of RESET must be
more than the required stable time for the ceramic
resonator.
0
~
3
0
r'-I-----'-II
.~I
Figure 4. Data Memory Map
On the I'PD7566/66A, the ceramic oscillator operates
with a ceramic resonator connected across CL 1 and
CL2. The output from the ceramic oscillator is used as
the system clock (CL); it is divided by two to produce the
CPU clock (c/».
The standby mode control circuit is made up of a STOP
flip-flop and a HALT flip-flop. The STOP instruction sets
the STOP flip-flop and stops the ceramic oscillation,
thus stopping the supply for all clocks. The STOP flipflop is reset by the RESET signal (high level) and restarts
ceramic oscillation. The supply of each clock resumes
when RESET goes low.
n
Figure 2. Program Memory Map
(0) DOH
64 words x 4 bits
(63) 3FH L -_ _ _-I
83-Q02594A
Figure 5. Call Instruction Storage to Stack
Stack Area
3
SP·4
SP·3
SP·2
Sp·1
°
°lolpc·l pC8
psw'
pc.·pc,
pc,·pc.
*Blt 1 of PSW
Is always O.
83-002595A
Figure 6. Configuration of the Accumulator
.J
Figure 7. Configuration of the Program Status
Word
.
3
2
0
SK,
SK,
c
I I I°I I
PSW
83-00.2597A
3-146
NEe
pPD7556/56A/66/66A
Figure B. System Clock Generator for pPD7556/56A
STOP F/F
S
Q
1 - - - - - - - - -__
STOP'
HALT F/F
R
Q
S
HALT'
RESET (High)
Standby Release
RESET ( _____ )
• (to CPU)
' - - - - - - - - - - - - - _ CL (System Clock)
*Executlon of Instruction
83-0025986
Figure 9. System Clock Generator for pPD7566/66A
STOP F/F
Q
S
J---------J.r-l-,-- STOP'
HALT F/F
Q
F~---I-- HALT'
S
CL1
RESET (High)
Ceramic
Oscillator
Standby Release
CL2
'-
\ - - - - RESET
'---f----------
RESET
"-~
(To CPU)
' - - - - - - - - - - - - - - _ CL (System Clock)
* Execution of Instruction
83-0025998
Clock Control Circuit
The clock control circuit consists of a 2-bit clock mode
register (bits CM1 and CM2), prescalers 1, 2, and 3, and
a multiplexer. It takes the output of the system clock
generator (CL) and event pulses (POc). It also selects the
clock source and prescaler according to the setting in
the clock mode register and supplies the timer/event
counter with count pulses. Figure 10 shows the clock
control circuit.
Table 2 lists the codes set in the clock mode register by
the OPL instruction to specify the count pulse frequency.
When you set the clock mode register with the OPL
instruction, clear bit 0 of the accumulator (corresponding to bit CMO of the EVAKIT-7500 or ILPD7500H during
emulation).
3-147
II
NEe
pPD7556/56A/66/66A
Test Control Circuit
Figure 10. Clock Control Circuit
The ~PD7566/66A has two test sources, as shown in
table 3.
The test control circuit consists of two test request flags
INTT RQF and INTO RQF) set by the two test sources,
the SM3 flag which determines whether INTO is enabled,
and a test request flag control circuit that checks the
contents of each test request flag by executing an SKI
instruction and resetting the flags.
CL
The OPL instruction (L = FH, corresponding to A3) sets
the SM 3 flag. INTO is enabled when SM 3 = 1.
Table 3. p,PD7556/56A/66/66A Test Sources
poo------t=~~==i~
"Instruction
Execution
Source
Function
Location
Request Flag
INTT
Overflow in timer/
event counter
Internal
INTT RQF
INTO
Test request signal
from POo pin
External
INTO RQF
83-002600A
Table 2. Selecting the Count Pulse Frequency
CM2
o
o
CM1
Frequency Selected
o
CL/256
o
CL/32
The request flag INTT RQF is set when a timer overflow
occurs in the. timer event counter. The SKI or TIMER
instruction resets it.
The logical sum of the outputs from the test request flags
releases HALT mode. The mode is released when one or
both flags are set. Both flags and SM3 are reset when the
RESET Signal is input. After reset, signal input to the
INTO pin is inhibited as the initial condition.
CL/4
Figure 12 is a block diagram of the test control circuit.
Timer/Event Counter
The timer/event counter is a binary 8-bit up-counter
which is incremented each time a count pulse is input.
The TIMER instruction or a RESET signal clears it to
OOH. When an overflow occurs, the counter is reset from
FFH to OOH. Figure 11 shows the inputs and outputs of
the counter.
Figure 11. TimerlEvent Counter
·TCNTAM--...,....-----+\
CP
"Timer
Reset
"Instruction Execution
83-002601A
ttlEC
Figure 12.
pPD7556/56A/66/66A
Test Control Circuit Block Diagram
Internal Bus
INn-+-----I
II
HALT
Release
INTOV--'-----J
Note (1)
Instruction execution
83-0026028
Standby Modes
Table 4. S TOP and HALT Modes
The ~PD7556/56A/66/66A has two standby modes to
reduce power consumption while the program is in the
wait state. The STOP and HALT instructions set these
modes.
Mode
CL
q.
POo
CPU
STOP
x
x
o
x
When the program enters a standby mode, program
execution stops and the contents of all registers and
data memory immediately before the program entered
standby mode are retained. The timer can operate even
in HALT mode.
The RESET signal or STANDBY release signal(1) releases
STOP mode. HALT mode is released when one or both of
the test request flags are set, or when the RESET signal
is input. The program cannot enter a standby mode
when a test request is being set, even if the STOP or
HALT command is executed.
If there is some uncertainty about the state of the test
request flags, execute the SKI instruction to reset them
so the program can enter standby mode.
Table 4 compares STOP and HALT modes. The. main
difference is that STOP mode stops the system clockand
HALT does not. Oscillation stops during STOP mode.
The power consumed by the oscillator is the difference
between the two modes. In STOP mode, data memory
can be retained with a lower supply voltage.
Note:
(1) Standby release signal for ~PD7556/56A only.
Timer
Released by
RESET input
INTTRQF,
INTO RQF
(,aPD7556/56A only)
HALT
0
x
o
x
o
INTTRQF
INTO RQF
RESET input
Notes:
(1) 0: operates. x: stops.
6.: operates depending on clock source. "PD7556/56A; if external
clock is used, STOP instruction will not stop CL. In this case
STOP mode acts as HALT mode.
Power-on Reset Circuit
Figure 13 shows a circuit example of the power-on reset
circuit using a resistor and a capacitor. This is the
simplest reset control circuit. Figure 14 shows the circuit
with a pull-down resistor internally connected to RESET
as a mask option.
"PD7556/56A/66/66A Applications
Figures 15-18 show examples of application circuits for
the ~PD7556/56A/66/66A.
Table 5 compares the features of the low-end products of
the 7500 series devices.
3-149
tt1EC
pPD7556/56A/66/66A
Figure 14. Power-on Reset Circuit with Pull-down
Resistor
Figure 13. Power-on Reset Circuit
!z
-
RESET
RESET
83-002603A
GND
83·Q02604A
Table 5. Product Comparison
Item
Instruction
cycle/system
clock (5 V)
"PD7554/54A
"PD7564/64A
"PD7556/56A
RC
4 "s/
500 kHz
4 "s/
500 kHz
External
2.86 "s/
700 kHz
2.86 "s/
700 kHz
Ceramic
"PD7566/66A
3 "s/
660 kHz
3 "s/
660 kHz
45
Instruction set
47
47
45
ROM
1024 x 8
1024 x 8
1024 x 8
1024 x 8
RAM
64x4
64x4
64x4
64x4
I/O port total
16 (max)
15
20 (max)
19
Port 0
POO·P03
POO•P03
POo-POl
POO•POl
P1o-P13
P01•P03
P8o-P~
P80·P82
Port 1
Port 8
P80·P82
P82/CL2
P80·P82
Port 10
Pl00·Pl03
Pl0o-Pl03
Pl00·Pl03
Pl0o-Pl03
Port 11
Pll 0•Pl1 3
Pll0·Pl13
Pll 0·Pl1 3
Pll0·Pl13
Timer/Event
counter
8·bit
8·bit
8·bit
8·bit
Serial Interface
8·bit
8·bit
4·channel
4·channel
Process
CMOS
CMOS
CMOS
CMOS
Package
20·pln plastic SOP
20·pin shrink DIP
20·pin plastic SOP
20·pin shrink DIP
24·pin plastic SOP
24·pin shrink DIP
24·pin plastic SO P
24·pin shrink DIP
P8a1CL2
Port 9
P9o-P9l
Comparator
3-150
P90·P9l
NEe
,.,PD7556/56A/66/66A
Figure 15. Refrigerator or Air Conditioner Circuitry
lED.4
l2VMax
RES
PBO
PB1
PI!:!
P90
P&,
.,....--I..
P1l3 t-'VII........
CtNo
CtN, Comparator
+-+-11--1 CtN2
CMOS
Output
Input
+--+-1-+--1 CIN3
II
, . . - - - - ; VREF
~VY~~---JV~-,P1~
r-'VY......>-------"'VII'v---i P102 Output
,---------1 Cll
t
Over·Current
Compressor
INTO
CMOS
WllhPull.Up
Detection
Resistor
With
PuIl·Down Pll0
P11j I---<:r
Reslstor
Motor
~
11---..,---1L..CL2
P112!-----0 Mask option
for mask
devices
I-~-+---Oo!lNT4
POltSCK
P02"SOISBO
POa/SI/SBl
P611KRl
Plio ""-
P60fKRO
P8l
P53
P52
P5l
P3l
PSO
psa
P3g
~
P7~R6
P731KR7
P20/PTOO
P2l
P2tPCL
P2aIBUZ
Nola: Vpp Is the programming pin In the 75POOB and should be
connected tD VOO' It Is not connected In the mask ROM ports.
83R~
Nola: Vpp Is the programming pin In the 75POO6 and should be
connected tD Voo. It Is not connected In the mask ROM ports.
83RlJ.I383A
4-4
NEe
Pin Identification
Symbol
Function
NC (Vpp)
No connection
(programming voltage for "PD75POO8
POolINT4
Port 0 input; interrupt 4
POl/SCi(
Port 0 input; serial clock
P02/S0/SBO
Port 0 input; serial out; serial interface
P03l'SI/SBl
Port 0 input; serial in; serial interface
Plo1lNTO
Port 1 input; interrupt 0
Pl l /INTl
Port 1 Input; interrupt 1
P12/INT2
Port 1 input; interrupt 2
P131'TIO
Port 1 input; timer 0 input
P201PTOO
Port 2 I/O; timer/event counter output
P2l
Port 2 I/O
P22/PCL
Port 2 I/O; clock output
P231'BUZ
Port 2 I/O; buzzer output
P30-P33
Port 3 I/O
P40-P43
Port 41/0
P50-P53
Port 51/0
P601KRO
Port 6 I/O; key scan input 0
P6l/KRl
Port 6 I/O; key scan input 1
P62/KR2
Port 6 I/O; key scan input 2
P631'KR3
Port 6 I/O; key scan input 3
P701KR4
Port 7 I/O; key scan input 4
P7l/KR5
Port 7 I/O; key scan input 5
P72/KR6
Port 7 I/O; key scan input 6
P731'KR7
Port 7 I/O; key scan input 7
P80-P8l
Port 81/0
RESET
Reset input
Voo
Positive power supply
Vss
Ground
Xl, X2
Main clock inputs
XT1, XT2
Subsystem ciock inputs
PIN FUNCTIONS
POo·POa, INT4, SCK, SO/S80, SI/S81
(Port 0, Interrupt 4, Serial Interface)
These pins can be used as 4-bit input port O. POo can
also be used for vectored interrupt 4, which interrupts on
either the leading edge or the trailing edge of the signal.
P0 1-P0 3 may also be used for the serial interface in the
SBI, 2-wireor3-wire mode. SI isthe serial input, SO isthe
serial output, and SCK is the serial clock. Reset causes
these pins to default to the port 0 input mode.
pPD7500x/75P008
P10·P1a, INTO·INT2, TIO (Port 1, Edge·Triggered
Interrupts, Timer Input)
These pins can be used as 4-bit input port 1. P10 and P1l
can also be used for edge-triggered interrupts INTO and
INT1. P12 can be used for INT2, which is also an
edge-triggered input, but one which generates an interrupt request and does not cause an interrupt. P13 can be
used as an input clock to the timer/event counter to
count external events. Reset causes these pins to default to the port 1 input mode.
P20·P2a, PTOo, PCl, 8UZ (Port 2, Timer/Event
Counter, Clock, or 8uzzer Output)
These pins can be used as 4-bit I/O port 2. When used as
an output the data is latched. When used as an input port
the port outputs are three-state. P20 can also be used as
the output of the timer/event counter flip flop (TOUT);
P22 can be used as the output for the clock generator
(PCl); and P23 can be used to output square waves for a
buzzer. Reset causes these pins to default to the port 2
input mode.
P30·P3a (Port 3)
These pins are used for I/O port 3. Each bit in this port
can be independently programmed to be either an input
or an output. This port has latched outputs, and can
directly drive LEOs. A reset Signal causes this port to
default to the input mode.
P4o·P4a, P5o·P5a (Ports 4 and 5)
Port 4 and 5 are 4-bit 110 ports which can be combined
together to function as a single 8-bit port. They have
latched outputs. Port 4 will directly drive LEOs. Outputs
are N-channel open drain, and can withstand up to 10
volts; pull-up resistor mask options are available for
these ports. A reset signal causes these ports to default
to the input mode.
p60·P6a, P7o·P7a, KRO·KR7 (Ports 6,7, and Edge
Detection)
Ports 6 and 7 are 4-bit I/O ports with latched outputs.
Each pin of port 6 can be independently programmed to
be either an input or an output, while port 7 can be
programmed to be either all inputs or all outputs. Ports 6
and 7 can be paired together to function as one 8-bit
port. Alternately, these pins may be used to detect the
falling edge of inputs KRO-KR3 (port 6) and KR4-KR7
(port 7). A reset signal causes these ports to default to
the input mode.
4-5
II
:,j
NEe
pPD750Ox/75P008
PSo-P81 (Port 8)
XT1, XT2 (Subsystem Clock Inputs)
Port 8 is a 2-bit I/O port. Outputs are latched. A reset
signal causes this port to default to the input mode.
These pins are the subsystem clock inputs. The clock
can be either a ceramic resonator or a crystal; an
external logic signal may also be used.
NCNpp (No Connection/Programming Pin)
RESET (Reset)
This pin maybe left unconnected when using the
J.tPD7500x. When using the programmable devices, this
pin is used to input the programming voltage during the
EPROM write/verify cycles. During normal operation of
the programmable device, this pin should be tied to Voo.
This is the reset input, and it is active low.
Voo (Power Supply)
The system positive power supply pin.
X1, X2 (Main System Clock Inputs)
Vss (Ground)
These pins are the main system clock inputs. The clock
can be either a ceramic resonator or a crystal; an
external logic signal may also be used.
System ground.
Block Diagram
POO·P03
P10·P13
P20·P23
TI0/P13
PTOO/P20
P30·P33
BUZlP23
Program
Memory
(ROM)
4096. a Bits
(!,PD75004)
6016. a Bits
(!,PD75006)
SI/SB1/P03
So/SBO/P02
P6o-P63
Decode
and
Control
Data Memory
P70·P73
(RAM)
512.4 Bits
8064. a Bits
(!'PD75008/
75POOa)
paO·pal
SCKlP01
INTO/P10
INT1/P1l
INT2IP12
INT4/POO
P60/KRO·
P~/KR3
System Clock
Clock
OUtput
Control
~~C:r
Generator
I---r---I
P701KR4-
~~~y
CPU Clock
t t t
P73/KR7
XT1 XT2
X1
X2
VDD VSS RESET
83YL·5732B
4-6
NEe
pPD7500x/75P008
Product Comparison
,.PD75006
,.PD75008
,.PD75P008CU/GB
Mask ROM
OOOH-FFFH
4096 x 8 bits
Mask ROM
OOOOH-I77FH
6016 x 8 bits
Mask ROM
00OOH-1F7FH
8064 x 8 bits
0000H-1F7FH
8064 x 8 bits
512 x 4 bits
Bank 0: 256 x 4
Bank 1: 256 x 4
512 x 4 bits
Bank 0: 256 x 4
Bank 1: 256 x 4
512 x 4 bits
Bank 0: 256 x 4
Bank 1: 256 x 4
512 x 4 bits
Bank 0: 256 x 4
Bank 1: 256 x 4
3-byte branch instruction
None
Provided
Provided
Provided
Other Instructions
Provided
Provided
Provided
Provided
Program counter
12 bits
13 bits
13 bits
13 bits
Item
Program memory
Data memory
OTP
Can be specified by software
Pull-up resistor,
ports 0-3; 6--8
Pull-up resistor,
ports 4, 5
Mask option
Operating voltage range
2.7 to 6.0 V
Mask option
Mask option
Not provided
2.7 to 6.0V
2.7 to 6.0 V
5V:!: 5%
42-pin plastic shrink DIP
44-pln plastic QFP (bent)
Package
Capacitance
ELECTRICAL SPECIFICATIONS
TA = 25°C; voo= 0 V
Absolute Maximum Ratings
TA = 25°C
Supply voltage, Voo
-0.3 to +7.0 V
Programming voltage, Vpp (.u,PD75P008 only)
-a.3 to +13.5V
Input voltage, VIN1
-0.3 to Voo + 0.3 V
-0.3 to 11 V
Input voltage, VIN2
(Ports 4 and 5 with open drain)
Output voltage, Vo
Symbol
Max
Unit
Input
capacitance
CIN
15
pF
Output
capacitance
COUT
15
pF
I/O
capacitance
CIO
15
pF
Min
Conditions
f = 1 MHz;
all unmeasured pins
returned to ground
-lOrnA
All pins
-30 mA
30 mA peak, 15 rnA rms
All ports except 0, 3-5
20 mA peak, 10 rnA rms
Total of ports 0, 3-5, 8
160 mA peak, 120 mA rms
Total of ports 2, 6, 7
Parameter
-0.3 to Voo + 0.3 V
High-level output current, IOH
Single pins
Low-level output current, IOL (Note 1)
Ports 0, 3-5 (one port pin)
42-pin plastic shrink DIP
44-pin plastic QFP (bent)
66 mA peak, 33 mA rms
Storage temperature, TSTG
-65 to +150°C
Operating temperature, TOPT (.u,PD7500x)
-40 to +85°C
Operating temperature, TOPT (.u,PD75P008 only)
-10to +70°C
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent
damage.
Notes:
(1) Effective value = Peak value x (Duty)1/2
4-7
II
NEe
pPD750Ox/75P008
Main System Clock Oscillator Characteristics
"PD7500x: TA ,;. -4010 +85°C, Voo = 2.7 to 6.0 V
"PD75P008: TA = -10 to +70°C, Voo = 4.5 to 5.5 V
Oscillator
Parameter
Ceramic resonator
(Figure lA)
Oscillation frequency (Note 1)
Crystal resonator
(Figure lA)
Oscillation frequency (Note 1)
External clock
(Figure 18)
Symbol
Min
fxx
1.0
fxx
1.0
Typ
Oscillation stabilization time (Note 2)
Max
Unit
Conditions
5.0
MHz
After Voo reaches the minimum
oscillator operating voltage range.
4 (Note 3)
ms
5.0
MHz
10 (Notes 3, 4)
ms
4.19
Oscillation stabilization time (Note 2)
30 (Notes 3, 5)
ms
Xl input frequency (Note 1)
fxx
1.0
5.0
MHz
Xl input low- and high-level width
txH, tXL
100
500
ns
Notes:
(1) The oscillation frequency and Xl input frequency are included
only to show the characteristics of the oscillators. Refer to the AC
Characteristics table for actual instruction execution times.
(3) Values shown are for the recommended resonators. Values for
resonators not shown in this data sheet should be obtained from
the manufacture~s specification sheets.
(2) The oscillation stabilization time is the time required for the
oscillator to stabilize after voltage is applied or the STOP mode is
released.
(4) Voo = 4.5 to 6.0 V for 7500x or 4.5 to 5.5 V for "PD75P008.
(5) For "PD750OX only at Voo = 2.7 - 6.0 V
Subsystem Clock OSCillator Characteristics
"PD7500x: TA = -40 to +85°C; Voo = 2.7 to 6.0 V
"PD75P008: TA = -10 to +7ooC; voo = 4.5 to 5.5 V
Oscillator
Parameter
Symbol
Min
Typ
Max
Unit
Crystal resonator
(Figure 2A)
Oscillation frequency
fXT
32
32.768
35
kHz
1.0
2
s
See note 4 under Main System
Oscillator Characteristics
2
s
See note 5 under Main System Oscillator
Characteristics
External clock
(Figure 28)
4-8
Oscillation stabilization time
XT1 input frequency
fXT
32
100
kHz
XT1 input low- and high-level width
tXTH, tXTL
5
15
,..s
Conditions
NEe
JlPD7500X/75P008
Recommended Oscillator Circuit Constants (For 7500x only)
Main system clock = Ceramic; TA = -40 to +85°C
o.clliation Voltage
Part Number
(Note 1)
Frequency
C1
C2
Manufacturer
(MHz)
(pF)
(pF)
MlnM
MaxM
Murata
CSAx.xxMK
1.0-1.99
30
30
2.7
6.0
CSA x.xxMG093
2.0-2.44
30
30
2.7
6.0
CST x.xxMG093
2.0-2.44
(Note 2)
(Note2)
2.7
6.0
CSAx.xxMGU
2.45-5.0
30
30
2.7
6.0
CSTx.xxMGU
2.45-5.0
(Note 2)
(Note 2)
2.7
6.0
CSAx.xxMG
2.0-5.0
30
30
3.0
6.0
CSTx.xxMG
2.0-5.0
(Note 2)
(Note 2)
3.0
6.0
KBR 1000H
1.0
100
100
2.7
6.0
KBR 2.0MS,
2.0
47
47
2.7
6.0
KBR 4.0MS
4.0
33
33
2.7
6.0
KBR5.0M
5.0
33
33
3.0
6.0
Kyocera
Notes:
(1) X.xx Indicates frequency.
(2) Cl and C2 not required; they are. in the oscillator.
Figure 1. Main System Clock Conllguratlons
A. Ceramlc/Crystal Resonator
Figure 2. Subsystem Clock Configurations
A. Crystal Resonator
,
.---+---1
Xl
~~T
XTl
C4
'---4----1 X2
XT2
330
len
B. External Clock
B. Extarnal Clock
»-.---1 Xl
XTl
I1PD74HCU04
X2
Note: When the Input Is an extemal clock, the stop mode
cannot be set because the Xl pin Is connected
10 System ground (Vssl.
Open- XT2
Note : For 75PO08. C3 _ 22 pI and C4 _ 33 pI
I3RI).U.WA
4-9
a
NEe
pPD750OX/75P008
Recommended Oscillator Circuit Constants (For 7500x only)
Main system clock
= Crystal; TA = -20 to
+70'C
Frequency
Oscillation Voltage
Manufacturer
Part Number
(MHz)
C1 (Note 1)
(pF)
C2
(pF)
Min (V)
Kinseki
HC-6U
1.0-2.0
20
22
2.7
6.0
HC-18U, HC-431U, HC-491U
2.0-5.0
20
22
2.7
6.0
Max (V)
Notes:
(1) Keep Cl between 15 and 33 pF when adjusting the oscillation
frequency.
Recommended Oscillator Circuit Constants (For 7500x only)
Subsystem clock = Crystal; TA = -10 to +60'C
Oscillation Voltage
Manufacturer
Part Number
(MHz)
C3 (Note 1)
(pF)
C4
(pF)
Min (V)
Max (V)
Kinseki
P-3
32.768
18
18
2.7
6.0
Frequency
Notes:
(1) Keep C3 between 10 and 33 pF when adjusting the oscillation
frequency,
DC Characteristics
"PD750Ox: TA = -40 to +85'C, Voo = 2.7 to 6.0 V
"PD75P008: TA = -10 to +70'C, Voo = 4.5 to 5.5 V
Parameter
Symbol
Max
Unit
High-level input voltage
VIH1
O· 7Voo
Voo
V
Ports 2, 3, 8
VIH2
0.8Voo
Voo
V
Ports 0, 1, 6, 7, and RESET
VIH3
O· 7Voo
Voo
V
Ports 4 and 5; built-in pull-up resistor
O·7Voo
10
V
Ports 4 and 5 with open drain
Low-level input voltage
High-level output voltage
Low-level output voltage
Typ
Voo-0.5
Voo
V
Xl,X2, XTl
VIL1
0
0.3Voo
V
Ports 2, 3, 4, 5, 8
VIL2
0
0.2Voo
V
Ports 0, 1, 6, 7; RESET
VIL3
0
0.4
V
Xl, X2, XTl
VOH1
(Note 1)
Voo-l.0
V
Ports 0, 2, 3, 6, 7, 8; IOH = -1 rnA
VOH2
(Note 2)
Vo o-0.5
V
Ports 0, 2, 3, 6, 7, 8; Voo
IOH = -100 !LA
Ports 4 and 5; (Note 1); IOL = 15 rnA;
VOL1
= 2.7 to 6.0 V;
0.4
2.0
V
0.6
2.0
V
Port 3; (Note 1); IOL = 15 rnA
0.4
V
Ports 0, 2-8; (Note 1); IOL = 1.6 rnA
0.5
(Note 2)
V
Ports 0, 2-8; Voo
0.2Voo
(Note 1)
V
SBQ, 1 open drain; pull-up resistance." 1kG
0.2Voo
(Note 2)
V
580, 1 open drain; Voo = 2.7 to 6.0 V;
pull-up resistance." 5kll
= 4.5 to 6.0 V;
IOL = 400 !LA
ILIH1
3
All except Xl , X2, and XT1; VIN = Voo
/loA
--~---------------------------------------------------------------20
Xl, X2, and XT1; VIN = Voo
/loA
IUH2
20
4-10
Conditions
VIH4
VOL2
High-level input leakage current
Min
!LA
Ports 4, 5 with open drain; VIN
= 10 V
NEe
pPD750Ox/75POO8
DC Characteristics (cant)
Parameter
Symbol
Max
Unit
low-level input leakage current
IUL 1
-3
p.A
All except Xt, X2, andXTt; VIN = 0 V
IUL2
-20
p.A
Xl, X2, and XT1; VIN = 0 V
lLOHl
3
p.A
High-level output leakage
current
Min
Typ
Conditions
All except ports 4 and 5 with open drain;
= Voo
Your
Your = 10 V
lLOH2
20
p.A
Ports 4 and 5 with open drain;
low-level output leakage
current
ILOL
-3
p.A
Your
Built-in pull-up resistor
RL1
80
kG
Ports 0-3, 6-8 (except POol; VIN
Voo = 5.0 V ± 10%
= 0 V;
300
(Note 2)
kG
Ports 0-3, 6-8 (except POo); VIN
Voo = 3.0 V ±10%
= 0 V;
70
kG
Ports 4, 5; Your = Voo -2.0 V;
Voo = 5.0 V ± 10%
60
kG
Ports 4, 5; VO UT = Voo -2.0 V;
\'bo = 3.0 V ± 10%
15
40
30
(Note 2)
RL2
(Note 2)
15
40
10
Supply current
(Note 3)
IDOl
(Note 2)
2.5
8.0
mA
Voo
(Note 2)
0.35
1.2
mA
Voo
(Note 8)
1004
= 5.0 V ±
= 3.0 V ±
10% (Notes 4, 7)
5
15
mA
Voo = 5 V ±10%; (Notes 4, 6)
1500
p.A
HALT mode; Voo = 5 V ± 10% (Note 4)
(Note 2)
150
450
p.A
HALT mode; Voo
(Notes
2,5)
30
90
p.A
Voo = 3 V ± 10%
(Notes
5,8)
350
1000
p.A
Voo = 5V ±10%
(Notes
2,5)
5
15
p.A
(Notes
5,8)
35
100
=3V
± 10%
HALT mode; Voo
=3V
± 10%
p.A
HALT mode Voo
=5V
±10%
0.5
20
p.A
STOP mode; XTl
(Note 2)
0.1
10
p.A
STOP mode; XTI
(Note 2)
0.1
5
p.A
STOP mode; XTI
TA = 25'C
1005
II
10% (Notes 4, 6)
500
1002
1003
= OV
= 0 V; Voo = 5.0 V ±
= 0 V; Voo = 3.0 V ±
= 0 V; Voo = 3.0 V ±
10%
10%
10%;
Notes:
(1) Voo
= 4.5 to 6.0 V for 7500x and Voo = 4.5 to 5.5 V for 75P008.
(2) For 7500x only.
(3) Does not include pull-up resistor current.
(4) 4.19 MHz crystal oscillator; Cl
= C2 = 22 pF.
(5) 32.768 kHz crystal oscillator.
(6) When operated in the high-speed mode with the processor clock
control register (PCC) set to 0011.
(7) When operated in the low-speed mode with the PCC set to 0000.
(8) For 75P008 only.
4-11
NEe
pPD7500x/75P008
DC Characteristics
100 vs VOO (Crystal Oscillator at 4.19 MHz)
loovs Voo (Ceramic Oscillator at 4.19 MHz)
I=TA 25"C
I=TA
Main System Clock
5000
Hlgh·speed mode ......
PCC"()011
1000
13
Q.
~
I
Main System bOCk
f--
l~
C
~
:>
>-
Q.
Cl.
50
~
/
V
:>
'"
~
V
Operation mode;"
*
0..
100
=
I
=HALT mode
/
I
V
*
5
*
- * Meln system clock In STOP mode.
I I I I I
1
o
2
3
4
5
Power Supply Voltage VOO (V)
f---
1
6
7
./
./
0..
HALT mode
./
Operation mode'"
10
-
Subsystem Cock
50
~
./
./
V '"
ci!
10
5
mode
PCC=0010'" . /
,---LJ,.speed 1m ode /
PCC=Oooo
:>
U
>-
U
f - Middle-speed
f-
_0
./
100
500
~0
Subsystem C ock
HALT \node/
HALT mod
I
I
*
* Meln system clock In STOP mode.
I
o
I
I
I
I
2
3
4
5
Power Supply Voltage VOO (V)
Note: Values of 100 are about 10%
larger using a ceramic oscillator
as compared to a crystal oscillator.
4-12
~
1000
/'
Low·speed mode /
PCC=OOOO
~
Hlgh·speed mode ...-:::
PCC"()011 ".,
............
Mlddle.speed
PCC=0010
V
0
_0
~
.,.....
.......
500
~
c
I
m~e V
25'C
5000
6
7
t-{EC
pPD750Ox/75P008
DC Characteristics (cont)
100 va Voo (Ceramic Oscillator at 2.00 MHz)
100 va fxx (VOO = 5 V)
3
f:TA=25"C
~:
TA=25°C
Main Syatem Clock
5000
Hlgh·speed mode ,.. i-"'"'
V
.PCC..oo
I .
1000
I~
~
8:
PCC..oo:/
~
/"
pcc..oooo
./'
100
50
./
./
"
tJ)
J
./
Operation mode.l
Mlddl&-speed mode-
/
PCC=0010
/'
!-OW-speed rnocl~
~O_
HALT mod
*
••. aln Systen! Clock-
I
r---* Main SY1tam ciCCI In STar mode.
1
o
II
/. "
/"
/
/'
V
10
r--
/
./
*
V
l/
L.
Subsystem C ock
HAlTlnooe/
5
High-speed mode
2
~
-
PCC-0010
r - - Low-speed /node
c
~
~ I-
.
/'
500
~
.£l
E
F= Mlddl&-speed mode
i-"'"'
2
3
4
5
6
o
7
HAlTm~e
I
o
2
3
4
5
. Ixx (MHz)
Power Supply VollBg8 VOO (V)
100 va fxx (VOO =3 V)
II
~
0.5
r----r----r----r---...,..--...,
0.3
I---If--:""'-I---t---t---I
0.2
I----+----::,p..",.e:.==--t----t----\
0.1
I----+---+_-
l
_8
o
2
3
4
5
Ixx (MHz)
4-13
pPD750Ox/75P008
DC Characteristics (cont)
IOL ysvOL (Ports 0,2,6,7)
IOL vs VOL (Ports 4, 5)
40
40
I'--TA J5'C .
I---TA='25'C
30
VOO=6V
30 Voo= 6
voo=tv-
1--' '-nVoo=5V
I
/
10
I
II
rl
II /
VOO=3V
::...J
/'
---
/
~
10
-VOO =2.7V
1/
'I
'II
Jr
I'
II
I
4-14
Voo =3V
L---
I /"
II
VOO =2.7V
//
o
~VOO=4V
I
V
I
II /
I /
I /
11
III
11/
V VOO=5V
2
3
4
5
o
2
3
4
5
NEe
pPD7500X/75P008
DC Characteristics (cont)
IOL VB VOL (Port 3)
40...---.---.----.---.----,
15
Z
Z VOO =5V
I---VOO=6V
I
II
/
fJ /
II
l
1/
/II V _
~
_
11/
VOO =2.7V
""
5
~
2
3
II
11 II
!
0
VOO=4V
ll1L
VOO=3V
/"'"
'II
'II
~
I/"
J
10
~
II I
I
'1I
Vol>· VOH
- TA J50 C
VOO=6/~OO~VVOO=4V---t----t
I
VB
20
I--TA=1 250C-+---+--t----1
30
IOH
4
5
,
I~
o
.' VOO=3V
VOO =2.7V
fJl//
r!L
2
3
4
5
VOL (V)
4-15
NEe
pPD750Ox/75P008
AC Characteristics
"PD7500x: TA = -40 to +85'C. voo = 2.7 to 6.0 V
"PD75P008: TA = -10 to + 70'C. voo = 4.5 to 5.5 V
Parameter
Symbol
Min
Cycle time
(Note 1)
tCY
0.95
TIO input frequency
RESET low-level width
Unit
64
lIS
Conditions
Main system clock (Note 2)
3.8
(Note 3)
64
"s
Main system clock; Voo
122
125
"s
Subsystem clock
(Note 3)
275
0
0.48
1.8
Interrupt inputs
low- and high-level width
Max
114
0
TIO input low- and high-level width
Typ
(Note 3)
MHz
(Note 2)
kHz
Voo
= 2.7 to 6.0 V
= 2.7 to 6.0 V
"s
(Note 2)
= 2.7 to 6.0 V
lIS
Voo
(Note 4)
lIS
INTO
10
"s
INT1. INT2. INT4
10
"s
KRO-KR7
10
"s
Notes:
(1) Cycle time (minimum instruction execution time) is determined
by the frequency of the oscillator connected to the microcomputer. system .clock control register (SCC). and the processor
clock cont rol (PC C).
(2) Voo = 4.5 to 6.0 V for 7500x and Voo = 4.5 to 5.5 V for 75POO8.
(3) For 7500x only.
4-16
(4)
2tcy or
128/fx. depending on the setting of the interrupt mode
register QMO).
NEe
"PD750Ox/75P008
Figure 3. Guaranteed Operating Range
IlPD7500X
IlPD75P008
70
64
~~~
~~
~:::
~:::
~
.&
~
~:::
··III
6
5
~g
'·::1:1
.iEr .....
4
'}:J}}H
3
\It\1
2
II
III
1
F'"I
I--I--t--t--~~i----I!
05
o
g
234567
Power Supply VoIlag8 VDO (V)
0.5
o
2
3
5
6
I
7
Power Supply Voltage Voo (V)
4-17
NEe
pPD750Ox/75P008
Serial Transfer Operation
2-line/3-line Serial I/O mode (SCi<. .. internal clock output)
/tPD7500x: TA = -40 to +85"C, Voo = 2.7 to 6.0 V
I'PD75P008: TA = -10 to +70"C, voo = 4.5 to 5.5 V
Parameter
Symbol
SCi< cycle time
SCi< low- and
SI vs.
SI vs.
SCi< i
SCi< i
Min
Typ
Max
1600
ns
3800
(Note 2)
0.5tKCy-150
(Note 2)
ns
high-level width
setup time
tSIK1
hold time
SCK t - SO output delay time
(Note 3)
Unit
150
Conditions
(Note 1)
. Voo =2.7 to 6.0 V
ns
(Note 1)
ns
Voo= 2.7 to 6.0 V
ns
400
ns
tKS01
(Note 2)
250
ns
(Note 1)
1000
ns
Voo= 2.7 to 6.0 V
Serial Transfer Operation
2-line/3-line Serial I/O mode (SCR... external clock output)
/tPD7500x: TA = -40 to +85"C, Voo = 2.7 to 6.0 V
I'PD75P008: TA = -10 to +70"C, Voo = 4.5 to 5.5 V
Parameter
Symbol
Min
SCi< cycle time
tKCY2
800
3200
SCi< low- and high-level width
tKL2, iKH2
SCi< i setup time
SCi< i hold time
SCi< ~ - SO output delay time
SI vs.
tSIK2
100
tKSI2
400
(Note 2)
(Note 2)
Notes:
(1) Voo = 4.5 to 6.0 V for 7500x and Voo = 4.5 to 5.5 V for 75P008.
(2) For 7500x only.
(3) The rising edge of the output delay time must be less than 600 ns.
For example, if SBO and SB1 are pulled up with 5 kll resistors, the
total capacitance of the serial bus line must be no greater than
120 pF.
Unit
Conditions
ns
(Note 1)
ns
Voo= 2.7 to 6.0 V
ns
(Note 1)
ns
Voo = 2.7 to 6.0 V
ns
ns
tKS02
(Note 3)
4-18
Max
400
1600
SI vs.
Typ
(Note 2)
300
ns
(Note 1)
1000
ns
Voo = 2.7 to 6.0 V
NEe
pPD750Ox/75POO8
SBI Mode
S'CR. .. lnternal clock output (master)
~PD75OOx: TA
= -40 to +85"C. Voo = 2.7 to 6.0 V
= -10 to +70"C. Voo = 4.5 to 5.5 V
~PD75P008: TA
Parameter
Symbol
S'OR cycle time
ft*
Data Memory
(RAM)
512 x 4 Bits
SVSBI/P0 3
(1024
P6a-P63
x 4 Bits) *
SOISBO/P02
P70-P73
SCKlPOI
P80-P83
INTO/PIO
INTI/PI I
PIOO-PIOs
INT2IPI2
INT4IPOo
KRO-KR3/
PSo-P6a
KR4-KR7/Q'--_ _--'
P70-P73
P110-P113
fXl2N
AVDD
System Clock
AVREF+
AVREFAVSS
AID
Converter
Clock
Output
Control
Clock
Generator
Stand By
Control
Divider
CPU Clocks
ANO-AN3/
1 1 1 1
PI 10-PI 13
AN4-AN7
PCUP22
XTI XT2
XI
X2
VDD
VSS
RESET IC (Vpp)
MAFVPIOo
MAI/PIOI
MAZlPI02
MAT/ PI03
PPO/P2 1
Multifunction
Timer
*Applies to I'PD75P036
83RD-6563B
4-32
t-IEC
pPD75028/75P036
Specifications
ROM
8064 bytes (GPD75028)
Tlmer!Counter
Three timers. These Include an 8-blt
timer/event Counter, an 8-bIt basic
Interval timer, and a clock timet
Multifunction timer
Thle can be used as an 8-bIt timer/
event couflter, PWM output, 16-bIt
free-runnlng timer; or 16-blt counter for
an Integrating AID converter.
Serial Interface
NEC standard aerial bus Interface
(SBI)
External Interrupt.
Threa vector IntiirrllPts. one test Input.
Internal Interrupts
Four vector InterruPts, one test Input.
16256 bytes (GPD7l5P036j
RAM
512 x 4 bits (GPD75028)
1024 x 4 bits (GPD75P036j
General-purpose registers
4 bits x8 or8 bltsx4
Instruction cycle
0.95 111/1.91 l1li15.3 fl8 (with main
system clock operating at 4.19 MHz)
122 fl8 (with subsystem clock
operating at 32 kHz)
VO ports
AID converter
48 total lines. There are 12 N-channel
open-drain VO ports, each tolerating
as much as 10 volt•• Pull-up realstor
mask-option I. available In the
JlPD75028 only. The remaining 36 lines
are standard CMOS, Including 12
Input ports and 24 I/O port•• 01 theee,
Z1 have aoftwarHSlectabie pullup
resl.tors, and four have .oftwa....
selectable pulldown resl.tors.
8-blt x 8-channel
Low voltage operation p0881 ble
(Voo .. 2.7 to 6.0 V)
Clock serial Interface
BIt sequential buffer
Clock output
(PC~
16-blt, on-chlp
CPU clock "': 524 kHz, 262 kHz, 65.6
kHz (with main system clock operating
at 4.19 MHz)
Buzzer output (BU2)
2 kHz, 4 kHz, 32 kHz (with subsystem
clock operating at 32.768 kHz)
Package
64-pln plastic shrink DIP (750 ml~
64-pln plastic QFP (14 x 14 mm)
Operating voltage
Voo .. 2.7 to 6.0 V
4<-33
II
pPD7S028nSP036
4-34
NEe
t-IEC
NEG Electronics Inc.
pPD75048/75P056
General·Purpose 4·Bit Microcomputers
With EEPROM and AID Converter
Description
The pPD75048 is a single-chip CMOS microcomputer
containing CPU, ROM, EEPROM, RAM, I/O ports, several timer/counters, AID converter, vectored interrupts,
subsystem clock, and serial interface.
The instruction set allows the user to manipulate RAM
data and I/O ports in 1-, 4-, and 8-bit units. The devices
are ideally suited for controlling devices which require
EEPROM, such as meters requiring individual calibration.
Features
o 103 instructions
- Bit manipulation
-4-bit and 8-bit transfer
- GET! instruction, to convert one 2-byte or two
1-byte instructions into a single 1-byte
instruction
-1-byte relative branch instruction
o Fast execution time (@ 4.19 MHz)
- High-speed cycle: 0.95 ps
- Lower-voltage cycles: 1.91 and 15.3 ps
o 8064 bytes of program ROM: pPD75048
o 16256 bytes of program ROM: pPD75P056
o 1024 x 4 bits of EEPROM
o 512 x 4 bits of RAM
-Allows operation on 1, 4, or 8 bits
o Bit sequential buffer
-16-bit, bit manipulation memory
o Eight 4-bit registers
o Accumulators
-1-bit (CY)
-4-bit (A)
-8-bit (XA)
o 481/0 lines
-12 N-channel open drain; can withstand 10 V
-12 outputs directly drive LEDs
-43 lines can have an on-Chip pullup/pulldown
resistor
o Four timers
- 8-bit basic interval timer
- 8-bit timer/event counter
-14-bit watch timer
-16-bit multifunction timer/event counter which
can be used as an 8-bit timer/event counter,
PWM output, 16-bit free-running tinier, or 16-bit
counter for an integrating AID converter
o AID converter
- 8-channel, 8-bit
o Four zero cross detection pins
o 8-bit serial interface
-SBI mode
- 2- or 3-wire mode: data transfer can be full
duplex or receive only, and can be MSB or LSB
first
o Vectored interrupts
- Three external interrupts
- Four internal interrupts
- Nine inputs which each generate one interrupt
request
o Standby modes
- HALT mode: stops CPU only
- STOP mode: stops main clock generator
o Operates with oscillator or ceramic resonator
o OTP version: pPD75P056
o CMOS operation, with VDD from 2.7 to 6.0 V
Ordering Information
Part Number
Package Type
/lPD75048CW-xxx
64-pln plastic SDIP
Mask ROM
/lPD75048GC-xxx-AB8
64-pin plastic QFP
Mask ROM
/lPD75P056CW*
64-pin plastic SDIP
OTP
/lPD75P056GC-AB8*
64-pin plastic QFP
OTP
ROM
*Under Development
o One external event input
50202
4-35
II
NEe
pP1)7S048/75P056,
Pin Configurations
64-Pin SDIP"
.
SB1/sIIPOS
SBO/SOIP02
SCKtP01
Vss
P30
P31
1>:12
P33
P40
P41
P42
P43
P50
P51
P52
INT4IPOo
BUZlP2a
PCUP22.
PPO/P21
PrOolP20
MAT/P1Oa
MAZlP102
MAI/P10 l
MARlP100
RESET
X1
P53
P6oJKRO
P611KR1
X2
10 (Vpp)
XT1
XT2
P7o!KR4
"00
P711KRS
P6~R2
P6a1KR3
P7~R8
A"oO
AVREF+
AVREF_
AN7
P7a1K R7
P80
P81
ANa
ANS
P82
AN4
P90
AN3IP113
1'91
AN2IP112
AN11P111
ANOIP110
AVss
P92
TIOIP13
PBs
P93
...._ - _.......
P10/INTO
P11/INT1
P12/INT2
10: Should be Connected toVOO. Used !IS Vpp program pin In I'P075P058
,
4-36
I3RIJ.eI2OA
NEe
IIPD75048/75P056
64-PinQFP
P4a
P90
P42
P91
P41
P92
P40
P9s
PlotlNTO
P:J:j
P~
Pll'INTl
pSI
PI2'INT2
P30
vss
P1slTlO
SB1ISVP0:3
AVSS
ANO/P110
SBOISOIP02
ANIIPlll
SCKlPOl
INT4IPOO
AN2IPI12
BUZlP2S
PCUP22
AN4
PPOIP21
AN6
AN3IPllS
II
AN5
IC: Should be connected to VOO" Used as VPP programming pin In I'P075P056
83RD-6621B
4-37
NEe
pPD75048/75P056
Pin Identification
Symbol
Function
Symbol
Function
POoIINT4
Port 0 input; interrupt 4
Ie (Vpp)
Internally connected
(Programming voltage for "PD75P056)
X1,X2
Main clock inputs
XT1, XT2
Subsystem clock inputs
Port 0 input; serial clock
Port 0 input; serial out; serial interface
P0:JISI/SB1
Port 0 input; serial in; serial interface
P1of1NTO
Port 1 input; interrupt 0
Reset input
Port 1 input; interrupt 1
Voo
Positive power supply
P12f1NT2
Port 1 input; interrupt,2
Vss
Ground
P1:J1TI0
Port 1 input; timer 0 input
P201PTOO
Port 2 I/O; timer/event counter output
PIN FUNCTIONS
Port 2 I/O; multifunction timer output
POo/INT4, P01/SCK, P02/S0/SBO, POa/SI/SB1
Port 2 I/O; clock output
These pins can be used as 4-bit input port o. Or, POo can
also be used for vectored interrupt 4, which interrupts on
either the leading edge or the trailing edge of the signal.
P0 1-P03 may also be used for the serial interface in the
S81 or 2- or 3-wire mode. SI is the serial input, SO is the
serial output, and SCK is the serial clock. Reset causes
these pins to default to the port 0 input mode.
P2:J1BUZ
Port 2 I/O; buzzer output
Port 31/0
Port 4 I/O
Port 5 I/O
P601KRO
Port 6 I/O; key scan input 0
Port 6 I/O; key scan input 1
Port 6 I/O; key scan input 2
P~:JIKR3
Port 6 I/O; key scan input 3
P701KR4
Port 7 I/O; key scan input 4
Port 9 I/O
These pins .can be used as 4-bit input port 1. Or, P10 and
P11 can also be used for edge-triggered interrupts INTO
and INT1. P12 can be used for INT2, whic'h is also an
edge-triggered input, but one which generates an interrupt request and does not cause an interrupt. P13 can be
used as an input clock to the timer/event counter to
count external events. Reset causes these pins to default to the port 1 input mode.
Port 10 I/O; multifunction timer/event counter
output
P2o/PTOO, P21/PPO, P22/PCL, P23/BUZ
Port 7 I/O; key scan input 5
Port 7 I/O; key scan input 6
P7:J1KR7
Port 7 I/O; key scan input 7
Port 81/0
P100lMAR
Port 10 I/O; multifunction timer/event counter
output
Port 10 I/O; multifunction timer/event counter
output
P10:JIMAT
Port 10 I/O; multifunction timer/event counter
input
P1101ANO
Port 11 I/O; AID converter input 0
Port 11 I/O; A/D converter input 1
Port 11 I/O; AID converter input 2
P11:J1AN3
Port 11 I/O; A/D converter input 3
AN4-AN7
AID converter inputs 4-7
AVoo
AID converter positive power supply
AVss
A/D converter ground
AID converter reference voltages
4-38
P101INTO, P11/INT1, P12/INT2, P1afTIO
These pins can be used as 4-bit I/O port 2. When used as
an output, the da:ta is latched. When used as an input
port, the port outputs are three-state. P20 can also be
used as the output of the timer/event counter flip flop
(TOUT); P21 can also be used as the output for the
multifunction timer/event counter T flip flop; P22 can be
used as the output (PCL) of the clock generator; and P23
can be used to output square waves for a buzzer. Reset
causes these pins to default to the port 2 input mode.
P30·P33
These pins are used for I/O port 3. Each bit in this port
can be independently programmed to be either an input
or an output. This port has latched outputs, and can
directly drive LEOs. A reset signal causes this port to
default to the input mode.
NEe
pPD75048/75P056
P40-P43, P50-P53
AVo 0
Port 4 and port 5 are identical 4-bit I/O ports which can
be combined together to function as a single a-bit port.
Latched outputs will directly drive LEOs. Outputs are
N-channel open drain, and can withstand up to 10 volts;
pullup resistor mask options are available for these
ports. A reset signal causes these ports to default to the
input mode.
A/D converter positive power supply.
AVss
A/D converter analog ground.
AVREF+, AVREFA/D converter positive and negative reference voltages.
P60/KRO, P61/KR1, P62/KR2, P6a1KR3
P70/KR4, P71/KR5, P72/KR6, P7a1KR7
Ports. 6 and 7 are 4-bit I/O ports with latched outputs.
Each pin of port 6 can be independently programmed to
be either an input or an output, while port 7 can be
programmed to be either all inputs or all outputs. Alternately, these pins may be used to detect the falling edge
of inputs KRO-KR3 (port 6) and KR4-KR7 (port 7). A reset
signal causes these ports to default to the input mode.
P80-P83, P90-P93
Ports a and 9 are identical 4-bit I/O ports. Outputs are
latched. A reset signal causes these ports to default to
the input mode.
P10olMAR, P101/MAI, P102/MAZ, P10alMAT
These pins are used for I/O Port 10. Outputs are Nchannel open drain which can withstand up to 10 volts.
PlOo-P102 can also be used as the MAR, MAl, and MAZ
outputs from the multifunction timer/event counter's A/D
control logic. P10s can be used as the input MAT to the
multifunction timer/event counter's A/D control logic. A
reset signal causes this port to default to the input mode.
ICNpp
This pin should be connected to Voo when using the
~PD7504a. For the ~PD75P056, this pin is used as the
programming voltage input during the EPROM write/
verify cycles. When the device is not being programmed,
this pin should be connected to Voo.
1[11
X1,X2
These pins are the main system clock inputs. The clock
can be either a ceramic resonator or a crystal; an
external logic signal may also be used.
XT1, XT2
These pins are the subsystem clock inputs. The clock
can be either a ceramic resonator or a crystal; an
external logic signal may also be used.
This is the reset input, and it is active low.
Voo
The system positive power supply pin.
P110/ANO, P111/AN1, P112/AN2, P11a1AN3
These pins are used for I/O Port 11, or can alternately be
used as A/D converter inputs ANO-AN3. A reset signal
causes this port to default to the input mode.
Vss
System ground.
AN4-AN7
A/D converter inputs AN4-AN7.
4-39
1*{EC
pPD7S048nSPOS6
Block Diagram
TI0/P13
PTOO/P20
BUZlP23
P4o-P43
Program
Memory
(ROM)
DaIaMemory
6064 x8Blts
(16256 x 8 Bits)'
(RAM)
512x4BI1s
Decode
and
Control
SVSB1/P03
So/SBO/P02
DaIaMemory
(EEPROM)
SCKlP01
1024 x4 Bits
P70-P73
PBO-P83
INTO/P10
INT1/P11
INT2IP12
INT4IPOO
P100-P103
P11Q-P113
KRO-KR3/
P60-P63
KR4-KR71
P70-P73
AVoo"
AVREF+
AVREFAVSS
ANO-AN3/
P11Q-P113
AN4-AN7
System Clack
Clock
OUtput
Control
Clock
Divider
Generator
1---...----1 S6:c::r
XT1 XT2 X1
X2
CPU Clock 0
t t t t
Voo
VSS RESET IC (Vpp)
'Applies to I'I'075P056
83RD-8S668
4-40
NEe
pPD75048/75P056
Specifications
ROM
8064 bytes (j4PD75048)
16256 bytes (j4PD75P056)
RAM
512 x 4 bits
EEPROM
1024 x 4 bits
General-purpose
registers
4 bits
Instruction cycle
0.95 "s/I.91 "s/15.3 /IS
(with main system clock operating at 4.19 MHz)
48 total lines. There are 12 N-channel opendrain I/O ports, each tolerating as much as 10
volts. (Pullup resistor mask-option Is available
in the "PD75048 only). The remaining 36 lines
are standard CMOS, including 12 input ports
and 24 I/O pons. Of these, 27 have softwareselectable pullup resistors, and four have
software-selectable pulldown resistors.
NO converter
Three. These include an 8-bit timer/event
counter, an 8-bit basic interval timer, and a
clock timer.
This can be used as an 8-bit timer/event
counter, PWM output, 16-bit free-running timer,
or 16-bit counter for an integrating A/D
converter.
NEC standard serial bus interface (SBI)
Clock serial interface
External
interrupts
Three vector interrupts, one test input.
Internal
interrupts
Six vector interrupts, one test input.
Bit sequential
buffer
16-bit, on-chip
Clock output
(PCL)
CPU clock
524 kHz, 262 kHz, 65.6 kHz
(with main system clock operating at 4.19 MHz)
Buzzer output
(BUZ)
2 kHz, 4 kHz, 32 kHz (with subsystem clock
operating at 32.768 kHz)
Package
cp;
64-pin plastic SDIP (750 mil)
64-pin plastic QFP (14 x 14 mm)
8-bit x 8-channel
Low-voltage operation possi ble
(Voo= 2.7 to 6.0 V)
Timer/Counter
Serial interface
x 8 or 8 bits x 4
122"s
(with subsystem clock operating at 32 kHz)
I/O Ports
Multifunction
timer
Operating
voltage
=
Voo
2.7 to 6.0 V
EEPROM target specification
Voo = 2.7 to 6.0 V
4-41
II
pPD75048175P056
'l'
4-42
'.
NEe
!\fEe
pPD751xx/75P1xx
High-End 4-Bit Microcomputers
NEG Electronics Inc.
Description
[J
The J.lPD751XX/P1xx is a family of high-p~r~ormance
single-chip CMOS microcomputers. containing CPU,
ROM, RAM, I/O ports, comparator, interval ti~er: two
timer/counters, vectored interrupts, and a senal Interface.
The instruction set allows the user to manipulate RAM
data and I/O. ports in 1-, 4-, and 8-bit units. The devices
are ideally suited for controlling VCRs, telephones, and
meters.
Both EPROM and OTP versions are available. See ordering information.
Features
[J
[J
[J
[J
[J
136 instructions
- Bit manipulation
- 4-bit and 8-bit transfer, arithmetic, logical,
comparison, and increment/decrement
instructions
- 1-byte relative branch
- GETlinstruction, to convert one 2-byte,
one 3-byte, or two 1-byte instructions into a
single1-byte instruction
Fast execution time
(Main system clock @ 4.19 MHz)
- High-speed cycle: 0.95 J.ls
- Lower-voltage cycles: 1.91 and 15.3 J.ls
Program ROM
-J.lPD75104/104A: 4096 bytes
-J.lPD75106: 6016 bytes
-J.lPD75108/10BA/P108: 8064 bytes
-J.lPD75112: 12160 bytes
-J.lPD75116/P116: 16256 bytes
Data memory (RAM)
-J.lPD75104/104A/106: 320 x 4 bits
- Others: 512 x 4 bits
-Allows operation on 1, 4, or 8 bits
Bit sequential buffer
-16-bit, bit manipulation memory
[J
Four banks of eight 4-bit registers
[J
Accumulators
-1-bit (CY)
-4-bit (A)
-8-bit (XA)
58 I/O lines
-All outputs directly drive LEDs
(Islnk = 15 rnA rms)
-12 N-channel open-drain, can withstand 12V
-441/0 lines
-14 input-only lines
[J
4-input programmable threshold comparator
[J
Three timers
- One 8-bit basic interval timer
- Two 8-bit timer/event counters
[J
8-bit serial interface
- Data transfer can 'be full duplex or receive only,
and can be MSB or LSB first
[J
Vectored interrupts
- Two-level nesting
- Three external interrlJpts
- Four internal interrupts- Two inputs which generate an interrupt request
[J
Standby modes
- HALT mode: stops CPU only
-STOP mode: stops main system clock
[J
Power-on-reset and power-on flag
(always provided with J.lPD75P10B, n.ever on
J.lPD75P116, and available on the others as a mask
option)
[J
Mask option port pull-up resistors
(not available on J.lPD75P108/P116)
[J
Operates with oscillator or ceramic resonator
[J
CMOS operation, with Voo from 2.7 to 6.0 V
[J
Low operating current (@5 V and 4.19 MHz)
- Normal operation: 3.0 rnA typical
- HALT mode: 0.5 rnA typical
- STOP mode: 0.1 J.IA typical
[J
Programmable versions
- OTP & EPROM: J.lPD75P108
- OTP: J.lPD75P116
- OTP, low voltage: J.lPD75P108B (Note)
Note: Low voltage target spec of 2.7 to 6.0 V operation.
Contact your local NEC Sales Office for latest information; none of the electrical specifications in this
data sheet directly apply to this part.
4-43
II
NEe
IIPD751.xx/75P1xx
Ordering Information
Part Number
Package Type
IlPD75104CW-xxx
64-pin plastic SDIP (750 miQ
Mask ROM
IlPD75104G-xxx-l B
= 2.05 mm; pHch = 1.0 mm)
64-pin plastic OFP (resin thickness = 2.7 mm; pitch = 1.0 mm)
64-pin plastic OFP (resin thickness = 2.55 mm; pitch = O.S mm)
Mask ROM
IlPD75104GF-xxx-3BE
IlPD75104AGC-xxx-ABS
ROM
64-pin plastic OFP (resin thickness
Mask ROM
Mask ROM
IlPD75106CW-xxx
64-pin plastic SDIP (750 miQ
Mask ROM
IlPD75106G-xxx-l B
64-pin plastic OFP (resin thickness = 2.05 mm; pHch = 1.0 mm)
Mask ROM
IlPD75106GF-xxx-3BE
64-pin plastic OFP (resin thickness
IlPD7510SCW-xxx
64-pin plastic SDIP (750 miQ
= 2.7 mm; pitch = 1.0 mm)
Mask ROM
Mask ROM
IlPD7510SG-xxx-l B
64-pin plastic OFP (resin thickness = 2.05 mm; pitch = 1.0 mm)
IlPD7510SGF-xxx-3BE
64-pin plastic OFP (resin thickness
IlPD7510SAG-xxx-22
64-pin plastic OFP (resin thickness = 1.5 mm; pitch = O.S mm)
Mask ROM
IlPD7510SAGC-xxx-ABS
64-pin plastic OFP (resin thickness = 2.55 mm; pitch = O.S mm)
Mask ROM
OTP
= 2.7 mm; pitch = 1.0 mm)
IlPD75Pl0SCW
64-pin plastic SDIP (750 miQ
IlPD75Pl0SDW
64-pin shrink CERDIP (wI 350-mil window)
IlPD75Pl0SG-l B
64-pin plastic QFP (resin thickness
= 2.05 mm; pitch = 1.0 mm)
Mask ROM
Mask ROM
EPROM
OTP
IlPD75Pl0SBCW (Note 2)
64-pin plastic SDIP
Low voltage OTP
IlPD75Pl0SBGF-3BE (Note 2)
64-pin plastic OFP
Low voltage OTP
IlPD75112CW-xxx
64-pin plastic SDIP (750 miQ
Mask ROM
IlPD75112GF-xxx-3BE
64-pin plastic OFP (resin thickness = 2.7 mm; pitch = 1.0 mm)
Mask ROM
IlPD75116CW-xxx
64-pin plastic SDIP (750 miQ
Mask ROM
= 2.7 mm; pitch = 1.0 mm)
IlPD75116GF-xxx-3BE
64-pin plastic OFP (resin thickness
IlPD75PI16CW-xxx
64-pin plastic SDIP (750 miQ
OTP
IlPD75PI16GF-xxx-3BE
64-pin plastic OFP (resin thickness = 2.7 mm; pitch = 1.0 mm)
OTP
Notes:
(1) xxx indicates ROM code suffix.
(2) Contact your local NEC .sales office for latest information.
4-44
Mask ROM
NEe
pPD751xx/75P1:xx:
Pin Configurations
64-Pin Plastic SDIP and 64-Pin Ceramic SDIP
w/Window
64-Pin Plastic QFP (All Parts Except
pPD75104A/108Aj
*0:.
P13/INT3
Voo
P12/1NT2
P90
P11/1NT1
P9,
Pl0/INTO
P92
PTH03
P93
PTH02
PBO
PTH01
PB,
PTHOO
PB2
TIO
PB3
TI'
P70
P52
P23
P7,
PSI
P121
P22/PCL
P72
P122
P21JPT01
P73
~
P2o/PTOO
P60
P03/S1
P6,
P02/S0
P62
<>c~ 0
0 0 ;!
> z <>-
P41
P40
PS3
P131
0
P132
P133
P120
RESET
X2
POO/INT4
XI
POl/SCK
P123
P63
P02/SO
P01/SCK
P63
POo/INT4
X,
P123
X2
P122
RESET
P60
P21/PTOI
P121
PSo
P73
P22/PCL
P120
PS,
P72
P23
P133
PS2
P71
TI1
TIO
41
P62
P61
P03/S1
P20/PTOO
P132
PS3
P70
P131
POD
P83
PTHOO
P130
PO,
PTHOI
P143
P02
P8 2
P142
P03
P141
P30 (MOO)
P140
P31 (MD1)
*NC(Vpp)
*
*
P32 (MD2) *
Voo
P33(MD3)*
.....
0(1')(\1_0(1)
coCOCJ)CJ)CJ)cnCl)
c..o.o...c..a..I..>
~~~~~ :I:'"
~~';.~t t
a: a:: c:: a::
0
*Vppand MDO-MD3 are for
* Vpp and MOo-M03 are for
programming the j.l.PD75P10anSP116
programming the IlPD75Pl 08l7SP116
83-007156A
83YL-7157A
4-45
II
ttlEC
IIPD751XX/75P1xx
Pin Configurations (cont)
64-PIn PI••tlc QFP (pPD75104A/108A only)
P8s
~
0
Pal
PlIo
P8s
P9:z
I'9j
PlIo
Vss
jlPD75l04AGC
jlPD75l0SAGIGC
P1311NT3
P12/1NT2
PlllINTl
Pl0llNTO
PTH03
PTH02
PTHOl
&1RD-71(7B
.4-46
NEe
pPD751xx/75P1xx
Block Diagram
TID
PTOO/P20
Til
Program
Memory
PTQ1/P21
~D75104'104A:
SI/P03
SO/PO.
seK/P01
4096 x 8
IlPD751 06: 6016 x 8
IlPD15108f1 OaAlP1 08:
8064 x 8
IlPD75112: 12160x8
j.LPD75116fP116:
RAM
Decode
and
Control
Data Memory
~PD75l04/l04A1106:
320 x 4
Others: 512 x 4
II
16256 x 8
!NTO/P1 0
INT1/P11
INJ2/P1 2
INT3/P1 3
INT4/POo
P130·P133
1 1 1
Voo
Vss
P140·P143
RESET
83-0071558
4-47
NEe
"PD751 XX/75P1 xx
Pin Identification
PIN FUNCTIONS
Symbol
Function
POoIINT4
Port 0 Input; Interrupt 4
Port 0 Input; serial clock
P02I'SO
Port 0 input; serial out
POalSI
Port 0 Input; serial in
Plo1lNTO
Port 1 input; interrupt 0
Port 1 input; Interrupt 1
P121'1NT2
Port 1 Input; Interrupt 3
P20fPTOO
Port 2 110; timer/event counter 0
Port 2 110; timer/event counter 1
Port 2 110; clock output
Port 2110
Port 3 I/O; programming mode select 0
(uPD75Pl08/P116)
Port 3 I/O; programming mode select 1
(uPD75Pl08/P116)
P321'MD2
Port 3 I/O; programming mode select 2
(uPD75Pl08/Pl16)
P3a1MD3
Port 3 110; programming mode select 3
(uPD75Pl08/ Pl16)
P40·P43
Port 4 110
P50·P53
Port 5'1/0
P60·P63
Port 6 I/O
P70·P73
Port 71/0
P80·P83
Port 8 110
P90·P93
Port 91/0
Pl20·P123
Port 12 I/O
P1So·P133
Port 13110
P140·P143
Port 14110
PTHOO·PTH03
4·bit programmable threshold comparator
analog input port
RESET
Reset input
TIO/Tll
Event timer/counter external input
voo
Positive power supply
vss
Ground
Xl,X2
Main clock inputs
NC/Vpp
No connection; programming pin for
jJPD75Pl08/Pl16
4-48
These pins can be used as the 4·bit input port O. POe
can be used for vectored interrupt 4, which interrupts
on either the leading edge or the trailing edge of the
signal. P01·P03 may also be used for the serial interface;
SI is the serial input, SO is the serial output, and SCK is
the serial clock. Reset causes these pins to default to
the Port 0 input mode.
Port 1 Input; Interrupt 2
Pla1INT3
P301MDO
POolINT4, P01/SCK, P02/S0, POaiSI
P101INTO, P11/INT1, P12/INT2, P1a1INT3
These pins can be used as 4·bit input port 1. They can
also be used, respectively, for edge·triggered interrupts
INTO,INT1, INT2, and INT3. INTO and INT1 are triggered
by rising or falling edges, while INT2 and INT3 respond
to rising edges only and generate an interrupt request
but not an interrupt. Reset causes these pins to default
to the Port 1 input mode. Individual pull·up resistors can
be provided by mask option in the JlP075104A/108A.
P2o/PTOO, P21/PT01. P22/PCL, P23
These pins can be used as 4·bit I/O port 2. This port has
latched outputs, and can directly drive LEOs. PTOO and
PT01 are the timer/event counter output pins; PCL is
the clock output pin. Reset causes these pins to default
to the Port 2 input mode.
P301MDO, P31/MD1, P32/MD2, P3a1MD3
These pins are used for I/O Port 3. Each bit in this port
can be independently programmed to be either an input
or an output. This port has latched outputs, and can
directly drive LEOs. PSo·P33 are used as the program·
ming mode select pins for the JlP075P108/P116 during
EPROM/OTP programming and verification. A reset sig·
nal causes this port to default to the input mode.
P40·P43. P50·P53
Port 4 and Port 5 are identical 4-bit I/O ports which can
be combined together to function as a single 8·bit port.
Latched outputs will directly drive LEOs. A reset signal
causes these ports to default to the input mode. Indi·
vidual pull·up resistors are available as a mask option in
the JlPD75104A/108A.
t-IEC
pPD751xx/75P1xx
P60·P63, P7 O·P73
TIO, TI1
Port 6 and Port 7 are 4-bit I/O ports; port 6 is I/O bit
programmable. These ports may be combined together
to function as a single 8-bit port. Latched outputs will
directly drive LEOs. A reset signal causes these ports to
default to the input mode. Individual pull-up resistors
are available as a mask option in the pP075104A/108A
External event input for the timer/event counters. Each
pin can also act as an edge-triggered vectored interrupt
and a i-bit input port.
P80·P93, P90·P93
Port 8 and Port 9 are identical 4-bit I/O ports which can
be combined together to function as a single 8-bit port.
Latched outputs will directly drive LEOs. A reset signal
causes these ports to default to the input mode. Individual pull-up resistors are available as a mask option in
the pP075104A/108A
NCNpp
This pin may be left unconnected when using the
pP0751xx. For the pP075P108/P116, this pin is used as
the programming voltage input during the EPROM
write/verify cycles. When the devices are not being
programmed, this pin should be connected to VDD. Pin
must be connected to VDD if the same circuit board is
used for both programmable and non programmable
devices.
X1,X2
P120·P123, P130·P133
Port 12 and Port 13 are identical 4-bit I/O ports which
can be combined together to function as a single 8-bit
por"t. Latched outputs will directly drive LEOs. Outputs
are N-channel open drain, and can withstand up to 12
volts; pull-up resistor mask options are available for
these ports. A reset signal causes these ports to default
to the input mode.
These pins are the system clock inputs. The clock can
be either a ceramic resonator or a crystal; an external
logic signal may also be used.
This is the reset input, and it is active low.
Voo
P140·P143
Port 14 is a 4-bit I/O port. Latched outputs will directly
drive LEOs. Outputs are N·channel open drain, and can
withstand up to 12 volts; pull-up resistor mask options
are available for this port. A reset signal causes the port
to default to the input mode.
The system positive power supply pin.
Vss
System ground.
PTHOO·PTH03
4-channel comparator with 4-bit resol ution and on-chip
resistor ladder.
Product Comparison
Item
,.PD75104/104A
,.PD75106
"PD75108/108A
,.P075P108
,.P075112
,.P075116
,.P075P116
Program
memory
Mask ROM
OOOH-FFFH
4096 x 8 bits
Mask ROM
OOOH-177FH
6016 x 8 bits
Mask ROM
OOOH-1F7FH
8064 x 8 bits
EPROM/OTP
000H-1FFFH
8192 x 8 bits
Mask ROM
000H-2F7FH
12160 x 8 bits
Mask ROM
OOOH-3F7FH
16256 x 8 bits
OOOH-3FFFH
16384 x 8 bits
Data
memory
320 x 4 bits
Bank 0: 256 x 4
Bank 1: 64 x 4
320 x 4 bits
Bank 0: 256 x 4
Bank 1: 64 x 4
512 x 4 bits
Bank 0: 256 x 4
Bank 1: 256 x 4
512 x 4 bits
Bank 0: 256 x 4
Bank 1: 256 x 4
512 x 4 bits
Bank 0: 256 x 4
Bank 1: 256 x 4
512 x 4 bits
Bank 0: 256 x 4
Bank 1 : 256 x 4
512 x 4 bits
Bank 0: 256 x 4
Bank 1 : 256 x 4
Instruction
set
The BR laddr instruction is not provided in the JlPD751 04/1 04A.
Port lines
CMOS I/O lines: 32
12 open-drain outputs with 12 V breakdown. These outputs can have pull-up resistors as a mask option, except
for programmable parts. (Note 1)
Lines which directly drive LEDs: 44
Total number of lines: 52 (44 I/O and 8 input-only)
OTP
4-49
II
NEe
pPD751xx/15P1xx
Product Comparison
Item
"PD75104l104A
"PD75106
"PD75108/108A
"PD75P.108
"PD75112
"PD75116
"PD75P116
Power-onreset
circuit and
power-on
flag
Mask option
Mask!)ptlon
Mask option
Internally
provided
Mask option
Mask option
Not included
Operating
voltage
range
2.7 to 6.0 V
2,7 to 6.0V
2.7 to 6.0 V
5V ± 10%
2.7 to 6.0 V
2.7 to 6.0 V
5V± 10%
Package,
See ordering Information f9r a complete list of packages
Note.:
(1) The IIPD75104/104A have 24 additional VO port lines and 4 more
Input-only lines with mask option programmable pul~up resistors.
ADDRESS SPACES AND MEMORY MAPS
OOOOH to 0001 H:
The 75X architecture has two separate address spaces,
one for program memory (ROM), and another for data
memory (RAM).
Program Memory (ROM)
The ROM is addressed by the program counter. The size
of the program counter is 12, 13, or 14 bits; its size
depends on which member of the family is being used,
as does the amount of ROM present. The ROM contains
program object code,interriJpt vector table, a GETI
instruction reference table, and table data. Table data
can be obtained using the table reference instruction,
MOVT.
Figure 1 shows the addressing range which can be
made using a branch instruction or subroutine call
instruction. In addition, the BR PCDE and BR PCXA
instructions can be used for a branch where only the
low 8 bits of the PC are changed. The program memory
addresses are,
pPD75104/104A: OOOH to FFFH
pPD75106: OOOOHto 1nFH
pPD75108/108A: OOOOH to 1F7FH
pPD75P108: OOOOH to 1FFFH .
pPD75112: OOOOH to 2F7FH
pPD75116: OQooH to 3F7FH
IlPD75P116: OoaOH to 3FFFH
All locations of ROM except OOOH and 0001 H can be
used as program memory. However, if interrupts or
GETI instructions are used, the locations corresponding to those functions cannot be used. Addresses are
normally reserved as follows:
4-50
002H to oaOBH:
0020H to 007FH:
This address area contains the
program start address when a
RESET is applied, and Is also used
for setting the values of RBE and
MBE. Program execution can be
started from any address after a
RESET.
This area is used for interrupt vector
addresses and for setting the value
of RBE and MBE. Interrupts can
start from any location except
where noted.
This is the table area for GETI
instructions~ The GETl instruction
is used to access 1, 2 or 3-byte
instructions using one byte of
program memory. This is useful in
compacting code.
Program Counter (PC)
This is a 12/13/14-bit binary counter that contains the
address of the current program memory location. The
IlP075104/104A contain a 12-bit PC, the IlPD75106/108/
108A/P108 have a 13-bit PC, and theIlPD75112/116/P116
have a 14-bit PC.
When an instruction is executed, the PC is automatically incremented by the n\.lmber of bytes of the current
instruction. When a branch instruction (BR, BRCB) is
executed, the contents of the immediate data or register pair indicating the new address are loaded into some
or all the bits of the PO. When a subroutine call instruction (CALL, CALLF) is executed or an interrupt is
generated, the PC is incremented to point to the next
instruction, and this information is saved on the stack.
During an interrupt, the program s~atus word (PSW) is
NEe
also automatically saved on the stack. The address to
be jumped to by the CALL or interrupt is then loaded
into the PC.
When a return instruction (RET, RETS, or RETI) is
executed, the contents of the stack are restored to the
PC.
Data Memory (RAM)
The data memory contains three memory banks, 0, 1,
and 15. The RAM memory map is shown in figure 2. The·
memory consists of general purpose static RAM, general purpose registers, and peripheral control registers.
Memory banks are accessed by using the MBE (memory
bank enable) bit and by programming the BS (bank
select) register. If MBE = 0, the lower 128 nibbles of
memory bank 0 and the upper 128 nibbles of memory
bank 15 are accessed. If MBE = 1, the upper four bits in
the BS register will specify the memory bank. The values
are OH for memory bank 0, 1H for memory bank 1, and
FH for memory bank 15. Memory bank 0 contains 256
nibbles, while memory bank 1 contains either 64 or 256
nibbles depending on which member of the JiPD751XX/
P1XX family is being used. Although the memory is
organized in nibbles, the 75X architecture allows the
data to be manipulated in bytes, nibbles and individual
bits.
.
The data memory is used for storing processed data,
general purpose registers, and as a stack for subroutine
or interrupt service. Because of its static nature, the
RAM will retain its data when the chip is in the STOP
mode, provided VDD is at least 2 volts.
The on-chip peripheral control registers and ports reside in the upper 128 nibbles of bank 15. Bank 15
addresses which are not assigned to a register are not
available as random memory except for the is-bit sequential buffer. Also, the lower 128 nibbles of bank 15 do
not contain RAM.
There are four general-purpose register banks in RAM
BankO, beginning at address OOH. Each bank contains
eight 4-bit registers, (B, C, D, E, H, L, X, A), which may
be used together to form four 8-bit registers. Register
bank selection is accomplished by using the two loworder bits of the BS register and the RBE (register bank
enable) bit. A register bank is selected by setting RBE to
1 and programming BS to be OH-3H for register banks
0-3, respectively. If RBE = 0, the chip defaults to bank O.
Registers which are not used for any other purpose may
be used as general purpose RAM.
pPD751xxJ75P1xx
Each register can be used either in a 4-bit configuration
or in a 8-bit configuration when paired with one of the
others (BC, DE, HL, XA). There is also a "DL.:' pair
available. DL and pairs DE and HL can be used as data
pointers. For 8-bit manipulation, besides BC, DE, HL,
and XA, register pairs BC', DE', HL', and XA' are provided. If memory bank 0 is selected and BC' is referenced, BC' is register BC in memory bank 1. If bank 1 is
selected and BC' is referenced, BC' is register BC in
bank O.The same concept is true for register banks 2
and3
Figure 1. Program Memory Map
Address
OOOOH
7
6
I I
o
M BE RBE Internal reset start address
(high order six bits)
II
cJlF
l!addr
instruction
entry
MBE I RBE IINTBT/INT4 start address
(high order six bits)
address
Internal reset start address
(low order eight bits)
0002H
INTBT/INT4 start address
(low order eight bits)
0004H
BRCB
I caddr
instruction
branch
address
MBEI RBE IINTO/INT1 start address
(high order six bits)
INTO/INT1 start address
(low order eight bits)
0006H
MBEI RBEI
INTSIO start address
(high order six bits)
INTSIO start address
(low order eight bits)
OOOBH
MBEI RBEI
CAll
!addr
instruction
subroutine
entry
address
INTTO start address
(high order six bits)
INITO start address
(low order eight bits)
OOOAH
MBEIRBEI
I
BR !caddr
instruction
branch
address
INTT1 start address
(high order six bits)
INTT1 start address
(low order eight bits)
0002H
007FH
OOBOH
07FFH'f
OBOOHJ:
I
BR$addr
instruction
relative
branch
address
GETI instruction reference table
'f_
1;L
Subroutine
entry and
1
·branch
;L
address
by
GETI
1__-+- instruction
J,
1__+
J,
1 __-,---,,---,-
OFFFH' f t - - - - - - - - - - - - 1
100~J:
'f
2FFFHl'
3000HJ,
3F7FHl'
1FFFH
2000H~
49NR-724A
4-5.1
t\'EC
pPD751xx/75P1xx
Figure 2.
~
I 01FH
Data Memory Map fpPD75104/104A/106}
11purpose
General
registers
32x4
Data Memory
-----
Stack
area
224 x 4
1
I
Bank 1
Not
Internally
!
Bank 15
128 x 4
~
.f
h:~:~:;::~a
32x4
----~!~---
'T>~
I
Bank 1
L
~
Bank 15
~
H Register
004H
E Register
005H
D Register
006H
C Register
007H
B Register
I
I
I
I
017H
I
I
I
I
01FH
General
purpose registers
----
1
j
i
Same as the bank O.
Register bank 1
Same as the bank O.
Register bank 2
Same as the bank O.
Register bank 3
~
t
~
t
~
Stack
area
224x4
3
0
B
1
D
General purpose
static RAM
512x4
256x4
!
Not
Internally
r
H
perJheral
128 x 4
hardware area
C
3
~,
3
0
E
!5>
L
H
1
i'::>"
"'"
0
3
X
DPrOVided
3
H
0
3
A
83RO-7146A
----~!~--49NR·726A
4-52
L Register
003H
018H
II
BankO
X Register
002H
010H
Figure 28. Data Memory Map
fpPD75108 to pPD75116}
-
001H
I
I
I
I
OOFH
49NR-723A
~
I 01FH
A Register
008H
I
~DprOVided
OOOH
Register bank 0
General purpose
static RAM
320 x4
64 x4
L
o
ADDRESS 3
BankO
'T,,"
Figure 3. General Purpose Register
Configurations
t-IEC
pPD751xx/75P1xx
Addressing Modes
The pPD751xx/P1xx is able to address data memory and
ports as individual bits, nibbles, or bytes. The addressing modes are as follows:
1-bit direct data memory
4-bit direct data memory
Table 1.
4-bit register indirect (@rpa)
8-bit direct data memory
8-bit register indirect (@HL)
See table 1 for data memory addressing and table 2 for
peripheral control register addressing.
Data Memory Addressing Modes
Addressing Mode
Representation Format
How the Address Is Created
I-bit direct addressing
mem.bit
If MBE = 0, the memory bank is Bank 0 for addresses 00H-7FH, and Bank 15
for addresses 80H-F FH.
If MBE = 1, the memory bank is selected by the four bits of the MBS.
The bit to be manipulated is specified inmem.bit
4-bit direct addressing
mem
If MBE = 0, the. memory bank Is Bank 0 for addresses 00H-7FH, and Bank 15
for addresses 80H-F FH.
If MBE = 1, the memory bank is selected by the four bits of the MBS.
The bit to be manipulated is specified in memo
8-bit direct addressing
mem (must be an even address)
If MBE = 0, the memory bank is Bank 0 for addresses 00H-7FH, and Bank 15
for addresses 80H-F FH.
If MBE = 1, the memory bank is selected by the four bits of the MBS.
The bit to be manipulated is specified in memo
@HL, @HL+, @HL-
The memory bank is sele~ted by the four bits of the MBS, and the location
within the memory bank is contained in register HL
@HL+ : After addressing the L register automatically increments.
@HL-: After addressing, the L register automatically decrements.
@DE
The memory bank is always Bank 0, and the location within the memory bank is
contained in register DE
@DL
The memory bank is alwaYs Bank 0, and the location within the memory bank is
contained in register D L
8-bit register Indirect
addressing
@HL (must be an even address)
The memory bank is selected by the four bits of the MBS, and the location
within the memory bank is contained in register HL.
Bit manipulation
addressing
fmem.bit
The memory bank is Bank 15, and the location is fmem, where
fmem = FBOH- FBFH for interrupts
fmem = FFOH-FFFH
ports
The actual bit is specified in fmem.bit
4-bit register indirect
addressing
va
pmem.@L
(where pmem= FCOH to FFFH)
The memory location is independent of MBE and MBS. The upper 10 address
bits of the location are contained in the ten high order bits of pmem and the two
lower address bits are contained in the two upper bits of register L
The bit to be manipulated is specified by the two LSBs of register L
@H+ mem.bit
The memory bank is selected by the four bits of the MBS, and the location is
determined by the following:
The four upper bits are the contents of register H
The four lower bits are memo
The actual bit is specified in mem.bit.
Stack addressing
The memory bank is always Bank 0, and the location is indicated by the stack
pointer (SP)
MBE: memory bank enable bit
MB: memory bank
MBS: memory bank select register
mem: a location within a memory bank
mem.bit: a bit at a specified memory location.
fmem and pmem are specialized cases of memo
4-53
II
t-IEC
pPD751XX/75P1xx
Table 2. Addressing Modes During Peripheral Hardware Operation
Manipulation
Addressing Mode
Applicable Hardware
l-bit
With MBE = 0 (or MBE = 1 and MBS = 15) direct addressing
(address in mem.bit)
All hardware where bit manipulation can be
performed
.Direct addressing regardless of how MBE and MBS are set.
(address in fmem.bit)
ISTO, ISn, MBE, RBE
IExxx, IRQxxx, PORTn (n= 0 to 3)
Indirect addressing regardless of how MBE and MBS are set.
(address in pmem. @L)
BSBn.x
PORTn
With MBE = 0 (or MBE = 1 and MBS = 15) direct addressing
(address in mem.bit)
All hardware where 4-bit manipulation can be
performed
4-bit
With MBE = 1 and MBS = 15, register indirect addressing
(address in @HL)
B-bit
With MBE= 0 (or MBE = 1 and MBS = 15) direct addressing
(address in mem); mem must be an even address
All hardware where B-bit manipulation can be
performed
With MBE = 1 and MBS = 15, register indirect addressing (address
in @HL); L register must contain an even number
INSTRUCTIONS
The pPD751xx/p1xx provides a powerful set of 136
instructions.
Instruction Timing
The minimum instruction execution time is 0.95 ps with
a 4.19 MHz clock. The PCC register can be used to
program the CPU's minimum instruction cycle time to
0.95, 1.91, or 15,3 ps; all three speeds presuppose a
4.19 MHz crystal. Reducing the CPU clock speed will
reduce the microprocessor's power consumption.
Instruction Set
The instruction set contains the following features:
•
•
•
•
•
Versatile bit manipulation instructions
Efficient 4-bit manipulation instructions
a-bit instructions
GETI instruction to reduce program size
Vertically st()red instructions and base correction
instructions
• Table reference instructions
• 1-byte relative branch instructions
The instruction set is unusually powerful for a 4-bit
microcomputer. It consists of the full 75X instruction
set. It contains instructions that operate on 1-bit, 4-bit,
and a-bit data. It contains a-bit instructions generically
equivalent to virtually every 4-bit instruction type. Specifically, the instruction set contains the following a-bit
instruction types:
4-54
• Arithmetic: ADD W/CARRY, ADD W/SKlP,
.SUB W/BORROW, SUB W/SKIP
• Logical: AND, OR, XOR
• Comparison: SKE (skip if equal)
• Transfer: MOV, MOVT, XCH, IN, OUT, PUSH, POP, BR,
CALL
• Manipulation: INC W/SKJP, DEC W/SKIP
In addition, some of the 4-bit ports may be paired
together to function as one a-bit port. The combination
of 8-bit ports and 8-bit instructions allows IN and OUT
instructions to move full bytes of data at a time.
Organization. Tables 3 and 4 define the instruction set
symbols and operand formats, found in the instruction
set.
Clock Cycles. One machine cycle equals one CPU
Clock Cycle 4>. The PCC selects one of four available
CPU cycle speeds.
Skip Cycles. S equals the number of extra machine
cycles required for skip operation when executing a
skip instruction:
• S = 0; no skip
• S = 1; one- or two-byte instruction or GETI instruction is skipped
• S = 2; three-byte instruction is skipped (BR !addr,
CALL !addr)
NEe
pPD751XX/75P1xx
Table 3. Instruction Set Symbols
Table 4.
The devices use the following symbol definitions:
Symbol
Description
reg
regl
X, A, B, C, D, E, H, L
X, B, C, D, E, H, L
rp
rpl
rp2
rp'
rp'l
XA, BC, DE, HL
rpa
rpal
HL, HL+, HL-, DE, DL
DE, DL
n4
n8
4-bit immediate data or label
8-bit immediate data or label
mem (Note 1)
bit
8·bit immediate data or label
2·bit immediate data or label
fmem
pmem
FBOH·FBFH, FFOH-FFFH immediate data or label
FCOH-FFFH Immediate data or label
addr, caddr
JlPD75104: OOOH-FFFH immediate data or label
Symbol
A
B
C
D
E
H
L
X
XA
BC
DE
DL
HL
XA'
BC'
DE'
HL'
PC
SP
CY
PSW
MBE
RBE
PORTn
IME
IPS
IExxx
RBS
MBS
PCC
(xx)
xxH
Definition
A register; 4-bit accumulator
B register; 4-bit register
C register; 4-bit register
D register; 4-bit register
E register; 4-bit register
H register; 4-bit register
L register; 4-bit register
X register; 4-bit register
XA register pair; a-bit accumulator
BC register pair; 8-bit register
DE register pair; a-bit register
DL register pair; a-bit register
HL register pair; 8-bit register
XA' register pair; a-bit register
BC' register pair; a-bit register
DE' register pair; a-bit register
HL' register pair; a-bit register
Program counter
Stack pointer
Carry flag; bit accumulator
Program status word
Memory bank enable flag
Register bank enable flag
Port n (n = 0-9,12-14)
Interrupt master enable
Interrupt priority selection register
Interrupt enable flag
Register bank selection register
Memory bank selection register
Clock processor control register
Separation between address and bit
The contents addressed by xx
Hexadecimal data
Operation Representation Format
and Description Method
An operand is entered in the operand field of each
instruction according to the format of the instruction
(see assembler specifications). When two or more en
tries are indicated in the description method, one
should be selected. Capital letters and symbols must be
entered exactly as shown. For immediate data, a proper
numeric value or label should be entered as shown in
table 4.
Operand Formats
BC, DE, HL
BC, DE
XA, BC, DE, HL, XA', BC' DE', HL'
BC, DE, HL, XA', BC' DE', HL'
JlPD75106: OOOH-I77FH immediate data or label
JlPD75108: 000H-1F7FH immediate data or label
JlPD75Pl08: 000H-1FFFH immediate data or label
JlPD75112: 000H-2F7FH Immediate data or label
JlPD75116: 000H-3F7F immediate data or label
JlPD75P116: 000H-3FFFH immediate data or label.
faddr
II-bit immediate data or label
taddr
20H·7EH immediate data (where bit 0
PORTn
Port O·Port 9, Port 12·Port 14
IEBT, IESIO, IETO, IET1, IEO·IE4
RBO-RB3
MBO, MB1, MB15
IExxx
RBn
MBn
= 0) or label
Notes:
(1) Memory address must be an even number in 8·bit processing.
String Instructions
The jlPD751xx/P1xx family has the.following two types
of string effect instructions:
(1) MOV A, #n4 or MOV XA, #n8
(2) MOV HL, #n8
String effect means to place the same type instructions
in consecutive addresses. For example;
AO: MOVA, #0
A1: MOV A, #1
XA7: MOV XA, #07
4-55
II
ttlEC
pPD751XX/75P1xx:
If the first execution address is AO, the two subsequent
instructions are treated as NOP instructions during
program execution; if the first execution address is A1,
the instruction that follows is treated. as an NOP instruction during program execution. This means that
only the first string instruction is valid, with the follow-
ing string instructions being treated as NOPinstructions during program execution.
The string instructions increase efficiency when setting
constants into an accumulator (A register or Y.A
register-pair) or into a data pointer (HL register pair).
Instruction Set
Mnemonic
Operand
Bytes
Machine Cycle
Operation
Skip Condition
2
2
A- n4
reg1 -
String A
Transfer
MOV
A, #n4
reg1, #n4
XA, #n8
2
2
XA- n8
String A
HL, #n8
2
2
HL- n8
String B
rp2, #n8
2
2
A,@HL
2+S
A-
A,@HL-
2+S
A - (HL), then L+-L-1
A, @rpa1
L= 0
L= FH
A+- (rpa1)
XA +- (HL)
2
@HL,XA
2
2
(HL) - XA
A,mem
2
2
A- (mem)
XA,mem
2
2
XA .... (mem)
mem,A
2
2
(mem) -A
mem,XA
2
2
(mem) -XA
A, reg1
2
2
A-
XA, rp'
2
2
XA - rp'
reg1, A
2
2
reg1 +- A
rp'1, XA
2
2
rp'1
(HL) - A
A,@HL
(reg1)
+-
XA
A-(HL)
A,@HL+
2+8
A - (HL), then L+-L+1
L= 0
A,@HL-
2+S
A ... (HL), then L-L-1
L = FH
A, @rpa1
A - (rpa1)
XA,@HL
2
2
A,mem
2
2
A- (mem)
XA,mem
2
2
XA- (mem)
2
2
XA ... rp'
XA,@PCDE
3
XA +- (PC13-8+ DE)ROM
XA,@PCXA
3
XA
A, reg1
XA, rp'
4-56
(HL), then L-L+1
2
@HL,A
MOVT
rp2 - n8
A- (HL)
A,@HL+
XA,@HL
XCH
n4
XA- (HL)
A ... (reg1)
+-
(PC13-8+XA)ROM
NEe·
pPD751xx/75P1xx
Instruction Set (cont)
Mnemonic
Operand
Bytes
Machine Cycle
Skip Condition
Operation
Transfer (cont)
MOV1
CY, fmem.bit
2
2
CY, pmem.@L
2
2
CY - (pmem7_2+ '-3-2.bit(L1-0))
CY, @H+ mem.bit
2
2
CY - (H+ mema_o.blt)
fmem.bit, CY
2
2
(fmem.bit) - CY
pmem.@L, CY
2
2
(pmem7_2+ '-3-2.bit(L1-O)) - CY
@H+ mem.bit, CY
2
2
(H+ mema_o.bit) - CY
1+S
A- A+n4
Carry
2
2+S
XA - XA+n8
Carry
1+S
A- A+(HL)
Carry
XA - XA+rp'
Carry
rp'1 - rp'1 +XA
Carry
CY - (fmem.bit)
Arithmetic
ADDS
A, #n4
XA, #n8
A,@HL
ADDC
SUBS
SUBC
AND
XA, rp'
2
2+S
rp'1, XA
2
2+S
A,@HL
XA, rp'
2
2
rp'1, XA
2
2
A,@HL
A- A-(HL)
Borrow
2
2+S
XA - XA-rp'
Borrow
rp'1,XA
2
2+S
rp'1 - rp'1-XA
Borrow
XA, rp'
2
2
rp'1, XA
2
2
rp'1, CY - rp'1-XA-CY
A, #n4
2
2
A-A/\ n4
2
2
XA- XA/\ rp'
A,@HL
A, CY - A- (HL) - CY
XA, CY - XA-rp'-CY
A-A/\ (HL)
rp'1, XA
2
2
rp'1 - rp'1 /\ XA
A, #n4
2
2
A-AVn4
2
2
XA-XA V rp'
rp'1, XA
2
2
rp'1 - rp'1 V XA
A, #n4
2
2
A- AXOR n4
XA, rp'
2
2
XA - XA XOR rp'
rp'1, XA
2
2
rp'1 - rp'1 XOR XA
2
2
A-A
A,@HL
XA, rp'
XOR
rp'1, CY - rp'1 + XA+ CY
1+S
A,@HL
OR
XA, CY - XA+ rp'+ CY
XA, rp'
XA, rp'
a
A, CY - A+ (HL)+CY
A-A V (HL)
A,@HL
A - A XOR (HL)
Accumulator Manipulation
RORC
A
NOT
A
CY
+-
Ao,
Aa -
CY, An-1 - An
4-57
NEe
pPD751xx/75P1xx
Instruction Set (cant)
Mnemonic
Operand
Bytes
Machine Cycle
Operation
Skip Condition
reg - reg+ 1
=0
= OOH
(HL) = 0
(mem) = 0
reg = FH
rp' = FFH
Increment/decrement
INCS
DECS
reg
1+S
rpl
1+S
rp1 - rpl + 1
@HL
2
2+S
(HL) -
mem
2
2+S
(mem) -
1+S
reg - reg-1
2+S
rp' - rp'-l
reg
reg
rp1
(HL)+l
(mem) + 1
rp'
2
reg, #n4
2
2+S
skip il reg
@HL,#n4
2
2+S
skip il (H L)
1+S
skip il A
XA,@HL
2
2+S
skip il XA
A, reg
2
2+S
XA, rp'
2
2+S
Comparison
SKE
A,@HL
= n4
= n4
reg
= n4
= n4
(HL)
= (HL)
= (HL)
skip il A = reg
skip il XA = rp'
= (HL)
= (HL)
A = reg
XA = rp'
A
XA
Carry Flag Manipulation
SET1
CY
CLR1
CY
SKT
CY
NOT1
CY
CY-1
CY-O
1+S
skip il CY
CY
+-
=
1
+-
1
CY
=
1
CY
Memory Bit Manipulation
SET1
CLR1
SKT
SKF
4-58
mem.bit
2
2
(mem.bit)
Imem.bit
2
2
(Imem.bit) - 1
(pmem7_2+ l:3-2.bit(L1_0)) +- 1
pmem.@L
2
2
@H+mem.bit
2
2
(H + mem3-o.bit) +- 1
mem.bit
2
2
(mem.bit) +- 0
Imem.bit
2
2
(Imem.bit) - 0
pmem.@L
2
2
(pmem7_2+ L3_2.bit(L1-o))
@H+mem.bit
2
2
(H + mem3-o.bit)
<-
+-
0
0
=1
=1
mem.bit
2
2+S
skip il (mem.bit)
Imem.bit
2
2+S
skip if (Imem.bit)
pmem.@L
2
2+S
skip il (pmem7_2+ l:3-2.bit(L1-o))
@I;\+mem.bit
2
2+8
skip il (H+ mem3_0.bit)
skip il (mem.bit)
=1
=1
(pmem.@L = 1)
(mem.bit)
(Imem.bit)
=
=
1
(@H+ mem.bit)
=1
1
mem.bit
2
2+S
Imem.bit
2
2+8
=0
skip il (Imem.bit) = 0
pmem.@L
2
2+8
skip il (pmem7_2+ l:3-2.bit(L1-o))
@H+mem.bit
2
2+8
skip il (H+ mem3_0.bit)
=0
(Imem.bit) = 0
(pmem.@L = 0)
(mem.bit)
=0
=0
(@H+ mem.bit)
=0
NEe
IIPD751XX/75P1xx
Instruction Set (cont)
Mnemonic
Bytes
Machine Cycle
fmem.blt
2
2+S
skip if (fmem.bit)
pmem.@L
2
2+S
skip If (pmem7_2+ l:!-2.bit(Ll-ol)
@H+mem.bit
2
2+S
skip If (H+ mem3-o.blt)
Operand
Operation
Skip Condition
Memory Bit Manipulation (cont)
SKTCLR
ANDI
OR1
XORI
= 1 and clear
(fmem.bil)
= 1 and olear
= 1 and clear
CY, fmem.bit
2
2
CY - CY f\ (fmem.bil)
CY, pmem.@L
2
2
CY - Cy f\ (pmem7_2+ L3-2.bit(Ll-ol)
CY, @H+ mem.blt
2
2
CY - CY f\ (H+ mem3-Q.bit)
CY, fmem.blt
2
2
CY - Cy V (fmem.bil)
CY, pmem.@L
2
2
CY ... Cy V (pmem7_2+ l:!-2.blt(Ll-ol)
CY, @H+ mem.bit
2
2
Cy ... Cy V (H+ mem3-Q.bil)
CY, fmem.bit
2
2
Cy ... CY XOR (fmem.bil)
CY, pmem.@L
2
2
Cy ... CY XOR (pmem7_2+ l:!-2.blt(Ll-ol)
CY, @H+ mem.blt
2
2
Cy ... CY XOR (H+ mem3-Q.blt)
3
3
PCI3-Q ... addr
2
PC13-o ... addr
=1
(pmem.@L = 1)
(@H+ mem.blt)
=1
II
Branch
BR (Note 1)
addr
laddr (Note 1)
PCI3-Q - addr
$addr
BRCB
loaddr
2
2
PCI 3-o .... PCl3,12+caddrll-o
BA
PCDE
2
3
PC13-o -
PCI3-S+ DE
PCXA
2
3
PCI 3-Q -
PCI3-S+ XA
Subroutine Stack Control
CALL
laddr
3
3
(SP-4)(SP-l)(SP-2) ... PC11-o
(SP-3) - (MBE, ABE, PCI3,121
PCI3-0 - addr, SP - (SP-4)
CALLF
Ifaddr
2
2
(SP-4)(SP-l)(SP-2) ... PCll-o
(SP-3) - (MBE, ABE, PCI3.121
PCI 3-0 - 00, faddr, SP - (SP-4)
AET
3
(MBE, ABE, PCI3,121 ... (SP+ 1)
PC11 -0 -(SP)(SP+3)(SP+2)
SP-(SP+4)
AETS
3+S
RETI
3
PUSH
POP
2
2
2
2
rp
BS
Unconditional
(PCI3.121- (SP+l)
PCll-o - (SP)(SP+3)(SP+2)
PSW ... (SP+ 4)(SP+ 5), SP - (SP+6)
(SP-l)(SP-2) -
rp
BS
(MBE, RBE, PCI3.121- (SP+l)
PCll-o - (SP)(SP+3)(SP+2)
SP - (SP+4), then skip unconditionally
rp, SP ... (SP-2)
(SP-1) .... MBS, (SP-2) +- RBS, SP +- (SP-2)
rp -
(SP+1)(SP), SP ... (SP+2)
MBS +- (SP+l), ABS -
(SP). SP .... (SP+2)
4-59
t¥EC
pPD751xx/75P1xx
Instruction Set (cont)
Mnemonic
Operand
Bytes
Machine Cycle
Operation
Skip Condition
Interrupt Control
2
2
IME .... 1
2
2
IExxx
2
2
IME .... O
2
2
IExxx .... 0
A, PORTn
2
2
A .... PORTn : (n = 0 to 9, 12-14)
XA, PORTn
2
2
XA .... PORTn+ 1, PORTn: (n = 4,6,8, 12)
2
2
PORTn ... A: (n = 2 to 9, 12-14)
2
2
PORTn+ 1, PORTn .... XA: (n = 4,6,8, 12)
HALT
2
2
Set HALT mode (PCC.2 .... 1)
STOP
2
2
Set STOP mode (PCC.3 ... 1)
EI
IExxx
01
IExxx
+- 1
Input/Output (Note 2)
IN
OUT
PORTn,XA
CPU Control
No operation
NOP
Specisl
SEL
GETI
= 0-3)
RBn
2
2
RBS ... n: (n
MBn
2
2
MBS .... n: (n = 0,1,15)
3
When the table is specified by the TBR
Instruction,
PC 11 -0 .... (taddrla_o + (taddr+ 1)
When the table is specified by the TeALL
Instruction
(SP-4)(SP-1)(SP-2) .... PC11-o:
(SP-3) .... (MBE, RBE, PC13,12l:
PC l 3-D .... (taddr)s-o + (taddr+ 1):
SP-SP-4
When the table Is specified by any other
instructions, the (taddr), (taddr+ 1) Instructions
are executed. (Note 3)
taddr
Depends on the
referenced
instruction
Notes:
(1) Appropriate Instructions are selected from BR laddr, BRCB
Icaddr, and BR $addr by the assembler. (BR laddr is not available
on the pPD75104I104A)
(2) When executing the IN/OUT instruction, either MBE must be
reset to 0, or MBE and MBS must be set to 1 and 15, respectively.
4-60
(3) TBR and TCALL are pseudolnstructions used only to specify
these tables.
ttlEC
pPD751XX/75P1xx:
Table 5. Digital Port Features
Port Number
Type
Operational Features
Comments
Port 0
4-bit Input
Can be read or tested at any time regardless of
the functional mode of the shared pins.
Pins are also used for Sl, SO, SCt<, and INT4.
Port 1
4-bit input
Can be read or tested at any time regardless of
the functional mode of the shared pins.
Pins also used for INTO-INT3.
On the pP075104A/1OBA, Internal pul~up
resistors are available for each line as a mask
option.
Port 3
Port 6
4-blt
VO
Can be set for input or output mode In 1-blt
units.
On the pP075104A/108A, internal pul~up
resistors are available for each line of port 6 as
a mask option.
Port 2
(Note 1)
4-bItVO
Can be set for input or output mode in 4-bit
units.
Pins are also used for PTOO, PT01, and PCL
Port 4
Port 5
Port 7
Port 8
Port 9
(Note 1)
4-bit
Can be set for Input or output mode In 4-bit
units.
Ports 4-5, 6-7, and 8-9 can be paired together to
enable 8-blt data transfers.
On the pP075104A/108A, internal pul~up
resistors are available for each line as a mask
option.
Port 12
Port 13
Port 14
(Notes 1, 2)
4-bitVO
Can be set for Input or output mode In 4-bit
units; Ports 12 and 13 can be paired to form a
single 8-bit VO port.
Except for pP075P108/P116, internal pul~up
resistors are available for each line as a mask
option.
VO
Notes:
(1) Ports 2-9 and 12-14 can directly drive LEOs. Total current must
not exceed 200 mA (peak).
Input/Output Ports
There are thirteen 4-bit ports; some are I/O ports and
some are input only. Figure 4 shows the structure of the
ports and table 5 lists the features. Figure ~ also shows
the structure of inputs and outputs of the other pins.
(2) The output stage of ports 12-14 contains an N-channel open-drain
transistor capable of withstanding 12 V.
The PCC register controls the HALT and STOP logic and
can also be used to set the CPU to operate at one of
three speeds. The CLOM register controls the output
clock PCL
Basic Interval Timer
Clock Generator
The clock generator (figure 5) uses the crystal inputs X1
and X2 as a time base to provide clocks for the
JlPD751xx!P1xx . The generator consists of an oscillator, frequency dividers, multiplexers, and two control
registers, (PCC and CLOM). By programming PCC and
CLOM, frequencies derived from the crystal are supplied to the CPU, the interval timer, the timer/event
counter, the serial interface, and the output pin, PCL
The basic interval timer (figure 6) is used to provide
continuous real-time interrupts. It consists of a mUltiplexer, an a-bit free-running counter, and a 4-bit control
register (BTM). Each time the counter reaches FFH it
causes an interrupt, overflows to OOH and continues to
count. The BTM register is used to select one of four
clock inputs to the counter as well as clear the counter
and its interrupt request. The counter can generate 250
ms interrupts with a 4.19 MHz crystal and also provides
oscillator stabilization time when the chip comes out of
the STOP mode.
4-61
II
NEe
pPD751XX/75P1u
Figure 4. I/O Circuit.
Type A
Type E-A
(for Type E)
(P40-P43, P50-P53, P60-P63,
P70-P73. P8o-P83, P90-P93)
VOD
,
Input
~,,"" ~"P,,_Ch"
VDD
Resistor
~; Pull-Up
(Mask Option for
Data
, 75104A and 75108A only)
IntOut
Output Disable
N-ch
CMOS standard input buffer
TypeB
Input/output circuit composed of a Type D push-pull
output and a Type A input buffer.
(POo. P03, P10-P13, TIO, TI1, RESET)
VDD
Pull-Up Resistor .
(Mask option ~'
available at P10-P13
for75104Aand751~8A)
,
Input
"
,
,
TypeF
(P01)
Data
In/Out
Output Disable
Schmit! trigger input with
hysteresis characteristic.
TypeD
(For Type E, F)
Input/output circuit composed of a Type D push-pull
output and a Type B Schmit! trigger input
VDD
Datalli~"p-Ch"
""
Output Disable
Type M-A
(P120-P123. P130-P133. P140-P143)
,," N-ch
,
VDD
Output
-=
,
Pull-Up Resistor ~
(Mask option not available ~
in 75P108or75P116) ..
' - - - t " - O IntOut
.
Da~
Output Dlsab: -L..,/'- I
Push-pull output where output can be placed in high
Impedance. P and N channels are tumed o~.
N-ch
(+12V)
TypeE
(PO 2 ,P20-P23, P30-P33)
Data
In/Out
Output Disable
MediumVoltage Input Buffer (+12 V)
TypeN
(PTHOO-PTH03)
InputlOutput circuit Composed of a Type D
output and a Type A"lnput bUffer.
PU~h.:pull
'
"
VREF
(Threshold Voltage)
49NR-7258
4-62
NEe
pPD751 xx/75P1 xx
Figure 5. Clock Generator
Interval Timer: fxx/25, fxx/27, fxx/29 , fxx/2 2
Timer/EventCounter: fxx/24, fxx/26, fxx/28, fxx/210, fxx/212
XTAL
~
~
X1
J
fxx
System
Oscillator
X2
STOP
I
Serial Interface: 0 (CPU Clock), fxx/24, fxx/21 0
Frequency Divider
118 1116
1112
I
I
Multiplexer --<> P22/PCL
STOP
Logic
ENB
1
CPU Clock Multiplexer
'I SEL
-
,I
Output
1
1/4
1
1
n
HALT
Logic
1
1
I
SEL
0
(to CPU)
a
HALT
I
PCC Register
CLOM Register
1
4{
4{
Inter nal
DataBus
49NR·7226
Figure 6. Basic Interval Timer
fxX /2 5
fxx/27
fxx/29
fxx/212
Overflow
8-Bit Binary
Counter
S
Interrupt
Request
Flag
Vector
Interrupt
Request
8
I n l e r n a l . . - - - - ' - - - - - - - - ' ' - - - - - - - - ' - - - - -____
DataBus~--------------------~
49NR-721A
4-63
~EC
pPD751XX/75P1xx
Timer/Event Counters
Serial Interface
Each of the two timer/event counters (figure 7) consists
of an 8-bit modulo register, 8-bit comparator, 8-bit
count register, clock multiplexer, mode control register,
and a TOUT flip flop. There is also some control logic so
that the timer's TOUT flip flop can be sent to port 2.
The 8-bit serial interface (figure 8) allows the
pPD751xx/P1xx to communicate with other NEC or
NEC-like serial interfaces. It consists of an 8-bit shift
register, 3-bit counter, clock multiplexer, and control
register SIOM. The three-wire interface consists of the
serial data in (SI), serial data out (SO), and serial shift
clock (SCK).
The two timers differ only by the clock selection to the
count register. Timer 0 has an fxx/16 clock input, and
Timer 1 has an fxx/4096 clock input. TIO and TI1 can also
be used as external clock inputs to count events.
The 8-bit shift register is loaded with a byte of data, and
when bit 3 of SIOM is set, 8 clock pulses are generated.
These pulses shift data out the SO line and data in from
the SI line, thus, communicating in full duplex. Each
time bit 3 of SIOM is set, a burst of eight clock pulses is
generated and eight bits of data will be sent. Data may
be sent either LSB or MSB first. The interface may also
be set to receive data only; in this case SO is in the
high-impedance state. One of four internal clocks or an
external clock may be used to clock the data.
An 8-bit value is loaded into the modulo register, and a
count register clock is selected by the clock multiplexer,
via control register TMO (or TM1 for counter 1). The
count register is incremented each time it receives a CP
pulse. When the value in the count register is equal to
the count in the modulo register, the comparator generates a signal which toggles the TOUT flip flop and
causes the count register to be reset to OOH. The count
register will continue to count up unless stopped. Each
time TOUT changes state it causes an interrupt. This
signal can also be used as a clock for the serial
interface.
Figure 7. Timer/Event Counter
InternaI
Data Bus
I
i
Mode Register
(TMO)
8
8f
I
J
Modulo Register
(TMODO)
I
L
l
Comparator
~
TOUT
F/F
~~
(T1 n1 )
To
Selector ~~
Control
Logic
j---+-P2 n
8
TI0(TI1)
Ixx/21 a
Ixx/28
,•• /2 6
Ixx/24 (TO)
IT
~
CP
Clock
Multiplexer
-
Count Register
(TO)
I
Serial Interface
(from Timer/Event
Counter a only)
IROTn
l.x/2 12 (T1)
49NR-720B
4-64
NEe
Comparator Port
The four-input comparator port (figure 9) contains a
resistor ladder with 4-bit resolution, a 4-1 multiplexer, a
comparator, a 1-4 demultiplexer, and an input result
register, PTHO. This port is controlled by the 8-bit PTHM
register and operates in a sequential manner. When bit
7 of the PTHM starts the comparator, the comparator
reads and converts input PTH3, then the others in order,
ending with PTHO. Then the PTHO register may be read
to get the results.
pPD751XX/75P1xx
Figure B. Serial Interface Block Diagram
Intemal[=====::::;======::::::;===:l
Data
Bu.
POa/SI
P02/SO-----t-------'
The user may select a slow or fast conversion time.
With a 4.19 MHz crystal, total time required to convert
all four inputs is 258 jJs and 32.3 jJs, respectively.
IROSIO
SEL
Bit Sequential Buffer
The bit sequential buffer is 16 bits of general-purpose
RAM located in the upper half of memory bank 15, and is
the only general-purpose RAM in this area All other
locations in this bank contain either the on-chip peripheral control registers or are unused addresses. A typical
application of this buffer might be to store data for the
next serial output or to store data from a serial input. It
could also be used to store data which is to be sent from
a port. This area can be bit, nibble, or byte manipulated.
Interrupts·
The jJPD751xx/P1xx family interrupts (figure 10) are all
vectored; there are five external and four internal interrupts. Table 4 gives a summary of the interrupts. The
hardware provides two levels of interrupt nesting; interrupt priorities can be changed via register IPS. Inputs
INT2 and INT3 will detect rising edges and generate an
interrupt request flag which is testable. Neither INT2 nor
INT3 will cause an interrupt, but they can be used to
release the STANDBY mode.
-0(CPUCLK)
Clock
- Ixx/2 4
P01/SCK~~---<.---I
Multiplexer _lxx/210
_TOUTFIF
49NA-719A
Figure 9. Comparator Port
PTHOa-+
PTHO.a
PTH02""
Input
PTH01 .... Multiplexer
PTHD.2
PTHOo'"
PTHD.O
PTHD.1
'----'
PTHO
Register
VDD
Rl2
R
PTHM7
R
Resistor
Ladder
Multiplexer
SEL
~HMO
·PTHMa
R
4
PTHM
Register
4
Rl2
Internal
Data Bus
49NR-718A
4-65
II
ttiEC
pPD751XX/75P1xx
Figure 10. Interrupt Controller Block Diagram
Intemal
Dam Bus /
cib~
I
9
Interrupt Enable Flag
(IEXXX)
I
I
I
t~
(IME) I IPS
t
•
Decoder
J
-
'--
IRQBT
INTBT
~
INT41POO
Double Edge
Detection Circuit
INTOIP10
'-I Detection
Edge
~
Circuit
IRQ
4
IROO
-
"'--1 Delection
Edge
~
Circuit
INT11P11
IRQt
•
INTSIO
IROSIO
•
INTTO
IROTO
IROT1
INTT1
Rising Edge
Detection Circuit
IRQ2
INT31P13
~
-->L~
r---
1ST··
Rising Edge
Detection Circuil
IRQ3
~
TI
VR~
____
-D
-D
-D
-D
Priority
Control
=::)
Vector
Table
Address
Gen
--=0
-D
-D
Request
Flags
'---
-
~
------'-: ""-
Standby
Release
Signal
49NR-7178
Standby Modes
The standby mode is summarized in table 7 and consists of three submodes, HALT, STOP, and Data Retention.
HALT mode. The HALT mode is entered by executing
the HALT instruction. In this mode, the. clock to the CPU
is shut off (thus stopping the CPU), while all other parts
of the chip remain fully functional.
STOP mode. The STOP mode is entered by executing
the STOP instruction. In this mode, the chip's main
system oscillator is shut off, thereby stopping all portions of the Chip.
4-66
The HALT and STOP modes are released by a RESET or
by any interrupt request.
Data Retention mode. This mode may be entered after
entering the STOP mode. Here, supply voltage Voo may
be lowered to 2 volts to further reduce power consumption. The contents of the RAM and registers are retained. This mode is released by first raising Voo to the
proper operating range, then releasing the STOP mode.
NEe
pPD751xx/75P1xx
Table 6. Interrupt Sources
Interrupt
Source
Operation and Source
Internal/
External
INTBT
Reference time interval signal from basic
interval timer
Internal
INT4
Both rising and f ailing edge detection
External
INTO
Selection of rising or falling edge detection
External
INT1
Selection of rising or falling edge detection
External
INTSIO
Serial data transfer completion signal
INTTO
Coincidence signal between timer/counter 0,
or edge detect ion of TIO input
'
INTT1
Interrupt
Priority
Vectored Interrupt Request Signal
(Vector Table Address)
VRQ1 (002H)
2
, VRQ2 (OOO4H)
Internal
3
VRQ3 (OOO6H)
InternaVExternal
4
VRQ4 (OOOBH)
Coincidence signal between timer/counter 1,
or edge detection of TI1 input
InternaVExternal
5
VRQ5 (OOOAH)
INT2
RiSing edge detection
External
Testable input signals (IRQ2 and IRQ3 are set)
INT3
Rising edge detection
External
a
Table 7. Standby Mode Operation
Item
STOP Mode
HALT Mode
HALT Instruction
Setting the mode
STOP Instruction
Clock oscillator
The main system clock oscillator is stopped
Only CPU cloc::k
Basic interval
timer
Operation stopped
Can Operate (IRQBT is set by reference time intervaQ
Serial interface
Can operate only when external SCK Input Is
selected for serial clock. (Note 1)
Can operate if other than CPU clock
serial clock
Timer/event
counter
Can operate oniy when Tin (n = 0, 1) pin Input
is selected for count clock
Can operate
Clock output
circuit
Stops operation
Can operate if other than CPU clock
CPU
Operation stopped
Operation stopped ,
Retained data
Contents of all registers (general registers, flags, mode registers, and output latches) and contents of data
memory retained
Release signal
Interrupt request signal (enabled with Interrupt enable flag) from operating hardware or RESET
cp is stopPed (~cillation contin~es)
cP is speoified as
cP is specified
Notes:
(1) Can also operate with TIOselected as the serial clock, but only
when Timer/Event Counter 0 Is operated with an external TIO
Input.
4-67
NEe
pPD751XX/75P1xx
RESET and the Reset Generator
Figure 11. Power-On-Reset Signal Generator and
PONF
The power-an-reset (POR) generator (figure 11) is always· .present in the· pPD75P108, not present in the
pPD75P116, and available by mask option in the mask
ROM devices.
RESET
The POR circuit generates a one-shot pulse by detecting the supply voltage rising edge. Use of this pulse is
determined by mask option:
(1)
I
-I)-....--'--'---'DInternal
V ,--__.
Reset Signal
(RES)
Switch
B
Both SWA and SWB are ON.
When the power suPPly rising edge is detected,
the internal reset signal (RES) is generated and
the power-on flag (PONF) is set at the same time.
(2)
SWA only is ON.
When the power supply rising edge is detected,
PONF is set. (RES is not generated automatically.)
(3)
Both SWA and SWB are OFF.
The power-on reset generator and and power-on
flag are disabled. RES is generated only by the
RESET input.
Internal
Bus
83VL-71 ..8A
Table 8. State of the Device after ReSet
RESET Inputted
During Standby Mode
Hardware
The six low-order bits of program memory address OOOH are loaded
into PC13-PCa. The contents of address 0001H are loaded Into
PC7-PCO.
Program counter (PC)
psw
RESE'l'lnputted
Dudng Normal Operation
or Power-on
Carry flag (CY)
Held
Undefined
Skip flags (SKO, SK1, SK2)
o
o
o
o
Interrupt status flags (ISTO, IS11)
Bank enable flags (MBE, RBE)
Bit 6 of program memory address OOOH Is loaded into RBE and bit
7 Into MBE.
Stack pointer (SP)
Undefined
Undefined
Data memory (RAM)
Held (Note 1)
Undefined
General purpose registers
(X, A, H, L, 0, E, B, C)
Held
Undefined
Bank selection registers
(MBS, RBS)
0,0
0,0
Baslo Interval timer
Timer/event counter
(n=O, 1)
Serial interface
4-68
Counter (B1)
Undefined
Undefined
Mode register (BTM)
0
0
0
Counter (Tn)
0
Modulo register (TMODn)
FFH
FFH
Mode register (TMn)
0
0
TOEn, TOFn
0,0
0,0
Shift register (SIO)
Held
Undefined
Mode register (SIOM)
0
0
NEe
pPD751xx/75P1xx
Table B. State of the Device after Reset (cont)
REm Inputted
FiE!ETlnputted
During Standby Mode
During Normal Operation
or Power·on
Processor clock control register
(PC C)
0
0
Clock output mode register
(CLOM)
0
0
Hardware
Clock generator
and clock output circu it
Interrupt function
Digital ports
Interrupt request flags (IRQxxx)
Reset to 0
Reset to 0
Interrupt enable flags (IExxx)
0
0
Priority selection register (IPS)
0
0
INTO, and INTl mode registers
(IMO,IM1)
0,0
0,0
Output buffers
Off
Off
Output latches
Cleared (to 0)
Cleared (to 0)
Input/output mode registers
(PMGA, PMGB, PMGC)
0
0
Bit sequential buffer
Analog port
II
0
0
PTHOO-OS input latches
Undefined
Undefined
Mode register (PTHM)
0
0
Power-on flag (PONF)
Undefined
1, Undefined (Note 2)
Bit sequential buffer
(BSBO-S)
0
0
Notes:
(1) Addresses OF8H to OFDH are undefined after RESET.
(2) This value is 1 upon power-on-reset and undefined during normal
operation.
EPROM Write/Verify
Table 9. EPROM Write/Verify Pin Functions
The pPD75P108 contains 8192 bytes of EPROM, while
the pPD75P116 has 16256 bytes. Table 9 shows the pin
functions during the Write/Verify cycles. Note that it is
not necessary to enter an address, since the address is
updated by pulsing the clock pins. When VDD = 6 V and
Vpp = 21 V in the pPD75P108 (or Vpp = 12.5 V in the
pPD75P116) are applied, the EPROM is placed in the
write/Verify mode. The operation is selected by the
MDO-MD3 pins, as shown in table 10.
Pin Name
Functlori
Xl,X2
After a write/Verlfy write, the Xl, and X2 clock
pins are pulsed. (Note that these pins are
also pulsed during a read.)
MOO-MOO
These are the operation mode selection pins.
P4o-P43
(four low-order bits)
PSo-PS3
(four high-order bits)
8-bit data Input/output pins for write/verify
Vee
,Supply voltage. Normally S volts; 6 volts Is
applied during writetverlfy
Vpp
Normally S volts; Vpp
21 V in the
JlPD7SP108 (or V pp = 12.S V in the
JlPD7SPl16) during wrlte/Verlfy
=
Notes:
(1) A cover should be placed over the UV erase window. The OTP
. devices do not have windows, thus the EPROM contents cannot
be erased.
4-69
fttIEC
pPD751 XX/75P 1:xx:
Caution
Table 10.
Apart from their normal functions, The POo/INT4 and
RESET pins are used to test the internal operation of
the programmable devices. The test mode is entered by
applying a voltage greater than VDD to either of these
pins.
For this reason, care must be taken to limit the voltage
applied to these two pins. F or example, it is conceivable
that even during normal operation enough spurious
noise may be present to set the chip into the test mode.
If this happens, further normal operation is impossible.
Consequently, it is important that interwiring noise be
suppressed as much as possible. If this is inconvenient,
anti-noise measures, like those shown in figure 12,
should be implemented.
The write!verify mode is entered by applying 6 volts to
VDD and Vpp = 21 V in the pPD75P108 (or Vpp = 12.5 V
in the pPD75P116). Mode is determined by the setting of
the MDO-MD3 pins; all other pins are tied to ground by
pulldown resistors.
Figure 12. Noise Reduction Techniques
MOO
MOl
M02
0
M03
0
Clear program memory address
Write mode
0
0
Operation Mode
0
x
Verify mode
Program inhibit
Notes:
(1) X = Don't care.
EPROM WriteNerifY Procedure
EPROMs can be written at high speed using the follow
ing procedure:
( 1) Pull unused pins to Vss through resistors. Set the
X1 pin low.
( 2) Supply 5 volts to the VDD and Vpp pins.
( 3) wait for 10 ps.
( 4) Select the clear program memory address mode.
A. Connection of diode between
POo/INT4 or RESET and VOO
( 5) For the pPD15P108, supply 6 volts to VDD and 21.0
volts to Vpp. For the pPD75P116, supply 6 volts to
VDD, and 12.5 vcilts to Vpp.
I
Voo
..
WritelVerify Operation
vpp = 21 V intheIlPD75P108, vpp = 12.5 inthe1lPD75P116,
voo = +6.0V
Operation Mode SpeCification
( 6) Select the program inhibit mode .
POOIINT4 (RESET)
( 7) Write data in the 1 ms write mode.
( 8) Select the program inhibit mode.
( 9) Select the verify mode. If the data is. correct,
proceed to step 10. If not, repeat steps 7, 8, and 9.
B. Connection of capacitor between
POOIINT4 or RESET and VDO
+
(10) Perform one additional write with an MDO pulse
width equal in ms to the number of writes performed in step 7, times 1 ms.
I
voo
(11) Select the program inhibit mode.
POo/INT4 (RESET)
83R.D·7149A
(12) Apply four pulses to the X1 pin to increment the
program memory address by one.
(13) Repeat steps 7-12 until the end address is reached.
(14) Select the clear program memory address mode.
(15) Return the VDD and Vpp pins back to
(16) Turn off the power.
+ 5 volts.
NEe
pPD751XX/75P1xx
Figure 13. EPROM Write/llerify Cycle Timing
""'!-~----x Repetitions----~I
~Write-~'~I""--Verify---;~+-'-Additional Write-.....~I.---Address Increment---..j-I
Vpp= 12.SV - - - r-------------~ff_:...------------------VPP=VDD--f
r-------------->ff_-------------------
VDD=VDD+1- - VDD=VDD--f
X1
,
J
p~~:~~ -----«
InputDala
>--<
Output
Data~!---(
Input Data
)>-------------
II
MDO
(P30)
MD1
(P3 1)
MD2
/
---'
/
r--------------~~-------------------
(P3 2) - - '
MD3
/r--------------;f,~(--------------------(P3 3 ) - - - ,
49NR·S76B
EPROM Read Procedure
( 6) Select the program inhibit mode.
The EPROM contents can be read by using the following procedure:
( 7) Select the verify mode. Apply four pulses to the X1
pin. Every four clock pulses will output the data
stored in one address.
( 1) Pull unused pins to Vss through resistors. Set the
X1 pin low.
( 8) Select the program inhibit mode.
( 2) Supply 5 volts to the VDD and Vpp pins.
( 9) Select the clear program memory address mode.
( 3) Wait for 10 ps.
(10) Return the VDD and Vpp pins to
( 4) Select the clear program memory address mode.
(11) Turn off the power.
+ 5 volts.
( 5) For the pPD75P108. supply 6 volts to VD D and 21.0
volts to Vpp. For the pPD75P116. supply 6 volts to
VDD. and 12.5 volts to Vpp.
4-71
NEe
pPD751XX/75P 1xx:
rll/ure 14. EPROM Read Cycle Timing
r -----------------------------~----------~J~
Vpp= l2.SV Vpp.Voo--'
voO=VOO+l - I.,..
--~--------------------------------------~J~
voo·voo--'
'1/\
Xl
p~~~~----------~(~
______O_ut_pu_tO_a_m____
__J)(~______Ou_tP_ut_~_m
\
MOO)
(P3o)
J)(~__________~~~
______
r
~.------------------~-----------------------------,
MOl
(P31l __________
~----------------------------------------------~J~
r-------------------------------------------_a----
M02/
(P32l
M03
,r----------------oJ\.
(P33l - - - '
"49NR-517B
Program Memory Erase (pPD75P108DW only)
The pPD75P108DW allows the programmed data co~
tents to be erased by light rays whose wavelength IS
shorter than about 400 nm. The programmed data
contents may also be erased if the uncovered window is
exposed to direct sunlight or a fluorescent light for
several hours. Thus, to protect the data contents, cover
the window with an opaque film. NEe provides qualitytested shading film with each UV EPROM shipment.
4-72
F or normal EPROM erase, place the device under an
ultraviolet light source (254 nm). The minimum amount
of radiation exposure required to erase the
pPD75P108DW completely is 15 Ws/cm 2 (ultraviolet ray
strength times erase time). This corresponds to about
15 to 20 minutes when using a UV lamp of 12 Vpp pW/
cm2• However, the erase time may be prolonged if the
UV lamp is old or if the device window is dirty. The
distance between the light source and the window
should be 2.5 cm or less.
NEe
pPD751XX/75P1:xx
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (J1PD751xx)
TA
= 25°C
-0.3 to + 7.0 V
Supply voltage, Voo
Operating temperature, tOPT
-40 to + 85°C
Input voltage, VI1 (ports 12-14)
-0.3 to Voo + 0.3 V
Storage temperature, tSTG
-S5 to + 1500C
Input voltage, VI2 (ports 12-14;
internal pull-up resistor)
-0.3 to Voo + 0.3 V
Input voltage, VI2 (ports 12-14;
open drain)
-0.3 to +13V
(Note 1)
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent
damage.
Output voltage, Vo
-0.3 to VOO + 0.3 V
High-level output current, IOH
(Single pin)
-15mA
High-level output current, IOH
(Total of all pins)
-30 mA
Low-level output current, IOL
(Single pin)
Low-level output current, IOL
(Total of ports 0, 2-4, 12-14)
Low-level output current, IOL
(Total of ports 5-9)
Notes:
(1) When applying more than 10 V to ports 12, 13, or 14, the external
pull-up resistor must be at least 50 ko'
(2) rms value
=
pk x (duty cycle) Yo.
Capacitance (J1PD751 xx)
30 mA pk
15 mA rms (Note 2)
100 mA pk
SO mA rms (Note 2)
100 mA pk
voo
=
0 V; TA
=
25°C
Parameter
Symbol
Max
Unit
Conditions
Input capacitance
CIN
15
pF
Output capacitance
COUT
15
pF
I/O capacitance
CIO
15
pF
f = 1 MHz;
all unmeasured
pins returned
to ground
SO mA rms (Note 2)
Oscillator Characteristics (All devices)
/lPD751xx: TA = -40 to + 85°C; Voo = 2.7 to S.O V
/lPD75Pl08: TA = -10 to + 85°C; VOO = 4.5 to 5.5 V
/lPD75PllS: TA = -40 to + 85°C; VOO = 4.5 to 5.5 V
Oscillator
Parameter
Symbol
Min
Ceramic resonator
(Figure 15A)
Oscillation frequency (Note 1)
!xx
2.0
Crystal resonator
(Figure 15A)
External clock
(Figure 159)
Oscillation stabilization time (Note 2)
Oscillation frequency (Note 1)
!xx
2.0
Oscillation stabilization time (Note 2)
Typ
Max
Unit
5.0
MHz
4 (Note 3)
ms
5.0
MHz
10 (Note 3)
ms
30 (Note 3)
ms
Xl input frequency (Note 1)
fXX
2.0
5.0
MHz
Xl input high/low level width
!xH, !xL
100
250
ns
Conditions
After Voo reaches
oscillation voltage
Voo
= 4.5 to S.O V
Notes:
(1) The oscillation frequency and Xl input frequency are included
only to show the characteristics of the oscillators. Refer to the AC
Characteristics table for actual instruction execution times.
(3) Values shown are for the recommended resonators. Values for
resonators not shown in this data sheet should be obtained from
the manufacturer's spec sheets.
(2) The oscillation stabilization time is the time required for the
oscillator to stabilize after voltage is applied or the STOP mode is
released.
4-73
II
NEe
pPD751 XX/75P 1xx
Recommended Ceramic' Resonators (tlPD751 xx)
Figure 15. System Clock Configurations
A. CeramlclCrystal Resonator
de
C21:
~
Manufacturer
Part Number
C1
(pF)
C2
CPF)
Murata
CSA2.00MG
30
30
VOO
CSA4.19MG
30
30
VOO
CSA4.19MGU
30
30
KBR-2.0MS
100
100
KBR·4.0MS
KBR·4.19MS
KBR·4.9152M
33
33
33
33
CST4.19T
(Note 1)
X2
Kyocera
B. Extarnal Clock
L>~t----I
Remarks
= 2.7 to 6.0 V
= 3.0 to 6.0 V
VOO = 2.7 to 6.0 V
VOO = 3.0 to 6.0 V
Voo
= 3.0 to 6.0 V
33
33
Note8:
X1
(3) Cl and C2 are contained in the oscillator.
"P074HCU04
X2
Note: When the Input Is an external clock, the stop mode
cannot be set because the X1 pin Is connected
to System ground (VSS).
83RD-6805A
Recommended Crystal Resonator (tlPD751 xx)
Manufacturer
Frequency (MHz)
Part Number (note 1)
C1 (pF)
C2 (PF)
4.19
HC-49/U
22
22
Kinseki
Remarks
Voo
= 2.7 to 6.0 V
Notes:
(1) Equivalent series resistance of crystal must be less than 80
n
Comparator Characteristics (All devices)
JIPD751xx: Voo = 4.5 to 6.0 V; TA = -40 to + 85°C
JIPD75Pl08: TA = -10 to + 85°C; Voo = 4.5 to 5.5 V
JIPD75P116: TA = -40 to + 85°C; Voo = 4,5 to 5.5 V
Parameter
Symbol
Min
Comparison accuracy
o
o
Threshold voltage
PTH input voltage
Comparator consumption
current
4-74
ICOMP
Typ
Max
Unit
±100
mV
Voo
v
Voo
Conditions
V
mA
Set PTHM7 to
1
NEe
pPD751xx/75P1xx
DC Characteristics (J.tPD751xx)
TA = -40 to +85°C; Voo = 2.7 to 6.0 V
Parameter
High-level input voltage
Low-level input voltage
High-level output voltage
Symbol
Min
Typ
Max
Unit
VOO
V
Except ports 0,1,12-14, TlO, Til, RESET, XI, X2
Ports 0, 1, TIO, Til and RESET
VIHI
VIH2
0.8VOO
VOO
V
VIH3
0· 7V 00
VOO
V
Ports 12-14; buitt-in pull-up resistor
V
Ports 12-14; open drain
0· 7V 00
12
VIH4
VOo-°·5
VOO
V
XI, X2
VIL 1
°
0.3VOO
V
Except ports 0, 1, TIO, Til, RESET, XI, X2
VIL2
°
0.2VOO
V
Ports 0, 1, TIO, Til and RESET
VIL3
°
VOo-l.0
0.4
V
XI, X2
V
VOO = 4.5 to 6.0 V; IOH = -1 mA
V
VOO = 2.7 to 6.0 V; IOH = -100 JiA
Ports 0, 2-9; VOO = 4.5 to 6.0 V; IOL = 15 rnA
VOH
Voo-°·5
Low-level output voltage
High-level input leakage current
Low-level input leakage current
High-level output leakage current
Conditions
O·7VOO
0.35
2.0
V
0.35
2.0
V
Ports 12-14; Voo = 4.5 to 6.0 V; IOL = 10 rnA
0.4
V
VOO = 4.5 to 6.0 V; IOL= 1.6 rnA
0.5
V
IOL = 400 JiA
IUHl
3
JiA
All except X1, X2, and ports 12-14; VIN = VOO
IUH2
20
J1A
Xl, X2; VIN = VOO
IUH3
20
JiA
Ports 12-14 (with open drain); VIN = 12 V
JiA
All except Xl, X2; VIN = ° V
VOL
IUL 1
-3
IUL2
-20
JiA
Xl,X2;VIN=OV
ILOHI
3
JiA
Other than Ports 12-14; VOUT = Voo
ILOH2
20
JiA
Ports 12-14 (open drain); VOUT = 12 V
Low-level output leakage current
ILOL
-3
JiA
VOUT =
Internal pull-up resistor
RL
70
kO
Ports 12-14; Voo = 5.0 V ± 10%
Supply current (Note 1)
1001
15
40
80
kO
Ports 12-14
9
rnA
Voo = 5 V ± 10% (Notes 2, 3)
0.55
1.5
rnA
Voo = 3 V ± 10% (Notes 3, 4)
600
1800
JiA
HALT mode; VOO = 5 V ± 10% (Note 3)
200
600
JiA
HALT mode; Voo = 3 V ± 10% (Note 3)
0.1
10
JiA
STOP mode; Voo = 3 V ± 10%
10
10D2
1003
oV
3
Notes:
(1) Does not include pull-up resistor current, current through the
power-on-reset circu it, or comparator current.
(3) fxx= 4.19 MHz; Cl = C2= 22 pF.
(4) When operated in the low-speed mode with the PCC set to 0000.
(2) When operated in the high-speed mode with the processor clock
control register (PCC) set to 0011.
4-75
II
NEe
pPD751XX/75P1xx
Figure 16. DC Characteristics (lJPD751xx)
100 vs Voo (4.19 MHz Crystal Rasonator)
100 vs fxx (Crystal Rasonator)
3.0
TA - 25"C
(Voo - 5.0 V. TA= 2S"C)
sooo
//
.....
Hlgrpeed rde
1000
~
=
SOO
~
f-
,-
~c
~
~
0
i
1'l
~(OO~ V
~
!
2.0
High-speed mode
(0011)
C
~
~
I'"
Mlddl&-speed mode
(0010)
1.5
<3
/'
Low-speed mode
(0000)
~
Q.
Q.
:>
UJ
HAL mode 0100) ,
J
100
so
1.0
V
----
J
HALTmre(0100)
r--
o
5
./
/
o
V
2
/
() Indicates set value for Pee
I
5
4
3
6
Power Supply Voltage VOO (V)
Mr
1
.
, .'
22pFr
4-76
X2
D
.
XTAL
4.194304 MHz
22PF
7
~
-
( ) Indicates set value for Pee
o
2
fxx (MHz)
10
1
.....-
0.5
:>
UJ
STOP mode (1000)
(When Power-on reset circuit and
Power-on flag are On-chIP~
I'"
/
'a.
Mlddl&-speed mode (0010)
Low-speed mod _~
(0000)
2.5
I
I
3
4
5
NEe
JlPD751xx/75P1xx
Figure 16. DC Characteristics (J.lPD751xx) (cont)
100 vs Voo (4.19 MHz Ceramic Resonator)
100 vs fxx (Ceramic Resonator)
3.0
PA
2S'C
(Voo = 5.0 V. TA= 2S'C)
""....
SOOO
......,.....,
Hlgrpeed r i e
1000
19
c.
SOO
~
1
F=
II-
0
l
/'
Low-speed mod
(0000)
I
/
I
/
"
(/J
Middle-speed mode
(0010)
1.S
Low-speed mode
(0000)
0.
SO
.,./'
V
l---'"
V--
,..-
r-
HALT mLe (0100)
O.S
( ) Indicates set value for
"a;
(/J
I--
~
0.
STOP mode (1000)
(When Power-on reset circuit and
Power-on flag are on-chl P
o
y
10
S
---
1.0
~
8
~
0-
High-speed mode
(0011)
2.0
0
..9
E
~
<.>
"
~
0-
....""
V
~
Middle-speed mode (0010)
HAL~mode (b100) .-
..9
E
100
~
19c.
(OO~ /
2.5
o
2
I
I
3
4
pce
S
fxx (MHz)
./
/
/
1
o
( ) Indicates set value for PCC
1/
3
2
I
I
I
4
S
6
7
Power Supply Voltage VOO (V)
j;t
o
1
X2
Ceramic resonator
4.19 MHz
30pF
r r
30PF
4-77
pPD751XX/75P1xx,
Figure 16. DC Chsracferlstlcs ClJPD751xx) (cont)
100 va fxx (External Clock)
3.0
(Voo. 5.0 V. TA- 25"0)
2.5
'8
~
~0
.9
i
(3
i
...............
,
2.0
.,../
Hlgh~speed mode
(0011)
1.5
Middle-speed mode
(0010)
1.0
Low-speed mode
::J
(0000)
rJ)
----
I
0.5
o
I
I
L
2
3
'xx (MHz)
4-78
--
~
() Indlc:ate8 set value lor pee -
HALT mLe (0100)
o
~
4
5
NEe
IIPD751 xx/75P1 xx
Figure 16_ DC CharacteristiCS (JiPD751xx) (cont)
IOL vs VOL (Ports 0, 2-9)
IOL vs VOL (Ports 12-14)
30
VOO~/
!VO°Vvr
://
VOO=4V
ij /
1/
/
V
VOO=3V
~V
A'L
o
2
4
3
VOl.. (V)
II
W
o
2
3
4
VOl.. (V)
IOH vs VOO -VOH (Ports 0, 2-9)
-15
'-r;,I
Voo~V
.I
VOO25V
JV/ V
~V
l(! V
f; V
o
~
o
/"'" r--
VOO-4V
VOO=3V
r-
2
3
4
VOO-VOH (V)
4-79
ttlEC
pPD751XX/75P1xx
Power-on-Reset Circuit Characteristics (All devices exept IlPD75P116... notes 3, 4)
JlPD751xx: TA = -40 to +85°C
JlPD75Pl08: TA
-10 to + 85°C
=
Parameter
Symbol
Min
Power-on reset voltage, high
VOOH
4.5
Max
Unit
VOO max
V
0
0.2
V
(Note 1)
Jls
10
100
JlA
VOO = 5 V.
2
20
JlA
VOO = 2.5 V
Power-on reset voltage, low
VOOl
Power supply voltage rise time
tr
10
Power supply voltage off time
foil
1
POR circuit consumption circuit ;
JlPD75108 only (Note 2)
IOOPA
Typ
Conditions
= 6.0 V
= 5.5 V
j./PD751xx: VOO max
JlPD75Pl08: VOO max
s
j:
10%
Notes:
(1) 217/1"" (31.3 ms atf"" = 4.19 MHz)
(2) Current consumed when POR circuit or power-on flag is provided
internally.
Power-On-Reset 17mlng
(3) Power supply voltage must be raised smoothiy. See "Power-OnReset" timing diagram.
(4) Power-on-reset circuit is available as a mask option on on all
JlPD751xx devices, Is always provided with the JlPD75Pl08, and
not available on the j./PD75Pl16.
Voo
Note: Start the power supply smoothly.
83RD·5852A
AC Characteristics (lJPD751xx)
TA = -40 to + 85°C; VOO
= 2.7 to 6.0 V
Parameter
Symbol
Min
Max
Unit
Cycle time
(Note 1)
tCY
0.95
32
Jls
VOO
3.8
32
JlS
VOO
TIO, Til Input frequency
frl
0
0
TIO, Til input high- and low-level width
SCK cycle time
SCK high and low level width
4-80
Typ
MHz
275
kHz
0.48
j./s
1.8
j./s
0.8
j./s
0.95
j./s
3.2
j./s
3.8
Jls
.0.4
Condition.
= 4.5 to 6.0 V
= 2.7 to 6.0 V
VOO = 4.5 to 6.0 V
VOO = 2.7 to 6.0 V
VOO = 4.5 to 6.0 V
VOO = 2.7 to 6.0 V
Input; VOO = 4.5 to 6.0 V
Output; VOO = 4.5 to 6.0 V
Input; VOO = 2.7 to 6.0 V
Output; VOO = 2.7 to 6.0 V
JlS
Input; Voo = 4.5 to 6.0 V
0.5tKCy-50
ns
Output; VOO = 4.5 to 6.0 V
1.6
j./s
Input;. VOO
0.5 tKCy-l50
ns
Output; VOO
= 2.7 to 6.0 V
= 2.7 to 6.0 V
NEe
pPD751XX/75P1xx
AC Characteristics
~PD751xx)
(cont)
Symbol
Min
SI va SCK t setup time
tSIK
100
SI va SCK t hold time
tKSI
400
Parameter
Typ
Max
Unit
Conditions
ns
ns
SCK ~ to SO output delay time
300
ns
Voo
1000
ns
Voo
INTO-INT4 high- and low-level width
5
j./s
RESET low level width
5
/ls
= 4.5 to 6.0 V
= 2.7 to 6.0 V
Notes:
(1) Cycle time (minimum instruction execution time is determined
by the freque(1CY of the oscillator connected to the microcomputer, system clock control register (SCC), and the processor
clock control (PCC). See figure 17.
Figure 18. AC Timing IIeasurement Points
(except Ports 0, I, 710, 711, XI,X2,
lind RESET)
Figure 17. Guaranteed Operating Range
0.7 Voo _
(pPD751xx)
Measurement-O.7 Voo
O.3Voo -
poIn'"
II
- 0 .3Vco
tcy vs VDD (With main system clock)
Figure 1M Clock Timing IIeasurement Points
Clock TIming
Figure IBB.
71 71mlng
TITlming
TIO,Tll
0.8Voo
0.2Voo
ii
r-+--r-+~--+-~~I
0.5 ....._ - ' - _......._ ......._......l"--_"'"-_......_....I
°
2
3
4
5
8
7
Power Supply Voltage VOO (V)
4-81
NEe
pPD151XX/75P1xx
Figure
IBC~
Serial Transfer Timing
Figure IBF. fll VS Voo
fTl vsVOO
~---tKCY---~
5000
SI
I==+==+==t=~r==+==+===l
O.SVoo
0.2Voo
SCK
----t---::
::
1
~'"
~"
~
....
,.,. ....
,.,.
,. ...,
••••••••
\i;;. ,,."'
oT T T T T'FiTT
o
4-90
2
3
4
5
6
,.
~
'Ii
7
NEe
pPD751.xx/75P1:xx
, Data Memory STOP Mode Low Voltage Data Retention Characteristics (JLPD75P1 xx)
/lPD75Pl08: TA = -10 to + 85"C; voo = 4.5 to 5.5 V
/lPD75P116: TA = -40 to + 85"C; voo = 4.5 to 5.5 V
Parameter
Symbol
Min
Data retention voltage
VOOOR
2.0
Data retention current (Note 1)
IOOOR
Release signal set time
tSREL
Oscillation stabilization time (Note 2)
tWAIT
Typ
Max
Unit
5.5
V
0.1
10
/lA
/lPD75PI16; VOOOR = 2.0 V (Note 4)
15
40
/lA
/lPD75Pl08; VOOOR = 2.0 V (Note 4)
o
Conditions
/ls
217/fxx
s
Release by RESET input
(Note 3)
ms
Release by interrupt request
Notes:
BTM3
(1) Includes current in the power-on-reset circuit, but excludes current in the comparator circuit.
(2) Consult the manufacturer's resonator or crystal specification for
this value.
(3) Oscillation stabilization WAIT time is the time during which the
CPU is stopped and the crystal is stabilizing. This time is
required to prevent unstable operation while the oscillation Is
started. The interval timer can be used to delay the CPU from
executing instructions using the basic interval timer mode
register (BTM) according to the following table:
BTM2
BTMl
BTMO
WAITtime (fxx = 4.19 MHz)
0
0
1
1
0
1
0
1
0
1
1
1
220lfxx
217lfxx
2 15lfxx
213/fxx
(Approx 250 ms)
(Approx 31.3 ms)
(Approx 7.82 ms)
(Approx 1.95 ms)
(4) IOOOR Is less for the /lPD75P116 because it does not contain the
power-on-reset or power-on flag circu ity
DC Programming Characteristics (JLPD75P1 xx)
/lPD75Pl08: VOO
/lPD75PI16: VOO
= 6.0 ± 0.25 V; Vpp =
= 6.0 ± 0.25 V; Vpp =
21.0 ± 0.5 V; Vss
12.5 ± 0.3 V; Vss
= 0 V; TA = 25"C
= 0 V; TA = 25"C
Parameter
Symbol
High-level input voltage
VIH1
O·7VOO
VIH2
Voo-0.5
VIL1
0
VIL2
0
Low-level input voltage
Input leakage current
III
High-level output voltage
VOH
Low-level output voltage
Min
Typ
Max
Unit
VOO
V
All except XI, X2
VOO
V
Xl,X2
0.3VOO
V
All exc.ept XI, X2
0.4
V
Xl, X2
10
/lA
VIN
V
IOH
VOo-l.0
VOL
0.4
V
VOO supply current
100
30
rnA
Vpp supply current
Ipp
30
rnA
Conditions
= VIL or VIH
= -1 rnA
IOL = 1.6 rnA
MOO
= VIL;
MOl
= VIH
Notes:
(1) Vpp must not exceed +22.0 V (J.tP 075 Pl08) or + 13.5 V
(J.tPD75PI16), including overshoot.
(2) VOO must be applied before Vpp, and should be removed after
Vpp is removed.
4-91
II
WEe
pPD751XX/75P1xx
AC Programming Characteristics (IlPD75P1 xX)
J.lPD75Pl08: VOO
J.lPD75Pl16: VOO
= 6.0 :!: 0.25 V; Vpp = 21.0:!: 0.5 V; Vss = 0 V; TA = 25·C
= 6.0 :!: 0.25 V; Vpp = 12.5:!: 0.3 V; VSS = 0 V; TA = 25·C
Parameter
Symbol
Address setup time to MOO , (Note 2)
tAS
MOl to MOO , setup
tM1S
Data to MOO , setup
tos
Address hold from MOO
Data hold from MOO
t (Note 2)
t
Data output float from MOO
t delay
t
MOO t
(Note 1)
Min
tAS
2
J.ls
tOES
2
J.ls
tos
2
J.ls
tAH
2
J.lS
tOH
tOH
2
tOF
tOF
0
tAH
Max
Unit
J.ls
130
ns
Vpp Setup to MOO
tvps
tvps
2
VOO Setup to
tvos
tvcs
2
Initialized, program pulse width
tpw
tpw
0.95
1.05
ms
Adc!itional program pulse width
topw
topw
0.95
21
ms
MOO setup to MOlt
tMOS
tCES
2
Data output from MOO' delay
tDl/
MOl hold to MOO
t
tOEH
2
MOl recovery from MOO ,
tM1R
tOR
2
Program counter reset
tpCR
Xl input hlgh/low level width
!xH. !xL
Xl input frequency
!xx
Initial mode set
MOO setup to MD1
t
J.ls
J.ls
J.ls
tDl/
tM1H
;
v!
10
J.ls
MOO
= MOl = VIL'
J.ls
tM1H
J.ls
tM1H
+
+
0.125
MHz
tl
2
J.ls
J.ls
tM3S
tM3H
2
J.ls
MOO setup to MOO'
tM3SR
2
J.ls
Address to deta output delay time (Note 2)
tOAo
'Acc
2
Address to deta output hold time (Note 2)
tHAO
tOH
0
Data output from MOO , float delay time
ns
2
J.ls
tOFR
2
J.ls
(1) These symbols correspond to these of the J.lP027C256 EPROM.
(2) The Internal address signal Is Incremented by one by the rising
edge of the fourth XI pulse.The address Is not connected to an
external pin.
4-92
J.ls
130
tM3HR
Notes:
tM1R :i!: 50 J.ls
J.ls
4.19
MOO hold to MD1 ,
t
tM1R :i!: 50 J.I,S
J.lS
2
MOO output hold from MOO
Conditions
During program read
cycle
t\fEC
pPD751xx/75P1xx
Figure 21. EPROM Program Memory Write/Verify Timing
'VPS
~--------------~G~--------------------~)~
'VOS
~--------------~6~--------------------~5~
'XH
Xl
'XL
II
MOO
MOl
M02
~__________________~~___________________________'W~~~
M03
83RD-70488
4-93
NEe
pPD751XX/1SP1xx
Figure 22. EPROII Program Memory Read Timing
tvps
Vpp
vpp
VDD
tVDS
VDD +1
VDD
VDD
Xl
~~:~: ......-+--+----
>
83RO·683OB
4-97
pPD752Ox/7521x/75CG2xx/75P216A
Pin Configurations (cont)
64-Pin Ceramic Piggyback SDIP
S3
voo
S4
S2
S1
SO
... ~
4 voo9 1
POoIINT4
62
r.,
....2s9Voo
61
S5
60
S7
I
P01/SCK
A129 2
I
P02/SO
P03/S1
A79 3
P1 0 "NTO
I
P11"NT1
P12/1NT2
A69 4
P13fT1O
A59 5
I
I
P20
P21
A49 6
P22
P23/BUZ
A39 7
I
P30
I
P31
A29 s
I
P32
P33
A19 9
P60
I
I
S6
279 Voo 59
SS
58
S9
I
269A1357
I
58
VpRE
259AS
VLOAO
T151S10
I
T14/S11
T131S121PHo
249A9
T121S131PH1
I
T111S14/PH2
239A11
I
50
229 Vss. 49
I
4S
21 9vss 47
I
46
209A10 45
I
44
P61
A09 10
199CE
P62
I
I
1s917
P63
109 11
P40
I
I
P41
119 12
1791s
43
T10/S151PH3
T9
TS
T7
T6
T5
T4
T3
T2
T1
TO
RESET
P42
I
I
P53
P43
PPO
129 13
16 9 14
PS2
I
I
X1
29
15 9 13
30 vss9
L 14
___
31
~
X2
VSS
P51
PSo
XT2
XT1
83R()..6831A
4-98
NEe
t-IEC
pPD7520xn521x/75CG2xx/75P216A
Pin Configurations (cont)
64-Pin Ceramic Piggyback QFP
~ro~Q~~G«aG~~~~~~EM~
52
10 NC
100
101413 12
Ao
0
11
A1
0
10
A2
0
9
A3
0
8
A4 A5 A6
000
7
6
5 40A7
32
~
30
12 015
3 OA12 29
V55016
20VDD 28
27
10NC 26
NC017
320V
25
DD 24
31 OVDD 23
22
24
Q 0
17 CE A10
8 9
o
23
25 26 27 28
0
0
0
0
V55 NC A11 A9
10 11 12 13 14 15
29 3'0
22
0
~3~
A8
20
16 17 18 19
P01/5CK
POO/INT4
50
51
52
53
VDD
54
55
56
57
58
59
II
83RD·6832B
4-99
NEe
pPD752Ox/7521x/75CG2XX/75P216A
Pin Identification
Symbol
POoIINT4
Function
Port 0 input; interrupt 4
Port 0 input; serial clock
P02l'SO
Port 0 input; serial out
PO:JISI
Port 0 input; serial in
Plo1lNTO
Port 1 input; interrupt 0
Port 1 input; interrupt 1
Pl~NT2
Port 1 input; interrupt 2
Pl:J1TIO
Port 1 input; timer 0 input
Port 21/0
P2:J1BUZ
Port 2 I/O; buzzer output
P30-P3:J1MDD-MD3
Port 3 I/O; OTP operation mode
l/IPD75P216A)
P40-P43
Port 4 I/O
P50-P53
Port 51/0
P6o-P63
Port 61/0
PHoITI3/S12
Port H output; digit select line; segment line
Port H output; digit select line; segment line
Port H output; digit select line; segment line
PH:JITID/SI5
Port H output; digit select line; segment line
PPO
Pulse output
RESET
Reset input
S0-89
FIP segment outputs
TO-T9
FIP digit select outputs
T14/S11
T15/S10
Digit selects T14 and T15; segment lines S10
and SII
Voo
Positive power supply
FIP high-voltage negative supply voltage
P10-P13, INTO-INT2, TIO (Port 1, Interrupts,
Timer Input)
These pins can be used as 4-bit input port 1. P10 and P11
can also be used for edge-triggered interrupts INTO and
INT1. P12 can be used for INT2, which is also an
edge-triggered input, but one which generates an interrupt request and does not cause an interrupt. P13 can be
used as an input clock to the timer/event counter to
count external events. Reset causes these pins to default to the port 1 input mode.
P20-P23, BUZ (Port 2, Buzzer Output)
These pins can be used as 4-bit I/O port 2. When used as
an output the data is latched. When used as an input port
the port outputs are three-state. P23 can also be used to
output square waves for a buzzer. Reset causes these
pins to default to the port 2 input mode.
P30-P33 (MDO-MD3) (Port 3)
These pins are used for input/output port 3. Each bit in
this port can be independently programmed to be either
an input or output. This port has latched outputs. MOO
through MD3 are used for the MPD75P216A OTP program
memory write and verify mode to select the operation
mode. A reset causes this port to be in the input mode.
P40·P43 (Port 4)
These pins are used for input/output port 4; this port has
latched outputs. Port 4 outputs can directly drive an
LED. Ports 4 and 5 can be paired together to function as
one 8-bit port. A reset causes this port to be in the input
mode.
FIP predriver negative supply voltage
Vss
Ground
XI, X2
Main clock inputs
XT1, XT2
Subsystem clock inputs
PIN FUNCTIONS
POo-P03, INT4, SCK, SO, SI (Port 0, Interrupt 4,
Serial Clock, Serial In/Out)
These pins can be used as 4-bit input port O. POD can
also be used for vectored interrupt 4, which interrupts on
either the leading edge or the trailing edge of the signal.
P01-P03 may also be used for the serial interface under
the control of the SIOM register. SI is the serial input, SO
is the serial output, and SCK is the serial clock. Reset
causes these pins to default to the port 0 input mode.
'4-100
P50·P53 (Port 5)
These pins are used for input/output port 5; this port has
latched outputs and its outputs can directly drive an
LED. Ports 4 and 5 can be paired together to function as
one 8-bit port. A reset causes this port to be in the input
mode.
p60·P63 (Port 6)
Port 6 is a 4-bit I/O port. Outputs are latched, and each
bit can be independently programmed to be either an
input or an output. Port 6 can have pull-down resistors
added as a mask option. A reset signal causes this port
to default to the input mode.
NEe
PHo-PH3, T10-T13, S12-S15 (Port H, Digit Select,
Segment Lines)
Port H is a 4-bit output-only port, with P-channel opendrain outputs capable of directly driving LEDs. Pulldown resistors can be selected as a mask-option. Alternatively, these pins can be used as high voltage digit!
segment outputs. A reset signal causes this port to
default to the high-impedance state; if mask-option resistors are present the output goes low.
SO-S9 (Segment Lines)
These are high-voltage outputs used as FIP controller
segment lines. Pull-down resistors can be selected as a
mask-option. A reset signal sets these pins to the highimpedance state; if mask-option resistors are present
the outputs go low.
pPD7520x/7521x/75CG2xx/75P216A
PPO (Timer/Pulse Generator Output)
This is an output Signal from the timer/pulse generator,
and can be either PWM (Pulse Width Modulated) or a
square wave. This pin can also be used as a 1-bit output
port. Pin assumes a high impedance state upon reset.
X1, X2 (System Clock Inputs)
These pins are the main system clock inputs. The clock
can be either a ceramic or crystal resonator; an external
logic signal may also be used as a clock source.
XT1, XT2 (Subsystem Clock Inputs)
These pins are the subsystem clock inputs. The clock
can be either a ceramic or crystal resonator; an external
logic signal may also be used as a clock source.
RESET (Reset)
TO-T9 (FIP Digit Select)
This is the reset input, and it is active low.
These are high-voltage outputs used as FIP controller
digit select timing signals. Pull-down resistors can be
selected as a mask-option. A reset signal sets these pins
to the high-impedance state; if mask-option resistors are
present the outputs go low.
VPRE (Predriver Power)
T14/S11, T15/S10 (Digit Select/Segment Lines)
These two pins provide additional digit select or segment
lines. When not used for the display they can be used as
static outputs. Internal pull-down resistors are available
as a mask option.
This is the power supply for the predrivers of the FIP
controller/driver.
VLOAD (FIP Power Supply)
This pin is used to supply power to the output drivers for
the segment lines and digit select pins of the FIP
controller/driver.
Voo (Power Supply)
The system positive power supply pin.
Vss (Ground)
System ground.
4-101
NEe
pPD7520x/7521 xnSCG 2xx/7SP216A
Block Diagram
J.lI'D75206
(6016 Bytes)
J.lI'D75208
(8064 Bytes)
SI/P03
Data Memory
(RAM)
fLPD75206
(369 x 4)
fLPD75208
(497 x4)
fLPD75212A1216AI
P216A
(512 x4)
Decode
and
Control
fLPD75212A
(12160 Bytes)
SOIP0 2
SCK/P01
TO-T9
T1 0/S15/PH3T131S121PHo
INTO/P10
T141S11
INT1/P11
T15!S10
fxxl2N
INT2IP12
INT4IPOo
SO-S9
System Clock
Generator
8
VpRE '
VLOAD
BUZlP23
XT1 XT2
X1
X2
! ! !
• Not on fLPD75P216A
VDD VSS RESET
83RD-6583B
4-102
NEe
JlPD7520x/7521x/75CG2xx/75P216A
Product Comparison
Item
IlPD75CG208
IlPD75CG216A
IlPD75206
IlPD75208
IlPD75212A
IlPD75216A
IlPD75P216A
Program
memory
(ROM)
Piggyback
EPROM
00OOH-1FFFH
8192 x 8 bits
Piggyback
EPROM
OOOOH-3FFFH
16384 x 8 bits
Mask ROM
OOOOH-177FH
6016 x 8 bits
Mask ROM
OOOOH-1 F7FH
8064 x 8 bits
Mask ROM
00OOH-2F7FH
12160 x 8 bits
Mask ROM
OOOOH-3F7FH
16256 x 8 bits
OTP
OOOH-3F7FH
16256 x 8 bits
Data
memory
(RAM)
497 x 4 bits
512 x 4 bits
369 x 4 bits
497 x 4 bits
512 x 4 bits
512 x 4 bits
512 x 4 bits
Port 6
None
None
Mask option
(each bit)
Mask option
(each bit)
Mask option
(each bit)
Mask option
(each bit)
None
pul~down
resistor
SO-S8,
TO-T9
On-chip
pul~down
resistor
On-chip
Each bit can be mask programmed either for a
pul~down resistor or as an open drain eutput
pul~down
resistor
Each bit can be mask programmed either for a
or as an open drain output
pul~down
resistor
Open drain
S9,
T10-T15
Open drain
Open drain
Number
of FIP
segments
19 - 12
9 - 16
9 - 12
9 -12
9 - 16
9 -16
9-16
Power-on
reset
circuitry
On-chip
On-chip
Mask option
Mask option
Mask option
Mask option
None
Low-power
data
retention
Not provided
Not provided
2 volts
2 volts
2 volts
2 volts
Not provided
Operating
voltage
range
5V ± 10%
5V ± 10%
2.7 to 6.0 V
2.7to 6.0V
2.7 to 6.0V
2.7 to 6.0V
5V ±10%
Package
64-pin piggyback ceramic
shrink DIP with window.
64-pin piggyback
ceramic QFP with window.
64-pin plastic shrink DIP
64-pin plastic QFP
II
64-pin
plastic
shrink DIP
4-103
NEe
pPD752Ox/7521 x/75CG 2xx/75P216A
Capacitance (All Parts)
ELECTRICAL SPECIFICATIONS
Voo
Absolute Maximum Ratings (All Parts)
TA = 25°C
Supply voltage, Voo
-0.3 to + 7.0 V
Supply voltage, VLOAO
VOO-40 to Voo+ 0.3 V
Supply voltage, VpRE (Note 1)
VOo-12 to Voo+ 0.3 V
Supply voltage, Vpp (Note 2)
Input voltage, VI
-0.3 to + 13.5 V
-0.3 to Voo + 0.3 V
Output voltage, Vo (other than display)
Output voltage, Voo (display pins)
= OV; TA = 25°C
Parameter
Symbol
Input capacitance
Output capac~ance;
other than display
Output capac~ance;
display only
I/O
capac~ance
Max
Unit
CIN
15
pF
COUT1
15
pF
COUT2
35
pF
CIO
15
pF
-0.3 to Voo + 0.3 V
VOO-40 to Voo+ 0.3 V
High-level output current, IOH
(single pin; other than display)
-15mA
High-level output current, IOH
(single pin; SO-S9)
-15mA
Operating Supply Voltage
Mask ROM parts: TA = -40 to + 85°C
Programmable parts: TA = -10 to + 70°C
Parameter
CPU (Note 2)
Min
Max
Unit
(Note 3)
6.0
V
(Note 4)
5.5
V
/lPD75CG208/CG216A
and /lPD75P216A only
High-level output current, IOH
(single pin; TO-T15)
-30mA
4.5
High-level output current, IOH
(total of all pins other than display)
-20mA
4.5
6.0
V
4.5
5.5
V
High-level output current, IOH
(total of all display outputs)
17mA
Low-level output current, IOL
(total of all pins)
60mA
Power dissipation, PT (Plastic QFP)
450mW
Pr (Plastic SDIP)
'600 mW
Storage temperature, tSTG
-65 to + 150°C
Operating temperature, tOPT (Note 3)
-40 to +85°C
Operating temperature, tOPT (Note 4)
-10 to +70°C
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent
damage.
Notes:
(1) Does not apply to /lPD75P216A.
(2) For /lPD75P216A only.
(3) For mask ROM parts.
(4) For /lPD75CG208/CG216NP216A.
4-104
Conditions
-120 mA
Low-level output current, IOL (single pin)
Power dissipation,
Conditions
f = 1 MHz;
all unmeasured
pins returned
to ground
Timer/pulse
generator
4.5
6.0
V
(Note 4)
4.5
5.5
V
/lPD75CG208/CG216A
and /lPD75P216A only
Other hardwar:>-1>-----1 XI
XTI
I'PD74HCU04
X2
Open- XT2
Note: For 75P008, C3
Note: When the Input Is an external clock, the stop mode
cannot be set because the XI pin is connected
to System ground (Vss).
83RD·6444A
83RD-6443A
4-106
=22 pI and C4 =33 pI
NEe
JlPD7520x/7521 X/75CG 2xx/75P216A
Recommended Main System Clock OSCillator Circuit Constants
(Mask ROM Parts and "PD75CG216A)
.
Main system clock
= Ceramic; TA = -40 to
+85·C ~or mask ROM parts) and -10 to +70"C (for "PD75CG216A)
Remarks
Manufacturer
Product name (Note 1)
C1 (pF)
C2 (PF)
Murata
CSA2.00MG
30
30
CSA4.19MG
30
30
CSA4.91MG
30
30
CAT2.00MG
None
None
C on-chip type
CST4.19MG
None
None
C on-chlp type
CST 4.91MG
None
None
KBR-2.0 MS
47
47
KBR-4.0MS
33
33
KBR-4.19MS
33
33
KBR-4.91MS
33
33
FCR-3.58M2
30
30
FCR-4.00M2
30
30
FCR-4.19M2
30
30
FCR-4.19MC
None
None
Kyocera
TDK
C on-chlp type
.For mask ROM parts only
a
C on-chip type
Notes:
(1) Oscillation voltage range = 4.0 to 6.0 V for mask ROM parts and
Voo = 4.5 to 5.5 V for "PD75CG216A
Recommended Main System Clock Oscillator Circuit Constants
(Mask ROM Parts and "PD75CG216A)
Main system clock
Manufacturer
Klnsekl
= Crystal; TA =
-40 to +85·C (for mask ROM parts) and -10 to +70·C (for "PD75CG216Aj
Oscillator Voltage Range
Frequency
(MHz)
Retainer
Load Capacitance
CL (PF)
C1 (PF)
C2 (pF)
Min (V)
Max (V)
2.00
HC-18/U
16
20
20
4.5
(Note 1)
4.19
HC-49/U
16
20
20
4.5
(Note 1)
4.91
HC-43/U
16
20
20
4.5
(Note 1)
Notes:
(1) Oscillation voltage range max = 6.0 V for mask ROM parts and
5.5 V for "PD75CG216A.
Recommended Subsystem Clock Oscillator Circuit Constants
(Mask ROM Parts and "PD75CG216A)
Subsystem clock
= Crystal; TA = -10 to
+6O"C (for the mask ROM parts) and -10 to +70·C (for the "PD75CG216A)
OSCillator Voltage Range
Type
Load Capacitance
CL (pF)
C3 (pF)
C4 (PF)
R (kll)
Min (V)
Max (V)
Klnseki
P-3
12
22
22
330
(Note 1)
(Note 1)
Citizen
CFS-308
14
22
33
330
(Note 1)
(Note 1)
Manufacturer
Notes:
(1) Oscillation voltage range is 2.7 to 6.0 V for the mask ROM parts
and 4.5 to 5.5 V for the "PD75CG216A.
4-107
NEe
pPD752Ox/7521X/75CG2xxn5P216A
Recommended Main System Clock Ceramic Resonators (I'PD75CG208)
External Capacitors
Manufacturer
Product name
C1 (pF)
VDD Range
C2 (pF)
Min (V)
MaxM
4.5
5.5
Murata
CSA 4.19 MG
30
60
Kyocera
KBR-2.09 MS
68
68
4.5
5.5
KBR-3.58 MS
33
33
4.5
5.5
KBR-4.19 MS
33
33
4.5
5.5
KBR-4.9 M
33
33
4.5
5.5
Recommended Main System Clock Crystal Resonators (p.PD75CG208)
VDD Range
External Capacitors
Manufacturer (Note 1)
Product name
Kinseki
HC-49/U
C1 (pF) (Note 2)
C2 (pF)
Min M
MaxM
15
15
4.5
5.5
Notes:
(2) Variable range of C1 for frequency trimming should be 10 to 33
(pF).
(1) Equivalent series resistance of a crystal must be lower than 80 O.
Power-on Reset Characteristics (Note 1)
= -40 to +85'C, Voo = 2.7 to 6.0 (Mask ROM parts); TA = -10 to
TA
Parameter
Symbol
Min
POR high-level operating voltage
VOOH
4.5
+70'C, Voo
Typ
= 5 V :t10%
(,uPD75CG208 and "PD75CG216A)
Max
Unit
6.0
V
POR low-level operating voltage
VOOL
0
0.2
V
Supply vOltage rise time
Ir
10
(Note 2)
lIs
Supply voltage OFF time
toll
POR circuit current dissipation (Note 3)
IOOPR
Conditions
s
= 5 V :t
10
100
IIA
VOO
10
200
"A
VOO = 5 V :t10%
(,uPD75CG208/CG216A only)
2
20
"A
VOO
10%; (,uPD752Xx only)
= 2.7 V (,uPD752Xx only)
Notes:
(1) This circuit is present on the "PD75CG208 and "PD75CG216.ltis
a mask option on mask ROM parts and is not available on the
"PD75P216A.
(2) 217/fxx (31.3 ms at fxx
= 4.19 MHz).
Figure 3. Power-on Reset 77ming
VOO
(3) Current which flows when the internal reset circuit and power-on
flag are used.
Note: Start the power supply smoothly.
83RD-5852A
4-108
ttiEC
pPD7520x/7521x/75CG2xx/75P216A
DC Characteristics
TA = -40 to +85°C, voo = 2.7 to 6.0 V (Mask ROM parts); TA = -10 to +70OC; Voo = 4.5 to 5.5 V (Programmable Parts)
Parameter
Symbol
Max
Unit
High-level input voltage
VIH1
0.7Voo
Voo
V
VIH2
0.75Voo
Voo
V
Ports 0 and 1;
VIH3
Voe-0.4
Voo
V
Xl, X2, XT1
VIH4
0.65Voo
Voo
V
Port 6; Voo = 4.5 to 6.0 V (jlPD752xx only);
5 V ± 10% (programmable parts)
0.7Voo
Voo
V
Port 6; Voo = 2.7 to 6.0 V (jlPD752xx only)
All except poris 0,1,6; Xl, X2, XT1,
Low-level Input voltage
High~evel output voltage
Conditions
All except ports 0,1,6; Xl, X2, XT1, ~
RESET
FiESEf
VIL1
0
0.3Vo o
VIL2
0
0.2Voo
V
Ports 0, 1, and 6;
VIL3
0
0.4
V
Xl, X2,XT1
VOH
Voe-1.0
V
All outputs; 10H = -1
Voe-0.5
V
All outputs; 10H = -loopA (Note 11)
10-17; VIN = 0 V; I/.IPD75CG208/G216A only)
IlL
Low-level output voltage
VOL
Low-level Input
leakage current
Typ
V
Low-Ievel current
High-level input leakage current
Min
mET
rnA (Note 10)
-300
-BOO
~
0.4
2.0
V
Ports 4 and 5; 10L = 15 rnA (Note 10)
0.4
V
All output pins; 10L = 1.6 rnA (Note 10)
All output pins; 10L = 400 pA (jlPD752xx only)
0.5
V
IlIH1
3
~
All except Xl, X2, and XT1; VIN = Voo
ILIH2
20
~
Xl, X2, and XT1; VIN = Voo
ILIL1
-3
~
All except Xl, X2, and XT1; VIN = 0 V
ILlL2
-20
~
Xl, X2, and XT1; VIN = OV
II
High-level output leakage current
ILOH
3
~
All output pins; VOUT = Voo
Low-level output leakage current
ILOL1
-3
~
All except display output pins; VOUT = 0 V
ILOL2
-10
~
Display output pins; VO UT = VLOAO = Voo-35 V
Display output current
Internal pull-down resistor
(mask option)
100
Rpe
RL
-3
-5.5
mA
80-89 (Note 1)
see Recommended External Circuit
-3
-5.5
mA
80-S9; Voo = 4.5 to 6.0 V; Voo = Voo -2 V
I/.IPD75P216A only)
-1.5
-3.5
mA
80-89; All except "PD75P216A (Note 2) .
-15
-22
mA
TO-T15 (Note 1)
see Recommended External Circuit
-15
-22
mA
TO-T15;Voo = 4.5t06.0V;Voo =Voo-2V
I/.IPD75P216A only)
-7
-15
mA
TO-T15; All except "PD75P216A (Note 2)
30
80
200
kO
Port 6; Voo = 4.5 to 6.0 V (jlPD75206/208)
20
80
200
kG
Port 6; Voo = 4.5 to 6.0 V (jlPD75212A/216A only);
VIN = Voo
30
1000
kG
Port 6; Voo = 2.7 to 6.0 V I/.IPD75206/208)
20
1000
kG
Port 6; Voo = 2.7 to 6.0 V I/.IPD75212A/216A only);
VIN = Voo
25
70
135
kG
Display output pins; VOO-VLOAO = 35 V
I/.IPD75212A/216A/P216A)
40
70
120
kO
Display output pins; VOO-VLOAO = 35 V
I/.IPD75206/208/CG208/CG216A)
4-109
NEe
pPD752Ox/7521 x/75CG 2XX/75P216A
DC Characteristics (cont)
Parameter
Supply current
(Note 6)
Symbol
IDOl
(Note 3)
1002
(Note 3)
1003
1004
1005
Min
Typ
Max
Unit
Conditions
3.0
9.0
mA
Voe = 5 V :!: 10% (Note 4)
0.55
1.5
mA
Vee =3 V :!: 10% (Note 5; IIPD752xx only)
600
1800
HALT mode; Vee = 5 V:!: 10% (Note 12)
200
SOO
IIA
IIA
40
120
IIA
Vee = 3 V :!: 10% (Notes 7, 8; IIPD752xx only)
100
300
IIA
(Note 7; IIPD75CG208/CG216A and
IIPD75P21SA only)
5
15
IIA
HALT mode; Voo = 3 V :!: 10%
(Notes 7, 8; IIPD752xx only)
40
100
IIA
HALT mode (Notes 7, 8; ",PD75CG208/CG216A
and ",PD75P21SA only)
0.5
20
IIA
STOP mode; XTI = 0 V; Voo = 5 V :!: 10 %;
IIPD752xx only (Note 6)
0.1
10
IIA
STOP mode; XTt = 0 V; Voo = 3 V:!: 10 %;
IIPD752xx only (Note 6)
10
200
IIA
STOP mode; XTI = 0 V;
(Note 9; IIPD75CG208 and IIPD75CG216A only)
0.5
200
IIA
STOP mode; XTt
HALT mode; Vee = 3 V :!: 10% (,uPD752xx only)
= 0 V (,uPD75P216A only)
Notes:
(1) Voo = 4.5 to S.O V for mask ROM parts and Voo = 4.5 to 5.5 V
for programmable parts; Voo = Voo -2 V; VPRE = Voo -9:!: 1 V.
(2) Veo = 4.5 to 6.0 V for mask ROM parts and Voo = 4.5 to 5.5 V
for programmable parts; Voo = Voo -2 V; VpRE = 0 V.
(7) 32 kHz crystal osci lIator.
(8) Value when the system clock control register (SCC) is set to
1001, generation of the main system clock pulse is stopped, and
the CPU Is operated by the subsystem clock pulse.
(3) 4.19 MHz crystal oscillator; Cl = C2 = 15 pF.
(9) With the CE or OE of the piggybacked .EPROM set high.
(4) Value during high-speed operation and the processor control
clock (PCC) is set to 0011.
(10) Voo = 4.5 to 6.0 V for mask ROM parts and Voo = 4.5 to 5.5 V
for programmable parts.
(5) Value during low-speed operation and the processor control
clock (PCC) is set to 0000.
(11) Voo = 2.7 to 6.0 V for mask ROM parts and Voo = 4.5 to 5.5 V
for programmable parts.
(6) Does not include pull-down resistor current for SO-S8 and TO-T9.
In the mask ROM parts, the current for the power-on reset circuit
(mask option) is not included. In the IIPD75CG208/CG216A, the
current for the piggyback EPROM and the current in the on-chip
pull-up resistors for 10-17 is not included.
(12) For the IIPD75CG208/CG216A, the CE or OE pin of the piggyback EPROM is set to a high level.
4-110
(t3) No subsystem clock.
NEe
pPD752Ox/7521 x/75CG 2xx/75P216A
AC Characteristics
Mask ROM parts: TA = -40 to +85°C; Voo = 2.7 to 6.0 V
Programmable parts: TA = -10 to + 700C; Voo = 5 V ± 10%
Parameter
Symbol
Min
Max
Unit
Cycle time: minimum
instruction execution time
(Note 1)
Icv
0.95
32
"s
Main system clock; Voo = 4.5 to Voo max
3.8
32
"s
Main system clock; Voo = 2.7 to 6.0 V;
(p.PD752xx only)
TIO input frequency
Itl
114
Typ
122
125
"s
0
0.6
MHz
Voo = 4.5 to VOO max (.uPD752xx/P216A)
0
165
kHz
Voo = 2.7 to 6.0 V (.uPD752xx only)
MHz
0
TIO input lowand high-level width
SCK cycle time
SCK low- and high-level width
SCK i setup time
SI vs. SCK i hold time
SCK ~ - SO output delay time
S I vs.
Interrupt inputs lowand high-level width
RESET lOW-level width
tiL, tlH
tKCV
tKL, tKH
(.uPD75CG208/CG216A only)
"s
Voo = 4.5 to VOO max (.uPD752xx and
"PD75P216A only)
3
"s
Voo = 2.7 to 6.0 V (.uPD752xx only)
0048
"s
(p.PD75CG208/CG216A only)
0.8
"s
Input; Voo = 4.5 to Voo max
0.95
"s
Output; Voo = 4.5 to Voo max
3.2
"s
Input; Voo = 2.7 to 6.0 V (.uPD752xx only)
3.8
"s
Output; Voo = 2.7 to 6.0 V (.uPD752xx only)
004
"s
Input; Voo = 4.5 to Voo max
0.5tKcv- 50
ns
Output; Voo = 4.5 to Voo max
1.6
"s
Input; Voo = 2.7 to 6.0 V (.uPD752xx only)
Output; Voo
0.5 tKCV - 150
ns
100
ns
tKSI
400
tKSO
tRSL
Subsystem clock
0.83
tSIK
tINTL, tlNTH
Conditions
= 2.7 V to 6.0 V (p.PD752xx only)
ns
300
ns
Voo = 4.5 to Voo max
1000
ns
Voo = 2.7 to 6.0 V (.uPD752xx only)
(Note 2)
"s
INTO
2 Icv
"s
INT1
10
"s
INT2.INT4
10
"s
Notes:
(1) Cycle time is determined by the frequency of the oscillator
connected to the microcomputer. system clock control register
(SCC). Voo, and the processor clock control (PCC). See the
graph depicting the supply voltage vs. The cycle time when the
microcomputer is operating on the main system clock.
(2) 2tcv or 128/fxx • depending on the setting of the interrupt mode
register (IMO).
Recommended External Circuit
Voo
+5V
R09.1EL
'] ~ B.29-9.3V
VpRE
68kn
VLOAO
GN°h
-30V
83RD·6559A
4-111
II
t\fEC
pPD7520X/7521X/75CG2xx/75P216A
DC Characteristics C#£PD752xx only)
loovsVOO
I OL vs VOL (Ports 0, 2, 3, 6)
20
TA-25'C
5000
High-speed mode
reC-(OO 11) " .
Mlddl...speed mod~ " .
PCC-(0010)
1000
fl
15.
500
~
~
0
.J;l
i
<3,.,
R:
"
--
PCC (0000)
r--
HALT
(0,100)
/'
./
/'
f-- Subsystem clock
. f--' operaUon mode"
/
/
HALT mode
.'/
/
V
2
-
/'
( ) Indicates set1vaiue
3
I
VOO=2.7V
~
~
o
2
3
4
4
5
6
7
-20
~Co
~ -15
,,,L
-;::
~
<'
.5.
4.19
MHz
:r
Q 3 3 PF
C
~
"
If'/V -
-10
(.)
S
S-
a
Ir
fe-roo."
~VOO=5V
.9
-5
o
'//
~~
o
2
VOO=3V
I
VOO-2.7V
3
VOO-VQH(V)
4-112
5
IOH vs Voo - VOH (Ports 0, 2, 3, 6)
101 PCC
X2
15PF~
VOO =3V
1
. /.....
Low-level output voltage VOL (V)
Power Supply Voltage Voo(V)
Xl
/'
5
o
f-Voo";sv
STOP mode (1000)
(When Power-on reset
circuit and Power-on
flag are on-chip.)
r-- Subsystem clock
o
1
--'
/'
10
1
1
r
VOOj4V
V
'/
I
~
10
!
V
50
5
~
~
i
G
100
Ul
~
V........... / "
15
~
~ode
Tl a 2Jc
"rfl I/~
~Co
~
t-- Low-speed mod
t--
I
VOO =6V
4
5
~EC
pPD7520x/7521x/75CG2xx/75P216A
DC Characteristics (J£PD752xx only) (cant)
100 vs VOO - VOO (TO - T15)
I OL vs VOL (Ports 4 and 5)
20
t
~
~vriO=6r
h
~I "~-'~l
10
0
~
J
!t
'IV
~
~...J
~
Voo= 2.7V
~
E
8
~
~ ~~4--1-+--+~~~~~4--+~
~VOO~3V
~
"
1!
,-Volo=5V
15
~
~
T1= 25Jc
'I
5
1/
0
2
4
3
!"
100 vs VOO - VOO (50 - 59)
-10
/
0
-5
'"
:E
o
~
o
t
V
~
<
g
VOO=4V
// ".--
:;
~
VOO-VpRE=10V /
1!
'li
Vvoo= V
-10
T~=25'C
I V /'
/
-5
~
t,t
/'
"....
2
3
'/
Ih y
c3
Yoo-13V
r
I
1.
VOO-VPRE= 4V_
".....-
I.~
o
5
V~-VprE='V
~~
i;'
~
is
4
~
J~ V
B
7
/voo- jPRE j 8V
i/ /'
c
9
E
~
5
4
3
10H vs VOO - VOH (Ports 4 and 5)
-voo=~
0
1
.c
2
Voo-Voo(V)
1!'li
:J:
II
5
Tl~25~
9
1---I-..u.Il--,,4--I--+--I-~I---I--+~
Low-level oUlput voltage VOL (V)
-20
~
-10
is
0
~ -15
-20
1/
o
2
3
4
5
Voo-Voo(V)
4-113
NEe
pPD7520x/7521 x/75CG 2xx/75P216A
Figure 4. Guaranteed Operating RIInge
flPD75CG20S/CG216A and
flPD75P216A
flPD752XX
40
40
32
3~~r::
32
~~
~r:
::::r:::
3~~r::
6
6
5
5
:u!"'~"""9
4
4
3
3
~r::
~~
~~
~r::
1'7 err
~r:
Ii
I
'"~,~,
Up";:~~'e
Ii
•••••••••••
2
2
,
,
~
~
~
~
0.5
2
3
4
5
Power Supply Voltage VDD (V)
4-114
6
7
~
0.5
o
~
2
3
4
5
Power Supply Voltage VDD (V)
6
7
t¥EC
JlPD7520x/7521 x/75CG 2xx/75P216A
Figure 5. AC Timing Measurement Points
Figure 7.
Serial Transfer Timing
Serial 1/0 Mode (3·Llne)
All Except X1 andXT1
1+----tKCY---~
tKL
0.75 VDD _
tKH
Measurement- 0.75 VDD
0.2 VDD - -
points
- . 0.2 VDD
SCK
tSIK
X1 and XT1
SI----!-~
tKSO
0.4 V
so
tKsl
Input Data
f_______---'x'--__
OUtput Data
83RD·7213A
Figure 8.
Interrupt Input Timing
0.4V
83RO-7211A
INTO,1,2,4
83RD-7214A
Figure 6.
TID Timing
Figure 9. RESET Input Timing
4-115
II
NEe
pPD7S20X/7521X/7SCG2xX/75P216A
Data Memory STOp· MOde Low Voltage Data Retention Characteristics
Mask ROM parts: TA = -40 to +85"0
Programmable parts: TA = -10 to + 70"C
Parameter
Symbol
Min
Data retention voltage
VOOOR
2.0
Data retention current (Note 1)
IOOOR
Release signal SET time
tSREL
Oscillation stabilization time (Note 2)
tWAIT
Typ
Max
Unit
VOomax
V
0.1
10
pA
VOOOR
10
200
pA
VOOOR
0
~
ms
Release by mET input
(Note 3)
ms
Release by Interrupt request
(1) Excludes the on-chlppull-down resistor and power-on reset
circuit (mask option) in the mask ROM parts.
(2) Consult the vendor's resonator specification for this value.
(3) Oscillation stabllizatlOl) WAIT time is the time during which the
CPU is stopped and the crystal Is stabilizing. This time Is
required to prevent unstable operation while the oscillation is
started. The Interval timer can be used to delay the" CPU from
executing Instructions using the setting of the basic interval
timer mode register (BTM) according to the following table:
4-116
BTM2
BTM1
BTMO
WAIT time (fxx
0
0
1
1
0
1
0
1
0
1
1
1
2?-O/txx
217/txx
215/txx
213/txx
= 2.0 V (,uPD752xx and ~PD75P216A)
= 2.0 V (,uPD75CG208ICG216A)
2171fx
Notes:
BTM3
Conditions
= 4.19 MHz)
(Approx 250 rns)
(Approx 31.3 ms)
(Approx 7.62 ms)
(Approx 1.95 ms)
NEe
pPD752Ox/7521 X/75CG 2xx/75P216A
Figure 10. Data Retention Timing
A. STOP mode Is released by RESET Input
Internal reset
operaHon
t:
VDD
I
II
STOP mode
HALT mode
I
I
Data retention mode _ _
t
VOOOR
Operation
mode
/
ExecuHon 01
STOP Instruction
\ "---J
tWAIT
_tSREL
II
B. STOP mode Is released by Interrupt signal
HALT mode
t:
VOO
t
Executional
STOP Instruction
Stand by release signal
(Inlerrupt request)
I
I
STOP mode
OperaHon
mode
Data retention mode _ _
VOOOR
/
tSREL
J
~
4-117
NEe
pPD752OX/7521 X/75CG 2xx/75P216A
DC Programming Characteristics (J£PD75P216A only)
TA
= 25 :!: 5°C; Voo = 6.0 :!: 0.25 V; Vpp = 12.5 ±0.3 V; Vss = 0 V
Parameter
Symbol
Max
Unit
High-level input voltage
VIHl
0.7Voo
Voo
V
All except Xl, X2
VIH2
Vo o-0.5
Voo
V
Xl, X2
VIL1
0
0.3Voo
V
All except Xl, X2
0
0.4
V
Xl, X2
10
p.A
VIN
V
IOH
Low-level input voltage
Min
VIL2
Input leakage current
IlL
High-level output voltage
VOH
Typ
Voo-l.e
Low-level output voltage
VOL
0.4
V
Voo supply current
100
30
mA
Vpp supply current
Ipp
30
mA
Conditions
= VIL or VIH
= -1 mA
IOL = 1.6mA
MDO
= VIL; MDl = VIH
Notes:
(1) Vpp must not exceed +22.0 V, including overshoot.
4-118
(2) Voo is to be applied prior to Vpp and to be removed after Vpp is
removed.
NEe
pPD752Ox/7521 x/75CG 2xx/75P216A
AC Programming Characteristics (,4PD75P216A only)
= 25 ± 5'C; Voo = (t.0 ± 0.25 V; Vpp = 12.5 ± 0.3 V; Vss = 0 V
TA
Parameter
Symbol
Address setup time (Note 2)
tAS
Typ
Max
Unit
EPROM Symbol (Note 1)
Min
tAS
2
/,S
MDI to MDO J, setup
tM1S
tOES
2
/,S
Data to MDO J, setup
tos
tos
2
/,S
Address hold from MDO f (Note 2)
tAH
tAH
2
/'S
Data hold from MDO f
tOH
tOH
2
I'S
Data output float delay from MDO f
tOF
tOF
0
Vpp setup to MD3 f
tvps
tvps
2
VOO setup to MD3 f
tvos
tvcs
2
Initialized program pulse width
tpw
tpw
0.95
1.05
ms
Additional program pulse width
topw
topw
0.95
21
ms
tCES
2
MDO setup to MDI f
tMOS
Data output delay from MDO J,
tov
130
Conditions
ns
/'S
/'S
I'S
tov
/,S
MDO
= MDI = VIL
+
+
MDI hold to MDO f
tM1H
tOEH
2
I'S
tM1H
MDI recovery from MDO J,
tM1R
tOR
2
/'S
tM1H
Program counter reset
tpCR
10
I'S
Xl input high/low level width
tXH' tXL
Xl inputfrequency
fxx
0.125
tM1R '" 50 liS
tM1R '" 50 liS
/los
4.19
MHz
Initial mode set
tl
2
/,S
MD3 Setup to MDI f
tM3S
2
/,9
MD3 hold to MDI J,
tM3H
2
/,S
MD3 setup to MDO J,
tM3SR
2
I'S
Address ...... data output delay time (Note 2)
tOAD
tACC
2
/,S
Address ...... data output hold time (Note 2)
tHAD
tOH
0
MD3 output hold from MDO f
tM3HR
2
/,S
Data output float delay from MD3 J,
tOFR
2
liS
130
During program read cycle
ns
Notes:
(1) These symbols correspond to those of the /,PD27C256 EPROM.
(2) The internal address signal is incremented by the rising edge of
the fourth Xl pulse; it is not connected to an external pin.
4-119
II
pPD7S2Oxns21xnsCG2xxJ7SP216A
Figure 11.
NEe
OTP Memory Write Timing (Programmable)
tvps
vpp
vpp
~--------------~G~--------------------~S~
VDD
tVDS
~~------------~S~--------------------~5~
X1
83RO-e836B
4-120
t-fEC
Figure 12.
pPD7520x/7521 x/75CG 2xx/75P216A
OTP Memory Read Timing (Programmable)
tvps
Vpp
vpp
vDD
tVDS
Xt
~~g:~~; --+-+----<1
Data OUtput
Data Output
;~
1 ' - - - - - - - " "'--_ _---J '------',~tDFR
tDV
MDO
MDt----+--+------------------------~r-~~---
MD2
t M3SR
MD3
83RD-6461B
4-121
pPD7520x/7521 X/7.5CG 2xx/75P216A
4-122
NEe
NEG Electronics Inc.
Description
The Il-PD75268 is a low-cost, high-performance, singlechip CMOS microcomputer containing CPU, ROM, RAM,
I/O ports, several timer/counters, a FIP controller, vectored interrupts, main and subsystem clocks, and serial
interface. The devices are ideally suited for controlling
VCRs, microwave ovens, electronic stoves, washing machines, electronic cash registers, audio equipment, and
meters.
(For the programmable equivalents, use Il-PD75CG 216 or
Il-PD75P216A.)
pPD75268
4-Bit Microcomputer
With FIP® (VF) Controller/Driver
o 8-bit serial interface
- Data transfer can be full duplex or receive only,
and can be MSB or LSB first
o Vectored interrupts
- Three external interrupts
- Four internal interrupts
o Two interrupt requests
o Standby modes
- HALT mode: stops CPU only
- STOP mode: stops main system clock
o Operates with oscillator or ceramic resonator
Features
o CMOS technology, with VDD from 2.7 to 6.0 V
o 103 instructions
- Bit manipulation
- 4-bit add and subtract
- 4-bit and 8-bit transfer
- GETI instruction, to convert one 2-byte or two
1-byte instructions into a single 1-byte instruction
- 1-byte relative branch
Ordering Information
Part Number
Package Type
ROM
"PD75268CW-xxx
64-pin plastic SDIP
Mask ROM
"PD75268GF-xxx-3BE
64-pin plastic QFP
Mask ROM
Note:
xxx indicates ROM code.
o Fast execution time (@ 4.19 MHz)
- High-speed cycle: 0.95 Il-S
- Lower-voltage cycles: 1.91 and 15.3 Il-S
o 8064 bytes of program ROM
o 512 x 4 bits of program RAM
o Eight 4-bit registers
o 32 port lines
- 20 general-purpose I/O, 8 outputs directly drive
LEDs (lsink = 15 rnA rms)
- 8 input-only lines
o Three timers
- 8-bit basic interval timer
- 8-bit timer/event counter
- 14-bit watch timer with buzzer output
o Programmable FIP controller with memory area
- Up to 16 segments
- Up to 16 digits
FIP is a registered trademark of NEC Corporation
50211
4-123
II
ttfEC
"PD752G8
Pin Configurations
tu-I'In SDIP
voo
S3
52
Sl
S5
so
sa
POofINT4
P01ISCK
P02fSO
PO:3/s1
P10/INTO
Pll/INT1
P12/INT2
PlI lTIO
P20
P21
P22
P2aIBUZ
S7
P30
P31
P32
P3a
P60
P61
P62
PBs
P4Q
P41
P42
P43
NC
Xl
X2
Vss
S4
sa
S9
VpRE
VLOAO.
T151S10
T14/S11
Tl31S121PI-'o
T121S131PHl
Tll/S14/P1i2
T10/SlS/PH:!
T9
T8
T7
T6
T5
T4
T3
T2
Tl
TO
RESET
PSa
P52
PSl
P50
XT2
XTl
83RD-6557A
4-124
NEe
pPD75268
Pin Configurations
64-PlnQFP
~~~~~
~1
••
«.~~~~~~~$M~
~
~
P42
P43
NC
P01/5CK
POO/INT4
so
51
52
53
XI
VDD
54
55
56
57
58
59
o
2345678
II
83R().6558B
Pin Identification
Symbol
Function
Symbol
Function
POoflNT4
Port 0 Input; Interrupt 4
T14/S11
T15/S10
Digit selects T14 and T15; segment selects S10 and
Sll.
Port 0 Input; serial clock
P~/SO
Port 0 input; serial out
POa/SI
Port 0 Input; serial In
Plof1NTO
Port 1 input; Interrupt 0
Port 1 input; interrupt 1
P1i1NT2
Pla/TIO
Port 1 Input; Interrupt 2
Port 1 Input; timer 0 Input
Port 21/0
P2a/BUZ
Port 2 I/O; buzzer output
Port 31/0
Port 41/0
Port 51/0
Port 61/0
PHoIT13/S12
Port H output; digit select line; segment select line
Port H output; digit select line; segment select line
Port H output; digit select line; segment select line
PHa/T101S15
Port H output; digit select line; segment select line
S0-59
FIP segment outputs
TO-T9
FIP digit select outputs
Xl, X2
Main clock Inputs
XT1,XT2
Subsystem clock Inputs
VPRE
FIP predrlver negative supply voltage
VLOAD
FIP high-voltage negative supply voltage
Reset Input
Voo
Positive power supply
V55
Ground
PIN FUNCTIONS
POo/INT4, P01/SCK, P~SO, POafSI
These pins can be used as 4-bit input port O. Or, POo can
also be used for vectored interrupt 4, which interrupts on
either the leading edge or the trailing edge of the signal.
P01-P03 may also be used for the serial interface in the
2/3 wire mode. SI Is the serial input, SO is the serial
output, and SCK is the serial clock. Reset causes these
pins to default to the port 0 input mode.
4-125
NEe
pPD75268
P1o/1NTO, P11/INT1, P1z/INT2, P13IT10
TO-T9
These pins can be used as 4-bit input port 1. Or, P10 and
P1, can also be used for edge-triggered interrupts INTO
and INT1. P12 can be used for INT2, which is also an
edge-triggered input, but one which generates an Interrupt request and does not cause an interrupt. P1s can be
used as an input clock to the timer/event counter to
count external events. Reset causes these pins to default to the port 1 Input mode.
These are high-voltage outputs used as FIP controller
digit select timing signals. pulldown resistors Can be
selected as a mask-option. A reset signal sets these pins
to the high-impedance state; if mask-option resistors are
present the outputs go low.
P20,P21,P22'P~
These pins can be used as 4-bit I/O port 2. When used as
an output, the data Is latched. When used as an input
port the port outputs are three-state. P2s can also be
used to output square waves for a buzzer. Reset causes
these pins to default to the port 2 input mode.
P30.p33, P4o-P43, P5o-P53
Ports 3, 4, and port 5 are 4-bit I/O ports with latched
outputs. Ports 4 and 5 will directly drive LEOs. Each bit of
port 3 can be independently programmed to be either an
input or an output, while ports 4 and 5 can be programmed to be either an input port or an output port. A
reset Signal causes these ports to default to the input
mode.
T14/S11, T15/S10
These two pins provide additional digit or segment
selectors. When not used for the display they can be
used as static outputs. Internal pulldown resistors are
available as a mask option.
X1,X2
These pins are the main system clock inputs. The clock
can be either a ceramic resonator or a crystal; an
external logic signal may also be used.
XT1,XT2
These pins are the subsystem clock inputs. The clock
can be either a ceramic resonator or a crystal; an
external logic signal may also be used.
RESET
This is the reset Input, and it is active low.
P60-P63
Port 61s a 4-blt I/O port. Outputs are latched, and each
bit can be independently programmed to be either an
Input or an output. Port 6 can have pulldown resistors
added as a mask option. A reset signal causes this port
to default to the input mode.
PHo/T13/S12, PH1/112/S13, PH:zIT11/S14,
PH3fT10/S15
Port H Is a 4-bit output-only port, with P-channel opendrain outputs capable of directly driving LEOs. Output
pulldown resistors can be selected as a mask-option.
Alternatively, these pins can be used as high-voltage
digit/segment outputs (T13/S15 - T10/S12). A reset signal
causes this port to default to the high-impedance state;
if mask-option resistors are present the output goes low.
$0-S9
These are high-voltage outputs used asFIP controller
segment Signals. pulldown resistors can be selected as a
mask-option. A reset signal sets these pins to the hlghImpedance state; if mask-option resistors are present
the outputs go low.
4-126
VPRE
This is the power supply for the predrivers of the FIP
controller.
VLOAD
This pin is used to supply power to the output drivers for
the segment and digit select pins of the FIP controller.
VDD
The system positive power supply pin.
Vss
System ground.
NEe
pPD75268
Block Diagram
4-127
t-IEC
pPD75268
ELECTRICAL SPECIFICATIONS
Absolu~e
TA = 25"C
Maximum Ratings
-0.3 to +7.0 V
Supply wltage, Voo
Supply wltage, VUlAO
Voo -40 to Voo +0.3 V
Supply wltage, VPRE
Voo -12 to Voo+0.3'V
Low-Ievel output current, IOL
(sfl'lgle pin)
17 rnA
Low-Ieve/ output current, IOL
(total of aU pins)
60mA
Input wltage, VIN
-0.3 to Voo + 0.3 V
Power dissipation,
Output wltage, Vo (other than display)
-0.3 to Voo + 0.3 V
Power dissipation,
Output wltags, Voo (display pins)
Voo -40 to Voo +0.3 V
High-level output current, IOH
(single pin; other than display)
-15 rnA
High-level output current, IOH
(elngle pin; 80-89)
-15 inA
High-level output current, IOH
(single pin; 1O-T15)
-SOmA
High-level output current, IOH
(total of ,III, pins other than display)
-20mA
High-level output current, IOH
(total of all display outputs)
Po (plastic QFp)
Po (plastic SDIp)
450 mW (Note 1)
600 mW (Note 1)
Storage temperature, tsrG
-85 to + 150"0
Operating temperature, tOPT
-4Oto +85"C
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent
damage. The device 8hculd be operated within the limits apeclfled
under DC and AC Characterlatlca.
Note.:
-120mA
(1) Care must be taken whIm designing the mICrocomputer that the,
total power dissipation does not exceed the maximum allowable.
Power Is dissipated In three areas:
a. At the CPU. Po Is calculated by the product of Voo (max)
and I001(max).
b. By the output pins. '/btal power dissipation Is the sum of the
values for each pin when maximum current Is applied.
c. By the pulldown resistors.
Main System Clock Oscillator Characteristics
TA .. -40 to +85"C; voo .. 2.7 to 6.0 V
Oaclllator
Parameter
Ceramic resonator
(FIgure 1A)
Oscillation frequency (Note 1)
Crystal resonator
(FIgure 1A)
Oscillation frequency (Note 1)
External clock
(FIgure 18)
Symbol
Min
fxx
2.0
fxx
2;0
Typ
Oscillation stabilization time (Note 2)
Oscillation stabilization time (Note 2)
X1 Inputfrequency
X1 Input hlgh- and low-level width
fx
txH, tlCL.
4.19
Max
Unit
5.0
MHz
4 (Note 3)
ms
5.0
MHz
10 (Note 3)
ms
30 (Note 3)
ms
2.0
5.0
MHz
100
250
ns
Condition.
Voo .. 4.5 to 6.0 V
Notea:
(1) The oscillation frequency and X1 Input frequency are Included
only to show the frequency range of the oscillators. Refer to the
AC Characterlstlce table for actual Instruction execution times.
(2) The oscillation stabilization time Is the time required for the
oscillator to stabillzeaftsr Voo Is applied or the STOP mode Is
released.
4-128
(3) Valuss shown are typical values for resonators. Actual values
should be obtained from the manufacturer's specification
sheets.
NEe
pPD75268
Subsystem Clock Oscillator Characteristics
TA = -40 to +85°C; Voo = 2.7 to 6.0 V
Oscillator
Parameter
Symbol
Min
Typ
Max
Unit
Crystal resonator
(FIgure 2A)
Oscillation frequency (Note 1)
fxr
32
32.768
35
kHz
External clock
(FIgure 28)
Oscillation stabilization time (Note 2)
1.0
2 (Note 3)
s
10 (Note 3)
s
XT1 Input frequency
fxr
32
100
kHz
XTl Input high- and low-level width
IxTH. IxTL
10
32
""
Notes:
(1) The oscillation frequency and Xl Input frequency are Included
only to show the frequency range of the oscillators. Refer to the
AC Characteristics table for actual Instruction execution times.
Conditions
Voo = 4.5 to 6.0 V
(3) values shown are typical values for resonators. Actual values
should be obtained from the manufacturer's specification
sheeta.
(2) The oscillation stabilization time Is the time required for the
oscillator to stabilize after Voo Is applied or the STOP mode Is
released.
Figure 1. Mllin System Clock Conflgurlltloll8
II
Figure 2. Subsystem Clock ConfigurlltlOll8
A. Crystal Resonator
A. Ceramic/Crystal Resonator
.--_--IXT1
~~
T
\l33PF
'---~-IX2
XT2
330
kG
B. External Clock
B. External Clock
.;>0_.----1
*
X1
»--~-IXT1
X2
Open- XT2
~P074HCU04
83RD-6443A
83RD-6444A
4-129
NEe
pPD75268
Capacitance
Operating Supply Voltage
voo = OV;TA = 25°C
TA
Parameter
Symbol
Input capacitance
Min
Max
Unit
~N
15
pF
Output capacitance;
Other than display
output pins
Coun
15
pF
Output capacitance;
Display output pins
COUT2
35
pF
1/0 capacitance
CIO
15
pF
Conditions
= -40 to
+85°C
Parameter
Min
Max
Unit
(Note 2)
6.0
V
Display controller
4.5
6.0
V
Other hardware (Note 1)
2.7
6.0
V
CPU (Note 1)
=
f
1 MHz
All unmeasured
pins returned
to ground
Notes:
(1) The CPU does not Include the system clock oscillator and the
display controller.
(2) Varies according to the cycle time. See AC .Characterlstlcs.
DC Characteristics
TA
= -40 to
+85°C; voo
= 2.7 to 6.0 V
Typ
Parameter
Symbol
Max
Unit
High-level Input voltage
V.Hl
0.7Voo
Voo
V
VIH2
0.75Voo
Voo
V
Ports 0 and1;.RESET
VIH3
Voo-0.4
Voo
V
X1, X2, XTt
VIH4
O.65Voo
Voo
V
Port 6; Voo
0.7Voo
Voo
V
Port 6; Voo
VILl
0
0.3Voo
V
All except ports 0,1, and 6; RESET; X1, X2, XTt
VIL2
0
0.2Voo
V
Ports 0, 1 and 6; RESET
VIL3
0
0.4
V
X1, X2,XTt
VOH
Voo-1.0
V
All outputs; Voo
Voo-0.5
V
All outputs; Voo
Low-level Input voltage
High-level output voltage
Low-level output voltage
Min
0.4
VOL
2.0
V
0.4
V
Conditions
All except ports 0 and 1; RESET; X1, X2, XT1
= 4.5 to 6.0 V
= 2.7 to 6.0 V
= 4.6 to 6.0 V; 10H = -1 rnA
= 2.7 to 6.0 V; 10H = -100 IlA
Ports 4 and 5; Voo = 4.6 to 6.0 V; 10L = 15 rnA
All output pins; Voo = 4.6 to 6.0 V; 10L = 1.6 mA
All output pins; Voo = 2.7 to 6.0 V; 10L = 400 pA
All exceptX1, X2, and XT1; VIN =Voo
X1, X2, and XT1; VIN = Voo
All except X1, X2, and XT1; VIN = 0 V
X1, X2, and XT1; VIN = 0 V
All output pins; VOUT = Voo
All except display output pins; VOUT = 0 V
0.5
V
ILIHl
3
p.A
ILIH2
20
p.A
ILILl
-3
p.A
ILIL2
-20
p.A
High-level output leakage current
ILOH
3
p.A
Low-level output leakage current
ILOL 1
-3
p.A
ILOL2
-10
p.A
Display output pins;
VOUT = VLOAO = Voo-35 V
High-level Input leakage current
Low-level input leakage current
Display output current
4-130
100
-3
-5.5
rnA
SO - S9; (Note 1) and Recommended External
Circuit (figure 3)
-1.5
-3.5
rnA
SO -89; (Note 2)
-15
-22
rnA
TO - T15; (Note 1) and Recommended External
Circuit (figure 3)
-7
-15
rnA
TO - Tt5; (Note 2)
ttlEC
pPD75268
DC Characteristics (cont)
Parameter
Symbol
Internal pulldown reslltor
(mask option)
RP6
Min
Typ
Max
Unit
20
80
200
kO
1000
kO
Port 6; Voo '" 2.7 to 6.0 V; VIN - Voo
70
135
kO
Display output pins; VOo-VLOAO - 35 V
20
25
Supply current
(Note 6)
Condition.
Port 6; Voo '" 4.5 to 6.0 V; VIN .. Voo
= 5 V :I: 10'11> (Notes 3, 4)
= 3 V :I: 10'11> (Notes 3, 5)
3.0
9.0
rnA
Yeo
0.65
1.5
rnA
Voo
800
1800
800
1003
40
120
1004
5
15
/IA
/IA
/IA
pA
HALT mode; Voo .. 5 V :I: 10% (Note 3)
200
10DS
0.5
20
/IA
STOP mode; XT~ .. OV; Voo .. 5 V :I: 10 'II>
0.1
10
pA
STOP mode; XT1 '" OV; Voo
1001
1002
HALT mode; Yeo '" 3 V :I: 10% (Nete 3)
Voo .. 3 V :I: 10'11> (Notel 7, 8)
HALT mode; Yeo .. 3 V :I: 10% (Notes 7, 8)
= 3 V :I: 10 'II>
Nota.:
(5) value durlnglow-speed operation; processor control clock (POC)
Is set to 0000.
(1) Voo - 4.5 to 6.0 V; Voo '" Voo -2 V; VPRE '" Voo -9:1:1 V
(2) Voo .. 4.5 to 6.0 V; Veo .. Voo -2 V; VPRE .. 0 V
(3) 4.19 MHz crystal oscillator, C1 .. C2 .. 15 pF.
(6)' Does not Include Internal pulldown reslltor current.
(7) 32 MHz crystal oscillator
(8) value when the system clock control register (SCC) II set to 1001,
(4) value during hlgh-epeed operation; processor control clock
(pCC) II set to 0011.
main system clock Is ItOpped, and the lubsystem clock operates
the chip.
PIC Characteristics
TA .. -40 to +85"C; voo
= 2.7 to 6.0 V
Min
Cycle time
minimum Instruction execution time -
tcv
Max
Unit
32
pi
CPU using main system clock;
voo '" 4.5 to 6.0 V
3.8
32
pi
CPU using main system clock;
Voo ",'2.7 to 6.0 V
125
pi
CPU using lubayatem clock;
Voo '" 2.7 to 6.0 V
0.6
MHz
Vpo .. 4.5 to 6.0 V
165
kHz
" Voo .;. 2.7 to 6.0, V
(Note 1)
114
TIO Input frequency
fori
TIO Input high- and Iow-Ievel width
~cycletlme
~ high- and Iow-Ievel width
Typ
0.95
lKcv
o
o
122
Condition.
0.83
pi
Voo - 4.5 to 6.0 V
3
pi
Voo = 2.7 to 6.0 V
0.8
pi
Input; Voo
0.95
pi
Output; Voo '" 4.5 to 6.0 V
3.2
pI
Input; Voo '" 2.7 to 6.0 V
3.8
pi
Output; Voo
0.4
pi
Input; Voo
= 4.5 to 6.0 V
0.5iKcr50
ns
= 2.7 to 6.0 V
= 4.5 to 6.0 V
Output; Voo = 4.5 to 6.0 V
1.6
pi
Input; Voo = 2.7 to 6.0 V
0.5tl(Cy-150
ns
Output; Voo '" 2.7 to 6.0 V
4-131
II
NEe
pPD75268
AC Characteristics (cont)
Parameter
Symbol
Min
SI to ~ i setup time
tSIK
100
SI to ~ i hold time
~I
400
~ ,J. to SO output delay time
~o
Interrupt Inputs
low- and high-level width
tlNlH,
tlNTL
mE'I' low-level width
tRSL
Typ
Max
Unit
Conditions
ns
ns
300
ns
VOO = 4.5 to S.O V
1000
ns
VOO = 2.7toS.OV
(Note 2)
p.S
INTO
2tCY
p.S
INT1
10
p.S
INT2,INT4
10
p.S
Notes:
(1) Cycle time Is determined by the frequency of the oscillator
connected to the microcomputer, system clock control register
(SCC), and the processor clock control (PCC). See the graph
depicting the Supply Voltage to the cycle time (fIgure 4) when the
microcomputer Is operating on the main system clock.
(2) 2tcY or 128/1xx, depending on the setting of the Interrupt mode
regl ster OMO).
Data Memory STOP Mode Low Voltage Data Retention Characteristics
TA = -40 to +85°C
Parameter
Symbol
Min
Data retention voltage
VOOOR
2.0
Data retention current
IOOOR
Release signal SET time
tsREL
Oscillation stabilization tll1"e (Note 2)
tWAfT
Typ
0.1
0
Max
Unit
S.O
V
10
/loA
Conditions
VOOOR = 2.0 V (Note 1)
p.S
(2)
ms
Release by mET Input
(2)
ms
Release by Interrupt request
Notes:
(1) Excludes current In the Internal pull down resistors.
(2) Oscillation stabilization WAIT time Is the time during which the
CPU Is stopped and the crystal Is stabilizing; consult the vendo~s resonator or crystal specifications sheet for this value. This
time is required to prevent unstable operation while the oscillation is started. The interval timer can be used to delay the CPU
from executing instructions using the basic interval timer mode
register (BTM) according to the following table:
BTM3
BTM2
o
o
1
1
4-132
BTM1
BTMO
o
1
o
o
1
1
1
1
WAIT time
2,20/fxx (Approx 250 ms)
217!fxx (Approx 31.3 ms)
215!fxx (Approx 7.82 ms)
213!fxx (Approx 1.95 ms)
Figure 3. Recommended Externa' Circuit
VOO
+5V
R09.1EL
~ ( ' 8.29·9.3V
VpRE
681<0
VLOAO
-30V
GNOn
83RO-6559A
t'tIEC
pPD75268
TIMING WAVEFORMS
Figure 4. GUllranteed Operating RIInge
tcvvsVoo
AC Timing lIellSurement Point.
(Excluding X1 and XT1 input pins)
(Operation on main system clock)
40
32
~~P:
:::~
0.75 VOD--- Measurement _0.75 VOO
:::~
::::=::
0.2 VOO -
points
- - 0.2 VOO
6
83RD-s457A
5
ng
Clock Timing
4
3
II
2
1
83RD-6714A
0.5
°
2
3
4
5
6
I
110 Timing
7
Power Supply Voltage VOO (V)
83R0-6458A
Serial Transfer Timing
tKCY
I+-tKL-+ f - t K : j
-SCK
\
tSIK
SI
',00_
so
f
"'"
tKSI
Input Oata
OulputOata
X
83RD-6712A
4-133
ttiEC
pPD75268
,
1fESi!'f Input 71""ng
Interrupt Input TImIng
INTO,1,2,4
83RD-I713A
"'t. Retention TIming
A. STOP mode Is released by RESET Input
Internal reset
operation
I
t:
I
I
STOP mode
VDDDR
I
I
Data retenUon mode _ _
t
HAlT mOde
OperaUon
mode
/
ExewUonof
STOP Instruction
\
>0......1
_tSREL
tWAIT
B. STOP mode Is released by Interrupt signal
HALT mode
t:
_
t
. ExewUon of
STOP Instruction
Standby release signal
(Interrupt request)
4-134
I
ss------STOPmode _ _ _ _ _ _ _--I~_I--I~- ~:uon
Data retention mode
VDDDR
tSREL
NEe
pPD7530x/31X/P308/P316
4·Bit Microcomputers
With LCD Controller/Driver
NEG Electronics Inc.
Description
The pPD753Ox/31x is a family of high-performance
single-chip CMOS microcomputers containing CPU,
ROM, RAM, I/O ports, several timer/counters, vectored
interrupts, subsystem clock, and serial interface.
The instruction set allows the user to manipulate RAM
data and I/O ports in 1-, 4-, and 8-bit units. The devices
are ideally suited for controlling VCRs, telephones,
meters, handheld instruments, and devices with LCDs.
Development tools include a low-cost in-circuit emulator, relocatable assembler, and C-like structured assembler.
Both EPROM and OTP versions are available. See ordering information.
Features
o 103 instructions
- Bit manipulation
-4-bit and 8-bit transfer
-1-byte relative branch
- GETI instruction converts one 2-byte/3-byte or
two 1-byte instructions into a single 1-byte
instruction
o Fast execution time
(Main system clock @ 4.19 MHz)
- High-speed cycle: 0.95 ps
- Lower-voltage cycles: 1.91 and 15.3 ps
o Program ROM
- /.lPD75304: 4096 bytes
-pPD75306: 6016 bytes
- pPD75308/P308: 8064 bytes
-pPD75312: 12160 bytes
- pPD75316/P316/P316A: 16256 bytes
o Data memory (RAM)
-512x 4 bits
- Allows operation on 1, 4, or 8 bits
o Bit sequential buffer
-16-bit, bit manipulation memory
o Eight 4-bit registers or four 8-bit registers
o Accumulators
-1-bit (CY)
-4-bit (A)
-8-bit (XA)
o 241/0 lines
50244
-All outputs directly drive LEDs
(Is ink = 15 mA rms)
- 8 N-channel open-drain, can withstand 10 V
- 8 input-only lines
o One external event input
o Subsystem clock allows watch timer and LCD
controller to operate in STOP mode
o Three timers
- 8-bit basic interval timer
- 8-bit timer/event counter
-14-bit watch timer
o LCD controller/driver
- 32 segment lines
- 4 common lines
-4 operating modes: static; multiplexed 1/2 bias;
triplexed 1/2 or 1/3 bias; quadruplexed 1/3 bias
- LCD resistor ladder available as a mask option
o 8-bit serial interface
-SBI mode
- 2- or 3-wire mode: Data transfer can be full
duplex or receive only, and can be MSB or LSB
first
o Vectored interrupts
- Three external interrupts
- Three internal interrupts
- Nine inputs which generate an interrupt request
o Standby modes
- HALT mode: stops CPU only
- STOP mode: stops main system clock
o Optional pull up resistors
- By software: 23 lines
- By mask option: 8 lines
o Operates with oscillator or ceramic resonator
o CMOS operation, with Voo from 2.7 to 6.0 V
o Programmable versions
-
OTP & EPROM: pPD75P308
OTP: pPD75P316
OTP, low voltage: pPD75P316AGF (Note)
EPROM, low voltage: pPD75P316AK (Note)
o Low operating current (@5 V and 4.19 MHz)
- Normal operation: 2.5 mA typical
- HALT mode: 0.5 mA typical
- STOP mode: 0.1 mA typical
Note: Low voltage target spec of 2.7 to 6.0 V operation.
Contact your local NEC Sales Office for latest information; none of the electrical specifications in this
data sheet directly apply to these parts.
4-135
II
t-{EC
pPD753Ox/31x/P308/P316
Ordering Information
Part Number
Package Type
ROM
Part Number
Package Type
ROM
"PD75304GF-xxx-3B9
SO-pin plastic QFP
Mask ROM
"PD75316GF-xxx-3B9
SO-pin plastic QFP
Mask ROM
"PD75306GF-xxx-3B9
SO-pin plastic QFP
Mask ROM
"PD75P316GF-3B9
SO-pin plastic QFP
OTP
"PD75308GF-xxx-3B9
SO-pin plastic QFP
Mask ROM
"PD75P316AGF-3B9
SO-pin plastic QFP
"PD75P30SGF-3B9
SO-pin plastic QFP
OTP
Low
voltage
OTP
"PD75P30SK
SO-pin ceramic Lee
w/Window
EPROM
"PD75P316AK
SO-pin ceramic Lee
w/Window
"PD75312GF-xxx-3B9
SO-pin plastic QFP
Mask ROM
Low
voltage
EPROM
Notes:
(1) xxx indicates ROM code suffix.
Pin Configurations
~ ~ ~ ~ ~ ~ ~ ~ ~ ~
S12
0
R mm~
~ ~
64
P70/KR4
P63/KR3
P62/KR2
61
P61/KR1
60
P60/KRo
59
X2
X1
NC orVpp
XT2
S21
XT1
S22
VDD
P33/MD3 t
P32/MD2 t
S23
S24/BPO
S25/BP1
51
P31/SYNC/MD1 t
S26/BP2
50
P30 ILCDCLlMDO t
S27/BP3
49
P23/BUZ
S26/BP4
P22/PCL
S29/BP5
P21
S3Q/BP6
P20/PTOQ
S31/BP7
P131T10
COMO
P12/1NT2
COM1
COM2
P11I1NT1
P10/lNTO
COM3
P03/SI/SB1
• Pin 57 is Vpp in the programmable package. Connect this pin to VDD in the fLPD75P306/P316/P316A.
t MDO-MD3 are used as the programming mode selection pins on the fLPD75P306/P3161P316A during EPROM and OTP programming and verification.
49NR-5S2B
4-136
NEe
pPD7530x/31x/P308/P316
Pin Identification
Symbol
Function
Symbol
Function
BIAS
LCD power bias output
VLC1
LCD drive level 1
BPoIS24
BP1/S25
BP2/S26
BPa/S27
BP4fS28
BP&'S29
BPelS30
BP7/S31
1-bit output ports BPo-BP7;
LCD segments S24-831
VLC2
LCD drive level 2
Xl, X2
Main clock inputs
XT1, XT2
Subsystem clock inputs
COMO-COM3
LCD Common output 0-3
NCIVpp
No connection (programming pin for
POoIINT4
Positive power supply
Vss
Ground
PIN FUNCTIONS
~PD75P308/P316/P316A)
POo/lNT4, P01/SCK, P02/S0/SBO, POa/SI/SB1
Port 0 input; interrupt 4
These pins can be used as 4-bit input port o. POo can
also be used for vectored interrupt 4, which interrupts on
either the leading edge or the trailing edge of the signal.
P01-P03 may also be used forthe serial interface. SI is
the serial input, SO is the serial output, and SCK is the
serial clock. Reset causes these pins to default to the
port 0 input mode.
Port 0 input; serial clock
Port 0 input; serial out
POa/SI/SB1
Port 0 input; serial in
P1of1NTO
Port 1 input; interrupt 0
P21/1NT2
Port 1 Input; interrupt 2
P1a/T10
Port 1 input; timer 0 input
P2ofPTOo
Port 2 I/O; timer/event counter output
P21
Port 21/0
Port 1 input; interrupt 1
P22/PC L
Port 2 I/O; clock output
P2a/BUZ
Port 2 I/O; buzzer output
P301LCDCL/MDO
Port 3 I/O; LCD clock output; programming
mode select 0 (p.PD75P308/P3l6/P3l6A)
P31/SYNC/MDl
Port 3 I/O; SYNC output; programming mode
select 1 (p.PD75P308/P316/P3l6A)
P~/MD2
Port 3 I/O; programming mode select 2
(p.PD75P308/P3l6/P3l6A)
P3a/MD3
Port 3 I/O; programming mode select 3
(p.PD75P308/P3l6/P3l6A)
P40-P43
Port 4 I/O
P50-P53
Port 5 I/O
P601KRO
Port 6 I/O; key scan input 0
P61/KR1
Port 6 I/O; key scan input 1
P~KR2
Port 6 I/O; key scan input 2
P6a/KR3
Port 6 I/O; key scan input 3
P701KR4
Voo
P10/INTO, P11/INT1, P12fINT2, P1a/TIO
These pins can be used as 4-bit input port 1. P10 and P1l
can also be used for edge-triggered interrupts INTO and
INT1. P12 can be used for INT2, which is also an
edge-triggered input, but one which generates an Interrupt request and does not cause an Interrupt. P13 can be
used as an input clock to the timer/event counter to
count external events. Reset causes these pins to default to the port 1 input mode.
P20/PTOO, P21, P22/PCL, P2a/BUZ
These pins can be used as 4-bit I/O port 2. When used as
an output the data is latched. When used as an input port
the port outputs are three-state. P20 can also be used as
the output of the timer/event counter flip flop (TOUT);
P22 can be used as the output (PCL) for the clock
generator; and P23 can be used to output square waves
for a buzzer. Reset causes these pins to default to the
port 2 input mode.
Port 7 I/O; key scan input 4
Port 7 I/O; key scan input 5
Port 7 I/O; key scan input 6
P7a/KR7
Port 7 I/O; key scan input 7
Reset input
S0-823
LCD segment output
LCD drive level 0
4-137
..
...
NEe
pPD753Ox/31X/P308/P316
P30/LCDCLlMDO, P31/SYNC/MD1, P3a/MD2,
P33/MD3·
These pins are used for I/O Port 3. Each bit in this port
can be independently programmed to be either an input
or an output. This port has latched outputs, and can
directly drive LEOs.P3o and P3l can also be used
respectively as LCD clock and LCD sync outputs. P30P33 are used as the programming mode select pins for
the p.P075P30SIP316/P316A during EPROM/OTP programming and verification. A reset signal causes this
port to default to the input mode.
P40-P43, P50-P53
Port 4 and Port 5 are identical 4-bit I/O ports which can
be combined together to function as a single S-bit port.
Latched outputs will directly drive LEOs. Outputs are
N-channel open drain, and can withstand up to 10 volts;
pull-up resistor mask options are available for these
ports. A reset signal causes these ports to default to the
input mode.
P6ofKR0, P61/KR1, PS2IKR2, P6a1KR3
P7ofKR4, P71/KR5, P721KR6, P7a1KR7
Ports 6 and 7 are 4-bit I/O ports which can be combined
together to function as a single S-bit port. Outputs are
latched. Each pin of port 6 can be independently programmed to be either an input or an output, while port 7
can be programmed to be either all inputs or all outputs.
Alternately, these pins may be used to detect the falling
edge of inputs KRO - KR3 (port 6) and KR4 - KR7 (port 7).
A reset signal causes these ports to default to the input
mode.
SO-S23
Thes.e are the LCD segment drivers.
COMO-COM3
These are the LCD common input drivers.
BPoIS24-BP7/S31
The.se can be used either as eight 1-bit ports or as
additional LCD segment drivers. When used as segment
outputs they are selectable in 4-bit increments.
4":13S
VLCO-V LC2
These pins are used to set the drive levels for the LCD. If
the internal resistor ladder mask option is selected,
these pins are outputs; if .the internal resistor ladder is
not selected, these pins are inputs to which an external
resistor network must be connected.
BIAS
Thes output is used in conjunction with the VLCO - VLC2
pins to set the LCD contrast level.
NCNpp
This pin may be left unconnected when using the
p.P07530x/31x. For the p.P075P30S/P316IP316A, this pin
is used as the programming voltage input during the
EPROM write/verify cycles. When the devices are not
being programmed, this pin should be connected to Voo.
X1,X2
These pins are the main system clock inputs. The input
can be either a ceramic resonator or a crystal; an
external logic signal may also be used.
XT1,XT2
These pins are the subsystem clock inputs. The input can
be either a ceramic resonator or a crystal; an external
logic signal may also be used.
RESET
This is the reset input, and it is active low.
Voo
The system pOSitive power supply pin.
Vss
System ground.
NEe
IIPD7530x/31x/P308/P316
Block Diagram
POO-P03
P10-P13
P2o-P23
TI0/P13
P3o-P33 *
MDO-MD3
PTOO/P20
P40-P43
BUZlP2 3
P50-P53
ROM
Program Memory
(The Memory size
varies depending
on Ihe product
Iype.)
PaO-P6 3
Decode
and
Conlrol
SVSB1/P03
RAM
Data Memory
P70-P73
512 x4 bits
SO/SBO/P02
SO-S23
SCKlP01
S24/BPOS3l1BP7
COMO-COM3
INTO/P10
INT1/P11
VLCO-VLC2
INT2IP12
INT4/POO
KRO/P60
-KR7/P73
System Clock
Clock
Oulput
Control
g~~~:r I-_G_e_nTera_l_o_r--I s~~c::r
BIAS
CPU Clock "
LCDCUP30
SYNC/P31
4-139
II
NEe
pPD7530x/31X/P308/P316
Product Comparison (cont)
Item
"PD75304
"PD75306
"PD75308
"PD75P308
"PD75312
"PD75316
"PD75P316/A
Vpp, PROM
programming
pins
None
None
None
Included
None
None
Included
Operati ng voltage
range
2.7 to 6.0 V
2.7 to 6.0 V
2.7 to 6.0 V
5V±10%
2.7 to 6.0 V
2.7 to 6.0 V
5V±10%
2.7 to 6.0 V·
Package
aO-pin plastic QFP
aO-pin plastic
QFP
SO-pin
ceramic
LCCwith
window
aO-pin plastic QFP
SO-pin plastic
QFP
SO-pin ceramic
LCC w/Window·
·"PD75P316A only.
ADDRESS SPACES AND
MEMORY MAPS
The 75X architecture has two separate address spaces,
one for program memory (ROM), and another for data
memory (RAM).
Program Memory (ROM)
The ROM is addressed by the program counter. The size
of the program counter is 12, 13, or 14 bits; its size
depends on which member of the family is being used, as
does the amount of ROM present. The ROM contains
program object code, interrupt vector table, a GETI
instruction reference table, and table data. Table data
can be obtained using the table reference instruction,
MOvr.
Figure 1 shows the addressing range which can be made
using a branch instruction or subroutine call instruction.
In addition, the BR PCDE and BR PCXA instructions can
be used for a branch where only the low 8 bits of the PC
are changed. The program memory addresses are:
75304: OOOH to FFFH
75306: OOOOH to 177FH
75308: OOOOH to 1F7FH
75P308: OOOOH to 1F7FH
75312: OOOOH to 2F7FH
75316: OOOOH to 3F7FH
75P316: OOOOH to 3F7FH
75P316A: OOOOH to 3F7FH
4-140
All locations if ROM except OOOOH and 0001 H can be
used as program memory. However, if interrupts or GETI
instructions are used, the locations corresponding to
those functions cannot be used. Addresses are normally
reserved as follows:
OOOH to 0001 H:
This address area is used as the
vector address for RESET, and also
contains the MBE bit.
0002H to OOOBH: This area is used for interrupt vector
addresses. Each vector address
contains an MBE bit value, and the
interrupts can start from any location
except where noted.
0020H to 007FH: This is the table area for GETI
instructions. The GETI instruction is
used to access one 2-byte/3-byte or
two 1-byte instructions using· one
byte of program memory. This is
useful in compacting code.
NEe
pPD7530x/31x/P308/P316
Figure 1. Program Memory Map
Address
OOOOH
7
o
6
I
.I
MBE
0
IInternal reset start address
I (high order six bits)
(CALL, CALLF) is executed or an interrupt is generated,
the PC is incremented to point to the next instruction,
and this information is saved on the stack. During an
interrupt, the program status word (PSW) is also automatically saved on the stack. The address to be jumped
to by the CALL or interrupt is then loaded into the PC.
J
When a return instruction (RET, RETS, or RETI) is executed, the contents of the stack are restored to the PC.
0004H
instruction
branch
INTO start address
(low order eight bits)
0006H
address
INT1 start address
(high order six bits)
CALL
laddr
INn start address
(low order eight bits)
instruction
subroutine
INTCSI start address
(high order six bits)
0008H
OOOAH
MBEI 0
I
entry
address
I
INTCSI start address
(low order eight bits)
BR laddr
instruction
INTTO start address
(high order six bits)
branch
address
I
INTTO start address
(low order eight bits)
0020H
Data Memory (RAM)
BRCB
Icaddr
INTO start address
(high order six bits)
GETI instruction reference table
007FH 1 - - - - - - - - - - - 1
BR$addr
instruction
relative
branch
address
(-15to
+16)
0080HI~1-_ _ _ _ _ _ _ _ _--1_~I
07FFH
0800H
OFFFHJ_ _ _ _ _ _ _ _ _--l:f_ _+
1000H
branch
destination
1FFFH'f.I---_---I:f---t2000H~
~
subroutine
entry
2FFFFII-----------I--+
3000H
3F7FH'tL--_ _ _ _ _ _ _ _
addrss
;.J,
G TI
instruction
address,
-I'f
The data memory contains three memory banks, 0, 1,
and 15. The RAM memory map is shown in figure 2. The
memory consists of general purpose static RAM and
peripheral control registers, and accessed by using the
MBE (memory bank enable) and by programming the BS
(bank select register). If MBE = 0, the lower 128 nibbles
of memory bank 0 and the upper 128 nibbles of memory
bank 15 are accessed. If MBE = 1, the upper four bits in
the BS register will specify the memory bank. The values
are OH for memory bank 0, 1H for memory bank 1, and
OFH for memory bank 15. Memory banks 0 and 1 each
contain 256 nibbles; while the memory is organized in
nibbles, the 75X architecture allows the data to be
manipulated in bytes, nibbles and individual bits.
The data memory is used for storing proces~ed data,
general purpose registers, and as a stack for subroutine
or interrupt service. The last 32 nibbles of bank 1 are
used to store the LCD display data. If this area is not
completely used by the LCD, it may be used as generalpurpose RAM. Because of its static nature, the RAM will
retain its data when CPU operation is stopped and the
chip is in the standby mode, provided Voo is at least 2
volts.
49NR-566A
Program Counter (PC)
This is a 12/13/14-bit binary counter that contains the
address of the current program memory location. The
75304 contains a 12-bit PC, the 75306/8 has a 13-bit PC,
and the 75312/16 each contain a 14-bit PC.
When an instruction is executed, the PC is automatically
incremented by the number of bytes of the current
instruction. When a branch instruction (BR, BRCB) is
executed, the contents of the immediate data or register
pair indicating the new address are loaded into some or
all the bits of the PC. When a subroutine call instruction
There are eight 4-bit general-purpose registers in bank 0
starting at location OOH. These registers may also be
used as four 8-bit registers. The on-chip peripheral
control registers and ports reside in the upper 128
nibbles of bank 15. Bank 15 addresses which are not
assigned to a register are not available as random
memory except for the 16-bit sequential buffer. Also, the
lower 128 nibbles of bank 15 do not contain RAM.
4-141
II
NEe
pPD753Ox/31X/P308/P316
Addressing Modes
Figure 2. Data Memory Map:
"oliiiH
007H
OOSH
-----
Slack
area
IiankO
256 x 4
r
The pPD753Ox/31x is able to address data memory and
ports as individual bits, nibbles, or bytes. The addressing modes are as follows:
11purpose
General
registers
ax.4
1
100H
General purpose
slatio RAM
256~4
Bank 1
lEBH
lEOH
1-bit direct data memory
4-bit direct data memory
4-bit register indirect (@rpa)
a-bit direct data memory
a-bit register indirect (@HL)
480(4
-----
lFFH
1dataDisplay
memory
32x4
BaLI l:aOHG]l2B.
x 4.
L.Em! .
See table 1 for data memory addressing and table 2 for
peripheral control register addressing.
General purpose
slatio RAM
perJherai
hardware area
_ _....1*_ __
49NR-567A
Table 1. Data Memory Addressing Modes
Addressing Mode
Representation Format
How the Address Is Created
1-bIt direct addressing
mem.blt
If MBE = 0, the memory bank is Bank 0 for addresses OOH-7FH, and Bank 15
for addresses 8OH-F FH.
If MBE = 1, the memory bank is selected by the four bits of the MBS.
The bit to be manipulated Is specified In mem.blt
4-blt direct addressing
mem
If MBE = 0, the memory bank Is Bank 0 for addresses .OOH-7FH, and Bank 15
for addresses 80H-F FH.
If MBE = 1, the memory bank Is selected by the four bits of the MBS.
The bit to be manipulated is specified in memo
8-bltdlrect addressing
mem (must be an even address)
If MBE = 0, the memory bank is Bank 0 for addresses OOH-7FH, and Bank 15
for addresses 8OH-F FH.
If MBE = 1, the memory bank is selected by the four bits of the MBS.
The bit to be manipulated Is specified in memo
4-bit register Indirect
addressing
8-blt register indirect
addressing
4-142
@HL
The memory bank is selected by the four bits of the MBS, and the location
.
within the memory bank Is contained In register HL.
@DE
The memory bank is always Bank 0, and the location within the memory bank is
contained in register DE
@DL
The memory bank is always Bank 0, and the locatlori within the memory bank Is
contained in reg later 0 L
@HL (must be an even addreas)
The memory bank is selected by the four bits of the MBS, and the location
within the memory bank is contained In register HL.
NEe
Table 1.
pPD7530x/31x/P308/P316
Data Memory Addressing Modes
Addressing Mode
Representation Format
How the Address Is Created
Bit manipulation
addressing
fmem.bit
The memory bank is Bank 15, and the location is fmem, where
fmem = FBOH·FBFH for interrupts
fmem = FFOH·FFFH 1/0 ports
The actuai bit is specified in fmem.bit
pmem.@L
The memory location is independent of MBE and MBS. The upper 10 address
bits of the location are contained in the ten high order bits of pmem and the two
lower address bits are contained in the two upper bits of register L.
The bit to be manipulated is specified by the two LSBs of register L.
@H
+ mem.bit
The memory bank is selected by the four bits of the MBS, and the location is
determined by the following:
The four upper bits are the contents of register H
The four lower bits are memo
The actual bit is specified in mem.bit.
The memory bank is always Bank 0, and the location is indicated by the stack
pointer (SP)
Stack addressing
MBE:'memory bank enabie bit
MB: memory bank
MBS: memory bank select register
mem: a location within a memory bank
mem.bit: a bit at a specified memory location.
fmem and pmem are specialized cases of memo
II
Table 2. Addressing Modes During Peripheral Hardware Operation
Manipulation
Addressing Mode
Applicable Hardware
l·bit
With MBE= 0 (or MBE = 1 and MBS = 15) direct addressing
(specification in mem.bit)
All hardware where bit manipulation can be
performed
Direct addressing regardless of how MBE and MBS are set.
(specification in fmem.bii)
ISTO, MBE
IExxx, IRQxxx, PORTn.x
Indirect addressing regardless of how MBE and M BS are set.
(specification in pmem. @L)
BSBn.x
PORTn.x
With MBE = 0 (or MBE = 1 and MBS = 15) direct addressing
(specification in mem.bit)
All hardware where 4·bit manipulation can be
performed
4·bit
With MBE = 1 and MBS = 15, register indirect addressing
(specification in @HL)
B·bit
With MBE = 0 (or MBE = 1 and MBS = 15) direct addressing
(specification in mem); mem must be an even address
All hardware where B·bit manipulation can be
performed
With MBE = 1 and MBS = 15, register indirect addressing
(specification in @HL); L register must contain an even number
4-143
twEC
pPD753OX/31X/P308/P316
Instruction Execution Times
Operation Code Symbols
The minimum instruction execution time is 0.95 /-IS with
a 4.19 MHz clock. The PCC register· can be used to
program the CPU's minimum instruction. cycle time to
0.95, 1.91, or 15.3 "s; all three speeds presuppose a
4.19 MHz crystal. Reducing the CPU clock speed will
reduce the microprocessor's power consumption.
The following opcode symbols are used with the
"PD7530xi31x family.
Instruction Set
The instruction set contains the following features:
•
•
•
•
•
Versatile bit manipulation instructions
Efficient 4-bit manipulation instructions
B-bit data transfer instructions
GETI instruction to reduce program size
Vertically stored instructions and base correction
instructions
• Table reference instructions
• 1-byte relative branch instructions
Symbol Definitions
The "PD7530xi31x family uses the following symbol
definitions:
Symbol
A-B
C
D
E
H
L
X
XA
BC
DE
DL
HL
PC
SP
CY
P&N
MBE
PORTn
IME
IExxx
MBS
PCC
(xx)
xxH
4-144
Definition
A register; 4-bit accumulator
B register; 4-bitaccumulator
C register; 4-bit accumulator
D register; 4-bit accumulator
E register; 4-bit accumulator
H register; 4-bit accumulator
L register; 4-bit accumulator
X register; 4-bit accumulator
XA register pair; B-bit accumulator
BC register pair
DE register pair
DL register pair
HL register pair
Program counter
Stack pointer
Carry flag; bit accumulator
Program status word
Memory bank enable flag
Port n (n = 0-7)
Interrupt master enable
Interrupt enable flag
Memory bank selection register
Clock processor control register
Separation between address and bit
The contents addressed by xx
Hexadecimal data
reg, reg1
R2
·-O~·
o
o
o
1
1
1
1
R1
-0- ~
o
o
1
o
1
1
1
o
o
o
1
o
1
1
1
Register
A (reg only)
X (reg, reg1)
L (reg, reg1)
H (reg, reg1)
E (reg, reg1)
D (reg, reg1)
C (reg, reg1)
B (reg, reg1)
@rpa,@rpa1
~
9.L
~
1
1
0
0
o
o
~
o
o
o
o
o
o
1
1
0
~
o
o
1
1
1
1
Addressing
@HL (@rpa only)
@DE (@rpa, @rpa1)
@DL(@rpa, @rpa1)
1
1
!!L.- ~
o
o
1
o
o
o
1
o
1
o
1
o
o
1
1
register pairs
reg-pair
P2
P1
0 0 XA
o 1
HL
DE
1
0
1
1
BC
IExxx
IEBT
lEW
IETO
IECSI
lEO
1
IE2
IE4
IE1
o
o
!L !I!!..
x
x
x
x
x
x
x
x
x
Operation Representation Format and
Description Method
An operand is entered in the operand field of each
instruction according to the format of the instruction
(see assembler specifications). When two or more entries are indicated in the description method, one should
be selected. Capital letters and symbols must be entered exactly as shown. For immediate data, a proper
numeric value or label should be entered.
NEe
IIPD7530x/31X/P308/P316
Table 3. Symbol Abbreviations
Symbol
Description
Symbol
reg
regl
X,A,B,C,D,E,H,L
X,B,C,D,E,H,L
addr, caddr
rp
rpl
rp2
XA, BC, DE, HL
BC, DE, HL
BC, DE
rpa
rpal
HL, DE, DL
DE, DL
n4
n8
4-bit immediate data or label
8-blt Immediate data or label
mem (Note 1)
bit
8-blt Immediate data or label
2-bit Immediate data or label
fmem
pmem
Description
/lPD75304: OOOH-F F FH immediate data or label
/lPD75306: OOOOH-l77FH immediate data or
label
/lPD75308/P308: OOOOH-l F7FH immediate data
or label
/lPD75312: OOOOH-2F7FH Immediate data or
label
/lPD75316/P316: ooooH-3F7F immediate data or
label
FBOH-FBFH, FFOH-FFFH immediate data or
label
FCOH-FFFH immediate data or label
faddr
ll-bit immediate data or label
taddr
20H-7FH Immediate data (where bit 0 = 0) or
label
PORTn
Port 0 -Port 7
IEBT, IECSI, IETO, IEO-IE4, lEW
MBO, MB1, MB15
IExxx
MBn
II
Notes:
(1) Memory address must be an even number in 8-bit processing.
Instruction Set
Mnemonic
Operand
Operation
Skip Condition
A-- n4
String A
Bytes
Machine Cycle
regl, #n4
2
2
regl -- n4
XA, #n8
2
2
XA--n8
String A
HL, #n8
2
2
HL-- n8
String B
rp2, #n8
2
2
Transfer
MOV
A, #n4
rp2 -- n8
A,@HL
A -- (HL)
A, @rpal
A- (rpal)
XA,@HL
2
2
@HL,XA
2
2
(HL) - XA
A,mem
2
2
A-- (mem)
XA,mem
2
2
XA- (mem)
mem,A
2
2
(mem) -A
mem,XA
2
2
(mem) -XA
A, regl
2
2
A .... (regl)
@HL,A
XA - (HL)
(HL) --A
XA, rp
2
2
XA- rp
regl, A
2
2
regl .... A
rpl, XA
2
2
rpl
<-
XA
4-145
NEe
pPD753Ox/31X/P308/P316
Instruction Set (cont)
Mnemonic
Operand
Bytes
Machine Cycle'
"
", Skip Condition"
Operation
TrBnsfer(coht)
XCH
A,@HL
1
A - (HL)
A-(rpa1)
A, Ci&)r"a1
XA,@HL
2
2
A,mem
2
2
A- (mem)
XA,mem
2
2
XA- (mem)
A, reg1
MOVT
XA - (HL)
A- (reg1)
XA, rp
2
2
XA-rp
XA, @PODE
1
3
XA .... (PC12-S+ DE) ROM
3
XA .... (PC12-S+XA)ROM
XA,@PCXA
Arithmetic
~
.
ADDS
A, #n4
1
A,@HL
1+S
A .... A+n4
"
Carry
1+S
A .... A+(HL)
Carry
A, CY .... A+ (HL)+ oy
AD DC
A,@HL
1
SUBS
A,@HL
1
1+S
SUBC
A,@HL
AND
A, #n4
2
2
2
2
2
2
A, CY - A - (HL) - CY
A,@HL
OR
A, #n4
A, #n4
A....AA n4
A-A A (HL)
A,@HL
XOR
Borrow
A - A-(HL)
A-AVn4
A-AV(HL)
A,@HL
A-AXOR n4
A .... AXOR (HL)
Accumulator Manipulation
CY .... Ao,
Aa .... CY, An-1
RORO
A
1
NOT
A
2
2
1+S
reg .... reg+ 1
reg =0
@HL
2
2+S
(HL) .... (HL)+1
(HL) .. 0
mem
2
2+S
(mem) .... (mem)+1
(mel)'l) = 0
1+S
reg - reg-1
,eg'= FH
reg = n4
- An
A-A
Increment/Decrement
INOS
'DECS
reg
reg
Comparison
SKE
reg, #n4
2
2:t S
skip If reg = ';4
@HL, #n4
2
2+S
,skip H (HL) = n4
A,@HL
A, reg
2
(HL) = n4
1+S
, . skip if A = (HL)
A = (HL)
2+S
skip If A = reg
A,= reg
Carry Flag Manipulation
SET1
oy
OY .... 1
OLR1
oy
OY .... O
SKT
oy
NOT1
OY
4-146
1+S
skip HCY = 1
OY .... OY
CY= 1
ttlEC
pPD7530X/31X/P308/P316
Instruction Set (cont)
Mnemonic
Operand
Bytes
Machine Cycle
Operation
Skip Condition
Memory Bit Manipulation
SETI
CLRI
SKI'
SKF
SKI'CLR
ANDI
ORI
XORI
mem.bit
2
2
(mem.bit) -- 1
Imem.bit
2
2
(Imem.bit) -- 1
pmem.@L
2
2
(pmem7_2+ La_2.bit(Ll-Q)) -- 1
@H+mem.bit
2
2
(H +mem3-Q.bit) -- 1
mem.bit
2
2
(mem.bit) -- 0
Imem.bit
2
2
(lmem.bit) -- 0
pmem.@L
2
2
(pmem7_2+ Ls_2.bit(L1-o)) -- 0
@H+mem.bit
2
2
(H + memS-Q.bit) -- 0
mem.bit
2
2+S
skip il (mem. bit) = 1
Imem.bit
2
2+S
skip il (/mem.bit) = 1
(Imem.bit) = 1
pmem.@L
2
2+S
skip il (pmem7_2 + La-2.bit(Ll-0)) = 0
(pmem.@L = 1)
(mem.bit) = 1
@H+mem.bit
2
2+S
skip il (H+memS-Q.bit) = 1
(@H+mem.bit) = 1
mem.bit
2
2+S
skip il (mem.bit) = 0
(mem.bit) = 0
Imem.bit
2
2+S
skip il (/mem.bit) = 0
(Imem.bit) = 0
pmem.@L
2
2+S
skip il (pmem7_2 + LS_2.bit(Ll_ol) = 0
(pmem.@L = 0)
@H+mem.bit
2
2+S
skip il (H+mems_o.bit) = 0
(@H+mem.bit) = 0
Imem.bit
2
2+S
skip il (Imem.bit) = 1 and clear
(lmem.bit) = 1
pmem.@L
2
2+S
skip if (pmem7_2 + La_2.bit(L1_0)) = 1 and
clear
(pmem.@L = 1)
@H+mem.bit
2
2+S
skip il (H + memS-Q.bit) = 1 and clear
(@H+mem.bit) = 1
CY, Imem.bit
2
2
Cy -- CY A (/mem.bit)
CY, pmem.@L
2
2
CY -- CY A (pmem7_2+Ls_2.bit(Ll-Q))
CY, @H+mem.bit
2
2
CY -- CY A (H+mems-Q.bit)
CY, Imem.bit
2
2
CY -
CY, pmem.@L
2
2
CY - CY V (pmem7_2+L3-2.bit(Ll-Q))
CY, @H+mem.bit
2
2
CY - CY V (H+mems_o.bit)
CY, Imem.bit
2
2
CY -- CY XOR (/mem.bit)
CY, pmem.@L
2
2
CY -- CY XOR (pmem7_2+LS_2.bit(L1-Q))
CY, @H+mem.bit
2
2
CY -- CY XOR (H+mems_o.bit)
3
3
PC12-0 - addr
2
PC12-0 -- addr
2
2
PC12-0 -
CY V (/mem.bit)
Branch
BR (Note 1)
addr
laddr
PC12-0 -- addr
$addr
BRCB
Icaddr
PCI2-0+caddrl1-0
Subroutine Stack Control
CALL
!addr
3
3
(SP-4)(SP-l)(SP-2) -- PC11-0
(SP-3) - (MBE, 0, O,PC 1
PC12-0 - addr, SP -- (SP-4)
CALLF
!faddr
2
2
(SP-4)(SP-l)(SP-2) -- PC 11 -0
(SP-3) -- (MBE, 0, 0, PC1:V
PC 12-0 -- 00, laddr, SP - (SP-4)
:v
4-147
II
NEe
pPD753Ox/31x/P308/P316
Instruction Set (cont)
Mnemonic
Operand
Bytes
Machine Cycle
Skip Condition
Operation
Subroutine Stack Control (cont)
RET
3
RETS
3+S
RETI
3
PUSH
POP
Unconditional
(PCl2l- (SP+1)
PC11-O - (SP)(SP+3)(SP+2)
PSW - (SP+4)(SP+5), SP - (SP+6)
rp, SP .... (SP-2)
2
2
(SP-1) - MBS, (SP-2) - O,SP -
2
2
MBS -
2
2
I.ME --1
2
2
IExxx .... 1
2
2
IME -- 0
2
2
IExxx .... 0
rp
BS
(MBE, PC12l .... (SP+1)
PC11-O -- (SP)(SP+3)(SP+2)
SP - (SP+4), then skip unconditionally
(SP-1)(SP-2) -
rp
BS
(MBE, PCl2l .... (SP+1)
PC11-0 .... (SP)(SP+3)(SP+2)
SP -- (SP+4)
rp -
(SP+1)(SP), SP (SP+1), SP -
(SP-2)
(SP+2)
(SP+2)
Interrupt Control
EI
IExxx
01
IExxx
Input/Output (Note 2)
IN
OUT
= Oto 7)
A, PORTn
2
2
A .... PORTn; (n
XA, PORTn
2
2
XA -- PORTn + 1, PORTn; (n
PORTn, A
2
2
PORTn .... A; (n
PORTn, XA
2
2
PORTn+1, PORT n - XA; (n
= 4,6)
= 2 to 7)
= 4,6)
CPU Control
HALT
2
2
Set HALT mode (PCC.2 .... 1)
STOP
2
2
Set STOP mode (PCC.3 .... 1)
No operation
NOP
Special
SEL
MBn
GETI
taddr
2
MBS - n; (n
When (taddrh_6 = 00,
PC 12-O - (taddrko + (taddr+1)
When (taddrh_6 = 01,
(SP-4)(SP-1)(SP-2) - PC11-O;
(SP-3) .... (MBE,O,O,PC l 2l;
PC12-0 -- (taddr)4_0 + (taddr+ 1);
SP .... SP-4
When (taddrh_6 = 10,
(taddr), (taddr+ 1) instructions are
executed.
Notes:
(1) Appropriate instructions are selected from BR laddr, BRCB
Icaddr, and BR $saddr by the assembler.
(2) When executing the IN/OUT instruction, either MBE must be
reset to 0, or MBE and MBS must be set to 1 and 15, respectively.
4-148
= 0,
2
3
1, 15)
Depends on the
referenced instruction
ttlEC
pPD7530X/31X/P308/P316
Input/Output Ports
There are eight 4-bit ports; some are I/O ports and
some are input only. Figure 3 shows the structure of the
ports and table 4 lists the features. Figure 3 also shows
the structure of inputs and outputs of the other pins.
Table 4.
Types and Features of Digital Port.
Port
Function
Operation and Features
PORT 0
----PORT 1
4-blt input
Can always be read or tested regardless of the
operation mode.
PORT 3 (Note 1)
4-bit Input/output
Can be placed In input or output mode in 1-bit
units.
Pins also used for lCDCl, SYNC and MOO-MOO,
(Note 2)
~-~----------Pins also used for KRO -KR3.
4-blt input/output
Can be placed in input or output mode In 4-bit
units. Ports 6· and 7 can be paired for data
input/output in 8-bit units.
Port 2 pins are also used for PTOO, PCl and BUZ.
PORT 6
PORT 2
PORT 7
Remarks
Pins also used for INT4, SCK SO/S80, SVSB1.
Pins also used for INTO-2 and TIO.
Pins also used for KR4-KR7.
PORT 4 (Note 1)
PORT 5 (Note 1)
4-blt input/output
(N-channel
open
drain, 10 volts)
Can be placed in input or output mode in 4-bit
units. Ports 4 and 5 can be paired for data
input/output in 8-bit units.
Internal pull-up resistor can be specified in 1-bit
units by using mask option.
BPO-BP7
1-bit output
Data Is output in 1-blt units. The BPO-BP7 pins
are also used as LCD segment pins S24-831.
BPO-BP7 and S24-831 can be changed by using
software.
The capacity of drive Is very small. Used for
CMOS load drive.
Notes:
(1) These ports directly drive lEDs.
(2) PORT 3 lines are also used for MOO-MOO in J.lPD75P308/P316/
P316Aonly.
4-149
II
t\fEC
pPD753Ox/31x/P308/P316
Figure 3. I/O Circuits
Type A
Type E·B
(for Type E-B)
(P20-P23. P30-P33)
VDD
VDD
_Ch
Input
~~
N-ch
Data
InlOut
Output Disable
CMOS standard input buffer
TypeB
(POO. RESET)
Input~
Type F·A
(P01. P60-P63. P70-P73)
Schmitt trigger input with
hysteresis characteristic.
VDD
Type B-C
(P10-P1 3)
VDD
Data
IniOut
Output Disable
Type F·B
TypeD
(P0 2)
(For Type E-B. F-A)
VDD
VDD
Data~~_Ch
Output Disable
-=
Output
Pull-Up Resistor Enable
Output Disable (P)
P-ch
----I
P-ch
Push-pull output where output can be placed in high
impedance. P and N channels are tumed off.
Data
Output Disable
---+---1
------------1
Output Disable (N) - - - - - - - - '
4-150
--J:>o--1
N-ch
'---4-<: InlOut
N-ch
NEe
pPD7530x/31x/P308/P316
Figure 3. I/O Circuit. (conI)
TypeG-A
TypeG-B
(SO-S23)
(COMO-COMa)
..L P-ch
..L PoOh
VLCO
VLCO
VLC1----+
VLC1----+
T
T
PoOh
Output
SEG Data
N-ch
t---t--<> Output
VLC2
COM Data
------+.----1
N-ch
T
P-ch
II
VLC2----+
T
N-Ch
T
TypeG-C
(BPO-BP7)
TN'Ch
..L P-ch
TypeM
Voo
(P40 -P4 a. P50-P5a)
..L P-ch
Veo
I
Pull-Up Resistor ~
(Mask option not on ~
75P308 or 75P316)
VLCO
..L
+-_--.-<> In/Out
Data~
Output Disable--L-/'l
VLC1
NoOh
(+10 V)
T
SEG Datal
Bit Port Data
Output
Medium Voltage Input Buffer (+10 V)
VLC2
Type M-C
(POa)
VDD
P-ch
,..----+-0 In/Out
Data~
Output Disable ~. I
49NR-560B
4-151
NEe
pPD753OX/31X/P308/P316
Clock Generator
The clock generator (figure 4) uses the crystal inputs X1
and X2 as a time base to provide clocks for the
p.PD7530xJ31x. The generator consists of an oscillator,
frequency dividers, multiplexers, and three control registers, PCC, SCC, and CLOM. By programming PCC and
CLOM, frequencies derived from the crystal are supplied
to the CPU, the interval timer, the timer/event counter,
the watch timer, the serial interface, and the output pin,
PCL.
The PCC and SCC registers control the HALT and STOP
logic and can also be used to set the CPU to operate at
one of four speeds. The CLOM register controls the
output clock PCL.
The p.PD7530xJ31x family also contains a subsystem
clock, consisting of an oscillator driven by an external
crystal. It operates at 32-35 kHz, and can be used as a
clock source to the watch timer and the CPU.
Basic Interval Timer
The basic interval timer (figure 5) is used to provide
continuous real-time interrupts. It consists of a multiplexer, an 8-bit free-running counter, and a 4-bit BTM
control register. Each time the counter reaches FFH it
causes an interrupt, overflows to OOH and continues to
count. The BTM register is used to select one of four
clock inputs to the counter as well as clear the counter
and its interrupt request. The counter can generate 250
ms interrupts with a 4.19 MHz crystal and also provides
oscillator stabilization time when the chip comes out of
the STOP mode.
Figure 4. Clock Generator
XT1
XTAL=
L-
s~~~fi::;;n 1-~lxtL_ _ _ _ _ _- - - - - - - - - - + w a t c h T i m e r
Watch Timer: Ixx/27
XT2
Interval Timer: Ixx /2 5 , Ixx /27 , Ixx/29, Ixx/212
TimellEvent Counter: Ixx/24, Ixx/26, Ixx/28, Ixx/210
XTAL
~
T..-
I
X1 Main
System
Ixx
Oscillator
J
114 1/8 1/16
STOP
STOP
Logic
J
Frequency Divider
1112
X2
Serial Interlace: Ixx/23, Ixx/24, Ixx/26
1
1/64
l
JJ
Multiplexer
ENB
II
CPU Clock Multiplexer
SEL
1
Output
1/4
1
I
f----o P22/PCL
SEL
j
121
(to CPU)
)
HALT
Logic
1
1
HALT
'------+
' x t - Multiplexer
1
1
PCC Register
41'
1
I
SCC Register
21'
J
f---
l
CLOM Register
J
4f
Inte rnal
Data Bus
49NR-545B
4-152
t\'EC
pPD7530x/31x/P308/P316
Figure 5. B••ie 'nter",,' 7imer
1•• 125
1•• /27
1•• 129
Overflow
8-Bit Binary
Counter
Start
1••/212
Timer/Event Counter (TMO)
The timer/event counter (figure 6) consists of an 8·bit
modulo register, a·bit comparator, a-bit count register,
clock multiplexer,. mode control register TMO, and a
TOUT flip flop. There is also some control logic so that
the timer's TOUT flip flop can be sent to port 2.
Interrupt
Request
S
Interrupt
Request
Flag
8
Internal[=~=====~===~~===J
Data
Bus
"NR.-
Figure 6.
7imer/Event Counter
Interna1/
Data Bus
8
8f
I
T10/P 13
1",,/210
1••/2 8
l.xl26
1",,12 4
An 8-bit value is loaded into the modulo register, and a
count register clock is selected by the clock multiplexer,
via control register TMO. The count register is incremented each time it receives a CP pulse. When the value
in the count register is equal to the count in the modulo
register, the comparator generates a signal which toggles the TOUT flip flop and causes the count register to
be reset to DOH. The count register will continue to count
up unless stopped. Each time TOUT changes state it
causes an interrupt. This signal can also be used as a
clock for the serial interface.
D
Mode Register
(TMO)
L[>-:
Clock
Multiple.er
I
8,
---
CP
I
Modulo Register
(TMODO)
I
Comparator
8¥
Count Register
(TO)
J
r
3
TOUT
FIF
Control
Logic
I"-- P20/PTO
J
Serial Interface
and IRQTO
... R.....
4-153
II
NEe
pPD7530x/31x/P308/P316
Watch Timer
The watch timer (figure 7) generates interrupt requests
(but no interrupts) at 0.5 second intervals when using a
4.19 MHz crystal. It is commonly used as a time source
for keeping track of the time of day, can operate in the
STOP mode and is capable of generating a 2 kHz buzzer
output signal.
The watch timer consists of an input multiplexer, divider,
output multiplexer, control logic, and control register
WM. It is also used as a clock source for the LCD
controller.
Serial Interface
The 8-bit serial interface (figure 8) allows the
I'PD7530X/31x to communicate with other NEC or NEClike serial interfa.ces. It consists of an 8-bit shift register
(SIO), serial-out latch (SO), 8-bit address comparator,
slave address register (SVA), control registers CSIM and
SBIC, busy/acknowledge circuitry, bus release/detect
circuitry, serial clock counter, clock multiplexer, and
clock control circuitry. The three-wire interface consists
of the serial data in (SI/SB1), serial data out (SO/SBO),
and serial shift clock (SCI<).
Figure 7.
Watch Timer
Internal . . . - - - - - - - - - - - - - - - - ,
Data Bus ' - - - - - - , - - - - - r - - - - - - - - - '
SEL
Ixt
Interrupt
Request
IROW
L--------ILCD
(to LCD Controller)
49NR·550A
4-154
There are three modes of operation, 2-wire serial, 3-wire
serial, and 2-wire SBI. The simplest modes are the
2/3-wire serial. In these modes, the 8-bit shift register is
loaded with a byte of data and 8 clock pulses are
generated. These pulses shift data out the SO line and
data in from the SI line, thus, communicating in full
duplex. Each time a byte of data is sent, a burst of eight
clock pulses is generated and eight bits of data will be
sent. Data may be sent either LSB or MSB first. The
interface may also be set to receive data only; in this
case SO is in the high-impedance state. One of four
internal clocks or an external clock may be used to clock
the data.
The SBI mode uses a 2-wire interface (figure 9) with
devices in a master/slave configuration. At anyone time,
there is a single master, with all other devices being
slaves. The master can send addresses, commands, and
data over the bus. The slaves are able to detect in
hardware if their particular address has been sent, and
can also detect whether a command or piece of data has
been sent. There can be as many as 256 slave addresses,
256 commands, and 256 data types. All commands are
user-defined, and it is possible to send commands
which change slaves into masters; when this happens,
the previous master becomes a slave. This type of work
is done in firmware, and the bus can be as simple or
complex as the user wishes.
NEe
pPD7530x/31x/P308/P316
Figure 8. Seriallntertace Block Diagram
Internal
Bus
~
I
Bit
Test
Control Serial Interface
Mode Register (CSIM)
a
I
L I->
II
'--
POa/SVSB1
I),.
"'"
Selector
-5=
PD2/S0/SBO
r-
Bit
Manipulation
a
a
I
a-Bit Slave Address
Register (SVA)
I
a-Bit Address
Comparator
Serial Acknowledge Interface
Control Register (SBIC)
I
~,-.J:tW
~gnal
V
=u
RElT
CMDT
SET ClR
a-Bit Shift Register (SIO)
I- f-"
r
DSerialO
Output
latch
=::r-
-c-tIJ
I),.
"'"
~
Bit
Tes
'--Selector
I+-
~
ACKT BSYE
ACKE
~
II
ACk~!r~dge
-
Output Circuit
'--
t-- I-
t---
Bus Releasel
CommandJ
Acknowledge
Detection
Circuit
RElD
CMDD
ACKD
T
Ilo.
Serial Clock
Counter
"'"
r--P01
lQ"-~
latch
-
'--
r--
IROCSI
Control
Circuit
IROCSI
~
I~
Serial Clock
Control
Circuit
-4--fxx /2 3
- lxx /2 4
Clock
- lxx /2 6
Multiplexer
-TOUTF/F
~ =::JExternal SCK
L
J
49NR-558B
4-155
NEe
pPD753Ox/31x/P308/P316
Figure 9. SBI Mode Master/Slave Configuration
7
Master CPU
""D753XX
Slave CPU
I'PD753XX
(SB1), SBO
S80,(SB1)
Address 1
-
SCK
SCK
Slave CPU
SBO,(SB1)
Address 2
t
,
> - - + SCK
,
SlavelC
SBO, (SB1)
.
Address N
SCK
49NR-559A
LCD Controller/Driver
The LCD controller/driver (figure 10) can be pro·
grammed to operate in any of four modes, It can
operate in the static mode (drive 32 segments), the
multiplexed mode (drive 64 segments), the triplexed
mode (drive 96 segments), or quadruplexed mode
(drive 128 segments). The multiplexed mode uses 1/2
bias, the triplexed mode can use either 1/2 or 1/3 bias,
and the quadruplexed mode uses 1/3 bias.
The controller automatically refreshes the LCD by tak·
ing data from the upper 32 nibbles of RAM memory bank
1, and uses display data multiplexers, segment drivers
S0-S31 , and common drivers COM~OM3 to drive the
LCD. It is controlled by registers LCDM, LCDC, and
PGMA. The LCD main controller clock (fLCD) is provided
by the watch timer. Because the watch timer operates
while the chip is in the STOP mode, so does the LCD
controller.
The SYNC signal and clock LCDCL are provided so that
additional LCD controllers can be added. Drive levels
can be set internally by ordering the resistor ladder
mask option, otherwise, external resistors can be con·
nected to pins VLCo-VLC2 and the BIAS pin. The BIAS pin
can be used to control the contrast of the LCD.
Figure 10. LCD Controller Block Diagram
D~~~~I~_ _ _ _,---------------.-----------------~
Display Data
Memory
Display Data
Multiplexers
L---r-..l....---r-....I
Segment
Drivers
COM1
COM3
VLCl
49NR·5GOB
4-156
NEe
Bit Sequential Buffer
The bit sequential buffer is 16 bits of general-purpose
RAM located in the upper half of memory bank 15, and is
the only general-purpose RAM in this area All other
locations in this bank contain either the on-chip peripheral control registers or are unused addresses. A typical
application of this buffer might be to store data for the
next serial output or to store data from a serial input. It
could also be used to store data which is to be sent from
a port. This area can be bit, nibble, or byte manipulated.
IIPD7530x/31X/P308/P316
addition, INT2 will sense the rising edge inputs and
generate an interrupt request flag which is testable.
Inputs KRO-KR7 will detect falling edges, and generate
the same interrupt request flag as INT2. Neither INT2
nor KRO-KR7 will cause an interrupt, but they can be
used to release the STANDBY mode. All interrupts and
interrupt requests except INTO will release the
STANDBY mode.
Interrupts
The pPD7530x/31x family interrupts (figure 11) are all
vectored; there are three external and three internal
interrupts. Table 5 gives a summary of the interrupts. In
Figure 11_ Interrupt Controller Block Diagram
c====;==~===;:==;~===;::~~~=;::::;::=;======~==::;;:::===:~
Internal
Data
Bus -
INTBT
INT4IPOO
-----1-+-------1
-----+-+-1
INTO/P10
INT1/P11
INTCSI
Priority
Control
------------1
Vector
Table
Address
Gen
INTTO------------I
INTW-------------~
INT2/P12
Standby
Release
Signal
49NR.s61B
4-157
II
NEC
IIPD7530xl31x1P308/P316
Standby Modes
The standby mode is summarized in taple 6 and consists of three sul:>modes.
HALT mode. The HALT mode is entered by executing
the HALT instruction. Inthis mode, the clock to the CPU
is shut off (thus stopping the CPU), whi Ie all other parts
of the chip, with the exception of INTO, remain fully
functional.
STOP mode. The STOP mode is entered by executing
the STOP instruction. In this mode, the chip's main
system oscillator is shut off, thereby stopping all por-
tions of the chip except those which function off the
subsystem clock. If the subsystem clock is used, it
always remains on.
The HALT and STOP modes are released by a RESET or
by any interrupt request except INTO.
Data Retention mode. This mode may be entered after
entering the STOP mode. Here, supply voltage Voo may
be lowered to 2 volts to further reduce power consumption. The contents of the RAM and registers are retained.
This mode is released by first raising Vooto the proper
operating range, then releasing the STOP mode.
Table 5. Interrupt Sources
Internal/
External
Interrupt Priority
(Note)
Vectored Interrupt Request Signal
(Vector Table Address)
Interrupt Source
Operation
INTBT
Reference time interval signal from basic
interval timer
Internal
VRQl
(OOO2H)
INT4
Both riSing and falling edge detection
External
VRQl
(OO02H)
INTO
Selection of rising or falling edge detection
External
2
VRQ2
(OO04H)
INTl
Selection of rising or falling edge detection
External
3
VRQ3
(OO06H)
INTCSI
Serial data transfer end signal
Internal
4
VRQ4
(OO08H)
INTTO
Coincidence signal between programmable
timer/counter count register and modulo
register
Internal
5
VRQ5
(OOOAH)
INT2
Rising edge detection of input to INT2 pin, or
falling edge detection of any input to KRO-KR7
External
Testable Input signals
(IRQ2 and IRQW are set)
INTW
Signal from watch timer
Internal
Notes:
(1) The interrupt priority order is used to determine the priority when
two or more interrupts are generated simultaneously.
Table 6. Standby Mode Operation
Setting Instruction
STOP Instruction
HALT Instruction
System clock when standby mode is set
Can be set only during main system or
subsystem clock
Can be set during either main system or
subsystem clock
Clock oscillator
Only the main system clock oscillator is
stopped
Only CPU clock ¢ is stopped (oscillation
continues)
Basic interval timer
Operation stopped
Can Operate
Serial interface
Can operate only when external SCK input is
selected for serial clock
Can operate
Timer/event counter
Can operate only when TIO pin input is selected
for count clock
Can operate
Watch timer
Can operate only when txT is selected for count
clock
Can operate
4-158
NEe
IlPD753OX/31X/P308/P316
Table 6. Standby Mode Operation (cont)
Setting Instruction
STOP Instruction
HALT Instruction
LCD controller
Can operate only when txT is selected for
LCDCL
Can operate
INT1, INT2, INT4 can operate; INTO cannot
External interrupts
Operation stop
CPU
Interrupt request signal (enabled with interrupt enable flag) from operating hardware or RESET
Release signal
Reset
See table 7 for the state of the chip after a RESET is
applied.
Table 7. State of the Device after Reset
RESET Input During
Standby Mode
Hardware
Program counter (PC)
PSW
RESET Input During
Operation
JlPD75304
The low-order 4 bits of program memory address OOOOH are loaded
into PCll-PCB. The contents of address 0001H are loaded into
PC7-PCO.
JlPD75306
JlPD7530B
JlPD75P30B
The low·order 5 bits of program memory address OOOOH are loaded
into PC12-PCB. The contents of address 0001 H are loaded into
PC7-PCO.
JlPD753l2
JlPD753l6
JlPD75P316
JlPD75P316A
The low-order 6 bits of program memory address OOOOH are loaded
into PCl3-PCB. The contents of address 0001H are loaded into
PC7-PCO.
Carry flag (CY)
Held
Undefined
Skip flags (SKO-SK2)
o
a
a
o
Interrupt status flag (ISTO)
Bit 7 of program memory address OOOOH is loaded into MBE
Bank enable flag (MBE)
Stack pointer (SP)
Undefined
Undefined
Data memory (RAM)
Held (Note 1)
Undefined
General purpose registers
Held
Undefined
a
a
(X, A, H, L, D, E, B, C)
Bank selection register
(MBS)
Basic Interval timer
Timer/event counter
Counter (Bl)
Undefined
Undefined
Mode register (BTM)
a
a
Counter (fa)
0
a
Modulo register (TMODO)
FFH
FFH
Mode register (fMO)
a
a
TOEa, TOUT F/F
0,0
0, a
Watch timer
Mode register (WM)
a
0
Serial interface
Shift register (S 10)
Held
Undefined
Operation mode register (CSIM)
0
a
SBI control register (SBIC)
a
a
Slave address register (SVA)
Held
Undefined
4-159
II
NEe
pPD753Ox/31X/P308/P316
Table 7. State oft. Device after Reset (conI)
RESET Input During
Standby Mode
RESET Input During
Operation
Processor clock control register
(PCC)
0
0
System clock control register
(SCC)
0
0
Clock output mode register
(CLOM)
0
0
Display mode register (LCDM)
0
0
Display control register (LCDC)
0
0
Interrupt request flags (IRQxxx)
Reset to 0
Reset to 0
Interrupt enable flags (IExxx)
0
0
Interrupt master enable flag
(IME)
0
0
INTO, INn, and INT2 and mode
registers (IMO, IM1, and IM2)
0,0,0
0,0,0
Output buffers
Off
Off
Output latches
Cleared
Cleared
Input/output mode registers
0
0
0
0
Hardware
Clock generator
and clock output c Ircu it
LCD controller
Interrupt function
Digital ports
(PGMA, B)
Pullup resistor speciflcetion
register (POGA)
Bit sequential buffer
Held
Undefined
Pin conditions
Input
Input
With incorporated pullup resistor, high level; with open drain, high
Impedance
80-823
Undefined
Undefined
COMo-COM3
BIAS
Notes:
(1) The data of deta memory address OF8H'()FDH is undefined by
RESET.
4-160
With incorporated reslator ladder, low level; with no Incorporated
resistor ladder, high impedance
NEe
,.,PD7530X13'1xIP308IP316
EPROM Write and Verify
EPROM Write/Verify Procedure
The JlPD75P308 contains 8064 bytes of EPROM, while
the JlPD75P316/16A have 16256 bytes. Table 8 shows the
pin functions during the write and verify cycles. Note
that it is not necessary to enter an address, since the
address is updated by pulsing the clock pins. When 6 V
and 12.5 V are applied to the VDD and Vpp pins, respectively, the EPROM is placed in the write/Verify mode. The
operation is selected by the MDo-M[?3 pins, as shown
in table 9.
EPROMs can be written at high speed using the following procedure: (see figure 12)
Table B. EPROM Write and Verify Pin Functions
Pin Name
Function
X1,X2
After a wrlte/verlfy write, the X1, and X2 clock
pins are pulsed. (Note that these pins are also
pulsed during a read).
(1)
Pull unused pins to Vss through resistors. Set the
X1 pin low.
(2)
Supply 5 volts to the VDD and Vpp pins.
(3)
wait for 10 Jls.
(4)
Select the clear program memory address mode.
(5)
Supply 6 volts to the VDD and 12.5 volts to the Vpp
pins.
(6)
Select the program inhibit mode.
(7)
Write data in the 1 ms write mode.
(8)
Select the program inhibit mode.
(9)
Select the verify mode. If the data is correct,
proceed to step 10. If not, repeat steps 7, 8, and 9.
MOO-MD3
These are the operation mode selection pins.
P4o-P4a
(four Iow-order bits)
P50-P53
(four high-order bits)
a-bit data Input/output pins for write verify
Yoo
Supply voltage. Normally 5 volts; 6 volts is
applied during wrlte/verify
(12) Apply four pulses to the X1 pin to increment the
program memory address by one.
Ypp
Normally 5 volts; 12.5 volts is applied during
write/Verlfy
(13) Repeat steps 7-12 unti I the end address is reached.
(10) Perform one additional write.
(11) Select the program inhibit mode.
(14) Select the clear program memory address mode.
Notes:
(1) A cover should be placed over the UV erase window. The
pPD75P308GF/P316GF/P316AGF do not have windows, thus the
EPROM contents cannot be erased.
Table 9.
(15) Return the VDD and Vpp pins back to
+ 5 volts.
(16) Turn off the power.
Write/Verlfy Operation
Ypp= +12.5Y;Yoo= +6.0Y
Operation Mode Specification
MDO
MD1
MD2
o
o
o
MD3
Operation Mode
o
Clear program memory address
Write mode
o
Verify mode
x
Program Inhibit
Notes:
(1) x = Don't care.
4-161
a
NEe
pPD7530x131xJP308/P316
Figure 12. EPROM Write/Verify Cycle Timing
J
I-<-----x
Repetitionsi----:'I
I--Write--;oo.I.I,.,.--Verify-----;~-.-
Additional Write-.....+-I.f----Address Increment:---+l·1
r---------------:!f.,}:-c-------------------
Vpp= 12.5 V - - VPP=VDD--'
r--------------::Ilf.:.....----------------------
VDD=VDD+1- - VDD=VDD--'
X1
P:~~:~:-----c(
Input Data
>--<
Output Data
~~
Input Data
)>---__________
MDO
(P3o)
MD2
. /~-------------~If.
(P3 21 - '
MD3
/r------------~If.:.....-------------------(P33 1 - - ,
49NR-576B
EPROM Read Procedure
(6)
Select the program inhibit mode.
The EPROM contents can be read by using the following
procedure: (see figure 13)
(7)
Pull unused pins to Vss through resistors. Set the
X1 pin low.
Select the verify mode. Apply four pulses to theX1
pin. Every four clock pulses will output the data
stored in one address.
(8)
Select the program inhibit mode.
(2)
Supply 5 volts to the Voo and Vpp pins.
(9)
Select the clear program memory address mode.
(3)
Wait for 10/1s.
(10) Return the Voo and Vpp pins back to
(4)
Select the clear program memory address mode.
(11) Turn off the power.
(5)
Supply 6 volts to the Voo and 12.5 volts to the Vpp
pins.
(1)
4-162
+ 5 volts.
1t(EC
pPD7530x/31x/P308/P316.
Figure 13. EPROM Read Cycle Timing
Vpp= 12.5 V _ ,.,..
Vpp=VOO-'
--------------------------------------------~J~
--------------------------:lJJ.--
VOO=VOO+1- ....
VOO=VOOJ
X1
~~~~--------------~(~_______Ou_tP_ut_D_am__. ____~)(~______O_u_tPu_t_Da_m______~)(~____________~~~
MOO/
(P30)
.
\~--~~----------~!;--
M01
P3
( 1)
----------------------------------------------------------------------------------------------:JJ~
M02/~----------------------~~--
(P32)
M03--./
(P33)
'\.....
',,-. ...
49NR-517B
Program Memory Erase (p.PD75P308K1P31aAK
only)
The pPD75P308K/P316AK allows the programmed data
contents to be erased by light rayswhose wavelength is
shorter than about 400 nm. The programmed data
contents may also be erased if the uncovered window is
exposed to direct sunlight or a fluorescent light for
several hours. Thus, to protect the data contents, cover
the window with an opaque film.· NEe attaches qualitytested shading filrn to the UV EPROM products for
shipping.
For normal EPROM erase, place the device under an
ultraviolet light source (254 nm). The minimum amount
of radiation exposure required to erase the pPD75P308K
completely is 15 Ws/cm 2 (ultraviolet ray strength times
erase time). This corresponds to about 15 to 20 minutes
when using a UV lamp of 12000pW/cm2 . However, the
erase time may be prolonged if the UV lamp is old or if
the· device window is dirty. The distance between. th~
light source and the window should be 2.5 cm or less.
4-163
m
ttlEC
pPD753Ox/31x/P308/P316
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (All devices)
TA = 25·C
+ 7.0 V
+ 13.5 V
-0.3 to VOO + 0.3 V
-0.3 to VOO + 0.3 V
-0.3 to
Supply voltage, Voo
Supply voltage, Vpp (75P308/P316 only)
Input voltage, VI1 (other than ports 4, 5)
Input vofiage, VI2 (ports 4, 5; internal pullup
resistor; 753Ox/31x only)
-0.3 to
-65 to
Storage temperature, tSTG
Operating temperature, tOPT (75P308/P316)
-10 to +.70·C
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent
damage.
Notes:
High-level output current, IOH
(Single pin)
-15 mA
(1) rms value = peak x (duty cycle)¥...
High-level output current, IOH
(Total of all pins)
-30 mA
-0.3 to
-0.3 to Voo
Low-level output current, IOL
(Single pin)
Low-level output current, IOL
(Total of ports 0, 2, 3, 5)
Low-level output current, IOL
(Total of ports 4, 6, 7)
+ 85·C
-40 to
+ 11 V
+ 0.3 V
Input vo~age, VI3 (ports 4, 5; open drain)
Output voltage, Vo
+ 1SOOC
Operating temperature, tOPT (753Ox/31x)
Capacitance (All devices)
Voo = 0 V; TA = 2SOC
30 mA peak
15 mA rms (Note 1)
100 mA.peak
60 mA rms (Note 1)
Parameter
Symbol
Input capacitance
Output capacitance
I/O capacitance
Max
Unit
CIN
15
pF
COUT
15
pF
CvO
15
pF
Conditions
f = 1 MHz;
all unmeasured
pins returned
to ground
100 mA peak
60 mA rms (Note 1)
Main System Clock Oscillator Characteristics (All devices, see figure 16)
jlPD753Ox/31x: TA = -40 to + 85·C; VOO = 2.7 to 6.0 V
jlPD75P308/P316: TA = -10 to + 70·C; VOO = 5 V :!: 5%
Oscillator
Parameter
Symbol
Min
Ceramic resonator
(Figure 14)
Oscillation frequency (Note 1)
!xx
1.0
Crystal resonator
(Figure 14)
Oscillation frequency (Note 1)
External clock
(Figure 14)
Typ
Oscillation stabilization time (Note 2)
!xx
1.0
Oscillation stabilization time (Note 2)
4.19
Max
Unit
5.0
MHz
4 (Note 3)
ms
Conditions
After Voo reaches oscillator
operating voltage
5.0
MHz
10 (Note 3)
ms
Voo = 4.5 to Voo max
30 (Note 3)
ms
Voo = 2.7 to 6.0 V
(jlPD7530X/31 x only)
Xl input frequency (Note 1)
fxx
1.0
5.0
MHz
Xl input low- and high'level width
tXH, txL
100
500
ns
Notes:
(1) The oscillation frequency and Xl input frequency are included
only to show the characteristics of the oscillators. Refer to the AC
Characteristics table for actual instruction execution times.
(2) The oscillation stabilization time is the time required for the
oscillator to stabilize after voltage is applied or the STOP mode is
released.
4-164
(3) Values shown are for the recommended resonators. Values for
resonators not shown in this data sheet should be obtained from
the manufacturer's spec sheets.
NEe
"PD753OX/31X/P308/P316
Figure 15. Subsystem C/~k CtjnliguratltjllS
Figure 14. Main System C/tjck ContiguratltjllS
A. CeramlclCrystal Resonator
A. Cryatal Resonator
;--1>---1 X1
;--1,.---1 XT1
'---4>---1 X2
'---4~W'r-l
B. External Clock
:><>_----1
XT2
: : ' 1.-_ _ _ _.......
B. External Clock
X1
~~----IXT1
I1P074HCU04
Open
II
XT2.
Note: When the Input Is an external clock, the stop mode
cannot be set because the X1 pin Is connected
to system ground (Vss).
Subsystem Clock OSCillator Characteristics (All devices, see figure 16)
IlPD753Ox/31x: TA = -40 to + 85'C; Voo = 2.7 to 6.0 V
jlPD75P308/P316: TA = -10 to + 70'C; Voo = 5 V :!: 5%
Oscillator
Parameter
Symbol
Crystal resonator
(Figure 14A)
Oscillation frequency
txT
External clock
(Figure 148)
Min
Typ
Max
.Unlt
32
32.768
35
kHz
Oscillation stabilization
time (Note 1)
1.0
Conditions
2
e
Voo
10
s
VOO
XT1 input frequency
txT
32
100
kHz
XT1 Input low- and
txTH, txTL
10
15
lIS
= 4.5 to Voo max
= 2.7 to 6.0 V (PD753Ox/31x only)
h igli-Ievel width
Notes:
(1) Values shown are for the recommended. Values for resonators not
shown in this data sheat should be obtained from the manufacturer's spec sheets.
4-165
NEe
IIPD7530x/31X/P308/P316
Figure 16. Clock AC Timing Points XI and XTI
Recommended Main System Crystal .
Resonators (,4PD7530x/31x only)
Manufacturer
Kinseki
Frequency
(MHz)
C1
C2
Retainer
(pF)
(pF)
Remarks
2.00
HC-18/U
22
22
Voo = 2.7
to 6.0 V
4.19
HC-49/U
22
22
4.91
HC-43/U
22
22
Recommended Subsystem Crystal Resonators
(,4PD7530x131 x onl y)
O.4V
83RD-5884A
Recommended Main System Ceramic
Resonators (,4PD7530x/31x only)
C1
C2
(pF)
(pF)
Remarks
15
15
Voo = 2.5
lo3.5V
CSB 1000020
220
220
CSA 2.00MG093
CSA4.19MGU
CSA4.91MGU
30
30
30
30
30
30
Voo = 2.7
10 6.0 V
CST 2.00MG093
C,ST 4.19MGU
CST4.91MGU
None
None
None
None
None
None
Voo = 2.7
106.0V
(Note 1)
KBR-l000H
100
100
KBR-2.0MS
68
68
Voo = 3.0
106.0V
KBR-4.0MS
KBR-4.19MS
KBR-4.91MS
33
33
33
33
33
33
Manufacturer
Part Number
Murata
CSA 2.00MG093
Kyocera
Notes:
(1) Cl and C2 are contained in the oscillator.
4-166
Manufacturer
Kinseki
C1
C2
Type
(pF)
(PF)
R
(Idl)
Remarks
P-3
22
22
330
Voo = 2.7106.0 V
ttlEC
pPD7530x131X/P308/P316
DC Characteristics (p.PD7530xJ31x)
TA = -40 to
+ 85'C; voo
= 2.7 to 6.0 V
Parameter
High-level input voltage
Low-level input voltage
Symbol
Low-level input leakage current
High-level output leakage current
LOW-level output leakage current
Unit
Conditions
Ports 2,3
O· 7V OO
VOO
VIH2
0.8VOO
VOO
V
Ports 0, 1, 6, 7; and RESET
VIH3
0.7VOO
VOO
V
Ports 4 and 5; built-in pullup resistor
0.7VOO
10
V
Ports 4 and 5; open drain
VIH4
VOn-°. 5
VOO
V
X1, X2, XT1
VIL1
0.3VOO
V
Ports 2, 3, 4, 5
0.2VOO
V
Ports 0, 1, 6, 7; RESET
VIL3
a
a
a
V
X1.
VOH1
VOn-1.O
V
Ports 0, 2, 3, 6, 7, BIAS; VOO = 4.5 to 6.0 V;
IOH = -1 rnA
VOn-°. 5
V
Ports 0,2,3,6,7, BIAS; VOO = 2.7 to 6.0 V;
IOH =-100 JlA
VOn-2.O
V
BP0-7 (WIth two IOL outputs)
VOO = 4.5 to 6.0 V;
IOH .. -100 JlA
VOn-1.O
V
BP0-7 (with two IOL outputs)
VOO = 2.7 to 6.0 V;
IOH = -30JlA
2.0
V
Ports 3, 4, 5; VOO = 4.5 to 6.0 V;
IOL= 15 rnA
0.4
V
Ports 0, 2-7; VOO = 4.5 to 6.0 V;
IOL= 1.6 rnA
0.5
V
Ports 0, 2-7; VOO = 2.7 to 6.0 V;
IOL= 400JlA
0.2VOO
V
sea, 1; VOO =
1.0
V
BP0-7 (With two IOL outputs)
VOO = 4.5 to 6.0 V;
IOL = 100 JIA
1.0
V
BI>0-7 (WIth two IOL outputs)
VOO = 2.7 to 6.0 V;
IOL = 50 JlA
IUH1
3
JlA
All except X1, X2, XT1 and ports 4, 5;
VIN = VOO
ILIH2
20
JlA
X1, X2, and XT1; VIN = VOO
IUH3
20
JlA
Ports 4 and 5 (with open drain); VIN = 10 V
ILIL 1
-3
JlA
All except X1, X2, and XT1; VIN =
IUL2
-20
JlA
X1, X2, and XT1; VIN =
Other than Ports 4 and 5; VOUT = Voo
VOL1
VOL2
High-level input leakage current
Max
VIH1
VOH2
Low-level output voltage
Typ
V
VIL2
High-level output voltage
Min
0.4
0.4
X2, XT1
II
2.7 to 6.0 V;
pullup resistance '" 1kO
aV
aV
ILOH1
3
JlA
ILOH2
20
JlA
Ports 4 and 5 (open drain); VOUT = 10 V
ILOL
-3
JlA
VOUT = OV
4-167
NEe
pPD753OX/31X/P308/P316
DC Characteristics Cl£PD7530X/31x) (cont)
Paramater
Symbol
Built-In pullup resistor
RL1
Min
Typ
Max
Unit
15
40
80
kO
Ports 0,-3, 6, 7 (except POa); VIN = 0 V;
Voo .. 5.0 V :I: 10%
200
kO
Ports 0-3, 6, 7 (except POo); VIN
VOO = 3.0 V :I: 10%
70
kO
Ports 4, 5; VOUT
:1:10%
60
kO
Ports 4, 5;
:1:10%
30
RL2
15
40
10
LCD drive voltage
VLCO
2.5
LCD split resistor
RLCO
60
LCD output voltage deviation;
common (Note 1)
VOOC
LCD output voltage deviation;
segment (Note 1) , ,
VODS
Conditions
= 0 V;
= V00"'2 V; VOO .. 5.0 V
Your = Vo0"'2 V; Voo = 3.0 V
VOO
V
150
kO
0
:1:0.2
V
10
:l:5pA;
VLCO = VLCOO = 2.75 V to VOO;
VLCD1 = 213 VLCO
VLCD2
1/3 VLCO
0
:1:0.2
V
10 = :1:1 pA;
VLCO = VLCOO" 2.75 V to VOO;
VLC01
213 VLCO
VLCD2 = 1/3 VLCO
100
=
=
=
Supply current
(Note 3)
= 5 V :I: 10% (Note 4)
2.5
8.0
mA
VOO
0.35
1.2
mA
VOO .. 3 V :I: 10% (Note 5)
IOD2
(Note 2)
500
1500
pA
HALT mode; Voo .. 5 V:I: 10%
150
450
pA
HALT mode; VOO
iOD3
30
90
pA
VOO
IOD1
(Note 2)
IOP4
5
15
pA
= 3 V :I: 10%
= 3 V :I: 10% (Note 5)
HALT mode; VOO = 3 V :I: 10% (Note 6)
IODS
0.5
20
pA
STOP mode; XT1 = 0 V; VOO = 5 V :I: 10%
0.1
10
pA
STOP mode; XT1
= 0 V; VOO .. 3 V
:I: 10%
0.1
5
pA
STOP mode; XT1
10%; TA
25°C
= 0 V; Voo .. 3 V
:I:
=
Notes:
(4) When operated in the high-speed mode with the processor clock
control register (PCC) setto 0011.
(1) Voltage devlatlon:ls the difference ~etween the Ideal value of
segment or com'mon output (VLCOn; n = 0, 1, 2) and the output
voltage.
(5) When operated In the low-speed mode with the PCC set to 0000.
(2) 4.19 MHz crystal oscillator; 01 =, 0,2 .. 22 pF.
(6) Main system clock stopped and subsystem clock running (SCC
(3) Does not Include pullup resistor current and current through LCD
resistor ladder.
= 1001).
.
NEe
pPD753Ox/31X/P308/P316
Figure 17. DC Characteristics
100 vs Voo (Crystal Resonator at 4.19 MHz)
f:TA
TA-2 'C
25'C
Main Syatem Clock
5000
Main System Clock
High-speed mode .,,PCG..oo
I
1000
Ci!
~ 500
I
Main System Clock
Mlddle.speed mode
PCC..o01
I
I
r---
?:'
r- Main System bOCk
1
r-
f-
Q
E
§
100
I
V
-
Main System Clock
High-speed mode .,,-
.....
.....
..........
1000
?:'
~
1
./
Main ystem Clock
.9
E
/
@l
=
PCC=0010
./
- MaIn System Clock
_
Low-speed mode
PCC..oOOO
Q
Subsystem Cock
../
V
./
Main System CI~/
HALT mode
Subsystem Cock
.,...".
100
8
()
~
c.
SOO
.....
PCC=oV --. /
~ =Middle-speed mode
-
a.
./
/
Main System Clock
IHALT mode
Main System Clock
5000
~
./
Low-speed mod~ ....
PCC.OOOO
I
.9
100 vs VOO (Ceramic Resonator at 4.19 MHz)
50
r-- Subsystem Cloc
"
CIJ
~
~
./
V
Operation mode"
I
0-
10
*
c.
""
/
/
I-'I-'1
o
* i n syrm
./
/
*
/
1== Su system Clock
5
*
eli
3
r-
HALT mode
*
* rln syslem Cloci In STOr mode.
J
t-
In STOr mode.
1
2
./
10
HALT mode"
II
I
I
t---Subsystem CI ~•
Operation mode /
j
r- Subsystem Clock
5 I-'-
II
50
"
CIJ
4
5
Power Supply Voltage V DO (V)
6
7
o
2
3
4
5
6
7
Power Supply Voltage V DO (V)
Note: Values of 100 are about 10% larger using a ceramic resonator
as compared to a crystal resonator.
4-169
NEC
pPD753Ox/31X/P308/P316
FIgure 17. DC ChIIret:ferlstlCtl (conI)
100 vs Voo (Ceramic Resonator at 1.00 MHz)
IDO vs VOO (Ceramic Rasonator at 2.00 MHz)
~A-2 OC
::TA-2 'C
5000
5000
~Iock
M.ln ! ystem
Maln System CI
Hglwpeed m~ ....-:::
PCC-0011 ..".
1000
Ir:
PCC-0010' /
~
, Maln System Clock /
Low-speed mode
0
~
!
~
g.
MaIn systitm Clock
Middle-speed mod.
500
V
PCC-Oooo
MaIn system Clock
100
v;:
,
Ir:
/'
i
d
t,
50
t--~b~stem CI......
Operadon mod.....
I
*
5
/'
,
50
/
/
Cperating mod. /
/
10
~Su system CI
t--
HALT
inod
5
o
osdllaUon and
I HALT linod.
1
2
3
4
Maln ~stem dock
STOP mod. + 32 KHz
r- *r n ~.rm d j k1 ST, mode.
5
Power Supply Voltage Voo (V)
4-170
Subsystem C ock
Maln System Clock
HALT mode
100
*
1
/'
PCC-O~/
I
~
/
10
Maln System Clock '"Y..
Low-speed m~
~
/
~
'PCC-OO'J.!l
500
~
Subsy.tein C ock
System ( lock
~
Maln SySt8m Clock
Middle-speed mode
~
/
HALT mode
til
PCC..ooll
1000
./
1/
~.In
Maln System,·Clock
High-speed mod~"
8
7
o
2
3
4
5
Power Supply Voltage VOO (V)
6
7
NEe
,..PD753Ox/31x/P308/P316
Figure 17. DC Characteristics (cont)
IOL vs VOL (Ports 0, 2, 6, 7)
IOL vs VOL (Ports 3, 4, 5)
40
40~---r----~--~----~--~
f---TA =1 25,<:
r---TA= k5'C--t----t---t---1
'-r-r
VOO=6V
30 1---'
I
_
VOO=5V
30 VOO -6V r T / V OO =4V
VOO=4V-
VOO =5V
".-
I
III /
I /
1
II
I /
20
/I
III
rl/
,....
If . /
I ~
10
'I
'I ../'
VOO=3V
~
V
----
VOO=3V
II
Voo = 2.7 V
I~
Voo = 2.7 V
'LL
10
//
'!/
1/
If
!fJl
:1
o
I
~
2
3
4
5
0
2
3
4
5
VQL(V)
4-171
t-{EC
IlPD753Ox/31X/P308/P316
Figure 17. DC Characteristics (cont)
VOL vs IOL (BPO· 3, BP4· 7)
VOL vs IOL (BPO· 3, BP4· 7)
200r---------~----------,-----------,
~Or------r----~;-----'-----~------'
*
(Voo = SV. TA= 25°C)
*
Number of
Number of
700
600
500
~
~
1-'
I~
2
400
100
1-'
_0
_0
3
100
300
4
200
50
* to BP7. BPO to BP3
or BP4
number of pins
outputting the sarne level.
100
I
a:
a
::l
2
3
VOL (V)
4-172
*
Of pins
4
5
a
Of pins BPa to BP3 or BP4
to BP7. number of pins
outputting the sarne level.
I
~
a
2
VOL (V)
3
NEe
pPD753Ox/31X/P308/P316
Figure 17. DC Characteristics {cont}
Voo· VOH vslOH (BPO· 3, BP4· 7)
Voo • VOH vslOH (Ports 0, 2·7)
20
r--TA=~S"C
-600
.----.,.--..,....---r----,.--....,
-soo
J---+--+--t-
* concurrent
Number of
outputs:
15 r--voo-avT VVoo_sv
/
-400
II
II
II I
./'"
I /'
JlI/
II II
/I
III . /
f/I ~---
S
---
VOOE4V
Ir:
,"
3
·200
VOO -3V
4
VOO -2.7V
-100
"V/
2
II
:J:
_0
~///
o
2
~ -300
3
Voo-VOH(V)
4
I
S
1---h-~~-7"''-+-~--+----I---I
2
3
4
S
VOO-VOH(V)
4-173
t\'EC
IlPD753Ox:/31x/P308/P316
Figure 17. DC Characteristics (conI)
Voo· VOH vs IOH (BPO· 3, BP4· 7)
fxx
3
-200 . . .- - - - . . , . . - - - - . . . . . , - - - - - - ,
.
I
VS
100
I
I
~:
f- (VOO = 5V, TA= 25°C)
* concurrent
Number of
outputs:
-150
1-----+--7""--1------1
High-speed mode
PCC=OO/,
2
~dle-speed
V
"5
c.
~
2
~ -100 J------j~+------:Ii:=----_I
~
_0
3
V
V
4
* toOf
pins BPO to BP3 or BP4
BP7, number of pins
outputting the same level.
o
VOO-VOH(V)
4-174
/'"
Low-speed modePCC=OOOO
I
1
o
-
Main systej Clock -
~
3
modePCC=0010
/
/'
~
~__~____~__~i
2
/
/
l/
HALTmJde
I
o
2
3
fxx (MHz)
4
5
NEe
pPD753Ox/31X/P308/P316
Figure 17. DC Characteristics (conI)
IxxvslOO
0.5 .....- - , - - - . . , . . - - . . . , . - - -.....- - - ,
High-speed mode
PCC-0011
0.4 t----t--1,..--+~~
~
C5.
0.3
~
!
C
~
0.2
0.1
II
o
!xx (MHz)
AC Characteristics (,£PD7530x131x only)
TA
= -40 to +85"0; Voo = 2.7 to 6.0 V
Parameter
Symbol
Min
Cycle time
(Note 1)
tOY
(Figure 19)
0.95
Jrl
(Figure 20)
TIO Input low- and high-level width
Interrupt Inputs
low- and high-level width
RESET low level width
Max
Unit
64
lIS
Conditions
Marn system clock; Voo= 4.5 to 6.0 V
64
lIS
Main system clock; VOO = 2.7 to 6.0 V
125
lIS
Subsystem clock
0
1
MHz
VOO =
0
275
kHz
VOO = .2.7 t~ 6.0 V
3.8
114
TIO Input frequency
Typ
122
4.5toMV
tTIH' trlL
(Figure 20)
0.48
lIS
Voo = 4.5 to 6.0 V
1.8
lIS
Voo = 2.7 to 6.0 V
tiNT HitlNTL
(Figure 21)
(Note 2)
lIS
INTO
10
lIS
INTt. 2.4
10
lIS
KRO-KR7
10
lIS
tRSL
(Figure 22)
Notes:
(1) Cycle time (minimum instruction execution time) is determined
by the frequency of the oscillator connected to the microcomputer. system clock control register (SCC). and the processor
clock control (PCC). See figure 19.
(2) 2tOY or 128/1x• depending on the setting of the interrupt mode
register (IMO).
4-175
NEe
pPD753Ox/31x/P308/P316
Figure 18. AC Timing Measurement Points
(exceptXI andXTI)
Figure 20.
TlO Timing
0.8 VDD _ _ Measurement _o.8 VDD
0.3 VDD -
points
-
0.3 VDD
83RI)..7302A
8aRD-845M
Figure 19. Guaranteed Operating Range
Figure 21. Interrupt Input Timing
(pPD753OX/31x only)
tCY
VS
Voo (With main system clock)
INTO,1,2,4
70
~~~~
KRO-7
83R().6747A
~~
~R:
~~
Figure 22. RESET Timing
6
RESET Input Timing
5
4
RESET
3
-.~'~'}'\..._
83RD-6748A
2
1
.'
i
a:
Ii!
.5
°°
4-176
2
3
4
5
Power Supply Voltage VDD (V)
6
7
NEe
pPD753OX/31X/P308/P316
Serial Transfer Operation (J£PD7530X/31x only) (see figures 18, 23)
2-lIne/3-lIne Serial VO mode (SCK = internal clock output)
TA = -40 to + 85°C; Voo" 2.7 to 6.0 V
Parameter
Symbol
Min
Unit
Conditions
SCK cycle time
IKCY1
1600
n8
VOO
3800
n8
Voo
0.5 tKCY1 -50
n8
Voo .. 4.5 to 6.0 V
0.5 tKCY1 -150
n8
Voo .. 2.7 to 6.0 V
n8
SCK low- and high-level width
tKH1/ t KL 1
SI va SCK t setup time
1sIK1
150
SI va SCK t hold time
tKSI1
400
SCK' to SO output delay time
Typ
Max
= 4.5 to 6.0 V
= 2.7 to 6.0 V
ns
tKS01
250
n8
VOO '" 4.5 to 6.0 V
1000
n8
VOO
= 2.7 to 6.0 V
Serial Transfer Operation (J£PD7530x131x only) (see figures 18, 23)
=
2-lIne/3-lIne Serial VO mode (SCK
external clock output)
TA" -40 to + 85°C; VOO
2.7 to 6.0 V
=
Parameter
SCK cycle time
SCK low- and high-level width
Symbol
Min
Unit
Conditions
IKCY2
800
n8
Voo .. 4.5 to 6.0 V
3200
n8
VOO" 2.7 to 6.0 V
400
n8
VOO .. 4.5 to 6.0 V
1600
ns
VOO
ns
tKHi tKl2
SI va SCK t setup time
tSIK2
100
SI va SCK t hold time
tKSI2
400
SCK l to SO output delay time
tKS02
Typ
Max
= 2.7 to 6.0 V
ns
300
n8
Voo
= 4.5 to 6.0 V
1000
n8
Voo
= 2.7 to 6.0 V
4-177
II
NEe
pPD753Ox/31x1P3081P316
SBI Mode ijlPD7530X/31 x only) (see figures 18,23)
SCK = internal clock output (master)
TA = -40 to +8S'C;Voo = 2.7 to 6.0 V
Parameter
Symbol
Min
Unit
Conditions
SCK cycle time
tKCY3
1600
ns
Voo = 4.S to 6.0 V
3800
ns
Voo = 2.7 to 6.0 V
SCK low- and high-level width
tKH:Y tKL3
O.S tKCY:;SO
ns
Voo = 4.5 to 6.0 V
0.5 tKCy:;150
ns
Voo = 2.7 to 6.0 V
ns
Typ
Max
SBO, SB1 vs SCK t setup time
tSIK3
150
SBO, SB1 vs SCK t hold time
tKSI3
0.5 tKCY3
tKS03
0
250
ns
Voo = 4.5 to 6.0 V
0
1000
ns
Voo = 2.7 to 6.0 V
SCK ~ to SBO, SB1 output delay time
ns
SCK tto SBO, SB1 ~
tKSB
tKCY3
ns
SBO, SB1 Ho SCK ~
tSBK
tKCY3
ns
SBO, SBl low-level width
tSBL
tKCY3
ns
tKCY3
ns
SBO, SB1 high,level width
tSBH
SBI Mode ijlPD7530x/31x only). (see figures 18, 23)
SCK = external clook output (slave)
TA= -40 to +8S'C; Voo = 2.7 to 6.0 V
Parameter
Symbol
Min
Unit
Conditions
SCK cycle time
tKCY4
800
ns
Voo = 4.5 to 6.0 V
3200
ns
Voo = 2.7 to 6.0 V
SCK low- and high-level width
tKH.v tKL4
400
ns
Voo = 4.5 to 6.0 V
1600
ns
Voo = 2.7 to 6.0 V
ns
SBO, SBl vs SCK t setup time
tSIK4
100
SBO, SB1 vs SCK t hold time
tKSI4
0.5 tKCY4
tKS04
0
SCK ~ to SBO, SB1 output delay time
0
Typ
Max
ns
300
.ns
Voo = 4.5 to 6.0 V
1000
ns
Voo = 2.7 to 6.0 V
ns
SCK flo SBO, SB1 •
tKSB
tKCY4
SBO, SB1 Ho SCK ~
tSBK
tKCY4
ns
SBO, SB1 low-level width
tSBL
tKCY4
ns
SBO, SB1 high-level width
tSBH
tKCY4
ns
4-178
NEe
pPD7530x131x/P308/P316
Figure 23. Serial Transfer Timing
Serial 110 Mode (3-Llne)
Serial 1/0 Mode (2-Llne)
tKCY1
I+-tKL1SCK
_ t KH
=!
\
'\
tSIK1
tKSI1
Input Data
SI
...
S80,1
~>f: -O-U~-u-tD-a-ta ~)(r
tKS01_
SO ...............
.....
...............
I]
SBI Mode Bus Release Signal Transfer Timing
SCK
S80,1
SBI Mode Command Signal Transfer Timing
S60,1
83RD-s904B
4-179
NEe
IIPD7530x/31X/P308/P316
Data Memory STOP Mode Low Voltage Data Retention Characteristics
(;£PD7530X131x) (see figure 24)
.
TA = -40 to + 85"0
Parmeter
Symbol
Min
Data retention voltage
VOOOR
2.0
Data retention current (Note 1)
IOOOR
Release elgnal eet time
tSREL
Oscillation etablllzation time (Note 2)
tWAIT
Typ
0.1
0
Max
Unit
6.0
V
10
!IA
Conditions
VOOOR
= 2.0 V
Jls
(Notes 3, 4)
ms
Release by RESET Input
(Note 3)
ms
Release by interrupt request
Notes:
(1) Excludes current In the pullup reslstore.
(2) Oscillation etablllzation WArr time Is the time during which the
CPU Ie stopped and the crystal ie stabilizing. This time is
required to prewnt unstable operation while the oscillation la
etarted. The Interval timer can be used to delay the CPU from
executing Instructions using the basic interval timer mode
register (BTM) according to the following table:
BTM3
4-180
BTM2
BTM1
BTMO
WArrtlme (fxx
0
0
1
1
0
1
0
1
0
1
1
1
220/fxx
2 17/fxx
2 15/fxx
213/fxx
= 4.19 MHz)
(Approx 250 ms)
(Approx 31.3 ms)
(Approx 7.82 ms)
(Approx 1.95 ms)
(3) Consult the manufacturer's resonator or crystal specification
aheat for this value.
(4) The Interval timer will cause a delay of 217Jfxx after a reset
NEe
pPD753Ox/31X/P308/P316
Figure 24. Data Retention Timing
A. STOP mode Is released by RESET Input
Internal reset
operation
t:'
t
VDD
I
II
STOP mode
I
1
Data retention mode _ _
VDDDR
HALT mode
Operation
mode
/
Execution of
STOP Instruction
\ I\.....J
I-- tSREL
tWAIT
II
B. STOP mode Is released by Interrupt signal
HALT mode
t:
_
t
-----STOPmode
5-S
I
--------*'11-'1_-14- ~:."tlon
Data retention mode
VDDDR
Execution 01
STOP Instruction
Standby release signal
(Interrupt request)
83RD-64568
4-181
pPD753Ox/31X/P308/P316
Recommended Ceramic Resonators
(,£PD75P308/P316)
voo
= 4.75 to 5.25 V; TA = -10 to + 7(1'C
C1
C2
Manufacturer
Part Number
(PF)
(PF)
Murata
CSA2.00MG
30
30
CSA4.19MG
CSA4.91MGU
30
30
30
30
CST4.19MG
(NOte 1)
(Note 1)
Remarks
Notes:
(1) 30 pF capacitors are Internally provided.
DC Characteristics, (JIPD75P308JP316)
TA = -10 to +7(1'0; VOO
=5V±
5%
Parameter
Symbol:,
Max
Unit
High-level input voltage
VIHI
' 0.7VOO
VOO
V
Ports 2, 3
VIH2
0.8VOO
VOO
V
Ports 0, 1, 6, 7; RESET
VIH3
0.7
10
V
Ports 4, 5; open drain
VIH4
Voo-O.5
VOO
V
X1, X2, XT1
VILI
0
0.3 VOO
V
Ports 2, 3,
VIL2
0
0.2VOO
V
Ports 0, 1, 6, 7, RESET
VIL3
0
0.4
V
X1, X2,XT1
VOHI
Voo-l.0
V
Ports 0, 2, 3, 6, 7, BIAS; 10H
VOH2
VOo-2.0
V
BPo-7; 10H =' -100 JlA (Note 1)
Low-Ievellnput voltage
High-level output voltage
Low-level outpu~voltage ,
High·levelinput leakage current
Low-level input leakage current
High-level output leakage current
Min
Typ
Conditions
4, 5'
= -1
mA
2.0
V
Ports 3, 4, 5; 10L= 15 mA
0.4
V
All output pins; 10L= 1.6 mA
VOL2
0.2VOO
V
SOO, SB1 ; open drain
pullup resistor ~ lkQ
VOL3
1.0
V
IUHl
3
/lA
All except X1 , X2, and XT1; VIN
IUH2
20
/lA
X1, X2, and XT1: VIN
IUH3
20
/lA
Ports 4 and 5: VIN
IUL 1
-3
/lA
All except X1;'X2, and XT1; VIN
IUL2
-20
/lA
X1, X2, and Xl1: VIN
ILOHI
3
/lA
All output pins except ports 4, 5: VOUT
0.4
VOL 1
BPo-7: 10L = 100 JlA (Note 1)
= VOO
= VOO
= 10 V
= {J V
= 0V
= 10 V
ILOH2
20
/lA
Ports 4, 5: VOUT
Low-level output leakage current
ILOL
-3
/lA
VOUT
Internal pullup resistor
RU
15
80
kQ
Ports 0-3, 6, 7 (except POol: VIN
LCD drive voltage
VLCO
2.5
VOO
V
LCD output voltage deviation:
common (Note 7)
VOOC
0
±0.2
V
LCD output voltage deviation:
segment (Note 7)
Voos
0
40
= OV
10 = ±5/lA:
VLCO
VLCOO
2.75 V to VOO:
VLCOI
2/ 3VLCO
VLCD2
1/3VLCO
=
=
=
±O.2
V
=
=
10
±1 JlA:
VLCO
VLCOO
2.75 V to VOO:
VLCOI = 2/3VLCO
VLCD2
1/3VLCO
=
=
=
=0V
= Voo
ttlEC
"PD753Ox/31X/P308/P316
DC Characteristics (J£PD75P30B/P316) (cont)
Parameter
Supply current
(Note 2)
Typ
Max
Unit
1001
5.0
15.0
rnA
(Notes 3, 4)
1002
500
1500
JlA
HALT Mode (Note 3)
1000
350
1000
JlA
(Notes 5, 6)
35
100
JlA
HALT mode (Notes 5, 6)
0.5
20
JlA
STOP mode; xn = OV
(Note 6)
Symbol
Min
10D4
Conditions
Notes:
(1) When any two pins of BPO-BP3 and any two pins of BP4-BP7 are
used simultaneously for output
(2) Does not Include pullup resistor current
(3) 4.19 MHz crystal oscillator; Cl = C2 = 15 pF, and subsystem
clock running.
(4) Value during high-speed operation and the processor control
clock (PCC) is set to 0011.
(5) Value when the system clock control register (SOO) is set to 1001 ,
generation of the main system clock pulse is stopped, and the
SOO is operated by the subsystem clock.
(6) 32 MHz crystal oscillator.
(7) Voltage deviation Is the difference between the ideal value of
segment or common output (VLCOn; .n = 0, 1, 2) and the output
voltage.
AC Characteristics (J£PD75P308/P316) (see figure 18)
= -10 to + 70"0; VOO = 5 V :I: 5%
TA
Symbol
Min
tcv
(Figure 20)
0.95
TIO Inputfrequency
frl
(Figure 20)
.0
MHz
TIO input low- and high-level width
trlH, trlL
(Figure 20)
0.48
Jls
Interrupt inputs
low- and high-level width
tiNT WtINTL
(Figure 21)
(Note 2)
Jls
INTO
10
Jls
INn, INT2, INT4
KRO-KR7
RESET low level width
tASL
(Figure 22)
10
JlS
114
Typ
Conditions
Parameter
Cycle time
(minimum instruction execution time - Note 1)
122
Max
Unit
64
JlS
.Main system clock
Jls
Subsystem clock
125
Notes:
(1) Cycle time is determined by the frequency of the oscillator
connected to the microcomputer, ,ystem clock control register
(SOO), and the processor clock control (POO). See figure 25.
(2) 2tcv or 128/fxx, depending on the setting of the interrupt mode
register(IMO).
4-183
II
NEe
pPD753Ox/31x/P308/P316
Figure 25. Guaranteed Operating Range fpPD75P308/P316)
tCY vs Voo (Using main system clock)
70
64
F
60
~~
6
~~
~~
~~
~~
~
~~
5
i
4
3
I
2
Ii
Ii
•••••••
I
Ii....
0.5
o
2
3
5
4
6
7
Power Supply Voltage VDO (V)
Serial Transfer Operation (J£PD75P308/P316) (see figures 18, 23)
2-line/3-line serial I/O mode (SCK = internal clock output
TA = -10 to + 70°C; Voo = 5 V ± 5%
Parameter
Symbol
Min
SCK cycle time
tKCY1
1600
ns
SCK low- and high-level width
tKL 1/tKH1
0.5 tKCY1-50
ns
SI set-up time (against SCK t)
tSIK1
150
ns
SI hold time (against SCK t)
tKSI1
400
SCK + to SO output delay time
tKS01
4-184
Typ
Max
Unit
ns
250
ns
Conditions
NEe
pPD753OX/31x/P308/P316
Serial Transfer Operation ij£PD75P308/P316) (see figures 18, 23)
2-line/3-line serial I/O mode (SCK = external clock input
TA = -10 to +70'C; Voo = 5 V ± 5%
Parameter
Symbol
Min
SCK cyole time
tKCY2
800
Typ
Max
ns
SCK low- and high-level width
tKl2" tKH2
400
ns
SI set-up time (against SCK t)
tSIl<2
100
ns
SI hold time (against SCK t)
tKSI2
400
SCK I to SO output delay time
tKS02
Unit
Conditions
ns
ns
300
S81 Mode ij£PD75P308/P316) (see figures 18, 23)
SCK = internal clock output (master)
TA = -10 to + 70'C; Voo = 5 V ± 5%
Parameter
Symbol
Min
SCK cyole time
tKCY3
1600
ns
SCK low- and high-level width
tKHaltKl3
0,5 tKCy:;-50
ns
SBO, SBl vs SCK t setup time
tSIK3
150
ns
SBO, SBl vs SCK t hold time
tKSI3
O,5tKCY3
ns
SCK I to SBO, SBl output delay time
tKS03
SCK t to SBO, SBl I
tKSB
tKCY3
ns
SBO, SBl Ito SCK I
tSBK
tKCY3
ns
SBO, SBl low-level width
tSBl
tKCY3
ns
SBO, SBl high-level width
tSBH
tKCY3
ns
Typ
0
Max
250
Unit
Conditions
II
ns
S81 Mode ("PD75P308/P316) (see figures 18, 23)
SCK = external clock input (slave)
TA = ~10 to + 70'C; Voo = 5 V ± 5%
Parameter
Symbol
Min
SCK cycle time
tKCY4
800
ns
SCK low- and high-level width
tKH¥ tKl4
400
ns
SBO, SBl vs SCK t setup time
tSIK4
100
ns
SBO, SBl vs SCK t hold time
tKSI4
0,5 tKCY4
SCK I to SBO, SBl output delay time
tKS04
0
SCK t to SBO, SBl I
tKSB
tKCY4
ns
SBO, SBl I to SCK I
tSBK
tKCY4
ns
SBO, SBl low-level width
tSBL
tKCY4
ns
SBO, SBl high-level width
tSBH
tKCY4
ns
Typ
Max
Unit
Conditions
ns
300
ns
4-185
NEe
pPD7530X131x/P308/P316
Data Memory STOP Mode Low Voltage Data Retention Characteristics
(p.PD75P308/P316) (see figure 24)
TA = -10to + 70°C
Parameter
Symbol
Min
Data retention voltage
VOOOR
2.0
Data retention ourrent (Note 1)
IOOOR
Release signal set time
tSREL
Osoillation stabilization time (Note 2)
tWArr
Typ
Max
Unit
6.0
V
10
JlA
0.1
0
Conditions
VOOOR
= 2.0V
Jis
(Notes 3, 4)
ms
Release by RESET input
(Note 3)
ms
Release by interrupt request
Notes:
(1) Exoludes current in the pullup resistors.
(2) Oscillation stabilization WAIT time is the time during whioh the
CPU Is stopped and the crystal is stabilizing. This time is
required to prevent unstable operation while the oscillation is
started. The interval timer can be used to delay the CPU from
executing instructions using the basic interval timer mode
register (BTM) aooording to the following table:
BTM3
BTM2
0
°
1
1
BTM1
0
1
0
1
BTMO
0
1
1
1
(3) Consult the manufacturer's resonator or crystal speoifioation for
this value.
(4) The interval timer will oause a delay of 2 17ffxx after a reset.
WAITtime (f"" = 4.19 MHz)
220ff"" (Approx 250 ms)
217ff"" (Approx 31.3 ms)
215ff"" (Approx 7.82 ms)
213ff"" (Approx 1.95 ms)
DC Programming Characteristics (p.PD75P308/P316)
TA = 25 ± 5°C; Voo ~ 6.0 ± 0.25 V; Vpp = 12.5 ± 0.3 V; Vss = 0 V
Parameter
High-level input voltage
Low-level Input voltage
Max
Unit
VIHI
O· 7V oo
VOO
V
All exoept X1, X2
VIH2
VOo-°·5
VOO
V
X1, X2
0.3VOO
V
All exoept X1, X2
0.4
V
X1,X2
10
JiA
VIN
V
IOH
Symbol
Min
VIL1
°
0
VIl2
Input leakage current
III
High-level output voltage
VOH
Typ
Voo-1.0
LOW-level output voltage
VOL
0.4
V
VOO supply ourrent
100
30
mA
Vpp supply current
Ipp
30
mA
Conditions
= Vll.or VIH
= -1 mA
IOl = 1.6 mA
MDO
= Vll; MD1 = VIH
Notes:
(1) Vpp must not exceed +13.5 V, including overshoot.
4-186
(2) VOO must be applied before Vpp and VOO should be removed
after Vpp is removed.
ttlEC
pPD7530x131xJP308/P316
AC Programming Characteristics (,£PD75P308/P316) (see figures 26, 27)
TA
= 25 ± 5'C; VOO = 6.0 ± 0.25 V; Vpp = 12.5 ± 0.3 V; Vss = 0 V
Parameter
Symbol
Address setup time to MOO ~ (Note 2)
tAS
MDl to MDO ~ setup
tM1S
Data to MDO ~ setup
Address hold from MOO
Data hold from MDO
t
(Note 2)
t
Data output float delay from MOO
t
(Note 1)
Min
Max
Unit
tAS
2
jlS
tOES
2
jls
tos
tos
2
jls
lAH
tAH
2
jlS
tOH
tOH
2
tOF
tOF
0
2
Conditions
jlS
130
ns
t
VOO setup to MD3 t
tvps
tvps
tvos
tvcs
2
Initialized program pulse width
tpw
tpw
0.95
1.05
ms
.Additional program pulse width
topw
topw
0.95
21
ms
tMOS
tCES
2
jls
t[N
t[}l
jls
MDO
= MDl = VIL
tM1H
tOEH
2
fJs
tM1H
tM1R
tOR
2
fJs
tM1H
+
+
10
fJs
Vpp setup to MD3
t
MOO setup to MDl
Data output delay from MOO ~
MDI hold to MOO
t
MDI recovery from MDO
~
Program counter reset
tpCR
jls
jlS
0.125
XI input low- and high-level width
txH, txL
Xl input frequency
Ix
Initial mode set
tl
2
fJS
tM35
2
fJS
MD3 hold to MDI ~
tM3H
2
fJs
MOO setup to MOO ~
tM3SR
2
fJs
Address to data output delay time (Note 2)
tOAD
1&.cc
2
fJs
Address to data output hold time (Note 2)
tHAD
tOH
0
MOO setup to MDI
t
MOO output hold from MOO
t
Data output float delay from MOO ~
tM1R :!: 50 fJI
tM1R :!: 50 jlS
fJs
4.19
130
MHz
During Program
Relid cycle
ns
tM3HR
2
fJS
tOFR
2
fJs
Notes:
(1) These sym bois correspond to those on the fJPD27C256 EPROM.
(2) The internal address signal Is Incremented by one at the rising
edge of the fourth Xl pulse; it is not connected to an external pin.
4-187
II
N'EC
pPD753Ox/31X/P308/P316
Figure 26. EPROM Progrsm Memory Write Timing
Vpp
vpp
~--------------~6------------~------~$~
VDD
tVDS
~------------~~~--------------~~--~5r--
Xl
S
tM1H
6
tM3S
~
S
'-~
5.
83RD-70488
4-188
NEe
pPD753Ox/31x/P308/P316
Figure 27. EPROM Program Memory Read Timing
IVPS
Vpp
Vpp
Voo
IVOS
XI
DataOUlpUI
~~g:~~~ --+-+----(1
~--------------~
II
OataOutpUI
IOV
MOO
MOI ..........~..........~........................................................................................................................~~..........~...............--
M02
I M3SR
M03
83RO-64618
4-189
pPD753OX/31X/P308/P316
NEe
NEe
pPD75328/75P328
4·Bit Microcomputers
With LCD Controller/Driver
and AID Converter
NEG Electronics Inc.
Description
The J.lPD75328 and J.lPD75P328 are high performance
single-chip CMOS microcomputers. They each contain
a CPU, ROM, RAM, interval timer, timer/event counter,
watch timer, LCD controller, A/D converter, subsystem
clock, serial interface, I/O ports, and vectored interrupts. The instruction set allows the user to manipulate
RAM data arid I/O ports in one-, four-, and eight-bit
units. The devices are suitable for controlling video
caS&ette recorders (VCRs), telephones, and meters.
The J.lPD75P328 is a one-time programmable (OTP)
version of the J.lPD75328.
Features
o 103 Instructions
- Bit manipulation instructions
- Four-bit and eight-bit transfer instructions
- One-byte relative branch instructions
- GETI instruction converting 1 two-byte or threebyte instruction or 2 one-byte instructions into 1
one-byte instruction
o Instruction execution cycles
- High-speed cycle: 0.95 J.lS/4.1.9 MHz
-Low-voltage cycle: 1.91 J.lS/4.19 MHz,
15.3J.ls/4.19 MHz,
o Program memory (J,lPD75328/75P328): 8064 bytes
o Data memory (RAM)
- Allows operation on one, four, and eight bits
- 512 x four-bit data
o Timers
- One eight-bit basic interval timer
- One eight-bit timer/event counters
- One fourteen-bit watch timer
o AID converter
- Six-channel
-Eight-bit
o LCD controller/driver
- Four common lines
- Twenty segment lines
- Operational modes
Static
Multiplexed 1/2 bias
Triplexed 1/2 or 1/3 bias
Quadriplexed 1/3 bias
II
o Eight-bit serial interface
-Serial bus in (SBI) mode
- Two or three wire mode
Data transfer (MSB or LSB first)
Full duplex mode
Receive only mode
o Vectored interrupts
- Three external interrupts
- Three internal interrupts
- Nine inputs generating one interrupt request
o Standby modes
- Halt mode: stops CPU only
- Stop mode: stops main system clock
o Bit-sequential buffer
-16-bit, bit manipulation memory
o Mask options (Not available on the J.lPD75P328)
- Pull-up resistors for ports 4 and 5
- LCD resistor ladder
-Subsystem clock feed back resistor
o Eight four-bit registers
o Operates with oscillator or ceramic resonator
o Accumulators
- One-bit accumulator (CY)
- Four-bit accumulator (A)
- Eight-bit accumulator (XA)
o CMOS technology (at 5 V and 4.19 MHz)
- Normal operation: 2.5 mA (typical)
- Halt mode: 0.5 rnA (typical)
- Stop mode: 0.1 J.lA (typical)
o 241/0 lines
- Twelve output ports that can directly drive LEDs
(sink 15 mA rms)
- Eight N-channel, open-drain outputs with 10 V
maximum
o One-time programmable (OTP) version
(J,lPD75P328) available
Ordering Information
Package
ROM
o 12 Input only lines
pPD75328GC-xxx-3B9
80-pin plastic QFP
Mask
o One external event input
pPD75P328GC-3B9
80-pin plastic QFP
OTP
Part Number
Notes:
(1) xxx indicates ROM code suffix.
50255
4-191
ttlEC
pPD7S32snSP32S
Pin Configuration
SO-Pin Plastic QFP
g
~ ~ ~ ~ ~ ~ ~ ~ ~
R m~
~ ~ ~ ~ ~ ~ ~
0
S311BP7
S30lBP6
S291BP5
1
2
3
S281BP4
4
P83
5271BP3
526IBP2
P82
523
5
6
7
8
9
522
521
520
10
11
12
519
518
13
14
517
516
15
16
515
514
17
P131T10
P1211NT2
18
19
20
P1111NT1
P101lNTO
P031511SB1
S25 1BP1
524IBPo
513
512
59
AN2
AN1
ANO
P81
P80
P331MD3·
P321MD2·
P3115YNCIMD1·
50
P30ILCDCUMDO·
49
P231BUZ
P221PCL
P21
P20lPTOO
41
• MDO-MD3 and Vpp are for programming the J1PD75P328.
49NR-G07B
4-192
~EC
IIPD75328/75P328
Pin Identification
Symbol
Function
POoflNT4
Port 0 input; Interrupt 4.
P01/S"CR
Port 0 Input; serial clock ~
POiSO/SBO
Port 0 input; serial data out
POalSI/SBl
Port 0 input; serial data in
P10-P2/1NTO-INT2
Port 1 inputs; interrupts INTO-INT2
Pla1TIO
Port 1 input; timer 0 Input TIO
P201PTOO
Four-bit I/O port 2 (P2o-P2a)/timer/event
-P2-=1----- counter output 0 (PTOO)/port clock output
_ _ _ _ _ _ (PCL)/buzzer output (BUZ)
P22/PCL
P2a1BUZ
P301LCDCL/
(MDo)
';"P3-1"::'S/'--Y-NC-/-(M-D-1-)-
Four-bit I/O port 3 (P3o-P3al/LCD clock
output (LCDCL)/sync output (SYNC)/OTP
operation mode (MDo-MD3 for "PD75P32B)
also used for the serial interface in the SBI or 2/3 wire
mode. The serial input (SI) and serial bus one (SB1),
serial output (SO) and serial bus zero (SBO), and the
serial clock (SCK) make-up the serial interface. Port 0 is
in the input mode at reset.
P13/T10, P12/INT2, P11/INT1, P1011NTO
(Port 1 , Edge-Triggered Interrupts, Timer Input)
Port 1 can be used as a four-bit input port. INTO and INT1
are edge-triggered vectored interrupts. INT2 is an edgetriggered input which generates an input request, but
does not cause an interrupt. TIO is an input clock to the
timer/event counter and is used to count external events.
Port 1 is in the input mode at reset.
P23/BUZ, P22/PCL, P21, P201PTOo
(Port 2, Clock, Buzzer, and Timer/Event Counter
Outputs)
P32-P3a1(MD2-MDal
P40-P43
Four-bit I/O port 4
P50-P53
Four-bit I/O port 5
peo-peal
KRo-KR3
Four-bit I/O port e (P6o-Peal/
key scan inputs 0-3 (KRo-KRal
Four-bit I/O port 7 (P7o-P73)/
key scan inputs 4-7 (KR4-KR7)
PBo-PB3
Four-bit I/O port B
LCD segment outputs 12-23
COMo-COM3
LCD common outputs 0-3
Eight one-bit output ports (BPO-BP7)/
LCD segments 24-31 (S24-8 31 )
LCD voltage drive level
BIAS
ANO-ANs
LCD power bias output
AID converter inputs (ANo-ANsl
AID converter reference voltage'
AVss
Port 2 can be used as a four-bit I/O port. When used as
an output port, the output data is latched. When used as
an input port, the outputs are high-impedance. P20 is
used to output the timer/event counter flip/flop signal
TOUT. P22 is used to out putt he PCl clock from the clock
generator and P23 is used to output square waves for a
buzzer. Port 2 is in the input mode at reset.
AID converter ground
NC (Vpp)
No connection (Vpp for "PD75P32B)
X2,Xl
Main clock inputs
XT2,XTl
Subsystem clock inputs
Reset Input
Voo
Positive power supply
Vss
Ground
PIN FUNCTIONS
P33/MD3, P32/MD2, P31/SYNC/MD1,
P30/LCDCL/MDo (Port 3, LCD Outputs,
OTP Operation Mode for I'PD75P328)
Port 3 is a programmable four-bit I/O port. Each bit can
be independently programmed to be either an input or an
output. The port has latched outputs and can directly
drive LEOs. P30 and P31 can be used to output the LCO
clock and LCO sync signal, respectively. MOo through
M03 are used for the ~P075P328 OTP program memory
write and verify mode to select the operation mode. Port
3 is in the input mode at reset.
P40·P43 (Port 4)
Port 4 isa four-bit I/O port. Ports 4 and 5 can be paired
together to function as one 8-bit port. Port 4 has latched
outputs and can directly drive LEOs. The outputs are
N-channel, open drain, 10 V max. An internal pull-up
resistor is available as a mask option. Port 4 is in the
input mode at reset.
P03/SI/SB1, PO:z/SO/SBO, P01/SCK, POo/INT4
(Port 0, INT4, Serial Interface)
Port 0 can be used as a four-bit input port. POo can be
used for INT4 which is an edge-triggered vectored interrupt triggered by a rising or falling edge. P01-P03 are
4-193
II
NEe
pPD75328/75P328
P50-P53 (Port 5)
BIAS (Bias Output)
Port 5 is a four-bit I/O port.Ports 4 and 5 can be paired
together to function as one a-bit port. Port 5 has latched
outputs and can directly drive LEOs. The outputs are
N-channel, open drain, 10 V max. An internal pull-up
resistor is available as a mask option. Port 5 is in the
input mode at reset.
BIAS output is used with VLca through VLC2 to set the
static, 1/2 bias, or 1/3 bias levels.
P631KR3-P601KRo
(Port 6, Edge Detection of KRo-KR3)
Port 6 is a programmable four-bit I/O port. Port 6 has
latched outputs and each bit can be independently
programmed to be either an input or an output. Ports 6
and 7 can be paired together to function as one a-bit
port. Port 6 can be used to detect the falling edge of
inputs KRo- KR3.Port 6 is in the input mode at reset.
P73/KR7-P701KR4
(Port 7, Edge Detection of KR4-KR7)
Port 7 is a four-bit I/O port. The port has latched outputs.
Ports 6 and 7 can be paired together to function as one
a-bit port. Port 7 can be used .to detect the falling edge
of inputs KR4 through KR 7. Port 7 is in the input mode at
reset.
P80-P83 (Port 8)
Port a is a four-bit I/O port with latched outputs. Port a is
in the input mode at reset.
S12-S23 (LCD Segment Outputs)
S1Z through S23 are the LCD segment output signals
which directly drive the LCD segment inputs.
COMo-COM3 (LCD CQmmon Outputs)
COMo through COM 3 are the LCD common output signals, which directly drive the common LCD inputs.
BPO/S24-BP7/S31
(One-Bit Output Ports, Segment Outputs)
BPo through BP7 call be used as a one-bit ports or as
additional LCD segment outputs. As LQD segment outputs, they are selectable in four-bit units: BPo-BPg/S24
-S27 or BP4-BP7/S28-S31·
VLCO-VLC2 (LCD Voltage Levels)
VLCO through VLC2 are used to set the LCD drive levels.
These pins are outputs when the internal resistor ladder
mask option is selected. When an external resistor
ladder is used, the pins are inputs and must be connected to set the LCD drive levels.
4-194
ANO-AN5 (AID Converter Inputs)
ANa through AN5 are inputs to the six-channel eight-bit
AID converter.
AVREF (AID Converter Reference Voltage)
AVREF is used to supply a reference voltage to the A/D
converter.
AVss (Analog Ground)
AVss is the analog ground pin for the AID converter.
NCNpp (No Connection, programming Pin)
This pin is connected when using the I'PD75P328 and
may be left unconnected when using the p.PD75328.
When programming a device, the programming voltage
Vpp is used during the EPROM write/verify cycles. When
a device is not being programmed, this pin should be
connected to Voo.
X2, X1 (Main System Clock Inputs)
X1 and X2 are the main system clock inputs. The clock is
controlled bya crystal or a ceramic oscillator. An
external logic signal can be used as a clock source. See
figure 1.
XT2, XT1 (Subsystem Clock Inputs)
XT1 and XT2 are the subsystem clock source inputs.
These pins use a crystal, ceramic oscillator, or a logic
Signal as an input. See figure 2.
RESET (Reset)
System reset input pin (active low).
Voo (Power Supply)
Positive power supply.
Vss (Ground)
System ground.
NEe
pPD75328/75P328
Block Diagram
ANO-ANS
AVREF
AVSS ~-"_ _ _""
T10/P1 3
PTOO/P20
P4o-P43
PSo-PS3
BUZlP23
ROM
Program Memory
P6o-P63
8064 x 8 bits
Decode
and
Control
SlfSBlIP03
SOiSBOIP02
RAM
Data Memory
P7o-P73
S12 x 4 bits
P8o-P83
SCKIPO;
S12-S23
S24 IBPOS31 IBP7
INTO/P1 0
INn/P1 l
COMo-COM3
INT2IP12
Ixxl2 N
INT4IP00
VLCO-VLC2
System Clock
Generator
BIAS
Stand By
Control
CPUClockf2J
LCDCUP30
SYNc/P3 1
PCUP2 2
XTl XT2 XI
X2
1 1 1
VDD
VSS
RESET
83Yl-574OB
4-195
II
NEe
pPD75328/75P328
Figure 1. Main System Clock Configurations
The I'PD75P328 contain a one-time programmable (OTP)
program memory and the I'PD75328 contains a mask
ROM program memory. The I'PD75328 and I'PD75P328
differ only in their program memory and mask options,
but otherwise are identical in their CPU functions and
internal hardware. Their differences are shown in table 1.
Crystal or Ceramic Oscillator
Table 1. Differences between pPD75328 and
pPD75P328
External Clock *
*
When the input is an external clock, the stop mode cannot be
set because the Xt pin is connected to system ground (V SS).
49NR-60SA
Figure 2. Subsystem Clock Configurations
r I-I
Crystal Oscillator
C3
f--t-I
~4
T
330 kn
I'PD75328 AND I'PD75P328 DIFFERENCES
XT1
XT2
Item
"PD75P328
Program memory
One-time EPROM
Mask ROM
a064 x a bits
8064 x a bits
Ports 4 and 5 pullup resistor
"PD75328
OOOOH - 1F7FH
OOOOH - 1F7FH
Not offered
Mask option
LCD resistor ladder Not offered
Mask option
Subsystem clock
oscillating feed
back resistor
On-chip
Mask option
Programming pin
connecti ons
Vpp pin and one-time
EPROM program pins
None
Operating supply
voltage range
5V ±5%
2.7 to 6.0V
Package
aO-pin plastic QFP
with bent leads
aO-pin plastic QFP
with bent leads
External Clock
I'PD75328 AND I'PD75308 COMPARISON
">0--...--1 XT1
XT2
49NR-G09A
4-196
The I'PD75328 provides 7 CMOS I/O ports; the I'PD75308
has 6. The I'PD75308 does not contain an AID coriverter.
However, the I'PD75308 does have an LCD controller
with 32 segment outputs versus 20 for the I'PD75328.
Table 2 compares the features of the two devices.
NEe
pPD75328/75P328
Table 2. pPD75328 and pPD753D8 Features
Comparison
Item
"PD75328
"PD75308
ROM
8064 bytes
Same as "PD75328
RAM
512 x 4 bits
Same as "PD75328
General
purpose
register
4 bits x 8 or 8 bits x4
Same as "PD75328
Selectable from .95
Same as "PD75328
Instruction
cycle
Input/
output
port
281/0 lines
8 input only
8 output only
241/0 lines
8 input
8 output only
CMOS
input
port
8 lines shared with
I NTIS 10. Can be
pulled by software,
except for POo
Same as "PD75328
CMOS
110 port
20 lines (4 lines can
directly drive LED).
Can be pulled by
software, except for
POo
16 lines (4 lines can
directly drive LED).
Can be pulled by
software, except for
CMOS
output
port
418 lines (shared
segment output and
selected by softwa re)
Same as "PD75328
N-
8 lines can be pulled
up by mask option,
directly drive LED,
have continuous 10 V
applied
Same as "PD75328
Timer
counters
Timerlevent counter,
basic Interval timer,
clock timer
Same as "PD75328
Serial
interface
NEC-SBI serial bus
interface
Same as "PD75328
Normal clock
synchronized serial
interface
Same as "PD75328
6-channel analog
Input, 8-blt precision
Not offered
6 vector Interrupts
(3 external and
31nternaQ
Same as "PD75328
2 test inputs
(1 external and
1 InternaQ
Same as "PD75328
Parallel edge
detection for key scan
Input
Same as "PD75328
AID
converter
Interrupt
Instruction
set
POo
"PD75308
Bit: data set/reset/lest/
boolean operation
4-blt data transferl
arlthmetic/increment/
decrement/
comparison
LCD
controllerl
driver
"s/1.91 "s/15.3 "s
(4.19 MHz) and 122,.s
(32 kHz)
channel
110 port
Item
8-bit data transfer
Same as "PD75328
20 segment Qutputs
32 segment outputs
4 common outputs
Display mode:
StatiC
Multiplexed
Trlplexed
Quadriplexed
Resistor ladder
network for
LCD drive voltage
supply (mask option)
Operating
voltage
2.7 to 6.0 V
Package
80-pin plastic QFP
(.65 pitch)
Same as "PD75328
SO-pin plastic QFP
(.8 pitch)
4-197
~EC
pPD75328/75P328
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings, "PD75328/P328
TA = 25°C
Supply voltage, Voo
-0.3 to +7.0 V
Input voltage, VI1 (except ports 4 and 5)
-0.3 to Voo +0.3 V
Input voltage, VI2 &
9
"-
3
.,;
E
2
F
f'\.
~
is
0.5
o
3
2
~
r'\.
4
5
7
6
Supply Voltage, VOO (V)
49NR-70GA
II
A/D Converter Characteristics, "PD75328
TA = -10 to +85°C; Voo = 3,5 to 6,0 V; AVss = Vss = 0 V
Parameter
Symbol
Resolution
Min
Typ
8
8
Unit
Max
Absolute accuracy (Note 1)
8
bits
±1,5
LSB
Conditions
2,5 V s AVREF S VOO
Conversion time
teONV
168/fx
s
(Note 2)
Sampling time
tSAMP
44/fx
s
(Note 3)
Analog input voltage
AV'sS
V
AVREF
Analog input impedance
Mil
1000
1,0
AVREF current
2,0
mA
Notes:
(1) The absolute accuracy does not include the quantization error
(±1/2 LSB),
(2) The total conversion time until EOC =
fxx = 4,19 MHz,
1 is 40.1 p's at
(3) The time until completion of sampling is 10,5 p's (fxx= 4,19 MHz),
Note that the sampling time value is Included in the total
conversion time value,
(4) For detailed NO converter information refer to the
use~s
manual.
Serial Transfer Operatioh, "PD75328
2·Line/3·Line Serial I/O Mode (SCK, Internal Clock Output)
TA = -40 to +85°C; Voo = 2,7 to 6,0 V
Unit
Symbol
Min
tKCY1
1600
ns
sc:::K low- and high-level width
tKL1. tKH1
SI vs
sc:::K i
setup time
Typ
Max
Parameter
sc:::K cycle time
3800
ns
0,5tKCY1-5O
ns
0,5tKCY1-150
ns
ns
tSlK1
150
51 vs sc:::K i hold time
iKSl1
400
sc:::K ~ to SO output delay time
iKS01
Conditions
Voo = 4,5 to 6;0 V
Voo = 4,5 to 6,0 V
ns
250
ns
1000
ns
Voo = 4,5 to 6,0 V
4-203
t-rEC
pPD75328/75P328
Serial Transfer OpE!ratlon, "PD75328
2-Line/3-Line Serial I/O Mode (SCK, External Clock Input)
TA = -40 to +85°C; Vee = 2.7 to 6.0 V
Parameter
~oycletlme
Symbol
Min
iKcY2
800
Typ
Unit
ns
3200
ns
400
ns
Max
~ low- and high-level width
'KL2' ~H2
1600
ns
SI vs ~ f setup time
tSIK2
100
ns
SI vs ~ f hold time
~12
400
~ ~ to SO output delay time
~02
Conditions
Vee = 4.5 to 6.0 V
Vee = 4.5 to 6.0 V
ns
300
ns
1000
ns
Vee = 4.5 to 6.0 V
SBI Mode, "PD75328
SCK, Internal Clock Output (Master)
TA = -40 to +85°C; Vee = 2.7 to 6.0 V
Parameter
Symbol
Min
S'CK cycle time
~CY3
1600
ns
3800
ns
~wldth
'KL3, ~H3
Typ
Max
Unit
0.5iKcv3 -50
ns
0.5iKcY3 -150
ns
ns
SBO, SBI VS ~ f setup time
tSIK3
150
SBO, SBI vs ~ f hClld time
~13
0.5tKCY3
~ ~ to SBO, SBI output delay time
~03
0
Conditions
Vee
= 4.5 to 6.0 V
Vee = 4.5 to 6.0 V
ns
0
250
ns
1000
ns
~ flo SBO, SBI ~
~B
iKcY3
ns
SBO, SBI ~ to 'SC'K ~
tSBK
tKCY3
ns
SBO, SBI low-level width
tSBl
tKCV3
ns
SBO, SBI high-level width
tSBH
iKcY3
ns
Vee = 4.5 to 6.0 V
SBI Mode, "PD75328
SCK, External Clock Input (Slave)
TA = -40 to +85"C; Vee
= 2.7 to 6.0 V
Parameter
~CYCletlme
~ low- and high-level width
Symbol
Min
iKcv4
800
ns
3200
ns
400
ns
1600
ns
'KL4'~H4
Typ
Max
Unit
SBO, SBI VS ~ f setup time
tSIK4
100
ns
SBO, SBI VS ~ f hold time
~14
0.5~CV4
ns
~ ~ to SBO, SBI output delay time
~04
0
300
ns
0
1000
ns
~ftoSBO,SBI ~
tro-1
+---+-<> In/Out
N."h
NEe
,.,PD75328/75P328
Figure 13. Input/Output Circuits (cont)
TypeG-A
Type G-B
(S12-S31)
(COMo-COM3)
~P-Ch
~P-Ch
VLCO
VLCO
VLC1-----+
VLC1-----+
T
T
N-ch
P-ch
Output
SEG Data
+--+--<> Output
VLC2 - - - - - - - +
COM Data
-------+..---1
T
T
VLC2-----+
N- Ch
T
Type G-C
(BPO-BP7)
~
T
N-Ch
P-ch
Ilf'D75328 Type M
VDD
(P40-P43. P50-P53)
~P-Ch
VDD
VLCO
+--~-<>
Bi~~~rt~~~ - - - - - - - - - - 1
VLC2
-------+
InlOut
Data~
VLC1-----+
OutputDisable~
Output
Medium Voltage Input Buffer (+10 V)
ILPD75P328 Type M-B
(P40-P43. P50-P53)
..-----~-<>
Data~
Output Disable~
InlOul
N-ch
(+10 V)
Medium Voltage Input Buffer (+10 V)
49NR-627B
4-221
NEe
pPD7S328nSP328
Figure 13. Input/Output Circuit. (conI)
TypeM-C·
(P03)
Type V
TypaZ
(ANo-ANS)
(AVREF)
VDD
In 0--+----1
Pull-Up ResislD, Enable---t>o-1
P-eh
r---+-<>
Dala~
Output Disable
-L-/'-'
VDD
InfOut
N-ch
Reference Voltage
(From the voltage tap in
the series ,e_i_lDr ladder)
I
I
r
AVss
49NR-628B
Serial Interface
The a-bit serial interface allows the ~PD7532a to communicate with other NEC or NEC like serial interfaces.
The serial interface consists of an a-bit shift register
(SIO), serial output latch (SO), a-bit address comparator, slave address register (SVA), control registers (CSIM
and SBIC), busy/acknowledge circuitry, and bus release/
detect circuitry. See figure 14. The interface also contains a serial clock counter, clock mUltiplexer, and serjal
clock control logic. The serial interface contains a three
wire interface, which consists of the following:
• Serial Data In (SI/SB1)
• Serial Data Out (SO/SBO)
• Serial Shift Clock (SCI<)
The three serial interface operation modes are:
• Two-wire serial mode
• Three-wire serial mode
• Two-wire SBI mode
The two or three wire serial modes are the simplest
modes; the a-bit shift register is loaded with a byte of
data and eight clock.pulses are generated. The pulses
shift data out of the SO line and in from the SI line,
thereby communicating in full duplex. When a byte of
data is sent, a burst of eight clock pulses is generated
and a-bits of data are sent. The data may be sent with the
LSB or MSB first. The interfaGe can also be set to receive
data only, consequently SO will be in the high impedance
state. One of four internal clocks or an external clock
clocks the data.
4-222
The SBI mode uses a two-wire interface with devices in
a master/slave configuration. See figure 15. There is only
one master device at a time; all others are slaves. The
master sends addresses, commands, and data over the
bus. The slaves are able to detect in hardware if their
addresses were sent, a command was sent, or a portion
of data were sent. There can be up to 256 slave addresses, 256 commands, and 256 data types. All commands are user definable. Commands can be sent to
change slaves into masters; previous masters become
slaves. Firmware performs this type of operation and
thus the user decides whether the bus is simple or
complex.
NEe
pPD75328/75P328
Figure 14. Serial Interface Block Diagram
Interna I
Bus
~
I
Bit
Test
Control Serial Interface
Mode Register (CSIM)
a
a
I
L l-
II
'--
Pes /SIISB1
~
17
Selector
-4
PD2/S0/SBO
I-
->
Bit
Manipulation
a
I
a-Bit Slave Address
Register (SVA)
I
a-Bit Address
V
Comparator
=u
Bit
Tes
Serial Acknowledge Interface
Control Register (SBIC)
I
"~jj
~gnal
RElT
CMDT
SET ClR
a-Bit Shift Register (SIO)J- -->- D Serial 0
Output
latch
f-
f
-c-iJ "'~ """~
~
V
'---
Selector
l5=
'-
~
II
ACKE
Busyl
Acknowledge
Output Circuit
\.
-
'---Releasel RElD
I--- f- Bus
Commandl
CMDD
f-
Acknowledge
Detection
Circuit
T
~
V
Serial Clock
Counter
,--
lQ_,r
----
-1
--
IROCSI
Control
Circuit
IROCSI
~
POj
latch
ACKD
I'--
Serial Clock
Control
Circuit
~
"}
I
- lxx /2 3
-lxx/24
Clock
- lxx /2 6
Multiplexer
-TOUTF/F
~ =:JExternal SCK
I
49NR-558B
4-223
NEe
IIPD7S32snSP328
Figure 15. SBllIode MasterlSlare Configuration
Master CPU
I1f'D7532B
51aveCPU
I1f'D75328
(561), SBO
560,(561)
Addre.s1
-
SCi(
SCK
51aveCPU
560, (561)
Address 2
f---- 5CK
,
~
:
5lavelC
560,(561)
Address N
SCK
49NR·645A
LCD Controller/Driver
The liquid-crystal display (LCD) controller/driver can
directly drive up to a maximum of 80 segments. See
figure 16. The controller can be programmed to operate
in the static mode (drive 20 segments), multiplexed
mode (drive 40 segments), triplexed mode (drive 60
segments), or the quadriplexed mode (driva80 segments). The multiplexed mode uses 1/2 BIAS voltage;
triplexed mode uses 1/2 or 1/3 BIAS voltage; and the
quadriplexed mode uses 1/3 BIAS voltage,
The controller/driver automatically refreshes the LCD
with data from the upper 20 nibbles of RAM memory
bank one. To drive an LCD, the controller/driver uses
display data multiplexers, segment drivers S12-831. and
common drivers COMo-COM3. The LCD controller/driver
is controlled by registers LCDM, LCDC, and PGMA. The
LCD controller/driver clock (FLCD) is the main clock and
is supplied by the watch timer. The watch timer operates
while the chip is in the STOP mode, when it is driven from
the subsystem clock. Hence the LCD controller/driver
also operates in the STOP mode.
The SYNC signal and LCDCL clock are available as
outputs so that additional LCD controllers can be added.
The drive signals for the controller/driver can be set
internally by the resistor ladder mask option (ordered as
a mask option). However,; the levels can also be set by
using external resistors connected to pins VLCO-VLC2. To
control the contrast of the LCD, a BIAS pin is also
available.
Figure 16. LCD Controller/Drirer Block Diagram
Data6us
Internal
[====:::;:=============:::;:::====:;:====:::;====:::;:::=::=J
Display Data
Memory
L.T-T-.i-T--I-T-T-.........J
Display Data
Multiplexer.
Segment
Drivers
COM1
COM3
VLC1
49NR-663B
NEe
pPD75328/75P328
AID Converter
other locations in this bank contain either on-chip peripheral control registers or unused addresses. A typical
application for this buffer is data storage for the next
serial output or input. Another application is as a port
output data storage area. The bit sequential buffer can
be bit, nibble, or byte manipulated.
The 8-bit analog to digital (AID) converter is equipped
with six inputs and uses an successive approximation
routine (SAR) for the AID conversion. See figure 17. An
AID conversion occurs when one of six inputs is selected
by the ADM register. The conversion starts by setting bit
3 of the ADM register. The selected input is sampled by
using the sample and hold circuit and multiplexer. Then,
using the SAR with the comparator, resistor ladder, and
SA register, the input value is converted. The converted
value is stored in the SA register. When bit 2 of the ADM
register is set, conversion is complete and can be read
from the SA register.
Interrupts
The three external and three internal interrupts are all
vectored interrupts and are shown in figure 18. Table 7
lists a summary of the interrupts. Input INT2 detects
rising edge inputs and generates an interrupt request
flag, which is testable. Inputs KRo through KR7 detect a
falling edge and generate the same interrupt request flag
as INT2. INT2 and KRo through KR7 do not cause an
interrupt, but can be used to release the standby mode.
Interrupt requests and all interrupts except INTO release
the standby mode.
Bit Sequential Buffer
The 16-bit sequential buffer is the only general purpose
RAM in the upper half of data memory bank 15: all the
Figure IT_AID Converter Block Diagram
Internal Bus I
Jj
ADM Register [
o
• i"
IADM6iADMsiADM4i soci EOC i
o
T1
0
I
8
!
Sample Hold Circuit
1- - - - - - - - - - - - I
I
'1
r.....
1-
I
I
....
I
Multiplexer
Control Circuit
I
I
I
I
I
L _____________ I
I
I
~I
SA Register (8)
I
8
r
AVREF
Rl2
AVSS
K
Tap Decoder
r I
R
-
I
1
R
Series Resistor Ladder
R
Rl2
I
49NR-646B
4-225
II
pPD75328/75P328
NEe
Figure 18. Interrupt Controller Block Diagram
Internal
Dam Bus
~----------'-------r------'----~~--------~-.-'~r-r-.-'-.---------~~--r---~-.------~~
INTBT - - - - - H - - - , - - - - - - I
INTO/P10
INT1/P11
Priority
Control
INTCSI------------_I
Vector
Table
Address
Gen
INTTO---------------.I
INTW
-------------1
Smndby
Release
Signal
49NR·5618
4-226
NEe
pPD75328/75P328
Table 7. Interrupt Sources
Interrupt Source
Internal/External
Interrupt Priority
(Note 1)
Vectored Interrupt Request!
Table Address
INTBT
(Time reference interval signal from the basic
interval timer)
Internal
INT4
(Rising and falling edge detection)
External
INTO
(Rising/falling edge detection)
External
2
VR02/0004H
INT1
(Rising/falling edge detection)
External
3
VR03/0006H
INTCSI
(Serial data transfer end signal)
Internal
4
VR04/0008H
INTTO
(Signal generated when programmable timer/
counter count register and modulo register
coincide)
Internal
5
VR05/000AH
INT2
(Rising edge input detection to INT2 pin or
falling edge input detection to KRo-KR7)
VR01/0002H
II
Testable input signals (Tests if IR02 and IROW are set)
INTW
(Watch timer signaQ
Notes:
(1) The interrupt priority determines the order when two or more
simultaneous interrupts occur.
Standby Modes
Three standby modes, HALT, STOP, and data retention
reduce power consumption during a program standby
state. Table 8 summarizes the standby modes.
Execution of the HALT instruction selects the HALT
mode. In the HALT mode, the CPU clock q, is turned off
which stops the CPU. However, all other portions of the
chip except interrupt INTO are functional. Execution of
the STOP instruction selects the STOP mode. In the
STOP mode, the chip's main system oscillator is turned
off, stopping all portions of the chip except those operating from the subsystem clock. If the subsystem clock is
used, it remains on.
A RESET or any interrupt request except INTO releases
the HALT and STOP modes. The data retention mode can
be selected after the STOP mode has been selected. In
this mode, the supply voltage Voo can be lowered to
2 volts, further reducing the power consumption. The
contents of the RAM and registers are retained. The data
retention mode is released by first raising the supply
voltage Voo to its operating level. The chip will now be in
the STOP mode which may be released as described
above.
4-227
NEe
pPD75328/75P328
Table 8. Operation ofthe Standby Modes
Operating State
STOP Mode
Mode setting instruction
STOP instruction
HALT instruction
Clock oscillator
Only the main system clock oscillator is
stopped.
Only CPU clock q, is stopped. Main and
subsystem oscillators continue to operate.
Basic interval timer
Operation stops
Operation continues (IROBT is set at reference
time intervals).
Serial i nterf ace
Operates only when external ~ input is
selected for serial clock.
Operational.
Timer/event counter
Operates only when TIO pin input is selected for
clock count.
Operational.
Watch timer
Operates when flIT is selected for the clock
count.
Operational.
LCD controller
Operates only when flIT is selected for LCDCL.
Operational.
External interrupts
INT1, INT2, and INT4 are allowed to operate.
Only INTO cannot operate.
All operational except INTO
CPU
Operation stops.
Operation stops
Release signal
Enabled interrupt request signal (except INTO)
with Interrupt enable flag or RESET input.
Enabled interrupt request signal (except INTO)
with interrupt enable flag or RESET input.
HALT mode
RESET
Table 9 shows the status of the chip, after the RESET
signal is applied.
Table 9. Chip Status after RESET
Function
RESET during Standby Mode
Program counter (PC)
Contents of the low· order five bits of program memory address OOOOH are loaded
into program counter PC12-PC8; contents of address 0001 H are loaded into PC7 -PCO.
PSW - carry flag (Cy)
Held
Unknown
PSW - skip flag (SKO-Si<2)
o
o
PSW - interrupt status flag (IS TO)
0
PSW - bank enable flag (MBE)
RESET during Operational Mode
0
Bit 7 of program memory address OOOOH sets state of MBE.
Stack pointer (SP)
Unknown
Unknown
Data memory (RAM)
Held (note 1)
Unknown
General-purpose registers (X, A, H, L, 0, E, B, C)
Held
Unknown
Bank selection register (MBS)
0
0
Basic interval timer - counter (Bn
Unknown
Unknown
Basic interval timer - mode register (BTM)
0
0
Timer/event counter - counter (TO)
0
0
Timer/event counter - modulo register (TMODO)
FFH
FFH
Timer/event counter - mode register (TMO)
0
0
Timer/event counter - TOEO, TOUT F/F
0, 0
0, 0
Watch timer mode register (WM)
0
0
Serial Interface - shift register (SIO)
Held
Unknown
Serial interface - operation mode register (CSIM)
0
0
Serial interface - SBI control register (SBIC)
0
0
4-228
t\fEC
Table 9.
IIPD75328/75P328
Chip Status after RESET (cont)
Function
RESET during Standby Mode
RESET during O~ratlonal Mode
Serial Interface - slave address register (SVA)
Held
Unknown
Clock generator, clock output circuit -processor
clock control register (PCC)
o
o
Clock generator, clock output circuit -system
clock control register (SCC)
o
o
Clock generator, clock output circult-clock output
mode register (CLOM)
o
o
LCD controller - display mode register (LCDM)
o
o
o
o
LCD controller - display control register. (LCD C)
NO converter - mode register (ADM), EOC
04H (EOC = 1)
04H (EOC = 1)
NO converter - SA register
7FH
7FH
Interrupt function - lriterrupi request flags
ORQXXX)
Reset to 0
Reset to 0
Interrupt function - Interrupt enable flags OEXXX)
o
o
o
o
Interrupt function -INTO, INT1, and INT2 mode
registers OMO, IM1, and 1M2)
0,0,0
0,0,0
Digital ports - output buffer
Off
Off
Digital ports - output latch
Cleared to zero
Cleared to zero
Digital ports -.1/0 mode registers
(PMGA, PMGB, PMGC)
o
o
Digital ports ~ Pull-up resistor specification
register (POGA, POGB)
o
o
Pin states - POo-P03' P1o-P13' P2o-P23, P30-P33,
P60-P63, P7o-P73, PSo-P83
Input
Input
Pin states - P40-P43, P50-P53
Internal pul~up resistors (high leveO.
Open drain (hIgh Impedance).
Interrupt function - Interrupt master enable flag
OME)
Pin states - Sl::523' COMo-COM 3
Unknown
Pin states - BIAS
Internal resistor ladder Oow leveO.
External resistor ladder (high impedance).
BIt sequential buffer (BSBO-BSB3)
Held
II
Unknown
Unknown
Notes:
(1) Data In addresses OFSH-oFDH of the data memory Is undefined
when the RESET signal is Input.
4-229
NEe
IIPD75328/75P328
OTP PROM (Program Memory Write and Verify)
The ~PD75P328contain 8064 x eight-bits of one-time
programmable (OTP) program memory. The OTP is programmed by the pins listed in table 10. During OTP
programming, addresses are incremented by applying
clock pulses to the X1 input.
Program Memory WriteNerify. The· pro,gram memory
write/verify procedure follows (high speed write is enabled):
( 1) Connect unused pins to Vss through a pull-down
resistor. Hold X1 low.
( 2) Supply 5 V to VDD and Vpp.
( 3) Wait for 10 ~s.
Table 10. OTP Access
Pin
Function
Vpp
OTP programming voltage pin (normally Voo)
X1
Address increment clock input during
programming.
MDo-MDa
Mode selection during OTP programming
P4o-P4a
4-bit data 1/0 pins during OTP programming, loworder four bits
P50-P53
4-bit data I/O pins during OTP programming, highorder four bits
Voo
Supply voltage pin: 5 V ± 10% during normal
operation; 6 V during OTP programming.
( 4) Select the program memory address clear mode.
( 5) Change the voltage on VDD to 6 V and on Vpp to
12.5 V.
( 6) Select the program inhibit mode.
(7) Write data in the 1 ms write mode.
( 8) Select the program inhibit mode.
( 9) Select the verify mode. If data is written correctly,
proceed to step 10; if data is not written correctly,
repeat steps 7-9.
Notes:
(10) Perform one additional write.
(1) During OTP programming: Connect all unused pins (except XT2)
to Vss through a pull-down resistor. Do not connect the XT2 pin.
(11) Select the program inhibit mode.
(2) The IlPD75PS28 has no erasure window. The program memory
data cannot be erased with ultraviolet light.
(12) Increment the program memory address by one by
inputting four pulses to X1.
(13) Repeat steps 7-12 until the end address occurs.
OTP Operation Mode
(14) Select the program memory address clear mode.
The ~PD75P328 operates in the program memory write/
verify mode when + 6 V is applied to VDD and 12.5 V to
Vpp. Mode pins MDo-MDs select the operation modes
shown in Table 11.
Table 11. OTP Operation Mode Selection
vpp
= +12.5 V;
MDo
voo
= +6 V
MD1
MD2
MDa
H
L
H
L
Operating Mode
Program memory address clear
L
H
H
H
Program memory write
L
L
H
H
Program memory verify
H
X
H
H
Program inhibit
Notes:
(1) X
=
4-230
Lor H.
(15) Change the voltage on VDD and Vpp to 5 V.
(16) Turn off power.
The timing for steps 2-12 is shown in figure 19.
NEe
Figure 19.
IIPD75328/75P328
Timing Diagram for Program Memory Writel'lerify
""'~C------X Repetitions-----+l~1
j.---write--ooj~\"'--Verify-->t..--.-Additional Write-.....-t-j•.-----Address Increment---~.I
Vpp
VDD
c-------------------Vpp - - - r - - - - - - - - - - - - - - - : i / ; f VDD---'
r-----------------;£r-c- - - - - - - - - - - - - - - - - - - -
VDD+1 - - VDD---'
X1
p;~~~;i~ ------«
Input Data
>-<
Output Data
~~
Input Data
)>-------------
II
MDO
(P30)
rc
MD3~
(P33)
49NR-G64B
Program Memory Read. The program memory read
procedure follows:
( 7) Select the verify mode. When four clock pulses are
input to X1, one address of data is output.
( 1) Connect unused pins to Vss through a pull-down
resistor. Hold X1 low.
( 8) Select the program inhibit mode.
( 2) Supply 5 V to Voo and Vpp.
( 3) Wait for 10 p.s.
( 4) Select the program memory address clear mode.
( 9) Select the program memory address clear mode.
(10) Change the voltage on Voo and Vpp to 5 V.
(11) Turn off power.
The timing for steps 2-9 is shown in figure 20.
( 5) Change the voltage on Voo to 6 V and on Vpp to
12.5 V.
( 6) Select the program inhibit mode.
4-231
t-{EC
pPD75328/75P328
Figure 20.
Vpp
Timing Diagram for Program Memory Read
Vpp--,T--------------------------------------------------------~Jf
VDD
---I
~D+t--T--------------------------------------------------------~£~C--------
VDD VDD-./
rlL
Xt
~~~~----------~(~______O_u_tP_ut_D_a~______~)(~______O_u_tP_ut_Da_ta______~)(
MOO)
(P3o)
:
)-
\~--------------~f~
MDt
(
P3
t)
-------------------------------------------------------------,JJ.,F_'-------
MD2/r---------------------------------------------------------~£F-C-------(P32)
~L
>
49NR-665B
INSTRUCTIONS
Instruction Set
The I4PD75328 provides a powerful set of 103 instructions.
The instruction set contains the following features:
Instruction Timing
The minimum instruction execution time is 0.95 I4S with
a crystal frequency of 4.19 MHz. The processor clock
control (PCG) register is used to program the CPU
instruction execution time to 0.95 p.s, 1.91I4S, or 15.314S
(assuming a 4.19 MHz crystal). Power consumption can
be reduced by lowering the CPU speed.
4-232
•
•
•
•
•
•
•
Versatile bit manipulation instructions
Four-bit manipulation instructions
Eight-bit data transfer instructions
GETI instruction to reduce program size
Vertically stored and base correction instructions
Table reference instructions
One-byte relative branch instructions
NEe
pPD75328/75P328
Organization. Tables 12-15 define the operands, symbols, and addressing symbols found in table 16. Table 16
lists the instruction set encodings by instruction groups.
Clock Cycles. One machine cycle equals one CPU clock
cycle f/l. The PCC selects one of four available CPU cycle
speeds.
Skip Cycles. S equals the number of extra machine
cycles required for skip operation when executing a skip
instruction:
• S = 0, No skip
• S = 1, one- or two-byte instruction or G ETI instruction is skipped
• S = 2, three-byte instruction is skipped
(SR !addr, CALL !addr instruction)
Table 12. Operand Formats and Values
Format
Values
reg
X,A,B,C,D,E,H,L
regl
X,B,C,D,E,H,L
rp
XA,BC,DE,HL
rpl
BC, DE, HL
rp2
BC,DE
rpa
HL, DE, DL
rpal
DE, DL
n4
4-bit immediate data or label
nS
S-bit immediate data or label
mem (Note I)
S-bit immediate data or label
Table 13. Instruction Set Symbol Identifiers
Symbol
Description
A
A register (4-bit accumulator)
B
B register (4-bit accumulator)
C
C register (4-bit accumulator)
D
D register (4-bit accumulator)
E
E register (4-bit accumulator)
H
H register (4-bit accumulator)
L
L register (4-bit accumulator)
x
X register (4-bit accumulator)
XA
XA register pair (S-bit accumulator)
BC
BC register pair
DE
DE register pair
HL
HL register pair
DL
D L register pair
PC
Program counter
SP
Stack pointer
Cy
Carry flag (bit accumulator)
PSW
Program status word
MBE
Memory bank enable flag
PORTn
Port O-S
IME
Interrupt master enable flag
IExxx
Interrupt' enable flag
MBS
Memory bank selection register
PCC
II
Processor clock control register
Separation between address and bit
bit
2-bit immediate data or label
frnem
FBOH-FBFH, FFOH-FFFH immediate data or label
pmem
FCOH-FFFH immediate data or label
addr
0000H-177FH immediate data or label
caddr
12-bit immediate data or label
faddr
II-bit immediate data or label
taddr
20H-7EH immediate data (bit 0
PORTn
PORT O-S
IExxx
IEBT, IECSI, IETO, lEO, lEI, IE2, IE4, lEW
MBn
MBO, MBI, MBI5
(xx)
Contents addressed by xx
xxH
Hexadecimal data
= 0) or label
Notes:
(I) Only the even memory address is used in S-bit data processing.
4-233
NEe
pPD75328/75P328
Table 14. Instruction Code Symbols
Table 15. Addressing Symbols
reg,reg1
Symbol
Description
R2
R1
Ro
Register
*1
MB=MBE/\ MBS (MBS=O, 1, 15)
0
0
0
A
reg
*2
MB=O
0
0
X
reg,reg1
*3
L
reg,reg1
H
reg,reg1
MBE=O: MB=O (00H-7FH)
MB=15 (80H-FFH)
MBE=l: MB=MBS (MBS=O, 1, 15)
E
reg,reg1
*4
MB = 15, fmem = FBOH-FBFH,
FFOH-FFFH
D
reg,reg1
*5
MB=15, pmem=FCOH-FFFH
C
reg,reg1
*6
addr=000H-1F7FH
B
reg,reg1
*7
addr= (Current PC) -15 to (Current PC) -1
(Current PC) +2 to (Current PC) + 16
*8
caddr=OOOOH-OFFFH (PC12=0) or
1000H-1F7FH (PC12= 1)
@rpa
*9
faddr=0000H-07FFH
@DE
@rpa,@rpa1
*10
taddr= 0020H-007FH
@DL
@rpa,@rpa1
Notes:
0
0
0
0
0
0
0
@rpa,@rpa1
Q2
Q1
Qo
Addressing
0
0
1
@HL
0
0
0
Address
Area
Data
memory
Program
memory
(1) MB = Memory bank that can be addressed.
Register Pairs
(2) For symbol *2 (MB = 0, regardless of the status of MBE and
MBS).
P2
P1
reg-pair
0
0
XA
rp
HL
rp,rp1
DE
rp,rp1,rp2
BC
rp,rp1,rp2
0
0
IE-xxx
Ns
N2
N1
No
IExxx
0
0
0
0
IEBT
0
0
0
lEW
0
IETO
0
0
0
0
0
IECSI
0
0
0
4-234
lEO
IE2
0
0
IE4
0
IE1
(3) For symbol *4 and *5 (MB = 15, regardless of the status of MBE
and MBS).
(4) For symbol *6 through *10 indicates each addressable area.
(5) The addressing symbols are used in the "Addressing Area"
column of the instruction set encodings. See table 16.
WEe
Table 16.
Mnemonic
pPD75328/75P328
Instruction Set Encodings
Operand
Operation
Bytes
Machine
Cycles
2
2
Addressing
Area
Skip Conditions
Data Transfers
MOV
String A
A, #n4
A-n4
regl, #n4
regl - n4
XA, #n8
XA-n8
2
2
String A
HL, #n8
HL- n8
2
2
String B
rp2, #n8
rp2 - n8
2
2
A,@HL
A- (HL)
*1
A, @rpal
A - (rpal)
*2
XA,@HL
XA- (HL)
@HL,A
(HL) -A
@HL,XA
2
2
(HL) -XA
2
2
*1
A,mem
A- (mem)
2
2
*3
XA,mem
XA- (mem)
2
2
*3
mem,A
(mem) -A
2
2
*3
mem,XA
*3
*1
*1
(mem) -XA
2
2
A, regl
A - regl
2
2
XA, rp
XA-rp
2
2
regl, A
regl - A
2
2
2
2
rpl, XA
rpl -XA
A,@HL
A"" (HL)
A, @rpal
A"" (rpal)
XA,@HL
XA"" (HL)
2
2
*1
A,mem
A <-+ (mem)
2
2
*3
XA,mem
XA .... (mem)
2
2
*3
A, regl
A"" (regl)
XA, rp
XA .... rp
XA,@PCDE
XA -(PC12-8+DE)ROM
3
XA,@PCXA
XA - (PC12-8+XA)ROM
3
A, #n4
A-A+n4
I+S
A,@HL
A-A+(HL)
1+S
ADDC
A,@HL
A, CY -A+ (HL) +CY
SUBS
A,@HL
A-A-(HL)
SUBC
A,@HL
A, CY - A+(HL)-CY
AND
A, #n4
A - AA n4
A,@HL
A-AA(HL)
A, #n4
A-AVn4
XCH
MOVT
II
*1
*2
2
2
Arithmetic
ADDS
OR
XOR
A,@HL
A-A V (HL)
A, #n4
A - A-V-n4
A,@HL
A - A-V-(HL)
Carry
*1
Carry
*1
I+S
*1
Borrow
*1
2
2
2
2
2
2
*1
*1
*1
4-235
NEe
pPD7532sn5P32S
Table lB. Instruction Set Encodings (cont)
Mnemonic
Operand
Operation
Bytes
Machine
Cycles
2
2
Addressing
Area
Skip Conditions
Accumulator
RORC
A
CV -
NOT
A
A-A
Ao. Aa -
CY, An-l - An
Increme(lt/DBCfBmBnt
INCS
DECS
reg
reg - reg+1
@HL
(HL) - (HL)+l
2
2+S
*1
(HL) = 0
mem
(mem) - (mem) +1
2
2+S
*3
(mem) = 0
reg
reg - reg-1
reg. #n4
Skip if reg = n4
2
2+S
@HL.#n4
Skip if (HLJ = n4
2
2+S
*1
(HL) = n4
A.@HL
Skip If A = (HLJ
1+S
*1
A = (HLJ
A. reg
Skip if A = reg
CV-1
1+S
.reg = 0
1+S
reg = FH
Comparison
SKE
2
reg = n4
2+S
A = reg
1+S
CY = 1
Flags
SET1
CV
CLR1
CV
CV-O
SKT
CV
Skip ifCV = 1
NOT1
CV
CV-C'Y
Memory Bits
SET1
CLR1
SKT
SKF
SKTCLR
4-236
mem.bit
(mem.bit) -1
2
2
*3
fmem.bit
(fmem.bit) - 1
2
2
*4
pmem.@L
(pmem7_2+ - La-2.bit (Ll-oI) - 1
2
2
*5
@H+mem.blt
(H+mem~.bit)
2
2
*1
-1
mem.blt
(mem.bit) -0
2
2
*3
fmem.bit
(fmem.blt) - 0
2
2
*4
pmem.@L
(pmem7_2+La-2·bit (Ll-ol) - 0
2
2
*5
@H+mem.bit
(H+mema-o.bit) - 0
2
2
*1
mem;bit
Skip if (mem.blt) = 1
2
2+S
*3
(mem.blt) =1
fmem.bit
Skip if (fmem.bit) = 1
2
2+S
*4
(fmem.bit) = 1
pmem.@L
Skip if (pmem7_2 + La-2.bit (Ll -ol) = 1
2
2+S
*5
(pmem.@LJ = 1
@H+mem.blt
Skip if (H+mem3'1l.bit) = 1
2
2+S
*1
(@H+mem.blt) =1
mem.blt
Skip if (mem.bit) = 0
2
2+S
*3
(mem.bit) =0
fmem.bit
Skip if (fmem.bit) = 0
2
2+S
*4
(fmam.blt) =0
pmem.@L
Skip if (pmem7-2 + La-2.blt (Ll-ol) = 0
2
2+S
*5
(pmem.@L) =0
@H+mem.blt
Skip if (H+mema-o.bit) = 0
2
2+S
*1
(@H+mem.blt) =0
fmam.blt
Skip If (fmem.bit) = 1 and clear
2
2+S
*4
(fmem.blt) = 1
pmem.@L
Skip If (pmem7_2+ La-2.bit (Ll -ol) = 1
and clear
2
2+S
*5
(pmem.@LJ =1
@H+mem.blt
Skip if (H+mem~.blt) = 1 and clear
2
2+S
*1
(@H+mem.blt) =1
NEe
Table 16.
Mnemonic
pPD75328/75P328
Instruction Set Encodings (cont)
Operand
Operation
Bytes
Machine
Cycles
Addressing
Area
Skip Conditions
Memory Bits (cont)
ANDl
ORl
XORl
BR
CY, fmem.bit
CY +- CY 1\ (fmem.bit)
2
2
*4
CY,
pmem.@L
CY +- CY 1\ (pmem7_2+ L:!_2.bit (Ll-0))
2
2
*5
CY,
@H+mem.bit
CY +- CY 1\ (H+mem3_0.bit)
2
2
*1
CY, fmem.bit
CY - CY V (fmem.bit)
2
2
*4
CY,
pmem.@L
CY -CY V (pmem7_2+ L:!_2.bit (Ll-0))
2
2
*5
CY,
@H+mem.bit
CY - CY V (H + mema-o.bit)
2
2
*1
CY, fmem.bit
CY - CY¥(fmem.bit)
2
2
*4
CY,
pmem.@L
CY -CY¥(pmem7_2+L3_2·bit (Ll-0))
2
2
*5
CY,
@H+mem.bit
CY - CY¥(H+mem3_0.bit)
2
2
*1
addr
PC 12-O - addr (appropriate instructions
are selected from BR laddr, BRCB Icaddr,
and BR $addr by the assembler)
laddr
PC12-0 - addr
$addr
PC 12-0 -addr
Icaddr
PCll-O -caddrll-O
CALL
laddr
CALLF
Ifaddr
BRCB
II
*6
3
3
*6
2
*7
2
2
*8
(SP-l) - (PC7-4) , (SP-2) +-- PC3-0
(SP-3) +-- (MBE, 0, 0, PC l 2l,
(SP-4) +-- PCll-8, PC12-0 +-- addr,
SP - SP-4
3
3
*6
(SP-l) - PC7-4, (SP-2) +-- PC3-O
(SP-3) +-- (MBE, 0,0, PCl2l,
(SP-4) +-- PCll-8, SP +-- (SP-4),
PC +-(00, Al0-o)
2
2
*9
Subroutine
RET
PC11-8 - (SP). (MBE, PC1:!! - (SP+l),
PCa-o +- (SP+2), PC7-4 +-- (SP+3),
SP- (SP+4)
3
RETS
PCll-8 - (SP), (MBE, PC1:!!- (SP+l),
PC3-0 (SP+2), PC7-4 +-- (SP+3)
SP +-- SP+4, then Skip unconditionally
3+S
RETI
PCll-8 +-- (SP) , PC12 - (SP+l)
PCa-o - (SP+2), PC7-4 (SP+3)
PSWL - (SP+4), PSWH +-- (SP+6)
PUSH
POP
rp
(SP-l) (SP-2)
BS
(SP-l) - MBS, (SP-2)
rp
rp
BS
MBS
+--
+--
rp, SP
(SP+l) (SP) , SP
+--
+--
+-+--
Unconditional
3
SP-2
0, SP
+--
SP-2
2
2
2
2
SP+2
(SP+l), SP - SP+2
4-237
NEe
pPD15328n5P328
Table 16. Instruction Set Encodings (cont)
Mnemonic
Operand
Bytes
Machine
Cycles
IME-l
2
2
IExxx- 1
2
2
IME-O
2
2
IExxx - 0
2
2
Operation
Addressing
Area
Skip Conditions
Interrupt
EI
IExxx
01
IExxx
Input/Output
IN (Note 1)
OUT
(Note 1)
A, PORTn
A-
2
2
XA, PORTn
XA - PORT n +l, PORTn (n = 4,6)
2
2
PORTn, A
PORTn - A (n = 2-S)
2
2
PORTn, XA
PORT n + l , PORTn - XA (n = 4,6)
2
2
PORTn (n = O-S)
CPU Control
HALT
Set HALT Mode (PCC.2 -
1)
2
2
STOP
Set STOP Mode (PCC.3 -
1)
2
2
NOP
No Operation
Miscellaneous
SEL
MBn
MBS - n (n = 0, 1, 15)
2
GETI
taddr
When (taddrh_6 = 00;
PC12-o - (taddr)4_0 + (taddr+ 1)
3
When (taddrh_6 = 01;
(SP-4) (SP-l) (SP-2) - PC11-o
(SP-3) - (MBE, 0, 0, PC1:!!
PC12 -0 - (taddr)4-o + (taddr+l)
SP = SP-4
When (taddrh_6 = 10;
(taddr)(taddr+l)
instruction is executed
Notes:
(1) When executing an IN or OUT instruction, MBE = 0 or MBE = 1
and MBS = 15.
4-238
*10
Depends on the
referenced
instruction
t-IEC
IlPD7800 Series:
8-Bit Microcomputers
1
5-1
II
8-Bit, General·Purpose Microcomputers
Section 5
p.PD7800 Series:
8~B!t, Genera!~Purpose
P.4!crocomputers
"PD78C1X/78C1 xA/CG14/CP14
a-Bit CMOS Microcomputers
With AID Converter
5-2
5-3
NEe
NEe
IIPD78C1x/C1xA/CG14/CP14
8·Bit CMOS Microcomputers
With AID Converter
NEG Electronics Inc.
Description
The family of single-chip microcomputers covered by
this data sheet includes the following types:
pPD78C10
pPD78C11
pPD78C14
pPD78C10A
pPD78C11A
pPD78C12A
pPD78C14A
pPD78CG14
pPD78CP14
These microcomputers integrate sophisticated on-chip
peripheral functions normally provided by external
components. Their internal 16-bit ALU and data paths,
combined with a powerful instruction set and addressing, make the devices appropriate in data processing as
well as control applications.
The devices integrate a 16-bit ALU, 4K-, 8K-, or 16K-byte
ROM, 256-byte RAM, an eight channel A/D converter, a
multifunction 16-bit timer/event counter, two S-bit timers, a USART, and two zero-cross detect inputs on a
single die, allowing their use in fast, high-end processing applications. This involves analog signal interface
and processing.
ThepPD7SC1x/C1xA/Cx14 family includes: 4K-, 8K-, and
16K-byte mask ROM devices, embedded with a custom
customer program; ROM less devices for use with up to
64K-bytes of external memory; 16K-byte piggyback
EPROM device for prototyping; 16K-byte EPROM or OTP
ROM devices for prototyping and low-volume production. The pPD7SC11A/C12A/C14A also have mask optional pullup resistors available on ports A, B, and C.
Features
o CMOS technology
- 25 mA operating current
(7SC10/C10A/C11/C11A/C12A)
- 30 mA operating current (7SC14/C14A)
o Complete single-chip microcomputer
-16-bit ALU
-4K, 8K, or 16K x S ROM
- 256-byte RAM
o 441/0 lines
o Mask optional pull up resistors
- Ports A, B, and C
-pPD7SC11A/C12A/C14A only
o Expansion capabilities
- SOS5A-like bus
- 60K-byte external memory address range
o Eight-channel, 8-bit A/D converter
- Autoscan mode
- Channel select mode
o Full-duplex USART
- Synchronous and asynchronous
o 159 instructions
-16-bit arithmetic, multiply, and divide
- HALT and STOP instructions
o O.S-ps instruction cycle time (15-MHz operation)
o Prioritized interrupt structure
- Three external
- Eight internal
II
o Standby function
o On-chip clock generator
Ordering Information
Part Number
Package
ROM
JIPD78C10CW
64-pln plastic SDIP
ROMless
JIPD78C10G-36
64-pln plastic QUIP
JIPD78C10G-1 B
64-pin plastic QFP
(Resin thickness
2.05 mm)
JIPD78C10GF-3BE
64-pin plastic QFP
(Resin thickness
2.7mm)
JIPD78C10L
68-pin PLCC
JIPD78C10ACW
64-pin plastic SDIP
JIPD78C10AGF-3BE
64-pin plastic QFP
JIPD78C10AGQ-36
64-pin plastic QUIP
JIPD78C10AL
68-pin PLCC
JIPD78C11 CW-xxx
64-pin plastic SDIP
JIPD78C11 G-xxx-36
64-pin plastic QUIP
JIPD78C11 G-xxx-1 B
64-pin plastic QFP
(Resin thickness
2.05 mm)
JIPD78C11 GF-xxx-3BE
64-pln plastic QFP
(Resin thickness
2.7mm)
JIPD78C11 L-xxx
68-pin PLCC
ROMless
4Kmask ROM
o Two zero-cross detect inputs
o Two 8-bit timers
50248
5-3
NEe
pPD78C1x/C1xA/CG14/CP14
Pin Configurations
Ordering Information (cont)
Part Number
Package
ROM
IIPD78C11 ACW-xxx
64-pin plastic SDIP
4Kmask ROM
IIPD78C11 AGF-xxx-SBE
64-pin plastic QFP
IIPD78C11 AGQ-xxx-S6
64-f)ln plastic QUIP
IIPD78C11 AL-xxx
68-pin PLCC
IIPD78C12ACW-xxx
64-pin plastic SDIP
IIPD78C12AGF-xxx-SBE
64-pin plastic QFP
8K mask ROM
IIPD78C12AG-xxx-S6
64-pin plastic QUIP
IIPD78C12AL-xxx
68-pin PLCC
IIPD78C14CW-xxx
64-pin plastic SDIP
IIPD78C14G-xxx-36
64-pin plastic QUIP
IIPD78C14G-xxx-1 B
64-pin plastic QFP
(Resin thickness
2.05 mm)
IIPD78C14GF-xxx-SBE
64-pin plastic QFP
(Resin thickness
2.7mm)
IIPD78C14L-xxx
68-pln PLCC
IIPD78C14AG-xxx-AB8
64-pin plastic QFP
(Interpin pitch
0.8mm)
16K mask
ROM
JlPD78CG14E
64-pin ceramic
piggyback QUIP
4/8/16K
piggyback
EPROM
IIPD78CP14CW
64-pln plastic SDIP
16KOTP ROM
IIPD78CP14G-S6
64-pin plastic QUIP
IIPD78CP14GF-SBE
64-pin plastic QFP
IIPD78CP14L
68-pin PLCC
IIPD78CP14DW
64-pin ceramic SDIP
with window
IIPD78CP14R
64-pln ceramic QUIP
with window
16K mask
ROM
16KLN
EPROM
64-Pin QUIP or SDIP (plastic or Ceramic)
PAo
PA1
PA2
PAs
PA4
PAS
PAs
PA7
P80
P81
PB2
PBs
PB4
PBs
PBS
PB7
PCOfTxD
PC1/RxD
PC2/SCK
PCsfTviNr2
PC4fTO
PCS/CI
pcs/GOo
PC7/C01
NMI
INT1
MODE1
RESET
MODEO
X2
X1
Vss
VDD
STOP
PD7
POe
PDs
PD4
PDa
PD2
PD1
PDQ
PF7
PFs
PFS
PF4
PFs
PF2
PF1
PFo
ALE
WR
AD
AVDD
AVAREF
AN7
ANs
ANS
AN4
ANs
AN2
AN1
ANo
AVSS
83ML-6178A
Notes:
(1) xxx indicates ROM code suffix.
5-4
t-lEC
IIPD78C1 X/C 1xA/CG 14/CP14
64-Pin Plastic QFP
;a/il ~ ~ ~ ~ ~
P03
P04
PDs
P06
P07
STOP
~!3~:o:~!Il!l!~1nl;l;gj
52
53
54
55
56
S7
32
AN4
31
AN3
30
AN2
29
ANl
26
27
ANO
Vss
Xl
AVss
VDD
PAO
56
59
26
PAl
60
24
X2
PA2
61
23
MOOEO
PA3
62
22
REsET
PA4
63
S4
21
MODEl
PAS
25
0
.....
20
(\1('1)
...
.,,«),...
·INTl
0
..... N CI) . . an
co m .............................
~ ~ ~ ~
lilff'itlf~I~~§lli~
~!CcS't:::1I.
lI.e
II.
lJ
11.11.
83ML·818OB
.5-5
II
JiPD78C1X/C1xA/CG14/CP14
fJ4-Pln Ceramic PIgg_c~ QUIP
I',',
I
PAo
PAl
PA2
PAS
PA4
PAS
PA6
PA7
PBo
PBl
PB2
.. ,
VOO
STOP
r"
s2
voo91 .....2119 "00 61
60
1
1
A1292
1
279Vss 59
1
56
A79 s
1
269A1S S7
1
56
A69.i
1
259 A6
1
PBs
PB4
PBS
PBs
PB7
PCofTxO
As9 S
1
249Ag
1
As9 7
1
229Vss 49
1
46
I'C1/RxD
A29 8
1
21 9Al0 47
1
46
A19 9
1
209CE45
1
44
A09 10
1
19 9 17
1
109 11
1
18 9 16
1
119 12
1
17
129 1S
1
16 9 14
1
6
A4g
1
pc:!!SCK
PC3IINT2
PC4fTO
PCsJCl
I'CflICOo
PC7/COI
NMI
INTI
MODEl
RESET
MODEO
X2
Xl
Vss
29
e
52
239All Sl
1
50
91 15
30 vss9 14 1591S
'- _ _ _ ..I
Sl
P07
P06
POs
P04
POs
\,
PD2
POI
PDo
PF7
PF6
PFs
PF4
PFs
PF2
PFI
PFo
ALE
WR
RD
AVOO
VAREF
AN7
AN6
ANS
AN4
ANS
AN2
ANI
ANo
AVss
8SRD-6142A
5-6
~EC
pPD78C1x/C1xA/CG14/CP14
68-PinPLCC
N
.....
'lit
('I)
0
0
N
.....
I~
..
O<~«« en D.. a.. a.. Il. D.. a.. _
'lit
fD
C')
~
CD
PA7
10
PBO
11
PB1
CO ..... CO
Il)
fD
Il)
'lit
CI')
C\I
~fD~~~fa~
u;
60
0
P01
59
PDQ
12
58
PF7
PB2
13
57
PF6
PB3
14
56
PF5
PB4
15
55
PF4
PB5
16
54
PF3
PB6
17
53
PF2
PB7
18
52
PF1
PCo/TxO
19
51
PFO
PC1/RxO
20
50
ALE
WR
PC2iSCK
21
49
PCafTIIINT2
22
48
RO
IC
23
47
PC,VrO
24
46
AVOO
IC
PCstCI
25
26
45
PCs/COo
44
~
re
~
g
~ ~ ~ ~ ~ ~ ~ ~ ~ ~
- -It;;
WXX
0
'" Sl~ !zw
-§~§
~
gj
;
II
VAREF
AN7
~ ~
In!i!
In
Z
- Z
'" Z
'" Z
... Z
'"
!@
>;::«««<
83Ml..s1799
5-7
fttfEC
pPD78C1X/C1xA/CG14/CP14
Symbol
Pin Identification
Function
Pin Identification
"PD78CG14E Upper EPROM Pins
ALE
Address latch enable output
Symbol
Pin
ANO-AN7
AID converter analog inputs 0-7
Ao-A13
2-10,21
23-26
INT1
Interrupt request 1 input
MODEO
Mode 0 Input; 1/0 memory output
MODE1
Mode 1 input
NMI
Nonmaskable interrupt input
PAo-PA7
Port A 110
PBo-PB7
Port B 110
PCoITxD
Port C 110 line 0; transmit data output
20
Chip enable signal for 27C256/27C256A; highlevel output (during STOP or HALl), otherwise,
low-level output
10-17
11-13
15-19
8-bit input of data read from 27C256/27C256A
Same potential as lower Voo pin; Vee power
supply line (Vpp) for 27C256/27C256A
Voo
Voo
28
Same potential as lower Voo pin; Vee power
supply line {Vecl for 27C256/27C256A
Port C 110 line 2; serial clock 110
Vss
14
Same potential as lower Vss pin connected to
the 27C256/27C256A GND pin
Port C 110 line 3; timer input; interrupt request 2
input
Vss
22
Same potential as lower Vss pin; ()E signal
(always lOw) input to 27C256/27C256A
Vss
27
Same potential as lower Vss pin; A14 signal
(always low) input to 27C256/27C256A
PC4fTO
Port C 110 line 4; timer output
PCs/CI
Port C 110 line 5; counter input
Port ClIO lines 6, 7; counter outputs 0, 1
PDo-PD7
Port D 110; expansion memory address, data
bus (bits ADo-AD7)
PFo-PF7
Port F 110; expansion memory address,
(bits ABa-AB1sl
Read strobe output
Reset input
Stop mode control input
AID converter reference voltage
WR
Write strobe output
X1, X2
Crystal connections 1, 2
AVoo
AVss
AID converter power supply voltage
AID converter power supply ground
Voo
5 V power supply
Vss
Ground
IC
Internal connection
5-8
14-bit program counter (PCO-PC1:V output used
as 27C256/27C256A address signals
~
Port C 110 line 1; receive data input
PCalTIIINT2
Function
NEe
IIPD78C1x/C1xA/CG14/CP14
PIN FUNCTIONS
PAo·PA7 (Port A)
~LE
Port A is an 8-bit three-state port. Each bit is independently programmable as either input or output. Reset
makes all lines of port A inputs.' Mask ·O'ptional pullup
resistors are available on the "PD78C11A/C12A/C14A.
(Address Latch Enable)
The ALE output is used to latch the address of PDQ-PD7
into an external latch.
ANO·AN7 (Analog Inputs)
These are the eight analog inputs to the A/D converter.
AN4-AN7 can also be used as a digital input for falling
edge detection.
PBO·PB7' (Port' B)
CI (Counter Input)
Port B Is an 8-biUhree-state port; Each bit ialndependently programmable as either input or output. Reset
makes all lines of port B Inputs. Mask optional puUup
resistors are available' on the "PD18C11A/C12A/C14A.
External pulse input to timer/event counter.
PCO·PC7 (Port C)
COo, C01 (Counter Outputs)
Port C is an 8-bit three-state port. Each bit is independently programmable as either input or output. Alternatively, the lines of port C can be used as control lines for
the USART, interrupts, and timer. Reset makes all lines ?f
port C inputs. Mask optional puUup resistors are ayallable on the "PD78C11A/C12A/C14A.
Programmable waveform outputs based on timer/event
counter.
INT1 (Interrupt Request 1)
INT1 is a rising edge triggered, maskable interrupt input.
It is also an ac-input, zero-cross detection terminal.
PDo·PD7 (Port D)
If the optional pullup resistor is specified for this pin on
the "PD78C11A/C12A/C14A, the zero-cross detection
circuitry will not function.
Port 0 is an 8-bit three-state port. It can be programmed
as either 8 bits of input or 8 bits of outP\Jt. When external
expansion memory is used, port 0 acts as the multiplexed address/data bus.
INT2 (Interrupt Request 2)
INT2 is a falling edge triggered, maskable interrupt
input. It is also an ac-input, zero-cross detection terminal.
MODEO, MODE1 (Mode 0, 1)
The MODEO and MODE1 inputs select the amount of
external memory. MODEO outputs the 10 signal, and
MODE1 outputs the M1 signal. An external pull up resistor to Voo is required if the input is to be a logic high.
The value of this pull up resistor, R, is dependent on tcyc
and is calculated as follows: R in KO is 4 s R s 0.4 tcyc
where tCYC is in ns units.
NMI (Nonmaskable Interrupt)
PFo·PF7 (Port F)
Port F is an 8-bit three-state port. Each bit is independently programmable as either input or output. When
external expansion memory is used, port F outputs the
high-order address bits.
RD (Read Strobe)
The three-state RD output goes low to gate data from
external devices onto the data bus. RD goes high during
reset.
RESET (Reset)
When the Schmitt-triggered RESET input is brought low,
it initializes the device.
Falling edge, Schmitt triggered nonmaskable interrupt
input.
5-9
t\fEC
pPD78C1x/C1xA/CG14/CP14
RxD (Receive Data)
WR (Write Strobe)
Serial data input terminal.
The three~state \A/R output goes lov; to indicate that the
SCK (Serial Clock)
data bus holds valid data. It is a strobe signal for
external memory or I/O write operations. WR goes high
during reset.
Output for the serial clock when internal clock is used.
Input for serial clock when external clock is used.
STOP (STOP Mode Control Input)
A low-level input on STOP (Schmitt-triggered input)
stops the system clock oscillator.
X1, X2 (Crystal Connections)
X1 and X2 are the system clock crystal oscillator terminals. X1 is the input for an external clock.
AVOD (AID Converter Power)
TI (Timer Input)
This is the power supply voltage for the A/D converter.
Timer input terminal.
AVss (AID Converter Power Ground)
TO (Timer Output)
AVss is the ground potentialfor the A/D converter power
supply.
The output of· TO is a square wave with a frequency
determined by the timer/counter.
VOO (Power Supply)
TxD (Transmit Data)
Voo is the +5-volt power supply.
Serial data output terminal.
Vss (Ground)
VARE F
(AID Converter Reference)
vAREF sets the upper limit for the A/D conversion range.
5-10
Ground potential.
NEe
pPD78C1X/C1xA/CG14/CP14
Block Diagram
X1
Clock
X2
Generator
8
12
PC 1ITxD - - - - I
PC1IRxO---+\
PC2ISCK_--+\
1--:~~+-_C=-:--I}Ea~
H
NMi---+\
INT1---+\
L
1-=-+-::-'; =:
EA'
AN4-AN7
}
Program
Memory
Data
Memory
[256-byte]
.~.
~
TVINT2
~
II
..
PCSICIPC61C00+
PC7IC01+
t:
~
8
.
PB7-PBo
Insl
AN7-ANQ
Decoder
VAREF---+\
~~---.
A V s s - L . . -_ _-'
16
ReadlWrite
Note:
1. On-Chip ROM
78C10IC10A
78C11IC11A
78C12A
78C141C14A
78CP14
Control I
System
Control
I I I i t
:0
: 4096 Bytes
AD
WR
: 8192 Bytes
: 16384 Bytes
: 16384 Bytes EPROM/OTP ROM
ALE
MOOE1 MOOEO
pd~Cor I
RESET
t t
VOo
\ICc
(STOP)
(VOO)
Vss
83A~B
FUNCTIONAL DESCRIPTION
Memory Map
The p.PD7BC1x/C1xA/Cx14 family can directly address
up to 64K bytes of memory. Except for the on-chip ROM
(or PROM) and RAM (FFOOH-FFFFH), any memory location can be used as ROM or RAM. The memory map,
figure 1, defines the 0 to 64K-byte memory space for the
p.PD7BC1X/C1xA/Cx14 family.
The p.PD7BCG14 and the "PD7BCP14 can be programmed in software to have 4K, BK, or 16K bytes of
internal· program memory. This programming is transparent to the ROM-based device,allowing easy transfer
of code to a ROM-based device.
Input/Output
The p.PD7BC1 x/C1 xA/Cx14 family has 44 digital 1/0 lines,
five B-bit ports (ports A, B, C, D, F), and four digital input
lines (AN4-AN7).
5-11
ftfEC
pPD78C1 X/C 1xA/CG 14/CP14
Analog Input Lines. ANO-AN7 are configured as analog
input lines for the on-chip A/D converter. Lines AN4-AN7
can be used as digital input lines for falling edge detec..
tion.
Port A, Port S, Port C, Port F. Each line of these ports
can be individually programmed as an input or output.
When used as I/O ports, all have latched outputs and
high-impedance inputs. On the ~PD78C11 A/C12A/C14A,
mask optional pullup resistors are available for ports A,
B, and C.
Port D. Port D can be programmed as a byte input or a
byte output.
Control Lines. Under software control, each line of port
C can be configured individually as a control line for the
serial interface, timer, and timer/counter or as an VO
port.
Memory ~xpansion. In addition to the single"chip operation mode, the ~PD78C1x/C1xA/Cx14 family has four
memory expansion modes. Under soft"l'are control, port
D can provide a multiplexed low-order address and data
bus; port F can provide a high-order address bus. Table
1 shows the relation between memory expansion modes
and the pin configurations of port 0 ij.nd port F.
Table 1. Memory E1!Pllllllion Modes and Port
ConfiguratIons
.
Port Configuration
Memory Expan$lon
Port
None
PortO
. I!O port
Port F
110 port
256 bytes
Port 0
Multiplexed address!
data bus
Port F
I!O port
4K bytes
PortO
Multiplexed address!
data bus
Port F (PFo·PFa)
Address bus
Port F (PF4-PF7)
I/O port
Port 0
Multiplexed address/
data bus
16K bytes
60K bytes
5-12
Port F (PFo-PFsl
Address bus
Port F (PFs-PF7)
I/O port
Port 0
Multiplexed address/
data bus
Port F
Address bus
Timers
The two S-bit timers may be programmed independently
or cascaded as a 16-bit timer. The timer can be software
set to increment at intervals of four machine cycles
(0.8 ~s at 15-MHz operation) or 128 machine cycles
(25.6 ~s at 15-MHz), or to increment on receipt of a pulse
at TI. Figure 2 is the block diagram for the timer.
Timer/Event Counter
The 16-bit multifunctional timer/event counter (figure 3)
can.be used for the following operations:
•
•
•
'.
•
Interval timer
External event counter
Frequency measurement
Pulse width measurement
Programmable frequency and duty cycle waveform
output
• Single pulse output
a-Bit AID Converter
• 8 input channels
• 4 conversion result registers
• 2 powerful operation modes
- Autoscan mode
- Channel select mode
• Successive approximation technique
• Absolute accuracy: 0.6% FSR ± 1/2 LSB
• Conversion range: 0 to 5 V
• Conversion time: 38.4 ~s
• Interrupt generation
NEe
pPD78C1x/C1xA/CG14/CP14
Figure 1. Memory Map
o
Internal Program Memory
4,096 Bytes: 78C11/C11A
8192 Bytes: 78C12A
16,384 Bytes: 78C141C14A1
CG141CP14
(External Memory on 78C10/C10A)
0
ReseVStandby Release
4
IROO
8
IR01
10H
IR02
18H
IR03
20H
IR04
28H
lAOS
OFFFH
1000H
External
Memory
61,184 Bytes: 78C11/C11A
57,088 Bytes: 78C12A
48,896 Bytes: 78C141C14A1
CG14/CP14
FEFFH
FFOOH
Internal RAM
256 Bytes x8
FFFFH
~"I
SoftlNT
SOH
LowADDR
81H
HlghADDR
82H
LowADDR
83H
HighADDR
I
C8I1Table
BEH
LowADDR
BFH
COH
HlghADDR
}t=31
User's Area
83RD·6944B
5-13
NEe
pPD78C1X/C1xA/CG14/CP14
Figure 2.
Timer Block Diagram
. s - - - -.....-I
...----1
----,.
r:;:--------,I
TlmerO
~2----·1
To TlmeriEvent Counter
or Serial Clock Source
_~I
INITO
.s
B12
8384
I xtaI
Ixtal x .1/3
Ixtal x 1/12
Ixtal x 1/384
Input crysrallrequency
83RD.fI3688
5-14
NEe
pPD78C1x/C1xA/CG14/CP14
Figure 3. Block Diagram for the Timer!Event Counter
Internal Bus
612--1
PCstCI
TO Signal
from Interval
Timer FtF
Output
Control
Clock
Select
'-_ _ _ _--1
CP ,
CPo
INTEO
Interrupt
Control
INTEl
INTEIN
612='
1112
xtal x
'xtal: Input Crystal 'requency
83RD-s635B
Analog/Digital Converter
The jlPD78C1x/C1xA/Cx14 family features an 8-bit, highspeed, high accuracy A/D converter..The A/D converter
is made up of a 256-resistor ladder and a successive
approximation register (SAR). There are four conversion
result registers (CRO-CR3).
The eight-channel analog input may be operated in
either of two modes. In the select mode, the conversion
value of one analog input is sequentially stored in CROCR3. In the scan mode, either the upper four channels or
the lower four channels may be specified. Then those
four channels will be consecutively selected and the
conversion results stored sequentially in the four conversion result registers.
Figure 4 is the block diagram for the A/D converter. To
stop the operation of the A/D converter and thus reduce
power consumption, set VARE F = 0 V.
Interrupt Structure
There are 12 interrupt sources in the jlPD78C1x/C1xA/
Cx14 family of chips. Three are external interrupts and
nine are internal. Table 2 shows 11 interrupt sources
divided into seven priority levels where IROO is the
highest and IR06 is the lowest. See figure 5.
5-15
II
NEC
pPD78C1X1C1xA/CG14/CP14
Figure 4. AID Converter Block Diagram
AVC~------------~
AVSS------------,
VAREF-----------,
ANO -------I
AN 1 -------I
AN2 - - - - - - I
AN3 -------I
AN4 -----1ri
ANS ---.-1H
AN6 - ......+-1---1
AN7-P++-IH
Internal Bus
83RD-6638A
Figure 5. Interrupt Structure Block Diagram
NMI-INTTO-INTT1-INT1-INT2-INTEO-INTE1-INTEIN-INTAO-INTSR-INTST--
OV'---'--+ER-SB _ _
INTFNMI
Test
Control
• Skip Control
TFRequest
Register
Interrupt
Generation
Enable
Priority
Control
EI
S
01
R
~TF
Test
Flag
Register
INTFNMI--
AN4-AN7¢
Interrupt
Address
SOFTI-+-
5-16
Q
~I
83RD-6637B
NEe
pPD78C1X/C1xA/CG14/CP14
Standby Functions
The p.PD78C1xJC1xA/Cx14 family has two standby
modes: HALT and STOP. The HALT mode reduces power
consumption to 50% of normal operating requirements,
while maintaining the contents of on-chip registers,
RAM, and control status. The system clock and on-board
peripherals continue to operate, but the CPU stops
executing instructions. The HALT mode is initiated by
executing the HLT instruction. The HALT mode can be
released by any nonmasked interrupt or by RESET.
The STOP mode reduces power consumption to less
than 0.1% of normal operating requirements. There are
two STOP modes: type A and type B.
Type A is initiated by executing a STOP instruction. If
Vee is held above 2.5 V, the on-board RAM is saved. The
oscillator is stopped. The STOP mode can be released
by an input on NMI or RESET. The user can program
oscillator stabilization time up to 52.4 ms via timer 1. By
checking the standby flag (SB), the user can determine
whether the processor has been in the standby mode or
has been powered up.
Type B is initiated by inputting a low level on the STOP
input. The RAM contents are saved if Vee is held above
2.5 V. The oscillator is stopped. The STOP mode is
released by raising STOP to a high level. The oscillator
stabilization time is fixed at 52.4 ms; 52.4 ms after STOP
is raised, instruction execution will automatically begin
at location o. You can increase the stabilization time by
holding RESET low for the required time period.
Universal Serial Interface
The serial interface can operate in one of three modes:
synchronous, asynchronous, and I/O interface. The I/O
interface mode transfers data MSB first, for easy interfacing to certain NEC peripheral devices. Synchronous
and asynchronous modes transfer data LSB first. Synchronous operation offers two modes of data reception:
search and nonsearoh. In the search mode, data is
transferred one bit at a time from the serial register to the
receive buffer. This allows a software search for a sync
character. In the nonsearch mode, data transfer from the
serial register to the transmit buffer occurs eight bits at
a time. Figure 6 shows the universal serial interface block
diagram.
zero-Crossing Detector
The INT1 and INT2 terminals (used common to TI and
PC3) can detect the zero-crossing point of low-frequency
AC signals. When driven directly, these pins respond as
a normal digital input. Figure 7 shows the zero-crossing
detection circuitry.
Table 2. Interrupt Sources
Interrupt Request
Interrupt Address
Type of Interrupt
Internal/External
IROO
4
JijfiM .!Nonmaskable interrupt)
External
IRQ1
8
INTTO, INTT1 (Coincidence slynals from timers
0,1)
Internal
IRQ2
16
INT1,
IROO
24
INTEO, INTE 1 (Coincidence signals from timer/
event counter)
Internal
IRQ4
32
INTEIN (Falling signal of CI or TO Into the timer/
event counter)
Internal or External
INTAD (AID converter interrupt)
Internal
IRQ5
40
INTSR (Serial receive interrupt)
Internal
fN'i'2 (Maskable Interrupts)
External
INST (Serial send Interrupt)
IROO
96
SO FTI instruction
Internal
5-17
II
NEe
pPD78C1x/C1xA/CG14/CP14
Figure 6. Universal Serial Interface Block
Diagram
I
r
INTSR
-1>-
~
U
Receive Buffer
(RxB)
Serial Mode
Register
Transmit Buffer
(T xB)
n
~
Serial Register
(S-P)
Serial Register
(P-S)
!
1 !
i
Receive Control
~
l
r---- INTST
t---
Transmit Control
--ER
t
1
1_824
B24=lxtai x
e384
1
24
1 - Interval Timer FIF
/1384 = I xtal x 3:W
SK1,2J
Ixtai : Oscllla~on Frequency (MHz) 01 Crystal
PCo'TxD
83RD-66399
Figure 7. Zero-Crossing Detection Circuit
I
I
I~I
I
~L">.~/
II
I
II
I
Source
I
I
I.
--.-JI
Internal.
Signal
AC Input
I
--11--+0---..,....--1
1f1F
I
!rOutput
INT1
or
INT2
83RD-6643A
5-18
NEe
pPD78C1 X/C 1xA/CG 14/CP14
The zero-crossing detection capability allows you to
make the 50-60 Hz power signal the basis for system
timing and to control. voltage ph~se-sensitive devices.
To use the zero-cross detection mode, an AC signal of
1.0 to 1.8 V (peak-to-peak) and a maximum frequency of
1 kHz is coupled through an external capacitor to the
INT1 and INT2 pins.
Capacitance
TA =25'C; voo = Vss = 0 V
Max
Unit
10
pF
Output capacitance . Co
20
pF
1/0 capacitance
20
pF
Parameter
Symbol
Input capacitance
Cj
Cjo
Conditions
fc = 1 MHz;
unmeasured pins
returned to 0 V
For the INT1 pin, the internal digital state is sensed as a
the rising edge crosses the average DC level,
when it becomes a 1 and an INT1. interrupt is generated.
o until
For the INT2 pin, the state is sensed as a 1 until the
falling edge crosses the average DC level, when it
becomes a 0 and INT2 is generated.
ELECTRICAL SPECIFICATIONS
Absolut~
= 25"C
Maximum Ratings
TA
Power supply voltage, Voo
-C.5to +7.0V
Pow8r supply voltage, AVoo
AVss to Voo +0.5 V
Power supply voltage, AVSS
-0.5 to +0.5 V
Power supply voltage, VI'!' (IlPD78CP14 only)
Input voltage, VI
-C.5 to Voo +.5 V
STOP pin (IlPD78CP14 Only) .
-0.5 to '.+.1.3.5 V
-0.5 to Voo+.5 V
Output voltage, Vo
Output current, low; 10L
Each output pin
Total
4.0mA
100mA
Output current, high; 10H
Each output pin
Total
-2.0mA
-50mA
Reference input voltage,
II
-0.5 to + 13.5
V~EF
Operating temperature, TOPR
fxTAL :s 15 MHz
Storage temperature, TSTG
-0.5 to AVoo +0.3 V
-40 to +85'C
-65 to +15O'C
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent
damage. The device should be operated within the limits specified
under DC and AC Characteristics.
5-19
NEe
pPD78C1x/C1xA/CG14/CP14
Oscillation Characteristics
TA = -40 to +85°C; voo = AVoo = 5 V :I: 10% (:1:5% I4PD78CP14);
VSS ;" AVss= 0 V; Voo - 0.8 V s AVoo s Voo; 3.4 V s VAREF S AVoo
Resonator
Ceramic resonator
(Note 1) or XTAL
(Note 2)
External clock
Recommended
Circuit
Parameter
(Note 3)
Oscillation frequency (fxx)
(Note 4)
Min
Xl inputfrequency (fx)
Xl input, rise, fall time (t,.,
Max
Unit
Conditions
15
MHz
AID converter not used
5.8
15
MHz
AID converter used
6
15
MHz
I4PD78CP14 only
4
15
MHz
AID converter not used
5.8
15
MHz
AID converter used
6
15
MHz
I4PD78CP14 only
0
20
ns
20
250
ns
20
167
ns
4
tr)
Xl input low- and high-level
width (!CPL, !CPH)
Typ
I4PD78CP14
Notes:
(1) Refer to the Resonator and Capacitance Requirements table for
the recommended ceramic resonators.
(2) For XTAL, the following external capacitances are recommended: Cl = C2 = 10 pF
(3) For XTAL, see the Recommended XTAL or Ceramic Resonator
Oscillation Circuit Diagram.
(4) See the following recommended external clock diagram.
When using an external crystal, it should be a parallel-resonant,
fundamental mode, "AT cur' crystal. Capacitors Cl and C2 are
required for frequency stability. The values of Cl and C2 (Cl =
C2) can be calculated from the load capacitance (CU, specified
by the crystal manufacturer:
CL =
Cl xC2 +Cs
Cl + C2
Where Cs is any stray capacitance in parallel with the crystal such as
the I4PD78Cl0, I4PD78Cll, or I4PD78C14 input capacitance between
Xl and X2.
5-20
NEe
"PD78C1x/C1xA/CG14/CP14
Recommentled XlJIlL or Ceramic Resonator
Oscillation Circuit Dillgram
Recommended Exter".' Clock Oisgram
Clock
.:>0_+----1 Xl
HCMOS
Inverters
X2
External oscillation circuit should be as close to the
Xl and X2 pins as possible.
Do not place other signal lines In the shaded area.
Resonator and Capacitance Requirements
= -40 to +85"C
TA
Manufacturer
Product Number
Murata
CSA15.0MX3
TDK
Cl, C2 (PF)
22
CSA10.0MT
30
CST10.0MT
Not required
CSA6.00MG
30
CST6.00MG
Not required
CSA12.0MT
30
CST12.DMT
Not required
.CSA15.00MXOO1
15
CSA7.37MT
30
CST7.37MT
Not required
FCR12.0MC
Not requl red
Conditions
"PD78C10, 78Cll, 78C14,
78C14A, 780014
II
Applies to all "PD78Clx1C.1xAJCG14
"PD78C10A/78C11 A/78Cl2A
"PD78C10I78C11/78C14/
78C14A/78CG14
5-21
NEe
pPD78C1x/C1xA/CG14/CP14
DC Characteristics
TA = -40" to +85°C; voo
= +5.0 V ±10%; voo = +5.0 V ±
Parameter
Qu.... 1vt.1
Input voltage, low
VIL1
Input voltage, high
5% IIIPD78C14 only); Vss
T,_
=0V
P.1ax
Unit
0
0.8
V
VIL2
0
0.2Voo
V
Note 1 inputs
VIH1
2.2
Voo
V
All except XI, X2, and Note 1 inputs
VIH2
0.8Voo
Voo
V
XI, X2, and Note 1 Inputs
0.45
V
IOL
Voo-l.0
V
IOH
Vo o-0.5
V
M!n
-1·"--
"I'
Conditions
All except Note 1 inputs
= 2.0 rnA
= 1.0mA
IOH = -100 ItA
Output voltage, low
VOL
Output voltage, high
VOH
Data retention voltage
VOOOR
V
STOP mode
Input cu rrent
111
:1:200
p.A
INTl (Note 2); TI (PCal (Note 3); 0 V S VI S
Voo
Input cu rrent
IIIPD78CG14 only)
112
:1:200
p.A
INTI (Note 2); TI (PCal (Note 3); 0 V S VI S
Voo
Input current
IIIPD78CG14 only)
'13
-300
p.A
10-17 (upper input pin); VI
Input leakage current
ILl
±10
p.A
All except INT1, TI (PCal, 0 V S VI S Voo
Output leakage cu rrent
ILO
±10
ItA
OV S Vo S Voo
AVoo supply current
Al001
0.5
1.3
mA
f
Al002
10
20
p.A
STOP mode
1001
13
25
mA
Normal operation; f = 15 MHz;
IIIPD78CI0/C10NCI1/CIINCI2A only)
1002
7
13
mA
HALT mode; f = 15 MHz;
IIIPD78CI0/CI0NCI1/CIINCI2A only)
1003
16
30
mA
Normal operation; f = 15 MHz
IIIPD78CI4/CI4NCGI4)
32
rnA
Normal operation; f
IIIPD78CP14 only)
15
mA
HALT mode; f = 15 MHz;
(.<1PD78CI4/CI4NCG14/CP14 only)
15
p.A
VOOO R
Voo supply current
2.5
1004
8
1005
Data retention current
1000R
300
10
Pull up resistor
RL
17
27
50
75
=0
= 15 MHz
= 15 MHz;
= 2.5 V (Note 4)
IIIPD78CP14 only·Note 4)
= 5.0 V :!: 10% (Note 4)
,.A
VOOOR
mA
IIIPD78CP14 only·Note 4)
KIl
PortA, B, C; 3.5V S Voo S 5.5 V; VI
IIIPD78CIINCI2NCI4A only)
= OV
Notes:
(1) Inputs RESET, STOP, NMI, SCK, INTP1, TI, and AN4·AN7.
(2) Assuming ZCM register is set to self·blas.
(3) Assuming ZCM register Is setto self·bias and the MCC register is
set to control mode.
5-22
(4) Hardware/software STOP mode and assuming ZCM register is
set to self·bias not selected.
t-rEC
JlPD78C1x/C1xA/CG14/CP14
Serial Operation
Parameter
Symbol
Min
~CYCletlme
tCYK
0.8
p.S
~ Input (Notes 1, 3)
0.4
p.S
~ Input (Note 2)
1.6
p.S
~ output (Note 3)
335
ns
~ Input (Notes 1, 3)
160
ns
~ Input (Note 2)
700
ns
~ output (Note 3)
335
ns
~ Input (Notes 1, 3)
160
ns
~ Input (Note 2)
~wldthlow
lKKL
~widthhigh
lKKH
Max
Unit
Conditions
700
ns
~ output (Note 3)
RxD setup time to ~ t
tAXI<
80
ns
(Note 1)
RxD hold time after ~ t
lKRX
80
ns
(Note 1)
~ ~ TxD delay time
ltax
ns
(Note 1)
210
Notes:
(3) fxTAl = 15 MHz.
(1) 1 x baud rate in synchronous or I/O Interface mode.
(2) 16 x baud rate or 64 x baud rate In asynchronous mode.
II
Zero-Cross Characteristics
Max
Unit
Vzx
1.8
VACp..p
Azx
±135
mV
1
kHz
Parameter
Symbol
Zero-eross detection Input
Zero-eross accuracy
Zero-eross detection Input frequency
fzx
Min
0.05
Condition
AC coupled 60 Hz sine wave
AC Characteristics (cant)
TA= -40' to +85"C; Voo = AVoo = +5.0V ±10'lb (±5'lb on "PD78CP14); Vss =OV
Parameter
Symbol
RESET pulse width high, low
tRSH, ~SL
Min
NMI pulse width high, low
fNIH, fNlH
10
Xl input cycle time
tC'I'C
86
tAL
30
lLA
tAR
Address setup to A LE
Address hold to ALE
Address to
~
~
AD ~ delay time
Max
10
Unit
Conditions
p.S
250
"s
ns
167
ns
(Note 1)
ns
(Notes 2,3)
35
ns
(Notes 2, 3)
100
ns
(Notes 2, 3)
RD ~ to address floating
tAFR
20
ns
(Note 2)
Address to data Input
tAD
250
ns
(Notes 2, 3)
ALE ~ to data input
It.OR
135
ns
(Notes 2, 3)
RD ~ to data input
tRO
120
ns
(Notes 2,3)
ALE Ho RD
~
delay time
Data hold time Ri5 t
RD t to ALE t delay time
RDwidth low
It.R
15
ns
(Notes 2, 3)
tRDH
0
ns
(Note 2)
till
80
ns
(Notes 2, 3)
tRR
215
ns
Data read (Notes 2, 3)
415
ns
Opcode fetch (Notes 2, 3)
5-23
ttiEC
pPD78C1X/cixA/CG14/CP14
AC Characteristics (cont)
Parameter
Unit
Conditions
90
ns
(Notes 2, 3)
IML
30
ns
(Note 3)
ILM
35
ns
(Note 3)
IlL
30
ns
(Note 3)
III
35
ns
(Note 3)
100
ns
(Notes 2, 3)
Symbol
Min
ALE width high
Ml setup time to ALE
~
Ml hold time after ALE ~
iO/M setup time to ALE ~
iO/M hold time after ALE ~
Address 10 WR ~ delay
Max
ALE Ho data output
lLow
180
ns
(Notes 2, 3)
WR ~ to data output
two
100
ns
(Note 2)
ALE ~ to WR ~ delay time
15
ns
(Notes 2,3)
Data setup time to WR i
tow
165
ns
(Notes 2, 3)
tWOH
60
ns
(Notes 2, 3)
WR i to ALE i delay time
80
ns
(Notes 2,3)
WRwidth low
215
ns
(Notes 2, 3)
ns
(Notes 2, 3)
ns
(Note 2)
Data hold time to WR i
tww
Address to data input
250
tACC
Data hold time from address
0
Notes:
(3) Values' are for 15-MHz operation. For operation at other frequencies, refer to the table called Bus Timing Depending on tC'I'C'
(1) Applies to "PD7SCPI4 only.
(2) Load capacitance CL
=
150 pF.
AID Converter Characteristics
TA = -40°·to +85°C; voo = +5,0 V ±10% (±5% on "PD78CPI4); Vss = AVss OV;
Voo -0.5 V ,;;. AVoo ,;; Voo; 3.4 V ,;; VAREF .,;; AVoo
Parameter
Symbol
Resolution
Min
Typ
Sampling time
tCONV
tSAMP
VIAN
Analog input impedance
RAN
Reference voltage
VAREF
VAREF current
IAREFI
AVoo supply current
TA = -10 to +700C; 66 ns ,;; tcyc
4.0 V ,;; VAREF S AVoo
%FSR
±0.6
%FSR
66 ns ,;; tcyc ,;; 170 ns; 4.0 V ,;; VAREF ,;; AVoo
±0.8
%FSR
66 ns ,;; tC'I'C ,;; 170 ns; 3.4 V ,;; VAREF ,;; AVoo
576
tcyc
66 ns ,;; tC'I'C ,;; 110 ns
432
tcyc
110 ns s tC'I'C s 170 ns
tcyc
66 ns ,;; tcyc ,;; 110 ns
tcyc
110 ns ,;; tC'I'C ,;; 170 ns
96
0
VAREF
V
M!l
1000.
AVoo
V
1.5
3.0
mA
Operation mode
IAREF2
0.7
1.5
mA
STOP mode
AlDOl
0.5
1.3
mA
Operation mode
Alo02
10
20
"A
STOP mode
3.4
Notes:
(1) Quantizing error (±1/2 LSB) is not inciuded.
(2) FSR = Full-scale resolution.
5-24
Conditions
±0.4
72
Analog input voltage
Unit
bits
Absolute accuracy
(Note 1)
Conversion time
Max
8
S
170 ns;
NEe
pPD78C1X/C1xA/CG14/CP14
Bus Timing Dependent on tCYK
Symbol
Min/Max (ns)
Calculation Formula
Symbol
tTIH' tTIL
Min
ST (TI input - peal
tiL
tCI1H. tCI1L
(Note 2)
Min
ST (TI input - pes)
tCI2H. tCI2L
(Note 3)
Min
48T (TI input - pes)
tllH' tilL
Min
3ST (INTI)
t12H. tl2L
tANH. tANL
Min
Min
Min
tAL
U
Min
tAR
Min
Min/Max (ns)
Calculation Formula
Min
2T - 100
tLi
Min
T-30
tAW
Min
3T - 100
tLOW
Max
T + 110
It.w
Min
T-50
tow
Min
4T - 100
3ST (AN4-AN7)
tWOH
Min
2T-70
2T - 100
tWL
Min
2T-50
tww
Min
4T-50
tCYK
Min
12T ~ input) (Note 1)
Min
24T (~ output)
Min
5T + 5 ~ input) (Note 1)
Min
12T - 100 ~ output)
Min
5T + 5 (SCR input) (Note 1)
Min
12T - 100 (SCK output)
3ST
QNT2)
T-30
3T -100
lAD
Max
7T -220
~OR
Max
5T - 200
tRo
Max
4T - 150
~
Min
T-50
tRL
Min
tKKL
tKKH
2T-50
Min
4T - 50 (Data read)
Notes:
Min
7T - 50 (Opcode fetch)
(1) 1 x baud rate in synchronous or I/O interface mode; T
~
Min
2T-40
tML
Min
2T - 100
tLM
Min
T-30
tRR
= tcyc =
1/fXTAL'
The items not included in this list are independent of oscillator
frequency (fXTAU'
(2) Event counter mode.
(3) Pulse width measurement mode.
Data Memory STOP Mode Data Retention Characteristics
TA
= -40 to 85'C
Parameter
Symbol
Min
Data retention power supply voltage
VOOOR
2.5
Data retention power supply current
IOOOR
Typ
15
Max
Unit
5.5
V
15
p.A
VOOOR
50
p.A
VOOOR
p.A
VOOOR
rnA
VOOOR
300
200
Conditions
= 2.5V
= 5.0 V ±10%
= 2.4 V (p.PD78CPI4)
= 5.0 V :1:5% (p.PD78CPI4)
p.s
VOO rise. fall time
tRv'o,1fvo
STOP setup time to VOO
STI5P hold time from VOO
tSSTVO
12T +0.5
p.s
tHvOST
12T+0.5
p.s
5-25
B
NEe
pPD78C1X/C1xA/CG14/CP14
Timing waveforms
Data Retention Timing
VOOOR
tFVO
tRVD
~~,----.-~
83RD-6847A
Read Operation
1t-4---T1----t-"I"~--T2---+rtO-----T3
-----10'
X1
AB1s-ABe
[PF7-PFo]
ADOR15-AOORe
~------------------tAD----------~----~
AD7-ADO
[PD7-PDO]
ADDR7-ADDRO
1
tRDH
Data In
t------I------tLDR --'---------~
tAFR
tRL
ALE
~--------tRD--------~
1-------tRR----------~
MODEO [iO]
[Note 1]·
Note:
[1] iO signal is output to the MOOED pin [II MOOED Is pulled up to VDD] during a
raad or write olspeelal ragI8ter,_ sr-sr2 or a write to ragister MM or MF. ReIer to
description 01 Port Emulatton Mode [PEM] In the Use,.s Manual lor lurther
explanation. This signal Is not output on the PPD78CP14.
83-0042768
5-26
NEe
IIPD78C1x/C1xA/CG14/CP14
Write Operation
1~·----------Tl--------~~----------T2--------~·+I·~--------T3--------~'I
Xl
AB15-ABS
[PF7-PF ol
ADDR15-ADDRS
AD7-ADO
[PD7-PD ol
Data-out
~-----------tow----------~
ALE
~--------------
tww ------------~
MODEO [iOl
[Note 11
Note:
[11 iO signalis output to the MODEO pin [if MODEO is pulled upto Vool during a
read orwrile of special, registers sr..sr2 or a write to register MM or MF. Refer to
description of Port Emulation Mode [PEMI in the Us.r's Manual for further
explanation, Thl. signal I. not output on the IlPD78CP14,
83-0042788
5-27
ttlEC
pPD78C1X/C1xA/CG14/CP14
Opcode Fetch Oper.tlon
~1'------T1----~'~I'~----T2------'~I.'------T3----~'~1'~----T4------'~1
X1
AB15-ABS
[PF7-PFO]
-y:)
ex -
ADDR15-ADDRB
I-
lAD
AD7-ADO
[PD7-PDo]
)
Opcode
ADDR7-ADDRo
IRDH
~------'1
ILDRILL-
-ILA-
..... I--IAFR
I---IRL-
/
ALE
~IAL
____
i-"--IRDIRR
!--ILR ....
IAR
MODE1 [!Mi']
[Nole1]
/
!.---IML-
~ ILM
Nole:
[1] M1 signal i. oulpullO Ihe MODEl pin during every Opcode Felch II MODE1
pin 18 pulled up 10 VDD. This IIgnalll nol output on the J,iPD78CP14.
83-0042798
5-28
NEe
pPD78C1x/C1xA/CG14/CP14
Serial Operation Transmit/Receive Timing
•
'CYK
~
_'KKL_I_'KKH_
/I
\
1-'KTx)
TxD
I
RxD
)
K
.'RXK. . 1 1•
'KRX
~
83R[)....69518
Timer Input Timing
Timer/Event Counter Input Timing:
Event Counter /IIode
83-003287A
83-Q0328SA
5-29
pPD78C1X/ClxA/CG14/CP14
11mer/EVent Counter Input Timing:
External Clock Timing .
Pulse Width Jleaillinlment lIode·
·1
~----~~----------~I
X1
83-003289A
83-003292A
Interrupt Input Timing
AC 11mlng "IiI.t PoInt.
NMI
~F·-=1[~'J.....--·
VDD-1.0==X: 2.2 V .... Test Points .... 2.2 V
0.45'1
.
0.8V ~
...... 0.8 V
C
83-003283A
,~ ~""J='""ll.....-
,~
AN4-AN7 Edge Detection 11mlng
J".=(..J.....-83-OO3290A
pPD7BCGI4E EPROM Read 11mlng
RESET Input 11mlng
RESET
J.tRSHJ[tRSLJ_
0.8 VDD
0.2VDD
63-003291A
7---- ----
10- 1
83RD-008OA
5-30
NEe
pPD78C1X/C1 xA/CG14/CP14
I'PD78CP14 PROGRAMMING
Table 3.
In the ~PD78CP14, the mask ROM of the ~PD78C1X/
C1XA is replaced by a one-time programmable ROM
(OTP ROM) or a reprogrammable, ultraviolet erasable
ROM (UV EPROM). The ROM is 16,384 by 8 bits and can
be programmed using a general-purpose PROM writer
with a ~PD27C256A programming mode. Refer to tables
3 through 5 and the AC and DC Programming Characteristics for specific information applicable to programming the ~PD78CP14.
The PA-78CP14CW/GF/GQ/L are the socket adapters
used for configuring the ~PD78CP14 to fit a standard
~PD27C256A PROM socket.
Table 4.
Pin Functions during EPROM
Programming
Pin
Function
PAo-PA7
Ao-A7
Description
Low-order S-bit address
PFo
As
High-order 7 -bit address
NMI
Ag
PFz-PF6
A1o-A14
PDo-PD7
Do-D7
Data input/output
PB6
mE
Chip enable input
PB7
()E
Output enable input
RESET
RESET
PROM programming mode requires a
low voltage on this pin
Mode 0
Mode 0
Enter PROM programming mode by
applying a high voltage to this pin
Mode 1
Mode 1
Enter PROM programming mode by
applying a low voltage to this pin
STOP
Vpp
High-voltage Input (write/verify) high
level (read)
Summary of Operation Modes for EPROM Programming
CE
OE
Vpp
Voo
RESET
MODEO
Program write
L
H
+12.5V
+6V
L
H
L
L
Program verify
H
L
+12.5V
+6V
L
H
L
L
Operation Mode
MODE1
A14
Program inhibit
H
H
+12.5V
+6V
L
H
L
L
Read
L
L
+5V
+5V
L
H
L
L
Output disable
L
H
+5V
+5V
L
H
L
L
Standby
H
L/H
+5V
+5V
L
H
L
L
Notes:
(1) The CE, OE, Vpp , and VOD pins are all compatible with the
",PD27C256A pins.
Caution: When Vpp is set to + 12.5 V and VOO is set to +6 V, you
cannot set both mE and OE to low level (L).
5-31
II
NEe
pPD78C1X/C1xA/CG14/CP14
Table 5. Recommended Connections tOl' UllUtled
Pins (EPROM Pr.ammlng.llode)
Recommended C-onnectlon Method
Pin
PROM Read Procedure
(1)
FIX the RESET pin, the MODE1 pin, and A14 pin to
a low level and connect the MOOEO pin to a high
level.
Connect to Vss
INT1
Xl
. Connect to Vss
X2
ANO-AN7
Connect to Vss
Apply
Input the address of the data to be read to pins
Ao-A14'
(4)
Read mode is entered with a pulse (active low) on
both the CE and OE pins.
(5)
Data is output to the 00-07 pins.
Connect to Vss
AVec
Connect to Vss
AVss
Connect to Vss
Remaining pins
Connect each pin via a resistor to Vss
+ 5 V to the Voo and Vpp pins.
(2)
(3)
Leave this pin disconnected
EPROM Erasure
PROM Write Procedure
( 1) Connect the RESET pin, the MOOE1 pin, and A14
pin to a low level and connect the MODEO pin to a
high level. Connect all unused pins as recommended in Table 5.
+6 V to the Voo pin and + 12.5 V to the Vpp
Data in an EPROM is erased by exposing the quartz
window in the ceramic package to light having a wavelength shorter than 400 nm, including ultraviolet rays,
direct sunlight, and fluorescent light. To prevent unintentional erasure, mask the window.
Typically, data is erased by 254-nm ultraviolet rays. A
minimum lighting level of 15W-s/cm2 (ultraviolet ray
intensity x· exposure time) is required to completely
( 3) Provide the initial address.
erase written data. Erasure by an ultraviolet lamp rated
at 12 mW/cm2 takes approximately 15 to 20 minutes.
( 4) Provide write data.
Remove any filter on the lamp and place the device
(.5) Provide 1-ms p~ogram pulse (active low) to the CE . within 2.5 cm of the lamp tubes.
pin.
( 2) Apply
pin.
( 6) This bit is now verified with a pulse (active low) to
the OE pin. If the data has been written, proceed to
step 8; if not, repeat steps 4 to 6. If the data cannot
be correctly written after 25 attempts, go to step 7.
( 7) Classify as defective and stop write operation.
( 8) Provide write data and supply program pulse (for
additional writing) for 3 ms times the number of
repeats performed between steps 4 to 6.
( 9) Increment the address.
(10) Repeat steps 4 to 9 until the end address.
5-32
NEe
pPD78C1x/C1xA/CG14/CP14
"PD78CP14 DC Programming Characteristics
TA
= 25 :l:5°C; MODE1
= VIL; MODEO = VIH; Vss = 0 V
Parameter
SymllCll
Symbol*
MIn
High-level Input voltage
VIH
VIH
2.2
-0.3
Low-level Input voltage
VIL
VIL
Input leakage current
ILIP
III
High-level output voltage
VOH
VOH
Low-level output voltage
VOL
VOL
Typ
Max
UnIt
Voop+0.3
V
0.8
V
:1:10
f!A
Output leakage current
ILO
Voop
VCC
5.75
4.5
Vpp power voltage
Vpp
Vpp
12.2
10H = -1.0mA
0.45
V
10L = 2.0mA
100
= VIH
:1:10
f!A
o :S; Vo
6.25
V
Program memory write mode
5.0
5.5
V
Program memory read mode
12.5
12.8
V
program memory write mode
V
Program memory read mode
30
mA
Program memory write mode
30
mA
6.0
Vpp=Voop
Voop power current
Os V1 S Voop
V
Voo-1.0
Voop power voltage
ConditIon
Icc
s VooP; 'OE
Program memory read mode;
= VIL; VI = VIH
'CE
Vpp power current
Ipp
Ipp
mA
30
Program memory read mode;
'CE - VII': 'OE - VIH
100
f!A
Program memory write mode
* Corresponding symbols of the "PD27C256A.
"PD78CP14 AC Programming Characteristics
TA = 25 :l:5°C; MODE1 = VIU Vss = 0 V
. Symbol*
Parameter
Symbol·
Address setup time to 'CE .).
tsAC
tAS
2
1'8
Min
Typ
Max
Unit
Data to OE .). delay time
tOOOO
tOES
2
1'8
Input data setup time to CE .).
tSIOC
tos
2
1'8
Address hold time from CE i
tHCA
tAH
2
1'8
Input data hold time from 'CE i
tHCIO
tOH
2
Output data hold time from 'OE i
tHOOO
tOF
0
Vpp setup time to 'CE J.
tSVPC
tvps
2
Voop setup time to 'CE .).
tsvoc
tvos
2
Initial program pulse width
tWL1
tpw
0.95
Additional program pulse width
tWL2
topw
2.85
MODEO/MODE1 setup time VB. 'CE.).
tSMC
Address to data output time
toAOD
tACC
CE .). to data output time
'OE .). to data output time
Data hold time from OE i or 'CE i
tocoo
tCE
toooo
tOE
tHCOO
tOF
0
Data hold time from address
tHADO
tOH
0
Condition
I'is
130
ns
1'8
1'8
1.0
1.05
ms
78.75
ms
2
2
1'8
MODE1 = VIL and MODEO = VIH
1'8
OE = VIL
"s
130
"s
ns
ns
OE = VIL
* Corresponding symbols of the "PD27C256A.
5-33
B
NEe
IIPD78C1x/C1xA/CG14/CP14
pPD711CP14 PROM Write lIIode Timing
Ao-A14
~1~----~----------~----------------~--------~~ J~--~---------------
.-J
-
Effective Address
-.
_tSAC
--<
Mode 1 VIH
MedeO V Il
-
Data
Input
~IDC_
~
_
Data
Output
tHeID
~-
---
tHooD
tSIDC _
=>--
-
Data
Input
--
I--
K
tHCA
tHeID
Mode 1 =Vll
Mode 0 =VIH
tSMC
VPP
VPP
VDOP
VDDP + 1
VDDP
VDOP
--.I
--
~
tsvPC
~VDC
r---;
tWl1
"'--
- ~L=o
tDDoo
_tWl2_
S
Notes:
(1)
VDOP must be applied before applying Vpp. It should be removed afterremovlng Vpp.
(2)
Vpp must not exceed +13 V, Indudlng overshoot.
83RD-6948B
5-34
ttiEC
pPD78C1xJC1xA/CG14/CP14
pPD7BCP14 PROM Relld Mode Timing
Effective Address
CE
HI-Z
Notes:
(1)
To read PROM within the tOAOD range, the delay of 5E~ from CE~must be within t OAOO - toooo-
(2)
tHCOD Is the time from the state In which either 5E or CE flrst becomes V IH83RD·69498
5-35
ItIEC
pPD78C1x/C1xA/CG14/CP14
Operand Definitions
Operand Symbols
Symbol
Registers
r
r1
r2
Allowable Dpernds
V, A, B, C, D, E, H, L
EAH, EAL, B, C, D, E, H, L
A, B, C
Special Registers
sr
PA;PB, PC, PD, PF, MKH, MKL, ANM, SMH, SML, EOM,
ETMM, TMM, MM, MCC, MA, MB, MC, MF, TXB,
.TMO, TM1, ZCM
sr1
PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM, RXB,
CRO, CR1, CR2, CR3
sr2
sr3
sr4
PA, PB, PC, PD, PF, MKH, ANM, MKL, SMH, I!OM, TMM
ETMO, ETM1
ECNT, ECPT
Register Pairs
rp
rp1
rp2
rp3
SP, B, D, H
V, B, D, H, EA
SP, B, D, H, EA
B, D, H
Special Registers (sr-sr4)
PA= PortA
PB = Port B
PC = Port C
PD = Port D
PF = Port F
MA = Mode A
MB = Mode B
MC= Mode C
MCC = Mode control C
MF= Mode F
ECNT = Timer/event
counter upcounter
ECPT = Timer/event
counter capture
ETMM = Timer/event
counter mode
EOM = Timer/event
counter output mode
°
MM = Memory mapping
TMO = Timer register
TM1 = Timer register 1
TMM = Timing mode
ETMO = Timer/event counter
register 0
ETM1 = Timer/event counter
register 1
ZCM = Zero-cross mode
control register
Register Pair Addressing
Register Pairs (rp-rp3)
rpa
rpa1
B, D, H, D+ , H+ , D-, HB, D, H
rpa2
B, D, H, D+, H+, D-, H-, D+byte, H+A, H+B,
H+EA, H+byte
SP = Stack pOinter
B=BC
D= DE
rpa3
D, H, D++, H++, D+byte, H+A, H+B, H+EA, H+byte
Flags
CY,HC,Z
Interrupt Flags
irf
INTFNMI, INTFTO, INTFT1, INTF1, INTF2, INTFEO, INTFE1,
INTFEIN, INTFAD, INTFSR, INTFST, ER, OV, AN4, AN5, AN6,
AN7, SB
Immediate Data
wa
word
byte
bit
5-36
8-bit immediate data (low byte of working register address)
16-bit immediate data
8-bit immediate data
3-bit immediate data (b2, b1, bo)
TXB = Transmit buffer
RXB = Receive buffer
. SMH = Serial mode high
SML = Serial mode low
MKH = Mask high
MKL = Mask low
ANM = A/D channel mode
CRO to CR3= A/ Dconversion
result 0-3
H = HL
V=VA
EA = Extended accumulator
Register Pair Addressing (rpa-rpa3)
B = (BC)
D= (DE)
H = (HL)
D+ = (DE)+
H+ = (HL)+
D- = (DE)H- = (HL)-
D++ = (DE)++
H++ = (HL)++
D+byte = (DE+byte)
H+byte = (HL+byte)
H+A = (HL+A)
H+B = (HL+B)
H+EA = (HL+EA)
Flags (f)
CY = Carry
HC = Half-carry
Z = Zero
Interrupt Flags (Irf)
INTFNMI = NMI interrupt flag
INTFTO = flO
INTFT1 = FT1
INTF1 = F1
INTF2 = F2
INTFEO = FEO
INTFE1 = FE1
. INTFEIN = FEIN
INTFAD = FAD
INTFSR = FSR
INTFST= FST
ER = Error
OV = Overflow
AN4 to AN7 = Analog input 4-7
SB = Standby
fttfEC
pPD78C1x/C1xA/CG14/CP14
Operand Codes
Special Registers (sr3)
Registers (r, r2)
R2
Rl
Ro
Reg
r2
Uo
Special Reg
0
0
0
0
0
0
1
1
0
1
0
1
V
o
A
B
C
1
ETMO
ETMI
0
0
1
1
0
1
0
1
D
E
H
L
I
Special Registers (sr4)
Tl
To
Reg
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EAH
EAL
B
C
D
E
H
L
S4
S3
S2
SI
So
Special Reg
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
0
1
1
0
0
1
0
1
1
0
1
0
1
PA
PB
PC
PD
PF
MKH
MKL
ANM
SMH
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
ETMM
TMM
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
0
1
0
MM
MCC
MA
MB
MC
MF
TXB
1
0
0
1
RXB
0
1
TMO
TMI
0
0
sr
srI
sr2
PI
Po
Reg Pair
0
0
0
0
0
0
1
1
0
0
1
0
1
0
SP
rp
0
0
0
0
0
0
1
1
0
1
0
1
CRO
CRI
CR2
CR3
0
0
0
ZCM
Q2
Ql
0
0
0
0
1
0
0
1
1
0
Qo
0
1
0
1
0
rp2
rp3
III
BC
DE
HL
EA
Reg Pair
VA
BC
DE
HL
EA
Register Pair Addressing (rpa, rpa1, rpa2)
A2
SML
EOM
1
0
0
0
0
0
P2
Register Pairs (rp1)
S5
0
0
0
0
0
0
0
ECNT
ECPT
Register Pairs (rp, rp2, rp3)
Special Registers (sr, sr1, sr2)
1
Special Reg
o
1
Registers (r1)
T2
Vo
I I
II
AO
Addressing
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
-
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
(DE)+
(HL)+
(DE)(HL)-
0
1
1
0
1
1
1
0
1
1
1
0
1
0
1
(DE+byte)
(HL+A)
(HL+B)
(HL+EA)
(HL +byte)
rpa2
(BC)
(DE)
(HL)
Register Pair Addressing (rpa3)
C3
C2
Cl
Co
0
0
0
0
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
0
0
1
0
0
1
1
0
1
0
1
1
0
1
0
1
Addressing
(DE)
(HL)
(DE)++
(HL)++
(DE+byte)
(HL+A)
(HL+B)
(HL+EA)
(HL+byte)
5-37
tttfEC
pPD78C1X/C1xA/CG14/CP14
Operand Codes (conI)
Graphic Symbols
Symbol
Flags (f)
Description
Transfer direction, result
F2
F1
Fo
Flag
0
0
0
1
0
1
1
0
0
0
1
0
/\
Logical product (logical AND)
CY
HC
V
Logical sum (logical OR)
Z
-¥
14
13
12
11
10
Flag
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
NMI
0
0
0
0
0
0
0
0
0
0
0
0
5-38
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
1
1
0
0
0
1
1
0
Exclusive-OR
Complement
Interrupt Flags (Irf)
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
FTO
FT1
F1
F2
FEO
FE1
FEIN
FAD
F5R
F5T
ER
OV
AN4
AN5
AN6
AN7
58
Concatenation
Instruction Set
Operation Gode
12
II
-
rilaemonic
Operand
Operation
7
6
5
13
4 3
0
0
0
0
0
stale
B4
2
1
0
7
6
5 4 3
2
1
0
(Nole 1)
lyleS
Skip
Condition
B-BltData Transfer
MOV
MVI
r1,A
A, r1
(r1) +- (A)
(A)+-(r1)
0
0
'sr,A'
'A,sr1
r,word
(sr)+-(A)
(A) +- (sr1)
(r) +- (word)
0
0
0
word,r
(word) +- (r)
0
'r,byte (r) +- byte
sr2,byte (sr2) +- byte
0
0
MVIW
'wa, byte ((V).(wa)) +- byte
0
MVIX
STAW
LDAW
STAX
LDAX
EXX
'rpa1,byte (rpa1) +- byte
((V).(wa)) +- (A)
'wa
(A) +- ((V}.(wa))
'wa
0
0
0
A3
A3
0
EXA
EXH
BLOCK
'rpa2
'rpa2
((rpa2)) -- (A)
(A) -- ((rpa2))
(B) - (B'), (C) - (C'), (D) - (0')
(E) - (E'), (H) - (H'), (L) - (L')
(V) - (V'), (A) - (A'), (EA) .... (EA')
(H) - (H'), (L) - (L')
((DE)) +- ((HL)), (DE) -- (DE) + 1,
(HL) -- (HL) + 1, (C) +- (C)-l
End if borrow
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
1 0 1
1 1 0 0
0 0 0 0
Lowaddr
1 0 0 0 0
Lowaddr
0 1 R2 R1 Ro
0 0 1 0 0
Data
1 0 0 0
Data
0 1 o A1 Ao
0 0 0 1 1
0 0 0 0
1
A2 A1 Ao
0
A2 A1 Ao
0 0 0
0
0
0
0
0
0
0
0
16-8H Data Transfer
DMOV
rp3, EA (rp3tJ -- (EAL), (rp3H) +- (EAH)
0
1
(rp~)
0
0
EA,rp3 {EAL) -- (rp3L), (EAH) --
4
4
T2 T1 To
T2 T1 To
0
0
0
0
0
0
0
0
S5S4S3~S1S0
Ro
10
10
17
2
2
4
Ro
17
4
7
0 0 OS2 S1 S0
14
2
3
Offset
13
3
Data
Offset
Offset
Data (Note 2)
Data (Note 2)
10
10
10
2
2
2
2
2
1
0
S5S4S3~S1So
0
1 0 1 R2 R1
High addr
1 1 1 R2 R1
High addr
Data
S3 0
7/13 (Note 3)
7/13 (Note 3)
4
4
4
13x
(C+1)
0
0
4
P1 Po
P1 Po
4
Notes:
(1) For the skip con~ition, the idle states are as follows:
2-byte instruction (with '): 7 states
1-byte instruction: 4 states
2-byte instruction: 8 states
3-byte instruction (with '): 10 states
3-byte instruction: 11 states
4-byte instruction: 14 states
~
~
(2) 82 (Data): rpa2 = D+byte or H+byte.
(3) Right side of slash (/) in states indicates case rpa2 or rpa3 = D+byte, H+A,
H+8, H+EA, or H+byte.
(4) B3 (Data): rpa3 = D+byte or H+byte.
"I:
"....
C
ext
(")
....
~
....
~
G)
....
~
(")
"....
en
I
(,)
~
<0
II
en
~
o
"C
Instruction Set (cont)
"'a
o
.....
Operation Code
II
Mnemonic
Operand
7
Operation
6
5
4
13
3
~
2
1
0
U
4 321
765
State
0
(Note 1)
Iytes
14
2
14
2
20
4
a
20
4
1 1 1
High addr
a
20
4
a a a a 1
a
20
4
14/20 (Note 3)
3
20
4
20
4
20
4
00001
High addr
20
4
a a a
14/20 (Note 3)
3
16-BII Data Transfer (conti
[)MOV
SBCD
a a
a a
a
a
5r3. EA (5r3) +- (EA)
EA.5r4
(EA) +- (5r4)
word
(word) +- (C). (word
a
+ 1) +- (B)
a a a
a a a
a a a 0
a
a a 1 Uo
1 1 a a a a a Vo
a a a 1 1 1 1 a
Lowaddr
SDED
word
(word)+- (E). (word
a
+ 1) +- (D)
High addr
100
a a
a
1
Lowaddr
SHLD
word
(word) +- (L). (wor{f + 1) +- (H)
SSPD
word
(word) +- (SPLl. (word
a
+ 1) + - (SPH)
100
Lowaddr
a
a a
1 a a 0 a
a a
Lowaddr
STEAX
rpa3
((rpa3»
+-
(EAL). (((rpa3))
+ 1)) + - (EAH)
a
0
1
High addr
High addr
a a 1 a a a
a a
1 C3 C2 C1 Co
Skip
Condition
CI)
n
....
~
n
....
~n
G)
....
~"'a
.....c;.
Data (Note 4)
LBCD.
LDED
word
word
(C)
(E)
+-
(word). (D) + - (word
+-
a
(word). (B) + - (word + 1)
a
+ 1)
1 a a
Lowaddr
1
1
1
;1
~ow
LHLD
word
(L)
(word). (H) + - (word
+-
+ 1)
0
1
1
a
0
0
a
00011111
High addr
00
00101
addr
0
High addr
a a
~
a a
Lowaddr
LSPD
word
(SPLl
+-
(word). (SPH)
+-
(word + 1)
0
a
1
High addr
0
a
0
Lowaddr
LDEAX
rpa3
(EAL)
+-
((rpa3)). (EAH)
+-
(((rpa3)
+ 1))
a
1
0
a
1.
a a a
C3 C2 C1 Co
Data (Note 4)
PUSH
POP
LXI
rpl
rpl
(((SP) -1))
(((SP) - 2))
+-
(rplH).
(rplLl. (SP)
(rplL) +- ((SP)). (rplH)
(SP) + - (SP) + 2
*rp2.word (rp2)
TABLE
+-
(0)
(B)
+-
+-
+-
+-
(((SP)
(word)
(((PC) + 3 + (A))).
+ 3 + (A) + 1))
0110020100
13
0100020100
10
(SP) - 2
+ 1)).
a
P2 P1 Po a 1
High byte
a
1
001
a
a a
0
a
Low byte
10101
a a a
+- (((PC)
10
3
17
2
8
8
8
8
2
2
2
2
8-Bit Arithmetic [Registerl
ADD
ADC
A.r
(A)
r.A
(r)
A.r
r.A
+-
(A)
+ (r)
+ (A)
(A) + - (A) + (r) + (CY)
(r)
+-
+-
(r)
(r)
+ (A) + (CY)
a
a
o
o
a a a a a
a a a a 0
0 a 0 0 0
o
0
o
0
0
0
0
1
1
~ ~
~
~
~
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0 R2 R1 Ro
a R2 R1 Ro
~
~
o
Instruction Set (cont)
Operation Code
Bl
B3
Mnemonic
Operand
Operation
B2
B4
7
6
5
4
3
2
1
0
7
6
5
4
3
2
0
0
a
a
a
a
a
0
a
0
a
0
0
a
a
a
0
0
a
0
0
1
1
1
1
1
1
0
0
0
0
a
a
a
a
a
a
a
0
a
0
a
a
0
0
0
0
a
0
0
a
0
a
0
a
0
a
a
a
0
0
a
a
a
a
0
0
0
0
0
0
a
0
a
a
a
0
0
a
a
0
a
a
a
0
a
0
0
a
0
0
0
a
a
a
a
a
0
0
a
a
0
a
a
a
a
0
a
0
0
0
1
a
1
a
1
a
1
a
1
a
1
a
1
a
1
a
1
0
1
0
1
0
0
1
1
1
1
a
a
a
a
a
0
0
a
a
a
0
a
1
1
1
1
1
1
1
0
a
0
0
1
1
a
0
a
0
a
a
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
0
a
a
a
a
a
a
a
1
1
1
1
a
a
1
1
1
0
0
0
a
a
a
a
a
a
a
a
a
a
a
a
a
0
0
0
a
0
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
0
0
0
1
1
1
1
1
1
0
a
a
0
0
0
0
0
a
a
0
a
0
0
0
0
1
1
1
1
1
1
0
a
a
a
o
a
a
a
a
0
a
a
a
0
a
a
a
a
a
a
a
a
a
a
a
a
1
a
a
a
1
a a
a 0
0
0
0
0
1
a
o
o
1
1
0
0
0
State
(Note 1)
Bytes
Skip
Condition
B-Bit Arithmetic [Reglsterl(cont]
ADDNC
(A) + (r)
(r) + (A)
(A) - (r)
(r) - (A)
(A) - (r) - (CY)
(r) - (A) - (CY)
(A) - (r)
(r) - (A)
(A) A (r)
(r) A (A)
(A) v (r)
(r) V (A)
(A)-V-(r)
(r)-v-(A)
(r) - 1
(A) - 1
(r)
(A)
(r)
(A)
(r)
EQA
A,r
r,A
A,r
r,A
A,r
r,A
A,r
r,A
A,r
r,A
A,r
r,A
A,r
r,A
A,r
r,A
A,r
r,A
A,r
r,A
A,r
(A) (r) (A) (r) (A) (r) (A) (r) (A) (r) (A) (r) (A) (r) (A) (r) (A) (r) (A) (r) (A) -
aNA
OFFA
r,A
A,r
A,r
(r) - (A)
(A) A (r)
(A) A (r)
SUB
SBB
SUBNB
ANA
ORA
XRA
GTA
LTA
NEA
8-Bit Arithmetic (Memory]
ADDX
rpa
(A) ADCX
ADDNCX
SUBX
SBBX
SUBNBX
ANAX
ORAX
rpa
rpa
rpa
rpa
rpa
rpa
rpa
(A)
+ ((rpa))
(A) - (A) + ((rpa)) + (CY)
(A) - (A) + ((rpa))
(A) - (A) - ((rpa))
(A) - (A) - ((rpa)) - (CY)
(A) - (A) - ((rpa))
(A) - (A) A ((rpa))
(A) - (A) v ((rpa))
a
a
a
a
a
a
o
a
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(J1
I
~
11
RO
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
RO
RO
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
a
1
1 R2 Rl Ro
1 R2 Rl Ro
1 R2 Rl Ro
8
8
8
2
2
2
0
1
0
o
1
1
a
1
a
a
0
0
a
a
1
1
11
2
11
11
11
11
11
11
11
2
2
2
2
2
2
2
1
1
1
1
1
1
A2
A2
A2
A2
A2
A2
A2
A2
Rl
Rl
Rl
Rl
Rl
Rl
Rl
Rl
Rl
Rl
Rl
Rl
Rl
Rl
Rl
Rl
Rl
Rl
Rl
Rl
Rl
AI
AI
AI
AI
AI
AI
AI
AI
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
No carry
No carry
~
o
No borrow
No borrow
No borrow
No borrow
Borrow
Borrow
No zero
No zero
Zero
Zero
No zero
Zero
No carry
't:
'1:11
C
.....
01)
....
~....
(")
~
G)
No borrow
....
~'1:11
....
.r::..
t
'1:
Instruction Set (cont)
I\)
'V
Operation Code
Mnemonic
Operand
Operation
7
~
~
n
M
654
3
2
1
0
0
0
0
o
o
o
o
1·
o
o
o
o
o
o
o
o
o
o
7
C
N
654
3
2
1
0
o
o
o
0, 1
0 A2 A1
0
1
0
1
1 A2A1
0
1
1"
1
1
0 b 0
0 0 0
o
o
0
Ao
Ao
Ao
Ao
Ao
Ao
Ao
State
INote I)
Bytes
Skip
Condltloll
B-BH ArlthmBllc IMamoryllcontl
XRAX
GTAX
LTAX
NEAX
EOA",
ONAX
OFFAX
rpa
rpa
rpa
rpa
rpa
rpa
rpa
(A) - (A)-V-((rpa))
(A) - ((rp<>0".
• , . " • • ,," 0 0 ~. 0 <>", .,'
o ':E~ m~i !!m ~:U
',,,coooo.",,,, • • • • '
'. J' •• ""."O."'.'"
'"."'''
•• 00.',.", •
.".
.0'>00.00."'."
' . n"0"••.. ~·".".""
•
•••••
00 • • ' ' ' 0 ' .
o
0
'.100.,0.000.'Joo.' ••• '
o •••• oo •• ".oo.ooo.co
o
o o ::::: ::::: :m: ':m
•••• 0000.0.00.00.00
o
{lo.ooooo." ••• oooa."o
o
o
• • 000 • • • • • • • • • • • 0 0 0 .
•• 00._0000.0000.000.
000.0 •••• 0.0000.000.
1
nm !!m mi! :ml
0 •• 0000 •• 0
o
o
0000000000.000.0 ••• 0
0000000000 •• 0 •• 000.0
00000 • • • • • • 0.0.000.0
••••• 00000.0.0.000.0
00000 • • • • • • 000.000.0
0000000000.000.000.0
0000000000.000.0 ••• 0
o
•••• ·.00".
eoo."o.coo.cooo.o,'".
o
HlHHHlnmm;;
o •• oc ••••• o ••• o.ooa.
ca.ccOcOO • • COO • • O(J".
1
:::::::::::::::::::::
O Tesl ___ 0.7VOO
0.3 VOO
Points - - - 0.3 VOO
83..()(J2909A
83·003856A
Clock Mtrveform
Interface
RESET
CL
83-002910A
01.02
I.n.~
~IHR03<,-_____
83-002912A
Serial Interface
c/o
BUSY
SCK
SI
LSB
II
)
so
83-0029088
8-29
NEC
pPD7228/28A
Parallel Interface
CID
BUSy----(I
5TB
----------.1
00-D3
DO-D3
83{X)29118
Command Summary
Instruction Code
Mnemonic
Operation
SFF
Set frame frequency
0
0
0
SMM
Set multiplexing mode
0
0
0
DISP OFF
Display off
0
0
DISP ON
Display on
0
LDPI
Load data pointer with immediate
SRM
Set read mode
0
SWM
Set write mode
SORM
SANDM
0
Hex Code
F1
Fo
1
M2
M1
Mo
18H-1FH
0
0
0
0
0
08H
0
0
0
0
0
D6
D5
D4
D3
D2
D1
Do
80H-B1H, COH-F1H
1
1
0
0
0
11
10
60H-63H
0
0
0
11
10
64H-67H
Set OR mode
0
0
11
10
68H-6BH
Set AND mode
0
0
11
10
6CH-6FH
0
1
0
72H
J1
Jo
20H-3FH
Bo
J1
Jo
40H-SFH
1
1
0
0
7CH
0
7DH
0
0
0
01H
Set cha racter mode with left entry
0
0
0
SCMR
Set character mode with right entry
0
0
0
BRESET
Bit reset
0
~
B1
Bo
BSET
Bit set
0
B2
B1
CLCURS
Clear cursor
0
1
WRCURS
Write cursor
0
STOP
Set stop mode
0
0
0
0
0
B2-80
Specifies a data memory bit
D6-DO
Immediate data
F2-FO
Specifies frame frequency as a submultiple of clock
frequency
11-10
Specifies modification of data pointer contents after
byte data is processed
J1-JO
Specifies modification of data pointer contents after
bit is set or reset
M2'"MO
Specifies data memory bank, number of rows, functions
of row/column drivers, and SYNC pin mode
0
OSH
71H
SCML
8-30
10H-14H
F2
0
NEe
Development Tools
9-1
II
NEe
Development Tools
Section 9
Development Tools
4-8il; pPD7500 Series
8-8it; pPD78K2 Series (cont)
EVAKIT-7500B
For the pPD7500 Series
9-3
IE-78210
In-Circuit Emulator
9-51
ASM75
Absolute Assembler for the pPD7500 Series
9-7
IE-78220
In-Circuit Emulator
9-55
CC782XX
C Compiler Package for the pPD782XX
Series
9-59
RA78K2
Relocatable Assembler Package for the
pPD782XX Series
9-63
S178K2
Structured Assembler Preprocessor for the
pPD782XX Series
9-67
4-8it; pPD75000 Series
RA75X
Relocatable Assembler Package for the
pPD75000 Series
S175X
Structured Assembler Preprocessor for the
pPD75000 Series
9-9
9-15
8-8it; pPD7800 Series
DDK-78C10
Evaluation Board for the pPD78CXX Series
9-19
IE-78C11
In-Circuit Emulator
9-23
DDK-78310A
Evaluation Board for the pPD78310A
9-71
CC87
Micro-Series T• C Compiler Package for the
pPD7800 Series
9-27
EB-78320
Evaluation Board for the pPD78320
9-75
9-29
IE-78310A
In-Circuit Emulator
9-79
RA87
Relocatable Assembler Package for the
IlPD7800 Series
IE-78320
In-Circuit Emulator
9-83
CC7831X
C Compiler Package for the pPD7831X/
pPD7831XA Series
9-89
CC7832X
C Compiler Package for the pPD7832X
Series
9-93
RA78K3
Relocatable Assembler Package for the
IlPD7831X/7832X
9-97
8-8it; pPD78K2 Series
DK-78K2
IlPD782XX Designer Kits
9-33
EK-78K2
pPD782XX Evaluation Kits
9-35
IK-78K2
pPD782XX In-Circuit Emulator Kits
9-37
DDB-78K2
Evaluation Boards for the IlPD782XX Series
9-39
EB-78210
Evaluation Board for the pPD78213
9-43
EB-78220
Evaluation Board for the pPD78220
9-47
9-2
8/16-8it; pPD78K3 Series
S178K3
Structured Assembler Preprocessor for the
IlPD783XX Series
9-101
PG-1500 Series
EPROM Programmer
9-105
NEe
EVAKIT-7500B
for the "PD7500 Series
NEG Electronics Inc.
Description
The EVAKIT-7500B is a stand-alone EVAKIT for NEC's
p.PD7500 series of four-bit, single-chip microcomputers.
The EVAKIT-7500B provides complete hardware emulation and software debug capabilities for the p.PD7507
and p.PD7506 microcomputers. With the addition of
device specific add-on boards, the EVAKIT-7500B is
easily tailored to support the remaining members of the
family.
Real-time and single-step emulation capability, together
with a powerful on-board system monitor and real-time
trace capability, create a powerful debug .environment.
The EVAKIT-7500B is controlled either from an on-board
keypad or over a serial line from a terminal or host
computer. User programs are downloaded through a
serial line or read from a PROM. Existing programs can
be modified or small programs can be created using the
on-board hexadecimal keypad.
A host controller program for an IBM PC® series or
compatible computer is provided with each EVAKIT7500B. This program provides the following additional
capabilities: complete EVAKIT-7500B control from the
host console, program upload/download, line assembly,
host system directory display and symbolic debugging.
IBM PC is a registered trademark of International Business Machines
Corporation.
Features
o Real-time and single-step emulation capability
o 8K bytes of user program memory
o Powerful system monitor
- Display/modify/move program memory
- Display/modify data memory
- Load/verify/display PROM
- Examine/modify internal registers
- Full disassembler
o User-specified breakp()int conditions
- Program counter and number of passes
- Stack pointer
- Data address and value
o Real-time trace capability
- 2048 instruction cycle trace
- External trace probes
o Supports three operating modes
- On-board hexadecimal keypad controlled
- External terminal controlled
- Host computer system controlled
o Serial interface: RS-232C or TTL
o EPROM programming capability (2764 and 27128)
o Host Control Software for IBM PC Series or
compatible
EVAKIT-7500B
50196
9-3
NEe
EVAKIT-7500B
EVAKlT-7500B ADD·ON BOARDS
~.
' .
EV7528
EV7508H
The EV7508H is an add-on board for the EVAKIT-7500B
which is required for emulating the ~PD7507Hand the
~PD7508H microcomputers. This board plugs directly
into the ~PD7500 socket on theEVAKIT-7500B, allowing
the system to support thesehigh speed versions afthe
~PD7500 series.
.
EV7514
The EV7528 is an add-on board for the EVAKIT-7500B
required for, emulating the ~PD7527A, ~PD7528A,
~PD7537A,and' ~PD7538A microcomputers. This board
is mounted. under the EVAKIT-7500B, allowing the
EVAKIT tosupport the additional features of these parts:
I/O ports with high dielectric strength, optional pulldown resistors, and zero voltage detection circuits.
EV7533
The EV7533 is an add-on board for the EVAKIJ-7500B
required for emulating the ~PD7533·microcomputer. This
board plugs directly into the ~PD7500 socket, allowing
the EVAKIT to emulate the ~PD7533's four analog inputs
and its 8~bit A/D converter.
EV7554A
The EV7554A is an add-on board for the EVAKIT-7500B
required for emulating the ~PD7554.f54A, ~PD7556/56A,
~PD7564/6~, and ~PD7566/66A microcomputers. This
board mounts 0'; .top of EVAKIT-7500B, allowing the
EVAKIT to emulate the aClditionalfeatures of these parts:
optional pull-up/pull-'dpwn re~i,stors for ports 0, 1, 10,
and '11; cO(T1parator/CMOS inputs for port 1; high
current/CMOS outputsf~r'ports 8, 9, 10, and '11.
The EV7514 is an add-on board for the EVAKIT-7500B
required for emulating the ~PD7502 and ~PD7503 microcomputers. This board is mounted under the EVAKIT7500B, adding LCD controller/driver capability to the
EVAKIT.
9-4
NEe
EVAKIT-7500B
I'PD7500 SERIES SYSTEM
EVALUATION BOARDS
SE-7514A
The SE-7514A is the system evaluation board for the
I4PD7500 series microcomputers with LCD direct drive
capabilities: ItPD7502 and ItPD7503. The SE-7514A is
functionally equivalent to the ROM-based microcomputers. With the user's program housed in either an onboard ItPD2764 or I4PD27128, you can connect the
SE-7514A to your prototype and evaluate total system
performance.
SE-7554A
The SE-7554A is the system evaluation board for the
I4PD7500 series mini/microcomputers: ItPD7554/54A,
I4PD7556/56A, I4PD7564/64A, and ItPD7566/66A. The SE7554A is functionally equivalent to the ROM-based minimicrocomputer. It can be set up to emulate any of the
available mask options. With your program residing in
the lower 4K bytes of an on-board ItPD2754, you can
connect the SE-7554A to your prototype and evaluate
total system performance.
9-5
EVAKIT-7500B
9-6
t\fEC
N"EC
NEC Electronics Inc.
ASM75
Absolute Assembler
for the pPD7500 Series
Description
Ordering Information
The "PD7500 series absolute assembler (ASM75) converts symbolic source code for the enti re "PD7500 series
microcomputer family into executable absolute address
object code. The assembler verifies that each instruction
assembled is valid for the target microcomputer specified at assembly time. An object code file is produced in
ASCII hexadecimal format and may be down loaded to a
PROM programmer or hardware debugger.
Part Number
System
Description
ASM75·D52
MS·DOS
5-1/4" double-density floppy diskette
Features
CJ
CJ
CJ
CJ
CJ
CJ
Absolute address object code output
Macro definition capability
Generic jump with optimization capability
Conditional assembly options
- Up to eight levels of nesting
User-selectable and directable output files
Runs under the MS-DOS@ operating system
MS·DOS Is a registered trademark of Microsoft Corporation.
50191
9-7
ASM75
9-8
NEe
NtEC
NEe Electronics Inc.
RA75X
Relocatable Assembler Package
for the pPD75000 Series
Description
Program Syntax
The RA75X relocatable assembler package converts
symbolic source code for the ~PD75000 series of microcomputers into executable absolute address object
code. The package consists of six separate programs:
assembler (RA75X), linker (LK75X), hexadecimal format
object converter (OC75X), librarian (LB75X), list converter (LCNV75X), and macroprocessor (MP).
An RA75X source module consists of a series of code
and data segments. Each segment consists of statements composed of up to four fields: symbol, mnemonic,
operand, and comment.
RA75X translates a symbolic source module into a relocatable object module. The assembler verifies that each
instruction assembled is valid for the target microcomputer specified at assembly time.
LK75X combines relocatable object modules and absolute load modules and converts them into an absolute
load module. OC75X converts an absolute object modl,I)e or an absolute load module to an ASCII hexadecimal
format object file. LB75X allows commonly used relocatable object modules to be stored in ohe file and linked
into multiple programs, greatly increasing programming
efficiency. When a library file is included as input to the
linker, the linker extracts only those modules required to
resolve external references from the library file and
relocates and links them intothe.absolute load module.
LONV75X allows relocatable list files to be converted
into absolute list files. MP expands macros contained in
a source program prior to assembling.
Features
[J
Absolute address object code output
[J
Generic branch capability and optimization
[J
User-selectable and directable output files
[J
Extensive error reporting
[J
Macro capabilities
[J
Runs under MS-DOS@ and VAX@NMS@ operating
systems
Ordering Information
Part Number
System
Description
RA75X-D52
MS-DOS
5-1/4" double-density floppy diskette
RA75X-WT1
VAANMS
9-track 1600 BPI magnetic tape
MS-DOS is a registered trademark of Microsoft Corporation.
VAA and VMS are registered trademarks of Digital Equipment
Corporation.
IBM PC, PC/XT, and PC/AT are registered trademarks of International
Business Machines Corporation.
50114
The symbol field may contain a label, whose value is the
instruction or data address, or a name, which represents
an instruction address, data address, or a constant. The
mnemonic field may contain an instruction or an assembler directive. The operand field contains the data or
expression for the specified instruction or directive. The
comment field allows explanatory comments to. be
added to a program.
.
Character constants are translated into seven-bit ASCII
codes. Numeric constants may be specified as binary,
octal, decimal, or hexadecimal. Arithmetic expressions
may include the operators +, -, *, /, NOT; AND, OR, XOR,
EO or =, NE or < >, GT or >, GE or > =, LT or <, LE
or < =, SHR, SHL, MOD, .(bit position), the + sign, and
the- sign.
Assembler Directives
Assembler directives give instructions to the assembler.
They are not translated into machine code during assembly. Basic assembler. directives include: storage definition (DB, r:JN, OS, STKLN), symbol definition (EOU, SET),
and program boundary definition (ORG, END). Program
linkage directives are provided to NAME the module and
to declare symbols as PUBLIC or external (EXTRN).
Segment definition directives define whether a segment
is a code segment (CSEG) allocated to ROM, or a data
segment (DSEG) allocated to RAM. The relocation attributes for each segment directive are specified in its
operand. These attributes, which specify how the various segments are to be linked, include INBLOCK,
XBLOCK, SENT, lENT, PAG~, and AT.
I ne Vt:N I n alrectlve aennes me status oT me memory
bank enable flag (MBE), the register bank enable flag
(RBE), and the code entry address for the interrupt
vectors. The TCALL/TBR directives create a table that
allows the CALL and BR instructions to function for the
GETI instruction.
NEe
RA75X
The "PD75000 series instruction set contains three
branch instructions with varying legal address ranges.
To avoid calculating which branch instruction to use,
you can substitute the BR (Branch) directive for any BR
$addr (one-byte branch), BRCB Icaddr (two-byte
branch), or BR laddr (three-byte branch) instruction in
your source program. During assembly, a suitable
branch instruction is chosen for each BR directive.
Figure 1. RA75X Assembler Functional Diagram
Source
Module
File
System
Console
Assembler Controls
The RA75X assembler controls can be specified in a
variety of ways. Depending upon the particular control,
the controls can be specified directly in the assembler
command line, in a parameter file invoked in the command line, at the beginning of the source module, or
anywhere in the source program. The RA75X assembler
controls include the following:
•
•
•
•
•
•
•
Target microcomputer specification
Output file selection and destination
Listing format controls
Date specification
Generation/suppression of listing
Title specification
Inclusion of other source files
On source program only)
• Page eject (in source program only)
The listing file contains the complete assembly listing or
only lines with errors, and a symbol table or cross
reference table. The symbol table shows all defined
symbols in alphabetical order, their types, attributes,
and the values initially assigned to them. The crossreference table contains all defined symbols and the
numbers of all statements that refer to them.
The object file contains the relocatable object module. It
is in aNEC proprietary relocatable object module format.
The object file may also contain local symbol information for the symbolic debugger. Figure 1 is the relocatable
assembler functional diagram.
9-10
Include
File
RA75X
f1I'D75000 Series
Relocatable
Assembler
Relocatable
Object
Module
File
Assembler
List File
49NR-60GA
Linker
The linker combines several relocalable object modules
or absolute load modules, resolving PUBLIC/EXTRN
references between modules, to create an absolute load
module. This load module contains both absolute object
code and symbol information. The linker can search
library files for required modules to resolve external
references.
The linker controls for LK75X can be specified in either
the command line or a parameter file. The programmer
can specify the date, the module name, the stack size
and starting address, an inhibited area in ROM space,
the starting address and order for relocatable code
segments, and whether segments are linked sequentially
as input or randomly in the most effective manner. The
programmer can also specify that a list file containing a
link map, a local symbol table, or a public symbol table
be created. Figure 2 is the linker functional diagram.
tttlEC
RA75X
FIgure 2. UC75X UnIc., Functional 01eg'1IIII
Absolute
Load
Module
Files
Library
Files
FlgUl'll3.
OC75XHe_dec/1IlII1 Fo"na, Object Code
Con"ert., Fullt:tlonal DI."am
Relocatable
Object
Module
Files
I
Relocatable
Object
Module
File"
Absolute
Load
Module
File
I
or
System
Console
~
LK75X
75000 Series Linker
Absolute
Load
Module
File
1+-----+
Temporary
Work Files
!
System
Console
~
Linker
UstFile
OC75X
Hexadecimal Format
Object Converter
Hexadecimal
Object
Code File
Symbol
File for
Debugger
49NR-639A
" Absolute addresses with no external references
49NR-634A
Hexadecimal Format Object Converter
The OC75X object converter outputs the object code file
in ASCII hexadecimal format, which can be downloaded
to a PROM programmer or hardware debugger. The
object converter controls for OC75X can be specified in
the command line or a parameter file. The programmer
can specify whether or not to generate a symbol file for
a hardware debugger and whether the addresses of the
hex code should be sorted in numerical order or left as
ordered in the source program. Figure 3 is the functional
diagram of the hexadecimal format object code conwrter.
LIbrarian
The LB75X librarian creates and maintains library files
containing relocatable object modules. This reduces the
number of files to be linked together by allowing several
modules to be kept in a single file, and provides an easy
wav to link freauentlv used modules into programs.
Modules can be added to or deleted from a library file, or
the contents of the library file can be listed.
LIst Converter
Normally, listing files produced by a relocatable assembler do not show the final absolute address for instructions, because their location is not decided until link
time. The address shown in the listing is only the offset
from the start of the code or data segment.
The LCNV75X list converter uses the assembly list and
object module files from the assembler and the linkers
load module file to· create an absolute address assembly
listing. This absolute listing shows the addresses of
Instructions as their final absolute address in memory. It
Is useful for debugging and documentating the assembled program. The programmer can specify the load
module (-L), assembly list (-A), and output assembly
(-0) file names. Figure 4 is the functional diagram of the
list converter.
9-11
9
NEe
RA75X
Figure 4. LCN75X Ust Converter Functional
Diagram
Figure 5. liP lIacroprocessor Functional Diagram
Operating Environment
The RA75X package can run under a variety of operating
systems. A version is available for an MS-DOS system
with one or more disk drives and at least 128K of system
memory. Another version is available to run on a Digital
Equipment Corporation VAX Computer system under a
VMS (Version 4.1 or later) operating system.
Emulator Controller Program
Macroprocessor
The macroprocessor interprets the macros described in
a source program and expands them to create another
source program. This can be input to the assembler. It
has the following three main functions:
• Expands macros by defining and referencing them
• Reads and expands include files
• Selects assembler source based on a conditional
macro instruction
Figure 5 is the functional diagram of the macroprocessor.
9-12
Absolute hex-format object module files produced by
the RA75X relocatable assembler package can be debugged using an NEC EVAKIT-75X stand-alone emulator.
The EVAKIT-75X controller program EC75X, allows the
programmer to communicate with the . emulator through
an RS-232C serial line. EC75X is available to run on the
IBM PC@, PC/XT@, and PC/AT@ under MS-DOS, and is
included with the MS-DOS version ofthe RA75X package
at no extra charge.
NEe
The EC75X controller program provides the following
features:
• Uploading/downloading of hexadecimal object files
and symbol table
• Symbolic debugging
• Complete emulator control from host console
• On-line help facilities
• Macro command file capabilities
• Host system directory display
• Disk storage of debug session
License Agreement
RA75X
Documentation
For more information on source program formats, assembler operation, and actual program examples NEC
Electronics Inc. provides the following documentation:
• RA75X I-IPD75000 Series Relocatable Assembler
Package, Language Manual (MS-DOS)
• RA75X I-IPD75000 Series Relocatable Assembler
Package, Operation Manual (VMS)
• MP Macroprocessor, User's Manual
This documentation is provided with purchased copies
of the package. Additional copies may be obtained from
NEC Electronics Inc.
RA75X is sold under terms of a license agreement, which
is included with the assembler. The accompanying card
must be completed and returned to NEC Electronics Inc.
to register the license. Software updates are provided
free to registered users.
9-13
RA75X
9-14
NEe
NEe
NEe Electronics Inc.
Description
The ST75X structured assembler preprocessor is a companion program to the RA75X relocatable assembler for
the NEC "PD75000 series of microcomputers. ST75X
converts a source code file containing structured assembly statements into a pure assembly language source file,
which can then be assembled with RA75X.
ST75X
Structured Assembler Preprocessor
for the pPD75000 Series
Structured Assembler PreprocelJllor
Functional Diagram
ST75X converts a structured assembly statement into
one or more "PD75000 assembly language instructions
that perform the desired operation. Since ST75X converts only structured statements and does not convert
"PD75000 assembly language instructions, a structured
source program can include a combination of "PD75000
structured statements and assembly language.
ST75X enables the assembly language programmer to
use some of the structures and syntax of higher-level
languages, such as the C language. This improves program readability and reliability, and increases programmer productivity.
Features
CJ
CJ
CJ
CJ
CJ
CJ
CJ
Control structures for conditions, looping, and
switch-case
Preprocessor directives for conditional code
generation
C-like representation of comparison operations
C-like representation of assignment/arithmetic
operations
Increment and decrement operators
Uses all "PD75000 mnemonics, registers, and
features
Runs under MS-DOS$ and VAX.$NMS$ operating
systems
Ordering Information
The ST75X structured assembler preprocessor is
provided in the follOwing software package at no cost:
RA75X Relocatable Assembler Package for "PD75000
Series Microcomputers.
MS-DOS Is a registered trademark of Microsoft Corporation
VAX and VMS are registered trademarks of Digital Equipment
Corporation.
150115
49NR-638A
A Summary of Structured Language
A line of source code for the ST75X contains either a
structured assembly statement or a "PD75000 assembly
language statement. "PD75000 assembly language
statements (j4PD75000 instructions, RA75X directives,
or RA75X controls) pass through ST75X without change.
Structured assembly statements consist of preprocessor
directives, assignment statements, and control statements. These statements are entered one per line, and
are terminated at the end of aline. An optional comment . . .
may follow a semicolon at the end of the statement; all
text following a semicolon is ignored by ST75)(,
a
Preprocessor directives cause ST75X to include or omit
portions of code. Assignment statements generate one
or more "PD75000 assembly language instructions to
alter the contents of a register· or variable. Control
statements aenerate the necessary instructions to test
conditions and change control flow based on those
conditions.
Preprocessor Directives
ST75X preprocessor direc~ives set and test variables,
allowing conditional processing of code; include external files; and map instructions to "PD75000 GETI table
reference instructions. Table 1 lists the preprocessor
directives and their functions.
9-15
NEe
STt5X
TIIbie 1. PrtIprot:etI8or Dlrecl"",..nd Functions
Directive
Function
#deflne, NAME value
Deflneethe variable NAME, lilt to the
lupplled value.
#IfdefABC
< Itatementl >
#eIae
#endlf
If ABC Is defined ae above, or on the
command line with the -D option, the
flret let of Itatementl Is procll88d
and the 18cond lilt Is Ignoredj If ABC
was net defined, or defined ae zero,
the flret lilt of Itatementals Ignored
and the 18cond lilt II proc888ed.
#Include ''filename"
The named fill Is read from disk and
plOCa8l8d ae If Included In thl source.
#defgetl gatlnaml
< Instructlona >
#Indgatl
Thilistec:llnatructiona are aealgnec:l
to gatlname. When those lnatructlons
are found In the lource, they are
replaced by a "GETI getlnaml"
lnatructlon.
A$Slgnment, Increment, 8nc:1 D$Crement
Statements
8T75X provides the ability to represent an assignment, or
an assignment with an arithmetic operation, In the C
language syntax:
destination source
The assignment operators allow either simple assignment, , or the combination of an assignment with an
arithmetic operation on the source and destination.
Examples:
A ... B;, Move, contents of B register to A
A' + ... @HL ; Add contents of memqry at HL to A,
; store in A
Where an assignment requires an Intermediate register
to hold the value being assigned, the register is deSignated by naming It in parentheses following the assignment operation.
Examples:
,DATA1 ... B (A) ; 8torecontents of B Into memory at
; DATA1, using A as temporary
; storage
BC & ... HL (XA) ; AND BC with HL, store in BC, use
; XAastemp
M/•
.2.
AIIs",nmenl aper.'ortl with &limp_
IIIId nclions
Operator
Example
liunctlon
A-B
A-B
<->
A <-> B
Contents of A and B are exchanged
+-
A += B
A-A+B
A-- B
A-A-B
-&-
A&- B
A - A & B Oogloal AND)
IA
AI- B
AA_ B
A - A I B Oogloal OR)
++
A++
A-A+~
A--
A-A-1
A - A AB Ooglcal XOR)
control Statements
Control statements allow conditions to be tested. Based
on the results of the test, blocks of code can be executed
or Skipped. Reserved words in the control statement
define the start and end of blocks 01 code, and expressions to, be evaluated.
Example:
If (A ...... @HL')
PORTS = B (A)
A ... @HL
else
A += @HL
A- .. B
PORTS ... A
endif
The condition is tested.
If A equals the content of
memory at HL, this code Is
executed.
'
Otherwise, this code is
execut&d.
Table 3 shows the directives used within the control
statements.
TIIbl.3. Conlrol Sf.'emen' D1riN:I"'"
Directive
Function
If - Iiself - 8Ise - endlf
Test variable expressions
IfJllt - elself..bit - else - endlf
Test bit expresSlona
IWItch - caee - default - ends
Select baeec:I on variable
1or- next
Loop, test variable
whlle..,enclw
repeat - until
whlle..blt - endw
~p,testblt
The increment and decrement operatorB-(+ +' and --)
oP$rate on a single operand.
repeat - untlLbIt
break
ExIt control block
Table 2 lists the' assignment operators with examples
and functions.
'
'
continue
Skip to top of, block
goto LABEL
Branch to label
9-16
~EC
ST75X
variable and Bit Expressions
Table 7. Bit Expressions
Variable expressions for tests consist of a single value, a
comparison between two variables, or a logical combi.Il~tion of comparisons. Bit expressions test individual
bits. Table 4 shows examples of comparisons.
Bit Expression
Table 4. Examples of VIIrIBble ExpreSsion
Comparisons
Comparison
Meaning
Example
BILprimary
(PORTO.2)
IBiLprimary
(ICY)
BILprlmary && BiLprlmary
(A.O&&CY)
BiLprlmary II.BiLprimary
( PORTO.2 II Cy)
A BiLprimary can be either a reserved word bit identifier, such as a bit of a register or port (PORTO.1, Cy), or
a bit definition symbol (SBO EQU PORTO.2).
.
If (A).
True If A Is non-zero
If(A C)
Trua if A Is less than B and greater
than C
iLbit ( PORT1.2 )
True if bit 2 of PORT1 is 1
ST75X Operation and Controls
ST75X is invoked by specifying the name of the source
file, followed by optional controls.
The allowable expressions using variables are shown in
table 5.
Example:
C> ST75X ABC.SRC -DXYZ = 3
Table 5. Expressions and Examples
ST75X reads the specified source file and produces an
output assembly language file, which can be input to
RA75X. The output file contains all lines provided in the
input source file, plus those generated by ST75X. Lines
containing no statements for the structured assembler
are passed through unchanged. Lines with structured
assembly statements are placed in the output preceded
by a semicolon. RA75X treats these lines as comments.
These lines are then followed by the code generated by
ST75X.
Expression
Example
Primary
(A)
Term
(A<=B)
Term &&Term
«AC»
Term II Term
«A= =C) II (A= =B»
A primary value for a variable expression is a register
name or defined symbol. A term consists of two primary
values compared with a binary operator. Table 6 lists the
supported binary operators and their meanings.
Table 6. Billllry OperatoTII
Binary Operator
Meaning
Table B. STT5X Preprocessor ControllJ
Equals
1=
Not equal
>
Greater than
->=
Greater than or equal to
<
Less than
< =
Less than or equal to
Cit expretisiulltj Lt:=tjL
i.u.iiviuutli iJiLo u; 1-"'wi~i.i;I-~,
The controls for ST75X are specified in the preprocessor
command line or in a parameter file invoked in the
command line. Table 8 lists the ST75X preprocessor
controls and functions.
tJvi-~~, VI
Control
Function
-Dlilename
Specify name of output assembly source file
-Ffllename
Specify name of parameter file to be read
-EfHename
Specify name of error listing file
-Dsymbol[ =value]
Define symbol Oike #deflne in code)
-I[d:][directory]
Define path for Include file
.. -
~
..... ---
-'''1111,11', ••..,
.... _ ... , _ _ "'JlP"> _ _ ....... , _ _ _ .. _ .. _ _ .... _ .. _ ....................... ....
...................... -... •.... ·a- ._. 0-"-'-"-- ----
memory locations. Table 7 shows the allowable forms of
bit expressions.
9-17
ST75X
The -0 option allows the name of the output file to be
specified. If not specified, the output file name defaults
to the name of the input source file with the extension
.ASM.
The -F option allows a parameter file to be specified,
which will be read by ST75X. This parameter file can
contain a list of controls to be given to ST75X, instead of
or in addition to those specified on the command line.
The -E option specifies the name of the error listing file.
The error file contains the file name, error number,
description of error, and the line containing the error. If
the -E option is not specified, the error file name defaults
to the name of the input source file with the extension
.EST.
9-18
NEe
The -0 control allows a symbol to be defined on the
command line, with an optional value provided. If a
symbol is defined but no value specified, the value
defaults to 1. If the source file contains a #define
directive, which specifies a variable with the same name
as the -0 control, the value on the command line will
override the value in the #define directive.
The -I specifies a drive or directory other than the
current drive and directory to search for include files.
The -wr control specifies the number of TAB characters
to insert before labels, instruction mnemonics, and instruction operands generated by ST75X. This allows
clear separation of assembly language instructions
coded in the source file from those generated by ST75X.
NEe
DDK·78C10
Evaluation Board
for the IIPD78CXX Series
NEe Electronics Inc.
Description
The DDK-7BC10 is an evaluation board for the NEC
IlPD78CXX series of B-bit single-chip microcomputers.
The DDK-7BC10 Is designed to provide maximum flexibility when evaluating and designing with the IlPD7BCXX
series. Prominent features of the DDK-7BC10 are BK
bytes of ROM. BK bytes of RAM. an RS-232C communication port. and a powerful monitor program. The DDK78C10 board Is supplied on an IBM pee compatible card
and includes a playpen area for building your application
specific hardware.
A copy of RAB7. the "PD7800 series relocatable assembler for use on an IBM PC. PCJXT«I. PC A'P. or compatible host computer. is shipped with each DDK-7BC10 to
allow code to be developed for evaluation purposes.
Also included with the DDK-78C10 is an emulator controller program for the IBM PC. the source code for the
monitor. and a complete set of documentation. This total
package provides you with a fast. efficient way of evaluating the capabilities of the IlPD7BCXX series for your
application.
[]
[]
[]
[]
[]
[]
[]
- ROM: BK bytes
- RAM: BK bytes
Powerful on-board debug monitor
- Real-time operation
- Dlsplay/change/filVmove memory
- One software breakpoint
- User program download capability
-Input from ports A, C. andportB (bits 2-7)
- Output to ports A. C. and port B (bits 2-7)
- Repeat the previous command
RS-232C serial interface for terminal or host
computer
Playpen area for user circuitry
IBM PC card form factor
RAB7 "PD7800 series relocatable assembler
package
Host control software for IBM PC. PC/XT, PC/AT,
or compatibles
Source code for DDK-7BC10 monitor included
Ordering Information
Part Number
Deacrlptlon
Features
DDK-78C10
Evaluation board for th~ IIPD78CXX aeries
[] "PD7BCXX series evaluation board with power
supply
[] On-board memory
IBM pc, PCIXT, and pc AT are reglatered trademarks of International
Business Machines Corooratlon.
DDK-78C10 evaluation Board
eo181
NEe
DDK·78C10 ,
Hardware Description
Software Description
The DO K-78C1 0 features a "PD78C10 with 16K bytes of
on·board memory. The first 8K bytes are dedicated to
ROM and contain a powerful monitor program. The
second 8K bytes are dedicated to RAM and can be used
for user program storage. The internal RAM area of the
"PD78C10 (addresses OFFOOH to OFFFFH) is used for
the monitor stack and data area.
The DDK-78C10 comes with a powerful interactive mono
itor to facilitate software design with the "PD78CXX
series. A user program can be downloaded into user
RAM and executed in real·time with or without a break·
point.
The serial port of the "PD78C10 is connected through an
RS-232C driver/receiver to an DB25 pin connector. A
reset switch is provided to return the DDK-78C10 to the
power-up state without losing the contents of the exter·
nal RAM.
The DDK-78C10 supports one address breakpoint that
can be specified in the Go command line. The monitor
sets a breakpoint by substituting a software interrupt
instruction (opcode 72H) for an instruction in the user
program.
Additional commands are available to:
An AC/DC converter is provided to power the DDK-78C10
in the stand·alone mode, The DDK-78C10 can also reo
ceive its power directly from the IBM PC bus.
The DDK-78C10 block diagram is shown below.
•
•
•
•
•
Display, fill, change, or move memory
Display the command list
Input data from ports A, C, and port B (bits 2-7)
Output data to ports A, C, and port B (bits 2-7)
Repeat the previous command
Block Diagram
rPF5-PF7
PFQ-PF4/
PF5-PF7
Address
Decoder
-------v'
Monitor
EPROM
A
-"
v
it
PFQ-PF4
I1PD78C10
POQ-P0 7
PB2-PB7
PB1
~
Address
Buffer
-----"
SRAM
"-
...-
-v
f=>
PBQ
I
TxO
Driver!
Receiver
RxO
J3
r
49NR-580B
9-20
NEe
DDK·78C10
Table 1 contain& a complete list of the DDK-78C10
monitor commands and their syntax.
Table 1. CommandUst
Command
Function
Syntax
C
Change memory byte
C[addr]
D
Display memory
D[saddr][,eaddr]
F
Fill memory
F[saddr],[eaddr],dd
Emulator Controller Program
Absolute address object files produced by the RA87
relocatable assembler package can be downloaded to
the DDK-78C1O using the NEC emulator controller program which is supplied with the DDK-78C1O. This controller program allows you to download files from your
IBM PC or compatible to the DDK-78C10 board. In
addition to downloading files, the NEC emulator controller program provides you the following additional capabilities:
Go (to breakpoint)
G[saddr][,baddr]
Input from port A,C, and
port B (bits 2-7)
I[p]
H
Show this menu of
commands
H
L
Load a HEX file on to the
DDK-78Cl0
L[saddr]
•
•
•
•
M
Move a block of memory
M[saddr][,eaddr][,addr]
License Agreement
0
Output to port A, C, and
port B (bits 2-7)
O[p]
R
Repeats the previous
command
R
G
Notes:
(1) addr
= 16-bit address in hexadecimal format
(2) dd = 8-blt value in hexadecimal format
= 16-bit start address in hexadecimal format
eaddr = 16-bit end address in hexadecimal format
(3) saddr
(4)
Complete DDK-78C1O control from host console
On-line help facilities
Host system directory and file display
Storage of debug session on disk
RA87 is provided under the terms of a license agreement
which is included with the DDK-78C10 board. The accompanying card must be completed and returned to
NEC Electronics Inc. to register the license. Software
updates are provided to registered users.
Documentation
For further information on the DDK-78C10 evaluation
board, NEC Electronics Inc. provides the following
documentation:
(5) p = ports A,B ,C
• DDK-78C10 User's Manual
RA87 Relocatable Assembler Package
The RA87 relocatable assembler package converts symbolic source code for the /-tPD7800 series 8-bit singlechip microcomputers into executable absolute address
object code. A copy of RA87 is included with the DDK78C10 for use on an IBM PC, PC/XT, PC AT, or compatible. Using this software, you can easily write evaluation
programs for the /-tPD78CXX family.
This manual is provided with the board. Additional copies may be obtained from NEC Electronics Inc.
9-21
DDK·78C10
9-22
ttiEC
NEe
IE-78C11
In-Ci rcuit Emulator
NEe Electronics Inc.
Description
The IE-78C11 Is an in-circuit emulator providing both
hardware emulation and software debugging capabilities for the NEC "PD78C10, "PD78C11, "PD78C14, and
"PD78CP14 eight-bit single-chip microcomputers. Realtime and single-step emulation, coupled with sophistIcated memory mapping features, breakpoints and trace
capabilities, create a powerful debugging environment.
A line assembler and disassembler, full register and
memory control, and complete upload/download capabilities simplify the task of debugging hardware and
software. The IE-78C11 Is designed to operate as a
stand-alone, In-circuit emulator controlled from either a
user terminal or a host computer system.
Features
o Real-time and single-step emulation capability
[J User-specified breakpoints
- Logical OR of up to four sets of break conditions:
Opcode fetch count
External sense clips condition
;f:mulatlon" time
logical AND of addresses, data values,
CPU controls, and number of loops
[J Sophisticated trace capabilities
-Instruction or machine cycle display
- 1,024 trace frames
- Address, control. data, and port trace
Powerful memory mapping
- 64K bytes of RAM mappable in 256-byte blocks
[J Une assembler/disassembler
o Operating state LED indicators
[J Latch-up warning for CMOS protection
o Eight external sense probes
[J Self-diagnostic command
[J Stand-alone configuration
- User terminal controlled.
- Host computer system controlled
[J IE78C11 controller program fot IBM PC-. pcncre.
PC ATiI>, or compatibles
- Symbolic debugging
- Autoexecution of commands
- On-line help facility
- Debug session logging
[J
Ordering Information
Part Number
Delcrlptlon
IE-78C11-M
In-clrcult emulator for IlPD78C101C11/C14/CP14
EP-7811HGQ
Emulator probe for 54-pin QUIP package
(shipped with IE-78C11)
EV-8001-54
Optional emulator probe adapter for 54-pin
shrink DIP package (used wHh EP-7811HGQ)
u;lM pc, PCIXT, and pc AT are registered trademarks of international
Buslnese Machines Corporation.
IE-78C11 In-Clrcult Emulator
110182
9-23
II
ttlEC
IE·78C11
Hardware Description
Trace Capabilities
The IE-78C11 hardware consists of a controller module,
driver module, interface probe, external sensing clips,
and the Interconnecting cables. The controller module,
responsible for real-time trace and control of the driver
module, houses the host CPU, two RS-232C serial ports,
and an IEEE-796 bus connection. The driver module
containing the emulatIon chip and associated control
logic is connected to the controller module by two
50-pin flat cables. The driver module Interfaces to the
prototype system through the 64-pln emulation probe
and eight external sensing clips used for monitoring
user-selected signals In the prototype hardware.
The IE-78C11 has a 1K x 56-bit trace RAM for storing
emulation data for each machine C1cIe. For the range
specified by the user, a trace can be performed on the
address, data, and control signals, including RD, WR, OP
and 10/M as well as ports A and B and the signals from
the eight external sense clips, for up to 1,023 machine
cycles. In machine cycle display mode, the trace display
includes the address, data, cycle, port A and port B. In
the Instruction cycle trace mode, the trace display includes the address, object, label, mnemoniC, port A and
port B.
Memory M.pplng
A self-diagnostlc command monitors the IE-7SC11 for
error-free operation. It checks Internal memory. ports A,
B, C, 0, and F, the analog inputs, pins MODEO and
MODE 1, and the serial I/O lines.
The IE-78C11 Incorporates a sophisticated memory
mapping scheme which allows access to up to 64K
bytes of memory mapped In 256-byte units. The map
command allocates memory space of the emulation
CPU either to the user system or to the IE system. Even
if development of the target system is not complete,
software debugging Is possible by using this internal
RAM in place of the target system RAM. When memory Is
mapped as Int8rnal ROM of the IE-78C11, write-protect
becomes oper$tive.
Emulation
Following termination of real-time emulation or during
slngle-step emulation, the registers,. stack pOinter, program staJos word, and program counter are displayed.
Following a real-time emulation break, the IE-7SC11
automatically enters the single-step mode. Each time
the space bar is pressed during slngle-step emulation,
one instruction is executed and the trace data, disassembly list, and the register contents are displayed.
Breakp,olnt Capabilities
The following three conditions cause a break in real-time
emulation:
• Entering the ESC (escape) key on the user terminal
• Attempting l;Iocess to a non-mapped area
• Satisfying a user-designated breakpoint
Four uSer-designated breakpoints may be selected from
a cqmblnatlon of address registers, data registers, or
control signals. A break can also be set 111 the following
ways: by a loop counter, by an Instruption count, by a
timer function set In the range of 1 to 65,535 ms, and by
matching user-speclfied condiJions for the eIght external sense!llg,nals.
'
9-24
Self-Diagnostics
Utilities
The upload/download commands provide easy loading
and saving of hex files to and from a disk. The on-board
assembler/disassembler allows the user to avoid programming In machine code. Display/change register/
memory commands give the user full data manipulation
capability. Initialize commands allow the user to choose
a clock source and a base number, and to define memory
locations.
Operating States and CMOS Protection
Four LED indicators HALT, SO FT STOP, HARD STOP,
and LATCH-UP are provided on the top panel of the driver
module to Indicl!,te the IE-7SC11 operating state. HALT,
and SO FT STOP will light when executing a HLT or
STOP Instruction. The HARD STOP LED lights when a
low level is Input on the STQP pin. The LATCH-UP LED
lights when any CMOS ICin the driver module is in
danger of being dam"ged by improper voltage levels on
the pins. A protection c1rcul~ is'activated to isolate the
CMOS 19s from the power supply.
t-IEC
Emulation Accuracy
Software can designate ports 0 and F as either input or
output ports if they are being used to communicate with
a peripheral device with a bidirectional data bus. However, when using the IE·78C11, the user must specify the
port direction upon power-up, and only use the port in
that configuration. The low level output voltage of RD,
WA, ALE, PDo·per, or PFo·PF7 for the p.PD78C1On8C11/
78C14 is typically .45 V. Depending on the conditions,
the emulator may deviate up to ± 10% of this rating.
IE·78C11
Table 1. Stand-Alone and IBII PC Based
Controller Progrlllll (conf)
Command
Function
RUN
Commencee execution of emulator CPU In realtime with options for break conditions
SN
Saves contents of hex memory onto disk
SPR
Displays or modlflee the speclsl registers of
emulator CPU
SUF
Base number specification (hax, octal,
declmaQ
TR?
Changes or displays the trsce conditions for both
real-time or slngle-etep emulation
IE78C11 Controller Program
The IE·78C11 can be connected to an IBM PC, PCIXT, PC
AT or compatible by an RS·232C port and operated in
system mode. By using the accompanying control soft·
ware, the debugging capabilities of the IE·78C11 are
greatly increased. Macro command file capability allows
the user to execute a defined set of commands automat·
ically. The on·line help facility, the history command, and
the ability to store the console display on disk ease
debugging tasks. The uploading and downloading capa·
bility can be utilized to upload and download both object
code and symbol information. Other advantages are an
alter symbol command and a terminate command for
exiting to the operating system.
Table 1 lists commands available for both the stand·
alone and IBM PC controlled configurations of the IE·
78C11. Commands listed in table 2 supplement table 1,
but can be used only with the IBM PC based controller
program, IE78C11.
Tabl.,. Stand-Alone and IBII PC Based
Controller Program
Command
Function
ASM
line assemble command
BR?
Changee or displays the breakpoint register used
for stopping real·tlme emulation
ClK
Clock command Onternal or externaQ
DAS
Disassemble command
DIG
Self·dlagnostlc command
----
lOD
loads hex format file Into program memory
MAP
Memory mapping (64K bytee are accessible)
MAT
Calculator function
MDR
Displays or modlflee the mode registers of emulator
CPU
MEM
Memory manipulation command
MOV
Moves memory content to different mapping area
REG
Displays or modlllee the registers of emulator CPU
RES
Resets IE·76C11 and emulator CPU
blna~
Table 2. 1811 PC Ba..d Controller Program
Command
Function
DIR
Displays fllenamee
EXT
Termlnatee IE·78C11 operation
HLP
Displays command format
lCD
Loads hex format and symbol fllee
LST
Storee console display on disk
MOD
Inputs local symbols of specified modulee
PAG
Displays and changes V register value
SAY
Saves object code and symbol table onto disk
STR
Automatically executes macro command file
SYM
Clears, displays, or changes a symbol
Equipment Supplied
The IE·78C11·M package consists of the following:
• IE·78C11 controller module
• IE78C11 controller program QBM PC based)
• IE·78C11 driver module with 64·pin QUIP emulation
probe and eight external sense probes
• Power supply connector
• Serial commUnication cable for RS·232C to RS·232C
• Serial communication cable for TTL to RS·232C
• IE·78C11 user's manual
... ~~~~~~ff~ ~~~ ",~ .. nt:>l ..t ..rI h.",IwAI'A
• warranty policy and registration card
9-25
II
NEe
IE·78C11
Basic Specifications
Documentation
Control module:
For further information on IE-78C11 operation, NEC
Electronics Inc. provides the in-circuit emulator together
with the following manuals:
• Weight: 560 g
• External dimensions: length, 230 mm; width, 305 mm
• Power consumption: 6.5 A ( + 5 V max), 0.5 A
(+ 12 V max), 0.5 A (-12 V max)
Driver module:
• Weight: 2,600 g
• External dimensions: length, 400 mm; width, 230 mm;
height, 48 mm
Environmental Characteristics
• Operating temperature range: 0 to +45°C
• Storage temperature range: -10 to +55°C
• Ambient humidity range: 30 to 85% relative humidity
9-26
• IE-78C11-M In-Circuit Emulator Stand-Alone
Users Manual
• IE78XX Controller Program User's Manual
(IBM PC Based)
• IE-78C11 Sample Session User's Manual
(IBM PC Based)
Additional copies may be obtained from NEC
Electronics Inc.
CC87
Micro-Series TM
C Complier Package
for the pPD7800 Series
t-IEC
NEe Electronics Inc.
Description
[J
The CC87 Micro-Series'" C complier package for the
NEC /LPD7800 series of microcomputers consists of an
ANSI C cross compiler, relocatable macro assembler,
linker, library manager, loader, and converter. Developed
by IAR systems In Sweden for NEC, the Micro-Series C
compiler package Is available for use on an MS-DOSe,
VAXNMse, or VAX/UNIX"'4.2BSD or ULTRlxe system
with a free-standing system as target (embedded system). The target microcomputers supported by this
package are: /LPD7807/09, /LPD7810/10H, /LPD7811/11H,
/LPD78PG11/PG11 H, and the /LPD78C10/C11/C14.
Ordering Information
Part Number
System
Description
CCMSD·15DD·87
MS·DOS
5-1/4" doubl.denalty
floppy diskette
CCVMS·OT16-87
VAXJVMS
9·track 1600 BPI
magnetlo tape
CCUNX·OT16-87
VAXNNIX4.2BSD
orULTRIX
9-track 1600 BPI
magnetic tape
C CROSS COMPILER (ICC7800)
Description
The C cross compiler which is the ICC7800 program,
converts standard C source code Into relocatable object
modules in the IAR systems proprietary universal binary
relocatable object format (UBRO F). This format is used
for all relocatable object files in the micro series development system, whether generated by an assembler or
compiler.
Features
[J
ANSI standard C
- Const, volatile, signed, void, enum keywords
- Function prototyping
- Hex strinaconstants
- Structure and union assignments
Micro-5erles Is a trademark of 1M Systems AB.
MS·DOS Is a registered trademark of Microsoft Corporation.
V/IIX. and VMS are registered trademarks of Digital equipment
Corporation.
UNIX Is a trademark of AT&T.
ULTRIX Is a registered trademark of Digital Equipment Corporation.
150194
[J
[J
[J
[J
[J
UNIX LINT functions Oegal C code verification}
Integrated into the compiler
Interface checking between modules performed by
the linker XLiNK
Ubrary interface checking
Generation of list and full cross reference files
Built In help facility
Simple diagnostics
C LIbrary Functions
The CC87 Micro-Series C compiler package includes
most of the important C library functions that apply to
PROM-based embedded systems. All library functions
reside in the supplied library files. Header files that
declare the set of library functions are also Included.
The following library functions are available:
CHARACTER HANDLING
isalnum isalpha iscntrl Isdigit islower
isprint ispunct
isspace isupper tolower toupper
NON·LOGICAL JUMPS < setjmp.h >
longjmp setjmp
FORMATTED INPUT/OUTPUT < stdio.h >
getchar printf putchar sprintf Jormatted_write
n.
GENERAL UTILITIES
calloc exit free malloc ralloc
_
STRING HANDLING < string.h >
strcat strcmp strcpy strlen strncat strncmp strncpy
MATHEMATICS
atan atan2 cos exp log log10 modf pow sin sqrt tan
Memory Models
:!":::~ !!~~ !'..a-,~ ~~~~~~' mnrtAII!l. RtAti~ And 1'A9ntrant.
which differ only in allocation of auto variables. In the
reentrant mode, all local auto variables are allocated and
deallocated dynamically; the auto variables reside on
the stack, which is necessary If recursive or reentrant
functions are needed. This option sometimes generates
more code and slower code than the static mode. In the
static mode, all function level variables are put Into static
memory, with the exception of function arguments which
are always placed on the stack.
9-27
N'EO
cel7
RELOCATABLE MACRO ASSEMBLER (A7800)
Description
The relocatable rnacro~ssembler(A7800), translates
symbolic source code for the NEC "PD7800ser/es of
microcompute~ l~oreloca~le.obj~ct modules i".the
IAR systems proprietary UBRO F format. .. '
.,
Features
LOADER (RC7800) AND
CONVERTER (CONVERn
Linker output is usually fed to the target system RAMI
PROM or emulator using the RC7800 loader or other user
program. Prevlou$ly written assembler programs, coded
by theNEC "PD1aoo ..famlly assembler, maybe converted to the. A7800 assembler format using the CON~
VERT program. .'
..
The relocatable macro assemblerfeatures anJasfollows:
LIBRARIAN (XLIS)
Absolute or relocatable address object cOde output
Directives
- List formatting
.
- Conditional assembly, separate assembly
- Memory allocatlOf!
....;. Macro definition and value assignments to
symbol directives
o Generation of list files
C Generation of cross reference and symbol tables
C Ability to include files In anOther source .'
The XLIB librarian creates and maintains files containing
relocatable object 'modules. WithXLlB; the user can'
merge. object .' files· from different assemblieS!
compilations in order to create libraries; delete individual
modules, change the order of modules and check the
CRC In a module; and rename modules, segments,
externals or entrieS..In addition, XLIB.· can change the
properties of a module to be conditionally or uncondItionally loaded. Use of XLIB reduces. the number Of files
that need·. to be linked together by allowing several
modules to be kept In a single file,. providing an easy way
to link freql,lently used modules into programs.
C
C
Directives
LICENSE AGREEMENT
Assembler directives give Instructions. to the program
but are not translated into machihe code during assembly. Basic directives Include those fOr storage definition
and memory allocation (DB, DD, ~ OS); symbol control and usability (pUBLIC, EXTERN, LOCSYM); and
value assignments to symbols (SET, EQU, =, DEFINE).
CC87 Micro-Series C Cor;npiler package Is sold .lJnder
terms of a license agreement. which Is Included with the
purchased copies of the complier: The accompanying
card must be completed and sent to NEC Electronics
Inc. to register the license. Software updates are provided free to registered users.
Program control directi~s .Include those for module
definition (NAME, MODULE, ENDMOD); segmemdefinition and control (ASEG, RSEG, STACK, COMMON,
ORG); conditional assemblyQF. 'ELSE, ENDIF); macro
processing (MACRO, ENDMAC); and listings control
(LSTOUT, LSTCND, LSTCOD, LSTEXP, .L.STMAC,
LSlWIO, LSTFOR, LSTPAG, PAGSIZ, PAGE,TITL, STITL,
PTITL, PSTITL, LSTXRF).··
.
.
For further information on source program format, complier operation, assembler operation, linker, librarian, and
converter programs, and actual program examples, NEC
Electronics Inc. provides the following documentation:
LINKER (XLINK)
The universal linker, XLiN K, combines reloc~table object
modules arid absolute load mOdules and produces one
absoluteIOad ..rOOdule. The contro.ls for XLlNK may b8
specified either on the comman!1line or In a ~rameter
file. ,In addition to, being able to generate several types of
absolute lo8d. module formats, ins also possible to
generate cross reference listS with an Index list; define
segment allocation; fOrce load and conditional load "Of
flies; bank segments; and' define a' Symbol on a command line. The absolute load module can contain symbol infOrmation as well as absolute object code.
,
'.
DOCUMENTATION
• Micro-8eries AN SI C Cross Compiler fOr
Microprocessor Development
• ICC7800 Micro-8eries ANSI XCross-Compiler '
Appendix for the 7800 Microprocessor Family
• Micro-8erles Assemblers, '. Linker, and Librarian for
Microprocessor Development
• A7800 Micro-Series 7800 Family Assembler Reference
Manual
• Mlcro-8eries RC7800 and Converter Manual
This documentation is provided with. purchased copies
of theMlcro-8eries C Complier package.
NEe
NEe Electronics Inc.
RA87
Relocatable Assembler Package
for the I'PD7800 Series
Description
Ordering Information
The RA87 relocatable assembler package converts symbolic source code for the "PD7800 series of microcomputers into' executable absolute address object code.
The "PD7800 series relocatable assembler package consists of six separate programs: assembler (RA87), linker
(LK87) , hexadecimal format object converter (OC87) ,
librarian (LB87), list converter (LCNV87), and macroprocessor (MP).
Part Number System
Description
RA87-D52
MS-DOS
5-1/4 Inch double-density floppy diskette
RA87-WT1
VJ(XfVMS 9-track 1600 BPI magnetic tape
RA87 translates a symbolic source module into a relo-,
catable object module. The assembler verifies that each
instruction assembled is valid for the target microcomputer specified at assembly time.
LK87 combines relocatable object modules and absolute
load modules and converts them into an absolute load
module. OC87 converts an absolute object module or an
absolute load module into an ASCII hexadecimal format
object file.
LB87 allows commonly used relocatable object modules
to be stored in one file and linked into multiple programs,
greatly increasing programming effiCiency. When a library file is included in the input to the linker, the linker
extracts only those modules required to resolve external
references from the file and relocates and links them into
the 'absolute load module.
LCNV87 allows relocatable list files to be converted into
absolute list files. MP expands macros contained in a
source program prior to assembling.
Features
o
o
o
o
o
o
Absolute address object code output
Generic jump capability
User-selectable and directable output files
Extensive error reporting
Macro Capabilities
Runs under MS-DOSIB> and VAXIjJ)/VM~1jJ) operatmg
systems
MS-DOS Is a registered trademark of Microsoft Corporation.
VJ(X and VMS are registered trademarks of Digital Equipment
Corporation.
Program Syntax
An RA87 source module consists of a series of code,
byte-oriented data, or bit-oriented data segments. Each
segment consists of statements composed of up to four
fields: symbol, mnemonic, operand, comment.
The symbol field may contain a label whose value is the
instruction or data address or a name which represents
an instruction address, data address or a constant. The
mnemonic field may contain an instruction or an assembler directive. The operand field contains the data or
expression for the specified insti'uctionor directive. The
comment field allows explanatory comments to be
added to a program.
Character constants are translated into seven-bit ASCII
codes. Numeric constants may be specified as binary,
octal, decimal, or hexadecimal. Arithmetic expressions
may include the operators +, -, *,/, NOT, AND, OR, XOR,
EO, NE, GT, GE, LT, LE, SHR, SHL, HIGH byte, LOW byte,
MOD, and the - sign.
Assembler Directives
Assembler directives give instructions to the assembler
but are not translated into machine code during assembly. Basic assembler directives include: storage definition (DB, r::JN, DS, DBIT); symbol definition (EOU, SET,
CODE, DATA, BIT); and program boundary definition
(ORG, END). Program linkage directives are provided to
NAME the module and to declare symbols as PUBLIC or
external (EXTRN).
Segment definition directives define whether a segment
is a code segment (CSEG), allocated to ROM; a data
segment (DSEG) or a bit segment (BSEG), allocated to
RAM; or a working register segment (VREG). The address boundary conditions for each segment directive
are specified in its operand. These include UNIT, PAGE,
INPAGE, FIXEDAREA, BYTE, CALLTABLE, AT, BITADDRESSABLE. The combination types of PUBLIC, COMMON and COMPLETE, specified in the operand, define
how to link segments with the same name and segment
definition.
9-29
..
_
ttlEC
RA87
The ~PD7800 series instruction set contains three jump
instructions with varying legal address ranges. To avoid
calculating which jump instruction to use, the programmer can substitute the generic jump (GJMP) directive for
any relative jump (JR), any extended relative jump (JRE),
or any long jump (JMP) instruction in the source program. During assembly a suitable jump instruction is
chosen for eachGJMP directive.
Assembler Controls
The RA87 assembler (figure 1) has two types of controls.
The primary controls, which are specified in the assembler command line, a parameter file, or at the beginning
of the source module, are as follows:
•
•
•
•
Target microcomputer specification
Output file selection and destination
Listing format controls
Date specification
The general controls, specified in the assembler command line, a parameter file, or at any place in the source
program, are as follows:
• Generation/suppression of listing
• Listing titles
• Inclusion of other source files
(in source program only)
• Page eject (in source program only)
The listing file may contain the complete assembly
listing or only lines with errors, and a symbol table or a
cross reference table. The symbol table shows all defined
symbols in alphabetical order, their types, attributes,
and the values initially assigned to them. The crossreference table. contains all defined symbols and the
numbers of all statements that refer to them.
The object file contains the relocatable object module.
The format of this module is a NEC proprietary relocatable object module format. This object file may also
contain local symbol information for the symbolic debugger.
9-.30
Figure 1. Relocatable Assembler Functional
Diagram
Source
Module
File
Include
File
~
System
Console
~
RA87
7800 Series
Relocatable
Assembler
foE-+
foE-+
~
~
Relocatable
Object
Module
File
Assembler
list File
Temporary
Work Files
49NR-629A
Linker
The LK87 linker (figure 2) combines several relocatable
object modules or absolute load modules, resolving
PUBLIC/EXTRN references between modules, to create
an absolute load module. This load module contains
both absolute object code and symbol information. The
linker will also search library files for required modules to
resolve external references. The linker controls for LK87
can be specified in either the command line or in a
parameter file. The programmer can specify the date,
module name, stack size and starting address, ROM/
RAM segment allocation, starting address and order for
code/data/bit relocatable segments, and the page address for the working register group. The programmer
may also specify that a list file containing a link map, a
local symbol table, or a public symbol table be created.
NEe
RAa7
Librarian
Figure 2. Unker Functiolllll DI.am
Absolute
Load
Module
File 1
...
Absolute
Load
Module
Filen
Relocalable
Object
Module
File 1
...
Relocatable
Object
Module
Fllen
I
I
The LB87 librarian creates and maintains library files
containing relocatable object modules. This reduces the
number of files to be linked together by allowing several
modules to be stored in a single file. This provides an
easy way to link frequently used modules into programs.
Modules can be added to, deleted from, or the contents
of the library file can be listed.
List Converter
System
Console
I--
LK87
7800 Series Linker
Absolute
Load
Module
File
~
Temporary
Work Files
Linkar
List File
.t9NR-63CIA
Hexadecimal Format Object Converter
The OC 87 object converter (figure 3) outputs the object
code file in ASCII hexadecimal format, which can be
downloaded to a prom programmer or hardware debug'ger. The programmer can specify whether or not to
generate a symbol file for a hardware debugger.
Normally, listing files produced by a relocatable assembler do not show the final absolute address for instructions, as their location is not decided until link time. The
address shown in the listing is only the offset from the
start of the code or data segment.
The LCNV87 list converter (figure 4) uses the assembly
list and object module files from the assembler and the
load module file from the linker, to create an absolute
address assembly listing. This absolute listing shows the
addresses of instructions as their final absolute address
in memory, and is useful in debugging or program
documentation. The programmer can specify the load
module (-L), assembly list (-A), and output assembly (-0)
file names.
Figure 4. Ust Converter Functional DIagram
Figure 3. Hexadecimal Format Object Code
Converter Functiolllll DilJfll'am
Relocatable
Object
Module
File"
I
System
Console
--
Absolute
Load
Module
File
or
J
I
OC87
Hexadecimal Format
Object Converter
Hexadecimal
Object
Code File
Symbol
Ale for
Debugger
" Absolute addresses wilh no external references
49NA-631A
9-31
NEe
RA87
Macroprocessor
The MP macroprocessor (figure 5) interprets the macros
described in a source program and expands them to
create another source program, which can then be input
to the assembler. It has the following three main functions:
• Expands macros by defining and referencing them
• Reads and expands include files
• Selects an assembler source based on a conditional
macro instruction
Figure 6. Macroprocessor Functional Diagram
These emulator controller programs provides the following features:
•
•
•
•
•
•
•
Uploading and downloading of object and symbol files
Symbolic debugging
Complete emulator control from host console
On-line help facilities
Macro command file capabilities
Host system directory and file display
Disk storage of debug session
License Agreement
RA87 is sold under terms of a license agreement which is
included with the assembler. The accompanying card
must be completed and returned to NEC Electronics Inc.
to register the license. Software updates are provided
free to registered users.
Documentation
For further information on source program formats,
assembler operation, and actual program examples,
NEC Electronics Inc. provides the following documentation:
• RA87 I4PD?800 Series Relocatable Assembler
Paokage User's Manual
• MP Macroprocessor User's Manual
49NR-633A
This dooumentation is provided with purchased copies
of the package. Additional copies may be obtained from
NEC Electronics Inc.
Operating Environment
The NEC RA87 package can run under a variety of
operating systems. A version is available to run on a
MS-DOS system with one or more disk drives and at
least 128K of system memory. Another version is available to run on a Digital Equipment Corporation VAX
computer under the VMS (Version 4.1 or later) operating
system.
Emulator Controller Program
Absolute object files produced by the RA8? relocatable
assembler package can be debugged using the appropriate NEC stand-alone in-circuit emulator. NEC emulator controller programs allow communication with the
emulator through an RS-232C serial line. An emulator
controller program can run on the IBM PC@, PCIXT@,
and PC/AT@ under MS-DOS and is provided with the
in-circuit emulator at no extra charge.
9-32
IBM PC, PC/XT, and PC/AT are registered trademarks of International
Business Machines Corporation.
t-IEC
NEe Electronics Inc.
DK·78K2
pPD782XX Des Igner Kits
Description
Features
The DK-78K2 designer kits are powerful development
toolboxes for the 78K2 family of eight-bit microcomputers. Each kit Includes all the hardware and software to
design and implement elaborate embedded control applications for the "PD7821 X, "PD7822X, or "PD7823X. To
enhance the development process, each kit includes
NEe's new ST78K2 structured assembler preprocessor,
which provides high-level language constructs without
code inefficiency.
o
o
o
o
o
The DK-78K2 features an EB-782XX emulation board with
either a "PD78213, "PD78220, or "PD78230 microcomputer, probe connector, on-board monitor, and serial
interface for an IBM P~, PC/XT~, PC/AT~, or compatible computer. The EB-782XX emulation board can be
used without a target system or can be directly connected to a user's system with the enclosed emulation
probe.
o
The on-board monitor facilitates access to RAM, ROM,
I/O, and special function registers in a real-time environment. Programs can be downloaded to the on-board 32K
byte memory for evaluation and debugging. A line assembler and disassembler provide easy code debugging
and modification. An NEC emulator controller program
on disk makes it possible to download code from an IBM
PC and provides complete control of the EB-782XX from
the console of the PC.
o
o
o
EB-782XX emulation board
32K bytes of static RAM
Resident monitor
Emulation probe
Power supply
RA78K2 relocatable assembler package
ST78K2 structured assembler preprocessor
Emulator controller program for IBM PC, PC/XT, PC
AT, or compatibles
Full documentation package
Ordering Information
Part Number
Deacrlptlon
DK-78K2-21XCW
"PD7821X designer kit for shrink DIP package
DK-78K2-21XGJ
"PD7821X designer kit for QFP package
DK-78K2-21XGQ
"PD7821X designer kit for QUIP package
DK-78K2-21XL
"PD7821X designer kit for PLCC package
DK-78K2-22XGJ
"PD7822X designer kit for QFP package
DK-78K2-22XL
"PD7822X designer kit for PLCC package
DK-78K2-2SXGC
"PD7823X designer kit for 80-pln QFP package
DK-78K2-23XGJ
"PD7823X designer kit for 94-pln QFP package
DK-78K2-23XL
"PD7823X designer kit for PLC C package
The kit includes both the RA78K2 relocatable assembler
package and the ST78K2 structured assembler preprocessor for software development. Source modules consist of a combination of structured and pure assembly
language which reduces development time and effort. A
complete set of documentation is provided for the EB782XX, its two software packages, the target "PD782XX
microcomputer, and other NEC support products for the
78K2family.
IBM PC, PC/XT, and PC AT are registered trademarks of International
Business Machines Corporation.
9-33
DK·78K2
9-34
NEe
1ttlEC
NEe Electronics Inc.
EK·78K2
pPD782XX Evaluation Kits
Description
Features
The EK-78K2 are powerful evaluation kits for the 78K2
family of eight-bit microcomputers. The EK-78K2 allows
full evaluation of the "PD7821 X, "PD7822X, or "PD7823X
in either a stand-alone or an application environment.
Each kit Includes all of the tools to write and test
application software, and to experiment with the 78K2
hardware. Also included for user evaluation Is a copy of
NEC's new S178K2 structured assembler preprocessor,
which provides high-level language constructs without
code ineffiency.
The EK-78K2 features a DDB-78K2 evaluation board with
either the "PD78213, "PD78220, or "PD78233 microcomputer and a serial Interface that will convert an IBM
P~, PC,ocre, PC AT4D, or compatible into a 78K2 design
center. The on-board monitor facilitates the hex object
code downloading from a PC to the resident RAM on the
DDB board, where It then can be executed In real-time.
An NEC emulator controller program on disk allows c;ode
to be downloaded from an IBM PC and provides complete control of the DDB-78K2 from the PC console.
The kit Includes both the RA78K2 relocatable assembler
package and the S178K2 structured assembler preprocessor for writing evaluation programs. A complete set
of documentation Is provided for the DDB-78K2, Its two
software packages, the target "PD782XX microcomputer, and other NEC support products for the 78K2
family.
...... ........ ....."AI .. __ .................. ______1_&_..._ .................... _ _ .. 1......
~
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
DDB-78K2-2XX evaluation board
32K bytes of static RAM
Resident monitor ROM
Expansion ROM socket for extended data memory
Nine square Inches of user prototype area
Power supply
RA78K2 relocatable assembler package
ST78K2 structured assembler preprocessor
Emulator controller program for IBM PC, PC/xT. PC
AT, or compatibles
Full documentation package
Ordering Information
PlII'tNumber
Description
EK-78K2·21X
"PD7821X evaluation kit OBM PC Based)
EK·78K2·22X
"PD7822X evaluation kit OBM PC Based)
EK·78K2-23X
"PD7823X evaluation kit OBM PC Based)
1.......6 ......... : ........... 1
IWI.,. I _, """'''''1 ""•• _ "_ .... _._ ._.'_ .. _. __ •• __ ••• _ •.• __ ....• _ ... __ ._ .. __ _
Business Machines Corporation.
9-35
EK·78K2
9-36
NEe
NEe
IK-78K2
IIPD782XX In-Circuit Emulator Kits
NEe Electronics Inc.
Description
The IK-78K2 in-circuit emulator kits are the ultimate
debugging tools for the 78K2 family of eight-bit microcomputers. Each kit includes all of the hardware and
software to design and implement elaborate embedded
control applications for the I'PD7821X, I'PD7822X, or
I'PD7823X. To enhance the user's.development process,
each kit includes NEC's new ST78K2 structured assembler preprocessor, which provides high-level language
constructs without code inefficiency.
The IK-78K2 features an IE-782XX in-circuit emulator and
emulator probe. The IE-782XX can be used without a
target system or can be connected directly to a user's
system with an enclosed emulator probe. This full feature
emulator for the I'PD7821X, I'PD7822)(. or I'PD7823X
microcomputers provides upload/download capabilities
from an IBM PC\!), PC/XT\!), PC AT\!) or compatible computer using the NEC emulator controller program on
disk. This controller program allows the in-circuit emulator (IE) to be controlled directly from a PC console and
enhances the IE with an added HELP facility, STRING
command file capability, and HISTORY command.
Real-time and single-step emulation capability together
with extremely sophisticated breakpoint and trace capabilities create a powerful, real-time debugging environment. All memory can be written to or read from,
displayed using the disassembler, altered by the line
assembler and traced without restrictions. All special
function registers can also be displayed and altered. Up
to 32K bytes of internal high-speed memory can be
mapped for internal ROM emulation.
Features
Cl
Cl
Cl
Cl
Cl
Cl
IE-782XX in-circuit emulator
Emulation probe
RA78K2 relocatable assembler package
ST78K2 structured assembler preprocessor
Emulator controller program for IBM PC, PC/XT, PC
AT, or compatibles
Full documentation package
Ordering Information
Part Number
Description
IK-78K2-21XCW
"PD7821X In-clrcult emulator kit for shrink DIP
package
IK-78K2-21XGJ
"PD7821X In-clrcult emulator kit for QFP
package
IK-78K2-21XGQ
"PD7821X In-clrcuit emulator kit for QUIP
package
IK-78K2-21XL
"PD7821X In-circult emulator kit for PLCC
package
IK-78K2-22XGJ
"PD7822X In-clrcult emulator kit for QFP
package
IK-78K2-22XL
"PD7822X In-circult emulator kit for PLCC
package
IK-78K2-23XGC
"PD7823X In-circult emulator kit for 80-pin QFP
package
IK-78K2-23XGJ
"PD7823X In-clrcult emulator kit for 94-pln QFP
package
IK-78K2-23XL
"PD7823X In-clrcuit emulator kit for PLCC
package
The kit includes both the RA78K2 relocatable assembler
package and the ST78K2 structured assembler preprocessor for software development. Source modules can
consist of a combination of structured and pure assembly language which greatly reduces development time
and effort. A complete set of documentation is provided
fnr tn .. IF-7A?XX, it!: two !:oftware oackaaes. the taraet
/AoPD782XX microcomputer, and other NEC support products for the 78K2 family.
IBM PC, PCiXT. and PC AT are registered trademarks of International
Business Machines Corporation.
9-37
m
IK·78K2
9-38
NEe
t-IEC
NEG Electronics Inc.
Description
The DDB-78K2 are evaluation boards for the NEC
/-IPD782XX eight-bit, single-chip microcomputers. The
DDB-78K2 provides maximum flexibility when evaluating
and designing with the /-IPD782XX family of microcomputers. Every DDB-78K2 features a /-IPD78213, /-IPD78220
or /-IPD78233 microcomputer, 32K bytes of ROM, 32K
bytes of RAM, /-IPD27C512 footprint for 64K bytes of
optional extended data memory, RS-232C communication port, and a powerful monitor program. A playpen
area is included for evaluating the /-IPD782XX with application specific hardware.
DDB·78K2
Evaluation Boards
for the IlPD782XX Series
o /-IPD27C512 footprint for 64K bytes of extended data
memory
o Powerful on-board debug monitor
- Real-time and single-step operation
- Display/change memory and internal registers
- Multiple software breakpoints
- User program download capability
o RS-232C serial interface for terminal or host
computer
o Playpen area for user circuitry
o Includes AC/DC converter
Features
Ordering Information
o /-IPD78213, /-IPD78220, or /-IPD78233 evaluation
board
- Convertible by changing microcomputer and
firmware
The DDB-78K2 evaluation boards are sold only as part of
the following:
• EK-78K2 evaluation kits
o On-board memory
- ROM: 32K bytes
- RAM: 32K bytes
DDB-7BK2 Evaluation Board
50267
9-39
NEe
DDB·7aK2
.
.
DDB·78K2 Block Diagram
Hqh
ADo-AD7
RS-232C
Connector
I--
RS-232C
Interface
Lr
SIO
Socket to Socket
Connections
J1I'D78213
68-PinPLCC
Socket
I
1
Monitor
EPROM
0-7FFF
Address Latch
AO-A7
A15-A19
27C512
I
A8-A14
H
Control
Logic
I
I
I
I
I-RAM
8000-FFFF
J1I'043256A
I
Header
'----
J1I'078220
J1I'D78233
84-PinPLCC
Socket
WTiW
o
9-40
Extended
Dam Memory
EPROM
Footprint
FOOOO-FFFFF
27C512
I
49NR-68OB
ttlEC
DDB·78K2
Hardware Description
Additional commands are available to:
The DDB-78K2 features 64K bytes of on-board memory.
The first 32K bytes are dedicated to ROM and include a
powerful monitor program. The second 32K bytes are
dedicated to RAM and can include a user area for user
program downloading (28K bytes), interrupt and CALLT
re-vector area (256 bytes), monitor work area (3.8K
bytes), and the internal RAM and register area of the
p.PD78213, p.PD78220, or p.PD78233 (768 bytes). The
DDB-78K2 contains a footprint for a user installed
p.PD27C512 EPROM. This provides access to 64K bytes
of extended data memory space (OFOOOOH to
OFFFFFH).
• Display, fill, change, or move memory
• Display or change the general and· special function
registers
• Disassemble memory
• Display the command list
• Initialize the interrupt and call table re-vector areas
• Set the monitor's environment
The microcomputer UART is connected to a DB25 pin
connector through an RS-232C driver/receiver. If the
capabilities of the UART need to be evaluated, a jumper
selectable option allows the clock-synchronized serial
interface (SIO) to be used in place of the UART for
communicating to a terminal or host computer.
All the microqomputer pins are connected to wirewrap
headers. This provides a convenient place for attaching
oscilloscope probes for performing detailed signal analysis or for connecting application specific hardware.
A reset switch allows the DDB-78K2 to return to the
power-up state without losing the contents of the external RAM. An NMI switch returns control from a user
program to the monitor while saving the user's state. An
AC/DC converter provides power to the DDB-78K2.
Software Description
Every DDB-78K2 has a powerful interactive monitor to
facilitate software design for the p.PD782XX microcomputer. A user program can be downloaded into user RAM
and executed in real-time with or without breakpoints or
executed one instruction at a time. During singlestepping, the registers, program counter, and the next
instruction to be executed are displayed.
The DDB-78K2 has nine address breakpoints. The user
can set up to eight of these prior to program execution.
The ninth breakpoint is reserved for use in the GO
cornrnanu iiut::. lilt=' IIIUllii.UI t;)t:;Li) a ~,-t:;Ci~iJv:i'~::'Y- .;u::;~~:
tuting a software break instruction (opcode 5EH) for an
instruction in the user's program.
Table 1 contains a complete list of the DDB-78K2 monitor
commands and their syntax.
Table 1. Command Ust
Command
Function
Syntax
?/H
Print this summary of
commands
? or H
B
Show or set breakpoints
B{bpH,addr}
C
Change memory bytes
C{{b:}addrH,val}
D
Display memory bytes
D{{b:}addr}{.addr}
E
Show or set environment
variables
E{var,val}
F
Fill memory bytes with
value
F{b:}addr,addr,val
G
Go (execute to
breakpoint)
G{addrH,addr}
Initialize interrupt &
CALLT vectors
K
Kill breakpoint(s)
K{bp}
L
Load HEX file into
memory
L{{b:}addr}
M
Move a block of memory
M{b:}addr,addr,{b:}addr
R
Display/change registers
R{s,}{reg{,val}}
S
Display/change special
function registers
S{sfr{,val}}
T
Trace execution (trace
mode)
T{addr}
U
Unassemble a block of
memory
U{addr}{,addr}
Notes:
PJ aour
=
= four-bit bank number in hexadecimal format (0 - FH).
bp = breakpoint number (0 - 7).
reg = general purpose register mnemonic.
s = register bank selector (0 - 3).
sIr = special function register mnemonic.
val = eight-bit value in hexadecimal notation.
(2) b
(3)
(4)
(5)
(6)
(7)
(8) var = environment variable mnemonic.
(9) {
}
= optional parameter.
9-41
Pel
iii
DDB-78K2
Documentation
For further information on the DDB-78K2 Evaluation
Board, NEC Electronics, Inc. provides the following manual:
• DDB-78K2 ",PD782XX Evaluation Board User's Manual
This manual is provided with the board. Additional copies may be obtained from NEC Electronics Inc.
9-42
NEe
NEe
EB-78210
Evaluation Board
for the IIPD78213
NEe Electronics Inc.
Description
CI
The EB-78210 is an evaluation board for the NEC
p.PD78213 eight-bit, single-chip microcomputer. The EB78210 provides a simple way to evaluate the capabilities
of the p.PD78213 in an application without having to
build a prototype. If it is necessary to connect the
EB-78210 directly to a target system, the IE-7821O emulator probes can be purchased separately.
CI
Display/change speCial function registers
CI
User program upload/download capability
The EB-78210 features 32K bytes of static RAM for
evaluation programs, an RS-232C communication port,
and a powerful on-board monitor. Evaluation programs
can be downloaded from a host computer or created
directly on the board using the line assembler. Programs
can be executed in real-time with or without breakpoints
or one instruction at a time. Commands are available to
display or change memory, general or special function
registers, and to disassemble code.
A controller program cont rols the EB-78210 directly from
the console of an IBM PC@>, PC/XT@>, PC AT@>, or compatible host computer using an RS-232C serial interface.
Features
CI
p.PD78213 evaluation board
CI
32K bytes of static RAM
CI
Real-time and single-step execution
CI
Four parallel or sequential breakpoints
Display/change memory and general registers
CI
Symbolic debugging support
CI
Line assembler and disassembler
CI
RS-232C serial interface for host computer
CI
Host control software for IBM PC, PC/XT, PC AT, or
compatibles
CI
Connection to a target system using in-circuit
emulator probes
IBM PC, PClXT and PC AT are registered trademarks of International
Business Machines Corporation.
Ordering Information
Part Number
Description
EB-78210-PC
,,078213 evaluation board OBM PC Based)
EP-78210CW-R
Emulator probe for 64-pin shrink DIP package
(op1ional)
EP-78210GJ-R
Emulator probe for 74-pin QFP (optionaQ
EP-78210GQ.R
Emulator probe for 64-pin QUIP package
(optional)
EP-78210L-R
Emulator probe for 68-pin PLCC package
(optional)
EB-78210
502111
9-43
ttlEC
EB·78210
Block Diagram
POmD'2,t:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::~
3,6,7r
AS-A15
rt:::::=Jr=:::::::::::::::A:dd:re:.:.:B:US::::::::::::::::::::::~
PPD78213
EmulalQr
Probe
AddressIDala Bus
49NR-6598
9-44
ttlEC
Hardware Description
The EB-78210 features 32K bytes of on-board static
RAM. It can be used without a target system or can be
directly connected to a target system using one of the
IE-7B210 emulation probes. When the EB-78210 is used
without a target system, 28K bytes of RAM are available
for downloading programs; the on-board monitor uses
the remaining 4K bytes as a work area. When the EB78210 is connected to a target system, 52K bytes of the
~PD78213's 64K-byte code space are mapped to the
target system. The extended ~PD78213 data memory
space (10000H to OFFFFFH) is also mapped to the
target system. A memory extension command specifies
the high-order four bits of the address of the external
extended data memory for use in the memory display
commands.
The serial port for the host computer connection consists of a ~PD71051 USART, an RS-232C driver/receiver,
and a DB25 pin connector. A reset switch returns the
EB-78210 to the power-up state. An AC/DC converter is
shipped with each EB-78210 board for convenience. The
EB-78210 can also be powered from batteries using the
enclosed battery holder.
Emulation
EB·78210
sequential breakpoint, each address must be encountered in the specified order before a break in emulation
can occur. These breakpoints are set by substituting a
software break instruction for an instruction In the user's
program.
Software Description
The EB-78210 is controlled from the console of an IBM
PC, PC/XT, PC AT, or compatible computer with an
RS-232C interface using the ehclosed emulator controller program. This program provides commands for
downloading and uploading object· code and symbol
files to and from the EB-78210. A line assembler and
disassembler avoid debugging In machine code. The
symbolic debugging commands allow the use of labels
instead of absolute addresses. Full data manipulation
capability is available with the change register/memory
commands. Initialization commands allow the user to
choose a base number, register mnemonics, and extended data memory segment.
The EB-78210 program also has macro command file
capability, so the user can execute a defined set of
commands automatically. The on-line help facility, history command, and ability to store the console display
on disk or send it to a printer ease debugging tasks.
The EB-78210 allows the following methods of program
emulation: real-time program execution with or without
breakpoints; real-time program execution for a specified
number of instructions; single-step emulation for a specified number of instructions or until a register condition
is satisfied. The registers, stack pointer, program status
word, and program counter are displayed following termination of real-time emulation or during single-step
emulation. The EB-78210 enters the single-step mode
following a real-time emulation break. When the enter
key is pressed during single-step emulation, the next
instruction is executed and the executed address, instruction mnemonic and above data are displayed.
Table 1 lists the available EB-78210 commands. These
are a subset of the IE-7821O commands.
Table 1. CommandUsf
Command Function
ASM
Une assemble command
BRS
Sets Instruction address breakpOints
COM
Creates command file
DAS
Disassemble command
DIR
Displays disk directory
EXP
Changes/displays high-order four bits of an address of
the externally extended data memory
Emulation Accuracy
EXT
Terminates EB-78210 controller program operation
When the emUlation proDa is COlllltlCLtlU LU a La' 1:1'"
system, ports 0, 2, 3, 6, 7, and the A/D converter related
signals are identical to the device. However, all other
signals differ from the actual device because of buffering
and control gating.
!-II!':
Disolava last twenty commands
HLP
Displays format of commands
LOD
Loads object code and symbol files
LST
Sends console display to disk or printer
MAP
Dlslays memory map
Breakpoint Capabilities
MAT
Evaluates arithmetiC expression
The EB-78210 has four parallel instruction address
breakpoints or up to a four-level sequential instruction
address breakpoint. If anyone of the four parallel breakpoints is satisfied, a break in emulation occurs. For a
MDR
Displays/modifies "PD78213 mode registers
MEM
Memory manipulation command
REG
Displays/modifies "PD78213 registers
I]
9-45
E8·78210
Tsbl• .,. CQID",.nd US, (con#)
Command FunctIon
RES
Resets only the "PD78213
RGM
ChangeS/displays the Implied or general register mode
for the display of registers In a disassembler list
RUN
Executes programs In slngle-step mode or In real·tlme
with options for break conditions
SAY
Saves contents of memory onto disk
SPR
DlsplayS/modlfles "PD78213 special function registers
STR
Automatically executes command string file
S UF
Base number specification (hex, octal, binary,
declmaQ
SYM
AddS/deleteS/displayS/changes/loads/saves symbols
VFf( .
Compares contents of an object file with memory
Equipment Supplied
The EB-78210-PC package consists of the following:
•
•
•
•
•
•
EB-78210 evaluation board
EB-78210 user's manual
System disk for IBM PC
AC/DC converter power supply
Battery holder and mounting hardware
Warranty policy and registration card
Documentation
For further information on EB-78210 operation, NEC
Electronics Inc. provides the following manual with the
board:
• EB-78210 "PD78213 Evaluation Board User's Manual
Additional copies may be obtained from NEe
Electronics Inc.
9-46
t¥EC
NEe
EB-78220
Evaluation Board
for the pPD78220
NEG Electronics Inc.
Description
The EB-78220 is an evaluation board for the NEC
,...PD78220 eight-bit single-chip microcomputer. The EB78220 provides a simple way to evaluate the capabilities
of the ,...PD78220 in an application without having to
build a prototype. If it is necessary to connect the
EB-78220 directly to a target system, the IE-78220 emulator probes can be purchased separately.
The EB-78220 features 32K bytes of static RAM for
evaluation programs, an RS-232C communication port,
and a powerful on-board monitor. Evaluation programs
can be downloaded from a host computer or created
directly on the board using the line assembler. Programs
can be executed in real-time with or without breakpoints
or one instruction at a time. Commands are available to
display or change memory, general or special function
registers, and to disassemble your code.
o Four parallel or sequential breakpoints
o Display/change memory and general registers
o Display/change special function registers
o User program upload/download capability
o Symbolic debugging support
o Line assembler and disassembler
o RS-232C serial interface for host computer
o Host control software for IBM PC, PC/XT, PC AT, or
compatibles
o Connection to a target system using in-circuit
emulator probes
IBM PC, PC/XT, and PC AT are registered trademarks of International
Business Machines Corporation.
Ordering Information
A controller program controls the EB-78220 directly from
the console of an IBM PC®, PC/XT®, PC AT® or compatible host computer using an RS-232C serial interface.
Part Number
Description
EB-78220-PC
/lPD78220 evaluation board (IBM PC Based)
EP-78220GJ-R
Emulator probe for 94-pin QFP (optional)
Features
EP-78220L-R
Emulator probe for 84-pin PLCC package
(optional)
o ,...PD78220 evaluation board
o 32K bytes of static RAM
o Real-time and single-step execution
EB-7B220
_eo
9-47
NEe
EB·78220
Block Diagram
r
PortsO'l'2,t:=====================================~
3,6,7, PT
AS-A15
J.tPD78220
r
t:==:;Ir=========A=d:d:re:ss:B:U:S::==========~~
Probe
Emulator
Address/Data Bus
49NR-658B
9-48
t\fEC
Hardware Description
The EB-78220 features 32K bytes of on-board static
RAM. It can be used without a target system or can be
directly connected to a target system using one of the
IE-78220 emulation probes. When the EB-78220 is used
without a target system, 28K bytes of RAM are available
for downloading programs; the on-board monitor uses
the remaining 4K bytes as a work area. When the EB78220 is connected to a target system, 52K bytes of the
~P078220's 64K-byte code space are mapped to the
target system. The extended ~P078220 data memory
space (10000H to OFFFFFH) is also mapped to the
target system. A memory extension command specifies
the high-order four bits of the address of the external
extended data memory for use in the memory display
commands.
The serial port for the host computer connection consists of a ~PD71051 USART, an RS-232C driver/receiver,
and a OB25 pin connector. A reset switch returns the
EB-78220 to the power-up state. An AC/OC converter is
shipped with each EB-78220 board for convenience. The
EB-78220 can also be powered from batteries using the
enclosed battery holder.
Emulation
The EB-78220 allows the following methods of program
emulation: real-time program execution with or without
breakpoints; real-time program execution for a specified
number of instructions; single-step emulation for a specified number of instructions or until a register condition
is satisfied. The registers, stack pointer, program status
word, and program counter are displayed following termination of real-time emulation or during single-step
emulation. The EB-78220 enters the single-step mode
following a real-time emulation break. When the enter
key is pressed during single-step emulation, the next
instruction is executed and the executed address, instruction mnemonic and above data are displayed.
Emulation Accuracy
When the emulation probe is connected to a target
system, ports 0, 1,2,3,6,7 and the analog comparators
are identical to the device. However, all other signals
differ from the actual device because of buffering and
control gating.
Breakpoint Capabilities
The EB-78220 has four parallel instruction address
breakpoints or up to a four-level sequential instruction
address breakpoint. If anyone of the four parallel breakpoints is satisfied, a break in emulation occurs. For a
EB-78220
sequential breakpoint, each address must be encountered in the specified order before a break in emulation
can occur. These breakpoints are set by substituting a
software break instruction for an instruction in the user's
program.
Software Description
The EB-78220 is controlled from the console of an IBM
PC, PC/XT, PC AT, or compatible computer with an
RS-232C interface using the enclosed emulator controller program. This program provides commands for
downloading and uploading object code and symbol
files to and from the EB-78220. A line assembler and
disassembler avoid debuggining in machine code. The
symbolic debugging commands allow the use of labels
instead of absolute addresses. Full data manipulation
capability is available with the change register/memory
commands. Initialization commands allow the user to
choose a base number, register mnemonics, and extended data memory segment.
The EB-78220 program also has macro command file
capability, so the user can execute a defined set of
commands automatically. The on-line help facility, history command, and ability to. store the console display
on disk or send it to a printer ease debugging tasks.
Table 1 lists the available EB-78220 commands. These
are a subset of the IE-78220 commands.
Table 1. CommandUst
Command
Function
ASM
Line assemble command
BRS
Sets instruction address breakpoints
m
COM
Creates command file
DAS
Disassemble command
DIR
Displays disk directory
EXP
Changes/displays high-order four bits of an address of
the externally extended data memory
EXT
Terminates EB-78220 controller program operation
HIS
Displays last twenty commands
HLP
Displays format of commands
LaD
Loads object code and symbol files
LST
Sends console display to disk or printer
MAP
Dislays memory map
MAT
Evaluates arithmetic expression
MDR
Displays/modifies I'PD78220 mode registers
MEM
Memory manipulation command
REG
Displays/modifies I'PD78220 registers
RES
Resets only the I'PD78220
9-49
t-IEC
EB·78220
Table 1. Command List (cont)
Documentation
Command
Function
RGM
Changes/displays the implied or general register mode
for the display of registers in a disassembler list
For further information on EB-78220 operation, NEC
Electronics Inc. provides the following manual with thl3
board:
RUN
Executes programs in single-step mode or in real-time
with options for break conditions
SAY
Saves contents of memory onto disk
SPR
Displays/modifies "PD78220 special function registers
STR
Automatically executes command string file
SUF
Base number specification (hex, 'octal, binary,
decimal)
SYM
Adds/deletes/displays/changes/loads/saves symbols
VRY
Compares contents of an object file with memory
Equipment Supplied
The EB-78220-PC package consists of the following:
•
•
•
•
•
•
EB-78220 evaluation board
EB-78220 user's manual
System disk for IBM PC
AC/DC converter power supply
Battery holder and mounting hardware
Warranty policy and registration card
9-50
• EB-78220 ~PD78220 Evaluation Board User's Manual
Additional copies may be obtained from NEC
Electronics Inc.
NEe
IE-78210
In-Circuit Emulator
NEG Electronics Inc.
Description
The1E-7821O is an in-circuit emulator providing both
hardware emulation and software debugging capabilities for the NEC I'PD78213 and I'PD78214 single-chip
microcomputers. Real-time and single-step emulation,
inconjunction with sophisticated memory mapping features, breakpoints, and trace capabilities, create a
powerful debugging environment. A line assembler/
disassembler, full register and memory control, symbolic
debugging, and complete upload/download capabilities
simplify the task of debugging hardware and software.
Features
o Real-time and single-step emulation capability
o User-specified breakpoints; logical OR of up to four
o Powerful memory mapping feature
- 64K bytes of RAM mappable in 128-byte blocks
- Up to 16K bytes of high-speed internal RAM for
I'PD78214 ROM emulation
o Line assembler/disassembler
o Symbolic debugging
- 2,000 symbols available
-IEEE-796 bus memory expansion slot for 32K
additional symbols
o CMOS latch-up warning and protection
o Eight external sense clips on emulator probe
o Stand-alone mode or system mode with host control
program
IE-78210
sets of break conditions
- Opcode fetch count
- External sense clip condition
- Parallel or sequential fetch address break
- Logical AND of addresses, data values, CPU
controls, and loop count
o Sophisticated trace capabilities
- Traces program-fetch or data access
- 2K x 44-bit trace buffer
- Address, control, data, and external signal trace
features
- Instruction or frame display
- Trace search capability
- Trace display before or after specified break
IBM PC, PC/XT, and PC AT are registered trademarks of International
Business Machines Corporation.
50193
9-51
t¥EC
IE·78210
Block Diagram
IE-78210-R
RS-232C
Controll
Trace
Module
Host
Emulator Probe
IE System Bus
Driver
;1--~_Ta...:rg,,-et,--p-,ro,--be~-:1ILJI
.~
Module
8 External Sense Clips
49NR-60SB
Ordering Information
Part Number
Deacrlptlon
IE-78210-R
In-clrcult emulator for "PD7821X
EP-78210CW-R
Emulator probe for 64-pln shrink DIP (optlonaQ
EP-78210GJ-R
Emulator probe for 74-pln QFP (optlonaQ
EP-78210GC-R
Emulator probe for 64-pln QUIP (optlonaQ
EP-78210L-R
Emulator probe for 68-pln PLCC (optlonaQ
Hardware Description
As the IE-7821O block diagram shows, the IE-7821O
hardware consists of a control/trace module, driver module, target probe, external sensing clips, and interconnecting system bus. The control/trace module includes
the trace control unit, emulation memory unit, break
control unit, and latch-up alarm unit. This module also
houses the emulation CPU, which directly connects to
the target emulation probe. The driver module houses
the serial interface Circuit, control CPU, trace RAM, and
system memory.
Memory Mapping
The IE-7821O has a sophisticated memory mapping
scheme which allows access of up to 64K bytes of
internal memory, mappable in 128-byte units. The map
command allocates the first 64K bytes of memory space
of the emulation CPU either to the user system or to the
IE system. Even if development of the target system is
not complete, software debugging is still possible by
using this internal RAM in place of the target system
RAM. In addition to this emulation memory, the IE-78210
has an alternate high-speed memory for real-time
emulation of the I-4PD78214 internal ROM. 4K, 8K, 12K, or
16K bytes of the high speed memory can be selected as
internal ROM.
9-52
The extended data memory space of the emulation CPU
(10000H to OFFFFFH) is always mapped to the user
system. A memory extension command is available to
specify the high order four bits of the address of the
external extended data memory for use in the memory
display and break setting commands.
Emulation
The IE-7821O allows the following methods of program
emulation: real-time program execution with or without
breakpoints; real-time program execution for a specified
number of instructions; and single-step emulation for a
specified number of instructions or until a register condition is satisfied. Following termination of real-time
emulation or during single-step emulation, the registers,
stack pointer, program status word, and program
counter are displayed. Following a real-time emulation
break, the IE-7821O enters the single-step mode. Each
time the enter key is pressed during single-step emulation, the next smallest group of instructions is executed
and the above data is displayed.
Emulation Accuracy
Once a breakpoint is reached during emulation, the next
few instructions are executed before breaking actually
occurs. This is known as slip. The exact number of
instructions slipped depends on the instructions in the
prefetch queue and whether the emulation chip is accessing internal ROM or external memory. Ports 4
through 6 and the· AID converter related signals are
identical to the devices. However, other Signals differ
from the actual device due to buffering and control
gating.
ttlEC
IE·78210
Breakpoint Capabilities
Utilities
The break function can be divided Into two types: break
register (physical and logical) breaks and fail-safe
breaks. The user sets physical break registers to cause
emulation breaks upon address, data, status or loop
count; Instruction count; parallel or sequential fetch
addresses or matching a condition on an external sense
clip. Combinations of these physical registers can then
be set to the logical break registers and executed when
running a break command. Fail-safe break conditions
occur unconditionally and include manual break (ESC
key or STP command in RUN N mode), non-mapped
memory break, write-protected memory break, and SFR
Illegal access break.
The upload/download commands provide easy loading
and saving of hex files to and from a host computer. The
on-board assembler/disassembler allows the user to
avoid programming In machine code. The symbolic
debugging commands allow the use of labels instead of
absolute addresses. Full data manipulation capability is
available for the user with the change register/memory
commands. Initialization commands allow the user to
choose a clock source and a base number, and to define
the system memory map.
Trace Capabilities
The IE-78210 has a 2K x 44-bit trace RAM for storing
emulation data from each. machine cycle. All fetchrelated or data access-related addresses, data, CPU
status signals and the eight external sense clips can be
traced for up to 2,047 machine cycles. There are two
types of trace displays: frame mode and instruction
mode. In the frame mode display, the frame number and
type, address and data information and external sense
Clip status are displayed for each frame in the order in
which they are traced. In instruction mode, the executed
Instructions are displayed with their frame number, instruction address, mnemonics and operands. A number
of trace display options are available. These Include the
display of all trace data, the display of only the frames
meeting trace data search conditions, the display of five
lines before or after frame meeting trace data search
condition and the display of a specified number of lines
following detection of the specified break register
condition.
During real-time program emulation without breakpoints, the break condition can be used to stop the
tracer a specified number of frames after the break
condition is satisfied. At tracer stop time, the trace
buffer can be viewed, new trace conditions set and the
trace restarted while the program continues to execute
in real-time.
CMOS Protection
The latch-up alarm circuit is activated when any CMOS
IC in the driver module is in danger of being damaged by
improper voltage levels on the pins. A protection circuit
isolates the power supply to CMOS ICs and the message
"emulation CPU latchupl" is displayed.
System Mode
The IE-78210 can be connected to an IBM P~, PC/XT~,
PC AT~, or MD-086FD-10 by an RS232C port and operated in system mode. By using the accompanying control software, the debugging capabilities of the IE-78210
are greatly increased. It has a macro command file
capability, allowing the user to execute a defined set of
commands automatically. The on-line help facility, the
history command, and the ability to store the console
display on disk ease debugging tasks. The uploading!
downloading capability can be utilized to upload and
download both object code and symbol information.
Other advantages are a verify command that compares
memory to hex files, an alter symbol command, and a
termination command for exiting to the operating
system.
Table 1 lists commands available for both the standalone and system modes of the IE-7821O. Commands
listed in table 2 supplement table 1, but can only be used
in the system mode.
Tllble 1. Stllnd-AIone lind System lIIode
Commllnds
Command
Function
ASM
line assemble command
BR?
Changes/di splays breakpoint regl ster used for
stoppln" real-time emulation
ClK
Clock command Onternal or externaO
UA~
UI8aSSemDI8 commanD
DlY
ChangeS/displays trace frame count after trace
trigger has been detected
EXP
Changes/displays high-order 4 bits of an address of
the externally extended data memory
LCD
loads hex format file Into program memory
MAP
Memory mapping (64K bytes are accessible)
MAT
Performs arithmetic operation on an expression
MDR
Displays/modifies mode registers of emulator CPU
MEM
Memory manipulation command
9-53
NEe
IE·78210
Equipment Supplied
DIble 1. SllIIItI-AIone and ~yst.m IIode
CommendII(contJ
The IE-78210-R package consists of the following:
Command
Function
MOD
sets chamel two mod. setting
MOV
MoveS m.mory content to different mapping area
IE-7821O housing
IE-78210-R user's manuals
Systel"fl disk for MD-Dse series
System disk for IBM PC
AC power cable
AC ground adapter
Ground cable
Spare fuse
RS-232C interface cable
Two 16-pin component carriers
Warranty policy and registration card
SAY
Saves contents of h.x m.mory onto. disk
•
•
•
•
•
•
•
•
•
•
•
SPR
Displaye/modifl.. special registers of emulator
CPU
Basic Specifications
STP
Stops emulation CPU during normal emulation
SUF
Baa. number speCification (hex, octal,
SYM
CI.. re, displays, or changes a symbol
TRG
Starts· real-tim. trac.r during normal .mulatlon
TR?
Changes/displays trace conditions for either realtime or slngl_tep .mulatlon
PGM
Performe PG sarles programmer from II:!
REG
Displaya/modifl.. reglst~ of .mulator CPU
RES
Resets 1E-78210 and/or emulator CPU
RGM
Changee/dlsplays th.lmplled or g.neral register
mod. for the display of reglstere In a dl.....mbl.r
list
RUN
Comm.nc.. ex.cutlon of .mulator CPU In realtime with options for break conditione
blna~
d.clmaQ
Compares cont.nts of an object fll' with memory
contents
Dlbl.2. Syst.m IIode Only COIIJIIIIIIIds
Command
Function
COM
Creat.. command fll.
DIR
Displays fllenam..
EXT
Terminates 18078210 operation
HIS
Displays last twenty commands
HLP
Displays command format
LST
Stor.. console display on·dlsk
STR
Automatically ex.cutes macro command fll.
SYM
Loads and saves eymbol file
• Weight: 10.5 kg
• External dimensions: length, 395 mm; width, 291 mm;
height, 217 mm
• Power consumption: 100 V AC, 50/60 Hz, 5 A
environmental Characteristics
• Operating temperature range: 10 to + 40°C
• StoragE! temperature range: -20 to +45°C
• Ambient humidity range: 10 90% relative humidity
to
Documentation
For further Information on IE-78210 operation, NEC
Electronics Inc. provides the following manuals with the
in-circuit emulator:
.
Additional copies may be obtained from NEC
Electronics Inc.
9-54
.
• IE-78210 "PD7821X In-Circuit Emulator HardWare
Manual
.IE-78210 "PD7821X In-Circuit Emulator Software
Manual
• IE78210 Controller Program User's Manual
(IBM PC Based)
NEe
NEG Electronics Inc.
Description
The IE-78220 is an in-circuit emulator providing both
hardware emulation and software debugging capabilities for the NEC p.PD78220 and p.PD78224 single-chip
microcomputers. Real-time and single-step emulation, in
conjunction with sophisticated memory mapping features, breakpoints and trace capabilities, create a
powerful debugging environment. A line assembler/
disassembler, full register and memory control, symbolic
debugging, and complete upload/download capabilities
simplify the task of debugging hardware and software.
Features
o Real-time and single-step emulation capability
o User-specified breakpoints; logical OR of up to four
sets of break conditions
- Opcode fetch count
- External sense clip condition
- Parallel or sequential fetch address break
- Logical AND of addresses, data values, CPU
controls, and loop count
IE·78220
In·Circuit Emulator
o Sophisticated trace capa~ilities
- Traces program fetch or data access
- 2K x 44-bit trace buffer
- Address, control, data, and external signal trace
features
-Instruction or frame display
- Trace search capability
- Trace display before or after specified break
o Powerful memory mapping feature
- 64K bytes of RAM mappable in 128-byte blocks
- Up to 16K bytes of high-speed internal RAM for
p.PD78224 ROM emulation
o Line assembler/disassembler
o Symbolic debugging
- 2,000 symbols available
-IEEE-796 bus memory expansion slot for 32K
additional symbols
o CMOS latch-up warning and protection
o Eight external sense clips on emulator probe
o Stand-alone mode or system mode with host control
program
IBM PC, PCIXT, and PC AT are registered trademarks of International
Business Machines Corporation.
IE-78220
II
50182
9-55
NEe
IE·78220
Block Diagram
IE-78220-R
Host
RS-232C
.......,...,...,.,.,.,.,...,.,.,.,.,.,.,.,.,.,,',',',','"",,"""""""
Controll
Trace
Module
Emulator Probe
Target Probe
IE System Bus
Driver
Module
8 External Sense Clips
49NR-579B
Ordering Information
Part Number
Description
IE-78220-R
In-circuit emulator for "PD78220/78224
EP-78220GJ-R
Emulator probe for 94-pln QFP (optionaQ
EP-78220L-R
Emulator probe for 84-pin PLCC (ojltionaQ
Hardware Description
As the IE-78220 block diagram shows, the IE-78220
hardware consists of a control/trace module, driver module target probe, external sensing clips, and interconne~ting system bus. The control/trace module includes
the trace control unit, emulation memory unit, break
control unit, and latch-up alarm unit. This module also
houses the emulation CPU, which directly connects to
the target emulation probe. The driver module houses
the serial interface circuit, control CPU, trace RAM, and
system memory.
Memory Mapping
The IE-78220 has a sophisticated memory mapping
scheme which allows access to up to 64K bytes of
internal memory, mappable in 128-byte units. The map
command allocates the first 64K bytes of memory space
of the emulation CPU either to the user system or to the
IE system. Even if development of the target system is
not complete, software debugging is still possible by
using this internal RAM in place of the target system
RAM. In addition to this emulation memory, the IE-78220
has an alternate high-speed memory for real-time emulation ofthe ILPD78224 internal ROM. 4K, 8K, 12K, or 16K
bytes of the high speed memory may be selected as
internal ROM.
9-5.6
The extended data memory space of the emulation CPU
(10000H to OFFFFFH) is always mapped to the user
system.. A memory extension command is available to
specify the high order four bits of the address of the
external extended data memory for use in the memory
display and break setting commands.
Emulation
The IE-78220 allows the following methods of program
emulation: real-time program execution with or without
breakpoints; real-time program execution for a specified
number of instructions; and single-step emulation for a
specified number of instructions or until a register condition is satisfied. Following termination of real-time
emulation or during single-step emulation, the registers,
stack pointer, program status word, and program
counter are displayed. Following a real-time emulation
break, the IE-78220 enters the single-step mode. Each
time the enter key is pressed during single-step emulation, the next smallest group of instructions is executed
and the.above data is displayed.
Emulation Accuracy
Once a breakpoint is reached, during emulation, the next
several instructions are executed before breaking actually occurs. This is known as slip. The exact number of
instructions slipped depends on the instructions in the
prefetch queue and whether the emulation chip is accessing internal ROM or external memory. Ports 4, 5., 6,
and the T related signals are identical to the devices.
However, other signals differ from the actual device due
to buffering and control gating.
NEe
IE·78220
Breakpoint Capabilities
Utilities
The break function can be divided into two types; break
register (physical and logical) breaks, and fail-safe
breaks. The user can set physical break registers to
cause emulation breaks upon address, data, status, or
loop count; instruction count; and parallel or sequential
fetch addresses or matching a condition on an external
sense clips. Combinations of these physical registers
can then be set to the logical break registers and
executed when running a break command. Fail-safe
break conditions occur unconditionally and include
manual break (ESC key or STP command in RUN N
mode), non-mapped memory break, write-protected
memory break, and SFR illegal access break.
The upload/download commands provide easy loading
and saving of hex files to and from a host computer. The
on-board assembler/disassembler allows the user to
avoid programming in machine cqde. The symbolic
debugging commands allow the use of labels instead of
absolute addresses. Full data manipulation capability is
available for the user with the change register/memory
commands. Initialization commands allow the user to
choose a clock source and a base number, and to define
the system memory map.
Trace Capabilities
The IE-78220 has a 2K x 44-bit trace RAM for storing
emulation data from each machine cycle. All fetchrelated or data access-related addresses, data, CPU
status signals and the eight external sense clips can be
traced for up to 2,047 machine cycles. There are two
types of trace displays: frame mode and instruction
mode. In the frame mode display, the frame number and
type, address and data information and external sense
clip status are displayed for each frame in the order in
which they are traced. In instruction mode, the executed
instructions are displayed with their frame number, instruction address, mnemonics and operands. A number
of trace display options are available. These include the
displaying of all trace data, the displaying of only frames
meeting trace data search conditions, the displaying of
five lines before or after frame meeting trace data search
condition, and the displaying of a specified number of
lines following detection of the specified break register
condition.
During real-time program emulation without breakpoints, the break condition can be used to stop the
tracer a specified number of frames after the break
condition is satisfied. At tracer stop time, the trace
System Mode
The IE-78220 can be connected to an IBM PC®, PC/XT®,
PC AT®, or MD-086FD-10 via an RS232C port and operated in system mode. By using the accompanying control software, the debugging capabilities ofthe IE-78220R are greatly increased. It has a macro command file
capability, allowing the user to execute a defined set of
commands automatically. The on-line help facility, the
history command, and the ability to store the console
display on disk ease debugging tasks. The uploading/
downloading capability can be utilized to upload and
download both object code and symbol information.
Other advantages are a verify command that compares
memory to hex files, an alter symbol command, and a
termination command for exiting to the operating
system.
Table 1 lists commands available for both the standalone and system modes of the IE-78220. Commands
listed in table 2 supplement table 1, but can be used only
in the system mode.
Table 1. Stand-Alone and System Mode
Commands
Command
Function
ASM
Line assemble command
-S-R?-.---C-h-a-ng-e-s/-d-is-pl-ay-s-b~re-a-kp-o-in-t-re-g-is-te-r-u-se-d-f-or--stopping real-time emulation
ClK
Clock command (internal or externaQ
hllffor ,::,?n ho \/iawon, now tr~~A ~nnrlitinnr;::. ~At_ and thA
----w-.-_-~-~;;--;-,~-,:;.-:~-~-;;-;_.-.:...;_;-•.:;-;_;~----...:------
trace restarted while the program continues to execute
in real-time.
DlY
Changes/displays trace frame count after trace trigger
has been detected
CMOS Protection
EXP
Changes/displays high-order 4 bits of an address of
the externally extended data memory
The latch-up alarm circuit is activated when any CMOS
IC in the driver module is in danger of being damaged by
improper voltage levels on the pins. A protection circuit
isolates the power supply to CMOS ICs and the message
"emulation CPU latchup !" is displayed.
LCD
loads hex format file into program memory
MAP
Memory mapping (64K bytes are accessible)
MAT
Performs arithmetic operation on an expression
MDR
Displays/modifies mode registers of emulator CPU
MEM
Memory manipulation command
9-57
ttiEC
IE-78220
Table 1. Stand-Alone and System Mode
Commands (cont)
Command
Function
MOD
Sets channel two mode setting
MOV
Moves memory content to different mapping area
PGM
Performs PG series programmer from IE
REG
Displays/modifies registers of emulator CPU
RES
Resets IE·78220 and/or emulator CPU
RGM
Changes/displays the implied or general register mode
for the display of registers in a disassembler list
RUN
Commences execution of emulator CPU in real-time
with options for break conditions
SAV
Saves contents of hex memory onto disk
SPR
Displays/modifies special registers of emulator CPU
STP
Stops emulation CPU during normal emulation
SUF
Base number specification (hex, octal, binary,
decimaQ
SYM
Clears, displays, or changes a symbol
TRG
Starts real-time tracer during normal emulation
TR?
Changes/displays trace conditions for either real-time
or single-step emulation
VRY
Compares the contents of an object file with memory
contents
Table 2. System Mode Only Commands
Command Function
COM
Equipment Supplied
The IE-78220-R package consists of the following:·
•
•
•
•
•
•
•
•
•
•
•
IE-78220 housing
IE~78220-R user's manuals
System disk for MD-086 series
System disk for IBM PC
AC power cable
AC ground adapter
Ground cable
Spare fuse
RS-232C interface cable
Two 16-pin component carriers
Warranty policy and registration card
Basic Specifications
• Weight: 10.5 kg
• External dimensions: length, 395 mm; width, 291 mm;
height, 217 mm
• Power consumption: 100 V AC, 50/60 Hz, 5 A
Environmental Characteristics
• Operating temperature range: 10 to +400 C
• Storage temperature range: -20 to + 450 C
• Ambient humidity range: 10 to 90% relative humidity
Documentation
Creates command file
DIR
Displays file names
EXT
Terminates IE-78220 operation
HIS
Displays last twenty commands
HLP
Displays command format
LST
Stores console display on disk
STR
Automatically executes macro command file
SYM
Loads and saves symbol file
For further information on the IE-78220 operation, NEC
Electronics Inc. provides the following manuals with the
in-circuit emulator:
• IE-78220 ItPD7822X In-Circuit Emulator Hardware
Manual
• IE-78220 ItPD7822X In-Circuit Emulator Software
Manual
• IE78220 Controller Program User's Manual
(IBM PC Based)
Additional copies may be obtained from NEC
Electronics Inc.
9-58
t¥EC
NEe Electronics Inc.
CC782XX
C Complier Package
for the pPD782XX Series
Description
Complier Options
The CC782XX C compiler package for the NEC
"PD782XX microcomputers consists of an Kernighan
and Ritchie compatible C cross compiler (CC210), relocatable assembler (RA210), linker (LK210) , librarian
(LB210), locater (LC210), and an emulator controller
program. The CC782XX C compiler package is available
for use on an MS-DOS. system with a free-standing
system as the target (embedded system).
The CC210 C compiler supports the following options
during compilation:
Features
o Kernighan and Ritchie standard·C
- unsigned, enum, typedef, interrupt keywords
- extern, auto, static, register keywords
o Legal C code verification integrated into the
compiler
o User-selectable and directable output files, list and
full cross reference files
o Macro definitions
o Branch optimization
o Conditional assembly
o Simple diagnostics
o Powerful librarian
Ordering Information
Part Number
System
Description
CCMSD-15DD-782XX
MS-DOS
5-1/4 Inch double-density floppy
diskette
C CROSS COMPILER (CC210)
Description
The CC210 C cross compiler converts standard C
source code into relocatable object modules. The same
relocatable object format is used for all relocatable
UUJ~CL III~tj ill Lilt; C t,,;UIII..,iiCliI ..,tu.;~a\:l"'J 1-~wal-~;gOO u: :.uY-i
it is generated (by an assembler or compiler).
•
•
•
•
•
•
•
•
Integer size control
Include file control
Defining/undefining constants
Prologue/epilogue control
Forced stack checking before each C function
Packed data allocation
Special relocatable data segment
Microprocessor type
C Library Functions
The CC210 C Compiler library includes most of the
important C library functions that apply to PROM-based
embedded systems. All library functions reside in the
supplied library files. Header files that declare the set of
library functions are also included.
The following character operation macros are available:
CHARACTER HANDLING < ctype.h >
Classification macros:
isalnum isalpha isascii iscntrl isdigit isgraph
islower isprint ispunct isspace isupper isxdigit
Conversion macros:
toascii to lower toupper
The following library functions are available:
NON-LOGICAL JUMPS < setjmp.h >
longjmp setjmp
FORMATTED INPUT/OUTPUT < stdio.h >
sscanf sprintf
__... _...... __ .1_... __
~I:~II=OA
I
11 ..... 11 ITIr:=Q
crta (startup for C programs)
cipt ~nterrupt system support)
chkstk (check for stack overflow)
MS-DOS Is a registered trademark of Microsoft Corporation.
50247
9-59
NEe
CC782XX
STRING HANDLING < string.h >
strcat strchr strcmp strcpy strcspn strlen strncat
strncmp strncpy strpbrk strrchr strspn strtok
MATHEMATICS
abs atoi atol
Memory Models
CC210 supports only the small memory model, since the
",PD782XX series can only address a maximum of 64K
bytes of program memory.
RELOCATABLE ASSEMBLER (RA210)
Description
RA210 translates a symbolic source module into a relocatable object module. The assembler verifies that each
instruction is valid for the target ",PD782XX microcomputer and produces a listing file and a relocatable object
module.
Character constants are translated into seven-bit ASCII
codes. Numeric constants may be specified as binary,
octal, decimal, or hexadecimal. Arithmetic expressions
may include the operators +, -, *, /, MOD, OR, AND,
NOT, XOR, EO, NE, LT, LE, GT, GE, SHR, SHL, LOv-.:
HIGH, ., (), and character constants.
Macro Capability
RA210 allows the definition of macro code sequences
with up to five parameters, LOCAL symbols, and special
repeated code sequences. The macro code sequence
differs from a subroutine call because the invocation of
a macro in the source code results in the direct replacement of the macro call with the defined code sequence.
Assembler Directives
Assembler directives give instructions to the assembler
but are not translated into machine code during assembly. Basic assembler directives include: storage definition and allocation directives (DB,ovv, DS, DBIT); symbol
directives (EOU, SET); location counter control directive
(ORG). Program control directives include: segment directives (CSEG, CSEG FIXED, CSEG CALLT, DSEG,
BSEG, ENDS); linkage directives (NAME, PUBLIC, EXTRN, EXTBIT); macro directives (MACRO, LOCAL,
REPT, IRp, ENDM, EXITM); automatic BR instruction
selection directive (BR) and assembly termination directive (END).
9-60
Assembler Controls
There are two types of assembler controls available for
RA210. Primary controls specified in the assembler
command line or at the beginning of the source module,
are as follows:
•
•
•
•
•
•
•
•
Processor selection
Output object file selection
Output list file selection
Listing format controls
Date specification
Optimization selection
V\brkfile drive selection
Symbol letter case selection
General controls, specified in the source program, are as
follows:
• Inclusion of other source files
• Page eject
• Generation/suppression of listing
• Listing subtitles
• Conditional assembly controls
LINKER (LK210)
LK210 combines multiple relocatable object modules
and library modules and converts them into a single
relocatable object module. The linker resolves PUBLIC/
EXTRN references between modules, creating a relocatable output module that contains both relocatable object
code and symbol information. The linker will also search
library files for required modules to resolve external
references. The linker controls for LK210 can be specified in either the command line or in a parameter file.
Linker options include specifying the date and the absolute load module name, specifying the creation of a list
file containing a link map, and specifying the letter case
for symbols.
LOCATER (LC210)
LC210 converts a relocatable object module with no
external references into an ASCII hexadecimal format
absolute object code file. The locater outputs two files:
an absolute load file in an expanded seven-bit ASCII
hexadecimal format, which can be downloaded to a
PROM programmer and a symbol file for the symbolic
debugger. Locater options include specifying the starting address and order for code/data/stack segments,
specifying areas of memory to be protected from being
assigned, and specifying the creation of a map file with
symbol tables.
~EC
CC782XX
LIBRARIAN (LB210)
LICENSE AGREEMENT
LB210 allows commonly used relocatable object modules to be stored in one file and linked into multiple
programs, greatly increasing programming efficiency.
When a library file is included in the input of the linker, the
linker extracts from the library file only those modules
required to resolve external references and links them
with the other modules.
CC782XX is $old under terms of a license agreement,
which is included with purchased copies of the assembler. The accompanying card must be completed and
returned to NEC Electronics Inc. to register the license.
Software updates are provided free to registered users
for one year.
The librarian creates and maintains library files containing relocatable object modules. Modules can be added
to or deleted from a library file, or the contents of the
library file can be listed.
DOCUMENTATION
EMULATOR CONTROLLER PROGRAM
Absolute object files produced by the CC782XX C compiler package can be debugged using the appropriate
NEC stand-alone in-circuit emulator. NEC emulator controller programs allow you to communicate with the
emulator through an RS-232C serial line. An emulator
controller program is available to run on the IBM P~,
PCJXT~, or PC A~ under MS-DOS. The emulator controller program provides the following features:
•
•
•
•
•
•
•
•
For further information on source program formats, C
compiler and assembler operation, and actual program
examples, NEC Electronics Inc. provides the following
documentation:
• CC78XXX C Compiler IlPD78XXX C Compiler
User's Manual
• CC78XXX C Compiler IlPD78XXX Relocatable
Assembler User's Manual
This documentation is provided with purchased copies
of the package. Additional copies may be obtained from
NEC Electronics Inc.
Uploading/downloading of object/symbol files
Symbolic debugging capability
Complete emulator control from host console
On-line help facilities
Macro command file capabilities
Host system directory and file display
Disk storage of debug session
Storage of last 20 commands for recall
II
IBM PC, PCJXT, and PC AT are registered trademarks of International
Business Machines Corporation.
9-61
CC782XX
9-62
NEe
NEe
NEe Electronics Inc.
Description
The RA78K2 relocatable assembler package converts
symbolic source code for the p.PD782XX eight-bit singlechip microcomputers into executable absolute address
object code. The RA78K2 relocatable assembler package
consists of four separate programs: assembler
(RA78K2), linker (LK78K2), locater (LC78K2), and librarian (LB78K2).
RA78K2 translates a symbolic source module into a
relocatable object module. The assembler verifies that
each instruction assembled is valid for the target microcomputer specified at assembly time and produces a
listing file and a relocatable object module.
LK78K2 combines multiple relocatable object modules
and library modules and converts them into a single
relocatable object module. LC78K2 converts a relocatable object module with no external references into an
ASCII hexadecimal format absolute object code file.
LB78K2 allows commonly used relocatable object modules to be stored in one file and linked into multiple
programs, greatly increasing programming efficiency.
When a library file is Included In the Input ofthe linker, the
linker extraCts from the library file only those modules
required to resolve external references and links them
with the other modules.
Features
[J
Absolute address object code output
User selectable and directable output files
Macro definitions
Branch optimization
Conditional assembly
Extensive error reporting
Powerful librarian
[J
RlInA IInriAr MS-DOSQl) Anri VAXQl)NMSQl) nnArAtinn
[J
[J
<
[J
[J
[J
[J
systems
Ms.DOS Is a registered trademark.of Microsoft Corporation.
V/JIX and VMS are registered trademarks of Digital Equipment
Corporation.
50191
RA7eK2
Relocatable Assembler PaCkage
for the pPD782XX Series
Ordering Information
Put Number
System
eeacrlptlon
RA78K2'[)52
MS-DOS
5·1/4 Inch doubl.denslty floppy
diskette
RA78K2·WT1
V/llXlVMS
9-treck 1600 BPI magnetic tape
Program Syntax
An RA78K2 source module consists of a series of code,
data, or bit segments. Each segment consists of statements composed of up to four fields: symbol, mnemonic,
operand, and comment.
The symbol field may contain a label whose value Is the
Instruction or data address or a name which represents
an Instruction address, data addresS; or constant. The
mnemonic field may contain an instruction or assembler
directive. The operand field contains the data or expression for the specified instruction or directive. The comment field allows explanatory comments to be added to
a program.
Character constants are translated into seven-bit ASCII
codes. Numeric constants may be specified as binary.
octal, decimal, or hexadecimal. Arithmetic expressions
may Include the operators +, -, *, /, MOD, OR, AND,
NOT, XOR, EO, NE, LT, LE, GT, GE, SHR, SHL, LO'll(
HIGH, ., ( ), and character constants.
Macro Definition
RA78K2 allows the definition of macro code sequences
with up to five parameters, LOCAL symbols, and special
repeated code sequences. The macro code sequence is
different than a subroutine call in that the invocation of a
macro in the source code results in the direct replacement of the macro call with the defined code sequence.
Assembler Directives
RsSerTIOler ciireClives give immuciions to ine assemoler
but are not translated into machine code during assembly. Basic assembler directives include: storage definition and allocation directives (DB, rm. OS, OBIT); symbol directives (EOU, SET); and the location counter
control directive ORG. Program control directives include: segment directives (CSEG, DSEG, BSEG, ENDS);
linkage directives (NAME, PUBLIC, EXTRN, EXTBIT);
macro directives (MACRO, LOCAL, REPT, IRP, EXITM,
ENDM); automatic BR instruction directive (BR); and
assembly termination directive (END).
NEe
RA78K2
Assembler Controls
TheRA78K2 assembler (figure 1) has two types of controis. The primary controls, which are specified in the
assembler command line or at the beginning of the
source module, are as follows:
•
•
•
•
•
•
Processor selection
Output object creation selection
Output list file selection
listing format controls
Optimization selection
V\brk file drive specification
The general controls, specified in the source program,
are as follows:
• Inclusion of other source files
• Page eject
• Generation/suppression of listing
• Listing titles
• Conditional assembly controls
The listing file may contain the complete assembly
listing or only lines with errors, and a symbol or crossreference table. The symbol table shows all defined
symbols in alphabetical order, their types, attributes,
and the values Initially assigned to them.
The cross-reference table contains all defined symbols
and the numbers of all statements that refer to them. The
object file contains the relocatable object module. The
format of this module is an NEC proprietary relocatable
object module format.
If the optimization option is chosen, the assembler will
generate the most efficient code by converting, wherever possible, three-byte absolute branches into twobyte relative branches.
Figure 1. RelOClltable Assembler Functional
Diagram
System
Console
Source
Module
File
Include
File
~
~
RA78K2
Relocatable
Assembler
~
1-
~
~
Relocatable
Object
Module
File
Assembler
List File
Temporary
Work Files
49NA.,5B2A
Linker
The LK78K2 linker (figure 2) combines several relocatable object modules, resolving PUBLIC/EXTRN references between modules, to create a relocatable output
module. This output module contains both relocatable
object code and symbol information. The linker will also
search library files for required modules to resolve external references. The linker controls for LK78K2 can be
specified in either the command line or in a parameter
file. The programmer can specify the date, the absolute
load module name, and control the creation of a list file
containing a link map.
Figure 2. Unker Functional Diagram
Library
File 1
...
Relocalable
Object
Module
File 1
Library
Filen
...
I
System
Console
Relocatable
Object
Module
File n
I
~
LK78K2
Linker
Relocatable
Object
Module
File
I--
Temporary
Work Files
Linker
List File
49NR-5S4A
9-64
NEe
RA78K2
Locater
Emulator Controller Program
The LC78K2 locater (figure 3), outputs two files: an
absolute load file in an expanded hexadecimal format
seven-bit ASCII, which can be downloaded to a PROM
programmer; and a symbol file for the symbolic debugger. The programmer can specify the starting address
and order for code/data/stack segments, and protect
areas of memory from being assigned. The programmer
can specify that a map file with symbol tables be
created.
Absolute object files produced by the RA78K2 relocatable assembler package can be debugged by using the
appropriate NEC stand-alone in-circuit emulator. NEC
emulator controller programs allows communication
with the emulator through an RS-232C serial line. An
emulator controller program can run on the IBM P~,
PC/XTI!!, or PC ATI!! under MS-DOS and is provided with
the in-circuit emulator at no extra charge.
These emulator controller programs provide the following features:
Figure 3. LOCIIfer Functlolllli Dlsgrllm
•
•
•
•
•
•
•
•
Relocatable
Object
Module
File
*
LC78K2
Locater
~
Symbol
File for
Debugger
B
Map File
Uploading and downloading of object and symbol files
Symbolic debugging capability
Complete emulator control from host console
On-line help facilities
Macro command file capabilities
Host system directory and file display
Disk storage of debug session
Storage of last 20 commands for recall
LIcense Agreement
RA78K2 is sold under terms of a license agreement,
which is incl uded with the assembler. The accompanying
card must be completed and returned to NEC Electronics Inc. to register the license. Software updates are
provided free to registered users.
~
Hexadecimal
Object
Code File
Documentation
* With no external references
49NR-5S6A
Librarian
The LB78K2 librarian creates and maintains library files
containing relocatable object modules. This reduces the
number of files to be linked together by storing several
modules in a single file. This provides an easy way to link
frequently used modules into programs. Modules can be
01"41"10.1"1 +n ,",01.0.+.01'1 f ..,,1"'n "',. ...01"'1010,..0.1'4 \A,;+h;n a IIh,.oru fila
-------------. -- --1------- ----- .. -----------"
the contents of the library file can be listed.
I"U'
-------~--.
Operating Environment
The NEC RA78K2 package can run under a variety of
operating systems. A version is available to run on a
MS-DOS system with one or more disk drives and at
least 128K of system memory. Another version is available to run on a Digital Equipment Corporation VAX
computer under the VMS (Version 4.1 or later) operating
system.
For further information on source program formats,
assembler operation, and actual program examples,
NEC Electronics Inc. provides the following documentation:
• RA78K2!,PD782XX Relocatable Assembler Package
Language Manual
• RA78K2!,PD782XX Relocatable Assembler Package
Operation Manual (MS-DOS)
• RA78K2!,PD782XX Relocatable Assembler Package
Ooeration Manual NMS)
This documentation is provided with purchased copies
of the package. Additional copies may be obtained from
NEC Electronics Inc.
IBM PC, PC/XT, and PC AT are registered trademarks of International
Business Machines Corporation.
9-65
III
•
RA78K2
9-66
NEe
ttlEC
NEC Electronics Inc.
Description
The ST78K2 structured assembler preprocessor is a
companion program to the RA78K2 relocatable assembler for the NEC /-IPD782XX series of microcomputers.
ST78K2 converts a source code file containing structured assembly statements into a pure assembly language source file, which can then be assembled with
RA78K2.
ST78K2 converts a structured assembly statement into
one or more /-IPD782XX assembly language instructions
which perform the desired operation. Since ST78K2 only
converts the structured assembly statements and does
not convert /-IPD782XX assembly language instructions,
a structured source program can include a combination
of ILPD782XX structured assembly statements and assembly language.
ST78K2 enables the assembly language programmer to
use some of the structures and syntax of higher-level
languages such as the C language. This improves program readability and reliability, and increases programmer productivity.
Features
o Control structures for conditions, looping, and
switch-case
o Preprocessor directives for conditional code
generation
DC-like representation of comparison operations
DC-like representation of assignment/arithmetic
operations
o Increment and decrement operators
o Allow use of allILPD782XX mnemonics, registers,
and features
o Runs under MS-DOS® and VAX®NMS® operating
c.'.~+ol"\."""~
-J -~- . .. -
Ordering Information
The ST78K2 structured assembler preprocessor is included in the following software package at no cost:
ST78K2
Structured Assembler Preprocessor
for the pPD782XX Series
Structured Assembler Preprocessor Functional
Diagram
RA78K2
I'PD782XX
Relocatable
Assembler
49NR-588A
Summary Of Structured Language
A line of source code for ST78K2 contains either a
structured assembly statement or a /-IPD782XX assembly
language statement. ILPD782XX assembly language
statements (p,PD782XX instructions, RA78K2 directives,
or RA78K2 controls) pass through ST78K2 without
change.
Structured assembly statements consist of preprocessor
directives, assignment statements, and control statements. These statements are entered one per line, and
are terminated by a line feed character. An optional
comment may follow a semicolon at the end of the
statement; all text following a semicolon is ignored by
ST78K2.
Preprocessor directives cause ST78K2 to include or omit
oortions of code. Assianment statements cause ST78K2
to generate one or more /-IPD782XX assembly language
instructions to alter the contents of a register or variable.
Control statements cause ST78K2 to generate the necessary instructions to test conditions and change control flow based on those conditions .
• RA78K2 /-IPD782XX Relocatable Assembler Package
MS-DOS is a registered trademark of Microsoft Corporation.
VIV< and VMS are registered trademarks of Digital Equipment
Corporation.
50253
9-67
NEe
ST78K2,
.
Preprocessor Directives
Examples:
8T78K2 preprocessor directives set and test variables,
allowing conditional processing of code; include external files; and map instructions to ",PD782XX CALT table
reference instructions. Table 1 lists the preprocessor
directives and their functions.
DATA1 = B(A)
Table 1. Preprocessor Directives and Functions
Directive
Function
#define NAME value
Defines the variable NAME, set to the
supplied value.
, #ifdefABC
, < statements>
#else
< statements>
#endif
#include "filename"
#defcallt @LABEL
CALL lIabel
#endcallt
If ABC has been defined as above, or on
the command line with the -0 option, the
first set of statements is processed and
the second set ignored; If ABC has not
been defined, or defined as zero, the first
set of statements Is Ignored and the
second set is processed.
The named file is read from disk and
proC'essed as If Included In the source.
Whenever the Instruction "CALL lIabel" is
encountered In the source program, It Is
replaced by "CALLT [@LABELJ". The
label must be defined In the CALLT table.
Assignment, Increment, And Decrement
Statements
8T78K2 provides the ability to represent an assignment,
or, an Elssignment with an ,arithmetic operation, in C
language syntax:
destination < assign-op > source
The assignment operators allow either simple assignment, or the combination of an assignment with an
arithmetic operation on the source and destination.
Examples:
;Move contents of B register to A
A = B
A + = [HL] ;Add contents of memory at HL to A,
;store in A
,
'
Wl'\erean assignment requires an intermediate register
tO"hold the value being assigned, the register is designated by naming it in parentheses following the assignment, operation. ,
9-68
BC & = HL (XA)
"~
;8tore contents of B into memory at
;DATA 1, using A as temporary
;storage
;and BC with HL, store in BC,
;use XA as teinp
The increment and decrement operators (+
operate on a single operand.
+
and -)
Table 2 lists the assignment operators with examples
and functions.
Table 2. .ignment Operators with ExlImples
and Functions "
Operator
Example
Function
A=B
A-B
<->
A < - >B
Contents of A and B are exchanged
+=
A += B
A-A+B
A-= B
A--A,-B
*=
AX*= B
AX-AX*B
1=
AX/= C
AX-AX/C
&=
A&= B
A- A & B Ooglcal AND)
1=
AI= B
A - A 1BOoglcal OR)
A'= B
A - A ' B Ooglcal XOR)
»=
A»=B
(CY-Ao.An-1-An, ... ,Amax-O) x B times
«=
A«=B
(CY-A max,An +1-An, .. .Ao-O) x B times
++
A++
A-A+1
A-
A-A-1
Control Statements
Control statements ,allow conditions to be tested. Based
on the results of the test, blocks of code are allowed to
be executed or skipped. Reserved words in the control
statement define the start and end of bloCks of code; 'and
expressions to be evaluated.
NEe
ST78K2
Table 5. Expressions and Examples
Example:
if (A = = [HLJ)
PS = B (A)
A = [HL]
;The condition is tested
;If A equals the content of memory
;at HL, this code is executed
else
A + = [HL]
A- = B
PS = A
;Otherwise this code is executed
endif
Table 3 shows the control statements and their functions.
Table 3. Control Statement Directives
Expression
Example
Primary
(A)
Term
(A <= B)
Term && Term
((AC)) (logical AND)
Term II Term
( (A= = C) II (A= = B) ) (logicaIOR)
A primary value for a variable expression is a register
name or defined symbol. A term consists of two primary
values compared with a binary operator. Table 6 lists the
supported binary operators and their meanings.
Table 6. Binary Operators
Binary Operator
Meaning
Control Statement
Function
if - elseif - else - end if
Test variable expressions
1=
Not Equal
iLbit - elseiLbit - else - endif
Test bit expressions
>
Greater Than
switch - case - default - ends
Select based on variable
>
for - next
Loop, test variable
<
while - endw
Equals
<
=
Greater Than or Equal To
Less Than
=
Less Than or Equal To
repeat - until
Loop, test bit
repeat - unti Lbit
Bit expressions test individual bits of registers, ports, or
memory locations. Table 7 shows the acceptable forms
of bit expressions.
break
Exit control block
continue
Skip to top of block
Table 7. Bit Expressions and Examples
goto LABEL
Branch to label
Bit Expression
Variable And Bit Expressions
Variable expressions for tests consist of a single value,
comparison between two variables, or a logical combination of comparisons. Bit expressions test individual
bits. Table 4 shows examples of comparisons.
Table 4. Examples of Variable Expression
Comparisons
Example
BiLprimary
(P2.1 )
IBiLprimary
(ICY)
BiLprimary && BiLprimary
(A.O && CY)
BiLprimary II BiLprimary
(P2.211 CY)
A BiLprimary can be either a reserved word bit identifier, such as a bit of a register or port (P2.1, Cy), or a bit
definition symbol (SBO EQU P2.2).
ST78K2 Operation And Controls
Comparison
Meaning
if ( A \
True if A is non-zero
if (A < B)
True if A is less than B
ST7RK? i~ invoked bv soecifvino the name of the source
file, followed by optional controls.
if ((A < B) && (A > C))
True if A is less than B and greater than C
Example:
iLbit ( P3.2 )
True if bit 2 of P3 is 1
iLbit (IP3.2)
True if bit 2 of P3 is 0
The allowable expressions using variables are shown in
table S.
C>ST78K2 ABC.SRC -DXYZ
=
3
ST78K2 reads the specified source file and produces an
output assembly language file, which can be input to
RA78K2. The output file contains all lines provided in the
input source file, plus those generated by ST78K2. Lines
containing no statements for the structured assembler
are passed through unchanged. Lines with structured
9-69
tVEC
ST78K2
assembly statements are placed in the output preceded
by a semicolon. RA78K2 treats these lines as comments.
These commented lines are then followed by the code
generated by ST78K2.
The controls for ST78K2 are specified in the preprocessor command iine or in a parameter file invoked in the
command line. Table 8 lists the ST78K2 preprocessor
controls and functions.
Table 8. ST78K2 Preprocessor Controls
Control
Function
-OIliename
Specify name of output assembly source file
-Ffllename
Specify name of parameter file to be read
-Efilename
Specify name of error listing file
-Dsymbol[=value]
Define a symbol (like #define hi code)
-I[d:][directory]
Define path for include file
-WTn1,n2,n3
Define TAB settings for generated code
-SCcharacter
Defines word symbol last character
The -0 option allows the name of the output file to be
specified. If not specified, the output file name defaults
to. the name of the input source file with the extension
.ASM.
The -F option allows a parameter file to be specified,
which will be read by ST78K2. This parameter file can
contain a list of controls to be given to ST78K2, instead
of or in addition to those specified on the command line.
The -E option specifies the name of the error listing file.
The error file contains the file name, error number,
description of error and the line containing the error. If
the -E option is not specified, the error file name defaults
to the name of the input source file with the extension
.ESl:
The -0 control .allows a symbol to be defined on the
command line, with an optional value provided. If a
symbol is defined but no value specified, the value
defaults to 1. If the source file contains a. #define
directive which specifies a variable with the same name
as the -0 control, the value on the command line will
override the value in the #define directive.
9-70
The -I control specifies a drive or directory other than the
current drive and directory to search for include files.
The -WT control specifies the number of TAB characters
to insert before labels, instruction mnernonics, and instruction operands generated by ST78K2. This allows
clear separation of assembly language instructions
coded in the source file from those generated by
ST78K2.
The -SCcharacter control specifies the character used
as the last character in a word symbol. The character
must be a letter of the alphabet or the @, _ or ? This
allows ST78K2 to distingush between word and byte
operations. Symbols which end in this character are
treated as word symbols and will generate a word
operation (ie. MOVW). If the -SC option is not specified,
ST78K2 assumes that a symbol ending with the character "P" or "p" is a word symbol.
Documentation
For further information on source program formats,
preprocessor operation, and actual program examples,
NEC Electronics Inc. provides the following documentation.
• St78K2/ST78K3 "PD782xx/"P0783xx Structured Assembler Preprocessor User's Manual.
This documentation is provided with purchased copies
of the RA78K2 !-'P0782xx relocatable assembler package. Additional copies can be obtained from NEC Electronics Inc.
NEe
DDK·78310A
Evaluation Board
for the pPD78310A
NEe Electronics Inc.
Description
The DDK-78310A is an evaluation board for the NEC
I4PD78310A eight/sixteen-bit, single-chip microcomputer. The DDK-78310A provides maximum flexibility
when evaluating and designing with the I4PD78310A. The
DDK-78310A features 32K bytes of ROM, 32K bytes of
RAM, RS-232C communication port, and a powerful
monitor program. The DDK-78310A board is provided on
an IBM PCI!> compatible card and includes a playpen
area for building application specific hardware.
A copy of RA78K3, the I4PD7831X/I4PD7832X relocatable
assembler for use on an IBM PCI!>, PC/XTI!>, PC ATiI>, or
compatible host computer, is shipped with each DDK78310A to allow development of code for evaluation
purposes. Also included with the DDK-7831OA is a emulator controller program for the IBM PC, a small demonstration program in ROM, the source code for the monitor, and a complete set of documentation. This total
package provides a fast, efficient means for evaluating
the capabilities of the I4PD78310A for the user's
application.
IBM PC, PCIXT, and PC AT are registered trademarks of International
Business Machines Corporation.
Features
o I4PD78310A evaluation board with power supply
o On-board memory:
- ROM: 32K-byte
- RAM: 32K-byte
o Powerful on-board debug monitor:
-
Real-time and single-step operation
Display/change memory and internal registers
Disassembler
Multiple software breakpoints
User program download capability
o RS-232C serial interface for terminal or host
computer
o Playpen area for user circuitry
o IBM PC card form factor
o RA78K3I4PD7831X/I4PD7832X relocatable assembler
package
o Host control software for IBM PC, PC/XT, PC/AT, or
compatibles
o Demonstration program in ROM
o Source code for DDK-78310A monitor included
Ordering Information
Part Number
Description
DDK-78310A
IIPD78310A evaluation board
DDK-78310A Evaluation Board
9-71
t-IEC
DDK·78310A
Hardware Description
The DDK-78310A features 64K bytes of on-board memory. The lower 32K bytes are dedicated to ROM and
include a powerful monitor program and user area. The
upper 32K bytes are dedicated to RAM and include a user
area for program downloading (7DFFH bytes), a monitor
work area (7CFH bytes), and the internal RAM area of the
ILPD78310A (1 F FH bytes).
The ILPD78310A serial port is connected by an RS-232C
driver/receiver to a DB25 pin connector. A reset switch
allows the DDK-78310A to return to the power-up state
without losing the contents ofthe external RAM. An NMI
switch returns control from a user program to the monitor while saving the user's state.
An AC/DC converter provides power for the DDK-78310A
in the stand-alone mode. The DDK-78310A can also
receive power directly from the IBM PC bus.
program can be downloaded into user RAM and executed either in real-time with or without breakpoints or
executed one instruction at a time. During singlestepping, the registers, program counter, and the next
instruction to be executed are displayed.
The DDK-7831OA has eight address breakpoints. The
user can set up to seven of these prior to program
execution. The eighth breakpoint is reserved for use in
the GO command line. The monitor sets a breakpoint by
substituting a software break instruction (opcode 5EH)
for an instruction in the user's program.
Additional commands are available to:
•
•
•
•
•
Software Description
The DDK-78310A has a powerful interactive monitor to
facilitate software design using the ILPD7831OA. A user
Display, fill, change, or move memory
Display or change registers
Disassemble memory
Display the command list
Place the interrupt vector and call table areas at OH or
8000H
Table 1 contains a complete list of the DDK-78310A
monitor commands and their syntax.
Block Diagram
A
As-A14
EPROM
OH-7FFFH
Address
Latch
Ao- A 7
ADo-AD7
U
r-
'---
RAM
8000H-FDFFH t---
IlPD78310A
-WR
-
RD
A15
Control
Logic
RFSH
TxD
RxD
R8-232C
Interface
49NR-6528
9-72
NEe
DDK·78310A
Emulator Controller Program
Table 1. Command Ust
Command
Function
Syntax
?/H
Show this menu of commands
?
B
Show or set breakpoints
B[bp,addr)
C
Change memory byte
C[addr)[,val)
D
Display memory
D[addr)[,addr)
F
Fill memory
Faddr,addr,val
G
Go (to breakpoint)
Gladdr)[,addr)
Move interrupt vectors to/from
8000H
Absolute address object files produced by the RA78K3
relocatable assembler package can be downloaded to
the DDK-7831OA using the NEC emulator controller program, supplied with the DDK-78310A. This controller
program allows files to be downloaded from an IBM PC
or compatible to the DDK-7831OA board. In addition to
downloading files, the NEC emulator controller program
provides these additional capabilities:
K
Kill breakpoint(s)
K[bp)
L
Load a HEX file on to the DDK78310A
L[addr)
•
•
•
•
Complete DDK-78310A control from host console
On-line help facilities
Host system directory and file display
Storage of debug session on disk
M
Move a block of memory
Maddr,addr,addr
License Agreement
R
Display/change registers
R[reg)
T
Trace execution
T[addr)
U
Unassemble a block of memory
U[addr)[,addr)
RA78K3 is provided under the terms of a license agreement included with the DDK-78310A board. The accompanying card must be completed and returned to NEC
Electronics Inc. to register the license. Software updates
are provided to registered users.
Notes:
= 16-bit address in hexadecimal format.
= breakpoint number, 1-7.
reg = general purpose or control register mnemonic.
val = eight-bit value in hexadecimal notation.
[) = optional parameter.
(1) addr
(2) bp
Documentation
(3)
For further information on the DDK-7831OA evaluation
board, NEC Electronics Inc. provides the following
manual:
(4)
(5)
RA78K3 Relocatable Assembler Package
The RA78K3 relocatable assembler package converts
symbolic source code for the JLPD7831X and JLPD7832X
eight/sixteen-bit, single-chip microcomputers into executable absolute address object code. A copy of RA 78K3
is included with the DDK-7831OA to use with an IBM PC,
PC/XT, PC AT, or compatible. Evaluation programs for
the JLPD78310A can be written easily with this software.
• DDK-78310A JLPD78310A Evaluation Board User's
Manual
This manual is provided with the board. Additional copies can be obtained from NEC Electronics Inc.
9-73
DDK-78310A
9-74
NEe
!\fEe
NEe Electronics Inc.
EB·78320
Evaluation Board
for the pPD78320
Description
CJ
Four parallel or sequential breakpoints
The EB-7832o. is an evaluation board for the NEC
~PD7832o. eight-bit, single-chip microcomputer. The EB78320. provides a simple way to evaluate the capabilities
of the ~PD7832o. in an application without having to
build a prototype. If it is necessary to connect the
EB-7832o. directly to a target system, the IE-78320 emulator probes can be purchased separately.
CJ
Display/change memory and general registers
The EB-7832o. features 32K bytes of static RAM for
evaluation programs, an RS-232C communication port,
and a powerful on-board monitor. Evaluation programs
can be downloaded from a host computer or created
directly on the board using the line assembler. Programs
can be executed in real-time with or without breakpoints
or one instruction at a time. Commands are available to
display or change memory, general or special function
registers, and to disassemble code.
CJ
Display/change special function registers
CJ
User program upload/download capability
CJ
Symbolic debugging support
CJ
Line assembler and disassembler
CJ
RS-232C serial interface for host computer
CJ
Host control software for IBM PC, PC/XT, PC AT, or
compatibles
CJ
Connection to a target system using in-circuit
emulator probes
IBM PC, PCIXT and PC AT are registered trademarks of International
Business Machines Corporation.
Ordering Information
A controller program controls the EB-7832o. directly from
the console of an IBM PC@, PC/XT@, PC AT@, or compatible host computer using an RS-232C serial interface.
Part Number
Description
EB-78320-PC
I4PD78320 evaluation board OBM PC Based)
EP-78320GJ-R
Emulator probe for 74-pin QFP (optlonaQ
Features
EP-78320l-R
Emulator probe for 5S-pln PLCC package
(optionaQ
CJ ~PD7832o.
evaluation board
CJ
32K bytes of static RAM
CJ
Real-time and single-step execution
EB-78320
9-75
NEe
EB·78320
Block Diagram
portsO'2,t:==============================================================================~~
3, y,8r
Ae-A15 r~======Ir==================A=dd=r=es=s=B=U:S========================~~~:;':-~
Buffer 1-----1'~1
PAO-PAy
",PDY1P301
t---" Manager
Emulator
.---~/1
IlPD78320
Turbo Access
Probe
PBO-PBY~======~~~==================================::"l
Address/Data Bus
Buffer
49NR-6568
9-76
ttlEC
Hardware Description
The EB-78320 features 32K bytes of on-board static
RAM. It can be used without a target system or can be
directly connected to a target system using one of the
IE-78320 emulation probes. When the EB-78320 is used
without a target system, 28K bytes of RAM are available
for downloading programs; the on-board monitor uses
the remaining 4K bytes as a work area. When the EB78320 is connected to a target system, 52K bytes of the
,",PD78320's 64K-byte code space are mapped to the
target system.
The EB-78320 can be used to evaluate the instruction
execution speed of the ,",PD78322's internal ROM by
installing a ,",PD71 P301 turbo access manager in the
footprint on the board. When using the ,",PD71 P301, the
evaluation program is placed in the EPROM of the
,",PD71P301; the emulation function of the EB-78320
board is not available.
The serial port for the host computer connection consists of a ,",PD71051 USART, an RS-232C driver/receiver
and a DB25 pin connector. A reset switch returns the
EB-78320 to the power-up state. An ac/dc converter is
shipped with each EB-78320 board for convenience. The
EB-78320 can also be powered from batteries using the
enclosed battery holder.
Emulation
The EB-78320 allows the following methods of program
emulation: real-time program execution with or without
breakpoints; real-time program execution for a specified
number of instructions; single-step emulation for a specified number of instructions or until a register condition
is satisfied. The registers, stack pointer, program status
word, and program counter are displayed following termination of real-time emulation or during single-step
emulation. The EB-78320 enters the single-step mode
following a real-time emulation break. When the enter
key is pressed during single-step emulation, the next
instruction is executed, and the executed address, instruction mnemonic and above data are displayed.
EB·78320
address breakpoint. If anyone of the four parallel breakpoints is satisfied, a break in emulation occurs. For a
sequential breakpoint, each address must be encountered in the specified order before a break in emulation
can occur. These breakpoints are set by substituting a
software break instruction for an instruction in the user's
program.
Software Description
The EB-78320 is controlled from the console of an IBM
PC, PC/XT, PC AT, or compatible computer with an
RS-232C interface using the enclosed emulator controller program. This program provides commands for
downloading and uploading object code and symbol
files to and from the EB-78320. A line assembler and
disassembler avoid debugging in machine Code. The
symbolic debugging commands allow the use of labels
instead of absolute addresses. Full data manipulation
capability is available with the change register/memory
commands. Initialization commands choose a base
number and register mnemonics.
The EB-78320 program also has macro command file
capability, so the user can execute a defined set of
commands automatically. The on-line help facility, history command, and ability to store the console display
on disk or send ino a printer ease debugging tasks.
Table 1 lists the available EB-78320 commands. These
are a subset of the IE-78320 commands.
Table 1. Command Ust
Command Function
ASM
Une assemble command
BRS
Sets instruction address breakpoints
COM
Creates command file
DAS
Disassemble command
DIR
Displays disk directory
EXT
Terminates EB-78320 controller program operation
HIS
Displays last twenty commands
Emulation Accuracy
When the emulation probe is connected to a target
system, ports 0, 2, 3, 7, and 8, the watchdog timer output
and the A/D converter related signals are identical to the
device. However, all other signals differ from the actual
device because of buffering and control gating.
Breakpoint Capabilities
The EB-78320 has four parallel instruction address
breakpoints or up to a four-level sequential instruction
LOD
Loads object code and symbol files
LST
Sends console display to disk or printer
MAP
Dlslays memory map
MAT
Evaluates arithmetic expression
MDR
Dlsplaystmodlfles "PD78320 mode registers
MEM
Memory manipulation command
REG
Displays/modifies "PD78320 registers
RES
Resets only the "PD78320
9-77
EB·78320
Table 1. Command Usl (conI)
Command Function
RUN
Executes programs In slngle-step mode or In real-time
with options for break conditions
SAY
Saves contents of memory onlo disk
SPR
Displays/modifies IIPD78320 special function registers
STR
Automatically executes command string file
SUF
Base number specification (hex, octal, binary,
declmaQ
SYM
Adds/deleleS/dlsplays/changeS/ioads/saves symbols
VRY
Compares contents of an object file with memory
Equipment Supplied
The EB-78320-PC package consists of the following:
• EB-78320 evaluation board
• EB-78320 user's manual
• .System disk for IBM PC
• AC/DC converter power supply
• Battery holder and mounting hardware
• Warranty policy and registration card
Documentation
For further information on EB-78320 operation, NEC
Electronics Inc. provides the following manual with the
board:
• EB-78320 ~PD78320 Evaluation Board User's Manual
Additional copies may be obtained from NEC
Electronics Inc.
9-78
NEe
NEe
IE-78310A
In-CI reult Emulator
NEe Electronics Inc.
Description
The IE-7831OA is an in-circuit emulator providing both
hardware emulation and software debugging capabilities for the NEC "PD78310A and "PD78312A single-chip
microcomputers. Real-time and single-step emulation, in
conjunction with sophisticated memory mapping features, breakpoints, and trace capabilities, create a powerful debugging environment. A line. assembler/disassembler, full register and memory control, symbolic
debugging, and complete upload/download capabilities
simplify the task of debugging hardware and software.
Features
C
C
C
C
Real-time and single-step emulation capability
User-specified breakpoints
- logical OR of up to four sets of break conditions
Opcode fetch count
.
External sense clips condition
Emulation time
Logical AND of addresses, data values, CPU
controls, and loop count
Sophisticated trace capabilities
- Instruction, frame, or macro service display
- 2K x 44-bit trace buffer
- Address, control, data, and port trace features
Powerful memory mapping feature .
- 64K bytes of RAM mappable in 256-byte blocks
C
C
C
C
C
C
- Up to 16K bytes of high-speed internal RAM for
"PD78312A ROM emulation
Une assembler/disassembler
Symbolic debugging
- 2,000 symbols available
-IEEE-796 bus memory expansion slot for 32K
additional symbols
CMOS latch-up warning and protection
Eight external sense clips
SeH-dlagnostic command
Stand-alone mode or system mode with host control
program
Ordering Information
Part Humber
Delcrlptlon
1E-7831OA-R
In-clrcult emulator for !,PD78310AJ!,PD78312A
EP-78310CW
Emulator probe for 54·pln lihrlnk DIP
package(shlpped wHh 1E-78310A)
EP-78310GQ
Emulator probe for 54·pln QUIP
package(shlpped with 1E-78310A)
EP-78310L
Emulator probe for 58-pin· PLeC package
EP-78310GF
Emulator probe for 54-pin QFP package
(optlona~
(optlona~
IE·7831OA wlth.Emulator Probe
9-79
NEe
IE·78310A
Hardware Description
Emulation
As the IE-7831OA block diagram shows, the IE-78310A
hardware consists of a control/trace module, driver module, target probe, external sense clips, and interconnecting system bus. The control/trace module includes the
trace control unit, emulation memory unit, selfdiagnostic unit, break control unit, and latch-up alarm
unit. This module also houses the emulation CPU, which
is directly connected to the target emulation probe. The
driver module houses the serial interface circuit, control
CPU, trace RAM, and system memory.
Memory Mapping
The IE-78310A allows the following methods of program
emulation: real-time program execution with or without
breakpoints; real-time program execution for a specified
number of instructions; and single-step emulation for a
specified number of instructions or until a register conditionis satisfied. Following termination of real-time
emulation or during single-step emulation, the registers,
stack pointer, program status word, and program
counter are displayed. Following a real-time emulation
break, the IE-78310A enters the single-step mode. Each
time the space bar is pressed during Single-step emulation, the next smallest group of instructions Is executed
and the above data is displayed.
The IE-78310A has a sophisticated memory mapping
scheme which allows access of up t064K bytes of
internal memory, mappable in 256-byte units. The map
command allocates the memory space of the emulation
CPU either to the user system or tothe IE system. Even
if development of the target system is not complete,
software debugging is still possible by using this internal RAM in place of the target system RAM. In addition to
this emulation memory, the IE-78310A has an alternate
high-speed memory for real-time emulation of the
"PD78312A internal ROM. 0, 4K, 8K, or 16K bytes of the
high speed memory can be selected as internal ROM.
Once a breakpoint is reached during emulation, the next
few instructions are executed before breaking actually
occurs. This Is known as Slip. The exact number of
instructions Slipped depends on the instructions in the
prefetch queue and whether the emulation chip is accessing internal ROM or external memory. Ports 0, 2, 3,
the AID, and the refresh signals are identical to the
"PD78310AI"PD78312A. However, other signals differ
from the actual device due to buffering and control
gating.
Emulation Accuracy
Block Diagram
Emulator Probe
IE-78310A
RS-232C
Host
:.:.:.::::::::::~ ::::::::::::::~:::::::.:.:.y.:,:""N···
Control I
Trace
Module
Target Probe
IE System Bus
1........I
Driver
Module
\.
8 External Sense Clips
49NR-581B
9-80
NEe
IE·78310A
Self-Diagnostics
Utilities
A self-diagnostic command monitors the IE-7831OA for
error-free operation. It checks alternate RAM, user RAM,
address/data bus, the 64-pin probe, the emulation chip
(including all port lines), and both the EANpp and reset
lines.
The upload/download commands provide easy loading
and saving of hex files to and from a host computer. The
on-board assembler/disassembler allows the user to
avoid programming in machine code. The symbolic
debugging commands allow the use of labels instead of
absolute addresses. Full data manipulation capability is
available for the user with the change register/memory
commands. Initialization commands allow the user to
choose a clock source and a base number, and to define
the system memory map.
Breakpoint Capabilities
The break function can be divided into three types: break
register (physical and logical) breaks, command breaks,
and fail-safe breaks. The user sets physical break registers to cause emulation breaks upon address, data,
status or loop count; instruction count; timer (1 to
65,535 ms range) or matching a set of conditions on the
eight external sense clips. Combinations of these physical registers can then be set to the logical break registers and executed when running a break command.
Command breaks are set in the emulation command and
can cause emulation breaks after a specified number of
steps are executed or a register condition is satisfied.
Fail-safe break conditions occur unconditionally and
include manual break (ESC key), non-mapped memory
break, write-protected memory break, and reset break.
Trace Capabilities
The IE-78310A has a 2K x 44-blt trace RAM for storing
emulation data from each machine cycle. Given a userspecified range, trace can be performed upon address,
data, frame status Signals (RD, WR, MSRD, MSWR, OP,
M1), ports PO to P5, and the eight external sense clips
for up to 2,047 machine cycles. There are three types of
trace displays: frame mode, macro service mode, and
instruction mode. In frame mode display, the frame
number and type, address and data information and port
and external sense clip status are displayed for each
frame in the order In which they are traced. In instruction
mode, the executed instructions are displayed with their
frame number, instruction address, mnemonics and operands. In macro service mode, reads/writes of the
macro service routines are added into the instruction
mode display.
System Mode
The IE-78310A can be connected to an IBM P~,
PC/XT$, PC ATe, or MD-086FD-10 by an. RS232C part
and operated in system mode. By using the accompanying control software, the debugging capabilities of the
IE-78310A-R are greatly increased. It has a macro command file capability, allowing the user to execute a
defined set of commands automatically. The on-line help
facility, the history command, and the ability to store the
console display on disk ease debugging tasks. The
uploading/downloading capability can be utilized to upload and download both object code and symbol information. Other advantages are a verify command that
compares memory to hex files, an alter symbol command, and a termination command for exiting to the
operating system.
Table 1 lists commands available for both the standalone and system modes of the IE-78310A Commands
listed in table 2 supplement table 1, but can only be used
in the system mode.
IBM PC, PC/XT, and PC AT are registered trademarks of International
Business Machines Corporation.
CMOS Protection
The latch-up alarm circuit is activated when any CMOS
IC in the driver module is in danger of being damaged by
improper voltage levels on the pins. A protection circuit
isolates the power supply to CMOS ICs and the message
"emulation CPU latchup I" is displayed.
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IE·78310A
Table 1. Stand-Alone and System Mode
COtnIIIIInds
Command Function
ASM
Une assemble command
BR?
ChangeS/displays breakpoint register used for
stopping reel-time emulation
ClK
Clock command (Internal or external)
DAS
Disassemble command
DIG
Self-dlagnostlc command
lOD
Loads hex format file Into program memory
MAP
Memory mapping (64K bytes are accessible)
MDR
DisplayS/modifies mode registers of emulator CPU
MEM
Memory manipulation command
MOD
Sets channel two mode setting
MOV
Moves memory content to different mapping area
REG
DisplayS/modifies registers of emulator CPU
RES
Resets IE-78310A and/or emulator CPU
RUN
Commences execution of emulator CPU In real-time
with options for break conditions
• Target probe unit for 64-pin QUIP socket
(EP-78310GQ)
• External sense clips
• IE-78310A-R user's manuals
• System disk for MD-086 series
• System disk for IBM PC
• AC power cable
• AC ground adapter
• Ground cable
• Spare fuse
• RS-232C interface cable
• Two 16-pin component carriers
• Warranty policy and registration card
Basic Specifications
• Weight: 10.5 kg
• External dimensions: length, 395 mm; width, 291 mm;
height, 217 mm
• Power consumption: 100 V AC, 50/60 Hz, 5 A
SAV
Saves contents of hex memory onto disk
Environmental Characteristics
SPR
Displays/modifies special registers of emulator CPU
SUF
Base number specification (hex, octal, binary,
declmaQ
• Operating temperature range: 10 to + 40°C
• Storage temperature range: -20 to + 45°C
• Ambient humidity range: 10 to 90% relative humidity
SYM
Clears, displays, or chimges a symbol
TR?
ChangeS/displays trace conditions for either real-time
or single-step emulation
VFf(
Compares memory and hex files
Table 2. System Mode Only Commands
Command Function
COM
Creates command file
DIR
Displays filenames
EXT
Terminates IE-78310A controller program operation
HIS
Displays last twenty commands
HLP
Displays command format
lST
Stores console display on disk
STR
Automatically executes macro command file
SYM
loads and saves symbol file
Equipment Supplied
The IE-78310A-R package consists of the following:
• IE-78310A housing
• Target probe cable
• Target probe unit for 64-pin shrink DIP socket
(EP-78310CW)
9-82
Documentation
For further information on IE-78310A operation, NEC
Electronics Inc. provides the following manuals with the
in-circuit emulator:
• IE-78310A "PD7831XA In-Circuit Emulator Hardware
User's Manual
• IE-78310A "PD7831XA In-Circuit Emulator Software
User's Manual
• IE78310A Controller Manual (IBM PC Based)
• IE-78310A Sample Session (IBM PC Based)
Additional copies
Electronics Inc.
may
be
obtained
from
NEC
NEe
IE-78320
In-Circuit Emulator
NEC Electronics Inc.
Description
The IE-78320 is an in-circuit emulator providing both
hardware emulation and software debugging capabilities for the NEC I'PD78320 and I'PD78322 single-chip
microcomputers. Real-time and single-step emulation,
combined with sophisticated memory mapping features,
breakpoints and trace capabilities, create a powerful
debugging environment. A line assembler and disassembler, full register and memory control, symbolic debugging, and complete upload/download capabilities simplify the task of debugging hardware and software.
Features
o Sophisticated trace capabilities
- Traces main and internal CPU bus activity or
main bus and external sense clip activity
- 2K x 44-bit trace buffer
- Instruction, instruction with macro service, or
frame display
- Trace search capability
- Trace display before or after specified break
o Powerful memory mapping
- Up to 56K bytes of RAM for internal ROM, turbo
access manager memory, or off-chip memory
emulation
- Mappable in 8K-byte blocks
o Real-time and non-real-time emulation
o Emulation timer and instruction counter
o User-specified breakpoints
o Line assembler/disassembler
-
Logical OR of up to four sets of. break conditions
Executed instruction count
External sense clip number one condition
Parallel or sequential instruction address break
Logical AND of addresses, data values, CPU
status, loop count, and external sense clip data
for either the main or internal CPU bus
MS·DOS is a registered trademark of Microsoft Corporation.
IBM PC, PC/XT, and PC AT are registered trademarks of International
Business Machines Corporation.
o Symbolic debugging
- 7,000 symbols available
o CMOS latch-up warning and protection
o Eight external sense clips on emulator probe
o Stand-alone or system mode with host control
program
o Centronics parallel interface for optional high-speed
download
IE-78320
50281
9-83
NEe
IE·78320
Block Diagram
Emulator Probe
IE-78320-R
RS-232C
Host
"'" """"""""'.
C~:~ I
A
IE System Bus -"
J~~~~[il-.
---CLJI
_-.:.Ta:::.rge!!:::..:tP...:,;ro:,::b::,.e
Module
.J
I
8 Extemal Sense Clips
49NR-661B
Ordering Information
Emulation
Part Number
Description
IE-78320-R
In-circuit emulator for I'PD78320 and "PD78322
EP-78320L-R
Emulator probe for 68-pin PLCC package
(optionaQ
The IE-78320 allows the following methods of program
emulation: real-time program execution with or without
breakpoints; non-real-time program execution for a
specified number of instructions or until a register condition is satisfied. During non-real-time program execution, the display and trace of procedures at a nesting
level deeper than the routine from which execution was
started is optional. During non-real-time emulation, each
executed instruction is displayed with its frame number
and bus cycle status, instruction address, data, label,
mnemonic, and operands. Display of the registers is
optional and can be specified by the user.
Emulator probe for 74-pin QFP (optional)
Hardware Description
. The IE-78320 hardware consists of a control/trace modul,e, driver module, target probe, external sense clips,
and the interconnecting system bus. The control/trace
module includes the trace control unit, emulation memory unit, break control unit, and the latch-up alarm unit.
The control/trace module also houses the emulation
CPU, which is connected directly to the target emulation
probe. The driver module houses the serial and parallel
interface circuits, trace RAM, control CPU, and system
memory.
Memory Mapping
The IE-78320 incorporates a sophisticated memory
mapping scheme which allows the 64K bytes of microcomputer memory space to be mapped to internal or
external memory in 8K-byte units. Even if development of
the target system is not complete, software debugging is
possible by using internal RAM in place of the target
system RAM or ROM.
The first 56K bytes of memory space can be emulated in
the in-circuit emulator as internal on-chip ROM, turbo
access manager (p.PD71 P301) memory, off-chip memory
(RAM) or write-protected off-chip memory (ROM); it can
be mapped to the user system; it can be left unmapped.
The remaining 8K bytes of memory space excluding the
on-chip internal RAM and special function register area
can be mapped to the user system or be left unmapped.
9-84
Following termination of real-time program emulation,
the elapsed emulation time, number of instructions executed, and the registers (general registers, stack pointer,
program counter, and program status word) are displayed and the IE-78320 enters single-step emulation
mode. Following termination of non-real-time program
emulation, the IE-78320 enters the single-step emulation
mode. Each time the enter key is pressed during singlestep emulation, the next instruction is executed and its
frame number and bus cycle status, instruction address,
data, label, mnemonic, operands, and registers are displayed.
Emulation Accuracy
All port-related and A/D converter related signals are
taken directly from the emulation chip. These signals
function identically to the devices. To improve signal
quality a 100 {) resistor is inserted in series on each
port-related line. Other signals differ from the actual
device due to buffering and control gating.
NEe
IE·78320
Breakpoint Capabilities
The IE-78320 has four types of break functions: event
detection breaks, command breaks, fail-safe breaks, and
manual breaks. Event detection breaks can be set to
stop emulation on: address, data, status, external data,
or loop count for main bus activity (addresses OH to
OFDFFH and OFFDOH to OFFDFH); address, status,
external data, or loop count for CPU internal bus activity
(addresses OFEOOH to OFFCFH and OFFEOH to
OFFFFH); matching a condition on external sense clip
number one; executed instruction count; four parallel
instruction address breakpoints or up to a four-level
sequential instruction address breakpoint. Combinations of the above conditions can be specified as a break
event and enabled for real-time emulation.
Once a break event associated with main bus activity or
CPU internal bus activity is reached during emulation,
several instructions are executed before emulation is
stopped. The exact number of instructions slipped (slippage) depends on the instructions in the prefetch queue
and if the emulation CPU is accessing internal ROM or
external memory. Slippage does not occur on parallel or
sequential instruction address break events.
Command breaks can be specified on the command line
of the non-real-time emulation command. Non-real-time
emulation can be ,stopped when an internal register
condition is satisfied or a specified number of instructions have been executed.
Fail-safe break conditions oCcur unconditionally and
include a non-map access break, write protected break
and turbo access break. A non-map access break occurs
when an attempt is made to access a non-mapped
memory area or non-existing special function register
(SFR). A write-protected break occurs when an attempt
is made to write to read-only emulation memory or SFR.
A turbo access break occurs when a continuous fetch
operation is performed on any off-Chip emulation memory.
A manual break occurs when the ESC key is input during
non-real-time execution, or the STP or reset command is
.
.'
IIIJJUL UUIIIIY It::al-Lllllt:: CAt::l..oULIVII.
Trace Capabilities
The IE-78320 has a 2K x 44-bit trace RAM for storing
emulation data from each machine cycle. The addresses,
data, and CPU status of the main bus are always traced
along with either the addresses and status of the CPU
internal bus or the external sense clips as selected by
the user. There are three types of trace displays: frame
mode, instruction mode, and instruction mode with
macro service. In the frame mode display, the frame
number and type, address and data information and
external sense clip status are displayed for each frame in
the order in which they are traced. In instruction mode,
the executed instructions are displayed with their frame
number, bus cycle status, instruction address, data,
external sense clip data, label, mnemonics, and operands. In the instruction mode with macro service, macro
service reads and writes are added to the instruction
mode display.
A number of trace display options are available. These
include the display of all trace data, the display of all
frames related to branch processing and the occurrence
of an interrupt, the display of only the frames meeting the
trace data search conditions, the display of five lines
before or after the frame meeting the trace data search
condition and the display of a specified number of lines
following the detection of the specified break condition.
During real-time program execution without breakpoints, the break condition can be used to stop the
tracer a specified number of frames after the break
condition is satisfied. At tracer stop time, the trace
buffer can be viewed, new trace conditions set, and the
tracer restarted while the program continues to execute
in real-time.
CMOS Protection
The latch-up warning circuit is activated when a CMOS
latch-up condition occurs in the emulation CPU or any of
its peripheral CMOS devices. A protection circuit isolates the power supply to the emulation CPU, its peripheral CMOS devices and all TTL devices driving the
CMOS devices and the message "Emulation CPU
Latchup !" is displayed.
Utilities
The upload/download commands provide easy loading
and saving of hex files to and from a host computer. The
on-board assembler/disassembler allows the user to
avoid debugging in machine code. The symbolic debugaina commands allow the use of labels instead of absoiute addresses. Full data manipulation commands are
available for memory, the general registers, and special
function registers. Initialization commands allow the
userto choose a clock source, a base number, to specify
the serial parameters for channel two and to define the
system memory map. Other commands are available to
evaluate an arithmetic expression,to output an external
trigger signal when an specified event has occurred, and
to control an NEC PG-series PROM programmer.
9-85
NEe
IE"78320
System Mode
The IE-78320 can be connected to an IBM PCCU>, PC/XTCU>,
PC ATCU>, or PC-9OO0 series by an RS232C port and
operated in system mode. By using the accompanying
control software, the debugging capabilities of the IE78320 are greatly increased. The controller program has
a macro .command file-capability, allowing the user to
execute a defined set of commands automatically. The
on-line help facility, the history command display, and
the ability to send the console display to a printer or to
the disk ease debugging tasks. The uploading and downloading capability can be utilized to upload and download both object code and symbol information.
MS-DOSCU> programs can be executed without terminating the controller program. Other advantages are a verify
command that compares memory to hex files, an alter
symbol command, and a termination command for exitingto the operating system.
Table 1 lists commands available for both the standalone and system modes of the IE-78320. Commands.
listed in table 2 supplement table 1, but can only be used
in the system mode.
Table ,_ Stand-Alone and System Mode
Commands
Command
Function
ASM
Assembles source code line by line
BRA
. Specifies break events In program or internal data
memory area
Table 1. Stand-Alone and System Mode
Commands {confJ
Command
Function
MOV
Moves memory content to different mapping area
OUT
Outputs external trigger
PGM
Controls PG series programmer from 1E-78320
REG
Displays/modifies registers of emulator CPU
RES
Resets the IE-78320 and/or emulator CPU
RU N
Executes programs In reahtlme or non-real-time
SAV
Saves contents of memory onto disk
SF R
DisplaYS/modifies special function registers of
emulator CPU
SPR
Displays/modifies special registers of emulator CPU
STP
Stops emulation CPU during
SYM
ACids/deletes/dlsplays/changes/loads/saveS symbols
rea~tlme
emulation
TRD
DisplaYs trace data
TRF
Sets condition for trace buffer search
TRG
Starts reill-time tracer during real-time emulation
TRM
Selects CPU internal bus or external sense clips for
tracing
TRP
Displays/moves trace buffer pointer
VRY
Compares contents of an object file with memory
Table 2. System Mode Only Commands
Command
Function
COM
Creates command file
Displays disk directory
BRD
Selects external signal as break !lvent
DIR
BRE
Sets a number of Instructions executed as break
event
DOS
Aliows execution of MS-DOS programs
EXT
Terminates IE-78320 controlier program operation
BRM
Enables break events
BRS
Sets paraliel or sequential instruction address
breakpoints
HLP
BRn
ORs various break events together (n = 0 to 3)
lOD
loads object code and symbol files
ClK
Selects internal or external clOck
lST
Sends console display to disk or printer
CNT
Displays elapsed emulation time and number of
Instructions executed
SAV
Saves contents of memory and the debug
envirllnment onto disk
DAS
Disassembles program memory
STR
Automatically executes command string file
D lV
lOD
- Changes/displays number of frames to be traced after
trace trigger has been detected
loads hex format file into program memory
MAP
Displays/changes memory map
MAT
.Evaluates arithmetic expression
MDR
Displays/modifies mode registers of emulator CPU
MEM
Dlsplays/ changes/fills/moves/exchange/ searches/
verifies/tests memory
MOD
Sets channel two serial parameters
9-86
HIS
Displays last twenty commands
. Displays format of commands
NEe
IE·78320
Equipment Supplied
Environmental Characteristics
The IE-78320-R package consists of the following:
• Operating temperature range: 10 to + 40°C
• Storage temperature range: 20 to + 45°C
• Ambient humidity range: 10 to 90% relative humidity
•
•
•
•
•
•
•
•
•
•
IE-78320-R housing
IE-78320 user's manuals
PC-9800 series system disk
IBM PC system disk
AC power cable
AC ground adapter
Ground cable
Spare fuse
RS-232C interface cable
Warranty policy and registration card
Basic Specifications
• Weight: 8.5 kg
• External dimensions:
length, 370 mm; width, 160 mm;
height, 283 mm
• Power source: 100 V AC, 50/60 Hz
Documentation
For further information on IE-78320 operation, NEC
Electronics Inc. provides the following manuals with the
in-circuit emulator:
• IE-78320 jJ.PD78320/322 In-Circuit Emulator Hardware
Manual
• IE-78320 jJ.PD78320/322 In-Circuit Emulator Software
Manual
Additional copies may be obtained from NEC
Electronics Inc.
9-87
IE·78320
ttiEC
NEe
NEG Electronics Inc.
CC7831X
C Compiler Package
for the pPD7831X/pPD7831XA Series
Description
Compiler Options
The CC7831X C compiler package for the NEC
~PD7831X1~PD7831XA microcomputers consists of a
Kernighan and Ritchie compatible C cross compiler
(CC310), relocatable assembler (RA310), linker (LK310),
librarian (LB310), locater (LC310), and an emulator controller program. The CC7831X C compiler package is
available for use on an MS-DOS® system with a freestanding system as target (embedded system).
The CC310 C compiler supports the following options
during compilation:
Features
o Kernighan and Ritchie standard C
- unsigned, enum, typedef, interrupt keywords
- extern, auto, static, register keywords
o Legal C code verification integrated into the
compiler
o User-selectable and directable output files, list and
full cross reference files
o Macro definitions
•
•
•
•
•
•
•
•
Integer size control
Include file control
Defining/undefining constants
Local symbol information included in object files
Prologue/epilogue control
Forced stack checking before each C function
Packed data allocation
Special relocatable data segment
C Library Functions
The CC310 C compiler library includes most of the
important C library functions that apply to PROM based
embedded systems. AU Jibrary functions reside in the
supplied library files. Header files that declare the set of
library functions are also included.
o Branch optimization
The following character operation macros are available:
o Conditional assembly
CHARACTER HANDLING < ctype.h >
o Simple diagnostics
Classification Macros:
o Powerful librarian
isalnum isalpha isascii iscntrl isdigit isgraph
islower isprint ispunct isspace isupper isxdigit
Ordering Information
Part Number
System
Descr I ptlon
CCMSD-15DD-7831X
MS-DOS
5-1/4 inch double-density floppy
diskette
C CROSS COMPILER (CC310)
The CC310 C cross compiler converts standard C source
code into relocatable object modules. The same relocatable object format is used for all relocatable object files
.a.1-.~
toascii tolower toupper
The following library functions are available:
NON-LOGICAL JUMPS
longjmp setjmp
Description
!_
Conversion Macros:
FORMATTED INPUT/OUTPUT
sscanf sprintf
.,.,...,...,...". ...... 1"""',,... .... .,: ............. ............ ,.." .. ~+ ...... .....
................ " ..... ::::t ..... W'::::II_._ ..... _ .... _ ......... ::J- •• -.-~--
,... _ _ _ _ :1 ....... ..- ......... 1",..,.."...
II. La ..... _
.............. ,., •• """
(by an assembler or compiler).
MS-DOS is a registered trademark of Microsoft Corporation.
50258
9-89
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CC7831X
GENERAL UTILITIES
crtO (startup for C programs)
cipt (interrupt system support)
chkstk (check for stack overflow)
STRING HANDLING < string.h >
strcat strchr strcmp strcpy strcspn strlen strncat
strncmp strncpy strpbrk strrchr strspn strtok
MATHEMATICS
abs atoi atol
Memory Models
CC310 supports only the small memory model, since the
ILPD7831X/ILPD7831XA can only address a maximum of
64K bytes of program memory.
RELOCATABLE ASSEMBLER (RA310)
Description
RA310 translates a symbolic source module into a relo~
catable object module. The assembler verifies that each
instruction is valid for the target ILPD7831 X, ILPD7831XA,
or ILPD7832X microcomputer and produces a listing file
and a relocatable object module.
Character constants are translated into seven-bit ASCII
codes. Numeric constants may be specified as binary,
octal, decimal, or hexadecimal. Arithmetic expressions
may include the operators +, -, *,.t, MOD, OR, AND,
NOT, XOR, EO, NE, LT, LE, GT, GE, SHR, SHL, LOW,
HIGH, ., 0, and character constants.
Macro Capability
RA310 allows the definition of macro code sequences
with up to five parameters, LOCAL symbols, and special
repeated code sequences. The macro code sequence
differs from a subroutine call because the invocation of
a macro in the source code results in the direct replacement of the macro call with the defined code sequence.
Assembler Directives
Assembler directives give instructions to the assembler
but are not translated into machine code during assembly. Basic assembler directives include: storage definition and allocation directives (DB,DW, DS, OBIT); symbol
directives (EOU, SET); location counter control directive
(ORG). Program control directives include: segment directives (CSEG, CSEG FIXED, CSEG CALLTO; CSEG
CALLT1, DSEG, BSEG, ENDS); linkage directives
(NAME, PUBLIC, EXTRN, EXTBIT); register assignment
directives (RSS); macro directives (MACRO, LOCAL,
9-90
REPT, IRP, ENDM, EXITM); automatic BR instruction
selection directive (BR) and assembly termination directive (END).
Assembler Controls
There are two types of assembler controls available for
RA310. The primary controls specified in the assembler
command line or at the beginning of the source module
are as follows:
•
•
•
•
•
•
•
•
Processor selection
Output object file selection
Output list file selection
Listing format controls
Date specification
Optimization selection
Workfile drive selection
Symbol letter case selection
General controls, specified in the source program, are as
follows:
• Inclusion of other source files
•
•
•
•
Page eject
Generation/suppression of listing
Listing subtitles
Conditional assembly controls
LINKER (LK310)
LK310 combines multiple relocatable object modules
and library modules and converts them into a single
relocatable object module. The linker resolves PUBLICI
EXTRN references between modules, creating a relocatable output module that contains both relocatable object
code and symbol information. The linker wi II also search
library files for required modules to resolve external
references. The linker controls for LK310 may be specified in either the command line or in a parameter file.
Linker options .incl ude specifyingthe date and the absolute load module name, specifying the creation of a list
file containing a link map, and specifying the letter case
for symbols.
LOCATER (LC310)
LC310 converts a relocatable object module with no
external references into an ASCII hexadecimal format
absolute object code file. The locater outputs two files:
an absolute load file in an expanded seven-bit ASCII
hexadecimal format, which can be downloaded to a
PROM programmer and a symbol file for the symbolic
debugger. Locater options include specifying the starting address and order for code/data/stack segments,
NEe
specifying areas of memory to be protected from being
assigned, and specifying the creation of a map file with
symbol tables.
LIBRARIAN (LB310)
LB310 allows commonly used relocatable object modules to be stored in one file and linked into multiple
programs, greatly increasing programming efficiency.
When a library file is included in the input of the linker, the
linker extracts from the library file only those modules
required to resolve external references and links them
with the other modules.
The librarian creates and maintains library files containing relocatable object modules. Modules can be added
to or deleted from a library file, or the contents of the
library file can be listed.
EMULATOR CONTROLLER PROGRAM
Absolute object files produced by the CC7831X C compiler package can be debugged using an NEC standalone in-circuit emulator. An NEC emulator controller
program allows you to communicate with the emulator
through an RS-232C serial line. The emulator controller
program is available to run on the IBM PC®, PCf)
Classification Macros:
lsalnum isalpha isascii iscntrl Isdigit isgraph
islower isprint ispunct isspace isupper isxdigit
Conversion Macros:
toascii tolower toupper
The following library functions are available:
NON-LOGICAL JUMPS < setjmp.h >
longjmp setjmp
FORMATTED INPUT/OUTPUT < stdio,h >
sscanf sprintf
GENERAL UTILITIES
crta (startup for C programs)
cipt (interrupt system support)
chkstk (check for stack overflow)
STRING HANDLING
strcat strchr strcmp strcpy strcspn strlen strncat
strncmp strncpy strpbrk strrchr strspn strtok
MATHEMATICS
abs atoi atol
~7
9-93
t\'EC
CC7832X
Memory Models
CC320 supports only the small memory model since the
"PD7832X can only address a maximum of 64K bytes of
program memory.
RELOCATABLE ASSEMBLER (RA310)
Description
RA310 translates a symbolic source module into a relocatable object module. The assembler verifies that each
Instruction I~ valid for the target "PD7831X, "PD7831XA,
or "PD7832X microcomputer and produces a listing file
and a relocatable object module.
.
Character constants are translated Into seven-bit ASCII
codes. Numeric constants may be specified as binary,
octal, decimal, or hexadecimal. Arithmetic expressions
may Include the operators +, -, *, /, MOD, OA, AND,
NOT, XOR, EQ, NE, LT, LE, GT, GE, SHA, SHL, LOVl(
HIGH, .,0; and charac;ter constants.
Macro Capability
RA310 allows the definition of ,macro code sequences
with up to five parameters, LOCAL symbols, and special
repeated code sequences. The macro code sequence
differs from a subroutine call because the invocation of
a macro In the source code results Ih the direct replacement of the macro call with the defined code sequence.
Assembler Directives
•
•
•
•
•
•
Output list file selection
Wstlng format controls
Date specification
Optimization selection
V\brkfile drive selection
Symbol letter case selection
General controls, specified in the source program, are as
follows:
•. Inclusion of other source files
• Page eject
• Generation/suppression of listing
• Wsting subtitles
• Conditional assembly controls
LINKER (LK310)
LK310 combines multlplereloeatable object modules
and library modules and converts them into a single
relocatable object module. The linker resolves PUBLICI
EXTAN references between modules, creating a'relocatable output module that contains both relocatable object
code and symbol information. The linker will also search
library files for required modules to resolve external
references. The linker controls for LK310 may be specified In either the command line or in a parameter file.
Linker options include specifying the date and the absolute load module name, specifying the creation of a list
file containing a link map, and specifying the letter case
for symbols.
Assembler directives give instructions to the assembler
but are not translated Into machine code during assembly. Basic assembler directives Include: storage definition and allocation directives (DB,DV\( DS, DBIT); symbol
directives (EQU, SET)i location counter control directive
(OAG). Program control directives include: segment directives (CSEG, CSEG FIXED, CSEG CALLTO, CSEG
CALlT1, DSEG, BSEG, ENDS); linkage directives
(NAME, PUBLIC, EXTAN, EXTBIT); register assignment
directives (ASS); macro directives (MACAO" LOCAL,
AEPT, lAp, ENDM, EXITM); automatic BA instruction
selection directive (BA) and assembly termination directive (END).
LC310 converts a relocatable object module with no
external references into an ASCII hexadecimal format
absolute object code file. The locater outputs two flies:
an absolute load file in an expanded .seven-blt ASCII
hexadecimal format, which can be downloaded to a
PAOM programmer and a symbol file for the symboliC
debugger: Locater options include specifying the starting address and order for code/data/stack segments,
specifying areas of memory to be protected from being
assigned, and specifying the creation of a map file with
symbol tables.
Assembler Controls
LIBRARIAN (LB310)
There are two types of assembler controls available for
RA310.. The primary controls, specified in the al!S9mbler
command line or a~ the beginning of the source module
are as follows:
LB310 allows commonly used relocatable object modules to be stored in one file and linked into multiple
programs, greatly increasing programming efficiency.
When a library file is included In the Input of the linker, the
linker extracts from the library file only those modules
required to resolve external references and links them
with the other modules.
• Processor selection
• Output object file selection
9-94
LOCATER (LC310)
~EC
The librarian creates and maintains library files containing relocatable object modules. Modules can be added
to or deleted from a library file, or the contents of the
library file can be listed.
EMULATOR CONTROLLER PROGRAM
Absolute object files produced by the CC7832X C compiler package can be debugged using an NEC standalone in-circuit emulator. An NEC emulator controller
program allows you to communicate with the emulator
through an RS-232C serial line. The emulator controller
program is available to run on the IBM P~, PC/XTI!l, or
PC ATI!l under MS-DOS. It provides the following features:
•
•
•
•
•
•
•
•
Uploading/downloading of object/symbol files
Symbolic debugging capability
Complete emulator control from host console
On-line help facilities
Macro command file capabilities
Host system directory and file display
Storage of debug session on disk
Storage of last 20 commands for recall
CC7832X
LICENSE AGREEMENT
CC7832X is sold under terms of a license agreement,
which is included with purchased copies. The accompanying card must be completed and returned to NEC
Electronics Inc. to register the license. Software updates
are provided free to registered users for one year.
IBM PC, PC/XT, and PC AT are trademarks of International BUSiness
Machines Corporation.
DOCUMENTATION
For further. information on source program formats, C
compiler and assembler operation, and actual program
examples, NEC Electronics Inc. provides the following
documentation:
• CC78XXX C Compiler ~PD78XXX C Compiler User's
Manual
• CC78XXX C Compiler ~PD78XXX Relocatable Assembler User's Manual
This documentation is provided with purchased copies
of the package. Additional copies may be obtained from
NEC Electronics Inc.
9-95
007832)(
9-96
fttlEC
NEe
NEe Electronics Inc.
RA78K3
Relocatable Assembler Package
for the pPD7831X/7832X
Description
Ordering Information
The RA78K3 relocatable assembler package converts
symbolic source code for the "PD7831X and "PD7832X
eight/sixteen-bit, single-chip microcomputers into executable absolute address object code. The RA78K3 reloeatable assembler package consists of four separate
programs: assembler (RA78K3), linker (LK78K3), locater
(LC78K3); and librarian (LB78K3).
Part Number System
RA78K3 translates a symbolic source module into a
relocatable object module. The assembler verifies that
each instruction assembled is valid for the target microcomputer specified at assembly time and produces a
listing file and a relocatable object module.
LK78K3 combines multiple relocatable object and library
modules and converts them to a single relocatable
object module. LC78K3 converts a relocatable object
module with no external references into an ASCII hexadecimal format absolute object code file.
LB 78K3 allows commonly used relocatable object modules to be stored in one file and linked into multiple
programs, greatly increasing programming efficiency.
When a library file is included in the input ofthe linker, the
linker extracts from the library file only those modules
required to resolve external references and links them
with the other modules.
Features
CJ
CJ
CJ
CJ
CJ
CJ
CJ
W
Absolute address object code output
User-selectable and directable output files
Macro definitions
Branch optimization
Conditional assembly
Extensive error reporting
Powerful librarian
Muns unaer ivIi)-uu~~ ana -vM~iviVi~;;' upefi:llill\:j
systems
RA78K3-D52
Description
MS·DOS 5-1/4 Inch double·denslty floppy diskette
RA78K3·WT1 V/lI)(/VMS 9-track 1600 BPI magnetic tape
Program Syntax
An RA78K3 source module consists of a series of code,
data, or bit segments. Each segment consists of statements composed of up to four fields: symbol, mnemonic,
operand, and comment.
The symbol field may contain a label, whose value is the
instruction or data address, or a name which represents
an instruction address, data address, or constant. The
mnemonic field may contain an instruction or assembler
directive. The operand field' contains the data or expression for the specified instruction or directive. The comment field allows explanatory comments to be added to
a program.
Character constants are translated into seven~bit ASCII
codes. Numeric constants may be specified as binary,
octal, decimal, or hexadecimal. Arithmetic expressions
may include the operators +, -, *, /, MOD, OR, AND,
NOT, XOR,EQ, NE, LT, LE, GT, GE, SHR, SHL, LO~
HIGH, ., (), and character constants.
Macro Definition
RA78K3 allows the definition of macro code sequences
with up to five parameters, LOCAL symbols, and special
repeated code sequences. The macro code sequence
differs from a subroutine call: the invocation of a macro
in the source code results in the direct replacement oft he
macro call with the defined code sequence.
MS·DOS Is a registered trademark of Microsoft Corporation.
V/lIX and VMS are registered trademarks of Digital Equipment
Corporation.
50251
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~
t\'EC
RA78K3
Assembler Directives
Assembler directives give instructions to the assembler.
They are not translated into machine code during assembly. Basic assembler directives include: storage definition and allocation directives (DB, rJN, OS, OBIT); symbol directives (EQU, SET); and location counter control
directive (ORG). Program control directives include:
segment directives (CSEG, OSEG, BSEG, ENDS); linkage directives (NAME, PUBLIC, EXTRN, EXTBIT); macro
directives (MACRO, LOCAL, REPT, IRP, EXITM, ENOM);
automatic BR instruction directive (BR); register assignment directive (RSS); .and assembly termination directive (END).
Figure 1. Relocstsble Assembler Functlonsl
Dillgrsm
System
Console
Assembler Controls
The RA78K3 assembler (figure 1) has two types of
controls. Primary controls are specified in the assembler
command line or at the beginning of the source module
and are as follows:
•
•
•
•
•
•
Processor selection
Output object creation selection
Output list file selection
Listing format controls
Optimization selection
\\brk file drive speCification
General controls are specified in the source program
and are as follows:
•
•
•
•
•
Inclusion of other source files
Page eject
Generation/suppression of listing
Listing titles
Conditional assembly controls
The listing file contains either the complete assembly
listing or only the lines with errors, and a symbol or
cross-reference table. The symbol table shows all defined symbols in alphabetical order, with the types,
attributes, and the values initially assigned to them.
The cross-reference table contains all defined symbols
and the numbers of all statements referring to them. The
object file cpntains the relocatable object module. This is
an NEC proprietary relocatable object module format.
If the optimization option is chosen, the assembler will
generate the most efficient code by converting, wherever possible, three-byte absolute branches into twobyte relative branches.
9-98
Source
Module
File
Include
File
~
~.
RA78K3
Relocatable
Assembler
'-'
~
~
J
Relocatable
Object
Module
File
Assembler
List File
Temporary
Work Files
49NR·5B3A
Linker
The LK78K3 linker (figure 2) combines several relocatable object modules, resolving PUBLIC/EXTRN references between modules, to create a relocatable output
module. This output module contains both relocatable
object code and symbol information. The linker will also
search library files for required modules to resolve external references. The linker controls for LK78K3 can be
specified in either the command line or in a parameter
file. The programmer can specify the date, and absolute
load module name, and control the creation of a list file
containing a link map.
NEe
RA78K3
Figure 2. Unker Functionsl Diagram
library
Module
File 1
...
Relocalable
Object
Module
File 1
Library
Module
File n
...
Relocalable
Object
Module
File
Relocatable
Object
Module
File n
*
1
I
System
Console
Figure 3. LDClller Functional Diagram
~
LK78K3
Linker
Relocalable
Object
Module
File
+---+
Temporary
Work Files
c
System
Console
LC78K3
Locater
rB ~
Symbol
File for
Debugger
Linker
list File
49NR-585A
Locater
The LC78K3 (figure 3) locater outputs two files: an
absolute load file in a seven-bit ASCII expanded hexadecimal format, which can be downloaded to a PROM
programmer; and a symbol file for the symbolic debugger. The programmer can specify the starting address
and order for code/data/stack segments, and can protect
areas of memory from being assigned. The programmer
can specify that a map file with symbol tables be
created.
Map File
Temporary
Work Files
Hexadecimal
Object
Code File
* With no ex~rnal references
49NR-587A
Librarian
The LB78K3librarian creates and maintains library files
containing relocatable object modules. This reduces the
number of files to be linked together by storing several
modules in a single file. This provides an easy way to link
frequently used modules into programs. IVIodules can be
added to, deleted from, or replaced within a library file; or
the contents of the library file can be listed.
9-99
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RA78K3
Operating Environment
The NEC RA78K3 package runs under a variety of operating systems. One version runs on an MS-DOS system
with one or more disk drives and at least 128K of system
memory. Another version runs on a Digital Equipment
Corporation VAX computer under the VMS (Version 4.1 or
later) operating system.
Emulator Controller Program
Absolute object flies produced by the RA78K3 relocatable assembler package can be debugged with the
appropriate NEC stand-alone in-circuit emulator. NEC
emulator controller programs allows communication
with the emulator through an RS-232C serial line. An
emulator controller program can run on the IBM P~,
PC~, OR PC ATe under MS-DOS and is provided with
the in-circuit emulator at no extra charge.
These emulator controller programs provide the followIng featlires:
•
•
•
•
•
•
•
•
Uploading/downloading of object and symbol flies
Symbolic debugging capability
Complete emulator control from host console
On~line help facilities
Macro command file capabilities
Host system directory and file dillplay
Disk storage of debug session
Storage of last 20 commands for recaU
9-100
License Agreement
RA78K3 Is .sold under. terms of a license agreement,
which is included with the assembler. The accompanying
card rnust be completed and returned to NEe Electron. ics Inc. to register the license. Software updates' are
provided ftee to registered users.
Documentation
For further information on source program formats,
operation, and actual program examples,
NEC Electronics Inc. provides the following documentation:
a~embler
• RA78K3 "PD7831X/"PD7832X Relocatable Assembler
Package, Language Manual
• RA78K3 "PD7831X/"PD7832X Relocatable Assembler
Package, Operation Manual (MS-DOS)
• RA78K3 "PD7831)(f"PD7832X Relocatable Assembler
Package, Operation Manual (VMS)
This documentation Is provided with purchased copies
of the package. Additional copies may be obtained from
NEC Electronics Inc.
IBM PC, PClXT, and PC AT are registered trademarks of Internaltlonal
E!UBlness Machines Corporation.•
NEe
NEC Electronics Inc.
Description
The ST78K3 structured assembler preprocessor is a
companion program to the RA78K3 relocatable assembler for the NEC p,PD783XX series of microcomputers.
ST78K3 converts a source code file containing structured assembly statements into a pure assembly language source file, which then can be assembled with
RA78K3.
ST78K3
Structured Assembler Preprocessor
for the pPD783XX Series
Structured Assembler Preprocessor
Functional Diagram
ST78K3 will convert a structured assembly statement
into one or more p,PD783XX assembly language instructions which perform the desired operation. Since
ST78K3 converts only the structured assembly statements and does not convert p,PD783XX assembly language instructions, a structured source program can
include a combination of p,PD783XX structured assembly
statements and assembly language.
ST78K3 enables the assembly language programmer to
use some of the structures and syntax of higher-level
languages such as the C language. This improves program readability and reliability, and increases programmer productivity.
Features
o Control structures for conditions, looping, and
switch-case
o Preprocessor directives for conditional code
generation
DC-like representation of comparison operations
DC-like representation of assignment/arithmetic
operations
o Increment and decrement operators
o Allow use of all p,PD783XX mnemonics, registers,
and features
o Runs under MS-DOS® and VAX®NMS® operating
systems
Ordering Information
The ST78K3 structured assembler preprocessor is included in the following software packages at no cost:
RA78K3
I1PD783XX
Relocatable
Assembler
49NR-S89A
Summary Of Structured Language
A line of source code for ST78K3 contains either a
structured assembly statement or a p,PD783XX assembly
language statement. p,PD783XX assembly language
statements (p,PD783XX instructions, RA78K3 directives,
or RA78K3 controls) pass through ST78K3 without
change.
Structured assembly statements consist of preprocessor
directives, assignment statements, and control statements. These statements are entered one per line, and
are terminated by a line feed character. An optional
comment may follow a semicolon at the end of the
statement; all text following a semicolon is ignored by
ST78K3.
Preprocessor directives cause ST78K3 to include or omit
portions of code. Assignment statements cause ST78K3
•
-
-
LV ~vl 1'01
_0-
cut:;
_
VIII;; VI
..... _ _ ......... "
IIIVI II::
......
p.rlJ (OvA./\.
at:tt:tCIIIUI
Y
IQllyuayc
instructions to alter the contents of a register or variable.
Control statements cause ST78K3 to generate the necessary instructions to test conditions and change control flow based on those conditions.
• RA78K3 p,PD783XX Relocatable Assembler Package
MS·DOS is a registered trademark of Microsoft Corporation.
VAX and VMS are registered trademarks of Digital Equipment
Corporation.
50254
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•
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ST78K3
Preprocessor Directives
ST78K3 preprocessor directives set and test variables.
allowing conditional processing of code; include external files; and map instructions to p.PD783XX CALT table
reference instructions. Table 1 lists the preprocessor
directives and their functions.
Table ,_ Preprocessor Directives and Functions
Directive
#ifdef ABC
#else
#endif
If ABC has been defined as above. or on the
command line with the -D option. the first set
of statements is processed and the second
set ignored; if ABC has not been defined. or
defined as zero. the first set of statements is
ignored and the second set is processed.
#include "filename"
The named file is read from disk and
processed as if included in the source.
#defcallt @LABEL
CALL !label
#endcallt
Whenever the instruction "CALL !label" is
encountered in the source program. it is
replaced by "CALLT [@LABEL]". The label
must be defined in the CALLT table.
ASSignment, Increment, and Decrement
Statements
ST78K3 provides the ability to represent an assignment.
or an assignment with an arithmetic operation. in C
language syntax:
destination < assign-op > source
The assignment operators allow either simple assignment. or the combination of an assignment with an
arithmetic operation on the source and destination.
Examples:
Where an assignment requires an intermediate register
to hold the value being aSSigned. the register is designated by naming it in parentheses following the assignment operation.
Operator
=
B (A)
HL (XA)
Example
Function
A=B
A--B
< - >
A< - > B
Contents of A and B are exchanged
+=
A+=B
A--A+B
A-= B
A--A-B
*=
AX *= B
AX--AX*B
/=
AX/= C
AX--AX/C
&=
A&= B
A -- A & B Qogical AND)
1=
AI= B
A -- A I B (logical OR)
A'= B
A -- A ' B (logical XOR)
»=
A»=B
(CY--Ao.An.1--An ..... Amax--O) x B times
«=
A«=B
(CY--Amax.An+1 .....An .... Ao--O) x B times
++
A++
A--A+l
A-
A--A-l
Control Statements
Control statements allow conditions to be tested. Based
on the results of the test. blocks of code are allowed to
be executed or skipped. Reserved words in the control
statement define the start and end of blocks of code. and
expressions to be evaluated.
Example:
==
= B (A)
;The condition is tested.
;If A equals the content of memory
;at HL. this code is executed.
A + = [HL]
;Otherwise. this code is executed.
if (A
[HLJ)
A = [HL]
else
A- = B
P5 = A
endif
Table 3 shows the control statements and their functions.
Examples:
=
Table 2. Assignment Operators with Examples
and Functions
P5
A= B
;Move contents of B register to.A
A + = [HL] ;Add contents of memory at HL to A.
;store in A
BC &
Table 2 lists the assignment operators with examples
and functions.
Function
#define NAME value Defines the variable NAME. set to the
supplied value.
DATA 1
The increment and decrement operators (+ + and --)
operate on a single operand.
;Store contents of B into memory at
;DATA 1. using A as temporary storage
;and BC with HL. store in BC.
;use XA as temp
t-{EC
ST78K3
Table 3. Control Statements and Function
Table 6. Binary Operators
Control Statement
Function
Binary Operator
if - elseif - else - endif
Test variable expressions
Meaning
Equals
iLbit - elseiLbit - else - endif
Test bit expressions
1=
switch - case - default - ends
Select based on variable
>
Not equal
Greater than
for - next
Loop, test variable
>=
Greater than or eq ual
while· endw
Loop, test variable
<
Less than
repeat - unti I
Loop, test variable
<=
Less than or equal
Loop, test bit
Loop, test bit
repeat - untiLbit
break
Exit cont rol block
continue
Skip to top of block
gotoLABEL
Branch to label
Bit expressions test individual bits of registers, ports, or
memory locations. Table 7 shows the acceptable forms
of bit expressions.
Table 7. Bit Expressions and Examples
Bit Express Ion
Variable And Bit Expressions
Variable expressions for tests consist of a single value,
comparison between two variables, or a logical combination of comparisons. Bit expressions test individual
bits. Table 4 shows examples of comparisons:
Table 4. Examples of Variable Expression
Comparisons
Comparison
Meaning
if(A)
Tru e if A is non-zero
if (A < B)
True if A is less than B
if ((A < B) && (A > C))
True if A is less than B and greater than C
iLbit ( P1.2)
True if bit 2 of P1 is 1
iLbit (!P1.2 )
True if bit 2 of P1 is 0
The allowable expressions using variables are shown in
table 5.
Table 5.
Expressions and Examples
Expression
Example
Primary
(A)
Term
(A <= B)
T ....
~~
,_••••
0 0
__
.,.__
~
.'W • • • •
Term II Term
",.
0<)
1 .. _
,....\\ " ___ ' __ '
......... ,
\ \,. - --I ........... \' • ...- ...., J \ ..... ~ •..,""'" , .. " ..... ,
_~n\
((A= =C) II (A= = B) ) (logical OR)
A primary value for a variable expression is a register
name or defined symbol. A term consists of two primary
values compared with a binary operator. Table 6 lists the
supported binary operators and their meanings.
Example
BiLprimary
( PO.1)
!BiLprimary
(ICY)
BiLprimary && BiLprimary
(AO && CY)
BiLprimary II BiLprimary
(PO.211 CY)
A Bit_primary can be either a reserved word bit identifier, such as a bit of a register or port (PO.1, Cy), or a bit
definition symbol (SBO EQU PO.2).
ST7BK3 Operation And Controls
ST78K3 consists of four files: ST78K3.EXE, ST78K3.0MA
(/LPD78310A/312A), ST78K3.0MB (/LPD78320/322/327/
328), and ST78K3.0MC ~PD78330/334). Before invoking
ST78K3, the user must copy the appropriate file to
ST78K3.0M1. For example, ifthe user is developing code
for the /LPD78310A/312A, the user must type:
C>COPY ST78K3.0MA ST78K3.0M1
ST78K3 is invoked by specifying the name of the source
file, followed by optional controls.
Example:
C>ST78K3 ABC.SRC -DXYZ=3
ST78K3 reads the specified source file and produces an
output assembly language file, which can be input to
RA78K3. The output file contains all lines provided in the
input source file, plus those generated by ST78K3. Lines
containing no statements for the structured assembler
are passed through unchanged. Lines with structured
assembly statements are placed in the output preceded
by a semicolon. RA78K3 treats these lines as comments.
These commented lines are then followed by the code
generated by ST78K3.
9-103
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ST78K3
The controls for ST78K3 are specified in the preprocessor command line or in a parameter' file invoked in the
command line.· Table 8 lists the ST78K3 preprocessor
controls and functions.
Table 8. S 1711K3 Preprocessor Controls
Control
Function
-Ofilename
Specify name of output assembly source file
-Ffilename
Specify name of parameter file to be read
-Efilename
Specify name of error listing file
-Dsymbol[ =valuel
Define a symbol Oike #define in code)
-I[d:][directoryl
Define path for include file
-WTn1,n2,n3
Define TAB settings for generated code
-SCcharacter
Defines word symbol last character
The -0 option allows the name of the output fUeto be
specified. If not specified, the output file name defaults
to the name of the input source file with the extension
.ASM.
The -F option allows a parameter file to be specified,
which will be read by ST78K3. This parameter file can
contain a list of controls to .be given to ST78K3, instead
of or in addition to those speCified on the command line.
The -E option specifies the name of the error listing file.
The error file contains the file name,· etrornumber,
description of error and the line containing the error. If
the -E option is not specified, the error file name defaults
to the name of the input source file with the extension
.EST. '
The -0 control allows a symbol to be defined on the
command line, with an optional value provided. If a
symbol is defined but no value is specified, the value
defaults to 1. If the source file contains a #define
directive which specifies a variable with the same name
as the -0 control, the value on the command line will
override the value in the #define directive.
9-104
The -I control specifies a drive or directory other than the
current drive and directory to search for include files.
The -WT control specifies the number of TAB characters
to insert before labels, instruction mnemonics, and instruction operands generated by ST78K3. This allows
clear separation of assembly language instructions
coded in the source file from those generated by
ST78K3.
The -SCcharacter control specifies the character used
as the last character in a word symbol. The character
must be a letter of the alphabet or the @, _ or ? This
allows ST78K3 to distinguish between word and byte
operations. Symbols which end in this character are
treated as word symbols and will generate a word
operation (ie. MCNW). If the -SC operation is not specified, ST78K3 assumes that a symbol ending with the
character "P" or "p" is a word symbol.
Documentation
For further information on source program formats,
preprocessor operation, and actual program Eixamples,
NEC Electronics Inc. provides the following documentation:
• ST78K2/ST78K3 ~P0782xx/~P0783xx Structured Assembler Preprocessor User's Manual
This documentation is provided with purchased copies
of the RA78K3 ~P0783xx relocatable assembler package. Additional copies may be obtained from NEC
Electronics Inc.
t-IEC
PG·1500 Series
EPROM Programmer
NEC Electronics Inc.
Description
The PG-1500 series is a stand-alone EPROM programmer
for programming 256-kilobit to 1-megabit EPROMs and
EPROM/OTP devices for NEC's 4/8/16-bit single-chip
microcomputers and digital signal processors. The system consists of the PG-1500 base programmer, interchangeable programmer adapter modules for standard
EPROM devices and the /l-PD75XX/75XXX series 4-bit
microcomputers, and a variety of programmer adapters
to support the individual devices and package types. The
PG-1500 can be controlled from either a remote terminal
or host computer via an RS-232C serial port, or directly
from the on-board keypad in stand-alone mode.
Features
o Interchangeable modules for programming:
- 256-kilobit to 1-megabit EPROMs
- NEC /l-PD75XX and /l-PD75XXX series 4-bit
microcomputers
- NEC /l-PD78XX and /l-PD78XXX series 8-bit
microcomputers
- NEC V-series 16-bit microcomputers
- NEC /l-PD77XXX digital signal processors
o PROM insertion error detection circuitry
o Address splitting for 16/32-bit microprocessors
o Memory edit function to change/confirm PG-1500
buffer
o Address/data/message display LCD
o RS-232C serial interface
o Centronics compatible parallel interface
o Power-on diagnostics
o Supports three data transfer formats
-Intel extended hex (Note 1)
- Extended Tektronix hex (Note 2)
- Motorola S (Note 3)
o Two modes of operation
- Remote controlled
- Stand-alone
o Host Controller Program for IBM PC® Series
IBM PC is a registered trademark of International Business Machines
Corporation
Notes:
(1) Developed by Intel Corporation.
o 512K-bytes data RAM
(2) Developed by' Tektronix Corporation.
o Silicon signature read function
(3) Developed by Motorola Inc.
PG-1500 Series
50117
9-105
NEe
PG·1500 Series
Ordering Information
Part Number
Description
Part Number
Description
PG-1500
PG-1500 Series EPROM Programmer for 27XXX
EPROMS, NEC 4/8116 microcomputers, and
DSP devices Oncludes 027A and 04A
Programming Adapter Modules)
PA-75P516GF
Programmer Adapter for "PD75P516GF
PA-75P516K
Programmer Adapter for "PD75P516K
PA-77P25C
Programmer Adapter for "PD77P25C/D
PA-70P322L
Programmer Adapter for "PD70P322K
PA-77P56C
Programmer Adapter for "PD77P56CRlG
PA-71 PS01 GF
Programmer Adapter for "PD71 PS01 GF
PA-77P2SOR
Programmer Adapter for "PD77P2SOR
PA-71PS01GQ
Programmer Adapter for "PD71 PS01 GQ
PA-78CP14CW
Programmer Adapter for "PD78CP14cw, OW
PA-71P301KA
Programmer Adapter for "PD71 PSOl KA
PA-78CP14GF
Programmer Adapter for "PD78CP14GF
PA-71P301KB
Programmer Adapter for "PD71 PS01 KB
PA-78CP14GQ
Programmer Adapter for "PD78CP14G!R
PA-71PS01L
Programmer Adapter for "PD71 P301 L
PA-78CP14L
Programmer Adapter for "PD78CP14L
PA-75P54CS
Programmer Adapter for "PD75P54/64CS"
"PD75P54/64G
PA-78P214CW
Programmer Adapter for "PD78P214CW
PA-78P214GJ
Programmer Adapter for "PD78P214GJ
PA-78P214GQ
Programmer Adapter for "PD78P214GQ
PA-78P214L
Programmer Adapter for "PD78P214L
PA-78P224GJ
Programmer Adapter for "PD78P224GJ
PA-78P224L
Programmer Adapter for "PD78P224L
PA-7BP238GC
Programmer Adapter for "PD7BP238GC
PA-7BP238GJ
Programmer Adapter for "PD7BP238GJ
PA-7BP238KF
Programmer Adapter for "PD7BP238KF
PA-7BP238LQ
Programmer Adapter for "PD7BP238LQ
PA-7BP312CW
Programmer Adapter for "PD7BP312ACW/DW
PA-7BP312GF
Programmer Adapter for "PD7BP312AGF
PA-7BP312GQ
Programmer Adapter for "PD7BP312AGQfR
PA-7BP312L
Programmer Adapter for "PD7BP312AL
PA-78P322GJ
Programmer Adapter for "PD7BP322GJ
PA-7BP322KC
Programmer Adapter for "PD7BP322KC
PA-7BP322KD
Programmer Adapter for "PD7BP322KD
PA-7BP322L
Programmer Adapter for "PD7BP322L
PA-75P56CS
Programmer Adapter for "PD75P56/66CS,
"PD75P56I66G
PA-75POOSCU
Programmer Adapter for "PD75POOSCU/G B
PA-75P036CW
Programmer Adapter for "PD75P036CW
PA-75P036GC
Programmer Adapter for "PD75P036GC
PA-75P10BCW
Programmer Adapter for
"PD75P1OSCW/DW/BCW, "PD75P116CW
PA-75P1OSG
PA-75P116GF
PA-75P216ACW
PA-75P3OSGF
PA-75PSOBK
Programmer Adapter for "PD75P1OSG/BGF,
"PD75P116GF
Programmer Adapter for "PD75P10BG/BGF,
"PD75P116GF
Programmer Adapter for "PD75P216ACW
Programmer Adapter for ",PD75PS08GF,
"PD75P316GF/AGF
Programmer Adapter for "PD75P308K,
"PD75P316AK
PA-75P32BGC
Programmer Adapter for "PD75P32BGC
PA-75P402CT
Programmer Adapter for "PD75P402CT
PA-75P402GB
Programmer Adapter for "PD75P402G B
9-106
NEe
PG·1500 Series
Figure 1. PG-1500 System Block Dilll/Tam
Programmer Adapters
Programmer Adapter Modules
PG-1500
Base Programmer
1--------83ML.s8368
Architecture
The PG-1500 base unit contains an NEC p.PD70208
(V40 TM) microprocessor with 128K bytes of monitor ROM,
32K bytes of working RAM, 512K bytes of data memory,
an RS-232C serial port, a Centronics compatible parallel
interface, an LCD display, and a 23-key keypad. Figure 1
the PG-1500 Programming Adapters Selection Guide for
a list of all available adapters.
On power-up, the PG-1500 performs a self-diagnostic on
its internal memory, its data bus, its power supply, and
its reference voltages.
shows a block diaQram of the PG-1500.
Operation
The PG-1500 has two interchangeable programmer
adapter modules: one for 27XXX EPROMS, NEC's 4/8/16
bit microcomputers, and DSP devices which use the
p.PD27C256A programming algorithm (027A board), and
another for NEC's p.PD75XX!75XXX 4-bit microcomputers which must be programmed in a serial fashion (04A
board). These adapter modules plug directly into the top
of the PG-1500 and can accept a wide variety of programmer socket adapters to support NEC's devices. Refer to
The PG-1500 operates in stand-alone mode from the
on-board keypad, or in remote control mode from an
external terminal or from a host computer via an RS232C serial port.
Stand-Alone Mode
Table 1 lists the PG-1500 commands available iii standalone mode.
9-107
NEe
PG·1500Series
Table 2. Address Splitting Modes
Table 1. PG-1500 Commands in Stand-Alone
Mode
Mode
Description
Command
Function
Normal
DEVICE SELECT
Selects the EPROM to be used
The data is not split at all. Each byte of data in the
buffer is programmed into the device.
16EVN
Each byte of data on an even address In the buffer is
programmed into the device.
16000
Each byte of data on an odd address in the buffer Is
programmed into the device.
DEVICE BLANK
Checks if the EPROM is blank
DEVICE COPY
Reads data from the EPROM
DEVICE PROG
Writes data into the EPROM
DEVICE VERIFY
Verifies EPROM contents against PG-1500
buffer
32/2E
The first two bytes of every four bytes in the buffer is
programmed into the device.
DEVICECONT
Performs BLANK, PROG, VERIFY
commands in sequence
32/20
The third and fourth byte of every four bytes in the
buffer is programmed into the device.
EDIT CHANGE
Display/change the contents of the PG-1500
buffer
32/4E1
The first byte of every four bytes in the buffer is
programmed into the device.
EDIT INITIAL
Initializes the PG-1500 buffer
32/401
EDIT MOVE
Moves a block of data within PG-1500 buffer
The second byte of every four bytes in the buffer is
programmed into the device.
EDIT SEARCH
Searches PG-1500 buffer for 1-, 2-, or
4-byte patterns
32/4E2
The third byte of every four bytes in the buffer is
programmed into the device.
EDIT C-SUM
Performs checksum on all data in PG-1500
buffer
32/402
The fourth byte of every four bytes in the buffer is
programmed into the device.
FUNCTION S-IN
Inputs data from serial port in three formats
FUNCTION S-OUT
Outputs data from serial port in three
formats
FUNCTION REMOTE
Sets PG-1500 to remote control mode
FUNCTION P-IN
Inputs data from parallel port in three
formats
FUNCTION MODE
Sets up the RS-232C serial port parameters
The stand-alone commands fall into three groups:
• DEVICE commands associated with the device to be
programmed
• EDIT commands for interacting with the PG-1500
memory buffer
• FUNCTION commands for setting up and controlling
the PG-1500
The DEVICE commands are available to check if an
EPROM device is blank, to copy data from the device to
the PG-1500 buffer, to write the buffer data to the device,
and to compare the data in the device with the data in the
buffer. Blank checking, programming, and verification of
the device can be performed sequentially using a single
command.
To support various 16- and 32-bit microprocessors, the
PG-1500 can split the data in its buffer in a variety of
ways. When a data file is loaded into the PG-1500, the
complete file is stored in the buffer and can be dynamIcally split during writing and verification. The PG-1500
supports the address splitting modes described in table
2.
9-108
This method of address splitting also allows the complete original file to be recreated in the buffer when
reading from a set of master EPROMs.
A silicon signature is stored in all NEC devices and
contains information on the device type, start and stop
addresses, and programming voltages. The PG-1500 can
read the silicon signature of the particular device being
programmed either manually or automatically, or the
device code can be entered manually.
The EDIT commands initialize the PG-1500 buffer to a
known value, move a block of data from one location to
another, and change/display data at a particular address. The PG-1500 buffer can also be searched for all
occurrences of any 1-, 2-, or 4-byte pattern. Finally, a
checksum can be calculated for all the data contained in
the buffer.
The FUNCTION commands control the setup of the
RS-232C serial port, whether the PG-1500 checks for a
PROM insertion error, whether the PG-1500 is operated
through the serial port, and how data is input/output·
from the PG-1500. Data can be input to the PG-1500
through either the RS~232C serial port or the Centronics
. compatible parallel port in Intel Extended Hex, Extended
Tektronix Hex, or Motorola S formats. Data can also be
output via the RS-232C port in any of these three
formats.
NEe
Remote Control Mode
Table 3 lists the PG-1500 commands available in Remote
Control Mode.
Table 3. PG-1500 Commands in Remote Control
Mode
Command
Function
RR
Reads data from the EPROM
RS
Selects the EPROM to be used
PG-1S00 Series
ROM device, loads the file, writes the ROM and returns to
the operating system when 1 set of ROM devices is
completed.
In the terminal mode, all of the remote control commands listed in Table 3 are available for entry at the
prompt. An additional operating system shell (OS) command allows execution of MS-DOS® programs without
termination of the controller program. This OS command
is also available in the control mode.
Verifies EPROM contents against PG·1500 buffer
MS-DOS is a registered trademark of Microsoft Corporation
Writes data into EPROM
EquipmenfSupplied
RZ
Checks if EPROM is blank
MC
Change the contents of the PG-1500 buffer
MD
Displays the contents of the PG-I500 buffer
MF
Initializes the PG-1500 buffer
PI
Inputs data from parallel port (Intel Extended HEX)
PM
Inputs data from parallel port (Motorola S)
PT
Inputs data from parallel port (Extended Tektronix
HEX)
LI
Inputs data from serial port (Intel Extended HEX)
LM
Inputs data from serial port (Motorola S)
LT
Inputs data from serial port (Extended Tektronix
HEX)
SI
Outputs data from serial port (Intel Extended HEX)
SM
Outputs data from serial port (Motorola S)
ST
Outputs data from serial port (Extended Tektronix
HEX)
??
Help command
Host Controller Program
The PG-1500 can be controlled from an IBM PC series
host computer using the accompanying PG-1500 controller program. The controller program has three modes
of operation: control mode, auto mode, and terminal
mode.
In the control mode, commands to be executed and
f./C1IC1f11tmm; [0 oe cflangeci are seiecrea Trom a screen
display using the cursor control keys. The PG-1500 can
be automatically configured from information contained
in a optional configuration file. This file specifies the
name of the file to be loaded, the ROM device, the
address splitting mode, the HEX file format and whether
the serial or parallel port is to be used for loading the
data.
The PG-1500 package includes the following:
• PG-1500 EPROM Programmer Base Unit
• 027A Socket Board for 27XXX EPROMS and
~PD27C256A-like devices
• 04A Interface Board for NEC ~PD75XX/~PD75XXX
Microcomputers
• PG-1500 Controller Program Disk for IBM PC
•
•
•
•
•
Power Cord
Power Ground Plug Adapter
Spare Fuses (2)
PG-1500 EPROM Programmer User's Manuals
Warranty Policy and Registration Card
Basic Specifications
• Power requirements:
- 90 to 250 VAC, 50 to 60 Hz
• Environment conditions:
- Operating temperature range: 10 to 35°C
- Operating humidity range: 20 to 80% relative
humidity
• RS-232C serial port:
- Baud rates: 1200,2400,4800,9600, 19200
- Parity: none, even, odd
- X-ON/X-OFF: on, off
- Bit configuration: 7, 8
- Stop bits: 1, 2
Documentation
For further information on the operation of the PG-1500,
NEC provides the following documentation:
• PG-1500 EPROM Programmer User's Manual
• PG-1500 Controller Program User's Manual
(IBM PC Based)
In auto mode, the controller program reads in the configuration file, configures itself accordingly, checks the
9-109
II
PG·1500 Series
9-110
fttlEC
Package Drawings
10-1
lID
NEe
Package Drawings
Section 10
Package Drawings
Package/Device Cross-Reference
10-3
54-Pin Ceramic LCC (w/Window)
10-20
2O-Pin Plastic Shrink DIP
10-5
54-Pin Ceramic Piggyback Shrink DIP
10-21
2O-Pin Plastic SOP
10-5
54-Pin Ceramic Piggyback QUIP
10-22
24-Pin Plastic Shrink DIP
10-6
54-Pin Ceramic Piggyback QFP
10-23
24-Pin Plastic SOP
10-6
54-Pin Plastic QFP (2.55 mm thick)
10-24
4O-Pin Plastic DIP
10-7
54-Pin Plastic QFP (1.5 mm thick)
10-25
40-Pin Plastic Shrink DIP
10-8
54-Pin Plastic QFP (2.7 mm thick)
10-26
10-9
54-Pin Plastic QFP (2.05 mm thick)
10-27
42-Pin Plastic DIP
10-10
54-Pin Ceramic QUIP (w/Window)
10-28
42-Pin Plastic Shrink DIP
10-10
54-Pin Plastic QUIP
10-29
42-Pin Ceramic Piggyback DIP
10-11
58-Pin PLCC
10-30
44-Pin Ceramic LCC (w/Window)
10-12
74-Pin Plastic QFP
10-31
44-Pin Plastic QFP
10-13
SO-Pin Ceramic LCC (w/Window)
10-32
44-Pin PLCC
10-14
80-Pin Plastic QFP (14 by 14 mm)
10-32
52-Pin Plastic QFP (1.8-mm leads)
10-15
SO-Pin Plastic QFP (20 by 14 mm;
1.8-mm leads)
10-33
80-Pin Plastic QFP (20 by 14 mm;
2.35-mm leads)
10-34
84-Pin PLCC
10-35
94-Pin Ceramic LCC (w/Window)
10-36
94-Pin Plastic QFP
10-37
40-Pin Ceramic Piggyback DIP
52-Pin Plastic QFP (3.5-mm leads)
10-16
54-Pin Shrink CERDIP (w/350-mil
window)
10-17
54-Pin Shrink CERDIP (w/300-mil
window)
10-18
54-Pin Plastic Shrink DIP
10-19
10-2
ttiEC
Package Drawings
Package/Device Cross Reference
Package
Device, "PO
Package
Device, "PO
20-Pin Plastic Shrink DIP
7554CS
7554ACS
75P54CS
7564CS
7564ACS
75P64CS
44-Pin PLCC
71 P301 L
52-Pin Plastic QFP
(l.B-mm leads)
7507GC
750BGC
52-Pin Plastic QFP
(3.5-mm leads)
7225G
64-Pin Shrink CERDIP
(w/350-mll window)
75Pl08DW
7BCP14DW
7BP312ADW
64-Pin Shrink CERDIP
(w/300-mll window)
7BP214DW
64-Pin Plastic Shrink DIP
7502BCW
75P036CW
75048CW
75P056CW
751xxCW
75P108CW
75Pl08BCW
75P116CW
75208CW
7520BCW
75212ACW
75216ACW
75P216ACW
75268CW
64-Pin Ceramic LCC
(w/window)
71 P301KB
64-Pin Ceramic
Piggyback Shrink DIP
75CG208E
75CG216AE
64-Pin Ceramic
Piggyback QUIP
78CG14E
64-Pin Ceramic
Piggyback QFP
75CG208EA
75CG216AEA
64-Pin Plastic QFP
(2.55 mm thick)
75028GC
75P036GC
7504BGC
75P056GC
75104AGC
751 OBAG C
78C14AG
2O-Pin Plastic SOP
7554G
7554AG
75P54G
7564G
7564AG
75P64G
24-Pin Plastic Shrink DIP
7556CS
7556ACS
75P56CS
7566CS
7566ACS
75P66CS
24-Pin Plastic SOP (300
miQ
7556G
7556AG
75P56G
7566G
7566AG
75P66G
40-Pin Plastic DIP
7507C
7507HC
7508C
7508HC
40-Pin Plastic Shrink DIP
7507CU
7507HCU
7508CU
7508HCU
40-Pin Ceramic
Piggyback DIP
75CG08E
75CG08HE
42-Pin Plastic DIP
7527AC
7528AC
7533C
7537AC
7538AC
42-Pin Plastic Shrink DIP
7527ACU
7528ACU
7533CU
7537ACU
7538ACU
64-Pin Plastic QFP
(1.5 mm thick)
7510BAG
64-Pin Plastic QFP
71 P301GF
IOUUX\...IU
\.::::.t
Ivv'::::IIr.lr
75POO8CU
42-Pin Ceramic
Piggyback DIP
75CG28E
75CG33E
75CG38E
44-Pin Ceramic LCC
(w/window)
71P301KA
44-Pin Plastic QFP
7507HGB
7508HGB
7500xGB
75P008GB
7533G
mm mICK)
7503GF
751xxGF
75P108BGF
75P116GF
75206GF
7520BGF
75212AGF
75216AGF
75268GF
7BC10CW
78C10ACW
78C11CW
78C11ACW
78Cl2ACW
78C14CW
78CP14CW
78213CW
78214CW
78P214CW
78310ACW
78312ACW
78P312ACW
III
78Cl0GF
---.---78Cl1GF
78Cl1AGF
78Cl2AGF
78C14GF
78CP14GF
78310AGF
78312AGF
78P312AGF
10-3
NEe
Package Drawings
PackagelDevlce Cross Reference (cont)
Package
Devlce,,,PD
Package
Device, "PD
54-Pin Plastic QFP
(2.05 mm thick)
,7227G
75104G
75106G
75108G
75P108G
75206G
75208G
78C1oo-1B
78C11G-1B
78C14G-1B
ao-Pln Ceramic LCC
(w/WlndOw)
75P308K
75P316AK
ao-Pin Plastic QFP
(14 by 14 mm)
75328GC
75P328GC
78233GC
78234GC
78P238GC
80 -Pin Plastic QFP
(20 by 14 mm; 1.8-mm
leads)
753xxGF
75P308GF
75P316GF
75P316AGF
ao-Pin Plastic QFP
(20 by 14 mm; 2.35-mm
leads)
7228G
7228AG
54-Pin Plastic PLCC
78220L
78224L
78P224L
78233LQ
78234LQ
78P238LQ
94-Pin Ceramic LCC
(w/Wlndow)
78P238KF
54-Pin Ceramic QUIP
(w/WlndOw)
54-Pin Plastic QUIP
68-Pln PLCC
74-Pi n Plast Ie QFP
10-4
71 P301 RQ
78CP14R
78P214R
78P312AR
71P301GQ
78C10G-36
78C10AGQ..36
78C11G-36
78C11AGQ-36
78Cl2AG-36
78C14G-36
18CP14G-36
, 78C10L
78C10AL
78C11L
78C11AL
78Cl2AL
78C14L
78CP14L
78213L
78214L
78P214L
78213GJ
78214GJ
78P214GJ
78320GJ
78322GJ
78213GQ
78214GQ
78P214GQ
78310AGQ
78312AGQ
78P312AGQ
78310AL
78312AL
78P312AL
78320L
78322L
94-Pln Plastic QFP
78220GJ
78224GJ
78P224GJ
78233GJ
,78234GJ
78P238GJ
NEe
Package Drawings
20-Pin Plastic Shrink DIP
Item
Millimeters
A
.771 max
B
19.57 max
1.78 max
Inches
C
1.778 (TP)
.070 (TP)
D
O.SO ±0.10
.020
F
0.85 min
.033 min
G
3.2 ±0.3
.126 ±.012
H
0.51 min
.020 min
I
4.31 max
J
5.08 max
.170 max
.200 max
K'
.070 max
~:gg~
7.62 (TP)
.300 (TP)
L
6.5
.256
M
0.25
N
0.17
~g:6~
11
20
.010
~:gg~
.007
• Item K to center of leads
when formed parallel.
sl.....
I-
o
N ...,,®=<.JMI
..."f$J"-L.:..:..
49NR·sg36 (9/89)
P20C-70·300B
20-Pin Plastic SOP
Item
Millimeters
A
.512 max
B
13.00 max
0.78 max
C
1.27 (TP)
.050 (TP)
D
0.40
E
F
0.1 ±0.1
1.8 max
.004 ±.004
.071 max
G
1.55
.061
H
7.7 ±0.3
.303 ±.012
.220
~g:6g
5.6
1.1
Inches
.031 max
.016
~:gg~
K
0.20
.008
~ :gg~
L
0.6 ±0.2
.024
~:gg:
M
0.12
.005
P20GM·50-300B, C
11
E
I;
1~1
A
.043
~g:6~
20
,-rr!;~
o
f$J
M
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49NA-594B (Q/S9)
10-5
NEG
Package Dr.wlngs
24-Pin Plllstic Shrink DIP
Ilem
Millimeters
A
C
23.12 max
1.78 max
1.778 (TP)
D
0.50 ±0.10
a
F
G
H
0.85 min
3.2 ±0.3
0.51 min
4.31 maX
5.08 max
. 7.62 (TP)
6.5
J
K·
L
N
0.17
".
Inches
.911 max
.070 max
.070 (TP)
.033
.126
.020
.170
.200
.300
.256
min
±.012
min
max
max
(TP)
24
'"',
13
~ UUUu:-: uuuu:
.1
A
.007
• Item K to cent.... of leads
when formed parallel.
[£] f$l
N
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S24C>7o.300S
49NR-596B (9189)
24-Pin Plllstic SOP (300 mil)
Ilem
Millimeters
A
C
15.54 max
0.78 max
1.27 (TP)
D
0.40
E
0.1 ±0.1
F
G
H
I
1.8 max
a
1.55
7.7 ±0.3
5.6
1.1
~g:Jg
.016
~:gg~
.004 ±.004
.071 max
.061
.303 ± .012
.220
.043
K
0.20
.008
~:gg~
L
0.6 ±0.2
.024
~:gg;
M
0.12
.005
P24GM-SO·3008
10-6
~g:rig
Inches
24
13
.612 max
.031 max
.050 (TP)
110 :
: : : :-: : : : :
,:,1
A
.~I~J
[£] f$l
M
@i
49NR·5958 (9189)
NEe
Package Drawings
4D-Pin Plastic DIP
Item
Millimeters
Inches
A
B
C
53.34 max
2.100 max
15.24 [TP]
.600 [TP[
13.2
.520
D
5.72 max
.225 max
E
F
4.31 max
.170 max
3.6±O.3
.142±.012
G
2.54 max
.100 max
H
2.54 [TP]
1.2mln
.100 [TP]
.047 min
J
0.51 min
.020 min
K
0.50 ±O.10
.02O±.004
L
0.25
M
0.25
I
~:6~
.010
~:~~~
40
~;
21
: : : : : : : : :-: : : : : : : : : ; .1
A
.010
ffi,~
'""tl
~L
.-It-'
P4OC·1()o"600A
83vQ.6140B (6189)
10-7
NEe
Package Drawings
4O-Pin Plastic Shrink DIP
Item
Millimeters
A
B
C
39.13 max
2.67 max
.106 max
1.778 (TP)
.070 (TP)
D
0.50 ±0.10
.020
F
0.9 min
.035 min
G
3.2 ±0.3
.126 ±.012
H
0.51 min
.020 min
Inches
1.541 max
~ :gg~
4.31 max
.170 max
5.08 max
.200 max
15.24 (TP)
.600 (TP)
L
13.2
.520
M
0.25
N
0.17
K"
~g:~~
.010
21
40
~:gg~
I.
.007
20
.1
A
" Item K to center of leads
when formed parallel.
0
L
/
_LL
,~!~IH H
H
H
M
P4OC-70..aOOA
10-8
\-
0-15'
......
o
f$J
N
®I
49NR-544B (7189)
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Package Drawings
4O-Pin Ceramic Piggyback DIP
Item
A
C
M
2.54 max
Inches
2.100 max
.800 ± .016
.100
.036 min
.018 ±.002
.010
.100 (TP)
.100 max
N
0.25 ±0.05
.010
Q
15.24
7.28 max
1.0 min
3.5,±0.3
3.0 max
.600
.287
.039
.138
.118
F
G
H
Millimeters
53.34 max
20.32 ± 0.4
2.54
0.92 min
0.46 ±0.05
0.25
2.54 [P)
S
T
U
V
~:~~~
max
min
±.012
max
15
28
,-
00000000000000
~
-
./
c
00000000000000
1
14
'-
A
I
OJ I$l
P40E·100·'
I
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49NR·597a
1918911
10-9
NEe
Package .Drawings
42-Pln PI.stlc DIP
22
42
Item
Mllllmet.re
Inch.
A
B
C
SS.88 max
2.54 max
2.54[TP]
2.2 max
.100 max
0
0.50:t0.10
.02O~:~O:
F
G
H
1.2 min
3.6iC.30
0.51 min
4.31 max
5.72 max
15.24 (TP]
13.2
.047 min
.142:t.012
.020 min
.170 max
.226 max
.600 [TP]
.520
J
K
L
.100 [!Pl
M
O.25~~:ri~
.010 ~:gg:
N
0.25
.01
PoI2C-1OD-8OOA, S
42-Pln PI.stlc Shrink DIP
Item
Millimeters
Inches
A
B
C
39.13 max
1.78 max
1.778 (TP)
1.541 max
.070 max
.070 (TP)
0
0.50 :to.10
.020
F
G
H
L
0.9 min
3.2 :to.3
0.51 min
4.31 max
5.08 max
15.24 (TP)
13.2
.035
.126
.020
.170
.200
.600
.520
M
0.25
N
0.17
J
K"
:g:cig
.010
42
22
::gg~
min
:t.012
min
max
max
(TP)
::gg~
.007
" Item K to center of leads
when fonned parallel.
0
L
Iii
Nl!. l!~
..
.H .H .H .H .H
I-
IT]
10-10
.H.H
M1:
TI
g~,g~
~g
F
o
BI-
P42C-70-600A
J-\
1$1
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49NR-557B (7A19)
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Package Drawings
42-Pin Ceramic Piggyback DIP
Item
A
C
Millimeters
55.88 max
20.32 ±0.4
F
2.54
0.92 min
0.46 ±0.05
0.25
G
H
Inches
2.200 max
.800 ±.016
.100
.036 min
.018 ±.002
.010
M
2.54 (TP)
2.54 max
.100 (TP)
.100 max
N
0.25 ±0.05
.010
Q
.600
.287 max
~:gg~
S
15.24
7.28 max
T
U
1.0 min
.039 min
3.5 ±0.3
.138 ±.012
V
3.0 max
.118 max
-
15
28
00000000000000
~
c
-
1/
00000000000000
1
I.
14
~-
A
·1
V
m
s
u
I
P420·100·A
49NR·.... (9189)
I
10-11
NEe
Package Drawings
44-Pin Ceramic LCC (w/Window)
Ilem
Millimeters
A
8
C
16.51 ± 0.4
15.50
15.50
16.51 ±0.4
1.02
1.52
3.048 max
0.64 ±0.10
0.12
1.27 (TP)
D
E
F
G
H
I
J
K
L
P
Q
R
S
T
y
1.27 ±0.2
2.16 ±0.2
0.2 rad
1.02 cor
1.905
1.905
8.89 dia
0.51 cor
Inches
.650
.610
.610
.650
.040
.060
.120
.025
.005
.050
.050
.085
.008
.040
.075
.075
.350
.020
±.016
A
8
Ii-
±.016
C D
max
±.004
(TP)
±.008
±.008
rad
cor
dia
01$l
X44KW-SOA-1
10-12
I
®I
49NR-69BB (3190)
NEe
Package Drawings
44-Pin Plastic QFP
Item
Millimeter.
A
13.6 ±0.4
.535
~:g~~
B
10.0 ±0.2
.394
~
c
10.0 ±0.2
.394
~
~ :g~~
D
13.6 ±0.4
.535
F
1.0
.039
.039
:ggg
:ggg
G
1.0
H
0.35 ±0.10
.014
0.15
.006
.031 (TP)
0.8 (TP)
K
.071
~:ggg
0.8 ±0.2
.031
~:gg~
.006
~:gg~
~g:6~
0.15
N
P
0.15
2.7
0.1 ±0.1
Q
R
S
0.1 ±0.1
3.0 max
C D
~:gg~
1.8 ±0.2
M
A
Inche.
.006
f$l
I
@10
Enlarged detail of lead end
.106
.004 ±.004
.004 ±.004
.119 max
Q
P44GB-80-3B4·1
R
49NR-556B (1190)
10-13
NEe
Package Drawings
44-PinPLCC
Item
Millimeters
A
B
C
17.5 ±O.2
16.58
16.58
17.5 ±O.2
1.94 ±O.15
0.6
4.4 ±O.2
2.8 ±O.2
0.9 min
3.4
D
E
F
G
H
I
K
T
1.27 lIP)
0.40 ±O.10
0.12
15.50 ±O.2O
0.15
0.8 radius
U
0.20
M
N
P
Q
~:6~
Inches
.689 ±.008
.653
.653
.689 ±.008
.076 ±.006
.024
.173 ±.008
.110 ±.008
.035 min
.134
.050 (TP)
.016 ±.004
.005
.610 ±.008
.006
.031 radius
.008
44
C
D
U
F
~:gg~
G
T
P
P44L·5OA 1·1
10-14
3190 83YL-5804B
NEe
Package Drawings
52-Pin Plastic OFP (1.8-mm leads)
Item
Millimeters
Inches
A
17.6 ±0.4
.693 ±.016
8
14.0 ±0.2
.551
~ :gg~
c
14.0 ±0.2
.551
~ :gg~
D
.693 ± .016
.039
G
17.6 ±0.4
1.0
1.0
H
0.40 ±0.10
.016
0.20
1.0 (TP)
.039 (TP)
1.8 ±0.2
.071
~:gg~
0.8 ±0.2
.031
~ :gg~
.006
~:gg~
F
K
~g:6~
.039
C D
~:gg~
.008
M
0.15
N
0.15
.006
P
R
2.7
0.1 ±0.1
0.1 ±0.1
.106
.004 ± .004
.004 ± .004
S
3.0 max
.119 max
Q
A
f$l
@10
Enlarged detail of lead end
Q
P52GC-100-366
R
49NR-493B (5189)
10-15
NEe
Package Drawings
52-Pin Plastic QFP (3.5-mm leads)
Itam
Millimeters
Inches
A
21.0 ± 0.4
.827 ± .016
B
14.0 ±0.2
.551
~:gg~
C
14.0 ±0.2
.551
~:gg~
0
G
21.0 ± 0.4
1.0
1.0
.827 ±.016
.039
.039
H
0.40 ±0.10
.016
0.20
1.0 (TP)
.008
.039 (TP)
K
3.5 ±0.2
.138
~:gg~
L
2.2 ±0.2
.087
~:gg~
M
0.15
.006
~:gg~
N
0.15
F
~g:6~
~g:~
P
2.6
Q
0.1 ±0.1
A
~:gg~
-E:a:Et---+----jI=a===>_ C 0
F
.006
.102
~:gg~
.004 ±.004
I$l
I
@ID]
K
q::~nnlJ+
~
LW
Q
P52G-1GO-OO
10-16
49NR-5368
(6189)
NEe
Package Drawings
64-Pin Shrink CERDIP (w1350-mil window)
Item
Millimeters
Inches
A
58.68 max
2.310 max
B
1.78 max
.070 max
C
1.778 (TP)
.070 (TP)
D
0.46 ±0.05
.018 ± .002
F
G
H
0.8 min
.031 min
3.5 ±0.3
.138 ±.012
1.0 min
.039 min
3.0
.118
5.08 max
.200 max
K'
19.05 (TP)
.750 (TP)
18.8
.740
M
0.25 ± 0.05
.010
N
0.25
.010
S
8.89 dia
.350 dia
L
~ :~~~
_~_0_15°
... Item K to center of leads
when formed parallel.
64
33
~
t'\
V
I.
1
A
ICl
Iff)1
N (M)
I
I P640W.70.750A--
10-17
NEe
Package Drawings
64-Pin Shrink CERDIP (w1300-mil window)
Item
Millimeters
Inches
A
58.68 max
1.78 max
1.778 (TP)
0.46 ±0.05
0.8 min
3.5 ±0.3
1.0 min
3.0
5.08 max
19.05 (TP)
18.8
2.310 max
.070 max
.070 (TP)
.018 ±.002
.031 min
.138 ± .012
.039 min
.118
.200 max
.750 (TPJ
.740
M
0.25 ±0.05
.010
N
0.25
7.62 dia
.010
.300 dia
B
C
D
F
G
H
K'
S
~ :gg~
~_0_15°
* Item K to center of leads
when formed parallel.
33
64
(vl
1\
\+~ .-J
1"\
V
I.
.1
A
o
P64DW·70·7SOA1
10-18
32
1
f$l
N
@I
49NR-G91 B (2190)
NEe
Package Drawings
64-Pin Plastic Shrink DIP
33
64
~---------------------A----------------~----~
E
:IE
f$-I
nem
A
B
C
0
E
F
G
H
I
M
Millimeters
58.68 max
19.05 (TP)
17.0
5.08 max
4.31 max
3.2:tO.3
1.78 max
1.778 (TP)
0.9 min
0.51 min
0.50 :to.10
Inches
2.310 max
.750 (TP)
.669
.200 max
.170 max
.126 ±.012
.070 max
.070 (TP)
.035 min
.020 min
.02O±.004
L
O.25~:ci~
:010~:gg;
M
0.17
.007
K
@I
~--[[)----+I
o ~ 15°
83VL-5S60B (&89)
10-19
NEe
Package Drawings
64-Pin Ceramic LCC (w/Window)
lIem
A
B
C
D
E
F
G
H
K
Q
R
S
T
U
W
Millimeters
20.0 ±0.4
19.0
13.2
14.0 ±0.4
1.64
2.14
3.556 max
0.70 ± 0.10
0.1
1.0 (TP)
1.0 ±0.2
0.25 cor
1.0
1.0
3.0 rad
12.0
0.8 ±0.2
A
Inches
.787 ±.016
.748
.520
.550 ±.016
.065
.084
.140 max
.028 ±.004
.004
.039 (TP)
.039 ±.008
.010 cor
.039
.039
.118 rad
.472
.031 ±.008
B
i'
U
I'
.,1
·i
n
I
'\
1/
+
~
il
0
w
Q
1
1
It
64
+
1
s
R~ lLl-
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H-I~
I
K-
1-
@I
49NR·699B (5190)
10-20
NEe
Package Drawings
64-Pin Ceramic Piggyback Shrink DIP
Item
M1111meters
Inches
A
58.68 max
22.86 ±0.4
2.310 max
.900 ±.016
2.54
0.80 min
0.46 ±0.05
.100
.031 min
.018 ±.002
.007
.070 (TP)
M
0.17
1.778 (TP)
1.78 max
N
0.25 ±0.05
.010
Q
5
15.24
8.28 max
.600
.326 max
T
U
1.0 min
3.5 ±0.3
.039 min
V
3.9 max
.154 max
W
19.05
.750
C
F
G
H
I
.070 max
~:gg~
.138 ±.012
,28
15
00000000000000
~
c
-
f'"
00000000000000
1
I.
14
A
.iV
~________~~~~~~w-~~~~~~~~~________~-1
I
P64E·70-A
5
I
MI~I
0f$J
I
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.9N ...71.
",.J
10-21
Package Drawings
64-Pin Ceramic Piggyback QUIP
Item
Millimeters
Inches
A
41.91 max
26.67 ± 0.4
2.54
0.92 min
0.46 ±0.05
0.25
2.54 (TP)
1.27 (TP)
1.27 max
1.650 max
1.050 ±.016
.100
.036 min
.018 ± .002
.010
.100 (TP)
.050 (TP)
.050 max
N
0.25 ±0.05
.010
Q
15.24
8.54 max
1.0 min
3.5 ±0.3
4.41 max
24.13
19.05
.600
.336
.039
.138
.174
.950
.750
C
G
H
K
M
S
T
U
V
W
X
[§]
10-22
~
15
00000000000000
------~--~-----------1rC
~ :gg~
max
min
± .012
00000000000000
14
max
~I'--------------------A--------------------~.I
NEe
Package Drawings
64-Pin Ceramic Piggyback QFP
Itam
Mllllmata..
Inch. .
u
~:g~
A
24.7 ±0.5
.972
B
C
0
E
F
G
20.3
16.3
18.7 ±0.5
1.27 (TP)
2.15
1.15
.799
.642
.736 ±.02O
.050 (TP)
.085
.045
H
.40 ±0.10
.016
J
0.20
1.0 (TP)
.OOB
.039 (TP)
K
1.2 ±0.2
.047
L
2.2 ±0.2
087+ .OOB
•
-.009
M
0.15
.006
N
0.15 ±0.05
.006
S
T
9.5 max
3.0 max
.374 max
.11B max
U
2.2 ±0.2
.OB7
V
3.2 ±0.2
.126 ±.OOB
~:gg~
~:gg:
~:gg~
~:ggg
F
End View
P64EA-100..A,
..NR-612B (2190)
10-23
NEe
Package:Drawlngs
64-Pin Plastic QFP {2.55 mm thiclr}
Hem
A
MIllimeters
17.6 :1:0.4
Inch ..
.693 ':1:.016
B
14.0 :1:0.2
.551
~:gg:
C
14.0 :1:0.2
.551
~:gg:
0
F
G
17.6 :1:0.4
1.0
1.0
.693 :1:.016
.039
.039
H
0.35 :1:0.10
.014
K
0.15
0.8 (TP)
1.8 :1:0.2
.006
.031 (TP)
.071 :1:.008
.031
~:gg:
.006
~:gg;
L
0.8 :1:0.2
M
0.15
N
0.15
2.55
0.1:1:0.1
0.1 :1:0.1
2.85 max
P
Q
R
S
~g:Jg
A
C 0
~:gg~
.006
.100
.004. :1:.004
.004 :1:.004
.112 max
@I
I
®10
Enlarged detail of lead end
4
Q
R
"'R-6698 (1190)
NEe
Package Drawings
64-Pin Plastic QFP (1.5 mm thick)
Item
Millimeters
A
18.4 ±0.4
.724
~:g1~
B
14.0 ±0.2
.551
~:gg~
c
14.0 ±0.2
.551
~:gg~
0
18,4 ±0,4
.724
~:g1~
F
G
1.0
1.0
.039
.039
H
0.35 ±0.10
.014
0.15
0.8 (TP)
.006
.031 (TP)
C 0
2.2 ±0.2
.087
~:gg:
L
1.0 ±0.2
.039
~:gg~
M
0.15
.006
~:gg~
N
P
0.15
1.5 ±0.1
0.0 ±0.1
1.7 max
Q
S
B
~:gg~
K
~g:cig
A
Inches
.006
.059 ±.004
.000 ±.004
.067 max
f$l
I
@10
K
Aoooonoo*onooonoJ:]
~
~ LJD
Enlarged detail of lead end
M
49NR-S70B (1/90)
m
10·25
ttiEC
Package Drawings
64-Pin Plastic QFP (2.7 mm thick)
item
Millimeters
A
23.6 to.4
Inches
.929 t.016
B
20.0 to.2
.795
~ :gg~
c
14.0 to.2
.551
~:gg~
0
17.6 to.4
.693 t .016
F
G
1.0
1.0
.039
.039
H
0.40 to.l0
.016
0.20
.008
.039 (TP)
K
1.8 to.2
.071
~
L
0.8 to.2
.031
~ :gg~
M
0.15
.006
~:ggj
N
P
0.15
.006
2.7
0.1 to.l
.106
Q
R
0.1 ±0.1
S
3.0 max
C 0
~:gg~
1.0 (TP)
~g:6~
A
:ggg
.004 ± .004
.004 ± .004
.119 max
f$J
I
@ID]
Enlarged detail of lead end
Q
PS4GF-100-3B8,3BE-'
10-26
R
49NR-5998 (2t90)
NEe
Package Drawings
64-Pin Plastic QFP (2.05 mm thick)
Item
Millimeters
Inches
A
24.7 ± 0.4
.972
~ :g~~
B
20.0 ± 0.2
.795
~ :gg~
c
t4.0 ±0.2
.55t
~ :gg~
D
t8.7 ± 0.4
.736 ±.016
F
1.0
1.0
.039
G
H
0.40 ±0.10
.016
0.20
1.0 (TP)
.008
K
2.35 ±0.2
.093
~ :gg~
L
1.2 ±0.2
.047
~:gg~
M
0.15
.006
~:gg~
N
0.15
P
2.05
Q
0.1 ±0.1
.004 ± .004
s
2.45 max
.096 max
A
.039
~g:6~
.039 (TP)
.006
~ g:~
C D
~ :gg~
.081
~:gg~
f$J
I
@10
Enlarged detail of lead end
Q
P64G-tOO·12,19-1
49NR-5438 (2190)
m
10-27
NEe
Package Drawings
64-Pin Cerllmic QUIP (w/Window)
Item
MIllimeters
Inches
A
C
41.91 max
26.67 ±0.4
1.650 max
1.050 ± .016
G
0.92 min
.036 min
H
J
0.46 ±0.05
0.25
2.54 (TP)
.018 ±.002
.010
.100 (TP)
K
1.27 (TP)
.050 (TP)
M
1.27 max
.050 max
N
0.25 ±0.05
.010
S
T
4.72 max
1.0 min
.186 max
U
3.5 ±0.3
.138
W
X
Y
24.13
.950
19.05
8.89 dia
.750
.350 dia
I
~------~-------------+-c
=:gg~
.039 min
=:g~~
I.
~ ~
I-l=N
E
P64EW·tOO·A
10-28
A
.1
1
P
:r1
X
-2l
W
49NR..s10B
15.09)
NEe
Package Drawings
64-Pin PI.stic QUIP
Item
Millimeters
~g:~
Inches
~:g6~
A
41.5
c
16.5
.650
H
0.50 ±0.10
.020
J
K
0.25
2.54 (TP)
1.27 (TP)
.010
.100 (TP)
.050 (TP)
M
1.1
N
0.25
P
4.0 ±0.3
s
w
X
1.634
.043
~:g6~
.010
~:gg~
.157
~:gg
3.6 ±0.1
.142
~:gg~
24.13 ± 1.05
19.05 ± 1.05
.950 ±.042
.750 ±.042
~g:~~
~g:6g
1
-----+J
~:gg~
I.
.1
A
w
1$1
P64GQ-100·36
I
®10
49NR·508B
(4/69)
m
10-29
t\fEC
package Drawings
68-PinPLCC
A
lIem
Millimeters
A
B
C
0
25.2±O.2
.992±.00S
24.20
.953
24.20
.953
25.2±O2
.992±.OOS
E
1.94±O.15
.076~:g~
F
0.6
.024
G
4.4±O.2
.173~:gg:
H
2.8±O2
.110~:gg:
0.9 min
.035 min
K
Ii-
Inches
3.4
.134
1.27 lIP)
.050 lIP)
M
0.40 ±O.10
.016 ~:gg~
N
0.12
.005
P
23.12±O.2O
.910 ~:gg:
Q
0.15
.006
T
O.Sradlus
.031 radius
U
O·2Q~:ci~
.006 ~:gg:
CJCJCJCJCJCJCJCJ
66
c
0
F
G
(:?J90)
P68L-5OA1-1
10-30
83YL-5561B
NEe
Package Drawings
74-Pin Plastic QFP
Inches
Item
Millimeters
A
23.2 ± 0.4
.913
~ :g~~
B
20.0 ±0.2
.787
~ :gg~
c
20.0 ±0.2
.787
~ :gg~
D
23.2 ± 0.4
.913
~ :g~~
2.0
1.0
2.0
1.0
.079
.039
.079
.039
H
0.40 ±0.10
.016
K
0.20
1.0 (TP)
1.6 ±0.2
.008
.039 (TP)
.063 ±.O02
L
0.8 ±0.2
.031
~:gg~
M
0.15
.006
~:gg~
N
P
0.15
3.7
0.1 ±0.1
0.1 ±0.1
4.0 max
Fl
F2
Gl
G2
Q
R
S
~g:~~
F2
C D
~:gg~
.006
.146
.004 ± .004
.004 ± .004
.158 max
f$l
®10
Enlarged detail of lead end
4
Q
S74G.1·100·5SJ·1
R
49NR-3478 (2190)
m
10-31
NEe
Package Drawings
SO-Pin Ceramic LeC (w/wlndow)
Item
Millimeters
A
20.0 ±0.4
.787
B
C
0
E
F
19.0
13.2
14.2 ±0.4
1.64
2.14
4.064 max
0.51 ±0.10
0.08
0.8 (TP)
.748
.520
.559
.065
.084
.160
.020
.003
.031
K
1.0 ±0.2
.039
Q
0.5 cor
.020 cor
R
S
T
U
0.8
1.1
3.0 rad
12.0
.031
.043
.118 rad
.472
W
0.75 ±0.2
.030
G
H
Inches
A
~:gl~
±.016
B
I'
u
ill
"
mex
±.004
/
~
(TP)
~:gg~
~:ggg
+
'\
'I
W
Q
v".,..".".".."nnnn"""""'".".".."nnnr"".,....,.J
1
CD
ill
K-I
I:hnnnnnnnnnnnnnnnnnnnnnnffiii.}
I
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X80KW-80A
49NR·617B (11/89)
SO-Pin Plastic QFP (14 by 14 mm)
Item
A
Inches
.677 ±.016
B
14.0 ±0.2
.551
~:gg~
C
14.0 ±0.2
.551
~:gg~
0
F
G
17.2 ±0.4
0.8
0.8
.6n
±.016
H
0.30 ±0.10
.012
J
K
0.13
0.65 (TP)
1.6 ±0.2
.005
.026 (TP)
.063 ±.008
L
0.8 ±0.2
.031
~:gg~
M
01"5 + 0.10
. -0.05
0.15
2.7
0.1 ±0.1
0.1 ±0.1
3.0 max
.006
~:gg:
N
P
Q
R
S
S80GC·65-3B9·1
10-32
Millimeters
17.2 ±0.4
.031
.031
~:gg~
.006
.106
.004 ±.004
.004 ±.004
.119 max
---+---
I$l
I
C 0
®10
Enlarged detail of lead end
K
Annnruuuuu~uuuuuuum~--.i
4eill
LJ[l
M
~
Q
R
49NR·591 B (2t'90)
NEe
Package Drawings
SO-Pin Plastic QFP (20 by 14 mm; I.B-mm leads)
Item
Millimeters
Inches
A
23.6±C.4
B
2O.0±C.2
.929±.016
+.009
.71I1 -.008
C
14.0±C.2
.551 +.009
-.008
D
17.6±C.4
1.0
0.8
.693±.016
.039
.031
H
0.35±C.10
.014
J
0.15
0.8 (TP)
K
1.8±C.2
.006
.031 (TP)
+.009
.071 -.008
L
0.8±C.2
.031
F
G
~:~~
M
0.15
N
P
0.15
2.7
0.1 ±C.1
0.1 ±C.1
3.0 max
Q
R
S
..
~:~~
C
D
~:~:
006 +.004
.
-.002
.006
.106
.004±.004
.004±.004
.118 max
G
H
@j1@lw
Pin Detail
,1,1: ~
Q
P8OGF-eo-aB9-1
R
831H·5S43B
(2190)
10-33
NEe
Package Drawings
SO-Pin Plastic QFP (20 by 14 mmj 2.35-mm leads)
Item
A
24.7±O.4
Inches
.972±.016
B
2O.0±O.2
767 +.009
.
-.OOS
C
14.0±O.2
.551 +.009
-.OOS
D
F
G
1S.7±O.4
.736±.016
1.0
.039
O.S
.031
H
0.35±O.10
.014
0.15
.006
O.S (TP)
.031 (TP)
+.009
.093 -.OOS
K
2.35±O.2
L
1.2±O.2
M
0.15
N
0.15
~:6g
~:~
P
2.05
R
0.1 ±O.1
P80G-80-t2
10-34
MillImeters
~:gg~
A
B
•
I
~-+--~
C
D
.047 +.009
-.OOS
006 +.004
•
-.002
.006
.OS1
~::!
.004±.004
G
H
83SL-6222B
(6189)
NEe
Package Drawings
B4-PinPLCC
r ====:====-==::
i
I" i
nnnonnnnnn
lIem
Millimeters
Inche.
Q
0.6
4.4 ±C.2
2.8 ±C.2
0.9 min
3.4
1.27 ITP)
0.40 ±C.10
0.12
28.20 ±C.2O
0.15
1.189 ±.008
1.153
1.153
1.189 ±.008
.076 ±.006
.024
.173 ±.008
.110 ±.008
.035 min
.134
.050 (TP)
.016 ±.004
.005
1.110 ±.OOS
.008
T
O.S radius
.031 radius
A
30.2 ±C.2
B
C
D
29.28
29.28
30.2 ±C.2
. 1.94 ±C.15
E
F
G
H
J
K
M
N
P
u
.008
84
----------'---f3--C
D
:.~~~
F
G
T
~----~----------P----------------~
P84L-50A3-t
(2/!10)
83VL-58068
10-35
tt1EC
Package Drawings
94-Pin Ceramic LeC (w/lllfindow)
Item
Millimeters
Inches
A
B
C
20.0 ±0.4
18.0
18.0
.787 ±.017
.709
.709
0
20.0 ±0.4
1.94
2.14
4.064 max
0.51 ± 0.10
0.08
0.8 (TP)
.787 ± .017
.076
.064
.160 max
.020 ±.004
1.0 ±0.2
0.3 ccr
1.6
1.6
1.75 rad
.039 ±.OO8
.012 cor
.063
.063
.069 rad
11.5
0.75 ±0.2
1.0 ccr
.453
.030 ±.OO8
.039 ccr
E
F
G
H
J
K
Q
R
S
T
U
W
Y
A
\'1'
B
III!
u
. 'I
1---,
T~
.003
.031 (TP)
..:U
C
o
-
1:loooooooonnrmmnmrm~[IE IF IG
w
s
-F*-----
X94KW-80A
10-36
+ ------l=-I-
49NR·704B (3190)
NEe
Package Drawings
94-Pin Plastic aFP
Item
Millimeters
Inches
A
23.2 ±O.4
.913 +.017
-.016
B
20.0 ±O.2
.787 +.009
-.008
C
20.0 ±O.2
.787 +.009
-.008
D
23.2 ±O.4
.913 +.017
-.016
Fl
1.6
.063
F2
G1
G2
0.8
1.6
.031
.063
0.8
.031
H
0.35 ±O.10
+.004
.014 -.005
0.15
.006
J
K
0.8 (TP)
1.6 ±O.2
.031 (TP)
.063 ±.008
L
0.8 ±O.2
.031
M
0.15
N
P
~:ri~
0.15
F2
C D
+.009
-.008
+.004
.006 -.003
.006
.146
Q
3.7
0.1 ±O.l
R
0.1 ±O.l
.004 ±.004
S
4.0 max
.158 max
.004 ±.O04
Detail of lead end
Il
R
P
S
Q
$94GJ-8Q-5BG-1
10-37
Package Drawings
10-38
fttIEC
NEe Electronics Inc.
CORPORATE HEADQUARTERS
401 Ellis Street
PO. Box 7241
Mountain View, CA 94039
TEL 415-960 -6000
TLX 3715792
For literature, call toll-free 8 a.m. 10 4 p.m. Pacific time:
1-800-632-3531
50053
<> '990 NEG Electronics Inc .lPrinled in U.S.A .
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